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Akimeite/AndroidModule
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uvccamera/src/main/jni/libjpeg-turbo-1.5.0/simd/jsimd_arm_neon.S
|
/*
* ARMv7 NEON optimizations for libjpeg-turbo
*
* Copyright (C) 2009-2011, Nokia Corporation and/or its subsidiary(-ies).
* All Rights Reserved.
* Author: Siarhei Siamashka <siarhei.siamashka@nokia.com>
* Copyright (C) 2014, Siarhei Siamashka. All Rights Reserved.
* Copyright (C) 2014, Linaro Limited. All Rights Reserved.
* Copyright (C) 2015, D. R. Commander. All Rights Reserved.
* Copyright (C) 2015-2016, Matthieu Darbois. All Rights Reserved.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack, "", %progbits /* mark stack as non-executable */
#endif
.text
.fpu neon
.arch armv7a
.object_arch armv4
.arm
.syntax unified
#define RESPECT_STRICT_ALIGNMENT 1
/*****************************************************************************/
/* Supplementary macro for setting function attributes */
.macro asm_function fname
#ifdef __APPLE__
.globl _\fname
_\fname:
#else
.global \fname
#ifdef __ELF__
.hidden \fname
.type \fname, %function
#endif
\fname:
#endif
.endm
/* Transpose a block of 4x4 coefficients in four 64-bit registers */
.macro transpose_4x4 x0, x1, x2, x3
vtrn.16 \x0, \x1
vtrn.16 \x2, \x3
vtrn.32 \x0, \x2
vtrn.32 \x1, \x3
.endm
#define CENTERJSAMPLE 128
/*****************************************************************************/
/*
* Perform dequantization and inverse DCT on one block of coefficients.
*
* GLOBAL(void)
* jsimd_idct_islow_neon (void *dct_table, JCOEFPTR coef_block,
* JSAMPARRAY output_buf, JDIMENSION output_col)
*/
#define FIX_0_298631336 (2446)
#define FIX_0_390180644 (3196)
#define FIX_0_541196100 (4433)
#define FIX_0_765366865 (6270)
#define FIX_0_899976223 (7373)
#define FIX_1_175875602 (9633)
#define FIX_1_501321110 (12299)
#define FIX_1_847759065 (15137)
#define FIX_1_961570560 (16069)
#define FIX_2_053119869 (16819)
#define FIX_2_562915447 (20995)
#define FIX_3_072711026 (25172)
#define FIX_1_175875602_MINUS_1_961570560 (FIX_1_175875602 - FIX_1_961570560)
#define FIX_1_175875602_MINUS_0_390180644 (FIX_1_175875602 - FIX_0_390180644)
#define FIX_0_541196100_MINUS_1_847759065 (FIX_0_541196100 - FIX_1_847759065)
#define FIX_3_072711026_MINUS_2_562915447 (FIX_3_072711026 - FIX_2_562915447)
#define FIX_0_298631336_MINUS_0_899976223 (FIX_0_298631336 - FIX_0_899976223)
#define FIX_1_501321110_MINUS_0_899976223 (FIX_1_501321110 - FIX_0_899976223)
#define FIX_2_053119869_MINUS_2_562915447 (FIX_2_053119869 - FIX_2_562915447)
#define FIX_0_541196100_PLUS_0_765366865 (FIX_0_541196100 + FIX_0_765366865)
/*
* Reference SIMD-friendly 1-D ISLOW iDCT C implementation.
* Uses some ideas from the comments in 'simd/jiss2int-64.asm'
*/
#define REF_1D_IDCT(xrow0, xrow1, xrow2, xrow3, xrow4, xrow5, xrow6, xrow7) \
{ \
DCTELEM row0, row1, row2, row3, row4, row5, row6, row7; \
JLONG q1, q2, q3, q4, q5, q6, q7; \
JLONG tmp11_plus_tmp2, tmp11_minus_tmp2; \
\
/* 1-D iDCT input data */ \
row0 = xrow0; \
row1 = xrow1; \
row2 = xrow2; \
row3 = xrow3; \
row4 = xrow4; \
row5 = xrow5; \
row6 = xrow6; \
row7 = xrow7; \
\
q5 = row7 + row3; \
q4 = row5 + row1; \
q6 = MULTIPLY(q5, FIX_1_175875602_MINUS_1_961570560) + \
MULTIPLY(q4, FIX_1_175875602); \
q7 = MULTIPLY(q5, FIX_1_175875602) + \
MULTIPLY(q4, FIX_1_175875602_MINUS_0_390180644); \
q2 = MULTIPLY(row2, FIX_0_541196100) + \
MULTIPLY(row6, FIX_0_541196100_MINUS_1_847759065); \
q4 = q6; \
q3 = ((JLONG) row0 - (JLONG) row4) << 13; \
q6 += MULTIPLY(row5, -FIX_2_562915447) + \
MULTIPLY(row3, FIX_3_072711026_MINUS_2_562915447); \
/* now we can use q1 (reloadable constants have been used up) */ \
q1 = q3 + q2; \
q4 += MULTIPLY(row7, FIX_0_298631336_MINUS_0_899976223) + \
MULTIPLY(row1, -FIX_0_899976223); \
q5 = q7; \
q1 = q1 + q6; \
q7 += MULTIPLY(row7, -FIX_0_899976223) + \
MULTIPLY(row1, FIX_1_501321110_MINUS_0_899976223); \
\
/* (tmp11 + tmp2) has been calculated (out_row1 before descale) */ \
tmp11_plus_tmp2 = q1; \
row1 = 0; \
\
q1 = q1 - q6; \
q5 += MULTIPLY(row5, FIX_2_053119869_MINUS_2_562915447) + \
MULTIPLY(row3, -FIX_2_562915447); \
q1 = q1 - q6; \
q6 = MULTIPLY(row2, FIX_0_541196100_PLUS_0_765366865) + \
MULTIPLY(row6, FIX_0_541196100); \
q3 = q3 - q2; \
\
/* (tmp11 - tmp2) has been calculated (out_row6 before descale) */ \
tmp11_minus_tmp2 = q1; \
\
q1 = ((JLONG) row0 + (JLONG) row4) << 13; \
q2 = q1 + q6; \
q1 = q1 - q6; \
\
/* pick up the results */ \
tmp0 = q4; \
tmp1 = q5; \
tmp2 = (tmp11_plus_tmp2 - tmp11_minus_tmp2) / 2; \
tmp3 = q7; \
tmp10 = q2; \
tmp11 = (tmp11_plus_tmp2 + tmp11_minus_tmp2) / 2; \
tmp12 = q3; \
tmp13 = q1; \
}
#define XFIX_0_899976223 d0[0]
#define XFIX_0_541196100 d0[1]
#define XFIX_2_562915447 d0[2]
#define XFIX_0_298631336_MINUS_0_899976223 d0[3]
#define XFIX_1_501321110_MINUS_0_899976223 d1[0]
#define XFIX_2_053119869_MINUS_2_562915447 d1[1]
#define XFIX_0_541196100_PLUS_0_765366865 d1[2]
#define XFIX_1_175875602 d1[3]
#define XFIX_1_175875602_MINUS_0_390180644 d2[0]
#define XFIX_0_541196100_MINUS_1_847759065 d2[1]
#define XFIX_3_072711026_MINUS_2_562915447 d2[2]
#define XFIX_1_175875602_MINUS_1_961570560 d2[3]
.balign 16
jsimd_idct_islow_neon_consts:
.short FIX_0_899976223 /* d0[0] */
.short FIX_0_541196100 /* d0[1] */
.short FIX_2_562915447 /* d0[2] */
.short FIX_0_298631336_MINUS_0_899976223 /* d0[3] */
.short FIX_1_501321110_MINUS_0_899976223 /* d1[0] */
.short FIX_2_053119869_MINUS_2_562915447 /* d1[1] */
.short FIX_0_541196100_PLUS_0_765366865 /* d1[2] */
.short FIX_1_175875602 /* d1[3] */
/* reloadable constants */
.short FIX_1_175875602_MINUS_0_390180644 /* d2[0] */
.short FIX_0_541196100_MINUS_1_847759065 /* d2[1] */
.short FIX_3_072711026_MINUS_2_562915447 /* d2[2] */
.short FIX_1_175875602_MINUS_1_961570560 /* d2[3] */
asm_function jsimd_idct_islow_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req r1
TMP3 .req r2
TMP4 .req ip
ROW0L .req d16
ROW0R .req d17
ROW1L .req d18
ROW1R .req d19
ROW2L .req d20
ROW2R .req d21
ROW3L .req d22
ROW3R .req d23
ROW4L .req d24
ROW4R .req d25
ROW5L .req d26
ROW5R .req d27
ROW6L .req d28
ROW6R .req d29
ROW7L .req d30
ROW7R .req d31
/* Load and dequantize coefficients into NEON registers
* with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 ( q8 )
* 1 | d18 | d19 ( q9 )
* 2 | d20 | d21 ( q10 )
* 3 | d22 | d23 ( q11 )
* 4 | d24 | d25 ( q12 )
* 5 | d26 | d27 ( q13 )
* 6 | d28 | d29 ( q14 )
* 7 | d30 | d31 ( q15 )
*/
adr ip, jsimd_idct_islow_neon_consts
vld1.16 {d16, d17, d18, d19}, [COEF_BLOCK, :128]!
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vld1.16 {d20, d21, d22, d23}, [COEF_BLOCK, :128]!
vmul.s16 q8, q8, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q9, q9, q1
vld1.16 {d24, d25, d26, d27}, [COEF_BLOCK, :128]!
vmul.s16 q10, q10, q2
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vmul.s16 q11, q11, q3
vld1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]
vmul.s16 q12, q12, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q14, q14, q2
vmul.s16 q13, q13, q1
vld1.16 {d0, d1, d2, d3}, [ip, :128] /* load constants */
add ip, ip, #16
vmul.s16 q15, q15, q3
vpush {d8-d15} /* save NEON registers */
/* 1-D IDCT, pass 1, left 4x8 half */
vadd.s16 d4, ROW7L, ROW3L
vadd.s16 d5, ROW5L, ROW1L
vmull.s16 q6, d4, XFIX_1_175875602_MINUS_1_961570560
vmlal.s16 q6, d5, XFIX_1_175875602
vmull.s16 q7, d4, XFIX_1_175875602
/* Check for the zero coefficients in the right 4x8 half */
push {r4, r5}
vmlal.s16 q7, d5, XFIX_1_175875602_MINUS_0_390180644
vsubl.s16 q3, ROW0L, ROW4L
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 1 * 8))]
vmull.s16 q2, ROW2L, XFIX_0_541196100
vmlal.s16 q2, ROW6L, XFIX_0_541196100_MINUS_1_847759065
orr r0, r4, r5
vmov q4, q6
vmlsl.s16 q6, ROW5L, XFIX_2_562915447
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 2 * 8))]
vmlal.s16 q6, ROW3L, XFIX_3_072711026_MINUS_2_562915447
vshl.s32 q3, q3, #13
orr r0, r0, r4
vmlsl.s16 q4, ROW1L, XFIX_0_899976223
orr r0, r0, r5
vadd.s32 q1, q3, q2
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 3 * 8))]
vmov q5, q7
vadd.s32 q1, q1, q6
orr r0, r0, r4
vmlsl.s16 q7, ROW7L, XFIX_0_899976223
orr r0, r0, r5
vmlal.s16 q7, ROW1L, XFIX_1_501321110_MINUS_0_899976223
vrshrn.s32 ROW1L, q1, #11
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 4 * 8))]
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW5L, XFIX_2_053119869_MINUS_2_562915447
orr r0, r0, r4
vmlsl.s16 q5, ROW3L, XFIX_2_562915447
orr r0, r0, r5
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2L, XFIX_0_541196100_PLUS_0_765366865
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 5 * 8))]
vmlal.s16 q6, ROW6L, XFIX_0_541196100
vsub.s32 q3, q3, q2
orr r0, r0, r4
vrshrn.s32 ROW6L, q1, #11
orr r0, r0, r5
vadd.s32 q1, q3, q5
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 6 * 8))]
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW0L, ROW4L
orr r0, r0, r4
vrshrn.s32 ROW2L, q1, #11
orr r0, r0, r5
vrshrn.s32 ROW5L, q3, #11
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 7 * 8))]
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW7L, XFIX_0_298631336_MINUS_0_899976223
orr r0, r0, r4
vadd.s32 q2, q5, q6
orrs r0, r0, r5
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
ldrd r4, [COEF_BLOCK, #(-96 + 2 * (4 + 0 * 8))]
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
orr r0, r4, r5
vsub.s32 q3, q1, q4
pop {r4, r5}
vrshrn.s32 ROW7L, q2, #11
vrshrn.s32 ROW3L, q5, #11
vrshrn.s32 ROW0L, q6, #11
vrshrn.s32 ROW4L, q3, #11
beq 3f /* Go to do some special handling for the sparse
right 4x8 half */
/* 1-D IDCT, pass 1, right 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vadd.s16 d10, ROW7R, ROW3R
vadd.s16 d8, ROW5R, ROW1R
/* Transpose left 4x8 half */
vtrn.16 ROW6L, ROW7L
vmull.s16 q6, d10, XFIX_1_175875602_MINUS_1_961570560
vmlal.s16 q6, d8, XFIX_1_175875602
vtrn.16 ROW2L, ROW3L
vmull.s16 q7, d10, XFIX_1_175875602
vmlal.s16 q7, d8, XFIX_1_175875602_MINUS_0_390180644
vtrn.16 ROW0L, ROW1L
vsubl.s16 q3, ROW0R, ROW4R
vmull.s16 q2, ROW2R, XFIX_0_541196100
vmlal.s16 q2, ROW6R, XFIX_0_541196100_MINUS_1_847759065
vtrn.16 ROW4L, ROW5L
vmov q4, q6
vmlsl.s16 q6, ROW5R, XFIX_2_562915447
vmlal.s16 q6, ROW3R, XFIX_3_072711026_MINUS_2_562915447
vtrn.32 ROW1L, ROW3L
vshl.s32 q3, q3, #13
vmlsl.s16 q4, ROW1R, XFIX_0_899976223
vtrn.32 ROW4L, ROW6L
vadd.s32 q1, q3, q2
vmov q5, q7
vadd.s32 q1, q1, q6
vtrn.32 ROW0L, ROW2L
vmlsl.s16 q7, ROW7R, XFIX_0_899976223
vmlal.s16 q7, ROW1R, XFIX_1_501321110_MINUS_0_899976223
vrshrn.s32 ROW1R, q1, #11
vtrn.32 ROW5L, ROW7L
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW5R, XFIX_2_053119869_MINUS_2_562915447
vmlsl.s16 q5, ROW3R, XFIX_2_562915447
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2R, XFIX_0_541196100_PLUS_0_765366865
vmlal.s16 q6, ROW6R, XFIX_0_541196100
vsub.s32 q3, q3, q2
vrshrn.s32 ROW6R, q1, #11
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW0R, ROW4R
vrshrn.s32 ROW2R, q1, #11
vrshrn.s32 ROW5R, q3, #11
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW7R, XFIX_0_298631336_MINUS_0_899976223
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vrshrn.s32 ROW7R, q2, #11
vrshrn.s32 ROW3R, q5, #11
vrshrn.s32 ROW0R, q6, #11
vrshrn.s32 ROW4R, q3, #11
/* Transpose right 4x8 half */
vtrn.16 ROW6R, ROW7R
vtrn.16 ROW2R, ROW3R
vtrn.16 ROW0R, ROW1R
vtrn.16 ROW4R, ROW5R
vtrn.32 ROW1R, ROW3R
vtrn.32 ROW4R, ROW6R
vtrn.32 ROW0R, ROW2R
vtrn.32 ROW5R, ROW7R
1: /* 1-D IDCT, pass 2 (normal variant), left 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW1R, XFIX_1_175875602 /* ROW5L <-> ROW1R */
vmlal.s16 q6, ROW1L, XFIX_1_175875602
vmlal.s16 q6, ROW3R, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L <-> ROW3R */
vmlal.s16 q6, ROW3L, XFIX_1_175875602_MINUS_1_961570560
vmull.s16 q7, ROW3R, XFIX_1_175875602 /* ROW7L <-> ROW3R */
vmlal.s16 q7, ROW3L, XFIX_1_175875602
vmlal.s16 q7, ROW1R, XFIX_1_175875602_MINUS_0_390180644 /* ROW5L <-> ROW1R */
vmlal.s16 q7, ROW1L, XFIX_1_175875602_MINUS_0_390180644
vsubl.s16 q3, ROW0L, ROW0R /* ROW4L <-> ROW0R */
vmull.s16 q2, ROW2L, XFIX_0_541196100
vmlal.s16 q2, ROW2R, XFIX_0_541196100_MINUS_1_847759065 /* ROW6L <-> ROW2R */
vmov q4, q6
vmlsl.s16 q6, ROW1R, XFIX_2_562915447 /* ROW5L <-> ROW1R */
vmlal.s16 q6, ROW3L, XFIX_3_072711026_MINUS_2_562915447
vshl.s32 q3, q3, #13
vmlsl.s16 q4, ROW1L, XFIX_0_899976223
vadd.s32 q1, q3, q2
vmov q5, q7
vadd.s32 q1, q1, q6
vmlsl.s16 q7, ROW3R, XFIX_0_899976223 /* ROW7L <-> ROW3R */
vmlal.s16 q7, ROW1L, XFIX_1_501321110_MINUS_0_899976223
vshrn.s32 ROW1L, q1, #16
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW1R, XFIX_2_053119869_MINUS_2_562915447 /* ROW5L <-> ROW1R */
vmlsl.s16 q5, ROW3L, XFIX_2_562915447
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2L, XFIX_0_541196100_PLUS_0_765366865
vmlal.s16 q6, ROW2R, XFIX_0_541196100 /* ROW6L <-> ROW2R */
vsub.s32 q3, q3, q2
vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW0L, ROW0R /* ROW4L <-> ROW0R */
vshrn.s32 ROW2L, q1, #16
vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW3R, XFIX_0_298631336_MINUS_0_899976223 /* ROW7L <-> ROW3R */
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW3L, q5, #16
vshrn.s32 ROW0L, q6, #16
vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
/* 1-D IDCT, pass 2, right 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW5R, XFIX_1_175875602
vmlal.s16 q6, ROW5L, XFIX_1_175875602 /* ROW5L <-> ROW1R */
vmlal.s16 q6, ROW7R, XFIX_1_175875602_MINUS_1_961570560
vmlal.s16 q6, ROW7L, XFIX_1_175875602_MINUS_1_961570560 /* ROW7L <-> ROW3R */
vmull.s16 q7, ROW7R, XFIX_1_175875602
vmlal.s16 q7, ROW7L, XFIX_1_175875602 /* ROW7L <-> ROW3R */
vmlal.s16 q7, ROW5R, XFIX_1_175875602_MINUS_0_390180644
vmlal.s16 q7, ROW5L, XFIX_1_175875602_MINUS_0_390180644 /* ROW5L <-> ROW1R */
vsubl.s16 q3, ROW4L, ROW4R /* ROW4L <-> ROW0R */
vmull.s16 q2, ROW6L, XFIX_0_541196100 /* ROW6L <-> ROW2R */
vmlal.s16 q2, ROW6R, XFIX_0_541196100_MINUS_1_847759065
vmov q4, q6
vmlsl.s16 q6, ROW5R, XFIX_2_562915447
vmlal.s16 q6, ROW7L, XFIX_3_072711026_MINUS_2_562915447 /* ROW7L <-> ROW3R */
vshl.s32 q3, q3, #13
vmlsl.s16 q4, ROW5L, XFIX_0_899976223 /* ROW5L <-> ROW1R */
vadd.s32 q1, q3, q2
vmov q5, q7
vadd.s32 q1, q1, q6
vmlsl.s16 q7, ROW7R, XFIX_0_899976223
vmlal.s16 q7, ROW5L, XFIX_1_501321110_MINUS_0_899976223 /* ROW5L <-> ROW1R */
vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
vsub.s32 q1, q1, q6
vmlal.s16 q5, ROW5R, XFIX_2_053119869_MINUS_2_562915447
vmlsl.s16 q5, ROW7L, XFIX_2_562915447 /* ROW7L <-> ROW3R */
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW6L, XFIX_0_541196100_PLUS_0_765366865 /* ROW6L <-> ROW2R */
vmlal.s16 q6, ROW6R, XFIX_0_541196100
vsub.s32 q3, q3, q2
vshrn.s32 ROW6R, q1, #16
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vaddl.s16 q5, ROW4L, ROW4R /* ROW4L <-> ROW0R */
vshrn.s32 ROW6L, q1, #16 /* ROW6L <-> ROW2R */
vshrn.s32 ROW5R, q3, #16
vshl.s32 q5, q5, #13
vmlal.s16 q4, ROW7R, XFIX_0_298631336_MINUS_0_899976223
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW7R, q2, #16
vshrn.s32 ROW7L, q5, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW4L, q6, #16 /* ROW4L <-> ROW0R */
vshrn.s32 ROW4R, q3, #16
2: /* Descale to 8-bit and range limit */
vqrshrn.s16 d16, q8, #2
vqrshrn.s16 d17, q9, #2
vqrshrn.s16 d18, q10, #2
vqrshrn.s16 d19, q11, #2
vpop {d8-d15} /* restore NEON registers */
vqrshrn.s16 d20, q12, #2
/* Transpose the final 8-bit samples and do signed->unsigned conversion */
vtrn.16 q8, q9
vqrshrn.s16 d21, q13, #2
vqrshrn.s16 d22, q14, #2
vmov.u8 q0, #(CENTERJSAMPLE)
vqrshrn.s16 d23, q15, #2
vtrn.8 d16, d17
vtrn.8 d18, d19
vadd.u8 q8, q8, q0
vadd.u8 q9, q9, q0
vtrn.16 q10, q11
/* Store results to the output buffer */
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d16}, [TMP1]
vtrn.8 d20, d21
vst1.8 {d17}, [TMP2]
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d18}, [TMP1]
vadd.u8 q10, q10, q0
vst1.8 {d19}, [TMP2]
ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
vtrn.8 d22, d23
vst1.8 {d20}, [TMP1]
vadd.u8 q11, q11, q0
vst1.8 {d21}, [TMP2]
vst1.8 {d22}, [TMP3]
vst1.8 {d23}, [TMP4]
bx lr
3: /* Left 4x8 half is done, right 4x8 half contains mostly zeros */
/* Transpose left 4x8 half */
vtrn.16 ROW6L, ROW7L
vtrn.16 ROW2L, ROW3L
vtrn.16 ROW0L, ROW1L
vtrn.16 ROW4L, ROW5L
vshl.s16 ROW0R, ROW0R, #2 /* PASS1_BITS */
vtrn.32 ROW1L, ROW3L
vtrn.32 ROW4L, ROW6L
vtrn.32 ROW0L, ROW2L
vtrn.32 ROW5L, ROW7L
cmp r0, #0
beq 4f /* Right 4x8 half has all zeros, go to 'sparse' second
pass */
/* Only row 0 is non-zero for the right 4x8 half */
vdup.s16 ROW1R, ROW0R[1]
vdup.s16 ROW2R, ROW0R[2]
vdup.s16 ROW3R, ROW0R[3]
vdup.s16 ROW4R, ROW0R[0]
vdup.s16 ROW5R, ROW0R[1]
vdup.s16 ROW6R, ROW0R[2]
vdup.s16 ROW7R, ROW0R[3]
vdup.s16 ROW0R, ROW0R[0]
b 1b /* Go to 'normal' second pass */
4: /* 1-D IDCT, pass 2 (sparse variant with zero rows 4-7), left 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW1L, XFIX_1_175875602
vmlal.s16 q6, ROW3L, XFIX_1_175875602_MINUS_1_961570560
vmull.s16 q7, ROW3L, XFIX_1_175875602
vmlal.s16 q7, ROW1L, XFIX_1_175875602_MINUS_0_390180644
vmull.s16 q2, ROW2L, XFIX_0_541196100
vshll.s16 q3, ROW0L, #13
vmov q4, q6
vmlal.s16 q6, ROW3L, XFIX_3_072711026_MINUS_2_562915447
vmlsl.s16 q4, ROW1L, XFIX_0_899976223
vadd.s32 q1, q3, q2
vmov q5, q7
vmlal.s16 q7, ROW1L, XFIX_1_501321110_MINUS_0_899976223
vadd.s32 q1, q1, q6
vadd.s32 q6, q6, q6
vmlsl.s16 q5, ROW3L, XFIX_2_562915447
vshrn.s32 ROW1L, q1, #16
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW2L, XFIX_0_541196100_PLUS_0_765366865
vsub.s32 q3, q3, q2
vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vshll.s16 q5, ROW0L, #13
vshrn.s32 ROW2L, q1, #16
vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW3L, q5, #16
vshrn.s32 ROW0L, q6, #16
vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
/* 1-D IDCT, pass 2 (sparse variant with zero rows 4-7), right 4x8 half */
vld1.s16 {d2}, [ip, :64] /* reload constants */
vmull.s16 q6, ROW5L, XFIX_1_175875602
vmlal.s16 q6, ROW7L, XFIX_1_175875602_MINUS_1_961570560
vmull.s16 q7, ROW7L, XFIX_1_175875602
vmlal.s16 q7, ROW5L, XFIX_1_175875602_MINUS_0_390180644
vmull.s16 q2, ROW6L, XFIX_0_541196100
vshll.s16 q3, ROW4L, #13
vmov q4, q6
vmlal.s16 q6, ROW7L, XFIX_3_072711026_MINUS_2_562915447
vmlsl.s16 q4, ROW5L, XFIX_0_899976223
vadd.s32 q1, q3, q2
vmov q5, q7
vmlal.s16 q7, ROW5L, XFIX_1_501321110_MINUS_0_899976223
vadd.s32 q1, q1, q6
vadd.s32 q6, q6, q6
vmlsl.s16 q5, ROW7L, XFIX_2_562915447
vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
vsub.s32 q1, q1, q6
vmull.s16 q6, ROW6L, XFIX_0_541196100_PLUS_0_765366865
vsub.s32 q3, q3, q2
vshrn.s32 ROW6R, q1, #16
vadd.s32 q1, q3, q5
vsub.s32 q3, q3, q5
vshll.s16 q5, ROW4L, #13
vshrn.s32 ROW6L, q1, #16 /* ROW6L <-> ROW2R */
vshrn.s32 ROW5R, q3, #16
vadd.s32 q2, q5, q6
vsub.s32 q1, q5, q6
vadd.s32 q6, q2, q7
vsub.s32 q2, q2, q7
vadd.s32 q5, q1, q4
vsub.s32 q3, q1, q4
vshrn.s32 ROW7R, q2, #16
vshrn.s32 ROW7L, q5, #16 /* ROW7L <-> ROW3R */
vshrn.s32 ROW4L, q6, #16 /* ROW4L <-> ROW0R */
vshrn.s32 ROW4R, q3, #16
b 2b /* Go to epilogue */
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.unreq ROW0L
.unreq ROW0R
.unreq ROW1L
.unreq ROW1R
.unreq ROW2L
.unreq ROW2R
.unreq ROW3L
.unreq ROW3R
.unreq ROW4L
.unreq ROW4R
.unreq ROW5L
.unreq ROW5R
.unreq ROW6L
.unreq ROW6R
.unreq ROW7L
.unreq ROW7R
/*****************************************************************************/
/*
* jsimd_idct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the inverse DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_ifast'
* function from jidctfst.c
*
* Normally 1-D AAN DCT needs 5 multiplications and 29 additions.
* But in ARM NEON case some extra additions are required because VQDMULH
* instruction can't handle the constants larger than 1. So the expressions
* like "x * 1.082392200" have to be converted to "x * 0.082392200 + x",
* which introduces an extra addition. Overall, there are 6 extra additions
* per 1-D IDCT pass, totalling to 5 VQDMULH and 35 VADD/VSUB instructions.
*/
#define XFIX_1_082392200 d0[0]
#define XFIX_1_414213562 d0[1]
#define XFIX_1_847759065 d0[2]
#define XFIX_2_613125930 d0[3]
.balign 16
jsimd_idct_ifast_neon_consts:
.short (277 * 128 - 256 * 128) /* XFIX_1_082392200 */
.short (362 * 128 - 256 * 128) /* XFIX_1_414213562 */
.short (473 * 128 - 256 * 128) /* XFIX_1_847759065 */
.short (669 * 128 - 512 * 128) /* XFIX_2_613125930 */
asm_function jsimd_idct_ifast_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req r1
TMP3 .req r2
TMP4 .req ip
/* Load and dequantize coefficients into NEON registers
* with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 ( q8 )
* 1 | d18 | d19 ( q9 )
* 2 | d20 | d21 ( q10 )
* 3 | d22 | d23 ( q11 )
* 4 | d24 | d25 ( q12 )
* 5 | d26 | d27 ( q13 )
* 6 | d28 | d29 ( q14 )
* 7 | d30 | d31 ( q15 )
*/
adr ip, jsimd_idct_ifast_neon_consts
vld1.16 {d16, d17, d18, d19}, [COEF_BLOCK, :128]!
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vld1.16 {d20, d21, d22, d23}, [COEF_BLOCK, :128]!
vmul.s16 q8, q8, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q9, q9, q1
vld1.16 {d24, d25, d26, d27}, [COEF_BLOCK, :128]!
vmul.s16 q10, q10, q2
vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
vmul.s16 q11, q11, q3
vld1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]
vmul.s16 q12, q12, q0
vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
vmul.s16 q14, q14, q2
vmul.s16 q13, q13, q1
vld1.16 {d0}, [ip, :64] /* load constants */
vmul.s16 q15, q15, q3
vpush {d8-d13} /* save NEON registers */
/* 1-D IDCT, pass 1 */
vsub.s16 q2, q10, q14
vadd.s16 q14, q10, q14
vsub.s16 q1, q11, q13
vadd.s16 q13, q11, q13
vsub.s16 q5, q9, q15
vadd.s16 q15, q9, q15
vqdmulh.s16 q4, q2, XFIX_1_414213562
vqdmulh.s16 q6, q1, XFIX_2_613125930
vadd.s16 q3, q1, q1
vsub.s16 q1, q5, q1
vadd.s16 q10, q2, q4
vqdmulh.s16 q4, q1, XFIX_1_847759065
vsub.s16 q2, q15, q13
vadd.s16 q3, q3, q6
vqdmulh.s16 q6, q2, XFIX_1_414213562
vadd.s16 q1, q1, q4
vqdmulh.s16 q4, q5, XFIX_1_082392200
vsub.s16 q10, q10, q14
vadd.s16 q2, q2, q6
vsub.s16 q6, q8, q12
vadd.s16 q12, q8, q12
vadd.s16 q9, q5, q4
vadd.s16 q5, q6, q10
vsub.s16 q10, q6, q10
vadd.s16 q6, q15, q13
vadd.s16 q8, q12, q14
vsub.s16 q3, q6, q3
vsub.s16 q12, q12, q14
vsub.s16 q3, q3, q1
vsub.s16 q1, q9, q1
vadd.s16 q2, q3, q2
vsub.s16 q15, q8, q6
vadd.s16 q1, q1, q2
vadd.s16 q8, q8, q6
vadd.s16 q14, q5, q3
vsub.s16 q9, q5, q3
vsub.s16 q13, q10, q2
vadd.s16 q10, q10, q2
/* Transpose */
vtrn.16 q8, q9
vsub.s16 q11, q12, q1
vtrn.16 q14, q15
vadd.s16 q12, q12, q1
vtrn.16 q10, q11
vtrn.16 q12, q13
vtrn.32 q9, q11
vtrn.32 q12, q14
vtrn.32 q8, q10
vtrn.32 q13, q15
vswp d28, d21
vswp d26, d19
/* 1-D IDCT, pass 2 */
vsub.s16 q2, q10, q14
vswp d30, d23
vadd.s16 q14, q10, q14
vswp d24, d17
vsub.s16 q1, q11, q13
vadd.s16 q13, q11, q13
vsub.s16 q5, q9, q15
vadd.s16 q15, q9, q15
vqdmulh.s16 q4, q2, XFIX_1_414213562
vqdmulh.s16 q6, q1, XFIX_2_613125930
vadd.s16 q3, q1, q1
vsub.s16 q1, q5, q1
vadd.s16 q10, q2, q4
vqdmulh.s16 q4, q1, XFIX_1_847759065
vsub.s16 q2, q15, q13
vadd.s16 q3, q3, q6
vqdmulh.s16 q6, q2, XFIX_1_414213562
vadd.s16 q1, q1, q4
vqdmulh.s16 q4, q5, XFIX_1_082392200
vsub.s16 q10, q10, q14
vadd.s16 q2, q2, q6
vsub.s16 q6, q8, q12
vadd.s16 q12, q8, q12
vadd.s16 q9, q5, q4
vadd.s16 q5, q6, q10
vsub.s16 q10, q6, q10
vadd.s16 q6, q15, q13
vadd.s16 q8, q12, q14
vsub.s16 q3, q6, q3
vsub.s16 q12, q12, q14
vsub.s16 q3, q3, q1
vsub.s16 q1, q9, q1
vadd.s16 q2, q3, q2
vsub.s16 q15, q8, q6
vadd.s16 q1, q1, q2
vadd.s16 q8, q8, q6
vadd.s16 q14, q5, q3
vsub.s16 q9, q5, q3
vsub.s16 q13, q10, q2
vpop {d8-d13} /* restore NEON registers */
vadd.s16 q10, q10, q2
vsub.s16 q11, q12, q1
vadd.s16 q12, q12, q1
/* Descale to 8-bit and range limit */
vmov.u8 q0, #0x80
vqshrn.s16 d16, q8, #5
vqshrn.s16 d17, q9, #5
vqshrn.s16 d18, q10, #5
vqshrn.s16 d19, q11, #5
vqshrn.s16 d20, q12, #5
vqshrn.s16 d21, q13, #5
vqshrn.s16 d22, q14, #5
vqshrn.s16 d23, q15, #5
vadd.u8 q8, q8, q0
vadd.u8 q9, q9, q0
vadd.u8 q10, q10, q0
vadd.u8 q11, q11, q0
/* Transpose the final 8-bit samples */
vtrn.16 q8, q9
vtrn.16 q10, q11
vtrn.32 q8, q10
vtrn.32 q9, q11
vtrn.8 d16, d17
vtrn.8 d18, d19
/* Store results to the output buffer */
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d16}, [TMP1]
vst1.8 {d17}, [TMP2]
ldmia OUTPUT_BUF!, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d18}, [TMP1]
vtrn.8 d20, d21
vst1.8 {d19}, [TMP2]
ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
vst1.8 {d20}, [TMP1]
vtrn.8 d22, d23
vst1.8 {d21}, [TMP2]
vst1.8 {d22}, [TMP3]
vst1.8 {d23}, [TMP4]
bx lr
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
/*****************************************************************************/
/*
* jsimd_idct_4x4_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 4x4 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_4x4'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 4x4 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*
* TODO: a bit better instructions scheduling can be achieved by expanding
* idct_helper/transpose_4x4 macros and reordering instructions,
* but readability will suffer somewhat.
*/
#define CONST_BITS 13
#define FIX_0_211164243 (1730) /* FIX(0.211164243) */
#define FIX_0_509795579 (4176) /* FIX(0.509795579) */
#define FIX_0_601344887 (4926) /* FIX(0.601344887) */
#define FIX_0_720959822 (5906) /* FIX(0.720959822) */
#define FIX_0_765366865 (6270) /* FIX(0.765366865) */
#define FIX_0_850430095 (6967) /* FIX(0.850430095) */
#define FIX_0_899976223 (7373) /* FIX(0.899976223) */
#define FIX_1_061594337 (8697) /* FIX(1.061594337) */
#define FIX_1_272758580 (10426) /* FIX(1.272758580) */
#define FIX_1_451774981 (11893) /* FIX(1.451774981) */
#define FIX_1_847759065 (15137) /* FIX(1.847759065) */
#define FIX_2_172734803 (17799) /* FIX(2.172734803) */
#define FIX_2_562915447 (20995) /* FIX(2.562915447) */
#define FIX_3_624509785 (29692) /* FIX(3.624509785) */
.balign 16
jsimd_idct_4x4_neon_consts:
.short FIX_1_847759065 /* d0[0] */
.short -FIX_0_765366865 /* d0[1] */
.short -FIX_0_211164243 /* d0[2] */
.short FIX_1_451774981 /* d0[3] */
.short -FIX_2_172734803 /* d1[0] */
.short FIX_1_061594337 /* d1[1] */
.short -FIX_0_509795579 /* d1[2] */
.short -FIX_0_601344887 /* d1[3] */
.short FIX_0_899976223 /* d2[0] */
.short FIX_2_562915447 /* d2[1] */
.short 1 << (CONST_BITS+1) /* d2[2] */
.short 0 /* d2[3] */
.macro idct_helper x4, x6, x8, x10, x12, x14, x16, shift, y26, y27, y28, y29
vmull.s16 q14, \x4, d2[2]
vmlal.s16 q14, \x8, d0[0]
vmlal.s16 q14, \x14, d0[1]
vmull.s16 q13, \x16, d1[2]
vmlal.s16 q13, \x12, d1[3]
vmlal.s16 q13, \x10, d2[0]
vmlal.s16 q13, \x6, d2[1]
vmull.s16 q15, \x4, d2[2]
vmlsl.s16 q15, \x8, d0[0]
vmlsl.s16 q15, \x14, d0[1]
vmull.s16 q12, \x16, d0[2]
vmlal.s16 q12, \x12, d0[3]
vmlal.s16 q12, \x10, d1[0]
vmlal.s16 q12, \x6, d1[1]
vadd.s32 q10, q14, q13
vsub.s32 q14, q14, q13
.if \shift > 16
vrshr.s32 q10, q10, #\shift
vrshr.s32 q14, q14, #\shift
vmovn.s32 \y26, q10
vmovn.s32 \y29, q14
.else
vrshrn.s32 \y26, q10, #\shift
vrshrn.s32 \y29, q14, #\shift
.endif
vadd.s32 q10, q15, q12
vsub.s32 q15, q15, q12
.if \shift > 16
vrshr.s32 q10, q10, #\shift
vrshr.s32 q15, q15, #\shift
vmovn.s32 \y27, q10
vmovn.s32 \y28, q15
.else
vrshrn.s32 \y27, q10, #\shift
vrshrn.s32 \y28, q15, #\shift
.endif
.endm
asm_function jsimd_idct_4x4_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req r1
TMP3 .req r2
TMP4 .req ip
vpush {d8-d15}
/* Load constants (d3 is just used for padding) */
adr TMP4, jsimd_idct_4x4_neon_consts
vld1.16 {d0, d1, d2, d3}, [TMP4, :128]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d4 | d5
* 1 | d6 | d7
* 2 | d8 | d9
* 3 | d10 | d11
* 4 | - | -
* 5 | d12 | d13
* 6 | d14 | d15
* 7 | d16 | d17
*/
vld1.16 {d4, d5, d6, d7}, [COEF_BLOCK, :128]!
vld1.16 {d8, d9, d10, d11}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d12, d13, d14, d15}, [COEF_BLOCK, :128]!
vld1.16 {d16, d17}, [COEF_BLOCK, :128]!
/* dequantize */
vld1.16 {d18, d19, d20, d21}, [DCT_TABLE, :128]!
vmul.s16 q2, q2, q9
vld1.16 {d22, d23, d24, d25}, [DCT_TABLE, :128]!
vmul.s16 q3, q3, q10
vmul.s16 q4, q4, q11
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d26, d27, d28, d29}, [DCT_TABLE, :128]!
vmul.s16 q5, q5, q12
vmul.s16 q6, q6, q13
vld1.16 {d30, d31}, [DCT_TABLE, :128]!
vmul.s16 q7, q7, q14
vmul.s16 q8, q8, q15
/* Pass 1 */
idct_helper d4, d6, d8, d10, d12, d14, d16, 12, d4, d6, d8, d10
transpose_4x4 d4, d6, d8, d10
idct_helper d5, d7, d9, d11, d13, d15, d17, 12, d5, d7, d9, d11
transpose_4x4 d5, d7, d9, d11
/* Pass 2 */
idct_helper d4, d6, d8, d10, d7, d9, d11, 19, d26, d27, d28, d29
transpose_4x4 d26, d27, d28, d29
/* Range limit */
vmov.u16 q15, #0x80
vadd.s16 q13, q13, q15
vadd.s16 q14, q14, q15
vqmovun.s16 d26, q13
vqmovun.s16 d27, q14
/* Store results to the output buffer */
ldmia OUTPUT_BUF, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
#if defined(__ARMEL__) && !RESPECT_STRICT_ALIGNMENT
/* We can use much less instructions on little endian systems if the
* OS kernel is not configured to trap unaligned memory accesses
*/
vst1.32 {d26[0]}, [TMP1]!
vst1.32 {d27[0]}, [TMP3]!
vst1.32 {d26[1]}, [TMP2]!
vst1.32 {d27[1]}, [TMP4]!
#else
vst1.8 {d26[0]}, [TMP1]!
vst1.8 {d27[0]}, [TMP3]!
vst1.8 {d26[1]}, [TMP1]!
vst1.8 {d27[1]}, [TMP3]!
vst1.8 {d26[2]}, [TMP1]!
vst1.8 {d27[2]}, [TMP3]!
vst1.8 {d26[3]}, [TMP1]!
vst1.8 {d27[3]}, [TMP3]!
vst1.8 {d26[4]}, [TMP2]!
vst1.8 {d27[4]}, [TMP4]!
vst1.8 {d26[5]}, [TMP2]!
vst1.8 {d27[5]}, [TMP4]!
vst1.8 {d26[6]}, [TMP2]!
vst1.8 {d27[6]}, [TMP4]!
vst1.8 {d26[7]}, [TMP2]!
vst1.8 {d27[7]}, [TMP4]!
#endif
vpop {d8-d15}
bx lr
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_idct_2x2_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 2x2 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_2x2'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 2x2 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*/
.balign 8
jsimd_idct_2x2_neon_consts:
.short -FIX_0_720959822 /* d0[0] */
.short FIX_0_850430095 /* d0[1] */
.short -FIX_1_272758580 /* d0[2] */
.short FIX_3_624509785 /* d0[3] */
.macro idct_helper x4, x6, x10, x12, x16, shift, y26, y27
vshll.s16 q14, \x4, #15
vmull.s16 q13, \x6, d0[3]
vmlal.s16 q13, \x10, d0[2]
vmlal.s16 q13, \x12, d0[1]
vmlal.s16 q13, \x16, d0[0]
vadd.s32 q10, q14, q13
vsub.s32 q14, q14, q13
.if \shift > 16
vrshr.s32 q10, q10, #\shift
vrshr.s32 q14, q14, #\shift
vmovn.s32 \y26, q10
vmovn.s32 \y27, q14
.else
vrshrn.s32 \y26, q10, #\shift
vrshrn.s32 \y27, q14, #\shift
.endif
.endm
asm_function jsimd_idct_2x2_neon
DCT_TABLE .req r0
COEF_BLOCK .req r1
OUTPUT_BUF .req r2
OUTPUT_COL .req r3
TMP1 .req r0
TMP2 .req ip
vpush {d8-d15}
/* Load constants */
adr TMP2, jsimd_idct_2x2_neon_consts
vld1.16 {d0}, [TMP2, :64]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d4 | d5
* 1 | d6 | d7
* 2 | - | -
* 3 | d10 | d11
* 4 | - | -
* 5 | d12 | d13
* 6 | - | -
* 7 | d16 | d17
*/
vld1.16 {d4, d5, d6, d7}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d10, d11}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d12, d13}, [COEF_BLOCK, :128]!
add COEF_BLOCK, COEF_BLOCK, #16
vld1.16 {d16, d17}, [COEF_BLOCK, :128]!
/* Dequantize */
vld1.16 {d18, d19, d20, d21}, [DCT_TABLE, :128]!
vmul.s16 q2, q2, q9
vmul.s16 q3, q3, q10
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d24, d25}, [DCT_TABLE, :128]!
vmul.s16 q5, q5, q12
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d26, d27}, [DCT_TABLE, :128]!
vmul.s16 q6, q6, q13
add DCT_TABLE, DCT_TABLE, #16
vld1.16 {d30, d31}, [DCT_TABLE, :128]!
vmul.s16 q8, q8, q15
/* Pass 1 */
#if 0
idct_helper d4, d6, d10, d12, d16, 13, d4, d6
transpose_4x4 d4, d6, d8, d10
idct_helper d5, d7, d11, d13, d17, 13, d5, d7
transpose_4x4 d5, d7, d9, d11
#else
vmull.s16 q13, d6, d0[3]
vmlal.s16 q13, d10, d0[2]
vmlal.s16 q13, d12, d0[1]
vmlal.s16 q13, d16, d0[0]
vmull.s16 q12, d7, d0[3]
vmlal.s16 q12, d11, d0[2]
vmlal.s16 q12, d13, d0[1]
vmlal.s16 q12, d17, d0[0]
vshll.s16 q14, d4, #15
vshll.s16 q15, d5, #15
vadd.s32 q10, q14, q13
vsub.s32 q14, q14, q13
vrshrn.s32 d4, q10, #13
vrshrn.s32 d6, q14, #13
vadd.s32 q10, q15, q12
vsub.s32 q14, q15, q12
vrshrn.s32 d5, q10, #13
vrshrn.s32 d7, q14, #13
vtrn.16 q2, q3
vtrn.32 q3, q5
#endif
/* Pass 2 */
idct_helper d4, d6, d10, d7, d11, 20, d26, d27
/* Range limit */
vmov.u16 q15, #0x80
vadd.s16 q13, q13, q15
vqmovun.s16 d26, q13
vqmovun.s16 d27, q13
/* Store results to the output buffer */
ldmia OUTPUT_BUF, {TMP1, TMP2}
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
vst1.8 {d26[0]}, [TMP1]!
vst1.8 {d27[4]}, [TMP1]!
vst1.8 {d26[1]}, [TMP2]!
vst1.8 {d27[5]}, [TMP2]!
vpop {d8-d15}
bx lr
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_ycc_extrgb_convert_neon
* jsimd_ycc_extbgr_convert_neon
* jsimd_ycc_extrgbx_convert_neon
* jsimd_ycc_extbgrx_convert_neon
* jsimd_ycc_extxbgr_convert_neon
* jsimd_ycc_extxrgb_convert_neon
*
* Colorspace conversion YCbCr -> RGB
*/
.macro do_load size
.if \size == 8
vld1.8 {d4}, [U, :64]!
vld1.8 {d5}, [V, :64]!
vld1.8 {d0}, [Y, :64]!
pld [U, #64]
pld [V, #64]
pld [Y, #64]
.elseif \size == 4
vld1.8 {d4[0]}, [U]!
vld1.8 {d4[1]}, [U]!
vld1.8 {d4[2]}, [U]!
vld1.8 {d4[3]}, [U]!
vld1.8 {d5[0]}, [V]!
vld1.8 {d5[1]}, [V]!
vld1.8 {d5[2]}, [V]!
vld1.8 {d5[3]}, [V]!
vld1.8 {d0[0]}, [Y]!
vld1.8 {d0[1]}, [Y]!
vld1.8 {d0[2]}, [Y]!
vld1.8 {d0[3]}, [Y]!
.elseif \size == 2
vld1.8 {d4[4]}, [U]!
vld1.8 {d4[5]}, [U]!
vld1.8 {d5[4]}, [V]!
vld1.8 {d5[5]}, [V]!
vld1.8 {d0[4]}, [Y]!
vld1.8 {d0[5]}, [Y]!
.elseif \size == 1
vld1.8 {d4[6]}, [U]!
vld1.8 {d5[6]}, [V]!
vld1.8 {d0[6]}, [Y]!
.else
.error unsupported macroblock size
.endif
.endm
.macro do_store bpp, size
.if \bpp == 24
.if \size == 8
vst3.8 {d10, d11, d12}, [RGB]!
.elseif \size == 4
vst3.8 {d10[0], d11[0], d12[0]}, [RGB]!
vst3.8 {d10[1], d11[1], d12[1]}, [RGB]!
vst3.8 {d10[2], d11[2], d12[2]}, [RGB]!
vst3.8 {d10[3], d11[3], d12[3]}, [RGB]!
.elseif \size == 2
vst3.8 {d10[4], d11[4], d12[4]}, [RGB]!
vst3.8 {d10[5], d11[5], d12[5]}, [RGB]!
.elseif \size == 1
vst3.8 {d10[6], d11[6], d12[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
vst4.8 {d10, d11, d12, d13}, [RGB]!
.elseif \size == 4
vst4.8 {d10[0], d11[0], d12[0], d13[0]}, [RGB]!
vst4.8 {d10[1], d11[1], d12[1], d13[1]}, [RGB]!
vst4.8 {d10[2], d11[2], d12[2], d13[2]}, [RGB]!
vst4.8 {d10[3], d11[3], d12[3], d13[3]}, [RGB]!
.elseif \size == 2
vst4.8 {d10[4], d11[4], d12[4], d13[4]}, [RGB]!
vst4.8 {d10[5], d11[5], d12[5], d13[5]}, [RGB]!
.elseif \size == 1
vst4.8 {d10[6], d11[6], d12[6], d13[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 16
.if \size == 8
vst1.16 {q15}, [RGB]!
.elseif \size == 4
vst1.16 {d30}, [RGB]!
.elseif \size == 2
vst1.16 {d31[0]}, [RGB]!
vst1.16 {d31[1]}, [RGB]!
.elseif \size == 1
vst1.16 {d31[2]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_ycc_rgb_convert_neon colorid, bpp, r_offs, g_offs, b_offs
/*
* 2-stage pipelined YCbCr->RGB conversion
*/
.macro do_yuv_to_rgb_stage1
vaddw.u8 q3, q1, d4 /* q3 = u - 128 */
vaddw.u8 q4, q1, d5 /* q2 = v - 128 */
vmull.s16 q10, d6, d1[1] /* multiply by -11277 */
vmlal.s16 q10, d8, d1[2] /* multiply by -23401 */
vmull.s16 q11, d7, d1[1] /* multiply by -11277 */
vmlal.s16 q11, d9, d1[2] /* multiply by -23401 */
vmull.s16 q12, d8, d1[0] /* multiply by 22971 */
vmull.s16 q13, d9, d1[0] /* multiply by 22971 */
vmull.s16 q14, d6, d1[3] /* multiply by 29033 */
vmull.s16 q15, d7, d1[3] /* multiply by 29033 */
.endm
.macro do_yuv_to_rgb_stage2
vrshrn.s32 d20, q10, #15
vrshrn.s32 d21, q11, #15
vrshrn.s32 d24, q12, #14
vrshrn.s32 d25, q13, #14
vrshrn.s32 d28, q14, #14
vrshrn.s32 d29, q15, #14
vaddw.u8 q11, q10, d0
vaddw.u8 q12, q12, d0
vaddw.u8 q14, q14, d0
.if \bpp != 16
vqmovun.s16 d1\g_offs, q11
vqmovun.s16 d1\r_offs, q12
vqmovun.s16 d1\b_offs, q14
.else /* rgb565 */
vqshlu.s16 q13, q11, #8
vqshlu.s16 q15, q12, #8
vqshlu.s16 q14, q14, #8
vsri.u16 q15, q13, #5
vsri.u16 q15, q14, #11
.endif
.endm
.macro do_yuv_to_rgb_stage2_store_load_stage1
/* "do_yuv_to_rgb_stage2" and "store" */
vrshrn.s32 d20, q10, #15
/* "load" and "do_yuv_to_rgb_stage1" */
pld [U, #64]
vrshrn.s32 d21, q11, #15
pld [V, #64]
vrshrn.s32 d24, q12, #14
vrshrn.s32 d25, q13, #14
vld1.8 {d4}, [U, :64]!
vrshrn.s32 d28, q14, #14
vld1.8 {d5}, [V, :64]!
vrshrn.s32 d29, q15, #14
vaddw.u8 q3, q1, d4 /* q3 = u - 128 */
vaddw.u8 q4, q1, d5 /* q2 = v - 128 */
vaddw.u8 q11, q10, d0
vmull.s16 q10, d6, d1[1] /* multiply by -11277 */
vmlal.s16 q10, d8, d1[2] /* multiply by -23401 */
vaddw.u8 q12, q12, d0
vaddw.u8 q14, q14, d0
.if \bpp != 16 /**************** rgb24/rgb32 ******************************/
vqmovun.s16 d1\g_offs, q11
pld [Y, #64]
vqmovun.s16 d1\r_offs, q12
vld1.8 {d0}, [Y, :64]!
vqmovun.s16 d1\b_offs, q14
vmull.s16 q11, d7, d1[1] /* multiply by -11277 */
vmlal.s16 q11, d9, d1[2] /* multiply by -23401 */
do_store \bpp, 8
vmull.s16 q12, d8, d1[0] /* multiply by 22971 */
vmull.s16 q13, d9, d1[0] /* multiply by 22971 */
vmull.s16 q14, d6, d1[3] /* multiply by 29033 */
vmull.s16 q15, d7, d1[3] /* multiply by 29033 */
.else /**************************** rgb565 ********************************/
vqshlu.s16 q13, q11, #8
pld [Y, #64]
vqshlu.s16 q15, q12, #8
vqshlu.s16 q14, q14, #8
vld1.8 {d0}, [Y, :64]!
vmull.s16 q11, d7, d1[1]
vmlal.s16 q11, d9, d1[2]
vsri.u16 q15, q13, #5
vmull.s16 q12, d8, d1[0]
vsri.u16 q15, q14, #11
vmull.s16 q13, d9, d1[0]
vmull.s16 q14, d6, d1[3]
do_store \bpp, 8
vmull.s16 q15, d7, d1[3]
.endif
.endm
.macro do_yuv_to_rgb
do_yuv_to_rgb_stage1
do_yuv_to_rgb_stage2
.endm
/* Apple gas crashes on adrl, work around that by using adr.
* But this requires a copy of these constants for each function.
*/
.balign 16
jsimd_ycc_\colorid\()_neon_consts:
.short 0, 0, 0, 0
.short 22971, -11277, -23401, 29033
.short -128, -128, -128, -128
.short -128, -128, -128, -128
asm_function jsimd_ycc_\colorid\()_convert_neon
OUTPUT_WIDTH .req r0
INPUT_BUF .req r1
INPUT_ROW .req r2
OUTPUT_BUF .req r3
NUM_ROWS .req r4
INPUT_BUF0 .req r5
INPUT_BUF1 .req r6
INPUT_BUF2 .req INPUT_BUF
RGB .req r7
Y .req r8
U .req r9
V .req r10
N .req ip
/* Load constants to d1, d2, d3 (d0 is just used for padding) */
adr ip, jsimd_ycc_\colorid\()_neon_consts
vld1.16 {d0, d1, d2, d3}, [ip, :128]
/* Save ARM registers and handle input arguments */
push {r4, r5, r6, r7, r8, r9, r10, lr}
ldr NUM_ROWS, [sp, #(4 * 8)]
ldr INPUT_BUF0, [INPUT_BUF]
ldr INPUT_BUF1, [INPUT_BUF, #4]
ldr INPUT_BUF2, [INPUT_BUF, #8]
.unreq INPUT_BUF
/* Save NEON registers */
vpush {d8-d15}
/* Initially set d10, d11, d12, d13 to 0xFF */
vmov.u8 q5, #255
vmov.u8 q6, #255
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
blt 9f
0:
ldr Y, [INPUT_BUF0, INPUT_ROW, lsl #2]
ldr U, [INPUT_BUF1, INPUT_ROW, lsl #2]
mov N, OUTPUT_WIDTH
ldr V, [INPUT_BUF2, INPUT_ROW, lsl #2]
add INPUT_ROW, INPUT_ROW, #1
ldr RGB, [OUTPUT_BUF], #4
/* Inner loop over pixels */
subs N, N, #8
blt 3f
do_load 8
do_yuv_to_rgb_stage1
subs N, N, #8
blt 2f
1:
do_yuv_to_rgb_stage2_store_load_stage1
subs N, N, #8
bge 1b
2:
do_yuv_to_rgb_stage2
do_store \bpp, 8
tst N, #7
beq 8f
3:
tst N, #4
beq 3f
do_load 4
3:
tst N, #2
beq 4f
do_load 2
4:
tst N, #1
beq 5f
do_load 1
5:
do_yuv_to_rgb
tst N, #4
beq 6f
do_store \bpp, 4
6:
tst N, #2
beq 7f
do_store \bpp, 2
7:
tst N, #1
beq 8f
do_store \bpp, 1
8:
subs NUM_ROWS, NUM_ROWS, #1
bgt 0b
9:
/* Restore all registers and return */
vpop {d8-d15}
pop {r4, r5, r6, r7, r8, r9, r10, pc}
.unreq OUTPUT_WIDTH
.unreq INPUT_ROW
.unreq OUTPUT_BUF
.unreq NUM_ROWS
.unreq INPUT_BUF0
.unreq INPUT_BUF1
.unreq INPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_yuv_to_rgb
.purgem do_yuv_to_rgb_stage1
.purgem do_yuv_to_rgb_stage2
.purgem do_yuv_to_rgb_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R G B */
generate_jsimd_ycc_rgb_convert_neon extrgb, 24, 0, 1, 2
generate_jsimd_ycc_rgb_convert_neon extbgr, 24, 2, 1, 0
generate_jsimd_ycc_rgb_convert_neon extrgbx, 32, 0, 1, 2
generate_jsimd_ycc_rgb_convert_neon extbgrx, 32, 2, 1, 0
generate_jsimd_ycc_rgb_convert_neon extxbgr, 32, 3, 2, 1
generate_jsimd_ycc_rgb_convert_neon extxrgb, 32, 1, 2, 3
generate_jsimd_ycc_rgb_convert_neon rgb565, 16, 0, 0, 0
.purgem do_load
.purgem do_store
/*****************************************************************************/
/*
* jsimd_extrgb_ycc_convert_neon
* jsimd_extbgr_ycc_convert_neon
* jsimd_extrgbx_ycc_convert_neon
* jsimd_extbgrx_ycc_convert_neon
* jsimd_extxbgr_ycc_convert_neon
* jsimd_extxrgb_ycc_convert_neon
*
* Colorspace conversion RGB -> YCbCr
*/
.macro do_store size
.if \size == 8
vst1.8 {d20}, [Y]!
vst1.8 {d21}, [U]!
vst1.8 {d22}, [V]!
.elseif \size == 4
vst1.8 {d20[0]}, [Y]!
vst1.8 {d20[1]}, [Y]!
vst1.8 {d20[2]}, [Y]!
vst1.8 {d20[3]}, [Y]!
vst1.8 {d21[0]}, [U]!
vst1.8 {d21[1]}, [U]!
vst1.8 {d21[2]}, [U]!
vst1.8 {d21[3]}, [U]!
vst1.8 {d22[0]}, [V]!
vst1.8 {d22[1]}, [V]!
vst1.8 {d22[2]}, [V]!
vst1.8 {d22[3]}, [V]!
.elseif \size == 2
vst1.8 {d20[4]}, [Y]!
vst1.8 {d20[5]}, [Y]!
vst1.8 {d21[4]}, [U]!
vst1.8 {d21[5]}, [U]!
vst1.8 {d22[4]}, [V]!
vst1.8 {d22[5]}, [V]!
.elseif \size == 1
vst1.8 {d20[6]}, [Y]!
vst1.8 {d21[6]}, [U]!
vst1.8 {d22[6]}, [V]!
.else
.error unsupported macroblock size
.endif
.endm
.macro do_load bpp, size
.if \bpp == 24
.if \size == 8
vld3.8 {d10, d11, d12}, [RGB]!
pld [RGB, #128]
.elseif \size == 4
vld3.8 {d10[0], d11[0], d12[0]}, [RGB]!
vld3.8 {d10[1], d11[1], d12[1]}, [RGB]!
vld3.8 {d10[2], d11[2], d12[2]}, [RGB]!
vld3.8 {d10[3], d11[3], d12[3]}, [RGB]!
.elseif \size == 2
vld3.8 {d10[4], d11[4], d12[4]}, [RGB]!
vld3.8 {d10[5], d11[5], d12[5]}, [RGB]!
.elseif \size == 1
vld3.8 {d10[6], d11[6], d12[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
vld4.8 {d10, d11, d12, d13}, [RGB]!
pld [RGB, #128]
.elseif \size == 4
vld4.8 {d10[0], d11[0], d12[0], d13[0]}, [RGB]!
vld4.8 {d10[1], d11[1], d12[1], d13[1]}, [RGB]!
vld4.8 {d10[2], d11[2], d12[2], d13[2]}, [RGB]!
vld4.8 {d10[3], d11[3], d12[3], d13[3]}, [RGB]!
.elseif \size == 2
vld4.8 {d10[4], d11[4], d12[4], d13[4]}, [RGB]!
vld4.8 {d10[5], d11[5], d12[5], d13[5]}, [RGB]!
.elseif \size == 1
vld4.8 {d10[6], d11[6], d12[6], d13[6]}, [RGB]!
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_rgb_ycc_convert_neon colorid, bpp, r_offs, g_offs, b_offs
/*
* 2-stage pipelined RGB->YCbCr conversion
*/
.macro do_rgb_to_yuv_stage1
vmovl.u8 q2, d1\r_offs /* r = { d4, d5 } */
vmovl.u8 q3, d1\g_offs /* g = { d6, d7 } */
vmovl.u8 q4, d1\b_offs /* b = { d8, d9 } */
vmull.u16 q7, d4, d0[0]
vmlal.u16 q7, d6, d0[1]
vmlal.u16 q7, d8, d0[2]
vmull.u16 q8, d5, d0[0]
vmlal.u16 q8, d7, d0[1]
vmlal.u16 q8, d9, d0[2]
vrev64.32 q9, q1
vrev64.32 q13, q1
vmlsl.u16 q9, d4, d0[3]
vmlsl.u16 q9, d6, d1[0]
vmlal.u16 q9, d8, d1[1]
vmlsl.u16 q13, d5, d0[3]
vmlsl.u16 q13, d7, d1[0]
vmlal.u16 q13, d9, d1[1]
vrev64.32 q14, q1
vrev64.32 q15, q1
vmlal.u16 q14, d4, d1[1]
vmlsl.u16 q14, d6, d1[2]
vmlsl.u16 q14, d8, d1[3]
vmlal.u16 q15, d5, d1[1]
vmlsl.u16 q15, d7, d1[2]
vmlsl.u16 q15, d9, d1[3]
.endm
.macro do_rgb_to_yuv_stage2
vrshrn.u32 d20, q7, #16
vrshrn.u32 d21, q8, #16
vshrn.u32 d22, q9, #16
vshrn.u32 d23, q13, #16
vshrn.u32 d24, q14, #16
vshrn.u32 d25, q15, #16
vmovn.u16 d20, q10 /* d20 = y */
vmovn.u16 d21, q11 /* d21 = u */
vmovn.u16 d22, q12 /* d22 = v */
.endm
.macro do_rgb_to_yuv
do_rgb_to_yuv_stage1
do_rgb_to_yuv_stage2
.endm
.macro do_rgb_to_yuv_stage2_store_load_stage1
vrshrn.u32 d20, q7, #16
vrshrn.u32 d21, q8, #16
vshrn.u32 d22, q9, #16
vrev64.32 q9, q1
vshrn.u32 d23, q13, #16
vrev64.32 q13, q1
vshrn.u32 d24, q14, #16
vshrn.u32 d25, q15, #16
do_load \bpp, 8
vmovn.u16 d20, q10 /* d20 = y */
vmovl.u8 q2, d1\r_offs /* r = { d4, d5 } */
vmovn.u16 d21, q11 /* d21 = u */
vmovl.u8 q3, d1\g_offs /* g = { d6, d7 } */
vmovn.u16 d22, q12 /* d22 = v */
vmovl.u8 q4, d1\b_offs /* b = { d8, d9 } */
vmull.u16 q7, d4, d0[0]
vmlal.u16 q7, d6, d0[1]
vmlal.u16 q7, d8, d0[2]
vst1.8 {d20}, [Y]!
vmull.u16 q8, d5, d0[0]
vmlal.u16 q8, d7, d0[1]
vmlal.u16 q8, d9, d0[2]
vmlsl.u16 q9, d4, d0[3]
vmlsl.u16 q9, d6, d1[0]
vmlal.u16 q9, d8, d1[1]
vst1.8 {d21}, [U]!
vmlsl.u16 q13, d5, d0[3]
vmlsl.u16 q13, d7, d1[0]
vmlal.u16 q13, d9, d1[1]
vrev64.32 q14, q1
vrev64.32 q15, q1
vmlal.u16 q14, d4, d1[1]
vmlsl.u16 q14, d6, d1[2]
vmlsl.u16 q14, d8, d1[3]
vst1.8 {d22}, [V]!
vmlal.u16 q15, d5, d1[1]
vmlsl.u16 q15, d7, d1[2]
vmlsl.u16 q15, d9, d1[3]
.endm
.balign 16
jsimd_\colorid\()_ycc_neon_consts:
.short 19595, 38470, 7471, 11059
.short 21709, 32768, 27439, 5329
.short 32767, 128, 32767, 128
.short 32767, 128, 32767, 128
asm_function jsimd_\colorid\()_ycc_convert_neon
OUTPUT_WIDTH .req r0
INPUT_BUF .req r1
OUTPUT_BUF .req r2
OUTPUT_ROW .req r3
NUM_ROWS .req r4
OUTPUT_BUF0 .req r5
OUTPUT_BUF1 .req r6
OUTPUT_BUF2 .req OUTPUT_BUF
RGB .req r7
Y .req r8
U .req r9
V .req r10
N .req ip
/* Load constants to d0, d1, d2, d3 */
adr ip, jsimd_\colorid\()_ycc_neon_consts
vld1.16 {d0, d1, d2, d3}, [ip, :128]
/* Save ARM registers and handle input arguments */
push {r4, r5, r6, r7, r8, r9, r10, lr}
ldr NUM_ROWS, [sp, #(4 * 8)]
ldr OUTPUT_BUF0, [OUTPUT_BUF]
ldr OUTPUT_BUF1, [OUTPUT_BUF, #4]
ldr OUTPUT_BUF2, [OUTPUT_BUF, #8]
.unreq OUTPUT_BUF
/* Save NEON registers */
vpush {d8-d15}
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
blt 9f
0:
ldr Y, [OUTPUT_BUF0, OUTPUT_ROW, lsl #2]
ldr U, [OUTPUT_BUF1, OUTPUT_ROW, lsl #2]
mov N, OUTPUT_WIDTH
ldr V, [OUTPUT_BUF2, OUTPUT_ROW, lsl #2]
add OUTPUT_ROW, OUTPUT_ROW, #1
ldr RGB, [INPUT_BUF], #4
/* Inner loop over pixels */
subs N, N, #8
blt 3f
do_load \bpp, 8
do_rgb_to_yuv_stage1
subs N, N, #8
blt 2f
1:
do_rgb_to_yuv_stage2_store_load_stage1
subs N, N, #8
bge 1b
2:
do_rgb_to_yuv_stage2
do_store 8
tst N, #7
beq 8f
3:
tst N, #4
beq 3f
do_load \bpp, 4
3:
tst N, #2
beq 4f
do_load \bpp, 2
4:
tst N, #1
beq 5f
do_load \bpp, 1
5:
do_rgb_to_yuv
tst N, #4
beq 6f
do_store 4
6:
tst N, #2
beq 7f
do_store 2
7:
tst N, #1
beq 8f
do_store 1
8:
subs NUM_ROWS, NUM_ROWS, #1
bgt 0b
9:
/* Restore all registers and return */
vpop {d8-d15}
pop {r4, r5, r6, r7, r8, r9, r10, pc}
.unreq OUTPUT_WIDTH
.unreq OUTPUT_ROW
.unreq INPUT_BUF
.unreq NUM_ROWS
.unreq OUTPUT_BUF0
.unreq OUTPUT_BUF1
.unreq OUTPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_rgb_to_yuv
.purgem do_rgb_to_yuv_stage1
.purgem do_rgb_to_yuv_stage2
.purgem do_rgb_to_yuv_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R G B */
generate_jsimd_rgb_ycc_convert_neon extrgb, 24, 0, 1, 2
generate_jsimd_rgb_ycc_convert_neon extbgr, 24, 2, 1, 0
generate_jsimd_rgb_ycc_convert_neon extrgbx, 32, 0, 1, 2
generate_jsimd_rgb_ycc_convert_neon extbgrx, 32, 2, 1, 0
generate_jsimd_rgb_ycc_convert_neon extxbgr, 32, 3, 2, 1
generate_jsimd_rgb_ycc_convert_neon extxrgb, 32, 1, 2, 3
.purgem do_load
.purgem do_store
/*****************************************************************************/
/*
* Load data into workspace, applying unsigned->signed conversion
*
* TODO: can be combined with 'jsimd_fdct_ifast_neon' to get
* rid of VST1.16 instructions
*/
asm_function jsimd_convsamp_neon
SAMPLE_DATA .req r0
START_COL .req r1
WORKSPACE .req r2
TMP1 .req r3
TMP2 .req r4
TMP3 .req r5
TMP4 .req ip
push {r4, r5}
vmov.u8 d0, #128
ldmia SAMPLE_DATA!, {TMP1, TMP2, TMP3, TMP4}
add TMP1, TMP1, START_COL
add TMP2, TMP2, START_COL
add TMP3, TMP3, START_COL
add TMP4, TMP4, START_COL
vld1.8 {d16}, [TMP1]
vsubl.u8 q8, d16, d0
vld1.8 {d18}, [TMP2]
vsubl.u8 q9, d18, d0
vld1.8 {d20}, [TMP3]
vsubl.u8 q10, d20, d0
vld1.8 {d22}, [TMP4]
ldmia SAMPLE_DATA!, {TMP1, TMP2, TMP3, TMP4}
vsubl.u8 q11, d22, d0
vst1.16 {d16, d17, d18, d19}, [WORKSPACE, :128]!
add TMP1, TMP1, START_COL
add TMP2, TMP2, START_COL
vst1.16 {d20, d21, d22, d23}, [WORKSPACE, :128]!
add TMP3, TMP3, START_COL
add TMP4, TMP4, START_COL
vld1.8 {d24}, [TMP1]
vsubl.u8 q12, d24, d0
vld1.8 {d26}, [TMP2]
vsubl.u8 q13, d26, d0
vld1.8 {d28}, [TMP3]
vsubl.u8 q14, d28, d0
vld1.8 {d30}, [TMP4]
vsubl.u8 q15, d30, d0
vst1.16 {d24, d25, d26, d27}, [WORKSPACE, :128]!
vst1.16 {d28, d29, d30, d31}, [WORKSPACE, :128]!
pop {r4, r5}
bx lr
.unreq SAMPLE_DATA
.unreq START_COL
.unreq WORKSPACE
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
/*****************************************************************************/
/*
* jsimd_fdct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the forward DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_fdct_ifast'
* function from jfdctfst.c
*
* TODO: can be combined with 'jsimd_convsamp_neon' to get
* rid of a bunch of VLD1.16 instructions
*/
#define XFIX_0_382683433 d0[0]
#define XFIX_0_541196100 d0[1]
#define XFIX_0_707106781 d0[2]
#define XFIX_1_306562965 d0[3]
.balign 16
jsimd_fdct_ifast_neon_consts:
.short (98 * 128) /* XFIX_0_382683433 */
.short (139 * 128) /* XFIX_0_541196100 */
.short (181 * 128) /* XFIX_0_707106781 */
.short (334 * 128 - 256 * 128) /* XFIX_1_306562965 */
asm_function jsimd_fdct_ifast_neon
DATA .req r0
TMP .req ip
vpush {d8-d15}
/* Load constants */
adr TMP, jsimd_fdct_ifast_neon_consts
vld1.16 {d0}, [TMP, :64]
/* Load all DATA into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 | q8
* 1 | d18 | d19 | q9
* 2 | d20 | d21 | q10
* 3 | d22 | d23 | q11
* 4 | d24 | d25 | q12
* 5 | d26 | d27 | q13
* 6 | d28 | d29 | q14
* 7 | d30 | d31 | q15
*/
vld1.16 {d16, d17, d18, d19}, [DATA, :128]!
vld1.16 {d20, d21, d22, d23}, [DATA, :128]!
vld1.16 {d24, d25, d26, d27}, [DATA, :128]!
vld1.16 {d28, d29, d30, d31}, [DATA, :128]
sub DATA, DATA, #(128 - 32)
mov TMP, #2
1:
/* Transpose */
vtrn.16 q12, q13
vtrn.16 q10, q11
vtrn.16 q8, q9
vtrn.16 q14, q15
vtrn.32 q9, q11
vtrn.32 q13, q15
vtrn.32 q8, q10
vtrn.32 q12, q14
vswp d30, d23
vswp d24, d17
vswp d26, d19
/* 1-D FDCT */
vadd.s16 q2, q11, q12
vswp d28, d21
vsub.s16 q12, q11, q12
vsub.s16 q6, q10, q13
vadd.s16 q10, q10, q13
vsub.s16 q7, q9, q14
vadd.s16 q9, q9, q14
vsub.s16 q1, q8, q15
vadd.s16 q8, q8, q15
vsub.s16 q4, q9, q10
vsub.s16 q5, q8, q2
vadd.s16 q3, q9, q10
vadd.s16 q4, q4, q5
vadd.s16 q2, q8, q2
vqdmulh.s16 q4, q4, XFIX_0_707106781
vadd.s16 q11, q12, q6
vadd.s16 q8, q2, q3
vsub.s16 q12, q2, q3
vadd.s16 q3, q6, q7
vadd.s16 q7, q7, q1
vqdmulh.s16 q3, q3, XFIX_0_707106781
vsub.s16 q6, q11, q7
vadd.s16 q10, q5, q4
vqdmulh.s16 q6, q6, XFIX_0_382683433
vsub.s16 q14, q5, q4
vqdmulh.s16 q11, q11, XFIX_0_541196100
vqdmulh.s16 q5, q7, XFIX_1_306562965
vadd.s16 q4, q1, q3
vsub.s16 q3, q1, q3
vadd.s16 q7, q7, q6
vadd.s16 q11, q11, q6
vadd.s16 q7, q7, q5
vadd.s16 q13, q3, q11
vsub.s16 q11, q3, q11
vadd.s16 q9, q4, q7
vsub.s16 q15, q4, q7
subs TMP, TMP, #1
bne 1b
/* store results */
vst1.16 {d16, d17, d18, d19}, [DATA, :128]!
vst1.16 {d20, d21, d22, d23}, [DATA, :128]!
vst1.16 {d24, d25, d26, d27}, [DATA, :128]!
vst1.16 {d28, d29, d30, d31}, [DATA, :128]
vpop {d8-d15}
bx lr
.unreq DATA
.unreq TMP
/*****************************************************************************/
/*
* GLOBAL(void)
* jsimd_quantize_neon (JCOEFPTR coef_block, DCTELEM *divisors,
* DCTELEM *workspace);
*
* Note: the code uses 2 stage pipelining in order to improve instructions
* scheduling and eliminate stalls (this provides ~15% better
* performance for this function on both ARM Cortex-A8 and
* ARM Cortex-A9 when compared to the non-pipelined variant).
* The instructions which belong to the second stage use different
* indentation for better readiability.
*/
asm_function jsimd_quantize_neon
COEF_BLOCK .req r0
DIVISORS .req r1
WORKSPACE .req r2
RECIPROCAL .req DIVISORS
CORRECTION .req r3
SHIFT .req ip
LOOP_COUNT .req r4
vld1.16 {d0, d1, d2, d3}, [WORKSPACE, :128]!
vabs.s16 q12, q0
add CORRECTION, DIVISORS, #(64 * 2)
add SHIFT, DIVISORS, #(64 * 6)
vld1.16 {d20, d21, d22, d23}, [CORRECTION, :128]!
vabs.s16 q13, q1
vld1.16 {d16, d17, d18, d19}, [RECIPROCAL, :128]!
vadd.u16 q12, q12, q10 /* add correction */
vadd.u16 q13, q13, q11
vmull.u16 q10, d24, d16 /* multiply by reciprocal */
vmull.u16 q11, d25, d17
vmull.u16 q8, d26, d18
vmull.u16 q9, d27, d19
vld1.16 {d24, d25, d26, d27}, [SHIFT, :128]!
vshrn.u32 d20, q10, #16
vshrn.u32 d21, q11, #16
vshrn.u32 d22, q8, #16
vshrn.u32 d23, q9, #16
vneg.s16 q12, q12
vneg.s16 q13, q13
vshr.s16 q2, q0, #15 /* extract sign */
vshr.s16 q3, q1, #15
vshl.u16 q14, q10, q12 /* shift */
vshl.u16 q15, q11, q13
push {r4, r5}
mov LOOP_COUNT, #3
1:
vld1.16 {d0, d1, d2, d3}, [WORKSPACE, :128]!
veor.u16 q14, q14, q2 /* restore sign */
vabs.s16 q12, q0
vld1.16 {d20, d21, d22, d23}, [CORRECTION, :128]!
vabs.s16 q13, q1
veor.u16 q15, q15, q3
vld1.16 {d16, d17, d18, d19}, [RECIPROCAL, :128]!
vadd.u16 q12, q12, q10 /* add correction */
vadd.u16 q13, q13, q11
vmull.u16 q10, d24, d16 /* multiply by reciprocal */
vmull.u16 q11, d25, d17
vmull.u16 q8, d26, d18
vmull.u16 q9, d27, d19
vsub.u16 q14, q14, q2
vld1.16 {d24, d25, d26, d27}, [SHIFT, :128]!
vsub.u16 q15, q15, q3
vshrn.u32 d20, q10, #16
vshrn.u32 d21, q11, #16
vst1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]!
vshrn.u32 d22, q8, #16
vshrn.u32 d23, q9, #16
vneg.s16 q12, q12
vneg.s16 q13, q13
vshr.s16 q2, q0, #15 /* extract sign */
vshr.s16 q3, q1, #15
vshl.u16 q14, q10, q12 /* shift */
vshl.u16 q15, q11, q13
subs LOOP_COUNT, LOOP_COUNT, #1
bne 1b
pop {r4, r5}
veor.u16 q14, q14, q2 /* restore sign */
veor.u16 q15, q15, q3
vsub.u16 q14, q14, q2
vsub.u16 q15, q15, q3
vst1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]!
bx lr /* return */
.unreq COEF_BLOCK
.unreq DIVISORS
.unreq WORKSPACE
.unreq RECIPROCAL
.unreq CORRECTION
.unreq SHIFT
.unreq LOOP_COUNT
/*****************************************************************************/
/*
* GLOBAL(void)
* jsimd_h2v1_fancy_upsample_neon (int max_v_samp_factor,
* JDIMENSION downsampled_width,
* JSAMPARRAY input_data,
* JSAMPARRAY *output_data_ptr);
*
* Note: the use of unaligned writes is the main remaining bottleneck in
* this code, which can be potentially solved to get up to tens
* of percents performance improvement on Cortex-A8/Cortex-A9.
*/
/*
* Upsample 16 source pixels to 32 destination pixels. The new 16 source
* pixels are loaded to q0. The previous 16 source pixels are in q1. The
* shifted-by-one source pixels are constructed in q2 by using q0 and q1.
* Register d28 is used for multiplication by 3. Register q15 is used
* for adding +1 bias.
*/
.macro upsample16 OUTPTR, INPTR
vld1.8 {q0}, [\INPTR]!
vmovl.u8 q8, d0
vext.8 q2, q1, q0, #15
vmovl.u8 q9, d1
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d0, d28
vmlal.u8 q11, d1, d28
vmov q1, q0 /* backup source pixels to q1 */
vrshrn.u16 d6, q8, #2
vrshrn.u16 d7, q9, #2
vshrn.u16 d8, q10, #2
vshrn.u16 d9, q11, #2
vst2.8 {d6, d7, d8, d9}, [\OUTPTR]!
.endm
/*
* Upsample 32 source pixels to 64 destination pixels. Compared to 'usample16'
* macro, the roles of q0 and q1 registers are reversed for even and odd
* groups of 16 pixels, that's why "vmov q1, q0" instructions are not needed.
* Also this unrolling allows to reorder loads and stores to compensate
* multiplication latency and reduce stalls.
*/
.macro upsample32 OUTPTR, INPTR
/* even 16 pixels group */
vld1.8 {q0}, [\INPTR]!
vmovl.u8 q8, d0
vext.8 q2, q1, q0, #15
vmovl.u8 q9, d1
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d0, d28
vmlal.u8 q11, d1, d28
/* odd 16 pixels group */
vld1.8 {q1}, [\INPTR]!
vrshrn.u16 d6, q8, #2
vrshrn.u16 d7, q9, #2
vshrn.u16 d8, q10, #2
vshrn.u16 d9, q11, #2
vmovl.u8 q8, d2
vext.8 q2, q0, q1, #15
vmovl.u8 q9, d3
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d2, d28
vmlal.u8 q11, d3, d28
vst2.8 {d6, d7, d8, d9}, [\OUTPTR]!
vrshrn.u16 d6, q8, #2
vrshrn.u16 d7, q9, #2
vshrn.u16 d8, q10, #2
vshrn.u16 d9, q11, #2
vst2.8 {d6, d7, d8, d9}, [\OUTPTR]!
.endm
/*
* Upsample a row of WIDTH pixels from INPTR to OUTPTR.
*/
.macro upsample_row OUTPTR, INPTR, WIDTH, TMP1
/* special case for the first and last pixels */
sub \WIDTH, \WIDTH, #1
add \OUTPTR, \OUTPTR, #1
ldrb \TMP1, [\INPTR, \WIDTH]
strb \TMP1, [\OUTPTR, \WIDTH, asl #1]
ldrb \TMP1, [\INPTR], #1
strb \TMP1, [\OUTPTR, #-1]
vmov.8 d3[7], \TMP1
subs \WIDTH, \WIDTH, #32
blt 5f
0: /* process 32 pixels per iteration */
upsample32 \OUTPTR, \INPTR
subs \WIDTH, \WIDTH, #32
bge 0b
5:
adds \WIDTH, \WIDTH, #16
blt 1f
0: /* process 16 pixels if needed */
upsample16 \OUTPTR, \INPTR
subs \WIDTH, \WIDTH, #16
1:
adds \WIDTH, \WIDTH, #16
beq 9f
/* load the remaining 1-15 pixels */
add \INPTR, \INPTR, \WIDTH
tst \WIDTH, #1
beq 2f
sub \INPTR, \INPTR, #1
vld1.8 {d0[0]}, [\INPTR]
2:
tst \WIDTH, #2
beq 2f
vext.8 d0, d0, d0, #6
sub \INPTR, \INPTR, #1
vld1.8 {d0[1]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[0]}, [\INPTR]
2:
tst \WIDTH, #4
beq 2f
vrev64.32 d0, d0
sub \INPTR, \INPTR, #1
vld1.8 {d0[3]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[2]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[1]}, [\INPTR]
sub \INPTR, \INPTR, #1
vld1.8 {d0[0]}, [\INPTR]
2:
tst \WIDTH, #8
beq 2f
vmov d1, d0
sub \INPTR, \INPTR, #8
vld1.8 {d0}, [\INPTR]
2: /* upsample the remaining pixels */
vmovl.u8 q8, d0
vext.8 q2, q1, q0, #15
vmovl.u8 q9, d1
vaddw.u8 q10, q15, d4
vaddw.u8 q11, q15, d5
vmlal.u8 q8, d4, d28
vmlal.u8 q9, d5, d28
vmlal.u8 q10, d0, d28
vmlal.u8 q11, d1, d28
vrshrn.u16 d10, q8, #2
vrshrn.u16 d12, q9, #2
vshrn.u16 d11, q10, #2
vshrn.u16 d13, q11, #2
vzip.8 d10, d11
vzip.8 d12, d13
/* store the remaining pixels */
tst \WIDTH, #8
beq 2f
vst1.8 {d10, d11}, [\OUTPTR]!
vmov q5, q6
2:
tst \WIDTH, #4
beq 2f
vst1.8 {d10}, [\OUTPTR]!
vmov d10, d11
2:
tst \WIDTH, #2
beq 2f
vst1.8 {d10[0]}, [\OUTPTR]!
vst1.8 {d10[1]}, [\OUTPTR]!
vst1.8 {d10[2]}, [\OUTPTR]!
vst1.8 {d10[3]}, [\OUTPTR]!
vext.8 d10, d10, d10, #4
2:
tst \WIDTH, #1
beq 2f
vst1.8 {d10[0]}, [\OUTPTR]!
vst1.8 {d10[1]}, [\OUTPTR]!
2:
9:
.endm
asm_function jsimd_h2v1_fancy_upsample_neon
MAX_V_SAMP_FACTOR .req r0
DOWNSAMPLED_WIDTH .req r1
INPUT_DATA .req r2
OUTPUT_DATA_PTR .req r3
OUTPUT_DATA .req OUTPUT_DATA_PTR
OUTPTR .req r4
INPTR .req r5
WIDTH .req ip
TMP .req lr
push {r4, r5, r6, lr}
vpush {d8-d15}
ldr OUTPUT_DATA, [OUTPUT_DATA_PTR]
cmp MAX_V_SAMP_FACTOR, #0
ble 99f
/* initialize constants */
vmov.u8 d28, #3
vmov.u16 q15, #1
11:
ldr INPTR, [INPUT_DATA], #4
ldr OUTPTR, [OUTPUT_DATA], #4
mov WIDTH, DOWNSAMPLED_WIDTH
upsample_row OUTPTR, INPTR, WIDTH, TMP
subs MAX_V_SAMP_FACTOR, MAX_V_SAMP_FACTOR, #1
bgt 11b
99:
vpop {d8-d15}
pop {r4, r5, r6, pc}
.unreq MAX_V_SAMP_FACTOR
.unreq DOWNSAMPLED_WIDTH
.unreq INPUT_DATA
.unreq OUTPUT_DATA_PTR
.unreq OUTPUT_DATA
.unreq OUTPTR
.unreq INPTR
.unreq WIDTH
.unreq TMP
.purgem upsample16
.purgem upsample32
.purgem upsample_row
/*****************************************************************************/
/*
* GLOBAL(JOCTET*)
* jsimd_huff_encode_one_block (working_state *state, JOCTET *buffer,
* JCOEFPTR block, int last_dc_val,
* c_derived_tbl *dctbl, c_derived_tbl *actbl)
*
*/
.macro emit_byte BUFFER, PUT_BUFFER, PUT_BITS, ZERO, TMP
sub \PUT_BITS, \PUT_BITS, #0x8
lsr \TMP, \PUT_BUFFER, \PUT_BITS
uxtb \TMP, \TMP
strb \TMP, [\BUFFER, #1]!
cmp \TMP, #0xff
/*it eq*/
strbeq \ZERO, [\BUFFER, #1]!
.endm
.macro put_bits PUT_BUFFER, PUT_BITS, CODE, SIZE
/*lsl \PUT_BUFFER, \PUT_BUFFER, \SIZE*/
add \PUT_BITS, \SIZE
/*orr \PUT_BUFFER, \PUT_BUFFER, \CODE*/
orr \PUT_BUFFER, \CODE, \PUT_BUFFER, lsl \SIZE
.endm
.macro checkbuf15 BUFFER, PUT_BUFFER, PUT_BITS, ZERO, TMP
cmp \PUT_BITS, #0x10
blt 15f
eor \ZERO, \ZERO, \ZERO
emit_byte \BUFFER, \PUT_BUFFER, \PUT_BITS, \ZERO, \TMP
emit_byte \BUFFER, \PUT_BUFFER, \PUT_BITS, \ZERO, \TMP
15:
.endm
.balign 16
jsimd_huff_encode_one_block_neon_consts:
.byte 0x01
.byte 0x02
.byte 0x04
.byte 0x08
.byte 0x10
.byte 0x20
.byte 0x40
.byte 0x80
asm_function jsimd_huff_encode_one_block_neon
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
add r7, sp, #0x1c
sub r4, sp, #0x40
bfc r4, #0, #5
mov sp, r4 /* align sp on 32 bytes */
vst1.64 {d8, d9, d10, d11}, [r4, :128]!
vst1.64 {d12, d13, d14, d15}, [r4, :128]
sub sp, #0x140 /* reserve 320 bytes */
str r0, [sp, #0x18] /* working state > sp + Ox18 */
add r4, sp, #0x20 /* r4 = t1 */
ldr lr, [r7, #0x8] /* lr = dctbl */
sub r10, r1, #0x1 /* r10=buffer-- */
ldrsh r1, [r2]
mov r9, #0x10
mov r8, #0x1
adr r5, jsimd_huff_encode_one_block_neon_consts
/* prepare data */
vld1.8 {d26}, [r5, :64]
veor q8, q8, q8
veor q9, q9, q9
vdup.16 q14, r9
vdup.16 q15, r8
veor q10, q10, q10
veor q11, q11, q11
sub r1, r1, r3
add r9, r2, #0x22
add r8, r2, #0x18
add r3, r2, #0x36
vmov.16 d0[0], r1
vld1.16 {d2[0]}, [r9, :16]
vld1.16 {d4[0]}, [r8, :16]
vld1.16 {d6[0]}, [r3, :16]
add r1, r2, #0x2
add r9, r2, #0x30
add r8, r2, #0x26
add r3, r2, #0x28
vld1.16 {d0[1]}, [r1, :16]
vld1.16 {d2[1]}, [r9, :16]
vld1.16 {d4[1]}, [r8, :16]
vld1.16 {d6[1]}, [r3, :16]
add r1, r2, #0x10
add r9, r2, #0x40
add r8, r2, #0x34
add r3, r2, #0x1a
vld1.16 {d0[2]}, [r1, :16]
vld1.16 {d2[2]}, [r9, :16]
vld1.16 {d4[2]}, [r8, :16]
vld1.16 {d6[2]}, [r3, :16]
add r1, r2, #0x20
add r9, r2, #0x32
add r8, r2, #0x42
add r3, r2, #0xc
vld1.16 {d0[3]}, [r1, :16]
vld1.16 {d2[3]}, [r9, :16]
vld1.16 {d4[3]}, [r8, :16]
vld1.16 {d6[3]}, [r3, :16]
add r1, r2, #0x12
add r9, r2, #0x24
add r8, r2, #0x50
add r3, r2, #0xe
vld1.16 {d1[0]}, [r1, :16]
vld1.16 {d3[0]}, [r9, :16]
vld1.16 {d5[0]}, [r8, :16]
vld1.16 {d7[0]}, [r3, :16]
add r1, r2, #0x4
add r9, r2, #0x16
add r8, r2, #0x60
add r3, r2, #0x1c
vld1.16 {d1[1]}, [r1, :16]
vld1.16 {d3[1]}, [r9, :16]
vld1.16 {d5[1]}, [r8, :16]
vld1.16 {d7[1]}, [r3, :16]
add r1, r2, #0x6
add r9, r2, #0x8
add r8, r2, #0x52
add r3, r2, #0x2a
vld1.16 {d1[2]}, [r1, :16]
vld1.16 {d3[2]}, [r9, :16]
vld1.16 {d5[2]}, [r8, :16]
vld1.16 {d7[2]}, [r3, :16]
add r1, r2, #0x14
add r9, r2, #0xa
add r8, r2, #0x44
add r3, r2, #0x38
vld1.16 {d1[3]}, [r1, :16]
vld1.16 {d3[3]}, [r9, :16]
vld1.16 {d5[3]}, [r8, :16]
vld1.16 {d7[3]}, [r3, :16]
vcgt.s16 q8, q8, q0
vcgt.s16 q9, q9, q1
vcgt.s16 q10, q10, q2
vcgt.s16 q11, q11, q3
vabs.s16 q0, q0
vabs.s16 q1, q1
vabs.s16 q2, q2
vabs.s16 q3, q3
veor q8, q8, q0
veor q9, q9, q1
veor q10, q10, q2
veor q11, q11, q3
add r9, r4, #0x20
add r8, r4, #0x80
add r3, r4, #0xa0
vclz.i16 q0, q0
vclz.i16 q1, q1
vclz.i16 q2, q2
vclz.i16 q3, q3
vsub.i16 q0, q14, q0
vsub.i16 q1, q14, q1
vsub.i16 q2, q14, q2
vsub.i16 q3, q14, q3
vst1.16 {d0, d1, d2, d3}, [r4, :256]
vst1.16 {d4, d5, d6, d7}, [r9, :256]
vshl.s16 q0, q15, q0
vshl.s16 q1, q15, q1
vshl.s16 q2, q15, q2
vshl.s16 q3, q15, q3
vsub.i16 q0, q0, q15
vsub.i16 q1, q1, q15
vsub.i16 q2, q2, q15
vsub.i16 q3, q3, q15
vand q8, q8, q0
vand q9, q9, q1
vand q10, q10, q2
vand q11, q11, q3
vst1.16 {d16, d17, d18, d19}, [r8, :256]
vst1.16 {d20, d21, d22, d23}, [r3, :256]
add r1, r2, #0x46
add r9, r2, #0x3a
add r8, r2, #0x74
add r3, r2, #0x6a
vld1.16 {d8[0]}, [r1, :16]
vld1.16 {d10[0]}, [r9, :16]
vld1.16 {d12[0]}, [r8, :16]
vld1.16 {d14[0]}, [r3, :16]
veor q8, q8, q8
veor q9, q9, q9
veor q10, q10, q10
veor q11, q11, q11
add r1, r2, #0x54
add r9, r2, #0x2c
add r8, r2, #0x76
add r3, r2, #0x78
vld1.16 {d8[1]}, [r1, :16]
vld1.16 {d10[1]}, [r9, :16]
vld1.16 {d12[1]}, [r8, :16]
vld1.16 {d14[1]}, [r3, :16]
add r1, r2, #0x62
add r9, r2, #0x1e
add r8, r2, #0x68
add r3, r2, #0x7a
vld1.16 {d8[2]}, [r1, :16]
vld1.16 {d10[2]}, [r9, :16]
vld1.16 {d12[2]}, [r8, :16]
vld1.16 {d14[2]}, [r3, :16]
add r1, r2, #0x70
add r9, r2, #0x2e
add r8, r2, #0x5a
add r3, r2, #0x6c
vld1.16 {d8[3]}, [r1, :16]
vld1.16 {d10[3]}, [r9, :16]
vld1.16 {d12[3]}, [r8, :16]
vld1.16 {d14[3]}, [r3, :16]
add r1, r2, #0x72
add r9, r2, #0x3c
add r8, r2, #0x4c
add r3, r2, #0x5e
vld1.16 {d9[0]}, [r1, :16]
vld1.16 {d11[0]}, [r9, :16]
vld1.16 {d13[0]}, [r8, :16]
vld1.16 {d15[0]}, [r3, :16]
add r1, r2, #0x64
add r9, r2, #0x4a
add r8, r2, #0x3e
add r3, r2, #0x6e
vld1.16 {d9[1]}, [r1, :16]
vld1.16 {d11[1]}, [r9, :16]
vld1.16 {d13[1]}, [r8, :16]
vld1.16 {d15[1]}, [r3, :16]
add r1, r2, #0x56
add r9, r2, #0x58
add r8, r2, #0x4e
add r3, r2, #0x7c
vld1.16 {d9[2]}, [r1, :16]
vld1.16 {d11[2]}, [r9, :16]
vld1.16 {d13[2]}, [r8, :16]
vld1.16 {d15[2]}, [r3, :16]
add r1, r2, #0x48
add r9, r2, #0x66
add r8, r2, #0x5c
add r3, r2, #0x7e
vld1.16 {d9[3]}, [r1, :16]
vld1.16 {d11[3]}, [r9, :16]
vld1.16 {d13[3]}, [r8, :16]
vld1.16 {d15[3]}, [r3, :16]
vcgt.s16 q8, q8, q4
vcgt.s16 q9, q9, q5
vcgt.s16 q10, q10, q6
vcgt.s16 q11, q11, q7
vabs.s16 q4, q4
vabs.s16 q5, q5
vabs.s16 q6, q6
vabs.s16 q7, q7
veor q8, q8, q4
veor q9, q9, q5
veor q10, q10, q6
veor q11, q11, q7
add r1, r4, #0x40
add r9, r4, #0x60
add r8, r4, #0xc0
add r3, r4, #0xe0
vclz.i16 q4, q4
vclz.i16 q5, q5
vclz.i16 q6, q6
vclz.i16 q7, q7
vsub.i16 q4, q14, q4
vsub.i16 q5, q14, q5
vsub.i16 q6, q14, q6
vsub.i16 q7, q14, q7
vst1.16 {d8, d9, d10, d11}, [r1, :256]
vst1.16 {d12, d13, d14, d15}, [r9, :256]
vshl.s16 q4, q15, q4
vshl.s16 q5, q15, q5
vshl.s16 q6, q15, q6
vshl.s16 q7, q15, q7
vsub.i16 q4, q4, q15
vsub.i16 q5, q5, q15
vsub.i16 q6, q6, q15
vsub.i16 q7, q7, q15
vand q8, q8, q4
vand q9, q9, q5
vand q10, q10, q6
vand q11, q11, q7
vst1.16 {d16, d17, d18, d19}, [r8, :256]
vst1.16 {d20, d21, d22, d23}, [r3, :256]
ldr r12, [r7, #0xc] /* r12 = actbl */
add r1, lr, #0x400 /* r1 = dctbl->ehufsi */
mov r9, r12 /* r9 = actbl */
add r6, r4, #0x80 /* r6 = t2 */
ldr r11, [r0, #0x8] /* r11 = put_buffer */
ldr r4, [r0, #0xc] /* r4 = put_bits */
ldrh r2, [r6, #-128] /* r2 = nbits */
ldrh r3, [r6] /* r3 = temp2 & (((JLONG) 1)<<nbits) - 1; */
ldr r0, [lr, r2, lsl #2]
ldrb r5, [r1, r2]
put_bits r11, r4, r0, r5
checkbuf15 r10, r11, r4, r5, r0
put_bits r11, r4, r3, r2
checkbuf15 r10, r11, r4, r5, r0
mov lr, r6 /* lr = t2 */
add r5, r9, #0x400 /* r5 = actbl->ehufsi */
ldrsb r6, [r5, #0xf0] /* r6 = actbl->ehufsi[0xf0] */
veor q8, q8, q8
vceq.i16 q0, q0, q8
vceq.i16 q1, q1, q8
vceq.i16 q2, q2, q8
vceq.i16 q3, q3, q8
vceq.i16 q4, q4, q8
vceq.i16 q5, q5, q8
vceq.i16 q6, q6, q8
vceq.i16 q7, q7, q8
vmovn.i16 d0, q0
vmovn.i16 d2, q1
vmovn.i16 d4, q2
vmovn.i16 d6, q3
vmovn.i16 d8, q4
vmovn.i16 d10, q5
vmovn.i16 d12, q6
vmovn.i16 d14, q7
vand d0, d0, d26
vand d2, d2, d26
vand d4, d4, d26
vand d6, d6, d26
vand d8, d8, d26
vand d10, d10, d26
vand d12, d12, d26
vand d14, d14, d26
vpadd.i8 d0, d0, d2
vpadd.i8 d4, d4, d6
vpadd.i8 d8, d8, d10
vpadd.i8 d12, d12, d14
vpadd.i8 d0, d0, d4
vpadd.i8 d8, d8, d12
vpadd.i8 d0, d0, d8
vmov.32 r1, d0[1]
vmov.32 r8, d0[0]
mvn r1, r1
mvn r8, r8
lsrs r1, r1, #0x1
rrx r8, r8 /* shift in last r1 bit while shifting out DC bit */
rbit r1, r1 /* r1 = index1 */
rbit r8, r8 /* r8 = index0 */
ldr r0, [r9, #0x3c0] /* r0 = actbl->ehufco[0xf0] */
str r1, [sp, #0x14] /* index1 > sp + 0x14 */
cmp r8, #0x0
beq 6f
1:
clz r2, r8
add lr, lr, r2, lsl #1
lsl r8, r8, r2
ldrh r1, [lr, #-126]
2:
cmp r2, #0x10
blt 3f
sub r2, r2, #0x10
put_bits r11, r4, r0, r6
cmp r4, #0x10
blt 2b
eor r3, r3, r3
emit_byte r10, r11, r4, r3, r12
emit_byte r10, r11, r4, r3, r12
b 2b
3:
add r2, r1, r2, lsl #4
ldrh r3, [lr, #2]!
ldr r12, [r9, r2, lsl #2]
ldrb r2, [r5, r2]
put_bits r11, r4, r12, r2
checkbuf15 r10, r11, r4, r2, r12
put_bits r11, r4, r3, r1
checkbuf15 r10, r11, r4, r2, r12
lsls r8, r8, #0x1
bne 1b
6:
add r12, sp, #0x20 /* r12 = t1 */
ldr r8, [sp, #0x14] /* r8 = index1 */
adds r12, #0xc0 /* r12 = t2 + (DCTSIZE2/2) */
cmp r8, #0x0
beq 6f
clz r2, r8
sub r12, r12, lr
lsl r8, r8, r2
add r2, r2, r12, lsr #1
add lr, lr, r2, lsl #1
b 7f
1:
clz r2, r8
add lr, lr, r2, lsl #1
lsl r8, r8, r2
7:
ldrh r1, [lr, #-126]
2:
cmp r2, #0x10
blt 3f
sub r2, r2, #0x10
put_bits r11, r4, r0, r6
cmp r4, #0x10
blt 2b
eor r3, r3, r3
emit_byte r10, r11, r4, r3, r12
emit_byte r10, r11, r4, r3, r12
b 2b
3:
add r2, r1, r2, lsl #4
ldrh r3, [lr, #2]!
ldr r12, [r9, r2, lsl #2]
ldrb r2, [r5, r2]
put_bits r11, r4, r12, r2
checkbuf15 r10, r11, r4, r2, r12
put_bits r11, r4, r3, r1
checkbuf15 r10, r11, r4, r2, r12
lsls r8, r8, #0x1
bne 1b
6:
add r0, sp, #0x20
add r0, #0xfe
cmp lr, r0
bhs 1f
ldr r1, [r9]
ldrb r0, [r5]
put_bits r11, r4, r1, r0
checkbuf15 r10, r11, r4, r0, r1
1:
ldr r12, [sp, #0x18]
str r11, [r12, #0x8]
str r4, [r12, #0xc]
add r0, r10, #0x1
add r4, sp, #0x140
vld1.64 {d8, d9, d10, d11}, [r4, :128]!
vld1.64 {d12, d13, d14, d15}, [r4, :128]
sub r4, r7, #0x1c
mov sp, r4
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
.purgem emit_byte
.purgem put_bits
.purgem checkbuf15
|
Akimeite/AndroidModule
| 143,313
|
uvccamera/src/main/jni/libjpeg-turbo-1.5.0/simd/jsimd_arm64_neon.S
|
/*
* ARMv8 NEON optimizations for libjpeg-turbo
*
* Copyright (C) 2009-2011, Nokia Corporation and/or its subsidiary(-ies).
* All Rights Reserved.
* Author: Siarhei Siamashka <siarhei.siamashka@nokia.com>
* Copyright (C) 2013-2014, Linaro Limited. All Rights Reserved.
* Author: Ragesh Radhakrishnan <ragesh.r@linaro.org>
* Copyright (C) 2014-2016, D. R. Commander. All Rights Reserved.
* Copyright (C) 2015-2016, Matthieu Darbois. All Rights Reserved.
* Copyright (C) 2016, Siarhei Siamashka. All Rights Reserved.
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#if defined(__linux__) && defined(__ELF__)
.section .note.GNU-stack, "", %progbits /* mark stack as non-executable */
#endif
.text
#define RESPECT_STRICT_ALIGNMENT 1
/*****************************************************************************/
/* Supplementary macro for setting function attributes */
.macro asm_function fname
#ifdef __APPLE__
.globl _\fname
_\fname:
#else
.global \fname
#ifdef __ELF__
.hidden \fname
.type \fname, %function
#endif
\fname:
#endif
.endm
/* Transpose elements of single 128 bit registers */
.macro transpose_single x0, x1, xi, xilen, literal
ins \xi\xilen[0], \x0\xilen[0]
ins \x1\xilen[0], \x0\xilen[1]
trn1 \x0\literal, \x0\literal, \x1\literal
trn2 \x1\literal, \xi\literal, \x1\literal
.endm
/* Transpose elements of 2 differnet registers */
.macro transpose x0, x1, xi, xilen, literal
mov \xi\xilen, \x0\xilen
trn1 \x0\literal, \x0\literal, \x1\literal
trn2 \x1\literal, \xi\literal, \x1\literal
.endm
/* Transpose a block of 4x4 coefficients in four 64-bit registers */
.macro transpose_4x4_32 x0, x0len, x1, x1len, x2, x2len, x3, x3len, xi, xilen
mov \xi\xilen, \x0\xilen
trn1 \x0\x0len, \x0\x0len, \x2\x2len
trn2 \x2\x2len, \xi\x0len, \x2\x2len
mov \xi\xilen, \x1\xilen
trn1 \x1\x1len, \x1\x1len, \x3\x3len
trn2 \x3\x3len, \xi\x1len, \x3\x3len
.endm
.macro transpose_4x4_16 x0, x0len, x1, x1len, x2, x2len, x3, x3len, xi, xilen
mov \xi\xilen, \x0\xilen
trn1 \x0\x0len, \x0\x0len, \x1\x1len
trn2 \x1\x2len, \xi\x0len, \x1\x2len
mov \xi\xilen, \x2\xilen
trn1 \x2\x2len, \x2\x2len, \x3\x3len
trn2 \x3\x2len, \xi\x1len, \x3\x3len
.endm
.macro transpose_4x4 x0, x1, x2, x3, x5
transpose_4x4_16 \x0, .4h, \x1, .4h, \x2, .4h, \x3, .4h, \x5, .16b
transpose_4x4_32 \x0, .2s, \x1, .2s, \x2, .2s, \x3, .2s, \x5, .16b
.endm
.macro transpose_8x8 l0, l1, l2, l3, l4, l5, l6, l7, t0, t1, t2, t3
trn1 \t0\().8h, \l0\().8h, \l1\().8h
trn1 \t1\().8h, \l2\().8h, \l3\().8h
trn1 \t2\().8h, \l4\().8h, \l5\().8h
trn1 \t3\().8h, \l6\().8h, \l7\().8h
trn2 \l1\().8h, \l0\().8h, \l1\().8h
trn2 \l3\().8h, \l2\().8h, \l3\().8h
trn2 \l5\().8h, \l4\().8h, \l5\().8h
trn2 \l7\().8h, \l6\().8h, \l7\().8h
trn1 \l4\().4s, \t2\().4s, \t3\().4s
trn2 \t3\().4s, \t2\().4s, \t3\().4s
trn1 \t2\().4s, \t0\().4s, \t1\().4s
trn2 \l2\().4s, \t0\().4s, \t1\().4s
trn1 \t0\().4s, \l1\().4s, \l3\().4s
trn2 \l3\().4s, \l1\().4s, \l3\().4s
trn2 \t1\().4s, \l5\().4s, \l7\().4s
trn1 \l5\().4s, \l5\().4s, \l7\().4s
trn2 \l6\().2d, \l2\().2d, \t3\().2d
trn1 \l0\().2d, \t2\().2d, \l4\().2d
trn1 \l1\().2d, \t0\().2d, \l5\().2d
trn2 \l7\().2d, \l3\().2d, \t1\().2d
trn1 \l2\().2d, \l2\().2d, \t3\().2d
trn2 \l4\().2d, \t2\().2d, \l4\().2d
trn1 \l3\().2d, \l3\().2d, \t1\().2d
trn2 \l5\().2d, \t0\().2d, \l5\().2d
.endm
#define CENTERJSAMPLE 128
/*****************************************************************************/
/*
* Perform dequantization and inverse DCT on one block of coefficients.
*
* GLOBAL(void)
* jsimd_idct_islow_neon (void *dct_table, JCOEFPTR coef_block,
* JSAMPARRAY output_buf, JDIMENSION output_col)
*/
#define CONST_BITS 13
#define PASS1_BITS 2
#define F_0_298 2446 /* FIX(0.298631336) */
#define F_0_390 3196 /* FIX(0.390180644) */
#define F_0_541 4433 /* FIX(0.541196100) */
#define F_0_765 6270 /* FIX(0.765366865) */
#define F_0_899 7373 /* FIX(0.899976223) */
#define F_1_175 9633 /* FIX(1.175875602) */
#define F_1_501 12299 /* FIX(1.501321110) */
#define F_1_847 15137 /* FIX(1.847759065) */
#define F_1_961 16069 /* FIX(1.961570560) */
#define F_2_053 16819 /* FIX(2.053119869) */
#define F_2_562 20995 /* FIX(2.562915447) */
#define F_3_072 25172 /* FIX(3.072711026) */
.balign 16
Ljsimd_idct_islow_neon_consts:
.short F_0_298
.short -F_0_390
.short F_0_541
.short F_0_765
.short - F_0_899
.short F_1_175
.short F_1_501
.short - F_1_847
.short - F_1_961
.short F_2_053
.short - F_2_562
.short F_3_072
.short 0 /* padding */
.short 0
.short 0
.short 0
#undef F_0_298
#undef F_0_390
#undef F_0_541
#undef F_0_765
#undef F_0_899
#undef F_1_175
#undef F_1_501
#undef F_1_847
#undef F_1_961
#undef F_2_053
#undef F_2_562
#undef F_3_072
#define XFIX_P_0_298 v0.h[0]
#define XFIX_N_0_390 v0.h[1]
#define XFIX_P_0_541 v0.h[2]
#define XFIX_P_0_765 v0.h[3]
#define XFIX_N_0_899 v0.h[4]
#define XFIX_P_1_175 v0.h[5]
#define XFIX_P_1_501 v0.h[6]
#define XFIX_N_1_847 v0.h[7]
#define XFIX_N_1_961 v1.h[0]
#define XFIX_P_2_053 v1.h[1]
#define XFIX_N_2_562 v1.h[2]
#define XFIX_P_3_072 v1.h[3]
asm_function jsimd_idct_islow_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x1
TMP3 .req x9
TMP4 .req x10
TMP5 .req x11
TMP6 .req x12
TMP7 .req x13
TMP8 .req x14
sub sp, sp, #64
adr x15, Ljsimd_idct_islow_neon_consts
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], #32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], #32
ld1 {v0.8h, v1.8h}, [x15]
ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [COEF_BLOCK], #64
ld1 {v18.8h, v19.8h, v20.8h, v21.8h}, [DCT_TABLE], #64
ld1 {v6.8h, v7.8h, v8.8h, v9.8h}, [COEF_BLOCK], #64
ld1 {v22.8h, v23.8h, v24.8h, v25.8h}, [DCT_TABLE], #64
cmeq v16.8h, v3.8h, #0
cmeq v26.8h, v4.8h, #0
cmeq v27.8h, v5.8h, #0
cmeq v28.8h, v6.8h, #0
cmeq v29.8h, v7.8h, #0
cmeq v30.8h, v8.8h, #0
cmeq v31.8h, v9.8h, #0
and v10.16b, v16.16b, v26.16b
and v11.16b, v27.16b, v28.16b
and v12.16b, v29.16b, v30.16b
and v13.16b, v31.16b, v10.16b
and v14.16b, v11.16b, v12.16b
mul v2.8h, v2.8h, v18.8h
and v15.16b, v13.16b, v14.16b
shl v10.8h, v2.8h, #(PASS1_BITS)
sqxtn v16.8b, v15.8h
mov TMP1, v16.d[0]
sub sp, sp, #64
mvn TMP2, TMP1
cbnz TMP2, 2f
/* case all AC coeffs are zeros */
dup v2.2d, v10.d[0]
dup v6.2d, v10.d[1]
mov v3.16b, v2.16b
mov v7.16b, v6.16b
mov v4.16b, v2.16b
mov v8.16b, v6.16b
mov v5.16b, v2.16b
mov v9.16b, v6.16b
1:
/* for this transpose, we should organise data like this:
* 00, 01, 02, 03, 40, 41, 42, 43
* 10, 11, 12, 13, 50, 51, 52, 53
* 20, 21, 22, 23, 60, 61, 62, 63
* 30, 31, 32, 33, 70, 71, 72, 73
* 04, 05, 06, 07, 44, 45, 46, 47
* 14, 15, 16, 17, 54, 55, 56, 57
* 24, 25, 26, 27, 64, 65, 66, 67
* 34, 35, 36, 37, 74, 75, 76, 77
*/
trn1 v28.8h, v2.8h, v3.8h
trn1 v29.8h, v4.8h, v5.8h
trn1 v30.8h, v6.8h, v7.8h
trn1 v31.8h, v8.8h, v9.8h
trn2 v16.8h, v2.8h, v3.8h
trn2 v17.8h, v4.8h, v5.8h
trn2 v18.8h, v6.8h, v7.8h
trn2 v19.8h, v8.8h, v9.8h
trn1 v2.4s, v28.4s, v29.4s
trn1 v6.4s, v30.4s, v31.4s
trn1 v3.4s, v16.4s, v17.4s
trn1 v7.4s, v18.4s, v19.4s
trn2 v4.4s, v28.4s, v29.4s
trn2 v8.4s, v30.4s, v31.4s
trn2 v5.4s, v16.4s, v17.4s
trn2 v9.4s, v18.4s, v19.4s
/* Even part: reverse the even part of the forward DCT. */
add v18.8h, v4.8h, v8.8h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*2], quantptr[DCTSIZE*2]) + DEQUANTIZE(inptr[DCTSIZE*6], quantptr[DCTSIZE*6]) */
add v22.8h, v2.8h, v6.8h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) + DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
smull2 v19.4s, v18.8h, XFIX_P_0_541 /* z1h z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
sub v26.8h, v2.8h, v6.8h /* z2 - z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) - DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
smull v18.4s, v18.4h, XFIX_P_0_541 /* z1l z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
mov v21.16b, v19.16b /* tmp3 = z1 */
mov v20.16b, v18.16b /* tmp3 = z1 */
smlal2 v19.4s, v8.8h, XFIX_N_1_847 /* tmp2h tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065); */
smlal v18.4s, v8.4h, XFIX_N_1_847 /* tmp2l tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065); */
sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
smlal2 v21.4s, v4.8h, XFIX_P_0_765 /* tmp3h tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865); */
smlal v20.4s, v4.4h, XFIX_P_0_765 /* tmp3l tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865); */
sshll v22.4s, v22.4h, #(CONST_BITS) /* tmp0l tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
sshll v26.4s, v26.4h, #(CONST_BITS) /* tmp1l tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
add v2.4s, v22.4s, v20.4s /* tmp10l tmp10 = tmp0 + tmp3; */
sub v6.4s, v22.4s, v20.4s /* tmp13l tmp13 = tmp0 - tmp3; */
add v8.4s, v26.4s, v18.4s /* tmp11l tmp11 = tmp1 + tmp2; */
sub v4.4s, v26.4s, v18.4s /* tmp12l tmp12 = tmp1 - tmp2; */
add v28.4s, v23.4s, v21.4s /* tmp10h tmp10 = tmp0 + tmp3; */
sub v31.4s, v23.4s, v21.4s /* tmp13h tmp13 = tmp0 - tmp3; */
add v29.4s, v27.4s, v19.4s /* tmp11h tmp11 = tmp1 + tmp2; */
sub v30.4s, v27.4s, v19.4s /* tmp12h tmp12 = tmp1 - tmp2; */
/* Odd part per figure 8; the matrix is unitary and hence its
* transpose is its inverse. i0..i3 are y7,y5,y3,y1 respectively.
*/
add v22.8h, v9.8h, v5.8h /* z3 = tmp0 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v24.8h, v7.8h, v3.8h /* z4 = tmp1 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v18.8h, v9.8h, v3.8h /* z1 = tmp0 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v20.8h, v7.8h, v5.8h /* z2 = tmp1 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v26.8h, v22.8h, v24.8h /* z5 = z3 + z4 */
smull2 v11.4s, v9.8h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
smull2 v13.4s, v7.8h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
smull2 v15.4s, v5.8h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
smull2 v17.4s, v3.8h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
smull2 v27.4s, v26.8h, XFIX_P_1_175 /* z5h z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
smull2 v23.4s, v22.8h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560) */
smull2 v25.4s, v24.8h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644) */
smull2 v19.4s, v18.8h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223) */
smull2 v21.4s, v20.8h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447) */
smull v10.4s, v9.4h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
smull v12.4s, v7.4h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
smull v14.4s, v5.4h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
smull v16.4s, v3.4h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
smull v26.4s, v26.4h, XFIX_P_1_175 /* z5l z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
smull v22.4s, v22.4h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560) */
smull v24.4s, v24.4h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644) */
smull v18.4s, v18.4h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223) */
smull v20.4s, v20.4h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447) */
add v23.4s, v23.4s, v27.4s /* z3 += z5 */
add v22.4s, v22.4s, v26.4s /* z3 += z5 */
add v25.4s, v25.4s, v27.4s /* z4 += z5 */
add v24.4s, v24.4s, v26.4s /* z4 += z5 */
add v11.4s, v11.4s, v19.4s /* tmp0 += z1 */
add v10.4s, v10.4s, v18.4s /* tmp0 += z1 */
add v13.4s, v13.4s, v21.4s /* tmp1 += z2 */
add v12.4s, v12.4s, v20.4s /* tmp1 += z2 */
add v15.4s, v15.4s, v21.4s /* tmp2 += z2 */
add v14.4s, v14.4s, v20.4s /* tmp2 += z2 */
add v17.4s, v17.4s, v19.4s /* tmp3 += z1 */
add v16.4s, v16.4s, v18.4s /* tmp3 += z1 */
add v11.4s, v11.4s, v23.4s /* tmp0 += z3 */
add v10.4s, v10.4s, v22.4s /* tmp0 += z3 */
add v13.4s, v13.4s, v25.4s /* tmp1 += z4 */
add v12.4s, v12.4s, v24.4s /* tmp1 += z4 */
add v17.4s, v17.4s, v25.4s /* tmp3 += z4 */
add v16.4s, v16.4s, v24.4s /* tmp3 += z4 */
add v15.4s, v15.4s, v23.4s /* tmp2 += z3 */
add v14.4s, v14.4s, v22.4s /* tmp2 += z3 */
/* Final output stage: inputs are tmp10..tmp13, tmp0..tmp3 */
add v18.4s, v2.4s, v16.4s /* tmp10 + tmp3 */
add v19.4s, v28.4s, v17.4s /* tmp10 + tmp3 */
sub v20.4s, v2.4s, v16.4s /* tmp10 - tmp3 */
sub v21.4s, v28.4s, v17.4s /* tmp10 - tmp3 */
add v22.4s, v8.4s, v14.4s /* tmp11 + tmp2 */
add v23.4s, v29.4s, v15.4s /* tmp11 + tmp2 */
sub v24.4s, v8.4s, v14.4s /* tmp11 - tmp2 */
sub v25.4s, v29.4s, v15.4s /* tmp11 - tmp2 */
add v26.4s, v4.4s, v12.4s /* tmp12 + tmp1 */
add v27.4s, v30.4s, v13.4s /* tmp12 + tmp1 */
sub v28.4s, v4.4s, v12.4s /* tmp12 - tmp1 */
sub v29.4s, v30.4s, v13.4s /* tmp12 - tmp1 */
add v14.4s, v6.4s, v10.4s /* tmp13 + tmp0 */
add v15.4s, v31.4s, v11.4s /* tmp13 + tmp0 */
sub v16.4s, v6.4s, v10.4s /* tmp13 - tmp0 */
sub v17.4s, v31.4s, v11.4s /* tmp13 - tmp0 */
shrn v2.4h, v18.4s, #16 /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS+PASS1_BITS+3) */
shrn v9.4h, v20.4s, #16 /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS+PASS1_BITS+3) */
shrn v3.4h, v22.4s, #16 /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS+PASS1_BITS+3) */
shrn v8.4h, v24.4s, #16 /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS+PASS1_BITS+3) */
shrn v4.4h, v26.4s, #16 /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS+PASS1_BITS+3) */
shrn v7.4h, v28.4s, #16 /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS+PASS1_BITS+3) */
shrn v5.4h, v14.4s, #16 /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS+PASS1_BITS+3) */
shrn v6.4h, v16.4s, #16 /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS+PASS1_BITS+3) */
shrn2 v2.8h, v19.4s, #16 /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS+PASS1_BITS+3) */
shrn2 v9.8h, v21.4s, #16 /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS+PASS1_BITS+3) */
shrn2 v3.8h, v23.4s, #16 /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS+PASS1_BITS+3) */
shrn2 v8.8h, v25.4s, #16 /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS+PASS1_BITS+3) */
shrn2 v4.8h, v27.4s, #16 /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS+PASS1_BITS+3) */
shrn2 v7.8h, v29.4s, #16 /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS+PASS1_BITS+3) */
shrn2 v5.8h, v15.4s, #16 /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS+PASS1_BITS+3) */
shrn2 v6.8h, v17.4s, #16 /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS+PASS1_BITS+3) */
movi v0.16b, #(CENTERJSAMPLE)
/* Prepare pointers (dual-issue with NEON instructions) */
ldp TMP1, TMP2, [OUTPUT_BUF], 16
sqrshrn v28.8b, v2.8h, #(CONST_BITS+PASS1_BITS+3-16)
ldp TMP3, TMP4, [OUTPUT_BUF], 16
sqrshrn v29.8b, v3.8h, #(CONST_BITS+PASS1_BITS+3-16)
add TMP1, TMP1, OUTPUT_COL
sqrshrn v30.8b, v4.8h, #(CONST_BITS+PASS1_BITS+3-16)
add TMP2, TMP2, OUTPUT_COL
sqrshrn v31.8b, v5.8h, #(CONST_BITS+PASS1_BITS+3-16)
add TMP3, TMP3, OUTPUT_COL
sqrshrn2 v28.16b, v6.8h, #(CONST_BITS+PASS1_BITS+3-16)
add TMP4, TMP4, OUTPUT_COL
sqrshrn2 v29.16b, v7.8h, #(CONST_BITS+PASS1_BITS+3-16)
ldp TMP5, TMP6, [OUTPUT_BUF], 16
sqrshrn2 v30.16b, v8.8h, #(CONST_BITS+PASS1_BITS+3-16)
ldp TMP7, TMP8, [OUTPUT_BUF], 16
sqrshrn2 v31.16b, v9.8h, #(CONST_BITS+PASS1_BITS+3-16)
add TMP5, TMP5, OUTPUT_COL
add v16.16b, v28.16b, v0.16b
add TMP6, TMP6, OUTPUT_COL
add v18.16b, v29.16b, v0.16b
add TMP7, TMP7, OUTPUT_COL
add v20.16b, v30.16b, v0.16b
add TMP8, TMP8, OUTPUT_COL
add v22.16b, v31.16b, v0.16b
/* Transpose the final 8-bit samples */
trn1 v28.16b, v16.16b, v18.16b
trn1 v30.16b, v20.16b, v22.16b
trn2 v29.16b, v16.16b, v18.16b
trn2 v31.16b, v20.16b, v22.16b
trn1 v16.8h, v28.8h, v30.8h
trn2 v18.8h, v28.8h, v30.8h
trn1 v20.8h, v29.8h, v31.8h
trn2 v22.8h, v29.8h, v31.8h
uzp1 v28.4s, v16.4s, v18.4s
uzp2 v30.4s, v16.4s, v18.4s
uzp1 v29.4s, v20.4s, v22.4s
uzp2 v31.4s, v20.4s, v22.4s
/* Store results to the output buffer */
st1 {v28.d}[0], [TMP1]
st1 {v29.d}[0], [TMP2]
st1 {v28.d}[1], [TMP3]
st1 {v29.d}[1], [TMP4]
st1 {v30.d}[0], [TMP5]
st1 {v31.d}[0], [TMP6]
st1 {v30.d}[1], [TMP7]
st1 {v31.d}[1], [TMP8]
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], #32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], #32
blr x30
.balign 16
2:
mul v3.8h, v3.8h, v19.8h
mul v4.8h, v4.8h, v20.8h
mul v5.8h, v5.8h, v21.8h
add TMP4, xzr, TMP2, LSL #32
mul v6.8h, v6.8h, v22.8h
mul v7.8h, v7.8h, v23.8h
adds TMP3, xzr, TMP2, LSR #32
mul v8.8h, v8.8h, v24.8h
mul v9.8h, v9.8h, v25.8h
b.ne 3f
/* Right AC coef is zero */
dup v15.2d, v10.d[1]
/* Even part: reverse the even part of the forward DCT. */
add v18.4h, v4.4h, v8.4h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*2], quantptr[DCTSIZE*2]) + DEQUANTIZE(inptr[DCTSIZE*6], quantptr[DCTSIZE*6]) */
add v22.4h, v2.4h, v6.4h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) + DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
sub v26.4h, v2.4h, v6.4h /* z2 - z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) - DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
smull v18.4s, v18.4h, XFIX_P_0_541 /* z1l z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
sshll v22.4s, v22.4h, #(CONST_BITS) /* tmp0l tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
mov v20.16b, v18.16b /* tmp3 = z1 */
sshll v26.4s, v26.4h, #(CONST_BITS) /* tmp1l tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
smlal v18.4s, v8.4h, XFIX_N_1_847 /* tmp2l tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065); */
smlal v20.4s, v4.4h, XFIX_P_0_765 /* tmp3l tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865); */
add v2.4s, v22.4s, v20.4s /* tmp10l tmp10 = tmp0 + tmp3; */
sub v6.4s, v22.4s, v20.4s /* tmp13l tmp13 = tmp0 - tmp3; */
add v8.4s, v26.4s, v18.4s /* tmp11l tmp11 = tmp1 + tmp2; */
sub v4.4s, v26.4s, v18.4s /* tmp12l tmp12 = tmp1 - tmp2; */
/* Odd part per figure 8; the matrix is unitary and hence its
* transpose is its inverse. i0..i3 are y7,y5,y3,y1 respectively.
*/
add v22.4h, v9.4h, v5.4h /* z3 = tmp0 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v24.4h, v7.4h, v3.4h /* z4 = tmp1 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v18.4h, v9.4h, v3.4h /* z1 = tmp0 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v20.4h, v7.4h, v5.4h /* z2 = tmp1 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v26.4h, v22.4h, v24.4h /* z5 = z3 + z4 */
smull v10.4s, v9.4h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
smull v12.4s, v7.4h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
smull v14.4s, v5.4h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
smull v16.4s, v3.4h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
smull v26.4s, v26.4h, XFIX_P_1_175 /* z5l z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
smull v22.4s, v22.4h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560) */
smull v24.4s, v24.4h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644) */
smull v18.4s, v18.4h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223) */
smull v20.4s, v20.4h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447) */
add v22.4s, v22.4s, v26.4s /* z3 += z5 */
add v24.4s, v24.4s, v26.4s /* z4 += z5 */
add v10.4s, v10.4s, v18.4s /* tmp0 += z1 */
add v12.4s, v12.4s, v20.4s /* tmp1 += z2 */
add v14.4s, v14.4s, v20.4s /* tmp2 += z2 */
add v16.4s, v16.4s, v18.4s /* tmp3 += z1 */
add v10.4s, v10.4s, v22.4s /* tmp0 += z3 */
add v12.4s, v12.4s, v24.4s /* tmp1 += z4 */
add v16.4s, v16.4s, v24.4s /* tmp3 += z4 */
add v14.4s, v14.4s, v22.4s /* tmp2 += z3 */
/* Final output stage: inputs are tmp10..tmp13, tmp0..tmp3 */
add v18.4s, v2.4s, v16.4s /* tmp10 + tmp3 */
sub v20.4s, v2.4s, v16.4s /* tmp10 - tmp3 */
add v22.4s, v8.4s, v14.4s /* tmp11 + tmp2 */
sub v24.4s, v8.4s, v14.4s /* tmp11 - tmp2 */
add v26.4s, v4.4s, v12.4s /* tmp12 + tmp1 */
sub v28.4s, v4.4s, v12.4s /* tmp12 - tmp1 */
add v14.4s, v6.4s, v10.4s /* tmp13 + tmp0 */
sub v16.4s, v6.4s, v10.4s /* tmp13 - tmp0 */
rshrn v2.4h, v18.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS-PASS1_BITS) */
rshrn v3.4h, v22.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS-PASS1_BITS) */
rshrn v4.4h, v26.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS-PASS1_BITS) */
rshrn v5.4h, v14.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v2.8h, v16.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v3.8h, v28.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS-PASS1_BITS) */
rshrn2 v4.8h, v24.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS-PASS1_BITS) */
rshrn2 v5.8h, v20.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS-PASS1_BITS) */
mov v6.16b, v15.16b
mov v7.16b, v15.16b
mov v8.16b, v15.16b
mov v9.16b, v15.16b
b 1b
.balign 16
3:
cbnz TMP4, 4f
/* Left AC coef is zero */
dup v14.2d, v10.d[0]
/* Even part: reverse the even part of the forward DCT. */
add v18.8h, v4.8h, v8.8h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*2], quantptr[DCTSIZE*2]) + DEQUANTIZE(inptr[DCTSIZE*6], quantptr[DCTSIZE*6]) */
add v22.8h, v2.8h, v6.8h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) + DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
smull2 v19.4s, v18.8h, XFIX_P_0_541 /* z1h z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
sub v26.8h, v2.8h, v6.8h /* z2 - z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) - DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
mov v21.16b, v19.16b /* tmp3 = z1 */
smlal2 v19.4s, v8.8h, XFIX_N_1_847 /* tmp2h tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065); */
sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
smlal2 v21.4s, v4.8h, XFIX_P_0_765 /* tmp3h tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865); */
add v28.4s, v23.4s, v21.4s /* tmp10h tmp10 = tmp0 + tmp3; */
sub v31.4s, v23.4s, v21.4s /* tmp13h tmp13 = tmp0 - tmp3; */
add v29.4s, v27.4s, v19.4s /* tmp11h tmp11 = tmp1 + tmp2; */
sub v30.4s, v27.4s, v19.4s /* tmp12h tmp12 = tmp1 - tmp2; */
/* Odd part per figure 8; the matrix is unitary and hence its
* transpose is its inverse. i0..i3 are y7,y5,y3,y1 respectively.
*/
add v22.8h, v9.8h, v5.8h /* z3 = tmp0 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v24.8h, v7.8h, v3.8h /* z4 = tmp1 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v18.8h, v9.8h, v3.8h /* z1 = tmp0 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v20.8h, v7.8h, v5.8h /* z2 = tmp1 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v26.8h, v22.8h, v24.8h /* z5 = z3 + z4 */
smull2 v11.4s, v9.8h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
smull2 v13.4s, v7.8h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
smull2 v15.4s, v5.8h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
smull2 v17.4s, v3.8h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
smull2 v27.4s, v26.8h, XFIX_P_1_175 /* z5h z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
smull2 v23.4s, v22.8h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560) */
smull2 v25.4s, v24.8h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644) */
smull2 v19.4s, v18.8h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223) */
smull2 v21.4s, v20.8h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447) */
add v23.4s, v23.4s, v27.4s /* z3 += z5 */
add v22.4s, v22.4s, v26.4s /* z3 += z5 */
add v25.4s, v25.4s, v27.4s /* z4 += z5 */
add v24.4s, v24.4s, v26.4s /* z4 += z5 */
add v11.4s, v11.4s, v19.4s /* tmp0 += z1 */
add v13.4s, v13.4s, v21.4s /* tmp1 += z2 */
add v15.4s, v15.4s, v21.4s /* tmp2 += z2 */
add v17.4s, v17.4s, v19.4s /* tmp3 += z1 */
add v11.4s, v11.4s, v23.4s /* tmp0 += z3 */
add v13.4s, v13.4s, v25.4s /* tmp1 += z4 */
add v17.4s, v17.4s, v25.4s /* tmp3 += z4 */
add v15.4s, v15.4s, v23.4s /* tmp2 += z3 */
/* Final output stage: inputs are tmp10..tmp13, tmp0..tmp3 */
add v19.4s, v28.4s, v17.4s /* tmp10 + tmp3 */
sub v21.4s, v28.4s, v17.4s /* tmp10 - tmp3 */
add v23.4s, v29.4s, v15.4s /* tmp11 + tmp2 */
sub v25.4s, v29.4s, v15.4s /* tmp11 - tmp2 */
add v27.4s, v30.4s, v13.4s /* tmp12 + tmp1 */
sub v29.4s, v30.4s, v13.4s /* tmp12 - tmp1 */
add v15.4s, v31.4s, v11.4s /* tmp13 + tmp0 */
sub v17.4s, v31.4s, v11.4s /* tmp13 - tmp0 */
mov v2.16b, v14.16b
mov v3.16b, v14.16b
mov v4.16b, v14.16b
mov v5.16b, v14.16b
rshrn v6.4h, v19.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS-PASS1_BITS) */
rshrn v7.4h, v23.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS-PASS1_BITS) */
rshrn v8.4h, v27.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS-PASS1_BITS) */
rshrn v9.4h, v15.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v6.8h, v17.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v7.8h, v29.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS-PASS1_BITS) */
rshrn2 v8.8h, v25.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS-PASS1_BITS) */
rshrn2 v9.8h, v21.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS-PASS1_BITS) */
b 1b
.balign 16
4:
/* "No" AC coef is zero */
/* Even part: reverse the even part of the forward DCT. */
add v18.8h, v4.8h, v8.8h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*2], quantptr[DCTSIZE*2]) + DEQUANTIZE(inptr[DCTSIZE*6], quantptr[DCTSIZE*6]) */
add v22.8h, v2.8h, v6.8h /* z2 + z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) + DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
smull2 v19.4s, v18.8h, XFIX_P_0_541 /* z1h z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
sub v26.8h, v2.8h, v6.8h /* z2 - z3 = DEQUANTIZE(inptr[DCTSIZE*0], quantptr[DCTSIZE*0]) - DEQUANTIZE(inptr[DCTSIZE*4], quantptr[DCTSIZE*4]) */
smull v18.4s, v18.4h, XFIX_P_0_541 /* z1l z1 = MULTIPLY(z2 + z3, FIX_0_541196100); */
sshll2 v23.4s, v22.8h, #(CONST_BITS) /* tmp0h tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
mov v21.16b, v19.16b /* tmp3 = z1 */
mov v20.16b, v18.16b /* tmp3 = z1 */
smlal2 v19.4s, v8.8h, XFIX_N_1_847 /* tmp2h tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065); */
smlal v18.4s, v8.4h, XFIX_N_1_847 /* tmp2l tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065); */
sshll2 v27.4s, v26.8h, #(CONST_BITS) /* tmp1h tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
smlal2 v21.4s, v4.8h, XFIX_P_0_765 /* tmp3h tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865); */
smlal v20.4s, v4.4h, XFIX_P_0_765 /* tmp3l tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865); */
sshll v22.4s, v22.4h, #(CONST_BITS) /* tmp0l tmp0 = LEFT_SHIFT(z2 + z3, CONST_BITS); */
sshll v26.4s, v26.4h, #(CONST_BITS) /* tmp1l tmp1 = LEFT_SHIFT(z2 - z3, CONST_BITS); */
add v2.4s, v22.4s, v20.4s /* tmp10l tmp10 = tmp0 + tmp3; */
sub v6.4s, v22.4s, v20.4s /* tmp13l tmp13 = tmp0 - tmp3; */
add v8.4s, v26.4s, v18.4s /* tmp11l tmp11 = tmp1 + tmp2; */
sub v4.4s, v26.4s, v18.4s /* tmp12l tmp12 = tmp1 - tmp2; */
add v28.4s, v23.4s, v21.4s /* tmp10h tmp10 = tmp0 + tmp3; */
sub v31.4s, v23.4s, v21.4s /* tmp13h tmp13 = tmp0 - tmp3; */
add v29.4s, v27.4s, v19.4s /* tmp11h tmp11 = tmp1 + tmp2; */
sub v30.4s, v27.4s, v19.4s /* tmp12h tmp12 = tmp1 - tmp2; */
/* Odd part per figure 8; the matrix is unitary and hence its
* transpose is its inverse. i0..i3 are y7,y5,y3,y1 respectively.
*/
add v22.8h, v9.8h, v5.8h /* z3 = tmp0 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v24.8h, v7.8h, v3.8h /* z4 = tmp1 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v18.8h, v9.8h, v3.8h /* z1 = tmp0 + tmp3 = DEQUANTIZE(inptr[DCTSIZE*7], quantptr[DCTSIZE*7]) + DEQUANTIZE(inptr[DCTSIZE*1], quantptr[DCTSIZE*1]) */
add v20.8h, v7.8h, v5.8h /* z2 = tmp1 + tmp2 = DEQUANTIZE(inptr[DCTSIZE*5], quantptr[DCTSIZE*5]) + DEQUANTIZE(inptr[DCTSIZE*3], quantptr[DCTSIZE*3]) */
add v26.8h, v22.8h, v24.8h /* z5 = z3 + z4 */
smull2 v11.4s, v9.8h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
smull2 v13.4s, v7.8h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
smull2 v15.4s, v5.8h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
smull2 v17.4s, v3.8h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
smull2 v27.4s, v26.8h, XFIX_P_1_175 /* z5h z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
smull2 v23.4s, v22.8h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560) */
smull2 v25.4s, v24.8h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644) */
smull2 v19.4s, v18.8h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223) */
smull2 v21.4s, v20.8h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447) */
smull v10.4s, v9.4h, XFIX_P_0_298 /* tmp0 = MULTIPLY(tmp0, FIX_0_298631336) */
smull v12.4s, v7.4h, XFIX_P_2_053 /* tmp1 = MULTIPLY(tmp1, FIX_2_053119869) */
smull v14.4s, v5.4h, XFIX_P_3_072 /* tmp2 = MULTIPLY(tmp2, FIX_3_072711026) */
smull v16.4s, v3.4h, XFIX_P_1_501 /* tmp3 = MULTIPLY(tmp3, FIX_1_501321110) */
smull v26.4s, v26.4h, XFIX_P_1_175 /* z5l z5 = MULTIPLY(z3 + z4, FIX_1_175875602) */
smull v22.4s, v22.4h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560) */
smull v24.4s, v24.4h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644) */
smull v18.4s, v18.4h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223) */
smull v20.4s, v20.4h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447) */
add v23.4s, v23.4s, v27.4s /* z3 += z5 */
add v22.4s, v22.4s, v26.4s /* z3 += z5 */
add v25.4s, v25.4s, v27.4s /* z4 += z5 */
add v24.4s, v24.4s, v26.4s /* z4 += z5 */
add v11.4s, v11.4s, v19.4s /* tmp0 += z1 */
add v10.4s, v10.4s, v18.4s /* tmp0 += z1 */
add v13.4s, v13.4s, v21.4s /* tmp1 += z2 */
add v12.4s, v12.4s, v20.4s /* tmp1 += z2 */
add v15.4s, v15.4s, v21.4s /* tmp2 += z2 */
add v14.4s, v14.4s, v20.4s /* tmp2 += z2 */
add v17.4s, v17.4s, v19.4s /* tmp3 += z1 */
add v16.4s, v16.4s, v18.4s /* tmp3 += z1 */
add v11.4s, v11.4s, v23.4s /* tmp0 += z3 */
add v10.4s, v10.4s, v22.4s /* tmp0 += z3 */
add v13.4s, v13.4s, v25.4s /* tmp1 += z4 */
add v12.4s, v12.4s, v24.4s /* tmp1 += z4 */
add v17.4s, v17.4s, v25.4s /* tmp3 += z4 */
add v16.4s, v16.4s, v24.4s /* tmp3 += z4 */
add v15.4s, v15.4s, v23.4s /* tmp2 += z3 */
add v14.4s, v14.4s, v22.4s /* tmp2 += z3 */
/* Final output stage: inputs are tmp10..tmp13, tmp0..tmp3 */
add v18.4s, v2.4s, v16.4s /* tmp10 + tmp3 */
add v19.4s, v28.4s, v17.4s /* tmp10 + tmp3 */
sub v20.4s, v2.4s, v16.4s /* tmp10 - tmp3 */
sub v21.4s, v28.4s, v17.4s /* tmp10 - tmp3 */
add v22.4s, v8.4s, v14.4s /* tmp11 + tmp2 */
add v23.4s, v29.4s, v15.4s /* tmp11 + tmp2 */
sub v24.4s, v8.4s, v14.4s /* tmp11 - tmp2 */
sub v25.4s, v29.4s, v15.4s /* tmp11 - tmp2 */
add v26.4s, v4.4s, v12.4s /* tmp12 + tmp1 */
add v27.4s, v30.4s, v13.4s /* tmp12 + tmp1 */
sub v28.4s, v4.4s, v12.4s /* tmp12 - tmp1 */
sub v29.4s, v30.4s, v13.4s /* tmp12 - tmp1 */
add v14.4s, v6.4s, v10.4s /* tmp13 + tmp0 */
add v15.4s, v31.4s, v11.4s /* tmp13 + tmp0 */
sub v16.4s, v6.4s, v10.4s /* tmp13 - tmp0 */
sub v17.4s, v31.4s, v11.4s /* tmp13 - tmp0 */
rshrn v2.4h, v18.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS-PASS1_BITS) */
rshrn v3.4h, v22.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS-PASS1_BITS) */
rshrn v4.4h, v26.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS-PASS1_BITS) */
rshrn v5.4h, v14.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS-PASS1_BITS) */
rshrn v6.4h, v19.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*0] = (int) DESCALE(tmp10 + tmp3, CONST_BITS-PASS1_BITS) */
rshrn v7.4h, v23.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*1] = (int) DESCALE(tmp11 + tmp2, CONST_BITS-PASS1_BITS) */
rshrn v8.4h, v27.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*2] = (int) DESCALE(tmp12 + tmp1, CONST_BITS-PASS1_BITS) */
rshrn v9.4h, v15.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*3] = (int) DESCALE(tmp13 + tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v2.8h, v16.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v3.8h, v28.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS-PASS1_BITS) */
rshrn2 v4.8h, v24.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS-PASS1_BITS) */
rshrn2 v5.8h, v20.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS-PASS1_BITS) */
rshrn2 v6.8h, v17.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*4] = (int) DESCALE(tmp13 - tmp0, CONST_BITS-PASS1_BITS) */
rshrn2 v7.8h, v29.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*5] = (int) DESCALE(tmp12 - tmp1, CONST_BITS-PASS1_BITS) */
rshrn2 v8.8h, v25.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*6] = (int) DESCALE(tmp11 - tmp2, CONST_BITS-PASS1_BITS) */
rshrn2 v9.8h, v21.4s, #(CONST_BITS-PASS1_BITS) /* wsptr[DCTSIZE*7] = (int) DESCALE(tmp10 - tmp3, CONST_BITS-PASS1_BITS) */
b 1b
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.unreq TMP5
.unreq TMP6
.unreq TMP7
.unreq TMP8
#undef CENTERJSAMPLE
#undef CONST_BITS
#undef PASS1_BITS
#undef XFIX_P_0_298
#undef XFIX_N_0_390
#undef XFIX_P_0_541
#undef XFIX_P_0_765
#undef XFIX_N_0_899
#undef XFIX_P_1_175
#undef XFIX_P_1_501
#undef XFIX_N_1_847
#undef XFIX_N_1_961
#undef XFIX_P_2_053
#undef XFIX_N_2_562
#undef XFIX_P_3_072
/*****************************************************************************/
/*
* jsimd_idct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the inverse DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_ifast'
* function from jidctfst.c
*
* Normally 1-D AAN DCT needs 5 multiplications and 29 additions.
* But in ARM NEON case some extra additions are required because VQDMULH
* instruction can't handle the constants larger than 1. So the expressions
* like "x * 1.082392200" have to be converted to "x * 0.082392200 + x",
* which introduces an extra addition. Overall, there are 6 extra additions
* per 1-D IDCT pass, totalling to 5 VQDMULH and 35 VADD/VSUB instructions.
*/
#define XFIX_1_082392200 v0.h[0]
#define XFIX_1_414213562 v0.h[1]
#define XFIX_1_847759065 v0.h[2]
#define XFIX_2_613125930 v0.h[3]
.balign 16
Ljsimd_idct_ifast_neon_consts:
.short (277 * 128 - 256 * 128) /* XFIX_1_082392200 */
.short (362 * 128 - 256 * 128) /* XFIX_1_414213562 */
.short (473 * 128 - 256 * 128) /* XFIX_1_847759065 */
.short (669 * 128 - 512 * 128) /* XFIX_2_613125930 */
asm_function jsimd_idct_ifast_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x1
TMP3 .req x9
TMP4 .req x10
TMP5 .req x11
TMP6 .req x12
TMP7 .req x13
TMP8 .req x14
/* Load and dequantize coefficients into NEON registers
* with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 ( v16.8h )
* 1 | d18 | d19 ( v17.8h )
* 2 | d20 | d21 ( v18.8h )
* 3 | d22 | d23 ( v19.8h )
* 4 | d24 | d25 ( v20.8h )
* 5 | d26 | d27 ( v21.8h )
* 6 | d28 | d29 ( v22.8h )
* 7 | d30 | d31 ( v23.8h )
*/
/* Save NEON registers used in fast IDCT */
adr TMP5, Ljsimd_idct_ifast_neon_consts
ld1 {v16.8h, v17.8h}, [COEF_BLOCK], 32
ld1 {v0.8h, v1.8h}, [DCT_TABLE], 32
ld1 {v18.8h, v19.8h}, [COEF_BLOCK], 32
mul v16.8h, v16.8h, v0.8h
ld1 {v2.8h, v3.8h}, [DCT_TABLE], 32
mul v17.8h, v17.8h, v1.8h
ld1 {v20.8h, v21.8h}, [COEF_BLOCK], 32
mul v18.8h, v18.8h, v2.8h
ld1 {v0.8h, v1.8h}, [DCT_TABLE], 32
mul v19.8h, v19.8h, v3.8h
ld1 {v22.8h, v23.8h}, [COEF_BLOCK], 32
mul v20.8h, v20.8h, v0.8h
ld1 {v2.8h, v3.8h}, [DCT_TABLE], 32
mul v22.8h, v22.8h, v2.8h
mul v21.8h, v21.8h, v1.8h
ld1 {v0.4h}, [TMP5] /* load constants */
mul v23.8h, v23.8h, v3.8h
/* 1-D IDCT, pass 1 */
sub v2.8h, v18.8h, v22.8h
add v22.8h, v18.8h, v22.8h
sub v1.8h, v19.8h, v21.8h
add v21.8h, v19.8h, v21.8h
sub v5.8h, v17.8h, v23.8h
add v23.8h, v17.8h, v23.8h
sqdmulh v4.8h, v2.8h, XFIX_1_414213562
sqdmulh v6.8h, v1.8h, XFIX_2_613125930
add v3.8h, v1.8h, v1.8h
sub v1.8h, v5.8h, v1.8h
add v18.8h, v2.8h, v4.8h
sqdmulh v4.8h, v1.8h, XFIX_1_847759065
sub v2.8h, v23.8h, v21.8h
add v3.8h, v3.8h, v6.8h
sqdmulh v6.8h, v2.8h, XFIX_1_414213562
add v1.8h, v1.8h, v4.8h
sqdmulh v4.8h, v5.8h, XFIX_1_082392200
sub v18.8h, v18.8h, v22.8h
add v2.8h, v2.8h, v6.8h
sub v6.8h, v16.8h, v20.8h
add v20.8h, v16.8h, v20.8h
add v17.8h, v5.8h, v4.8h
add v5.8h, v6.8h, v18.8h
sub v18.8h, v6.8h, v18.8h
add v6.8h, v23.8h, v21.8h
add v16.8h, v20.8h, v22.8h
sub v3.8h, v6.8h, v3.8h
sub v20.8h, v20.8h, v22.8h
sub v3.8h, v3.8h, v1.8h
sub v1.8h, v17.8h, v1.8h
add v2.8h, v3.8h, v2.8h
sub v23.8h, v16.8h, v6.8h
add v1.8h, v1.8h, v2.8h
add v16.8h, v16.8h, v6.8h
add v22.8h, v5.8h, v3.8h
sub v17.8h, v5.8h, v3.8h
sub v21.8h, v18.8h, v2.8h
add v18.8h, v18.8h, v2.8h
sub v19.8h, v20.8h, v1.8h
add v20.8h, v20.8h, v1.8h
transpose_8x8 v16, v17, v18, v19, v20, v21, v22, v23, v28, v29, v30, v31
/* 1-D IDCT, pass 2 */
sub v2.8h, v18.8h, v22.8h
add v22.8h, v18.8h, v22.8h
sub v1.8h, v19.8h, v21.8h
add v21.8h, v19.8h, v21.8h
sub v5.8h, v17.8h, v23.8h
add v23.8h, v17.8h, v23.8h
sqdmulh v4.8h, v2.8h, XFIX_1_414213562
sqdmulh v6.8h, v1.8h, XFIX_2_613125930
add v3.8h, v1.8h, v1.8h
sub v1.8h, v5.8h, v1.8h
add v18.8h, v2.8h, v4.8h
sqdmulh v4.8h, v1.8h, XFIX_1_847759065
sub v2.8h, v23.8h, v21.8h
add v3.8h, v3.8h, v6.8h
sqdmulh v6.8h, v2.8h, XFIX_1_414213562
add v1.8h, v1.8h, v4.8h
sqdmulh v4.8h, v5.8h, XFIX_1_082392200
sub v18.8h, v18.8h, v22.8h
add v2.8h, v2.8h, v6.8h
sub v6.8h, v16.8h, v20.8h
add v20.8h, v16.8h, v20.8h
add v17.8h, v5.8h, v4.8h
add v5.8h, v6.8h, v18.8h
sub v18.8h, v6.8h, v18.8h
add v6.8h, v23.8h, v21.8h
add v16.8h, v20.8h, v22.8h
sub v3.8h, v6.8h, v3.8h
sub v20.8h, v20.8h, v22.8h
sub v3.8h, v3.8h, v1.8h
sub v1.8h, v17.8h, v1.8h
add v2.8h, v3.8h, v2.8h
sub v23.8h, v16.8h, v6.8h
add v1.8h, v1.8h, v2.8h
add v16.8h, v16.8h, v6.8h
add v22.8h, v5.8h, v3.8h
sub v17.8h, v5.8h, v3.8h
sub v21.8h, v18.8h, v2.8h
add v18.8h, v18.8h, v2.8h
sub v19.8h, v20.8h, v1.8h
add v20.8h, v20.8h, v1.8h
/* Descale to 8-bit and range limit */
movi v0.16b, #0x80
/* Prepare pointers (dual-issue with NEON instructions) */
ldp TMP1, TMP2, [OUTPUT_BUF], 16
sqshrn v28.8b, v16.8h, #5
ldp TMP3, TMP4, [OUTPUT_BUF], 16
sqshrn v29.8b, v17.8h, #5
add TMP1, TMP1, OUTPUT_COL
sqshrn v30.8b, v18.8h, #5
add TMP2, TMP2, OUTPUT_COL
sqshrn v31.8b, v19.8h, #5
add TMP3, TMP3, OUTPUT_COL
sqshrn2 v28.16b, v20.8h, #5
add TMP4, TMP4, OUTPUT_COL
sqshrn2 v29.16b, v21.8h, #5
ldp TMP5, TMP6, [OUTPUT_BUF], 16
sqshrn2 v30.16b, v22.8h, #5
ldp TMP7, TMP8, [OUTPUT_BUF], 16
sqshrn2 v31.16b, v23.8h, #5
add TMP5, TMP5, OUTPUT_COL
add v16.16b, v28.16b, v0.16b
add TMP6, TMP6, OUTPUT_COL
add v18.16b, v29.16b, v0.16b
add TMP7, TMP7, OUTPUT_COL
add v20.16b, v30.16b, v0.16b
add TMP8, TMP8, OUTPUT_COL
add v22.16b, v31.16b, v0.16b
/* Transpose the final 8-bit samples */
trn1 v28.16b, v16.16b, v18.16b
trn1 v30.16b, v20.16b, v22.16b
trn2 v29.16b, v16.16b, v18.16b
trn2 v31.16b, v20.16b, v22.16b
trn1 v16.8h, v28.8h, v30.8h
trn2 v18.8h, v28.8h, v30.8h
trn1 v20.8h, v29.8h, v31.8h
trn2 v22.8h, v29.8h, v31.8h
uzp1 v28.4s, v16.4s, v18.4s
uzp2 v30.4s, v16.4s, v18.4s
uzp1 v29.4s, v20.4s, v22.4s
uzp2 v31.4s, v20.4s, v22.4s
/* Store results to the output buffer */
st1 {v28.d}[0], [TMP1]
st1 {v29.d}[0], [TMP2]
st1 {v28.d}[1], [TMP3]
st1 {v29.d}[1], [TMP4]
st1 {v30.d}[0], [TMP5]
st1 {v31.d}[0], [TMP6]
st1 {v30.d}[1], [TMP7]
st1 {v31.d}[1], [TMP8]
blr x30
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.unreq TMP5
.unreq TMP6
.unreq TMP7
.unreq TMP8
/*****************************************************************************/
/*
* jsimd_idct_4x4_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 4x4 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_4x4'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 4x4 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*
* TODO: a bit better instructions scheduling can be achieved by expanding
* idct_helper/transpose_4x4 macros and reordering instructions,
* but readability will suffer somewhat.
*/
#define CONST_BITS 13
#define FIX_0_211164243 (1730) /* FIX(0.211164243) */
#define FIX_0_509795579 (4176) /* FIX(0.509795579) */
#define FIX_0_601344887 (4926) /* FIX(0.601344887) */
#define FIX_0_720959822 (5906) /* FIX(0.720959822) */
#define FIX_0_765366865 (6270) /* FIX(0.765366865) */
#define FIX_0_850430095 (6967) /* FIX(0.850430095) */
#define FIX_0_899976223 (7373) /* FIX(0.899976223) */
#define FIX_1_061594337 (8697) /* FIX(1.061594337) */
#define FIX_1_272758580 (10426) /* FIX(1.272758580) */
#define FIX_1_451774981 (11893) /* FIX(1.451774981) */
#define FIX_1_847759065 (15137) /* FIX(1.847759065) */
#define FIX_2_172734803 (17799) /* FIX(2.172734803) */
#define FIX_2_562915447 (20995) /* FIX(2.562915447) */
#define FIX_3_624509785 (29692) /* FIX(3.624509785) */
.balign 16
Ljsimd_idct_4x4_neon_consts:
.short FIX_1_847759065 /* v0.h[0] */
.short -FIX_0_765366865 /* v0.h[1] */
.short -FIX_0_211164243 /* v0.h[2] */
.short FIX_1_451774981 /* v0.h[3] */
.short -FIX_2_172734803 /* d1[0] */
.short FIX_1_061594337 /* d1[1] */
.short -FIX_0_509795579 /* d1[2] */
.short -FIX_0_601344887 /* d1[3] */
.short FIX_0_899976223 /* v2.h[0] */
.short FIX_2_562915447 /* v2.h[1] */
.short 1 << (CONST_BITS+1) /* v2.h[2] */
.short 0 /* v2.h[3] */
.macro idct_helper x4, x6, x8, x10, x12, x14, x16, shift, y26, y27, y28, y29
smull v28.4s, \x4, v2.h[2]
smlal v28.4s, \x8, v0.h[0]
smlal v28.4s, \x14, v0.h[1]
smull v26.4s, \x16, v1.h[2]
smlal v26.4s, \x12, v1.h[3]
smlal v26.4s, \x10, v2.h[0]
smlal v26.4s, \x6, v2.h[1]
smull v30.4s, \x4, v2.h[2]
smlsl v30.4s, \x8, v0.h[0]
smlsl v30.4s, \x14, v0.h[1]
smull v24.4s, \x16, v0.h[2]
smlal v24.4s, \x12, v0.h[3]
smlal v24.4s, \x10, v1.h[0]
smlal v24.4s, \x6, v1.h[1]
add v20.4s, v28.4s, v26.4s
sub v28.4s, v28.4s, v26.4s
.if \shift > 16
srshr v20.4s, v20.4s, #\shift
srshr v28.4s, v28.4s, #\shift
xtn \y26, v20.4s
xtn \y29, v28.4s
.else
rshrn \y26, v20.4s, #\shift
rshrn \y29, v28.4s, #\shift
.endif
add v20.4s, v30.4s, v24.4s
sub v30.4s, v30.4s, v24.4s
.if \shift > 16
srshr v20.4s, v20.4s, #\shift
srshr v30.4s, v30.4s, #\shift
xtn \y27, v20.4s
xtn \y28, v30.4s
.else
rshrn \y27, v20.4s, #\shift
rshrn \y28, v30.4s, #\shift
.endif
.endm
asm_function jsimd_idct_4x4_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x1
TMP3 .req x2
TMP4 .req x15
/* Save all used NEON registers */
sub sp, sp, 272
str x15, [sp], 16
/* Load constants (v3.4h is just used for padding) */
adr TMP4, Ljsimd_idct_4x4_neon_consts
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
ld1 {v0.4h, v1.4h, v2.4h, v3.4h}, [TMP4]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | v4.4h | v5.4h
* 1 | v6.4h | v7.4h
* 2 | v8.4h | v9.4h
* 3 | v10.4h | v11.4h
* 4 | - | -
* 5 | v12.4h | v13.4h
* 6 | v14.4h | v15.4h
* 7 | v16.4h | v17.4h
*/
ld1 {v4.4h, v5.4h, v6.4h, v7.4h}, [COEF_BLOCK], 32
ld1 {v8.4h, v9.4h, v10.4h, v11.4h}, [COEF_BLOCK], 32
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v12.4h, v13.4h, v14.4h, v15.4h}, [COEF_BLOCK], 32
ld1 {v16.4h, v17.4h}, [COEF_BLOCK], 16
/* dequantize */
ld1 {v18.4h, v19.4h, v20.4h, v21.4h}, [DCT_TABLE], 32
mul v4.4h, v4.4h, v18.4h
mul v5.4h, v5.4h, v19.4h
ins v4.d[1], v5.d[0] /* 128 bit q4 */
ld1 {v22.4h, v23.4h, v24.4h, v25.4h}, [DCT_TABLE], 32
mul v6.4h, v6.4h, v20.4h
mul v7.4h, v7.4h, v21.4h
ins v6.d[1], v7.d[0] /* 128 bit q6 */
mul v8.4h, v8.4h, v22.4h
mul v9.4h, v9.4h, v23.4h
ins v8.d[1], v9.d[0] /* 128 bit q8 */
add DCT_TABLE, DCT_TABLE, #16
ld1 {v26.4h, v27.4h, v28.4h, v29.4h}, [DCT_TABLE], 32
mul v10.4h, v10.4h, v24.4h
mul v11.4h, v11.4h, v25.4h
ins v10.d[1], v11.d[0] /* 128 bit q10 */
mul v12.4h, v12.4h, v26.4h
mul v13.4h, v13.4h, v27.4h
ins v12.d[1], v13.d[0] /* 128 bit q12 */
ld1 {v30.4h, v31.4h}, [DCT_TABLE], 16
mul v14.4h, v14.4h, v28.4h
mul v15.4h, v15.4h, v29.4h
ins v14.d[1], v15.d[0] /* 128 bit q14 */
mul v16.4h, v16.4h, v30.4h
mul v17.4h, v17.4h, v31.4h
ins v16.d[1], v17.d[0] /* 128 bit q16 */
/* Pass 1 */
idct_helper v4.4h, v6.4h, v8.4h, v10.4h, v12.4h, v14.4h, v16.4h, 12, \
v4.4h, v6.4h, v8.4h, v10.4h
transpose_4x4 v4, v6, v8, v10, v3
ins v10.d[1], v11.d[0]
idct_helper v5.4h, v7.4h, v9.4h, v11.4h, v13.4h, v15.4h, v17.4h, 12, \
v5.4h, v7.4h, v9.4h, v11.4h
transpose_4x4 v5, v7, v9, v11, v3
ins v10.d[1], v11.d[0]
/* Pass 2 */
idct_helper v4.4h, v6.4h, v8.4h, v10.4h, v7.4h, v9.4h, v11.4h, 19, \
v26.4h, v27.4h, v28.4h, v29.4h
transpose_4x4 v26, v27, v28, v29, v3
/* Range limit */
movi v30.8h, #0x80
ins v26.d[1], v27.d[0]
ins v28.d[1], v29.d[0]
add v26.8h, v26.8h, v30.8h
add v28.8h, v28.8h, v30.8h
sqxtun v26.8b, v26.8h
sqxtun v27.8b, v28.8h
/* Store results to the output buffer */
ldp TMP1, TMP2, [OUTPUT_BUF], 16
ldp TMP3, TMP4, [OUTPUT_BUF]
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
add TMP3, TMP3, OUTPUT_COL
add TMP4, TMP4, OUTPUT_COL
#if defined(__ARMEL__) && !RESPECT_STRICT_ALIGNMENT
/* We can use much less instructions on little endian systems if the
* OS kernel is not configured to trap unaligned memory accesses
*/
st1 {v26.s}[0], [TMP1], 4
st1 {v27.s}[0], [TMP3], 4
st1 {v26.s}[1], [TMP2], 4
st1 {v27.s}[1], [TMP4], 4
#else
st1 {v26.b}[0], [TMP1], 1
st1 {v27.b}[0], [TMP3], 1
st1 {v26.b}[1], [TMP1], 1
st1 {v27.b}[1], [TMP3], 1
st1 {v26.b}[2], [TMP1], 1
st1 {v27.b}[2], [TMP3], 1
st1 {v26.b}[3], [TMP1], 1
st1 {v27.b}[3], [TMP3], 1
st1 {v26.b}[4], [TMP2], 1
st1 {v27.b}[4], [TMP4], 1
st1 {v26.b}[5], [TMP2], 1
st1 {v27.b}[5], [TMP4], 1
st1 {v26.b}[6], [TMP2], 1
st1 {v27.b}[6], [TMP4], 1
st1 {v26.b}[7], [TMP2], 1
st1 {v27.b}[7], [TMP4], 1
#endif
/* vpop {v8.4h - v15.4h} ;not available */
sub sp, sp, #272
ldr x15, [sp], 16
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
blr x30
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_idct_2x2_neon
*
* This function contains inverse-DCT code for getting reduced-size
* 2x2 pixels output from an 8x8 DCT block. It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_idct_2x2'
* function from jpeg-6b (jidctred.c).
*
* NOTE: jpeg-8 has an improved implementation of 2x2 inverse-DCT, which
* requires much less arithmetic operations and hence should be faster.
* The primary purpose of this particular NEON optimized function is
* bit exact compatibility with jpeg-6b.
*/
.balign 8
Ljsimd_idct_2x2_neon_consts:
.short -FIX_0_720959822 /* v14[0] */
.short FIX_0_850430095 /* v14[1] */
.short -FIX_1_272758580 /* v14[2] */
.short FIX_3_624509785 /* v14[3] */
.macro idct_helper x4, x6, x10, x12, x16, shift, y26, y27
sshll v15.4s, \x4, #15
smull v26.4s, \x6, v14.h[3]
smlal v26.4s, \x10, v14.h[2]
smlal v26.4s, \x12, v14.h[1]
smlal v26.4s, \x16, v14.h[0]
add v20.4s, v15.4s, v26.4s
sub v15.4s, v15.4s, v26.4s
.if \shift > 16
srshr v20.4s, v20.4s, #\shift
srshr v15.4s, v15.4s, #\shift
xtn \y26, v20.4s
xtn \y27, v15.4s
.else
rshrn \y26, v20.4s, #\shift
rshrn \y27, v15.4s, #\shift
.endif
.endm
asm_function jsimd_idct_2x2_neon
DCT_TABLE .req x0
COEF_BLOCK .req x1
OUTPUT_BUF .req x2
OUTPUT_COL .req x3
TMP1 .req x0
TMP2 .req x15
/* vpush {v8.4h - v15.4h} ; not available */
sub sp, sp, 208
str x15, [sp], 16
/* Load constants */
adr TMP2, Ljsimd_idct_2x2_neon_consts
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v21.8b, v22.8b}, [sp], 16
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v30.8b, v31.8b}, [sp], 16
ld1 {v14.4h}, [TMP2]
/* Load all COEF_BLOCK into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | v4.4h | v5.4h
* 1 | v6.4h | v7.4h
* 2 | - | -
* 3 | v10.4h | v11.4h
* 4 | - | -
* 5 | v12.4h | v13.4h
* 6 | - | -
* 7 | v16.4h | v17.4h
*/
ld1 {v4.4h, v5.4h, v6.4h, v7.4h}, [COEF_BLOCK], 32
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v10.4h, v11.4h}, [COEF_BLOCK], 16
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v12.4h, v13.4h}, [COEF_BLOCK], 16
add COEF_BLOCK, COEF_BLOCK, #16
ld1 {v16.4h, v17.4h}, [COEF_BLOCK], 16
/* Dequantize */
ld1 {v18.4h, v19.4h, v20.4h, v21.4h}, [DCT_TABLE], 32
mul v4.4h, v4.4h, v18.4h
mul v5.4h, v5.4h, v19.4h
ins v4.d[1], v5.d[0]
mul v6.4h, v6.4h, v20.4h
mul v7.4h, v7.4h, v21.4h
ins v6.d[1], v7.d[0]
add DCT_TABLE, DCT_TABLE, #16
ld1 {v24.4h, v25.4h}, [DCT_TABLE], 16
mul v10.4h, v10.4h, v24.4h
mul v11.4h, v11.4h, v25.4h
ins v10.d[1], v11.d[0]
add DCT_TABLE, DCT_TABLE, #16
ld1 {v26.4h, v27.4h}, [DCT_TABLE], 16
mul v12.4h, v12.4h, v26.4h
mul v13.4h, v13.4h, v27.4h
ins v12.d[1], v13.d[0]
add DCT_TABLE, DCT_TABLE, #16
ld1 {v30.4h, v31.4h}, [DCT_TABLE], 16
mul v16.4h, v16.4h, v30.4h
mul v17.4h, v17.4h, v31.4h
ins v16.d[1], v17.d[0]
/* Pass 1 */
#if 0
idct_helper v4.4h, v6.4h, v10.4h, v12.4h, v16.4h, 13, v4.4h, v6.4h
transpose_4x4 v4.4h, v6.4h, v8.4h, v10.4h
idct_helper v5.4h, v7.4h, v11.4h, v13.4h, v17.4h, 13, v5.4h, v7.4h
transpose_4x4 v5.4h, v7.4h, v9.4h, v11.4h
#else
smull v26.4s, v6.4h, v14.h[3]
smlal v26.4s, v10.4h, v14.h[2]
smlal v26.4s, v12.4h, v14.h[1]
smlal v26.4s, v16.4h, v14.h[0]
smull v24.4s, v7.4h, v14.h[3]
smlal v24.4s, v11.4h, v14.h[2]
smlal v24.4s, v13.4h, v14.h[1]
smlal v24.4s, v17.4h, v14.h[0]
sshll v15.4s, v4.4h, #15
sshll v30.4s, v5.4h, #15
add v20.4s, v15.4s, v26.4s
sub v15.4s, v15.4s, v26.4s
rshrn v4.4h, v20.4s, #13
rshrn v6.4h, v15.4s, #13
add v20.4s, v30.4s, v24.4s
sub v15.4s, v30.4s, v24.4s
rshrn v5.4h, v20.4s, #13
rshrn v7.4h, v15.4s, #13
ins v4.d[1], v5.d[0]
ins v6.d[1], v7.d[0]
transpose v4, v6, v3, .16b, .8h
transpose v6, v10, v3, .16b, .4s
ins v11.d[0], v10.d[1]
ins v7.d[0], v6.d[1]
#endif
/* Pass 2 */
idct_helper v4.4h, v6.4h, v10.4h, v7.4h, v11.4h, 20, v26.4h, v27.4h
/* Range limit */
movi v30.8h, #0x80
ins v26.d[1], v27.d[0]
add v26.8h, v26.8h, v30.8h
sqxtun v30.8b, v26.8h
ins v26.d[0], v30.d[0]
sqxtun v27.8b, v26.8h
/* Store results to the output buffer */
ldp TMP1, TMP2, [OUTPUT_BUF]
add TMP1, TMP1, OUTPUT_COL
add TMP2, TMP2, OUTPUT_COL
st1 {v26.b}[0], [TMP1], 1
st1 {v27.b}[4], [TMP1], 1
st1 {v26.b}[1], [TMP2], 1
st1 {v27.b}[5], [TMP2], 1
sub sp, sp, #208
ldr x15, [sp], 16
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v21.8b, v22.8b}, [sp], 16
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v30.8b, v31.8b}, [sp], 16
blr x30
.unreq DCT_TABLE
.unreq COEF_BLOCK
.unreq OUTPUT_BUF
.unreq OUTPUT_COL
.unreq TMP1
.unreq TMP2
.purgem idct_helper
/*****************************************************************************/
/*
* jsimd_ycc_extrgb_convert_neon
* jsimd_ycc_extbgr_convert_neon
* jsimd_ycc_extrgbx_convert_neon
* jsimd_ycc_extbgrx_convert_neon
* jsimd_ycc_extxbgr_convert_neon
* jsimd_ycc_extxrgb_convert_neon
*
* Colorspace conversion YCbCr -> RGB
*/
.macro do_load size
.if \size == 8
ld1 {v4.8b}, [U], 8
ld1 {v5.8b}, [V], 8
ld1 {v0.8b}, [Y], 8
prfm pldl1keep, [U, #64]
prfm pldl1keep, [V, #64]
prfm pldl1keep, [Y, #64]
.elseif \size == 4
ld1 {v4.b}[0], [U], 1
ld1 {v4.b}[1], [U], 1
ld1 {v4.b}[2], [U], 1
ld1 {v4.b}[3], [U], 1
ld1 {v5.b}[0], [V], 1
ld1 {v5.b}[1], [V], 1
ld1 {v5.b}[2], [V], 1
ld1 {v5.b}[3], [V], 1
ld1 {v0.b}[0], [Y], 1
ld1 {v0.b}[1], [Y], 1
ld1 {v0.b}[2], [Y], 1
ld1 {v0.b}[3], [Y], 1
.elseif \size == 2
ld1 {v4.b}[4], [U], 1
ld1 {v4.b}[5], [U], 1
ld1 {v5.b}[4], [V], 1
ld1 {v5.b}[5], [V], 1
ld1 {v0.b}[4], [Y], 1
ld1 {v0.b}[5], [Y], 1
.elseif \size == 1
ld1 {v4.b}[6], [U], 1
ld1 {v5.b}[6], [V], 1
ld1 {v0.b}[6], [Y], 1
.else
.error unsupported macroblock size
.endif
.endm
.macro do_store bpp, size, fast_st3
.if \bpp == 24
.if \size == 8
.if \fast_st3 == 1
st3 {v10.8b, v11.8b, v12.8b}, [RGB], 24
.else
st1 {v10.b}[0], [RGB], #1
st1 {v11.b}[0], [RGB], #1
st1 {v12.b}[0], [RGB], #1
st1 {v10.b}[1], [RGB], #1
st1 {v11.b}[1], [RGB], #1
st1 {v12.b}[1], [RGB], #1
st1 {v10.b}[2], [RGB], #1
st1 {v11.b}[2], [RGB], #1
st1 {v12.b}[2], [RGB], #1
st1 {v10.b}[3], [RGB], #1
st1 {v11.b}[3], [RGB], #1
st1 {v12.b}[3], [RGB], #1
st1 {v10.b}[4], [RGB], #1
st1 {v11.b}[4], [RGB], #1
st1 {v12.b}[4], [RGB], #1
st1 {v10.b}[5], [RGB], #1
st1 {v11.b}[5], [RGB], #1
st1 {v12.b}[5], [RGB], #1
st1 {v10.b}[6], [RGB], #1
st1 {v11.b}[6], [RGB], #1
st1 {v12.b}[6], [RGB], #1
st1 {v10.b}[7], [RGB], #1
st1 {v11.b}[7], [RGB], #1
st1 {v12.b}[7], [RGB], #1
.endif
.elseif \size == 4
st3 {v10.b, v11.b, v12.b}[0], [RGB], 3
st3 {v10.b, v11.b, v12.b}[1], [RGB], 3
st3 {v10.b, v11.b, v12.b}[2], [RGB], 3
st3 {v10.b, v11.b, v12.b}[3], [RGB], 3
.elseif \size == 2
st3 {v10.b, v11.b, v12.b}[4], [RGB], 3
st3 {v10.b, v11.b, v12.b}[5], [RGB], 3
.elseif \size == 1
st3 {v10.b, v11.b, v12.b}[6], [RGB], 3
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
st4 {v10.8b, v11.8b, v12.8b, v13.8b}, [RGB], 32
.elseif \size == 4
st4 {v10.b, v11.b, v12.b, v13.b}[0], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[1], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[2], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[3], [RGB], 4
.elseif \size == 2
st4 {v10.b, v11.b, v12.b, v13.b}[4], [RGB], 4
st4 {v10.b, v11.b, v12.b, v13.b}[5], [RGB], 4
.elseif \size == 1
st4 {v10.b, v11.b, v12.b, v13.b}[6], [RGB], 4
.else
.error unsupported macroblock size
.endif
.elseif \bpp==16
.if \size == 8
st1 {v25.8h}, [RGB], 16
.elseif \size == 4
st1 {v25.4h}, [RGB], 8
.elseif \size == 2
st1 {v25.h}[4], [RGB], 2
st1 {v25.h}[5], [RGB], 2
.elseif \size == 1
st1 {v25.h}[6], [RGB], 2
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_ycc_rgb_convert_neon colorid, bpp, r_offs, rsize, \
g_offs, gsize, b_offs, bsize, \
defsize, fast_st3
/*
* 2-stage pipelined YCbCr->RGB conversion
*/
.macro do_yuv_to_rgb_stage1
uaddw v6.8h, v2.8h, v4.8b /* q3 = u - 128 */
uaddw v8.8h, v2.8h, v5.8b /* q2 = v - 128 */
smull v20.4s, v6.4h, v1.h[1] /* multiply by -11277 */
smlal v20.4s, v8.4h, v1.h[2] /* multiply by -23401 */
smull2 v22.4s, v6.8h, v1.h[1] /* multiply by -11277 */
smlal2 v22.4s, v8.8h, v1.h[2] /* multiply by -23401 */
smull v24.4s, v8.4h, v1.h[0] /* multiply by 22971 */
smull2 v26.4s, v8.8h, v1.h[0] /* multiply by 22971 */
smull v28.4s, v6.4h, v1.h[3] /* multiply by 29033 */
smull2 v30.4s, v6.8h, v1.h[3] /* multiply by 29033 */
.endm
.macro do_yuv_to_rgb_stage2
rshrn v20.4h, v20.4s, #15
rshrn2 v20.8h, v22.4s, #15
rshrn v24.4h, v24.4s, #14
rshrn2 v24.8h, v26.4s, #14
rshrn v28.4h, v28.4s, #14
rshrn2 v28.8h, v30.4s, #14
uaddw v20.8h, v20.8h, v0.8b
uaddw v24.8h, v24.8h, v0.8b
uaddw v28.8h, v28.8h, v0.8b
.if \bpp != 16
sqxtun v1\g_offs\defsize, v20.8h
sqxtun v1\r_offs\defsize, v24.8h
sqxtun v1\b_offs\defsize, v28.8h
.else
sqshlu v21.8h, v20.8h, #8
sqshlu v25.8h, v24.8h, #8
sqshlu v29.8h, v28.8h, #8
sri v25.8h, v21.8h, #5
sri v25.8h, v29.8h, #11
.endif
.endm
.macro do_yuv_to_rgb_stage2_store_load_stage1 fast_st3
rshrn v20.4h, v20.4s, #15
rshrn v24.4h, v24.4s, #14
rshrn v28.4h, v28.4s, #14
ld1 {v4.8b}, [U], 8
rshrn2 v20.8h, v22.4s, #15
rshrn2 v24.8h, v26.4s, #14
rshrn2 v28.8h, v30.4s, #14
ld1 {v5.8b}, [V], 8
uaddw v20.8h, v20.8h, v0.8b
uaddw v24.8h, v24.8h, v0.8b
uaddw v28.8h, v28.8h, v0.8b
.if \bpp != 16 /**************** rgb24/rgb32 ******************************/
sqxtun v1\g_offs\defsize, v20.8h
ld1 {v0.8b}, [Y], 8
sqxtun v1\r_offs\defsize, v24.8h
prfm pldl1keep, [U, #64]
prfm pldl1keep, [V, #64]
prfm pldl1keep, [Y, #64]
sqxtun v1\b_offs\defsize, v28.8h
uaddw v6.8h, v2.8h, v4.8b /* v6.16b = u - 128 */
uaddw v8.8h, v2.8h, v5.8b /* q2 = v - 128 */
smull v20.4s, v6.4h, v1.h[1] /* multiply by -11277 */
smlal v20.4s, v8.4h, v1.h[2] /* multiply by -23401 */
smull2 v22.4s, v6.8h, v1.h[1] /* multiply by -11277 */
smlal2 v22.4s, v8.8h, v1.h[2] /* multiply by -23401 */
smull v24.4s, v8.4h, v1.h[0] /* multiply by 22971 */
smull2 v26.4s, v8.8h, v1.h[0] /* multiply by 22971 */
.else /**************************** rgb565 ********************************/
sqshlu v21.8h, v20.8h, #8
sqshlu v25.8h, v24.8h, #8
sqshlu v29.8h, v28.8h, #8
uaddw v6.8h, v2.8h, v4.8b /* v6.16b = u - 128 */
uaddw v8.8h, v2.8h, v5.8b /* q2 = v - 128 */
ld1 {v0.8b}, [Y], 8
smull v20.4s, v6.4h, v1.h[1] /* multiply by -11277 */
smlal v20.4s, v8.4h, v1.h[2] /* multiply by -23401 */
smull2 v22.4s, v6.8h, v1.h[1] /* multiply by -11277 */
smlal2 v22.4s, v8.8h, v1.h[2] /* multiply by -23401 */
sri v25.8h, v21.8h, #5
smull v24.4s, v8.4h, v1.h[0] /* multiply by 22971 */
smull2 v26.4s, v8.8h, v1.h[0] /* multiply by 22971 */
prfm pldl1keep, [U, #64]
prfm pldl1keep, [V, #64]
prfm pldl1keep, [Y, #64]
sri v25.8h, v29.8h, #11
.endif
do_store \bpp, 8, \fast_st3
smull v28.4s, v6.4h, v1.h[3] /* multiply by 29033 */
smull2 v30.4s, v6.8h, v1.h[3] /* multiply by 29033 */
.endm
.macro do_yuv_to_rgb
do_yuv_to_rgb_stage1
do_yuv_to_rgb_stage2
.endm
/* Apple gas crashes on adrl, work around that by using adr.
* But this requires a copy of these constants for each function.
*/
.balign 16
.if \fast_st3 == 1
Ljsimd_ycc_\colorid\()_neon_consts:
.else
Ljsimd_ycc_\colorid\()_neon_slowst3_consts:
.endif
.short 0, 0, 0, 0
.short 22971, -11277, -23401, 29033
.short -128, -128, -128, -128
.short -128, -128, -128, -128
.if \fast_st3 == 1
asm_function jsimd_ycc_\colorid\()_convert_neon
.else
asm_function jsimd_ycc_\colorid\()_convert_neon_slowst3
.endif
OUTPUT_WIDTH .req x0
INPUT_BUF .req x1
INPUT_ROW .req x2
OUTPUT_BUF .req x3
NUM_ROWS .req x4
INPUT_BUF0 .req x5
INPUT_BUF1 .req x6
INPUT_BUF2 .req x1
RGB .req x7
Y .req x8
U .req x9
V .req x10
N .req x15
sub sp, sp, 336
str x15, [sp], 16
/* Load constants to d1, d2, d3 (v0.4h is just used for padding) */
.if \fast_st3 == 1
adr x15, Ljsimd_ycc_\colorid\()_neon_consts
.else
adr x15, Ljsimd_ycc_\colorid\()_neon_slowst3_consts
.endif
/* Save NEON registers */
st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
st1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
st1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
st1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
st1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
st1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
ld1 {v0.4h, v1.4h}, [x15], 16
ld1 {v2.8h}, [x15]
/* Save ARM registers and handle input arguments */
/* push {x4, x5, x6, x7, x8, x9, x10, x30} */
stp x4, x5, [sp], 16
stp x6, x7, [sp], 16
stp x8, x9, [sp], 16
stp x10, x30, [sp], 16
ldr INPUT_BUF0, [INPUT_BUF]
ldr INPUT_BUF1, [INPUT_BUF, #8]
ldr INPUT_BUF2, [INPUT_BUF, #16]
.unreq INPUT_BUF
/* Initially set v10, v11.4h, v12.8b, d13 to 0xFF */
movi v10.16b, #255
movi v13.16b, #255
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
b.lt 9f
0:
lsl x16, INPUT_ROW, #3
ldr Y, [INPUT_BUF0, x16]
ldr U, [INPUT_BUF1, x16]
mov N, OUTPUT_WIDTH
ldr V, [INPUT_BUF2, x16]
add INPUT_ROW, INPUT_ROW, #1
ldr RGB, [OUTPUT_BUF], #8
/* Inner loop over pixels */
subs N, N, #8
b.lt 3f
do_load 8
do_yuv_to_rgb_stage1
subs N, N, #8
b.lt 2f
1:
do_yuv_to_rgb_stage2_store_load_stage1 \fast_st3
subs N, N, #8
b.ge 1b
2:
do_yuv_to_rgb_stage2
do_store \bpp, 8, \fast_st3
tst N, #7
b.eq 8f
3:
tst N, #4
b.eq 3f
do_load 4
3:
tst N, #2
b.eq 4f
do_load 2
4:
tst N, #1
b.eq 5f
do_load 1
5:
do_yuv_to_rgb
tst N, #4
b.eq 6f
do_store \bpp, 4, \fast_st3
6:
tst N, #2
b.eq 7f
do_store \bpp, 2, \fast_st3
7:
tst N, #1
b.eq 8f
do_store \bpp, 1, \fast_st3
8:
subs NUM_ROWS, NUM_ROWS, #1
b.gt 0b
9:
/* Restore all registers and return */
sub sp, sp, #336
ldr x15, [sp], 16
ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [sp], 32
ld1 {v4.8b, v5.8b, v6.8b, v7.8b}, [sp], 32
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
ld1 {v16.8b, v17.8b, v18.8b, v19.8b}, [sp], 32
ld1 {v20.8b, v21.8b, v22.8b, v23.8b}, [sp], 32
ld1 {v24.8b, v25.8b, v26.8b, v27.8b}, [sp], 32
ld1 {v28.8b, v29.8b, v30.8b, v31.8b}, [sp], 32
/* pop {r4, r5, r6, r7, r8, r9, r10, pc} */
ldp x4, x5, [sp], 16
ldp x6, x7, [sp], 16
ldp x8, x9, [sp], 16
ldp x10, x30, [sp], 16
br x30
.unreq OUTPUT_WIDTH
.unreq INPUT_ROW
.unreq OUTPUT_BUF
.unreq NUM_ROWS
.unreq INPUT_BUF0
.unreq INPUT_BUF1
.unreq INPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_yuv_to_rgb
.purgem do_yuv_to_rgb_stage1
.purgem do_yuv_to_rgb_stage2
.purgem do_yuv_to_rgb_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R rsize G gsize B bsize defsize fast_st3*/
generate_jsimd_ycc_rgb_convert_neon extrgb, 24, 0, .4h, 1, .4h, 2, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon extbgr, 24, 2, .4h, 1, .4h, 0, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon extrgbx, 32, 0, .4h, 1, .4h, 2, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon extbgrx, 32, 2, .4h, 1, .4h, 0, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon extxbgr, 32, 3, .4h, 2, .4h, 1, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon extxrgb, 32, 1, .4h, 2, .4h, 3, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon rgb565, 16, 0, .4h, 0, .4h, 0, .4h, .8b, 1
generate_jsimd_ycc_rgb_convert_neon extrgb, 24, 0, .4h, 1, .4h, 2, .4h, .8b, 0
generate_jsimd_ycc_rgb_convert_neon extbgr, 24, 2, .4h, 1, .4h, 0, .4h, .8b, 0
.purgem do_load
.purgem do_store
/*****************************************************************************/
/*
* jsimd_extrgb_ycc_convert_neon
* jsimd_extbgr_ycc_convert_neon
* jsimd_extrgbx_ycc_convert_neon
* jsimd_extbgrx_ycc_convert_neon
* jsimd_extxbgr_ycc_convert_neon
* jsimd_extxrgb_ycc_convert_neon
*
* Colorspace conversion RGB -> YCbCr
*/
.macro do_store size
.if \size == 8
st1 {v20.8b}, [Y], #8
st1 {v21.8b}, [U], #8
st1 {v22.8b}, [V], #8
.elseif \size == 4
st1 {v20.b}[0], [Y], #1
st1 {v20.b}[1], [Y], #1
st1 {v20.b}[2], [Y], #1
st1 {v20.b}[3], [Y], #1
st1 {v21.b}[0], [U], #1
st1 {v21.b}[1], [U], #1
st1 {v21.b}[2], [U], #1
st1 {v21.b}[3], [U], #1
st1 {v22.b}[0], [V], #1
st1 {v22.b}[1], [V], #1
st1 {v22.b}[2], [V], #1
st1 {v22.b}[3], [V], #1
.elseif \size == 2
st1 {v20.b}[4], [Y], #1
st1 {v20.b}[5], [Y], #1
st1 {v21.b}[4], [U], #1
st1 {v21.b}[5], [U], #1
st1 {v22.b}[4], [V], #1
st1 {v22.b}[5], [V], #1
.elseif \size == 1
st1 {v20.b}[6], [Y], #1
st1 {v21.b}[6], [U], #1
st1 {v22.b}[6], [V], #1
.else
.error unsupported macroblock size
.endif
.endm
.macro do_load bpp, size, fast_ld3
.if \bpp == 24
.if \size == 8
.if \fast_ld3 == 1
ld3 {v10.8b, v11.8b, v12.8b}, [RGB], #24
.else
ld1 {v10.b}[0], [RGB], #1
ld1 {v11.b}[0], [RGB], #1
ld1 {v12.b}[0], [RGB], #1
ld1 {v10.b}[1], [RGB], #1
ld1 {v11.b}[1], [RGB], #1
ld1 {v12.b}[1], [RGB], #1
ld1 {v10.b}[2], [RGB], #1
ld1 {v11.b}[2], [RGB], #1
ld1 {v12.b}[2], [RGB], #1
ld1 {v10.b}[3], [RGB], #1
ld1 {v11.b}[3], [RGB], #1
ld1 {v12.b}[3], [RGB], #1
ld1 {v10.b}[4], [RGB], #1
ld1 {v11.b}[4], [RGB], #1
ld1 {v12.b}[4], [RGB], #1
ld1 {v10.b}[5], [RGB], #1
ld1 {v11.b}[5], [RGB], #1
ld1 {v12.b}[5], [RGB], #1
ld1 {v10.b}[6], [RGB], #1
ld1 {v11.b}[6], [RGB], #1
ld1 {v12.b}[6], [RGB], #1
ld1 {v10.b}[7], [RGB], #1
ld1 {v11.b}[7], [RGB], #1
ld1 {v12.b}[7], [RGB], #1
.endif
prfm pldl1keep, [RGB, #128]
.elseif \size == 4
ld3 {v10.b, v11.b, v12.b}[0], [RGB], #3
ld3 {v10.b, v11.b, v12.b}[1], [RGB], #3
ld3 {v10.b, v11.b, v12.b}[2], [RGB], #3
ld3 {v10.b, v11.b, v12.b}[3], [RGB], #3
.elseif \size == 2
ld3 {v10.b, v11.b, v12.b}[4], [RGB], #3
ld3 {v10.b, v11.b, v12.b}[5], [RGB], #3
.elseif \size == 1
ld3 {v10.b, v11.b, v12.b}[6], [RGB], #3
.else
.error unsupported macroblock size
.endif
.elseif \bpp == 32
.if \size == 8
ld4 {v10.8b, v11.8b, v12.8b, v13.8b}, [RGB], #32
prfm pldl1keep, [RGB, #128]
.elseif \size == 4
ld4 {v10.b, v11.b, v12.b, v13.b}[0], [RGB], #4
ld4 {v10.b, v11.b, v12.b, v13.b}[1], [RGB], #4
ld4 {v10.b, v11.b, v12.b, v13.b}[2], [RGB], #4
ld4 {v10.b, v11.b, v12.b, v13.b}[3], [RGB], #4
.elseif \size == 2
ld4 {v10.b, v11.b, v12.b, v13.b}[4], [RGB], #4
ld4 {v10.b, v11.b, v12.b, v13.b}[5], [RGB], #4
.elseif \size == 1
ld4 {v10.b, v11.b, v12.b, v13.b}[6], [RGB], #4
.else
.error unsupported macroblock size
.endif
.else
.error unsupported bpp
.endif
.endm
.macro generate_jsimd_rgb_ycc_convert_neon colorid, bpp, r_offs, g_offs, \
b_offs, fast_ld3
/*
* 2-stage pipelined RGB->YCbCr conversion
*/
.macro do_rgb_to_yuv_stage1
ushll v4.8h, v1\r_offs\().8b, #0 /* r = v4 */
ushll v6.8h, v1\g_offs\().8b, #0 /* g = v6 */
ushll v8.8h, v1\b_offs\().8b, #0 /* b = v8 */
rev64 v18.4s, v1.4s
rev64 v26.4s, v1.4s
rev64 v28.4s, v1.4s
rev64 v30.4s, v1.4s
umull v14.4s, v4.4h, v0.h[0]
umull2 v16.4s, v4.8h, v0.h[0]
umlsl v18.4s, v4.4h, v0.h[3]
umlsl2 v26.4s, v4.8h, v0.h[3]
umlal v28.4s, v4.4h, v0.h[5]
umlal2 v30.4s, v4.8h, v0.h[5]
umlal v14.4s, v6.4h, v0.h[1]
umlal2 v16.4s, v6.8h, v0.h[1]
umlsl v18.4s, v6.4h, v0.h[4]
umlsl2 v26.4s, v6.8h, v0.h[4]
umlsl v28.4s, v6.4h, v0.h[6]
umlsl2 v30.4s, v6.8h, v0.h[6]
umlal v14.4s, v8.4h, v0.h[2]
umlal2 v16.4s, v8.8h, v0.h[2]
umlal v18.4s, v8.4h, v0.h[5]
umlal2 v26.4s, v8.8h, v0.h[5]
umlsl v28.4s, v8.4h, v0.h[7]
umlsl2 v30.4s, v8.8h, v0.h[7]
.endm
.macro do_rgb_to_yuv_stage2
rshrn v20.4h, v14.4s, #16
shrn v22.4h, v18.4s, #16
shrn v24.4h, v28.4s, #16
rshrn2 v20.8h, v16.4s, #16
shrn2 v22.8h, v26.4s, #16
shrn2 v24.8h, v30.4s, #16
xtn v20.8b, v20.8h /* v20 = y */
xtn v21.8b, v22.8h /* v21 = u */
xtn v22.8b, v24.8h /* v22 = v */
.endm
.macro do_rgb_to_yuv
do_rgb_to_yuv_stage1
do_rgb_to_yuv_stage2
.endm
/* TODO: expand macros and interleave instructions if some in-order
* ARM64 processor actually can dual-issue LOAD/STORE with ALU */
.macro do_rgb_to_yuv_stage2_store_load_stage1 fast_ld3
do_rgb_to_yuv_stage2
do_load \bpp, 8, \fast_ld3
st1 {v20.8b}, [Y], #8
st1 {v21.8b}, [U], #8
st1 {v22.8b}, [V], #8
do_rgb_to_yuv_stage1
.endm
.balign 16
.if \fast_ld3 == 1
Ljsimd_\colorid\()_ycc_neon_consts:
.else
Ljsimd_\colorid\()_ycc_neon_slowld3_consts:
.endif
.short 19595, 38470, 7471, 11059
.short 21709, 32768, 27439, 5329
.short 32767, 128, 32767, 128
.short 32767, 128, 32767, 128
.if \fast_ld3 == 1
asm_function jsimd_\colorid\()_ycc_convert_neon
.else
asm_function jsimd_\colorid\()_ycc_convert_neon_slowld3
.endif
OUTPUT_WIDTH .req w0
INPUT_BUF .req x1
OUTPUT_BUF .req x2
OUTPUT_ROW .req x3
NUM_ROWS .req x4
OUTPUT_BUF0 .req x5
OUTPUT_BUF1 .req x6
OUTPUT_BUF2 .req x2 /* OUTPUT_BUF */
RGB .req x7
Y .req x9
U .req x10
V .req x11
N .req w12
/* Load constants to d0, d1, d2, d3 */
.if \fast_ld3 == 1
adr x13, Ljsimd_\colorid\()_ycc_neon_consts
.else
adr x13, Ljsimd_\colorid\()_ycc_neon_slowld3_consts
.endif
ld1 {v0.8h, v1.8h}, [x13]
ldr OUTPUT_BUF0, [OUTPUT_BUF]
ldr OUTPUT_BUF1, [OUTPUT_BUF, #8]
ldr OUTPUT_BUF2, [OUTPUT_BUF, #16]
.unreq OUTPUT_BUF
/* Save NEON registers */
sub sp, sp, #64
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
/* Outer loop over scanlines */
cmp NUM_ROWS, #1
b.lt 9f
0:
ldr Y, [OUTPUT_BUF0, OUTPUT_ROW, lsl #3]
ldr U, [OUTPUT_BUF1, OUTPUT_ROW, lsl #3]
mov N, OUTPUT_WIDTH
ldr V, [OUTPUT_BUF2, OUTPUT_ROW, lsl #3]
add OUTPUT_ROW, OUTPUT_ROW, #1
ldr RGB, [INPUT_BUF], #8
/* Inner loop over pixels */
subs N, N, #8
b.lt 3f
do_load \bpp, 8, \fast_ld3
do_rgb_to_yuv_stage1
subs N, N, #8
b.lt 2f
1:
do_rgb_to_yuv_stage2_store_load_stage1 \fast_ld3
subs N, N, #8
b.ge 1b
2:
do_rgb_to_yuv_stage2
do_store 8
tst N, #7
b.eq 8f
3:
tbz N, #2, 3f
do_load \bpp, 4, \fast_ld3
3:
tbz N, #1, 4f
do_load \bpp, 2, \fast_ld3
4:
tbz N, #0, 5f
do_load \bpp, 1, \fast_ld3
5:
do_rgb_to_yuv
tbz N, #2, 6f
do_store 4
6:
tbz N, #1, 7f
do_store 2
7:
tbz N, #0, 8f
do_store 1
8:
subs NUM_ROWS, NUM_ROWS, #1
b.gt 0b
9:
/* Restore all registers and return */
sub sp, sp, #64
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
br x30
.unreq OUTPUT_WIDTH
.unreq OUTPUT_ROW
.unreq INPUT_BUF
.unreq NUM_ROWS
.unreq OUTPUT_BUF0
.unreq OUTPUT_BUF1
.unreq OUTPUT_BUF2
.unreq RGB
.unreq Y
.unreq U
.unreq V
.unreq N
.purgem do_rgb_to_yuv
.purgem do_rgb_to_yuv_stage1
.purgem do_rgb_to_yuv_stage2
.purgem do_rgb_to_yuv_stage2_store_load_stage1
.endm
/*--------------------------------- id ----- bpp R G B Fast LD3 */
generate_jsimd_rgb_ycc_convert_neon extrgb, 24, 0, 1, 2, 1
generate_jsimd_rgb_ycc_convert_neon extbgr, 24, 2, 1, 0, 1
generate_jsimd_rgb_ycc_convert_neon extrgbx, 32, 0, 1, 2, 1
generate_jsimd_rgb_ycc_convert_neon extbgrx, 32, 2, 1, 0, 1
generate_jsimd_rgb_ycc_convert_neon extxbgr, 32, 3, 2, 1, 1
generate_jsimd_rgb_ycc_convert_neon extxrgb, 32, 1, 2, 3, 1
generate_jsimd_rgb_ycc_convert_neon extrgb, 24, 0, 1, 2, 0
generate_jsimd_rgb_ycc_convert_neon extbgr, 24, 2, 1, 0, 0
.purgem do_load
.purgem do_store
/*****************************************************************************/
/*
* Load data into workspace, applying unsigned->signed conversion
*
* TODO: can be combined with 'jsimd_fdct_ifast_neon' to get
* rid of VST1.16 instructions
*/
asm_function jsimd_convsamp_neon
SAMPLE_DATA .req x0
START_COL .req x1
WORKSPACE .req x2
TMP1 .req x9
TMP2 .req x10
TMP3 .req x11
TMP4 .req x12
TMP5 .req x13
TMP6 .req x14
TMP7 .req x15
TMP8 .req x4
TMPDUP .req w3
mov TMPDUP, #128
ldp TMP1, TMP2, [SAMPLE_DATA], 16
ldp TMP3, TMP4, [SAMPLE_DATA], 16
dup v0.8b, TMPDUP
add TMP1, TMP1, START_COL
add TMP2, TMP2, START_COL
ldp TMP5, TMP6, [SAMPLE_DATA], 16
add TMP3, TMP3, START_COL
add TMP4, TMP4, START_COL
ldp TMP7, TMP8, [SAMPLE_DATA], 16
add TMP5, TMP5, START_COL
add TMP6, TMP6, START_COL
ld1 {v16.8b}, [TMP1]
add TMP7, TMP7, START_COL
add TMP8, TMP8, START_COL
ld1 {v17.8b}, [TMP2]
usubl v16.8h, v16.8b, v0.8b
ld1 {v18.8b}, [TMP3]
usubl v17.8h, v17.8b, v0.8b
ld1 {v19.8b}, [TMP4]
usubl v18.8h, v18.8b, v0.8b
ld1 {v20.8b}, [TMP5]
usubl v19.8h, v19.8b, v0.8b
ld1 {v21.8b}, [TMP6]
st1 {v16.8h, v17.8h, v18.8h, v19.8h}, [WORKSPACE], 64
usubl v20.8h, v20.8b, v0.8b
ld1 {v22.8b}, [TMP7]
usubl v21.8h, v21.8b, v0.8b
ld1 {v23.8b}, [TMP8]
usubl v22.8h, v22.8b, v0.8b
usubl v23.8h, v23.8b, v0.8b
st1 {v20.8h, v21.8h, v22.8h, v23.8h}, [WORKSPACE], 64
br x30
.unreq SAMPLE_DATA
.unreq START_COL
.unreq WORKSPACE
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMP4
.unreq TMP5
.unreq TMP6
.unreq TMP7
.unreq TMP8
.unreq TMPDUP
/*****************************************************************************/
/*
* jsimd_fdct_islow_neon
*
* This file contains a slow-but-accurate integer implementation of the
* forward DCT (Discrete Cosine Transform). The following code is based
* directly on the IJG''s original jfdctint.c; see the jfdctint.c for
* more details.
*
* TODO: can be combined with 'jsimd_convsamp_neon' to get
* rid of a bunch of VLD1.16 instructions
*/
#define CONST_BITS 13
#define PASS1_BITS 2
#define DESCALE_P1 (CONST_BITS-PASS1_BITS)
#define DESCALE_P2 (CONST_BITS+PASS1_BITS)
#define F_0_298 2446 /* FIX(0.298631336) */
#define F_0_390 3196 /* FIX(0.390180644) */
#define F_0_541 4433 /* FIX(0.541196100) */
#define F_0_765 6270 /* FIX(0.765366865) */
#define F_0_899 7373 /* FIX(0.899976223) */
#define F_1_175 9633 /* FIX(1.175875602) */
#define F_1_501 12299 /* FIX(1.501321110) */
#define F_1_847 15137 /* FIX(1.847759065) */
#define F_1_961 16069 /* FIX(1.961570560) */
#define F_2_053 16819 /* FIX(2.053119869) */
#define F_2_562 20995 /* FIX(2.562915447) */
#define F_3_072 25172 /* FIX(3.072711026) */
.balign 16
Ljsimd_fdct_islow_neon_consts:
.short F_0_298
.short -F_0_390
.short F_0_541
.short F_0_765
.short - F_0_899
.short F_1_175
.short F_1_501
.short - F_1_847
.short - F_1_961
.short F_2_053
.short - F_2_562
.short F_3_072
.short 0 /* padding */
.short 0
.short 0
.short 0
#undef F_0_298
#undef F_0_390
#undef F_0_541
#undef F_0_765
#undef F_0_899
#undef F_1_175
#undef F_1_501
#undef F_1_847
#undef F_1_961
#undef F_2_053
#undef F_2_562
#undef F_3_072
#define XFIX_P_0_298 v0.h[0]
#define XFIX_N_0_390 v0.h[1]
#define XFIX_P_0_541 v0.h[2]
#define XFIX_P_0_765 v0.h[3]
#define XFIX_N_0_899 v0.h[4]
#define XFIX_P_1_175 v0.h[5]
#define XFIX_P_1_501 v0.h[6]
#define XFIX_N_1_847 v0.h[7]
#define XFIX_N_1_961 v1.h[0]
#define XFIX_P_2_053 v1.h[1]
#define XFIX_N_2_562 v1.h[2]
#define XFIX_P_3_072 v1.h[3]
asm_function jsimd_fdct_islow_neon
DATA .req x0
TMP .req x9
/* Load constants */
adr TMP, Ljsimd_fdct_islow_neon_consts
ld1 {v0.8h, v1.8h}, [TMP]
/* Save NEON registers */
sub sp, sp, #64
st1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
/* Load all DATA into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 | v16.8h
* 1 | d18 | d19 | v17.8h
* 2 | d20 | d21 | v18.8h
* 3 | d22 | d23 | v19.8h
* 4 | d24 | d25 | v20.8h
* 5 | d26 | d27 | v21.8h
* 6 | d28 | d29 | v22.8h
* 7 | d30 | d31 | v23.8h
*/
ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [DATA], 64
ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [DATA]
sub DATA, DATA, #64
/* Transpose */
transpose_8x8 v16, v17, v18, v19, v20, v21, v22, v23, v31, v2, v3, v4
/* 1-D FDCT */
add v24.8h, v16.8h, v23.8h /* tmp0 = dataptr[0] + dataptr[7]; */
sub v31.8h, v16.8h, v23.8h /* tmp7 = dataptr[0] - dataptr[7]; */
add v25.8h, v17.8h, v22.8h /* tmp1 = dataptr[1] + dataptr[6]; */
sub v30.8h, v17.8h, v22.8h /* tmp6 = dataptr[1] - dataptr[6]; */
add v26.8h, v18.8h, v21.8h /* tmp2 = dataptr[2] + dataptr[5]; */
sub v29.8h, v18.8h, v21.8h /* tmp5 = dataptr[2] - dataptr[5]; */
add v27.8h, v19.8h, v20.8h /* tmp3 = dataptr[3] + dataptr[4]; */
sub v28.8h, v19.8h, v20.8h /* tmp4 = dataptr[3] - dataptr[4]; */
/* even part */
add v8.8h, v24.8h, v27.8h /* tmp10 = tmp0 + tmp3; */
sub v9.8h, v24.8h, v27.8h /* tmp13 = tmp0 - tmp3; */
add v10.8h, v25.8h, v26.8h /* tmp11 = tmp1 + tmp2; */
sub v11.8h, v25.8h, v26.8h /* tmp12 = tmp1 - tmp2; */
add v16.8h, v8.8h, v10.8h /* tmp10 + tmp11 */
sub v20.8h, v8.8h, v10.8h /* tmp10 - tmp11 */
add v18.8h, v11.8h, v9.8h /* tmp12 + tmp13 */
shl v16.8h, v16.8h, #PASS1_BITS /* dataptr[0] = (DCTELEM) LEFT_SHIFT(tmp10 + tmp11, PASS1_BITS); */
shl v20.8h, v20.8h, #PASS1_BITS /* dataptr[4] = (DCTELEM) LEFT_SHIFT(tmp10 - tmp11, PASS1_BITS); */
smull2 v24.4s, v18.8h, XFIX_P_0_541 /* z1 hi = MULTIPLY(tmp12 + tmp13, XFIX_P_0_541); */
smull v18.4s, v18.4h, XFIX_P_0_541 /* z1 lo = MULTIPLY(tmp12 + tmp13, XFIX_P_0_541); */
mov v22.16b, v18.16b
mov v25.16b, v24.16b
smlal v18.4s, v9.4h, XFIX_P_0_765 /* lo z1 + MULTIPLY(tmp13, XFIX_P_0_765) */
smlal2 v24.4s, v9.8h, XFIX_P_0_765 /* hi z1 + MULTIPLY(tmp13, XFIX_P_0_765) */
smlal v22.4s, v11.4h, XFIX_N_1_847 /* lo z1 + MULTIPLY(tmp12, XFIX_N_1_847) */
smlal2 v25.4s, v11.8h, XFIX_N_1_847 /* hi z1 + MULTIPLY(tmp12, XFIX_N_1_847) */
rshrn v18.4h, v18.4s, #DESCALE_P1
rshrn v22.4h, v22.4s, #DESCALE_P1
rshrn2 v18.8h, v24.4s, #DESCALE_P1 /* dataptr[2] = (DCTELEM) DESCALE(z1 + MULTIPLY(tmp13, XFIX_P_0_765), CONST_BITS-PASS1_BITS); */
rshrn2 v22.8h, v25.4s, #DESCALE_P1 /* dataptr[6] = (DCTELEM) DESCALE(z1 + MULTIPLY(tmp12, XFIX_N_1_847), CONST_BITS-PASS1_BITS); */
/* Odd part */
add v8.8h, v28.8h, v31.8h /* z1 = tmp4 + tmp7; */
add v9.8h, v29.8h, v30.8h /* z2 = tmp5 + tmp6; */
add v10.8h, v28.8h, v30.8h /* z3 = tmp4 + tmp6; */
add v11.8h, v29.8h, v31.8h /* z4 = tmp5 + tmp7; */
smull v4.4s, v10.4h, XFIX_P_1_175 /* z5 lo = z3 lo * XFIX_P_1_175 */
smull2 v5.4s, v10.8h, XFIX_P_1_175
smlal v4.4s, v11.4h, XFIX_P_1_175 /* z5 = MULTIPLY(z3 + z4, FIX_1_175875602); */
smlal2 v5.4s, v11.8h, XFIX_P_1_175
smull2 v24.4s, v28.8h, XFIX_P_0_298
smull2 v25.4s, v29.8h, XFIX_P_2_053
smull2 v26.4s, v30.8h, XFIX_P_3_072
smull2 v27.4s, v31.8h, XFIX_P_1_501
smull v28.4s, v28.4h, XFIX_P_0_298 /* tmp4 = MULTIPLY(tmp4, FIX_0_298631336); */
smull v29.4s, v29.4h, XFIX_P_2_053 /* tmp5 = MULTIPLY(tmp5, FIX_2_053119869); */
smull v30.4s, v30.4h, XFIX_P_3_072 /* tmp6 = MULTIPLY(tmp6, FIX_3_072711026); */
smull v31.4s, v31.4h, XFIX_P_1_501 /* tmp7 = MULTIPLY(tmp7, FIX_1_501321110); */
smull2 v12.4s, v8.8h, XFIX_N_0_899
smull2 v13.4s, v9.8h, XFIX_N_2_562
smull2 v14.4s, v10.8h, XFIX_N_1_961
smull2 v15.4s, v11.8h, XFIX_N_0_390
smull v8.4s, v8.4h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223); */
smull v9.4s, v9.4h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447); */
smull v10.4s, v10.4h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560); */
smull v11.4s, v11.4h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644); */
add v10.4s, v10.4s, v4.4s /* z3 += z5 */
add v14.4s, v14.4s, v5.4s
add v11.4s, v11.4s, v4.4s /* z4 += z5 */
add v15.4s, v15.4s, v5.4s
add v28.4s, v28.4s, v8.4s /* tmp4 += z1 */
add v24.4s, v24.4s, v12.4s
add v29.4s, v29.4s, v9.4s /* tmp5 += z2 */
add v25.4s, v25.4s, v13.4s
add v30.4s, v30.4s, v10.4s /* tmp6 += z3 */
add v26.4s, v26.4s, v14.4s
add v31.4s, v31.4s, v11.4s /* tmp7 += z4 */
add v27.4s, v27.4s, v15.4s
add v28.4s, v28.4s, v10.4s /* tmp4 += z3 */
add v24.4s, v24.4s, v14.4s
add v29.4s, v29.4s, v11.4s /* tmp5 += z4 */
add v25.4s, v25.4s, v15.4s
add v30.4s, v30.4s, v9.4s /* tmp6 += z2 */
add v26.4s, v26.4s, v13.4s
add v31.4s, v31.4s, v8.4s /* tmp7 += z1 */
add v27.4s, v27.4s, v12.4s
rshrn v23.4h, v28.4s, #DESCALE_P1
rshrn v21.4h, v29.4s, #DESCALE_P1
rshrn v19.4h, v30.4s, #DESCALE_P1
rshrn v17.4h, v31.4s, #DESCALE_P1
rshrn2 v23.8h, v24.4s, #DESCALE_P1 /* dataptr[7] = (DCTELEM) DESCALE(tmp4 + z1 + z3, CONST_BITS-PASS1_BITS); */
rshrn2 v21.8h, v25.4s, #DESCALE_P1 /* dataptr[5] = (DCTELEM) DESCALE(tmp5 + z2 + z4, CONST_BITS-PASS1_BITS); */
rshrn2 v19.8h, v26.4s, #DESCALE_P1 /* dataptr[3] = (DCTELEM) DESCALE(tmp6 + z2 + z3, CONST_BITS-PASS1_BITS); */
rshrn2 v17.8h, v27.4s, #DESCALE_P1 /* dataptr[1] = (DCTELEM) DESCALE(tmp7 + z1 + z4, CONST_BITS-PASS1_BITS); */
/* Transpose */
transpose_8x8 v16, v17, v18, v19, v20, v21, v22, v23, v31, v2, v3, v4
/* 1-D FDCT */
add v24.8h, v16.8h, v23.8h /* tmp0 = dataptr[0] + dataptr[7]; */
sub v31.8h, v16.8h, v23.8h /* tmp7 = dataptr[0] - dataptr[7]; */
add v25.8h, v17.8h, v22.8h /* tmp1 = dataptr[1] + dataptr[6]; */
sub v30.8h, v17.8h, v22.8h /* tmp6 = dataptr[1] - dataptr[6]; */
add v26.8h, v18.8h, v21.8h /* tmp2 = dataptr[2] + dataptr[5]; */
sub v29.8h, v18.8h, v21.8h /* tmp5 = dataptr[2] - dataptr[5]; */
add v27.8h, v19.8h, v20.8h /* tmp3 = dataptr[3] + dataptr[4]; */
sub v28.8h, v19.8h, v20.8h /* tmp4 = dataptr[3] - dataptr[4]; */
/* even part */
add v8.8h, v24.8h, v27.8h /* tmp10 = tmp0 + tmp3; */
sub v9.8h, v24.8h, v27.8h /* tmp13 = tmp0 - tmp3; */
add v10.8h, v25.8h, v26.8h /* tmp11 = tmp1 + tmp2; */
sub v11.8h, v25.8h, v26.8h /* tmp12 = tmp1 - tmp2; */
add v16.8h, v8.8h, v10.8h /* tmp10 + tmp11 */
sub v20.8h, v8.8h, v10.8h /* tmp10 - tmp11 */
add v18.8h, v11.8h, v9.8h /* tmp12 + tmp13 */
srshr v16.8h, v16.8h, #PASS1_BITS /* dataptr[0] = (DCTELEM) DESCALE(tmp10 + tmp11, PASS1_BITS); */
srshr v20.8h, v20.8h, #PASS1_BITS /* dataptr[4] = (DCTELEM) DESCALE(tmp10 - tmp11, PASS1_BITS); */
smull2 v24.4s, v18.8h, XFIX_P_0_541 /* z1 hi = MULTIPLY(tmp12 + tmp13, XFIX_P_0_541); */
smull v18.4s, v18.4h, XFIX_P_0_541 /* z1 lo = MULTIPLY(tmp12 + tmp13, XFIX_P_0_541); */
mov v22.16b, v18.16b
mov v25.16b, v24.16b
smlal v18.4s, v9.4h, XFIX_P_0_765 /* lo z1 + MULTIPLY(tmp13, XFIX_P_0_765) */
smlal2 v24.4s, v9.8h, XFIX_P_0_765 /* hi z1 + MULTIPLY(tmp13, XFIX_P_0_765) */
smlal v22.4s, v11.4h, XFIX_N_1_847 /* lo z1 + MULTIPLY(tmp12, XFIX_N_1_847) */
smlal2 v25.4s, v11.8h, XFIX_N_1_847 /* hi z1 + MULTIPLY(tmp12, XFIX_N_1_847) */
rshrn v18.4h, v18.4s, #DESCALE_P2
rshrn v22.4h, v22.4s, #DESCALE_P2
rshrn2 v18.8h, v24.4s, #DESCALE_P2 /* dataptr[2] = (DCTELEM) DESCALE(z1 + MULTIPLY(tmp13, XFIX_P_0_765), CONST_BITS-PASS1_BITS); */
rshrn2 v22.8h, v25.4s, #DESCALE_P2 /* dataptr[6] = (DCTELEM) DESCALE(z1 + MULTIPLY(tmp12, XFIX_N_1_847), CONST_BITS-PASS1_BITS); */
/* Odd part */
add v8.8h, v28.8h, v31.8h /* z1 = tmp4 + tmp7; */
add v9.8h, v29.8h, v30.8h /* z2 = tmp5 + tmp6; */
add v10.8h, v28.8h, v30.8h /* z3 = tmp4 + tmp6; */
add v11.8h, v29.8h, v31.8h /* z4 = tmp5 + tmp7; */
smull v4.4s, v10.4h, XFIX_P_1_175 /* z5 lo = z3 lo * XFIX_P_1_175 */
smull2 v5.4s, v10.8h, XFIX_P_1_175
smlal v4.4s, v11.4h, XFIX_P_1_175 /* z5 = MULTIPLY(z3 + z4, FIX_1_175875602); */
smlal2 v5.4s, v11.8h, XFIX_P_1_175
smull2 v24.4s, v28.8h, XFIX_P_0_298
smull2 v25.4s, v29.8h, XFIX_P_2_053
smull2 v26.4s, v30.8h, XFIX_P_3_072
smull2 v27.4s, v31.8h, XFIX_P_1_501
smull v28.4s, v28.4h, XFIX_P_0_298 /* tmp4 = MULTIPLY(tmp4, FIX_0_298631336); */
smull v29.4s, v29.4h, XFIX_P_2_053 /* tmp5 = MULTIPLY(tmp5, FIX_2_053119869); */
smull v30.4s, v30.4h, XFIX_P_3_072 /* tmp6 = MULTIPLY(tmp6, FIX_3_072711026); */
smull v31.4s, v31.4h, XFIX_P_1_501 /* tmp7 = MULTIPLY(tmp7, FIX_1_501321110); */
smull2 v12.4s, v8.8h, XFIX_N_0_899
smull2 v13.4s, v9.8h, XFIX_N_2_562
smull2 v14.4s, v10.8h, XFIX_N_1_961
smull2 v15.4s, v11.8h, XFIX_N_0_390
smull v8.4s, v8.4h, XFIX_N_0_899 /* z1 = MULTIPLY(z1, - FIX_0_899976223); */
smull v9.4s, v9.4h, XFIX_N_2_562 /* z2 = MULTIPLY(z2, - FIX_2_562915447); */
smull v10.4s, v10.4h, XFIX_N_1_961 /* z3 = MULTIPLY(z3, - FIX_1_961570560); */
smull v11.4s, v11.4h, XFIX_N_0_390 /* z4 = MULTIPLY(z4, - FIX_0_390180644); */
add v10.4s, v10.4s, v4.4s
add v14.4s, v14.4s, v5.4s
add v11.4s, v11.4s, v4.4s
add v15.4s, v15.4s, v5.4s
add v28.4s, v28.4s, v8.4s /* tmp4 += z1 */
add v24.4s, v24.4s, v12.4s
add v29.4s, v29.4s, v9.4s /* tmp5 += z2 */
add v25.4s, v25.4s, v13.4s
add v30.4s, v30.4s, v10.4s /* tmp6 += z3 */
add v26.4s, v26.4s, v14.4s
add v31.4s, v31.4s, v11.4s /* tmp7 += z4 */
add v27.4s, v27.4s, v15.4s
add v28.4s, v28.4s, v10.4s /* tmp4 += z3 */
add v24.4s, v24.4s, v14.4s
add v29.4s, v29.4s, v11.4s /* tmp5 += z4 */
add v25.4s, v25.4s, v15.4s
add v30.4s, v30.4s, v9.4s /* tmp6 += z2 */
add v26.4s, v26.4s, v13.4s
add v31.4s, v31.4s, v8.4s /* tmp7 += z1 */
add v27.4s, v27.4s, v12.4s
rshrn v23.4h, v28.4s, #DESCALE_P2
rshrn v21.4h, v29.4s, #DESCALE_P2
rshrn v19.4h, v30.4s, #DESCALE_P2
rshrn v17.4h, v31.4s, #DESCALE_P2
rshrn2 v23.8h, v24.4s, #DESCALE_P2 /* dataptr[7] = (DCTELEM) DESCALE(tmp4 + z1 + z3, CONST_BITS-PASS1_BITS); */
rshrn2 v21.8h, v25.4s, #DESCALE_P2 /* dataptr[5] = (DCTELEM) DESCALE(tmp5 + z2 + z4, CONST_BITS-PASS1_BITS); */
rshrn2 v19.8h, v26.4s, #DESCALE_P2 /* dataptr[3] = (DCTELEM) DESCALE(tmp6 + z2 + z3, CONST_BITS-PASS1_BITS); */
rshrn2 v17.8h, v27.4s, #DESCALE_P2 /* dataptr[1] = (DCTELEM) DESCALE(tmp7 + z1 + z4, CONST_BITS-PASS1_BITS); */
/* store results */
st1 {v16.8h, v17.8h, v18.8h, v19.8h}, [DATA], 64
st1 {v20.8h, v21.8h, v22.8h, v23.8h}, [DATA]
/* Restore NEON registers */
sub sp, sp, #64
ld1 {v8.8b, v9.8b, v10.8b, v11.8b}, [sp], 32
ld1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
br x30
.unreq DATA
.unreq TMP
#undef XFIX_P_0_298
#undef XFIX_N_0_390
#undef XFIX_P_0_541
#undef XFIX_P_0_765
#undef XFIX_N_0_899
#undef XFIX_P_1_175
#undef XFIX_P_1_501
#undef XFIX_N_1_847
#undef XFIX_N_1_961
#undef XFIX_P_2_053
#undef XFIX_N_2_562
#undef XFIX_P_3_072
/*****************************************************************************/
/*
* jsimd_fdct_ifast_neon
*
* This function contains a fast, not so accurate integer implementation of
* the forward DCT (Discrete Cosine Transform). It uses the same calculations
* and produces exactly the same output as IJG's original 'jpeg_fdct_ifast'
* function from jfdctfst.c
*
* TODO: can be combined with 'jsimd_convsamp_neon' to get
* rid of a bunch of VLD1.16 instructions
*/
#undef XFIX_0_541196100
#define XFIX_0_382683433 v0.h[0]
#define XFIX_0_541196100 v0.h[1]
#define XFIX_0_707106781 v0.h[2]
#define XFIX_1_306562965 v0.h[3]
.balign 16
Ljsimd_fdct_ifast_neon_consts:
.short (98 * 128) /* XFIX_0_382683433 */
.short (139 * 128) /* XFIX_0_541196100 */
.short (181 * 128) /* XFIX_0_707106781 */
.short (334 * 128 - 256 * 128) /* XFIX_1_306562965 */
asm_function jsimd_fdct_ifast_neon
DATA .req x0
TMP .req x9
/* Load constants */
adr TMP, Ljsimd_fdct_ifast_neon_consts
ld1 {v0.4h}, [TMP]
/* Load all DATA into NEON registers with the following allocation:
* 0 1 2 3 | 4 5 6 7
* ---------+--------
* 0 | d16 | d17 | v0.8h
* 1 | d18 | d19 | q9
* 2 | d20 | d21 | q10
* 3 | d22 | d23 | q11
* 4 | d24 | d25 | q12
* 5 | d26 | d27 | q13
* 6 | d28 | d29 | q14
* 7 | d30 | d31 | q15
*/
ld1 {v16.8h, v17.8h, v18.8h, v19.8h}, [DATA], 64
ld1 {v20.8h, v21.8h, v22.8h, v23.8h}, [DATA]
mov TMP, #2
sub DATA, DATA, #64
1:
/* Transpose */
transpose_8x8 v16, v17, v18, v19, v20, v21, v22, v23, v1, v2, v3, v4
subs TMP, TMP, #1
/* 1-D FDCT */
add v4.8h, v19.8h, v20.8h
sub v20.8h, v19.8h, v20.8h
sub v28.8h, v18.8h, v21.8h
add v18.8h, v18.8h, v21.8h
sub v29.8h, v17.8h, v22.8h
add v17.8h, v17.8h, v22.8h
sub v21.8h, v16.8h, v23.8h
add v16.8h, v16.8h, v23.8h
sub v6.8h, v17.8h, v18.8h
sub v7.8h, v16.8h, v4.8h
add v5.8h, v17.8h, v18.8h
add v6.8h, v6.8h, v7.8h
add v4.8h, v16.8h, v4.8h
sqdmulh v6.8h, v6.8h, XFIX_0_707106781
add v19.8h, v20.8h, v28.8h
add v16.8h, v4.8h, v5.8h
sub v20.8h, v4.8h, v5.8h
add v5.8h, v28.8h, v29.8h
add v29.8h, v29.8h, v21.8h
sqdmulh v5.8h, v5.8h, XFIX_0_707106781
sub v28.8h, v19.8h, v29.8h
add v18.8h, v7.8h, v6.8h
sqdmulh v28.8h, v28.8h, XFIX_0_382683433
sub v22.8h, v7.8h, v6.8h
sqdmulh v19.8h, v19.8h, XFIX_0_541196100
sqdmulh v7.8h, v29.8h, XFIX_1_306562965
add v6.8h, v21.8h, v5.8h
sub v5.8h, v21.8h, v5.8h
add v29.8h, v29.8h, v28.8h
add v19.8h, v19.8h, v28.8h
add v29.8h, v29.8h, v7.8h
add v21.8h, v5.8h, v19.8h
sub v19.8h, v5.8h, v19.8h
add v17.8h, v6.8h, v29.8h
sub v23.8h, v6.8h, v29.8h
b.ne 1b
/* store results */
st1 {v16.8h, v17.8h, v18.8h, v19.8h}, [DATA], 64
st1 {v20.8h, v21.8h, v22.8h, v23.8h}, [DATA]
br x30
.unreq DATA
.unreq TMP
#undef XFIX_0_382683433
#undef XFIX_0_541196100
#undef XFIX_0_707106781
#undef XFIX_1_306562965
/*****************************************************************************/
/*
* GLOBAL(void)
* jsimd_quantize_neon (JCOEFPTR coef_block, DCTELEM *divisors,
* DCTELEM *workspace);
*
*/
asm_function jsimd_quantize_neon
COEF_BLOCK .req x0
DIVISORS .req x1
WORKSPACE .req x2
RECIPROCAL .req DIVISORS
CORRECTION .req x9
SHIFT .req x10
LOOP_COUNT .req x11
mov LOOP_COUNT, #2
add CORRECTION, DIVISORS, #(64 * 2)
add SHIFT, DIVISORS, #(64 * 6)
1:
subs LOOP_COUNT, LOOP_COUNT, #1
ld1 {v0.8h, v1.8h, v2.8h, v3.8h}, [WORKSPACE], 64
ld1 {v4.8h, v5.8h, v6.8h, v7.8h}, [CORRECTION], 64
abs v20.8h, v0.8h
abs v21.8h, v1.8h
abs v22.8h, v2.8h
abs v23.8h, v3.8h
ld1 {v28.8h, v29.8h, v30.8h, v31.8h}, [RECIPROCAL], 64
add v20.8h, v20.8h, v4.8h /* add correction */
add v21.8h, v21.8h, v5.8h
add v22.8h, v22.8h, v6.8h
add v23.8h, v23.8h, v7.8h
umull v4.4s, v20.4h, v28.4h /* multiply by reciprocal */
umull2 v16.4s, v20.8h, v28.8h
umull v5.4s, v21.4h, v29.4h
umull2 v17.4s, v21.8h, v29.8h
umull v6.4s, v22.4h, v30.4h /* multiply by reciprocal */
umull2 v18.4s, v22.8h, v30.8h
umull v7.4s, v23.4h, v31.4h
umull2 v19.4s, v23.8h, v31.8h
ld1 {v24.8h, v25.8h, v26.8h, v27.8h}, [SHIFT], 64
shrn v4.4h, v4.4s, #16
shrn v5.4h, v5.4s, #16
shrn v6.4h, v6.4s, #16
shrn v7.4h, v7.4s, #16
shrn2 v4.8h, v16.4s, #16
shrn2 v5.8h, v17.4s, #16
shrn2 v6.8h, v18.4s, #16
shrn2 v7.8h, v19.4s, #16
neg v24.8h, v24.8h
neg v25.8h, v25.8h
neg v26.8h, v26.8h
neg v27.8h, v27.8h
sshr v0.8h, v0.8h, #15 /* extract sign */
sshr v1.8h, v1.8h, #15
sshr v2.8h, v2.8h, #15
sshr v3.8h, v3.8h, #15
ushl v4.8h, v4.8h, v24.8h /* shift */
ushl v5.8h, v5.8h, v25.8h
ushl v6.8h, v6.8h, v26.8h
ushl v7.8h, v7.8h, v27.8h
eor v4.16b, v4.16b, v0.16b /* restore sign */
eor v5.16b, v5.16b, v1.16b
eor v6.16b, v6.16b, v2.16b
eor v7.16b, v7.16b, v3.16b
sub v4.8h, v4.8h, v0.8h
sub v5.8h, v5.8h, v1.8h
sub v6.8h, v6.8h, v2.8h
sub v7.8h, v7.8h, v3.8h
st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [COEF_BLOCK], 64
b.ne 1b
br x30 /* return */
.unreq COEF_BLOCK
.unreq DIVISORS
.unreq WORKSPACE
.unreq RECIPROCAL
.unreq CORRECTION
.unreq SHIFT
.unreq LOOP_COUNT
/*****************************************************************************/
/*
* Downsample pixel values of a single component.
* This version handles the common case of 2:1 horizontal and 1:1 vertical,
* without smoothing.
*
* GLOBAL(void)
* jsimd_h2v1_downsample_neon (JDIMENSION image_width, int max_v_samp_factor,
* JDIMENSION v_samp_factor,
* JDIMENSION width_blocks, JSAMPARRAY input_data,
* JSAMPARRAY output_data);
*/
.balign 16
Ljsimd_h2_downsample_neon_consts:
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F /* diff 0 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0E /* diff 1 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0D, 0x0D /* diff 2 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0C, 0x0C, 0x0C /* diff 3 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B, 0x0B /* diff 4 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A, 0x0A /* diff 5 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09 /* diff 6 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08 /* diff 7 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07 /* diff 8 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x06, \
0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06 /* diff 9 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x05, 0x05, \
0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05 /* diff 10 */
.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x04, 0x04, 0x04, \
0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04 /* diff 11 */
.byte 0x00, 0x01, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, \
0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 /* diff 12 */
.byte 0x00, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, \
0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 /* diff 13 */
.byte 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, \
0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 /* diff 14 */
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* diff 15 */
asm_function jsimd_h2v1_downsample_neon
IMAGE_WIDTH .req x0
MAX_V_SAMP .req x1
V_SAMP .req x2
BLOCK_WIDTH .req x3
INPUT_DATA .req x4
OUTPUT_DATA .req x5
OUTPTR .req x9
INPTR .req x10
TMP1 .req x11
TMP2 .req x12
TMP3 .req x13
TMPDUP .req w15
mov TMPDUP, #0x10000
lsl TMP2, BLOCK_WIDTH, #4
sub TMP2, TMP2, IMAGE_WIDTH
adr TMP3, Ljsimd_h2_downsample_neon_consts
add TMP3, TMP3, TMP2, lsl #4
dup v16.4s, TMPDUP
ld1 {v18.16b}, [TMP3]
1: /* row loop */
ldr INPTR, [INPUT_DATA], #8
ldr OUTPTR, [OUTPUT_DATA], #8
subs TMP1, BLOCK_WIDTH, #1
b.eq 3f
2: /* columns */
ld1 {v0.16b}, [INPTR], #16
mov v4.16b, v16.16b
subs TMP1, TMP1, #1
uadalp v4.8h, v0.16b
shrn v6.8b, v4.8h, #1
st1 {v6.8b}, [OUTPTR], #8
b.ne 2b
3: /* last columns */
ld1 {v0.16b}, [INPTR]
mov v4.16b, v16.16b
subs V_SAMP, V_SAMP, #1
/* expand right */
tbl v2.16b, {v0.16b}, v18.16b
uadalp v4.8h, v2.16b
shrn v6.8b, v4.8h, #1
st1 {v6.8b}, [OUTPTR], #8
b.ne 1b
br x30
.unreq IMAGE_WIDTH
.unreq MAX_V_SAMP
.unreq V_SAMP
.unreq BLOCK_WIDTH
.unreq INPUT_DATA
.unreq OUTPUT_DATA
.unreq OUTPTR
.unreq INPTR
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMPDUP
/*****************************************************************************/
/*
* Downsample pixel values of a single component.
* This version handles the common case of 2:1 horizontal and 2:1 vertical,
* without smoothing.
*
* GLOBAL(void)
* jsimd_h2v2_downsample_neon (JDIMENSION image_width, int max_v_samp_factor,
* JDIMENSION v_samp_factor, JDIMENSION width_blocks,
* JSAMPARRAY input_data, JSAMPARRAY output_data);
*/
.balign 16
asm_function jsimd_h2v2_downsample_neon
IMAGE_WIDTH .req x0
MAX_V_SAMP .req x1
V_SAMP .req x2
BLOCK_WIDTH .req x3
INPUT_DATA .req x4
OUTPUT_DATA .req x5
OUTPTR .req x9
INPTR0 .req x10
INPTR1 .req x14
TMP1 .req x11
TMP2 .req x12
TMP3 .req x13
TMPDUP .req w15
mov TMPDUP, #1
lsl TMP2, BLOCK_WIDTH, #4
lsl TMPDUP, TMPDUP, #17
sub TMP2, TMP2, IMAGE_WIDTH
adr TMP3, Ljsimd_h2_downsample_neon_consts
orr TMPDUP, TMPDUP, #1
add TMP3, TMP3, TMP2, lsl #4
dup v16.4s, TMPDUP
ld1 {v18.16b}, [TMP3]
1: /* row loop */
ldr INPTR0, [INPUT_DATA], #8
ldr OUTPTR, [OUTPUT_DATA], #8
ldr INPTR1, [INPUT_DATA], #8
subs TMP1, BLOCK_WIDTH, #1
b.eq 3f
2: /* columns */
ld1 {v0.16b}, [INPTR0], #16
ld1 {v1.16b}, [INPTR1], #16
mov v4.16b, v16.16b
subs TMP1, TMP1, #1
uadalp v4.8h, v0.16b
uadalp v4.8h, v1.16b
shrn v6.8b, v4.8h, #2
st1 {v6.8b}, [OUTPTR], #8
b.ne 2b
3: /* last columns */
ld1 {v0.16b}, [INPTR0], #16
ld1 {v1.16b}, [INPTR1], #16
mov v4.16b, v16.16b
subs V_SAMP, V_SAMP, #1
/* expand right */
tbl v2.16b, {v0.16b}, v18.16b
tbl v3.16b, {v1.16b}, v18.16b
uadalp v4.8h, v2.16b
uadalp v4.8h, v3.16b
shrn v6.8b, v4.8h, #2
st1 {v6.8b}, [OUTPTR], #8
b.ne 1b
br x30
.unreq IMAGE_WIDTH
.unreq MAX_V_SAMP
.unreq V_SAMP
.unreq BLOCK_WIDTH
.unreq INPUT_DATA
.unreq OUTPUT_DATA
.unreq OUTPTR
.unreq INPTR0
.unreq INPTR1
.unreq TMP1
.unreq TMP2
.unreq TMP3
.unreq TMPDUP
/*****************************************************************************/
/*
* GLOBAL(JOCTET*)
* jsimd_huff_encode_one_block (working_state *state, JOCTET *buffer,
* JCOEFPTR block, int last_dc_val,
* c_derived_tbl *dctbl, c_derived_tbl *actbl)
*
*/
BUFFER .req x1
PUT_BUFFER .req x6
PUT_BITS .req x7
PUT_BITSw .req w7
.macro emit_byte
sub PUT_BITS, PUT_BITS, #0x8
lsr x19, PUT_BUFFER, PUT_BITS
uxtb w19, w19
strb w19, [BUFFER, #1]!
cmp w19, #0xff
b.ne 14f
strb wzr, [BUFFER, #1]!
14:
.endm
.macro put_bits CODE, SIZE
lsl PUT_BUFFER, PUT_BUFFER, \SIZE
add PUT_BITS, PUT_BITS, \SIZE
orr PUT_BUFFER, PUT_BUFFER, \CODE
.endm
.macro checkbuf31
cmp PUT_BITS, #0x20
b.lt 31f
emit_byte
emit_byte
emit_byte
emit_byte
31:
.endm
.macro checkbuf47
cmp PUT_BITS, #0x30
b.lt 47f
emit_byte
emit_byte
emit_byte
emit_byte
emit_byte
emit_byte
47:
.endm
.macro generate_jsimd_huff_encode_one_block fast_tbl
.balign 16
.if \fast_tbl == 1
Ljsimd_huff_encode_one_block_neon_consts:
.else
Ljsimd_huff_encode_one_block_neon_slowtbl_consts:
.endif
.byte 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, \
0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
.if \fast_tbl == 1
.byte 0, 1, 2, 3, 16, 17, 32, 33, \
18, 19, 4, 5, 6, 7, 20, 21 /* L0 => L3 : 4 lines OK */
.byte 34, 35, 48, 49, 255, 255, 50, 51, \
36, 37, 22, 23, 8, 9, 10, 11 /* L0 => L3 : 4 lines OK */
.byte 8, 9, 22, 23, 36, 37, 50, 51, \
255, 255, 255, 255, 255, 255, 52, 53 /* L1 => L4 : 4 lines OK */
.byte 54, 55, 40, 41, 26, 27, 12, 13, \
14, 15, 28, 29, 42, 43, 56, 57 /* L0 => L3 : 4 lines OK */
.byte 6, 7, 20, 21, 34, 35, 48, 49, \
50, 51, 36, 37, 22, 23, 8, 9 /* L4 => L7 : 4 lines OK */
.byte 42, 43, 28, 29, 14, 15, 30, 31, \
44, 45, 58, 59, 255, 255, 255, 255 /* L1 => L4 : 4 lines OK */
.byte 255, 255, 255, 255, 56, 57, 42, 43, \
28, 29, 14, 15, 30, 31, 44, 45 /* L3 => L6 : 4 lines OK */
.byte 26, 27, 40, 41, 42, 43, 28, 29, \
14, 15, 30, 31, 44, 45, 46, 47 /* L5 => L7 : 3 lines OK */
.byte 255, 255, 255, 255, 0, 1, 255, 255, \
255, 255, 255, 255, 255, 255, 255, 255 /* L4 : 1 lines OK */
.byte 255, 255, 255, 255, 255, 255, 255, 255, \
0, 1, 16, 17, 2, 3, 255, 255 /* L5 => L6 : 2 lines OK */
.byte 255, 255, 255, 255, 255, 255, 255, 255, \
255, 255, 255, 255, 8, 9, 22, 23 /* L5 => L6 : 2 lines OK */
.byte 4, 5, 6, 7, 255, 255, 255, 255, \
255, 255, 255, 255, 255, 255, 255, 255 /* L7 : 1 line OK */
.endif
.if \fast_tbl == 1
asm_function jsimd_huff_encode_one_block_neon
.else
asm_function jsimd_huff_encode_one_block_neon_slowtbl
.endif
sub sp, sp, 272
sub BUFFER, BUFFER, #0x1 /* BUFFER=buffer-- */
/* Save ARM registers */
stp x19, x20, [sp], 16
.if \fast_tbl == 1
adr x15, Ljsimd_huff_encode_one_block_neon_consts
.else
adr x15, Ljsimd_huff_encode_one_block_neon_slowtbl_consts
.endif
ldr PUT_BUFFER, [x0, #0x10]
ldr PUT_BITSw, [x0, #0x18]
ldrsh w12, [x2] /* load DC coeff in w12 */
/* prepare data */
.if \fast_tbl == 1
ld1 {v23.16b}, [x15], #16
ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x15], #64
ld1 {v4.16b, v5.16b, v6.16b, v7.16b}, [x15], #64
ld1 {v16.16b, v17.16b, v18.16b, v19.16b}, [x15], #64
ld1 {v24.16b, v25.16b, v26.16b, v27.16b}, [x2], #64
ld1 {v28.16b, v29.16b, v30.16b, v31.16b}, [x2], #64
sub w12, w12, w3 /* last_dc_val, not used afterwards */
/* ZigZag 8x8 */
tbl v0.16b, {v24.16b, v25.16b, v26.16b, v27.16b}, v0.16b
tbl v1.16b, {v24.16b, v25.16b, v26.16b, v27.16b}, v1.16b
tbl v2.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v2.16b
tbl v3.16b, {v24.16b, v25.16b, v26.16b, v27.16b}, v3.16b
tbl v4.16b, {v28.16b, v29.16b, v30.16b, v31.16b}, v4.16b
tbl v5.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
tbl v6.16b, {v27.16b, v28.16b, v29.16b, v30.16b}, v6.16b
tbl v7.16b, {v29.16b, v30.16b, v31.16b}, v7.16b
ins v0.h[0], w12
tbx v1.16b, {v28.16b}, v16.16b
tbx v2.16b, {v29.16b, v30.16b}, v17.16b
tbx v5.16b, {v29.16b, v30.16b}, v18.16b
tbx v6.16b, {v31.16b}, v19.16b
.else
add x13, x2, #0x22
sub w12, w12, w3 /* last_dc_val, not used afterwards */
ld1 {v23.16b}, [x15]
add x14, x2, #0x18
add x3, x2, #0x36
ins v0.h[0], w12
add x9, x2, #0x2
ld1 {v1.h}[0], [x13]
add x15, x2, #0x30
ld1 {v2.h}[0], [x14]
add x19, x2, #0x26
ld1 {v3.h}[0], [x3]
add x20, x2, #0x28
ld1 {v0.h}[1], [x9]
add x12, x2, #0x10
ld1 {v1.h}[1], [x15]
add x13, x2, #0x40
ld1 {v2.h}[1], [x19]
add x14, x2, #0x34
ld1 {v3.h}[1], [x20]
add x3, x2, #0x1a
ld1 {v0.h}[2], [x12]
add x9, x2, #0x20
ld1 {v1.h}[2], [x13]
add x15, x2, #0x32
ld1 {v2.h}[2], [x14]
add x19, x2, #0x42
ld1 {v3.h}[2], [x3]
add x20, x2, #0xc
ld1 {v0.h}[3], [x9]
add x12, x2, #0x12
ld1 {v1.h}[3], [x15]
add x13, x2, #0x24
ld1 {v2.h}[3], [x19]
add x14, x2, #0x50
ld1 {v3.h}[3], [x20]
add x3, x2, #0xe
ld1 {v0.h}[4], [x12]
add x9, x2, #0x4
ld1 {v1.h}[4], [x13]
add x15, x2, #0x16
ld1 {v2.h}[4], [x14]
add x19, x2, #0x60
ld1 {v3.h}[4], [x3]
add x20, x2, #0x1c
ld1 {v0.h}[5], [x9]
add x12, x2, #0x6
ld1 {v1.h}[5], [x15]
add x13, x2, #0x8
ld1 {v2.h}[5], [x19]
add x14, x2, #0x52
ld1 {v3.h}[5], [x20]
add x3, x2, #0x2a
ld1 {v0.h}[6], [x12]
add x9, x2, #0x14
ld1 {v1.h}[6], [x13]
add x15, x2, #0xa
ld1 {v2.h}[6], [x14]
add x19, x2, #0x44
ld1 {v3.h}[6], [x3]
add x20, x2, #0x38
ld1 {v0.h}[7], [x9]
add x12, x2, #0x46
ld1 {v1.h}[7], [x15]
add x13, x2, #0x3a
ld1 {v2.h}[7], [x19]
add x14, x2, #0x74
ld1 {v3.h}[7], [x20]
add x3, x2, #0x6a
ld1 {v4.h}[0], [x12]
add x9, x2, #0x54
ld1 {v5.h}[0], [x13]
add x15, x2, #0x2c
ld1 {v6.h}[0], [x14]
add x19, x2, #0x76
ld1 {v7.h}[0], [x3]
add x20, x2, #0x78
ld1 {v4.h}[1], [x9]
add x12, x2, #0x62
ld1 {v5.h}[1], [x15]
add x13, x2, #0x1e
ld1 {v6.h}[1], [x19]
add x14, x2, #0x68
ld1 {v7.h}[1], [x20]
add x3, x2, #0x7a
ld1 {v4.h}[2], [x12]
add x9, x2, #0x70
ld1 {v5.h}[2], [x13]
add x15, x2, #0x2e
ld1 {v6.h}[2], [x14]
add x19, x2, #0x5a
ld1 {v7.h}[2], [x3]
add x20, x2, #0x6c
ld1 {v4.h}[3], [x9]
add x12, x2, #0x72
ld1 {v5.h}[3], [x15]
add x13, x2, #0x3c
ld1 {v6.h}[3], [x19]
add x14, x2, #0x4c
ld1 {v7.h}[3], [x20]
add x3, x2, #0x5e
ld1 {v4.h}[4], [x12]
add x9, x2, #0x64
ld1 {v5.h}[4], [x13]
add x15, x2, #0x4a
ld1 {v6.h}[4], [x14]
add x19, x2, #0x3e
ld1 {v7.h}[4], [x3]
add x20, x2, #0x6e
ld1 {v4.h}[5], [x9]
add x12, x2, #0x56
ld1 {v5.h}[5], [x15]
add x13, x2, #0x58
ld1 {v6.h}[5], [x19]
add x14, x2, #0x4e
ld1 {v7.h}[5], [x20]
add x3, x2, #0x7c
ld1 {v4.h}[6], [x12]
add x9, x2, #0x48
ld1 {v5.h}[6], [x13]
add x15, x2, #0x66
ld1 {v6.h}[6], [x14]
add x19, x2, #0x5c
ld1 {v7.h}[6], [x3]
add x20, x2, #0x7e
ld1 {v4.h}[7], [x9]
ld1 {v5.h}[7], [x15]
ld1 {v6.h}[7], [x19]
ld1 {v7.h}[7], [x20]
.endif
cmlt v24.8h, v0.8h, #0
cmlt v25.8h, v1.8h, #0
cmlt v26.8h, v2.8h, #0
cmlt v27.8h, v3.8h, #0
cmlt v28.8h, v4.8h, #0
cmlt v29.8h, v5.8h, #0
cmlt v30.8h, v6.8h, #0
cmlt v31.8h, v7.8h, #0
abs v0.8h, v0.8h
abs v1.8h, v1.8h
abs v2.8h, v2.8h
abs v3.8h, v3.8h
abs v4.8h, v4.8h
abs v5.8h, v5.8h
abs v6.8h, v6.8h
abs v7.8h, v7.8h
eor v24.16b, v24.16b, v0.16b
eor v25.16b, v25.16b, v1.16b
eor v26.16b, v26.16b, v2.16b
eor v27.16b, v27.16b, v3.16b
eor v28.16b, v28.16b, v4.16b
eor v29.16b, v29.16b, v5.16b
eor v30.16b, v30.16b, v6.16b
eor v31.16b, v31.16b, v7.16b
cmeq v16.8h, v0.8h, #0
cmeq v17.8h, v1.8h, #0
cmeq v18.8h, v2.8h, #0
cmeq v19.8h, v3.8h, #0
cmeq v20.8h, v4.8h, #0
cmeq v21.8h, v5.8h, #0
cmeq v22.8h, v6.8h, #0
xtn v16.8b, v16.8h
xtn v18.8b, v18.8h
xtn v20.8b, v20.8h
xtn v22.8b, v22.8h
umov w14, v0.h[0]
xtn2 v16.16b, v17.8h
umov w13, v24.h[0]
xtn2 v18.16b, v19.8h
clz w14, w14
xtn2 v20.16b, v21.8h
lsl w13, w13, w14
cmeq v17.8h, v7.8h, #0
sub w12, w14, #32
xtn2 v22.16b, v17.8h
lsr w13, w13, w14
and v16.16b, v16.16b, v23.16b
neg w12, w12
and v18.16b, v18.16b, v23.16b
add x3, x4, #0x400 /* r1 = dctbl->ehufsi */
and v20.16b, v20.16b, v23.16b
add x15, sp, #0x80 /* x15 = t2 */
and v22.16b, v22.16b, v23.16b
ldr w10, [x4, x12, lsl #2]
addp v16.16b, v16.16b, v18.16b
ldrb w11, [x3, x12]
addp v20.16b, v20.16b, v22.16b
checkbuf47
addp v16.16b, v16.16b, v20.16b
put_bits x10, x11
addp v16.16b, v16.16b, v18.16b
checkbuf47
umov x9,v16.D[0]
put_bits x13, x12
cnt v17.8b, v16.8b
mvn x9, x9
addv B18, v17.8b
add x4, x5, #0x400 /* x4 = actbl->ehufsi */
umov w12, v18.b[0]
lsr x9, x9, #0x1 /* clear AC coeff */
ldr w13, [x5, #0x3c0] /* x13 = actbl->ehufco[0xf0] */
rbit x9, x9 /* x9 = index0 */
ldrb w14, [x4, #0xf0] /* x14 = actbl->ehufsi[0xf0] */
cmp w12, #(64-8)
mov x11, sp
b.lt 4f
cbz x9, 6f
st1 {v0.8h, v1.8h, v2.8h, v3.8h}, [x11], #64
st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x11], #64
st1 {v24.8h, v25.8h, v26.8h, v27.8h}, [x11], #64
st1 {v28.8h, v29.8h, v30.8h, v31.8h}, [x11], #64
1:
clz x2, x9
add x15, x15, x2, lsl #1
lsl x9, x9, x2
ldrh w20, [x15, #-126]
2:
cmp x2, #0x10
b.lt 3f
sub x2, x2, #0x10
checkbuf47
put_bits x13, x14
b 2b
3:
clz w20, w20
ldrh w3, [x15, #2]!
sub w11, w20, #32
lsl w3, w3, w20
neg w11, w11
lsr w3, w3, w20
add x2, x11, x2, lsl #4
lsl x9, x9, #0x1
ldr w12, [x5, x2, lsl #2]
ldrb w10, [x4, x2]
checkbuf31
put_bits x12, x10
put_bits x3, x11
cbnz x9, 1b
b 6f
4:
movi v21.8h, #0x0010
clz v0.8h, v0.8h
clz v1.8h, v1.8h
clz v2.8h, v2.8h
clz v3.8h, v3.8h
clz v4.8h, v4.8h
clz v5.8h, v5.8h
clz v6.8h, v6.8h
clz v7.8h, v7.8h
ushl v24.8h, v24.8h, v0.8h
ushl v25.8h, v25.8h, v1.8h
ushl v26.8h, v26.8h, v2.8h
ushl v27.8h, v27.8h, v3.8h
ushl v28.8h, v28.8h, v4.8h
ushl v29.8h, v29.8h, v5.8h
ushl v30.8h, v30.8h, v6.8h
ushl v31.8h, v31.8h, v7.8h
neg v0.8h, v0.8h
neg v1.8h, v1.8h
neg v2.8h, v2.8h
neg v3.8h, v3.8h
neg v4.8h, v4.8h
neg v5.8h, v5.8h
neg v6.8h, v6.8h
neg v7.8h, v7.8h
ushl v24.8h, v24.8h, v0.8h
ushl v25.8h, v25.8h, v1.8h
ushl v26.8h, v26.8h, v2.8h
ushl v27.8h, v27.8h, v3.8h
ushl v28.8h, v28.8h, v4.8h
ushl v29.8h, v29.8h, v5.8h
ushl v30.8h, v30.8h, v6.8h
ushl v31.8h, v31.8h, v7.8h
add v0.8h, v21.8h, v0.8h
add v1.8h, v21.8h, v1.8h
add v2.8h, v21.8h, v2.8h
add v3.8h, v21.8h, v3.8h
add v4.8h, v21.8h, v4.8h
add v5.8h, v21.8h, v5.8h
add v6.8h, v21.8h, v6.8h
add v7.8h, v21.8h, v7.8h
st1 {v0.8h, v1.8h, v2.8h, v3.8h}, [x11], #64
st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x11], #64
st1 {v24.8h, v25.8h, v26.8h, v27.8h}, [x11], #64
st1 {v28.8h, v29.8h, v30.8h, v31.8h}, [x11], #64
1:
clz x2, x9
add x15, x15, x2, lsl #1
lsl x9, x9, x2
ldrh w11, [x15, #-126]
2:
cmp x2, #0x10
b.lt 3f
sub x2, x2, #0x10
checkbuf47
put_bits x13, x14
b 2b
3:
ldrh w3, [x15, #2]!
add x2, x11, x2, lsl #4
lsl x9, x9, #0x1
ldr w12, [x5, x2, lsl #2]
ldrb w10, [x4, x2]
checkbuf31
put_bits x12, x10
put_bits x3, x11
cbnz x9, 1b
6:
add x13, sp, #0xfe
cmp x15, x13
b.hs 1f
ldr w12, [x5]
ldrb w14, [x4]
checkbuf47
put_bits x12, x14
1:
sub sp, sp, 16
str PUT_BUFFER, [x0, #0x10]
str PUT_BITSw, [x0, #0x18]
ldp x19, x20, [sp], 16
add x0, BUFFER, #0x1
add sp, sp, 256
br x30
.endm
generate_jsimd_huff_encode_one_block 1
generate_jsimd_huff_encode_one_block 0
.unreq BUFFER
.unreq PUT_BUFFER
.unreq PUT_BITS
.unreq PUT_BITSw
.purgem emit_byte
.purgem put_bits
.purgem checkbuf31
.purgem checkbuf47
|
Akimeite/AndroidModule
| 140,841
|
uvccamera/src/main/jni/libjpeg-turbo-1.5.0/simd/jsimd_mips_dspr2.S
|
/*
* MIPS DSPr2 optimizations for libjpeg-turbo
*
* Copyright (C) 2013-2014, MIPS Technologies, Inc., California.
* All Rights Reserved.
* Authors: Teodora Novkovic (teodora.novkovic@imgtec.com)
* Darko Laus (darko.laus@imgtec.com)
* Copyright (C) 2015, D. R. Commander. All Rights Reserved.
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including commercial applications, and to alter it and redistribute it
* freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software
* in a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
* 3. This notice may not be removed or altered from any source distribution.
*/
#include "jsimd_mips_dspr2_asm.h"
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_c_null_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - output_buf
* a3 - output_row
* 16(sp) - num_rows
* 20(sp) - cinfo->num_components
*
* Null conversion for compression
*/
SAVE_REGS_ON_STACK 8, s0, s1
lw t9, 24(sp) // t9 = num_rows
lw s0, 28(sp) // s0 = cinfo->num_components
andi t0, a0, 3 // t0 = cinfo->image_width & 3
beqz t0, 4f // no residual
nop
0:
addiu t9, t9, -1
bltz t9, 7f
li t1, 0
1:
sll t3, t1, 2
lwx t5, t3(a2) // t5 = outptr = output_buf[ci]
lw t2, 0(a1) // t2 = inptr = *input_buf
sll t4, a3, 2
lwx t5, t4(t5) // t5 = outptr = output_buf[ci][output_row]
addu t2, t2, t1
addu s1, t5, a0
addu t6, t5, t0
2:
lbu t3, 0(t2)
addiu t5, t5, 1
sb t3, -1(t5)
bne t6, t5, 2b
addu t2, t2, s0
3:
lbu t3, 0(t2)
addu t4, t2, s0
addu t7, t4, s0
addu t8, t7, s0
addu t2, t8, s0
lbu t4, 0(t4)
lbu t7, 0(t7)
lbu t8, 0(t8)
addiu t5, t5, 4
sb t3, -4(t5)
sb t4, -3(t5)
sb t7, -2(t5)
bne s1, t5, 3b
sb t8, -1(t5)
addiu t1, t1, 1
bne t1, s0, 1b
nop
addiu a1, a1, 4
bgez t9, 0b
addiu a3, a3, 1
b 7f
nop
4:
addiu t9, t9, -1
bltz t9, 7f
li t1, 0
5:
sll t3, t1, 2
lwx t5, t3(a2) // t5 = outptr = output_buf[ci]
lw t2, 0(a1) // t2 = inptr = *input_buf
sll t4, a3, 2
lwx t5, t4(t5) // t5 = outptr = output_buf[ci][output_row]
addu t2, t2, t1
addu s1, t5, a0
addu t6, t5, t0
6:
lbu t3, 0(t2)
addu t4, t2, s0
addu t7, t4, s0
addu t8, t7, s0
addu t2, t8, s0
lbu t4, 0(t4)
lbu t7, 0(t7)
lbu t8, 0(t8)
addiu t5, t5, 4
sb t3, -4(t5)
sb t4, -3(t5)
sb t7, -2(t5)
bne s1, t5, 6b
sb t8, -1(t5)
addiu t1, t1, 1
bne t1, s0, 5b
nop
addiu a1, a1, 4
bgez t9, 4b
addiu a3, a3, 1
7:
RESTORE_REGS_FROM_STACK 8, s0, s1
j ra
nop
END(jsimd_c_null_convert_mips_dspr2)
/*****************************************************************************/
/*
* jsimd_extrgb_ycc_convert_mips_dspr2
* jsimd_extbgr_ycc_convert_mips_dspr2
* jsimd_extrgbx_ycc_convert_mips_dspr2
* jsimd_extbgrx_ycc_convert_mips_dspr2
* jsimd_extxbgr_ycc_convert_mips_dspr2
* jsimd_extxrgb_ycc_convert_mips_dspr2
*
* Colorspace conversion RGB -> YCbCr
*/
.macro GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 colorid, pixel_size, r_offs, g_offs, b_offs
.macro DO_RGB_TO_YCC r, \
g, \
b, \
inptr
lbu \r, \r_offs(\inptr)
lbu \g, \g_offs(\inptr)
lbu \b, \b_offs(\inptr)
addiu \inptr, \pixel_size
.endm
LEAF_MIPS_DSPR2(jsimd_\colorid\()_ycc_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - output_buf
* a3 - output_row
* 16(sp) - num_rows
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw t7, 48(sp) // t7 = num_rows
li s0, 0x4c8b // FIX(0.29900)
li s1, 0x9646 // FIX(0.58700)
li s2, 0x1d2f // FIX(0.11400)
li s3, 0xffffd4cd // -FIX(0.16874)
li s4, 0xffffab33 // -FIX(0.33126)
li s5, 0x8000 // FIX(0.50000)
li s6, 0xffff94d1 // -FIX(0.41869)
li s7, 0xffffeb2f // -FIX(0.08131)
li t8, 0x807fff // CBCR_OFFSET + ONE_HALF-1
0:
addiu t7, -1 // --num_rows
lw t6, 0(a1) // t6 = input_buf[0]
lw t0, 0(a2)
lw t1, 4(a2)
lw t2, 8(a2)
sll t3, a3, 2
lwx t0, t3(t0) // t0 = output_buf[0][output_row]
lwx t1, t3(t1) // t1 = output_buf[1][output_row]
lwx t2, t3(t2) // t2 = output_buf[2][output_row]
addu t9, t2, a0 // t9 = end address
addiu a3, 1
1:
DO_RGB_TO_YCC t3, t4, t5, t6
mtlo s5, $ac0
mtlo t8, $ac1
mtlo t8, $ac2
maddu $ac0, s2, t5
maddu $ac1, s5, t5
maddu $ac2, s5, t3
maddu $ac0, s0, t3
maddu $ac1, s3, t3
maddu $ac2, s6, t4
maddu $ac0, s1, t4
maddu $ac1, s4, t4
maddu $ac2, s7, t5
extr.w t3, $ac0, 16
extr.w t4, $ac1, 16
extr.w t5, $ac2, 16
sb t3, 0(t0)
sb t4, 0(t1)
sb t5, 0(t2)
addiu t0, 1
addiu t2, 1
bne t2, t9, 1b
addiu t1, 1
bgtz t7, 0b
addiu a1, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_\colorid\()_ycc_convert_mips_dspr2)
.purgem DO_RGB_TO_YCC
.endm
/*------------------------------------------id -- pix R G B */
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extrgb, 3, 0, 1, 2
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extbgr, 3, 2, 1, 0
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extrgbx, 4, 0, 1, 2
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extbgrx, 4, 2, 1, 0
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extxbgr, 4, 3, 2, 1
GENERATE_JSIMD_RGB_YCC_CONVERT_MIPS_DSPR2 extxrgb, 4, 1, 2, 3
/*****************************************************************************/
/*
* jsimd_ycc_extrgb_convert_mips_dspr2
* jsimd_ycc_extbgr_convert_mips_dspr2
* jsimd_ycc_extrgbx_convert_mips_dspr2
* jsimd_ycc_extbgrx_convert_mips_dspr2
* jsimd_ycc_extxbgr_convert_mips_dspr2
* jsimd_ycc_extxrgb_convert_mips_dspr2
*
* Colorspace conversion YCbCr -> RGB
*/
.macro GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 colorid, pixel_size, r_offs, g_offs, b_offs, a_offs
.macro STORE_YCC_TO_RGB scratch0 \
scratch1 \
scratch2 \
outptr
sb \scratch0, \r_offs(\outptr)
sb \scratch1, \g_offs(\outptr)
sb \scratch2, \b_offs(\outptr)
.if (\pixel_size == 4)
li t0, 0xFF
sb t0, \a_offs(\outptr)
.endif
addiu \outptr, \pixel_size
.endm
LEAF_MIPS_DSPR2(jsimd_ycc_\colorid\()_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - input_row
* a3 - output_buf
* 16(sp) - num_rows
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw s1, 48(sp)
li t3, 0x8000
li t4, 0x166e9 // FIX(1.40200)
li t5, 0x1c5a2 // FIX(1.77200)
li t6, 0xffff492e // -FIX(0.71414)
li t7, 0xffffa7e6 // -FIX(0.34414)
repl.ph t8, 128
0:
lw s0, 0(a3)
lw t0, 0(a1)
lw t1, 4(a1)
lw t2, 8(a1)
sll s5, a2, 2
addiu s1, -1
lwx s2, s5(t0)
lwx s3, s5(t1)
lwx s4, s5(t2)
addu t9, s2, a0
addiu a2, 1
1:
lbu s7, 0(s4) // cr
lbu s6, 0(s3) // cb
lbu s5, 0(s2) // y
addiu s2, 1
addiu s4, 1
addiu s7, -128
addiu s6, -128
mul t2, t7, s6
mul t0, t6, s7 // Crgtab[cr]
sll s7, 15
mulq_rs.w t1, t4, s7 // Crrtab[cr]
sll s6, 15
addu t2, t3 // Cbgtab[cb]
addu t2, t0
mulq_rs.w t0, t5, s6 // Cbbtab[cb]
sra t2, 16
addu t1, s5
addu t2, s5 // add y
ins t2, t1, 16, 16
subu.ph t2, t2, t8
addu t0, s5
shll_s.ph t2, t2, 8
subu t0, 128
shra.ph t2, t2, 8
shll_s.w t0, t0, 24
addu.ph t2, t2, t8 // clip & store
sra t0, t0, 24
sra t1, t2, 16
addiu t0, 128
STORE_YCC_TO_RGB t1, t2, t0, s0
bne s2, t9, 1b
addiu s3, 1
bgtz s1, 0b
addiu a3, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_ycc_\colorid\()_convert_mips_dspr2)
.purgem STORE_YCC_TO_RGB
.endm
/*------------------------------------------id -- pix R G B A */
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extrgb, 3, 0, 1, 2, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extbgr, 3, 2, 1, 0, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extrgbx, 4, 0, 1, 2, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extbgrx, 4, 2, 1, 0, 3
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extxbgr, 4, 3, 2, 1, 0
GENERATE_JSIMD_YCC_RGB_CONVERT_MIPS_DSPR2 extxrgb, 4, 1, 2, 3, 0
/*****************************************************************************/
/*
* jsimd_extrgb_gray_convert_mips_dspr2
* jsimd_extbgr_gray_convert_mips_dspr2
* jsimd_extrgbx_gray_convert_mips_dspr2
* jsimd_extbgrx_gray_convert_mips_dspr2
* jsimd_extxbgr_gray_convert_mips_dspr2
* jsimd_extxrgb_gray_convert_mips_dspr2
*
* Colorspace conversion RGB -> GRAY
*/
.macro GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 colorid, pixel_size, r_offs, g_offs, b_offs
.macro DO_RGB_TO_GRAY r, \
g, \
b, \
inptr
lbu \r, \r_offs(\inptr)
lbu \g, \g_offs(\inptr)
lbu \b, \b_offs(\inptr)
addiu \inptr, \pixel_size
.endm
LEAF_MIPS_DSPR2(jsimd_\colorid\()_gray_convert_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - input_buf
* a2 - output_buf
* a3 - output_row
* 16(sp) - num_rows
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
li s0, 0x4c8b // s0 = FIX(0.29900)
li s1, 0x9646 // s1 = FIX(0.58700)
li s2, 0x1d2f // s2 = FIX(0.11400)
li s7, 0x8000 // s7 = FIX(0.50000)
lw s6, 48(sp)
andi t7, a0, 3
0:
addiu s6, -1 // s6 = num_rows
lw t0, 0(a1)
lw t1, 0(a2)
sll t3, a3, 2
lwx t1, t3(t1)
addiu a3, 1
addu t9, t1, a0
subu t8, t9, t7
beq t1, t8, 2f
nop
1:
DO_RGB_TO_GRAY t3, t4, t5, t0
DO_RGB_TO_GRAY s3, s4, s5, t0
mtlo s7, $ac0
maddu $ac0, s2, t5
maddu $ac0, s1, t4
maddu $ac0, s0, t3
mtlo s7, $ac1
maddu $ac1, s2, s5
maddu $ac1, s1, s4
maddu $ac1, s0, s3
extr.w t6, $ac0, 16
DO_RGB_TO_GRAY t3, t4, t5, t0
DO_RGB_TO_GRAY s3, s4, s5, t0
mtlo s7, $ac0
maddu $ac0, s2, t5
maddu $ac0, s1, t4
extr.w t2, $ac1, 16
maddu $ac0, s0, t3
mtlo s7, $ac1
maddu $ac1, s2, s5
maddu $ac1, s1, s4
maddu $ac1, s0, s3
extr.w t5, $ac0, 16
sb t6, 0(t1)
sb t2, 1(t1)
extr.w t3, $ac1, 16
addiu t1, 4
sb t5, -2(t1)
sb t3, -1(t1)
bne t1, t8, 1b
nop
2:
beqz t7, 4f
nop
3:
DO_RGB_TO_GRAY t3, t4, t5, t0
mtlo s7, $ac0
maddu $ac0, s2, t5
maddu $ac0, s1, t4
maddu $ac0, s0, t3
extr.w t6, $ac0, 16
sb t6, 0(t1)
addiu t1, 1
bne t1, t9, 3b
nop
4:
bgtz s6, 0b
addiu a1, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_\colorid\()_gray_convert_mips_dspr2)
.purgem DO_RGB_TO_GRAY
.endm
/*------------------------------------------id -- pix R G B */
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extrgb, 3, 0, 1, 2
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extbgr, 3, 2, 1, 0
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extrgbx, 4, 0, 1, 2
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extbgrx, 4, 2, 1, 0
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extxbgr, 4, 3, 2, 1
GENERATE_JSIMD_RGB_GRAY_CONVERT_MIPS_DSPR2 extxrgb, 4, 1, 2, 3
/*****************************************************************************/
/*
* jsimd_h2v2_merged_upsample_mips_dspr2
* jsimd_h2v2_extrgb_merged_upsample_mips_dspr2
* jsimd_h2v2_extrgbx_merged_upsample_mips_dspr2
* jsimd_h2v2_extbgr_merged_upsample_mips_dspr2
* jsimd_h2v2_extbgrx_merged_upsample_mips_dspr2
* jsimd_h2v2_extxbgr_merged_upsample_mips_dspr2
* jsimd_h2v2_extxrgb_merged_upsample_mips_dspr2
*
* Merged h2v2 upsample routines
*/
.macro GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 colorid, \
pixel_size, \
r1_offs, \
g1_offs, \
b1_offs, \
a1_offs, \
r2_offs, \
g2_offs, \
b2_offs, \
a2_offs
.macro STORE_H2V2_2_PIXELS scratch0 \
scratch1 \
scratch2 \
scratch3 \
scratch4 \
scratch5 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
sb \scratch3, \r2_offs(\outptr)
sb \scratch4, \g2_offs(\outptr)
sb \scratch5, \b2_offs(\outptr)
.if (\pixel_size == 8)
li \scratch0, 0xFF
sb \scratch0, \a1_offs(\outptr)
sb \scratch0, \a2_offs(\outptr)
.endif
addiu \outptr, \pixel_size
.endm
.macro STORE_H2V2_1_PIXEL scratch0 \
scratch1 \
scratch2 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
.if (\pixel_size == 8)
li t0, 0xFF
sb t0, \a1_offs(\outptr)
.endif
.endm
LEAF_MIPS_DSPR2(jsimd_h2v2_\colorid\()_merged_upsample_mips_dspr2)
/*
* a0 - cinfo->output_width
* a1 - input_buf
* a2 - in_row_group_ctr
* a3 - output_buf
* 16(sp) - cinfo->sample_range_limit
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
lw t9, 56(sp) // cinfo->sample_range_limit
lw v0, 0(a1)
lw v1, 4(a1)
lw t0, 8(a1)
sll t1, a2, 3
addiu t2, t1, 4
sll t3, a2, 2
lw t4, 0(a3) // t4 = output_buf[0]
lwx t1, t1(v0) // t1 = input_buf[0][in_row_group_ctr*2]
lwx t2, t2(v0) // t2 = input_buf[0][in_row_group_ctr*2 + 1]
lwx t5, t3(v1) // t5 = input_buf[1][in_row_group_ctr]
lwx t6, t3(t0) // t6 = input_buf[2][in_row_group_ctr]
lw t7, 4(a3) // t7 = output_buf[1]
li s1, 0xe6ea
addiu t8, s1, 0x7fff // t8 = 0x166e9 [FIX(1.40200)]
addiu s0, t8, 0x5eb9 // s0 = 0x1c5a2 [FIX(1.77200)]
addiu s1, zero, 0xa7e6 // s4 = 0xffffa7e6 [-FIX(0.34414)]
xori s2, s1, 0xeec8 // s3 = 0xffff492e [-FIX(0.71414)]
srl t3, a0, 1
blez t3, 2f
addu t0, t5, t3 // t0 = end address
1:
lbu t3, 0(t5)
lbu s3, 0(t6)
addiu t5, t5, 1
addiu t3, t3, -128 // (cb - 128)
addiu s3, s3, -128 // (cr - 128)
mult $ac1, s1, t3
madd $ac1, s2, s3
sll s3, s3, 15
sll t3, t3, 15
mulq_rs.w s4, t8, s3 // s4 = (C1 * cr + ONE_HALF)>> SCALEBITS
extr_r.w s5, $ac1, 16
mulq_rs.w s6, s0, t3 // s6 = (C2 * cb + ONE_HALF)>> SCALEBITS
lbu v0, 0(t1)
addiu t6, t6, 1
addiu t1, t1, 2
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu AT, 0(t3)
lbu s7, 0(s3)
lbu ra, 0(v1)
lbu v0, -1(t1)
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
lbu v0, 0(t2)
STORE_H2V2_2_PIXELS AT, s7, ra, t3, s3, v1, t4
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu AT, 0(t3)
lbu s7, 0(s3)
lbu ra, 0(v1)
lbu v0, 1(t2)
addiu t2, t2, 2
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
STORE_H2V2_2_PIXELS AT, s7, ra, t3, s3, v1, t7
bne t0, t5, 1b
nop
2:
andi t0, a0, 1
beqz t0, 4f
lbu t3, 0(t5)
lbu s3, 0(t6)
addiu t3, t3, -128 // (cb - 128)
addiu s3, s3, -128 // (cr - 128)
mult $ac1, s1, t3
madd $ac1, s2, s3
sll s3, s3, 15
sll t3, t3, 15
lbu v0, 0(t1)
extr_r.w s5, $ac1, 16
mulq_rs.w s4, t8, s3 // s4 = (C1 * cr + ONE_HALF)>> SCALEBITS
mulq_rs.w s6, s0, t3 // s6 = (C2 * cb + ONE_HALF)>> SCALEBITS
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
lbu v0, 0(t2)
STORE_H2V2_1_PIXEL t3, s3, v1, t4
addu t3, v0, s4 // y+cred
addu s3, v0, s5 // y+cgreen
addu v1, v0, s6 // y+cblue
addu t3, t9, t3 // y+cred
addu s3, t9, s3 // y+cgreen
addu v1, t9, v1 // y+cblue
lbu t3, 0(t3)
lbu s3, 0(s3)
lbu v1, 0(v1)
STORE_H2V2_1_PIXEL t3, s3, v1, t7
4:
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
j ra
nop
END(jsimd_h2v2_\colorid\()_merged_upsample_mips_dspr2)
.purgem STORE_H2V2_1_PIXEL
.purgem STORE_H2V2_2_PIXELS
.endm
/*-----------------------------------------id -- pix R1 G1 B1 A1 R2 G2 B2 A2 */
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extrgb, 6, 0, 1, 2, 6, 3, 4, 5, 6
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extbgr, 6, 2, 1, 0, 3, 5, 4, 3, 6
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extrgbx, 8, 0, 1, 2, 3, 4, 5, 6, 7
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extbgrx, 8, 2, 1, 0, 3, 6, 5, 4, 7
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extxbgr, 8, 3, 2, 1, 0, 7, 6, 5, 4
GENERATE_H2V2_MERGED_UPSAMPLE_MIPS_DSPR2 extxrgb, 8, 1, 2, 3, 0, 5, 6, 7, 4
/*****************************************************************************/
/*
* jsimd_h2v1_merged_upsample_mips_dspr2
* jsimd_h2v1_extrgb_merged_upsample_mips_dspr2
* jsimd_h2v1_extrgbx_merged_upsample_mips_dspr2
* jsimd_h2v1_extbgr_merged_upsample_mips_dspr2
* jsimd_h2v1_extbgrx_merged_upsample_mips_dspr2
* jsimd_h2v1_extxbgr_merged_upsample_mips_dspr2
* jsimd_h2v1_extxrgb_merged_upsample_mips_dspr2
*
* Merged h2v1 upsample routines
*/
.macro GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 colorid, \
pixel_size, \
r1_offs, \
g1_offs, \
b1_offs, \
a1_offs, \
r2_offs, \
g2_offs, \
b2_offs, \
a2_offs
.macro STORE_H2V1_2_PIXELS scratch0 \
scratch1 \
scratch2 \
scratch3 \
scratch4 \
scratch5 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
sb \scratch3, \r2_offs(\outptr)
sb \scratch4, \g2_offs(\outptr)
sb \scratch5, \b2_offs(\outptr)
.if (\pixel_size == 8)
li t0, 0xFF
sb t0, \a1_offs(\outptr)
sb t0, \a2_offs(\outptr)
.endif
addiu \outptr, \pixel_size
.endm
.macro STORE_H2V1_1_PIXEL scratch0 \
scratch1 \
scratch2 \
outptr
sb \scratch0, \r1_offs(\outptr)
sb \scratch1, \g1_offs(\outptr)
sb \scratch2, \b1_offs(\outptr)
.if (\pixel_size == 8)
li t0, 0xFF
sb t0, \a1_offs(\outptr)
.endif
.endm
LEAF_MIPS_DSPR2(jsimd_h2v1_\colorid\()_merged_upsample_mips_dspr2)
/*
* a0 - cinfo->output_width
* a1 - input_buf
* a2 - in_row_group_ctr
* a3 - output_buf
* 16(sp) - range_limit
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
li t0, 0xe6ea
lw t1, 0(a1) // t1 = input_buf[0]
lw t2, 4(a1) // t2 = input_buf[1]
lw t3, 8(a1) // t3 = input_buf[2]
lw t8, 56(sp) // t8 = range_limit
addiu s1, t0, 0x7fff // s1 = 0x166e9 [FIX(1.40200)]
addiu s2, s1, 0x5eb9 // s2 = 0x1c5a2 [FIX(1.77200)]
addiu s0, t0, 0x9916 // s0 = 0x8000
addiu s4, zero, 0xa7e6 // s4 = 0xffffa7e6 [-FIX(0.34414)]
xori s3, s4, 0xeec8 // s3 = 0xffff492e [-FIX(0.71414)]
srl t0, a0, 1
sll t4, a2, 2
lwx s5, t4(t1) // s5 = inptr0
lwx s6, t4(t2) // s6 = inptr1
lwx s7, t4(t3) // s7 = inptr2
lw t7, 0(a3) // t7 = outptr
blez t0, 2f
addu t9, s6, t0 // t9 = end address
1:
lbu t2, 0(s6) // t2 = cb
lbu t0, 0(s7) // t0 = cr
lbu t1, 0(s5) // t1 = y
addiu t2, t2, -128 // t2 = cb - 128
addiu t0, t0, -128 // t0 = cr - 128
mult $ac1, s4, t2
madd $ac1, s3, t0
sll t0, t0, 15
sll t2, t2, 15
mulq_rs.w t0, s1, t0 // t0 = (C1*cr + ONE_HALF)>> SCALEBITS
extr_r.w t5, $ac1, 16
mulq_rs.w t6, s2, t2 // t6 = (C2*cb + ONE_HALF)>> SCALEBITS
addiu s7, s7, 1
addiu s6, s6, 1
addu t2, t1, t0 // t2 = y + cred
addu t3, t1, t5 // t3 = y + cgreen
addu t4, t1, t6 // t4 = y + cblue
addu t2, t8, t2
addu t3, t8, t3
addu t4, t8, t4
lbu t1, 1(s5)
lbu v0, 0(t2)
lbu v1, 0(t3)
lbu ra, 0(t4)
addu t2, t1, t0
addu t3, t1, t5
addu t4, t1, t6
addu t2, t8, t2
addu t3, t8, t3
addu t4, t8, t4
lbu t2, 0(t2)
lbu t3, 0(t3)
lbu t4, 0(t4)
STORE_H2V1_2_PIXELS v0, v1, ra, t2, t3, t4, t7
bne t9, s6, 1b
addiu s5, s5, 2
2:
andi t0, a0, 1
beqz t0, 4f
nop
3:
lbu t2, 0(s6)
lbu t0, 0(s7)
lbu t1, 0(s5)
addiu t2, t2, -128 //(cb - 128)
addiu t0, t0, -128 //(cr - 128)
mul t3, s4, t2
mul t4, s3, t0
sll t0, t0, 15
sll t2, t2, 15
mulq_rs.w t0, s1, t0 // (C1*cr + ONE_HALF)>> SCALEBITS
mulq_rs.w t6, s2, t2 // (C2*cb + ONE_HALF)>> SCALEBITS
addu t3, t3, s0
addu t3, t4, t3
sra t5, t3, 16 // (C4*cb + ONE_HALF + C3*cr)>> SCALEBITS
addu t2, t1, t0 // y + cred
addu t3, t1, t5 // y + cgreen
addu t4, t1, t6 // y + cblue
addu t2, t8, t2
addu t3, t8, t3
addu t4, t8, t4
lbu t2, 0(t2)
lbu t3, 0(t3)
lbu t4, 0(t4)
STORE_H2V1_1_PIXEL t2, t3, t4, t7
4:
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, ra
j ra
nop
END(jsimd_h2v1_\colorid\()_merged_upsample_mips_dspr2)
.purgem STORE_H2V1_1_PIXEL
.purgem STORE_H2V1_2_PIXELS
.endm
/*-----------------------------------------id -- pix R1 G1 B1 A1 R2 G2 B2 A2 */
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extrgb, 6, 0, 1, 2, 6, 3, 4, 5, 6
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extbgr, 6, 2, 1, 0, 3, 5, 4, 3, 6
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extrgbx, 8, 0, 1, 2, 3, 4, 5, 6, 7
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extbgrx, 8, 2, 1, 0, 3, 6, 5, 4, 7
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extxbgr, 8, 3, 2, 1, 0, 7, 6, 5, 4
GENERATE_H2V1_MERGED_UPSAMPLE_MIPS_DSPR2 extxrgb, 8, 1, 2, 3, 0, 5, 6, 7, 4
/*****************************************************************************/
/*
* jsimd_h2v2_fancy_upsample_mips_dspr2
*
* Fancy processing for the common case of 2:1 horizontal and 2:1 vertical.
*/
LEAF_MIPS_DSPR2(jsimd_h2v2_fancy_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - downsampled_width
* a2 - input_data
* a3 - output_data_ptr
*/
SAVE_REGS_ON_STACK 24, s0, s1, s2, s3, s4, s5
li s4, 0
lw s2, 0(a3) // s2 = *output_data_ptr
0:
li t9, 2
lw s1, -4(a2) // s1 = inptr1
1:
lw s0, 0(a2) // s0 = inptr0
lwx s3, s4(s2)
addiu s5, a1, -2 // s5 = downsampled_width - 2
srl t4, s5, 1
sll t4, t4, 1
lbu t0, 0(s0)
lbu t1, 1(s0)
lbu t2, 0(s1)
lbu t3, 1(s1)
addiu s0, 2
addiu s1, 2
addu t8, s0, t4 // t8 = end address
andi s5, s5, 1 // s5 = residual
sll t4, t0, 1
sll t6, t1, 1
addu t0, t0, t4 // t0 = (*inptr0++) * 3
addu t1, t1, t6 // t1 = (*inptr0++) * 3
addu t7, t0, t2 // t7 = thiscolsum
addu t6, t1, t3 // t5 = nextcolsum
sll t0, t7, 2 // t0 = thiscolsum * 4
subu t1, t0, t7 // t1 = thiscolsum * 3
shra_r.w t0, t0, 4
addiu t1, 7
addu t1, t1, t6
srl t1, t1, 4
sb t0, 0(s3)
sb t1, 1(s3)
beq t8, s0, 22f // skip to final iteration if width == 3
addiu s3, 2
2:
lh t0, 0(s0) // t0 = A3|A2
lh t2, 0(s1) // t2 = B3|B2
addiu s0, 2
addiu s1, 2
preceu.ph.qbr t0, t0 // t0 = 0|A3|0|A2
preceu.ph.qbr t2, t2 // t2 = 0|B3|0|B2
shll.ph t1, t0, 1
sll t3, t6, 1
addu.ph t0, t1, t0 // t0 = A3*3|A2*3
addu t3, t3, t6 // t3 = this * 3
addu.ph t0, t0, t2 // t0 = next2|next1
addu t1, t3, t7
andi t7, t0, 0xFFFF // t7 = next1
sll t2, t7, 1
addu t2, t7, t2 // t2 = next1*3
addu t4, t2, t6
srl t6, t0, 16 // t6 = next2
shra_r.w t1, t1, 4 // t1 = (this*3 + last + 8) >> 4
addu t0, t3, t7
addiu t0, 7
srl t0, t0, 4 // t0 = (this*3 + next1 + 7) >> 4
shra_r.w t4, t4, 4 // t3 = (next1*3 + this + 8) >> 4
addu t2, t2, t6
addiu t2, 7
srl t2, t2, 4 // t2 = (next1*3 + next2 + 7) >> 4
sb t1, 0(s3)
sb t0, 1(s3)
sb t4, 2(s3)
sb t2, 3(s3)
bne t8, s0, 2b
addiu s3, 4
22:
beqz s5, 4f
addu t8, s0, s5
3:
lbu t0, 0(s0)
lbu t2, 0(s1)
addiu s0, 1
addiu s1, 1
sll t3, t6, 1
sll t1, t0, 1
addu t1, t0, t1 // t1 = inptr0 * 3
addu t3, t3, t6 // t3 = thiscolsum * 3
addu t5, t1, t2
addu t1, t3, t7
shra_r.w t1, t1, 4
addu t0, t3, t5
addiu t0, 7
srl t0, t0, 4
sb t1, 0(s3)
sb t0, 1(s3)
addiu s3, 2
move t7, t6
bne t8, s0, 3b
move t6, t5
4:
sll t0, t6, 2 // t0 = thiscolsum * 4
subu t1, t0, t6 // t1 = thiscolsum * 3
addu t1, t1, t7
addiu s4, 4
shra_r.w t1, t1, 4
addiu t0, 7
srl t0, t0, 4
sb t1, 0(s3)
sb t0, 1(s3)
addiu t9, -1
addiu s3, 2
bnez t9, 1b
lw s1, 4(a2)
srl t0, s4, 2
subu t0, a0, t0
bgtz t0, 0b
addiu a2, 4
RESTORE_REGS_FROM_STACK 24, s0, s1, s2, s3, s4, s5
j ra
nop
END(jsimd_h2v2_fancy_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v1_fancy_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - downsampled_width
* a2 - input_data
* a3 - output_data_ptr
*/
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
.set at
beqz a0, 3f
sll t0, a0, 2
lw s1, 0(a3)
li s3, 0x10001
addu s0, s1, t0
0:
addiu t8, a1, -2
srl t9, t8, 2
lw t7, 0(a2)
lw s2, 0(s1)
lbu t0, 0(t7)
lbu t1, 1(t7) // t1 = inptr[1]
sll t2, t0, 1
addu t2, t2, t0 // t2 = invalue*3
addu t2, t2, t1
shra_r.w t2, t2, 2
sb t0, 0(s2)
sb t2, 1(s2)
beqz t9, 11f
addiu s2, 2
1:
ulw t0, 0(t7) // t0 = |P3|P2|P1|P0|
ulw t1, 1(t7)
ulh t2, 4(t7) // t2 = |0|0|P5|P4|
preceu.ph.qbl t3, t0 // t3 = |0|P3|0|P2|
preceu.ph.qbr t0, t0 // t0 = |0|P1|0|P0|
preceu.ph.qbr t2, t2 // t2 = |0|P5|0|P4|
preceu.ph.qbl t4, t1 // t4 = |0|P4|0|P3|
preceu.ph.qbr t1, t1 // t1 = |0|P2|0|P1|
shll.ph t5, t4, 1
shll.ph t6, t1, 1
addu.ph t5, t5, t4 // t5 = |P4*3|P3*3|
addu.ph t6, t6, t1 // t6 = |P2*3|P1*3|
addu.ph t4, t3, s3
addu.ph t0, t0, s3
addu.ph t4, t4, t5
addu.ph t0, t0, t6
shrl.ph t4, t4, 2 // t4 = |0|P3|0|P2|
shrl.ph t0, t0, 2 // t0 = |0|P1|0|P0|
addu.ph t2, t2, t5
addu.ph t3, t3, t6
shra_r.ph t2, t2, 2 // t2 = |0|P5|0|P4|
shra_r.ph t3, t3, 2 // t3 = |0|P3|0|P2|
shll.ph t2, t2, 8
shll.ph t3, t3, 8
or t2, t4, t2
or t3, t3, t0
addiu t9, -1
usw t3, 0(s2)
usw t2, 4(s2)
addiu s2, 8
bgtz t9, 1b
addiu t7, 4
11:
andi t8, 3
beqz t8, 22f
addiu t7, 1
2:
lbu t0, 0(t7)
addiu t7, 1
sll t1, t0, 1
addu t2, t0, t1 // t2 = invalue
lbu t3, -2(t7)
lbu t4, 0(t7)
addiu t3, 1
addiu t4, 2
addu t3, t3, t2
addu t4, t4, t2
srl t3, 2
srl t4, 2
sb t3, 0(s2)
sb t4, 1(s2)
addiu t8, -1
bgtz t8, 2b
addiu s2, 2
22:
lbu t0, 0(t7)
lbu t2, -1(t7)
sll t1, t0, 1
addu t1, t1, t0 // t1 = invalue * 3
addu t1, t1, t2
addiu t1, 1
srl t1, t1, 2
sb t1, 0(s2)
sb t0, 1(s2)
addiu s1, 4
bne s1, s0, 0b
addiu a2, 4
3:
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
j ra
nop
END(jsimd_h2v1_fancy_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v1_downsample_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - cinfo->max_v_samp_factor
* a2 - compptr->v_samp_factor
* a3 - compptr->width_in_blocks
* 16(sp) - input_data
* 20(sp) - output_data
*/
.set at
SAVE_REGS_ON_STACK 24, s0, s1, s2, s3, s4
beqz a2, 7f
lw s1, 44(sp) // s1 = output_data
lw s0, 40(sp) // s0 = input_data
srl s2, a0, 2
andi t9, a0, 2
srl t7, t9, 1
addu s2, t7, s2
sll t0, a3, 3 // t0 = width_in_blocks*DCT
srl t7, t0, 1
subu s2, t7, s2
0:
andi t6, a0, 1 // t6 = temp_index
addiu t6, -1
lw t4, 0(s1) // t4 = outptr
lw t5, 0(s0) // t5 = inptr0
li s3, 0 // s3 = bias
srl t7, a0, 1 // t7 = image_width1
srl s4, t7, 2
andi t8, t7, 3
1:
ulhu t0, 0(t5)
ulhu t1, 2(t5)
ulhu t2, 4(t5)
ulhu t3, 6(t5)
raddu.w.qb t0, t0
raddu.w.qb t1, t1
raddu.w.qb t2, t2
raddu.w.qb t3, t3
shra.ph t0, t0, 1
shra_r.ph t1, t1, 1
shra.ph t2, t2, 1
shra_r.ph t3, t3, 1
sb t0, 0(t4)
sb t1, 1(t4)
sb t2, 2(t4)
sb t3, 3(t4)
addiu s4, -1
addiu t4, 4
bgtz s4, 1b
addiu t5, 8
beqz t8, 3f
addu s4, t4, t8
2:
ulhu t0, 0(t5)
raddu.w.qb t0, t0
addqh.w t0, t0, s3
xori s3, s3, 1
sb t0, 0(t4)
addiu t4, 1
bne t4, s4, 2b
addiu t5, 2
3:
lbux t1, t6(t5)
sll t1, 1
addqh.w t2, t1, s3 // t2 = pixval1
xori s3, s3, 1
addqh.w t3, t1, s3 // t3 = pixval2
blez s2, 5f
append t3, t2, 8
addu t5, t4, s2 // t5 = loop_end2
4:
ush t3, 0(t4)
addiu s2, -1
bgtz s2, 4b
addiu t4, 2
5:
beqz t9, 6f
nop
sb t2, 0(t4)
6:
addiu s1, 4
addiu a2, -1
bnez a2, 0b
addiu s0, 4
7:
RESTORE_REGS_FROM_STACK 24, s0, s1, s2, s3, s4
j ra
nop
END(jsimd_h2v1_downsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v2_downsample_mips_dspr2)
/*
* a0 - cinfo->image_width
* a1 - cinfo->max_v_samp_factor
* a2 - compptr->v_samp_factor
* a3 - compptr->width_in_blocks
* 16(sp) - input_data
* 20(sp) - output_data
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
beqz a2, 8f
lw s1, 52(sp) // s1 = output_data
lw s0, 48(sp) // s0 = input_data
andi t6, a0, 1 // t6 = temp_index
addiu t6, -1
srl t7, a0, 1 // t7 = image_width1
srl s4, t7, 2
andi t8, t7, 3
andi t9, a0, 2
srl s2, a0, 2
srl t7, t9, 1
addu s2, t7, s2
sll t0, a3, 3 // s2 = width_in_blocks*DCT
srl t7, t0, 1
subu s2, t7, s2
0:
lw t4, 0(s1) // t4 = outptr
lw t5, 0(s0) // t5 = inptr0
lw s7, 4(s0) // s7 = inptr1
li s6, 1 // s6 = bias
2:
ulw t0, 0(t5) // t0 = |P3|P2|P1|P0|
ulw t1, 0(s7) // t1 = |Q3|Q2|Q1|Q0|
ulw t2, 4(t5)
ulw t3, 4(s7)
precrq.ph.w t7, t0, t1 // t2 = |P3|P2|Q3|Q2|
ins t0, t1, 16, 16 // t0 = |Q1|Q0|P1|P0|
raddu.w.qb t1, t7
raddu.w.qb t0, t0
shra_r.w t1, t1, 2
addiu t0, 1
srl t0, 2
precrq.ph.w t7, t2, t3
ins t2, t3, 16, 16
raddu.w.qb t7, t7
raddu.w.qb t2, t2
shra_r.w t7, t7, 2
addiu t2, 1
srl t2, 2
sb t0, 0(t4)
sb t1, 1(t4)
sb t2, 2(t4)
sb t7, 3(t4)
addiu t4, 4
addiu t5, 8
addiu s4, s4, -1
bgtz s4, 2b
addiu s7, 8
beqz t8, 4f
addu t8, t4, t8
3:
ulhu t0, 0(t5)
ulhu t1, 0(s7)
ins t0, t1, 16, 16
raddu.w.qb t0, t0
addu t0, t0, s6
srl t0, 2
xori s6, s6, 3
sb t0, 0(t4)
addiu t5, 2
addiu t4, 1
bne t8, t4, 3b
addiu s7, 2
4:
lbux t1, t6(t5)
sll t1, 1
lbux t0, t6(s7)
sll t0, 1
addu t1, t1, t0
addu t3, t1, s6
srl t0, t3, 2 // t2 = pixval1
xori s6, s6, 3
addu t2, t1, s6
srl t1, t2, 2 // t3 = pixval2
blez s2, 6f
append t1, t0, 8
5:
ush t1, 0(t4)
addiu s2, -1
bgtz s2, 5b
addiu t4, 2
6:
beqz t9, 7f
nop
sb t0, 0(t4)
7:
addiu s1, 4
addiu a2, -1
bnez a2, 0b
addiu s0, 8
8:
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_h2v2_downsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v2_smooth_downsample_mips_dspr2)
/*
* a0 - input_data
* a1 - output_data
* a2 - compptr->v_samp_factor
* a3 - cinfo->max_v_samp_factor
* 16(sp) - cinfo->smoothing_factor
* 20(sp) - compptr->width_in_blocks
* 24(sp) - cinfo->image_width
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw s7, 52(sp) // compptr->width_in_blocks
lw s0, 56(sp) // cinfo->image_width
lw s6, 48(sp) // cinfo->smoothing_factor
sll s7, 3 // output_cols = width_in_blocks * DCTSIZE
sll v0, s7, 1
subu v0, v0, s0
blez v0, 2f
move v1, zero
addiu t0, a3, 2 // t0 = cinfo->max_v_samp_factor + 2
0:
addiu t1, a0, -4
sll t2, v1, 2
lwx t1, t2(t1)
move t3, v0
addu t1, t1, s0
lbu t2, -1(t1)
1:
addiu t3, t3, -1
sb t2, 0(t1)
bgtz t3, 1b
addiu t1, t1, 1
addiu v1, v1, 1
bne v1, t0, 0b
nop
2:
li v0, 80
mul v0, s6, v0
li v1, 16384
move t4, zero
move t5, zero
subu t6, v1, v0 // t6 = 16384 - tmp_smoot_f * 80
sll t7, s6, 4 // t7 = tmp_smoot_f * 16
3:
/* Special case for first column: pretend column -1 is same as column 0 */
sll v0, t4, 2
lwx t8, v0(a1) // outptr = output_data[outrow]
sll v1, t5, 2
addiu t9, v1, 4
addiu s0, v1, -4
addiu s1, v1, 8
lwx s2, v1(a0) // inptr0 = input_data[inrow]
lwx t9, t9(a0) // inptr1 = input_data[inrow+1]
lwx s0, s0(a0) // above_ptr = input_data[inrow-1]
lwx s1, s1(a0) // below_ptr = input_data[inrow+2]
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, 0(s2)
lbu v1, 2(s2)
lbu t0, 0(t9)
lbu t1, 2(t9)
addu v0, v0, v1
mult $ac1,t2, t6
addu t0, t0, t1
lbu t2, 2(s0)
addu t0, t0, v0
lbu t3, 2(s1)
addu s3, t0, s3
lbu v0, 0(s0)
lbu t0, 0(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
addu t0, t0, v0
addu s3, t0, s3
madd $ac1,s3, t7
extr_r.w v0, $ac1, 16
addiu t8, t8, 1
addiu s2, s2, 2
addiu t9, t9, 2
addiu s0, s0, 2
addiu s1, s1, 2
sb v0, -1(t8)
addiu s4, s7, -2
and s4, s4, 3
addu s5, s4, t8 //end adress
4:
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, -1(s2)
lbu v1, 2(s2)
lbu t0, -1(t9)
lbu t1, 2(t9)
addu v0, v0, v1
mult $ac1, t2, t6
addu t0, t0, t1
lbu t2, 2(s0)
addu t0, t0, v0
lbu t3, 2(s1)
addu s3, t0, s3
lbu v0, -1(s0)
lbu t0, -1(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
addu t0, t0, v0
addu s3, t0, s3
madd $ac1, s3, t7
extr_r.w t2, $ac1, 16
addiu t8, t8, 1
addiu s2, s2, 2
addiu t9, t9, 2
addiu s0, s0, 2
sb t2, -1(t8)
bne s5, t8, 4b
addiu s1, s1, 2
addiu s5, s7, -2
subu s5, s5, s4
addu s5, s5, t8 //end adress
5:
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, -1(s2)
lbu v1, 2(s2)
lbu t0, -1(t9)
lbu t1, 2(t9)
addu v0, v0, v1
mult $ac1, t2, t6
addu t0, t0, t1
lbu t2, 2(s0)
addu t0, t0, v0
lbu t3, 2(s1)
addu s3, t0, s3
lbu v0, -1(s0)
lbu t0, -1(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
lh v1, 2(t9)
addu t0, t0, v0
lh v0, 2(s2)
addu s3, t0, s3
lh t0, 2(s0)
lh t1, 2(s1)
madd $ac1, s3, t7
extr_r.w t2, $ac1, 16
ins t0, t1, 16, 16
ins v0, v1, 16, 16
raddu.w.qb s3, t0
lbu v1, 4(s2)
lbu t0, 1(t9)
lbu t1, 4(t9)
sb t2, 0(t8)
raddu.w.qb t3, v0
lbu v0, 1(s2)
addu t0, t0, t1
mult $ac1, t3, t6
addu v0, v0, v1
lbu t2, 4(s0)
addu t0, t0, v0
lbu v0, 1(s0)
addu s3, t0, s3
lbu t0, 1(s1)
lbu t3, 4(s1)
addu v0, v0, t2
sll s3, s3, 1
addu t0, t0, t3
lh v1, 4(t9)
addu t0, t0, v0
lh v0, 4(s2)
addu s3, t0, s3
lh t0, 4(s0)
lh t1, 4(s1)
madd $ac1, s3, t7
extr_r.w t2, $ac1, 16
ins t0, t1, 16, 16
ins v0, v1, 16, 16
raddu.w.qb s3, t0
lbu v1, 6(s2)
lbu t0, 3(t9)
lbu t1, 6(t9)
sb t2, 1(t8)
raddu.w.qb t3, v0
lbu v0, 3(s2)
addu t0, t0,t1
mult $ac1, t3, t6
addu v0, v0, v1
lbu t2, 6(s0)
addu t0, t0, v0
lbu v0, 3(s0)
addu s3, t0, s3
lbu t0, 3(s1)
lbu t3, 6(s1)
addu v0, v0, t2
sll s3, s3, 1
addu t0, t0, t3
lh v1, 6(t9)
addu t0, t0, v0
lh v0, 6(s2)
addu s3, t0, s3
lh t0, 6(s0)
lh t1, 6(s1)
madd $ac1, s3, t7
extr_r.w t3, $ac1, 16
ins t0, t1, 16, 16
ins v0, v1, 16, 16
raddu.w.qb s3, t0
lbu v1, 8(s2)
lbu t0, 5(t9)
lbu t1, 8(t9)
sb t3, 2(t8)
raddu.w.qb t2, v0
lbu v0, 5(s2)
addu t0, t0, t1
mult $ac1, t2, t6
addu v0, v0, v1
lbu t2, 8(s0)
addu t0, t0, v0
lbu v0, 5(s0)
addu s3, t0, s3
lbu t0, 5(s1)
lbu t3, 8(s1)
addu v0, v0, t2
sll s3, s3, 1
addu t0, t0, t3
addiu t8, t8, 4
addu t0, t0, v0
addiu s2, s2, 8
addu s3, t0, s3
addiu t9, t9, 8
madd $ac1, s3, t7
extr_r.w t1, $ac1, 16
addiu s0, s0, 8
addiu s1, s1, 8
bne s5, t8, 5b
sb t1, -1(t8)
/* Special case for last column */
lh v0, 0(s2)
lh v1, 0(t9)
lh t0, 0(s0)
lh t1, 0(s1)
ins v0, v1, 16, 16
ins t0, t1, 16, 16
raddu.w.qb t2, v0
raddu.w.qb s3, t0
lbu v0, -1(s2)
lbu v1, 1(s2)
lbu t0, -1(t9)
lbu t1, 1(t9)
addu v0, v0, v1
mult $ac1, t2, t6
addu t0, t0, t1
lbu t2, 1(s0)
addu t0, t0, v0
lbu t3, 1(s1)
addu s3, t0, s3
lbu v0, -1(s0)
lbu t0, -1(s1)
sll s3, s3, 1
addu v0, v0, t2
addu t0, t0, t3
addu t0, t0, v0
addu s3, t0, s3
madd $ac1, s3, t7
extr_r.w t0, $ac1, 16
addiu t5, t5, 2
sb t0, 0(t8)
addiu t4, t4, 1
bne t4, a2, 3b
addiu t5, t5, 2
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_h2v2_smooth_downsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_int_upsample_mips_dspr2)
/*
* a0 - upsample->h_expand[compptr->component_index]
* a1 - upsample->v_expand[compptr->component_index]
* a2 - input_data
* a3 - output_data_ptr
* 16(sp) - cinfo->output_width
* 20(sp) - cinfo->max_v_samp_factor
*/
.set at
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
lw s0, 0(a3) // s0 = output_data
lw s1, 32(sp) // s1 = cinfo->output_width
lw s2, 36(sp) // s2 = cinfo->max_v_samp_factor
li t6, 0 // t6 = inrow
beqz s2, 10f
li s3, 0 // s3 = outrow
0:
addu t0, a2, t6
addu t7, s0, s3
lw t3, 0(t0) // t3 = inptr
lw t8, 0(t7) // t8 = outptr
beqz s1, 4f
addu t5, t8, s1 // t5 = outend
1:
lb t2, 0(t3) // t2 = invalue = *inptr++
addiu t3, 1
beqz a0, 3f
move t0, a0 // t0 = h_expand
2:
sb t2, 0(t8)
addiu t0, -1
bgtz t0, 2b
addiu t8, 1
3:
bgt t5, t8, 1b
nop
4:
addiu t9, a1, -1 // t9 = v_expand - 1
blez t9, 9f
nop
5:
lw t3, 0(s0)
lw t4, 4(s0)
subu t0, s1, 0xF
blez t0, 7f
addu t5, t3, s1 // t5 = end address
andi t7, s1, 0xF // t7 = residual
subu t8, t5, t7
6:
ulw t0, 0(t3)
ulw t1, 4(t3)
ulw t2, 8(t3)
usw t0, 0(t4)
ulw t0, 12(t3)
usw t1, 4(t4)
usw t2, 8(t4)
usw t0, 12(t4)
addiu t3, 16
bne t3, t8, 6b
addiu t4, 16
beqz t7, 8f
nop
7:
lbu t0, 0(t3)
sb t0, 0(t4)
addiu t3, 1
bne t3, t5, 7b
addiu t4, 1
8:
addiu t9, -1
bgtz t9, 5b
addiu s0, 8
9:
addu s3, s3, a1
bne s3, s2, 0b
addiu t6, 1
10:
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
j ra
nop
END(jsimd_int_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v1_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - cinfo->output_width
* a2 - input_data
* a3 - output_data_ptr
*/
lw t7, 0(a3) // t7 = output_data
andi t8, a1, 0xf // t8 = residual
sll t0, a0, 2
blez a0, 4f
addu t9, t7, t0 // t9 = output_data end address
0:
lw t5, 0(t7) // t5 = outptr
lw t6, 0(a2) // t6 = inptr
addu t3, t5, a1 // t3 = outptr + output_width (end address)
subu t3, t8 // t3 = end address - residual
beq t5, t3, 2f
move t4, t8
1:
ulw t0, 0(t6) // t0 = |P3|P2|P1|P0|
ulw t2, 4(t6) // t2 = |P7|P6|P5|P4|
srl t1, t0, 16 // t1 = |X|X|P3|P2|
ins t0, t0, 16, 16 // t0 = |P1|P0|P1|P0|
ins t1, t1, 16, 16 // t1 = |P3|P2|P3|P2|
ins t0, t0, 8, 16 // t0 = |P1|P1|P0|P0|
ins t1, t1, 8, 16 // t1 = |P3|P3|P2|P2|
usw t0, 0(t5)
usw t1, 4(t5)
srl t0, t2, 16 // t0 = |X|X|P7|P6|
ins t2, t2, 16, 16 // t2 = |P5|P4|P5|P4|
ins t0, t0, 16, 16 // t0 = |P7|P6|P7|P6|
ins t2, t2, 8, 16 // t2 = |P5|P5|P4|P4|
ins t0, t0, 8, 16 // t0 = |P7|P7|P6|P6|
usw t2, 8(t5)
usw t0, 12(t5)
addiu t5, 16
bne t5, t3, 1b
addiu t6, 8
beqz t8, 3f
move t4, t8
2:
lbu t1, 0(t6)
sb t1, 0(t5)
sb t1, 1(t5)
addiu t4, -2
addiu t6, 1
bgtz t4, 2b
addiu t5, 2
3:
addiu t7, 4
bne t9, t7, 0b
addiu a2, 4
4:
j ra
nop
END(jsimd_h2v1_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_h2v2_upsample_mips_dspr2)
/*
* a0 - cinfo->max_v_samp_factor
* a1 - cinfo->output_width
* a2 - input_data
* a3 - output_data_ptr
*/
lw t7, 0(a3)
blez a0, 7f
andi t9, a1, 0xf // t9 = residual
0:
lw t6, 0(a2) // t6 = inptr
lw t5, 0(t7) // t5 = outptr
addu t8, t5, a1 // t8 = outptr end address
subu t8, t9 // t8 = end address - residual
beq t5, t8, 2f
move t4, t9
1:
ulw t0, 0(t6)
srl t1, t0, 16
ins t0, t0, 16, 16
ins t0, t0, 8, 16
ins t1, t1, 16, 16
ins t1, t1, 8, 16
ulw t2, 4(t6)
usw t0, 0(t5)
usw t1, 4(t5)
srl t3, t2, 16
ins t2, t2, 16, 16
ins t2, t2, 8, 16
ins t3, t3, 16, 16
ins t3, t3, 8, 16
usw t2, 8(t5)
usw t3, 12(t5)
addiu t5, 16
bne t5, t8, 1b
addiu t6, 8
beqz t9, 3f
move t4, t9
2:
lbu t0, 0(t6)
sb t0, 0(t5)
sb t0, 1(t5)
addiu t4, -2
addiu t6, 1
bgtz t4, 2b
addiu t5, 2
3:
lw t6, 0(t7) // t6 = outptr[0]
lw t5, 4(t7) // t5 = outptr[1]
addu t4, t6, a1 // t4 = new end address
beq a1, t9, 5f
subu t8, t4, t9
4:
ulw t0, 0(t6)
ulw t1, 4(t6)
ulw t2, 8(t6)
usw t0, 0(t5)
ulw t0, 12(t6)
usw t1, 4(t5)
usw t2, 8(t5)
usw t0, 12(t5)
addiu t6, 16
bne t6, t8, 4b
addiu t5, 16
beqz t9, 6f
nop
5:
lbu t0, 0(t6)
sb t0, 0(t5)
addiu t6, 1
bne t6, t4, 5b
addiu t5, 1
6:
addiu t7, 8
addiu a0, -2
bgtz a0, 0b
addiu a2, 4
7:
j ra
nop
END(jsimd_h2v2_upsample_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_islow_mips_dspr2)
/*
* a0 - coef_block
* a1 - compptr->dcttable
* a2 - output
* a3 - range_limit
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
addiu sp, sp, -256
move v0, sp
addiu v1, zero, 8 // v1 = DCTSIZE = 8
1:
lh s4, 32(a0) // s4 = inptr[16]
lh s5, 64(a0) // s5 = inptr[32]
lh s6, 96(a0) // s6 = inptr[48]
lh t1, 112(a0) // t1 = inptr[56]
lh t7, 16(a0) // t7 = inptr[8]
lh t5, 80(a0) // t5 = inptr[40]
lh t3, 48(a0) // t3 = inptr[24]
or s4, s4, t1
or s4, s4, t3
or s4, s4, t5
or s4, s4, t7
or s4, s4, s5
or s4, s4, s6
bnez s4, 2f
addiu v1, v1, -1
lh s5, 0(a1) // quantptr[DCTSIZE*0]
lh s6, 0(a0) // inptr[DCTSIZE*0]
mul s5, s5, s6 // DEQUANTIZE(inptr[0], quantptr[0])
sll s5, s5, 2
sw s5, 0(v0)
sw s5, 32(v0)
sw s5, 64(v0)
sw s5, 96(v0)
sw s5, 128(v0)
sw s5, 160(v0)
sw s5, 192(v0)
b 3f
sw s5, 224(v0)
2:
lh t0, 112(a1)
lh t2, 48(a1)
lh t4, 80(a1)
lh t6, 16(a1)
mul t0, t0, t1 // DEQUANTIZE(inptr[DCTSIZE*7],quant[DCTSIZE*7])
mul t1, t2, t3 // DEQUANTIZE(inptr[DCTSIZE*3],quant[DCTSIZE*3])
mul t2, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*5],quant[DCTSIZE*5])
mul t3, t6, t7 // DEQUANTIZE(inptr[DCTSIZE*1],quant[DCTSIZE*1])
lh t4, 32(a1)
lh t5, 32(a0)
lh t6, 96(a1)
lh t7, 96(a0)
addu s0, t0, t1 // z3 = tmp0 + tmp2
addu s1, t1, t2 // z2 = tmp1 + tmp2
addu s2, t2, t3 // z4 = tmp1 + tmp3
addu s3, s0, s2 // z3 + z4
addiu t9, zero, 9633 // FIX_1_175875602
mul s3, s3, t9 // z5 = MULTIPLY(z3 + z4, FIX_1_175875602)
addu t8, t0, t3 // z1 = tmp0 + tmp3
addiu t9, zero, 2446 // FIX_0_298631336
mul t0, t0, t9 // tmp0 = MULTIPLY(tmp0, FIX_0_298631336)
addiu t9, zero, 16819 // FIX_2_053119869
mul t2, t2, t9 // tmp1 = MULTIPLY(tmp1, FIX_2_053119869)
addiu t9, zero, 25172 // FIX_3_072711026
mul t1, t1, t9 // tmp2 = MULTIPLY(tmp2, FIX_3_072711026)
addiu t9, zero, 12299 // FIX_1_501321110
mul t3, t3, t9 // tmp3 = MULTIPLY(tmp3, FIX_1_501321110)
addiu t9, zero, 16069 // FIX_1_961570560
mul s0, s0, t9 // -z3 = MULTIPLY(z3, FIX_1_961570560)
addiu t9, zero, 3196 // FIX_0_390180644
mul s2, s2, t9 // -z4 = MULTIPLY(z4, FIX_0_390180644)
addiu t9, zero, 7373 // FIX_0_899976223
mul t8, t8, t9 // -z1 = MULTIPLY(z1, FIX_0_899976223)
addiu t9, zero, 20995 // FIX_2_562915447
mul s1, s1, t9 // -z2 = MULTIPLY(z2, FIX_2_562915447)
subu s0, s3, s0 // z3 += z5
addu t0, t0, s0 // tmp0 += z3
addu t1, t1, s0 // tmp2 += z3
subu s2, s3, s2 // z4 += z5
addu t2, t2, s2 // tmp1 += z4
addu t3, t3, s2 // tmp3 += z4
subu t0, t0, t8 // tmp0 += z1
subu t1, t1, s1 // tmp2 += z2
subu t2, t2, s1 // tmp1 += z2
subu t3, t3, t8 // tmp3 += z1
mul s0, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*2],quant[DCTSIZE*2])
addiu t9, zero, 6270 // FIX_0_765366865
mul s1, t6, t7 // DEQUANTIZE(inptr[DCTSIZE*6],quant[DCTSIZE*6])
lh t4, 0(a1)
lh t5, 0(a0)
lh t6, 64(a1)
lh t7, 64(a0)
mul s2, t9, s0 // MULTIPLY(z2, FIX_0_765366865)
mul t5, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*0],quant[DCTSIZE*0])
mul t6, t6, t7 // DEQUANTIZE(inptr[DCTSIZE*4],quant[DCTSIZE*4])
addiu t9, zero, 4433 // FIX_0_541196100
addu s3, s0, s1 // z2 + z3
mul s3, s3, t9 // z1 = MULTIPLY(z2 + z3, FIX_0_541196100)
addiu t9, zero, 15137 // FIX_1_847759065
mul t8, s1, t9 // MULTIPLY(z3, FIX_1_847759065)
addu t4, t5, t6
subu t5, t5, t6
sll t4, t4, 13 // tmp0 = (z2 + z3) << CONST_BITS
sll t5, t5, 13 // tmp1 = (z2 - z3) << CONST_BITS
addu t7, s3, s2 // tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865)
subu t6, s3, t8 // tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065)
addu s0, t4, t7
subu s1, t4, t7
addu s2, t5, t6
subu s3, t5, t6
addu t4, s0, t3
subu s0, s0, t3
addu t3, s2, t1
subu s2, s2, t1
addu t1, s3, t2
subu s3, s3, t2
addu t2, s1, t0
subu s1, s1, t0
shra_r.w t4, t4, 11
shra_r.w t3, t3, 11
shra_r.w t1, t1, 11
shra_r.w t2, t2, 11
shra_r.w s1, s1, 11
shra_r.w s3, s3, 11
shra_r.w s2, s2, 11
shra_r.w s0, s0, 11
sw t4, 0(v0)
sw t3, 32(v0)
sw t1, 64(v0)
sw t2, 96(v0)
sw s1, 128(v0)
sw s3, 160(v0)
sw s2, 192(v0)
sw s0, 224(v0)
3:
addiu a1, a1, 2
addiu a0, a0, 2
bgtz v1, 1b
addiu v0, v0, 4
move v0, sp
addiu v1, zero, 8
4:
lw t0, 8(v0) // z2 = (JLONG) wsptr[2]
lw t1, 24(v0) // z3 = (JLONG) wsptr[6]
lw t2, 0(v0) // (JLONG) wsptr[0]
lw t3, 16(v0) // (JLONG) wsptr[4]
lw s4, 4(v0) // (JLONG) wsptr[1]
lw s5, 12(v0) // (JLONG) wsptr[3]
lw s6, 20(v0) // (JLONG) wsptr[5]
lw s7, 28(v0) // (JLONG) wsptr[7]
or s4, s4, t0
or s4, s4, t1
or s4, s4, t3
or s4, s4, s7
or s4, s4, s5
or s4, s4, s6
bnez s4, 5f
addiu v1, v1, -1
shra_r.w s5, t2, 5
andi s5, s5, 0x3ff
lbux s5, s5(a3)
lw s1, 0(a2)
replv.qb s5, s5
usw s5, 0(s1)
usw s5, 4(s1)
b 6f
nop
5:
addu t4, t0, t1 // z2 + z3
addiu t8, zero, 4433 // FIX_0_541196100
mul t5, t4, t8 // z1 = MULTIPLY(z2 + z3, FIX_0_541196100)
addiu t8, zero, 15137 // FIX_1_847759065
mul t1, t1, t8 // MULTIPLY(z3, FIX_1_847759065)
addiu t8, zero, 6270 // FIX_0_765366865
mul t0, t0, t8 // MULTIPLY(z2, FIX_0_765366865)
addu t4, t2, t3 // (JLONG) wsptr[0] + (JLONG) wsptr[4]
subu t2, t2, t3 // (JLONG) wsptr[0] - (JLONG) wsptr[4]
sll t4, t4, 13 // tmp0 = ((wsptr[0] + wsptr[4]) << CONST_BITS
sll t2, t2, 13 // tmp1 = ((wsptr[0] - wsptr[4]) << CONST_BITS
subu t1, t5, t1 // tmp2 = z1 + MULTIPLY(z3, - FIX_1_847759065)
subu t3, t2, t1 // tmp12 = tmp1 - tmp2
addu t2, t2, t1 // tmp11 = tmp1 + tmp2
addu t5, t5, t0 // tmp3 = z1 + MULTIPLY(z2, FIX_0_765366865)
subu t1, t4, t5 // tmp13 = tmp0 - tmp3
addu t0, t4, t5 // tmp10 = tmp0 + tmp3
lw t4, 28(v0) // tmp0 = (JLONG) wsptr[7]
lw t6, 12(v0) // tmp2 = (JLONG) wsptr[3]
lw t5, 20(v0) // tmp1 = (JLONG) wsptr[5]
lw t7, 4(v0) // tmp3 = (JLONG) wsptr[1]
addu s0, t4, t6 // z3 = tmp0 + tmp2
addiu t8, zero, 9633 // FIX_1_175875602
addu s1, t5, t7 // z4 = tmp1 + tmp3
addu s2, s0, s1 // z3 + z4
mul s2, s2, t8 // z5 = MULTIPLY(z3 + z4, FIX_1_175875602)
addu s3, t4, t7 // z1 = tmp0 + tmp3
addu t9, t5, t6 // z2 = tmp1 + tmp2
addiu t8, zero, 16069 // FIX_1_961570560
mul s0, s0, t8 // -z3 = MULTIPLY(z3, FIX_1_961570560)
addiu t8, zero, 3196 // FIX_0_390180644
mul s1, s1, t8 // -z4 = MULTIPLY(z4, FIX_0_390180644)
addiu t8, zero, 2446 // FIX_0_298631336
mul t4, t4, t8 // tmp0 = MULTIPLY(tmp0, FIX_0_298631336)
addiu t8, zero, 7373 // FIX_0_899976223
mul s3, s3, t8 // -z1 = MULTIPLY(z1, FIX_0_899976223)
addiu t8, zero, 16819 // FIX_2_053119869
mul t5, t5, t8 // tmp1 = MULTIPLY(tmp1, FIX_2_053119869)
addiu t8, zero, 20995 // FIX_2_562915447
mul t9, t9, t8 // -z2 = MULTIPLY(z2, FIX_2_562915447)
addiu t8, zero, 25172 // FIX_3_072711026
mul t6, t6, t8 // tmp2 = MULTIPLY(tmp2, FIX_3_072711026)
addiu t8, zero, 12299 // FIX_1_501321110
mul t7, t7, t8 // tmp3 = MULTIPLY(tmp3, FIX_1_501321110)
subu s0, s2, s0 // z3 += z5
subu s1, s2, s1 // z4 += z5
addu t4, t4, s0
subu t4, t4, s3 // tmp0
addu t5, t5, s1
subu t5, t5, t9 // tmp1
addu t6, t6, s0
subu t6, t6, t9 // tmp2
addu t7, t7, s1
subu t7, t7, s3 // tmp3
addu s0, t0, t7
subu t0, t0, t7
addu t7, t2, t6
subu t2, t2, t6
addu t6, t3, t5
subu t3, t3, t5
addu t5, t1, t4
subu t1, t1, t4
shra_r.w s0, s0, 18
shra_r.w t7, t7, 18
shra_r.w t6, t6, 18
shra_r.w t5, t5, 18
shra_r.w t1, t1, 18
shra_r.w t3, t3, 18
shra_r.w t2, t2, 18
shra_r.w t0, t0, 18
andi s0, s0, 0x3ff
andi t7, t7, 0x3ff
andi t6, t6, 0x3ff
andi t5, t5, 0x3ff
andi t1, t1, 0x3ff
andi t3, t3, 0x3ff
andi t2, t2, 0x3ff
andi t0, t0, 0x3ff
lw s1, 0(a2)
lbux s0, s0(a3)
lbux t7, t7(a3)
lbux t6, t6(a3)
lbux t5, t5(a3)
lbux t1, t1(a3)
lbux t3, t3(a3)
lbux t2, t2(a3)
lbux t0, t0(a3)
sb s0, 0(s1)
sb t7, 1(s1)
sb t6, 2(s1)
sb t5, 3(s1)
sb t1, 4(s1)
sb t3, 5(s1)
sb t2, 6(s1)
sb t0, 7(s1)
6:
addiu v0, v0, 32
bgtz v1, 4b
addiu a2, a2, 4
addiu sp, sp, 256
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_islow_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_ifast_cols_mips_dspr2)
/*
* a0 - inptr
* a1 - quantptr
* a2 - wsptr
* a3 - mips_idct_ifast_coefs
*/
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
addiu t9, a0, 16 // end address
or AT, a3, zero
0:
lw s0, 0(a1) // quantptr[DCTSIZE*0]
lw t0, 0(a0) // inptr[DCTSIZE*0]
lw t1, 16(a0) // inptr[DCTSIZE*1]
muleq_s.w.phl v0, t0, s0 // tmp0 ...
lw t2, 32(a0) // inptr[DCTSIZE*2]
lw t3, 48(a0) // inptr[DCTSIZE*3]
lw t4, 64(a0) // inptr[DCTSIZE*4]
lw t5, 80(a0) // inptr[DCTSIZE*5]
muleq_s.w.phr t0, t0, s0 // ... tmp0 ...
lw t6, 96(a0) // inptr[DCTSIZE*6]
lw t7, 112(a0) // inptr[DCTSIZE*7]
or s4, t1, t2
or s5, t3, t4
bnez s4, 1f
ins t0, v0, 16, 16 // ... tmp0
bnez s5, 1f
or s6, t5, t6
or s6, s6, t7
bnez s6, 1f
sw t0, 0(a2) // wsptr[DCTSIZE*0]
sw t0, 16(a2) // wsptr[DCTSIZE*1]
sw t0, 32(a2) // wsptr[DCTSIZE*2]
sw t0, 48(a2) // wsptr[DCTSIZE*3]
sw t0, 64(a2) // wsptr[DCTSIZE*4]
sw t0, 80(a2) // wsptr[DCTSIZE*5]
sw t0, 96(a2) // wsptr[DCTSIZE*6]
sw t0, 112(a2) // wsptr[DCTSIZE*7]
addiu a0, a0, 4
b 2f
addiu a1, a1, 4
1:
lw s1, 32(a1) // quantptr[DCTSIZE*2]
lw s2, 64(a1) // quantptr[DCTSIZE*4]
muleq_s.w.phl v0, t2, s1 // tmp1 ...
muleq_s.w.phr t2, t2, s1 // ... tmp1 ...
lw s0, 16(a1) // quantptr[DCTSIZE*1]
lw s1, 48(a1) // quantptr[DCTSIZE*3]
lw s3, 96(a1) // quantptr[DCTSIZE*6]
muleq_s.w.phl v1, t4, s2 // tmp2 ...
muleq_s.w.phr t4, t4, s2 // ... tmp2 ...
lw s2, 80(a1) // quantptr[DCTSIZE*5]
lw t8, 4(AT) // FIX(1.414213562)
ins t2, v0, 16, 16 // ... tmp1
muleq_s.w.phl v0, t6, s3 // tmp3 ...
muleq_s.w.phr t6, t6, s3 // ... tmp3 ...
ins t4, v1, 16, 16 // ... tmp2
addq.ph s4, t0, t4 // tmp10
subq.ph s5, t0, t4 // tmp11
ins t6, v0, 16, 16 // ... tmp3
subq.ph s6, t2, t6 // tmp12 ...
addq.ph s7, t2, t6 // tmp13
mulq_s.ph s6, s6, t8 // ... tmp12 ...
addq.ph t0, s4, s7 // tmp0
subq.ph t6, s4, s7 // tmp3
muleq_s.w.phl v0, t1, s0 // tmp4 ...
muleq_s.w.phr t1, t1, s0 // ... tmp4 ...
shll_s.ph s6, s6, 1 // x2
lw s3, 112(a1) // quantptr[DCTSIZE*7]
subq.ph s6, s6, s7 // ... tmp12
muleq_s.w.phl v1, t7, s3 // tmp7 ...
muleq_s.w.phr t7, t7, s3 // ... tmp7 ...
ins t1, v0, 16, 16 // ... tmp4
addq.ph t2, s5, s6 // tmp1
subq.ph t4, s5, s6 // tmp2
muleq_s.w.phl v0, t5, s2 // tmp6 ...
muleq_s.w.phr t5, t5, s2 // ... tmp6 ...
ins t7, v1, 16, 16 // ... tmp7
addq.ph s5, t1, t7 // z11
subq.ph s6, t1, t7 // z12
muleq_s.w.phl v1, t3, s1 // tmp5 ...
muleq_s.w.phr t3, t3, s1 // ... tmp5 ...
ins t5, v0, 16, 16 // ... tmp6
ins t3, v1, 16, 16 // ... tmp5
addq.ph s7, t5, t3 // z13
subq.ph v0, t5, t3 // z10
addq.ph t7, s5, s7 // tmp7
subq.ph s5, s5, s7 // tmp11 ...
addq.ph v1, v0, s6 // z5 ...
mulq_s.ph s5, s5, t8 // ... tmp11
lw t8, 8(AT) // FIX(1.847759065)
lw s4, 0(AT) // FIX(1.082392200)
addq.ph s0, t0, t7
subq.ph s1, t0, t7
mulq_s.ph v1, v1, t8 // ... z5
shll_s.ph s5, s5, 1 // x2
lw t8, 12(AT) // FIX(-2.613125930)
sw s0, 0(a2) // wsptr[DCTSIZE*0]
shll_s.ph v0, v0, 1 // x4
mulq_s.ph v0, v0, t8 // tmp12 ...
mulq_s.ph s4, s6, s4 // tmp10 ...
shll_s.ph v1, v1, 1 // x2
addiu a0, a0, 4
addiu a1, a1, 4
sw s1, 112(a2) // wsptr[DCTSIZE*7]
shll_s.ph s6, v0, 1 // x4
shll_s.ph s4, s4, 1 // x2
addq.ph s6, s6, v1 // ... tmp12
subq.ph t5, s6, t7 // tmp6
subq.ph s4, s4, v1 // ... tmp10
subq.ph t3, s5, t5 // tmp5
addq.ph s2, t2, t5
addq.ph t1, s4, t3 // tmp4
subq.ph s3, t2, t5
sw s2, 16(a2) // wsptr[DCTSIZE*1]
sw s3, 96(a2) // wsptr[DCTSIZE*6]
addq.ph v0, t4, t3
subq.ph v1, t4, t3
sw v0, 32(a2) // wsptr[DCTSIZE*2]
sw v1, 80(a2) // wsptr[DCTSIZE*5]
addq.ph v0, t6, t1
subq.ph v1, t6, t1
sw v0, 64(a2) // wsptr[DCTSIZE*4]
sw v1, 48(a2) // wsptr[DCTSIZE*3]
2:
bne a0, t9, 0b
addiu a2, a2, 4
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_ifast_cols_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_ifast_rows_mips_dspr2)
/*
* a0 - wsptr
* a1 - output_buf
* a2 - output_col
* a3 - mips_idct_ifast_coefs
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8, a3
addiu t9, a0, 128 // end address
lui s8, 0x8080
ori s8, s8, 0x8080
0:
lw AT, 36(sp) // restore $a3 (mips_idct_ifast_coefs)
lw t0, 0(a0) // wsptr[DCTSIZE*0+0/1] b a
lw s0, 16(a0) // wsptr[DCTSIZE*1+0/1] B A
lw t2, 4(a0) // wsptr[DCTSIZE*0+2/3] d c
lw s2, 20(a0) // wsptr[DCTSIZE*1+2/3] D C
lw t4, 8(a0) // wsptr[DCTSIZE*0+4/5] f e
lw s4, 24(a0) // wsptr[DCTSIZE*1+4/5] F E
lw t6, 12(a0) // wsptr[DCTSIZE*0+6/7] h g
lw s6, 28(a0) // wsptr[DCTSIZE*1+6/7] H G
precrq.ph.w t1, s0, t0 // B b
ins t0, s0, 16, 16 // A a
bnez t1, 1f
or s0, t2, s2
bnez s0, 1f
or s0, t4, s4
bnez s0, 1f
or s0, t6, s6
bnez s0, 1f
shll_s.ph s0, t0, 2 // A a
lw a3, 0(a1)
lw AT, 4(a1)
precrq.ph.w t0, s0, s0 // A A
ins s0, s0, 16, 16 // a a
addu a3, a3, a2
addu AT, AT, a2
precrq.qb.ph t0, t0, t0 // A A A A
precrq.qb.ph s0, s0, s0 // a a a a
addu.qb s0, s0, s8
addu.qb t0, t0, s8
sw s0, 0(a3)
sw s0, 4(a3)
sw t0, 0(AT)
sw t0, 4(AT)
addiu a0, a0, 32
bne a0, t9, 0b
addiu a1, a1, 8
b 2f
nop
1:
precrq.ph.w t3, s2, t2
ins t2, s2, 16, 16
precrq.ph.w t5, s4, t4
ins t4, s4, 16, 16
precrq.ph.w t7, s6, t6
ins t6, s6, 16, 16
lw t8, 4(AT) // FIX(1.414213562)
addq.ph s4, t0, t4 // tmp10
subq.ph s5, t0, t4 // tmp11
subq.ph s6, t2, t6 // tmp12 ...
addq.ph s7, t2, t6 // tmp13
mulq_s.ph s6, s6, t8 // ... tmp12 ...
addq.ph t0, s4, s7 // tmp0
subq.ph t6, s4, s7 // tmp3
shll_s.ph s6, s6, 1 // x2
subq.ph s6, s6, s7 // ... tmp12
addq.ph t2, s5, s6 // tmp1
subq.ph t4, s5, s6 // tmp2
addq.ph s5, t1, t7 // z11
subq.ph s6, t1, t7 // z12
addq.ph s7, t5, t3 // z13
subq.ph v0, t5, t3 // z10
addq.ph t7, s5, s7 // tmp7
subq.ph s5, s5, s7 // tmp11 ...
addq.ph v1, v0, s6 // z5 ...
mulq_s.ph s5, s5, t8 // ... tmp11
lw t8, 8(AT) // FIX(1.847759065)
lw s4, 0(AT) // FIX(1.082392200)
addq.ph s0, t0, t7 // tmp0 + tmp7
subq.ph s7, t0, t7 // tmp0 - tmp7
mulq_s.ph v1, v1, t8 // ... z5
lw a3, 0(a1)
lw t8, 12(AT) // FIX(-2.613125930)
shll_s.ph s5, s5, 1 // x2
addu a3, a3, a2
shll_s.ph v0, v0, 1 // x4
mulq_s.ph v0, v0, t8 // tmp12 ...
mulq_s.ph s4, s6, s4 // tmp10 ...
shll_s.ph v1, v1, 1 // x2
addiu a0, a0, 32
addiu a1, a1, 8
shll_s.ph s6, v0, 1 // x4
shll_s.ph s4, s4, 1 // x2
addq.ph s6, s6, v1 // ... tmp12
shll_s.ph s0, s0, 2
subq.ph t5, s6, t7 // tmp6
subq.ph s4, s4, v1 // ... tmp10
subq.ph t3, s5, t5 // tmp5
shll_s.ph s7, s7, 2
addq.ph t1, s4, t3 // tmp4
addq.ph s1, t2, t5 // tmp1 + tmp6
subq.ph s6, t2, t5 // tmp1 - tmp6
addq.ph s2, t4, t3 // tmp2 + tmp5
subq.ph s5, t4, t3 // tmp2 - tmp5
addq.ph s4, t6, t1 // tmp3 + tmp4
subq.ph s3, t6, t1 // tmp3 - tmp4
shll_s.ph s1, s1, 2
shll_s.ph s2, s2, 2
shll_s.ph s3, s3, 2
shll_s.ph s4, s4, 2
shll_s.ph s5, s5, 2
shll_s.ph s6, s6, 2
precrq.ph.w t0, s1, s0 // B A
ins s0, s1, 16, 16 // b a
precrq.ph.w t2, s3, s2 // D C
ins s2, s3, 16, 16 // d c
precrq.ph.w t4, s5, s4 // F E
ins s4, s5, 16, 16 // f e
precrq.ph.w t6, s7, s6 // H G
ins s6, s7, 16, 16 // h g
precrq.qb.ph t0, t2, t0 // D C B A
precrq.qb.ph s0, s2, s0 // d c b a
precrq.qb.ph t4, t6, t4 // H G F E
precrq.qb.ph s4, s6, s4 // h g f e
addu.qb s0, s0, s8
addu.qb s4, s4, s8
sw s0, 0(a3) // outptr[0/1/2/3] d c b a
sw s4, 4(a3) // outptr[4/5/6/7] h g f e
lw a3, -4(a1)
addu.qb t0, t0, s8
addu a3, a3, a2
addu.qb t4, t4, s8
sw t0, 0(a3) // outptr[0/1/2/3] D C B A
bne a0, t9, 0b
sw t4, 4(a3) // outptr[4/5/6/7] H G F E
2:
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8, a3
j ra
nop
END(jsimd_idct_ifast_rows_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_fdct_islow_mips_dspr2)
/*
* a0 - data
*/
SAVE_REGS_ON_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8
lui t0, 6437
ori t0, 2260
lui t1, 9633
ori t1, 11363
lui t2, 0xd39e
ori t2, 0xe6dc
lui t3, 0xf72d
ori t3, 9633
lui t4, 2261
ori t4, 9633
lui t5, 0xd39e
ori t5, 6437
lui t6, 9633
ori t6, 0xd39d
lui t7, 0xe6dc
ori t7, 2260
lui t8, 4433
ori t8, 10703
lui t9, 0xd630
ori t9, 4433
li s8, 8
move a1, a0
1:
lw s0, 0(a1) // tmp0 = 1|0
lw s1, 4(a1) // tmp1 = 3|2
lw s2, 8(a1) // tmp2 = 5|4
lw s3, 12(a1) // tmp3 = 7|6
packrl.ph s1, s1, s1 // tmp1 = 2|3
packrl.ph s3, s3, s3 // tmp3 = 6|7
subq.ph s7, s1, s2 // tmp7 = 2-5|3-4 = t5|t4
subq.ph s5, s0, s3 // tmp5 = 1-6|0-7 = t6|t7
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, s7, t0 // ac0 += t5* 6437 + t4* 2260
dpa.w.ph $ac0, s5, t1 // ac0 += t6* 9633 + t7* 11363
mult $ac1, $0, $0 // ac1 = 0
dpa.w.ph $ac1, s7, t2 // ac1 += t5*-11362 + t4* -6436
dpa.w.ph $ac1, s5, t3 // ac1 += t6* -2259 + t7* 9633
mult $ac2, $0, $0 // ac2 = 0
dpa.w.ph $ac2, s7, t4 // ac2 += t5* 2261 + t4* 9633
dpa.w.ph $ac2, s5, t5 // ac2 += t6*-11362 + t7* 6437
mult $ac3, $0, $0 // ac3 = 0
dpa.w.ph $ac3, s7, t6 // ac3 += t5* 9633 + t4*-11363
dpa.w.ph $ac3, s5, t7 // ac3 += t6* -6436 + t7* 2260
addq.ph s6, s1, s2 // tmp6 = 2+5|3+4 = t2|t3
addq.ph s4, s0, s3 // tmp4 = 1+6|0+7 = t1|t0
extr_r.w s0, $ac0, 11 // tmp0 = (ac0 + 1024) >> 11
extr_r.w s1, $ac1, 11 // tmp1 = (ac1 + 1024) >> 11
extr_r.w s2, $ac2, 11 // tmp2 = (ac2 + 1024) >> 11
extr_r.w s3, $ac3, 11 // tmp3 = (ac3 + 1024) >> 11
addq.ph s5, s4, s6 // tmp5 = t1+t2|t0+t3 = t11|t10
subq.ph s7, s4, s6 // tmp7 = t1-t2|t0-t3 = t12|t13
sh s0, 2(a1)
sh s1, 6(a1)
sh s2, 10(a1)
sh s3, 14(a1)
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, s7, t8 // ac0 += t12* 4433 + t13* 10703
mult $ac1, $0, $0 // ac1 = 0
dpa.w.ph $ac1, s7, t9 // ac1 += t12*-10704 + t13* 4433
sra s4, s5, 16 // tmp4 = t11
addiu a1, a1, 16
addiu s8, s8, -1
extr_r.w s0, $ac0, 11 // tmp0 = (ac0 + 1024) >> 11
extr_r.w s1, $ac1, 11 // tmp1 = (ac1 + 1024) >> 11
addu s2, s5, s4 // tmp2 = t10 + t11
subu s3, s5, s4 // tmp3 = t10 - t11
sll s2, s2, 2 // tmp2 = (t10 + t11) << 2
sll s3, s3, 2 // tmp3 = (t10 - t11) << 2
sh s2, -16(a1)
sh s3, -8(a1)
sh s0, -12(a1)
bgtz s8, 1b
sh s1, -4(a1)
li t0, 2260
li t1, 11363
li t2, 9633
li t3, 6436
li t4, 6437
li t5, 2261
li t6, 11362
li t7, 2259
li t8, 4433
li t9, 10703
li a1, 10704
li s8, 8
2:
lh a2, 0(a0) // 0
lh a3, 16(a0) // 8
lh v0, 32(a0) // 16
lh v1, 48(a0) // 24
lh s4, 64(a0) // 32
lh s5, 80(a0) // 40
lh s6, 96(a0) // 48
lh s7, 112(a0) // 56
addu s2, v0, s5 // tmp2 = 16 + 40
subu s5, v0, s5 // tmp5 = 16 - 40
addu s3, v1, s4 // tmp3 = 24 + 32
subu s4, v1, s4 // tmp4 = 24 - 32
addu s0, a2, s7 // tmp0 = 0 + 56
subu s7, a2, s7 // tmp7 = 0 - 56
addu s1, a3, s6 // tmp1 = 8 + 48
subu s6, a3, s6 // tmp6 = 8 - 48
addu a2, s0, s3 // tmp10 = tmp0 + tmp3
subu v1, s0, s3 // tmp13 = tmp0 - tmp3
addu a3, s1, s2 // tmp11 = tmp1 + tmp2
subu v0, s1, s2 // tmp12 = tmp1 - tmp2
mult s7, t1 // ac0 = tmp7 * c1
madd s4, t0 // ac0 += tmp4 * c0
madd s5, t4 // ac0 += tmp5 * c4
madd s6, t2 // ac0 += tmp6 * c2
mult $ac1, s7, t2 // ac1 = tmp7 * c2
msub $ac1, s4, t3 // ac1 -= tmp4 * c3
msub $ac1, s5, t6 // ac1 -= tmp5 * c6
msub $ac1, s6, t7 // ac1 -= tmp6 * c7
mult $ac2, s7, t4 // ac2 = tmp7 * c4
madd $ac2, s4, t2 // ac2 += tmp4 * c2
madd $ac2, s5, t5 // ac2 += tmp5 * c5
msub $ac2, s6, t6 // ac2 -= tmp6 * c6
mult $ac3, s7, t0 // ac3 = tmp7 * c0
msub $ac3, s4, t1 // ac3 -= tmp4 * c1
madd $ac3, s5, t2 // ac3 += tmp5 * c2
msub $ac3, s6, t3 // ac3 -= tmp6 * c3
extr_r.w s0, $ac0, 15 // tmp0 = (ac0 + 16384) >> 15
extr_r.w s1, $ac1, 15 // tmp1 = (ac1 + 16384) >> 15
extr_r.w s2, $ac2, 15 // tmp2 = (ac2 + 16384) >> 15
extr_r.w s3, $ac3, 15 // tmp3 = (ac3 + 16384) >> 15
addiu s8, s8, -1
addu s4, a2, a3 // tmp4 = tmp10 + tmp11
subu s5, a2, a3 // tmp5 = tmp10 - tmp11
sh s0, 16(a0)
sh s1, 48(a0)
sh s2, 80(a0)
sh s3, 112(a0)
mult v0, t8 // ac0 = tmp12 * c8
madd v1, t9 // ac0 += tmp13 * c9
mult $ac1, v1, t8 // ac1 = tmp13 * c8
msub $ac1, v0, a1 // ac1 -= tmp12 * c10
addiu a0, a0, 2
extr_r.w s6, $ac0, 15 // tmp6 = (ac0 + 16384) >> 15
extr_r.w s7, $ac1, 15 // tmp7 = (ac1 + 16384) >> 15
shra_r.w s4, s4, 2 // tmp4 = (tmp4 + 2) >> 2
shra_r.w s5, s5, 2 // tmp5 = (tmp5 + 2) >> 2
sh s4, -2(a0)
sh s5, 62(a0)
sh s6, 30(a0)
bgtz s8, 2b
sh s7, 94(a0)
RESTORE_REGS_FROM_STACK 40, s0, s1, s2, s3, s4, s5, s6, s7, s8
jr ra
nop
END(jsimd_fdct_islow_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_fdct_ifast_mips_dspr2)
/*
* a0 - data
*/
.set at
SAVE_REGS_ON_STACK 8, s0, s1
li a1, 0x014e014e // FIX_1_306562965 (334 << 16)|(334 & 0xffff)
li a2, 0x008b008b // FIX_0_541196100 (139 << 16)|(139 & 0xffff)
li a3, 0x00620062 // FIX_0_382683433 (98 << 16) |(98 & 0xffff)
li s1, 0x00b500b5 // FIX_0_707106781 (181 << 16)|(181 & 0xffff)
move v0, a0
addiu v1, v0, 128 // end address
0:
lw t0, 0(v0) // tmp0 = 1|0
lw t1, 4(v0) // tmp1 = 3|2
lw t2, 8(v0) // tmp2 = 5|4
lw t3, 12(v0) // tmp3 = 7|6
packrl.ph t1, t1, t1 // tmp1 = 2|3
packrl.ph t3, t3, t3 // tmp3 = 6|7
subq.ph t7, t1, t2 // tmp7 = 2-5|3-4 = t5|t4
subq.ph t5, t0, t3 // tmp5 = 1-6|0-7 = t6|t7
addq.ph t6, t1, t2 // tmp6 = 2+5|3+4 = t2|t3
addq.ph t4, t0, t3 // tmp4 = 1+6|0+7 = t1|t0
addq.ph t8, t4, t6 // tmp5 = t1+t2|t0+t3 = t11|t10
subq.ph t9, t4, t6 // tmp7 = t1-t2|t0-t3 = t12|t13
sra t4, t8, 16 // tmp4 = t11
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, t9, s1
mult $ac1, $0, $0 // ac1 = 0
dpa.w.ph $ac1, t7, a3 // ac1 += t4*98 + t5*98
dpsx.w.ph $ac1, t5, a3 // ac1 += t6*98 + t7*98
mult $ac2, $0, $0 // ac2 = 0
dpa.w.ph $ac2, t7, a2 // ac2 += t4*139 + t5*139
mult $ac3, $0, $0 // ac3 = 0
dpa.w.ph $ac3, t5, a1 // ac3 += t6*334 + t7*334
precrq.ph.w t0, t5, t7 // t0 = t5|t6
addq.ph t2, t8, t4 // tmp2 = t10 + t11
subq.ph t3, t8, t4 // tmp3 = t10 - t11
extr.w t4, $ac0, 8
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, t0, s1 // ac0 += t5*181 + t6*181
extr.w t0, $ac1, 8 // t0 = z5
extr.w t1, $ac2, 8 // t1 = MULTIPLY(tmp10, 139)
extr.w t7, $ac3, 8 // t2 = MULTIPLY(tmp12, 334)
extr.w t8, $ac0, 8 // t8 = z3 = MULTIPLY(tmp11, 181)
add t6, t1, t0 // t6 = z2
add t7, t7, t0 // t7 = z4
subq.ph t0, t5, t8 // t0 = z13 = tmp7 - z3
addq.ph t8, t5, t8 // t9 = z11 = tmp7 + z3
addq.ph t1, t0, t6 // t1 = z13 + z2
subq.ph t6, t0, t6 // t6 = z13 - z2
addq.ph t0, t8, t7 // t0 = z11 + z4
subq.ph t7, t8, t7 // t7 = z11 - z4
addq.ph t5, t4, t9
subq.ph t4, t9, t4
sh t2, 0(v0)
sh t5, 4(v0)
sh t3, 8(v0)
sh t4, 12(v0)
sh t1, 10(v0)
sh t6, 6(v0)
sh t0, 2(v0)
sh t7, 14(v0)
addiu v0, 16
bne v1, v0, 0b
nop
move v0, a0
addiu v1, v0, 16
1:
lh t0, 0(v0) // 0
lh t1, 16(v0) // 8
lh t2, 32(v0) // 16
lh t3, 48(v0) // 24
lh t4, 64(v0) // 32
lh t5, 80(v0) // 40
lh t6, 96(v0) // 48
lh t7, 112(v0) // 56
add t8, t0, t7 // t8 = tmp0
sub t7, t0, t7 // t7 = tmp7
add t0, t1, t6 // t0 = tmp1
sub t1, t1, t6 // t1 = tmp6
add t6, t2, t5 // t6 = tmp2
sub t5, t2, t5 // t5 = tmp5
add t2, t3, t4 // t2 = tmp3
sub t3, t3, t4 // t3 = tmp4
add t4, t8, t2 // t4 = tmp10 = tmp0 + tmp3
sub t8, t8, t2 // t8 = tmp13 = tmp0 - tmp3
sub s0, t0, t6 // s0 = tmp12 = tmp1 - tmp2
ins t8, s0, 16, 16 // t8 = tmp12|tmp13
add t2, t0, t6 // t2 = tmp11 = tmp1 + tmp2
mult $0, $0 // ac0 = 0
dpa.w.ph $ac0, t8, s1 // ac0 += t12*181 + t13*181
add s0, t4, t2 // t8 = tmp10+tmp11
sub t4, t4, t2 // t4 = tmp10-tmp11
sh s0, 0(v0)
sh t4, 64(v0)
extr.w t2, $ac0, 8 // z1 = MULTIPLY(tmp12+tmp13,FIX_0_707106781)
addq.ph t4, t8, t2 // t9 = tmp13 + z1
subq.ph t8, t8, t2 // t2 = tmp13 - z1
sh t4, 32(v0)
sh t8, 96(v0)
add t3, t3, t5 // t3 = tmp10 = tmp4 + tmp5
add t0, t5, t1 // t0 = tmp11 = tmp5 + tmp6
add t1, t1, t7 // t1 = tmp12 = tmp6 + tmp7
andi t4, a1, 0xffff
mul s0, t1, t4
sra s0, s0, 8 // s0 = z4 = MULTIPLY(tmp12, FIX_1_306562965)
ins t1, t3, 16, 16 // t1 = tmp10|tmp12
mult $0, $0 // ac0 = 0
mulsa.w.ph $ac0, t1, a3 // ac0 += t10*98 - t12*98
extr.w t8, $ac0, 8 // z5 = MULTIPLY(tmp10-tmp12,FIX_0_382683433)
add t2, t7, t8 // t2 = tmp7 + z5
sub t7, t7, t8 // t7 = tmp7 - z5
andi t4, a2, 0xffff
mul t8, t3, t4
sra t8, t8, 8 // t8 = z2 = MULTIPLY(tmp10, FIX_0_541196100)
andi t4, s1, 0xffff
mul t6, t0, t4
sra t6, t6, 8 // t6 = z3 = MULTIPLY(tmp11, FIX_0_707106781)
add t0, t6, t8 // t0 = z3 + z2
sub t1, t6, t8 // t1 = z3 - z2
add t3, t6, s0 // t3 = z3 + z4
sub t4, t6, s0 // t4 = z3 - z4
sub t5, t2, t1 // t5 = dataptr[5]
sub t6, t7, t0 // t6 = dataptr[3]
add t3, t2, t3 // t3 = dataptr[1]
add t4, t7, t4 // t4 = dataptr[7]
sh t5, 80(v0)
sh t6, 48(v0)
sh t3, 16(v0)
sh t4, 112(v0)
addiu v0, 2
bne v0, v1, 1b
nop
RESTORE_REGS_FROM_STACK 8, s0, s1
j ra
nop
END(jsimd_fdct_ifast_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_quantize_mips_dspr2)
/*
* a0 - coef_block
* a1 - divisors
* a2 - workspace
*/
.set at
SAVE_REGS_ON_STACK 16, s0, s1, s2
addiu v0, a2, 124 // v0 = workspace_end
lh t0, 0(a2)
lh t1, 0(a1)
lh t2, 128(a1)
sra t3, t0, 15
sll t3, t3, 1
addiu t3, t3, 1
mul t0, t0, t3
lh t4, 384(a1)
lh t5, 130(a1)
lh t6, 2(a2)
lh t7, 2(a1)
lh t8, 386(a1)
1:
andi t1, 0xffff
add t9, t0, t2
andi t9, 0xffff
mul v1, t9, t1
sra s0, t6, 15
sll s0, s0, 1
addiu s0, s0, 1
addiu t9, t4, 16
srav v1, v1, t9
mul v1, v1, t3
mul t6, t6, s0
andi t7, 0xffff
addiu a2, a2, 4
addiu a1, a1, 4
add s1, t6, t5
andi s1, 0xffff
sh v1, 0(a0)
mul s2, s1, t7
addiu s1, t8, 16
srav s2, s2, s1
mul s2,s2, s0
lh t0, 0(a2)
lh t1, 0(a1)
sra t3, t0, 15
sll t3, t3, 1
addiu t3, t3, 1
mul t0, t0, t3
lh t2, 128(a1)
lh t4, 384(a1)
lh t5, 130(a1)
lh t8, 386(a1)
lh t6, 2(a2)
lh t7, 2(a1)
sh s2, 2(a0)
lh t0, 0(a2)
sra t3, t0, 15
sll t3, t3, 1
addiu t3, t3, 1
mul t0, t0,t3
bne a2, v0, 1b
addiu a0, a0, 4
andi t1, 0xffff
add t9, t0, t2
andi t9, 0xffff
mul v1, t9, t1
sra s0, t6, 15
sll s0, s0, 1
addiu s0, s0, 1
addiu t9, t4, 16
srav v1, v1, t9
mul v1, v1, t3
mul t6, t6, s0
andi t7, 0xffff
sh v1, 0(a0)
add s1, t6, t5
andi s1, 0xffff
mul s2, s1, t7
addiu s1, t8, 16
addiu a2, a2, 4
addiu a1, a1, 4
srav s2, s2, s1
mul s2, s2, s0
sh s2, 2(a0)
RESTORE_REGS_FROM_STACK 16, s0, s1, s2
j ra
nop
END(jsimd_quantize_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_quantize_float_mips_dspr2)
/*
* a0 - coef_block
* a1 - divisors
* a2 - workspace
*/
.set at
li t1, 0x46800100 //integer representation 16384.5
mtc1 t1, f0
li t0, 63
0:
lwc1 f2, 0(a2)
lwc1 f10, 0(a1)
lwc1 f4, 4(a2)
lwc1 f12, 4(a1)
lwc1 f6, 8(a2)
lwc1 f14, 8(a1)
lwc1 f8, 12(a2)
lwc1 f16, 12(a1)
madd.s f2, f0, f2, f10
madd.s f4, f0, f4, f12
madd.s f6, f0, f6, f14
madd.s f8, f0, f8, f16
lwc1 f10, 16(a1)
lwc1 f12, 20(a1)
trunc.w.s f2, f2
trunc.w.s f4, f4
trunc.w.s f6, f6
trunc.w.s f8, f8
lwc1 f14, 24(a1)
lwc1 f16, 28(a1)
mfc1 t1, f2
mfc1 t2, f4
mfc1 t3, f6
mfc1 t4, f8
lwc1 f2, 16(a2)
lwc1 f4, 20(a2)
lwc1 f6, 24(a2)
lwc1 f8, 28(a2)
madd.s f2, f0, f2, f10
madd.s f4, f0, f4, f12
madd.s f6, f0, f6, f14
madd.s f8, f0, f8, f16
addiu t1, t1, -16384
addiu t2, t2, -16384
addiu t3, t3, -16384
addiu t4, t4, -16384
trunc.w.s f2, f2
trunc.w.s f4, f4
trunc.w.s f6, f6
trunc.w.s f8, f8
sh t1, 0(a0)
sh t2, 2(a0)
sh t3, 4(a0)
sh t4, 6(a0)
mfc1 t1, f2
mfc1 t2, f4
mfc1 t3, f6
mfc1 t4, f8
addiu t0, t0, -8
addiu a2, a2, 32
addiu a1, a1, 32
addiu t1, t1, -16384
addiu t2, t2, -16384
addiu t3, t3, -16384
addiu t4, t4, -16384
sh t1, 8(a0)
sh t2, 10(a0)
sh t3, 12(a0)
sh t4, 14(a0)
bgez t0, 0b
addiu a0, a0, 16
j ra
nop
END(jsimd_quantize_float_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_2x2_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - output_buf
* a3 - output_col
*/
.set at
SAVE_REGS_ON_STACK 24, s0, s1, s2, s3, s4, s5
addiu sp, sp, -40
move v0, sp
addiu s2, zero, 29692
addiu s3, zero, -10426
addiu s4, zero, 6967
addiu s5, zero, -5906
lh t0, 0(a1) // t0 = inptr[DCTSIZE*0]
lh t5, 0(a0) // t5 = quantptr[DCTSIZE*0]
lh t1, 48(a1) // t1 = inptr[DCTSIZE*3]
lh t6, 48(a0) // t6 = quantptr[DCTSIZE*3]
mul t4, t5, t0
lh t0, 16(a1) // t0 = inptr[DCTSIZE*1]
lh t5, 16(a0) // t5 = quantptr[DCTSIZE*1]
mul t6, t6, t1
mul t5, t5, t0
lh t2, 80(a1) // t2 = inptr[DCTSIZE*5]
lh t7, 80(a0) // t7 = quantptr[DCTSIZE*5]
lh t3, 112(a1) // t3 = inptr[DCTSIZE*7]
lh t8, 112(a0) // t8 = quantptr[DCTSIZE*7]
mul t7, t7, t2
mult zero, zero
mul t8, t8, t3
li s0, 0x73FCD746 // s0 = (29692 << 16) | (-10426 & 0xffff)
li s1, 0x1B37E8EE // s1 = (6967 << 16) | (-5906 & 0xffff)
ins t6, t5, 16, 16 // t6 = t5|t6
sll t4, t4, 15
dpa.w.ph $ac0, t6, s0
lh t1, 2(a1)
lh t6, 2(a0)
ins t8, t7, 16, 16 // t8 = t7|t8
dpa.w.ph $ac0, t8, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 18(a1)
lh t6, 18(a0)
lh t2, 50(a1)
lh t7, 50(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 82(a1)
lh t2, 82(a0)
lh t3, 114(a1)
lh t4, 114(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 0(v0)
sw t8, 20(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
lh t1, 6(a1)
lh t6, 6(a0)
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 22(a1)
lh t6, 22(a0)
lh t2, 54(a1)
lh t7, 54(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 86(a1)
lh t2, 86(a0)
lh t3, 118(a1)
lh t4, 118(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 4(v0)
sw t8, 24(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
lh t1, 10(a1)
lh t6, 10(a0)
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 26(a1)
lh t6, 26(a0)
lh t2, 58(a1)
lh t7, 58(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 90(a1)
lh t2, 90(a0)
lh t3, 122(a1)
lh t4, 122(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 8(v0)
sw t8, 28(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
lh t1, 14(a1)
lh t6, 14(a0)
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
mul t5, t6, t1
lh t1, 30(a1)
lh t6, 30(a0)
lh t2, 62(a1)
lh t7, 62(a0)
mul t6, t6, t1
subu t8, t4, t0
mul t7, t7, t2
addu t0, t4, t0
shra_r.w t0, t0, 13
lh t1, 94(a1)
lh t2, 94(a0)
lh t3, 126(a1)
lh t4, 126(a0)
shra_r.w t8, t8, 13
mul t1, t1, t2
mul t3, t3, t4
sw t0, 12(v0)
sw t8, 32(v0)
sll t4, t5, 15
ins t7, t6, 16, 16
mult zero, zero
dpa.w.ph $ac0, t7, s0
ins t3, t1, 16, 16
dpa.w.ph $ac0, t3, s1
mflo t0, $ac0
lw t9, 0(a2)
lw t3, 0(v0)
lw t7, 4(v0)
lw t1, 8(v0)
addu t9, t9, a3
sll t3, t3, 15
subu t8, t4, t0
addu t0, t4, t0
shra_r.w t0, t0, 13
shra_r.w t8, t8, 13
sw t0, 16(v0)
sw t8, 36(v0)
lw t5, 12(v0)
lw t6, 16(v0)
mult t7, s2
madd t1, s3
madd t5, s4
madd t6, s5
lw t5, 24(v0)
lw t7, 28(v0)
mflo t0, $ac0
lw t8, 32(v0)
lw t2, 36(v0)
mult $ac1, t5, s2
madd $ac1, t7, s3
madd $ac1, t8, s4
madd $ac1, t2, s5
addu t1, t3, t0
subu t6, t3, t0
shra_r.w t1, t1, 20
shra_r.w t6, t6, 20
mflo t4, $ac1
shll_s.w t1, t1, 24
shll_s.w t6, t6, 24
sra t1, t1, 24
sra t6, t6, 24
addiu t1, t1, 128
addiu t6, t6, 128
lw t0, 20(v0)
sb t1, 0(t9)
sb t6, 1(t9)
sll t0, t0, 15
lw t9, 4(a2)
addu t1, t0, t4
subu t6, t0, t4
addu t9, t9, a3
shra_r.w t1, t1, 20
shra_r.w t6, t6, 20
shll_s.w t1, t1, 24
shll_s.w t6, t6, 24
sra t1, t1, 24
sra t6, t6, 24
addiu t1, t1, 128
addiu t6, t6, 128
sb t1, 0(t9)
sb t6, 1(t9)
addiu sp, sp, 40
RESTORE_REGS_FROM_STACK 24, s0, s1, s2, s3, s4, s5
j ra
nop
END(jsimd_idct_2x2_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_4x4_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - output_buf
* a3 - output_col
* 16(sp) - workspace[DCTSIZE*4]; // buffers data between passes
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
lw v1, 48(sp)
move t0, a1
move t1, v1
li t9, 4
li s0, 0x2e75f93e
li s1, 0x21f9ba79
li s2, 0xecc2efb0
li s3, 0x52031ccd
0:
lh s6, 32(t0) // inptr[DCTSIZE*2]
lh t6, 32(a0) // quantptr[DCTSIZE*2]
lh s7, 96(t0) // inptr[DCTSIZE*6]
lh t7, 96(a0) // quantptr[DCTSIZE*6]
mul t6, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh s4, 0(t0) // inptr[DCTSIZE*0]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s5, 0(a0) // quantptr[0]
li s6, 15137
li s7, 6270
mul t2, s4, s5 // tmp0 = (inptr[0] * quantptr[0])
mul t6, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh t5, 112(t0) // inptr[DCTSIZE*7]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s4, 112(a0) // quantptr[DCTSIZE*7]
lh v0, 80(t0) // inptr[DCTSIZE*5]
lh s5, 80(a0) // quantptr[DCTSIZE*5]
lh s6, 48(a0) // quantptr[DCTSIZE*3]
sll t2, t2, 14 // tmp0 <<= (CONST_BITS+1)
lh s7, 16(a0) // quantptr[DCTSIZE*1]
lh t8, 16(t0) // inptr[DCTSIZE*1]
subu t6, t6, t7 // tmp2 = MULTIPLY(z2, t5) - MULTIPLY(z3, t6)
lh t7, 48(t0) // inptr[DCTSIZE*3]
mul t5, s4, t5 // z1 = (inptr[DCTSIZE*7] * quantptr[DCTSIZE*7])
mul v0, s5, v0 // z2 = (inptr[DCTSIZE*5] * quantptr[DCTSIZE*5])
mul t7, s6, t7 // z3 = (inptr[DCTSIZE*3] * quantptr[DCTSIZE*3])
mul t8, s7, t8 // z4 = (inptr[DCTSIZE*1] * quantptr[DCTSIZE*1])
addu t3, t2, t6 // tmp10 = tmp0 + z2
subu t4, t2, t6 // tmp10 = tmp0 - z2
mult $ac0, zero, zero
mult $ac1, zero, zero
ins t5, v0, 16, 16
ins t7, t8, 16, 16
addiu t9, t9, -1
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
mflo s4, $ac0
mflo s5, $ac1
addiu a0, a0, 2
addiu t1, t1, 4
addiu t0, t0, 2
addu t6, t4, s4
subu t5, t4, s4
addu s6, t3, s5
subu s7, t3, s5
shra_r.w t6, t6, 12 // DESCALE(tmp12 + temp1, 12)
shra_r.w t5, t5, 12 // DESCALE(tmp12 - temp1, 12)
shra_r.w s6, s6, 12 // DESCALE(tmp10 + temp2, 12)
shra_r.w s7, s7, 12 // DESCALE(tmp10 - temp2, 12)
sw t6, 28(t1)
sw t5, 60(t1)
sw s6, -4(t1)
bgtz t9, 0b
sw s7, 92(t1)
// second loop three pass
li t9, 3
1:
lh s6, 34(t0) // inptr[DCTSIZE*2]
lh t6, 34(a0) // quantptr[DCTSIZE*2]
lh s7, 98(t0) // inptr[DCTSIZE*6]
lh t7, 98(a0) // quantptr[DCTSIZE*6]
mul t6, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh s4, 2(t0) // inptr[DCTSIZE*0]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s5, 2(a0) // quantptr[DCTSIZE*0]
li s6, 15137
li s7, 6270
mul t2, s4, s5 // tmp0 = (inptr[0] * quantptr[0])
mul v0, s6, t6 // z2 = (inptr[DCTSIZE*2] * quantptr[DCTSIZE*2])
lh t5, 114(t0) // inptr[DCTSIZE*7]
mul t7, s7, t7 // z3 = (inptr[DCTSIZE*6] * quantptr[DCTSIZE*6])
lh s4, 114(a0) // quantptr[DCTSIZE*7]
lh s5, 82(a0) // quantptr[DCTSIZE*5]
lh t6, 82(t0) // inptr[DCTSIZE*5]
sll t2, t2, 14 // tmp0 <<= (CONST_BITS+1)
lh s6, 50(a0) // quantptr[DCTSIZE*3]
lh t8, 18(t0) // inptr[DCTSIZE*1]
subu v0, v0, t7 // tmp2 = MULTIPLY(z2, t5) - MULTIPLY(z3, t6)
lh t7, 50(t0) // inptr[DCTSIZE*3]
lh s7, 18(a0) // quantptr[DCTSIZE*1]
mul t5, s4, t5 // z1 = (inptr[DCTSIZE*7] * quantptr[DCTSIZE*7])
mul t6, s5, t6 // z2 = (inptr[DCTSIZE*5] * quantptr[DCTSIZE*5])
mul t7, s6, t7 // z3 = (inptr[DCTSIZE*3] * quantptr[DCTSIZE*3])
mul t8, s7, t8 // z4 = (inptr[DCTSIZE*1] * quantptr[DCTSIZE*1])
addu t3, t2, v0 // tmp10 = tmp0 + z2
subu t4, t2, v0 // tmp10 = tmp0 - z2
mult $ac0, zero, zero
mult $ac1, zero, zero
ins t5, t6, 16, 16
ins t7, t8, 16, 16
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
mflo t5, $ac0
mflo t6, $ac1
addiu t9, t9, -1
addiu t0, t0, 2
addiu a0, a0, 2
addiu t1, t1, 4
addu s5, t4, t5
subu s4, t4, t5
addu s6, t3, t6
subu s7, t3, t6
shra_r.w s5, s5, 12 // DESCALE(tmp12 + temp1, 12)
shra_r.w s4, s4, 12 // DESCALE(tmp12 - temp1, 12)
shra_r.w s6, s6, 12 // DESCALE(tmp10 + temp2, 12)
shra_r.w s7, s7, 12 // DESCALE(tmp10 - temp2, 12)
sw s5, 32(t1)
sw s4, 64(t1)
sw s6, 0(t1)
bgtz t9, 1b
sw s7, 96(t1)
move t1, v1
li s4, 15137
lw s6, 8(t1) // wsptr[2]
li s5, 6270
lw s7, 24(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((JLONG) wsptr[2], FIX_1_847759065)
lw t2, 0(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((JLONG) wsptr[6], - FIX_0_765366865)
lh t5, 28(t1) // wsptr[7]
lh t6, 20(t1) // wsptr[5]
lh t7, 12(t1) // wsptr[3]
lh t8, 4(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((JLONG) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, 19)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, 19)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, 19)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, 19)
sll s4, t9, 2
lw v0, 0(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
// 2
li s4, 15137
lw s6, 40(t1) // wsptr[2]
li s5, 6270
lw s7, 56(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((JLONG) wsptr[2], FIX_1_847759065)
lw t2, 32(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((JLONG) wsptr[6], - FIX_0_765366865)
lh t5, 60(t1) // wsptr[7]
lh t6, 52(t1) // wsptr[5]
lh t7, 44(t1) // wsptr[3]
lh t8, 36(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((JLONG) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, CONST_BITS-PASS1_BITS+1)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, CONST_BITS-PASS1_BITS+1)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, CONST_BITS-PASS1_BITS+1)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, CONST_BITS-PASS1_BITS+1)
sll s4, t9, 2
lw v0, 4(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
// 3
li s4, 15137
lw s6, 72(t1) // wsptr[2]
li s5, 6270
lw s7, 88(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((JLONG) wsptr[2], FIX_1_847759065)
lw t2, 64(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((JLONG) wsptr[6], - FIX_0_765366865)
lh t5, 92(t1) // wsptr[7]
lh t6, 84(t1) // wsptr[5]
lh t7, 76(t1) // wsptr[3]
lh t8, 68(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((JLONG) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, 19)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, 19)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, 19)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, 19)
sll s4, t9, 2
lw v0, 8(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
li s4, 15137
lw s6, 104(t1) // wsptr[2]
li s5, 6270
lw s7, 120(t1) // wsptr[6]
mul s4, s4, s6 // MULTIPLY((JLONG) wsptr[2], FIX_1_847759065)
lw t2, 96(t1) // wsptr[0]
mul s5, s5, s7 // MULTIPLY((JLONG) wsptr[6], -FIX_0_765366865)
lh t5, 124(t1) // wsptr[7]
lh t6, 116(t1) // wsptr[5]
lh t7, 108(t1) // wsptr[3]
lh t8, 100(t1) // wsptr[1]
ins t5, t6, 16, 16
ins t7, t8, 16, 16
mult $ac0, zero, zero
dpa.w.ph $ac0, t5, s0
dpa.w.ph $ac0, t7, s1
mult $ac1, zero, zero
dpa.w.ph $ac1, t5, s2
dpa.w.ph $ac1, t7, s3
sll t2, t2, 14 // tmp0 = ((JLONG) wsptr[0]) << (CONST_BITS+1)
mflo s6, $ac0
// MULTIPLY(wsptr[2], FIX_1_847759065 + MULTIPLY(wsptr[6], -FIX_0_765366865)
subu s4, s4, s5
addu t3, t2, s4 // tmp10 = tmp0 + z2;
mflo s7, $ac1
subu t4, t2, s4 // tmp10 = tmp0 - z2;
addu t7, t4, s6
subu t8, t4, s6
addu t5, t3, s7
subu t6, t3, s7
shra_r.w t5, t5, 19 // DESCALE(tmp10 + temp2, 19)
shra_r.w t6, t6, 19 // DESCALE(tmp10 - temp2, 19)
shra_r.w t7, t7, 19 // DESCALE(tmp12 + temp1, 19)
shra_r.w t8, t8, 19 // DESCALE(tmp12 - temp1, 19)
sll s4, t9, 2
lw v0, 12(a2) // output_buf[ctr]
shll_s.w t5, t5, 24
shll_s.w t6, t6, 24
shll_s.w t7, t7, 24
shll_s.w t8, t8, 24
sra t5, t5, 24
sra t6, t6, 24
sra t7, t7, 24
sra t8, t8, 24
addu v0, v0, a3 // outptr = output_buf[ctr] + output_col
addiu t5, t5, 128
addiu t6, t6, 128
addiu t7, t7, 128
addiu t8, t8, 128
sb t5, 0(v0)
sb t7, 1(v0)
sb t8, 2(v0)
sb t6, 3(v0)
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_4x4_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_6x6_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - output_buf
* a3 - output_col
*/
.set at
SAVE_REGS_ON_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
addiu sp, sp, -144
move v0, sp
addiu v1, v0, 24
addiu t9, zero, 5793
addiu s0, zero, 10033
addiu s1, zero, 2998
1:
lh s2, 0(a0) // q0 = quantptr[ 0]
lh s3, 32(a0) // q1 = quantptr[16]
lh s4, 64(a0) // q2 = quantptr[32]
lh t2, 64(a1) // tmp2 = inptr[32]
lh t1, 32(a1) // tmp1 = inptr[16]
lh t0, 0(a1) // tmp0 = inptr[ 0]
mul t2, t2, s4 // tmp2 = tmp2 * q2
mul t1, t1, s3 // tmp1 = tmp1 * q1
mul t0, t0, s2 // tmp0 = tmp0 * q0
lh t6, 16(a1) // z1 = inptr[ 8]
lh t8, 80(a1) // z3 = inptr[40]
lh t7, 48(a1) // z2 = inptr[24]
lh s2, 16(a0) // q0 = quantptr[ 8]
lh s4, 80(a0) // q2 = quantptr[40]
lh s3, 48(a0) // q1 = quantptr[24]
mul t2, t2, t9 // tmp2 = tmp2 * 5793
mul t1, t1, s0 // tmp1 = tmp1 * 10033
sll t0, t0, 13 // tmp0 = tmp0 << 13
mul t6, t6, s2 // z1 = z1 * q0
mul t8, t8, s4 // z3 = z3 * q2
mul t7, t7, s3 // z2 = z2 * q1
addu t3, t0, t2 // tmp10 = tmp0 + tmp2
sll t2, t2, 1 // tmp2 = tmp2 << 2
subu t4, t0, t2 // tmp11 = tmp0 - tmp2;
subu t5, t3, t1 // tmp12 = tmp10 - tmp1
addu t3, t3, t1 // tmp10 = tmp10 + tmp1
addu t1, t6, t8 // tmp1 = z1 + z3
mul t1, t1, s1 // tmp1 = tmp1 * 2998
shra_r.w t4, t4, 11 // tmp11 = (tmp11 + 1024) >> 11
subu t2, t6, t8 // tmp2 = z1 - z3
subu t2, t2, t7 // tmp2 = tmp2 - z2
sll t2, t2, 2 // tmp2 = tmp2 << 2
addu t0, t6, t7 // tmp0 = z1 + z2
sll t0, t0, 13 // tmp0 = tmp0 << 13
subu s2, t8, t7 // q0 = z3 - z2
sll s2, s2, 13 // q0 = q0 << 13
addu t0, t0, t1 // tmp0 = tmp0 + tmp1
addu t1, s2, t1 // tmp1 = q0 + tmp1
addu s2, t4, t2 // q0 = tmp11 + tmp2
subu s3, t4, t2 // q1 = tmp11 - tmp2
addu t6, t3, t0 // z1 = tmp10 + tmp0
subu t7, t3, t0 // z2 = tmp10 - tmp0
addu t4, t5, t1 // tmp11 = tmp12 + tmp1
subu t5, t5, t1 // tmp12 = tmp12 - tmp1
shra_r.w t6, t6, 11 // z1 = (z1 + 1024) >> 11
shra_r.w t7, t7, 11 // z2 = (z2 + 1024) >> 11
shra_r.w t4, t4, 11 // tmp11 = (tmp11 + 1024) >> 11
shra_r.w t5, t5, 11 // tmp12 = (tmp12 + 1024) >> 11
sw s2, 24(v0)
sw s3, 96(v0)
sw t6, 0(v0)
sw t7, 120(v0)
sw t4, 48(v0)
sw t5, 72(v0)
addiu v0, v0, 4
addiu a1, a1, 2
bne v0, v1, 1b
addiu a0, a0, 2
/* Pass 2: process 6 rows from work array, store into output array. */
move v0, sp
addiu v1, v0, 144
2:
lw t0, 0(v0)
lw t2, 16(v0)
lw s5, 0(a2)
addiu t0, t0, 16
sll t0, t0, 13
mul t3, t2, t9
lw t6, 4(v0)
lw t8, 20(v0)
lw t7, 12(v0)
addu s5, s5, a3
addu s6, t6, t8
mul s6, s6, s1
addu t1, t0, t3
subu t4, t0, t3
subu t4, t4, t3
lw t3, 8(v0)
mul t0, t3, s0
addu s7, t6, t7
sll s7, s7, 13
addu s7, s6, s7
subu t2, t8, t7
sll t2, t2, 13
addu t2, s6, t2
subu s6, t6, t7
subu s6, s6, t8
sll s6, s6, 13
addu t3, t1, t0
subu t5, t1, t0
addu t6, t3, s7
subu t3, t3, s7
addu t7, t4, s6
subu t4, t4, s6
addu t8, t5, t2
subu t5, t5, t2
shll_s.w t6, t6, 6
shll_s.w t3, t3, 6
shll_s.w t7, t7, 6
shll_s.w t4, t4, 6
shll_s.w t8, t8, 6
shll_s.w t5, t5, 6
sra t6, t6, 24
addiu t6, t6, 128
sra t3, t3, 24
addiu t3, t3, 128
sb t6, 0(s5)
sra t7, t7, 24
addiu t7, t7, 128
sb t3, 5(s5)
sra t4, t4, 24
addiu t4, t4, 128
sb t7, 1(s5)
sra t8, t8, 24
addiu t8, t8, 128
sb t4, 4(s5)
addiu v0, v0, 24
sra t5, t5, 24
addiu t5, t5, 128
sb t8, 2(s5)
addiu a2, a2, 4
bne v0, v1, 2b
sb t5, 3(s5)
addiu sp, sp, 144
RESTORE_REGS_FROM_STACK 32, s0, s1, s2, s3, s4, s5, s6, s7
j ra
nop
END(jsimd_idct_6x6_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_12x12_pass1_mips_dspr2)
/*
* a0 - compptr->dct_table
* a1 - coef_block
* a2 - workspace
*/
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
li a3, 8
1:
// odd part
lh t0, 48(a1)
lh t1, 48(a0)
lh t2, 16(a1)
lh t3, 16(a0)
lh t4, 80(a1)
lh t5, 80(a0)
lh t6, 112(a1)
lh t7, 112(a0)
mul t0, t0, t1 // z2
mul t1, t2, t3 // z1
mul t2, t4, t5 // z3
mul t3, t6, t7 // z4
li t4, 10703 // FIX(1.306562965)
li t5, 4433 // FIX_0_541196100
li t6, 7053 // FIX(0.860918669)
mul t4, t0,t4 // tmp11
mul t5, t0,t5 // -tmp14
addu t7, t1,t2 // tmp10
addu t8, t7,t3 // tmp10 + z4
mul t6, t6, t8 // tmp15
li t8, 2139 // FIX(0.261052384)
mul t8, t7, t8 // MULTIPLY(tmp10, FIX(0.261052384))
li t7, 2295 // FIX(0.280143716)
mul t7, t1, t7 // MULTIPLY(z1, FIX(0.280143716))
addu t9, t2, t3 // z3 + z4
li s0, 8565 // FIX(1.045510580)
mul t9, t9, s0 // -tmp13
li s0, 12112 // FIX(1.478575242)
mul s0, t2, s0 // MULTIPLY(z3, FIX(1.478575242)
li s1, 12998 // FIX(1.586706681)
mul s1, t3, s1 // MULTIPLY(z4, FIX(1.586706681))
li s2, 5540 // FIX(0.676326758)
mul s2, t1, s2 // MULTIPLY(z1, FIX(0.676326758))
li s3, 16244 // FIX(1.982889723)
mul s3, t3, s3 // MULTIPLY(z4, FIX(1.982889723))
subu t1, t1, t3 // z1-=z4
subu t0, t0, t2 // z2-=z3
addu t2, t0, t1 // z1+z2
li t3, 4433 // FIX_0_541196100
mul t2, t2, t3 // z3
li t3, 6270 // FIX_0_765366865
mul t1, t1, t3 // MULTIPLY(z1, FIX_0_765366865)
li t3, 15137 // FIX_0_765366865
mul t0, t0, t3 // MULTIPLY(z2, FIX_1_847759065)
addu t8, t6, t8 // tmp12
addu t3, t8, t4 // tmp12 + tmp11
addu t3, t3, t7 // tmp10
subu t8, t8, t9 // tmp12 + tmp13
addu s0, t5, s0
subu t8, t8, s0 // tmp12
subu t9, t6, t9
subu s1, s1, t4
addu t9, t9, s1 // tmp13
subu t6, t6, t5
subu t6, t6, s2
subu t6, t6, s3 // tmp15
// even part start
lh t4, 64(a1)
lh t5, 64(a0)
lh t7, 32(a1)
lh s0, 32(a0)
lh s1, 0(a1)
lh s2, 0(a0)
lh s3, 96(a1)
lh v0, 96(a0)
mul t4, t4, t5 // DEQUANTIZE(inptr[DCTSIZE*4],quantptr[DCTSIZE*4])
mul t5, t7, s0 // DEQUANTIZE(inptr[DCTSIZE*2],quantptr[DCTSIZE*2])
mul t7, s1, s2 // DEQUANTIZE(inptr[DCTSIZE*0],quantptr[DCTSIZE*0])
mul s0, s3, v0 // DEQUANTIZE(inptr[DCTSIZE*6],quantptr[DCTSIZE*6])
// odd part end
addu t1, t2, t1 // tmp11
subu t0, t2, t0 // tmp14
// update counter and pointers
addiu a3, a3, -1
addiu a0, a0, 2
addiu a1, a1, 2
// even part rest
li s1, 10033
li s2, 11190
mul t4, t4, s1 // z4
mul s1, t5, s2 // z4
sll t5, t5, 13 // z1
sll t7, t7, 13
addiu t7, t7, 1024 // z3
sll s0, s0, 13 // z2
addu s2, t7, t4 // tmp10
subu t4, t7, t4 // tmp11
subu s3, t5, s0 // tmp12
addu t2, t7, s3 // tmp21
subu s3, t7, s3 // tmp24
addu t7, s1, s0 // tmp12
addu v0, s2, t7 // tmp20
subu s2, s2, t7 // tmp25
subu s1, s1, t5 // z4 - z1
subu s1, s1, s0 // tmp12
addu s0, t4, s1 // tmp22
subu t4, t4, s1 // tmp23
// final output stage
addu t5, v0, t3
subu v0, v0, t3
addu t3, t2, t1
subu t2, t2, t1
addu t1, s0, t8
subu s0, s0, t8
addu t8, t4, t9
subu t4, t4, t9
addu t9, s3, t0
subu s3, s3, t0
addu t0, s2, t6
subu s2, s2, t6
sra t5, t5, 11
sra t3, t3, 11
sra t1, t1, 11
sra t8, t8, 11
sra t9, t9, 11
sra t0, t0, 11
sra s2, s2, 11
sra s3, s3, 11
sra t4, t4, 11
sra s0, s0, 11
sra t2, t2, 11
sra v0, v0, 11
sw t5, 0(a2)
sw t3, 32(a2)
sw t1, 64(a2)
sw t8, 96(a2)
sw t9, 128(a2)
sw t0, 160(a2)
sw s2, 192(a2)
sw s3, 224(a2)
sw t4, 256(a2)
sw s0, 288(a2)
sw t2, 320(a2)
sw v0, 352(a2)
bgtz a3, 1b
addiu a2, a2, 4
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
j ra
nop
END(jsimd_idct_12x12_pass1_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_idct_12x12_pass2_mips_dspr2)
/*
* a0 - workspace
* a1 - output
*/
SAVE_REGS_ON_STACK 16, s0, s1, s2, s3
li a3, 12
1:
// Odd part
lw t0, 12(a0)
lw t1, 4(a0)
lw t2, 20(a0)
lw t3, 28(a0)
li t4, 10703 // FIX(1.306562965)
li t5, 4433 // FIX_0_541196100
mul t4, t0, t4 // tmp11
mul t5, t0, t5 // -tmp14
addu t6, t1, t2 // tmp10
li t7, 2139 // FIX(0.261052384)
mul t7, t6, t7 // MULTIPLY(tmp10, FIX(0.261052384))
addu t6, t6, t3 // tmp10 + z4
li t8, 7053 // FIX(0.860918669)
mul t6, t6, t8 // tmp15
li t8, 2295 // FIX(0.280143716)
mul t8, t1, t8 // MULTIPLY(z1, FIX(0.280143716))
addu t9, t2, t3 // z3 + z4
li s0, 8565 // FIX(1.045510580)
mul t9, t9, s0 // -tmp13
li s0, 12112 // FIX(1.478575242)
mul s0, t2, s0 // MULTIPLY(z3, FIX(1.478575242))
li s1, 12998 // FIX(1.586706681)
mul s1, t3, s1 // MULTIPLY(z4, FIX(1.586706681))
li s2, 5540 // FIX(0.676326758)
mul s2, t1, s2 // MULTIPLY(z1, FIX(0.676326758))
li s3, 16244 // FIX(1.982889723)
mul s3, t3, s3 // MULTIPLY(z4, FIX(1.982889723))
subu t1, t1, t3 // z1 -= z4
subu t0, t0, t2 // z2 -= z3
addu t2, t1, t0 // z1 + z2
li t3, 4433 // FIX_0_541196100
mul t2, t2, t3 // z3
li t3, 6270 // FIX_0_765366865
mul t1, t1, t3 // MULTIPLY(z1, FIX_0_765366865)
li t3, 15137 // FIX_1_847759065
mul t0, t0, t3 // MULTIPLY(z2, FIX_1_847759065)
addu t3, t6, t7 // tmp12
addu t7, t3, t4
addu t7, t7, t8 // tmp10
subu t3, t3, t9
subu t3, t3, t5
subu t3, t3, s0 // tmp12
subu t9, t6, t9
subu t9, t9, t4
addu t9, t9, s1 // tmp13
subu t6, t6, t5
subu t6, t6, s2
subu t6, t6, s3 // tmp15
addu t1, t2, t1 // tmp11
subu t0, t2, t0 // tmp14
// even part
lw t2, 16(a0) // z4
lw t4, 8(a0) // z1
lw t5, 0(a0) // z3
lw t8, 24(a0) // z2
li s0, 10033 // FIX(1.224744871)
li s1, 11190 // FIX(1.366025404)
mul t2, t2, s0 // z4
mul s0, t4, s1 // z4
addiu t5, t5, 0x10
sll t5, t5, 13 // z3
sll t4, t4, 13 // z1
sll t8, t8, 13 // z2
subu s1, t4, t8 // tmp12
addu s2, t5, t2 // tmp10
subu t2, t5, t2 // tmp11
addu s3, t5, s1 // tmp21
subu s1, t5, s1 // tmp24
addu t5, s0, t8 // tmp12
addu v0, s2, t5 // tmp20
subu t5, s2, t5 // tmp25
subu t4, s0, t4
subu t4, t4, t8 // tmp12
addu t8, t2, t4 // tmp22
subu t2, t2, t4 // tmp23
// increment counter and pointers
addiu a3, a3, -1
addiu a0, a0, 32
// Final stage
addu t4, v0, t7
subu v0, v0, t7
addu t7, s3, t1
subu s3, s3, t1
addu t1, t8, t3
subu t8, t8, t3
addu t3, t2, t9
subu t2, t2, t9
addu t9, s1, t0
subu s1, s1, t0
addu t0, t5, t6
subu t5, t5, t6
sll t4, t4, 4
sll t7, t7, 4
sll t1, t1, 4
sll t3, t3, 4
sll t9, t9, 4
sll t0, t0, 4
sll t5, t5, 4
sll s1, s1, 4
sll t2, t2, 4
sll t8, t8, 4
sll s3, s3, 4
sll v0, v0, 4
shll_s.w t4, t4, 2
shll_s.w t7, t7, 2
shll_s.w t1, t1, 2
shll_s.w t3, t3, 2
shll_s.w t9, t9, 2
shll_s.w t0, t0, 2
shll_s.w t5, t5, 2
shll_s.w s1, s1, 2
shll_s.w t2, t2, 2
shll_s.w t8, t8, 2
shll_s.w s3, s3, 2
shll_s.w v0, v0, 2
srl t4, t4, 24
srl t7, t7, 24
srl t1, t1, 24
srl t3, t3, 24
srl t9, t9, 24
srl t0, t0, 24
srl t5, t5, 24
srl s1, s1, 24
srl t2, t2, 24
srl t8, t8, 24
srl s3, s3, 24
srl v0, v0, 24
lw t6, 0(a1)
addiu t4, t4, 0x80
addiu t7, t7, 0x80
addiu t1, t1, 0x80
addiu t3, t3, 0x80
addiu t9, t9, 0x80
addiu t0, t0, 0x80
addiu t5, t5, 0x80
addiu s1, s1, 0x80
addiu t2, t2, 0x80
addiu t8, t8, 0x80
addiu s3, s3, 0x80
addiu v0, v0, 0x80
sb t4, 0(t6)
sb t7, 1(t6)
sb t1, 2(t6)
sb t3, 3(t6)
sb t9, 4(t6)
sb t0, 5(t6)
sb t5, 6(t6)
sb s1, 7(t6)
sb t2, 8(t6)
sb t8, 9(t6)
sb s3, 10(t6)
sb v0, 11(t6)
bgtz a3, 1b
addiu a1, a1, 4
RESTORE_REGS_FROM_STACK 16, s0, s1, s2, s3
jr ra
nop
END(jsimd_idct_12x12_pass2_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_convsamp_mips_dspr2)
/*
* a0 - sample_data
* a1 - start_col
* a2 - workspace
*/
lw t0, 0(a0)
li t7, 0xff80ff80
addu t0, t0, a1
ulw t1, 0(t0)
ulw t2, 4(t0)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
lw t0, 4(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 0(a2)
usw t4, 4(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 8(a2)
usw t6, 12(a2)
lw t0, 8(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 16(a2)
usw t4, 20(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 24(a2)
usw t6, 28(a2)
lw t0, 12(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 32(a2)
usw t4, 36(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 40(a2)
usw t6, 44(a2)
lw t0, 16(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 48(a2)
usw t4, 52(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 56(a2)
usw t6, 60(a2)
lw t0, 20(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 64(a2)
usw t4, 68(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 72(a2)
usw t6, 76(a2)
lw t0, 24(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 80(a2)
usw t4, 84(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 88(a2)
usw t6, 92(a2)
lw t0, 28(a0)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu t0, t0, a1
addu.ph t3, t3, t7
addu.ph t4, t4, t7
ulw t1, 0(t0)
ulw t2, 4(t0)
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 96(a2)
usw t4, 100(a2)
preceu.ph.qbr t3, t1
preceu.ph.qbl t4, t1
usw t5, 104(a2)
usw t6, 108(a2)
preceu.ph.qbr t5, t2
preceu.ph.qbl t6, t2
addu.ph t3, t3, t7
addu.ph t4, t4, t7
addu.ph t5, t5, t7
addu.ph t6, t6, t7
usw t3, 112(a2)
usw t4, 116(a2)
usw t5, 120(a2)
usw t6, 124(a2)
j ra
nop
END(jsimd_convsamp_mips_dspr2)
/*****************************************************************************/
LEAF_MIPS_DSPR2(jsimd_convsamp_float_mips_dspr2)
/*
* a0 - sample_data
* a1 - start_col
* a2 - workspace
*/
.set at
lw t0, 0(a0)
addu t0, t0, a1
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 4(a0)
swc1 f2, 0(a2)
swc1 f4, 4(a2)
swc1 f6, 8(a2)
addu t0, t0, a1
swc1 f8, 12(a2)
swc1 f10, 16(a2)
swc1 f12, 20(a2)
swc1 f14, 24(a2)
swc1 f16, 28(a2)
//elemr 1
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 8(a0)
swc1 f2, 32(a2)
swc1 f4, 36(a2)
swc1 f6, 40(a2)
addu t0, t0, a1
swc1 f8, 44(a2)
swc1 f10, 48(a2)
swc1 f12, 52(a2)
swc1 f14, 56(a2)
swc1 f16, 60(a2)
//elemr 2
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 12(a0)
swc1 f2, 64(a2)
swc1 f4, 68(a2)
swc1 f6, 72(a2)
addu t0, t0, a1
swc1 f8, 76(a2)
swc1 f10, 80(a2)
swc1 f12, 84(a2)
swc1 f14, 88(a2)
swc1 f16, 92(a2)
//elemr 3
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 16(a0)
swc1 f2, 96(a2)
swc1 f4, 100(a2)
swc1 f6, 104(a2)
addu t0, t0, a1
swc1 f8, 108(a2)
swc1 f10, 112(a2)
swc1 f12, 116(a2)
swc1 f14, 120(a2)
swc1 f16, 124(a2)
//elemr 4
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 20(a0)
swc1 f2, 128(a2)
swc1 f4, 132(a2)
swc1 f6, 136(a2)
addu t0, t0, a1
swc1 f8, 140(a2)
swc1 f10, 144(a2)
swc1 f12, 148(a2)
swc1 f14, 152(a2)
swc1 f16, 156(a2)
//elemr 5
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 24(a0)
swc1 f2, 160(a2)
swc1 f4, 164(a2)
swc1 f6, 168(a2)
addu t0, t0, a1
swc1 f8, 172(a2)
swc1 f10, 176(a2)
swc1 f12, 180(a2)
swc1 f14, 184(a2)
swc1 f16, 188(a2)
//elemr 6
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
lw t0, 28(a0)
swc1 f2, 192(a2)
swc1 f4, 196(a2)
swc1 f6, 200(a2)
addu t0, t0, a1
swc1 f8, 204(a2)
swc1 f10, 208(a2)
swc1 f12, 212(a2)
swc1 f14, 216(a2)
swc1 f16, 220(a2)
//elemr 7
lbu t1, 0(t0)
lbu t2, 1(t0)
lbu t3, 2(t0)
lbu t4, 3(t0)
lbu t5, 4(t0)
lbu t6, 5(t0)
lbu t7, 6(t0)
lbu t8, 7(t0)
addiu t1, t1, -128
addiu t2, t2, -128
addiu t3, t3, -128
addiu t4, t4, -128
addiu t5, t5, -128
addiu t6, t6, -128
addiu t7, t7, -128
addiu t8, t8, -128
mtc1 t1, f2
mtc1 t2, f4
mtc1 t3, f6
mtc1 t4, f8
mtc1 t5, f10
mtc1 t6, f12
mtc1 t7, f14
mtc1 t8, f16
cvt.s.w f2, f2
cvt.s.w f4, f4
cvt.s.w f6, f6
cvt.s.w f8, f8
cvt.s.w f10, f10
cvt.s.w f12, f12
cvt.s.w f14, f14
cvt.s.w f16, f16
swc1 f2, 224(a2)
swc1 f4, 228(a2)
swc1 f6, 232(a2)
swc1 f8, 236(a2)
swc1 f10, 240(a2)
swc1 f12, 244(a2)
swc1 f14, 248(a2)
swc1 f16, 252(a2)
j ra
nop
END(jsimd_convsamp_float_mips_dspr2)
/*****************************************************************************/
|
AKNoryx28/zygisk-imgui-modmenu
| 1,077
|
module/src/main/cpp/Dobby/source/TrampolineBridge/ClosureTrampolineBridge/arm/dummy/closure-trampoline-template-arm.S
|
// .section __TEXT,__text,regular,pure_instructions
#if defined(ENABLE_CLOSURE_BRIDGE_TEMPLATE)
#if defined(__WIN32__) || defined(__APPLE__)
#define cdecl(s) _##s
#else
#define cdecl(s) s
#endif
.align 4
#if !defined(ENABLE_CLOSURE_TRAMPOLINE_CARRY_OBJECT_PTR)
// closure trampoline carray the object pointer, and fetch required members at the runtime assembly code.
// #include "TrampolineBridge/ClosureTrampolineBridge/ClosureTrampoline.h"
// #define OFFSETOF(TYPE, ELEMENT) ((size_t)&(((TYPE *)0)->ELEMENT))
#define OFFSETOF_ClourseTrampolineEntry_carry_data 4
#define OFFSETOF_ClourseTrampolineEntry_carry_handler 0
.globl cdecl(closure_trampoline_template)
cdecl(closure_trampoline_template):
ldr r12, ClourseTrampolineEntryPtr
ldr pc, [r12, #0]
ClourseTrampolineEntryPtr:
.long 0
#else
; closure trampoline just carray the required members from the object.
.globl cdecl(closure_trampoline_template)
cdecl(closure_trampoline_template):
ldr r12, =carry_data
ldr pc, =carry_handler
carry_data:
.long 0
carry_handler:
.long 0
#endif
#endif
|
AKNoryx28/zygisk-imgui-modmenu
| 1,230
|
module/src/main/cpp/Dobby/source/TrampolineBridge/ClosureTrampolineBridge/arm64/dummy/closure-trampoline-template-arm64.S
|
// .section __TEXT,__text,regular,pure_instructions
#if defined(ENABLE_CLOSURE_BRIDGE_TEMPLATE)
#if defined(__WIN32__) || defined(__APPLE__)
#define cdecl(s) _##s
#else
#define cdecl(s) s
#endif
.align 4
#if !defined(ENABLE_CLOSURE_TRAMPOLINE_CARRY_OBJECT_PTR)
// closure trampoline carray the object pointer, and fetch required members at the runtime assembly code.
// #include "TrampolineBridge/ClosureTrampolineBridge/ClosureTrampoline.h"
// #define OFFSETOF(TYPE, ELEMENT) ((size_t)&(((TYPE *)0)->ELEMENT))
#define OFFSETOF_ClourseTrampolineEntry_carry_data 8
#define OFFSETOF_ClourseTrampolineEntry_carry_handler 0
.globl cdecl(closure_trampoline_template)
cdecl(closure_trampoline_template):
ldr x17, ClourseTrampolineEntryPtr
ldr x16, OFFSETOF_ClourseTrampolineEntry_carry_data
ldr x17, OFFSETOF_ClourseTrampolineEntry_carry_handler
br x17
ClourseTrampolineEntryPtr:
.long 0
.long 0
#else
; closure trampoline just carray the required members from the object.
.globl cdecl(closure_trampoline_template)
cdecl(closure_trampoline_template):
ldr x16, =carry_data
ldr x17, =carry_handler
br x17
carry_data:
.long 0
.long 0
carry_handler:
.long 0
.long 0
#endif
#endif
|
akospasztor/stm32-dma-uart
| 22,177
|
EWARM/startup_stm32l476xx.s
|
;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
;* File Name : startup_stm32l476xx.s
;* Author : MCD Application Team
;* Version : V1.3.0
;* Date : 17-February-2017
;* Description : STM32L476xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
akospasztor/stm32-bootloader
| 23,919
|
projects/STM32L496-Discovery/EWARM/startup_stm32l496xx.s
|
;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
akospasztor/stm32-bootloader
| 14,391
|
projects/STM32L496-Discovery/GCC/startup_stm32l496xx.s
|
/**
******************************************************************************
* @file startup_stm32l496xx.s
* @author MCD Application Team
* @brief STM32L496xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word DFSDM1_FLT3_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word SDMMC1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word DFSDM1_FLT0_IRQHandler
.word DFSDM1_FLT1_IRQHandler
.word DFSDM1_FLT2_IRQHandler
.word COMP_IRQHandler
.word LPTIM1_IRQHandler
.word LPTIM2_IRQHandler
.word OTG_FS_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word LPUART1_IRQHandler
.word QUADSPI_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SAI1_IRQHandler
.word SAI2_IRQHandler
.word SWPMI1_IRQHandler
.word TSC_IRQHandler
.word LCD_IRQHandler
.word 0
.word RNG_IRQHandler
.word FPU_IRQHandler
.word CRS_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word DCMI_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word DMA2D_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
akospasztor/stm32-bootloader
| 23,919
|
projects/STM32L496-CustomHw/EWARM/startup_stm32l496xx.s
|
;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
;* File Name : startup_stm32l496xx.s
;* Author : MCD Application Team
;* Description : STM32L496xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
DCD CRS_IRQHandler ; CRS error
DCD I2C4_EV_IRQHandler ; I2C4 event
DCD I2C4_ER_IRQHandler ; I2C4 error
DCD DCMI_IRQHandler ; DCMI global interrupt
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD DMA2D_IRQHandler ; DMA2D global interrupt
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK CRS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CRS_IRQHandler
B CRS_IRQHandler
PUBWEAK I2C4_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_EV_IRQHandler
B I2C4_EV_IRQHandler
PUBWEAK I2C4_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C4_ER_IRQHandler
B I2C4_ER_IRQHandler
PUBWEAK DCMI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DCMI_IRQHandler
B DCMI_IRQHandler
PUBWEAK CAN2_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_TX_IRQHandler
B CAN2_TX_IRQHandler
PUBWEAK CAN2_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX0_IRQHandler
B CAN2_RX0_IRQHandler
PUBWEAK CAN2_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_RX1_IRQHandler
B CAN2_RX1_IRQHandler
PUBWEAK CAN2_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN2_SCE_IRQHandler
B CAN2_SCE_IRQHandler
PUBWEAK DMA2D_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2D_IRQHandler
B DMA2D_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
akospasztor/stm32-bootloader
| 22,105
|
projects/STM32L476-CustomHw/EWARM/startup_stm32l476xx.s
|
;/********************* COPYRIGHT(c) 2017 STMicroelectronics ********************
;* File Name : startup_stm32l476xx.s
;* Author : MCD Application Team
;* Description : STM32L476xx Ultra Low Power Devices vector
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == _iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address.
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;********************************************************************************
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_PVM_IRQHandler ; PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1, ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD DFSDM1_FLT3_IRQHandler ; DFSDM1 Filter 3 global Interrupt
DCD TIM8_BRK_IRQHandler ; TIM8 Break Interrupt
DCD TIM8_UP_IRQHandler ; TIM8 Update Interrupt
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation Interrupt
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
DCD ADC3_IRQHandler ; ADC3 global Interrupt
DCD FMC_IRQHandler ; FMC
DCD SDMMC1_IRQHandler ; SDMMC1
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global Interrupt
DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global Interrupt
DCD DFSDM1_FLT2_IRQHandler ; DFSDM1 Filter 2 global Interrupt
DCD COMP_IRQHandler ; COMP Interrupt
DCD LPTIM1_IRQHandler ; LP TIM1 interrupt
DCD LPTIM2_IRQHandler ; LP TIM2 interrupt
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Channel6_IRQHandler ; DMA2 Channel 6
DCD DMA2_Channel7_IRQHandler ; DMA2 Channel 7
DCD LPUART1_IRQHandler ; LP UART 1 interrupt
DCD QUADSPI_IRQHandler ; Quad SPI global interrupt
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt
DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt
DCD SWPMI1_IRQHandler ; Serial Wire Interface global interrupt
DCD TSC_IRQHandler ; Touch Sense Controller global interrupt
DCD LCD_IRQHandler ; LCD global interrupt
DCD 0 ; Reserved
DCD RNG_IRQHandler ; RNG global interrupt
DCD FPU_IRQHandler ; FPU
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_PVM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_PVM_IRQHandler
B PVD_PVM_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_IRQHandler
B DMA1_Channel2_IRQHandler
PUBWEAK DMA1_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel3_IRQHandler
B DMA1_Channel3_IRQHandler
PUBWEAK DMA1_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_IRQHandler
B DMA1_Channel4_IRQHandler
PUBWEAK DMA1_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel5_IRQHandler
B DMA1_Channel5_IRQHandler
PUBWEAK DMA1_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel6_IRQHandler
B DMA1_Channel6_IRQHandler
PUBWEAK DMA1_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel7_IRQHandler
B DMA1_Channel7_IRQHandler
PUBWEAK ADC1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_2_IRQHandler
B ADC1_2_IRQHandler
PUBWEAK CAN1_TX_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_TX_IRQHandler
B CAN1_TX_IRQHandler
PUBWEAK CAN1_RX0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX0_IRQHandler
B CAN1_RX0_IRQHandler
PUBWEAK CAN1_RX1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_RX1_IRQHandler
B CAN1_RX1_IRQHandler
PUBWEAK CAN1_SCE_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
CAN1_SCE_IRQHandler
B CAN1_SCE_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_TIM15_IRQHandler
B TIM1_BRK_TIM15_IRQHandler
PUBWEAK TIM1_UP_TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_UP_TIM16_IRQHandler
B TIM1_UP_TIM16_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_TRG_COM_TIM17_IRQHandler
B TIM1_TRG_COM_TIM17_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK USART3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART3_IRQHandler
B USART3_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK DFSDM1_FLT3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT3_IRQHandler
B DFSDM1_FLT3_IRQHandler
PUBWEAK TIM8_BRK_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_BRK_IRQHandler
B TIM8_BRK_IRQHandler
PUBWEAK TIM8_UP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_UP_IRQHandler
B TIM8_UP_IRQHandler
PUBWEAK TIM8_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_TRG_COM_IRQHandler
B TIM8_TRG_COM_IRQHandler
PUBWEAK TIM8_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM8_CC_IRQHandler
B TIM8_CC_IRQHandler
PUBWEAK ADC3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC3_IRQHandler
B ADC3_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK SDMMC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SDMMC1_IRQHandler
B SDMMC1_IRQHandler
PUBWEAK TIM5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK UART4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART4_IRQHandler
B UART4_IRQHandler
PUBWEAK UART5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
UART5_IRQHandler
B UART5_IRQHandler
PUBWEAK TIM6_DAC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM6_DAC_IRQHandler
B TIM6_DAC_IRQHandler
PUBWEAK TIM7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM7_IRQHandler
B TIM7_IRQHandler
PUBWEAK DMA2_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel1_IRQHandler
B DMA2_Channel1_IRQHandler
PUBWEAK DMA2_Channel2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel2_IRQHandler
B DMA2_Channel2_IRQHandler
PUBWEAK DMA2_Channel3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel3_IRQHandler
B DMA2_Channel3_IRQHandler
PUBWEAK DMA2_Channel4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel4_IRQHandler
B DMA2_Channel4_IRQHandler
PUBWEAK DMA2_Channel5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel5_IRQHandler
B DMA2_Channel5_IRQHandler
PUBWEAK DFSDM1_FLT0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT0_IRQHandler
B DFSDM1_FLT0_IRQHandler
PUBWEAK DFSDM1_FLT1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT1_IRQHandler
B DFSDM1_FLT1_IRQHandler
PUBWEAK DFSDM1_FLT2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DFSDM1_FLT2_IRQHandler
B DFSDM1_FLT2_IRQHandler
PUBWEAK COMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
COMP_IRQHandler
B COMP_IRQHandler
PUBWEAK LPTIM1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM1_IRQHandler
B LPTIM1_IRQHandler
PUBWEAK LPTIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPTIM2_IRQHandler
B LPTIM2_IRQHandler
PUBWEAK OTG_FS_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Channel6_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel6_IRQHandler
B DMA2_Channel6_IRQHandler
PUBWEAK DMA2_Channel7_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA2_Channel7_IRQHandler
B DMA2_Channel7_IRQHandler
PUBWEAK LPUART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LPUART1_IRQHandler
B LPUART1_IRQHandler
PUBWEAK QUADSPI_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
QUADSPI_IRQHandler
B QUADSPI_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK SAI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI1_IRQHandler
B SAI1_IRQHandler
PUBWEAK SAI2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SAI2_IRQHandler
B SAI2_IRQHandler
PUBWEAK SWPMI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SWPMI1_IRQHandler
B SWPMI1_IRQHandler
PUBWEAK TSC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TSC_IRQHandler
B TSC_IRQHandler
PUBWEAK LCD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LCD_IRQHandler
B LCD_IRQHandler
PUBWEAK RNG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RNG_IRQHandler
B RNG_IRQHandler
PUBWEAK FPU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FPU_IRQHandler
B FPU_IRQHandler
END
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
akospasztor/stm32-project-template
| 14,197
|
mcal/st-stm32l4/gcc-arm/startup_stm32l496xx.s
|
/**
******************************************************************************
* @file startup_stm32l496xx.s
* @author MCD Application Team
* @brief STM32L496xx devices vector table GCC toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address,
* - Configure the clock system
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M4 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* Set stack pointer */
/* Call the clock system initialization function.*/
bl SystemInit
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
ldr r1, =_edata
ldr r2, =_sidata
movs r3, #0
b LoopCopyDataInit
CopyDataInit:
ldr r4, [r2, r3]
str r4, [r0, r3]
adds r3, r3, #4
LoopCopyDataInit:
adds r4, r0, r3
cmp r4, r1
bcc CopyDataInit
/* Zero fill the bss segment. */
ldr r2, =_sbss
ldr r4, =_ebss
movs r3, #0
b LoopFillZerobss
FillZerobss:
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
cmp r2, r4
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex-M4. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_PVM_IRQHandler
.word TAMP_STAMP_IRQHandler
.word RTC_WKUP_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word CAN1_TX_IRQHandler
.word CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_TIM15_IRQHandler
.word TIM1_UP_TIM16_IRQHandler
.word TIM1_TRG_COM_TIM17_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word TIM4_IRQHandler
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word I2C2_EV_IRQHandler
.word I2C2_ER_IRQHandler
.word SPI1_IRQHandler
.word SPI2_IRQHandler
.word USART1_IRQHandler
.word USART2_IRQHandler
.word USART3_IRQHandler
.word EXTI15_10_IRQHandler
.word RTC_Alarm_IRQHandler
.word DFSDM1_FLT3_IRQHandler
.word TIM8_BRK_IRQHandler
.word TIM8_UP_IRQHandler
.word TIM8_TRG_COM_IRQHandler
.word TIM8_CC_IRQHandler
.word ADC3_IRQHandler
.word FMC_IRQHandler
.word SDMMC1_IRQHandler
.word TIM5_IRQHandler
.word SPI3_IRQHandler
.word UART4_IRQHandler
.word UART5_IRQHandler
.word TIM6_DAC_IRQHandler
.word TIM7_IRQHandler
.word DMA2_Channel1_IRQHandler
.word DMA2_Channel2_IRQHandler
.word DMA2_Channel3_IRQHandler
.word DMA2_Channel4_IRQHandler
.word DMA2_Channel5_IRQHandler
.word DFSDM1_FLT0_IRQHandler
.word DFSDM1_FLT1_IRQHandler
.word DFSDM1_FLT2_IRQHandler
.word COMP_IRQHandler
.word LPTIM1_IRQHandler
.word LPTIM2_IRQHandler
.word OTG_FS_IRQHandler
.word DMA2_Channel6_IRQHandler
.word DMA2_Channel7_IRQHandler
.word LPUART1_IRQHandler
.word QUADSPI_IRQHandler
.word I2C3_EV_IRQHandler
.word I2C3_ER_IRQHandler
.word SAI1_IRQHandler
.word SAI2_IRQHandler
.word SWPMI1_IRQHandler
.word TSC_IRQHandler
.word LCD_IRQHandler
.word 0
.word RNG_IRQHandler
.word FPU_IRQHandler
.word CRS_IRQHandler
.word I2C4_EV_IRQHandler
.word I2C4_ER_IRQHandler
.word DCMI_IRQHandler
.word CAN2_TX_IRQHandler
.word CAN2_RX0_IRQHandler
.word CAN2_RX1_IRQHandler
.word CAN2_SCE_IRQHandler
.word DMA2D_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_PVM_IRQHandler
.thumb_set PVD_PVM_IRQHandler,Default_Handler
.weak TAMP_STAMP_IRQHandler
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
.weak RTC_WKUP_IRQHandler
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_IRQHandler
.thumb_set EXTI0_IRQHandler,Default_Handler
.weak EXTI1_IRQHandler
.thumb_set EXTI1_IRQHandler,Default_Handler
.weak EXTI2_IRQHandler
.thumb_set EXTI2_IRQHandler,Default_Handler
.weak EXTI3_IRQHandler
.thumb_set EXTI3_IRQHandler,Default_Handler
.weak EXTI4_IRQHandler
.thumb_set EXTI4_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_IRQHandler
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
.weak DMA1_Channel3_IRQHandler
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
.weak DMA1_Channel4_IRQHandler
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
.weak DMA1_Channel5_IRQHandler
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
.weak DMA1_Channel6_IRQHandler
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
.weak DMA1_Channel7_IRQHandler
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
.weak ADC1_2_IRQHandler
.thumb_set ADC1_2_IRQHandler,Default_Handler
.weak CAN1_TX_IRQHandler
.thumb_set CAN1_TX_IRQHandler,Default_Handler
.weak CAN1_RX0_IRQHandler
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
.weak CAN1_RX1_IRQHandler
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
.weak CAN1_SCE_IRQHandler
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
.weak EXTI9_5_IRQHandler
.thumb_set EXTI9_5_IRQHandler,Default_Handler
.weak TIM1_BRK_TIM15_IRQHandler
.thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
.weak TIM1_UP_TIM16_IRQHandler
.thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
.weak TIM1_TRG_COM_TIM17_IRQHandler
.thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM4_IRQHandler
.thumb_set TIM4_IRQHandler,Default_Handler
.weak I2C1_EV_IRQHandler
.thumb_set I2C1_EV_IRQHandler,Default_Handler
.weak I2C1_ER_IRQHandler
.thumb_set I2C1_ER_IRQHandler,Default_Handler
.weak I2C2_EV_IRQHandler
.thumb_set I2C2_EV_IRQHandler,Default_Handler
.weak I2C2_ER_IRQHandler
.thumb_set I2C2_ER_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
.weak USART2_IRQHandler
.thumb_set USART2_IRQHandler,Default_Handler
.weak USART3_IRQHandler
.thumb_set USART3_IRQHandler,Default_Handler
.weak EXTI15_10_IRQHandler
.thumb_set EXTI15_10_IRQHandler,Default_Handler
.weak RTC_Alarm_IRQHandler
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
.weak DFSDM1_FLT3_IRQHandler
.thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
.weak TIM8_BRK_IRQHandler
.thumb_set TIM8_BRK_IRQHandler,Default_Handler
.weak TIM8_UP_IRQHandler
.thumb_set TIM8_UP_IRQHandler,Default_Handler
.weak TIM8_TRG_COM_IRQHandler
.thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
.weak TIM8_CC_IRQHandler
.thumb_set TIM8_CC_IRQHandler,Default_Handler
.weak ADC3_IRQHandler
.thumb_set ADC3_IRQHandler,Default_Handler
.weak FMC_IRQHandler
.thumb_set FMC_IRQHandler,Default_Handler
.weak SDMMC1_IRQHandler
.thumb_set SDMMC1_IRQHandler,Default_Handler
.weak TIM5_IRQHandler
.thumb_set TIM5_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak TIM6_DAC_IRQHandler
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
.weak TIM7_IRQHandler
.thumb_set TIM7_IRQHandler,Default_Handler
.weak DMA2_Channel1_IRQHandler
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
.weak DMA2_Channel2_IRQHandler
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
.weak DMA2_Channel3_IRQHandler
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
.weak DMA2_Channel4_IRQHandler
.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
.weak DMA2_Channel5_IRQHandler
.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
.weak DFSDM1_FLT0_IRQHandler
.thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
.weak DFSDM1_FLT1_IRQHandler
.thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
.weak DFSDM1_FLT2_IRQHandler
.thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
.weak COMP_IRQHandler
.thumb_set COMP_IRQHandler,Default_Handler
.weak LPTIM1_IRQHandler
.thumb_set LPTIM1_IRQHandler,Default_Handler
.weak LPTIM2_IRQHandler
.thumb_set LPTIM2_IRQHandler,Default_Handler
.weak OTG_FS_IRQHandler
.thumb_set OTG_FS_IRQHandler,Default_Handler
.weak DMA2_Channel6_IRQHandler
.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
.weak DMA2_Channel7_IRQHandler
.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
.weak LPUART1_IRQHandler
.thumb_set LPUART1_IRQHandler,Default_Handler
.weak QUADSPI_IRQHandler
.thumb_set QUADSPI_IRQHandler,Default_Handler
.weak I2C3_EV_IRQHandler
.thumb_set I2C3_EV_IRQHandler,Default_Handler
.weak I2C3_ER_IRQHandler
.thumb_set I2C3_ER_IRQHandler,Default_Handler
.weak SAI1_IRQHandler
.thumb_set SAI1_IRQHandler,Default_Handler
.weak SAI2_IRQHandler
.thumb_set SAI2_IRQHandler,Default_Handler
.weak SWPMI1_IRQHandler
.thumb_set SWPMI1_IRQHandler,Default_Handler
.weak TSC_IRQHandler
.thumb_set TSC_IRQHandler,Default_Handler
.weak LCD_IRQHandler
.thumb_set LCD_IRQHandler,Default_Handler
.weak RNG_IRQHandler
.thumb_set RNG_IRQHandler,Default_Handler
.weak FPU_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
.weak CRS_IRQHandler
.thumb_set CRS_IRQHandler,Default_Handler
.weak I2C4_EV_IRQHandler
.thumb_set I2C4_EV_IRQHandler,Default_Handler
.weak I2C4_ER_IRQHandler
.thumb_set I2C4_ER_IRQHandler,Default_Handler
.weak DCMI_IRQHandler
.thumb_set DCMI_IRQHandler,Default_Handler
.weak CAN2_TX_IRQHandler
.thumb_set CAN2_TX_IRQHandler,Default_Handler
.weak CAN2_RX0_IRQHandler
.thumb_set CAN2_RX0_IRQHandler,Default_Handler
.weak CAN2_RX1_IRQHandler
.thumb_set CAN2_RX1_IRQHandler,Default_Handler
.weak CAN2_SCE_IRQHandler
.thumb_set CAN2_SCE_IRQHandler,Default_Handler
.weak DMA2D_IRQHandler
.thumb_set FPU_IRQHandler,Default_Handler
|
akpc806a/CAN_Logger
| 3,483
|
Firmware/IAR/os/ports/RVCT/ARMCMx/chcoreasm_v7m.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/*
* Imports the Cortex-Mx configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
CONTEXT_OFFSET EQU 12
SCB_ICSR EQU 0xE000ED04
ICSR_PENDSVSET EQU 0x10000000
PRESERVE8
THUMB
AREA |.text|, CODE, READONLY
IMPORT chThdExit
IMPORT chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
IMPORT dbg_check_unlock
IMPORT dbg_check_lock
#endif
/*
* Performs a context switch between two threads.
*/
EXPORT _port_switch
_port_switch PROC
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
vpush {s16-s31}
#endif
str sp, [r1, #CONTEXT_OFFSET]
ldr sp, [r0, #CONTEXT_OFFSET]
#if CORTEX_USE_FPU
vpop {s16-s31}
#endif
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
ENDP
/*
* Start a thread by invoking its work function.
* If the work function returns @p chThdExit() is automatically invoked.
*/
EXPORT _port_thread_start
_port_thread_start PROC
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
movs r3, #CORTEX_BASEPRI_DISABLED
msr BASEPRI, r3
#endif
mov r0, r5
blx r4
bl chThdExit
ENDP
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
EXPORT _port_switch_from_isr
EXPORT _port_exit_from_isr
_port_switch_from_isr PROC
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
_port_exit_from_isr
#if CORTEX_SIMPLIFIED_PRIORITY
mov r3, #SCB_ICSR :AND: 0xFFFF
movt r3, #SCB_ICSR :SHR: 16
mov r2, #ICSR_PENDSVSET
str r2, [r3, #0]
cpsie i
waithere b waithere
#else
svc #0
#endif
ENDP
END
|
akpc806a/CAN_Logger
| 3,537
|
Firmware/IAR/os/ports/RVCT/ARMCMx/chcoreasm_v6m.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/*
* Imports the Cortex-Mx configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
CONTEXT_OFFSET EQU 12
SCB_ICSR EQU 0xE000ED04
PRESERVE8
THUMB
AREA |.text|, CODE, READONLY
IMPORT chThdExit
IMPORT chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
IMPORT dbg_check_unlock
IMPORT dbg_check_lock
#endif
/*
* Performs a context switch between two threads.
*/
EXPORT _port_switch
_port_switch PROC
push {r4, r5, r6, r7, lr}
mov r4, r8
mov r5, r9
mov r6, r10
mov r7, r11
push {r4, r5, r6, r7}
mov r3, sp
str r3, [r1, #CONTEXT_OFFSET]
ldr r3, [r0, #CONTEXT_OFFSET]
mov sp, r3
pop {r4, r5, r6, r7}
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
pop {r4, r5, r6, r7, pc}
ENDP
/*
* Start a thread by invoking its work function.
* If the work function returns @p chThdExit() is automatically invoked.
*/
EXPORT _port_thread_start
_port_thread_start PROC
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
cpsie i
mov r0, r5
blx r4
bl chThdExit
ENDP
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
EXPORT _port_switch_from_isr
EXPORT _port_exit_from_isr
_port_switch_from_isr PROC
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
_port_exit_from_isr
ldr r2, =SCB_ICSR
movs r3, #128
#if CORTEX_ALTERNATE_SWITCH
lsls r3, r3, #21
str r3, [r2, #0]
cpsie i
#else
lsls r3, r3, #24
str r3, [r2, #0]
#endif
waithere b waithere
ENDP
END
|
akpc806a/CAN_Logger
| 3,898
|
Firmware/IAR/os/ports/RVCT/ARMCMx/cstartup.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;// <h> Main Stack Configuration (IRQ Stack)
;// <o> Main Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>
main_stack_size EQU 0x00000400
;// <h> Process Stack Configuration
;// <o> Process Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>
proc_stack_size EQU 0x00000400
;// <h> C-runtime heap size
;// <o> C-runtime heap size (in Bytes) <0x0-0xFFFFFFFF:8>
;// </h>
heap_size EQU 0x00000400
AREA MSTACK, NOINIT, READWRITE, ALIGN=3
main_stack_mem SPACE main_stack_size
EXPORT __initial_msp
__initial_msp
AREA CSTACK, NOINIT, READWRITE, ALIGN=3
__main_thread_stack_base__
EXPORT __main_thread_stack_base__
proc_stack_mem SPACE proc_stack_size
EXPORT __initial_sp
__initial_sp
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE heap_size
__heap_limit
CONTROL_MODE_PRIVILEGED EQU 0
CONTROL_MODE_UNPRIVILEGED EQU 1
CONTROL_USE_MSP EQU 0
CONTROL_USE_PSP EQU 2
PRESERVE8
THUMB
AREA |.text|, CODE, READONLY
/*
* Reset handler.
*/
IMPORT __main
EXPORT Reset_Handler
Reset_Handler PROC
cpsid i
ldr r0, =__initial_sp
msr PSP, r0
movs r0, #CONTROL_MODE_PRIVILEGED :OR: CONTROL_USE_PSP
msr CONTROL, r0
isb
bl __early_init
IF {CPU} = "Cortex-M4.fp"
LDR R0, =0xE000ED88 ; Enable CP10,CP11
LDR R1, [R0]
ORR R1, R1, #(0xF << 20)
STR R1, [R0]
ENDIF
ldr r0, =__main
bx r0
ENDP
__early_init PROC
EXPORT __early_init [WEAK]
bx lr
ENDP
ALIGN
/*
* User Initial Stack & Heap.
*/
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
ldr r0, =Heap_Mem
ldr r1, =(proc_stack_mem + proc_stack_size)
ldr r2, =(Heap_Mem + heap_size)
ldr r3, =proc_stack_mem
bx lr
ALIGN
ENDIF
END
|
akpc806a/CAN_Logger
| 7,592
|
Firmware/IAR/os/ports/RVCT/ARMCMx/STM32L1xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32L1XX_MD)
#define _FROM_ASM_
#include "board.h"
#endif
PRESERVE8
AREA RESET, DATA, READONLY
IMPORT __initial_msp
IMPORT Reset_Handler
EXPORT __Vectors
__Vectors
DCD __initial_msp
DCD Reset_Handler
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
AREA |.text|, CODE, READONLY
THUMB
/*
* Default interrupt handlers.
*/
EXPORT _unhandled_exception
_unhandled_exception PROC
EXPORT NMIVector [WEAK]
EXPORT HardFaultVector [WEAK]
EXPORT MemManageVector [WEAK]
EXPORT BusFaultVector [WEAK]
EXPORT UsageFaultVector [WEAK]
EXPORT Vector1C [WEAK]
EXPORT Vector20 [WEAK]
EXPORT Vector24 [WEAK]
EXPORT Vector28 [WEAK]
EXPORT SVCallVector [WEAK]
EXPORT DebugMonitorVector [WEAK]
EXPORT Vector34 [WEAK]
EXPORT PendSVVector [WEAK]
EXPORT SysTickVector [WEAK]
EXPORT Vector40 [WEAK]
EXPORT Vector44 [WEAK]
EXPORT Vector48 [WEAK]
EXPORT Vector4C [WEAK]
EXPORT Vector50 [WEAK]
EXPORT Vector54 [WEAK]
EXPORT Vector58 [WEAK]
EXPORT Vector5C [WEAK]
EXPORT Vector60 [WEAK]
EXPORT Vector64 [WEAK]
EXPORT Vector68 [WEAK]
EXPORT Vector6C [WEAK]
EXPORT Vector70 [WEAK]
EXPORT Vector74 [WEAK]
EXPORT Vector78 [WEAK]
EXPORT Vector7C [WEAK]
EXPORT Vector80 [WEAK]
EXPORT Vector84 [WEAK]
EXPORT Vector88 [WEAK]
EXPORT Vector8C [WEAK]
EXPORT Vector90 [WEAK]
EXPORT Vector94 [WEAK]
EXPORT Vector98 [WEAK]
EXPORT Vector9C [WEAK]
EXPORT VectorA0 [WEAK]
EXPORT VectorA4 [WEAK]
EXPORT VectorA8 [WEAK]
EXPORT VectorAC [WEAK]
EXPORT VectorB0 [WEAK]
EXPORT VectorB4 [WEAK]
EXPORT VectorB8 [WEAK]
EXPORT VectorBC [WEAK]
EXPORT VectorC0 [WEAK]
EXPORT VectorC4 [WEAK]
EXPORT VectorC8 [WEAK]
EXPORT VectorCC [WEAK]
EXPORT VectorD0 [WEAK]
EXPORT VectorD4 [WEAK]
EXPORT VectorD8 [WEAK]
EXPORT VectorDC [WEAK]
EXPORT VectorE0 [WEAK]
EXPORT VectorE4 [WEAK]
EXPORT VectorE8 [WEAK]
EXPORT VectorEC [WEAK]
EXPORT VectorF0 [WEAK]
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
b _unhandled_exception
ENDP
END
|
akpc806a/CAN_Logger
| 10,355
|
Firmware/IAR/os/ports/RVCT/ARMCMx/STM32F1xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \
!defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \
!defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \
!defined(STM32F10X_CL)
#define _FROM_ASM_
#include "board.h"
#endif
PRESERVE8
AREA RESET, DATA, READONLY
IMPORT __initial_msp
IMPORT Reset_Handler
EXPORT __Vectors
__Vectors
DCD __initial_msp
DCD Reset_Handler
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
defined(STM32F10X_XL) || defined(STM32F10X_CL)
DCD VectorEC
DCD VectorF0
DCD VectorF4
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
DCD Vector128
DCD Vector12C
#endif
#if defined(STM32F10X_CL)
DCD Vector130
DCD Vector134
DCD Vector138
DCD Vector13C
DCD Vector140
DCD Vector144
DCD Vector148
DCD Vector14C
#endif
AREA |.text|, CODE, READONLY
THUMB
/*
* Default interrupt handlers.
*/
EXPORT _unhandled_exception
_unhandled_exception PROC
EXPORT NMIVector [WEAK]
EXPORT HardFaultVector [WEAK]
EXPORT MemManageVector [WEAK]
EXPORT BusFaultVector [WEAK]
EXPORT UsageFaultVector [WEAK]
EXPORT Vector1C [WEAK]
EXPORT Vector20 [WEAK]
EXPORT Vector24 [WEAK]
EXPORT Vector28 [WEAK]
EXPORT SVCallVector [WEAK]
EXPORT DebugMonitorVector [WEAK]
EXPORT Vector34 [WEAK]
EXPORT PendSVVector [WEAK]
EXPORT SysTickVector [WEAK]
EXPORT Vector40 [WEAK]
EXPORT Vector44 [WEAK]
EXPORT Vector48 [WEAK]
EXPORT Vector4C [WEAK]
EXPORT Vector50 [WEAK]
EXPORT Vector54 [WEAK]
EXPORT Vector58 [WEAK]
EXPORT Vector5C [WEAK]
EXPORT Vector60 [WEAK]
EXPORT Vector64 [WEAK]
EXPORT Vector68 [WEAK]
EXPORT Vector6C [WEAK]
EXPORT Vector70 [WEAK]
EXPORT Vector74 [WEAK]
EXPORT Vector78 [WEAK]
EXPORT Vector7C [WEAK]
EXPORT Vector80 [WEAK]
EXPORT Vector84 [WEAK]
EXPORT Vector88 [WEAK]
EXPORT Vector8C [WEAK]
EXPORT Vector90 [WEAK]
EXPORT Vector94 [WEAK]
EXPORT Vector98 [WEAK]
EXPORT Vector9C [WEAK]
EXPORT VectorA0 [WEAK]
EXPORT VectorA4 [WEAK]
EXPORT VectorA8 [WEAK]
EXPORT VectorAC [WEAK]
EXPORT VectorB0 [WEAK]
EXPORT VectorB4 [WEAK]
EXPORT VectorB8 [WEAK]
EXPORT VectorBC [WEAK]
EXPORT VectorC0 [WEAK]
EXPORT VectorC4 [WEAK]
EXPORT VectorC8 [WEAK]
EXPORT VectorCC [WEAK]
EXPORT VectorD0 [WEAK]
EXPORT VectorD4 [WEAK]
EXPORT VectorD8 [WEAK]
EXPORT VectorDC [WEAK]
EXPORT VectorE0 [WEAK]
EXPORT VectorE4 [WEAK]
EXPORT VectorE8 [WEAK]
EXPORT VectorEC [WEAK]
EXPORT VectorF0 [WEAK]
EXPORT VectorF4 [WEAK]
EXPORT VectorF8 [WEAK]
EXPORT VectorFC [WEAK]
EXPORT Vector100 [WEAK]
EXPORT Vector104 [WEAK]
EXPORT Vector108 [WEAK]
EXPORT Vector10C [WEAK]
EXPORT Vector110 [WEAK]
EXPORT Vector114 [WEAK]
EXPORT Vector118 [WEAK]
EXPORT Vector11C [WEAK]
EXPORT Vector120 [WEAK]
EXPORT Vector124 [WEAK]
EXPORT Vector128 [WEAK]
EXPORT Vector12C [WEAK]
EXPORT Vector130 [WEAK]
EXPORT Vector134 [WEAK]
EXPORT Vector138 [WEAK]
EXPORT Vector13C [WEAK]
EXPORT Vector140 [WEAK]
EXPORT Vector144 [WEAK]
EXPORT Vector148 [WEAK]
EXPORT Vector14C [WEAK]
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
Vector128
Vector12C
Vector130
Vector134
Vector138
Vector13C
Vector140
Vector144
Vector148
Vector14C
b _unhandled_exception
ENDP
END
|
akpc806a/CAN_Logger
| 6,258
|
Firmware/IAR/os/ports/RVCT/ARMCMx/LPC11xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
PRESERVE8
AREA RESET, DATA, READONLY
IMPORT __initial_msp
IMPORT Reset_Handler
EXPORT __Vectors
__Vectors
DCD __initial_msp
DCD Reset_Handler
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
AREA |.text|, CODE, READONLY
THUMB
/*
* Default interrupt handlers.
*/
EXPORT _unhandled_exception
_unhandled_exception PROC
EXPORT NMIVector [WEAK]
EXPORT HardFaultVector [WEAK]
EXPORT MemManageVector [WEAK]
EXPORT BusFaultVector [WEAK]
EXPORT UsageFaultVector [WEAK]
EXPORT Vector1C [WEAK]
EXPORT Vector20 [WEAK]
EXPORT Vector24 [WEAK]
EXPORT Vector28 [WEAK]
EXPORT SVCallVector [WEAK]
EXPORT DebugMonitorVector [WEAK]
EXPORT Vector34 [WEAK]
EXPORT PendSVVector [WEAK]
EXPORT SysTickVector [WEAK]
EXPORT Vector40 [WEAK]
EXPORT Vector44 [WEAK]
EXPORT Vector48 [WEAK]
EXPORT Vector4C [WEAK]
EXPORT Vector50 [WEAK]
EXPORT Vector54 [WEAK]
EXPORT Vector58 [WEAK]
EXPORT Vector5C [WEAK]
EXPORT Vector60 [WEAK]
EXPORT Vector64 [WEAK]
EXPORT Vector68 [WEAK]
EXPORT Vector6C [WEAK]
EXPORT Vector70 [WEAK]
EXPORT Vector74 [WEAK]
EXPORT Vector78 [WEAK]
EXPORT Vector7C [WEAK]
EXPORT Vector80 [WEAK]
EXPORT Vector84 [WEAK]
EXPORT Vector88 [WEAK]
EXPORT Vector8C [WEAK]
EXPORT Vector90 [WEAK]
EXPORT Vector94 [WEAK]
EXPORT Vector98 [WEAK]
EXPORT Vector9C [WEAK]
EXPORT VectorA0 [WEAK]
EXPORT VectorA4 [WEAK]
EXPORT VectorA8 [WEAK]
EXPORT VectorAC [WEAK]
EXPORT VectorB0 [WEAK]
EXPORT VectorB4 [WEAK]
EXPORT VectorB8 [WEAK]
EXPORT VectorBC [WEAK]
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
b _unhandled_exception
ENDP
END
|
akpc806a/CAN_Logger
| 8,800
|
Firmware/IAR/os/ports/RVCT/ARMCMx/LPC13xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
PRESERVE8
AREA RESET, DATA, READONLY
IMPORT __initial_msp
IMPORT Reset_Handler
EXPORT __Vectors
__Vectors
DCD __initial_msp
DCD Reset_Handler
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
DCD VectorF4
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
AREA |.text|, CODE, READONLY
THUMB
/*
* Default interrupt handlers.
*/
EXPORT _unhandled_exception
_unhandled_exception PROC
EXPORT NMIVector [WEAK]
EXPORT HardFaultVector [WEAK]
EXPORT MemManageVector [WEAK]
EXPORT BusFaultVector [WEAK]
EXPORT UsageFaultVector [WEAK]
EXPORT Vector1C [WEAK]
EXPORT Vector20 [WEAK]
EXPORT Vector24 [WEAK]
EXPORT Vector28 [WEAK]
EXPORT SVCallVector [WEAK]
EXPORT DebugMonitorVector [WEAK]
EXPORT Vector34 [WEAK]
EXPORT PendSVVector [WEAK]
EXPORT SysTickVector [WEAK]
EXPORT Vector40 [WEAK]
EXPORT Vector44 [WEAK]
EXPORT Vector48 [WEAK]
EXPORT Vector4C [WEAK]
EXPORT Vector50 [WEAK]
EXPORT Vector54 [WEAK]
EXPORT Vector58 [WEAK]
EXPORT Vector5C [WEAK]
EXPORT Vector60 [WEAK]
EXPORT Vector64 [WEAK]
EXPORT Vector68 [WEAK]
EXPORT Vector6C [WEAK]
EXPORT Vector70 [WEAK]
EXPORT Vector74 [WEAK]
EXPORT Vector78 [WEAK]
EXPORT Vector7C [WEAK]
EXPORT Vector80 [WEAK]
EXPORT Vector84 [WEAK]
EXPORT Vector88 [WEAK]
EXPORT Vector8C [WEAK]
EXPORT Vector90 [WEAK]
EXPORT Vector94 [WEAK]
EXPORT Vector98 [WEAK]
EXPORT Vector9C [WEAK]
EXPORT VectorA0 [WEAK]
EXPORT VectorA4 [WEAK]
EXPORT VectorA8 [WEAK]
EXPORT VectorAC [WEAK]
EXPORT VectorB0 [WEAK]
EXPORT VectorB4 [WEAK]
EXPORT VectorB8 [WEAK]
EXPORT VectorBC [WEAK]
EXPORT VectorC0 [WEAK]
EXPORT VectorC4 [WEAK]
EXPORT VectorC8 [WEAK]
EXPORT VectorCC [WEAK]
EXPORT VectorD0 [WEAK]
EXPORT VectorD4 [WEAK]
EXPORT VectorD8 [WEAK]
EXPORT VectorDC [WEAK]
EXPORT VectorE0 [WEAK]
EXPORT VectorE4 [WEAK]
EXPORT VectorE8 [WEAK]
EXPORT VectorEC [WEAK]
EXPORT VectorF0 [WEAK]
EXPORT VectorF4 [WEAK]
EXPORT VectorF8 [WEAK]
EXPORT VectorFC [WEAK]
EXPORT Vector100 [WEAK]
EXPORT Vector104 [WEAK]
EXPORT Vector108 [WEAK]
EXPORT Vector10C [WEAK]
EXPORT Vector110 [WEAK]
EXPORT Vector114 [WEAK]
EXPORT Vector118 [WEAK]
EXPORT Vector11C [WEAK]
EXPORT Vector120 [WEAK]
EXPORT Vector124 [WEAK]
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
b _unhandled_exception
ENDP
END
|
akpc806a/CAN_Logger
| 11,246
|
Firmware/IAR/os/ports/RVCT/ARMCMx/STM32F4xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32F4XX)
#define _FROM_ASM_
#include "board.h"
#endif
PRESERVE8
AREA RESET, DATA, READONLY
IMPORT __initial_msp
IMPORT Reset_Handler
EXPORT __Vectors
__Vectors
DCD __initial_msp
DCD Reset_Handler
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
DCD VectorF4
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
DCD Vector128
DCD Vector12C
DCD Vector130
DCD Vector134
DCD Vector138
DCD Vector13C
DCD Vector140
DCD Vector144
DCD Vector148
DCD Vector14C
DCD Vector150
DCD Vector154
DCD Vector158
DCD Vector15C
DCD Vector160
DCD Vector164
DCD Vector168
DCD Vector16C
DCD Vector170
DCD Vector174
DCD Vector178
DCD Vector17C
DCD Vector180
DCD Vector184
AREA |.text|, CODE, READONLY
THUMB
/*
* Default interrupt handlers.
*/
EXPORT _unhandled_exception
_unhandled_exception PROC
EXPORT NMIVector [WEAK]
EXPORT HardFaultVector [WEAK]
EXPORT MemManageVector [WEAK]
EXPORT BusFaultVector [WEAK]
EXPORT UsageFaultVector [WEAK]
EXPORT Vector1C [WEAK]
EXPORT Vector20 [WEAK]
EXPORT Vector24 [WEAK]
EXPORT Vector28 [WEAK]
EXPORT SVCallVector [WEAK]
EXPORT DebugMonitorVector [WEAK]
EXPORT Vector34 [WEAK]
EXPORT PendSVVector [WEAK]
EXPORT SysTickVector [WEAK]
EXPORT Vector40 [WEAK]
EXPORT Vector44 [WEAK]
EXPORT Vector48 [WEAK]
EXPORT Vector4C [WEAK]
EXPORT Vector50 [WEAK]
EXPORT Vector54 [WEAK]
EXPORT Vector58 [WEAK]
EXPORT Vector5C [WEAK]
EXPORT Vector60 [WEAK]
EXPORT Vector64 [WEAK]
EXPORT Vector68 [WEAK]
EXPORT Vector6C [WEAK]
EXPORT Vector70 [WEAK]
EXPORT Vector74 [WEAK]
EXPORT Vector78 [WEAK]
EXPORT Vector7C [WEAK]
EXPORT Vector80 [WEAK]
EXPORT Vector84 [WEAK]
EXPORT Vector88 [WEAK]
EXPORT Vector8C [WEAK]
EXPORT Vector90 [WEAK]
EXPORT Vector94 [WEAK]
EXPORT Vector98 [WEAK]
EXPORT Vector9C [WEAK]
EXPORT VectorA0 [WEAK]
EXPORT VectorA4 [WEAK]
EXPORT VectorA8 [WEAK]
EXPORT VectorAC [WEAK]
EXPORT VectorB0 [WEAK]
EXPORT VectorB4 [WEAK]
EXPORT VectorB8 [WEAK]
EXPORT VectorBC [WEAK]
EXPORT VectorC0 [WEAK]
EXPORT VectorC4 [WEAK]
EXPORT VectorC8 [WEAK]
EXPORT VectorCC [WEAK]
EXPORT VectorD0 [WEAK]
EXPORT VectorD4 [WEAK]
EXPORT VectorD8 [WEAK]
EXPORT VectorDC [WEAK]
EXPORT VectorE0 [WEAK]
EXPORT VectorE4 [WEAK]
EXPORT VectorE8 [WEAK]
EXPORT VectorEC [WEAK]
EXPORT VectorF0 [WEAK]
EXPORT VectorF4 [WEAK]
EXPORT VectorF8 [WEAK]
EXPORT VectorFC [WEAK]
EXPORT Vector100 [WEAK]
EXPORT Vector104 [WEAK]
EXPORT Vector108 [WEAK]
EXPORT Vector10C [WEAK]
EXPORT Vector110 [WEAK]
EXPORT Vector114 [WEAK]
EXPORT Vector118 [WEAK]
EXPORT Vector11C [WEAK]
EXPORT Vector120 [WEAK]
EXPORT Vector124 [WEAK]
EXPORT Vector128 [WEAK]
EXPORT Vector12C [WEAK]
EXPORT Vector130 [WEAK]
EXPORT Vector134 [WEAK]
EXPORT Vector138 [WEAK]
EXPORT Vector13C [WEAK]
EXPORT Vector140 [WEAK]
EXPORT Vector144 [WEAK]
EXPORT Vector148 [WEAK]
EXPORT Vector14C [WEAK]
EXPORT Vector150 [WEAK]
EXPORT Vector154 [WEAK]
EXPORT Vector158 [WEAK]
EXPORT Vector15C [WEAK]
EXPORT Vector160 [WEAK]
EXPORT Vector164 [WEAK]
EXPORT Vector168 [WEAK]
EXPORT Vector16C [WEAK]
EXPORT Vector170 [WEAK]
EXPORT Vector174 [WEAK]
EXPORT Vector178 [WEAK]
EXPORT Vector17C [WEAK]
EXPORT Vector180 [WEAK]
EXPORT Vector184 [WEAK]
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
Vector128
Vector12C
Vector130
Vector134
Vector138
Vector13C
Vector140
Vector144
Vector148
Vector14C
Vector150
Vector154
Vector158
Vector15C
Vector160
Vector164
Vector168
Vector16C
Vector170
Vector174
Vector178
Vector17C
Vector180
Vector184
b _unhandled_exception
ENDP
END
|
akpc806a/CAN_Logger
| 3,130
|
Firmware/IAR/os/ports/IAR/ARMCMx/chcoreasm_v7m.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?chcoreasm_v7m
AAPCS INTERWORK, VFP_COMPATIBLE
PRESERVE8
/*
* Imports the Cortex-Mx configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
CONTEXT_OFFSET SET 12
SCB_ICSR SET 0xE000ED04
ICSR_PENDSVSET SET 0x10000000
SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
EXTERN chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
EXTERN dbg_check_unlock
EXTERN dbg_check_lock
#endif
THUMB
/*
* Performs a context switch between two threads.
*/
PUBLIC _port_switch
_port_switch:
push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
#if CORTEX_USE_FPU
vpush {s16-s31}
#endif
str sp, [r1, #CONTEXT_OFFSET]
ldr sp, [r0, #CONTEXT_OFFSET]
#if CORTEX_USE_FPU
vpop {s16-s31}
#endif
pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
/*
* Start a thread by invoking its work function.
* If the work function returns @p chThdExit() is automatically invoked.
*/
PUBLIC _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
#if CORTEX_SIMPLIFIED_PRIORITY
cpsie i
#else
movs r3, #CORTEX_BASEPRI_DISABLED
msr BASEPRI, r3
#endif
mov r0, r5
blx r4
bl chThdExit
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
PUBLIC _port_switch_from_isr
PUBLIC _port_exit_from_isr
_port_switch_from_isr:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
_port_exit_from_isr:
#if CORTEX_SIMPLIFIED_PRIORITY
mov r3, #LWRD SCB_ICSR
movt r3, #HWRD SCB_ICSR
mov r2, #ICSR_PENDSVSET
str r2, [r3]
cpsie i
.L3: b .L3
#else
svc #0
#endif
END
|
akpc806a/CAN_Logger
| 3,189
|
Firmware/IAR/os/ports/IAR/ARMCMx/chcoreasm_v6m.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?chcoreasm_v6m
AAPCS INTERWORK, VFP_COMPATIBLE
PRESERVE8
/*
* Imports the Cortex-Mx configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
CONTEXT_OFFSET SET 12
SCB_ICSR SET 0xE000ED04
SECTION .text:CODE:NOROOT(2)
EXTERN chThdExit
EXTERN chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
EXTERN dbg_check_unlock
EXTERN dbg_check_lock
#endif
THUMB
/*
* Performs a context switch between two threads.
*/
PUBLIC _port_switch
_port_switch:
push {r4, r5, r6, r7, lr}
mov r4, r8
mov r5, r9
mov r6, r10
mov r7, r11
push {r4, r5, r6, r7}
mov r3, sp
str r3, [r1, #CONTEXT_OFFSET]
ldr r3, [r0, #CONTEXT_OFFSET]
mov sp, r3
pop {r4, r5, r6, r7}
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
pop {r4, r5, r6, r7, pc}
/*
* Start a thread by invoking its work function.
* If the work function returns @p chThdExit() is automatically invoked.
*/
PUBLIC _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
cpsie i
mov r0, r5
blx r4
bl chThdExit
/*
* Post-IRQ switch code.
* Exception handlers return here for context switching.
*/
PUBLIC _port_switch_from_isr
PUBLIC _port_exit_from_isr
_port_switch_from_isr:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
_port_exit_from_isr:
ldr r2, =SCB_ICSR
movs r3, #128
#if CORTEX_ALTERNATE_SWITCH
lsls r3, r3, #21
str r3, [r2, #0]
cpsie i
#else
lsls r3, r3, #24
str r3, [r2, #0]
#endif
waithere:
b waithere
END
|
akpc806a/CAN_Logger
| 2,257
|
Firmware/IAR/os/ports/IAR/ARMCMx/cstartup.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?cstartup
CONTROL_MODE_PRIVILEGED SET 0
CONTROL_MODE_UNPRIVILEGED SET 1
CONTROL_USE_MSP SET 0
CONTROL_USE_PSP SET 2
AAPCS INTERWORK, VFP_COMPATIBLE, ROPI
PRESERVE8
SECTION .intvec:CODE:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
PUBLIC __main_thread_stack_base__
__main_thread_stack_base__:
PUBLIC __heap_end__
__heap_end__:
SECTION SYSHEAP:DATA:NOROOT(3)
PUBLIC __heap_base__
__heap_base__:
PUBLIC __iar_program_start
EXTERN __vector_table
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
EXTERN __cmain
SECTION .text:CODE:REORDER(2)
REQUIRE __vector_table
THUMB
__iar_program_start:
cpsid i
ldr r0, =SFE(CSTACK)
msr PSP, r0
movs r0, #CONTROL_MODE_PRIVILEGED | CONTROL_USE_PSP
msr CONTROL, r0
isb
bl __early_init
bl __iar_init_core
bl __iar_init_vfp
b __cmain
PUBWEAK __early_init
__early_init:
bx lr
END
|
akpc806a/CAN_Logger
| 5,408
|
Firmware/IAR/os/ports/IAR/ARMCMx/STM32L1xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32L1XX_MD)
#define _FROM_ASM_
#include "board.h"
#endif
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(3)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
_unhandled_exception
b _unhandled_exception
END
|
akpc806a/CAN_Logger
| 7,317
|
Firmware/IAR/os/ports/IAR/ARMCMx/STM32F1xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#if !defined(STM32F10X_LD) && !defined(STM32F10X_LD_VL) && \
!defined(STM32F10X_MD) && !defined(STM32F10X_MD_VL) && \
!defined(STM32F10X_HD) && !defined(STM32F10X_XL) && \
!defined(STM32F10X_CL)
#define _FROM_ASM_
#include "board.h"
#endif
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(3)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
#if defined(STM32F10X_MD_VL) || defined(STM32F10X_HD) || \
defined(STM32F10X_XL) || defined(STM32F10X_CL)
DCD VectorEC
DCD VectorF0
DCD VectorF4
#endif
#if defined(STM32F10X_HD) || defined(STM32F10X_XL) || defined(STM32F10X_CL)
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
DCD Vector128
DCD Vector12C
#endif
#if defined(STM32F10X_CL)
DCD Vector130
DCD Vector134
DCD Vector138
DCD Vector13C
DCD Vector140
DCD Vector144
DCD Vector148
DCD Vector14C
#endif
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBWEAK VectorF4
PUBWEAK VectorF8
PUBWEAK VectorFC
PUBWEAK Vector100
PUBWEAK Vector104
PUBWEAK Vector108
PUBWEAK Vector10C
PUBWEAK Vector110
PUBWEAK Vector114
PUBWEAK Vector118
PUBWEAK Vector11C
PUBWEAK Vector120
PUBWEAK Vector124
PUBWEAK Vector128
PUBWEAK Vector12C
PUBWEAK Vector130
PUBWEAK Vector134
PUBWEAK Vector138
PUBWEAK Vector13C
PUBWEAK Vector140
PUBWEAK Vector144
PUBWEAK Vector148
PUBWEAK Vector14C
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
Vector128
Vector12C
Vector130
Vector134
Vector138
Vector13C
Vector140
Vector144
Vector148
Vector14C
_unhandled_exception
b _unhandled_exception
END
|
akpc806a/CAN_Logger
| 4,568
|
Firmware/IAR/os/ports/IAR/ARMCMx/LPC11xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
_unhandled_exception
b _unhandled_exception
END
|
akpc806a/CAN_Logger
| 6,132
|
Firmware/IAR/os/ports/IAR/ARMCMx/LPC13xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
DCD VectorF4
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBWEAK VectorF4
PUBWEAK VectorF8
PUBWEAK VectorFC
PUBWEAK Vector100
PUBWEAK Vector104
PUBWEAK Vector108
PUBWEAK Vector10C
PUBWEAK Vector110
PUBWEAK Vector114
PUBWEAK Vector118
PUBWEAK Vector11C
PUBWEAK Vector120
PUBWEAK Vector124
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
_unhandled_exception
b _unhandled_exception
END
|
akpc806a/CAN_Logger
| 7,620
|
Firmware/IAR/os/ports/IAR/ARMCMx/STM32F4xx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
MODULE ?vectors
AAPCS INTERWORK, VFP_COMPATIBLE, RWPI_COMPATIBLE
PRESERVE8
SECTION IRQSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(3)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table:
DCD SFE(IRQSTACK)
DCD __iar_program_start
DCD NMIVector
DCD HardFaultVector
DCD MemManageVector
DCD BusFaultVector
DCD UsageFaultVector
DCD Vector1C
DCD Vector20
DCD Vector24
DCD Vector28
DCD SVCallVector
DCD DebugMonitorVector
DCD Vector34
DCD PendSVVector
DCD SysTickVector
DCD Vector40
DCD Vector44
DCD Vector48
DCD Vector4C
DCD Vector50
DCD Vector54
DCD Vector58
DCD Vector5C
DCD Vector60
DCD Vector64
DCD Vector68
DCD Vector6C
DCD Vector70
DCD Vector74
DCD Vector78
DCD Vector7C
DCD Vector80
DCD Vector84
DCD Vector88
DCD Vector8C
DCD Vector90
DCD Vector94
DCD Vector98
DCD Vector9C
DCD VectorA0
DCD VectorA4
DCD VectorA8
DCD VectorAC
DCD VectorB0
DCD VectorB4
DCD VectorB8
DCD VectorBC
DCD VectorC0
DCD VectorC4
DCD VectorC8
DCD VectorCC
DCD VectorD0
DCD VectorD4
DCD VectorD8
DCD VectorDC
DCD VectorE0
DCD VectorE4
DCD VectorE8
DCD VectorEC
DCD VectorF0
DCD VectorF4
DCD VectorF8
DCD VectorFC
DCD Vector100
DCD Vector104
DCD Vector108
DCD Vector10C
DCD Vector110
DCD Vector114
DCD Vector118
DCD Vector11C
DCD Vector120
DCD Vector124
DCD Vector128
DCD Vector12C
DCD Vector130
DCD Vector134
DCD Vector138
DCD Vector13C
DCD Vector140
DCD Vector144
DCD Vector148
DCD Vector14C
DCD Vector150
DCD Vector154
DCD Vector158
DCD Vector15C
DCD Vector160
DCD Vector164
DCD Vector168
DCD Vector16C
DCD Vector170
DCD Vector174
DCD Vector178
DCD Vector17C
DCD Vector180
DCD Vector184
/*
* Default interrupt handlers.
*/
PUBWEAK NMIVector
PUBWEAK HardFaultVector
PUBWEAK MemManageVector
PUBWEAK BusFaultVector
PUBWEAK UsageFaultVector
PUBWEAK Vector1C
PUBWEAK Vector20
PUBWEAK Vector24
PUBWEAK Vector28
PUBWEAK SVCallVector
PUBWEAK DebugMonitorVector
PUBWEAK Vector34
PUBWEAK PendSVVector
PUBWEAK SysTickVector
PUBWEAK Vector40
PUBWEAK Vector44
PUBWEAK Vector48
PUBWEAK Vector4C
PUBWEAK Vector50
PUBWEAK Vector54
PUBWEAK Vector58
PUBWEAK Vector5C
PUBWEAK Vector60
PUBWEAK Vector64
PUBWEAK Vector68
PUBWEAK Vector6C
PUBWEAK Vector70
PUBWEAK Vector74
PUBWEAK Vector78
PUBWEAK Vector7C
PUBWEAK Vector80
PUBWEAK Vector84
PUBWEAK Vector88
PUBWEAK Vector8C
PUBWEAK Vector90
PUBWEAK Vector94
PUBWEAK Vector98
PUBWEAK Vector9C
PUBWEAK VectorA0
PUBWEAK VectorA4
PUBWEAK VectorA8
PUBWEAK VectorAC
PUBWEAK VectorB0
PUBWEAK VectorB4
PUBWEAK VectorB8
PUBWEAK VectorBC
PUBWEAK VectorC0
PUBWEAK VectorC4
PUBWEAK VectorC8
PUBWEAK VectorCC
PUBWEAK VectorD0
PUBWEAK VectorD4
PUBWEAK VectorD8
PUBWEAK VectorDC
PUBWEAK VectorE0
PUBWEAK VectorE4
PUBWEAK VectorE8
PUBWEAK VectorEC
PUBWEAK VectorF0
PUBWEAK VectorF4
PUBWEAK VectorF8
PUBWEAK VectorFC
PUBWEAK Vector100
PUBWEAK Vector104
PUBWEAK Vector108
PUBWEAK Vector10C
PUBWEAK Vector110
PUBWEAK Vector114
PUBWEAK Vector118
PUBWEAK Vector11C
PUBWEAK Vector120
PUBWEAK Vector124
PUBWEAK Vector128
PUBWEAK Vector12C
PUBWEAK Vector130
PUBWEAK Vector134
PUBWEAK Vector138
PUBWEAK Vector13C
PUBWEAK Vector140
PUBWEAK Vector144
PUBWEAK Vector148
PUBWEAK Vector14C
PUBWEAK Vector150
PUBWEAK Vector154
PUBWEAK Vector158
PUBWEAK Vector15C
PUBWEAK Vector160
PUBWEAK Vector164
PUBWEAK Vector168
PUBWEAK Vector16C
PUBWEAK Vector170
PUBWEAK Vector174
PUBWEAK Vector178
PUBWEAK Vector17C
PUBWEAK Vector180
PUBWEAK Vector184
PUBLIC _unhandled_exception
SECTION .text:CODE:REORDER(1)
THUMB
NMIVector
HardFaultVector
MemManageVector
BusFaultVector
UsageFaultVector
Vector1C
Vector20
Vector24
Vector28
SVCallVector
DebugMonitorVector
Vector34
PendSVVector
SysTickVector
Vector40
Vector44
Vector48
Vector4C
Vector50
Vector54
Vector58
Vector5C
Vector60
Vector64
Vector68
Vector6C
Vector70
Vector74
Vector78
Vector7C
Vector80
Vector84
Vector88
Vector8C
Vector90
Vector94
Vector98
Vector9C
VectorA0
VectorA4
VectorA8
VectorAC
VectorB0
VectorB4
VectorB8
VectorBC
VectorC0
VectorC4
VectorC8
VectorCC
VectorD0
VectorD4
VectorD8
VectorDC
VectorE0
VectorE4
VectorE8
VectorEC
VectorF0
VectorF4
VectorF8
VectorFC
Vector100
Vector104
Vector108
Vector10C
Vector110
Vector114
Vector118
Vector11C
Vector120
Vector124
Vector128
Vector12C
Vector130
Vector134
Vector138
Vector13C
Vector140
Vector144
Vector148
Vector14C
Vector150
Vector154
Vector158
Vector15C
Vector160
Vector164
Vector168
Vector16C
Vector170
Vector174
Vector178
Vector17C
Vector180
Vector184
_unhandled_exception
b _unhandled_exception
END
|
akpc806a/CAN_Logger
| 2,010
|
Firmware/IAR/os/ports/GCC/MSP430/chcoreasm.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
#include "chconf.h"
#define FALSE 0
#define TRUE 1
.text
.p2align 1, 0
.weak _port_switch
_port_switch:
push r11
push r10
push r9
push r8
push r7
push r6
push r5
push r4
mov r1, 6(r14)
mov 6(r15), r1
pop r4
pop r5
pop r6
pop r7
pop r8
pop r9
pop r10
pop r11
ret
.p2align 1, 0
.weak _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
call #dbg_check_unlock
#endif
eint
mov r11, r15
call r10
call #chThdExit
; Falls into _port_halt
.p2align 1, 0
.weak _port_halt
_port_halt:
dint
.L1: jmp .L1
|
akpc806a/CAN_Logger
| 4,536
|
Firmware/IAR/os/ports/GCC/ARM/crt0.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file ARM/crt0.s
* @brief Generic ARM7/9 startup file for ChibiOS/RT.
*
* @addtogroup ARM_CORE
* @{
*/
#if !defined(__DOXYGEN__)
.set MODE_USR, 0x10
.set MODE_FIQ, 0x11
.set MODE_IRQ, 0x12
.set MODE_SVC, 0x13
.set MODE_ABT, 0x17
.set MODE_UND, 0x1B
.set MODE_SYS, 0x1F
.set I_BIT, 0x80
.set F_BIT, 0x40
.text
.code 32
.balign 4
/*
* Reset handler.
*/
.global ResetHandler
ResetHandler:
/*
* Stack pointers initialization.
*/
ldr r0, =__ram_end__
/* Undefined */
msr CPSR_c, #MODE_UND | I_BIT | F_BIT
mov sp, r0
ldr r1, =__und_stack_size__
sub r0, r0, r1
/* Abort */
msr CPSR_c, #MODE_ABT | I_BIT | F_BIT
mov sp, r0
ldr r1, =__abt_stack_size__
sub r0, r0, r1
/* FIQ */
msr CPSR_c, #MODE_FIQ | I_BIT | F_BIT
mov sp, r0
ldr r1, =__fiq_stack_size__
sub r0, r0, r1
/* IRQ */
msr CPSR_c, #MODE_IRQ | I_BIT | F_BIT
mov sp, r0
ldr r1, =__irq_stack_size__
sub r0, r0, r1
/* Supervisor */
msr CPSR_c, #MODE_SVC | I_BIT | F_BIT
mov sp, r0
ldr r1, =__svc_stack_size__
sub r0, r0, r1
/* System */
msr CPSR_c, #MODE_SYS | I_BIT | F_BIT
mov sp, r0
// ldr r1, =__sys_stack_size__
// sub r0, r0, r1
/*
* Early initialization.
*/
#ifndef THUMB_NO_INTERWORKING
bl __early_init
#else
add r0, pc, #1
bx r0
.code 16
bl __early_init
mov r0, pc
bx r0
.code 32
#endif
/*
* Data initialization.
* NOTE: It assumes that the DATA size is a multiple of 4.
*/
ldr r1, =_textdata
ldr r2, =_data
ldr r3, =_edata
dataloop:
cmp r2, r3
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo dataloop
/*
* BSS initialization.
* NOTE: It assumes that the BSS size is a multiple of 4.
*/
mov r0, #0
ldr r1, =_bss_start
ldr r2, =_bss_end
bssloop:
cmp r1, r2
strlo r0, [r1], #4
blo bssloop
/*
* Main program invocation.
*/
#ifdef THUMB_NO_INTERWORKING
add r0, pc, #1
bx r0
.code 16
bl main
ldr r1, =_main_exit_handler
bx r1
.code 32
#else
bl main
b _main_exit_handler
#endif
/*
* Default main function exit handler.
*/
.weak _main_exit_handler
.global _main_exit_handler
_main_exit_handler:
.loop: b .loop
/*
* Default early initialization code. It is declared weak in order to be
* replaced by the real initialization code.
* Early initialization is performed just after reset before BSS and DATA
* segments initialization.
*/
#ifdef THUMB_NO_INTERWORKING
.thumb_func
.code 16
#endif
.weak __early_init
hwinit0:
bx lr
.code 32
#endif
/** @} */
|
akpc806a/CAN_Logger
| 7,186
|
Firmware/IAR/os/ports/GCC/ARM/chcoreasm.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file ARM/chcoreasm.s
* @brief ARM7/9 architecture port low level code.
*
* @addtogroup ARM_CORE
* @{
*/
#include "chconf.h"
#define FALSE 0
#define TRUE 1
#if !defined(__DOXYGEN__)
.set MODE_USR, 0x10
.set MODE_FIQ, 0x11
.set MODE_IRQ, 0x12
.set MODE_SVC, 0x13
.set MODE_ABT, 0x17
.set MODE_UND, 0x1B
.set MODE_SYS, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
/*
* Interrupt enable/disable functions, only present if there is THUMB code in
* the system because those are inlined in ARM code.
*/
#ifdef THUMB_PRESENT
.balign 16
.code 16
.thumb_func
.global _port_disable_thumb
_port_disable_thumb:
mov r3, pc
bx r3
.code 32
mrs r3, CPSR
orr r3, #I_BIT
msr CPSR_c, r3
orr r3, #F_BIT
msr CPSR_c, r3
bx lr
.balign 16
.code 16
.thumb_func
.global _port_suspend_thumb
_port_suspend_thumb:
.thumb_func
.global _port_lock_thumb
_port_lock_thumb:
mov r3, pc
bx r3
.code 32
msr CPSR_c, #MODE_SYS | I_BIT
bx lr
.balign 16
.code 16
.thumb_func
.global _port_enable_thumb
_port_enable_thumb:
.thumb_func
.global _port_unlock_thumb
_port_unlock_thumb:
mov r3, pc
bx r3
.code 32
msr CPSR_c, #MODE_SYS
bx lr
#endif
.balign 16
#ifdef THUMB_PRESENT
.code 16
.thumb_func
.global _port_switch_thumb
_port_switch_thumb:
mov r2, pc
bx r2
// Jumps into _port_switch_arm in ARM mode
#endif
.code 32
.global _port_switch_arm
_port_switch_arm:
#ifdef CH_CURRP_REGISTER_CACHE
stmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
str sp, [r1, #12]
ldr sp, [r0, #12]
#ifdef THUMB_PRESENT
ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, lr}
bx lr
#else /* !THUMB_PRESENT */
ldmfd sp!, {r4, r5, r6, r8, r9, r10, r11, pc}
#endif /* !THUMB_PRESENT */
#else /* !CH_CURRP_REGISTER_CACHE */
stmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
str sp, [r1, #12]
ldr sp, [r0, #12]
#ifdef THUMB_PRESENT
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, lr}
bx lr
#else /* !THUMB_PRESENT */
ldmfd sp!, {r4, r5, r6, r7, r8, r9, r10, r11, pc}
#endif /* !THUMB_PRESENT */
#endif /* !CH_CURRP_REGISTER_CACHE */
/*
* Common exit point for all IRQ routines, it performs the rescheduling if
* required.
* System stack frame structure after a context switch in the
* interrupt handler:
*
* High +------------+
* | LR_USR | -+
* | R12 | |
* | R3 | |
* | R2 | | External context: IRQ handler frame
* | R1 | |
* | R0 | |
* | PC | | (user code return address)
* | PSR_USR | -+ (user code status)
* | .... | <- chSchDoReschedule() stack frame, optimize it for space
* | LR | -+ (system code return address)
* | R11 | |
* | R10 | |
* | R9 | |
* | R8 | | Internal context: chSysSwitch() frame
* | (R7) | | (optional, see CH_CURRP_REGISTER_CACHE)
* | R6 | |
* | R5 | |
* SP-> | R4 | -+
* Low +------------+
*/
.balign 16
#ifdef THUMB_NO_INTERWORKING
.code 16
.thumb_func
.globl _port_irq_common
_port_irq_common:
bl chSchIsPreemptionRequired
mov lr, pc
bx lr
.code 32
#else /* !THUMB_NO_INTERWORKING */
.code 32
.globl _port_irq_common
_port_irq_common:
bl chSchIsPreemptionRequired
#endif /* !THUMB_NO_INTERWORKING */
cmp r0, #0 // Simply returns if a
ldmeqfd sp!, {r0-r3, r12, lr} // reschedule is not
subeqs pc, lr, #4 // required.
// Saves the IRQ mode registers in the system stack.
ldmfd sp!, {r0-r3, r12, lr} // IRQ stack now empty.
msr CPSR_c, #MODE_SYS | I_BIT
stmfd sp!, {r0-r3, r12, lr} // Registers on System Stack.
msr CPSR_c, #MODE_IRQ | I_BIT
mrs r0, SPSR
mov r1, lr
msr CPSR_c, #MODE_SYS | I_BIT
stmfd sp!, {r0, r1} // Push R0=SPSR, R1=LR_IRQ.
// Context switch.
#ifdef THUMB_NO_INTERWORKING
add r0, pc, #1
bx r0
.code 16
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
mov lr, pc
bx lr
.code 32
#else /* !THUMB_NO_INTERWORKING */
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchDoReschedule
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
#endif /* !THUMB_NO_INTERWORKING */
// Re-establish the IRQ conditions again.
ldmfd sp!, {r0, r1} // Pop R0=SPSR, R1=LR_IRQ.
msr CPSR_c, #MODE_IRQ | I_BIT
msr SPSR_fsxc, r0
mov lr, r1
msr CPSR_c, #MODE_SYS | I_BIT
ldmfd sp!, {r0-r3, r12, lr}
msr CPSR_c, #MODE_IRQ | I_BIT
subs pc, lr, #4
/*
* Threads trampoline code.
* NOTE: The threads always start in ARM mode and then switches to the
* thread-function mode.
*/
.balign 16
.code 32
.globl _port_thread_start
_port_thread_start:
#if CH_DBG_SYSTEM_STATE_CHECK
mov r0, #0
ldr r1, =dbg_lock_cnt
str r0, [r1]
#endif
msr CPSR_c, #MODE_SYS
#ifndef THUMB_NO_INTERWORKING
mov r0, r5
mov lr, pc
bx r4
bl chThdExit
#else /* !THUMB_NO_INTERWORKING */
add r0, pc, #1
bx r0
.code 16
mov r0, r5
bl jmpr4
bl chThdExit
jmpr4:
bx r4
#endif /* !THUMB_NO_INTERWORKING */
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 8,940
|
Firmware/IAR/os/ports/GCC/PPC/ivor.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file PPC/ivor.s
* @brief Kernel ISRs.
*
* @addtogroup PPC_CORE
* @{
*/
/*
* Imports the PPC configuration headers.
*/
#define _FROM_ASM_
#include "chconf.h"
#include "chcore.h"
#if !defined(__DOXYGEN__)
/*
* INTC registers address.
*/
.equ INTC_IACKR, 0xfff48010
.equ INTC_EOIR, 0xfff48018
.section .handlers, "ax"
#if PPC_SUPPORTS_DECREMENTER
/*
* _IVOR10 handler (Book-E decrementer).
*/
.align 4
.globl _IVOR10
.type _IVOR10, @function
_IVOR10:
/* Creation of the external stack frame (extctx structure).*/
stwu %sp, -80(%sp) /* Size of the extctx structure.*/
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
stw %r0, 32(%sp) /* Saves GPR0. */
mfSRR0 %r0
stw %r0, 8(%sp) /* Saves PC. */
mfSRR1 %r0
stw %r0, 12(%sp) /* Saves MSR. */
mfCR %r0
stw %r0, 16(%sp) /* Saves CR. */
mfLR %r0
stw %r0, 20(%sp) /* Saves LR. */
mfCTR %r0
stw %r0, 24(%sp) /* Saves CTR. */
mfXER %r0
stw %r0, 28(%sp) /* Saves XER. */
stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
stw %r4, 40(%sp)
stw %r5, 44(%sp)
stw %r6, 48(%sp)
stw %r7, 52(%sp)
stw %r8, 56(%sp)
stw %r9, 60(%sp)
stw %r10, 64(%sp)
stw %r11, 68(%sp)
stw %r12, 72(%sp)
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
/* Reset DIE bit in TSR register.*/
lis %r3, 0x0800 /* DIS bit mask. */
mtspr 336, %r3 /* TSR register. */
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_enter_isr
bl dbg_check_lock_from_isr
#endif
bl chSysTimerHandlerI
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock_from_isr
bl dbg_check_leave_isr
#endif
/* System tick handler invocation.*/
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchIsPreemptionRequired
cmpli cr0, %r3, 0
beq cr0, _ivor_exit
bl chSchDoReschedule
b _ivor_exit
#endif /* PPC_SUPPORTS_DECREMENTER */
/*
* _IVOR4 handler (Book-E external interrupt).
*/
.align 4
.globl _IVOR4
.type _IVOR4, @function
_IVOR4:
/* Creation of the external stack frame (extctx structure).*/
stwu %sp, -80(%sp) /* Size of the extctx structure.*/
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
e_stmvsrrw 8(%sp) /* Saves PC, MSR. */
e_stmvsprw 16(%sp) /* Saves CR, LR, CTR, XER. */
e_stmvgprw 32(%sp) /* Saves GPR0, GPR3...GPR12. */
#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
stw %r0, 32(%sp) /* Saves GPR0. */
mfSRR0 %r0
stw %r0, 8(%sp) /* Saves PC. */
mfSRR1 %r0
stw %r0, 12(%sp) /* Saves MSR. */
mfCR %r0
stw %r0, 16(%sp) /* Saves CR. */
mfLR %r0
stw %r0, 20(%sp) /* Saves LR. */
mfCTR %r0
stw %r0, 24(%sp) /* Saves CTR. */
mfXER %r0
stw %r0, 28(%sp) /* Saves XER. */
stw %r3, 36(%sp) /* Saves GPR3...GPR12. */
stw %r4, 40(%sp)
stw %r5, 44(%sp)
stw %r6, 48(%sp)
stw %r7, 52(%sp)
stw %r8, 56(%sp)
stw %r9, 60(%sp)
stw %r10, 64(%sp)
stw %r11, 68(%sp)
stw %r12, 72(%sp)
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
/* Software vector address from the INTC register.*/
lis %r3, INTC_IACKR@h
ori %r3, %r3, INTC_IACKR@l /* IACKR register address. */
lwz %r3, 0(%r3) /* IACKR register value. */
lwz %r3, 0(%r3)
mtCTR %r3 /* Software handler address. */
#if PPC_USE_IRQ_PREEMPTION
/* Allows preemption while executing the software handler.*/
wrteei 1
#endif
/* Exectes the software handler.*/
bctrl
#if PPC_USE_IRQ_PREEMPTION
/* Prevents preemption again.*/
wrteei 0
#endif
/* Informs the INTC that the interrupt has been served.*/
mbar 0
lis %r3, INTC_EOIR@h
ori %r3, %r3, INTC_EOIR@l
stw %r3, 0(%r3) /* Writing any value should do. */
/* Verifies if a reschedule is required.*/
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_lock
#endif
bl chSchIsPreemptionRequired
cmpli cr0, %r3, 0
beq cr0, _ivor_exit
bl chSchDoReschedule
/* Context restore.*/
.globl _ivor_exit
_ivor_exit:
#if CH_DBG_SYSTEM_STATE_CHECK
bl dbg_check_unlock
#endif
#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
e_lmvgprw 32(%sp) /* Restores GPR0, GPR3...GPR12. */
e_lmvsprw 16(%sp) /* Restores CR, LR, CTR, XER. */
e_lmvsrrw 8(%sp) /* Restores PC, MSR. */
#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
lwz %r3, 36(%sp) /* Restores GPR3...GPR12. */
lwz %r4, 40(%sp)
lwz %r5, 44(%sp)
lwz %r6, 48(%sp)
lwz %r7, 52(%sp)
lwz %r8, 56(%sp)
lwz %r9, 60(%sp)
lwz %r10, 64(%sp)
lwz %r11, 68(%sp)
lwz %r12, 72(%sp)
lwz %r0, 8(%sp)
mtSRR0 %r0 /* Restores PC. */
lwz %r0, 12(%sp)
mtSRR1 %r0 /* Restores MSR. */
lwz %r0, 16(%sp)
mtCR %r0 /* Restores CR. */
lwz %r0, 20(%sp)
mtLR %r0 /* Restores LR. */
lwz %r0, 24(%sp)
mtCTR %r0 /* Restores CTR. */
lwz %r0, 28(%sp)
mtXER %r0 /* Restores XER. */
lwz %r0, 32(%sp) /* Restores GPR0. */
#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
addi %sp, %sp, 80 /* Back to the previous frame. */
rfi
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 3,937
|
Firmware/IAR/os/ports/GCC/PPC/crt0.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file PPC/crt0.s
* @brief Generic PowerPC startup file for ChibiOS/RT.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
.section .crt0, "ax"
.align 2
.globl _boot_address
.type _boot_address, @function
_boot_address:
/*
* Stack setup.
*/
lis %r1, __process_stack_end__@h
ori %r1, %r1, __process_stack_end__@l
li %r0, 0
stwu %r0, -8(%r1)
/*
* Small sections registers initialization.
*/
lis %r2, __sdata2_start__@h
ori %r2, %r2, __sdata2_start__@l
lis %r13, __sdata_start__@h
ori %r13, %r13, __sdata_start__@l
/*
* Early initialization.
*/
bl __early_init
/*
* BSS clearing.
*/
lis %r4, __bss_start__@h
ori %r4, %r4, __bss_start__@l
lis %r5, __bss_end__@h
ori %r5, %r5, __bss_end__@l
li %r7, 0
.bssloop:
cmpl cr0, %r4, %r5
bge cr0, .bssend
stw %r7, 0(%r4)
addi %r4, %r4, 4
b .bssloop
.bssend:
/*
* DATA initialization.
*/
lis %r4, __romdata_start__@h
ori %r4, %r4, __romdata_start__@l
lis %r5, __data_start__@h
ori %r5, %r5, __data_start__@l
lis %r6, __data_end__@h
ori %r6, %r6, __data_end__@l
.dataloop:
cmpl cr0, %r5, %r6
bge cr0, .dataend
lwz %r7, 0(%r4)
addi %r4, %r4, 4
stw %r7, 0(%r5)
addi %r5, %r5, 4
b .dataloop
.dataend:
/*
* Late initialization.
*/
bl __late_init
/*
* Main program invocation.
*/
bl main
b _main_exit_handler
/*
* Default main exit code, infinite loop.
*/
.weak _main_exit_handler
.globl _main_exit_handler
.type _main_exit_handler, @function
_main_exit_handler:
b _main_exit_handler
/*
* Default early initialization code, none.
*/
.weak __early_init
.globl __early_init
.type __early_init, @function
__early_init:
blr
/*
* Default late initialization code, none.
*/
.weak __late_init
.globl __late_init
.type __late_init, @function
__late_init:
blr
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 2,799
|
Firmware/IAR/os/ports/GCC/ARM/AT91SAM7/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file ARM/AT91SAM7/vectors.s
* @brief Interrupt vectors for the AT91SAM7 family.
*
* @defgroup ARM_AT91SAM7_VECTORS AT91SAM7 Interrupt Vectors
* @ingroup ARM_SPECIFIC
* @details Interrupt vectors for the AT91SAM7 family.
* @{
*/
#if defined(__DOXYGEN__)
/**
* @brief Unhandled exceptions handler.
* @details Any undefined exception vector points to this function by default.
* This function simply stops the system into an infinite loop.
*
* @notapi
*/
void _unhandled_exception(void) {}
#endif
#if !defined(__DOXYGEN__)
.section vectors
.code 32
.balign 4
/*
* System entry points.
*/
_start:
ldr pc, _reset
ldr pc, _undefined
ldr pc, _swi
ldr pc, _prefetch
ldr pc, _abort
nop
ldr pc, [pc,#-0xF20] /* AIC - AIC_IVR */
ldr pc, [pc,#-0xF20] /* AIC - AIC_FVR */
_reset:
.word ResetHandler /* In crt0.s */
_undefined:
.word UndHandler
_swi:
.word SwiHandler
_prefetch:
.word PrefetchHandler
_abort:
.word AbortHandler
.word 0
.word 0
.word 0
.text
.code 32
.balign 4
/*
* Default exceptions handlers. The handlers are declared weak in order to be
* replaced by the real handling code. Everything is defaulted to an infinite
* loop.
*/
.weak UndHandler
UndHandler:
.weak SwiHandler
SwiHandler:
.weak PrefetchHandler
PrefetchHandler:
.weak AbortHandler
AbortHandler:
.weak FiqHandler
FiqHandler:
.global _unhandled_exception
_unhandled_exception:
b _unhandled_exception
#endif
/** @} */
|
akpc806a/CAN_Logger
| 2,760
|
Firmware/IAR/os/ports/GCC/ARM/LPC214x/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file ARM/LPC214x/vectors.s
* @brief Interrupt vectors for the LPC214x family.
*
* @defgroup ARM_LPC214x_VECTORS LPC214x Interrupt Vectors
* @ingroup ARM_SPECIFIC
* @details Interrupt vectors for the LPC214x family.
* @{
*/
#if defined(__DOXYGEN__)
/**
* @brief Unhandled exceptions handler.
* @details Any undefined exception vector points to this function by default.
* This function simply stops the system into an infinite loop.
*
* @notapi
*/
void _unhandled_exception(void) {}
#endif
#if !defined(__DOXYGEN__)
.section vectors
.code 32
.balign 4
/*
* System entry points.
*/
_start:
ldr pc, _reset
ldr pc, _undefined
ldr pc, _swi
ldr pc, _prefetch
ldr pc, _abort
nop
ldr pc, [pc,#-0xFF0] /* VIC - IRQ Vector Register */
ldr pc, _fiq
_reset:
.word ResetHandler /* In crt0.s */
_undefined:
.word UndHandler
_swi:
.word SwiHandler
_prefetch:
.word PrefetchHandler
_abort:
.word AbortHandler
_fiq:
.word FiqHandler
.word 0
.word 0
/*
* Default exceptions handlers. The handlers are declared weak in order to be
* replaced by the real handling code. Everything is defaulted to an infinite
* loop.
*/
.weak UndHandler
UndHandler:
.weak SwiHandler
SwiHandler:
.weak PrefetchHandler
PrefetchHandler:
.weak AbortHandler
AbortHandler:
.weak FiqHandler
FiqHandler:
.global _unhandled_exception
_unhandled_exception:
b _unhandled_exception
#endif
/** @} */
|
akpc806a/CAN_Logger
| 13,515
|
Firmware/IAR/os/ports/GCC/PPC/SPC56ECxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560BCxx/vectors.s
* @brief SPC560BCxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216, vector217, vector218, vector219
.long vector220, vector221, vector222, vector223
.long vector224, vector225, vector226, vector227
.long vector228, vector229, vector230, vector231
.long vector232, vector233, vector234, vector235
.long vector236, vector237, vector238, vector239
.long vector240, vector241, vector242, vector243
.long vector244, vector245, vector246, vector247
.long vector248, vector249, vector250, vector251
.long vector252, vector253, vector254, vector255
.long vector256, vector257, vector258, vector259
.long vector260, vector261, vector262, vector263
.long vector264, vector265, vector266, vector267
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216, vector217, vector218, vector219
.weak vector220, vector221, vector222, vector223
.weak vector224, vector225, vector226, vector227
.weak vector228, vector229, vector230, vector231
.weak vector232, vector233, vector234, vector235
.weak vector236, vector237, vector238, vector239
.weak vector240, vector241, vector242, vector243
.weak vector244, vector245, vector246, vector247
.weak vector248, vector249, vector250, vector251
.weak vector252, vector253, vector254, vector255
.weak vector256, vector257, vector258, vector259
.weak vector260, vector261, vector262, vector263
.weak vector264, vector265, vector266, vector267
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
vector217:
vector218:
vector219:
vector220:
vector221:
vector222:
vector223:
vector224:
vector225:
vector226:
vector227:
vector228:
vector229:
vector230:
vector231:
vector232:
vector233:
vector234:
vector235:
vector236:
vector237:
vector238:
vector239:
vector240:
vector241:
vector242:
vector243:
vector244:
vector245:
vector246:
vector247:
vector248:
vector249:
vector250:
vector251:
vector252:
vector253:
vector254:
vector255:
vector256:
vector257:
vector258:
vector259:
vector260:
vector261:
vector262:
vector263:
vector264:
vector265:
vector266:
vector267:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,735
|
Firmware/IAR/os/ports/GCC/PPC/SPC563Mxx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC563Mxx/bam.s
* @brief SPC563Mxx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
#if PPC_USE_VLE
.long 0x015A0000
#else
.long 0x005A0000
#endif
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 5,903
|
Firmware/IAR/os/ports/GCC/PPC/SPC563Mxx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC563Mxx/core.s
* @brief e200z3 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_UCLE 0x04000000
#define MSR_SPE 0x02000000
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_FP 0x00002000
#define MSR_ME 0x00001000
#define MSR_FE0 0x00000800
#define MSR_DE 0x00000200
#define MSR_FE1 0x00000100
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
/* IVORs initialization.*/
lis %r3, _unhandled_exception@h
ori %r3, %r3, _unhandled_exception@l
mtspr 400, %r3 /* IVOR0-15 */
mtspr 401, %r3
mtspr 402, %r3
mtspr 403, %r3
mtspr 404, %r3
mtspr 405, %r3
mtspr 406, %r3
mtspr 407, %r3
mtspr 408, %r3
mtspr 409, %r3
mtspr 410, %r3
mtspr 411, %r3
mtspr 412, %r3
mtspr 413, %r3
mtspr 414, %r3
mtspr 415, %r3
mtspr 528, %r3 /* IVOR32-34 */
mtspr 529, %r3
mtspr 530, %r3
blr
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _unhandled_exception
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 17,561
|
Firmware/IAR/os/ports/GCC/PPC/SPC563Mxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC563Mxx/vectors.s
* @brief SPC563Mxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216, vector217, vector218, vector219
.long vector220, vector221, vector222, vector223
.long vector224, vector225, vector226, vector227
.long vector228, vector229, vector230, vector231
.long vector232, vector233, vector234, vector235
.long vector236, vector237, vector238, vector239
.long vector240, vector241, vector242, vector243
.long vector244, vector245, vector246, vector247
.long vector248, vector249, vector250, vector251
.long vector252, vector253, vector254, vector255
.long vector256, vector257, vector258, vector259
.long vector260, vector261, vector262, vector263
.long vector264, vector265, vector266, vector267
.long vector268, vector269, vector270, vector271
.long vector272, vector273, vector274, vector275
.long vector276, vector277, vector278, vector279
.long vector280, vector281, vector282, vector283
.long vector284, vector285, vector286, vector287
.long vector288, vector289, vector290, vector291
.long vector292, vector293, vector294, vector295
.long vector296, vector297, vector298, vector299
.long vector300, vector301, vector302, vector303
.long vector304, vector305, vector306, vector307
.long vector308, vector309, vector310, vector311
.long vector312, vector313, vector314, vector315
.long vector316, vector317, vector318, vector319
.long vector320, vector321, vector322, vector323
.long vector324, vector325, vector326, vector327
.long vector328, vector329, vector330, vector331
.long vector332, vector333, vector334, vector335
.long vector336, vector337, vector338, vector339
.long vector340, vector341, vector342, vector343
.long vector344, vector345, vector346, vector347
.long vector348, vector349, vector350, vector351
.long vector352, vector353, vector354, vector355
.long vector356, vector357, vector358, vector359
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216, vector217, vector218, vector219
.weak vector220, vector221, vector222, vector223
.weak vector224, vector225, vector226, vector227
.weak vector228, vector229, vector230, vector231
.weak vector232, vector233, vector234, vector235
.weak vector236, vector237, vector238, vector239
.weak vector240, vector241, vector242, vector243
.weak vector244, vector245, vector246, vector247
.weak vector248, vector249, vector250, vector251
.weak vector252, vector253, vector254, vector255
.weak vector256, vector257, vector258, vector259
.weak vector260, vector261, vector262, vector263
.weak vector264, vector265, vector266, vector267
.weak vector268, vector269, vector270, vector271
.weak vector272, vector273, vector274, vector275
.weak vector276, vector277, vector278, vector279
.weak vector280, vector281, vector282, vector283
.weak vector284, vector285, vector286, vector287
.weak vector288, vector289, vector290, vector291
.weak vector292, vector293, vector294, vector295
.weak vector296, vector297, vector298, vector299
.weak vector300, vector301, vector302, vector303
.weak vector304, vector305, vector306, vector307
.weak vector308, vector309, vector310, vector311
.weak vector312, vector313, vector314, vector315
.weak vector316, vector317, vector318, vector319
.weak vector320, vector321, vector322, vector323
.weak vector324, vector325, vector326, vector327
.weak vector328, vector329, vector330, vector331
.weak vector332, vector333, vector334, vector335
.weak vector336, vector337, vector338, vector339
.weak vector340, vector341, vector342, vector343
.weak vector344, vector345, vector346, vector347
.weak vector348, vector349, vector350, vector351
.weak vector352, vector353, vector354, vector355
.weak vector356, vector357, vector358, vector359
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
vector217:
vector218:
vector219:
vector220:
vector221:
vector222:
vector223:
vector224:
vector225:
vector226:
vector227:
vector228:
vector229:
vector230:
vector231:
vector232:
vector233:
vector234:
vector235:
vector236:
vector237:
vector238:
vector239:
vector240:
vector241:
vector242:
vector243:
vector244:
vector245:
vector246:
vector247:
vector248:
vector249:
vector250:
vector251:
vector252:
vector253:
vector254:
vector255:
vector256:
vector257:
vector258:
vector259:
vector260:
vector261:
vector262:
vector263:
vector264:
vector265:
vector266:
vector267:
vector268:
vector269:
vector270:
vector271:
vector272:
vector273:
vector274:
vector275:
vector276:
vector277:
vector278:
vector279:
vector280:
vector281:
vector282:
vector283:
vector284:
vector285:
vector286:
vector287:
vector288:
vector289:
vector290:
vector291:
vector292:
vector293:
vector294:
vector295:
vector296:
vector297:
vector298:
vector299:
vector300:
vector301:
vector302:
vector303:
vector304:
vector305:
vector306:
vector307:
vector308:
vector309:
vector310:
vector311:
vector312:
vector313:
vector314:
vector315:
vector316:
vector317:
vector318:
vector319:
vector320:
vector321:
vector322:
vector323:
vector324:
vector325:
vector326:
vector327:
vector328:
vector329:
vector330:
vector331:
vector332:
vector333:
vector334:
vector335:
vector336:
vector337:
vector338:
vector339:
vector340:
vector341:
vector342:
vector343:
vector344:
vector345:
vector346:
vector347:
vector348:
vector349:
vector350:
vector351:
vector352:
vector353:
vector354:
vector355:
vector356:
vector357:
vector358:
vector359:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,677
|
Firmware/IAR/os/ports/GCC/PPC/SPC560BCxx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560BCxx/bam.s
* @brief SPC560BCxx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
.long 0x015A0000
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 6,096
|
Firmware/IAR/os/ports/GCC/PPC/SPC560BCxx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560BCxx/core.s
* @brief e200z0 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_ME 0x00001000
#define MSR_DE 0x00000200
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
blr
.section .ivors, "ax"
.globl IVORS
IVORS:
IVOR0: b IVOR0
.align 4
IVOR1: b _IVOR1
.align 4
IVOR2: b _IVOR2
.align 4
IVOR3: b _IVOR3
.align 4
IVOR4: b _IVOR4
.align 4
IVOR5: b _IVOR5
.align 4
IVOR6: b _IVOR6
.align 4
IVOR7: b _IVOR7
.align 4
IVOR8: b _IVOR8
.align 4
IVOR9: b _IVOR9
.align 4
IVOR10: b _IVOR10
.align 4
IVOR11: b _IVOR11
.align 4
IVOR12: b _IVOR12
.align 4
IVOR13: b _IVOR13
.align 4
IVOR14: b _IVOR14
.align 4
IVOR15: b _IVOR15
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
.weak _unhandled_exception
_IVOR0:
_IVOR1:
_IVOR2:
_IVOR3:
_IVOR5:
_IVOR6:
_IVOR7:
_IVOR8:
_IVOR9:
_IVOR11:
_IVOR12:
_IVOR13:
_IVOR14:
_IVOR15:
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 11,298
|
Firmware/IAR/os/ports/GCC/PPC/SPC560BCxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560BCxx/vectors.s
* @brief SPC560BCxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,675
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Bxx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Bxx/bam.s
* @brief SPC560Bxx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
.long 0x015A0000
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 6,095
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Bxx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Bxx/core.s
* @brief e200z0 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_ME 0x00001000
#define MSR_DE 0x00000200
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
blr
.section .ivors, "ax"
.globl IVORS
IVORS:
IVOR0: b IVOR0
.align 4
IVOR1: b _IVOR1
.align 4
IVOR2: b _IVOR2
.align 4
IVOR3: b _IVOR3
.align 4
IVOR4: b _IVOR4
.align 4
IVOR5: b _IVOR5
.align 4
IVOR6: b _IVOR6
.align 4
IVOR7: b _IVOR7
.align 4
IVOR8: b _IVOR8
.align 4
IVOR9: b _IVOR9
.align 4
IVOR10: b _IVOR10
.align 4
IVOR11: b _IVOR11
.align 4
IVOR12: b _IVOR12
.align 4
IVOR13: b _IVOR13
.align 4
IVOR14: b _IVOR14
.align 4
IVOR15: b _IVOR15
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
.weak _unhandled_exception
_IVOR0:
_IVOR1:
_IVOR2:
_IVOR3:
_IVOR5:
_IVOR6:
_IVOR7:
_IVOR8:
_IVOR9:
_IVOR11:
_IVOR12:
_IVOR13:
_IVOR14:
_IVOR15:
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 12,039
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Bxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Bxx/vectors.s
* @brief SPC560Bxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216, vector217, vector218, vector219
.long vector220, vector221, vector222, vector223
.long vector224, vector225, vector226, vector227
.long vector228, vector229, vector230, vector231
.long vector232, vector233
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216, vector217, vector218, vector219
.weak vector220, vector221, vector222, vector223
.weak vector224, vector225, vector226, vector227
.weak vector228, vector229, vector230, vector231
.weak vector232, vector233
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
vector217:
vector218:
vector219:
vector220:
vector221:
vector222:
vector223:
vector224:
vector225:
vector226:
vector227:
vector228:
vector229:
vector230:
vector231:
vector232:
vector233:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,735
|
Firmware/IAR/os/ports/GCC/PPC/SPC56ELxx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC56ELxx/bam.s
* @brief SPC56ELxx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
#if PPC_USE_VLE
.long 0x015A0000
#else
.long 0x005A0000
#endif
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 18,932
|
Firmware/IAR/os/ports/GCC/PPC/SPC56ELxx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC56ELxx/core.s
* @brief e200z4 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name MASx registers definitions
* @{
*/
#define MAS0_TBLMAS_TBL 0x10000000
#define MAS0_ESEL_MASK 0x000F0000
#define MAS0_ESEL(n) ((n) << 16)
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID_MASK 0x00FF0000
#define MAS1_TS 0x00001000
#define MAS1_TSISE_MASK 0x00000F80
#define MAS1_TSISE_1K 0x00000000
#define MAS1_TSISE_2K 0x00000080
#define MAS1_TSISE_4K 0x00000100
#define MAS1_TSISE_8K 0x00000180
#define MAS1_TSISE_16K 0x00000200
#define MAS1_TSISE_32K 0x00000280
#define MAS1_TSISE_64K 0x00000300
#define MAS1_TSISE_128K 0x00000380
#define MAS1_TSISE_256K 0x00000400
#define MAS1_TSISE_512K 0x00000480
#define MAS1_TSISE_1M 0x00000500
#define MAS1_TSISE_2M 0x00000580
#define MAS1_TSISE_4M 0x00000600
#define MAS1_TSISE_8M 0x00000680
#define MAS1_TSISE_16M 0x00000700
#define MAS1_TSISE_32M 0x00000780
#define MAS1_TSISE_64M 0x00000800
#define MAS1_TSISE_128M 0x00000880
#define MAS1_TSISE_256M 0x00000900
#define MAS1_TSISE_512M 0x00000980
#define MAS1_TSISE_1G 0x00000A00
#define MAS1_TSISE_2G 0x00000A80
#define MAS1_TSISE_4G 0x00000B00
#define MAS2_EPN_MASK 0xFFFFFC00
#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
#define MAS2_EBOOK 0x00000000
#define MAS2_VLE 0x00000020
#define MAS2_W 0x00000010
#define MAS2_I 0x00000008
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS3_RPN_MASK 0xFFFFFC00
#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
#define MAS3_U0 0x00000200
#define MAS3_U1 0x00000100
#define MAS3_U2 0x00000080
#define MAS3_U3 0x00000040
#define MAS3_UX 0x00000020
#define MAS3_SX 0x00000010
#define MAS3_UW 0x00000008
#define MAS3_SW 0x00000004
#define MAS3_UR 0x00000002
#define MAS3_SR 0x00000001
/** @} */
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BPRED_MASK 0x00000006
#define BUCSR_BPRED_0 0x00000000
#define BUCSR_BPRED_1 0x00000002
#define BUCSR_BPRED_2 0x00000004
#define BUCSR_BPRED_3 0x00000006
#define BUCSR_BALLOC_MASK 0x00000030
#define BUCSR_BALLOC_0 0x00000000
#define BUCSR_BALLOC_1 0x00000010
#define BUCSR_BALLOC_2 0x00000020
#define BUCSR_BALLOC_3 0x00000030
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name LICSR1 registers definitions
* @{
*/
#define LICSR1_ICE 0x00000001
#define LICSR1_ICINV 0x00000002
#define LICSR1_ICORG 0x00000010
/** @} */
/**
* @name TLB default settings
* @{
*/
#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
MAS3_UR | MAS3_SR)
#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_128K)
#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
MAS3_UR | MAS3_SR)
#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name LICSR1 default settings
* @{
*/
#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_UCLE 0x04000000
#define MSR_SPE 0x02000000
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_FP 0x00002000
#define MSR_ME 0x00001000
#define MSR_FE0 0x00000800
#define MSR_DE 0x00000200
#define MSR_FE1 0x00000100
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
_ramcode:
tlbwe
isync
blr
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* Invalidating all TLBs except TLB0.
*/
lis %r3, 0
mtspr 625, %r3 /* MAS1 */
mtspr 626, %r3 /* MAS2 */
mtspr 627, %r3 /* MAS3 */
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
/*
* TLB1 allocated to internal RAM.
*/
lis %r3, TLB1_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB1_MAS1@h
ori %r3, %r3, TLB1_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB1_MAS2@h
ori %r3, %r3, TLB1_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB1_MAS3@h
ori %r3, %r3, TLB1_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB2 allocated to internal Peripherals Bridge A.
*/
lis %r3, TLB2_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB2_MAS1@h
ori %r3, %r3, TLB2_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB2_MAS2@h
ori %r3, %r3, TLB2_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB2_MAS3@h
ori %r3, %r3, TLB2_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB3 allocated to internal Peripherals Bridge B.
*/
lis %r3, TLB3_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB3_MAS1@h
ori %r3, %r3, TLB3_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB3_MAS2@h
ori %r3, %r3, TLB3_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB3_MAS3@h
ori %r3, %r3, TLB3_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB4 allocated to on-platform peripherals.
*/
lis %r3, TLB4_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB4_MAS1@h
ori %r3, %r3, TLB4_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB4_MAS2@h
ori %r3, %r3, TLB4_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB4_MAS3@h
ori %r3, %r3, TLB4_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB5 allocated to on-platform peripherals.
*/
lis %r3, TLB5_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB5_MAS1@h
ori %r3, %r3, TLB5_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB5_MAS2@h
ori %r3, %r3, TLB5_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB5_MAS3@h
ori %r3, %r3, TLB5_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* Special function registers clearing, required in order to avoid
* possible problems with lockstep mode.
*/
mtcrf 0xFF, %r31
mtspr 9, %r31 /* CTR */
mtspr 22, %r31 /* DEC */
mtspr 26, %r31 /* SRR0-1 */
mtspr 27, %r31
mtspr 54, %r31 /* DECAR */
mtspr 58, %r31 /* CSRR0-1 */
mtspr 59, %r31
mtspr 61, %r31 /* DEAR */
mtspr 256, %r31 /* USPRG0 */
mtspr 272, %r31 /* SPRG1-7 */
mtspr 273, %r31
mtspr 274, %r31
mtspr 275, %r31
mtspr 276, %r31
mtspr 277, %r31
mtspr 278, %r31
mtspr 279, %r31
mtspr 285, %r31 /* TBU */
mtspr 284, %r31 /* TBL */
#if 0
mtspr 318, %r31 /* DVC1-2 */
mtspr 319, %r31
#endif
mtspr 562, %r31 /* DBCNT */
mtspr 570, %r31 /* MCSRR0 */
mtspr 571, %r31 /* MCSRR1 */
mtspr 604, %r31 /* SPRG8-9 */
mtspr 605, %r31
/*
* *Finally* the TLB0 is re-allocated to flash, note, the final phase
* is executed from RAM.
*/
lis %r3, TLB0_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB0_MAS1@h
ori %r3, %r3, TLB0_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB0_MAS2@h
ori %r3, %r3, TLB0_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB0_MAS3@h
ori %r3, %r3, TLB0_MAS3@l
mtspr 627, %r3 /* MAS3 */
mflr %r4
lis %r6, _ramcode@h
ori %r6, %r6, _ramcode@l
lis %r7, 0x40010000@h
mtctr %r7
lwz %r3, 0(%r6)
stw %r3, 0(%r7)
lwz %r3, 4(%r6)
stw %r3, 4(%r7)
lwz %r3, 8(%r6)
stw %r3, 8(%r7)
bctrl
mtlr %r4
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
/*
* Cache invalidated and then enabled.
*/
li %r3, LICSR1_ICINV
mtspr 1011, %r3 /* LICSR1 */
.inv: mfspr %r3, 1011 /* LICSR1 */
andi. %r3, %r3, LICSR1_ICINV
bne .inv
lis %r3, LICSR1_DEFAULT@h
ori %r3, %r3, LICSR1_DEFAULT@l
mtspr 1011, %r3 /* LICSR1 */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
/* IVORs initialization.*/
lis %r3, _unhandled_exception@h
ori %r3, %r3, _unhandled_exception@l
mtspr 400, %r3 /* IVOR0-15 */
mtspr 401, %r3
mtspr 402, %r3
mtspr 403, %r3
mtspr 404, %r3
mtspr 405, %r3
mtspr 406, %r3
mtspr 407, %r3
mtspr 408, %r3
mtspr 409, %r3
mtspr 410, %r3
mtspr 411, %r3
mtspr 412, %r3
mtspr 413, %r3
mtspr 414, %r3
mtspr 415, %r3
mtspr 528, %r3 /* IVOR32-34 */
mtspr 529, %r3
mtspr 530, %r3
blr
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _unhandled_exception
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 12,985
|
Firmware/IAR/os/ports/GCC/PPC/SPC56ELxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC56ELxx/vectors.s
* @brief SPC56ELxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216, vector217, vector218, vector219
.long vector220, vector221, vector222, vector223
.long vector224, vector225, vector226, vector227
.long vector228, vector229, vector230, vector231
.long vector232, vector233, vector234, vector235
.long vector236, vector237, vector238, vector239
.long vector240, vector241, vector242, vector243
.long vector244, vector245, vector246, vector247
.long vector248, vector249, vector250, vector251
.long vector252, vector253, vector254, vector255
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216, vector217, vector218, vector219
.weak vector220, vector221, vector222, vector223
.weak vector224, vector225, vector226, vector227
.weak vector228, vector229, vector230, vector231
.weak vector232, vector233, vector234, vector235
.weak vector236, vector237, vector238, vector239
.weak vector240, vector241, vector242, vector243
.weak vector244, vector245, vector246, vector247
.weak vector248, vector249, vector250, vector251
.weak vector252, vector253, vector254, vector255
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
vector217:
vector218:
vector219:
vector220:
vector221:
vector222:
vector223:
vector224:
vector225:
vector226:
vector227:
vector228:
vector229:
vector230:
vector231:
vector232:
vector233:
vector234:
vector235:
vector236:
vector237:
vector238:
vector239:
vector240:
vector241:
vector242:
vector243:
vector244:
vector245:
vector246:
vector247:
vector248:
vector249:
vector250:
vector251:
vector252:
vector253:
vector254:
vector255:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,675
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Dxx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Dxx/bam.s
* @brief SPC560Dxx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
.long 0x015A0000
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 6,095
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Dxx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Dxx/core.s
* @brief e200z0 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_ME 0x00001000
#define MSR_DE 0x00000200
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
blr
.section .ivors, "ax"
.globl IVORS
IVORS:
IVOR0: b IVOR0
.align 4
IVOR1: b _IVOR1
.align 4
IVOR2: b _IVOR2
.align 4
IVOR3: b _IVOR3
.align 4
IVOR4: b _IVOR4
.align 4
IVOR5: b _IVOR5
.align 4
IVOR6: b _IVOR6
.align 4
IVOR7: b _IVOR7
.align 4
IVOR8: b _IVOR8
.align 4
IVOR9: b _IVOR9
.align 4
IVOR10: b _IVOR10
.align 4
IVOR11: b _IVOR11
.align 4
IVOR12: b _IVOR12
.align 4
IVOR13: b _IVOR13
.align 4
IVOR14: b _IVOR14
.align 4
IVOR15: b _IVOR15
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
.weak _unhandled_exception
_IVOR0:
_IVOR1:
_IVOR2:
_IVOR3:
_IVOR5:
_IVOR6:
_IVOR7:
_IVOR8:
_IVOR9:
_IVOR11:
_IVOR12:
_IVOR13:
_IVOR14:
_IVOR15:
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 8,550
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Dxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Dxx/vectors.s
* @brief SPC560Dxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,735
|
Firmware/IAR/os/ports/GCC/PPC/SPC564Axx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC564Axx/bam.s
* @brief SPC564Axx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
#if PPC_USE_VLE
.long 0x015A0000
#else
.long 0x005A0000
#endif
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 16,756
|
Firmware/IAR/os/ports/GCC/PPC/SPC564Axx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC564Axx/core.s
* @brief e200z4 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name MASx registers definitions
* @{
*/
#define MAS0_TBLMAS_TBL 0x10000000
#define MAS0_ESEL_MASK 0x000F0000
#define MAS0_ESEL(n) ((n) << 16)
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID_MASK 0x00FF0000
#define MAS1_TS 0x00001000
#define MAS1_TSISE_MASK 0x00000F80
#define MAS1_TSISE_1K 0x00000000
#define MAS1_TSISE_2K 0x00000080
#define MAS1_TSISE_4K 0x00000100
#define MAS1_TSISE_8K 0x00000180
#define MAS1_TSISE_16K 0x00000200
#define MAS1_TSISE_32K 0x00000280
#define MAS1_TSISE_64K 0x00000300
#define MAS1_TSISE_128K 0x00000380
#define MAS1_TSISE_256K 0x00000400
#define MAS1_TSISE_512K 0x00000480
#define MAS1_TSISE_1M 0x00000500
#define MAS1_TSISE_2M 0x00000580
#define MAS1_TSISE_4M 0x00000600
#define MAS1_TSISE_8M 0x00000680
#define MAS1_TSISE_16M 0x00000700
#define MAS1_TSISE_32M 0x00000780
#define MAS1_TSISE_64M 0x00000800
#define MAS1_TSISE_128M 0x00000880
#define MAS1_TSISE_256M 0x00000900
#define MAS1_TSISE_512M 0x00000980
#define MAS1_TSISE_1G 0x00000A00
#define MAS1_TSISE_2G 0x00000A80
#define MAS1_TSISE_4G 0x00000B00
#define MAS2_EPN_MASK 0xFFFFFC00
#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
#define MAS2_EBOOK 0x00000000
#define MAS2_VLE 0x00000020
#define MAS2_W 0x00000010
#define MAS2_I 0x00000008
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS3_RPN_MASK 0xFFFFFC00
#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
#define MAS3_U0 0x00000200
#define MAS3_U1 0x00000100
#define MAS3_U2 0x00000080
#define MAS3_U3 0x00000040
#define MAS3_UX 0x00000020
#define MAS3_SX 0x00000010
#define MAS3_UW 0x00000008
#define MAS3_SW 0x00000004
#define MAS3_UR 0x00000002
#define MAS3_SR 0x00000001
/** @} */
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BPRED_MASK 0x00000006
#define BUCSR_BPRED_0 0x00000000
#define BUCSR_BPRED_1 0x00000002
#define BUCSR_BPRED_2 0x00000004
#define BUCSR_BPRED_3 0x00000006
#define BUCSR_BALLOC_MASK 0x00000030
#define BUCSR_BALLOC_0 0x00000000
#define BUCSR_BALLOC_1 0x00000010
#define BUCSR_BALLOC_2 0x00000020
#define BUCSR_BALLOC_3 0x00000030
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name TLB default settings
* @{
*/
#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
MAS3_UR | MAS3_SR)
#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
MAS3_UR | MAS3_SR)
#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \
MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
/** @} */
/**
* @name LICSR1 registers definitions
* @{
*/
#define LICSR1_ICE 0x00000001
#define LICSR1_ICINV 0x00000002
#define LICSR1_ICORG 0x00000010
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name LICSR1 default settings
* @{
*/
#define LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_UCLE 0x04000000
#define MSR_SPE 0x02000000
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_FP 0x00002000
#define MSR_ME 0x00001000
#define MSR_FE0 0x00000800
#define MSR_DE 0x00000200
#define MSR_FE1 0x00000100
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
_ramcode:
tlbwe
isync
blr
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* Invalidating all TLBs except TLB1.
*/
lis %r3, 0
mtspr 625, %r3 /* MAS1 */
mtspr 626, %r3 /* MAS2 */
mtspr 627, %r3 /* MAS3 */
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
mtspr 624, %r3 /* MAS0 */
tlbwe
/*
* TLB0 allocated to internal RAM.
*/
lis %r3, TLB0_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB0_MAS1@h
ori %r3, %r3, TLB0_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB0_MAS2@h
ori %r3, %r3, TLB0_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB0_MAS3@h
ori %r3, %r3, TLB0_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB2 allocated to internal Peripherals Bridge A.
*/
lis %r3, TLB2_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB2_MAS1@h
ori %r3, %r3, TLB2_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB2_MAS2@h
ori %r3, %r3, TLB2_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB2_MAS3@h
ori %r3, %r3, TLB2_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB3 allocated to internal Peripherals Bridge B.
*/
lis %r3, TLB3_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB3_MAS1@h
ori %r3, %r3, TLB3_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB3_MAS2@h
ori %r3, %r3, TLB3_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB3_MAS3@h
ori %r3, %r3, TLB3_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* TLB4 allocated to on-platform peripherals.
*/
lis %r3, TLB4_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB4_MAS1@h
ori %r3, %r3, TLB4_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB4_MAS2@h
ori %r3, %r3, TLB4_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB4_MAS3@h
ori %r3, %r3, TLB4_MAS3@l
mtspr 627, %r3 /* MAS3 */
tlbwe
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* *Finally* the TLB1 is re-allocated to flash, note, the final phase
* is executed from RAM.
*/
lis %r3, TLB1_MAS0@h
mtspr 624, %r3 /* MAS0 */
lis %r3, TLB1_MAS1@h
ori %r3, %r3, TLB1_MAS1@l
mtspr 625, %r3 /* MAS1 */
lis %r3, TLB1_MAS2@h
ori %r3, %r3, TLB1_MAS2@l
mtspr 626, %r3 /* MAS2 */
lis %r3, TLB1_MAS3@h
ori %r3, %r3, TLB1_MAS3@l
mtspr 627, %r3 /* MAS3 */
mflr %r4
lis %r6, _ramcode@h
ori %r6, %r6, _ramcode@l
lis %r7, 0x40010000@h
mtctr %r7
lwz %r3, 0(%r6)
stw %r3, 0(%r7)
lwz %r3, 4(%r6)
stw %r3, 4(%r7)
lwz %r3, 8(%r6)
stw %r3, 8(%r7)
bctrl
mtlr %r4
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
/*
* Cache invalidated and then enabled.
*/
li %r3, LICSR1_ICINV
mtspr 1011, %r3 /* LICSR1 */
.inv: mfspr %r3, 1011 /* LICSR1 */
andi. %r3, %r3, LICSR1_ICINV
bne .inv
lis %r3, LICSR1_DEFAULT@h
ori %r3, %r3, LICSR1_DEFAULT@l
mtspr 1011, %r3 /* LICSR1 */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
/* IVORs initialization.*/
lis %r3, _unhandled_exception@h
ori %r3, %r3, _unhandled_exception@l
mtspr 400, %r3 /* IVOR0-15 */
mtspr 401, %r3
mtspr 402, %r3
mtspr 403, %r3
mtspr 404, %r3
mtspr 405, %r3
mtspr 406, %r3
mtspr 407, %r3
mtspr 408, %r3
mtspr 409, %r3
mtspr 410, %r3
mtspr 411, %r3
mtspr 412, %r3
mtspr 413, %r3
mtspr 414, %r3
mtspr 415, %r3
mtspr 528, %r3 /* IVOR32-34 */
mtspr 529, %r3
mtspr 530, %r3
blr
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _unhandled_exception
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 23,123
|
Firmware/IAR/os/ports/GCC/PPC/SPC564Axx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC564Axx/vectors.s
* @brief SPC564Axx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216, vector217, vector218, vector219
.long vector220, vector221, vector222, vector223
.long vector224, vector225, vector226, vector227
.long vector228, vector229, vector230, vector231
.long vector232, vector233, vector234, vector235
.long vector236, vector237, vector238, vector239
.long vector240, vector241, vector242, vector243
.long vector244, vector245, vector246, vector247
.long vector248, vector249, vector250, vector251
.long vector252, vector253, vector254, vector255
.long vector256, vector257, vector258, vector259
.long vector260, vector261, vector262, vector263
.long vector264, vector265, vector266, vector267
.long vector268, vector269, vector270, vector271
.long vector272, vector273, vector274, vector275
.long vector276, vector277, vector278, vector279
.long vector280, vector281, vector282, vector283
.long vector284, vector285, vector286, vector287
.long vector288, vector289, vector290, vector291
.long vector292, vector293, vector294, vector295
.long vector296, vector297, vector298, vector299
.long vector300, vector301, vector302, vector303
.long vector304, vector305, vector306, vector307
.long vector308, vector309, vector310, vector311
.long vector312, vector313, vector314, vector315
.long vector316, vector317, vector318, vector319
.long vector320, vector321, vector322, vector323
.long vector324, vector325, vector326, vector327
.long vector328, vector329, vector330, vector331
.long vector332, vector333, vector334, vector335
.long vector336, vector337, vector338, vector339
.long vector340, vector341, vector342, vector343
.long vector344, vector345, vector346, vector347
.long vector348, vector349, vector350, vector351
.long vector352, vector353, vector354, vector355
.long vector356, vector357, vector358, vector359
.long vector360, vector361, vector362, vector363
.long vector364, vector365, vector366, vector367
.long vector368, vector369, vector370, vector371
.long vector372, vector373, vector374, vector375
.long vector376, vector377, vector378, vector379
.long vector380, vector381, vector382, vector383
.long vector384, vector385, vector386, vector387
.long vector388, vector389, vector390, vector391
.long vector392, vector393, vector394, vector395
.long vector396, vector397, vector398, vector399
.long vector400, vector401, vector402, vector403
.long vector404, vector405, vector406, vector407
.long vector408, vector409, vector410, vector411
.long vector412, vector413, vector414, vector415
.long vector416, vector417, vector418, vector419
.long vector420, vector421, vector422, vector423
.long vector424, vector425, vector426, vector427
.long vector428, vector429, vector430, vector431
.long vector432, vector433, vector434, vector435
.long vector436, vector437, vector438, vector439
.long vector440, vector441, vector442, vector443
.long vector444, vector445, vector446, vector447
.long vector448, vector449, vector450, vector451
.long vector452, vector453, vector454, vector455
.long vector456, vector457, vector458, vector459
.long vector460, vector461, vector462, vector463
.long vector464, vector465, vector466, vector467
.long vector468, vector469, vector470, vector471
.long vector472, vector473, vector474, vector475
.long vector476, vector477, vector478, vector479
.long vector480, vector481, vector482, vector483
.long vector484, vector485
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216, vector217, vector218, vector219
.weak vector220, vector221, vector222, vector223
.weak vector224, vector225, vector226, vector227
.weak vector228, vector229, vector230, vector231
.weak vector232, vector233, vector234, vector235
.weak vector236, vector237, vector238, vector239
.weak vector240, vector241, vector242, vector243
.weak vector244, vector245, vector246, vector247
.weak vector248, vector249, vector250, vector251
.weak vector252, vector253, vector254, vector255
.weak vector256, vector257, vector258, vector259
.weak vector260, vector261, vector262, vector263
.weak vector264, vector265, vector266, vector267
.weak vector268, vector269, vector270, vector271
.weak vector272, vector273, vector274, vector275
.weak vector276, vector277, vector278, vector279
.weak vector280, vector281, vector282, vector283
.weak vector284, vector285, vector286, vector287
.weak vector288, vector289, vector290, vector291
.weak vector292, vector293, vector294, vector295
.weak vector296, vector297, vector298, vector299
.weak vector300, vector301, vector302, vector303
.weak vector304, vector305, vector306, vector307
.weak vector308, vector309, vector310, vector311
.weak vector312, vector313, vector314, vector315
.weak vector316, vector317, vector318, vector319
.weak vector320, vector321, vector322, vector323
.weak vector324, vector325, vector326, vector327
.weak vector328, vector329, vector330, vector331
.weak vector332, vector333, vector334, vector335
.weak vector336, vector337, vector338, vector339
.weak vector340, vector341, vector342, vector343
.weak vector344, vector345, vector346, vector347
.weak vector348, vector349, vector350, vector351
.weak vector352, vector353, vector354, vector355
.weak vector356, vector357, vector358, vector359
.weak vector360, vector361, vector362, vector363
.weak vector364, vector365, vector366, vector367
.weak vector368, vector369, vector370, vector371
.weak vector372, vector373, vector374, vector375
.weak vector376, vector377, vector378, vector379
.weak vector380, vector381, vector382, vector383
.weak vector384, vector385, vector386, vector387
.weak vector388, vector389, vector390, vector391
.weak vector392, vector393, vector394, vector395
.weak vector396, vector397, vector398, vector399
.weak vector400, vector401, vector402, vector403
.weak vector404, vector405, vector406, vector407
.weak vector408, vector409, vector410, vector411
.weak vector412, vector413, vector414, vector415
.weak vector416, vector417, vector418, vector419
.weak vector420, vector421, vector422, vector423
.weak vector424, vector425, vector426, vector427
.weak vector428, vector429, vector430, vector431
.weak vector432, vector433, vector434, vector435
.weak vector436, vector437, vector438, vector439
.weak vector440, vector441, vector442, vector443
.weak vector444, vector445, vector446, vector447
.weak vector448, vector449, vector450, vector451
.weak vector452, vector453, vector454, vector455
.weak vector456, vector457, vector458, vector459
.weak vector460, vector461, vector462, vector463
.weak vector464, vector465, vector466, vector467
.weak vector468, vector469, vector470, vector471
.weak vector472, vector473, vector474, vector475
.weak vector476, vector477, vector478, vector479
.weak vector480, vector481, vector482, vector483
.weak vector484, vector485
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
vector217:
vector218:
vector219:
vector220:
vector221:
vector222:
vector223:
vector224:
vector225:
vector226:
vector227:
vector228:
vector229:
vector230:
vector231:
vector232:
vector233:
vector234:
vector235:
vector236:
vector237:
vector238:
vector239:
vector240:
vector241:
vector242:
vector243:
vector244:
vector245:
vector246:
vector247:
vector248:
vector249:
vector250:
vector251:
vector252:
vector253:
vector254:
vector255:
vector256:
vector257:
vector258:
vector259:
vector260:
vector261:
vector262:
vector263:
vector264:
vector265:
vector266:
vector267:
vector268:
vector269:
vector270:
vector271:
vector272:
vector273:
vector274:
vector275:
vector276:
vector277:
vector278:
vector279:
vector280:
vector281:
vector282:
vector283:
vector284:
vector285:
vector286:
vector287:
vector288:
vector289:
vector290:
vector291:
vector292:
vector293:
vector294:
vector295:
vector296:
vector297:
vector298:
vector299:
vector300:
vector301:
vector302:
vector303:
vector304:
vector305:
vector306:
vector307:
vector308:
vector309:
vector310:
vector311:
vector312:
vector313:
vector314:
vector315:
vector316:
vector317:
vector318:
vector319:
vector320:
vector321:
vector322:
vector323:
vector324:
vector325:
vector326:
vector327:
vector328:
vector329:
vector330:
vector331:
vector332:
vector333:
vector334:
vector335:
vector336:
vector337:
vector338:
vector339:
vector340:
vector341:
vector342:
vector343:
vector344:
vector345:
vector346:
vector347:
vector348:
vector349:
vector350:
vector351:
vector352:
vector353:
vector354:
vector355:
vector356:
vector357:
vector358:
vector359:
vector360:
vector361:
vector362:
vector363:
vector364:
vector365:
vector366:
vector367:
vector368:
vector369:
vector370:
vector371:
vector372:
vector373:
vector374:
vector375:
vector376:
vector377:
vector378:
vector379:
vector380:
vector381:
vector382:
vector383:
vector384:
vector385:
vector386:
vector387:
vector388:
vector389:
vector390:
vector391:
vector392:
vector393:
vector394:
vector395:
vector396:
vector397:
vector398:
vector399:
vector400:
vector401:
vector402:
vector403:
vector404:
vector405:
vector406:
vector407:
vector408:
vector409:
vector410:
vector411:
vector412:
vector413:
vector414:
vector415:
vector416:
vector417:
vector418:
vector419:
vector420:
vector421:
vector422:
vector423:
vector424:
vector425:
vector426:
vector427:
vector428:
vector429:
vector430:
vector431:
vector432:
vector433:
vector434:
vector435:
vector436:
vector437:
vector438:
vector439:
vector440:
vector441:
vector442:
vector443:
vector444:
vector445:
vector446:
vector447:
vector448:
vector449:
vector450:
vector451:
vector452:
vector453:
vector454:
vector455:
vector456:
vector457:
vector458:
vector459:
vector460:
vector461:
vector462:
vector463:
vector464:
vector465:
vector466:
vector467:
vector468:
vector469:
vector470:
vector471:
vector472:
vector473:
vector474:
vector475:
vector476:
vector477:
vector478:
vector479:
vector480:
vector481:
vector482:
vector483:
vector484:
vector485:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 1,675
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Pxx/bam.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Pxx/bam.s
* @brief SPC560Pxx boot assistant record.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* BAM record.*/
.section .bam, "ax"
.long 0x015A0000
.long _reset_address
.align 2
.globl _reset_address
.type _reset_address, @function
_reset_address:
bl _coreinit
bl _ivinit
b _boot_address
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 6,095
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Pxx/core.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Pxx/core.s
* @brief e200z0 core configuration.
*
* @addtogroup PPC_CORE
* @{
*/
/**
* @name BUCSR registers definitions
* @{
*/
#define BUCSR_BPEN 0x00000001
#define BUCSR_BALLOC_BFI 0x00000200
/** @} */
/**
* @name BUCSR default settings
* @{
*/
#define BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
/** @} */
/**
* @name MSR register definitions
* @{
*/
#define MSR_WE 0x00040000
#define MSR_CE 0x00020000
#define MSR_EE 0x00008000
#define MSR_PR 0x00004000
#define MSR_ME 0x00001000
#define MSR_DE 0x00000200
#define MSR_IS 0x00000020
#define MSR_DS 0x00000010
#define MSR_RI 0x00000002
/** @} */
/**
* @name MSR default settings
* @{
*/
#define MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
/** @} */
#if !defined(__DOXYGEN__)
.section .coreinit, "ax"
.align 2
.globl _coreinit
.type _coreinit, @function
_coreinit:
/*
* RAM clearing, this device requires a write to all RAM location in
* order to initialize the ECC detection hardware, this is going to
* slow down the startup but there is no way around.
*/
xor %r0, %r0, %r0
xor %r1, %r1, %r1
xor %r2, %r2, %r2
xor %r3, %r3, %r3
xor %r4, %r4, %r4
xor %r5, %r5, %r5
xor %r6, %r6, %r6
xor %r7, %r7, %r7
xor %r8, %r8, %r8
xor %r9, %r9, %r9
xor %r10, %r10, %r10
xor %r11, %r11, %r11
xor %r12, %r12, %r12
xor %r13, %r13, %r13
xor %r14, %r14, %r14
xor %r15, %r15, %r15
xor %r16, %r16, %r16
xor %r17, %r17, %r17
xor %r18, %r18, %r18
xor %r19, %r19, %r19
xor %r20, %r20, %r20
xor %r21, %r21, %r21
xor %r22, %r22, %r22
xor %r23, %r23, %r23
xor %r24, %r24, %r24
xor %r25, %r25, %r25
xor %r26, %r26, %r26
xor %r27, %r27, %r27
xor %r28, %r28, %r28
xor %r29, %r29, %r29
xor %r30, %r30, %r30
xor %r31, %r31, %r31
lis %r4, __ram_start__@h
ori %r4, %r4, __ram_start__@l
lis %r5, __ram_end__@h
ori %r5, %r5, __ram_end__@l
.cleareccloop:
cmpl %cr0, %r4, %r5
bge %cr0, .cleareccend
stmw %r16, 0(%r4)
addi %r4, %r4, 64
b .cleareccloop
.cleareccend:
/*
* Branch prediction enabled.
*/
li %r3, BUCSR_DEFAULT
mtspr 1013, %r3 /* BUCSR */
blr
/*
* Exception vectors initialization.
*/
.global _ivinit
.type _ivinit, @function
_ivinit:
/* MSR initialization.*/
lis %r3, MSR_DEFAULT@h
ori %r3, %r3, MSR_DEFAULT@l
mtMSR %r3
/* IVPR initialization.*/
lis %r3, __ivpr_base__@h
ori %r3, %r3, __ivpr_base__@l
mtIVPR %r3
blr
.section .ivors, "ax"
.globl IVORS
IVORS:
IVOR0: b IVOR0
.align 4
IVOR1: b _IVOR1
.align 4
IVOR2: b _IVOR2
.align 4
IVOR3: b _IVOR3
.align 4
IVOR4: b _IVOR4
.align 4
IVOR5: b _IVOR5
.align 4
IVOR6: b _IVOR6
.align 4
IVOR7: b _IVOR7
.align 4
IVOR8: b _IVOR8
.align 4
IVOR9: b _IVOR9
.align 4
IVOR10: b _IVOR10
.align 4
IVOR11: b _IVOR11
.align 4
IVOR12: b _IVOR12
.align 4
IVOR13: b _IVOR13
.align 4
IVOR14: b _IVOR14
.align 4
IVOR15: b _IVOR15
.section .handlers, "ax"
/*
* Unhandled exceptions handler.
*/
.weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
.weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
.weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
.weak _unhandled_exception
_IVOR0:
_IVOR1:
_IVOR2:
_IVOR3:
_IVOR5:
_IVOR6:
_IVOR7:
_IVOR8:
_IVOR9:
_IVOR11:
_IVOR12:
_IVOR13:
_IVOR14:
_IVOR15:
.type _unhandled_exception, @function
_unhandled_exception:
b _unhandled_exception
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akpc806a/CAN_Logger
| 13,232
|
Firmware/IAR/os/ports/GCC/PPC/SPC560Pxx/vectors.s
|
/*
ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
2011,2012,2013 Giovanni Di Sirio.
This file is part of ChibiOS/RT.
ChibiOS/RT is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
ChibiOS/RT is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
---
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes ChibiOS/RT, without being obliged to provide
the source code for any proprietary components. See the file exception.txt
for full details of how and when the exception can be applied.
*/
/**
* @file SPC560Pxx/vectors.s
* @brief SPC560Pxx vectors table.
*
* @addtogroup PPC_CORE
* @{
*/
#if !defined(__DOXYGEN__)
/* Software vectors table. The vectors are accessed from the IVOR4
handler only. In order to declare an interrupt handler just create
a function withe the same name of a vector, the symbol will
override the weak symbol declared here.*/
.section .vectors, "ax"
.align 4
.globl _vectors
_vectors:
.long vector0, vector1, vector2, vector3
.long vector4, vector5, vector6, vector7
.long vector8, vector9, vector10, vector11
.long vector12, vector13, vector14, vector15
.long vector16, vector17, vector18, vector19
.long vector20, vector21, vector22, vector23
.long vector24, vector25, vector26, vector27
.long vector28, vector29, vector30, vector31
.long vector32, vector33, vector34, vector35
.long vector36, vector37, vector38, vector39
.long vector40, vector41, vector42, vector43
.long vector44, vector45, vector46, vector47
.long vector48, vector49, vector50, vector51
.long vector52, vector53, vector54, vector55
.long vector56, vector57, vector58, vector59
.long vector60, vector61, vector62, vector63
.long vector64, vector65, vector66, vector67
.long vector68, vector69, vector70, vector71
.long vector72, vector73, vector74, vector75
.long vector76, vector77, vector78, vector79
.long vector80, vector81, vector82, vector83
.long vector84, vector85, vector86, vector87
.long vector88, vector89, vector90, vector91
.long vector92, vector93, vector94, vector95
.long vector96, vector97, vector98, vector99
.long vector100, vector101, vector102, vector103
.long vector104, vector105, vector106, vector107
.long vector108, vector109, vector110, vector111
.long vector112, vector113, vector114, vector115
.long vector116, vector117, vector118, vector119
.long vector120, vector121, vector122, vector123
.long vector124, vector125, vector126, vector127
.long vector128, vector129, vector130, vector131
.long vector132, vector133, vector134, vector135
.long vector136, vector137, vector138, vector139
.long vector140, vector141, vector142, vector143
.long vector144, vector145, vector146, vector147
.long vector148, vector149, vector150, vector151
.long vector152, vector153, vector154, vector155
.long vector156, vector157, vector158, vector159
.long vector160, vector161, vector162, vector163
.long vector164, vector165, vector166, vector167
.long vector168, vector169, vector170, vector171
.long vector172, vector173, vector174, vector175
.long vector176, vector177, vector178, vector179
.long vector180, vector181, vector182, vector183
.long vector184, vector185, vector186, vector187
.long vector188, vector189, vector190, vector191
.long vector192, vector193, vector194, vector195
.long vector196, vector197, vector198, vector199
.long vector200, vector201, vector202, vector203
.long vector204, vector205, vector206, vector207
.long vector208, vector209, vector210, vector211
.long vector212, vector213, vector214, vector215
.long vector216, vector217, vector218, vector219
.long vector220, vector221, vector222, vector223
.long vector224, vector225, vector226, vector227
.long vector228, vector229, vector230, vector231
.long vector232, vector233, vector234, vector235
.long vector236, vector237, vector238, vector239
.long vector240, vector241, vector242, vector243
.long vector244, vector245, vector246, vector247
.long vector248, vector249, vector250, vector251
.long vector252, vector253, vector254, vector255
.long vector256, vector257, vector258, vector259
.long vector260
.text
.align 2
.weak vector0, vector1, vector2, vector3
.weak vector4, vector5, vector6, vector7
.weak vector8, vector9, vector10, vector11
.weak vector12, vector13, vector14, vector15
.weak vector16, vector17, vector18, vector19
.weak vector20, vector21, vector22, vector23
.weak vector24, vector25, vector26, vector27
.weak vector28, vector29, vector30, vector31
.weak vector32, vector33, vector34, vector35
.weak vector36, vector37, vector38, vector39
.weak vector40, vector41, vector42, vector43
.weak vector44, vector45, vector46, vector47
.weak vector48, vector49, vector50, vector51
.weak vector52, vector53, vector54, vector55
.weak vector56, vector57, vector58, vector59
.weak vector60, vector61, vector62, vector63
.weak vector64, vector65, vector66, vector67
.weak vector68, vector69, vector70, vector71
.weak vector72, vector73, vector74, vector75
.weak vector76, vector77, vector78, vector79
.weak vector80, vector81, vector82, vector83
.weak vector84, vector85, vector86, vector87
.weak vector88, vector89, vector90, vector91
.weak vector92, vector93, vector94, vector95
.weak vector96, vector97, vector98, vector99
.weak vector100, vector101, vector102, vector103
.weak vector104, vector105, vector106, vector107
.weak vector108, vector109, vector110, vector111
.weak vector112, vector113, vector114, vector115
.weak vector116, vector117, vector118, vector119
.weak vector120, vector121, vector122, vector123
.weak vector124, vector125, vector126, vector127
.weak vector128, vector129, vector130, vector131
.weak vector132, vector133, vector134, vector135
.weak vector136, vector137, vector138, vector139
.weak vector140, vector141, vector142, vector143
.weak vector144, vector145, vector146, vector147
.weak vector148, vector149, vector150, vector151
.weak vector152, vector153, vector154, vector155
.weak vector156, vector157, vector158, vector159
.weak vector160, vector161, vector162, vector163
.weak vector164, vector165, vector166, vector167
.weak vector168, vector169, vector170, vector171
.weak vector172, vector173, vector174, vector175
.weak vector176, vector177, vector178, vector179
.weak vector180, vector181, vector182, vector183
.weak vector184, vector185, vector186, vector187
.weak vector188, vector189, vector190, vector191
.weak vector192, vector193, vector194, vector195
.weak vector196, vector197, vector198, vector199
.weak vector200, vector201, vector202, vector203
.weak vector204, vector205, vector206, vector207
.weak vector208, vector209, vector210, vector211
.weak vector212, vector213, vector214, vector215
.weak vector216, vector217, vector218, vector219
.weak vector220, vector221, vector222, vector223
.weak vector224, vector225, vector226, vector227
.weak vector228, vector229, vector230, vector231
.weak vector232, vector233, vector234, vector235
.weak vector236, vector237, vector238, vector239
.weak vector240, vector241, vector242, vector243
.weak vector244, vector245, vector246, vector247
.weak vector248, vector249, vector250, vector251
.weak vector252, vector253, vector254, vector255
.weak vector256, vector257, vector258, vector259
.weak vector260
vector0:
vector1:
vector2:
vector3:
vector4:
vector5:
vector6:
vector7:
vector8:
vector9:
vector10:
vector11:
vector12:
vector13:
vector14:
vector15:
vector16:
vector17:
vector18:
vector19:
vector20:
vector21:
vector22:
vector23:
vector24:
vector25:
vector26:
vector27:
vector28:
vector29:
vector30:
vector31:
vector32:
vector33:
vector34:
vector35:
vector36:
vector37:
vector38:
vector39:
vector40:
vector41:
vector42:
vector43:
vector44:
vector45:
vector46:
vector47:
vector48:
vector49:
vector50:
vector51:
vector52:
vector53:
vector54:
vector55:
vector56:
vector57:
vector58:
vector59:
vector60:
vector61:
vector62:
vector63:
vector64:
vector65:
vector66:
vector67:
vector68:
vector69:
vector70:
vector71:
vector72:
vector73:
vector74:
vector75:
vector76:
vector77:
vector78:
vector79:
vector80:
vector81:
vector82:
vector83:
vector84:
vector85:
vector86:
vector87:
vector88:
vector89:
vector90:
vector91:
vector92:
vector93:
vector94:
vector95:
vector96:
vector97:
vector98:
vector99:
vector100:
vector101:
vector102:
vector103:
vector104:
vector105:
vector106:
vector107:
vector108:
vector109:
vector110:
vector111:
vector112:
vector113:
vector114:
vector115:
vector116:
vector117:
vector118:
vector119:
vector120:
vector121:
vector122:
vector123:
vector124:
vector125:
vector126:
vector127:
vector128:
vector129:
vector130:
vector131:
vector132:
vector133:
vector134:
vector135:
vector136:
vector137:
vector138:
vector139:
vector140:
vector141:
vector142:
vector143:
vector144:
vector145:
vector146:
vector147:
vector148:
vector149:
vector150:
vector151:
vector152:
vector153:
vector154:
vector155:
vector156:
vector157:
vector158:
vector159:
vector160:
vector161:
vector162:
vector163:
vector164:
vector165:
vector166:
vector167:
vector168:
vector169:
vector170:
vector171:
vector172:
vector173:
vector174:
vector175:
vector176:
vector177:
vector178:
vector179:
vector180:
vector181:
vector182:
vector183:
vector184:
vector185:
vector186:
vector187:
vector188:
vector189:
vector190:
vector191:
vector192:
vector193:
vector194:
vector195:
vector196:
vector197:
vector198:
vector199:
vector200:
vector201:
vector202:
vector203:
vector204:
vector205:
vector206:
vector207:
vector208:
vector209:
vector210:
vector211:
vector212:
vector213:
vector214:
vector215:
vector216:
vector217:
vector218:
vector219:
vector220:
vector221:
vector222:
vector223:
vector224:
vector225:
vector226:
vector227:
vector228:
vector229:
vector230:
vector231:
vector232:
vector233:
vector234:
vector235:
vector236:
vector237:
vector238:
vector239:
vector240:
vector241:
vector242:
vector243:
vector244:
vector245:
vector246:
vector247:
vector248:
vector249:
vector250:
vector251:
vector252:
vector253:
vector254:
vector255:
vector256:
vector257:
vector258:
vector259:
vector260:
.weak _unhandled_irq
.type _unhandled_irq, @function
_unhandled_irq:
b _unhandled_irq
#endif /* !defined(__DOXYGEN__) */
/** @} */
|
akrasuski1/usbasp-uart
| 4,431
|
firmware/tpi.S
|
/**
* \brief Size-optimized code for TPI
* \file tpi.s
* \author Sawomir Fra
*/
#include <avr/io.h>
#include "tpi_defs.h"
#define TPI_CLK_PORT PORTB
#define TPI_CLK_DDR DDRB
#define TPI_CLK_BIT 5
#define TPI_DATAOUT_PORT PORTB
#define TPI_DATAOUT_DDR DDRB
#define TPI_DATAOUT_BIT 3
#ifdef TPI_WITH_OPTO
# define TPI_DATAIN_PIN PINB
# define TPI_DATAIN_DDR DDRB
# define TPI_DATAIN_BIT 4
#else
# define TPI_DATAIN_PIN PINB
# define TPI_DATAIN_BIT 3
#endif
.comm tpi_dly_cnt, 2
/**
* TPI init
*/
.global tpi_init
tpi_init:
/* CLK <= out */
sbi _SFR_IO_ADDR(TPI_CLK_DDR), TPI_CLK_BIT
#ifdef TPI_WITH_OPTO
/* DATAIN <= pull-up */
cbi _SFR_IO_ADDR(TPI_DATAIN_DDR), TPI_DATAIN_BIT
sbi _SFR_IO_ADDR(TPI_DATAIN_PORT), TPI_DATAIN_BIT
/* DATAOUT <= high */
sbi _SFR_IO_ADDR(TPI_DATAOUT_DDR), TPI_DATAOUT_BIT
sbi _SFR_IO_ADDR(TPI_DATAOUT_PORT), TPI_DATAOUT_BIT
#else
/* DATA <= pull-up */
cbi _SFR_IO_ADDR(TPI_DATAOUT_DDR), TPI_DATAOUT_BIT
sbi _SFR_IO_ADDR(TPI_DATAOUT_PORT), TPI_DATAOUT_BIT
#endif
/* 32 bits */
ldi r21, 32
1:
rcall tpi_bit_h
dec r21
brne 1b
ret
/**
* Update PR
* in: r25:r24 <= PR
* lost: r18-r21,r24,r30-r31
*/
tpi_pr_update:
movw r20, r24
ldi r24, TPI_OP_SSTPR(0)
rcall tpi_send_byte
mov r24, r20
rcall tpi_send_byte
ldi r24, TPI_OP_SSTPR(1)
rcall tpi_send_byte
mov r24, r21
// rjmp tpi_send_byte
/**
* Send one byte
* in: r24 <= byte
* lost: r18-r19,r30-r31
*/
.global tpi_send_byte
tpi_send_byte:
/* start bit */
rcall tpi_bit_l
/* 8 data bits */
ldi r18, 8
ldi r19, 0
1:
// parity
eor r19, r24
// get bit, shift
bst r24, 0
lsr r24
// send
rcall tpi_bit
dec r18
brne 1b
/* parity bit */
bst r19, 0
rcall tpi_bit
/* 2 stop bits */
rcall tpi_bit_h
// rjmp tpi_bit_h
/**
* Exchange of one bit
* in: T <= bit_in
* out: T => bit_out
* lost: r30-r31
*/
tpi_bit_h:
set
tpi_bit:
/* TPIDATA = T */
#ifdef TPI_WITH_OPTO
// DATAOUT = high (opto should allow TPIDATA to be pulled low by external device)
// if(T == 0)
// DATAOUT = low
sbi _SFR_IO_ADDR(TPI_DATAOUT_PORT), TPI_DATAOUT_BIT
brts 1f
tpi_bit_l:
cbi _SFR_IO_ADDR(TPI_DATAOUT_PORT), TPI_DATAOUT_BIT
1:
#else
// DATAOUT = pull-up
// if(T == 0)
// DATAOUT = low
cbi _SFR_IO_ADDR(TPI_DATAOUT_DDR), TPI_DATAOUT_BIT
sbi _SFR_IO_ADDR(TPI_DATAOUT_PORT), TPI_DATAOUT_BIT
brts 1f
tpi_bit_l:
cbi _SFR_IO_ADDR(TPI_DATAOUT_PORT), TPI_DATAOUT_BIT
sbi _SFR_IO_ADDR(TPI_DATAOUT_DDR), TPI_DATAOUT_BIT
1:
#endif
/* delay(); */
lds r30, tpi_dly_cnt
lds r31, tpi_dly_cnt+1
1:
sbiw r30, 1
brsh 1b
/* TPICLK = 1 */
sbi _SFR_IO_ADDR(TPI_CLK_PORT), TPI_CLK_BIT
/* T = TPIDATA */
in r30, _SFR_IO_ADDR(TPI_DATAIN_PIN)
bst r30, TPI_DATAIN_BIT
/* delay(); */
lds r30, tpi_dly_cnt
lds r31, tpi_dly_cnt+1
1:
sbiw r30, 1
brsh 1b
/* TPICLK = 0 */
cbi _SFR_IO_ADDR(TPI_CLK_PORT), TPI_CLK_BIT
ret
/**
* Receive one byte
* out: r24 => byte
* lost: r18-r19,r30-r31
*/
.global tpi_recv_byte
tpi_recv_byte:
/* waitfor(start_bit, 192); */
ldi r18, 192
1:
rcall tpi_bit_h
brtc .tpi_recv_found_start
dec r18
brne 1b
/* no start bit: set return value */
.tpi_break_ret0:
ldi r24, 0
/* send 2 breaks (24++ bits) */
ldi r18, 26
1:
rcall tpi_bit_l
dec r18
brne 1b
/* send hi */
rjmp tpi_bit_h
// ----
.tpi_recv_found_start:
/* recv 8bits(+calc.parity) */
ldi r18, 8
ldi r19, 0
1:
rcall tpi_bit_h
lsr r24
bld r24, 7
eor r19, r24
dec r18
brne 1b
/* recv parity */
rcall tpi_bit_h
bld r18, 7
eor r19, r18
brmi .tpi_break_ret0
/* recv stop bits */
rcall tpi_bit_h
rjmp tpi_bit_h
/**
* Read Block
*/
.global tpi_read_block
tpi_read_block:
// X <= dptr
movw XL, r22
// r23 <= len
mov r23, r20
/* set PR */
rcall tpi_pr_update
/* read data */
.tpi_read_loop:
ldi r24, TPI_OP_SLD_INC
rcall tpi_send_byte
rcall tpi_recv_byte
st X+, r24
dec r23
brne .tpi_read_loop
ret
/**
* Write block
*/
.global tpi_write_block
tpi_write_block:
// X <= sptr
movw XL, r22
// r23 <= len
mov r23, r20
/* set PR */
rcall tpi_pr_update
/* write data */
.tpi_write_loop:
ldi r24, TPI_OP_SOUT(NVMCMD)
rcall tpi_send_byte
ldi r24, NVMCMD_WORD_WRITE
rcall tpi_send_byte
ldi r24, TPI_OP_SST_INC
rcall tpi_send_byte
ld r24, X+
rcall tpi_send_byte
.tpi_nvmbsy_wait:
ldi r24, TPI_OP_SIN(NVMCSR)
rcall tpi_send_byte
rcall tpi_recv_byte
andi r24, NVMCSR_BSY
brne .tpi_nvmbsy_wait
dec r23
brne .tpi_write_loop
ret
|
akrasuski1/usbasp-uart
| 11,323
|
firmware/usbdrv/usbdrvasm.S
|
/* Name: usbdrvasm.S
* Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
* Author: Christian Starkjohann
* Creation Date: 2007-06-13
* Tabsize: 4
* Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
* License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
* Revision: $Id: usbdrvasm.S 785 2010-05-30 17:57:07Z cs $
*/
/*
General Description:
This module is the assembler part of the USB driver. This file contains
general code (preprocessor acrobatics and CRC computation) and then includes
the file appropriate for the given clock rate.
*/
#define __SFR_OFFSET 0 /* used by avr-libc's register definitions */
#include "usbportability.h"
#include "usbdrv.h" /* for common defs */
/* register names */
#define x1 r16
#define x2 r17
#define shift r18
#define cnt r19
#define x3 r20
#define x4 r21
#define x5 r22
#define bitcnt x5
#define phase x4
#define leap x4
/* Some assembler dependent definitions and declarations: */
#ifdef __IAR_SYSTEMS_ASM__
extern usbRxBuf, usbDeviceAddr, usbNewDeviceAddr, usbInputBufOffset
extern usbCurrentTok, usbRxLen, usbRxToken, usbTxLen
extern usbTxBuf, usbTxStatus1, usbTxStatus3
# if USB_COUNT_SOF
extern usbSofCount
# endif
public usbCrc16
public usbCrc16Append
COMMON INTVEC
# ifndef USB_INTR_VECTOR
ORG INT0_vect
# else /* USB_INTR_VECTOR */
ORG USB_INTR_VECTOR
# undef USB_INTR_VECTOR
# endif /* USB_INTR_VECTOR */
# define USB_INTR_VECTOR usbInterruptHandler
rjmp USB_INTR_VECTOR
RSEG CODE
#else /* __IAR_SYSTEMS_ASM__ */
# ifndef USB_INTR_VECTOR /* default to hardware interrupt INT0 */
# ifdef INT0_vect
# define USB_INTR_VECTOR INT0_vect // this is the "new" define for the vector
# else
# define USB_INTR_VECTOR SIG_INTERRUPT0 // this is the "old" vector
# endif
# endif
.text
.global USB_INTR_VECTOR
.type USB_INTR_VECTOR, @function
.global usbCrc16
.global usbCrc16Append
#endif /* __IAR_SYSTEMS_ASM__ */
#if USB_INTR_PENDING < 0x40 /* This is an I/O address, use in and out */
# define USB_LOAD_PENDING(reg) in reg, USB_INTR_PENDING
# define USB_STORE_PENDING(reg) out USB_INTR_PENDING, reg
#else /* It's a memory address, use lds and sts */
# define USB_LOAD_PENDING(reg) lds reg, USB_INTR_PENDING
# define USB_STORE_PENDING(reg) sts USB_INTR_PENDING, reg
#endif
#define usbTxLen1 usbTxStatus1
#define usbTxBuf1 (usbTxStatus1 + 1)
#define usbTxLen3 usbTxStatus3
#define usbTxBuf3 (usbTxStatus3 + 1)
;----------------------------------------------------------------------------
; Utility functions
;----------------------------------------------------------------------------
#ifdef __IAR_SYSTEMS_ASM__
/* Register assignments for usbCrc16 on IAR cc */
/* Calling conventions on IAR:
* First parameter passed in r16/r17, second in r18/r19 and so on.
* Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer)
* Result is passed in r16/r17
* In case of the "tiny" memory model, pointers are only 8 bit with no
* padding. We therefore pass argument 1 as "16 bit unsigned".
*/
RTMODEL "__rt_version", "3"
/* The line above will generate an error if cc calling conventions change.
* The value "3" above is valid for IAR 4.10B/W32
*/
# define argLen r18 /* argument 2 */
# define argPtrL r16 /* argument 1 */
# define argPtrH r17 /* argument 1 */
# define resCrcL r16 /* result */
# define resCrcH r17 /* result */
# define ptrL ZL
# define ptrH ZH
# define ptr Z
# define byte r22
# define bitCnt r19
# define polyL r20
# define polyH r21
# define scratch r23
#else /* __IAR_SYSTEMS_ASM__ */
/* Register assignments for usbCrc16 on gcc */
/* Calling conventions on gcc:
* First parameter passed in r24/r25, second in r22/23 and so on.
* Callee must preserve r1-r17, r28/r29
* Result is passed in r24/r25
*/
# define argLen r22 /* argument 2 */
# define argPtrL r24 /* argument 1 */
# define argPtrH r25 /* argument 1 */
# define resCrcL r24 /* result */
# define resCrcH r25 /* result */
# define ptrL XL
# define ptrH XH
# define ptr x
# define byte r18
# define bitCnt r19
# define polyL r20
# define polyH r21
# define scratch r23
#endif
#if USB_USE_FAST_CRC
; This implementation is faster, but has bigger code size
; Thanks to Slawomir Fras (BoskiDialer) for this code!
; It implements the following C pseudo-code:
; unsigned table(unsigned char x)
; {
; unsigned value;
;
; value = (unsigned)x << 6;
; value ^= (unsigned)x << 7;
; if(parity(x))
; value ^= 0xc001;
; return value;
; }
; unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen)
; {
; unsigned crc = 0xffff;
;
; while(argLen--)
; crc = table(lo8(crc) ^ *argPtr++) ^ hi8(crc);
; return ~crc;
; }
; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen);
; argPtr r24+25 / r16+r17
; argLen r22 / r18
; temp variables:
; byte r18 / r22
; scratch r23
; resCrc r24+r25 / r16+r17
; ptr X / Z
usbCrc16:
mov ptrL, argPtrL
mov ptrH, argPtrH
ldi resCrcL, 0xFF
ldi resCrcH, 0xFF
rjmp usbCrc16LoopTest
usbCrc16ByteLoop:
ld byte, ptr+
eor resCrcL, byte ; resCrcL is now 'x' in table()
mov byte, resCrcL ; compute parity of 'x'
swap byte
eor byte, resCrcL
mov scratch, byte
lsr byte
lsr byte
eor byte, scratch
inc byte
lsr byte
andi byte, 1 ; byte is now parity(x)
mov scratch, resCrcL
mov resCrcL, resCrcH
eor resCrcL, byte ; low byte of if(parity(x)) value ^= 0xc001;
neg byte
andi byte, 0xc0
mov resCrcH, byte ; high byte of if(parity(x)) value ^= 0xc001;
clr byte
lsr scratch
ror byte
eor resCrcH, scratch
eor resCrcL, byte
lsr scratch
ror byte
eor resCrcH, scratch
eor resCrcL, byte
usbCrc16LoopTest:
subi argLen, 1
brsh usbCrc16ByteLoop
com resCrcL
com resCrcH
ret
#else /* USB_USE_FAST_CRC */
; This implementation is slower, but has less code size
;
; extern unsigned usbCrc16(unsigned char *argPtr, unsigned char argLen);
; argPtr r24+25 / r16+r17
; argLen r22 / r18
; temp variables:
; byte r18 / r22
; bitCnt r19
; poly r20+r21
; scratch r23
; resCrc r24+r25 / r16+r17
; ptr X / Z
usbCrc16:
mov ptrL, argPtrL
mov ptrH, argPtrH
ldi resCrcL, 0
ldi resCrcH, 0
ldi polyL, lo8(0xa001)
ldi polyH, hi8(0xa001)
com argLen ; argLen = -argLen - 1: modified loop to ensure that carry is set
ldi bitCnt, 0 ; loop counter with starnd condition = end condition
rjmp usbCrcLoopEntry
usbCrcByteLoop:
ld byte, ptr+
eor resCrcL, byte
usbCrcBitLoop:
ror resCrcH ; carry is always set here (see brcs jumps to here)
ror resCrcL
brcs usbCrcNoXor
eor resCrcL, polyL
eor resCrcH, polyH
usbCrcNoXor:
subi bitCnt, 224 ; (8 * 224) % 256 = 0; this loop iterates 8 times
brcs usbCrcBitLoop
usbCrcLoopEntry:
subi argLen, -1
brcs usbCrcByteLoop
usbCrcReady:
ret
; Thanks to Reimar Doeffinger for optimizing this CRC routine!
#endif /* USB_USE_FAST_CRC */
; extern unsigned usbCrc16Append(unsigned char *data, unsigned char len);
usbCrc16Append:
rcall usbCrc16
st ptr+, resCrcL
st ptr+, resCrcH
ret
#undef argLen
#undef argPtrL
#undef argPtrH
#undef resCrcL
#undef resCrcH
#undef ptrL
#undef ptrH
#undef ptr
#undef byte
#undef bitCnt
#undef polyL
#undef polyH
#undef scratch
#if USB_CFG_HAVE_MEASURE_FRAME_LENGTH
#ifdef __IAR_SYSTEMS_ASM__
/* Register assignments for usbMeasureFrameLength on IAR cc */
/* Calling conventions on IAR:
* First parameter passed in r16/r17, second in r18/r19 and so on.
* Callee must preserve r4-r15, r24-r29 (r28/r29 is frame pointer)
* Result is passed in r16/r17
* In case of the "tiny" memory model, pointers are only 8 bit with no
* padding. We therefore pass argument 1 as "16 bit unsigned".
*/
# define resL r16
# define resH r17
# define cnt16L r30
# define cnt16H r31
# define cntH r18
#else /* __IAR_SYSTEMS_ASM__ */
/* Register assignments for usbMeasureFrameLength on gcc */
/* Calling conventions on gcc:
* First parameter passed in r24/r25, second in r22/23 and so on.
* Callee must preserve r1-r17, r28/r29
* Result is passed in r24/r25
*/
# define resL r24
# define resH r25
# define cnt16L r24
# define cnt16H r25
# define cntH r26
#endif
# define cnt16 cnt16L
; extern unsigned usbMeasurePacketLength(void);
; returns time between two idle strobes in multiples of 7 CPU clocks
.global usbMeasureFrameLength
usbMeasureFrameLength:
ldi cntH, 6 ; wait ~ 10 ms for D- == 0
clr cnt16L
clr cnt16H
usbMFTime16:
dec cntH
breq usbMFTimeout
usbMFWaitStrobe: ; first wait for D- == 0 (idle strobe)
sbiw cnt16, 1 ;[0] [6]
breq usbMFTime16 ;[2]
sbic USBIN, USBMINUS ;[3]
rjmp usbMFWaitStrobe ;[4]
usbMFWaitIdle: ; then wait until idle again
sbis USBIN, USBMINUS ;1 wait for D- == 1
rjmp usbMFWaitIdle ;2
ldi cnt16L, 1 ;1 represents cycles so far
clr cnt16H ;1
usbMFWaitLoop:
in cntH, USBIN ;[0] [7]
adiw cnt16, 1 ;[1]
breq usbMFTimeout ;[3]
andi cntH, USBMASK ;[4]
brne usbMFWaitLoop ;[5]
usbMFTimeout:
#if resL != cnt16L
mov resL, cnt16L
mov resH, cnt16H
#endif
ret
#undef resL
#undef resH
#undef cnt16
#undef cnt16L
#undef cnt16H
#undef cntH
#endif /* USB_CFG_HAVE_MEASURE_FRAME_LENGTH */
;----------------------------------------------------------------------------
; Now include the clock rate specific code
;----------------------------------------------------------------------------
#ifndef USB_CFG_CLOCK_KHZ
# ifdef F_CPU
# define USB_CFG_CLOCK_KHZ (F_CPU/1000)
# else
# error "USB_CFG_CLOCK_KHZ not defined in usbconfig.h and no F_CPU set!"
# endif
#endif
#if USB_CFG_CHECK_CRC /* separate dispatcher for CRC type modules */
# if USB_CFG_CLOCK_KHZ == 18000
# include "usbdrvasm18-crc.inc"
# else
# error "USB_CFG_CLOCK_KHZ is not one of the supported crc-rates!"
# endif
#else /* USB_CFG_CHECK_CRC */
# if USB_CFG_CLOCK_KHZ == 12000
# include "usbdrvasm12.inc"
# elif USB_CFG_CLOCK_KHZ == 12800
# include "usbdrvasm128.inc"
# elif USB_CFG_CLOCK_KHZ == 15000
# include "usbdrvasm15.inc"
# elif USB_CFG_CLOCK_KHZ == 16000
# include "usbdrvasm16.inc"
# elif USB_CFG_CLOCK_KHZ == 16500
# include "usbdrvasm165.inc"
# elif USB_CFG_CLOCK_KHZ == 20000
# include "usbdrvasm20.inc"
# else
# error "USB_CFG_CLOCK_KHZ is not one of the supported non-crc-rates!"
# endif
#endif /* USB_CFG_CHECK_CRC */
|
akshaybaweja/component-tester-oled
| 14,329
|
Source Code/samplingADC_cnt.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include <avr/eeprom.h>
#include <stdlib.h>
#include "config.h"
#include "part_defs.h"
.GLOBAL samplingADC
.func samplingADC
#if AUTO_CLOCK_DIV == ((1<<ADPS2) | (1<<ADPS1) | (1<<ADPS0))
#define TICS_PER_ADC_CLOCK 128
#else
#define TICS_PER_ADC_CLOCK 64
#endif
#define ADC_StartDelay 32 /* we cannot trigger the ADC before the Counter1 is started */
#define ADC_SHtime (TICS_PER_ADC_CLOCK*2) /* time to ADC S&H for triggered start */
;===============================================================================================
; This version uses counter1 for start of first ADC-cycle in a Signal sequence
;===============================================================================================
.section .text
samplingADC:
;uint16_t samplingADC(R24:25 what, R22:23 array[], R20 nn, R18 Rport_1, R16 Rddr_1, R14 Rport_0, R12 Rddr_0) {}
; R24 = The length of the generated pulse in clock tics.
; Supported values are 0-15 for pulse-length 1-16 .
; Bit 0x10 is used for a direct pulse with length 1.
; For direct pulse the ADC port is used as output without 680 Ohm resistors.
; R25 = Pulse-distance (span)
; Possible values for pulse distance are 1,2,4,8,13,16,26,32,52,64,104,128 and 208 .
; All other values match not with the ADC convertion time without remainder,
; so that the sample time is not correct for the second and all following conversion periods.
; R22:23 The address of a array, which hold the data
ldi r26, 0 ; no RAM space
ldi r27, 0
ldi r30, lo8(gs(Retur1)) ;0x6B ; 107
ldi r31, hi8(gs(Retur1)) ;0x32 ; 50
jmp __prologue_saves__
Retur1:
; clr r1
mov R13, R18 ; R13 = Rport_1
movw R18,R24 ; R18 = pulse-length+options, R19 = distance of samples
and R19, R19
brne no_zero
ldi R19, 1 ; span must be 1
no_zero:
andi R18, 0x1f ; 0 - 15 for pulse length and direct-pulse option
movw R4, R22 ; R4:5 = &array[0];
ldi R21, 1 ; nn=256
cpse R20, r1
ldi R21, 0 ; nn <256
mov r22, R20 ; NN
dec r22
mul R19, r22 ; (NN-1) * span
movw r22, r0 ; r22:23 = last_sample = (NN-1) * span
clr r1 ; restore zero register
; R19 = span, r27=clock_div
ldi r26, lo8(TICS_PER_ADC_CLOCK*13)
ldi r27, hi8(TICS_PER_ADC_CLOCK*13)
movw r2, r26 ; save tics per ADC cycle in r2:3
AOUT R_PORT, R14 ; Rport_0 set to start condition
AOUT R_DDR, R12 ; Rddr_0
ldi r26, (1<<ADTS2) | (0<<ADTS1) | (1<<ADTS0);
sts ADCSRB, r26 ; // trigger source COUNTER1 compare match B
ldi r27, (1<<ADEN) | (1<<ADSC) | (1<<ADATE) | (1<<ADIF) | (0<<ADIE) | AUTO_CLOCK_DIV;
sts ADCSRA, r27 ; start first ADC with ext trigger, but start immediately
wait_adc:
lds r26, ADCSRA ; while (ADCSRA & (1 << ADSC))
sbrc r26, ADSC
rjmp wait_adc ; /* wait until first initial conversion is done */
sts ADCSRA, r26 ; clear flags (1<<ADIF)
mov r10, r1 ; start_pos = 0;
mov r11, r1
movw r6, r10 ; r6:7 Samples = 0; // no ADC sample get yet
; // The pulse generation is time critical
; // we are just behind the previous cycle of the ADC
; // time to next S&H is below 1.5 ADC clocks.
; // If required, the next Signal period begins in about 13 ADC-clocks.
; // We switch back to the initial trigger source to stop the counter after completing this cycle.
//==============================================================================================
GeneratePulse:
; r2:3 = CPUtics of a full ADC period (13 ADC-clocks)
; r4:5 = Address of buffer
; r6:7 = Samples, the count of collected data
; r8:9 = sample_pos the tic position of actual sample
; r10:11 = start_pos, the tic position of the first sample in this signal period
; R12 = Rddr_0
; R13 = Rport_1
; R14 = Rport_0
; r15 = scratch
; R16 = Rddr_1
; r17 = scratch
; R19 = span each time shift step has span CPU-tics
; R20:21 = nn the number of requested data elements
; r22:23 = last_sample the position of last sample
; R24 = option, R18 = pulse_width, R19 = span
sts TCCR1B, r1 ; TCCR1B = 0; // stop counter1
sts TCCR1A, r1 ; TCCR1A = 0; // set counter1 to normal mode
sts TCNT1H, r1 ; TCNT1 = 0; // set initial counter to zero
sts TCNT1L, r1
; // set the ADC Start time, documentation mentions a 3 CPU clock delay, which is compensated here
movw r26, r10 ; start_pos
movw r8, r10 ; sample_pos = start_pos
add r26, R18 ; + pulse_width
adc r27, r1
adiw r26, (ADC_StartDelay - 3)
sts OCR1BH, r27 ; OCR1B = (ADC_StartDelay - 3 + start_pos);
sts OCR1BL, r26 ; set compare B to start condition for this Pulse generation
subi r26, lo8(-(ADC_SHtime + 16 + 3)) ; + time to S&H
sbci r27, hi8(-(ADC_SHtime + 16 + 3)) ;
sts OCR1AH, r27 ; OCR1A = (ADC_StartDelay + ADC_SHtime + 16 + start_pos );
sts OCR1AL, r26 ; update compare A interrupt to behind S&H
sts TIMSK1, r1 ; // disable counter1 compare A Interrupt
ldi r26, (1<<ICF1) | (1<<OCF1B) | (1<<OCF1A) | (1<<TOV1);
out _SFR_IO_ADDR(TIFR1), r26 ; clear interrupt flags
cp r6, R20 ; if (Samples >= nn)
cpc r7, R21
brcs get_next_data
// all samples collected, finish
finish:
clr r1
sts TCCR1B, r1 ; TCCR1B = 0; // stop counter1
ldi r26, (1<<ADIF) | (1<<ADIE) ; // stop ADC
sts ADCSRA, r26
;## in r28, _SFR_IO_ADDR(SPL)
;## in r29, _SFR_IO_ADDR(SPH)
ldi r30, 18 ; restore full register list
jmp __epilogue_restores__
;============== return ======================
get_next_data:
ldi r26, (0<<ICNC1)|(1<<CS10) ; TCCR1B = (0<<ICNC1)|(1<<CS10);
sts TCCR1B, r26 ; // start counter at full speed
;============ Counter 1 is started =================================================
; // We must count the CPU cycles used by the program to generate the signal just before S&H!
; The counter starts ADC in ADC_StartDelay tics.
; The signal generation takes 13 tics + (dp_width-1).
; So we must only delay the two ADC clock cycles (ADC_SHtime) plus the ADC_StartDelay,
; but minus the count of tics for the signal generation.
; The time difference for the different signal types is compensated with counter delay.
#define SignalStartDelay (ADC_SHtime+ADC_StartDelay-11+1)
; 256 + 32 -11 = 277
ldi r26, (SignalStartDelay / 3)
lop1:
dec r26
brne lop1
#if (SignalStartDelay % 3) > 1
nop
#endif
#if (SignalStartDelay % 3) > 0
nop
#endif
ldi r30, lo8(gs(Return2)) ;11
ldi r31, hi8(gs(Return2)) ;10
sub r30, R18 ;9 -pulse_width
sbc r31, r1 ;8
mov r27, R14 ;7 Rport_0
or r27, R13 ;6 Rport_1
wdr ;5 wdt_reset();
ijmp ;4 computed goto Return+(16-dp_width)
rjmp direct_pulse ; special pulse without resistors, two additional tics
AOUT R_PORT, R13 ;17 R_PORT = Rport_1, dp_width = (16-1)
AOUT R_PORT, R13 ;16 R_PORT = Rport_1, dp_width = (15-1)
AOUT R_PORT, R13 ;15 R_PORT = Rport_1, dp_width = (14-1)
AOUT R_PORT, R13 ;14 R_PORT = Rport_1, dp_width = (13-1)
AOUT R_PORT, R13 ;13 R_PORT = Rport_1, dp_width = (12-1)
AOUT R_PORT, R13 ;12 R_PORT = Rport_1, dp_width = (11-1)
AOUT R_PORT, R13 ;11 R_PORT = Rport_1, dp_width = (10-1)
AOUT R_PORT, R13 ;10 R_PORT = Rport_1, dp_width = (9-1)
AOUT R_PORT, R13 ; 9 R_PORT = Rport_1, dp_width = (8-1)
AOUT R_PORT, R13 ; 8 R_PORT = Rport_1, dp_width = (7-1)
AOUT R_PORT, R13 ; 7 R_PORT = Rport_1, dp_width = (6-1)
AOUT R_PORT, R13 ; 6 R_PORT = Rport_1, dp_width = (5-1)
AOUT R_PORT, R13 ; 5 R_PORT = Rport_1, dp_width = (4-1)
AOUT R_PORT, R13 ; 4 R_PORT = Rport_1, dp_width = (3-1)
AOUT R_PORT, R13 ; 3 R_PORT = Rport_1, dp_width = (2-1)
Return2:
AOUT R_PORT, r27 ; 2 R_PORT = Rport_1|Rport_0; // beginning of step, or end of (last) impulse
AOUT R_DDR, R16 ; 1 R_DDR = Rddr_1; // start of first measurement is aligned with this
;============ End of time critical part =================================================
AOUT R_PORT, R14 ; R_PORT = Rport_0; only switch of unused Rport_0
rjmp wait_cnt
;; cap:
; byte d=( (hivolt) ? HiPinR_L : HiPinR_H );
; samplingADC(samp_opt, uu, N2+1, d, HiPinR_H, d, HiPinR_L);
;
; Rport_1 = Rport_0 = HiPinR_H or HiPinR_L
; Rddr_1 = HiPinR_H
; Rddr_0 = HiPinR_L
;
;uint16_t samplingADC(R24:25 what, R22:23 array[], R20 nn, R18 Rport_1, R16 Rddr_1, R14 Rport_0, R12 Rddr_0) {}
;
; samplingADC(par, uu, 0, HiPinR_L, 0, 0, HiPinR_L);
;; LC:
; Rport_1 = HiPinR_L
; Rport_0 = 0
; Rddr_1 = 0
; Rddr_0 = HiPinR_L
;
;; UJT:
; port0 = pinmaskRL(B2pin);
; port1 = pinmaskRL(B2pin) | pinmaskRH(Epin)
; ddr1 = pinmaskRL(B2pin) | pinmaskRH(Epin)
; ddr0 = pinmaskRL(B2pin) | pinmaskRL(Epin);
direct_pulse:
nop ;16 + 2 tics for rjmp
#if MHZ_CPU != 16
; nop ;15
#endif
in r30, _SFR_IO_ADDR(ADC_DDR) ;14
in r31, _SFR_IO_ADDR(ADC_PORT) ;13
ldi r26, (1<<TP3) ;12
sbrc R12, PIN_RL2 ;11 is the bit for TP2 resistor set?
ldi r26, (1<<TP2) ;10
sbrc R12, PIN_RL1 ;9 ist the bit for TP3 resistor set?
ldi r26, (1<<TP1) ;8
; r26 now hold the bit for the direct ADC port
mov r27, r31 ;7 ADC_PORT state
or r27, r26 ;6 r27 is the for ADC port with HiPin set to 1
or r26, r30 ;5 r26 enables the HiPin and LoPin output, ADC_DDR
AOUT ADC_PORT, r27 ;4 set Hipin to high
AOUT R_DDR, R16 ;3 R_DDR = Rddr1 open all resistor ports
AOUT ADC_DDR, r26 ;2 one clock tic high without resistor at HiPin, current about 5V/(42 Ohm)=119mA !!!
#if MHZ_CPU == 16
; AOUT ADC_DDR, r26 ;2 one clock tic high without resistor at HiPin, current about 5V/(42 Ohm)=119mA !!!
#endif
AOUT ADC_DDR, r30 ;1 disable the HiPin output
;============ End of time critical part =================================================
AOUT ADC_PORT, r31 ; reset Hipin to low
rjmp wait_cnt
wait_cnt:
sbis _SFR_IO_ADDR(TIFR1), OCF1A ; while (TIFR1 & (1 << OCF1A) == 0)
rjmp wait_cnt ; /* wait until counter1 compare match is done */
;---------------XXXXXXXX-------------------------
; // The first triggered ADC conversion takes 13.5 ADC clock cycles from Counter Reg B compare
sts TCCR1B, r1 ; TCCR1B = 0; // stop counter, no longer required_
ldi r26, (1<<ICF1) | (1<<OCF1B) | (1<<OCF1A) | (1<<TOV1);
out _SFR_IO_ADDR(TIFR1), r26 ; clear interrupt flags
//==============================================================================================
CheckNextSample:
; // The pulse generation is time critical.
; // We are just behind the previous cycle of the ADC for repeated conversion.
; // The time to next S&H is below 1.5 ADC clocks in this case.
; // If required, the next Signal period begins in about 13 ADC-clocks.
; // Let us look, if the next ADC S&H is within the sampling period
movw r26, r8 ; sample_pos
add r26, r2 ; sample_pos + adc_period
adc r27, r3
cp r22, r26 ;R22:23 = position of last sample, r26:27 = sample_pos + adc_period+1
cpc r23, r27
brcc more_data ; if (((start1 + m_shift) + samples_per_adc_period + 1) > nn)
; --------------------------------------------------------------
; // The running ADC-cycle is the last one in this Signal period
; // We switch back to the initial trigger source to stop the counter after completing this cycle.
ldi r26, (1<<ADTS2) | (0<<ADTS1) | (1<<ADTS0);
sts ADCSRB, r26 ; trigger source = COUNTER1 compare match B, STOP after ADC-cycle ends
; // We must differ between the first and repeated ADC cycle condition.
; // If it is the first cycle, we are already behind the S&H time (Counter1 Compare match A).
; // The other situation is the repeated ADC. In this case we are just behind
; // the end of ADC cycle, so we must wait for the next S&H time.
; // The next S&H is at 1.5*ADCclock.
cp r10, r8 ; start_delay <= sample_pos
cpc r11, r9
brcc behind_SH ; if (m_shift > 0)
// This is not the first ADC-cycle in this Signal-generation cycle.
// Let us wait for next SH time.
ldi r26, ((TICS_PER_ADC_CLOCK*3)/6) ; 1.5 * ADC_CLOCK
lop3:
dec r26
brne lop3
behind_SH:
; -------------------------------------
; toggle output back to the idle state
AOUT R_PORT, R14 ; 5 Rport_0
AOUT R_DDR, R12 ; 4 Rddr_0
rcall store_data ; store new ADC data to array and count Samples
; // This was the last ADC data of this Signal period, update the time shift registers
add r10, R19 ; start_pos += span:
adc r11, r1
; call wait200us ; ############# for Test only #################################################
rjmp GeneratePulse ; last data of this signal period is fetched
; --------------------------------------------------------------
; // there are more data to collect in this Signal period
; // Now we try to switch the ADC to free running mode
more_data:
sts ADCSRB, r1 ;ADCSRB = 0; // source ADC finish == 13 ADC clock cyclus free run
rcall store_data ; store new ADC data in array and count Samples
add r8, r2 ; sample_pos += adc_period;
adc r9, r3 ;
rjmp CheckNextSample ; check, if the next data is the last one in this signal period
; Store ADC data in caller's array
; Wait for ADC data ready with polling
; The position of array cell is array[start1 + m_shift]
; r8:9 = position of sample, R4:5 = beginn of array
; Function use register r17:15 to get new ADC data and
; register r26:27 to read (and accumulate) the old data at the array place.
; every call increments the Samples counter r6:7 .
store_data:
movw r26, r8 ; sample_pos
movw r30, R4 ; &array
sub_loop:
sub r26, R19 ; - span
sbc r27, r1
brcs is_found
adiw r30, 2 ; increment array address
rjmp sub_loop
is_found:
ld r26, Z ; lo8(array[start1 + m_shift])
ldd r27, Z+1 ; hi8(array[start1 + m_shift])
; r30:31 = Z = number of a 16-Bit element.
wait_adc3:
lds r17, ADCSRA ; while (ADCSRA & (1 << ADIF) == 0)
sbrs r17, ADIF
rjmp wait_adc3 ; /* wait until conversion is done */
sts ADCSRA, r17 ; clear the interrupt ADIF
; // next ADC data are ready
lds r17, ADCL ; neẃ ADC value
lds r15, ADCH
;## lds r17, TCNT1L ; TCNT
;## lds r15, TCNT1H
sbrc r24, smplADC_cumul ; skip next instruction, if no acummulate
add r17, r26 ; + lo8(array[start1 + m_shift])
st Z+, r17 ; store lower part
sbrc r24, smplADC_cumul ; skip next instruction, if no acummulate
adc r15, r27 ; + hi8(array[start1 + m_shift])
st Z, r15 ; store upper part
ldi r17, 1
add r6, r17 ; Samples++
adc r7, r1 ; add carry to r7
ret ; return store_data
.endfunc
|
akshaybaweja/component-tester-oled
| 6,649
|
Source Code/ReadADC.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include "config.h"
#include <stdlib.h>
//#include "autoinout.h"
.GLOBAL ReadADC
.GLOBAL W20msReadADC
.GLOBAL W10msReadADC
.GLOBAL W5msReadADC
.func ReadADC
.extern wait100us
.extern wait5ms
.extern wait10ms
#define Samples 0
#define RefFlag 1
#define U_Bandgap 2
#define U_AVCC 4
;// assembler version of ReadADC.c
;// ACALL is defined in config.h as rcall for ATmega8 and as call for ATmega168
#define RCALL rcall
#ifdef INHIBIT_SLEEP_MODE
.macro StartADCwait
#if ADCSRA < 32
sbi ADCSRA, ADSC;
#else
ldi r24, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable and start ADC */
sts ADCSRA, r24;
#endif
lds r24, ADCSRA; /* while (ADCSRA & (1 <<ADSC)) */
sbrc r24, ADSC;
rjmp .-8 ; /* wait until conversion is done */
.endm
#else
.macro StartADCwait
ldi r24, (1<<ADEN) | (1<<ADIF) | (1<<ADIE) | AUTO_CLOCK_DIV; /* enable ADC and Interrupt */
sts ADCSRA, r24;
ldi r24, (1 << SM0) | (1 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
sleep; /* wait for ADC */
ldi r24, (1 << SM0) | (0 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (0 << SE); */
.endm
#endif
.section .text
;unsigned int W20msReadADC(uint8_t Probe)
;unsigned int W5msReadADC(uint8_t Probe)
#ifdef INHIBIT_SLEEP_MODE
W20msReadADC:
ACALL wait10ms;
;// runs to W10msReadADC
W10msReadADC:
ACALL wait5ms;
;// runs to W5msReadADC
W5msReadADC:
ACALL wait5ms;
;// runs directly to ReadADC, this will replace "ACALL ReadADC + ret"
#else
W20msReadADC:
push r24;
ldi r24, 4; /* 4 * 5ms */
RCALL sleep_5ms;
rjmp to_read;
W10msReadADC:
push r24;
ldi r24, 2; /* 2 * 5ms */
RCALL sleep_5ms;
rjmp to_read;
W5msReadADC:
push r24;
ldi r24, 1; /* 1 * 5ms */
RCALL sleep_5ms;
to_read:
pop r24;
; run directly to ReadADC
#endif
;unsigned int ReadADC(uint8_t Probe)
ReadADC:
; //returns result of ADC port Probe scaled to mV resolution (unsigned int)
; unsigned long Value;
push r17;
; unsigned int U; /* return value (mV) */
; uint8_t Samples; /* loop counter */
; unsigned long Value; /* ADC value */
mov r17, r24; Probe
ori r17, (1 << REFS0) ; Probe |= (1 << REFS0); /* use internal reference anyway */
get_sample:
AOUT ADMUX, r17 ; ADMUX = Probe; /* set input channel and U reference */
#ifdef AUTOSCALE_ADC
/* if voltage reference changed run a dummy conversion */
mov r30, r17;
andi r30, (1 << REFS1) ; Samples = Probe & (1 << REFS1); /* get REFS1 bit flag */
lds r24, ADCconfig+RefFlag ;
cp r30, r24;
breq no_ref_change ; if (Samples != ADCconfig.RefFlag)
sts ADCconfig+RefFlag, r30 ; ADCconfig.RefFlag = Samples; /* update flag */
#ifdef NO_AREF_CAP
RCALL wait100us ; wait100us(); /* time for voltage stabilization */
#else
#ifdef INHIBIT_SLEEP_MODE
RCALL wait10ms ; wait10ms(); /* long time for voltage stabilization */
#else
ldi r24, 2 ; /* 2 * 5ms */
RCALL sleep_5ms ; wait_about10ms()
#endif
#endif /* end NO_AREF_CAP */
StartADCwait ; // allways do one dummy read of ADC, 112us
#endif /* end AUTOSCALE_ADC */
;unsigned int ReadADC (uint8_t Probe) {
no_ref_change:
/* * sample ADC readings */
ldi r18, 0x00; Value = 0UL; /* reset sampling variable */
ldi r19, 0x00;
movw r20, r18;
ldi r30, 0x00; Samples = 0; /* number of samples to take */
rjmp r2ae8 ;
; while (Samples < ADCconfig.Samples) /* take samples */
Loop:
StartADCwait /* start ADC and wait */
lds r22, ADCL; Value += ADCW; /* add ADC reading */
lds r23, ADCH;
add r18, r22;
adc r19, r23;
adc r20, r1;
adc r21, r1;
#ifdef AUTOSCALE_ADC
; /* auto-switch voltage reference for low readings */
; if ((Samples == 4) && (ADCconfig.U_Bandgap > 255) && ((uint16_t)Value < 1024) && !(Probe & (1 << REFS1))) {
cpi r30, 0x04; Samples == 4
brne cnt_next ; if ((Samples == 4) &&
lds r24, ADCconfig+3;
cpi r24,0;
breq cnt_next ; if ( && (ADCconfig.U_Bandgap > 255) )
ldi r24, hi8(1024) ; Value < 1024
cpi r18, lo8(1024)
cpc r19, r24;
brcc cnt_next ; if ( && && ((uint16_t)Value < 1024) )
sbrc r17, REFS1;
rjmp cnt_next ; if ( && && && !(Probe & (1 << REFS1)))
ori r17, (1 << REFS1); Probe |= (1 << REFS1); /* select internal bandgap reference */
#if (PROCESSOR_TYP == 644) || (PROCESSOR_TYP == 1280)
cbr r17, (1<<REFS0); Probe &= ~(1 << REFS0); /* ATmega640/1280/2560 1.1V Reference with REFS0=0 */
#endif
rjmp get_sample ; goto get_sample; /* re-run sampling */
#endif /* end AUTOSCALE_ADC */
cnt_next:
subi r30, 0xFF; Samples++; /* one more done */
r2ae8:
lds r24, ADCconfig+Samples;
cp r30, r24 ; while (Samples < ADCconfig.Samples) /* take samples */
brcs Loop ;
lds r22, ADCconfig+U_AVCC ; U = ADCconfig.U_AVCC; /* Vcc reference */
lds r23, ADCconfig+U_AVCC+1;
#ifdef AUTOSCALE_ADC
; /* * convert ADC reading to voltage * - single sample: U = ADC reading * U_ref / 1024 */
; /* get voltage of reference used */
sbrs r17, REFS1 ; if (Probe & (1 << REFS1))
rjmp r2b02 ;
lds r22, ADCconfig+U_Bandgap ; U = ADCconfig.U_Bandgap; /* bandgap reference */
lds r23, ADCconfig+U_Bandgap+1;
#endif /* end AUTOSCALE_ADC */
; /* convert to voltage; */
r2b02:
ldi r24, 0x00 ; Value *= U; /* ADC readings * U_ref */
ldi r25, 0x00; 0
ACALL __mulsi3; ; sum(ADCreads) * ADC_reference
ldi r18, lo8(1023) ; Value /= 1023; /* / 1024 for 10bit ADC */
ldi r19, hi8(1023);
ldi r20, 0x00; 0
ldi r21, 0x00; 0
ACALL __udivmodsi4; R22-25 / R18-21
movw r22, r18;
movw r24, r20;
; /* de-sample to get average voltage */
lds r18,ADCconfig+Samples ; Value /= ADCconfig.Samples;
ldi r19, 0x00; 0
ldi r20, 0x00; 0
ldi r21, 0x00; 0
ACALL __udivmodsi4; R22-25 / R18-21
movw r24, r18 ;;// return ((unsigned int)(Value / (1023 * (unsigned long)ADCconfig.Samples)));
pop r17;
ret;
.endfunc
.func abs_diff
.GLOBAL abs_diff
abs_diff:
movw r18, r22
sub r18, r24
sbc r19, r25
brcs is_pl ; return v1-v2
movw r24, r18
ret ; return v2-v1
.endfunc
.func vcc_diff
.GLOBAL vcc_diff
; uint16_t vcc_diff(uint16_t v2) // computes unsigned_diff(ADCconfig.U_AVCC, v2)
vcc_diff:
movw r22, r24
lds r24, ADCconfig+U_AVCC
lds r25, ADCconfig+U_AVCC+1
; runs to function unsigned diff
.endfunc
.func unsigned_diff
.GLOBAL unsigned_diff
; uint16_t unsigned_diff(uint16_t v1, uint16_t v2) // computes v1-v2 if positive, otherwise returns 0
unsigned_diff:
cp r22, r24
cpc r23, r25
brcc no_pl
is_pl:
sub r24, r22
sbc r25, r23
ret ; return v1-v2
no_pl:
ldi r24, 0
ldi r25, 0
ret ;
.endfunc
|
akshaybaweja/component-tester-oled
| 2,082
|
Source Code/swuart.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include "config.h"
#define bitcnt r18
#define temp r21
#define Txbyte r24
#define SER_PORT _SFR_IO_ADDR(SERIAL_PORT)
#define SER_DDR _SFR_IO_ADDR(SERIAL_DDR)
;* Software-UART nach Atmel AVR-Application-Note AVR305
;***************************************************************************
;*
;* "putchar"
;*
;* This subroutine transmits the byte stored in the "Txbyte" register
;* Low registers used :None
;* High registers used :2 (bitcnt,Txbyte)
;* Pointers used :None
;*
;***************************************************************************
.func uart_putc
.global uart_putc
.extern wait100us
.extern wait3us
.section .text
uart_putc:
#if defined(WITH_UART) && (!defined(WITH_HARDWARE_SERIAL))
; push bitcnt
; in temp,_SFR_IO_ADDR(SREG)
push Txbyte ; save character
push bitcnt ; save register used for bit count
ldi bitcnt,10 ;1+8+sb (sb is # of stop bits)
com Txbyte ;Inverte everything
sbi SER_DDR,SERIAL_BIT ; enable output of serial bit
sec ;Start bit
putchar0: brcc putchar1 ;If carry set
#ifdef SWUART_INVERT
sbi SER_PORT,SERIAL_BIT ; send a '0'
#else
cbi SER_PORT,SERIAL_BIT ; send a '0'
#endif
rjmp putchar2 ;else
putchar1:
#ifdef SWUART_INVERT
cbi SER_PORT,SERIAL_BIT ; send a '1'
#else
sbi SER_PORT,SERIAL_BIT ; send a '1'
#endif
nop
putchar2:
rcall wait100us ; about 9600 Baud
#if F_CPU >= 8000000UL
rcall wait3us
#endif
lsr Txbyte ;Get next bit
dec bitcnt ;If not all bit sent
brne putchar0 ; send next
;else
pop bitcnt ; restore register used for bit count
pop Txbyte ; restore character send
; out _SFR_IO_ADDR(SREG),temp
; pop bitcnt
#endif /* defined(WITH_UART) && (!defined(WITH_HARDWARE_SERIAL)) */
#ifdef WITH_HARDWARE_SERIAL
; wait for empty transmit buffer
w3:
lds r25, UCSR0A
sbrs r25, UDRE0
rjmp w3 ; wait
AOUT UDR0, r24 ; put data to transmit buffer
#endif /* def WITH_HARDWARE_SERIAL */
ret ; return
.endfunc
|
akshaybaweja/component-tester-oled
| 5,853
|
Source Code/UfAusgabe.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include <avr/eeprom.h>
#include "config.h"
#include "part_defs.h"
.section .text
#define zero_reg r1
#define RCALL rcall
/* #include <avr/io.h> */
/* #include "Transistortester.h" */
/* void mVAusgabe(uint8_t nn) { */
/* if (nn < 3) { */
/* // Output in mV units */
/* DisplayValue(diodes.Voltage[nn],-3,'V',3); */
/* lcd_space(); */
/* } */
/* } */
.GLOBAL mVAusgabe
.extern DisplayValue
.extern lcd_space
.func mVAusgabe
mVAusgabe:
; if (nn < 6) {
cpi r24, 0x06 ; 6
brcc ad1ca4;
// Output in mV units
LDIZ diodes+12;
add r30,r24
adc r31,zero_reg
add r30,r24
adc r31,zero_reg
ld r24, Z ; diodes.Voltage[nn]
ldd r25, Z+1 ; 0x01
ldi r22, 0x03 ; 3
RCALL Display_mV ; Display_mV(diodes.Voltage[nn],3);
RCALL lcd_space; ; lcd_space();
ad1ca4:
ret
.endfunc
/* // ****************************************************************** */
/* // output of flux voltage for 1-2 diodes in row 2 */
/* // bcdnum = Numbers of both Diodes: */
/* // higher 4 Bit number of first Diode */
/* // lower 4 Bit number of second Diode (Structure diodes[nn]) */
/* // if number >= 3 no output is done */
/* void UfAusgabe(uint8_t bcdnum) { */
/* if (ResistorsFound > 0) { //also Resistor(s) found */
/* lcd_space(); */
/* lcd_data(LCD_CHAR_RESIS3); // special symbol or R */
/* } */
/* lcd_line2(); //2. row */
/* lcd_PGM_string(Uf_str); //"Uf=" */
/* mVAusgabe(bcdnum >> 4); */
/* mVAusgabe(bcdnum & 0x0f); */
/* } */
.GLOBAL UfAusgabe
.extern lcd_space
.extern lcd_data
.extern lcd_line2
.extern mVAusgabe
.func UfAusgabe
UfAusgabe:
push r17
mov r17, r24
lds r24, ResistorsFound; 0x0168
and r24, r24
breq ad1cbe; if (ResistorsFound > 0) {
RCALL lcd_space; lcd_space();
ldi r24, LCD_CHAR_RESIS3; 0
RCALL lcd_data; lcd_data(LCD_CHAR_RESIS3); // special symbol or R
ad1cbe:
RCALL lcd_line2; //2. row
ldi r24, lo8(Uf_str); 0xE9
ldi r25, hi8(Uf_str); 0x01
#ifdef USE_EEPROM
RCALL lcd_fix_string ; lcd_PGM_string(Uf_str); //"Uf="
#else
RCALL lcd_pgm_string ; lcd_PGM_string(Uf_str); //"Uf="
#endif
mov r24, r17
swap r24
andi r24, 0x0F
rcall mVAusgabe ; mVAusgabe(bcdnum >> 4);
mov r24, r17
andi r24, 0x0F ; 15
rcall mVAusgabe ; mVAusgabe(bcdnum & 0x0f);
pop r17
ret
.endfunc
/* void SerienDiodenAusgabe() { */
/* uint8_t first; */
/* uint8_t second; */
/* first = diode_sequence >> 4; */
/* second = diode_sequence & 3; */
/* lcd_testpin(diodes.Anode[first]); */
/* lcd_PGM_string(AnKat_str); //"->|-" */
/* lcd_testpin(diodes.Cathode[first]); */
/* lcd_PGM_string(AnKat_str); //"->|-" */
/* lcd_testpin(diodes.Cathode[second]); */
/* UfAusgabe(diode_sequence); */
/* } */
.GLOBAL SerienDiodenAusgabe
.extern lcd_testpin
.extern UfAusgabe
.extern AnKat_str
.func SerienDiodenAusgabe
SerienDiodenAusgabe:
lds r24, diode_sequence; 0x0102
swap r24
andi r24, 0x0F ; first = diode_sequence >> 4;
rcall DiodeSymbol_ApinCpin ; 1->|-2
lds r24, diode_sequence; 0x0102
andi r24, 0x03 ; second = diode_sequence & 3;
RCALL DiodeSymbol_ACpin ; ->|-3
lds r24, diode_sequence; x0102
rcall UfAusgabe ; UfAusgabe(diode_sequence);
ret
.endfunc
.func load_diodes_adr
load_diodes_adr:
ldi r30, lo8(diodes) ;0x80
ldi r31, hi8(diodes) ;0x01
add r30, r24 ; [nn]
adc r31, zero_reg
ret
.endfunc
.GLOBAL DiodeSymbol_withPins
.func DiodeSymbol_withPins
DiodeSymbol_withPins:
#if FLASHEND > 0x1fff
// enough memory (>8k) to sort the pins
push r28
rcall load_diodes_adr
#if EBC_STYLE == 321
// the higher test pin number is left side
ld r28, Z ; diodes.Anode[nn]
ldd r25, Z+6 ; diodes.Cathode[nn]
cp r28, r25
brcc cat_first1 ; if (anode_nr > cathode_nr) {
rcall DiodeSymbol_ApinCpin
rjmp diode_fin
// } else {
cat_first1:
rcall DiodeSymbol_CpinApin
#else
// the higher test pin number is right side
ld r25, Z
ldd r28, Z+6 ; if (anode_nr < cathode_nr) {
cp r28, r25
brcc cat_first2
rcall DiodeSymbol_ApinCpin
rjmp diode_fin
// } else {
cat_first2:
rcall DiodeSymbol_CpinApin
#endif
#else
rcall DiodeSymbol_ApinCpin
#endif
diode_fin:
rcall lcd_space
pop r28
ret
.endfunc
.GLOBAL DiodeSymbol_ApinCpin
.func DiodeSymbol_ApinCpin
DiodeSymbol_ApinCpin:
rcall load_diodes_adr
push r24
ld r24, Z ;Anode
RCALL lcd_testpin ; lcd_testpin(diodes.Anode[nn]);
pop r24
rcall DiodeSymbol_ACpin ; ->|-3
ret
.endfunc
.GLOBAL DiodeSymbol_ACpin
.func DiodeSymbol_ACpin
DiodeSymbol_ACpin:
push r24
ldi r24, lo8(AnKat_str) ;0xA3
ldi r25, hi8(AnKat_str) ;0x03
#ifdef USE_EEPROM
.extern lcd_fix_string
RCALL lcd_fix_string ; lcd_PGM_string(AnKat_str); //"->|-"
#else
.extern lcd_pgm_string
RCALL lcd_pgm_string ; lcd_PGM_string(AnKat_str); //"->|-"
#endif
pop r24
rcall load_diodes_adr
ldd r24, Z+6 ; Cathode
RCALL lcd_testpin ; lcd_testpin(diodes.Cathode[nn]);
ret
.endfunc
.GLOBAL DiodeSymbol_CpinApin
.func DiodeSymbol_CpinApin
DiodeSymbol_CpinApin:
rcall load_diodes_adr
push r24
ldd r24, Z+6 ;Cathode
RCALL lcd_testpin ; lcd_testpin(diodes.Cathode[nn]);
pop r24
rcall DiodeSymbol_CApin ; -|<-3
ret
.endfunc
.GLOBAL DiodeSymbol_CApin
.func DiodeSymbol_CApin
DiodeSymbol_CApin:
push r24
ldi r24, lo8(KatAn_str) ;0xA3
ldi r25, hi8(KatAn_str) ;0x03
#ifdef USE_EEPROM
.extern lcd_fix_string
RCALL lcd_fix_string ; lcd_PGM_string(KatAn_str); //"->|-"
#else
.extern lcd_pgm_string
RCALL lcd_pgm_string ; lcd_PGM_string(KatAn_str); //"->|-"
#endif
pop r24
rcall load_diodes_adr
ld r24, Z ; Anode
RCALL lcd_testpin ; lcd_testpin(diodes.Anode[nn]);
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 8,084
|
Source Code/wait1000ms.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
.func wait1000ms
.global wait5s ; wait 5 seconds
.global wait4s ; wait 4 seconds
.global wait3s ; wait 3 seconds
.global wait2s ; wait 2 seconds
.global wait1s ; wait 1 seconds
.global wait1000ms ; wait 1 second and wait 1000ms are identical
.global wait500ms ; wait 500ms
.global wait400ms ; wait 400ms
.global wait300ms ; wait 300ms
.global wait200ms ; wait 200ms
.global wait100ms ; wait 100ms
.global wait50ms ; wait 50ms
.global wait40ms ; wait 40ms
.global wait30ms ; wait 30ms
.global wait20ms ; wait 20ms
.global wait10ms ; wait 10ms
.global wait5ms ; wait 5ms
.global wait4ms ; wait 4ms
.global wait3ms ; wait 3ms
.global wait2ms ; wait 2ms
.global wait1ms ; wait 1ms
.global wait500us ; wait 500µs
.global wait400us ; wait 400µs
.global wait300us ; wait 300µs
.global wait200us ; wait 200µs
.global wait100us ; wait 100µs
.global wait50us ; wait 50µs
.global wait40us ; wait 40µs
.global wait30us ; wait 30µs
.global wait20us ; wait 20µs
.global wait10us ; wait 10µs
/* A delay of 5us require a clock frequency of at least 1.4 MHz */
.global wait5us ; wait 5µs
.global wait4us ; wait 4µs
.global wait3us ; wait 3µs
.global wait2us ; wait 2µs
/* A delay of 1us require a clock frequency of at least 7 MHz */
.global wait1us ; wait 1µs
;wait loops for ATmega at a clock above 1MHz
; use of flash memory is: 76 bytes (16MHz operation, including 2 Byte Watch Dog reset at wait100ms)
; Every wait call needs only one instruction (rcall) for every of the 36 different delays (500ns - 5s).
; No registers are used. (only stack pointer)
; A maximum of 28 bytes of space for return addresses is used in RAM
; I see no way to implement this function with C-language (too tricky)
wait5s:
rcall wait1s ; 12+x return-adresses
wait4s:
rcall wait1s ; 12+x return-adresses
wait3s:
rcall wait1s ; 12+x return-adresses
wait2s:
rcall wait1s ;1s 12+x Return-Adresses
wait1s:
wait1000ms:
rcall wait500ms ;500ms 11+x Return-Adresses
wait500ms:
rcall wait100ms ;100ms 10+x Return-Adresses
wait400ms:
rcall wait100ms ;100ms 10+x Return-Adresses
wait300ms:
rcall wait100ms ;100ms 10+x Return-Adresses
wait200ms:
rcall wait100ms ;100ms 10+x Return-Adresses
wait100ms:
rcall wait50ms ; 50ms 9+x Return-Adresses
wait50ms:
rcall wait10ms ;10ms 8+x Return-Adresses
wait40ms:
rcall wait10ms ;10ms 8+x Return-Adresses
wait30ms:
rcall wait10ms ;10ms 8+x Return-Adresses
wait20ms:
rcall wait10ms ;10ms 8+x Return-Adresses
wait10ms:
rcall wait5ms ;5ms 7+x Return-Adresses
wait5ms:
wdr ; every 5ms one Watchdog reset!
rcall wait1ms ;1ms 6+x Return-Adresses
wait4ms:
rcall wait1ms ;1ms 6+x Return-Adresses
wait3ms:
rcall wait1ms ;1ms 6+x Return-Adresses
wait2ms:
rcall wait1ms ;1ms 6+x Return-Adresses
wait1ms:
rcall wait500us ;500us 5+x Return-Adresses
wait500us:
rcall wait100us ;100us 4+x Return-Adresses
wait400us:
rcall wait100us ;100us 4+x Return-Adresses
wait300us:
rcall wait100us ;100us 4+x Return-Adresses
wait200us:
rcall wait100us ;100us 4+x Return-Adresses
# RCALL_TICS specify the number of tics used for rcall and ret instruction
#if FLASH_END > 0x1ffff
/* special 3 byte return address takes two tics more */
#define RCALL_TICS 9
#else
#define RCALL_TICS 7
#endif
/* PS25_PER_TIC specify the number of 25ps units for one clock tic */
/* 40000000000 need more than 32 bit, so F_CPU is divided by 10 to match the 32-bit */
/* Note, that there is a little error of time delay, if 1/F_CPU does not match a multiple */
/* of a 25ps unit */
/* Normally the higher delay values are build with multiple of the base delay, */
/* so wait100us is done with 100 times of a wait1us call for example. */
/* But for F_CPU values, that does not match the 1us delay, corrections are done */
/* for the wait calls up to the wait100us call. The higher wait calls are not corrected. */
#define PS25_PER_TIC (4000000000 / ((F_CPU + 5) / 10))
#define US100_TICS (4000000 / PS25_PER_TIC)
#define US50_TICS (2000000 / PS25_PER_TIC)
#define US40_TICS (1600000 / PS25_PER_TIC)
#define US30_TICS (1200000 / PS25_PER_TIC)
#define US20_TICS (800000 / PS25_PER_TIC)
#define US10_TICS (400000 / PS25_PER_TIC)
#define US5_TICS (200000 / PS25_PER_TIC)
#define US4_TICS (160000 / PS25_PER_TIC)
#define US3_TICS (120000 / PS25_PER_TIC)
#define US2_TICS (80000 / PS25_PER_TIC)
#define US1_TICS (40000 / PS25_PER_TIC)
#define NS500_TICS (20000 / PS25_PER_TIC)
wait100us:
#if US100_TICS > (2 * US50_TICS)
nop
#endif
rcall wait50us ; 50us delay
wait50us:
#if US50_TICS > (US40_TICS + US10_TICS)
nop
#endif
rcall wait10us ;10us delay
wait40us:
#if US40_TICS > (US30_TICS + US10_TICS)
nop
#endif
rcall wait10us ;10us delay
wait30us:
#if US30_TICS > (US20_TICS + US10_TICS)
nop
#endif
rcall wait10us ;10us delay
wait20us:
#if US20_TICS > (2 * US10_TICS)
nop
#endif
rcall wait10us ;10us delay
wait10us: ;
#if US5_TICS >= RCALL_TICS
#if US10_TICS > (2 * US5_TICS)
nop
#endif
rcall wait5us
; at least 5us delay is possible
#if US1_TICS >= RCALL_TICS
; a 1us delay is also possible
#if NS500_TICS >= RCALL_TICS
wait5us:
#if US5_TICS > (US4_TICS + US1_TICS)
nop
#endif
rcall wait1us
wait4us:
#if US4_TICS > (US3_TICS + US1_TICS)
nop
#endif
rcall wait1us
wait3us:
#if US3_TICS > (US2_TICS + US1_TICS)
nop
#endif
rcall wait1us
wait2us:
#if US2_TICS > (2 * US1_TICS)
nop
#endif
rcall wait1us
wait1us:
; a 500ns delay is also possible with call
#if US1_TICS > (2 * NS500_TICS)
nop
#endif
rcall wait500ns
.global wait500ns
wait500ns:
#define INNER_TICS NS500_TICS
#else
#define INNER_TICS US1_TICS
wait5us:
#if US5_TICS > (US4_TICS + US1_TICS)
nop
#endif
rcall wait1us
wait4us:
#if US4_TICS > (US3_TICS + US1_TICS)
nop
#endif
rcall wait1us
wait3us:
#if US3_TICS > (US2_TICS + US1_TICS)
nop
#endif
rcall wait1us
wait2us:
#if US2_TICS > (2 * US1_TICS)
nop
#endif
rcall wait1us
wait1us:
#endif
#else
; wait5us is the inner body, 1us not possible
#define INNER_TICS US5_TICS
wait5us:
wait4us:
wait3us:
#if INNER_TICS < (RCALL_TICS * 2)
wait2us:
wait1us:
#else
#define LATE_2US
#endif
#endif
#else
; wait10us is the inner body
#define INNER_TICS US10_TICS
wait5us:
wait4us:
wait3us:
wait2us:
wait1us:
#endif
; Now we have to build the inner loop with INNER_TICS clock tics.
; The rcall and ret take RCALL_TICS clock tics (7 or 9).
#if INNER_TICS < RCALL_TICS
#error wait100ms can not build a function with 10us, F_CPU frequency too low!
#endif
;-----------------------------------------------------------------------------
#if INNER_TICS >= (RCALL_TICS * 4)
#define WAST_TICS3 ((INNER_TICS / 4) - RCALL_TICS)
; Build two nested loops waitinner1 and waitinner2
wait5us:
#if INNER_TICS > ((INNER_TICS/2) * 2)
nop
#endif
rcall waitinner2
waitinner2:
#ifdef LATE_2US
wait2us:
#endif
#if ((INNER_TICS / 2) - (2*(RCALL_TICS+WAST_TICS3))) > 0
nop
#endif
rcall waitinner1
waitinner1:
#ifdef LATE_2US
wait1us:
#endif
#if WAST_TICS3 > 1
nop
#endif
#if WAST_TICS3 > 0
nop
#endif
#else
; ################################## INNER_TICS < (RCALL_TICS * 4)
#if INNER_TICS >= (RCALL_TICS * 2)
#define WAST_TICS2 ((INNER_TICS - (2*RCALL_TICS)) / 2)
wait5us:
#if (INNER_TICS - (2*WAST_TICS2)) > (2*RCALL_TICS)
nop
#endif
rcall waitinner1
#ifdef LATE_2US
wait2us:
wait1us:
#endif
waitinner1:
#else
; ################################# INNER_TICS < (RCALL_TICS * 2)
#define WAST_TICS2 (INNER_TICS - RCALL_TICS)
#endif
#endif
#if WAST_TICS2 > 7
#warning wait1000ms: WAST_TICS2 > 7, delay times may be wrong!
#endif
#if WAST_TICS2 >= 6
rjmp . /* two additional tics */
#endif
#if WAST_TICS2 >= 4
rjmp . /* two additional tics */
#endif
#if WAST_TICS2 >= 2
rjmp . /* two additional tics */
#endif
#if ((WAST_TICS2 / 2) * 2) < WAST_TICS2
nop /* one additional tic */
#endif
ret
|
akshaybaweja/component-tester-oled
| 30,205
|
Source Code/GetESR_107.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include <avr/eeprom.h>
#include "config.h"
#include <stdlib.h>
.GLOBAL GetESR
.func GetESR
/* MAX_CNT is the maximum loop counter for repetition of mesurement */
#define MAX_CNT 128
/* ADC_Sleep_Mode enables the sleep state for reading ADC */
//#define ADC_Sleep_Mode
/* ESR_DEBUG enables additional Output on row 3 and row 4 */
//#define ESR_DEBUG
#ifdef INHIBIT_SLEEP_MODE
/* Makefile option set to disable the sleep mode */
#undef ADC_Sleep_Mode
#endif
#define zero_reg r1
// uint8_t big_cap;
#define big_cap 1
// unsigned long sumvolt0,sumvolt1,sumvolt2; // 3 sums of ADC readings
#define sumvolt0 2 /* r14-r17 */
#define sumvolt1 6 /* SP + 6:9 */
#define sumvolt2 10 /* SP + 10:13 */
// uint8_t LoADC; // used to switch Lowpin directly to GND or VCC
#define LoADC 14 /* SP + 14 */
// uint8_t HiADC; // used to switch Highpin directly to GND or VCC
#define HiADC 15 /* SP + 15 */
// unsigned int adcv[3]; // array for 3 ADC readings
// first part adcv0 r2/r3
// first part adcv1 Y+16/17
#define adcvv1 16
// first part adcv2 Y+18/19
#define adcvv2 18
// unsigned long cap_val_nF; // capacity in nF
#define cap_val_nF 20 /* SP + 20:23 */
#define adcv0L r2
#define adcv0H r3
#define adcv2L r24
#define adcv2H r25
// uint8_t HiPinR_L; // used to switch 680 Ohm to HighPin
#define HiPinR_L r12
// uint8_t LoPinR_L; // used to switch 680 Ohm to LowPin
#define LoPinR_L r7
// uint8_t ii,jj; // tempory values
// uint8_t StartADCmsk; // Bit mask to start the ADC
#define StartADCmsk r10
// uint8_t SelectLowPin;
#define SelectLowPin r6
// uint8_t SelectHighPin;
#define SelectHighPin r11
// int8_t esr0; // used for ESR zero correction
// #define esr0 r2
// Structure cap:
.extern cap
#define cval_max 4
#define esr 12
#define ca 16
#define cb 17
#define cpre_max 19
.extern EE_ESR_ZERO
#ifdef ADC_Sleep_Mode
// #define StartADCwait() ADCSRA = (1<<ADEN) | (1<<ADIF) | (1<<ADIE) | AUTO_CLOCK_DIV; /* enable ADC and Interrupt */
// set_sleep_mode(SLEEP_MODE_ADC);
// sleep_mode() /* Start ADC, return if ADC has finished */
.macro StartADCwait
ldi r24, (1 << SM0) | (1 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
sleep; /* wait for ADC */
ldi r24, (1 << SM0) | (0 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
.endm
#else
// #define StartADCwait() ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable ADC and start */
.macro StartADCwait
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk = r10 */
lds r24, ADCSRA; /* while (ADCSRA & (1 <<ADSC)) */
sbrc r24, ADSC;
rjmp .-8 ; /* wait until conversion is done */
.endm
#endif
/* ************************************************************************************ */
/* Adjust the timing for switch off the load current for big capacitors */
/* ************************************************************************************ */
// with wdt_reset the timing can be adjusted,
// when time is too short, voltage is down before SH of ADC
// when time is too long, capacitor will be overloaded.
// That will cause too high voltage without current.
.macro DelayBigCap
call wait10us; // SH at 2.5 ADC clocks behind start = 20 us
call wait5us
#ifdef ADC_Sleep_Mode
/* Wake up from sleep with Interrupt: 1+4+4T, jmp, rti, ldi, out takes 18 clock tics, */
/* 3+1 clock tics (sts,out) are needed for instructions before the current is switched off. */
#if F_CPU == 8000000UL
call wait2us; /* wait2us(); // with only 17 us delay the voltage goes down before SH */
/* delay 17us + 3 clock tics (CALL instead of RCALL) = 17.375 us @ 8 MHz */
/* + 22 clock tics delay from interrupt return, +2.75us = 20.125 + */
/* 19.875 us - */ /* 20.0 us ? */
#endif
#if F_CPU == 16000000UL
call wait3us; /* wait3us(); // with only 18 us delay the voltage goes down before SH */
/* delay 18us + 3 clock tics (CALL instead of RCALL) = 18.1875 us */
/* + 22 clock tics delay from interrupt return, +1.375us = 19.5625 us */
call wait500ns; /* wait500ns(); // 20.125 us + */
/* 19.9375 us - */ /* 20.0625 us ? */ /* 20.1875 us + */
#endif
#else
/* Polling mode: lds,sbrc,sts and out Instructions are 7 clock tics */
#if F_CPU == 8000000UL
call wait4us; // with only 18 us delay the voltage goes down before SH
/* delay 19us + 3 clock tics (CALL instead of RCALL) = 19.375 us @ 8 MHz */
/* + 7 clock tics delay from while loop, +0.875us = 20.25 us + */
/* 19.875us - */ /* 20.0 us ? */ /* 20.125us + */
#endif
#if F_CPU == 16000000UL
call wait4us; // with only 18 us delay the voltage goes down before SH
/* delay 19us + 3 clock tics (CALL instead of RCALL) = 19.1875 us */
/* + 7 clock tics delay from while loop, +0.4375us = 19.625 us */
push r24; /* 19.75 us */
pop r24; /* 19.875 us */
wdr ; /* wdt_reset(); // 19.9375us */
wdr ; /* wdt_reset(); // 20.0 us - */
wdr ; /* wdt_reset(); // 20.0625us ? */
wdr ; /* wdt_reset(); // 20.125 us + */
#endif
#endif
.endm
/* ************************************************************************************ */
/* Adjust the timing for switch off the load current for small capacitors */
/* ************************************************************************************ */
.macro DelaySmallCap
#ifdef ADC_Sleep_Mode
/* Wake up from sleep with Interrupt: 1+4+4T, jmp, rti, ldi, out takes 18 clock tics, */
/* 5+1 clock tics (sts,rjmp,out) are needed for instructions before the current is switched off. */
#if F_CPU == 8000000UL
/* Restart from sleep needs more than 2us, that is more than one ADC-clock tic in fast mode. */
/* More than one clock delay for the restart of ADC is required, 3.5 instead of 2.5 ADC clock delay */
call wait4us; /* wait4us(); // with only 3 us delay the voltage goes down before SH */
/* delay 4us + 1 clock tics (CALL instead of RCALL) = 4.125 us @ 8 MHz */
/* + 24 clock tics delay from interrupt return, +3.0us = 7.125 us + */
/* 6.75us - */ /* 6.875us ? */ /* 7.0us + */
#endif
#if F_CPU == 16000000UL
call wait3us; /* wait3us(); // with only 3 us delay the voltage goes down before SH */
/* delay 3us + 1 clock tics (CALL instead of RCALL) = 3.0625 us */
/* + 24 clock tics delay from interrupt return, +1.5us = 4.5625 us */
call wait500ns; /* wait500ns(); // 5.125 us + */
/* 4.9375us - */ /* 5.0625us ? */ /* 5.1875 us + */
#endif
#else
/* Polling mode, lds,sbrc,sts,rjmp and out Instructions are 9 clock tics */
#if F_CPU == 8000000UL
call wait4us; // with only 3 us delay the voltage goes down before SH
/* delay 4us + 1 clock tic (CALL instead of RCALL) = 4.125 us @ 8 MHz */
/* + 9 clock tics delay from while loop, +1.125us = 5.25 us + */
/* 4.875us - */ /* 5.0 us ? */ /* 5.125us + */
#endif
#if F_CPU == 16000000UL
call wait4us; // with only 18 us delay the voltage goes down before SH
/* delay 4us + 1 clock tics (CALL instead of RCALL) = 4.0625 us */
/* + 9 clock tics delay from while loop, +0.5625us = 4.625 us */
push r24; /* 4.8125 us */
pop r24; /* 4.9375 us */
wdr ; /* wdt_reset(); // 5.0 us - */
wdr ; /* wdt_reset(); // 5.0625us ? */
wdr ; /* wdt_reset(); // 5.125 us + */
#endif
#endif
.endm
//=================================================================
//=================================================================
//void GetESR() {
.section .text
GetESR:
push r2
push r3
push r4
push r5
push r6
push r7
push r8
push r9
push r10
push r11
push r12
push r13
push r14
push r15
push r16
push r17
push r29
push r28
in r28, _SFR_IO_ADDR(SPL);
in r29, _SFR_IO_ADDR(SPH);
sbiw r28, 0x1a;
in r0, _SFR_IO_ADDR(SREG);
cli
out _SFR_IO_ADDR(SPH), r29;
out _SFR_IO_ADDR(SREG), r0;
out _SFR_IO_ADDR(SPL), r28;
lds r18, cap+cval_max; /* cap_val_nF = cap.cval_max; */
lds r19, cap+cval_max+1;
lds r20, cap+cval_max+2;
lds r21, cap+cval_max+3;
lds r17, cap+cpre_max; /* prefix = cap.cpre_max; */
rjmp ad_35ba;
ad_35ac:
movw r24, r20; /* cval /= 10; // reduce value by factor ten */
movw r22, r18
ldi r18, 0x0A; 10
mov r19, zero_reg
mov r20, zero_reg
mov r21, zero_reg
call __udivmodsi4; /* r18:21 = r22:25 / r18:21 */
subi r17, 0xFF; /* prefix++; // take next decimal prefix */
ad_35ba:
cpi r17, -9; /* while (prefix < -9) { // set cval to nF unit */
brlt ad_35ac; /* } */
std Y+cap_val_nF, r18
std Y+cap_val_nF+1, r19
std Y+cap_val_nF+2, r20
std Y+cap_val_nF+3, r21
cpi r18, lo8(1800/4); /* if (cap_val_nF < (1800/4)) return; //capacity lower than 1.8 uF */
ldi r22, hi8(1800/4)
cpc r19, r22
cpc r20, zero_reg
cpc r21, zero_reg
brcc ad_35e4
rjmp ad_exit;
ad_35e4:
#ifdef ADC_Sleep_Mode
ldi r24, (1 << SM0) | (1 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
#endif
cpi r18, lo8((1800*2)+1); /* if (cap_val_nF > (1800*2)) { */
ldi r23, hi8((1800*2)+1);
cpc r19, r23
cpc r20, zero_reg
cpc r21, zero_reg
brcs ad_35fe
ldi r24, 0x01; 1
std Y+big_cap, r24; /* big_cap = 1; */
cpi r18, lo8(50000); /* if (cap_val_nF > (50000)) { */
ldi r23, hi8(50000);
cpc r19, r23
cpc r20, zero_reg
cpc r21, zero_reg
brcs not_very_big
ldi r24, 0x02; 2
std Y+big_cap, r24; /* big_cap = 2; // very big capacitor */
not_very_big:
/* normal ADC-speed, ADC-Clock 8us */
#ifdef ADC_Sleep_Mode
ldi r25, (1<<ADEN) | (1<<ADIF) | (1<<ADIE) | AUTO_CLOCK_DIV; /* enable ADC and Interrupt */
mov StartADCmsk, r25
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#else
ldi r18, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable and start ADC */
mov StartADCmsk, r18
#endif
rjmp ad_3604; /* } else { */
ad_35fe:
/* fast ADC-speed, ADC-Clock 2us */
#ifdef ADC_Sleep_Mode
ldi r25, (1<<ADEN) | (1<<ADIF) | (1<<ADIE) | FAST_CLOCK_DIV; /* enable ADC and Interrupt */
mov StartADCmsk, r25
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#else
ldi r25, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | FAST_CLOCK_DIV; /* enable and start ADC */
mov StartADCmsk, r25
#endif
std Y+big_cap, zero_reg; /* big_cap = 0 */
/* } */
ad_3604:
ldi r24, lo8(ESR_str);
ldi r25, hi8(ESR_str);
#ifdef USE_EEPROM
call lcd_fix_string; /* lcd_MEM_string(ESR_str); // " ESR=" */
#else
call lcd_mem_string; /* lcd_MEM_string(ESR_str); // " ESR=" */
#endif
lds r14, cap+ca; /* LoADC = pgm_read_byte(&PinADCtab[cap.ca]) | TXD_MSK; */
mov SelectLowPin,r14
LDIZ PinADCtab;
add r30, r14
adc r31, zero_reg
lpm r24, Z+;
ori r24, TXD_MSK;
std Y+LoADC, r24;
lds r15, cap+cb; /* HiADC = pgm_read_byte(&PinADCtab[cap.cb]) | TXD_MSK; */
mov SelectHighPin,r15
LDIZ PinADCtab;
add r30, r15
adc r31, zero_reg
lpm r24, Z+;
ori r24, TXD_MSK;
std Y+HiADC, r24;
LDIZ PinRLtab; /* LoPinR_L = pgm_read_byte(&PinRLtab[cap.ca]); //R_L mask for LowPin R_L load */
add r30, r14
adc r31, zero_reg
lpm LoPinR_L, Z+;
LDIZ PinRLtab; /* HiPinR_L = pgm_read_byte(&PinRLtab[cap.cb]); //R_L mask for HighPin R_L load */
add r30, r15
adc r31, zero_reg
lpm HiPinR_L, Z+;
#if (PROCESSOR_TYP == 644) || (PROCESSOR_TYP == 1280)
/* ATmega640/1280/2560 1.1V Reference with REFS0=0 */
// SelectLowPin = (cap.ca | (1<<REFS1) | (0<<REFS0)); // switch ADC to LowPin, Internal Ref.
ldi r25, (1<<REFS1)|(0<<REFS0); 0xC0
or SelectLowPin, r25
// SelectHighPin = (cap.cb | (1<<REFS1) | (0<<REFS0)); // switch ADC to HighPin, Internal Ref.
or SelectHighPin, r25
#else
// SelectLowPin = (cap.ca | (1<<REFS1) | (1<<REFS0)); // switch ADC to LowPin, Internal Ref.
ldi r25, (1<<REFS1)|(1<<REFS0); 0xC0
or SelectLowPin, r25
// SelectHighPin = (cap.cb | (1<<REFS1) | (1<<REFS0)); // switch ADC to HighPin, Internal Ref.
or SelectHighPin, r25
#endif
// Measurement of ESR of capacitors AC Mode
ldi r24, 0x01; /* sumvolt0 = 1; // set sum of LowPin voltage to 1 to prevent divide by zero */
mov r14, r24
mov r15, zero_reg
mov r16, zero_reg
mov r17, zero_reg
std Y+sumvolt1, r24; /* sumvolt1 = 1; // clear sum of HighPin voltage with current */
// // offset is about (x*10*200)/34000 in 0.01 Ohm units
std Y+sumvolt1+1, zero_reg;
std Y+sumvolt1+2, zero_reg;
std Y+sumvolt1+3, zero_reg;
std Y+sumvolt2, zero_reg; /* sumvolt2 = 0; // clear sum of HighPin voltage without current */
std Y+sumvolt2+1, zero_reg;
std Y+sumvolt2+2, zero_reg;
std Y+sumvolt2+3, zero_reg;
call EntladePins; /* EntladePins(); // discharge capacitor */
ldi r24, TXD_VAL;
out _SFR_IO_ADDR(ADC_PORT), r24; /* ADC_PORT = TXD_VAL; // switch ADC-Port to GND */
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; // set Mux input and Voltage Reference to internal 1.1V */
#ifdef NO_AREF_CAP
call wait100us; /* time for voltage stabilization */
#else
call wait10ms; /* time for voltage stabilization with 100nF */
#endif
// Measurement frequency is given by sum of ADC-Reads < 680 Hz for normal ADC speed.
// For fast ADC mode the frequency is below 2720 Hz (used for capacity value below 3.6 uF).
// ADC Sample and Hold (SH) is done 1.5 ADC clock number after real start of conversion.
// Real ADC-conversion is started with the next ADC-Clock (125kHz) after setting the ADSC bit.
eor r13, r13; /* for(ii=0;ii<MAX_CNT;ii++) { */
// when time is too short, voltage is down before SH of ADC
// when time is too long, capacitor will be overloaded.
// That will cause too high voltage without current.
ldi r27, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | FAST_CLOCK_DIV; /* enable ADC and start with ADSC */
mov r9, r27
// adcv[0] = ADCW; // Voltage LowPin with current
// ADMUX = SelectHighPin;
ldi r26, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable ADC and start with ADSC */
mov r8, r26
/* ********* Forward direction, connect Low side with GND *********** */
ad_3692:
ldd r19, Y+LoADC;
out _SFR_IO_ADDR(ADC_DDR), r19; /* ADC_DDR = LoADC; // switch Low-Pin to output (GND) */
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; */
StartADCwait /* start ADC and wait */
;======= /* while (1) { */
while_lop1:
wdr ; /* wdt_reset(); */
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; */
out _SFR_IO_ADDR(R_PORT), HiPinR_L; /* R_PORT = HiPinR_L; // switch R-Port to VCC */
out _SFR_IO_ADDR(R_DDR), HiPinR_L; /* R_DDR = HiPinR_L; // switch R_L port for HighPin to output (VCC) */
StartADCwait /* start ADC and wait */
StartADCwait /* start ADC and wait */
lds adcv0L, ADCW; /* adcv[0] = ADCW; // Voltage LowPin with current */
lds adcv0H, ADCW+1
sts ADMUX, SelectHighPin; /* ADMUX = SelectHighPin; */
ldd r20, Y+big_cap; /* if (!big_cap) { */
and r20, r20
brne ad_big1
/* **** Polling mode, small cap **** */
StartADCwait /* start ADC and wait */
sts ADCSRA, r9; /* ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | FAST_CLOCK_DIV; // enable ADC and start */
DelaySmallCap; /* wait the time defined by macro */
rjmp ad_swoff1; /* } else { */
ad_big1:
/* **** Polling mode, big cap **** */
StartADCwait /* start ADC and wait */
// Start Conversion, real start is next rising edge of ADC clock
sts ADCSRA, r8; /* ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; // enable ADC and start */
DelayBigCap; /* wait the time defined by macro */
/* } */
ad_swoff1:
out _SFR_IO_ADDR(R_DDR), zero_reg; /* R_DDR = 0; // switch current off, SH is 1.5 ADC clock behind real start */
out _SFR_IO_ADDR(R_PORT), zero_reg; /* R_PORT = 0; */
ad_370c:
lds r24, ADCSRA; /* while (ADCSRA&(1<<ADSC)); // wait for conversion finished */
sbrc r24, ADSC
rjmp ad_370c
lds r18, ADCW; /* adcv[1] = ADCW; // Voltage HighPin with current */
lds r19, ADCW+1;
#ifdef ADC_Sleep_Mode
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#endif
StartADCwait /* start ADC and wait */
StartADCwait /* start ADC and wait */
lds r24, ADCW; /* adcv[2] = ADCW; // Voltage HighPin without current */
lds r25, ADCW+1;
cpi r24, 0x03; /* if (adcv[2] > 2) break; // at least more than two digits required */
cpc r25, zero_reg
brcc end_while1;
rjmp while_lop1; /* } // end while (1) */
;=======
end_while1:
// sumvolt0 += adcv[0]; // add sum of both LowPin voltages with current
// adcv0 = r2/r3
// sumvolt1 += adcv[1]; // add HighPin voltages with current
// adcv1 = r18/r19
std Y+adcvv1, r18;
std Y+adcvv1+1, r19;
// sumvolt2 += adcv[2]; // capacitor voltage without current
// adcv2 = R24/r25
std Y+adcvv2, r24;
std Y+adcvv2+1, r25;
/* ********* Reverse direction, connect High side with GND *********** */
ldd r19, Y+HiADC; /* ADC_DDR = HiADC; // switch High Pin to GND */
out _SFR_IO_ADDR(ADC_DDR), r19;
StartADCwait /* start ADC and wait */
;======= /* while (1) { */
while_lop2:
wdr ; /* wdt_reset(); */
sts ADMUX, SelectHighPin; /* ADMUX = SelectHighPin; */
out _SFR_IO_ADDR(R_PORT), LoPinR_L; /* R_PORT = LoPinR_L; */
out _SFR_IO_ADDR(R_DDR), LoPinR_L; /* R_DDR = LoPinR_L; // switch LowPin with 680 Ohm to VCC */
StartADCwait /* start ADC and wait */
StartADCwait /* start ADC and wait */
lds r22, ADCW; /* adcv[0] = ADCW; // Voltage HighPin with current */
lds r23, ADCW+1;
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; */
ldd r20, Y+big_cap ; /* if (!big_cap) { */
and r20, r20
brne ad_big2
// ****** Polling mode small cap
StartADCwait /* start ADC and wait */
sts ADCSRA, r9; /* ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | FAST_CLOCK_DIV; // enable ADC and start */
DelaySmallCap; /* wait the time defined by macro */
rjmp ad_swoff2; /* } else { */
ad_big2:
// ****** Polling mode big cap
StartADCwait /* start ADC and wait */
sts ADCSRA, r8; /* ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; // enable ADC and start with ADSC */
DelayBigCap; /* wait the time defined by macro */
/* } */
ad_swoff2:
out _SFR_IO_ADDR(R_DDR), zero_reg; // switch current off, SH is 1.5 ADC clock ticks behind real start
out _SFR_IO_ADDR(R_PORT), zero_reg;
ad_37f4:
lds r24, ADCSRA; /* while (ADCSRA&(1<<ADSC)); // wait for conversion finished */
sbrc r24, ADSC
rjmp ad_37f4
lds r20, ADCW; /* adcv[1] = ADCW; // Voltage LowPin with current */
lds r21, ADCW+1;
#ifdef ADC_Sleep_Mode
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#endif
StartADCwait /* start ADC and wait */
StartADCwait /* start ADC and wait */
lds r18, ADCW; /* adcv[2] = ADCW; // Voltage LowPin without current */
lds r19, ADCW+1;
cpi r18, 0x03; /* if (adcv[2] > 2) break; // at least more than two digits required */
cpc r19, zero_reg
brcc end_while2;
rjmp while_lop2; /* } // end while (1) */
;=======
end_while2:
out _SFR_IO_ADDR(R_DDR), zero_reg; /* R_DDR = 0; // switch current off */
movw r24, r22; /* sumvolt0 += adcv[0]; // add LowPin voltages with current */
add r24, adcv0L; /* // add sum of both LowPin voltages with current */
adc r25, adcv0H
add r14, r24
adc r15, r25
adc r16, zero_reg
adc r17, zero_reg
std Y+sumvolt0, r14
std Y+sumvolt0+1, r15
std Y+sumvolt0+2, r16
std Y+sumvolt0+3, r17
ldd r24, Y+adcvv1; /* sumvolt1 += adcv[1]; // add HighPin voltages with current */
ldd r25, Y+adcvv1+1;
add r24, r20
adc r25, r21
ldd r20, Y+sumvolt1; /* sumvolt1 += adcv[1]; // add HighPin voltages with current */
ldd r21, Y+sumvolt1+1;
ldd r22, Y+sumvolt1+2;
ldd r23, Y+sumvolt1+3;
add r20, r24
adc r21, r25
adc r22, zero_reg
adc r23, zero_reg
std Y+sumvolt1, r20;
std Y+sumvolt1+1, r21;
std Y+sumvolt1+2, r22;
std Y+sumvolt1+3, r23;
ldd r24, Y+adcvv2; /* // add HighPin voltages without current */
ldd r25, Y+adcvv2+1; 0x11
add r24, r18
adc r25, r19
ldd r20, Y+sumvolt2; /* sumvolt2 += adcv[2]; // add HighPin voltages without current */
ldd r21, Y+sumvolt2+1;
ldd r22, Y+sumvolt2+2;
ldd r23, Y+sumvolt2+3;
add r20, r24
adc r21, r25
adc r22, zero_reg
adc r23, zero_reg
std Y+sumvolt2, r20 ;
std Y+sumvolt2+1, r21;
std Y+sumvolt2+2, r22;
std Y+sumvolt2+3, r23;
// Measurement frequency is given by sum of ADC-Reads < 680 Hz for normal ADC speed.
// For fast ADC mode the frequency is below 2720 Hz (used for capacity value below 3.6 uF).
// ADC Sample and Hold (SH) is done 1.5 ADC clock number after real start of conversion.
// Real ADC-conversion is started with the next ADC-Clock (125kHz) after setting the ADSC bit.
inc r13; /* for( ;ii<MAX_CNT;ii++) */
mov r21, r13
cpi r21, MAX_CNT;
breq ad_38ac
rjmp ad_3692; /* } // end for */
ad_38ac:
#ifdef ESR_DEBUG
movw r22, r14; /* DisplayValue(sumvolt0,0,'L',4); */
movw r24, r16;
ldi r20, 0;
ldi r18, 'L';
ldi r16, 4 ;
call DisplayValue
#endif
ldd r10, Y+cap_val_nF;
ldd r11, Y+cap_val_nF+1;
ldd r12, Y+cap_val_nF+2;
ldd r13, Y+cap_val_nF+3;
ldd r22, Y+big_cap; /* if (big_cap) { */
and r22, r22
breq is_small
// HighPin Voltage, which is usually 2 * 14 * 8 us = 224 us.
// With the loading of the capacitor the current will sink, so we get a too high voltage at
// the LowPin. The velocity of degration is inversely proportional to time constant (represented by capacity value).
// Time constant for 1uF & 720 Ohm is 720us
// // sumvolt0 -= (sumvolt0 * 150UL) / cap_val_nF; // Version 1.04k
ldi r18, lo8(310); /* sumvolt0 -= (sumvolt0 * 345UL) / cap_val_nF; */
ldi r19, hi8(310);
rjmp ad_38dc /* } else { */
is_small:
ldi r18, lo8(105); /* sumvolt0 -= (sumvolt0 * 105UL) / cap_val_nF; */
ldi r19, hi8(105);
ad_38dc:
ldi r20, 0x00;
ldi r21, 0x00;
ldd r22, Y+sumvolt0
ldd r23, Y+sumvolt0+1
ldd r24, Y+sumvolt0+2
ldd r25, Y+sumvolt0+3
call __mulsi3; /* r22:25 = r22:25 * r18:21 */
movw r18, r10; /* cap_val_nF */
movw r20, r12
call __udivmodsi4; /* r18:21 = r22:25 / r18:21 */
ldd r10, Y+sumvolt0;
ldd r11, Y+sumvolt0+1;
ldd r12, Y+sumvolt0+2;
ldd r13, Y+sumvolt0+3;
sub r10, r18; /* r10:13 == sumvolt0 -= */
sbc r11, r19
sbc r12, r20
sbc r13, r21 /* } */
#ifdef ESR_DEBUG
call lcd_line3;
ldd r22, Y+sumvolt1; /* DisplayValue(sumvolt1,0,'H',4); */
ldd r23, Y+sumvolt1+1;
ldd r24, Y+sumvolt1+2; 0
ldi r25, 0x00; 0
ldi r20, 0;
ldi r18, 'H';
ldi r16, 4 ;
call DisplayValue
ldi r24, ' '
call lcd_data
#endif
ldi r24, lo8(EE_ESR_ZERO); /* esr0 = (int8_t)eeprom_read_byte(&EE_ESR_ZERO); */
ldi r25, hi8(EE_ESR_ZERO);
call eeprom_read_byte;
mov r2, r24
// // sumvolt0 += (((long)sumvolt0 * esr0) / (RRpinMI * 10)); // subtract 0.23 Ohm from ESR, Vers. 1.04k
// sumvolt2 += (((long)sumvolt0 * esr0) / (RRpinMI * 10)); // subtract 0.23 Ohm from ESR
mov r22, r24
eor r23, r23
sbrc r22, 7
com r23
mov r24, r23
mov r25, r23
movw r18, r10; /* sumvolt0 */
movw r20, r12;
call __mulsi3; /* r22:25 = r22:25 * r18:21 */
#if RRpinMI == PIN_RM
ldi r18, lo8(RRpinMI*10)
ldi r19, hi8(RRpinMI*10)
#else
lds r4, RRpinMI
lds r5, RRpinMI+1
add r4,r4; RRpinMI*2
adc r5,r5
movw r18,r4
ldi r30,4
ad_3924:
add r18,r4; + (2*RRpinMI)
adc r19,r5
dec r30
brne ad_3924
#endif
movw r4,r18; /* r4:5 = 10 * RRpinMI */
ldi r20, 0x00;
ldi r21, 0x00;
call __divmodsi4; /* r18:21 = r22:25 / r18:21 */
ldd r24, Y+sumvolt2 ;
ldd r25, Y+sumvolt2+1;
ldd r26, Y+sumvolt2+2;
ldd r27, Y+sumvolt2+3;
add r18, r24 /* r18 == sumvolt2 += */
adc r19, r25
adc r20, r26
adc r21, r27
std Y+sumvolt2, r18;
std Y+sumvolt2+1, r19;
std Y+sumvolt2+2, r20;
std Y+sumvolt2+3, r21;
#ifdef ESR_DEBUG
movw r22, r10; /* DisplayValue(sumvolt0,0,'C',4); */
movw r24, r12;
ldi r20, 0;
ldi r18, 'C';
ldi r16, 4 ;
call DisplayValue
#endif
ldd r6, Y+sumvolt1; /* if (sumvolt1 > sumvolt0) { */
ldd r7, Y+sumvolt1+1;
ldd r8, Y+sumvolt1+2;
ldd r9, Y+sumvolt1+3;
cp r10, r6
cpc r11, r7
cpc r12, r8
cpc r13, r9
brcc ad_396c
sub r6, r10; /* sumvolt1 -= sumvolt0; // difference HighPin - LowPin Voltage with current */
sbc r7, r11
sbc r8, r12
sbc r9, r13
rjmp ad_3972; /* } else { */
ad_396c:
eor r6, r6; /* sumvolt1 = 0; */
eor r7, r7
movw r8, r6
ad_3972:
#ifdef ESR_DEBUG
call lcd_line4;
movw r22, r6; /* DisplayValue(sumvolt1,0,'d',4); */
movw r24, r8
ldi r20, 0;
ldi r18, 'd';
ldi r16, 4 ;
call DisplayValue
ldi r24, ' '
call lcd_data
ldd r22, Y+sumvolt2; /* DisplayValue(sumvolt2,0,' ',4); */
ldd r23, Y+sumvolt2+1;
ldd r24, Y+sumvolt2+2;
ldd r25, Y+sumvolt2+3;
ldi r20, 0;
ldi r18, ' ';
ldi r16, 4 ;
call DisplayValue
#endif
movw r22, r4
ldi r24, 0x00;
ldi r25, 0x00; /* r22:25 = 10 * (unsigned long)RRpinMI) */
/* jj = 0; */
ldd r14, Y+sumvolt2; /* if (sumvolt1 >= sumvolt2) { */
ldd r15, Y+sumvolt2+1;
ldd r16, Y+sumvolt2+2;
ldd r17, Y+sumvolt2+3;
cp r6, r14; /* r6:9 = sumvolt1 */
cpc r7, r15
cpc r8, r16
cpc r9, r17
brcs ad_39c0
// mean voltage at the capacitor is higher with current
// sumvolt0 is the sum of voltages at LowPin, caused by output resistance of Port
// RRpinMI is the port output resistance in 0.1 Ohm units.
// we scale up the difference voltage with 10 to get 0.01 Ohm units of ESR
/* cap.esr = ((sumvolt1 - sumvolt2) * 10 * (unsigned long)RRpinMI) / sumvolt0; */
movw r18, r6
movw r20, r8
sub r18, r14; /* sumvolt1 - sumvolt2 */
sbc r19, r15
sbc r20, r16
sbc r21, r17
call __mulsi3; /* r22:25 = r22:25 * r18:21 */
movw r18, r10; /* r10:13 = sumvolt0 */
movw r20, r12
call __udivmodsi4; /* r18:21 = r22:25 / r18:21 */
sts cap+esr, r18;
sts cap+esr+1, r19;
movw r22, r18; /* DisplayValue(cap.esr,-2,LCD_CHAR_OMEGA,2); */
ldi r24, 0x00; 0
ldi r25, 0x00; 0
ldi r20, -2 ; 254
ldi r18, LCD_CHAR_OMEGA;
ldi r16, 2 ;
call DisplayValue
rjmp ad_exit; /* } else { */
ad_39c0:
/* jj = ((sumvolt2 - sumvolt1) * 10 * (unsigned long)RRpinMI) / sumvolt0; */
movw r18, r14
movw r20, r16
sub r18, r6
sbc r19, r7
sbc r20, r8
sbc r21, r9
call __mulsi3; /* r22:25 = r22:25 * r18:21 */
movw r18, r10
movw r20, r12
call __udivmodsi4; /* r18:21 = r22:25 / r18:21 */
mov r17, r18
ldi r24,'0'; /* lcd_data('0'); */
call lcd_data
mov r24, r17; /* if ((jj < 100) && (jj > 0)) { */
subi r24, 0x01; 1
cpi r24, 0x63; 99
brcc ad_exit;
ldd r19, Y+big_cap; /* if (big_cap != 2) { */
cpi r19, 0x02; /* (cap_val_nF > (50000)) */
brne ad_3a0e
ldi r24,'?'; /* lcd_data('?'); // mark ESR zero correction */
call lcd_data
mov r22, r2; /* esr0 -= jj; // correct ESR_ZERO by negative resistance */
sub r22, r17
ldi r24, lo8(EE_ESR_ZERO); /* eeprom_write_byte((uint8_t *)(&EE_ESR_ZERO), (int8_t)esr0); */
ldi r25, hi8(EE_ESR_ZERO); /* // fix new zero offset */
call eeprom_write_byte
rjmp ad_exit; /* } else { */
ad_3a0e:
ldi r24,'!'; /* lcd_data('!'); // mark ESR zero without correction */
call lcd_data
// return; /* } } } */
ad_exit:
#ifdef ADC_Sleep_Mode
out _SFR_IO_ADDR(SMCR), zero_reg; /* SMCR = 0 */
#endif
adiw r28, 0x1a; 26
in r0, _SFR_IO_ADDR(SREG); 63
cli
out _SFR_IO_ADDR(SPH), r29; 62
out _SFR_IO_ADDR(SREG), r0; 63
out _SFR_IO_ADDR(SPL), r28; 61
pop r28
pop r29
pop r17
pop r16
pop r15
pop r14
pop r13
pop r12
pop r11
pop r10
pop r9
pop r8
pop r7
pop r6
pop r5
pop r4
pop r3
pop r2
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 1,658
|
Source Code/get_log.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include "config.h"
#include <stdlib.h>
#include "config.h"
#define Log_Tab_Distance 20
.GLOBAL get_log
.func get_log
.extern LogTab
.section .text
; // get_log interpolate a table with the function -1000*log(1 - (permil/1000))
; uint16_t get_log(uint16_t permil) {
get_log:
push r28
push r29
ldi r18, lo8(Log_Tab_Distance) ;0x14
ldi r19, hi8(Log_Tab_Distance) ;0x00
movw r22, r18
call __udivmodhi4 ; tabind = permil / Log_Tab_Distance; // index to table
movw r26, r24
; r26:27 = tabres = permil % Log_Tab_Distance; // fraction of table distance
; // interpolate the table of factors
; y1 = pgm_read_word(&LogTab[tabind]); // get the lower table value
LDIZ LogTab;
add r30, r22
adc r31, r23
add r30, r22
adc r31, r23 ; &LogTab[tabind]
lpm r28, Z+ ; y1 = pgm_read_word(&LogTab[tabind]); // get the lower table value
lpm r29, Z+
lpm r20, Z+ ; y2 = pgm_read_word(&LogTab[tabind+1]); // get the higher table value
lpm r21, Z+
; result = ((y2 - y1) * tabres ) / Log_Tab_Distance + y1; // interpolate
sub r20, r28 ; (y2 - y1)
sbc r21, r29 ; hi8(y2 - y1)
mul r20, r26 ; * tabres (maximum 19)
movw r24, r0 ; r24:25 = ((y2 - y1) * tabres )
mul r20, r27 ; hi8(tabres)
add r25, r0
mul r21, r26 ; hi8(y2 - Y1)
add r25, r0
eor r1, r1
movw r22, r18 ; Log_Tab_Distance
call __udivmodhi4 ; ((y2 - y1) * tabres ) / Log_Tab_Distance
add r22, r28 ; result = ((y2 - y1) * tabres ) / Log_Tab_Distance + y1; // interpolate
adc r23, r29
movw r24, r22 ; return(result);
pop r29
pop r28
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 14,195
|
Source Code/samplingADC.S
|
// June 2015 - Jan 2016, pa3fwm@amsat.org
#ifdef SamplingADC_CNT
#include "samplingADC_cnt.S" /* take replacement with counter1 use */
#else
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include "config.h"
#include <stdlib.h>
.GLOBAL samplingADC_freqgen
.func samplingADC_freqgen
.endfunc
.GLOBAL samplingADC_freqgen_sck
.func samplingADC_freqgen_sck
.endfunc
.GLOBAL samplingADC
.func samplingADC
#if (TICS_PER_ADC_CLOCK != 128) && (TICS_PER_ADC_CLOCK != 64)
#error Unsupported clock frequency
#endif
#define TICS_PER_ADC_CYCLE 13*TICS_PER_ADC_CLOCK
#define Lessdelay (256-2*TICS_PER_ADC_CLOCK)
.section .progmem.gcc
; We put this code not simply generically in .text, but in .progmem.gcc.
; Gcc's linker script forces this section to be immediately after the interrupt vectors,
; and it seems in case of the transistortester code nothing else ends up in this section.
; We also put the genfreq code at the start of this file, so it will be the first thing
; after the vectors. This guarantees that the condition on genfreq_jmpbase (see below) is satisfied.
#ifdef WITH_XTAL
genfreq:
; generate signal with frequency CPUclock / ( 8 + R11 + R10/256 )
; generate r19 periods
; to do this, we have a loop where we jump back to r27:31 in "normal" case, or (r27:31)-1 in case of "carry" of the fractional bits
mov r19, r0
ldi r27, lo8(gs(genfreq_jmpbase))
sub r27, r11
ldi r26, 0 ; accumulated backlog
push r30
push r31
ldi r31, hi8(gs(genfreq_jmpbase))
;
; NOTE: we assume that lo8(gs(genfreq_jmpbase)) > 8 so r31 never needs to be updated
; this is guaranteed due to the placement in .progmem.gcc, see the above comment.
;
nop
nop
nop
nop
nop
nop
nop
mov r30, r27
genfreq_jmpbase:
AOUT R_PORT, R18 ; = Rport_1
AOUT R_PORT, R14 ; = Rport_0
dec r19
breq genfreq_end1
add r26, r10
sbc r30, r1
ijmp
genfreq_end1:
AOUT R_DDR, R16 ; R_DDR = Rddr_1 ; switch to "active" state (relatively high impedance in case of crystal measurement) immediately after the last impulse, to preserve a positive DC component
pop r31
pop r30
sbrs r24, smplADC_sck ; should we short-circuit the DUT (crystal)?
rjmp genfreq_end
AIN r26, ADC_DDR
ori r26, (1<<TP1)|(1<<TP2)|(1<<TP3)
AOUT ADC_DDR,r26
rjmp genfreq_end
#endif
samplingADC:
samplingADC_freqgen:
samplingADC_freqgen_sck:
; prototypes for C declared in tt_function.h ; documentation is also there
;uint16_t samplingADC(R24:25 what, R22:23 array[], R20 nn, R18 Rport_1, R16 Rddr_1, R14 Rport_0, R12 Rddr_0, R10:11 freq, R8 shortcircuitduration ) {}
; the last two arguments are only used WITH_XTAL, and are optional (can be omitted if not needed; registers will not be clobbered)
#ifdef WITH_XTAL
push r4 ; r4:5 will be used for the high-pass filter
push r5
push r17
mov r5, r1
dec r5 ; set bit 7 in r5 to mark it for initialization
sbrs r24, smplADC_sck ; if we'll need to short-circuit the DUT later on, store the correct value of ADC_DDR in r9
rjmp L30a
push r9
AIN r9, ADC_DDR ;
L30a:
push r7
lds r7, ADMUX
#endif
; r25 is span
mov r30, r22 ; r31:r30 := ptr
mov r31, r23
cpi r25, 0 ; set nonsensical span of 0 to 1
brne L16
inc r25
L16:
AOUT R_PORT, R14 ; Rport_0
AOUT R_DDR, R12 ; Rddr_0
ldi r27, (1<<ADEN) | (1<<ADSC) | (1<<ADATE) | (1<<ADIF) | (0<<ADIE) | AUTO_CLOCK_DIV;
sts ADCSRA, r27 ; start first ADC with ext trigger, but start immediately also, to get done that first conversion which takes extra long
ldi r26, (1<<ADTS2) | (0<<ADTS1) | (1<<ADTS0);
sts ADCSRB, r26 ; trigger source is COUNTER1 compare match B
ldi r26, (1<<WGM12)
sts TCCR1B, r26 ; TCCR1B = 0; stop counter1
sts TCCR1A, r1 ; TCCR1A = 0; set counter1 to Clear Timer on Compare Match mode
ldi r26, 0xff
sts TCNT1H, r26 ; set initial counter to -1
sts TCNT1L, r26
ldi r26, (1<<OCF1B)|(1<<OCF1A)
sts TIFR1, r26 ; reset both counter compare interrupts, otherwise ADC might be started prematurely
sts OCR1BH, r1 ; schedule start of ADC cycle at counter=0, i.e., essentially immediately
sts OCR1BL, r1 ;
#ifdef WITH_XTAL
sbrs r24, smplADC_many ; if we have the long excitation
rjmp L20a
ldi r26, 3 ; schedule start of ADC cycle at counter=3*256
sts OCR1BH, r26
dec r26
sts TCNT1H, r26 ; and make sure TCNT1 is initialized sucht that this is still essentially immediately
ldi r26, 0xff
sts TCNT1L, r26
L20a:
#endif
#ifdef WITH_XTAL
; compute number of cycles for genfreq:
push r24 ; we need registers r24 and r25 for calling __udivmodhi4
push r25
ldi r25, 184/4 ; total duration should be at most 255 cycles, but there's some 66 cycles of overhead (determined experimentally)
sbrc r24, smplADC_many ; except in case of long set of pulses for crystal excitation, then
ldi r25, (184+3*256)/4 ; total duration should be at most 4*256 cycles
L20: ; note that we've divided r25:24 by 4 in the above, so it fits in 16 bits
ldi r24, 0
movw r22,r10
subi r23, -8 ; period is 8+r11+r10/256
lsr r23 ; divide period by 4 since we've divided duration by 4 too
ror r22
lsr r23
ror r22
call __udivmodhi4
mov r0,r22 ; store number of pulses in r0
inc r0 ; 1 more pulse than periods
pop r25
pop r24
#endif
; prepare timing and registers for main loop
; r27:26 will contain the TOP value for the counter, i.e., 1 less than the pulse-generation period
ldi r27, hi8(TICS_PER_ADC_CYCLE-1)
ldi r26, lo8(TICS_PER_ADC_CYCLE-1)
sub r26, r25 ; this defaults to 1663-span, but may need to be incremented if measurement will take longer due to large span
ldi r21, 1 ; r21 will contain number of ADC readings per pulse
mov r19, r25 ; load span into r19; total measurement will cover r19*nn tics, which is upperbounded by 256*r19
; one ADC cycle is 13*128 (or 13*64) tics, but we need some time for generating the pulse, so can fit say at most 10*128 = 5*256 tics (or 8*64 = 2*256; 10*64 isn't a multiple of 256, so would require more code)
; NEW: leave a bit more space so we can also do the long train of pulses for crystals
L14:
cpi r19, (1+10*TICS_PER_ADC_CLOCK/256) ; if "remaining" span <=5 (or <=2), we're fine, don't need to increase pulse generation period
#ifdef WITH_XTAL
sbrc r24, smplADC_many
cpi r19, (2+2*TICS_PER_ADC_CLOCK/256) ; in case of long pulse train: if "remaining" span <=3 (or <=2), we're fine, don't need to increase pulse generation period
#endif
brmi L13
subi r26, lo8(-TICS_PER_ADC_CYCLE) ; otherwise, extend pulse generation period by 1664
sbci r27, hi8(-TICS_PER_ADC_CYCLE)
inc r21 ; increment number of ADC readings per pulse
subi r19, 3*(TICS_PER_ADC_CLOCK/64) ; each extra ADC cycle included in pulse generation period makes space for 13*128 (or 13*64) tics; for simplicity we (safely) calculate as if it were 12*128 = 6*256 (or 12*64 = 3*256)
rjmp L14 ; check whether this was enough
L13:
sts OCR1AH, r27 ; store calculated TOP value for counter 1
sts OCR1AL, r26 ;
wait_adc:
lds r26, ADCSRA
sbrs r26, ADIF
rjmp wait_adc ; wait until the initial conversion finishes
ldi r27, (1<<ADEN) | (1<<ADATE) | (1<<ADIF) | (0<<ADIE) | AUTO_CLOCK_DIV;
sts ADCSRA, r27 ; reset ADC interrupt flag
ldi r26,(1<<OCIE1A)
sts TIMSK1, r26 ; disable counter1 compare B Interrupt (used to trigger ADC), enable counter1 compare A Interrupt (used to exit sleep to generate next pulse)
ldi r26, (1<<CS10)|(1<<WGM12)
sts TCCR1B, r26 ; start counter1 at full speed
ldi r22, 2 ; skip first ADC result since it is nonsense (it predates the start of the pulse or step)
ldi r26, 0 ; switch ADC to free-running mode (we can do that here because can be sure that by now it has been triggered)
sts ADCSRB, r26 ;
; we'll have counter1 counting up from 0 to about 1663 (or multiples of that)
; each time it overflows, we'll start our signal for "exciting" the DUT
; first sample will be taken 2*128 clockcycles after triggering
; so this whole signal generation procedure should take 256 clockcycles
; note: there's some uncertainty due to the unknown time the interrupt handler takes, which may be compiler-dependent
; at 8 MHz, the first sample is taken after only 128 clockcycles; this is taken into account via the Lessdelay macro
; we have the following excitation options, governed by the "what" parameter:
; - 0 (default): step (Rddr_0 -> Rddr_1) and optionally single pulse (Rport_1)
; - smplADC_freq: bunch of pulses via Rport_1
; - ... |smplADC_many: 4 times longer bunch of pulses via Rport_1
; - ... |smplADC_sck: short-circuit the DUT for a while after applying pulses
; - smplADC_direct: single pulse via the ADC pins, i.e. with no series resistance ("direct" pulse)
backtosleep:
ldi r26, (1<<SE)
sts SMCR, r26
sleep
; toggle output (back) to the idle state
AOUT R_PORT, R14 ; Rport_0
AOUT R_DDR, R12 ; Rddr_0
sbrs r24, smplADC_direct
rjmp stepresponse
; wait a bit less than 256 ticks; precise value determined experimentally, by looking at the sampled data and aligning start of response with first sample
#define Delay_pulse (201-Lessdelay)
ldi r26, (Delay_pulse/3)
#if Delay_pulse%3>0
nop
#endif
#if Delay_pulse%3>1
nop
#endif
L11: dec r26
brne L11
; do the "direct" pulse, i.e., apply the pulse via de ADC pins, with no series resistance
push r30
push r31
AIN r30, ADC_DDR ;
AIN r31, ADC_PORT ;
ldi r26, (1<<TP3) ;
sbrc R12, PIN_RL2 ; is the bit for TP2 resistor set?
ldi r26, (1<<TP2) ;
sbrc R12, PIN_RL1 ; ist the bit for TP3 resistor set?
ldi r26, (1<<TP1) ;
; r26 now hold the bit for the direct ADC port
mov r27, r31 ; ADC_PORT state
or r27, r26 ; r27 is the for ADC port with HiPin set to 1
or r26, r30 ; r26 enables the HiPin and LoPin output, ADC_DDR
AOUT ADC_PORT, r27 ; set Hipin to high
AOUT R_DDR, R16 ; R_DDR = Rddr1 open all resistor ports
AOUT ADC_DDR, r26 ; one clock tic high without resistor at HiPin, current about 5V/(42 Ohm)=119mA !!!
AOUT ADC_DDR, r30 ; disable the HiPin output
AOUT ADC_PORT, r31 ; reset Hipin to low
pop r31
pop r30
rjmp waitevent
backtosleep2:
jmp backtosleep
stepresponse:
#ifdef WITH_XTAL
sbrc r24,smplADC_freq
rjmp genfreq
#endif
stepresponse2:
; wait a bit less than 256 ticks; precise value determined experimentally
#ifdef WITH_XTAL
#define Delay_step (211-Lessdelay)
#else
#define Delay_step (214-Lessdelay)
#endif
ldi r26, (Delay_step/3)
#if Delay_step%3>0
nop
#endif
#if Delay_step%3>1
nop
#endif
L10: dec r26
brne L10
AOUT R_PORT, R18 ; = Rport_1
AOUT R_PORT, R14 ; = Rport_0
nop
; generate start of step signal
; this is (should be) aligned with the first sample
AOUT R_DDR, R16 ; R_DDR = Rddr_1
genfreq_end:
waitevent: ; waiting loop: we wait until either counter1 is almost going to be reset, or the AD converter has a result
lds r26, TCNT1L ; need to read TCNT1L to latch TCNT1H
lds r26, TCNT1H
lds r27, OCR1AH
inc r26
cp r26, r27 ; check if TCNT1H is getting near OCR1AH; if so, go to sleep to be sure not to miss the interrupt
brcc backtosleep2
#ifdef WITH_XTAL
sbrs r24, smplADC_sck ; are we doing a measurement involving short-circuiting the DUT (crystal)?
rjmp L26
cp r26, r8 ; then check whether it's getting time to end the short-circuit
brne L26 ; r8 determines how many times 256 clockcycles the short-circuit should last
L27: ; we enter this point up to 256 clockcycles early
lds r26, TCNT1L ; (need to read TCNT1L to latch TCNT1H)
lds r26, TCNT1H
cp r26, r8 ; busyloop until r26 exceeds r8; due to this busyloop there's a few cycles of uncertainty, but that doesn't matter for this application
breq L27
AOUT ADC_DDR,r9 ; set ADC_DDR back to its original non-shortcircuiting value
L26:
#endif
lds r26, ADCSRA ; otherwise:
sbrs r26, ADIF ; check if conversion done (interrupt flag is raised)
rjmp waitevent ; if not, go back to checking counter
; the ADC gives a result
ldi r27, (1<<ADEN) | (1<<ADATE) | (1<<ADIF) | (0<<ADIE) | AUTO_CLOCK_DIV;
sts ADCSRA, r27 ; reset ADC interrupt flag
#ifdef WITH_XTAL
sbrs r24,smplADC_mux ; do we need to toggle MUX?
rjmp L23
ldi r23, 3
cpi r21, 2 ; if span so large that we have to discard one or more ADC readings per cycle:
brcs L23
brne L24 ; if precisely one ADC reading per cycle to be discarded, r23=1, otherwise =3
ldi r23, 1 ; now r23 is the value of r21 (counter for ADC discarding) at which we have to set the ADMUX to its proper setting
L24:
mov r19, r7
cp r22, r23
breq L22
andi r19, 0xf8 ; set ADMUX to input 0 if we're going to discard the value
L22:
sts ADMUX, r19
L23:
#endif
; now need to check whether we should read or discard it
dec r22 ; r22 counts AD conversions within one pulse cycle
brnewaitevent:
brne waitevent ; if r22 not yet zero, it's not yet our turn
lds r22, ADCL ; read ADC
lds r23, ADCH
#ifdef WITH_XTAL
sbrs r5, 7 ; bit 7 of r5 is used as marker that we still need to initialize the DC level
rjmp L25
movw r4, r22
lsl r4 ; r4:5 = r22:23 << 2
rol r5 ; rotate left through Carry
lsl r4
rol r5 ; rotate left through Carry
;lsl r4
;rol r5
L25:
mov r17, r4 ; r4:5 contains "DC-level"<<2
mov r19, r5
lsr r19 ; shift >>2
ror r17
lsr r19
ror r17
;lsr r19
;ror r17
sbrc r24, smplADC_hpf
sub r22, r17 ; subtract DC from sample
sbrc r24, smplADC_hpf
sbc r23, r19
add r4, r22 ; update DC<<2, namely dc := (sample-dc)/8 ;
adc r5, r23
#endif
ld r19, z ; and store, accumulating if that bit in r24 is set
sbrc r24, smplADC_cumul
add r22, r19
st z+, r22
ld r19, z
sbrc r24, smplADC_cumul
adc r23, r19
sbrs r24, smplADC_8bit
st z+, r23
mov r22, r21 ; reinitialize r22
dec r20 ; decrement counter of remaining samples
; brne waitevent
brne brnewaitevent
end:
AOUT TIMSK1, r1 ; disable counter1 interrupts
AOUT TCCR1B, r1 ; stop counter1
ldi r27, AUTO_CLOCK_DIV;
AOUT ADCSRA, r27 ; disable ADC
#ifdef WITH_XTAL
AOUT ADMUX, r7
pop r7
sbrs r24, smplADC_sck ; if possibly short-circuiting the DUT, restore ADC_DDR
rjmp L30c
AOUT ADC_DDR, r9
pop r9
L30c:
pop r17
pop r5
pop r4
#endif
ret
#endif /* SamplingADC_CNT */
|
akshaybaweja/component-tester-oled
| 1,235
|
Source Code/i2lcd.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include "config.h"
.GLOBAL u2lcd
.GLOBAL u2lcd_space
.extern lcd_data
.extern lcd_string
.extern lcd_space
.func i2lcd
; use allways rcall for nearby functions
#define RCALL rcall
.section .text
.GLOBAL i2lcd
i2lcd: ; void i2lcd(int iw)
#if FLASHEND > 0x1fff
;; movw r20, r24
sbrs r25, 7
rjmp to_lcd ; if (iw >= 0) {
; // negativ value, output - and invert iw
push r24 ; save r24:r25
push r25
ldi r24,'-' ; 45
RCALL lcd_data ; lcd_data('-'); uses r22
pop r25 ; recall r25:r24
pop r24 ; old r24
com r25
neg r24
sbci r25,-1 ; iw = - iw
#endif
u2lcd: ; void i2lcd(uint16_t iw)
to_lcd: ; void i2lcd(uint16_t iw)
ldi r22, lo8(outval) ;0x0F
ldi r23, hi8(outval) ;0x01
ldi r20, 10
ldi r21, 0x00 ; 0
ACALL utoa ; utoa(iw, outval, 10); //output voltage to string
RCALL lcd_string ;lcd_string(utoa(iw, outval, 10)); //output correction voltage
ret
#if FLASHEND > 0x1fff
.GLOBAL i2lcd_space
i2lcd_space:
RCALL i2lcd
rjmp space_ret ; use return from u2lcd_space
u2lcd_space:
RCALL i2lcd
space_ret:
RCALL lcd_space
ret
#endif
.endfunc
|
akshaybaweja/component-tester-oled
| 27,661
|
Source Code/GetESR.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include <avr/eeprom.h>
#include <stdlib.h>
#include "config.h"
#include "part_defs.h"
.GLOBAL GetESR
.func GetESR
/* MAX_CNT is the maximum loop counter for repetition of mesurement */
#define MAX_CNT 255
/* ADC_Sleep_Mode enables the sleep state for reading ADC */
//#define ADC_Sleep_Mode
/* ESR_DEBUG enables additional Output on row 3 and row 4 */
//#define ESR_DEBUG
#ifdef INHIBIT_SLEEP_MODE
/* Makefile option set to disable the sleep mode */
#undef ADC_Sleep_Mode
#endif
#define zero_reg r1
// uint8_t big_cap;
// #define big_cap 1
#if defined(__AVR_ATmega2560__)
// ATmega2560 uses 3 bytes for return address
#define RetAdr 3
#else
// normalle 2 bytes are used for the return address
#define RetAdr 2
#endif
// unsigned long sumvolt0,sumvolt1,sumvolt2; // 3 sums of ADC readings
#define sumvolt0 RetAdr /* r14-r17 */
#define sumvolt1 RetAdr+4 /* SP + 6:9 */
#define sumvolt2 RetAdr+8 /* SP + 10:13 */
// uint8_t LoADC; // used to switch Lowpin directly to GND or VCC
#define LoADC RetAdr+12 /* SP + 14 */
// uint8_t HiADC; // used to switch Highpin directly to GND or VCC
#define HiADC RetAdr+13 /* SP + 15 */
// unsigned int adcv[4]; // array for 4 ADC readings
// first part adcv0 r2/r3
// first part adcv1 Y+16/17
#define adcvv1 RetAdr+14
// first part adcv2 Y+18/19
#define adcvv2 RetAdr+16
// unsigned long cap_val_nF; // capacity in nF
#define cap_val_nF RetAdr+18 /* SP + 20:23 */
#define LowUpCount RetAdr+22 /* SP + 24 */
#define HighUpCount RetAdr+23 /* SP + 25 */
#define LowTooHigh RetAdr+24 /* SP + 26 */
#define HighTooHigh RetAdr+25 /* SP + 27 */
#define adcv0L r2
#define adcv0H r3
#define adcv2L r24
#define adcv2H r25
#define HiPinR_L r12 /* used to switch 680 Ohm to HighPin */
#define LoPinR_L r7 /* used to switch 680 Ohm to LowPin */
// uint8_t ii,jj; // tempory values
#define StartADCmsk r10 /* Bit mask to start the ADC */
#define SelectLowPin r6
#define SelectHighPin r11
// Structure cap:
.extern cap
#define cval_max 4
#define esr 12
#define ca 16
#define cb 17
#define cpre_max 19
.extern EE_ESR_ZEROtab
#ifdef ADC_Sleep_Mode
// #define StartADCwait() ADCSRA = (1<<ADEN) | (1<<ADIF) | (1<<ADIE) | AUTO_CLOCK_DIV; /* enable ADC and Interrupt */
// set_sleep_mode(SLEEP_MODE_ADC);
// sleep_mode() /* Start ADC, return if ADC has finished */
.macro StartADCwait
ldi r24, (1 << SM0) | (1 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
sleep; /* wait for ADC */
ldi r24, (1 << SM0) | (0 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
.endm
#else
// #define StartADCwait() ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable ADC and start */
.macro StartADCwait
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk = r10 */
lds r24, ADCSRA; /* while (ADCSRA & (1 <<ADSC)) */
sbrc r24, ADSC;
rjmp .-8 ; /* wait until conversion is done */
.endm
#endif
#define HALF_PULSE_LENGTH_TICS (F_CPU_HZ / 1000000)
//=================================================================
; #define WITHOUT_PROLOGUE /* to use the local push / pop techniques */
; without the local push/pop you can save 82 bytes Flash memory
//=================================================================
//void GetESR(uint8_t hipin, uint8_t lopin) {
.section .text
GetESR:
#ifdef WITHOUT_PROLOGUE
push r2;
push r3;
push r4;
push r5;
push r6;
push r7;
push r8;
push r9;
push r10;
push r11;
push r12;
push r13;
push r14;
push r15;
push r16;
push r17;
push r29;
push r28;
in r28, _SFR_IO_ADDR(SPL);
in r29, _SFR_IO_ADDR(SPH);
sbiw r28, 30 ;
in r0, _SFR_IO_ADDR(SREG);
cli
out _SFR_IO_ADDR(SPH), r29;
out _SFR_IO_ADDR(SREG), r0;
out _SFR_IO_ADDR(SPL), r28;
#else
.extern __prologue_saves__
.extern __epilogue_restores__
ldi r26, 30 ;
ldi r27, 0 ;
ldi r30, lo8(gs(Retur2)) ;
ldi r31, hi8(gs(Retur2)) ;
jmp __prologue_saves__ ;
Retur2:
#endif
#if TP_MIN > 0
subi r22, TP_MIN
subi r24, TP_MIN
#endif
mov SelectLowPin, r22;
mov SelectHighPin, r24;
add r24, r22;
std Y+1, r24;
lds r18, PartFound; /* if (PartFound == PART_CAPACITOR) { */
cpi r18, PART_CAPACITOR;
; brne ad_35e4;
brne load_max;
lds r18, cap+cval_max; /* cap_val_nF = cap.cval_max; */
lds r19, cap+cval_max+1;
lds r20, cap+cval_max+2;
lds r21, cap+cval_max+3;
sbrc r21, 7; /* negativ bit is set */
rjmp set_high
lds r17, cap+cpre_max; /* prefix = cap.cpre_max; */
rjmp ad_35ba;
ad_35ac:
movw r24, r20; /* cval /= 10; // reduce value by factor ten */
movw r22, r18
ldi r18, 0x0A; 10
mov r19, zero_reg
mov r20, zero_reg
mov r21, zero_reg
call __udivmodsi4; /* r18:21 = r22:25 / r18:21 */
subi r17, 0xFF; /* prefix++; // take next decimal prefix */
ad_35ba:
cpi r17, -9; /* while (prefix < -9) { // set cval to nF unit */
brlt ad_35ac; /* } */
brne load_max; /* load max value for correction */
; cpi r18, lo8(900/10); /* if (cap_val_nF < (900/10)) return(0xffff); //capacity lower than 90 nF */
; ldi r22, hi8(900/10)
cpi r18, lo8(200/10); /* if (cap_val_nF < (200/10)) return(0xffff); //capacity lower than 20 nF */
ldi r22, hi8(200/10)
cpc r19, r22
cpc r20, zero_reg
cpc r21, zero_reg
brcc ad_35e4
set_high:
ldi r24, 0xff;
ldi r25, 0xff;
rjmp ad_exit;
ad_35e4: /* } */
cpi r17, -9; /* if ((pp > -9) || (cap_val_nF > 32000)) { */
brne load_max;
ldi r24, lo8(32000);
cp r18, r24
ldi r24, hi8(32000);
cpc r19, r24;
; ldi r24, hlo8(32000);
; cpc r20, r24;
cpc r20, r1;
; ldi r24, hhi8(32000);
; cpc r21, r24;
cpc r20, r1;
brcs store_cvn;
load_max:
ldi r18, lo8(32000); /* cap_val_nF = 65000 */
ldi r19, hi8(32000);
; ldi r20, hlo8(32000); /* upper word is allways zero */
; ldi r21, hhi8(32000); /* upper word is allways zero */
store_cvn:
std Y+cap_val_nF, r18
std Y+cap_val_nF+1, r19
; std Y+cap_val_nF+2, r20; /* upper word is allways zero */
; std Y+cap_val_nF+3, r21; /* upper word is allways zero */
#ifdef ADC_Sleep_Mode
ldi r24, (1 << SM0) | (1 << SE);
out _SFR_IO_ADDR(SMCR), r24; /* SMCR = (1 << SM0) | (1 << SE); */
/* normal ADC-speed, ADC-Clock 8us */
ldi r25, (1<<ADEN) | (1<<ADIF) | (1<<ADIE) | AUTO_CLOCK_DIV; /* enable ADC and Interrupt */
mov StartADCmsk, r25;
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#else
ldi r18, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable and start ADC */
mov StartADCmsk, r18;
#endif
#if (((PIN_RL1 + 1) != PIN_RH1) || ((PIN_RL2 + 1) != PIN_RH2) || ((PIN_RL3 + 1) != PIN_RH3))
LDIZ PinRLRHADCtab+6; /* LoADC = pgm_read_byte((&PinRLRHADCtab[6])+cap.ca) | TXD_MSK; */
#else
LDIZ PinRLRHADCtab+3; /* LoADC = pgm_read_byte((&PinRLRHADCtab[3])+cap.ca) | TXD_MSK; */
#endif
add r30, SelectLowPin;
adc r31, zero_reg;
lpm r24, Z+;
ori r24, TXD_MSK;
std Y+LoADC, r24;
#if (((PIN_RL1 + 1) != PIN_RH1) || ((PIN_RL2 + 1) != PIN_RH2) || ((PIN_RL3 + 1) != PIN_RH3))
LDIZ PinRLRHADCtab+6; /* HiADC = pgm_read_byte((&PinRLRHADCtab[6])+cap.cb) | TXD_MSK; */
#else
LDIZ PinRLRHADCtab+3; /* HiADC = pgm_read_byte((&PinRLRHADCtab[3])+cap.cb) | TXD_MSK; */
#endif
add r30, SelectHighPin;
adc r31, zero_reg;
lpm r24, Z+;
ori r24, TXD_MSK;
std Y+HiADC, r24;
LDIZ PinRLRHADCtab; /* LoPinR_L = pgm_read_byte(&PinRLRHADCtab[cap.ca]); //R_L mask for LowPin R_L load */
add r30, SelectLowPin;
adc r31, zero_reg;
lpm LoPinR_L, Z+;
LDIZ PinRLRHADCtab; /* HiPinR_L = pgm_read_byte(&PinRLRHADCtab[cap.cb]); //R_L mask for HighPin R_L load */
add r30, SelectHighPin;
adc r31, zero_reg;
lpm HiPinR_L, Z+;
#if (PROCESSOR_TYP == 644) || (PROCESSOR_TYP == 1280)
/* ATmega640/1280/2560 1.1V Reference with REFS0=0 */
// SelectLowPin = (cap.ca | (1<<REFS1) | (0<<REFS0)); // switch ADC to LowPin, Internal Ref.
ldi r25, (1<<REFS1)|(0<<REFS0); 0x80
or SelectLowPin, r25;
// SelectHighPin = (cap.cb | (1<<REFS1) | (0<<REFS0)); // switch ADC to HighPin, Internal Ref.
or SelectHighPin, r25;
#else
// SelectLowPin = (cap.ca | (1<<REFS1) | (1<<REFS0)); // switch ADC to LowPin, Internal Ref.
ldi r25, (1<<REFS1)|(1<<REFS0); 0xC0
or SelectLowPin, r25;
// SelectHighPin = (cap.cb | (1<<REFS1) | (1<<REFS0)); // switch ADC to HighPin, Internal Ref.
or SelectHighPin, r25;
#endif
// Measurement of ESR of capacitors AC Mode
ldi r24, 0x01; /* sumvolt0 = 1; // set sum of LowPin voltage to 1 to prevent divide by zero */
mov r14, r24;
mov r15, zero_reg;
mov r16, zero_reg;
mov r17, zero_reg;
std Y+sumvolt1, r24; /* sumvolt1 = 1; // clear sum of HighPin voltage with current */
// // offset is about (x*10*200)/34000 in 0.01 Ohm units
std Y+sumvolt1+1, zero_reg;
std Y+sumvolt1+2, zero_reg;
std Y+sumvolt1+3, zero_reg;
std Y+sumvolt2, zero_reg; /* sumvolt2 = 0; // clear sum of HighPin voltage without current */
std Y+sumvolt2+1, zero_reg;
std Y+sumvolt2+2, zero_reg;
std Y+sumvolt2+3, zero_reg;
std Y+LowUpCount, zero_reg;
std Y+HighUpCount, zero_reg;
std Y+HighTooHigh, zero_reg;
std Y+LowTooHigh, zero_reg;
call EntladePins; /* EntladePins(); // discharge capacitor */
ldi r24, TXD_VAL;
AOUT ADC_PORT, r24; /* ADC_PORT = TXD_VAL; // switch ADC-Port to GND */
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; // set Mux input and Voltage Reference to internal 1.1V */
#ifdef NO_AREF_CAP
call wait100us; /* time for voltage stabilization */
#else
call wait10ms; /* time for voltage stabilization with 100nF */
#endif
/* start voltage should be negativ */
ldd r19, Y+HiADC; /* ADC_DDR = HiADC; // switch High Pin to GND */
AOUT ADC_DDR, r19; /* switch High Pin to GND */
AOUT R_PORT, LoPinR_L /* r7 */
AOUT R_DDR, LoPinR_L /* r7 */
ldi r21, (HALF_PULSE_LENGTH_TICS/3)
plop1:
dec r21
brne plop1
#if (HALF_PULSE_LENGTH_TICS % 3) > 1
nop
#endif
#if (HALF_PULSE_LENGTH_TICS % 3) > 0
nop
#endif
AOUT R_DDR, zero_reg; /* R_DDR = 0 */
AOUT R_PORT, zero_reg; /* R_PORT = 0 */
// Measurement frequency is given by sum of ADC-Reads < 1116 Hz for normal ADC speed.
// ADC Sample and Hold (SH) is done 1.5 ADC clock number after real start of conversion.
// Real ADC-conversion is started with the next ADC-Clock (125kHz) after setting the ADSC bit.
eor r13, r13; /* for(ii=0;ii<MAX_CNT;ii++) { */
// when time is too short, voltage is down before SH of ADC
// when time is too long, capacitor will be overloaded.
// That will cause too high voltage without current.
// adcv[0] = ADCW; // Voltage LowPin with current
// ADMUX = SelectHighPin;
/* ********* Forward direction, connect Low side with GND *********** */
esr_loop:
ldd r19, Y+LoADC;
AOUT ADC_DDR, r19; /* ADC_DDR = LoADC; // switch Low-Pin to output (GND) */
AOUT R_PORT, LoPinR_L; /* R_PORT = LoPinR_L (r7) */
AOUT R_DDR, LoPinR_L; /* R_DDR = LoPinR_L (r7) */
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; */
wdr ; /* wdt_reset(); */
;=#= StartADCwait /* start ADC and wait */
StartADCwait /* start ADC and wait */
lds adcv0L, ADCW; /* adcv[0] = ADCW; // Voltage LowPin reference */
lds adcv0H, ADCW+1;
sts ADMUX, SelectHighPin; /* ADMUX = SelectHighPin; */
mov r20, HiPinR_L
rcall strtADC_pulse ; start ADC, generate pulse and wait
lds r18, ADCW; /* adcv[1] = ADCW; // Voltage HighPin with current */
lds r19, ADCW+1;
#ifdef ADC_Sleep_Mode
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#endif
;=======
std Y+adcvv1, r18;
std Y+adcvv1+1, r19;
/* ********* Reverse direction, connect High side with GND *********** */
ldd r19, Y+HiADC; /* ADC_DDR = HiADC; // switch High Pin to GND */
AOUT ADC_DDR, r19; /* ADC_DDR = HiADC; // switch High-Pin to output (GND) */
AOUT R_PORT, HiPinR_L; /* R_PORT = HiPinR_L (r12); // switch R-Port to VCC */
AOUT R_DDR, HiPinR_L; /* R_DDR = HiPinR_L (r12); // switch R_L port for HighPin to output (VCC) */
wdr ; /* wdt_reset(); */
sts ADMUX, SelectHighPin; /* ADMUX = SelectHighPin; */
;=#= StartADCwait /* start ADC and wait */
StartADCwait /* start ADC and wait */
lds r22, ADCW; /* adcv[2] = ADCW; // Reverse Reference Voltage HighPin */
lds r23, ADCW+1;
sts ADMUX, SelectLowPin; /* ADMUX = SelectLowPin; */
// ****** Polling mode big cap
mov r20, LoPinR_L
rcall strtADC_pulse ; start ADC, generate pulse and wait
lds r20, ADCW; /* adcv[3] = ADCW; // Voltage LowPin with current */
lds r21, ADCW+1;
#ifdef ADC_Sleep_Mode
sts ADCSRA, StartADCmsk; /* ADCSRA = StartADCmsk; // enable ADC and Interrupt */
#endif
AOUT R_DDR, zero_reg; /* R_DDR = 0; // switch current off */
movw r24, r22; /* adcv[2] */
add r24, adcv0L; /* adcv[0] + adcv[2] // add sum of both LowPin voltages with current */
adc r25, adcv0H;
add r14, r24; /* r14:17 = sumvolt0 += (adcv[0] + adcv[2]); */
adc r15, r25;
adc r16, zero_reg;
adc r17, zero_reg;
std Y+sumvolt0, r14;
std Y+sumvolt0+1, r15;
std Y+sumvolt0+2, r16;
std Y+sumvolt0+3, r17;
ldd r24, Y+adcvv1; /* add HighPin voltages with current */
ldd r25, Y+adcvv1+1;
add r24, r20; /* adcv[1] + adcv[3] */
adc r25, r21;
ldd r18, Y+sumvolt1; /* sumvolt1 += (adcv[1] + adcv[3]); */
ldd r19, Y+sumvolt1+1;
ldd r22, Y+sumvolt1+2;
ldd r23, Y+sumvolt1+3;
add r18, r24;
adc r19, r25;
adc r22, zero_reg;
adc r23, zero_reg;
std Y+sumvolt1, r18;
std Y+sumvolt1+1, r19;
std Y+sumvolt1+2, r22;
std Y+sumvolt1+3, r23;
/*===================================================================================================*/
/* Range Check for voltages */
/* Y+adcvv1 is still the voltage of forward direction, r20:21 the voltage of reverse direction */
ldi r18, lo8(50);
cp r18, r20;
cpc zero_reg, r21;
brcs is_ok1; /* r20:21 >= 50 */
AOUT R_PORT, LoPinR_L; /* R_PORT = LoPinR_L (r7); */
AOUT R_DDR, LoPinR_L; /* R_DDR = LoPinR_L (r7); // switch LowPin with 680 Ohm to VCC */
call wait1us; /* additional charge the capacitor */
AOUT R_DDR, zero_reg; // switch current off
AOUT R_PORT, zero_reg;
ldd r24, Y+LowUpCount; /* count additional load pulses at Low side */
inc r24;
std Y+LowUpCount, r24;
rjmp is_ok1b;
is_ok1:
cpi r20, lo8(1000);
ldi r23, hi8(1000);
cpc r21, r23;
brcs is_ok1b; /* voltage reverse direction < 1000 */
ldd r24, Y+LowTooHigh; /* count pulses with too high voltage at Low side */
inc r24;
std Y+LowTooHigh, r24;
is_ok1b:
ldd r24, Y+adcvv1;
ldd r25, Y+adcvv1+1;
cp r18, r24;
cpc zero_reg, r25; /* adcvv1 >= 50 */
brcs is_ok2;
ldd r19, Y+LoADC;
AOUT ADC_DDR, r19; /* ADC_DDR = LoADC; // switch Low-Pin to output (GND) */
AOUT R_PORT, HiPinR_L; /* R_PORT = HiPinR_L (r12); // switch R-Port to VCC */
AOUT R_DDR, HiPinR_L; /* R_DDR = HiPinR_L (r12); // switch R_L port for HighPin to output (VCC) */
call wait1us; /* additional charge the capacitor */
;## DelayBigCap; /* wait the time defined by macro */
AOUT R_DDR, zero_reg; /* R_DDR = 0; // switch current off, SH is 1.5 ADC clock behind real start */
AOUT R_PORT, zero_reg; /* R_PORT = 0; */
ldd r24, Y+HighUpCount; /* count additional load pulses at High side */
inc r24;
std Y+HighUpCount, r24;
rjmp is_ok2b;
is_ok2:
cpi r24, lo8(1000);
ldi r23, hi8(1000);
cpc r25, r23;
brcs is_ok2b; /* voltage forward direction < 1000 */
ldd r24, Y+HighTooHigh; /* count pulses with too high voltage at High side */
inc r24;
std Y+HighTooHigh, r24;
is_ok2b:
/*===================================================================================================*/
inc r13; /* for( ;ii<MAX_CNT;ii++) */
mov r21, r13;
cpi r21, MAX_CNT;
breq ad_38ac;
#if FLASHEND > 0x3fff
/* use additional 470k only with processors with more than 16k */
cpi r21, MAX_CNT/2;
brne jesr_loop
; activate also the 470k resistors for half of samples
#if (((PIN_RL1 + 1) != PIN_RH1) || ((PIN_RL2 + 1) != PIN_RH2) || ((PIN_RL3 + 1) != PIN_RH3))
LDIZ PinRLRHADCtab+3; /* HiPinR_H = pgm_read_byte(&PinRLRHADCtab[cap.cb+3]); //R_H mask for HighPin R_H load */
mov r21, SelectHighPin;
andi r21, 0x03
add r30, r21;
adc r31, zero_reg;
lpm r21, Z+;
add HiPinR_L, r21 ; enable also the 470k resistor
LDIZ PinRLRHADCtab+3; /* LoPinR_H = pgm_read_byte(&PinRLRHADCtab[cap.ca+3]); //R_H mask for LowPin R_H load */
mov r21, SelectLowPin;
andi r21, 0x03
add r30, r21;
adc r31, zero_reg;
lpm r21, Z+;
add LoPinR_L, r21 ; enable also the 470k resistor
#else
mov r21, HiPinR_L
add r21, r21 ; quick and dirty: usually is double HiPinR_H
add HiPinR_L, r21
mov r21, LoPinR_L
add r21, r21 ; quick and dirty: usually is double LoPinR_H
add LoPinR_L, r21
#endif
jesr_loop:
#endif
rjmp esr_loop; /* } // end for */
ad_38ac:
#if RRpinMI == PIN_RM
ldi r18, lo8(PIN_RM*10);
ldi r19, hi8(PIN_RM*10);
#else
lds r4, RRpinMI; /* pin_rmi */
lds r5, RRpinMI+1;
add r4, r4; RRpinMI*2
adc r5, r5;
movw r18, r4;
ldi r30, 4;
ad_2r:
add r18, r4; + 4*(2*RRpinMI)
adc r19, r5;
dec r30;
brne ad_2r; add next (2*RRpinMI)
#endif
movw r4, r18; /* r4:5 = 10 * RRpinMI */
movw r10, r14; /* r10:13 = r14:17 = sumvolt0 */
movw r12, r16;
ldd r6, Y+sumvolt1;
ldd r7, Y+sumvolt1+1;
ldd r8, Y+sumvolt1+2;
ldd r9, Y+sumvolt1+3;
/* ############################################################ */
lds r18, PartFound; /* if (PartFound == PART_CAPACITOR) { */
cpi r18, PART_CAPACITOR;
brne no_sub; /* it is not a capacitor */
; rjmp no_sub; /* ############## for debug */
/* First half of load pulse (13.5us) loads quicker than the second half of load pulse. */
/* Aproximation of 5000*(1 - exp(13.5e-6/(cap_val_nF*1.e-9*(0.1*(PIN_RM+PIN_RP+R_L_VAL)))) - 2500*(1 - exp(-27e-6/(cap_val_nF*1.e-9*(0.1*(PIN_RM+PIN_RP+R_L_VAL))))) */
/* is done by ((6744116/(PIN_RM+PIN_RP+R_L_VAL))*(6744116/(PIN_RM+PIN_RP+R_L_VAL))) / (cap_val_nF * (cap_val_nF + (137180/(PIN_RM+PIN_RP+R_L_VAL)))) */
/* is done by 872520 / (cap_val_nF * (cap_val_nF + 19)) */
; #define FAKTOR_ESR (9537620/(PIN_RM+PIN_RP+R_L_VAL))
ldd r22, Y+cap_val_nF; /* sumvolt1 -= (1745098UL*MAX_CNT) / (cap_val_nF * (cap_val_nF + 19)); */
ldd r23, Y+cap_val_nF+1;
; ldd r24, Y+cap_val_nF+2;
mov r24, r1 /* upper bits of cap_val_nF are allway zero */
; ldd r25, Y+cap_val_nF+3;
mov r25, r1 /* upper bits of cap_val_nF are allway zero */
;#define FAKTOR_ESR (580000/(PIN_RM+PIN_RP+R_L_VAL)) /* 80 */
;#define CAP_OFFSET (32000/(PIN_RM+PIN_RP+R_L_VAL)) /* 4 nF */
#define FAKTOR_ESR (550000/(PIN_RM+PIN_RP+R_L_VAL)) /* 76 */
#define CAP_OFFSET (38000/(PIN_RM+PIN_RP+R_L_VAL)) /* 5 nF */
#if F_CPU == 16000000UL
;#define FAKTOR_ESR (920000/(PIN_RM+PIN_RP+R_L_VAL)) /* 127 */
;#define CAP_OFFSET (410400/(PIN_RM+PIN_RP+R_L_VAL)) /* 57 nF */
;#define FAKTOR_ESR (780000/(PIN_RM+PIN_RP+R_L_VAL)) /* 127 */
#else
;#define FAKTOR_ESR (920000/(PIN_RM+PIN_RP+R_L_VAL)) /* 127 */
;#define CAP_OFFSET (433200/(PIN_RM+PIN_RP+R_L_VAL)) /* 60 nF */
#endif
subi r22, lo8(CAP_OFFSET); 0xED; 237
sbci r23, hi8(CAP_OFFSET); 0xFF; 255
sbci r24, hlo8(CAP_OFFSET); 0xFF; 255
sbci r25, hhi8(CAP_OFFSET); 0xFF; 255
movw r18, r22; /* r18:21 = r22:25 = (cap_val_nF-60); */
movw r20, r24;
call __mulsi3; /* (cap_val_nF - 60) * (cap_val_nF - 60) */
movw r18, r22;
movw r20, r24;
ldi r22, lo8(FAKTOR_ESR*FAKTOR_ESR*MAX_CNT); 0x36; 54
ldi r23, hi8(FAKTOR_ESR*FAKTOR_ESR*MAX_CNT); 0x29; 41
ldi r24, hlo8(FAKTOR_ESR*FAKTOR_ESR*MAX_CNT); 0x86; 134
ldi r25, hhi8(FAKTOR_ESR*FAKTOR_ESR*MAX_CNT); 0x1A; 26
call __udivmodsi4;
sub r6, r18
sbc r7, r19
sbc r8, r20
sbc r9, r21
no_sub: /* } */
/* ############################################################ */
cp r10, r6; /* if (sumvolt1 > sumvolt0) { */
cpc r11, r7;
cpc r12, r8;
cpc r13, r9;
brcc ad_396c;
sub r6, r10; /* sumvolt1 -= sumvolt0; // difference HighPin - LowPin Voltage with current */
sbc r7, r11;
sbc r8, r12;
sbc r9, r13;
rjmp ad_3972; /* } else { */
ad_396c:
eor r6, r6; /* sumvolt1 = 0; */
eor r7, r7
movw r8, r6
ad_3972:
#ifdef ESR_DEBUG
movw r22, r6; /* DisplayValue(sumvolt1,0,'d',4); */
movw r24, r8
ldi r20, 0;
ldi r18, 'd';
ldi r16, 4 ;
call DisplayValue;
call lcd_line3;
ldd r24, Y+LowUpCount;
ldi r25, 0;
ldi r22, 0;
ldi r20, '<';
ldi r18, 4 ;
call DisplayValue16;
ldd r24, Y+HighUpCount;
ldi r25, 0;
ldi r22, 0;
ldi r20, '>';
ldi r18, 4 ;
call DisplayValue16;
ldd r24, Y+LowTooHigh;
ldi r25, 0;
ldi r22, 0;
ldi r20, '+';
ldi r18, 4 ;
call DisplayValue16;
ldd r24, Y+HighTooHigh;
ldi r25, 0;
ldi r22, 0;
ldi r20, '#';
ldi r18, 4 ;
call DisplayValue16;
call wait2s
#endif
movw r22, r4
ldi r24, 0x00;
ldi r25, 0x00; /* r22:25 = 10 * (unsigned long)RRpinMI) */
/* jj = 0; */
// mean voltage at the capacitor is higher with current
// sumvolt0 is the sum of voltages at LowPin, caused by output resistance of Port
// RRpinMI is the port output resistance in 0.1 Ohm units.
// we scale up the difference voltage with 10 to get 0.01 Ohm units of ESR
/* esrvalue = (sumvolt1 * 10 * (unsigned long)RRpinMI) / sumvolt0; */
movw r18, r6; /* r18:21 = r6:9 = sumvolt1 */
movw r20, r8;
call __mulsi3; /* r22:25 = r22:25 * r18:21 */
movw r18, r10; /* r18:21 = r10:13 = sumvolt0 */
movw r20, r12;
call __udivmodsi4; /* r18:21 = r22:25 / r18:21 */
ldi r24, lo8(EE_ESR_ZEROtab); /* esr0 = (int8_t)eeprom_read_byte(&EE_ESR_ZEROtab[lopin+hipin]); */
ldi r25, hi8(EE_ESR_ZEROtab);
ldd r23, Y+1;
add r24, r23;
adc r25, zero_reg;
call eeprom_read_byte;
mov r6, r24;
movw r24,r18; /* r24:25 = r18:19 = esrvalue */
ldi r22, 16;
ldi r23, 0;
call __udivmodhi4 /* r22:23 = r24:25 / r22:23 */
add r18, r22; /* esrvalue += esrvalue / 16; */
adc r19, r23;
movw r24,r18; /* esrvalue */
cp r6, r24; /* if (esrvalue > esr0) esrvalue -= esr0; */
cpc zero_reg, r25;
brcc esr_too_less;
sub r24, r6; /* - esr0 */
sbc r25, zero_reg;
rjmp ad_exit;
esr_too_less:
#ifdef AUTO_CAL
subi r24, lo8(-R_LIMIT_TO_UNCALIBRATED); /* + 0.20 Ohm */
sbci r25, hi8(-R_LIMIT_TO_UNCALIBRATED); /* esrvalue + 20 */
cp r24, r6; /* if ((esrvalue+20) < esr0) ; */
cpc r25, zero_reg;
brcc esr_too_less2;
ldd r24, Y+cap_val_nF; /* mark only, if cap_val_nF > 4500 */
ldd r25, Y+cap_val_nF+1;
; ldd r26, Y+cap_val_nF+2; /* the upper bits (cap_val_nF+2|3) are always zero */
cpi r24, lo8(4500);
ldi r24, hi8(4500);
cpc r25, r24;
brcs esr_too_less2;
call mark_as_uncalibrated;
/* ldi r24,'<'; */
/* call lcd_data; */
esr_too_less2:
#endif
mov r24, zero_reg;
mov r25, zero_reg;
ad_exit:
#ifdef ADC_Sleep_Mode
out _SFR_IO_ADDR(SMCR), zero_reg; /* SMCR = 0 */
#endif
#ifdef WITHOUT_PROLOGUE
adiw r28, 30 ;
in r0, _SFR_IO_ADDR(SREG); 63
cli
out _SFR_IO_ADDR(SPH), r29; 62
out _SFR_IO_ADDR(SREG), r0; 63
out _SFR_IO_ADDR(SPL), r28; 61
pop r28;
pop r29;
pop r17;
pop r16;
pop r15;
pop r14;
pop r13;
pop r12;
pop r11;
pop r10;
pop r9;
pop r8;
pop r7;
pop r6;
pop r5;
pop r4;
pop r3;
pop r2;
ret;
#else
adiw r28, 30
ldi r30, 18
jmp __epilogue_restores__
#endif
; #####################################################################################
; Start ADC and generate a Pulse around the sample and hold time,
; then wait for end of conversion and return.
; #####################################################################################
/* ************************************************************************************ */
/* Adjust the timing for switch off the load current for big capacitors */
/* ************************************************************************************ */
// With wdt_reset the timing can be fine adjusted.
// The middle of current pulse should be at the SH time of ADC.
// SH time of next ADC cycle is 20 us after last ADC ready.
// The timing of the middle of the load pulse is critical
// for capacitors with low capacity value (100 nF).
// For resistors or capacitors with big capacity value the
// voltage is constant or nearly constant.
// For this reason the timing is extremly critical for
// capacitors with low capacity value.
// Charging of capacitor begins with negative voltage and
// should be zero at SH time with a zero ESR capacitor.
#if R_PORT < 0x40
#define OUT_DELAY 2 /* two AOUT take 2 tics (out instruction) */
#else
#define OUT_DELAY 4 /* two AOUT take 4 tics (sts instruction) */
#endif
; #define WITHOUT_CNT_START
strtADC_pulse:
#ifdef WITHOUT_CNT_START
StartADCwait /* start ADC and wait */
// Start Conversion, real start is next rising edge of ADC clock
ldi r21, (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable ADC and start with ADSC */
sts ADCSRA, r21; /* ADCSRA = (1<<ADSC) | (1<<ADEN) | (1<<ADIF) | AUTO_CLOCK_DIV; // enable ADC and start */
#ifdef ADC_Sleep_Mode
/* Wake up from sleep with Interrupt: 1+4+4T, jmp, rti, ldi, out takes 18 clock tics, */
#define PIN_HIGH_DELAY (9+2+4+OUT_DELAY + 5 + 3 + (F_CPU_HZ/4000000))
#else
/* Polling mode:
delay to pin high: lds,sbrc,sts and out Instructions are 7 clock tics */
#define PIN_HIGH_DELAY (6+OUT_DELAY + 3 + (F_CPU_HZ/4000000))
#endif
#define WAST_TICS (((TICS_PER_ADC_CLOCK*5)/2) - HALF_PULSE_LENGTH_TICS - PIN_HIGH_DELAY)
#else
sts TCCR1B, r1 ; stop counter1
sts TCCR1A, r1 ; TCCR1A = 0 , normal port operation
sts TIMSK1, r1 ; disable all timer1 interrupts
sts OCR1BH, r1 ; OCR!B = 0
sts OCR1BL, r1
ldi r21, (1<<OCF1B) | (1<<OCF1A) | (1<<TOV1)
AOUT TIFR1, r21 ; clear flags
ldi r21, 0xff
sts TCNT1H, r21 ; TCNT1 = -1
sts TCNT1L, r21
ldi r21, (1<<ADTS2) | (1<<ADTS0) ; Start ADC with counter1 compare B
sts ADCSRB, r21
ldi r21, (1<<ADEN) | (1<<ADATE) | (1<<ADIF) | AUTO_CLOCK_DIV; /* enable ADC */
sts ADCSRA, r21; /* ADCSRA = (1<<ADEN) | (1<<ADSC) | (1<<ADIF) | AUTO_CLOCK_DIV; // enable ADC */
ldi r21, (1<<CS10)
sts TCCR1B, r21 ; Start Counter 1 with full speed
#define PIN_HIGH_DELAY (OUT_DELAY - 5 + (F_CPU_HZ/4000000))
#define WAST_TICS ((TICS_PER_ADC_CLOCK*2) - HALF_PULSE_LENGTH_TICS - PIN_HIGH_DELAY)
#endif
; additional delay to the start of current pulse
ldi r21, (WAST_TICS/3)
wlop1:
dec r21
brne wlop1
#if (WAST_TICS % 3) > 1
nop
#endif
#if (WAST_TICS % 3) > 0
nop
#endif
AOUT R_PORT, r20; /* R_PORT = HiPinR_L (r12); // switch R-Port to VCC */
AOUT R_DDR, r20; /* R_DDR = HiPinR_L (r12); // switch R_L port for HighPin to output (VCC) */
; AOUT R_PORT, LoPinR_L; /* R_PORT = LoPinR_L (r7) ; */
; AOUT R_DDR, LoPinR_L; /* R_DDR = LoPinR_L (r7) ; // switch LowPin with 680 Ohm to VCC */
#define FULL_PULSE_LENGTH_TICS ((HALF_PULSE_LENGTH_TICS*2)+(MHZ_CPU/14))
ldi r21, (FULL_PULSE_LENGTH_TICS/3)
plop2:
dec r21
brne plop2
#if (FULL_PULSE_LENGTH_TICS % 3) > 1
nop
#endif
#if (FULL_PULSE_LENGTH_TICS % 3) > 0
nop
#endif
AOUT R_DDR, zero_reg; /* R_DDR = 0; // switch current off, SH is 1.5 ADC clock behind real start */
AOUT R_PORT, zero_reg; /* R_PORT = 0; */
#ifndef WITHOUT_CNT_START
sts TCCR1B, r1 ; stop counter1
#endif
wadfin2:
lds r24, ADCSRA; /* while (ADCSRA&(1<<ADSC)); // wait for conversion finished */
sbrs r24, ADIF;
rjmp wadfin2;
sts ADCSRA, r24 ; clear flags
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 24,755
|
Source Code/lcd_hw_4_bit.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
;---------------------------------------------------------------------
#include <avr/io.h>
#include "config.h"
;#define FAST_SERIAL_OUT /* use no sub-function for bit setting */
#define FAST_SPI_OUTPUT
.section .text
;----------------------------------------------------------------------
; Global Definitions
;----------------------------------------------------------------------
#define preg_1 r24
#define preg_2 r22
; for ST7565 controller: Serial Clock Input (SCL)
#define set_en_low cbi _SFR_IO_ADDR(HW_LCD_EN_PORT), HW_LCD_EN_PIN
#define set_en_high sbi _SFR_IO_ADDR(HW_LCD_EN_PORT), HW_LCD_EN_PIN
#define set_en_output sbi (_SFR_IO_ADDR(HW_LCD_EN_PORT) - 1), HW_LCD_EN_PIN
#define set_en_input cbi (_SFR_IO_ADDR(HW_LCD_EN_PORT) - 1), HW_LCD_EN_PIN
; Register select (0 = Command, 1 = Data)
#define set_rs_low cbi _SFR_IO_ADDR(HW_LCD_RS_PORT), HW_LCD_RS_PIN
#define set_rs_high sbi _SFR_IO_ADDR(HW_LCD_RS_PORT), HW_LCD_RS_PIN
#define set_rs_output sbi (_SFR_IO_ADDR(HW_LCD_RS_PORT) - 1), HW_LCD_RS_PIN
#define set_rs_input cbi (_SFR_IO_ADDR(HW_LCD_RS_PORT) - 1), HW_LCD_RS_PIN
; for ST7565 controller: Serial data input (SI)
#define set_b0_low cbi _SFR_IO_ADDR(HW_LCD_B0_PORT), HW_LCD_B0_PIN
#define set_b0_high sbi _SFR_IO_ADDR(HW_LCD_B0_PORT), HW_LCD_B0_PIN
#define set_b0_output sbi (_SFR_IO_ADDR(HW_LCD_B0_PORT) - 1), HW_LCD_B0_PIN
#define set_b0_input cbi (_SFR_IO_ADDR(HW_LCD_B0_PORT) - 1), HW_LCD_B0_PIN
; for ST7565 controller: Chip Enable
#define set_ce_low cbi _SFR_IO_ADDR(HW_LCD_CE_PORT), HW_LCD_CE_PIN
#define set_ce_high sbi _SFR_IO_ADDR(HW_LCD_CE_PORT), HW_LCD_CE_PIN
#define set_ce_output sbi (_SFR_IO_ADDR(HW_LCD_CE_PORT) - 1), HW_LCD_CE_PIN
#define set_ce_input cbi (_SFR_IO_ADDR(HW_LCD_CE_PORT) - 1), HW_LCD_CE_PIN
#define set_b4_low cbi _SFR_IO_ADDR(HW_LCD_B4_PORT), HW_LCD_B4_PIN
#define set_b4_high sbi _SFR_IO_ADDR(HW_LCD_B4_PORT), HW_LCD_B4_PIN
#define set_b4_output sbi (_SFR_IO_ADDR(HW_LCD_B4_PORT) - 1), HW_LCD_B4_PIN
#define set_b5_low cbi _SFR_IO_ADDR(HW_LCD_B5_PORT), HW_LCD_B5_PIN
#define set_b5_high sbi _SFR_IO_ADDR(HW_LCD_B5_PORT), HW_LCD_B5_PIN
#define set_b5_output sbi (_SFR_IO_ADDR(HW_LCD_B5_PORT) - 1), HW_LCD_B5_PIN
#define set_b6_low cbi _SFR_IO_ADDR(HW_LCD_B6_PORT), HW_LCD_B6_PIN
#define set_b6_high sbi _SFR_IO_ADDR(HW_LCD_B6_PORT), HW_LCD_B6_PIN
#define set_b6_output sbi (_SFR_IO_ADDR(HW_LCD_B6_PORT) - 1), HW_LCD_B6_PIN
#define set_b7_low cbi _SFR_IO_ADDR(HW_LCD_B7_PORT), HW_LCD_B7_PIN
#define set_b7_high sbi _SFR_IO_ADDR(HW_LCD_B7_PORT), HW_LCD_B7_PIN
#define set_b7_output sbi (_SFR_IO_ADDR(HW_LCD_B7_PORT) - 1), HW_LCD_B7_PIN
; for ST7108 Controller: select CS1 and CS2
#define set_cs1_low cbi _SFR_IO_ADDR(HW_LCD_CS1_PORT), HW_LCD_CS1_PIN
#define set_cs1_high sbi _SFR_IO_ADDR(HW_LCD_CS1_PORT), HW_LCD_CS1_PIN
#define set_cs1_output sbi (_SFR_IO_ADDR(HW_LCD_CS1_PORT) - 1), HW_LCD_CS1_PIN
#define set_cs2_low cbi _SFR_IO_ADDR(HW_LCD_CS2_PORT), HW_LCD_CS2_PIN
#define set_cs2_high sbi _SFR_IO_ADDR(HW_LCD_CS2_PORT), HW_LCD_CS2_PIN
#define set_cs2_output sbi (_SFR_IO_ADDR(HW_LCD_CS2_PORT) - 1), HW_LCD_CS2_PIN
#define set_clk_low cbi _SFR_IO_ADDR(HW_LCD_CLK_PORT), HW_LCD_CLK_PIN
#define set_clk_high sbi _SFR_IO_ADDR(HW_LCD_CLK_PORT), HW_LCD_CLK_PIN
#define set_clk_output sbi (_SFR_IO_ADDR(HW_LCD_CLK_PORT) - 1), HW_LCD_CLK_PIN
#define set_pclk_low cbi _SFR_IO_ADDR(HW_LCD_PCLK_PORT), HW_LCD_PCLK_PIN
#define set_pclk_high sbi _SFR_IO_ADDR(HW_LCD_PCLK_PORT), HW_LCD_PCLK_PIN
#define set_pclk_output sbi (_SFR_IO_ADDR(HW_LCD_PCLK_PORT) - 1), HW_LCD_PCLK_PIN
#define RCALL rcall
/* For normal I2C mode use 5us wait time, but SSD1306 is faster, the cycle time is specified as 2.5us. */
/* So we use 2us, which results to a cycle time of >4us */
#define WAIT_I2C wait2us
#define release_sda cbi (_SFR_IO_ADDR(HW_LCD_SDA_PORT) - 1), HW_LCD_SDA_PIN
#define set_low_sda sbi (_SFR_IO_ADDR(HW_LCD_SDA_PORT) - 1), HW_LCD_SDA_PIN
#define release_scl cbi (_SFR_IO_ADDR(HW_LCD_SCL_PORT) - 1), HW_LCD_SCL_PIN
#define set_low_scl sbi (_SFR_IO_ADDR(HW_LCD_SCL_PORT) - 1), HW_LCD_SCL_PIN
#define HW_LCD_SDA_OUT _SFR_IO_ADDR(HW_LCD_SDA_PORT)
#define HW_LCD_SCL_OUT _SFR_IO_ADDR(HW_LCD_SCL_PORT)
#define HW_LCD_SDA_IN (_SFR_IO_ADDR(HW_LCD_SDA_PORT) - 2)
#define HW_LCD_SCL_IN (_SFR_IO_ADDR(HW_LCD_SCL_PORT) - 2)
/* SSD1306 controller defines 0x3C or 0x3D (SA0=1) as address LCD_I2C_ADDR */
;----------------------------------------------------------------------
;
; "_lcd_hw_write"
;
; preg_1 (r24) = flags
; preg_2 (r22) = data
;
;----------------------------------------------------------------------
.global _lcd_hw_write
.func _lcd_hw_write
.extern wait1us
.extern wait30us ; used only for slow 4-bit interface (SLOW_LCD)
.extern wait50us ; used for ST7920 controller
#if (LCD_INTERFACE_MODE == MODE_SPI) || (LCD_INTERFACE_MODE == MODE_3LINE)
;---------------------------------------------------------------------------------
; serial output for ST7565 controller, 4-Bit SPI
_lcd_hw_write:
#ifdef LCD_SPI_OPEN_COL
set_en_low
set_en_output // en/CLK to GND
#ifdef PULLUP_DISABLE
AOUT MCUCR, r1 ; MCUCR = 0; //enable pull up resistors
#endif
set_ce_low
set_ce_output // enable chip
; Set RS (0=Cmd, 1=Char)
#if (LCD_INTERFACE_MODE == MODE_3LINE)
sbrs preg_1, 0
rjmp clr_rs
set_b0_input
set_b0_high // enable B0 pullup
rjmp set_sce
clr_rs:
set_b0_low
set_b0_output
set_sce:
set_rs_low
set_rs_output // SCE to GND;
rcall wait1us
set_en_input
set_en_high // enable en pullup
rcall wait1us
#else
sbrs preg_1, 0
rjmp clr_rs
set_rs_input // set B0 to input
set_rs_high // enable B0 pullup
rjmp fini_rs
clr_rs:
set_rs_low
set_rs_output // set B0 for RS to GND
fini_rs:
rcall wait1us
#endif
; Send bit-7
ROL preg_2 // shift B7 to carry
rcall shift_out
; Send bit-6
ROL preg_2 // shift B6 to carry
rcall shift_out
; Send bit-5
ROL preg_2 // shift B5 to carry
rcall shift_out
; Send bit-4
ROL preg_2 // shift B4 to carry
rcall shift_out
; Send bit-3
ROL preg_2 // shift B3 to carry
rcall shift_out
; Send bit-2
ROL preg_2 // shift B2 to carry
rcall shift_out
; Send bit-1
ROL preg_2 // shift B1 to carry
rcall shift_out
; Send bit-0
ROL preg_2 // shift B0 to carry
rcall shift_out
rcall wait1us
set_en_low
set_en_output // set en/clk to GND
#if (LCD_INTERFACE_MODE == MODE_3LINE)
// rcall wait1us
set_rs_input // SCE to high
set_rs_high // enable pullup
#endif
set_ce_input
set_ce_high // disable chip
#ifdef PULLUP_DISABLE
ldi r25, (1<<PUD) ;
AOUT MCUCR, r25 ; MCUCR = (1<<PUD); //disable pull up resistors
#endif
set_en_low
set_en_output // en/CLK to GND
set_b0_low // ## reset b0 to GND to prevent incorrect detection of rotary encoder movement
set_b0_output // ##
ret // return _lcd_hw_write
// sub-function shift_out: send 1, if carry is set, send 0, if carry is reset
shift_out:
set_en_low
set_en_output // set en/clk to GND
brcc clr_bit
set_b0_input // set B0 to input
set_b0_high // enable B0 pullup = high
rjmp fini_bit
clr_bit:
set_b0_low
set_b0_output // set B0 for Bx to GND
fini_bit:
set_en_input
set_en_high // enable en/clk pullup
rcall wait1us
ret
#else /* no LCD_SPI_OPEN_COL */
#ifdef FAST_SPI_OUTPUT
; Set RS (0=Cmd, 1=Char)
set_ce_low
set_ce_output // enable chip
#if (LCD_INTERFACE_MODE == MODE_3LINE)
set_en_low
sbrc preg_1, 0
set_b0_high
sbrs preg_1, 0
set_b0_low
set_b0_output ; set B0 to output
set_rs_low ; SCE to GND
set_rs_output //init hardware
set_en_high ; force data read from LCD controller
#else
sbrc preg_1, 0
set_rs_high
sbrs preg_1, 0
set_rs_low
set_rs_output; //init hardware
set_b0_output ; wait for address setup, set B0 to output
#endif
; Send bit-7
set_en_low
sbrc preg_2, 7
set_b0_high
sbrs preg_2, 7
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-6
set_en_low
sbrc preg_2, 6
set_b0_high
sbrs preg_2, 6
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-5
set_en_low
sbrc preg_2, 5
set_b0_high
sbrs preg_2, 5
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-4
set_en_low
sbrc preg_2, 4
set_b0_high
sbrs preg_2, 4
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-3
set_en_low
sbrc preg_2, 3
set_b0_high
sbrs preg_2, 3
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-2
set_en_low
sbrc preg_2, 2
set_b0_high
sbrs preg_2, 2
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-1
set_en_low
sbrc preg_2, 1
set_b0_high
sbrs preg_2, 1
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-0
set_en_low
sbrc preg_2, 0
set_b0_high
sbrs preg_2, 0
set_b0_low
set_en_high ; force data read from LCD controller
#if (LCD_INTERFACE_MODE == MODE_3LINE)
set_rs_high ; SCE to VCC
#endif
set_ce_high // disable chip
set_en_low
set_b0_low // ## reset b0 to GND to prevent incorrect detection of rotary encoder movement
ret // return _lcd_hw_write
#else /* no FAST_SPI_OUTPUT */
; Set RS (0=Cmd, 1=Char)
set_ce_low // enable chip
set_ce_output
#if (LCD_INTERFACE_MODE == MODE_3LINE)
set_en_low
set_rs_low
set_rs_output //init hardware
sbrc preg_1, 0
set_b0_high // set to data
sbrs preg_1, 0
set_b0_low // set to command
set_b0_output ; set B0 to output
set_rs_low ; SCE to GND
set_en_high ; force data read from LCD controller
#else
sbrc preg_1, 0
set_rs_high
sbrs preg_1, 0
set_rs_low
set_rs_output; //init hardware
set_b0_output ; wait for address setup, set B0 to output
#endif
; Send bit-7
ROL preg_2 // shift B7 to carry
rcall shift_out2
; Send bit-6
ROL preg_2 // shift B6 to carry
rcall shift_out2
; Send bit-5
ROL preg_2 // shift B5 to carry
rcall shift_out2
; Send bit-4
ROL preg_2 // shift B4 to carry
rcall shift_out2
; Send bit-3
ROL preg_2 // shift B3 to carry
rcall shift_out2
; Send bit-2
ROL preg_2 // shift B2 to carry
rcall shift_out2
; Send bit-1
ROL preg_2 // shift B1 to carry
rcall shift_out2
; Send bit-0
ROL preg_2 // shift B0 to carry
rcall shift_out2
#if (LCD_INTERFACE_MODE == MODE_3LINE)
set_rs_high ; SCE to VCC
#endif
set_ce_high // disable chip
set_en_low
set_b0_low // ## reset b0 to GND to prevent incorrect detection of rotary encoder movement
ret // return _lcd_hw_write
shift_out2:
set_en_low;
brcs set_bit
set_b0_low
rjmp fini_bit
set_bit:
set_b0_high // enable B0 pullup
fini_bit:
set_b0_output // set B0 to output mode
set_en_high // set en up
ret
#endif /* FAST_SPI_OUTPUT */
#endif /* LCD_SPI_OPEN_COL */
.endfunc
#elif (LCD_INTERFACE_MODE == MODE_7920_SERIAL) || (LCD_INTERFACE_MODE == MODE_1803_SERIAL)
;---------------------------------------------------------------------------------
_lcd_hw_write:
; 1-bit interface for ST7920 controller
set_b0_high
set_b0_output ; enable output mode
set_en_low
set_en_output ; enable output mode
RCALL toggle_en ; set en high and low
RCALL four_bits ; output four times 1
set_b0_low ; RW to write
RCALL toggle_en ; set en high and low
sbrc preg_1, 0
set_b0_high ; data mode
sbrs preg_1, 0
set_b0_low ; instruction mode
RCALL toggle_en ; set en high and low
set_b0_low
RCALL toggle_en ; set en high and low
; first 8 bit transfer finished
#if (LCD_INTERFACE_MODE == MODE_7920_SERIAL)
; output highest bit first
sbrc preg_2, 7
set_b0_high ; bit 7 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 6
set_b0_high ; bit 6 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 5
set_b0_high ; bit 5 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 4
set_b0_high ; bit 4 == 1
RCALL toggle_en ; set en high and low
set_b0_low
RCALL four_bits ; output 4 times 0
; the upper 4-bit are followed by 4 x 0
set_b0_low
sbrc preg_2, 3
set_b0_high ; bit 3 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 2
set_b0_high ; bit 2 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 1
set_b0_high ; bit 1 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 0
set_b0_high ; bit 0 == 1
RCALL toggle_en ; set en high and low
set_b0_low
RCALL four_bits ; output 4 times 0
; the lower 4-bit are followed by 4 x 0
#else /* (LCD_INTERFACE_MODE == MODE_1803_SERIAL) */
; output lowest bit first
sbrc preg_2, 0
set_b0_high ; bit 0 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 1
set_b0_high ; bit 1 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 2
set_b0_high ; bit 2 == 1
RCALL toggle_en ; set en high and low
; the upper 4-bit are followed by 4 x 0
set_b0_low
sbrc preg_2, 3
set_b0_high ; bit 3 == 1
RCALL toggle_en ; set en high and low
set_b0_low
RCALL four_bits ; output 4 times 0
; the lower 4-bit are followed by 4 x 0
set_b0_low
sbrc preg_2, 4
set_b0_high ; bit 4 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 5
set_b0_high ; bit 5 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 6
set_b0_high ; bit 6 == 1
RCALL toggle_en ; set en high and low
set_b0_low
sbrc preg_2, 7
set_b0_high ; bit 7 == 1
RCALL toggle_en ; set en high and low
set_b0_low
RCALL four_bits ; output 4 times 0
; the upper 4-bit are followed by 4 x 0
#endif
RCALL wait50us
RCALL wait30us ; at least 72 us delay
ret // return _lcd_hw_write
.endfunc
/* output 4 times the same bit */
four_bits:
RCALL toggle_en
RCALL toggle_en
RCALL toggle_en
RCALL toggle_en
ret
toggle_en:
set_en_high ;force data read from LCD controller
set_en_high ; hold en high to meet the specification (300ns)
set_en_low ; set SCLK back to low
ret
#elif (LCD_INTERFACE_MODE == MODE_I2C)
;---------------------------------------------------------------------------------
;===================================================
_lcd_hw_write:
; use I2C as master
push preg_2
push preg_1 ; save data/command
release_scl
rcall WAIT_I2C
set_low_sda ; set START bit
rcall WAIT_I2C
ldi preg_1, (LCD_I2C_ADDR*2)
rcall i2c_send ; write I2C address
pop preg_2
ldi preg_1,0x80 ; send command type
sbrc preg_2,0 ; skip if bit 0 is unset
ldi preg_1,0x40 ; send data type
rcall i2c_send ; send command/data
pop preg_1 ;restore data from parameter
rcall i2c_send ; write the data
set_low_sda ; set the sda signal to low STOP
rcall WAIT_I2C
release_scl ; pullup move the scl signal to high
rcall WAIT_I2C
release_sda ; pullup move the sda signal to high, STOP
rcall WAIT_I2C
ret // return _lcd_hw_write
;
;===================================================
i2c_send:
sec ;set carry
rol preg_1 ; shift carry to r24 bit 0 and bit 7 of r24 to carry
i2c_wf:
set_low_scl ; scl signal to low, data change
brcc wr0
; carry was set
release_sda ; pullup move the sda signal to high
rjmp wr1
wr0:
set_low_sda ; set the sda signal to low
wr1:
rcall WAIT_I2C ; wait defined time
release_scl ; pullup move the scl signal to high
rcall WAIT_I2C ; wait defined time
lsl preg_1
brne i2c_wf
; 8 bit are transfered
set_low_scl ; scl signal to low, data change
release_sda ; give sda free
rcall WAIT_I2C ; wait defined time
release_scl ; pullup move the scl signal to high, ack cycle
loop:
sbis HW_LCD_SCL_IN, HW_LCD_SCL_PIN
rjmp loop ; wait for releasing SCL
; r24 is zero, return 0
sbic HW_LCD_SDA_IN, HW_LCD_SDA_PIN
ldi preg_1,1 ; if SDA is returned high, answer 1
rcall WAIT_I2C ; wait defined time
set_low_scl
rcall WAIT_I2C ; wait defined time
ret
.endfunc
.global i2c_init
.func i2c_init
.extern wait5us
i2c_init:
release_sda
release_scl
cbi HW_LCD_SDA_OUT, HW_LCD_SDA_PIN ; set output to 0, no pull up
cbi HW_LCD_SCL_OUT, HW_LCD_SCL_PIN ; set output to 0, no pull up
ret
.endfunc
#elif (LCD_INTERFACE_MODE == MODE_7108_SERIAL)
;---------------------------------------------------------------------------------
_lcd_hw_write:
; serial interface for ST7108 controller
set_clk_low
set_clk_output
set_pclk_low
set_pclk_output
set_en_low
set_en_output
set_b0_low
set_b0_output
sbrc preg_2, 7
set_b0_high ; bit 7 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 6
set_b0_high ; bit 6 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 5
set_b0_high ; bit 5 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 4
set_b0_high ; bit 4 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 3
set_b0_high ; bit 3 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 2
set_b0_high ; bit 2 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 1
set_b0_high ; bit 1 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
sbrc preg_2, 0
set_b0_high ; bit 0 == 1
#ifdef FAST_SERIAL_OUT
set_clk_high ; set clk high and low
set_clk_low
set_b0_low
#else
RCALL toggle_clk ; set clk high and low
#endif
; all 8 bit are loaded to the 74HC164 output
set_pclk_high ; set parallel clk high and low
set_pclk_low
set_rs_low ; instruction mode
set_rs_output ; if RS is set to same as B0, RS is allready output
sbrc preg_1, 0
set_rs_high ; data mode
RCALL wait1us ; hold the setup time of RS
set_en_high
RCALL wait1us
set_en_low
; RCALL wait30us ; at least 30 us delay
RCALL wait10us ; at least 10 us delay
ret
.endfunc
#ifndef FAST_SERIAL_OUT
toggle_clk:
set_clk_high
set_clk_high
set_clk_low
set_b0_low
ret
#endif
#else /* !(LCD_INTERFACE_MODE == (MODE_SPI | MODE_7920_SERIAL | MODE_I2C | MODE_7108_SERIAL)) */
;---------------------------------------------------------------------------------
_lcd_hw_write:
; must be a 4-bit parallel interface for HD44780 compatible controller or simular
; Set RS (0=Cmd, 1=Char)
sbrc preg_1, 0
set_rs_high
sbrs preg_1, 0
set_rs_low
set_rs_output; //init hardware
nop ; //wait for address setup
set_en_high
set_en_output; //init hardware
; Send high nibble
set_b4_low
set_b5_low
set_b6_low
set_b7_low
sbrc preg_2, 4
set_b4_high
set_b4_output; //init hardware
sbrc preg_2, 5
set_b5_high
set_b5_output; //init hardware
sbrc preg_2, 6
set_b6_high
set_b6_output; //init hardware
sbrc preg_2, 7
set_b7_high
set_b7_output; //init hardware
nop ; wait for data setup time
set_en_low ; force data read from LCD controller
RCALL wait1us
; skip sending low nibble for init commands
sbrc preg_1, 7
rjmp _lcd_hw_write_exit
; Send low nibble
set_en_high
set_b4_low
set_b5_low
set_b6_low
set_b7_low
sbrc preg_2, 0
set_b4_high
sbrc preg_2, 1
set_b5_high
sbrc preg_2, 2
set_b6_high
sbrc preg_2, 3
set_b7_high
nop ; wait for data setup time
set_en_low ; force data read from LCD controller
#if (LCD_ST_TYPE == 7920)
RCALL wait50us
#endif
#ifdef SLOW_LCD
RCALL wait50us
#else
RCALL wait1us
#endif
_lcd_hw_write_exit:
ret ; end _lcd_hw_write
.endfunc
#endif /* LCD_INTERFACE_MODE */
;----------------------------------------------------------------------
#if (LCD_ST_TYPE == 7108)
.global _lcd_hw_select
.func _lcd_hw_select
; select one of the two controllers or both
;
; preg_1 (r24) = bit 0 for CS1 and bit 1 for CS2
;
_lcd_hw_select:
#ifdef ST_CS_LOW /* inverted CS level, 0 = enable */
sbrc preg_1, 0
set_cs1_low ; enable controller 1
sbrs preg_1, 0
set_cs1_high ; disable controller 1
sbrc preg_1, 1
set_cs2_low ; enable controller 2
sbrs preg_1, 1
set_cs2_high ; disable controller 2
#else /* not inverted CS level, 1 = enable */
sbrc preg_1, 0
set_cs1_high ; enable controller 1
sbrs preg_1, 0
set_cs1_low ; disable controller 1
sbrc preg_1, 1
set_cs2_high ; enable controller 2
sbrs preg_1, 1
set_cs2_low ; disable controller 2
#endif
set_cs1_output ; enable output CS1
set_cs2_output ; enable output CS2
ret
.endfunc
#endif
|
akshaybaweja/component-tester-oled
| 2,153
|
Source Code/RvalOut.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include <avr/eeprom.h>
#include <stdlib.h>
#include "config.h"
#include "part_defs.h"
/* #include <avr/io.h> */
/* #include <avr/eeprom.h> */
/* #include <avr/pgmspace.h> */
/* #include "Transistortester.h" */
/* void RvalOut(uint8_t nrr) { */
/* // output of resistor value */
/* #if FLASHEND > 0x1fff */
/* uint16_t rr; */
/* if ((resis[nrr].rx < 100) && (inductor_lpre == 0)) { */
/* rr = GetESR(resis[nrr].ra,resis[nrr].rb); */
/* DisplayValue(rr,-2,LCD_CHAR_OMEGA,3); */
/* } else { */
/* DisplayValue(resis[nrr].rx,-1,LCD_CHAR_OMEGA,4); */
/* } */
/* #else */
/* DisplayValue(resis[nrr].rx,-1,LCD_CHAR_OMEGA,4); */
/* #endif */
/* lcd_space(); */
/* } */
#define zero_reg r1
#define RCALL rcall
.GLOBAL RvalOut
.func RvalOut
.extern DisplayValue
.extern GetESR
.extern lcd_space
.extern ResistorVal
.section .text
RvalOut: ; void RvalOut(uint8_t nrr)
push r16
mov r16, r24
LDIZ ResistorVal
add r24, r24 ; nrr*2
add r24, r24 ; nrr*4
add r30, r24
adc r31, zero_reg
ld r22, Z ; resis[rr].rx
ldd r23, Z+1 ; 0x01
ldd r24, Z+2 ; 0x02
ldd r25, Z+3 ; 0x03
#if FLASHEND > 0x1fff
cpi r22, 0x64 ; 100
cpc r23, r1
cpc r24, r1
cpc r25, r1
brcc ad1d8e ; (ResistorVal[nrr] < 100)
lds r18, inductor_lpre
sbrc r18, 7 ; minus bit set?
rjmp ad1d8e ; (inductor_lpre >= 0)
mov r24,r16
ACALL Rnum2pins; ; pins = Rnum2pins(nrr)
mov r22, r25
ACALL GetESR ; rr = GetESR(resis[nrr].ra,resis[nrr].rb);
; movw r22, r24
; ldi r24, 0
; ldi r25, 0
; ldi r20, -2 ; 254
; ldi r16, 0x03 ; 3
; rjmp ad1d94 ; DisplayValue(rr,-2,LCD_CHAR_OMEGA,3);
ldi r22, -2
ldi r18, 3
ldi r20, LCD_CHAR_OMEGA
RCALL DisplayValue16 ; DisplayValue16(rr,-2,LCD_OMEGA,3);
rjmp ret_with_space
ad1d8e: ; } else {
#endif
; r22-r25 = ResistorVal[rr]
ldi r20, -1 ; 255
ldi r16, 0x04 ; DisplayValue(resis[nrr].rx,-1,LCD_CHAR_OMEGA,4);
;ad1d94:
ldi r18, LCD_CHAR_OMEGA ; 244
RCALL DisplayValue
ret_with_space:
RCALL lcd_space ; lcd_space();
pop r16
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 3,938
|
Source Code/GetRLmultip.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/eeprom.h>
#include <stdlib.h>
#include "config.h"
#define zero_reg r1
/* unsigned int GetRLmultip(unsigned int cvolt) { */
// interpolate table RLtab corresponding to voltage cvolt
/* unsigned int uvolt; */
/* unsigned int y1, y2; */
/* uint8_t tabind; */
/* uint8_t tabres; */
/* if (cvolt >= RL_Tab_Beginn) { */
/* uvolt = cvolt - RL_Tab_Beginn; */
/* } else { */
/* uvolt = 0; // limit to begin of table */
/* } */
/* tabind = uvolt / RL_Tab_Abstand; */
/* tabres = uvolt % RL_Tab_Abstand; */
/* tabres = RL_Tab_Abstand - tabres; */
/* if (tabind > ((RL_Tab_Length/RL_Tab_Abstand)-1)) { */
/* tabind = (RL_Tab_Length/RL_Tab_Abstand)-1; // limit to end of table */
/* tabres = 0; */
/* } */
/* y1 = MEM_read_word(&RLtab[tabind]); */
/* y2 = MEM_read_word(&RLtab[tabind+1]); */
/* return ( ((y1 - y2) * tabres + (RL_Tab_Abstand/2)) / RL_Tab_Abstand + y2); // interpolate table */
/*} */
.GLOBAL GetRLmultip
.func GetRLmultip
#define RL_Tab_Abstand 25 // displacement of table 25mV
#define RL_Tab_Beginn 300 // begin of table ist 300mV
#define RL_Tab_Length 1100 // length of table is 1400-300
.section .text
; unsigned int GetRLmultip(unsigned int cvolt)
GetRLmultip:
push r0
ldi r18, hi8(RL_Tab_Beginn) ; 1
cpi r24, lo8(RL_Tab_Beginn) ; 44
cpc r25, r18
brcc is_bigger ;if (cvolt >= RL_Tab_Beginn)
ldi r24, lo8(RL_Tab_Beginn) ; uvolt = 0 = RL_Tab_Begin - RL_Tab_Begin
ldi r25, hi8(RL_Tab_Beginn) ; limit to begin of table
is_bigger:
subi r24, lo8(RL_Tab_Beginn) ; uvolt = cvolt - RL_Tab_Beginn;
sbci r25, hi8(RL_Tab_Beginn) ; 1
ldi r22, lo8(RL_Tab_Abstand) ; 25
ldi r23, hi8(RL_Tab_Abstand) ; 0
ACALL __udivmodhi4 ;tabind = uvolt / RL_Tab_Abstand;
; r24:25 tabres = uvolt % RL_Tab_Abstand; // r25 allways zero
; tabres = RL_Tab_Abstand - tabres;
ldi r25, RL_Tab_Abstand ; 25
cpi r22, ((RL_Tab_Length/RL_Tab_Abstand)-1) ; if (tabind > ((RL_Tab_Length/RL_Tab_Abstand)-1))
brcs is_lower
mov r25, r24 ; tabres = 0 = (RL_Tab_Abstand==tabres) - tabres
ldi r22, (RL_Tab_Length/RL_Tab_Abstand)-1; tabind = (RL_Tab_Length/RL_Tab_Abstand)-1;// limit to end of table
is_lower:
sub r25, r24 ; tabres = RL_Tab_Abstand - tabres;
; r22 = tabind , r25 = tabres
LDIZ RLtab
add r30, r22 ; + tabind
adc r31, zero_reg
add r30, r22 ; + tabind (word access)
adc r31, zero_reg
#ifdef MEM_EEPROM
push r25 ; save tabres
movw r24,r30
ACALL eeprom_read_byte ; y1 = MEM_read_word(&RLtab[tabind]);
mov r20, r24
adiw r30, 1 ; address of high order byte
movw r24,r30
ACALL eeprom_read_byte ; y1 = MEM_read_word(&RLtab[tabind]);
mov r21, r24
adiw r30, 1 ; tabind+1
movw r24,r30
ACALL eeprom_read_byte ; y2 = MEM_read_word(&RLtab[tabind+1]);
mov r18, r24
adiw r30, 1 ; address of high order byte
movw r24,r30
ACALL eeprom_read_byte ; y2 = MEM_read_word(&RLtab[tabind+1]);
mov r19, r24
pop r22 ; restore tabres in r22
#else
lpm r20, Z+ ; y1 = MEM_read_word(&RLtab[tabind]);
lpm r21, Z+
lpm r18, Z+ ; y2 = MEM_read_word(&RLtab[tabind+1]);
lpm r19, Z+
mov r22, r25
#endif
; return ( ((y1 - y2) * tabres + (RL_Tab_Abstand/2)) / RL_Tab_Abstand + y2); // interpolate table
;; ldi r23, 0x00 ; hi8(tabres) allways zero
sub r20, r18 ; y1 - y2
sbc r21, r19 ; maximum of 3466 need two registers
mul r22, r20 ;lo8(tabres) * lo8(y1-y2)
movw r24, r0 ; r24:25 = *
mul r22, r21 ;lo8(tabres) * hi8(y1-y2)
add r25, r0 ; r25 + lo8(*)
;; mul r23, r20 ;hi8(tabres) * lo8(y1-y2) , allways zero
;; add r25, r0 ; r25 + lo8(*)
eor r1, r1
adiw r24, (RL_Tab_Abstand/2) ; 12
ldi r22, lo8(RL_Tab_Abstand) ; 25
ldi r23, hi8(RL_Tab_Abstand) ; 0
ACALL __udivmodhi4 ; ((y1 - y2) * tabres + (RL_Tab_Abstand/2)) / RL_Tab_Abstand
add r22, r18 ; + y2
adc r23, r19
movw r24, r22
pop r0
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 1,117
|
Source Code/CombineToLong.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include "config.h"
#include <stdlib.h>
.section .text
.func CombineII2Long
.global CombineBI2Long
.global CombineII2Long
// This tricky function replaces the long-winded way of gcc compiler
// to build = high*65536 + low
// if there is any way to shorten the gcc implementation,
// this function can be omitted.
;//unsigned long CombineBI2Long(uint8_t high, unsigned int low)
; {
CombineBI2Long:
// r24 = high input (byte)
// r22,r23 = low input
// CombineToLong = (unsigned long)(((unsigned long)high * 65536) + low); //compute total
// CombineToLong = r22-r25
clr r25 //in case of high is byte, clear upper byte
// ret // because next function has nothing to do, use that return
;//unsigned long CombineII2Long(unsigned int high, unsigned int low)
; {
CombineII2Long:
// r24,r25 = high input
// r22,r23 = low input
// CombineToLong = (unsigned long)(((unsigned long)high * 65536) + low); //compute total
// CombineToLong return value = r22-r25
// in case of high is unsigned int, nothing to do
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 5,524
|
Source Code/wait_for_key_ms.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <stdlib.h>
#include "config.h"
#include "lcd_defines.h"
#ifdef WITH_ROTARY_SWITCH
#warning Please use the C-version of this program, if you use the Rotary Switch!
#error Modify your Makefile!
#endif
#define RCALL rcall
#define MAX_CS 150
#define incre 6
.GLOBAL wait_for_key_ms
#if INHIBIT_SLEEP_MODE
.extern wait200ms
.extern wait10ms
#else
.extern sleep_5ms
#endif
.func wait_for_key_ms
.section .text
;/* wait max_time or previous key press */
;/* max_time zero wait without time limit */
;/* return value: !=0 == key is pressed for xx*10ms, 0 == key is not pressed, time expired */
;uint8_t wait_for_key_ms(int max_time)
wait_for_key_ms:
push r14
push r15
push r16
push r17
push r28 ; save registers r28:29
push r29
movw r14, r24 ; r14:15 = max_time
; // if key is pressed, return 1
; // if max_time == 0 , do not count, wait endless
ldi r28, 101 ; kk = 100
wrelease:
sbic _SFR_IO_ADDR(RST_PIN_REG), RST_PIN ; if((RST_PIN_REG & (1<<RST_PIN)))
rjmp no_w200
#if INHIBIT_SLEEP_MODE
RCALL wait5ms ; wait5ms();
#else
ldi r24, 1
RCALL sleep_5ms ; wait_about5ms();
#endif
subi r28, 1 ; kk--;
brne wrelease ; while (kk >= 0)
no_w200:
movw r28,r14 ; count_time = max_time
ldi r16, 0x55 ; key_pressed = 0x55;
ldi r17, 0 ; key_cs = 0
; wait max_time milliseconds or endless, if zero
no_cnt:
sbrc r29, 7 ; while (count_time >= 0)
rjmp to_ret
wloop:
#if INHIBIT_SLEEP_MODE
RCALL wait10ms ; wait10ms();
#else
ldi r24, 0x02 ; 2
RCALL sleep_5ms ; wait_about10ms();
#endif
add r16, r16 ; key_pressed += key_pressed; // multiply with 2 is shift to left
sbis _SFR_IO_ADDR(RST_PIN_REG), RST_PIN ; if((RST_PIN_REG & (1<<RST_PIN))) {
subi r16, 0xff ; key_pressed++; //append a 1
andi r16, 0x3f ; key_pressed &= 0x3f;
cpi r16, 0x3f ; if (key_pressed == 0x3f) //63 all bits set
brne not_pressed
cpse r17, r1 ; if (key_cs == 0)
rjmp no_first
movw r28,r14 ; count_time = max_time;
ldi r17, 4 ; key_cs = 4;
no_first:
subi r17, 0xff ; key_cs++;
cpi r17, MAX_CS ; if (key_cs >= MAX_CS)
brcs cnt_loop ;
rjmp to_ret ; break;
not_pressed:
cpse r16, r1 ; if (( key_pressed == 0) &&
rjmp cnt_loop
cpse r17, r1 ; ( key_cs != 0))
rjmp to_ret ; break;
cnt_loop:
wdr ; wdt_reset();
sbiw r28, 0x00 ; if (count_time > 0) // count only, if counter > 0
breq no_cnt ; special case zero, don't count
sbiw r28, 0x0a ; count_time -= 10; // 10 ms are done, count down
brne no_cnt ; if (count_time == 0) count_time = -1; // never count to zero, zero is endless!
ldi r28, 0xFF ; count_time = -1
ldi r29, 0xFF ;
rjmp no_cnt
to_ret:
mov r24, r17 ; return(key_cs)
pop r29 ; restore registers r29:28
pop r28
pop r17
pop r16
pop r15
pop r14
ret
.endfunc
#ifdef WAIT_LINE2_CLEAR
.GLOBAL wait_for_key_5s_line2
.extern wait_for_key_ms
.extern lcd_line2
.extern lcd_clear_line
.func wait_for_key_5s_line2
; /* wait 5 seconds or previous key press, then clear line 2 of LCD and */
; /* set the cursor to the beginning of line 2 */
; void wait_for_key_5s_line2(void)
wait_for_key_5s_line2:
#if 0
ldi r24, '+'
RCALL lcd_data ; lcd_data('+');
ldi r24, lo8(SHORT_WAIT_TIME) ; 0x88
ldi r25, hi8(SHORT_WAIT_TIME) ; 0x13
RCALL wait_for_key_ms ;wait_for_key_ms(SHORT_WAIT_TIME);
#if (LCD_LINES < 4)
RCALL lcd_line2 ; //2. row
RCALL lcd_clear_line ; lcd_clear_line(); // clear the whole line
RCALL lcd_line2 ; //2. row
#else
RCALL lcd_line4 ; //4. row
RCALL lcd_clear_line ; lcd_clear_line(); // clear the whole line
RCALL lcd_line4 ; //4. row
#endif
#else
push r28
RCALL lcd_save_position
mov r28, r24 ; current_line = lcd_save_position()
lds r24, last_line_used
and r24, r24
breq x83c ; if (last_line_used != 0)
cpi r24, 1
brne x822
cpi r28, (LCD_LINES-1)
brne x822 ; if ((last_line_used == 1) &&(current_line == (LCD_LINES-1)))
ldi r22, (LCD_LINE_LENGTH -1)
ldi r24, ((LCD_LINES - 1) * PAGES_PER_LINE)
rcall lcd_set_cursor ; lcd_set_cursor(((LCD_LINES - 1) * PAGES_PER_LINE), (LCD_LINE_LENGTH - 1))
ldi r24, '+' ; // add a + sign at the last location of screen
rcall lcd_data ; lcd_data('+')
ldi r22, (LCD_LINE_LENGTH -1)
ldi r24, ((LCD_LINES - 1) * PAGES_PER_LINE)
rcall lcd_set_cursor ; lcd_set_cursor(((LCD_LINES - 1) * PAGES_PER_LINE), (LCD_LINE_LENGTH - 1))
x822:
#ifdef WITH_ROTARY_SWITCH
ldi r24, lo8(SHORT_WAIT_TIME) ; 0x88
ldi r25, hi8(SHORT_WAIT_TIME) ; 0x13
rcall wait_for_key_ms ;wait_for_key_ms(SHORT_WAIT_TIME); // wait until time is elapsed or key is pressed
cpse r24, r1
rjmp x855
lds r24, rotary+incre
cpse r24, r1
rjmp x822
#else
ldi r24, lo8(SHORT_WAIT_TIME) ; 0x88
ldi r25, hi8(SHORT_WAIT_TIME) ; 0x13
rcall wait_for_key_ms ;wait_for_key_ms(SHORT_WAIT_TIME); // wait until time is elapsed or key is pressed
#endif
x855:
cpi r28, (LCD_LINES - 1) ; (current_line == (LCD_LINES - 1))
brne x83a
lds r24, last_line_used
cpi r24, 1
brne x83a ; if ((current_line == (LCD_LINES - 1)) && (last_line_used == 1))
ldi r24, (LCD_LINES - 1)
ldi r22, 0x00 ; 0
rcall lcd_set_cursor ; lcd_set_cursor((LCD_LINES-1) * PAGES_PER_LINE,0)
rcall lcd_clear_line
x83a:
rcall lcd_restore_position
x83c:
pop r28
#endif
ret
.endfunc
#endif
|
akshaybaweja/component-tester-oled
| 7,905
|
Source Code/PinLayout.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include "config.h"
#include "part_defs.h"
;// show the Pin Layout of the device
; void PinLayout(char pin1, char pin2, char pin3)
;// pin1-3 is EBC or SGD or CGA
; typedef struct {
; unsigned long hfe; //0 current amplification factor
; unsigned int uBE; //4 B-E-voltage of the Transistor
; unsigned int current; //6 current of Drain in 0.01mA
; // for bipolar current is ICE0
; unsigned int gthvoltage; //8 Gate-threshold voltage
; // for bipolar gthvoltage is ICEs in 0.01mA
; uint8_t b,c,e; //10,11,12 pins of the Transistor
; uint8_t count; //13
; }trans_t;
#define RCALL rcall
.GLOBAL PinLayout
.func PinLayout
.extern lcd_data
.extern lcd_space
.extern lcd_testpin
.extern _trans
#define OFFS_b 12 /* offset to trans.b */
#define OFFS_c 13 /* offset to trans.c */
#define OFFS_e 14 /* offset to trans.e */
.extern N123_str
.extern N321_str
PinLayout:
#ifndef EBC_STYLE
; // Layout with 123= style
push r14
push r15
push r16
push r17
mov r17, r24 ; Pin1
mov r16, r22 ; Pin2
mov r15, r20 ; Pin3
ldi r24, lo8(N123_str) ; 0x0B
ldi r25, hi8(N123_str) ; 0x01
#ifdef USE_EEPROM
RCALL lcd_fix_string ; lcd_MEM_string(N123_str); //" 123="
#else
RCALL lcd_pgm_string ; lcd_MEM_string(N123_str); //" 123="
#endif
eor r14, r14 ; for (ipp=0;
loop1:
lds r30, _trans
lds r31, _trans+1
ldd r24, Z+OFFS_e ; _trans->e
cp r14, r24
brne checkb ; if (ipp == _trans->e)
mov r24, r17 ; pin1
rjmp data_ipp ; lcd_data(pin1); // Output Character in right order
checkb:
ldd r24, Z+OFFS_b ; _trans->b
cp r14, r24 ; if (ipp == _trans->b)
brne checkc
mov r24, r16
rjmp data_ipp ; lcd_data(pin2);
checkc:
ldd r24, Z+OFFS_c ; _trans->c
cp r14, r24
brne next_ipp ; if (ipp == _trans->c)
mov r24, r15
data_ipp:
RCALL lcd_data ; lcd_data(pin3);
next_ipp:
inc r14
mov r24, r14
cpi r24, 0x03 ; for ( ;ipp<3;ipp++) {
brne loop1
pop r17
pop r16
pop r15
pop r14
ret
#else
#if EBC_STYLE == 321
; // Layout with 321= style
push r14
push r15
push r16
push r17
mov r17, r24 ; Pin1
mov r16, r22 ; Pin2
mov r15, r20 ; Pin3
ldi r24, lo8(N321_str) ; 0x0B
ldi r25, hi8(N321_str) ; 0x01
#ifdef USE_EEPROM
RCALL lcd_fix_string ; lcd_MEM_string(N321_str); //" 321="
#else
RCALL lcd_pgm_string ; lcd_MEM_string(N321_str); //" 321="
#endif
ldi r24, 0x03 ; 3
mov r14, r24 ; ipp = 3;
loop2:
dec r14 ; ipp--;
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_e ; _trans->e
cp r14, r24
brne checkb ; if (ipp == _trans->e)
mov r24, r17 ; lcd_data(pin1); // Output Character in right order
rjmp data_ipp2
checkb:
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_b ; _trans->b
cp r14, r24
brne checkc ; if (ipp == _trans->b)
mov r24, r16 ; lcd_data(pin2);
rjmp data_ipp2
checkc:
ldd r24, Z+OFFS_c ; _trans->c
cp r14, r24
brne next_ipp2 ; if (ipp == _trans->c)
mov r24, r15 ; lcd_data(pin3);
data_ipp2:
RCALL lcd_data ; lcd_data(pinx);
next_ipp2:
and r14, r14 ; while (ipp != 0)
brne loop2
pop r17
pop r16
pop r15
pop r14
ret
#else
; // Layout with EBC= style
push r15
push r16
push r17
mov r17, r24 ; Pin1
mov r16, r22 ; Pin2
mov r15, r20 ; Pin3
RCALL lcd_space ; lcd_space();
mov r24, r17 ; Pin1
RCALL lcd_data ; lcd_data(pin1);
mov r24, r16 ; Pin2
RCALL lcd_data ; lcd_data(pin2);
mov r24, r15 ; Pin3
RCALL lcd_data ; lcd_data(pin3);
RCALL lcd_equal ; lcd_data('=');
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_e ; _trans->e
RCALL lcd_testpin ; lcd_testpin(_trans->e);
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_b ; _trans->b
RCALL lcd_testpin ; lcd_testpin(_trans->b);
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_c ; _trans->c
RCALL lcd_testpin ; lcd_testpin(_trans->c);
pop r17
pop r16
pop r15
ret
#endif
#endif
.endfunc
#ifdef WITH_GRAPHICS
.GLOBAL PinLayoutLine
.func PinLayoutLine
PinLayoutLine:
push r14
push r15
push r16
push r17
mov r17, r24 ; Pin1
mov r16, r22 ; Pin2
mov r15, r20 ; Pin3
ldi r24, 0
call lcd_next_line_wait ; lcd_next_line_wait(0);
#ifdef NO_LONG_PINLAYOUT
RCALL lcd_space ; lcd_space()
ldi r24, lo8(Pin_str) ;
ldi r25, hi8(Pin_str) ;
#ifdef USE_EEPROM
RCALL lcd_fix_string ; lcd_MEM_string(Pin_str); //"Pin "
#else
RCALL lcd_pgm_string ; lcd_MEM_string(Pin_str); //"Pin "
#endif
mov r20, r15
mov r22, r16
mov r24, r17
RCALL PinLayout ; PinLayout(Pin1, Pin2, Pin3)
#else
ldi r24, lo8(Pin_str) ;
ldi r25, hi8(Pin_str) ;
#ifdef USE_EEPROM
RCALL lcd_fix_string ; lcd_MEM_string(Pin_str); //"Pin "
#else
RCALL lcd_pgm_string ; lcd_MEM_string(Pin_str); //"Pin "
#endif
#ifndef EBC_STYLE
; // Layout with 1= 2= 3= style
eor r14, r14 ; for (ipp=0;
lloop1:
mov r24, r14
RCALL lcd_testpin ; lcd_testpin(ipp)
RCALL lcd_equal ; lcd_data('=')
lds r30, _trans
lds r31, _trans+1
ldd r24, Z+OFFS_e ; _trans->e
cp r14, r24
brne lcheckb ; if (ipp == _trans->e)
mov r24, r17 ; pin1
rjmp ldata_ipp ; lcd_data(pin1); // Output Character in right order
lcheckb:
ldd r24, Z+OFFS_b ; _trans->b
cp r14, r24 ; if (ipp == _trans->b)
brne lcheckc
mov r24, r16
rjmp ldata_ipp ; lcd_data(pin2);
lcheckc:
ldd r24, Z+OFFS_c ; _trans->c
cp r14, r24
brne lnext_ipp ; if (ipp == _trans->c)
mov r24, r15
ldata_ipp:
RCALL lcd_data ; lcd_data(pin3);
lnext_ipp:
RCALL lcd_space ; lcd_space()
inc r14
mov r24, r14
cpi r24, 0x03 ; for ( ;ipp<3;ipp++) {
brne lloop1
#else
#if EBC_STYLE == 321
; // Layout with 3= 2= 1= style
ldi r24, 0x03 ; 3
mov r14, r24 ; ipp = 3;
lloop2:
dec r14 ; ipp--;
mov r24, r14
RCALL lcd_testpin ; lcd_testpin(ipp)
RCALL lcd_equal ; lcd_data('=')
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_e ; _trans->e
cp r14, r24
brne lcheckb ; if (ipp == _trans->e)
mov r24, r17 ; lcd_data(pin1); // Output Character in right order
rjmp ldata_ipp2
lcheckb:
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_b ; _trans->b
cp r14, r24
brne lcheckc ; if (ipp == _trans->b)
mov r24, r16 ; lcd_data(pin2);
rjmp ldata_ipp2
lcheckc:
ldd r24, Z+OFFS_c ; _trans->c
cp r14, r24
brne lnext_ipp2 ; if (ipp == _trans->c)
mov r24, r15 ; lcd_data(pin3);
ldata_ipp2:
RCALL lcd_data ; lcd_data(pinx);
lnext_ipp2:
RCALL lcd_space ; lcd_space()
and r14, r14 ; while (ipp != 0)
brne lloop2
#else
; // Layout with E= B= C= style
mov r24, r17 ; Pin1
RCALL lcd_data ; lcd_data(pin1);
RCALL lcd_equal ; lcd_data('=')
lds r30, _trans ;
lds r31, _trans+1 ;
ldd r24, Z+OFFS_e ; _trans->e
RCALL lcd_testpin ; lcd_testpin(_trans->e);
RCALL lcd_space ; lcd_space()
mov r24, r16 ; Pin2
RCALL lcd_data ; lcd_data(pin2);
RCALL lcd_equal ; lcd_data('=')
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_b ; _trans->b
RCALL lcd_testpin ; lcd_testpin(_trans->b);
RCALL lcd_space ; lcd_space()
mov r24, r15 ; Pin3
RCALL lcd_data ; lcd_data(pin3);
RCALL lcd_equal ; lcd_data('=');
lds r30, _trans ;0x0142
lds r31, _trans+1 ;0x0143
ldd r24, Z+OFFS_c ; _trans->c
RCALL lcd_testpin ; lcd_testpin(_trans->c);
#endif /* =321 */
#endif /* EBC_STYLE */
#endif /* NO_LONG_PINLAYOUT */
pop r17 ; restore registers and return
pop r16
pop r15
pop r14
ret
.endfunc
#endif /* WITH_GRAPHICS */
.GLOBAL Rnum2pins
.func Rnum2pins
Rnum2pins:
mov r22,r24
ldi r24, TP1
ldi r25, TP3
and r22,r22
brne nozero
ldi r25, TP2
nozero:
cpi r22, 2
brne no_two
ldi r24, TP2
no_two:
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 3,919
|
Source Code/RefVoltage.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/eeprom.h>
#include "config.h"
#include "part_defs.h"
#define zero_reg r1
#define Ref_Tab_Abstand 50
; displacement of table is 50mV
#define Ref_Tab_Beginn 1000
; // begin of table is 1000mV
.GLOBAL RefVoltage
.func RefVoltage
.extern eeprom_read_byte
.extern RHtab
.section .text
RefVoltage:
#ifdef AUTO_CAL
ldi r24, lo8(ref_offset) ; 1
ldi r25, hi8(ref_offset) ; 0
;; ACALL eeprom_read_word ; eeprom_read_word((uint16_t *)(&ref_offset));
;; lds r18, ref_mv
;; lds r19, ref_mv+1
;; add r18, r24 ; referenz = ref_mv +
;; adc r19, r25
ACALL eeprom_read_byte ; eeprom_read_word((uint16_t *)(&ref_offset)); done as two read_byte
mov r19, r24
ldi r24, lo8(ref_offset+1)
ldi r25, hi8(ref_offset+1)
ACALL eeprom_read_byte
lds r18, ref_mv
add r18, r19
lds r19, ref_mv+1
adc r19, r24
#else
lds r18, ref_mv
lds r19, ref_mv+1
subi r18, -REF_C_KORR ; referenz = ref_mv + REF_C_KORR;
adc r19, zero_reg
#endif
sts ref_mv_offs, r18
sts ref_mv_offs+1, r19
#ifdef AUTO_RH
ldi r24, hi8(Ref_Tab_Beginn) ; 3
cpi r18, lo8(Ref_Tab_Beginn) ; 232
cpc r19, r24
brcs ad210e ; if (referenz >= Ref_Tab_Beginn)
movw r24, r18
subi r24, lo8(Ref_Tab_Beginn) ; 232 referenz -= Ref_Tab_Beginn;
sbci r25, hi8(Ref_Tab_Beginn) ; 3
rjmp ad2112
ad210e:
ldi r24, 0x00 ; referenz = 0; // limit to begin of table
ldi r25, 0x00 ; 0
ad2112:
ldi r22, lo8(Ref_Tab_Abstand) ; 50 tabind = referenz / Ref_Tab_Abstand;
ldi r23, hi8(Ref_Tab_Abstand) ; 0
ACALL __udivmodhi4
; r22 = tabind = referenz / Ref_Tab_Abstand;
; r24 = tabres = referenz % Ref_Tab_Abstand;
cpi r22, 0x08 ; if (tabind > 7)
brcs ad2120
ldi r22, 0x07 ; tabind = 7; // limit to end of table
ad2120:
; // interpolate the table of factors
LDIZ RHtab
add r30, r22
adc r31, zero_reg
add r30, r22
adc r31, zero_reg
lpm r20, Z+ ; y1 = pgm_read_word(&RHtab[tabind]);
lpm r21, Z+
lpm r18, Z+ ; y2 = pgm_read_word(&RHtab[tabind+1]);
lpm r19, Z+
ldi r22, Ref_Tab_Abstand ; 50
sub r22, r24 ; tabres = Ref_Tab_Abstand-tabres;
; // interpolate the table of factors
; // RHmultip is the interpolated factor to compute capacity from load time with 470k
;; ldi r23, 0x00 ; 0
sub r20, r18 ; y1 - y2
#if FLASHEND > 0x1fff
sbc r21, r19 ; hi8(y1 - y2) is usually allway zero
#endif
mul r22, r20 ; lo8(tabres) * lo8(y1-y2)
movw r24, r0 ; r24:25 = *
#if FLASHEND > 0x1fff
mul r22, r21 ; lo8(tabres) * hi8(y1-y2)
add r25, r0 ; r25 + lo8(*)
#endif
;; mul r23, r20 ; hi8(tabres) * lo8(y1*y2) , allways zero
;; add r25, r0 ; r25 + lo8(*)
eor r1, r1
adiw r24, (Ref_Tab_Abstand/2) ; 25
ldi r22, lo8(Ref_Tab_Abstand) ; 50
ldi r23, hi8(Ref_Tab_Abstand) ; 0
ACALL __udivmodhi4 ; ((y1 - y2) * tabres + (Ref_Tab_Abstand/2)) / Ref_Tab_Abstand
add r22, r18 ; + y2
adc r23, r19
sts RHmultip+1, r23
sts RHmultip, r22
#else
ldi r22, lo8(DEFAULT_RH_FAKT)
ldi r23, hi8(DEFAULT_RH_FAKT)
sts RHmultip, r22
sts RHmultip+1, r23
#endif
#ifdef AUTO_CAL
ldi r24, lo8(RefDiff)
ldi r25, hi8(RefDiff)
ACALL eeprom_read_byte ; (int8_t)eeprom_read_byte((uint8_t *)&RefDiff));
eor r25, r25 ; set zero for sign extend
sbrc r24, 7 ; minus?
com r25 ; yes, set to 0xff
lds r22, ref_mv ; ADCconfig.U_Bandgap = (ref_mv + (int8_t)eeprom_read_byte((uint8_t *)&RefDiff));
lds r23, ref_mv+1
add r24, r22
adc r25, r23
#else
ldi r22, lo8(REF_R_KORR)
ldi r23, hi8(REF_R_KORR)
lds r24, ref_mv ; ADCconfig.U_Bandgap = (ref_mv + REF_R_KORR);
lds r25, ref_mv+1
add r24, r22
adc r25, r23
#endif
#define U_Bandgap 2
sts ADCconfig+U_Bandgap+1, r25
sts ADCconfig+U_Bandgap, r24
sts adc_internal_reference+1, r25 ; adc_internal_reference = ADCconfig.U_Bandgap;
sts adc_internal_reference, r24
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 3,686
|
Source Code/lcd_hw_1_bit.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
;---------------------------------------------------------------------
#include <avr/io.h>
#include "config.h"
.section .text
;----------------------------------------------------------------------
; Global Definitions
;----------------------------------------------------------------------
#define preg_1 r24
#define preg_2 r22
; Serial Clock Input (SCL)
#define set_en_low cbi _SFR_IO_ADDR(HW_LCD_EN_PORT), HW_LCD_EN_PIN
#define set_en_high sbi _SFR_IO_ADDR(HW_LCD_EN_PORT), HW_LCD_EN_PIN
; Register select (0 = Command, 1 = Data)
#define set_rs_low cbi _SFR_IO_ADDR(HW_LCD_RS_PORT), HW_LCD_RS_PIN
#define set_rs_high sbi _SFR_IO_ADDR(HW_LCD_RS_PORT), HW_LCD_RS_PIN
; Serial data input (SI)
#define set_b0_low cbi _SFR_IO_ADDR(HW_LCD_B0_PORT), HW_LCD_B0_PIN
#define set_b0_high sbi _SFR_IO_ADDR(HW_LCD_B0_PORT), HW_LCD_B0_PIN
;----------------------------------------------------------------------
;
; "_lcd_hw_write"
;
; preg_1 (r24) = flags
; preg_2 (r22) = data
;
; Write one byte (Cmd or Data) to ST7565 controller. In assembler for
; Performance reasons.
;----------------------------------------------------------------------
.global _lcd_hw_write
.func _lcd_hw_write
.extern wait1us
_lcd_hw_write:
; Set RS (0=Cmd, 1=Data)
sbrc preg_1, 0
set_rs_high
sbrs preg_1, 0
set_rs_low
_bit_loop:
; Send bit-7
set_en_low
sbrc preg_2, 7
set_b0_high
sbrs preg_2, 7
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-6
set_en_low
sbrc preg_2, 6
set_b0_high
sbrs preg_2, 6
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-5
set_en_low
sbrc preg_2, 5
set_b0_high
sbrs preg_2, 5
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-4
set_en_low
sbrc preg_2, 4
set_b0_high
sbrs preg_2, 4
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-3
set_en_low
sbrc preg_2, 3
set_b0_high
sbrs preg_2, 3
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-2
set_en_low
sbrc preg_2, 2
set_b0_high
sbrs preg_2, 2
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-1
set_en_low
sbrc preg_2, 1
set_b0_high
sbrs preg_2, 1
set_b0_low
set_en_high ; force data read from LCD controller
; Send bit-0
set_en_low
sbrc preg_2, 0
set_b0_high
sbrs preg_2, 0
set_b0_low
set_en_high ; force data read from LCD controller
_lcd_hw_write_exit:
ret
.endfunc
|
akshaybaweja/component-tester-oled
| 2,937
|
Source Code/sleep_5ms.S
|
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
#include <avr/io.h>
#include <avr/common.h>
#include "config.h"
#include <stdlib.h>
#define RCALL rcall
.GLOBAL sleep_5ms
.func sleep_5ms
.extern wait5ms
.section .text
#define DELAY_10ms (((F_CPU_HZ / 100) - RESTART_DELAY_TICS) / TICS_PER_T2_COUNT)
#define DELAY_5ms (((F_CPU_HZ / 200) - RESTART_DELAY_TICS) / TICS_PER_T2_COUNT)
;/* set the processor to sleep state */
;/* wake up will be done with compare match interrupt of counter 2 */
; void sleep_5ms(uint8_t spause){
sleep_5ms:
ldi r25, 0x00 ; pause = spause;
cpi r24, 201
brcs wloop ; if (spause > 200)
;// spause = 202 = 2s
;// spause = 203 = 3s
;// spause = 204 = 4s
;// spause = 205 = 5s
subi r24, 0xC8 ; 200 pause = (spause-200) * 200;
ldi r20, 0xC8 ; 200
mul r24, r20 ; (spause-200) * 200
movw r24, r0 ; r24:25 = (spause-200) * 200
eor r1, r1
wloop:
sbiw r24, 0x00 ; 0 while (pause > 0)
brne check_remain
; sts TIMSK2, r1 ; TIMSK2 = (0<<OCIE2B) | (0<<OCIE2A) | (0<<TOIE2); /* disable output compare match A interrupt */
;#endif
ret
check_remain:
#if (F_CPU_HZ / 400) > RESTART_DELAY_TICS
lds r18, TCCR1B ; if (TCCR1B & ((1<<CS12)|(1<<CS11)|(1<<CS10)) != 0)
andi r18, ((1<<CS12)|(1<<CS11)|(1<<CS10)) ;
breq do_sleep
; timer 1 is running, don't use sleep
RCALL wait5ms ; wait5ms();
sbiw r24, 1 ; pause -= 1;
rjmp wloop
do_sleep:
cpi r24, 0x01 ; 1
cpc r25, r1
breq only_one ; if (pause > 1)
sbiw r24, 0x02 ; pause -= 2;
; // Startup time is too long with 1MHz Clock!!!!
ldi r19, DELAY_10ms ; /* set to 10ms above the actual counter */
rjmp set_cntr
only_one:
ldi r19, DELAY_5ms ; /* set to 5ms above the actual counter */
ldi r24, 0x00 ; pause = 0;
ldi r25, 0x00 ; 0
set_cntr:
lds r18, TCNT2
add r18, r19 ; + t2_offset
sts OCR2A, r18 ; OCR2A = TCNT2 + t2_offset; /* set the compare value */
ldi r20, ((0<<OCIE2B) | (1<<OCIE2A) | (0<<TOIE2)); /* enable output compare match A interrupt */
sts TIMSK2, r20 ; TIMSK2 = (0<<OCIE2B) | (1<<OCIE2A) | (0<<TOIE2); /* enable output compare match A interrupt */
;; ldi r18, (1 << SM1) | (1 << SM0) | (0 << SE); set_sleep_mode(SLEEP_MODE_PWR_SAVE)
;; out _SFR_IO_ADDR(SMCR), r18; /* SMCR = (1 <<SM1) | (1 << SM0) | (0 << SE); */
ldi r18, (1 << SM1) | (1 << SM0) | (1 << SE);
out _SFR_IO_ADDR(SMCR), r18; /* SMCR = (1 <<SM1) | (1 << SM0) | (1 << SE); */
sleep ;
; // wake up after output compare match interrupt
ldi r18, (1 << SM1) | (1 << SM0) | (0 << SE);
out _SFR_IO_ADDR(SMCR), r18; /* SMCR = (1 << SM0) | (0 << SE); */
sts TIMSK2, r1 ; TIMSK2 = (0<<OCIE2B) | (0<<OCIE2A) | (0<<TOIE2); /* disable output compare match A interrupt */
wdr ; wdt_reset();
#else
; // restart delay ist too long, use normal delay of 5ms
RCALL wait5ms ; wait5ms(); // wait5ms includes wdt_reset()
sbiw r24, 1 ; pause -= 1;
#endif
rjmp wloop
.endfunc
|
aksudya/nachos
| 3,808
|
threads/switch-old.s
|
/* switch.s
* Machine dependent context switch routines. DO NOT MODIFY THESE!
*
* Context switching is inherently machine dependent, since
* the registers to be saved, how to set up an initial
* call frame, etc, are all specific to a processor architecture.
*
* This file currently supports the following architectures:
* DEC MIPS
* SUN SPARC
* HP PA-RISC
* Intel 386
*
* We define two routines for each architecture:
*
* ThreadRoot(InitialPC, InitialArg, WhenDonePC, StartupPC)
* InitialPC - The program counter of the procedure to run
* in this thread.
* InitialArg - The single argument to the thread.
* WhenDonePC - The routine to call when the thread returns.
* StartupPC - Routine to call when the thread is started.
*
* ThreadRoot is called from the SWITCH() routine to start
* a thread for the first time.
*
* SWITCH(oldThread, newThread)
* oldThread - The current thread that was running, where the
* CPU register state is to be saved.
* newThread - The new thread to be run, where the CPU register
* state is to be loaded from.
*/
/*
Copyright (c) 1992-1993 The Regents of the University of California.
All rights reserved. See copyright.h for copyright notice and limitation
of liability and disclaimer of warranty provisions.
*/
#include "copyright.h"
#include "switch.h"
.text
.align 2
.globl ThreadRoot
/* void ThreadRoot( void )
**
** expects the following registers to be initialized:
** eax points to startup function (interrupt enable)
** edx contains inital argument to thread function
** esi points to thread function
** edi point to Thread::Finish()
*/
ThreadRoot:
pushl %ebp
movl %esp,%ebp
pushl InitialArg
call *StartupPC
call *InitialPC
call *WhenDonePC
# NOT REACHED
movl %ebp,%esp
popl %ebp
ret
/* void SWITCH( thread *t1, thread *t2 )
**
** on entry, stack looks like this:
** 8(esp) -> thread *t2
** 4(esp) -> thread *t1
** (esp) -> return address
**
** we push the current eax on the stack so that we can use it as
** a pointer to t1, this decrements esp by 4, so when we use it
** to reference stuff on the stack, we add 4 to the offset.
*/
.comm _eax_save,4
.globl SWITCH
SWITCH:
movl %eax,_eax_save # save the value of eax
movl 4(%esp),%eax # move pointer to t1 into eax
movl %ebx,_EBX(%eax) # save registers
movl %ecx,_ECX(%eax)
movl %edx,_EDX(%eax)
movl %esi,_ESI(%eax)
movl %edi,_EDI(%eax)
movl %ebp,_EBP(%eax)
movl %esp,_ESP(%eax) # save stack pointer
movl _eax_save,%ebx # get the saved value of eax
movl %ebx,_EAX(%eax) # store it
movl 0(%esp),%ebx # get return address from stack into ebx
movl %ebx,_PC(%eax) # save it into the pc storage
movl 8(%esp),%eax # move pointer to t2 into eax
movl _EAX(%eax),%ebx # get new value for eax into ebx
movl %ebx,_eax_save # save it
movl _EBX(%eax),%ebx # retore old registers
movl _ECX(%eax),%ecx
movl _EDX(%eax),%edx
movl _ESI(%eax),%esi
movl _EDI(%eax),%edi
movl _EBP(%eax),%ebp
movl _ESP(%eax),%esp # restore stack pointer
movl _PC(%eax),%eax # restore return address into eax
movl %eax,4(%esp) # copy over the ret address on the stack
movl _eax_save,%eax
ret
|
aksudya/nachos
| 9,083
|
threads/switch.s
|
/* switch.s
* Machine dependent context switch routines. DO NOT MODIFY THESE!
*
* Context switching is inherently machine dependent, since
* the registers to be saved, how to set up an initial
* call frame, etc, are all specific to a processor architecture.
*
* This file currently supports the following architectures:
* DEC MIPS
* SUN SPARC
* HP PA-RISC
* Intel 386
*
* We define two routines for each architecture:
*
* ThreadRoot(InitialPC, InitialArg, WhenDonePC, StartupPC)
* InitialPC - The program counter of the procedure to run
* in this thread.
* InitialArg - The single argument to the thread.
* WhenDonePC - The routine to call when the thread returns.
* StartupPC - Routine to call when the thread is started.
*
* ThreadRoot is called from the SWITCH() routine to start
* a thread for the first time.
*
* SWITCH(oldThread, newThread)
* oldThread - The current thread that was running, where the
* CPU register state is to be saved.
* newThread - The new thread to be run, where the CPU register
* state is to be loaded from.
*/
/*
Copyright (c) 1992-1993 The Regents of the University of California.
All rights reserved. See copyright.h for copyright notice and limitation
of liability and disclaimer of warranty provisions.
*/
#include "copyright.h"
#include "switch.h"
#ifdef HOST_MIPS
/* Symbolic register names */
#define z $0 /* zero register */
#define a0 $4 /* argument registers */
#define a1 $5
#define s0 $16 /* callee saved */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define sp $29 /* stack pointer */
#define fp $30 /* frame pointer */
#define ra $31 /* return address */
.text
.align 2
.globl ThreadRoot
.ent ThreadRoot,0
ThreadRoot:
or fp,z,z # Clearing the frame pointer here
# makes gdb backtraces of thread stacks
# end here (I hope!)
jal StartupPC # call startup procedure
move a0, InitialArg
jal InitialPC # call main procedure
jal WhenDonePC # when were done, call clean up procedure
# NEVER REACHED
.end ThreadRoot
# a0 -- pointer to old Thread
# a1 -- pointer to new Thread
.globl SWITCH
.ent SWITCH,0
SWITCH:
sw sp, SP(a0) # save new stack pointer
sw s0, S0(a0) # save all the callee-save registers
sw s1, S1(a0)
sw s2, S2(a0)
sw s3, S3(a0)
sw s4, S4(a0)
sw s5, S5(a0)
sw s6, S6(a0)
sw s7, S7(a0)
sw fp, FP(a0) # save frame pointer
sw ra, PC(a0) # save return address
lw sp, SP(a1) # load the new stack pointer
lw s0, S0(a1) # load the callee-save registers
lw s1, S1(a1)
lw s2, S2(a1)
lw s3, S3(a1)
lw s4, S4(a1)
lw s5, S5(a1)
lw s6, S6(a1)
lw s7, S7(a1)
lw fp, FP(a1)
lw ra, PC(a1) # load the return address
j ra
.end SWITCH
#endif // HOST_MIPS
#ifdef HOST_SPARC
/* NOTE! These files appear not to exist on Solaris --
* you need to find where (the SPARC-specific) MINFRAME, ST_FLUSH_WINDOWS, ...
* are defined. (I don't have a Solaris machine, so I have no way to tell.)
*/
/* From sys/trap.h and sys/asm_linkage.h */
#include <sys/trap.h>
#define _ASM
#include <sys/stack.h>
.seg "text"
/* SPECIAL to the SPARC:
* The first two instruction of ThreadRoot are skipped because
* the address of ThreadRoot is made the return address of SWITCH()
* by the routine Thread::StackAllocate. SWITCH() jumps here on the
* "ret" instruction which is really at "jmp %o7+8". The 8 skips the
* two nops at the beginning of the routine.
*/
.globl ThreadRoot
ThreadRoot:
nop ; nop /* These 2 nops are skipped because we are called
* with a jmp+8 instruction. */
clr %fp /* Clearing the frame pointer makes gdb backtraces
* of thread stacks end here. */
/* Currently the arguments are in out registers we
* save them into local registers so they won't be
* trashed during the calls we make. */
mov InitialPC, %l0
mov InitialArg, %l1
mov WhenDonePC, %l2
/* Execute the code:
* call StartupPC();
* call InitialPC(InitialArg);
* call WhenDonePC();
*/
call StartupPC,0
nop
call %l0, 1
mov %l1, %o0 /* Using delay slot to setup argument to InitialPC */
call %l2, 0
nop
/* WhenDonePC call should never return. If it does
* we execute a trap into the debugger. */
ta ST_BREAKPOINT
.globl SWITCH
SWITCH:
save %sp, -SA(MINFRAME), %sp
st %fp, [%i0]
st %i0, [%i0+I0]
st %i1, [%i0+I1]
st %i2, [%i0+I2]
st %i3, [%i0+I3]
st %i4, [%i0+I4]
st %i5, [%i0+I5]
st %i7, [%i0+I7]
ta ST_FLUSH_WINDOWS
nop
mov %i1, %l0
ld [%l0+I0], %i0
ld [%l0+I1], %i1
ld [%l0+I2], %i2
ld [%l0+I3], %i3
ld [%l0+I4], %i4
ld [%l0+I5], %i5
ld [%l0+I7], %i7
ld [%l0], %i6
ret
restore
#endif // HOST_SPARC
#ifdef HOST_SNAKE
;rp = r2, sp = r30
;arg0 = r26, arg1 = r25, arg2 = r24, arg3 = r23
.SPACE $TEXT$
.SUBSPA $CODE$
ThreadRoot
.PROC
.CALLINFO CALLER,FRAME=0
.ENTRY
.CALL
ble 0(%r6) ;call StartupPC
or %r31, 0, %rp ;put return address in proper register
or %r4, 0, %arg0 ;load InitialArg
.CALL ;in=26
ble 0(%r3) ;call InitialPC
or %r31, 0, %rp ;put return address in proper register
.CALL
ble 0(%r5) ;call WhenDonePC
.EXIT
or %r31, 0, %rp ;shouldn't really matter - doesn't return
.PROCEND
SWITCH
.PROC
.CALLINFO CALLER,FRAME=0
.ENTRY
; save process state of oldThread
stw %sp, SP(%arg0) ;save stack pointer
stw %r3, S0(%arg0) ;save callee-save registers
stw %r4, S1(%arg0)
stw %r5, S2(%arg0)
stw %r6, S3(%arg0)
stw %r7, S4(%arg0)
stw %r8, S5(%arg0)
stw %r9, S6(%arg0)
stw %r10, S7(%arg0)
stw %r11, S8(%arg0)
stw %r12, S9(%arg0)
stw %r13, S10(%arg0)
stw %r14, S11(%arg0)
stw %r15, S12(%arg0)
stw %r16, S13(%arg0)
stw %r17, S14(%arg0)
stw %r18, S15(%arg0)
stw %rp, PC(%arg0) ;save program counter
; restore process state of nextThread
ldw SP(%arg1), %sp ;restore stack pointer
ldw S0(%arg1), %r3 ;restore callee-save registers
ldw S1(%arg1), %r4
ldw S2(%arg1), %r5
ldw S3(%arg1), %r6
ldw S4(%arg1), %r7
ldw S5(%arg1), %r8
ldw S6(%arg1), %r9
ldw S7(%arg1), %r10
ldw S8(%arg1), %r11
ldw S9(%arg1), %r12
ldw S10(%arg1), %r13
ldw S11(%arg1), %r14
ldw S12(%arg1), %r15
ldw S13(%arg1), %r16
ldw S14(%arg1), %r17
ldw PC(%arg1), %rp ;save program counter
bv 0(%rp)
.EXIT
ldw S15(%arg1), %r18
.PROCEND
.EXPORT SWITCH,ENTRY,PRIV_LEV=3,RTNVAL=GR
.EXPORT ThreadRoot,ENTRY,PRIV_LEV=3,RTNVAL=GR
#endif
#ifdef HOST_i386
.text
.align 2
.globl ThreadRoot
/* void ThreadRoot( void )
**
** expects the following registers to be initialized:
** eax points to startup function (interrupt enable)
** edx contains inital argument to thread function
** esi points to thread function
** edi point to Thread::Finish()
*/
ThreadRoot:
pushl %ebp
movl %esp,%ebp
pushl InitialArg
call *StartupPC
call *InitialPC
call *WhenDonePC
// NOT REACHED
movl %ebp,%esp
popl %ebp
ret
/* void SWITCH( thread *t1, thread *t2 )
**
** on entry, stack looks like this:
** 8(esp) -> thread *t2
** 4(esp) -> thread *t1
** (esp) -> return address
**
** we push the current eax on the stack so that we can use it as
** a pointer to t1, this decrements esp by 4, so when we use it
** to reference stuff on the stack, we add 4 to the offset.
*/
.comm _eax_save,4
.globl SWITCH
SWITCH:
movl %eax,_eax_save # save the value of eax
movl 4(%esp),%eax # move pointer to t1 into eax
movl %ebx,_EBX(%eax) # save registers
movl %ecx,_ECX(%eax)
movl %edx,_EDX(%eax)
movl %esi,_ESI(%eax)
movl %edi,_EDI(%eax)
movl %ebp,_EBP(%eax)
movl %esp,_ESP(%eax) # save stack pointer
movl _eax_save,%ebx # get the saved value of eax
movl %ebx,_EAX(%eax) # store it
movl 0(%esp),%ebx # get return address from stack into ebx
movl %ebx,_PC(%eax) # save it into the pc storage
movl 8(%esp),%eax # move pointer to t2 into eax
movl _EAX(%eax),%ebx # get new value for eax into ebx
movl %ebx,_eax_save # save it
movl _EBX(%eax),%ebx # retore old registers
movl _ECX(%eax),%ecx
movl _EDX(%eax),%edx
movl _ESI(%eax),%esi
movl _EDI(%eax),%edi
movl _EBP(%eax),%ebp
movl _ESP(%eax),%esp # restore stack pointer
movl _PC(%eax),%eax # restore return address into eax
movl %eax,4(%esp) # copy over the ret address on the stack
movl _eax_save,%eax
ret
#endif
|
aksudya/nachos
| 2,373
|
test/start.s
|
/* Start.s
* Assembly language assist for user programs running on top of Nachos.
*
* Since we don't want to pull in the entire C library, we define
* what we need for a user program here, namely Start and the system
* calls.
*/
#define IN_ASM
#include "syscall.h"
.text
.align 2
/* -------------------------------------------------------------
* __start
* Initialize running a C program, by calling "main".
*
* NOTE: This has to be first, so that it gets loaded at location 0.
* The Nachos kernel always starts a program by jumping to location 0.
* -------------------------------------------------------------
*/
.globl __start
.ent __start
__start:
jal main
move $4,$0
jal Exit /* if we return from main, exit(0) */
.end __start
/* -------------------------------------------------------------
* System call stubs:
* Assembly language assist to make system calls to the Nachos kernel.
* There is one stub per system call, that places the code for the
* system call into register r2, and leaves the arguments to the
* system call alone (in other words, arg1 is in r4, arg2 is
* in r5, arg3 is in r6, arg4 is in r7)
*
* The return value is in r2. This follows the standard C calling
* convention on the MIPS.
* -------------------------------------------------------------
*/
.globl Halt
.ent Halt
Halt:
addiu $2,$0,SC_Halt
syscall
j $31
.end Halt
.globl Exit
.ent Exit
Exit:
addiu $2,$0,SC_Exit
syscall
j $31
.end Exit
.globl Exec
.ent Exec
Exec:
addiu $2,$0,SC_Exec
syscall
j $31
.end Exec
.globl Join
.ent Join
Join:
addiu $2,$0,SC_Join
syscall
j $31
.end Join
.globl Create
.ent Create
Create:
addiu $2,$0,SC_Create
syscall
j $31
.end Create
.globl Open
.ent Open
Open:
addiu $2,$0,SC_Open
syscall
j $31
.end Open
.globl Read
.ent Read
Read:
addiu $2,$0,SC_Read
syscall
j $31
.end Read
.globl Write
.ent Write
Write:
addiu $2,$0,SC_Write
syscall
j $31
.end Write
.globl Close
.ent Close
Close:
addiu $2,$0,SC_Close
syscall
j $31
.end Close
.globl Fork
.ent Fork
Fork:
addiu $2,$0,SC_Fork
syscall
j $31
.end Fork
.globl Yield
.ent Yield
Yield:
addiu $2,$0,SC_Yield
syscall
j $31
.end Yield
/* dummy function to keep gcc happy */
.globl __main
.ent __main
__main:
j $31
.end __main
|
al3xtjames/Clover
| 16,046
|
BootHFS/boot1x.s
|
;
; Copyright (c) 2014-2015 Zenith432 All rights reserved.
;
; Partition Boot Loader: boot1x
; This version of boot1x tries to find a stage2 boot file in the root folder.
;
; Credits:
; Portions based on boot1f32.
; Thanks to Robert Shullich for
; "Reverse Engineering the Microsoft exFAT File System" dated Dec 1, 2009.
; T13 Commitee document EDD-4 for information about BIOS int 0x13.
;
; This program is designed to reside in blocks 0 - 1 of an exFAT partition.
; It expects that the MBR has left the drive number in DL.
;
; This version requires a BIOS with EBIOS (LBA) support.
;
; This code is written for the NASM assembler.
; nasm -f bin -o boot1x boot1x.s
;
; Written by zenith432 during November 2014.
; Modified by zenith432 January 2015
; Added Feature: Support digit keypress with two second delay (-DSELECTION_FEATURE)
;
bits 16
%define VERBOSE 1
%define USESIDL 1
%define USEBP 1
kMaxBlockCount equ 127 ; Max block count supported by Int 0x13, function 0x42, old school
kBootBlockBytes equ 512 ; Bytes in a exFAT Boot block
kBootSignature equ 0xaa55 ; Boot block signature
kBoot1StackAddress equ 0xfff0 ; Address of top-of-stack 0:0xfff0
kBoot1LoadAddr equ 0x7c00 ; Address of loaded boot block 0:0x7c00
kBoot2Segment equ 0x2000 ; Address for boot2 0x2000:0x200
kBoot2Address equ 512
kFATBuf equ 0x6c00 ; Address for FAT block buffer 0:0x6c00 (4K space)
kRootDirBuf equ 0x5c00 ; Address for Root Directory block buffer 0:0x5c00 (4K space)
kMaxCluster equ 0xfffffff7 ; exFAT max cluster value + 1 (for FAT32 it's 0x0ffffff8)
kMaxContigClusters equ 1024 ; Max contiguous clusters returned by getRange
kBootNameHash equ 0xdc36 ; exFAT name hash for 'BOOT' (in UTF16LE)
kBoot2MaxBytes equ (512 * 1024 - 512) ; must fit between 0x20200 and 0xa0000
struc PartitionEntry ; MBR partition entry (truncated)
times 8 resb 1
.lba: resd 1 ; starting lba
endstruc
struc BootParams ; BOOT file parameters
.cluster: resd 1 ; 1st cluster of BOOT
.size: resd 1 ; size of BOOT in bytes
resw 1
.flag: resb 1
endstruc
struc DirIterator ; exFAT Directory Iterator
.entries_end: resb 1 ; beyond last 32-byte entry (possible values 16, 32, 64, 128)
.cluster: resd 1 ; current cluster
.lba_high: resd 1 ; upper 32 bits of lba
.lba_end: resd 1 ; beyond last block (lower 32-bits)
.lba: resd 1 ; current block
.entry: resb 1 ; current 32-byte entry
endstruc
struc FATCache ; Manages cache state for FAT blocks
.shift: resb 1 ; right shift for converting cluster # to FAT block address
.mask: resw 1 ; bit mask for finding cluster # in FAT block
.lba: resd 1 ; lba # cached in FAT block buffer (note that FAT block address is limited to 32 bits)
endstruc
%ifdef USEBP
%define BPR bp - gPartitionOffset +
%else
%define BPR
%endif
section .text
org kBoot1LoadAddr
jmp start
times (3 - $ + $$) nop
gOEMName: times 8 db 0 ; 'EXFAT '
;
; Scratch Area
; Used for data structures
;
times (64 - BootParams_size - DirIterator_size - FATCache_size - $ + $$) db 0
gsParams: times BootParams_size db 0
gsIterator: times DirIterator_size db 0
gsFATCache: times FATCache_size db 0
;
; exFAT BPB
;
gPartitionOffset: dd 0, 0
gVolumeLength: dd 0, 0
gFATOffset: dd 0
gFATLength: dd 0
gClusterHeapOffset: dd 0
gClusterCount: dd 0
gRootDirectory1stCluster: dd 0
gVolumeSerialNubmer: dd 0
gFileSystemRevision: dw 0 ; 0x100
gVolumeFlags: dw 0
gBytesPerBlock: db 0 ; range 9 - 12 (power of 2)
gBlocksPerCluster: db 0 ; gBytesPerBlock + gBlocksPerCluster <= 25 (power of 2)
gNumberOfFATs: db 0 ; should be 1
gDriveSelect: db 0 ; probably 0x80
gPercentInUse: db 0
times 7 db 0
start:
cli
xor eax, eax
mov ss, ax
mov sp, kBoot1StackAddress
sti
mov ds, ax
mov es, ax
;
; Initializing global variables.
;
%ifdef USEBP
mov bp, gPartitionOffset
%endif
%ifdef USESIDL
;
; Shouldn't be necessary to use DS:SI because
; 1) Existing gPartitionOffset must be correct in
; order for filesystem to work well when mounted.
; 2) LBA may be 64 bits if booted from GPT.
; 3) Not all MBR boot records pass DS:SI
; pointing to MBR partition entry.
;
%if 0
mov ecx, [si + PartitionEntry.lba]
mov [BPR gPartitionOffset + 4], eax
mov [BPR gPartitionOffset], ecx
%endif
;
; However, by convention BIOS passes boot
; drive number in dl, so use that instead
; of existing gDriveSelect
;
mov [BPR gDriveSelect], dl
%endif
;
; Initialize FAT Cache
;
dec eax
mov dword [BPR gsFATCache + FATCache.lba], eax ; alternatively store gFATLength here
mov cl, [BPR gBytesPerBlock]
sub cl, 2 ; range 7 - 10
mov [BPR gsFATCache + FATCache.shift], cl
neg ax
shl ax, cl
dec ax
mov [BPR gsFATCache + FATCache.mask], ax
;
; Initialize Iterator
;
mov al, 1
sub cl, 3 ; range 4 - 7
shl al, cl
mov [BPR gsIterator + DirIterator.entries_end], al
mov [BPR gsIterator + DirIterator.entry], al
xor eax, eax
mov ecx, [BPR gRootDirectory1stCluster]
mov [BPR gsIterator + DirIterator.lba_end], eax
mov [BPR gsIterator + DirIterator.lba], eax
mov [BPR gsIterator + DirIterator.cluster], ecx
%ifdef VERBOSE
mov di, init_str
call log_string
%endif
%ifdef SELECTION_FEATURE
call setBootFile
%endif
;
; Search root directory for BOOT
;
.loop:
call nextDirEntry
jc error
cld
lodsb
.revert:
test al, al ; end of root directory?
jz error
cmp al, 0x85 ; file/subdir entry?
jnz .loop
lodsb
cmp al, 2 ; 2ndary count should be 2
jb .loop
add si, 2 ; skip checksum
lodsb
test al, 0x10 ; file attributes - check not a directory
jnz .loop
call nextDirEntry
jc error
cld
lodsb
cmp al, 0xc0 ; stream extension entry?
jnz .revert
lodsb
mov dl, al ; General 2ndary flag
inc si
lodsb
.name_length_point:
cmp al, 4 ; name length
jnz .loop
lodsw ; name hash
.name_hash_point:
cmp ax, kBootNameHash
jnz .loop
add si, 2
mov eax, [si + 4] ; high 32 bits of valid data length
test eax, eax
jz .more
and dl, 0xfe ; if size too big, mark as no allocation
.more:
lodsd ; valid data length
mov [BPR gsParams + BootParams.size], eax
add si, 8
lodsd ; first cluster
mov [BPR gsParams + BootParams.cluster], eax
mov [BPR gsParams + BootParams.flag], dl
call nextDirEntry
jc error
cld
lodsb
cmp al, 0xc1
jnz .revert
inc si ; skip flags
lodsd ; unicode chars 1 - 2
or eax, 0x200020 ; tolower
cmp eax, 0x6f0062 ; 'bo' in UTF16LE
jnz .loop
lodsd ; unicode chars 3 - 4
or eax, 0x200020 ; tolower
cmp eax, 0x74006f ; 'ot' in UTF16LE
jnz .loop
;
; done - found boot file!
;
mov dl, [BPR gsParams + BootParams.flag]
test dl, 1 ; no allocation or length too big?
jz error
mov ebx, [BPR gsParams + BootParams.size]
cmp ebx, kBoot2MaxBytes + 1
jnb error
call BytesToBlocks ; convert size to blocks
; boot2 file size in blocks is in bx
load_boot2: ; anchor for localizing next labels
xor esi, esi ; no blocks after 1st range
test dl, 2 ; FAT Chain?
cmovnz edx, [BPR gsParams + BootParams.cluster] ; if not
jnz .oneshot ; load contiguous file
;
; load via FAT
;
mov si, bx ; total blocks to si
.loop:
mov eax, [BPR gsParams + BootParams.cluster]
mov edx, eax
call getRange
test ebx, ebx
jnz .nonempty
test si, si
jnz error
jmp boot2
.nonempty:
cmp ebx, esi
cmovnb bx, si
sub si, bx
mov [BPR gsParams + BootParams.cluster], eax
.oneshot:
call ClusterToLBA
mov ax, bx
mov ecx, edx
mov edx, (kBoot2Segment << 4) | kBoot2Address
call readBlocks
; TODO: error
test si, si
jnz .loop
; fall through to boot2
boot2:
mov dl, [BPR gDriveSelect] ; load BIOS drive number
jmp kBoot2Segment:kBoot2Address
error:
%ifdef VERBOSE
mov di, error_str
call log_string
%endif
hang:
hlt
jmp hang
;--------------------------------------------------------------------------
; ClusterToLBA - Converts cluster number to 64-bit LBA
;
; Arguments:
; EDX = cluster number
;
; Returns
; EDI:EDX = corresponding block address
;
; Assumes input cluster number is valid
;
ClusterToLBA:
push cx
xor edi, edi
sub edx, 2
mov cl, [BPR gBlocksPerCluster]
shld edi, edx, cl
shl edx, cl
add edx, [BPR gClusterHeapOffset]
adc edi, 0
pop cx
ret
;--------------------------------------------------------------------------
; BytesToBlocks - Converts byte size to blocks (rounding up to next block)
;
; Arguments:
; EBX = size in bytes
;
; Returns:
; EBX = size in blocks (rounded up)
;
; Clobbers eax, cl
;
BytesToBlocks:
xor eax, eax
inc ax
mov cl, [BPR gBytesPerBlock]
shl ax, cl
dec ax
add ebx, eax
shr ebx, cl
ret
times (kBootBlockBytes - 2 - $ + $$) nop
dw kBootSignature
block1_end:
;--------------------------------------------------------------------------
; nextDirEntry - Locates the next 32-byte entry in Root Directory,
; loading block if necessary.
;
; Returns:
; CF set if end of Root Directory
; CF clear, and DS:SI points to next entry if exists
;
; Clobbers eax, ebx, ecx, edx, edi
;
nextDirEntry:
movzx ax, [BPR gsIterator + DirIterator.entry]
cmp al, [BPR gsIterator + DirIterator.entries_end]
jb .addressentry
mov ecx, [BPR gsIterator + DirIterator.lba]
mov edi, [BPR gsIterator + DirIterator.lba_high]
cmp ecx, [BPR gsIterator + DirIterator.lba_end]
jnz .readblock
mov eax, [BPR gsIterator + DirIterator.cluster]
mov edx, eax
call getRange
test ebx, ebx
jnz .nonempty
stc
ret
.nonempty:
mov [BPR gsIterator + DirIterator.cluster], eax
call ClusterToLBA
mov ecx, edx
add edx, ebx
mov [BPR gsIterator + DirIterator.lba_high], edi
mov [BPR gsIterator + DirIterator.lba_end], edx
.readblock:
mov al, 1
%if 0
mov edx, kRootDirBuf
%else
xor edx, edx
mov dh, kRootDirBuf >> 8
%endif
call readLBA
; TODO error
inc ecx
jnz .skip
inc edi
mov [BPR gsIterator + DirIterator.lba_high], edi
.skip:
mov [BPR gsIterator + DirIterator.lba], ecx
xor ax, ax
.addressentry:
mov si, ax
inc al
mov [BPR gsIterator + DirIterator.entry], al
shl si, 5
add si, kRootDirBuf
clc
ret
;--------------------------------------------------------------------------
; getRange - Calculates contiguous range of clusters from FAT
;
; Arguments:
; EAX = start cluster
;
; Returns:
; EAX = next cluster after range
; EBX = number of contiguous blocks in range
;
; Range calculated is at most kMaxContigClusters clusters long
;
getRange:
push ecx
push edx
push edi
push si
xor edi, edi
%if 0
mov edx, kFATBuf
%else
mov edx, edi
mov dh, kFATBuf >> 8
%endif
mov ebx, edi
.loop:
cmp eax, 2
jb .finishup
cmp eax, -9 ;kMaxCluster
jnb .finishup
cmp bx, kMaxContigClusters
jnb .finishup
inc bx
mov si, ax
and si, [BPR gsFATCache + FATCache.mask]
shl si, 2
mov ecx, eax
inc ecx
push ecx
mov cl, [BPR gsFATCache + FATCache.shift]
shr eax, cl
cmp eax, [BPR gsFATCache + FATCache.lba]
jz .iscached
mov ecx, [BPR gFATOffset]
add ecx, eax
mov [BPR gsFATCache + FATCache.lba], eax
mov al, 1
call readLBA
; TODO: error?
.iscached:
pop ecx
mov eax, [kFATBuf + si]
cmp eax, ecx
jz .loop
.finishup:
mov cl, [BPR gBlocksPerCluster]
shl ebx, cl
pop si
pop edi
pop edx
pop ecx
ret
%ifdef SELECTION_FEATURE
;--------------------------------------------------------------------------
; setBootFile - Waits two seconds for a keypress.
; If keypress is digit '0' - '9' alters boot file from /boot to /boot<digit>
; If keypress anything else or no keypress - uses /boot.
;
; Arguments:
; None
;
; Returns:
; None
;
; Clobbers ax, cx, dx
;
setBootFile:
mov cx, 2000 ; loop counter = max 2000 miliseconds in total
.loop:
mov ah, 1 ; int 0x16, Func 0x01 - get keyboard status/preview key
int 0x16
jnz .keypress ; got keypress
; wait for 1 ms: int 0x15, Func 0x86 (wait for cx:dx microseconds)
push cx ; save loop counter
xor cx, cx
mov dx, 1000
mov ah, 0x86
int 0x15
pop cx ; restore loop counter
loop .loop
.done:
ret
.keypress:
xor ah, ah ; read the char from buffer to spend it
int 0x16
; have a key - ASCII is in al
cmp al, '0'
jb .done
cmp al, '9' + 1
jae .done
;
; Alter code so name length tested is 5 instead of 4
; Compute new hash value with digit and alter code
; to check for modified hash value.
; Note: code continues to compare 4 characters 'boot'.
; For any other ascii character in 5th position,
; the hash value does not collide. There are
; non-ascii unicode characters in 5th position that
; collide with hash-value, but ignore those for simplicity.
;
xor ah, ah
inc byte [start.name_length_point + 1]
add ax, (kBootNameHash >> 1) | ((kBootNameHash & 1) << 15)
ror ax, 1
mov [start.name_hash_point + 1], ax
ret
%endif
;--------------------------------------------------------------------------
; readBlocks - Reads more than kMaxBlockCount blocks using LBA addressing.
;
; Arguments:
; AX = number of blocks to read (valid from 1-1280).
; EDX = pointer to where the blocks should be stored.
; EDI:ECX = block offset in partition (64 bits)
;
; Returns:
; CF = 0 success
; 1 error
;
readBlocks:
pushad
mov bx, ax
.loop:
xor eax, eax
mov al, kMaxBlockCount
cmp bx, ax
cmovb ax, bx
call readLBA
; TODO: error?
sub bx, ax
jz .exit
add ecx, eax
adc edi, 0
push cx
mov cl, [BPR gBytesPerBlock]
shl eax, cl
pop cx
add edx, eax
jmp .loop
.exit:
popad
ret
;--------------------------------------------------------------------------
; readLBA - Read blocks from a partition using LBA addressing.
;
; Arguments:
; AL = number of blocks to read (valid from 1-kMaxBlockCount).
; EDX = pointer to where the blocks should be stored.
; EDI:ECX = block offset in partition (64 bits)
; [gDriveSelect] = drive number (0x80 + unit number)
; [gPartitionOffset] = partition location on drive
;
; Returns:
; CF = 0 success
; 1 error
; Presently, jumps to error on BIOS-reported failure
;
readLBA:
pushad ; save all registers
push es ; save ES
mov bp, sp ; save current SP
;
; Adjust to 16 bit segment:offset address
; to allow for reading up to 64K
;
mov bl, dl
and bx, 0xf
shr edx, 4
mov es, dx
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
add ecx, [gPartitionOffset]
adc edi, [gPartitionOffset + 4]
push edi
push ecx
push es
push bx
xor ah, ah
push ax
push word 16
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; DL = drive number (0x80 + unit number)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov dl, [gDriveSelect] ; load BIOS drive number
mov si, sp
mov ah, 0x42
int 0x13
jc error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
; xor ax, ax ; Func 0
; int 0x13 ; INT 13
; stc ; set carry to indicate error
;.exit
mov sp, bp
pop es
popad
ret
%ifdef VERBOSE
;--------------------------------------------------------------------------
; Write a string with log_title_str prefix to the console.
;
; Arguments:
; DS:DI pointer to a NULL terminated string.
;
log_string:
pushad
push di
mov si, log_title_str
call print_string
pop si
call print_string
popad
ret
;-------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
.loop:
lodsb ; load a byte from DS:SI into AL
test al, al ; Is it a NULL?
jz .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp .loop
.exit:
ret
%endif ; VERBOSE
;--------------------------------------------------------------------------
; Static data.
;
%ifdef VERBOSE
log_title_str: db 13, 10, 'boot1x: ', 0
init_str: db 'init', 0
error_str: db 'error', 0
%endif
times (kBootBlockBytes - 4 - $ + block1_end) db 0
dw 0, kBootSignature
|
al3xtjames/Clover
| 25,441
|
BootHFS/boot0.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Boot Loader: boot0
;
; A small boot sector program written in x86 assembly whose only
; responsibility is to locate the active partition, load the
; partition booter into memory, and jump to the booter's entry point.
; It leaves the boot drive in DL and a pointer to the partition entry in SI.
;
; This boot loader must be placed in the Master Boot Record.
;
; In order to coexist with a fdisk partition table (64 bytes), and
; leave room for a two byte signature (0xAA55) in the end, boot0 is
; restricted to 446 bytes (512 - 64 - 2). If boot0 did not have to
; live in the MBR, then we would have 510 bytes to work with.
;
; boot0 is always loaded by the BIOS or another booter to 0:7C00h.
;
; This code is written for the NASM assembler.
; nasm boot0.s -o boot0
;
; This version of boot0 implements hybrid GUID/MBR partition scheme support
;
; Written by Tamás Kosárszky on 2008-03-10 and JrCs on 2013-05-08.
;
; Turbo added EFI System Partition boot support
;
; Added KillerJK's switchPass2 modifications
;
; JrCs added FAT32/exFAT System Partition boot support on GPT pure partition scheme
;
;
; boot0af and boot0ss share the same code except.
; The ACTIVEFIRST macro is used to select the right code
; boot0af - define ACTIVEFIRST
; boot0ss - do not define ACTIVEFIRST
;
;
; Set to 1 to enable obscure debug messages.
;
DEBUG EQU 0
;
; Set to 1 to enable verbose mode
;
VERBOSE EQU 0
;
; Various constants.
;
kBoot0Segment EQU 0x0000
kBoot0Stack EQU 0xFFF0 ; boot0 stack pointer
kBoot0LoadAddr EQU 0x7C00 ; boot0 load address
kBoot0RelocAddr EQU 0xE000 ; boot0 relocated address
kMBRBuffer EQU 0x1000 ; MBR buffer address
kLBA1Buffer EQU 0x1200 ; LBA1 - GPT Partition Table Header buffer address
kGPTABuffer EQU 0x1400 ; GUID Partition Entry Array buffer address
kPartTableOffset EQU 0x1be
kMBRPartTable EQU kMBRBuffer + kPartTableOffset
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kHFSPSignature EQU 'H+' ; HFS+ volume signature
kHFSPCaseSignature EQU 'HX' ; HFS+ volume case-sensitive signature
kEXFATSignature EQU 'EX' ; exFAT volume signature
kFAT32BootCodeOffset EQU 0x5a ; offset of boot code in FAT32 boot sector
kBoot1FAT32Magic EQU 'BO' ; Magic string to detect our boot1f32 code
kGPTSignatureLow EQU 'EFI ' ; GUID Partition Table Header Signature
kGPTSignatureHigh EQU 'PART'
kGUIDLastDwordOffs EQU 12 ; last 4 byte offset of a GUID
kPartCount EQU 4 ; number of paritions per table
kPartTypeEXFAT EQU 0x07 ; exFAT Filesystem type
kPartTypeFAT32 EQU 0x0c ; FAT32 Filesystem type
kPartTypeHFS EQU 0xaf ; HFS+ Filesystem type
kPartTypePMBR EQU 0xee ; On all GUID Partition Table disks a Protective MBR (PMBR)
; in LBA 0 (that is, the first block) precedes the
; GUID Partition Table Header to maintain compatibility
; with existing tools that do not understand GPT partition structures.
; The Protective MBR has the same format as a legacy MBR
; and contains one partition entry with an OSType set to 0xEE
; reserving the entire space used on the disk by the GPT partitions,
; including all headers.
kPartActive EQU 0x80 ; active flag enabled
kPartInactive EQU 0x00 ; active flag disabled
kAppleGUID EQU 0xACEC4365 ; last 4 bytes of Apple type GUIDs.
kEFISystemGUID EQU 0x3BC93EC9 ; last 4 bytes of EFI System Partition Type GUID:
; C12A7328-F81F-11D2-BA4B-00A0C93EC93B
kBasicDataGUID EQU 0xC79926B7 ; last 4 bytes of Basic Data System Partition Type GUID:
; EBD0A0A2-B9E5-4433-87C0-68B6B72699C7
%ifdef FLOPPY
kDriveNumber EQU 0x00
%else
kDriveNumber EQU 0x80
%endif
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
;
; Format of GPT Partition Table Header
;
struc gpth
.Signature resb 8
.Revision resb 4
.HeaderSize resb 4
.HeaderCRC32 resb 4
.Reserved resb 4
.MyLBA resb 8
.AlternateLBA resb 8
.FirstUsableLBA resb 8
.LastUsableLBA resb 8
.DiskGUID resb 16
.PartitionEntryLBA resb 8
.NumberOfPartitionEntries resb 4
.SizeOfPartitionEntry resb 4
.PartitionEntryArrayCRC32 resb 4
endstruc
;
; Format of GUID Partition Entry Array
;
struc gpta
.PartitionTypeGUID resb 16
.UniquePartitionGUID resb 16
.StartingLBA resb 8
.EndingLBA resb 8
.Attributes resb 8
.PartitionName resb 72
endstruc
;
; Macros.
;
%macro DebugCharMacro 1
mov al, %1
call print_char
%endmacro
%macro LogString 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%else
%define DebugChar(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot0RelocAddr
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; Set up the stack to grow down from kBoot0Segment:kBoot0Stack.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor ax, ax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot0Stack ; sp <- top of stack
sti ; reenable interrupts
mov es, ax ; es <- 0
mov ds, ax ; ds <- 0
;
; Relocate boot0 code.
;
mov si, kBoot0LoadAddr ; si <- source
mov di, kBoot0RelocAddr ; di <- destination
cld ; auto-increment SI and/or DI registers
mov cx, kSectorBytes/2 ; copy 256 words
repnz movsw ; repeat string move (word) operation
;
; Code relocated, jump to start_reloc in relocated location.
;
jmp kBoot0Segment:start_reloc
;--------------------------------------------------------------------------
; Start execution from the relocated location.
;
start_reloc:
DebugChar('>')
%if DEBUG
mov al, dl
call print_hex
%endif
;
; Since this code may not always reside in the MBR, always start by
; loading the MBR to kMBRBuffer and LBA1 to kGPTBuffer.
;
xor eax, eax
mov [my_lba], eax ; store LBA sector 0 for read_lba function
mov al, 2 ; load two sectors: MBR and LBA1
mov bx, kMBRBuffer ; MBR load address
call load
jc error ; MBR load error
;
; Look for the booter partition in the MBR partition table,
; which is at offset kMBRPartTable.
;
mov si, kMBRPartTable ; pointer to partition table
call find_boot ; will not return on success
error:
LogString(boot_error_str)
hang:
hlt
jmp hang
;--------------------------------------------------------------------------
; Find the active (boot) partition and load the booter from the partition.
;
; Arguments:
; DL = drive number (0x80 + unit number)
; SI = pointer to fdisk partition table.
;
; Clobber list:
; EAX, BX, EBP
;
find_boot:
;
; Check for boot block signature 0xAA55 following the 4 partition
; entries.
;
cmp WORD [si + part_size * kPartCount], kBootSignature
jne .exit ; boot signature not found.
xor bx, bx ; BL will be set to 1 later in case of
; Protective MBR has been found
inc bh ; BH = 1. Giving a chance for a second pass
; to boot an inactive but boot1h aware HFS+ partition
; by scanning the MBR partition entries again.
.start_scan:
mov cx, kPartCount ; number of partition entries per table
.loop:
;
; First scan through the partition table looking for the active
; partition.
;
%if DEBUG
mov al, [si + part.type] ; print partition type
call print_hex
%endif
mov eax, [si + part.lba] ; save starting LBA of current
mov [my_lba], eax ; MBR partition entry for read_lba function
cmp BYTE [si + part.type], 0 ; unused partition?
je .continue ; skip to next entry
cmp BYTE [si + part.type], kPartTypePMBR ; check for Protective MBR
jne .testPass
mov BYTE [si + part.bootid], kPartInactive ; found Protective MBR
; clear active flag to make sure this protective
; partition won't be used as a bootable partition.
mov bl, 1 ; Assume we can deal with GPT but try to scan
; later if not found any other bootable partitions.
.testPass:
cmp bh, 1
jne .Pass2
.Pass1:
%ifdef ACTIVEFIRST
jmp SHORT .tryToBootIfActive
%else
jmp SHORT .tryToBootSupportedFS
%endif
.Pass2:
%ifdef ACTIVEFIRST
jmp SHORT .tryToBootSupportedFS
%endif
.tryToBootIfActive:
; We're going to try to boot a partition if it is active
cmp BYTE [si + part.bootid], kPartActive
jne .continue
xor dh, dh ; Argument for loadBootSector to skip file system signature check.
jmp SHORT .tryToBoot
.tryToBootSupportedFS:
; We're going to try to boot a partition with a supported filesystem
; equipped with boot1x in its boot record regardless if it's active or not.
mov dh, 1 ; Argument for loadBootSector to check file system signature.
cmp BYTE [si + part.type], kPartTypeHFS
je .tryToBoot
cmp BYTE [si + part.type], kPartTypeFAT32
je .tryToBoot
cmp BYTE [si + part.type], kPartTypeEXFAT
jne .continue
.tryToBoot:
;
; Found boot partition, read boot sector to memory.
;
call loadBootSector
jne .continue
jmp SHORT initBootLoader
.continue:
add si, BYTE part_size ; advance SI to next partition entry
loop .loop ; loop through all partition entries
;
; Scanned all partitions but not found any with active flag enabled
; Anyway if we found a protective MBR before we still have a chance
; for a possible GPT Header at LBA 1
;
dec bl
jnz .switchPass2 ; didn't find Protective MBR before
call checkGPT
.switchPass2:
;
; Switching to Pass 2
; try to find a boot1h aware HFS+ MBR partition
;
dec bh
mov si, kMBRPartTable ; set SI to first entry of MBR Partition table
jz .start_scan ; scan again
.exit:
ret ; Giving up.
;
; Jump to partition booter. The drive number is already in register DL.
; SI is pointing to the modified partition entry.
;
initBootLoader:
DebugChar('J')
%if VERBOSE
LogString(done_str)
%endif
jmp kBoot0LoadAddr
;
; Found Protective MBR Partition Type: 0xEE
; Check for 'EFI PART' string at the beginning
; of LBA1 for possible GPT Table Header
;
checkGPT:
push bx
mov di, kLBA1Buffer ; address of GUID Partition Table Header
cmp DWORD [di], kGPTSignatureLow ; looking for 'EFI '
jne .exit ; not found. Giving up.
cmp DWORD [di + 4], kGPTSignatureHigh ; looking for 'PART'
jne .exit ; not found. Giving up indeed.
mov si, di
;
; Loading GUID Partition Table Array
;
mov eax, [si + gpth.PartitionEntryLBA] ; starting LBA of GPT Array
mov [my_lba], eax ; save starting LBA for read_lba function
mov cx, [si + gpth.NumberOfPartitionEntries] ; number of GUID Partition Array entries
mov bx, [si + gpth.SizeOfPartitionEntry] ; size of GUID Partition Array entry
push bx ; push size of GUID Partition entry
;
; Calculating number of sectors we need to read for loading a GPT Array
;
; push dx ; preserve DX (DL = BIOS drive unit number)
; mov ax, cx ; AX * BX = number of entries * size of one entry
; mul bx ; AX = total byte size of GPT Array
; pop dx ; restore DX
; shr ax, 9 ; convert to sectors
;
; ... or:
; Current GPT Arrays uses 128 partition entries each 128 bytes long
; 128 entries * 128 bytes long GPT Array entries / 512 bytes per sector = 32 sectors
;
mov al, 32 ; maximum sector size of GPT Array (hardcoded method)
mov bx, kGPTABuffer
push bx ; push address of GPT Array
call load ; read GPT Array
pop si ; SI = address of GPT Array
pop bx ; BX = size of GUID Partition Array entry
jc error
;
; Walk through GUID Partition Table Array
; and load boot record from first supported partition.
;
; If it has boot signature (0xAA55) then jump to it
; otherwise skip to next partition.
;
%if VERBOSE
LogString(gpt_str)
%endif
.gpt_loop:
mov eax, [si + gpta.PartitionTypeGUID + kGUIDLastDwordOffs]
cmp eax, kAppleGUID ; check current GUID Partition for Apple's GUID type
je .gpt_ok
;
; Turbo - also try EFI System Partition
;
cmp eax, kEFISystemGUID ; check current GUID Partition for EFI System Partition GUID type
je .gpt_ok
;
; JrCs - also try FAT2 System Partition
;
cmp eax, kBasicDataGUID ; check current GUID Partition for Basic Data Partition GUID type
jne .gpt_continue
.gpt_ok:
;
; Found a possible good partition try to boot it
;
mov eax, [si + gpta.StartingLBA] ; load boot sector from StartingLBA
mov [my_lba], eax
mov dh, 1 ; Argument for loadBootSector to check file system signature.
call loadBootSector
jne .gpt_continue ; no boot loader signature
mov si, kMBRPartTable ; fake the current GUID Partition
mov [si + part.lba], eax ; as MBR style partition for boot1h
mov BYTE [si + part.type], kPartTypeHFS ; with HFS+ filesystem type (0xAF)
jmp SHORT initBootLoader
.gpt_continue:
add si, bx ; advance SI to next partition entry
loop .gpt_loop ; loop through all partition entries
.exit:
pop bx
ret ; no more GUID partitions. Giving up.
;--------------------------------------------------------------------------
; loadBootSector - Load boot sector
;
; Arguments:
; DL = drive number (0x80 + unit number)
; DH = 0 skip file system signature checking
; 1 enable file system signature checking
; [my_lba] = starting LBA.
;
; Returns:
; ZF = 0 if boot sector hasn't kBootSignature
; 1 if boot sector has kBootSignature
;
loadBootSector:
pusha
mov al, 3
mov bx, kBoot0LoadAddr
call load
jc error
or dh, dh
jz .checkBootSignature
.checkHFSSignature:
%if VERBOSE
LogString(test_str)
%endif
;
; Looking for HFSPlus ('H+') or HFSPlus case-sensitive ('HX') signature.
;
mov ax, [kBoot0LoadAddr + 2 * kSectorBytes]
cmp ax, kHFSPSignature ; 'H+'
je .checkBootSignature
cmp ax, kHFSPCaseSignature ; 'HX'
je .checkBootSignature
;
; Looking for exFAT signature
;
mov ax, [kBoot0LoadAddr + 3]
cmp ax, kEXFATSignature ; 'EX'
je .checkBootSignature
;
; Looking for boot1f32 magic string.
;
mov ax, [kBoot0LoadAddr + kFAT32BootCodeOffset]
cmp ax, kBoot1FAT32Magic
jne .exit
.checkBootSignature:
;
; Check for boot block signature 0xAA55
;
cmp WORD [kBoot0LoadAddr + kSectorBytes - 2], kBootSignature
.exit:
popa
ret
;--------------------------------------------------------------------------
; load - Load one or more sectors from a partition.
;
; Arguments:
; AL = number of 512-byte sectors to read.
; ES:BX = pointer to where the sectors should be stored.
; DL = drive number (0x80 + unit number)
; [my_lba] = starting LBA.
;
; Returns:
; CF = 0 success
; 1 error
;
load:
push cx
.ebios:
mov cx, 5 ; load retry count
.ebios_loop:
call read_lba ; use INT13/F42
jnc .exit
loop .ebios_loop
.exit:
pop cx
ret
;--------------------------------------------------------------------------
; read_lba - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; ES:BX = pointer to where the sectors should be stored.
; DL = drive number (0x80 + unit number)
; [my_lba] = starting LBA.
;
; Returns:
; CF = 0 success
; 1 error
;
read_lba:
pushad ; save all registers
mov bp, sp ; save current SP
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
mov ecx, [my_lba] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
; It pushes 2 bytes with a smaller opcode than if WORD was used
push BYTE 16 ; offset 0-1, packet size
DebugChar('<')
%if DEBUG
mov eax, ecx
call print_hex
%endif
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; DL = drive number (80h + drive unit)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov si, sp
mov ah, 0x42
int 0x13
jnc .exit
DebugChar('R') ; indicate INT13/F42 error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
xor ax, ax ; Func 0
int 0x13 ; INT 13
stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
popad
ret
;--------------------------------------------------------------------------
; Write a string with 'boot0: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pusha
push di
mov si, log_title_str
call print_string
pop si
call print_string
popa
ret
;--------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
cld ; increment SI after each lodsb call
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp short .loop
.exit:
ret
%if DEBUG
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pusha
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popa
ret
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
getc:
pusha
mov ah, 0
int 0x16
popa
ret
%endif ;DEBUG
;--------------------------------------------------------------------------
; NULL terminated strings.
;
%if VERBOSE
gpt_str db 'GPT', 0
test_str db 'test', 0
done_str db 'done', 0
%endif
boot_error_str db 'error', 0
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized booter with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
;
; According to EFI specification, maximum boot code size is 440 bytes
;
pad_boot:
times 428-($-$$) db 0 ; 428 = 440 - len(log_title_str)
log_title_str:
%ifdef ACTIVEFIRST
db 10, 13, 'boot0af: ', 0 ; can be use as signature
%else
db 10, 13, 'boot0ss: ', 0 ; can be use as signature
%endif
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
ABSOLUTE 0xE400
;
; In memory variables.
;
my_lba resd 1 ; Starting LBA for read_lba function
; END
|
al3xtjames/Clover
| 16,074
|
BootHFS/boot1xalt.s
|
;
; Copyright (c) 2014-2015 Zenith432 All rights reserved.
;
; Partition Boot Loader: boot1x
; This version of boot1x tries to find a stage2 boot file in the root folder.
;
; Credits:
; Portions based on boot1f32.
; Thanks to Robert Shullich for
; "Reverse Engineering the Microsoft exFAT File System" dated Dec 1, 2009.
; T13 Commitee document EDD-4 for information about BIOS int 0x13.
;
; This program is designed to reside in blocks 0 - 1 of an exFAT partition.
; It expects that the MBR has left the drive number in DL.
;
; This version requires a BIOS with EBIOS (LBA) support.
;
; This code is written for the NASM assembler.
; nasm -f bin -o boot1x boot1x.s
;
; Written by zenith432 during November 2014.
; Modified by zenith432 January 2015
; Added Feature: Support digit keypress with two second delay (-DSELECTION_FEATURE)
;
bits 16
%define SELECTION_FEATURE 1
%define VERBOSE 1
%define USESIDL 1
%define USEBP 1
kMaxBlockCount equ 127 ; Max block count supported by Int 0x13, function 0x42, old school
kBootBlockBytes equ 512 ; Bytes in a exFAT Boot block
kBootSignature equ 0xaa55 ; Boot block signature
kBoot1StackAddress equ 0xfff0 ; Address of top-of-stack 0:0xfff0
kBoot1LoadAddr equ 0x7c00 ; Address of loaded boot block 0:0x7c00
kBoot2Segment equ 0x2000 ; Address for boot2 0x2000:0x200
kBoot2Address equ 512
kFATBuf equ 0x6c00 ; Address for FAT block buffer 0:0x6c00 (4K space)
kRootDirBuf equ 0x5c00 ; Address for Root Directory block buffer 0:0x5c00 (4K space)
kMaxCluster equ 0xfffffff7 ; exFAT max cluster value + 1 (for FAT32 it's 0x0ffffff8)
kMaxContigClusters equ 1024 ; Max contiguous clusters returned by getRange
kBootNameHash equ 0xdc36 ; exFAT name hash for 'BOOT' (in UTF16LE)
kBoot2MaxBytes equ (512 * 1024 - 512) ; must fit between 0x20200 and 0xa0000
struc PartitionEntry ; MBR partition entry (truncated)
times 8 resb 1
.lba: resd 1 ; starting lba
endstruc
struc BootParams ; BOOT file parameters
.cluster: resd 1 ; 1st cluster of BOOT
.size: resd 1 ; size of BOOT in bytes
resw 1
.flag: resb 1
endstruc
struc DirIterator ; exFAT Directory Iterator
.entries_end: resb 1 ; beyond last 32-byte entry (possible values 16, 32, 64, 128)
.cluster: resd 1 ; current cluster
.lba_high: resd 1 ; upper 32 bits of lba
.lba_end: resd 1 ; beyond last block (lower 32-bits)
.lba: resd 1 ; current block
.entry: resb 1 ; current 32-byte entry
endstruc
struc FATCache ; Manages cache state for FAT blocks
.shift: resb 1 ; right shift for converting cluster # to FAT block address
.mask: resw 1 ; bit mask for finding cluster # in FAT block
.lba: resd 1 ; lba # cached in FAT block buffer (note that FAT block address is limited to 32 bits)
endstruc
%ifdef USEBP
%define BPR bp - gPartitionOffset +
%else
%define BPR
%endif
section .text
org kBoot1LoadAddr
jmp start
times (3 - $ + $$) nop
gOEMName: times 8 db 0 ; 'EXFAT '
;
; Scratch Area
; Used for data structures
;
times (64 - BootParams_size - DirIterator_size - FATCache_size - $ + $$) db 0
gsParams: times BootParams_size db 0
gsIterator: times DirIterator_size db 0
gsFATCache: times FATCache_size db 0
;
; exFAT BPB
;
gPartitionOffset: dd 0, 0
gVolumeLength: dd 0, 0
gFATOffset: dd 0
gFATLength: dd 0
gClusterHeapOffset: dd 0
gClusterCount: dd 0
gRootDirectory1stCluster: dd 0
gVolumeSerialNubmer: dd 0
gFileSystemRevision: dw 0 ; 0x100
gVolumeFlags: dw 0
gBytesPerBlock: db 0 ; range 9 - 12 (power of 2)
gBlocksPerCluster: db 0 ; gBytesPerBlock + gBlocksPerCluster <= 25 (power of 2)
gNumberOfFATs: db 0 ; should be 1
gDriveSelect: db 0 ; probably 0x80
gPercentInUse: db 0
times 7 db 0
start:
cli
xor eax, eax
mov ss, ax
mov sp, kBoot1StackAddress
sti
mov ds, ax
mov es, ax
;
; Initializing global variables.
;
%ifdef USEBP
mov bp, gPartitionOffset
%endif
%ifdef USESIDL
;
; Shouldn't be necessary to use DS:SI because
; 1) Existing gPartitionOffset must be correct in
; order for filesystem to work well when mounted.
; 2) LBA may be 64 bits if booted from GPT.
; 3) Not all MBR boot records pass DS:SI
; pointing to MBR partition entry.
;
%if 0
mov ecx, [si + PartitionEntry.lba]
mov [BPR gPartitionOffset + 4], eax
mov [BPR gPartitionOffset], ecx
%endif
;
; However, by convention BIOS passes boot
; drive number in dl, so use that instead
; of existing gDriveSelect
;
mov [BPR gDriveSelect], dl
%endif
;
; Initialize FAT Cache
;
dec eax
mov dword [BPR gsFATCache + FATCache.lba], eax ; alternatively store gFATLength here
mov cl, [BPR gBytesPerBlock]
sub cl, 2 ; range 7 - 10
mov [BPR gsFATCache + FATCache.shift], cl
neg ax
shl ax, cl
dec ax
mov [BPR gsFATCache + FATCache.mask], ax
;
; Initialize Iterator
;
mov al, 1
sub cl, 3 ; range 4 - 7
shl al, cl
mov [BPR gsIterator + DirIterator.entries_end], al
mov [BPR gsIterator + DirIterator.entry], al
xor eax, eax
mov ecx, [BPR gRootDirectory1stCluster]
mov [BPR gsIterator + DirIterator.lba_end], eax
mov [BPR gsIterator + DirIterator.lba], eax
mov [BPR gsIterator + DirIterator.cluster], ecx
%ifdef VERBOSE
mov di, init_str
call log_string
%endif
%ifdef SELECTION_FEATURE
call setBootFile
%endif
;
; Search root directory for BOOT
;
.loop:
call nextDirEntry
jc error
cld
lodsb
.revert:
test al, al ; end of root directory?
jz error
cmp al, 0x85 ; file/subdir entry?
jnz .loop
lodsb
cmp al, 2 ; 2ndary count should be 2
jb .loop
add si, 2 ; skip checksum
lodsb
test al, 0x10 ; file attributes - check not a directory
jnz .loop
call nextDirEntry
jc error
cld
lodsb
cmp al, 0xc0 ; stream extension entry?
jnz .revert
lodsb
mov dl, al ; General 2ndary flag
inc si
lodsb
.name_length_point:
cmp al, 4 ; name length
jnz .loop
lodsw ; name hash
.name_hash_point:
cmp ax, kBootNameHash
jnz .loop
add si, 2
mov eax, [si + 4] ; high 32 bits of valid data length
test eax, eax
jz .more
and dl, 0xfe ; if size too big, mark as no allocation
.more:
lodsd ; valid data length
mov [BPR gsParams + BootParams.size], eax
add si, 8
lodsd ; first cluster
mov [BPR gsParams + BootParams.cluster], eax
mov [BPR gsParams + BootParams.flag], dl
call nextDirEntry
jc error
cld
lodsb
cmp al, 0xc1
jnz .revert
inc si ; skip flags
lodsd ; unicode chars 1 - 2
or eax, 0x200020 ; tolower
cmp eax, 0x6f0062 ; 'bo' in UTF16LE
jnz .loop
lodsd ; unicode chars 3 - 4
or eax, 0x200020 ; tolower
cmp eax, 0x74006f ; 'ot' in UTF16LE
jnz .loop
;
; done - found boot file!
;
mov dl, [BPR gsParams + BootParams.flag]
test dl, 1 ; no allocation or length too big?
jz error
mov ebx, [BPR gsParams + BootParams.size]
cmp ebx, kBoot2MaxBytes + 1
jnb error
call BytesToBlocks ; convert size to blocks
; boot2 file size in blocks is in bx
load_boot2: ; anchor for localizing next labels
xor esi, esi ; no blocks after 1st range
test dl, 2 ; FAT Chain?
cmovnz edx, [BPR gsParams + BootParams.cluster] ; if not
jnz .oneshot ; load contiguous file
;
; load via FAT
;
mov si, bx ; total blocks to si
.loop:
mov eax, [BPR gsParams + BootParams.cluster]
mov edx, eax
call getRange
test ebx, ebx
jnz .nonempty
test si, si
jnz error
jmp boot2
.nonempty:
cmp ebx, esi
cmovnb bx, si
sub si, bx
mov [BPR gsParams + BootParams.cluster], eax
.oneshot:
call ClusterToLBA
mov ax, bx
mov ecx, edx
mov edx, (kBoot2Segment << 4) | kBoot2Address
call readBlocks
; TODO: error
test si, si
jnz .loop
; fall through to boot2
boot2:
mov dl, [BPR gDriveSelect] ; load BIOS drive number
jmp kBoot2Segment:kBoot2Address
error:
%ifdef VERBOSE
mov di, error_str
call log_string
%endif
hang:
hlt
jmp hang
;--------------------------------------------------------------------------
; ClusterToLBA - Converts cluster number to 64-bit LBA
;
; Arguments:
; EDX = cluster number
;
; Returns
; EDI:EDX = corresponding block address
;
; Assumes input cluster number is valid
;
ClusterToLBA:
push cx
xor edi, edi
sub edx, 2
mov cl, [BPR gBlocksPerCluster]
shld edi, edx, cl
shl edx, cl
add edx, [BPR gClusterHeapOffset]
adc edi, 0
pop cx
ret
;--------------------------------------------------------------------------
; BytesToBlocks - Converts byte size to blocks (rounding up to next block)
;
; Arguments:
; EBX = size in bytes
;
; Returns:
; EBX = size in blocks (rounded up)
;
; Clobbers eax, cl
;
BytesToBlocks:
xor eax, eax
inc ax
mov cl, [BPR gBytesPerBlock]
shl ax, cl
dec ax
add ebx, eax
shr ebx, cl
ret
times (kBootBlockBytes - 2 - $ + $$) nop
dw kBootSignature
block1_end:
;--------------------------------------------------------------------------
; nextDirEntry - Locates the next 32-byte entry in Root Directory,
; loading block if necessary.
;
; Returns:
; CF set if end of Root Directory
; CF clear, and DS:SI points to next entry if exists
;
; Clobbers eax, ebx, ecx, edx, edi
;
nextDirEntry:
movzx ax, [BPR gsIterator + DirIterator.entry]
cmp al, [BPR gsIterator + DirIterator.entries_end]
jb .addressentry
mov ecx, [BPR gsIterator + DirIterator.lba]
mov edi, [BPR gsIterator + DirIterator.lba_high]
cmp ecx, [BPR gsIterator + DirIterator.lba_end]
jnz .readblock
mov eax, [BPR gsIterator + DirIterator.cluster]
mov edx, eax
call getRange
test ebx, ebx
jnz .nonempty
stc
ret
.nonempty:
mov [BPR gsIterator + DirIterator.cluster], eax
call ClusterToLBA
mov ecx, edx
add edx, ebx
mov [BPR gsIterator + DirIterator.lba_high], edi
mov [BPR gsIterator + DirIterator.lba_end], edx
.readblock:
mov al, 1
%if 0
mov edx, kRootDirBuf
%else
xor edx, edx
mov dh, kRootDirBuf >> 8
%endif
call readLBA
; TODO error
inc ecx
jnz .skip
inc edi
mov [BPR gsIterator + DirIterator.lba_high], edi
.skip:
mov [BPR gsIterator + DirIterator.lba], ecx
xor ax, ax
.addressentry:
mov si, ax
inc al
mov [BPR gsIterator + DirIterator.entry], al
shl si, 5
add si, kRootDirBuf
clc
ret
;--------------------------------------------------------------------------
; getRange - Calculates contiguous range of clusters from FAT
;
; Arguments:
; EAX = start cluster
;
; Returns:
; EAX = next cluster after range
; EBX = number of contiguous blocks in range
;
; Range calculated is at most kMaxContigClusters clusters long
;
getRange:
push ecx
push edx
push edi
push si
xor edi, edi
%if 0
mov edx, kFATBuf
%else
mov edx, edi
mov dh, kFATBuf >> 8
%endif
mov ebx, edi
.loop:
cmp eax, 2
jb .finishup
cmp eax, -9 ;kMaxCluster
jnb .finishup
cmp bx, kMaxContigClusters
jnb .finishup
inc bx
mov si, ax
and si, [BPR gsFATCache + FATCache.mask]
shl si, 2
mov ecx, eax
inc ecx
push ecx
mov cl, [BPR gsFATCache + FATCache.shift]
shr eax, cl
cmp eax, [BPR gsFATCache + FATCache.lba]
jz .iscached
mov ecx, [BPR gFATOffset]
add ecx, eax
mov [BPR gsFATCache + FATCache.lba], eax
mov al, 1
call readLBA
; TODO: error?
.iscached:
pop ecx
mov eax, [kFATBuf + si]
cmp eax, ecx
jz .loop
.finishup:
mov cl, [BPR gBlocksPerCluster]
shl ebx, cl
pop si
pop edi
pop edx
pop ecx
ret
%ifdef SELECTION_FEATURE
;--------------------------------------------------------------------------
; setBootFile - Waits two seconds for a keypress.
; If keypress is digit '0' - '9' alters boot file from /boot to /boot<digit>
; If keypress anything else or no keypress - uses /boot.
;
; Arguments:
; None
;
; Returns:
; None
;
; Clobbers ax, cx, dx
;
setBootFile:
mov cx, 2000 ; loop counter = max 2000 miliseconds in total
.loop:
mov ah, 1 ; int 0x16, Func 0x01 - get keyboard status/preview key
int 0x16
jnz .keypress ; got keypress
; wait for 1 ms: int 0x15, Func 0x86 (wait for cx:dx microseconds)
push cx ; save loop counter
xor cx, cx
mov dx, 1000
mov ah, 0x86
int 0x15
pop cx ; restore loop counter
loop .loop
.done:
ret
.keypress:
xor ah, ah ; read the char from buffer to spend it
int 0x16
; have a key - ASCII is in al
cmp al, '0'
jb .done
cmp al, '9' + 1
jae .done
;
; Alter code so name length tested is 5 instead of 4
; Compute new hash value with digit and alter code
; to check for modified hash value.
; Note: code continues to compare 4 characters 'boot'.
; For any other ascii character in 5th position,
; the hash value does not collide. There are
; non-ascii unicode characters in 5th position that
; collide with hash-value, but ignore those for simplicity.
;
xor ah, ah
inc byte [start.name_length_point + 1]
add ax, (kBootNameHash >> 1) | ((kBootNameHash & 1) << 15)
ror ax, 1
mov [start.name_hash_point + 1], ax
ret
%endif
;--------------------------------------------------------------------------
; readBlocks - Reads more than kMaxBlockCount blocks using LBA addressing.
;
; Arguments:
; AX = number of blocks to read (valid from 1-1280).
; EDX = pointer to where the blocks should be stored.
; EDI:ECX = block offset in partition (64 bits)
;
; Returns:
; CF = 0 success
; 1 error
;
readBlocks:
pushad
mov bx, ax
.loop:
xor eax, eax
mov al, kMaxBlockCount
cmp bx, ax
cmovb ax, bx
call readLBA
; TODO: error?
sub bx, ax
jz .exit
add ecx, eax
adc edi, 0
push cx
mov cl, [BPR gBytesPerBlock]
shl eax, cl
pop cx
add edx, eax
jmp .loop
.exit:
popad
ret
;--------------------------------------------------------------------------
; readLBA - Read blocks from a partition using LBA addressing.
;
; Arguments:
; AL = number of blocks to read (valid from 1-kMaxBlockCount).
; EDX = pointer to where the blocks should be stored.
; EDI:ECX = block offset in partition (64 bits)
; [gDriveSelect] = drive number (0x80 + unit number)
; [gPartitionOffset] = partition location on drive
;
; Returns:
; CF = 0 success
; 1 error
; Presently, jumps to error on BIOS-reported failure
;
readLBA:
pushad ; save all registers
push es ; save ES
mov bp, sp ; save current SP
;
; Adjust to 16 bit segment:offset address
; to allow for reading up to 64K
;
mov bl, dl
and bx, 0xf
shr edx, 4
mov es, dx
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
add ecx, [gPartitionOffset]
adc edi, [gPartitionOffset + 4]
push edi
push ecx
push es
push bx
xor ah, ah
push ax
push word 16
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; DL = drive number (0x80 + unit number)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov dl, [gDriveSelect] ; load BIOS drive number
mov si, sp
mov ah, 0x42
int 0x13
jc error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
; xor ax, ax ; Func 0
; int 0x13 ; INT 13
; stc ; set carry to indicate error
;.exit
mov sp, bp
pop es
popad
ret
%ifdef VERBOSE
;--------------------------------------------------------------------------
; Write a string with log_title_str prefix to the console.
;
; Arguments:
; DS:DI pointer to a NULL terminated string.
;
log_string:
pushad
push di
mov si, log_title_str
call print_string
pop si
call print_string
popad
ret
;-------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
.loop:
lodsb ; load a byte from DS:SI into AL
test al, al ; Is it a NULL?
jz .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp .loop
.exit:
ret
%endif ; VERBOSE
;--------------------------------------------------------------------------
; Static data.
;
%ifdef VERBOSE
log_title_str: db 13, 10, 'boot1x: ', 0
init_str: db 'init', 0
error_str: db 'error', 0
%endif
times (kBootBlockBytes - 4 - $ + block1_end) db 0
dw 0, kBootSignature
|
al3xtjames/Clover
| 22,582
|
BootHFS/boot0ab.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Boot Loader: boot0
;
; A small boot sector program written in x86 assembly whose only
; responsibility is to locate the active partition, load the
; partition booter into memory, and jump to the booter's entry point.
; It leaves the boot drive in DL and a pointer to the partition entry in SI.
;
; This boot loader must be placed in the Master Boot Record.
;
; In order to coexist with a fdisk partition table (64 bytes), and
; leave room for a two byte signature (0xAA55) in the end, boot0 is
; restricted to 446 bytes (512 - 64 - 2). If boot0 did not have to
; live in the MBR, then we would have 510 bytes to work with.
;
; boot0 is always loaded by the BIOS or another booter to 0:7C00h.
;
; This code is written for the NASM assembler.
; nasm boot0ab.s -o boot0ab
;
; This version of boot0 implements hybrid GUID/MBR partition scheme support
;
; Written by Tams Kosrszky on 2008-03-10
;
; Turbo added EFI System Partition boot support
;
; Added KillerJK's switchPass2 modifications
;
;
; Set to 1 to enable obscure debug messages.
;
DEBUG EQU 0
;
; Set to 1 to enable verbose mode
;
VERBOSE EQU 1
;
; Various constants.
;
kBoot0Segment EQU 0x0000
kBoot0Stack EQU 0xFFF0 ; boot0 stack pointer
kBoot0LoadAddr EQU 0x7C00 ; boot0 load address
kBoot0RelocAddr EQU 0xE000 ; boot0 relocated address
kMBRBuffer EQU 0x1000 ; MBR buffer address
kLBA1Buffer EQU 0x1200 ; LBA1 - GPT Partition Table Header buffer address
kGPTABuffer EQU 0x1400 ; GUID Partition Entry Array buffer address
kPartTableOffset EQU 0x1be
kMBRPartTable EQU kMBRBuffer + kPartTableOffset
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kHFSPSignature EQU 'H+' ; HFS+ volume signature
kHFSPCaseSignature EQU 'HX' ; HFS+ volume case-sensitive signature
kFAT32BootCodeOffset EQU 0x5a ; offset of boot code in FAT32 boot sector
kBoot1FAT32Magic EQU 'BO' ; Magic string to detect our boot1f32 code
kGPTSignatureLow EQU 'EFI ' ; GUID Partition Table Header Signature
kGPTSignatureHigh EQU 'PART'
kGUIDLastDwordOffs EQU 12 ; last 4 byte offset of a GUID
kPartCount EQU 4 ; number of paritions per table
kPartTypeHFS EQU 0xaf ; HFS+ Filesystem type
kPartTypeABHFS EQU 0xab ; Apple_Boot partition
kPartTypePMBR EQU 0xee ; On all GUID Partition Table disks a Protective MBR (PMBR)
; in LBA 0 (that is, the first block) precedes the
; GUID Partition Table Header to maintain compatibility
; with existing tools that do not understand GPT partition structures.
; The Protective MBR has the same format as a legacy MBR
; and contains one partition entry with an OSType set to 0xEE
; reserving the entire space used on the disk by the GPT partitions,
; including all headers.
kPartActive EQU 0x80 ; active flag enabled
kPartInactive EQU 0x00 ; active flag disabled
kHFSGUID EQU 0x48465300 ; first 4 bytes of Apple HFS Partition Type GUID.
kAppleGUID EQU 0xACEC4365 ; last 4 bytes of Apple type GUIDs. 426F6F74-0000-11AA-AA11-00306543ECAC
kEFISystemGUID EQU 0x3BC93EC9 ; last 4 bytes of EFI System Partition Type GUID:
; C12A7328-F81F-11D2-BA4B-00A0C93EC93B
%ifdef FLOPPY
kDriveNumber EQU 0x00
%else
kDriveNumber EQU 0x80
%endif
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
;
; Format of GPT Partition Table Header
;
struc gpth
.Signature resb 8
.Revision resb 4
.HeaderSize resb 4
.HeaderCRC32 resb 4
.Reserved resb 4
.MyLBA resb 8
.AlternateLBA resb 8
.FirstUsableLBA resb 8
.LastUsableLBA resb 8
.DiskGUID resb 16
.PartitionEntryLBA resb 8
.NumberOfPartitionEntries resb 4
.SizeOfPartitionEntry resb 4
.PartitionEntryArrayCRC32 resb 4
endstruc
;
; Format of GUID Partition Entry Array
;
struc gpta
.PartitionTypeGUID resb 16
.UniquePartitionGUID resb 16
.StartingLBA resb 8
.EndingLBA resb 8
.Attributes resb 8
.PartitionName resb 72
endstruc
;
; Macros.
;
%macro DebugCharMacro 1
mov al, %1
call print_char
%endmacro
%macro LogString 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%else
%define DebugChar(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot0RelocAddr
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; Set up the stack to grow down from kBoot0Segment:kBoot0Stack.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor ax, ax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot0Stack ; sp <- top of stack
sti ; reenable interrupts
mov es, ax ; es <- 0
mov ds, ax ; ds <- 0
;
; Relocate boot0 code.
;
mov si, kBoot0LoadAddr ; si <- source
mov di, kBoot0RelocAddr ; di <- destination
cld ; auto-increment SI and/or DI registers
mov cx, kSectorBytes/2 ; copy 256 words
repnz movsw ; repeat string move (word) operation
;
; Code relocated, jump to start_reloc in relocated location.
;
jmp kBoot0Segment:start_reloc
;--------------------------------------------------------------------------
; Start execution from the relocated location.
;
start_reloc:
DebugChar('>')
%if DEBUG
mov al, dl
call print_hex
%endif
;
; Since this code may not always reside in the MBR, always start by
; loading the MBR to kMBRBuffer and LBA1 to kGPTBuffer.
;
xor eax, eax
mov [my_lba], eax ; store LBA sector 0 for read_lba function
mov al, 2 ; load two sectors: MBR and LBA1
mov bx, kMBRBuffer ; MBR load address
call load
jc error ; MBR load error
;
; Look for the booter partition in the MBR partition table,
; which is at offset kMBRPartTable.
;
mov si, kMBRPartTable ; pointer to partition table
call find_boot ; will not return on success
error:
LogString(boot_error_str)
hang:
hlt
jmp hang
;--------------------------------------------------------------------------
; Find the active (boot) partition and load the booter from the partition.
;
; Arguments:
; DL = drive number (0x80 + unit number)
; SI = pointer to fdisk partition table.
;
; Clobber list:
; EAX, BX, EBP
;
find_boot:
;
; Check for boot block signature 0xAA55 following the 4 partition
; entries.
;
cmp WORD [si + part_size * kPartCount], kBootSignature
jne .exit ; boot signature not found.
xor bx, bx ; BL will be set to 1 later in case of
; Protective MBR has been found
inc bh ; BH = 1. Giving a chance for a second pass
; to boot an inactive but boot1h aware HFS+ partition
; by scanning the MBR partition entries again.
.start_scan:
mov cx, kPartCount ; number of partition entries per table
.loop:
;
; First scan through the partition table looking for the active
; partition.
;
%if DEBUG
mov al, [si + part.type] ; print partition type
call print_hex
%endif
mov eax, [si + part.lba] ; save starting LBA of current
mov [my_lba], eax ; MBR partition entry for read_lba function
cmp BYTE [si + part.type], 0 ; unused partition?
je .continue ; skip to next entry
cmp BYTE [si + part.type], kPartTypePMBR ; check for Protective MBR
jne .testPass
mov BYTE [si + part.bootid], kPartInactive ; found Protective MBR
; clear active flag to make sure this protective
; partition won't be used as a bootable partition.
mov bl, 1 ; Assume we can deal with GPT but try to scan
; later if not found any other bootable partitions.
.testPass:
cmp bh, 1
jne .Pass2
.Pass1:
cmp BYTE [si + part.type], kPartTypeABHFS ; In pass 1 we're going to find a HFS+ partition
; equipped with boot1h in its boot record
; regardless if it's active or not.
jne .continue
mov dh, 1 ; Argument for loadBootSector to check HFS+ partition signature.
jmp .tryToBoot
.Pass2:
cmp BYTE [si + part.bootid], kPartActive ; In pass 2 we are walking on the standard path
; by trying to hop on the active partition.
jne .continue
xor dh, dh ; Argument for loadBootSector to skip HFS+ partition
; signature check.
DebugChar('*')
;
; Found boot partition, read boot sector to memory.
;
.tryToBoot:
call loadBootSector
jne .continue
jmp SHORT initBootLoader
.continue:
add si, BYTE part_size ; advance SI to next partition entry
loop .loop ; loop through all partition entries
;
; Scanned all partitions but not found any with active flag enabled
; Anyway if we found a protective MBR before we still have a chance
; for a possible GPT Header at LBA 1
;
dec bl
jnz .switchPass2 ; didn't find Protective MBR before
call checkGPT
.switchPass2:
;
; Switching to Pass 2
; try to find a boot1h aware HFS+ MBR partition
;
dec bh
mov si, kMBRPartTable ; set SI to first entry of MBR Partition table
jz .start_scan ; scan again
.exit:
ret ; Giving up.
;
; Jump to partition booter. The drive number is already in register DL.
; SI is pointing to the modified partition entry.
;
initBootLoader:
DebugChar('J')
%if VERBOSE
LogString(done_str)
%endif
jmp kBoot0LoadAddr
;
; Found Protective MBR Partition Type: 0xEE
; Check for 'EFI PART' string at the beginning
; of LBA1 for possible GPT Table Header
;
checkGPT:
push bx
mov di, kLBA1Buffer ; address of GUID Partition Table Header
cmp DWORD [di], kGPTSignatureLow ; looking for 'EFI '
jne .exit ; not found. Giving up.
cmp DWORD [di + 4], kGPTSignatureHigh ; looking for 'PART'
jne .exit ; not found. Giving up indeed.
mov si, di
;
; Loading GUID Partition Table Array
;
mov eax, [si + gpth.PartitionEntryLBA] ; starting LBA of GPT Array
mov [my_lba], eax ; save starting LBA for read_lba function
mov cx, [si + gpth.NumberOfPartitionEntries] ; number of GUID Partition Array entries
mov bx, [si + gpth.SizeOfPartitionEntry] ; size of GUID Partition Array entry
push bx ; push size of GUID Partition entry
;
; Calculating number of sectors we need to read for loading a GPT Array
;
; push dx ; preserve DX (DL = BIOS drive unit number)
; mov ax, cx ; AX * BX = number of entries * size of one entry
; mul bx ; AX = total byte size of GPT Array
; pop dx ; restore DX
; shr ax, 9 ; convert to sectors
;
; ... or:
; Current GPT Arrays uses 128 partition entries each 128 bytes long
; 128 entries * 128 bytes long GPT Array entries / 512 bytes per sector = 32 sectors
;
mov al, 32 ; maximum sector size of GPT Array (hardcoded method)
mov bx, kGPTABuffer
push bx ; push address of GPT Array
call load ; read GPT Array
pop si ; SI = address of GPT Array
pop bx ; BX = size of GUID Partition Array entry
jc error
;
; Walk through GUID Partition Table Array
; and load boot record from first available HFS+ partition.
;
; If it has boot signature (0xAA55) then jump to it
; otherwise skip to next partition.
;
%if VERBOSE
LogString(gpt_str)
%endif
.gpt_loop:
mov eax, [si + gpta.PartitionTypeGUID + kGUIDLastDwordOffs]
cmp eax, kAppleGUID ; check current GUID Partition for Apple's GUID type
je .gpt_ok
;
; Turbo - also try EFI System Partition
;
cmp eax, kEFISystemGUID ; check current GUID Partition for EFI System Partition GUID type
jne .gpt_continue
.gpt_ok:
;
; Found HFS Partition
;
mov eax, [si + gpta.StartingLBA] ; load boot sector from StartingLBA
mov [my_lba], eax
mov dh, 1 ; Argument for loadBootSector to check HFS+ partition signature.
call loadBootSector
jne .gpt_continue ; no boot loader signature
mov si, kMBRPartTable ; fake the current GUID Partition
mov [si + part.lba], eax ; as MBR style partition for boot1h
mov BYTE [si + part.type], kPartTypeHFS ; with HFS+ filesystem type (0xAF)
jmp SHORT initBootLoader
.gpt_continue:
add si, bx ; advance SI to next partition entry
loop .gpt_loop ; loop through all partition entries
.exit:
pop bx
ret ; no more GUID partitions. Giving up.
;--------------------------------------------------------------------------
; loadBootSector - Load boot sector
;
; Arguments:
; DL = drive number (0x80 + unit number)
; DH = 0 skip HFS+ partition signature checking
; 1 enable HFS+ partition signature checking
; [my_lba] = starting LBA.
;
; Returns:
; ZF = 0 if boot sector hasn't kBootSignature
; 1 if boot sector has kBootSignature
;
loadBootSector:
pusha
mov al, 3
mov bx, kBoot0LoadAddr
call load
jc error
or dh, dh
jz .checkBootSignature
.checkHFSSignature:
%if VERBOSE
LogString(test_str)
%endif
;
; Looking for HFSPlus ('H+') or HFSPlus case-sensitive ('HX') signature.
;
mov ax, [kBoot0LoadAddr + 2 * kSectorBytes]
cmp ax, kHFSPSignature ; 'H+'
je .checkBootSignature
cmp ax, kHFSPCaseSignature ; 'HX'
je .checkBootSignature
;
; Looking for boot1f32 magic string.
;
mov ax, [kBoot0LoadAddr + kFAT32BootCodeOffset]
cmp ax, kBoot1FAT32Magic
jne .exit
.checkBootSignature:
;
; Check for boot block signature 0xAA55
;
mov di, bx
cmp WORD [di + kSectorBytes - 2], kBootSignature
.exit:
popa
ret
;--------------------------------------------------------------------------
; load - Load one or more sectors from a partition.
;
; Arguments:
; AL = number of 512-byte sectors to read.
; ES:BX = pointer to where the sectors should be stored.
; DL = drive number (0x80 + unit number)
; [my_lba] = starting LBA.
;
; Returns:
; CF = 0 success
; 1 error
;
load:
push cx
.ebios:
mov cx, 5 ; load retry count
.ebios_loop:
call read_lba ; use INT13/F42
jnc .exit
loop .ebios_loop
.exit:
pop cx
ret
;--------------------------------------------------------------------------
; read_lba - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; ES:BX = pointer to where the sectors should be stored.
; DL = drive number (0x80 + unit number)
; [my_lba] = starting LBA.
;
; Returns:
; CF = 0 success
; 1 error
;
read_lba:
pushad ; save all registers
mov bp, sp ; save current SP
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
mov ecx, [my_lba] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
; It pushes 2 bytes with a smaller opcode than if WORD was used
push BYTE 16 ; offset 0-1, packet size
DebugChar('<')
%if DEBUG
mov eax, ecx
call print_hex
%endif
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; DL = drive number (80h + drive unit)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov si, sp
mov ah, 0x42
int 0x13
jnc .exit
DebugChar('R') ; indicate INT13/F42 error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
xor ax, ax ; Func 0
int 0x13 ; INT 13
stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
popad
ret
;--------------------------------------------------------------------------
; Write a string with 'boot0: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pusha
push di
mov si, log_title_str
call print_string
pop si
call print_string
popa
ret
;--------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
cld ; increment SI after each lodsb call
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp short .loop
.exit:
ret
%if DEBUG
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pusha
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popa
ret
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
getc:
pusha
mov ah, 0
int 0x16
popa
ret
%endif ;DEBUG
;--------------------------------------------------------------------------
; NULL terminated strings.
;
log_title_str db 10, 13, 'boot0: ', 0
boot_error_str db 'error', 0
%if VERBOSE
gpt_str db 'GPT', 0
test_str db 'test', 0
done_str db 'done', 0
%endif
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized booter with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
;
; According to EFI specification, maximum boot code size is 440 bytes
;
;
; XXX - compilation errors with debug enabled (see comment above about nasm)
; Azi: boot0.s:808: error: TIMES value -111 is negative
; boot0.s:811: error: TIMES value -41 is negative
;
pad_boot:
times 440-($-$$) db 0
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
ABSOLUTE 0xE400
;
; In memory variables.
;
my_lba resd 1 ; Starting LBA for read_lba function
; END
|
al3xtjames/Clover
| 37,087
|
BootHFS/boot1h2.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Partition Boot Loader: boot1h
;
; This program is designed to reside in sector 0+1 of an HFS+ partition.
; It expects that the MBR has left the drive number in DL
; and a pointer to the partition entry in SI.
;
; This version requires a BIOS with EBIOS (LBA) support.
;
; This code is written for the NASM assembler.
; nasm boot1.s -o boot1h
;
; This version of boot1h tries to find a stage2 boot file in the root folder.
;
; NOTE: this is an experimental version with multiple extent support.
;
; Written by Tams Kosrszky on 2008-04-14
;
;
; Set to 1 to enable obscure debug messages.
;
DEBUG EQU 0
;
; Set to 1 to enable unused code.
;
UNUSED EQU 0
;
; Set to 1 to enable verbose mode.
;
VERBOSE EQU 0
;
; Various constants.
;
NULL EQU 0
CR EQU 0x0D
LF EQU 0x0A
mallocStart EQU 0x1000 ; start address of local workspace area
maxSectorCount EQU 64 ; maximum sector count for readSectors
maxNodeSize EQU 16384
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kBoot1StackAddress EQU 0xFFF0 ; boot1 stack pointer
kBoot1LoadAddr EQU 0x7C00 ; boot1 load address
kBoot1RelocAddr EQU 0xE000 ; boot1 relocated address
kBoot1Sector1Addr EQU kBoot1RelocAddr + kSectorBytes ; boot1 load address for sector 1
kHFSPlusBuffer EQU kBoot1Sector1Addr + kSectorBytes ; HFS+ Volume Header address
kBoot2Sectors EQU (480 * 1024 - 512) / kSectorBytes ; max size of 'boot' file in sectors = 448 but I want 472
kBoot2Segment EQU 0x2000 ; boot2 load segment
kBoot2Address EQU kSectorBytes ; boot2 load address
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
;-------------------------------------------------------------------------
; HFS+ related structures and constants
;
kHFSPlusSignature EQU 'H+' ; HFS+ volume signature
kHFSPlusCaseSignature EQU 'HX' ; HFS+ volume case-sensitive signature
kHFSPlusCaseSigX EQU 'X' ; upper byte of HFS+ volume case-sensitive signature
kHFSPlusExtentDensity EQU 8 ; 8 extent descriptors / extent record
;
; HFSUniStr255
;
struc HFSUniStr255
.length resw 1
.unicode resw 255
endstruc
;
; HFSPlusExtentDescriptor
;
struc HFSPlusExtentDescriptor
.startBlock resd 1
.blockCount resd 1
endstruc
;
; HFSPlusForkData
;
struc HFSPlusForkData
.logicalSize resq 1
.clumpSize resd 1
.totalBlocks resd 1
.extents resb kHFSPlusExtentDensity * HFSPlusExtentDescriptor_size
endstruc
;
; HFSPlusVolumeHeader
;
struc HFSPlusVolumeHeader
.signature resw 1
.version resw 1
.attributes resd 1
.lastMountedVersion resd 1
.journalInfoBlock resd 1
.createDate resd 1
.modifyDate resd 1
.backupDate resd 1
.checkedDate resd 1
.fileCount resd 1
.folderCount resd 1
.blockSize resd 1
.totalBlocks resd 1
.freeBlocks resd 1
.nextAllocation resd 1
.rsrcClumpSize resd 1
.dataClumpSize resd 1
.nextCatalogID resd 1
.writeCount resd 1
.encodingsBitmap resq 1
.finderInfo resd 8
.allocationFile resb HFSPlusForkData_size
.extentsFile resb HFSPlusForkData_size
.catalogFile resb HFSPlusForkData_size
.attributesFile resb HFSPlusForkData_size
.startupFile resb HFSPlusForkData_size
endstruc
;
; B-tree related structures and constants
;
kBTIndexNode EQU 0
kBTMaxRecordLength EQU 264 ; sizeof(kHFSPlusFileThreadRecord)
kHFSRootParentID EQU 1 ; Parent ID of the root folder
kHFSRootFolderID EQU 2 ; Folder ID of the root folder
kHFSExtentsFileID EQU 3 ; File ID of the extents overflow file
kHFSCatalogFileID EQU 4 ; File ID of the catalog file
kHFSPlusFileRecord EQU 0x200
kForkTypeData EQU 0
kForkTypeResource EQU 0xFF
;
; BTNodeDescriptor
;
struc BTNodeDescriptor
.fLink resd 1
.bLink resd 1
.kind resb 1
.height resb 1
.numRecords resw 1
.reserved resw 1
endstruc
;
; BTHeaderRec
;
struc BTHeaderRec
.treeDepth resw 1
.rootNode resd 1
.leafRecords resd 1
.firstLeafNode resd 1
.lastLeafNode resd 1
.nodeSize resw 1
.maxKeyLength resw 1
.totalNodes resd 1
.freeNodes resd 1
.reserved1 resw 1
.clumpSize resd 1
.btreeType resb 1
.keyCompareType resb 1
.attributes resd 1
.reserved3 resd 16
endstruc
;
; BTIndexRec
;
struc BTIndexRec
.childID resd 1
endstruc
;
; HFSPlusCatalogKey
;
struc HFSPlusCatalogKey
;
; won't use the keyLength field for easier addressing data inside this structure
;
;.keyLength resw 1
.parentID resd 1
.nodeName resb HFSUniStr255_size
endstruc
;
; HFSPlusExtentKey
;
struc HFSPlusExtentKey
;
; won't use the keyLength field for easier addressing data inside this structure
;
;.keyLength resw 1
.forkType resb 1
.pad resb 1
.fileID resd 1
.startBlock resd 1
endstruc
;
; HFSPlusBSDInfo
;
struc HFSPlusBSDInfo
.ownerID resd 1
.groupID resd 1
.adminFlags resb 1
.ownerFlags resb 1
.fileMode resw 1
.special resd 1
endstruc
;
; FileInfo
;
struc FileInfo
.fileType resd 1
.fileCreator resd 1
.finderFlags resw 1
.location resw 2
.reservedField resw 1
endstruc
;
; ExtendedFileInfo
;
struc ExtendedFileInfo
.reserved1 resw 4
.extFinderFlags resw 1
.reserved2 resw 1
.putAwayFolderID resd 1
endstruc
;
; HFSPlusCatalogFile
;
struc HFSPlusCatalogFile
.recordType resw 1
.flags resw 1
.reserved1 resd 1
.fileID resd 1
.createDate resd 1
.contentModDate resd 1
.attributeModDate resd 1
.accessDate resd 1
.backupDate resd 1
.permissions resb HFSPlusBSDInfo_size
.userInfo resb FileInfo_size
.finderInfo resb ExtendedFileInfo_size
.textEncoding resd 1
.reserved2 resd 1
.dataFork resb HFSPlusForkData_size
.resourceFork resb HFSPlusForkData_size
endstruc
;
; Macros.
;
%macro jmpabs 1
push WORD %1
ret
%endmacro
%macro DebugCharMacro 1
pushad
mov al, %1
call print_char
call getc
popad
%endmacro
%macro PrintCharMacro 1
pushad
mov al, %1
call print_char
popad
%endmacro
%macro PutCharMacro 1
call print_char
%endmacro
%macro PrintHexMacro 1
call print_hex
%endmacro
%macro PrintString 1
mov si, %1
call print_string
%endmacro
%macro LogString 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%define PrintChar(x) PrintCharMacro x
%define PutChar(x) PutCharMacro
%define PrintHex(x) PrintHexMacro x
%else
%define DebugChar(x)
%define PrintChar(x)
%define PutChar(x)
%define PrintHex(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot1RelocAddr
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; Set up the stack to grow down from kBoot1StackSegment:kBoot1StackAddress.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor ax, ax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot1StackAddress ; sp <- top of stack
sti ; reenable interrupts
mov ds, ax ; ds <- 0
mov es, ax ; es <- 0
;
; Relocate boot1 code.
;
push si
mov si, kBoot1LoadAddr ; si <- source
mov di, kBoot1RelocAddr ; di <- destination
cld ; auto-increment SI and/or DI registers
mov cx, kSectorBytes ; copy 256 words
rep movsb ; repeat string move (word) operation
pop si
;
; Code relocated, jump to startReloc in relocated location.
;
; FIXME: Is there any way to instruct NASM to compile a near jump
; using absolute address instead of relative displacement?
;
jmpabs startReloc
;--------------------------------------------------------------------------
; Start execution from the relocated location.
;
startReloc:
;
; Initializing global variables.
;
mov eax, [si + part.lba]
mov [gPartLBA], eax ; save the current partition LBA offset
mov [gBIOSDriveNumber], dl ; save BIOS drive number
;mov WORD [gMallocPtr], mallocStart ; set free space pointer
;
; Loading upper 512 bytes of boot1h and HFS+ Volume Header.
;
xor ecx, ecx ; sector 1 of current partition
inc ecx
mov al, 2 ; read 2 sectors: sector 1 of boot1h + HFS+ Volume Header
mov edx, kBoot1Sector1Addr
call readLBA
;
; Initializing more global variables.
;
mov eax, [kHFSPlusBuffer + HFSPlusVolumeHeader.blockSize]
bswap eax ; convert to little-endian
shr eax, 9 ; convert to sector unit
mov [gBlockSize], eax ; save blockSize as little-endian sector unit!
;
; Looking for HFSPlus ('H+') or HFSPlus case-sensitive ('HX') signature.
;
mov ax, [kHFSPlusBuffer + HFSPlusVolumeHeader.signature]
cmp ax, kHFSPlusCaseSignature
je findRootBoot
cmp ax, kHFSPlusSignature
je setBootFile
hang:
hlt
jmp hang
; dmazar
; Switch between different /boot files.
; Wait for a key press for max 2 seconds and if key is pressed
; then try to load /boot<pressed key>.
; If not found - wait for another key press again.
; If timeout - load default /boot file.
;
setBootFile:
mov WORD [gMallocPtr], mallocStart ; set free space pointer
mov cx, 2000 ; loop counter = max 2000 miliseconds in total
.loop:
mov ah, 0x01 ; int 0x16, Func 0x01 - get keyboard status/preview key
int 0x16
jz .wait ; no keypress - wait and loop again
xor ah, ah ; read the char from buffer to spend it
int 0x16
; have a key - ASCII is in al - put it to file name /boot<pressed key>
mov BYTE [searchCatKeyName + 8], al
jmp SHORT .bootFileSet ; try to boot
.wait:
; waith for 1 ms: int 0x15, Func 0x86 (wait for cx:dx microseconds)
push cx ; save loop counter
xor cx, cx
mov dx, 1000
mov ah, 0x86
int 0x15
pop cx ; restore loop counter
loop .loop
; no keypress so far
; change filename to /boot by changing size in searchCatalogKey to 4 chars
; and try to load
mov WORD [searchCatalogKeyNL], 4
.bootFileSet:
;--------------------------------------------------------------------------
; Find stage2 boot file in a HFS+ Volume's root folder.
;
findRootBoot:
mov al, kHFSCatalogFileID
lea si, [searchCatalogKey]
lea di, [kHFSPlusBuffer + HFSPlusVolumeHeader.catalogFile + HFSPlusForkData.extents]
call lookUpBTree
jne error
lea si, [bp + BTree.recordDataPtr]
mov si, [si]
cmp WORD [si], kHFSPlusFileRecord
jne error
; EAX = Catalog File ID
; BX = read size in sectors
; ECX = file offset in sectors
; EDX = address of read buffer
; DI = address of HFSPlusForkData
;
; Use the second big-endian double-word as the file length in HFSPlusForkData.logicalSize
;
mov ebx, [si + HFSPlusCatalogFile.dataFork + HFSPlusForkData.logicalSize + 4]
bswap ebx ; convert file size to little-endian
add ebx, kSectorBytes - 1 ; adjust size before unit conversion
shr ebx, 9 ; convert file size to sector unit
cmp bx, kBoot2Sectors ; check if bigger than max stage2 size
ja error
mov eax, [si + HFSPlusCatalogFile.fileID]
bswap eax ; convert fileID to little-endian
xor ecx, ecx
mov edx, (kBoot2Segment << 4) + kBoot2Address
lea di, [si + HFSPlusCatalogFile.dataFork + HFSPlusForkData.extents]
call readExtent
%if VERBOSE
LogString(root_str)
%endif
boot2:
%if DEBUG
DebugChar ('!')
%endif
%if UNUSED
;
; Waiting for a key press.
;
mov ah, 0
int 0x16
%endif
mov ax, 0x1900
mov es, ax
mov BYTE [es:4], 1
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
jmp kBoot2Segment:kBoot2Address
error:
%if VERBOSE
LogString(error_str)
%endif
; not found - try again. user will have a chance to press different key
; note: if /boot is not present we may have an endless loop in trying
jmp setBootFile
;--------------------------------------------------------------------------
; readSectors - Reads more than 127 sectors using LBA addressing.
;
; Arguments:
; AX = number of 512-byte sectors to read (valid from 1-1280).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
;
; Returns:
; CF = 0 success
; 1 error
;
readSectors:
pushad
mov bx, ax
.loop:
xor eax, eax ; EAX = 0
mov al, bl ; assume we reached the last block.
cmp bx, maxSectorCount ; check if we really reached the last block
jb .readBlock ; yes, BX < MaxSectorCount
mov al, maxSectorCount ; no, read MaxSectorCount
.readBlock:
call readLBA
sub bx, ax ; decrease remaning sectors with the read amount
jz .exit ; exit if no more sectors left to be loaded
add ecx, eax ; adjust LBA sector offset
shl ax, 9 ; convert sectors to bytes
add edx, eax ; adjust target memory location
jmp .loop ; read remaining sectors
.exit:
popad
ret
;--------------------------------------------------------------------------
; readLBA - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
; [bios_drive_number] = drive number (0x80 + unit number)
;
; Returns:
; CF = 0 success
; 1 error
;
readLBA:
pushad ; save all registers
push es ; save ES
mov bp, sp ; save current SP
;
; Convert EDX to segment:offset model and set ES:BX
;
; Some BIOSes do not like offset to be negative while reading
; from hard drives. This usually leads to "boot1: error" when trying
; to boot from hard drive, while booting normally from USB flash.
; The routines, responsible for this are apparently different.
; Thus we split linear address slightly differently for these
; capricious BIOSes to make sure offset is always positive.
;
mov bx, dx ; save offset to BX
and bh, 0x0f ; keep low 12 bits
shr edx, 4 ; adjust linear address to segment base
xor dl, dl ; mask low 8 bits
mov es, dx ; save segment to ES
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
add ecx, [gPartLBA] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
push WORD 16 ; offset 0-1, packet size
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; [bios_drive_number] = drive number (0x80 + unit number)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
mov si, sp
mov ah, 0x42
int 0x13
jc error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
; xor ax, ax ; Func 0
; int 0x13 ; INT 13
; stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
pop es ; restore ES
popad
ret
%if VERBOSE
;--------------------------------------------------------------------------
; Write a string with 'boot1: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pushad
push di
mov si, log_title_str
call print_string
pop si
call print_string
popad
ret
;-------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp .loop
.exit:
ret
%endif ; VERBOSE
%if DEBUG
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
%if UNUSED
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
%endif ; UNUSED
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
;--------------------------------------------------------------------------
; getc - wait for a key press
;
getc:
pushad
mov ah, 0
int 0x16
popad
ret
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pushad
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popad
ret
%endif ; DEBUG
%if UNUSED
;--------------------------------------------------------------------------
; Convert null terminated string to HFSUniStr255
;
; Arguments:
; DS:DX pointer to a NULL terminated string.
; ES:DI pointer to result.
;
ConvertStrToUni:
pushad ; save registers
push di ; save DI for unicode string length pointer
mov si, dx ; use SI as source string pointer
xor ax, ax ; AX = unicode character
mov cl, al ; CL = string length
.loop:
stosw ; store unicode character (length 0 at first run)
lodsb ; load next character to AL
inc cl ; increment string length count
cmp al, NULL ; check for string terminator
jne .loop
pop di ; restore unicode string length pointer
dec cl ; ignoring terminator from length count
mov [di], cl ; save string length
popad ; restore registers
ret
%endif ; UNUSED
;--------------------------------------------------------------------------
; Convert big-endian HFSUniStr255 to little-endian
;
; Arguments:
; DS:SI = pointer to big-endian HFSUniStr255
; ES:DI = pointer to result buffer
;
ConvertHFSUniStr255ToLE:
pushad
lodsw
xchg ah, al
stosw
cmp al, 0
je .exit
mov cx, ax
.loop:
lodsw
xchg ah, al ; convert AX to little-endian
;
; When working with a case-sensitive HFS+ (HX) filesystem, we shouldn't change the case.
;
cmp BYTE [kHFSPlusBuffer + HFSPlusVolumeHeader.signature + 1], kHFSPlusCaseSigX
je .keepcase
or ax, ax
jne .convertToLE
dec ax ; NULL must be the strongest char
.convertToLE:
cmp ah, 0
ja .keepcase
cmp al, 'A'
jb .keepcase
cmp al, 'Z'
ja .keepcase
add al, 32 ; convert to lower-case
.keepcase:
stosw
loop .loop
.exit:
popad
ret
;--------------------------------------------------------------------------
; compare HFSPlusExtentKey structures
;
; Arguments:
; DS:SI = search key
; ES:DI = trial key
;
; Returns:
; [BTree.searchResult] = result
; FLAGS = relation between search and trial keys
;
compareHFSPlusExtentKeys:
pushad
mov dl, 0 ; DL = result of comparison, DH = bestGuess
mov eax, [si + HFSPlusExtentKey.fileID]
cmp eax, [di + HFSPlusExtentKey.fileID]
jne .checkFlags
cmp BYTE [si + HFSPlusExtentKey.forkType], kForkTypeData
jne .checkFlags
mov eax, [si + HFSPlusExtentKey.startBlock]
cmp eax, [di + HFSPlusExtentKey.startBlock]
je compareHFSPlusCatalogKeys.exit
.checkFlags:
ja compareHFSPlusCatalogKeys.searchKeyGreater ; search key > trial key
jb compareHFSPlusCatalogKeys.trialKeyGreater ; search key < trial key
;--------------------------------------------------------------------------
; Compare HFSPlusCatalogKey structures
;
; Arguments:
; DS:SI = search key
; ES:DI = trial key
;
; Returns:
; [BTree.searchResult] = result
; FLAGS = relation between search and trial keys
;
compareHFSPlusCatalogKeys:
pushad
xor dx, dx ; DL = result of comparison, DH = bestGuess
xchg si, di
lodsd
mov ecx, eax ; ECX = trial parentID
xchg si, di
lodsd ; EAX = search parentID
cmp eax, ecx
ja .searchKeyGreater ; search parentID > trial parentID
jb .trialKeyGreater ; search parentID < trial parentID
.compareNodeName: ; search parentID = trial parentID
xchg si, di
lodsw
mov cx, ax ; CX = trial nodeName.length
xchg si, di
lodsw ; AX = search nodeName.length
cmp cl, 0 ; trial nodeName.length = 0?
je .searchKeyGreater
cmp ax, cx
je .strCompare
ja .searchStrLonger
.trialStrLonger:
dec dh
mov cx, ax
jmp .strCompare
.searchStrLonger:
inc dh
.strCompare:
repe cmpsw
ja .searchKeyGreater
jb .trialKeyGreater
mov dl, dh
jmp .exit
.trialKeyGreater:
dec dl
jmp .exit
.searchKeyGreater:
inc dl
.exit:
mov [bp + BTree.searchResult], dl
cmp dl, 0 ; set flags to check relation between keys
popad
ret
;--------------------------------------------------------------------------
; Allocate memory
;
; Arguments:
; CX = size of requested memory
;
; Returns:
; BP = start address of allocated memory
;
; Clobber list:
; CX
;
malloc:
push ax ; save AX
push di ; save DI
mov di, [gMallocPtr] ; start address of free space
push di ; save free space start address
inc di ;
inc di ; keep the first word untouched
dec cx ; for the last memory block pointer.
dec cx ;
mov al, NULL ; fill with zero
rep stosb ; repeat fill
mov [gMallocPtr], di ; adjust free space pointer
pop bp ; BP = start address of allocated memory
mov [di], bp ; set start address of allocated memory at next
; allocation block's free space address.
pop di ; restore DI
pop ax ; restore AX
ret
%if UNUSED
;--------------------------------------------------------------------------
; Free allocated memory
;
; Returns:
; BP = start address of previously allocated memory
;
free:
lea bp, [gMallocPtr]
mov bp, [bp]
mov [gMallocPtr], bp
ret
%endif ; UNUSED
;--------------------------------------------------------------------------
; Static data.
;
%if VERBOSE
root_str db '/boot', NULL
%endif
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized sector with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
;
; Sector 1 code area
;
;--------------------------------------------------------------------------
; lookUpBTree - initializes a new BTree instance and
; look up for HFSPlus Catalog File or Extent Overflow keys
;
; Arguments:
; AL = kHFSPlusFileID (Catalog or Extents Overflow)
; SI = address of searchKey
; DI = address of HFSPlusForkData.extents
;
; Returns:
; BP = address of BTree instance
; ECX = rootNode's logical offset in sectors
;
lookUpBTree:
mov cx, BTree_size ; allocate memory with BTree_size
call malloc ; BP = start address of allocated memory.
mov [bp + BTree.fileID], al ; save fileFileID
mov edx, [di] ; first extent of current file
call blockToSector ; ECX = converted to sector unit
mov al, 1 ; 1 sector is enough for
xor edx, edx ; reading current file's header.
lea dx, [bp + BTree.BTHeaderBuffer] ; load into BTreeHeaderBuffer
call readLBA ; read
mov ax, [bp + BTree.BTHeaderBuffer + BTNodeDescriptor_size + BTHeaderRec.nodeSize]
xchg ah, al ; convert to little-endian
mov [bp + BTree.nodeSize], ax ; save nodeSize
;
; Always start the lookup process with the root node.
;
mov edx, [bp + BTree.BTHeaderBuffer + BTNodeDescriptor_size + BTHeaderRec.rootNode]
.readNode:
;
; Converting nodeID to sector unit
;
mov ax, [bp + BTree.nodeSize]
shr ax, 9 ; convert nodeSize to sectors
mov bx, ax ; BX = read sector count
cwde
bswap edx ; convert node ID to little-endian
mul edx ; multiply with nodeSize converted to sector unit
mov ecx, eax ; ECX = file offset in BTree
mov eax, [bp + BTree.fileID]
lea edx, [bp + BTree.nodeBuffer]
call readExtent
;
; AX = lowerBound = 0
;
xor ax, ax
;
; BX = upperBound = numRecords - 1
;
mov bx, [bp + BTree.nodeBuffer + BTNodeDescriptor.numRecords]
xchg bh, bl
dec bx
.bsearch:
cmp ax, bx
ja .checkResult ; jump if lowerBound > upperBound
mov cx, ax
add cx, bx
shr cx, 1 ; test index = (lowerBound + upperBound / 2)
call getBTreeRecord
%if UNUSED
pushad
jl .csearchLessThanTrial
jg .csearchGreaterThanTrial
PrintChar('=')
jmp .csearchCont
.csearchGreaterThanTrial:
PrintChar('>')
jmp .csearchCont
.csearchLessThanTrial:
PrintChar('<')
.csearchCont:
popad
%endif ; UNUSED
.adjustBounds:
je .checkResult
jl .searchLessThanTrial
jg .searchGreaterThanTrial
jmp .bsearch
.searchLessThanTrial:
mov bx, cx
dec bx ; upperBound = index - 1
jmp .bsearch
.searchGreaterThanTrial:
mov ax, cx
inc ax ; lowerBound = index + 1
jmp .bsearch
.checkResult:
cmp BYTE [bp + BTree.searchResult], 0
jge .foundKey
mov cx, bx
call getBTreeRecord
.foundKey:
cmp BYTE [bp + BTree.nodeBuffer + BTNodeDescriptor.kind], kBTIndexNode
jne .exit
lea bx, [bp + BTree.recordDataPtr]
mov bx, [bx]
mov edx, [bx]
jmp .readNode
.exit:
cmp BYTE [bp + BTree.searchResult], 0
ret
;--------------------------------------------------------------------------
; getBTreeRecord - read and compare BTree record
;
; Arguments:
; CX = record index
; SI = address of search key
;
; Returns:
; [BTree.searchResult] = result of key compare
; [BTree.recordDataPtr] = address of record data
;
getBTreeRecord:
pushad
push si ; save SI
lea di, [bp + BTree.nodeBuffer] ; DI = start of nodeBuffer
push di ; use later
mov ax, [bp + BTree.nodeSize] ; get nodeSize
add di, ax ; DI = beyond nodeBuffer
inc cx ; increment index
shl cx, 1 ; * 2
sub di, cx ; DI = pointer to record
mov ax, [di] ; offset to record
xchg ah, al ; convert to little-endian
pop di ; start of nodeBuffer
add di, ax ; DI = address of record key
mov si, di ; save to SI
mov ax, [di] ; keyLength
xchg ah, al ; convert to little-endian
inc ax ; suppress keySize (2 bytes)
inc ax ;
add di, ax ; DI = address of record data
mov [bp + BTree.recordDataPtr], di ; save address of record data
lea di, [bp + BTree.trialKey]
push di ; save address of trialKey
lodsw ; suppress keySize (2 bytes)
;
; Don't need to compare as DWORD since all reserved CNIDs fits to a single byte
;
cmp BYTE [bp + BTree.fileID], kHFSCatalogFileID
je .prepareTrialCatalogKey
.prepareTrialExtentKey:
mov bx, compareHFSPlusExtentKeys
movsw ; copy forkType + pad
mov cx, 2 ; copy fileID + startBlock
.extentLoop:
lodsd
bswap eax ; convert to little-endian
stosd
loop .extentLoop
jmp .exit
.prepareTrialCatalogKey:
mov bx, compareHFSPlusCatalogKeys
lodsd
bswap eax ; convert ParentID to little-endian
stosd
call ConvertHFSUniStr255ToLE ; convert nodeName to little-endian
.exit:
pop di ; restore address of trialKey
%if UNUSED
;
; Print catalog trial key
;
pushad
mov si, di
lodsd
PrintChar('k')
PrintHex()
lodsw
cmp ax, 0
je .printExit
mov cx, ax
.printLoop:
lodsw
call print_char
loop .printLoop
.printExit:
popad
;
;
;
%endif ; UNUSED
%if UNUSED
;
; Print extent trial key
;
pushad
PrintChar('k')
mov si, di
xor eax, eax
lodsw
PrintHex()
lodsd
PrintHex()
lodsd
PrintHex()
popad
;
;
;
%endif ; UNUSED
pop si ; restore SI
call bx ; call key compare proc
popad
ret
;--------------------------------------------------------------------------
; readExtent - read extents from a HFS+ file (multiple extent support)
;
; Arguments:
; EAX = Catalog File ID
; BX = read size in sectors
; ECX = file offset in sectors
; EDX = address of read buffer
; DI = address of HFSPlusForkData.extents
;
readExtent:
pushad
;
; Save Catalog File ID as part of a search HFSPlusExtentKey
; for a possible Extents Overflow lookup.
;
mov [bp + BTree.searchExtentKey + HFSPlusExtentKey.fileID], eax
mov [bp + BTree.readBufferPtr], edx
mov ax, bx
cwde
mov [bp + BTree.readSize], eax
mov ebx, ecx ; EBX = file offset
xor eax, eax
mov [bp + BTree.currentExtentOffs], eax
.beginExtentBlock:
mov BYTE [bp + BTree.extentCount], 0
.extentSearch:
cmp BYTE [bp + BTree.extentCount], kHFSPlusExtentDensity
jb .continue
.getNextExtentBlock:
push ebx
mov eax, [bp + BTree.currentExtentOffs]
;
; Converting sector unit to HFS+ allocation block unit.
;
xor edx, edx
div DWORD [gBlockSize] ; divide with blockSize
;
; Preparing searchExtentKey's startBlock field.
;
mov [bp + BTree.searchExtentKey + HFSPlusExtentKey.startBlock], eax
mov al, kHFSExtentsFileID
lea si, [bp + BTree.searchExtentKey]
lea di, [kHFSPlusBuffer + HFSPlusVolumeHeader.extentsFile + HFSPlusForkData.extents]
call lookUpBTree
jnz NEAR .exit
;
; BP points to the new workspace allocated by lookUpBTree.
;
lea di, [bp + BTree.recordDataPtr]
mov di, [di]
;
; Switch back to the previous workspace.
;
lea bp, [gMallocPtr]
mov bp, [bp]
mov [gMallocPtr], bp
pop ebx
jmp .beginExtentBlock
.continue:
mov edx, [di + HFSPlusExtentDescriptor.blockCount]
call blockToSector ; ECX = converted current extent's blockCount to sectors
mov eax, [bp + BTree.currentExtentOffs] ; EAX = current extent's start offset (sector)
mov edx, eax
add edx, ecx ; EDX = next extent's start offset (sector)
cmp ebx, edx
mov [bp + BTree.currentExtentOffs], edx ; set currentExtentOffs as the next extent's start offset
jae .nextExtent ; jump to next extent if file offset > next extent's start offset
.foundExtent:
mov edx, ebx
sub edx, eax ; EDX = relative offset within current extent
mov eax, edx ; will be used below to determine read size
mov esi, [bp + BTree.readSize] ; ESI = remaining sectors to be read
add edx, esi
cmp edx, ecx ; test if relative offset + readSize fits to this extent
jbe .read ; read all remaining sectors from this extent
.splitRead:
sub ecx, eax ; read amount of sectors beginning at relative offset
mov esi, ecx ; of current extent up to the end of current extent
.read:
mov edx, [di + HFSPlusExtentDescriptor.startBlock]
call blockToSector ; ECX = converted to sectors
add ecx, eax ; file offset converted to sectors
push si
mov ax, si
mov edx, [bp + BTree.readBufferPtr]
call readSectors
pop si
add ebx, esi
mov ax, si
cwde
shl ax, 9 ; convert SI (read sector count) to byte unit
add [bp + BTree.readBufferPtr], eax
sub [bp + BTree.readSize], esi
jz .exit
.nextExtent:
add di, kHFSPlusExtentDensity
inc BYTE [bp + BTree.extentCount]
jmp .extentSearch
.exit:
popad
ret
;--------------------------------------------------------------------------
; Convert big-endian HFSPlus allocation block to sector unit
;
; Arguments:
; EDX = allocation block
;
; Returns:
; ECX = allocation block converted to sector unit
;
; Clobber list:
; EDX
;
blockToSector:
push eax
mov eax, [gBlockSize]
bswap edx ; convert allocation block to little-endian
mul edx ; multiply with block number
mov ecx, eax ; result in EAX
pop eax
ret
%if UNUSED
;--------------------------------------------------------------------------
; Convert sector unit to HFSPlus allocation block unit
;
; Arguments:
; EDX = sector
;
; Returns:
; ECX = converted to allocation block unit
;
; Clobber list:
; EDX
;
sectorToBlock:
push eax
mov eax, edx
xor edx, edx
div DWORD [gBlockSize] ; divide with blockSize
mov ecx, eax ; result in EAX
pop eax
ret
%endif ; UNUSED
%if UNUSED
;--------------------------------------------------------------------------
; Convert big-endian BTree node ID to sector unit
;
; Arguments:
; EDX = node ID
;
; Returns:
; ECX = node ID converted to sector unit
;
; Clobber list:
; EDX
;
nodeToSector:
push eax
mov ax, [bp + BTree.nodeSize]
shr ax, 9 ; convert nodeSize to sectors
cwde
bswap edx ; convert node ID to little-endian
mul edx ; multiply with node ID
mov ecx, eax ; result in EAX
pop eax
ret
%endif ; UNUSED
;--------------------------------------------------------------------------
; Static data.
;
%if VERBOSE
log_title_str db CR, LF, 'boot1: ', NULL
error_str db 'error', NULL
%endif
searchCatalogKey dd kHFSRootFolderID
searchCatalogKeyNL dw searchCatKeyNameLen
searchCatKeyName dw 'b', 'o', 'o', 't', 'x' ; must be lower case
searchCatKeyNameLen EQU ($ - searchCatKeyName) / 2
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized sector with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
pad_sector_1:
times 1022-($-$$) db 0
dw kBootSignature
;
; Local BTree variables
;
struc BTree
.mallocLink resw 1 ; pointer to previously allocated memory block
.fileID resd 1 ; will use as BYTE
.nodeSize resd 1 ; will use as WORD
.searchExtentKey resb HFSPlusExtentKey_size
.searchResult resb 1
.trialKey resb kBTMaxRecordLength
.recordDataPtr resw 1
.readBufferPtr resd 1
.currentExtentOffs resd 1
.readSize resd 1
.extentCount resb 1
ALIGNB 2
.BTHeaderBuffer resb kSectorBytes
.nodeBuffer resb maxNodeSize
endstruc
;
; Global variables
;
ABSOLUTE kHFSPlusBuffer + HFSPlusVolumeHeader_size
gPartLBA resd 1
gBIOSDriveNumber resw 1
gBlockSize resd 1
gMallocPtr resw 1
; END
|
al3xtjames/Clover
| 14,403
|
BootHFS/boot1f32.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Partition Boot Loader: boot1f32
;
; This program is designed to reside in sector 0 of a FAT32 partition.
; It expects that the MBR has left the drive number in DL
; and a pointer to the partition entry in SI.
;
; This version requires a BIOS with EBIOS (LBA) support.
;
; This code is written for the NASM assembler.
; nasm boot1f32.s -o boot1f32
;
; dd if=origbs of=newbs skip=3 seek=3 bs=1 count=87 conv=notrunc
;
;
; This version of boot1f32 tries to find a stage2 boot file in the root folder.
;
; Written by mackerintel on 2009-01-26
;
;
; Set to 1 to enable obscure debug messages.
;
DEBUG EQU 0
;
; Set to 1 to enable unused code.
;
UNUSED EQU 0
;
; Set to 1 to enable verbose mode.
;
VERBOSE EQU 0
;
; Set to 1 to make this stage 1 loader expecting arguments in SI and DL registers.
;
USESIDL EQU 1
;
; Various constants.
;
NULL EQU 0
CR EQU 0x0D
LF EQU 0x0A
maxSectorCount EQU 64 ; maximum sector count for readSectors
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kBoot1StackAddress EQU 0xFFF0 ; boot1 stack pointer
kBoot1LoadAddr EQU 0x7C00 ; boot1 load address
kBoot1RelocAddr EQU 0xE000 ; boot1 relocated address
kBoot2Sectors EQU (480 * 1024 - 512) / kSectorBytes ; max size of 'boot' file in sectors
kBoot2Segment EQU 0x2000 ; boot2 load segment
kBoot2Address EQU kSectorBytes ; boot2 load address
FATBUF EQU 0x7000 ; Just place for one sectors
DIRBUFSEG EQU 0x1000 ; Cluster sizes >64KB aren't supported
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
struc direntry
.nameext resb 11
.attr resb 1
.nused1 resb 8
.highclus resw 1
.nused2 resb 4
.lowclus resw 1
.size resd 1
endstruc
;
; Macros.
;
%macro jmpabs 1
push WORD %1
ret
%endmacro
%macro DebugCharMacro 1
pushad
mov al, %1
call print_char
call getc
popad
%endmacro
%macro PrintCharMacro 1
pushad
mov al, %1
call print_char
popad
%endmacro
%macro PutCharMacro 1
call print_char
%endmacro
%macro PrintHexMacro 1
call print_hex
%endmacro
%macro PrintString 1
mov si, %1
call print_string
%endmacro
%macro LogString 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%define PrintChar(x) PrintCharMacro x
%define PutChar(x) PutCharMacro
%define PrintHex(x) PrintHexMacro x
%else
%define DebugChar(x)
%define PrintChar(x)
%define PutChar(x)
%define PrintHex(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot1LoadAddr
jmp start
times 3-($-$$) nop
gOEMName times 8 db 0 ;OEMNAME
gBPS dw 0
gSPC db 0
gReservedSectors dw 0
gNumFats db 0
gCrap1 times 11 db 0
gPartLBA dd 0
gPartSize dd 0
gSectPerFat dd 0
gCrap2 times 4 db 0
gRootCluster dd 0
gCrap3 times 16 db 0
gBIOSDriveNumber db 0
gExtInfo times 25 db 0
gFileName db "BOOT " ; Used as a magic string in boot0
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; set up the stack to grow down from kBoot1StackSegment:kBoot1StackAddress.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor eax, eax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot1StackAddress ; sp <- top of stack
sti ; reenable interrupts
mov ds, ax ; ds <- 0
mov es, ax ; es <- 0
;
; Initializing global variables.
;
mov ax, word [gReservedSectors]
%if USESIDL
add eax, [si + part.lba]
%else
add eax, [gPartLBA]
%endif
mov [gPartLBA], eax ; save the current FAT LBA offset
%if USESIDL
mov [gBIOSDriveNumber], dl ; save BIOS drive number
%endif
xor eax,eax
mov al, [gNumFats]
mul dword [gSectPerFat]
mov [gSectPerFat], eax
;--------------------------------------------------------------------------
; Find stage2 boot file in a FAT32 Volume's root folder.
;
findRootBoot:
%if VERBOSE
LogString(init_str)
%endif
mov eax, [gRootCluster]
nextdirclus:
mov edx, DIRBUFSEG<<4
call readCluster
jc error
xor si, si
mov bl, [gSPC]
shl bx, 9
add bx, si
nextdirent:
mov di, gFileName
push ds
push DIRBUFSEG
pop ds
mov cl, [si]
test cl, cl
jz dserror
mov cx, 11
repe cmpsb
jz direntfound
falsealert:
pop ds
add cl, 21
add si, cx
cmp si, bx
jz nextdirclus
jmp nextdirent
direntfound:
; test byte [ds:si+direntry.attr-11], 0x18
lodsb
test al, 0x18
jnz falsealert
push WORD [si + direntry.highclus - 12]
push WORD [si + direntry.lowclus - 12]
pop eax
pop ds
mov edx, (kBoot2Segment << 4) + kBoot2Address
cont_read:
push edx
call readCluster
pop edx
pushf
xor ebx,ebx
mov bl, [gSPC]
shl ebx, 9
add edx, ebx
popf
jnc cont_read
boot2:
%if DEBUG
DebugChar ('!')
%endif
%if UNUSED
;
; Waiting for a key press.
;
mov ah, 0
int 0x16
%endif
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
jmp kBoot2Segment:kBoot2Address
dserror:
pop ds
error:
%if VERBOSE
LogString(error_str)
%endif
hang:
hlt
jmp hang
; readCluster - Reads cluster EAX to (EDX), updates EAX to next cluster
readCluster:
cmp eax, 0x0ffffff8
jb do_read
stc
ret
do_read:
push eax
xor ecx,ecx
dec eax
dec eax
mov cl, [gSPC]
push edx
mul ecx
pop edx
add eax, [gSectPerFat]
mov ecx, eax
xor ah,ah
mov al, [gSPC]
call readSectors
jc clusend
pop ecx
push cx
shr ecx, 7
xor ax, ax
inc ax
mov edx, FATBUF
call readSectors
jc clusend
pop si
and si, 0x7f
shl si, 2
mov eax, [FATBUF + si]
and eax, 0x0fffffff
clc
ret
clusend:
pop eax
ret
;--------------------------------------------------------------------------
; readSectors - Reads more than 127 sectors using LBA addressing.
;
; Arguments:
; AX = number of 512-byte sectors to read (valid from 1-1280).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
;
; Returns:
; CF = 0 success
; 1 error
;
readSectors:
pushad
mov bx, ax
.loop:
xor eax, eax ; EAX = 0
mov al, bl ; assume we reached the last block.
cmp bx, maxSectorCount ; check if we really reached the last block
jb .readBlock ; yes, BX < MaxSectorCount
mov al, maxSectorCount ; no, read MaxSectorCount
.readBlock:
call readLBA
sub bx, ax ; decrease remaning sectors with the read amount
jz .exit ; exit if no more sectors left to be loaded
add ecx, eax ; adjust LBA sector offset
shl ax, 9 ; convert sectors to bytes
add edx, eax ; adjust target memory location
jmp .loop ; read remaining sectors
.exit:
popad
ret
;--------------------------------------------------------------------------
; readLBA - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
; [bios_drive_number] = drive number (0x80 + unit number)
;
; Returns:
; CF = 0 success
; 1 error
;
readLBA:
pushad ; save all registers
push es ; save ES
mov bp, sp ; save current SP
;
; Convert EDX to segment:offset model and set ES:BX
;
; Some BIOSes do not like offset to be negative while reading
; from hard drives. This usually leads to "boot1: error" when trying
; to boot from hard drive, while booting normally from USB flash.
; The routines, responsible for this are apparently different.
; Thus we split linear address slightly differently for these
; capricious BIOSes to make sure offset is always positive.
;
mov bx, dx ; save offset to BX
and bh, 0x0f ; keep low 12 bits
shr edx, 4 ; adjust linear address to segment base
xor dl, dl ; mask low 8 bits
mov es, dx ; save segment to ES
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
add ecx, [gPartLBA] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
push WORD 16 ; offset 0-1, packet size
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; [bios_drive_number] = drive number (0x80 + unit number)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
mov si, sp
mov ah, 0x42
int 0x13
jc error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
; xor ax, ax ; Func 0
; int 0x13 ; INT 13
; stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
pop es ; restore ES
popad
ret
%if VERBOSE
;--------------------------------------------------------------------------
; Write a string with 'boot1: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pushad
push di
mov si, log_title_str
call print_string
pop si
call print_string
popad
ret
;-------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp .loop
.exit:
ret
%endif ; VERBOSE
%if DEBUG
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
%if UNUSED
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
%endif ; UNUSED
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
;--------------------------------------------------------------------------
; getc - wait for a key press
;
getc:
pushad
mov ah, 0
int 0x16
popad
ret
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pushad
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popad
ret
%endif ; DEBUG
;--------------------------------------------------------------------------
; Static data.
;
%if VERBOSE
log_title_str db CR, LF, 'b1f: ', NULL
init_str db 'init', NULL
error_str db 'error', NULL
%endif
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized sector with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
ABSOLUTE kBoot1LoadAddr + kSectorBytes
; END
|
al3xtjames/Clover
| 26,384
|
BootHFS/boot0md.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Boot Loader: boot0
;
; A small boot sector program written in x86 assembly whose only
; responsibility is to locate the active partition, load the
; partition booter into memory, and jump to the booter's entry point.
; It leaves the boot drive in DL and a pointer to the partition entry in SI.
;
; This boot loader must be placed in the Master Boot Record.
;
; In order to coexist with a fdisk partition table (64 bytes), and
; leave room for a two byte signature (0xAA55) in the end, boot0 is
; restricted to 446 bytes (512 - 64 - 2). If boot0 did not have to
; live in the MBR, then we would have 510 bytes to work with.
;
; boot0 is always loaded by the BIOS or another booter to 0:7C00h.
;
; This code is written for the NASM assembler.
; nasm boot0.s -o boot0
;
; This version of boot0 implements hybrid GUID/MBR partition scheme support
;
; Written by Tams Kosrszky on 2008-03-10
;
; Turbo added EFI System Partition boot support
;
; Added KillerJK's switchPass2 modifications
;
; dmazar: 10/7/2011 added scanning of all BIOS accessible drives:
; - iterates over all drives and searches for HSF bootable partition (with boot1h)
; and loads from it
; - if not found, itarates over drives again and searches for active partition and
; loads from it
;
; dmazar: 19/7/2011
; Searching for bootable partition works in 3 passes now:
;
; - Pass1:
; - for the boot drive only:
; - searches MBR partition table for an active HSF+ bootable partition and boots it
; - if not found and disk is actually GPT, then searches for the first HFS+ bootable
; partition (or EFI with boot1f32) in the GPT array and boots it
; - if still not found, then continues with Pass2
;
; - Pass2:
; - iterates over all drives and for each drive:
; - searches MBR partition table for the first HSF+ bootable partition and boots it
; - if not found and disk is actually GPT, then searches for the first HFS+ bootable
; partition (or EFI with boot1f32) in the GPT array and boots it
; - if still not found, then continues with the next drive
; - if all drives are searched and nothing found, then continues with Pass3
; - Pass3:
; - iterates over all drives and for each drive:
; - searches MBR partition table for the first active bootable partition and boots it
; - if not found and disk is actually GPT, then searches for the first HFS+ bootable
; partition (or EFI with boot1f32) in the GPT and boots it
; - if still not found, then continues with the next drive
; - if all drives are searched and nothing found, finishes with "boot0: error"
;
; Bootable partition above means a partition with the boot sector signature (0xAA55)
; at the end of the partition boot sector.
; Booting partition means loading partition boot sector and passing control to partition
; boot loader (for example boot1h).
; Drives are searched in the order defined in the BIOS. Drive which is selected as the boot drive
; is searched first.
;
; If compiled with DEBUG=1 gives debug output:
; P - starting new pass
; D - starting disk scanning: MBR and then GPT
; p - checking MBR partition entry
; t - testing MBR partition
; l - MBR or GPT partition satisfies conditions - loading partition boot sector
; G - found GPT
; + - stage 1 booter loaded, press a key to continue
; E - error
;
;
; Set to 1 to enable obscure debug messages.
;
;DEBUG EQU CONFIG_BOOT0_DEBUG
DEBUG EQU 0
NOT_USED EQU 0 ; exclude print_hex - no space for it
;
; Verbose - write boot0 messages
; No space for verbose and debug in the same time
;
;VERBOSE EQU CONFIG_BOOT0_VERBOSE
%if DEBUG
VERBOSE EQU 0
%else
VERBOSE EQU 1
%endif
;
; Various constants.
;
kBoot0Segment EQU 0x0000
kBoot0Stack EQU 0xFFF0 ; boot0 stack pointer
kBoot0LoadAddr EQU 0x7C00 ; boot0 load address
kBoot0RelocAddr EQU 0xE000 ; boot0 relocated address
kMBRBuffer EQU 0x1000 ; MBR buffer address
kLBA1Buffer EQU 0x1200 ; LBA1 - GPT Partition Table Header buffer address
kGPTABuffer EQU 0x1400 ; GUID Partition Entry Array buffer address
kPartTableOffset EQU 0x1be
kMBRPartTable EQU kMBRBuffer + kPartTableOffset
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kHFSPSignature EQU 'H+' ; HFS+ volume signature
kHFSPCaseSignature EQU 'HX' ; HFS+ volume case-sensitive signature
kFAT32BootCodeOffset EQU 0x5a ; offset of boot code in FAT32 boot sector
kBoot1FAT32Magic EQU 'BO' ; Magic string to detect our boot1f32 code
kGPTSignatureLow EQU 'EFI ' ; GUID Partition Table Header Signature
kGPTSignatureHigh EQU 'PART'
kGUIDLastDwordOffs EQU 12 ; last 4 byte offset of a GUID
kPartCount EQU 4 ; number of paritions per table
kPartTypeHFS EQU 0xaf ; HFS+ Filesystem type
kPartTypePMBR EQU 0xee ; On all GUID Partition Table disks a Protective MBR (PMBR)
; in LBA 0 (that is, the first block) precedes the
; GUID Partition Table Header to maintain compatibility
; with existing tools that do not understand GPT partition structures.
; The Protective MBR has the same format as a legacy MBR
; and contains one partition entry with an OSType set to 0xEE
; reserving the entire space used on the disk by the GPT partitions,
; including all headers.
kPartActive EQU 0x80 ; active flag enabled
kPartInactive EQU 0x00 ; active flag disabled
kHFSGUID EQU 0x48465300 ; first 4 bytes of Apple HFS Partition Type GUID.
kAppleGUID EQU 0xACEC4365 ; last 4 bytes of Apple type GUIDs.
kEFISystemGUID EQU 0x3BC93EC9 ; last 4 bytes of EFI System Partition Type GUID:
; C12A7328-F81F-11D2-BA4B-00A0C93EC93B
%ifdef FLOPPY
kDriveNumber EQU 0x00
%else
kDriveNumber EQU 0x80
%endif
kPass1 EQU 3 ; Pass1
kPass2 EQU 2 ; Pass2
kPass3 EQU 1 ; Pass3
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
;
; Format of GPT Partition Table Header
;
struc gpth
.Signature resb 8
.Revision resb 4
.HeaderSize resb 4
.HeaderCRC32 resb 4
.Reserved resb 4
.MyLBA resb 8
.AlternateLBA resb 8
.FirstUsableLBA resb 8
.LastUsableLBA resb 8
.DiskGUID resb 16
.PartitionEntryLBA resb 8
.NumberOfPartitionEntries resb 4
.SizeOfPartitionEntry resb 4
.PartitionEntryArrayCRC32 resb 4
endstruc
;
; Format of GUID Partition Entry Array
;
struc gpta
.PartitionTypeGUID resb 16
.UniquePartitionGUID resb 16
.StartingLBA resb 8
.EndingLBA resb 8
.Attributes resb 8
.PartitionName resb 72
endstruc
;
; Macros.
;
%macro DebugCharMacro 1
mov al, %1
call print_char
%endmacro
%macro DebugPauseMacro 0
call getc
%endmacro
%macro LogStringMacro 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%define DebugPause DebugPauseMacro
%else
%define DebugChar(x)
%define DebugPause
%endif
%if VERBOSE
%define LogString(x) LogStringMacro x
%else
%define LogString(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot0RelocAddr
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; Set up the stack to grow down from kBoot0Segment:kBoot0Stack.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor ax, ax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot0Stack ; sp <- top of stack
sti ; reenable interrupts
mov es, ax ; es <- 0
mov ds, ax ; ds <- 0
;
; Relocate boot0 code.
;
mov si, kBoot0LoadAddr ; si <- source
mov di, kBoot0RelocAddr ; di <- destination
cld ; auto-increment SI and/or DI registers
mov cx, kSectorBytes/2 ; copy 256 words
repnz movsw ; repeat string move (word) operation
;
; Code relocated, jump to start_reloc in relocated location.
;
jmp kBoot0Segment:start_reloc
;--------------------------------------------------------------------------
; Start execution from the relocated location.
;
start_reloc:
;
; BH is pass counter
; Pass1 BH=3, Pass2 BH=2, Pass3 BH=1
;
mov bh, kPass1 ; BH = 3. Pass1
pass_loop:
DebugChar('P') ; starting new pass
push dx ; save dl (boot drive) for next pass
.scan_drive:
;
; Since this code may not always reside in the MBR, always start by
; loading the MBR to kMBRBuffer and LBA1 to kGPTBuffer.
;
push bx ; save BH (scan pass counter)
xor eax, eax
mov [my_lba], eax ; store LBA sector 0 for read_lba function
mov al, 2 ; load two sectors: MBR and LBA1
mov bx, kMBRBuffer ; MBR load address
call load
pop bx ; restore BH
jc .next_pass ; MBR load error - normally because we scanned all drives
DebugChar('D') ; starting disk scanning
;
; Look for the booter partition in the MBR partition table,
; which is at offset kMBRPartTable.
;
mov si, kMBRPartTable ; pointer to partition table
call find_boot ; will not return on success
; if returns - booter partition is not found
; skip scanning of all drives in Pass1
cmp bh, kPass1
je .next_pass
; try next drive
; if next drive does not exists - will break on the MBR load error above
inc dl
jmp short .scan_drive
.next_pass:
; all drives scanned - move to next pass
pop dx ; restore orig boot drive
dec bh ; decrement scan pass counter
jnz pass_loop ; if not zero - exec next pass
; we ran all passes - nothing found - error
error:
DebugChar('E')
DebugPause
LogString(boot_error_str)
hang:
hlt
jmp short hang
;--------------------------------------------------------------------------
; Find the active (boot) partition and load the booter from the partition.
;
; Arguments:
; DL = drive number (0x80 + unit number)
; SI = pointer to fdisk partition table.
; BH = pass counter
;
; Clobber list:
; EAX, BX, EBP
;
find_boot:
;
; Check for boot block signature 0xAA55 following the 4 partition
; entries.
;
cmp WORD [si + part_size * kPartCount], kBootSignature
jne .exit ; boot signature not found.
xor bl, bl ; BL will be set to 1 later in case of
; Protective MBR has been found
.start_scan:
mov cx, kPartCount ; number of partition entries per table
.loop:
DebugChar('p') ; checking partition entry
mov eax, [si + part.lba] ; save starting LBA of current
mov [my_lba], eax ; MBR partition entry for read_lba function
cmp BYTE [si + part.type], 0 ; unused partition?
je .continue ; skip to next entry
cmp BYTE [si + part.type], kPartTypePMBR ; check for Protective MBR
jne .testPass
mov BYTE [si + part.bootid], kPartInactive ; found Protective MBR
; clear active flag to make sure this protective
; partition won't be used as a bootable partition.
mov bl, 1 ; Assume we can deal with GPT but try to scan
; later if not found any other bootable partitions.
;
; The following code between .testPass and .tryToBoot performs checking for 3 passes:
; Pass1 (BH=3) if (partition is HFS+ and active) then { DH=1; call loadBootSector}
; Pass2 (BH=2) if (partition is HFS+) then { DH=1; call loadBootSector}
; Pass3 (BH=1) if (partition is active) then { DH=0; call loadBootSector}
;
; BH is Pass counter
; DH is argument to loadBootSector
; = 0 - skip HFS+ partition signature check
; = 1 - check for HFS+ partition signature
;
; Code may be harder to read because I tried to optimized it for minimum size.
;
.testPass:
DebugChar('t') ; testing partition
xor dh, dh ; DH=0 This will be used in Pass3 (partition is active, not HFS+).
cmp bh, kPass3 ; If this is Pass3 (BH=1)
je .checkActive ; check for active flag only.
.checkHFS:
; We are in Pass1 (BH=3) or Pass2 (BH=2).
inc dh ; DH=1
cmp BYTE [si + part.type], kPartTypeHFS ; Check for a HFS+ partition.
jne .continue
cmp bh, kPass2 ; It's HFS+. That's enough checking for Pass2,
je .tryToBoot ; so try to boot (with DH=1)
; Pass1 needs active flag check also ...
.checkActive:
; We are in Pass1 or Pass3
cmp BYTE [si + part.bootid], kPartActive ; Check if partition is Active
jne .continue
;
; Found boot partition, read boot sector to memory.
;
.tryToBoot:
call loadBootSector
jne .continue
jmp SHORT initBootLoader
.continue:
add si, BYTE part_size ; advance SI to next partition entry
loop .loop ; loop through all partition entries
;
; Scanned all partitions but not found any with active flag enabled
; Anyway if we found a protective MBR before we still have a chance
; for a possible GPT Header at LBA 1
;
dec bl
jnz .exit ; didn't find Protective MBR before
call checkGPT
.exit:
ret ; Giving up.
;
; Jump to partition booter. The drive number is already in register DL.
; SI is pointing to the modified partition entry.
;
initBootLoader:
DebugChar('+')
DebugPause
LogString(done_str)
jmp kBoot0LoadAddr
;
; Found Protective MBR Partition Type: 0xEE
; Check for 'EFI PART' string at the beginning
; of LBA1 for possible GPT Table Header
;
checkGPT:
push bx
mov di, kLBA1Buffer ; address of GUID Partition Table Header
cmp DWORD [di], kGPTSignatureLow ; looking for 'EFI '
jne .exit ; not found. Giving up.
cmp DWORD [di + 4], kGPTSignatureHigh ; looking for 'PART'
jne .exit ; not found. Giving up indeed.
DebugChar('G') ; found GPT
mov si, di
;
; Loading GUID Partition Table Array
;
mov eax, [si + gpth.PartitionEntryLBA] ; starting LBA of GPT Array
mov [my_lba], eax ; save starting LBA for read_lba function
mov cx, [si + gpth.NumberOfPartitionEntries] ; number of GUID Partition Array entries
mov bx, [si + gpth.SizeOfPartitionEntry] ; size of GUID Partition Array entry
push bx ; push size of GUID Partition entry
;
; Calculating number of sectors we need to read for loading a GPT Array
;
; push dx ; preserve DX (DL = BIOS drive unit number)
; mov ax, cx ; AX * BX = number of entries * size of one entry
; mul bx ; AX = total byte size of GPT Array
; pop dx ; restore DX
; shr ax, 9 ; convert to sectors
;
; ... or:
; Current GPT Arrays uses 128 partition entries each 128 bytes long
; 128 entries * 128 bytes long GPT Array entries / 512 bytes per sector = 32 sectors
;
mov al, 32 ; maximum sector size of GPT Array (hardcoded method)
mov bx, kGPTABuffer
push bx ; push address of GPT Array
call load ; read GPT Array
pop si ; SI = address of GPT Array
pop bx ; BX = size of GUID Partition Array entry
;jc error
jc .exit ; dmazar's change to continue disk scanning if encountering invalid LBA.
;
; Walk through GUID Partition Table Array
; and load boot record from first available HFS+ partition.
;
; If it has boot signature (0xAA55) then jump to it
; otherwise skip to next partition.
;
LogString(gpt_str)
.gpt_loop:
mov eax, [si + gpta.PartitionTypeGUID + kGUIDLastDwordOffs]
cmp eax, kAppleGUID ; check current GUID Partition for Apple's GUID type
je .gpt_ok
;
; Turbo - also try EFI System Partition
;
cmp eax, kEFISystemGUID ; check current GUID Partition for EFI System Partition GUID type
jne .gpt_continue
.gpt_ok:
;
; Found HFS Partition
;
mov eax, [si + gpta.StartingLBA] ; load boot sector from StartingLBA
mov [my_lba], eax
mov dh, 1 ; Argument for loadBootSector to check HFS+ partition signature.
call loadBootSector
jne .gpt_continue ; no boot loader signature
mov si, kMBRPartTable ; fake the current GUID Partition
mov [si + part.lba], eax ; as MBR style partition for boot1h
mov BYTE [si + part.type], kPartTypeHFS ; with HFS+ filesystem type (0xAF)
jmp SHORT initBootLoader
.gpt_continue:
add si, bx ; advance SI to next partition entry
loop .gpt_loop ; loop through all partition entries
.exit:
pop bx
ret ; no more GUID partitions. Giving up.
;--------------------------------------------------------------------------
; loadBootSector - Load boot sector
;
; Arguments:
; DL = drive number (0x80 + unit number)
; DH = 0 skip HFS+ partition signature checking
; 1 enable HFS+ partition signature checking
; [my_lba] = starting LBA.
;
; Returns:
; ZF = 0 if boot sector hasn't kBootSignature
; 1 if boot sector has kBootSignature
;
loadBootSector:
pusha
DebugChar('l') ; loading partition boot sector
mov al, 3
mov bx, kBoot0LoadAddr
call load
;jc error
or dl, dl ; to set flag Z=0 ; dmazar's change to continue disk scanning if encountering invalid LBA.
jc .exit ; dmazar's change to continue disk scanning if encountering invalid LBA.
or dh, dh
jz .checkBootSignature
.checkHFSSignature:
;LogString(test_str) ; dmazar: removed to get space
;
; Looking for HFSPlus ('H+') or HFSPlus case-sensitive ('HX') signature.
;
mov ax, [kBoot0LoadAddr + 2 * kSectorBytes]
cmp ax, kHFSPSignature ; 'H+'
je .checkBootSignature
cmp ax, kHFSPCaseSignature ; 'HX'
je .checkBootSignature
;
; Looking for boot1f32 magic string.
;
mov ax, [kBoot0LoadAddr + kFAT32BootCodeOffset]
cmp ax, kBoot1FAT32Magic
jne .exit
.checkBootSignature:
;
; Check for boot block signature 0xAA55
;
mov di, bx
cmp WORD [di + kSectorBytes - 2], kBootSignature
.exit:
popa
ret
;--------------------------------------------------------------------------
; load - Load one or more sectors from a partition.
;
; Arguments:
; AL = number of 512-byte sectors to read.
; ES:BX = pointer to where the sectors should be stored.
; DL = drive number (0x80 + unit number)
; [my_lba] = starting LBA.
;
; Returns:
; CF = 0 success
; 1 error
;
load:
push cx
.ebios:
mov cx, 5 ; load retry count
.ebios_loop:
call read_lba ; use INT13/F42
jnc .exit
loop .ebios_loop
.exit:
pop cx
ret
;--------------------------------------------------------------------------
; read_lba - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; ES:BX = pointer to where the sectors should be stored.
; DL = drive number (0x80 + unit number)
; [my_lba] = starting LBA.
;
; Returns:
; CF = 0 success
; 1 error
;
read_lba:
pushad ; save all registers
mov bp, sp ; save current SP
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
mov ecx, [my_lba] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
; It pushes 2 bytes with a smaller opcode than if WORD was used
push BYTE 16 ; offset 0-1, packet size
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; DL = drive number (80h + drive unit)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov si, sp
mov ah, 0x42
int 0x13
jnc .exit
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
xor ax, ax ; Func 0
int 0x13 ; INT 13
stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
popad
ret
%if VERBOSE
;--------------------------------------------------------------------------
; Write a string with 'boot0: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pusha
push di
mov si, log_title_str
call print_string
pop si
call print_string
popa
ret
;--------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
cld ; increment SI after each lodsb call
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp short .loop
.exit:
ret
%endif ;VERBOSE
%if DEBUG
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pusha
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popa
ret
getc:
pusha
mov ah, 0
int 0x16
popa
ret
%endif ;DEBUG
%if NOT_USED
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
%endif ; NOT_USED
%if VERBOSE
;--------------------------------------------------------------------------
; NULL terminated strings.
;
log_title_str db 10, 13, 'boot0:', 0
boot_error_str db 'error', 0
gpt_str db 'GPT', 0
;test_str db 'test', 0
done_str db 'done', 0
%endif
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized booter with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
;
; According to EFI specification, maximum boot code size is 440 bytes
;
pad_boot:
times 440-($-$$) db 0
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
ABSOLUTE 0xE400
;
; In memory variables.
;
my_lba resd 1 ; Starting LBA for read_lba function
; END
|
al3xtjames/Clover
| 15,228
|
BootHFS/boot1f32alt.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Partition Boot Loader: boot1f32
;
; This program is designed to reside in sector 0 of a FAT32 partition.
; It expects that the MBR has left the drive number in DL
; and a pointer to the partition entry in SI.
;
; This version requires a BIOS with EBIOS (LBA) support.
;
; This code is written for the NASM assembler.
; nasm boot1f32.s -o boot1f32
;
; dd if=origbs of=newbs skip=3 seek=3 bs=1 count=87 conv=notrunc
;
;
; This version of boot1f32 tries to find a stage2 boot file in the root folder.
;
; Written by mackerintel on 2009-01-26
;
;
; Set to 1 to enable obscure debug messages.
;
DEBUG EQU 0
;
; Set to 1 to enable unused code.
;
UNUSED EQU 0
;
; Set to 1 to enable verbose mode.
;
VERBOSE EQU 0
;
; Set to 1 to make this stage 1 loader expecting arguments in SI and DL registers.
;
USESIDL EQU 1
;
; Various constants.
;
NULL EQU 0
CR EQU 0x0D
LF EQU 0x0A
maxSectorCount EQU 64 ; maximum sector count for readSectors
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kBoot1StackAddress EQU 0xFFF0 ; boot1 stack pointer
kBoot1LoadAddr EQU 0x7C00 ; boot1 load address
kBoot1RelocAddr EQU 0xE000 ; boot1 relocated address
kBoot2Sectors EQU (480 * 1024 - 512) / kSectorBytes ; max size of 'boot' file in sectors
kBoot2Segment EQU 0x2000 ; boot2 load segment
kBoot2Address EQU kSectorBytes ; boot2 load address
FATBUF EQU 0x7000 ; Just place for one sectors
DIRBUFSEG EQU 0x1000 ; Cluster sizes >64KB aren't supported
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
struc direntry
.nameext resb 11
.attr resb 1
.nused1 resb 8
.highclus resw 1
.nused2 resb 4
.lowclus resw 1
.size resd 1
endstruc
;
; Macros.
;
%macro jmpabs 1
push WORD %1
ret
%endmacro
%macro DebugCharMacro 1
pushad
mov al, %1
call print_char
call getc
popad
%endmacro
%macro PrintCharMacro 1
pushad
mov al, %1
call print_char
popad
%endmacro
%macro PutCharMacro 1
call print_char
%endmacro
%macro PrintHexMacro 1
call print_hex
%endmacro
%macro PrintString 1
mov si, %1
call print_string
%endmacro
%macro LogString 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%define PrintChar(x) PrintCharMacro x
%define PutChar(x) PutCharMacro
%define PrintHex(x) PrintHexMacro x
%else
%define DebugChar(x)
%define PrintChar(x)
%define PutChar(x)
%define PrintHex(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot1LoadAddr
jmp start
times 3-($-$$) nop
gOEMName times 8 db 0 ;OEMNAME
gBPS dw 0
gSPC db 0
gReservedSectors dw 0
gNumFats db 0
gCrap1 times 11 db 0
gPartLBA dd 0
gPartSize dd 0
gSectPerFat dd 0
gCrap2 times 4 db 0
gRootCluster dd 0
gCrap3 times 16 db 0
gBIOSDriveNumber db 0
gExtInfo times 25 db 0
gFileName db "BOOT " ; Used as a magic string in boot0
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; set up the stack to grow down from kBoot1StackSegment:kBoot1StackAddress.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor eax, eax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot1StackAddress ; sp <- top of stack
sti ; reenable interrupts
mov ds, ax ; ds <- 0
mov es, ax ; es <- 0
;
; Initializing global variables.
;
mov ax, word [gReservedSectors]
%if USESIDL
add eax, [si + part.lba]
%else
add eax, [gPartLBA]
%endif
mov [gPartLBA], eax ; save the current FAT LBA offset
%if USESIDL
mov [gBIOSDriveNumber], dl ; save BIOS drive number
%endif
xor eax,eax
mov al, [gNumFats]
mul dword [gSectPerFat]
mov [gSectPerFat], eax
;--------------------------------------------------------------------------
; Find stage2 boot file in a FAT32 Volume's root folder.
;
findRootBoot:
setBootFile:
mov cx, 2000 ; loop counter = max 2000 miliseconds in total
.loop:
mov ah, 0x01 ; int 0x16, Func 0x01 - get keyboard status/preview key
int 0x16
jz .wait ; no keypress - wait and loop again
xor ah, ah ; read the char from buffer to spend it
int 0x16
; have a key - ASCII is in al - put it to file name /boot<pressed key>
mov BYTE [gFileName + 4], al
jmp SHORT .bootFileSet ; try to boot
.wait:
; waith for 1 ms: int 0x15, Func 0x86 (wait for cx:dx microseconds)
push cx ; save loop counter
xor cx, cx
mov dx, 1000
mov ah, 0x86
int 0x15
pop cx ; restore loop counter
loop .loop
; no keypress so far
; change filename to /boot by putting space as 5th char
; and try to load
; mov BYTE [gFileName + 4], ' '
.bootFileSet:
%if VERBOSE
LogString(init_str)
%endif
mov eax, [gRootCluster]
nextdirclus:
mov edx, DIRBUFSEG<<4
call readCluster
jc error
xor si, si
mov bl, [gSPC]
shl bx, 9
add bx, si
nextdirent:
mov di, gFileName
push ds
push DIRBUFSEG
pop ds
mov cl, [si]
test cl, cl
jz dserror
mov cx, 11
repe cmpsb
jz direntfound
falsealert:
pop ds
add cl, 21
add si, cx
cmp si, bx
jz nextdirclus
jmp nextdirent
direntfound:
; test byte [ds:si+direntry.attr-11], 0x18
lodsb
test al, 0x18
jnz falsealert
push WORD [si + direntry.highclus - 12]
push WORD [si + direntry.lowclus - 12]
pop eax
pop ds
mov edx, (kBoot2Segment << 4) + kBoot2Address
cont_read:
push edx
call readCluster
pop edx
pushf
xor ebx,ebx
mov bl, [gSPC]
shl ebx, 9
add edx, ebx
popf
jnc cont_read
boot2:
%if DEBUG
DebugChar ('!')
%endif
%if UNUSED
;
; Waiting for a key press.
;
mov ah, 0
int 0x16
%endif
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
jmp kBoot2Segment:kBoot2Address
dserror:
pop ds
error:
%if VERBOSE
LogString(error_str)
%endif
hang:
hlt
jmp hang
; readCluster - Reads cluster EAX to (EDX), updates EAX to next cluster
readCluster:
cmp eax, 0x0ffffff8
jb do_read
stc
ret
do_read:
push eax
xor ecx,ecx
dec eax
dec eax
mov cl, [gSPC]
push edx
mul ecx
pop edx
add eax, [gSectPerFat]
mov ecx, eax
xor ah,ah
mov al, [gSPC]
call readSectors
jc clusend
pop ecx
push cx
shr ecx, 7
xor ax, ax
inc ax
mov edx, FATBUF
call readSectors
jc clusend
pop si
and si, 0x7f
shl si, 2
mov eax, [FATBUF + si]
and eax, 0x0fffffff
clc
ret
clusend:
pop eax
ret
;--------------------------------------------------------------------------
; readSectors - Reads more than 127 sectors using LBA addressing.
;
; Arguments:
; AX = number of 512-byte sectors to read (valid from 1-1280).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
;
; Returns:
; CF = 0 success
; 1 error
;
readSectors:
pushad
mov bx, ax
.loop:
xor eax, eax ; EAX = 0
mov al, bl ; assume we reached the last block.
cmp bx, maxSectorCount ; check if we really reached the last block
jb .readBlock ; yes, BX < MaxSectorCount
mov al, maxSectorCount ; no, read MaxSectorCount
.readBlock:
call readLBA
sub bx, ax ; decrease remaning sectors with the read amount
jz .exit ; exit if no more sectors left to be loaded
add ecx, eax ; adjust LBA sector offset
shl ax, 9 ; convert sectors to bytes
add edx, eax ; adjust target memory location
jmp .loop ; read remaining sectors
.exit:
popad
ret
;--------------------------------------------------------------------------
; readLBA - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
; [bios_drive_number] = drive number (0x80 + unit number)
;
; Returns:
; CF = 0 success
; 1 error
;
readLBA:
pushad ; save all registers
push es ; save ES
mov bp, sp ; save current SP
;
; Convert EDX to segment:offset model and set ES:BX
;
; Some BIOSes do not like offset to be negative while reading
; from hard drives. This usually leads to "boot1: error" when trying
; to boot from hard drive, while booting normally from USB flash.
; The routines, responsible for this are apparently different.
; Thus we split linear address slightly differently for these
; capricious BIOSes to make sure offset is always positive.
;
mov bx, dx ; save offset to BX
and bh, 0x0f ; keep low 12 bits
shr edx, 4 ; adjust linear address to segment base
xor dl, dl ; mask low 8 bits
mov es, dx ; save segment to ES
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
add ecx, [gPartLBA] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
push WORD 16 ; offset 0-1, packet size
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; [bios_drive_number] = drive number (0x80 + unit number)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
mov si, sp
mov ah, 0x42
int 0x13
jc error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
; xor ax, ax ; Func 0
; int 0x13 ; INT 13
; stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
pop es ; restore ES
popad
ret
%if VERBOSE
;--------------------------------------------------------------------------
; Write a string with 'boot1: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pushad
push di
mov si, log_title_str
call print_string
pop si
call print_string
popad
ret
;-------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp .loop
.exit:
ret
%endif ; VERBOSE
%if DEBUG
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
%if UNUSED
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
%endif ; UNUSED
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
;--------------------------------------------------------------------------
; getc - wait for a key press
;
getc:
pushad
mov ah, 0
int 0x16
popad
ret
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pushad
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popad
ret
%endif ; DEBUG
;--------------------------------------------------------------------------
; Static data.
;
%if VERBOSE
log_title_str db CR, LF, 'b1f: ', NULL
init_str db 'init', NULL
error_str db 'error', NULL
%endif
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized sector with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
ABSOLUTE kBoot1LoadAddr + kSectorBytes
; END
|
al3xtjames/Clover
| 35,694
|
BootHFS/boot1h.s
|
; Copyright (c) 1999-2003 Apple Computer, Inc. All rights reserved.
;
; @APPLE_LICENSE_HEADER_START@
;
; Portions Copyright (c) 1999-2003 Apple Computer, Inc. All Rights
; Reserved. This file contains Original Code and/or Modifications of
; Original Code as defined in and that are subject to the Apple Public
; Source License Version 2.0 (the "License"). You may not use this file
; except in compliance with the License. Please obtain a copy of the
; License at http://www.apple.com/publicsource and read it before using
; this file.
;
; The Original Code and all software distributed under the License are
; distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
; EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
; INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE OR NON- INFRINGEMENT. Please see the
; License for the specific language governing rights and limitations
; under the License.
;
; @APPLE_LICENSE_HEADER_END@
;
; Partition Boot Loader: boot1h
;
; This program is designed to reside in sector 0+1 of an HFS+ partition.
; It expects that the MBR has left the drive number in DL
; and a pointer to the partition entry in SI.
;
; This version requires a BIOS with EBIOS (LBA) support.
;
; This code is written for the NASM assembler.
; nasm boot1.s -o boot1h
;
; This version of boot1h tries to find a stage2 boot file in the root folder.
;
; NOTE: this is an experimental version with multiple extent support.
;
; Written by Tams Kosrszky on 2008-04-14
;
;
; Set to 1 to enable obscure debug messages.
;
DEBUG EQU 0
;
; Set to 1 to enable unused code.
;
UNUSED EQU 0
;
; Set to 1 to enable verbose mode.
;
VERBOSE EQU 1
;
; Various constants.
;
NULL EQU 0
CR EQU 0x0D
LF EQU 0x0A
mallocStart EQU 0x1000 ; start address of local workspace area
maxSectorCount EQU 64 ; maximum sector count for readSectors
maxNodeSize EQU 16384
kSectorBytes EQU 512 ; sector size in bytes
kBootSignature EQU 0xAA55 ; boot sector signature
kBoot1StackAddress EQU 0xFFF0 ; boot1 stack pointer
kBoot1LoadAddr EQU 0x7C00 ; boot1 load address
kBoot1RelocAddr EQU 0xE000 ; boot1 relocated address
kBoot1Sector1Addr EQU kBoot1RelocAddr + kSectorBytes ; boot1 load address for sector 1
kHFSPlusBuffer EQU kBoot1Sector1Addr + kSectorBytes ; HFS+ Volume Header address
kBoot2Sectors EQU (480 * 1024 - 512) / kSectorBytes ; max size of 'boot' file in sectors = 448 but I want 472
kBoot2Segment EQU 0x2000 ; boot2 load segment
kBoot2Address EQU kSectorBytes ; boot2 load address
;
; Format of fdisk partition entry.
;
; The symbol 'part_size' is automatically defined as an `EQU'
; giving the size of the structure.
;
struc part
.bootid resb 1 ; bootable or not
.head resb 1 ; starting head, sector, cylinder
.sect resb 1 ;
.cyl resb 1 ;
.type resb 1 ; partition type
.endhead resb 1 ; ending head, sector, cylinder
.endsect resb 1 ;
.endcyl resb 1 ;
.lba resd 1 ; starting lba
.sectors resd 1 ; size in sectors
endstruc
;-------------------------------------------------------------------------
; HFS+ related structures and constants
;
kHFSPlusSignature EQU 'H+' ; HFS+ volume signature
kHFSPlusCaseSignature EQU 'HX' ; HFS+ volume case-sensitive signature
kHFSPlusCaseSigX EQU 'X' ; upper byte of HFS+ volume case-sensitive signature
kHFSPlusExtentDensity EQU 8 ; 8 extent descriptors / extent record
;
; HFSUniStr255
;
struc HFSUniStr255
.length resw 1
.unicode resw 255
endstruc
;
; HFSPlusExtentDescriptor
;
struc HFSPlusExtentDescriptor
.startBlock resd 1
.blockCount resd 1
endstruc
;
; HFSPlusForkData
;
struc HFSPlusForkData
.logicalSize resq 1
.clumpSize resd 1
.totalBlocks resd 1
.extents resb kHFSPlusExtentDensity * HFSPlusExtentDescriptor_size
endstruc
;
; HFSPlusVolumeHeader
;
struc HFSPlusVolumeHeader
.signature resw 1
.version resw 1
.attributes resd 1
.lastMountedVersion resd 1
.journalInfoBlock resd 1
.createDate resd 1
.modifyDate resd 1
.backupDate resd 1
.checkedDate resd 1
.fileCount resd 1
.folderCount resd 1
.blockSize resd 1
.totalBlocks resd 1
.freeBlocks resd 1
.nextAllocation resd 1
.rsrcClumpSize resd 1
.dataClumpSize resd 1
.nextCatalogID resd 1
.writeCount resd 1
.encodingsBitmap resq 1
.finderInfo resd 8
.allocationFile resb HFSPlusForkData_size
.extentsFile resb HFSPlusForkData_size
.catalogFile resb HFSPlusForkData_size
.attributesFile resb HFSPlusForkData_size
.startupFile resb HFSPlusForkData_size
endstruc
;
; B-tree related structures and constants
;
kBTIndexNode EQU 0
kBTMaxRecordLength EQU 264 ; sizeof(kHFSPlusFileThreadRecord)
kHFSRootParentID EQU 1 ; Parent ID of the root folder
kHFSRootFolderID EQU 2 ; Folder ID of the root folder
kHFSExtentsFileID EQU 3 ; File ID of the extents overflow file
kHFSCatalogFileID EQU 4 ; File ID of the catalog file
kHFSPlusFileRecord EQU 0x200
kForkTypeData EQU 0
kForkTypeResource EQU 0xFF
;
; BTNodeDescriptor
;
struc BTNodeDescriptor
.fLink resd 1
.bLink resd 1
.kind resb 1
.height resb 1
.numRecords resw 1
.reserved resw 1
endstruc
;
; BTHeaderRec
;
struc BTHeaderRec
.treeDepth resw 1
.rootNode resd 1
.leafRecords resd 1
.firstLeafNode resd 1
.lastLeafNode resd 1
.nodeSize resw 1
.maxKeyLength resw 1
.totalNodes resd 1
.freeNodes resd 1
.reserved1 resw 1
.clumpSize resd 1
.btreeType resb 1
.keyCompareType resb 1
.attributes resd 1
.reserved3 resd 16
endstruc
;
; BTIndexRec
;
struc BTIndexRec
.childID resd 1
endstruc
;
; HFSPlusCatalogKey
;
struc HFSPlusCatalogKey
;
; won't use the keyLength field for easier addressing data inside this structure
;
;.keyLength resw 1
.parentID resd 1
.nodeName resb HFSUniStr255_size
endstruc
;
; HFSPlusExtentKey
;
struc HFSPlusExtentKey
;
; won't use the keyLength field for easier addressing data inside this structure
;
;.keyLength resw 1
.forkType resb 1
.pad resb 1
.fileID resd 1
.startBlock resd 1
endstruc
;
; HFSPlusBSDInfo
;
struc HFSPlusBSDInfo
.ownerID resd 1
.groupID resd 1
.adminFlags resb 1
.ownerFlags resb 1
.fileMode resw 1
.special resd 1
endstruc
;
; FileInfo
;
struc FileInfo
.fileType resd 1
.fileCreator resd 1
.finderFlags resw 1
.location resw 2
.reservedField resw 1
endstruc
;
; ExtendedFileInfo
;
struc ExtendedFileInfo
.reserved1 resw 4
.extFinderFlags resw 1
.reserved2 resw 1
.putAwayFolderID resd 1
endstruc
;
; HFSPlusCatalogFile
;
struc HFSPlusCatalogFile
.recordType resw 1
.flags resw 1
.reserved1 resd 1
.fileID resd 1
.createDate resd 1
.contentModDate resd 1
.attributeModDate resd 1
.accessDate resd 1
.backupDate resd 1
.permissions resb HFSPlusBSDInfo_size
.userInfo resb FileInfo_size
.finderInfo resb ExtendedFileInfo_size
.textEncoding resd 1
.reserved2 resd 1
.dataFork resb HFSPlusForkData_size
.resourceFork resb HFSPlusForkData_size
endstruc
;
; Macros.
;
%macro jmpabs 1
push WORD %1
ret
%endmacro
%macro DebugCharMacro 1
pushad
mov al, %1
call print_char
call getc
popad
%endmacro
%macro PrintCharMacro 1
pushad
mov al, %1
call print_char
popad
%endmacro
%macro PutCharMacro 1
call print_char
%endmacro
%macro PrintHexMacro 1
call print_hex
%endmacro
%macro PrintString 1
mov si, %1
call print_string
%endmacro
%macro LogString 1
mov di, %1
call log_string
%endmacro
%if DEBUG
%define DebugChar(x) DebugCharMacro x
%define PrintChar(x) PrintCharMacro x
%define PutChar(x) PutCharMacro
%define PrintHex(x) PrintHexMacro x
%else
%define DebugChar(x)
%define PrintChar(x)
%define PutChar(x)
%define PrintHex(x)
%endif
;--------------------------------------------------------------------------
; Start of text segment.
SEGMENT .text
ORG kBoot1RelocAddr
;--------------------------------------------------------------------------
; Boot code is loaded at 0:7C00h.
;
start:
;
; Set up the stack to grow down from kBoot1StackSegment:kBoot1StackAddress.
; Interrupts should be off while the stack is being manipulated.
;
cli ; interrupts off
xor ax, ax ; zero ax
mov ss, ax ; ss <- 0
mov sp, kBoot1StackAddress ; sp <- top of stack
sti ; reenable interrupts
mov ds, ax ; ds <- 0
mov es, ax ; es <- 0
;
; Relocate boot1 code.
;
push si
mov si, kBoot1LoadAddr ; si <- source
mov di, kBoot1RelocAddr ; di <- destination
cld ; auto-increment SI and/or DI registers
mov cx, kSectorBytes ; copy 256 words
rep movsb ; repeat string move (word) operation
pop si
;
; Code relocated, jump to startReloc in relocated location.
;
; FIXME: Is there any way to instruct NASM to compile a near jump
; using absolute address instead of relative displacement?
;
jmpabs startReloc
;--------------------------------------------------------------------------
; Start execution from the relocated location.
;
startReloc:
;
; Initializing global variables.
;
mov eax, [si + part.lba]
mov [gPartLBA], eax ; save the current partition LBA offset
mov [gBIOSDriveNumber], dl ; save BIOS drive number
mov WORD [gMallocPtr], mallocStart ; set free space pointer
;
; Loading upper 512 bytes of boot1h and HFS+ Volume Header.
;
xor ecx, ecx ; sector 1 of current partition
inc ecx
mov al, 2 ; read 2 sectors: sector 1 of boot1h + HFS+ Volume Header
mov edx, kBoot1Sector1Addr
call readLBA
;
; Initializing more global variables.
;
mov eax, [kHFSPlusBuffer + HFSPlusVolumeHeader.blockSize]
bswap eax ; convert to little-endian
shr eax, 9 ; convert to sector unit
mov [gBlockSize], eax ; save blockSize as little-endian sector unit!
;
; Looking for HFSPlus ('H+') or HFSPlus case-sensitive ('HX') signature.
;
mov ax, [kHFSPlusBuffer + HFSPlusVolumeHeader.signature]
cmp ax, kHFSPlusCaseSignature
je findRootBoot
cmp ax, kHFSPlusSignature
jne error
;--------------------------------------------------------------------------
; Find stage2 boot file in a HFS+ Volume's root folder.
;
findRootBoot:
mov al, kHFSCatalogFileID
lea si, [searchCatalogKey]
lea di, [kHFSPlusBuffer + HFSPlusVolumeHeader.catalogFile + HFSPlusForkData.extents]
call lookUpBTree
jne error
lea si, [bp + BTree.recordDataPtr]
mov si, [si]
cmp WORD [si], kHFSPlusFileRecord
jne error
; EAX = Catalog File ID
; BX = read size in sectors
; ECX = file offset in sectors
; EDX = address of read buffer
; DI = address of HFSPlusForkData
;
; Use the second big-endian double-word as the file length in HFSPlusForkData.logicalSize
;
mov ebx, [si + HFSPlusCatalogFile.dataFork + HFSPlusForkData.logicalSize + 4]
bswap ebx ; convert file size to little-endian
add ebx, kSectorBytes - 1 ; adjust size before unit conversion
shr ebx, 9 ; convert file size to sector unit
cmp bx, kBoot2Sectors ; check if bigger than max stage2 size
ja error
mov eax, [si + HFSPlusCatalogFile.fileID]
bswap eax ; convert fileID to little-endian
xor ecx, ecx
mov edx, (kBoot2Segment << 4) + kBoot2Address
lea di, [si + HFSPlusCatalogFile.dataFork + HFSPlusForkData.extents]
call readExtent
%if VERBOSE
LogString(bootfile_msg)
%endif
boot2:
%if DEBUG
DebugChar ('!')
%endif
%if UNUSED
;
; Waiting for a key press.
;
mov ah, 0
int 0x16
%endif
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
jmp kBoot2Segment:kBoot2Address
error:
%if VERBOSE
LogString(error_str)
%endif
hang:
hlt
jmp hang
;--------------------------------------------------------------------------
; readSectors - Reads more than 127 sectors using LBA addressing.
;
; Arguments:
; AX = number of 512-byte sectors to read (valid from 1-1280).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
;
; Returns:
; CF = 0 success
; 1 error
;
readSectors:
pushad
mov bx, ax
.loop:
xor eax, eax ; EAX = 0
mov al, bl ; assume we reached the last block.
cmp bx, maxSectorCount ; check if we really reached the last block
jb .readBlock ; yes, BX < MaxSectorCount
mov al, maxSectorCount ; no, read MaxSectorCount
.readBlock:
call readLBA
sub bx, ax ; decrease remaning sectors with the read amount
jz .exit ; exit if no more sectors left to be loaded
add ecx, eax ; adjust LBA sector offset
shl ax, 9 ; convert sectors to bytes
add edx, eax ; adjust target memory location
jmp .loop ; read remaining sectors
.exit:
popad
ret
;--------------------------------------------------------------------------
; readLBA - Read sectors from a partition using LBA addressing.
;
; Arguments:
; AL = number of 512-byte sectors to read (valid from 1-127).
; EDX = pointer to where the sectors should be stored.
; ECX = sector offset in partition
; [bios_drive_number] = drive number (0x80 + unit number)
;
; Returns:
; CF = 0 success
; 1 error
;
readLBA:
pushad ; save all registers
push es ; save ES
mov bp, sp ; save current SP
;
; Convert EDX to segment:offset model and set ES:BX
;
; Some BIOSes do not like offset to be negative while reading
; from hard drives. This usually leads to "boot1: error" when trying
; to boot from hard drive, while booting normally from USB flash.
; The routines, responsible for this are apparently different.
; Thus we split linear address slightly differently for these
; capricious BIOSes to make sure offset is always positive.
;
mov bx, dx ; save offset to BX
and bh, 0x0f ; keep low 12 bits
shr edx, 4 ; adjust linear address to segment base
xor dl, dl ; mask low 8 bits
mov es, dx ; save segment to ES
;
; Create the Disk Address Packet structure for the
; INT13/F42 (Extended Read Sectors) on the stack.
;
; push DWORD 0 ; offset 12, upper 32-bit LBA
push ds ; For sake of saving memory,
push ds ; push DS register, which is 0.
add ecx, [gPartLBA] ; offset 8, lower 32-bit LBA
push ecx
push es ; offset 6, memory segment
push bx ; offset 4, memory offset
xor ah, ah ; offset 3, must be 0
push ax ; offset 2, number of sectors
push WORD 16 ; offset 0-1, packet size
;
; INT13 Func 42 - Extended Read Sectors
;
; Arguments:
; AH = 0x42
; [bios_drive_number] = drive number (0x80 + unit number)
; DS:SI = pointer to Disk Address Packet
;
; Returns:
; AH = return status (sucess is 0)
; carry = 0 success
; 1 error
;
; Packet offset 2 indicates the number of sectors read
; successfully.
;
mov dl, [gBIOSDriveNumber] ; load BIOS drive number
mov si, sp
mov ah, 0x42
int 0x13
jc error
;
; Issue a disk reset on error.
; Should this be changed to Func 0xD to skip the diskette controller
; reset?
;
; xor ax, ax ; Func 0
; int 0x13 ; INT 13
; stc ; set carry to indicate error
.exit:
mov sp, bp ; restore SP
pop es ; restore ES
popad
ret
%if VERBOSE
;--------------------------------------------------------------------------
; Write a string with 'boot1: ' prefix to the console.
;
; Arguments:
; ES:DI pointer to a NULL terminated string.
;
; Clobber list:
; DI
;
log_string:
pushad
push di
mov si, log_title_str
call print_string
pop si
call print_string
popad
ret
;-------------------------------------------------------------------------
; Write a string to the console.
;
; Arguments:
; DS:SI pointer to a NULL terminated string.
;
; Clobber list:
; AX, BX, SI
;
print_string:
mov bx, 1 ; BH=0, BL=1 (blue)
.loop:
lodsb ; load a byte from DS:SI into AL
cmp al, 0 ; Is it a NULL?
je .exit ; yes, all done
mov ah, 0xE ; INT10 Func 0xE
int 0x10 ; display byte in tty mode
jmp .loop
.exit:
ret
%endif ; VERBOSE
%if DEBUG
;--------------------------------------------------------------------------
; Write the 4-byte value to the console in hex.
;
; Arguments:
; EAX = Value to be displayed in hex.
;
print_hex:
pushad
mov cx, WORD 4
bswap eax
.loop:
push ax
ror al, 4
call print_nibble ; display upper nibble
pop ax
call print_nibble ; display lower nibble
ror eax, 8
loop .loop
%if UNUSED
mov al, 10 ; carriage return
call print_char
mov al, 13
call print_char
%endif ; UNUSED
popad
ret
print_nibble:
and al, 0x0f
add al, '0'
cmp al, '9'
jna .print_ascii
add al, 'A' - '9' - 1
.print_ascii:
call print_char
ret
;--------------------------------------------------------------------------
; getc - wait for a key press
;
getc:
pushad
mov ah, 0
int 0x16
popad
ret
;--------------------------------------------------------------------------
; Write a ASCII character to the console.
;
; Arguments:
; AL = ASCII character.
;
print_char:
pushad
mov bx, 1 ; BH=0, BL=1 (blue)
mov ah, 0x0e ; bios INT 10, Function 0xE
int 0x10 ; display byte in tty mode
popad
ret
%endif ; DEBUG
%if UNUSED
;--------------------------------------------------------------------------
; Convert null terminated string to HFSUniStr255
;
; Arguments:
; DS:DX pointer to a NULL terminated string.
; ES:DI pointer to result.
;
ConvertStrToUni:
pushad ; save registers
push di ; save DI for unicode string length pointer
mov si, dx ; use SI as source string pointer
xor ax, ax ; AX = unicode character
mov cl, al ; CL = string length
.loop:
stosw ; store unicode character (length 0 at first run)
lodsb ; load next character to AL
inc cl ; increment string length count
cmp al, NULL ; check for string terminator
jne .loop
pop di ; restore unicode string length pointer
dec cl ; ignoring terminator from length count
mov [di], cl ; save string length
popad ; restore registers
ret
%endif ; UNUSED
;--------------------------------------------------------------------------
; Convert big-endian HFSUniStr255 to little-endian
;
; Arguments:
; DS:SI = pointer to big-endian HFSUniStr255
; ES:DI = pointer to result buffer
;
ConvertHFSUniStr255ToLE:
pushad
lodsw
xchg ah, al
stosw
cmp al, 0
je .exit
mov cx, ax
.loop:
lodsw
xchg ah, al ; convert AX to little-endian
;
; When working with a case-sensitive HFS+ (HX) filesystem, we shouldn't change the case.
;
cmp BYTE [kHFSPlusBuffer + HFSPlusVolumeHeader.signature + 1], kHFSPlusCaseSigX
je .keepcase
or ax, ax
jne .convertToLE
dec ax ; NULL must be the strongest char
.convertToLE:
cmp ah, 0
ja .keepcase
cmp al, 'A'
jb .keepcase
cmp al, 'Z'
ja .keepcase
add al, 32 ; convert to lower-case
.keepcase:
stosw
loop .loop
.exit:
popad
ret
;--------------------------------------------------------------------------
; compare HFSPlusExtentKey structures
;
; Arguments:
; DS:SI = search key
; ES:DI = trial key
;
; Returns:
; [BTree.searchResult] = result
; FLAGS = relation between search and trial keys
;
compareHFSPlusExtentKeys:
pushad
mov dl, 0 ; DL = result of comparison, DH = bestGuess
mov eax, [si + HFSPlusExtentKey.fileID]
cmp eax, [di + HFSPlusExtentKey.fileID]
jne .checkFlags
cmp BYTE [si + HFSPlusExtentKey.forkType], kForkTypeData
jne .checkFlags
mov eax, [si + HFSPlusExtentKey.startBlock]
cmp eax, [di + HFSPlusExtentKey.startBlock]
je compareHFSPlusCatalogKeys.exit
.checkFlags:
ja compareHFSPlusCatalogKeys.searchKeyGreater ; search key > trial key
jb compareHFSPlusCatalogKeys.trialKeyGreater ; search key < trial key
;--------------------------------------------------------------------------
; Compare HFSPlusCatalogKey structures
;
; Arguments:
; DS:SI = search key
; ES:DI = trial key
;
; Returns:
; [BTree.searchResult] = result
; FLAGS = relation between search and trial keys
;
compareHFSPlusCatalogKeys:
pushad
xor dx, dx ; DL = result of comparison, DH = bestGuess
xchg si, di
lodsd
mov ecx, eax ; ECX = trial parentID
xchg si, di
lodsd ; EAX = search parentID
cmp eax, ecx
ja .searchKeyGreater ; search parentID > trial parentID
jb .trialKeyGreater ; search parentID < trial parentID
.compareNodeName: ; search parentID = trial parentID
xchg si, di
lodsw
mov cx, ax ; CX = trial nodeName.length
xchg si, di
lodsw ; AX = search nodeName.length
cmp cl, 0 ; trial nodeName.length = 0?
je .searchKeyGreater
cmp ax, cx
je .strCompare
ja .searchStrLonger
.trialStrLonger:
dec dh
mov cx, ax
jmp .strCompare
.searchStrLonger:
inc dh
.strCompare:
repe cmpsw
ja .searchKeyGreater
jb .trialKeyGreater
mov dl, dh
jmp .exit
.trialKeyGreater:
dec dl
jmp .exit
.searchKeyGreater:
inc dl
.exit:
mov [bp + BTree.searchResult], dl
cmp dl, 0 ; set flags to check relation between keys
popad
ret
;--------------------------------------------------------------------------
; Allocate memory
;
; Arguments:
; CX = size of requested memory
;
; Returns:
; BP = start address of allocated memory
;
; Clobber list:
; CX
;
malloc:
push ax ; save AX
push di ; save DI
mov di, [gMallocPtr] ; start address of free space
push di ; save free space start address
inc di ;
inc di ; keep the first word untouched
dec cx ; for the last memory block pointer.
dec cx ;
mov al, NULL ; fill with zero
rep stosb ; repeat fill
mov [gMallocPtr], di ; adjust free space pointer
pop bp ; BP = start address of allocated memory
mov [di], bp ; set start address of allocated memory at next
; allocation block's free space address.
pop di ; restore DI
pop ax ; restore AX
ret
%if UNUSED
;--------------------------------------------------------------------------
; Free allocated memory
;
; Returns:
; BP = start address of previously allocated memory
;
free:
lea bp, [gMallocPtr]
mov bp, [bp]
mov [gMallocPtr], bp
ret
%endif ; UNUSED
;--------------------------------------------------------------------------
; Static data.
;
%if VERBOSE
bootfile_msg db '/boot', CR, LF, NULL
%endif
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized sector with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
; If the booter code becomes too large, then nasm will complain
; that the 'times' argument is negative.
pad_table_and_sig:
times 510-($-$$) db 0
dw kBootSignature
;
; Sector 1 code area
;
;--------------------------------------------------------------------------
; lookUpBTree - initializes a new BTree instance and
; look up for HFSPlus Catalog File or Extent Overflow keys
;
; Arguments:
; AL = kHFSPlusFileID (Catalog or Extents Overflow)
; SI = address of searchKey
; DI = address of HFSPlusForkData.extents
;
; Returns:
; BP = address of BTree instance
; ECX = rootNode's logical offset in sectors
;
lookUpBTree:
mov cx, BTree_size ; allocate memory with BTree_size
call malloc ; BP = start address of allocated memory.
mov [bp + BTree.fileID], al ; save fileFileID
mov edx, [di] ; first extent of current file
call blockToSector ; ECX = converted to sector unit
mov al, 1 ; 1 sector is enough for
xor edx, edx ; reading current file's header.
lea dx, [bp + BTree.BTHeaderBuffer] ; load into BTreeHeaderBuffer
call readLBA ; read
mov ax, [bp + BTree.BTHeaderBuffer + BTNodeDescriptor_size + BTHeaderRec.nodeSize]
xchg ah, al ; convert to little-endian
mov [bp + BTree.nodeSize], ax ; save nodeSize
;
; Always start the lookup process with the root node.
;
mov edx, [bp + BTree.BTHeaderBuffer + BTNodeDescriptor_size + BTHeaderRec.rootNode]
.readNode:
;
; Converting nodeID to sector unit
;
mov ax, [bp + BTree.nodeSize]
shr ax, 9 ; convert nodeSize to sectors
mov bx, ax ; BX = read sector count
cwde
bswap edx ; convert node ID to little-endian
mul edx ; multiply with nodeSize converted to sector unit
mov ecx, eax ; ECX = file offset in BTree
mov eax, [bp + BTree.fileID]
lea edx, [bp + BTree.nodeBuffer]
call readExtent
;
; AX = lowerBound = 0
;
xor ax, ax
;
; BX = upperBound = numRecords - 1
;
mov bx, [bp + BTree.nodeBuffer + BTNodeDescriptor.numRecords]
xchg bh, bl
dec bx
.bsearch:
cmp ax, bx
ja .checkResult ; jump if lowerBound > upperBound
mov cx, ax
add cx, bx
shr cx, 1 ; test index = (lowerBound + upperBound / 2)
call getBTreeRecord
%if UNUSED
pushad
jl .csearchLessThanTrial
jg .csearchGreaterThanTrial
PrintChar('=')
jmp .csearchCont
.csearchGreaterThanTrial:
PrintChar('>')
jmp .csearchCont
.csearchLessThanTrial:
PrintChar('<')
.csearchCont:
popad
%endif ; UNUSED
.adjustBounds:
je .checkResult
jl .searchLessThanTrial
jg .searchGreaterThanTrial
jmp .bsearch
.searchLessThanTrial:
mov bx, cx
dec bx ; upperBound = index - 1
jmp .bsearch
.searchGreaterThanTrial:
mov ax, cx
inc ax ; lowerBound = index + 1
jmp .bsearch
.checkResult:
cmp BYTE [bp + BTree.searchResult], 0
jge .foundKey
mov cx, bx
call getBTreeRecord
.foundKey:
cmp BYTE [bp + BTree.nodeBuffer + BTNodeDescriptor.kind], kBTIndexNode
jne .exit
lea bx, [bp + BTree.recordDataPtr]
mov bx, [bx]
mov edx, [bx]
jmp .readNode
.exit:
cmp BYTE [bp + BTree.searchResult], 0
ret
;--------------------------------------------------------------------------
; getBTreeRecord - read and compare BTree record
;
; Arguments:
; CX = record index
; SI = address of search key
;
; Returns:
; [BTree.searchResult] = result of key compare
; [BTree.recordDataPtr] = address of record data
;
getBTreeRecord:
pushad
push si ; save SI
lea di, [bp + BTree.nodeBuffer] ; DI = start of nodeBuffer
push di ; use later
mov ax, [bp + BTree.nodeSize] ; get nodeSize
add di, ax ; DI = beyond nodeBuffer
inc cx ; increment index
shl cx, 1 ; * 2
sub di, cx ; DI = pointer to record
mov ax, [di] ; offset to record
xchg ah, al ; convert to little-endian
pop di ; start of nodeBuffer
add di, ax ; DI = address of record key
mov si, di ; save to SI
mov ax, [di] ; keyLength
xchg ah, al ; convert to little-endian
inc ax ; suppress keySize (2 bytes)
inc ax ;
add di, ax ; DI = address of record data
mov [bp + BTree.recordDataPtr], di ; save address of record data
lea di, [bp + BTree.trialKey]
push di ; save address of trialKey
lodsw ; suppress keySize (2 bytes)
;
; Don't need to compare as DWORD since all reserved CNIDs fits to a single byte
;
cmp BYTE [bp + BTree.fileID], kHFSCatalogFileID
je .prepareTrialCatalogKey
.prepareTrialExtentKey:
mov bx, compareHFSPlusExtentKeys
movsw ; copy forkType + pad
mov cx, 2 ; copy fileID + startBlock
.extentLoop:
lodsd
bswap eax ; convert to little-endian
stosd
loop .extentLoop
jmp .exit
.prepareTrialCatalogKey:
mov bx, compareHFSPlusCatalogKeys
lodsd
bswap eax ; convert ParentID to little-endian
stosd
call ConvertHFSUniStr255ToLE ; convert nodeName to little-endian
.exit:
pop di ; restore address of trialKey
%if UNUSED
;
; Print catalog trial key
;
pushad
mov si, di
lodsd
PrintChar('k')
PrintHex()
lodsw
cmp ax, 0
je .printExit
mov cx, ax
.printLoop:
lodsw
call print_char
loop .printLoop
.printExit:
popad
;
;
;
%endif ; UNUSED
%if UNUSED
;
; Print extent trial key
;
pushad
PrintChar('k')
mov si, di
xor eax, eax
lodsw
PrintHex()
lodsd
PrintHex()
lodsd
PrintHex()
popad
;
;
;
%endif ; UNUSED
pop si ; restore SI
call bx ; call key compare proc
popad
ret
;--------------------------------------------------------------------------
; readExtent - read extents from a HFS+ file (multiple extent support)
;
; Arguments:
; EAX = Catalog File ID
; BX = read size in sectors
; ECX = file offset in sectors
; EDX = address of read buffer
; DI = address of HFSPlusForkData.extents
;
readExtent:
pushad
;
; Save Catalog File ID as part of a search HFSPlusExtentKey
; for a possible Extents Overflow lookup.
;
mov [bp + BTree.searchExtentKey + HFSPlusExtentKey.fileID], eax
mov [bp + BTree.readBufferPtr], edx
mov ax, bx
cwde
mov [bp + BTree.readSize], eax
mov ebx, ecx ; EBX = file offset
xor eax, eax
mov [bp + BTree.currentExtentOffs], eax
.beginExtentBlock:
mov BYTE [bp + BTree.extentCount], 0
.extentSearch:
cmp BYTE [bp + BTree.extentCount], kHFSPlusExtentDensity
jb .continue
.getNextExtentBlock:
push ebx
mov eax, [bp + BTree.currentExtentOffs]
;
; Converting sector unit to HFS+ allocation block unit.
;
xor edx, edx
div DWORD [gBlockSize] ; divide with blockSize
;
; Preparing searchExtentKey's startBlock field.
;
mov [bp + BTree.searchExtentKey + HFSPlusExtentKey.startBlock], eax
mov al, kHFSExtentsFileID
lea si, [bp + BTree.searchExtentKey]
lea di, [kHFSPlusBuffer + HFSPlusVolumeHeader.extentsFile + HFSPlusForkData.extents]
call lookUpBTree
jnz NEAR .exit
;
; BP points to the new workspace allocated by lookUpBTree.
;
lea di, [bp + BTree.recordDataPtr]
mov di, [di]
;
; Switch back to the previous workspace.
;
lea bp, [gMallocPtr]
mov bp, [bp]
mov [gMallocPtr], bp
pop ebx
jmp .beginExtentBlock
.continue:
mov edx, [di + HFSPlusExtentDescriptor.blockCount]
call blockToSector ; ECX = converted current extent's blockCount to sectors
mov eax, [bp + BTree.currentExtentOffs] ; EAX = current extent's start offset (sector)
mov edx, eax
add edx, ecx ; EDX = next extent's start offset (sector)
cmp ebx, edx
mov [bp + BTree.currentExtentOffs], edx ; set currentExtentOffs as the next extent's start offset
jae .nextExtent ; jump to next extent if file offset > next extent's start offset
.foundExtent:
mov edx, ebx
sub edx, eax ; EDX = relative offset within current extent
mov eax, edx ; will be used below to determine read size
mov esi, [bp + BTree.readSize] ; ESI = remaining sectors to be read
add edx, esi
cmp edx, ecx ; test if relative offset + readSize fits to this extent
jbe .read ; read all remaining sectors from this extent
.splitRead:
sub ecx, eax ; read amount of sectors beginning at relative offset
mov esi, ecx ; of current extent up to the end of current extent
.read:
mov edx, [di + HFSPlusExtentDescriptor.startBlock]
call blockToSector ; ECX = converted to sectors
add ecx, eax ; file offset converted to sectors
push si
mov ax, si
mov edx, [bp + BTree.readBufferPtr]
call readSectors
pop si
add ebx, esi
mov ax, si
cwde
shl ax, 9 ; convert SI (read sector count) to byte unit
add [bp + BTree.readBufferPtr], eax
sub [bp + BTree.readSize], esi
jz .exit
.nextExtent:
add di, kHFSPlusExtentDensity
inc BYTE [bp + BTree.extentCount]
jmp .extentSearch
.exit:
popad
ret
;--------------------------------------------------------------------------
; Convert big-endian HFSPlus allocation block to sector unit
;
; Arguments:
; EDX = allocation block
;
; Returns:
; ECX = allocation block converted to sector unit
;
; Clobber list:
; EDX
;
blockToSector:
push eax
mov eax, [gBlockSize]
bswap edx ; convert allocation block to little-endian
mul edx ; multiply with block number
mov ecx, eax ; result in EAX
pop eax
ret
%if UNUSED
;--------------------------------------------------------------------------
; Convert sector unit to HFSPlus allocation block unit
;
; Arguments:
; EDX = sector
;
; Returns:
; ECX = converted to allocation block unit
;
; Clobber list:
; EDX
;
sectorToBlock:
push eax
mov eax, edx
xor edx, edx
div DWORD [gBlockSize] ; divide with blockSize
mov ecx, eax ; result in EAX
pop eax
ret
%endif ; UNUSED
%if UNUSED
;--------------------------------------------------------------------------
; Convert big-endian BTree node ID to sector unit
;
; Arguments:
; EDX = node ID
;
; Returns:
; ECX = node ID converted to sector unit
;
; Clobber list:
; EDX
;
nodeToSector:
push eax
mov ax, [bp + BTree.nodeSize]
shr ax, 9 ; convert nodeSize to sectors
cwde
bswap edx ; convert node ID to little-endian
mul edx ; multiply with node ID
mov ecx, eax ; result in EAX
pop eax
ret
%endif ; UNUSED
;--------------------------------------------------------------------------
; Static data.
;
%if VERBOSE
log_title_str db 'boot1: ', NULL
error_str db 'error', NULL
%endif
searchCatalogKey dd kHFSRootFolderID
dw searchCatKeyNameLen
searchCatKeyName dw 'b', 'o', 'o', 't' ; must be lower case
searchCatKeyNameLen EQU ($ - searchCatKeyName) / 2
;--------------------------------------------------------------------------
; Pad the rest of the 512 byte sized sector with zeroes. The last
; two bytes is the mandatory boot sector signature.
;
pad_sector_1:
times 1022-($-$$) db 0
dw kBootSignature
;
; Local BTree variables
;
struc BTree
.mallocLink resw 1 ; pointer to previously allocated memory block
.fileID resd 1 ; will use as BYTE
.nodeSize resd 1 ; will use as WORD
.searchExtentKey resb HFSPlusExtentKey_size
.searchResult resb 1
.trialKey resb kBTMaxRecordLength
.recordDataPtr resw 1
.readBufferPtr resd 1
.currentExtentOffs resd 1
.readSize resd 1
.extentCount resb 1
ALIGNB 2
.BTHeaderBuffer resb kSectorBytes
.nodeBuffer resb maxNodeSize
endstruc
;
; Global variables
;
ABSOLUTE kHFSPlusBuffer + HFSPlusVolumeHeader_size
gPartLBA resd 1
gBIOSDriveNumber resw 1
gBlockSize resd 1
gMallocPtr resw 1
; END
|
al3xtjames/Clover
| 2,412
|
Library/OpensslLib/SysCall/Ia32/MathReminderU64x64.S
|
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# MathReminderU64x64.S
#
# Abstract:
#
# 64-bit Math Worker Function.
# Divides a 64-bit unsigned value by another 64-bit unsigned value and returns
# the 64-bit unsigned remainder
#
#------------------------------------------------------------------------------
.686:
.code:
ASM_GLOBAL ASM_PFX(__umoddi3), ASM_PFX(DivU64x64Remainder)
#------------------------------------------------------------------------------
#
# void __cdecl __umoddi3 (void)
#
#------------------------------------------------------------------------------
ASM_PFX(__umoddi3):
# Original local stack when calling __umoddi3
# -----------------
# | |
# |---------------|
# | |
# |-- Divisor --|
# | |
# |---------------|
# | |
# |-- Dividend --|
# | |
# |---------------|
# | ReturnAddr** |
# ESP---->|---------------|
#
#
# Set up the local stack for Reminder pointer
#
sub $8, %esp
push %esp
#
# Set up the local stack for Divisor parameter
#
movl 28(%esp), %eax
push %eax
movl 28(%esp), %eax
push %eax
#
# Set up the local stack for Dividend parameter
#
movl 28(%esp), %eax
push %eax
movl 28(%esp), %eax
push %eax
#
# Call native DivU64x64Remainder of BaseLib
#
jmp ASM_PFX(DivU64x64Remainder)
#
# Put the Reminder in EDX:EAX as return value
#
movl 20(%esp), %eax
movl 24(%esp), %edx
#
# Adjust stack
#
add $28, %esp
ret $16
|
al3xtjames/Clover
| 1,620
|
Library/OpensslLib/SysCall/Ia32/MathRShiftU64.S
|
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# MathRShiftU64.S
#
# Abstract:
#
# 64-bit Math Worker Function.
# Shifts a 64-bit unsigned value right by a certain number of bits.
#
#------------------------------------------------------------------------------
.686:
.code:
ASM_GLOBAL ASM_PFX(__ashrdi3)
#------------------------------------------------------------------------------
#
# void __cdecl __ashrdi3 (void)
#
#------------------------------------------------------------------------------
ASM_PFX(__ashrdi3):
#
# Checking: Only handle 64bit shifting or more
#
cmpb $64, %cl
jae _Exit
#
# Handle shifting between 0 and 31 bits
#
cmpb $32, %cl
jae More32
shrd %cl, %edx, %eax
shr %cl, %edx
ret
#
# Handle shifting of 32-63 bits
#
More32:
movl %edx, %eax
xor %edx, %edx
and $31, %cl
shr %cl, %eax
ret
#
# Invalid number (less then 32bits), return 0
#
_Exit:
xor %eax, %eax
xor %edx, %edx
ret
|
al3xtjames/Clover
| 2,162
|
Library/OpensslLib/SysCall/Ia32/MathMultS64x64.S
|
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# MathMultS64x64.S
#
# Abstract:
#
# 64-bit Math Worker Function.
# Multiplies a 64-bit signed or unsigned value by a 64-bit signed or unsigned value
# and returns a 64-bit result
#
#------------------------------------------------------------------------------
.686:
.code:
ASM_GLOBAL ASM_PFX(_mulll), ASM_PFX(MultS64x64)
#------------------------------------------------------------------------------
#
# void __cdecl __mulll (void)
#
#------------------------------------------------------------------------------
ASM_PFX(__mulll):
# Original local stack when calling __mulll
# -----------------
# | |
# |---------------|
# | |
# |--Multiplier --|
# | |
# |---------------|
# | |
# |--Multiplicand-|
# | |
# |---------------|
# | ReturnAddr** |
# ESP---->|---------------|
#
#
# Set up the local stack for Multiplicand parameter
#
movl 16(%esp), %eax
push %eax
movl 16(%esp), %eax
push %eax
#
# Set up the local stack for Multiplier parameter
#
movl 16(%esp), %eax
push %eax
movl 16(%esp), %eax
push %eax
#
# Call native MulS64x64 of BaseLib
#
jmp ASM_PFX(MultS64x64)
#
# Adjust stack
#
add $16, %esp
ret $16
|
al3xtjames/Clover
| 2,285
|
Library/OpensslLib/SysCall/Ia32/MathDivU64x64.S
|
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# MathDivU64x64.S
#
# Abstract:
#
# 64-bit Math Worker Function.
# Divides a 64-bit unsigned value with a 64-bit unsigned value and returns
# a 64-bit unsigned result.
#
#------------------------------------------------------------------------------
.686:
.code:
ASM_GLOBAL ASM_PFX(__udivdi3), ASM_PFX(DivU64x64Remainder)
#------------------------------------------------------------------------------
#
# void __cdecl __udivdi3 (void)
#
#------------------------------------------------------------------------------
ASM_PFX(__udivdi3):
# Original local stack when calling __udivdi3
# -----------------
# | |
# |---------------|
# | |
# |-- Divisor --|
# | |
# |---------------|
# | |
# |-- Dividend --|
# | |
# |---------------|
# | ReturnAddr** |
# ESP---->|---------------|
#
#
# Set up the local stack for NULL Reminder pointer
#
xorl %eax, %eax
push %eax
#
# Set up the local stack for Divisor parameter
#
movl 20(%esp), %eax
push %eax
movl 20(%esp), %eax
push %eax
#
# Set up the local stack for Dividend parameter
#
movl 20(%esp), %eax
push %eax
movl 20(%esp), %eax
push %eax
#
# Call native DivU64x64Remainder of BaseLib
#
jmp ASM_PFX(DivU64x64Remainder)
#
# Adjust stack
#
addl $20, %esp
ret $16
|
al3xtjames/Clover
| 1,580
|
Library/OpensslLib/SysCall/Ia32/MathLShiftS64.S
|
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php.
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
# Module Name:
#
# MathLShiftS64.S
#
# Abstract:
#
# 64-bit Math Worker Function.
# Shifts a 64-bit signed value left by a certain number of bits.
#
#------------------------------------------------------------------------------
.686:
.code:
ASM_GLOBAL ASM_PFX(__ashldi3)
#------------------------------------------------------------------------------
#
# void __cdecl __ashldi3 (void)
#
#------------------------------------------------------------------------------
ASM_PFX(__ashldi3):
#
# Handle shifting of 64 or more bits (return 0)
#
cmpb $64, %cl
jae ReturnZero
#
# Handle shifting of between 0 and 31 bits
#
cmpb $32, %cl
jae More32
shld %cl, %eax, %edx
shl %cl, %eax
ret
#
# Handle shifting of between 32 and 63 bits
#
More32:
movl %eax, %edx
xor %eax, %eax
and $31, %cl
shl %cl, %edx
ret
ReturnZero:
xor %eax, %eax
xor %edx, %edx
ret
|
al3xtjames/Clover
| 3,597
|
Library/OpensslLib/openssl-1.0.1e/crypto/ia64cpuid.S
|
// Works on all IA-64 platforms: Linux, HP-UX, Win64i...
// On Win64i compile with ias.exe.
.text
.global OPENSSL_cpuid_setup#
.proc OPENSSL_cpuid_setup#
OPENSSL_cpuid_setup:
{ .mib; br.ret.sptk.many b0 };;
.endp OPENSSL_cpuid_setup#
.global OPENSSL_rdtsc#
.proc OPENSSL_rdtsc#
OPENSSL_rdtsc:
{ .mib; mov r8=ar.itc
br.ret.sptk.many b0 };;
.endp OPENSSL_rdtsc#
.global OPENSSL_atomic_add#
.proc OPENSSL_atomic_add#
.align 32
OPENSSL_atomic_add:
{ .mii; ld4 r2=[r32]
nop.i 0
nop.i 0 };;
.Lspin:
{ .mii; mov ar.ccv=r2
add r8=r2,r33
mov r3=r2 };;
{ .mmi; mf;;
cmpxchg4.acq r2=[r32],r8,ar.ccv
nop.i 0 };;
{ .mib; cmp.ne p6,p0=r2,r3
nop.i 0
(p6) br.dpnt .Lspin };;
{ .mib; nop.m 0
sxt4 r8=r8
br.ret.sptk.many b0 };;
.endp OPENSSL_atomic_add#
// Returns a structure comprising pointer to the top of stack of
// the caller and pointer beyond backing storage for the current
// register frame. The latter is required, because it might be
// insufficient to wipe backing storage for the current frame
// (as this procedure does), one might have to go further, toward
// higher addresses to reach for whole "retroactively" saved
// context...
.global OPENSSL_wipe_cpu#
.proc OPENSSL_wipe_cpu#
.align 32
OPENSSL_wipe_cpu:
.prologue
.fframe 0
.save ar.pfs,r2
.save ar.lc,r3
{ .mib; alloc r2=ar.pfs,0,96,0,96
mov r3=ar.lc
brp.loop.imp .L_wipe_top,.L_wipe_end-16
};;
{ .mii; mov r9=ar.bsp
mov r8=pr
mov ar.lc=96 };;
.body
{ .mii; add r9=96*8-8,r9
mov ar.ec=1 };;
// One can sweep double as fast, but then we can't quarantee
// that backing storage is wiped...
.L_wipe_top:
{ .mfi; st8 [r9]=r0,-8
mov f127=f0
mov r127=r0 }
{ .mfb; nop.m 0
nop.f 0
br.ctop.sptk .L_wipe_top };;
.L_wipe_end:
{ .mfi; mov r11=r0
mov f6=f0
mov r14=r0 }
{ .mfi; mov r15=r0
mov f7=f0
mov r16=r0 }
{ .mfi; mov r17=r0
mov f8=f0
mov r18=r0 }
{ .mfi; mov r19=r0
mov f9=f0
mov r20=r0 }
{ .mfi; mov r21=r0
mov f10=f0
mov r22=r0 }
{ .mfi; mov r23=r0
mov f11=f0
mov r24=r0 }
{ .mfi; mov r25=r0
mov f12=f0
mov r26=r0 }
{ .mfi; mov r27=r0
mov f13=f0
mov r28=r0 }
{ .mfi; mov r29=r0
mov f14=f0
mov r30=r0 }
{ .mfi; mov r31=r0
mov f15=f0
nop.i 0 }
{ .mfi; mov f16=f0 }
{ .mfi; mov f17=f0 }
{ .mfi; mov f18=f0 }
{ .mfi; mov f19=f0 }
{ .mfi; mov f20=f0 }
{ .mfi; mov f21=f0 }
{ .mfi; mov f22=f0 }
{ .mfi; mov f23=f0 }
{ .mfi; mov f24=f0 }
{ .mfi; mov f25=f0 }
{ .mfi; mov f26=f0 }
{ .mfi; mov f27=f0 }
{ .mfi; mov f28=f0 }
{ .mfi; mov f29=f0 }
{ .mfi; mov f30=f0 }
{ .mfi; add r9=96*8+8,r9
mov f31=f0
mov pr=r8,0x1ffff }
{ .mib; mov r8=sp
mov ar.lc=r3
br.ret.sptk b0 };;
.endp OPENSSL_wipe_cpu#
.global OPENSSL_cleanse#
.proc OPENSSL_cleanse#
OPENSSL_cleanse:
{ .mib; cmp.eq p6,p0=0,r33 // len==0
#if defined(_HPUX_SOURCE) && !defined(_LP64)
addp4 r32=0,r32
#endif
(p6) br.ret.spnt b0 };;
{ .mib; and r2=7,r32
cmp.leu p6,p0=15,r33 // len>=15
(p6) br.cond.dptk .Lot };;
.Little:
{ .mib; st1 [r32]=r0,1
cmp.ltu p6,p7=1,r33 } // len>1
{ .mbb; add r33=-1,r33 // len--
(p6) br.cond.dptk .Little
(p7) br.ret.sptk.many b0 };;
.Lot:
{ .mib; cmp.eq p6,p0=0,r2
(p6) br.cond.dptk .Laligned };;
{ .mmi; st1 [r32]=r0,1;;
and r2=7,r32 }
{ .mib; add r33=-1,r33
br .Lot };;
.Laligned:
{ .mmi; st8 [r32]=r0,8
and r2=-8,r33 // len&~7
add r33=-8,r33 };; // len-=8
{ .mib; cmp.ltu p6,p0=8,r2 // ((len+8)&~7)>8
(p6) br.cond.dptk .Laligned };;
{ .mbb; cmp.eq p6,p7=r0,r33
(p7) br.cond.dpnt .Little
(p6) br.ret.sptk.many b0 };;
.endp OPENSSL_cleanse#
|
al3xtjames/Clover
| 2,988
|
Library/OpensslLib/openssl-1.0.1e/crypto/armv4cpuid.S
|
#include "arm_arch.h"
.text
.code 32
.align 5
.global _armv7_neon_probe
.type _armv7_neon_probe,%function
_armv7_neon_probe:
.word 0xf26ee1fe @ vorr q15,q15,q15
.word 0xe12fff1e @ bx lr
.size _armv7_neon_probe,.-_armv7_neon_probe
.global _armv7_tick
.type _armv7_tick,%function
_armv7_tick:
mrc p15,0,r0,c9,c13,0
.word 0xe12fff1e @ bx lr
.size _armv7_tick,.-_armv7_tick
.global OPENSSL_atomic_add
.type OPENSSL_atomic_add,%function
OPENSSL_atomic_add:
#if __ARM_ARCH__>=6
.Ladd: ldrex r2,[r0]
add r3,r2,r1
strex r2,r3,[r0]
cmp r2,#0
bne .Ladd
mov r0,r3
.word 0xe12fff1e @ bx lr
#else
stmdb sp!,{r4-r6,lr}
ldr r2,.Lspinlock
adr r3,.Lspinlock
mov r4,r0
mov r5,r1
add r6,r3,r2 @ &spinlock
b .+8
.Lspin: bl sched_yield
mov r0,#-1
swp r0,r0,[r6]
cmp r0,#0
bne .Lspin
ldr r2,[r4]
add r2,r2,r5
str r2,[r4]
str r0,[r6] @ release spinlock
ldmia sp!,{r4-r6,lr}
tst lr,#1
moveq pc,lr
.word 0xe12fff1e @ bx lr
#endif
.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
.global OPENSSL_cleanse
.type OPENSSL_cleanse,%function
OPENSSL_cleanse:
eor ip,ip,ip
cmp r1,#7
subhs r1,r1,#4
bhs .Lot
cmp r1,#0
beq .Lcleanse_done
.Little:
strb ip,[r0],#1
subs r1,r1,#1
bhi .Little
b .Lcleanse_done
.Lot: tst r0,#3
beq .Laligned
strb ip,[r0],#1
sub r1,r1,#1
b .Lot
.Laligned:
str ip,[r0],#4
subs r1,r1,#4
bhs .Laligned
adds r1,r1,#4
bne .Little
.Lcleanse_done:
tst lr,#1
moveq pc,lr
.word 0xe12fff1e @ bx lr
.size OPENSSL_cleanse,.-OPENSSL_cleanse
.global OPENSSL_wipe_cpu
.type OPENSSL_wipe_cpu,%function
OPENSSL_wipe_cpu:
ldr r0,.LOPENSSL_armcap
adr r1,.LOPENSSL_armcap
ldr r0,[r1,r0]
eor r2,r2,r2
eor r3,r3,r3
eor ip,ip,ip
tst r0,#1
beq .Lwipe_done
.word 0xf3000150 @ veor q0, q0, q0
.word 0xf3022152 @ veor q1, q1, q1
.word 0xf3044154 @ veor q2, q2, q2
.word 0xf3066156 @ veor q3, q3, q3
.word 0xf34001f0 @ veor q8, q8, q8
.word 0xf34221f2 @ veor q9, q9, q9
.word 0xf34441f4 @ veor q10, q10, q10
.word 0xf34661f6 @ veor q11, q11, q11
.word 0xf34881f8 @ veor q12, q12, q12
.word 0xf34aa1fa @ veor q13, q13, q13
.word 0xf34cc1fc @ veor q14, q14, q14
.word 0xf34ee1fe @ veor q15, q15, q15
.Lwipe_done:
mov r0,sp
tst lr,#1
moveq pc,lr
.word 0xe12fff1e @ bx lr
.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
.global OPENSSL_instrument_bus
.type OPENSSL_instrument_bus,%function
OPENSSL_instrument_bus:
eor r0,r0,r0
tst lr,#1
moveq pc,lr
.word 0xe12fff1e @ bx lr
.size OPENSSL_instrument_bus,.-OPENSSL_instrument_bus
.global OPENSSL_instrument_bus2
.type OPENSSL_instrument_bus2,%function
OPENSSL_instrument_bus2:
eor r0,r0,r0
tst lr,#1
moveq pc,lr
.word 0xe12fff1e @ bx lr
.size OPENSSL_instrument_bus2,.-OPENSSL_instrument_bus2
.align 5
.LOPENSSL_armcap:
.word OPENSSL_armcap_P-.LOPENSSL_armcap
#if __ARM_ARCH__>=6
.align 5
#else
.Lspinlock:
.word atomic_add_spinlock-.Lspinlock
.align 5
.data
.align 2
atomic_add_spinlock:
.word 0
#endif
.comm OPENSSL_armcap_P,4,4
.hidden OPENSSL_armcap_P
|
al3xtjames/Clover
| 8,025
|
Library/OpensslLib/openssl-1.0.1e/crypto/sparccpuid.S
|
#if defined(__SUNPRO_C) && defined(__sparcv9)
# define ABI64 /* They've said -xarch=v9 at command line */
#elif defined(__GNUC__) && defined(__arch64__)
# define ABI64 /* They've said -m64 at command line */
#endif
#ifdef ABI64
.register %g2,#scratch
.register %g3,#scratch
# define FRAME -192
# define BIAS 2047
#else
# define FRAME -96
# define BIAS 0
#endif
.text
.align 32
.global OPENSSL_wipe_cpu
.type OPENSSL_wipe_cpu,#function
! Keep in mind that this does not excuse us from wiping the stack!
! This routine wipes registers, but not the backing store [which
! resides on the stack, toward lower addresses]. To facilitate for
! stack wiping I return pointer to the top of stack of the *caller*.
OPENSSL_wipe_cpu:
save %sp,FRAME,%sp
nop
#ifdef __sun
#include <sys/trap.h>
ta ST_CLEAN_WINDOWS
#else
call .walk.reg.wins
#endif
nop
call .PIC.zero.up
mov .zero-(.-4),%o0
ld [%o0],%f0
ld [%o0],%f1
subcc %g0,1,%o0
! Following is V9 "rd %ccr,%o0" instruction. However! V8
! specification says that it ("rd %asr2,%o0" in V8 terms) does
! not cause illegal_instruction trap. It therefore can be used
! to determine if the CPU the code is executing on is V8- or
! V9-compliant, as V9 returns a distinct value of 0x99,
! "negative" and "borrow" bits set in both %icc and %xcc.
.word 0x91408000 !rd %ccr,%o0
cmp %o0,0x99
bne .v8
nop
! Even though we do not use %fp register bank,
! we wipe it as memcpy might have used it...
.word 0xbfa00040 !fmovd %f0,%f62
.word 0xbba00040 !...
.word 0xb7a00040
.word 0xb3a00040
.word 0xafa00040
.word 0xaba00040
.word 0xa7a00040
.word 0xa3a00040
.word 0x9fa00040
.word 0x9ba00040
.word 0x97a00040
.word 0x93a00040
.word 0x8fa00040
.word 0x8ba00040
.word 0x87a00040
.word 0x83a00040 !fmovd %f0,%f32
.v8: fmovs %f1,%f31
clr %o0
fmovs %f0,%f30
clr %o1
fmovs %f1,%f29
clr %o2
fmovs %f0,%f28
clr %o3
fmovs %f1,%f27
clr %o4
fmovs %f0,%f26
clr %o5
fmovs %f1,%f25
clr %o7
fmovs %f0,%f24
clr %l0
fmovs %f1,%f23
clr %l1
fmovs %f0,%f22
clr %l2
fmovs %f1,%f21
clr %l3
fmovs %f0,%f20
clr %l4
fmovs %f1,%f19
clr %l5
fmovs %f0,%f18
clr %l6
fmovs %f1,%f17
clr %l7
fmovs %f0,%f16
clr %i0
fmovs %f1,%f15
clr %i1
fmovs %f0,%f14
clr %i2
fmovs %f1,%f13
clr %i3
fmovs %f0,%f12
clr %i4
fmovs %f1,%f11
clr %i5
fmovs %f0,%f10
clr %g1
fmovs %f1,%f9
clr %g2
fmovs %f0,%f8
clr %g3
fmovs %f1,%f7
clr %g4
fmovs %f0,%f6
clr %g5
fmovs %f1,%f5
fmovs %f0,%f4
fmovs %f1,%f3
fmovs %f0,%f2
add %fp,BIAS,%i0 ! return pointer to callers top of stack
ret
restore
.zero: .long 0x0,0x0
.PIC.zero.up:
retl
add %o0,%o7,%o0
#ifdef DEBUG
.global walk_reg_wins
.type walk_reg_wins,#function
walk_reg_wins:
#endif
.walk.reg.wins:
save %sp,FRAME,%sp
cmp %i7,%o7
be 2f
clr %o0
cmp %o7,0 ! compiler never cleans %o7...
be 1f ! could have been a leaf function...
clr %o1
call .walk.reg.wins
nop
1: clr %o2
clr %o3
clr %o4
clr %o5
clr %o7
clr %l0
clr %l1
clr %l2
clr %l3
clr %l4
clr %l5
clr %l6
clr %l7
add %o0,1,%i0 ! used for debugging
2: ret
restore
.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
.global OPENSSL_atomic_add
.type OPENSSL_atomic_add,#function
.align 32
OPENSSL_atomic_add:
#ifndef ABI64
subcc %g0,1,%o2
.word 0x95408000 !rd %ccr,%o2, see comment above
cmp %o2,0x99
be .v9
nop
save %sp,FRAME,%sp
ba .enter
nop
#ifdef __sun
! Note that you do not have to link with libthread to call thr_yield,
! as libc provides a stub, which is overloaded the moment you link
! with *either* libpthread or libthread...
#define YIELD_CPU thr_yield
#else
! applies at least to Linux and FreeBSD... Feedback expected...
#define YIELD_CPU sched_yield
#endif
.spin: call YIELD_CPU
nop
.enter: ld [%i0],%i2
cmp %i2,-4096
be .spin
mov -1,%i2
swap [%i0],%i2
cmp %i2,-1
be .spin
add %i2,%i1,%i2
stbar
st %i2,[%i0]
sra %i2,%g0,%i0
ret
restore
.v9:
#endif
ld [%o0],%o2
1: add %o1,%o2,%o3
.word 0xd7e2100a !cas [%o0],%o2,%o3, compare [%o0] with %o2 and swap %o3
cmp %o2,%o3
bne 1b
mov %o3,%o2 ! cas is always fetching to dest. register
add %o1,%o2,%o0 ! OpenSSL expects the new value
retl
sra %o0,%g0,%o0 ! we return signed int, remember?
.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
.global _sparcv9_rdtick
.align 32
_sparcv9_rdtick:
subcc %g0,1,%o0
.word 0x91408000 !rd %ccr,%o0
cmp %o0,0x99
bne .notick
xor %o0,%o0,%o0
.word 0x91410000 !rd %tick,%o0
retl
.word 0x93323020 !srlx %o0,32,%o1
.notick:
retl
xor %o1,%o1,%o1
.type _sparcv9_rdtick,#function
.size _sparcv9_rdtick,.-_sparcv9_rdtick
.global _sparcv9_vis1_probe
.align 8
_sparcv9_vis1_probe:
add %sp,BIAS+2,%o1
.word 0xc19a5a40 !ldda [%o1]ASI_FP16_P,%f0
retl
.word 0x81b00d80 !fxor %f0,%f0,%f0
.type _sparcv9_vis1_probe,#function
.size _sparcv9_vis1_probe,.-_sparcv9_vis1_probe
! Probe and instrument VIS1 instruction. Output is number of cycles it
! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
! is slow (documented to be 6 cycles on T2) and the core is in-order
! single-issue, it should be possible to distinguish Tx reliably...
! Observed return values are:
!
! UltraSPARC IIe 7
! UltraSPARC III 7
! UltraSPARC T1 24
!
! Numbers for T2 and SPARC64 V-VII are more than welcomed.
!
! It would be possible to detect specifically US-T1 by instrumenting
! fmul8ulx16, which is emulated on T1 and as such accounts for quite
! a lot of %tick-s, couple of thousand on Linux...
.global _sparcv9_vis1_instrument
.align 8
_sparcv9_vis1_instrument:
.word 0x91410000 !rd %tick,%o0
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x93410000 !rd %tick,%o1
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x95410000 !rd %tick,%o2
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x97410000 !rd %tick,%o3
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
.word 0x99410000 !rd %tick,%o4
! calculate intervals
sub %o1,%o0,%o0
sub %o2,%o1,%o1
sub %o3,%o2,%o2
sub %o4,%o3,%o3
! find minumum value
cmp %o0,%o1
.word 0x38680002 !bgu,a %xcc,.+8
mov %o1,%o0
cmp %o0,%o2
.word 0x38680002 !bgu,a %xcc,.+8
mov %o2,%o0
cmp %o0,%o3
.word 0x38680002 !bgu,a %xcc,.+8
mov %o3,%o0
retl
nop
.type _sparcv9_vis1_instrument,#function
.size _sparcv9_vis1_instrument,.-_sparcv9_vis1_instrument
.global _sparcv9_vis2_probe
.align 8
_sparcv9_vis2_probe:
retl
.word 0x81b00980 !bshuffle %f0,%f0,%f0
.type _sparcv9_vis2_probe,#function
.size _sparcv9_vis2_probe,.-_sparcv9_vis2_probe
.global _sparcv9_fmadd_probe
.align 8
_sparcv9_fmadd_probe:
.word 0x81b00d80 !fxor %f0,%f0,%f0
.word 0x85b08d82 !fxor %f2,%f2,%f2
retl
.word 0x81b80440 !fmaddd %f0,%f0,%f2,%f0
.type _sparcv9_fmadd_probe,#function
.size _sparcv9_fmadd_probe,.-_sparcv9_fmadd_probe
.global OPENSSL_cleanse
.align 32
OPENSSL_cleanse:
cmp %o1,14
nop
#ifdef ABI64
bgu %xcc,.Lot
#else
bgu .Lot
#endif
cmp %o1,0
bne .Little
nop
retl
nop
.Little:
stb %g0,[%o0]
subcc %o1,1,%o1
bnz .Little
add %o0,1,%o0
retl
nop
.align 32
.Lot:
#ifndef ABI64
subcc %g0,1,%g1
! see above for explanation
.word 0x83408000 !rd %ccr,%g1
cmp %g1,0x99
bne .v8lot
nop
#endif
.v9lot: andcc %o0,7,%g0
bz .v9aligned
nop
stb %g0,[%o0]
sub %o1,1,%o1
ba .v9lot
add %o0,1,%o0
.align 16,0x01000000
.v9aligned:
.word 0xc0720000 !stx %g0,[%o0]
sub %o1,8,%o1
andcc %o1,-8,%g0
#ifdef ABI64
.word 0x126ffffd !bnz %xcc,.v9aligned
#else
.word 0x124ffffd !bnz %icc,.v9aligned
#endif
add %o0,8,%o0
cmp %o1,0
bne .Little
nop
retl
nop
#ifndef ABI64
.v8lot: andcc %o0,3,%g0
bz .v8aligned
nop
stb %g0,[%o0]
sub %o1,1,%o1
ba .v8lot
add %o0,1,%o0
nop
.v8aligned:
st %g0,[%o0]
sub %o1,4,%o1
andcc %o1,-4,%g0
bnz .v8aligned
add %o0,4,%o0
cmp %o1,0
bne .Little
nop
retl
nop
#endif
.type OPENSSL_cleanse,#function
.size OPENSSL_cleanse,.-OPENSSL_cleanse
.section ".init",#alloc,#execinstr
call OPENSSL_cpuid_setup
nop
|
al3xtjames/Clover
| 1,690
|
Library/OpensslLib/openssl-1.0.1e/crypto/s390xcpuid.S
|
.text
.globl OPENSSL_s390x_facilities
.type OPENSSL_s390x_facilities,@function
.align 16
OPENSSL_s390x_facilities:
lghi %r0,0
larl %r2,OPENSSL_s390xcap_P
stg %r0,8(%r2)
.long 0xb2b02000 # stfle 0(%r2)
brc 8,.Ldone
lghi %r0,1
.long 0xb2b02000 # stfle 0(%r2)
.Ldone:
lg %r2,0(%r2)
br %r14
.size OPENSSL_s390x_facilities,.-OPENSSL_s390x_facilities
.globl OPENSSL_rdtsc
.type OPENSSL_rdtsc,@function
.align 16
OPENSSL_rdtsc:
stck 16(%r15)
lg %r2,16(%r15)
br %r14
.size OPENSSL_rdtsc,.-OPENSSL_rdtsc
.globl OPENSSL_atomic_add
.type OPENSSL_atomic_add,@function
.align 16
OPENSSL_atomic_add:
l %r1,0(%r2)
.Lspin: lr %r0,%r1
ar %r0,%r3
cs %r1,%r0,0(%r2)
brc 4,.Lspin
lgfr %r2,%r0 # OpenSSL expects the new value
br %r14
.size OPENSSL_atomic_add,.-OPENSSL_atomic_add
.globl OPENSSL_wipe_cpu
.type OPENSSL_wipe_cpu,@function
.align 16
OPENSSL_wipe_cpu:
xgr %r0,%r0
xgr %r1,%r1
lgr %r2,%r15
xgr %r3,%r3
xgr %r4,%r4
lzdr %f0
lzdr %f1
lzdr %f2
lzdr %f3
lzdr %f4
lzdr %f5
lzdr %f6
lzdr %f7
br %r14
.size OPENSSL_wipe_cpu,.-OPENSSL_wipe_cpu
.globl OPENSSL_cleanse
.type OPENSSL_cleanse,@function
.align 16
OPENSSL_cleanse:
#if !defined(__s390x__) && !defined(__s390x)
llgfr %r3,%r3
#endif
lghi %r4,15
lghi %r0,0
clgr %r3,%r4
jh .Lot
clgr %r3,%r0
bcr 8,%r14
.Little:
stc %r0,0(%r2)
la %r2,1(%r2)
brctg %r3,.Little
br %r14
.align 4
.Lot: tmll %r2,7
jz .Laligned
stc %r0,0(%r2)
la %r2,1(%r2)
brctg %r3,.Lot
.Laligned:
srlg %r4,%r3,3
.Loop: stg %r0,0(%r2)
la %r2,8(%r2)
brctg %r4,.Loop
lghi %r4,7
ngr %r3,%r4
jnz .Little
br %r14
.size OPENSSL_cleanse,.-OPENSSL_cleanse
.section .init
brasl %r14,OPENSSL_cpuid_setup
.comm OPENSSL_s390xcap_P,16,8
|
al3xtjames/Clover
| 21,544
|
Library/OpensslLib/openssl-1.0.1e/crypto/md5/asm/md5-ia64.S
|
/* Copyright (c) 2005 Hewlett-Packard Development Company, L.P.
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
// Common registers are assigned as follows:
//
// COMMON
//
// t0 Const Tbl Ptr TPtr
// t1 Round Constant TRound
// t4 Block residual LenResid
// t5 Residual Data DTmp
//
// {in,out}0 Block 0 Cycle RotateM0
// {in,out}1 Block Value 12 M12
// {in,out}2 Block Value 8 M8
// {in,out}3 Block Value 4 M4
// {in,out}4 Block Value 0 M0
// {in,out}5 Block 1 Cycle RotateM1
// {in,out}6 Block Value 13 M13
// {in,out}7 Block Value 9 M9
// {in,out}8 Block Value 5 M5
// {in,out}9 Block Value 1 M1
// {in,out}10 Block 2 Cycle RotateM2
// {in,out}11 Block Value 14 M14
// {in,out}12 Block Value 10 M10
// {in,out}13 Block Value 6 M6
// {in,out}14 Block Value 2 M2
// {in,out}15 Block 3 Cycle RotateM3
// {in,out}16 Block Value 15 M15
// {in,out}17 Block Value 11 M11
// {in,out}18 Block Value 7 M7
// {in,out}19 Block Value 3 M3
// {in,out}20 Scratch Z
// {in,out}21 Scratch Y
// {in,out}22 Scratch X
// {in,out}23 Scratch W
// {in,out}24 Digest A A
// {in,out}25 Digest B B
// {in,out}26 Digest C C
// {in,out}27 Digest D D
// {in,out}28 Active Data Ptr DPtr
// in28 Dummy Value -
// out28 Dummy Value -
// bt0 Coroutine Link QUICK_RTN
//
/// These predicates are used for computing the padding block(s) and
/// are shared between the driver and digest co-routines
//
// pt0 Extra Pad Block pExtra
// pt1 Load next word pLoad
// pt2 Skip next word pSkip
// pt3 Search for Pad pNoPad
// pt4 Pad Word 0 pPad0
// pt5 Pad Word 1 pPad1
// pt6 Pad Word 2 pPad2
// pt7 Pad Word 3 pPad3
#define DTmp r19
#define LenResid r18
#define QUICK_RTN b6
#define TPtr r14
#define TRound r15
#define pExtra p6
#define pLoad p7
#define pNoPad p9
#define pPad0 p10
#define pPad1 p11
#define pPad2 p12
#define pPad3 p13
#define pSkip p8
#define A_ out24
#define B_ out25
#define C_ out26
#define D_ out27
#define DPtr_ out28
#define M0_ out4
#define M1_ out9
#define M10_ out12
#define M11_ out17
#define M12_ out1
#define M13_ out6
#define M14_ out11
#define M15_ out16
#define M2_ out14
#define M3_ out19
#define M4_ out3
#define M5_ out8
#define M6_ out13
#define M7_ out18
#define M8_ out2
#define M9_ out7
#define RotateM0_ out0
#define RotateM1_ out5
#define RotateM2_ out10
#define RotateM3_ out15
#define W_ out23
#define X_ out22
#define Y_ out21
#define Z_ out20
#define A in24
#define B in25
#define C in26
#define D in27
#define DPtr in28
#define M0 in4
#define M1 in9
#define M10 in12
#define M11 in17
#define M12 in1
#define M13 in6
#define M14 in11
#define M15 in16
#define M2 in14
#define M3 in19
#define M4 in3
#define M5 in8
#define M6 in13
#define M7 in18
#define M8 in2
#define M9 in7
#define RotateM0 in0
#define RotateM1 in5
#define RotateM2 in10
#define RotateM3 in15
#define W in23
#define X in22
#define Y in21
#define Z in20
/* register stack configuration for md5_block_asm_data_order(): */
#define MD5_NINP 3
#define MD5_NLOC 0
#define MD5_NOUT 29
#define MD5_NROT 0
/* register stack configuration for helpers: */
#define _NINPUTS MD5_NOUT
#define _NLOCALS 0
#define _NOUTPUT 0
#define _NROTATE 24 /* this must be <= _NINPUTS */
#if defined(_HPUX_SOURCE) && !defined(_LP64)
#define ADDP addp4
#else
#define ADDP add
#endif
#if defined(_HPUX_SOURCE) || defined(B_ENDIAN)
#define HOST_IS_BIG_ENDIAN
#endif
// Macros for getting the left and right portions of little-endian words
#define GETLW(dst, src, align) dep.z dst = src, 32 - 8 * align, 8 * align
#define GETRW(dst, src, align) extr.u dst = src, 8 * align, 32 - 8 * align
// MD5 driver
//
// Reads an input block, then calls the digest block
// subroutine and adds the results to the accumulated
// digest. It allocates 32 outs which the subroutine
// uses as it's inputs and rotating
// registers. Initializes the round constant pointer and
// takes care of saving/restoring ar.lc
//
/// INPUT
//
// in0 Context Ptr CtxPtr0
// in1 Input Data Ptr DPtrIn
// in2 Integral Blocks BlockCount
// rp Return Address -
//
/// CODE
//
// v2 Input Align InAlign
// t0 Shared w/digest -
// t1 Shared w/digest -
// t2 Shared w/digest -
// t3 Shared w/digest -
// t4 Shared w/digest -
// t5 Shared w/digest -
// t6 PFS Save PFSSave
// t7 ar.lc Save LCSave
// t8 Saved PR PRSave
// t9 2nd CtxPtr CtxPtr1
// t10 Table Base CTable
// t11 Table[0] CTable0
// t13 Accumulator A AccumA
// t14 Accumulator B AccumB
// t15 Accumulator C AccumC
// t16 Accumulator D AccumD
// pt0 Shared w/digest -
// pt1 Shared w/digest -
// pt2 Shared w/digest -
// pt3 Shared w/digest -
// pt4 Shared w/digest -
// pt5 Shared w/digest -
// pt6 Shared w/digest -
// pt7 Shared w/digest -
// pt8 Not Aligned pOff
// pt8 Blocks Left pAgain
#define AccumA r27
#define AccumB r28
#define AccumC r29
#define AccumD r30
#define CTable r24
#define CTable0 r25
#define CtxPtr0 in0
#define CtxPtr1 r23
#define DPtrIn in1
#define BlockCount in2
#define InAlign r10
#define LCSave r21
#define PFSSave r20
#define PRSave r22
#define pAgain p63
#define pOff p63
.text
/* md5_block_asm_data_order(MD5_CTX *c, const void *data, size_t num)
where:
c: a pointer to a structure of this type:
typedef struct MD5state_st
{
MD5_LONG A,B,C,D;
MD5_LONG Nl,Nh;
MD5_LONG data[MD5_LBLOCK];
unsigned int num;
}
MD5_CTX;
data: a pointer to the input data (may be misaligned)
num: the number of 16-byte blocks to hash (i.e., the length
of DATA is 16*NUM.
*/
.type md5_block_asm_data_order, @function
.global md5_block_asm_data_order
.align 32
.proc md5_block_asm_data_order
md5_block_asm_data_order:
.md5_block:
.prologue
{ .mmi
.save ar.pfs, PFSSave
alloc PFSSave = ar.pfs, MD5_NINP, MD5_NLOC, MD5_NOUT, MD5_NROT
ADDP CtxPtr1 = 8, CtxPtr0
mov CTable = ip
}
{ .mmi
ADDP DPtrIn = 0, DPtrIn
ADDP CtxPtr0 = 0, CtxPtr0
.save ar.lc, LCSave
mov LCSave = ar.lc
}
;;
{ .mmi
add CTable = .md5_tbl_data_order#-.md5_block#, CTable
and InAlign = 0x3, DPtrIn
}
{ .mmi
ld4 AccumA = [CtxPtr0], 4
ld4 AccumC = [CtxPtr1], 4
.save pr, PRSave
mov PRSave = pr
.body
}
;;
{ .mmi
ld4 AccumB = [CtxPtr0]
ld4 AccumD = [CtxPtr1]
dep DPtr_ = 0, DPtrIn, 0, 2
} ;;
#ifdef HOST_IS_BIG_ENDIAN
rum psr.be;; // switch to little-endian
#endif
{ .mmb
ld4 CTable0 = [CTable], 4
cmp.ne pOff, p0 = 0, InAlign
(pOff) br.cond.spnt.many .md5_unaligned
} ;;
// The FF load/compute loop rotates values three times, so that
// loading into M12 here produces the M0 value, M13 -> M1, etc.
.md5_block_loop0:
{ .mmi
ld4 M12_ = [DPtr_], 4
mov TPtr = CTable
mov TRound = CTable0
} ;;
{ .mmi
ld4 M13_ = [DPtr_], 4
mov A_ = AccumA
mov B_ = AccumB
} ;;
{ .mmi
ld4 M14_ = [DPtr_], 4
mov C_ = AccumC
mov D_ = AccumD
} ;;
{ .mmb
ld4 M15_ = [DPtr_], 4
add BlockCount = -1, BlockCount
br.call.sptk.many QUICK_RTN = md5_digest_block0
} ;;
// Now, we add the new digest values and do some clean-up
// before checking if there's another full block to process
{ .mmi
add AccumA = AccumA, A_
add AccumB = AccumB, B_
cmp.ne pAgain, p0 = 0, BlockCount
}
{ .mib
add AccumC = AccumC, C_
add AccumD = AccumD, D_
(pAgain) br.cond.dptk.many .md5_block_loop0
} ;;
.md5_exit:
#ifdef HOST_IS_BIG_ENDIAN
sum psr.be;; // switch back to big-endian mode
#endif
{ .mmi
st4 [CtxPtr0] = AccumB, -4
st4 [CtxPtr1] = AccumD, -4
mov pr = PRSave, 0x1ffff ;;
}
{ .mmi
st4 [CtxPtr0] = AccumA
st4 [CtxPtr1] = AccumC
mov ar.lc = LCSave
} ;;
{ .mib
mov ar.pfs = PFSSave
br.ret.sptk.few rp
} ;;
#define MD5UNALIGNED(offset) \
.md5_process##offset: \
{ .mib ; \
nop 0x0 ; \
GETRW(DTmp, DTmp, offset) ; \
} ;; \
.md5_block_loop##offset: \
{ .mmi ; \
ld4 Y_ = [DPtr_], 4 ; \
mov TPtr = CTable ; \
mov TRound = CTable0 ; \
} ;; \
{ .mmi ; \
ld4 M13_ = [DPtr_], 4 ; \
mov A_ = AccumA ; \
mov B_ = AccumB ; \
} ;; \
{ .mii ; \
ld4 M14_ = [DPtr_], 4 ; \
GETLW(W_, Y_, offset) ; \
mov C_ = AccumC ; \
} \
{ .mmi ; \
mov D_ = AccumD ;; \
or M12_ = W_, DTmp ; \
GETRW(DTmp, Y_, offset) ; \
} \
{ .mib ; \
ld4 M15_ = [DPtr_], 4 ; \
add BlockCount = -1, BlockCount ; \
br.call.sptk.many QUICK_RTN = md5_digest_block##offset; \
} ;; \
{ .mmi ; \
add AccumA = AccumA, A_ ; \
add AccumB = AccumB, B_ ; \
cmp.ne pAgain, p0 = 0, BlockCount ; \
} \
{ .mib ; \
add AccumC = AccumC, C_ ; \
add AccumD = AccumD, D_ ; \
(pAgain) br.cond.dptk.many .md5_block_loop##offset ; \
} ;; \
{ .mib ; \
nop 0x0 ; \
nop 0x0 ; \
br.cond.sptk.many .md5_exit ; \
} ;;
.align 32
.md5_unaligned:
//
// Because variable shifts are expensive, we special case each of
// the four alignements. In practice, this won't hurt too much
// since only one working set of code will be loaded.
//
{ .mib
ld4 DTmp = [DPtr_], 4
cmp.eq pOff, p0 = 1, InAlign
(pOff) br.cond.dpnt.many .md5_process1
} ;;
{ .mib
cmp.eq pOff, p0 = 2, InAlign
nop 0x0
(pOff) br.cond.dpnt.many .md5_process2
} ;;
MD5UNALIGNED(3)
MD5UNALIGNED(1)
MD5UNALIGNED(2)
.endp md5_block_asm_data_order
// MD5 Perform the F function and load
//
// Passed the first 4 words (M0 - M3) and initial (A, B, C, D) values,
// computes the FF() round of functions, then branches to the common
// digest code to finish up with GG(), HH, and II().
//
// INPUT
//
// rp Return Address -
//
// CODE
//
// v0 PFS bit bucket PFS
// v1 Loop Trip Count LTrip
// pt0 Load next word pMore
/* For F round: */
#define LTrip r9
#define PFS r8
#define pMore p6
/* For GHI rounds: */
#define T r9
#define U r10
#define V r11
#define COMPUTE(a, b, s, M, R) \
{ \
.mii ; \
ld4 TRound = [TPtr], 4 ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ \
.mmi ; \
add a = Z, b ; \
mov R = M ; \
nop 0x0 ; \
} ;;
#define LOOP(a, b, s, M, R, label) \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ .mib ; \
add a = Z, b ; \
mov R = M ; \
br.ctop.sptk.many label ; \
} ;;
// G(B, C, D) = (B & D) | (C & ~D)
#define G(a, b, c, d, M) \
{ .mmi ; \
add Z = M, TRound ; \
and Y = b, d ; \
andcm X = c, d ; \
} ;; \
{ .mii ; \
add Z = Z, a ; \
or Y = Y, X ;; \
add Z = Z, Y ; \
} ;;
// H(B, C, D) = B ^ C ^ D
#define H(a, b, c, d, M) \
{ .mmi ; \
add Z = M, TRound ; \
xor Y = b, c ; \
nop 0x0 ; \
} ;; \
{ .mii ; \
add Z = Z, a ; \
xor Y = Y, d ;; \
add Z = Z, Y ; \
} ;;
// I(B, C, D) = C ^ (B | ~D)
//
// However, since we have an andcm operator, we use the fact that
//
// Y ^ Z == ~Y ^ ~Z
//
// to rewrite the expression as
//
// I(B, C, D) = ~C ^ (~B & D)
#define I(a, b, c, d, M) \
{ .mmi ; \
add Z = M, TRound ; \
andcm Y = d, b ; \
andcm X = -1, c ; \
} ;; \
{ .mii ; \
add Z = Z, a ; \
xor Y = Y, X ;; \
add Z = Z, Y ; \
} ;;
#define GG4(label) \
G(A, B, C, D, M0) \
COMPUTE(A, B, 5, M0, RotateM0) \
G(D, A, B, C, M1) \
COMPUTE(D, A, 9, M1, RotateM1) \
G(C, D, A, B, M2) \
COMPUTE(C, D, 14, M2, RotateM2) \
G(B, C, D, A, M3) \
LOOP(B, C, 20, M3, RotateM3, label)
#define HH4(label) \
H(A, B, C, D, M0) \
COMPUTE(A, B, 4, M0, RotateM0) \
H(D, A, B, C, M1) \
COMPUTE(D, A, 11, M1, RotateM1) \
H(C, D, A, B, M2) \
COMPUTE(C, D, 16, M2, RotateM2) \
H(B, C, D, A, M3) \
LOOP(B, C, 23, M3, RotateM3, label)
#define II4(label) \
I(A, B, C, D, M0) \
COMPUTE(A, B, 6, M0, RotateM0) \
I(D, A, B, C, M1) \
COMPUTE(D, A, 10, M1, RotateM1) \
I(C, D, A, B, M2) \
COMPUTE(C, D, 15, M2, RotateM2) \
I(B, C, D, A, M3) \
LOOP(B, C, 21, M3, RotateM3, label)
#define FFLOAD(a, b, c, d, M, N, s) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
add Z = Z, Y ;; \
dep.z Y = Z, 32, 32 ; \
} ;; \
{ .mii ; \
nop 0x0 ; \
shrp Z = Z, Y, 64 - s ;; \
add a = Z, b ; \
} ;;
#define FFLOOP(a, b, c, d, M, N, s, dest) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
add Z = Z, Y ;; \
dep.z Y = Z, 32, 32 ; \
} ;; \
{ .mii ; \
nop 0x0 ; \
shrp Z = Z, Y, 64 - s ;; \
add a = Z, b ; \
} \
{ .mib ; \
cmp.ne pMore, p0 = 0, LTrip ; \
add LTrip = -1, LTrip ; \
br.ctop.dptk.many dest ; \
} ;;
.type md5_digest_block0, @function
.align 32
.proc md5_digest_block0
.prologue
md5_digest_block0:
.altrp QUICK_RTN
.body
{ .mmi
alloc PFS = ar.pfs, _NINPUTS, _NLOCALS, _NOUTPUT, _NROTATE
mov LTrip = 2
mov ar.lc = 3
} ;;
{ .mii
cmp.eq pMore, p0 = r0, r0
mov ar.ec = 0
nop 0x0
} ;;
.md5_FF_round0:
FFLOAD(A, B, C, D, M12, RotateM0, 7)
FFLOAD(D, A, B, C, M13, RotateM1, 12)
FFLOAD(C, D, A, B, M14, RotateM2, 17)
FFLOOP(B, C, D, A, M15, RotateM3, 22, .md5_FF_round0)
//
// !!! Fall through to md5_digest_GHI
//
.endp md5_digest_block0
.type md5_digest_GHI, @function
.align 32
.proc md5_digest_GHI
.prologue
.regstk _NINPUTS, _NLOCALS, _NOUTPUT, _NROTATE
md5_digest_GHI:
.altrp QUICK_RTN
.body
//
// The following sequence shuffles the block counstants round for the
// next round:
//
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
// 1 6 11 0 5 10 14 4 9 14 3 8 13 2 7 12
//
{ .mmi
mov Z = M0
mov Y = M15
mov ar.lc = 3
}
{ .mmi
mov X = M2
mov W = M9
mov V = M4
} ;;
{ .mmi
mov M0 = M1
mov M15 = M12
mov ar.ec = 1
}
{ .mmi
mov M2 = M11
mov M9 = M14
mov M4 = M5
} ;;
{ .mmi
mov M1 = M6
mov M12 = M13
mov U = M3
}
{ .mmi
mov M11 = M8
mov M14 = M7
mov M5 = M10
} ;;
{ .mmi
mov M6 = Y
mov M13 = X
mov M3 = Z
}
{ .mmi
mov M8 = W
mov M7 = V
mov M10 = U
} ;;
.md5_GG_round:
GG4(.md5_GG_round)
// The following sequence shuffles the block constants round for the
// next round:
//
// 1 6 11 0 5 10 14 4 9 14 3 8 13 2 7 12
// 5 8 11 14 1 4 7 10 13 0 3 6 9 12 15 2
{ .mmi
mov Z = M0
mov Y = M1
mov ar.lc = 3
}
{ .mmi
mov X = M3
mov W = M5
mov V = M6
} ;;
{ .mmi
mov M0 = M4
mov M1 = M11
mov ar.ec = 1
}
{ .mmi
mov M3 = M9
mov U = M8
mov T = M13
} ;;
{ .mmi
mov M4 = Z
mov M11 = Y
mov M5 = M7
}
{ .mmi
mov M6 = M14
mov M8 = M12
mov M13 = M15
} ;;
{ .mmi
mov M7 = W
mov M14 = V
nop 0x0
}
{ .mmi
mov M9 = X
mov M12 = U
mov M15 = T
} ;;
.md5_HH_round:
HH4(.md5_HH_round)
// The following sequence shuffles the block constants round for the
// next round:
//
// 5 8 11 14 1 4 7 10 13 0 3 6 9 12 15 2
// 0 7 14 5 12 3 10 1 8 15 6 13 4 11 2 9
{ .mmi
mov Z = M0
mov Y = M15
mov ar.lc = 3
}
{ .mmi
mov X = M10
mov W = M1
mov V = M4
} ;;
{ .mmi
mov M0 = M9
mov M15 = M12
mov ar.ec = 1
}
{ .mmi
mov M10 = M11
mov M1 = M6
mov M4 = M13
} ;;
{ .mmi
mov M9 = M14
mov M12 = M5
mov U = M3
}
{ .mmi
mov M11 = M8
mov M6 = M7
mov M13 = M2
} ;;
{ .mmi
mov M14 = Y
mov M5 = X
mov M3 = Z
}
{ .mmi
mov M8 = W
mov M7 = V
mov M2 = U
} ;;
.md5_II_round:
II4(.md5_II_round)
{ .mib
nop 0x0
nop 0x0
br.ret.sptk.many QUICK_RTN
} ;;
.endp md5_digest_GHI
#define FFLOADU(a, b, c, d, M, P, N, s, offset) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
GETLW(W, P, offset) ; \
add Z = Z, Y ; \
} ;; \
{ .mii ; \
or W = W, DTmp ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ .mii ; \
add a = Z, b ; \
GETRW(DTmp, P, offset) ; \
mov P = W ; \
} ;;
#define FFLOOPU(a, b, c, d, M, P, N, s, offset) \
{ .mii ; \
(pMore) ld4 N = [DPtr], 4 ; \
add Z = M, TRound ; \
and Y = c, b ; \
} \
{ .mmi ; \
andcm X = d, b ;; \
add Z = Z, a ; \
or Y = Y, X ; \
} ;; \
{ .mii ; \
ld4 TRound = [TPtr], 4 ; \
(pMore) GETLW(W, P, offset) ; \
add Z = Z, Y ; \
} ;; \
{ .mii ; \
(pMore) or W = W, DTmp ; \
dep.z Y = Z, 32, 32 ;; \
shrp Z = Z, Y, 64 - s ; \
} ;; \
{ .mii ; \
add a = Z, b ; \
(pMore) GETRW(DTmp, P, offset) ; \
(pMore) mov P = W ; \
} \
{ .mib ; \
cmp.ne pMore, p0 = 0, LTrip ; \
add LTrip = -1, LTrip ; \
br.ctop.sptk.many .md5_FF_round##offset ; \
} ;;
#define MD5FBLOCK(offset) \
.type md5_digest_block##offset, @function ; \
\
.align 32 ; \
.proc md5_digest_block##offset ; \
.prologue ; \
.altrp QUICK_RTN ; \
.body ; \
md5_digest_block##offset: \
{ .mmi ; \
alloc PFS = ar.pfs, _NINPUTS, _NLOCALS, _NOUTPUT, _NROTATE ; \
mov LTrip = 2 ; \
mov ar.lc = 3 ; \
} ;; \
{ .mii ; \
cmp.eq pMore, p0 = r0, r0 ; \
mov ar.ec = 0 ; \
nop 0x0 ; \
} ;; \
\
.pred.rel "mutex", pLoad, pSkip ; \
.md5_FF_round##offset: \
FFLOADU(A, B, C, D, M12, M13, RotateM0, 7, offset) \
FFLOADU(D, A, B, C, M13, M14, RotateM1, 12, offset) \
FFLOADU(C, D, A, B, M14, M15, RotateM2, 17, offset) \
FFLOOPU(B, C, D, A, M15, RotateM0, RotateM3, 22, offset) \
\
{ .mib ; \
nop 0x0 ; \
nop 0x0 ; \
br.cond.sptk.many md5_digest_GHI ; \
} ;; \
.endp md5_digest_block##offset
MD5FBLOCK(1)
MD5FBLOCK(2)
MD5FBLOCK(3)
.align 64
.type md5_constants, @object
md5_constants:
.md5_tbl_data_order: // To ensure little-endian data
// order, code as bytes.
data1 0x78, 0xa4, 0x6a, 0xd7 // 0
data1 0x56, 0xb7, 0xc7, 0xe8 // 1
data1 0xdb, 0x70, 0x20, 0x24 // 2
data1 0xee, 0xce, 0xbd, 0xc1 // 3
data1 0xaf, 0x0f, 0x7c, 0xf5 // 4
data1 0x2a, 0xc6, 0x87, 0x47 // 5
data1 0x13, 0x46, 0x30, 0xa8 // 6
data1 0x01, 0x95, 0x46, 0xfd // 7
data1 0xd8, 0x98, 0x80, 0x69 // 8
data1 0xaf, 0xf7, 0x44, 0x8b // 9
data1 0xb1, 0x5b, 0xff, 0xff // 10
data1 0xbe, 0xd7, 0x5c, 0x89 // 11
data1 0x22, 0x11, 0x90, 0x6b // 12
data1 0x93, 0x71, 0x98, 0xfd // 13
data1 0x8e, 0x43, 0x79, 0xa6 // 14
data1 0x21, 0x08, 0xb4, 0x49 // 15
data1 0x62, 0x25, 0x1e, 0xf6 // 16
data1 0x40, 0xb3, 0x40, 0xc0 // 17
data1 0x51, 0x5a, 0x5e, 0x26 // 18
data1 0xaa, 0xc7, 0xb6, 0xe9 // 19
data1 0x5d, 0x10, 0x2f, 0xd6 // 20
data1 0x53, 0x14, 0x44, 0x02 // 21
data1 0x81, 0xe6, 0xa1, 0xd8 // 22
data1 0xc8, 0xfb, 0xd3, 0xe7 // 23
data1 0xe6, 0xcd, 0xe1, 0x21 // 24
data1 0xd6, 0x07, 0x37, 0xc3 // 25
data1 0x87, 0x0d, 0xd5, 0xf4 // 26
data1 0xed, 0x14, 0x5a, 0x45 // 27
data1 0x05, 0xe9, 0xe3, 0xa9 // 28
data1 0xf8, 0xa3, 0xef, 0xfc // 29
data1 0xd9, 0x02, 0x6f, 0x67 // 30
data1 0x8a, 0x4c, 0x2a, 0x8d // 31
data1 0x42, 0x39, 0xfa, 0xff // 32
data1 0x81, 0xf6, 0x71, 0x87 // 33
data1 0x22, 0x61, 0x9d, 0x6d // 34
data1 0x0c, 0x38, 0xe5, 0xfd // 35
data1 0x44, 0xea, 0xbe, 0xa4 // 36
data1 0xa9, 0xcf, 0xde, 0x4b // 37
data1 0x60, 0x4b, 0xbb, 0xf6 // 38
data1 0x70, 0xbc, 0xbf, 0xbe // 39
data1 0xc6, 0x7e, 0x9b, 0x28 // 40
data1 0xfa, 0x27, 0xa1, 0xea // 41
data1 0x85, 0x30, 0xef, 0xd4 // 42
data1 0x05, 0x1d, 0x88, 0x04 // 43
data1 0x39, 0xd0, 0xd4, 0xd9 // 44
data1 0xe5, 0x99, 0xdb, 0xe6 // 45
data1 0xf8, 0x7c, 0xa2, 0x1f // 46
data1 0x65, 0x56, 0xac, 0xc4 // 47
data1 0x44, 0x22, 0x29, 0xf4 // 48
data1 0x97, 0xff, 0x2a, 0x43 // 49
data1 0xa7, 0x23, 0x94, 0xab // 50
data1 0x39, 0xa0, 0x93, 0xfc // 51
data1 0xc3, 0x59, 0x5b, 0x65 // 52
data1 0x92, 0xcc, 0x0c, 0x8f // 53
data1 0x7d, 0xf4, 0xef, 0xff // 54
data1 0xd1, 0x5d, 0x84, 0x85 // 55
data1 0x4f, 0x7e, 0xa8, 0x6f // 56
data1 0xe0, 0xe6, 0x2c, 0xfe // 57
data1 0x14, 0x43, 0x01, 0xa3 // 58
data1 0xa1, 0x11, 0x08, 0x4e // 59
data1 0x82, 0x7e, 0x53, 0xf7 // 60
data1 0x35, 0xf2, 0x3a, 0xbd // 61
data1 0xbb, 0xd2, 0xd7, 0x2a // 62
data1 0x91, 0xd3, 0x86, 0xeb // 63
.size md5_constants#,64*4
|
al3xtjames/Clover
| 28,245
|
Library/OpensslLib/openssl-1.0.1e/crypto/bn/asm/sparcv8.S
|
.ident "sparcv8.s, Version 1.4"
.ident "SPARC v8 ISA artwork by Andy Polyakov <appro@fy.chalmers.se>"
/*
* ====================================================================
* Written by Andy Polyakov <appro@fy.chalmers.se> for the OpenSSL
* project.
*
* Rights for redistribution and usage in source and binary forms are
* granted according to the OpenSSL license. Warranty of any kind is
* disclaimed.
* ====================================================================
*/
/*
* This is my modest contributon to OpenSSL project (see
* http://www.openssl.org/ for more information about it) and is
* a drop-in SuperSPARC ISA replacement for crypto/bn/bn_asm.c
* module. For updates see http://fy.chalmers.se/~appro/hpe/.
*
* See bn_asm.sparc.v8plus.S for more details.
*/
/*
* Revision history.
*
* 1.1 - new loop unrolling model(*);
* 1.2 - made gas friendly;
* 1.3 - fixed problem with /usr/ccs/lib/cpp;
* 1.4 - some retunes;
*
* (*) see bn_asm.sparc.v8plus.S for details
*/
.section ".text",#alloc,#execinstr
.file "bn_asm.sparc.v8.S"
.align 32
.global bn_mul_add_words
/*
* BN_ULONG bn_mul_add_words(rp,ap,num,w)
* BN_ULONG *rp,*ap;
* int num;
* BN_ULONG w;
*/
bn_mul_add_words:
cmp %o2,0
bg,a .L_bn_mul_add_words_proceed
ld [%o1],%g2
retl
clr %o0
.L_bn_mul_add_words_proceed:
andcc %o2,-4,%g0
bz .L_bn_mul_add_words_tail
clr %o5
.L_bn_mul_add_words_loop:
ld [%o0],%o4
ld [%o1+4],%g3
umul %o3,%g2,%g2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
st %o4,[%o0]
addx %g1,0,%o5
ld [%o0+4],%o4
ld [%o1+8],%g2
umul %o3,%g3,%g3
dec 4,%o2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g3,%o4
st %o4,[%o0+4]
addx %g1,0,%o5
ld [%o0+8],%o4
ld [%o1+12],%g3
umul %o3,%g2,%g2
inc 16,%o1
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
st %o4,[%o0+8]
addx %g1,0,%o5
ld [%o0+12],%o4
umul %o3,%g3,%g3
inc 16,%o0
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g3,%o4
st %o4,[%o0-4]
addx %g1,0,%o5
andcc %o2,-4,%g0
bnz,a .L_bn_mul_add_words_loop
ld [%o1],%g2
tst %o2
bnz,a .L_bn_mul_add_words_tail
ld [%o1],%g2
.L_bn_mul_add_words_return:
retl
mov %o5,%o0
nop
.L_bn_mul_add_words_tail:
ld [%o0],%o4
umul %o3,%g2,%g2
addcc %o4,%o5,%o4
rd %y,%g1
addx %g1,0,%g1
addcc %o4,%g2,%o4
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_add_words_return
st %o4,[%o0]
ld [%o1+4],%g2
ld [%o0+4],%o4
umul %o3,%g2,%g2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_add_words_return
st %o4,[%o0+4]
ld [%o1+8],%g2
ld [%o0+8],%o4
umul %o3,%g2,%g2
rd %y,%g1
addcc %o4,%o5,%o4
addx %g1,0,%g1
addcc %o4,%g2,%o4
st %o4,[%o0+8]
retl
addx %g1,0,%o0
.type bn_mul_add_words,#function
.size bn_mul_add_words,(.-bn_mul_add_words)
.align 32
.global bn_mul_words
/*
* BN_ULONG bn_mul_words(rp,ap,num,w)
* BN_ULONG *rp,*ap;
* int num;
* BN_ULONG w;
*/
bn_mul_words:
cmp %o2,0
bg,a .L_bn_mul_words_proceeed
ld [%o1],%g2
retl
clr %o0
.L_bn_mul_words_proceeed:
andcc %o2,-4,%g0
bz .L_bn_mul_words_tail
clr %o5
.L_bn_mul_words_loop:
ld [%o1+4],%g3
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
addx %g1,0,%o5
st %g2,[%o0]
ld [%o1+8],%g2
umul %o3,%g3,%g3
addcc %g3,%o5,%g3
rd %y,%g1
dec 4,%o2
addx %g1,0,%o5
st %g3,[%o0+4]
ld [%o1+12],%g3
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
inc 16,%o1
st %g2,[%o0+8]
addx %g1,0,%o5
umul %o3,%g3,%g3
addcc %g3,%o5,%g3
rd %y,%g1
inc 16,%o0
addx %g1,0,%o5
st %g3,[%o0-4]
andcc %o2,-4,%g0
nop
bnz,a .L_bn_mul_words_loop
ld [%o1],%g2
tst %o2
bnz,a .L_bn_mul_words_tail
ld [%o1],%g2
.L_bn_mul_words_return:
retl
mov %o5,%o0
nop
.L_bn_mul_words_tail:
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_words_return
st %g2,[%o0]
nop
ld [%o1+4],%g2
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
addx %g1,0,%o5
deccc %o2
bz .L_bn_mul_words_return
st %g2,[%o0+4]
ld [%o1+8],%g2
umul %o3,%g2,%g2
addcc %g2,%o5,%g2
rd %y,%g1
st %g2,[%o0+8]
retl
addx %g1,0,%o0
.type bn_mul_words,#function
.size bn_mul_words,(.-bn_mul_words)
.align 32
.global bn_sqr_words
/*
* void bn_sqr_words(r,a,n)
* BN_ULONG *r,*a;
* int n;
*/
bn_sqr_words:
cmp %o2,0
bg,a .L_bn_sqr_words_proceeed
ld [%o1],%g2
retl
clr %o0
.L_bn_sqr_words_proceeed:
andcc %o2,-4,%g0
bz .L_bn_sqr_words_tail
clr %o5
.L_bn_sqr_words_loop:
ld [%o1+4],%g3
umul %g2,%g2,%o4
st %o4,[%o0]
rd %y,%o5
st %o5,[%o0+4]
ld [%o1+8],%g2
umul %g3,%g3,%o4
dec 4,%o2
st %o4,[%o0+8]
rd %y,%o5
st %o5,[%o0+12]
nop
ld [%o1+12],%g3
umul %g2,%g2,%o4
st %o4,[%o0+16]
rd %y,%o5
inc 16,%o1
st %o5,[%o0+20]
umul %g3,%g3,%o4
inc 32,%o0
st %o4,[%o0-8]
rd %y,%o5
st %o5,[%o0-4]
andcc %o2,-4,%g2
bnz,a .L_bn_sqr_words_loop
ld [%o1],%g2
tst %o2
nop
bnz,a .L_bn_sqr_words_tail
ld [%o1],%g2
.L_bn_sqr_words_return:
retl
clr %o0
.L_bn_sqr_words_tail:
umul %g2,%g2,%o4
st %o4,[%o0]
deccc %o2
rd %y,%o5
bz .L_bn_sqr_words_return
st %o5,[%o0+4]
ld [%o1+4],%g2
umul %g2,%g2,%o4
st %o4,[%o0+8]
deccc %o2
rd %y,%o5
nop
bz .L_bn_sqr_words_return
st %o5,[%o0+12]
ld [%o1+8],%g2
umul %g2,%g2,%o4
st %o4,[%o0+16]
rd %y,%o5
st %o5,[%o0+20]
retl
clr %o0
.type bn_sqr_words,#function
.size bn_sqr_words,(.-bn_sqr_words)
.align 32
.global bn_div_words
/*
* BN_ULONG bn_div_words(h,l,d)
* BN_ULONG h,l,d;
*/
bn_div_words:
wr %o0,%y
udiv %o1,%o2,%o0
retl
nop
.type bn_div_words,#function
.size bn_div_words,(.-bn_div_words)
.align 32
.global bn_add_words
/*
* BN_ULONG bn_add_words(rp,ap,bp,n)
* BN_ULONG *rp,*ap,*bp;
* int n;
*/
bn_add_words:
cmp %o3,0
bg,a .L_bn_add_words_proceed
ld [%o1],%o4
retl
clr %o0
.L_bn_add_words_proceed:
andcc %o3,-4,%g0
bz .L_bn_add_words_tail
clr %g1
ba .L_bn_add_words_warn_loop
addcc %g0,0,%g0 ! clear carry flag
.L_bn_add_words_loop:
ld [%o1],%o4
.L_bn_add_words_warn_loop:
ld [%o2],%o5
ld [%o1+4],%g3
ld [%o2+4],%g4
dec 4,%o3
addxcc %o5,%o4,%o5
st %o5,[%o0]
ld [%o1+8],%o4
ld [%o2+8],%o5
inc 16,%o1
addxcc %g3,%g4,%g3
st %g3,[%o0+4]
ld [%o1-4],%g3
ld [%o2+12],%g4
inc 16,%o2
addxcc %o5,%o4,%o5
st %o5,[%o0+8]
inc 16,%o0
addxcc %g3,%g4,%g3
st %g3,[%o0-4]
addx %g0,0,%g1
andcc %o3,-4,%g0
bnz,a .L_bn_add_words_loop
addcc %g1,-1,%g0
tst %o3
bnz,a .L_bn_add_words_tail
ld [%o1],%o4
.L_bn_add_words_return:
retl
mov %g1,%o0
.L_bn_add_words_tail:
addcc %g1,-1,%g0
ld [%o2],%o5
addxcc %o5,%o4,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_add_words_return
st %o5,[%o0]
ld [%o1+4],%o4
addcc %g1,-1,%g0
ld [%o2+4],%o5
addxcc %o5,%o4,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_add_words_return
st %o5,[%o0+4]
ld [%o1+8],%o4
addcc %g1,-1,%g0
ld [%o2+8],%o5
addxcc %o5,%o4,%o5
st %o5,[%o0+8]
retl
addx %g0,0,%o0
.type bn_add_words,#function
.size bn_add_words,(.-bn_add_words)
.align 32
.global bn_sub_words
/*
* BN_ULONG bn_sub_words(rp,ap,bp,n)
* BN_ULONG *rp,*ap,*bp;
* int n;
*/
bn_sub_words:
cmp %o3,0
bg,a .L_bn_sub_words_proceed
ld [%o1],%o4
retl
clr %o0
.L_bn_sub_words_proceed:
andcc %o3,-4,%g0
bz .L_bn_sub_words_tail
clr %g1
ba .L_bn_sub_words_warm_loop
addcc %g0,0,%g0 ! clear carry flag
.L_bn_sub_words_loop:
ld [%o1],%o4
.L_bn_sub_words_warm_loop:
ld [%o2],%o5
ld [%o1+4],%g3
ld [%o2+4],%g4
dec 4,%o3
subxcc %o4,%o5,%o5
st %o5,[%o0]
ld [%o1+8],%o4
ld [%o2+8],%o5
inc 16,%o1
subxcc %g3,%g4,%g4
st %g4,[%o0+4]
ld [%o1-4],%g3
ld [%o2+12],%g4
inc 16,%o2
subxcc %o4,%o5,%o5
st %o5,[%o0+8]
inc 16,%o0
subxcc %g3,%g4,%g4
st %g4,[%o0-4]
addx %g0,0,%g1
andcc %o3,-4,%g0
bnz,a .L_bn_sub_words_loop
addcc %g1,-1,%g0
tst %o3
nop
bnz,a .L_bn_sub_words_tail
ld [%o1],%o4
.L_bn_sub_words_return:
retl
mov %g1,%o0
.L_bn_sub_words_tail:
addcc %g1,-1,%g0
ld [%o2],%o5
subxcc %o4,%o5,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_sub_words_return
st %o5,[%o0]
nop
ld [%o1+4],%o4
addcc %g1,-1,%g0
ld [%o2+4],%o5
subxcc %o4,%o5,%o5
addx %g0,0,%g1
deccc %o3
bz .L_bn_sub_words_return
st %o5,[%o0+4]
ld [%o1+8],%o4
addcc %g1,-1,%g0
ld [%o2+8],%o5
subxcc %o4,%o5,%o5
st %o5,[%o0+8]
retl
addx %g0,0,%o0
.type bn_sub_words,#function
.size bn_sub_words,(.-bn_sub_words)
#define FRAME_SIZE -96
/*
* Here is register usage map for *all* routines below.
*/
#define t_1 %o0
#define t_2 %o1
#define c_1 %o2
#define c_2 %o3
#define c_3 %o4
#define ap(I) [%i1+4*I]
#define bp(I) [%i2+4*I]
#define rp(I) [%i0+4*I]
#define a_0 %l0
#define a_1 %l1
#define a_2 %l2
#define a_3 %l3
#define a_4 %l4
#define a_5 %l5
#define a_6 %l6
#define a_7 %l7
#define b_0 %i3
#define b_1 %i4
#define b_2 %i5
#define b_3 %o5
#define b_4 %g1
#define b_5 %g2
#define b_6 %g3
#define b_7 %g4
.align 32
.global bn_mul_comba8
/*
* void bn_mul_comba8(r,a,b)
* BN_ULONG *r,*a,*b;
*/
bn_mul_comba8:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
ld bp(0),b_0
umul a_0,b_0,c_1 !=!mul_add_c(a[0],b[0],c1,c2,c3);
ld bp(1),b_1
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
umul a_0,b_1,t_1 !=!mul_add_c(a[0],b[1],c2,c3,c1);
ld ap(1),a_1
addcc c_2,t_1,c_2
rd %y,t_2
addxcc %g0,t_2,c_3 !=
addx %g0,%g0,c_1
ld ap(2),a_2
umul a_1,b_0,t_1 !mul_add_c(a[1],b[0],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
st c_2,rp(1) !r[1]=c2;
addx c_1,%g0,c_1 !=
umul a_2,b_0,t_1 !mul_add_c(a[2],b[0],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx %g0,%g0,c_2
ld bp(2),b_2
umul a_1,b_1,t_1 !mul_add_c(a[1],b[1],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
ld bp(3),b_3
addx c_2,%g0,c_2 !=
umul a_0,b_2,t_1 !mul_add_c(a[0],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
st c_3,rp(2) !r[2]=c3;
umul a_0,b_3,t_1 !mul_add_c(a[0],b[3],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
umul a_1,b_2,t_1 !=!mul_add_c(a[1],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
ld ap(3),a_3
umul a_2,b_1,t_1 !mul_add_c(a[2],b[1],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
ld ap(4),a_4
umul a_3,b_0,t_1 !mul_add_c(a[3],b[0],c1,c2,c3);!=
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_4,b_0,t_1 !mul_add_c(a[4],b[0],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
umul a_3,b_1,t_1 !mul_add_c(a[3],b[1],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_2,b_2,t_1 !=!mul_add_c(a[2],b[2],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
ld bp(4),b_4
umul a_1,b_3,t_1 !mul_add_c(a[1],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
ld bp(5),b_5
umul a_0,b_4,t_1 !=!mul_add_c(a[0],b[4],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(4) !r[4]=c2;
umul a_0,b_5,t_1 !mul_add_c(a[0],b[5],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
umul a_1,b_4,t_1 !mul_add_c(a[1],b[4],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_2,b_3,t_1 !=!mul_add_c(a[2],b[3],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_3,b_2,t_1 !mul_add_c(a[3],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
ld ap(5),a_5
umul a_4,b_1,t_1 !mul_add_c(a[4],b[1],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
ld ap(6),a_6
addx c_2,%g0,c_2 !=
umul a_5,b_0,t_1 !mul_add_c(a[5],b[0],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
st c_3,rp(5) !r[5]=c3;
umul a_6,b_0,t_1 !mul_add_c(a[6],b[0],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
umul a_5,b_1,t_1 !=!mul_add_c(a[5],b[1],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_4,b_2,t_1 !mul_add_c(a[4],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
umul a_3,b_3,t_1 !mul_add_c(a[3],b[3],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_2,b_4,t_1 !mul_add_c(a[2],b[4],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
ld bp(6),b_6
addx c_3,%g0,c_3 !=
umul a_1,b_5,t_1 !mul_add_c(a[1],b[5],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
ld bp(7),b_7
umul a_0,b_6,t_1 !mul_add_c(a[0],b[6],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
st c_1,rp(6) !r[6]=c1;
addx c_3,%g0,c_3 !=
umul a_0,b_7,t_1 !mul_add_c(a[0],b[7],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx %g0,%g0,c_1
umul a_1,b_6,t_1 !mul_add_c(a[1],b[6],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_2,b_5,t_1 !mul_add_c(a[2],b[5],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_3,b_4,t_1 !=!mul_add_c(a[3],b[4],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
umul a_4,b_3,t_1 !mul_add_c(a[4],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_5,b_2,t_1 !mul_add_c(a[5],b[2],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
ld ap(7),a_7
umul a_6,b_1,t_1 !=!mul_add_c(a[6],b[1],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
umul a_7,b_0,t_1 !mul_add_c(a[7],b[0],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
st c_2,rp(7) !r[7]=c2;
umul a_7,b_1,t_1 !mul_add_c(a[7],b[1],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
umul a_6,b_2,t_1 !=!mul_add_c(a[6],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_5,b_3,t_1 !mul_add_c(a[5],b[3],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
umul a_4,b_4,t_1 !mul_add_c(a[4],b[4],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_3,b_5,t_1 !mul_add_c(a[3],b[5],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_2,b_6,t_1 !=!mul_add_c(a[2],b[6],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_1,b_7,t_1 !mul_add_c(a[1],b[7],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !
addx c_2,%g0,c_2
st c_3,rp(8) !r[8]=c3;
umul a_2,b_7,t_1 !mul_add_c(a[2],b[7],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
umul a_3,b_6,t_1 !=!mul_add_c(a[3],b[6],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_4,b_5,t_1 !mul_add_c(a[4],b[5],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
umul a_5,b_4,t_1 !mul_add_c(a[5],b[4],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_6,b_3,t_1 !mul_add_c(a[6],b[3],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_7,b_2,t_1 !=!mul_add_c(a[7],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(9) !r[9]=c1;
umul a_7,b_3,t_1 !mul_add_c(a[7],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
umul a_6,b_4,t_1 !mul_add_c(a[6],b[4],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_5,b_5,t_1 !=!mul_add_c(a[5],b[5],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
umul a_4,b_6,t_1 !mul_add_c(a[4],b[6],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_3,b_7,t_1 !mul_add_c(a[3],b[7],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(10) !r[10]=c2;
umul a_4,b_7,t_1 !=!mul_add_c(a[4],b[7],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2 !=
umul a_5,b_6,t_1 !mul_add_c(a[5],b[6],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
umul a_6,b_5,t_1 !mul_add_c(a[6],b[5],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_7,b_4,t_1 !mul_add_c(a[7],b[4],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(11) !r[11]=c3;
addx c_2,%g0,c_2 !=
umul a_7,b_5,t_1 !mul_add_c(a[7],b[5],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
umul a_6,b_6,t_1 !mul_add_c(a[6],b[6],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_5,b_7,t_1 !mul_add_c(a[5],b[7],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
st c_1,rp(12) !r[12]=c1;
addx c_3,%g0,c_3 !=
umul a_6,b_7,t_1 !mul_add_c(a[6],b[7],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3 !=
addx %g0,%g0,c_1
umul a_7,b_6,t_1 !mul_add_c(a[7],b[6],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(13) !r[13]=c2;
umul a_7,b_7,t_1 !=!mul_add_c(a[7],b[7],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
nop !=
st c_3,rp(14) !r[14]=c3;
st c_1,rp(15) !r[15]=c1;
ret
restore %g0,%g0,%o0
.type bn_mul_comba8,#function
.size bn_mul_comba8,(.-bn_mul_comba8)
.align 32
.global bn_mul_comba4
/*
* void bn_mul_comba4(r,a,b)
* BN_ULONG *r,*a,*b;
*/
bn_mul_comba4:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
ld bp(0),b_0
umul a_0,b_0,c_1 !=!mul_add_c(a[0],b[0],c1,c2,c3);
ld bp(1),b_1
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
umul a_0,b_1,t_1 !=!mul_add_c(a[0],b[1],c2,c3,c1);
ld ap(1),a_1
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc %g0,t_2,c_3
addx %g0,%g0,c_1
ld ap(2),a_2
umul a_1,b_0,t_1 !=!mul_add_c(a[1],b[0],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(1) !r[1]=c2;
umul a_2,b_0,t_1 !mul_add_c(a[2],b[0],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
ld bp(2),b_2
umul a_1,b_1,t_1 !=!mul_add_c(a[1],b[1],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
ld bp(3),b_3
umul a_0,b_2,t_1 !mul_add_c(a[0],b[2],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
st c_3,rp(2) !r[2]=c3;
umul a_0,b_3,t_1 !=!mul_add_c(a[0],b[3],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3 !=
umul a_1,b_2,t_1 !mul_add_c(a[1],b[2],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
ld ap(3),a_3
umul a_2,b_1,t_1 !mul_add_c(a[2],b[1],c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_3,b_0,t_1 !=!mul_add_c(a[3],b[0],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_3,b_1,t_1 !mul_add_c(a[3],b[1],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
umul a_2,b_2,t_1 !mul_add_c(a[2],b[2],c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
umul a_1,b_3,t_1 !=!mul_add_c(a[1],b[3],c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(4) !r[4]=c2;
umul a_2,b_3,t_1 !mul_add_c(a[2],b[3],c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
umul a_3,b_2,t_1 !mul_add_c(a[3],b[2],c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(5) !r[5]=c3;
addx c_2,%g0,c_2 !=
umul a_3,b_3,t_1 !mul_add_c(a[3],b[3],c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
st c_1,rp(6) !r[6]=c1;
st c_2,rp(7) !r[7]=c2;
ret
restore %g0,%g0,%o0
.type bn_mul_comba4,#function
.size bn_mul_comba4,(.-bn_mul_comba4)
.align 32
.global bn_sqr_comba8
bn_sqr_comba8:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
ld ap(1),a_1
umul a_0,a_0,c_1 !=!sqr_add_c(a,0,c1,c2,c3);
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
ld ap(2),a_2
umul a_0,a_1,t_1 !=!sqr_add_c2(a,1,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc %g0,t_2,c_3
addx %g0,%g0,c_1 !=
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3
st c_2,rp(1) !r[1]=c2;
addx c_1,%g0,c_1 !=
umul a_2,a_0,t_1 !sqr_add_c2(a,2,0,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx %g0,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
ld ap(3),a_3
umul a_1,a_1,t_1 !sqr_add_c(a,1,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
st c_3,rp(2) !r[2]=c3;
umul a_0,a_3,t_1 !=!sqr_add_c2(a,3,0,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3 !=
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
ld ap(4),a_4
addx c_3,%g0,c_3 !=
umul a_1,a_2,t_1 !sqr_add_c2(a,2,1,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_4,a_0,t_1 !sqr_add_c2(a,4,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_3,a_1,t_1 !sqr_add_c2(a,3,1,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
ld ap(5),a_5
umul a_2,a_2,t_1 !sqr_add_c(a,2,c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
st c_2,rp(4) !r[4]=c2;
addx c_1,%g0,c_1 !=
umul a_0,a_5,t_1 !sqr_add_c2(a,5,0,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx %g0,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
umul a_1,a_4,t_1 !sqr_add_c2(a,4,1,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
ld ap(6),a_6
umul a_2,a_3,t_1 !sqr_add_c2(a,3,2,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
st c_3,rp(5) !r[5]=c3;
umul a_6,a_0,t_1 !sqr_add_c2(a,6,0,c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx %g0,%g0,c_3
addcc c_1,t_1,c_1 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_5,a_1,t_1 !sqr_add_c2(a,5,1,c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
addcc c_1,t_1,c_1 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
umul a_4,a_2,t_1 !sqr_add_c2(a,4,2,c1,c2,c3);
addcc c_1,t_1,c_1 !=
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
addcc c_1,t_1,c_1 !=
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3
ld ap(7),a_7
umul a_3,a_3,t_1 !=!sqr_add_c(a,3,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(6) !r[6]=c1;
umul a_0,a_7,t_1 !sqr_add_c2(a,7,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_1,a_6,t_1 !sqr_add_c2(a,6,1,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_2,a_5,t_1 !sqr_add_c2(a,5,2,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_3,a_4,t_1 !sqr_add_c2(a,4,3,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
st c_2,rp(7) !r[7]=c2;
umul a_7,a_1,t_1 !sqr_add_c2(a,7,1,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
addcc c_3,t_1,c_3 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_6,a_2,t_1 !sqr_add_c2(a,6,2,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
addcc c_3,t_1,c_3 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_5,a_3,t_1 !sqr_add_c2(a,5,3,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
addcc c_3,t_1,c_3 !=
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_4,a_4,t_1 !sqr_add_c(a,4,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(8) !r[8]=c3;
addx c_2,%g0,c_2 !=
umul a_2,a_7,t_1 !sqr_add_c2(a,7,2,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_3,a_6,t_1 !sqr_add_c2(a,6,3,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_4,a_5,t_1 !sqr_add_c2(a,5,4,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(9) !r[9]=c1;
umul a_7,a_3,t_1 !sqr_add_c2(a,7,3,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_6,a_4,t_1 !sqr_add_c2(a,6,4,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_5,a_5,t_1 !sqr_add_c(a,5,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(10) !r[10]=c2;
umul a_4,a_7,t_1 !=!sqr_add_c2(a,7,4,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2 !=
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2
umul a_5,a_6,t_1 !=!sqr_add_c2(a,6,5,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx c_2,%g0,c_2 !=
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
st c_3,rp(11) !r[11]=c3;
addx c_2,%g0,c_2 !=
umul a_7,a_5,t_1 !sqr_add_c2(a,7,5,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_6,a_6,t_1 !sqr_add_c(a,6,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
st c_1,rp(12) !r[12]=c1;
umul a_6,a_7,t_1 !sqr_add_c2(a,7,6,c2,c3,c1);
addcc c_2,t_1,c_2 !=
rd %y,t_2
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2 !=
addxcc c_3,t_2,c_3
st c_2,rp(13) !r[13]=c2;
addx c_1,%g0,c_1 !=
umul a_7,a_7,t_1 !sqr_add_c(a,7,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1 !=
st c_3,rp(14) !r[14]=c3;
st c_1,rp(15) !r[15]=c1;
ret
restore %g0,%g0,%o0
.type bn_sqr_comba8,#function
.size bn_sqr_comba8,(.-bn_sqr_comba8)
.align 32
.global bn_sqr_comba4
/*
* void bn_sqr_comba4(r,a)
* BN_ULONG *r,*a;
*/
bn_sqr_comba4:
save %sp,FRAME_SIZE,%sp
ld ap(0),a_0
umul a_0,a_0,c_1 !sqr_add_c(a,0,c1,c2,c3);
ld ap(1),a_1 !=
rd %y,c_2
st c_1,rp(0) !r[0]=c1;
ld ap(2),a_2
umul a_0,a_1,t_1 !=!sqr_add_c2(a,1,0,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2
addxcc %g0,t_2,c_3
addx %g0,%g0,c_1 !=
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1 !=
st c_2,rp(1) !r[1]=c2;
umul a_2,a_0,t_1 !sqr_add_c2(a,2,0,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2 !=
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1 !=
addx c_2,%g0,c_2
ld ap(3),a_3
umul a_1,a_1,t_1 !sqr_add_c(a,1,c3,c1,c2);
addcc c_3,t_1,c_3 !=
rd %y,t_2
addxcc c_1,t_2,c_1
st c_3,rp(2) !r[2]=c3;
addx c_2,%g0,c_2 !=
umul a_0,a_3,t_1 !sqr_add_c2(a,3,0,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx %g0,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
umul a_1,a_2,t_1 !sqr_add_c2(a,2,1,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
addx c_3,%g0,c_3
addcc c_1,t_1,c_1
addxcc c_2,t_2,c_2
addx c_3,%g0,c_3 !=
st c_1,rp(3) !r[3]=c1;
umul a_3,a_1,t_1 !sqr_add_c2(a,3,1,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx %g0,%g0,c_1
addcc c_2,t_1,c_2
addxcc c_3,t_2,c_3 !=
addx c_1,%g0,c_1
umul a_2,a_2,t_1 !sqr_add_c(a,2,c2,c3,c1);
addcc c_2,t_1,c_2
rd %y,t_2 !=
addxcc c_3,t_2,c_3
addx c_1,%g0,c_1
st c_2,rp(4) !r[4]=c2;
umul a_2,a_3,t_1 !=!sqr_add_c2(a,3,2,c3,c1,c2);
addcc c_3,t_1,c_3
rd %y,t_2
addxcc c_1,t_2,c_1
addx %g0,%g0,c_2 !=
addcc c_3,t_1,c_3
addxcc c_1,t_2,c_1
st c_3,rp(5) !r[5]=c3;
addx c_2,%g0,c_2 !=
umul a_3,a_3,t_1 !sqr_add_c(a,3,c1,c2,c3);
addcc c_1,t_1,c_1
rd %y,t_2
addxcc c_2,t_2,c_2 !=
st c_1,rp(6) !r[6]=c1;
st c_2,rp(7) !r[7]=c2;
ret
restore %g0,%g0,%o0
.type bn_sqr_comba4,#function
.size bn_sqr_comba4,(.-bn_sqr_comba4)
.align 32
|
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