repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
alisw/GMP | 6,740 | mpn/m88k/mc88110/sub_n.S | ; mc88110 __gmpn_sub_n -- Subtract two limb vectors of the same length > 0 and
; store difference in a third limb vector.
; Copyright 1995, 1996, 2000 Free Software Foundation, Inc.
; This file is part of the GNU MP Library.
;
; The GNU MP Library is free software; you can redistribute it and/or modify
; it under ... |
alisw/GMP | 8,721 | mpn/cray/cfp/mulwwc90.s | * Helper for mpn_mul_1, mpn_addmul_1, and mpn_submul_1 for Cray PVP.
* Copyright 1996, 2000 Free Software Foundation, Inc.
* This file is generated from mulww.f in this same directory.
* This file is part of the GNU MP Library.
*
* The GNU MP Library is free software; you can redistribute it and/or modify
... |
alisw/GMP | 8,704 | mpn/cray/cfp/mulwwj90.s | * Helper for mpn_mul_1, mpn_addmul_1, and mpn_submul_1 for Cray PVP.
* Copyright 1996, 2000 Free Software Foundation, Inc.
* This file is generated from mulww.f in this same directory.
* This file is part of the GNU MP Library.
*
* The GNU MP Library is free software; you can redistribute it and/or modify
... |
AlkaMotors/AM32-MultiRotor-ESC-firmware | 9,455 | Mcu/f051/Startup/startup_stm32f051k6tx.s | /**
******************************************************************************
* @file startup_stm32f051x8.s
* @author MCD Application Team
* @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain.
* This module performs:
* - Set the initi... |
AlkaMotors/AM32-MultiRotor-ESC-firmware | 10,676 | Mcu/f350/Startup/startup_stm32f302cbtx.s | /**
******************************************************************************
* @file startup_stm32f302xc.s
* @author MCD Application Team
* @brief STM32F302xB/STM32F302xC devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* ... |
AlkaMotors/AM32-MultiRotor-ESC-firmware | 8,881 | Mcu/f031/Startup/startup_stm32f031c6tx.s | /**
******************************************************************************
* @file startup_stm32f031x6.s
* @author MCD Application Team
* @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* ... |
AlkaMotors/AM32-MultiRotor-ESC-firmware | 11,792 | Mcu/l431/Startup/startup_stm32l431kbux.s | /**
******************************************************************************
* @file startup_stm32l431xx.s
* @author MCD Application Team
* @brief STM32L431xx devices vector table for GCC toolchain.
* This module performs:
* - Set the initial SP
* ... |
AlkaMotors/AM32-MultiRotor-ESC-firmware | 9,555 | Mcu/g071/Startup/startup_stm32g071gbux.s | /**
******************************************************************************
* @file startup_stm32g071xx.s
* @author MCD Application Team
* @brief STM32G071xx devices vector table for SW4STM32 toolchain.
* This module performs:
* - Set the initial SP
* ... |
AlkaMotors/f051bldc | 10,606 | Startup/startup_stm32f051k6tx.s | /**
******************************************************************************
* @file startup_stm32f051x8.s
* @author MCD Application Team
* @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain.
* This module performs:
* - Set the initi... |
AlkaMotors/f051bldc | 10,606 | WORKINGDONTTOUCH/startup/startup_stm32f051x8.s | /**
******************************************************************************
* @file startup_stm32f051x8.s
* @author MCD Application Team
* @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain.
* This module performs:
* - Set the initi... |
AlkaMotors/f051bldc | 10,606 | F051Version2Sept2019/startup/startup_stm32f051x8.s | /**
******************************************************************************
* @file startup_stm32f051x8.s
* @author MCD Application Team
* @brief STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for GCC toolchain.
* This module performs:
* - Set the initi... |
AllenDowney/ExercisesInC | 1,268 | examples/lock/lock.s | .file "lock.c"
.text
.globl make_lock
.type make_lock, @function
make_lock:
.LFB2:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movl $4, %edi
call malloc
movq %rax, -8(%rbp)
movq -8(%rbp), %rax
movl $0, (%rax)
movq -8(%rbp), ... |
AllenDowney/ExercisesInC | 1,257 | examples/lock/lock_bts.s | .file "lock.c"
.text
.globl make_lock
.type make_lock, @function
make_lock:
.LFB2:
.cfi_startproc
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movl $4, %edi
call malloc
movq %rax, -8(%rbp)
movq -8(%rbp), %rax
movl $0, (%rax)
movq -8(%rbp), ... |
allexoll/BBB-BareMetal | 1,422 | 03_LED/start.s |
_start:
mrs r0, cpsr
bic r0, r0, #0x1F @ clear mode bits
orr r0, r0, #0x13 @ set SVC mode
orr r0, r0, #0xC0 @ disable FIQ and IRQ
msr cpsr, r0
ldr sp, =0x4030CDFC @6kB public stack TMR 26.1.3.2
bl _main
.loop: b .loop
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r... |
allexoll/BBB-BareMetal | 1,960 | 04_UART/start.s |
.globl _start
_start:
mrs r0, cpsr
bic r0, r0, #0x1F ;@ clear mode bits
orr r0, r0, #0x13 ;@ set SVC mode
orr r0, r0, #0xC0 ;@ disable FIQ and IRQ
msr cpsr, r0
mrc p15,0,r0,c1,c0,2 ;@ read cp access register
orr r0,r0,#0x00F00000 ;@ enable full access to neon/vfp (coproc 10&11)
mcr p15,0,... |
allexoll/BBB-BareMetal | 1,494 | 01_Blinker/start.s | .equ CM_PER_GPIO1_CLKCTRL, 0x44e000AC
.equ GPIO1_OE, 0x4804C134
.equ GPIO1_SETDATAOUT, 0x4804C194
_start:
mrs r0, cpsr
bic r0, r0, #0x1F @ clear mode bits
orr r0, r0, #0x13 @ set SVC mode
orr r0, r0, #0xC0 @ disable FIQ and IRQ
msr cpsr, r0
@sub sp,sp,#0x1800 @6kB public stack
bl _main
.loop: b ... |
allexoll/BBB-BareMetal | 1,421 | 02_GPIO/start.s |
_start:
mrs r0, cpsr
bic r0, r0, #0x1F @ clear mode bits
orr r0, r0, #0x13 @ set SVC mode
orr r0, r0, #0xC0 @ disable FIQ and IRQ
msr cpsr, r0
ldr sp, =0x4030CDFC @6kB public stack TMR 26.1.3.2
bl _main
.loop: b .loop
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r... |
allexoll/BBB-BareMetal | 3,070 | 10_I2C/core/startup_ARMCA8.s |
.equ IRQ_MODE, 0x12
.equ FIQ_MODE, 0x11
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
.code 32
.global Entry
.func
Entry:
__isr_vectors:
ldr pc,[pc,#24]
ldr pc,[pc,#24]
ldr pc,[pc,#24]
ldr pc,[pc,#24]
ldr pc,[pc,#24]
... |
allexoll/BBB-BareMetal | 6,348 | 10_I2C/core/core_handlers.s | /**
* @file core_handler.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief this files contains the EXC handlers.
**/
.equ NO_IRQ, 0x80 // mask to disable IRQ
.equ NO_FIQ, 0x40 // mask to disable FIQ
.equ NO_INT, (NO_IRQ|NO_FIQ) // mask to disable IRQ & FIQ
.equ IRQ... |
allexoll/BBB-BareMetal | 1,775 | 10_I2C/core/llma.s | /**
* @file llma.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief contains Low Level Memory Access functions
**/
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl PUT16
PUT16:
strh r1,[r0]
bx lr
.globl GET16
GET16:
ldrh r0,[r0]
bx lr
.globl PUT8
PUT8:
strb... |
allexoll/BBB-BareMetal | 3,534 | 05_low_level_init/core/startup_ARMCA8.s |
.equ IRQ_MODE, 0x12
.equ FIQ_MODE, 0x11
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
.code 32
.global Entry
.func
Entry:
.if userland == 1
.section .isr_vector
.align 4
.global __isr_vectors
__isr_vectors:
ldr pc,[pc,#24]
b .
b ... |
allexoll/BBB-BareMetal | 3,087 | 05_low_level_init/core/core_handlers.s | /**
* @file core_handler.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief this files contains the EXC handlers.
**/
.equ NO_IRQ, 0x80 // mask to disable IRQ
.equ NO_FIQ, 0x40 // mask to disable FIQ
.equ NO_INT, (NO_IRQ|NO_FIQ) // mask to disable IRQ & FIQ
.equ IRQ... |
allexoll/BBB-BareMetal | 1,709 | 05_low_level_init/core/llma.s | /**
* @file llma.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief contains Low Level Memory Access functions
**/
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl PUT16
PUT16:
strh r1,[r0]
bx lr
.globl GET16
GET16:
ldrh r0,[r0]
bx lr
.globl PUT8
PUT8:
strb... |
allexoll/BBB-BareMetal | 10,183 | 06_stdlib/core/__aeabi.s | /*
* armDivision.s: Optimized ARM division routines
*
* End of the file for licence details.
*
* You need to provide the method void __div0(void) in your code
* to handle divide by zero.
*
*/
/**
* @file __aeabi.s
* @author Alexis Marquet
* @date 28 Apr 2015
* @brief this file contains implementations fo... |
allexoll/BBB-BareMetal | 3,534 | 06_stdlib/core/startup_ARMCA8.s |
.equ IRQ_MODE, 0x12
.equ FIQ_MODE, 0x11
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
.code 32
.global Entry
.func
Entry:
.if userland == 1
.section .isr_vector
.align 4
.global __isr_vectors
__isr_vectors:
ldr pc,[pc,#24]
b .
b ... |
allexoll/BBB-BareMetal | 3,087 | 06_stdlib/core/core_handlers.s | /**
* @file core_handler.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief this files contains the EXC handlers.
**/
.equ NO_IRQ, 0x80 // mask to disable IRQ
.equ NO_FIQ, 0x40 // mask to disable FIQ
.equ NO_INT, (NO_IRQ|NO_FIQ) // mask to disable IRQ & FIQ
.equ IRQ... |
allexoll/BBB-BareMetal | 1,709 | 06_stdlib/core/llma.s | /**
* @file llma.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief contains Low Level Memory Access functions
**/
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl PUT16
PUT16:
strh r1,[r0]
bx lr
.globl GET16
GET16:
ldrh r0,[r0]
bx lr
.globl PUT8
PUT8:
strb... |
allexoll/BBB-BareMetal | 10,183 | 07_Bootloader/core/__aeabi.s | /*
* armDivision.s: Optimized ARM division routines
*
* End of the file for licence details.
*
* You need to provide the method void __div0(void) in your code
* to handle divide by zero.
*
*/
/**
* @file __aeabi.s
* @author Alexis Marquet
* @date 28 Apr 2015
* @brief this file contains implementations fo... |
allexoll/BBB-BareMetal | 3,534 | 07_Bootloader/core/startup_ARMCA8.s |
.equ IRQ_MODE, 0x12
.equ FIQ_MODE, 0x11
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
.code 32
.global Entry
.func
Entry:
.if userland == 1
.section .isr_vector
.align 4
.global __isr_vectors
__isr_vectors:
ldr pc,[pc,#24]
b .
b ... |
allexoll/BBB-BareMetal | 3,087 | 07_Bootloader/core/core_handlers.s | /**
* @file core_handler.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief this files contains the EXC handlers.
**/
.equ NO_IRQ, 0x80 // mask to disable IRQ
.equ NO_FIQ, 0x40 // mask to disable FIQ
.equ NO_INT, (NO_IRQ|NO_FIQ) // mask to disable IRQ & FIQ
.equ IRQ... |
allexoll/BBB-BareMetal | 1,775 | 07_Bootloader/core/llma.s | /**
* @file llma.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief contains Low Level Memory Access functions
**/
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl PUT16
PUT16:
strh r1,[r0]
bx lr
.globl GET16
GET16:
ldrh r0,[r0]
bx lr
.globl PUT8
PUT8:
strb... |
allexoll/BBB-BareMetal | 10,183 | 09_USB_Bootloader/core/__aeabi.s | /*
* armDivision.s: Optimized ARM division routines
*
* End of the file for licence details.
*
* You need to provide the method void __div0(void) in your code
* to handle divide by zero.
*
*/
/**
* @file __aeabi.s
* @author Alexis Marquet
* @date 28 Apr 2015
* @brief this file contains implementations fo... |
allexoll/BBB-BareMetal | 3,546 | 09_USB_Bootloader/core/startup_ARMCA8.s |
.equ IRQ_MODE, 0x12
.equ FIQ_MODE, 0x11
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
.code 32
.global Entry
.func
Entry:
.if userland == 1
.section .isr_vector
.align 4
.global __isr_vectors
__isr_vectors:
ldr pc,[pc,#24]
b .
b ... |
allexoll/BBB-BareMetal | 6,348 | 09_USB_Bootloader/core/core_handlers.s | /**
* @file core_handler.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief this files contains the EXC handlers.
**/
.equ NO_IRQ, 0x80 // mask to disable IRQ
.equ NO_FIQ, 0x40 // mask to disable FIQ
.equ NO_INT, (NO_IRQ|NO_FIQ) // mask to disable IRQ & FIQ
.equ IRQ... |
allexoll/BBB-BareMetal | 1,831 | 09_USB_Bootloader/core/llma.s | /**
* @file llma.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief contains Low Level Memory Access functions
**/
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl PUT16
PUT16:
strh r1,[r0]
bx lr
.globl GET16
GET16:
ldrh r0,[r0]
bx lr
.globl PUT8
PUT8:
strb... |
allexoll/BBB-BareMetal | 3,070 | 08_test_CXX/core/startup_ARMCA8.s |
.equ IRQ_MODE, 0x12
.equ FIQ_MODE, 0x11
.equ SVC_MODE, 0x13
.equ ABT_MODE, 0x17
.equ UND_MODE, 0x1B
.equ SYS_MODE, 0x1F
.equ I_BIT, 0x80
.equ F_BIT, 0x40
.text
.code 32
.global Entry
.func
Entry:
__isr_vectors:
ldr pc,[pc,#24]
ldr pc,[pc,#24]
ldr pc,[pc,#24]
ldr pc,[pc,#24]
ldr pc,[pc,#24]
... |
allexoll/BBB-BareMetal | 3,087 | 08_test_CXX/core/core_handlers.s | /**
* @file core_handler.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief this files contains the EXC handlers.
**/
.equ NO_IRQ, 0x80 // mask to disable IRQ
.equ NO_FIQ, 0x40 // mask to disable FIQ
.equ NO_INT, (NO_IRQ|NO_FIQ) // mask to disable IRQ & FIQ
.equ IRQ... |
allexoll/BBB-BareMetal | 1,775 | 08_test_CXX/core/llma.s | /**
* @file llma.s
* @author Alexis Marquet
* @date 27 Feb 2015
* @brief contains Low Level Memory Access functions
**/
.globl PUT32
PUT32:
str r1,[r0]
bx lr
.globl GET32
GET32:
ldr r0,[r0]
bx lr
.globl PUT16
PUT16:
strh r1,[r0]
bx lr
.globl GET16
GET16:
ldrh r0,[r0]
bx lr
.globl PUT8
PUT8:
strb... |
AllenDang/cimgui-go | 12,846 | thirdparty/SDL/src/video/arm/pixman-arm-neon-asm.S | /*
* Copyright © 2009 Nokia Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, pub... |
AllenDang/cimgui-go | 19,392 | thirdparty/SDL/src/video/arm/pixman-arm-simd-asm.S | /*
* Copyright (c) 2016 RISC OS Open Ltd
*
* This software is provided 'as-is', without any express or implied
* warranty. In no event will the authors be held liable for any damages
* arising from the use of this software.
*
* Permission is granted to anyone to use this software for any purpose,
* including c... |
Alliance-Algorithm/rmcs_slave | 22,903 | bsp/HAL/startup_stm32f407xx.s | /**
******************************************************************************
* @file startup_stm32f407xx.s
* @author MCD Application Team
* @brief STM32F407xx Devices vector table for GCC based toolchains.
* This module performs:
* - Set the initial SP
* ... |
Alliance-Algorithm/rmcs_slave | 11,110 | bsp/SEGGER/RTT/SEGGER_RTT_ASM_ARMv7M.S | /*********************************************************************
* (c) SEGGER Microcontroller GmbH *
* The Embedded Experts *
* www.segger.com *
************************************... |
AllTradesZach/PY32-Examples | 10,554 | PY32_Test_LED_Blink/RTE/Device/PY32F003x6/startup_py32f003x6.s | ;******************************************************************************
;* @file : startup_py32f003xx.s
;* @brief : PY32F003xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* ... |
AllTradesZach/PY32-Examples | 10,554 | PY32_Test_ADC_UART/RTE/Device/PY32F003x6/startup_py32f003x6.s | ;******************************************************************************
;* @file : startup_py32f003xx.s
;* @brief : PY32F003xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* ... |
allvm/allvm-tools | 25,797 | libs/none/unwind/UnwindRegistersRestore.S | //===-------------------- UnwindRegistersRestore.S ------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===---------------------------... |
allvm/allvm-tools | 24,206 | libs/none/unwind/UnwindRegistersSave.S | //===------------------------ UnwindRegistersSave.S -----------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===---------------------------... |
allvm/allvm-tools | 1,077 | third_party/musl/src/thread/sh/atomics.s | /* Contract for all versions is same as cas.l r2,r3,@r0
* pr and r1 are also clobbered (by jsr & r1 as temp).
* r0,r2,r4-r15 must be preserved.
* r3 contains result (==r2 iff cas succeeded). */
.align 2
.global __sh_cas_gusa
.hidden __sh_cas_gusa
__sh_cas_gusa:
mov.l r5,@-r15
mov.l r4,@-r15
mov r0,r4
mova 1f,r... |
allvm/allvm-tools | 1,717 | third_party/musl/src/thread/arm/atomics.s | .syntax unified
.text
.global __a_barrier_dummy
.hidden __a_barrier_dummy
.type __a_barrier_dummy,%function
__a_barrier_dummy:
bx lr
.global __a_barrier_oldkuser
.hidden __a_barrier_oldkuser
.type __a_barrier_oldkuser,%function
__a_barrier_oldkuser:
push {r0,r1,r2,r3,ip,lr}
mov r1,r0
mov r2,sp
ldr ip,=0xffff0fc0... |
allvm/allvm-tools | 1,218 | third_party/musl/src/thread/powerpc/clone.s | .text
.global __clone
.hidden __clone
.type __clone, %function
__clone:
# int clone(fn, stack, flags, arg, ptid, tls, ctid)
# a b c d e f g
# 3 4 5 6 7 8 9
# pseudo C code:
# tid = syscall(SYS_clone,c,b,e,f,g);
# if (!tid) syscall(SYS_exit, a(d));
# return... |
allvm/allvm-tools | 1,866 | third_party/musl/src/thread/powerpc/syscall_cp.s | .global __cp_begin
.hidden __cp_begin
.global __cp_end
.hidden __cp_end
.global __cp_cancel
.hidden __cp_cancel
.hidden __cancel
.global __syscall_cp_asm
.hidden __syscall_cp_asm
#r0: volatile. may be modified during linkage.
#r1: stack frame: 16 byte alignment.
#r2: tls/thread pointer on pp32
#r3,r4: return values, f... |
allvm/allvm-tools | 2,032 | third_party/musl/src/setjmp/powerpc64/setjmp.s | .global __setjmp
.global _setjmp
.global setjmp
.type __setjmp,@function
.type _setjmp,@function
.type setjmp,@function
__setjmp:
_setjmp:
setjmp:
ld 5, 24(1) # load from the TOC slot in the caller's stack frame
b __setjmp_toc
.localentry __setjmp,.-__setjmp
.localentry _setjmp,.-_setjmp
.localentry... |
allvm/allvm-tools | 1,670 | third_party/musl/src/setjmp/powerpc64/longjmp.s | .global _longjmp
.global longjmp
.type _longjmp,@function
.type longjmp,@function
_longjmp:
longjmp:
# 0) move old return address into the link register
ld 0, 0*8(3)
mtlr 0
# 1) restore cr
ld 0, 1*8(3)
mtcr 0
# 2) restore SP
ld 1, 2*8(3)
# 3) restore TOC into both r2 and the caller's stack.
#... |
allvm/allvm-tools | 1,053 | third_party/musl/src/setjmp/powerpc/setjmp.S | .global ___setjmp
.hidden ___setjmp
.global __setjmp
.global _setjmp
.global setjmp
.type __setjmp,@function
.type _setjmp,@function
.type setjmp,@function
___setjmp:
__setjmp:
_setjmp:
setjmp:
/* 0) store IP int 0, then into the jmpbuf pointed to by r3 (first arg) */
mflr 0
stw 0, 0(3)
/* 1) store re... |
allvm/allvm-tools | 1,195 | third_party/musl/src/setjmp/powerpc/longjmp.S | .global _longjmp
.global longjmp
.type _longjmp,@function
.type longjmp,@function
_longjmp:
longjmp:
/*
* void longjmp(jmp_buf env, int val);
* put val into return register and restore the env saved in setjmp
* if val(r4) is 0, put 1 there.
*/
/* 0) move old return address into r0 */
lwz 0, 0(3)
/* ... |
allvm/allvm-tools | 1,054 | third_party/musl/src/ldso/arm/tlsdesc.S | .syntax unified
.text
.global __tlsdesc_static
.hidden __tlsdesc_static
.type __tlsdesc_static,%function
__tlsdesc_static:
ldr r0,[r0]
bx lr
.global __tlsdesc_dynamic
.hidden __tlsdesc_dynamic
.type __tlsdesc_dynamic,%function
__tlsdesc_dynamic:
push {r2,r3,ip,lr}
ldr r1,[r0]
ldr r2,[r1,#4] // r2 = offset
ldr ... |
allvm/allvm-tools | 1,166 | third_party/musl/src/string/i386/memset.s | .global memset
.type memset,@function
memset:
mov 12(%esp),%ecx
cmp $62,%ecx
ja 2f
mov 8(%esp),%dl
mov 4(%esp),%eax
test %ecx,%ecx
jz 1f
mov %dl,%dh
mov %dl,(%eax)
mov %dl,-1(%eax,%ecx)
cmp $2,%ecx
jbe 1f
mov %dx,1(%eax)
mov %dx,(-1-2)(%eax,%ecx)
cmp $6,%ecx
jbe 1f
shl $16,%edx
mov 8(%esp),%dl
m... |
allvm/allvm-tools | 4,437 | third_party/musl/src/string/aarch64/memcpy.S | /*
* memcpy - copy memory area
*
* Copyright (c) 2012-2020, Arm Limited.
* SPDX-License-Identifier: MIT
*/
/* Assumptions:
*
* ARMv8-a, AArch64, unaligned accesses.
*
*/
#define dstin x0
#define src x1
#define count x2
#define dst x3
#define srcend x4
#define dstend x5
#define A_l x6
#defin... |
allvm/allvm-tools | 2,386 | third_party/musl/src/string/aarch64/memset.S | /*
* memset - fill memory with a constant byte
*
* Copyright (c) 2012-2020, Arm Limited.
* SPDX-License-Identifier: MIT
*/
/* Assumptions:
*
* ARMv8-a, AArch64, Advanced SIMD, unaligned accesses.
*
*/
#define dstin x0
#define val x1
#define valw w1
#define count x2
#define dst x3
#define dsten... |
allvm/allvm-tools | 13,178 | third_party/musl/src/string/arm/memcpy.S | /*
* Copyright (C) 2008 The Android Open Source Project
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, t... |
allvm/allvm-tools | 1,128 | third_party/musl/src/string/x86_64/memset.s | .global memset
.type memset,@function
memset:
movzbq %sil,%rax
mov $0x101010101010101,%r8
imul %r8,%rax
cmp $126,%rdx
ja 2f
test %edx,%edx
jz 1f
mov %sil,(%rdi)
mov %sil,-1(%rdi,%rdx)
cmp $2,%edx
jbe 1f
mov %ax,1(%rdi)
mov %ax,(-1-2)(%rdi,%rdx)
cmp $6,%edx
jbe 1f
mov %eax,(1+2)(%rdi)
mov %eax,(-1-... |
allvm/allvm-tools | 1,435 | third_party/musl/src/math/i386/exp_ld.s | .global expm1l
.type expm1l,@function
expm1l:
fldt 4(%esp)
fldl2e
fmulp
mov $0xc2820000,%eax
push %eax
flds (%esp)
pop %eax
fucomp %st(1)
fnstsw %ax
sahf
fld1
jb 1f
# x*log2e < -65, return -1 without underflow
fstp %st(1)
fchs
ret
1: fld %st(1)
fabs
fucom %st(1)
fnstsw %ax
fstp %st(0)
fstp %st(0)
... |
allvm/allvm-tools | 1,934 | third_party/musl/src/math/i386/expl.s | # exp(x) = 2^hi + 2^hi (2^lo - 1)
# where hi+lo = log2e*x with 128bit precision
# exact log2e*x calculation depends on nearest rounding mode
# using the exact multiplication method of Dekker and Veltkamp
.global expl
.type expl,@function
expl:
fldt 4(%esp)
# interesting case: 0x1p-32 <= |x| < 16384
# check if (e... |
allvm/allvm-tools | 1,355 | third_party/musl/src/math/x32/exp2l.s | .global expm1l
.type expm1l,@function
expm1l:
fldt 8(%esp)
fldl2e
fmulp
movl $0xc2820000,-4(%esp)
flds -4(%esp)
fucomip %st(1),%st
fld1
jb 1f
# x*log2e <= -65, return -1 without underflow
fstp %st(1)
fchs
ret
1: fld %st(1)
fabs
fucomip %st(1),%st
fstp %st(0)
ja 1f
f2xm1
ret
1: push %rax
call 1f
pop... |
allvm/allvm-tools | 1,953 | third_party/musl/src/math/x32/expl.s | # exp(x) = 2^hi + 2^hi (2^lo - 1)
# where hi+lo = log2e*x with 128bit precision
# exact log2e*x calculation depends on nearest rounding mode
# using the exact multiplication method of Dekker and Veltkamp
.global expl
.type expl,@function
expl:
fldt 8(%esp)
# interesting case: 0x1p-32 <= |x| < 16384
# check if (e... |
allvm/allvm-tools | 1,355 | third_party/musl/src/math/x86_64/exp2l.s | .global expm1l
.type expm1l,@function
expm1l:
fldt 8(%rsp)
fldl2e
fmulp
movl $0xc2820000,-4(%rsp)
flds -4(%rsp)
fucomip %st(1),%st
fld1
jb 1f
# x*log2e <= -65, return -1 without underflow
fstp %st(1)
fchs
ret
1: fld %st(1)
fabs
fucomip %st(1),%st
fstp %st(0)
ja 1f
f2xm1
ret
1: push %rax
call 1f
pop... |
allvm/allvm-tools | 1,956 | third_party/musl/src/math/x86_64/expl.s | # exp(x) = 2^hi + 2^hi (2^lo - 1)
# where hi+lo = log2e*x with 128bit precision
# exact log2e*x calculation depends on nearest rounding mode
# using the exact multiplication method of Dekker and Veltkamp
.global expl
.type expl,@function
expl:
fldt 8(%rsp)
# interesting case: 0x1p-32 <= |x| < 16384
# check if (e... |
allvm/allvm-tools | 2,715 | third_party/musl/src/fenv/i386/fenv.s | .hidden __hwcap
.global feclearexcept
.type feclearexcept,@function
feclearexcept:
mov 4(%esp),%ecx
and $0x3f,%ecx
fnstsw %ax
# consider sse fenv as well if the cpu has XMM capability
call 1f
1: addl $__hwcap-1b,(%esp)
pop %edx
testl $0x02000000,(%edx)
jz 2f
# maintain exceptions in the sse mxcsr, clear x8... |
allvm/allvm-tools | 1,444 | third_party/musl/src/fenv/x32/fenv.s | .global feclearexcept
.type feclearexcept,@function
feclearexcept:
# maintain exceptions in the sse mxcsr, clear x87 exceptions
mov %edi,%ecx
and $0x3f,%ecx
fnstsw %ax
test %eax,%ecx
jz 1f
fnclex
1: stmxcsr -8(%esp)
and $0x3f,%eax
or %eax,-8(%esp)
test %ecx,-8(%esp)
jz 1f
not %ecx
and %ecx,-8(%esp)
ldmxc... |
allvm/allvm-tools | 1,233 | third_party/musl/src/fenv/sh/fenv.S | #if __SH_FPU_ANY__ || __SH4__
.global fegetround
.type fegetround, @function
fegetround:
sts fpscr, r0
rts
and #3, r0
.global __fesetround
.hidden __fesetround
.type __fesetround, @function
__fesetround:
sts fpscr, r0
mov #-4, r1
and r1, r0
or r4, r0
lds r0, fpscr
rts
mov #0, r0
.global fetestexcept... |
allvm/allvm-tools | 1,444 | third_party/musl/src/fenv/x86_64/fenv.s | .global feclearexcept
.type feclearexcept,@function
feclearexcept:
# maintain exceptions in the sse mxcsr, clear x87 exceptions
mov %edi,%ecx
and $0x3f,%ecx
fnstsw %ax
test %eax,%ecx
jz 1f
fnclex
1: stmxcsr -8(%rsp)
and $0x3f,%eax
or %eax,-8(%rsp)
test %ecx,-8(%rsp)
jz 1f
not %ecx
and %ecx,-8(%rsp)
ldmxc... |
allvm/allvm-tools | 1,150 | third_party/musl/src/fenv/mips/fenv.S | #ifndef __mips_soft_float
.set noreorder
.global feclearexcept
.type feclearexcept,@function
feclearexcept:
and $4, $4, 0x7c
cfc1 $5, $31
or $5, $5, $4
xor $5, $5, $4
ctc1 $5, $31
jr $ra
li $2, 0
.global feraiseexcept
.type feraiseexcept,@function
feraiseexcept:
and $4, $4,... |
allvm/allvm-tools | 1,902 | third_party/musl/src/fenv/powerpc/fenv.S | #ifndef _SOFT_FLOAT
.global feclearexcept
.type feclearexcept,@function
feclearexcept:
andis. 3,3,0x3e00
/* if (r3 & FE_INVALID) r3 |= all_invalid_flags */
andis. 0,3,0x2000
stwu 1,-16(1)
beq- 0,1f
oris 3,3,0x01f8
ori 3,3,0x0700
1:
/*
* note: fpscr contains various fpu status and control
* flags and we don... |
allyourcodebase/openssl | 8,177 | crypto/x86_64cpuid.s |
.hidden OPENSSL_cpuid_setup
.section .init
call OPENSSL_cpuid_setup
.hidden OPENSSL_ia32cap_P
.comm OPENSSL_ia32cap_P,16,4
.text
.globl OPENSSL_atomic_add
.type OPENSSL_atomic_add,@function
.align 16
OPENSSL_atomic_add:
.cfi_startproc
.byte 243,15,30,250
movl (%rdi),%eax
.Lspin: leaq (%rsi,%rax,1),%r8
.byte 0xf... |
allyourcodebase/openssl | 39,815 | crypto/camellia/cmll-x86_64.s | .text
.globl Camellia_EncryptBlock
.type Camellia_EncryptBlock,@function
.align 16
Camellia_EncryptBlock:
.cfi_startproc
movl $128,%eax
subl %edi,%eax
movl $3,%edi
adcl $0,%edi
jmp .Lenc_rounds
.cfi_endproc
.size Camellia_EncryptBlock,.-Camellia_EncryptBlock
.globl Camellia_EncryptBlock_Rounds
.type Camellia... |
allyourcodebase/openssl | 96,934 | crypto/sha/sha512-x86_64.s | .text
.globl sha512_block_data_order
.type sha512_block_data_order,@function
.align 16
sha512_block_data_order:
.cfi_startproc
leaq OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
testl $2048,%r10d
jnz .Lxop_shortcut
andl $296,%r11d
cmpl $296,%r11d
je .Lavx2_shortcut
a... |
allyourcodebase/openssl | 102,128 | crypto/sha/sha1-x86_64.s | .text
.globl sha1_block_data_order
.type sha1_block_data_order,@function
.align 16
sha1_block_data_order:
.cfi_startproc
movl OPENSSL_ia32cap_P+0(%rip),%r9d
movl OPENSSL_ia32cap_P+4(%rip),%r8d
movl OPENSSL_ia32cap_P+8(%rip),%r10d
testl $512,%r8d
jz .Lialu
testl $536870912,%r10d
jnz _shaext_shortcut
andl $29... |
allyourcodebase/openssl | 156,450 | crypto/sha/sha256-mb-x86_64.s | .text
.globl sha256_multi_block
.type sha256_multi_block,@function
.align 32
sha256_multi_block:
.cfi_startproc
movq OPENSSL_ia32cap_P+4(%rip),%rcx
btq $61,%rcx
jc _shaext_shortcut
testl $268435456,%ecx
jnz _avx_shortcut
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
.cfi_offset %rbx,-16
pushq %rbp
.... |
allyourcodebase/openssl | 97,908 | crypto/sha/sha256-x86_64.s | .text
.globl sha256_block_data_order
.type sha256_block_data_order,@function
.align 16
sha256_block_data_order:
.cfi_startproc
leaq OPENSSL_ia32cap_P(%rip),%r11
movl 0(%r11),%r9d
movl 4(%r11),%r10d
movl 8(%r11),%r11d
testl $536870912,%r11d
jnz _shaext_shortcut
andl $296,%r11d
cmpl $296,%r11d
je .Lavx2_shor... |
allyourcodebase/openssl | 8,733 | crypto/sha/keccak1600-x86_64.s | .text
.type __KeccakF1600,@function
.align 32
__KeccakF1600:
.cfi_startproc
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.align 32
.Loop:
movq -100(%rdi),%r8
movq -52(%rdi),%r9
movq -4(%rdi),%r10
movq 44(%rdi),%r11
xorq -84(%rdi),%rcx
xorq -76... |
allyourcodebase/openssl | 150,107 | crypto/sha/sha1-mb-x86_64.s | .text
.globl sha1_multi_block
.type sha1_multi_block,@function
.align 32
sha1_multi_block:
.cfi_startproc
movq OPENSSL_ia32cap_P+4(%rip),%rcx
btq $61,%rcx
jc _shaext_shortcut
testl $268435456,%ecx
jnz _avx_shortcut
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
.cfi_offset %rbx,-16
pushq %rbp
.cfi_of... |
allyourcodebase/openssl | 23,609 | crypto/rc4/rc4-md5-x86_64.s | .text
.align 16
.globl rc4_md5_enc
.type rc4_md5_enc,@function
rc4_md5_enc:
.cfi_startproc
cmpq $0,%r9
je .Labort
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa... |
allyourcodebase/openssl | 11,897 | crypto/rc4/rc4-x86_64.s | .text
.globl RC4
.type RC4,@function
.align 16
RC4:
.cfi_startproc
.byte 243,15,30,250
orq %rsi,%rsi
jne .Lentry
.byte 0xf3,0xc3
.Lentry:
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-24
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offset %r13,-32
.... |
allyourcodebase/openssl | 12,904 | crypto/md5/md5-x86_64.s | .text
.align 16
.globl ossl_md5_block_asm_data_order
.type ossl_md5_block_asm_data_order,@function
ossl_md5_block_asm_data_order:
.cfi_startproc
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-16
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-3... |
allyourcodebase/openssl | 74,405 | crypto/chacha/chacha-x86_64.s | .text
.align 64
.Lzero:
.long 0,0,0,0
.Lone:
.long 1,0,0,0
.Linc:
.long 0,1,2,3
.Lfour:
.long 4,4,4,4
.Lincy:
.long 0,2,4,6,1,3,5,7
.Leight:
.long 8,8,8,8,8,8,8,8
.Lrot16:
.byte 0x2,0x3,0x0,0x1, 0x6,0x7,0x4,0x5, 0xa,0xb,0x8,0x9, 0xe,0xf,0xc,0xd
.Lrot24:
.byte 0x3,0x0,0x1,0x2, 0x7,0x4,0x5,0x6, 0xb,0x8,0x9,0xa, 0xf,0... |
allyourcodebase/openssl | 38,055 | crypto/modes/ghash-x86_64.s | .text
.globl gcm_gmult_4bit
.type gcm_gmult_4bit,@function
.align 16
gcm_gmult_4bit:
.cfi_startproc
.byte 243,15,30,250
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjus... |
allyourcodebase/openssl | 3,413,131 | crypto/modes/aes-gcm-avx512.s |
.globl ossl_vaes_vpclmulqdq_capable
.type ossl_vaes_vpclmulqdq_capable,@function
.align 32
ossl_vaes_vpclmulqdq_capable:
movq OPENSSL_ia32cap_P+8(%rip),%rcx
movq $6600291188736,%rdx
xorl %eax,%eax
andq %rdx,%rcx
cmpq %rdx,%rcx
cmoveq %rcx,%rax
.byte 0xf3,0xc3
.size ossl_vaes_vpclmulqdq_capable, .-ossl_vaes_vpc... |
allyourcodebase/openssl | 19,157 | crypto/modes/aesni-gcm-x86_64.s | .text
.type _aesni_ctr32_ghash_6x,@function
.align 32
_aesni_ctr32_ghash_6x:
.cfi_startproc
vmovdqu 32(%r11),%xmm2
subq $6,%rdx
vpxor %xmm4,%xmm4,%xmm4
vmovdqu 0-128(%rcx),%xmm15
vpaddb %xmm2,%xmm1,%xmm10
vpaddb %xmm2,%xmm10,%xmm11
vpaddb %xmm2,%xmm11,%xmm12
vpaddb %xmm2,%xmm12,%xmm13
vpaddb %xmm2,%xmm13,%x... |
allyourcodebase/openssl | 69,339 | crypto/poly1305/poly1305-x86_64.s | .text
.globl poly1305_init
.hidden poly1305_init
.globl poly1305_blocks
.hidden poly1305_blocks
.globl poly1305_emit
.hidden poly1305_emit
.type poly1305_init,@function
.align 32
poly1305_init:
.cfi_startproc
xorq %rax,%rax
movq %rax,0(%rdi)
movq %rax,8(%rdi)
movq %rax,16(%rdi)
cmpq $0,%rsi
je .Lno_key
l... |
allyourcodebase/openssl | 13,665 | crypto/ec/x25519-x86_64.s | .text
.globl x25519_fe51_mul
.type x25519_fe51_mul,@function
.align 32
x25519_fe51_mul:
.cfi_startproc
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-16
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cf... |
allyourcodebase/openssl | 515,779 | crypto/ec/ecp_nistz256-x86_64.s | .text
.globl ecp_nistz256_precomputed
.type ecp_nistz256_precomputed,@object
.align 4096
ecp_nistz256_precomputed:
.long 0x18a9143c,0x79e730d4,0x5fedb601,0x75ba95fc,0x77622510,0x79fb732b,0xa53755c6,0x18905f76,0xce95560a,0xddf25357,0xba19e45c,0x8b4ab8e4,0xdd21f325,0xd2e88688,0x25885d85,0x8571ff18
.long 0x10ddd64d,0x850... |
allyourcodebase/openssl | 20,601 | crypto/bn/x86_64-mont.s | .text
.globl bn_mul_mont
.type bn_mul_mont,@function
.align 16
bn_mul_mont:
.cfi_startproc
movl %r9d,%r9d
movq %rsp,%rax
.cfi_def_cfa_register %rax
testl $3,%r9d
jnz .Lmul_enter
cmpl $8,%r9d
jb .Lmul_enter
movl OPENSSL_ia32cap_P+8(%rip),%r11d
cmpq %rsi,%rdx
jne .Lmul4x_enter
testl $7,%r9d
jz .Lsqr8x_ent... |
allyourcodebase/openssl | 32,464 | crypto/bn/rsaz-x86_64.s | .text
.globl rsaz_512_sqr
.type rsaz_512_sqr,@function
.align 32
rsaz_512_sqr:
.cfi_startproc
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8
.cfi_offset %r12,-32
pushq %r13
.cfi_adjust_cfa_offset 8
.cfi_offse... |
allyourcodebase/openssl | 29,904 | crypto/bn/rsaz-3k-avx512.s | .text
.globl ossl_rsaz_amm52x30_x1_ifma256
.type ossl_rsaz_amm52x30_x1_ifma256,@function
.align 32
ossl_rsaz_amm52x30_x1_ifma256:
.cfi_startproc
.byte 243,15,30,250
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8... |
allyourcodebase/openssl | 19,134 | crypto/bn/rsaz-2k-avx512.s |
.globl ossl_rsaz_avx512ifma_eligible
.type ossl_rsaz_avx512ifma_eligible,@function
.align 32
ossl_rsaz_avx512ifma_eligible:
movl OPENSSL_ia32cap_P+8(%rip),%ecx
xorl %eax,%eax
andl $2149777408,%ecx
cmpl $2149777408,%ecx
cmovel %ecx,%eax
.byte 0xf3,0xc3
.size ossl_rsaz_avx512ifma_eligible, .-ossl_rsaz_avx512ifma_e... |
allyourcodebase/openssl | 58,673 | crypto/bn/x86_64-mont5.s | .text
.globl bn_mul_mont_gather5
.type bn_mul_mont_gather5,@function
.align 64
bn_mul_mont_gather5:
.cfi_startproc
movl %r9d,%r9d
movq %rsp,%rax
.cfi_def_cfa_register %rax
testl $7,%r9d
jnz .Lmul_enter
movl OPENSSL_ia32cap_P+8(%rip),%r11d
jmp .Lmul4x_enter
.align 16
.Lmul_enter:
movd 8(%rsp),%xmm5
pushq %... |
allyourcodebase/openssl | 31,714 | crypto/bn/rsaz-4k-avx512.s | .text
.globl ossl_rsaz_amm52x40_x1_ifma256
.type ossl_rsaz_amm52x40_x1_ifma256,@function
.align 32
ossl_rsaz_amm52x40_x1_ifma256:
.cfi_startproc
.byte 243,15,30,250
pushq %rbx
.cfi_adjust_cfa_offset 8
.cfi_offset %rbx,-16
pushq %rbp
.cfi_adjust_cfa_offset 8
.cfi_offset %rbp,-24
pushq %r12
.cfi_adjust_cfa_offset 8... |
allyourcodebase/openssl | 39,559 | crypto/bn/rsaz-avx2.s | .text
.globl rsaz_1024_sqr_avx2
.type rsaz_1024_sqr_avx2,@function
.align 64
rsaz_1024_sqr_avx2:
.cfi_startproc
leaq (%rsp),%rax
.cfi_def_cfa_register %rax
pushq %rbx
.cfi_offset %rbx,-16
pushq %rbp
.cfi_offset %rbp,-24
pushq %r12
.cfi_offset %r12,-32
pushq %r13
.cfi_offset %r13,-40
pushq %r14
.cfi_offset %r14... |
allyourcodebase/openssl | 5,864 | crypto/bn/x86_64-gf2m.s | .text
.type _mul_1x1,@function
.align 16
_mul_1x1:
.cfi_startproc
subq $128+8,%rsp
.cfi_adjust_cfa_offset 128+8
movq $-1,%r9
leaq (%rax,%rax,1),%rsi
shrq $3,%r9
leaq (,%rax,4),%rdi
andq %rax,%r9
leaq (,%rax,8),%r12
sarq $63,%rax
leaq (%r9,%r9,1),%r10
sarq $63,%rsi
leaq (,%r9,4),%r11
andq %rbp,%rax
sarq ... |
allyourcodebase/openssl | 29,686 | crypto/whrlpool/wp-x86_64.s | .text
.globl whirlpool_block
.type whirlpool_block,@function
.align 16
whirlpool_block:
.cfi_startproc
movq %rsp,%rax
.cfi_def_cfa_register %rax
pushq %rbx
.cfi_offset %rbx,-16
pushq %rbp
.cfi_offset %rbp,-24
pushq %r12
.cfi_offset %r12,-32
pushq %r13
.cfi_offset %r13,-40
pushq %r14
.cfi_offset %r14,-48
pushq... |
allyourcodebase/openssl | 58,582 | crypto/aes/aesni-sha1-x86_64.s | .text
.globl aesni_cbc_sha1_enc
.type aesni_cbc_sha1_enc,@function
.align 32
aesni_cbc_sha1_enc:
.cfi_startproc
movl OPENSSL_ia32cap_P+0(%rip),%r10d
movq OPENSSL_ia32cap_P+4(%rip),%r11
btq $61,%r11
jc aesni_cbc_sha1_enc_shaext
andl $268435456,%r11d
andl $1073741824,%r10d
orl %r11d,%r10d
cmpl $1342177280,%r... |
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