repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
0intro/9legacy | 3,515 | sys/src/libc/spim64/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVV R1, s1+0(FP)
MOVW n+16(FP), R3 /* R3 is count */
MOVV R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVV s2+8(FP), R5 /* R5 is from-pointer */
ADDVU R3,R5, R7 /* R7 is end from-point... |
0intro/9legacy | 1,151 | sys/src/libc/spim64/strcpy.s | TEXT strcpy(SB), $0
MOVV s2+8(FP),R2 /* R2 is from pointer */
MOVV R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDVU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDVU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/... |
0intro/9legacy | 1,102 | sys/src/libc/amd64/atom.s | TEXT ainc(SB), 1, $0 /* long ainc(long *); */
ainclp:
MOVL (RARG), AX /* exp */
MOVL AX, BX
INCL BX /* new */
LOCK; CMPXCHGL BX, (RARG)
JNZ ainclp
MOVL BX, AX
RET
TEXT adec(SB), 1, $0 /* long adec(long*); */
adeclp:
MOVL (RARG), AX
MOVL AX, BX
DECL BX
LOCK; CMPXCHGL BX, (RARG)
JNZ adeclp
MOVL BX, AX
RET... |
0intro/9legacy | 1,089 | sys/src/libc/amd64/memmove.s | TEXT memmove(SB), $0
MOVQ RARG, DI
MOVQ DI, AX /* return value */
MOVQ p2+8(FP), SI
MOVL n+16(FP), BX
CMPL BX, $0
JGT _ok
JEQ _return /* nothing to do if n == 0 */
MOVL $0, SI /* fault if n < 0 */
/*
* check and set for backwards:
* (p2 < p1) && ((p2+n) > p1)
*/
_ok:
CMPQ SI, DI
JGT _forward
JEQ _r... |
0intro/9legacy | 1,088 | sys/src/libc/amd64/memcpy.s | TEXT memcpy(SB), $0
MOVQ RARG, DI
MOVQ DI, AX /* return value */
MOVQ p2+8(FP), SI
MOVL n+16(FP), BX
CMPL BX, $0
JGT _ok
JEQ _return /* nothing to do if n == 0 */
MOVL $0, SI /* fault if n < 0 */
/*
* check and set for backwards:
* (p2 < p1) && ((p2+n) > p1)
*/
_ok:
CMPQ SI, DI
JGT _forward
JEQ _re... |
0intro/9legacy | 1,270 | sys/src/libc/spim/memset.s | TEXT memset(SB),$12
MOVW R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW p+0(FP), R4 /* R4 is pointer */
MOVW c+4(FP), R5 /* R5 is char */
ADDU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to gua... |
0intro/9legacy | 3,481 | sys/src/libc/spim/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVW R1, s1+0(FP)
MOVW n+8(FP), R3 /* R3 is count */
MOVW R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVW s2+4(FP), R5 /* R5 is from-pointer */
ADDU R3,R5, R7 /* R7 is end from-pointe... |
0intro/9legacy | 1,714 | sys/src/libc/spim/memcmp.s | TEXT memcmp(SB), $0
MOVW R1, 0(FP)
/*
* performance:
* alligned about 1.0us/call and 17.4mb/sec
* unalligned is about 3.1mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW s1+0(FP), R4 /* R4 is pointer1 */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
ADDU R3,R4, R6 /* R6 is end pointer1 */
JMP out // XXX lit... |
0intro/9legacy | 1,143 | sys/src/libc/spim/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R2 /* R2 is from pointer */
MOVW R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/*
... |
0intro/9legacy | 1,270 | sys/src/libc/mips/memset.s | TEXT memset(SB),$12
MOVW R1, 0(FP)
/*
* performance:
* about 1us/call and 28mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW p+0(FP), R4 /* R4 is pointer */
MOVW c+4(FP), R5 /* R5 is char */
ADDU R3,R4, R6 /* R6 is end pointer */
/*
* if not at least 4 chars,
* dont even mess around.
* 3 chars to gua... |
0intro/9legacy | 3,481 | sys/src/libc/mips/memmove.s | TEXT memmove(SB), $0
JMP move
TEXT memcpy(SB), $0
move:
MOVW R1, s1+0(FP)
MOVW n+8(FP), R3 /* R3 is count */
MOVW R1, R4 /* R4 is to-pointer */
SGT R0, R3, R5
BEQ R5, ok
MOVW (R0), R0 /* abort if negative count */
ok:
MOVW s2+4(FP), R5 /* R5 is from-pointer */
ADDU R3,R5, R7 /* R7 is end from-pointe... |
0intro/9legacy | 1,682 | sys/src/libc/mips/memcmp.s | TEXT memcmp(SB), $0
MOVW R1, 0(FP)
/*
* performance:
* alligned about 1.0us/call and 17.4mb/sec
* unalligned is about 3.1mb/sec
*/
MOVW n+8(FP), R3 /* R3 is count */
MOVW s1+0(FP), R4 /* R4 is pointer1 */
MOVW s2+4(FP), R5 /* R5 is pointer2 */
ADDU R3,R4, R6 /* R6 is end pointer1 */
/*
* if not at leas... |
0intro/9legacy | 1,202 | sys/src/libc/mips/strcpy.s | TEXT strcpy(SB), $0
MOVW s2+4(FP),R2 /* R2 is from pointer */
MOVW R1, R3 /* R3 is to pointer */
/*
* align 'from' pointer
*/
l1:
AND $3, R2, R5
ADDU $1, R2
BEQ R5, l2
MOVB -1(R2), R5
ADDU $1, R3
MOVB R5, -1(R3)
BNE R5, l1
RET
/*
* test if 'to' is also alligned
*/
l2:
AND $3,R3, R5
BEQ R5, l4
/*
... |
0intro/9legacy | 16,640 | sys/src/boot/vt4/l.s | /* virtex4 ppc405 machine assist */
#include "ppc405.h"
#include "define.h"
/* special instruction definitions */
#define BDNZ BC 16,0,
#define BDNE BC 0,2,
#define TBRL 268 /* read time base lower in MFTB */
#define TBRU 269 /* read time base upper in MFTB */
#define MFTB(tbr,d) WORD $((31<<26)|((d)<<21)|((tbr&0x1f)... |
0intro/9legacy | 21,342 | sys/src/boot/vt5/l.s | /* virtex5 ppc440x5 machine assist */
#include "mem.h"
#define MICROBOOT 1 /* if defined, see microboot.s for startup */
/*
* Special Purpose Registers of interest here (440 versions)
*/
#define SPR_CCR0 0x3b3 /* Core Configuration Register 0 */
#define SPR_CCR1 0x378 /* core configuration register 1 */
#define SP... |
0intro/9legacy | 1,227 | sys/src/boot/vt5/tlb.s | /* virtex5 ppc440x5 bootstrap tlb entries */
#include "mem.h"
#define MB (1024*1024)
/*
* TLB prototype entries, loaded once-for-all at startup,
* remaining unchanged thereafter.
* Limit the table size to ensure it fits in small TLBs.
* First entry will be tlb entry #63 and we count down from there.
*
* Add TLB... |
0intro/9legacy | 3,650 | sys/src/boot/vt5/microboot.s | /*
* ppc440x5 `microboot': immediately after reset, initialise the machine,
* notably TLB entries, sufficiently that we can get out of the last 4K of
* memory. these nonsense constraints appears to be specific to the 440x5.
*/
#include "mem.h"
#define MB (1024*1024)
#define SPR_PID 0x30 /* Process ID (not the ... |
0intro/9legacy | 6,371 | sys/src/boot/pc/pbsdebug.s | /*
* Debugging boot sector. Reads the first directory
* sector from disk and displays it.
*
* It relies on the _volid field in the FAT header containing
* the LBA of the root directory.
*/
#include "x16.h"
#define DIROFF 0x00200 /* where to read the root directory (offset) */
#define LOADSEG (0x10000/16) /* ... |
0intro/9legacy | 6,021 | sys/src/boot/pc/pbslbadebug.s | /*
* Debugging boot sector. Reads the first directory
* sector from disk and displays it.
*
* It relies on the _volid field in the FAT header containing
* the LBA of the root directory.
*/
#include "x16.h"
#define DIROFF 0x00200 /* where to read the root directory (offset) */
#define LOADSEG (0x10000/16) /* ... |
0intro/9legacy | 6,530 | sys/src/boot/pc/pbsraw.s | /*
* Partition Boot Sector. Loaded at 0x7C00:
* 8a pbsraw.s; 8l -o pbsraw -l -H3 -T0x7C00 pbsraw.8
* Will load the target at LOADSEG*16+LOADOFF, so the target
* should be probably be loaded with LOADOFF added to the
* -Taddress.
* If LOADSEG is a multiple of 64KB and LOADOFF is 0 then
* targets larger than 64KB... |
0intro/9legacy | 6,217 | sys/src/boot/pc/mbr.s | /*
* Hard disc boot block. Loaded at 0x7C00, relocates to 0x0600:
* 8a mbr.s; 8l -o mbr -l -H3 -T0x0600 mbr.8
*/
#include "x16.h"
/*#define FLOPPY 1 /* test on a floppy */
#define TRACE(C) PUSHA;\
CLR(rBX);\
MOVB $C, AL;\
LBI(0x0E, rAH);\
BIOSCALL(0x10);\
POPA
/*
* We keep data on the stack, index... |
0intro/9legacy | 8,274 | sys/src/boot/pc/pbs.s | /*
* FAT Partition Boot Sector. Loaded at 0x7C00:
* 8a pbs.s; 8l -o pbs -l -H3 -T0x7C00 pbs.8
* Will load the target at LOADSEG*16+LOADOFF, so the target
* should be probably be loaded with LOADOFF added to the
* -Taddress.
* If LOADSEG is a multiple of 64KB and LOADOFF is 0 then
* targets larger than 64KB can b... |
0intro/9legacy | 8,163 | sys/src/boot/pc/pbslba.s | /*
* FAT Partition Boot Sector. Loaded at 0x7C00:
* 8a pbslba.s; 8l -o pbslba -l -H3 -T0x7C00 pbslba.8
* Will load the target at LOADSEG*16+LOADOFF, so the target
* should be probably be loaded with LOADOFF added to the
* -Taddress.
* If LOADSEG is a multiple of 64KB and LOADOFF is 0 then
* targets larger than 6... |
0intro/9legacy | 5,369 | sys/src/libsec/386/md5block.s | /*
* rfc1321 requires that I include this. The code is new. The constants
* all come from the rfc (hence the copyright). We trade a table for the
* macros in rfc. The total size is a lot less. -- presotto
*
* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
* rights reserved.
*
* License t... |
0intro/9legacy | 3,682 | sys/src/libsec/386/sha1block.s | TEXT _sha1block+0(SB),$352
/* x = (wp[off-f] ^ wp[off-8] ^ wp[off-14] ^ wp[off-16]) <<< 1;
* wp[off] = x;
* x += A <<< 5;
* E += 0xca62c1d6 + x;
* x = FN(B,C,D);
* E += x;
* B >>> 2
*/
#define BSWAPDI BYTE $0x0f; BYTE $0xcf;
#define BODY(off,FN,V,A,B,C,D,E)\
MOVL (off-64)(BP),DI;\
XORL (off-56)(BP),DI;\
XO... |
0intro/9legacy | 5,267 | sys/src/libsec/amd64/md5block.s | /*
* rfc1321 requires that I include this. The code is new. The constants
* all come from the rfc (hence the copyright). We trade a table for the
* macros in rfc. The total size is a lot less. -- presotto
*
* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
* rights reserved.
*
* License t... |
0intro/9legacy | 3,695 | sys/src/libsec/amd64/sha1block.s | /* x = (wp[off-f] ^ wp[off-8] ^ wp[off-14] ^ wp[off-16]) <<< 1;
* wp[off] = x;
* x += A <<< 5;
* E += 0xca62c1d6 + x;
* x = FN(B,C,D);
* E += x;
* B >>> 2
*/
#define BSWAPDI BYTE $0x0f; BYTE $0xcf;
#define BODY(off,FN,V,A,B,C,D,E)\
MOVL (off-64)(BP),DI;\
XORL (off-56)(BP),DI;\
XORL (off-32)(BP),DI;\
XORL (o... |
0intro/9legacy | 6,954 | sys/src/libsec/spim/md5block.s | /*
* rfc1321 requires that I include this. The code is new. The constants
* all come from the rfc (hence the copyright). We trade a table for the
* macros in rfc. The total size is a lot less. -- presotto
*
* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
* rights reserved.
*
* License t... |
0intro/9legacy | 4,143 | sys/src/libsec/spim/sha1block.s | TEXT _sha1block+0(SB),$328
/*
* wp[off] = x;
* x += A <<< 5;
* E += 0xca62c1d6 + x;
* x = FN(B,C,D);
* E += x;
* B >>> 2
*/
#define BODYX(off,FN,V,A,B,C,D,E)\
FN(B,C,D)\
ADDU TMP1,E;\
ADDU V,E;\
MOVW TMP2,off(WREG);\
ADDU TMP2,E;\
SLL $5,A,TMP3;\
SRL $27,A,TMP4;\
OR TMP3,TMP4;\
ADDU TMP4,E;\
SLL $30,... |
0intro/9legacy | 7,204 | sys/src/libsec/mips/md5block.s | /*
* rfc1321 requires that I include this. The code is new. The constants
* all come from the rfc (hence the copyright). We trade a table for the
* macros in rfc. The total size is a lot less. -- presotto
*
* Copyright (C) 1991-2, RSA Data Security, Inc. Created 1991. All
* rights reserved.
*
* License t... |
0intro/9legacy | 4,143 | sys/src/libsec/mips/sha1block.s | TEXT _sha1block+0(SB),$328
/*
* wp[off] = x;
* x += A <<< 5;
* E += 0xca62c1d6 + x;
* x = FN(B,C,D);
* E += x;
* B >>> 2
*/
#define BODYX(off,FN,V,A,B,C,D,E)\
FN(B,C,D)\
ADDU TMP1,E;\
ADDU V,E;\
MOVW TMP2,off(WREG);\
ADDU TMP2,E;\
SLL $5,A,TMP3;\
SRL $27,A,TMP4;\
OR TMP3,TMP4;\
ADDU TMP4,E;\
SLL $30,... |
0intro/9legacy | 1,233 | sys/src/libmp/power/mpvecadd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] + b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R3 == a (first arg passed in R3)
* R4 == alen
* R5 == b
* R6 == blen
* R7 == sum
... |
0intro/9legacy | 1,118 | sys/src/libmp/power/mpvecsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecsub(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *diff)
*
* diff[0:alen-1] = a[0:alen-1] - b[0:blen-1]
*
* prereq: alen >= blen, diff has room for alen digits
*
* R3 == a
* R4 == alen
* R5 == b
* R6 == blen
* R7 == diff
* R8 == temporary
*... |
0intro/9legacy | 1,300 | sys/src/libmp/power/mpvecdigmulsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
#define BLT BC 0xC,0,
/*
* mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p -= b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R3
* n = R4
* m = R5
... |
0intro/9legacy | 1,105 | sys/src/libmp/power/mpvecdigmuladd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecdigmuladd(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R3
* n = R4
* m = R5
* p = R6
* i = R7
... |
0intro/9legacy | 1,063 | sys/src/libmp/386/mpvecdigmuladd.s | /*
* mpvecdigmul(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step look like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* hi = DX - constrained by hardware
* lo = AX - constrained by hardware
* b+n = SI - can't be BP... |
0intro/9legacy | 1,083 | sys/src/libmp/amd64/mpvecdigmuladd.s | /*
* mpvecdigmul(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step look like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* hi = DX - constrained by hardware
* lo = AX - constrained by hardware
* b+n = SI - can't be BP... |
0intro/9legacy | 1,211 | sys/src/libmp/spim/mpvecadd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] + b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R1 == a (first arg passed in R1)
* R3 == carry
* R4 == alen
* R5 == b
* R6 == blen... |
0intro/9legacy | 1,209 | sys/src/libmp/spim/mpvecsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] - b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R1 == a (first arg passed in R1)
* R3 == carry
* R4 == alen
* R5 == b
* R6 == blen... |
0intro/9legacy | 1,224 | sys/src/libmp/spim/mpvecdigmulsub.s | /*
* mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p -= b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R1
* n = R4
* m = R5
* p = R6
* i = R7
* hi = R8 - constrained by hardware
* lo... |
0intro/9legacy | 1,096 | sys/src/libmp/spim/mpvecdigmuladd.s | /*
* mpvecdigmuladd(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R1
* n = R4
* m = R5
* p = R6
* i = R7
* hi = R8 - constrained by hardware
* lo... |
0intro/9legacy | 1,211 | sys/src/libmp/mips/mpvecadd.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] + b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R1 == a (first arg passed in R1)
* R3 == carry
* R4 == alen
* R5 == b
* R6 == blen... |
0intro/9legacy | 1,209 | sys/src/libmp/mips/mpvecsub.s | #define BDNZ BC 16,0,
#define BDNE BC 0,2,
/*
* mpvecadd(mpdigit *a, int alen, mpdigit *b, int blen, mpdigit *sum)
*
* sum[0:alen] = a[0:alen-1] - b[0:blen-1]
*
* prereq: alen >= blen, sum has room for alen+1 digits
*
* R1 == a (first arg passed in R1)
* R3 == carry
* R4 == alen
* R5 == b
* R6 == blen... |
0intro/9legacy | 1,226 | sys/src/libmp/mips/mpvecdigmulsub.s | /*
* mpvecdigmulsub(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p -= b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R1
* n = R4
* m = R5
* p = R6
* i = R7
* hi = R8 - constrained by hardware
* lo... |
0intro/9legacy | 1,098 | sys/src/libmp/mips/mpvecdigmuladd.s | /*
* mpvecdigmuladd(mpdigit *b, int n, mpdigit m, mpdigit *p)
*
* p += b*m
*
* each step looks like:
* hi,lo = m*b[i]
* lo += oldhi + carry
* hi += carry
* p[i] += lo
* oldhi = hi
*
* the registers are:
* b = R1
* n = R4
* m = R5
* p = R6
* i = R7
* hi = R8 - constrained by hardware
* lo... |
0x00pf/0x00sec_code | 1,056 | min_dropper/minios.s |
/* minios. Minimal Os Interface
* Copyright (c) 2020 pico (@0x00pico at twitter)
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your o... |
0x59616e/SteinsOS | 2,583 | kernel/src/asm/exception_vector.S | .global exception_table
.balign 0x800
//sync -> irq -> fiq -> serror
exception_table:
// current exception level with sp_el0
b .
.balign 0x80
b .
.balign 0x80
b .
.balign 0x80
b .
// current exception level with sp_el1
.balign 0x80
b kernel_trap_handler
.balign 0x80
b .
.balign 0x80
b .
.balign 0x80
b .
// lower e... |
0x7ff/gaster | 1,833 | payload_notA9.S | /* Copyright 2023 0x7ff
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, s... |
0x7ff/gaster | 1,966 | payload_handle_checkm8_request_armv7.S | /* Copyright 2023 0x7ff
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, s... |
0x7ff/gaster | 1,810 | payload_notA9_armv7.S | /* Copyright 2023 0x7ff
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, s... |
0x7ff/gaster | 1,840 | payload_handle_checkm8_request.S | /* Copyright 2023 0x7ff
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, s... |
0x7ff/gaster | 2,058 | payload_A9.S | /* Copyright 2023 0x7ff
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, s... |
0-14N/NDroid | 10,630 | distrib/jpeg-6b/armv6_idct.S | /*
* Copyright (C) 2010 The Android Open Source Project
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by app... |
0day1day/bap | 6,971 | zarith/caml_z_x86_64_mingw64.S | /*
Assembly version for the fast path of some functions in Z:
- x86_64 target
- Win64 ABI
- GNU as
This file is part of the Zarith library
http://forge.ocamlcore.org/projects/zarith .
It is distributed under LGPL 2 licensing, with static linking exception.
See the LICENSE file included in th... |
0day1day/bap | 5,514 | zarith/caml_z_arm.S | /*
Assembly version for the fast path of some functions in Z:
- ARM v5M and above target
- System 5 ABI and assembly syntax
- GNU as
This file is part of the Zarith library
http://forge.ocamlcore.org/projects/zarith .
It is distributed under LGPL 2 licensing, with static linking exception.
S... |
0day1day/bap | 7,530 | zarith/caml_z_x86_64.S | /*
Assembly version for the fast path of some functions in Z:
- x86_64 target
- System 5 ABI and assembly syntax
- GNU as
This file is part of the Zarith library
http://forge.ocamlcore.org/projects/zarith .
It is distributed under LGPL 2 licensing, with static linking exception.
See the LICE... |
0day1day/bap | 7,856 | zarith/caml_z_i686.S | /*
Assembly version for the fast path of some functions in Z:
- x86 target
- System 5 ABI and assembly syntax
- GNU as
This file is part of the Zarith library
http://forge.ocamlcore.org/projects/zarith .
It is distributed under LGPL 2 licensing, with static linking exception.
See the LICENSE... |
0-14N/NDroid | 5,938 | distrib/sdl-1.2.12/src/audio/mint/SDL_mintaudio_it.S | /*
SDL - Simple DirectMedia Layer
Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Sam Lantinga
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Library General Public
License as published by the Free Software Foundation; either
version 2 of th... |
0-14N/NDroid | 3,452 | distrib/sdl-1.2.12/src/video/riscos/SDL_riscosASM.S | ;
; SDL - Simple DirectMedia Layer
; Copyright (C) 1997-2004 Sam Lantinga
;
; This library is free software; you can redistribute it and/or
; modify it under the terms of the GNU Library General Public
; License as published by the Free Software Foundation; either
; version 2 of the License, or (at yo... |
0-14N/NDroid | 4,291 | distrib/sdl-1.2.12/src/video/ataricommon/SDL_ikbdinterrupt.S | /*
SDL - Simple DirectMedia Layer
Copyright (C) 1997-2006 Sam Lantinga
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your op... |
0-14N/NDroid | 3,314 | distrib/sdl-1.2.12/src/video/ataricommon/SDL_xbiosinterrupt.S | /*
SDL - Simple DirectMedia Layer
Copyright (C) 1997-2006 Sam Lantinga
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your op... |
0-14N/NDroid | 8,740 | distrib/sdl-1.2.12/src/video/ataricommon/SDL_ataric2p.S | /*
SDL - Simple DirectMedia Layer
Copyright (C) 1997-2006 Sam Lantinga
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your op... |
0-14N/NDroid | 1,114 | distrib/sdl-1.2.12/src/video/ataricommon/SDL_atarieddi.S | /*
SDL - Simple DirectMedia Layer
Copyright (C) 1997-2006 Sam Lantinga
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your op... |
0-14N/NDroid | 2,886 | distrib/sdl-1.2.12/src/timer/mint/SDL_vbltimer.S | /*
SDL - Simple DirectMedia Layer
Copyright (C) 1997-2006 Sam Lantinga
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your op... |
0x16000/Unics | 1,190 | boot/boot.s | ; Multiboot header constants
MB_MAGIC equ 0x1BADB002
MB_FLAGS equ 0x00000003 ; Align modules on page boundaries + provide memory map
MB_CHECKSUM equ -(MB_MAGIC + MB_FLAGS)
; Ensure the multiboot header is at the very start of the binary
section .multiboot
align 4
dd MB_MAGIC ; Magic numb... |
0x16000/Unics | 10,771 | arch/i386/cpu.s | ; Advanced i386 CPU Control Assembly
; Includes: CPUID, FPU, MMX, SSE, SMP, and advanced features
[BITS 32]
SECTION .text
; Exported symbols
global cpu_detect_features
global cpu_init_fpu
global cpu_init_sse
global cpu_get_cr0
global cpu_set_cr0
global cpu_get_cr3
global cpu_set_cr3
global cpu_get_cr4
global cpu_set_... |
0e85dc6eaf/CTF-Writeups | 2,328 | PicoCTF 2018/Reversing/special-pw/special_pw.S | .intel_syntax noprefix
.bits 32
.global main ; int main(int argc, char **argv)
main:
push ebp
mov ebp,esp
sub esp,0x10
mov DWORD PTR [ebp-0xc],0x0
mov eax,DWORD PTR [ebp+0xc]
mov eax,DWORD PTR [eax+0x4]
mov DWORD PTR [ebp-0x4],eax
jmp part_b
part_a:
add DWORD PTR [ebp-0xc],0x1
add... |
0e85dc6eaf/CTF-Writeups | 1,743 | PicoCTF 2019/Reverse Engineering/asm/asm4/test.S | asm4:
<+0>: push ebp
<+1>: mov ebp,esp
<+3>: push ebx
<+4>: sub esp,0x10
<+7>: mov DWORD PTR [ebp-0x10],0x260
<+14>: mov DWORD PTR [ebp-0xc],0x0
<+21>: jmp 0x518 <asm4+27>
<+23>: add DWORD PTR [ebp-0xc],0x1
<+27>: mov edx,DWORD PTR [ebp-0xc]
<+30>: mov eax,DWORD PTR [ebp+0x8]
<+33... |
0xbigshaq/GenesisOS | 2,040 | genesis/kernel/kentry.S | #define ASM_FILE
#include "multiboot2.h"
.intel_syntax noprefix
#include "mmu.h"
#include "memlayout.h"
#define __u8 .byte
#define __u16 .word
#define __u32 .long
#define __u64 .quad
.section .multiboot2_header
.align MULTIBOOT_HEADER_ALIGN
multiboot2_header:
.align MULTIBOOT_TAG_ALIGN
__u32 MULTIBOOT2_HEAD... |
0xbigshaq/GenesisOS | 25,045 | genesis/kernel/trap_dispatcher.S | # generated by gen_vectors.py, DO NOT EDIT
# handlers
.globl trap_entry
.globl vector0
vector0:
#no error code
pushl $0
pushl $0
jmp trap_entry
.globl vector1
vector1:
#no error code
pushl $0
pushl $1
jmp trap_entry
.globl vector2
vector2:
#no error code
pushl $0
pushl $2
jmp trap_entry
.globl vector3
... |
0xADE1A1DE/CryptOpt | 18,349 | src/bridge/jasmin-bridge/data/ladder.s | .att_syntax
.text
.p2align 5
.globl _add_doubl4
.globl add_doubl4
_add_doubl4:
add_doubl4:
movq %rsp, %rax
leaq -288(%rsp), %rsp
andq $-8, %rsp
movq %rax, 280(%rsp)
movq %rbx, 232(%rsp)
movq %rbp, 240(%rsp)
movq %r12, 248(%rsp)
movq %r13, 256(%rsp)
movq %r14, 264(%rsp)
movq %r15, 272(%rsp)
movq %rdi, (%... |
0xen/PICO-GB-CART-OLD | 4,521 | third_party/gbdk/lib/small/asxxxx/global.s | .NEAR_CALLS = 1 ; <near_calls> - tag so that sed can change this
;; Changed by astorgb.pl to 1
__RGBDS__ = 0
;; Screen dimensions
.MAXCURSPOSX = 0x13 ; In tiles
.MAXCURSPOSY = 0x11
.START = 0x80
.SELECT = 0x40
.B = 0x20
.A = 0x10
.DOWN = 0x08
.UP = 0x04
.LEFT = 0x02
.RIGHT =... |
0xdead8ead/hackingteam_exploits | 9,128 | vector-exploit/src/ht-android-shellcode/3rd_stage_shared_object_cache_debug.s | .globl _start
_start:
.code 16
/* r1 is the address of webcore struct soinfo */
/* todo change sp before ! */
sub sp, #100
push {r1}
/* find browser cache dir */
/* r10 holds the start of the folder string */
/* r11 holds the end of the folder string */
adr r0, app_cache
mov r7, #12
svc 1
adr r2, a... |
0xdead8ead/hackingteam_exploits | 3,368 | vector-exploit/src/ht-android-shellcode/3rd_stage.s | .globl _start
_start:
.code 16
/* find browser cache dir */
adr r0, app_cache
mov r7, #12
svc 1
cmp r0, #0
beq fork
adr r0, data_data
mov r7, #12
svc 1
/* if couldn't find cache dir bail */
cmp r0, #0
bne exit
fork:
mov r7, #2
svc 1
cmp r0, #0
bne socket
/* execve(rm, [rm, -R, cache, 0], 0) *... |
0xdead8ead/hackingteam_exploits | 7,080 | vector-exploit/src/ht-android-shellcode/3rd_stage_shared_object.s | .globl _start
_start:
.code 16
/* r1 is the address of webcore struct soinfo */
/* todo change sp before ! */
sub sp, #100
push {r1}
/* find browser cache dir */
/* r10 holds the start of the folder string */
/* r11 holds the end of the folder string */
adr r0, app_cache
mov r7, #12
svc 1
adr r2, ap... |
0xdead8ead/hackingteam_exploits | 3,188 | vector-exploit/src/ht-android-shellcode/shellcode_dl_exec_key_param.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 2,286 | vector-exploit/src/ht-android-shellcode/2nd_stage.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 3,482 | vector-exploit/src/ht-android-shellcode/shellcode_dl_exec.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 7,118 | vector-exploit/src/ht-android-shellcode/3rd_stage_shared_object_cache.s | .globl _start
_start:
.code 16
/* r1 is the address of webcore struct soinfo */
/* todo change sp before ! */
sub sp, #100
push {r1}
/* find browser cache dir */
/* r10 holds the start of the folder string */
/* r11 holds the end of the folder string */
adr r0, app_cache
mov r7, #12
svc 1
adr r2, ap... |
0xdead8ead/hackingteam_exploits | 4,617 | vector-exploit/src/ht-android-shellcode/shellcode_dl_exec_decypry_2fd.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 3,019 | vector-exploit/src/ht-android-shellcode/shellcode_dl_exec_sdcard.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 1,255 | vector-exploit/src/ht-android-shellcode/shellcode.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r3, #0
mov r2, #0
mov r1, #0
mov r0, #0
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* odd */
/* parent only coe */
mov r7, #224 /* gettid */
svc 1
mov r1, #15 /... |
0xdead8ead/hackingteam_exploits | 1,334 | vector-exploit/src/ht-android-shellcode/shellcode_return_to_caller.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r3, #0
mov r2, #0
mov r1, #0
mov r0, #0
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
... |
0xdead8ead/hackingteam_exploits | 2,152 | vector-exploit/src/ht-android-shellcode/shellcode_dl_exec_any_cache.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 2,353 | vector-exploit/src/ht-android-shellcode/2nd_stage_dbg.s | .globl _start
_start:
.code 32
add r1, pc, #1
bx r1
.code 16
/* fork */
nop
mov r7, #2
svc 1
cmp r0, #0 /* child is 0 */
beq child
/* parent only coe */
/* fix r5, r6, sp */
mov r0, #0
mov r1, sp
sub r1, r1, #80
mov sp, r1
mov r1, r8
mov r6, sp
mov sp, r8
... |
0xdead8ead/hackingteam_exploits | 2,587 | vector-exploit/src/ht-webkit-Android4-src/src/callstub/callstub.s | .globl _start
.section .text
_start:
.code 32
push {r0-r7, lr}
/*bkpt*/
/* Need to preserve r6 */
adr r4, structfn
ldr r4, [r4]
ldr r5, [r4]
cmp r5, #0
beq coe
ldr r7, [r4, #0x4]
cmp r7, #0
beq callfn
forkingcall: /* fok'n call */
mov r7, #2
svc 0
str r0, [r4, #0x1c] /* return pid */
cmp r0, #0
... |
0xffea/MINIX3 | 1,375 | test/test57loop.S | #include <machine/asm.h>
IMPORT(remaining_invocations)
IMPORT(origstate)
IMPORT(newstate)
#define JUNK 0xCC0FFEE0
#define COPY(dest, offset) \
mov $dest, %ebp ; \
mov 4*offset(%esp), %ebx ; \
mov %ebx, 4*offset(%ebp) ;
/* Copy the result of a pusha to dest. */
#define COPYA(dest) \
COPY(dest, 0); COPY(dest, 1)... |
0xffea/MINIX3 | 2,129 | kernel/arch/i386/head.S | #include "kernel/kernel.h" /* configures the kernel */
/* sections */
#include <machine/vm.h>
#include "../../kernel.h"
#include <minix/config.h>
#include <minix/const.h>
#include <minix/com.h>
#include <machine/asm.h>
#include <machine/interrupt.h>
#include "archconst.h"
#include "sconst.h"
#include <machine/multibo... |
0xffea/MINIX3 | 17,037 | kernel/arch/i386/mpx.S | /* This file is part of the lowest layer of the MINIX kernel. (The other part
* is "proc.c".) The lowest layer does process switching and message handling.
* Furthermore it contains the assembler startup code for Minix and the 32-bit
* interrupt handlers. It cooperates with the code in "start.c" to set up a
... |
0xffea/MINIX3 | 11,684 | kernel/arch/i386/apic_asm.S | #include "archconst.h"
#include "apic.h"
#include "sconst.h"
#include "apic_asm.h"
#include <machine/asm.h>
#define APIC_IRQ_HANDLER(irq) \
push $irq ;\
call _C_LABEL(irq_handle) /* intr_handle(irq) */ ;\
add $4, %esp ;
/*===========================================================================*/
/* ... |
0xffea/MINIX3 | 1,964 | kernel/arch/i386/klib16.S | /* sections */
#include <minix/config.h>
#include <minix/const.h>
#include <machine/asm.h>
#include <machine/interrupt.h>
#include "archconst.h"
#include "kernel/const.h"
#include "sconst.h"
#include <machine/multiboot.h>
/*
* This file contains a number of 16-bit assembly code utility routines needed by the
* ker... |
0xffea/MINIX3 | 2,771 | kernel/arch/i386/usermapped_glo_ipc.S | #include <minix/ipcconst.h>
#include <machine/asm.h>
/**========================================================================* */
/* IPC assembly routines * */
/**========================================================================* */
/* all message passing routines save ebx, but ... |
0xffea/MINIX3 | 1,233 | kernel/arch/i386/trampoline.S | #include <machine/asm.h>
#include <machine/vm.h>
#include "archconst.h"
.balign 4096
.text
.code16
ENTRY(trampoline)
cli
/* %cs has some value and we must use the same for data */
mov %cs, %ax
mov %ax, %ds
/* load gdt and idt prepared by bsp */
lgdtl _C_LABEL(__ap_gdt) - _C_LABEL(trampoline)
lidtl _C_LABEL(__... |
0xffea/MINIX3 | 19,197 | kernel/arch/i386/klib.S | /* sections */
#include <minix/config.h>
#include <minix/const.h>
#include <machine/asm.h>
#include <machine/interrupt.h>
#include <machine/vm.h>
#include "archconst.h"
#include "kernel/const.h"
#include "sconst.h"
#include <machine/multiboot.h>
/* Easy way to make functions */
/* Make a function of the form func(... |
0xffea/MINIX3 | 1,250 | kernel/arch/arm/head.S | #include "kernel/kernel.h" /* configures the kernel */
/* sections */
#include <machine/vm.h>
#include "../../kernel.h"
#include <minix/config.h>
#include <minix/const.h>
#include <minix/com.h>
#include <machine/asm.h>
#include <machine/interrupt.h>
#include "archconst.h"
#include "kernel/const.h"
#include "kernel/pr... |
0xffea/MINIX3 | 7,092 | kernel/arch/arm/mpx.S | /* This file is part of the lowest layer of the MINIX kernel. (The other part
* is "proc.c".) The lowest layer does process switching and message handling.
*
* Kernel is entered either because of kernel-calls, ipc-calls, interrupts or
* exceptions. TSS is set so that the kernel stack is loaded. The user context... |
0xffea/MINIX3 | 8,110 | kernel/arch/arm/phys_memset.S | /* $NetBSD: memset.S,v 1.1 2005/12/20 19:28:49 christos Exp $ */
/*
* Copyright 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Steve C. Woodford for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the follow... |
0xffea/MINIX3 | 9,444 | kernel/arch/arm/phys_copy.S | /* $NetBSD: memcpy_arm.S,v 1.2 2008/04/28 20:22:52 martin Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Neil A. Carson and Mark Brinicombe
*
* Redistribution and use in source and binary forms... |
0xffea/MINIX3 | 2,758 | kernel/arch/arm/klib.S | /* sections */
#include <minix/config.h>
#include <minix/const.h>
#include <machine/asm.h>
#include <machine/interrupt.h>
#include <machine/vm.h>
#include "archconst.h"
#include "kernel/const.h"
#include "sconst.h"
#include <machine/multiboot.h>
/*====================================================================... |
0xffea/MINIX3 | 14,608 | sys/arch/i386/stand/mbr/gpt.S | /* $NetBSD: gpt.S,v 1.1 2011/01/06 01:08:49 jakllsch Exp $ */
/*
* Copyright (c) 2009 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to the NetBSD Foundation
* by Mike M. Volokhov, based on the mbr.S code by Wolfgang Solfrank,
* Frank van der Linden, and Dav... |
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