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| size
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AAAAyl0n/Lambda0
| 15,145
|
1.Hardware/Screen/1.28英寸GC9A01圆形TFT资料/代码/STM32/STM32F10x/ASM/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 9,377
|
1.Hardware/Screen/1.28英寸GC9A01圆形TFT资料/代码/STM32/STM32F10x/ASM/stm32f10x_startup.s
|
;***************************************************************************************
; Amount of memory (in bytes) allocated for Stack and Heap
; Tailor those values to your application needs
;***************************************************************************************
Stack_Size EQU 0x400
Heap_Size EQU 0x400
;*******************************************************************************
; Allocate space for the Stack
;*******************************************************************************
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack
SPACE Stack_Size
;*******************************************************************************
; Allocate space for the Heap
;*******************************************************************************
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap
SPACE Heap_Size
;********************************************************************************
;* Declarations for the interrupt handlers that are used by the application.
;********************************************************************************
IMPORT __main
IMPORT OSPendSV
IMPORT SysTickHandler
IMPORT WWDG_IRQHandler
IMPORT PVD_IRQHandler
IMPORT TAMPER_IRQHandler
IMPORT RTC_IRQHandler
IMPORT FLASH_IRQHandler
IMPORT RCC_IRQHandler
IMPORT EXTI0_IRQHandler
IMPORT EXTI1_IRQHandler
IMPORT EXTI2_IRQHandler
IMPORT EXTI3_IRQHandler
IMPORT EXTI4_IRQHandler
IMPORT DMAChannel1_IRQHandler
IMPORT DMAChannel2_IRQHandler
IMPORT DMAChannel3_IRQHandler
IMPORT DMAChannel4_IRQHandler
IMPORT DMAChannel5_IRQHandler
IMPORT DMAChannel6_IRQHandler
IMPORT DMAChannel7_IRQHandler
IMPORT ADC_IRQHandler
IMPORT USB_HP_CAN_TX_IRQHandler
IMPORT USB_LP_CAN_RX0_IRQHandler
IMPORT CAN_RX1_IRQHandler
IMPORT CAN_SCE_IRQHandler
IMPORT EXTI9_5_IRQHandler
IMPORT TIM1_BRK_IRQHandler
IMPORT TIM1_UP_IRQHandler
IMPORT TIM1_TRG_COM_IRQHandler
IMPORT TIM1_CC_IRQHandler
IMPORT TIM2_IRQHandler
IMPORT TIM3_IRQHandler
IMPORT TIM4_IRQHandler
IMPORT I2C1_EV_IRQHandler
IMPORT I2C1_ER_IRQHandler
IMPORT I2C2_EV_IRQHandler
IMPORT I2C2_ER_IRQHandler
IMPORT SPI1_IRQHandler
IMPORT SPI2_IRQHandler
IMPORT USART1_IRQHandler
IMPORT USART2_IRQHandler
IMPORT USART3_IRQHandler
IMPORT EXTI15_10_IRQHandler
IMPORT RTCAlarm_IRQHandler
IMPORT USBWakeUp_IRQHandler
PRESERVE8
;**********************************************************************************
;* Reset code section.
;**********************************************************************************
AREA RESET, CODE, READONLY
THUMB
;*******************************************************************************
; Fill-up the Vector Table entries with the exceptions ISR address
;*******************************************************************************
EXPORT __Vectors
__Vectors
DCD Stack + Stack_Size ; Top of Stack
DCD Reset_Handler
DCD NMIException
DCD HardFaultException
DCD MemManageException
DCD BusFaultException
DCD UsageFaultException
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVCHandler
DCD DebugMonitor
DCD 0 ; Reserved
DCD OSPendSV
DCD SysTickHandler
DCD WWDG_IRQHandler
DCD PVD_IRQHandler
DCD TAMPER_IRQHandler
DCD RTC_IRQHandler
DCD FLASH_IRQHandler
DCD RCC_IRQHandler
DCD EXTI0_IRQHandler
DCD EXTI1_IRQHandler
DCD EXTI2_IRQHandler
DCD EXTI3_IRQHandler
DCD EXTI4_IRQHandler
DCD DMAChannel1_IRQHandler
DCD DMAChannel2_IRQHandler
DCD DMAChannel3_IRQHandler
DCD DMAChannel4_IRQHandler
DCD DMAChannel5_IRQHandler
DCD DMAChannel6_IRQHandler
DCD DMAChannel7_IRQHandler
DCD ADC_IRQHandler
DCD USB_HP_CAN_TX_IRQHandler
DCD USB_LP_CAN_RX0_IRQHandler
DCD CAN_RX1_IRQHandler
DCD CAN_SCE_IRQHandler
DCD EXTI9_5_IRQHandler
DCD TIM1_BRK_IRQHandler
DCD TIM1_UP_IRQHandler
DCD TIM1_TRG_COM_IRQHandler
DCD TIM1_CC_IRQHandler
DCD TIM2_IRQHandler
DCD TIM3_IRQHandler
DCD TIM4_IRQHandler
DCD I2C1_EV_IRQHandler
DCD I2C1_ER_IRQHandler
DCD I2C2_EV_IRQHandler
DCD I2C2_ER_IRQHandler
DCD SPI1_IRQHandler
DCD SPI2_IRQHandler
DCD USART1_IRQHandler
DCD USART2_IRQHandler
DCD USART3_IRQHandler
DCD EXTI15_10_IRQHandler
DCD RTCAlarm_IRQHandler
DCD USBWakeUp_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
;******************************************************************************************
;* Reset entry
;******************************************************************************************
EXPORT Reset_Handler
Reset_Handler
IMPORT __main
LDR R0, =__main
BX R0
;******************************************************************************************
;* NMI exception handler.
;* It simply enters an infinite loop.
;******************************************************************************************
NMIException
B NMIException
;******************************************************************************************
;* Fault interrupt handler.
;* It simply enters an infinite loop.
;******************************************************************************************
HardFaultException
B HardFaultException
;******************************************************************************************
;* MemManage interrupt handler.
;* It simply enters an infinite loop.
;******************************************************************************************
MemManageException
B MemManageException
;******************************************************************************************
;* Bus Fault interrupt handler.
;* It simply enters an infinite loop.
;******************************************************************************************
BusFaultException
B BusFaultException
;******************************************************************************************
;* UsageFault interrupt handler.
;* It simply enters an infinite loop.
;******************************************************************************************
UsageFaultException
B UsageFaultException
;******************************************************************************************
;* DebugMonitor interrupt handler.
;* It simply enters an infinite loop.
;******************************************************************************************
DebugMonitor
B DebugMonitor
;******************************************************************************************
;* SVCall interrupt handler.
;* It simply enters an infinite loop.
;******************************************************************************************
SVCHandler
B SVCHandler
;*******************************************************************************************
;* Make sure the end of this section is aligned.
;*******************************************************************************************
ALIGN
;********************************************************************************************
;* Code section for initializing the heap and stack
;********************************************************************************************
AREA |.text|, CODE, READONLY
;********************************************************************************************
;* The function expected of the C library startup
;* code for defining the stack and heap memory locations.
;********************************************************************************************
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, =Heap
LDR R1, =(Stack + Stack_Size)
LDR R2, =(Heap + Heap_Size)
LDR R3, =Stack
BX LR
;******************************************************************************************
;* Make sure the end of this section is aligned.
;******************************************************************************************
ALIGN
;*******************************************************************************************
;* End Of File
;*******************************************************************************************
END
|
AAAAyl0n/Lambda0
| 15,592
|
1.Hardware/Screen/1.28英寸GC9A01圆形TFT资料/代码/STM32/STM32F10x/ASM/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.3.0
;* Date : 04/16/2010
;* Description : STM32F10x XL-Density Devices vector table for RVMDK
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 13,347
|
1.Hardware/Screen/1.28英寸GC9A01圆形TFT资料/代码/STM32/STM32F10x/ASM/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.3.0
;* Date : 04/16/2010
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for RVMDK toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 29,171
|
1.Hardware/Screen/1.28英寸GC9A01圆形TFT资料/代码/STM32/STM32F407/CORE/startup_stm32f40_41xxx.s
|
;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
;* File Name : startup_stm32f40_41xxx.s
;* Author : MCD Application Team
;* @version : V1.4.0
;* @date : 04-August-2014
;* Description : STM32F40xxx/41xxx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the system clock and the external SRAM mounted on
;* STM324xG-EVAL board to be used as data memory (optional,
;* to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM4 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
; You may not use this file except in compliance with the License.
; You may obtain a copy of the License at:
;
; http://www.st.com/software_license_agreement_liberty_v2
;
; Unless required by applicable law or agreed to in writing, software
; distributed under the License is distributed on an "AS IS" BASIS,
; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; See the License for the specific language governing permissions and
; limitations under the License.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
DCD FPU_IRQHandler ; FPU
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
EXPORT FPU_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
FPU_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 12,472
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_md.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000C00 ;0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 12,079
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_ld.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1_2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 13,758
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_md_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_md_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Medium Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 15,398
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_cl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_cl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Connectivity line devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 and ADC2
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C1 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC alarm through EXTI line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_IRQHandler ; DMA2 Channel4
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_IRQHandler
DMA2_Channel5_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 15,145
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_hd.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_IRQHandler ; TIM1 Break
DCD TIM1_UP_IRQHandler ; TIM1 Update
DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_IRQHandler ; TIM8 Break
DCD TIM8_UP_IRQHandler ; TIM8 Update
DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_IRQHandler [WEAK]
EXPORT TIM1_UP_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_IRQHandler [WEAK]
EXPORT TIM8_UP_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_IRQHandler
TIM1_UP_IRQHandler
TIM1_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_IRQHandler
TIM8_UP_IRQHandler
TIM8_TRG_COM_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 15,597
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_xl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_xl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x XL-Density Devices vector table for MDK-ARM
;* toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM3210E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD ADC3_IRQHandler ; ADC3
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_IRQHandler ; TIM6
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_2_IRQHandler [WEAK]
EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK]
EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT USBWakeUp_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT ADC3_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_2_IRQHandler
USB_HP_CAN1_TX_IRQHandler
USB_LP_CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
USBWakeUp_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
ADC3_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 13,352
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_ld_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_ld_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x Low Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD 0 ; Reserved
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
AAAAyl0n/Lambda0
| 15,346
|
2.Firmware/stm32-SimpleFOC_keil/startup/startup_stm32f10x_hd_vl.s
|
;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f10x_hd_vl.s
;* Author : MCD Application Team
;* Version : V3.5.0
;* Date : 11-March-2011
;* Description : STM32F10x High Density Value Line Devices vector table
;* for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Configure the clock system and also configure the external
;* SRAM mounted on STM32100E-EVAL board to be used as data
;* memory (optional, to be enabled by user)
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD TAMPER_IRQHandler ; Tamper
DCD RTC_IRQHandler ; RTC
DCD FLASH_IRQHandler ; Flash
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line 0
DCD EXTI1_IRQHandler ; EXTI Line 1
DCD EXTI2_IRQHandler ; EXTI Line 2
DCD EXTI3_IRQHandler ; EXTI Line 3
DCD EXTI4_IRQHandler ; EXTI Line 4
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
DCD ADC1_IRQHandler ; ADC1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line
DCD CEC_IRQHandler ; HDMI-CEC
DCD TIM12_IRQHandler ; TIM12
DCD TIM13_IRQHandler ; TIM13
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC underrun
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
DCD DMA2_Channel5_IRQHandler ; DMA2 Channel5
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMPER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_IRQHandler [WEAK]
EXPORT DMA1_Channel3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_IRQHandler [WEAK]
EXPORT DMA1_Channel5_IRQHandler [WEAK]
EXPORT DMA1_Channel6_IRQHandler [WEAK]
EXPORT DMA1_Channel7_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTCAlarm_IRQHandler [WEAK]
EXPORT CEC_IRQHandler [WEAK]
EXPORT TIM12_IRQHandler [WEAK]
EXPORT TIM13_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Channel1_IRQHandler [WEAK]
EXPORT DMA2_Channel2_IRQHandler [WEAK]
EXPORT DMA2_Channel3_IRQHandler [WEAK]
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
EXPORT DMA2_Channel5_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMPER_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_IRQHandler
DMA1_Channel3_IRQHandler
DMA1_Channel4_IRQHandler
DMA1_Channel5_IRQHandler
DMA1_Channel6_IRQHandler
DMA1_Channel7_IRQHandler
ADC1_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM15_IRQHandler
TIM1_UP_TIM16_IRQHandler
TIM1_TRG_COM_TIM17_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTCAlarm_IRQHandler
CEC_IRQHandler
TIM12_IRQHandler
TIM13_IRQHandler
TIM14_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Channel1_IRQHandler
DMA2_Channel2_IRQHandler
DMA2_Channel3_IRQHandler
DMA2_Channel4_5_IRQHandler
DMA2_Channel5_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
|
aanon4/HomeKit
| 18,726
|
src/nrf52/gcc_startup_nrf52.S
|
/*
Copyright (c) 2015, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
NOTE: Template files (including this one) are application specific and therefore
expected to be copied into the application project folder prior to its use!
*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 8192
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 8192
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .Vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long POWER_CLOCK_IRQHandler
.long RADIO_IRQHandler
.long UARTE0_UART0_IRQHandler
.long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
.long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.long NFCT_IRQHandler
.long GPIOTE_IRQHandler
.long SAADC_IRQHandler
.long TIMER0_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
.long RTC0_IRQHandler
.long TEMP_IRQHandler
.long RNG_IRQHandler
.long ECB_IRQHandler
.long CCM_AAR_IRQHandler
.long WDT_IRQHandler
.long RTC1_IRQHandler
.long QDEC_IRQHandler
.long COMP_LPCOMP_IRQHandler
.long SWI0_EGU0_IRQHandler
.long SWI1_EGU1_IRQHandler
.long SWI2_EGU2_IRQHandler
.long SWI3_EGU3_IRQHandler
.long SWI4_EGU4_IRQHandler
.long SWI5_EGU5_IRQHandler
.long TIMER3_IRQHandler
.long TIMER4_IRQHandler
.long PWM0_IRQHandler
.long PDM_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long MWU_IRQHandler
.long PWM1_IRQHandler
.long PWM2_IRQHandler
.long SPIM2_SPIS2_SPI2_IRQHandler
.long RTC2_IRQHandler
.long I2S_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.size __Vectors, . - __Vectors
/* Reset Handler */
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.fnstart
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
LDR R0, =SystemInit
BLX R0
LDR R0, =_start
BX R0
.pool
.cantunwind
.fnend
.size Reset_Handler,.-Reset_Handler
.section ".text"
/* Dummy Exception Handlers (infinite loops which can be modified) */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak MemoryManagement_Handler
.type MemoryManagement_Handler, %function
MemoryManagement_Handler:
B .
.size MemoryManagement_Handler, . - MemoryManagement_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
B .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
B .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ POWER_CLOCK_IRQHandler
IRQ RADIO_IRQHandler
IRQ UARTE0_UART0_IRQHandler
IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
IRQ NFCT_IRQHandler
IRQ GPIOTE_IRQHandler
IRQ SAADC_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ RTC0_IRQHandler
IRQ TEMP_IRQHandler
IRQ RNG_IRQHandler
IRQ ECB_IRQHandler
IRQ CCM_AAR_IRQHandler
IRQ WDT_IRQHandler
IRQ RTC1_IRQHandler
IRQ QDEC_IRQHandler
IRQ COMP_LPCOMP_IRQHandler
IRQ SWI0_EGU0_IRQHandler
IRQ SWI1_EGU1_IRQHandler
IRQ SWI2_EGU2_IRQHandler
IRQ SWI3_EGU3_IRQHandler
IRQ SWI4_EGU4_IRQHandler
IRQ SWI5_EGU5_IRQHandler
IRQ TIMER3_IRQHandler
IRQ TIMER4_IRQHandler
IRQ PWM0_IRQHandler
IRQ PDM_IRQHandler
IRQ MWU_IRQHandler
IRQ PWM1_IRQHandler
IRQ PWM2_IRQHandler
IRQ SPIM2_SPIS2_SPI2_IRQHandler
IRQ RTC2_IRQHandler
IRQ I2S_IRQHandler
.end
|
aanon4/HomeKit
| 7,661
|
src/nrf51/gcc_startup_nrf51.S
|
/*
Copyright (c) 2015, Nordic Semiconductor ASA
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
* Neither the name of Nordic Semiconductor ASA nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
NOTE: Template files (including this one) are application specific and therefore
expected to be copied into the application project folder prior to its use!
*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 2048
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 2048
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .Vectors
.align 2
.globl __Vectors
__Vectors:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long POWER_CLOCK_IRQHandler
.long RADIO_IRQHandler
.long UART0_IRQHandler
.long SPI0_TWI0_IRQHandler
.long SPI1_TWI1_IRQHandler
.long 0 /*Reserved */
.long GPIOTE_IRQHandler
.long ADC_IRQHandler
.long TIMER0_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
.long RTC0_IRQHandler
.long TEMP_IRQHandler
.long RNG_IRQHandler
.long ECB_IRQHandler
.long CCM_AAR_IRQHandler
.long WDT_IRQHandler
.long RTC1_IRQHandler
.long QDEC_IRQHandler
.long LPCOMP_IRQHandler
.long SWI0_IRQHandler
.long SWI1_IRQHandler
.long SWI2_IRQHandler
.long SWI3_IRQHandler
.long SWI4_IRQHandler
.long SWI5_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.size __Vectors, . - __Vectors
/* Reset Handler */
.equ NRF_POWER_RAMON_ADDRESS, 0x40000524
.equ NRF_POWER_RAMONB_ADDRESS, 0x40000554
.equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3
.text
.thumb
.thumb_func
.align 1
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.fnstart
/* Make sure ALL RAM banks are powered on */
MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
LDR R0, =NRF_POWER_RAMON_ADDRESS
LDR R2, [R0]
ORRS R2, R1
STR R2, [R0]
LDR R0, =NRF_POWER_RAMONB_ADDRESS
LDR R2, [R0]
ORRS R2, R1
STR R2, [R0]
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC0
.LC1:
subs r3, 4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt .LC1
.LC0:
LDR R0, =SystemInit
BLX R0
LDR R0, =_start
BX R0
.pool
.cantunwind
.fnend
.size Reset_Handler,.-Reset_Handler
.section ".text"
/* Dummy Exception Handlers (infinite loops which can be modified) */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ POWER_CLOCK_IRQHandler
IRQ RADIO_IRQHandler
IRQ UART0_IRQHandler
IRQ SPI0_TWI0_IRQHandler
IRQ SPI1_TWI1_IRQHandler
IRQ GPIOTE_IRQHandler
IRQ ADC_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ RTC0_IRQHandler
IRQ TEMP_IRQHandler
IRQ RNG_IRQHandler
IRQ ECB_IRQHandler
IRQ CCM_AAR_IRQHandler
IRQ WDT_IRQHandler
IRQ RTC1_IRQHandler
IRQ QDEC_IRQHandler
IRQ LPCOMP_IRQHandler
IRQ SWI0_IRQHandler
IRQ SWI1_IRQHandler
IRQ SWI2_IRQHandler
IRQ SWI3_IRQHandler
IRQ SWI4_IRQHandler
IRQ SWI5_IRQHandler
.end
|
aanon4/HomeKit
| 16,139
|
src/homekit/crypto/uNaCl/mul.S
|
.align 2
.global multiply256x256_asm
.type multiply256x256_asm, %function
multiply256x256_asm:
push {r4-r7,lr}
mov r3, r8
mov r4, r9
mov r5, r10
mov r6, r11
push {r0-r6}
mov r12, r0
mov r10, r2
mov r11, r1
mov r0,r2
ldm r0!, {r4,r5,r6,r7}
ldm r1!, {r2,r3,r6,r7}
push {r0,r1}
/////////BEGIN LOW PART //////////////////////
/////////MUL128/////////////
//MUL64
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
//////////////////////////
mov r4, r12
stm r4!, {r0,r1}
push {r4}
push {r0,r1}
mov r1, r10
mov r10, r2
ldm r1, {r0, r1, r4, r5}
mov r2, r4
mov r7, r5
sub r2, r0
sbc r7, r1
sbc r6, r6
eor r2, r6
eor r7, r6
sub r2, r6
sbc r7, r6
push {r2, r7}
mov r2, r11
mov r11, r3
ldm r2, {r0, r1, r2, r3}
sub r0, r2
sbc r1, r3
sbc r7, r7
eor r0, r7
eor r1, r7
sub r0, r7
sbc r1, r7
eor r7, r6
mov r12, r7
push {r0, r1}
//MUL64
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
mov r4, r10
mov r5, r11
eor r6, r6
add r0, r4
adc r1, r5
adc r2, r6
adc r3, r6
mov r10, r2
mov r11, r3
pop {r2-r5}
push {r0, r1}
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
pop {r4, r5}
mov r6, r12
mov r7, r12
eor r0, r6
eor r1, r6
eor r2, r6
eor r3, r6
asr r6, r6, #1
adc r0, r4
adc r1, r5
adc r4, r2
adc r5, r3
eor r2, r2
adc r6,r2
adc r7,r2
pop {r2, r3}
mov r8, r2
mov r9, r3
add r2, r0
adc r3, r1
mov r0, r10
mov r1, r11
adc r4, r0
adc r5, r1
adc r6, r0
adc r7, r1
////////END LOW PART/////////////////////
pop {r0}
stm r0!, {r2,r3}
pop {r1,r2}
push {r0}
push {r4-r7}
mov r10, r1
mov r11, r2
ldm r1!, {r4, r5}
ldm r2, {r2, r3}
/////////BEGIN HIGH PART////////////////
/////////MUL128/////////////
//MUL64
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
push {r0,r1}
mov r1, r10
mov r10, r2
ldm r1, {r0, r1, r4, r5}
mov r2, r4
mov r7, r5
sub r2, r0
sbc r7, r1
sbc r6, r6
eor r2, r6
eor r7, r6
sub r2, r6
sbc r7, r6
push {r2, r7}
mov r2, r11
mov r11, r3
ldm r2, {r0, r1, r2, r3}
sub r0, r2
sbc r1, r3
sbc r7, r7
eor r0, r7
eor r1, r7
sub r0, r7
sbc r1, r7
eor r7, r6
mov r12, r7
push {r0, r1}
//MUL64
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
mov r4, r10
mov r5, r11
eor r6, r6
add r0, r4
adc r1, r5
adc r2, r6
adc r3, r6
mov r10, r2
mov r11, r3
pop {r2-r5}
push {r0, r1}
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
pop {r4, r5}
mov r6, r12
mov r7, r12
eor r0, r6
eor r1, r6
eor r2, r6
eor r3, r6
asr r6, r6, #1
adc r0, r4
adc r1, r5
adc r4, r2
adc r5, r3
eor r2, r2
adc r6,r2 //0,1
adc r7,r2
pop {r2, r3}
mov r8, r2
mov r9, r3
add r2, r0
adc r3, r1
mov r0, r10
mov r1, r11
adc r4, r0
adc r5, r1
adc r6, r0
adc r7, r1
////////END HIGH PART/////////////////////
mov r0, r8
mov r1, r9
mov r8, r6
mov r9, r7
pop {r6, r7}
add r0, r6
adc r1, r7
pop {r6, r7}
adc r2, r6
adc r3, r7
pop {r7}
stm r7!, {r0-r3}
mov r10, r7
eor r0,r0
mov r6, r8
mov r7, r9
adc r4, r0
adc r5, r0
adc r6, r0
adc r7, r0
pop {r0,r1,r2}
mov r12, r2
push {r0, r4-r7}
ldm r1, {r0-r7}
sub r0, r4
sbc r1, r5
sbc r2, r6
sbc r3, r7
eor r4, r4
sbc r4, r4
eor r0, r4
eor r1, r4
eor r2, r4
eor r3, r4
sub r0, r4
sbc r1, r4
sbc r2, r4
sbc r3, r4
mov r6, r12
mov r12, r4 //carry
mov r5, r10
stm r5!, {r0-r3}
mov r11, r5
mov r8, r0
mov r9, r1
ldm r6, {r0-r7}
sub r4, r0
sbc r5, r1
sbc r6, r2
sbc r7, r3
eor r0, r0
sbc r0, r0
eor r4, r0
eor r5, r0
eor r6, r0
eor r7, r0
sub r4, r0
sbc r5, r0
sbc r6, r0
sbc r7, r0
mov r1, r12
eor r0, r1
mov r1, r11
stm r1!, {r4-r7}
push {r0}
mov r2, r8
mov r3, r9
/////////BEGIN MIDDLE PART////////////////
/////////MUL128/////////////
//MUL64
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
push {r0,r1}
mov r1, r10
mov r10, r2
ldm r1, {r0, r1, r4, r5}
mov r2, r4
mov r7, r5
sub r2, r0
sbc r7, r1
sbc r6, r6
eor r2, r6
eor r7, r6
sub r2, r6
sbc r7, r6
push {r2, r7}
mov r2, r11
mov r11, r3
ldm r2, {r0, r1, r2, r3}
sub r0, r2
sbc r1, r3
sbc r7, r7
eor r0, r7
eor r1, r7
sub r0, r7
sbc r1, r7
eor r7, r6
mov r12, r7
push {r0, r1}
//MUL64
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
mov r4, r10
mov r5, r11
eor r6, r6
add r0, r4
adc r1, r5
adc r2, r6
adc r3, r6
mov r10, r2
mov r11, r3
pop {r2-r5}
push {r0, r1}
mov r6, r5
mov r1, r2
sub r5, r4
sbc r0, r0
eor r5, r0
sub r5, r0
sub r1, r3
sbc r7, r7
eor r1, r7
sub r1, r7
eor r7, r0
mov r9, r1
mov r8, r5
lsr r1,r4,#16
uxth r4,r4
mov r0,r4
uxth r5,r2
lsr r2,#16
mul r0,r5//00
mul r5,r1//10
mul r4,r2//01
mul r1,r2//11
lsl r2,r4,#16
lsr r4,r4,#16
add r0,r2
adc r1,r4
lsl r2,r5,#16
lsr r4,r5,#16
add r0,r2
adc r1,r4
lsr r4, r6,#16
uxth r6, r6
uxth r5, r3
lsr r3, r3, #16
mov r2, r6
mul r2, r5
mul r5, r4
mul r6, r3
mul r3, r4
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
lsl r4,r6,#16
lsr r5,r6,#16
add r2,r4
adc r3,r5
eor r6, r6
add r2, r1
adc r3, r6
mov r1, r9
mov r5, r8
mov r8, r0
lsr r0, r1,#16
uxth r1,r1
mov r4,r1
lsr r6,r5,#16
uxth r5,r5
mul r1,r5
mul r4,r6
mul r5,r0
mul r0,r6
lsl r6,r4,#16
lsr r4,#16
add r1,r6
adc r0,r4
lsl r6,r5,#16
lsr r5,#16
add r1,r6
adc r0,r5
eor r1,r7
eor r0,r7
eor r4, r4
asr r7, r7, #1
adc r1, r2
adc r2, r0
adc r7, r4
mov r0, r8
add r1, r0
adc r2, r3
adc r3, r7
pop {r4, r5}
mov r6, r12
mov r7, r12
eor r0, r6
eor r1, r6
eor r2, r6
eor r3, r6
asr r6, r6, #1
adc r0, r4
adc r1, r5
adc r4, r2
adc r5, r3
eor r2, r2
adc r6,r2 //0,1
adc r7,r2
pop {r2, r3}
mov r8, r2
mov r9, r3
add r2, r0
adc r3, r1
mov r0, r10
mov r1, r11
adc r4, r0
adc r5, r1
adc r6, r0
adc r7, r1
//////////END MIDDLE PART////////////////
pop {r0,r1} //r0,r1
mov r12, r0 //negative
eor r2, r0
eor r3, r0
eor r4, r0
eor r5, r0
eor r6, r0
eor r7, r0
push {r4-r7}
ldm r1!, {r4-r7}
mov r11, r1 //reference
mov r1, r9
eor r1, r0
mov r10, r4
mov r4, r8
asr r0, #1
eor r0, r4
mov r4, r10
adc r0, r4
adc r1, r5
adc r2, r6
adc r3, r7
eor r4, r4
adc r4, r4
mov r10, r4 //carry
mov r4, r11
ldm r4, {r4-r7}
add r0, r4
adc r1, r5
adc r2, r6
adc r3, r7
mov r9, r4
mov r4, r11
stm r4!, {r0-r3}
mov r11, r4
pop {r0-r3}
mov r4, r9
adc r4, r0
adc r5, r1
adc r6, r2
adc r7, r3
mov r1, #0
adc r1, r1
mov r0, r10
mov r10, r1 //carry
asr r0, #1
pop {r0-r3}
adc r4, r0
adc r5, r1
adc r6, r2
adc r7, r3
mov r8, r0
mov r0, r11
stm r0!, {r4-r7}
mov r11, r0
mov r0, r8
mov r6, r12
mov r5, r10
eor r4, r4
adc r5, r6
adc r6, r4
add r0, r5
adc r1, r6
adc r2, r6
adc r3, r6
mov r7, r11
stm r7!, {r0-r3}
pop {r3-r6}
mov r8, r3
mov r9, r4
mov r10, r5
mov r11, r6
pop {r4-r7,pc}
bx lr
.size multiply256x256_asm, .-multiply256x256_asm
|
aanon4/HomeKit
| 11,682
|
src/homekit/crypto/uNaCl/sqr.S
|
.align 2
.global square256_asm
.type square256_asm, %function
square256_asm:
push {r4-r7,lr}
mov r2, r8
mov r3, r9
mov r4, r10
mov r5, r11
push {r0-r5}
mov r12, r0
mov r4, r1
ldm r4!, {r0-r3}
push {r4}
/////////BEGIN LOW PART //////////////////////
///SQR 128, in r0-r3
mov r8, r2
mov r9, r3
eor r4, r4
sub r2, r0
sbc r3, r1
sbc r4, r4
eor r2, r4
eor r3, r4
sub r2, r4
sbc r3, r4
mov r10, r2
mov r11, r3
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r7, r7
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r7, r7
add r1, r0
adc r2, r3
adc r7, r3
mov r3, r12
stm r3!, {r0-r1}
push {r3}
mov r12, r0
mov r0, r8
mov r8, r1
mov r1, r9
mov r9, r2
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r4, r4
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r4, r4
add r1, r0
adc r2, r3
adc r3, r4
eor r4, r4
mov r6, r9
add r0, r6
adc r7, r1
adc r2, r4
adc r3, r4
mov r1, r11
mov r11, r0
mov r0, r10
mov r9, r2
mov r10,r3
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r4, r4
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r4, r4
add r1, r0
adc r2, r3
adc r3, r4
mov r6, r11
mov r4, r11
mov r5, r7
sub r6, r0
sbc r7, r1
sbc r4, r2
sbc r5, r3
eor r1, r1
sbc r1, r1
mov r2, r12
mov r3, r8
add r2, r6
adc r3, r7
mov r6, r9
mov r7, r10
adc r4, r6
adc r5, r7
adc r6, r1
adc r7, r1
//results r12, r8, r2-r7
/////////END LOW PART ////////////////////////
pop {r0,r1}
stm r0!, {r2, r3}
push {r0, r4-r7}
ldm r1, {r0-r3}
/////////BEGIN HIGH PART //////////////////////
///SQR 128, in r0-r3
mov r8, r2
mov r9, r3
eor r4, r4
sub r2, r0
sbc r3, r1
sbc r4, r4
eor r2, r4
eor r3, r4
sub r2, r4
sbc r3, r4
mov r10, r2
mov r11, r3
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r7, r7
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r7, r7
add r1, r0
adc r2, r3
adc r7, r3
mov r12, r0
mov r0, r8
mov r8, r1
mov r1, r9
mov r9, r2
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r4, r4
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r4, r4
add r1, r0
adc r2, r3
adc r3, r4
eor r4, r4
mov r6, r9
add r0, r6
adc r7, r1
adc r2, r4
adc r3, r4
mov r1, r11
mov r11, r0
mov r0, r10
mov r9, r2
mov r10,r3
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r4, r4
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r4, r4
add r1, r0
adc r2, r3
adc r3, r4
mov r6, r11
mov r4, r11
mov r5, r7
sub r6, r0
sbc r7, r1
sbc r4, r2
sbc r5, r3
eor r1, r1
sbc r1, r1
mov r2, r12
mov r3, r8
add r2, r6
adc r3, r7
mov r6, r9
mov r7, r10
adc r4, r6
adc r5, r7
adc r6, r1
adc r7, r1
//results r12, r8, r2-r7
/////////END HIGH PART ////////////////////////
mov r0, r12
mov r1, r8
mov r8, r4
mov r9, r5
mov r10, r6
mov r11, r7
pop {r4}
mov r12, r4//str
pop {r4-r7}
add r0, r4
adc r1, r5
adc r2, r6
adc r3, r7
mov r4, r12
stm r4!, {r0-r3}//low part
mov r4, r8
mov r5, r9
mov r6, r10
mov r7, r11
eor r0, r0
adc r4, r0
adc r5, r0
adc r6, r0
adc r7, r0
pop {r0, r1} //r0->out, r1, in
push {r0,r4-r7}
ldm r1, {r0-r7}
sub r0, r4
sbc r1, r5
sbc r2, r6
sbc r3, r7
sbc r4, r4
eor r0, r4
eor r1, r4
eor r2, r4
eor r3, r4
sub r0, r4
sbc r1, r4
sbc r2, r4
sbc r3, r4
//////////BEGIN MIDDLE PART////////////////
///SQR 128, in r0-r3
mov r8, r2
mov r9, r3
eor r4, r4
sub r2, r0
sbc r3, r1
sbc r4, r4
eor r2, r4
eor r3, r4
sub r2, r4
sbc r3, r4
mov r10, r2
mov r11, r3
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r7, r7
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r7, r7
add r1, r0
adc r2, r3
adc r7, r3
mov r12, r0
mov r0, r8
mov r8, r1
mov r1, r9
mov r9, r2
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r4, r4
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r4, r4
add r1, r0
adc r2, r3
adc r3, r4
eor r4, r4
mov r6, r9
add r0, r6
adc r7, r1
adc r2, r4
adc r3, r4
mov r1, r11
mov r11, r0
mov r0, r10
mov r9, r2
mov r10,r3
//SQR64, in: r0, r1, out: r0-r3, used: r0-r6
mov r2, r0
eor r3, r3
sub r2, r1
sbc r3, r3
eor r2, r3
sub r2, r3
lsr r3, r0, #16
uxth r0, r0
mov r4, r0
mul r4, r3
mul r0, r0
mul r3, r3
lsr r5, r4, #16
lsl r4, #16
add r0, r4
adc r3, r5
add r0, r4
adc r3, r5
lsr r4, r1, #16
uxth r1, r1
mov r5, r1
mul r5, r4
mul r1, r1
mul r4, r4
eor r6, r6
add r1, r3
adc r4, r6
lsr r3, r5, #16
lsl r5, r5, #16
add r1, r5
adc r4, r3
add r1, r5
adc r3, r4
lsr r4, r2, #16
uxth r2, r2
mov r5, r2
mul r5, r4
mul r2, r2
mul r4, r4
lsr r6, r5, #16
lsl r5, #16
add r2, r5
adc r4, r6
add r5, r2
adc r6, r4
eor r4, r4
mov r2, r1
sub r1, r5
sbc r2, r6
sbc r4, r4
add r1, r0
adc r2, r3
adc r3, r4
mov r6, r11
mov r4, r11
mov r5, r7
sub r6, r0
sbc r7, r1
sbc r4, r2
sbc r5, r3
eor r1, r1
sbc r1, r1
mov r2, r12
mov r3, r8
add r2, r6
adc r3, r7
mov r6, r9
mov r7, r10
adc r4, r6
adc r5, r7
adc r6, r1
adc r7, r1
//results r12, r8, r2-r7
//////////END MIDDLE PART//////////////////
mvn r2, r2
mvn r3, r3
mvn r4, r4
mvn r5, r5
mvn r6, r6
mvn r7, r7
pop {r1}
push {r4-r7}
mov r4, #1
asr r4, #1
ldm r1!, {r4-r7}
mov r0, r12
mov r12, r1 ////////ref
mov r1, r8
mvn r0, r0
mvn r1, r1
adc r0, r4
adc r1, r5
adc r2, r6
adc r3, r7
eor r4, r4
adc r4, r4
mov r8, r4 //carry A --ini
mov r4, r12
ldm r4, {r4-r7}
add r0, r4
adc r1, r5
adc r2, r6
adc r3, r7
mov r9, r4
mov r4, r12
stm r4!, {r0-r3}
mov r12, r4
mov r4, r9
pop {r0-r3}
adc r4, r0
adc r5, r1
adc r6, r2
adc r7, r3
eor r0, r0
adc r0, r0
mov r9, r0 //carry B --ini
mov r0, r8
asr r0, #1 //carry A --end
pop {r0-r3}
adc r4, r0
adc r5, r1
adc r6, r2
adc r7, r3
mov r8, r0
mov r0, r12
stm r0!, {r4-r7}
mov r11, r0
mov r0, r8
eor r4, r4
mov r5, r9
adc r5, r4 //carry B --end
mvn r6, r4
add r5, r6
adc r6, r4
add r0, r5
adc r1, r6
adc r2, r6
adc r3, r6
mov r7, r11
stm r7!, {r0-r3}
pop {r3-r6}
mov r8, r3
mov r9, r4
mov r10, r5
mov r11, r6
pop {r4-r7,pc}
bx lr
.size square256_asm, .-square256_asm
|
aanon4/HomeKit
| 3,013
|
src/homekit/crypto/uNaCl/cortex_m0_reduce25519.S
|
// Implementation of a partial reduction modulo 2^255 - 38.
//
// B. Haase, Endress + Hauser Conducta GmbH & Ko. KG
// public domain.
//
// gnu assembler format.
//
// Generated and tested with C++ functions in the test subdirectory and on the target.
//
.cpu cortex-m0
.fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 2
.eabi_attribute 34, 0
.eabi_attribute 18, 4
.code 16
.file "cortex_m0_reduce25519.s"
.text
.align 2
.global fe25519_reduceTo256Bits_asm
.code 16
.thumb_func
.type fe25519_reduceTo256Bits_asm, %function
fe25519_reduceTo256Bits_asm:
push {r4,r5,r6,r7,r14}
ldr r2,[r1,#60]
lsr r3,r2,#16
uxth r2,r2
mov r7,#38
mul r2,r7
mul r3,r7
ldr r4,[r1,#28]
lsr r5,r3,#16
lsl r3,r3,#16
mov r6,#0
add r4,r2
adc r5,r6
add r4,r3
adc r5,r6
lsl r2,r4,#1
lsr r2,r2,#1
str r2,[r0,#28]
lsr r4,r4,#31
lsl r5,r5,#1
orr r4,r5
mov r2,#19
mul r2,r4
ldr r4,[r1,#0]
add r2,r4
mov r3,#0
adc r3,r6
ldr r4,[r1,#32]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r2,r4
adc r3,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
str r2,[r0,#0]
ldr r4,[r1,#4]
add r3,r4
mov r2,#0
adc r2,r6
ldr r4,[r1,#36]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r3,r4
adc r2,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r3,r4
adc r2,r5
str r3,[r0,#4]
ldr r4,[r1,#8]
add r2,r4
mov r3,#0
adc r3,r6
ldr r4,[r1,#40]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r2,r4
adc r3,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
str r2,[r0,#8]
ldr r4,[r1,#12]
add r3,r4
mov r2,#0
adc r2,r6
ldr r4,[r1,#44]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r3,r4
adc r2,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r3,r4
adc r2,r5
str r3,[r0,#12]
ldr r4,[r1,#16]
add r2,r4
mov r3,#0
adc r3,r6
ldr r4,[r1,#48]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r2,r4
adc r3,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
str r2,[r0,#16]
ldr r4,[r1,#20]
add r3,r4
mov r2,#0
adc r2,r6
ldr r4,[r1,#52]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r3,r4
adc r2,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r3,r4
adc r2,r5
str r3,[r0,#20]
ldr r4,[r1,#24]
add r2,r4
mov r3,#0
adc r3,r6
ldr r4,[r1,#56]
lsr r5,r4,#16
uxth r4,r4
mul r5,r7
mul r4,r7
add r2,r4
adc r3,r6
lsl r4,r5,#16
lsr r5,r5,#16
add r2,r4
adc r3,r5
str r2,[r0,#24]
ldr r4,[r0,#28]
add r4,r3
str r4,[r0,#28]
pop {r4,r5,r6,r7,r15}
.size fe25519_reduceTo256Bits_asm, .-fe25519_reduceTo256Bits_asm
|
aanon4/HomeKit
| 3,392
|
src/homekit/crypto/uNaCl/cortex_m0_mpy121666.S
|
// Implementation of multiplication of an fe25519 bit value with the curve constant 121666.
//
// B. Haase, Endress + Hauser Conducta GmbH & Ko. KG
// public domain.
//
// gnu assembler format.
//
// Generated and tested with C++ functions in the test subdirectory.
//
// ATTENTION:
// Not yet tested on target hardware.
.cpu cortex-m0
.fpu softvfp
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.eabi_attribute 26, 1
.eabi_attribute 30, 2
.eabi_attribute 34, 0
.eabi_attribute 18, 4
.code 16
.file "cortex_m0_reduce25519.s"
.text
.align 2
.global fe25519_mpyWith121666_asm
.code 16
.thumb_func
.type fe25519_mpyWith121666_asm, %function
fe25519_mpyWith121666_asm:
push {r4,r5,r6,r7,r14}
ldr r7,__label_for_immediate_56130
ldr r2,[r1,#28]
lsl r5,r2,#16
lsr r6,r2,#16
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r5,r2
mov r2,#0
adc r6,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r5,r2
adc r6,r3
lsl r2,r5,#1
lsr r2,r2,#1
str r2,[r0,#28]
lsr r5,r5,#31
lsl r6,r6,#1
orr r5,r6
mov r6,#19
mul r5,r6
mov r6,#0
ldr r2,[r1,#0]
lsl r3,r2,#16
lsr r4,r2,#16
add r5,r3
adc r6,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r5,r2
mov r2,#0
adc r6,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r5,r2
adc r6,r3
str r5,[r0,#0]
mov r5,#0
ldr r2,[r1,#4]
lsl r3,r2,#16
lsr r4,r2,#16
add r6,r3
adc r5,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r6,r2
mov r2,#0
adc r5,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r6,r2
adc r5,r3
str r6,[r0,#4]
mov r6,#0
ldr r2,[r1,#8]
lsl r3,r2,#16
lsr r4,r2,#16
add r5,r3
adc r6,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r5,r2
mov r2,#0
adc r6,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r5,r2
adc r6,r3
str r5,[r0,#8]
mov r5,#0
ldr r2,[r1,#12]
lsl r3,r2,#16
lsr r4,r2,#16
add r6,r3
adc r5,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r6,r2
mov r2,#0
adc r5,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r6,r2
adc r5,r3
str r6,[r0,#12]
mov r6,#0
ldr r2,[r1,#16]
lsl r3,r2,#16
lsr r4,r2,#16
add r5,r3
adc r6,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r5,r2
mov r2,#0
adc r6,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r5,r2
adc r6,r3
str r5,[r0,#16]
mov r5,#0
ldr r2,[r1,#20]
lsl r3,r2,#16
lsr r4,r2,#16
add r6,r3
adc r5,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r6,r2
mov r2,#0
adc r5,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r6,r2
adc r5,r3
str r6,[r0,#20]
mov r6,#0
ldr r2,[r1,#24]
lsl r3,r2,#16
lsr r4,r2,#16
add r5,r3
adc r6,r4
lsr r3,r2,#16
uxth r2,r2
mul r2,r7
mul r3,r7
add r5,r2
mov r2,#0
adc r6,r2
lsl r2,r3,#16
lsr r3,r3,#16
add r5,r2
adc r6,r3
str r5,[r0,#24]
mov r5,#0
ldr r2,[r0,#28]
add r6,r2
str r6,[r0,#28]
pop {r4,r5,r6,r7,r15}
.align 2
__label_for_immediate_56130:
.word 56130
.size fe25519_mpyWith121666_asm, .-fe25519_mpyWith121666_asm
|
aap/b
| 14,805
|
pdp10_its/ba10.s
|
RELOCATABLE
.INSRT B;B DEF
%"main":
.+1
OP Y,5
OP Y,23
OP2 S,36
OP2 X,%"getarg"
OP N2
OP2 A,23
OP2 X,%"args"
OP2 C,0
OP N3
OP2 IVA,22
OP2 X,%"sixch"
OP N2
OP2 A,23
OP N3
OP B1
OP2 C,0
OP B4
OP2 F,L1
L2:
OP2 S,36
OP2 X,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL2
-144542315044
-170443300000
LL2:
OP N3
OP2 IX,%"exit"
OP N2
OP2 C,1
OP N3
L1:
OP2 IVX,%"fin"
OP2 X,%"openr"
OP N2
OP2 C,12
OP2 A,22
OP2 X,%"sixch"
OP N2
OP2 VX,.+3
OP2 T,LL3
-134000000000
LL3:
OP N3
OP N3
OP B1
OP2 C,0
OP B7
OP2 F,L3
OP2 IX,LL1+0
OP N6
L3:
OP2 IVX,%"fout"
OP2 X,%"openw"
OP N2
OP2 C,13
OP2 A,22
OP2 X,%"sixch"
OP N2
OP2 VX,.+3
OP2 T,LL4
-64000000000
LL4:
OP N3
OP N3
OP B1
OP2 C,0
OP B7
OP2 F,L4
OP2 IX,LL1+0
OP N6
L4:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL5
-265646330172
-371267636550
-353540000000
LL5:
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL6
272231651644
-256767542174
202110543024
0
LL6:
OP N3
L5:
OP2 IVA,2
OP2 X,%"getchar"
OP N1
OP B1
OP2 C,0
OP B11
OP2 F,L6
OP2 IA,2
OP2 Z,L7
L10=114
L11:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL7
-316642042754
0
LL7:
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L13=161
L14:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL10
-316642041266
-103540000000
LL10:
OP2 X,%"getw"
OP N1
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L15=147
L16:
OP2 IX,%"readsym"
OP N2
OP2 A,5
OP N3
OP2 IX,%"lchar"
OP N2
OP2 A,5
OP2 X,%"namsiz"
OP2 C,0
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL11
51124222746
211641200000
LL11:
OP2 A,5
OP N3
OP2 IX,LL1+1
OP N6
L17=145
L20:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL12
45345330424
0
LL12:
OP N3
OP2 IVX,%"ilbl"
OP2 VX,%"loc"
OP U7
OP B1
OP2 IX,LL1+1
OP N6
L21=166
L22:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL13
45345330424
0
LL13:
OP N3
OP2 IX,LL1+1
OP N6
L23=154
L24:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL14
46304567424
0
LL14:
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L25=157
L26:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL15
45135705000
LL15:
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L27=162
L30:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL16
45347527126
227361200000
LL16:
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L31=160
L32:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL17
-315473210214
50000000000
LL17:
OP2 X,%"ilbl"
OP N3
OP2 IX,LL1+1
OP N6
L33=153
L34:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL20
46372031100
-256472152266
-103540000000
LL20:
OP2 X,%"getw"
OP N1
OP2 C,1
OP B14
OP N3
OP2 IX,LL1+1
OP N6
L35=164
L36:
L37=146
L40:
L41=172
L42:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL21
46372031100
227065446112
-103540000000
LL21:
OP2 A,2
OP2 C,40
OP B15
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L43=171
L44:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL22
46372020262
261135705000
LL22:
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L45=163
L46:
OP2 IVX,%"stklvl"
OP2 X,%"getw"
OP N1
OP B1
OP2 IVX,%"drop"
OP2 C,1
OP B1
OP2 IVX,%"blockp"
OP2 X,%"space"
OP B1
OP2 IVX,%"sp"
OP2 X,%"stack"
OP B1
OP2 IVX,%"ap"
OP2 X,%"ast"
OP B1
OP2 IX,LL1+1
OP N6
L47=170
L50:
OP2 IX,%"readsym"
OP N2
OP2 VA,20
OP2 X,%"blockp"
OP B1
OP N3
OP2 IX,%"lchar"
OP N2
OP2 A,20
OP2 X,%"namsiz"
OP2 C,0
OP N3
OP2 IVX,%"blockp"
OP2 C,10
OP B114
OP2 IVX,%"sp"
OP U7
OP2 X,%"block"
OP N2
OP2 C,1
OP2 A,2
OP2 A,20
OP N3
OP B1
OP2 IX,LL1+1
OP N6
L51=141
L52:
L53=143
L54:
L55=151
L56:
OP2 IVX,%"sp"
OP U7
OP2 X,%"block"
OP N2
OP2 C,1
OP2 A,2
OP2 X,%"getw"
OP N1
OP N3
OP B1
OP2 IX,LL1+1
OP N6
L57=74
L60:
OP2 IVX,%"sp"
OP U7
OP2 VA,20
OP2 X,%"block"
OP N2
OP2 C,1
OP2 C,163
OP2 C,0
OP N3
OP B1
OP B1
OP2 IVA,3
OP2 VA,4
OP2 C,0
OP B1
OP B1
L61:
OP2 IVA,2
OP2 X,%"getchar"
OP N1
OP B1
OP2 C,76
OP B5
OP2 F,L62
OP2 IA,2
OP2 C,157
OP B4
OP2 F,L63
OP2 IVA,2
OP2 X,%"getw"
OP N1
OP B1
OP2 IVA,3
OP2 C,7
OP B113
OP2 IVA,3
OP2 A,2
OP B102
OP2 IVA,4
OP U5
OP2 C,5
OP B4
OP2 F,L64
OP2 IVX,%"blockp"
OP U7
OP2 A,3
OP2 C,1
OP B13
OP B1
OP2 IVA,3
OP2 VA,4
OP2 C,0
OP B1
OP B1
L64:
L63:
OP2 T,L61
L62:
OP2 IVA,3
OP2 C,5
OP2 A,4
OP B15
OP2 C,7
OP B17
OP B113
OP2 IVX,%"blockp"
OP U7
OP2 A,3
OP2 C,1
OP B13
OP B1
OP2 IA,20
OP2 C,1
OP B14
OP2 X,%"blockp"
OP2 A,20
OP B15
OP2 C,2
OP B15
OP B1
OP2 IX,LL1+1
OP N6
L65=142
L66:
L67=165
L70:
OP2 IX,%"build"
OP N2
OP2 A,2
OP2 X,%"getw"
OP N1
OP N3
OP2 IX,LL1+1
OP N6
L71=156
L72:
OP2 IVA,3
OP2 X,%"getw"
OP N1
OP B1
OP2 IA,3
OP2 Z,L73
L74=1
L75:
OP2 IX,%"sp"
OP2 C,-1
OP B14
OP2 X,%"block"
OP N2
OP2 C,2
OP2 C,12051
OP2 X,%"sp"
OP2 C,-1
OP N4
OP2 C,0
OP N3
OP B1
OP2 IX,LL1+1
OP N6
L76=2
L77:
OP2 IVX,%"ap"
OP U7
OP2 X,%"sp"
OP B1
OP2 IX,LL1+1
OP N6
L100=3
L101:
OP2 IVA,21
OP2 X,%"sp"
OP B1
OP2 IVX,%"sp"
OP2 VA,3
OP2 VX,%"ap"
OP U6
OP U3
OP B1
OP B1
OP2 IVA,20
OP2 X,%"block"
OP N2
OP2 C,2
OP2 C,12051
OP2 VX,%"sp"
OP U6
OP U3
OP2 A,21
OP2 A,3
OP B15
OP N3
OP B1
L102:
OP2 IA,3
OP2 A,21
OP B7
OP2 F,L103
OP2 IVX,%"blockp"
OP U7
OP2 VA,3
OP U7
OP U3
OP B1
OP2 T,L102
L103:
OP2 IVX,%"sp"
OP U7
OP2 A,20
OP B1
OP2 IX,LL1+1
OP N6
L104=4
L105:
OP2 IX,%"build"
OP N2
OP2 C,26735
OP N3
OP2 IX,LL1+1
OP N6
L106=6
L107:
L110=7
L111:
L112=11
L113:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL23
46372020234
227361200000
LL23:
OP2 A,3
OP N3
OP2 IX,LL1+1
OP N6
OP2 T,.+20
L73:
7
L74
L75
L76
L77
L100
L101
L104
L105
L106
L107
L110
L111
L112
L113
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL24
-106773210400
LL24:
OP2 A,3
OP N3
OP2 IX,LL1+1
OP N6
L114=77
L115:
OP2 IVA,21
OP2 VX,%"sp"
OP U6
OP U3
OP B1
OP2 IVA,20
OP2 VX,%"sp"
OP U6
OP U3
OP B1
OP2 IVA,3
OP2 VX,%"sp"
OP U6
OP U3
OP B1
OP2 IVX,%"sp"
OP U7
OP2 X,%"block"
OP N2
OP2 C,4
OP2 A,2
OP2 X,%"getw"
OP N1
OP2 A,3
OP2 A,20
OP2 A,21
OP N3
OP B1
OP2 IX,LL1+1
OP N6
L116=123
L117:
OP2 IVX,%"setstk"
OP2 C,1
OP B1
OP2 IX,LL1+1
OP N6
L120=105
L121:
L122:
OP2 IX,%"sp"
OP2 X,%"stack"
OP B11
OP2 F,L123
OP2 IX,%"cexpr"
OP N2
OP2 VX,%"sp"
OP U6
OP U3
OP2 C,0
OP N3
OP2 IVX,%"drop"
OP2 C,1
OP B1
OP2 T,L122
L123:
OP2 IX,LL1+1
OP N6
L124=12
L125:
OP2 IX,LL1+1
OP N6
OP2 T,.+70
L7:
33
L10
L11
L13
L14
L15
L16
L17
L20
L21
L22
L23
L24
L25
L26
L27
L30
L31
L32
L33
L34
L35
L36
L37
L40
L41
L42
L43
L44
L45
L46
L47
L50
L51
L52
L53
L54
L55
L56
L57
L60
L65
L66
L67
L70
L71
L72
L114
L115
L116
L117
L120
L121
L124
L125
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL25
44236567326
351004567424
0
LL25:
OP2 A,2
OP N3
L12:
OP2 T,L5
L6:
OP2 S,36
OP2 X,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL26
-351427373000
LL26:
OP N3
OP N11
LL1:
L2
L12
%"build":
.+1
OP2 S,6
OP2 A,2
OP2 C,26735
OP B4
OP2 F,L126
OP2 IX,%"build"
OP N2
OP2 C,142
OP2 C,14
OP N3
OP2 IVA,2
OP2 C,165
OP B1
OP2 IVA,3
OP2 C,3
OP B1
L126:
OP2 IA,2
OP2 Z,L127
L130=165
L131:
OP2 IVA,4
OP2 VX,%"sp"
OP U6
OP U3
OP B1
OP2 IA,3
OP2 Z,L132
L133=1
L134:
OP2 IA,4
OP2 C,0
OP N4
OP2 C,165
OP B4
OP2 A,4
OP2 C,1
OP N4
OP2 C,3
OP B4
OP B3
OP2 F,L135
OP2 IVX,%"sp"
OP U7
OP2 A,4
OP2 C,2
OP N4
OP B1
OP N11
L135:
OP2 IX,LL27+0
OP N6
L137=3
L140:
OP2 IA,4
OP2 C,0
OP N4
OP2 C,165
OP B4
OP2 A,4
OP2 C,1
OP N4
OP2 C,1
OP B4
OP B3
OP2 F,L141
OP2 IVX,%"sp"
OP U7
OP2 A,4
OP2 C,2
OP N4
OP B1
OP N11
L141:
OP2 IX,LL27+0
OP N6
OP2 T,.+6
L132:
2
L133
L134
L137
L140
L136:
OP2 S,6
OP2 VX,%"sp"
OP U7
OP2 X,%"block"
OP N2
OP2 C,2
OP2 A,2
OP2 A,3
OP2 A,4
OP N3
OP B1
OP N11
L142=142
L143:
OP2 IVX,%"sp"
OP U6
OP2 C,-1
OP B14
OP2 X,%"block"
OP N2
OP2 C,3
OP2 A,2
OP2 A,3
OP2 X,%"sp"
OP2 C,-1
OP N4
OP2 X,%"sp"
OP U3
OP N3
OP B1
OP N11
OP2 T,.+6
L127:
2
L130
L131
L142
L143
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL30
-164242611470
201134300000
LL30:
OP2 A,2
OP N3
OP N11
LL27:
L136
%"leaf":
.+1
OP2 S,4
OP2 X,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL32
46372031100
0
LL32:
OP N3
OP2 IX,%"drop"
OP2 F,L144
OP2 IX,%"putchar"
OP N2
OP2 C,111
OP N3
L144:
OP2 IA,2
OP2 F,L145
OP2 IX,%"putchar"
OP N2
OP2 C,126
OP N3
L145:
OP2 IX,%"putchar"
OP N2
OP2 A,3
OP2 C,40
OP B15
OP N3
OP2 IVX,%"drop"
OP2 C,0
OP B1
OP N11
LL31:
%"cexpr":
.+1
OP2 S,7
OP2 X,%"setstk"
OP2 F,L146
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL34
46372031100
-262473210354
0
LL34:
OP2 X,%"stklvl"
OP N3
OP2 IVX,%"setstk"
OP2 VX,%"drop"
OP2 C,0
OP B1
OP B1
L146:
OP2 IVA,4
OP2 A,2
OP2 C,1
OP N4
OP B1
OP2 IA,2
OP U3
OP2 Z,L147
L150=143
L151:
OP2 IA,3
OP2 F,L152
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL35
-130462315062
-170473711424
50000000000
LL35:
OP N3
L152:
OP2 IX,%"leaf"
OP N2
OP2 A,3
OP2 C,143
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL36
261135705000
LL36:
OP2 A,4
OP N3
OP N11
L153=141
L154:
OP2 IX,%"leaf"
OP N2
OP2 A,3
OP2 C,141
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL37
261135705000
LL37:
OP2 A,4
OP N3
OP N11
L155=151
L156:
OP2 IX,%"leaf"
OP N2
OP2 A,3
OP2 C,170
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL40
262311422736
255135705000
LL40:
OP2 X,%"ilbl"
OP2 A,4
OP N3
OP N11
L157=170
L160:
OP2 IX,%"leaf"
OP N2
OP2 A,3
OP2 C,170
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL41
261124222746
210240000000
LL41:
OP2 A,4
OP N3
OP N11
L161=163
L162:
OP2 IA,3
OP2 F,L163
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL42
-130462315062
-170473711424
50000000000
LL42:
OP N3
L163:
OP2 IX,%"leaf"
OP N2
OP2 C,1
OP2 C,170
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL43
261345331424
46372031100
-256466331666
-103540000000
LL43:
OP2 VA,6
OP2 VX,%"loc"
OP U7
OP B1
OP N3
OP2 IVA,4
OP2 A,2
OP2 C,1
OP N4
OP B1
OP2 IVA,5
OP2 A,2
OP2 C,2
OP B14
OP B1
L164:
OP2 IVA,4
OP U10
OP2 F,L165
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL44
227361200000
LL44:
OP2 VA,5
OP U7
OP U3
OP N3
OP2 T,L164
L165:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL45
-315473210214
50000000000
LL45:
OP2 A,6
OP N3
OP N11
L166=165
L167:
OP2 IVA,5
OP2 A,2
OP2 C,2
OP N4
OP B1
OP2 IA,4
OP2 C,3
OP B4
OP2 F,L170
OP2 IA,3
OP2 F,L171
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,2
OP N4
OP2 C,0
OP N3
OP N11
L171:
OP2 IA,5
OP2 C,0
OP N4
OP2 C,142
OP B4
OP2 A,5
OP2 C,1
OP N4
OP2 C,14
OP B4
OP B3
OP2 F,L172
OP2 IX,%"cexpr"
OP N2
OP2 A,5
OP2 C,2
OP N4
OP2 C,0
OP N3
OP2 IX,%"cexpr"
OP N2
OP2 A,5
OP2 C,3
OP N4
OP2 C,0
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL46
46372020234
320240000000
LL46:
OP N3
OP N11
L172:
L170:
OP2 IA,3
OP2 F,L173
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL47
-130462315062
-170473711424
50000000000
LL47:
OP N3
L173:
OP2 IA,4
OP2 C,1
OP B4
OP2 F,L174
OP2 IX,%"cexpr"
OP N2
OP2 A,5
OP2 C,1
OP N3
OP N11
L174:
OP2 IX,%"cexpr"
OP N2
OP2 A,5
OP2 A,4
OP2 C,1
OP B4
OP2 A,4
OP2 C,5
OP B10
OP B2
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL50
46372020112
-162642073000
LL50:
OP2 A,2
OP U3
OP2 C,40
OP B15
OP2 A,4
OP N3
OP N11
L175=142
L176:
OP2 IA,3
OP2 F,L177
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL51
-130462315062
-170473711424
50000000000
LL51:
OP N3
L177:
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,2
OP N4
OP2 A,4
OP2 C,1
OP B4
OP2 A,4
OP2 C,100
OP B10
OP B2
OP N3
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,3
OP N4
OP2 C,0
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL52
46372020112
-162642073000
LL52:
OP2 A,2
OP U3
OP2 C,40
OP B15
OP2 A,4
OP N3
OP N11
L200=77
L201:
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,2
OP N4
OP2 C,0
OP N3
OP2 IVX,%"drop"
OP2 C,1
OP B1
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL53
46372031100
-346466355042
50000000000
LL53:
OP2 A,2
OP2 C,1
OP N4
OP N3
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,3
OP N4
OP2 C,0
OP N3
OP2 IVX,%"drop"
OP2 C,1
OP B1
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL54
46372031100
-256466355042
50000000000
LL54:
OP2 A,2
OP2 C,1
OP N4
OP2 C,1
OP B14
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL55
-316642042754
0
LL55:
OP2 A,2
OP2 C,1
OP N4
OP N3
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,4
OP N4
OP2 C,0
OP N3
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL56
-316642042754
0
LL56:
OP2 A,2
OP2 C,1
OP N4
OP2 C,1
OP B14
OP N3
OP N11
L202=12051
L203:
OP2 IX,%"cexpr"
OP N2
OP2 A,2
OP2 C,1
OP N4
OP2 C,0
OP N3
OP2 IVA,4
OP2 A,2
OP2 C,2
OP N4
OP B1
OP2 IA,4
OP2 C,0
OP B4
OP2 F,L204
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL57
46372020234
304240000000
LL57:
OP N3
OP N11
L204:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL60
46372020234
310240000000
LL60:
OP N3
OP2 IVA,5
OP2 A,2
OP2 C,3
OP B14
OP B1
L205:
OP2 IVA,4
OP U10
OP2 F,L206
OP2 IX,%"cexpr"
OP N2
OP2 VA,5
OP U7
OP U3
OP2 C,0
OP N3
OP2 T,L205
L206:
OP2 IX,%"printf"
OP N2
OP2 VX,.+3
OP2 T,LL61
46372020234
314240000000
LL61:
OP N3
OP N11
OP2 T,.+24
L147:
11
L150
L151
L153
L154
L155
L156
L157
L160
L161
L162
L166
L167
L175
L176
L200
L201
L202
L203
OP2 IX,%"error"
OP N2
OP2 VX,.+3
OP2 T,LL62
-50422410442
-40433710040
201134305000
LL62:
OP2 A,2
OP U3
OP N3
OP N11
LL33:
%"getw":
.+1
OP2 S,5
OP2 VA,4
OP2 C,0
OP B1
OP2 IVA,2
OP2 C,0
OP B1
L207:
OP2 IVA,3
OP2 X,%"getchar"
OP N1
OP B1
OP2 C,40
OP B5
OP2 F,L210
OP2 IA,3
OP2 C,55
OP B4
OP2 F,L211
OP2 IVA,4
OP2 C,1
OP B1
OP2 T,L212
L211:
OP2 IVA,2
OP2 A,2
OP2 C,10
OP B17
OP2 A,3
OP B14
OP2 C,60
OP B15
OP B1
L212:
OP2 T,L207
L210:
OP2 IA,4
OP2 F,L213
OP2 IVA,2
OP2 A,2
OP U2
OP B1
L213:
OP2 IA,2
OP N7
OP N11
LL63:
%"readsym":
.+1
OP2 S,5
OP2 VA,3
OP2 C,0
OP B1
L214:
OP2 IVA,4
OP2 X,%"getchar"
OP N1
OP B1
OP2 C,40
OP B5
OP2 F,L215
OP2 IX,%"lchar"
OP N2
OP2 A,2
OP2 VA,3
OP U7
OP2 A,4
OP N3
OP2 T,L214
L215:
L216:
OP2 IA,3
OP2 X,%"namsiz"
OP B7
OP2 F,L217
OP2 IX,%"lchar"
OP N2
OP2 A,2
OP2 VA,3
OP U7
OP2 C,0
OP N3
OP2 T,L216
L217:
OP N11
LL64:
%"block":
.+1
OP2 S,12
OP2 VA,10
OP2 X,%"blockp"
OP B1
OP2 IVA,11
OP2 VA,3
OP B1
OP2 IVA,2
OP U7
L220:
OP2 IVA,2
OP U10
OP2 F,L221
OP2 IVX,%"blockp"
OP U7
OP2 VA,11
OP U7
OP U3
OP B1
OP2 T,L220
L221:
OP2 IA,10
OP N7
OP N11
LL65:
%"error":
.+1
OP2 S,6
OP2 VX,%"nerror"
OP U7
OP2 IVA,5
OP2 X,%"fout"
OP B1
OP2 IVX,%"fout"
OP2 C,1
OP B1
OP2 IX,%"printf"
OP N2
OP2 A,2
OP2 A,3
OP2 A,4
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,12
OP N3
OP2 IVX,%"fout"
OP2 A,5
OP B1
OP N11
LL66:
%"namsiz":
12
%"space":
.+1
.=.+372
%"blockp":
.=.+1
%"nerror":
.=.+1
%"ap":
0
%"ast":
.+1
.=.+50
%"sp":
0
%"stack":
.+1
.=.+50
%"ilbl":
.=.+1
%"loc":
1
%"stklvl":
0
%"setstk":
0
%"drop":
0
END
|
aap/b
| 1,121
|
pdp10_its/printf.s
|
RELOCATABLE
.INSRT B;B DEF
%"printf":
.+1
OP2 S,21
OP2 VA,17
OP2 C,0
OP B1
OP2 IVA,14
OP2 VA,3
OP B1
L1:
L2:
OP2 S,21
OP2 VA,16
OP2 X,%"char"
OP N2
OP2 A,2
OP2 VA,17
OP U7
OP N3
OP B1
OP2 C,45
OP B5
OP2 F,L3
OP2 IA,16
OP2 C,0
OP B4
OP2 F,L4
OP N11
L4:
OP2 IX,%"putchar"
OP N2
OP2 A,16
OP N3
OP2 T,L2
L3:
OP2 IVA,15
OP2 VA,14
OP U7
OP U3
OP B1
OP2 IVA,16
OP2 X,%"char"
OP N2
OP2 A,2
OP2 VA,17
OP U7
OP N3
OP B1
OP2 Z,L5
L6=144
L7:
L10=157
L11:
OP2 IX,%"printn"
OP N2
OP2 A,15
OP2 A,16
OP2 C,157
OP B4
OP2 F,L12
OP2 IC,10
OP2 T,L13
L12:
OP2 IC,12
L13:
OP N3
OP2 IX,LL1+0
OP N6
L14=143
L15:
OP2 IX,%"putchar"
OP N2
OP2 A,15
OP N3
OP2 IX,LL1+0
OP N6
L16=163
L17:
OP2 IVA,20
OP2 C,0
OP B1
L20:
OP2 IVA,16
OP2 X,%"char"
OP N2
OP2 A,15
OP2 VA,20
OP U7
OP N3
OP B1
OP2 C,0
OP B5
OP2 F,L21
OP2 IX,%"putchar"
OP N2
OP2 A,16
OP N3
OP2 T,L20
L21:
OP2 IX,LL1+0
OP N6
OP2 T,.+12
L5:
4
L6
L7
L10
L11
L14
L15
L16
L17
OP2 IX,%"putchar"
OP N2
OP2 C,45
OP N3
OP2 IVA,17
OP U10
OP2 IVA,14
OP U10
OP2 IX,LL1+0
OP N6
OP N11
LL1:
L1
END
|
aap/b
| 25,985
|
pdp10_its/bc10.s
|
RELOCATABLE
.INSRT B;B DEF
%"main":
.+1
OP Y,3
OP2 S,16
OP2 X,%"getarg"
OP N2
OP2 A,3
OP2 X,%"args"
OP2 C,0
OP N3
OP2 IVA,2
OP2 X,%"sixch"
OP N2
OP2 A,3
OP N3
OP B1
OP2 C,0
OP B4
OP2 F,L1
L2:
OP2 S,16
OP2 X,%"err"
OP N2
OP2 C,33555
OP2 C,0
OP N3
OP2 IX,%"exit"
OP N2
OP2 C,1
OP N3
L1:
OP2 IVX,%"fin"
OP2 X,%"openr"
OP N2
OP2 C,12
OP2 A,2
OP2 X,%"sixch"
OP N2
OP2 VX,.+3
OP2 T,LL2
-170000000000
LL2:
OP N3
OP N3
OP B1
OP2 C,0
OP B7
OP2 F,L3
OP2 IX,LL1+0
OP N6
L3:
OP2 IVX,%"fout"
OP2 X,%"openw"
OP N2
OP2 C,13
OP2 A,2
OP2 X,%"sixch"
OP N2
OP2 VX,.+3
OP2 T,LL3
-134000000000
LL3:
OP N3
OP N3
OP B1
OP2 C,0
OP B7
OP2 F,L4
OP2 IX,LL1+0
OP N6
L4:
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL4
-170241310400
LL4:
OP2 C,4
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL5
-150161306444
0
LL5:
OP2 C,3
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL6
-140401310400
LL6:
OP2 C,6
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL7
-64641305034
-110000000000
LL7:
OP2 C,7
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL10
-130640000000
LL10:
OP2 C,10
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL11
-40562611466
0
LL11:
OP2 C,11
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL12
-150461415400
LL12:
OP2 C,12
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL13
-60202605472
-140000000000
LL13:
OP2 C,13
OP N3
OP2 IX,%"keyw"
OP N2
OP2 VX,.+3
OP2 T,LL14
-160741415400
LL14:
OP2 C,14
OP N3
L5:
OP2 IX,%"eof"
OP U4
OP2 F,L6
OP2 IX,%"extdef"
OP N1
OP2 IX,%"enddef"
OP N1
OP2 T,L5
L6:
OP2 IX,%"exit"
OP N2
OP2 X,%"nerror"
OP2 C,0
OP B5
OP N3
OP N11
LL1:
L2
%"keyw":
.+1
OP2 S,11
OP2 VA,4
OP2 X,%"namsiz"
OP B1
OP2 IVA,5
OP2 VA,6
OP2 C,0
OP B1
OP B1
L7:
OP2 IVA,4
OP U10
OP2 F,L10
OP2 IX,%"lchar"
OP N2
OP2 X,%"symbuf"
OP2 VA,5
OP U7
OP2 VA,7
OP2 X,%"char"
OP N2
OP2 A,2
OP2 VA,6
OP U7
OP N3
OP B1
OP N3
OP2 IA,7
OP2 C,0
OP B4
OP2 F,L11
OP2 IVA,6
OP U10
L11:
OP2 T,L7
L10:
OP2 IVA,10
OP2 X,%"lookup"
OP N1
OP B1
OP2 IA,10
OP2 C,0
OP B14
OP2 C,1
OP B1
OP2 IA,10
OP2 C,1
OP B14
OP2 A,3
OP B1
OP N11
LL15:
%"extdef":
.+1
OP2 S,5
OP2 VA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,0
OP B4
OP2 A,2
OP2 C,12
OP B4
OP B2
OP2 F,L12
OP N11
L12:
OP2 IA,2
OP2 C,17
OP B5
OP2 F,L13
OP2 IX,LL16+0
OP N6
L13:
OP2 IX,%"csym"
OP2 C,0
OP B14
OP2 C,3
OP B1
OP2 IX,%"gensym"
OP N2
OP2 C,147
OP2 X,%"csym"
OP2 C,2
OP B14
OP N3
OP2 IVA,4
OP2 C,1
OP B1
OP2 IVX,%"peeksym"
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,6
OP B4
OP2 F,L15
OP2 IVX,%"peeksym"
OP2 C,-1
OP B1
OP2 IVA,4
OP2 C,0
OP B1
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,15
OP B4
OP2 F,L16
OP2 IVA,4
OP2 X,%"cval"
OP B1
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
L16:
OP2 IA,2
OP2 C,7
OP B5
OP2 F,L17
OP2 IX,LL16+0
OP N6
L17:
OP2 IX,%"gen0"
OP N2
OP2 C,166
OP N3
L15:
L20:
OP2 S,5
OP2 VA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 Z,L21
L22=4
L23:
OP2 IVX,%"nauto"
OP2 C,2
OP B1
OP2 IVX,%"nlbl"
OP2 C,0
OP B1
OP2 IX,%"gen0"
OP N2
OP2 C,145
OP N3
OP2 IX,%"declare"
OP N2
OP2 C,5
OP N3
OP2 IX,%"gen0"
OP N2
OP2 C,123
OP N3
OP2 IX,%"stmt"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,11
OP N3
OP2 IX,%"gen0"
OP N2
OP2 C,160
OP N3
OP2 IVA,3
OP2 C,0
OP B1
L24:
OP2 IA,3
OP2 X,%"nlbl"
OP B7
OP2 F,L25
OP2 IX,%"gen1"
OP N2
OP2 C,154
OP2 X,%"lbltab"
OP2 VA,3
OP U7
OP N4
OP N3
OP2 T,L24
L25:
OP N11
L26=12
L27:
L30:
OP2 S,5
OP2 A,4
OP2 C,0
OP B11
OP2 F,L31
OP2 IX,%"gen1"
OP N2
OP2 C,162
OP2 A,4
OP N3
L31:
OP N11
L32=15
L33:
OP2 IX,%"gen1"
OP N2
OP2 C,157
OP2 X,%"cval"
OP N3
L34:
OP2 S,5
OP2 VA,4
OP U10
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,12
OP B4
OP2 F,L35
OP2 IX,LL16+2
OP N6
L35:
OP2 IA,2
OP2 C,21
OP B5
OP2 F,L36
OP2 IX,LL16+0
OP N6
L36:
OP2 IX,LL16+1
OP N6
L37=16
L40:
OP2 IX,%"getstr"
OP N1
OP2 IX,LL16+3
OP N6
L41=0
L42:
OP N11
OP2 T,.+14
L21:
5
L22
L23
L26
L27
L32
L33
L37
L40
L41
L42
L14:
OP2 S,5
OP2 X,%"err"
OP N2
OP2 C,36170
OP2 C,0
OP N3
OP2 IX,%"errflush"
OP N2
OP2 A,2
OP N3
OP N11
LL16:
L14
L20
L30
L34
%"enddef":
.+1
OP2 S,3
OP2 VA,2
OP2 X,%"symtab"
OP B1
L43:
OP2 IA,2
OP2 X,%"symtab"
OP2 X,%"stablen"
OP B14
OP B7
OP2 F,L44
OP2 IA,2
OP2 C,2
OP N4
OP2 F,L45
OP2 IA,2
OP2 C,0
OP N4
OP2 C,0
OP B4
OP2 F,L46
OP2 IX,%"err"
OP N2
OP2 C,35356
OP2 A,2
OP2 C,2
OP B14
OP N3
L46:
L45:
OP2 IA,2
OP2 C,0
OP N4
OP2 C,1
OP B5
OP2 F,L47
OP2 IA,2
OP2 C,2
OP B14
OP2 C,0
OP B1
OP2 IVX,%"symused"
OP U10
L47:
OP2 IVA,2
OP2 X,%"symsz"
OP B114
OP2 T,L43
L44:
OP N11
LL17:
%"declare":
.+1
L50:
OP2 S,4
OP2 VA,3
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,17
OP B4
OP2 F,L51
OP2 IX,%"csym"
OP U3
OP2 C,0
OP B5
OP2 F,L52
OP2 IX,%"err"
OP N2
OP2 C,34544
OP2 X,%"csym"
OP2 C,2
OP B14
OP N3
L52:
OP2 IX,%"csym"
OP2 A,2
OP B1
OP2 IA,2
OP2 C,3
OP B5
OP2 F,L53
OP2 IX,%"csym"
OP2 C,4
OP B1
OP2 IX,%"csym"
OP2 C,1
OP B14
OP2 VX,%"nauto"
OP U7
OP B1
L53:
OP2 IVA,3
OP2 X,%"symbol"
OP N1
OP B1
OP2 IA,2
OP2 C,4
OP B4
OP2 A,3
OP2 C,15
OP B4
OP B3
OP2 F,L54
OP2 IX,%"gen1"
OP N2
OP2 C,171
OP2 X,%"csym"
OP2 C,1
OP N4
OP N3
OP2 IVX,%"nauto"
OP2 X,%"cval"
OP B114
OP2 IVA,3
OP2 X,%"symbol"
OP N1
OP B1
L54:
OP2 IA,3
OP2 C,21
OP B5
OP2 F,L55
OP2 IX,LL20+0
OP N6
L55:
OP2 T,L50
L51:
L56:
OP2 S,4
OP2 A,3
OP2 C,12
OP B4
OP2 A,2
OP2 C,5
OP B5
OP B3
OP2 A,3
OP2 C,5
OP B4
OP2 A,2
OP2 C,5
OP B4
OP B3
OP B2
OP2 F,L57
OP N11
L57:
OP2 IX,%"err"
OP N2
OP2 C,34770
OP2 C,0
OP N3
OP2 IX,%"errflush"
OP N2
OP2 A,3
OP N3
OP N11
LL20:
L56
%"stmt":
.+1
OP2 S,10
OP2 VA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 Z,L60
L61=0
L62:
OP2 IX,%"err"
OP N2
OP2 C,17677
OP2 C,0
OP N3
OP N11
L63=11
L64:
OP2 IVX,%"peeksym"
OP2 A,2
OP B1
L65=12
L66:
OP N11
L67=10
L70:
L71:
OP2 IX,%"eof"
OP U4
OP2 F,L72
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,11
OP B4
OP2 F,L73
OP N11
L73:
OP2 IVX,%"peeksym"
OP2 A,2
OP B1
OP2 IX,%"stmt"
OP N1
OP2 T,L71
L72:
OP2 IX,%"err"
OP N2
OP2 C,11051
OP2 C,0
OP N3
OP N11
L74=20
L75:
OP2 IX,%"cval"
OP2 Z,L76
L77=4
L100:
L101=3
L102:
OP2 IX,%"declare"
OP N2
OP2 X,%"cval"
OP N3
OP2 IX,%"stmt"
OP N6
L103=6
L104:
OP2 IX,%"expr"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,6
OP N3
OP2 IX,LL21+0
OP N6
L106=7
L107:
OP2 IVX,%"peeksym"
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,4
OP B4
OP2 F,L110
OP2 IX,%"pexpr"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,7
OP N3
OP2 IX,LL21+0
OP N6
L110:
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,11
OP N3
OP2 IX,LL21+0
OP N6
L111=10
L112:
OP2 IX,%"pexpr"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,146
OP2 VA,3
OP2 VX,%"loc"
OP U7
OP B1
OP N3
OP2 IX,%"stmt"
OP N1
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,20
OP B4
OP2 X,%"cval"
OP2 C,12
OP B4
OP B3
OP2 F,L113
OP2 IX,%"gen1"
OP N2
OP2 C,164
OP2 VA,4
OP2 VX,%"loc"
OP U7
OP B1
OP N3
OP2 IX,%"label"
OP N2
OP2 A,3
OP N3
OP2 IX,%"stmt"
OP N1
OP2 IX,%"label"
OP N2
OP2 A,4
OP N3
OP N11
L113:
OP2 IVX,%"peeksym"
OP2 A,2
OP B1
OP2 IX,%"label"
OP N2
OP2 A,3
OP N3
OP N11
L114=11
L115:
OP2 IX,%"label"
OP N2
OP2 VA,3
OP2 VX,%"loc"
OP U7
OP B1
OP N3
OP2 IVA,4
OP2 VX,%"loc"
OP U7
OP B1
OP2 IX,%"pexpr"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,146
OP2 A,4
OP N3
OP2 IX,%"stmt"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,164
OP2 A,3
OP N3
OP2 IX,%"label"
OP N2
OP2 A,4
OP N3
OP N11
L116=14
L117:
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,15
OP B5
OP2 F,L120
OP2 IX,LL21+1
OP N6
L120:
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,22
OP B5
OP2 F,L122
OP2 IX,LL21+1
OP N6
L122:
OP2 IX,%"swp"
OP2 C,0
OP B4
OP2 F,L123
OP2 IX,LL21+1
OP N6
L123:
OP2 IX,%"swp"
OP2 X,%"swtab"
OP2 X,%"swsiz"
OP B14
OP B10
OP2 F,L124
OP2 IX,%"err"
OP N2
OP2 C,17543
OP2 C,0
OP N3
OP2 IX,%"exit"
OP N2
OP2 C,1
OP N3
L124:
OP2 IX,%"gen2"
OP N2
OP2 C,161
OP2 X,%"loc"
OP2 X,%"cval"
OP N3
OP2 IVX,%"swp"
OP U7
OP2 VX,%"loc"
OP U7
OP B1
OP2 IX,%"label"
OP N2
OP2 VX,%"loc"
OP U7
OP N3
OP2 IX,%"stmt"
OP N6
L125=13
L126:
OP2 IX,%"expr"
OP N1
OP2 IX,%"gen1"
OP N2
OP2 C,172
OP2 VA,3
OP2 VX,%"loc"
OP U7
OP B1
OP N3
OP2 IX,%"swp"
OP2 C,0
OP B4
OP2 F,L127
OP2 IVX,%"swp"
OP2 X,%"swtab"
OP B1
L127:
OP2 IVA,7
OP2 X,%"swp"
OP B1
OP2 IX,%"stmt"
OP N1
OP2 IX,%"swp"
OP2 A,7
OP B4
OP2 F,L130
OP2 IX,%"err"
OP N2
OP2 C,34767
OP2 C,0
OP N3
L130:
OP2 IX,%"gen1"
OP N2
OP2 C,153
OP2 C,1
OP2 X,%"swp"
OP2 A,7
OP B15
OP2 C,2
OP B17
OP B14
OP N3
OP2 IX,%"label"
OP N2
OP2 A,3
OP N3
OP2 IX,%"gen1"
OP N2
OP2 C,157
OP2 X,%"swp"
OP2 A,7
OP B15
OP N3
OP2 IVA,6
OP2 A,7
OP B1
L131:
OP2 IA,6
OP2 X,%"swp"
OP B5
OP2 F,L132
OP2 IX,%"gen1"
OP N2
OP2 C,154
OP2 VA,3
OP2 VA,6
OP U7
OP U3
OP B1
OP N3
OP2 IX,%"gen1"
OP N2
OP2 C,154
OP2 VA,3
OP U5
OP N3
OP2 T,L131
L132:
OP2 IVX,%"swp"
OP2 A,7
OP B1
OP N11
OP2 T,.+22
L76:
10
L77
L100
L101
L102
L103
L104
L106
L107
L111
L112
L114
L115
L116
L117
L125
L126
OP2 IX,LL21+1
OP N6
L133=17
L134:
OP2 IX,%"peekc"
OP2 C,72
OP B4
OP2 F,L135
OP2 IVX,%"peekc"
OP2 C,0
OP B1
OP2 IX,%"csym"
OP2 C,0
OP N4
OP2 C,0
OP B11
OP2 F,L136
OP2 IX,%"err"
OP N2
OP2 C,34544
OP2 X,%"csym"
OP2 C,2
OP B14
OP N3
OP2 IX,%"stmt"
OP N6
L136:
OP2 IX,%"csym"
OP2 C,0
OP B14
OP2 C,2
OP B1
OP2 IX,%"deflab"
OP N1
OP2 IX,%"label"
OP N2
OP2 X,%"lbltab"
OP2 X,%"csym"
OP2 C,1
OP N4
OP2 C,1
OP B15
OP N4
OP N3
OP2 IX,%"gen0"
OP N2
OP2 C,123
OP N3
OP2 IX,%"stmt"
OP N6
L135:
OP2 T,.+16
L60:
6
L61
L62
L63
L64
L65
L66
L67
L70
L74
L75
L133
L134
OP2 IVX,%"peeksym"
OP2 A,2
OP B1
OP2 IX,%"expr"
OP N1
L105:
OP2 S,10
OP2 VA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,12
OP B4
OP2 F,L137
OP N11
L137:
L121:
OP2 S,10
OP2 X,%"err"
OP N2
OP2 C,34770
OP2 C,0
OP N3
OP2 IX,%"errflush"
OP N2
OP2 A,2
OP N3
OP2 IX,%"stmt"
OP N6
OP N11
LL21:
L105
L121
%"deflab":
.+1
OP2 S,2
OP2 X,%"csym"
OP2 C,1
OP N4
OP2 C,0
OP B4
OP2 F,L140
OP2 IX,%"nlbl"
OP2 X,%"lblsiz"
OP B10
OP2 F,L141
OP2 IX,%"err"
OP N2
OP2 C,17551
OP2 C,0
OP N3
OP2 IX,%"exit"
OP N2
OP2 C,1
OP N3
L141:
OP2 IX,%"lbltab"
OP2 X,%"nlbl"
OP B14
OP2 VX,%"loc"
OP U7
OP B1
OP2 IX,%"csym"
OP2 C,1
OP B14
OP2 VX,%"nlbl"
OP U5
OP B1
L140:
OP N11
LL22:
%"label":
.+1
OP2 S,3
OP2 X,%"gen1"
OP N2
OP2 C,114
OP2 A,2
OP N3
OP N11
LL23:
%"putw":
.+1
OP2 S,3
OP2 A,2
OP2 C,0
OP B7
OP2 F,L142
OP2 IX,%"putchar"
OP N2
OP2 C,55
OP N3
L142:
OP2 IX,%"prtn"
OP N2
OP2 A,2
OP2 C,10
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,40
OP N3
OP N11
LL24:
%"putsym":
.+1
OP2 S,5
OP2 VA,3
OP2 C,0
OP B1
L143:
OP2 IA,3
OP2 X,%"namsiz"
OP B7
OP2 VA,4
OP2 X,%"char"
OP N2
OP2 A,2
OP2 VA,3
OP U7
OP N3
OP B1
OP2 C,0
OP B5
OP B3
OP2 F,L144
OP2 IX,%"putchar"
OP N2
OP2 A,4
OP N3
OP2 T,L143
L144:
OP2 IX,%"putchar"
OP N2
OP2 C,40
OP N3
OP N11
LL25:
%"gen0":
.+1
OP2 S,3
OP2 X,%"putchar"
OP N2
OP2 A,2
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,12
OP N3
OP N11
LL26:
%"gen1":
.+1
OP2 S,4
OP2 X,%"putchar"
OP N2
OP2 A,2
OP N3
OP2 IX,%"putw"
OP N2
OP2 A,3
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,12
OP N3
OP N11
LL27:
%"gen2":
.+1
OP2 S,5
OP2 X,%"putchar"
OP N2
OP2 A,2
OP N3
OP2 IX,%"putw"
OP N2
OP2 A,3
OP N3
OP2 IX,%"putw"
OP N2
OP2 A,4
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,12
OP N3
OP N11
LL30:
%"gensym":
.+1
OP2 S,4
OP2 X,%"putchar"
OP N2
OP2 A,2
OP N3
OP2 IX,%"putsym"
OP N2
OP2 A,3
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,12
OP N3
OP N11
LL31:
%"pexpr":
.+1
OP2 S,3
OP2 VA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,4
OP B5
OP2 F,L145
OP2 IX,LL32+0
OP N6
L145:
OP2 IX,%"expr"
OP N1
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,5
OP B4
OP2 F,L147
OP N11
L147:
L146:
OP2 S,3
OP2 X,%"err"
OP N2
OP2 C,34770
OP2 C,0
OP N3
OP2 IX,%"errflush"
OP N2
OP2 A,2
OP N3
OP N11
LL32:
L146
%"expr":
.+1
OP Y,3
OP Y,31
OP2 S,63
OP2 VA,2
OP2 A,3
OP B1
OP2 IVA,30
OP2 A,31
OP B1
OP2 IA,2
OP2 C,0
OP B1
OP2 IA,30
OP2 C,6
OP B1
OP2 IVA,56
OP2 C,0
OP B1
OP2 IX,%"gen1"
OP N2
OP2 C,163
OP2 X,%"nauto"
OP N3
L150:
OP2 S,63
OP2 VA,57
OP2 X,%"symbol"
OP N1
OP B1
OP2 Z,L151
L152=17
L153:
OP2 IX,%"csym"
OP U3
OP2 C,0
OP B4
OP2 F,L154
OP2 IX,%"peekc"
OP2 C,50
OP B4
OP2 F,L155
OP2 IX,%"csym"
OP2 C,0
OP B14
OP2 C,3
OP B1
OP2 T,L156
L155:
OP2 IX,%"deflab"
OP N1
L156:
L154:
OP2 IX,%"csym"
OP U3
OP2 Z,L157
L160=3
L161:
OP2 IX,%"gensym"
OP N2
OP2 C,170
OP2 X,%"csym"
OP2 C,2
OP B14
OP N3
OP2 IX,LL33+1
OP N6
L163=0
L164:
L165=2
L166:
OP2 IX,%"gen1"
OP N2
OP2 C,151
OP2 X,%"csym"
OP2 C,1
OP N4
OP2 C,1
OP B15
OP N3
OP2 IX,LL33+1
OP N6
L167=4
L170:
OP2 IX,%"gen1"
OP N2
OP2 C,141
OP2 X,%"csym"
OP2 C,1
OP N4
OP N3
OP2 IX,LL33+1
OP N6
OP2 T,.+12
L157:
4
L160
L161
L163
L164
L165
L166
L167
L170
OP2 IX,LL33+2
OP N6
L172=15
L173:
L174:
OP2 S,63
OP2 X,%"gen1"
OP N2
OP2 C,143
OP2 X,%"cval"
OP N3
OP2 IX,LL33+1
OP N6
L175=16
L176:
OP2 IX,%"gen0"
OP N2
OP2 C,74
OP N3
OP2 IX,%"getstr"
OP N1
OP2 IX,%"gen0"
OP N2
OP2 C,76
OP N3
L162:
OP2 S,63
OP2 A,56
OP2 F,L177
OP2 IX,LL33+2
OP N6
L177:
OP2 IVA,56
OP2 C,1
OP B1
OP2 IX,LL33+0
OP N6
L200=72
L201:
L202=73
L203:
OP2 IA,56
OP2 F,L204
OP2 IVA,57
OP2 C,2
OP B114
L204:
OP2 IX,LL33+4
OP N6
L206=71
L207:
OP2 IA,56
OP2 F,L210
OP2 IX,LL33+2
OP N6
L210:
OP2 IX,LL33+4
OP N6
L211=43
L212:
OP2 IA,56
OP U4
OP2 F,L213
OP2 IVX,%"peeksym"
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,15
OP B4
OP2 F,L214
OP2 IVX,%"peeksym"
OP2 C,-1
OP B1
OP2 IVX,%"cval"
OP2 X,%"cval"
OP U2
OP B1
OP2 IX,LL33+3
OP N6
L214:
OP2 IVA,57
OP2 C,67
OP B1
L213:
OP2 IVA,56
OP2 C,0
OP B1
OP2 IX,LL33+4
OP N6
L215=31
L216:
L217=45
L220:
OP2 IA,56
OP2 F,L221
OP2 IVA,56
OP2 C,0
OP B1
OP2 T,L222
L221:
OP2 IA,57
OP2 C,31
OP B4
OP2 F,L223
OP2 IVA,57
OP2 C,66
OP B1
OP2 T,L224
L223:
OP2 IVA,57
OP2 C,70
OP B1
L224:
L222:
OP2 IX,LL33+4
OP N6
L225=4
L226:
OP2 IA,56
OP2 F,L227
OP2 IVA,57
OP2 X,%"symbol"
OP N1
OP B1
OP2 C,5
OP B4
OP2 F,L230
OP2 IVA,57
OP2 C,25
OP B1
OP2 T,L231
L230:
OP2 IVX,%"peeksym"
OP2 A,57
OP B1
OP2 IVA,57
OP2 C,24
OP B1
OP2 IVA,56
OP2 C,0
OP B1
L231:
L227:
OP2 IX,LL33+4
OP N6
L232=5
L233:
L234=7
L235:
OP2 IA,56
OP U4
OP2 F,L236
OP2 IX,LL33+2
OP N6
L236:
OP2 IX,LL33+4
OP N6
OP2 T,.+32
L151:
14
L152
L153
L172
L173
L175
L176
L200
L201
L202
L203
L206
L207
L211
L212
L215
L216
L217
L220
L225
L226
L232
L233
L234
L235
OP2 IA,56
OP U4
OP2 F,L237
OP2 IX,LL33+2
OP N6
L237:
OP2 IVA,56
OP2 C,0
OP B1
L205:
OP2 S,63
OP2 VA,60
OP2 X,%"opdope"
OP2 A,57
OP N4
OP B1
OP2 IA,60
OP2 A,30
OP U3
OP B11
OP2 A,60
OP2 A,30
OP U3
OP B4
OP2 A,60
OP2 C,1
OP B3
OP2 C,0
OP B5
OP B3
OP B2
OP2 F,L240
OP2 IA,57
OP2 Z,L241
L242=24
L243:
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,2
OP N3
L244=4
L245:
L246=6
L247:
OP2 IVA,60
OP2 C,4
OP B1
OP2 T,.+10
L241:
3
L242
L243
L244
L245
L246
L247
OP2 IA,2
OP2 A,3
OP2 C,24
OP B14
OP B10
OP2 F,L250
OP2 IX,%"err"
OP N2
OP2 C,17545
OP2 C,0
OP N3
OP2 IX,%"exit"
OP N2
OP2 C,1
OP N3
L250:
OP2 IVA,2
OP U5
OP2 A,57
OP B1
OP2 IVA,30
OP U5
OP2 A,60
OP B1
OP2 IX,LL33+0
OP N6
L240:
OP2 IVA,30
OP U6
OP2 IVA,61
OP2 VA,2
OP U10
OP U3
OP B1
OP2 Z,L251
L252=0
L253:
OP2 IVX,%"peeksym"
OP2 A,57
OP B1
OP2 IX,%"gen0"
OP N2
OP2 C,105
OP N3
OP N11
L254=23
L255:
OP2 IX,%"gen1"
OP N2
OP2 C,77
OP2 VX,%"loc"
OP U7
OP N3
OP2 IVX,%"loc"
OP U7
L256=22
L257:
OP2 IX,LL33+4
OP N6
L260=24
L261:
OP2 IA,57
OP2 C,5
OP B5
OP2 F,L262
OP2 IX,LL33+2
OP N6
L262:
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,3
OP N3
OP2 IX,LL33+0
OP N6
L263=25
L264:
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,1
OP N3
L265=21
L266:
OP2 IX,LL33+4
OP N6
L267=4
L270:
OP2 IA,57
OP2 C,5
OP B5
OP2 F,L271
OP2 IX,LL33+2
OP N6
L271:
OP2 IX,LL33+0
OP N6
L272=6
L273:
OP2 IA,57
OP2 C,7
OP B5
OP2 F,L274
OP2 IX,LL33+2
OP N6
L274:
OP2 IX,%"gen1"
OP N2
OP2 C,156
OP2 C,4
OP N3
OP2 IX,LL33+0
OP N6
OP2 T,.+22
L251:
10
L252
L253
L254
L255
L256
L257
L260
L261
L263
L264
L265
L266
L267
L270
L272
L273
L275:
OP2 S,63
OP2 A,61
OP2 C,27
OP B7
OP2 F,L276
OP2 IX,LL33+2
OP N6
OP2 T,L277
L276:
OP2 IA,61
OP2 C,46
OP B6
OP2 F,L300
OP2 IX,%"gen1"
OP N2
OP2 C,142
OP2 A,61
OP2 C,27
OP B15
OP2 C,1
OP B14
OP N3
OP2 T,L301
L300:
OP2 IA,61
OP2 C,65
OP B6
OP2 F,L302
OP2 IX,%"gen1"
OP N2
OP2 C,142
OP2 A,61
OP2 C,47
OP B15
OP2 C,102
OP B14
OP N3
OP2 T,L303
L302:
OP2 IA,61
OP2 C,75
OP B6
OP2 F,L304
OP2 IX,%"gen1"
OP N2
OP2 C,165
OP2 A,61
OP2 C,66
OP B15
OP2 C,1
OP B14
OP N3
L304:
L303:
L301:
L277:
OP2 IX,LL33+4
OP N6
L171:
OP2 S,63
OP2 X,%"err"
OP N2
OP2 C,31370
OP2 C,0
OP N3
OP2 IX,%"errflush"
OP N2
OP2 A,57
OP N3
OP N11
LL33:
L150
L162
L171
L174
L205
L275
%"errflush":
.+1
L305:
OP2 S,3
OP2 A,2
OP2 C,12
OP B5
OP2 A,2
OP2 C,10
OP B5
OP B3
OP2 A,2
OP2 C,11
OP B5
OP B3
OP2 F,L306
OP2 IVA,2
OP2 X,%"symbol"
OP N1
OP B1
OP2 T,L305
L306:
OP2 IVX,%"peeksym"
OP2 A,2
OP B1
OP N11
LL34:
%"lookup":
.+1
OP2 S,7
OP2 VA,2
OP2 C,0
OP B1
OP2 IVA,5
OP2 X,%"symbuf"
OP B1
OP2 IVA,3
OP2 X,%"nwps"
OP B1
L307:
OP2 IVA,3
OP U10
OP2 F,L310
OP2 IVA,2
OP2 VA,5
OP U7
OP U3
OP B114
OP2 T,L307
L310:
OP2 IA,2
OP2 C,0
OP B7
OP2 F,L311
OP2 IVA,2
OP2 A,2
OP U2
OP B1
L311:
OP2 IVA,2
OP2 X,%"stabsz"
OP B116
OP2 IVA,2
OP2 X,%"symsz"
OP B117
L312:
OP2 IVA,4
OP2 X,%"symtab"
OP2 A,2
OP2 C,2
OP B14
OP B14
OP B1
OP U3
OP2 F,L313
OP2 IVA,5
OP2 X,%"symbuf"
OP B1
OP2 IVA,3
OP2 X,%"nwps"
OP B1
L314:
OP2 IVA,3
OP U10
OP2 F,L315
OP2 IVA,4
OP U7
OP U3
OP2 VA,5
OP U7
OP U3
OP B5
OP2 F,L316
OP2 IX,LL35+0
OP N6
L316:
OP2 T,L314
L315:
OP2 IX,%"symtab"
OP2 A,2
OP B14
OP N7
L317:
OP2 S,7
OP2 VA,2
OP2 X,%"symsz"
OP B114
OP2 X,%"stablen"
OP B10
OP2 F,L320
OP2 IVA,2
OP2 C,0
OP B1
L320:
OP2 T,L312
L313:
OP2 IVX,%"symused"
OP U5
OP2 X,%"stabsz"
OP B10
OP2 F,L321
OP2 IX,%"err"
OP N2
OP2 C,17563
OP2 C,0
OP N3
OP2 IX,%"exit"
OP N2
OP2 C,1
OP N3
L321:
OP2 IVA,6
OP2 VA,4
OP2 X,%"symtab"
OP2 A,2
OP B14
OP B1
OP B1
OP2 IVA,5
OP2 X,%"symbuf"
OP B1
OP2 IVA,4
OP U7
OP2 C,0
OP B1
OP2 IVA,4
OP U7
OP2 C,0
OP B1
OP2 IVA,3
OP2 X,%"nwps"
OP B1
L322:
OP2 IVA,3
OP U10
OP2 F,L323
OP2 IVA,4
OP U7
OP2 VA,5
OP U7
OP U3
OP B1
OP2 T,L322
L323:
OP2 IA,6
OP N7
OP N11
LL35:
L317
%"symbol":
.+1
L324:
OP2 S,5
OP2 X,%"peeksym"
OP2 C,0
OP B10
OP2 F,L325
OP2 IVA,3
OP2 X,%"peeksym"
OP B1
OP2 IVX,%"peeksym"
OP2 C,-1
OP B1
OP2 IA,3
OP N7
L325:
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 IX,%"eof"
OP2 F,L326
OP2 IC,0
OP N7
L326:
OP2 IVA,3
OP2 C,177
OP B103
OP2 IX,%"ctab"
OP2 A,3
OP N4
OP2 Z,L327
L330=1
L331:
OP2 IX,LL36+0
OP N6
L332=42
L333:
OP2 IX,%"subseq"
OP N2
OP2 C,53
OP2 C,42
OP2 C,72
OP N3
OP N7
L334=43
L335:
OP2 IX,%"subseq"
OP N2
OP2 C,55
OP2 C,43
OP2 C,73
OP N3
OP N7
L336=71
L337:
OP2 IX,%"subseq"
OP N2
OP2 C,75
OP2 C,71
OP2 C,33
OP N3
OP N7
L340=35
L341:
OP2 IX,%"subseq"
OP N2
OP2 C,74
OP2 C,0
OP2 C,1
OP N3
OP2 F,L342
OP2 IC,41
OP N7
L342:
OP2 IX,%"subseq"
OP N2
OP2 C,75
OP2 C,35
OP2 C,34
OP N3
OP N7
L343=37
L344:
OP2 IX,%"subseq"
OP N2
OP2 C,76
OP2 C,0
OP2 C,1
OP N3
OP2 F,L345
OP2 IC,40
OP N7
L345:
OP2 IX,%"subseq"
OP N2
OP2 C,75
OP2 C,37
OP2 C,36
OP N3
OP N7
L346=27
L347:
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 C,75
OP B4
OP2 F,L350
OP2 IX,%"subseq"
OP N2
OP2 C,75
OP2 C,32
OP2 C,51
OP N3
OP N7
L350:
OP2 IX,%"ctab"
OP2 A,3
OP N4
OP2 C,1
OP B4
OP2 F,L351
OP2 IC,27
OP N7
L351:
OP2 IX,%"ungetchr"
OP N2
OP2 A,3
OP N3
OP2 IVA,3
OP2 X,%"symbol"
OP N1
OP B1
OP2 IA,3
OP2 C,30
OP B10
OP2 A,3
OP2 C,46
OP B6
OP B3
OP2 F,L352
OP2 IA,3
OP2 C,30
OP B15
OP2 C,47
OP B14
OP N7
L352:
OP2 IVX,%"peeksym"
OP2 A,3
OP B1
OP2 IC,27
OP N7
L353=46
L354:
OP2 IX,%"subseq"
OP N2
OP2 C,52
OP2 C,1
OP2 C,0
OP N3
OP2 F,L355
OP2 IC,46
OP N7
L355:
L356:
OP2 IC,1
OP2 F,L357
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 IX,%"eof"
OP2 F,L360
OP2 IX,%"err"
OP N2
OP2 C,57
OP2 C,0
OP N3
OP2 IC,0
OP N7
L360:
OP2 IA,3
OP2 C,52
OP B4
OP2 F,L361
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 IA,3
OP2 C,57
OP B4
OP2 F,L362
OP2 IX,LL36+0
OP N6
L362:
L361:
OP2 T,L356
L357:
L363=13
L364:
OP2 IVX,%"cval"
OP2 C,0
OP B1
OP2 IA,3
OP2 C,60
OP B4
OP2 F,L365
OP2 IVA,2
OP2 C,10
OP B1
OP2 T,L366
L365:
OP2 IVA,2
OP2 C,12
OP B1
L366:
L367:
OP2 IX,%"ctab"
OP2 A,3
OP N4
OP2 C,13
OP B4
OP2 F,L370
OP2 IVX,%"cval"
OP2 X,%"cval"
OP2 A,2
OP B17
OP2 A,3
OP B14
OP2 C,60
OP B15
OP B1
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 T,L367
L370:
OP2 IX,%"ungetchr"
OP N2
OP2 A,3
OP N3
OP2 IC,15
OP N7
L371=3
L372:
OP2 IX,%"getcc"
OP N1
OP N7
L373=14
L374:
OP2 IVA,4
OP2 C,0
OP B1
L375:
OP2 IX,%"ctab"
OP2 A,3
OP N4
OP2 C,14
OP B4
OP2 X,%"ctab"
OP2 A,3
OP N4
OP2 C,13
OP B4
OP B2
OP2 F,L376
OP2 IA,4
OP2 X,%"namsiz"
OP B7
OP2 F,L377
OP2 IX,%"lchar"
OP N2
OP2 X,%"symbuf"
OP2 VA,4
OP U7
OP2 A,3
OP N3
L377:
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 T,L375
L376:
L400:
OP2 IA,4
OP2 X,%"namsiz"
OP B7
OP2 F,L401
OP2 IX,%"lchar"
OP N2
OP2 X,%"symbuf"
OP2 VA,4
OP U7
OP2 C,0
OP N3
OP2 T,L400
L401:
OP2 IX,%"ungetchr"
OP N2
OP2 A,3
OP N3
OP2 IVX,%"csym"
OP2 X,%"lookup"
OP N1
OP B1
OP2 IX,%"csym"
OP2 C,0
OP N4
OP2 C,1
OP B4
OP2 F,L402
OP2 IVX,%"cval"
OP2 X,%"csym"
OP2 C,1
OP N4
OP B1
OP2 IC,20
OP N7
L402:
OP2 IC,17
OP N7
OP2 T,.+30
L327:
13
L330
L331
L332
L333
L334
L335
L336
L337
L340
L341
L343
L344
L346
L347
L353
L354
L363
L364
L371
L372
L373
L374
OP2 IX,%"ctab"
OP2 A,3
OP N4
OP N7
OP N11
LL36:
L324
%"subseq":
.+1
OP2 S,6
OP2 VA,5
OP2 X,%"getchr"
OP N1
OP B1
OP2 A,2
OP B4
OP2 F,L403
OP2 IA,4
OP N7
L403:
OP2 IX,%"ungetchr"
OP N2
OP2 A,5
OP N3
OP2 IA,3
OP N7
OP N11
LL37:
%"getstr":
.+1
L404:
OP2 S,3
OP2 VA,2
OP2 X,%"mapch"
OP N2
OP2 C,42
OP N3
OP B1
OP2 C,0
OP B10
OP2 F,L405
OP2 IX,%"gen1"
OP N2
OP2 C,157
OP2 A,2
OP N3
OP2 T,L404
L405:
OP N11
LL40:
%"getcc":
.+1
OP2 S,3
OP2 VX,%"cval"
OP2 C,0
OP B1
L406:
OP2 IVA,2
OP2 X,%"mapch"
OP N2
OP2 C,47
OP N3
OP B1
OP2 C,0
OP B10
OP2 F,L407
OP2 IVX,%"cval"
OP2 X,%"cval"
OP2 X,%"nbpc"
OP B13
OP2 A,2
OP B14
OP B1
OP2 T,L406
L407:
OP2 IC,15
OP N7
OP N11
LL41:
%"mapch":
.+1
OP2 S,4
OP2 VA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 IX,%"eof"
OP2 A,3
OP2 C,12
OP B4
OP B2
OP2 F,L410
OP2 IX,%"err"
OP N2
OP2 C,10442
OP2 C,0
OP N3
OP2 IX,%"ungetchr"
OP N2
OP2 A,3
OP N3
OP2 IC,-1
OP N7
L410:
OP2 IA,3
OP2 A,2
OP B4
OP2 F,L411
OP2 IC,-1
OP N7
L411:
OP2 IA,3
OP2 C,52
OP B4
OP2 F,L412
OP2 IVA,3
OP2 X,%"getchr"
OP N1
OP B1
OP2 IA,3
OP2 Z,L413
L414=60
L415:
L416=145
L417:
OP2 IC,0
OP N7
L420=164
L421:
OP2 IC,11
OP N7
L422=162
L423:
OP2 IC,15
OP N7
L424=156
L425:
OP2 IC,12
OP N7
OP2 T,.+14
L413:
5
L414
L415
L416
L417
L420
L421
L422
L423
L424
L425
L412:
OP2 IA,3
OP N7
OP N11
LL42:
%"getchr":
.+1
OP2 S,3
OP2 X,%"peekc"
OP2 F,L426
OP2 IVA,2
OP2 X,%"peekc"
OP B1
OP2 IVX,%"peekc"
OP2 C,0
OP B1
OP2 T,L427
L426:
OP2 IVA,2
OP2 X,%"getchar"
OP N1
OP B1
L427:
OP2 IA,2
OP2 C,0
OP B6
OP2 F,L430
OP2 IVX,%"eof"
OP2 C,1
OP B1
OP2 IC,0
OP N7
L430:
OP2 IA,2
OP2 C,12
OP B4
OP2 F,L431
OP2 IVX,%"line"
OP U7
L431:
OP2 IA,2
OP N7
OP N11
LL43:
%"ungetchr":
.+1
OP2 S,3
OP2 A,2
OP2 C,12
OP B4
OP2 F,L432
OP2 IVX,%"line"
OP U10
L432:
OP2 IVX,%"peekc"
OP2 A,2
OP B1
OP N11
LL44:
%"prtn":
.+1
OP2 S,5
OP2 A,2
OP2 C,0
OP B7
OP2 F,L433
OP2 IVA,2
OP2 A,2
OP U2
OP B1
L433:
OP2 IVA,4
OP2 A,2
OP2 A,3
OP B20
OP B1
OP2 F,L434
OP2 IX,%"prtn"
OP N2
OP2 A,4
OP2 A,3
OP N3
L434:
OP2 IX,%"putchar"
OP N2
OP2 A,2
OP2 A,3
OP B16
OP2 C,60
OP B14
OP N3
OP N11
LL45:
%"err":
.+1
OP2 S,5
OP2 VX,%"nerror"
OP U7
OP2 IVA,4
OP2 X,%"fout"
OP B1
OP2 IVX,%"fout"
OP2 C,1
OP B1
OP2 IX,%"prtn"
OP N2
OP2 X,%"line"
OP2 C,12
OP N3
OP2 IX,%"putchar"
OP N2
OP2 C,40
OP N3
OP2 IX,%"putchar"
OP N2
OP2 A,2
OP N3
OP2 IA,3
OP2 F,L435
OP2 IX,%"putchar"
OP N2
OP2 C,40
OP N3
OP2 IX,%"putsym"
OP N2
OP2 A,3
OP N3
L435:
OP2 IX,%"putchar"
OP N2
OP2 C,12
OP N3
OP2 IVX,%"fout"
OP2 A,4
OP B1
OP N11
LL46:
%"symbuf":
.+1
.=.+2
%"nwps":
2
%"nbpc":
7
%"namsiz":
12
%"symsz":
4
%"symused":
0
%"stabsz":
620
%"stablen":
3100
%"symtab":
.+1
.=.+3100
%"loc":
1
%"swsiz":
170
%"swtab":
.+1
.=.+170
%"swp":
0
%"nauto":
0
%"nlbl":
0
%"lblsiz":
50
%"lbltab":
.+1
.=.+50
%"peeksym":
-1
%"peekc":
0
%"eof":
0
%"line":
1
%"csym":
0
%"cval":
0
%"nerror":
0
%"ctab":
.+1
377
377
377
377
377
377
377
377
377
1
1
1
377
1
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
1
71
16
377
377
44
31
3
4
5
45
42
21
43
14
46
13
13
13
13
13
13
13
13
13
13
22
12
35
27
37
23
377
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
6
377
7
377
14
377
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
10
30
11
377
377
%"opdope":
.+1
0
0
0
0
36
2
36
2
0
0
0
0
0
0
0
0
0
6
15
15
36
36
0
13
16
20
22
22
24
24
24
24
26
26
30
30
32
32
32
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
35
35
35
35
35
35
35
35
END
|
aap/b
| 1,081
|
pdp10_its/blib.s
|
RELOCATABLE
.INSRT B;B DEF
%"getarg":
.+1
OP2 S,7
OP2 VA,5
OP2 C,0
OP B1
L1:
OP2 IVA,6
OP2 X,%"char"
OP N2
OP2 A,3
OP2 A,4
OP N3
OP B1
OP2 C,40
OP B4
OP2 F,L2
OP2 IVA,4
OP U7
OP2 T,L1
L2:
L3:
OP2 IVA,6
OP2 X,%"char"
OP N2
OP2 A,3
OP2 VA,4
OP U7
OP N3
OP B1
OP2 C,0
OP B5
OP2 A,6
OP2 C,40
OP B5
OP B3
OP2 A,6
OP2 C,11
OP B5
OP B3
OP2 F,L4
OP2 IX,%"lchar"
OP N2
OP2 A,2
OP2 VA,5
OP U7
OP2 A,6
OP N3
OP2 T,L3
L4:
OP2 IA,4
OP N7
OP N11
LL1:
%"sixbit":
.+1
OP2 S,3
OP2 VA,2
OP2 C,40
OP B115
OP2 IA,2
OP2 C,0
OP B7
OP2 F,L5
OP2 IC,0
OP N7
L5:
OP2 IA,2
OP2 C,77
OP B11
OP2 F,L6
OP2 IVA,2
OP2 C,40
OP B115
L6:
OP2 IA,2
OP2 C,77
OP B3
OP N7
OP N11
LL2:
%"sixch":
.+1
OP2 S,6
OP2 VA,5
OP2 VA,3
OP2 C,0
OP B1
OP B1
L7:
OP2 IA,3
OP2 C,6
OP B7
OP2 VA,4
OP2 X,%"char"
OP N2
OP2 A,2
OP2 VA,3
OP U7
OP N3
OP B1
OP2 C,0
OP B5
OP B3
OP2 F,L10
OP2 IVA,5
OP2 X,%"sixbit"
OP N2
OP2 A,4
OP N3
OP2 C,6
OP2 A,3
OP B15
OP2 C,6
OP B17
OP B13
OP B114
OP2 T,L7
L10:
OP2 IA,5
OP N7
OP N11
LL3:
END
|
aap/b
| 6,295
|
pdp11/bilib.s
|
ipc = r3
idp = r4
isp = r5
/ set frame size
.globl s
s: mov idp,isp / get current frame
add (ipc)+,isp / put sp above it
jmp *(ipc)+
/ transfer if false
.globl f
f: mov (ipc)+,r0 / get argument
mov -(isp),(isp)+ / check top of stack
bne 1f
mov r0,ipc / jump to target if == 0
1: jmp *(ipc)+
/ transfer
.globl t
t: mov (ipc)+,ipc
jmp *(ipc)+
/ init automatic vector
.globl y
y: mov idp,r0
add (ipc)+,r0 / address of pointer
mov r0,r1 / remember address
asr r0 / to byte address
inc r0 / address of vector
mov r0,(r1)
jmp *(ipc)+
/ switch
.globl z
z: mov (ipc),ipc / go to switch table
mov -2(isp),r0 / switch value from stack
mov (ipc)+,r1 / number of cases
1: cmp r0,(ipc)+ / check case
beq 1f
tst (ipc)+ / skip label
dec r1
bne 1b
jmp *(ipc)+ / default
1: mov (ipc),ipc / case found
jmp *(ipc)+
.globl n1,n2,n3
/ mark
n2: mov isp,-(sp) / remember isp for function call
tst (isp)+ / slot for return address
jmp *(ipc)+
/ call
n3: mov (sp)+,isp / pop isp from sp
/ mcall
n1: mov ipc,(isp) / save return address
mov -(isp),ipc / jump to address on stack
mov idp,(isp) / replace by old frame pointer
mov isp,idp / setup new frame pointer
jmp *(ipc)+
/ index vector
.globl n4
n4: mov -(isp),r1 / vector address
add -(isp),r1 / add offset
asl r1 / to byte address
mov (r1),(isp)+ / get value
jmp *(ipc)+
/ goto
.globl n6
n6: mov -2(isp),ipc
jmp *(ipc)+
/ return with value
.globl n7
n7: mov -(isp),r0 / pop return value from stack
mov idp,isp / restore old stack
mov (isp),idp / restore old frame
mov r0,(isp)+ / push return value
mov (isp),ipc / jump to return address
jmp *(ipc)+
/ return without value
.globl n11
n11: mov idp,isp / restore old stack
mov (isp)+,idp / restore old frame
mov (isp),ipc / jump to return address
jmp *(ipc)+
/ push automatic lvalue
.globl va, iva
iva: tst -(isp)
va: mov idp,r1 / frame
add (ipc)+,r1 / offset
asr r1 / to word address
mov r1,(isp)+ / push it
jmp *(ipc)+
/ push automatic rvalue
.globl a, ia
ia: tst -(isp)
a: mov idp,r1 / frame
add (ipc)+,r1 / offset
mov (r1),(isp)+ / push value
jmp *(ipc)+
/ push constant
.globl c, ic
ic: mov (ipc)+,-2(isp)
jmp *(ipc)+
c: mov (ipc)+,(isp)+
jmp *(ipc)+
/ push external lvalue
.globl vx, ivx
ivx: tst -(isp)
vx: mov (ipc)+,r1
asr r1 / to word address
mov r1,(isp)+ / push it
jmp *(ipc)+
/ push external rvalue
.globl x, ix
ix: mov *(ipc)+,-2(isp)
jmp *(ipc)+
x: mov *(ipc)+,(isp)+
jmp *(ipc)+
/ Unary operators
/ - operator
.globl u2
u2: neg -2(isp)
jmp *(ipc)+
/ * operator
.globl u3
u3: mov -(isp),r1
asl r1 / to byte address
mov (r1),(isp)+ / push rvalue
jmp *(ipc)+
/ ! operator
.globl u4
u4: tst -(isp)
beq 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ prefix ++ operator
.globl u5
u5: mov -(isp),r1
asl r1
inc (r1)
mov (r1),(isp)+
jmp *(ipc)+
/ prefix -- operator
.globl u6
u6: mov -(isp),r1
asl r1
dec (r1)
mov (r1),(isp)+
jmp *(ipc)+
/ postfix ++ operator
.globl u7
u7: mov -(isp),r1
asl r1
mov (r1),(isp)+
inc (r1)
jmp *(ipc)+
/ postfix -- operator
.globl u10
u10: mov -(isp),r1
asl r1
mov (r1),(isp)+
dec (r1)
jmp *(ipc)+
/ Binary operators
/ = operator
.globl b1
b1: mov -(isp),r0 / value
mov -(isp),r1
asl r1 / address
mov r0,(r1)
mov r0,(isp)+
jmp *(ipc)+
/ | operator
.globl b2
b2: bis -(isp),-2(isp)
jmp *(ipc)+
/ & operator
.globl b3
b3: mov -(isp),r0
com r0
bic r0,-2(isp)
jmp *(ipc)+
/ == operator
.globl b4
b4: cmp -(isp),-(isp)
beq 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ != operator
.globl b5
b5: cmp -(isp),-(isp)
bne 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ <= operator
.globl b6
b6: cmp -(isp),-(isp)
bge 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ < operator
.globl b7
b7: cmp -(isp),-(isp)
bgt 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ >= operator
.globl b10
b10: cmp -(isp),-(isp)
ble 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ > operator
.globl b11
b11: cmp -(isp),-(isp)
blt 1f
clr (isp)+
jmp *(ipc)+
1: mov $1,(isp)+
jmp *(ipc)+
/ >> operator
.globl b12
b12: mov -(isp),r2 / shift amount
mov -(isp),r1 / word
clr r0
neg r2 / right shift
ashc r2,r0
mov r1,(isp)+
jmp *(ipc)+
/ << operator
.globl b13
b13: mov -(isp),r2 / shift amount
mov -(isp),r1 / word
clr r0
ashc r2,r0
mov r1,(isp)+
jmp *(ipc)+
/ + operator
.globl b14
b14: add -(isp),-2(isp)
jmp *(ipc)+
/ - operator
.globl b15
b15: sub -(isp),-2(isp)
jmp *(ipc)+
/ % operator
.globl b16
b16: mov -(isp),r2 / divisor
mov -(isp),r1 / dividend
clr r0
div r2,r0
mov r1,(isp)+
jmp *(ipc)+
/ * operator
.globl b17
b17: mov -(isp),r2 / multiplier
mov -(isp),r1 / multiplicand
mul r2,r1
mov r1,(isp)+
jmp *(ipc)+
/ / operator
.globl b20
b20: mov -(isp),r2 / divisor
mov -(isp),r1 / dividend
clr r0
div r2,r0
mov r0,(isp)+
jmp *(ipc)+
/ =| operator
.globl b102
b102: mov -(isp),r0 / rvalue
mov -(isp),r1
asl r1 / lvalue
bis r0,(r1)
mov (r1),(isp)+
jmp *(ipc)+
/ =& operator
.globl b103
b103: mov -(isp),r0 / rvalue
mov -(isp),r1
asl r1 / lvalue
com r0
bic r0,(r1)
mov (r1),(isp)+
jmp *(ipc)+
/ =>> operator
.globl b112
b112: mov -(isp),r2 / rvalue
mov -(isp),r1
asl r1 / lvalue
mov r1,-(sp)
mov (r1),r1
clr r0
neg r2 / right shift
ashc r2,r0
mov r1,*(sp)+
mov r1,(isp)+
jmp *(ipc)+
/ =<< operator
.globl b113
b113: mov -(isp),r2 / rvalue
mov -(isp),r1
asl r1 / lvalue
mov r1,-(sp)
mov (r1),r1
clr r0
ashc r2,r0
mov r1,*(sp)+
mov r1,(isp)+
jmp *(ipc)+
/ =+ operator
.globl b114
b114: mov -(isp),r0 / rvalue
mov -(isp),r1
asl r1 / lvalue
add r0,(r1)
mov (r1),(isp)+
jmp *(ipc)+
/ =- operator
.globl b115
b115: mov -(isp),r0 / rvalue
mov -(isp),r1
asl r1 / lvalue
sub r0,(r1)
mov (r1),(isp)+
jmp *(ipc)+
/ =% operator
.globl b116
b116: mov -(isp),r2 / rvalue
mov -(isp),r1
asl r1 / lvalue
mov r1,-(sp)
mov (r1),r1
clr r0
div r2,r0
mov r1,*(sp)+
mov r1,(isp)+
jmp *(ipc)+
/ =* operator
.globl b117
b117: mov -(isp),r2 / rvalue
mov -(isp),r0
asl r0 / lvalue
mov r0,-(sp)
mov (r0),r0
clr r1
mul r2,r0
mov r1,*(sp)+
mov r1,(isp)+
jmp *(ipc)+
/ =/ operator
.globl b120
b120: mov -(isp),r2 / rvalue
mov -(isp),r1
asl r1 / lvalue
mov r1,-(sp)
mov (r1),r1
clr r0
div r2,r0
mov r0,*(sp)+
mov r0,(isp)+
jmp *(ipc)+
|
aap/b
| 2,546
|
pdp11/libb.s
|
ipc = r3
idp = r4
isp = r5
.globl exit
exit: sys 1.
read: sys 3.
br sysret
write: sys 4.
br sysret
open: sys 5.
br sysret
close: sys 6.
br sysret
lseek: sys 19.
br sysret
sysret: bcc 1f
mov $-1,r0
1: rts pc
.globl _putchar
.data
_putchar: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,ch / get character
tstb ch+1 / check if one or two chars
beq 1f / one char
/ swab ch / sure about swab here?
mov $2,-(sp)
br 2f
1: mov $1,-(sp)
2: mov $ch,-(sp)
mov _fout,-(sp) / fd
jsr pc,write
add $6,sp
jmp n7
.globl _getchar
.data
_getchar: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov $1,-(sp)
mov $ch2,-(sp)
mov _fin,-(sp)
jsr pc,read
add $6,sp
tst r0
bne 1f
clr ch2
1: mov ch2,(isp)+
jmp n7
.data
ch: 0
ch2: 0
.globl _fin, _fout, _ferr
_fin: 0
_fout: 1
_ferr: 2
.text
.globl _char
.data
_char: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r1 / string
asl r1
add (isp),r1 / add index
movb (r1),r0 / get char
mov r0,(isp)+
jmp n7
.globl _lchar
.data
_lchar: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r0 / string
asl r0
add (isp)+,r0 / add index
mov (isp)+,r1 / char
movb r1,(r0) / get char
jmp n7
.globl _open
.data
_open: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r0 / name
asl r0
mov (isp)+,r1 / flags
mov (isp),-(sp) / mode
mov r1,-(sp)
mov r0,-(sp)
jsr pc,open
add $6,sp
mov r0,(isp)+
jmp n7
.globl _creat
.data
_creat: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r0 / name
asl r0
mov (isp),-(sp) / mode
mov $3001,-(sp) / O_CREAT | O_TRUNC | O_WRONLY
mov r0,-(sp)
jsr pc,open
add $6,sp
mov r0,(isp)+
jmp n7
.globl _close
.data
_close: 1f
.text
1: 1f
1: mov 4(idp),-(sp) / fd
jsr pc,close
tst (sp)+
jmp n11
.globl _seek
.data
_seek: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r0 / fd
mov (isp)+,r1 / offset
mov (isp),-(sp) / whence
mov r1,-(sp)
clr -(sp) / offset high word
mov r0,-(sp)
jsr pc,lseek
add $8.,sp
mov r0,(isp)+
jmp n7
.globl _write
.data
_write: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r0 / fd
mov (isp)+,r1 / buf
asl r1
mov (isp),-(sp) / count
mov r1,-(sp)
mov r0,-(sp)
jsr pc,write
add $6,sp
mov r0,(isp)+
jmp n7
.globl _read
.data
_read: 1f
.text
1: 1f
1: mov idp,isp
cmp (isp)+,(isp)+
mov (isp)+,r0 / fd
mov (isp)+,r1 / buf
asl r1
mov (isp),-(sp) / count
mov r1,-(sp)
mov r0,-(sp)
jsr pc,read
add $6,sp
mov r0,(isp)+
jmp n7
.globl _exit
.data
_exit: 1f
.text
1: 1f
1: mov 4(idp),-(sp)
jsr pc,exit
|
aap/b
| 2,205
|
riscv64/libb.S
|
#define idp s0
#define isp s1
#define ipc s2
# to adjust stack, addiu isp,(2+nargs)*8,
# (2+1)*8 if no args but returns value
.globl _putchar
.data
_putchar: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,24
ld t0,16(idp) # chars
la a1,ch
sd t0,(a1)
move a2,zero # num chars
1: beq t0,zero,1f
srli t0,t0,8
addi a2,a2,1
j 1b
1: ld a0,_fout
call write@plt
sd a0,-8(isp)
j n7
.globl _getchar
.data
_getchar: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,24
ld a0,_fin
la a1,ch
li a2,1
call read@plt
li t0,1
move t1,zero
bne a0,t0,1f
lb t1,ch
1: sd t1,-8(isp)
j n7
.data
ch: .dword 0
.dword 0
.globl _fin, _fout, _ferr
_fin: .dword 0
_fout: .dword 1
_ferr: .dword 2
.text
.globl _char
.data
_char: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,32
ld t6,16(idp) # string
slli t6,t6,3
ld t0,24(idp) # offset
add t6,t6,t0
lb t1,(t6)
sd t1,-8(isp)
j n7
.globl _lchar
.data
_lchar: .dword 1f
.text
1: .dword 1f
1: ld t6,16(idp) # string
slli t6,t6,3
ld t0,24(idp) # offet
add t6,t6,t0
ld t1,32(idp) # char
sb t1,(t6)
j n11
.globl _open
.data
_open: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,40
ld a0,16(idp) # path
ld a1,24(idp) # flags
ld a2,32(idp) # mode
slli a0,a0,3
call open@plt
sd a0,-8(isp)
j n7
.globl _creat
.data
_creat: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,32
ld a0,16(idp) # path
li a1,01101 # flags, O_CREAT, O_TRUNC, O_WRONLY
ld a2,24(idp) # mode
slli a0,a0,3
call open@plt
sd a0,-8(isp)
j n7
.globl _close
.data
_close: .dword 1f
.text
1: .dword 1f
1: ld a0,16(idp)
call close@plt
j n11
.globl _seek
.data
_seek: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,40
ld a0,16(idp) # fd
ld a1,24(idp) # off
ld a2,32(idp) # whence
call lseek@plt
sd a0,-8(isp)
j n7
.globl _write
.data
_write: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,40
ld a0,16(idp) # fd
ld a1,24(idp) # buf
ld a2,32(idp) # count
slli a1,a1,3
call write@plt
sd a0,-8(isp)
j n7
.globl _read
.data
_read: .dword 1f
.text
1: .dword 1f
1: addi isp,isp,40
ld a0,16(idp) # fd
ld a1,24(idp) # buf
ld a2,32(idp) # count
slli a1,a1,3
call read@plt
sd a0,-8(isp)
j n7
.globl _exit
.data
_exit: .dword 1f
1: .dword 1f
.text
1: ld a0,16(isp)
call exit@plt
|
aap/b
| 1,317
|
riscv64/brt1.S
|
#define idp s0
#define isp s1
#define ipc s2
.macro FETCH skip=0
ld t0,\skip(ipc)
addi ipc,ipc,8+\skip
jr t0
.endm
stacksz = 1000
.data
.globl _argv
_argv: .dword 0
.bss
.align 3
stack: .space 8*stacksz
.text
.globl main, fetch
main:
la isp,stack
move idp,isp
la ipc,init
# B argc
sd a0,16(idp)
# argv, have to make a B vector out of this, urgh
slli t0,a0,3
sub sp,sp,t0
# B argv
srli t0,sp,3
sd t0,24(idp)
# add argc as element 0 for external argv
sd a0,-8(sp)
addi sp,sp,-8
la t1,_argv
srli t0,sp,3
sd t0,(t1)
# copy arguments to stack with word alignment
# NB: the last word can have junk bytes after the NUL
addi t6,sp,8
1: beq a0,zero,1f
addi a0,a0,-1
# count string
ld t5,(a1)
li t4,7
2: lb t1,(t5)
addi t4,t4,1
beq t1,zero,2f
addi t5,t5,1
j 2b
2: li t1,~7
and t4,t4,t1
# make space for string and copy it
sub sp,sp,t4
move t0,sp
ld t5,(a1)
2: beq t4,zero,2f
addi t4,t4,-1
lb t1,(t5)
sb t1,(t0)
addi t0,t0,1
addi t5,t5,1
j 2b
2: srli t0,sp,3
sd t0,(t6)
addi a1,a1,8
addi t6,t6,8
j 1b
1:
jal t6,startchain
fetch: #FETCH
ld t0,(ipc)
addi ipc,ipc,8
jr t0
init:
.dword x, _main
.dword n1, 1f
1: ld a0,-8(isp)
call exit@plt
.globl chain
chain:
ld t0,(ra)
addi ra,ra,8
beq t0,zero,1f
ld t1,(t0)
srli t1,t1,3
sd t1,(t0)
j chain
1: jr ra
startchain:
|
aap/b
| 6,187
|
riscv64/bilib.S
|
#define idp s0
#define isp s1
#define ipc s2
.macro FETCH skip=0
ld t0,\skip(ipc)
addi ipc,ipc,8+\skip
jr t0
.endm
.extern fetch
# set stack
.globl s
s:
ld isp,(ipc)
add isp,isp,idp
FETCH 8
# transfer if false
.globl f
f:
ld t0,-8(isp)
beq t0,zero,t
FETCH 8
# transfer
.globl t
t:
ld ipc,(ipc)
FETCH
# init automatic vector
.globl y
y:
ld t6,(ipc)
add t6,t6,idp
addi t0,t6,8
srli t0,t0,3
sd t0,(t6)
FETCH 8
# switch
.globl z
z: ld t6,(ipc)
ld t0,-8(isp)
ld t1,(t6)
addi t6,t6,8
1: beq t1,zero,2f
ld t2,(t6)
beq t2,t0,1f
addi t1,t1,-1
addi t6,t6,16
j 1b
1: ld ipc,8(t6) # found case
FETCH
2: move ipc,t6 # fall through
FETCH
.globl n1,n2,n3
# call
n3:
ld isp,(sp)
addi sp,sp,8
# mcall
n1:
sd ipc,(isp)
addi isp,isp,-8
ld ipc,(isp)
sd idp,(isp)
move idp,isp
FETCH
# mark
n2:
sd isp,-8(sp)
addi sp,sp,-8
addi isp,isp,8
FETCH
# index vector
.globl n4
n4:
ld t0,-8(isp)
ld t1,-16(isp)
addi isp,isp,-8
add t6,t0,t1
slli t6,t6,3
ld t0,(t6)
sd t0,-8(isp)
FETCH
# goto
.globl n6
n6:
ld ipc,-8(isp)
FETCH
# return with value
.globl n7
n7:
ld t0,-8(isp)
addi isp,idp,8
ld idp,(idp)
sd t0,-8(isp)
ld ipc,(isp)
FETCH
# return without value
.globl n11
n11:
addi isp,idp,8
ld idp,(idp)
ld ipc,(isp)
FETCH
#
# Push values
#
# push automatic lvalue
.globl va, iva
va: addi isp,isp,8
iva: ld t6,(ipc)
add t6,t6,idp
srli t0,t6,3
sd t0,-8(isp)
FETCH 8
# push automatic rvalue
.globl a, ia
a: addi isp,isp,8
ia: ld t6,(ipc)
add t6,t6,idp
ld t0,(t6)
sd t0,-8(isp)
FETCH 8
# push constant
.globl c, ic
c: addi isp,isp,8
ic: ld t0,(ipc)
sd t0,-8(isp)
FETCH 8
# push external lvalue
.globl vx, ivx
vx: addi isp,isp,8
ivx: ld t6,(ipc)
srli t0,t6,3
sd t0,-8(isp)
FETCH 8
# push external rvalue
.globl x, ix
x: addi isp,isp,8
ix: ld t6,(ipc)
ld t0,(t6)
sd t0,-8(isp)
FETCH 8
#
# Unary operators
#
# - operator
.globl u2
u2:
ld t0,-8(isp)
sub t0,zero,t0
sd t0,-8(isp)
FETCH
# * operator
.globl u3
u3:
ld t6,-8(isp)
slli t6,t6,3
ld t0,(t6)
sd t0,-8(isp)
FETCH
# ! operator
.globl u4
u4:
ld t0,-8(isp)
beq t0,zero,1f
sd zero,-8(isp)
FETCH
1: li t0,1
sd t0,-8(isp)
FETCH
# prefix ++ operator
.globl u5
u5:
ld t6,-8(isp)
slli t6,t6,3
ld t0,(t6)
addi t0,t0,1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# prefix -- operator
.globl u6
u6:
ld t6,-8(isp)
slli t6,t6,3
ld t0,(t6)
addi t0,t0,-1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# postfix ++ operator
.globl u7
u7:
ld t6,-8(isp)
slli t6,t6,3
ld t0,(t6)
sd t0,-8(isp)
addi t0,t0,1
sd t0,(t6)
FETCH
# postfix -- operator
.globl u10
u10:
ld t6,-8(isp)
slli t6,t6,3
ld t0,(t6)
sd t0,-8(isp)
addi t0,t0,-1
sd t0,(t6)
FETCH
#
# Binary operators
#
# = operator
.globl b1
b1:
ld t0,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
sd t0,(t6)
sd t0,-8(isp)
FETCH
# | operator
.globl b2
b2:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
or t0,t0,t1
sd t0,-8(isp)
FETCH
# & operator
.globl b3
b3:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
and t0,t0,t1
sd t0,-8(isp)
FETCH
# == operator
.globl b4
b4:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
beq t0,t1,1f
sd zero,-8(isp)
FETCH
1:
li t0,1
sd t0,-8(isp)
FETCH
# != operator
.globl b5
b5:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
bne t0,t1,1f
sd zero,-8(isp)
FETCH
1:
li t0,1
sd t0,-8(isp)
FETCH
# <= operator
.globl b6
b6:
ld t1,-8(isp)
ld t0,-16(isp)
slt t0,t1,t0
xori t0,t0,1
addi isp,isp,-8
sd t0,-8(isp)
FETCH
# < operator
.globl b7
b7:
ld t1,-8(isp)
ld t0,-16(isp)
slt t0,t0,t1
addi isp,isp,-8
sd t0,-8(isp)
FETCH
# >= operator
.globl b10
b10:
ld t1,-8(isp)
ld t0,-16(isp)
slt t0,t0,t1
xori t0,t0,1
addi isp,isp,-8
sd t0,-8(isp)
FETCH
# > operator
.globl b11
b11:
ld t1,-8(isp)
ld t0,-16(isp)
slt t0,t1,t0
addi isp,isp,-8
sd t0,-8(isp)
FETCH
# >> operator
.globl b12
b12:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
sra t0,t0,t1
sd t0,-8(isp)
FETCH
# << operator
.globl b13
b13:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
sll t0,t0,t1
sd t0,-8(isp)
FETCH
# + operator
.globl b14
b14:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
add t0,t0,t1
sd t0,-8(isp)
FETCH
# - operator
.globl b15
b15:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
sub t0,t0,t1
sd t0,-8(isp)
FETCH
# % operator
.globl b16
b16:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
rem t0,t0,t1
sd t0,-8(isp)
FETCH
# * operator
.globl b17
b17:
ld t1,-8(isp)
ld t0,-16(isp)
addi isp,isp,-8
mul t0,t0,t1
sd t0,-8(isp)
FETCH
# / operator
.globl b20
b20:
ld t1,-8(isp)
ld t0,-16(isp)
div t0,t0,t1
addi isp,isp,-8
sd t0,-8(isp)
FETCH
# =| operator
.globl b102
b102:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-4
slli t6,t6,3
ld t0,(t6)
or t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =& operator
.globl b103
b103:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
and t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =>> operator
.globl b112
b112:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-4
slli t6,t6,3
ld t0,(t6)
sra t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =<< operator
.globl b113
b113:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
sll t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =+ operator
.globl b114
b114:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
add t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =- operator
.globl b115
b115:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
sub t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =% operator
.globl b116
b116:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
rem t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =* operator
.globl b117
b117:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
mul t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
# =/ operator
.globl b120
b120:
ld t1,-8(isp) # value
ld t6,-16(isp) # address
addi isp,isp,-8
slli t6,t6,3
ld t0,(t6)
div t0,t0,t1
sd t0,(t6)
sd t0,-8(isp)
FETCH
|
aap/b
| 5,831
|
amd64/bilib.s
|
.set dp, %r13
.set sp, %r14
.set pc, %r15
.macro FETCH skip=0
add $8+\skip, pc
jmp *-8(pc)
.endm
.extern fetch
# set stack
.globl s
s:
mov dp,sp
add (pc),sp
FETCH 8
# transfer if false
.globl f
f:
cmpq $0,-8(sp)
jz t
FETCH 8
# transfer
.globl t
t:
mov (pc),pc
FETCH
# init automatic vector
.globl y
y:
mov dp,%rax
add (pc),%rax
lea 8(%rax),%rbx
shr $3,%rbx
mov %rbx,(%rax)
FETCH 8
# switch
.globl z
z:
mov (pc),%rsi
mov -8(sp),%rbx
lodsq
mov %rax,%rcx
1: lodsq
cmp %rax,%rbx
je 2f
add $8, %rsi
dec %rcx
jnz 1b
lea 8(%rsi), pc # manually inlined FETCH
jmp *(%rsi)
2: mov (%rsi),pc
FETCH
.globl n1,n2,n3
# call
n3:
pop sp
# mcall
n1:
mov pc,(sp)
sub $8,sp
mov (sp),pc
mov dp,(sp)
mov sp,dp
FETCH
# mark
n2: push sp
add $8,sp
FETCH
# index vector
.globl n4
n4:
mov -8(sp),%rax
add -16(sp),%rax
sub $8,sp
mov (,%rax,8),%rax
mov %rax,-8(sp)
FETCH
# goto
.globl n6
n6:
mov -8(sp),pc
FETCH
# return with value
.globl n7
n7:
mov -8(sp),%rax
mov dp,sp
mov (sp),dp
mov %rax,(sp)
add $8,sp
mov (sp),pc
FETCH
# return without value
.globl n11
n11:
mov dp,sp
mov (sp),dp
add $8,sp
mov (sp),pc
FETCH
#
# Push values
#
# push automatic lvalue
.globl va, iva
va: add $8,sp
iva: mov dp,%rax
add (pc),%rax
shr $3,%rax
mov %rax,-8(sp)
FETCH 8
# push automatic rvalue
.globl a, ia
a: add $8,sp
ia: mov dp,%rax
add (pc),%rax
mov (%rax),%rax
mov %rax,-8(sp)
FETCH 8
# push constant
.globl c, ic
c: add $8,sp
ic: mov (pc),%rax
mov %rax,-8(sp)
FETCH 8
# push external lvalue
.globl vx, ivx
vx: add $8,sp
ivx: mov (pc),%rax
shr $3,%rax
mov %rax,-8(sp)
FETCH 8
# push external rvalue
.globl x, ix
x: add $8,sp
ix: mov (pc),%rax
mov (%rax),%rax
mov %rax,-8(sp)
FETCH 8
#
# Unary operators
#
# - operator
.globl u2
u2:
negq -8(sp)
FETCH
# * operator
.globl u3
u3:
mov -8(sp),%rax
mov (,%rax,8),%rax
mov %rax,-8(sp)
FETCH
# ! operator
.globl u4
u4:
xor %rax,%rax
cmpq %rax,-8(sp)
setz %al
mov %rax,-8(sp)
FETCH
# prefix ++ operator
.globl u5
u5:
mov -8(sp),%rax
shl $3,%rax
mov (%rax),%rdx
inc %rdx
mov %rdx,(%rax)
mov %rdx,-8(sp)
FETCH
# prefix -- operator
.globl u6
u6:
mov -8(sp),%rax
shl $3,%rax
mov (%rax),%rdx
dec %rdx
mov %rdx,(%rax)
mov %rdx,-8(sp)
FETCH
# postfix ++ operator
.globl u7
u7:
mov -8(sp),%rax
shl $3,%rax
mov (%rax),%rdx
mov %rdx,-8(sp)
inc %rdx
mov %rdx,(%rax)
FETCH
# postfix -- operator
.globl u10
u10:
mov -8(sp),%rax
shl $3,%rax
mov (%rax),%rdx
mov %rdx,-8(sp)
dec %rdx
mov %rdx,(%rax)
FETCH
#
# Binary operators
#
# = operator
.globl b1
b1:
mov -8(sp),%rax # value
mov -16(sp),%rbx # address
sub $8,sp
mov %rax,(,%rbx,8)
mov %rax,-8(sp)
FETCH
# | operator
.globl b2
b2:
mov -8(sp),%rax
or %rax,-16(sp)
sub $8,sp
FETCH
# & operator
.globl b3
b3:
mov -8(sp),%rax
and %rax,-16(sp)
sub $8,sp
FETCH
# == operator
.globl b4
b4:
xor %rax,%rax
mov -8(sp),%rdx
cmp -16(sp),%rdx
sete %al
sub $8,sp
mov %rax,-8(sp)
FETCH
# != operator
.globl b5
b5:
xor %rax,%rax
mov -8(sp),%rdx
cmp -16(sp),%rdx
setne %al
sub $8,sp
mov %rax,-8(sp)
FETCH
# <= operator
.globl b6
b6:
xor %rax,%rax
mov -16(sp),%rdx
cmp -8(sp),%rdx
setle %al
sub $8,sp
mov %rax,-8(sp)
FETCH
# < operator
.globl b7
b7:
xor %rax,%rax
mov -16(sp),%rdx
cmp -8(sp),%rdx
setl %al
sub $8,sp
mov %rax,-8(sp)
FETCH
# >= operator
.globl b10
b10:
xor %rax,%rax
mov -16(sp),%rdx
cmp -8(sp),%rdx
setge %al
sub $8,sp
mov %rax,-8(sp)
FETCH
# > operator
.globl b11
b11:
xor %rax,%rax
mov -16(sp),%rdx
cmp -8(sp),%rdx
setg %al
sub $8,sp
mov %rax,-8(sp)
FETCH
# >> operator
.globl b12
b12:
mov -16(sp),%rax
mov -8(sp),%ecx
shr %cl,%rax
sub $8,sp
mov %rax,-8(sp)
FETCH
# << operator
.globl b13
b13:
mov -16(sp),%rax
mov -8(sp),%ecx
shl %cl,%rax
sub $8,sp
mov %rax,-8(sp)
FETCH
# + operator
.globl b14
b14:
mov -8(sp),%rax
add %rax, -16(sp)
sub $8,sp
FETCH
# - operator
.globl b15
b15:
mov -8(sp),%rax
sub %rax, -16(sp)
sub $8,sp
FETCH
# % operator
.globl b16
b16:
mov -16(sp),%rax
cqto
idivq -8(sp)
sub $8,sp
mov %rdx,-8(sp)
FETCH
# * operator
.globl b17
b17:
mov -8(sp),%rax
imul -16(sp), %rax
sub $8,sp
mov %rax, -8(sp)
FETCH
# / operator
.globl b20
b20:
mov -16(sp),%rax
cqto
idivq -8(sp)
sub $8,sp
mov %rax,-8(sp)
FETCH
# =| operator
.globl b102
b102:
mov -8(sp),%rax # value
mov -16(sp),%rbx # address
sub $8,sp
shl $3,%rbx
or (%rbx),%rax
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
# =& operator
.globl b103
b103:
mov -8(sp),%rax # value
mov -16(sp),%rbx # address
sub $8,sp
shl $3,%rbx
and (%rbx),%rax
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
# =>> operator
.globl b112
b112:
mov -8(sp),%ecx # value
mov -16(sp),%rbx # address
sub $8,sp
shl $3,%rbx
mov (%rbx),%rax
shr %cl,%rax
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
# =<< operator
.globl b113
b113:
mov -8(sp),%ecx # value
mov -16(sp),%rbx # address
sub $8,sp
shl $3,%rbx
mov (%rbx),%rax
shl %cl,%rax
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
# =+ operator
.globl b114
b114:
mov -8(sp),%rax # value
mov -16(sp),%rbx # address
sub $8,sp
shl $3,%rbx
add (%rbx),%rax
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
# =- operator
.globl b115
b115:
mov -8(sp),%rax # value
mov -16(sp),%rbx # address
sub $8,sp
shl $3,%rbx
sub %rax,(%rbx)
mov (%rbx),%rax
mov %rax,-8(sp)
FETCH
# =% operator
.globl b116
b116:
mov -16(sp),%rbx # address
shl $3,%rbx
mov (%rbx),%rax
cqto
idivq -8(sp)
sub $8,sp
mov %rdx,(%rbx)
mov %rdx,-8(sp)
FETCH
# =* operator
.globl b117
b117:
mov -16(sp),%rbx # address
shl $3,%rbx
mov (%rbx),%rax
imul -8(sp), %rax
sub $8,sp
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
# =/ operator
.globl b120
b120:
mov -16(sp),%rbx # address
shl $3,%rbx
mov (%rbx),%rax
cqto
idivq -8(sp)
sub $8,sp
mov %rax,(%rbx)
mov %rax,-8(sp)
FETCH
|
aap/b
| 2,174
|
amd64/libb.s
|
.set dp, %r13
.set sp, %r14
.set pc, %r15
.set a0, %rdi
.set a1, %rsi
.set a2, %rdx
.set a4, %rcx
.set a5, %r8
.set a6, %r9
.globl _putchar
.data
_putchar: .quad 1f
.text
1: .quad 1f
1: mov 16(sp),%rax
mov _fout(%rip),a0
lea ch(%rip),a1
mov %rax,(a1)
xor a2,a2
1: cmpb $0,(a1,a2,1)
je 1f
inc a2
jmp 1b
1: call write
jmp n11
.globl _getchar
.data
_getchar: .quad 1f
.text
1: .quad 1f
1: add $24,sp
mov _fin(%rip),a0
lea ch(%rip),a1
mov $1,a2
call read
cmp $1,%eax
jne 1f
movzbl ch(%rip),%eax
mov %rax,-8(sp)
jmp n7
1: movq $0,-8(sp)
jmp n7
.data
ch: .quad 0
.quad 0
.globl _fin, _fout, _ferr
_fin: .quad 0
_fout: .quad 1
_ferr: .quad 2
.text
.globl _char
.data
_char: .quad 1f
.text
1: .quad 1f
1: add $24,sp
mov 16(dp),%rax # string
mov 24(dp),%rcx # offset
xor %rdx,%rdx
movzbl (%rcx,%rax,8),%edx # load
mov %rdx,-8(sp)
jmp n7
.globl _lchar
.data
_lchar: .quad 1f
.text
1: .quad 1f
1: mov 16(dp),%rax # string
mov 24(dp),%rcx # offset
movzbl 32(dp),%edx # char
movb %dl,(%rcx,%rax,8) # store
jmp n11
.globl _open
.data
_open: .quad 1f
.text
1: .quad 1f
1: add $40,sp
mov 16(dp),a0 # path
shl $3,a0
mov 24(dp),a1 # flags
mov 32(dp),a2 # mode
call open
movslq %eax,%rax
mov %rax,-8(sp)
jmp n7
.globl _creat
.data
_creat: .quad 1f
.text
1: .quad 1f
1: add $32,sp
mov 16(dp),a0 # path
shl $3,a0
mov $01101,a1 # flags, O_CREAT, O_TRUNC, O_WRONLY
mov 24(dp),a2 # mode
call open
movslq %eax,%rax
mov %rax,-8(sp)
jmp n7
.globl _close
.data
_close: .quad 1f
.text
1: .quad 1f
1: mov 16(dp),a0
call close
jmp n11
.globl _seek
.data
_seek: .quad 1f
.text
1: .quad 1f
1: add $40,sp
mov 16(dp),a0 # fd
mov 24(dp),a1 # off
mov 32(dp),a2 # whence
call lseek
mov %rax,-8(sp)
jmp n7
.globl _write
.data
_write: .quad 1f
.text
1: .quad 1f
1: add $40,sp
mov 16(dp),a0 # fd
mov 24(dp),a1 # buf
shl $3,a1
mov 32(dp),a2 # count
call write
mov %rax,-8(sp)
jmp n7
.globl _read
.data
_read: .quad 1f
.text
1: .quad 1f
1: add $40,sp
mov 16(dp),a0 # fd
mov 24(dp),a1 # buf
shl $3,a1
mov 32(dp),a2 # count
call read
mov %rax,-8(sp)
jmp n7
.globl _exit
.data
_exit: .quad 1f
1: .quad 1f
.text
1: mov 16(dp),a0
call exit
|
aap/b
| 1,442
|
amd64/brt1.s
|
.set dp, %r13
.set sp, %r14
.set pc, %r15
.macro FETCH skip=0
add $8+\skip, pc
jmp *-8(pc)
.endm
stacksz = 1000
.data
.globl _argv
_argv: .quad 0
.bss
.align 8
stack: .space 8*stacksz
.text
.globl main, fetch
main:
lea stack(%rip),sp
mov sp,dp
lea init(%rip),pc
mov %rdi,%r11 # argc
mov %rsi,%r12 # argv
# B argc at 16(sp)
movq %r11,16(sp)
# argv, have to make a B vector out of this, urgh
lea (,%r11,8),%rax
sub %rax,%rsp # make space for argv array
# B argv at 24(sp)
mov %rsp,%rbx
shr $3,%rbx
mov %rbx,24(sp)
# add argc as element 0 for external argv
push %r11
mov %rsp,%rbx
shr $3,%rbx
mov %rbx,_argv
# copy arguments to stack with word alignment
# NB: the last word can have junk bytes after the NUL
lea 8(%rsp),%rbx
1:
test %r11,%r11
jz 1f # end of array
# count string
mov $-7,%rcx
mov (%r12),%rdi # argv[i]
xor %al,%al
repne scasb # find end
# rcx is -(len+7) (including NUL) now
neg %rcx
and $-8,%rcx # aligned to qwords
sub %rcx,%rsp # make space for it
# copy string
shr $3,%rcx
mov (%r12),%rsi
add $8,%r12
mov %rsp,%rdi
rep movsq
# store pointer in argv array
mov %rsp,%rax
shr $3,%rax
mov %rax,(%rbx)
add $8,%rbx
dec %r11
jmp 1b
1:
call startchain
fetch:
FETCH
init:
.quad x, _main
.quad n1, 1f
1: mov -8(sp),%rdi
call exit
.globl chain
chain:
pop %rsi
1: lodsq
test %rax,%rax
jz 1f
mov (%rax),%rdx
shr $3,%rdx
mov %rdx,(%rax)
jmp 1b
1: jmp *%rsi
startchain:
|
aap/b
| 6,362
|
mips32/bilib.s
|
.set idp,$s0
.set isp,$s1
.set ipc,$s2
.set noreorder
.macro FETCH skip=0
lw $v0,\skip(ipc)
jr $v0
addiu ipc,4+\skip
.endm
.extern fetch
# set stack
.globl s
s:
lw isp,(ipc)
addu isp,idp
FETCH 4
# transfer if false
.globl f
f:
lw $t0,-4(isp)
beq $t0,$zero,t
nop
FETCH 4
# transfer
.globl t
t:
lw ipc,(ipc)
FETCH
# init automatic vector
.globl y
y:
lw $v0,(ipc)
addu $v1,$v0,idp
addiu $t0,$v1,4
srl $v0,$t0,2
sw $v0,($v1)
FETCH 4
# switch
.globl z
z: lw $v0,(ipc)
lw $t0,-4(isp)
lw $t1,($v0)
addiu $v0,4
1: beq $t1,$zero,2f
nop
lw $t2,($v0)
beq $t2,$t0,1f
addiu $t1,-1
b 1b
addiu $v0,8
1: lw ipc,4($v0) # found case
FETCH
2: move ipc,$v0 # fall through
FETCH
.globl n1,n2,n3
# call
n3:
lw isp,($sp)
addiu $sp,4
# mcall
n1:
sw ipc,(isp)
addiu isp,-4
lw ipc,(isp)
sw idp,(isp)
move idp,isp
FETCH
# mark
n2:
sw isp,-4($sp)
addiu $sp,-4
addiu isp,4
FETCH
# index vector
.globl n4
n4:
lw $t0,-4(isp)
lw $t1,-8(isp)
addiu isp,-4
addu $v0,$t0,$t1
sll $v0,$v0,2
lw $t0,($v0)
sw $t0,-4(isp)
FETCH
# goto
.globl n6
n6:
lw ipc,-4(isp)
FETCH
# return with value
.globl n7
n7:
lw $t0,-4(isp)
addiu isp,idp,4
lw idp,(idp)
sw $t0,-4(isp)
lw ipc,(isp)
FETCH
# return without value
.globl n11
n11:
addiu isp,idp,4
lw idp,(idp)
lw ipc,(isp)
FETCH
#
# Push values
#
# push automatic lvalue
.globl va, iva
va: addiu isp,4
iva: lw $v0,(ipc)
addu $v1,$v0,idp
srl $t0,$v1,2
sw $t0,-4(isp)
FETCH 4
# push automatic rvalue
.globl a, ia
a: addiu isp,4
ia: lw $v0,(ipc)
addu $v1,$v0,idp
lw $t0,($v1)
sw $t0,-4(isp)
FETCH 4
# push constant
.globl c, ic
c: addiu isp,4
ic: lw $t0,(ipc)
sw $t0,-4(isp)
FETCH 4
# push external lvalue
.globl vx, ivx
vx: addiu isp,4
ivx: lw $v0,(ipc)
srl $t0,$v0,2
sw $t0,-4(isp)
FETCH 4
# push external rvalue
.globl x, ix
x: addiu isp,4
ix: lw $v0,(ipc)
lw $t0,($v0)
sw $t0,-4(isp)
FETCH 4
#
# Unary operators
#
# - operator
.globl u2
u2:
lw $t0,-4(isp)
subu $t0,$zero,$t0
sw $t0,-4(isp)
FETCH
# * operator
.globl u3
u3:
lw $v0,-4(isp)
sll $v0,2
lw $t0,($v0)
sw $t0,-4(isp)
FETCH
# ! operator
.globl u4
u4:
lw $t0,-4(isp)
beq $t0,$zero,1f
li $t0,1
sw $zero,-4(isp)
FETCH
1: sw $t0,-4(isp)
FETCH
# prefix ++ operator
.globl u5
u5:
lw $v0,-4(isp)
sll $v0,$v0,2
lw $t0,($v0)
addiu $t0,$t0,1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# prefix -- operator
.globl u6
u6:
lw $v0,-4(isp)
sll $v0,$v0,2
lw $t0,($v0)
addiu $t0,$t0,-1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# postfix ++ operator
.globl u7
u7:
lw $v0,-4(isp)
sll $v0,$v0,2
lw $t0,($v0)
sw $t0,-4(isp)
addiu $t0,$t0,1
sw $t0,($v0)
FETCH
# postfix -- operator
.globl u10
u10:
lw $v0,-4(isp)
sll $v0,$v0,2
lw $t0,($v0)
sw $t0,-4(isp)
addiu $t0,$t0,-1
sw $t0,($v0)
FETCH
#
# Binary operators
#
# = operator
.globl b1
b1:
lw $t0,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# | operator
.globl b2
b2:
lw $t1,-4(isp)
lw $t0,-8(isp)
addiu isp,-4
or $t0,$t1
sw $t0,-4(isp)
FETCH
# & operator
.globl b3
b3:
lw $t1,-4(isp)
lw $t0,-8(isp)
addiu isp,-4
and $t0,$t1
sw $t0,-4(isp)
FETCH
# == operator
.globl b4
b4:
lw $t1,-4(isp)
lw $t0,-8(isp)
beq $t0,$t1,1f
addiu isp,-4
sw $zero,-4(isp)
FETCH
1:
li $t0,1
sw $t0,-4(isp)
FETCH
# != operator
.globl b5
b5:
lw $t1,-4(isp)
lw $t0,-8(isp)
bne $t0,$t1,1f
addiu isp,-4
sw $zero,-4(isp)
FETCH
1:
li $t0,1
sw $t0,-4(isp)
FETCH
# <= operator
.globl b6
b6:
lw $t1,-4(isp)
lw $t0,-8(isp)
slt $t0,$t1,$t0
xori $t0,$t0,1
addiu isp,-4
sw $t0,-4(isp)
FETCH
# < operator
.globl b7
b7:
lw $t1,-4(isp)
lw $t0,-8(isp)
slt $t0,$t0,$t1
addiu isp,-4
sw $t0,-4(isp)
FETCH
# >= operator
.globl b10
b10:
lw $t1,-4(isp)
lw $t0,-8(isp)
slt $t0,$t0,$t1
xori $t0,$t0,1
addiu isp,-4
sw $t0,-4(isp)
FETCH
# > operator
.globl b11
b11:
lw $t1,-4(isp)
lw $t0,-8(isp)
slt $t0,$t1,$t0
addiu isp,-4
sw $t0,-4(isp)
FETCH
# >> operator
.globl b12
b12:
lw $t1,-4(isp)
lw $t0,-8(isp)
addiu isp,-4
srav $t0,$t0,$t1
sw $t0,-4(isp)
FETCH
# << operator
.globl b13
b13:
lw $t1,-4(isp)
lw $t0,-8(isp)
addiu isp,-4
sllv $t0,$t0,$t1
sw $t0,-4(isp)
FETCH
# + operator
.globl b14
b14:
lw $t1,-4(isp)
lw $t0,-8(isp)
addiu isp,-4
addu $t0,$t1
sw $t0,-4(isp)
FETCH
# - operator
.globl b15
b15:
lw $t1,-4(isp)
lw $t0,-8(isp)
addiu isp,-4
subu $t0,$t1
sw $t0,-4(isp)
FETCH
# % operator
.globl b16
b16:
lw $t1,-4(isp)
lw $t0,-8(isp)
div $t0,$t1
addiu isp,-4
mfhi $t0
sw $t0,-4(isp)
FETCH
# * operator
.globl b17
b17:
lw $t1,-4(isp)
lw $t0,-8(isp)
mult $t0,$t1
addiu isp,-4
mflo $t0
sw $t0,-4(isp)
FETCH
# / operator
.globl b20
b20:
lw $t1,-4(isp)
lw $t0,-8(isp)
div $t0,$t1
addiu isp,-4
mflo $t0
sw $t0,-4(isp)
FETCH
# =| operator
.globl b102
b102:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
or $t0,$t1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =& operator
.globl b103
b103:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
and $t0,$t1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =>> operator
.globl b112
b112:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
srav $t0,$t0,$t1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =<< operator
.globl b113
b113:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
sllv $t0,$t0,$t1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =+ operator
.globl b114
b114:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
addu $t0,$t1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =- operator
.globl b115
b115:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
subu $t0,$t1
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =% operator
.globl b116
b116:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
div $t0,$t1
mfhi $t0
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =* operator
.globl b117
b117:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
mult $t0,$t1
mflo $t0
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
# =/ operator
.globl b120
b120:
lw $t1,-4(isp) # value
lw $v0,-8(isp) # address
addiu isp,-4
sll $v0,2
lw $t0,($v0)
div $t0,$t1
mflo $t0
sw $t0,($v0)
sw $t0,-4(isp)
FETCH
|
aap/b
| 2,151
|
mips32/libb.s
|
.set idp,$s0
.set isp,$s1
.set ipc,$s2
.set noreorder
# to adjust stack, addiu isp,(2+nargs)*4,
# (2+1)*4 if no args but returns value
.globl _putchar
.data
_putchar: .word 1f
.text
1: .word 1f
1: addiu isp,12
lw $t0,8(idp) # chars
la $a1,ch
sw $t0,($a1)
move $a2,$zero # num chars
1: beq $t0,$zero,1f
srl $t0,8
b 1b
addiu $a2,1
1: lw $a0,_fout
jal write
nop
j n7
sw $v0,-4(isp)
.globl _getchar
.data
_getchar: .word 1f
.text
1: .word 1f
1: addiu isp,12
lw $a0,_fin
la $a1,ch
jal read
li $a2,1
li $v1,1
bne $v0,$v1,1f
move $v0,$zero
lb $v0,ch
1: j n7
sw $v0,-4(isp)
.data
ch: .word 0
.word 0
.globl _fin, _fout, _ferr
_fin: .word 0
_fout: .word 1
_ferr: .word 2
.text
.globl _char
.data
_char: .word 1f
.text
1: .word 1f
1: addiu isp,16
lw $v0,8(idp) # string
sll $v0,2
lw $t0,12(idp) # offset
addu $v0,$t0
lb $t1,($v0)
j n7
sw $t1,-4(isp)
.globl _lchar
.data
_lchar: .word 1f
.text
1: .word 1f
1: lw $v0,8(idp) # string
sll $v0,2
lw $t0,12(idp) # offet
addu $v0,$t0
lw $t1,16(idp) # char
j n11
sb $t1,($v0)
.globl _open
.data
_open: .word 1f
.text
1: .word 1f
1: addiu isp,20
lw $a0,8(idp) # path
lw $a1,12(idp) # flags
lw $a2,16(idp) # mode
jal open
sll $a0,2
j n7
sw $v0,-4(isp)
.globl _creat
.data
_creat: .word 1f
.text
1: .word 1f
1: addiu isp,16
lw $a0,8(idp) # path
li $a1,01401 # flags, O_CREAT, O_TRUNC, O_WRONLY
lw $a2,12(idp) # mode
jal open
sll $a0,2
j n7
sw $v0,-4(isp)
.globl _close
.data
_close: .word 1f
.text
1: .word 1f
1: jal close
lw $a0,8(idp)
j n11
nop
.globl _seek
.data
_seek: .word 1f
.text
1: .word 1f
1: addiu isp,20
lw $a0,8(idp) # fd
lw $a1,12(idp) # off
jal lseek
lw $a2,16(idp) # whence
j n7
sw $v0,-4(isp)
.globl _write
.data
_write: .word 1f
.text
1: .word 1f
1: addiu isp,20
lw $a0,8(idp) # fd
lw $a1,12(idp) # buf
lw $a2,16(idp) # count
jal write
sll $a1,2
j n7
sw $v0,-4(isp)
.globl _read
.data
_read: .word 1f
.text
1: .word 1f
1: addiu isp,20
lw $a0,8(idp) # fd
lw $a1,12(idp) # buf
lw $a2,16(idp) # count
jal read
sll $a1,2
j n7
sw $v0,-4(isp)
.globl _exit
.data
_exit: .word 1f
1: .word 1f
.text
1: jal exit
lw $a0,8(isp)
|
aap/b
| 1,319
|
mips32/brt1.s
|
.set idp,$s0
.set isp,$s1
.set ipc,$s2
.set noreorder
.macro FETCH skip=0
lw $v0,\skip(ipc)
jr $v0
addiu ipc,4+\skip
.endm
stacksz = 1000
.data
.globl _argv
_argv: .word 0
.bss
.align 2
stack: .space 4*stacksz
.text
.globl main, fetch
main:
la isp,stack
move idp,isp
la ipc,init
# B argc
sw $a0,8(idp)
# argv, have to make a B vector out of this, urgh
sll $t0,$a0,2
subu $sp,$t0
# B argv
srl $v1,$sp,2
sw $v1,12(idp)
# add argc as element 0 for external argv
sw $a0,-4($sp)
addiu $sp,-4
srl $v1,$sp,2
sw $v1,_argv
# copy arguments to stack with word alignment
# NB: the last word can have junk bytes after the NUL
addiu $v0,$sp,4
1: beq $a0,$zero,1f
addiu $a0,-1
# count string
lw $v1,($a1)
li $t0,3
2: lb $t1,($v1)
beq $t1,$zero,2f
addiu $t0,1
b 2b
addiu $v1,1
2: li $t1,~3
and $t0,$t1
# make space for string and copy it
subu $sp,$t0
move $t2,$sp
lw $v1,($a1)
2: beq $t0,$zero,2f
addiu $t0,-1
lb $t1,($v1)
sb $t1,($t2)
addiu $t2,1
b 2b
addiu $v1,1
2: addiu $a1,4
srl $t2,$sp,2
sw $t2,($v0)
j 1b
addiu $v0,4
1:
jal startchain
nop
fetch: FETCH
init:
.word x, _main
.word n1, 1f
1: jal exit
lw $a0,-4(isp)
.globl chain
chain:
lw $v0,($ra)
beq $v0,$zero,1f
addiu $ra,4
lw $t0,($v0)
srl $t0,2
b chain
sw $t0,($v0)
1: jr $ra
nop
startchain:
move $t7,$ra
|
aap/b
| 19,506
|
unix1_bdir/bc.s
|
jmp 9f
.globl .main
.main:
.+2
s; 4
x; .argv
c; 0
n4
c; 3
b7
f; L1
ix; .write
n2
c; 1
vx; 1f
t; 2f
1:
71101
20147
67543
67165
5164
0
2:
c; 12
n3
ix; .exit
n2
c; 1
n3
L1:
ivx; .fin
x; .open
n2
x; .argv
c; 2
n4
c; 0
n3
b1
c; 0
b7
f; L2
ix; .write
n2
c; 1
vx; 1f
t; 2f
1:
67111
72560
20164
64546
62554
5077
0
2:
c; 14
n3
ix; .exit
n2
c; 1
n3
L2:
ivx; .fout
x; .creat
n2
x; .argv
c; 3
n4
c; 16
n3
b1
c; 0
b7
f; L3
ix; .write
n2
c; 1
vx; 1f
t; 2f
1:
72517
70164
72165
63040
66151
37545
12
2:
c; 15
n3
ix; .exit
n2
c; 1
n3
L3:
ix; .keyw
n2
vx; 1f
t; 2f
1:
72541
67564
0
2:
c; 4
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
74145
71164
156
2:
c; 3
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
67547
67564
0
2:
c; 6
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
62562
72564
67162
0
2:
c; 7
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
63151
0
2:
c; 10
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
64167
66151
145
2:
c; 11
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
66145
62563
0
2:
c; 12
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
73563
72151
64143
0
2:
c; 13
n3
ix; .keyw
n2
vx; 1f
t; 2f
1:
60543
62563
0
2:
c; 14
n3
L4:
ix; .eof
u4
f; L5
ix; .extdef
n1
ix; .enddef
n1
t; L4
L5:
ix; .exit
n2
x; .nerror
c; 0
b5
n3
n11
7:
.globl .keyw
.keyw:
.+2
s; 22
va; 10
x; .namsiz
b1
iva; 12
va; 14
c; 0
b1
b1
L6:
iva; 10
u10
f; L7
ix; .lchar
n2
x; .symbuf
va; 12
u7
va; 16
x; .char
n2
a; 4
va; 14
u7
n3
b1
n3
ia; 16
c; 0
b4
f; L10
iva; 14
u10
L10:
t; L6
L7:
iva; 20
x; .lookup
n1
b1
ia; 20
c; 0
b14
c; 1
b1
ia; 20
c; 1
b14
a; 6
b1
n11
7:
.globl .extdef
.extdef:
.+2
s; 12
va; 4
x; .symbol
n1
b1
c; 0
b4
a; 4
c; 12
b4
b2
f; L11
n11
L11:
ia; 4
c; 17
b5
f; L12
ix; 7f+0
n6
L12:
ix; .csym
c; 0
b14
c; 3
b1
ix; .gensym
n2
c; 147
x; .csym
c; 2
b14
n3
iva; 10
c; 1
b1
ivx; .peeksym
x; .symbol
n1
b1
c; 6
b4
f; L14
ivx; .peeksym
c; -1
b1
iva; 10
c; 0
b1
iva; 4
x; .symbol
n1
b1
c; 15
b4
f; L15
iva; 10
x; .cval
b1
iva; 4
x; .symbol
n1
b1
L15:
ia; 4
c; 7
b5
f; L16
ix; 7f+0
n6
L16:
ix; .gen0
n2
c; 166
n3
L14:
L17:
s; 12
va; 4
x; .symbol
n1
b1
z; L20
L21=4
L22:
ivx; .nauto
c; 2
b1
ivx; .nlbl
c; 0
b1
ix; .gen0
n2
c; 145
n3
ix; .declare
n2
c; 5
n3
ix; .gen0
n2
c; 123
n3
ix; .stmt
n1
ix; .gen1
n2
c; 156
c; 11
n3
ix; .gen0
n2
c; 160
n3
iva; 6
c; 0
b1
L23:
ia; 6
x; .nlbl
b7
f; L24
ix; .gen1
n2
c; 154
x; .lbltab
va; 6
u7
n4
n3
t; L23
L24:
n11
L25=12
L26:
L27:
s; 12
a; 10
c; 0
b11
f; L30
ix; .gen1
n2
c; 162
a; 10
n3
L30:
n11
L31=15
L32:
ix; .gen1
n2
c; 157
x; .cval
n3
L33:
s; 12
va; 10
u10
iva; 4
x; .symbol
n1
b1
c; 12
b4
f; L34
ix; 7f+4
n6
L34:
ia; 4
c; 21
b5
f; L35
ix; 7f+0
n6
L35:
ix; 7f+2
n6
L36=16
L37:
ix; .getstr
n1
ix; 7f+6
n6
L40=0
L41:
n11
t; .+30
L20:
5
L21
L22
L25
L26
L31
L32
L36
L37
L40
L41
L13:
s; 12
x; .err
n2
c; 74170
c; 0
n3
ix; .errflush
n2
a; 4
n3
n11
7:
L13
L17
L27
L33
.globl .enddef
.enddef:
.+2
s; 6
va; 4
x; .symtab
b1
L42:
ia; 4
x; .symtab
x; .stablen
b14
b7
f; L43
ia; 4
c; 2
n4
f; L44
ia; 4
c; 0
n4
c; 0
b4
f; L45
ix; .err
n2
c; 72556
a; 4
c; 2
b14
n3
L45:
L44:
ia; 4
c; 0
n4
c; 1
b5
f; L46
ia; 4
c; 2
b14
c; 0
b1
ivx; .symused
u10
L46:
iva; 4
x; .symsz
b114
t; L42
L43:
n11
7:
.globl .declare
.declare:
.+2
L47:
s; 10
va; 6
x; .symbol
n1
b1
c; 17
b4
f; L50
ix; .csym
u3
c; 0
b5
f; L51
ix; .err
n2
c; 71144
x; .csym
c; 2
b14
n3
L51:
ix; .csym
a; 4
b1
ia; 4
c; 3
b5
f; L52
ix; .csym
c; 4
b1
ix; .csym
c; 1
b14
vx; .nauto
u7
b1
L52:
iva; 6
x; .symbol
n1
b1
ia; 4
c; 4
b4
a; 6
c; 15
b4
b3
f; L53
ix; .gen1
n2
c; 171
x; .csym
c; 1
n4
n3
ivx; .nauto
x; .cval
b114
iva; 6
x; .symbol
n1
b1
L53:
ia; 6
c; 21
b5
f; L54
ix; 7f+0
n6
L54:
t; L47
L50:
L55:
s; 10
a; 6
c; 12
b4
a; 4
c; 5
b5
b3
a; 6
c; 5
b4
a; 4
c; 5
b4
b3
b2
f; L56
n11
L56:
ix; .err
n2
c; 71570
c; 0
n3
ix; .errflush
n2
a; 6
n3
n11
7:
L55
.globl .stmt
.stmt:
.+2
s; 20
va; 4
x; .symbol
n1
b1
z; L57
L60=0
L61:
ix; .err
n2
c; 37477
c; 0
n3
n11
L62=11
L63:
ivx; .peeksym
a; 4
b1
L64=12
L65:
n11
L66=10
L67:
L70:
ix; .eof
u4
f; L71
iva; 4
x; .symbol
n1
b1
c; 11
b4
f; L72
n11
L72:
ivx; .peeksym
a; 4
b1
ix; .stmt
n1
t; L70
L71:
ix; .err
n2
c; 22051
c; 0
n3
n11
L73=20
L74:
ix; .cval
z; L75
L76=4
L77:
L100=3
L101:
ix; .declare
n2
x; .cval
n3
ix; .stmt
n6
L102=6
L103:
ix; .expr
n1
ix; .gen1
n2
c; 156
c; 6
n3
ix; 7f+0
n6
L105=7
L106:
ivx; .peeksym
x; .symbol
n1
b1
c; 4
b4
f; L107
ix; .pexpr
n1
ix; .gen1
n2
c; 156
c; 7
n3
ix; 7f+0
n6
L107:
ix; .gen1
n2
c; 156
c; 11
n3
ix; 7f+0
n6
L110=10
L111:
ix; .pexpr
n1
ix; .gen1
n2
c; 146
va; 6
vx; .loc
u7
b1
n3
ix; .stmt
n1
iva; 4
x; .symbol
n1
b1
c; 20
b4
x; .cval
c; 12
b4
b3
f; L112
ix; .gen1
n2
c; 164
va; 10
vx; .loc
u7
b1
n3
ix; .label
n2
a; 6
n3
ix; .stmt
n1
ix; .label
n2
a; 10
n3
n11
L112:
ivx; .peeksym
a; 4
b1
ix; .label
n2
a; 6
n3
n11
L113=11
L114:
ix; .label
n2
va; 6
vx; .loc
u7
b1
n3
iva; 10
vx; .loc
u7
b1
ix; .pexpr
n1
ix; .gen1
n2
c; 146
a; 10
n3
ix; .stmt
n1
ix; .gen1
n2
c; 164
a; 6
n3
ix; .label
n2
a; 10
n3
n11
L115=14
L116:
iva; 4
x; .symbol
n1
b1
c; 15
b5
f; L117
ix; 7f+2
n6
L117:
iva; 4
x; .symbol
n1
b1
c; 22
b5
f; L121
ix; 7f+2
n6
L121:
ix; .swp
c; 0
b4
f; L122
ix; 7f+2
n6
L122:
ix; .swp
x; .swtab
x; .swsiz
b14
b10
f; L123
ix; .err
n2
c; 37143
c; 0
n3
ix; .exit
n2
c; 1
n3
L123:
ix; .gen2
n2
c; 161
x; .loc
x; .cval
n3
ivx; .swp
u7
vx; .loc
u7
b1
ix; .label
n2
vx; .loc
u7
n3
ix; .stmt
n6
L124=13
L125:
ix; .expr
n1
ix; .gen1
n2
c; 172
va; 6
vx; .loc
u7
b1
n3
ix; .swp
c; 0
b4
f; L126
ivx; .swp
x; .swtab
b1
L126:
iva; 16
x; .swp
b1
ix; .stmt
n1
ix; .swp
a; 16
b4
f; L127
ix; .err
n2
c; 71567
c; 0
n3
L127:
ix; .gen1
n2
c; 153
c; 1
x; .swp
a; 16
b15
c; 2
b17
b14
n3
ix; .label
n2
a; 6
n3
ix; .gen1
n2
c; 157
x; .swp
a; 16
b15
n3
iva; 14
a; 16
b1
L130:
ia; 14
x; .swp
b5
f; L131
ix; .gen1
n2
c; 154
va; 6
va; 14
u7
u3
b1
n3
ix; .gen1
n2
c; 154
va; 6
u5
n3
t; L130
L131:
ivx; .swp
a; 16
b1
n11
t; .+44
L75:
10
L76
L77
L100
L101
L102
L103
L105
L106
L110
L111
L113
L114
L115
L116
L124
L125
ix; 7f+2
n6
L132=17
L133:
ix; .peekc
c; 72
b4
f; L134
ivx; .peekc
c; 0
b1
ix; .csym
c; 0
n4
c; 0
b11
f; L135
ix; .err
n2
c; 71144
x; .csym
c; 2
b14
n3
ix; .stmt
n6
L135:
ix; .csym
c; 0
b14
c; 2
b1
ix; .deflab
n1
ix; .label
n2
x; .lbltab
x; .csym
c; 1
n4
c; 1
b15
n4
n3
ix; .gen0
n2
c; 123
n3
ix; .stmt
n6
L134:
t; .+34
L57:
6
L60
L61
L62
L63
L64
L65
L66
L67
L73
L74
L132
L133
ivx; .peeksym
a; 4
b1
ix; .expr
n1
L104:
s; 20
va; 4
x; .symbol
n1
b1
c; 12
b4
f; L136
n11
L136:
L120:
s; 20
x; .err
n2
c; 71570
c; 0
n3
ix; .errflush
n2
a; 4
n3
ix; .stmt
n6
n11
7:
L104
L120
.globl .deflab
.deflab:
.+2
s; 4
x; .csym
c; 1
n4
c; 0
b4
f; L137
ix; .nlbl
x; .lblsiz
b10
f; L140
ix; .err
n2
c; 37151
c; 0
n3
ix; .exit
n2
c; 1
n3
L140:
ix; .lbltab
x; .nlbl
b14
vx; .loc
u7
b1
ix; .csym
c; 1
b14
vx; .nlbl
u5
b1
L137:
n11
7:
.globl .label
.label:
.+2
s; 6
x; .gen1
n2
c; 114
a; 4
n3
n11
7:
.globl .putw
.putw:
.+2
s; 6
x; .write
n2
x; .fout
va; 4
c; 2
n3
n11
7:
.globl .gen0
.gen0:
.+2
s; 6
x; .putchar
n2
a; 4
n3
n11
7:
.globl .gen1
.gen1:
.+2
s; 10
x; .putchar
n2
a; 4
n3
ix; .putw
n2
a; 6
n3
n11
7:
.globl .gen2
.gen2:
.+2
s; 12
x; .putchar
n2
a; 4
n3
ix; .putw
n2
a; 6
n3
ix; .putw
n2
a; 10
n3
n11
7:
.globl .gensym
.gensym:
.+2
s; 10
x; .putchar
n2
a; 4
n3
ix; .write
n2
x; .fout
a; 6
x; .namsiz
n3
n11
7:
.globl .pexpr
.pexpr:
.+2
s; 6
va; 4
x; .symbol
n1
b1
c; 4
b5
f; L141
ix; 7f+0
n6
L141:
ix; .expr
n1
iva; 4
x; .symbol
n1
b1
c; 5
b4
f; L143
n11
L143:
L142:
s; 6
x; .err
n2
c; 71570
c; 0
n3
ix; .errflush
n2
a; 4
n3
n11
7:
L142
.globl .expr
.expr:
.+2
y; 6
y; 62
s; 146
va; 4
a; 6
b1
iva; 60
a; 62
b1
ia; 4
c; 0
b1
ia; 60
c; 6
b1
iva; 134
c; 0
b1
ix; .gen1
n2
c; 163
x; .nauto
n3
L144:
s; 146
va; 136
x; .symbol
n1
b1
z; L145
L146=17
L147:
ix; .csym
u3
c; 0
b4
f; L150
ix; .peekc
c; 50
b4
f; L151
ix; .csym
c; 0
b14
c; 3
b1
t; L152
L151:
ix; .deflab
n1
L152:
L150:
ix; .csym
u3
z; L153
L154=3
L155:
ix; .gensym
n2
c; 170
x; .csym
c; 2
b14
n3
ix; 7f+2
n6
L157=0
L160:
L161=2
L162:
ix; .gen1
n2
c; 151
x; .csym
c; 1
n4
c; 1
b15
n3
ix; 7f+2
n6
L163=4
L164:
ix; .gen1
n2
c; 141
x; .csym
c; 1
n4
n3
ix; 7f+2
n6
t; .+24
L153:
4
L154
L155
L157
L160
L161
L162
L163
L164
ix; 7f+4
n6
L166=15
L167:
L170:
s; 146
x; .gen1
n2
c; 143
x; .cval
n3
ix; 7f+2
n6
L171=16
L172:
ix; .gen0
n2
c; 74
n3
ix; .getstr
n1
ix; .gen0
n2
c; 76
n3
L156:
s; 146
a; 134
f; L173
ix; 7f+4
n6
L173:
iva; 134
c; 1
b1
ix; 7f+0
n6
L174=72
L175:
L176=73
L177:
ia; 134
f; L200
iva; 136
c; 2
b114
L200:
ix; 7f+10
n6
L202=71
L203:
ia; 134
f; L204
ix; 7f+4
n6
L204:
ix; 7f+10
n6
L205=43
L206:
ia; 134
u4
f; L207
ivx; .peeksym
x; .symbol
n1
b1
c; 15
b4
f; L210
ivx; .peeksym
c; -1
b1
ivx; .cval
x; .cval
u2
b1
ix; 7f+6
n6
L210:
iva; 136
c; 67
b1
L207:
iva; 134
c; 0
b1
ix; 7f+10
n6
L211=31
L212:
L213=45
L214:
ia; 134
f; L215
iva; 134
c; 0
b1
t; L216
L215:
ia; 136
c; 31
b4
f; L217
iva; 136
c; 66
b1
t; L220
L217:
iva; 136
c; 70
b1
L220:
L216:
ix; 7f+10
n6
L221=4
L222:
ia; 134
f; L223
iva; 136
x; .symbol
n1
b1
c; 5
b4
f; L224
iva; 136
c; 25
b1
t; L225
L224:
ivx; .peeksym
a; 136
b1
iva; 136
c; 24
b1
iva; 134
c; 0
b1
L225:
L223:
ix; 7f+10
n6
L226=5
L227:
L230=7
L231:
ia; 134
u4
f; L232
ix; 7f+4
n6
L232:
ix; 7f+10
n6
t; .+64
L145:
14
L146
L147
L166
L167
L171
L172
L174
L175
L176
L177
L202
L203
L205
L206
L211
L212
L213
L214
L221
L222
L226
L227
L230
L231
ia; 134
u4
f; L233
ix; 7f+4
n6
L233:
iva; 134
c; 0
b1
L201:
s; 146
va; 140
x; .opdope
a; 136
n4
c; 6
b12
c; 77
b3
b1
ia; 140
a; 60
u3
b11
a; 140
a; 60
u3
b4
x; .opdope
a; 136
n4
c; 2
b3
c; 0
b5
b3
b2
f; L234
ia; 136
z; L235
L236=24
L237:
ix; .gen1
n2
c; 156
c; 2
n3
L240=4
L241:
L242=6
L243:
iva; 140
c; 4
b1
t; .+20
L235:
3
L236
L237
L240
L241
L242
L243
ia; 4
a; 6
c; 24
b14
b10
f; L244
ix; .err
n2
c; 37145
c; 0
n3
ix; .exit
n2
c; 1
n3
L244:
iva; 4
u5
a; 136
b1
iva; 60
u5
a; 140
b1
ix; 7f+0
n6
L234:
iva; 60
u6
iva; 142
va; 4
u10
u3
b1
z; L245
L246=0
L247:
ivx; .peeksym
a; 136
b1
ix; .gen0
n2
c; 105
n3
n11
L250=23
L251:
ix; .gen1
n2
c; 77
vx; .loc
u7
n3
ivx; .loc
u7
L252=22
L253:
ix; 7f+10
n6
L254=24
L255:
ia; 136
c; 5
b5
f; L256
ix; 7f+4
n6
L256:
ix; .gen1
n2
c; 156
c; 3
n3
ix; 7f+0
n6
L257=25
L260:
ix; .gen1
n2
c; 156
c; 1
n3
L261=21
L262:
ix; 7f+10
n6
L263=4
L264:
ia; 136
c; 5
b5
f; L265
ix; 7f+4
n6
L265:
ix; 7f+0
n6
L266=6
L267:
ia; 136
c; 7
b5
f; L270
ix; 7f+4
n6
L270:
ix; .gen1
n2
c; 156
c; 4
n3
ix; 7f+0
n6
t; .+44
L245:
10
L246
L247
L250
L251
L252
L253
L254
L255
L257
L260
L261
L262
L263
L264
L266
L267
L271:
s; 146
a; 142
c; 27
b7
f; L272
ix; 7f+4
n6
t; L273
L272:
ia; 142
c; 46
b6
f; L274
ix; .gen1
n2
c; 142
a; 142
c; 27
b15
c; 1
b14
n3
t; L275
L274:
ia; 142
c; 65
b6
f; L276
ix; .gen1
n2
c; 142
a; 142
c; 47
b15
c; 102
b14
n3
t; L277
L276:
ia; 142
c; 75
b6
f; L300
ix; .gen1
n2
c; 165
a; 142
c; 66
b15
c; 1
b14
n3
L300:
L277:
L275:
L273:
ix; 7f+10
n6
L165:
s; 146
x; .err
n2
c; 62570
c; 0
n3
ix; .errflush
n2
a; 136
n3
n11
7:
L144
L156
L165
L170
L201
L271
.globl .errflush
.errflush:
.+2
L301:
s; 6
a; 4
c; 12
b5
a; 4
c; 10
b5
b3
a; 4
c; 11
b5
b3
f; L302
iva; 4
x; .symbol
n1
b1
t; L301
L302:
ivx; .peeksym
a; 4
b1
n11
7:
.globl .lookup
.lookup:
.+2
s; 16
va; 4
c; 0
b1
iva; 12
x; .symbuf
b1
iva; 6
x; .nwps
b1
L303:
iva; 6
u10
f; L304
iva; 4
va; 12
u7
u3
b114
t; L303
L304:
ia; 4
c; 0
b7
f; L305
iva; 4
a; 4
u2
b1
L305:
iva; 4
x; .stabsz
b116
iva; 4
x; .symsz
b117
L306:
iva; 10
x; .symtab
a; 4
c; 2
b14
b14
b1
u3
f; L307
iva; 12
x; .symbuf
b1
iva; 6
x; .nwps
b1
L310:
iva; 6
u10
f; L311
iva; 10
u7
u3
va; 12
u7
u3
b5
f; L312
ix; 7f+0
n6
L312:
t; L310
L311:
ix; .symtab
a; 4
b14
n7
L313:
s; 16
va; 4
x; .symsz
b114
x; .stablen
b10
f; L314
iva; 4
c; 0
b1
L314:
t; L306
L307:
ivx; .symused
u5
x; .stabsz
b10
f; L315
ix; .err
n2
c; 37163
c; 0
n3
ix; .exit
n2
c; 1
n3
L315:
iva; 14
va; 10
x; .symtab
a; 4
b14
b1
b1
iva; 12
x; .symbuf
b1
iva; 10
u7
c; 0
b1
iva; 10
u7
c; 0
b1
iva; 6
x; .nwps
b1
L316:
iva; 6
u10
f; L317
iva; 10
u7
va; 12
u7
u3
b1
t; L316
L317:
ia; 14
n7
n11
7:
L313
.globl .symbol
.symbol:
.+2
L320:
s; 12
x; .peeksym
c; 0
b10
f; L321
iva; 6
x; .peeksym
b1
ivx; .peeksym
c; -1
b1
ia; 6
n7
L321:
iva; 6
x; .getchr
n1
b1
ix; .eof
f; L322
ic; 0
n7
L322:
iva; 6
c; 177
b103
ix; .ctab
a; 6
n4
z; L323
L324=1
L325:
ix; 7f+0
n6
L326=42
L327:
ix; .subseq
n2
c; 53
c; 42
c; 72
n3
n7
L330=43
L331:
ix; .subseq
n2
c; 55
c; 43
c; 73
n3
n7
L332=71
L333:
ix; .subseq
n2
c; 75
c; 71
c; 33
n3
n7
L334=35
L335:
ix; .subseq
n2
c; 74
c; 0
c; 1
n3
f; L336
ic; 41
n7
L336:
ix; .subseq
n2
c; 75
c; 35
c; 34
n3
n7
L337=37
L340:
ix; .subseq
n2
c; 76
c; 0
c; 1
n3
f; L341
ic; 40
n7
L341:
ix; .subseq
n2
c; 75
c; 37
c; 36
n3
n7
L342=27
L343:
iva; 6
x; .getchr
n1
b1
c; 75
b4
f; L344
ix; .subseq
n2
c; 75
c; 32
c; 51
n3
n7
L344:
ix; .ctab
a; 6
n4
c; 1
b4
f; L345
ic; 27
n7
L345:
ix; .ungetchr
n2
a; 6
n3
iva; 6
x; .symbol
n1
b1
ia; 6
c; 30
b10
a; 6
c; 46
b6
b3
f; L346
ia; 6
c; 30
b15
c; 47
b14
n7
L346:
ivx; .peeksym
a; 6
b1
ic; 27
n7
L347=46
L350:
ix; .subseq
n2
c; 52
c; 1
c; 0
n3
f; L351
ic; 46
n7
L351:
L352:
ic; 1
f; L353
iva; 6
x; .getchr
n1
b1
ix; .eof
f; L354
ix; .err
n2
c; 57
c; 0
n3
ic; 0
n7
L354:
ia; 6
c; 52
b4
f; L355
iva; 6
x; .getchr
n1
b1
ia; 6
c; 57
b4
f; L356
ix; 7f+0
n6
L356:
L355:
t; L352
L353:
L357=13
L360:
ivx; .cval
c; 0
b1
ia; 6
c; 60
b4
f; L361
iva; 4
c; 10
b1
t; L362
L361:
iva; 4
c; 12
b1
L362:
L363:
ix; .ctab
a; 6
n4
c; 13
b4
f; L364
ivx; .cval
x; .cval
a; 4
b17
a; 6
b14
c; 60
b15
b1
iva; 6
x; .getchr
n1
b1
t; L363
L364:
ix; .ungetchr
n2
a; 6
n3
ic; 15
n7
L365=3
L366:
ix; .getcc
n1
n7
L367=14
L370:
iva; 10
c; 0
b1
L371:
ix; .ctab
a; 6
n4
c; 14
b4
x; .ctab
a; 6
n4
c; 13
b4
b2
f; L372
ia; 10
x; .namsiz
b7
f; L373
ix; .lchar
n2
x; .symbuf
va; 10
u7
a; 6
n3
L373:
iva; 6
x; .getchr
n1
b1
t; L371
L372:
L374:
ia; 10
x; .namsiz
b7
f; L375
ix; .lchar
n2
x; .symbuf
va; 10
u7
c; 0
n3
t; L374
L375:
ix; .ungetchr
n2
a; 6
n3
ivx; .csym
x; .lookup
n1
b1
ix; .csym
c; 0
n4
c; 1
b4
f; L376
ivx; .cval
x; .csym
c; 1
n4
b1
ic; 20
n7
L376:
ic; 17
n7
t; .+60
L323:
13
L324
L325
L326
L327
L330
L331
L332
L333
L334
L335
L337
L340
L342
L343
L347
L350
L357
L360
L365
L366
L367
L370
ix; .ctab
a; 6
n4
n7
n11
7:
L320
.globl .subseq
.subseq:
.+2
s; 14
va; 12
x; .getchr
n1
b1
a; 4
b4
f; L377
ia; 10
n7
L377:
ix; .ungetchr
n2
a; 12
n3
ia; 6
n7
n11
7:
.globl .getstr
.getstr:
.+2
s; 12
va; 10
va; 6
c; 0
b1
b1
L400:
iva; 4
x; .mapch
n2
c; 42
n3
b1
c; 0
b10
f; L401
ix; .lchar
n2
va; 10
va; 6
u7
a; 4
n3
ia; 6
c; 2
b4
f; L402
ix; .gen1
n2
c; 157
a; 10
n3
iva; 10
va; 6
c; 0
b1
b1
L402:
t; L400
L401:
ix; .gen1
n2
c; 157
a; 10
n3
n11
7:
.globl .getcc
.getcc:
.+2
s; 10
va; 6
c; 0
b1
ivx; .cval
c; 0
b1
L403:
iva; 4
x; .mapch
n2
c; 47
n3
b1
c; 0
b10
f; L404
ivx; .cval
x; .cval
c; 10
b13
a; 4
b14
b1
t; L403
L404:
ic; 15
n7
n11
7:
.globl .mapch
.mapch:
.+2
s; 10
va; 6
x; .getchr
n1
b1
ix; .eof
a; 6
c; 12
b4
b2
f; L405
ix; .err
n2
c; 21042
c; 0
n3
ix; .ungetchr
n2
a; 6
n3
ic; -1
n7
L405:
ia; 6
a; 4
b4
f; L406
ic; -1
n7
L406:
ia; 6
c; 52
b4
f; L407
iva; 6
x; .getchr
n1
b1
ia; 6
z; L410
L411=60
L412:
L413=145
L414:
ic; 0
n7
L415=164
L416:
ic; 11
n7
L417=156
L420:
ic; 12
n7
t; .+24
L410:
4
L411
L412
L413
L414
L415
L416
L417
L420
L407:
ia; 6
n7
n11
7:
.globl .getchr
.getchr:
.+2
s; 6
x; .peekc
f; L421
iva; 4
x; .peekc
b1
ivx; .peekc
c; 0
b1
t; L422
L421:
iva; 4
x; .getchar
n1
b1
L422:
ia; 4
c; 0
b6
f; L423
ivx; .eof
c; 1
b1
ic; 0
n7
L423:
ia; 4
c; 12
b4
f; L424
ivx; .line
u7
L424:
ia; 4
n7
n11
7:
.globl .ungetchr
.ungetchr:
.+2
s; 6
a; 4
c; 12
b4
f; L425
ivx; .line
u10
L425:
ivx; .peekc
a; 4
b1
n11
7:
.globl .prtn
.prtn:
.+2
s; 12
va; 10
a; 4
a; 6
b20
b1
f; L426
ix; .prtn
n2
a; 10
a; 6
n3
L426:
ix; .putchar
n2
a; 4
a; 6
b16
c; 60
b14
n3
n11
7:
.globl .err
.err:
.+2
s; 12
vx; .nerror
u7
iva; 10
x; .fout
b1
ivx; .fout
c; 1
b1
ix; .prtn
n2
x; .line
c; 12
n3
ix; .putchar
n2
c; 40
n3
ix; .putchar
n2
a; 4
n3
ia; 6
f; L427
ix; .putchar
n2
c; 40
n3
ix; .write
n2
x; .fout
a; 6
x; .namsiz
n3
L427:
ix; .putchar
n2
c; 12
n3
ivx; .fout
a; 10
b1
n11
7:
.globl .symbuf
.symbuf:
0
8:
.=.+10
.globl .nwps
.nwps:
4
.globl .namsiz
.namsiz:
10
.globl .symsz
.symsz:
6
.globl .symused
.symused:
0
.globl .stabsz
.stabsz:
144
.globl .stablen
.stablen:
1130
.globl .symtab
.symtab:
8b-2
8:
.=.+2260
.globl .loc
.loc:
1
.globl .swsiz
.swsiz:
170
.globl .swtab
.swtab:
8b-2
8:
.=.+360
.globl .swp
.swp:
0
.globl .nauto
.nauto:
0
.globl .nlbl
.nlbl:
0
.globl .lblsiz
.lblsiz:
50
.globl .lbltab
.lbltab:
8b-2
8:
.=.+120
.globl .peeksym
.peeksym:
-1
.globl .peekc
.peekc:
0
.globl .eof
.eof:
0
.globl .line
.line:
1
.globl .csym
.csym:
0
.globl .cval
.cval:
0
.globl .nerror
.nerror:
0
.globl .ctab
.ctab:
8b-2
8:
377
377
377
377
377
377
377
377
377
1
1
1
377
1
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
377
1
71
16
377
377
44
31
3
4
5
45
42
21
43
14
46
13
13
13
13
13
13
13
13
13
13
22
12
35
27
37
23
377
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
6
377
7
377
14
377
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
10
30
11
377
377
.globl .opdope
.opdope:
8b-2
8:
0
0
0
0
3600
200
3600
200
0
0
0
0
0
0
0
0
0
701
1403
1403
3601
3601
1
1207
1601
2001
2201
2201
2401
2401
2401
2401
2601
2601
3001
3001
3201
3201
3201
1207
1207
1207
1207
1207
1207
1207
1207
1207
1207
1207
1207
1207
1207
1207
3406
3402
3402
3402
3406
3406
3406
3406
9: jsr r5,chain
8b-2
8:
|
aap/b
| 10,258
|
unix1_bdir/ba.s
|
jmp 9f
.globl .main
.main:
.+2
y; 10
s; 42
x; .argv
c; 0
n4
c; 3
b7
f; L1
ix; .printf
n2
vx; 1f
t; 2f
1:
71101
20147
67543
67165
5164
0
2:
n3
ix; .exit
n2
c; 1
n3
L1:
ivx; .fin
x; .open
n2
x; .argv
c; 2
n4
c; 0
n3
b1
c; 0
b7
f; L2
ix; .printf
n2
vx; 1f
t; 2f
1:
60503
23556
20164
64546
62156
22440
5163
0
2:
x; .argv
c; 2
n4
n3
ix; .exit
n2
c; 1
n3
L2:
ivx; .fout
x; .creat
n2
x; .argv
c; 3
n4
c; 16
n3
b1
c; 0
b7
f; L3
ix; .printf
n2
vx; 1f
t; 2f
1:
60503
23556
20164
71143
60545
62564
22440
5163
0
2:
x; .argv
c; 3
n4
n3
ix; .exit
n2
c; 1
n3
L3:
ix; .printf
n2
vx; 1f
t; 2f
1:
65011
70155
34440
5146
0
2:
n3
L4:
iva; 4
x; .getchar
n1
b1
c; 0
b11
f; L5
ia; 4
z; L6
L7=114
L10:
ix; .printf
n2
vx; 1f
t; 2f
1:
22514
35157
12
2:
x; .getw
n1
n3
ix; 7f+0
n6
L12=161
L13:
ix; .printf
n2
vx; 1f
t; 2f
1:
22514
36557
67445
12
2:
x; .getw
n1
x; .getw
n1
n3
ix; 7f+0
n6
L14=147
L15:
ix; .read
n2
x; .fin
a; 10
x; .namsiz
n3
ix; .lchar
n2
a; 10
x; .namsiz
c; 0
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
27012
66147
61157
20154
22456
5163
22456
35163
12
2:
a; 10
a; 10
n3
ix; 7f+0
n6
L16=145
L17:
ix; .printf
n2
vx; 1f
t; 2f
1:
27011
31053
12
2:
n3
ix; 7f+0
n6
L20=166
L21:
ix; .chain
n1
ix; 7f+0
n6
L22=154
L23:
ix; .printf
n2
vx; 1f
t; 2f
1:
46011
67445
12
2:
x; .getw
n1
n3
ix; 7f+0
n6
L24=157
L25:
ix; .printf
n2
vx; 1f
t; 2f
1:
22411
5157
0
2:
x; .getw
n1
n3
ix; 7f+0
n6
L26=162
L27:
ix; .printf
n2
vx; 1f
t; 2f
1:
27011
27075
22453
5157
0
2:
x; .getw
n1
c; 2
b17
n3
ix; 7f+0
n6
L30=160
L31:
ix; .printf
n2
vx; 1f
t; 2f
1:
35067
12
2:
n3
ix; 7f+0
n6
L32=153
L33:
ix; .printf
n2
vx; 1f
t; 2f
1:
72011
20073
25456
67445
12
2:
x; .getw
n1
c; 1
b14
c; 2
b17
n3
ix; 7f+0
n6
L34=164
L35:
L36=146
L37:
L40=172
L41:
ix; .printf
n2
vx; 1f
t; 2f
1:
22411
35543
46040
67445
12
2:
a; 4
x; .getw
n1
n3
ix; 7f+0
n6
L42=171
L43:
ix; .printf
n2
vx; 1f
t; 2f
1:
74411
20073
67445
12
2:
x; .getw
n1
c; 2
b17
n3
ix; 7f+0
n6
L44=163
L45:
ivx; .stklvl
x; .getw
n1
b1
ivx; .drop
c; 1
b1
ivx; .blockp
x; .space
b1
ivx; .sp
x; .stack
b1
ivx; .ap
x; .ast
b1
ix; 7f+0
n6
L46=170
L47:
ix; .read
n2
x; .fin
va; 36
x; .blockp
b1
x; .namsiz
n3
ix; .lchar
n2
a; 36
x; .namsiz
c; 0
n3
ivx; .blockp
c; 10
b114
ivx; .sp
u7
x; .block
n2
c; 1
a; 4
a; 36
n3
b1
ix; 7f+0
n6
L50=141
L51:
L52=143
L53:
L54=151
L55:
ivx; .sp
u7
x; .block
n2
c; 1
a; 4
x; .getw
n1
n3
b1
ix; 7f+0
n6
L56=74
L57:
ivx; .sp
u7
va; 36
x; .block
n2
c; 1
c; 163
c; 0
n3
b1
b1
L60:
iva; 4
x; .getchar
n1
b1
c; 76
b5
f; L61
ivx; .blockp
u7
x; .getw
n1
b1
t; L60
L61:
ia; 36
c; 1
b14
x; .blockp
a; 36
b15
c; 2
b15
b1
ix; 7f+0
n6
L62=142
L63:
L64=165
L65:
ix; .build
n2
a; 4
x; .getw
n1
n3
ix; 7f+0
n6
L66=156
L67:
iva; 6
x; .getw
n1
b1
ia; 6
z; L70
L71=1
L72:
ix; .sp
c; -1
b14
x; .block
n2
c; 2
c; 24051
x; .sp
c; -1
n4
c; 0
n3
b1
ix; 7f+0
n6
L73=2
L74:
ivx; .ap
u7
x; .sp
b1
ix; 7f+0
n6
L75=3
L76:
iva; 40
x; .sp
b1
ivx; .sp
va; 6
vx; .ap
u6
u3
b1
b1
iva; 36
x; .block
n2
c; 2
c; 24051
vx; .sp
u6
u3
a; 40
a; 6
b15
n3
b1
L77:
ia; 6
a; 40
b7
f; L100
ivx; .blockp
u7
va; 6
u7
u3
b1
t; L77
L100:
ivx; .sp
u7
a; 36
b1
ix; 7f+0
n6
L101=4
L102:
ix; .build
n2
c; 55535
n3
ix; 7f+0
n6
L103=6
L104:
L105=7
L106:
L107=11
L110:
ix; .printf
n2
vx; 1f
t; 2f
1:
22411
22543
5157
0
2:
a; 4
a; 6
n3
ix; 7f+0
n6
t; .+40
L70:
7
L71
L72
L73
L74
L75
L76
L101
L102
L103
L104
L105
L106
L107
L110
ix; .error
n2
vx; 1f
t; 2f
1:
20156
67445
0
2:
a; 6
n3
ix; 7f+0
n6
L111=77
L112:
iva; 40
vx; .sp
u6
u3
b1
iva; 36
vx; .sp
u6
u3
b1
iva; 6
vx; .sp
u6
u3
b1
ivx; .sp
u7
x; .block
n2
c; 4
a; 4
x; .getw
n1
a; 6
a; 36
a; 40
n3
b1
ix; 7f+0
n6
L113=123
L114:
ivx; .setstk
c; 1
b1
ix; 7f+0
n6
L115=105
L116:
L117:
ix; .sp
x; .stack
b11
f; L120
ix; .cexpr
n2
vx; .sp
u6
u3
c; 0
n3
ivx; .drop
c; 1
b1
t; L117
L120:
ix; 7f+0
n6
t; .+154
L6:
32
L7
L10
L12
L13
L14
L15
L16
L17
L20
L21
L22
L23
L24
L25
L26
L27
L30
L31
L32
L33
L34
L35
L36
L37
L40
L41
L42
L43
L44
L45
L46
L47
L50
L51
L52
L53
L54
L55
L56
L57
L62
L63
L64
L65
L66
L67
L111
L112
L113
L114
L115
L116
L11:
t; L4
L5:
s; 42
x; .printf
n2
vx; 1f
t; 2f
1:
34412
4472
71552
4562
32562
61454
60550
67151
12
2:
n3
ix; .chain
n1
n11
7:
L11
.globl .build
.build:
.+2
s; 14
a; 4
c; 55535
b4
f; L121
ix; .build
n2
c; 142
c; 14
n3
iva; 4
c; 165
b1
iva; 6
c; 3
b1
L121:
ia; 4
z; L122
L123=165
L124:
iva; 10
vx; .sp
u6
u3
b1
ia; 6
z; L125
L126=1
L127:
ia; 10
c; 0
n4
c; 165
b4
a; 10
c; 1
n4
c; 3
b4
b3
f; L130
ivx; .sp
u7
a; 10
c; 2
n4
b1
n11
L130:
ix; 7f+0
n6
L132=3
L133:
ia; 10
c; 0
n4
c; 165
b4
a; 10
c; 1
n4
c; 1
b4
b3
f; L134
ivx; .sp
u7
a; 10
c; 2
n4
b1
n11
L134:
ix; 7f+0
n6
t; .+14
L125:
2
L126
L127
L132
L133
L131:
s; 14
vx; .sp
u7
x; .block
n2
c; 2
a; 4
a; 6
a; 10
n3
b1
n11
L135=142
L136:
ivx; .sp
u6
c; -1
b14
x; .block
n2
c; 3
a; 4
a; 6
x; .sp
c; -1
n4
x; .sp
u3
n3
b1
n11
t; .+14
L122:
2
L123
L124
L135
L136
ix; .error
n2
vx; 1f
t; 2f
1:
72542
66151
20144
61445
0
2:
a; 4
n3
n11
7:
L131
.globl .leaf
.leaf:
.+2
s; 10
x; .putchar
n2
c; 11
n3
ix; .drop
f; L137
ix; .putchar
n2
c; 151
n3
L137:
ia; 4
f; L140
ix; .putchar
n2
c; 166
n3
L140:
ix; .putchar
n2
a; 6
n3
ivx; .drop
c; 0
b1
n11
7:
.globl .cexpr
.cexpr:
.+2
s; 14
x; .setstk
f; L141
ix; .printf
n2
vx; 1f
t; 2f
1:
71411
20073
67445
12
2:
x; .stklvl
c; 2
b17
n3
ivx; .setstk
vx; .drop
c; 0
b1
b1
L141:
iva; 10
a; 4
c; 1
n4
b1
ia; 4
u3
z; L142
L143=143
L144:
ia; 6
f; L145
ix; .error
n2
vx; 1f
t; 2f
1:
66151
62554
60547
20154
73154
12
2:
n3
L145:
ix; .leaf
n2
a; 6
c; 143
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
20073
67445
12
2:
a; 10
n3
n11
L146=141
L147:
ix; .leaf
n2
a; 6
c; 141
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
20073
67445
12
2:
a; 10
c; 2
b17
n3
n11
L150=151
L151:
ix; .leaf
n2
a; 6
c; 170
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
20073
63067
22453
5157
0
2:
a; 10
c; 2
b17
n3
n11
L152=170
L153:
ix; .leaf
n2
a; 6
c; 170
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
20073
22456
5163
0
2:
a; 10
n3
n11
L154=163
L155:
ia; 6
f; L156
ix; .error
n2
vx; 1f
t; 2f
1:
66151
62554
60547
20154
73154
12
2:
n3
L156:
ix; .leaf
n2
c; 1
c; 170
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
20073
63061
4412
35564
31040
5146
35061
12
2:
n3
iva; 10
a; 4
c; 1
n4
b1
iva; 12
a; 4
c; 2
b14
b1
L157:
iva; 10
u10
f; L160
ix; .printf
n2
vx; 1f
t; 2f
1:
67445
12
2:
va; 12
u7
u3
n3
t; L157
L160:
ix; .printf
n2
vx; 1f
t; 2f
1:
35062
12
2:
n3
n11
L161=165
L162:
iva; 12
a; 4
c; 2
n4
b1
ia; 10
c; 3
b4
f; L163
ia; 6
f; L164
ix; .cexpr
n2
a; 4
c; 2
n4
c; 0
n3
n11
L164:
ia; 12
c; 0
n4
c; 142
b4
a; 12
c; 1
n4
c; 14
b4
b3
f; L165
ix; .cexpr
n2
a; 12
c; 2
n4
c; 0
n3
ix; .cexpr
n2
a; 12
c; 3
n4
c; 0
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
67011
5064
0
2:
n3
n11
L165:
L163:
ia; 6
f; L166
ix; .error
n2
vx; 1f
t; 2f
1:
66151
62554
60547
20154
73154
12
2:
n3
L166:
ia; 10
c; 1
b4
f; L167
ix; .cexpr
n2
a; 12
c; 1
n3
n11
L167:
ix; .cexpr
n2
a; 12
a; 10
c; 1
b4
a; 10
c; 5
b10
b2
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
22411
22543
5157
0
2:
a; 4
u3
a; 10
n3
n11
L170=142
L171:
ia; 6
f; L172
ix; .error
n2
vx; 1f
t; 2f
1:
66151
62554
60547
20154
73154
12
2:
n3
L172:
ix; .cexpr
n2
a; 4
c; 2
n4
a; 10
c; 1
b4
a; 10
c; 100
b10
b2
n3
ix; .cexpr
n2
a; 4
c; 3
n4
c; 0
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
22411
22543
5157
0
2:
a; 4
u3
a; 10
n3
n11
L173=77
L174:
ix; .cexpr
n2
a; 4
c; 2
n4
c; 0
n3
ivx; .drop
c; 1
b1
ix; .printf
n2
vx; 1f
t; 2f
1:
63011
20073
22514
5157
0
2:
a; 4
c; 1
n4
n3
ix; .cexpr
n2
a; 4
c; 3
n4
c; 0
n3
ivx; .drop
c; 1
b1
ix; .printf
n2
vx; 1f
t; 2f
1:
72011
20073
22514
5157
0
2:
a; 4
c; 1
n4
c; 1
b14
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
22514
35157
12
2:
a; 4
c; 1
n4
n3
ix; .cexpr
n2
a; 4
c; 4
n4
c; 0
n3
ix; .printf
n2
vx; 1f
t; 2f
1:
22514
35157
12
2:
a; 4
c; 1
n4
c; 1
b14
n3
n11
L175=24051
L176:
ix; .cexpr
n2
a; 4
c; 1
n4
c; 0
n3
iva; 10
a; 4
c; 2
n4
b1
ia; 10
c; 0
b4
f; L177
ix; .printf
n2
vx; 1f
t; 2f
1:
67011
5061
0
2:
n3
n11
L177:
ix; .printf
n2
vx; 1f
t; 2f
1:
67011
5062
0
2:
n3
iva; 12
a; 4
c; 3
b14
b1
L200:
iva; 10
u10
f; L201
ix; .cexpr
n2
va; 12
u7
u3
c; 0
n3
t; L200
L201:
ix; .printf
n2
vx; 1f
t; 2f
1:
67011
5063
0
2:
n3
n11
t; .+50
L142:
11
L143
L144
L146
L147
L150
L151
L152
L153
L154
L155
L161
L162
L170
L171
L173
L174
L175
L176
ix; .error
n2
vx; 1f
t; 2f
1:
67165
67153
73557
20156
70157
22440
5143
0
2:
a; 4
u3
n3
n11
7:
.globl .chn
.chn:
0
.globl .chain
.chain:
.+2
s; 4
x; .chn
f; L202
ix; .printf
n2
vx; 1f
t; 2f
1:
34011
26542
5062
35070
12
2:
n3
t; L203
L202:
ix; .printf
n2
vx; 1f
t; 2f
1:
30011
34012
5072
0
2:
n3
L203:
ivx; .chn
c; 1
b1
n11
7:
.globl .getw
.getw:
.+2
s; 6
va; 4
c; 0
b1
ix; .read
n2
x; .fin
va; 4
c; 2
n3
ia; 4
n7
n11
7:
.globl .block
.block:
.+2
s; 24
va; 20
x; .blockp
b1
iva; 22
va; 6
b1
iva; 4
u7
L204:
iva; 4
u10
f; L205
ivx; .blockp
u7
va; 22
u7
u3
b1
t; L204
L205:
ia; 20
n7
n11
7:
.globl .error
.error:
.+2
s; 14
vx; .nerror
u7
iva; 12
x; .fout
b1
ivx; .fout
c; 1
b1
ix; .printf
n2
a; 4
a; 6
a; 10
n3
ix; .putchar
n2
c; 12
n3
ivx; .fout
a; 12
b1
n11
7:
.globl .namsiz
.namsiz:
10
.globl .space
.space:
0
8:
.=.+764
.globl .blockp
.blockp:
.=.+2
.globl .nerror
.nerror:
.=.+2
.globl .ap
.ap:
0
.globl .ast
.ast:
8b-2
8:
.=.+120
.globl .sp
.sp:
0
.globl .stack
.stack:
8b-2
8:
.=.+120
.globl .stklvl
.stklvl:
0
.globl .setstk
.setstk:
0
.globl .drop
.drop:
0
9: jsr r5,chain
8b-2
8:
|
aap/b
| 1,806
|
unix1_bdir/int/bl.s
|
/ B library -- exit
.globl .exit
.exit: .+2
n10; n7
sys exit
/ B library -- write
.globl .write
.write: .+2
n10; n7
mov r4,r5
cmp (r5)+,(r5)+
mov (r5)+,r0
asl (r5)
mov (r5)+,0f
mov (r5)+,1f
sys write; 0:..; 1:..
bec 1f
mov $-1,r0
1:
mov r0,(r5)+
jmp fetch
/ B library -- open
.globl .open
.text
.open: .+2
n10; n7
mov r4,r5
cmp (r5)+,(r5)+
asl (r5)
mov (r5)+,0f
mov (r5)+,1f
sys open; 0:..; 1:..
bcc 1f
mov $-1,r0
1:
mov r0,(r5)+
jmp fetch
/ B library -- creat
.globl .creat
.creat:
.+2
n10; n7
mov r4,r5
cmp (r5)+,(r5)+
asl (r5)
mov (r5)+,1f
mov (r5)+,2f
sys creat; 1:..; 2:..
bec 1f
mov $-1,r0
1:
mov r0,(r5)+
jmp fetch
/ B library -- getchar
.globl .getchar
.globl .fin
.getchar:
.+2
n10; n7
mov .fin,r0
sys read; ch; 01
bes 1f
tst r0
beq 1f
mov ch,r0
br 2f
1:
clr r0
2:
mov r4,r5
add $4,r5
mov r0,(r5)+
jmp fetch
/ch: .=.+2
.fin: 0
/ B library -- putchar
.globl .putchar
.globl .flush
.globl .fout
.putchar:
.+2
n10; n11
mov 4(r4),ch
mov .fout,r0
tstb ch+1
beq 1f
swab ch
sys write; ch; 02
br 2f
1:
sys write; ch; 01
2:
jmp fetch
.flush:
.+2
n11
ch: .=.+2
.fout: 1
/ B library -- char
.globl .char
.char: .+2
n10; n7
mov r4,r5
add $4,r5
mov (r5)+,r1
asl r1
add (r5),r1
movb (r1),r0
mov r0,(r5)+
jmp fetch
/ B library -- lchar
.globl .lchar
.lchar: .+2
n10; n11
mov r4,r5
cmp (r5)+,(r5)+
mov (r5)+,r0
asl r0
add (r5)+,r0
movb (r5),(r0)
jmp fetch
/ B library -- read
.globl .read
.read: .+2
n10; n7
mov r4,r5
cmp (r5)+,(r5)+
mov (r5)+,r0
asl (r5)
mov (r5)+,0f
mov (r5)+,1f
sys read; 0:..; 1:..
bec 1f
mov $-1,r0
1:
mov r0,(r5)+
jmp fetch
|
aap/b
| 4,035
|
unix1_bdir/int/bi.s
|
/ could optimize eae with r2
/ ac 302
/ mq 304
.globl fetch
fetch:
mov (r3)+,r0 / fetch
mov r0,mq
clr ac
mov $3,lsh
mov ac,r1
asl r1 / jump offset
asr r0
bcs const
addr:
clr ac
mov $-3,lsh
mov mq,r0 / byte address
add $core,r0 / relocate to user
jmp *tab0(r1)
const:
bit $004000,r0 / sxt constant
bne const1
const0:
bic $170000,r0
jmp *tab1(r1)
const1:
bis $170000,r0
jmp *tab1(r1)
tab0: x.; ix.; vx.; ivx.; f.; t.; z.; misc.
tab1: c.; ic.; a.; ia.; va.; iva.; s.; y.
ic.: tst -(r5)
c.: mov r0,(r5)+
jmp fetch
ia.: tst -(r5)
a.: mov r4,r1
add r0,r1
mov (r1),(r5)+
jmp fetch
iva.: tst -(r5)
va.: mov r4,r1
add r0,r1
asr r1
mov r1,(r5)+
jmp fetch
s.: mov r4,r5
add r0,r5
jmp fetch
y.: add r4,r0
mov r0,r1
asr r0
inc r0
mov r0,(r1)
jmp fetch
ix.: tst -(r5)
x.: mov (r0),(r5)+
jmp fetch
ivx.: tst -(r5)
vx.: asr r0
mov r0,(r5)+
jmp fetch
f.: mov -(r5),(r5)+
bne 1f
t.: mov r0,r3
1: jmp fetch
z.: mov r0,r3
mov -2(r5),r0
mov (r3)+,r1 / num cases
1: cmp r0,(r3)+
beq 2f
tst (r3)+
dec r1
bne 1b
jmp fetch
2: mov (r3),r3
jmp fetch
misc.: / sub $core,r0 / unrelocate
jmp *mtab-core(r0)
mtab:
b1.
b2.
b3.
b4.
b5.
b6.
b7.
b10.
b11.
b12.
b13.
b14.
b15.
b16.
b17.
b20.
b102.
b103.
/ b104.
/ b105.
/ b106.
/ b107.
/ b110.
/ b111.
b112.
b113.
b114.
b115.
b116.
b117.
b120.
u2.
u3.
u4.
u5.
u6.
u7.
u10.
n1.
n2.
n3.
n4.
n5. /not threaded
in5. /not threaded
n6.
n7.
n10. /not threaded
n11.
b1.: mov -(r5),r0
mov -(r5),r1
asl r1
mov r0,(r1)
mov r0,(r5)+
jmp fetch
b2.: bis -(r5),-2(r5)
jmp fetch
b3.: mov -(r5),r0
com r0
bic r0,-2(r5)
jmp fetch
b4.: cmp -(r5),-(r5)
beq 1f
br 2f
b5.: cmp -(r5),-(r5)
bne 1f
br 2f
b6.: cmp -(r5),-(r5)
bge 1f
br 2f
b7.: cmp -(r5),-(r5)
bgt 1f
br 2f
b10.: cmp -(r5),-(r5)
ble 1f
br 2f
b11.: cmp -(r5),-(r5)
blt 1f
br 2f
1: mov $1,(r5)+
jmp fetch
2: clr (r5)+
jmp fetch
b12.: mov -(r5),r0
mov -(r5),ac
sub r0,lsh
mov ac,(r5)+
jmp fetch
b13.: mov -(r5),r0
mov -(r5),mq
mov r0,lsh
mov mq,(r5)+
jmp fetch
b14.: add -(r5),-2(r5)
jmp fetch
b15.: sub -(r5),-2(r5)
jmp fetch
b16.: mov -(r5),r0
mov -(r5),mq
mov r0,div
mov ac,(r5)+
jmp fetch
b17.: mov -(r5),mq
mov -(r5),mul
mov mq,(r5)+
jmp fetch
b20.: mov -(r5),r0
mov -(r5),mq
mov r0,div
mov mq,(r5)+
jmp fetch
b102.: mov -(r5),r0
mov -(r5),r1
asl r1
bis r0,(r1)
mov (r1),(r5)+
jmp fetch
b103.: mov -(r5),r0
mov -(r5),r1
asl r1
com r0
bic r0,(r1)
mov (r1),(r5)+
jmp fetch
b112.: mov -(r5),r0
mov -(r5),r1
asl r1
mov (r1),ac
sub r0,lsh
mov ac,(r1)
mov (r1),(r5)+
jmp fetch
b113.: mov -(r5),r0
mov -(r5),r1
asl r1
mov (r1),mq
mov r0,lsh
mov mq,(r1)
mov (r1),(r5)+
jmp fetch
b114.: mov -(r5),r0
mov -(r5),r1
asl r1
add r0,(r1)
mov (r1),(r5)+
jmp fetch
b115.: mov -(r5),r0
mov -(r5),r1
asl r1
sub r0,(r1)
mov (r1),(r5)+
jmp fetch
b116.: mov -(r5),r0
mov -(r5),r1
asl r1
mov (r1),mq
mov r0,div
mov ac,(r1)
mov (r1),(r5)+
jmp fetch
b117.: mov -(r5),mq
mov -(r5),r1
asl r1
mov (r1),mul
mov mq,(r1)
mov (r1),(r5)+
jmp fetch
b120.: mov -(r5),r0
mov -(r5),r1
asl r1
mov (r1),mq
mov r0,div
mov mq,(r1)
mov (r1),(r5)+
jmp fetch
u2.: neg -2(r5)
jmp fetch
u3.: mov -(r5),r1
asl r1
mov (r1),(r5)+
jmp fetch
u4.: tst -(r5)
beq 1f
clr (r5)+
jmp fetch
1: mov $1,(r5)+
jmp fetch
u5.: mov -(r5),r1
asl r1
inc (r1)
mov (r1),(r5)+
jmp fetch
u6.: mov -(r5),r1
asl r1
dec (r1)
mov (r1),(r5)+
jmp fetch
u7.: mov -(r5),r1
asl r1
mov (r1),(r5)+
inc (r1)
jmp fetch
u10.: mov -(r5),r1
asl r1
mov (r1),(r5)+
dec (r1)
jmp fetch
n2.: mov r5,-(sp)
tst (r5)+
jmp fetch
n3.: mov (sp)+,r5
n1.: mov r3,(r5)
mov -(r5),r3
mov r4,(r5)
mov r5,r4
jmp fetch
n4.: mov -(r5),r1
add -(r5),r1
asl r1
mov (r1),(r5)+
jmp fetch
in5.: tst -(r5)
n5.: mov (r3)+,(r5)+
jmp fetch
n6.: mov -2(r5),r3
jmp fetch
n7.: mov -(r5),r0
mov r4,r5
mov (r5),r4
mov r0,(r5)+
mov (r5),r3
jmp fetch
n10.: jmp 2(r3)
n11.: mov r4,r5
mov (r5)+,r4
mov (r5),r3
jmp fetch
|
aap/b
| 1,359
|
unix1_bdir/olibb/ctime.s
|
.globl .ctime
.globl ctime
.globl n11
.ctime:
.+2
.+2
mov r4,r5
cmp (r5)+,(r5)+
mov (r5)+,r0
asl r0
mov (r0)+,-(sp)
mov (r0)+,*$mq
mov (sp)+,*$ac
mov (r5)+,r0
asl r0
clrb 17(r0)
jsr pc,ctime
jmp n11
ctime:
mov r2,-(sp)
mov r3,-(sp)
/ mov $28.,febru
cmp *$ac,yrtime
blo 2f
bhi 1f
cmp *$mq,yrtime+2
bcs 2f
1:
mov *$ac,-(sp)
sub yrtime+2,*$mq
sbc (sp)
sub yrtime,(sp)
mov (sp)+,*$ac
mov $29.,febru
2:
mov $-4,*$lsh
mov $13500.,*$div
mov *$mq,r3
mov *$ac,*$mq
mov $2,*$lsh
mov $15.,*$div
add $15.,r0
jsr r5,tdiv; 10.
jsr r5,tdiv; 6
movb $':,-(r0)
jsr r5,tdiv; 10.
jsr r5,tdiv; 6
movb $':,-(r0)
mov r3,*$mq
mov $24.,*$div
mov *$mq,r3
mov *$ac,*$mq
jsr r5,tdiv; 10.
jsr r5,tdiv; 10.
mov $daytab,r2
1:
cmp (r2),r3
bgt 2f
sub (r2)+,r3
br 1b
2:
movb $' ,-(r0)
sub $daytab,r2
asl r2
add $montab+4,r2
inc r3
mov r3,*$mq
jsr r5,tdiv; 10.
tst *$mq
beq 2f
add $60,*$mq
movb *$mq,-(r0)
br 3f
2:
movb $' ,-(r0)
3:
movb $' ,-(r0)
movb -(r2),-(r0)
movb -(r2),-(r0)
movb -(r2),-(r0)
mov (sp)+,r3
mov (sp)+,r2
rts pc
tdiv:
clr *$ac
mov (r5)+,*$div
add $'0,*$ac
movb *$ac,-(r0)
rts r5
yrtime:
70310
11000
daytab: 31.
febru: 28.
31.
30.
31.
30.
31.
31.
30.
31.
30.
999.
montab:
<\0Jan>
<\0Feb>
<\0Mar>
<\0Apr>
<\0May>
<\0Jun>
<\0Jul>
<\0Aug>
<\0Sep>
<\0Oct>
<\0Nov>
<\0Dec>
|
aap/b
| 1,101
|
unix1_bdir/olibb/print.s
|
jmp 9f
.globl .printf
.printf:
.+2
s; 42
va; 36
c; 0
b1
iva; 30
va; 6
b1
L1:
s; 42
va; 34
x; .char
n2
a; 4
va; 36
u7
n3
b1
c; 45
b5
f; L2
ia; 34
c; 0
b4
f; L3
ix; .flush
n1
n11
L3:
ix; .putchar
n2
a; 34
n3
ix; 7f+0
n6
L2:
iva; 32
va; 30
u7
u3
b1
iva; 34
x; .char
n2
a; 4
va; 36
u7
n3
b1
z; L4
L5=144
L6:
L7=157
L10:
ia; 32
c; 0
b7
f; L11
iva; 32
a; 32
u2
b1
ix; .putchar
n2
c; 55
n3
L11:
ix; .printn
n2
a; 32
a; 34
c; 157
b4
f; L12
ic; 10
t; L13
L12:
ic; 12
L13:
n3
ix; 7f+0
n6
L14=143
L15:
ix; .putchar
n2
a; 32
n3
ix; 7f+0
n6
L16=163
L17:
iva; 40
c; 0
b1
L20:
iva; 34
x; .char
n2
a; 32
va; 40
u7
n3
b1
c; 0
b5
f; L21
ix; .putchar
n2
a; 34
n3
t; L20
L21:
ix; 7f+0
n6
t; .+24
L4:
4
L5
L6
L7
L10
L14
L15
L16
L17
ix; .putchar
n2
c; 45
n3
iva; 36
u10
iva; 30
u10
ix; 7f+0
n6
n11
7:
L1
.globl .printn
.printn:
.+2
s; 12
va; 10
a; 4
a; 6
b20
b1
f; L22
ix; .printn
n2
a; 10
a; 6
n3
L22:
ix; .putchar
n2
a; 4
a; 6
b16
c; 60
b14
n3
n11
7:
9: jsr r5,chain
0;
8:
|
aap/b
| 1,304
|
unix1_bdir/libb/ctime.s
|
.globl .ctime
.globl ctime
.globl n11
.ctime:
.+2
.+2
mov r4,r5
cmp (r5)+,(r5)+
mov (r5)+,r0
asl r0
mov (r0)+,-(sp)
mov (r0)+,mq
mov (sp)+,ac
mov (r5)+,r0
asl r0
clrb 17(r0)
jsr pc,ctime
jmp n11
ctime:
mov r2,-(sp)
mov r3,-(sp)
mov $28.,febru
cmp ac,yrtime
blo 2f
bhi 1f
cmp mq,yrtime+2
bcs 2f
1:
mov ac,-(sp)
sub yrtime+2,mq
sbc (sp)
sub yrtime,(sp)
mov (sp)+,ac
mov $29.,febru
2:
mov $-4,lsh
mov $13500.,div
mov mq,r3
mov ac,mq
mov $2,lsh
mov $15.,div
add $15.,r0
jsr r5,tdiv; 10.
jsr r5,tdiv; 6
movb $':,-(r0)
jsr r5,tdiv; 10.
jsr r5,tdiv; 6
movb $':,-(r0)
mov r3,mq
mov $24.,div
mov mq,r3
mov ac,mq
jsr r5,tdiv; 10.
jsr r5,tdiv; 10.
mov $daytab,r2
1:
cmp (r2),r3
bgt 2f
sub (r2)+,r3
br 1b
2:
movb $' ,-(r0)
sub $daytab,r2
asl r2
add $montab+4,r2
inc r3
mov r3,mq
jsr r5,tdiv; 10.
tst mq
beq 2f
add $60,mq
movb mq,-(r0)
br 3f
2:
movb $' ,-(r0)
3:
movb $' ,-(r0)
movb -(r2),-(r0)
movb -(r2),-(r0)
movb -(r2),-(r0)
mov (sp)+,r3
mov (sp)+,r2
rts pc
tdiv:
clr ac
mov (r5)+,div
add $'0,ac
movb ac,-(r0)
rts r5
yrtime:
70310
11000
daytab: 31.
febru: 28.
31.
30.
31.
30.
31.
31.
30.
31.
30.
999.
montab:
<\0Jan>
<\0Feb>
<\0Mar>
<\0Apr>
<\0May>
<\0Jun>
<\0Jul>
<\0Aug>
<\0Sep>
<\0Oct>
<\0Nov>
<\0Dec>
|
aap/pdp6
| 1,071
|
code/main.s
|
AC0==0
AC1==1
AC2==2
PDP==17
CPA==0
PRS==4
PTP==100
EXTERN PUTC,PUTS
EXTERN GETCH,GETC
EXTERN PUTN
EXTERN PTPUT
EXTERN DTTEST
ENTRY: JRST START
PDL: BLOCK 100
SP: XWD -100,PDL-1
START: MOVE PDP,SP
;; NUMBER TEST
; MOVE AC1,[-1234]
; PUSHJ PDP,PUTN
; MOVE AC1,[1234]
; PUSHJ PDP,PUTN
;; DECTAPE TEST
; JRST DTTEST
;; UUO TEST
; UUO1 123
;; ENABLE CLOCK PI ON CHANNEL 1
; CONO CPA,2001
;; ENABLE PI ON CHANNEL 1
; CONO PRS,2300
; JRST .
;; WRITE MESSAGE TO TTY
MOVSI AC2,440700
HRRI AC2,MSG
PUSHJ PDP,PUTS
;; WRITE FROM TTY TO PTP
PUSHJ PDP,GETC
; CONO PTP,20
; PUSHJ PDP,PTPUT
JRST .-1
HALT
;MSG: ASCIZ /Hello, world!
;yo! > /
MSG: ASCIZ /Hello, VCF PNW!
> /
; UUO HANDLER
UUO: 0
MOVSI AC2,440700
HRRI AC2,UUOMSG
PUSHJ PDP,PUTS
JRSTF @UUO
UUOMSG: ASCIZ /(UUO)/
CLK: ^D60
; CHANNEL 1 HANDLER
CH1: 0
SOSLE CLK
JRST CH1X
MOVEI AC2,^D60
MOVEM AC2,CLK
MOVSI AC2,440700
HRRI AC2,CH1MSG
PUSHJ PDP,PUTS
CH1X: CONO CPA,1001
JEN @CH1
CH1MSG: ASCIZ /*TICK*/
; UUO AND PI VECTORS
LOC 40
LOC40: 0
JSR UUO
JSR CH1
HALT 1
RELOC
END ENTRY
|
aappleby/metroboy
| 1,152
|
tests/micro_audio/audio3.s
|
.include "header.inc"
; Wave
; NR30 FF1A E--- ---- DAC power
; NR31 FF1B LLLL LLLL Length load (256-L)
; NR32 FF1C -VV- ---- Volume code (00=0%, 01=100%, 10=50%, 11=25%)
; NR33 FF1D FFFF FFFF Frequency LSB
; NR34 FF1E TL-- -FFF Trigger, Length enable, Frequency MSB
; DAC power
; Length
; Volume
; Frequency LSB
; Frequency MSB - can change
; Length enable
; Trigger
main:
; turn audio on
ld a, %11111111
ldh ($25), a
ldh ($26), a
; load waveform
ld a, $FF
ldh ($30), a
ldh ($31), a
ldh ($32), a
ldh ($33), a
ldh ($34), a
ldh ($35), a
ldh ($36), a
ldh ($37), a
ld a, $00
ldh ($38), a
ldh ($39), a
ldh ($3A), a
ldh ($3B), a
ldh ($3C), a
ldh ($3D), a
ldh ($3E), a
ldh ($3F), a
; FF1A E------- DAC power
ld a, %10000000
ldh ($1A), a
; FF1B LLLLLLLL Length load (256-L)
ld a, %11111111
ldh ($1B), a
; FF1C -VV----- Volume code (00=0%, 01=100%, 10=50%, 11=25%)
ld a, %00100000
ldh ($1C), a
; FF1D FFFFFFFF Frequency LSB
ld a, %11111111
ldh ($1D), a
; FF1E TL---FFF Trigger, Length enable, Frequency MSB
ld a, %11000011
ldh ($1E), a
; FF1A E------- DAC power
ld a, %00000000
ldh ($1A), a
end:
jr end
|
aappleby/metroboy
| 974
|
tests/micro_audio/spu_env_change.s
|
.include "header.inc"
; Square 1
; NR10 FF10 -PPPNSSS Sweep period, negate, shift
; NR11 FF11 DDLLLLLL Duty, Length load (64-L)
; NR12 FF12 VVVVAPPP Starting volume, Envelope add mode, period
; NR13 FF13 FFFFFFFF Frequency LSB
; NR14 FF14 TL---FFF Trigger, Length enable, Frequency MSB
; FF76 - pcm12
; FF77 - pcm34
; envelope
.macro nr10 ARGS p n s
ld a, (p << 4) | (n << 3) | s
ldh ($10), a
.endm
.macro nr11 ARGS d l
ld a, (d << 6) | l
ldh ($11), a
.endm
.macro nr12 ARGS v a p
ld a, (v << 4) | (a << 3) | p
ldh ($12), a
.endm
.macro trigger ARGS freq l
ld a, freq & $FF
ldh ($13), a
ld a, $80 | (l << 6) | (freq >> 8)
ldh ($14), a
.endm
;-------------------------------------------------------------------------------
main:
ld a, $FF
ldh ($25), a
ldh ($26), a
nr10 0 0 0
nr11 2 0
nr12 15 0 0
; 18
trigger (2047 - 47) 0
;nr12 10 1 0
;nr12 10 0 0
end:
ldh a, ($76)
and $0F
ld ($8000), a
ldh a, ($26)
and $0F
ld ($8002), a
jr end
|
aappleby/metroboy
| 2,198
|
tests/micro_audio/audio4.s
|
.include "header.inc"
; Noise
; FF1F ---- ---- Not used
; NR41 FF20 --LL LLLL Length load (64-L)
; NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period
; NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code
; NR44 FF23 TL-- ---- Trigger, Length enable
; Noise
; FF1F ---- ---- Not used
; NR42 FF21 VVVV APPP Starting volume, Envelope add mode, period
; NR43 FF22 SSSS WDDD Clock shift, Width mode of LFSR, Divisor code
; NR44 FF23 TL-- ---- Trigger, Length enable
; noise -
; reloading length register does _not_ extend sound
; continuously retriggering stops the sound
; continuously setting length enable bit stops the sound
; can change shift while noise is playing
; if length enabled
; continuous
; length - writable (63-L-1)
; volume - is weird
; env direction
; env period
; shift
; width
; divisor
; once
; length - writable (63-L-1)
; volume - is weird
; env direction - can't change
; env period
; shift
; width
; divisor
; if length not enabled
; length
; volume
; env direction
; env period
; shift
; width
; divisor
; cannot change volume during sound at all?
; cannot increase volume during playback?
; can change env period during sound
; cannot change env dir during sound
; length enabled, once -
; 1:
; 62:
; 63: ........ ........ ........ ........ s....... ........ ........ ....xxxx
; seems like writing once when env is 63 clears bits (xor)
; length is always writable, but actual sound length is _63_-_L_-_1_, wrapping around to 63 if L = 63
; can change dir/period during sound, but still acts weird
; if volume = 0 and env = down, sound never starts
main:
; turn audio on
ld a, %11111111
ldh ($25), a
ldh ($26), a
; FF20 --LLLLLL Length load (63-L-1)
ld a, %00000000
ldh ($20), a
; FF21 VVVVAPPP Starting volume, Envelope add mode, period
ld a, %11110000
ldh ($21), a
; FF22 SSSSWDDD Clock shift, Width mode of LFSR, Divisor code
ld a, %00100111
ldh ($22), a
; FF23 TL------ Trigger, Length enable
ld a, %10000000
ldh ($23), a
; FF23 TL------ Trigger, Length enable
ld a, %11000000
ldh ($23), a
end:
jr end
|
aappleby/metroboy
| 1,107
|
tests/micro_audio/audio1.s
|
.include "header.inc"
; Square 1
; NR10 FF10 -PPPNSSS Sweep period, negate, shift
; NR11 FF11 DDLLLLLL Duty, Length load (64-L)
; NR12 FF12 VVVVAPPP Starting volume, Envelope add mode, period
; NR13 FF13 FFFFFFFF Frequency LSB
; NR14 FF14 TL---FFF Trigger, Length enable, Frequency MSB
; starting with sweep off then turning it on after trigger does something weird
; starting with %01110000 and changing to %01110111 after trigger is super weird
; starting with %01111000 and changing to %01111111 after trigger also super weird, sounds like above
main:
; turn audio on
ld a, %11111111
ldh ($25), a
ldh ($26), a
; FF10 -PPPNSSS Sweep period, negate, shift
ld a, %01111000
ldh ($10), a
; FF11 DDLLLLLL Duty, Length load (64-L)
ld a, %10000000
ldh ($11), a
; FF12 VVVVAPPP Starting volume, Envelope add mode, period
ld a, %11110000
ldh ($12), a
; FF13 FFFFFFFF Frequency LSB
ld a, %01111111
ldh ($13), a
; FF14 TL---FFF Trigger, Length enable, Frequency MSB
ld a, %11000111
ldh ($14), a
; FF10 -PPPNSSS Sweep period, negate, shift
ld a, %01111111
ldh ($10), a
end:
jr end
|
aappleby/metroboy
| 1,846
|
tests/cpu_instrs/source/05-op rp.s
|
; Tests BC/DE/HL arithmetic
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $0B,0,0 ; DEC BC
.byte $1B,0,0 ; DEC DE
.byte $2B,0,0 ; DEC HL
.byte $03,0,0 ; INC BC
.byte $13,0,0 ; INC DE
.byte $23,0,0 ; INC HL
.byte $09,0,0 ; ADD HL,BC
.byte $19,0,0 ; ADD HL,DE
.byte $29,0,0 ; ADD HL,HL
instrs_end:
test_instr:
ld c,$00
call test
ld c,$10
call test
ld c,$E0
call test
ld c,$F0
call test
ret
test:
; Go through each value for HL
ld hl,values
hl_loop:
ld e,(hl)
inc hl
ld d,(hl)
inc hl
push hl
; Go through each value for BC, DE, A
ld hl,values
values_loop:
push bc
push de
push hl
push de
push bc
; BC
ld c,(hl)
inc hl
ld b,(hl)
inc hl
; DE
ld e,(hl)
inc hl
ld d,(hl)
inc hl
; HL, AF
pop af
ld a,(hl)
pop hl
; call print_regs
jp instr
instr_done:
; Checksum registers
call checksum_af_bc_de_hl
pop hl
pop de
pop bc
inc hl
inc hl
ld a,l
cp <values_end
jr nz,values_loop
pop hl
ld a,l
cp <values_end
jr nz,hl_loop
ret
values:
.word $0000,$0001,$000F,$0010,$001F,$007F,$0080,$00FF
.word $0100,$0F00,$1F00,$1000,$7FFF,$8000,$FFFF
values_end:
.word $0000,$0001,$000F,$0010,$001F,$007F,$0080,$00FF
.word $0100,$0F00,$1F00,$1000,$7FFF,$8000,$FFFF
checksums:
.byte $C0,$A1,$36,$A3,$BE,$15,$B8,$2B,$9F,$93,$C6,$C2,$86,$C0,$07,$81,$0F,$75,$35,$38,$6B,$C7,$0A,$1B,$06,$68,$4B,$42,$64,$B4,$8C,$18,$FB,$6C,$31,$94,
|
aappleby/metroboy
| 7,694
|
tests/cpu_instrs/source/09-op r,r.s
|
; Tests most register instructions.
; Takes 10 seconds.
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $00,0,0 ; NOP
.byte $2F,0,0 ; CPL
.byte $37,0,0 ; SCF
.byte $3F,0,0 ; CCF
.byte $B0,0,0 ; OR B
.byte $B1,0,0 ; OR C
.byte $B2,0,0 ; OR D
.byte $B3,0,0 ; OR E
.byte $B4,0,0 ; OR H
.byte $B5,0,0 ; OR L
.byte $B7,0,0 ; OR A
.byte $B8,0,0 ; CP B
.byte $B9,0,0 ; CP C
.byte $BA,0,0 ; CP D
.byte $BB,0,0 ; CP E
.byte $BC,0,0 ; CP H
.byte $BD,0,0 ; CP L
.byte $BF,0,0 ; CP A
.byte $80,0,0 ; ADD B
.byte $81,0,0 ; ADD C
.byte $82,0,0 ; ADD D
.byte $83,0,0 ; ADD E
.byte $84,0,0 ; ADD H
.byte $85,0,0 ; ADD L
.byte $87,0,0 ; ADD A
.byte $88,0,0 ; ADC B
.byte $89,0,0 ; ADC C
.byte $8A,0,0 ; ADC D
.byte $8B,0,0 ; ADC E
.byte $8C,0,0 ; ADC H
.byte $8D,0,0 ; ADC L
.byte $8F,0,0 ; ADC A
.byte $90,0,0 ; SUB B
.byte $91,0,0 ; SUB C
.byte $92,0,0 ; SUB D
.byte $93,0,0 ; SUB E
.byte $94,0,0 ; SUB H
.byte $95,0,0 ; SUB L
.byte $97,0,0 ; SUB A
.byte $98,0,0 ; SBC B
.byte $99,0,0 ; SBC C
.byte $9A,0,0 ; SBC D
.byte $9B,0,0 ; SBC E
.byte $9C,0,0 ; SBC H
.byte $9D,0,0 ; SBC L
.byte $9F,0,0 ; SBC A
.byte $A0,0,0 ; AND B
.byte $A1,0,0 ; AND C
.byte $A2,0,0 ; AND D
.byte $A3,0,0 ; AND E
.byte $A4,0,0 ; AND H
.byte $A5,0,0 ; AND L
.byte $A7,0,0 ; AND A
.byte $A8,0,0 ; XOR B
.byte $A9,0,0 ; XOR C
.byte $AA,0,0 ; XOR D
.byte $AB,0,0 ; XOR E
.byte $AC,0,0 ; XOR H
.byte $AD,0,0 ; XOR L
.byte $AF,0,0 ; XOR A
.byte $05,0,0 ; DEC B
.byte $0D,0,0 ; DEC C
.byte $15,0,0 ; DEC D
.byte $1D,0,0 ; DEC E
.byte $25,0,0 ; DEC H
.byte $2D,0,0 ; DEC L
.byte $3D,0,0 ; DEC A
.byte $04,0,0 ; INC B
.byte $0C,0,0 ; INC C
.byte $14,0,0 ; INC D
.byte $1C,0,0 ; INC E
.byte $24,0,0 ; INC H
.byte $2C,0,0 ; INC L
.byte $3C,0,0 ; INC A
.byte $07,0,0 ; RLCA
.byte $17,0,0 ; RLA
.byte $0F,0,0 ; RRCA
.byte $1F,0,0 ; RRA
.byte $CB,$00,0 ; RLC B
.byte $CB,$01,0 ; RLC C
.byte $CB,$02,0 ; RLC D
.byte $CB,$03,0 ; RLC E
.byte $CB,$04,0 ; RLC H
.byte $CB,$05,0 ; RLC L
.byte $CB,$07,0 ; RLC A
.byte $CB,$08,0 ; RRC B
.byte $CB,$09,0 ; RRC C
.byte $CB,$0A,0 ; RRC D
.byte $CB,$0B,0 ; RRC E
.byte $CB,$0C,0 ; RRC H
.byte $CB,$0D,0 ; RRC L
.byte $CB,$0F,0 ; RRC A
.byte $CB,$10,0 ; RL B
.byte $CB,$11,0 ; RL C
.byte $CB,$12,0 ; RL D
.byte $CB,$13,0 ; RL E
.byte $CB,$14,0 ; RL H
.byte $CB,$15,0 ; RL L
.byte $CB,$17,0 ; RL A
.byte $CB,$18,0 ; RR B
.byte $CB,$19,0 ; RR C
.byte $CB,$1A,0 ; RR D
.byte $CB,$1B,0 ; RR E
.byte $CB,$1C,0 ; RR H
.byte $CB,$1D,0 ; RR L
.byte $CB,$1F,0 ; RR A
.byte $CB,$20,0 ; SLA B
.byte $CB,$21,0 ; SLA C
.byte $CB,$22,0 ; SLA D
.byte $CB,$23,0 ; SLA E
.byte $CB,$24,0 ; SLA H
.byte $CB,$25,0 ; SLA L
.byte $CB,$27,0 ; SLA A
.byte $CB,$28,0 ; SRA B
.byte $CB,$29,0 ; SRA C
.byte $CB,$2A,0 ; SRA D
.byte $CB,$2B,0 ; SRA E
.byte $CB,$2C,0 ; SRA H
.byte $CB,$2D,0 ; SRA L
.byte $CB,$2F,0 ; SRA A
.byte $CB,$30,0 ; SWAP B
.byte $CB,$31,0 ; SWAP C
.byte $CB,$32,0 ; SWAP D
.byte $CB,$33,0 ; SWAP E
.byte $CB,$34,0 ; SWAP H
.byte $CB,$35,0 ; SWAP L
.byte $CB,$37,0 ; SWAP A
.byte $CB,$38,0 ; SRL B
.byte $CB,$39,0 ; SRL C
.byte $CB,$3A,0 ; SRL D
.byte $CB,$3B,0 ; SRL E
.byte $CB,$3C,0 ; SRL H
.byte $CB,$3D,0 ; SRL L
.byte $CB,$3F,0 ; SRL A
instrs_end:
test_instr:
ld c,$00
call test
ld c,$F0
call test
ret
test:
; Go through each value for A
ld hl,values
a_loop:
ld b,(hl)
push hl
; Go through each value for other registers
ld hl,values
values_loop:
push bc
push hl
push bc
; BC
ld a,(hl+)
ld b,a
ld a,(hl+)
ld c,a
; HL
ld a,(hl+)
ld d,a
ld a,(hl+)
ld e,a
push de
; DE
ld a,(hl+)
ld d,a
ld a,(hl+)
ld e,a
pop hl
pop af
; call print_regs
jp instr
instr_done:
; Checksum registers
call checksum_af_bc_de_hl
pop hl
pop bc
inc hl
ld a,l
cp <values_end
jr nz,values_loop
pop hl
inc hl
ld a,l
cp <values_end
jr nz,a_loop
ret
values:
.byte $00,$01,$0F,$10,$1F,$7F,$80,$F0,$FF
values_end:
.byte $00,$01,$0F,$10,$1F,$7F,$80,$F0,$FF
checksums:
.byte $7C,$55,$BD,$05,$BA,$C7,$AC,$D1,$74,$6D,$82,$4A,$0F,$06,$2A,$C5
.byte $FA,$97,$9B,$9D,$C3,$32,$A0,$78,$00,$C1,$9F,$69,$C0,$D1,$C2,$A1
.byte $55,$0D,$3F,$C8,$09,$7D,$97,$92,$CE,$66,$30,$56,$95,$F3,$01,$A1
.byte $5B,$97,$54,$4C,$56,$FC,$A0,$89,$42,$F8,$7B,$2A,$E6,$7C,$03,$40
.byte $45,$60,$C5,$A8,$B7,$BF,$B0,$EF,$A0,$7A,$1B,$4F,$FB,$22,$B4,$33
.byte $06,$3D,$B5,$C7,$3C,$A4,$D5,$23,$C1,$BE,$75,$8B,$E0,$9B,$98,$BB
.byte $0E,$75,$D9,$E6,$82,$A7,$E2,$66,$CD,$78,$4F,$E8,$8E,$D4,$2D,$3E
.byte $88,$5C,$58,$C7,$F9,$20,$5F,$B9,$A8,$E4,$CA,$5E,$C8,$DB,$88,$94
.byte $A3,$0D,$87,$60,$8B,$BA,$2B,$27,$41,$88,$83,$B1,$0A,$41,$9E,$D6
.byte $98,$8D,$19,$B7,$13,$C6,$D5,$BF,$83,$CE,$74,$9F,$00,$34,$07,$5E
.byte $F0,$E1,$1A,$68,$8F,$BA,$85,$A7,$A0,$46,$06,$A5,$75,$F9,$83,$48
.byte $12,$EF,$1B,$03,$C8,$FB,$79,$EA,$9B,$00,$6C,$A9,$0D,$5E,$CB,$57
.byte $41,$1B,$4B,$0C,$B2,$08,$D8,$E3,$43,$07,$E1,$93,$34,$73,$23,$C9
.byte $18,$2F,$38,$F9,$D1,$3B,$AB,$5A,$BF,$C6,$F8,$03,$50,$0C,$A4,$32
.byte $6B,$06,$7E,$FE,$ED,$8B,$D4,$15,$29,$46,$6D,$24,$6E,$5B,$15,$1A
.byte $32,$AE,$87,$B0,$DC,$20,$AC,$4B,$2B,$63,$60,$C7,$C1,$92,$75,$AA
.byte $6F,$CA,$17,$53,$5A,$C5,$78,$EA,$61,$01,$10,$83,$DD,$08,$D8,$78
.byte $CA,$0B,$F5,$1F,$92,$55,$08,$01,$7F,$EA,$CD,$9B,$2A,$AA,$73,$17
.byte $E0,$9F,$D0,$BA,$E7,$73,$72,$3D,$B7,$95,$2F,$3B,$A7,$78,$50,$36
.byte $81,$04,$5B,$9E,$9A,$DE,$A4,$DD,$21,$B2,$9B,$36,$9F,$D7,$C8,$32
.byte $48,$0E,$FC,$E5,$55,$C3,$53,$75,$A4,$ED,$A9,$E0,$9E,$78,$A7,$1D
.byte $B8,$F4,$7C,$D6,$90,$2A,$03,$87,$81,$D8,$D5,$90,$63,$02,$C4,$52
.byte $C2,$BE,$85,$B3,$32,$9A,$9E,$2D,$E3,$FB,$22,$47,$8E,$65,$08,$73
.byte $72,$5A,$73,$95,$ED,$EC,$59,$9D,$C8,$67,$68,$F1,$4B,$ED,$41,$D5
.byte $68,$39,$75,$F3,$FC,$09,$EF,$0D,$20,$2B,$43,$A3,$69,$AA,$89,$4F
.byte $84,$87,$7B,$58,$42,$0A,$56,$EF,$1B,$0E,$19,$CA,$6F,$1B,$F9,$17
.byte $EA,$B6,$4C,$B2,$1A,$C4,$C0,$B1,$E2,$B2,$45,$4E,$91,$0A,$8D,$AE
.byte $17,$31,$55,$A3,$1B,$69,$72,$D8,$03,$E9,$55,$8D,$87,$27,$36,$63
.byte $E6,$85,$12,$D1,$F2,$32,$97,$4D,$B5,$FA,$08,$A9,$97,$2A,$5A,$C2
.byte $FD,$2D,$A4,$27,$57,$7C,$EC,$BD,$CC,$67,$19,$21,$46,$D4,$CD,$D6
.byte $CB,$55,$D4,$E2,$9E,$F3,$32,$2E,$AA,$F8,$BB,$B3,$F6,$3A,$CC,$08
.byte $64,$8B,$C2,$5F,$58,$66,$AF,$67,$B3,$44,$2C,$66,$72,$E7,$3B,$3F
.byte $5B,$87,$0C,$17,$58,$E2,$B4,$A0,$70,$18,$81,$E6,$42,$56,$12,$CE
.byte $BB,$13,$46,$3C,$BE,$5A,$FB,$53
|
aappleby/metroboy
| 3,131
|
tests/cpu_instrs/source/07-jr,jp,call,ret,rst.s
|
; Tests branch instructions
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
; JR cond,skip
; INC A
; skip:
.byte $18,$01,$3C ; JR *+3
.byte $20,$01,$3C ; JR NZ,*+3
.byte $28,$01,$3C ; JR Z,*+3
.byte $30,$01,$3C ; JR NC,*+3
.byte $38,$01,$3C ; JR C,*+3
.byte $C2,<taken,>taken ; JP NZ,taken
.byte $C3,<taken,>taken ; JP taken
.byte $CA,<taken,>taken ; JP Z,taken
.byte $D2,<taken,>taken ; JP NC,taken
.byte $DA,<taken,>taken ; JP C,taken
.byte $C4,<taken,>taken ; CALL NZ,taken
.byte $CC,<taken,>taken ; CALL Z,taken
.byte $CD,<taken,>taken ; CALL taken
.byte $D4,<taken,>taken ; CALL NC,taken
.byte $DC,<taken,>taken ; CALL C,taken
; RET cond
; INC A
.byte $C0,$3C,0 ; RET NZ
.byte $C8,$3C,0 ; RET Z
.byte $C9,$3C,0 ; RET
.byte $D0,$3C,0 ; RET NC
.byte $D8,$3C,0 ; RET C
.byte $D9,$3C,0 ; RETI
; RST
; can only easily test this one on devcart
.byte $C7,0,0 ; RST $00
.ifndef BUILD_DEVCART
.byte $CF,0,0 ; RST $08
.byte $D7,0,0 ; RST $10
.byte $DF,0,0 ; RST $18
.byte $E7,0,0 ; RST $20
.byte $EF,0,0 ; RST $28
.byte $F7,0,0 ; RST $30
.byte $FF,0,0 ; RST $38
.endif
instrs_end:
test_instr:
wreg IE,0 ; disable interrupts, since RETI does EI
; Go through all 16 combinations of flags
ld bc,$1200
-
; Fill 4 bytes of new stack
ld a,$12
ld ($DF80-2),a
ld a,$34
ld ($DF80-3),a
ld a,$56
ld ($DF80-4),a
ld a,$78
ld ($DF80-5),a
; Set AF
push bc
pop af
; Switch to new stack
ld (temp),sp
ld sp,$DF80
; Set return address
ld de,instr+3
push de
jp instr
instr_done:
inc a
taken:
di ; RETI enables interrupts
; Save new SP and switch to yet another stack
ld (temp+2),sp
ld sp,$DF70
; Checksum A and SP
call update_crc_fast
ld a,(temp+2)
call update_crc_fast
ld a,(temp+3)
call update_crc_fast
; Checksum 4 bytes of stack
ld a,($DF80-2)
call update_crc_fast
ld a,($DF80-3)
call update_crc_fast
ld a,($DF80-4)
call update_crc_fast
ld a,($DF80-5)
call update_crc_fast
ldsp temp
ld a,c
add $10
ld c,a
jr nz,-
ret
checksums:
.byte $EC,$A4,$94,$79,$C4,$00,$96,$2C,$C4,$64,$90,$33,$77,$C7,$0A,$D4
.byte $77,$A3,$0C,$CB,$79,$E7,$7E,$AE,$DA,$DC,$03,$F7,$4F,$9F,$E9,$20
.byte $72,$12,$DA,$01,$44,$6A,$4D,$8F,$D1,$79,$30,$4C,$AA,$37,$F2,$6A
.byte $97,$EA,$56,$5F,$32,$28,$C7,$D1,$49,$66,$05,$F7,$80,$0F,$BA,$8E
.byte $41,$E2,$A4,$9A,$2D,$2D,$8C,$72,$A5,$13,$76,$A8,$64,$FE,$68,$BC
.byte $2D,$2D,$8C,$72,$50,$96,$24,$27,$50,$96,$24,$27,$50,$96,$24,$27
.byte $50,$96,$24,$27,$50,$96,$24,$27,$50,$96,$24,$27,$50,$96,$24,$27
.byte $50,$96,$24,$27
.include "multi_custom.s"
|
aappleby/metroboy
| 1,217
|
tests/cpu_instrs/source/02-interrupts.s
|
; Tests DI, EI, and HALT (STOP proved untestable)
.include "shell.inc"
main:
wreg IE,$04
set_test 2,"EI"
ei
ld bc,0
push bc
pop bc
inc b
wreg IF,$04
interrupt_addr:
dec b
jp nz,test_failed
ld hl,sp-2
ldi a,(hl)
cp <interrupt_addr
jp nz,test_failed
ld a,(hl)
cp >interrupt_addr
jp nz,test_failed
lda IF
and $04
jp nz,test_failed
set_test 3,"DI"
di
ld bc,0
push bc
pop bc
wreg IF,$04
ld hl,sp-2
ldi a,(hl)
or (hl)
jp nz,test_failed
lda IF
and $04
jp z,test_failed
set_test 4,"Timer doesn't work"
wreg TAC,$05
wreg TIMA,0
wreg IF,0
delay 500
lda IF
delay 500
and $04
jp nz,test_failed
delay 500
lda IF
and $04
jp z,test_failed
pop af
set_test 5,"HALT"
wreg TAC,$05
wreg TIMA,0
wreg IF,0
halt ; timer interrupt will exit halt
nop ; avoids DMG bug
lda IF
and $04
jp z,test_failed
jp tests_passed
.bank 0 slot 0
.org $50
inc a
ret
|
aappleby/metroboy
| 2,530
|
tests/cpu_instrs/source/08-misc instrs.s
|
; Tests miscellaneous instructions
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $F0,$91,0 ; LDH A,($91)
.byte $E0,$91,0 ; LDH ($91),A
.byte $F2,$00,0 ; LDH A,(C)
.byte $E2,$00,0 ; LDH (C),A
.byte $FA,$91,$FF ; LD A,($FF91)
.byte $EA,$91,$FF ; LD ($FF91),A
.byte $08,$91,$FF ; LD ($FF91),SP
.byte $01,$23,$01 ; LD BC,$0123
.byte $11,$23,$01 ; LD DE,$0123
.byte $21,$23,$01 ; LD HL,$0123
.byte $31,$23,$01 ; LD SP,$0123
.byte $F5,0,0 ; PUSH AF
.byte $C5,0,0 ; PUSH BC
.byte $D5,0,0 ; PUSH DE
.byte $E5,0,0 ; PUSH HL
.byte $F1,0,0 ; POP AF
.byte $C1,0,0 ; POP BC
.byte $D1,0,0 ; POP DE
.byte $E1,0,0 ; POP HL
instrs_end:
test_instr:
; C = flags register
ld c,$00
call test
ld c,$10
call test
ld c,$E0
call test
ld c,$F0
call test
ret
test:
; Fill RAM
ld a,$FE
ld ($FF90),a
ld a,$DC
ld ($FF91),a
ld a,$BA
ld ($FF92),a
; Fill stack
ld a,$13
ld ($DF80),a
ld a,$57
ld ($DF80-1),a
ld a,$9B
ld ($DF80-2),a
ld a,$DF
ld ($DF80-3),a
; Set registers
ld b,$12
push bc
ld bc,$5691
ld de,$9ABC
ld hl,$DEF0
pop af
; Switch stack
ld (temp),sp
ld sp,$DF80-2
jp instr
instr_done:
; Save new SP and switch to another stack
ld (temp+2),sp
ld sp,$DF70
call checksum_af_bc_de_hl
; Checksum SP
ld a,(temp+2)
call update_crc_fast
ld a,(temp+3)
call update_crc_fast
; Checksum RAM
ld a,($FF90)
call update_crc_fast
ld a,($FF91)
call update_crc_fast
ld a,($FF92)
call update_crc_fast
; Checksum stack
ld a,($DF80)
call update_crc_fast
ld a,($DF80-1)
call update_crc_fast
ld a,($DF80-2)
call update_crc_fast
ld a,($DF80-3)
call update_crc_fast
; Restore SP
ldsp temp
ret
checksums:
.byte $4D,$FF,$15,$97,$6D,$A7,$35,$65,$4D,$FF,$15,$97,$6D,$A7,$35,$65,$4D,$FF,$15,$97,$6D,$A7,$35,$65,$AD,$FA,$5E,$41,$D0,$78,$79,$C1,$AF,$66,$99,$34,$0D,$E1,$97,$99,$6F,$D0,$6F,$5D,$C3,$1F,$A3,$8A,$C2,$F1,$9C,$F3,$C1,$C3,$DC,$78,$C0,$2D,$E3,$01,$8F,$C4,$0F,$44,$95,$22,$6A,$39,$61,$C5,$AB,$55,$FB,$DF,$2C,$52,
|
aappleby/metroboy
| 9,892
|
tests/cpu_instrs/source/10-bit ops.s
|
; Tests most register instructions.
; Takes 15 seconds.
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $CB,$40,0 ; BIT 0,B
.byte $CB,$41,0 ; BIT 0,C
.byte $CB,$42,0 ; BIT 0,D
.byte $CB,$43,0 ; BIT 0,E
.byte $CB,$44,0 ; BIT 0,H
.byte $CB,$45,0 ; BIT 0,L
.byte $CB,$47,0 ; BIT 0,A
.byte $CB,$48,0 ; BIT 1,B
.byte $CB,$49,0 ; BIT 1,C
.byte $CB,$4A,0 ; BIT 1,D
.byte $CB,$4B,0 ; BIT 1,E
.byte $CB,$4C,0 ; BIT 1,H
.byte $CB,$4D,0 ; BIT 1,L
.byte $CB,$4F,0 ; BIT 1,A
.byte $CB,$50,0 ; BIT 2,B
.byte $CB,$51,0 ; BIT 2,C
.byte $CB,$52,0 ; BIT 2,D
.byte $CB,$53,0 ; BIT 2,E
.byte $CB,$54,0 ; BIT 2,H
.byte $CB,$55,0 ; BIT 2,L
.byte $CB,$57,0 ; BIT 2,A
.byte $CB,$58,0 ; BIT 3,B
.byte $CB,$59,0 ; BIT 3,C
.byte $CB,$5A,0 ; BIT 3,D
.byte $CB,$5B,0 ; BIT 3,E
.byte $CB,$5C,0 ; BIT 3,H
.byte $CB,$5D,0 ; BIT 3,L
.byte $CB,$5F,0 ; BIT 3,A
.byte $CB,$60,0 ; BIT 4,B
.byte $CB,$61,0 ; BIT 4,C
.byte $CB,$62,0 ; BIT 4,D
.byte $CB,$63,0 ; BIT 4,E
.byte $CB,$64,0 ; BIT 4,H
.byte $CB,$65,0 ; BIT 4,L
.byte $CB,$67,0 ; BIT 4,A
.byte $CB,$68,0 ; BIT 5,B
.byte $CB,$69,0 ; BIT 5,C
.byte $CB,$6A,0 ; BIT 5,D
.byte $CB,$6B,0 ; BIT 5,E
.byte $CB,$6C,0 ; BIT 5,H
.byte $CB,$6D,0 ; BIT 5,L
.byte $CB,$6F,0 ; BIT 5,A
.byte $CB,$70,0 ; BIT 6,B
.byte $CB,$71,0 ; BIT 6,C
.byte $CB,$72,0 ; BIT 6,D
.byte $CB,$73,0 ; BIT 6,E
.byte $CB,$74,0 ; BIT 6,H
.byte $CB,$75,0 ; BIT 6,L
.byte $CB,$77,0 ; BIT 6,A
.byte $CB,$78,0 ; BIT 7,B
.byte $CB,$79,0 ; BIT 7,C
.byte $CB,$7A,0 ; BIT 7,D
.byte $CB,$7B,0 ; BIT 7,E
.byte $CB,$7C,0 ; BIT 7,H
.byte $CB,$7D,0 ; BIT 7,L
.byte $CB,$7F,0 ; BIT 7,A
.byte $CB,$80,0 ; RES 0,B
.byte $CB,$81,0 ; RES 0,C
.byte $CB,$82,0 ; RES 0,D
.byte $CB,$83,0 ; RES 0,E
.byte $CB,$84,0 ; RES 0,H
.byte $CB,$85,0 ; RES 0,L
.byte $CB,$87,0 ; RES 0,A
.byte $CB,$88,0 ; RES 1,B
.byte $CB,$89,0 ; RES 1,C
.byte $CB,$8A,0 ; RES 1,D
.byte $CB,$8B,0 ; RES 1,E
.byte $CB,$8C,0 ; RES 1,H
.byte $CB,$8D,0 ; RES 1,L
.byte $CB,$8F,0 ; RES 1,A
.byte $CB,$90,0 ; RES 2,B
.byte $CB,$91,0 ; RES 2,C
.byte $CB,$92,0 ; RES 2,D
.byte $CB,$93,0 ; RES 2,E
.byte $CB,$94,0 ; RES 2,H
.byte $CB,$95,0 ; RES 2,L
.byte $CB,$97,0 ; RES 2,A
.byte $CB,$98,0 ; RES 3,B
.byte $CB,$99,0 ; RES 3,C
.byte $CB,$9A,0 ; RES 3,D
.byte $CB,$9B,0 ; RES 3,E
.byte $CB,$9C,0 ; RES 3,H
.byte $CB,$9D,0 ; RES 3,L
.byte $CB,$9F,0 ; RES 3,A
.byte $CB,$A0,0 ; RES 4,B
.byte $CB,$A1,0 ; RES 4,C
.byte $CB,$A2,0 ; RES 4,D
.byte $CB,$A3,0 ; RES 4,E
.byte $CB,$A4,0 ; RES 4,H
.byte $CB,$A5,0 ; RES 4,L
.byte $CB,$A7,0 ; RES 4,A
.byte $CB,$A8,0 ; RES 5,B
.byte $CB,$A9,0 ; RES 5,C
.byte $CB,$AA,0 ; RES 5,D
.byte $CB,$AB,0 ; RES 5,E
.byte $CB,$AC,0 ; RES 5,H
.byte $CB,$AD,0 ; RES 5,L
.byte $CB,$AF,0 ; RES 5,A
.byte $CB,$B0,0 ; RES 6,B
.byte $CB,$B1,0 ; RES 6,C
.byte $CB,$B2,0 ; RES 6,D
.byte $CB,$B3,0 ; RES 6,E
.byte $CB,$B4,0 ; RES 6,H
.byte $CB,$B5,0 ; RES 6,L
.byte $CB,$B7,0 ; RES 6,A
.byte $CB,$B8,0 ; RES 7,B
.byte $CB,$B9,0 ; RES 7,C
.byte $CB,$BA,0 ; RES 7,D
.byte $CB,$BB,0 ; RES 7,E
.byte $CB,$BC,0 ; RES 7,H
.byte $CB,$BD,0 ; RES 7,L
.byte $CB,$BF,0 ; RES 7,A
.byte $CB,$C0,0 ; SET 0,B
.byte $CB,$C1,0 ; SET 0,C
.byte $CB,$C2,0 ; SET 0,D
.byte $CB,$C3,0 ; SET 0,E
.byte $CB,$C4,0 ; SET 0,H
.byte $CB,$C5,0 ; SET 0,L
.byte $CB,$C7,0 ; SET 0,A
.byte $CB,$C8,0 ; SET 1,B
.byte $CB,$C9,0 ; SET 1,C
.byte $CB,$CA,0 ; SET 1,D
.byte $CB,$CB,0 ; SET 1,E
.byte $CB,$CC,0 ; SET 1,H
.byte $CB,$CD,0 ; SET 1,L
.byte $CB,$CF,0 ; SET 1,A
.byte $CB,$D0,0 ; SET 2,B
.byte $CB,$D1,0 ; SET 2,C
.byte $CB,$D2,0 ; SET 2,D
.byte $CB,$D3,0 ; SET 2,E
.byte $CB,$D4,0 ; SET 2,H
.byte $CB,$D5,0 ; SET 2,L
.byte $CB,$D7,0 ; SET 2,A
.byte $CB,$D8,0 ; SET 3,B
.byte $CB,$D9,0 ; SET 3,C
.byte $CB,$DA,0 ; SET 3,D
.byte $CB,$DB,0 ; SET 3,E
.byte $CB,$DC,0 ; SET 3,H
.byte $CB,$DD,0 ; SET 3,L
.byte $CB,$DF,0 ; SET 3,A
.byte $CB,$E0,0 ; SET 4,B
.byte $CB,$E1,0 ; SET 4,C
.byte $CB,$E2,0 ; SET 4,D
.byte $CB,$E3,0 ; SET 4,E
.byte $CB,$E4,0 ; SET 4,H
.byte $CB,$E5,0 ; SET 4,L
.byte $CB,$E7,0 ; SET 4,A
.byte $CB,$E8,0 ; SET 5,B
.byte $CB,$E9,0 ; SET 5,C
.byte $CB,$EA,0 ; SET 5,D
.byte $CB,$EB,0 ; SET 5,E
.byte $CB,$EC,0 ; SET 5,H
.byte $CB,$ED,0 ; SET 5,L
.byte $CB,$EF,0 ; SET 5,A
.byte $CB,$F0,0 ; SET 6,B
.byte $CB,$F1,0 ; SET 6,C
.byte $CB,$F2,0 ; SET 6,D
.byte $CB,$F3,0 ; SET 6,E
.byte $CB,$F4,0 ; SET 6,H
.byte $CB,$F5,0 ; SET 6,L
.byte $CB,$F7,0 ; SET 6,A
.byte $CB,$F8,0 ; SET 7,B
.byte $CB,$F9,0 ; SET 7,C
.byte $CB,$FA,0 ; SET 7,D
.byte $CB,$FB,0 ; SET 7,E
.byte $CB,$FC,0 ; SET 7,H
.byte $CB,$FD,0 ; SET 7,L
.byte $CB,$FF,0 ; SET 7,A
instrs_end:
test_instr:
ld c,$00
call test
ld c,$F0
call test
ret
test:
; Go through each value for A
ld hl,values
a_loop:
ld b,(hl)
push hl
; Go through each value for other registers
ld hl,values
values_loop:
push bc
push hl
push bc
; BC
ld a,(hl+)
ld b,a
ld a,(hl+)
ld c,a
; HL
ld a,(hl+)
ld d,a
ld a,(hl+)
ld e,a
push de
; DE
ld a,(hl+)
ld d,a
ld a,(hl+)
ld e,a
pop hl
pop af
; call print_regs
jp instr
instr_done:
; Checksum registers
call checksum_af_bc_de_hl
pop hl
pop bc
inc hl
ld a,l
cp <values_end
jr nz,values_loop
pop hl
inc hl
ld a,l
cp <values_end
jr nz,a_loop
ret
values:
.byte $00,$01,$02,$04,$08,$10,$20,$40,$80,$FF
values_end:
.byte $00,$01,$02,$04,$08,$10,$20,$40,$80,$FF
checksums:
.byte $46,$51,$4A,$16,$D4,$18,$B2,$4E,$ED,$B5,$15,$EA,$74,$66,$66,$3E
.byte $C2,$F3,$7F,$6A,$63,$CA,$62,$21,$72,$1E,$E4,$83,$6A,$56,$41,$1D
.byte $91,$90,$DB,$38,$54,$0A,$6C,$24,$02,$9E,$EA,$5B,$6D,$A7,$CB,$80
.byte $B4,$0B,$F3,$0F,$40,$38,$75,$BB,$AF,$30,$2B,$E5,$BD,$97,$D0,$33
.byte $83,$CB,$FD,$0A,$BB,$21,$93,$95,$28,$2F,$A2,$F6,$1B,$5F,$47,$E5
.byte $A3,$2E,$39,$63,$6C,$E0,$02,$BB,$78,$F1,$BA,$CB,$2C,$9F,$49,$E0
.byte $6C,$E0,$02,$BB,$04,$28,$A9,$FD,$5E,$D7,$2E,$93,$1B,$78,$08,$00
.byte $83,$CB,$FD,$0A,$BB,$21,$93,$95,$69,$17,$20,$96,$C3,$B4,$B6,$51
.byte $C1,$4E,$C3,$05,$72,$D0,$25,$98,$44,$F0,$99,$B7,$B4,$0B,$F3,$0F
.byte $54,$0A,$6C,$24,$45,$10,$2B,$9D,$86,$3C,$DF,$27,$02,$9E,$EA,$5B
.byte $B7,$B6,$4F,$60,$70,$E0,$E1,$AA,$C2,$F3,$7F,$6A,$63,$CA,$62,$21
.byte $80,$76,$41,$65,$AA,$3B,$D4,$2C,$ED,$B5,$15,$EA,$74,$66,$66,$3E
.byte $AD,$FF,$A0,$43,$7B,$4C,$06,$A4,$15,$32,$EE,$44,$43,$A6,$68,$3B
.byte $6F,$5D,$BE,$D4,$DA,$75,$1B,$EF,$9B,$4D,$99,$8F,$49,$E8,$A9,$1D
.byte $F5,$1B,$58,$3A,$92,$25,$2D,$51,$38,$5C,$62,$05,$DD,$A9,$63,$AD
.byte $E3,$78,$2F,$37,$90,$15,$DB,$62,$58,$E2,$E8,$35,$BB,$C1,$5A,$EA
.byte $06,$FE,$28,$AA,$4F,$5D,$64,$BF,$83,$CF,$7F,$B2,$F9,$A9,$90,$BF
.byte $DD,$06,$B6,$64,$25,$8A,$E0,$24,$FA,$40,$95,$13,$91,$61,$93,$0D
.byte $69,$A8,$0E,$0B,$AE,$FD,$DF,$1A,$D4,$98,$D8,$11,$61,$E9,$16,$66
.byte $BD,$82,$1F,$2C,$E2,$74,$26,$77,$13,$E4,$6A,$25,$D7,$DE,$8A,$4F
.byte $1F,$7B,$47,$BC,$DA,$DB,$31,$E7,$2B,$06,$2C,$39,$15,$FC,$1C,$0B
.byte $1A,$3B,$A0,$0F,$55,$E5,$D8,$1C,$6D,$6C,$7F,$B8,$14,$AD,$9C,$AF
.byte $92,$B6,$60,$40,$76,$E6,$6D,$2F,$9E,$CA,$45,$6D,$54,$97,$47,$35
.byte $EE,$39,$50,$63,$47,$8C,$8A,$AB,$18,$F7,$6D,$10,$B7,$A6,$74,$0C
.byte $11,$24,$9C,$F5,$64,$5D,$FB,$16,$65,$1C,$59,$C6,$B9,$E3,$30,$52
.byte $1D,$E4,$B8,$9E,$A3,$2F,$7B,$6F,$03,$20,$24,$41,$4C,$F7,$22,$B8
.byte $92,$A7,$75,$E3,$1D,$F2,$5E,$FD,$B7,$A4,$F3,$34,$BF,$F7,$37,$CA
.byte $67,$22,$D4,$4D,$DE,$1A,$99,$58,$B2,$65,$91,$12,$F2,$8C,$65,$08
.byte $69,$E2,$9B,$D3,$94,$8C,$71,$F1,$D8,$22,$29,$53,$E8,$6A,$D9,$55
.byte $3E,$24,$42,$EF,$38,$12,$AC,$02,$35,$84,$7D,$2C,$C2,$34,$AC,$E2
.byte $4B,$AA,$E0,$31,$8F,$A0,$F2,$13,$A8,$4F,$7B,$98,$02,$16,$3B,$D4
.byte $8D,$09,$58,$A4,$FF,$46,$CA,$17,$08,$AA,$78,$02,$4A,$CF,$72,$E1
.byte $A8,$55,$52,$89,$F8,$FD,$D6,$4E,$22,$E7,$8F,$C6,$80,$F1,$BB,$3C
.byte $09,$1B,$4A,$4A,$06,$A1,$FD,$54,$E4,$BF,$D8,$27,$14,$23,$42,$90
.byte $B3,$7B,$55,$14,$77,$22,$EE,$92,$E9,$37,$76,$8C,$7D,$CF,$B7,$C7
.byte $D2,$90,$17,$48,$BB,$52,$BC,$19,$AA,$91,$9F,$DC,$0D,$AA,$C9,$24
.byte $C8,$45,$DF,$AB,$B3,$83,$A8,$9E,$0F,$AA,$62,$2F,$C4,$C0,$28,$BA
.byte $32,$56,$99,$69,$C9,$77,$4B,$62,$6B,$FF,$B6,$DD,$42,$46,$7A,$00
.byte $DA,$E9,$67,$4D,$46,$9C,$B5,$92,$04,$B5,$F6,$03,$01,$3C,$A2,$47
.byte $40,$15,$4A,$D6,$04,$39,$BC,$2F,$E9,$E1,$39,$59,$9B,$6A,$A4,$12
.byte $97,$23,$99,$30,$9E,$A6,$70,$AD,$C7,$1B,$D6,$1F,$05,$15,$D2,$5B
.byte $29,$0F,$5A,$CC,$0A,$99,$A2,$68,$5D,$58,$ED,$9C,$B9,$82,$CD,$74
|
aappleby/metroboy
| 1,128
|
tests/cpu_instrs/source/01-special.s
|
; Tests instructions that don't fit template
.include "shell.inc"
main:
set_test 2,"JR negative"
ld a,0
jp jr_neg
inc a
- inc a
inc a
cp 2
jp nz,test_failed
jp +
jr_neg:
jr -
+
set_test 3,"JR positive"
ld a,0
jr +
inc a
+ inc a
inc a
cp 2
jp nz,test_failed
set_test 4,"LD PC,HL"
ld hl,+
ld a,0
ld pc,hl
inc a
+ inc a
inc a
cp 2
jp nz,test_failed
set_test 5,"POP AF"
ld bc,$1200
- push bc
pop af
push af
pop de
ld a,c
and $F0
cp e
jp nz,test_failed
inc b
inc c
jr nz,-
set_test 6,"DAA"
; Test all combinations of A and flags (256*16 total)
ld de,0
- push de
pop af
daa
push af
call update_crc
pop hl
ld a,l
call update_crc
inc d
jr nz,-
ld a,e
add $10
ld e,a
jr nz,-
check_crc $6A9F8D8A
jp tests_passed
|
aappleby/metroboy
| 4,409
|
tests/cpu_instrs/source/11-op a,(hl).s
|
; Tests (HL/BC/DE) instructions.
; Takes 20 seconds.
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $0A,0,0 ; LD A,(BC)
.byte $1A,0,0 ; LD A,(DE)
.byte $02,0,0 ; LD (BC),A
.byte $12,0,0 ; LD (DE),A
.byte $2A,0,0 ; LD A,(HL+)
.byte $3A,0,0 ; LD A,(HL-)
.byte $22,0,0 ; LD (HL+),A
.byte $32,0,0 ; LD (HL-),A
.byte $B6,0,0 ; OR (HL)
.byte $BE,0,0 ; CP (HL)
.byte $86,0,0 ; ADD (HL)
.byte $8E,0,0 ; ADC (HL)
.byte $96,0,0 ; SUB (HL)
.byte $9E,0,0 ; SBC (HL)
.byte $A6,0,0 ; AND (HL)
.byte $AE,0,0 ; XOR (HL)
.byte $35,0,0 ; DEC (HL)
.byte $34,0,0 ; INC (HL)
.byte $CB,$06,0 ; RLC (HL)
.byte $CB,$0E,0 ; RRC (HL)
.byte $CB,$16,0 ; RL (HL)
.byte $CB,$1E,0 ; RR (HL)
.byte $CB,$26,0 ; SLA (HL)
.byte $CB,$2E,0 ; SRA (HL)
.byte $CB,$36,0 ; SWAP (HL)
.byte $CB,$3E,0 ; SRL (HL)
.byte $CB,$46,0 ; BIT 0,(HL)
.byte $CB,$4E,0 ; BIT 1,(HL)
.byte $CB,$56,0 ; BIT 2,(HL)
.byte $CB,$5E,0 ; BIT 3,(HL)
.byte $CB,$66,0 ; BIT 4,(HL)
.byte $CB,$6E,0 ; BIT 5,(HL)
.byte $CB,$76,0 ; BIT 6,(HL)
.byte $CB,$7E,0 ; BIT 7,(HL)
.byte $CB,$86,0 ; RES 0,(HL)
.byte $CB,$8E,0 ; RES 1,(HL)
.byte $CB,$96,0 ; RES 2,(HL)
.byte $CB,$9E,0 ; RES 3,(HL)
.byte $CB,$A6,0 ; RES 4,(HL)
.byte $CB,$AE,0 ; RES 5,(HL)
.byte $CB,$B6,0 ; RES 6,(HL)
.byte $CB,$BE,0 ; RES 7,(HL)
.byte $CB,$C6,0 ; SET 0,(HL)
.byte $CB,$CE,0 ; SET 1,(HL)
.byte $CB,$D6,0 ; SET 2,(HL)
.byte $CB,$DE,0 ; SET 3,(HL)
.byte $CB,$E6,0 ; SET 4,(HL)
.byte $CB,$EE,0 ; SET 5,(HL)
.byte $CB,$F6,0 ; SET 6,(HL)
.byte $CB,$FE,0 ; SET 7,(HL)
.byte $27,0,0 ; DAA
instrs_end:
test_instr:
ld c,$00
call test
ld c,$10
call test
ld c,$E0
call test
ld c,$F0
call test
ret
test:
; Go through each value for A
ld hl,values
a_loop:
ld b,(hl)
push hl
; Go through each value for (HL)
ld hl,values
values_loop:
push bc
push hl
push bc
; BC
ld a,(hl+)
ld bc,rp_temp
ld (rp_temp),a
; DE
ld a,(hl+)
ld de,rp_temp+1
ld (rp_temp+1),a
; HL
ld a,(hl)
ld hl,rp_temp+2
ld (rp_temp+2),a
; AF
pop af
; call print_regs
jp instr
instr_done:
; Checksum AF, HL, and (HL)
push hl
push af
call update_crc_fast
pop hl
ld a,l
call update_crc_fast
pop bc
ld a,b
call update_crc_fast
ld a,c
call update_crc_fast
ld a,(rp_temp)
call update_crc_fast
ld a,(rp_temp+1)
call update_crc_fast
ld a,(rp_temp+2)
call update_crc_fast
pop hl
pop bc
inc hl
ld a,l
cp <values_end
jr nz,values_loop
pop hl
inc hl
ld a,l
cp <values_end
jr nz,a_loop
ret
values:
.byte $00,$01,$0F,$10,$1F,$7F,$80,$F0,$FF,$02,$04,$08,$20,$40
values_end:
.byte $00,$01,$0F,$10,$1F,$7F,$80,$F0,$FF,$02,$04,$08,$20,$40
checksums:
.byte $E0,$E5,$09,$A7,$FB,$28,$0D,$AE,$AC,$BB,$91,$D8,$B3,$E2,$AF,$C4
.byte $3D,$B5,$02,$07,$4F,$6E,$5B,$7E,$AE,$02,$E7,$14,$DC,$D9,$BE,$6D
.byte $F1,$48,$A9,$42,$67,$08,$FE,$57,$06,$6A,$A9,$B1,$FD,$A5,$84,$F0
.byte $82,$FC,$24,$A9,$A8,$1D,$BB,$E2,$F8,$23,$8C,$DE,$0E,$1D,$64,$D1
.byte $05,$E0,$24,$41,$53,$75,$47,$55,$F4,$D9,$10,$6A,$38,$16,$28,$D8
.byte $D1,$28,$A3,$E0,$A2,$05,$B8,$FE,$B0,$F4,$F5,$8F,$4B,$39,$03,$B0
.byte $8A,$07,$BA,$90,$25,$99,$A7,$78,$E6,$9A,$D1,$49,$C9,$B2,$A3,$E5
.byte $36,$34,$CB,$5A,$97,$42,$71,$09,$39,$87,$25,$EC,$54,$EE,$C5,$B3
.byte $FC,$B5,$6F,$BD,$0B,$D8,$46,$6F,$6A,$27,$81,$9F,$F8,$38,$E2,$71
.byte $55,$19,$21,$83,$4B,$85,$9F,$4B,$A1,$78,$14,$60,$58,$08,$D9,$57
.byte $11,$8C,$83,$9A,$9F,$01,$D1,$90,$E8,$82,$0B,$5A,$BD,$75,$86,$21
.byte $DF,$83,$E9,$23,$1E,$B6,$7F,$D1,$4A,$18,$A5,$8E,$CF,$CF,$CA,$51
.byte $3F,$03,$A4,$96,$C3,$1F,$9E,$88,$0C,$DF,$1F,$B1
|
aappleby/metroboy
| 1,880
|
tests/cpu_instrs/source/04-op r,imm.s
|
; Tests immediate instructions
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $36,0,0 ; LD (HL),$00
.byte $06,0,0 ; LD B,$00
.byte $0E,0,0 ; LD C,$00
.byte $16,0,0 ; LD D,$00
.byte $1E,0,0 ; LD E,$00
.byte $26,0,0 ; LD H,$00
.byte $2E,0,0 ; LD L,$00
.byte $3E,0,0 ; LD A,$00
.byte $F6,0,0 ; OR $00
.byte $FE,0,0 ; CP $00
.byte $C6,0,0 ; ADD $00
.byte $CE,0,0 ; ADC $00
.byte $D6,0,0 ; SUB $00
.byte $DE,0,0 ; SBC $00
.byte $E6,0,0 ; AND $00
.byte $EE,0,0 ; XOR $00
instrs_end:
test_instr:
ld c,$00
call test
ld c,$10
call test
ld c,$E0
call test
ld c,$F0
call test
ret
test:
; Go through each value for A
ld hl,values
a_loop:
ld b,(hl)
push hl
; Go through each value for immediate data
ld hl,values
values_loop:
push bc
push hl
; Set registers
push bc
ld a,(hl)
ld (instr+1),a
ld bc,$1234
ld de,$5678
ld hl,rp_temp
pop af
; call print_regs
jp instr
instr_done:
; Checksum registers and (hl)
call checksum_af_bc_de_hl
ld a,(rp_temp)
call update_crc_fast
pop hl
pop bc
inc hl
ld a,l
cp <values_end
jr nz,values_loop
pop hl
inc hl
ld a,l
cp <values_end
jr nz,a_loop
ret
values:
.byte $00,$01,$0F,$10,$1F,$7F,$80,$F0,$FF
values_end:
checksums:
.byte $7F,$7F,$05,$B7,$85,$82,$94,$B6,$D8,$0A,$D6,$F5,$44,$8C,$37,$2A,$FB,$46,$05,$FA,$BD,$2F,$9E,$C1,$5A,$56,$2A,$DA,$D0,$EE,$14,$BA,$EA,$42,$36,$D2,$87,$28,$AB,$30,$4D,$A2,$63,$C6,$34,$4E,$55,$08,$9B,$1C,$97,$0E,$49,$F8,$73,$D4,$86,$C7,$DC,$C6,$03,$BF,$43,$21,
|
aappleby/metroboy
| 3,712
|
tests/cpu_instrs/source/06-ld r,r.s
|
; Tests LD r,r ($40-$7F)
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $40,0,0 ; LD B,B
.byte $41,0,0 ; LD B,C
.byte $42,0,0 ; LD B,D
.byte $43,0,0 ; LD B,E
.byte $44,0,0 ; LD B,H
.byte $45,0,0 ; LD B,L
.byte $46,0,0 ; LD B,(HL)
.byte $47,0,0 ; LD B,A
.byte $48,0,0 ; LD C,B
.byte $49,0,0 ; LD C,C
.byte $4A,0,0 ; LD C,D
.byte $4B,0,0 ; LD C,E
.byte $4C,0,0 ; LD C,H
.byte $4D,0,0 ; LD C,L
.byte $4E,0,0 ; LD C,(HL)
.byte $4F,0,0 ; LD C,A
.byte $50,0,0 ; LD D,B
.byte $51,0,0 ; LD D,C
.byte $52,0,0 ; LD D,D
.byte $53,0,0 ; LD D,E
.byte $54,0,0 ; LD D,H
.byte $55,0,0 ; LD D,L
.byte $56,0,0 ; LD D,(HL)
.byte $57,0,0 ; LD D,A
.byte $58,0,0 ; LD E,B
.byte $59,0,0 ; LD E,C
.byte $5A,0,0 ; LD E,D
.byte $5B,0,0 ; LD E,E
.byte $5C,0,0 ; LD E,H
.byte $5D,0,0 ; LD E,L
.byte $5E,0,0 ; LD E,(HL)
.byte $5F,0,0 ; LD E,A
.byte $60,0,0 ; LD H,B
.byte $61,0,0 ; LD H,C
.byte $62,0,0 ; LD H,D
.byte $63,0,0 ; LD H,E
.byte $64,0,0 ; LD H,H
.byte $65,0,0 ; LD H,L
.byte $66,0,0 ; LD H,(HL)
.byte $67,0,0 ; LD H,A
.byte $68,0,0 ; LD L,B
.byte $69,0,0 ; LD L,C
.byte $6A,0,0 ; LD L,D
.byte $6B,0,0 ; LD L,E
.byte $6C,0,0 ; LD L,H
.byte $6D,0,0 ; LD L,L
.byte $6E,0,0 ; LD L,(HL)
.byte $6F,0,0 ; LD L,A
.byte $70,0,0 ; LD (HL),B
.byte $71,0,0 ; LD (HL),C
.byte $72,0,0 ; LD (HL),D
.byte $73,0,0 ; LD (HL),E
.byte $74,0,0 ; LD (HL),H
.byte $75,0,0 ; LD (HL),L
.byte $77,0,0 ; LD (HL),A
.byte $78,0,0 ; LD A,B
.byte $79,0,0 ; LD A,C
.byte $7A,0,0 ; LD A,D
.byte $7B,0,0 ; LD A,E
.byte $7C,0,0 ; LD A,H
.byte $7D,0,0 ; LD A,L
.byte $7E,0,0 ; LD A,(HL)
.byte $7F,0,0 ; LD A,A
instrs_end:
test_instr:
ld c,$00
call test
ld c,$10
call test
ld c,$E0
call test
ld c,$F0
call test
ret
test:
; Put different value in each register and (hl_temp)
ld b,$BC
push bc
ld a,$DE
ld (rp_temp),a
ld a,$12
ld bc,$3456
ld de,$789A
ld hl,rp_temp ; (HL) points to RAM
pop af
; call print_regs
jp instr
instr_done:
; Checksum registers and (HL)
call checksum_af_bc_de_hl
ld a,(rp_temp)
call update_crc_fast
ret
checksums:
.byte $40,$3A,$AF,$06,$B6,$CB,$B2,$AB,$6F,$EF,$71,$9B,$75,$E3,$6C,$B9,$34,$FB,$26,$B7,$5A,$B9,$2F,$CE,$34,$FB,$26,$B7,$C2,$0A,$3B,$1A,$2A,$8A,$D6,$7C,$40,$3A,$AF,$06,$AF,$0A,$74,$70,$19,$A9,$6E,$6F,$11,$DA,$FE,$FE,$18,$10,$04,$2B,$11,$DA,$FE,$FE,$7B,$6A,$87,$84,$8B,$87,$34,$12,$00,$45,$DE,$01,$40,$3A,$AF,$06,$93,$E2,$8F,$C6,$DD,$7D,$90,$32,$FF,$90,$1B,$A8,$DD,$7D,$90,$32,$56,$BF,$7A,$21,$23,$C0,$FA,$06,$3B,$1D,$A0,$80,$3F,$44,$1B,$9C,$40,$3A,$AF,$06,$56,$25,$85,$CD,$D7,$B1,$DB,$F9,$56,$25,$85,$CD,$4E,$F8,$DF,$4B,$F0,$C3,$F9,$18,$20,$0F,$F6,$91,$71,$69,$CE,$46,$F0,$A0,$03,$4D,$40,$3A,$AF,$06,$29,$47,$E2,$36,$40,$3A,$AF,$06,$90,$F6,$A0,$8F,$3D,$62,$26,$A9,$A4,$52,$C1,$75,$45,$ED,$75,$40,$8A,$4D,$63,$56,$AF,$BA,$2D,$FE,$40,$3A,$AF,$06,$AF,$BA,$2D,$FE,$36,$8A,$CA,$22,$34,$8D,$C2,$65,$1A,$DB,$FF,$54,$32,$C0,$E8,$55,$ED,$4A,$87,$2F,$40,$3A,$AF,$06,$9D,$BC,$81,$E6,$6E,$6C,$92,$37,$B1,$EC,$C3,$29,$1D,$C5,$9F,$A1,$59,$6F,$66,$CD,$B4,$FB,$FD,$74,$EC,$13,$F3,$8E,$70,$0C,$5F,$ED,$EC,$13,$F3,$8E,$40,$3A,$AF,$06,
|
aappleby/metroboy
| 1,981
|
tests/cpu_instrs/source/03-op sp,hl.s
|
; Tests SP/HL instructions
;.define PRINT_CHECKSUMS 1
.include "shell.inc"
.include "instr_test.s"
instrs:
.byte $33,0,0 ; INC SP
.byte $3B,0,0 ; DEC SP
.byte $39,0,0 ; ADD HL,SP
.byte $F9,0,0 ; LD SP,HL
.byte $E8,$01,0 ; ADD SP,1
.byte $E8,$FF,0 ; ADD SP,-1
.byte $F8,$01,0 ; LD HL,SP+1
.byte $F8,$FF,0 ; LD HL,SP-1
instrs_end:
test_instr:
; C = flags register
ld c,$00
call test
ld c,$F0
call test
ret
test:
; Go through each value for HL
ld hl,values
hl_loop:
ld e,(hl)
inc hl
ld d,(hl)
inc hl
push hl
; Go through each value for SP
ld hl,values
values_loop:
push bc
push de
push hl
push bc
pop af
; Switch stack
ld (temp),sp
ld a,(hl+)
ld h,(hl)
ld l,a
; call print_regs
ld sp,hl
; Set registers
ld h,d
ld l,e
ld a,$12
ld bc,$5691
ld de,$9ABC
jp instr
instr_done:
; Save new SP and switch to yet another stack
ld (temp+2),sp
ld sp,$DF70
call checksum_af_bc_de_hl
; Checksum SP
ld a,(temp+2)
call update_crc_fast
ld a,(temp+3)
call update_crc_fast
ldsp temp
pop hl
pop de
pop bc
inc hl
inc hl
ld a,l
cp <values_end
jr nz,values_loop
pop hl
ld a,l
cp <values_end
jr nz,hl_loop
ret
values:
.word $0000,$0001,$000F,$0010,$001F,$007F,$0080,$00FF
.word $0100,$0F00,$1F00,$1000,$7FFF,$8000,$FFFF
values_end:
.word $0000,$0001,$000F,$0010,$001F,$007F,$0080,$00FF
.word $0100,$0F00,$1F00,$1000,$7FFF,$8000,$FFFF
checksums:
.byte $BC,$F4,$CD,$8C,$C7,$5E,$89,$E5,$36,$65,$21,$55,$D6,$6A,$2A,$FF
.byte $EB,$34,$37,$B9,$08,$5F,$22,$13,$B6,$2A,$37,$C3,$72,$43,$5C,$4D
|
aappleby/metroboy
| 2,575
|
tests/cpu_instrs/source/common/numbers.s
|
; Printing of numeric values
; Prints value of indicated register/pair
; as 2/4 hex digits, followed by a space.
; Updates checksum with printed values.
; Preserved: AF, BC, DE, HL
print_regs:
call print_af
call print_bc
call print_de
call print_hl
call print_newline
ret
print_a:
push af
print_a_:
call print_hex
ld a,' '
call print_char_nocrc
pop af
ret
print_af:
push af
call print_hex
pop af
print_f:
push bc
push af
pop bc
call print_c
pop bc
ret
print_b:
push af
ld a,b
jr print_a_
print_c:
push af
ld a,c
jr print_a_
print_d:
push af
ld a,d
jr print_a_
print_e:
push af
ld a,e
jr print_a_
print_h:
push af
ld a,h
jr print_a_
print_l:
push af
ld a,l
jr print_a_
print_bc:
push af
push bc
print_bc_:
ld a,b
call print_hex
ld a,c
pop bc
jr print_a_
print_de:
push af
push bc
ld b,d
ld c,e
jr print_bc_
print_hl:
push af
push bc
ld b,h
ld c,l
jr print_bc_
; Prints A as two hex chars and updates checksum
; Preserved: BC, DE, HL
print_hex:
call update_crc
print_hex_nocrc:
push af
swap a
call +
pop af
+ and $0F
cp 10
jr c,+
add 7
+ add '0'
jp print_char_nocrc
; Prints char_nz if Z flag is clear,
; char_z if Z flag is set.
; Preserved: AF, BC, DE, HL
.macro print_nz ARGS char_nz, char_z
push af
ld a,char_nz
jr nz,print_nz\@
ld a,char_z
print_nz\@:
call print_char
pop af
.endm
; Prints char_nc if C flag is clear,
; char_c if C flag is set.
; Preserved: AF, BC, DE, HL
.macro print_nc ARGS char_nc, char_c
push af
ld a,char_nc
jr nz,print_nc\@
ld a,char_c
print_nc\@:
call print_char
pop af
.endm
; Prints A as 2 decimal digits
; Preserved: AF, BC, DE, HL
print_dec2:
push af
push bc
jr +
; Prints A as 1-3 digit decimal value
; Preserved: AF, BC, DE, HL
print_dec:
push af
push bc
cp 10
jr c,++
ld c,100
cp c
call nc,@digit
+ ld c,10
call @digit
++ add '0'
call print_char
pop bc
pop af
ret
@digit:
ld b,'0'-1
- inc b
sub c
jr nc,-
add c
ld c,a
ld a,b
call print_char
ld a,c
ret
|
aappleby/metroboy
| 1,224
|
tests/cpu_instrs/source/common/crc.s
|
; CRC-32 checksum calculation
.define checksum dp+0 ; little-endian, complemented
.redefine dp dp+4
; Initializes checksum module. Might initialize tables
; in the future.
init_crc:
jr reset_crc
; Clears CRC
; Preserved: BC, DE, HL
reset_crc:
ld a,$FF
sta checksum+0
sta checksum+1
sta checksum+2
sta checksum+3
ret
; Updates current checksum with byte A
; Preserved: AF, BC, DE, HL
; Time: 237 cycles average
update_crc:
; 65 cycles + 8*cycles per bit
; min cycles per bit: 14
; max cycles per bit: 29
push af
push bc
push de
push hl
ld hl,checksum+3
ld b,(hl)
dec l
ld c,(hl)
dec l
ld d,(hl)
dec l
xor (hl)
ld h,8
- srl b
rr c
rr d
rra
jr nc,+
ld e,a
ld a,b
xor $ED
ld b,a
ld a,c
xor $B8
ld c,a
ld a,d
xor $83
ld d,a
ld a,e
xor $20
+ dec h
jr nz,-
ld h,>checksum
ldi (hl),a
ld (hl),d
inc l
ld (hl),c
inc l
ld (hl),b
pop hl
pop de
pop bc
pop af
ret
|
aappleby/metroboy
| 1,751
|
tests/cpu_instrs/source/common/checksums.s
|
; Multiple checksum table handling
.define next_checksum bss+0
.redefine bss bss+2
; If PRINT_CHECKSUMS is defined, checksums are printed
; rather than compared.
; Initializes multiple checksum handler to use checksums
; table (defined by user).
; Preserved: BC, DE, HL
checksums_init:
ld a,<checksums
ld (next_checksum),a
ld a,>checksums
ld (next_checksum+1),a
ret
; Compares current checksum with next checksum in
; list. Z if they match, NZ if not.
; Preserved: BC, DE, HL
checksums_compare:
.ifdef PRINT_CHECKSUMS
lda checksum+3
push af
lda checksum+2
push af
lda checksum+1
push af
lda checksum+0
push af
ld a,(next_checksum)
inc a
ld (next_checksum),a
sub <checksums+1
and $03
ld a,','
jr nz,+
print_str newline,'.',"byte"
ld a,' '
+ call print_char
pop af
call @print_byte
pop af
call @print_byte
pop af
call @print_byte
ld a,'$'
call print_char
pop af
call print_hex
xor a
ret
@print_byte:
push af
ld a,'$'
call print_char
pop af
call print_hex
ld a,','
call print_char
ret
.else
push bc
push de
push hl
ld a,(next_checksum)
ld l,a
ld a,(next_checksum+1)
ld h,a
ld de,checksum
ld b,0
- ld a,(de)
xor (hl)
or b
ld b,a
inc hl
inc e
ld a,e
cp <(checksum+4)
jr nz,-
ld a,l
ld (next_checksum),a
ld a,h
ld (next_checksum+1),a
ld a,b
cp 0
pop hl
pop de
pop bc
ret
.endif
|
aappleby/metroboy
| 1,035
|
tests/cpu_instrs/source/common/cpu_speed.s
|
; CPU speed manipulation.
; Switches to normal speed. No effect on DMG.
; Preserved: BC, DE, HL
cpu_norm:
; Do nothing if not CGB
ld a,(gb_id)
and gb_id_cgb
ret z
lda KEY1
rlca
ret nc
jr cpu_speed_toggle
; Switches to double speed. No effect on DMG.
; Preserved: BC, DE, HL
cpu_fast:
; Do nothing if not CGB
ld a,(gb_id)
and gb_id_cgb
ret z
lda KEY1
rlca
ret c
cpu_speed_toggle:
di
lda IE
push af
xor a
sta IE
sta IF
wreg P1,$30
wreg KEY1,1
stop
nop
pop af
sta IE
ret
; Determines current CPU speed without using KEY1.
; A=1 if fast, 0 if normal. Always 0 on DMG.
; Preserved: BC, DE,HL
get_cpu_speed:
push bc
call sync_apu
wreg NR14,$C0
wreg NR11,-1
wreg NR12,8
wreg NR14,$C0
ld bc,-$262
- inc bc
lda NR52
and 1
jr nz,-
ld a,0
bit 7,b
jr nz,+
inc a
+ pop bc
ret
|
aappleby/metroboy
| 1,579
|
tests/cpu_instrs/source/common/crc_fast.s
|
; Fast table-based CRC-32
.define crc_tables (bss+$FF)&$FF00 ; 256-byte aligned
.redefine bss crc_tables+$400
; Initializes fast CRC tables and resets checksum.
; Time: 47 msec
init_crc_fast:
ld l,0
@next:
xor a
ld c,a
ld d,a
ld e,l
ld h,8
- rra
rr c
rr d
rr e
jr nc,+
xor $ED
ld b,a
ld a,c
xor $B8
ld c,a
ld a,d
xor $83
ld d,a
ld a,e
xor $20
ld e,a
ld a,b
+ dec h
jr nz,-
ld h,>crc_tables
ld (hl),e
inc h
ld (hl),d
inc h
ld (hl),c
inc h
ld (hl),a
inc l
jr nz,@next
jp init_crc
; Faster version of update_crc
; Preserved: BC, DE
; Time: 50 cycles (including CALL)
update_crc_fast:
; Fastest inline macro version of update_crc_fast
; Time: 40 cycles
; Size: 28 bytes
.macro update_crc_fast
ld l,a ; 1
lda checksum ; 3
xor l ; 1
ld l,a ; 1
ld h,>crc_tables ; 2
lda checksum+1 ; 3
xor (hl) ; 2
inc h ; 1
sta checksum ; 3
lda checksum+2 ; 3
xor (hl) ; 2
inc h ; 1
sta checksum+1 ; 3
lda checksum+3 ; 3
xor (hl) ; 2
inc h ; 1
sta checksum+2 ; 3
ld a,(hl) ; 2
sta checksum+3 ; 3
.endm
update_crc_fast
ret
|
aappleby/metroboy
| 3,011
|
tests/cpu_instrs/source/common/testing.s
|
; Diagnostic and testing utilities
.define result bss+0
.define test_name bss+1
.redefine bss bss+3
; Sets test code and optional error text
; Preserved: AF, BC, DE, HL
.macro set_test ; code[,text[,text2]]
push hl
call set_test_
jr @set_test\@
.byte \1
.if NARGS > 1
.byte \2
.endif
.if NARGS > 2
.byte \3
.endif
.byte 0
@set_test\@:
pop hl
.endm
set_test_:
pop hl
push hl
push af
inc hl
inc hl
ldi a,(hl)
ld (result),a
ld a,l
ld (test_name),a
ld a,h
ld (test_name+1),a
pop af
ret
; Initializes testing module
init_testing:
set_test $FF
call init_crc
ret
; Reports "Passed", then exits with code 0
tests_passed:
call print_newline
print_str "Passed"
ld a,0
jp exit
; Reports "Done" if set_test has never been used,
; "Passed" if set_test 0 was last used, or
; failure if set_test n was last used.
tests_done:
ld a,(result)
inc a
jr z,+
dec a
jr z,tests_passed
jr test_failed
+ print_str "Done"
ld a,0
jp exit
; Reports current error text and exits with result code
test_failed:
ld a,(test_name)
ld l,a
ld a,(test_name+1)
ld h,a
ld a,(hl)
or a
jr z,+
call print_newline
call print_str_hl
call print_newline
+
ld a,(result)
cp 1 ; if a = 0 then a = 1
adc 0
jp exit
; Prints checksum as 8-character hex value
; Preserved: AF, BC, DE, HL
print_crc:
push af
; Must read checksum entirely before printing,
; since printing updates it.
lda checksum
cpl
push af
lda checksum+1
cpl
push af
lda checksum+2
cpl
push af
lda checksum+3
cpl
call print_hex
pop af
call print_hex
pop af
call print_hex
pop af
call print_a
pop af
ret
; If checksum doesn't match expected, reports failed test.
; Passing 0 just prints checksum. Clears checksum afterwards.
.macro check_crc ARGS crc
.if crc == 0
call show_printing
call print_newline
call print_crc
.else
ld bc,(crc >> 16) ~ $FFFF
ld de,(crc & $FFFF) ~ $FFFF
call check_crc_
.endif
.endm
check_crc_:
lda checksum+0
cp e
jr nz,+
lda checksum+1
cp d
jr nz,+
lda checksum+2
cp c
jr nz,+
lda checksum+3
cp b
jr nz,+
jp reset_crc
+ call print_crc
jp test_failed
; Updates checksum with bytes from addr to addr+size-1
.macro checksum_mem ARGS addr,size
ld hl,addr
ld bc,size
call checksum_mem_
.endm
checksum_mem_:
- ldi a,(hl)
call update_crc
dec bc
ld a,b
or c
jr nz,-
ret
|
aappleby/metroboy
| 4,343
|
tests/cpu_instrs/source/common/apu.s
|
; Sound chip utilities
; Turns APU off
; Preserved: BC, DE, HL
sound_off:
wreg NR52,0
ret
; Turns APU on
; Preserved: BC, DE, HL
sound_on:
wreg NR52,$80 ; power
wreg NR51,$FF ; mono
wreg NR50,$77 ; volume
ret
; Synchronizes to APU length counter within
; tens of clocks. Uses square 2 channel.
; Preserved: BC, DE, HL
sync_apu:
wreg NR24,$00 ; disable length
wreg NR21,$3E ; length = 2 (in case of extra len clk)
wreg NR22,$08 ; silent without disabling channel
wreg NR24,$C0 ; start length
- lda NR52 ; wait for length to reach zero
and $02
jr nz,-
ret
; Synchronizes to first square sweep within
; tens of clocks. Uses square 1 channel.
; Preserved: BC, DE, HL
sync_sweep:
wreg NR10,$11 ; sweep period = 1, shift = 1
wreg NR12,$08 ; silent without disabling channel
wreg NR13,$FF ; freq = $3FF
wreg NR14,$83 ; start
- lda NR52
and $01
jr nz,-
ret
; Copies 16-byte wave from (HL) to wave RAM
; Preserved: BC, DE
load_wave:
push bc
wreg NR30,$00 ; disable while writing
ld c,$30
- ld a,(hl+)
ld ($FF00+c),a
inc c
bit 6,c
jr z,-
pop bc
ret
; Makes short beep
; Preserved: BC, DE, HL
beep:
xor a ; sound off
sta NR52
dec a
sta NR52 ; sound on
sta NR51 ; mono
sta NR50 ; volume
wreg NR12,$F1 ; volume, envelope rate
wreg NR14,$86 ; note on, pitch
delay_msec 250
ret
; Marks sound with bits of A encoded into volume
; Preserved: BC, DE, HL
mark_sound:
push bc
ld c,a
ld b,8
wreg NR10,0
wreg NR11,$80
wreg NR13,$F8
- ld a,$60
rl c
jr nc,+
ld a,$A0
+ sta NR12
wreg NR14,$87
delay_usec 300
wreg NR12,0
delay_usec 100
dec b
jr nz,-
pop bc
ret
; Fills wave RAM with A
; Preserved: BC, DE, HL
fill_wave:
push bc
ld c,$30
- ld ($FF00+c),a
inc c
bit 6,c
jr z,-
pop bc
ret
; Gets current length counter value for
; channel with mask A into A. Length counter
; must be enabled for that channel.
; Preserved: BC, DE, HL
get_len_a:
push bc
ld c,a
ld b,0
- lda NR52 ; 3
and c ; 1
jr z,+ ; 2
delay 4096-10
inc b ; 1
jr nz,- ; 3
+ ld a,b
pop bc
ret
; Synchronizes exactly to length clock. Next length clock
; occurs by 4079 clocks after this returns. Uses NR2x.
; Preserved: AF, BC, DE, HL
sync_length:
push af
push hl
ld hl,NR52
wreg NR22,$08 ; silent without disabling channel
wreg NR24,$40 ; avoids extra length clock on trigger
wreg NR21,-2 ; length = 2, in case clock occurs immediately
wreg NR24,$C0 ; start length
; Coarse sync
ld a,$02
- and (hl)
jr nz,-
; Fine sync. Slowly moves "forward" until
; length clock occurs just before reading NR52.
- delay 4097-20
wreg NR21,-1 ; 5
wreg NR24,$C0 ; 5
lda NR52 ; 3
delay 2 ; 2
and $02 ; 2
jr nz,- ; 3
pop hl
pop af
ret
; Delays n*4096 cycles
; Preserved: BC, DE, HL
.macro delay_frames ; n
ld a,\1
call delay_frames_
.endm
; Delays A*4096+13 cycles (including CALL)
; Preserved: BC, DE, HL
delay_a_frames:
or a ; 1
jr nz,+ ; 3
; -1
ret
delay_frames_: ; delays 4096*A-2 cycles (including CALL)
push af ; 4
ld a,256-13-20-12 ; 2
jr ++ ; 3
+
- push af ; 4
ld a,256-13-20 ; 2
++ call delay_a_20_cycles
delay 4096-256
pop af ; 3
dec a ; 1
jr nz,- ; 3
; -1
ret
.macro test_chan_timing ; chan, iter
ld a,\1
call print_dec
call print_space
ld a,\2
- push af
test_chan 1<<\1, \1*5+NR10
pop af
dec a
jr nz,-
call print_newline
.endm
.macro test_chans ARGS iter
test_chan_timing 0,iter
test_chan_timing 1,iter
test_chan_timing 2,iter
test_chan_timing 3,iter
.endm
|
aappleby/metroboy
| 5,377
|
tests/cpu_instrs/source/common/console.s
|
; Scrolling text console
; Console is 20x18 characters. Buffers lines, so
; output doesn't appear until a newline or flush.
; If scrolling isn't supported (i.e. SCY is treated
; as if always zero), the first 18 lines will
; still print properly). Also works properly if
; LY isn't supported (always reads back as the same
; value).
.define console_width 20
.define console_buf bss+0
.define console_pos bss+console_width
.define console_mode bss+console_width+1
.define console_scroll bss+console_width+2
.redefine bss bss+console_width+3
; Waits for start of LCD blanking period
; Preserved: BC, DE, HL
console_wait_vbl:
push bc
; Wait for start of vblank, with
; timeout in case LY doesn't work
; or LCD is disabled.
ld bc,-1250
- inc bc
ld a,b
or c
jr z,@timeout
lda LY
cp 144
jr nz,-
@timeout:
pop bc
ret
; Initializes text console
console_init:
call console_hide
; CGB-specific inits
ld a,(gb_id)
and gb_id_cgb
call nz,@init_cgb
; Clear nametable
ld a,' '
call @fill_nametable
; Load tiles
ld hl,TILES+$200
ld c,0
call @load_tiles
ld hl,TILES+$A00
ld c,$FF
call @load_tiles
; Init state
ld a,console_width
ld (console_pos),a
ld a,0
ld (console_mode),a
ld a,-8
ld (console_scroll),a
call console_scroll_up_
jr console_show
@fill_nametable:
ld hl,BGMAP0
ld b,4
- ld (hl),a
inc l
jr nz,-
inc h
dec b
jr nz,-
ret
@init_cgb:
; Clear palette
wreg $FF68,$80
ld b,16
- wreg $FF69,$FF
wreg $FF69,$7F
wreg $FF69,$00
wreg $FF69,$00
wreg $FF69,$00
wreg $FF69,$00
wreg $FF69,$00
wreg $FF69,$00
dec b
jr nz,-
; Clear attributes
ld a,1
ld (VBK),a
ld a,0
call @fill_nametable
ld a,0
ld (VBK),a
ret
@load_tiles:
ld de,ASCII
ld b,96
-- push bc
ld b,8
- ld a,(de)
inc de
xor c
ldi (hl),a
ldi (hl),a
dec b
jr nz,-
pop bc
dec b
jr nz,--
ret
; Shows console display
; Preserved: AF, BC, DE, HL
console_show:
push af
; Enable LCD
call console_wait_vbl
wreg LCDC,$91
wreg SCX,0
wreg BGP,$E4
jp console_apply_scroll_
; Hides console display by turning LCD off
; Preserved: AF, BC, DE, HL
console_hide:
push af
; LCD off
call console_wait_vbl
wreg LCDC,$11
pop af
ret
; Changes to normal text mode
; Preserved: BC, DE, HL
console_normal:
xor a
jr console_set_mode
; Changes to inverse text mode
; Preserved: BC, DE, HL
console_inverse:
ld a,$80
; Changes console mode to A.
; 0: Normal, $80: Inverse
; Preserved: BC, DE, HL
console_set_mode:
and $80
ld (console_mode),a
ret
; Prints char A to console. Will not appear until
; a newline or flush occurs.
; Preserved: AF, BC, DE, HL
console_print:
push af
cp 10
jr z,console_newline_
push hl
push af
ld hl,console_pos
ldi a,(hl)
cp <console_buf
jr nz,@not_at_end
; Newline if at end of current line. If this
; were done after writing to buffer, calling
; console_newline would print extra newline.
; Doing it before eliminates this.
; Ignore any spaces at end of line
pop af
cp ' '
jr z,@ignore_space
call console_newline
push af
@not_at_end:
pop af
or (hl) ; apply current attributes
dec l ; hl = console_pos
dec (hl) ; console_pos = console_pos - 1
ld l,(hl) ; hl = position in buffer
ld (hl),a
@ignore_space
pop hl
pop af
ret
; Displays current line and starts new one
; Preserved: AF, BC, DE, HL
console_newline:
push af
console_newline_:
call console_wait_vbl
call console_flush_
call console_scroll_up_
call console_flush_
jp console_apply_scroll_
console_scroll_up_:
push bc
push hl
; Scroll up 8 pixels
ld a,(console_scroll)
add 8
ld (console_scroll),a
; Start new clear line
ld a,' '
ld hl,console_buf + console_width - 1
ld b,console_width
- ldd (hl),a
dec b
jr nz,-
ld a,<(console_buf + console_width)
ld (console_pos),a
pop hl
pop bc
ret
; Displays current line's contents without scrolling.
; Preserved: A, BC, DE, HL
console_flush:
push af
call console_wait_vbl
call console_flush_
console_apply_scroll_:
ld a,(console_scroll)
sub 136
sta SCY
pop af
ret
console_flush_:
push de
push hl
; Address of row in nametable
ld a,(console_scroll)
ld l,a
ld h,(>BGMAP0) >> 2
add hl,hl
add hl,hl
; Copy line
ld de,console_buf + console_width
- dec e
ld a,(de)
ldi (hl),a
ld a,e
cp <console_buf
jr nz,-
pop hl
pop de
ret
ASCII:
.incbin "console.bin"
|
aappleby/metroboy
| 1,277
|
tests/cpu_instrs/source/common/build_rom.s
|
; Build as GB ROM
.memoryMap
defaultSlot 0
slot 0 $0000 size $4000
slot 1 $C000 size $4000
.endMe
.romBankSize $4000 ; generates $8000 byte ROM
.romBanks 2
.cartridgeType 1 ; MBC1
.computeChecksum
.computeComplementCheck
;;;; GB ROM header
; GB header read by bootrom
.org $100
nop
jp reset
; Nintendo logo required for proper boot
.byte $CE,$ED,$66,$66,$CC,$0D,$00,$0B
.byte $03,$73,$00,$83,$00,$0C,$00,$0D
.byte $00,$08,$11,$1F,$88,$89,$00,$0E
.byte $DC,$CC,$6E,$E6,$DD,$DD,$D9,$99
.byte $BB,$BB,$67,$63,$6E,$0E,$EC,$CC
.byte $DD,$DC,$99,$9F,$BB,$B9,$33,$3E
; Internal name
.ifdef ROM_NAME
.byte ROM_NAME
.endif
; CGB/DMG requirements
.org $143
.ifdef REQUIRE_CGB
.byte $C0
.else
.ifndef REQUIRE_DMG
.byte $80
.endif
.endif
.org $200
;;;; Shell
.include "runtime.s"
.include "console.s"
init_runtime:
call console_init
.ifdef TEST_NAME
print_str TEST_NAME,newline,newline
.endif
ret
std_print:
push af
sta SB
wreg SC,$81
delay 2304
pop af
jp console_print
post_exit:
call console_show
call play_byte
forever:
wreg NR52,0 ; sound off
- jr -
play_byte:
ret
.ends
|
aappleby/metroboy
| 1,941
|
tests/cpu_instrs/source/common/build_gbs.s
|
; Build as GBS music file
.memoryMap
defaultSlot 0
slot 0 $3000 size $1000
slot 1 $C000 size $1000
.endMe
.romBankSize $1000
.romBanks 2
;;;; GBS music file header
.byte "GBS"
.byte 1 ; vers
.byte 1 ; songs
.byte 1 ; first song
.word load_addr
.word reset
.word gbs_play
.word std_stack
.byte 0,0 ; timer
.ds $60,0
load_addr:
; WLA assumes we're building ROM and messes
; with bytes at the beginning, so skip them.
.ds $100,0
;;;; Shell
.include "runtime.s"
init_runtime:
ld a,$01 ; Identify as DMG hardware
ld (gb_id),a
.ifdef TEST_NAME
print_str TEST_NAME,newline,newline
.endif
ret
std_print:
sta SB
wreg SC,$81
delay 2304
ret
post_exit:
call play_byte
forever:
wreg NR52,0 ; sound off
- jp -
.ifndef CUSTOM_RESET
gbs_play:
.endif
console_flush:
console_normal:
console_inverse:
console_set_mode:
ret
; Reports A in binary as high and low tones, with
; leading low tone for reference. Omits leading
; zeroes.
; Preserved: AF, BC, DE, HL
play_byte:
push af
push hl
; HL = (A << 1) | 1
scf
rla
ld l,a
ld h,0
rl h
; Shift left until next-to-top bit is 1
- add hl,hl
bit 6,h
jr z,-
; Reset sound
delay_msec 400
wreg NR52,0 ; sound off
wreg NR52,$80 ; sound on
wreg NR51,$FF ; mono
wreg NR50,$77 ; volume
- add hl,hl
; Low or high pitch based on bit shifted out
; of HL
ld a,0
jr nc,+
ld a,$FF
+ sta NR23
; Play short tone
wreg NR21,$A0
wreg NR22,$F0
wreg NR24,$86
delay_msec 75
wreg NR22,0
wreg NR23,$F8
wreg NR24,$87
delay_msec 200
; Loop until HL = $8000
ld a,h
xor $80
or l
jr nz,-
pop hl
pop af
ret
.ends
|
aappleby/metroboy
| 1,783
|
tests/cpu_instrs/source/common/instr_test.s
|
; Framework for CPU instruction tests
; Calls test_instr with each instruction copied
; to instr, with a JP instr_done after it.
; Verifies checksum after testing instruction and
; prints opcode if it's wrong.
.include "checksums.s"
.include "cpu_speed.s"
.include "apu.s"
.include "crc_fast.s"
.define instr $DEF8
.define rp_temp (instr-4)
.define temp bss
; Sets SP to word at addr
; Preserved: BC, DE
.macro ldsp ; addr
ld a,(\1)
ld l,a
ld a,((\1)+1)
ld h,a
ld sp,hl
.endm
main:
call cpu_fast
call init_crc_fast
call checksums_init
set_test 0
ld hl,instrs
- ; Copy instruction
ld a,(hl+)
ld (instr),a
ld a,(hl+)
ld (instr+1),a
ld a,(hl+)
ld (instr+2),a
push hl
; Put JP instr_done after it
ld a,$C3
ld (instr+3),a
ld a,<instr_done
ld (instr+4),a
ld a,>instr_done
ld (instr+5),a
call reset_crc
call test_instr
call checksums_compare
jr z,passed
set_test 1
ld a,(instr)
call print_a
cp $CB
jr nz,+
ld a,(instr+1)
call print_a
+
passed:
; Next instruction
pop hl
ld a,l
cp <instrs_end
jr nz,-
ld a,h
cp >instrs_end
jr nz,-
jp tests_done
; Updates checksum with AF, BC, DE, and HL
checksum_af_bc_de_hl:
push hl
push af
update_crc_fast
pop hl
ld a,l
update_crc_fast
ld a,b
update_crc_fast
ld a,c
update_crc_fast
ld a,d
update_crc_fast
ld a,e
update_crc_fast
pop de
ld a,d
update_crc_fast
ld a,e
update_crc_fast
ret
|
aappleby/metroboy
| 1,777
|
tests/cpu_instrs/source/common/printing.s
|
; Main printing routine that checksums and
; prints to output device
; Character that does equivalent of print_newline
.define newline 10
; Prints char without updating checksum
; Preserved: BC, DE, HL
.define print_char_nocrc bss
.redefine bss bss+3
; Initializes printing. HL = print routine
init_printing:
ld a,l
ld (print_char_nocrc+1),a
ld a,h
ld (print_char_nocrc+2),a
jr show_printing
; Hides/shows further printing
; Preserved: BC, DE, HL
hide_printing:
ld a,$C9 ; RET
jr +
show_printing:
ld a,$C3 ; JP (nn)
+ ld (print_char_nocrc),a
ret
; Prints character and updates checksum UNLESS
; it's a newline.
; Preserved: AF, BC, DE, HL
print_char:
push af
cp newline
call nz,update_crc
call print_char_nocrc
pop af
ret
; Prints space. Does NOT update checksum.
; Preserved: AF, BC, DE, HL
print_space:
push af
ld a,' '
call print_char_nocrc
pop af
ret
; Advances to next line. Does NOT update checksum.
; Preserved: AF, BC, DE, HL
print_newline:
push af
ld a,newline
call print_char_nocrc
pop af
ret
; Prints immediate string
; Preserved: AF, BC, DE, HL
.macro print_str ; string,string2
push hl
call print_str_
.byte \1
.if NARGS > 1
.byte \2
.endif
.if NARGS > 2
.byte \3
.endif
.byte 0
pop hl
.endm
print_str_:
pop hl
call print_str_hl
jp hl
; Prints zero-terminated string pointed to by HL.
; On return, HL points to byte AFTER zero terminator.
; Preserved: AF, BC, DE
print_str_hl:
push af
jr +
- call print_char
+ ldi a,(hl)
or a
jr nz,-
pop af
ret
|
aappleby/metroboy
| 5,856
|
tests/cpu_instrs/source/common/delay.s
|
; Delays in cycles, milliseconds, etc.
; All routines are re-entrant (no global data). Routines never
; touch BC, DE, or HL registers. These ASSUME CPU is at normal
; speed. If running at double speed, msec/usec delays are half advertised.
; Delays n cycles, from 0 to 16777215
; Preserved: AF, BC, DE, HL
.macro delay ARGS n
.if n < 0
.printt "Delay must be >= 0"
.fail
.endif
.if n > 16777215
.printt "Delay must be < 16777216"
.fail
.endif
delay_ n&$FFFF, n>>16
.endm
; Delays n clocks, from 0 to 16777216*4. Must be multiple of 4.
; Preserved: AF, BC, DE, HL
.macro delay_clocks ARGS n
.if n # 4 != 0
.printt "Delay must be a multiple of 4"
.fail
.endif
delay_ (n/4)&$FFFF,(n/4)>>16
.endm
; Delays n microseconds (1/1000000 second)
; n can range from 0 to 4000 usec.
; Preserved: AF, BC, DE, HL
.macro delay_usec ARGS n
.if n < 0
.printt "Delay must be >= 0"
.fail
.endif
.if n > 4000
.printt "Delay must be <= 4000 usec"
.fail
.endif
delay_ ((n * 1048576 + 500000) / 1000000)&$FFFF,((n * 1048576 + 500000) / 1000000)>>16
.endm
; Delays n milliseconds (1/1000 second)
; n can range from 0 to 10000 msec.
; Preserved: AF, BC, DE, HL
.macro delay_msec ARGS n
.if n < 0
.printt "Delay must be >= 0"
.fail
.endif
.if n > 10000
.printt "Delay must be <= 10000 msec"
.fail
.endif
delay_ ((n * 1048576 + 500) / 1000)&$FFFF, ((n * 1048576 + 500) / 1000)>>16
.endm
; All the low/high quantities are to deal wla-dx's asinine
; restriction full expressions must evaluate to a 16-bit
; value. If the author ever rectifies this, all "high"
; arguments can be treated as zero and removed. Better yet,
; I'll just find an assembler that didn't crawl out of
; the sewer (this is one of too many bugs I've wasted
; hours working around).
.define max_short_delay 28
.macro delay_long_ ARGS n, high
; 0+ to avoid assembler treating as memory read
ld a,0+(((high<<16)+n) - 11) >> 16
call delay_65536a_9_cycles_
delay_nosave_ (((high<<16)+n) - 11)&$FFFF, 0
.endm
; Doesn't save AF, allowing minimization of AF save/restore
.macro delay_nosave_ ARGS n, high
; 65536+11 = maximum delay using delay_256a_9_cycles_
; 255+22 = maximum delay using delay_a_20_cycles
; 22 = minimum delay using delay_a_20_cycles
.if high > 1
delay_long_ n, high
.else
.if high*n > 11
delay_long_ n, high
.else
.if (high*(255+22+1))|n > 255+22
ld a,>(((high<<16)+n) - 11)
call delay_256a_9_cycles_
delay_nosave_ <(((high<<16)+n) - 11), 0
.else
.if n >= 22
ld a,n - 22
call delay_a_20_cycles
.else
delay_short_ n
.endif
.endif
.endif
.endif
.endm
.macro delay_ ARGS low, high
.if (high*(max_short_delay+1))|low > max_short_delay
push af
delay_nosave_ ((high<<16)+low - 7)&$FFFF, ((high<<16)+low - 7)>>16
pop af
.else
delay_short_ low
.endif
.endm
; Delays A cycles + overhead
; Preserved: BC, DE, HL
; Time: A+20 cycles (including CALL)
delay_a_20_cycles:
- sub 5 ; 2
jr nc,- ;3/2 do multiples of 5
rra ; 1
jr nc,+ ;3/2 bit 0
+ adc 1 ; 2
ret nc ;5/2 -1: 0 cycles
ret z ;5/2 0: 2 cycles
nop ; 1 1: 4 cycles
ret ; 4 (thanks to dclxvi for original algorithm)
; Delays A*256 cycles + overhead
; Preserved: BC, DE, HL
; Time: A*256+12 cycles (including CALL)
delay_256a_12_cycles:
or a ; 1
ret z ; 5/2
delay_256a_9_cycles_:
- delay 256-4
dec a ; 1
jr nz,- ;3/2
ret ; 4
; Delays A*65536 cycles + overhead
; Preserved: BC, DE, HL
; Time: A*65536+12 cycles (including CALL)
delay_65536a_12_cycles:
or a ; 1
ret z ;5/2
delay_65536a_9_cycles_:
- delay 65536-4
dec a ; 1
jr nz,- ;3/2
ret ; 4
; Delays H*256+L cycles + overhead
; Preserved: AF, BC, DE, HL
; Time: H*256+L+51 cycles
delay_hl_51_cycles:
push af
ld a,h
call delay_256a_12_cycles
ld a,l
call delay_a_20_cycles
pop af
ret
; delay_short_ macro calls into these
.ds max_short_delay-10,$00 ; NOP repeated several times
delay_unrolled_:
ret
.macro delay_short_ ARGS n
.if n < 0
.fail
.endif
.if n > max_short_delay
.fail
.endif
.if n == 1
nop
.endif
.if n == 2
nop
nop
.endif
.if n == 3
.byte $18,$00 ; JR +0
.endif
.if n == 4
.byte $18,$00 ; JR +0
nop
.endif
.if n == 5
.byte $18,$00 ; JR +0
nop
nop
.endif
.if n == 6
.byte $18,$00 ; JR +0
.byte $18,$00 ; JR +0
.endif
.if n == 7
push af
pop af
.endif
.if n == 8
push af
pop af
nop
.endif
.if n == 9
push af
pop af
nop
nop
.endif
.if n >= 10
call delay_unrolled_ + 10 - n
.endif
.endm
|
aappleby/metroboy
| 2,793
|
tests/cpu_instrs/source/common/runtime.s
|
; Common routines and runtime
; Must be defined by target-specific runtime:
;
; init_runtime: ; target-specific inits
; std_print: ; default routine to print char A
; post_exit: ; called at end of std_exit
; report_byte: ; report A to user
.define RUNTIME_INCLUDED 1
.ifndef bss
; address of next normal variable
.define bss $D800
.endif
.ifndef dp
; address of next direct-page ($FFxx) variable
.define dp $FF80
.endif
; DMG/CGB hardware identifier
.define gb_id_cgb $10 ; mask for testing CGB bit
.define gb_id_devcart $04 ; mask for testing "on devcart" bit
.define gb_id bss
.redefine bss bss+1
; Stack is normally here
.define std_stack $DFFF
; Copies $1000 bytes from HL to $C000, then jumps to it.
; A is preserved for jumped-to code.
copy_to_wram_then_run:
ld b,a
ld de,$C000
ld c,$10
- ldi a,(hl)
ld (de),a
inc e
jr nz,-
inc d
dec c
jr nz,-
ld a,b
jp $C000
.ifndef CUSTOM_RESET
reset:
; Run code from $C000, as is done on devcart. This
; ensures minimal difference in how it behaves.
ld hl,$4000
jp copy_to_wram_then_run
.bank 1 slot 1
.org $0 ; otherwise wla pads with lots of zeroes
jp std_reset
.endif
; Common routines
.include "gb.inc"
.include "macros.inc"
.include "delay.s"
.include "crc.s"
.include "printing.s"
.include "numbers.s"
.include "testing.s"
; Sets up hardware and runs main
std_reset:
; Init hardware
di
ld sp,std_stack
; Save DMG/CGB id
ld (gb_id),a
; Init hardware
.ifndef BUILD_GBS
wreg TAC,$00
wreg IF,$00
wreg IE,$00
.endif
wreg NR52,0 ; sound off
wreg NR52,$80 ; sound on
wreg NR51,$FF ; mono
wreg NR50,$77 ; volume
; TODO: clear all memory?
ld hl,std_print
call init_printing
call init_testing
call init_runtime
call reset_crc ; in case init_runtime prints anything
delay_msec 250
; Run user code
call main
; Default is to successful exit
ld a,0
jp exit
; Exits code and reports value of A
exit:
ld sp,std_stack
push af
call +
pop af
jp post_exit
+ push af
call print_newline
call show_printing
pop af
; Report exit status
cp 1
; 0: ""
ret c
; 1: "Failed"
jr nz,+
print_str "Failed",newline
ret
; n: "Failed #n"
+ print_str "Failed #"
call print_dec
call print_newline
ret
; returnOrg puts this code AFTER user code.
.section "runtime" returnOrg
|
aappleby/metron
| 2,290
|
tests/risc-v/instructions/lh.S
|
# See LICENSE for license details.
#*****************************************************************************
# lh.S
#-----------------------------------------------------------------------------
#
# Test lh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat );
TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat );
TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat );
TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat );
# Test with negative offset
TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 );
TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 );
TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 );
TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lh x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0xffffffffffffff00, \
la x1, tdat; \
addi x1, x1, -5; \
lh x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lh x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lh x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0x00ff
tdat2: .half 0xff00
tdat3: .half 0x0ff0
tdat4: .half 0xf00f
RVTEST_DATA_END
|
aappleby/metron
| 2,597
|
tests/risc-v/instructions/srai.S
|
# See LICENSE for license details.
#*****************************************************************************
# srai.S
#-----------------------------------------------------------------------------
#
# Test srai instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 );
TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 );
TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 );
TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 );
TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 );
TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 );
TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 );
TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 );
TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 );
TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_IMM_ZEROSRC1( 24, srai, 0, 4 );
TEST_IMM_ZERODEST( 25, srai, 33, 10 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 4,022
|
tests/risc-v/instructions/sra.S
|
# See LICENSE for license details.
#*****************************************************************************
# sra.S
#-----------------------------------------------------------------------------
#
# Test sra instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 );
TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 );
TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 );
TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 );
TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 );
TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 );
TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 );
TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 );
TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 );
TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 );
TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 );
TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 );
TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 );
TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 );
TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 );
TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce );
TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 );
TEST_RR_ZEROSRC1( 40, sra, 0, 15 );
TEST_RR_ZEROSRC2( 41, sra, 32, 32 );
TEST_RR_ZEROSRC12( 42, sra, 0 );
TEST_RR_ZERODEST( 43, sra, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,149
|
tests/risc-v/instructions/bge.S
|
# See LICENSE for license details.
#*****************************************************************************
# bge.S
#-----------------------------------------------------------------------------
#
# Test bge instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bge, 0, 0 );
TEST_BR2_OP_TAKEN( 3, bge, 1, 1 );
TEST_BR2_OP_TAKEN( 4, bge, -1, -1 );
TEST_BR2_OP_TAKEN( 5, bge, 1, 0 );
TEST_BR2_OP_TAKEN( 6, bge, 1, -1 );
TEST_BR2_OP_TAKEN( 7, bge, -1, -2 );
TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 );
TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 );
TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 );
TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 );
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 24, x1, 3, \
li x1, 1; \
bge x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,680
|
tests/risc-v/instructions/sw.S
|
# See LICENSE for license details.
#*****************************************************************************
# sw.S
#-----------------------------------------------------------------------------
#
# Test sw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat );
TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat );
TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat );
TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat );
# Test with negative offset
TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 );
TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 );
TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 );
TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x5, 0x12345678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sw x2, 32(x4); \
lw x5, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x58213098, \
la x1, tdat9; \
li x2, 0x58213098; \
addi x1, x1, -3; \
sw x2, 7(x1); \
la x4, tdat10; \
lw x5, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0xdeadbeef
tdat2: .word 0xdeadbeef
tdat3: .word 0xdeadbeef
tdat4: .word 0xdeadbeef
tdat5: .word 0xdeadbeef
tdat6: .word 0xdeadbeef
tdat7: .word 0xdeadbeef
tdat8: .word 0xdeadbeef
tdat9: .word 0xdeadbeef
tdat10: .word 0xdeadbeef
RVTEST_DATA_END
|
aappleby/metron
| 2,175
|
tests/risc-v/instructions/slti.S
|
# See LICENSE for license details.
#*****************************************************************************
# slti.S
#-----------------------------------------------------------------------------
#
# Test slti instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 );
TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 );
TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 );
TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 );
TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 );
TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 );
TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 );
TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff );
TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 );
TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff );
TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff );
TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 );
TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff );
TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 );
TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 );
TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 );
TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 );
TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 );
TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 );
TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 );
TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff );
TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,028
|
tests/risc-v/instructions/blt.S
|
# See LICENSE for license details.
#*****************************************************************************
# blt.S
#-----------------------------------------------------------------------------
#
# Test blt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, blt, 0, 1 );
TEST_BR2_OP_TAKEN( 3, blt, -1, 1 );
TEST_BR2_OP_TAKEN( 4, blt, -2, -1 );
TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 );
TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 );
TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 );
TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
blt x0, x1, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,633
|
tests/risc-v/instructions/and.S
|
# See LICENSE for license details.
#*****************************************************************************
# and.S
#-----------------------------------------------------------------------------
#
# Test and instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, and, 0 );
TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 1,829
|
tests/risc-v/instructions/ori.S
|
# See LICENSE for license details.
#*****************************************************************************
# ori.S
#-----------------------------------------------------------------------------
#
# Test ori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f );
TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f );
TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f );
TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 );
TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,538
|
tests/risc-v/instructions/bgeu.S
|
# See LICENSE for license details.
#*****************************************************************************
# bgeu.S
#-----------------------------------------------------------------------------
#
# Test bgeu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 );
TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 );
TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff );
TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 );
TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe );
TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 );
TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 );
TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 24, x1, 3, \
li x1, 1; \
bgeu x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,949
|
tests/risc-v/instructions/slt.S
|
# See LICENSE for license details.
#*****************************************************************************
# slt.S
#-----------------------------------------------------------------------------
#
# Test slt instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 );
TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 );
TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 );
TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 );
TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 );
TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 );
TEST_RR_ZEROSRC1( 35, slt, 0, -1 );
TEST_RR_ZEROSRC2( 36, slt, 1, -1 );
TEST_RR_ZEROSRC12( 37, slt, 0 );
TEST_RR_ZERODEST( 38, slt, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 3,452
|
tests/risc-v/instructions/srl.S
|
# See LICENSE for license details.
#*****************************************************************************
# srl.S
#-----------------------------------------------------------------------------
#
# Test srl instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
#define TEST_SRL(n, v, a) \
TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
TEST_SRL( 2, 0xffffffff80000000, 0 );
TEST_SRL( 3, 0xffffffff80000000, 1 );
TEST_SRL( 4, 0xffffffff80000000, 7 );
TEST_SRL( 5, 0xffffffff80000000, 14 );
TEST_SRL( 6, 0xffffffff80000001, 31 );
TEST_SRL( 7, 0xffffffffffffffff, 0 );
TEST_SRL( 8, 0xffffffffffffffff, 1 );
TEST_SRL( 9, 0xffffffffffffffff, 7 );
TEST_SRL( 10, 0xffffffffffffffff, 14 );
TEST_SRL( 11, 0xffffffffffffffff, 31 );
TEST_SRL( 12, 0x0000000021212121, 0 );
TEST_SRL( 13, 0x0000000021212121, 1 );
TEST_SRL( 14, 0x0000000021212121, 7 );
TEST_SRL( 15, 0x0000000021212121, 14 );
TEST_SRL( 16, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce );
TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 );
TEST_RR_ZEROSRC1( 40, srl, 0, 15 );
TEST_RR_ZEROSRC2( 41, srl, 32, 32 );
TEST_RR_ZEROSRC12( 42, srl, 0 );
TEST_RR_ZERODEST( 43, srl, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,310
|
tests/risc-v/instructions/lhu.S
|
# See LICENSE for license details.
#*****************************************************************************
# lhu.S
#-----------------------------------------------------------------------------
#
# Test lhu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat );
TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat );
TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat );
TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat );
# Test with negative offset
TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 );
TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 );
TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 );
TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lhu x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x000000000000ff00, \
la x1, tdat; \
addi x1, x1, -5; \
lhu x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lhu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lhu x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0x00ff
tdat2: .half 0xff00
tdat3: .half 0x0ff0
tdat4: .half 0xf00f
RVTEST_DATA_END
|
aappleby/metron
| 2,028
|
tests/risc-v/instructions/beq.S
|
# See LICENSE for license details.
#*****************************************************************************
# beq.S
#-----------------------------------------------------------------------------
#
# Test beq instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, beq, 0, 0 );
TEST_BR2_OP_TAKEN( 3, beq, 1, 1 );
TEST_BR2_OP_TAKEN( 4, beq, -1, -1 );
TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 );
TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 );
TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 );
TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
beq x0, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,308
|
tests/risc-v/instructions/lw.S
|
# See LICENSE for license details.
#*****************************************************************************
# lw.S
#-----------------------------------------------------------------------------
#
# Test lw instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat );
TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat );
TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat );
TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat );
# Test with negative offset
TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 );
TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 );
TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 );
TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x0000000000ff00ff, \
la x1, tdat; \
addi x1, x1, -32; \
lw x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0xffffffffff00ff00, \
la x1, tdat; \
addi x1, x1, -3; \
lw x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lw x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lw x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .word 0x00ff00ff
tdat2: .word 0xff00ff00
tdat3: .word 0x0ff00ff0
tdat4: .word 0xf00ff00f
RVTEST_DATA_END
|
aappleby/metron
| 2,366
|
tests/risc-v/instructions/bltu.S
|
# See LICENSE for license details.
#*****************************************************************************
# bltu.S
#-----------------------------------------------------------------------------
#
# Test bltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 );
TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff );
TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff );
TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe );
TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 );
TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
bltu x0, x1, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 3,145
|
tests/risc-v/instructions/add.S
|
# See LICENSE for license details.
#*****************************************************************************
# add.S
#-----------------------------------------------------------------------------
#
# Test add instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 );
TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 );
TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 );
TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff );
TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 );
TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff );
TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff );
TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 );
TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff );
TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 );
TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff );
TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 );
TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 );
TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 );
TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 );
TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 );
TEST_RR_ZEROSRC1( 35, add, 15, 15 );
TEST_RR_ZEROSRC2( 36, add, 32, 32 );
TEST_RR_ZEROSRC12( 37, add, 0 );
TEST_RR_ZERODEST( 38, add, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 1,087
|
tests/risc-v/instructions/jal.S
|
# See LICENSE for license details.
#*****************************************************************************
# jal.S
#-----------------------------------------------------------------------------
#
# Test jal instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Test 2: Basic test
#-------------------------------------------------------------
test_2:
li TESTNUM, 2
li ra, 0
jal x4, target_2
linkaddr_2:
nop
nop
j fail
target_2:
la x2, linkaddr_2
bne x2, x4, fail
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 3, ra, 3, \
li ra, 1; \
jal x0, 1f; \
addi ra, ra, 1; \
addi ra, ra, 1; \
addi ra, ra, 1; \
addi ra, ra, 1; \
1: addi ra, ra, 1; \
addi ra, ra, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,623
|
tests/risc-v/instructions/or.S
|
# See LICENSE for license details.
#*****************************************************************************
# or.S
#-----------------------------------------------------------------------------
#
# Test or instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f );
TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 );
TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f );
TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 );
TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff );
TEST_RR_ZEROSRC12( 26, or, 0 );
TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,827
|
tests/risc-v/instructions/slli.S
|
# See LICENSE for license details.
#*****************************************************************************
# slli.S
#-----------------------------------------------------------------------------
#
# Test slli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 );
TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 );
TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 );
TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 );
#if __riscv_xlen == 64
TEST_IMM_OP( 50, slli, 0x8000000000000000, 0x0000000000000001, 63 );
TEST_IMM_OP( 51, slli, 0xffffff8000000000, 0xffffffffffffffff, 39 );
TEST_IMM_OP( 52, slli, 0x0909080000000000, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_IMM_ZEROSRC1( 24, slli, 0, 31 );
TEST_IMM_ZERODEST( 25, slli, 33, 20 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,176
|
tests/risc-v/instructions/srli.S
|
# See LICENSE for license details.
#*****************************************************************************
# srli.S
#-----------------------------------------------------------------------------
#
# Test srli instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
#define TEST_SRLI(n, v, a) \
TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a)
TEST_SRLI( 2, 0xffffffff80000000, 0 );
TEST_SRLI( 3, 0xffffffff80000000, 1 );
TEST_SRLI( 4, 0xffffffff80000000, 7 );
TEST_SRLI( 5, 0xffffffff80000000, 14 );
TEST_SRLI( 6, 0xffffffff80000001, 31 );
TEST_SRLI( 7, 0xffffffffffffffff, 0 );
TEST_SRLI( 8, 0xffffffffffffffff, 1 );
TEST_SRLI( 9, 0xffffffffffffffff, 7 );
TEST_SRLI( 10, 0xffffffffffffffff, 14 );
TEST_SRLI( 11, 0xffffffffffffffff, 31 );
TEST_SRLI( 12, 0x0000000021212121, 0 );
TEST_SRLI( 13, 0x0000000021212121, 1 );
TEST_SRLI( 14, 0x0000000021212121, 7 );
TEST_SRLI( 15, 0x0000000021212121, 14 );
TEST_SRLI( 16, 0x0000000021212121, 31 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 );
TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 );
TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 );
TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 );
TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 );
TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 );
TEST_IMM_ZEROSRC1( 24, srli, 0, 4 );
TEST_IMM_ZERODEST( 25, srli, 33, 10 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,013
|
tests/risc-v/instructions/bne.S
|
# See LICENSE for license details.
#*****************************************************************************
# bne.S
#-----------------------------------------------------------------------------
#
# Test bne instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Branch tests
#-------------------------------------------------------------
# Each test checks both forward and backward branches
TEST_BR2_OP_TAKEN( 2, bne, 0, 1 );
TEST_BR2_OP_TAKEN( 3, bne, 1, 0 );
TEST_BR2_OP_TAKEN( 4, bne, -1, 1 );
TEST_BR2_OP_TAKEN( 5, bne, 1, -1 );
TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 );
TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 );
TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 );
TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
TEST_CASE( 21, x1, 3, \
li x1, 1; \
bne x1, x0, 1f; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
addi x1, x1, 1; \
1: addi x1, x1, 1; \
addi x1, x1, 1; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 4,229
|
tests/risc-v/instructions/sll.S
|
# See LICENSE for license details.
#*****************************************************************************
# sll.S
#-----------------------------------------------------------------------------
#
# Test sll instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 );
TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 );
TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 );
TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 );
TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 );
TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 );
TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 );
TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 );
TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 );
TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 );
TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 );
TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 );
# Verify that shifts only use bottom six(rv64) or five(rv32) bits
TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 );
TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 );
TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 );
TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce );
#if __riscv_xlen == 64
TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff );
TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 );
TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 );
TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 );
#endif
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 );
TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 );
TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 );
TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 );
TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 );
TEST_RR_ZEROSRC1( 40, sll, 0, 15 );
TEST_RR_ZEROSRC2( 41, sll, 32, 32 );
TEST_RR_ZEROSRC12( 42, sll, 0 );
TEST_RR_ZERODEST( 43, sll, 1024, 2048 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 1,861
|
tests/risc-v/instructions/xori.S
|
# See LICENSE for license details.
#*****************************************************************************
# xori.S
#-----------------------------------------------------------------------------
#
# Test xori instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f );
TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f );
TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f );
TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 );
TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 );
TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 1,436
|
tests/risc-v/instructions/jalr.S
|
# See LICENSE for license details.
#*****************************************************************************
# jalr.S
#-----------------------------------------------------------------------------
#
# Test jalr instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Test 2: Basic test
#-------------------------------------------------------------
test_2:
li TESTNUM, 2
li t0, 0
la t1, target_2
jalr t0, t1, 0
linkaddr_2:
j fail
target_2:
la t1, linkaddr_2
bne t0, t1, fail
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_JALR_SRC1_BYPASS( 4, 0, jalr );
TEST_JALR_SRC1_BYPASS( 5, 1, jalr );
TEST_JALR_SRC1_BYPASS( 6, 2, jalr );
#-------------------------------------------------------------
# Test delay slot instructions not executed nor bypassed
#-------------------------------------------------------------
.option push
.align 2
.option norvc
TEST_CASE( 7, t0, 4, \
li t0, 1; \
la t1, 1f; \
jr t1, -4; \
addi t0, t0, 1; \
addi t0, t0, 1; \
addi t0, t0, 1; \
addi t0, t0, 1; \
1: addi t0, t0, 1; \
addi t0, t0, 1; \
)
.option pop
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,748
|
tests/risc-v/instructions/sltu.S
|
# See LICENSE for license details.
#*****************************************************************************
# sltu.S
#-----------------------------------------------------------------------------
#
# Test sltu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Arithmetic tests
#-------------------------------------------------------------
TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 );
TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 );
TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 );
TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 );
TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 );
TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 );
TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 );
TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff );
TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 );
TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff );
TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff );
TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 );
TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff );
TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 );
TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 );
TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 );
TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 );
TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 );
TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 );
TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 );
TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 );
TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 );
TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 );
TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 );
TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 );
TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 );
TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 );
TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 );
TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 );
TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 );
TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 );
TEST_RR_ZEROSRC1( 35, sltu, 1, -1 );
TEST_RR_ZEROSRC2( 36, sltu, 0, -1 );
TEST_RR_ZEROSRC12( 37, sltu, 0 );
TEST_RR_ZERODEST( 38, sltu, 16, 30 );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
aappleby/metron
| 2,302
|
tests/risc-v/instructions/lbu.S
|
# See LICENSE for license details.
#*****************************************************************************
# lbu.S
#-----------------------------------------------------------------------------
#
# Test lbu instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat );
TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat );
TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat );
TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat );
# Test with negative offset
TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 );
TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 );
TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 );
TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 );
# Test with a negative base
TEST_CASE( 10, x5, 0x00000000000000ff, \
la x1, tdat; \
addi x1, x1, -32; \
lbu x5, 32(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x0000000000000000, \
la x1, tdat; \
addi x1, x1, -6; \
lbu x5, 7(x1); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 );
TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 );
TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 );
TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 );
TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 );
TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 );
#-------------------------------------------------------------
# Test write-after-write hazard
#-------------------------------------------------------------
TEST_CASE( 18, x2, 2, \
la x5, tdat; \
lbu x2, 0(x5); \
li x2, 2; \
)
TEST_CASE( 19, x2, 2, \
la x5, tdat; \
lbu x2, 0(x5); \
nop; \
li x2, 2; \
)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .byte 0xff
tdat2: .byte 0x00
tdat3: .byte 0xf0
tdat4: .byte 0x0f
RVTEST_DATA_END
|
aappleby/metron
| 2,642
|
tests/risc-v/instructions/sh.S
|
# See LICENSE for license details.
#*****************************************************************************
# sh.S
#-----------------------------------------------------------------------------
#
# Test sh instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Basic tests
#-------------------------------------------------------------
TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat );
TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat );
TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat );
TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat );
# Test with negative offset
TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 );
TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 );
TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 );
TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 );
# Test with a negative base
TEST_CASE( 10, x5, 0x5678, \
la x1, tdat9; \
li x2, 0x12345678; \
addi x4, x1, -32; \
sh x2, 32(x4); \
lh x5, 0(x1); \
)
# Test with unaligned base
TEST_CASE( 11, x5, 0x3098, \
la x1, tdat9; \
li x2, 0x00003098; \
addi x1, x1, -5; \
sh x2, 7(x1); \
la x4, tdat10; \
lh x5, 0(x4); \
)
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat );
TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat );
TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat );
TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat );
TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat );
TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat );
TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat );
TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat );
TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat );
TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat );
TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat );
TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat );
li a0, 0xbeef
la a1, tdat
sh a0, 6(a1)
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
tdat:
tdat1: .half 0xbeef
tdat2: .half 0xbeef
tdat3: .half 0xbeef
tdat4: .half 0xbeef
tdat5: .half 0xbeef
tdat6: .half 0xbeef
tdat7: .half 0xbeef
tdat8: .half 0xbeef
tdat9: .half 0xbeef
tdat10: .half 0xbeef
RVTEST_DATA_END
|
aappleby/metron
| 1,680
|
tests/risc-v/instructions/andi.S
|
# See LICENSE for license details.
#*****************************************************************************
# andi.S
#-----------------------------------------------------------------------------
#
# Test andi instruction.
#
#include "riscv_test.h"
#include "test_macros.h"
RVTEST_RV64U
RVTEST_CODE_BEGIN
#-------------------------------------------------------------
# Logical tests
#-------------------------------------------------------------
TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f );
TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 );
TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f );
TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 );
#-------------------------------------------------------------
# Source/Destination tests
#-------------------------------------------------------------
TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 );
#-------------------------------------------------------------
# Bypassing tests
#-------------------------------------------------------------
TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f );
TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f );
TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 );
TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f );
TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 );
TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f );
TEST_PASSFAIL
RVTEST_CODE_END
.data
RVTEST_DATA_BEGIN
TEST_DATA
RVTEST_DATA_END
|
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