repo_id
stringlengths 5
115
| size
int64 590
5.01M
| file_path
stringlengths 4
212
| content
stringlengths 590
5.01M
|
|---|---|---|---|
4ms/metamodule-plugin-sdk
| 14,909
|
plugin-libc/libgcc/config/cr16/lib1funcs.S
|
/* Libgcc Target specific implementation.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by KPIT Cummins Infosystems Limited.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifdef L_mulsi3
.text
.align 4
.globl ___mulsi3
___mulsi3:
movw r4,r0
movw r2,r1
/* Extended multiplication between the 2 lower words */
muluw r1,(r1,r0)
/* Multiply the lower word of each parameter */
mulw r2,r5
/* With the higher word of the other */
mulw r3,r4
/* Add products to the higher part of the final result */
addw r4,r1
addw r5,r1
jump (ra)
#endif
#ifdef L_divdi3
.text
.align 4
.globl ___divdi3
___divdi3:
push $4, r7, ra
/* Param #1 Long Long low bit first */
loadd 12(sp), (r1, r0)
loadd 16(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 20(sp), (r5, r4)
loadd 24(sp), (r7, r6)
/* Set neg to 0 */
movw $0, r10
subd $16, (sp)
/* Compare if param1 is greater than 0 */
cmpw $0, r3
ble L4
/* Invert param1 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r1, r0) /* Xor low bits of param 1 with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of param 1 with temp */
addd $1, (r1, r0) /* Add 1 to low bits of param 1 */
xorw $1, r10 /* Invert neg */
bcc L4 /* If no carry occurred go to L4 */
addd $1, (r3, r2) /* Add 1 to high bits of param 1 */
L4: stord (r1, r0), 0(sp)
stord (r3, r2), 4(sp)
/* Compare if param2 is greater than 0 */
cmpw $0, r7
ble L5
/* Invert param2 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r5, r4) /* Xor low bits of param 2 with temp */
xord (r9, r8), (r7, r6) /* Xor high bits of param 2 with temp */
addd $1, (r5, r4) /* Add 1 to low bits of param 2 */
xorw $1, r10 /* Invert neg */
bcc L5 /* If no carry occurred go to L5 */
addd $1, (r7, r6) /* Add 1 to high bits of param 2 */
L5: stord (r5, r4), 8(sp)
stord (r7, r6), 12(sp)
movw $0, r2
/* Call udivmoddi3 */
#ifdef __PIC__
loadd ___udivmoddi3@cGOT(r12), (r1,r0)
jal (r1,r0)
#else
bal (ra), ___udivmoddi3
#endif
/* If (neg) */
addd $16, (sp)
cmpw $0, r10 /* Compare 0 with neg */
beq Lexit__
/* Neg = -Neg */
xord (r9, r8), (r1, r0) /* Xor low bits of ures with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of ures with temp */
addd $1, (r1, r0) /* Add 1 to low bits of ures */
bcc Lexit__
addd $1, (r3, r2) /* Add 1 to high bit of ures */
Lexit__:
# ifdef __ID_SHARED_LIB__
pop $2, r12
# endif
popret $4, r7, ra
#endif
#ifdef L_lshrdi3
.text
.align 4
.globl ___lshrdi3
___lshrdi3:
push $3, r7
/* Load parameters from stack in this order */
movw r2, r6 /* Number of shifts */
loadd 6(sp), (r1, r0) /* Low bits */
loadd 10(sp), (r3, r2)/* High bits */
xorw $-1, r6 /* Invert number of shifts */
addw $1, r6 /* Add 1 by number of shifts */
movw r6, r7 /* Copy number of shifts */
tbit $15, r6 /* Test if number is negative */
bfs L2 /* If negative jump to L2 */
movd (r1, r0), (r9, r8) /* Copy low bits */
subw $32, r7 /* Calc how many bits will overflow */
/* Shift the temp low bit to the right to see the overflowing bits */
lshd r7, (r9, r8)
cmpw $32, r6 /* If number of shifts is higher than 31 */
blt L1 /* Shift by moving */
lshd r6, (r3, r2) /* Shift high bits */
lshd r6, (r1, r0) /* Shift low bits */
addd (r9, r8), (r3, r2) /* Add overflow to the high bits */
popret $3, r7 /* Return */
L1: movd $0, (r1, r0) /* Reset low bit */
movd (r9, r8), (r3, r2) /* Add the overflow from the low bit */
popret $3, r7 /* Return */
L2: movd (r3, r2), (r9, r8) /* Copy high bits */
addw $32, r7 /* Calc how many bits will overflow */
/* Shift the temp low bit to the left to see the overflowing bits */
lshd r7, (r9, r8)
cmpw $-32, r6 /* If number of shifts is lower than -31 */
bgt L3 /* Shift by moving */
lshd r6, (r1, r0) /* Shift low bits */
lshd r6, (r3, r2) /* Shift high bits */
addd (r9, r8), (r1, r0) /* Add overflow to the low bits */
popret $3, r7 /* Return */
L3: movd $0, (r3, r2) /* Reset the high bit */
movd (r9, r8), (r1, r0) /* Add the overflow from the high bit */
popret $3, r7 /* Return */
#endif
#ifdef L_moddi3
.text
.align 4
.globl ___moddi3
___moddi3:
push $4, r7, ra
/* Param #1 Long Long low bit first */
loadd 12(sp), (r1, r0)
loadd 16(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 20(sp), (r5, r4)
loadd 24(sp), (r7, r6)
subd $18, (sp)
/* Set neg to 0 */
storw $0, 16(sp)
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
/* Compare if param1 is greater than 0 */
cmpw $0, r3
ble L4
/* Invert param1 and neg */
xord (r9, r8), (r1, r0) /* Xor low bits of param 1 with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of param 1 with temp */
addd $1, (r1, r0) /* Add 1 to low bits of param 1 */
storw $1, 16(sp)
bcc L4 /* If no carry occurred go to L4 */
addd $1, (r3, r2) /* Add 1 to high bits of param 1 */
L4: stord (r1, r0), 0(sp)
stord (r3, r2), 4(sp)
/* Compare if param2 is greater than 0 */
cmpw $0, r7
ble L5
/* Invert param2 and neg */
xord (r9, r8), (r5, r4) /* Xor low bits of param 2 with temp */
xord (r9, r8), (r7, r6) /* Xor high bits of param 2 with temp */
addd $1, (r5, r4) /* Add 1 to low bits of param 2 */
bcc L5 /* If no carry occurred go to L5 */
addd $1, (r7, r6) /* Add 1 to high bits of param 2 */
L5: stord (r5, r4), 8(sp)
stord (r7, r6), 12(sp)
movw $1, r2
/* Call udivmoddi3 */
#ifdef __PIC__
loadd ___udivmoddi3@cGOT(r12), (r1,r0)
jal (r1,r0)
#else
bal (ra), ___udivmoddi3
#endif
/* If (neg) */
loadw 16(sp), r10 /* Load neg from stack */
addd $18, (sp)
cmpw $0, r10 /* Compare 0 with neg */
beq Lexit__
/* Neg = -Neg */
xord (r9, r8), (r1, r0) /* Xor low bits of ures with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of ures with temp */
addd $1, (r1, r0) /* Add 1 to low bits of ures */
bcc Lexit__
addd $1, (r3, r2) /* Add 1 to high bit of ures */
Lexit__:
# ifdef __ID_SHARED_LIB__
pop $2, r12
# endif
popret $4, r7, ra
#endif
#ifdef L_muldi3
.text
.align 4
.globl ___muldi3
___muldi3:
push $2, r13
push $7, r7
/* Param #1 Long Long low bit first */
loadd 18(sp), (r1, r0)
loadd 22(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 26(sp), (r5, r4)
loadd 30(sp), (r7, r6)
/* Clear r13, r12 */
movd $0, (r12)
movd $0, (r13)
/* Set neg */
movw $0, r10
/* Compare if param1 is greater than 0 */
cmpw $0, r3
ble L1
/* Invert param1 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r1, r0) /* Xor low bits of param 1 with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of param 1 with temp */
addd $1, (r1, r0) /* Add 1 to low bits of param 1 */
xorw $1, r10 /* Invert neg */
bcc L1 /* If no carry occurred go to L1 */
addd $1, (r3, r2) /* Add 1 to high bits of param 1 */
L1: /* Compare if param2 is greater than 0 */
cmpw $0, r7
ble L2
/* Invert param2 and neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r5, r4) /* Xor low bits of param 2 with temp */
xord (r9, r8), (r7, r6) /* Xor high bits of param 2 with temp */
addd $1, (r5, r4) /* Add 1 to low bits of param 2 */
xorw $1, r10 /* Invert neg */
bcc L2 /* If no carry occurred go to L2 */
addd $1, (r7, r6) /* Add 1 to high bits of param 2 */
L2: storw r10, 18(sp) /* Store neg to stack so we can use r10 */
/* B*D */
/* Bl*Dl */
macuw r0, r4, (r12) /* Multiply r0 and r4 and add to r12 */
/* Bh*Dl */
movd $0, (r9, r8) /* Clear r9, r8 */
macuw r1, r4, (r9, r8) /* Multiply Bh*Dl and add result to (r9, r8) */
movw r9, r10 /* Shift left: r9 to r10 */
lshd $16, (r9, r8) /* Shift left: r8 to r9 */
movw $0, r11 /* Clear r11 */
addd (r9, r8), (r12) /* Add (r9, r8) to r12 */
bcc L3 /* If no carry occurred go to L3 */
addd $1, (r13) /* If carry occurred add 1 to r13 */
L3: addd (r11, r10), (r13) /* Add (r11, r10) to r13 */
/* Bl*Dh */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r0, r5, (r9, r8) /* Multiply r0 and r5 and stor in (r9, r8) */
movw r9, r10 /* Shift left: r9 to r10 */
lshd $16, (r9, r8) /* Shift left: r8 to r9 */
addd (r9, r8), (r12) /* Add (r9, r8) to r12 */
bcc L4 /* If no carry occurred go to L4 */
addd $1, (r13) /* If carry occurred add 1 to r13 */
L4: addd (r11, r10), (r13) /* Add (r11, r10) to r13 */
/* Bh*Dh */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r1, r5, (r9, r8) /* Multiply r1 and r5 and add to r13 */
addd (r9, r8), (r13) /* Add (r9, r8) to result */
/* A*D */
/* Al*Dl */
movd $0, (r11, r10) /* Clear (r11, r10) */
macuw r2, r4, (r11, r10)/* Multiply r2 and r4 and add to (r11, r10) */
addd (r13), (r11, r10) /* Copy r13 to (r11, r10) */
/* Al*Dh */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r2, r5, (r9, r8) /* Multiply r2 and r5 and add to (r9, r8) */
addw r8, r11 /* Add r8 to r11 */
/* Ah*Dl */
muluw r3, (r5, r4) /* Multiply r3 and r4 and stor in (r5, r4) */
addw r4, r11 /* Add r4 to r11 */
/* B*C */
/* Bl*Cl */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r0, r6, (r9, r8) /* Multiply r0 and r6 and add to (r9, r8) */
addd (r9, r8), (r11, r10)/* Add (r9, r8) to result */
/* Bl*Ch */
movd $0, (r9, r8) /* Clear (r9, r8) */
macuw r0, r7, (r9, r8) /* Multiply r0 and r7 and add to (r9, r8) */
addw r8, r11 /* Add r8 to r11 */
loadw 18(sp), r8 /* Load neg from stack */
/* Bh*Cl */
muluw r1, (r7, r6) /* Multiply r1 and r6 and stor in (r7, r6) */
addw r6, r11 /* Add r6 to r11 */
E1: movd (r11, r10), (r3, r2)
movd (r12), (r1, r0)
/* If (neg) */
cmpw $0, r8 /* Compare 0 with neg */
beq Lexit__
/* Neg = -Neg */
movd $-1, (r9, r8) /* Temp set to FFFFFFFF */
xord (r9, r8), (r1, r0) /* Xor low bits of result with temp */
xord (r9, r8), (r3, r2) /* Xor high bits of result with temp */
addd $1, (r1, r0) /* Add 1 to low bits of result */
bcc Lexit__
addd $1, (r3, r2) /* Add 1 to high bit of result */
Lexit__:
pop $7, r7
popret $2, r13
#endif
#ifdef L_negdi2
.text
.align 4
.globl ___negdi2
___negdi2:
/* Load parameter from the registers in this order */
loadd 0(sp), (r1, r0)
loadd 4(sp), (r3, r2)
movd $-1, (r6, r5) /* Set temp to FFFFFFFF */
xord (r6, r5), (r1, r0) /* Xor low bits with temp */
xord (r6, r5), (r3, r2) /* Xor high bits with temp */
addd $1, (r1, r0) /* Add one */
jcc (ra)
addd $1, (r3, r2) /* Add the carry to the high bits */
jump (ra)
#endif
#ifdef L_udivdi3
.text
.align 4
.globl ___udivdi3
___udivdi3:
movw $0, r2
br ___udivmoddi3
#endif
#ifdef L_udivmoddi3
.text
.align 4
.globl ___udivmoddi3
___udivmoddi3:
push $2, r13
push $7, r7
/* Param #1 Long Long low bit first */
loadd 18(sp), (r1, r0)
storw r2, 18(sp) /* Store modulo on stack */
loadd 22(sp), (r3, r2)
/* Param #2 Long Long low bit first */
loadd 26(sp), (r5, r4)
loadd 30(sp), (r7, r6)
/* Set ures to 0 */
movd $0, (r13)
movd $0, (r12)
cmpd (r12), (r5, r4)
beq LE
L5: movd $1, (r9, r8) /* Store 1 in low bits from bit */
movd $0, (r11, r10) /* Store 0 in high bits from bit */
L6: /* While (den < num && (!den & (1LL<<63))) */
/* Compare high bits from param 1 and param 2 */
cmpd (r7, r6), (r3, r2)
bhi L10 /* If param 2 is greater go to L10 */
bne L8 /* If param 1 is greater go to L8 */
cmpd (r5, r4), (r1, r0) /* Compare low bits from param 1 and param 2 */
/* If param 2 is greater or the same go to L1 */
bhs L10
L8: /* Check if most significant bit of param 2 is set */
tbit $15, r7
bfs L10 /* If PSR is set go to L10 */
/* Shift bit */
lshd $1, (r11, r10) /* Shift left: high bits of bit */
/* Check if most significant bit of bit is set */
tbit $15, r9
lshd $1, (r9, r8) /* Shift left: low bits of bit */
bfs L28 /* If PSR is set go to L28 */
L9: /* Shift b */
lshd $1, (r7, r6) /* Shift left: high bits of param 2 */
/* Check if most significant bit of param 2 is set */
tbit $15, r5
lshd $1, (r5, r4) /* Shift left: low bits of param 2 */
bfc L6 /* If PSR is set go to L6 */
addw $1, r6 /* Add 1 to the highest bits of b */
br L6 /* Go to L6 */
L10: /* While (bit) */
cmpd $0, (r11, r10)
bne L11
cmpd $0, (r9, r8)
beq E1
L11: /* If (num >= den) */
cmpd (r3, r2), (r7, r6) /* Compare high bits of param 1 and param 2 */
blo L15 /* If param 1 lower than param 2 go to L15 */
bne L12 /* If not equal go to L12 */
cmpd (r1, r0), (r5, r4) /* Compare low bits of param 1 and param 2 */
blo L15 /* If param 1 lower than param 2 go to L15 */
L12: /* Ures |= bit */
ord (r11, r10), (r13)
ord (r9, r8), (r12)
/* Num -= den */
subd (r7, r6), (r3, r2) /* Subtract highest 32 bits from each other */
subd (r5, r4), (r1, r0) /* Subtract lowest 32 bits from each other */
bcc L15 /* If no carry occurred go to L15 */
subd $1, (r3, r2) /* Subtract the carry */
L15: /* Shift bit to the right */
lshd $-1, (r9, r8) /* Shift right: low bits of bit */
/* Check if least significant bit of high bits is set */
tbit $0, r10
lshd $-1, (r11, r10) /* Shift right: high bits of bit */
bfs L18 /* If PSR is set go to L18 */
L17: /* Shift param#2 to the right */
lshd $-1, (r5, r4) /* Shift right: low bits of param 2 */
/* Check if least significant bit of high bits is set */
tbit $0, r6
lshd $-1, (r7, r6) /* Shift right: high bits of param 2 */
bfc L10 /* If PSR is not set go to L10 */
/* Or with 0x8000 to set most significant bit */
orw $32768, r5
br L10 /* Go to L10 */
L18: /* Or with 0x8000 to set most significant bit */
orw $32768, r9
br L17
L28: /* Left shift bit */
addw $1, r10 /* Add 1 to highest bits of bit */
br L9 /* Go to L9 */
LE: cmpd (r12), (r7, r6)
bne L5
excp dvz
br Lexit__
E1: loadw 18(sp), r4
cmpw $0, r4
bne Lexit__
/* Return result */
movd (r12), (r1, r0)
movd (r13), (r3, r2)
Lexit__:
pop $7, r7
popret $2, r13
#endif
#ifdef L_umoddi3
.text
.align 4
.globl ___umoddi3
___umoddi3:
movw $1, r2
br ___udivmoddi3
#endif
|
4ms/metamodule-plugin-sdk
| 2,349
|
plugin-libc/libgcc/config/pa/lib2funcs.S
|
; Subroutines for calling unbound dynamic functions from within GDB for HPPA.
; Subroutines for out of line prologues and epilogues on for the HPPA
; Copyright (C) 1994-2022 Free Software Foundation, Inc.
; This file is part of GCC.
; GCC is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3, or (at your option)
; any later version.
; GCC is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
; Under Section 7 of GPL version 3, you are granted additional
; permissions described in the GCC Runtime Library Exception, version
; 3.1, as published by the Free Software Foundation.
; You should have received a copy of the GNU General Public License and
; a copy of the GCC Runtime Library Exception along with this program;
; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
; <http://www.gnu.org/licenses/>.
#if !defined(__pro__) && !defined(__rtems__)
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82
.SPACE $TEXT$
.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44
.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY
.SUBSPA $MILLICODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=8
#endif
.IMPORT $$dyncall,MILLICODE
#if !defined(__pro__) && !defined(__rtems__)
.SPACE $TEXT$
.SUBSPA $CODE$
#else
.text
#endif
; Simply call with the address of the desired import stub in %r22 and
; arguments in the normal place (%r26-%r23 and stack slots).
;
.align 4
.EXPORT __gcc_plt_call,ENTRY,PRIV_LEV=3,RTNVAL=GR
__gcc_plt_call
.PROC
.CALLINFO
.ENTRY
; Our return address comes in %r31, not %r2!
stw %r31,-8(%r30)
; An inline version of dyncall so we don't have to worry
; about long calls to millicode, PIC and other complexities.
bb,>=,n %r22,30,L$foo
depi 0,31,2,%r22
ldw 0(%r22),%r21
ldw 4(%r22),%r19
L$foo
ldsid (%r21),%r1
mtsp %r1,%sr0
ble 0(%sr0,%r21)
copy %r31,%r2
ldw -8(%r30),%r2
; We're going to be returning to a stack address, so we
; need to do an intra-space return.
ldsid (%rp),%r1
mtsp %r1,%sr0
be,n 0(%sr0,%rp)
.EXIT
.PROCEND
|
4ms/metamodule-plugin-sdk
| 72,005
|
plugin-libc/libgcc/config/pa/milli64.S
|
/* 32 and 64-bit millicode, original author Hewlett-Packard
adapted for gcc by Paul Bame <bame@debian.org>
and Alan Modra <alan@linuxcare.com.au>.
Copyright (C) 2001-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#if defined(__ELF__) && defined(__linux__)
.section .note.GNU-stack,"",%progbits
.previous
#endif
#ifdef pa64
.level 2.0w
#endif
/* Hardware General Registers. */
r0: .reg %r0
r1: .reg %r1
r2: .reg %r2
r3: .reg %r3
r4: .reg %r4
r5: .reg %r5
r6: .reg %r6
r7: .reg %r7
r8: .reg %r8
r9: .reg %r9
r10: .reg %r10
r11: .reg %r11
r12: .reg %r12
r13: .reg %r13
r14: .reg %r14
r15: .reg %r15
r16: .reg %r16
r17: .reg %r17
r18: .reg %r18
r19: .reg %r19
r20: .reg %r20
r21: .reg %r21
r22: .reg %r22
r23: .reg %r23
r24: .reg %r24
r25: .reg %r25
r26: .reg %r26
r27: .reg %r27
r28: .reg %r28
r29: .reg %r29
r30: .reg %r30
r31: .reg %r31
/* Hardware Space Registers. */
sr0: .reg %sr0
sr1: .reg %sr1
sr2: .reg %sr2
sr3: .reg %sr3
sr4: .reg %sr4
sr5: .reg %sr5
sr6: .reg %sr6
sr7: .reg %sr7
/* Hardware Floating Point Registers. */
fr0: .reg %fr0
fr1: .reg %fr1
fr2: .reg %fr2
fr3: .reg %fr3
fr4: .reg %fr4
fr5: .reg %fr5
fr6: .reg %fr6
fr7: .reg %fr7
fr8: .reg %fr8
fr9: .reg %fr9
fr10: .reg %fr10
fr11: .reg %fr11
fr12: .reg %fr12
fr13: .reg %fr13
fr14: .reg %fr14
fr15: .reg %fr15
/* Hardware Control Registers. */
cr11: .reg %cr11
sar: .reg %cr11 /* Shift Amount Register */
/* Software Architecture General Registers. */
rp: .reg r2 /* return pointer */
#ifdef pa64
mrp: .reg r2 /* millicode return pointer */
#else
mrp: .reg r31 /* millicode return pointer */
#endif
ret0: .reg r28 /* return value */
ret1: .reg r29 /* return value (high part of double) */
sp: .reg r30 /* stack pointer */
dp: .reg r27 /* data pointer */
arg0: .reg r26 /* argument */
arg1: .reg r25 /* argument or high part of double argument */
arg2: .reg r24 /* argument */
arg3: .reg r23 /* argument or high part of double argument */
/* Software Architecture Space Registers. */
/* sr0 ; return link from BLE */
sret: .reg sr1 /* return value */
sarg: .reg sr1 /* argument */
/* sr4 ; PC SPACE tracker */
/* sr5 ; process private data */
/* Frame Offsets (millicode convention!) Used when calling other
millicode routines. Stack unwinding is dependent upon these
definitions. */
r31_slot: .equ -20 /* "current RP" slot */
sr0_slot: .equ -16 /* "static link" slot */
#if defined(pa64)
mrp_slot: .equ -16 /* "current RP" slot */
psp_slot: .equ -8 /* "previous SP" slot */
#else
mrp_slot: .equ -20 /* "current RP" slot (replacing "r31_slot") */
#endif
#define DEFINE(name,value)name: .EQU value
#define RDEFINE(name,value)name: .REG value
#ifdef milliext
#define MILLI_BE(lbl) BE lbl(sr7,r0)
#define MILLI_BEN(lbl) BE,n lbl(sr7,r0)
#define MILLI_BLE(lbl) BLE lbl(sr7,r0)
#define MILLI_BLEN(lbl) BLE,n lbl(sr7,r0)
#define MILLIRETN BE,n 0(sr0,mrp)
#define MILLIRET BE 0(sr0,mrp)
#define MILLI_RETN BE,n 0(sr0,mrp)
#define MILLI_RET BE 0(sr0,mrp)
#else
#define MILLI_BE(lbl) B lbl
#define MILLI_BEN(lbl) B,n lbl
#define MILLI_BLE(lbl) BL lbl,mrp
#define MILLI_BLEN(lbl) BL,n lbl,mrp
#define MILLIRETN BV,n 0(mrp)
#define MILLIRET BV 0(mrp)
#define MILLI_RETN BV,n 0(mrp)
#define MILLI_RET BV 0(mrp)
#endif
#ifdef __STDC__
#define CAT(a,b) a##b
#else
#define CAT(a,b) a/**/b
#endif
#ifdef ELF
#define SUBSPA_MILLI .section .text
#define SUBSPA_MILLI_DIV .section .text.div,"ax",@progbits! .align 16
#define SUBSPA_MILLI_MUL .section .text.mul,"ax",@progbits! .align 16
#define ATTR_MILLI
#define SUBSPA_DATA .section .data
#define ATTR_DATA
#define GLOBAL $global$
#define GSYM(sym) !sym:
#define LSYM(sym) !CAT(.L,sym:)
#define LREF(sym) CAT(.L,sym)
#else
#ifdef coff
/* This used to be .milli but since link32 places different named
sections in different segments millicode ends up a long ways away
from .text (1meg?). This way they will be a lot closer.
The SUBSPA_MILLI_* specify locality sets for certain millicode
modules in order to ensure that modules that call one another are
placed close together. Without locality sets this is unlikely to
happen because of the Dynamite linker library search algorithm. We
want these modules close together so that short calls always reach
(we don't want to require long calls or use long call stubs). */
#define SUBSPA_MILLI .subspa .text
#define SUBSPA_MILLI_DIV .subspa .text$dv,align=16
#define SUBSPA_MILLI_MUL .subspa .text$mu,align=16
#define ATTR_MILLI .attr code,read,execute
#define SUBSPA_DATA .subspa .data
#define ATTR_DATA .attr init_data,read,write
#define GLOBAL _gp
#else
#define SUBSPA_MILLI .subspa $MILLICODE$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=8
#define SUBSPA_MILLI_DIV SUBSPA_MILLI
#define SUBSPA_MILLI_MUL SUBSPA_MILLI
#define ATTR_MILLI
#define SUBSPA_DATA .subspa $BSS$,quad=1,align=8,access=0x1f,sort=80,zero
#define ATTR_DATA
#define GLOBAL $global$
#endif
#define SPACE_DATA .space $PRIVATE$,spnum=1,sort=16
#define GSYM(sym) !sym
#define LSYM(sym) !CAT(L$,sym)
#define LREF(sym) CAT(L$,sym)
#endif
#ifdef L_dyncall
SUBSPA_MILLI
ATTR_DATA
GSYM($$dyncall)
.export $$dyncall,millicode
.proc
.callinfo millicode
.entry
#ifdef LINUX
extru,<> %r22,30,1,%r0 ; nullify if plabel bit set
bv,n %r0(%r22) ; branch to target
ldw -2(%r22),%r21 ; load address of target
bv %r0(%r21) ; branch to the real target
ldw 2(%r22),%r19 ; load new LTP value
#else
bb,>=,n %r22,30,LREF(1) ; branch if not plabel address
ldw -2(%r22),%r21 ; load address of target to r21
ldsid (%sr0,%r21),%r1 ; get the "space ident" selected by r21
ldw 2(%r22),%r19 ; load new LTP value
mtsp %r1,%sr0 ; move that space identifier into sr0
be 0(%sr0,%r21) ; branch to the real target
stw %r2,-24(%r30) ; save return address into frame marker
LSYM(1)
ldsid (%sr0,%r22),%r1 ; get the "space ident" selected by r22
mtsp %r1,%sr0 ; move that space identifier into sr0
be 0(%sr0,%r22) ; branch to the target
stw %r2,-24(%r30) ; save return address into frame marker
#endif
.exit
.procend
#endif
#ifdef L_divI
/* ROUTINES: $$divI, $$divoI
Single precision divide for signed binary integers.
The quotient is truncated towards zero.
The sign of the quotient is the XOR of the signs of the dividend and
divisor.
Divide by zero is trapped.
Divide of -2**31 by -1 is trapped for $$divoI but not for $$divI.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = quotient
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions:
. divisor is zero (traps with ADDIT,= 0,25,0)
. dividend==-2**31 and divisor==-1 and routine is $$divoI
. (traps with ADDO 26,25,0)
. Changes memory at the following places:
. NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Branchs to other millicode routines using BE
. $$div_# for # being 2,3,4,5,6,7,8,9,10,12,14,15
.
. For selected divisors, calls a divide by constant routine written by
. Karl Pettis. Eligible divisors are 1..15 excluding 11 and 13.
.
. The only overflow case is -2**31 divided by -1.
. Both routines return -2**31 but only $$divoI traps. */
RDEFINE(temp,r1)
RDEFINE(retreg,ret1) /* r29 */
RDEFINE(temp1,arg0)
SUBSPA_MILLI_DIV
ATTR_MILLI
.import $$divI_2,millicode
.import $$divI_3,millicode
.import $$divI_4,millicode
.import $$divI_5,millicode
.import $$divI_6,millicode
.import $$divI_7,millicode
.import $$divI_8,millicode
.import $$divI_9,millicode
.import $$divI_10,millicode
.import $$divI_12,millicode
.import $$divI_14,millicode
.import $$divI_15,millicode
.export $$divI,millicode
.export $$divoI,millicode
.proc
.callinfo millicode
.entry
GSYM($$divoI)
comib,=,n -1,arg1,LREF(negative1) /* when divisor == -1 */
GSYM($$divI)
ldo -1(arg1),temp /* is there at most one bit set ? */
and,<> arg1,temp,r0 /* if not, don't use power of 2 divide */
addi,> 0,arg1,r0 /* if divisor > 0, use power of 2 divide */
b,n LREF(neg_denom)
LSYM(pow2)
addi,>= 0,arg0,retreg /* if numerator is negative, add the */
add arg0,temp,retreg /* (denominaotr -1) to correct for shifts */
extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
extrs retreg,15,16,retreg /* retreg = retreg >> 16 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
ldi 0xcc,temp1 /* setup 0xcc in temp1 */
extru,= arg1,23,8,temp /* test denominator with 0xff00 */
extrs retreg,23,24,retreg /* retreg = retreg >> 8 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
ldi 0xaa,temp /* setup 0xaa in temp */
extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
extrs retreg,27,28,retreg /* retreg = retreg >> 4 */
and,= arg1,temp1,r0 /* test denominator with 0xcc */
extrs retreg,29,30,retreg /* retreg = retreg >> 2 */
and,= arg1,temp,r0 /* test denominator with 0xaa */
extrs retreg,30,31,retreg /* retreg = retreg >> 1 */
MILLIRETN
LSYM(neg_denom)
addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power of 2 */
b,n LREF(regular_seq)
sub r0,arg1,temp /* make denominator positive */
comb,=,n arg1,temp,LREF(regular_seq) /* test against 0x80000000 and 0 */
ldo -1(temp),retreg /* is there at most one bit set ? */
and,= temp,retreg,r0 /* if so, the denominator is power of 2 */
b,n LREF(regular_seq)
sub r0,arg0,retreg /* negate numerator */
comb,=,n arg0,retreg,LREF(regular_seq) /* test against 0x80000000 */
copy retreg,arg0 /* set up arg0, arg1 and temp */
copy temp,arg1 /* before branching to pow2 */
b LREF(pow2)
ldo -1(arg1),temp
LSYM(regular_seq)
comib,>>=,n 15,arg1,LREF(small_divisor)
add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
LSYM(normal)
subi 0,retreg,retreg /* make it positive */
sub 0,arg1,temp /* clear carry, */
/* negate the divisor */
ds 0,temp,0 /* set V-bit to the comple- */
/* ment of the divisor sign */
add retreg,retreg,retreg /* shift msb bit into carry */
ds r0,arg1,temp /* 1st divide step, if no carry */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 2nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 3rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 4th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 5th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 6th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 7th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 8th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 9th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 10th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 11th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 12th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 13th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 14th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 15th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 16th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 17th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 18th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 19th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 20th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 21st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 22nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 23rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 24th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 25th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 26th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 27th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 28th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 29th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 30th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 31st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 32nd divide step, */
addc retreg,retreg,retreg /* shift last retreg bit into retreg */
xor,>= arg0,arg1,0 /* get correct sign of quotient */
sub 0,retreg,retreg /* based on operand signs */
MILLIRETN
nop
LSYM(small_divisor)
#if defined(pa64)
/* Clear the upper 32 bits of the arg1 register. We are working with */
/* small divisors (and 32-bit integers) We must not be mislead */
/* by "1" bits left in the upper 32 bits. */
depd %r0,31,32,%r25
#endif
blr,n arg1,r0
nop
/* table for divisor == 0,1, ... ,15 */
addit,= 0,arg1,r0 /* trap if divisor == 0 */
nop
MILLIRET /* divisor == 1 */
copy arg0,retreg
MILLI_BEN($$divI_2) /* divisor == 2 */
nop
MILLI_BEN($$divI_3) /* divisor == 3 */
nop
MILLI_BEN($$divI_4) /* divisor == 4 */
nop
MILLI_BEN($$divI_5) /* divisor == 5 */
nop
MILLI_BEN($$divI_6) /* divisor == 6 */
nop
MILLI_BEN($$divI_7) /* divisor == 7 */
nop
MILLI_BEN($$divI_8) /* divisor == 8 */
nop
MILLI_BEN($$divI_9) /* divisor == 9 */
nop
MILLI_BEN($$divI_10) /* divisor == 10 */
nop
b LREF(normal) /* divisor == 11 */
add,>= 0,arg0,retreg
MILLI_BEN($$divI_12) /* divisor == 12 */
nop
b LREF(normal) /* divisor == 13 */
add,>= 0,arg0,retreg
MILLI_BEN($$divI_14) /* divisor == 14 */
nop
MILLI_BEN($$divI_15) /* divisor == 15 */
nop
LSYM(negative1)
sub 0,arg0,retreg /* result is negation of dividend */
MILLIRET
addo arg0,arg1,r0 /* trap iff dividend==0x80000000 && divisor==-1 */
.exit
.procend
.end
#endif
#ifdef L_divU
/* ROUTINE: $$divU
.
. Single precision divide for unsigned integers.
.
. Quotient is truncated towards zero.
. Traps on divide by zero.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = quotient
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions:
. divisor is zero
. Changes memory at the following places:
. NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Does not create a stack frame.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Branchs to other millicode routines using BE:
. $$divU_# for 3,5,6,7,9,10,12,14,15
.
. For selected small divisors calls the special divide by constant
. routines written by Karl Pettis. These are: 3,5,6,7,9,10,12,14,15. */
RDEFINE(temp,r1)
RDEFINE(retreg,ret1) /* r29 */
RDEFINE(temp1,arg0)
SUBSPA_MILLI_DIV
ATTR_MILLI
.export $$divU,millicode
.import $$divU_3,millicode
.import $$divU_5,millicode
.import $$divU_6,millicode
.import $$divU_7,millicode
.import $$divU_9,millicode
.import $$divU_10,millicode
.import $$divU_12,millicode
.import $$divU_14,millicode
.import $$divU_15,millicode
.proc
.callinfo millicode
.entry
GSYM($$divU)
/* The subtract is not nullified since it does no harm and can be used
by the two cases that branch back to "normal". */
ldo -1(arg1),temp /* is there at most one bit set ? */
and,= arg1,temp,r0 /* if so, denominator is power of 2 */
b LREF(regular_seq)
addit,= 0,arg1,0 /* trap for zero dvr */
copy arg0,retreg
extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
extru retreg,15,16,retreg /* retreg = retreg >> 16 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
ldi 0xcc,temp1 /* setup 0xcc in temp1 */
extru,= arg1,23,8,temp /* test denominator with 0xff00 */
extru retreg,23,24,retreg /* retreg = retreg >> 8 */
or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
ldi 0xaa,temp /* setup 0xaa in temp */
extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
extru retreg,27,28,retreg /* retreg = retreg >> 4 */
and,= arg1,temp1,r0 /* test denominator with 0xcc */
extru retreg,29,30,retreg /* retreg = retreg >> 2 */
and,= arg1,temp,r0 /* test denominator with 0xaa */
extru retreg,30,31,retreg /* retreg = retreg >> 1 */
MILLIRETN
nop
LSYM(regular_seq)
comib,>= 15,arg1,LREF(special_divisor)
subi 0,arg1,temp /* clear carry, negate the divisor */
ds r0,temp,r0 /* set V-bit to 1 */
LSYM(normal)
add arg0,arg0,retreg /* shift msb bit into carry */
ds r0,arg1,temp /* 1st divide step, if no carry */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 2nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 3rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 4th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 5th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 6th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 7th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 8th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 9th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 10th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 11th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 12th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 13th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 14th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 15th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 16th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 17th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 18th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 19th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 20th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 21st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 22nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 23rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 24th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 25th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 26th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 27th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 28th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 29th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 30th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 31st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds temp,arg1,temp /* 32nd divide step, */
MILLIRET
addc retreg,retreg,retreg /* shift last retreg bit into retreg */
/* Handle the cases where divisor is a small constant or has high bit on. */
LSYM(special_divisor)
/* blr arg1,r0 */
/* comib,>,n 0,arg1,LREF(big_divisor) ; nullify previous instruction */
/* Pratap 8/13/90. The 815 Stirling chip set has a bug that prevents us from
generating such a blr, comib sequence. A problem in nullification. So I
rewrote this code. */
#if defined(pa64)
/* Clear the upper 32 bits of the arg1 register. We are working with
small divisors (and 32-bit unsigned integers) We must not be mislead
by "1" bits left in the upper 32 bits. */
depd %r0,31,32,%r25
#endif
comib,> 0,arg1,LREF(big_divisor)
nop
blr arg1,r0
nop
LSYM(zero_divisor) /* this label is here to provide external visibility */
addit,= 0,arg1,0 /* trap for zero dvr */
nop
MILLIRET /* divisor == 1 */
copy arg0,retreg
MILLIRET /* divisor == 2 */
extru arg0,30,31,retreg
MILLI_BEN($$divU_3) /* divisor == 3 */
nop
MILLIRET /* divisor == 4 */
extru arg0,29,30,retreg
MILLI_BEN($$divU_5) /* divisor == 5 */
nop
MILLI_BEN($$divU_6) /* divisor == 6 */
nop
MILLI_BEN($$divU_7) /* divisor == 7 */
nop
MILLIRET /* divisor == 8 */
extru arg0,28,29,retreg
MILLI_BEN($$divU_9) /* divisor == 9 */
nop
MILLI_BEN($$divU_10) /* divisor == 10 */
nop
b LREF(normal) /* divisor == 11 */
ds r0,temp,r0 /* set V-bit to 1 */
MILLI_BEN($$divU_12) /* divisor == 12 */
nop
b LREF(normal) /* divisor == 13 */
ds r0,temp,r0 /* set V-bit to 1 */
MILLI_BEN($$divU_14) /* divisor == 14 */
nop
MILLI_BEN($$divU_15) /* divisor == 15 */
nop
/* Handle the case where the high bit is on in the divisor.
Compute: if( dividend>=divisor) quotient=1; else quotient=0;
Note: dividend>==divisor iff dividend-divisor does not borrow
and not borrow iff carry. */
LSYM(big_divisor)
sub arg0,arg1,r0
MILLIRET
addc r0,r0,retreg
.exit
.procend
.end
#endif
#ifdef L_remI
/* ROUTINE: $$remI
DESCRIPTION:
. $$remI returns the remainder of the division of two signed 32-bit
. integers. The sign of the remainder is the same as the sign of
. the dividend.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = destroyed
. arg1 = destroyed
. ret1 = remainder
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions: DIVIDE BY ZERO
. Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
. Unwindable
. Does not create a stack frame
. Is usable for internal or external microcode
DISCUSSION:
. Calls other millicode routines via mrp: NONE
. Calls other millicode routines: NONE */
RDEFINE(tmp,r1)
RDEFINE(retreg,ret1)
SUBSPA_MILLI
ATTR_MILLI
.proc
.callinfo millicode
.entry
GSYM($$remI)
GSYM($$remoI)
.export $$remI,MILLICODE
.export $$remoI,MILLICODE
ldo -1(arg1),tmp /* is there at most one bit set ? */
and,<> arg1,tmp,r0 /* if not, don't use power of 2 */
addi,> 0,arg1,r0 /* if denominator > 0, use power */
/* of 2 */
b,n LREF(neg_denom)
LSYM(pow2)
comb,>,n 0,arg0,LREF(neg_num) /* is numerator < 0 ? */
and arg0,tmp,retreg /* get the result */
MILLIRETN
LSYM(neg_num)
subi 0,arg0,arg0 /* negate numerator */
and arg0,tmp,retreg /* get the result */
subi 0,retreg,retreg /* negate result */
MILLIRETN
LSYM(neg_denom)
addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power */
/* of 2 */
b,n LREF(regular_seq)
sub r0,arg1,tmp /* make denominator positive */
comb,=,n arg1,tmp,LREF(regular_seq) /* test against 0x80000000 and 0 */
ldo -1(tmp),retreg /* is there at most one bit set ? */
and,= tmp,retreg,r0 /* if not, go to regular_seq */
b,n LREF(regular_seq)
comb,>,n 0,arg0,LREF(neg_num_2) /* if arg0 < 0, negate it */
and arg0,retreg,retreg
MILLIRETN
LSYM(neg_num_2)
subi 0,arg0,tmp /* test against 0x80000000 */
and tmp,retreg,retreg
subi 0,retreg,retreg
MILLIRETN
LSYM(regular_seq)
addit,= 0,arg1,0 /* trap if div by zero */
add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
sub 0,retreg,retreg /* make it positive */
sub 0,arg1, tmp /* clear carry, */
/* negate the divisor */
ds 0, tmp,0 /* set V-bit to the comple- */
/* ment of the divisor sign */
or 0,0, tmp /* clear tmp */
add retreg,retreg,retreg /* shift msb bit into carry */
ds tmp,arg1, tmp /* 1st divide step, if no carry */
/* out, msb of quotient = 0 */
addc retreg,retreg,retreg /* shift retreg with/into carry */
LSYM(t1)
ds tmp,arg1, tmp /* 2nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 3rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 4th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 5th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 6th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 7th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 8th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 9th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 10th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 11th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 12th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 13th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 14th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 15th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 16th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 17th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 18th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 19th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 20th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 21st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 22nd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 23rd divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 24th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 25th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 26th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 27th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 28th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 29th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 30th divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 31st divide step */
addc retreg,retreg,retreg /* shift retreg with/into carry */
ds tmp,arg1, tmp /* 32nd divide step, */
addc retreg,retreg,retreg /* shift last bit into retreg */
movb,>=,n tmp,retreg,LREF(finish) /* branch if pos. tmp */
add,< arg1,0,0 /* if arg1 > 0, add arg1 */
add,tr tmp,arg1,retreg /* for correcting remainder tmp */
sub tmp,arg1,retreg /* else add absolute value arg1 */
LSYM(finish)
add,>= arg0,0,0 /* set sign of remainder */
sub 0,retreg,retreg /* to sign of dividend */
MILLIRET
nop
.exit
.procend
#ifdef milliext
.origin 0x00000200
#endif
.end
#endif
#ifdef L_remU
/* ROUTINE: $$remU
. Single precision divide for remainder with unsigned binary integers.
.
. The remainder must be dividend-(dividend/divisor)*divisor.
. Divide by zero is trapped.
INPUT REGISTERS:
. arg0 == dividend
. arg1 == divisor
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = remainder
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions: DIVIDE BY ZERO
. Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Does not create a stack frame.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Calls other millicode routines using mrp: NONE
. Calls other millicode routines: NONE */
RDEFINE(temp,r1)
RDEFINE(rmndr,ret1) /* r29 */
SUBSPA_MILLI
ATTR_MILLI
.export $$remU,millicode
.proc
.callinfo millicode
.entry
GSYM($$remU)
ldo -1(arg1),temp /* is there at most one bit set ? */
and,= arg1,temp,r0 /* if not, don't use power of 2 */
b LREF(regular_seq)
addit,= 0,arg1,r0 /* trap on div by zero */
and arg0,temp,rmndr /* get the result for power of 2 */
MILLIRETN
LSYM(regular_seq)
comib,>=,n 0,arg1,LREF(special_case)
subi 0,arg1,rmndr /* clear carry, negate the divisor */
ds r0,rmndr,r0 /* set V-bit to 1 */
add arg0,arg0,temp /* shift msb bit into carry */
ds r0,arg1,rmndr /* 1st divide step, if no carry */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 2nd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 3rd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 4th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 5th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 6th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 7th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 8th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 9th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 10th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 11th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 12th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 13th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 14th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 15th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 16th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 17th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 18th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 19th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 20th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 21st divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 22nd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 23rd divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 24th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 25th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 26th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 27th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 28th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 29th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 30th divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 31st divide step */
addc temp,temp,temp /* shift temp with/into carry */
ds rmndr,arg1,rmndr /* 32nd divide step, */
comiclr,<= 0,rmndr,r0
add rmndr,arg1,rmndr /* correction */
MILLIRETN
nop
/* Putting >= on the last DS and deleting COMICLR does not work! */
LSYM(special_case)
sub,>>= arg0,arg1,rmndr
copy arg0,rmndr
MILLIRETN
nop
.exit
.procend
.end
#endif
#ifdef L_div_const
/* ROUTINE: $$divI_2
. $$divI_3 $$divU_3
. $$divI_4
. $$divI_5 $$divU_5
. $$divI_6 $$divU_6
. $$divI_7 $$divU_7
. $$divI_8
. $$divI_9 $$divU_9
. $$divI_10 $$divU_10
.
. $$divI_12 $$divU_12
.
. $$divI_14 $$divU_14
. $$divI_15 $$divU_15
. $$divI_16
. $$divI_17 $$divU_17
.
. Divide by selected constants for single precision binary integers.
INPUT REGISTERS:
. arg0 == dividend
. mrp == return pc
. sr0 == return space when called externally
OUTPUT REGISTERS:
. arg0 = undefined
. arg1 = undefined
. ret1 = quotient
OTHER REGISTERS AFFECTED:
. r1 = undefined
SIDE EFFECTS:
. Causes a trap under the following conditions: NONE
. Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
. Unwindable.
. Does not create a stack frame.
. Suitable for internal or external millicode.
. Assumes the special millicode register conventions.
DISCUSSION:
. Calls other millicode routines using mrp: NONE
. Calls other millicode routines: NONE */
/* TRUNCATED DIVISION BY SMALL INTEGERS
We are interested in q(x) = floor(x/y), where x >= 0 and y > 0
(with y fixed).
Let a = floor(z/y), for some choice of z. Note that z will be
chosen so that division by z is cheap.
Let r be the remainder(z/y). In other words, r = z - ay.
Now, our method is to choose a value for b such that
q'(x) = floor((ax+b)/z)
is equal to q(x) over as large a range of x as possible. If the
two are equal over a sufficiently large range, and if it is easy to
form the product (ax), and it is easy to divide by z, then we can
perform the division much faster than the general division algorithm.
So, we want the following to be true:
. For x in the following range:
.
. ky <= x < (k+1)y
.
. implies that
.
. k <= (ax+b)/z < (k+1)
We want to determine b such that this is true for all k in the
range {0..K} for some maximum K.
Since (ax+b) is an increasing function of x, we can take each
bound separately to determine the "best" value for b.
(ax+b)/z < (k+1) implies
(a((k+1)y-1)+b < (k+1)z implies
b < a + (k+1)(z-ay) implies
b < a + (k+1)r
This needs to be true for all k in the range {0..K}. In
particular, it is true for k = 0 and this leads to a maximum
acceptable value for b.
b < a+r or b <= a+r-1
Taking the other bound, we have
k <= (ax+b)/z implies
k <= (aky+b)/z implies
k(z-ay) <= b implies
kr <= b
Clearly, the largest range for k will be achieved by maximizing b,
when r is not zero. When r is zero, then the simplest choice for b
is 0. When r is not 0, set
. b = a+r-1
Now, by construction, q'(x) = floor((ax+b)/z) = q(x) = floor(x/y)
for all x in the range:
. 0 <= x < (K+1)y
We need to determine what K is. Of our two bounds,
. b < a+(k+1)r is satisfied for all k >= 0, by construction.
The other bound is
. kr <= b
This is always true if r = 0. If r is not 0 (the usual case), then
K = floor((a+r-1)/r), is the maximum value for k.
Therefore, the formula q'(x) = floor((ax+b)/z) yields the correct
answer for q(x) = floor(x/y) when x is in the range
(0,(K+1)y-1) K = floor((a+r-1)/r)
To be most useful, we want (K+1)y-1 = (max x) >= 2**32-1 so that
the formula for q'(x) yields the correct value of q(x) for all x
representable by a single word in HPPA.
We are also constrained in that computing the product (ax), adding
b, and dividing by z must all be done quickly, otherwise we will be
better off going through the general algorithm using the DS
instruction, which uses approximately 70 cycles.
For each y, there is a choice of z which satisfies the constraints
for (K+1)y >= 2**32. We may not, however, be able to satisfy the
timing constraints for arbitrary y. It seems that z being equal to
a power of 2 or a power of 2 minus 1 is as good as we can do, since
it minimizes the time to do division by z. We want the choice of z
to also result in a value for (a) that minimizes the computation of
the product (ax). This is best achieved if (a) has a regular bit
pattern (so the multiplication can be done with shifts and adds).
The value of (a) also needs to be less than 2**32 so the product is
always guaranteed to fit in 2 words.
In actual practice, the following should be done:
1) For negative x, you should take the absolute value and remember
. the fact so that the result can be negated. This obviously does
. not apply in the unsigned case.
2) For even y, you should factor out the power of 2 that divides y
. and divide x by it. You can then proceed by dividing by the
. odd factor of y.
Here is a table of some odd values of y, and corresponding choices
for z which are "good".
y z r a (hex) max x (hex)
3 2**32 1 55555555 100000001
5 2**32 1 33333333 100000003
7 2**24-1 0 249249 (infinite)
9 2**24-1 0 1c71c7 (infinite)
11 2**20-1 0 1745d (infinite)
13 2**24-1 0 13b13b (infinite)
15 2**32 1 11111111 10000000d
17 2**32 1 f0f0f0f 10000000f
If r is 1, then b = a+r-1 = a. This simplifies the computation
of (ax+b), since you can compute (x+1)(a) instead. If r is 0,
then b = 0 is ok to use which simplifies (ax+b).
The bit patterns for 55555555, 33333333, and 11111111 are obviously
very regular. The bit patterns for the other values of a above are:
y (hex) (binary)
7 249249 001001001001001001001001 << regular >>
9 1c71c7 000111000111000111000111 << regular >>
11 1745d 000000010111010001011101 << irregular >>
13 13b13b 000100111011000100111011 << irregular >>
The bit patterns for (a) corresponding to (y) of 11 and 13 may be
too irregular to warrant using this method.
When z is a power of 2 minus 1, then the division by z is slightly
more complicated, involving an iterative solution.
The code presented here solves division by 1 through 17, except for
11 and 13. There are algorithms for both signed and unsigned
quantities given.
TIMINGS (cycles)
divisor positive negative unsigned
. 1 2 2 2
. 2 4 4 2
. 3 19 21 19
. 4 4 4 2
. 5 18 22 19
. 6 19 22 19
. 8 4 4 2
. 10 18 19 17
. 12 18 20 18
. 15 16 18 16
. 16 4 4 2
. 17 16 18 16
Now, the algorithm for 7, 9, and 14 is an iterative one. That is,
a loop body is executed until the tentative quotient is 0. The
number of times the loop body is executed varies depending on the
dividend, but is never more than two times. If the dividend is
less than the divisor, then the loop body is not executed at all.
Each iteration adds 4 cycles to the timings.
divisor positive negative unsigned
. 7 19+4n 20+4n 20+4n n = number of iterations
. 9 21+4n 22+4n 21+4n
. 14 21+4n 22+4n 20+4n
To give an idea of how the number of iterations varies, here is a
table of dividend versus number of iterations when dividing by 7.
smallest largest required
dividend dividend iterations
. 0 6 0
. 7 0x6ffffff 1
0x1000006 0xffffffff 2
There is some overlap in the range of numbers requiring 1 and 2
iterations. */
RDEFINE(t2,r1)
RDEFINE(x2,arg0) /* r26 */
RDEFINE(t1,arg1) /* r25 */
RDEFINE(x1,ret1) /* r29 */
SUBSPA_MILLI_DIV
ATTR_MILLI
.proc
.callinfo millicode
.entry
/* NONE of these routines require a stack frame
ALL of these routines are unwindable from millicode */
GSYM($$divide_by_constant)
.export $$divide_by_constant,millicode
/* Provides a "nice" label for the code covered by the unwind descriptor
for things like gprof. */
/* DIVISION BY 2 (shift by 1) */
GSYM($$divI_2)
.export $$divI_2,millicode
comclr,>= arg0,0,0
addi 1,arg0,arg0
MILLIRET
extrs arg0,30,31,ret1
/* DIVISION BY 4 (shift by 2) */
GSYM($$divI_4)
.export $$divI_4,millicode
comclr,>= arg0,0,0
addi 3,arg0,arg0
MILLIRET
extrs arg0,29,30,ret1
/* DIVISION BY 8 (shift by 3) */
GSYM($$divI_8)
.export $$divI_8,millicode
comclr,>= arg0,0,0
addi 7,arg0,arg0
MILLIRET
extrs arg0,28,29,ret1
/* DIVISION BY 16 (shift by 4) */
GSYM($$divI_16)
.export $$divI_16,millicode
comclr,>= arg0,0,0
addi 15,arg0,arg0
MILLIRET
extrs arg0,27,28,ret1
/****************************************************************************
*
* DIVISION BY DIVISORS OF FFFFFFFF, and powers of 2 times these
*
* includes 3,5,15,17 and also 6,10,12
*
****************************************************************************/
/* DIVISION BY 3 (use z = 2**32; a = 55555555) */
GSYM($$divI_3)
.export $$divI_3,millicode
comb,<,N x2,0,LREF(neg3)
addi 1,x2,x2 /* this cannot overflow */
extru x2,1,2,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,0,x1
LSYM(neg3)
subi 1,x2,x2 /* this cannot overflow */
extru x2,1,2,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(neg)
addc x1,0,x1
GSYM($$divU_3)
.export $$divU_3,millicode
addi 1,x2,x2 /* this CAN overflow */
addc 0,0,x1
shd x1,x2,30,t1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,t1,x1
/* DIVISION BY 5 (use z = 2**32; a = 33333333) */
GSYM($$divI_5)
.export $$divI_5,millicode
comb,<,N x2,0,LREF(neg5)
addi 3,x2,t1 /* this cannot overflow */
sh1add x2,t1,x2 /* multiply by 3 to get started */
b LREF(pos)
addc 0,0,x1
LSYM(neg5)
sub 0,x2,x2 /* negate x2 */
addi 1,x2,x2 /* this cannot overflow */
shd 0,x2,31,x1 /* get top bit (can be 1) */
sh1add x2,x2,x2 /* multiply by 3 to get started */
b LREF(neg)
addc x1,0,x1
GSYM($$divU_5)
.export $$divU_5,millicode
addi 1,x2,x2 /* this CAN overflow */
addc 0,0,x1
shd x1,x2,31,t1 /* multiply by 3 to get started */
sh1add x2,x2,x2
b LREF(pos)
addc t1,x1,x1
/* DIVISION BY 6 (shift to divide by 2 then divide by 3) */
GSYM($$divI_6)
.export $$divI_6,millicode
comb,<,N x2,0,LREF(neg6)
extru x2,30,31,x2 /* divide by 2 */
addi 5,x2,t1 /* compute 5*(x2+1) = 5*x2+5 */
sh2add x2,t1,x2 /* multiply by 5 to get started */
b LREF(pos)
addc 0,0,x1
LSYM(neg6)
subi 2,x2,x2 /* negate, divide by 2, and add 1 */
/* negation and adding 1 are done */
/* at the same time by the SUBI */
extru x2,30,31,x2
shd 0,x2,30,x1
sh2add x2,x2,x2 /* multiply by 5 to get started */
b LREF(neg)
addc x1,0,x1
GSYM($$divU_6)
.export $$divU_6,millicode
extru x2,30,31,x2 /* divide by 2 */
addi 1,x2,x2 /* cannot carry */
shd 0,x2,30,x1 /* multiply by 5 to get started */
sh2add x2,x2,x2
b LREF(pos)
addc x1,0,x1
/* DIVISION BY 10 (shift to divide by 2 then divide by 5) */
GSYM($$divU_10)
.export $$divU_10,millicode
extru x2,30,31,x2 /* divide by 2 */
addi 3,x2,t1 /* compute 3*(x2+1) = (3*x2)+3 */
sh1add x2,t1,x2 /* multiply by 3 to get started */
addc 0,0,x1
LSYM(pos)
shd x1,x2,28,t1 /* multiply by 0x11 */
shd x2,0,28,t2
add x2,t2,x2
addc x1,t1,x1
LSYM(pos_for_17)
shd x1,x2,24,t1 /* multiply by 0x101 */
shd x2,0,24,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,16,t1 /* multiply by 0x10001 */
shd x2,0,16,t2
add x2,t2,x2
MILLIRET
addc x1,t1,x1
GSYM($$divI_10)
.export $$divI_10,millicode
comb,< x2,0,LREF(neg10)
copy 0,x1
extru x2,30,31,x2 /* divide by 2 */
addib,TR 1,x2,LREF(pos) /* add 1 (cannot overflow) */
sh1add x2,x2,x2 /* multiply by 3 to get started */
LSYM(neg10)
subi 2,x2,x2 /* negate, divide by 2, and add 1 */
/* negation and adding 1 are done */
/* at the same time by the SUBI */
extru x2,30,31,x2
sh1add x2,x2,x2 /* multiply by 3 to get started */
LSYM(neg)
shd x1,x2,28,t1 /* multiply by 0x11 */
shd x2,0,28,t2
add x2,t2,x2
addc x1,t1,x1
LSYM(neg_for_17)
shd x1,x2,24,t1 /* multiply by 0x101 */
shd x2,0,24,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,16,t1 /* multiply by 0x10001 */
shd x2,0,16,t2
add x2,t2,x2
addc x1,t1,x1
MILLIRET
sub 0,x1,x1
/* DIVISION BY 12 (shift to divide by 4 then divide by 3) */
GSYM($$divI_12)
.export $$divI_12,millicode
comb,< x2,0,LREF(neg12)
copy 0,x1
extru x2,29,30,x2 /* divide by 4 */
addib,tr 1,x2,LREF(pos) /* compute 5*(x2+1) = 5*x2+5 */
sh2add x2,x2,x2 /* multiply by 5 to get started */
LSYM(neg12)
subi 4,x2,x2 /* negate, divide by 4, and add 1 */
/* negation and adding 1 are done */
/* at the same time by the SUBI */
extru x2,29,30,x2
b LREF(neg)
sh2add x2,x2,x2 /* multiply by 5 to get started */
GSYM($$divU_12)
.export $$divU_12,millicode
extru x2,29,30,x2 /* divide by 4 */
addi 5,x2,t1 /* cannot carry */
sh2add x2,t1,x2 /* multiply by 5 to get started */
b LREF(pos)
addc 0,0,x1
/* DIVISION BY 15 (use z = 2**32; a = 11111111) */
GSYM($$divI_15)
.export $$divI_15,millicode
comb,< x2,0,LREF(neg15)
copy 0,x1
addib,tr 1,x2,LREF(pos)+4
shd x1,x2,28,t1
LSYM(neg15)
b LREF(neg)
subi 1,x2,x2
GSYM($$divU_15)
.export $$divU_15,millicode
addi 1,x2,x2 /* this CAN overflow */
b LREF(pos)
addc 0,0,x1
/* DIVISION BY 17 (use z = 2**32; a = f0f0f0f) */
GSYM($$divI_17)
.export $$divI_17,millicode
comb,<,n x2,0,LREF(neg17)
addi 1,x2,x2 /* this cannot overflow */
shd 0,x2,28,t1 /* multiply by 0xf to get started */
shd x2,0,28,t2
sub t2,x2,x2
b LREF(pos_for_17)
subb t1,0,x1
LSYM(neg17)
subi 1,x2,x2 /* this cannot overflow */
shd 0,x2,28,t1 /* multiply by 0xf to get started */
shd x2,0,28,t2
sub t2,x2,x2
b LREF(neg_for_17)
subb t1,0,x1
GSYM($$divU_17)
.export $$divU_17,millicode
addi 1,x2,x2 /* this CAN overflow */
addc 0,0,x1
shd x1,x2,28,t1 /* multiply by 0xf to get started */
LSYM(u17)
shd x2,0,28,t2
sub t2,x2,x2
b LREF(pos_for_17)
subb t1,x1,x1
/* DIVISION BY DIVISORS OF FFFFFF, and powers of 2 times these
includes 7,9 and also 14
z = 2**24-1
r = z mod x = 0
so choose b = 0
Also, in order to divide by z = 2**24-1, we approximate by dividing
by (z+1) = 2**24 (which is easy), and then correcting.
(ax) = (z+1)q' + r
. = zq' + (q'+r)
So to compute (ax)/z, compute q' = (ax)/(z+1) and r = (ax) mod (z+1)
Then the true remainder of (ax)/z is (q'+r). Repeat the process
with this new remainder, adding the tentative quotients together,
until a tentative quotient is 0 (and then we are done). There is
one last correction to be done. It is possible that (q'+r) = z.
If so, then (q'+r)/(z+1) = 0 and it looks like we are done. But,
in fact, we need to add 1 more to the quotient. Now, it turns
out that this happens if and only if the original value x is
an exact multiple of y. So, to avoid a three instruction test at
the end, instead use 1 instruction to add 1 to x at the beginning. */
/* DIVISION BY 7 (use z = 2**24-1; a = 249249) */
GSYM($$divI_7)
.export $$divI_7,millicode
comb,<,n x2,0,LREF(neg7)
LSYM(7)
addi 1,x2,x2 /* cannot overflow */
shd 0,x2,29,x1
sh3add x2,x2,x2
addc x1,0,x1
LSYM(pos7)
shd x1,x2,26,t1
shd x2,0,26,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,20,t1
shd x2,0,20,t2
add x2,t2,x2
addc x1,t1,t1
/* computed <t1,x2>. Now divide it by (2**24 - 1) */
copy 0,x1
shd,= t1,x2,24,t1 /* tentative quotient */
LSYM(1)
addb,tr t1,x1,LREF(2) /* add to previous quotient */
extru x2,31,24,x2 /* new remainder (unadjusted) */
MILLIRETN
LSYM(2)
addb,tr t1,x2,LREF(1) /* adjust remainder */
extru,= x2,7,8,t1 /* new quotient */
LSYM(neg7)
subi 1,x2,x2 /* negate x2 and add 1 */
LSYM(8)
shd 0,x2,29,x1
sh3add x2,x2,x2
addc x1,0,x1
LSYM(neg7_shift)
shd x1,x2,26,t1
shd x2,0,26,t2
add x2,t2,x2
addc x1,t1,x1
shd x1,x2,20,t1
shd x2,0,20,t2
add x2,t2,x2
addc x1,t1,t1
/* computed <t1,x2>. Now divide it by (2**24 - 1) */
copy 0,x1
shd,= t1,x2,24,t1 /* tentative quotient */
LSYM(3)
addb,tr t1,x1,LREF(4) /* add to previous quotient */
extru x2,31,24,x2 /* new remainder (unadjusted) */
MILLIRET
sub 0,x1,x1 /* negate result */
LSYM(4)
addb,tr t1,x2,LREF(3) /* adjust remainder */
extru,= x2,7,8,t1 /* new quotient */
GSYM($$divU_7)
.export $$divU_7,millicode
addi 1,x2,x2 /* can carry */
addc 0,0,x1
shd x1,x2,29,t1
sh3add x2,x2,x2
b LREF(pos7)
addc t1,x1,x1
/* DIVISION BY 9 (use z = 2**24-1; a = 1c71c7) */
GSYM($$divI_9)
.export $$divI_9,millicode
comb,<,n x2,0,LREF(neg9)
addi 1,x2,x2 /* cannot overflow */
shd 0,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
b LREF(pos7)
subb t1,0,x1
LSYM(neg9)
subi 1,x2,x2 /* negate and add 1 */
shd 0,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
b LREF(neg7_shift)
subb t1,0,x1
GSYM($$divU_9)
.export $$divU_9,millicode
addi 1,x2,x2 /* can carry */
addc 0,0,x1
shd x1,x2,29,t1
shd x2,0,29,t2
sub t2,x2,x2
b LREF(pos7)
subb t1,x1,x1
/* DIVISION BY 14 (shift to divide by 2 then divide by 7) */
GSYM($$divI_14)
.export $$divI_14,millicode
comb,<,n x2,0,LREF(neg14)
GSYM($$divU_14)
.export $$divU_14,millicode
b LREF(7) /* go to 7 case */
extru x2,30,31,x2 /* divide by 2 */
LSYM(neg14)
subi 2,x2,x2 /* negate (and add 2) */
b LREF(8)
extru x2,30,31,x2 /* divide by 2 */
.exit
.procend
.end
#endif
#ifdef L_mulI
/* VERSION "@(#)$$mulI $ Revision: 12.4 $ $ Date: 94/03/17 17:18:51 $" */
/******************************************************************************
This routine is used on PA2.0 processors when gcc -mno-fpregs is used
ROUTINE: $$mulI
DESCRIPTION:
$$mulI multiplies two single word integers, giving a single
word result.
INPUT REGISTERS:
arg0 = Operand 1
arg1 = Operand 2
r31 == return pc
sr0 == return space when called externally
OUTPUT REGISTERS:
arg0 = undefined
arg1 = undefined
ret1 = result
OTHER REGISTERS AFFECTED:
r1 = undefined
SIDE EFFECTS:
Causes a trap under the following conditions: NONE
Changes memory at the following places: NONE
PERMISSIBLE CONTEXT:
Unwindable
Does not create a stack frame
Is usable for internal or external microcode
DISCUSSION:
Calls other millicode routines via mrp: NONE
Calls other millicode routines: NONE
***************************************************************************/
#define a0 %arg0
#define a1 %arg1
#define t0 %r1
#define r %ret1
#define a0__128a0 zdep a0,24,25,a0
#define a0__256a0 zdep a0,23,24,a0
#define a1_ne_0_b_l0 comb,<> a1,0,LREF(l0)
#define a1_ne_0_b_l1 comb,<> a1,0,LREF(l1)
#define a1_ne_0_b_l2 comb,<> a1,0,LREF(l2)
#define b_n_ret_t0 b,n LREF(ret_t0)
#define b_e_shift b LREF(e_shift)
#define b_e_t0ma0 b LREF(e_t0ma0)
#define b_e_t0 b LREF(e_t0)
#define b_e_t0a0 b LREF(e_t0a0)
#define b_e_t02a0 b LREF(e_t02a0)
#define b_e_t04a0 b LREF(e_t04a0)
#define b_e_2t0 b LREF(e_2t0)
#define b_e_2t0a0 b LREF(e_2t0a0)
#define b_e_2t04a0 b LREF(e2t04a0)
#define b_e_3t0 b LREF(e_3t0)
#define b_e_4t0 b LREF(e_4t0)
#define b_e_4t0a0 b LREF(e_4t0a0)
#define b_e_4t08a0 b LREF(e4t08a0)
#define b_e_5t0 b LREF(e_5t0)
#define b_e_8t0 b LREF(e_8t0)
#define b_e_8t0a0 b LREF(e_8t0a0)
#define r__r_a0 add r,a0,r
#define r__r_2a0 sh1add a0,r,r
#define r__r_4a0 sh2add a0,r,r
#define r__r_8a0 sh3add a0,r,r
#define r__r_t0 add r,t0,r
#define r__r_2t0 sh1add t0,r,r
#define r__r_4t0 sh2add t0,r,r
#define r__r_8t0 sh3add t0,r,r
#define t0__3a0 sh1add a0,a0,t0
#define t0__4a0 sh2add a0,0,t0
#define t0__5a0 sh2add a0,a0,t0
#define t0__8a0 sh3add a0,0,t0
#define t0__9a0 sh3add a0,a0,t0
#define t0__16a0 zdep a0,27,28,t0
#define t0__32a0 zdep a0,26,27,t0
#define t0__64a0 zdep a0,25,26,t0
#define t0__128a0 zdep a0,24,25,t0
#define t0__t0ma0 sub t0,a0,t0
#define t0__t0_a0 add t0,a0,t0
#define t0__t0_2a0 sh1add a0,t0,t0
#define t0__t0_4a0 sh2add a0,t0,t0
#define t0__t0_8a0 sh3add a0,t0,t0
#define t0__2t0_a0 sh1add t0,a0,t0
#define t0__3t0 sh1add t0,t0,t0
#define t0__4t0 sh2add t0,0,t0
#define t0__4t0_a0 sh2add t0,a0,t0
#define t0__5t0 sh2add t0,t0,t0
#define t0__8t0 sh3add t0,0,t0
#define t0__8t0_a0 sh3add t0,a0,t0
#define t0__9t0 sh3add t0,t0,t0
#define t0__16t0 zdep t0,27,28,t0
#define t0__32t0 zdep t0,26,27,t0
#define t0__256a0 zdep a0,23,24,t0
SUBSPA_MILLI
ATTR_MILLI
.align 16
.proc
.callinfo millicode
.export $$mulI,millicode
GSYM($$mulI)
combt,<<= a1,a0,LREF(l4) /* swap args if unsigned a1>a0 */
copy 0,r /* zero out the result */
xor a0,a1,a0 /* swap a0 & a1 using the */
xor a0,a1,a1 /* old xor trick */
xor a0,a1,a0
LSYM(l4)
combt,<= 0,a0,LREF(l3) /* if a0>=0 then proceed like unsigned */
zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
sub,> 0,a1,t0 /* otherwise negate both and */
combt,<=,n a0,t0,LREF(l2) /* swap back if |a0|<|a1| */
sub 0,a0,a1
movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
LSYM(l0) r__r_t0 /* add in this partial product */
LSYM(l1) a0__256a0 /* a0 <<= 8 ****************** */
LSYM(l2) zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
LSYM(l3) blr t0,0 /* case on these 8 bits ****** */
extru a1,23,24,a1 /* a1 >>= 8 ****************** */
/*16 insts before this. */
/* a0 <<= 8 ************************** */
LSYM(x0) a1_ne_0_b_l2 ! a0__256a0 ! MILLIRETN ! nop
LSYM(x1) a1_ne_0_b_l1 ! r__r_a0 ! MILLIRETN ! nop
LSYM(x2) a1_ne_0_b_l1 ! r__r_2a0 ! MILLIRETN ! nop
LSYM(x3) a1_ne_0_b_l0 ! t0__3a0 ! MILLIRET ! r__r_t0
LSYM(x4) a1_ne_0_b_l1 ! r__r_4a0 ! MILLIRETN ! nop
LSYM(x5) a1_ne_0_b_l0 ! t0__5a0 ! MILLIRET ! r__r_t0
LSYM(x6) t0__3a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
LSYM(x7) t0__3a0 ! a1_ne_0_b_l0 ! r__r_4a0 ! b_n_ret_t0
LSYM(x8) a1_ne_0_b_l1 ! r__r_8a0 ! MILLIRETN ! nop
LSYM(x9) a1_ne_0_b_l0 ! t0__9a0 ! MILLIRET ! r__r_t0
LSYM(x10) t0__5a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
LSYM(x11) t0__3a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
LSYM(x12) t0__3a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
LSYM(x13) t0__5a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
LSYM(x14) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x15) t0__5a0 ! a1_ne_0_b_l0 ! t0__3t0 ! b_n_ret_t0
LSYM(x16) t0__16a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x17) t0__9a0 ! a1_ne_0_b_l0 ! t0__t0_8a0 ! b_n_ret_t0
LSYM(x18) t0__9a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
LSYM(x19) t0__9a0 ! a1_ne_0_b_l0 ! t0__2t0_a0 ! b_n_ret_t0
LSYM(x20) t0__5a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
LSYM(x21) t0__5a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
LSYM(x22) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x23) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x24) t0__3a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
LSYM(x25) t0__5a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
LSYM(x26) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x27) t0__3a0 ! a1_ne_0_b_l0 ! t0__9t0 ! b_n_ret_t0
LSYM(x28) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x29) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x30) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
LSYM(x31) t0__32a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
LSYM(x32) t0__32a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x33) t0__8a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
LSYM(x34) t0__16a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x35) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__t0_8a0
LSYM(x36) t0__9a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
LSYM(x37) t0__9a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
LSYM(x38) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x39) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x40) t0__5a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
LSYM(x41) t0__5a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
LSYM(x42) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x43) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x44) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x45) t0__9a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
LSYM(x46) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_a0
LSYM(x47) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_2a0
LSYM(x48) t0__3a0 ! a1_ne_0_b_l0 ! t0__16t0 ! b_n_ret_t0
LSYM(x49) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_4a0
LSYM(x50) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
LSYM(x51) t0__9a0 ! t0__t0_8a0 ! b_e_t0 ! t0__3t0
LSYM(x52) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x53) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x54) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
LSYM(x55) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x56) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x57) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x58) t0__3a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x59) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__3t0
LSYM(x60) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
LSYM(x61) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x62) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x63) t0__64a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
LSYM(x64) t0__64a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x65) t0__8a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
LSYM(x66) t0__32a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x67) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x68) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x69) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x70) t0__64a0 ! t0__t0_4a0 ! b_e_t0 ! t0__t0_2a0
LSYM(x71) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__t0ma0
LSYM(x72) t0__9a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
LSYM(x73) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_t0
LSYM(x74) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x75) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x76) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x77) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x78) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x79) t0__16a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
LSYM(x80) t0__16a0 ! t0__5t0 ! b_e_shift ! r__r_t0
LSYM(x81) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_t0
LSYM(x82) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x83) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x84) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x85) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x86) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x87) t0__9a0 ! t0__9t0 ! b_e_t02a0 ! t0__t0_4a0
LSYM(x88) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x89) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x90) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
LSYM(x91) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x92) t0__5a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x93) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__3t0
LSYM(x94) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__t0_2a0
LSYM(x95) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x96) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
LSYM(x97) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x98) t0__32a0 ! t0__3t0 ! b_e_t0 ! t0__t0_2a0
LSYM(x99) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x100) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
LSYM(x101) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x102) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
LSYM(x103) t0__5a0 ! t0__5t0 ! b_e_t02a0 ! t0__4t0_a0
LSYM(x104) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x105) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x106) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x107) t0__9a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__8t0_a0
LSYM(x108) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
LSYM(x109) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x110) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x111) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x112) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__16t0
LSYM(x113) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__3t0
LSYM(x114) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__3t0
LSYM(x115) t0__9a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x116) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__4t0_a0
LSYM(x117) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
LSYM(x118) t0__3a0 ! t0__4t0_a0 ! b_e_t0a0 ! t0__9t0
LSYM(x119) t0__3a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__9t0
LSYM(x120) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
LSYM(x121) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x122) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x123) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x124) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
LSYM(x125) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
LSYM(x126) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x127) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
LSYM(x128) t0__128a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
LSYM(x129) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0_a0 ! b_n_ret_t0
LSYM(x130) t0__64a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x131) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x132) t0__8a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x133) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x134) t0__8a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x135) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__3t0
LSYM(x136) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x137) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x138) t0__8a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x139) t0__8a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__4t0_a0
LSYM(x140) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__5t0
LSYM(x141) t0__8a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__2t0_a0
LSYM(x142) t0__9a0 ! t0__8t0 ! b_e_2t0 ! t0__t0ma0
LSYM(x143) t0__16a0 ! t0__9t0 ! b_e_t0 ! t0__t0ma0
LSYM(x144) t0__9a0 ! t0__8t0 ! b_e_shift ! r__r_2t0
LSYM(x145) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x146) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
LSYM(x147) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
LSYM(x148) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x149) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
LSYM(x150) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x151) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
LSYM(x152) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x153) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x154) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x155) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__5t0
LSYM(x156) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x157) t0__32a0 ! t0__t0ma0 ! b_e_t02a0 ! t0__5t0
LSYM(x158) t0__16a0 ! t0__5t0 ! b_e_2t0 ! t0__t0ma0
LSYM(x159) t0__32a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
LSYM(x160) t0__5a0 ! t0__4t0 ! b_e_shift ! r__r_8t0
LSYM(x161) t0__8a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x162) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_2t0
LSYM(x163) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__2t0_a0
LSYM(x164) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_4t0
LSYM(x165) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x166) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x167) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
LSYM(x168) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
LSYM(x169) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__8t0_a0
LSYM(x170) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__5t0
LSYM(x171) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__9t0
LSYM(x172) t0__5a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x173) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__9t0
LSYM(x174) t0__32a0 ! t0__t0_2a0 ! b_e_t04a0 ! t0__5t0
LSYM(x175) t0__8a0 ! t0__2t0_a0 ! b_e_5t0 ! t0__2t0_a0
LSYM(x176) t0__5a0 ! t0__4t0_a0 ! b_e_8t0 ! t0__t0_a0
LSYM(x177) t0__5a0 ! t0__4t0_a0 ! b_e_8t0a0 ! t0__t0_a0
LSYM(x178) t0__5a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__8t0_a0
LSYM(x179) t0__5a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__8t0_a0
LSYM(x180) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
LSYM(x181) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
LSYM(x182) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__2t0_a0
LSYM(x183) t0__9a0 ! t0__5t0 ! b_e_2t0a0 ! t0__2t0_a0
LSYM(x184) t0__5a0 ! t0__9t0 ! b_e_4t0 ! t0__t0_a0
LSYM(x185) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x186) t0__32a0 ! t0__t0ma0 ! b_e_2t0 ! t0__3t0
LSYM(x187) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__5t0
LSYM(x188) t0__9a0 ! t0__5t0 ! b_e_4t0 ! t0__t0_2a0
LSYM(x189) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
LSYM(x190) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__5t0
LSYM(x191) t0__64a0 ! t0__3t0 ! b_e_t0 ! t0__t0ma0
LSYM(x192) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
LSYM(x193) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x194) t0__8a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x195) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x196) t0__8a0 ! t0__3t0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x197) t0__8a0 ! t0__3t0 ! b_e_4t0a0 ! t0__2t0_a0
LSYM(x198) t0__64a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
LSYM(x199) t0__8a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x200) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_8t0
LSYM(x201) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x202) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x203) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__4t0_a0
LSYM(x204) t0__8a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
LSYM(x205) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__5t0
LSYM(x206) t0__64a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__3t0
LSYM(x207) t0__8a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
LSYM(x208) t0__5a0 ! t0__5t0 ! b_e_8t0 ! t0__t0_a0
LSYM(x209) t0__5a0 ! t0__5t0 ! b_e_8t0a0 ! t0__t0_a0
LSYM(x210) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__5t0
LSYM(x211) t0__5a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__5t0
LSYM(x212) t0__3a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__4t0_a0
LSYM(x213) t0__3a0 ! t0__4t0_a0 ! b_e_4t0a0 ! t0__4t0_a0
LSYM(x214) t0__9a0 ! t0__t0_4a0 ! b_e_2t04a0 ! t0__8t0_a0
LSYM(x215) t0__5a0 ! t0__4t0_a0 ! b_e_5t0 ! t0__2t0_a0
LSYM(x216) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
LSYM(x217) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
LSYM(x218) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
LSYM(x219) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
LSYM(x220) t0__3a0 ! t0__9t0 ! b_e_4t0 ! t0__2t0_a0
LSYM(x221) t0__3a0 ! t0__9t0 ! b_e_4t0a0 ! t0__2t0_a0
LSYM(x222) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__3t0
LSYM(x223) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x224) t0__9a0 ! t0__3t0 ! b_e_8t0 ! t0__t0_a0
LSYM(x225) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
LSYM(x226) t0__3a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__32t0
LSYM(x227) t0__9a0 ! t0__5t0 ! b_e_t02a0 ! t0__5t0
LSYM(x228) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
LSYM(x229) t0__9a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__3t0
LSYM(x230) t0__9a0 ! t0__5t0 ! b_e_5t0 ! t0__t0_a0
LSYM(x231) t0__9a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
LSYM(x232) t0__3a0 ! t0__2t0_a0 ! b_e_8t0 ! t0__4t0_a0
LSYM(x233) t0__3a0 ! t0__2t0_a0 ! b_e_8t0a0 ! t0__4t0_a0
LSYM(x234) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__9t0
LSYM(x235) t0__3a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__9t0
LSYM(x236) t0__9a0 ! t0__2t0_a0 ! b_e_4t08a0 ! t0__3t0
LSYM(x237) t0__16a0 ! t0__5t0 ! b_e_3t0 ! t0__t0ma0
LSYM(x238) t0__3a0 ! t0__4t0_a0 ! b_e_2t04a0 ! t0__9t0
LSYM(x239) t0__16a0 ! t0__5t0 ! b_e_t0ma0 ! t0__3t0
LSYM(x240) t0__9a0 ! t0__t0_a0 ! b_e_8t0 ! t0__3t0
LSYM(x241) t0__9a0 ! t0__t0_a0 ! b_e_8t0a0 ! t0__3t0
LSYM(x242) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__8t0_a0
LSYM(x243) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__3t0
LSYM(x244) t0__5a0 ! t0__3t0 ! b_e_4t0 ! t0__4t0_a0
LSYM(x245) t0__8a0 ! t0__3t0 ! b_e_5t0 ! t0__2t0_a0
LSYM(x246) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__3t0
LSYM(x247) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__3t0
LSYM(x248) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_8t0
LSYM(x249) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__8t0_a0
LSYM(x250) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__5t0
LSYM(x251) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__5t0
LSYM(x252) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
LSYM(x253) t0__64a0 ! t0__t0ma0 ! b_e_t0 ! t0__4t0_a0
LSYM(x254) t0__128a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
/*1040 insts before this. */
LSYM(ret_t0) MILLIRET
LSYM(e_t0) r__r_t0
LSYM(e_shift) a1_ne_0_b_l2
a0__256a0 /* a0 <<= 8 *********** */
MILLIRETN
LSYM(e_t0ma0) a1_ne_0_b_l0
t0__t0ma0
MILLIRET
r__r_t0
LSYM(e_t0a0) a1_ne_0_b_l0
t0__t0_a0
MILLIRET
r__r_t0
LSYM(e_t02a0) a1_ne_0_b_l0
t0__t0_2a0
MILLIRET
r__r_t0
LSYM(e_t04a0) a1_ne_0_b_l0
t0__t0_4a0
MILLIRET
r__r_t0
LSYM(e_2t0) a1_ne_0_b_l1
r__r_2t0
MILLIRETN
LSYM(e_2t0a0) a1_ne_0_b_l0
t0__2t0_a0
MILLIRET
r__r_t0
LSYM(e2t04a0) t0__t0_2a0
a1_ne_0_b_l1
r__r_2t0
MILLIRETN
LSYM(e_3t0) a1_ne_0_b_l0
t0__3t0
MILLIRET
r__r_t0
LSYM(e_4t0) a1_ne_0_b_l1
r__r_4t0
MILLIRETN
LSYM(e_4t0a0) a1_ne_0_b_l0
t0__4t0_a0
MILLIRET
r__r_t0
LSYM(e4t08a0) t0__t0_2a0
a1_ne_0_b_l1
r__r_4t0
MILLIRETN
LSYM(e_5t0) a1_ne_0_b_l0
t0__5t0
MILLIRET
r__r_t0
LSYM(e_8t0) a1_ne_0_b_l1
r__r_8t0
MILLIRETN
LSYM(e_8t0a0) a1_ne_0_b_l0
t0__8t0_a0
MILLIRET
r__r_t0
.procend
.end
#endif
|
4ms/metamodule-plugin-sdk
| 1,746
|
plugin-libc/libgcc/config/csky/crtn.S
|
# Terminate C-SKY .init and .fini sections.
# Copyright (C) 2018-2022 Free Software Foundation, Inc.
# Contributed by C-SKY Microsystems and Mentor Graphics.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just makes sure that the .fini and .init sections do in
# fact return. Users may put any desired instructions in those sections.
# This file is the last thing linked into any executable.
.file "crtn.S"
# Is this the GLIBC version?
#if defined(__gnu_linux__)
.section .init,"ax",@progbits
ldw lr, (sp, 0)
addi sp, 8
rts
.section .fini,"ax",@progbits
ldw lr, (sp, 0)
addi sp, 8
rts
#else /* !defined(__gnu_linux__) */
.section ".init"
ldw lr, (sp, 12)
addi sp, 16
jmp lr
.section ".fini"
ldw lr, (sp, 12)
addi sp, 16
jmp lr
# Th-th-th-that is all folks!
#endif /* defined(__gnu_linux__) */
|
4ms/metamodule-plugin-sdk
| 3,106
|
plugin-libc/libgcc/config/csky/crti.S
|
# Define _init and _fini entry points for C-SKY.
# Copyright (C) 2018-2022 Free Software Foundation, Inc.
# Contributed by C-SKY Microsystems and Mentor Graphics.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just makes a stack frame for the contents of the .fini and
# .init sections. Users may put any desired instructions in those
# sections.
.file "crti.S"
/* We use more complicated versions of this code with GLIBC. */
#if defined(__gnu_linux__)
#ifndef PREINIT_FUNCTION
# define PREINIT_FUNCTION __gmon_start__
#endif
#ifndef PREINIT_FUNCTION_WEAK
# define PREINIT_FUNCTION_WEAK 1
#endif
#if PREINIT_FUNCTION_WEAK
.global PREINIT_FUNCTION
.weak PREINIT_FUNCTION
.align 4
.type call_weak_fn, %function
call_weak_fn:
// push lr
subi sp, 4
stw lr, (sp)
#ifdef __PIC__
lrw a2, PREINIT_FUNCTION@GOT
addu a2, gb
ldw a2, (a2)
#else
lrw a2, PREINIT_FUNCTION
#endif
cmpnei a2, 0
bf 1f
jsr a2
1:
// pop lr
ldw lr, (sp)
addi sp, 4
rts
.align 4
#else
.hidden PREINIT_FUNCTION
#endif /* PREINIT_FUNCTION_WEAK */
.section .init,"ax",@progbits
.align 4
.globl _init
.type _init, @function
_init:
subi sp, 8
stw lr, (sp, 0)
#ifdef __PIC__
// stw gb, (sp, 4)
bsr .Lgetpc
.Lgetpc:
lrw gb, .Lgetpc@GOTPC
add gb, lr
#endif
#if PREINIT_FUNCTION_WEAK
#ifdef __PIC__
lrw a2, call_weak_fn@GOTOFF
add a2, gb
jsr a2
#else
jsri call_weak_fn
#endif
#else /* !PREINIT_FUNCTION_WEAK */
#ifdef __PIC__
lrw a2, PREINIT_FUNCTION@PLT
addu a2, gb
ldw a2, (a2)
jsr a2
#else
jsri PREINIT_FUNCTION
#endif
#endif /* PREINIT_FUNCTION_WEAK */
br 2f
.literals
.align 4
2:
.section .fini,"ax",@progbits
.align 4
.globl _fini
.type _fini, @function
_fini:
subi sp,8
stw lr, (sp, 0)
br 2f
.literals
.align 4
2:
/* These are the non-GLIBC versions. */
#else /* !defined(__gnu_linux__) */
.section ".init"
.global _init
.type _init,@function
.align 2
_init:
subi sp, 16
st.w lr, (sp, 12)
mov r0, r0
.section ".fini"
.global _fini
.type _fini,@function
.align 2
_fini:
subi sp, 16
st.w lr, (sp, 12)
mov r0, r0
#endif /* defined(__gnu_linux__) */
|
4ms/metamodule-plugin-sdk
| 12,754
|
plugin-libc/libgcc/config/csky/lib1funcs.S
|
/* libgcc routines for C-SKY.
Copyright (C) 2018-2022 Free Software Foundation, Inc.
Contributed by C-SKY Microsystems and Mentor Graphics.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Use the right prefix for global labels. */
#define CONCAT1(a, b) CONCAT2(a, b)
#define CONCAT2(a, b) a ## b
#define SYM(x) CONCAT1 (__, x)
#ifndef __CSKYBE__
#define xl r0
#define xh r1
#define yl r2
#define yh r3
#else
#define xh r0
#define xl r1
#define yh r2
#define yl r3
#endif
#ifdef __ELF__
#define TYPE(x) .type SYM (x),@function
#define SIZE(x) .size SYM (x), . - SYM (x)
#else
#define TYPE(x)
#define SIZE(x)
#endif
.macro FUNC_START name
.text
.align 2
.globl SYM (\name)
TYPE (\name)
SYM (\name):
.endm
.macro FUNC_END name
SIZE (\name)
.endm
/* Emulate FF1 ("fast find 1") instruction on ck801.
Result goes in rx, clobbering ry. */
#if defined(__CK801__)
.macro FF1_M rx, ry
movi \rx, 32
10:
cmphsi \ry, 1
bf 11f
subi \rx, \rx, 1
lsri \ry, \ry, 1
br 10b
11:
.endm
#else
.macro FF1_M rx, ry
ff1 \rx, \ry
.endm
#endif
/* Likewise emulate lslc instruction ("logical left shift to C") on CK801. */
#if defined(__CK801__)
.macro LSLC_M rx
cmpne \rx, \rx
addc \rx, \rx
.endm
#else
.macro LSLC_M rx
lslc \rx
.endm
#endif
/* Emulate the abs instruction. */
#if defined(__CK802__)
.macro ABS_M rx
btsti \rx, 31
bf 10f
not \rx
addi \rx, 1
10:
.endm
#elif defined(__CK801__)
.macro ABS_M rx
cmplti \rx, 1
bf 10f
not \rx
addi \rx, 1
10:
.endm
#else
.macro ABS_M rx
abs \rx
.endm
#endif
/* Emulate the ld.hs ("load signed halfword and extend") instruction
on ck801 and ck802. */
#if defined(__CK801__)
.macro LDBS_M rx, ry
ld.b \rx, (\ry, 0x0)
sextb \rx, \rx
.endm
#else
.macro LDBS_M rx, ry
ld.bs \rx, (\ry, 0x0)
.endm
#endif
#if defined(__CK801__)
.macro LDHS_M rx, ry
ld.h \rx, (\ry, 0x0)
sexth \rx, \rx
.endm
#else
.macro LDHS_M rx, ry
ld.hs \rx, (\ry, 0x0)
.endm
#endif
/* Signed and unsigned div/mod/rem functions. */
#ifdef L_udivsi3
FUNC_START udiv32
FUNC_START udivsi3
cmpnei a1, 0 // look for 0 divisor
bt 9f
trap 3 // divide by 0
9:
// control iterations, skip across high order 0 bits in dividend
cmpnei a0, 0
bt 8f
jmp lr // 0 dividend quick return
8:
push l0
movi a2, 1 // a2 is quotient (1 for a sentinel)
mov a3, a0
FF1_M l0, a3 // figure distance to skip
lsl a2, l0 // move the sentinel along (with 0's behind)
lsl a0, l0 // and the low 32 bits of numerator
// FIXME: Is this correct?
mov a3, a1 // looking at divisor
FF1_M l0, a3 // I can move 32-l0 more bits to left.
addi l0, 1 // ok, one short of that...
mov a3, a0
lsr a3, l0 // bits that came from low order...
not l0 // l0 == "32-n" == LEFT distance
addi l0, 33 // this is (32-n)
lsl a2,l0 // fixes the high 32 (quotient)
lsl a0,l0
cmpnei a2,0
bf 4f // the sentinel went away...
// run the remaining bits
1:
LSLC_M a0 // 1 bit left shift of a3-a0
addc a3, a3
cmphs a3, a1 // upper 32 of dividend >= divisor?
bf 2f
subu a3, a1 // if yes, subtract divisor
2:
addc a2, a2 // shift by 1 and count subtracts
bf 1b // if sentinel falls out of quotient, stop
4:
mov a0, a2 // return quotient
mov a1, a3 // and piggyback the remainder
pop l0
FUNC_END udiv32
FUNC_END udivsi3
#endif
#ifdef L_umodsi3
FUNC_START urem32
FUNC_START umodsi3
cmpnei a1, 0 // look for 0 divisor
bt 9f
trap 3 // divide by 0
9:
// control iterations, skip across high order 0 bits in dividend
cmpnei a0, 0
bt 8f
jmp lr // 0 dividend quick return
8:
mov a2, a0
FF1_M a3, a2 // figure distance to skip
movi a2, 1 // a2 is quotient (1 for a sentinel)
lsl a2, a3 // move the sentinel along (with 0's behind)
lsl a0, a3 // and the low 32 bits of numerator
movi a3, 0
1:
LSLC_M a0 // 1 bit left shift of a3-a0
addc a3, a3
cmphs a3, a1 // upper 32 of dividend >= divisor?
bf 2f
subu a3, a1 // if yes, subtract divisor
2:
addc a2, a2 // shift by 1 and count subtracts
bf 1b // if sentinel falls out of quotient, stop
4:
mov a0, a3 // and piggyback the remainder
jmp lr
FUNC_END urem32
FUNC_END umodsi3
#endif
#ifdef L_divsi3
FUNC_START div32
FUNC_START divsi3
cmpnei a1, 0 // look for 0 divisor
bt 9f
trap 3 // divide by 0
9:
// control iterations, skip across high order 0 bits in dividend
cmpnei a0, 0
bt 8f
jmp lr // 0 dividend quick return
8:
push l0, l1
mov l1, a0
xor l1, a1 // calc sign of quotient
ABS_M a0
ABS_M a1
movi a2, 1 // a2 is quotient (1 for a sentinel)
mov a3, a0
FF1_M l0, a3 // figure distance to skip
lsl a2, l0 // move the sentinel along (with 0's behind)
lsl a0, l0 // and the low 32 bits of numerator
// FIXME: is this correct?
mov a3, a1 // looking at divisor
FF1_M l0, a3 // I can move 32-l0 more bits to left.
addi l0, 1 // ok, one short of that...
mov a3, a0
lsr a3, l0 // bits that came from low order...
not l0 // l0 == "32-n" == LEFT distance
addi l0, 33 // this is (32-n)
lsl a2,l0 // fixes the high 32 (quotient)
lsl a0,l0
cmpnei a2,0
bf 4f // the sentinel went away...
// run the remaining bits
1:
LSLC_M a0 // 1 bit left shift of a3-a0
addc a3, a3
cmphs a3, a1 // upper 32 of dividend >= divisor?
bf 2f
subu a3, a1 // if yes, subtract divisor
2:
addc a2, a2 // shift by 1 and count subtracts
bf 1b // if sentinel falls out of quotient, stop
4:
mov a0, a2 // return quotient
mov a1, a3 // and piggyback the remainder
LSLC_M l1 // after adjusting for sign
bf 3f
not a0
addi a0, 1
not a1
addi a1, 1
3:
pop l0, l1
FUNC_END div32
FUNC_END divsi3
#endif
#ifdef L_modsi3
FUNC_START rem32
FUNC_START modsi3
push l0
cmpnei a1, 0 // look for 0 divisor
bt 9f
trap 3 // divide by 0
9:
// control iterations, skip across high order 0 bits in dividend
cmpnei a0, 0
bt 8f
pop l0 // 0 dividend quick return
8:
mov l0, a0
ABS_M a0
ABS_M a1
mov a2, a0
FF1_M a3, a2 // figure distance to skip
movi a2, 1 // a2 is quotient (1 for a sentinel)
lsl a2, a3 // move the sentinel along (with 0's behind)
lsl a0, a3 // and the low 32 bits of numerator
movi a3, 0
// run the remaining bits
1:
LSLC_M a0 // 1 bit left shift of a3-a0
addc a3, a3
cmphs a3, a1 // upper 32 of dividend >= divisor?
bf 2f
subu a3, a1 // if yes, subtract divisor
2:
addc a2, a2 // shift by 1 and count subtracts
bf 1b // if sentinel falls out of quotient, stop
4:
mov a0, a3 // and piggyback the remainder
LSLC_M l0 // after adjusting for sign
bf 3f
not a0
addi a0, 1
3:
pop l0
FUNC_END rem32
FUNC_END modsi3
#endif
/* Unordered comparisons for single and double float. */
#ifdef L_unordsf2
FUNC_START unordsf2
#if defined(__CK801__)
subi sp, 4
st.w r4, (sp, 0x0)
lsli r2, r0, 1
lsli r3, r1, 1
asri r4, r2, 24
not r4
cmpnei r4, 0
bt 1f
lsli r4, r0, 9
cmpnei r4, 0
bt 3f
1:
asri r4, r3, 24
not r4
cmpnei r4, 0
bt 2f
lsli r4, r1, 9
cmpnei r4, 0
bt 3f
2:
ld.w r4, (sp, 0x0)
addi sp, 4
movi r0, 0
rts
3:
ld.w r4, (sp, 0x0)
addi sp, 4
movi r0, 1
rts
#elif defined(__CK802__)
lsli r2, r0, 1
lsli r3, r1, 1
asri r2, r2, 24
not r13, r2
cmpnei r13, 0
bt 1f
lsli r13, r0, 9
cmpnei r13, 0
bt 3f
1:
asri r3, r3, 24
not r13, r3
cmpnei r13, 0
bt 2f
lsli r13, r1, 9
cmpnei r13, 0
bt 3f
2:
movi r0, 0
rts
3:
movi r0, 1
rts
#else
lsli r2, r0, 1
lsli r3, r1, 1
asri r2, r2, 24
not r13, r2
bnez r13, 1f
lsli r13, r0, 9
bnez r13, 3f
1:
asri r3, r3, 24
not r13, r3
bnez r13, 2f
lsli r13, r1, 9
bnez r13, 3f
2:
movi r0, 0
rts
3:
movi r0, 1
rts
#endif
FUNC_END unordsf2
#endif
#ifdef L_unorddf2
FUNC_START unorddf2
#if defined(__CK801__)
subi sp, 8
st.w r4, (sp, 0x0)
st.w r5, (sp, 0x4)
lsli r4, xh, 1
asri r4, r4, 21
not r4
cmpnei r4, 0
bt 1f
mov r4, xl
lsli r5, xh, 12
or r4, r5
cmpnei r4, 0
bt 3f
1:
lsli r4, yh, 1
asri r4, r4, 21
not r4
cmpnei r4, 0
bt 2f
mov r4,yl
lsli r5, yh, 12
or r4, r5
cmpnei r4, 0
bt 3f
2:
ld.w r4, (sp, 0x0)
ld.w r5, (sp, 0x4)
addi sp, 8
movi r0, 0
rts
3:
ld.w r4, (sp, 0x0)
ld.w r5, (sp, 0x4)
addi sp, 8
movi r0, 1
rts
#elif defined(__CK802__)
lsli r13, xh, 1
asri r13, r13, 21
not r13
cmpnei r13, 0
bt 1f
lsli xh, xh, 12
or r13, xl, xh
cmpnei r13, 0
bt 3f
1:
lsli r13, yh, 1
asri r13, r13, 21
not r13
cmpnei r13, 0
bt 2f
lsli yh, yh, 12
or r13, yl, yh
cmpnei r13, 0
bt 3f
2:
movi r0, 0
rts
3:
movi r0, 1
rts
#else
lsli r13, xh, 1
asri r13, r13, 21
not r13
bnez r13, 1f
lsli xh, xh, 12
or r13, xl, xh
bnez r13, 3f
1:
lsli r13, yh, 1
asri r13, r13, 21
not r13
bnez r13, 2f
lsli yh, yh, 12
or r13, yl, yh
bnez r13, 3f
2:
movi r0, 0
rts
3:
movi r0, 1
rts
#endif
FUNC_END unorddf2
#endif
/* When optimizing for size on ck801 and ck802, GCC emits calls to the
following helper functions when expanding casesi, instead of emitting
the table lookup and jump inline. Note that in these functions the
jump is handled by tweaking the value of lr before rts. */
#ifdef L_csky_case_sqi
FUNC_START _gnu_csky_case_sqi
subi sp, 4
st.w a1, (sp, 0x0)
mov a1, lr
add a1, a1, a0
LDBS_M a1, a1
lsli a1, a1, 1
add lr, lr, a1
ld.w a1, (sp, 0x0)
addi sp, 4
rts
FUNC_END _gnu_csky_case_sqi
#endif
#ifdef L_csky_case_uqi
FUNC_START _gnu_csky_case_uqi
subi sp, 4
st.w a1, (sp, 0x0)
mov a1, lr
add a1, a1, a0
ld.b a1, (a1, 0x0)
lsli a1, a1, 1
add lr, lr, a1
ld.w a1, (sp, 0x0)
addi sp, 4
rts
FUNC_END _gnu_csky_case_uqi
#endif
#ifdef L_csky_case_shi
FUNC_START _gnu_csky_case_shi
subi sp, 8
st.w a0, (sp, 0x4)
st.w a1, (sp, 0x0)
mov a1, lr
lsli a0, a0, 1
add a1, a1, a0
LDHS_M a1, a1
lsli a1, a1, 1
add lr, lr, a1
ld.w a0, (sp, 0x4)
ld.w a1, (sp, 0x0)
addi sp, 8
rts
FUNC_END _gnu_csky_case_shi
#endif
#ifdef L_csky_case_uhi
FUNC_START _gnu_csky_case_uhi
subi sp, 8
st.w a0, (sp, 0x4)
st.w a1, (sp, 0x0)
mov a1, lr
lsli a0, a0, 1
add a1, a1, a0
ld.h a1, (a1, 0x0)
lsli a1, a1, 1
add lr, lr, a1
ld.w a0, (sp, 0x4)
ld.w a1, (sp, 0x0)
addi sp, 8
rts
FUNC_END _gnu_csky_case_uhi
#endif
#ifdef L_csky_case_si
FUNC_START _gnu_csky_case_si
subi sp, 8
st.w a0, (sp, 0x4)
st.w a1, (sp, 0x0)
mov a1, lr
addi a1, a1, 2 // Align to word.
bclri a1, a1, 1
mov lr, a1
lsli a0, a0, 2
add a1, a1, a0
ld.w a0, (a1, 0x0)
add lr, lr, a0
ld.w a0, (sp, 0x4)
ld.w a1, (sp, 0x0)
addi sp, 8
rts
FUNC_END _gnu_csky_case_si
#endif
/* GCC expects that {__eq,__ne,__gt,__ge,__le,__lt}{df2,sf2}
will behave as __cmpdf2. So, we stub the implementations to
jump on to __cmpdf2 and __cmpsf2.
All of these short-circuit the return path so that __cmp{sd}f2
will go directly back to the caller. */
.macro COMPARE_DF_JUMP name
.import SYM (cmpdf2)
FUNC_START \name
jmpi SYM (cmpdf2)
FUNC_END \name
.endm
#ifdef L_eqdf2
COMPARE_DF_JUMP eqdf2
#endif /* L_eqdf2 */
#ifdef L_nedf2
COMPARE_DF_JUMP nedf2
#endif /* L_nedf2 */
#ifdef L_gtdf2
COMPARE_DF_JUMP gtdf2
#endif /* L_gtdf2 */
#ifdef L_gedf2
COMPARE_DF_JUMP gedf2
#endif /* L_gedf2 */
#ifdef L_ltdf2
COMPARE_DF_JUMP ltdf2
#endif /* L_ltdf2 */
#ifdef L_ledf2
COMPARE_DF_JUMP ledf2
#endif /* L_ledf2 */
/* Single-precision floating point stubs. */
.macro COMPARE_SF_JUMP name
.import SYM (cmpsf2)
FUNC_START \name
jmpi SYM (cmpsf2)
FUNC_END \name
.endm
#ifdef L_eqsf2
COMPARE_SF_JUMP eqsf2
#endif /* L_eqsf2 */
#ifdef L_nesf2
COMPARE_SF_JUMP nesf2
#endif /* L_nesf2 */
#ifdef L_gtsf2
COMPARE_SF_JUMP gtsf2
#endif /* L_gtsf2 */
#ifdef L_gesf2
COMPARE_SF_JUMP __gesf2
#endif /* L_gesf2 */
#ifdef L_ltsf2
COMPARE_SF_JUMP __ltsf2
#endif /* L_ltsf2 */
#ifdef L_lesf2
COMPARE_SF_JUMP lesf2
#endif /* L_lesf2 */
|
4ms/metamodule-plugin-sdk
| 1,264
|
plugin-libc/libgcc/config/visium/crtn.S
|
/* crtn.S for Visium.
Copyright (C) 2005-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.file "crtn.o"
.ident "GNU C crtn.o"
.section .init
move.l r23,r22
read.l r22,(r22)
read.l r21,1(r23)
bra tr,r21,r0
addi r23,8
.section .fini
move.l r23,r22
read.l r22,(r22)
read.l r21,1(r23)
bra tr,r21,r0
addi r23,8
|
4ms/metamodule-plugin-sdk
| 1,346
|
plugin-libc/libgcc/config/visium/crti.S
|
/* crti.S for Visium.
Copyright (C) 2005-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.file "crti.o"
.ident "GNU C crti.o"
.section .init
.globl __init
.type __init,@function
__init:
subi r23,8
nop
write.l (r23),r22
write.l 1(r23),r21
move.l r22,r23
.section .fini
.globl __fini
.type __fini,@function
__fini:
subi r23,8
nop
write.l (r23),r22
write.l 1(r23),r21
move.l r22,r23
|
4ms/metamodule-plugin-sdk
| 2,552
|
plugin-libc/libgcc/config/rs6000/eabi-cn.S
|
/* crtn.s for eabi
Copyright (C) 1996-2022 Free Software Foundation, Inc.
Written By Michael Meissner
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This file just supplies labeled ending points for the .got* and other
special sections. It is linked in last after other modules. */
.ident "GNU C crtn.s"
#ifndef __powerpc64__
.section ".got","aw"
.globl __GOT_END__
.type __GOT_END__,@object
__GOT_END__:
.section ".got1","aw"
.globl __GOT1_END__
.type __GOT1_END__,@object
__GOT1_END__:
.section ".got2","aw"
.globl __GOT2_END__
.type __GOT2_END__,@object
__GOT2_END__:
.section ".fixup","aw"
.globl __FIXUP_END__
.type __FIXUP_END__,@object
__FIXUP_END__:
.section ".ctors","aw"
.globl __CTOR_END__
.type __CTOR_END__,@object
__CTOR_END__:
.section ".dtors","aw"
.weak __DTOR_END__
.type __DTOR_END__,@object
__DTOR_END__:
.section ".sdata","aw"
.globl __SDATA_END__
.type __SDATA_END__,@object
__SDATA_END__:
.section ".sbss","aw",@nobits
.globl __SBSS_END__
.type __SBSS_END__,@object
__SBSS_END__:
.section ".sdata2","a"
.globl __SDATA2_END__
.type __SDATA2_END__,@object
__SDATA2_END__:
.section ".sbss2","a"
.globl __SBSS2_END__
.type __SBSS2_END__,@object
__SBSS2_END__:
.section ".gcc_except_table","aw"
.globl __EXCEPT_END__
.type __EXCEPT_END__,@object
__EXCEPT_END__:
.section ".eh_frame","aw"
.globl __EH_FRAME_END__
.type __EH_FRAME_END__,@object
__EH_FRAME_END__:
.long 0
/* Tail of __init function used for static constructors. */
.section ".init","ax"
lwz 0,20(1)
mtlr 0
addi 1,1,16
blr
/* Tail of __fini function used for static destructors. */
.section ".fini","ax"
lwz 0,20(1)
mtlr 0
addi 1,1,16
blr
#endif
|
4ms/metamodule-plugin-sdk
| 2,540
|
plugin-libc/libgcc/config/rs6000/e500crtresx64gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* "Exit" versions that return to their caller's caller. */
HIDDEN_FUNC(_rest64gpr_14_x) evldd 14,0(11)
HIDDEN_FUNC(_rest64gpr_15_x) evldd 15,8(11)
HIDDEN_FUNC(_rest64gpr_16_x) evldd 16,16(11)
HIDDEN_FUNC(_rest64gpr_17_x) evldd 17,24(11)
HIDDEN_FUNC(_rest64gpr_18_x) evldd 18,32(11)
HIDDEN_FUNC(_rest64gpr_19_x) evldd 19,40(11)
HIDDEN_FUNC(_rest64gpr_20_x) evldd 20,48(11)
HIDDEN_FUNC(_rest64gpr_21_x) evldd 21,56(11)
HIDDEN_FUNC(_rest64gpr_22_x) evldd 22,64(11)
HIDDEN_FUNC(_rest64gpr_23_x) evldd 23,72(11)
HIDDEN_FUNC(_rest64gpr_24_x) evldd 24,80(11)
HIDDEN_FUNC(_rest64gpr_25_x) evldd 25,88(11)
HIDDEN_FUNC(_rest64gpr_26_x) evldd 26,96(11)
HIDDEN_FUNC(_rest64gpr_27_x) evldd 27,104(11)
HIDDEN_FUNC(_rest64gpr_28_x) evldd 28,112(11)
HIDDEN_FUNC(_rest64gpr_29_x) evldd 29,120(11)
HIDDEN_FUNC(_rest64gpr_30_x) evldd 30,128(11)
HIDDEN_FUNC(_rest64gpr_31_x) lwz 0,148(11)
evldd 31,136(11)
addi 1,11,144
mtlr 0
blr
FUNC_END(_rest64gpr_31_x)
FUNC_END(_rest64gpr_30_x)
FUNC_END(_rest64gpr_29_x)
FUNC_END(_rest64gpr_28_x)
FUNC_END(_rest64gpr_27_x)
FUNC_END(_rest64gpr_26_x)
FUNC_END(_rest64gpr_25_x)
FUNC_END(_rest64gpr_24_x)
FUNC_END(_rest64gpr_23_x)
FUNC_END(_rest64gpr_22_x)
FUNC_END(_rest64gpr_21_x)
FUNC_END(_rest64gpr_20_x)
FUNC_END(_rest64gpr_19_x)
FUNC_END(_rest64gpr_18_x)
FUNC_END(_rest64gpr_17_x)
FUNC_END(_rest64gpr_16_x)
FUNC_END(_rest64gpr_15_x)
FUNC_END(_rest64gpr_14_x)
#endif
|
4ms/metamodule-plugin-sdk
| 6,145
|
plugin-libc/libgcc/config/rs6000/darwin-world.S
|
/* This file contains the exception-handling save_world and
* restore_world routines, which need to do a run-time check to see if
* they should save and restore the vector registers.
*
* Copyright (C) 2004-2022 Free Software Foundation, Inc.
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
#ifndef __ppc64__
.machine ppc7400
.data
.align 2
#ifdef __DYNAMIC__
.non_lazy_symbol_pointer
L_has_vec$non_lazy_ptr:
.indirect_symbol __cpu_has_altivec
.long 0
#else
/* For static, "pretend" we have a non-lazy-pointer. */
L_has_vec$non_lazy_ptr:
.long __cpu_has_altivec
#endif
.text
.align 2
/* save_world and rest_world save/restore F14-F31 and possibly V20-V31
(assuming you have a CPU with vector registers; we use a global var
provided by the System Framework to determine this.)
SAVE_WORLD takes R0 (the caller`s caller`s return address) and R11
(the stack frame size) as parameters. It returns the updated VRsave
in R0 if we`re on a CPU with vector regs.
For gcc3 onward, we need to save and restore CR as well, since scheduled
prologs can cause comparisons to be moved before calls to save_world.
USES: R0 R11 R12 */
.private_extern save_world
save_world:
stw r0,8(r1)
mflr r0
bcl 20,31,Ls$pb
Ls$pb: mflr r12
addis r12,r12,ha16(L_has_vec$non_lazy_ptr-Ls$pb)
lwz r12,lo16(L_has_vec$non_lazy_ptr-Ls$pb)(r12)
mtlr r0
lwz r12,0(r12)
/* grab CR */
mfcr r0
/* test HAS_VEC */
cmpwi r12,0
stfd f14,-144(r1)
stfd f15,-136(r1)
stfd f16,-128(r1)
stfd f17,-120(r1)
stfd f18,-112(r1)
stfd f19,-104(r1)
stfd f20,-96(r1)
stfd f21,-88(r1)
stfd f22,-80(r1)
stfd f23,-72(r1)
stfd f24,-64(r1)
stfd f25,-56(r1)
stfd f26,-48(r1)
stfd f27,-40(r1)
stfd f28,-32(r1)
stfd f29,-24(r1)
stfd f30,-16(r1)
stfd f31,-8(r1)
stmw r13,-220(r1)
/* stash CR */
stw r0,4(r1)
/* set R12 pointing at Vector Reg save area */
addi r12,r1,-224
/* allocate stack frame */
stwux r1,r1,r11
/* ...but return if HAS_VEC is zero */
bne+ L$saveVMX
/* Not forgetting to restore CR. */
mtcr r0
blr
L$saveVMX:
/* We're saving Vector regs too. */
/* Restore CR from R0. No More Branches! */
mtcr r0
/* We should really use VRSAVE to figure out which vector regs
we actually need to save and restore. Some other time :-/ */
li r11,-192
stvx v20,r11,r12
li r11,-176
stvx v21,r11,r12
li r11,-160
stvx v22,r11,r12
li r11,-144
stvx v23,r11,r12
li r11,-128
stvx v24,r11,r12
li r11,-112
stvx v25,r11,r12
li r11,-96
stvx v26,r11,r12
li r11,-80
stvx v27,r11,r12
li r11,-64
stvx v28,r11,r12
li r11,-48
stvx v29,r11,r12
li r11,-32
stvx v30,r11,r12
mfspr r0,VRsave
li r11,-16
stvx v31,r11,r12
stw r0,0(r12) /* VRsave lives at -224(R1). */
ori r0,r0,0xfff /* We just saved these. */
mtspr VRsave,r0
blr
/* rest_world is jumped to, not called, so no need to worry about LR.
clobbers R0, R7, R11 and R12. This just undoes the work done above. */
.private_extern rest_world
rest_world:
lwz r11, 0(r1) /* Pickup previous SP */
li r7, 0 /* Stack offset is zero, r10 is ignored. */
b Lrest_world_eh_r7
/* eh_rest_world_r10 is jumped to, not called, so no need to worry about LR.
R10 is the C++ EH stack adjust parameter, we return to the caller`s caller.
clobbers: R0, R7, R11 and R12
uses : R10
RETURNS : C++ EH Data registers (R3 - R6). */
.private_extern eh_rest_world_r10
eh_rest_world_r10:
lwz r11, 0(r1) /* Pickup previous SP */
mr r7,r10 /* Stack offset. */
/* pickup the C++ EH data regs (R3 - R6.) */
lwz r6,-420(r11)
lwz r5,-424(r11)
lwz r4,-428(r11)
lwz r3,-432(r11)
/* Fall through to Lrest_world_eh_r7. */
/* When we are doing the exception-handling epilog, R7 contains the offset to
add to the SP.
clobbers: R0, R11 and R12
uses : R7. */
Lrest_world_eh_r7:
/* See if we have Altivec. */
bcl 20,31,Lr7$pb
Lr7$pb: mflr r12
addis r12,r12,ha16(L_has_vec$non_lazy_ptr-Lr7$pb)
lwz r12,lo16(L_has_vec$non_lazy_ptr-Lr7$pb)(r12)
lwz r12,0(r12) /* R12 := HAS_VEC */
cmpwi r12,0
lmw r13,-220(r11)
beq L.rest_world_fp_eh
/* We have Altivec, restore VRsave and V20..V31 */
lwz r0,-224(r11)
li r12,-416
mtspr VRsave,r0
lvx v20,r11,r12
li r12,-400
lvx v21,r11,r12
li r12,-384
lvx v22,r11,r12
li r12,-368
lvx v23,r11,r12
li r12,-352
lvx v24,r11,r12
li r12,-336
lvx v25,r11,r12
li r12,-320
lvx v26,r11,r12
li r12,-304
lvx v27,r11,r12
li r12,-288
lvx v28,r11,r12
li r12,-272
lvx v29,r11,r12
li r12,-256
lvx v30,r11,r12
li r12,-240
lvx v31,r11,r12
L.rest_world_fp_eh:
lwz r0,4(r11) /* recover saved CR */
lfd f14,-144(r11)
lfd f15,-136(r11)
lfd f16,-128(r11)
lfd f17,-120(r11)
lfd f18,-112(r11)
lfd f19,-104(r11)
lfd f20,-96(r11)
lfd f21,-88(r11)
lfd f22,-80(r11)
lfd f23,-72(r11)
lfd f24,-64(r11)
lfd f25,-56(r11)
lfd f26,-48(r11)
lfd f27,-40(r11)
lfd f28,-32(r11)
lfd f29,-24(r11)
lfd f30,-16(r11)
mtcr r0 /* restore the saved cr. */
lwz r0, 8(r11) /* Pick up the 'real' return address. */
lfd f31,-8(r11)
mtctr r0 /* exception-handler ret. address */
add r1,r11,r7 /* set SP to original value + R7 offset */
bctr
#endif
/* we should never be called on ppc64 for this ... */
/* Done. */
|
4ms/metamodule-plugin-sdk
| 2,750
|
plugin-libc/libgcc/config/rs6000/crtresfpr.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
* 64-bit support written by David Edelsohn
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.machine ppc
.section ".text"
#include "ppc-asm.h"
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
/* Routines for restoring floating point registers, called by the compiler. */
/* Called with r11 pointing to the stack header word of the caller of the */
/* function, just beyond the end of the floating point save area. */
CFI_STARTPROC
HIDDEN_FUNC(_restfpr_14) lfd 14,-144(11) /* restore fp registers */
HIDDEN_FUNC(_restfpr_15) lfd 15,-136(11)
HIDDEN_FUNC(_restfpr_16) lfd 16,-128(11)
HIDDEN_FUNC(_restfpr_17) lfd 17,-120(11)
HIDDEN_FUNC(_restfpr_18) lfd 18,-112(11)
HIDDEN_FUNC(_restfpr_19) lfd 19,-104(11)
HIDDEN_FUNC(_restfpr_20) lfd 20,-96(11)
HIDDEN_FUNC(_restfpr_21) lfd 21,-88(11)
HIDDEN_FUNC(_restfpr_22) lfd 22,-80(11)
HIDDEN_FUNC(_restfpr_23) lfd 23,-72(11)
HIDDEN_FUNC(_restfpr_24) lfd 24,-64(11)
HIDDEN_FUNC(_restfpr_25) lfd 25,-56(11)
HIDDEN_FUNC(_restfpr_26) lfd 26,-48(11)
HIDDEN_FUNC(_restfpr_27) lfd 27,-40(11)
HIDDEN_FUNC(_restfpr_28) lfd 28,-32(11)
HIDDEN_FUNC(_restfpr_29) lfd 29,-24(11)
HIDDEN_FUNC(_restfpr_30) lfd 30,-16(11)
HIDDEN_FUNC(_restfpr_31) lfd 31,-8(11)
blr
FUNC_END(_restfpr_31)
FUNC_END(_restfpr_30)
FUNC_END(_restfpr_29)
FUNC_END(_restfpr_28)
FUNC_END(_restfpr_27)
FUNC_END(_restfpr_26)
FUNC_END(_restfpr_25)
FUNC_END(_restfpr_24)
FUNC_END(_restfpr_23)
FUNC_END(_restfpr_22)
FUNC_END(_restfpr_21)
FUNC_END(_restfpr_20)
FUNC_END(_restfpr_19)
FUNC_END(_restfpr_18)
FUNC_END(_restfpr_17)
FUNC_END(_restfpr_16)
FUNC_END(_restfpr_15)
FUNC_END(_restfpr_14)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,253
|
plugin-libc/libgcc/config/rs6000/crtrestvr.S
|
/* Routines for restoring vector registers.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Written by Alan Modra, IBM
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
#undef __ALTIVEC__
#define __ALTIVEC__ 1
#include "ppc-asm.h"
/* Called with r0 pointing just beyond the end of the vector save area. */
.machine altivec
.section ".text"
CFI_STARTPROC
HIDDEN_FUNC(_restvr_20)
li r11,-192
lvx v20,r11,r0
HIDDEN_FUNC(_restvr_21)
li r11,-176
lvx v21,r11,r0
HIDDEN_FUNC(_restvr_22)
li r11,-160
lvx v22,r11,r0
HIDDEN_FUNC(_restvr_23)
li r11,-144
lvx v23,r11,r0
HIDDEN_FUNC(_restvr_24)
li r11,-128
lvx v24,r11,r0
HIDDEN_FUNC(_restvr_25)
li r11,-112
lvx v25,r11,r0
HIDDEN_FUNC(_restvr_26)
li r11,-96
lvx v26,r11,r0
HIDDEN_FUNC(_restvr_27)
li r11,-80
lvx v27,r11,r0
HIDDEN_FUNC(_restvr_28)
li r11,-64
lvx v28,r11,r0
HIDDEN_FUNC(_restvr_29)
li r11,-48
lvx v29,r11,r0
HIDDEN_FUNC(_restvr_30)
li r11,-32
lvx v30,r11,r0
HIDDEN_FUNC(_restvr_31)
li r11,-16
lvx v31,r11,r0
blr
FUNC_END(_restvr_31)
FUNC_END(_restvr_30)
FUNC_END(_restvr_29)
FUNC_END(_restvr_28)
FUNC_END(_restvr_27)
FUNC_END(_restvr_26)
FUNC_END(_restvr_25)
FUNC_END(_restvr_24)
FUNC_END(_restvr_23)
FUNC_END(_restvr_22)
FUNC_END(_restvr_21)
FUNC_END(_restvr_20)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,455
|
plugin-libc/libgcc/config/rs6000/e500crtsav64gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for saving 64-bit integer registers, called by the compiler. */
HIDDEN_FUNC(_save64gpr_14) evstdd 14,0(11)
HIDDEN_FUNC(_save64gpr_15) evstdd 15,8(11)
HIDDEN_FUNC(_save64gpr_16) evstdd 16,16(11)
HIDDEN_FUNC(_save64gpr_17) evstdd 17,24(11)
HIDDEN_FUNC(_save64gpr_18) evstdd 18,32(11)
HIDDEN_FUNC(_save64gpr_19) evstdd 19,40(11)
HIDDEN_FUNC(_save64gpr_20) evstdd 20,48(11)
HIDDEN_FUNC(_save64gpr_21) evstdd 21,56(11)
HIDDEN_FUNC(_save64gpr_22) evstdd 22,64(11)
HIDDEN_FUNC(_save64gpr_23) evstdd 23,72(11)
HIDDEN_FUNC(_save64gpr_24) evstdd 24,80(11)
HIDDEN_FUNC(_save64gpr_25) evstdd 25,88(11)
HIDDEN_FUNC(_save64gpr_26) evstdd 26,96(11)
HIDDEN_FUNC(_save64gpr_27) evstdd 27,104(11)
HIDDEN_FUNC(_save64gpr_28) evstdd 28,112(11)
HIDDEN_FUNC(_save64gpr_29) evstdd 29,120(11)
HIDDEN_FUNC(_save64gpr_30) evstdd 30,128(11)
HIDDEN_FUNC(_save64gpr_31) evstdd 31,136(11)
blr
FUNC_END(_save64gpr_31)
FUNC_END(_save64gpr_30)
FUNC_END(_save64gpr_29)
FUNC_END(_save64gpr_28)
FUNC_END(_save64gpr_27)
FUNC_END(_save64gpr_26)
FUNC_END(_save64gpr_25)
FUNC_END(_save64gpr_24)
FUNC_END(_save64gpr_23)
FUNC_END(_save64gpr_22)
FUNC_END(_save64gpr_21)
FUNC_END(_save64gpr_20)
FUNC_END(_save64gpr_19)
FUNC_END(_save64gpr_18)
FUNC_END(_save64gpr_17)
FUNC_END(_save64gpr_16)
FUNC_END(_save64gpr_15)
FUNC_END(_save64gpr_14)
#endif
|
4ms/metamodule-plugin-sdk
| 2,585
|
plugin-libc/libgcc/config/rs6000/e500crtresx32gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for restoring 32-bit integer registers, called by the compiler. */
/* "Exit" versions that return to the caller's caller. */
HIDDEN_FUNC(_rest32gpr_14_x) lwz 14,-72(11)
HIDDEN_FUNC(_rest32gpr_15_x) lwz 15,-68(11)
HIDDEN_FUNC(_rest32gpr_16_x) lwz 16,-64(11)
HIDDEN_FUNC(_rest32gpr_17_x) lwz 17,-60(11)
HIDDEN_FUNC(_rest32gpr_18_x) lwz 18,-56(11)
HIDDEN_FUNC(_rest32gpr_19_x) lwz 19,-52(11)
HIDDEN_FUNC(_rest32gpr_20_x) lwz 20,-48(11)
HIDDEN_FUNC(_rest32gpr_21_x) lwz 21,-44(11)
HIDDEN_FUNC(_rest32gpr_22_x) lwz 22,-40(11)
HIDDEN_FUNC(_rest32gpr_23_x) lwz 23,-36(11)
HIDDEN_FUNC(_rest32gpr_24_x) lwz 24,-32(11)
HIDDEN_FUNC(_rest32gpr_25_x) lwz 25,-28(11)
HIDDEN_FUNC(_rest32gpr_26_x) lwz 26,-24(11)
HIDDEN_FUNC(_rest32gpr_27_x) lwz 27,-20(11)
HIDDEN_FUNC(_rest32gpr_28_x) lwz 28,-16(11)
HIDDEN_FUNC(_rest32gpr_29_x) lwz 29,-12(11)
HIDDEN_FUNC(_rest32gpr_30_x) lwz 30,-8(11)
HIDDEN_FUNC(_rest32gpr_31_x) lwz 0,4(11)
lwz 31,-4(11)
mr 1,11
mtlr 0
blr
FUNC_END(_rest32gpr_31_x)
FUNC_END(_rest32gpr_30_x)
FUNC_END(_rest32gpr_29_x)
FUNC_END(_rest32gpr_28_x)
FUNC_END(_rest32gpr_27_x)
FUNC_END(_rest32gpr_26_x)
FUNC_END(_rest32gpr_25_x)
FUNC_END(_rest32gpr_24_x)
FUNC_END(_rest32gpr_23_x)
FUNC_END(_rest32gpr_22_x)
FUNC_END(_rest32gpr_21_x)
FUNC_END(_rest32gpr_20_x)
FUNC_END(_rest32gpr_19_x)
FUNC_END(_rest32gpr_18_x)
FUNC_END(_rest32gpr_17_x)
FUNC_END(_rest32gpr_16_x)
FUNC_END(_rest32gpr_15_x)
FUNC_END(_rest32gpr_14_x)
#endif
|
4ms/metamodule-plugin-sdk
| 2,517
|
plugin-libc/libgcc/config/rs6000/e500crtrest64gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* "Tail" versions that perform a tail call. */
HIDDEN_FUNC(_rest64gpr_14_t) evldd 14,0(11)
HIDDEN_FUNC(_rest64gpr_15_t) evldd 15,8(11)
HIDDEN_FUNC(_rest64gpr_16_t) evldd 16,16(11)
HIDDEN_FUNC(_rest64gpr_17_t) evldd 17,24(11)
HIDDEN_FUNC(_rest64gpr_18_t) evldd 18,32(11)
HIDDEN_FUNC(_rest64gpr_19_t) evldd 19,40(11)
HIDDEN_FUNC(_rest64gpr_20_t) evldd 20,48(11)
HIDDEN_FUNC(_rest64gpr_21_t) evldd 21,56(11)
HIDDEN_FUNC(_rest64gpr_22_t) evldd 22,64(11)
HIDDEN_FUNC(_rest64gpr_23_t) evldd 23,72(11)
HIDDEN_FUNC(_rest64gpr_24_t) evldd 24,80(11)
HIDDEN_FUNC(_rest64gpr_25_t) evldd 25,88(11)
HIDDEN_FUNC(_rest64gpr_26_t) evldd 26,96(11)
HIDDEN_FUNC(_rest64gpr_27_t) evldd 27,104(11)
HIDDEN_FUNC(_rest64gpr_28_t) evldd 28,112(11)
HIDDEN_FUNC(_rest64gpr_29_t) evldd 29,120(11)
HIDDEN_FUNC(_rest64gpr_30_t) evldd 30,128(11)
HIDDEN_FUNC(_rest64gpr_31_t) lwz 0,148(11)
evldd 31,136(11)
addi 1,11,144
blr
FUNC_END(_rest64gpr_31_t)
FUNC_END(_rest64gpr_30_t)
FUNC_END(_rest64gpr_29_t)
FUNC_END(_rest64gpr_28_t)
FUNC_END(_rest64gpr_27_t)
FUNC_END(_rest64gpr_26_t)
FUNC_END(_rest64gpr_25_t)
FUNC_END(_rest64gpr_24_t)
FUNC_END(_rest64gpr_23_t)
FUNC_END(_rest64gpr_22_t)
FUNC_END(_rest64gpr_21_t)
FUNC_END(_rest64gpr_20_t)
FUNC_END(_rest64gpr_19_t)
FUNC_END(_rest64gpr_18_t)
FUNC_END(_rest64gpr_17_t)
FUNC_END(_rest64gpr_16_t)
FUNC_END(_rest64gpr_15_t)
FUNC_END(_rest64gpr_14_t)
#endif
|
4ms/metamodule-plugin-sdk
| 11,760
|
plugin-libc/libgcc/config/rs6000/morestack.S
|
#ifdef __powerpc64__
# PowerPC64 support for -fsplit-stack.
# Copyright (C) 2009-2022 Free Software Foundation, Inc.
# Contributed by Alan Modra <amodra@gmail.com>.
# This file is part of GCC.
# GCC is free software; you can redistribute it and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation; either version 3, or (at your option) any later
# version.
# GCC is distributed in the hope that it will be useful, but WITHOUT ANY
# WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#include <auto-host.h>
#if _CALL_ELF == 2
.abiversion 2
#define PARAMS 32
#else
#define PARAMS 48
#endif
#define MORESTACK_FRAMESIZE (PARAMS+96)
#define R2_SAVE -MORESTACK_FRAMESIZE+PARAMS-8
#define PARAMREG_SAVE -MORESTACK_FRAMESIZE+PARAMS+0
#define STATIC_CHAIN_SAVE -MORESTACK_FRAMESIZE+PARAMS+64
#define R29_SAVE -MORESTACK_FRAMESIZE+PARAMS+72
#define LINKREG_SAVE -MORESTACK_FRAMESIZE+PARAMS+80
#define NEWSTACKSIZE_SAVE -MORESTACK_FRAMESIZE+PARAMS+88
# Excess space needed to call ld.so resolver for lazy plt
# resolution. Go uses sigaltstack so this doesn't need to
# also cover signal frame size.
#define BACKOFF 4096
# Large excess allocated when calling non-split-stack code.
#define NON_SPLIT_STACK 0x100000
#if _CALL_ELF == 2
#define BODY_LABEL(name) name
#define ENTRY0(name) \
.global name; \
.hidden name; \
.type name,@function; \
name##:
#ifdef __PCREL__
#define ENTRY(name) \
ENTRY0(name); \
.localentry name, 1
#define JUMP_TARGET(name) name##@notoc
#else
#define ENTRY(name) \
ENTRY0(name); \
0: addis %r2,%r12,.TOC.-0b@ha; \
addi %r2,%r2,.TOC.-0b@l; \
.localentry name, .-name
#endif
#else
#define BODY_LABEL(name) .L.##name
#define ENTRY0(name) \
.global name; \
.hidden name; \
.type name,@function; \
.pushsection ".opd","aw"; \
.p2align 3; \
name##: .quad BODY_LABEL (name), .TOC.@tocbase, 0; \
.popsection; \
BODY_LABEL(name)##:
#define ENTRY(name) ENTRY0(name)
#endif
#define SIZE(name) .size name, .-BODY_LABEL(name)
#ifndef JUMP_TARGET
#define JUMP_TARGET(name) name
#endif
.text
# Just like __morestack, but with larger excess allocation
ENTRY0(__morestack_non_split)
.LFB1:
.cfi_startproc
# We use a cleanup to restore the tcbhead_t.__private_ss if
# an exception is thrown through this code.
#ifdef __PIC__
.cfi_personality 0x9b,DW.ref.__gcc_personality_v0
.cfi_lsda 0x1b,.LLSDA1
#else
.cfi_personality 0x3,__gcc_personality_v0
.cfi_lsda 0x3,.LLSDA1
#endif
# LR is already saved by the split-stack prologue code.
# We may as well have the unwinder skip over the call in the
# prologue too.
.cfi_offset %lr,16
addis %r12,%r12,-NON_SPLIT_STACK@h
SIZE (__morestack_non_split)
# Fall through into __morestack
# This function is called with non-standard calling conventions.
# On entry, r12 is the requested stack pointer. One version of the
# split-stack prologue that calls __morestack looks like
# ld %r0,-0x7000-64(%r13)
# addis %r12,%r1,-allocate@ha
# addi %r12,%r12,-allocate@l
# cmpld %r12,%r0
# bge+ enough
# mflr %r0
# std %r0,16(%r1)
# bl __morestack
# ld %r0,16(%r1)
# mtlr %r0
# blr
# enough:
# The normal function prologue follows here, with a small addition at
# the end to set up the arg pointer. The arg pointer is set up with:
# addi %r12,%r1,offset
# bge %cr7,.+8
# mr %r12,%r29
#
# Note that the lr save slot 16(%r1) has already been used.
# r3 thru r11 possibly contain arguments and a static chain
# pointer for the function we're calling, so must be preserved.
# cr7 must also be preserved.
ENTRY0(__morestack)
#if _CALL_ELF == 2
# Functions with localentry bits of zero cannot make calls if those
# calls might change r2. This is true generally, and also true for
# __morestack with its special calling convention. When __morestack's
# caller is non-pcrel but libgcc is pcrel, the functions called here
# might modify r2. r2 must be preserved on exit, and also restored
# for the call back to our caller.
std %r2,R2_SAVE(%r1)
#endif
# Save parameter passing registers, our arguments, lr, r29
# and use r29 as a frame pointer.
std %r3,PARAMREG_SAVE+0(%r1)
sub %r3,%r1,%r12 # calculate requested stack size
mflr %r12
std %r4,PARAMREG_SAVE+8(%r1)
std %r5,PARAMREG_SAVE+16(%r1)
std %r6,PARAMREG_SAVE+24(%r1)
std %r7,PARAMREG_SAVE+32(%r1)
addi %r3,%r3,BACKOFF
std %r8,PARAMREG_SAVE+40(%r1)
std %r9,PARAMREG_SAVE+48(%r1)
std %r10,PARAMREG_SAVE+56(%r1)
std %r11,STATIC_CHAIN_SAVE(%r1)
std %r29,R29_SAVE(%r1)
std %r12,LINKREG_SAVE(%r1)
std %r3,NEWSTACKSIZE_SAVE(%r1) # new stack size
mr %r29,%r1
#if _CALL_ELF == 2
.cfi_offset %r2,R2_SAVE
#endif
.cfi_offset %r29,R29_SAVE
.cfi_def_cfa_register %r29
stdu %r1,-MORESTACK_FRAMESIZE(%r1)
#if _CALL_ELF == 2 && !defined __PCREL__
# If this isn't a pcrel libgcc then the functions we call here will
# require r2 to be valid. If __morestack is called from pcrel code r2
# won't be valid. Set it up.
bcl 20,31,1f
1:
mflr %r12
addis %r2,%r12,.TOC.-1b@ha
addi %r2,%r2,.TOC.-1b@l
#endif
# void __morestack_block_signals (void)
bl JUMP_TARGET(__morestack_block_signals)
# void *__generic_morestack (size_t *pframe_size,
# void *old_stack,
# size_t param_size)
addi %r3,%r29,NEWSTACKSIZE_SAVE
mr %r4,%r29
li %r5,0 # no copying from old stack
bl JUMP_TARGET(__generic_morestack)
# Start using new stack
stdu %r29,-32(%r3) # back-chain
mr %r1,%r3
# Set __private_ss stack guard for the new stack.
ld %r12,NEWSTACKSIZE_SAVE(%r29) # modified size
addi %r3,%r3,BACKOFF-32
sub %r3,%r3,%r12
# Note that a signal frame has $pc pointing at the instruction
# where the signal occurred. For something like a timer
# interrupt this means the instruction has already executed,
# thus the region starts at the instruction modifying
# __private_ss, not one instruction after.
.LEHB0:
std %r3,-0x7000-64(%r13) # tcbhead_t.__private_ss
# void __morestack_unblock_signals (void)
bl JUMP_TARGET(__morestack_unblock_signals)
# Set up for a call to the target function, located 3
# instructions after __morestack's return address.
#
ld %r12,LINKREG_SAVE(%r29)
#if _CALL_ELF == 2
ld %r2,R2_SAVE(%r29)
#endif
ld %r3,PARAMREG_SAVE+0(%r29) # restore arg regs
ld %r4,PARAMREG_SAVE+8(%r29)
ld %r5,PARAMREG_SAVE+16(%r29)
ld %r6,PARAMREG_SAVE+24(%r29)
ld %r7,PARAMREG_SAVE+32(%r29)
ld %r8,PARAMREG_SAVE+40(%r29)
ld %r9,PARAMREG_SAVE+48(%r29)
addi %r0,%r12,12 # add 3 instructions
ld %r10,PARAMREG_SAVE+56(%r29)
ld %r11,STATIC_CHAIN_SAVE(%r29)
cmpld %cr7,%r12,%r0 # indicate we were called
mtctr %r0
bctrl # call caller!
# On return, save regs possibly used to return a value, and
# possibly trashed by calls to __morestack_block_signals,
# __generic_releasestack and __morestack_unblock_signals.
# Assume those calls don't use vector or floating point regs.
std %r3,PARAMREG_SAVE+0(%r29)
std %r4,PARAMREG_SAVE+8(%r29)
std %r5,PARAMREG_SAVE+16(%r29)
std %r6,PARAMREG_SAVE+24(%r29)
#if _CALL_ELF == 2
std %r7,PARAMREG_SAVE+32(%r29)
std %r8,PARAMREG_SAVE+40(%r29)
std %r9,PARAMREG_SAVE+48(%r29)
std %r10,PARAMREG_SAVE+56(%r29)
#endif
#if _CALL_ELF == 2 && !defined __PCREL__
# r2 was restored for calling back into our caller. Set it up again.
bcl 20,31,1f
1:
mflr %r12
addis %r2,%r12,.TOC.-1b@ha
addi %r2,%r2,.TOC.-1b@l
#endif
bl JUMP_TARGET(__morestack_block_signals)
# void *__generic_releasestack (size_t *pavailable)
addi %r3,%r29,NEWSTACKSIZE_SAVE
bl JUMP_TARGET(__generic_releasestack)
# Reset __private_ss stack guard to value for old stack
ld %r12,NEWSTACKSIZE_SAVE(%r29)
addi %r3,%r3,BACKOFF
sub %r3,%r3,%r12
.LEHE0:
std %r3,-0x7000-64(%r13) # tcbhead_t.__private_ss
bl JUMP_TARGET(__morestack_unblock_signals)
# Use old stack again.
mr %r1,%r29
# Restore return value regs, and return.
ld %r0,LINKREG_SAVE(%r29)
mtlr %r0
#if _CALL_ELF == 2
ld %r2,R2_SAVE(%r29)
#endif
ld %r3,PARAMREG_SAVE+0(%r29)
ld %r4,PARAMREG_SAVE+8(%r29)
ld %r5,PARAMREG_SAVE+16(%r29)
ld %r6,PARAMREG_SAVE+24(%r29)
#if _CALL_ELF == 2
ld %r7,PARAMREG_SAVE+32(%r29)
ld %r8,PARAMREG_SAVE+40(%r29)
ld %r9,PARAMREG_SAVE+48(%r29)
ld %r10,PARAMREG_SAVE+56(%r29)
#endif
ld %r29,R29_SAVE(%r29)
.cfi_def_cfa_register %r1
blr
# This is the cleanup code called by the stack unwinder when
# unwinding through code between .LEHB0 and .LEHE0 above.
cleanup:
.cfi_def_cfa_register %r29
std %r3,PARAMREG_SAVE(%r29) # Save exception header
# size_t __generic_findstack (void *stack)
mr %r3,%r29
bl JUMP_TARGET(__generic_findstack)
sub %r3,%r29,%r3
addi %r3,%r3,BACKOFF
std %r3,-0x7000-64(%r13) # tcbhead_t.__private_ss
ld %r3,PARAMREG_SAVE(%r29)
bl JUMP_TARGET(_Unwind_Resume)
#ifndef __PCREL__
nop
#endif
.cfi_endproc
SIZE (__morestack)
.section .gcc_except_table,"a",@progbits
.p2align 2
.LLSDA1:
.byte 0xff # @LPStart format (omit)
.byte 0xff # @TType format (omit)
.byte 0x1 # call-site format (uleb128)
.uleb128 .LLSDACSE1-.LLSDACSB1 # Call-site table length
.LLSDACSB1:
.uleb128 .LEHB0-.LFB1 # region 0 start
.uleb128 .LEHE0-.LEHB0 # length
.uleb128 cleanup-.LFB1 # landing pad
.uleb128 0 # no action, ie. a cleanup
.LLSDACSE1:
#ifdef __PIC__
# Build a position independent reference to the personality function.
.hidden DW.ref.__gcc_personality_v0
.weak DW.ref.__gcc_personality_v0
.section .data.DW.ref.__gcc_personality_v0,"awG",@progbits,DW.ref.__gcc_personality_v0,comdat
.p2align 3
DW.ref.__gcc_personality_v0:
.quad __gcc_personality_v0
.type DW.ref.__gcc_personality_v0, @object
.size DW.ref.__gcc_personality_v0, 8
#endif
.text
# Initialize the stack guard when the program starts or when a
# new thread starts. This is called from a constructor.
# void __stack_split_initialize (void)
ENTRY(__stack_split_initialize)
.cfi_startproc
addi %r3,%r1,-0x4000 # We should have at least 16K.
std %r3,-0x7000-64(%r13) # tcbhead_t.__private_ss
# void __generic_morestack_set_initial_sp (void *sp, size_t len)
mr %r3,%r1
li %r4, 0x4000
b JUMP_TARGET(__generic_morestack_set_initial_sp)
# The lack of .cfi_endproc here is deliberate. This function and the
# following ones can all use the default FDE.
SIZE (__stack_split_initialize)
# Return current __private_ss
# void *__morestack_get_guard (void)
ENTRY0(__morestack_get_guard)
ld %r3,-0x7000-64(%r13) # tcbhead_t.__private_ss
blr
SIZE (__morestack_get_guard)
# Set __private_ss
# void __morestack_set_guard (void *ptr)
ENTRY0(__morestack_set_guard)
std %r3,-0x7000-64(%r13) # tcbhead_t.__private_ss
blr
SIZE (__morestack_set_guard)
# Return the stack guard value for given stack
# void *__morestack_make_guard (void *stack, size_t size)
ENTRY0(__morestack_make_guard)
sub %r3,%r3,%r4
addi %r3,%r3,BACKOFF
blr
.cfi_endproc
SIZE (__morestack_make_guard)
# Make __stack_split_initialize a high priority constructor.
#if HAVE_INITFINI_ARRAY_SUPPORT
.section .init_array.00000,"aw",@progbits
#else
.section .ctors.65535,"aw",@progbits
#endif
.p2align 3
.quad __stack_split_initialize
.quad __morestack_load_mmap
.section .note.GNU-stack,"",@progbits
.section .note.GNU-split-stack,"",@progbits
.section .note.GNU-no-split-stack,"",@progbits
#endif /* __powerpc64__ */
|
4ms/metamodule-plugin-sdk
| 3,303
|
plugin-libc/libgcc/config/rs6000/e500crtsavg64gprctr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for saving 64-bit integer registers, called by the compiler. */
/* "GOT" versions that load the address of the GOT into lr before returning. */
HIDDEN_FUNC(_save64gpr_ctr_14_g) evstdd 14,0(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_15_g) evstdd 15,8(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_16_g) evstdd 16,16(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_17_g) evstdd 17,24(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_18_g) evstdd 18,32(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_19_g) evstdd 19,40(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_20_g) evstdd 20,48(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_21_g) evstdd 21,56(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_22_g) evstdd 22,64(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_23_g) evstdd 23,72(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_24_g) evstdd 24,80(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_25_g) evstdd 25,88(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_26_g) evstdd 26,96(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_27_g) evstdd 27,104(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_28_g) evstdd 28,112(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_29_g) evstdd 29,120(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_30_g) evstdd 30,128(11)
bdz _save64gpr_ctr_g_done
HIDDEN_FUNC(_save64gpr_ctr_31_g) evstdd 31,136(11)
_save64gpr_ctr_g_done: b _GLOBAL_OFFSET_TABLE_-4
FUNC_END(_save64gpr_ctr_31_g)
FUNC_END(_save64gpr_ctr_30_g)
FUNC_END(_save64gpr_ctr_29_g)
FUNC_END(_save64gpr_ctr_28_g)
FUNC_END(_save64gpr_ctr_27_g)
FUNC_END(_save64gpr_ctr_26_g)
FUNC_END(_save64gpr_ctr_25_g)
FUNC_END(_save64gpr_ctr_24_g)
FUNC_END(_save64gpr_ctr_23_g)
FUNC_END(_save64gpr_ctr_22_g)
FUNC_END(_save64gpr_ctr_21_g)
FUNC_END(_save64gpr_ctr_20_g)
FUNC_END(_save64gpr_ctr_19_g)
FUNC_END(_save64gpr_ctr_18_g)
FUNC_END(_save64gpr_ctr_17_g)
FUNC_END(_save64gpr_ctr_16_g)
FUNC_END(_save64gpr_ctr_15_g)
FUNC_END(_save64gpr_ctr_14_g)
#endif
|
4ms/metamodule-plugin-sdk
| 2,566
|
plugin-libc/libgcc/config/rs6000/e500crtrest32gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for restoring 32-bit integer registers, called by the compiler. */
/* "Tail" versions that perform a tail call. */
HIDDEN_FUNC(_rest32gpr_14_t) lwz 14,-72(11)
HIDDEN_FUNC(_rest32gpr_15_t) lwz 15,-68(11)
HIDDEN_FUNC(_rest32gpr_16_t) lwz 16,-64(11)
HIDDEN_FUNC(_rest32gpr_17_t) lwz 17,-60(11)
HIDDEN_FUNC(_rest32gpr_18_t) lwz 18,-56(11)
HIDDEN_FUNC(_rest32gpr_19_t) lwz 19,-52(11)
HIDDEN_FUNC(_rest32gpr_20_t) lwz 20,-48(11)
HIDDEN_FUNC(_rest32gpr_21_t) lwz 21,-44(11)
HIDDEN_FUNC(_rest32gpr_22_t) lwz 22,-40(11)
HIDDEN_FUNC(_rest32gpr_23_t) lwz 23,-36(11)
HIDDEN_FUNC(_rest32gpr_24_t) lwz 24,-32(11)
HIDDEN_FUNC(_rest32gpr_25_t) lwz 25,-28(11)
HIDDEN_FUNC(_rest32gpr_26_t) lwz 26,-24(11)
HIDDEN_FUNC(_rest32gpr_27_t) lwz 27,-20(11)
HIDDEN_FUNC(_rest32gpr_28_t) lwz 28,-16(11)
HIDDEN_FUNC(_rest32gpr_29_t) lwz 29,-12(11)
HIDDEN_FUNC(_rest32gpr_30_t) lwz 30,-8(11)
HIDDEN_FUNC(_rest32gpr_31_t) lwz 31,-4(11)
lwz 0,4(11)
mr 1,11
blr
FUNC_END(_rest32gpr_31_t)
FUNC_END(_rest32gpr_30_t)
FUNC_END(_rest32gpr_29_t)
FUNC_END(_rest32gpr_28_t)
FUNC_END(_rest32gpr_27_t)
FUNC_END(_rest32gpr_26_t)
FUNC_END(_rest32gpr_25_t)
FUNC_END(_rest32gpr_24_t)
FUNC_END(_rest32gpr_23_t)
FUNC_END(_rest32gpr_22_t)
FUNC_END(_rest32gpr_21_t)
FUNC_END(_rest32gpr_20_t)
FUNC_END(_rest32gpr_19_t)
FUNC_END(_rest32gpr_18_t)
FUNC_END(_rest32gpr_17_t)
FUNC_END(_rest32gpr_16_t)
FUNC_END(_rest32gpr_15_t)
FUNC_END(_rest32gpr_14_t)
#endif
|
4ms/metamodule-plugin-sdk
| 2,493
|
plugin-libc/libgcc/config/rs6000/e500crtres64gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for restoring 64-bit integer registers, called by the compiler. */
/* "Bare" versions that return to their caller. */
HIDDEN_FUNC(_rest64gpr_14) evldd 14,0(11)
HIDDEN_FUNC(_rest64gpr_15) evldd 15,8(11)
HIDDEN_FUNC(_rest64gpr_16) evldd 16,16(11)
HIDDEN_FUNC(_rest64gpr_17) evldd 17,24(11)
HIDDEN_FUNC(_rest64gpr_18) evldd 18,32(11)
HIDDEN_FUNC(_rest64gpr_19) evldd 19,40(11)
HIDDEN_FUNC(_rest64gpr_20) evldd 20,48(11)
HIDDEN_FUNC(_rest64gpr_21) evldd 21,56(11)
HIDDEN_FUNC(_rest64gpr_22) evldd 22,64(11)
HIDDEN_FUNC(_rest64gpr_23) evldd 23,72(11)
HIDDEN_FUNC(_rest64gpr_24) evldd 24,80(11)
HIDDEN_FUNC(_rest64gpr_25) evldd 25,88(11)
HIDDEN_FUNC(_rest64gpr_26) evldd 26,96(11)
HIDDEN_FUNC(_rest64gpr_27) evldd 27,104(11)
HIDDEN_FUNC(_rest64gpr_28) evldd 28,112(11)
HIDDEN_FUNC(_rest64gpr_29) evldd 29,120(11)
HIDDEN_FUNC(_rest64gpr_30) evldd 30,128(11)
HIDDEN_FUNC(_rest64gpr_31) evldd 31,136(11)
blr
FUNC_END(_rest64gpr_31)
FUNC_END(_rest64gpr_30)
FUNC_END(_rest64gpr_29)
FUNC_END(_rest64gpr_28)
FUNC_END(_rest64gpr_27)
FUNC_END(_rest64gpr_26)
FUNC_END(_rest64gpr_25)
FUNC_END(_rest64gpr_24)
FUNC_END(_rest64gpr_23)
FUNC_END(_rest64gpr_22)
FUNC_END(_rest64gpr_21)
FUNC_END(_rest64gpr_20)
FUNC_END(_rest64gpr_19)
FUNC_END(_rest64gpr_18)
FUNC_END(_rest64gpr_17)
FUNC_END(_rest64gpr_16)
FUNC_END(_rest64gpr_15)
FUNC_END(_rest64gpr_14)
#endif
|
4ms/metamodule-plugin-sdk
| 1,238
|
plugin-libc/libgcc/config/rs6000/crtdbase.S
|
/* Defines __gcc_unwind_dbase
Copyright (C) 2014-2022 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Symbol used as an arbitrary base for offsets inside the data
* segment for unwind information. */
.file "crtdbase.S"
.globl __gcc_unwind_dbase
.csect __gcc_unwind_dbase[RW],2
.align 2
__gcc_unwind_dbase:
.long 0
|
4ms/metamodule-plugin-sdk
| 3,143
|
plugin-libc/libgcc/config/rs6000/e500crtres64gprctr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for restoring 64-bit integer registers where the number of
registers to be restored is passed in CTR, called by the compiler. */
HIDDEN_FUNC(_rest64gpr_ctr_14) evldd 14,0(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_15) evldd 15,8(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_16) evldd 16,16(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_17) evldd 17,24(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_18) evldd 18,32(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_19) evldd 19,40(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_20) evldd 20,48(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_21) evldd 21,56(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_22) evldd 22,64(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_23) evldd 23,72(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_24) evldd 24,80(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_25) evldd 25,88(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_26) evldd 26,96(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_27) evldd 27,104(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_28) evldd 28,112(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_29) evldd 29,120(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_30) evldd 30,128(11)
bdz _rest64gpr_ctr_done
HIDDEN_FUNC(_rest64gpr_ctr_31) evldd 31,136(11)
_rest64gpr_ctr_done: blr
FUNC_END(_rest64gpr_ctr_31)
FUNC_END(_rest64gpr_ctr_30)
FUNC_END(_rest64gpr_ctr_29)
FUNC_END(_rest64gpr_ctr_28)
FUNC_END(_rest64gpr_ctr_27)
FUNC_END(_rest64gpr_ctr_26)
FUNC_END(_rest64gpr_ctr_25)
FUNC_END(_rest64gpr_ctr_24)
FUNC_END(_rest64gpr_ctr_23)
FUNC_END(_rest64gpr_ctr_22)
FUNC_END(_rest64gpr_ctr_21)
FUNC_END(_rest64gpr_ctr_20)
FUNC_END(_rest64gpr_ctr_19)
FUNC_END(_rest64gpr_ctr_18)
FUNC_END(_rest64gpr_ctr_17)
FUNC_END(_rest64gpr_ctr_16)
FUNC_END(_rest64gpr_ctr_15)
FUNC_END(_rest64gpr_ctr_14)
#endif
|
4ms/metamodule-plugin-sdk
| 3,466
|
plugin-libc/libgcc/config/rs6000/darwin-vecsave.S
|
/* This file contains the vector save and restore routines.
*
* Copyright (C) 2004-2022 Free Software Foundation, Inc.
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Vector save/restore routines for Darwin. Note that each vector
save/restore requires 2 instructions (8 bytes.)
THE SAVE AND RESTORE ROUTINES CAN HAVE ONLY ONE GLOBALLY VISIBLE
ENTRY POINT - callers have to jump to "saveFP+60" to save f29..f31,
for example. For FP reg saves/restores, it takes one instruction
(4 bytes) to do the operation; for Vector regs, 2 instructions are
required (8 bytes.). */
/* With some assemblers, we need the correct machine directive to get the
right CPU type / subtype in the file header. */
#if __ppc64__
.machine ppc64
#else
.machine ppc7400
#endif
.text
.align 2
.private_extern saveVEC
saveVEC:
li r11,-192
stvx v20,r11,r0
li r11,-176
stvx v21,r11,r0
li r11,-160
stvx v22,r11,r0
li r11,-144
stvx v23,r11,r0
li r11,-128
stvx v24,r11,r0
li r11,-112
stvx v25,r11,r0
li r11,-96
stvx v26,r11,r0
li r11,-80
stvx v27,r11,r0
li r11,-64
stvx v28,r11,r0
li r11,-48
stvx v29,r11,r0
li r11,-32
stvx v30,r11,r0
li r11,-16
stvx v31,r11,r0
blr
.private_extern restVEC
restVEC:
li r11,-192
lvx v20,r11,r0
li r11,-176
lvx v21,r11,r0
li r11,-160
lvx v22,r11,r0
li r11,-144
lvx v23,r11,r0
li r11,-128
lvx v24,r11,r0
li r11,-112
lvx v25,r11,r0
li r11,-96
lvx v26,r11,r0
li r11,-80
lvx v27,r11,r0
li r11,-64
lvx v28,r11,r0
li r11,-48
lvx v29,r11,r0
li r11,-32
lvx v30,r11,r0
li r11,-16
lvx v31,r11,r0
blr
/* saveVEC_vr11 -- as saveVEC but VRsave is returned in R11. */
.private_extern saveVEC_vr11
saveVEC_vr11:
li r11,-192
stvx v20,r11,r0
li r11,-176
stvx v21,r11,r0
li r11,-160
stvx v22,r11,r0
li r11,-144
stvx v23,r11,r0
li r11,-128
stvx v24,r11,r0
li r11,-112
stvx v25,r11,r0
li r11,-96
stvx v26,r11,r0
li r11,-80
stvx v27,r11,r0
li r11,-64
stvx v28,r11,r0
li r11,-48
stvx v29,r11,r0
li r11,-32
stvx v30,r11,r0
li r11,-16
stvx v31,r11,r0
mfspr r11,VRsave
blr
/* As restVec, but the original VRsave value passed in R10. */
.private_extern restVEC_vr10
restVEC_vr10:
li r11,-192
lvx v20,r11,r0
li r11,-176
lvx v21,r11,r0
li r11,-160
lvx v22,r11,r0
li r11,-144
lvx v23,r11,r0
li r11,-128
lvx v24,r11,r0
li r11,-112
lvx v25,r11,r0
li r11,-96
lvx v26,r11,r0
li r11,-80
lvx v27,r11,r0
li r11,-64
lvx v28,r11,r0
li r11,-48
lvx v29,r11,r0
li r11,-32
lvx v30,r11,r0
li r11,-16
lvx v31,r11,r0
/* restore VRsave from R10. */
mtspr VRsave,r10
blr
|
4ms/metamodule-plugin-sdk
| 3,685
|
plugin-libc/libgcc/config/rs6000/darwin-gpsave.S
|
/* This file contains the GPR save and restore routines for Darwin.
*
* Copyright (C) 2011-2022 Free Software Foundation, Inc.
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Contributed by Iain Sandoe <iains@gcc.gnu.org> */
/* Like their FP and VEC counterparts, these routines have only one externally
visible entry point. Calls have to be constructed as offsets from this.
(I.E. callers have to jump to "saveGPR+((x-13)*4" to save registers x..31).
Each save/load instruction is 4 bytes long (for both m32 and m64 builds).
The save/restores here are done w.r.t r11.
restGPRx restores the link reg from the stack and returns to the saved
address.
*/
#include "darwin-asm.h"
.text
.align 2
.private_extern saveGPR
saveGPR:
stg r13,(-19 * GPR_BYTES)(r11)
stg r14,(-18 * GPR_BYTES)(r11)
stg r15,(-17 * GPR_BYTES)(r11)
stg r16,(-16 * GPR_BYTES)(r11)
stg r17,(-15 * GPR_BYTES)(r11)
stg r18,(-14 * GPR_BYTES)(r11)
stg r19,(-13 * GPR_BYTES)(r11)
stg r20,(-12 * GPR_BYTES)(r11)
stg r21,(-11 * GPR_BYTES)(r11)
stg r22,(-10 * GPR_BYTES)(r11)
stg r23,( -9 * GPR_BYTES)(r11)
stg r24,( -8 * GPR_BYTES)(r11)
stg r25,( -7 * GPR_BYTES)(r11)
stg r26,( -6 * GPR_BYTES)(r11)
stg r27,( -5 * GPR_BYTES)(r11)
stg r28,( -4 * GPR_BYTES)(r11)
stg r29,( -3 * GPR_BYTES)(r11)
stg r30,( -2 * GPR_BYTES)(r11)
stg r31,( -1 * GPR_BYTES)(r11)
blr
/* */
.private_extern restGPR
restGPR:
lg r13,(-19 * GPR_BYTES)(r11)
lg r14,(-18 * GPR_BYTES)(r11)
lg r15,(-17 * GPR_BYTES)(r11)
lg r16,(-16 * GPR_BYTES)(r11)
lg r17,(-15 * GPR_BYTES)(r11)
lg r18,(-14 * GPR_BYTES)(r11)
lg r19,(-13 * GPR_BYTES)(r11)
lg r20,(-12 * GPR_BYTES)(r11)
lg r21,(-11 * GPR_BYTES)(r11)
lg r22,(-10 * GPR_BYTES)(r11)
lg r23,( -9 * GPR_BYTES)(r11)
lg r24,( -8 * GPR_BYTES)(r11)
lg r25,( -7 * GPR_BYTES)(r11)
lg r26,( -6 * GPR_BYTES)(r11)
lg r27,( -5 * GPR_BYTES)(r11)
lg r28,( -4 * GPR_BYTES)(r11)
lg r29,( -3 * GPR_BYTES)(r11)
lg r30,( -2 * GPR_BYTES)(r11)
lg r31,( -1 * GPR_BYTES)(r11)
blr
.private_extern restGPRx
restGPRx:
lg r13,(-19 * GPR_BYTES)(r11)
lg r14,(-18 * GPR_BYTES)(r11)
lg r15,(-17 * GPR_BYTES)(r11)
lg r16,(-16 * GPR_BYTES)(r11)
lg r17,(-15 * GPR_BYTES)(r11)
lg r18,(-14 * GPR_BYTES)(r11)
lg r19,(-13 * GPR_BYTES)(r11)
lg r20,(-12 * GPR_BYTES)(r11)
lg r21,(-11 * GPR_BYTES)(r11)
lg r22,(-10 * GPR_BYTES)(r11)
lg r23,( -9 * GPR_BYTES)(r11)
lg r24,( -8 * GPR_BYTES)(r11)
lg r25,( -7 * GPR_BYTES)(r11)
lg r26,( -6 * GPR_BYTES)(r11)
lg r27,( -5 * GPR_BYTES)(r11)
lg r28,( -4 * GPR_BYTES)(r11)
lg r29,( -3 * GPR_BYTES)(r11)
/* Like the FP restore, we start from the offset for r30
thus a restore of only r31 is not going to work. */
lg r0,SAVED_LR_OFFSET(r1)
lg r30,( -2 * GPR_BYTES)(r11)
mtlr r0
lg r31,( -1 * GPR_BYTES)(r11)
blr
|
4ms/metamodule-plugin-sdk
| 2,763
|
plugin-libc/libgcc/config/rs6000/crtsavfpr.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
* 64-bit support written by David Edelsohn
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.machine ppc
.section ".text"
#include "ppc-asm.h"
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
/* Routines for saving floating point registers, called by the compiler. */
/* Called with r11 pointing to the stack header word of the caller of the */
/* function, just beyond the end of the floating point save area. */
CFI_STARTPROC
HIDDEN_FUNC(_savefpr_14) stfd 14,-144(11) /* save fp registers */
HIDDEN_FUNC(_savefpr_15) stfd 15,-136(11)
HIDDEN_FUNC(_savefpr_16) stfd 16,-128(11)
HIDDEN_FUNC(_savefpr_17) stfd 17,-120(11)
HIDDEN_FUNC(_savefpr_18) stfd 18,-112(11)
HIDDEN_FUNC(_savefpr_19) stfd 19,-104(11)
HIDDEN_FUNC(_savefpr_20) stfd 20,-96(11)
HIDDEN_FUNC(_savefpr_21) stfd 21,-88(11)
HIDDEN_FUNC(_savefpr_22) stfd 22,-80(11)
HIDDEN_FUNC(_savefpr_23) stfd 23,-72(11)
HIDDEN_FUNC(_savefpr_24) stfd 24,-64(11)
HIDDEN_FUNC(_savefpr_25) stfd 25,-56(11)
HIDDEN_FUNC(_savefpr_26) stfd 26,-48(11)
HIDDEN_FUNC(_savefpr_27) stfd 27,-40(11)
HIDDEN_FUNC(_savefpr_28) stfd 28,-32(11)
HIDDEN_FUNC(_savefpr_29) stfd 29,-24(11)
HIDDEN_FUNC(_savefpr_30) stfd 30,-16(11)
HIDDEN_FUNC(_savefpr_31) stfd 31,-8(11)
blr
FUNC_END(_savefpr_31)
FUNC_END(_savefpr_30)
FUNC_END(_savefpr_29)
FUNC_END(_savefpr_28)
FUNC_END(_savefpr_27)
FUNC_END(_savefpr_26)
FUNC_END(_savefpr_25)
FUNC_END(_savefpr_24)
FUNC_END(_savefpr_23)
FUNC_END(_savefpr_22)
FUNC_END(_savefpr_21)
FUNC_END(_savefpr_20)
FUNC_END(_savefpr_19)
FUNC_END(_savefpr_18)
FUNC_END(_savefpr_17)
FUNC_END(_savefpr_16)
FUNC_END(_savefpr_15)
FUNC_END(_savefpr_14)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,418
|
plugin-libc/libgcc/config/rs6000/sol-ci.S
|
# crti.s for sysv4
# Copyright (C) 1996-2022 Free Software Foundation, Inc.
# Written By Michael Meissner
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just supplies labeled starting points for the .got* and other
# special sections. It is linked in first before other modules.
.ident "GNU C scrti.s"
#ifndef __powerpc64__
# Start of .text
.section ".text"
.globl _ex_text0
_ex_text0:
# Exception range
.section ".exception_ranges","aw"
.globl _ex_range0
_ex_range0:
# List of C++ constructors
.section ".ctors","aw"
.globl __CTOR_LIST__
.type __CTOR_LIST__,@object
__CTOR_LIST__:
# List of C++ destructors
.section ".dtors","aw"
.globl __DTOR_LIST__
.type __DTOR_LIST__,@object
__DTOR_LIST__:
# Head of _init function used for static constructors
.section ".init","ax"
.align 2
.globl _init
.type _init,@function
_init: stwu %r1,-16(%r1)
mflr %r0
stw %r31,12(%r1)
stw %r0,16(%r1)
bl _GLOBAL_OFFSET_TABLE_-4 # get the GOT address
mflr %r31
# lwz %r3,_ex_shared0@got(%r31)
# lwz %r4,-8(%r3) # _ex_register or 0
# cmpi %cr0,%r4,0
# beq .Lno_reg
# mtlr %r4
# blrl
#.Lno_reg:
# Head of _fini function used for static destructors
.section ".fini","ax"
.align 2
.globl _fini
.type _fini,@function
_fini: stwu %r1,-16(%r1)
mflr %r0
stw %r31,12(%r1)
stw %r0,16(%r1)
bl _GLOBAL_OFFSET_TABLE_-4 # get the GOT address
mflr %r31
# _environ and its evil twin environ, pointing to the environment
.section ".sdata","aw"
.align 2
.globl _environ
.space 4
.weak environ
.set environ,_environ
#endif
|
4ms/metamodule-plugin-sdk
| 3,207
|
plugin-libc/libgcc/config/rs6000/e500crtsav64gprctr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for saving 64-bit integer registers where the number of
registers to be saved is passed in CTR, called by the compiler. */
/* "Bare" versions that return to their caller. */
HIDDEN_FUNC(_save64gpr_ctr_14) evstdd 14,0(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_15) evstdd 15,8(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_16) evstdd 16,16(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_17) evstdd 17,24(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_18) evstdd 18,32(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_19) evstdd 19,40(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_20) evstdd 20,48(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_21) evstdd 21,56(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_22) evstdd 22,64(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_23) evstdd 23,72(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_24) evstdd 24,80(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_25) evstdd 25,88(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_26) evstdd 26,96(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_27) evstdd 27,104(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_28) evstdd 28,112(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_29) evstdd 29,120(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_30) evstdd 30,128(11)
bdz _save64gpr_ctr_done
HIDDEN_FUNC(_save64gpr_ctr_31) evstdd 31,136(11)
_save64gpr_ctr_done: blr
FUNC_END(_save64gpr_ctr_31)
FUNC_END(_save64gpr_ctr_30)
FUNC_END(_save64gpr_ctr_29)
FUNC_END(_save64gpr_ctr_28)
FUNC_END(_save64gpr_ctr_27)
FUNC_END(_save64gpr_ctr_26)
FUNC_END(_save64gpr_ctr_25)
FUNC_END(_save64gpr_ctr_24)
FUNC_END(_save64gpr_ctr_23)
FUNC_END(_save64gpr_ctr_22)
FUNC_END(_save64gpr_ctr_21)
FUNC_END(_save64gpr_ctr_20)
FUNC_END(_save64gpr_ctr_19)
FUNC_END(_save64gpr_ctr_18)
FUNC_END(_save64gpr_ctr_17)
FUNC_END(_save64gpr_ctr_16)
FUNC_END(_save64gpr_ctr_15)
FUNC_END(_save64gpr_ctr_14)
#endif
|
4ms/metamodule-plugin-sdk
| 2,669
|
plugin-libc/libgcc/config/rs6000/darwin-fpsave.S
|
/* This file contains the floating-point save and restore routines.
*
* Copyright (C) 2004-2022 Free Software Foundation, Inc.
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* THE SAVE AND RESTORE ROUTINES CAN HAVE ONLY ONE GLOBALLY VISIBLE
ENTRY POINT - callers have to jump to "saveFP+60" to save f29..f31,
for example. For FP reg saves/restores, it takes one instruction
(4 bytes) to do the operation; for Vector regs, 2 instructions are
required (8 bytes.)
MORAL: DO NOT MESS AROUND WITH THESE FUNCTIONS! */
#include "darwin-asm.h"
.text
.align 2
/* saveFP saves R0 -- assumed to be the callers LR -- to 8/16(R1). */
.private_extern saveFP
saveFP:
stfd f14,-144(r1)
stfd f15,-136(r1)
stfd f16,-128(r1)
stfd f17,-120(r1)
stfd f18,-112(r1)
stfd f19,-104(r1)
stfd f20,-96(r1)
stfd f21,-88(r1)
stfd f22,-80(r1)
stfd f23,-72(r1)
stfd f24,-64(r1)
stfd f25,-56(r1)
stfd f26,-48(r1)
stfd f27,-40(r1)
stfd f28,-32(r1)
stfd f29,-24(r1)
stfd f30,-16(r1)
stfd f31,-8(r1)
stg r0,SAVED_LR_OFFSET(r1)
blr
/* restFP restores the caller`s LR from 8/16(R1). Note that the code for
this starts at the offset of F30 restoration, so calling this
routine in an attempt to restore only F31 WILL NOT WORK (it would
be a stupid thing to do, anyway.) */
.private_extern restFP
restFP:
lfd f14,-144(r1)
lfd f15,-136(r1)
lfd f16,-128(r1)
lfd f17,-120(r1)
lfd f18,-112(r1)
lfd f19,-104(r1)
lfd f20,-96(r1)
lfd f21,-88(r1)
lfd f22,-80(r1)
lfd f23,-72(r1)
lfd f24,-64(r1)
lfd f25,-56(r1)
lfd f26,-48(r1)
lfd f27,-40(r1)
lfd f28,-32(r1)
lfd f29,-24(r1)
/* <OFFSET OF F30 RESTORE> restore callers LR */
lg r0,SAVED_LR_OFFSET(r1)
lfd f30,-16(r1)
/* and prepare for return to caller */
mtlr r0
lfd f31,-8(r1)
blr
|
4ms/metamodule-plugin-sdk
| 3,599
|
plugin-libc/libgcc/config/rs6000/crtresxgpr.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
* 64-bit support written by David Edelsohn
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.section ".text"
#include "ppc-asm.h"
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
/* Routines for restoring integer registers, called by the compiler. */
/* Called with r11 pointing to the stack header word of the caller of the */
/* function, just beyond the end of the integer restore area. */
CFI_STARTPROC
CFI_DEF_CFA_REGISTER (11)
CFI_OFFSET (65, 4)
CFI_OFFSET (14, -72)
CFI_OFFSET (15, -68)
CFI_OFFSET (16, -64)
CFI_OFFSET (17, -60)
CFI_OFFSET (18, -56)
CFI_OFFSET (19, -52)
CFI_OFFSET (20, -48)
CFI_OFFSET (21, -44)
CFI_OFFSET (22, -40)
CFI_OFFSET (23, -36)
CFI_OFFSET (24, -32)
CFI_OFFSET (25, -28)
CFI_OFFSET (26, -24)
CFI_OFFSET (27, -20)
CFI_OFFSET (28, -16)
CFI_OFFSET (29, -12)
CFI_OFFSET (30, -8)
CFI_OFFSET (31, -4)
HIDDEN_FUNC(_restgpr_14_x) lwz 14,-72(11) /* restore gp registers */
CFI_RESTORE (14)
HIDDEN_FUNC(_restgpr_15_x) lwz 15,-68(11)
CFI_RESTORE (15)
HIDDEN_FUNC(_restgpr_16_x) lwz 16,-64(11)
CFI_RESTORE (16)
HIDDEN_FUNC(_restgpr_17_x) lwz 17,-60(11)
CFI_RESTORE (17)
HIDDEN_FUNC(_restgpr_18_x) lwz 18,-56(11)
CFI_RESTORE (18)
HIDDEN_FUNC(_restgpr_19_x) lwz 19,-52(11)
CFI_RESTORE (19)
HIDDEN_FUNC(_restgpr_20_x) lwz 20,-48(11)
CFI_RESTORE (20)
HIDDEN_FUNC(_restgpr_21_x) lwz 21,-44(11)
CFI_RESTORE (21)
HIDDEN_FUNC(_restgpr_22_x) lwz 22,-40(11)
CFI_RESTORE (22)
HIDDEN_FUNC(_restgpr_23_x) lwz 23,-36(11)
CFI_RESTORE (23)
HIDDEN_FUNC(_restgpr_24_x) lwz 24,-32(11)
CFI_RESTORE (24)
HIDDEN_FUNC(_restgpr_25_x) lwz 25,-28(11)
CFI_RESTORE (25)
HIDDEN_FUNC(_restgpr_26_x) lwz 26,-24(11)
CFI_RESTORE (26)
HIDDEN_FUNC(_restgpr_27_x) lwz 27,-20(11)
CFI_RESTORE (27)
HIDDEN_FUNC(_restgpr_28_x) lwz 28,-16(11)
CFI_RESTORE (28)
HIDDEN_FUNC(_restgpr_29_x) lwz 29,-12(11)
CFI_RESTORE (29)
HIDDEN_FUNC(_restgpr_30_x) lwz 30,-8(11)
CFI_RESTORE (30)
HIDDEN_FUNC(_restgpr_31_x) lwz 0,4(11)
lwz 31,-4(11)
CFI_RESTORE (31)
mtlr 0
CFI_RESTORE (65)
mr 1,11
CFI_DEF_CFA_REGISTER (1)
blr
FUNC_END(_restgpr_31_x)
FUNC_END(_restgpr_30_x)
FUNC_END(_restgpr_29_x)
FUNC_END(_restgpr_28_x)
FUNC_END(_restgpr_27_x)
FUNC_END(_restgpr_26_x)
FUNC_END(_restgpr_25_x)
FUNC_END(_restgpr_24_x)
FUNC_END(_restgpr_23_x)
FUNC_END(_restgpr_22_x)
FUNC_END(_restgpr_21_x)
FUNC_END(_restgpr_20_x)
FUNC_END(_restgpr_19_x)
FUNC_END(_restgpr_18_x)
FUNC_END(_restgpr_17_x)
FUNC_END(_restgpr_16_x)
FUNC_END(_restgpr_15_x)
FUNC_END(_restgpr_14_x)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,794
|
plugin-libc/libgcc/config/rs6000/eabi-ci.S
|
/* crti.s for eabi
Copyright (C) 1996-2022 Free Software Foundation, Inc.
Written By Michael Meissner
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* This file just supplies labeled starting points for the .got* and other
special sections. It is linked in first before other modules. */
.ident "GNU C crti.s"
#include <ppc-asm.h>
#ifndef __powerpc64__
.section ".got","aw"
.globl __GOT_START__
.type __GOT_START__,@object
__GOT_START__:
.section ".got1","aw"
.globl __GOT1_START__
.type __GOT1_START__,@object
__GOT1_START__:
.section ".got2","aw"
.globl __GOT2_START__
.type __GOT2_START__,@object
__GOT2_START__:
.section ".fixup","aw"
.globl __FIXUP_START__
.type __FIXUP_START__,@object
__FIXUP_START__:
.section ".ctors","aw"
.globl __CTOR_LIST__
.type __CTOR_LIST__,@object
__CTOR_LIST__:
.section ".dtors","aw"
.globl __DTOR_LIST__
.type __DTOR_LIST__,@object
__DTOR_LIST__:
.section ".sdata","aw"
.globl __SDATA_START__
.type __SDATA_START__,@object
.weak _SDA_BASE_
.type _SDA_BASE_,@object
__SDATA_START__:
_SDA_BASE_:
.section ".sbss","aw",@nobits
.globl __SBSS_START__
.type __SBSS_START__,@object
__SBSS_START__:
.section ".sdata2","a"
.weak _SDA2_BASE_
.type _SDA2_BASE_,@object
.globl __SDATA2_START__
.type __SDATA2_START__,@object
__SDATA2_START__:
_SDA2_BASE_:
.section ".sbss2","a"
.globl __SBSS2_START__
.type __SBSS2_START__,@object
__SBSS2_START__:
.section ".gcc_except_table","aw"
.globl __EXCEPT_START__
.type __EXCEPT_START__,@object
__EXCEPT_START__:
.section ".eh_frame","aw"
.globl __EH_FRAME_BEGIN__
.type __EH_FRAME_BEGIN__,@object
__EH_FRAME_BEGIN__:
/* Head of __init function used for static constructors. */
.section ".init","ax"
.align 2
FUNC_START(__init)
stwu 1,-16(1)
mflr 0
stw 0,20(1)
/* Head of __fini function used for static destructors. */
.section ".fini","ax"
.align 2
FUNC_START(__fini)
stwu 1,-16(1)
mflr 0
stw 0,20(1)
#endif
|
4ms/metamodule-plugin-sdk
| 2,476
|
plugin-libc/libgcc/config/rs6000/e500crtres32gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for restoring 32-bit integer registers, called by the compiler. */
/* "Bare" versions that simply return to their caller. */
HIDDEN_FUNC(_rest32gpr_14) lwz 14,-72(11)
HIDDEN_FUNC(_rest32gpr_15) lwz 15,-68(11)
HIDDEN_FUNC(_rest32gpr_16) lwz 16,-64(11)
HIDDEN_FUNC(_rest32gpr_17) lwz 17,-60(11)
HIDDEN_FUNC(_rest32gpr_18) lwz 18,-56(11)
HIDDEN_FUNC(_rest32gpr_19) lwz 19,-52(11)
HIDDEN_FUNC(_rest32gpr_20) lwz 20,-48(11)
HIDDEN_FUNC(_rest32gpr_21) lwz 21,-44(11)
HIDDEN_FUNC(_rest32gpr_22) lwz 22,-40(11)
HIDDEN_FUNC(_rest32gpr_23) lwz 23,-36(11)
HIDDEN_FUNC(_rest32gpr_24) lwz 24,-32(11)
HIDDEN_FUNC(_rest32gpr_25) lwz 25,-28(11)
HIDDEN_FUNC(_rest32gpr_26) lwz 26,-24(11)
HIDDEN_FUNC(_rest32gpr_27) lwz 27,-20(11)
HIDDEN_FUNC(_rest32gpr_28) lwz 28,-16(11)
HIDDEN_FUNC(_rest32gpr_29) lwz 29,-12(11)
HIDDEN_FUNC(_rest32gpr_30) lwz 30,-8(11)
HIDDEN_FUNC(_rest32gpr_31) lwz 31,-4(11)
blr
FUNC_END(_rest32gpr_31)
FUNC_END(_rest32gpr_30)
FUNC_END(_rest32gpr_29)
FUNC_END(_rest32gpr_28)
FUNC_END(_rest32gpr_27)
FUNC_END(_rest32gpr_26)
FUNC_END(_rest32gpr_25)
FUNC_END(_rest32gpr_24)
FUNC_END(_rest32gpr_23)
FUNC_END(_rest32gpr_22)
FUNC_END(_rest32gpr_21)
FUNC_END(_rest32gpr_20)
FUNC_END(_rest32gpr_19)
FUNC_END(_rest32gpr_18)
FUNC_END(_rest32gpr_17)
FUNC_END(_rest32gpr_16)
FUNC_END(_rest32gpr_15)
FUNC_END(_rest32gpr_14)
#endif
|
4ms/metamodule-plugin-sdk
| 3,117
|
plugin-libc/libgcc/config/rs6000/darwin-tramp.S
|
/* Special support for trampolines
*
* Copyright (C) 1996-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
#include "darwin-asm.h"
/* Set up trampolines. */
.text
.align LOG2_GPR_BYTES
Ltrampoline_initial:
mflr r0
bl 1f
Lfunc = .-Ltrampoline_initial
.g_long 0 /* will be replaced with function address */
Lchain = .-Ltrampoline_initial
.g_long 0 /* will be replaced with static chain */
1: mflr r11
lg r12,0(r11) /* function address */
mtlr r0
mtctr r12
lg r11,GPR_BYTES(r11) /* static chain */
bctr
trampoline_size = .-Ltrampoline_initial
/* R3 = stack address to store trampoline */
/* R4 = length of trampoline area */
/* R5 = function address */
/* R6 = static chain */
.globl ___trampoline_setup
___trampoline_setup:
mflr r0 /* save return address */
bcl 20,31,LCF0 /* load up __trampoline_initial into r7 */
LCF0:
mflr r11
addis r7,r11,ha16(LTRAMP-LCF0)
lg r7,lo16(LTRAMP-LCF0)(r7)
subi r7,r7,4
li r8,trampoline_size /* verify trampoline big enough */
cmpg cr1,r8,r4
srwi r4,r4,2 /* # words to move (insns always 4-byte) */
addi r9,r3,-4 /* adjust pointer for lgu */
mtctr r4
blt cr1,Labort
mtlr r0
/* Copy the instructions to the stack */
Lmove:
lwzu r10,4(r7)
stwu r10,4(r9)
bdnz Lmove
/* Store correct function and static chain */
stg r5,Lfunc(r3)
stg r6,Lchain(r3)
/* Now flush both caches */
mtctr r4
Lcache:
icbi 0,r3
dcbf 0,r3
addi r3,r3,4
bdnz Lcache
/* Ensure cache-flushing has finished. */
sync
isync
/* Make stack writeable. */
b ___enable_execute_stack
Labort:
#ifdef __DYNAMIC__
bl L_abort$stub
.data
.section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32
.align 2
L_abort$stub:
.indirect_symbol _abort
mflr r0
bcl 20,31,L0$_abort
L0$_abort:
mflr r11
addis r11,r11,ha16(L_abort$lazy_ptr-L0$_abort)
mtlr r0
lgu r12,lo16(L_abort$lazy_ptr-L0$_abort)(r11)
mtctr r12
bctr
.data
.lazy_symbol_pointer
L_abort$lazy_ptr:
.indirect_symbol _abort
.g_long dyld_stub_binding_helper
#else
bl _abort
#endif
.data
.align LOG2_GPR_BYTES
LTRAMP:
.g_long Ltrampoline_initial
|
4ms/metamodule-plugin-sdk
| 4,651
|
plugin-libc/libgcc/config/rs6000/tramp.S
|
/* Special support for trampolines
*
* Copyright (C) 1996-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Set up trampolines. */
.section ".text"
#include "ppc-asm.h"
#include "config.h"
#ifndef __powerpc64__
.type trampoline_initial,@object
.align 2
trampoline_initial:
mflr r0
bcl 20,31,1f
.Lfunc = .-trampoline_initial
.long 0 /* will be replaced with function address */
.Lchain = .-trampoline_initial
.long 0 /* will be replaced with static chain */
1: mflr r11
mtlr r0
lwz r0,0(r11) /* function address */
lwz r11,4(r11) /* static chain */
mtctr r0
bctr
trampoline_size = .-trampoline_initial
.size trampoline_initial,trampoline_size
/* R3 = stack address to store trampoline */
/* R4 = length of trampoline area */
/* R5 = function address */
/* R6 = static chain */
FUNC_START(__trampoline_setup)
.cfi_startproc
mflr r0 /* save return address */
bcl 20,31,.LCF0 /* load up __trampoline_initial into r7 */
.cfi_register lr,r0
.LCF0:
mflr r11
addi r7,r11,trampoline_initial-4-.LCF0 /* trampoline address -4 */
cmpwi cr1,r4,trampoline_size /* verify that the trampoline is big enough */
srwi r4,r4,2 /* # words to move */
addi r9,r3,-4 /* adjust pointer for lwzu */
mtctr r4
blt cr1,.Labort
mtlr r0
/* Copy the instructions to the stack */
.Lmove:
lwzu r10,4(r7)
stwu r10,4(r9)
bdnz .Lmove
/* Store correct function and static chain */
stw r5,.Lfunc(r3)
stw r6,.Lchain(r3)
/* Now flush both caches */
mtctr r4
.Lcache:
icbi 0,r3
dcbf 0,r3
addi r3,r3,4
bdnz .Lcache
/* Finally synchronize things & return */
sync
isync
blr
.Labort:
/* Use a longcall sequence in the non PIC case on VxWorks, to prevent
possible relocation errors if this is module-loaded very far away from
the 'abort' entry point. */
#if defined (__VXWORKS__) && ! (defined __PIC__ || defined __pic__)
lis r11,JUMP_TARGET(abort)@ha
addic r11,r11,JUMP_TARGET(abort)@l
mtlr r11
blrl
#else
#if (defined __PIC__ || defined __pic__) && defined HAVE_AS_REL16
bcl 20,31,1f
1: mflr r30
addis r30,r30,_GLOBAL_OFFSET_TABLE_-1b@ha
addi r30,r30,_GLOBAL_OFFSET_TABLE_-1b@l
#endif
bl JUMP_TARGET(abort)
#endif
.cfi_endproc
FUNC_END(__trampoline_setup)
#elif _CALL_ELF == 2
.type trampoline_initial,@object
.align 3
trampoline_initial:
ld r11,.Lchain(r12)
ld r12,.Lfunc(r12)
mtctr r12
bctr
.Lfunc = .-trampoline_initial
.quad 0 /* will be replaced with function address */
.Lchain = .-trampoline_initial
.quad 0 /* will be replaced with static chain */
trampoline_size = .-trampoline_initial
.size trampoline_initial,trampoline_size
/* R3 = stack address to store trampoline */
/* R4 = length of trampoline area */
/* R5 = function address */
/* R6 = static chain */
#ifndef __PCREL__
.pushsection ".toc","aw"
.LC0:
.quad trampoline_initial-8
.popsection
#endif
FUNC_START(__trampoline_setup)
.cfi_startproc
#ifdef __PCREL__
pla 7,(trampoline_initial-8)@pcrel
#else
addis 7,2,.LC0@toc@ha
ld 7,.LC0@toc@l(7) /* trampoline address -8 */
#endif
cmpwi cr1,r4,trampoline_size /* verify that the trampoline is big enough */
srwi r4,r4,3 /* # doublewords to move */
addi r9,r3,-8 /* adjust pointer for stdu */
mtctr r4
blt cr1,.Labort
/* Copy the instructions to the stack */
.Lmove:
ldu r10,8(r7)
stdu r10,8(r9)
bdnz .Lmove
/* Store correct function and static chain */
std r5,.Lfunc(r3)
std r6,.Lchain(r3)
/* Now flush both caches */
mtctr r4
.Lcache:
icbi 0,r3
dcbf 0,r3
addi r3,r3,8
bdnz .Lcache
/* Finally synchronize things & return */
sync
isync
blr
.Labort:
bl JUMP_TARGET(abort)
nop
.cfi_endproc
FUNC_END(__trampoline_setup)
#endif
|
4ms/metamodule-plugin-sdk
| 2,262
|
plugin-libc/libgcc/config/rs6000/crtsavevr.S
|
/* Routines for saving vector registers.
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Written by Alan Modra, IBM
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
#undef __ALTIVEC__
#define __ALTIVEC__ 1
#include "ppc-asm.h"
/* Called with r0 pointing just beyond the end of the vector save area. */
.machine altivec
.section ".text"
CFI_STARTPROC
HIDDEN_FUNC(_savevr_20)
li r11,-192
stvx v20,r11,r0
HIDDEN_FUNC(_savevr_21)
li r11,-176
stvx v21,r11,r0
HIDDEN_FUNC(_savevr_22)
li r11,-160
stvx v22,r11,r0
HIDDEN_FUNC(_savevr_23)
li r11,-144
stvx v23,r11,r0
HIDDEN_FUNC(_savevr_24)
li r11,-128
stvx v24,r11,r0
HIDDEN_FUNC(_savevr_25)
li r11,-112
stvx v25,r11,r0
HIDDEN_FUNC(_savevr_26)
li r11,-96
stvx v26,r11,r0
HIDDEN_FUNC(_savevr_27)
li r11,-80
stvx v27,r11,r0
HIDDEN_FUNC(_savevr_28)
li r11,-64
stvx v28,r11,r0
HIDDEN_FUNC(_savevr_29)
li r11,-48
stvx v29,r11,r0
HIDDEN_FUNC(_savevr_30)
li r11,-32
stvx v30,r11,r0
HIDDEN_FUNC(_savevr_31)
li r11,-16
stvx v31,r11,r0
blr
FUNC_END(_savevr_31)
FUNC_END(_savevr_30)
FUNC_END(_savevr_29)
FUNC_END(_savevr_28)
FUNC_END(_savevr_27)
FUNC_END(_savevr_26)
FUNC_END(_savevr_25)
FUNC_END(_savevr_24)
FUNC_END(_savevr_23)
FUNC_END(_savevr_22)
FUNC_END(_savevr_21)
FUNC_END(_savevr_20)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,473
|
plugin-libc/libgcc/config/rs6000/e500crtsav32gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for saving 32-bit integer registers, called by the compiler. */
/* "Bare" versions that simply return to their caller. */
HIDDEN_FUNC(_save32gpr_14) stw 14,-72(11)
HIDDEN_FUNC(_save32gpr_15) stw 15,-68(11)
HIDDEN_FUNC(_save32gpr_16) stw 16,-64(11)
HIDDEN_FUNC(_save32gpr_17) stw 17,-60(11)
HIDDEN_FUNC(_save32gpr_18) stw 18,-56(11)
HIDDEN_FUNC(_save32gpr_19) stw 19,-52(11)
HIDDEN_FUNC(_save32gpr_20) stw 20,-48(11)
HIDDEN_FUNC(_save32gpr_21) stw 21,-44(11)
HIDDEN_FUNC(_save32gpr_22) stw 22,-40(11)
HIDDEN_FUNC(_save32gpr_23) stw 23,-36(11)
HIDDEN_FUNC(_save32gpr_24) stw 24,-32(11)
HIDDEN_FUNC(_save32gpr_25) stw 25,-28(11)
HIDDEN_FUNC(_save32gpr_26) stw 26,-24(11)
HIDDEN_FUNC(_save32gpr_27) stw 27,-20(11)
HIDDEN_FUNC(_save32gpr_28) stw 28,-16(11)
HIDDEN_FUNC(_save32gpr_29) stw 29,-12(11)
HIDDEN_FUNC(_save32gpr_30) stw 30,-8(11)
HIDDEN_FUNC(_save32gpr_31) stw 31,-4(11)
blr
FUNC_END(_save32gpr_31)
FUNC_END(_save32gpr_30)
FUNC_END(_save32gpr_29)
FUNC_END(_save32gpr_28)
FUNC_END(_save32gpr_27)
FUNC_END(_save32gpr_26)
FUNC_END(_save32gpr_25)
FUNC_END(_save32gpr_24)
FUNC_END(_save32gpr_23)
FUNC_END(_save32gpr_22)
FUNC_END(_save32gpr_21)
FUNC_END(_save32gpr_20)
FUNC_END(_save32gpr_19)
FUNC_END(_save32gpr_18)
FUNC_END(_save32gpr_17)
FUNC_END(_save32gpr_16)
FUNC_END(_save32gpr_15)
FUNC_END(_save32gpr_14)
#endif
|
4ms/metamodule-plugin-sdk
| 2,709
|
plugin-libc/libgcc/config/rs6000/crtsavgpr.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
* 64-bit support written by David Edelsohn
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.section ".text"
#include "ppc-asm.h"
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
/* Routines for saving integer registers, called by the compiler. */
/* Called with r11 pointing to the stack header word of the caller of the */
/* function, just beyond the end of the integer save area. */
CFI_STARTPROC
HIDDEN_FUNC(_savegpr_14) stw 14,-72(11) /* save gp registers */
HIDDEN_FUNC(_savegpr_15) stw 15,-68(11)
HIDDEN_FUNC(_savegpr_16) stw 16,-64(11)
HIDDEN_FUNC(_savegpr_17) stw 17,-60(11)
HIDDEN_FUNC(_savegpr_18) stw 18,-56(11)
HIDDEN_FUNC(_savegpr_19) stw 19,-52(11)
HIDDEN_FUNC(_savegpr_20) stw 20,-48(11)
HIDDEN_FUNC(_savegpr_21) stw 21,-44(11)
HIDDEN_FUNC(_savegpr_22) stw 22,-40(11)
HIDDEN_FUNC(_savegpr_23) stw 23,-36(11)
HIDDEN_FUNC(_savegpr_24) stw 24,-32(11)
HIDDEN_FUNC(_savegpr_25) stw 25,-28(11)
HIDDEN_FUNC(_savegpr_26) stw 26,-24(11)
HIDDEN_FUNC(_savegpr_27) stw 27,-20(11)
HIDDEN_FUNC(_savegpr_28) stw 28,-16(11)
HIDDEN_FUNC(_savegpr_29) stw 29,-12(11)
HIDDEN_FUNC(_savegpr_30) stw 30,-8(11)
HIDDEN_FUNC(_savegpr_31) stw 31,-4(11)
blr
FUNC_END(_savegpr_31)
FUNC_END(_savegpr_30)
FUNC_END(_savegpr_29)
FUNC_END(_savegpr_28)
FUNC_END(_savegpr_27)
FUNC_END(_savegpr_26)
FUNC_END(_savegpr_25)
FUNC_END(_savegpr_24)
FUNC_END(_savegpr_23)
FUNC_END(_savegpr_22)
FUNC_END(_savegpr_21)
FUNC_END(_savegpr_20)
FUNC_END(_savegpr_19)
FUNC_END(_savegpr_18)
FUNC_END(_savegpr_17)
FUNC_END(_savegpr_16)
FUNC_END(_savegpr_15)
FUNC_END(_savegpr_14)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,589
|
plugin-libc/libgcc/config/rs6000/e500crtsavg32gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for saving 32-bit integer registers, called by the compiler. */
/* "GOT" versions that load the address of the GOT into lr before returning. */
HIDDEN_FUNC(_save32gpr_14_g) stw 14,-72(11)
HIDDEN_FUNC(_save32gpr_15_g) stw 15,-68(11)
HIDDEN_FUNC(_save32gpr_16_g) stw 16,-64(11)
HIDDEN_FUNC(_save32gpr_17_g) stw 17,-60(11)
HIDDEN_FUNC(_save32gpr_18_g) stw 18,-56(11)
HIDDEN_FUNC(_save32gpr_19_g) stw 19,-52(11)
HIDDEN_FUNC(_save32gpr_20_g) stw 20,-48(11)
HIDDEN_FUNC(_save32gpr_21_g) stw 21,-44(11)
HIDDEN_FUNC(_save32gpr_22_g) stw 22,-40(11)
HIDDEN_FUNC(_save32gpr_23_g) stw 23,-36(11)
HIDDEN_FUNC(_save32gpr_24_g) stw 24,-32(11)
HIDDEN_FUNC(_save32gpr_25_g) stw 25,-28(11)
HIDDEN_FUNC(_save32gpr_26_g) stw 26,-24(11)
HIDDEN_FUNC(_save32gpr_27_g) stw 27,-20(11)
HIDDEN_FUNC(_save32gpr_28_g) stw 28,-16(11)
HIDDEN_FUNC(_save32gpr_29_g) stw 29,-12(11)
HIDDEN_FUNC(_save32gpr_30_g) stw 30,-8(11)
HIDDEN_FUNC(_save32gpr_31_g) stw 31,-4(11)
b _GLOBAL_OFFSET_TABLE_-4
FUNC_END(_save32gpr_31_g)
FUNC_END(_save32gpr_30_g)
FUNC_END(_save32gpr_29_g)
FUNC_END(_save32gpr_28_g)
FUNC_END(_save32gpr_27_g)
FUNC_END(_save32gpr_26_g)
FUNC_END(_save32gpr_25_g)
FUNC_END(_save32gpr_24_g)
FUNC_END(_save32gpr_23_g)
FUNC_END(_save32gpr_22_g)
FUNC_END(_save32gpr_21_g)
FUNC_END(_save32gpr_20_g)
FUNC_END(_save32gpr_19_g)
FUNC_END(_save32gpr_18_g)
FUNC_END(_save32gpr_17_g)
FUNC_END(_save32gpr_16_g)
FUNC_END(_save32gpr_15_g)
FUNC_END(_save32gpr_14_g)
#endif
|
4ms/metamodule-plugin-sdk
| 2,718
|
plugin-libc/libgcc/config/rs6000/crtresgpr.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
* 64-bit support written by David Edelsohn
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.section ".text"
#include "ppc-asm.h"
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
/* Routines for restoring integer registers, called by the compiler. */
/* Called with r11 pointing to the stack header word of the caller of the */
/* function, just beyond the end of the integer restore area. */
CFI_STARTPROC
HIDDEN_FUNC(_restgpr_14) lwz 14,-72(11) /* restore gp registers */
HIDDEN_FUNC(_restgpr_15) lwz 15,-68(11)
HIDDEN_FUNC(_restgpr_16) lwz 16,-64(11)
HIDDEN_FUNC(_restgpr_17) lwz 17,-60(11)
HIDDEN_FUNC(_restgpr_18) lwz 18,-56(11)
HIDDEN_FUNC(_restgpr_19) lwz 19,-52(11)
HIDDEN_FUNC(_restgpr_20) lwz 20,-48(11)
HIDDEN_FUNC(_restgpr_21) lwz 21,-44(11)
HIDDEN_FUNC(_restgpr_22) lwz 22,-40(11)
HIDDEN_FUNC(_restgpr_23) lwz 23,-36(11)
HIDDEN_FUNC(_restgpr_24) lwz 24,-32(11)
HIDDEN_FUNC(_restgpr_25) lwz 25,-28(11)
HIDDEN_FUNC(_restgpr_26) lwz 26,-24(11)
HIDDEN_FUNC(_restgpr_27) lwz 27,-20(11)
HIDDEN_FUNC(_restgpr_28) lwz 28,-16(11)
HIDDEN_FUNC(_restgpr_29) lwz 29,-12(11)
HIDDEN_FUNC(_restgpr_30) lwz 30,-8(11)
HIDDEN_FUNC(_restgpr_31) lwz 31,-4(11)
blr
FUNC_END(_restgpr_31)
FUNC_END(_restgpr_30)
FUNC_END(_restgpr_29)
FUNC_END(_restgpr_28)
FUNC_END(_restgpr_27)
FUNC_END(_restgpr_26)
FUNC_END(_restgpr_25)
FUNC_END(_restgpr_24)
FUNC_END(_restgpr_23)
FUNC_END(_restgpr_22)
FUNC_END(_restgpr_21)
FUNC_END(_restgpr_20)
FUNC_END(_restgpr_19)
FUNC_END(_restgpr_18)
FUNC_END(_restgpr_17)
FUNC_END(_restgpr_16)
FUNC_END(_restgpr_15)
FUNC_END(_restgpr_14)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 2,630
|
plugin-libc/libgcc/config/rs6000/e500crtsavg64gpr.S
|
/*
* Special support for e500 eabi and SVR4
*
* Copyright (C) 2008-2022 Free Software Foundation, Inc.
* Written by Nathan Froyd
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
.section ".text"
#include "ppc-asm.h"
#ifdef __SPE__
/* Routines for saving 64-bit integer registers, called by the compiler. */
/* "GOT" versions that load the address of the GOT into lr before returning. */
HIDDEN_FUNC(_save64gpr_14_g) evstdd 14,0(11)
HIDDEN_FUNC(_save64gpr_15_g) evstdd 15,8(11)
HIDDEN_FUNC(_save64gpr_16_g) evstdd 16,16(11)
HIDDEN_FUNC(_save64gpr_17_g) evstdd 17,24(11)
HIDDEN_FUNC(_save64gpr_18_g) evstdd 18,32(11)
HIDDEN_FUNC(_save64gpr_19_g) evstdd 19,40(11)
HIDDEN_FUNC(_save64gpr_20_g) evstdd 20,48(11)
HIDDEN_FUNC(_save64gpr_21_g) evstdd 21,56(11)
HIDDEN_FUNC(_save64gpr_22_g) evstdd 22,64(11)
HIDDEN_FUNC(_save64gpr_23_g) evstdd 23,72(11)
HIDDEN_FUNC(_save64gpr_24_g) evstdd 24,80(11)
HIDDEN_FUNC(_save64gpr_25_g) evstdd 25,88(11)
HIDDEN_FUNC(_save64gpr_26_g) evstdd 26,96(11)
HIDDEN_FUNC(_save64gpr_27_g) evstdd 27,104(11)
HIDDEN_FUNC(_save64gpr_28_g) evstdd 28,112(11)
HIDDEN_FUNC(_save64gpr_29_g) evstdd 29,120(11)
HIDDEN_FUNC(_save64gpr_30_g) evstdd 30,128(11)
HIDDEN_FUNC(_save64gpr_31_g) evstdd 31,136(11)
b _GLOBAL_OFFSET_TABLE_-4
FUNC_END(_save64gpr_31_g)
FUNC_END(_save64gpr_30_g)
FUNC_END(_save64gpr_29_g)
FUNC_END(_save64gpr_28_g)
FUNC_END(_save64gpr_27_g)
FUNC_END(_save64gpr_26_g)
FUNC_END(_save64gpr_25_g)
FUNC_END(_save64gpr_24_g)
FUNC_END(_save64gpr_23_g)
FUNC_END(_save64gpr_22_g)
FUNC_END(_save64gpr_21_g)
FUNC_END(_save64gpr_20_g)
FUNC_END(_save64gpr_19_g)
FUNC_END(_save64gpr_18_g)
FUNC_END(_save64gpr_17_g)
FUNC_END(_save64gpr_16_g)
FUNC_END(_save64gpr_15_g)
FUNC_END(_save64gpr_14_g)
#endif
|
4ms/metamodule-plugin-sdk
| 3,731
|
plugin-libc/libgcc/config/rs6000/crtresxfpr.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
* 64-bit support written by David Edelsohn
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.machine ppc
.section ".text"
#include "ppc-asm.h"
/* On PowerPC64 Linux, these functions are provided by the linker. */
#ifndef __powerpc64__
/* Routines for restoring floating point registers, called by the compiler. */
/* Called with r11 pointing to the stack header word of the caller of the */
/* function, just beyond the end of the floating point save area. */
/* In addition to restoring the fp registers, it will return to the caller's */
/* caller */
CFI_STARTPROC
CFI_DEF_CFA_REGISTER (11)
CFI_OFFSET (65, 4)
CFI_OFFSET (46, -144)
CFI_OFFSET (47, -136)
CFI_OFFSET (48, -128)
CFI_OFFSET (49, -120)
CFI_OFFSET (50, -112)
CFI_OFFSET (51, -104)
CFI_OFFSET (52, -96)
CFI_OFFSET (53, -88)
CFI_OFFSET (54, -80)
CFI_OFFSET (55, -72)
CFI_OFFSET (56, -64)
CFI_OFFSET (57, -56)
CFI_OFFSET (58, -48)
CFI_OFFSET (59, -40)
CFI_OFFSET (60, -32)
CFI_OFFSET (61, -24)
CFI_OFFSET (62, -16)
CFI_OFFSET (63, -8)
HIDDEN_FUNC(_restfpr_14_x) lfd 14,-144(11) /* restore fp registers */
CFI_RESTORE (46)
HIDDEN_FUNC(_restfpr_15_x) lfd 15,-136(11)
CFI_RESTORE (47)
HIDDEN_FUNC(_restfpr_16_x) lfd 16,-128(11)
CFI_RESTORE (48)
HIDDEN_FUNC(_restfpr_17_x) lfd 17,-120(11)
CFI_RESTORE (49)
HIDDEN_FUNC(_restfpr_18_x) lfd 18,-112(11)
CFI_RESTORE (50)
HIDDEN_FUNC(_restfpr_19_x) lfd 19,-104(11)
CFI_RESTORE (51)
HIDDEN_FUNC(_restfpr_20_x) lfd 20,-96(11)
CFI_RESTORE (52)
HIDDEN_FUNC(_restfpr_21_x) lfd 21,-88(11)
CFI_RESTORE (53)
HIDDEN_FUNC(_restfpr_22_x) lfd 22,-80(11)
CFI_RESTORE (54)
HIDDEN_FUNC(_restfpr_23_x) lfd 23,-72(11)
CFI_RESTORE (55)
HIDDEN_FUNC(_restfpr_24_x) lfd 24,-64(11)
CFI_RESTORE (56)
HIDDEN_FUNC(_restfpr_25_x) lfd 25,-56(11)
CFI_RESTORE (57)
HIDDEN_FUNC(_restfpr_26_x) lfd 26,-48(11)
CFI_RESTORE (58)
HIDDEN_FUNC(_restfpr_27_x) lfd 27,-40(11)
CFI_RESTORE (59)
HIDDEN_FUNC(_restfpr_28_x) lfd 28,-32(11)
CFI_RESTORE (60)
HIDDEN_FUNC(_restfpr_29_x) lfd 29,-24(11)
CFI_RESTORE (61)
HIDDEN_FUNC(_restfpr_30_x) lfd 30,-16(11)
CFI_RESTORE (62)
HIDDEN_FUNC(_restfpr_31_x) lwz 0,4(11)
lfd 31,-8(11)
CFI_RESTORE (63)
mtlr 0
CFI_RESTORE (65)
mr 1,11
CFI_DEF_CFA_REGISTER (1)
blr
FUNC_END(_restfpr_31_x)
FUNC_END(_restfpr_30_x)
FUNC_END(_restfpr_29_x)
FUNC_END(_restfpr_28_x)
FUNC_END(_restfpr_27_x)
FUNC_END(_restfpr_26_x)
FUNC_END(_restfpr_25_x)
FUNC_END(_restfpr_24_x)
FUNC_END(_restfpr_23_x)
FUNC_END(_restfpr_22_x)
FUNC_END(_restfpr_21_x)
FUNC_END(_restfpr_20_x)
FUNC_END(_restfpr_19_x)
FUNC_END(_restfpr_18_x)
FUNC_END(_restfpr_17_x)
FUNC_END(_restfpr_16_x)
FUNC_END(_restfpr_15_x)
FUNC_END(_restfpr_14_x)
CFI_ENDPROC
#endif
|
4ms/metamodule-plugin-sdk
| 1,985
|
plugin-libc/libgcc/config/rs6000/sol-cn.S
|
# crtn.s for sysv4
# Copyright (C) 1996-2022 Free Software Foundation, Inc.
# Written By Michael Meissner
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just supplies labeled ending points for the .got* and other
# special sections. It is linked in last after other modules.
.ident "GNU C scrtn.s"
#ifndef __powerpc64__
# Default versions of exception handling register/deregister
.weak _ex_register
.weak _ex_deregister
.set _ex_register,0
.set _ex_deregister,0
# End list of C++ constructors
.section ".ctors","aw"
.globl __CTOR_END__
.type __CTOR_END__,@object
__CTOR_END__:
# End list of C++ destructors
.section ".dtors","aw"
.weak __DTOR_END__
.type __DTOR_END__,@object
__DTOR_END__:
.section ".text"
.globl _ex_text1
_ex_text1:
.section ".exception_ranges","aw"
.globl _ex_range1
_ex_range1:
# Tail of _init used for static constructors
.section ".init","ax"
lwz %r0,16(%r1)
lwz %r31,12(%r1)
mtlr %r0
addi %r1,%r1,16
blr
# Tail of _fini used for static destructors
.section ".fini","ax"
lwz %r0,16(%r1)
lwz %r31,12(%r1)
mtlr %r0
addi %r1,%r1,16
blr
#endif
|
4ms/metamodule-plugin-sdk
| 9,007
|
plugin-libc/libgcc/config/rs6000/eabi.S
|
/*
* Special support for eabi and SVR4
*
* Copyright (C) 1995-2022 Free Software Foundation, Inc.
* Written By Michael Meissner
*
* This file is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 3, or (at your option) any
* later version.
*
* This file is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* Under Section 7 of GPL version 3, you are granted additional
* permissions described in the GCC Runtime Library Exception, version
* 3.1, as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License and
* a copy of the GCC Runtime Library Exception along with this program;
* see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
* <http://www.gnu.org/licenses/>.
*/
/* Do any initializations needed for the eabi environment */
.section ".text"
#include "ppc-asm.h"
#ifndef __powerpc64__
.section ".got2","aw"
.align 2
.LCTOC1 = . /* +32768 */
/* Table of addresses */
.Ltable = .-.LCTOC1
.long .LCTOC1 /* address we are really at */
.Lsda = .-.LCTOC1
.long _SDA_BASE_ /* address of the first small data area */
.Lsdas = .-.LCTOC1
.long __SDATA_START__ /* start of .sdata/.sbss section */
.Lsdae = .-.LCTOC1
.long __SBSS_END__ /* end of .sdata/.sbss section */
.Lsda2 = .-.LCTOC1
.long _SDA2_BASE_ /* address of the second small data area */
.Lsda2s = .-.LCTOC1
.long __SDATA2_START__ /* start of .sdata2/.sbss2 section */
.Lsda2e = .-.LCTOC1
.long __SBSS2_END__ /* end of .sdata2/.sbss2 section */
#ifdef _RELOCATABLE
.Lgots = .-.LCTOC1
.long __GOT_START__ /* Global offset table start */
.Lgotm1 = .-.LCTOC1
.long _GLOBAL_OFFSET_TABLE_-4 /* end of GOT ptrs before BLCL + 3 reserved words */
.Lgotm2 = .-.LCTOC1
.long _GLOBAL_OFFSET_TABLE_+12 /* start of GOT ptrs after BLCL + 3 reserved words */
.Lgote = .-.LCTOC1
.long __GOT_END__ /* Global offset table end */
.Lgot2s = .-.LCTOC1
.long __GOT2_START__ /* -mrelocatable GOT pointers start */
.Lgot2e = .-.LCTOC1
.long __GOT2_END__ /* -mrelocatable GOT pointers end */
.Lfixups = .-.LCTOC1
.long __FIXUP_START__ /* start of .fixup section */
.Lfixupe = .-.LCTOC1
.long __FIXUP_END__ /* end of .fixup section */
.Lctors = .-.LCTOC1
.long __CTOR_LIST__ /* start of .ctor section */
.Lctore = .-.LCTOC1
.long __CTOR_END__ /* end of .ctor section */
.Ldtors = .-.LCTOC1
.long __DTOR_LIST__ /* start of .dtor section */
.Ldtore = .-.LCTOC1
.long __DTOR_END__ /* end of .dtor section */
.Lexcepts = .-.LCTOC1
.long __EXCEPT_START__ /* start of .gcc_except_table section */
.Lexcepte = .-.LCTOC1
.long __EXCEPT_END__ /* end of .gcc_except_table section */
.Linit = .-.LCTOC1
.long .Linit_p /* address of variable to say we've been called */
.text
.align 2
.Lptr:
.long .LCTOC1-.Laddr /* PC relative pointer to .got2 */
#endif
.data
.align 2
.Linit_p:
.long 0
.text
FUNC_START(__eabi)
/* Eliminate -mrelocatable code if not -mrelocatable, so that this file can
be assembled with other assemblers than GAS. */
#ifndef _RELOCATABLE
addis 10,0,.Linit_p@ha /* init flag */
addis 11,0,.LCTOC1@ha /* load address of .LCTOC1 */
lwz 9,.Linit_p@l(10) /* init flag */
addi 11,11,.LCTOC1@l
cmplwi 2,9,0 /* init flag != 0? */
bnelr 2 /* return now, if we've been called already */
stw 1,.Linit_p@l(10) /* store a nonzero value in the done flag */
#else /* -mrelocatable */
mflr 0
bl .Laddr /* get current address */
.Laddr:
mflr 12 /* real address of .Laddr */
lwz 11,(.Lptr-.Laddr)(12) /* linker generated address of .LCTOC1 */
add 11,11,12 /* correct to real pointer */
lwz 12,.Ltable(11) /* get linker's idea of where .Laddr is */
lwz 10,.Linit(11) /* address of init flag */
subf. 12,12,11 /* calculate difference */
lwzx 9,10,12 /* done flag */
cmplwi 2,9,0 /* init flag != 0? */
mtlr 0 /* restore in case branch was taken */
bnelr 2 /* return now, if we've been called already */
stwx 1,10,12 /* store a nonzero value in the done flag */
beq+ 0,.Lsdata /* skip if we don't need to relocate */
/* We need to relocate the .got2 pointers. */
lwz 3,.Lgot2s(11) /* GOT2 pointers start */
lwz 4,.Lgot2e(11) /* GOT2 pointers end */
add 3,12,3 /* adjust pointers */
add 4,12,4
bl FUNC_NAME(__eabi_convert) /* convert pointers in .got2 section */
/* Fixup the .ctor section for static constructors */
lwz 3,.Lctors(11) /* constructors pointers start */
lwz 4,.Lctore(11) /* constructors pointers end */
bl FUNC_NAME(__eabi_convert) /* convert constructors */
/* Fixup the .dtor section for static destructors */
lwz 3,.Ldtors(11) /* destructors pointers start */
lwz 4,.Ldtore(11) /* destructors pointers end */
bl FUNC_NAME(__eabi_convert) /* convert destructors */
/* Fixup the .gcc_except_table section for G++ exceptions */
lwz 3,.Lexcepts(11) /* exception table pointers start */
lwz 4,.Lexcepte(11) /* exception table pointers end */
bl FUNC_NAME(__eabi_convert) /* convert exceptions */
/* Fixup the addresses in the GOT below _GLOBAL_OFFSET_TABLE_-4 */
lwz 3,.Lgots(11) /* GOT table pointers start */
lwz 4,.Lgotm1(11) /* GOT table pointers below _GLOBAL_OFFSET_TABLE-4 */
bl FUNC_NAME(__eabi_convert) /* convert lower GOT */
/* Fixup the addresses in the GOT above _GLOBAL_OFFSET_TABLE_+12 */
lwz 3,.Lgotm2(11) /* GOT table pointers above _GLOBAL_OFFSET_TABLE+12 */
lwz 4,.Lgote(11) /* GOT table pointers end */
bl FUNC_NAME(__eabi_convert) /* convert lower GOT */
/* Fixup any user initialized pointers now (the compiler drops pointers to */
/* each of the relocs that it does in the .fixup section). */
.Lfix:
lwz 3,.Lfixups(11) /* fixup pointers start */
lwz 4,.Lfixupe(11) /* fixup pointers end */
bl FUNC_NAME(__eabi_uconvert) /* convert user initialized pointers */
.Lsdata:
mtlr 0 /* restore link register */
#endif /* _RELOCATABLE */
/* Only load up register 13 if there is a .sdata and/or .sbss section */
lwz 3,.Lsdas(11) /* start of .sdata/.sbss section */
lwz 4,.Lsdae(11) /* end of .sdata/.sbss section */
cmpw 1,3,4 /* .sdata/.sbss section non-empty? */
beq- 1,.Lsda2l /* skip loading r13 */
lwz 13,.Lsda(11) /* load r13 with _SDA_BASE_ address */
/* Only load up register 2 if there is a .sdata2 and/or .sbss2 section */
.Lsda2l:
lwz 3,.Lsda2s(11) /* start of .sdata/.sbss section */
lwz 4,.Lsda2e(11) /* end of .sdata/.sbss section */
cmpw 1,3,4 /* .sdata/.sbss section non-empty? */
beq+ 1,.Ldone /* skip loading r2 */
lwz 2,.Lsda2(11) /* load r2 with _SDA2_BASE_ address */
/* Done adjusting pointers, return by way of doing the C++ global constructors. */
.Ldone:
b FUNC_NAME(__init) /* do any C++ global constructors (which returns to caller) */
FUNC_END(__eabi)
/* Special subroutine to convert a bunch of pointers directly.
r0 has original link register
r3 has low pointer to convert
r4 has high pointer to convert
r5 .. r10 are scratch registers
r11 has the address of .LCTOC1 in it.
r12 has the value to add to each pointer
r13 .. r31 are unchanged */
#ifdef _RELOCATABLE
FUNC_START(__eabi_convert)
cmplw 1,3,4 /* any pointers to convert? */
subf 5,3,4 /* calculate number of words to convert */
bclr 4,4 /* return if no pointers */
srawi 5,5,2
addi 3,3,-4 /* start-4 for use with lwzu */
mtctr 5
.Lcvt:
lwzu 6,4(3) /* pointer to convert */
cmpwi 0,6,0
beq- .Lcvt2 /* if pointer is null, don't convert */
add 6,6,12 /* convert pointer */
stw 6,0(3)
.Lcvt2:
bdnz+ .Lcvt
blr
FUNC_END(__eabi_convert)
/* Special subroutine to convert the pointers the user has initialized. The
compiler has placed the address of the initialized pointer into the .fixup
section.
r0 has original link register
r3 has low pointer to convert
r4 has high pointer to convert
r5 .. r10 are scratch registers
r11 has the address of .LCTOC1 in it.
r12 has the value to add to each pointer
r13 .. r31 are unchanged */
FUNC_START(__eabi_uconvert)
cmplw 1,3,4 /* any pointers to convert? */
subf 5,3,4 /* calculate number of words to convert */
bclr 4,4 /* return if no pointers */
srawi 5,5,2
addi 3,3,-4 /* start-4 for use with lwzu */
mtctr 5
.Lucvt:
lwzu 6,4(3) /* next pointer to pointer to convert */
add 6,6,12 /* adjust pointer */
lwz 7,0(6) /* get the pointer it points to */
stw 6,0(3) /* store adjusted pointer */
add 7,7,12 /* adjust */
stw 7,0(6)
bdnz+ .Lucvt
blr
FUNC_END(__eabi_uconvert)
#endif
#endif
|
4ms/metamodule-plugin-sdk
| 1,235
|
plugin-libc/libgcc/config/alpha/vms-dwarf2eh.S
|
/* VMS dwarf2 exception handling section sequentializer.
Copyright (C) 2002-2022 Free Software Foundation, Inc.
Contributed by Douglas B. Rupp (rupp@gnat.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Linking with this file forces the Dwarf2 EH section to be
individually loaded by the VMS linker an the unwinder to read it. */
.section .eh_frame,NOWRT
.align 0
|
4ms/metamodule-plugin-sdk
| 3,225
|
plugin-libc/libgcc/config/alpha/qrnnd.S
|
# Alpha 21064 __udiv_qrnnd
# Copyright (C) 1992-2022 Free Software Foundation, Inc.
# This file is part of GCC.
# The GNU MP Library is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 3 of the License, or (at your
# option) any later version.
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public
# License for more details.
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
#ifdef __ELF__
.section .note.GNU-stack,""
#endif
.set noreorder
.set noat
.text
.globl __udiv_qrnnd
.ent __udiv_qrnnd
#ifdef __VMS__
__udiv_qrnnd..en:
.frame $29,0,$26,0
.prologue
#else
__udiv_qrnnd:
.frame $30,0,$26,0
.prologue 0
#endif
#define cnt $2
#define tmp $3
#define rem_ptr $16
#define n1 $17
#define n0 $18
#define d $19
#define qb $20
#define AT $at
ldiq cnt,16
blt d,$largedivisor
$loop1: cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule d,n1,qb
subq n1,d,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule d,n1,qb
subq n1,d,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule d,n1,qb
subq n1,d,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule d,n1,qb
subq n1,d,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
subq cnt,1,cnt
bgt cnt,$loop1
stq n1,0(rem_ptr)
bis $31,n0,$0
ret $31,($26),1
$largedivisor:
and n0,1,$4
srl n0,1,n0
sll n1,63,tmp
or tmp,n0,n0
srl n1,1,n1
and d,1,$6
srl d,1,$5
addq $5,$6,$5
$loop2: cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule $5,n1,qb
subq n1,$5,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule $5,n1,qb
subq n1,$5,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule $5,n1,qb
subq n1,$5,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
cmplt n0,0,tmp
addq n1,n1,n1
bis n1,tmp,n1
addq n0,n0,n0
cmpule $5,n1,qb
subq n1,$5,tmp
cmovne qb,tmp,n1
bis n0,qb,n0
subq cnt,1,cnt
bgt cnt,$loop2
addq n1,n1,n1
addq $4,n1,n1
bne $6,$Odd
stq n1,0(rem_ptr)
bis $31,n0,$0
ret $31,($26),1
$Odd:
/* q' in n0. r' in n1 */
addq n1,n0,n1
cmpult n1,n0,tmp # tmp := carry from addq
subq n1,d,AT
addq n0,tmp,n0
cmovne tmp,AT,n1
cmpult n1,d,tmp
addq n0,1,AT
cmoveq tmp,AT,n0
subq n1,d,AT
cmoveq tmp,AT,n1
stq n1,0(rem_ptr)
bis $31,n0,$0
ret $31,($26),1
#ifdef __VMS__
.link
.align 3
__udiv_qrnnd:
.pdesc __udiv_qrnnd..en,null
#endif
.end __udiv_qrnnd
|
4ms/metamodule-plugin-sdk
| 2,113
|
plugin-libc/libgcc/config/alpha/vms-dwarf2.S
|
/* VMS dwarf2 section sequentializer.
Copyright (C) 2001-2022 Free Software Foundation, Inc.
Contributed by Douglas B. Rupp (rupp@gnat.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* Linking with this file forces Dwarf2 debug sections to be
sequentially loaded by the VMS linker, enabling GDB to read them. */
.section .debug_abbrev,NOWRT
.align 0
.globl $dwarf2.debug_abbrev
$dwarf2.debug_abbrev:
.section .debug_aranges,NOWRT
.align 0
.globl $dwarf2.debug_aranges
$dwarf2.debug_aranges:
.section .debug_frame,NOWRT
.align 0
.globl $dwarf2.debug_frame
$dwarf2.debug_frame:
.section .debug_info,NOWRT
.align 0
.globl $dwarf2.debug_info
$dwarf2.debug_info:
.section .debug_line,NOWRT
.align 0
.globl $dwarf2.debug_line
$dwarf2.debug_line:
.section .debug_loc,NOWRT
.align 0
.globl $dwarf2.debug_loc
$dwarf2.debug_loc:
.section .debug_macinfo,NOWRT
.align 0
.globl $dwarf2.debug_macinfo
$dwarf2.debug_macinfo:
.section .debug_pubnames,NOWRT
.align 0
.globl $dwarf2.debug_pubnames
$dwarf2.debug_pubnames:
.section .debug_str,NOWRT
.align 0
.globl $dwarf2.debug_str
$dwarf2.debug_str:
.section .debug_zzzzzz,NOWRT
.align 0
.globl $dwarf2.debug_zzzzzz
$dwarf2.debug_zzzzzz:
|
4ms/metamodule-plugin-sdk
| 1,541
|
plugin-libc/libgcc/config/bfin/crtn.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
* This file supplies function epilogues for the .init and .fini sections.
* It is linked in after all other files.
*/
.ident "GNU C crtn.o"
.section .init
unlink;
#if defined __ID_SHARED_LIB__
P5 = [SP++];
#elif defined __BFIN_FDPIC__
P3 = [SP++];
#endif
rts;
.section .fini
unlink;
#if defined __ID_SHARED_LIB__
P5 = [SP++];
#elif defined __BFIN_FDPIC__
P3 = [SP++];
#endif
rts;
|
4ms/metamodule-plugin-sdk
| 1,168
|
plugin-libc/libgcc/config/bfin/crtlibid.S
|
/* Provide a weak definition of the library ID, for the benefit of certain
configure scripts.
Copyright (C) 2005-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.ident "GNU C crtlibid.o"
.weak _current_shared_library_p5_offset_
.set _current_shared_library_p5_offset_, 0
|
4ms/metamodule-plugin-sdk
| 1,807
|
plugin-libc/libgcc/config/bfin/crti.S
|
/* Specialized code needed to support construction and destruction of
file-scope objects in C++ and Java code, and to support exception handling.
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/*
* This file just supplies function prologues for the .init and .fini
* sections. It is linked in before crtbegin.o.
*/
.ident "GNU C crti.o"
.section .init
.globl __init
.type __init,@function
__init:
#if defined __ID_SHARED_LIB__
[--SP] = P5;
#elif defined __BFIN_FDPIC__
[--SP] = P3;
#endif
LINK 12;
#if defined __ID_SHARED_LIB__
P5 = [P5 + _current_shared_library_p5_offset_]
#endif
.section .fini
.globl __fini
.type __fini,@function
__fini:
#if defined __ID_SHARED_LIB__
[--SP] = P5;
#elif defined __BFIN_FDPIC__
[--SP] = P3;
#endif
LINK 12;
#if defined __ID_SHARED_LIB__
P5 = [P5 + _current_shared_library_p5_offset_]
#endif
|
4ms/metamodule-plugin-sdk
| 5,125
|
plugin-libc/libgcc/config/bfin/lib1funcs.S
|
/* libgcc functions for Blackfin.
Copyright (C) 2005-2022 Free Software Foundation, Inc.
Contributed by Analog Devices.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifdef L_divsi3
.text
.align 2
.global ___divsi3;
.type ___divsi3, STT_FUNC;
___divsi3:
[--SP]= RETS;
[--SP] = R7;
R2 = -R0;
CC = R0 < 0;
IF CC R0 = R2;
R7 = CC;
R2 = -R1;
CC = R1 < 0;
IF CC R1 = R2;
R2 = CC;
R7 = R7 ^ R2;
CALL ___udivsi3;
CC = R7;
R1 = -R0;
IF CC R0 = R1;
R7 = [SP++];
RETS = [SP++];
RTS;
#endif
#ifdef L_modsi3
.align 2
.global ___modsi3;
.type ___modsi3, STT_FUNC;
___modsi3:
[--SP] = RETS;
[--SP] = R0;
[--SP] = R1;
CALL ___divsi3;
R2 = [SP++];
R1 = [SP++];
R2 *= R0;
R0 = R1 - R2;
RETS = [SP++];
RTS;
#endif
#ifdef L_udivsi3
.align 2
.global ___udivsi3;
.type ___udivsi3, STT_FUNC;
___udivsi3:
P0 = 32;
LSETUP (0f, 1f) LC0 = P0;
/* upper half of dividend */
R3 = 0;
0:
/* The first time round in the loop we shift in garbage, but since we
perform 33 shifts, it doesn't matter. */
R0 = ROT R0 BY 1;
R3 = ROT R3 BY 1;
R2 = R3 - R1;
CC = R3 < R1 (IU);
1:
/* Last instruction of the loop. */
IF ! CC R3 = R2;
/* Shift in the last bit. */
R0 = ROT R0 BY 1;
/* R0 is the result, R3 contains the remainder. */
R0 = ~ R0;
RTS;
#endif
#ifdef L_umodsi3
.align 2
.global ___umodsi3;
.type ___umodsi3, STT_FUNC;
___umodsi3:
[--SP] = RETS;
CALL ___udivsi3;
R0 = R3;
RETS = [SP++];
RTS;
#endif
#ifdef L_umulsi3_highpart
.align 2
.global ___umulsi3_highpart;
.type ___umulsi3_highpart, STT_FUNC;
___umulsi3_highpart:
A1 = R1.L * R0.L (FU);
A1 = A1 >> 16;
A0 = R1.H * R0.H, A1 += R1.L * R0.H (FU);
A1 += R0.L * R1.H (FU);
A1 = A1 >> 16;
A0 += A1;
R0 = A0 (FU);
RTS;
#endif
#ifdef L_smulsi3_highpart
.align 2
.global ___smulsi3_highpart;
.type ___smulsi3_highpart, STT_FUNC;
___smulsi3_highpart:
A1 = R1.L * R0.L (FU);
A1 = A1 >> 16;
A0 = R0.H * R1.H, A1 += R0.H * R1.L (IS,M);
A1 += R1.H * R0.L (IS,M);
A1 = A1 >>> 16;
R0 = (A0 += A1);
RTS;
#endif
#ifdef L_muldi3
.align 2
.global ___muldi3;
.type ___muldi3, STT_FUNC;
/*
R1:R0 * R3:R2
= R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
[X] = (R1.h * R3.h) * 2^96
[X] + (R1.h * R3.l + R1.l * R3.h) * 2^80
[X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
[T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
[T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
[T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
[T4] + (R0.l * R2.l)
We can discard the first three lines marked "X" since we produce
only a 64 bit result. So, we need ten 16-bit multiplies.
Individual mul-acc results:
[E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
[E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
[E3] = R0.l * R2.h + R2.l * R0.h
[E4] = R0.l * R2.l
We also need to add high parts from lower-level results to higher ones:
E[n]c = E[n] + (E[n+1]c >> 16), where E4c := E4
One interesting property is that all parts of the result that depend
on the sign of the multiplication are discarded. Those would be the
multiplications involving R1.h and R3.h, but only the top 16 bit of
the 32 bit result depend on the sign, and since R1.h and R3.h only
occur in E1, the top half of these results is cut off.
So, we can just use FU mode for all of the 16-bit multiplies, and
ignore questions of when to use mixed mode. */
___muldi3:
/* [SP] technically is part of the caller's frame, but we can
use it as scratch space. */
A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
A0 += R3.H * R0.L, A1 += R3.L * R0.H (FU) || [SP] = R4; /* E1 */
A0 += A1; /* E1 */
R4 = A0.w;
A0 = R0.l * R3.l (FU); /* E2 */
A0 += R2.l * R1.l (FU); /* E2 */
A1 = R2.L * R0.L (FU); /* E4 */
R3 = A1.w;
A1 = A1 >> 16; /* E3c */
A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
A1 += R0.L * R2.H (FU); /* E3c */
R0 = A1.w;
A1 = A1 >> 16; /* E2c */
A0 += A1; /* E2c */
R1 = A0.w;
/* low(result) = low(E3c):low(E4) */
R0 = PACK (R0.l, R3.l);
/* high(result) = E2c + (E1 << 16) */
R1.h = R1.h + R4.l (NS) || R4 = [SP];
RTS;
.size ___muldi3, .-___muldi3
#endif
|
4ms/metamodule-plugin-sdk
| 1,265
|
plugin-libc/libgcc/config/ft32/crtn.S
|
# crtn.S for FT32
#
# Copyright (C) 2009-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just makes sure that the .fini and .init sections do in
# fact return. Users may put any desired instructions in those sections.
# This file is the last thing linked into any executable.
.file "crtn.S"
.section ".init"
return
.section ".fini"
return
|
4ms/metamodule-plugin-sdk
| 4,749
|
plugin-libc/libgcc/config/ft32/crti-hw.S
|
.global _start
_start:
# START Interrupt Vector Table [[
jmp __PMSIZE-4 # RESET Vector
jmp interrupt_33 # Watchdog reset vector
jmp interrupt_0
jmp interrupt_1
jmp interrupt_2
jmp interrupt_3
jmp interrupt_4
jmp interrupt_5
jmp interrupt_6
jmp interrupt_7
jmp interrupt_8
jmp interrupt_9
jmp interrupt_10
jmp interrupt_11
jmp interrupt_12
jmp interrupt_13
jmp interrupt_14
jmp interrupt_15
jmp interrupt_16
jmp interrupt_17
jmp interrupt_18
jmp interrupt_19
jmp interrupt_20
jmp interrupt_21
jmp interrupt_22
jmp interrupt_23
jmp interrupt_24
jmp interrupt_25
jmp interrupt_26
jmp interrupt_27
jmp interrupt_28
jmp interrupt_29
jmp interrupt_30
jmp interrupt_31
jmp __PMSIZE-8 # Interrupt vector 32 (NMI)
# ]] END Interrupt Vector Table
codestart:
jmp init
.global _exithook
_exithook: # Debugger uses '_exithook' at 0x90 to catch program exit
return
init:
ldk $sp,__RAMSIZE
# Disable all interrupts
lda $r1,0x10000
lshr $r1,$r1,20
cmp $r1,0x90
ldk $r1,0x100e3 # FT900 IRQ Control Register
jmpc z,1f
ldk $r1,0x10123 # FT930 IRQ Control Register
1:
ldk $r4,0x80
sti.b $r1,0,$r4
# Initialize DATA by copying from program memory
ldk.l $r4,__data_load_start
ldk.l $r1,__data_load_end
ldk.l $r2,0 # Will use __data after binutils patch
jmp .dscopy
.dsloop:
# Copy PM[$r4] to RAM $r2
lpmi.l $r3,$r4,0
sti.l $r2,0,$r3
add.l $r4,$r4,4
add.l $r2,$r2,4
.dscopy:
cmp.l $r4,$r1
jmpc lt,.dsloop
# Zero BSS
ldk.l $r4,_bss_start
ldk.l $r2,_end
sub.l $r2,$r2,$r4
ldk.l $r1,0
ldk $r3,32764
1:
cmp $r2,$r3
jmpc lt,2f
memset $r4,$r1,$r3
add $r4,$r4,$r3
sub $r2,$r2,$r3
jmp 1b
2:
memset $r4,$r1,$r2
sub.l $sp,$sp,24 # Space for the caller argument frame
call main
.equ EXITEXIT,0x1fffc
.global _exit
_exit:
sta.l EXITEXIT,$r0 # simulator end of test
jmp _exithook
# Macro to construct the interrupt stub code.
# it just saves r0, loads r0 with the int vector
# and branches to interrupt_common.
.macro inth i=0
interrupt_\i:
push $r0 # {
lda $r0,(vector_table + 4 * \i)
jmp interrupt_common
.endm
inth 0
inth 1
inth 2
inth 3
inth 4
inth 5
inth 6
inth 7
inth 8
inth 9
inth 10
inth 11
inth 12
inth 13
inth 14
inth 15
inth 16
inth 17
inth 18
inth 19
inth 20
inth 21
inth 22
inth 23
inth 24
inth 25
inth 26
inth 27
inth 28
inth 29
inth 30
inth 31
inth 32
inth 33
# On entry: r0, already saved, holds the handler function
interrupt_common:
push $r1 # {
push $r2 # {
push $r3 # {
push $r4 # {
push $r5 # {
push $r6 # {
push $r7 # {
push $r8 # {
push $r9 # {
push $r10 # {
push $r11 # {
push $r12 # {
push $cc # {
calli $r0
pop $cc # }
pop $r12 # }
pop $r11 # }
pop $r10 # }
pop $r9 # }
pop $r8 # }
pop $r7 # }
pop $r6 # }
pop $r5 # }
pop $r4 # }
pop $r3 # }
pop $r2 # }
pop $r1 # }
pop $r0 # } matching push in interrupt_0-31 above
reti
# Null function for unassigned interrupt to point at
.global nullvector
nullvector:
return
.section .data
.global vector_table
vector_table:
.rept 34
.long nullvector
.endr
.section .text
.global __gxx_personality_sj0
__gxx_personality_sj0:
|
4ms/metamodule-plugin-sdk
| 1,313
|
plugin-libc/libgcc/config/ft32/crti.S
|
# crti.S for FT32
#
# Copyright (C) 2009-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file just make a stack frame for the contents of the .fini and
# .init sections. Users may put any desired instructions in those
# sections.
.file "crti.S"
.section ".init"
.global _init
.type _init, @function
.p2align 2
_init:
.section ".fini"
.global _fini
.type _fini,@function
.p2align 2
_fini:
|
4ms/metamodule-plugin-sdk
| 4,023
|
plugin-libc/libgcc/config/ft32/prolog.S
|
.global __prolog_$r13
__prolog_$r13:
exi $r13,$sp,0
jmpi $r13
.global __prolog_$r14
__prolog_$r14:
exi $r13,$sp,0
push $r14
jmpi $r13
.global __prolog_$r15
__prolog_$r15:
exi $r13,$sp,0
push $r14
push $r15
jmpi $r13
.global __prolog_$r16
__prolog_$r16:
exi $r13,$sp,0
push $r14
push $r15
push $r16
jmpi $r13
.global __prolog_$r17
__prolog_$r17:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
jmpi $r13
.global __prolog_$r18
__prolog_$r18:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
jmpi $r13
.global __prolog_$r19
__prolog_$r19:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
jmpi $r13
.global __prolog_$r20
__prolog_$r20:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
jmpi $r13
.global __prolog_$r21
__prolog_$r21:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
jmpi $r13
.global __prolog_$r22
__prolog_$r22:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
jmpi $r13
.global __prolog_$r23
__prolog_$r23:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
jmpi $r13
.global __prolog_$r24
__prolog_$r24:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
jmpi $r13
.global __prolog_$r25
__prolog_$r25:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
jmpi $r13
.global __prolog_$r26
__prolog_$r26:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
push $r26
jmpi $r13
.global __prolog_$r27
__prolog_$r27:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
push $r26
push $r27
jmpi $r13
.global __prolog_$r28
__prolog_$r28:
exi $r13,$sp,0
push $r14
push $r15
push $r16
push $r17
push $r18
push $r19
push $r20
push $r21
push $r22
push $r23
push $r24
push $r25
push $r26
push $r27
push $r28
jmpi $r13
|
4ms/metamodule-plugin-sdk
| 25,241
|
plugin-libc/libgcc/config/ft32/lib1funcs.S
|
# ieee754 sf routines for FT32
/* Copyright (C) 1995-2022 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
# See http://www.ens-lyon.fr/LIP/Pub/Rapports/PhD/PhD2006/PhD2006-02.pdf
# for implementation details of all except division which is detailed below
#
#ifdef L_fp_tools
// .global __cmpsf2_
nan: .long 0x7FFFFFFF # also abs mask
inf: .long 0x7F800000
sign_mask: .long 0x80000000
m_mask: .long 0x007FFFFF
exp_bias: .long 127
edge_case: .long 0x00FFFFFF
smallest_norm: .long 0x00800000 # implicit bit
high_FF: .long 0xFF000000
high_uint: .long 0xFFFFFFFF
ntz_table:
.byte 32,0,1,12,2,6,0,13,3,0,7,0,0,0,0,14
.byte 10,4,0,0,8,0,0,25,0,0,0,0,0,21,27,15
.byte 31,11,5,0,0,0,0,0,9,0,0,24,0,0,20,26
.byte 30,0,0,0,0,23,0,19,29,0,22,18,28,17,16,0
#endif
# Supply a few 'missing' instructions
# not
.macro not rd,r1
xor \rd,\r1,-1
.endm
# negate
.macro neg x
not \x, \x
add \x, \x, 1
.endm
# set $cc from the result of "ashl reg,dist"
.macro ashlcc reg,dist
.long 0x5de04008 | (\reg << 15) | (\dist << 4)
.endm
# converts an unsigned number x to a signed rep based on the bits in sign
# sign should be 0x00000000 or 0xffffffff.
.macro to_signed x, sign
add \x,\x,\sign # conditionally decrement x
xor \x,\x,\sign # conditionally complement x
.endm
.macro ld32 r,v
ldk \r,(\v>>10)
ldl \r,\r,(\v & 1023)
.endm
# calculate trailing zero count in x, also uses scr.
# Using Seal's algorithm
.macro ntz x, scr
not \scr, \x
add \scr, \scr, 1
and \x, \x, \scr
ashl \scr, \x, 4
add \x, \scr, \x
ashl \scr, \x, 6
add \x, \scr, \x
ashl \scr, \x, 16
sub \x, \scr, \x
lshr \x, \x, 26
ldk \scr, ntz_table
add \x, \x, \scr
lpmi.b \x, \x, 0
.endm
# calculate leading zero count
.macro nlz x, scr
flip \x, \x, 31
ntz \x, \scr
.endm
# Round 26 bit mantissa to nearest
# | 23 bits frac | G | R | S |
.macro round m, s1, s2
ldk \s1,0xc8
and \s2,\m,7
lshr \s1,\s1,\s2
and \s1,\s1,1
lshr \m,\m,2
add \m,\m,\s1
.endm
# If NZ, set the LSB of reg
.macro sticky reg
jmpc z,1f
or \reg,\reg,1 # set the sticky bit to 1
1:
.endm
##########################################################################
##########################################################################
## addition & subtraction
#if defined(L_subsf3) || defined(L_addsub_sf)
.global __subsf3
__subsf3:
# this is subtraction, so we just change the sign of r1
lpm $r2,sign_mask
xor $r1,$r1,$r2
jmp __addsf3
#endif
#if defined(L_addsf3) || defined(L_addsub_sf)
.global __addsf3
__addsf3:
# x in $r0, y in $r1, result z in $r0 --||| 100 instructions +/- |||--
# unpack e, calc d
bextu $r2,$r0,(8<<5)|23 # ex in r2
bextu $r3,$r1,(8<<5)|23 # ey in r3
sub $r5,$r2,$r3 # d = ex - ey
# Special values are 0x00 and 0xff in ex and ey.
# If (ex&ey) != 0 or (xy|ey)=255 then there may be
# a special value.
tst $r2,$r3
jmpc nz,1f
jmp slow
1: or $r4,$r2,$r3
cmp $r4,255
jmpc nz,no_special_vals
slow:
# Check for early exit
cmp $r2,0
jmpc z,test_if_not_255
cmp $r3,0
jmpc nz,no_early_exit
test_if_not_255:
cmp $r2,255
jmpc z,no_early_exit
cmp $r3,255
jmpc z,no_early_exit
or $r6,$r2,$r3
cmp $r6,0
jmpc nz,was_not_zero
and $r0,$r0,$r1
lpm $r1,sign_mask
and $r0,$r0,$r1
return
was_not_zero:
cmp $r2,0
jmpc nz,ret_x
move $r0,$r1
return
ret_x:
return
no_early_exit:
# setup to test for special values
sub $r6,$r2,1
and $r6,$r6,0xFE
sub $r7,$r3,1
and $r7,$r7,0xFE
# test for special values
cmp $r6,$r7
jmpc gte,ex_spec_is_gte
move $r6,$r7
ex_spec_is_gte:
cmp $r6,0xFE
jmpc nz,no_special_vals
cmp $r5,0
jmpc ns,d_gte_0
cmp $r3,0xFF
jmpc z,ret_y
cmp $r2,0
jmpc z,ret_y
ret_y:
move $r0,$r1
return
d_gte_0:
cmp $r5,0
jmpc z,d_is_0
cmp $r2,0xFF
jmpc z,ret_x
cmp $r3,0
jmpc z,ret_x
d_is_0:
cmp $r2,0xFF
jmpc nz,no_special_vals
ashl $r6,$r0,9 # clear all except x frac
ashl $r7,$r1,9 # clear all except y frac
or $r6,$r6,$r7
cmp $r6,0
jmpc nz,ret_nan
lshr $r4,$r0,31 # sx in r4
lshr $r5,$r1,31 # sy in r4
cmp $r4,$r5
jmpc nz,ret_nan
return
ret_nan:
lpm $r0,nan
return
no_special_vals:
ldk $r8,(1<<10)|(9<<5)|26 # setup implicit bit and mask for e
#----------------------
ashr $r4,$r0,31 # sx in r4
ashl $r0,$r0,3 # shift mx 3 for GRS bits
bins $r0,$r0,$r8 # clear sx, ex and add implicit bit mx
# change mx to signed mantissa
to_signed $r0,$r4
#----------------------
ashr $r4,$r1,31 # sy in r4
ashl $r1,$r1,3 # shift my 3 for GRS bits
bins $r1,$r1,$r8 # clear sy, ey and add implicit bit my
# change my to signed mantissa
to_signed $r1,$r4
#----------------------
# test if we swap ms based on d sign
cmp $r5,0
jmpc gte,noswap
# swap mx & my
xor $r0,$r0,$r1
xor $r1,$r0,$r1
xor $r0,$r0,$r1
# d positive means that ex>=ey, so ez = ex
# d negative means that ey>ex, so ez = ey
move $r2,$r3
# |d|
neg $r5
noswap:
# now $r2 = ez = max(ex,ey)
cmp $r5,26 # max necessary alignment shift is 26
jmpc lt,under_26
ldk $r5,26
under_26:
ldk $r7,-1
ashl $r7,$r7,$r5 # create inverse of mask for test of S bit value in discarded my
not $r7,$r7
tst $r1,$r7 # determine value of sticky bit
# shift my >> |d|
ashr $r1,$r1,$r5
sticky $r1
# add ms
add $r0,$r0,$r1
# $r4 = sign(mx), mx = |mx|
ashr $r4,$r0,31
xor $r0,$r0,$r4
sub $r0,$r0,$r4
# realign mantissa using leading zero count
flip $r7,$r0,31
ntz $r7,$r8
ashl $r0,$r0,$r7
btst $r0,(6<<5)|0 # test low bits for sticky again
lshr $r0,$r0,6
sticky $r0
# update exponent
add $r2,$r2,5
sub $r2,$r2,$r7
# Round to nearest
round $r0,$r7,$r6
# detect_exp_update
lshr $r6,$r0,24
add $r2,$r2,$r6
# final tests
# mz == 0? if so, we just bail with a +0
cmp $r0,0
jmpc nz,msum_not_zero
ldk $r0,0
return
msum_not_zero:
# Combined check that (1 <= ez <= 254)
sub $r3,$r2,1
cmp $r3,254
jmpc b,no_special_ret
# underflow?
cmp $r2,0
jmpc gt,no_under
ldk $r0,0
jmp pack_sz
no_under:
# overflow?
cmp $r2,255
jmpc lt,no_special_ret
ldk $r0,0x7F8
ashl $r0,$r0,20
jmp pack_sz
no_special_ret:
# Pack ez
ldl $r2,$r2,(8<<5)|23
bins $r0,$r0,$r2 # width = 8, pos = 23 pack ez
# Pack sz
pack_sz:
ldl $r4,$r4,(1<<5)|31
bins $r0,$r0,$r4 # width = 1, pos = 31 set sz to sy
return
#endif
##########################################################################
##########################################################################
## multiplication
#ifdef L_mulsf3
.global __mulsf3
__mulsf3:
# x in $r0, y in $r1, result z in $r0 --||| 61 instructions +/- |||--
# unpack e
bextu $r2,$r0,(8<<5)|23 # ex in r2
bextu $r3,$r1,(8<<5)|23 # ey in r3
# calc result sign
xor $r4,$r0,$r1
lpm $r5,sign_mask
and $r4,$r4,$r5 # sz in r4
# unpack m add implicit bit
ldk $r5,(1<<10)|(9<<5)|23 # setup implicit bit and mask for e
#----------------------
bins $r0,$r0,$r5 # clear sx, ex and add implicit bit mx
sub $r6,$r2,1
cmp $r6,254
jmpc b,1f
jmp slow_mul
1: sub $r6,$r3,1
cmp $r6,254
jmpc b,no_special_vals_mul
slow_mul:
# Check for early exit
cmp $r2,0
jmpc z,op_is_zero
cmp $r3,0
jmpc nz,no_early_exit_mul
op_is_zero:
cmp $r2,255
jmpc z,no_early_exit_mul
cmp $r3,255
jmpc z,no_early_exit_mul
move $r0,$r4
return
no_early_exit_mul:
# setup to test for special values
sub $r6,$r2,1
and $r6,$r6,0xFE
sub $r7,$r3,1
and $r7,$r7,0xFE
# test for special values
cmp $r6,$r7
jmpc gte,ex_spec_is_gte_ey_mul
move $r6,$r7
ex_spec_is_gte_ey_mul:
cmp $r6,0xFE
jmpc nz,no_special_vals_mul
cmp $r2,0xFF
jmpc nz,ex_not_FF_mul
ashl $r6,$r0,9
cmp $r6,0
jmpc nz,ret_nan
cmp $r3,0
jmpc z,ret_nan
ashl $r6,$r1,1
lpm $r7,high_FF
cmp $r6,$r7
jmpc a,ret_nan
cmp $r6,0
jmpc z,ret_nan
# infinity
lpm $r0,inf
or $r0,$r0,$r4
return
ex_not_FF_mul:
cmp $r2,0
jmpc nz,no_nan_mul
cmp $r3,0xFF
jmpc nz,no_nan_mul
jmp ret_nan
no_nan_mul:
lpm $r0,nan
and $r0,$r0,$r1
or $r0,$r0,$r4
return
ret_nan:
lpm $r0,nan
return
no_special_vals_mul:
bins $r1,$r1,$r5 # clear sy, ey and add implicit bit my
# calc ez
add $r3,$r2,$r3
sub $r3,$r3,127 # ez in r3
# (r1,r2) = R0 * R1
mul $r2,$r0,$r1
muluh $r1,$r0,$r1
btst $r1,(1<<5)|15 # XXX use jmpx
jmpc z,mul_z0
# mz is 1X.XX...X
# 48-bit product is in (r1,r2). The low 22 bits of r2
# are discarded.
lshr $r0,$r2,22
ashl $r1,$r1,10
or $r0,$r0,$r1 # r0 = (r1,r2) >> 22
ashlcc 2,10
sticky $r0
add $r3,$r3,1 # bump exponent
# Round to nearest
round $r0, $r1, $r2
lshr $r6,$r0,24
add $r3,$r3,$r6
sub $r6,$r3,1
cmp $r6,254
jmpc b,no_special_ret_mul
special_ret_mul:
# When the final exponent <= 0, result is flushed to 0 except
# for the border case 0x00FFFFFF which is promoted to next higher
# FP no., that is, the smallest "normalized" number.
cmp $r3,0
jmpc gt,exp_normal
# Pack ez
ldl $r3,$r3,(8<<5)|23
bins $r0,$r0,$r3 # width = 8, pos = 23 pack ez
lpm $r2,edge_case
cmp $r0,$r2
jmpc nz,no_edge_case
lpm $r0,smallest_norm
jmp pack_sz_mul
no_edge_case:
ldk $r0,0
jmp pack_sz_mul
exp_normal:
# overflow?
cmp $r3,255
jmpc lt,no_special_ret_mul
ldk $r0,0x7F8
ashl $r0,$r0,20
jmp pack_sz_mul
no_special_ret_mul:
# Pack ez
ldl $r3,$r3,(8<<5)|23
bins $r0,$r0,$r3 # width = 8, pos = 23 pack ez
# Pack sz
pack_sz_mul:
or $r0,$r0,$r4
return
mul_z0:
# mz is 0X.XX...X
# 48-bit product is in (r1,r2). The low 21 bits of r2
# are discarded.
lshr $r0,$r2,21
ashl $r1,$r1,11
or $r0,$r0,$r1 # r0 = (r1,r2) >> 22
ashlcc 2,11
sticky $r0
# Round to nearest
round $r0, $r1, $r2
lshr $r6,$r0,24
add $r3,$r3,$r6
sub $r6,$r3,1
cmp $r6,254
jmpc b,no_special_ret_mul
jmp special_ret_mul
#endif
##########################################################################
##########################################################################
## division
## See http://perso.ens-lyon.fr/gilles.villard/BIBLIOGRAPHIE/PDF/arith19.pdf
## for implementation details
#ifdef L_divsf3
dc_1: .long 0xffffe7d7
dc_2: .long 0xffffffe8
dc_3: .long 0xffbad86f
dc_4: .long 0xfffbece7
dc_5: .long 0xf3672b51
dc_6: .long 0xfd9d3a3e
dc_7: .long 0x9a3c4390
dc_8: .long 0xd4d2ce9b
dc_9: .long 0x1bba92b3
dc_10: .long 0x525a1a8b
dc_11: .long 0x0452b1bf
dc_12: .long 0xFFFFFFC0
spec_val_test: .long 0x7F7FFFFF
.global __divsf3
__divsf3:
push $r13
# x in $r0, y in $r1, result z in $r0 --||| 73 instructions +/- |||-
bextu $r10,$r0,(8<<5)|23 # ex in r2
bextu $r11,$r1,(8<<5)|23 # ey in r3
lpm $r6, m_mask
and $r2, $r0, $r6 # mx
and $r3, $r1, $r6 # my
cmp $r2,$r3
bextu $r2,$r30,(1<<5)|4 # c = Tx >= T;
ashl $r3,$r3,9 # T = X << 9;
lpm $r13, sign_mask
ashl $r4,$r0,8 # X8 = X << 8;
or $r4,$r4,$r13 # Mx = X8 | 0x80000000;
lshr $r5,$r4,$r2 # S = Mx >> c;
# calc D
sub $r2, $r11, $r2
add $r12, $r10, 125
sub $r2, $r12, $r2 # int D = (Ex + 125) - (Ey - c);
# calc result sign
xor $r12,$r0,$r1
and $r12,$r12,$r13 # Sr = ( X ˆ Y ) & 0x80000000;
# check early exit
cmp $r10, 0
jmpc nz, no_early_ret_dev
cmp $r11, 0
jmpc z, no_early_ret_dev
cmp $r11, 255
jmpc z, no_early_ret_dev
move $r0, $r12
pop $r13
return
no_early_ret_dev:
# setup to test for special values
sub $r8,$r10,1
and $r8,$r8,0xFE
sub $r9,$r11,1
and $r9,$r9,0xFE
# test for special values
cmp $r8, $r9
jmpc gte, absXm1_gte_absYm1
move $r8, $r9
absXm1_gte_absYm1:
cmp $r8, 0xFE
jmpc nz, no_spec_ret_div
cmp $r10, 0xFF
jmpc nz, ex_not_FF_div
lpm $r6, m_mask
and $r2, $r0, $r6 # mx
cmp $r2, 0
jmpc nz, ret_nan_div
cmp $r11, 0xFF
jmpc z, ret_nan_div
jmp ret_inf_div
ex_not_FF_div:
cmp $r11, 0xFF
jmpc nz, ey_not_FF_div
ashl $r13, $r1, 9
cmp $r13, 0
jmpc nz, ret_nan_div
move $r0, $r12
pop $r13
return
ey_not_FF_div:
or $r10, $r10, $r11
cmp $r10, 0
jmpc z, ret_nan_div
ret_inf_div:
lpm $r6, inf
move $r0, $r6
or $r0, $r0, $r12
pop $r13
return
ret_nan_div:
lpm $r0, nan
pop $r13
return
no_spec_ret_div:
# check for overflow
ldk $r6, 0xFE
cmp $r2, $r6
jmpc lt, no_overflow_div
lpm $r6, inf
or $r0, $r12, $r6
pop $r13
return
no_overflow_div:
# check for underflow
cmp $r2, 0
jmpc ns, no_underflow_div
xnor $r6, $r6, $r6 # -1
cmp $r2, $r6
jmpc nz, ret_sr_div
ldk $r7, 0xFF
xor $r6, $r6, $r7 # 0xFF ^ -1 = 0xFFFFFF00
cmp $r4, $r6
jmpc nz, ret_sr_div
lpm $r6, sign_mask
cmp $r4, $r6
jmpc nz, ret_sr_div
lshr $r0, $r6, 8
or $r0, $r0, $r12
pop $r13
return
ret_sr_div:
move $r0, $r12
pop $r13
return
no_underflow_div:
lpm $r6, dc_1
muluh $r7, $r3, $r6 # i0 = mul( T , 0xffffe7d7 );
lpm $r6, dc_2
sub $r7, $r6, $r7 # i1 = 0xffffffe8 - i0;
muluh $r7, $r5, $r7 # i2 = mul( S , i1 );
add $r7, $r7, 0x20 # i3 = 0x00000020 + i2;
muluh $r8, $r3, $r3 # i4 = mul( T , T );
muluh $r9, $r5, $r8 # i5 = mul( S , i4 );
lpm $r6, dc_3
muluh $r10, $r3, $r6 # i6 = mul( T , 0xffbad86f );
lpm $r6, dc_4
sub $r10, $r6, $r10 # i7 = 0xfffbece7 - i6;
muluh $r10, $r9, $r10 # i8 = mul( i5 , i7 );
add $r7, $r7, $r10 # i9 = i3 + i8;
muluh $r9, $r8, $r9 # i10 = mul( i4 , i5 );
lpm $r6, dc_5
muluh $r10, $r3, $r6 # i11 = mul( T , 0xf3672b51 );
lpm $r6, dc_6
sub $r10, $r6, $r10 # i12 = 0xfd9d3a3e - i11;
lpm $r6, dc_7
muluh $r11, $r3, $r6 # i13 = mul( T , 0x9a3c4390 );
lpm $r6, dc_8
sub $r11, $r6, $r11 # i14 = 0xd4d2ce9b - i13
muluh $r11, $r8, $r11 # i15 = mul( i4 , i14 );
add $r10, $r10, $r11 # i16 = i12 + i15;
muluh $r10, $r9, $r10 # i17 = mul( i10 , i16 )
add $r7, $r7, $r10 # i18 = i9 + i17;
muluh $r10, $r8, $r8 # i19 = mul( i4 , i4 );
lpm $r6, dc_9
muluh $r11, $r3, $r6 # i20 = mul( T , 0x1bba92b3 );
lpm $r6, dc_10
sub $r11, $r6, $r11 # i21 = 0x525a1a8b - i20;
lpm $r6, dc_11
muluh $r8, $r8, $r6 # i22 = mul( i4 , 0x0452b1bf );
add $r8, $r11, $r8 # i23 = i21 + i22;
muluh $r8, $r10, $r8 # i24 = mul( i19 , i23 );
muluh $r8, $r9, $r8 # i25 = mul( i10 , i24 );
add $r3, $r7, $r8 # V = i18 + i25;
# W = V & 0xFFFFFFC0;
lpm $r6, dc_12
and $r3, $r3, $r6 # W
# round and pack final values
ashl $r0, $r2, 23 # pack D
or $r0, $r0, $r12 # pack Sr
ashl $r12, $r1, 8
or $r12, $r12, $r13 # My
muluh $r10, $r3, $r12
lshr $r11, $r5, 1
cmp $r10, $r11
jmpc gte, div_ret_1
add $r3, $r3, 0x40
div_ret_1:
lshr $r3, $r3, 7
add $r0, $r0, $r3
pop $r13
return
#endif
##########################################################################
##########################################################################
## Negate
#ifdef L_negsf
.global __negsf
__negsf:
lpm $r1, sign_mask
xor $r0, $r0, $r1
return
#endif
##########################################################################
##########################################################################
## float to int & unsigned int
#ifdef L_fixsfsi
.global __fixsfsi
__fixsfsi: # 20 instructions
bextu $r1,$r0,(8<<5)|23 # e in r1
lshr $r2,$r0,31 # s in r2
lpm $r3, m_mask
and $r0,$r0,$r3 # m in r0
# test nan
cmp $r1,0xFF
jmpc nz, int_not_nan
cmp $r0,0
jmpc z, int_not_nan
ldk $r0,0
return
int_not_nan:
# test edges
cmp $r1, 127
jmpc gte, int_not_zero # lower limit
ldk $r0,0
return
int_not_zero:
cmp $r1, 158
jmpc lt, int_not_max # upper limit
lpm $r0, nan
cmp $r2, 0
jmpc z, int_positive
xnor $r0, $r0, 0
return
int_not_max:
lpm $r3, smallest_norm
or $r0, $r0, $r3 # set implicit bit
sub $r1, $r1, 150
cmp $r1, 0
jmpc s, shift_right
ashl $r0, $r0, $r1
jmp set_int_sign
shift_right:
xnor $r1, $r1, 0
add $r1, $r1, 1
lshr $r0, $r0, $r1
set_int_sign:
cmp $r2, 0
jmpc z, int_positive
xnor $r0, $r0, 0
add $r0, $r0, 1
int_positive:
return
#endif
#ifdef L_fixunssfsi
.global __fixunssfsi
__fixunssfsi: # 19 instructions
lshr $r2, $r0, 31 # s in r2
cmp $r2, 0
jmpc z, uint_not_neg
ldk $r0, 0
return
uint_not_neg:
bextu $r1, $r0, (8<<5)|23 # e in r1
sub $r1, $r1, 127
lpm $r3, m_mask
and $r0, $r0, $r3 # m in r0
# test nan
cmp $r1, 0xFF
jmpc nz, uint_not_nan
cmp $r0, 0
jmpc z, uint_not_nan
ldk $r0, 0
return
uint_not_nan:
# test edges
cmp $r1, 0
jmpc ns, uint_not_zero # lower limit
ldk $r0, 0
return
uint_not_zero:
lpm $r3, smallest_norm
or $r0, $r0, $r3 # set implicit bit
cmp $r1, 23
jmpc lt, shift_uint_right
sub $r1, $r1, 23
ashl $r0, $r0, $r1
return
shift_uint_right:
ldk $r3, 23
sub $r1, $r3, $r1
lshr $r0, $r0, $r1
return
#endif
##########################################################################
##########################################################################
## int & unsigned int to float
.macro i2f x, s1, s2, s3, lbl
move \s1, \x
nlz \s1, \s2
cmp \s1, 8
jmpc s, float_round\lbl
sub \s2, \s1, 8
ashl \x, \x, \s2
jmp float_no_round\lbl
float_round\lbl:
cmp \s1, 6
jmpc s, float_shift_right\lbl
sub \s2, \s1, 6
ashl \x, \x, \s2
jmp float_round_and_pack\lbl
float_shift_right\lbl:
ldk \s2, 6
sub \s2, \s2, \s1
xnor \s3, \s3 ,\s3 # 0xFFFFFFFF
ashl \s3, \s3 ,\s2 # create inverse of mask for test of S bit value in discarded my
xnor \s3, \s3 ,0 # NOT
tst \x, \s3 # determine value of sticky bit
lshr \x, \x, \s2
jmpc z,float_round_and_pack\lbl
or \x, \x, 1 # set the sticky bit to 1
float_round_and_pack\lbl:
bextu \s2, \x, (1<<5)|2 # extract low bit of m
or \x, \x, \s2 # or p into r
add \x, \x, 1
lshr \x, \x, 2
btst \x, (1<<5)|24 # test for carry from round
jmpc z, float_no_round\lbl
sub \s1, \s1, 1 # inc e for carry (actually dec nlz)
lshr \x, \x, 1
float_no_round\lbl:
ldk \s2, 158
sub \s1, \s2, \s1
# Pack e
ldl \s1, \s1, (8<<5)|23
bins \x, \x, \s1
.endm
#ifdef L_floatsisf
.global __floatsisf
__floatsisf: # 32 instructions
cmp $r0, 0
jmpc nz, float_not_zero
return
float_not_zero:
ashr $r1, $r0, 31 # s in r1
xor $r0, $r0, $r1 # cond neg
sub $r0, $r0, $r1
i2f $r0, $r2, $r3, $r4, 1
ldl $r1, $r1, (1<<5)|31
bins $r0, $r0, $r1
return
#endif
#ifdef L_floatunsisf
.global __floatunsisf
__floatunsisf: # 26 instructions
cmp $r0, 0
jmpc nz, float_not_zero2
return
float_not_zero2:
i2f $r0, $r1, $r2, $r3, 2
return
#endif
#if 0
##########################################################################
##########################################################################
## float compare
__cmpsf2_:
# calc abs vals
lpm $r3, nan # also abs mask
and $r2, $r0, $r3
and $r3, $r1, $r3
# test if either abs is nan
lpm $r4, inf
cmp $r2, $r4
jmpc gt, cmp_is_gt
cmp $r3, $r4
jmpc gt, cmp_is_gt
# test if both are 0
or $r2, $r2, $r3
cmp $r2, 0
jmpc z, cmp_is_eq
# test if eq
cmp $r0, $r1
jmpc z, cmp_is_eq
# -- if either is pos
and $r2, $r0, $r1
cmp $r2, 0
jmpc s, cmp_both_neg
cmp $r0, $r1
jmpc gt, cmp_is_gt
# r0 < r1
lpm $r0, high_uint
return
cmp_both_neg:
cmp $r0, $r1
jmpc lt, cmp_is_gt
# r0 < r1
lpm $r0, high_uint
return
cmp_is_gt:
ldk $r0, 1
return
cmp_is_eq:
ldk $r0, 0
return
#endif
#ifdef L_udivsi3
.global __udivsi3
__udivsi3:
# $r0 is dividend
# $r1 is divisor
ldk $r2,0
push $r28
ldk $r28,-32
0:
lshr $r3,$r0,31 # Shift $r2:$r0 left one
ashl $r0,$r0,1
ashl $r2,$r2,1
or $r2,$r2,$r3
cmp $r2,$r1
jmpc b,1f
2:
sub $r2,$r2,$r1
add $r0,$r0,1
1:
add $r28,$r28,1
jmpx 31,$r28,1,0b
pop $r28
# $r0: quotient
# $r2: remainder
return
#endif
#ifdef L_umodsi3
.global __umodsi3
__umodsi3:
call __udivsi3
move $r0,$r2
return
#endif
#ifdef L_divsi3
.global __divsi3
__divsi3:
xor $r5,$r0,$r1 # $r5 is sign of result
ashr $r2,$r0,31 # $r0 = abs($r0)
xor $r0,$r0,$r2
sub $r0,$r0,$r2
ashr $r2,$r1,31 # $r1 = abs($r1)
xor $r1,$r1,$r2
sub $r1,$r1,$r2
call __udivsi3
ashr $r5,$r5,31
xor $r0,$r0,$r5
sub $r0,$r0,$r5
return
#endif
#ifdef L_modsi3
.global __modsi3
__modsi3:
move $r5,$r0 # $r5 is sign of result
ashr $r2,$r0,31 # $r0 = abs($r0)
xor $r0,$r0,$r2
sub $r0,$r0,$r2
ashr $r2,$r1,31 # $r1 = abs($r1)
xor $r1,$r1,$r2
sub $r1,$r1,$r2
call __umodsi3
ashr $r5,$r5,31
xor $r0,$r0,$r5
sub $r0,$r0,$r5
return
#endif
|
4ms/metamodule-plugin-sdk
| 1,525
|
plugin-libc/libgcc/config/mips/crtn.S
|
/* Copyright (C) 2001-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
#ifdef __mips16
#define RA $7
#else
#define RA $31
#endif
.section .init,"ax",@progbits
init:
#ifdef __mips64
ld RA,40($sp)
daddu $sp,$sp,48
#else
lw RA,20($sp)
addu $sp,$sp,32
#endif
j RA
.section .fini,"ax",@progbits
fini:
#ifdef __mips64
ld RA,40($sp)
daddu $sp,$sp,48
#else
lw RA,20($sp)
addu $sp,$sp,32
#endif
j RA
|
4ms/metamodule-plugin-sdk
| 21,069
|
plugin-libc/libgcc/config/mips/mips16.S
|
/* mips16 floating point support code
Copyright (C) 1996-2022 Free Software Foundation, Inc.
Contributed by Cygnus Support
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
#include "auto-host.h"
#if defined(__mips_micromips) || defined(__mips_soft_float) \
|| __mips_isa_rev >= 6
/* Do nothing because this code is only needed when linking
against mips16 hard-float objects. Neither micromips code
nor soft-float nor MIPS R6 code can be linked against mips16
hard-float objects so we do not need these routines when
building libgcc for those cases. */
#else
#if defined(HAVE_AS_MODULE)
#if __mips_fpr == 32
.module fp=32
#elif __mips_fpr == 0
.module fp=xx
#elif __mips_fpr == 64
.module fp=64
#endif
#endif
/* This file contains mips16 floating point support functions. These
functions are called by mips16 code to handle floating point when
-msoft-float is not used. They accept the arguments and return
values using the soft-float calling convention, but do the actual
operation using the hard floating point instructions. */
#if defined _MIPS_SIM && (_MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIO64)
/* This file contains 32-bit assembly code. */
.set nomips16
/* Start a function. */
#define STARTFN(NAME) .globl NAME; .ent NAME; NAME:
/* Finish a function. */
#define ENDFN(NAME) .end NAME
/* ARG1
The FPR that holds the first floating-point argument.
ARG2
The FPR that holds the second floating-point argument.
RET
The FPR that holds a floating-point return value. */
#define RET $f0
#define ARG1 $f12
#ifdef __mips64
#define ARG2 $f13
#else
#define ARG2 $f14
#endif
/* Set 64-bit register GPR so that its high 32 bits contain HIGH_FPR
and so that its low 32 bits contain LOW_FPR. */
#define MERGE_GPRf(GPR, HIGH_FPR, LOW_FPR) \
.set noat; \
mfc1 $1, LOW_FPR; \
mfc1 GPR, HIGH_FPR; \
dsll $1, $1, 32; \
dsll GPR, GPR, 32; \
dsrl $1, $1, 32; \
or GPR, GPR, $1; \
.set at
/* Move the high 32 bits of GPR to HIGH_FPR and the low 32 bits of
GPR to LOW_FPR. */
#define MERGE_GPRt(GPR, HIGH_FPR, LOW_FPR) \
.set noat; \
dsrl $1, GPR, 32; \
mtc1 GPR, LOW_FPR; \
mtc1 $1, HIGH_FPR; \
.set at
/* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
#define DELAYt(T, OPCODE, OP2) \
.set noreorder; \
jr T; \
OPCODE, OP2; \
.set reorder
#if __mips >= 4
/* Coprocessor moves are interlocked from the MIPS IV ISA up. */
#define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2)
#else
/* Use "OPCODE. OP2" and jump to T. */
#define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
#endif
/* MOVE_SF_BYTE0(D)
Move the first single-precision floating-point argument between
GPRs and FPRs.
MOVE_SI_BYTE0(D)
Likewise the first single-precision integer argument.
MOVE_SF_BYTE4(D)
Move the second single-precision floating-point argument between
GPRs and FPRs, given that the first argument occupies 4 bytes.
MOVE_SF_BYTE8(D)
Move the second single-precision floating-point argument between
GPRs and FPRs, given that the first argument occupies 8 bytes.
MOVE_DF_BYTE0(D)
Move the first double-precision floating-point argument between
GPRs and FPRs.
MOVE_DF_BYTE8(D)
Likewise the second double-precision floating-point argument.
MOVE_SF_RET(D, T)
Likewise a single-precision floating-point return value,
then jump to T.
MOVE_SC_RET(D, T)
Likewise a complex single-precision floating-point return value.
MOVE_DF_RET(D, T)
Likewise a double-precision floating-point return value.
MOVE_DC_RET(D, T)
Likewise a complex double-precision floating-point return value.
MOVE_SI_RET(D, T)
Likewise a single-precision integer return value.
The D argument is "t" to move to FPRs and "f" to move from FPRs.
The return macros may assume that the target of the jump does not
use a floating-point register. */
#define MOVE_SF_RET(D, T) DELAY##D (T, m##D##c1 $2,$f0)
#define MOVE_SI_RET(D, T) DELAY##D (T, m##D##c1 $2,$f0)
#if defined(__mips64) && defined(__MIPSEB__)
#define MOVE_SC_RET(D, T) MERGE_GPR##D ($2, $f0, $f1); jr T
#elif defined(__mips64)
/* The high 32 bits of $2 correspond to the second word in memory;
i.e. the imaginary part. */
#define MOVE_SC_RET(D, T) MERGE_GPR##D ($2, $f1, $f0); jr T
#else
#define MOVE_SC_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f2)
#endif
#if defined(__mips64)
#define MOVE_SF_BYTE0(D) m##D##c1 $4,$f12
#define MOVE_SF_BYTE4(D) m##D##c1 $5,$f13
#define MOVE_SF_BYTE8(D) m##D##c1 $5,$f13
#else
#define MOVE_SF_BYTE0(D) m##D##c1 $4,$f12
#define MOVE_SF_BYTE4(D) m##D##c1 $5,$f14
#define MOVE_SF_BYTE8(D) m##D##c1 $6,$f14
#endif
#define MOVE_SI_BYTE0(D) MOVE_SF_BYTE0(D)
#if defined(__mips64)
#define MOVE_DF_BYTE0(D) dm##D##c1 $4,$f12
#define MOVE_DF_BYTE8(D) dm##D##c1 $5,$f13
#define MOVE_DF_RET(D, T) DELAY##D (T, dm##D##c1 $2,$f0)
#define MOVE_DC_RET(D, T) dm##D##c1 $3,$f1; MOVE_DF_RET (D, T)
#elif __mips_fpr != 32 && __mips_isa_rev >= 2 && defined(__MIPSEB__)
#define MOVE_DF_BYTE0(D) m##D##c1 $5,$f12; m##D##hc1 $4,$f12
#define MOVE_DF_BYTE8(D) m##D##c1 $7,$f14; m##D##hc1 $6,$f14
#define MOVE_DF_RET(D, T) m##D##c1 $3,$f0; DELAY##D (T, m##D##hc1 $2,$f0)
#define MOVE_DC_RET(D, T) m##D##c1 $5,$f2; m##D##hc1 $4,$f2; MOVE_DF_RET (D, T)
#elif __mips_fpr != 32 && __mips_isa_rev >= 2
#define MOVE_DF_BYTE0(D) m##D##c1 $4,$f12; m##D##hc1 $5,$f12
#define MOVE_DF_BYTE8(D) m##D##c1 $6,$f14; m##D##hc1 $7,$f14
#define MOVE_DF_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##hc1 $3,$f0)
#define MOVE_DC_RET(D, T) m##D##c1 $4,$f2; m##D##hc1 $5,$f2; MOVE_DF_RET (D, T)
#elif __mips_fpr == 0
#define MOVE_DF_BYTE0t sw $4, 0($29); sw $5, 4($29); ldc1 $f12, 0($29)
#define MOVE_DF_BYTE0f sdc1 $f12, 0($29); lw $4, 0($29); lw $5, 4($29)
#define MOVE_DF_BYTE0(D) MOVE_DF_BYTE0##D
#define MOVE_DF_BYTE8t sw $6, 8($29); sw $7, 12($29); ldc1 $f14, 8($29)
#define MOVE_DF_BYTE8f sdc1 $f14, 8($29); lw $6, 8($29); lw $7, 12($29)
#define MOVE_DF_BYTE8(D) MOVE_DF_BYTE8##D
#define MOVE_DF_RETt(T) sw $2, 0($29); sw $3, 4($29); DELAYt (T, ldc1 $f0, 0($29))
#define MOVE_DF_RETf(T) sdc1 $f0, 0($29); lw $2, 0($29); DELAYf (T, lw $3, 4($29))
#define MOVE_DF_RET(D, T) MOVE_DF_RET##D(T)
#define MOVE_DC_RETt(T) sw $4, 8($29); sw $5, 12($29); ldc1 $f2, 8($29); MOVE_DF_RETt(T)
#define MOVE_DC_RETf(T) sdc1 $f2, 8($29); lw $4, 8($29); lw $5, 12($29); MOVE_DF_RETf(T)
#define MOVE_DC_RET(D, T) MOVE_DF_RET##D(T)
#elif defined(__MIPSEB__)
/* FPRs are little-endian. */
#define MOVE_DF_BYTE0(D) m##D##c1 $4,$f13; m##D##c1 $5,$f12
#define MOVE_DF_BYTE8(D) m##D##c1 $6,$f15; m##D##c1 $7,$f14
#define MOVE_DF_RET(D, T) m##D##c1 $2,$f1; DELAY##D (T, m##D##c1 $3,$f0)
#define MOVE_DC_RET(D, T) m##D##c1 $4,$f3; m##D##c1 $5,$f2; MOVE_DF_RET (D, T)
#else
#define MOVE_DF_BYTE0(D) m##D##c1 $4,$f12; m##D##c1 $5,$f13
#define MOVE_DF_BYTE8(D) m##D##c1 $6,$f14; m##D##c1 $7,$f15
#define MOVE_DF_RET(D, T) m##D##c1 $2,$f0; DELAY##D (T, m##D##c1 $3,$f1)
#define MOVE_DC_RET(D, T) m##D##c1 $4,$f2; m##D##c1 $5,$f3; MOVE_DF_RET (D, T)
#endif
/* Single-precision math. */
/* Define a function NAME that loads two single-precision values,
performs FPU operation OPCODE on them, and returns the single-
precision result. */
#define OPSF3(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
MOVE_SF_BYTE4 (t); \
OPCODE RET,ARG1,ARG2; \
MOVE_SF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16addsf3
OPSF3 (__mips16_addsf3, add.s)
#endif
#ifdef L_m16subsf3
OPSF3 (__mips16_subsf3, sub.s)
#endif
#ifdef L_m16mulsf3
OPSF3 (__mips16_mulsf3, mul.s)
#endif
#ifdef L_m16divsf3
OPSF3 (__mips16_divsf3, div.s)
#endif
/* Define a function NAME that loads a single-precision value,
performs FPU operation OPCODE on it, and returns the single-
precision result. */
#define OPSF2(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
OPCODE RET,ARG1; \
MOVE_SF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16negsf2
OPSF2 (__mips16_negsf2, neg.s)
#endif
#ifdef L_m16abssf2
OPSF2 (__mips16_abssf2, abs.s)
#endif
/* Single-precision comparisons. */
/* Define a function NAME that loads two single-precision values,
performs floating point comparison OPCODE, and returns TRUE or
FALSE depending on the result. */
#define CMPSF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
MOVE_SF_BYTE4 (t); \
OPCODE ARG1,ARG2; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
/* Like CMPSF, but reverse the comparison operands. */
#define REVCMPSF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_SF_BYTE0 (t); \
MOVE_SF_BYTE4 (t); \
OPCODE ARG2,ARG1; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
#ifdef L_m16eqsf2
CMPSF (__mips16_eqsf2, c.eq.s, 0, 1)
#endif
#ifdef L_m16nesf2
CMPSF (__mips16_nesf2, c.eq.s, 0, 1)
#endif
#ifdef L_m16gtsf2
REVCMPSF (__mips16_gtsf2, c.lt.s, 1, 0)
#endif
#ifdef L_m16gesf2
REVCMPSF (__mips16_gesf2, c.le.s, 0, -1)
#endif
#ifdef L_m16lesf2
CMPSF (__mips16_lesf2, c.le.s, 0, 1)
#endif
#ifdef L_m16ltsf2
CMPSF (__mips16_ltsf2, c.lt.s, -1, 0)
#endif
#ifdef L_m16unordsf2
CMPSF(__mips16_unordsf2, c.un.s, 1, 0)
#endif
/* Single-precision conversions. */
#ifdef L_m16fltsisf
STARTFN (__mips16_floatsisf)
MOVE_SF_BYTE0 (t)
cvt.s.w RET,ARG1
MOVE_SF_RET (f, $31)
ENDFN (__mips16_floatsisf)
#endif
#ifdef L_m16fltunsisf
STARTFN (__mips16_floatunsisf)
.set noreorder
bltz $4,1f
MOVE_SF_BYTE0 (t)
.set reorder
cvt.s.w RET,ARG1
MOVE_SF_RET (f, $31)
1:
and $2,$4,1
srl $3,$4,1
or $2,$2,$3
mtc1 $2,RET
cvt.s.w RET,RET
add.s RET,RET,RET
MOVE_SF_RET (f, $31)
ENDFN (__mips16_floatunsisf)
#endif
#ifdef L_m16fix_truncsfsi
STARTFN (__mips16_fix_truncsfsi)
MOVE_SF_BYTE0 (t)
trunc.w.s RET,ARG1,$4
MOVE_SI_RET (f, $31)
ENDFN (__mips16_fix_truncsfsi)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
/* Double-precision math. */
/* Define a function NAME that loads two double-precision values,
performs FPU operation OPCODE on them, and returns the double-
precision result. */
#define OPDF3(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
MOVE_DF_BYTE8 (t); \
OPCODE RET,ARG1,ARG2; \
MOVE_DF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16adddf3
OPDF3 (__mips16_adddf3, add.d)
#endif
#ifdef L_m16subdf3
OPDF3 (__mips16_subdf3, sub.d)
#endif
#ifdef L_m16muldf3
OPDF3 (__mips16_muldf3, mul.d)
#endif
#ifdef L_m16divdf3
OPDF3 (__mips16_divdf3, div.d)
#endif
/* Define a function NAME that loads a double-precision value,
performs FPU operation OPCODE on it, and returns the double-
precision result. */
#define OPDF2(NAME, OPCODE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
OPCODE RET,ARG1; \
MOVE_DF_RET (f, $31); \
ENDFN (NAME)
#ifdef L_m16negdf2
OPDF2 (__mips16_negdf2, neg.d)
#endif
#ifdef L_m16absdf2
OPDF2 (__mips16_absdf2, abs.d)
#endif
/* Conversions between single and double precision. */
#ifdef L_m16extsfdf2
STARTFN (__mips16_extendsfdf2)
MOVE_SF_BYTE0 (t)
cvt.d.s RET,ARG1
MOVE_DF_RET (f, $31)
ENDFN (__mips16_extendsfdf2)
#endif
#ifdef L_m16trdfsf2
STARTFN (__mips16_truncdfsf2)
MOVE_DF_BYTE0 (t)
cvt.s.d RET,ARG1
MOVE_SF_RET (f, $31)
ENDFN (__mips16_truncdfsf2)
#endif
/* Double-precision comparisons. */
/* Define a function NAME that loads two double-precision values,
performs floating point comparison OPCODE, and returns TRUE or
FALSE depending on the result. */
#define CMPDF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
MOVE_DF_BYTE8 (t); \
OPCODE ARG1,ARG2; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
/* Like CMPDF, but reverse the comparison operands. */
#define REVCMPDF(NAME, OPCODE, TRUE, FALSE) \
STARTFN (NAME); \
MOVE_DF_BYTE0 (t); \
MOVE_DF_BYTE8 (t); \
OPCODE ARG2,ARG1; \
li $2,TRUE; \
bc1t 1f; \
li $2,FALSE; \
1:; \
j $31; \
ENDFN (NAME)
#ifdef L_m16eqdf2
CMPDF (__mips16_eqdf2, c.eq.d, 0, 1)
#endif
#ifdef L_m16nedf2
CMPDF (__mips16_nedf2, c.eq.d, 0, 1)
#endif
#ifdef L_m16gtdf2
REVCMPDF (__mips16_gtdf2, c.lt.d, 1, 0)
#endif
#ifdef L_m16gedf2
REVCMPDF (__mips16_gedf2, c.le.d, 0, -1)
#endif
#ifdef L_m16ledf2
CMPDF (__mips16_ledf2, c.le.d, 0, 1)
#endif
#ifdef L_m16ltdf2
CMPDF (__mips16_ltdf2, c.lt.d, -1, 0)
#endif
#ifdef L_m16unorddf2
CMPDF(__mips16_unorddf2, c.un.d, 1, 0)
#endif
/* Double-precision conversions. */
#ifdef L_m16fltsidf
STARTFN (__mips16_floatsidf)
MOVE_SI_BYTE0 (t)
cvt.d.w RET,ARG1
MOVE_DF_RET (f, $31)
ENDFN (__mips16_floatsidf)
#endif
#ifdef L_m16fltunsidf
STARTFN (__mips16_floatunsidf)
MOVE_SI_BYTE0 (t)
cvt.d.w RET,ARG1
bgez $4,1f
li.d ARG1, 4.294967296e+9
add.d RET, RET, ARG1
1: MOVE_DF_RET (f, $31)
ENDFN (__mips16_floatunsidf)
#endif
#ifdef L_m16fix_truncdfsi
STARTFN (__mips16_fix_truncdfsi)
MOVE_DF_BYTE0 (t)
trunc.w.d RET,ARG1,$4
MOVE_SI_RET (f, $31)
ENDFN (__mips16_fix_truncdfsi)
#endif
#endif /* !__mips_single_float */
/* We don't export stubs from libgcc_s.so and always require static
versions to be pulled from libgcc.a as needed because they use $2
and possibly $3 as arguments, diverging from the standard SysV ABI,
and as such would require severe pessimisation of MIPS16 PLT entries
just for this single special case.
For compatibility with old binaries that used safe standard MIPS PLT
entries and referred to these functions we still export them at
version GCC_4.4.0 for run-time loading only. */
#ifdef SHARED
#define CE_STARTFN(NAME) \
STARTFN (NAME##_compat); \
.symver NAME##_compat, NAME@GCC_4.4.0
#define CE_ENDFN(NAME) ENDFN (NAME##_compat)
#else
#define CE_STARTFN(NAME) \
STARTFN (NAME); \
.hidden NAME
#define CE_ENDFN(NAME) ENDFN (NAME)
#endif
/* Define a function NAME that moves a return value of mode MODE from
FPRs to GPRs. */
#define RET_FUNCTION(NAME, MODE) \
CE_STARTFN (NAME); \
MOVE_##MODE##_RET (t, $31); \
CE_ENDFN (NAME)
#ifdef L_m16retsf
RET_FUNCTION (__mips16_ret_sf, SF)
#endif
#ifdef L_m16retsc
RET_FUNCTION (__mips16_ret_sc, SC)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16retdf
RET_FUNCTION (__mips16_ret_df, DF)
#endif
#ifdef L_m16retdc
RET_FUNCTION (__mips16_ret_dc, DC)
#endif
#endif /* !__mips_single_float */
/* STUB_ARGS_X copies the arguments from GPRs to FPRs for argument
code X. X is calculated as ARG1 + ARG2 * 4, where ARG1 and ARG2
classify the first and second arguments as follows:
1: a single-precision argument
2: a double-precision argument
0: no argument, or not one of the above. */
#define STUB_ARGS_0 /* () */
#define STUB_ARGS_1 MOVE_SF_BYTE0 (t) /* (sf) */
#define STUB_ARGS_5 MOVE_SF_BYTE0 (t); MOVE_SF_BYTE4 (t) /* (sf, sf) */
#define STUB_ARGS_9 MOVE_SF_BYTE0 (t); MOVE_DF_BYTE8 (t) /* (sf, df) */
#define STUB_ARGS_2 MOVE_DF_BYTE0 (t) /* (df) */
#define STUB_ARGS_6 MOVE_DF_BYTE0 (t); MOVE_SF_BYTE8 (t) /* (df, sf) */
#define STUB_ARGS_10 MOVE_DF_BYTE0 (t); MOVE_DF_BYTE8 (t) /* (df, df) */
/* These functions are used by 16-bit code when calling via a function
pointer. They must copy the floating point arguments from the GPRs
to FPRs and then call function $2. */
#define CALL_STUB_NO_RET(NAME, CODE) \
CE_STARTFN (NAME); \
STUB_ARGS_##CODE; \
.set noreorder; \
jr $2; \
move $25,$2; \
.set reorder; \
CE_ENDFN (NAME)
#ifdef L_m16stub1
CALL_STUB_NO_RET (__mips16_call_stub_1, 1)
#endif
#ifdef L_m16stub5
CALL_STUB_NO_RET (__mips16_call_stub_5, 5)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stub2
CALL_STUB_NO_RET (__mips16_call_stub_2, 2)
#endif
#ifdef L_m16stub6
CALL_STUB_NO_RET (__mips16_call_stub_6, 6)
#endif
#ifdef L_m16stub9
CALL_STUB_NO_RET (__mips16_call_stub_9, 9)
#endif
#ifdef L_m16stub10
CALL_STUB_NO_RET (__mips16_call_stub_10, 10)
#endif
#endif /* !__mips_single_float */
/* Now we have the same set of functions, except that this time the
function being called returns an SFmode, SCmode, DFmode or DCmode
value; we need to instantiate a set for each case. The calling
function will arrange to preserve $18, so these functions are free
to use it to hold the return address.
Note that we do not know whether the function we are calling is 16
bit or 32 bit. However, it does not matter, because 16-bit
functions always return floating point values in both the gp and
the fp regs. It would be possible to check whether the function
being called is 16 bits, in which case the copy is unnecessary;
however, it's faster to always do the copy. */
#define CALL_STUB_RET(NAME, CODE, MODE) \
CE_STARTFN (NAME); \
.cfi_startproc; \
/* Create a fake CFA 4 bytes below the stack pointer. */ \
.cfi_def_cfa 29,-4; \
/* "Save" $sp in itself so we don't use the fake CFA. \
This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */ \
.cfi_escape 0x16,29,1,0x6d; \
move $18,$31; \
.cfi_register 31,18; \
STUB_ARGS_##CODE; \
.set noreorder; \
jalr $2; \
move $25,$2; \
.set reorder; \
MOVE_##MODE##_RET (f, $18); \
.cfi_endproc; \
CE_ENDFN (NAME)
/* First, instantiate the single-float set. */
#ifdef L_m16stubsf0
CALL_STUB_RET (__mips16_call_stub_sf_0, 0, SF)
#endif
#ifdef L_m16stubsf1
CALL_STUB_RET (__mips16_call_stub_sf_1, 1, SF)
#endif
#ifdef L_m16stubsf5
CALL_STUB_RET (__mips16_call_stub_sf_5, 5, SF)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubsf2
CALL_STUB_RET (__mips16_call_stub_sf_2, 2, SF)
#endif
#ifdef L_m16stubsf6
CALL_STUB_RET (__mips16_call_stub_sf_6, 6, SF)
#endif
#ifdef L_m16stubsf9
CALL_STUB_RET (__mips16_call_stub_sf_9, 9, SF)
#endif
#ifdef L_m16stubsf10
CALL_STUB_RET (__mips16_call_stub_sf_10, 10, SF)
#endif
#endif /* !__mips_single_float */
/* Now we have the same set of functions again, except that this time
the function being called returns an DFmode value. */
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubdf0
CALL_STUB_RET (__mips16_call_stub_df_0, 0, DF)
#endif
#ifdef L_m16stubdf1
CALL_STUB_RET (__mips16_call_stub_df_1, 1, DF)
#endif
#ifdef L_m16stubdf5
CALL_STUB_RET (__mips16_call_stub_df_5, 5, DF)
#endif
#ifdef L_m16stubdf2
CALL_STUB_RET (__mips16_call_stub_df_2, 2, DF)
#endif
#ifdef L_m16stubdf6
CALL_STUB_RET (__mips16_call_stub_df_6, 6, DF)
#endif
#ifdef L_m16stubdf9
CALL_STUB_RET (__mips16_call_stub_df_9, 9, DF)
#endif
#ifdef L_m16stubdf10
CALL_STUB_RET (__mips16_call_stub_df_10, 10, DF)
#endif
#endif /* !__mips_single_float */
/* Ho hum. Here we have the same set of functions again, this time
for when the function being called returns an SCmode value. */
#ifdef L_m16stubsc0
CALL_STUB_RET (__mips16_call_stub_sc_0, 0, SC)
#endif
#ifdef L_m16stubsc1
CALL_STUB_RET (__mips16_call_stub_sc_1, 1, SC)
#endif
#ifdef L_m16stubsc5
CALL_STUB_RET (__mips16_call_stub_sc_5, 5, SC)
#endif
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubsc2
CALL_STUB_RET (__mips16_call_stub_sc_2, 2, SC)
#endif
#ifdef L_m16stubsc6
CALL_STUB_RET (__mips16_call_stub_sc_6, 6, SC)
#endif
#ifdef L_m16stubsc9
CALL_STUB_RET (__mips16_call_stub_sc_9, 9, SC)
#endif
#ifdef L_m16stubsc10
CALL_STUB_RET (__mips16_call_stub_sc_10, 10, SC)
#endif
#endif /* !__mips_single_float */
/* Finally, another set of functions for DCmode. */
#if !defined(__mips_single_float) && !defined(__SINGLE_FLOAT)
#ifdef L_m16stubdc0
CALL_STUB_RET (__mips16_call_stub_dc_0, 0, DC)
#endif
#ifdef L_m16stubdc1
CALL_STUB_RET (__mips16_call_stub_dc_1, 1, DC)
#endif
#ifdef L_m16stubdc5
CALL_STUB_RET (__mips16_call_stub_dc_5, 5, DC)
#endif
#ifdef L_m16stubdc2
CALL_STUB_RET (__mips16_call_stub_dc_2, 2, DC)
#endif
#ifdef L_m16stubdc6
CALL_STUB_RET (__mips16_call_stub_dc_6, 6, DC)
#endif
#ifdef L_m16stubdc9
CALL_STUB_RET (__mips16_call_stub_dc_9, 9, DC)
#endif
#ifdef L_m16stubdc10
CALL_STUB_RET (__mips16_call_stub_dc_10, 10, DC)
#endif
#endif /* !__mips_single_float */
#endif
#endif /* defined(__mips_micromips) || defined(__mips_soft_float) */
|
4ms/metamodule-plugin-sdk
| 2,381
|
plugin-libc/libgcc/config/mips/vr4120-div.S
|
/* Support file for -mfix-vr4120.
Copyright (C) 2002-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
/* This file contains functions which implement divsi3 and modsi3 for
-mfix-vr4120. div and ddiv do not give the correct result when one
of the operands is negative. */
.set nomips16
#define DIV \
xor $3,$4,$5 /* t = x ^ y */ ; \
li $2,0x80000000; \
.set noreorder; \
bgez $4,1f /* x >= 0 */; \
and $3,$3,$2 /* t = (x ^ y) & 0x80000000 in delay slot */ ;\
.set reorder; \
subu $4,$0,$4 /* x = -x */ ; \
1:; \
.set noreorder; \
bgez $5,2f /* y >= 0 */ ; \
nop; \
subu $5,$0,$5 /* y = -y */ ; \
.set reorder; \
2:; \
divu $0,$4,$5; /* we use divu because of INT_MIN */ \
.set noreorder; \
bne $5,$0,3f; \
nop; \
break 7 /* division on zero y */ ; \
3:; \
.set reorder; \
mflo $2 /* r = x / y */ ; \
.set noreorder; \
beq $3,$0,4f /* t == 0 */ ; \
nop; \
subu $2,$0,$2 /* r = -r */ ; \
.set reorder; \
4:
.globl __vr4120_divsi3
.ent __vr4120_divsi3
__vr4120_divsi3:
DIV
j $31
.end __vr4120_divsi3
.globl __vr4120_modsi3
.ent __vr4120_modsi3
__vr4120_modsi3:
move $6,$4 # x1 = x
move $7,$5 # y1 = y
DIV
mult $2,$7 # r = r * y1
mflo $2
.set noreorder
j $31
subu $2,$6,$2 # r = x1 - r in delay slot
.end __vr4120_modsi3
|
4ms/metamodule-plugin-sdk
| 1,544
|
plugin-libc/libgcc/config/mips/crti.S
|
/* Copyright (C) 2001-2022 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
/* An executable stack is *not* required for these functions. */
#include "gnustack.h"
/* 4 slots for argument spill area. 1 for cpreturn, 1 for stack.
Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */
.section .init,"ax",@progbits
.globl _init
.type _init,@function
_init:
#ifdef __mips64
daddu $sp,$sp,-48
sd $31,40($sp)
#else
addu $sp,$sp,-32
sw $31,20($sp)
#endif
.section .fini,"ax",@progbits
.globl _fini
.type _fini,@function
_fini:
#ifdef __mips64
daddu $sp,$sp,-48
sd $31,40($sp)
#else
addu $sp,$sp,-32
sw $31,20($sp)
#endif
|
4ms/metamodule-plugin-sdk
| 5,358
|
plugin-libc/libgcc/config/or1k/lib1funcs.S
|
/* Copyright (C) 2018-2022 Free Software Foundation, Inc.
This file is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the
Free Software Foundation; either version 3, or (at your option) any
later version.
This file is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#ifdef L__mulsi3
.balign 4
.globl __mulsi3
.type __mulsi3, @function
__mulsi3:
l.movhi r11, 0 /* initial r */
/* Given R = X * Y ... */
1: l.sfeq r4, r0 /* while (y != 0) */
l.bf 2f
l.andi r5, r4, 1 /* if (y & 1) ... */
l.add r12, r11, r3
l.sfne r5, r0
#if defined(__or1k_cmov__)
l.cmov r11, r12, r11 /* ... r += x. */
l.srli r4, r4, 1 /* y >>= 1 */
#else
l.bnf 3f
l.srli r4, r4, 1 /* y >>= 1 */
l.ori r11, r12, 0
3:
#endif
l.j 1b
l.add r3, r3, r3 /* x <<= 1 */
2: l.jr r9
l.nop
.size __mulsi3, . - __mulsi3
#endif
#if defined(L__udivsi3) || defined(L__umodsi3) \
|| defined(L__divsi3) || defined(L__modsi3)
.global __udivmodsi3_internal
.hidden __udivmodsi3_internal
.type __udivmodsi3_internal, @function
#endif
#ifdef L__udivsi3
.balign 4
.global __udivsi3
.type __udivsi3, @function
__udivsi3:
__udivmodsi3_internal:
/* Note that the other division routines assume that r13
is not clobbered by this routine, and use that as to
save a return address without creating a stack frame. */
l.sfeq r4, r0 /* division by zero; return 0. */
l.ori r11, r0, 0 /* initial quotient */
l.bf 9f
l.ori r12, r3, 0 /* initial remainder */
/* Given X/Y, shift Y left until Y >= X. */
l.ori r6, r0, 1 /* mask = 1 */
1: l.sflts r4, r0 /* y has msb set */
l.bf 2f
l.sfltu r4, r12 /* y < x */
l.add r4, r4, r4 /* y <<= 1 */
l.bf 1b
l.add r6, r6, r6 /* mask <<= 1 */
/* Shift Y back to the right again, subtracting from X. */
2: l.add r7, r11, r6 /* tmp1 = quot + mask */
3: l.srli r6, r6, 1 /* mask >>= 1 */
l.sub r8, r12, r4 /* tmp2 = x - y */
l.sfleu r4, r12 /* y <= x */
l.srli r4, r4, 1 /* y >>= 1 */
#if defined(__or1k_cmov__)
l.cmov r11, r7, r11 /* if (y <= x) quot = tmp1 */
l.cmov r12, r8, r12 /* if (y <= x) x = tmp2 */
#else
l.bnf 4f
l.nop
l.ori r11, r7, 0
l.ori r12, r8, 0
4:
#endif
l.sfne r6, r0 /* loop until mask == 0 */
l.bf 3b
l.add r7, r11, r6 /* delay fill from loop start */
9: l.jr r9
l.nop
.size __udivsi3, . - __udivsi3
.size __udivmodsi3_internal, . - __udivmodsi3_internal
#endif
#ifdef L__umodsi3
.balign 4
.global __umodsi3
.type __umodsi3, @function
.cfi_startproc
__umodsi3:
/* Know that __udivmodsi3_internal does not clobber r13. */
l.ori r13, r9, 0
.cfi_register 9, 13
l.jal __udivmodsi3_internal
l.nop
l.jr r13 /* return to saved lr */
l.ori r11, r12, 0 /* move remainder to rv */
.cfi_endproc
.size __umodsi3, . - __umodsi3
#endif
/* For signed division we do:
-x / y = x / -y = -(x / y)
-x % y = -(x % y)
x % -y = x % y
which has the property that (x/y)*y + (x%y) = x. */
#ifdef L__divsi3
.balign 4
.global __divsi3
.type __divsi3, @function
.cfi_startproc
__divsi3:
l.xor r6, r3, r4 /* need result negate? */
l.sflts r3, r0 /* abs(x) */
#if defined(__or1k_cmov__)
l.sub r5, r0, r3
l.cmov r3, r5, r3
#else
l.bnf 1f
l.sub r5, r0, r3
l.ori r3, r5, 0
1:
#endif
l.sflts r4, r0 /* abs(y) */
#if defined(__or1k_cmov__)
l.sub r5, r0, r4
l.cmov r4, r5, r4
#else
l.bnf 2f
l.sub r5, r0, r4
l.ori r4, r5, 0
2:
#endif
/* If the result will not require sign flip, tail call. */
l.sflts r6, r0
l.bnf __udivmodsi3_internal
l.ori r13, r9, 0 /* save lr */
/* Otherwise, know that __udivmodsi3_internal does not clobber r13.
Perform a normal call, then negate and return via saved lr. */
.cfi_register 9, 13
l.jal __udivmodsi3_internal
l.nop
l.jr r13
l.sub r11, r0, r11
.cfi_endproc
.size __divsi3, . - __divsi3
#endif
#ifdef L__modsi3
.balign 4
.global __modsi3
.type __modsi3, @function
.cfi_startproc
__modsi3:
l.sflts r4, r0 /* abs(y) */
#if defined(__or1k_cmov__)
l.sub r5, r0, r4
l.cmov r4, r5, r4
#else
l.bnf 2f
l.sub r5, r0, r4
l.ori r4, r5, 0
2:
#endif
l.sflts r3, r0 /* x negative? */
l.bf 1f
l.ori r13, r9, 0 /* save lr */
/* Know that __udivmodsi3_internal does not clobber r13. */
.cfi_register 9, 13
/* X positive; no negate of the result required. */
l.jal __udivmodsi3_internal
l.nop
l.jr r13 /* return to saved lr */
l.ori r11, r12, 0 /* move remainder to rv */
/* X negative; negate both X and the result. */
1: l.jal __udivmodsi3_internal
l.sub r3, r0, r3
l.jr r13 /* return to saved lr */
l.sub r11, r0, r12 /* negate remainder to rv */
.cfi_endproc
.size __modsi3, .- __modsi3
#endif
|
4ms/metamodule-plugin-sdk
| 1,564
|
plugin-libc/libgcc/config/score/crtn.S
|
# crtn.S for Sunplus S+CORE
# Copyright (C) 2005-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file makes sure that the .init and .fini sections do in
# fact return.
#ifndef __pic__
.section .init, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
.section .fini, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
#else
.set pic
.section .init, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
.set pic
.section .fini, "ax", @progbits
lw r3, [r0, 20]
addi r0, 32
br r3
#endif
|
4ms/metamodule-plugin-sdk
| 3,342
|
plugin-libc/libgcc/config/score/crti.S
|
# crti.S for Sunplus S+CORE
#
# Copyright (C) 2005-2022 Free Software Foundation, Inc.
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by the
# Free Software Foundation; either version 3, or (at your option) any
# later version.
#
# This file is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# Under Section 7 of GPL version 3, you are granted additional
# permissions described in the GCC Runtime Library Exception, version
# 3.1, as published by the Free Software Foundation.
#
# You should have received a copy of the GNU General Public License and
# a copy of the GCC Runtime Library Exception along with this program;
# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
# <http://www.gnu.org/licenses/>.
# This file makes a stack frame for the contents of the .init and
# .fini sections.
.extern _stack
#ifndef __pic__
.section .init, "ax", @progbits
.weak _start
.ent _start
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_start:
la r28, _gp
la r8, __bss_start
la r9, __bss_end__
sub! r9, r8
srli! r9, 2
addi r9, -1
mtsr r9, sr0
li r9, 0
1:
sw r9, [r8]+, 4
bcnz 1b
la r0, _stack
jl _init
la r4, _end
jl _init_argv
jl exit
.end _start
.weak _init_argv
.ent
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_init_argv:
ldiu! r4, 0
ldiu! r5, 0
j main
.end _init_argv
.globl _init
.type _init, %function
_init:
addi r0, -32
sw r3, [r0, 20]
.section .fini, "ax", @progbits
.globl _fini
.type _fini, %function
_fini:
addi r0, -32
sw r3, [r0, 20]
#else
.section .init, "ax", @progbits
.set pic
.weak _start
.ent _start
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_start:
mv r29, r3
bl 0f
0:
.cpload r3
mv r3, r29
la r8, __bss_start
la r9, __bss_end__
sub! r9, r8
srli! r9, 2
addi r9, -1
mtsr r9, sr0
li r9, 0
1:
sw r9, [r8]+, 4
bcnz 1b
la r0, _stack
bl _init
la r4, _end
la r29, _init_argv
brl r29
la r29, exit
brl r29
.end _start
.weak _init_argv
.ent _init_argv
.frame r0, 0, r3, 0
.mask 0x00000000, 0
_init_argv:
ldiu! r4, 0
ldiu! r5, 0
la r29, main
brl r29
.end _init_argv
.globl _init
.type _init, %function
_init:
addi r0, -32
sw r3, [r0, 20]
.section .fini, "ax", @progbits
.globl _fini
.type _fini, %function
_fini:
addi r0, -32
sw r3, [r0, 20]
#endif
|
4ms/metamodule-plugin-sdk
| 1,778
|
plugin-libc/libgcc/config/epiphany/ieee-754/gtesf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
/* Assumptions: NaNs have all bits 10..30 and one of bit 0..9 set.
after sub: AC = ~Borrow.
clobber: TMP0
output: gt / gte indicates greater / greater or equal. */
FSTAB (__gtesf2,T_INT)
.global SYM(__gtesf2)
.balign 4
HIDDEN_FUNC(__gtesf2)
SYM(__gtesf2):
#ifndef FLOAT_FORMAT_MOTOROLA
mov TMP0,0xffff
movt TMP0,0x7f
add TMP0,TMP0,r0
eor TMP0,TMP0,r0
blt .Lret
mov TMP0,0xffff
movt TMP0,0x7f
add TMP0,TMP0,r1
#else
add TMP0,r0,0x3ff; check for r0 NaN
eor TMP0,TMP0,r0
blt .Lret
add TMP0,r1,0x3ff; check for r1 NaN
#endif
eor TMP0,TMP0,r1
blt .Lret
and TMP0,r0,r1
blt .Lneg
orr TMP0,r0,r1
lsl TMP0,TMP0,1
beq .Lret
sub TMP0,r0,r1
.Lret:
rts
.balign 4
.Lneg:
sub TMP0,r1,r0
rts
ENDFUNC(__gtesf2)
|
4ms/metamodule-plugin-sdk
| 3,976
|
plugin-libc/libgcc/config/epiphany/ieee-754/fast_div.S
|
/* Copyright (C) 2011-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
.section _fast_div_text,"a",@progbits;
.balign 8;
_fast_div_table:
.word 0x007fffff// mantissa mask
.word 0x40257ebb// hold constant a = 2.58586
.word 0x3f000000// hold constant 126 shifted to bits [30:23]
.word 0xc0ba2e88// hold constant b = -5.81818
.word 0x4087c1e8// hold constant c = 4.24242
.word 0x40000000// to hold constant 2 for Newton-Raphson iterations
.global SYM(__fast_recipsf2)
FUNC(__fast_recipsf2)
SYM(__fast_recipsf2):
//###################
//# input operands:
//###################
// Divisor
//R0
// Function address (used with negative offsets to read _fast_div_table)
//R1
/* Scratch registers: two single (TMP0/TMP5) and two pairs. */
#define P0L TMP1
#define P0H TMP2
#define P1L TMP3
#define P1H TMP4
//#########################################
//# Constants to be used in the algorithm
//#########################################
ldrd P0L , [ R1 , -3 ]
ldrd P1L , [ R1 , -2 ]
//#############################################################################
//# The Algorithm
//#
//# Operation: C=A/B
//# stage 1 - find the reciprocal 1/B according to the following scheme:
//# B = (2^E)*m (1<m<2, E=e-127)
//# 1/B = 1/((2^E)*m) = 1/((2^(E+1))*m1) (0.5<m1<1)
//# = (2^-(E+1))*(1/m1) = (2^E1)*(1/m1)
//#
//# Now we can find the new exponent:
//# e1 = E1+127 = -E-1+127 = -e+127-1+127 = 253-e **
//# 1/m1 alreadt has the exponent 127, so we have to add 126-e.
//# the exponent might underflow, which we can detect as a sign change.
//# Since the architeture uses flush-to-zero for subnormals, we can
//# give the result 0. then.
//#
//# The 1/m1 term with 0.5<m1<1 is approximated with the Chebyshev polynomial
//# 1/m1 = 2.58586*(m1^2) - 5.81818*m1 + 4.24242
//#
//# Next step is to use two iterations of Newton-Raphson algorithm to complete
//# the reciprocal calculation.
//#
//# Final result is achieved by multiplying A with 1/B
//#############################################################################
// R0 exponent and sign "replacement" into TMP0
AND TMP0,R0,P0L ;
ORR TMP0,TMP0,P1L
SUB TMP5,R0,TMP0 // R0 sign/exponent extraction into TMP5
// Calculate new mantissa
FMADD P1H,TMP0,P0H ;
// Calculate new exponent offset 126 - "old exponent"
SUB P1L,P1L,TMP5
ldrd P0L , [ R1 , -1 ]
FMADD P0L,TMP0,P1H ;
eor P1H,r0,P1L // check for overflow (N-BIT).
blt .Lret_0
// P0L exponent and sign "replacement"
sub P0L,P0L,TMP5
// Newton-Raphson iteration #1
MOV TMP0,P0H ;
FMSUB P0H,R0,P0L ;
FMUL P0L,P0H,P0L ;
// Newton-Raphson iteration #2
FMSUB TMP0,R0,P0L ;
FMUL R0,TMP0,P0L ;
jr lr
.Lret_0:ldrd P0L , [ R1 , -3 ]
lsr TMP0,r0,31 ; extract sign
lsl TMP0,TMP0,31
add P0L,P0L,r0 ; check for NaN input
eor P0L,P0L,r0
movgte r0,TMP0
jr lr
// Quotient calculation is expected by the caller: FMUL quotient,divident,R0
;
ENDFUNC(__fast_recipsf2)
|
4ms/metamodule-plugin-sdk
| 1,434
|
plugin-libc/libgcc/config/epiphany/ieee-754/uneqsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
FSTAB (__uneqsf2,T_INT)
.global SYM(__uneqsf2)
.balign 8,,2
HIDDEN_FUNC(__uneqsf2)
SYM(__uneqsf2):
sub TMP0,r0,r1
beq .Lret
orr TMP0,r0,r1
add TMP0,TMP0,TMP0
beq .Lret
mov TMP0,1
movt TMP0,0xff00
lsl TMP1,r0,1
sub TMP1,TMP0,TMP1
blteu .Lret
lsl TMP1,r1,1
sub TMP1,TMP0,TMP1
.Lret: rts /* uneq: lteu */
ENDFUNC(__uneqsf2)
|
4ms/metamodule-plugin-sdk
| 1,462
|
plugin-libc/libgcc/config/epiphany/ieee-754/eqsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
/* Assumption: NaNs have all bits 10..30 and one of bit 0..9 set. */
FSTAB (__eqsf2,T_INT)
.global SYM(__eqsf2)
.balign 4
HIDDEN_FUNC(__eqsf2)
SYM(__eqsf2):
sub TMP0,r0,r1
beq .Lno_bdiff
orr TMP0,r0,r1
add TMP0,TMP0,TMP0
rts
.Lno_bdiff:
#ifndef FLOAT_FORMAT_MOTOROLA
mov TMP0,0xffff
movt TMP0,0x7f
add TMP0,TMP0,r0
#else
add TMP0,r0,0x3ff
#endif
eor TMP0,TMP0,r0
lsr TMP0,TMP0,31
rts
ENDFUNC(__eqsf2)
|
4ms/metamodule-plugin-sdk
| 1,530
|
plugin-libc/libgcc/config/epiphany/ieee-754/ordsf2.S
|
/* Copyright (C) 2008-2022 Free Software Foundation, Inc.
Contributed by Embecosm on behalf of Adapteva, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "../epiphany-asm.h"
FSTAB (__ordsf2,T_INT)
.global SYM(__ordsf2)
.balign 8,,2
HIDDEN_FUNC(__ordsf2)
SYM(__ordsf2):
#ifndef FLOAT_FORMAT_MOTOROLA
mov TMP0,0
movt TMP0,0xff00
lsl TMP1,r0,1
sub TMP1,TMP1,TMP0
bgtu .Lret
lsl TMP1,r1,1
sub TMP1,TMP1,TMP0
.Lret: rts /* ordered: lteu */
#else
/* Assumption: NaNs have all bits 9..30 and one of bit 0..8 set. */
lsl TMP0,r0,1
add TMP0,TMP0,0x3fe
bgteu .Lret
lsl TMP0,r1,1
add TMP0,TMP0,0x3fe
.Lret: rts /* ordered: ltu */
#endif
ENDFUNC(__ordsf2)
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid45_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.45, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_45_4b
.type _nds32_vector_45_4b, @function
_nds32_vector_45_4b:
1:
j 1b
.size _nds32_vector_45_4b, .-_nds32_vector_45_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid40_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.40, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_40_4b
.type _nds32_vector_40_4b, @function
_nds32_vector_40_4b:
1:
j 1b
.size _nds32_vector_40_4b, .-_nds32_vector_40_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid15.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.15, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_15
.type _nds32_vector_15, @function
_nds32_vector_15:
1:
j 1b
.size _nds32_vector_15, .-_nds32_vector_15
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid18.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.18, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_18
.type _nds32_vector_18, @function
_nds32_vector_18:
1:
j 1b
.size _nds32_vector_18, .-_nds32_vector_18
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid32.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.32, "a"
.align 2
.weak _nds32_jmptbl_32
.type _nds32_jmptbl_32, @object
_nds32_jmptbl_32:
.word 0
.size _nds32_jmptbl_32, .-_nds32_jmptbl_32
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid01.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.01, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_01
.type _nds32_vector_01, @function
_nds32_vector_01:
1:
j 1b
.size _nds32_vector_01, .-_nds32_vector_01
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid32.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.32, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_32
.type _nds32_vector_32, @function
_nds32_vector_32:
1:
j 1b
.size _nds32_vector_32, .-_nds32_vector_32
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid00.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.00, "a"
.align 2
.weak _nds32_jmptbl_00
.type _nds32_jmptbl_00, @object
_nds32_jmptbl_00:
.word 0
.size _nds32_jmptbl_00, .-_nds32_jmptbl_00
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid12.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.12, "a"
.align 2
.weak _nds32_jmptbl_12
.type _nds32_jmptbl_12, @object
_nds32_jmptbl_12:
.word 0
.size _nds32_jmptbl_12, .-_nds32_jmptbl_12
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid53.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.53, "a"
.align 2
.weak _nds32_jmptbl_53
.type _nds32_jmptbl_53, @object
_nds32_jmptbl_53:
.word 0
.size _nds32_jmptbl_53, .-_nds32_jmptbl_53
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid12.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.12, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_12
.type _nds32_vector_12, @function
_nds32_vector_12:
1:
j 1b
.size _nds32_vector_12, .-_nds32_vector_12
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid27.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.27, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_27
.type _nds32_vector_27, @function
_nds32_vector_27:
1:
j 1b
.size _nds32_vector_27, .-_nds32_vector_27
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid44.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.44, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_44
.type _nds32_vector_44, @function
_nds32_vector_44:
1:
j 1b
.size _nds32_vector_44, .-_nds32_vector_44
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid56.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.56, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_56
.type _nds32_vector_56, @function
_nds32_vector_56:
1:
j 1b
.size _nds32_vector_56, .-_nds32_vector_56
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid58.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.58, "a"
.align 2
.weak _nds32_jmptbl_58
.type _nds32_jmptbl_58, @object
_nds32_jmptbl_58:
.word 0
.size _nds32_jmptbl_58, .-_nds32_jmptbl_58
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid40.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.40, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_40
.type _nds32_vector_40, @function
_nds32_vector_40:
1:
j 1b
.size _nds32_vector_40, .-_nds32_vector_40
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid40.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.40, "a"
.align 2
.weak _nds32_jmptbl_40
.type _nds32_jmptbl_40, @object
_nds32_jmptbl_40:
.word 0
.size _nds32_jmptbl_40, .-_nds32_jmptbl_40
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid49.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.49, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_49
.type _nds32_vector_49, @function
_nds32_vector_49:
1:
j 1b
.size _nds32_vector_49, .-_nds32_vector_49
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid53_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.53, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_53_4b
.type _nds32_vector_53_4b, @function
_nds32_vector_53_4b:
1:
j 1b
.size _nds32_vector_53_4b, .-_nds32_vector_53_4b
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid29_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.29, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_29_4b
.type _nds32_vector_29_4b, @function
_nds32_vector_29_4b:
1:
j 1b
.size _nds32_vector_29_4b, .-_nds32_vector_29_4b
|
4ms/metamodule-plugin-sdk
| 4,285
|
plugin-libc/libgcc/config/nds32/isr-library/excp_isr_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
#include "save_mac_regs.inc"
#include "save_fpu_regs.inc"
#include "save_fpu_regs_00.inc"
#include "save_fpu_regs_01.inc"
#include "save_fpu_regs_02.inc"
#include "save_fpu_regs_03.inc"
#include "save_all.inc"
#include "save_partial.inc"
#include "adj_intr_lvl.inc"
#include "restore_mac_regs.inc"
#include "restore_fpu_regs_00.inc"
#include "restore_fpu_regs_01.inc"
#include "restore_fpu_regs_02.inc"
#include "restore_fpu_regs_03.inc"
#include "restore_fpu_regs.inc"
#include "restore_all.inc"
#include "restore_partial.inc"
.section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */
.align 1
/*
First Level Handlers
1. First Level Handlers are invokded in vector section via jump instruction
with specific names for different configurations.
2. Naming Format: _nds32_e_SR_NT for exception handlers.
_nds32_i_SR_NT for interrupt handlers.
2.1 All upper case letters are replaced with specific lower case letters encodings.
2.2 SR: Saved Registers
sa: Save All regs (context)
ps: Partial Save (all caller-saved regs)
2.3 NT: Nested Type
ns: nested
nn: not nested
nr: nested ready
*/
/*
This is 4-byte vector size version.
The "_4b" postfix was added for 4-byte version symbol.
*/
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.globl _nds32_e_sa_ns_4b
.type _nds32_e_sa_ns_4b, @function
_nds32_e_sa_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_sa_nr_4b
.type _nds32_e_sa_nr_4b, @function
_nds32_e_sa_nr_4b:
#else /* Not nested handler. */
.globl _nds32_e_sa_nn_4b
.type _nds32_e_sa_nn_4b, @function
_nds32_e_sa_nn_4b:
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.globl _nds32_e_ps_ns_4b
.type _nds32_e_ps_ns_4b, @function
_nds32_e_ps_ns_4b:
#elif defined(NDS32_NESTED_READY)
.globl _nds32_e_ps_nr_4b
.type _nds32_e_ps_nr_4b, @function
_nds32_e_ps_nr_4b:
#else /* Not nested handler. */
.globl _nds32_e_ps_nn_4b
.type _nds32_e_ps_nn_4b, @function
_nds32_e_ps_nn_4b:
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
/*
This is 4-byte vector size version.
The vector id was restored into $lp in vector by compiler.
*/
#ifdef NDS32_SAVE_ALL_REGS
SAVE_ALL_4B
#else
SAVE_PARTIAL_4B
#endif
/* Prepare to call 2nd level handler. */
la $r2, _nds32_jmptbl_00
lw $r2, [$r2 + $r0 << #2]
ADJ_INTR_LVL /* Adjust INTR level. $r3 is clobbered. */
jral $r2
/* Restore used registers. */
#ifdef NDS32_SAVE_ALL_REGS
RESTORE_ALL
#else
RESTORE_PARTIAL
#endif
iret
#ifdef NDS32_SAVE_ALL_REGS
#if defined(NDS32_NESTED)
.size _nds32_e_sa_ns_4b, .-_nds32_e_sa_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_sa_nr_4b, .-_nds32_e_sa_nr_4b
#else /* Not nested handler. */
.size _nds32_e_sa_nn_4b, .-_nds32_e_sa_nn_4b
#endif /* endif for Nest Type */
#else /* not NDS32_SAVE_ALL_REGS */
#if defined(NDS32_NESTED)
.size _nds32_e_ps_ns_4b, .-_nds32_e_ps_ns_4b
#elif defined(NDS32_NESTED_READY)
.size _nds32_e_ps_nr_4b, .-_nds32_e_ps_nr_4b
#else /* Not nested handler. */
.size _nds32_e_ps_nn_4b, .-_nds32_e_ps_nn_4b
#endif /* endif for Nest Type */
#endif /* not NDS32_SAVE_ALL_REGS */
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid62.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.62, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_62
.type _nds32_vector_62, @function
_nds32_vector_62:
1:
j 1b
.size _nds32_vector_62, .-_nds32_vector_62
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid71_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.71, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_71_4b
.type _nds32_vector_71_4b, @function
_nds32_vector_71_4b:
1:
j 1b
.size _nds32_vector_71_4b, .-_nds32_vector_71_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid57.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.57, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_57
.type _nds32_vector_57, @function
_nds32_vector_57:
1:
j 1b
.size _nds32_vector_57, .-_nds32_vector_57
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid72_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.72, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_72_4b
.type _nds32_vector_72_4b, @function
_nds32_vector_72_4b:
1:
j 1b
.size _nds32_vector_72_4b, .-_nds32_vector_72_4b
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid65.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.65, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_65
.type _nds32_vector_65, @function
_nds32_vector_65:
1:
j 1b
.size _nds32_vector_65, .-_nds32_vector_65
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid57.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.57, "a"
.align 2
.weak _nds32_jmptbl_57
.type _nds32_jmptbl_57, @object
_nds32_jmptbl_57:
.word 0
.size _nds32_jmptbl_57, .-_nds32_jmptbl_57
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid14.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.14, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_14
.type _nds32_vector_14, @function
_nds32_vector_14:
1:
j 1b
.size _nds32_vector_14, .-_nds32_vector_14
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid15.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.15, "a"
.align 2
.weak _nds32_jmptbl_15
.type _nds32_jmptbl_15, @object
_nds32_jmptbl_15:
.word 0
.size _nds32_jmptbl_15, .-_nds32_jmptbl_15
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid26.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.26, "a"
.align 2
.weak _nds32_jmptbl_26
.type _nds32_jmptbl_26, @object
_nds32_jmptbl_26:
.word 0
.size _nds32_jmptbl_26, .-_nds32_jmptbl_26
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid55.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.55, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_55
.type _nds32_vector_55, @function
_nds32_vector_55:
1:
j 1b
.size _nds32_vector_55, .-_nds32_vector_55
|
4ms/metamodule-plugin-sdk
| 1,281
|
plugin-libc/libgcc/config/nds32/isr-library/jmptbl_vid52.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_jmptbl.52, "a"
.align 2
.weak _nds32_jmptbl_52
.type _nds32_jmptbl_52, @object
_nds32_jmptbl_52:
.word 0
.size _nds32_jmptbl_52, .-_nds32_jmptbl_52
|
4ms/metamodule-plugin-sdk
| 1,497
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid07.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.07, "ax"
#if __NDS32_ISR_VECTOR_SIZE_4__
/* The vector size is default 4-byte for v3 architecture. */
.vec_size 4
.align 2
#else
/* The vector size is default 16-byte for other architectures. */
.vec_size 16
.align 4
#endif
.weak _nds32_vector_07
.type _nds32_vector_07, @function
_nds32_vector_07:
1:
j 1b
.size _nds32_vector_07, .-_nds32_vector_07
|
4ms/metamodule-plugin-sdk
| 1,312
|
plugin-libc/libgcc/config/nds32/isr-library/vec_vid00_4b.S
|
/* c-isr library stuff of Andes NDS32 cpu for GNU compiler
Copyright (C) 2012-2022 Free Software Foundation, Inc.
Contributed by Andes Technology Corporation.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.
You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
.section .nds32_vector.00, "ax"
.vec_size 4
.align 2
.weak _nds32_vector_00_4b
.type _nds32_vector_00_4b, @function
_nds32_vector_00_4b:
1:
j 1b
.size _nds32_vector_00_4b, .-_nds32_vector_00_4b
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.