repo_id stringlengths 5 115 | size int64 590 5.01M | file_path stringlengths 4 212 | content stringlengths 590 5.01M |
|---|---|---|---|
vandercookking/h7_device_RTT | 2,589 | rt-thread/libcpu/arm/s3c24x0/context_rvds.S | ;/*
; * Copyright (c) 2006-2022, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-20 Bernard first version
; */
NOINT EQU 0xc0 ; disable interrupt in psr
AREA |.text|, CODE, READONLY, ALIGN=2
ARM
... |
vandercookking/h7_device_RTT | 53,898 | rt-thread/libcpu/arm/s3c24x0/start_rvds.S | ;/*****************************************************************************/
;/* S3C2440.S: Startup file for Samsung S3C440 */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> ... |
vandercookking/h7_device_RTT | 4,361 | rt-thread/libcpu/arm/realview-a8-vmm/context_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
#include <rtconfig.h>
#ifdef RT_USING_VMM
#include <vmm.h>
#endif
.section .text, "ax"
/*
* rt_base_t rt_hw... |
vandercookking/h7_device_RTT | 9,785 | rt-thread/libcpu/arm/realview-a8-vmm/start_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
#include <rtconfig.h>
#ifdef RT_USING_VMM
#include <vmm.h>
.equ orig_irq_isr, LINUX_VECTOR_POS+0x18
#else
... |
vandercookking/h7_device_RTT | 2,833 | rt-thread/libcpu/arm/realview-a8-vmm/cp15_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.globl rt_cpu_get_smp_id
rt_cpu_get_smp_id:
mrc p15, #0, r0, c0, c0, #5
bx lr
.globl rt_cpu_... |
vandercookking/h7_device_RTT | 7,549 | rt-thread/libcpu/arm/cortex-r4/context_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-01-20 Bernard first version
* 2011-07-22 Bernard added thumb mode porting
* 2013-05-24 Grissiom port to CCS
* 2013-05-26 Grissi... |
vandercookking/h7_device_RTT | 13,962 | rt-thread/libcpu/arm/cortex-r4/start_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
@-------------------------------------------------------------------------------
@ sys_core.asm
@
@ (c) Texas Instruments 2009-2013, All rights reserved.
@
#in... |
vandercookking/h7_device_RTT | 7,011 | rt-thread/libcpu/arm/cortex-m4/context_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs
; * 2012-01-01 aozima support c... |
vandercookking/h7_device_RTT | 7,122 | rt-thread/libcpu/arm/cortex-m4/context_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2009-10-11 Bernard first version
* 2012-01-01 aozima support context switch load/store FPU register.
* 2013-06-18 aozima add resto... |
vandercookking/h7_device_RTT | 6,982 | rt-thread/libcpu/arm/cortex-m4/context_rvds.S | ;/*
;* Copyright (c) 2006-2018, RT-Thread Development Team
;*
;* SPDX-License-Identifier: Apache-2.0
;*
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version.
; * 2012-01-01 aozima support context switch load/store FPU register.
; * 2013-06-18 aozima ad... |
vandercookking/h7_device_RTT | 5,779 | rt-thread/libcpu/arm/cortex-m0/context_iar.S | ;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r... |
vandercookking/h7_device_RTT | 6,278 | rt-thread/libcpu/arm/cortex-m0/context_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-01-25 Bernard first version
* 2012-06-01 aozima set pendsv priority to 0xFF.
* 2012-08-17 aozima fixed bug: store r8 - r11.
* 2013-02-2... |
vandercookking/h7_device_RTT | 5,903 | rt-thread/libcpu/arm/cortex-m0/context_rvds.S | ;/*
; * Copyright (c) 2006-2022, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Change Logs:
; * Date Author Notes
; * 2010-01-25 Bernard first version
; * 2012-06-01 aozima set pendsv priority to 0xFF.
; * 2012-08-17 aozima fixed bug: store r... |
vandercookking/h7_device_RTT | 6,016 | rt-thread/libcpu/arm/cortex-a/context_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
#include "rtconfig.h"
.section .text, "ax"
#ifdef RT_USING_SMP
#define rt_hw_interrupt_disable rt_hw_local_ir... |
vandercookking/h7_device_RTT | 16,692 | rt-thread/libcpu/arm/cortex-a/start_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
* 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks
* ... |
vandercookking/h7_device_RTT | 3,181 | rt-thread/libcpu/arm/cortex-a/cp15_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2013-07-05 Bernard the first version
*/
.globl rt_cpu_get_smp_id
rt_cpu_get_smp_id:
mrc p15, #0, r0, c0, c0, #5
bx lr
.globl rt_cpu_... |
vandercookking/h7_device_RTT | 10,121 | rt-thread/libcpu/avr32/uc3/exception_gcc.S | /* This file is part of the ATMEL AVR32-UC3-SoftwareFramework-1.6.0 Release */
/*This file is prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief Exception and interrupt vectors.
*
* This file maps all events supporte... |
vandercookking/h7_device_RTT | 2,732 | rt-thread/libcpu/avr32/uc3/context_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-03-27 Kyle First version
*/
#define AVR32_SR 0
#define AVR32_SR_GM_OFFSET 16
.text
/*
* rt_base_t rt_hw_interrupt_disable()
*/... |
vandercookking/h7_device_RTT | 4,120 | rt-thread/libcpu/blackfin/bf53x/context_vdsp.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-02-13 mojingxian First version
*/
.global _rt_hw_interrupt_disable;
.global _rt_hw_interrupt_enable;
.global _interrupt_thread_switch;
.extern _rt_interrup... |
vandercookking/h7_device_RTT | 4,021 | rt-thread/libcpu/v850/70f34/context_iar.S | #include "macdefs.inc"
name OS_Core
COMMON INTVEC:CODE
;********************************************************************
;
; function:
; description: Trap 0x10 vector used for context switch
; Right now, all TRAPs to $1x are trated the same way
;
org 50h
jr OSCtxSW
;**************... |
vandercookking/h7_device_RTT | 1,394 | rt-thread/libcpu/m16c/m16c62p/context_iar.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
* 2010-04-20 fify move p... |
vandercookking/h7_device_RTT | 1,219 | rt-thread/libcpu/m16c/m16c62p/context_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2010-04-09 fify the first version
* 2010-04-19 fify rewrite rt_hw_interrupt_disable/enable fuction
* 2010-04-20 fify move p... |
vandercookking/h7_device_RTT | 5,972 | rt-thread/libcpu/nios/nios_ii/context_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-02-14 aozima first implementation for Nios II
* 2011-02-20 aozima fix context&switch bug
*/
/**
* @addtogroup NIOS_II
*/
/*@{*/
.t... |
vandercookking/h7_device_RTT | 1,119 | rt-thread/libcpu/nios/nios_ii/vector.S | .set noat
.globl .Lexception_exit
.section .exceptions.exit.label
.Lexception_exit:
.section .exceptions.exit, "xa"
ldw r5, 68(sp)
/* get exception back */
ldw ea, 72(sp)
/* if(rt_thread_switch_interrupt_flag == 0) goto no_need_context */
ldw r4,%gprel(rt_thread_switch_interr... |
vandercookking/h7_device_RTT | 7,947 | rt-thread/libcpu/risc-v/common/context_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting implementation
* 2018/12/27 Jesven Add SMP support
* 2020/11/20 BalanceTWK Add FPU support... |
vandercookking/h7_device_RTT | 6,174 | rt-thread/libcpu/risc-v/common/interrupt_gcc.S | /*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023/01/17 WangShun The first version
* 2023/03/19 Flyingcys Add riscv_32e support
* 2023/08/09 HPMicro Fix the issue t0 was modified u... |
vandercookking/h7_device_RTT | 1,857 | rt-thread/libcpu/risc-v/juicevm/interrupt_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021/04/24 Juice The first version
*/
#include "cpuport.h"
.section .text.entry
.align 2
.global trap_entry
trap_entry:
/* save thread context ... |
vandercookking/h7_device_RTT | 2,013 | rt-thread/libcpu/risc-v/virt64/startup_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/01 Bernard The first version
* 2018/12/27 Jesven Add SMP support
* 2020/6/12 Xim Port to QEMU and remove SMP support
... |
vandercookking/h7_device_RTT | 2,620 | rt-thread/libcpu/risc-v/virt64/context_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting implementation
* 2018/12/27 Jesven Add SMP support
* 2021/02/02 lizhirui Add userspace s... |
vandercookking/h7_device_RTT | 2,348 | rt-thread/libcpu/risc-v/virt64/interrupt_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
* 2018/12/27 Jesven Add SMP schedule
* 2021/02/02 lizhirui Add userspace support
* 2021/12/24 ... |
vandercookking/h7_device_RTT | 2,289 | rt-thread/libcpu/risc-v/k210/startup_gcc.S | /*
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/01 Bernard The first version
* 2018/12/27 Jesven Add SMP support
*/
#define __ASSEMBLY__
#define MSTATUS_FS 0x00006000U /* ini... |
vandercookking/h7_device_RTT | 3,793 | rt-thread/libcpu/risc-v/k210/interrupt_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
* 2018/12/27 Jesven Add SMP schedule
*/
#define __ASSEMBLY__
#include "cpuport.h"
.section .te... |
vandercookking/h7_device_RTT | 1,836 | rt-thread/libcpu/risc-v/t-head/c906/startup_gcc.S | /*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/01 Bernard The first version
* 2018/12/27 Jesven Add SMP support
* 2020/6/12 Xim Port to QEMU and remove SMP support
... |
vandercookking/h7_device_RTT | 1,249 | rt-thread/libcpu/risc-v/t-head/c906/context_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/28 Bernard The unify RISC-V porting implementation
* 2018/12/27 Jesven Add SMP support
* 2021/02/02 lizhirui Add userspace s... |
vandercookking/h7_device_RTT | 2,607 | rt-thread/libcpu/risc-v/t-head/c906/interrupt_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/10/02 Bernard The first version
* 2018/12/27 Jesven Add SMP schedule
* 2021/02/02 lizhirui Add userspace support
* 2021/12/24 ... |
vandercookking/h7_device_RTT | 1,586 | rt-thread/libcpu/aarch64/common/vector_gcc.S | /*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
*/
.text
.globl system_vectors
.globl vector_exception
.globl vector_irq
.globl vector_fiq
system_vectors:
.align 11
.se... |
vandercookking/h7_device_RTT | 13,113 | rt-thread/libcpu/aarch64/common/context_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-05-18 Jesven the first version
* 2023-06-24 WangXiaoyao Support backtrace for user thread
*/
#include "rtconfig.h"
#include "asm-generic.h... |
vandercookking/h7_device_RTT | 1,295 | rt-thread/libcpu/aarch64/common/cpu_gcc.S | /*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2018-10-06 ZhaoXiaowei the first version
*/
.text
.globl rt_hw_get_current_el
rt_hw_get_current_el:
MRS X0, CurrentEL
CMP X0, 0xc
B.EQ 3f
CMP X0, 0x8
B.EQ 2f
... |
vandercookking/h7_device_RTT | 5,180 | rt-thread/libcpu/aarch64/common/cache.S | /*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-03-17 bigmagic first version
*/
/*
* void __asm_dcache_level(level)
*
* flush or invalidate one level cache.
*
* x0: cache level
... |
vandercookking/h7_device_RTT | 10,309 | rt-thread/libcpu/aarch64/cortex-a/entry_point.S | /*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Date Author Notes
* 2020-01-15 bigmagic the first version
* 2020-08-10 SummerGift support clang compiler
* 2023-04-29 GuEe-GUI support kernel's ARM64 boot header
*/
#inclu... |
vandercookking/h7_device_RTT | 8,114 | rt-thread/libcpu/arc/em/contex_gcc_mw.S | /*
* Copyright (c) 2018, Synopsys, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#define __ASSEMBLY__
#include "include/arc/arc.h"
#include "include/arc/arc_asm_common.h"
.global rt_interrupt_enter;
.global rt_interrupt_leave;
.global rt_thread_switch_interrupt_flag;
.global rt_interrupt_from_thread;
.global rt_... |
vandercookking/h7_device_RTT | 9,422 | rt-thread/components/lwp/arch/arm/cortex-a/lwp_gcc.S | /*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
* 2023-07-16 Shell Move part of the codes to C from asm in signal handling
*/
#include "rtconfig.h"
#incl... |
vandercookking/h7_device_RTT | 6,431 | rt-thread/components/lwp/arch/risc-v/rv64/lwp_gcc.S | /*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-10 Jesven first version
* 2021-02-03 lizhirui port to riscv64
* 2021-02-19 lizhirui port to new version of rt-smart
* 2022-1... |
vandercookking/h7_device_RTT | 11,984 | rt-thread/components/lwp/arch/aarch64/cortex-a/lwp_gcc.S | /*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-05-18 Jesven first version
* 2023-07-16 Shell Move part of the codes to C from asm in signal handling
*/
#ifndef __ASSEMBLY__
#defin... |
vandercookking/h7_device_RTT | 1,321 | rt-thread/components/lwp/arch/x86/i386/lwp_gcc.S | /*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-7-14 JasonHu first version
*/
#include "rtconfig.h"
.section .text.lwp
/*
* void lwp_switch_to_user(frame);
*/
.global lwp_switch_to_us... |
vectorpikachu/compiler | 6,531 | hello.S | .text
.globl main
main:
addi sp, sp, -352
entry:
li t0, 1
sw t0, 0(sp)
li t0, 0
sw t0, 4(sp)
lw t0, 0(sp)
sw t0, 8(sp)
lw t0, 8(sp)
li t1, 0
sub t1, t0, t1
snez t1, t1
sw t1, 12(sp)
lw t0, 12(sp)
bnez t0, then1
j short_circuit8
then1:
li t0, 1
sw t0, 4(sp)
li t0, 0
sw t0, 0(sp)... |
vectorpikachu/second-compiler | 18,174 | hello.S | .text
.globl init
init:
addi sp, sp, -144
init_0_entry_11:
j init_0_bb_2
init_0_bb_2:
mv t0, a0
sw t0, 16(sp)
li t0, 0
sw t0, 20(sp)
j init_0_while_entry_12
init_0_while_entry_12:
lw t0, 20(sp)
sw t0, 24(sp)
li t1, 10
slt t0, t0, t1
sw t0, 28(sp)
beqz t0, init_0_while_exit_9
j init_0_whi... |
VidyaBipin/rust_os | 2,086 | Usermode/rustrt0/armv8-helpers.S | .macro EXIDX method handle
/*
.long EXIDX_\method
.section .ARM.exidx.\method, #exidx
.globl EXIDX_\method
EXIDX_\method: .long \method - . - 0x80000000, \handle
.section .text
*/
.endm
.section .text
ENTRY(__aeabi_memcpy4)
ENTRY(__aeabi_memcpy8)
tst x2,x2
beq 2f
1:
LDR w3, [x1], #4
STR w3, [x0], #4
SUBS x2, x2, ... |
VidyaBipin/rust_os | 5,462 | Usermode/rustrt0/armv7-helpers.S | @
@ MAGIC MACRO
@
.macro EXIDX method handle
.long EXIDX_\method
.pushsection .ARM.exidx.\method, #exidx
.globl EXIDX_\method
EXIDX_\method: .long \method - . - 0x80000000, \handle
.popsection
.endm
#define ENTRY_(v) .globl v ; v:
.macro USER_LOG message
ldr r0, =9f
mov r1, #(10f - 9f)
mov r12, #0
svc #0
.pushsec... |
VidyaBipin/rust_os | 1,436 | Usermode/rustrt0/amd64.S |
#include "common.S"
.section .text.start
.extern main
.extern register_arguments
.weak start
start:
call *start_ra(%rip)
mov $0, %rdi
mov $0, %rsi
call *start_mn(%rip)
// Save return value for EXITPROCESS call
mov %rax, %rdi
mov $CORE_EXIT, %rax
syscall
ud2
start_ra: .quad register_arguments
start_mn: .q... |
VidyaBipin/rust_os | 1,436 | Kernel/Core/log_cfg.S |
#define LEVEL_LOG 5
#define LEVEL_DEBUG 6
#define LEVEL_TRACE 7
#if __SIZEOF_POINTER__ == 8
# define DEF_PTR(...) .quad __VA_ARGS__
# define LOG_CFG_ENT_PAD .long 0
#elif __SIZEOF_POINTER__ == 4
# define DEF_PTR(...) .long __VA_ARGS__
# define LOG_CFG_ENT_PAD
#endif
#define LOG_CFG_ENT(str, level) \
.set log_cfg_co... |
VidyaBipin/rust_os | 8,999 | Kernel/Core/arch/riscv64/start.S | // "Tifflin" Kernel
// - By John Hodge (Mutabah)
//
// Core/arch/riscv64/start.asm
// - RISC-V 64-bit boot shim
.option norvc #
#define KERNEL_BASE 0xFFFFFFFF00000000
#define SBI_BOOT 1
#
# Initial boot
#
.section .text.init
.global start
start:
#if SBI_BOOT
# SBI boot from qemu:
# a0 = HART ID
# a1 = FDT base
mv... |
VidyaBipin/rust_os | 10,245 | Kernel/Core/arch/armv8/start.S | //
//
//
#define KERNEL_BASE 0xFFFF800000000000
#define ENTRY(v) .globl v; .type v,"function"; v:
#define GLOBAL(v) .globl v; v:
#define PUSH(_t1,_t2) stp _t1,_t2, [sp, #-16]!
#define POP(_t1,_t2) ldp _t1,_t2, [sp], #16
#define PUSHA() \
PUSH(x29,x30); /* FP and LR */ \
PUSH(x16,x17); \
PUSH(x14,x15); \
PUSH(x12... |
VidyaBipin/rust_os | 12,064 | Kernel/Core/arch/armv7/start.S | @
@
@
#define KERNEL_BASE 0x80000000
#define ENTRY(v) .globl v; .type v,"function"; v:
#define GLOBAL(v) .globl v; v:
#if 1 || defined(PLATFORM_qemuvirt)
# define UART_BASE 0x09000000
# define RAM_START 0x40000000
#elif defined(PLATFORM_realviewpb)
# define UART_BASE 0x10009000
# define RAM_START 0x00000000
#endif
.... |
VidyaBipin/rust_os | 1,940 | Kernel/rundir/arm_bootloader/start.S |
// "platform-$(PLATFORM).h" is inserted by cpp
#define STACK_TOP (RAM_START+RAM_LENGTH)
#define ENTRY(n) .globl n ; n:
#include "../../../Usermode/rustrt0/armv7-helpers.S"
.extern _binary_______bin_kernel_armv7_bin_start
.section .text
b .
b .
b .
b .
b .
ENTRY(start)
mov sp, #STACK_TOP
mov r0, #UART_BASE
... |
VidyaBipin/rust_os | 1,815 | Bootloaders/arm/start.S |
// "platform-$(PLATFORM).h" is inserted by cpp
#define STACK_TOP (RAM_START+RAM_LENGTH)
#define ENTRY(n) .globl n ; n:
.extern _binary_______Kernel_bin_kernel_armv7_bin_start
.section .text
b .
b .
b .
b .
b .
ENTRY(start)
mov sp, #STACK_TOP
ldr r0, =UART_BASE
push {r0}
ldr r8, =_binary_______Kernel_bin... |
VidyaBipin/rust_os | 1,782 | Bootloaders/arm/start-bcm2708.S |
#define FDT_BASE 0x100 @ Placed here by the GPU
.extern bootloader_link_addr
.extern bootloader_size
.section .text
.globl start
start:
mov sp, #0x8000 @ Stick the stack just before the image
@ Relocate the bootloader so the kernel can be loaded to the bottom of RAM
mov r4, #0x8000 @ Source: Load address for b... |
VidyaBipin/rust_os | 2,324 | Bootloaders/aarch64/start.S |
// "platform-$(PLATFORM).h" is inserted by cpp
#define STACK_TOP (RAM_START+RAM_LENGTH)
#define ENTRY(n) .globl n ; n:
#include "../../Usermode/rustrt0/armv8-helpers.S"
.extern _binary_kernel_bin_start
.section .text
ENTRY(start)
mov x0, #STACK_TOP
mov sp, x0
mov x0, #UART_BASE
str x0, [sp, #-8]!
sub sp, sp,... |
violeteloiv/Solar-OS | 4,459 | src/boot.s | /* Rust's ASM block does not seem to default to at&t syntax. Force it with the
* following */
.att_syntax
/* Declare constants for the multiboot header. */
.set ALIGN, 1<<0 /* align loaded modules on page boundaries */
.set MEMINFO, 1<<1 /* provide memory map */
.set FLAGS, ALIGN | MEMI... |
violeteloiv/Solar-OS | 4,459 | src/boot.s | /* Rust's ASM block does not seem to default to at&t syntax. Force it with the
* following */
.att_syntax
/* Declare constants for the multiboot header. */
.set ALIGN, 1<<0 /* align loaded modules on page boundaries */
.set MEMINFO, 1<<1 /* provide memory map */
.set FLAGS, ALIGN | MEMI... |
vj4dsc/https-github.com-bytecodealliance-wasmtime | 4,165 | crates/fiber/src/unix/s390x.S | // A WORD OF CAUTION
//
// This entire file basically needs to be kept in sync with itself. It's not
// really possible to modify just one bit of this file without understanding
// all the other bits. Documentation tries to reference various bits here and
// there but try to make sure to read over everything before twe... |
vj4dsc/https-github.com-bytecodealliance-wasmtime | 4,052 | crates/runtime/src/arch/s390x.S | // Currently `global_asm!` isn't stable on s390x, so this is an external
// assembler file built with the `build.rs`.
.machine z13
.text
.hidden host_to_wasm_trampoline
.globl host_to_wasm_trampoline
.type host_to_wasm_trampoline,@function
.p2align 2
#define CONCAT2(a,... |
vladimirca2000/rust_minix | 4,242 | src/arch/exceptions.S | .section .text
// Exception vector table for AArch64
// Each entry is 0x80 bytes (128 bytes) apart
.align 11
.global exception_vector_table
exception_vector_table:
// Current EL with SP0
.align 7
curr_el_sp0_sync:
b default_exception_handler
.align 7
curr_el_sp0_irq:
b default_exception_handler
.align 7
cur... |
vmpl-dev/libvmpl-rs | 8,660 | src/start/dune.S | /*
* dune.S - assembly helper routines (e.g. system calls, interrupts, traps)
*/
#define __ASSEMBLY__
#include "vmpl-core.h"
#define USE_RDWRGSFS 1
#define MSR_FS_BASE 0xc0000100
#define GD_KT 0x10
#define GD_KD 0x18
#define GD_UD 0x28 | 0x03
#define GD_UT 0x30 | 0x03
/*
* Trap Frame Format
* NOTE: this ref... |
VR4sigma1/spectre2 | 10,572 | src/asm/keccakf1600_x86-64-win64.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.def __KeccakF1600; .scl 3; .type 32; .endef
.p2align 5
__KeccakF1600:
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.p2align 5
.L... |
VR4sigma1/spectre2 | 8,238 | src/asm/keccakf1600_x86-64-osx.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.p2align 5
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp L$oop
.p2align 5
L$oop:
movq -100(%rdi),%r8
mo... |
VR4sigma1/spectre2 | 8,619 | src/asm/keccakf1600_x86-64-elf.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.type __KeccakF1600,@function
.align 32
__KeccakF1600:
.cfi_startproc
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.align 32
.Loo... |
VR4sigma1/spectre2 | 10,572 | src/asm/keccakf1600_x86-64-mingw64.s | # Source: https://github.com/dot-asm/cryptogams/blob/master/x86_64/keccak1600-x86_64.pl
.text
.def __KeccakF1600; .scl 3; .type 32; .endef
.p2align 5
__KeccakF1600:
.byte 0xf3,0x0f,0x1e,0xfa
movq 60(%rdi),%rax
movq 68(%rdi),%rbx
movq 76(%rdi),%rcx
movq 84(%rdi),%rdx
movq 92(%rdi),%rbp
jmp .Loop
.p2align 5
.L... |
w1s3one805/Googvm | 1,406 | kernel_loader/src/test_elf.S | # Copyright 2022 The ChromiumOS Authors
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
# Build instructions:
# x86_64-linux-gnu-as test_elf.S -o test_elf.o
# x86_64-linux-gnu-ld test_elf.o -o test_elf.bin -T test_elf.ld
.intel_syntax noprefix
.section ... |
wangyanyu1817/Starry_homework | 1,598 | modules/axhal/linker.lds.S | OUTPUT_ARCH(%ARCH%)
BASE_ADDRESS = %KERNEL_BASE%;
ENTRY(_start)
SECTIONS
{
. = BASE_ADDRESS;
_skernel = .;
.text : ALIGN(4K) {
_stext = .;
*(.text.boot)
*(.text .text.*)
. = ALIGN(4K);
_etext = .;
}
.rodata : ALIGN(4K) {
_srodata = .;
*(.ro... |
wangyanyu1817/Starry_homework | 4,307 | modules/axhal/src/platform/x86_pc/multiboot.S | # Bootstrapping from 32-bit with the Multiboot specification.
# See https://www.gnu.org/software/grub/manual/multiboot/multiboot.html
.section .text.boot
.code32
.global _start
_start:
mov edi, eax # arg1: magic: 0x2BADB002
mov esi, ebx # arg2: multiboot info
jmp bsp_entry32
.bal... |
wangyanyu1817/Starry_homework | 1,965 | modules/axhal/src/platform/x86_pc/ap_start.S | # Boot application processors into the protected mode.
# Each non-boot CPU ("AP") is started up in response to a STARTUP
# IPI from the boot CPU. Section B.4.2 of the Multi-Processor
# Specification says that the AP will start in real mode with CS:IP
# set to XY00:0000, where XY is an 8-bit value sent with the
# STAR... |
wangyanyu1817/Starry_homework | 2,325 | modules/axhal/src/arch/riscv/trap.S | .macro SAVE_REGS, from_user
addi sp, sp, -{trapframe_size}
PUSH_GENERAL_REGS
csrr t0, sepc
csrr t1, sstatus
csrrw t2, sscratch, zero // save sscratch (sp) and zero it
STR t0, sp, 31 // tf.sepc
STR t1, sp, 32 // tf.sstatus
STR... |
wangyanyu1817/Starry_homework | 1,505 | modules/axhal/src/arch/x86_64/trap.S | .equ NUM_INT, 256
.altmacro
.macro DEF_HANDLER, i
.Ltrap_handler_\i:
.if \i == 8 || (\i >= 10 && \i <= 14) || \i == 17
# error code pushed by CPU
push \i # interrupt vector
jmp .Ltrap_common
.else
push 0 # fill in error code in TrapFrame
push \i # interrupt ... |
wangyanyu1817/Starry_homework | 4,435 | modules/axhal/src/arch/aarch64/trap.S | .macro clear_gp_regs
.irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
mov x\n, xzr
.endr
.endm
.macro SAVE_REGS, el
stp x0, x1, [sp]
stp x2, x3, [sp, 2 * 8]
stp x4, x5, [sp, 4 * 8]
stp x6, x7, [sp, 6 * 8]
stp x8, x9, [sp, 8 * 8]
... |
Wankupi/kernel | 3,572 | src/arch/trap.S | #define TRAP_FRAME_ADDR (0x0 - 0x1000 - 0x1000)
#define OFFSET_REGS 0x28
.extern kernel_trap_entry
.section .text._trap_entry_early
.global _trap_entry_early
.align 2
_trap_entry_early:
call kernel_trap_entry
j _trap_entry
.section .text.trampoline
.global _trap_entry
.align ... |
WashCout/PROJETO_INTEGRADOR_III_UNIVESP | 15,124 | ambientefrutos/Lib/site-packages/prophet/stan_model/cmdstan-2.33.1/stan/lib/stan_math/lib/tbb_2020.3/src/tbb/ia64-gas/atomic_support.s | // Copyright (c) 2005-2020 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law o... |
WashCout/PROJETO_INTEGRADOR_III_UNIVESP | 1,304 | ambientefrutos/Lib/site-packages/prophet/stan_model/cmdstan-2.33.1/stan/lib/stan_math/lib/tbb_2020.3/src/tbb/ia64-gas/log2.s | // Copyright (c) 2005-2020 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law o... |
WashCout/PROJETO_INTEGRADOR_III_UNIVESP | 1,270 | ambientefrutos/Lib/site-packages/prophet/stan_model/cmdstan-2.33.1/stan/lib/stan_math/lib/tbb_2020.3/src/tbb/ia64-gas/lock_byte.s | // Copyright (c) 2005-2020 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law o... |
WashCout/PROJETO_INTEGRADOR_III_UNIVESP | 2,687 | ambientefrutos/Lib/site-packages/prophet/stan_model/cmdstan-2.33.1/stan/lib/stan_math/lib/tbb_2020.3/src/tbb/ia64-gas/ia64_misc.s | // Copyright (c) 2005-2020 Intel Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law o... |
watertogas/risc_rust_os | 2,695 | os/src/trap/trap.S | .altmacro
.macro STORE_REGISTER n
sd x\n, \n*8(sp)
.endm
.macro LOAD_REGISTER n
ld x\n, \n*8(sp)
.endm
.section .text.trap
.global _user_trap_entry
.global _user_trap_return
.global _kernel_trap_entry
.global _kernel_trap_return
.align 2
_user_trap_entry:
#exchange stack, sscratch->u... |
weix2025/toy | 5,330 | deps/boringssl/linux-x86/crypto/test/trampoline-x86-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl abi_test_trampoline
.hidden abi_test_trampoline
.type abi_test_trampoline,@function
.al... |
weix2025/toy | 16,212 | deps/boringssl/linux-x86/crypto/fipsmodule/vpaes-x86-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
#ifdef BORINGSSL_DISPATCH_TEST
#endif
.align 64
.L_vpaes_consts:
.long 218628480,235210255,168... |
weix2025/toy | 11,526 | deps/boringssl/linux-x86/crypto/fipsmodule/md5-586-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl md5_block_asm_data_order
.hidden md5_block_asm_data_order
.type md5_block_asm_data_orde... |
weix2025/toy | 51,296 | deps/boringssl/linux-x86/crypto/fipsmodule/aesni-x86-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
#ifdef BORINGSSL_DISPATCH_TEST
#endif
.globl aes_hw_encrypt
.hidden aes_hw_encrypt
.type aes_h... |
weix2025/toy | 8,981 | deps/boringssl/linux-x86/crypto/fipsmodule/x86-mont-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl bn_mul_mont
.hidden bn_mul_mont
.type bn_mul_mont,@function
.align 16
bn_mul_mont:
.L_b... |
weix2025/toy | 67,825 | deps/boringssl/linux-x86/crypto/fipsmodule/sha1-586-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl sha1_block_data_order
.hidden sha1_block_data_order
.type sha1_block_data_order,@functi... |
weix2025/toy | 97,992 | deps/boringssl/linux-x86/crypto/fipsmodule/sha256-586-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl sha256_block_data_order
.hidden sha256_block_data_order
.type sha256_block_data_order,@... |
weix2025/toy | 5,668 | deps/boringssl/linux-x86/crypto/fipsmodule/ghash-ssse3-x86-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl gcm_gmult_ssse3
.hidden gcm_gmult_ssse3
.type gcm_gmult_ssse3,@function
.align 16
gcm_g... |
weix2025/toy | 49,847 | deps/boringssl/linux-x86/crypto/fipsmodule/sha512-586-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl sha512_block_data_order
.hidden sha512_block_data_order
.type sha512_block_data_order,@... |
weix2025/toy | 6,610 | deps/boringssl/linux-x86/crypto/fipsmodule/ghash-x86-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl gcm_init_clmul
.hidden gcm_init_clmul
.type gcm_init_clmul,@function
.align 16
gcm_init... |
weix2025/toy | 15,486 | deps/boringssl/linux-x86/crypto/fipsmodule/bn-586-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl bn_mul_add_words
.hidden bn_mul_add_words
.type bn_mul_add_words,@function
.align 16
bn... |
weix2025/toy | 17,356 | deps/boringssl/linux-x86/crypto/fipsmodule/co-586-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl bn_mul_comba8
.hidden bn_mul_comba8
.type bn_mul_comba8,@function
.align 16
bn_mul_comb... |
weix2025/toy | 19,414 | deps/boringssl/linux-x86/crypto/chacha/chacha-x86-linux.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86) && defined(__ELF__)
.text
.globl ChaCha20_ctr32
.hidden ChaCha20_ctr32
.type ChaCha20_ctr32,@function
.align 16
ChaCha20... |
weix2025/toy | 10,917 | deps/boringssl/win-aarch64/crypto/test/trampoline-armv8-win.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
#include <openssl/arm_arch.h>
.text
// abi_test_trampoline loads callee-saved registers from |s... |
weix2025/toy | 34,147 | deps/boringssl/win-aarch64/crypto/fipsmodule/sha256-armv8-win.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
// Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved.
//
// Licensed under the... |
weix2025/toy | 14,519 | deps/boringssl/win-aarch64/crypto/fipsmodule/ghashv8-armv8-win.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
#include <openssl/arm_arch.h>
#if __ARM_MAX_ARCH__>=7
.text
.arch armv8-a+crypto
.globl gcm_init... |
weix2025/toy | 16,139 | deps/boringssl/win-aarch64/crypto/fipsmodule/aesv8-armv8-win.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
#include <openssl/arm_arch.h>
#if __ARM_MAX_ARCH__>=7
.text
.arch armv8-a+crypto
.section .rodat... |
weix2025/toy | 31,029 | deps/boringssl/win-aarch64/crypto/fipsmodule/armv8-mont-win.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
#include <openssl/arm_arch.h>
.text
.globl bn_mul_mont
.def bn_mul_mont
.type 32
.endef
.al... |
weix2025/toy | 1,923 | deps/boringssl/win-aarch64/crypto/fipsmodule/bn-armv8-win.S | // This file is generated from a similarly-named Perl script in the BoringSSL
// source tree. Do not edit by hand.
#include <openssl/asm_base.h>
#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64) && defined(_WIN32)
#include <openssl/arm_arch.h>
.text
// BN_ULONG bn_add_words(BN_ULONG *rp, const BN_ULONG *ap, ... |
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