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stringlengths 5
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stsp/binutils-ia16
| 2,896
|
gas/testsuite/gas/arm/mve-vmov-1.s
|
.syntax unified
.thumb
.irp op0, s0, s1, s2, s4, s8, s16, s30, s31
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov \op0, \op1
vmov \op1, \op0
.endr
.endr
.macro vmov_rr, op0, op1
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op0, \op1, \op2
vmov \op2, \op0, \op1
.endr
vmov \op0, \op1, s0, s1
vmov \op0, \op1, s1, s2
vmov \op0, \op1, s2, s3
vmov \op0, \op1, s4, s5
vmov \op0, \op1, s8, s9
vmov \op0, \op1, s16, s17
vmov \op0, \op1, s30, s31
vmov s0, s1, \op0, \op1
vmov s1, s2, \op0, \op1
vmov s2, s3, \op0, \op1
vmov s4, s5, \op0, \op1
vmov s8, s9, \op0, \op1
vmov s16, s17, \op0, \op1
vmov s30, s31, \op0, \op1
.endm
.irp op0, r1, r2, r4, r7, r8, r10, r12, r14
vmov_rr r0, \op0
.endr
.irp op0, r0, r2, r4, r7, r8, r10, r12, r14
vmov_rr r1, \op0
.endr
.irp op0, r0, r1, r4, r7, r8, r10, r12, r14
vmov_rr r2, \op0
.endr
.irp op0, r0, r1, r2, r7, r8, r10, r12, r14
vmov_rr r4, \op0
.endr
.irp op0, r0, r1, r2, r4, r8, r10, r12, r14
vmov_rr r7, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r10, r12, r14
vmov_rr r8, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r12, r14
vmov_rr r10, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r10, r14
vmov_rr r12, \op0
.endr
.irp op0, r0, r1, r2, r4, r7, r8, r10, r12
vmov_rr r14, \op0
.endr
.macro vmov_qidx_r size, idx
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
vmov\size \op1[\idx], \op2
.endr
.endr
.endm
.irp idx, 0, 1, 2, 4, 8, 15, 13, 6
vmov_qidx_r .8, \idx
.endr
.irp idx, 0, 1, 2, 4, 7
vmov_qidx_r .16, \idx
.endr
.irp idx, 0, 1, 2, 3
vmov_qidx_r .32, \idx
.endr
.macro vmov_r_qidx size, idx
.irp op1, r0, r1, r2, r4, r7, r8, r10, r12, r14
.irp op2, q0, q1, q2, q4, q7
vmov\size \op1, \op2[\idx]
.endr
.endr
.endm
.irp data, .u8, .s8
.irp idx, 0, 1, 2, 4, 8, 15, 13, 6
vmov_r_qidx \data, \idx
.endr
.endr
.irp data, .u16, .s16
.irp idx, 0, 1, 2, 4, 7
vmov_r_qidx \data, \idx
.endr
.endr
.irp idx, 0, 1, 2, 3
vmov_r_qidx .32, \idx
.endr
vmov.i32 q0, #0
vmov.i32 q0, #255 @ 0x000000FF 000000FF
vmov.i32 q0, #65280 @ 0x0000FF00 0000FF00
vmov.i32 q0, #4278190080 @ 0xFF000000 FF000000
vmov.i32 q0, #16711680 @ 0x00FF0000 00FF0000
vmov.i16 q0, #0
vmov.i16 q0, #255 @ 0x00FF 00FF 00FF 00FF
vmov.i16 q0, #65280 @ 0xFF00 FF00 FF00 FF00
vmov.i8 q0, #0
vmov.i8 q0, #255 @ 0xFF FF FF FF FF FF FF FF
vmov.i64 q0, #18374686479671623680 @ 0xFF00000000000000
vmov.i64 q0, #71776119061217280 @ 0x00FF000000000000
vmov.i64 q0, #280375465082880 @ 0x0000FF0000000000
vmov.i64 q0, #1095216660480 @ 0x000000FF00000000
vmov.i64 q0, #4278190080 @ 0x00000000FF000000
vmov.i64 q0, #16711680 @ 0x00000000000FF0000
vmov.i64 q0, #65280 @ 0x0000000000000FF00
vmov.i64 q0, #255 @ 0x000000000000000FF
.irp op1, q0, q1, q2, q4, q7
.irp op2, q0, q1, q2, q4, q7
vmov \op1, \op2
.endr
.endr
.irp op1, d0, d1, d2, d4, d8, d15
.irp op2, d0, d1, d2, d4, d8, d15
vmov \op1, \op2
vmov.f64 \op1, \op2
.endr
.endr
|
stsp/binutils-ia16
| 4,907
|
gas/testsuite/gas/arm/armv8-2-fp16-simd.s
|
.macro f16_dq_ifsu reg0 reg1 reg2
.irp op, vabd.f16, vmax.f16, vmin.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_ifsu reg0 reg1 reg2
.irp op, vabdq.f16, vmaxq.f16, vminq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_abs_neg reg0 reg1
.irp op, vabs.f16, vneg.f16
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_q_abs_neg reg0 reg1
.irp op, vabsq.f16, vnegq.f16
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_fcmp reg0 reg1 reg2
.irp op, vacge.f16, vacgt.f16, vaclt.f16, vacle.f16, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_fcmp_imm0 reg0 reg1
.irp op, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
\op d\reg0, d\reg1, #0
\op q\reg0, q\reg1, #0
.endr
.endm
.macro f16_q_fcmp reg0 reg1 reg2
.irp op, vacgeq.f16, vacgtq.f16, vacltq.f16, vacleq.f16, vceqq.f16, vcgeq.f16, vcgtq.f16, vcleq.f16, vcltq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_addsub reg0 reg1 reg2
.irp op, vadd.f16, vsub.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_addsub reg0 reg1 reg2
.irp op, vaddq.f16, vsubq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_vmaxnm reg0 reg1 reg2
.irp op, vmaxnm.f16, vminnm.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_fmac reg0 reg1 reg2
.irp op, vfma.f16, vfms.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_fmacmaybe reg0 reg1 reg2
.irp op, vmla.f16, vmls.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_vrint reg0 reg1
.irp op, vrintz.f16, vrintx.f16, vrinta.f16, vrintn.f16, vrintp.f16, vrintm.f16
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_recip reg0 reg1
.irp op, vrecpe.f16, vrsqrte.f16
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_q_recip reg0 reg1
.irp op, vrecpeq.f16, vrsqrteq.f16
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_step reg0 reg1 reg2
.irp op, vrecps.f16, vrsqrts.f16
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_q_step reg0 reg1 reg2
.irp op, vrecpsq.f16, vrsqrtsq.f16
\op q\reg0, q\reg1, q\reg2
.endr
.endm
.macro f16_dq_cvt reg0 reg1
.irp op, vcvta.s16.f16, vcvtm.s16.f16, vcvtn.s16.f16, vcvtp.s16.f16, vcvta.u16.f16, vcvtm.u16.f16, vcvtn.u16.f16, vcvtp.u16.f16,
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_cvtz reg0 reg1
.irp op, vcvt.s16.f16, vcvt.u16.f16, vcvt.f16.s16, vcvt.f16.u16,
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endr
.endm
.macro f16_dq_cvtz_fixed reg0 reg1 imm
.irp op, vcvt.s16.f16, vcvt.u16.f16, vcvt.f16.s16, vcvt.f16.u16,
\op d\reg0, d\reg1, #\imm
\op q\reg0, q\reg1, #\imm
.endr
.endm
.macro f16_dq op reg0 reg1 reg2
\op d\reg0, d\reg1, d\reg2
\op q\reg0, q\reg1, q\reg2
.endm
.macro f16_d op reg0 reg1 reg2
\op d\reg0, d\reg1, d\reg2
.endm
.macro f16_q op reg0 reg1 reg2
\op q\reg0, q\reg1, q\reg2
.endm
.macro f16_dq_2 op reg0 reg1
\op d\reg0, d\reg1
\op q\reg0, q\reg1
.endm
.macro f16_d_2 op reg0 reg1
\op d\reg0, d\reg1
.endm
.macro f16_q_2 op reg0 reg1
\op q\reg0, q\reg1
.endm
func:
# neon_dyadic_if_su
f16_dq_ifsu 2 4 14
f16_q_ifsu 0 8 14
f16_d vabd.f16 1 3 15
f16_d vabd.f16 0 1 8
# neon_abs_neg
f16_dq_abs_neg 0 8
f16_q_abs_neg 2 6
f16_d_2 vabs.f16 7 3
f16_d_2 vneg.f16 9 1
# neon_fcmp
f16_dq_fcmp 2 4 14
f16_q_fcmp 0 8 14
# neon_addsub_if_i
f16_dq_addsub 2 4 14
f16_q_addsub 0 8 14
# neon_vmaxnm
f16_dq_vmaxnm 2 4 14
# neon_fmac
f16_dq_fmac 2 4 14
# neon_mac_maybe_scalar
f16_dq_fmacmaybe 2 4 14
# vrint
f16_dq_vrint 4 14
# neon_dyadic_if_i_d
f16_d vpadd.f16 4 8 14
# neon_recip_est
f16_dq_recip 4 8
f16_q_recip 0 10
# neon_step
f16_dq_step 8 10 12
f16_q_step 2 0 4
# neon_dyadic_if_su_d
f16_d vpmax.f16 4 8 14
f16_d vpmin.f16 10 8 2
# neon_mul
f16_d vmul.f16 4 8 14
f16_d vmul.f16 7 0 1
f16_q vmul.f16 2 8 0
# neon_cvt
f16_dq_cvt 6 12
# neon_cvtz
f16_dq_cvtz 14, 0
# neon_cvtz_fixed
f16_dq_cvtz_fixed 14, 0, 3
# neon_fcmp_imm0
f16_dq_fcmp_imm0 14, 2
.macro f16_d_by_scalar op reg0 reg1 reg2 idx
\op d\reg0, d\reg1, d\reg2[\idx]
.endm
.macro f16_q_by_scalar op reg0 reg1 reg2 idx
\op q\reg0, q\reg1, d\reg2[\idx]
.endm
.macro f16_dq_fmacmaybe_by_scalar reg0 reg1 reg2 idx
.irp op, vmla.f16, vmls.f16
\op d\reg0, d\reg1, d\reg2[\idx]
\op q\reg0, q\reg1, d\reg2[\idx]
.endr
.endm
# neon_mul (by scalar)
f16_d_by_scalar vmul.f16 7 0 1 0
f16_d_by_scalar vmul.f16 4 8 6 2
f16_q_by_scalar vmul.f16 2 8 0 1
f16_q_by_scalar vmul.f16 2 8 7 3
# neon_mac_maybe_scalar (by scalar)
f16_dq_fmacmaybe_by_scalar 2 4 1 0
f16_dq_fmacmaybe_by_scalar 1 8 7 3
|
stsp/binutils-ia16
| 9,347
|
gas/testsuite/gas/arm/sp-pc-validations-bad-t.s
|
.syntax unified
@ Enable Thumb mode
.thumb
.macro it_test opcode operands:vararg
itt eq
\opcode\()eq r15, \operands
moveq r0, r0
.endm
.macro it_testw opcode operands:vararg
itt eq
\opcode\()eq.w r15, \operands
moveq r0, r0
.endm
.macro LOAD operands:vararg
it_test ldr, \operands
.endm
.macro LOADw operands:vararg
it_testw ldr, \operands
.endm
@ Loads ===============================================================
@ LDR (register)
LOAD [r0]
LOAD [r0,#0]
LOAD [sp]
LOAD [sp,#0]
LOADw [r0]
LOADw [r0,#0]
LOAD [r0,#-4]
LOAD [r0],#4
LOAD [r0,#0]!
@ LDR (literal)
LOAD label
LOADw label
LOADw [pc, #-0]
@ LDR (register)
LOAD [r0, r1]
LOADw [r0, r1]
LOADw [r0, r1, LSL #2]
@ LDRB (immediate, Thumb)
ldrb pc, [r0,#4] @ low reg
@ldrb r0, [pc,#4] @ ALLOWED!
ldrb.w sp, [r0,#4] @ Unpredictable
ldrb.w pc, [r0,#4] @ => PLD
ldrb pc, [r0, #-4] @ => PLD
@ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT
ldrb pc, [r0],#4 @ BadReg
ldrb sp, [r0],#4 @ ditto
ldrb pc,[r0,#4]! @ ditto
ldrb sp,[r0,#4]! @ ditto
@ LDRB (literal)
ldrb pc,label @ => PLD
ldrb pc,[PC,#-0] @ => PLD (special case)
ldrb sp,label @ Unpredictable
ldrb sp,[PC,#-0] @ ditto
@ LDRB (register)
ldrb pc,[r0,r1] @ low reg
ldrb r0,[pc,r1] @ ditto
ldrb r0,[r1,pc] @ ditto
ldrb.w pc,[r0,r1,LSL #1] @ => PLD
ldrb.w sp,[r0,r1] @ Unpredictable
ldrb.w r2,[r0,pc,LSL #2] @ BadReg
ldrb.w r2,[r0,sp,LSL #2] @ ditto
@ LDRBT
ldrbt pc, [r0, #4] @ BadReg
ldrbt sp, [r0, #4] @ ditto
@ LDRD (immediate)
ldrd pc, r0, [r1] @ BadReg
ldrd sp, r0, [r1] @ ditto
ldrd r12, [r1] @ ditto
ldrd r14, [r1] @ ditto
ldrd r0, pc, [r1] @ ditto
ldrd r0, sp, [r1] @ ditto
ldrd pc, r0, [r1], #4 @ ditto
ldrd sp, r0, [r1], #4 @ ditto
ldrd r0, pc, [r1], #4 @ ditto
ldrd r0, sp, [r1], #4 @ ditto
ldrd r12, [r1], #4 @ ditto
ldrd r14, [r1], #4 @ ditto
ldrd pc, r0, [r1, #4]! @ ditto
ldrd sp, r0, [r1, #4]! @ ditto
ldrd r0, pc, [r1, #4]! @ ditto
ldrd r0, sp, [r1, #4]! @ ditto
ldrd r12, [r1, #4]! @ ditto
ldrd r14, [r1, #4]! @ ditto
@ LDRD (literal)
ldrd pc, r0, label @ BadReg
ldrd sp, r0, label @ ditto
ldrd r0, pc, label @ ditto
ldrd r0, sp, label @ ditto
ldrd pc, r0, [pc, #-0] @ ditto
ldrd sp, r0, [pc, #-0] @ ditto
ldrd r0, pc, [pc, #-0] @ ditto
ldrd r0, sp, [pc, #-0] @ ditto
@ LDRD (register): ARM only
@ LDREX/B/D/H
ldrex pc, [r0] @ BadReg
ldrex sp, [r0] @ ditto
ldrex r0, [pc] @ Unpredictable
ldrexb pc, [r0] @ BadReg
ldrexb sp, [r0] @ ditto
ldrexb r0, [pc] @ Unpredictable
ldrexd pc, r0, [r1] @ BadReg
ldrexd sp, r0, [r1] @ ditto
ldrexd r0, pc, [r1] @ ditto
ldrexd r0, sp, [r1] @ ditto
ldrexd r0, r1, [pc] @ Unpredictable
ldrexh pc, [r0] @ BadReg
ldrexh sp, [r0] @ ditto
ldrexh r0, [pc] @ Unpredictable
@ LDRH (immediate)
ldrh pc, [r0] @ low reg
ldrh pc, [r0, #4] @ ditto
@ldrh r0, [pc] @ ALLOWED!
@ldrh r0, [pc, #4] @ ditto
ldrh.w pc, [r0] @ => Unallocated memory hints
ldrh.w pc, [r0, #4] @ ditto
ldrh.w sp, [r0] @ Unpredictable
ldrh.w sp, [r0, #4] @ ditto
ldrh pc, [r0, #-3] @ => Unallocated memory hint
@ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT
ldrh pc,[r0],#4 @ BadReg
ldrh sp,[r0],#4 @ ditto
ldrh pc,[r0,#4]! @ ditto
ldrh sp,[r0,#4]! @ ditto
@ LDRH (literal)
ldrh pc, label @ Unallocated memory hint
ldrh pc, [pc, #-0] @ ditto
ldrh sp, label @ Unpredictable
ldrh sp, [pc, #-0] @ ditto
@ LDRH (register)
ldrh pc, [r0, r1] @ low reg
ldrh r0, [pc, r1] @ ditto
ldrh r0, [r1, pc] @ ditto
ldrh.w pc,[r0,r1,LSL #1] @ => Unallocated memory hints
ldrh.w sp,[r0,r1,LSL #1] @ Unpredictable
ldrh.w r2,[r0,pc,LSL #1] @ ditto
ldrh.w r2,[r0,sp,LSL #1] @ ditto
@ LDRHT
ldrht pc, [r0, #4] @ BadReg
ldrht sp, [r0, #4] @ ditto
@ LDRSB (immediate)
ldrsb pc, [r0, #4] @ => PLI
@ldrsb r0, [pc, #4] => LDRSB (literal)
ldrsb sp, [r0, #4] @ Unpredictable
ldrsb pc, [r0, #-4] @ => PLI
ldrsb sp,[r0,#-4] @ BadReg
ldrsb pc,[r0],#4 @ ditto
ldrsb sp,[r0],#4 @ ditto
ldrsb pc,[r0,#4]! @ ditto
ldrsb sp,[r0,#4]! @ ditto
@ LDRSB (literal)
ldrsb pc, label @ => PLI
ldrsb pc, [pc, #-0] @ => PLI
ldrsb sp, label @ Unpredictable
ldrsb sp, [pc, #-0] @ ditto
@ LDRSB (register)
ldrsb pc, [r0, r1] @ low reg
ldrsb r0, [pc, r1] @ ditto
ldrsb r0, [r1, pc] @ ditto
ldrsb.w pc, [r0, r1, LSL #2] @ => PLI
@ldrsb.w r0, [pc, r0, LSL #2] => LDRSB (literal)
ldrsb.w sp, [r0, r1, LSL #2] @ Unpredictable
ldrsb.w r2, [r0, pc, LSL #2] @ ditto
ldrsb.w r2, [r0, sp, LSL #2] @ ditto
@ LDRSBT
@ldrsbt r0, [pc, #4] => LDRSB (literal)
ldrsbt pc, [r0, #4] @ BadReg
ldrsbt sp, [r0, #4] @ ditto
@ LDRSH (immediate)
@ldrsh r0,[pc,#4] => LDRSH (literal)
ldrsh pc,[r0,#4] @ => Unallocated memory hints
ldrsh sp,[r0,#4] @ Unpredictable
ldrsh pc, [r0, #-4] @ => Unallocated memory hints
ldrsh pc,[r0],#4 @ BadReg
ldrsh pc,[r0,#4]! @ ditto
ldrsh sp,[r0,#-4] @ ditto
ldrsh sp,[r0],#4 @ ditto
ldrsh sp,[r0,#4]! @ ditto
@ LDRSH (literal)
ldrsh pc, label @ => Unallocated memory hints
ldrsh sp, label @ Unpredictable
ldrsh sp, [pc,#-0] @ ditto
@ LDRSH (register)
ldrsh pc,[r0,r1] @ low reg
ldrsh r0,[pc,r1] @ ditto
ldrsh r0,[r1,pc] @ ditto
@ldrsh.w r0,[pc,r1,LSL #3] => LDRSH (literal)
ldrsh.w pc,[r0,r1,LSL #3] @ => Unallocated memory hints
ldrsh.w sp,[r0,r1,LSL #3] @ Unpredictable
ldrsh.w r0,[r1,sp,LSL #3] @ BadReg
ldrsh.w r0,[r1,pc,LSL #3] @ ditto
@ LDRSHT
@ldrsht r0,[pc,#4] => LDRSH (literal)
ldrsht pc,[r0,#4] @ BadReg
ldrsht sp,[r0,#4] @ ditto
@ LDRT
@ldrt r0,[pc,#4] => LDR (literal)
ldrt pc,[r0,#4] @ BadReg
ldrt sp,[r0,#4] @ ditto
@ Stores ==============================================================
@ STR (immediate, Thumb)
str pc, [r0, #4] @ Unpredictable
str.w r0, [pc, #4] @ Undefined
str r0, [pc, #-4] @ ditto
str r0, [pc], #4 @ ditto
str r0, [pc, #4]! @ ditto
@ STR (register)
str.w r0,[pc,r1] @ Undefined
str.w r0,[pc,r1,LSL #2] @ ditto
@str.w pc,[r0,r1{,LSL #<imm2>}] @ Unpredictable
@str.w r1,[r0,sp{,LSL #<imm2>}] @ ditto
@str.w r1,[r0,pc{,LSL #<imm2>}] @ ditto
@ STRB (immediate, Thumb)
strb.w r0,[pc,#4] @ Undefined
strb.w pc,[r0,#4] @ Unpredictable
strb.w sp,[r0,#4] @ ditto
strb r0,[pc,#-4] @ Undefined
strb r0,[pc],#4 @ ditto
strb r0,[pc,#4]! @ ditto
strb pc,[r0,#-4] @ Unpredictable
strb pc,[r0],#4 @ ditto
strb pc,[r0,#4]! @ ditto
strb sp,[r0,#-4] @ ditto
strb sp,[r0],#4 @ ditto
strb sp,[r0,#4]! @ ditto
@ STRB (register)
strb.w r0,[pc,r1] @ Undefined
strb.w r0,[pc,r1,LSL #2] @ ditto
strb.w pc,[r0,r1] @ Unpredictable
strb.w pc,[r0,r1,LSL #2] @ ditto
strb.w sp,[r0,r1] @ ditto
strb.w sp,[r0,r1,LSL #2] @ ditto
strb.w r0,[r1,pc] @ ditto
strb.w r0,[r1,pc,LSL #2] @ ditto
strb.w r0,[r1,sp] @ ditto
strb.w r0,[r1,sp,LSL #2] @ ditto
@ STRBT
strbt r0,[pc,#4] @ Undefined
strbt pc,[r0,#4] @ Unpredictable
strbt sp,[r0,#4] @ ditto
@ STRD (immediate)
strd r0,r1,[pc,#4] @ Unpredictable
strd r0,r1,[pc],#4 @ ditto
strd r0,r1,[pc,#4]! @ ditto
strd pc,r0,[r1,#4] @ ditto
strd pc,r0,[r1],#4 @ ditto
strd pc,r0,[r1,#4]! @ ditto
strd sp,r0,[r1,#4] @ ditto
strd sp,r0,[r1],#4 @ ditto
strd sp,r0,[r1,#4]! @ ditto
strd r0,pc,[r1,#4] @ ditto
strd r0,pc,[r1],#4 @ ditto
strd r0,pc,[r1,#4]! @ ditto
strd r0,sp,[r1,#4] @ ditto
strd r0,sp,[r1],#4 @ ditto
strd r0,sp,[r1,#4]! @ ditto
@ STRD (register)
@No thumb.
@ STREX
strex pc,r0,[r1] @ Unpredictable
strex pc,r0,[r1,#4] @ ditto
strex sp,r0,[r1] @ ditto
strex sp,r0,[r1,#4] @ ditto
strex r0,pc,[r1] @ ditto
strex r0,pc,[r1,#4] @ ditto
strex r0,sp,[r1] @ ditto
strex r0,sp,[r1,#4] @ ditto
strex r0,r1,[pc] @ ditto
strex r0,r1,[pc,#4] @ ditto
@ STREXB
strexb pc,r0,[r1] @ Unpredictable
strexb sp,r0,[r1] @ ditto
strexb r0,pc,[r1] @ ditto
strexb r0,sp,[r1] @ ditto
strexb r0,r1,[pc] @ ditto
@ STREXD
strexd pc,r0,r1,[r2] @ Unpredictable
strexd sp,r0,r1,[r2] @ ditto
strexd r0,pc,r1,[r2] @ ditto
strexd r0,sp,r1,[r2] @ ditto
strexd r0,r1,pc,[r2] @ ditto
strexd r0,r1,sp,[r2] @ ditto
strexd r0,r1,r2,[pc] @ ditto
@ STREXH
strexh pc,r0,[r1] @ Unpredictable
strexh sp,r0,[r1] @ ditto
strexh r0,pc,[r1] @ ditto
strexh r0,sp,[r1] @ ditto
strexh r0,r1,[pc] @ ditto
@ STRH (immediate, Thumb)
strh.w r0,[pc] @ Undefined
strh.w r0,[pc,#4] @ ditto
strh r0,[pc,#-4] @ ditto
strh r0,[pc],#4 @ ditto
strh r0,[pc,#4]! @ ditto
@ STRH (register)
strh.w r0,[pc,r1] @ Undefined
strh.w r0,[pc,r1,LSL #2] @ ditto
strh.w pc,[r0,#4] @ Unpredictable
strh.w pc,[r0] @ ditto
strh.w sp,[r0,#4] @ ditto
strh.w sp,[r0] @ ditto
strh pc,[r0,#-4] @ ditto
strh pc,[r0],#4 @ ditto
strh pc,[r0,#4]! @ ditto
strh sp,[r0,#-4] @ ditto
strh sp,[r0],#4 @ ditto
strh sp,[r0,#4]! @ ditto
strh.w pc,[r0,r1] @ ditto
strh.w sp,[r0,r1] @ ditto
strh.w r0,[r1,pc] @ ditto
strh.w r0,[r1,sp] @ ditto
strh.w pc,[r0,r1,LSL #2] @ ditto
strh.w sp,[r0,r1,LSL #2] @ ditto
strh.w r0,[r1,pc,LSL #2] @ ditto
strh.w r0,[r1,sp,LSL #2] @ ditto
@ STRHT
strht r0,[pc,#4] @ Undefined
strht pc,[r0,#4] @ Unpredictable
strht sp,[pc,#4] @ ditto
@ STRT
strt r0,[pc,#4] @ Undefined
strt pc,[r0,#4] @ Unpredictable
strt sp,[r0,#4] @ ditto
@ ============================================================================
.label:
ldr r0, [r1]
|
stsp/binutils-ia16
| 1,461
|
gas/testsuite/gas/arm/mve-vstld.s
|
.syntax unified
.thumb
.macro all_vstld2 op
.irp part, 0, 1
.irp size, .8, .16, .32
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op\()\part\()\size {q0, q1}, [\op2]
\op\()\part\()\size {q1, q2}, [\op2]
\op\()\part\()\size {q2, q3}, [\op2]
\op\()\part\()\size {q3, q4}, [\op2]
\op\()\part\()\size {q4, q5}, [\op2]
\op\()\part\()\size {q5, q6}, [\op2]
\op\()\part\()\size {q6, q7}, [\op2]
.endr
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op\()\part\()\size {q0, q1}, [\op2]!
\op\()\part\()\size {q1, q2}, [\op2]!
\op\()\part\()\size {q2, q3}, [\op2]!
\op\()\part\()\size {q3, q4}, [\op2]!
\op\()\part\()\size {q4, q5}, [\op2]!
\op\()\part\()\size {q5, q6}, [\op2]!
\op\()\part\()\size {q6, q7}, [\op2]!
.endr
.endr
.endr
.endm
.macro all_vstld4 op
.irp part, 0, 1, 2, 3
.irp size, .8, .16, .32
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
\op\()\part\()\size {q0, q1, q2, q3}, [\op2]
\op\()\part\()\size {q1, q2, q3, q4}, [\op2]
\op\()\part\()\size {q2, q3, q4, q5}, [\op2]
\op\()\part\()\size {q3, q4, q5, q6}, [\op2]
\op\()\part\()\size {q4, q5, q6, q7}, [\op2]
.endr
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r14
\op\()\part\()\size {q0, q1, q2, q3}, [\op2]!
\op\()\part\()\size {q1, q2, q3, q4}, [\op2]!
\op\()\part\()\size {q2, q3, q4, q5}, [\op2]!
\op\()\part\()\size {q3, q4, q5, q6}, [\op2]!
\op\()\part\()\size {q4, q5, q6, q7}, [\op2]!
.endr
.endr
.endr
.endm
all_vstld2 vst2
all_vstld2 vld2
all_vstld4 vst4
all_vstld4 vld4
|
stsp/binutils-ia16
| 5,464
|
gas/testsuite/gas/arm/mve-vstld-bad.s
|
.syntax unified
.thumb
vst20.8 {q0, q2}, [r0]
vst20.8 {q0, q1, q2}, [r0]
vst20.8 {q0}, [r0]
vst20.8 {q0, q1}, [pc]
vst20.8 {q0, q1}, [pc]!
vst20.8 {q0, q1}, [sp]!
vst20.8 {q3, q2}, [r0]
vst20.64 {q0, q1}, [r0]
vst21.8 {q0, q2}, [r0]
vst21.8 {q0, q1, q2}, [r0]
vst21.8 {q0}, [r0]
vst21.8 {q0, q1}, [pc]
vst21.8 {q0, q1}, [pc]!
vst21.8 {q0, q1}, [sp]!
vst21.8 {q3, q2}, [r0]
vst21.64 {q0, q1}, [r0]
vst40.8 {q0, q2, q3, q4}, [r0]
vst40.8 {q0, q1, q3, q4}, [r0]
vst40.8 {q0, q1, q2, q4}, [r0]
vst40.8 {q3, q1, q2, q3}, [r0]
vst40.8 {q0, q1, q2, q3, q4}, [r0]
vst40.8 {q0, q1, q2}, [r0]
vst40.8 {q0, q1}, [r0]
vst40.8 {q0}, [r0]
vst40.8 {q0, q1, q2, q3}, [pc]
vst40.8 {q0, q1, q2, q3}, [pc]!
vst40.8 {q0, q1, q2, q3}, [sp]!
vst40.64 {q0, q1, q2, q3}, [r0]
vst41.8 {q0, q2, q3, q4}, [r0]
vst41.8 {q0, q1, q3, q4}, [r0]
vst41.8 {q0, q1, q2, q4}, [r0]
vst41.8 {q3, q1, q2, q3}, [r0]
vst41.8 {q0, q1, q2, q3, q4}, [r0]
vst41.8 {q0, q1, q2}, [r0]
vst41.8 {q0, q1}, [r0]
vst41.8 {q0}, [r0]
vst41.8 {q0, q1, q2, q3}, [pc]
vst41.8 {q0, q1, q2, q3}, [pc]!
vst41.8 {q0, q1, q2, q3}, [sp]!
vst41.64 {q0, q1, q2, q3}, [r0]
vst42.8 {q0, q2, q3, q4}, [r0]
vst42.8 {q0, q1, q3, q4}, [r0]
vst42.8 {q0, q1, q2, q4}, [r0]
vst42.8 {q3, q1, q2, q3}, [r0]
vst42.8 {q0, q1, q2, q3, q4}, [r0]
vst42.8 {q0, q1, q2}, [r0]
vst42.8 {q0, q1}, [r0]
vst42.8 {q0}, [r0]
vst42.8 {q0, q1, q2, q3}, [pc]
vst42.8 {q0, q1, q2, q3}, [pc]!
vst42.8 {q0, q1, q2, q3}, [sp]!
vst42.64 {q0, q1, q2, q3}, [r0]
vst43.8 {q0, q2, q3, q4}, [r0]
vst43.8 {q0, q1, q3, q4}, [r0]
vst43.8 {q0, q1, q2, q4}, [r0]
vst43.8 {q3, q1, q2, q3}, [r0]
vst43.8 {q0, q1, q2, q3, q4}, [r0]
vst43.8 {q0, q1, q2}, [r0]
vst43.8 {q0, q1}, [r0]
vst43.8 {q0}, [r0]
vst43.8 {q0, q1, q2, q3}, [pc]
vst43.8 {q0, q1, q2, q3}, [pc]!
vst43.8 {q0, q1, q2, q3}, [sp]!
vst43.64 {q0, q1, q2, q3}, [r0]
vst1.8 {q0, q1}, [r0]
vst2.8 {q0, q1}, [r0]
vst3.8 {q0, q1}, [r0]
vst4.8 {q0, q1}, [r0]
vst23.32 {q0, q1}, [r0]
vst44.32 {q0, q1, q2, q3}, [r0]
vld20.8 {q0, q2}, [r0]
vld20.8 {q0, q1, q2}, [r0]
vld20.8 {q0}, [r0]
vld20.8 {q0, q1}, [pc]
vld20.8 {q0, q1}, [pc]!
vld20.8 {q0, q1}, [sp]!
vld20.8 {q3, q2}, [r0]
vld20.64 {q0, q1}, [r0]
vld21.8 {q0, q2}, [r0]
vld21.8 {q0, q1, q2}, [r0]
vld21.8 {q0}, [r0]
vld21.8 {q0, q1}, [pc]
vld21.8 {q0, q1}, [pc]!
vld21.8 {q0, q1}, [sp]!
vld21.8 {q3, q2}, [r0]
vld21.64 {q0, q1}, [r0]
vld40.8 {q0, q2, q3, q4}, [r0]
vld40.8 {q0, q1, q3, q4}, [r0]
vld40.8 {q0, q1, q2, q4}, [r0]
vld40.8 {q3, q1, q2, q3}, [r0]
vld40.8 {q0, q1, q2, q3, q4}, [r0]
vld40.8 {q0, q1, q2}, [r0]
vld40.8 {q0, q1}, [r0]
vld40.8 {q0}, [r0]
vld40.8 {q0, q1, q2, q3}, [pc]
vld40.8 {q0, q1, q2, q3}, [pc]!
vld40.8 {q0, q1, q2, q3}, [sp]!
vld40.64 {q0, q1, q2, q3}, [r0]
vld41.8 {q0, q2, q3, q4}, [r0]
vld41.8 {q0, q1, q3, q4}, [r0]
vld41.8 {q0, q1, q2, q4}, [r0]
vld41.8 {q3, q1, q2, q3}, [r0]
vld41.8 {q0, q1, q2, q3, q4}, [r0]
vld41.8 {q0, q1, q2}, [r0]
vld41.8 {q0, q1}, [r0]
vld41.8 {q0}, [r0]
vld41.8 {q0, q1, q2, q3}, [pc]
vld41.8 {q0, q1, q2, q3}, [pc]!
vld41.8 {q0, q1, q2, q3}, [sp]!
vld41.64 {q0, q1, q2, q3}, [r0]
vld42.8 {q0, q2, q3, q4}, [r0]
vld42.8 {q0, q1, q3, q4}, [r0]
vld42.8 {q0, q1, q2, q4}, [r0]
vld42.8 {q3, q1, q2, q3}, [r0]
vld42.8 {q0, q1, q2, q3, q4}, [r0]
vld42.8 {q0, q1, q2}, [r0]
vld42.8 {q0, q1}, [r0]
vld42.8 {q0}, [r0]
vld42.8 {q0, q1, q2, q3}, [pc]
vld42.8 {q0, q1, q2, q3}, [pc]!
vld42.8 {q0, q1, q2, q3}, [sp]!
vld42.64 {q0, q1, q2, q3}, [r0]
vld43.8 {q0, q2, q3, q4}, [r0]
vld43.8 {q0, q1, q3, q4}, [r0]
vld43.8 {q0, q1, q2, q4}, [r0]
vld43.8 {q3, q1, q2, q3}, [r0]
vld43.8 {q0, q1, q2, q3, q4}, [r0]
vld43.8 {q0, q1, q2}, [r0]
vld43.8 {q0, q1}, [r0]
vld43.8 {q0}, [r0]
vld43.8 {q0, q1, q2, q3}, [pc]
vld43.8 {q0, q1, q2, q3}, [pc]!
vld43.8 {q0, q1, q2, q3}, [sp]!
vld43.64 {q0, q1, q2, q3}, [r0]
vld1.8 {q0, q1}, [r0]
vld2.8 {q0, q1}, [r0]
vld3.8 {q0, q1}, [r0]
vld4.8 {q0, q1}, [r0]
vld23.32 {q0, q1}, [r0]
vld44.32 {q0, q1, q2, q3}, [r0]
.macro cond2 op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().32 {q0, q1}, [r0]
.endr
.endm
.macro cond4 op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().32 {q0, q1, q2, q3}, [r0]
.endr
.endm
cond2 vst20
cond2 vst21
cond4 vst40
cond4 vst41
cond4 vst42
cond4 vst43
vpste
vst20t.32 {q0, q1}, [r0]
vst20e.32 {q0, q1}, [r0]
vpste
vst21t.32 {q0, q1}, [r0]
vst21e.32 {q0, q1}, [r0]
vpste
vst40t.32 {q0, q1, q2, q3}, [r0]
vst40e.32 {q0, q1, q2, q3}, [r0]
vpste
vst41t.32 {q0, q1, q2, q3}, [r0]
vst41e.32 {q0, q1, q2, q3}, [r0]
vpste
vst42t.32 {q0, q1, q2, q3}, [r0]
vst42e.32 {q0, q1, q2, q3}, [r0]
vpste
vst43t.32 {q0, q1, q2, q3}, [r0]
vst43e.32 {q0, q1, q2, q3}, [r0]
vpst
vst20.32 {q0, q1}, [r0]
vpst
vst21.32 {q0, q1}, [r0]
vpst
vst40.32 {q0, q1, q2, q3}, [r0]
vpst
vst41.32 {q0, q1, q2, q3}, [r0]
vpst
vst42.32 {q0, q1, q2, q3}, [r0]
vpst
vst43.32 {q0, q1, q2, q3}, [r0]
cond2 vld20
cond2 vld21
cond4 vld40
cond4 vld41
cond4 vld42
cond4 vld43
vpste
vld20t.32 {q0, q1}, [r0]
vld20e.32 {q0, q1}, [r0]
vpste
vld21t.32 {q0, q1}, [r0]
vld21e.32 {q0, q1}, [r0]
vpste
vld40t.32 {q0, q1, q2, q3}, [r0]
vld40e.32 {q0, q1, q2, q3}, [r0]
vpste
vld41t.32 {q0, q1, q2, q3}, [r0]
vld41e.32 {q0, q1, q2, q3}, [r0]
vpste
vld42t.32 {q0, q1, q2, q3}, [r0]
vld42e.32 {q0, q1, q2, q3}, [r0]
vpste
vld43t.32 {q0, q1, q2, q3}, [r0]
vld43e.32 {q0, q1, q2, q3}, [r0]
vpst
vld20.32 {q0, q1}, [r0]
vpst
vld21.32 {q0, q1}, [r0]
vpst
vld40.32 {q0, q1, q2, q3}, [r0]
vpst
vld41.32 {q0, q1, q2, q3}, [r0]
vpst
vld42.32 {q0, q1, q2, q3}, [r0]
vpst
vld43.32 {q0, q1, q2, q3}, [r0]
|
stsp/binutils-ia16
| 1,985
|
gas/testsuite/gas/arm/cde-mve-or-neon.s
|
.syntax unified
vcx1 p0, s0, #0
vcx1 p0, s0, #1920
vcx1 p0, s0, #64
vcx1 p0, s0, #63
vcx1 p7, s0, #0
vcx1 p0, s1, #0
vcx1 p0, s30, #0
vcx1 p0, d0, #0
vcx1 p0, d0, #1920
vcx1 p0, d0, #64
vcx1 p0, d0, #63
vcx1 p7, d0, #0
vcx1 p0, d15, #0
vcx1a p0, s0, #0
vcx1a p0, s0, #1920
vcx1a p0, s0, #64
vcx1a p0, s0, #63
vcx1a p7, s0, #0
vcx1a p0, s1, #0
vcx1a p0, s30, #0
vcx1a p0, d0, #0
vcx1a p0, d0, #1920
vcx1a p0, d0, #64
vcx1a p0, d0, #63
vcx1a p7, d0, #0
vcx1a p0, d15, #0
vcx2 p0, s0, s0, #0
vcx2 p0, s0, s0, #60
vcx2 p0, s0, s0, #2
vcx2 p0, s0, s0, #1
vcx2 p7, s0, s0, #0
vcx2 p0, s1, s0, #0
vcx2 p0, s30, s0, #0
vcx2 p0, s0, s1, #0
vcx2 p0, s0, s30, #0
vcx2 p0, d0, d0, #0
vcx2 p0, d0, d0, #60
vcx2 p0, d0, d0, #2
vcx2 p0, d0, d0, #1
vcx2 p7, d0, d0, #0
vcx2 p0, d15, d0, #0
vcx2 p0, d0, d15, #0
vcx2a p0, s0, s0, #0
vcx2a p0, s0, s0, #60
vcx2a p0, s0, s0, #2
vcx2a p0, s0, s0, #1
vcx2a p7, s0, s0, #0
vcx2a p0, s1, s0, #0
vcx2a p0, s30, s0, #0
vcx2a p0, s0, s1, #0
vcx2a p0, s0, s30, #0
vcx2a p0, d0, d0, #0
vcx2a p0, d0, d0, #60
vcx2a p0, d0, d0, #2
vcx2a p0, d0, d0, #1
vcx2a p7, d0, d0, #0
vcx2a p0, d15, d0, #0
vcx2a p0, d0, d15, #0
vcx3 p0, s0, s0, s0, #0
vcx3 p0, s0, s0, s0, #6
vcx3 p0, s0, s0, s0, #1
vcx3 p7, s0, s0, s0, #0
vcx3 p0, s1, s0, s0, #0
vcx3 p0, s30, s0, s0, #0
vcx3 p0, s0, s1, s0, #0
vcx3 p0, s0, s30, s0, #0
vcx3 p0, s0, s0, s1, #0
vcx3 p0, s0, s0, s30, #0
vcx3 p0, d0, d0, d0, #0
vcx3 p0, d0, d0, d0, #6
vcx3 p0, d0, d0, d0, #1
vcx3 p7, d0, d0, d0, #0
vcx3 p0, d15, d0, d0, #0
vcx3 p0, d0, d15, d0, #0
vcx3 p0, d0, d0, d15, #0
vcx3a p0, s0, s0, s0, #0
vcx3a p0, s0, s0, s0, #6
vcx3a p0, s0, s0, s0, #1
vcx3a p7, s0, s0, s0, #0
vcx3a p0, s1, s0, s0, #0
vcx3a p0, s30, s0, s0, #0
vcx3a p0, s0, s1, s0, #0
vcx3a p0, s0, s30, s0, #0
vcx3a p0, s0, s0, s1, #0
vcx3a p0, s0, s0, s30, #0
vcx3a p0, d0, d0, d0, #0
vcx3a p0, d0, d0, d0, #6
vcx3a p0, d0, d0, d0, #1
vcx3a p7, d0, d0, d0, #0
vcx3a p0, d15, d0, d0, #0
vcx3a p0, d0, d15, d0, #0
vcx3a p0, d0, d0, d15, #0
|
stsp/binutils-ia16
| 2,675
|
gas/testsuite/gas/arm/fpa-monadic.s
|
.text
.globl F
F:
mvfs f0, f0
mvfsp f0, f0
mvfsm f0, f0
mvfsz f0, f0
mvfd f0, f0
mvfdp f0, f0
mvfdm f0, f0
mvfdz f0, f0
mvfe f0, f0
mvfep f0, f0
mvfem f0, f0
mvfez f0, f0
mnfs f0, f0
mnfsp f0, f0
mnfsm f0, f0
mnfsz f0, f0
mnfd f0, f0
mnfdp f0, f0
mnfdm f0, f0
mnfdz f0, f0
mnfe f0, f0
mnfep f0, f0
mnfem f0, f0
mnfez f0, f0
abss f0, f0
abssp f0, f0
abssm f0, f0
abssz f0, f0
absd f0, f0
absdp f0, f0
absdm f0, f0
absdz f0, f0
abse f0, f0
absep f0, f0
absem f0, f0
absez f0, f0
rnds f0, f0
rndsp f0, f0
rndsm f0, f0
rndsz f0, f0
rndd f0, f0
rnddp f0, f0
rnddm f0, f0
rnddz f0, f0
rnde f0, f0
rndep f0, f0
rndem f0, f0
rndez f0, f0
sqts f0, f0
sqtsp f0, f0
sqtsm f0, f0
sqtsz f0, f0
sqtd f0, f0
sqtdp f0, f0
sqtdm f0, f0
sqtdz f0, f0
sqte f0, f0
sqtep f0, f0
sqtem f0, f0
sqtez f0, f0
logs f0, f0
logsp f0, f0
logsm f0, f0
logsz f0, f0
logd f0, f0
logdp f0, f0
logdm f0, f0
logdz f0, f0
loge f0, f0
logep f0, f0
logem f0, f0
logez f0, f0
lgns f0, f0
lgnsp f0, f0
lgnsm f0, f0
lgnsz f0, f0
lgnd f0, f0
lgndp f0, f0
lgndm f0, f0
lgndz f0, f0
lgne f0, f0
lgnep f0, f0
lgnem f0, f0
lgnez f0, f0
exps f0, f0
expsp f0, f0
expsm f0, f0
expsz f0, f0
expd f0, f0
expdp f0, f0
expdm f0, f0
expdz f0, f0
expe f0, f0
expep f0, f0
expem f0, f0
expdz f0, f0
sins f0, f0
sinsp f0, f0
sinsm f0, f0
sinsz f0, f0
sind f0, f0
sindp f0, f0
sindm f0, f0
sindz f0, f0
sine f0, f0
sinep f0, f0
sinem f0, f0
sinez f0, f0
coss f0, f0
cossp f0, f0
cossm f0, f0
cossz f0, f0
cosd f0, f0
cosdp f0, f0
cosdm f0, f0
cosdz f0, f0
cose f0, f0
cosep f0, f0
cosem f0, f0
cosez f0, f0
tans f0, f0
tansp f0, f0
tansm f0, f0
tansz f0, f0
tand f0, f0
tandp f0, f0
tandm f0, f0
tandz f0, f0
tane f0, f0
tanep f0, f0
tanem f0, f0
tanez f0, f0
asns f0, f0
asnsp f0, f0
asnsm f0, f0
asnsz f0, f0
asnd f0, f0
asndp f0, f0
asndm f0, f0
asndz f0, f0
asne f0, f0
asnep f0, f0
asnem f0, f0
asnez f0, f0
acss f0, f0
acssp f0, f0
acssm f0, f0
acssz f0, f0
acsd f0, f0
acsdp f0, f0
acsdm f0, f0
acsdz f0, f0
acse f0, f0
acsep f0, f0
acsem f0, f0
acsez f0, f0
atns f0, f0
atnsp f0, f0
atnsm f0, f0
atnsz f0, f0
atnd f0, f0
atndp f0, f0
atndm f0, f0
atndz f0, f0
atne f0, f0
atnep f0, f0
atnem f0, f0
atnez f0, f0
urds f0, f0
urdsp f0, f0
urdsm f0, f0
urdsz f0, f0
urdd f0, f0
urddp f0, f0
urddm f0, f0
urddz f0, f0
urde f0, f0
urdep f0, f0
urdem f0, f0
urdez f0, f0
nrms f0, f0
nrmsp f0, f0
nrmsm f0, f0
nrmsz f0, f0
nrmd f0, f0
nrmdp f0, f0
nrmdm f0, f0
nrmdz f0, f0
nrme f0, f0
nrmep f0, f0
nrmem f0, f0
nrmez f0, f0
|
stsp/binutils-ia16
| 1,138
|
gas/testsuite/gas/arm/mve-vhadd-vhsub-vrhadd-bad.s
|
.macro cond, op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s8 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vhadd.i8 q0, q1, q2
vhadd.s64 q0, q1, q2
vhadd.i8 q0, q1, r2
vhadd.s64 q0, q1, r2
vhsub.i16 q0, q1, q2
vhsub.u64 q0, q1, q2
vhsub.i16 q0, q1, r2
vhsub.u64 q0, q1, r2
vrhadd.i32 q0, q1, q2
vrhadd.s64 q0, q1, q2
vhadd.s8 q0, q1, sp
vhadd.s8 q0, q1, pc
vhsub.s8 q0, q1, sp
vhsub.s8 q0, q1, pc
vrhadd.s8 q0, q1, r2
cond vhadd, r2
cond vhadd, q2
cond vhsub, r2
cond vhsub, q2
cond vrhadd, q2
it eq
vhaddeq.s8 q0, q1, r2
vhaddeq.s8 q0, q1, r2
vpst
vhaddeq.s8 q0, q1, r2
vhaddt.s8 q0, q1, r2
vpst
vhadd.s8 q0, q1, r2
it eq
vhaddeq.s8 q0, q1, q2
vhaddeq.s8 q0, q1, q2
vpst
vhaddeq.s8 q0, q1, q2
vhaddt.s8 q0, q1, q2
vpst
vhadd.s8 q0, q1, q2
it eq
vhsubeq.s8 q0, q1, r2
vhsubeq.s8 q0, q1, r2
vpst
vhsubeq.s8 q0, q1, r2
vhsubt.s8 q0, q1, r2
vpst
vhsub.s8 q0, q1, r2
it eq
vhsubeq.s8 q0, q1, q2
vhsubeq.s8 q0, q1, q2
vpst
vhsubeq.s8 q0, q1, q2
vhsubt.s8 q0, q1, q2
vpst
vhsub.s8 q0, q1, q2
it eq
vrhaddeq.s8 q0, q1, q2
vrhaddeq.s8 q0, q1, q2
vpst
vrhaddeq.s8 q0, q1, q2
vrhaddt.s8 q0, q1, q2
vpst
vrhadd.s8 q0, q1, q2
|
stsp/binutils-ia16
| 1,101
|
gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s
|
@ Tests that are supposed to fail during parsing of LDRS group relocations.
.text
@ No NC variants exist for the LDRS relocations.
ldrd r0, [r0, #:pc_g0_nc:(f)]
ldrd r0, [r0, #:pc_g1_nc:(f)]
ldrd r0, [r0, #:sb_g0_nc:(f)]
ldrd r0, [r0, #:sb_g1_nc:(f)]
strd r0, [r0, #:pc_g0_nc:(f)]
strd r0, [r0, #:pc_g1_nc:(f)]
strd r0, [r0, #:sb_g0_nc:(f)]
strd r0, [r0, #:sb_g1_nc:(f)]
ldrh r0, [r0, #:pc_g0_nc:(f)]
ldrh r0, [r0, #:pc_g1_nc:(f)]
ldrh r0, [r0, #:sb_g0_nc:(f)]
ldrh r0, [r0, #:sb_g1_nc:(f)]
strh r0, [r0, #:pc_g0_nc:(f)]
strh r0, [r0, #:pc_g1_nc:(f)]
strh r0, [r0, #:sb_g0_nc:(f)]
strh r0, [r0, #:sb_g1_nc:(f)]
ldrsh r0, [r0, #:pc_g0_nc:(f)]
ldrsh r0, [r0, #:pc_g1_nc:(f)]
ldrsh r0, [r0, #:sb_g0_nc:(f)]
ldrsh r0, [r0, #:sb_g1_nc:(f)]
ldrsb r0, [r0, #:pc_g0_nc:(f)]
ldrsb r0, [r0, #:pc_g1_nc:(f)]
ldrsb r0, [r0, #:sb_g0_nc:(f)]
ldrsb r0, [r0, #:sb_g1_nc:(f)]
@ Instructions with a gibberish relocation code.
ldrd r0, [r0, #:foo:(f)]
strd r0, [r0, #:foo:(f)]
ldrh r0, [r0, #:foo:(f)]
strh r0, [r0, #:foo:(f)]
ldrsh r0, [r0, #:foo:(f)]
ldrsb r0, [r0, #:foo:(f)]
|
stsp/binutils-ia16
| 1,606
|
gas/testsuite/gas/arm/mve-vcvt-bad.s
|
.macro cond1
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcvt\().f16.s16 q0, q1, #1
.endr
.endm
.syntax unified
.thumb
vcvt.f16.s16 q0, q1, #0
vcvt.f16.s16 q0, q1, #17
vcvt.f16.u16 q0, q1, #0
vcvt.f16.u16 q0, q1, #17
vcvt.s16.f16 q0, q1, #0
vcvt.s16.f16 q0, q1, #17
vcvt.u16.f16 q0, q1, #0
vcvt.u16.f16 q0, q1, #17
vcvt.f32.s32 q0, q1, #0
vcvt.f32.s32 q0, q1, #33
vcvt.f32.u32 q0, q1, #0
vcvt.f32.u32 q0, q1, #33
vcvt.s32.f32 q0, q1, #0
vcvt.s32.f32 q0, q1, #33
vcvt.u32.f32 q0, q1, #0
vcvt.u32.f32 q0, q1, #33
vcvt.f64.s64 q0, q1, #1
vcvt.f64.u64 q0, q1, #1
vcvt.s64.f64 q0, q1, #1
vcvt.u64.f64 q0, q1, #1
cond1
it eq
vcvteq.f16.s16 q0, q1, #1
vcvteq.f16.s16 q0, q1, #1
vpst
vcvteq.f16.s16 q0, q1, #1
vcvtt.f16.s16 q0, q1, #1
vpst
vcvt.f16.s16 q0, q1, #1
.macro cond2
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vcvt\().f16.s16 q0, q1
.endr
.endm
cond2
vcvt.f64.s64 q0, q1
vcvt.f64.u64 q0, q1
vcvt.s64.f64 q0, q1
vcvt.u64.f64 q0, q1
it eq
vcvteq.u32.f32 q0, q1
vcvteq.u32.f32 q0, q1
vpst
vcvteq.u32.f32 q0, q1
vcvtt.u32.f32 q0, q1
vpst
vcvt.u32.f32 q0, q1
.macro cond3 mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().f16.f32 q0, q1
.endr
.endm
cond3 vcvtb
vcvtb.f16.f64 q0, q1
vcvtb.f64.f16 q0, q1
vcvtb.f32.f64 q0, q1
vcvtb.f64.f32 q0, q1
it eq
vcvtbeq.f16.f32 q0, q1
vcvtbeq.f16.f32 q0, q1
vpst
vcvtbeq.f16.f32 q0, q1
vcvtbt.f16.f32 q0, q1
vpst
vcvtb.f16.f32 q0, q1
cond3 vcvtt
vcvtt.f16.f64 q0, q1
vcvtt.f64.f16 q0, q1
vcvtt.f32.f64 q0, q1
vcvtt.f64.f32 q0, q1
it eq
vcvtteq.f16.f32 q0, q1
vcvtteq.f16.f32 q0, q1
vpst
vcvtteq.f16.f32 q0, q1
vcvttt.f16.f32 q0, q1
vpst
vcvtt.f16.f32 q0, q1
|
stsp/binutils-ia16
| 3,574
|
gas/testsuite/gas/arm/group-reloc-ldc.s
|
@ LDC group relocation tests.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store
\load 0, c0, [r0, #:pc_g0:(f + 0x214)]
\load 0, c0, [r0, #:pc_g1:(f + 0x214)]
\load 0, c0, [r0, #:pc_g2:(f + 0x214)]
\load 0, c0, [r0, #:sb_g0:(f + 0x214)]
\load 0, c0, [r0, #:sb_g1:(f + 0x214)]
\load 0, c0, [r0, #:sb_g2:(f + 0x214)]
\store 0, c0, [r0, #:pc_g0:(f + 0x214)]
\store 0, c0, [r0, #:pc_g1:(f + 0x214)]
\store 0, c0, [r0, #:pc_g2:(f + 0x214)]
\store 0, c0, [r0, #:sb_g0:(f + 0x214)]
\store 0, c0, [r0, #:sb_g1:(f + 0x214)]
\store 0, c0, [r0, #:sb_g2:(f + 0x214)]
\load 0, c0, [r0, #:pc_g0:(f - 0x214)]
\load 0, c0, [r0, #:pc_g1:(f - 0x214)]
\load 0, c0, [r0, #:pc_g2:(f - 0x214)]
\load 0, c0, [r0, #:sb_g0:(f - 0x214)]
\load 0, c0, [r0, #:sb_g1:(f - 0x214)]
\load 0, c0, [r0, #:sb_g2:(f - 0x214)]
\store 0, c0, [r0, #:pc_g0:(f - 0x214)]
\store 0, c0, [r0, #:pc_g1:(f - 0x214)]
\store 0, c0, [r0, #:pc_g2:(f - 0x214)]
\store 0, c0, [r0, #:sb_g0:(f - 0x214)]
\store 0, c0, [r0, #:sb_g1:(f - 0x214)]
\store 0, c0, [r0, #:sb_g2:(f - 0x214)]
.endm
ldctest ldc stc
ldctest ldcl stcl
ldctest ldc2 stc2
ldctest ldc2l stc2l
@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
.fpu fpa
.macro fpa_test load store
\load f0, [r0, #:pc_g0:(f + 0x214)]
\load f0, [r0, #:pc_g1:(f + 0x214)]
\load f0, [r0, #:pc_g2:(f + 0x214)]
\load f0, [r0, #:sb_g0:(f + 0x214)]
\load f0, [r0, #:sb_g1:(f + 0x214)]
\load f0, [r0, #:sb_g2:(f + 0x214)]
\store f0, [r0, #:pc_g0:(f + 0x214)]
\store f0, [r0, #:pc_g1:(f + 0x214)]
\store f0, [r0, #:pc_g2:(f + 0x214)]
\store f0, [r0, #:sb_g0:(f + 0x214)]
\store f0, [r0, #:sb_g1:(f + 0x214)]
\store f0, [r0, #:sb_g2:(f + 0x214)]
\load f0, [r0, #:pc_g0:(f - 0x214)]
\load f0, [r0, #:pc_g1:(f - 0x214)]
\load f0, [r0, #:pc_g2:(f - 0x214)]
\load f0, [r0, #:sb_g0:(f - 0x214)]
\load f0, [r0, #:sb_g1:(f - 0x214)]
\load f0, [r0, #:sb_g2:(f - 0x214)]
\store f0, [r0, #:pc_g0:(f - 0x214)]
\store f0, [r0, #:pc_g1:(f - 0x214)]
\store f0, [r0, #:pc_g2:(f - 0x214)]
\store f0, [r0, #:sb_g0:(f - 0x214)]
\store f0, [r0, #:sb_g1:(f - 0x214)]
\store f0, [r0, #:sb_g2:(f - 0x214)]
.endm
fpa_test ldfs stfs
fpa_test ldfd stfd
fpa_test ldfe stfe
fpa_test ldfp stfp
@ FLDS/FSTS
.fpu vfp
.macro vfp_test load store reg
\load \reg, [r0, #:pc_g0:(f + 0x214)]
\load \reg, [r0, #:pc_g1:(f + 0x214)]
\load \reg, [r0, #:pc_g2:(f + 0x214)]
\load \reg, [r0, #:sb_g0:(f + 0x214)]
\load \reg, [r0, #:sb_g1:(f + 0x214)]
\load \reg, [r0, #:sb_g2:(f + 0x214)]
\store \reg, [r0, #:pc_g0:(f + 0x214)]
\store \reg, [r0, #:pc_g1:(f + 0x214)]
\store \reg, [r0, #:pc_g2:(f + 0x214)]
\store \reg, [r0, #:sb_g0:(f + 0x214)]
\store \reg, [r0, #:sb_g1:(f + 0x214)]
\store \reg, [r0, #:sb_g2:(f + 0x214)]
\load \reg, [r0, #:pc_g0:(f - 0x214)]
\load \reg, [r0, #:pc_g1:(f - 0x214)]
\load \reg, [r0, #:pc_g2:(f - 0x214)]
\load \reg, [r0, #:sb_g0:(f - 0x214)]
\load \reg, [r0, #:sb_g1:(f - 0x214)]
\load \reg, [r0, #:sb_g2:(f - 0x214)]
\store \reg, [r0, #:pc_g0:(f - 0x214)]
\store \reg, [r0, #:pc_g1:(f - 0x214)]
\store \reg, [r0, #:pc_g2:(f - 0x214)]
\store \reg, [r0, #:sb_g0:(f - 0x214)]
\store \reg, [r0, #:sb_g1:(f - 0x214)]
\store \reg, [r0, #:sb_g2:(f - 0x214)]
.endm
vfp_test flds fsts s0
@ FLDD/FSTD
vfp_test fldd fstd d0
@ VLDR/VSTR
vfp_test vldr vstr d0
@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
.cpu ep9312
vfp_test cfldrs cfstrs mvf0
vfp_test cfldrd cfstrd mvd0
vfp_test cfldr32 cfstr32 mvfx0
vfp_test cfldr64 cfstr64 mvdx0
|
stsp/binutils-ia16
| 1,435
|
gas/testsuite/gas/arm/mve-vrmlaldavh.s
|
.syntax unified
.thumb
.irp op1, r0, r2, r4, r8, r10, r12, r14
.irp op2, r1, r3, r5, r7, r9, r11
.irp op3, q0, q1, q2, q4, q7
.irp op4, q0, q1, q2, q4, q7
.irp data, s32, u32
vrmlaldavh.\data \op1, \op2, \op3, \op4
vrmlaldavha.\data \op1, \op2, \op3, \op4
vrmlalvh.\data \op1, \op2, \op3, \op4
vrmlalvha.\data \op1, \op2, \op3, \op4
.endr
vrmlaldavhx.s32 \op1, \op2, \op3, \op4
vrmlaldavhax.s32 \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
.irp op1, r0, r2, r4, r8, r10, r12, r14
.irp op2, r1, r3, r5, r7, r9, r11
.irp op3, q0, q1, q2, q4, q7
.irp op4, q0, q1, q2, q4, q7
vrmlsldavh.s32 \op1, \op2, \op3, \op4
vrmlsldavha.s32 \op1, \op2, \op3, \op4
vrmlsldavhx.s32 \op1, \op2, \op3, \op4
vrmlsldavhax.s32 \op1, \op2, \op3, \op4
.endr
.endr
.endr
.endr
vpstete
vrmlaldavht.s32 r0, r1, q2, q3
vrmlaldavhe.u32 lr, r11, q7, q7
vrmlaldavhat.s32 lr, r11, q7, q7
vrmlaldavhae.u32 r0, r1, q2, q3
vpstete
vrmlaldavhxt.s32 r0, r1, q2, q3
vrmlaldavhxe.s32 r4, r7, q0, q5
vrmlaldavhaxt.s32 r0, r1, q2, q3
vrmlaldavhaxe.s32 lr, r11, q7, q7
vpstete
vrmlalvht.s32 r0, r1, q2, q3
vrmlalvhe.s32 lr, r11, q7, q7
vrmlalvhat.s32 r0, r1, q2, q3
vrmlalvhae.s32 lr, r11, q7, q7
vpstete
vrmlsldavht.s32 r0, r1, q2, q3
vrmlsldavhe.s32 lr, r11, q7, q7
vrmlsldavhat.s32 r0, r1, q2, q3
vrmlsldavhae.s32 lr, r11, q7, q7
vpstete
vrmlsldavhxt.s32 r0, r1, q2, q3
vrmlsldavhxe.s32 lr, r11, q7, q7
vrmlsldavhaxt.s32 r0, r1, q2, q3
vrmlsldavhaxe.s32 lr, r11, q7, q7
|
stsp/binutils-ia16
| 1,179
|
gas/testsuite/gas/arm/cde-mve.s
|
.syntax unified
vcx1 p0, q0, #0
vcx1 p0, q0, #2048
vcx1 p0, q0, #1920
vcx1 p0, q0, #64
vcx1 p0, q0, #63
vcx1 p7, q0, #0
vcx1 p0, q7, #0
vcx1a p0, q0, #0
vcx1a p0, q0, #2048
vcx1a p0, q0, #1920
vcx1a p0, q0, #64
vcx1a p0, q0, #63
vcx1a p7, q0, #0
vcx1a p0, q7, #0
vptt.i8 eq, q0, q0
vcx1t p0, q0, #0
vcx1at p0, q0, #0
vcx2 p0, q0, q0, #0
vcx2 p0, q0, q0, #64
vcx2 p0, q0, q0, #60
vcx2 p0, q0, q0, #2
vcx2 p0, q0, q0, #1
vcx2 p7, q0, q0, #0
vcx2 p0, q7, q0, #0
vcx2 p0, q0, q7, #0
vcx2a p0, q0, q0, #0
vcx2a p0, q0, q0, #64
vcx2a p0, q0, q0, #60
vcx2a p0, q0, q0, #2
vcx2a p0, q0, q0, #1
vcx2a p7, q0, q0, #0
vcx2a p0, q7, q0, #0
vcx2a p0, q0, q7, #0
vptt.i8 eq, q0, q0
vcx2t p0, q0, q0, #0
vcx2at p0, q0, q0, #0
vcx3 p0, q0, q0, q0, #0
vcx3 p0, q0, q0, q0, #8
vcx3 p0, q0, q0, q0, #6
vcx3 p0, q0, q0, q0, #1
vcx3 p7, q0, q0, q0, #0
vcx3 p0, q7, q0, q0, #0
vcx3 p0, q0, q7, q0, #0
vcx3 p0, q0, q0, q7, #0
vcx3a p0, q0, q0, q0, #0
vcx3a p0, q0, q0, q0, #8
vcx3a p0, q0, q0, q0, #6
vcx3a p0, q0, q0, q0, #1
vcx3a p7, q0, q0, q0, #0
vcx3a p0, q7, q0, q0, #0
vcx3a p0, q0, q7, q0, #0
vcx3a p0, q0, q0, q7, #0
vptt.i8 eq, q0, q0
vcx3t p0, q0, q0, q0, #0
vcx3at p0, q0, q0, q0, #0
|
stsp/binutils-ia16
| 6,271
|
gas/testsuite/gas/arm/vfp1xD.s
|
@ VFP Instructions for v1xD variants (Single precision only)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use s0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fmstat
fcmpes s0, s0
fcmpezs s0
fcmps s0, s0
fcmpzs s0
@ Monadic data operations
fabss s0, s0
fcpys s0, s0
fnegs s0, s0
fsqrts s0, s0
@ Dyadic data operations
fadds s0, s0, s0
fdivs s0, s0, s0
fmacs s0, s0, s0
fmscs s0, s0, s0
fmuls s0, s0, s0
fnmacs s0, s0, s0
fnmscs s0, s0, s0
fnmuls s0, s0, s0
fsubs s0, s0, s0
@ Load/store operations
flds s0, [r0]
fsts s0, [r0]
@ Load/store multiple operations
fldmias r0, {s0}
fldmfds r0, {s0}
fldmias r0!, {s0}
fldmfds r0!, {s0}
fldmdbs r0!, {s0}
fldmeas r0!, {s0}
fldmiax r0, {d0}
fldmfdx r0, {d0}
fldmiax r0!, {d0}
fldmfdx r0!, {d0}
fldmdbx r0!, {d0}
fldmeax r0!, {d0}
fstmias r0, {s0}
fstmeas r0, {s0}
fstmias r0!, {s0}
fstmeas r0!, {s0}
fstmdbs r0!, {s0}
fstmfds r0!, {s0}
fstmiax r0, {d0}
fstmeax r0, {d0}
fstmiax r0!, {d0}
fstmeax r0!, {d0}
fstmdbx r0!, {d0}
fstmfdx r0!, {d0}
@ Conversion operations
fsitos s0, s0
fuitos s0, s0
ftosis s0, s0
ftosizs s0, s0
ftouis s0, s0
ftouizs s0, s0
@ ARM from VFP operations
fmrs r0, s0
fmrx r0, fpsid
fmrx r0, fpscr
fmrx r0, fpexc
@ VFP From ARM operations
fmsr s0, r0
fmxr fpsid, r0
fmxr fpscr, r0
fmxr fpexc, r0
@ Now we test that the register fields are updated correctly for
@ each class of instruction.
@ Single register operations (compare-zero):
fcmpzs s1
fcmpzs s2
fcmpzs s31
@ Two register comparison operations:
fcmps s0, s1
fcmps s0, s2
fcmps s0, s31
fcmps s1, s0
fcmps s2, s0
fcmps s31, s0
fcmps s21, s12
@ Two register data operations (monadic)
fnegs s0, s1
fnegs s0, s2
fnegs s0, s31
fnegs s1, s0
fnegs s2, s0
fnegs s31, s0
fnegs s12, s21
@ Three register data operations (dyadic)
fadds s0, s0, s1
fadds s0, s0, s2
fadds s0, s0, s31
fadds s0, s1, s0
fadds s0, s2, s0
fadds s0, s31, s0
fadds s1, s0, s0
fadds s2, s0, s0
fadds s31, s0, s0
fadds s12, s21, s5
@ Conversion operations
fsitos s0, s1
fsitos s0, s2
fsitos s0, s31
fsitos s1, s0
fsitos s2, s0
fsitos s31, s0
ftosis s0, s1
ftosis s0, s2
ftosis s0, s31
ftosis s1, s0
ftosis s2, s0
ftosis s31, s0
@ Move to VFP from ARM
fmsr s0, r1
fmsr s0, r7
fmsr s0, r14
fmsr s1, r0
fmsr s2, r0
fmsr s31, r0
fmsr s21, r7
fmxr fpsid, r1
fmxr fpsid, r14
@ Move to ARM from VFP
fmrs r0, s1
fmrs r0, s2
fmrs r0, s31
fmrs r1, s0
fmrs r7, s0
fmrs r14, s0
fmrs r9, s11
fmrx r1, fpsid
fmrx r14, fpsid
@ Load/store operations
flds s0, [r1]
flds s0, [r14]
flds s0, [r0, #0]
flds s0, [r0, #1020]
flds s0, [r0, #-1020]
flds s1, [r0]
flds s2, [r0]
flds s31, [r0]
fsts s21, [r12, #804]
@ Load/store multiple operations
fldmias r0, {s1}
fldmias r0, {s2}
fldmias r0, {s31}
fldmias r0, {s0-s1}
fldmias r0, {s0-s2}
fldmias r0, {s0-s31}
fldmias r0, {s1-s31}
fldmias r0, {s2-s31}
fldmias r0, {s30-s31}
fldmias r1, {s0}
fldmias r14, {s0}
fstmiax r0, {d1}
fstmiax r0, {d2}
fstmiax r0, {d15}
fstmiax r0, {d0-d1}
fstmiax r0, {d0-d2}
fstmiax r0, {d0-d15}
fstmiax r0, {d1-d15}
fstmiax r0, {d2-d15}
fstmiax r0, {d14-d15}
fstmiax r1, {d0}
fstmiax r14, {d0}
@ Check that we assemble all the register names correctly
fcmpzs s0
fcmpzs s1
fcmpzs s2
fcmpzs s3
fcmpzs s4
fcmpzs s5
fcmpzs s6
fcmpzs s7
fcmpzs s8
fcmpzs s9
fcmpzs s10
fcmpzs s11
fcmpzs s12
fcmpzs s13
fcmpzs s14
fcmpzs s15
fcmpzs s16
fcmpzs s17
fcmpzs s18
fcmpzs s19
fcmpzs s20
fcmpzs s21
fcmpzs s22
fcmpzs s23
fcmpzs s24
fcmpzs s25
fcmpzs s26
fcmpzs s27
fcmpzs s28
fcmpzs s29
fcmpzs s30
fcmpzs s31
@ Now we check the placement of the conditional execution substring.
@ On VFP this is always at the end of the instruction.
@ We use different register numbers here to check for correct
@ disassembly
@ Comparison operations
fmstateq
fcmpeseq s3, s7
fcmpezseq s5
fcmpseq s1, s2
fcmpzseq s1
@ Monadic data operations
fabsseq s1, s3
fcpyseq s31, s19
fnegseq s20, s8
fsqrtseq s5, s7
@ Dyadic data operations
faddseq s6, s5, s4
fdivseq s3, s2, s1
fmacseq s31, s30, s29
fmscseq s28, s27, s26
fmulseq s25, s24, s23
fnmacseq s22, s21, s20
fnmscseq s19, s18, s17
fnmulseq s16, s15, s14
fsubseq s13, s12, s11
@ Load/store operations
fldseq s10, [r8]
fstseq s9, [r7]
@ Load/store multiple operations
fldmiaseq r1, {s8}
fldmfdseq r2, {s7}
fldmiaseq r3!, {s6}
fldmfdseq r4!, {s5}
fldmdbseq r5!, {s4}
fldmeaseq r6!, {s3}
fldmiaxeq r7, {d1}
fldmfdxeq r8, {d2}
fldmiaxeq r9!, {d3}
fldmfdxeq r10!, {d4}
fldmdbxeq r11!, {d5}
fldmeaxeq r12!, {d6}
fstmiaseq r13, {s2}
fstmeaseq r14, {s1}
fstmiaseq r1!, {s31}
fstmeaseq r2!, {s30}
fstmdbseq r3!, {s29}
fstmfdseq r4!, {s28}
fstmiaxeq r5, {d7}
fstmeaxeq r6, {d8}
fstmiaxeq r7!, {d9}
fstmeaxeq r8!, {d10}
fstmdbxeq r9!, {d11}
fstmfdxeq r10!, {d12}
@ Conversion operations
fsitoseq s27, s6
ftosiseq s25, s5
ftosizseq s23, s4
ftouiseq s21, s3
ftouizseq s19, s2
fuitoseq s17, s1
@ ARM from VFP operations
fmrseq r11, s3
fmrxeq r9, fpsid
@ VFP From ARM operations
fmsreq s3, r9
fmxreq fpsid, r8
@ Implementation specific system registers
fmrx r0, fpinst
fmrx r0, fpinst2
fmrx r0, mvfr0
fmrx r0, mvfr1
fmrx r0, c12
fmxr fpinst, r0
fmxr fpinst2, r0
fmxr mvfr0, r0
fmxr mvfr1, r0
fmxr c12, r0
@ ARM VMSR/VMRS instructions
vmrs r0, FPSCR
vmrs r1, FPSCR
vmrs r2, FPSCR
vmrs r3, FPSCR
vmrs r4, FPSCR
vmrs r5, FPSCR
vmrs r6, FPSCR
vmrs r7, FPSCR
vmrs r8, FPSCR
vmrs r9, FPSCR
vmrs r10, FPSCR
vmrs r11, FPSCR
vmrs r12, FPSCR
vmrs r14, FPSCR
vmrs APSR_nzcv, FPSCR
vmsr FPSCR, r0
vmsr FPSCR, r1
vmsr FPSCR, r2
vmsr FPSCR, r3
vmsr FPSCR, r4
vmsr FPSCR, r5
vmsr FPSCR, r6
vmsr FPSCR, r7
vmsr FPSCR, r8
vmsr FPSCR, r9
vmsr FPSCR, r10
vmsr FPSCR, r11
vmsr FPSCR, r12
vmsr FPSCR, r14
@ Priviledged extensions to VMSR/VMRS instructions
vmsr FPSID, r1
vmsr FPEXC, r2
vmsr FPINST, r3
vmsr FPINST2, r4
vmsr C15, r5
vmrs r3, FPSID
vmrs r4, MVFR1
vmrs r5, MVFR0
vmrs r6, FPEXC
vmrs r7, FPINST
vmrs r8, FPINST2
vmrs r9, C15
nop
nop
nop
|
stsp/binutils-ia16
| 4,433
|
gas/testsuite/gas/arm/vfp1.s
|
@ VFP Instructions for D variants (Double precision)
.text
.global F
F:
@ First we test the basic syntax and bit patterns of the opcodes.
@ Most of these tests deliberately use d0/r0 to avoid setting
@ any more bits than necessary.
@ Comparison operations
fcmped d0, d0
fcmpezd d0
fcmpd d0, d0
fcmpzd d0
@ Monadic data operations
fabsd d0, d0
fcpyd d0, d0
fnegd d0, d0
fsqrtd d0, d0
@ Dyadic data operations
faddd d0, d0, d0
fdivd d0, d0, d0
fmacd d0, d0, d0
fmscd d0, d0, d0
fmuld d0, d0, d0
fnmacd d0, d0, d0
fnmscd d0, d0, d0
fnmuld d0, d0, d0
fsubd d0, d0, d0
@ Load/store operations
fldd d0, [r0]
fstd d0, [r0]
@ Load/store multiple operations
fldmiad r0, {d0}
fldmfdd r0, {d0}
fldmiad r0!, {d0}
fldmfdd r0!, {d0}
fldmdbd r0!, {d0}
fldmead r0!, {d0}
fstmiad r0, {d0}
fstmead r0, {d0}
fstmiad r0!, {d0}
fstmead r0!, {d0}
fstmdbd r0!, {d0}
fstmfdd r0!, {d0}
@ Conversion operations
fsitod d0, s0
fuitod d0, s0
ftosid s0, d0
ftosizd s0, d0
ftouid s0, d0
ftouizd s0, d0
fcvtds d0, s0
fcvtsd s0, d0
@ ARM from VFP operations
fmrdh r0, d0
fmrdl r0, d0
@ VFP From ARM operations
fmdhr d0, r0
fmdlr d0, r0
@ Now we test that the register fields are updated correctly for
@ each class of instruction.
@ Single register operations (compare-zero):
fcmpzd d1
fcmpzd d2
fcmpzd d15
@ Two register comparison operations:
fcmpd d0, d1
fcmpd d0, d2
fcmpd d0, d15
fcmpd d1, d0
fcmpd d2, d0
fcmpd d15, d0
fcmpd d5, d12
@ Two register data operations (monadic)
fnegd d0, d1
fnegd d0, d2
fnegd d0, d15
fnegd d1, d0
fnegd d2, d0
fnegd d15, d0
fnegd d12, d5
@ Three register data operations (dyadic)
faddd d0, d0, d1
faddd d0, d0, d2
faddd d0, d0, d15
faddd d0, d1, d0
faddd d0, d2, d0
faddd d0, d15, d0
faddd d1, d0, d0
faddd d2, d0, d0
faddd d15, d0, d0
faddd d12, d9, d5
@ Conversion operations
fcvtds d0, s1
fcvtds d0, s2
fcvtds d0, s31
fcvtds d1, s0
fcvtds d2, s0
fcvtds d15, s0
fcvtsd s1, d0
fcvtsd s2, d0
fcvtsd s31, d0
fcvtsd s0, d1
fcvtsd s0, d2
fcvtsd s0, d15
@ Move to VFP from ARM
fmrdh r1, d0
fmrdh r14, d0
fmrdh r0, d1
fmrdh r0, d2
fmrdh r0, d15
fmrdl r1, d0
fmrdl r14, d0
fmrdl r0, d1
fmrdl r0, d2
fmrdl r0, d15
@ Move to ARM from VFP
fmdhr d0, r1
fmdhr d0, r14
fmdhr d1, r0
fmdhr d2, r0
fmdhr d15, r0
fmdlr d0, r1
fmdlr d0, r14
fmdlr d1, r0
fmdlr d2, r0
fmdlr d15, r0
@ Load/store operations
fldd d0, [r1]
fldd d0, [r14]
fldd d0, [r0, #0]
fldd d0, [r0, #1020]
fldd d0, [r0, #-1020]
fldd d1, [r0]
fldd d2, [r0]
fldd d15, [r0]
fstd d12, [r12, #804]
@ Load/store multiple operations
fldmiad r0, {d1}
fldmiad r0, {d2}
fldmiad r0, {d15}
fldmiad r0, {d0-d1}
fldmiad r0, {d0-d2}
fldmiad r0, {d0-d15}
fldmiad r0, {d1-d15}
fldmiad r0, {d2-d15}
fldmiad r0, {d14-d15}
fldmiad r1, {d0}
fldmiad r14, {d0}
@ Check that we assemble all the register names correctly
fcmpzd d0
fcmpzd d1
fcmpzd d2
fcmpzd d3
fcmpzd d4
fcmpzd d5
fcmpzd d6
fcmpzd d7
fcmpzd d8
fcmpzd d9
fcmpzd d10
fcmpzd d11
fcmpzd d12
fcmpzd d13
fcmpzd d14
fcmpzd d15
@ Now we check the placement of the conditional execution substring.
@ On VFP this is always at the end of the instruction.
@ Comparison operations
fcmpedeq d1, d15
fcmpezdeq d2
fcmpdeq d3, d14
fcmpzdeq d4
@ Monadic data operations
fabsdeq d5, d13
fcpydeq d6, d12
fnegdeq d7, d11
fsqrtdeq d8, d10
@ Dyadic data operations
fadddeq d9, d1, d15
fdivdeq d2, d3, d14
fmacdeq d4, d13, d12
fmscdeq d5, d6, d11
fmuldeq d7, d10, d9
fnmacdeq d8, d9, d10
fnmscdeq d7, d6, d11
fnmuldeq d5, d4, d12
fsubdeq d3, d13, d14
@ Load/store operations
flddeq d2, [r5]
fstdeq d1, [r12]
@ Load/store multiple operations
fldmiadeq r1, {d1}
fldmfddeq r2, {d2}
fldmiadeq r3!, {d3}
fldmfddeq r4!, {d4}
fldmdbdeq r5!, {d5}
fldmeadeq r6!, {d6}
fstmiadeq r7, {d15}
fstmeadeq r8, {d14}
fstmiadeq r9!, {d13}
fstmeadeq r10!, {d12}
fstmdbdeq r11!, {d11}
fstmfddeq r12!, {d10}
@ Conversion operations
fsitodeq d15, s1
fuitodeq d1, s31
ftosideq s1, d15
ftosizdeq s31, d2
ftouideq s15, d2
ftouizdeq s11, d3
fcvtdseq d1, s10
fcvtsdeq s11, d1
@ ARM from VFP operations
fmrdheq r8, d1
fmrdleq r7, d15
@ VFP From ARM operations
fmdhreq d1, r15
fmdlreq d15, r1
# Add three nop instructions to ensure that the
# output is 32-byte aligned as required for arm-aout.
nop
nop
nop
|
stsp/binutils-ia16
| 1,284
|
gas/testsuite/gas/arm/r15-bad.s
|
.text
.align 0
label:
mul r15, r1, r2
mul r1, r15, r2
mla r15, r2, r3, r4
mla r1, r15, r3, r4
mla r1, r2, r15, r4
mla r1, r2, r3, r15
smlabb r15, r2, r3, r4
smlabb r1, r15, r3, r4
smlabb r1, r2, r15, r4
smlabb r1, r2, r3, r15
smlalbb r15, r2, r3, r4
smlalbb r1, r15, r3, r4
smlalbb r1, r2, r15, r4
smlalbb r1, r2, r3, r15
smulbb r15, r2, r3
smulbb r1, r15, r3
smulbb r1, r2, r15
qadd r15, r2, r3
qadd r1, r15, r3
qadd r1, r2, r15
qadd16 r15, r2, r3
qadd16 r1, r15, r3
qadd16 r1, r2, r15
clz r15, r2
clz r1, r15
umaal r15, r2, r3, r4
umaal r1, r15, r3, r4
umaal r1, r2, r15, r4
umaal r1, r2, r3, r15
strex r15, r2, [r3]
strex r1, r15, [r3]
strex r1, r2, [r15]
ssat r15, #1, r2
ssat r1, #1, r15
ssat16 r15, #1, r2
ssat16 r1, #1, r15
smmul r15, r2, r3
smmul r1, r15, r3
smmul r1, r2, r15
smlald r15, r2, r3, r4
smlald r1, r15, r3, r4
smlald r1, r2, r15, r4
smlald r1, r2, r3, r15
smlad r15, r2, r3, r4
smlad r1, r15, r3, r4
smlad r1, r2, r15, r4
smlad r1, r2, r3, r15
sxth r15, r2
sxth r1, r15
sxtah r15, r2, r3
sxtah r1, r15, r3
sxtah r1, r2, r15
rfeda r15
rev r15, r2
rev r1, r15
pkhtb r15, r2, r3
pkhtb r1, r15, r3
pkhtb r1, r2, r15
ldrex r15, [r2]
ldrex r1, [r15]
swp r15, r2, [r3]
swp r1, r15, [r3]
swp r1, r2, [r15]
|
stsp/binutils-ia16
| 2,681
|
gas/testsuite/gas/arm/armv8-ar+fp.s
|
.syntax unified
.text
.arch_extension fp
.arm
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s31, s31
vmaxnm.f64 d0, d0, d0
vmaxnm.f64 d16, d16, d16
vmaxnm.f64 d15, d15, d15
vmaxnm.f64 d31, d31, d31
vminnm.f32 s0, s0, s0
vminnm.f32 s1, s1, s1
vminnm.f32 s30, s30, s30
vminnm.f32 s31, s31, s31
vminnm.f64 d0, d0, d0
vminnm.f64 d16, d16, d16
vminnm.f64 d15, d15, d15
vminnm.f64 d31, d31, d31
vcvta.s32.f32 s0, s0
vcvtn.s32.f32 s1, s1
vcvtp.u32.f32 s30, s30
vcvtm.u32.f32 s31, s31
vcvta.s32.f64 s0, d0
vcvtn.s32.f64 s1, d16
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d31
vrintz.f32 s0, s0
vrintx.f32 s1, s1
vrintreq.f32 s30, s30
vrinta.f32 s0, s0
vrintn.f32 s1, s1
vrintp.f32 s30, s30
vrintm.f32 s31, s31
vrintz.f64 d0, d0
vrintx.f64 d1, d1
vrintreq.f64 d30, d30
vrinta.f64 d0, d0
vrintn.f64 d1, d1
vrintp.f64 d30, d30
vrintm.f64 d31, d31
vcvtt.f16.f64 s0, d0
vcvtb.f16.f64 s1, d16
vcvtt.f16.f64 s30, d15
vcvtb.f16.f64 s31, d31
vcvtt.f64.f16 d0, s0
vcvtb.f64.f16 d16, s1
vcvtt.f64.f16 d15, s30
vcvtb.f64.f16 d31, s31
.thumb
vseleq.f32 s0, s0, s0
vselvs.f32 s1, s1, s1
vselge.f32 s30, s30, s30
vselgt.f32 s31, s31, s31
vseleq.f64 d0, d0, d0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
vmaxnm.f32 s0, s0, s0
vmaxnm.f32 s1, s1, s1
vmaxnm.f32 s30, s30, s30
vmaxnm.f32 s31, s31, s31
vmaxnm.f64 d0, d0, d0
vmaxnm.f64 d16, d16, d16
vmaxnm.f64 d15, d15, d15
vmaxnm.f64 d31, d31, d31
vminnm.f32 s0, s0, s0
vminnm.f32 s1, s1, s1
vminnm.f32 s30, s30, s30
vminnm.f32 s31, s31, s31
vminnm.f64 d0, d0, d0
vminnm.f64 d16, d16, d16
vminnm.f64 d15, d15, d15
vminnm.f64 d31, d31, d31
vcvta.s32.f32 s0, s0
vcvtn.s32.f32 s1, s1
vcvtp.u32.f32 s30, s30
vcvtm.u32.f32 s31, s31
vcvta.s32.f64 s0, d0
vcvtn.s32.f64 s1, d16
vcvtp.u32.f64 s30, d15
vcvtm.u32.f64 s31, d31
vrintz.f32 s0, s0
vrintx.f32 s1, s1
vrintr.f32 s30, s30
vrinta.f32 s0, s0
vrintn.f32 s1, s1
vrintp.f32 s30, s30
vrintm.f32 s31, s31
vrintz.f64 d0, d0
vrintx.f64 d1, d1
vrintr.f64 d30, d30
vrinta.f64 d0, d0
vrintn.f64 d1, d1
vrintp.f64 d30, d30
vrintm.f64 d31, d31
vcvtt.f16.f64 s0, d0
vcvtb.f16.f64 s1, d16
vcvtt.f16.f64 s30, d15
vcvtb.f16.f64 s31, d31
vcvtt.f64.f16 d0, s0
vcvtb.f64.f16 d16, s1
vcvtt.f64.f16 d15, s30
vcvtb.f64.f16 d31, s31
vmrs r9, MVFR2
vmsr MVFR2, r7
vmrs r4, mvfr2
vmsr mvfr2, r5
|
stsp/binutils-ia16
| 2,460
|
gas/testsuite/gas/arm/armv8-a+crypto.s
|
.syntax unified
.arch armv8-a
.arch_extension crypto
.arm
vmull.p64 q0, d0, d0
vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
aese.8 q15, q15
aesd.8 q0, q0
aesd.8 q7, q7
aesd.8 q8, q8
aesd.8 q15, q15
aesmc.8 q0, q0
aesmc.8 q7, q7
aesmc.8 q8, q8
aesmc.8 q15, q15
aesimc.8 q0, q0
aesimc.8 q7, q7
aesimc.8 q8, q8
aesimc.8 q15, q15
sha1c.32 q0, q0, q0
sha1c.32 q7, q7, q7
sha1c.32 q8, q8, q8
sha1c.32 q15, q15, q15
sha1p.32 q0, q0, q0
sha1p.32 q7, q7, q7
sha1p.32 q8, q8, q8
sha1p.32 q15, q15, q15
sha1m.32 q0, q0, q0
sha1m.32 q7, q7, q7
sha1m.32 q8, q8, q8
sha1m.32 q15, q15, q15
sha1su0.32 q0, q0, q0
sha1su0.32 q7, q7, q7
sha1su0.32 q8, q8, q8
sha1su0.32 q15, q15, q15
sha256h.32 q0, q0, q0
sha256h.32 q7, q7, q7
sha256h.32 q8, q8, q8
sha256h.32 q15, q15, q15
sha256h2.32 q0, q0, q0
sha256h2.32 q7, q7, q7
sha256h2.32 q8, q8, q8
sha256h2.32 q15, q15, q15
sha256su1.32 q0, q0, q0
sha256su1.32 q7, q7, q7
sha256su1.32 q8, q8, q8
sha256su1.32 q15, q15, q15
sha1h.32 q0, q0
sha1h.32 q7, q7
sha1h.32 q8, q8
sha1h.32 q15, q15
sha1su1.32 q0, q0
sha1su1.32 q7, q7
sha1su1.32 q8, q8
sha1su1.32 q15, q15
sha256su0.32 q0, q0
sha256su0.32 q7, q7
sha256su0.32 q8, q8
sha256su0.32 q15, q15
.thumb
vmull.p64 q0, d0, d0
vmull.p64 q15, d31, d31
aese.8 q0, q0
aese.8 q7, q7
aese.8 q8, q8
aese.8 q15, q15
aesd.8 q0, q0
aesd.8 q7, q7
aesd.8 q8, q8
aesd.8 q15, q15
aesmc.8 q0, q0
aesmc.8 q7, q7
aesmc.8 q8, q8
aesmc.8 q15, q15
aesimc.8 q0, q0
aesimc.8 q7, q7
aesimc.8 q8, q8
aesimc.8 q15, q15
sha1c.32 q0, q0, q0
sha1c.32 q7, q7, q7
sha1c.32 q8, q8, q8
sha1c.32 q15, q15, q15
sha1p.32 q0, q0, q0
sha1p.32 q7, q7, q7
sha1p.32 q8, q8, q8
sha1p.32 q15, q15, q15
sha1m.32 q0, q0, q0
sha1m.32 q7, q7, q7
sha1m.32 q8, q8, q8
sha1m.32 q15, q15, q15
sha1su0.32 q0, q0, q0
sha1su0.32 q7, q7, q7
sha1su0.32 q8, q8, q8
sha1su0.32 q15, q15, q15
sha256h.32 q0, q0, q0
sha256h.32 q7, q7, q7
sha256h.32 q8, q8, q8
sha256h.32 q15, q15, q15
sha256h2.32 q0, q0, q0
sha256h2.32 q7, q7, q7
sha256h2.32 q8, q8, q8
sha256h2.32 q15, q15, q15
sha256su1.32 q0, q0, q0
sha256su1.32 q7, q7, q7
sha256su1.32 q8, q8, q8
sha256su1.32 q15, q15, q15
sha1h.32 q0, q0
sha1h.32 q7, q7
sha1h.32 q8, q8
sha1h.32 q15, q15
sha1su1.32 q0, q0
sha1su1.32 q7, q7
sha1su1.32 q8, q8
sha1su1.32 q15, q15
sha256su0.32 q0, q0
sha256su0.32 q7, q7
sha256su0.32 q8, q8
sha256su0.32 q15, q15
|
stsp/binutils-ia16
| 2,093
|
gas/testsuite/gas/arm/mve-vldr-bad-1.s
|
.macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().u32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vldrb.16 q0, [r0, q1]
vldrb.p16 q0, [r0, q1]
vldrb.f16 q0, [r0, q1]
vldrb.32 q0, [r0, q1]
vldrb.f32 q0, [r0, q1]
vldrb.64 q0, [r0, q1]
vldrb.u64 q0, [r0, q1]
vldrb.s64 q0, [r0, q1]
vldrb.u32 q0, [pc, q1]
vldrb.u32 q0, [r0, q0]
cond vldrb
it eq
vldrbeq.u32 q0, [r0, q1]
vldrbeq.u32 q0, [r0, q1]
vpst
vldrbeq.u32 q0, [r0, q1]
vldrbt.u32 q0, [r0, q1]
vpst
vldrb.u32 q0, [r0, q1]
vldrh.32 q0, [r0, q1]
vldrh.f32 q0, [r0, q1]
vldrh.64 q0, [r0, q1]
vldrh.u64 q0, [r0, q1]
vldrh.s64 q0, [r0, q1]
vldrh.u32 q0, [pc, q1]
vldrh.u32 q0, [r0, q0]
cond vldrh
it eq
vldrheq.u32 q0, [r0, q1]
vldrheq.u32 q0, [r0, q1]
vpst
vldrheq.u32 q0, [r0, q1]
vldrht.u32 q0, [r0, q1]
vpst
vldrh.u32 q0, [r0, q1]
vldrw.64 q0, [r0, q1]
vldrw.u64 q0, [r0, q1]
vldrw.s64 q0, [r0, q1]
vldrw.u32 q0, [pc, q1]
vldrw.u32 q0, [r0, q0]
cond vldrw
it eq
vldrweq.u32 q0, [r0, q1]
vldrweq.u32 q0, [r0, q1]
vpst
vldrweq.u32 q0, [r0, q1]
vldrwt.u32 q0, [r0, q1]
vpst
vldrw.u32 q0, [r0, q1]
.macro cond64
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vldrd.u64 q0, [r0, q1]
.endr
.endm
vldrd.8 q0, [r0, q1]
vldrd.u8 q0, [r0, q1]
vldrd.s8 q0, [r0, q1]
vldrd.p8 q0, [r0, q1]
vldrd.16 q0, [r0, q1]
vldrd.u16 q0, [r0, q1]
vldrd.s16 q0, [r0, q1]
vldrd.p16 q0, [r0, q1]
vldrd.f16 q0, [r0, q1]
vldrd.32 q0, [r0, q1]
vldrd.u32 q0, [r0, q1]
vldrd.s32 q0, [r0, q1]
vldrd.f32 q0, [r0, q1]
cond64
it eq
vldrdeq.u64 q0, [r0, q1]
vldrdeq.u64 q0, [r0, q1]
vpst
vldrdeq.u64 q0, [r0, q1]
vldrdt.u64 q0, [r0, q1]
vpst
vldrd.u64 q0, [r0, q1]
vldrb.u8 q0, [r0, q1, #0]
vldrb.u8 q0, [r0, q1, UXTW #1]
vldrb.u16 q0, [r0, q1, UXTW #1]
vldrb.u32 q0, [r0, q1, UXTW #1]
vldrh.u16 q0, [r0, q1, #1]
vldrh.u16 q0, [r0, q1, UXTW #2]
vldrh.u32 q0, [r0, q1, UXTW #2]
vldrh.u16 q0, [r0, q1, UXTW #3]
vldrh.u32 q0, [r0, q1, UXTW #3]
vldrw.u32 q0, [r0, q1, #2]
vldrw.u32 q0, [r0, q1, UXTW #1]
vldrw.u32 q0, [r0, q1, UXTW #3]
vldrd.u64 q0, [r0, q1, #3]
vldrd.u64 q0, [r0, q1, UXTW #1]
vldrd.u64 q0, [r0, q1, UXTW #2]
vldrd.u64 q0, [r0, q1, UXTW #4]
|
stsp/binutils-ia16
| 2,724
|
gas/testsuite/gas/arm/mve-vstrldr-1.s
|
.syntax unified
.thumb
.macro all_vstr op, size, ext
.irp op1, q0, q1, q2, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
.irp op3, q0, q1, q2, q4, q7
\op\()\size \op1, [\op2, \op3]
\op\()\size \op1, [\op2, \op3, uxtw #\ext]
.endr
.endr
.endr
.endm
.irp size, .8, .16, .32
all_vstr vstrb, \size, 0
.endr
.irp size, .16, .32
all_vstr vstrh, \size, 1
.endr
all_vstr vstrw, .32, 2
all_vstr vstrd, .64, 3
vpstete
vstrbt.8 q1, [r0, q0]
vstrbe.8 q1, [r2, q2]
vstrbt.16 q2, [r3, q1]
vstrbe.16 q3, [r4, q6]
vpstete
vstrbt.32 q4, [r8, q2]
vstrbe.32 q7, [sp, q6]
vstrht.16 q0, [r0, q1]
vstrhe.16 q2, [r2, q0]
vpstet
vstrht.32 q1, [r1, q7]
vstrhe.32 q3, [r3, q2]
vstrht.16 q4, [r6, q5, UXTW #1]
vpstete
vstrht.16 q6, [r10, q3, UXTW #1]
vstrhe.32 q5, [r7, q4, UXTW #1]
vstrht.32 q7, [sp, q6, UXTW #1]
vstrwe.32 q0, [r2, q1]
vpstete
vstrwt.32 q1, [r5, q7]
vstrwe.32 q2, [r8, q3, UXTW #2]
vstrwt.32 q5, [sp, q0, UXTW #2]
vstrde.64 q0, [sp, q7]
vpstte
vstrdt.64 q2, [r0, q1]
vstrdt.64 q3, [r3, q5, UXTW #3]
vstrde.64 q7, [r7, q4, UXTW #3]
.macro all_vldr op, size, ext
.irp op2, r0, r1, r2, r4, r7, r8, r10, r12, r13, r14
.irp op3, q1, q2, q4, q7
\op\()\size q0, [\op2, \op3]
\op\()\size q0, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q2, q4, q7
\op\()\size q1, [\op2, \op3]
\op\()\size q1, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q1, q4, q7
\op\()\size q2, [\op2, \op3]
\op\()\size q2, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q1, q2, q7
\op\()\size q4, [\op2, \op3]
\op\()\size q4, [\op2, \op3, uxtw #\ext]
.endr
.irp op3, q0, q1, q2, q4
\op\()\size q7, [\op2, \op3]
\op\()\size q7, [\op2, \op3, uxtw #\ext]
.endr
.endr
.endm
.irp data, .u8, .s16, .u16, .s32, .u32
all_vldr vldrb, \data, 0
.endr
.irp data, .u16, .s32, .u32
all_vldr vldrh, \data, 1
.endr
all_vldr vldrw, .u32, 2
all_vldr vldrd, .u64, 3
vpstete
vldrbt.u8 q1, [r0, q0]
vldrbe.u8 q1, [r2, q2]
vldrbt.u16 q2, [r3, q1]
vldrbe.s16 q3, [r4, q6]
vpstete
vldrbt.u32 q4, [r8, q2]
vldrbe.s32 q7, [sp, q6]
vldrht.u16 q0, [r0, q1]
vldrhe.u16 q2, [r2, q0]
vpstete
vldrht.u32 q1, [r1, q7]
vldrhe.u32 q3, [r3, q2]
vldrht.u16 q4, [r6, q5, UXTW #1]
vldrhe.u16 q6, [r10, q3, UXTW #1]
vpstete
vldrht.u32 q5, [r7, q4, UXTW #1]
vldrhe.u32 q7, [sp, q6, UXTW #1]
vldrwt.u32 q0, [r2, q1]
vldrwe.u32 q1, [r5, q7]
vpstete
vldrwt.u32 q2, [r8, q3, UXTW #2]
vldrwe.u32 q5, [sp, q0, UXTW #2]
vldrdt.u64 q0, [sp, q7]
vldrde.u64 q2, [r0, q1]
vpste
vldrdt.u64 q3, [r3, q5, UXTW #3]
vldrde.u64 q7, [r7, q4, UXTW #3]
.irp dt, u8, s16, 8
vldrb.\dt q0, [r2, q3]
.endr
.irp dt, 16, u16, s32, f16, p16, u32
vldrh.\dt q0, [r2, q3, UXTW #1]
.endr
.irp dt, 32, u32, f32, p32
vldrw.\dt q0, [r2, q3, UXTW #2]
.endr
.irp dt, 64, u64, f64, p64
vldrd.\dt q0, [r2, q3, UXTW #3]
.endr
|
stsp/binutils-ia16
| 1,105
|
gas/testsuite/gas/arm/mve-vqdmull-bad.s
|
.macro cond op, lastreg
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 q0, q1, \lastreg
.endr
.endm
.syntax unified
.thumb
vqdmullt.s8 q0, q1, q2
vqdmullt.u8 q0, q1, q2
vqdmullt.i16 q0, q1, q2
vqdmullt.s64 q0, q1, q2
vqdmullb.s8 q0, q1, q2
vqdmullb.u8 q0, q1, q2
vqdmullb.i16 q0, q1, q2
vqdmullb.s64 q0, q1, q2
vqdmullt.s8 q0, q1, r2
vqdmullt.u8 q0, q1, r2
vqdmullt.i16 q0, q1, r2
vqdmullt.s64 q0, q1, r2
vqdmullb.s8 q0, q1, r2
vqdmullb.u8 q0, q1, r2
vqdmullb.i16 q0, q1, r2
vqdmullb.s64 q0, q1, r2
vqdmullt.s32 q0, q0, q2
vqdmullt.s32 q0, q1, q0
vqdmullb.s32 q0, q0, q2
vqdmullb.s32 q0, q1, q0
vqdmullt.s32 q0, q0, r2
vqdmullb.s32 q0, q0, r2
vqdmullt.s16 q0, q0, sp
vqdmullt.s16 q0, q0, pc
vqdmullb.s16 q0, q0, sp
vqdmullb.s16 q0, q0, pc
cond vqdmullt, q2
cond vqdmullb, q2
cond vqdmullt, r2
cond vqdmullb, r2
it eq
vqdmullteq.s32 q0, q1, q2
vqdmullteq.s32 q0, q1, q2
vpst
vqdmullteq.s32 q0, q1, q2
vqdmulltt.s32 q0, q1, q2
vpst
vqdmullt.s32 q0, q1, q2
it eq
vqdmullbeq.s32 q0, q1, q2
vqdmullbeq.s32 q0, q1, q2
vpst
vqdmullbeq.s32 q0, q1, q2
vqdmullbt.s32 q0, q1, q2
vpst
vqdmullb.s32 q0, q1, q2
|
stsp/binutils-ia16
| 1,305
|
gas/testsuite/gas/arm/mve-vmlaldav-bad.s
|
.macro cond, op
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\op\().s16 r0, r1, q1, q2
.endr
.endm
.syntax unified
.thumb
vmlaldav.s16 r0, sp, q1, q2
cond vmlaldav
cond vmlaldava
cond vmlaldavx
cond vmlaldavax
vmlaldav.s64 r0, r1, q1, q2
vmlaldav.f32 r0, r1, q1, q2
vmlaldav.s8 r0, r1, q1, q2
vmlaldav.s16 r0, q1, q2
vmlaldava.s64 r0, r1, q1, q2
vmlaldava.f32 r0, r1, q1, q2
vmlaldava.s8 r0, r1, q1, q2
vmlaldava.s16 r0, q1, q2
vmlaldavx.s64 r0, r1, q1, q2
vmlaldavx.f32 r0, r1, q1, q2
vmlaldavx.s8 r0, r1, q1, q2
vmlaldavx.s16 r0, q1, q2
vmlaldavax.s64 r0, r1, q1, q2
vmlaldavax.f32 r0, r1, q1, q2
vmlaldavax.s8 r0, r1, q1, q2
vmlaldavax.s16 r0, q1, q2
it eq
vmlaldaveq.s16 r0, r1, q1, q2
vmlaldaveq.s16 r0, r1, q1, q2
vmlaldaveq.s16 r0, r1, q1, q2
vmlaldavt.s16 r0, r1, q1, q2
vpst
vmlaldav.s16 r0, r1, q1, q2
it eq
vmlaldavaeq.s16 r0, r1, q1, q2
vmlaldavaeq.s16 r0, r1, q1, q2
vmlaldavaeq.s16 r0, r1, q1, q2
vmlaldavat.s16 r0, r1, q1, q2
vpst
vmlaldava.s16 r0, r1, q1, q2
it eq
vmlaldavxeq.s16 r0, r1, q1, q2
vmlaldavxeq.s16 r0, r1, q1, q2
vmlaldavxeq.s16 r0, r1, q1, q2
vmlaldavxt.s16 r0, r1, q1, q2
vpst
vmlaldavx.s16 r0, r1, q1, q2
it eq
vmlaldavaxeq.s16 r0, r1, q1, q2
vmlaldavaxeq.s16 r0, r1, q1, q2
vmlaldavaxeq.s16 r0, r1, q1, q2
vmlaldavaxt.s16 r0, r1, q1, q2
vpst
vmlaldavax.s16 r0, r1, q1, q2
|
stsp/binutils-ia16
| 4,535
|
gas/testsuite/gas/arm/archv6.s
|
.text
.align 0
label:
cps #15
cpsid if
cpsie if
ldrex r2, [r4]
ldrexne r4, [r8]
mcrr2 p0, 12, r7, r5, c3
mrrc2 p0, 12, r7, r5, c3
pkhbt r2, r5, r8
pkhbt r2, r5, r8, LSL #3
pkhbtal r2, r5, r8, LSL #3
pkhbteq r2, r5, r8, LSL #3
pkhtb r2, r5, r8 @ Equivalent to pkhbt r2, r8, r5.
pkhtb r2, r5, r8, ASR #3
pkhtbal r2, r5, r8, ASR #3
pkhtbeq r2, r5, r8, ASR #3
qadd16 r2, r4, r7
qadd16ne r2, r4, r7
qadd8 r2, r4, r7
qadd8ne r2, r4, r7
qaddsubx r2, r4, r7
qaddsubxne r2, r4, r7
qsub16 r2, r4, r7
qsub16ne r2, r4, r7
qsub8 r2, r4, r7
qsub8ne r2, r4, r7
qsubaddx r2, r4, r7
qsubaddx r2, r4, r7
rev r2, r4
rev16 r2, r4
rev16ne r3, r5
revne r3, r5
revsh r2, r4
revshne r3, r5
rfeda r2
rfefa r2!
rfedb r2
rfeea r2!
rfeia r2
rfefd r2!
rfeib r2
rfeed r2!
rfe r2
rfe r2!
sadd16 r2, r4, r7
sadd16ne r2, r4, r7
sxtah r2, r4, r5
sxtah r2, r4, r5, ROR #8
sxtahne r2, r4, r5
sxtahne r2, r4, r5, ROR #8
sadd8 r2, r4, r7
sadd8ne r2, r4, r7
sxtab16 r2, r4, r5
sxtab16 r2, r4, r5, ROR #8
sxtab16ne r2, r4, r5
sxtab16ne r2, r4, r5, ROR #8
sxtab r2, r4, r5
sxtab r2, r4, r5, ROR #8
sxtabne r2, r4, r5
sxtabne r2, r4, r5, ROR #8
saddsubx r2, r4, r7
saddsubxne r2, r4, r7
sel r1, r2, r3
selne r1, r2, r3
setend be
setend le
shadd16 r2, r4, r7
shadd16ne r2, r4, r7
shadd8 r2, r4, r7
shadd8ne r2, r4, r7
shaddsubx r2, r4, r7
shaddsubxne r2, r4, r7
shsub16 r2, r4, r7
shsub16ne r2, r4, r7
shsub8 r2, r4, r7
shsub8ne r2, r4, r7
shsubaddx r2, r4, r7
shsubaddxne r2, r4, r7
smlad r1,r2,r3,r4
smladle r1,r2,r3,r4
smladx r1,r2,r3,r4
smladxle r1,r2,r3,r4
smlald r1,r2,r3,r4
smlaldle r1,r2,r3,r4
smlaldx r1,r2,r3,r4
smlaldxle r1,r2,r3,r4
smlsd r1,r2,r3,r4
smlsdle r1,r2,r3,r4
smlsdx r1,r2,r3,r4
smlsdxle r1,r2,r3,r4
smlsld r1,r2,r3,r4
smlsldle r1,r2,r3,r4
smlsldx r1,r2,r3,r4
smlsldxle r1,r2,r3,r4
smmla r1,r2,r3,r4
smmlale r1,r2,r3,r4
smmlar r1,r2,r3,r4
smmlarle r1,r2,r3,r4
smmls r1,r2,r3,r4
smmlsle r1,r2,r3,r4
smmlsr r1,r2,r3,r4
smmlsrle r1,r2,r3,r4
smmul r1,r2,r3
smmulle r1,r2,r3
smmulr r1,r2,r3
smmulrle r1,r2,r3
smuad r1,r2,r3
smuadle r1,r2,r3
smuadx r1,r2,r3
smuadxle r1,r2,r3
smusd r1,r2,r3
smusdle r1,r2,r3
smusdx r1,r2,r3
smusdxle r1,r2,r3
srsia #16
srsib #16!
ssat r1, #1, r2
ssat r1, #1, r2, ASR #2
ssat r1, #1, r2, LSL #2
ssat16 r1, #1, r1
ssat16le r1, #1, r1
ssub16 r2, r4, r7
ssub16ne r2, r4, r7
ssub8 r2, r4, r7
ssub8ne r2, r4, r7
ssubaddx r2, r4, r7
ssubaddxne r2, r4, r7
strex r1, r2, [r3]
strexne r1, r2, [r3]
sxth r2, r5
sxth r2, r5, ROR #8
sxthne r2, r5
sxthne r2, r5, ROR #8
sxtb16 r2, r5
sxtb16 r2, r5, ROR #8
sxtb16ne r2, r5
sxtb16ne r2, r5, ROR #8
sxtb r2, r5
sxtb r2, r5, ROR #8
sxtbne r2, r5
sxtbne r2, r5, ROR #8
uadd16 r2, r4, r7
uadd16ne r2, r4, r7
uxtah r2, r3, r5
uxtah r2, r3, r5, ROR #8
uxtahne r2, r3, r5
uxtahne r2, r3, r5, ROR #8
uadd8 r2, r4, r7
uadd8ne r2, r4, r7
uxtab16 r2, r3, r5
uxtab16 r2, r3, r5, ROR #8
uxtab16ne r2, r3, r5
uxtab16ne r2, r3, r5, ROR #8
uxtab r2, r3, r5
uxtab r2, r3, r5, ROR #8
uxtabne r2, r3, r5
uxtabne r2, r3, r5, ROR #8
uaddsubx r2, r4, r7
uaddsubxne r2, r4, r7
uhadd16 r2, r4, r7
uhadd16ne r2, r4, r7
uhadd8 r2, r4, r7
uhadd8ne r2, r4, r7
uhaddsubx r2, r4, r7
uhaddsubxne r2, r4, r7
uhsub16 r2, r4, r7
uhsub16ne r2, r4, r7
uhsub8 r2, r4, r7
uhsub8ne r2, r4, r7
uhsubaddx r2, r4, r7
uhsubaddxne r2, r4, r7
umaal r1, r2, r3, r4
umaalle r1, r2, r3, r4
uqadd16 r2, r4, r7
uqadd16ne r2, r4, r7
uqadd8 r2, r4, r7
uqadd8ne r2, r4, r7
uqaddsubx r2, r4, r7
uqaddsubxne r2, r4, r7
uqsub16 r2, r4, r7
uqsub16ne r2, r4, r7
uqsub8 r2, r4, r7
uqsub8ne r2, r4, r7
uqsubaddx r2, r4, r7
uqsubaddxne r2, r4, r7
usad8 r1, r2, r3
usad8ne r1, r2, r3
usada8 r1, r2, r3, r4
usada8ne r1, r2, r3, r4
usat r1, #15, r2
usat r1, #15, r2, ASR #4
usat r1, #15, r2, LSL #4
usat16 r1, #15, r2
usat16le r1, #15, r2
usatle r1, #15, r2
usatle r1, #15, r2, ASR #4
usatle r1, #15, r2, LSL #4
usub16 r2, r4, r7
usub16ne r2, r4, r7
usub8 r2, r4, r7
usub8ne r2, r4, r7
usubaddx r2, r4, r7
usubaddxne r2, r4, r7
uxth r2, r5
uxth r2, r5, ROR #8
uxthne r2, r5
uxthne r2, r5, ROR #8
uxtb16 r2, r5
uxtb16 r2, r5, ROR #8
uxtb16ne r2, r5
uxtb16ne r2, r5, ROR #8
uxtb r2, r5
uxtb r2, r5, ROR #8
uxtbne r2, r5
uxtbne r2, r5, ROR #8
cpsie if, #10
cpsie if, #21
srsia sp, #16
srsib sp!, #16
|
stsp/binutils-ia16
| 1,332
|
gas/testsuite/gas/arm/arm7t.s
|
.text
.align 0
loadhalfwords:
ldrh r0, [r1]
ldrh r0, [r1]!
ldrh r0, [r1, r2]
ldrh r0, [r1, r2]!
ldrh r0, [r1,#0x0C]
ldrh r0, [r1,#0x0C]!
ldrh r0, [r1,#-0x0C]
ldrh r0, [r1], r2
ldrh r0, =0xFF00
ldrh r0, =0xC0DE
ldrh r0, .L2
storehalfwords:
strh r0, [r1]
strh r0, [r1]!
strh r0, [r1, r2]
strh r0, [r1, r2]!
strh r0, [r1,#0x0C]
strh r0, [r1,#0x0C]!
strh r0, [r1,#-0x0C]
strh r0, [r1], r2
strh r0, .L2
loadsignedbytes:
ldrsb r0, [r1]
ldrsb r0, [r1]!
ldrsb r0, [r1, r2]
ldrsb r0, [r1, r2]!
ldrsb r0, [r1,#0x0C]
ldrsb r0, [r1,#0x0C]!
ldrsb r0, [r1,#-0x0C]
ldrsb r0, [r1], r2
ldrsb r0, =0xDE
ldrsb r0, .L2
loadsignedhalfwords:
ldrsh r0, [r1]
ldrsh r0, [r1]!
ldrsh r0, [r1, r2]
ldrsh r0, [r1, r2]!
ldrsh r0, [r1, #0x0C]
ldrsh r0, [r1, #0x0C]!
ldrsh r0, [r1, #-0x0C]
ldrsh r0, [r1], r2
ldrsh r0, =0xFF00
ldrsh r0, =0xC0DE
ldrsh r0, .L2
misc:
ldralh r0, [r1, r2]
ldrneh r0, [r1, r2]
ldrhih r0, [r1, r2]
ldrlth r0, [r1, r2]
ldralsh r0, [r1, r2]
ldrnesh r0, [r1, r2]
ldrhish r0, [r1, r2]
ldrltsh r0, [r1, r2]
ldralsb r0, [r1, r2]
ldrnesb r0, [r1, r2]
ldrhisb r0, [r1, r2]
ldrltsb r0, [r1, r2]
ldrsh r0, =0xC0DE
ldrsh r0, =0xDEAD
.align
.L2:
.word fred
.ltorg
# Add two nop instructions to ensure that the
# output is 32-byte aligned as required for arm-aout.
nop
nop
|
stsp/binutils-ia16
| 2,214
|
gas/testsuite/gas/arm/mve-vstr-bad-1.s
|
.macro cond mnem
.irp cond, eq, ne, gt, ge, lt, le
it \cond
\mnem\().32 q0, [r0, q1]
.endr
.endm
.syntax unified
.thumb
vstrb.s8 q0, [r0, q1]
vstrb.u8 q0, [r0, q1]
vstrb.s16 q0, [r0, q1]
vstrb.u16 q0, [r0, q1]
vstrb.f16 q0, [r0, q1]
vstrb.u32 q0, [r0, q1]
vstrb.s32 q0, [r0, q1]
vstrb.f32 q0, [r0, q1]
vstrb.64 q0, [r0, q1]
vstrb.16 q0, [pc, q1]
cond vstrb
vstrh.8 q0, [r0, q1]
vstrh.s8 q0, [r0, q1]
vstrh.u8 q0, [r0, q1]
vstrh.s16 q0, [r0, q1]
vstrh.u16 q0, [r0, q1]
vstrh.f16 q0, [r0, q1]
vstrh.u32 q0, [r0, q1]
vstrh.s32 q0, [r0, q1]
vstrh.f32 q0, [r0, q1]
vstrh.64 q0, [r0, q1]
vstrh.16 q0, [pc, q1]
cond vstrh
vstrh.16 q0, [r0, q1, #1]
vstrh.16 q0, [r0, q1, UXTW #2]
vstrw.8 q0, [r0, q1]
vstrw.u8 q0, [r0, q1]
vstrw.s8 q0, [r0, q1]
vstrw.16 q0, [r0, q1]
vstrw.f16 q0, [r0, q1]
vstrw.u16 q0, [r0, q1]
vstrw.s16 q0, [r0, q1]
vstrw.u32 q0, [r0, q1]
vstrw.s32 q0, [r0, q1]
vstrw.f32 q0, [r0, q1]
vstrw.64 q0, [r0, q1]
vstrw.32 q0, [pc, q1]
cond vstrw
vstrw.32 q0, [r0, q1, #2]
vstrw.32 q0, [r0, q1, UXTW #1]
vstrw.32 q0, [r0, q1, UXTW #3]
vstrd.8 q0, [r0, q1]
vstrd.u8 q0, [r0, q1]
vstrd.s8 q0, [r0, q1]
vstrd.16 q0, [r0, q1]
vstrd.u16 q0, [r0, q1]
vstrd.s16 q0, [r0, q1]
vstrd.f16 q0, [r0, q1]
vstrd.32 q0, [r0, q1]
vstrd.u32 q0, [r0, q1]
vstrd.s32 q0, [r0, q1]
vstrd.f32 q0, [r0, q1]
vstrd.f64 q0, [r0, q1]
vstrd.u64 q0, [r0, q1]
vstrd.s64 q0, [r0, q1]
.macro cond64
.irp cond, eq, ne, gt, ge, lt, le
it \cond
vstrd\().64 q0, [r0, q1]
.endr
.endm
cond64
vstrd.64 q0, [r0, q1, #3]
vstrd.64 q0, [r0, q1, UXTW #1]
vstrd.64 q0, [r0, q1, UXTW #2]
vstrd.64 q0, [r0, q1, UXTW #4]
it eq
vstrbeq.32 q0, [r0, q1]
vstrbeq.32 q0, [r0, q1]
vpst
vstrbeq.32 q0, [r0, q1]
vpst
vstrb.32 q0, [r0, q1]
vstrbt.32 q0, [r0, q1]
vstrbe.32 q0, [r0, q1]
it eq
vstrheq.32 q0, [r0, q1]
vstrheq.32 q0, [r0, q1]
vpst
vstrheq.32 q0, [r0, q1]
vpst
vstrh.32 q0, [r0, q1]
vstrht.32 q0, [r0, q1]
vstrhe.32 q0, [r0, q1]
it eq
vstrweq.32 q0, [r0, q1]
vstrweq.32 q0, [r0, q1]
vpst
vstrweq.32 q0, [r0, q1]
vpst
vstrw.32 q0, [r0, q1]
vstrwt.32 q0, [r0, q1]
vstrwe.32 q0, [r0, q1]
it eq
vstrdeq.64 q0, [r0, q1]
vstrdeq.64 q0, [r0, q1]
vpst
vstrdeq.64 q0, [r0, q1]
vpst
vstrd.64 q0, [r0, q1]
vstrdt.64 q0, [r0, q1]
vstrde.64 q0, [r0, q1]
|
stsp/binutils-ia16
| 4,056
|
gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s
|
@ LDC group relocation tests that are supposed to fail during encoding.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store cst
\load 0, c0, [r0, #:pc_g0:(f + \cst)]
\load 0, c0, [r0, #:pc_g1:(f + \cst)]
\load 0, c0, [r0, #:pc_g2:(f + \cst)]
\load 0, c0, [r0, #:sb_g0:(f + \cst)]
\load 0, c0, [r0, #:sb_g1:(f + \cst)]
\load 0, c0, [r0, #:sb_g2:(f + \cst)]
\store 0, c0, [r0, #:pc_g0:(f + \cst)]
\store 0, c0, [r0, #:pc_g1:(f + \cst)]
\store 0, c0, [r0, #:pc_g2:(f + \cst)]
\store 0, c0, [r0, #:sb_g0:(f + \cst)]
\store 0, c0, [r0, #:sb_g1:(f + \cst)]
\store 0, c0, [r0, #:sb_g2:(f + \cst)]
\load 0, c0, [r0, #:pc_g0:(f - \cst)]
\load 0, c0, [r0, #:pc_g1:(f - \cst)]
\load 0, c0, [r0, #:pc_g2:(f - \cst)]
\load 0, c0, [r0, #:sb_g0:(f - \cst)]
\load 0, c0, [r0, #:sb_g1:(f - \cst)]
\load 0, c0, [r0, #:sb_g2:(f - \cst)]
\store 0, c0, [r0, #:pc_g0:(f - \cst)]
\store 0, c0, [r0, #:pc_g1:(f - \cst)]
\store 0, c0, [r0, #:pc_g2:(f - \cst)]
\store 0, c0, [r0, #:sb_g0:(f - \cst)]
\store 0, c0, [r0, #:sb_g1:(f - \cst)]
\store 0, c0, [r0, #:sb_g2:(f - \cst)]
.endm
ldctest ldc stc 0x1
ldctest ldcl stcl 0x1
ldctest ldc2 stc2 0x1
ldctest ldc2l stc2l 0x1
ldctest ldc stc 0x808
ldctest ldcl stcl 0x808
ldctest ldc2 stc2 0x808
ldctest ldc2l stc2l 0x808
@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
.fpu fpa
.macro fpa_test load store cst
\load f0, [r0, #:pc_g0:(f + \cst)]
\load f0, [r0, #:pc_g1:(f + \cst)]
\load f0, [r0, #:pc_g2:(f + \cst)]
\load f0, [r0, #:sb_g0:(f + \cst)]
\load f0, [r0, #:sb_g1:(f + \cst)]
\load f0, [r0, #:sb_g2:(f + \cst)]
\store f0, [r0, #:pc_g0:(f + \cst)]
\store f0, [r0, #:pc_g1:(f + \cst)]
\store f0, [r0, #:pc_g2:(f + \cst)]
\store f0, [r0, #:sb_g0:(f + \cst)]
\store f0, [r0, #:sb_g1:(f + \cst)]
\store f0, [r0, #:sb_g2:(f + \cst)]
\load f0, [r0, #:pc_g0:(f - \cst)]
\load f0, [r0, #:pc_g1:(f - \cst)]
\load f0, [r0, #:pc_g2:(f - \cst)]
\load f0, [r0, #:sb_g0:(f - \cst)]
\load f0, [r0, #:sb_g1:(f - \cst)]
\load f0, [r0, #:sb_g2:(f - \cst)]
\store f0, [r0, #:pc_g0:(f - \cst)]
\store f0, [r0, #:pc_g1:(f - \cst)]
\store f0, [r0, #:pc_g2:(f - \cst)]
\store f0, [r0, #:sb_g0:(f - \cst)]
\store f0, [r0, #:sb_g1:(f - \cst)]
\store f0, [r0, #:sb_g2:(f - \cst)]
.endm
fpa_test ldfs stfs 0x1
fpa_test ldfd stfd 0x1
fpa_test ldfe stfe 0x1
fpa_test ldfp stfp 0x1
fpa_test ldfs stfs 0x808
fpa_test ldfd stfd 0x808
fpa_test ldfe stfe 0x808
fpa_test ldfp stfp 0x808
@ FLDS/FSTS
.fpu vfp
.macro vfp_test load store reg cst
\load \reg, [r0, #:pc_g0:(f + \cst)]
\load \reg, [r0, #:pc_g1:(f + \cst)]
\load \reg, [r0, #:pc_g2:(f + \cst)]
\load \reg, [r0, #:sb_g0:(f + \cst)]
\load \reg, [r0, #:sb_g1:(f + \cst)]
\load \reg, [r0, #:sb_g2:(f + \cst)]
\store \reg, [r0, #:pc_g0:(f + \cst)]
\store \reg, [r0, #:pc_g1:(f + \cst)]
\store \reg, [r0, #:pc_g2:(f + \cst)]
\store \reg, [r0, #:sb_g0:(f + \cst)]
\store \reg, [r0, #:sb_g1:(f + \cst)]
\store \reg, [r0, #:sb_g2:(f + \cst)]
\load \reg, [r0, #:pc_g0:(f - \cst)]
\load \reg, [r0, #:pc_g1:(f - \cst)]
\load \reg, [r0, #:pc_g2:(f - \cst)]
\load \reg, [r0, #:sb_g0:(f - \cst)]
\load \reg, [r0, #:sb_g1:(f - \cst)]
\load \reg, [r0, #:sb_g2:(f - \cst)]
\store \reg, [r0, #:pc_g0:(f - \cst)]
\store \reg, [r0, #:pc_g1:(f - \cst)]
\store \reg, [r0, #:pc_g2:(f - \cst)]
\store \reg, [r0, #:sb_g0:(f - \cst)]
\store \reg, [r0, #:sb_g1:(f - \cst)]
\store \reg, [r0, #:sb_g2:(f - \cst)]
.endm
vfp_test flds fsts s0 0x1
vfp_test flds fsts s0 0x808
@ FLDD/FSTD
vfp_test fldd fstd d0 0x1
vfp_test fldd fstd d0 0x808
@ VLDR/VSTR
vfp_test vldr vstr d0 0x1
vfp_test vldr vstr d0 0x808
@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
.cpu ep9312
vfp_test cfldrs cfstrs mvf0 0x1
vfp_test cfldrd cfstrd mvd0 0x1
vfp_test cfldr32 cfstr32 mvfx0 0x1
vfp_test cfldr64 cfstr64 mvdx0 0x1
vfp_test cfldrs cfstrs mvf0 0x808
vfp_test cfldrd cfstrd mvd0 0x808
vfp_test cfldr32 cfstr32 mvfx0 0x808
vfp_test cfldr64 cfstr64 mvdx0 0x808
|
stsp/binutils-ia16
| 1,975
|
gas/testsuite/gas/arm/mve-vpt.s
|
.syntax unified
.thumb
.macro ins_2 cond2
vaddt.i32 q0, q1, q2
vadd\cond2\().i32 q0, q1, q2
.endm
.macro ins_3 cond2, cond3
ins_2 \cond2
vadd\cond3\().i32 q0, q1, q2
.endm
.macro ins_4 cond2, cond3, cond4
ins_3 \cond2, \cond3
vadd\cond4\().i32 q0, q1, q2
.endm
.macro vpt_1 data, cond, op1, op2
vpt\data \cond, \op1, \op2
vaddt.i32 q0, q1, q2
.endm
.macro help mask, data, cond, op1, op2
vpt\mask\data \cond, \op1, \op2
.endm
.macro vpt_2 data, cond, op1, op2
.irp cond2, t, e
help \cond2, \data, \cond, \op1, \op2
ins_2 \cond2
.endr
.endm
.macro vpt_3 data, cond, op1, op2
.irp cond2, t, e
.irp cond3, t, e
help \cond2\cond3, \data, \cond, \op1, \op2
ins_3 \cond2, \cond3
.endr
.endr
.endm
.macro vpt_4 data, cond, op1, op2
.irp cond2, t, e
.irp cond3, t, e
.irp cond4, t, e
help \cond2\cond3\cond4, \data, \cond, \op1, \op2
ins_4 \cond2, \cond3, \cond4
.endr
.endr
.endr
.endm
.macro vpt_qq data, cond
.irp op1, q0, q1, q4, q7
.irp op2, q0, q2, q5, q7
vpt_1 \data, \cond, \op1, \op2
vpt_2 \data, \cond, \op1, \op2
vpt_3 \data, \cond, \op1, \op2
vpt_4 \data, \cond, \op1, \op2
.endr
.endr
.endm
.macro vpt_qr data, cond
.irp op1, q0, q1, q4, q7
.irp op2, r0, r1, r2, r4, r7, r8, r9, r10, r12, r14, zr
vpt_1 \data, \cond, \op1, \op2
vpt_2 \data, \cond, \op1, \op2
vpt_3 \data, \cond, \op1, \op2
vpt_4 \data, \cond, \op1, \op2
.endr
.endr
.endm
.irp data, .f16, .f32
.irp cond, eq, ne, gt, le, ge, lt
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
.irp data, .i8, .i16, .i32
.irp cond, eq, ne
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
.irp data, .u8, .u16, .u32
.irp cond, cs, hi
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
.irp data, .s8, .s16, .s32
.irp cond, ge, lt, gt, le
vpt_qq \data, \cond
vpt_qr \data, \cond
.endr
.endr
vpst
vaddt.i32 q0, q1, q2
.irp cond2, t, e
vpst\cond2
ins_2 \cond2
.irp cond3, t, e
vpst\cond2\cond3
ins_3 \cond2, \cond3
.irp cond4, t, e
vpst\cond2\cond3\cond4
ins_4 \cond2, \cond3, \cond4
.endr
.endr
.endr
|
stsp/binutils-ia16
| 1,602
|
gas/testsuite/gas/arm/half-prec-vfpv3.s
|
.text
vcvtt.f32.f16 s0, s1
vcvtteq.f32.f16 s2, s3
vcvttne.f32.f16 s2, s3
vcvttcs.f32.f16 s2, s3
vcvttcc.f32.f16 s2, s3
vcvttmi.f32.f16 s2, s3
vcvttpl.f32.f16 s2, s3
vcvttvs.f32.f16 s2, s3
vcvttvc.f32.f16 s2, s3
vcvtthi.f32.f16 s2, s3
vcvttls.f32.f16 s2, s3
vcvttge.f32.f16 s2, s3
vcvttlt.f32.f16 s2, s3
vcvttgt.f32.f16 s2, s3
vcvttle.f32.f16 s2, s3
vcvttal.f32.f16 s2, s3
vcvtt.f16.f32 s0, s1
vcvtteq.f16.f32 s2, s3
vcvttne.f16.f32 s2, s3
vcvttcs.f16.f32 s2, s3
vcvttcc.f16.f32 s2, s3
vcvttmi.f16.f32 s2, s3
vcvttpl.f16.f32 s2, s3
vcvttvs.f16.f32 s2, s3
vcvttvc.f16.f32 s2, s3
vcvtthi.f16.f32 s2, s3
vcvttls.f16.f32 s2, s3
vcvttge.f16.f32 s2, s3
vcvttlt.f16.f32 s2, s3
vcvttgt.f16.f32 s2, s3
vcvttle.f16.f32 s2, s3
vcvttal.f16.f32 s2, s3
vcvtb.f32.f16 s0, s1
vcvtbeq.f32.f16 s2, s3
vcvtbne.f32.f16 s2, s3
vcvtbcs.f32.f16 s2, s3
vcvtbcc.f32.f16 s2, s3
vcvtbmi.f32.f16 s2, s3
vcvtbpl.f32.f16 s2, s3
vcvtbvs.f32.f16 s2, s3
vcvtbvc.f32.f16 s2, s3
vcvtbhi.f32.f16 s2, s3
vcvtbls.f32.f16 s2, s3
vcvtbge.f32.f16 s2, s3
vcvtblt.f32.f16 s2, s3
vcvtbgt.f32.f16 s2, s3
vcvtble.f32.f16 s2, s3
vcvtbal.f32.f16 s2, s3
vcvtb.f16.f32 s0, s1
vcvtbeq.f16.f32 s2, s3
vcvtbne.f16.f32 s2, s3
vcvtbcs.f16.f32 s2, s3
vcvtbcc.f16.f32 s2, s3
vcvtbmi.f16.f32 s2, s3
vcvtbpl.f16.f32 s2, s3
vcvtbvs.f16.f32 s2, s3
vcvtbvc.f16.f32 s2, s3
vcvtbhi.f16.f32 s2, s3
vcvtbls.f16.f32 s2, s3
vcvtbge.f16.f32 s2, s3
vcvtblt.f16.f32 s2, s3
vcvtbgt.f16.f32 s2, s3
vcvtble.f16.f32 s2, s3
vcvtbal.f16.f32 s2, s3
|
stsp/binutils-ia16
| 1,067
|
gas/testsuite/gas/arm/unwind.s
|
# Test generation of unwind tables
.text
foo: @ Simple function
.fnstart
.save {r4, lr}
mov r0, #0
.fnend
foo1: @ Typical frame pointer prologue
.fnstart
.movsp ip
@mov ip, sp
.pad #4
.save {fp, ip, lr}
@stmfd sp!, {fp, ip, lr, pc}
.setfp fp, ip, #4
@sub fp, ip, #4
mov r0, #1
.fnend
foo2: @ Custom personality routine
.fnstart
.save {r1, r4, r6, lr}
@stmfd {r1, r4, r6, lr}
mov r0, #2
.personality foo
.handlerdata
.word 42
.fnend
foo3: @ Saving iwmmxt registers
.fnstart
.save {wr12}
.save {wr13}
.save {wr11}
.save {wr10}
.save {wr10, wr11}
.save {wr0}
mov r0, #3
.fnend
.code 16
foo4: @ Thumb frame pointer
.fnstart
.save {r7, lr}
@push {r7, lr}
.setfp r7, sp
@mov r7, sp
.pad #8
@sub sp, sp, #8
mov r0, #4
.fnend
foo5: @ Save r0-r3 only.
.fnstart
.save {r0, r1, r2, r3}
mov r0, #5
.fnend
.code 32
foo6: @ Nested function with frame pointer
.fnstart
.pad #4
@push {ip}
.movsp ip, #4
@mov ip, sp
.pad #4
.save {fp, ip, lr}
@stmfd sp!, {fp, ip, lr, pc}
.setfp fp, ip, #-8
@sub fp, ip, #8
mov r0, #6
.fnend
|
stsp/binutils-ia16
| 1,716
|
gas/testsuite/gas/arm/armv8-ar.s
|
.syntax unified
.text
.arch armv8-a
.arm
foo:
sevl
hlt 0x0
hlt 0xf
hlt 0xfff0
stlb r0, [r0]
stlb r1, [r1]
stlb r14, [r14]
stlh r0, [r0]
stlh r1, [r1]
stlh r14, [r14]
stl r0, [r0]
stl r1, [r1]
stl r14, [r14]
stlexb r0, r1, [r14]
stlexb r1, r14, [r0]
stlexb r14, r0, [r1]
stlexh r0, r1, [r14]
stlexh r1, r14, [r0]
stlexh r14, r0, [r1]
stlex r0, r1, [r14]
stlex r1, r14, [r0]
stlex r14, r0, [r1]
stlexd r0, r2, r3, [r14]
stlexd r1, r12, r13, [r0]
stlexd r14, r0, r1, [r1]
ldab r0, [r0]
ldab r1, [r1]
ldab r14, [r14]
ldah r0, [r0]
ldah r1, [r1]
ldah r14, [r14]
lda r0, [r0]
lda r1, [r1]
lda r14, [r14]
ldaexb r0, [r0]
ldaexb r1, [r1]
ldaexb r14, [r14]
ldaexh r0, [r0]
ldaexh r1, [r1]
ldaexh r14, [r14]
ldaex r0, [r0]
ldaex r1, [r1]
ldaex r14, [r14]
ldaexd r0, r1, [r0]
ldaexd r2, r3, [r1]
ldaexd r12, r13, [r14]
.thumb
.thumb_func
bar:
sevl
sevl.n
sevl.w
dcps1
dcps2
dcps3
hlt 0
hlt 63
stlb r0, [r0]
stlb r1, [r1]
stlb r14, [r14]
stlh r0, [r0]
stlh r1, [r1]
stlh r14, [r14]
stl r0, [r0]
stl r1, [r1]
stl r14, [r14]
stlexb r0, r1, [r14]
stlexb r1, r14, [r0]
stlexb r14, r0, [r1]
stlexh r0, r1, [r14]
stlexh r1, r14, [r0]
stlexh r14, r0, [r1]
stlex r0, r1, [r14]
stlex r1, r14, [r0]
stlex r14, r0, [r1]
stlexd r0, r1, r1, [r14]
stlexd r1, r14, r14, [r0]
stlexd r14, r0, r0, [r1]
ldab r0, [r0]
ldab r1, [r1]
ldab r14, [r14]
ldah r0, [r0]
ldah r1, [r1]
ldah r14, [r14]
lda r0, [r0]
lda r1, [r1]
lda r14, [r14]
ldaexb r0, [r0]
ldaexb r1, [r1]
ldaexb r14, [r14]
ldaexh r0, [r0]
ldaexh r1, [r1]
ldaexh r14, [r14]
ldaex r0, [r0]
ldaex r1, [r1]
ldaex r14, [r14]
ldaexd r0, r1, [r0]
ldaexd r1, r14, [r1]
ldaexd r14, r0, [r14]
|
stsp/binutils-ia16
| 1,240
|
gas/testsuite/gas/arm/archv6t2-bad.s
|
@ We do not bother testing simple cases, e.g. immediates where
@ registers belong, trailing junk at end of line.
.text
x:
@ pc not allowed
bfc pc,#0,#1
bfi pc,r0,#0,#1
movw pc,#0
movt pc,#0
@ bitfield range limits
bfc r0,#0,#0
bfc r0,#32,#0
bfc r0,#0,#33
bfc r0,#33,#1
bfc r0,#32,#1
bfc r0,#28,#10
bfi r0,r1,#0,#0
bfi r0,r1,#32,#0
bfi r0,r1,#0,#33
bfi r0,r1,#33,#1
bfi r0,r1,#32,#1
bfi r0,r1,#28,#10
sbfx r0,r1,#0,#0
sbfx r0,r1,#32,#0
sbfx r0,r1,#0,#33
sbfx r0,r1,#33,#1
sbfx r0,r1,#32,#1
sbfx r0,r1,#28,#10
ubfx r0,r1,#0,#0
ubfx r0,r1,#32,#0
ubfx r0,r1,#0,#33
ubfx r0,r1,#33,#1
ubfx r0,r1,#32,#1
ubfx r0,r1,#28,#10
@ bfi accepts only #0 in Rm position
bfi r0,#1,#2,#3
@ mov16 range limits
movt r0,#65537
movw r0,#65537
movt r0,#-1
movw r0,#-1
@ ldsttv4 Rd == Rn (warning)
ldrht r0,[r0]
ldrsbt r0,[r0]
ldrsht r0,[r0]
strht r0,[r0]
@ Bug reported by user. GAS used to issue an error message
@ "r15 not allowed here" for these two instructions because
@ it thought that the "r2" operand was a PC-relative branch
@ to a label called "r2".
ldrex r0, r2
strex r1, r0, r2
@ movs shouldn't be extened to accept UINT16 can't fit into ARM modified
@ immediate format.
movs r0, #0x0999
|
stsp/binutils-ia16
| 2,935
|
gas/testsuite/gas/arm/msr-reg.s
|
@ Check MSR and MRS instruction operand syntax.
@ Also check for MSR/MRS acceptance in ARM/THUMB modes.
.section .text
.syntax unified
@ Write to Special Register from register
msr APSR,r9 @ deprecated usage.
msr APSR_g,r9
msr APSR_nzcvq,r9
msr APSR_nzcvqg,r9
@ Write to CPSR flags
msr CPSR,r9
msr CPSR_s,r9
msr CPSR_f,r9
msr CPSR_c,r9
msr CPSR_x,r9
@ Write to CPSR flag combos
msr CPSR_fs, r9
msr CPSR_fx, r9
msr CPSR_fc, r9
msr CPSR_sf, r9
msr CPSR_sx, r9
msr CPSR_sc, r9
msr CPSR_xf, r9
msr CPSR_xs, r9
msr CPSR_xc, r9
msr CPSR_cf, r9
msr CPSR_cs, r9
msr CPSR_cx, r9
msr CPSR_fsx, r9
msr CPSR_fsc, r9
msr CPSR_fxs, r9
msr CPSR_fxc, r9
msr CPSR_fcs, r9
msr CPSR_fcx, r9
msr CPSR_sfx, r9
msr CPSR_sfc, r9
msr CPSR_sxf, r9
msr CPSR_sxc, r9
msr CPSR_scf, r9
msr CPSR_scx, r9
msr CPSR_xfs, r9
msr CPSR_xfc, r9
msr CPSR_xsf, r9
msr CPSR_xsc, r9
msr CPSR_xcf, r9
msr CPSR_xcs, r9
msr CPSR_cfs, r9
msr CPSR_cfx, r9
msr CPSR_csf, r9
msr CPSR_csx, r9
msr CPSR_cxf, r9
msr CPSR_cxs, r9
msr CPSR_fsxc, r9
msr CPSR_fscx, r9
msr CPSR_fxsc, r9
msr CPSR_fxcs, r9
msr CPSR_fcsx, r9
msr CPSR_fcxs, r9
msr CPSR_sfxc, r9
msr CPSR_sfcx, r9
msr CPSR_sxfc, r9
msr CPSR_sxcf, r9
msr CPSR_scfx, r9
msr CPSR_scxf, r9
msr CPSR_xfsc, r9
msr CPSR_xfcs, r9
msr CPSR_xsfc, r9
msr CPSR_xscf, r9
msr CPSR_xcfs, r9
msr CPSR_xcsf, r9
msr CPSR_cfsx, r9
msr CPSR_cfxs, r9
msr CPSR_csfx, r9
msr CPSR_csxf, r9
msr CPSR_cxfs, r9
msr CPSR_cxsf, r9
@ Write to SPSR flags
msr SPSR,r9
msr SPSR_s,r9
msr SPSR_f,r9
msr SPSR_c,r9
msr SPSR_x,r9
@ Write to Saved status register
msr SPSR_fs, r9
msr SPSR_fx, r9
msr SPSR_fc, r9
msr SPSR_sf, r9
msr SPSR_sx, r9
msr SPSR_sc, r9
msr SPSR_xf, r9
msr SPSR_xs, r9
msr SPSR_xc, r9
msr SPSR_cf, r9
msr SPSR_cs, r9
msr SPSR_cx, r9
msr SPSR_fsx, r9
msr SPSR_fsc, r9
msr SPSR_fxs, r9
msr SPSR_fxc, r9
msr SPSR_fcs, r9
msr SPSR_fcx, r9
msr SPSR_sfx, r9
msr SPSR_sfc, r9
msr SPSR_sxf, r9
msr SPSR_sxc, r9
msr SPSR_scf, r9
msr SPSR_scx, r9
msr SPSR_xfs, r9
msr SPSR_xfc, r9
msr SPSR_xsf, r9
msr SPSR_xsc, r9
msr SPSR_xcf, r9
msr SPSR_xcs, r9
msr SPSR_cfs, r9
msr SPSR_cfx, r9
msr SPSR_csf, r9
msr SPSR_csx, r9
msr SPSR_cxf, r9
msr SPSR_cxs, r9
msr SPSR_fsxc, r9
msr SPSR_fscx, r9
msr SPSR_fxsc, r9
msr SPSR_fxcs, r9
msr SPSR_fcsx, r9
msr SPSR_fcxs, r9
msr SPSR_sfxc, r9
msr SPSR_sfcx, r9
msr SPSR_sxfc, r9
msr SPSR_sxcf, r9
msr SPSR_scfx, r9
msr SPSR_scxf, r9
msr SPSR_xfsc, r9
msr SPSR_xfcs, r9
msr SPSR_xsfc, r9
msr SPSR_xscf, r9
msr SPSR_xcfs, r9
msr SPSR_xcsf, r9
msr SPSR_cfsx, r9
msr SPSR_cfxs, r9
msr SPSR_csfx, r9
msr SPSR_csxf, r9
msr SPSR_cxfs, r9
msr SPSR_cxsf, r9
|
stsp/binutils-ia16
| 2,164
|
gas/testsuite/gas/arm/t16-bad.s
|
@ Things you can't do with 16-bit Thumb instructions, but you can
@ do with the equivalent ARM instruction. Does not include errors
@ caught by fixup processing (e.g. out-of-range immediates).
.text
.code 16
.thumb_func
l:
@ Arithmetic instruction templates
.macro ar2 opc
\opc r8,r0
\opc r0,r8
.endm
.macro ar2sh opc
ar2 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
.macro ar2r opc
ar2 \opc
\opc r0,r1,ror #8
.endm
.macro ar3 opc
\opc r1,r2,r3
\opc r8,r0
\opc r0,r8
.endm
.macro ar3sh opc
ar3 \opc
\opc r0,#12
\opc r0,r1,lsl #2
\opc r0,r1,lsl r3
.endm
ar2sh tst
ar2sh cmn
ar2sh mvn
ar2 neg
ar2 rev
ar2 rev16
ar2 revsh
ar2r sxtb
ar2r sxth
ar2r uxtb
ar2r uxth
ar3sh adc
ar3sh and
ar3sh bic
ar3sh eor
ar3sh orr
ar3sh sbc
ar3 mul
@ Shift instruction template
.macro shift opc
\opc r8,r0,#12 @ form 1
\opc r0,r8,#12
ar2 \opc @ form 2
.endm
shift asr
shift lsl
shift lsr
shift ror
ror r0,r1,#12
@ add/sub/mov/cmp are idiosyncratic
add r0,r1,lsl #2
add r0,r1,lsl r3
add r8,r0,#1 @ form 1
add r0,r8,#1
add r8,#10 @ form 2
add r8,r1,r2 @ form 3
add r1,r8,r2
add r1,r2,r8
add r8,pc,#4 @ form 5
add r8,sp,#4 @ form 6
ar3sh sub
sub r8,r0,#1 @ form 1
sub r0,r8,#1
sub r8,#10 @ form 2
sub r8,r1,r2 @ form 3
sub r1,r8,r2
sub r1,r2,r8
cmp r0,r1,lsl #2
cmp r0,r1,lsl r3
cmp r8,#255
mov r0,r1,lsl #2
mov r0,r1,lsl r3
mov r8,#255
@ Load/store template
.macro ldst opc
\opc r8,[r0]
\opc r0,[r8]
\opc r0,[r0,r8]
\opc r0,[r1,#4]!
\opc r0,[r1],#4
\opc r0,[r1,-r2]
\opc r0,[r1],r2
.endm
ldst ldr
ldst ldrb
ldst ldrh
ldst ldrsb
ldst ldrsh
ldst str
ldst strb
ldst strh
ldr r0,[r1,r2,lsl #1]
str r0,[r1,r2,lsl #1]
@ Load/store multiple
ldmia r8!,{r1,r2}
ldmia r7!,{r8}
ldmia r7,{r1,r2}
ldmia r7!,{r1,r7}
stmia r8!,{r1,r2}
stmia r7!,{r8}
stmia r7,{r1,r2}
stmia r7!,{r1,r7}
push {r8,r9}
pop {r8,r9}
@ Miscellaneous
bkpt #257
cpsie ai,#5
cpsid ai,#5
@ Conditional suffixes
addeq r0,r1,r2
@ low register non flag setting add.
.syntax unified
add r0, r1
@ Multiply
.syntax divided
mul r0, r0, r8
mul r0, r8, r0
mul r8, r0, r0
|
stsp/binutils-ia16
| 1,641
|
gas/testsuite/gas/sparc-solaris/sol-gcc.s
|
.file "hi-sol.c"
.stabs "/1h/devo/src/gas/testsuite/gas/",100,0,0,.LLtext0
.stabs "hi-sol.c",100,0,0,.LLtext0
.section ".text"
.LLtext0:
.stabs "gcc2_compiled.", 0x3c, 0, 0, 0
.stabs "int:t1=r1;-2147483648;2147483647;",128,0,0,0
.stabs "char:t2=r2;0;127;",128,0,0,0
.stabs "long int:t3=r1;-2147483648;2147483647;",128,0,0,0
.stabs "unsigned int:t4=r1;0;-1;",128,0,0,0
.stabs "long unsigned int:t5=r1;0;-1;",128,0,0,0
.stabs "short int:t6=r1;-32768;32767;",128,0,0,0
.stabs "long long int:t7=r1;0;-1;",128,0,0,0
.stabs "short unsigned int:t8=r1;0;65535;",128,0,0,0
.stabs "long long unsigned int:t9=r1;0;-1;",128,0,0,0
.stabs "signed char:t10=r1;-128;127;",128,0,0,0
.stabs "unsigned char:t11=r1;0;255;",128,0,0,0
.stabs "float:t12=r1;4;0;",128,0,0,0
.stabs "double:t13=r1;8;0;",128,0,0,0
.stabs "long double:t14=r1;8;0;",128,0,0,0
.stabs "void:t15=15",128,0,0,0
.stabs "msg:G16=ar1;0;13;2",32,0,0,0
.global msg
.section ".rodata"
.align 8
.type msg,#object
.size msg,14
msg:
.asciz "hello, world!"
.align 8
.LLC0:
.asciz "%s\n"
.section ".text"
.align 4
.stabs "main:F1",36,0,0,main
.stabs "argc:P1",64,0,0,24
.stabs "argv:P17=*18=*2",64,0,0,25
.global main
.type main,#function
.proc 04
main:
.stabn 68,0,4,.LM1-main
.LM1:
!#PROLOGUE# 0
save %sp,-112,%sp
!#PROLOGUE# 1
.stabn 68,0,5,.LM2-main
.LM2:
.LLBB2:
sethi %hi(.LLC0),%o0
or %o0,%lo(.LLC0),%o0
sethi %hi(msg),%o1
call printf,0
or %o1,%lo(msg),%o1
.stabn 68,0,6,.LM3-main
.LM3:
.stabn 68,0,7,.LM4-main
.LM4:
.LLBE2:
ret
restore %g0,0,%o0
.LLfe1:
.size main,.LLfe1-main
.stabn 192,0,0,.LLBB2-main
.stabn 224,0,0,.LLBE2-main
.ident "GCC: (GNU) cygnus-2.3.3"
|
stsp/binutils-ia16
| 2,504
|
gas/testsuite/gas/sparc-solaris/sol-cc.s
|
.section ".text" ! [internal]
.proc 4
.global main
.align 4
.global main
main:
!#PROLOGUE# 0
!#PROLOGUE# 1
save %sp,-96,%sp
sethi %hi(.L18),%o0
sethi %hi(msg),%o1
or %o1,%lo(msg),%o1 ! [internal]
call printf,2
or %o0,%lo(.L18),%o0 ! [internal]
ret
restore %g0,0,%o0
.type main,#function
.size main,(.-main)
.section ".data" ! [internal]
.align 4
Ddata.data:
.section ".bss" ! [internal]
Bbss.bss:
.section ".rodata" ! [internal]
Drodata.rodata:
.file "hi-sol.c"
.global msg
.global msg
msg:
.ascii "hello, world!\0"
.type msg,#object
.size msg,14
.section ".data1", #write, #alloc ! [internal]
.align 4
.L18:
.ascii "%s\n\0"
.ident "acomp: (CDS) SPARCompilers 2.0.1 03 Sep 1992"
.section "text" ! [internal]
.stabs "/cygint/s1/users/raeburn/",100,0,0,0
.stabs "hi-sol.c",100,0,3,0
.stabs "",56,0,0,0
.stabs "",56,0,0,0
.stabs "Xt ; g ; O ; V=2.0",60,0,0,0x2bb773ba
.stabs "char:t(0,1)=bsc1;0;8;",128,0,0,0
.stabs "short:t(0,2)=bs2;0;16;",128,0,0,0
.stabs "int:t(0,3)=bs4;0;32;",128,0,0,0
.stabs "long:t(0,4)=bs4;0;32;",128,0,0,0
.stabs "long long:t(0,5)=bs8;0;64;",128,0,0,0
.stabs "signed char:t(0,6)=bsc1;0;8;",128,0,0,0
.stabs "signed short:t(0,7)=bs2;0;16;",128,0,0,0
.stabs "signed int:t(0,8)=bs4;0;32;",128,0,0,0
.stabs "signed long:t(0,9)=bs4;0;32;",128,0,0,0
.stabs "signed long long:t(0,10)=bs8;0;64;",128,0,0,0
.stabs "unsigned char:t(0,11)=buc1;0;8;",128,0,0,0
.stabs "unsigned short:t(0,12)=bu2;0;16;",128,0,0,0
.stabs "unsigned int:t(0,13)=bu4;0;32;",128,0,0,0
.stabs "unsigned long:t(0,14)=bu4;0;32;",128,0,0,0
.stabs "unsigned long long:t(0,15)=bu8;0;64;",128,0,0,0
.stabs "float:t(0,16)=R1;4;",128,0,0,0
.stabs "double:t(0,17)=R2;8;",128,0,0,0
.stabs "long double:t(0,18)=R6;16;",128,0,0,0
.stabs "void:t(0,19)=bs0;0;0",128,0,0,0
.stabs "msg:G(0,20)=ar(0,3);0;13;(0,1)",32,0,14,0
.stabs "main:F(0,3);(0,3);(0,21)=*(0,22)=*(0,1)",36,0,0,main
.stabs "main",42,0,0,0
.stabn 192,0,1,0
.stabn 68,0,4,0
.stabs "argc:p(0,3)",160,0,4,68
.stabs "argv:p(0,21)",160,0,4,72
.stabs "printf:P(0,3)",36,0,0,0
.stabn 224,0,1,0
.stabs "",98,0,0,0
.section "text" ! [internal]
.xstabs ".stab.index","/cygint/s1/users/raeburn/",100,0,0,0
.xstabs ".stab.index","hi-sol.c",100,0,3,0
.xstabs ".stab.index","",56,0,0,0
.xstabs ".stab.index","",56,0,0,0
.xstabs ".stab.index","Xt ; g ; O ; V=2.0",60,0,0,0x2bb773ba
.xstabs ".stab.index","msg",32,0,0,0
.xstabs ".stab.index","main",42,0,0,0
.xstabs ".stab.index","main",36,0,0,0
|
stsp/binutils-ia16
| 20,650
|
gas/testsuite/gas/xstormy16/allinsn.s
|
.data
foodata: .word 42
.text
footext:
.text
.global movlmemimm
movlmemimm:
mov.b 0,#0
mov.w 255,#65535
mov.w 128,#32768
mov.b 127,#32767
mov.w 1,#1
mov.w 81,#64681
mov.w 247,#42230
mov.b 84,#16647
.text
.global movhmemimm
movhmemimm:
mov.b 0x7f00+0,#0
mov.w 0x7f00+255,#65535
mov.w 0x7f00+128,#32768
mov.b 0x7f00+127,#32767
mov.w 0x7f00+1,#1
mov.b 0x7f00+165,#1944
mov.w 0x7f00+186,#11517
mov.b 0x7f00+63,#25556
.text
.global movlgrmem
movlgrmem:
mov.b r0,0
mov.w r7,255
mov.w r4,128
mov.b r3,127
mov.w r1,1
mov.w r6,179
mov.w r0,183
mov.b r3,41
.text
.global movhgrmem
movhgrmem:
mov.b r0,0x7f00+0
mov.w r7,0x7f00+255
mov.w r4,0x7f00+128
mov.b r3,0x7f00+127
mov.w r1,0x7f00+1
mov.b r2,0x7f00+114
mov.w r2,0x7f00+210
mov.w r5,0x7f00+181
.text
.global movlmemgr
movlmemgr:
mov.b 0,r0
mov.w 255,r7
mov.w 128,r4
mov.b 127,r3
mov.w 1,r1
mov.w 137,r0
mov.w 26,r0
mov.b 127,r4
.text
.global movhmemgr
movhmemgr:
mov.b 0x7f00+0,r0
mov.w 0x7f00+255,r7
mov.w 0x7f00+128,r4
mov.b 0x7f00+127,r3
mov.w 0x7f00+1,r1
mov.w 0x7f00+98,r3
mov.w 0x7f00+135,r7
mov.b 0x7f00+229,r2
.text
.global movgrgri
movgrgri:
mov.b r0,(r0)
mov.w r7,(r15)
mov.w r4,(r8)
mov.b r3,(r7)
mov.w r1,(r1)
mov.w r6,(r4)
mov.b r0,(r12)
mov.w r5,(r9)
.text
.global movgrgripostinc
movgrgripostinc:
mov.b r0,(r0++)
mov.w r7,(r15++)
mov.w r4,(r8++)
mov.b r3,(r7++)
mov.w r1,(r1++)
mov.w r4,(r8++)
mov.w r3,(r12++)
mov.b r6,(r4++)
.text
.global movgrgripredec
movgrgripredec:
mov.b r0,(--r0)
mov.w r7,(--r15)
mov.w r4,(--r8)
mov.b r3,(--r7)
mov.w r1,(--r1)
mov.w r5,(--r9)
mov.w r4,(--r14)
mov.b r4,(--r7)
.text
.global movgrigr
movgrigr:
mov.b (r0),r0
mov.w (r15),r7
mov.w (r8),r4
mov.b (r7),r3
mov.w (r1),r1
mov.w (r4),r3
mov.b (r3),r6
mov.w (r7),r0
.text
.global movgripostincgr
movgripostincgr:
mov.b (r0++),r0
mov.w (r15++),r7
mov.w (r8++),r4
mov.b (r7++),r3
mov.w (r1++),r1
mov.w (r12++),r5
mov.b (r4++),r2
mov.b (r11++),r6
.text
.global movgripredecgr
movgripredecgr:
mov.b (--r0),r0
mov.w (--r15),r7
mov.w (--r8),r4
mov.b (--r7),r3
mov.w (--r1),r1
mov.b (--r8),r3
mov.b (--r11),r4
mov.w (--r1),r6
.text
.global movgrgrii
movgrgrii:
mov.b r0,(r0,0)
mov.w r7,(r15,-1)
mov.w r4,(r8,-2048)
mov.b r3,(r7,2047)
mov.w r1,(r1,1)
mov.w r6,(r8,-452)
mov.w r4,(r11,572)
mov.b r1,(r1,-1718)
.text
.global movgrgriipostinc
movgrgriipostinc:
mov.b r0,(r0++,0)
mov.w r7,(r15++,-1)
mov.w r4,(r8++,-2048)
mov.b r3,(r7++,2047)
mov.w r1,(r1++,1)
mov.w r6,(r0++,-64)
mov.b r7,(r15++,1060)
mov.b r0,(r7++,847)
.text
.global movgrgriipredec
movgrgriipredec:
mov.b r0,(--r0,0)
mov.w r7,(--r15,-1)
mov.w r4,(--r8,-2048)
mov.b r3,(--r7,2047)
mov.w r1,(--r1,1)
mov.w r0,(--r15,1780)
mov.w r6,(--r1,1506)
mov.w r7,(--r3,-2033)
.text
.global movgriigr
movgriigr:
mov.b (r0,0),r0
mov.w (r15,-1),r7
mov.w (r8,-2048),r4
mov.b (r7,2047),r3
mov.w (r1,1),r1
mov.w (r7,1948),r5
mov.b (r3,-844),r4
mov.w (r15,1704),r0
.text
.global movgriipostincgr
movgriipostincgr:
mov.b (r0++,0),r0
mov.w (r15++,-1),r7
mov.w (r8++,-2048),r4
mov.b (r7++,2047),r3
mov.w (r1++,1),r1
mov.w (r2++,-176),r7
mov.w (r8++,1389),r4
mov.b (r3++,47),r0
.text
.global movgriipredecgr
movgriipredecgr:
mov.b (--r0,0),r0
mov.w (--r15,-1),r7
mov.w (--r8,-2048),r4
mov.b (--r7,2047),r3
mov.w (--r1,1),r1
mov.b (--r8,1004),r4
mov.w (--r14,-1444),r2
mov.b (--r5,-927),r4
.text
.global movgrgr
movgrgr:
mov r0,r0
mov r15,r15
mov r8,r8
mov r7,r7
mov r1,r1
mov r9,r14
mov r7,r15
mov r12,r15
.text
.global movimm8
movimm8:
mov Rx,#0
mov Rx,#255
mov Rx,#128
mov Rx,#127
mov Rx,#1
mov Rx,#136
mov Rx,#83
mov Rx,#104
.text
.global movwimm8
movwimm8:
mov.w Rx,#0
mov.w Rx,#255
mov.w Rx,#128
mov.w Rx,#127
mov.w Rx,#1
mov.w Rx,#92
mov.w Rx,#97
mov.w Rx,#4
.text
.global movgrimm8
movgrimm8:
mov r0,#0
mov r7,#255
mov r4,#128
mov r3,#127
mov r1,#1
mov r2,#206
mov r4,#55
mov r2,#3
.text
.global movwgrimm8
movwgrimm8:
mov.w r0,#0
mov.w r7,#255
mov.w r4,#128
mov.w r3,#127
mov.w r1,#1
mov.w r4,#243
mov.w r3,#55
mov.w r2,#108
.text
.global movgrimm16
movgrimm16:
mov r0,#0
mov r15,#65535
mov r8,#32768
mov r7,#32767
mov r1,#1
mov r4,#20066
mov r3,#7190
mov r2,#15972
.text
.global movwgrimm16
movwgrimm16:
mov.w r0,#0
mov.w r15,#65535
mov.w r8,#32768
mov.w r7,#32767
mov.w r1,#1
mov.w r6,#16648
mov.w r8,#26865
mov.w r10,#20010
.text
.global movlowgr
movlowgr:
mov.b r0,RxL
mov.b r15,RxL
mov.b r8,RxL
mov.b r7,RxL
mov.b r1,RxL
mov.b r11,RxL
mov.b r5,RxL
mov.b r2,RxL
.text
.global movhighgr
movhighgr:
mov.b r0,RxH
mov.b r15,RxH
mov.b r8,RxH
mov.b r7,RxH
mov.b r1,RxH
mov.b r2,RxH
mov.b r7,RxH
mov.b r2,RxH
.text
.global movfgrgri
movfgrgri:
movf.b r0,(r0)
movf.w r7,(r15)
movf.w r4,(r8)
movf.b r3,(r7)
movf.w r1,(r1)
movf.b r6,(r15)
movf.b r1,(r10)
movf.b r6,(r1)
.text
.global movfgrgripostinc
movfgrgripostinc:
movf.b r0,(r0++)
movf.w r7,(r15++)
movf.w r4,(r8++)
movf.b r3,(r7++)
movf.w r1,(r1++)
movf.b r2,(r5++)
movf.w r5,(r10++)
movf.w r7,(r5++)
.text
.global movfgrgripredec
movfgrgripredec:
movf.b r0,(--r0)
movf.w r7,(--r15)
movf.w r4,(--r8)
movf.b r3,(--r7)
movf.w r1,(--r1)
movf.w r6,(--r10)
movf.b r1,(--r14)
movf.w r3,(--r7)
.text
.global movfgrigr
movfgrigr:
movf.b (r0),r0
movf.w (r15),r7
movf.w (r8),r4
movf.b (r7),r3
movf.w (r1),r1
movf.b (r5),r4
movf.b (r3),r4
movf.w (r12),r3
.text
.global movfgripostincgr
movfgripostincgr:
movf.b (r0++),r0
movf.w (r15++),r7
movf.w (r8++),r4
movf.b (r7++),r3
movf.w (r1++),r1
movf.b (r9++),r5
movf.w (r10++),r4
movf.b (r9++),r1
.text
.global movfgripredecgr
movfgripredecgr:
movf.b (--r0),r0
movf.w (--r15),r7
movf.w (--r8),r4
movf.b (--r7),r3
movf.w (--r1),r1
movf.b (--r0),r2
movf.w (--r11),r2
movf.b (--r10),r5
.text
.global movfgrgrii
movfgrgrii:
movf.b r0,(r8,r0,0)
movf.w r7,(r15,r15,-1)
movf.w r4,(r12,r8,-2048)
movf.b r3,(r11,r7,2047)
movf.w r1,(r9,r1,1)
movf.b r7,(r15,r0,1473)
movf.w r2,(r8,r9,-1522)
movf.w r2,(r13,r1,480)
.text
.global movfgrgriipostinc
movfgrgriipostinc:
movf.b r0,(r8,r0++,0)
movf.w r7,(r15,r15++,-1)
movf.w r4,(r12,r8++,-2048)
movf.b r3,(r11,r7++,2047)
movf.w r1,(r9,r1++,1)
movf.b r1,(r8,r2++,1398)
movf.w r4,(r8,r9++,-778)
movf.w r1,(r13,r14++,1564)
.text
.global movfgrgriipredec
movfgrgriipredec:
movf.b r0,(r8,--r0,0)
movf.w r7,(r15,--r15,-1)
movf.w r4,(r12,--r8,-2048)
movf.b r3,(r11,--r7,2047)
movf.w r1,(r9,--r1,1)
movf.b r6,(r8,--r7,254)
movf.w r5,(r12,--r12,1673)
movf.b r0,(r8,--r10,-38)
.text
.global movfgriigr
movfgriigr:
movf.b (r8,r0,0),r0
movf.w (r15,r15,-1),r7
movf.w (r12,r8,-2048),r4
movf.b (r11,r7,2047),r3
movf.w (r9,r1,1),r1
movf.w (r15,r2,-1636),r3
movf.w (r14,r12,1626),r1
movf.b (r11,r14,1540),r0
.text
.global movfgriipostincgr
movfgriipostincgr:
movf.b (r8,r0++,0),r0
movf.w (r15,r15++,-1),r7
movf.w (r12,r8++,-2048),r4
movf.b (r11,r7++,2047),r3
movf.w (r9,r1++,1),r1
movf.b (r15,r13++,466),r3
movf.b (r11,r11++,250),r4
movf.b (r10,r10++,-1480),r7
.text
.global movfgriipredecgr
movfgriipredecgr:
movf.b (r8,--r0,0),r0
movf.w (r15,--r15,-1),r7
movf.w (r12,--r8,-2048),r4
movf.b (r11,--r7,2047),r3
movf.w (r9,--r1,1),r1
movf.b (r13,--r10,-608),r0
movf.b (r9,--r11,831),r7
movf.w (r15,--r15,-2036),r6
.text
.global maskgrgr
maskgrgr:
mask r0,r0
mask r15,r15
mask r8,r8
mask r7,r7
mask r1,r1
mask r4,r0
mask r6,r11
mask r8,r4
.text
.global maskgrimm16
maskgrimm16:
mask r0,#0
mask r15,#65535
mask r8,#32768
mask r7,#32767
mask r1,#1
mask r7,#18153
mask r15,#7524
mask r14,#34349
.text
.global pushgr
pushgr:
push r0
push r15
push r8
push r7
push r1
push r9
push r4
push r3
.text
.global popgr
popgr:
pop r0
pop r15
pop r8
pop r7
pop r1
pop r3
pop r2
pop r12
.text
.global swpn
swpn:
swpn r0
swpn r15
swpn r8
swpn r7
swpn r1
swpn r15
swpn r4
swpn r3
.text
.global swpb
swpb:
swpb r0
swpb r15
swpb r8
swpb r7
swpb r1
swpb r2
swpb r12
swpb r2
.text
.global swpw
swpw:
swpw r0,r0
swpw r15,r15
swpw r8,r8
swpw r7,r7
swpw r1,r1
swpw r12,r4
swpw r8,r2
swpw r5,r13
.text
.global andgrgr
andgrgr:
and r0,r0
and r15,r15
and r8,r8
and r7,r7
and r1,r1
and r2,r2
and r15,r5
and r7,r5
.text
.global andimm8
andimm8:
and Rx,#0
and Rx,#255
and Rx,#128
and Rx,#127
and Rx,#1
and Rx,#206
and Rx,#11
and Rx,#232
.text
.global andgrimm16
andgrimm16:
and r0,#0
and r15,#65535
and r8,#32768
and r7,#32767
and r1,#1
and r10,#17229
and r11,#61451
and r5,#46925
.text
.global orgrgr
orgrgr:
or r0,r0
or r15,r15
or r8,r8
or r7,r7
or r1,r1
or r3,r5
or r14,r15
or r5,r12
.text
.global orimm8
orimm8:
or Rx,#0
or Rx,#255
or Rx,#128
or Rx,#127
or Rx,#1
or Rx,#4
or Rx,#38
or Rx,#52
.text
.global orgrimm16
orgrimm16:
or r0,#0
or r15,#65535
or r8,#32768
or r7,#32767
or r1,#1
or r2,#64563
or r2,#18395
or r1,#63059
.text
.global xorgrgr
xorgrgr:
xor r0,r0
xor r15,r15
xor r8,r8
xor r7,r7
xor r1,r1
xor r14,r1
xor r9,r9
xor r12,r8
.text
.global xorimm8
xorimm8:
xor Rx,#0
xor Rx,#255
xor Rx,#128
xor Rx,#127
xor Rx,#1
xor Rx,#208
xor Rx,#126
xor Rx,#55
.text
.global xorgrimm16
xorgrimm16:
xor r0,#0
xor r15,#65535
xor r8,#32768
xor r7,#32767
xor r1,#1
xor r15,#56437
xor r3,#901
xor r2,#37017
.text
.global notgr
notgr:
not r0
not r15
not r8
not r7
not r1
not r4
not r3
not r3
.text
.global addgrgr
addgrgr:
add r0,r0
add r15,r15
add r8,r8
add r7,r7
add r1,r1
add r12,r7
add r1,r10
add r14,r14
.text
.global addgrimm4
addgrimm4:
add r0,#0
add r15,#15
add r8,#8
add r7,#7
add r1,#1
add r7,#0
add r10,#9
add r7,#8
.text
.global addimm8
addimm8:
add Rx,#0
add Rx,#255
add Rx,#128
add Rx,#127
add Rx,#1
add Rx,#25
add Rx,#247
add Rx,#221
.text
.global addgrimm16
addgrimm16:
add r0,#0
add r15,#255
add r8,#128
add r7,#127
add r1,#1
add r3,#99
add r0,#15
add r7,#214
.text
.global adcgrgr
adcgrgr:
adc r0,r0
adc r15,r15
adc r8,r8
adc r7,r7
adc r1,r1
adc r2,r13
adc r14,r10
adc r2,r15
.text
.global adcgrimm4
adcgrimm4:
adc r0,#0
adc r15,#15
adc r8,#8
adc r7,#7
adc r1,#1
adc r15,#1
adc r1,#3
adc r6,#11
.text
.global adcimm8
adcimm8:
adc Rx,#0
adc Rx,#255
adc Rx,#128
adc Rx,#127
adc Rx,#1
adc Rx,#225
adc Rx,#75
adc Rx,#18
.text
.global adcgrimm16
adcgrimm16:
adc r0,#0
adc r15,#65535
adc r8,#32768
adc r7,#32767
adc r1,#1
adc r13,#63129
adc r3,#23795
adc r11,#49245
.text
.global subgrgr
subgrgr:
sub r0,r0
sub r15,r15
sub r8,r8
sub r7,r7
sub r1,r1
sub r8,r8
sub r9,r9
sub r9,r15
.text
.global subgrimm4
subgrimm4:
sub r0,#0
sub r15,#15
sub r8,#8
sub r7,#7
sub r1,#1
sub r2,#15
sub r12,#9
sub r8,#4
.text
.global subimm8
subimm8:
sub Rx,#0
sub Rx,#255
sub Rx,#128
sub Rx,#127
sub Rx,#1
sub Rx,#205
sub Rx,#153
sub Rx,#217
.text
.global subgrimm16
subgrimm16:
sub r0,#0
sub r15,#65535
sub r8,#32768
sub r7,#32767
sub r1,#1
sub r3,#51895
sub r11,#23617
sub r10,#7754
.text
.global sbcgrgr
sbcgrgr:
sbc r0,r0
sbc r15,r15
sbc r8,r8
sbc r7,r7
sbc r1,r1
sbc r11,r2
sbc r9,r1
sbc r4,r15
.text
.global sbcgrimm4
sbcgrimm4:
sbc r0,#0
sbc r15,#15
sbc r8,#8
sbc r7,#7
sbc r1,#1
sbc r10,#11
sbc r11,#10
sbc r13,#10
.text
.global sbcgrimm8
sbcgrimm8:
sbc Rx,#0
sbc Rx,#255
sbc Rx,#128
sbc Rx,#127
sbc Rx,#1
sbc Rx,#137
sbc Rx,#224
sbc Rx,#156
.text
.global sbcgrimm16
sbcgrimm16:
sbc r0,#0
sbc r15,#65535
sbc r8,#32768
sbc r7,#32767
sbc r1,#1
sbc r0,#32507
sbc r7,#8610
sbc r14,#20373
.text
.global incgr
incgr:
inc r0
inc r15
inc r8
inc r7
inc r1
inc r13
inc r1
inc r11
.text
.global incgrimm2
incgrimm2:
inc r0,#0
inc r15,#3
inc r8,#2
inc r7,#1
inc r1,#1
inc r14,#1
inc r5,#0
inc r12,#3
.text
.global decgr
decgr:
dec r0
dec r15
dec r8
dec r7
dec r1
dec r12
dec r8
dec r10
.text
.global decgrimm2
decgrimm2:
dec r0,#0
dec r15,#3
dec r8,#2
dec r7,#1
dec r1,#1
dec r5,#0
dec r13,#0
dec r13,#2
.text
.global rrcgrgr
rrcgrgr:
rrc r0,r0
rrc r15,r15
rrc r8,r8
rrc r7,r7
rrc r1,r1
rrc r8,r4
rrc r10,r14
rrc r15,r9
.text
.global rrcgrimm4
rrcgrimm4:
rrc r0,#0
rrc r15,#15
rrc r8,#8
rrc r7,#7
rrc r1,#1
rrc r11,#3
rrc r14,#12
rrc r2,#15
.text
.global rlcgrgr
rlcgrgr:
rlc r0,r0
rlc r15,r15
rlc r8,r8
rlc r7,r7
rlc r1,r1
rlc r15,r3
rlc r15,r7
rlc r15,r10
.text
.global rlcgrimm4
rlcgrimm4:
rlc r0,#0
rlc r15,#15
rlc r8,#8
rlc r7,#7
rlc r1,#1
rlc r8,#2
rlc r2,#6
rlc r6,#10
.text
.global shrgrgr
shrgrgr:
shr r0,r0
shr r15,r15
shr r8,r8
shr r7,r7
shr r1,r1
shr r13,r2
shr r7,r8
shr r6,r8
.text
.global shrgrimm
shrgrimm:
shr r0,#0
shr r15,#15
shr r8,#8
shr r7,#7
shr r1,#1
shr r9,#13
shr r2,#7
shr r8,#8
.text
.global shlgrgr
shlgrgr:
shl r0,r0
shl r15,r15
shl r8,r8
shl r7,r7
shl r1,r1
shl r2,r3
shl r0,r3
shl r2,r1
.text
.global shlgrimm
shlgrimm:
shl r0,#0
shl r15,#15
shl r8,#8
shl r7,#7
shl r1,#1
shl r6,#13
shl r3,#6
shl r15,#15
.text
.global asrgrgr
asrgrgr:
asr r0,r0
asr r15,r15
asr r8,r8
asr r7,r7
asr r1,r1
asr r5,r10
asr r3,r5
asr r6,r11
.text
.global asrgrimm
asrgrimm:
asr r0,#0
asr r15,#15
asr r8,#8
asr r7,#7
asr r1,#1
asr r13,#4
asr r0,#13
asr r6,#3
.text
.global set1grimm
set1grimm:
set1 r0,#0
set1 r15,#15
set1 r8,#8
set1 r7,#7
set1 r1,#1
set1 r6,#10
set1 r13,#1
set1 r13,#15
.text
.global set1grgr
set1grgr:
set1 r0,r0
set1 r15,r15
set1 r8,r8
set1 r7,r7
set1 r1,r1
set1 r6,r0
set1 r6,r7
set1 r14,r2
.text
.global set1lmemimm
set1lmemimm:
set1 0,#0
set1 255,#7
set1 128,#4
set1 127,#3
set1 1,#1
set1 244,#3
set1 55,#7
set1 252,#5
.text
.global set1hmemimm
set1hmemimm:
set1 0x7f00+0,#0
set1 0x7f00+255,#7
set1 0x7f00+128,#4
set1 0x7f00+127,#3
set1 0x7f00+1,#1
set1 0x7f00+10,#3
set1 0x7f00+99,#4
set1 0x7f00+148,#3
.text
.global clr1grimm
clr1grimm:
clr1 r0,#0
clr1 r15,#15
clr1 r8,#8
clr1 r7,#7
clr1 r1,#1
clr1 r12,#0
clr1 r8,#11
clr1 r7,#7
.text
.global clr1grgr
clr1grgr:
clr1 r0,r0
clr1 r15,r15
clr1 r8,r8
clr1 r7,r7
clr1 r1,r1
clr1 r3,r3
clr1 r0,r1
clr1 r15,r0
.text
.global clr1lmemimm
clr1lmemimm:
clr1 0,#0
clr1 255,#7
clr1 128,#4
clr1 127,#3
clr1 1,#1
clr1 114,#7
clr1 229,#4
clr1 86,#1
.text
.global clr1hmemimm
clr1hmemimm:
clr1 0x7f00+0,#0
clr1 0x7f00+255,#7
clr1 0x7f00+128,#4
clr1 0x7f00+127,#3
clr1 0x7f00+1,#1
clr1 0x7f00+44,#3
clr1 0x7f00+212,#5
clr1 0x7f00+67,#7
.text
.global cbwgr
cbwgr:
cbw r0
cbw r15
cbw r8
cbw r7
cbw r1
cbw r8
cbw r11
cbw r3
.text
.global revgr
revgr:
rev r0
rev r15
rev r8
rev r7
rev r1
rev r1
rev r1
rev r14
.text
.global bgr
bgr:
br r0
br r15
br r8
br r7
br r1
br r0
br r15
br r12
.text
.global jmp
jmp:
jmp r8,r0
jmp r9,r15
jmp r9,r8
jmp r8,r7
jmp r9,r1
jmp r9,r7
jmp r9,r5
jmp r8,r12
.text
.global jmpf
jmpf:
jmpf 0
jmpf 16777215
jmpf 8388608
jmpf 8388607
jmpf 1
jmpf 10731629
jmpf 15094866
jmpf 1464024
.text
.global callrgr
callrgr:
callr r0
callr r15
callr r8
callr r7
callr r1
callr r1
callr r12
callr r8
.text
.global callgr
callgr:
call r8,r0
call r9,r15
call r9,r8
call r8,r7
call r9,r1
call r9,r6
call r9,r14
call r8,r12
.text
.global callfimm
callfimm:
callf 0
callf 16777215
callf 8388608
callf 8388607
callf 1
callf 13546070
callf 10837983
callf 15197875
.text
.global icallrgr
icallrgr:
icallr r0
icallr r15
icallr r8
icallr r7
icallr r1
icallr r15
icallr r12
icallr r9
.text
.global icallgr
icallgr:
icall r8,r0
icall r9,r15
icall r9,r8
icall r8,r7
icall r9,r1
icall r9,r10
icall r8,r15
icall r8,r10
.text
.global icallfimm
icallfimm:
icallf 0
icallf 16777215
icallf 8388608
icallf 8388607
icallf 1
icallf 9649954
icallf 1979758
icallf 7661640
.text
.global iret
iret:
iret
.text
.global ret
ret:
ret
.text
.global mul
mul:
mul
.text
.global div
div:
div
.text
.global sdiv
sdiv:
sdiv
.text
.global divlh
divlh:
divlh
.text
.global sdivlh
sdivlh:
sdivlh
.text
.global nop
nop:
nop
ret
.text
.global halt
halt:
halt
.text
.global hold
hold:
hold
.text
.global holdx
holdx:
holdx
.text
.global brk
brk:
brk
.text
.global bccgrgr
bccgrgr:
bge r0,r0,0+(.+4)
bz r15,r15,-1+(.+4)
bpl r8,r8,-2048+(.+4)
bls r7,r7,2047+(.+4)
bnc r1,r1,1+(.+4)
bc r3,r13,1799+(.+4)
bge r1,r10,-2019+(.+4)
bz r0,r5,-1132+(.+4)
.text
.global bccgrimm8
bccgrimm8:
bge r0,#0,0+(.+4)
bz r7,#255,-1+(.+4)
bpl r4,#128,-2048+(.+4)
bls r3,#127,2047+(.+4)
bnc r1,#1,1+(.+4)
bnc r3,#8,1473+(.+4)
bnz.b r5,#203,1619+(.+4)
bc r7,#225,978+(.+4)
.text
.global bccimm16
bccimm16:
bge Rx,#0,0+(.+4)
bz Rx,#65535,-1+(.+4)
bpl Rx,#32768,-128+(.+4)
bls Rx,#32767,127+(.+4)
bnc Rx,#1,1+(.+4)
bz.b Rx,#30715,4+(.+4)
bnv Rx,#62266,-13+(.+4)
bnv Rx,#48178,108+(.+4)
.text
.global bngrimm4
bngrimm4:
bn r0,#0,0+(.+4)
bn r15,#15,-1+(.+4)
bn r8,#8,-2048+(.+4)
bn r7,#7,2047+(.+4)
bn r1,#1,1+(.+4)
bn r11,#3,-1975+(.+4)
bn r15,#4,-1205+(.+4)
bn r10,#8,1691+(.+4)
.text
.global bngrgr
bngrgr:
bn r0,r0,0+(.+4)
bn r15,r15,-1+(.+4)
bn r8,r8,-2048+(.+4)
bn r7,r7,2047+(.+4)
bn r1,r1,1+(.+4)
bn r4,r3,1181+(.+4)
bn r5,r2,77+(.+4)
bn r3,r7,631+(.+4)
.text
.global bnlmemimm
bnlmemimm:
bn 0,#0,0+(.+4)
bn 255,#7,-1+(.+4)
bn 128,#4,-2048+(.+4)
bn 127,#3,2047+(.+4)
bn 1,#1,1+(.+4)
bn 153,#7,-847+(.+4)
bn 204,#0,-1881+(.+4)
bn 242,#7,1396+(.+4)
.text
.global bnhmemimm
bnhmemimm:
bn 0x7f00+0,#0,0+(.+4)
bn 0x7f00+255,#7,-1+(.+4)
bn 0x7f00+128,#4,-2048+(.+4)
bn 0x7f00+127,#3,2047+(.+4)
bn 0x7f00+1,#1,1+(.+4)
bn 0x7f00+185,#3,-614+(.+4)
bn 0x7f00+105,#1,-668+(.+4)
bn 0x7f00+79,#7,1312+(.+4)
.text
.global bpgrimm4
bpgrimm4:
bp r0,#0,0+(.+4)
bp r15,#15,-1+(.+4)
bp r8,#8,-2048+(.+4)
bp r7,#7,2047+(.+4)
bp r1,#1,1+(.+4)
bp r0,#12,1075+(.+4)
bp r1,#5,551+(.+4)
bp r6,#8,1588+(.+4)
.text
.global bpgrgr
bpgrgr:
bp r0,r0,0+(.+4)
bp r15,r15,-1+(.+4)
bp r8,r8,-2048+(.+4)
bp r7,r7,2047+(.+4)
bp r1,r1,1+(.+4)
bp r4,r9,-614+(.+4)
bp r9,r10,-1360+(.+4)
bp r4,r1,407+(.+4)
.text
.global bplmemimm
bplmemimm:
bp 0,#0,0+(.+4)
bp 255,#7,-1+(.+4)
bp 128,#4,-2048+(.+4)
bp 127,#3,2047+(.+4)
bp 1,#1,1+(.+4)
bp 193,#3,-398+(.+4)
bp 250,#2,-1553+(.+4)
bp 180,#6,579+(.+4)
.text
.global bphmemimm
bphmemimm:
bp 0x7f00+0,#0,0+(.+4)
bp 0x7f00+255,#7,-1+(.+4)
bp 0x7f00+128,#4,-2048+(.+4)
bp 0x7f00+127,#3,2047+(.+4)
bp 0x7f00+1,#1,1+(.+4)
bp 0x7f00+195,#1,-432+(.+4)
bp 0x7f00+129,#5,-1508+(.+4)
bp 0x7f00+56,#3,1723+(.+4)
.text
.global bcc
bcc:
bge 0+(.+2)
bz -1+(.+2)
bpl -128+(.+2)
bls 127+(.+2)
bnc 1+(.+2)
bnz.b 48+(.+2)
bnc -7+(.+2)
bnz.b 74+(.+2)
.text
.global br
br:
br 0+(.+2)
br -2+(.+2)
br -2048+(.+2)
br 2046+(.+2)
br 1+(.+2)
br 1472+(.+2)
br 1618+(.+2)
br 978+(.+2)
.text
.global callrimm
callrimm:
callr 0+(.+2)
callr -2+(.+2)
callr -2048+(.+2)
callr 2046+(.+2)
callr 1+(.+2)
callr 1472+(.+2)
callr 1618+(.+2)
callr 978+(.+2)
movgrgrsi:
mov.b r0,(r0,extsym)
mov.w r7,(r15,extsym-1)
mov.w r4,(r8,extsym-2048)
mov.b r3,(r7,extsym+2047)
mov.w r1,(r1,extsym+1)
mov.w r6,(r8,extsym-452)
mov.w r4,(r11,extsym+572)
mov.b r1,(r1,extsym-1718)
.text
.global movgrgriipostinc
movgrgrsipostinc:
mov.b r0,(r0++,extsym)
mov.w r7,(r15++,extsym-1)
mov.w r4,(r8++,extsym-2048)
mov.b r3,(r7++,extsym+2047)
mov.w r1,(r1++,extsym+1)
mov.w r6,(r0++,extsym-64)
mov.b r7,(r15++,extsym+1060)
mov.b r0,(r7++,extsym+847)
.text
.global movgrgriipredec
movgrgrsipredec:
mov.b r0,(--r0,extsym)
mov.w r7,(--r15,extsym-1)
mov.w r4,(--r8,extsym-2048)
mov.b r3,(--r7,extsym+2047)
mov.w r1,(--r1,extsym+1)
mov.w r0,(--r15,extsym+1780)
mov.w r6,(--r1,extsym+1506)
mov.w r7,(--r3,extsym-2033)
.text
.global movgriigr
movgrsigr:
mov.b (r0,extsym),r0
mov.w (r15,extsym-1),r7
mov.w (r8,extsym-2048),r4
mov.b (r7,extsym+2047),r3
mov.w (r1,extsym+1),r1
mov.w (r7,extsym+1948),r5
mov.b (r3,extsym-844),r4
mov.w (r15,extsym+1704),r0
.text
.global movgriipostincgr
movgrsipostincgr:
mov.b (r0++,extsym),r0
mov.w (r15++,extsym-1),r7
mov.w (r8++,extsym-2048),r4
mov.b (r7++,extsym+2047),r3
mov.w (r1++,extsym+1),r1
mov.w (r2++,extsym-176),r7
mov.w (r8++,extsym+1389),r4
mov.b (r3++,extsym+47),r0
.text
.global movgriipredecgr
movgrsipredecgr:
mov.b (--r0,extsym),r0
mov.w (--r15,extsym-1),r7
mov.w (--r8,extsym-2048),r4
mov.b (--r7,extsym+2047),r3
mov.w (--r1,extsym+1),r1
mov.b (--r8,extsym+1004),r4
mov.w (--r14,extsym-1444),r2
mov.b (--r5,extsym-927),r4
|
stsp/binutils-ia16
| 21,767
|
gas/testsuite/gas/mep/allinsn.s
|
.data
foodata: .word 42
.text
footext:
.text
.global sb
sb:
sb $7,($fp)
sb $5,($9)
sb $7,($14)
sb $14,($fp)
sb $15,($14)
.text
.global sh
sh:
sh $3,($fp)
sh $12,($1)
sh $13,($2)
sh $2,($8)
sh $12,($10)
.text
.global sw
sw:
sw $11,($0)
sw $3,($7)
sw $13,($14)
sw $8,($9)
sw $gp,($fp)
.text
.global lb
lb:
lb $12,($11)
lb $9,($2)
lb $fp,($11)
lb $gp,($2)
lb $2,($12)
.text
.global lh
lh:
lh $15,($8)
lh $3,($10)
lh $9,($sp)
lh $6,($sp)
lh $15,($11)
.text
.global lw
lw:
lw $12,($10)
lw $9,($13)
lw $12,($gp)
lw $12,($11)
lw $13,($10)
.text
.global lbu
lbu:
lbu $14,($14)
lbu $12,($fp)
lbu $gp,($1)
lbu $fp,($12)
lbu $12,($1)
.text
.global lhu
lhu:
lhu $15,($4)
lhu $14,($4)
lhu $5,($4)
lhu $sp,($tp)
lhu $4,($15)
.text
.global sw_sp
sw_sp:
sw $9,3($8)
sw $10,4($5)
sw $0,3($gp)
sw $0,2($8)
sw $15,1($8)
.text
.global lw_sp
lw_sp:
lw $tp,1($5)
lw $15,1($0)
lw $0,4($12)
lw $11,1($tp)
lw $9,3($4)
.text
.global sb_tp
sb_tp:
sb $5,1($1)
sb $10,1($9)
sb $5,3($3)
sb $5,1($3)
sb $10,4($4)
.text
.global sh_tp
sh_tp:
sh $3,1($0)
sh $tp,1($9)
sh $9,4($10)
sh $15,3($14)
sh $14,4($9)
.text
.global sw_tp
sw_tp:
sw $6,2($13)
sw $6,1($15)
sw $2,2($3)
sw $6,2($12)
sw $3,1($11)
.text
.global lb_tp
lb_tp:
lb $tp,4($11)
lb $13,4($8)
lb $5,4($5)
lb $sp,2($gp)
lb $3,2($3)
.text
.global lh_tp
lh_tp:
lh $7,2($fp)
lh $4,3($8)
lh $14,1($sp)
lh $9,1($0)
lh $13,2($0)
.text
.global lw_tp
lw_tp:
lw $8,4($15)
lw $11,4($9)
lw $gp,1($2)
lw $9,2($14)
lw $8,1($12)
.text
.global lbu_tp
lbu_tp:
lbu $12,1($9)
lbu $11,1($9)
lbu $14,3($8)
lbu $0,2($sp)
lbu $13,1($11)
.text
.global lhu_tp
lhu_tp:
lhu $14,2($10)
lhu $11,1($8)
lhu $1,1($0)
lhu $7,2($15)
lhu $3,2($tp)
.text
.global sb16
sb16:
sb $7,-1($11)
sb $tp,1($gp)
sb $3,1($gp)
sb $14,2($6)
sb $14,1($7)
.text
.global sh16
sh16:
sh $12,-1($4)
sh $sp,1($1)
sh $2,-2($12)
sh $9,2($11)
sh $9,-2($12)
.text
.global sw16
sw16:
sw $11,-1($gp)
sw $4,4($15)
sw $2,-2($3)
sw $6,-1($2)
sw $fp,-2($tp)
.text
.global lb16
lb16:
lb $10,-2($2)
lb $3,-2($11)
lb $12,1($5)
lb $5,1($5)
lb $11,2($13)
.text
.global lh16
lh16:
lh $sp,-1($11)
lh $tp,-2($11)
lh $2,1($10)
lh $8,-1($7)
lh $14,-1($11)
.text
.global lw16
lw16:
lw $0,-1($5)
lw $12,-2($7)
lw $1,-2($3)
lw $1,2($7)
lw $4,1($fp)
.text
.global lbu16
lbu16:
lbu $12,-1($4)
lbu $14,1($11)
lbu $1,-1($13)
lbu $9,-1($tp)
lbu $8,1($15)
.text
.global lhu16
lhu16:
lhu $tp,-1($15)
lhu $gp,2($fp)
lhu $15,-1($12)
lhu $3,-1($0)
lhu $3,-2($12)
.text
.global sw24
sw24:
sw $11,(4)
sw $sp,(4)
sw $7,(8)
sw $10,(16)
sw $8,(160)
.text
.global lw24
lw24:
lw $4,(4)
lw $sp,(4)
lw $4,(16)
lw $fp,(0)
lw $tp,(8)
.text
.global extb
extb:
extb $13
extb $tp
extb $6
extb $14
extb $10
.text
.global exth
exth:
exth $15
exth $2
exth $5
exth $10
exth $4
.text
.global extub
extub:
extub $2
extub $tp
extub $3
extub $9
extub $gp
.text
.global extuh
extuh:
extuh $8
extuh $8
extuh $4
extuh $0
extuh $0
.text
.global ssarb
ssarb:
ssarb 2($fp)
ssarb 2($13)
ssarb 1($13)
ssarb 2($5)
ssarb 0($9)
.text
.global mov
mov:
mov $2,$3
mov $3,$11
mov $15,$10
mov $15,$0
mov $3,$tp
.text
.global movi8
movi8:
mov $11,-1
mov $6,2
mov $sp,-1
mov $sp,1
mov $gp,-1
.text
.global movi16
movi16:
mov $15,0
mov $0,2
mov $8,-1
mov $12,1
mov $7,-1
.text
.global movu24
movu24:
movu $2,1
movu $10,4
movu $9,0
movu $4,3
movu $14,1
.text
.global movu16
movu16:
movu $sp,1
movu $6,3
movu $0,3
movu $gp,3
movu $10,2
.text
.global movh
movh:
movh $8,2
movh $13,1
movh $gp,2
movh $12,0
movh $11,2
.text
.global add3
add3:
add3 $6,$11,$3
add3 $14,$13,$5
add3 $3,$11,$7
add3 $13,$14,$13
add3 $0,$14,$8
.text
.global add
add:
add $12,2
add $12,-1
add $4,1
add $6,1
add $6,2
.text
.global add3i
add3i:
add3 $11,$sp,4
add3 $4,$sp,1
add3 $0,$sp,0
add3 $13,$sp,3
add3 $11,$sp,0
.text
.global advck3
advck3:
advck3 $0,$gp,$10
advck3 $0,$tp,$0
advck3 $0,$gp,$13
advck3 $0,$7,$fp
advck3 $0,$1,$2
.text
.global sub
sub:
sub $8,$14
sub $1,$9
sub $13,$7
sub $15,$3
sub $2,$7
.text
.global sbvck3
sbvck3:
sbvck3 $0,$3,$gp
sbvck3 $0,$3,$7
sbvck3 $0,$10,$10
sbvck3 $0,$4,$tp
sbvck3 $0,$10,$15
.text
.global neg
neg:
neg $14,$7
neg $1,$7
neg $2,$11
neg $13,$fp
neg $14,$13
.text
.global slt3
slt3:
slt3 $0,$14,$8
slt3 $0,$4,$13
slt3 $0,$10,$14
slt3 $0,$14,$5
slt3 $0,$3,$12
.text
.global sltu3
sltu3:
sltu3 $0,$2,$8
sltu3 $0,$gp,$11
sltu3 $0,$2,$tp
sltu3 $0,$9,$fp
sltu3 $0,$6,$9
.text
.global slt3i
slt3i:
slt3 $0,$6,2
slt3 $0,$11,1
slt3 $0,$15,0
slt3 $0,$3,0
slt3 $0,$tp,0
.text
.global sltu3i
sltu3i:
sltu3 $0,$14,4
sltu3 $0,$tp,3
sltu3 $0,$3,1
sltu3 $0,$12,0
sltu3 $0,$1,3
.text
.global sl1ad3
sl1ad3:
sl1ad3 $0,$fp,$gp
sl1ad3 $0,$4,$2
sl1ad3 $0,$sp,$12
sl1ad3 $0,$9,$1
sl1ad3 $0,$fp,$2
.text
.global sl2ad3
sl2ad3:
sl2ad3 $0,$8,$13
sl2ad3 $0,$2,$3
sl2ad3 $0,$8,$9
sl2ad3 $0,$7,$12
sl2ad3 $0,$4,$12
.text
.global add3x
add3x:
add3 $tp,$11,1
add3 $tp,$4,-1
add3 $2,$13,1
add3 $3,$gp,1
add3 $10,$15,2
.text
.global slt3x
slt3x:
slt3 $fp,$1,-1
slt3 $0,$3,-2
slt3 $9,$15,-1
slt3 $3,$fp,2
slt3 $tp,$14,0
.text
.global sltu3x
sltu3x:
sltu3 $15,$11,2
sltu3 $6,$0,1
sltu3 $9,$11,3
sltu3 $0,$4,0
sltu3 $13,$gp,4
.text
.global or
or:
or $sp,$gp
or $fp,$3
or $0,$sp
or $tp,$0
or $8,$6
.text
.global and
and:
and $15,$sp
and $6,$14
and $4,$2
and $5,$fp
and $7,$14
.text
.global xor
xor:
xor $1,$12
xor $12,$tp
xor $10,$8
xor $sp,$11
xor $12,$8
.text
.global nor
nor:
nor $9,$5
nor $8,$2
nor $15,$9
nor $5,$sp
nor $sp,$14
.text
.global or3
or3:
or3 $13,$sp,2
or3 $sp,$tp,3
or3 $0,$10,4
or3 $9,$15,3
or3 $9,$sp,0
.text
.global and3
and3:
and3 $5,$8,1
and3 $11,$gp,3
and3 $6,$0,0
and3 $sp,$sp,0
and3 $1,$10,3
.text
.global xor3
xor3:
xor3 $0,$0,2
xor3 $15,$6,0
xor3 $13,$5,0
xor3 $15,$7,0
xor3 $15,$sp,2
.text
.global sra
sra:
sra $4,$1
sra $fp,$15
sra $1,$1
sra $0,$5
sra $9,$1
.text
.global srl
srl:
srl $2,$11
srl $15,$7
srl $1,$7
srl $3,$13
srl $14,$1
.text
.global sll
sll:
sll $11,$0
sll $tp,$fp
sll $8,$9
sll $13,$15
sll $sp,$sp
.text
.global srai
srai:
sra $1,2
sra $15,3
sra $sp,3
sra $6,4
sra $sp,3
.text
.global srli
srli:
srl $10,0
srl $9,3
srl $6,4
srl $10,2
srl $8,3
.text
.global slli
slli:
sll $0,0
sll $4,0
sll $13,2
sll $11,2
sll $6,0
.text
.global sll3
sll3:
sll3 $0,$tp,4
sll3 $0,$14,0
sll3 $0,$8,2
sll3 $0,$3,2
sll3 $0,$fp,0
.text
.global fsft
fsft:
fsft $gp,$10
fsft $gp,$9
fsft $15,$13
fsft $11,$3
fsft $5,$3
.text
.global bra
bra:
bra 2
bra -2
bra 2
bra 0
bra 2
.text
.global beqz
beqz:
beqz $1,-2
beqz $sp,2
beqz $4,4
beqz $4,0
beqz $9,-2
.text
.global bnez
bnez:
bnez $8,2
bnez $13,2
bnez $gp,0
bnez $6,2
bnez $8,-4
.text
.global beqi
beqi:
beqi $tp,3,0
beqi $0,4,-2
beqi $sp,4,-2
beqi $13,2,0
beqi $4,2,-8
.text
.global bnei
bnei:
bnei $8,1,0
bnei $5,1,2
bnei $5,0,8
bnei $9,4,-2
bnei $0,4,-8
.text
.global blti
blti:
blti $7,3,0
blti $1,1,0
blti $8,2,2
blti $11,2,2
blti $15,3,-2
.text
.global bgei
bgei:
bgei $4,3,-8
bgei $7,0,2
bgei $13,1,0
bgei $5,2,-2
bgei $12,4,-8
.text
.global beq
beq:
beq $7,$2,-2
beq $1,$3,-8
beq $2,$0,2
beq $sp,$fp,2
beq $3,$0,0
.text
.global bne
bne:
bne $6,$3,0
bne $sp,$3,-8
bne $8,$0,2
bne $gp,$sp,8
bne $sp,$4,2
.text
.global bsr12
bsr12:
bsr 2
bsr -8
bsr -16
bsr -2
bsr -8
.text
.global bsr24
bsr24:
bsr 4
bsr -2
bsr -4
bsr 0
bsr 2
.text
.global jmp
jmp:
jmp $2
jmp $tp
jmp $5
jmp $sp
jmp $fp
.text
.global jmp24
jmp24:
jmp 4
jmp 2
jmp 0
jmp 2
jmp 4
.text
.global jsr
jsr:
jsr $15
jsr $13
jsr $13
jsr $6
jsr $6
.text
.global ret
ret:
ret
.text
.global repeat
repeat:
repeat $4,2
repeat $fp,4
repeat $0,8
repeat $6,2
repeat $4,2
.text
.global erepeat
erepeat:
erepeat 2
erepeat 0
erepeat 2
erepeat -2
erepeat 0
.text
.global stc
stc:
stc $13,$mb1
stc $tp,$ccfg
stc $11,$dbg
stc $10,$ccfg
stc $9,$epc
.text
.global ldc
ldc:
ldc $tp,$lo
ldc $8,$npc
ldc $9,$mb0
ldc $15,$sar
ldc $9,$ccfg
.text
.global di
di:
di
.text
.global ei
ei:
ei
.text
.global reti
reti:
reti
.text
.global halt
halt:
halt
.text
.global swi
swi:
swi 2
swi 0
swi 2
swi 3
swi 1
.text
.global break
break:
break
.text
.global sycnm
syncm:
syncm
.text
.global stcb
stcb:
stcb $5,4
stcb $5,1
stcb $gp,0
stcb $15,4
stcb $11,2
.text
.global ldcb
ldcb:
ldcb $2,3
ldcb $2,4
ldcb $9,1
ldcb $10,4
ldcb $1,4
.text
.global bsetm
bsetm:
bsetm ($10),0
bsetm ($sp),0
bsetm ($1),2
bsetm ($sp),4
bsetm ($8),4
.text
.global bclrm
bclrm:
bclrm ($5),0
bclrm ($5),2
bclrm ($8),0
bclrm ($9),2
bclrm ($5),3
.text
.global bnotm
bnotm:
bnotm ($14),4
bnotm ($11),4
bnotm ($10),0
bnotm ($tp),4
bnotm ($fp),0
.text
.global btstm
btstm:
btstm $0,($14),0
btstm $0,($14),1
btstm $0,($11),0
btstm $0,($14),3
btstm $0,($fp),2
.text
.global tas
tas:
tas $7,($tp)
tas $7,($12)
tas $3,($fp)
tas $2,($5)
tas $6,($10)
.text
.global cache
cache:
cache 1,($13)
cache 3,($12)
cache 3,($9)
cache 4,($2)
cache 4,($7)
.text
.global mul
mul:
mul $8,$14
mul $2,$9
mul $14,$15
mul $9,$7
mul $7,$11
.text
.global mulu
mulu:
mulu $2,$5
mulu $6,$gp
mulu $gp,$sp
mulu $11,$14
mulu $3,$9
.text
.global mulr
mulr:
mulr $12,$6
mulr $13,$8
mulr $7,$10
mulr $gp,$1
mulr $0,$15
.text
.global mulru
mulru:
mulru $4,$2
mulru $14,$1
mulru $15,$4
mulru $10,$6
mulru $0,$gp
.text
.global madd
madd:
madd $4,$11
madd $15,$14
madd $14,$sp
madd $4,$tp
madd $1,$gp
.text
.global maddu
maddu:
maddu $0,$1
maddu $7,$6
maddu $9,$5
maddu $gp,$15
maddu $7,$13
.text
.global maddr
maddr:
maddr $6,$fp
maddr $9,$14
maddr $8,$gp
maddr $3,$2
maddr $1,$11
.text
.global maddru
maddru:
maddru $10,$3
maddru $15,$12
maddru $8,$fp
maddru $14,$3
maddru $fp,$15
.text
.global div
div:
div $9,$3
div $4,$14
div $2,$12
div $fp,$tp
div $tp,$6
.text
.global divu
divu:
divu $9,$5
divu $8,$13
divu $0,$14
divu $9,$5
divu $0,$5
.text
.global dret
dret:
dret
.text
.global dbreak
dbreak:
dbreak
.text
.global ldz
ldz:
ldz $gp,$4
ldz $10,$11
ldz $9,$9
ldz $15,$tp
ldz $gp,$3
.text
.global abs
abs:
abs $sp,$9
abs $5,$4
abs $tp,$13
abs $0,$3
abs $3,$14
.text
.global ave
ave:
ave $11,$10
ave $fp,$10
ave $14,$2
ave $10,$12
ave $15,$8
.text
.global min
min:
min $8,$3
min $7,$0
min $2,$2
min $5,$6
min $11,$5
.text
.global max
max:
max $11,$sp
max $gp,$0
max $12,$sp
max $gp,$2
max $14,$sp
.text
.global minu
minu:
minu $11,$8
minu $7,$5
minu $fp,$14
minu $11,$4
minu $2,$sp
.text
.global maxu
maxu:
maxu $3,$3
maxu $13,$0
maxu $4,$fp
maxu $gp,$2
maxu $12,$fp
.text
.global clip
clip:
clip $10,1
clip $15,4
clip $4,3
clip $15,3
clip $1,0
.text
.global clipu
clipu:
clipu $10,4
clipu $13,1
clipu $5,4
clipu $14,0
clipu $5,1
.text
.global sadd
sadd:
sadd $5,$0
sadd $15,$3
sadd $0,$10
sadd $sp,$12
sadd $4,$2
.text
.global ssub
ssub:
ssub $1,$10
ssub $4,$7
ssub $fp,$3
ssub $7,$gp
ssub $13,$4
.text
.global saddu
saddu:
saddu $9,$14
saddu $0,$10
saddu $7,$12
saddu $5,$15
saddu $13,$3
.text
.global ssubu
ssubu:
ssubu $15,$gp
ssubu $0,$15
ssubu $3,$10
ssubu $sp,$13
ssubu $2,$9
.text
.global swcp
swcp:
swcp $c3,($13)
swcp $c15,($13)
swcp $c13,($0)
swcp $c12,($12)
swcp $c9,($gp)
.text
.global lwcp
lwcp:
lwcp $c7,($3)
lwcp $c6,($3)
lwcp $c0,($2)
lwcp $c8,($fp)
lwcp $c11,($13)
.text
.global smcp
smcp:
smcp $c14,($9)
smcp $c2,($fp)
smcp $c14,($15)
smcp $c10,($8)
smcp $c2,($8)
.text
.global lmcp
lmcp:
lmcp $c11,($1)
lmcp $c8,($8)
lmcp $c11,($13)
lmcp $c8,($0)
lmcp $c8,($14)
.text
.global swcpi
swcpi:
swcpi $c7,($0+)
swcpi $c6,($gp+)
swcpi $c12,($8+)
swcpi $c14,($15+)
swcpi $c6,($0+)
.text
.global lwcpi
lwcpi:
lwcpi $c8,($2+)
lwcpi $c9,($0+)
lwcpi $c3,($14+)
lwcpi $c13,($5+)
lwcpi $c11,($gp+)
.text
.global smcpi
smcpi:
smcpi $c8,($2+)
smcpi $c11,($9+)
smcpi $c4,($3+)
smcpi $c14,($2+)
smcpi $c9,($3+)
.text
.global lmcpi
lmcpi:
lmcpi $c6,($14+)
lmcpi $c9,($5+)
lmcpi $c10,($6+)
lmcpi $c1,($6+)
lmcpi $c2,($8+)
.text
.global swcp16
swcp16:
swcp $c0,-1($2)
swcp $c5,1($10)
swcp $c8,2($12)
swcp $c14,-1($1)
swcp $c12,2($3)
.text
.global lwcp16
lwcp16:
lwcp $c8,-1($5)
lwcp $c12,1($15)
lwcp $c1,2($0)
lwcp $c4,1($13)
lwcp $c6,2($11)
.text
.global smcp16
smcp16:
smcp $c9,-1($10)
smcp $c14,1($gp)
smcp $c3,2($sp)
smcp $c15,-2($8)
smcp $c13,1($13)
.text
.global lmcp16
lmcp16:
lmcp $c0,1($15)
lmcp $c15,1($fp)
lmcp $c2,-1($8)
lmcp $c14,1($fp)
lmcp $c1,-1($10)
.text
.global sbcpa
sbcpa:
sbcpa $c14,($sp+),2
sbcpa $c2,($4+),-2
sbcpa $c8,($1+),0
sbcpa $c11,($3+),0
sbcpa $c9,($14+),-2
.text
.global lbcpa
lbcpa:
lbcpa $c7,($2+),-2
lbcpa $c12,($sp+),2
lbcpa $c5,($4+),-2
lbcpa $c7,($4+),-2
lbcpa $c8,($15+),0
.text
.global shcpa
shcpa:
shcpa $c0,($14+),0
shcpa $c12,($sp+),16
shcpa $c1,($4+),4
shcpa $c5,($4+),-32
shcpa $c1,($15+),0
.text
.global lhcpa
lhcpa:
lhcpa $c4,($4+),0
lhcpa $c6,($5+),48
lhcpa $c3,($6+),-52
lhcpa $c8,($6+),-24
lhcpa $c0,($9+),0
.text
.global swcpa
swcpa:
swcpa $c1,($9+),16
swcpa $c7,($sp+),32
swcpa $c3,($12+),48
swcpa $c10,($9+),8
swcpa $c14,($8+),4
.text
.global lwcpa
lwcpa:
lwcpa $c6,($gp+),-8
lwcpa $c4,($7+),4
lwcpa $c11,($gp+),-16
lwcpa $c10,($sp+),-32
lwcpa $c2,($2+),8
.text
.global smcpa
smcpa:
smcpa $c13,($15+),-8
smcpa $c6,($7+),-8
smcpa $c5,($3+),16
smcpa $c13,($15+),16
smcpa $c3,($12+),48
.text
.global lmcpa
lmcpa:
lmcpa $c9,($4+),0
lmcpa $c3,($sp+),-16
lmcpa $c15,($13+),8
lmcpa $c8,($8+),-8
lmcpa $c10,($9+),0
.text
.global sbcpm0
sbcpm0:
sbcpm0 $c10,($13+),8
sbcpm0 $c13,($5+),-8
sbcpm0 $c4,($5+),-8
sbcpm0 $c10,($tp+),16
sbcpm0 $c4,($5+),-24
.text
.global lbcpm0
lbcpm0:
lbcpm0 $c0,($4+),0
lbcpm0 $c9,($7+),-8
lbcpm0 $c12,($fp+),24
lbcpm0 $c8,($12+),16
lbcpm0 $c7,($fp+),16
.text
.global shcpm0
shcpm0:
shcpm0 $c2,($13+),2
shcpm0 $c7,($15+),-2
shcpm0 $c8,($2+),2
shcpm0 $c13,($5+),0
shcpm0 $c3,($14+),8
.text
.global lhcpm0
lhcpm0:
lhcpm0 $c7,($4+),8
lhcpm0 $c3,($3+),-2
lhcpm0 $c3,($1+),0
lhcpm0 $c2,($gp+),0
lhcpm0 $c12,($6+),2
.text
.global swcpm0
swcpm0:
swcpm0 $c8,($fp+),32
swcpm0 $c9,($sp+),0
swcpm0 $c9,($2+),-16
swcpm0 $c0,($14+),48
swcpm0 $c15,($1+),8
.text
.global lwcpm0
lwcpm0:
lwcpm0 $c14,($10+),-4
lwcpm0 $c11,($sp+),-4
lwcpm0 $c5,($7+),-8
lwcpm0 $c2,($12+),32
lwcpm0 $c2,($gp+),16
.text
.global smcpm0
smcpm0:
smcpm0 $c1,($12+),8
smcpm0 $c8,($4+),-16
smcpm0 $c10,($11+),0
smcpm0 $c1,($3+),-16
smcpm0 $c11,($sp+),-8
.text
.global lmcpm0
lmcpm0:
lmcpm0 $c14,($10+),0
lmcpm0 $c6,($15+),-16
lmcpm0 $c13,($1+),8
lmcpm0 $c10,($tp+),-24
lmcpm0 $c7,($14+),-24
.text
.global sbcpm1
sbcpm1:
sbcpm1 $c9,($fp+),0
sbcpm1 $c7,($12+),-24
sbcpm1 $c15,($5+),-24
sbcpm1 $c5,($tp+),16
sbcpm1 $c6,($1+),-128
.text
.global lbcpm1
lbcpm1:
lbcpm1 $c6,($gp+),2
lbcpm1 $c7,($tp+),-2
lbcpm1 $c4,($13+),1
lbcpm1 $c12,($2+),-2
lbcpm1 $c11,($7+),1
.text
.global shcpm1
shcpm1:
shcpm1 $c4,($fp+),24
shcpm1 $c11,($6+),-16
shcpm1 $c7,($8+),8
shcpm1 $c5,($12+),16
shcpm1 $c0,($8+),-32
.text
.global lhcpm1
lhcpm1:
lhcpm1 $c11,($0+),0
lhcpm1 $c7,($tp+),-2
lhcpm1 $c10,($8+),8
lhcpm1 $c3,($tp+),0
lhcpm1 $c9,($6+),2
.text
.global swcpm1
swcpm1:
swcpm1 $c9,($8+),24
swcpm1 $c9,($14+),0
swcpm1 $c9,($fp+),16
swcpm1 $c14,($1+),0
swcpm1 $c2,($sp+),8
.text
.global lwcpm1
lwcpm1:
lwcpm1 $c8,($fp+),0
lwcpm1 $c3,($14+),-16
lwcpm1 $c7,($6+),-8
lwcpm1 $c14,($fp+),-24
lwcpm1 $c3,($fp+),24
.text
.global smcpm1
smcpm1:
smcpm1 $c10,($4+),0
smcpm1 $c6,($sp+),-16
smcpm1 $c13,($7+),-24
smcpm1 $c3,($gp+),-8
smcpm1 $c0,($2+),8
.text
.global lmcpm1
lmcpm1:
lmcpm1 $c12,($1+),0
lmcpm1 $c0,($6+),8
lmcpm1 $c6,($2+),-8
lmcpm1 $c12,($gp+),-16
lmcpm1 $c14,($15+),48
/*
.text
.global cmov1
cmov1:
cmov $c11,$10
cmov $c14,$3
cmov $c3,$15
cmov $c6,$5
cmov $c6,$10
.text
.global cmov2
cmov2:
cmov $11,$c2
cmov $10,$c2
cmov $tp,$c10
cmov $12,$c9
cmov $15,$c3
.text
.global cmovc1
cmovc1:
cmovc $ccr9,$sp
cmovc $ccr12,$fp
cmovc $ccr1,$4
cmovc $ccr11,$sp
cmovc $ccr14,$7
.text
.global cmovc2
cmovc2:
cmovc $fp,$ccr6
cmovc $fp,$ccr6
cmovc $7,$ccr8
cmovc $sp,$ccr12
cmovc $sp,$ccr5
.text
.global cmovh1
cmovh1:
cmovh $c8,$1
cmovh $c12,$sp
cmovh $c11,$5
cmovh $c4,$4
cmovh $c3,$gp
.text
.global cmovh2
cmovh2:
cmovh $4,$c7
cmovh $gp,$c8
cmovh $6,$c10
cmovh $2,$c8
cmovh $10,$c4
*/
.text
.global bcpeq
bcpeq:
bcpeq 4,0
bcpeq 0,-2
bcpeq 4,-2
bcpeq 1,2
bcpeq 2,2
.text
.global bcpne
bcpne:
bcpne 2,0
bcpne 4,0
bcpne 1,0
bcpne 4,0
bcpne 1,2
.text
.global bcpat
bcpat:
bcpat 1,-2
bcpat 0,2
bcpat 0,-2
bcpat 2,0
bcpat 1,-2
.text
.global bcpaf
bcpaf:
bcpaf 4,0
bcpaf 3,0
bcpaf 4,0
bcpaf 1,2
bcpaf 4,2
.text
.global synccp
synccp:
synccp
.text
.global jsrv
jsrv:
jsrv $11
jsrv $5
jsrv $10
jsrv $12
jsrv $10
.text
.global bsrv
bsrv:
bsrv -2
bsrv -2
bsrv -2
bsrv 2
bsrv 0
.text
.global case106341
case106341:
stc $10,7
ldc $0, (4 + 4)
case106821:
/* Actual 16 bit form */
sb $0,($0)
sh $0,($0)
sw $0,($0)
lb $0,($0)
lh $0,($0)
lw $0,($0)
lbu $0,($0)
lhu $0,($0)
/* Should use 16 bit form */
sb $0,0($0)
sb $0,%lo(0)($0)
sb $0,%hi(0)($0)
sb $0,%uhi(0)($0)
sb $0,%sdaoff(0)($0)
sb $0,%tpoff(0)($0)
sh $0,0($0)
sh $0,%lo(0)($0)
sh $0,%hi(0)($0)
sh $0,%uhi(0)($0)
sh $0,%sdaoff(0)($0)
sh $0,%tpoff(0)($0)
sw $0,0($0)
sw $0,%lo(0)($0)
sw $0,%hi(0)($0)
sw $0,%uhi(0)($0)
sw $0,%sdaoff(0)($0)
sw $0,%tpoff(0)($0)
lb $0,0($0)
lb $0,%lo(0)($0)
lb $0,%hi(0)($0)
lb $0,%uhi(0)($0)
lb $0,%sdaoff(0)($0)
lb $0,%tpoff(0)($0)
lh $0,0($0)
lh $0,%lo(0)($0)
lh $0,%hi(0)($0)
lh $0,%uhi(0)($0)
lh $0,%sdaoff(0)($0)
lh $0,%tpoff(0)($0)
lw $0,0($0)
lw $0,%lo(0)($0)
lw $0,%hi(0)($0)
lw $0,%uhi(0)($0)
lw $0,%sdaoff(0)($0)
lw $0,%tpoff(0)($0)
lbu $0,0($0)
lbu $0,%lo(0)($0)
lbu $0,%hi(0)($0)
lbu $0,%uhi(0)($0)
lbu $0,%sdaoff(0)($0)
lbu $0,%tpoff(0)($0)
lhu $0,0($0)
lhu $0,%lo(0)($0)
lhu $0,%hi(0)($0)
lhu $0,%uhi(0)($0)
lhu $0,%sdaoff(0)($0)
lhu $0,%tpoff(0)($0)
/* Should use 32 bit form */
sb $0,1($0)
sb $0,%lo(1)($0)
sb $0,%hi(1)($0)
sb $0,%uhi(1)($0)
sb $0,%sdaoff(1)($0)
sb $0,%tpoff(1)($0)
sh $0,1($0)
sh $0,%lo(1)($0)
sh $0,%hi(1)($0)
sh $0,%uhi(1)($0)
sh $0,%sdaoff(1)($0)
sh $0,%tpoff(1)($0)
sw $0,1($0)
sw $0,%lo(1)($0)
sw $0,%hi(1)($0)
sw $0,%uhi(1)($0)
sw $0,%sdaoff(1)($0)
sw $0,%tpoff(1)($0)
lb $0,1($0)
lb $0,%lo(1)($0)
lb $0,%hi(1)($0)
lb $0,%uhi(1)($0)
lb $0,%sdaoff(1)($0)
lb $0,%tpoff(1)($0)
lh $0,1($0)
lh $0,%lo(1)($0)
lh $0,%hi(1)($0)
lh $0,%uhi(1)($0)
lh $0,%sdaoff(1)($0)
lh $0,%tpoff(1)($0)
lw $0,1($0)
lw $0,%lo(1)($0)
lw $0,%hi(1)($0)
lw $0,%uhi(1)($0)
lw $0,%sdaoff(1)($0)
lw $0,%tpoff(1)($0)
lbu $0,1($0)
lbu $0,%lo(1)($0)
lbu $0,%hi(1)($0)
lbu $0,%uhi(1)($0)
lbu $0,%sdaoff(1)($0)
lbu $0,%tpoff(1)($0)
lhu $0,1($0)
lhu $0,%lo(1)($0)
lhu $0,%hi(1)($0)
lhu $0,%uhi(1)($0)
lhu $0,%sdaoff(1)($0)
lhu $0,%tpoff(1)($0)
/* Should use 32 bit form */
sb $0,case106821($0)
sb $0,%lo(case106821)($0)
sb $0,%hi(case106821)($0)
sb $0,%uhi(case106821)($0)
sh $0,case106821($0)
sh $0,%lo(case106821)($0)
sh $0,%hi(case106821)($0)
sh $0,%uhi(case106821)($0)
sw $0,case106821($0)
sw $0,%lo(case106821)($0)
sw $0,%hi(case106821)($0)
sw $0,%uhi(case106821)($0)
lb $0,case106821($0)
lb $0,%lo(case106821)($0)
lb $0,%hi(case106821)($0)
lb $0,%uhi(case106821)($0)
lh $0,case106821($0)
lh $0,%lo(case106821)($0)
lh $0,%hi(case106821)($0)
lh $0,%uhi(case106821)($0)
lw $0,case106821($0)
lw $0,%lo(case106821)($0)
lw $0,%hi(case106821)($0)
lw $0,%uhi(case106821)($0)
lbu $0,case106821($0)
lbu $0,%lo(case106821)($0)
lbu $0,%hi(case106821)($0)
lbu $0,%uhi(case106821)($0)
lhu $0,case106821($0)
lhu $0,%lo(case106821)($0)
lhu $0,%hi(case106821)($0)
lhu $0,%uhi(case106821)($0)
|
stsp/binutils-ia16
| 21,991
|
gas/testsuite/gas/mep/dj1.s
|
mov $0,$0
mov $1,$0
mov $2,$0
mov $3,$0
mov $4,$0
mov $5,$0
mov $6,$0
mov $7,$0
mov $8,$0
mov $9,$0
mov $10,$0
mov $11,$0
mov $12,$0
mov $13,$0
mov $14,$0
mov $15,$0
mov $fp,$0
mov $tp,$0
mov $gp,$0
mov $sp,$0
sb $0,($0)
sh $0,($0)
sw $0,($0)
lb $0,($0)
lh $0,($0)
lw $0,($0)
lbu $0,($0)
lhu $0,($0)
sb $15,($0)
sh $15,($0)
sw $15,($0)
lb $15,($0)
lh $15,($0)
lw $15,($0)
lbu $15,($0)
lhu $15,($0)
sb $0,($15)
sh $0,($15)
sw $0,($15)
lb $0,($15)
lh $0,($15)
lw $0,($15)
lbu $0,($15)
lhu $0,($15)
sb $15,($15)
sh $15,($15)
sw $15,($15)
lb $15,($15)
lh $15,($15)
lw $15,($15)
lbu $15,($15)
lhu $15,($15)
sw $0,0($sp)
lw $0,0($sp)
sw $15,0($sp)
lw $15,0($sp)
sw $0,124($sp)
lw $0,124($sp)
sw $15,124($sp)
lw $15,124($sp)
sw $0,0($15)
lw $0,0($15)
sw $15,0($15)
lw $15,0($15)
sw $0,124($15)
lw $0,124($15)
sw $15,124($15)
lw $15,124($15)
sb $0,0($tp)
lb $0,0($tp)
lbu $0,0($tp)
sb $7,0($tp)
lb $7,0($tp)
lbu $7,0($tp)
sb $0,127($tp)
lb $0,127($tp)
lbu $0,127($tp)
sb $7,127($tp)
lb $7,127($tp)
lbu $7,127($tp)
sb $0,%tpoff(symbol)($tp)
lb $0,%tpoff(symbol)($tp)
lbu $0,%tpoff(symbol)($tp)
sb $7,%tpoff(symbol)($tp)
lb $7,%tpoff(symbol)($tp)
lbu $7,%tpoff(symbol)($tp)
sb $0,0($13)
lb $0,0($13)
lbu $0,0($13)
sb $7,0($13)
lb $7,0($13)
lbu $7,0($13)
sb $0,127($13)
lb $0,127($13)
lbu $0,127($13)
sb $7,127($13)
lb $7,127($13)
lbu $7,127($13)
sb $0,%tpoff(symbol)($13)
lb $0,%tpoff(symbol)($13)
lbu $0,%tpoff(symbol)($13)
sb $7,%tpoff(symbol)($13)
lb $7,%tpoff(symbol)($13)
lbu $7,%tpoff(symbol)($13)
sh $0,0($tp)
lh $0,0($tp)
lhu $0,0($tp)
sh $7,0($tp)
lh $7,0($tp)
lhu $7,0($tp)
sh $0,126($tp)
lh $0,126($tp)
lhu $0,126($tp)
sh $7,126($tp)
lh $7,126($tp)
lhu $7,126($tp)
sh $0,%tpoff(symbol)($tp)
lh $0,%tpoff(symbol)($tp)
lhu $0,%tpoff(symbol)($tp)
sh $7,%tpoff(symbol)($tp)
lh $7,%tpoff(symbol)($tp)
lhu $7,%tpoff(symbol)($tp)
sh $0,0($13)
lh $0,0($13)
lhu $0,0($13)
sh $7,0($13)
lh $7,0($13)
lhu $7,0($13)
sh $0,126($13)
lh $0,126($13)
lhu $0,126($13)
sh $7,126($13)
lh $7,126($13)
lhu $7,126($13)
sh $0,%tpoff(symbol)($13)
lh $0,%tpoff(symbol)($13)
lhu $0,%tpoff(symbol)($13)
sh $7,%tpoff(symbol)($13)
lh $7,%tpoff(symbol)($13)
lhu $7,%tpoff(symbol)($13)
sw $0,0($tp)
lw $0,0($tp)
sw $7,0($tp)
lw $7,0($tp)
sw $0,124($tp)
lw $0,124($tp)
sw $7,124($tp)
lw $7,124($tp)
sw $0,%tpoff(symbol)($tp)
lw $0,%tpoff(symbol)($tp)
sw $7,%tpoff(symbol)($tp)
lw $7,%tpoff(symbol)($tp)
sw $0,0($13)
lw $0,0($13)
sw $7,0($13)
lw $7,0($13)
sw $0,124($13)
lw $0,124($13)
sw $7,124($13)
lw $7,124($13)
sw $0,%tpoff(symbol)($13)
lw $0,%tpoff(symbol)($13)
sw $7,%tpoff(symbol)($13)
lw $7,%tpoff(symbol)($13)
sb $0,-32768($0)
sh $0,-32768($0)
sw $0,-32768($0)
lb $0,-32768($0)
lh $0,-32768($0)
lw $0,-32768($0)
lbu $0,-32768($0)
lhu $0,-32768($0)
sb $15,-32768($0)
sh $15,-32768($0)
sw $15,-32768($0)
lb $15,-32768($0)
lh $15,-32768($0)
lw $15,-32768($0)
lbu $15,-32768($0)
lhu $15,-32768($0)
sb $0,32767($0)
sh $0,32767($0)
sw $0,32767($0)
lb $0,32767($0)
lh $0,32767($0)
lw $0,32767($0)
lbu $0,32767($0)
lhu $0,32767($0)
sb $15,32767($0)
sh $15,32767($0)
sw $15,32767($0)
lb $15,32767($0)
lh $15,32767($0)
lw $15,32767($0)
lbu $15,32767($0)
lhu $15,32767($0)
sb $0,%sdaoff(symbol)($0)
sh $0,%sdaoff(symbol)($0)
sw $0,%sdaoff(symbol)($0)
lb $0,%sdaoff(symbol)($0)
lh $0,%sdaoff(symbol)($0)
lw $0,%sdaoff(symbol)($0)
lbu $0,%sdaoff(symbol)($0)
lhu $0,%sdaoff(symbol)($0)
sb $15,%sdaoff(symbol)($0)
sh $15,%sdaoff(symbol)($0)
sw $15,%sdaoff(symbol)($0)
lb $15,%sdaoff(symbol)($0)
lh $15,%sdaoff(symbol)($0)
lw $15,%sdaoff(symbol)($0)
lbu $15,%sdaoff(symbol)($0)
lhu $15,%sdaoff(symbol)($0)
sb $0,-32768($0)
sh $0,-32768($0)
sw $0,-32768($0)
lb $0,-32768($0)
lh $0,-32768($0)
lw $0,-32768($0)
lbu $0,-32768($0)
lhu $0,-32768($0)
sb $15,-32768($0)
sh $15,-32768($0)
sw $15,-32768($0)
lb $15,-32768($0)
lh $15,-32768($0)
lw $15,-32768($0)
lbu $15,-32768($0)
lhu $15,-32768($0)
sb $0,32767($0)
sh $0,32767($0)
sw $0,32767($0)
lb $0,32767($0)
lh $0,32767($0)
lw $0,32767($0)
lbu $0,32767($0)
lhu $0,32767($0)
sb $15,32767($0)
sh $15,32767($0)
sw $15,32767($0)
lb $15,32767($0)
lh $15,32767($0)
lw $15,32767($0)
lbu $15,32767($0)
lhu $15,32767($0)
sb $0,%tpoff(symbol)($0)
sh $0,%tpoff(symbol)($0)
sw $0,%tpoff(symbol)($0)
lb $0,%tpoff(symbol)($0)
lh $0,%tpoff(symbol)($0)
lw $0,%tpoff(symbol)($0)
lbu $0,%tpoff(symbol)($0)
lhu $0,%tpoff(symbol)($0)
sb $15,%tpoff(symbol)($0)
sh $15,%tpoff(symbol)($0)
sw $15,%tpoff(symbol)($0)
lb $15,%tpoff(symbol)($0)
lh $15,%tpoff(symbol)($0)
lw $15,%tpoff(symbol)($0)
lbu $15,%tpoff(symbol)($0)
lhu $15,%tpoff(symbol)($0)
sb $0,-32768($15)
sh $0,-32768($15)
sw $0,-32768($15)
lb $0,-32768($15)
lh $0,-32768($15)
lw $0,-32768($15)
lbu $0,-32768($15)
lhu $0,-32768($15)
sb $15,-32768($15)
sh $15,-32768($15)
sw $15,-32768($15)
lb $15,-32768($15)
lh $15,-32768($15)
lw $15,-32768($15)
lbu $15,-32768($15)
lhu $15,-32768($15)
sb $0,32767($15)
sh $0,32767($15)
sw $0,32767($15)
lb $0,32767($15)
lh $0,32767($15)
lw $0,32767($15)
lbu $0,32767($15)
lhu $0,32767($15)
sb $15,32767($15)
sh $15,32767($15)
sw $15,32767($15)
lb $15,32767($15)
lh $15,32767($15)
lw $15,32767($15)
lbu $15,32767($15)
lhu $15,32767($15)
sb $0,%sdaoff(symbol)($15)
sh $0,%sdaoff(symbol)($15)
sw $0,%sdaoff(symbol)($15)
lb $0,%sdaoff(symbol)($15)
lh $0,%sdaoff(symbol)($15)
lw $0,%sdaoff(symbol)($15)
lbu $0,%sdaoff(symbol)($15)
lhu $0,%sdaoff(symbol)($15)
sb $15,%sdaoff(symbol)($15)
sh $15,%sdaoff(symbol)($15)
sw $15,%sdaoff(symbol)($15)
lb $15,%sdaoff(symbol)($15)
lh $15,%sdaoff(symbol)($15)
lw $15,%sdaoff(symbol)($15)
lbu $15,%sdaoff(symbol)($15)
lhu $15,%sdaoff(symbol)($15)
sb $0,-32768($15)
sh $0,-32768($15)
sw $0,-32768($15)
lb $0,-32768($15)
lh $0,-32768($15)
lw $0,-32768($15)
lbu $0,-32768($15)
lhu $0,-32768($15)
sb $15,-32768($15)
sh $15,-32768($15)
sw $15,-32768($15)
lb $15,-32768($15)
lh $15,-32768($15)
lw $15,-32768($15)
lbu $15,-32768($15)
lhu $15,-32768($15)
sb $0,32767($15)
sh $0,32767($15)
sw $0,32767($15)
lb $0,32767($15)
lh $0,32767($15)
lw $0,32767($15)
lbu $0,32767($15)
lhu $0,32767($15)
sb $15,32767($15)
sh $15,32767($15)
sw $15,32767($15)
lb $15,32767($15)
lh $15,32767($15)
lw $15,32767($15)
lbu $15,32767($15)
lhu $15,32767($15)
sb $0,%tpoff(symbol)($15)
sh $0,%tpoff(symbol)($15)
sw $0,%tpoff(symbol)($15)
lb $0,%tpoff(symbol)($15)
lh $0,%tpoff(symbol)($15)
lw $0,%tpoff(symbol)($15)
lbu $0,%tpoff(symbol)($15)
lhu $0,%tpoff(symbol)($15)
sb $15,%tpoff(symbol)($15)
sh $15,%tpoff(symbol)($15)
sw $15,%tpoff(symbol)($15)
lb $15,%tpoff(symbol)($15)
lh $15,%tpoff(symbol)($15)
lw $15,%tpoff(symbol)($15)
lbu $15,%tpoff(symbol)($15)
lhu $15,%tpoff(symbol)($15)
sw $0,(0)
lw $0,(0)
sw $15,(0)
lw $15,(0)
sw $0,(0xfffffc)
lw $0,(0xfffffc)
sw $15,(0xfffffc)
lw $15,(0xfffffc)
sw $0,(symbol)
lw $0,(symbol)
sw $15,(symbol)
lw $15,(symbol)
extb $0
extub $0
exth $0
extuh $0
extb $15
extub $15
exth $15
extuh $15
ssarb 0($0)
ssarb 3($0)
ssarb 0($15)
ssarb 3($15)
mov $0,$0
mov $15,$0
mov $0,$15
mov $15,$15
mov $0,-32768
mov $15,-32768
mov $0,-128
mov $15,-128
mov $0,0
mov $15,0
mov $0,127
mov $15,127
mov $0,32767
mov $15,32767
mov $0,%lo(symbol)
mov $0,%hi(symbol)
mov $0,%uhi(symbol)
mov $0,%sdaoff(symbol)
mov $0,%tpoff(symbol)
movu $0,0
movu $7,0
movu $0,0xffffff
movu $7,0xffffff
movu $0,%lo(symbol)
movu $7,%lo(symbol)
movu $0,symbol
movu $7,symbol
movu $0,0
movh $0,0
movu $15,0
movh $15,0
movu $0,0xffff
movh $0,0xffff
movu $15,0xffff
movh $15,0xffff
movu $0,%lo(symbol)
movh $0,%lo(symbol)
movu $15,%lo(symbol)
movh $15,%lo(symbol)
movu $0,%hi(symbol)
movh $0,%hi(symbol)
movu $15,%hi(symbol)
movh $15,%hi(symbol)
movu $0,%uhi(symbol)
movh $0,%uhi(symbol)
movu $15,%uhi(symbol)
movh $15,%uhi(symbol)
movu $0,%lo(0x12345678)
movh $0,%lo(0x12345678)
movu $15,%lo(0x12345678)
movh $15,%lo(0x12345678)
movu $0,%hi(0x12345678)
movh $0,%hi(0x12345678)
movu $15,%hi(0x12345678)
movh $15,%hi(0x12345678)
movu $0,%uhi(0x12345678)
movh $0,%uhi(0x12345678)
movu $15,%uhi(0x12345678)
movh $15,%uhi(0x12345678)
add3 $0,$0,$0
add3 $15,$0,$0
add3 $0,$15,$0
add3 $15,$15,$0
add3 $0,$0,$15
add3 $15,$0,$15
add3 $0,$15,$15
add3 $15,$15,$15
add $0,-16
add $15,-16
add $0,0
add $15,0
add $0,15
add $15,15
add3 $0,$sp,0
add3 $15,$sp,0
add3 $0,$sp,124
add3 $15,$sp,124
add3 $0,$sp,1
add3 $15,$sp,1
advck3 $0,$0,$0
sbvck3 $0,$0,$0
advck3 $0,$15,$0
sbvck3 $0,$15,$0
advck3 $0,$0,$15
sbvck3 $0,$0,$15
advck3 $0,$15,$15
sbvck3 $0,$15,$15
sub $0,$0
neg $0,$0
sub $15,$0
neg $15,$0
sub $0,$15
neg $0,$15
sub $15,$15
neg $15,$15
slt3 $0,$0,$0
sltu3 $0,$0,$0
sl1ad3 $0,$0,$0
sl2ad3 $0,$0,$0
slt3 $0,$15,$0
sltu3 $0,$15,$0
sl1ad3 $0,$15,$0
sl2ad3 $0,$15,$0
slt3 $0,$0,$15
sltu3 $0,$0,$15
sl1ad3 $0,$0,$15
sl2ad3 $0,$0,$15
slt3 $0,$15,$15
sltu3 $0,$15,$15
sl1ad3 $0,$15,$15
sl2ad3 $0,$15,$15
add3 $0,$0,-32768
add3 $15,$0,-32768
add3 $0,$15,-32768
add3 $15,$15,-32768
add3 $0,$0,32767
add3 $15,$0,32767
add3 $0,$15,32767
add3 $15,$15,32767
add3 $0,$0,%lo(symbol)
add3 $15,$0,%lo(symbol)
add3 $0,$15,%lo(symbol)
add3 $15,$15,%lo(symbol)
slt3 $0,$0,0
sltu3 $0,$0,0
slt3 $0,$15,0
sltu3 $0,$15,0
slt3 $0,$0,31
sltu3 $0,$0,31
slt3 $0,$15,31
sltu3 $0,$15,31
or $0,$0
and $0,$0
xor $0,$0
nor $0,$0
or $15,$0
and $15,$0
xor $15,$0
nor $15,$0
or $0,$15
and $0,$15
xor $0,$15
nor $0,$15
or $15,$15
and $15,$15
xor $15,$15
nor $15,$15
or3 $0,$0,0
and3 $0,$0,0
xor3 $0,$0,0
or3 $15,$0,0
and3 $15,$0,0
xor3 $15,$0,0
or3 $0,$15,0
and3 $0,$15,0
xor3 $0,$15,0
or3 $15,$15,0
and3 $15,$15,0
xor3 $15,$15,0
or3 $0,$0,65535
and3 $0,$0,65535
xor3 $0,$0,65535
or3 $15,$0,65535
and3 $15,$0,65535
xor3 $15,$0,65535
or3 $0,$15,65535
and3 $0,$15,65535
xor3 $0,$15,65535
or3 $15,$15,65535
and3 $15,$15,65535
xor3 $15,$15,65535
or3 $0,$0,%lo(symbol)
and3 $0,$0,%lo(symbol)
xor3 $0,$0,%lo(symbol)
or3 $15,$0,%lo(symbol)
and3 $15,$0,%lo(symbol)
xor3 $15,$0,%lo(symbol)
or3 $0,$15,%lo(symbol)
and3 $0,$15,%lo(symbol)
xor3 $0,$15,%lo(symbol)
or3 $15,$15,%lo(symbol)
and3 $15,$15,%lo(symbol)
xor3 $15,$15,%lo(symbol)
sra $0,$0
srl $0,$0
sll $0,$0
fsft $0,$0
sra $15,$0
srl $15,$0
sll $15,$0
fsft $15,$0
sra $0,$15
srl $0,$15
sll $0,$15
fsft $0,$15
sra $15,$15
srl $15,$15
sll $15,$15
fsft $15,$15
sra $0,0
srl $0,0
sll $0,0
sra $15,0
srl $15,0
sll $15,0
sra $0,31
srl $0,31
sll $0,31
sra $15,31
srl $15,31
sll $15,31
sll3 $0,$0,0
sll3 $0,$15,0
sll3 $0,$0,31
sll3 $0,$15,31
bra .-2048+2
bra .+2046+2
bra symbol
beqz $0,.-128+2
bnez $0,.-128+2
beqz $15,.-128+2
bnez $15,.-128+2
beqz $0,.+126+2
bnez $0,.+126+2
beqz $15,.+126+2
bnez $15,.+126+2
beqz $0,symbol
bnez $0,symbol
beqz $15,symbol
bnez $15,symbol
beqi $0,0,.-65536+4
bnei $0,0,.-65536+4
blti $0,0,.-65536+4
bgei $0,0,.-65536+4
beqi $15,0,.-65536+4
bnei $15,0,.-65536+4
blti $15,0,.-65536+4
bgei $15,0,.-65536+4
beqi $0,15,.-65536+4
bnei $0,15,.-65536+4
blti $0,15,.-65536+4
bgei $0,15,.-65536+4
beqi $15,15,.-65536+4
bnei $15,15,.-65536+4
blti $15,15,.-65536+4
bgei $15,15,.-65536+4
beqi $0,0,.+32763+4
bnei $0,0,.+32763+4
blti $0,0,.+32763+4
bgei $0,0,.+32763+4
beqi $15,0,.+32763+4
bnei $15,0,.+32763+4
blti $15,0,.+32763+4
bgei $15,0,.+32763+4
beqi $0,15,.+32763+4
bnei $0,15,.+32763+4
blti $0,15,.+32763+4
bgei $0,15,.+32763+4
beqi $15,15,.+32763+4
bnei $15,15,.+32763+4
blti $15,15,.+32763+4
bgei $15,15,.+32763+4
beqi $0,0,symbol
bnei $0,0,symbol
blti $0,0,symbol
bgei $0,0,symbol
beqi $15,0,symbol
bnei $15,0,symbol
blti $15,0,symbol
bgei $15,0,symbol
beqi $0,15,symbol
bnei $0,15,symbol
blti $0,15,symbol
bgei $0,15,symbol
beqi $15,15,symbol
bnei $15,15,symbol
blti $15,15,symbol
bgei $15,15,symbol
beq $0,$0,.-65536+4
bne $0,$0,.-65536+4
beq $15,$0,.-65536+4
bne $15,$0,.-65536+4
beq $0,$15,.-65536+4
bne $0,$15,.-65536+4
beq $15,$15,.-65536+4
bne $15,$15,.-65536+4
beq $0,$0,.+32763+4
bne $0,$0,.+32763+4
beq $15,$0,.+32763+4
bne $15,$0,.+32763+4
beq $0,$15,.+32763+4
bne $0,$15,.+32763+4
beq $15,$15,.+32763+4
bne $15,$15,.+32763+4
beq $0,$0,symbol
bne $0,$0,symbol
beq $15,$0,symbol
bne $15,$0,symbol
beq $0,$15,symbol
bne $0,$15,symbol
beq $15,$15,symbol
bne $15,$15,symbol
bsr .-0x800000+4
bsr .-2048+2
bsr .+2046+2
bsr .+0x7ffffe+4
bsr symbol
jmp $0
jmp $15
jmp 0
jmp 0xfffffe
jmp symbol
jsr $0
jsr $15
ret
repeat $0,.-65536+4
repeat $15,.-65536+4
repeat $0,.+32763+4
repeat $15,.+32763+4
repeat $0,symbol
repeat $15,symbol
erepeat .-65536+4
erepeat .+32763+4
erepeat symbol
stc $0,$pc
ldc $0,$pc
stc $15,$pc
ldc $15,$pc
stc $0,$lp
ldc $0,$lp
stc $15,$lp
ldc $15,$lp
stc $0,$sar
ldc $0,$sar
stc $15,$sar
ldc $15,$sar
stc $0,$rpb
ldc $0,$rpb
stc $15,$rpb
ldc $15,$rpb
stc $0,$rpe
ldc $0,$rpe
stc $15,$rpe
ldc $15,$rpe
stc $0,$rpc
ldc $0,$rpc
stc $15,$rpc
ldc $15,$rpc
stc $0,$hi
ldc $0,$hi
stc $15,$hi
ldc $15,$hi
stc $0,$lo
ldc $0,$lo
stc $15,$lo
ldc $15,$lo
stc $0,$mb0
ldc $0,$mb0
stc $15,$mb0
ldc $15,$mb0
stc $0,$me0
ldc $0,$me0
stc $15,$me0
ldc $15,$me0
stc $0,$mb1
ldc $0,$mb1
stc $15,$mb1
ldc $15,$mb1
stc $0,$me1
ldc $0,$me1
stc $15,$me1
ldc $15,$me1
stc $0,$psw
ldc $0,$psw
stc $15,$psw
ldc $15,$psw
stc $0,$id
ldc $0,$id
stc $15,$id
ldc $15,$id
stc $0,$tmp
ldc $0,$tmp
stc $15,$tmp
ldc $15,$tmp
stc $0,$epc
ldc $0,$epc
stc $15,$epc
ldc $15,$epc
stc $0,$exc
ldc $0,$exc
stc $15,$exc
ldc $15,$exc
stc $0,$cfg
ldc $0,$cfg
stc $15,$cfg
ldc $15,$cfg
stc $0,$npc
ldc $0,$npc
stc $15,$npc
ldc $15,$npc
stc $0,$dbg
ldc $0,$dbg
stc $15,$dbg
ldc $15,$dbg
stc $0,$depc
ldc $0,$depc
stc $15,$depc
ldc $15,$depc
stc $0,$opt
ldc $0,$opt
stc $15,$opt
ldc $15,$opt
stc $0,$rcfg
ldc $0,$rcfg
stc $15,$rcfg
ldc $15,$rcfg
stc $0,$ccfg
ldc $0,$ccfg
stc $15,$ccfg
ldc $15,$ccfg
di
ei
reti
halt
break
syncm
swi 0
swi 3
stcb $0,0
ldcb $0,0
stcb $15,0
ldcb $15,0
stcb $0,65535
ldcb $0,65535
stcb $15,65535
ldcb $15,65535
stcb $0,symbol
ldcb $0,symbol
stcb $15,symbol
ldcb $15,symbol
bsetm ($0),0
bclrm ($0),0
bnotm ($0),0
bsetm ($15),0
bclrm ($15),0
bnotm ($15),0
bsetm ($0),7
bclrm ($0),7
bnotm ($0),7
bsetm ($15),7
bclrm ($15),7
bnotm ($15),7
btstm $0,($0),0
btstm $0,($15),0
btstm $0,($0),7
btstm $0,($15),7
tas $0,($0)
tas $15,($0)
tas $0,($15)
tas $15,($15)
cache 0,($0)
cache 3,($0)
cache 0,($15)
cache 3,($15)
mul $0,$0
madd $0,$0
mulr $0,$0
maddr $0,$0
mulu $0,$0
maddu $0,$0
mulru $0,$0
maddru $0,$0
mul $15,$0
madd $15,$0
mulr $15,$0
maddr $15,$0
mulu $15,$0
maddu $15,$0
mulru $15,$0
maddru $15,$0
mul $0,$15
madd $0,$15
mulr $0,$15
maddr $0,$15
mulu $0,$15
maddu $0,$15
mulru $0,$15
maddru $0,$15
mul $15,$15
madd $15,$15
mulr $15,$15
maddr $15,$15
mulu $15,$15
maddu $15,$15
mulru $15,$15
maddru $15,$15
div $0,$0
divu $0,$0
div $15,$0
divu $15,$0
div $0,$15
divu $0,$15
div $15,$15
divu $15,$15
dret
dbreak
ldz $0,$0
abs $0,$0
ave $0,$0
ldz $15,$0
abs $15,$0
ave $15,$0
ldz $0,$15
abs $0,$15
ave $0,$15
ldz $15,$15
abs $15,$15
ave $15,$15
min $0,$0
max $0,$0
minu $0,$0
maxu $0,$0
min $15,$0
max $15,$0
minu $15,$0
maxu $15,$0
min $0,$15
max $0,$15
minu $0,$15
maxu $0,$15
min $15,$15
max $15,$15
minu $15,$15
maxu $15,$15
clip $0,0
clipu $0,0
clip $15,0
clipu $15,0
clip $0,31
clipu $0,31
clip $15,31
clipu $15,31
sadd $0,$0
ssub $0,$0
saddu $0,$0
ssubu $0,$0
sadd $15,$0
ssub $15,$0
saddu $15,$0
ssubu $15,$0
sadd $0,$15
ssub $0,$15
saddu $0,$15
ssubu $0,$15
sadd $15,$15
ssub $15,$15
saddu $15,$15
ssubu $15,$15
swcp $c0,($0)
lwcp $c0,($0)
smcp $c0,($0)
lmcp $c0,($0)
swcp $c15,($0)
lwcp $c15,($0)
smcp $c15,($0)
lmcp $c15,($0)
swcp $c0,($15)
lwcp $c0,($15)
smcp $c0,($15)
lmcp $c0,($15)
swcp $c15,($15)
lwcp $c15,($15)
smcp $c15,($15)
lmcp $c15,($15)
swcpi $c0,($0+)
lwcpi $c0,($0+)
smcpi $c0,($0+)
lmcpi $c0,($0+)
swcpi $c15,($0+)
lwcpi $c15,($0+)
smcpi $c15,($0+)
lmcpi $c15,($0+)
swcpi $c0,($15+)
lwcpi $c0,($15+)
smcpi $c0,($15+)
lmcpi $c0,($15+)
swcpi $c15,($15+)
lwcpi $c15,($15+)
smcpi $c15,($15+)
lmcpi $c15,($15+)
sbcpa $c0,($0+),-128
lbcpa $c0,($0+),-128
sbcpm0 $c0,($0+),-128
lbcpm0 $c0,($0+),-128
sbcpm1 $c0,($0+),-128
lbcpm1 $c0,($0+),-128
sbcpa $c15,($0+),-128
lbcpa $c15,($0+),-128
sbcpm0 $c15,($0+),-128
lbcpm0 $c15,($0+),-128
sbcpm1 $c15,($0+),-128
lbcpm1 $c15,($0+),-128
sbcpa $c0,($15+),-128
lbcpa $c0,($15+),-128
sbcpm0 $c0,($15+),-128
lbcpm0 $c0,($15+),-128
sbcpm1 $c0,($15+),-128
lbcpm1 $c0,($15+),-128
sbcpa $c15,($15+),-128
lbcpa $c15,($15+),-128
sbcpm0 $c15,($15+),-128
lbcpm0 $c15,($15+),-128
sbcpm1 $c15,($15+),-128
lbcpm1 $c15,($15+),-128
sbcpa $c0,($0+),127
lbcpa $c0,($0+),127
sbcpm0 $c0,($0+),127
lbcpm0 $c0,($0+),127
sbcpm1 $c0,($0+),127
lbcpm1 $c0,($0+),127
sbcpa $c15,($0+),127
lbcpa $c15,($0+),127
sbcpm0 $c15,($0+),127
lbcpm0 $c15,($0+),127
sbcpm1 $c15,($0+),127
lbcpm1 $c15,($0+),127
sbcpa $c0,($15+),127
lbcpa $c0,($15+),127
sbcpm0 $c0,($15+),127
lbcpm0 $c0,($15+),127
sbcpm1 $c0,($15+),127
lbcpm1 $c0,($15+),127
sbcpa $c15,($15+),127
lbcpa $c15,($15+),127
sbcpm0 $c15,($15+),127
lbcpm0 $c15,($15+),127
sbcpm1 $c15,($15+),127
lbcpm1 $c15,($15+),127
shcpa $c0,($0+),-128
lhcpa $c0,($0+),-128
shcpm0 $c0,($0+),-128
lhcpm0 $c0,($0+),-128
shcpm1 $c0,($0+),-128
lhcpm1 $c0,($0+),-128
shcpa $c15,($0+),-128
lhcpa $c15,($0+),-128
shcpm0 $c15,($0+),-128
lhcpm0 $c15,($0+),-128
shcpm1 $c15,($0+),-128
lhcpm1 $c15,($0+),-128
shcpa $c0,($15+),-128
lhcpa $c0,($15+),-128
shcpm0 $c0,($15+),-128
lhcpm0 $c0,($15+),-128
shcpm1 $c0,($15+),-128
lhcpm1 $c0,($15+),-128
shcpa $c15,($15+),-128
lhcpa $c15,($15+),-128
shcpm0 $c15,($15+),-128
lhcpm0 $c15,($15+),-128
shcpm1 $c15,($15+),-128
lhcpm1 $c15,($15+),-128
shcpa $c0,($0+),126
lhcpa $c0,($0+),126
shcpm0 $c0,($0+),126
lhcpm0 $c0,($0+),126
shcpm1 $c0,($0+),126
lhcpm1 $c0,($0+),126
shcpa $c15,($0+),126
lhcpa $c15,($0+),126
shcpm0 $c15,($0+),126
lhcpm0 $c15,($0+),126
shcpm1 $c15,($0+),126
lhcpm1 $c15,($0+),126
shcpa $c0,($15+),126
lhcpa $c0,($15+),126
shcpm0 $c0,($15+),126
lhcpm0 $c0,($15+),126
shcpm1 $c0,($15+),126
lhcpm1 $c0,($15+),126
shcpa $c15,($15+),126
lhcpa $c15,($15+),126
shcpm0 $c15,($15+),126
lhcpm0 $c15,($15+),126
shcpm1 $c15,($15+),126
lhcpm1 $c15,($15+),126
swcpa $c0,($0+),-128
lwcpa $c0,($0+),-128
swcpm0 $c0,($0+),-128
lwcpm0 $c0,($0+),-128
swcpm1 $c0,($0+),-128
lwcpm1 $c0,($0+),-128
swcpa $c15,($0+),-128
lwcpa $c15,($0+),-128
swcpm0 $c15,($0+),-128
lwcpm0 $c15,($0+),-128
swcpm1 $c15,($0+),-128
lwcpm1 $c15,($0+),-128
swcpa $c0,($15+),-128
lwcpa $c0,($15+),-128
swcpm0 $c0,($15+),-128
lwcpm0 $c0,($15+),-128
swcpm1 $c0,($15+),-128
lwcpm1 $c0,($15+),-128
swcpa $c15,($15+),-128
lwcpa $c15,($15+),-128
swcpm0 $c15,($15+),-128
lwcpm0 $c15,($15+),-128
swcpm1 $c15,($15+),-128
lwcpm1 $c15,($15+),-128
swcpa $c0,($0+),124
lwcpa $c0,($0+),124
swcpm0 $c0,($0+),124
lwcpm0 $c0,($0+),124
swcpm1 $c0,($0+),124
lwcpm1 $c0,($0+),124
swcpa $c15,($0+),124
lwcpa $c15,($0+),124
swcpm0 $c15,($0+),124
lwcpm0 $c15,($0+),124
swcpm1 $c15,($0+),124
lwcpm1 $c15,($0+),124
swcpa $c0,($15+),124
lwcpa $c0,($15+),124
swcpm0 $c0,($15+),124
lwcpm0 $c0,($15+),124
swcpm1 $c0,($15+),124
lwcpm1 $c0,($15+),124
swcpa $c15,($15+),124
lwcpa $c15,($15+),124
swcpm0 $c15,($15+),124
lwcpm0 $c15,($15+),124
swcpm1 $c15,($15+),124
lwcpm1 $c15,($15+),124
smcpa $c0,($0+),-128
lmcpa $c0,($0+),-128
smcpm0 $c0,($0+),-128
lmcpm0 $c0,($0+),-128
smcpm1 $c0,($0+),-128
lmcpm1 $c0,($0+),-128
smcpa $c15,($0+),-128
lmcpa $c15,($0+),-128
smcpm0 $c15,($0+),-128
lmcpm0 $c15,($0+),-128
smcpm1 $c15,($0+),-128
lmcpm1 $c15,($0+),-128
smcpa $c0,($15+),-128
lmcpa $c0,($15+),-128
smcpm0 $c0,($15+),-128
lmcpm0 $c0,($15+),-128
smcpm1 $c0,($15+),-128
lmcpm1 $c0,($15+),-128
smcpa $c15,($15+),-128
lmcpa $c15,($15+),-128
smcpm0 $c15,($15+),-128
lmcpm0 $c15,($15+),-128
smcpm1 $c15,($15+),-128
lmcpm1 $c15,($15+),-128
smcpa $c0,($0+),120
lmcpa $c0,($0+),120
smcpm0 $c0,($0+),120
lmcpm0 $c0,($0+),120
smcpm1 $c0,($0+),120
lmcpm1 $c0,($0+),120
smcpa $c15,($0+),120
lmcpa $c15,($0+),120
smcpm0 $c15,($0+),120
lmcpm0 $c15,($0+),120
smcpm1 $c15,($0+),120
lmcpm1 $c15,($0+),120
smcpa $c0,($15+),120
lmcpa $c0,($15+),120
smcpm0 $c0,($15+),120
lmcpm0 $c0,($15+),120
smcpm1 $c0,($15+),120
lmcpm1 $c0,($15+),120
smcpa $c15,($15+),120
lmcpa $c15,($15+),120
smcpm0 $c15,($15+),120
lmcpm0 $c15,($15+),120
smcpm1 $c15,($15+),120
lmcpm1 $c15,($15+),120
/*
cmov $c0,$0
cmov $c15,$0
cmov $c0,$15
cmov $c15,$15
cmov $0,$c0
cmov $15,$c0
cmov $0,$c15
cmov $15,$c15
cmovc $ccr0,$0
cmovc $ccr15,$0
cmovc $ccr0,$15
cmovc $ccr15,$15
cmovc $0,$ccr0
cmovc $15,$ccr0
cmovc $0,$ccr15
cmovc $15,$ccr15
cmovh $c0,$0
cmovh $c15,$0
cmovh $c0,$15
cmovh $c15,$15
cmovh $0,$c0
cmovh $15,$c0
cmovh $0,$c15
cmovh $15,$c15
*/
bcpeq 0,.-65536+4
bcpne 0,.-65536+4
bcpat 0,.-65536+4
bcpaf 0,.-65536+4
bcpeq 15,.-65536+4
bcpne 15,.-65536+4
bcpat 15,.-65536+4
bcpaf 15,.-65536+4
bcpeq 0,.+32763+4
bcpne 0,.+32763+4
bcpat 0,.+32763+4
bcpaf 0,.+32763+4
bcpeq 15,.+32763+4
bcpne 15,.+32763+4
bcpat 15,.+32763+4
bcpaf 15,.+32763+4
bcpeq 0,symbol
bcpne 0,symbol
bcpat 0,symbol
bcpaf 0,symbol
bcpeq 15,symbol
bcpne 15,symbol
bcpat 15,symbol
bcpaf 15,symbol
synccp
jsrv $0
jsrv $15
bsrv .+4-0x800000
bsrv .+4+0x7ffffb
bsrv symbol
.byte symbol
.short symbol
.long symbol
|
stsp/binutils-ia16
| 29,325
|
gas/testsuite/gas/ia64/psn.s
|
lfetch.count [r2], 1, 64
lfetch.count.d0 [r22], 5, -64
lfetch.count.nt1 [r23], 9, 1024-64
lfetch.count.d1 [r122], 12, -1024
lfetch.count.nt2 [r5], 16, 0x80
lfetch.count.d2 [r15], 20, -0x100
lfetch.count.nta [r125], 24, 512
lfetch.count.d3 [r8], 29, 960
lfetch.count.d4 [r18], 34, -0x400
lfetch.count.d5 [r127], 62, 0x3bf
lfetch.count.d6 [r10], 63, -0x3ff
lfetch.count.d7 [r96], 64, 0
tf.z p1,p2 = 32;;
tf.nz p7,p2 = @clz;;
tf.z.unc p3,p2 = @clz
tf.nz p3,p4 = @mpy
tf.z.and p5,p4 = @datahints
tf.nz.and p5,p6 = 35
tf.nz.andcm p5,p6 = 35
tf.z.or p7,p6 = 63
tf.nz.or p5,p6 = 35
tf.z.or.andcm p7,p6 = @mpy
tf.nz.or.andcm p7,p6 = @datahints
tf.z.and.orcm p7,p6 = @clz
tf.nz.and.orcm p7,p6 = @mpy
{ .mib
tf.nz.unc p6,p0=33
nop.b 0 ;;
}
lfetch.d4 [r18]
{ .mmi
lfetch.fault.excl.d7 [r19] ;;
lfetch.count [r14], 2, 128
sxt4 r8=r10
}
{ .mmi
lfetch.count.d4 [r11], 64, 256;;
lfetch.excl.d5 [r17]
nop.i 0
}
{ .mmi
lfetch.fault.d6 [r16] ;;
mov dahr7=7
clz r3=r9 ;;
}
mov dahr6=6
mpy4 r2=r9,r8
mpyshl4 r2=r9,r8
{ .mmi
mov dahr5=5 ;;
mov dahr4=4
nop.i 0 ;;
}
{ .mib
mov dahr3=3
add r8=r2,r3
nop.b 0 ;;
}
{ .mmi
mov dahr2=2 ;;
mov dahr1=1
nop.i 0 ;;
}
{ .mib
mov dahr0=0
nop.i 0
}
mov r12 = dahr[r5]
mov r122 = dahr[r55]
st1 [ r65 ] = r93
st1.d1 [ r65 ] = r93
st1.nt1 [ r65 ] = r93
st1.d2 [ r65 ] = r93
st1.nt2 [ r65 ] = r93
st1.nta [ r65 ] = r93
st1.d3 [ r65 ] = r93
st1.d4 [ r65 ] = r93
st1.d5 [ r65 ] = r93
st1.d6 [ r65 ] = r93
st1.d7 [ r65 ] = r93
st2 [ r65 ] = r93
st2.d1 [ r65 ] = r93
st2.nt1 [ r65 ] = r93
st2.d2 [ r65 ] = r93
st2.nt2 [ r65 ] = r93
st2.nta [ r65 ] = r93
st2.d3 [ r65 ] = r93
st2.d4 [ r65 ] = r93
st2.d5 [ r65 ] = r93
st2.d6 [ r65 ] = r93
st2.d7 [ r65 ] = r93
st4 [ r65 ] = r93
st4.d1 [ r65 ] = r93
st4.nt1 [ r65 ] = r93
st4.d2 [ r65 ] = r93
st4.nt2 [ r65 ] = r93
st4.nta [ r65 ] = r93
st4.d3 [ r65 ] = r93
st4.d4 [ r65 ] = r93
st4.d5 [ r65 ] = r93
st4.d6 [ r65 ] = r93
st4.d7 [ r65 ] = r93
st8 [ r65 ] = r93
st8.d1 [ r65 ] = r93
st8.nt1 [ r65 ] = r93
st8.d2 [ r65 ] = r93
st8.nt2 [ r65 ] = r93
st8.nta [ r65 ] = r93
st8.d3 [ r65 ] = r93
st8.d4 [ r65 ] = r93
st8.d5 [ r65 ] = r93
st8.d6 [ r65 ] = r93
st8.d7 [ r65 ] = r93
st16 [ r65 ] = r93
st16 [ r65 ] = r93
st16.d1 [ r65 ] = r93
st16.nt1 [ r65 ] = r93
st16.d2 [ r65 ] = r93
st16.nt2 [ r65 ] = r93
st16.nta [ r65 ] = r93
st16.d3 [ r65 ] = r93
st16.d4 [ r65 ] = r93
st16.d5 [ r65 ] = r93
st16.d6 [ r65 ] = r93
st16.d7 [ r65 ] = r93
st16.nta [ r65 ] = r93
st16.d3 [ r65 ] = r93
st16.d4 [ r65 ] = r93
st16.d5 [ r65 ] = r93
st16.d6 [ r65 ] = r93
st16.d7 [ r65 ] = r93
st1.rel [ r65 ] = r93
st1.rel.d1 [ r65 ] = r93
st1.rel.nt1 [ r65 ] = r93
st1.rel.d2 [ r65 ] = r93
st1.rel.nt2 [ r65 ] = r93
st1.rel.nta [ r65 ] = r93
st1.rel.d3 [ r65 ] = r93
st1.rel.d4 [ r65 ] = r93
st1.rel.d5 [ r65 ] = r93
st1.rel.d6 [ r65 ] = r93
st1.rel.d7 [ r65 ] = r93
st2.rel [ r65 ] = r93
st2.rel.d1 [ r65 ] = r93
st2.rel.nt1 [ r65 ] = r93
st2.rel.d2 [ r65 ] = r93
st2.rel.nt2 [ r65 ] = r93
st2.rel.nta [ r65 ] = r93
st2.rel.d3 [ r65 ] = r93
st2.rel.d4 [ r65 ] = r93
st2.rel.d5 [ r65 ] = r93
st2.rel.d6 [ r65 ] = r93
st2.rel.d7 [ r65 ] = r93
st4.rel [ r65 ] = r93
st4.rel.d1 [ r65 ] = r93
st4.rel.nt1 [ r65 ] = r93
st4.rel.d2 [ r65 ] = r93
st4.rel.nt2 [ r65 ] = r93
st4.rel.nta [ r65 ] = r93
st4.rel.d3 [ r65 ] = r93
st4.rel.d4 [ r65 ] = r93
st4.rel.d5 [ r65 ] = r93
st4.rel.d6 [ r65 ] = r93
st4.rel.d7 [ r65 ] = r93
st8.rel [ r65 ] = r93
st8.rel.d1 [ r65 ] = r93
st8.rel.nt1 [ r65 ] = r93
st8.rel.d2 [ r65 ] = r93
st8.rel.nt2 [ r65 ] = r93
st8.rel.nta [ r65 ] = r93
st8.rel.d3 [ r65 ] = r93
st8.rel.d4 [ r65 ] = r93
st8.rel.d5 [ r65 ] = r93
st8.rel.d6 [ r65 ] = r93
st8.rel.d7 [ r65 ] = r93
st16.rel [ r65 ] = r93
st16.rel [ r65 ] = r93, ar.csd
st16.rel.d1 [ r65 ] = r93
st16.rel.d1 [ r65 ] = r93, ar.csd
st16.rel.nt1 [ r65 ] = r93
st16.rel.nt1 [ r65 ] = r93, ar.csd
st16.rel.d2 [ r65 ] = r93
st16.rel.d2 [ r65 ] = r93, ar.csd
st16.rel.nt2 [ r65 ] = r93
st16.rel.nt2 [ r65 ] = r93, ar.csd
st16.rel.nta [ r65 ] = r93
st16.rel.d3 [ r65 ] = r93
st16.rel.d4 [ r65 ] = r93
st16.rel.d5 [ r65 ] = r93
st16.rel.d6 [ r65 ] = r93
st16.rel.d7 [ r65 ] = r93
st16.rel.nta [ r65 ] = r93, ar.csd
st16.rel.d3 [ r65 ] = r93, ar.csd
st16.rel.d4 [ r65 ] = r93, ar.csd
st16.rel.d5 [ r65 ] = r93, ar.csd
st16.rel.d6 [ r65 ] = r93, ar.csd
st16.rel.d7 [ r65 ] = r93, ar.csd
st8.spill [ r65 ] = r93
st8.spill.d1 [ r65 ] = r93
st8.spill.nt1 [ r65 ] = r93
st8.spill.d2 [ r65 ] = r93
st8.spill.nt2 [ r65 ] = r93
st8.spill.nta [ r65 ] = r93
st8.spill.d3 [ r65 ] = r93
st8.spill.d4 [ r65 ] = r93
st8.spill.d5 [ r65 ] = r93
st8.spill.d6 [ r65 ] = r93
st8.spill.d7 [ r65 ] = r93
lfetch [ r60 ]
lfetch.d1 [ r60 ]
lfetch.nt1 [ r60 ]
lfetch.d2 [ r60 ]
lfetch.nt2 [ r60 ]
lfetch.nta [ r60 ]
lfetch.d3 [ r60 ]
lfetch.d4 [ r60 ]
lfetch.d5 [ r60 ]
lfetch.d6 [ r60 ]
lfetch.d7 [ r60 ]
stfs [ r60 ] = f90
stfs.d1 [ r60 ] = f90
stfs.nt1 [ r60 ] = f90
stfs.d2 [ r60 ] = f90
stfs.nt2 [ r60 ] = f90
stfs.nta [ r60 ] = f90
stfs.d3 [ r60 ] = f90
stfs.d4 [ r60 ] = f90
stfs.d5 [ r60 ] = f90
stfs.d6 [ r60 ] = f90
stfs.d7 [ r60 ] = f90
stfd [ r60 ] = f90
stfd.d1 [ r60 ] = f90
stfd.nt1 [ r60 ] = f90
stfd.d2 [ r60 ] = f90
stfd.nt2 [ r60 ] = f90
stfd.nta [ r60 ] = f90
stfd.d3 [ r60 ] = f90
stfd.d4 [ r60 ] = f90
stfd.d5 [ r60 ] = f90
stfd.d6 [ r60 ] = f90
stfd.d7 [ r60 ] = f90
stf8 [ r60 ] = f90
stf8.d1 [ r60 ] = f90
stf8.nt1 [ r60 ] = f90
stf8.d2 [ r60 ] = f90
stf8.nt2 [ r60 ] = f90
stf8.nta [ r60 ] = f90
stf8.d3 [ r60 ] = f90
stf8.d4 [ r60 ] = f90
stf8.d5 [ r60 ] = f90
stf8.d6 [ r60 ] = f90
stf8.d7 [ r60 ] = f90
stfe [ r60 ] = f90
stfe.d1 [ r60 ] = f90
stfe.nt1 [ r60 ] = f90
stfe.d2 [ r60 ] = f90
stfe.nt2 [ r60 ] = f90
stfe.nta [ r60 ] = f90
stfe.d3 [ r60 ] = f90
stfe.d4 [ r60 ] = f90
stfe.d5 [ r60 ] = f90
stfe.d6 [ r60 ] = f90
stfe.d7 [ r60 ] = f90
stf.spill [ r60 ] = f90
stf.spill.d1 [ r60 ] = f90
stf.spill.nt1 [ r60 ] = f90
stf.spill.d2 [ r60 ] = f90
stf.spill.nt2 [ r60 ] = f90
stf.spill.nta [ r60 ] = f90
stf.spill.d3 [ r60 ] = f90
stf.spill.d4 [ r60 ] = f90
stf.spill.d5 [ r60 ] = f90
stf.spill.d6 [ r60 ] = f90
stf.spill.d7 [ r60 ] = f90
/* Floating-point load. */
ldfs f121 = [ r125 ]
ldfs.nt1 f121 = [ r125 ]
ldfs.d1 f121 = [ r125 ]
ldfs.d2 f121 = [ r125 ]
ldfs.nt2 f121 = [ r125 ]
ldfs.nta f121 = [ r125 ]
ldfs.d3 f121 = [ r125 ]
ldfs.d4 f121 = [ r125 ]
ldfs.d5 f121 = [ r125 ]
ldfs.d6 f121 = [ r125 ]
ldfs.d7 f121 = [ r125 ]
ldfd f121 = [ r125 ]
ldfd.nt1 f121 = [ r125 ]
ldfd.d1 f121 = [ r125 ]
ldfd.d2 f121 = [ r125 ]
ldfd.nt2 f121 = [ r125 ]
ldfd.nta f121 = [ r125 ]
ldfd.d3 f121 = [ r125 ]
ldfd.d4 f121 = [ r125 ]
ldfd.d5 f121 = [ r125 ]
ldfd.d6 f121 = [ r125 ]
ldfd.d7 f121 = [ r125 ]
ldf8 f121 = [ r125 ]
ldf8.nt1 f121 = [ r125 ]
ldf8.d1 f121 = [ r125 ]
ldf8.d2 f121 = [ r125 ]
ldf8.nt2 f121 = [ r125 ]
ldf8.nta f121 = [ r125 ]
ldf8.d3 f121 = [ r125 ]
ldf8.d4 f121 = [ r125 ]
ldf8.d5 f121 = [ r125 ]
ldf8.d6 f121 = [ r125 ]
ldf8.d7 f121 = [ r125 ]
ldfe f121 = [ r125 ]
ldfe.nt1 f121 = [ r125 ]
ldfe.d1 f121 = [ r125 ]
ldfe.d2 f121 = [ r125 ]
ldfe.nt2 f121 = [ r125 ]
ldfe.nta f121 = [ r125 ]
ldfe.d3 f121 = [ r125 ]
ldfe.d4 f121 = [ r125 ]
ldfe.d5 f121 = [ r125 ]
ldfe.d6 f121 = [ r125 ]
ldfe.d7 f121 = [ r125 ]
ldfs.s f121 = [ r125 ]
ldfs.s.nt1 f121 = [ r125 ]
ldfs.s.d1 f121 = [ r125 ]
ldfs.s.d2 f121 = [ r125 ]
ldfs.s.nt2 f121 = [ r125 ]
ldfs.s.nta f121 = [ r125 ]
ldfs.s.d3 f121 = [ r125 ]
ldfs.s.d4 f121 = [ r125 ]
ldfs.s.d5 f121 = [ r125 ]
ldfs.s.d6 f121 = [ r125 ]
ldfs.s.d7 f121 = [ r125 ]
ldfd.s f121 = [ r125 ]
ldfd.s.nt1 f121 = [ r125 ]
ldfd.s.d1 f121 = [ r125 ]
ldfd.s.d2 f121 = [ r125 ]
ldfd.s.nt2 f121 = [ r125 ]
ldfd.s.nta f121 = [ r125 ]
ldfd.s.d3 f121 = [ r125 ]
ldfd.s.d4 f121 = [ r125 ]
ldfd.s.d5 f121 = [ r125 ]
ldfd.s.d6 f121 = [ r125 ]
ldfd.s.d7 f121 = [ r125 ]
ldf8.s f121 = [ r125 ]
ldf8.s.nt1 f121 = [ r125 ]
ldf8.s.d1 f121 = [ r125 ]
ldf8.s.d2 f121 = [ r125 ]
ldf8.s.nt2 f121 = [ r125 ]
ldf8.s.nta f121 = [ r125 ]
ldf8.s.d3 f121 = [ r125 ]
ldf8.s.d4 f121 = [ r125 ]
ldf8.s.d5 f121 = [ r125 ]
ldf8.s.d6 f121 = [ r125 ]
ldf8.s.d7 f121 = [ r125 ]
ldfe.s f121 = [ r125 ]
ldfe.s.nt1 f121 = [ r125 ]
ldfe.s.d1 f121 = [ r125 ]
ldfe.s.d2 f121 = [ r125 ]
ldfe.s.nt2 f121 = [ r125 ]
ldfe.s.nta f121 = [ r125 ]
ldfe.s.d3 f121 = [ r125 ]
ldfe.s.d4 f121 = [ r125 ]
ldfe.s.d5 f121 = [ r125 ]
ldfe.s.d6 f121 = [ r125 ]
ldfe.s.d7 f121 = [ r125 ]
ldfs.a f121 = [ r125 ]
ldfs.a.nt1 f121 = [ r125 ]
ldfs.a.d1 f121 = [ r125 ]
ldfs.a.d2 f121 = [ r125 ]
ldfs.a.nt2 f121 = [ r125 ]
ldfs.a.nta f121 = [ r125 ]
ldfs.a.d3 f121 = [ r125 ]
ldfs.a.d4 f121 = [ r125 ]
ldfs.a.d5 f121 = [ r125 ]
ldfs.a.d6 f121 = [ r125 ]
ldfs.a.d7 f121 = [ r125 ]
ldfd.a f121 = [ r125 ]
ldfd.a.nt1 f121 = [ r125 ]
ldfd.a.d1 f121 = [ r125 ]
ldfd.a.d2 f121 = [ r125 ]
ldfd.a.nt2 f121 = [ r125 ]
ldfd.a.nta f121 = [ r125 ]
ldfd.a.d3 f121 = [ r125 ]
ldfd.a.d4 f121 = [ r125 ]
ldfd.a.d5 f121 = [ r125 ]
ldfd.a.d6 f121 = [ r125 ]
ldfd.a.d7 f121 = [ r125 ]
ldf8.a f121 = [ r125 ]
ldf8.a.nt1 f121 = [ r125 ]
ldf8.a.d1 f121 = [ r125 ]
ldf8.a.d2 f121 = [ r125 ]
ldf8.a.nt2 f121 = [ r125 ]
ldf8.a.nta f121 = [ r125 ]
ldf8.a.d3 f121 = [ r125 ]
ldf8.a.d4 f121 = [ r125 ]
ldf8.a.d5 f121 = [ r125 ]
ldf8.a.d6 f121 = [ r125 ]
ldf8.a.d7 f121 = [ r125 ]
ldfe.a f121 = [ r125 ]
ldfe.a.nt1 f121 = [ r125 ]
ldfe.a.d1 f121 = [ r125 ]
ldfe.a.d2 f121 = [ r125 ]
ldfe.a.nt2 f121 = [ r125 ]
ldfe.a.nta f121 = [ r125 ]
ldfe.a.d3 f121 = [ r125 ]
ldfe.a.d4 f121 = [ r125 ]
ldfe.a.d5 f121 = [ r125 ]
ldfe.a.d6 f121 = [ r125 ]
ldfe.a.d7 f121 = [ r125 ]
ldfs.sa f121 = [ r125 ]
ldfs.sa.nt1 f121 = [ r125 ]
ldfs.sa.d1 f121 = [ r125 ]
ldfs.sa.d2 f121 = [ r125 ]
ldfs.sa.nt2 f121 = [ r125 ]
ldfs.sa.nta f121 = [ r125 ]
ldfs.sa.d3 f121 = [ r125 ]
ldfs.sa.d4 f121 = [ r125 ]
ldfs.sa.d5 f121 = [ r125 ]
ldfs.sa.d6 f121 = [ r125 ]
ldfs.sa.d7 f121 = [ r125 ]
ldfd.sa f121 = [ r125 ]
ldfd.sa.nt1 f121 = [ r125 ]
ldfd.sa.d1 f121 = [ r125 ]
ldfd.sa.d2 f121 = [ r125 ]
ldfd.sa.nt2 f121 = [ r125 ]
ldfd.sa.nta f121 = [ r125 ]
ldfd.sa.d3 f121 = [ r125 ]
ldfd.sa.d4 f121 = [ r125 ]
ldfd.sa.d5 f121 = [ r125 ]
ldfd.sa.d6 f121 = [ r125 ]
ldfd.sa.d7 f121 = [ r125 ]
ldf8.sa f121 = [ r125 ]
ldf8.sa.nt1 f121 = [ r125 ]
ldf8.sa.d1 f121 = [ r125 ]
ldf8.sa.d2 f121 = [ r125 ]
ldf8.sa.nt2 f121 = [ r125 ]
ldf8.sa.nta f121 = [ r125 ]
ldf8.sa.d3 f121 = [ r125 ]
ldf8.sa.d4 f121 = [ r125 ]
ldf8.sa.d5 f121 = [ r125 ]
ldf8.sa.d6 f121 = [ r125 ]
ldf8.sa.d7 f121 = [ r125 ]
ldfe.sa f121 = [ r125 ]
ldfe.sa.nt1 f121 = [ r125 ]
ldfe.sa.d1 f121 = [ r125 ]
ldfe.sa.d2 f121 = [ r125 ]
ldfe.sa.nt2 f121 = [ r125 ]
ldfe.sa.nta f121 = [ r125 ]
ldfe.sa.d3 f121 = [ r125 ]
ldfe.sa.d4 f121 = [ r125 ]
ldfe.sa.d5 f121 = [ r125 ]
ldfe.sa.d6 f121 = [ r125 ]
ldfe.sa.d7 f121 = [ r125 ]
ldf.fill f121 = [ r125 ]
ldf.fill.nt1 f121 = [ r125 ]
ldf.fill.d1 f121 = [ r125 ]
ldf.fill.d2 f121 = [ r125 ]
ldf.fill.nt2 f121 = [ r125 ]
ldf.fill.nta f121 = [ r125 ]
ldf.fill.d3 f121 = [ r125 ]
ldf.fill.d4 f121 = [ r125 ]
ldf.fill.d5 f121 = [ r125 ]
ldf.fill.d6 f121 = [ r125 ]
ldf.fill.d7 f121 = [ r125 ]
ldfs.c.clr f121 = [ r125 ]
ldfs.c.clr.nt1 f121 = [ r125 ]
ldfs.c.clr.d1 f121 = [ r125 ]
ldfs.c.clr.d2 f121 = [ r125 ]
ldfs.c.clr.nt2 f121 = [ r125 ]
ldfs.c.clr.nta f121 = [ r125 ]
ldfs.c.clr.d3 f121 = [ r125 ]
ldfs.c.clr.d4 f121 = [ r125 ]
ldfs.c.clr.d5 f121 = [ r125 ]
ldfs.c.clr.d6 f121 = [ r125 ]
ldfs.c.clr.d7 f121 = [ r125 ]
ldfd.c.clr f121 = [ r125 ]
ldfd.c.clr.nt1 f121 = [ r125 ]
ldfd.c.clr.d1 f121 = [ r125 ]
ldfd.c.clr.d2 f121 = [ r125 ]
ldfd.c.clr.nt2 f121 = [ r125 ]
ldfd.c.clr.nta f121 = [ r125 ]
ldfd.c.clr.d3 f121 = [ r125 ]
ldfd.c.clr.d4 f121 = [ r125 ]
ldfd.c.clr.d5 f121 = [ r125 ]
ldfd.c.clr.d6 f121 = [ r125 ]
ldfd.c.clr.d7 f121 = [ r125 ]
ldf8.c.clr f121 = [ r125 ]
ldf8.c.clr.nt1 f121 = [ r125 ]
ldf8.c.clr.d1 f121 = [ r125 ]
ldf8.c.clr.d2 f121 = [ r125 ]
ldf8.c.clr.nt2 f121 = [ r125 ]
ldf8.c.clr.nta f121 = [ r125 ]
ldf8.c.clr.d3 f121 = [ r125 ]
ldf8.c.clr.d4 f121 = [ r125 ]
ldf8.c.clr.d5 f121 = [ r125 ]
ldf8.c.clr.d6 f121 = [ r125 ]
ldf8.c.clr.d7 f121 = [ r125 ]
ldfe.c.clr f121 = [ r125 ]
ldfe.c.clr.nt1 f121 = [ r125 ]
ldfe.c.clr.d1 f121 = [ r125 ]
ldfe.c.clr.d2 f121 = [ r125 ]
ldfe.c.clr.nt2 f121 = [ r125 ]
ldfe.c.clr.nta f121 = [ r125 ]
ldfe.c.clr.d3 f121 = [ r125 ]
ldfe.c.clr.d4 f121 = [ r125 ]
ldfe.c.clr.d5 f121 = [ r125 ]
ldfe.c.clr.d6 f121 = [ r125 ]
ldfe.c.clr.d7 f121 = [ r125 ]
ldfs.c.nc f121 = [ r125 ]
ldfs.c.nc.nt1 f121 = [ r125 ]
ldfs.c.nc.d1 f121 = [ r125 ]
ldfs.c.nc.d2 f121 = [ r125 ]
ldfs.c.nc.nt2 f121 = [ r125 ]
ldfs.c.nc.nta f121 = [ r125 ]
ldfs.c.nc.d3 f121 = [ r125 ]
ldfs.c.nc.d4 f121 = [ r125 ]
ldfs.c.nc.d5 f121 = [ r125 ]
ldfs.c.nc.d6 f121 = [ r125 ]
ldfs.c.nc.d7 f121 = [ r125 ]
ldfd.c.nc f121 = [ r125 ]
ldfd.c.nc.nt1 f121 = [ r125 ]
ldfd.c.nc.d1 f121 = [ r125 ]
ldfd.c.nc.d2 f121 = [ r125 ]
ldfd.c.nc.nt2 f121 = [ r125 ]
ldfd.c.nc.nta f121 = [ r125 ]
ldfd.c.nc.d3 f121 = [ r125 ]
ldfd.c.nc.d4 f121 = [ r125 ]
ldfd.c.nc.d5 f121 = [ r125 ]
ldfd.c.nc.d6 f121 = [ r125 ]
ldfd.c.nc.d7 f121 = [ r125 ]
ldf8.c.nc f121 = [ r125 ]
ldf8.c.nc.nt1 f121 = [ r125 ]
ldf8.c.nc.d1 f121 = [ r125 ]
ldf8.c.nc.d2 f121 = [ r125 ]
ldf8.c.nc.nt2 f121 = [ r125 ]
ldf8.c.nc.nta f121 = [ r125 ]
ldf8.c.nc.d3 f121 = [ r125 ]
ldf8.c.nc.d4 f121 = [ r125 ]
ldf8.c.nc.d5 f121 = [ r125 ]
ldf8.c.nc.d6 f121 = [ r125 ]
ldf8.c.nc.d7 f121 = [ r125 ]
ldfe.c.nc f121 = [ r125 ]
ldfe.c.nc.nt1 f121 = [ r125 ]
ldfe.c.nc.d1 f121 = [ r125 ]
ldfe.c.nc.d2 f121 = [ r125 ]
ldfe.c.nc.nt2 f121 = [ r125 ]
ldfe.c.nc.nta f121 = [ r125 ]
ldfe.c.nc.d3 f121 = [ r125 ]
ldfe.c.nc.d4 f121 = [ r125 ]
ldfe.c.nc.d5 f121 = [ r125 ]
ldfe.c.nc.d6 f121 = [ r125 ]
ldfe.c.nc.d7 f121 = [ r125 ]
ld1 r120 = [ r20 ]
ld1.nt1 r120 = [ r20 ]
ld1.d1 r120 = [ r20 ]
ld1.d2 r120 = [ r20 ]
ld1.nt2 r120 = [ r20 ]
ld1.nta r120 = [ r20 ]
ld1.d3 r120 = [ r20 ]
ld1.d4 r120 = [ r20 ]
ld1.d5 r120 = [ r20 ]
ld1.d6 r120 = [ r20 ]
ld1.d7 r120 = [ r20 ]
ld2 r120 = [ r20 ]
ld2.nt1 r120 = [ r20 ]
ld2.d1 r120 = [ r20 ]
ld2.d2 r120 = [ r20 ]
ld2.nt2 r120 = [ r20 ]
ld2.nta r120 = [ r20 ]
ld2.d3 r120 = [ r20 ]
ld2.d4 r120 = [ r20 ]
ld2.d5 r120 = [ r20 ]
ld2.d6 r120 = [ r20 ]
ld2.d7 r120 = [ r20 ]
ld4 r120 = [ r20 ]
ld4.nt1 r120 = [ r20 ]
ld4.d1 r120 = [ r20 ]
ld4.d2 r120 = [ r20 ]
ld4.nt2 r120 = [ r20 ]
ld4.nta r120 = [ r20 ]
ld4.d3 r120 = [ r20 ]
ld4.d4 r120 = [ r20 ]
ld4.d5 r120 = [ r20 ]
ld4.d6 r120 = [ r20 ]
ld4.d7 r120 = [ r20 ]
ld8 r120 = [ r20 ]
ld8.nt1 r120 = [ r20 ]
ld8.d1 r120 = [ r20 ]
ld8.d2 r120 = [ r20 ]
ld8.nt2 r120 = [ r20 ]
ld8.nta r120 = [ r20 ]
ld8.d3 r120 = [ r20 ]
ld8.d4 r120 = [ r20 ]
ld8.d5 r120 = [ r20 ]
ld8.d6 r120 = [ r20 ]
ld8.d7 r120 = [ r20 ]
ld1.s r120 = [ r20 ]
ld1.s.nt1 r120 = [ r20 ]
ld1.s.d1 r120 = [ r20 ]
ld1.s.d2 r120 = [ r20 ]
ld1.s.nt2 r120 = [ r20 ]
ld1.s.nta r120 = [ r20 ]
ld1.s.d3 r120 = [ r20 ]
ld1.s.d4 r120 = [ r20 ]
ld1.s.d5 r120 = [ r20 ]
ld1.s.d6 r120 = [ r20 ]
ld1.s.d7 r120 = [ r20 ]
ld2.s r120 = [ r20 ]
ld2.s.nt1 r120 = [ r20 ]
ld2.s.d1 r120 = [ r20 ]
ld2.s.d2 r120 = [ r20 ]
ld2.s.nt2 r120 = [ r20 ]
ld2.s.nta r120 = [ r20 ]
ld2.s.d3 r120 = [ r20 ]
ld2.s.d4 r120 = [ r20 ]
ld2.s.d5 r120 = [ r20 ]
ld2.s.d6 r120 = [ r20 ]
ld2.s.d7 r120 = [ r20 ]
ld4.s r120 = [ r20 ]
ld4.s.nt1 r120 = [ r20 ]
ld4.s.d1 r120 = [ r20 ]
ld4.s.d2 r120 = [ r20 ]
ld4.s.nt2 r120 = [ r20 ]
ld4.s.nta r120 = [ r20 ]
ld4.s.d3 r120 = [ r20 ]
ld4.s.d4 r120 = [ r20 ]
ld4.s.d5 r120 = [ r20 ]
ld4.s.d6 r120 = [ r20 ]
ld4.s.d7 r120 = [ r20 ]
ld8.s r120 = [ r20 ]
ld8.s.nt1 r120 = [ r20 ]
ld8.s.d1 r120 = [ r20 ]
ld8.s.d2 r120 = [ r20 ]
ld8.s.nt2 r120 = [ r20 ]
ld8.s.nta r120 = [ r20 ]
ld8.s.d3 r120 = [ r20 ]
ld8.s.d4 r120 = [ r20 ]
ld8.s.d5 r120 = [ r20 ]
ld8.s.d6 r120 = [ r20 ]
ld8.s.d7 r120 = [ r20 ]
ld1.a r120 = [ r20 ]
ld1.a.nt1 r120 = [ r20 ]
ld1.a.d1 r120 = [ r20 ]
ld1.a.d2 r120 = [ r20 ]
ld1.a.nt2 r120 = [ r20 ]
ld1.a.nta r120 = [ r20 ]
ld1.a.d3 r120 = [ r20 ]
ld1.a.d4 r120 = [ r20 ]
ld1.a.d5 r120 = [ r20 ]
ld1.a.d6 r120 = [ r20 ]
ld1.a.d7 r120 = [ r20 ]
ld2.a r120 = [ r20 ]
ld2.a.nt1 r120 = [ r20 ]
ld2.a.d1 r120 = [ r20 ]
ld2.a.nt2 r120 = [ r20 ]
ld2.a.nta r120 = [ r20 ]
ld2.a.d3 r120 = [ r20 ]
ld2.a.d4 r120 = [ r20 ]
ld2.a.d5 r120 = [ r20 ]
ld2.a.d6 r120 = [ r20 ]
ld2.a.d7 r120 = [ r20 ]
ld4.a r120 = [ r20 ]
ld4.a.nt1 r120 = [ r20 ]
ld4.a.d1 r120 = [ r20 ]
ld4.a.d2 r120 = [ r20 ]
ld4.a.nt2 r120 = [ r20 ]
ld4.a.nta r120 = [ r20 ]
ld4.a.d3 r120 = [ r20 ]
ld4.a.d4 r120 = [ r20 ]
ld4.a.d5 r120 = [ r20 ]
ld4.a.d6 r120 = [ r20 ]
ld4.a.d7 r120 = [ r20 ]
ld8.a r120 = [ r20 ]
ld8.a.nt1 r120 = [ r20 ]
ld8.a.d1 r120 = [ r20 ]
ld8.a.d2 r120 = [ r20 ]
ld8.a.nt2 r120 = [ r20 ]
ld8.a.nta r120 = [ r20 ]
ld8.a.d3 r120 = [ r20 ]
ld8.a.d5 r120 = [ r20 ]
ld8.a.d6 r120 = [ r20 ]
ld8.a.d7 r120 = [ r20 ]
ld1.sa r120 = [ r20 ]
ld1.sa.nt1 r120 = [ r20 ]
ld1.sa.d1 r120 = [ r20 ]
ld1.sa.d2 r120 = [ r20 ]
ld1.sa.nt2 r120 = [ r20 ]
ld1.sa.nta r120 = [ r20 ]
ld1.sa.d3 r120 = [ r20 ]
ld1.sa.d4 r120 = [ r20 ]
ld1.sa.d5 r120 = [ r20 ]
ld1.sa.d6 r120 = [ r20 ]
ld1.sa.d7 r120 = [ r20 ]
ld2.sa r120 = [ r20 ]
ld2.sa.nt1 r120 = [ r20 ]
ld2.sa.d1 r120 = [ r20 ]
ld2.sa.d2 r120 = [ r20 ]
ld2.sa.nt2 r120 = [ r20 ]
ld2.sa.nta r120 = [ r20 ]
ld2.sa.d3 r120 = [ r20 ]
ld2.sa.d4 r120 = [ r20 ]
ld2.sa.d5 r120 = [ r20 ]
ld2.sa.d6 r120 = [ r20 ]
ld2.sa.d7 r120 = [ r20 ]
ld4.sa.nt1 r120 = [ r20 ]
ld4.sa.d1 r120 = [ r20 ]
ld4.sa.d2 r120 = [ r20 ]
ld4.sa.nt2 r120 = [ r20 ]
ld4.sa.nta r120 = [ r20 ]
ld4.sa.d3 r120 = [ r20 ]
ld4.sa.d4 r120 = [ r20 ]
ld4.sa.d5 r120 = [ r20 ]
ld4.sa.d6 r120 = [ r20 ]
ld4.sa.d7 r120 = [ r20 ]
ld8.sa r120 = [ r20 ]
ld8.sa.nt1 r120 = [ r20 ]
ld8.sa.d1 r120 = [ r20 ]
ld8.sa.d2 r120 = [ r20 ]
ld8.sa.nt2 r120 = [ r20 ]
ld8.sa.nta r120 = [ r20 ]
ld8.sa.d3 r120 = [ r20 ]
ld8.sa.d4 r120 = [ r20 ]
ld8.sa.d5 r120 = [ r20 ]
ld8.sa.d6 r120 = [ r20 ]
ld8.sa.d7 r120 = [ r20 ]
ld1.bias r120 = [ r20 ]
ld1.bias.nt1 r120 = [ r20 ]
ld1.bias.d1 r120 = [ r20 ]
ld1.bias.d2 r120 = [ r20 ]
ld1.bias.nt2 r120 = [ r20 ]
ld1.bias.nta r120 = [ r20 ]
ld1.bias.d3 r120 = [ r20 ]
ld1.bias.d4 r120 = [ r20 ]
ld1.bias.d5 r120 = [ r20 ]
ld1.bias.d6 r120 = [ r20 ]
ld1.bias.d7 r120 = [ r20 ]
ld2.bias r120 = [ r20 ]
ld2.bias.nt1 r120 = [ r20 ]
ld2.bias.d1 r120 = [ r20 ]
ld2.bias.d2 r120 = [ r20 ]
ld2.bias.nt2 r120 = [ r20 ]
ld2.bias.nta r120 = [ r20 ]
ld2.bias.d3 r120 = [ r20 ]
ld2.bias.d4 r120 = [ r20 ]
ld2.bias.d5 r120 = [ r20 ]
ld2.bias.d6 r120 = [ r20 ]
ld2.bias.d7 r120 = [ r20 ]
ld4.bias r120 = [ r20 ]
ld4.bias.nt1 r120 = [ r20 ]
ld4.bias.d1 r120 = [ r20 ]
ld4.bias.d2 r120 = [ r20 ]
ld4.bias.nt2 r120 = [ r20 ]
ld4.bias.nta r120 = [ r20 ]
ld4.bias.d3 r120 = [ r20 ]
ld4.bias.d4 r120 = [ r20 ]
ld4.bias.d5 r120 = [ r20 ]
ld4.bias.d6 r120 = [ r20 ]
ld4.bias.d7 r120 = [ r20 ]
ld8.bias r120 = [ r20 ]
ld8.bias.nt1 r120 = [ r20 ]
ld8.bias.d1 r120 = [ r20 ]
ld8.bias.d2 r120 = [ r20 ]
ld8.bias.nt2 r120 = [ r20 ]
ld8.bias.nta r120 = [ r20 ]
ld8.bias.d3 r120 = [ r20 ]
ld8.bias.d4 r120 = [ r20 ]
ld8.bias.d5 r120 = [ r20 ]
ld8.bias.d6 r120 = [ r20 ]
ld8.bias.d7 r120 = [ r20 ]
ld1.acq r120 = [ r20 ]
ld1.acq.nt1 r120 = [ r20 ]
ld1.acq.d1 r120 = [ r20 ]
ld1.acq.d2 r120 = [ r20 ]
ld1.acq.nt2 r120 = [ r20 ]
ld1.acq.nta r120 = [ r20 ]
ld1.acq.d3 r120 = [ r20 ]
ld1.acq.d4 r120 = [ r20 ]
ld1.acq.d5 r120 = [ r20 ]
ld1.acq.d6 r120 = [ r20 ]
ld2.acq r120 = [ r20 ]
ld2.acq.nt1 r120 = [ r20 ]
ld2.acq.d1 r120 = [ r20 ]
ld2.acq.d2 r120 = [ r20 ]
ld2.acq.nt2 r120 = [ r20 ]
ld2.acq.nta r120 = [ r20 ]
ld2.acq.d3 r120 = [ r20 ]
ld2.acq.d4 r120 = [ r20 ]
ld2.acq.d5 r120 = [ r20 ]
ld2.acq.d6 r120 = [ r20 ]
ld2.acq.d7 r120 = [ r20 ]
ld4.acq r120 = [ r20 ]
ld4.acq.nt1 r120 = [ r20 ]
ld4.acq.d1 r120 = [ r20 ]
ld4.acq.d2 r120 = [ r20 ]
ld4.acq.nt2 r120 = [ r20 ]
ld4.acq.nta r120 = [ r20 ]
ld4.acq.d3 r120 = [ r20 ]
ld4.acq.d4 r120 = [ r20 ]
ld4.acq.d5 r120 = [ r20 ]
ld4.acq.d6 r120 = [ r20 ]
ld4.acq.d7 r120 = [ r20 ]
ld8.acq r120 = [ r20 ]
ld8.acq.nt1 r120 = [ r20 ]
ld8.acq.d1 r120 = [ r20 ]
ld8.acq.d2 r120 = [ r20 ]
ld8.acq.nt2 r120 = [ r20 ]
ld8.acq.nta r120 = [ r20 ]
ld8.acq.d3 r120 = [ r20 ]
ld8.acq.d4 r120 = [ r20 ]
ld8.acq.d5 r120 = [ r20 ]
ld8.acq.d6 r120 = [ r20 ]
ld8.acq.d7 r120 = [ r20 ]
ld8.fill r120 = [ r20 ]
ld8.fill.nt1 r120 = [ r20 ]
ld8.fill.d1 r120 = [ r20 ]
ld8.fill.d2 r120 = [ r20 ]
ld8.fill.nt2 r120 = [ r20 ]
ld8.fill.nta r120 = [ r20 ]
ld8.fill.d3 r120 = [ r20 ]
ld8.fill.d4 r120 = [ r20 ]
ld8.fill.d5 r120 = [ r20 ]
ld8.fill.d6 r120 = [ r20 ]
ld8.fill.d7 r120 = [ r20 ]
ld1.c.clr r120 = [ r20 ]
ld1.c.clr.nt1 r120 = [ r20 ]
ld1.c.clr.d1 r120 = [ r20 ]
ld1.c.clr.d2 r120 = [ r20 ]
ld1.c.clr.nt2 r120 = [ r20 ]
ld1.c.clr.nta r120 = [ r20 ]
ld1.c.clr.d3 r120 = [ r20 ]
ld1.c.clr.d4 r120 = [ r20 ]
ld1.c.clr.d5 r120 = [ r20 ]
ld1.c.clr.d6 r120 = [ r20 ]
ld1.c.clr.d7 r120 = [ r20 ]
ld2.c.clr r120 = [ r20 ]
ld2.c.clr.nt1 r120 = [ r20 ]
ld2.c.clr.d1 r120 = [ r20 ]
ld2.c.clr.d2 r120 = [ r20 ]
ld2.c.clr.nt2 r120 = [ r20 ]
ld2.c.clr.nta r120 = [ r20 ]
ld2.c.clr.d3 r120 = [ r20 ]
ld2.c.clr.d4 r120 = [ r20 ]
ld2.c.clr.d5 r120 = [ r20 ]
ld2.c.clr.d6 r120 = [ r20 ]
ld2.c.clr.d7 r120 = [ r20 ]
ld4.c.clr r120 = [ r20 ]
ld4.c.clr.nt1 r120 = [ r20 ]
ld4.c.clr.d1 r120 = [ r20 ]
ld4.c.clr.d2 r120 = [ r20 ]
ld4.c.clr.nt2 r120 = [ r20 ]
ld4.c.clr.nta r120 = [ r20 ]
ld4.c.clr.d3 r120 = [ r20 ]
ld4.c.clr.d4 r120 = [ r20 ]
ld4.c.clr.d5 r120 = [ r20 ]
ld4.c.clr.d6 r120 = [ r20 ]
ld4.c.clr.d7 r120 = [ r20 ]
ld8.c.clr r120 = [ r20 ]
ld8.c.clr.nt1 r120 = [ r20 ]
ld8.c.clr.d1 r120 = [ r20 ]
ld8.c.clr.d2 r120 = [ r20 ]
ld8.c.clr.nt2 r120 = [ r20 ]
ld8.c.clr.nta r120 = [ r20 ]
ld8.c.clr.d3 r120 = [ r20 ]
ld8.c.clr.d4 r120 = [ r20 ]
ld8.c.clr.d5 r120 = [ r20 ]
ld8.c.clr.d6 r120 = [ r20 ]
ld8.c.clr.d7 r120 = [ r20 ]
ld1.c.nc r120 = [ r20 ]
ld1.c.nc.nt1 r120 = [ r20 ]
ld1.c.nc.d1 r120 = [ r20 ]
ld1.c.nc.d2 r120 = [ r20 ]
ld1.c.nc.nt2 r120 = [ r20 ]
ld1.c.nc.nta r120 = [ r20 ]
ld1.c.nc.d3 r120 = [ r20 ]
ld1.c.nc.d4 r120 = [ r20 ]
ld1.c.nc.d5 r120 = [ r20 ]
ld1.c.nc.d7 r120 = [ r20 ]
ld2.c.nc r120 = [ r20 ]
ld2.c.nc.nt1 r120 = [ r20 ]
ld2.c.nc.d1 r120 = [ r20 ]
ld2.c.nc.d2 r120 = [ r20 ]
ld2.c.nc.nt2 r120 = [ r20 ]
ld2.c.nc.nta r120 = [ r20 ]
ld2.c.nc.d3 r120 = [ r20 ]
ld2.c.nc.d4 r120 = [ r20 ]
ld2.c.nc.d5 r120 = [ r20 ]
ld2.c.nc.d6 r120 = [ r20 ]
ld2.c.nc.d7 r120 = [ r20 ]
ld4.c.nc r120 = [ r20 ]
ld4.c.nc.nt1 r120 = [ r20 ]
ld4.c.nc.d1 r120 = [ r20 ]
ld4.c.nc.d2 r120 = [ r20 ]
ld4.c.nc.nt2 r120 = [ r20 ]
ld4.c.nc.nta r120 = [ r20 ]
ld4.c.nc.d3 r120 = [ r20 ]
ld4.c.nc.d4 r120 = [ r20 ]
ld4.c.nc.d5 r120 = [ r20 ]
ld4.c.nc.d6 r120 = [ r20 ]
ld4.c.nc.d7 r120 = [ r20 ]
ld8.c.nc r120 = [ r20 ]
ld8.c.nc.nt1 r120 = [ r20 ]
ld8.c.nc.d1 r120 = [ r20 ]
ld8.c.nc.d2 r120 = [ r20 ]
ld8.c.nc.nt2 r120 = [ r20 ]
ld8.c.nc.nta r120 = [ r20 ]
ld8.c.nc.d3 r120 = [ r20 ]
ld8.c.nc.d4 r120 = [ r20 ]
ld8.c.nc.d5 r120 = [ r20 ]
ld8.c.nc.d6 r120 = [ r20 ]
ld8.c.nc.d7 r120 = [ r20 ]
ld1.c.clr.acq r120 = [ r20 ]
ld1.c.clr.acq.nt1 r120 = [ r20 ]
ld1.c.clr.acq.d1 r120 = [ r20 ]
ld1.c.clr.acq.d2 r120 = [ r20 ]
ld1.c.clr.acq.nt2 r120 = [ r20 ]
ld1.c.clr.acq.nta r120 = [ r20 ]
ld1.c.clr.acq.d3 r120 = [ r20 ]
ld1.c.clr.acq.d4 r120 = [ r20 ]
ld1.c.clr.acq.d5 r120 = [ r20 ]
ld1.c.clr.acq.d6 r120 = [ r20 ]
ld1.c.clr.acq.d7 r120 = [ r20 ]
ld2.c.clr.acq r120 = [ r20 ]
ld2.c.clr.acq.nt1 r120 = [ r20 ]
ld2.c.clr.acq.d1 r120 = [ r20 ]
ld2.c.clr.acq.d2 r120 = [ r20 ]
ld2.c.clr.acq.nt2 r120 = [ r20 ]
ld2.c.clr.acq.d3 r120 = [ r20 ]
ld2.c.clr.acq.d4 r120 = [ r20 ]
ld2.c.clr.acq.d5 r120 = [ r20 ]
ld2.c.clr.acq.d6 r120 = [ r20 ]
ld2.c.clr.acq.d7 r120 = [ r20 ]
ld4.c.clr.acq r120 = [ r20 ]
ld4.c.clr.acq.nt1 r120 = [ r20 ]
ld4.c.clr.acq.d1 r120 = [ r20 ]
ld4.c.clr.acq.d2 r120 = [ r20 ]
ld4.c.clr.acq.nt2 r120 = [ r20 ]
ld4.c.clr.acq.nta r120 = [ r20 ]
ld4.c.clr.acq.d3 r120 = [ r20 ]
ld4.c.clr.acq.d4 r120 = [ r20 ]
ld4.c.clr.acq.d5 r120 = [ r20 ]
ld4.c.clr.acq.d6 r120 = [ r20 ]
ld4.c.clr.acq.d7 r120 = [ r20 ]
ld8.c.clr.acq r120 = [ r20 ]
ld8.c.clr.acq.nt1 r120 = [ r20 ]
ld8.c.clr.acq.d1 r120 = [ r20 ]
ld8.c.clr.acq.d2 r120 = [ r20 ]
ld8.c.clr.acq.nt2 r120 = [ r20 ]
ld8.c.clr.acq.nta r120 = [ r20 ]
ld8.c.clr.acq.d3 r120 = [ r20 ]
ld8.c.clr.acq.d4 r120 = [ r20 ]
ld8.c.clr.acq.d5 r120 = [ r20 ]
ld8.c.clr.acq.d6 r120 = [ r20 ]
ld8.c.clr.acq.d7 r120 = [ r20 ]
ld16 r120 = [ r20 ]
ld16 r120 = [ r20 ]
ld16.nt1 r120 = [ r20 ]
ld16.d1 r120 = [ r20 ]
ld16.d2 r120 = [ r20 ]
ld16.nt2 r120 = [ r20 ]
ld16.nt1 r120 = [ r20 ]
ld16.d1 r120 = [ r20 ]
ld16.d2 r120 = [ r20 ]
ld16.nt2 r120 = [ r20 ]
ld16.nta r120 = [ r20 ]
ld16.d3 r120 = [ r20 ]
ld16.d4 r120 = [ r20 ]
ld16.d5 r120 = [ r20 ]
ld16.d6 r120 = [ r20 ]
ld16.d7 r120 = [ r20 ]
ld16.nta r120 = [ r20 ]
ld16.d3 r120 = [ r20 ]
ld16.d4 r120 = [ r20 ]
ld16.d5 r120 = [ r20 ]
ld16.d6 r120 = [ r20 ]
ld16.d7 r120 = [ r20 ]
ld16.acq r120 = [ r20 ]
ld16.acq r120, ar.csd = [ r20 ]
ld16.acq.nt1 r120 = [ r20 ]
ld16.acq.d1 r120 = [ r20 ]
ld16.acq.d2 r120, ar.csd = [ r20 ]
ld16.acq.nt2 r120 = [ r20 ]
ld16.acq.nt1 r120 = [ r20 ]
ld16.acq.d1 r120 = [ r20 ]
ld16.acq.d2 r120 = [ r20 ]
ld16.acq.nt2 r120 = [ r20 ]
ld16.acq.nta r120 = [ r20 ]
ld16.acq.d3 r120 = [ r20 ]
ld16.acq.d4 r120 = [ r20 ]
ld16.acq.d5 r120 = [ r20 ]
ld16.acq.d6 r120 = [ r20 ]
ld16.acq.d7 r120 = [ r20 ]
ld16.acq.nta r120, ar.csd = [ r20 ]
ld16.acq.d3 r120 = [ r20 ]
ld16.acq.d4 r120 = [ r20 ]
ld16.acq.d5 r120 = [ r20 ]
ld16.acq.d6 r120 = [ r20 ]
ld16.acq.d7 r120 = [ r20 ]
/* Pseudo-op that generates ldxmov relocation. */
ld8.mov r120 = [ r20 ], AAAAA
AAAAA:
|
stsp/binutils-ia16
| 1,704
|
gas/testsuite/gas/ia64/reloc.s
|
.global esym
.section .rodata.4, "a", @progbits
.section .rodata.8, "a", @progbits
.text
_start:
adds r1 = esym, r0
mov r2 = esym
movl r3 = esym
.xdata4 .rodata.4, esym
.xdata8 .rodata.8, esym
mov r2 = @gprel(esym)
movl r3 = @gprel(esym)
.xdata4 .rodata.4, @gprel(esym)
.xdata8 .rodata.8, @gprel(esym)
mov r2 = @ltoff(esym)
movl r3 = @ltoff(esym)
mov r2 = @pltoff(esym)
movl r3 = @pltoff(esym)
.xdata8 .rodata.8, @pltoff(esym)
movl r3 = @fptr(esym)
.xdata4 .rodata.4, @fptr(esym)
.xdata8 .rodata.8, @fptr(esym)
brl.call.sptk b1 = esym
br.call.sptk b2 = esym
chk.s r0, esym
fchkf esym
.xdata4 .rodata.4, @pcrel(esym)
.xdata8 .rodata.8, @pcrel(esym)
mov r2 = @ltoff(@fptr(esym))
movl r3 = @ltoff(@fptr(esym))
.xdata4 .rodata.4, @ltoff(@fptr(esym))
.xdata8 .rodata.8, @ltoff(@fptr(esym))
.xdata4 .rodata.4, @segrel(esym)
.xdata8 .rodata.8, @segrel(esym)
.xdata4 .rodata.4, @secrel(esym)
.xdata8 .rodata.8, @secrel(esym)
// REL32 only in executables
// REL64 only in executables
.xdata4 .rodata.4, @ltv(esym)
.xdata8 .rodata.8, @ltv(esym)
//todo PCREL21BI
mov r2 = @pcrel(esym)
movl r3 = @pcrel(esym)
.xdata16 .rodata.8, @iplt(esym)
// COPY only in executables
//todo movl r3 = -esym
mov r2 = @ltoffx(esym)
ld8.mov r3 = [r2], esym
adds r1 = @tprel(esym), r0
mov r2 = @tprel(esym)
movl r3 = @tprel(esym)
.xdata8 .rodata.8, @tprel(esym)
mov r2 = @ltoff(@tprel(esym))
.xdata8 .rodata.8, @dtpmod(esym)
mov r2 = @ltoff(@dtpmod(esym))
adds r1 = @dtprel(esym), r0
mov r2 = @dtprel(esym)
movl r3 = @dtprel(esym)
.xdata4 .rodata.4, @dtprel(esym)
.xdata8 .rodata.8, @dtprel(esym)
mov r2 = @ltoff(@dtprel(esym))
|
stsp/binutils-ia16
| 1,381
|
gas/testsuite/gas/ia64/reloc-bad.s
|
.psr abi64
.global esym
.section .rodata, "a", @progbits
.text
_start:
adds r1 = @gprel(esym), r0
adds r1 = @ltoff(esym), r0
.xdata4 .rodata, @ltoff(esym)
.xdata8 .rodata, @ltoff(esym)
adds r1 = @pltoff(esym), r0
.xdata4 .rodata, @pltoff(esym)
adds r1 = @fptr(esym), r0
mov r2 = @fptr(esym)
adds r1 = @pcrel(esym), r0
adds r1 = @ltoff(@fptr(esym)), r0
adds r1 = @segrel(esym), r0
mov r2 = @segrel(esym)
movl r3 = @segrel(esym)
adds r1 = @secrel(esym), r0
mov r2 = @secrel(esym)
movl r3 = @secrel(esym)
adds r1 = @ltv(esym), r0
mov r2 = @ltv(esym)
movl r3 = @ltv(esym)
adds r1 = @iplt(esym), r0
mov r2 = @iplt(esym)
movl r3 = @iplt(esym)
.xdata4 .rodata, @iplt(esym)
.xdata8 .rodata, @iplt(esym)
adds r1 = @ltoffx(esym), r0
.xdata4 .rodata, @tprel(esym)
adds r1 = @ltoff(@tprel(esym)), r0
movl r3 = @ltoff(@tprel(esym))
.xdata4 .rodata, @ltoff(@tprel(esym))
.xdata8 .rodata, @ltoff(@tprel(esym))
adds r1 = @dtpmod(esym), r0
mov r2 = @dtpmod(esym)
movl r3 = @dtpmod(esym)
.xdata4 .rodata, @dtpmod(esym)
adds r1 = @ltoff(@dtpmod(esym)), r0
movl r3 = @ltoff(@dtpmod(esym))
.xdata4 .rodata, @ltoff(@tprel(esym))
.xdata8 .rodata, @ltoff(@tprel(esym))
adds r1 = @ltoff(@dtprel(esym)), r0
movl r3 = @ltoff(@dtprel(esym))
.xdata4 .rodata, @ltoff(@dtprel(esym))
.xdata8 .rodata, @ltoff(@dtprel(esym))
|
stsp/binutils-ia16
| 2,474
|
gas/testsuite/gas/ia64/invalid-ar.s
|
// AR 0 to AR 47 can be accessed only by M unit.
mov.i r1 = ar0
mov.i r1 = ar1
mov.i r1 = ar2
mov.i r1 = ar3
mov.i r1 = ar4
mov.i r1 = ar5
mov.i r1 = ar6
mov.i r1 = ar7
mov.i r1 = ar8
mov.i r1 = ar9
mov.i r1 = ar10
mov.i r1 = ar11
mov.i r1 = ar12
mov.i r1 = ar13
mov.i r1 = ar14
mov.i r1 = ar15
mov.i r1 = ar16
mov.i r1 = ar17
mov.i r1 = ar18
mov.i r1 = ar19
mov.i r1 = ar20
mov.i r1 = ar21
mov.i r1 = ar22
mov.i r1 = ar23
mov.i r1 = ar24
mov.i r1 = ar25
mov.i r1 = ar26
mov.i r1 = ar27
mov.i r1 = ar28
mov.i r1 = ar29
mov.i r1 = ar30
mov.i r1 = ar31
mov.i r1 = ar32
mov.i r1 = ar33
mov.i r1 = ar34
mov.i r1 = ar35
mov.i r1 = ar36
mov.i r1 = ar37
mov.i r1 = ar38
mov.i r1 = ar39
mov.i r1 = ar40
mov.i r1 = ar41
mov.i r1 = ar42
mov.i r1 = ar43
mov.i r1 = ar44
mov.i r1 = ar45
mov.i r1 = ar46
mov.i r1 = ar47
// AR 48 to 63 can be accessed by I or M units.
// AR 64 to AR 111 can be accessed only by I unit.
mov.m r1 = ar64
mov.m r1 = ar65
mov.m r1 = ar66
mov.m r1 = ar67
mov.m r1 = ar68
mov.m r1 = ar69
mov.m r1 = ar70
mov.m r1 = ar71
mov.m r1 = ar72
mov.m r1 = ar73
mov.m r1 = ar74
mov.m r1 = ar75
mov.m r1 = ar76
mov.m r1 = ar77
mov.m r1 = ar78
mov.m r1 = ar79
mov.m r1 = ar80
mov.m r1 = ar81
mov.m r1 = ar82
mov.m r1 = ar83
mov.m r1 = ar84
mov.m r1 = ar85
mov.m r1 = ar86
mov.m r1 = ar87
mov.m r1 = ar88
mov.m r1 = ar89
mov.m r1 = ar90
mov.m r1 = ar91
mov.m r1 = ar92
mov.m r1 = ar93
mov.m r1 = ar94
mov.m r1 = ar95
mov.m r1 = ar96
mov.m r1 = ar97
mov.m r1 = ar98
mov.m r1 = ar99
mov.m r1 = ar100
mov.m r1 = ar101
mov.m r1 = ar102
mov.m r1 = ar103
mov.m r1 = ar104
mov.m r1 = ar105
mov.m r1 = ar106
mov.m r1 = ar107
mov.m r1 = ar108
mov.m r1 = ar109
mov.m r1 = ar110
mov.m r1 = ar111
// AR 112 to 127 can be accessed by I or M units.
// AR K0 to AR ITC can be accessed only by M unit.
mov.i r1 = ar.k0
mov.i r1 = ar.k1
mov.i r1 = ar.k2
mov.i r1 = ar.k3
mov.i r1 = ar.k4
mov.i r1 = ar.k5
mov.i r1 = ar.k6
mov.i r1 = ar.k7
mov.i r1 = ar.rsc
mov.i r1 = ar.bsp
mov.i r1 = ar.bspstore
mov.i r1 = ar.rnat
mov.i r1 = ar.fcr
mov.i r1 = ar.eflag
mov.i r1 = ar.csd
mov.i r1 = ar.ssd
mov.i r1 = ar.cflg
mov.i r1 = ar.fsr
mov.i r1 = ar.fir
mov.i r1 = ar.fdr
mov.i r1 = ar.ccv
mov.i r1 = ar.unat
mov.i r1 = ar.fpsr
mov.i r1 = ar.itc
mov.i r1 = ar.ruc
// AR PFS, LC and EC can be accessed only by I unit.
mov.m r1 = ar.pfs
mov.m r1 = ar.lc
mov.m r1 = ar.ec
|
stsp/binutils-ia16
| 4,746
|
gas/testsuite/gas/ia64/opc-i.s
|
.text
.type _start,@function
_start:
pmpyshr2 r4 = r5, r6, 0
pmpyshr2.u r4 = r5, r6, 16
pmpy2.r r4 = r5, r6
pmpy2.l r4 = r5, r6
mix1.r r4 = r5, r6
mix2.r r4 = r5, r6
mix4.r r4 = r5, r6
mix1.l r4 = r5, r6
mix2.l r4 = r5, r6
mix4.l r4 = r5, r6
pack2.uss r4 = r5, r6
pack2.sss r4 = r5, r6
pack4.sss r4 = r5, r6
unpack1.h r4 = r5, r6
unpack2.h r4 = r5, r6
unpack4.h r4 = r5, r6
unpack1.l r4 = r5, r6
unpack2.l r4 = r5, r6
unpack4.l r4 = r5, r6
pmin1.u r4 = r5, r6
pmax1.u r4 = r5, r6
pmin2 r4 = r5, r6
pmax2 r4 = r5, r6
psad1 r4 = r5, r6
mux1 r4 = r5, @rev
mux1 r4 = r5, @mix
mux1 r4 = r5, @shuf
mux1 r4 = r5, @alt
mux1 r4 = r5, @brcst
mux2 r4 = r5, 0
mux2 r4 = r5, 0xff
mux2 r4 = r5, 0xaa
pshr2 r4 = r5, r6
pshr2 r4 = r5, 0
pshr2 r4 = r5, 8
pshr2 r4 = r5, 31
pshr4 r4 = r5, r6
pshr4 r4 = r5, 0
pshr4 r4 = r5, 8
pshr4 r4 = r5, 31
pshr2.u r4 = r5, r6
pshr2.u r4 = r5, 0
pshr2.u r4 = r5, 8
pshr2.u r4 = r5, 31
pshr4.u r4 = r5, r6
pshr4.u r4 = r5, 0
pshr4.u r4 = r5, 8
pshr4.u r4 = r5, 31
shr r4 = r5, r6
shr.u r4 = r5, r6
pshl2 r4 = r5, r6
pshl2 r4 = r5, 0
pshl2 r4 = r5, 8
pshl2 r4 = r5, 31
pshl4 r4 = r5, r6
pshl4 r4 = r5, 0
pshl4 r4 = r5, 8
pshl4 r4 = r5, 31
shl r4 = r5, r6
popcnt r4 = r5
shrp r4 = r5, r6, 0
shrp r4 = r5, r6, 12
shrp r4 = r5, r6, 63
extr r4 = r5, 0, 16
extr r4 = r5, 0, 63
extr r4 = r5, 10, 40
extr.u r4 = r5, 0, 16
extr.u r4 = r5, 0, 63
extr.u r4 = r5, 10, 40
dep.z r4 = r5, 0, 16
dep.z r4 = r5, 0, 63
dep.z r4 = r5, 10, 40
dep.z r4 = 0, 0, 16
dep.z r4 = 127, 0, 63
dep.z r4 = -128, 5, 50
dep.z r4 = 0x55, 10, 40
dep r4 = 0, r5, 0, 16
dep r4 = -1, r5, 0, 63
// Insert padding NOPs to force the same template selection as IAS.
nop.m 0
nop.f 0
dep r4 = r5, r6, 10, 7
movl r4 = 0
movl r4 = 0xffffffffffffffff
movl r4 = 0x1234567890abcdef
break.i 0
break.i 0x1fffff
nop.i 0
nop.i 0x1fffff
chk.s.i r4, _start
mov r4 = b0
mov b0 = r4
mov pr = r4, 0
mov pr = r4, 0x1234
mov pr = r4, 0x1ffff
mov pr.rot = 0
// ??? This was originally 0x3ffffff, but that generates an assembler warning
// that the testsuite infrastructure isn't set up to ignore.
mov pr.rot = 0x3ff0000
mov pr.rot = -0x4000000
zxt1 r4 = r5
zxt2 r4 = r5
zxt4 r4 = r5
sxt1 r4 = r5
sxt2 r4 = r5
sxt4 r4 = r5
czx1.l r4 = r5
czx2.l r4 = r5
czx1.r r4 = r5
czx2.r r4 = r5
tbit.z p2, p3 = r4, 0
tbit.z.unc p2, p3 = r4, 1
tbit.z.and p2, p3 = r4, 2
tbit.z.or p2, p3 = r4, 3
tbit.z.or.andcm p2, p3 = r4, 4
tbit.z.orcm p2, p3 = r4, 5
tbit.z.andcm p2, p3 = r4, 6
tbit.z.and.orcm p2, p3 = r4, 7
tbit.nz p2, p3 = r4, 8
tbit.nz.unc p2, p3 = r4, 9
tbit.nz.and p2, p3 = r4, 10
tbit.nz.or p2, p3 = r4, 11
tbit.nz.or.andcm p2, p3 = r4, 12
tbit.nz.orcm p2, p3 = r4, 13
tbit.nz.andcm p2, p3 = r4, 14
tbit.nz.and.orcm p2, p3 = r4, 15
tnat.z p2, p3 = r4
tnat.z.unc p2, p3 = r4
tnat.z.and p2, p3 = r4
tnat.z.or p2, p3 = r4
tnat.z.or.andcm p2, p3 = r4
tnat.z.orcm p2, p3 = r4
tnat.z.andcm p2, p3 = r4
tnat.z.and.orcm p2, p3 = r4
tnat.nz p2, p3 = r4
tnat.nz.unc p2, p3 = r4
tnat.nz.and p2, p3 = r4
tnat.nz.or p2, p3 = r4
tnat.nz.or.andcm p2, p3 = r4
tnat.nz.orcm p2, p3 = r4
tnat.nz.andcm p2, p3 = r4
tnat.nz.and.orcm p2, p3 = r4
mov b3 = r4, .L1
mov.imp b3 = r4, .L1
.space 240
.L1:
mov.sptk b3 = r4, .L2
mov.sptk.imp b3 = r4, .L2
.space 240
.L2:
mov.dptk b3 = r4, .L3
mov.dptk.imp b3 = r4, .L3
.space 240
.L3:
mov.ret b3 = r4, .L4
mov.ret.imp b3 = r4, .L4
.space 240
.L4:
mov.ret.sptk b3 = r4, .L5
mov.ret.sptk.imp b3 = r4, .L5
.space 240
.L5:
mov.ret.dptk b3 = r4, .L6
mov.ret.dptk.imp b3 = r4, .L6
.space 240
.L6:
# instructions added by SDM2.1:
hint @pause
hint.i 0
hint.i @pause
hint.i 0x1fffff
(p7) hint @pause
(p7) hint.i 0
(p7) hint.i @pause
(p7) hint.i 0x1fffff
(p7) hint @pause
(p7) hint.i 0
(p7) hint.i @pause
(p7) hint.i 0x1fffff
# instructions added by SDM2.2:
tf.z p2, p3 = 39
tf.z.unc p2, p3 = 39
tf.z.and p2, p3 = 39
tf.z.or p2, p3 = 39
tf.z.or.andcm p2, p3 = 39
tf.z.orcm p2, p3 = 39
tf.z.andcm p2, p3 = 39
tf.z.and.orcm p2, p3 = 39
tf.nz p2, p3 = 39
tf.nz.unc p2, p3 = 39
tf.nz.and p2, p3 = 39
tf.nz.or p2, p3 = 39
tf.nz.or.andcm p2, p3 = 39
tf.nz.orcm p2, p3 = 39
tf.nz.andcm p2, p3 = 39
tf.nz.and.orcm p2, p3 = 39
(p7) tf.z p2, p3 = 39
(p7) tf.z.unc p2, p3 = 39
(p7) tf.z.and p2, p3 = 39
(p7) tf.z.or p2, p3 = 39
(p7) tf.z.or.andcm p2, p3 = 39
(p7) tf.z.orcm p2, p3 = 39
(p7) tf.z.andcm p2, p3 = 39
(p7) tf.z.and.orcm p2, p3 = 39
(p7) tf.nz p2, p3 = 39
(p7) tf.nz.unc p2, p3 = 39
(p7) tf.nz.and p2, p3 = 39
(p7) tf.nz.or p2, p3 = 39
(p7) tf.nz.or.andcm p2, p3 = 39
(p7) tf.nz.orcm p2, p3 = 39
(p7) tf.nz.andcm p2, p3 = 39
(p7) tf.nz.and.orcm p2, p3 = 39
|
stsp/binutils-ia16
| 13,085
|
gas/testsuite/gas/ia64/opc-f.s
|
.text
.type _start,@function
_start:
fma f4 = f5, f6, f7
fma.s0 f4 = f5, f6, f7
fma.s1 f4 = f5, f6, f7
fma.s2 f4 = f5, f6, f7
fma.s3 f4 = f5, f6, f7
fma.s f4 = f5, f6, f7
fma.s.s0 f4 = f5, f6, f7
fma.s.s1 f4 = f5, f6, f7
fma.s.s2 f4 = f5, f6, f7
fma.s.s3 f4 = f5, f6, f7
fma.d f4 = f5, f6, f7
fma.d.s0 f4 = f5, f6, f7
fma.d.s1 f4 = f5, f6, f7
fma.d.s2 f4 = f5, f6, f7
fma.d.s3 f4 = f5, f6, f7
fpma f4 = f5, f6, f7
fpma.s0 f4 = f5, f6, f7
fpma.s1 f4 = f5, f6, f7
fpma.s2 f4 = f5, f6, f7
fpma.s3 f4 = f5, f6, f7
fms f4 = f5, f6, f7
fms.s0 f4 = f5, f6, f7
fms.s1 f4 = f5, f6, f7
fms.s2 f4 = f5, f6, f7
fms.s3 f4 = f5, f6, f7
fms.s f4 = f5, f6, f7
fms.s.s0 f4 = f5, f6, f7
fms.s.s1 f4 = f5, f6, f7
fms.s.s2 f4 = f5, f6, f7
fms.s.s3 f4 = f5, f6, f7
fms.d f4 = f5, f6, f7
fms.d.s0 f4 = f5, f6, f7
fms.d.s1 f4 = f5, f6, f7
fms.d.s2 f4 = f5, f6, f7
fms.d.s3 f4 = f5, f6, f7
fpms f4 = f5, f6, f7
fpms.s0 f4 = f5, f6, f7
fpms.s1 f4 = f5, f6, f7
fpms.s2 f4 = f5, f6, f7
fpms.s3 f4 = f5, f6, f7
fnma f4 = f5, f6, f7
fnma.s0 f4 = f5, f6, f7
fnma.s1 f4 = f5, f6, f7
fnma.s2 f4 = f5, f6, f7
fnma.s3 f4 = f5, f6, f7
fnma.s f4 = f5, f6, f7
fnma.s.s0 f4 = f5, f6, f7
fnma.s.s1 f4 = f5, f6, f7
fnma.s.s2 f4 = f5, f6, f7
fnma.s.s3 f4 = f5, f6, f7
fnma.d f4 = f5, f6, f7
fnma.d.s0 f4 = f5, f6, f7
fnma.d.s1 f4 = f5, f6, f7
fnma.d.s2 f4 = f5, f6, f7
fnma.d.s3 f4 = f5, f6, f7
fpnma f4 = f5, f6, f7
fpnma.s0 f4 = f5, f6, f7
fpnma.s1 f4 = f5, f6, f7
fpnma.s2 f4 = f5, f6, f7
fpnma.s3 f4 = f5, f6, f7
fmpy f4 = f5, f6
fmpy.s0 f4 = f5, f6
fmpy.s1 f4 = f5, f6
fmpy.s2 f4 = f5, f6
fmpy.s3 f4 = f5, f6
fmpy.s f4 = f5, f6
fmpy.s.s0 f4 = f5, f6
fmpy.s.s1 f4 = f5, f6
fmpy.s.s2 f4 = f5, f6
fmpy.s.s3 f4 = f5, f6
fmpy.d f4 = f5, f6
fmpy.d.s0 f4 = f5, f6
fmpy.d.s1 f4 = f5, f6
fmpy.d.s2 f4 = f5, f6
fmpy.d.s3 f4 = f5, f6
fpmpy f4 = f5, f6
fpmpy.s0 f4 = f5, f6
fpmpy.s1 f4 = f5, f6
fpmpy.s2 f4 = f5, f6
fpmpy.s3 f4 = f5, f6
fadd f4 = f5, f6
fadd.s0 f4 = f5, f6
fadd.s1 f4 = f5, f6
fadd.s2 f4 = f5, f6
fadd.s3 f4 = f5, f6
fadd.s f4 = f5, f6
fadd.s.s0 f4 = f5, f6
fadd.s.s1 f4 = f5, f6
fadd.s.s2 f4 = f5, f6
fadd.s.s3 f4 = f5, f6
fadd.d f4 = f5, f6
fadd.d.s0 f4 = f5, f6
fadd.d.s1 f4 = f5, f6
fadd.d.s2 f4 = f5, f6
fadd.d.s3 f4 = f5, f6
fsub f4 = f5, f6
fsub.s0 f4 = f5, f6
fsub.s1 f4 = f5, f6
fsub.s2 f4 = f5, f6
fsub.s3 f4 = f5, f6
fsub.s f4 = f5, f6
fsub.s.s0 f4 = f5, f6
fsub.s.s1 f4 = f5, f6
fsub.s.s2 f4 = f5, f6
fsub.s.s3 f4 = f5, f6
fsub.d f4 = f5, f6
fsub.d.s0 f4 = f5, f6
fsub.d.s1 f4 = f5, f6
fsub.d.s2 f4 = f5, f6
fsub.d.s3 f4 = f5, f6
fnmpy f4 = f5, f6
fnmpy.s0 f4 = f5, f6
fnmpy.s1 f4 = f5, f6
fnmpy.s2 f4 = f5, f6
fnmpy.s3 f4 = f5, f6
fnmpy.s f4 = f5, f6
fnmpy.s.s0 f4 = f5, f6
fnmpy.s.s1 f4 = f5, f6
fnmpy.s.s2 f4 = f5, f6
fnmpy.s.s3 f4 = f5, f6
fnmpy.d f4 = f5, f6
fnmpy.d.s0 f4 = f5, f6
fnmpy.d.s1 f4 = f5, f6
fnmpy.d.s2 f4 = f5, f6
fnmpy.d.s3 f4 = f5, f6
fpnmpy f4 = f5, f6
fpnmpy.s0 f4 = f5, f6
fpnmpy.s1 f4 = f5, f6
fpnmpy.s2 f4 = f5, f6
fpnmpy.s3 f4 = f5, f6
fnorm f4 = f5
fnorm.s0 f4 = f5
fnorm.s1 f4 = f5
fnorm.s2 f4 = f5
fnorm.s3 f4 = f5
fnorm.s f4 = f5
fnorm.s.s0 f4 = f5
fnorm.s.s1 f4 = f5
fnorm.s.s2 f4 = f5
fnorm.s.s3 f4 = f5
fnorm.d f4 = f5
fnorm.d.s0 f4 = f5
fnorm.d.s1 f4 = f5
fnorm.d.s2 f4 = f5
fnorm.d.s3 f4 = f5
xma.l f4 = f5, f6, f7
xma.lu f4 = f5, f6, f7
xma.h f4 = f5, f6, f7
xma.hu f4 = f5, f6, f7
xmpy.l f4 = f5, f6
xmpy.lu f4 = f5, f6
xmpy.h f4 = f5, f6
xmpy.hu f4 = f5, f6
fselect f4 = f5, f6, f7
fcmp.eq p3, p4 = f4, f5
fcmp.eq.s0 p3, p4 = f4, f5
fcmp.eq.s1 p3, p4 = f4, f5
fcmp.eq.s2 p3, p4 = f4, f5
fcmp.eq.s3 p3, p4 = f4, f5
fcmp.eq.unc p3, p4 = f4, f5
fcmp.eq.unc.s0 p3, p4 = f4, f5
fcmp.eq.unc.s1 p3, p4 = f4, f5
fcmp.eq.unc.s2 p3, p4 = f4, f5
fcmp.eq.unc.s3 p3, p4 = f4, f5
fcmp.lt p3, p4 = f4, f5
fcmp.lt.s0 p3, p4 = f4, f5
fcmp.lt.s1 p3, p4 = f4, f5
fcmp.lt.s2 p3, p4 = f4, f5
fcmp.lt.s3 p3, p4 = f4, f5
fcmp.lt.unc p3, p4 = f4, f5
fcmp.lt.unc.s0 p3, p4 = f4, f5
fcmp.lt.unc.s1 p3, p4 = f4, f5
fcmp.lt.unc.s2 p3, p4 = f4, f5
fcmp.lt.unc.s3 p3, p4 = f4, f5
fcmp.le p3, p4 = f4, f5
fcmp.le.s0 p3, p4 = f4, f5
fcmp.le.s1 p3, p4 = f4, f5
fcmp.le.s2 p3, p4 = f4, f5
fcmp.le.s3 p3, p4 = f4, f5
fcmp.le.unc p3, p4 = f4, f5
fcmp.le.unc.s0 p3, p4 = f4, f5
fcmp.le.unc.s1 p3, p4 = f4, f5
fcmp.le.unc.s2 p3, p4 = f4, f5
fcmp.le.unc.s3 p3, p4 = f4, f5
fcmp.unord p3, p4 = f4, f5
fcmp.unord.s0 p3, p4 = f4, f5
fcmp.unord.s1 p3, p4 = f4, f5
fcmp.unord.s2 p3, p4 = f4, f5
fcmp.unord.s3 p3, p4 = f4, f5
fcmp.unord.unc p3, p4 = f4, f5
fcmp.unord.unc.s0 p3, p4 = f4, f5
fcmp.unord.unc.s1 p3, p4 = f4, f5
fcmp.unord.unc.s2 p3, p4 = f4, f5
fcmp.unord.unc.s3 p3, p4 = f4, f5
fcmp.gt p3, p4 = f4, f5
fcmp.gt.s0 p3, p4 = f4, f5
fcmp.gt.s1 p3, p4 = f4, f5
fcmp.gt.s2 p3, p4 = f4, f5
fcmp.gt.s3 p3, p4 = f4, f5
fcmp.gt.unc p3, p4 = f4, f5
fcmp.gt.unc.s0 p3, p4 = f4, f5
fcmp.gt.unc.s1 p3, p4 = f4, f5
fcmp.gt.unc.s2 p3, p4 = f4, f5
fcmp.gt.unc.s3 p3, p4 = f4, f5
fcmp.ge p3, p4 = f4, f5
fcmp.ge.s0 p3, p4 = f4, f5
fcmp.ge.s1 p3, p4 = f4, f5
fcmp.ge.s2 p3, p4 = f4, f5
fcmp.ge.s3 p3, p4 = f4, f5
fcmp.ge.unc p3, p4 = f4, f5
fcmp.ge.unc.s0 p3, p4 = f4, f5
fcmp.ge.unc.s1 p3, p4 = f4, f5
fcmp.ge.unc.s2 p3, p4 = f4, f5
fcmp.ge.unc.s3 p3, p4 = f4, f5
fcmp.neq p3, p4 = f4, f5
fcmp.neq.s0 p3, p4 = f4, f5
fcmp.neq.s1 p3, p4 = f4, f5
fcmp.neq.s2 p3, p4 = f4, f5
fcmp.neq.s3 p3, p4 = f4, f5
fcmp.neq.unc p3, p4 = f4, f5
fcmp.neq.unc.s0 p3, p4 = f4, f5
fcmp.neq.unc.s1 p3, p4 = f4, f5
fcmp.neq.unc.s2 p3, p4 = f4, f5
fcmp.neq.unc.s3 p3, p4 = f4, f5
fcmp.nlt p3, p4 = f4, f5
fcmp.nlt.s0 p3, p4 = f4, f5
fcmp.nlt.s1 p3, p4 = f4, f5
fcmp.nlt.s2 p3, p4 = f4, f5
fcmp.nlt.s3 p3, p4 = f4, f5
fcmp.nlt.unc p3, p4 = f4, f5
fcmp.nlt.unc.s0 p3, p4 = f4, f5
fcmp.nlt.unc.s1 p3, p4 = f4, f5
fcmp.nlt.unc.s2 p3, p4 = f4, f5
fcmp.nlt.unc.s3 p3, p4 = f4, f5
fcmp.nle p3, p4 = f4, f5
fcmp.nle.s0 p3, p4 = f4, f5
fcmp.nle.s1 p3, p4 = f4, f5
fcmp.nle.s2 p3, p4 = f4, f5
fcmp.nle.s3 p3, p4 = f4, f5
fcmp.nle.unc p3, p4 = f4, f5
fcmp.nle.unc.s0 p3, p4 = f4, f5
fcmp.nle.unc.s1 p3, p4 = f4, f5
fcmp.nle.unc.s2 p3, p4 = f4, f5
fcmp.nle.unc.s3 p3, p4 = f4, f5
fcmp.ngt p3, p4 = f4, f5
fcmp.ngt.s0 p3, p4 = f4, f5
fcmp.ngt.s1 p3, p4 = f4, f5
fcmp.ngt.s2 p3, p4 = f4, f5
fcmp.ngt.s3 p3, p4 = f4, f5
fcmp.ngt.unc p3, p4 = f4, f5
fcmp.ngt.unc.s0 p3, p4 = f4, f5
fcmp.ngt.unc.s1 p3, p4 = f4, f5
fcmp.ngt.unc.s2 p3, p4 = f4, f5
fcmp.ngt.unc.s3 p3, p4 = f4, f5
fcmp.nge p3, p4 = f4, f5
fcmp.nge.s0 p3, p4 = f4, f5
fcmp.nge.s1 p3, p4 = f4, f5
fcmp.nge.s2 p3, p4 = f4, f5
fcmp.nge.s3 p3, p4 = f4, f5
fcmp.nge.unc p3, p4 = f4, f5
fcmp.nge.unc.s0 p3, p4 = f4, f5
fcmp.nge.unc.s1 p3, p4 = f4, f5
fcmp.nge.unc.s2 p3, p4 = f4, f5
fcmp.nge.unc.s3 p3, p4 = f4, f5
fcmp.ord p3, p4 = f4, f5
fcmp.ord.s0 p3, p4 = f4, f5
fcmp.ord.s1 p3, p4 = f4, f5
fcmp.ord.s2 p3, p4 = f4, f5
fcmp.ord.s3 p3, p4 = f4, f5
fcmp.ord.unc p3, p4 = f4, f5
fcmp.ord.unc.s0 p3, p4 = f4, f5
fcmp.ord.unc.s1 p3, p4 = f4, f5
fcmp.ord.unc.s2 p3, p4 = f4, f5
fcmp.ord.unc.s3 p3, p4 = f4, f5
fclass.m p3, p4 = f4, @nat
fclass.nm p3, p4 = f4, @nat
fclass.m p3, p4 = f4, @qnan
fclass.nm p3, p4 = f4, @qnan
fclass.m p3, p4 = f4, @snan
fclass.nm p3, p4 = f4, @snan
fclass.m p3, p4 = f4, @pos
fclass.nm p3, p4 = f4, @pos
fclass.m p3, p4 = f4, @neg
fclass.nm p3, p4 = f4, @neg
fclass.m p3, p4 = f4, @unorm
fclass.nm p3, p4 = f4, @unorm
fclass.m p3, p4 = f4, @norm
fclass.nm p3, p4 = f4, @norm
fclass.m p3, p4 = f4, @inf
fclass.nm p3, p4 = f4, @inf
fclass.m p3, p4 = f4, 0x1ff
fclass.nm p3, p4 = f4, 0x1ff
fclass.m.unc p3, p4 = f4, @nat
fclass.nm.unc p3, p4 = f4, @nat
fclass.m.unc p3, p4 = f4, @qnan
fclass.nm.unc p3, p4 = f4, @qnan
fclass.m.unc p3, p4 = f4, @snan
fclass.nm.unc p3, p4 = f4, @snan
fclass.m.unc p3, p4 = f4, @pos
fclass.nm.unc p3, p4 = f4, @pos
fclass.m.unc p3, p4 = f4, @neg
fclass.nm.unc p3, p4 = f4, @neg
fclass.m.unc p3, p4 = f4, @unorm
fclass.nm.unc p3, p4 = f4, @unorm
fclass.m.unc p3, p4 = f4, @norm
fclass.nm.unc p3, p4 = f4, @norm
fclass.m.unc p3, p4 = f4, @inf
fclass.nm.unc p3, p4 = f4, @inf
fclass.m.unc p3, p4 = f4, 0x1ff
fclass.nm.unc p3, p4 = f4, 0x1ff
frcpa f4, p5 = f6, f7
frcpa.s0 f4, p5 = f6, f7
frcpa.s1 f4, p5 = f6, f7
frcpa.s2 f4, p5 = f6, f7
frcpa.s3 f4, p5 = f6, f7
fprcpa f4, p5 = f6, f7
fprcpa.s0 f4, p5 = f6, f7
fprcpa.s1 f4, p5 = f6, f7
fprcpa.s2 f4, p5 = f6, f7
fprcpa.s3 f4, p5 = f6, f7
frsqrta f4, p5 = f6
frsqrta.s0 f4, p5 = f6
frsqrta.s1 f4, p5 = f6
frsqrta.s2 f4, p5 = f6
frsqrta.s3 f4, p5 = f6
fprsqrta f4, p5 = f6
fprsqrta.s0 f4, p5 = f6
fprsqrta.s1 f4, p5 = f6
fprsqrta.s2 f4, p5 = f6
fprsqrta.s3 f4, p5 = f6
fmin f4 = f5, f6
fmin.s0 f4 = f5, f6
fmin.s1 f4 = f5, f6
fmin.s2 f4 = f5, f6
fmin.s3 f4 = f5, f6
fmax f4 = f5, f6
fmax.s0 f4 = f5, f6
fmax.s1 f4 = f5, f6
fmax.s2 f4 = f5, f6
fmax.s3 f4 = f5, f6
famin f4 = f5, f6
famin.s0 f4 = f5, f6
famin.s1 f4 = f5, f6
famin.s2 f4 = f5, f6
famin.s3 f4 = f5, f6
famax f4 = f5, f6
famax.s0 f4 = f5, f6
famax.s1 f4 = f5, f6
famax.s2 f4 = f5, f6
famax.s3 f4 = f5, f6
fpmin f4 = f5, f6
fpmin.s0 f4 = f5, f6
fpmin.s1 f4 = f5, f6
fpmin.s2 f4 = f5, f6
fpmin.s3 f4 = f5, f6
fpmax f4 = f5, f6
fpmax.s0 f4 = f5, f6
fpmax.s1 f4 = f5, f6
fpmax.s2 f4 = f5, f6
fpmax.s3 f4 = f5, f6
fpamin f4 = f5, f6
fpamin.s0 f4 = f5, f6
fpamin.s1 f4 = f5, f6
fpamin.s2 f4 = f5, f6
fpamin.s3 f4 = f5, f6
fpamax f4 = f5, f6
fpamax.s0 f4 = f5, f6
fpamax.s1 f4 = f5, f6
fpamax.s2 f4 = f5, f6
fpamax.s3 f4 = f5, f6
fpcmp.eq f3 = f4, f5
fpcmp.eq.s0 f3 = f4, f5
fpcmp.eq.s1 f3 = f4, f5
fpcmp.eq.s2 f3 = f4, f5
fpcmp.eq.s3 f3 = f4, f5
fpcmp.lt f3 = f4, f5
fpcmp.lt.s0 f3 = f4, f5
fpcmp.lt.s1 f3 = f4, f5
fpcmp.lt.s2 f3 = f4, f5
fpcmp.lt.s3 f3 = f4, f5
fpcmp.le f3 = f4, f5
fpcmp.le.s0 f3 = f4, f5
fpcmp.le.s1 f3 = f4, f5
fpcmp.le.s2 f3 = f4, f5
fpcmp.le.s3 f3 = f4, f5
fpcmp.unord f3 = f4, f5
fpcmp.unord.s0 f3 = f4, f5
fpcmp.unord.s1 f3 = f4, f5
fpcmp.unord.s2 f3 = f4, f5
fpcmp.unord.s3 f3 = f4, f5
fpcmp.gt f3 = f4, f5
fpcmp.gt.s0 f3 = f4, f5
fpcmp.gt.s1 f3 = f4, f5
fpcmp.gt.s2 f3 = f4, f5
fpcmp.gt.s3 f3 = f4, f5
fpcmp.ge f3 = f4, f5
fpcmp.ge.s0 f3 = f4, f5
fpcmp.ge.s1 f3 = f4, f5
fpcmp.ge.s2 f3 = f4, f5
fpcmp.ge.s3 f3 = f4, f5
fpcmp.neq f3 = f4, f5
fpcmp.neq.s0 f3 = f4, f5
fpcmp.neq.s1 f3 = f4, f5
fpcmp.neq.s2 f3 = f4, f5
fpcmp.neq.s3 f3 = f4, f5
fpcmp.nlt f3 = f4, f5
fpcmp.nlt.s0 f3 = f4, f5
fpcmp.nlt.s1 f3 = f4, f5
fpcmp.nlt.s2 f3 = f4, f5
fpcmp.nlt.s3 f3 = f4, f5
fpcmp.nle f3 = f4, f5
fpcmp.nle.s0 f3 = f4, f5
fpcmp.nle.s1 f3 = f4, f5
fpcmp.nle.s2 f3 = f4, f5
fpcmp.nle.s3 f3 = f4, f5
fpcmp.ngt f3 = f4, f5
fpcmp.ngt.s0 f3 = f4, f5
fpcmp.ngt.s1 f3 = f4, f5
fpcmp.ngt.s2 f3 = f4, f5
fpcmp.ngt.s3 f3 = f4, f5
fpcmp.nge f3 = f4, f5
fpcmp.nge.s0 f3 = f4, f5
fpcmp.nge.s1 f3 = f4, f5
fpcmp.nge.s2 f3 = f4, f5
fpcmp.nge.s3 f3 = f4, f5
fpcmp.ord f3 = f4, f5
fpcmp.ord.s0 f3 = f4, f5
fpcmp.ord.s1 f3 = f4, f5
fpcmp.ord.s2 f3 = f4, f5
fpcmp.ord.s3 f3 = f4, f5
fmerge.s f4 = f5, f6
fmerge.ns f4 = f5, f6
fmerge.se f4 = f5, f6
fmix.lr f4 = f5, f6
fmix.r f4 = f5, f6
fmix.l f4 = f5, f6
fsxt.l f4 = f5, f6
fpack f4 = f5, f6
fswap f4 = f5, f6
fswap.nl f4 = f5, f6
fswap.nr f4 = f5, f6
fand f4 = f5, f6
fandcm f4 = f5, f6
for f4 = f5, f6
fxor f4 = f5, f6
fpmerge.s f4 = f5, f6
fpmerge.ns f4 = f5, f6
fpmerge.se f4 = f5, f6
fabs f4 = f5
fneg f4 = f5
fnegabs f4 = f5
fpabs f4 = f5
fpneg f4 = f5
fpnegabs f4 = f5
fcvt.fx f4 = f5
fcvt.fx.s0 f4 = f5
fcvt.fx.s1 f4 = f5
fcvt.fx.s2 f4 = f5
fcvt.fx.s3 f4 = f5
fcvt.fx.trunc f4 = f5
fcvt.fx.trunc.s0 f4 = f5
fcvt.fx.trunc.s1 f4 = f5
fcvt.fx.trunc.s2 f4 = f5
fcvt.fx.trunc.s3 f4 = f5
fcvt.fxu f4 = f5
fcvt.fxu.s0 f4 = f5
fcvt.fxu.s1 f4 = f5
fcvt.fxu.s2 f4 = f5
fcvt.fxu.s3 f4 = f5
fcvt.fxu.trunc f4 = f5
fcvt.fxu.trunc.s0 f4 = f5
fcvt.fxu.trunc.s1 f4 = f5
fcvt.fxu.trunc.s2 f4 = f5
fcvt.fxu.trunc.s3 f4 = f5
fpcvt.fx f4 = f5
fpcvt.fx.s0 f4 = f5
fpcvt.fx.s1 f4 = f5
fpcvt.fx.s2 f4 = f5
fpcvt.fx.s3 f4 = f5
fpcvt.fx.trunc f4 = f5
fpcvt.fx.trunc.s0 f4 = f5
fpcvt.fx.trunc.s1 f4 = f5
fpcvt.fx.trunc.s2 f4 = f5
fpcvt.fx.trunc.s3 f4 = f5
fpcvt.fxu f4 = f5
fpcvt.fxu.s0 f4 = f5
fpcvt.fxu.s1 f4 = f5
fpcvt.fxu.s2 f4 = f5
fpcvt.fxu.s3 f4 = f5
fpcvt.fxu.trunc f4 = f5
fpcvt.fxu.trunc.s0 f4 = f5
fpcvt.fxu.trunc.s1 f4 = f5
fpcvt.fxu.trunc.s2 f4 = f5
fpcvt.fxu.trunc.s3 f4 = f5
fcvt.xf f4 = f5
fcvt.xuf f4 = f5
fsetc 0, 0
fsetc 0x3f, 0x3f
fsetc.s0 0, 0
fsetc.s0 0x3f, 0x3f
fsetc.s1 0, 0
fsetc.s1 0x3f, 0x3f
fsetc.s2 0, 0
fsetc.s2 0x3f, 0x3f
fsetc.s3 0, 0
fsetc.s3 0x3f, 0x3f
fclrf
fclrf.s0
fclrf.s1
fclrf.s2
fclrf.s3
fchkf _start
fchkf.s0 _start
fchkf.s1 _start
fchkf.s2 _start
fchkf.s3 _start
break.f 0
nop.f 0;;
# instructions added by SDM2.1:
hint.f 0
hint.f @pause
hint.f 0x1ffff
|
stsp/binutils-ia16
| 3,699
|
gas/testsuite/gas/ia64/unwind-ok.s
|
.text
.proc personality
personality:
br.ret.sptk rp
.endp personality
.proc full1
full1:
.prologue
.spill 0
.save.g 0x1
nop 0
.save.f 0x1
nop 0
.save.b 0x01
nop 0
.save.g 0x8
nop 0
.save.f 0x8
nop 0
.save.b 0x10
nop 0
.altrp b7
nop 0
.unwabi @svr4, 0
nop 0
.body
.spillreg r4, r2
nop 0
.spillreg.p p1, r7, r127
nop 0
.spillsp b1, 0x08
nop 0
.spillsp.p p2, b5, 0x10
nop 0
.spillpsp f2, 0x18
nop 0
.spillpsp.p p4, f5, 0x20
nop 0
.restorereg f16
nop 0
.restorereg.p p8, f31
nop 0
.spillreg ar.bsp, r16
nop 0
.spillreg ar.bspstore, r17
nop 0
.spillreg ar.fpsr, r18
nop 0
.spillreg ar.lc, r19
nop 0
.spillreg ar.pfs, r20
nop 0
.spillreg ar.rnat, r21
nop 0
.spillreg ar.unat, r22
nop 0
.spillreg psp, r23
nop 0
.spillreg pr, r24
nop 0
.spillreg rp, r25
nop 0
.spillreg @priunat, r26
nop 0
.label_state 1
nop 0
.restore sp
nop.x 0
.copy_state 1
br.ret.sptk rp
.personality personality
.handlerdata
data4 -1
data4 0
.endp full1
.proc full2
full2:
.prologue 0xb, r8
.spill 0
.save.gf 0x1, 0x00001
nop 0
nop 0
.save.b 0x11, r32
nop 0
nop 0
.save.gf 0x8, 0x80000
nop 0
nop 0
.spillreg f31, f127
nop 0
.spillreg.p p63, f16, f32
nop 0
.spillsp f5, 0x20
nop 0
.spillsp.p p31, f2, 0x18
nop 0
.spillpsp b5, 0x10
nop 0
.spillpsp.p p15, b1, 0x08
nop 0
.restorereg r7
nop 0
.restorereg.p p7, r4
nop 0
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body; .prologue; .body; .prologue; .body; .prologue; .body; .prologue
.body
.label_state 32
nop 0
.restore sp, 32
nop.x 0
.copy_state 32
br.ret.sptk rp
.endp full2
.proc full3
full3:
.prologue
.spill 0
.save.g 0x3, r32
nop 0
nop 0
.save.b 0x03, r34
nop 0
nop 0
.save.g 0xc, r124
nop 0
nop 0
.save.b 0x18, r126
nop 0
nop 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
.body
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
nop.x 0
br.ret.sptk rp
.endp full3
.proc fframe
fframe:
.prologue
.fframe 0
nop 0
.body
br.ret.sptk rp
.endp fframe
.proc vframe
vframe:
.prologue
.vframe r16
nop 0
.save ar.bsp, r17
nop 0
.save ar.bspstore, r18
nop 0
.save ar.fpsr, r19
nop 0
.save ar.lc, r20
nop 0
.save ar.pfs, r21
nop 0
.save ar.rnat, r22
nop 0
.save ar.unat, r23
nop 0
.save pr, r24
nop 0
.save @priunat, r25
nop 0
.save rp, r26
nop 0
.body
br.ret.sptk rp
.endp vframe
.proc vframesp
vframesp:
.prologue
.vframesp 0
nop 0
.savesp ar.bsp, 0x08
nop 0
.savesp ar.bspstore, 0x10
nop 0
.savesp ar.fpsr, 0x18
nop 0
.savesp ar.lc, 0x20
nop 0
.savesp ar.pfs, 0x28
nop 0
.savesp ar.rnat, 0x30
nop 0
.savesp ar.unat, 0x38
nop 0
.savesp pr, 0x40
nop 0
.savesp @priunat, 0x48
nop 0
.savesp rp, 0x50
nop 0
.body
br.ret.sptk rp
.endp vframesp
.proc psp
psp:
.prologue
.vframesp 0
nop 0
.savepsp ar.bsp, 0x08
nop 0
.savepsp ar.bspstore, 0x10
nop 0
.savepsp ar.fpsr, 0x18
nop 0
.savepsp ar.lc, 0x20
nop 0
.savepsp ar.pfs, 0x28
nop 0
.savepsp ar.rnat, 0x30
nop 0
.savepsp ar.unat, 0x38
nop 0
.savepsp pr, 0x40
nop 0
.savepsp @priunat, 0x48
nop 0
.savepsp rp, 0x50
nop 0
.body
br.ret.sptk rp
.endp psp
.proc simple
simple:
.unwentry
br.ret.sptk rp
.endp simple
|
stsp/binutils-ia16
| 39,967
|
gas/testsuite/gas/ia64/regs.s
|
.text
.type _start,@function
_start:
// Fixed and stacked integer registers.
{ .mii; mov r1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r95 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r96 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r97 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r98 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r99 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r100 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r101 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r102 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r103 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r104 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r105 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r106 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r107 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r108 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r109 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r110 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r111 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r112 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r113 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r114 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r115 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r116 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r117 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r118 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r119 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r120 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r121 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r122 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r123 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r124 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r125 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r126 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov r127 = r0; nop.i 0; nop.i 0;; }
// Alternate names for input registers
.regstk 96, 0, 0, 0
{ .mii; mov in0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov in95 = r0; nop.i 0; nop.i 0;; }
// Alternate names for output registers
.regstk 0, 0, 96, 0
{ .mii; mov out0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov out95 = r0; nop.i 0; nop.i 0;; }
// Alternate names for local registers
.regstk 0, 96, 0, 0
{ .mii; mov loc0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc3 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc4 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc5 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc6 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc7 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc8 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc9 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc10 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc11 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc12 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc13 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc14 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc15 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc16 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc17 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc18 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc19 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc20 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc21 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc22 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc23 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc24 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc25 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc26 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc27 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc28 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc29 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc30 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc31 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc32 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc33 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc34 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc35 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc36 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc37 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc38 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc39 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc40 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc41 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc42 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc43 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc44 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc45 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc46 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc47 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc48 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc49 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc50 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc51 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc52 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc53 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc54 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc55 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc56 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc57 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc58 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc59 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc60 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc61 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc62 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc63 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc64 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc65 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc66 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc67 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc68 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc69 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc70 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc71 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc72 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc73 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc74 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc75 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc76 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc77 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc78 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc79 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc80 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc81 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc82 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc83 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc84 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc85 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc86 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc87 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc88 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc89 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc90 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc91 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc92 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc93 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc94 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov loc95 = r0; nop.i 0; nop.i 0;; }
// Return value registers
{ .mii; mov ret0 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov ret1 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov ret2 = r0; nop.i 0; nop.i 0;; }
{ .mii; mov ret3 = r0; nop.i 0; nop.i 0;; }
{ .mii;
mov gp = r0
mov sp = r0
mov tp = r0;; }
// Floating point registers
{ .mfi; mov f2 = f0 ;; }
{ .mfi; mov f3 = f0 ;; }
{ .mfi; mov f4 = f0 ;; }
{ .mfi; mov f5 = f0 ;; }
{ .mfi; mov f6 = f0 ;; }
{ .mfi; mov f7 = f0 ;; }
{ .mfi; mov f8 = f0 ;; }
{ .mfi; mov f9 = f0 ;; }
{ .mfi; mov f10 = f0 ;; }
{ .mfi; mov f11 = f0 ;; }
{ .mfi; mov f12 = f0 ;; }
{ .mfi; mov f13 = f0 ;; }
{ .mfi; mov f14 = f0 ;; }
{ .mfi; mov f15 = f0 ;; }
{ .mfi; mov f16 = f0 ;; }
{ .mfi; mov f17 = f0 ;; }
{ .mfi; mov f18 = f0 ;; }
{ .mfi; mov f19 = f0 ;; }
{ .mfi; mov f20 = f0 ;; }
{ .mfi; mov f21 = f0 ;; }
{ .mfi; mov f22 = f0 ;; }
{ .mfi; mov f23 = f0 ;; }
{ .mfi; mov f24 = f0 ;; }
{ .mfi; mov f25 = f0 ;; }
{ .mfi; mov f26 = f0 ;; }
{ .mfi; mov f27 = f0 ;; }
{ .mfi; mov f28 = f0 ;; }
{ .mfi; mov f29 = f0 ;; }
{ .mfi; mov f30 = f0 ;; }
{ .mfi; mov f31 = f0 ;; }
{ .mfi; mov f32 = f0 ;; }
{ .mfi; mov f33 = f0 ;; }
{ .mfi; mov f34 = f0 ;; }
{ .mfi; mov f35 = f0 ;; }
{ .mfi; mov f36 = f0 ;; }
{ .mfi; mov f37 = f0 ;; }
{ .mfi; mov f38 = f0 ;; }
{ .mfi; mov f39 = f0 ;; }
{ .mfi; mov f40 = f0 ;; }
{ .mfi; mov f41 = f0 ;; }
{ .mfi; mov f42 = f0 ;; }
{ .mfi; mov f43 = f0 ;; }
{ .mfi; mov f44 = f0 ;; }
{ .mfi; mov f45 = f0 ;; }
{ .mfi; mov f46 = f0 ;; }
{ .mfi; mov f47 = f0 ;; }
{ .mfi; mov f48 = f0 ;; }
{ .mfi; mov f49 = f0 ;; }
{ .mfi; mov f50 = f0 ;; }
{ .mfi; mov f51 = f0 ;; }
{ .mfi; mov f52 = f0 ;; }
{ .mfi; mov f53 = f0 ;; }
{ .mfi; mov f54 = f0 ;; }
{ .mfi; mov f55 = f0 ;; }
{ .mfi; mov f56 = f0 ;; }
{ .mfi; mov f57 = f0 ;; }
{ .mfi; mov f58 = f0 ;; }
{ .mfi; mov f59 = f0 ;; }
{ .mfi; mov f60 = f0 ;; }
{ .mfi; mov f61 = f0 ;; }
{ .mfi; mov f62 = f0 ;; }
{ .mfi; mov f63 = f0 ;; }
{ .mfi; mov f64 = f0 ;; }
{ .mfi; mov f65 = f0 ;; }
{ .mfi; mov f66 = f0 ;; }
{ .mfi; mov f67 = f0 ;; }
{ .mfi; mov f68 = f0 ;; }
{ .mfi; mov f69 = f0 ;; }
{ .mfi; mov f70 = f0 ;; }
{ .mfi; mov f71 = f0 ;; }
{ .mfi; mov f72 = f0 ;; }
{ .mfi; mov f73 = f0 ;; }
{ .mfi; mov f74 = f0 ;; }
{ .mfi; mov f75 = f0 ;; }
{ .mfi; mov f76 = f0 ;; }
{ .mfi; mov f77 = f0 ;; }
{ .mfi; mov f78 = f0 ;; }
{ .mfi; mov f79 = f0 ;; }
{ .mfi; mov f80 = f0 ;; }
{ .mfi; mov f81 = f0 ;; }
{ .mfi; mov f82 = f0 ;; }
{ .mfi; mov f83 = f0 ;; }
{ .mfi; mov f84 = f0 ;; }
{ .mfi; mov f85 = f0 ;; }
{ .mfi; mov f86 = f0 ;; }
{ .mfi; mov f87 = f0 ;; }
{ .mfi; mov f88 = f0 ;; }
{ .mfi; mov f89 = f0 ;; }
{ .mfi; mov f90 = f0 ;; }
{ .mfi; mov f91 = f0 ;; }
{ .mfi; mov f92 = f0 ;; }
{ .mfi; mov f93 = f0 ;; }
{ .mfi; mov f94 = f0 ;; }
{ .mfi; mov f95 = f0 ;; }
{ .mfi; mov f96 = f0 ;; }
{ .mfi; mov f97 = f0 ;; }
{ .mfi; mov f98 = f0 ;; }
{ .mfi; mov f99 = f0 ;; }
{ .mfi; mov f100 = f0 ;; }
{ .mfi; mov f101 = f0 ;; }
{ .mfi; mov f102 = f0 ;; }
{ .mfi; mov f103 = f0 ;; }
{ .mfi; mov f104 = f0 ;; }
{ .mfi; mov f105 = f0 ;; }
{ .mfi; mov f106 = f0 ;; }
{ .mfi; mov f107 = f0 ;; }
{ .mfi; mov f108 = f0 ;; }
{ .mfi; mov f109 = f0 ;; }
{ .mfi; mov f110 = f0 ;; }
{ .mfi; mov f111 = f0 ;; }
{ .mfi; mov f112 = f0 ;; }
{ .mfi; mov f113 = f0 ;; }
{ .mfi; mov f114 = f0 ;; }
{ .mfi; mov f115 = f0 ;; }
{ .mfi; mov f116 = f0 ;; }
{ .mfi; mov f117 = f0 ;; }
{ .mfi; mov f118 = f0 ;; }
{ .mfi; mov f119 = f0 ;; }
{ .mfi; mov f120 = f0 ;; }
{ .mfi; mov f121 = f0 ;; }
{ .mfi; mov f122 = f0 ;; }
{ .mfi; mov f123 = f0 ;; }
{ .mfi; mov f124 = f0 ;; }
{ .mfi; mov f125 = f0 ;; }
{ .mfi; mov f126 = f0 ;; }
{ .mfi; mov f127 = f0 ;; }
// Floating point argument registers
{ .mfi; mov farg0 = f1 ;; }
{ .mfi; mov farg1 = f1 ;; }
{ .mfi; mov farg2 = f1 ;; }
{ .mfi; mov farg3 = f1 ;; }
{ .mfi; mov farg4 = f1 ;; }
{ .mfi; mov farg5 = f1 ;; }
{ .mfi; mov farg6 = f1 ;; }
{ .mfi; mov farg7 = f1 ;; }
// Floating point return value registers
{ .mfi; mov fret0 = f1 ;; }
{ .mfi; mov fret1 = f1 ;; }
{ .mfi; mov fret2 = f1 ;; }
{ .mfi; mov fret3 = f1 ;; }
{ .mfi; mov fret4 = f1 ;; }
{ .mfi; mov fret5 = f1 ;; }
{ .mfi; mov fret6 = f1 ;; }
{ .mfi; mov fret7 = f1 ;; }
// Predicate registers
{ .mii; (p0) mov r1 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p1) mov r2 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p2) mov r3 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p3) mov r4 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p4) mov r5 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p5) mov r6 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p6) mov r7 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p7) mov r8 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p8) mov r9 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p9) mov r10 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p10) mov r11 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p11) mov r12 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p12) mov r13 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p13) mov r14 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p14) mov r15 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p15) mov r16 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p16) mov r17 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p17) mov r18 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p18) mov r19 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p19) mov r20 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p20) mov r21 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p21) mov r22 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p22) mov r23 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p23) mov r24 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p24) mov r25 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p25) mov r26 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p26) mov r27 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p27) mov r28 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p28) mov r29 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p29) mov r30 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p30) mov r31 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p31) mov r32 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p32) mov r33 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p33) mov r34 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p34) mov r35 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p35) mov r36 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p36) mov r37 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p37) mov r38 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p38) mov r39 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p39) mov r40 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p40) mov r41 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p41) mov r42 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p42) mov r43 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p43) mov r44 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p44) mov r45 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p45) mov r46 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p46) mov r47 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p47) mov r48 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p48) mov r49 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p49) mov r50 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p50) mov r51 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p51) mov r52 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p52) mov r53 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p53) mov r54 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p54) mov r55 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p55) mov r56 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p56) mov r57 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p57) mov r58 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p58) mov r59 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p59) mov r60 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p60) mov r61 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p61) mov r62 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p62) mov r63 = r0; nop.i 0; nop.i 0;; }
{ .mii; (p63) mov r64 = r0; nop.i 0; nop.i 0;; }
// Predicates as a unit
{ .mmi; nop.m 0; mov r1 = pr ;; }
// mov r2 = pr.rot
// Branch registers.
{ .mmi; mov b0 = r0;; }
{ .mmi; mov b1 = r0;; }
{ .mmi; mov b2 = r0;; }
{ .mmi; mov b3 = r0;; }
{ .mmi; mov b4 = r0;; }
{ .mmi; mov b5 = r0;; }
{ .mmi; mov b6 = r0;; }
{ .mmi; mov b7 = r0;; }
{ .mmi; mov rp = r0;; }
// Application registers
{ .mmi; nop.m 0; mov r1 = ar0 ;; }
{ .mmi; nop.m 0; mov r1 = ar1 ;; }
{ .mmi; nop.m 0; mov r1 = ar2 ;; }
{ .mmi; nop.m 0; mov r1 = ar3 ;; }
{ .mmi; nop.m 0; mov r1 = ar4 ;; }
{ .mmi; nop.m 0; mov r1 = ar5 ;; }
{ .mmi; nop.m 0; mov r1 = ar6 ;; }
{ .mmi; nop.m 0; mov r1 = ar7 ;; }
// { .mmi; nop.m 0; mov r1 = ar8 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar9 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar10 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar11 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar12 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar13 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar14 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar15 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar16 ;; }
{ .mmi; nop.m 0; mov r1 = ar17 ;; }
{ .mmi; nop.m 0; mov r1 = ar18 ;; }
{ .mmi; nop.m 0; mov r1 = ar19 ;; }
// { .mmi; nop.m 0; mov r1 = ar20 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar21 ;; }
// { .mmi; nop.m 0; mov r1 = ar22 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar23 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar24 ;; }
{ .mmi; nop.m 0; mov r1 = ar25 ;; }
{ .mmi; nop.m 0; mov r1 = ar26 ;; }
{ .mmi; nop.m 0; mov r1 = ar27 ;; }
{ .mmi; nop.m 0; mov r1 = ar28 ;; }
{ .mmi; nop.m 0; mov r1 = ar29 ;; }
{ .mmi; nop.m 0; mov r1 = ar30 ;; }
// { .mmi; nop.m 0; mov r1 = ar31 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar32 ;; }
// { .mmi; nop.m 0; mov r1 = ar33 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar34 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar35 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar36 ;; }
// { .mmi; nop.m 0; mov r1 = ar37 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar38 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar39 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar40 ;; }
// { .mmi; nop.m 0; mov r1 = ar41 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar42 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar43 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar44 ;; }
{ .mmi; nop.m 0; mov r1 = ar45 ;; }
// { .mmi; nop.m 0; mov r1 = ar46 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar47 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar48 ;; }
{ .mmi; nop.m 0; mov r1 = ar49 ;; }
{ .mmi; nop.m 0; mov r1 = ar50 ;; }
{ .mmi; nop.m 0; mov r1 = ar51 ;; }
{ .mmi; nop.m 0; mov r1 = ar52 ;; }
{ .mmi; nop.m 0; mov r1 = ar53 ;; }
{ .mmi; nop.m 0; mov r1 = ar54 ;; }
{ .mmi; nop.m 0; mov r1 = ar55 ;; }
{ .mmi; nop.m 0; mov r1 = ar56 ;; }
{ .mmi; nop.m 0; mov r1 = ar57 ;; }
{ .mmi; nop.m 0; mov r1 = ar58 ;; }
{ .mmi; nop.m 0; mov r1 = ar59 ;; }
{ .mmi; nop.m 0; mov r1 = ar60 ;; }
{ .mmi; nop.m 0; mov r1 = ar61 ;; }
{ .mmi; nop.m 0; mov r1 = ar62 ;; }
{ .mmi; nop.m 0; mov r1 = ar63 ;; }
{ .mmi; nop.m 0; mov r1 = ar64 ;; }
{ .mmi; nop.m 0; mov r1 = ar65 ;; }
{ .mmi; nop.m 0; mov r1 = ar66 ;; }
// { .mmi; nop.m 0; mov r1 = ar67 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar68 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar69 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar70 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar71 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar72 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar73 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar74 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar75 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar76 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar77 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar78 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar79 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar80 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar81 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar82 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar83 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar84 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar85 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar86 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar87 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar88 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar89 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar90 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar91 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar92 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar93 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar94 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar95 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar96 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar97 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar98 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar99 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar100 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar101 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar102 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar103 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar104 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar105 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar106 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar107 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar108 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar109 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar110 ;; } // reserved
// { .mmi; nop.m 0; mov r1 = ar111 ;; } // reserved
{ .mmi; nop.m 0; mov r1 = ar112 ;; }
{ .mmi; nop.m 0; mov r1 = ar113 ;; }
{ .mmi; nop.m 0; mov r1 = ar114 ;; }
{ .mmi; nop.m 0; mov r1 = ar115 ;; }
{ .mmi; nop.m 0; mov r1 = ar116 ;; }
{ .mmi; nop.m 0; mov r1 = ar117 ;; }
{ .mmi; nop.m 0; mov r1 = ar118 ;; }
{ .mmi; nop.m 0; mov r1 = ar119 ;; }
{ .mmi; nop.m 0; mov r1 = ar120 ;; }
{ .mmi; nop.m 0; mov r1 = ar121 ;; }
{ .mmi; nop.m 0; mov r1 = ar122 ;; }
{ .mmi; nop.m 0; mov r1 = ar123 ;; }
{ .mmi; nop.m 0; mov r1 = ar124 ;; }
{ .mmi; nop.m 0; mov r1 = ar125 ;; }
{ .mmi; nop.m 0; mov r1 = ar126 ;; }
{ .mmi; nop.m 0; mov r1 = ar127 ;; }
// Application registers by name
{ .mmi; nop.m 0; mov r1 = ar.k0 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k1 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k2 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k3 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k4 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k5 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k6 ;;}
{ .mmi; nop.m 0; mov r1 = ar.k7 ;;}
{ .mmi; nop.m 0; mov r1 = ar.rsc ;; }
{ .mmi; nop.m 0; mov r1 = ar.bsp ;; }
{ .mmi; nop.m 0; mov r1 = ar.bspstore ;; }
{ .mmi; nop.m 0; mov r1 = ar.rnat ;; }
{ .mmi; nop.m 0; mov r1 = ar.ccv ;; }
{ .mmi; nop.m 0; mov r1 = ar.unat ;; }
{ .mmi; nop.m 0; mov r1 = ar.fpsr ;; }
{ .mmi; nop.m 0; mov r1 = ar.itc ;; }
{ .mmi; nop.m 0; mov r1 = ar.ruc ;; }
{ .mmi; nop.m 0; mov r1 = ar.pfs ;; }
{ .mmi; nop.m 0; mov r1 = ar.lc ;; }
{ .mmi; nop.m 0; mov r1 = ar.ec ;; }
// Control registers
{ .mfb; mov r1 = cr0 ;; }
{ .mfb; mov r1 = cr1 ;; }
{ .mfb; mov r1 = cr2 ;; }
// { .mfb; mov r1 = cr3 ;; } // reserved
// { .mfb; mov r1 = cr4 ;; } // reserved
// { .mfb; mov r1 = cr5 ;; } // reserved
// { .mfb; mov r1 = cr6 ;; } // reserved
// { .mfb; mov r1 = cr7 ;; } // reserved
{ .mfb; mov r1 = cr8 ;; }
{ .mfb; mov r1 = cr9 ;; }
// { .mfb; mov r1 = cr10 ;; } // reserved
// { .mfb; mov r1 = cr11 ;; } // reserved
// { .mfb; mov r1 = cr12 ;; } // reserved
// { .mfb; mov r1 = cr13 ;; } // reserved
// { .mfb; mov r1 = cr14 ;; } // reserved
// { .mfb; mov r1 = cr15 ;; } // reserved
{ .mfb; mov r1 = cr16 ;; }
{ .mfb; mov r1 = cr17 ;; }
// { .mfb; mov r1 = cr18 ;; } // reserved
{ .mfb; mov r1 = cr19 ;; }
{ .mfb; mov r1 = cr20 ;; }
{ .mfb; mov r1 = cr21 ;; }
{ .mfb; mov r1 = cr22 ;; }
{ .mfb; mov r1 = cr23 ;; }
{ .mfb; mov r1 = cr24 ;; }
{ .mfb; mov r1 = cr25 ;; }
// { .mfb; mov r1 = cr26 ;; } // reserved
// { .mfb; mov r1 = cr27 ;; } // reserved
// { .mfb; mov r1 = cr28 ;; } // reserved
// { .mfb; mov r1 = cr29 ;; } // reserved
// { .mfb; mov r1 = cr30 ;; } // reserved
// { .mfb; mov r1 = cr31 ;; } // reserved
// { .mfb; mov r1 = cr32 ;; } // reserved
// { .mfb; mov r1 = cr33 ;; } // reserved
// { .mfb; mov r1 = cr34 ;; } // reserved
// { .mfb; mov r1 = cr35 ;; } // reserved
// { .mfb; mov r1 = cr36 ;; } // reserved
// { .mfb; mov r1 = cr37 ;; } // reserved
// { .mfb; mov r1 = cr38 ;; } // reserved
// { .mfb; mov r1 = cr39 ;; } // reserved
// { .mfb; mov r1 = cr40 ;; } // reserved
// { .mfb; mov r1 = cr41 ;; } // reserved
// { .mfb; mov r1 = cr42 ;; } // reserved
// { .mfb; mov r1 = cr43 ;; } // reserved
// { .mfb; mov r1 = cr44 ;; } // reserved
// { .mfb; mov r1 = cr45 ;; } // reserved
// { .mfb; mov r1 = cr46 ;; } // reserved
// { .mfb; mov r1 = cr47 ;; } // reserved
// { .mfb; mov r1 = cr48 ;; } // reserved
// { .mfb; mov r1 = cr49 ;; } // reserved
// { .mfb; mov r1 = cr50 ;; } // reserved
// { .mfb; mov r1 = cr51 ;; } // reserved
// { .mfb; mov r1 = cr52 ;; } // reserved
// { .mfb; mov r1 = cr53 ;; } // reserved
// { .mfb; mov r1 = cr54 ;; } // reserved
// { .mfb; mov r1 = cr55 ;; } // reserved
// { .mfb; mov r1 = cr56 ;; } // reserved
// { .mfb; mov r1 = cr57 ;; } // reserved
// { .mfb; mov r1 = cr58 ;; } // reserved
// { .mfb; mov r1 = cr59 ;; } // reserved
// { .mfb; mov r1 = cr60 ;; } // reserved
// { .mfb; mov r1 = cr61 ;; } // reserved
// { .mfb; mov r1 = cr62 ;; } // reserved
// { .mfb; mov r1 = cr63 ;; } // reserved
{ .mfb; mov r1 = cr64 ;; }
{ .mfb; mov r1 = cr65 ;; }
{ .mfb; mov r1 = cr66 ;; }
{ .mfb; mov r1 = cr67 ;; }
{ .mfb; mov r1 = cr68 ;; }
{ .mfb; mov r1 = cr69 ;; }
{ .mfb; mov r1 = cr70 ;; }
{ .mfb; mov r1 = cr71 ;; }
{ .mfb; mov r1 = cr72 ;; }
{ .mfb; mov r1 = cr73 ;; }
{ .mfb; mov r1 = cr74 ;; }
// { .mfb; mov r1 = cr75 ;; } // reserved
// { .mfb; mov r1 = cr76 ;; } // reserved
// { .mfb; mov r1 = cr77 ;; } // reserved
// { .mfb; mov r1 = cr78 ;; } // reserved
// { .mfb; mov r1 = cr79 ;; } // reserved
{ .mfb; mov r1 = cr80 ;; }
{ .mfb; mov r1 = cr81 ;; }
// { .mfb; mov r1 = cr82 ;; } // reserved
// { .mfb; mov r1 = cr83 ;; } // reserved
// { .mfb; mov r1 = cr84 ;; } // reserved
// { .mfb; mov r1 = cr85 ;; } // reserved
// { .mfb; mov r1 = cr86 ;; } // reserved
// { .mfb; mov r1 = cr87 ;; } // reserved
// { .mfb; mov r1 = cr88 ;; } // reserved
// { .mfb; mov r1 = cr89 ;; } // reserved
// { .mfb; mov r1 = cr90 ;; } // reserved
// { .mfb; mov r1 = cr91 ;; } // reserved
// { .mfb; mov r1 = cr92 ;; } // reserved
// { .mfb; mov r1 = cr93 ;; } // reserved
// { .mfb; mov r1 = cr94 ;; } // reserved
// { .mfb; mov r1 = cr95 ;; } // reserved
// { .mfb; mov r1 = cr96 ;; } // reserved
// { .mfb; mov r1 = cr97 ;; } // reserved
// { .mfb; mov r1 = cr98 ;; } // reserved
// { .mfb; mov r1 = cr99 ;; } // reserved
// { .mfb; mov r1 = cr100 ;; } // reserved
// { .mfb; mov r1 = cr101 ;; } // reserved
// { .mfb; mov r1 = cr102 ;; } // reserved
// { .mfb; mov r1 = cr103 ;; } // reserved
// { .mfb; mov r1 = cr104 ;; } // reserved
// { .mfb; mov r1 = cr105 ;; } // reserved
// { .mfb; mov r1 = cr106 ;; } // reserved
// { .mfb; mov r1 = cr107 ;; } // reserved
// { .mfb; mov r1 = cr108 ;; } // reserved
// { .mfb; mov r1 = cr109 ;; } // reserved
// { .mfb; mov r1 = cr110 ;; } // reserved
// { .mfb; mov r1 = cr111 ;; } // reserved
// { .mfb; mov r1 = cr112 ;; } // reserved
// { .mfb; mov r1 = cr113 ;; } // reserved
// { .mfb; mov r1 = cr114 ;; } // reserved
// { .mfb; mov r1 = cr115 ;; } // reserved
// { .mfb; mov r1 = cr116 ;; } // reserved
// { .mfb; mov r1 = cr117 ;; } // reserved
// { .mfb; mov r1 = cr118 ;; } // reserved
// { .mfb; mov r1 = cr119 ;; } // reserved
// { .mfb; mov r1 = cr120 ;; } // reserved
// { .mfb; mov r1 = cr121 ;; } // reserved
// { .mfb; mov r1 = cr122 ;; } // reserved
// { .mfb; mov r1 = cr123 ;; } // reserved
// { .mfb; mov r1 = cr124 ;; } // reserved
// { .mfb; mov r1 = cr125 ;; } // reserved
// { .mfb; mov r1 = cr126 ;; } // reserved
// { .mfb; mov r1 = cr127 ;; } // reserved
// Control registers by name
{ .mfb; mov r1 = cr.dcr ;; }
{ .mfb; mov r1 = cr.itm ;; }
{ .mfb; mov r1 = cr.iva ;; }
{ .mfb; mov r1 = cr.pta ;; }
{ .mfb; mov r1 = cr.ipsr ;; }
{ .mfb; mov r1 = cr.isr ;; }
{ .mfb; mov r1 = cr.iip ;; }
{ .mfb; mov r1 = cr.iipa ;; }
{ .mfb; mov r1 = cr.ifs ;; }
{ .mfb; mov r1 = cr.iim ;; }
{ .mfb; mov r1 = cr.iha ;; }
{ .mfb; mov r1 = cr.iib0 ;; }
{ .mfb; mov r1 = cr.iib1 ;; }
{ .mfb; mov r1 = cr.lid ;; }
{ .mfb; mov r1 = cr.ivr ;; }
{ .mfb; mov r1 = cr.tpr ;; }
{ .mfb; mov r1 = cr.eoi ;; }
{ .mfb; mov r1 = cr.irr0 ;; }
{ .mfb; mov r1 = cr.irr1 ;; }
{ .mfb; mov r1 = cr.irr2 ;; }
{ .mfb; mov r1 = cr.irr3 ;; }
{ .mfb; mov r1 = cr.itv ;; }
{ .mfb; mov r1 = cr.pmv ;; }
{ .mfb; mov r1 = cr.lrr0 ;; }
{ .mfb; mov r1 = cr.lrr1 ;; }
{ .mfb; mov r1 = cr.cmcv ;; }
// Other registers
{ .mfb; mov r1 = psr ;; }
// { .mfb; mov r1 = psr.l ;; }
{ .mfb; mov r1 = psr.um ;; }
{ .mmi; mov r1 = ip ;; }
// Indirect register files
{ .mmi
mov r1 = pmc[r3]
mov r2 = pmc[r4]
nop.i 0;; }
{ .mmi
mov r1 = pmd[r3]
mov r2 = pmd[r4]
nop.i 0;; }
{ .mmi
mov r1 = pkr[r3]
mov r2 = pkr[r4]
nop.i 0;; }
{ .mmi
mov r1 = rr[r3]
mov r2 = rr[r4]
nop.i 0;; }
{ .mmi
mov r1 = ibr[r3]
mov r2 = ibr[r4]
nop.i 0;; }
{ .mmi
mov r1 = dbr[r3]
mov r2 = dbr[r4]
nop.i 0;; }
{ .mmi
mov r1 = CPUID[r3]
mov r2 = CPUID[r4]
nop.i 0;; }
{ .mmi
mov r1 = cpuid[r3]
mov r2 = cpuid[r4]
nop.i 0;; }
|
stsp/binutils-ia16
| 1,153
|
gas/testsuite/gas/ia64/tls.s
|
.section ".tdata", "awT", @progbits
.align 16
.global x#, y#, z#, a#, b#, c#
.protected a#, b#, c#
.type x#,@object
.size x#,4
x: data4 1
.type y#,@object
.size y#,4
y: data4 2
.type z#,@object
.size z#,4
z: data4 3
.align 8
.type a#,@object
.size a#,8
a: data8 4
.type b#,@object
.size b#,8
b: data8 5
.type c#,@object
.size c#,1
c: data1 6
.text
.align 16
.global foo#
.proc foo#
foo:
.prologue
alloc r36 = ar.pfs, 0, 5, 3, 0
.body
addl loc0 = @ltoff(@tprel(x)), gp;;
ld8 loc0 = [loc0];;
add loc1 = loc0, r13;;
mov r2 = r13;;
addl loc1 = @tprel(y), r2;;
mov loc0 = gp
addl out0 = @ltoff(@dtpmod(z)), gp
addl out1 = @ltoff(@dtprel(z)), gp;;
ld8 out0 = [out0]
ld8 out1 = [out1]
br.call.sptk.many b0 = __tls_get_addr;;
mov gp = loc0;;
addl out0 = @ltoff(@dtpmod(a)), gp
addl out1 = @dtprel(a), r0;;
ld8 out0 = [out0]
br.call.sptk.many b0 = __tls_get_addr;;
mov gp = loc0;;
addl out0 = @ltoff(@dtpmod(b)), gp
mov out1 = r0;;
ld8 out0 = [out0]
br.call.sptk.many b0 = __tls_get_addr;;
mov gp = loc0
mov r2 = ret0;;
addl loc1 = @dtprel(b), r2
addl loc2 = @dtprel(c), r2
br.ret.sptk.many b0
.endp foo#
|
stsp/binutils-ia16
| 18,157
|
gas/testsuite/gas/ia64/opc-b.s
|
.L0:
{ .bbb; nop.b 0
(p2) br.cond.sptk .L1
br.cond.sptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.clr .L1
br.cond.sptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few .L1
br.cond.sptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.few.clr .L1
br.cond.sptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.many .L1
br.cond.sptk.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.sptk.many.clr .L1
br.cond.sptk.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt .L1
br.cond.spnt .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.clr .L1
br.cond.spnt.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.few .L1
br.cond.spnt.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.few.clr .L1
br.cond.spnt.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.many .L1
br.cond.spnt.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.spnt.many.clr .L1
br.cond.spnt.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk .L1
br.cond.dptk .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.clr .L1
br.cond.dptk.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.few .L1
br.cond.dptk.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.few.clr .L1
br.cond.dptk.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.many .L1
br.cond.dptk.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dptk.many.clr .L1
br.cond.dptk.many.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt .L1
br.cond.dpnt .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.clr .L1
br.cond.dpnt.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.few .L1
br.cond.dpnt.few .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.few.clr .L1
br.cond.dpnt.few.clr .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.many .L1
br.cond.dpnt.many .L0
;; }
{ .bbb; nop.b 0
(p2) br.cond.dpnt.many.clr .L1
br.cond.dpnt.many.clr .L0
;; }
{ .bbb; (p2) br.wexit.sptk .L1 ;; }
{ .bbb; br.wexit.sptk .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.clr .L1 ;; }
{ .bbb; br.wexit.sptk.clr .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.few .L1 ;; }
{ .bbb; br.wexit.sptk.few .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.few.clr .L1 ;; }
{ .bbb; br.wexit.sptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.many .L1 ;; }
{ .bbb; br.wexit.sptk.many .L1 ;; }
{ .bbb; (p2) br.wexit.sptk.many.clr .L1 ;; }
{ .bbb; br.wexit.sptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt .L1 ;; }
{ .bbb; br.wexit.spnt .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.clr .L1 ;; }
{ .bbb; br.wexit.spnt.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.few .L1 ;; }
{ .bbb; br.wexit.spnt.few .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.few.clr .L1 ;; }
{ .bbb; br.wexit.spnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.many .L1 ;; }
{ .bbb; br.wexit.spnt.many .L1 ;; }
{ .bbb; (p2) br.wexit.spnt.many.clr .L1 ;; }
{ .bbb; br.wexit.spnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk .L1 ;; }
{ .bbb; br.wexit.dptk .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.clr .L1 ;; }
{ .bbb; br.wexit.dptk.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.few .L1 ;; }
{ .bbb; br.wexit.dptk.few .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.few.clr .L1 ;; }
{ .bbb; br.wexit.dptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.many .L1 ;; }
{ .bbb; br.wexit.dptk.many .L1 ;; }
{ .bbb; (p2) br.wexit.dptk.many.clr .L1 ;; }
{ .bbb; br.wexit.dptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt .L1 ;; }
{ .bbb; br.wexit.dpnt .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.few .L1 ;; }
{ .bbb; br.wexit.dpnt.few .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.few.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.many .L1 ;; }
{ .bbb; br.wexit.dpnt.many .L1 ;; }
{ .bbb; (p2) br.wexit.dpnt.many.clr .L1 ;; }
{ .bbb; br.wexit.dpnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk .L1 ;; }
{ .bbb; br.wtop.sptk .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.clr .L1 ;; }
{ .bbb; br.wtop.sptk.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.few .L1 ;; }
{ .bbb; br.wtop.sptk.few .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.few.clr .L1 ;; }
{ .bbb; br.wtop.sptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.many .L1 ;; }
{ .bbb; br.wtop.sptk.many .L1 ;; }
{ .bbb; (p2) br.wtop.sptk.many.clr .L1 ;; }
{ .bbb; br.wtop.sptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt .L1 ;; }
{ .bbb; br.wtop.spnt .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.clr .L1 ;; }
{ .bbb; br.wtop.spnt.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.few .L1 ;; }
{ .bbb; br.wtop.spnt.few .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.few.clr .L1 ;; }
{ .bbb; br.wtop.spnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.many .L1 ;; }
{ .bbb; br.wtop.spnt.many .L1 ;; }
{ .bbb; (p2) br.wtop.spnt.many.clr .L1 ;; }
{ .bbb; br.wtop.spnt.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk .L1 ;; }
{ .bbb; br.wtop.dptk .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.clr .L1 ;; }
{ .bbb; br.wtop.dptk.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.few .L1 ;; }
{ .bbb; br.wtop.dptk.few .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.few.clr .L1 ;; }
{ .bbb; br.wtop.dptk.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.many .L1 ;; }
{ .bbb; br.wtop.dptk.many .L1 ;; }
{ .bbb; (p2) br.wtop.dptk.many.clr .L1 ;; }
{ .bbb; br.wtop.dptk.many.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt .L1 ;; }
{ .bbb; br.wtop.dpnt .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.few .L1 ;; }
{ .bbb; br.wtop.dpnt.few .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.few.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.few.clr .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.many .L1 ;; }
{ .bbb; br.wtop.dpnt.many .L1 ;; }
{ .bbb; (p2) br.wtop.dpnt.many.clr .L1 ;; }
{ .bbb; br.wtop.dpnt.many.clr .L1 ;; }
{ .bbb; br.cloop.sptk .L1 ;; }
{ .bbb; br.cloop.sptk.clr .L1 ;; }
{ .bbb; br.cloop.sptk.few .L1 ;; }
{ .bbb; br.cloop.sptk.few.clr .L1 ;; }
{ .bbb; br.cloop.sptk.many .L1 ;; }
{ .bbb; br.cloop.sptk.many.clr .L1 ;; }
{ .bbb; br.cloop.spnt .L1 ;; }
{ .bbb; br.cloop.spnt.clr .L1 ;; }
{ .bbb; br.cloop.spnt.few .L1 ;; }
{ .bbb; br.cloop.spnt.few.clr .L1 ;; }
{ .bbb; br.cloop.spnt.many .L1 ;; }
{ .bbb; br.cloop.spnt.many.clr .L1 ;; }
{ .bbb; br.cloop.dptk .L1 ;; }
{ .bbb; br.cloop.dptk.clr .L1 ;; }
{ .bbb; br.cloop.dptk.few .L1 ;; }
{ .bbb; br.cloop.dptk.few.clr .L1 ;; }
{ .bbb; br.cloop.dptk.many .L1 ;; }
{ .bbb; br.cloop.dptk.many.clr .L1 ;; }
{ .bbb; br.cloop.dpnt .L1 ;; }
{ .bbb; br.cloop.dpnt.clr .L1 ;; }
{ .bbb; br.cloop.dpnt.few .L1 ;; }
{ .bbb; br.cloop.dpnt.few.clr .L1 ;; }
{ .bbb; br.cloop.dpnt.many .L1 ;; }
{ .bbb; br.cloop.dpnt.many.clr .L1 ;; }
{ .bbb; br.cexit.sptk .L1 ;; }
{ .bbb; br.cexit.sptk.clr .L1 ;; }
{ .bbb; br.cexit.sptk.few .L1 ;; }
{ .bbb; br.cexit.sptk.few.clr .L1 ;; }
{ .bbb; br.cexit.sptk.many .L1 ;; }
{ .bbb; br.cexit.sptk.many.clr .L1 ;; }
{ .bbb; br.cexit.spnt .L1 ;; }
{ .bbb; br.cexit.spnt.clr .L1 ;; }
{ .bbb; br.cexit.spnt.few .L1 ;; }
{ .bbb; br.cexit.spnt.few.clr .L1 ;; }
{ .bbb; br.cexit.spnt.many .L1 ;; }
{ .bbb; br.cexit.spnt.many.clr .L1 ;; }
{ .bbb; br.cexit.dptk .L1 ;; }
{ .bbb; br.cexit.dptk.clr .L1 ;; }
{ .bbb; br.cexit.dptk.few .L1 ;; }
{ .bbb; br.cexit.dptk.few.clr .L1 ;; }
{ .bbb; br.cexit.dptk.many .L1 ;; }
{ .bbb; br.cexit.dptk.many.clr .L1 ;; }
{ .bbb; br.cexit.dpnt .L1 ;; }
{ .bbb; br.cexit.dpnt.clr .L1 ;; }
{ .bbb; br.cexit.dpnt.few .L1 ;; }
{ .bbb; br.cexit.dpnt.few.clr .L1 ;; }
{ .bbb; br.cexit.dpnt.many .L1 ;; }
{ .bbb; br.cexit.dpnt.many.clr .L1 ;; }
{ .bbb; br.ctop.sptk .L1 ;; }
{ .bbb; br.ctop.sptk.clr .L1 ;; }
{ .bbb; br.ctop.sptk.few .L1 ;; }
{ .bbb; br.ctop.sptk.few.clr .L1 ;; }
{ .bbb; br.ctop.sptk.many .L1 ;; }
{ .bbb; br.ctop.sptk.many.clr .L1 ;; }
{ .bbb; br.ctop.spnt .L1 ;; }
{ .bbb; br.ctop.spnt.clr .L1 ;; }
{ .bbb; br.ctop.spnt.few .L1 ;; }
{ .bbb; br.ctop.spnt.few.clr .L1 ;; }
{ .bbb; br.ctop.spnt.many .L1 ;; }
{ .bbb; br.ctop.spnt.many.clr .L1 ;; }
{ .bbb; br.ctop.dptk .L1 ;; }
{ .bbb; br.ctop.dptk.clr .L1 ;; }
{ .bbb; br.ctop.dptk.few .L1 ;; }
{ .bbb; br.ctop.dptk.few.clr .L1 ;; }
{ .bbb; br.ctop.dptk.many .L1 ;; }
{ .bbb; br.ctop.dptk.many.clr .L1 ;; }
{ .bbb; br.ctop.dpnt .L1 ;; }
{ .bbb; br.ctop.dpnt.clr .L1 ;; }
{ .bbb; br.ctop.dpnt.few .L1 ;; }
{ .bbb; br.ctop.dpnt.few.clr .L1 ;; }
{ .bbb; br.ctop.dpnt.many .L1 ;; }
{ .bbb; br.ctop.dpnt.many.clr .L1 ;; }
{ .bbb; nop.b 0
(p2) br.call.sptk b0 = .L1
br.call.sptk b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.clr b0 = .L1
br.call.sptk.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.few b0 = .L1
br.call.sptk.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.few.clr b0 = .L1
br.call.sptk.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.many b0 = .L1
br.call.sptk.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.sptk.many.clr b0 = .L1
br.call.sptk.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt b0 = .L1
br.call.spnt b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.clr b0 = .L1
br.call.spnt.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.few b0 = .L1
br.call.spnt.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.few.clr b0 = .L1
br.call.spnt.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.many b0 = .L1
br.call.spnt.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.spnt.many.clr b0 = .L1
br.call.spnt.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk b0 = .L1
br.call.dptk b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.clr b0 = .L1
br.call.dptk.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.few b0 = .L1
br.call.dptk.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.few.clr b0 = .L1
br.call.dptk.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.many b0 = .L1
br.call.dptk.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dptk.many.clr b0 = .L1
br.call.dptk.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt b0 = .L1
br.call.dpnt b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.clr b0 = .L1
br.call.dpnt.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.few b0 = .L1
br.call.dpnt.few b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.few.clr b0 = .L1
br.call.dpnt.few.clr b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.many b0 = .L1
br.call.dpnt.many b0 = .L0
;; }
{ .bbb; nop.b 0
(p2) br.call.dpnt.many.clr b0 = .L1
br.call.dpnt.many.clr b0 = .L0
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk b2
br.cond.sptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.clr b2
br.cond.sptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.few b2
br.cond.sptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.few.clr b2
br.cond.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.many b2
br.cond.sptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.sptk.many.clr b2
br.cond.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt b2
br.cond.spnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.clr b2
br.cond.spnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.few b2
br.cond.spnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.few.clr b2
br.cond.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.many b2
br.cond.spnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.spnt.many.clr b2
br.cond.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk b2
br.cond.dptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.clr b2
br.cond.dptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.few b2
br.cond.dptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.few.clr b2
br.cond.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.many b2
br.cond.dptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dptk.many.clr b2
br.cond.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt b2
br.cond.dpnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.clr b2
br.cond.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.few b2
br.cond.dpnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.few.clr b2
br.cond.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.many b2
br.cond.dpnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.cond.dpnt.many.clr b2
br.cond.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.few b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.many b2
;; }
{ .bbb; nop.b 0;
nop.b 0
br.ia.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk b2
br.ret.sptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.clr b2
br.ret.sptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.few b2
br.ret.sptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.few.clr b2
br.ret.sptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.many b2
br.ret.sptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.sptk.many.clr b2
br.ret.sptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt b2
br.ret.spnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.clr b2
br.ret.spnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.few b2
br.ret.spnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.few.clr b2
br.ret.spnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.many b2
br.ret.spnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.spnt.many.clr b2
br.ret.spnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk b2
br.ret.dptk b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.clr b2
br.ret.dptk.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.few b2
br.ret.dptk.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.few.clr b2
br.ret.dptk.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.many b2
br.ret.dptk.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dptk.many.clr b2
br.ret.dptk.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt b2
br.ret.dpnt b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.clr b2
br.ret.dpnt.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.few b2
br.ret.dpnt.few b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.few.clr b2
br.ret.dpnt.few.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.many b2
br.ret.dpnt.many b2
;; }
{ .bbb; nop.b 0;
(p2) br.ret.dpnt.many.clr b2
br.ret.dpnt.many.clr b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk b0 = b2
br.call.sptk b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.clr b0 = b2
br.call.sptk.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.few b0 = b2
br.call.sptk.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.few.clr b0 = b2
br.call.sptk.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.many b0 = b2
br.call.sptk.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.sptk.many.clr b0 = b2
br.call.sptk.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt b0 = b2
br.call.spnt b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.clr b0 = b2
br.call.spnt.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.few b0 = b2
br.call.spnt.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.few.clr b0 = b2
br.call.spnt.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.many b0 = b2
br.call.spnt.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.spnt.many.clr b0 = b2
br.call.spnt.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk b0 = b2
br.call.dptk b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.clr b0 = b2
br.call.dptk.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.few b0 = b2
br.call.dptk.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.few.clr b0 = b2
br.call.dptk.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.many b0 = b2
br.call.dptk.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dptk.many.clr b0 = b2
br.call.dptk.many.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt b0 = b2
br.call.dpnt b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.clr b0 = b2
br.call.dpnt.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.few b0 = b2
br.call.dpnt.few b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.few.clr b0 = b2
br.call.dpnt.few.clr b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.many b0 = b2
br.call.dpnt.many b0 = b2
;; }
{ .bbb; nop.b 0;
(p2) br.call.dpnt.many.clr b0 = b2
br.call.dpnt.many.clr b0 = b2
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk .L0, .L2
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk.imp .L0, .L2
;; }
.L2:
{ .bbb; break.b 0; nop.b 0
brp.loop .L0, .L3
;; }
{ .bbb; break.b 0; nop.b 0
brp.loop.imp .L0, .L3
;; }
.L3:
{ .bbb; break.b 0; nop.b 0
brp.dptk .L0, .L4
;; }
{ .bbb; break.b 0; nop.b 0
brp.dptk.imp .L0, .L4
;; }
.L4:
{ .bbb; break.b 0; nop.b 0
brp.exit .L0, .L5
;; }
{ .bbb; break.b 0; nop.b 0
brp.exit.imp .L0, .L5
;; }
.L5:
{ .bbb; break.b 0; nop.b 0
brp.sptk b3, .L6
;; }
{ .bbb; break.b 0; nop.b 0
brp.sptk.imp b3, .L6
;; }
.L6:
{ .bbb; break.b 0; nop.b 0
brp.dptk b3, .L7
;; }
{ .bbb; break.b 0; nop.b 0
brp.dptk.imp b3, .L7
;; }
.L7:
{ .bbb; break.b 0; nop.b 0
brp.ret.sptk b3, .L8
;; }
{ .bbb; break.b 0; nop.b 0
brp.ret.sptk.imp b3, .L8
;; }
.L8:
{ .bbb; break.b 0; nop.b 0
brp.ret.dptk b3, .L9
;; }
{ .bbb; break.b 0; nop.b 0
brp.ret.dptk.imp b3, .L9
;; }
.L9:
.space 5888
{ .bbb; nop.b 0; nop.b 0; cover ;; }
{ .bbb; nop.b 0; nop.b 0; clrrrb ;; }
{ .bbb; nop.b 0; nop.b 0; clrrrb.pr ;; }
{ .bbb; nop.b 0; nop.b 0; rfi ;; }
{ .bbb; nop.b 0; nop.b 0; bsw.0 ;; }
{ .bbb; nop.b 0; nop.b 0; bsw.1 ;; }
{ .bbb; nop.b 0; nop.b 0; epc ;; }
.L1:
# instructions added by SDM2.1:
break.b 0x1ffff
hint.b @pause
hint.b 0x1ffff
nop.b 0x1ffff
# instructions added by SDM2.2:
vmsw.0
vmsw.1
|
stsp/binutils-ia16
| 1,741
|
gas/testsuite/gas/ia64/unwind-bad.s
|
.text
.proc full1
full1:
.prologue
.spill 0
.save.g 0
nop 0
.save.g 0x10
nop 0
.save.g -1
nop 0
.save.g 0x3
nop 0
.save.g 0x4
nop 0
.save.g 0x1
nop 0
.save.f 0
nop 0
.save.f 0x100000
nop 0
.save.f -1
nop 0
.save.f 0x3
nop 0
.save.f 0x4
nop 0
.save.f 0x1
nop 0
.save.b 0
nop 0
.save.b 0x20
nop 0
.save.b -1
nop 0
.save.b 0x3
nop 0
.save.b 0x4
nop 0
.save.b 0x1
nop 0
.spillreg r4, r0
nop 0
.spillreg r3, r2
nop 0
.spillreg r8, r9
nop 0
.spillreg b6, r10
nop 0
.spillreg f2, f0
nop 0
.spillreg f3, f1
nop 0
.spillreg f6, f7
nop 0
.spillreg f4, r11
nop 0
.spillreg f5, b0
nop 0
.spillreg.p p0, r4, r3
nop 0
.spillreg.p p1, r4, r0
nop 0
.spillreg.p p1, f16, f0
nop 0
.restorereg.p p0, r4
nop 0
.body
br.ret.sptk rp
.endp full1
.proc full2
full2:
.prologue
.spill 0
.save.gf 0, 0
nop 0
.save.gf 0x10, 0
nop 0
.save.gf 0, 0x100000
nop 0
.save.gf ~0, 0
nop 0
.save.gf 0, ~0
nop 0
.save.gf 1, 1
nop 0
.save.gf 2, 0
nop 0
.save.gf 1, 0
nop 0
.save.gf 0, 1
nop 0
.body
.label_state 1
.restore sp, 1
nop.x 0
.copy_state 2
br.ret.sptk rp
.endp full2
.proc full3
full3:
.prologue
.spill 0
.save.g 0x10, r16
nop 0
.save.g 0x01, r0
nop 0
.save.g 0x06, r127
nop 0
nop 0
.save.b 0x20, r16
nop 0
.save.b 0x01, r0
nop 0
.save.b 0x18, r127
nop 0
nop 0
.body
br.ret.sptk rp
.endp full3
.proc simple1
simple1:
.prologue 0x10, r2
br.ret.sptk rp
.endp simple1
.proc simple2
simple2:
.prologue 0, r2
br.ret.sptk rp
.endp simple2
.proc simple3
simple3:
.prologue -1, r2
.vframe r0
br.ret.sptk rp
.endp simple3
.proc simple4
simple4:
.prologue 0x1, r0
br.ret.sptk rp
.endp simple4
.proc simple5
simple5:
.prologue 0xc, r127
br.ret.sptk rp
.endp simple5
|
stsp/binutils-ia16
| 22,687
|
gas/testsuite/gas/ia64/opc-m.s
|
.text
.type _start,@function
_start:
ld1 r4 = [r5]
ld1 r4 = [r5], r6
ld1 r4 = [r5], -256
ld1.nt1 r4 = [r5]
ld1.nt1 r4 = [r5], r6
ld1.nt1 r4 = [r5], -243
ld1.nta r4 = [r5]
ld1.nta r4 = [r5], r6
ld1.nta r4 = [r5], -230
ld1.s r4 = [r5]
ld1.s r4 = [r5], r6
ld1.s r4 = [r5], -217
ld1.s.nt1 r4 = [r5]
ld1.s.nt1 r4 = [r5], r6
ld1.s.nt1 r4 = [r5], -204
ld1.s.nta r4 = [r5]
ld1.s.nta r4 = [r5], r6
ld1.s.nta r4 = [r5], -191
ld1.a r4 = [r5]
ld1.a r4 = [r5], r6
ld1.a r4 = [r5], -178
ld1.a.nt1 r4 = [r5]
ld1.a.nt1 r4 = [r5], r6
ld1.a.nt1 r4 = [r5], -165
ld1.a.nta r4 = [r5]
ld1.a.nta r4 = [r5], r6
ld1.a.nta r4 = [r5], -152
ld1.sa r4 = [r5]
ld1.sa r4 = [r5], r6
ld1.sa r4 = [r5], -139
ld1.sa.nt1 r4 = [r5]
ld1.sa.nt1 r4 = [r5], r6
ld1.sa.nt1 r4 = [r5], -126
ld1.sa.nta r4 = [r5]
ld1.sa.nta r4 = [r5], r6
ld1.sa.nta r4 = [r5], -113
ld1.c.clr r4 = [r5]
ld1.c.clr r4 = [r5], r6
ld1.c.clr r4 = [r5], -100
ld1.c.clr.nt1 r4 = [r5]
ld1.c.clr.nt1 r4 = [r5], r6
ld1.c.clr.nt1 r4 = [r5], -87
ld1.c.clr.nta r4 = [r5]
ld1.c.clr.nta r4 = [r5], r6
ld1.c.clr.nta r4 = [r5], -74
ld1.c.nc r4 = [r5]
ld1.c.nc r4 = [r5], r6
ld1.c.nc r4 = [r5], -61
ld1.c.nc.nt1 r4 = [r5]
ld1.c.nc.nt1 r4 = [r5], r6
ld1.c.nc.nt1 r4 = [r5], -48
ld1.c.nc.nta r4 = [r5]
ld1.c.nc.nta r4 = [r5], r6
ld1.c.nc.nta r4 = [r5], -35
ld1.bias r4 = [r5]
ld1.bias r4 = [r5], r6
ld1.bias r4 = [r5], -22
ld1.bias.nt1 r4 = [r5]
ld1.bias.nt1 r4 = [r5], r6
ld1.bias.nt1 r4 = [r5], -9
ld1.bias.nta r4 = [r5]
ld1.bias.nta r4 = [r5], r6
ld1.bias.nta r4 = [r5], 4
ld1.acq r4 = [r5]
ld1.acq r4 = [r5], r6
ld1.acq r4 = [r5], 17
ld1.acq.nt1 r4 = [r5]
ld1.acq.nt1 r4 = [r5], r6
ld1.acq.nt1 r4 = [r5], 30
ld1.acq.nta r4 = [r5]
ld1.acq.nta r4 = [r5], r6
ld1.acq.nta r4 = [r5], 43
ld1.c.clr.acq r4 = [r5]
ld1.c.clr.acq r4 = [r5], r6
ld1.c.clr.acq r4 = [r5], 56
ld1.c.clr.acq.nt1 r4 = [r5]
ld1.c.clr.acq.nt1 r4 = [r5], r6
ld1.c.clr.acq.nt1 r4 = [r5], 69
ld1.c.clr.acq.nta r4 = [r5]
ld1.c.clr.acq.nta r4 = [r5], r6
ld1.c.clr.acq.nta r4 = [r5], 82
ld2 r4 = [r5]
ld2 r4 = [r5], r6
ld2 r4 = [r5], 95
ld2.nt1 r4 = [r5]
ld2.nt1 r4 = [r5], r6
ld2.nt1 r4 = [r5], 108
ld2.nta r4 = [r5]
ld2.nta r4 = [r5], r6
ld2.nta r4 = [r5], 121
ld2.s r4 = [r5]
ld2.s r4 = [r5], r6
ld2.s r4 = [r5], 134
ld2.s.nt1 r4 = [r5]
ld2.s.nt1 r4 = [r5], r6
ld2.s.nt1 r4 = [r5], 147
ld2.s.nta r4 = [r5]
ld2.s.nta r4 = [r5], r6
ld2.s.nta r4 = [r5], 160
ld2.a r4 = [r5]
ld2.a r4 = [r5], r6
ld2.a r4 = [r5], 173
ld2.a.nt1 r4 = [r5]
ld2.a.nt1 r4 = [r5], r6
ld2.a.nt1 r4 = [r5], 186
ld2.a.nta r4 = [r5]
ld2.a.nta r4 = [r5], r6
ld2.a.nta r4 = [r5], 199
ld2.sa r4 = [r5]
ld2.sa r4 = [r5], r6
ld2.sa r4 = [r5], 212
ld2.sa.nt1 r4 = [r5]
ld2.sa.nt1 r4 = [r5], r6
ld2.sa.nt1 r4 = [r5], 225
ld2.sa.nta r4 = [r5]
ld2.sa.nta r4 = [r5], r6
ld2.sa.nta r4 = [r5], 238
ld2.c.clr r4 = [r5]
ld2.c.clr r4 = [r5], r6
ld2.c.clr r4 = [r5], 251
ld2.c.clr.nt1 r4 = [r5]
ld2.c.clr.nt1 r4 = [r5], r6
ld2.c.clr.nt1 r4 = [r5], -248
ld2.c.clr.nta r4 = [r5]
ld2.c.clr.nta r4 = [r5], r6
ld2.c.clr.nta r4 = [r5], -235
ld2.c.nc r4 = [r5]
ld2.c.nc r4 = [r5], r6
ld2.c.nc r4 = [r5], -222
ld2.c.nc.nt1 r4 = [r5]
ld2.c.nc.nt1 r4 = [r5], r6
ld2.c.nc.nt1 r4 = [r5], -209
ld2.c.nc.nta r4 = [r5]
ld2.c.nc.nta r4 = [r5], r6
ld2.c.nc.nta r4 = [r5], -196
ld2.bias r4 = [r5]
ld2.bias r4 = [r5], r6
ld2.bias r4 = [r5], -183
ld2.bias.nt1 r4 = [r5]
ld2.bias.nt1 r4 = [r5], r6
ld2.bias.nt1 r4 = [r5], -170
ld2.bias.nta r4 = [r5]
ld2.bias.nta r4 = [r5], r6
ld2.bias.nta r4 = [r5], -157
ld2.acq r4 = [r5]
ld2.acq r4 = [r5], r6
ld2.acq r4 = [r5], -144
ld2.acq.nt1 r4 = [r5]
ld2.acq.nt1 r4 = [r5], r6
ld2.acq.nt1 r4 = [r5], -131
ld2.acq.nta r4 = [r5]
ld2.acq.nta r4 = [r5], r6
ld2.acq.nta r4 = [r5], -118
ld2.c.clr.acq r4 = [r5]
ld2.c.clr.acq r4 = [r5], r6
ld2.c.clr.acq r4 = [r5], -105
ld2.c.clr.acq.nt1 r4 = [r5]
ld2.c.clr.acq.nt1 r4 = [r5], r6
ld2.c.clr.acq.nt1 r4 = [r5], -92
ld2.c.clr.acq.nta r4 = [r5]
ld2.c.clr.acq.nta r4 = [r5], r6
ld2.c.clr.acq.nta r4 = [r5], -79
ld4 r4 = [r5]
ld4 r4 = [r5], r6
ld4 r4 = [r5], -66
ld4.nt1 r4 = [r5]
ld4.nt1 r4 = [r5], r6
ld4.nt1 r4 = [r5], -53
ld4.nta r4 = [r5]
ld4.nta r4 = [r5], r6
ld4.nta r4 = [r5], -40
ld4.s r4 = [r5]
ld4.s r4 = [r5], r6
ld4.s r4 = [r5], -27
ld4.s.nt1 r4 = [r5]
ld4.s.nt1 r4 = [r5], r6
ld4.s.nt1 r4 = [r5], -14
ld4.s.nta r4 = [r5]
ld4.s.nta r4 = [r5], r6
ld4.s.nta r4 = [r5], -1
ld4.a r4 = [r5]
ld4.a r4 = [r5], r6
ld4.a r4 = [r5], 12
ld4.a.nt1 r4 = [r5]
ld4.a.nt1 r4 = [r5], r6
ld4.a.nt1 r4 = [r5], 25
ld4.a.nta r4 = [r5]
ld4.a.nta r4 = [r5], r6
ld4.a.nta r4 = [r5], 38
ld4.sa r4 = [r5]
ld4.sa r4 = [r5], r6
ld4.sa r4 = [r5], 51
ld4.sa.nt1 r4 = [r5]
ld4.sa.nt1 r4 = [r5], r6
ld4.sa.nt1 r4 = [r5], 64
ld4.sa.nta r4 = [r5]
ld4.sa.nta r4 = [r5], r6
ld4.sa.nta r4 = [r5], 77
ld4.c.clr r4 = [r5]
ld4.c.clr r4 = [r5], r6
ld4.c.clr r4 = [r5], 90
ld4.c.clr.nt1 r4 = [r5]
ld4.c.clr.nt1 r4 = [r5], r6
ld4.c.clr.nt1 r4 = [r5], 103
ld4.c.clr.nta r4 = [r5]
ld4.c.clr.nta r4 = [r5], r6
ld4.c.clr.nta r4 = [r5], 116
ld4.c.nc r4 = [r5]
ld4.c.nc r4 = [r5], r6
ld4.c.nc r4 = [r5], 129
ld4.c.nc.nt1 r4 = [r5]
ld4.c.nc.nt1 r4 = [r5], r6
ld4.c.nc.nt1 r4 = [r5], 142
ld4.c.nc.nta r4 = [r5]
ld4.c.nc.nta r4 = [r5], r6
ld4.c.nc.nta r4 = [r5], 155
ld4.bias r4 = [r5]
ld4.bias r4 = [r5], r6
ld4.bias r4 = [r5], 168
ld4.bias.nt1 r4 = [r5]
ld4.bias.nt1 r4 = [r5], r6
ld4.bias.nt1 r4 = [r5], 181
ld4.bias.nta r4 = [r5]
ld4.bias.nta r4 = [r5], r6
ld4.bias.nta r4 = [r5], 194
ld4.acq r4 = [r5]
ld4.acq r4 = [r5], r6
ld4.acq r4 = [r5], 207
ld4.acq.nt1 r4 = [r5]
ld4.acq.nt1 r4 = [r5], r6
ld4.acq.nt1 r4 = [r5], 220
ld4.acq.nta r4 = [r5]
ld4.acq.nta r4 = [r5], r6
ld4.acq.nta r4 = [r5], 233
ld4.c.clr.acq r4 = [r5]
ld4.c.clr.acq r4 = [r5], r6
ld4.c.clr.acq r4 = [r5], 246
ld4.c.clr.acq.nt1 r4 = [r5]
ld4.c.clr.acq.nt1 r4 = [r5], r6
ld4.c.clr.acq.nt1 r4 = [r5], -253
ld4.c.clr.acq.nta r4 = [r5]
ld4.c.clr.acq.nta r4 = [r5], r6
ld4.c.clr.acq.nta r4 = [r5], -240
ld8 r4 = [r5]
ld8 r4 = [r5], r6
ld8 r4 = [r5], -227
ld8.nt1 r4 = [r5]
ld8.nt1 r4 = [r5], r6
ld8.nt1 r4 = [r5], -214
ld8.nta r4 = [r5]
ld8.nta r4 = [r5], r6
ld8.nta r4 = [r5], -201
ld8.s r4 = [r5]
ld8.s r4 = [r5], r6
ld8.s r4 = [r5], -188
ld8.s.nt1 r4 = [r5]
ld8.s.nt1 r4 = [r5], r6
ld8.s.nt1 r4 = [r5], -175
ld8.s.nta r4 = [r5]
ld8.s.nta r4 = [r5], r6
ld8.s.nta r4 = [r5], -162
ld8.a r4 = [r5]
ld8.a r4 = [r5], r6
ld8.a r4 = [r5], -149
ld8.a.nt1 r4 = [r5]
ld8.a.nt1 r4 = [r5], r6
ld8.a.nt1 r4 = [r5], -136
ld8.a.nta r4 = [r5]
ld8.a.nta r4 = [r5], r6
ld8.a.nta r4 = [r5], -123
ld8.sa r4 = [r5]
ld8.sa r4 = [r5], r6
ld8.sa r4 = [r5], -110
ld8.sa.nt1 r4 = [r5]
ld8.sa.nt1 r4 = [r5], r6
ld8.sa.nt1 r4 = [r5], -97
ld8.sa.nta r4 = [r5]
ld8.sa.nta r4 = [r5], r6
ld8.sa.nta r4 = [r5], -84
ld8.c.clr r4 = [r5]
ld8.c.clr r4 = [r5], r6
ld8.c.clr r4 = [r5], -71
ld8.c.clr.nt1 r4 = [r5]
ld8.c.clr.nt1 r4 = [r5], r6
ld8.c.clr.nt1 r4 = [r5], -58
ld8.c.clr.nta r4 = [r5]
ld8.c.clr.nta r4 = [r5], r6
ld8.c.clr.nta r4 = [r5], -45
ld8.c.nc r4 = [r5]
ld8.c.nc r4 = [r5], r6
ld8.c.nc r4 = [r5], -32
ld8.c.nc.nt1 r4 = [r5]
ld8.c.nc.nt1 r4 = [r5], r6
ld8.c.nc.nt1 r4 = [r5], -19
ld8.c.nc.nta r4 = [r5]
ld8.c.nc.nta r4 = [r5], r6
ld8.c.nc.nta r4 = [r5], -6
ld8.bias r4 = [r5]
ld8.bias r4 = [r5], r6
ld8.bias r4 = [r5], 7
ld8.bias.nt1 r4 = [r5]
ld8.bias.nt1 r4 = [r5], r6
ld8.bias.nt1 r4 = [r5], 20
ld8.bias.nta r4 = [r5]
ld8.bias.nta r4 = [r5], r6
ld8.bias.nta r4 = [r5], 33
ld8.acq r4 = [r5]
ld8.acq r4 = [r5], r6
ld8.acq r4 = [r5], 46
ld8.acq.nt1 r4 = [r5]
ld8.acq.nt1 r4 = [r5], r6
ld8.acq.nt1 r4 = [r5], 59
ld8.acq.nta r4 = [r5]
ld8.acq.nta r4 = [r5], r6
ld8.acq.nta r4 = [r5], 72
ld8.c.clr.acq r4 = [r5]
ld8.c.clr.acq r4 = [r5], r6
ld8.c.clr.acq r4 = [r5], 85
ld8.c.clr.acq.nt1 r4 = [r5]
ld8.c.clr.acq.nt1 r4 = [r5], r6
ld8.c.clr.acq.nt1 r4 = [r5], 98
ld8.c.clr.acq.nta r4 = [r5]
ld8.c.clr.acq.nta r4 = [r5], r6
ld8.c.clr.acq.nta r4 = [r5], 111
ld8.fill r4 = [r5]
ld8.fill r4 = [r5], r6
ld8.fill r4 = [r5], 124
ld8.fill.nt1 r4 = [r5]
ld8.fill.nt1 r4 = [r5], r6
ld8.fill.nt1 r4 = [r5], 137
ld8.fill.nta r4 = [r5]
ld8.fill.nta r4 = [r5], r6
ld8.fill.nta r4 = [r5], 150
st1 [r4] = r5
st1 [r4] = r5, 163
st1.nta [r4] = r5
st1.nta [r4] = r5, 176
st2 [r4] = r5
st2 [r4] = r5, 189
st2.nta [r4] = r5
st2.nta [r4] = r5, 202
st4 [r4] = r5
st4 [r4] = r5, 215
st4.nta [r4] = r5
st4.nta [r4] = r5, 228
st8 [r4] = r5
st8 [r4] = r5, 241
st8.nta [r4] = r5
st8.nta [r4] = r5, 254
st1.rel [r4] = r5
st1.rel [r4] = r5, -245
st1.rel.nta [r4] = r5
st1.rel.nta [r4] = r5, -232
st2.rel [r4] = r5
st2.rel [r4] = r5, -219
st2.rel.nta [r4] = r5
st2.rel.nta [r4] = r5, -206
st4.rel [r4] = r5
st4.rel [r4] = r5, -193
st4.rel.nta [r4] = r5
st4.rel.nta [r4] = r5, -180
st8.rel [r4] = r5
st8.rel [r4] = r5, -167
st8.rel.nta [r4] = r5
st8.rel.nta [r4] = r5, -154
st8.spill [r4] = r5
st8.spill [r4] = r5, -141
st8.spill.nta [r4] = r5
st8.spill.nta [r4] = r5, -128
ldfs f4 = [r5]
ldfs f4 = [r5], r6
ldfs f4 = [r5], -115
ldfs.nt1 f4 = [r5]
ldfs.nt1 f4 = [r5], r6
ldfs.nt1 f4 = [r5], -102
ldfs.nta f4 = [r5]
ldfs.nta f4 = [r5], r6
ldfs.nta f4 = [r5], -89
ldfs.s f4 = [r5]
ldfs.s f4 = [r5], r6
ldfs.s f4 = [r5], -76
ldfs.s.nt1 f4 = [r5]
ldfs.s.nt1 f4 = [r5], r6
ldfs.s.nt1 f4 = [r5], -63
ldfs.s.nta f4 = [r5]
ldfs.s.nta f4 = [r5], r6
ldfs.s.nta f4 = [r5], -50
ldfs.a f4 = [r5]
ldfs.a f4 = [r5], r6
ldfs.a f4 = [r5], -37
ldfs.a.nt1 f4 = [r5]
ldfs.a.nt1 f4 = [r5], r6
ldfs.a.nt1 f4 = [r5], -24
ldfs.a.nta f4 = [r5]
ldfs.a.nta f4 = [r5], r6
ldfs.a.nta f4 = [r5], -11
ldfs.sa f4 = [r5]
ldfs.sa f4 = [r5], r6
ldfs.sa f4 = [r5], 2
ldfs.sa.nt1 f4 = [r5]
ldfs.sa.nt1 f4 = [r5], r6
ldfs.sa.nt1 f4 = [r5], 15
ldfs.sa.nta f4 = [r5]
ldfs.sa.nta f4 = [r5], r6
ldfs.sa.nta f4 = [r5], 28
ldfs.c.clr f4 = [r5]
ldfs.c.clr f4 = [r5], r6
ldfs.c.clr f4 = [r5], 41
ldfs.c.clr.nt1 f4 = [r5]
ldfs.c.clr.nt1 f4 = [r5], r6
ldfs.c.clr.nt1 f4 = [r5], 54
ldfs.c.clr.nta f4 = [r5]
ldfs.c.clr.nta f4 = [r5], r6
ldfs.c.clr.nta f4 = [r5], 67
ldfs.c.nc f4 = [r5]
ldfs.c.nc f4 = [r5], r6
ldfs.c.nc f4 = [r5], 80
ldfs.c.nc.nt1 f4 = [r5]
ldfs.c.nc.nt1 f4 = [r5], r6
ldfs.c.nc.nt1 f4 = [r5], 93
ldfs.c.nc.nta f4 = [r5]
ldfs.c.nc.nta f4 = [r5], r6
ldfs.c.nc.nta f4 = [r5], 106
ldfd f4 = [r5]
ldfd f4 = [r5], r6
ldfd f4 = [r5], 119
ldfd.nt1 f4 = [r5]
ldfd.nt1 f4 = [r5], r6
ldfd.nt1 f4 = [r5], 132
ldfd.nta f4 = [r5]
ldfd.nta f4 = [r5], r6
ldfd.nta f4 = [r5], 145
ldfd.s f4 = [r5]
ldfd.s f4 = [r5], r6
ldfd.s f4 = [r5], 158
ldfd.s.nt1 f4 = [r5]
ldfd.s.nt1 f4 = [r5], r6
ldfd.s.nt1 f4 = [r5], 171
ldfd.s.nta f4 = [r5]
ldfd.s.nta f4 = [r5], r6
ldfd.s.nta f4 = [r5], 184
ldfd.a f4 = [r5]
ldfd.a f4 = [r5], r6
ldfd.a f4 = [r5], 197
ldfd.a.nt1 f4 = [r5]
ldfd.a.nt1 f4 = [r5], r6
ldfd.a.nt1 f4 = [r5], 210
ldfd.a.nta f4 = [r5]
ldfd.a.nta f4 = [r5], r6
ldfd.a.nta f4 = [r5], 223
ldfd.sa f4 = [r5]
ldfd.sa f4 = [r5], r6
ldfd.sa f4 = [r5], 236
ldfd.sa.nt1 f4 = [r5]
ldfd.sa.nt1 f4 = [r5], r6
ldfd.sa.nt1 f4 = [r5], 249
ldfd.sa.nta f4 = [r5]
ldfd.sa.nta f4 = [r5], r6
ldfd.sa.nta f4 = [r5], -250
ldfd.c.clr f4 = [r5]
ldfd.c.clr f4 = [r5], r6
ldfd.c.clr f4 = [r5], -237
ldfd.c.clr.nt1 f4 = [r5]
ldfd.c.clr.nt1 f4 = [r5], r6
ldfd.c.clr.nt1 f4 = [r5], -224
ldfd.c.clr.nta f4 = [r5]
ldfd.c.clr.nta f4 = [r5], r6
ldfd.c.clr.nta f4 = [r5], -211
ldfd.c.nc f4 = [r5]
ldfd.c.nc f4 = [r5], r6
ldfd.c.nc f4 = [r5], -198
ldfd.c.nc.nt1 f4 = [r5]
ldfd.c.nc.nt1 f4 = [r5], r6
ldfd.c.nc.nt1 f4 = [r5], -185
ldfd.c.nc.nta f4 = [r5]
ldfd.c.nc.nta f4 = [r5], r6
ldfd.c.nc.nta f4 = [r5], -172
ldf8 f4 = [r5]
ldf8 f4 = [r5], r6
ldf8 f4 = [r5], -159
ldf8.nt1 f4 = [r5]
ldf8.nt1 f4 = [r5], r6
ldf8.nt1 f4 = [r5], -146
ldf8.nta f4 = [r5]
ldf8.nta f4 = [r5], r6
ldf8.nta f4 = [r5], -133
ldf8.s f4 = [r5]
ldf8.s f4 = [r5], r6
ldf8.s f4 = [r5], -120
ldf8.s.nt1 f4 = [r5]
ldf8.s.nt1 f4 = [r5], r6
ldf8.s.nt1 f4 = [r5], -107
ldf8.s.nta f4 = [r5]
ldf8.s.nta f4 = [r5], r6
ldf8.s.nta f4 = [r5], -94
ldf8.a f4 = [r5]
ldf8.a f4 = [r5], r6
ldf8.a f4 = [r5], -81
ldf8.a.nt1 f4 = [r5]
ldf8.a.nt1 f4 = [r5], r6
ldf8.a.nt1 f4 = [r5], -68
ldf8.a.nta f4 = [r5]
ldf8.a.nta f4 = [r5], r6
ldf8.a.nta f4 = [r5], -55
ldf8.sa f4 = [r5]
ldf8.sa f4 = [r5], r6
ldf8.sa f4 = [r5], -42
ldf8.sa.nt1 f4 = [r5]
ldf8.sa.nt1 f4 = [r5], r6
ldf8.sa.nt1 f4 = [r5], -29
ldf8.sa.nta f4 = [r5]
ldf8.sa.nta f4 = [r5], r6
ldf8.sa.nta f4 = [r5], -16
ldf8.c.clr f4 = [r5]
ldf8.c.clr f4 = [r5], r6
ldf8.c.clr f4 = [r5], -3
ldf8.c.clr.nt1 f4 = [r5]
ldf8.c.clr.nt1 f4 = [r5], r6
ldf8.c.clr.nt1 f4 = [r5], 10
ldf8.c.clr.nta f4 = [r5]
ldf8.c.clr.nta f4 = [r5], r6
ldf8.c.clr.nta f4 = [r5], 23
ldf8.c.nc f4 = [r5]
ldf8.c.nc f4 = [r5], r6
ldf8.c.nc f4 = [r5], 36
ldf8.c.nc.nt1 f4 = [r5]
ldf8.c.nc.nt1 f4 = [r5], r6
ldf8.c.nc.nt1 f4 = [r5], 49
ldf8.c.nc.nta f4 = [r5]
ldf8.c.nc.nta f4 = [r5], r6
ldf8.c.nc.nta f4 = [r5], 62
ldfe f4 = [r5]
ldfe f4 = [r5], r6
ldfe f4 = [r5], 75
ldfe.nt1 f4 = [r5]
ldfe.nt1 f4 = [r5], r6
ldfe.nt1 f4 = [r5], 88
ldfe.nta f4 = [r5]
ldfe.nta f4 = [r5], r6
ldfe.nta f4 = [r5], 101
ldfe.s f4 = [r5]
ldfe.s f4 = [r5], r6
ldfe.s f4 = [r5], 114
ldfe.s.nt1 f4 = [r5]
ldfe.s.nt1 f4 = [r5], r6
ldfe.s.nt1 f4 = [r5], 127
ldfe.s.nta f4 = [r5]
ldfe.s.nta f4 = [r5], r6
ldfe.s.nta f4 = [r5], 140
ldfe.a f4 = [r5]
ldfe.a f4 = [r5], r6
ldfe.a f4 = [r5], 153
ldfe.a.nt1 f4 = [r5]
ldfe.a.nt1 f4 = [r5], r6
ldfe.a.nt1 f4 = [r5], 166
ldfe.a.nta f4 = [r5]
ldfe.a.nta f4 = [r5], r6
ldfe.a.nta f4 = [r5], 179
ldfe.sa f4 = [r5]
ldfe.sa f4 = [r5], r6
ldfe.sa f4 = [r5], 192
ldfe.sa.nt1 f4 = [r5]
ldfe.sa.nt1 f4 = [r5], r6
ldfe.sa.nt1 f4 = [r5], 205
ldfe.sa.nta f4 = [r5]
ldfe.sa.nta f4 = [r5], r6
ldfe.sa.nta f4 = [r5], 218
ldfe.c.clr f4 = [r5]
ldfe.c.clr f4 = [r5], r6
ldfe.c.clr f4 = [r5], 231
ldfe.c.clr.nt1 f4 = [r5]
ldfe.c.clr.nt1 f4 = [r5], r6
ldfe.c.clr.nt1 f4 = [r5], 244
ldfe.c.clr.nta f4 = [r5]
ldfe.c.clr.nta f4 = [r5], r6
ldfe.c.clr.nta f4 = [r5], -255
ldfe.c.nc f4 = [r5]
ldfe.c.nc f4 = [r5], r6
ldfe.c.nc f4 = [r5], -242
ldfe.c.nc.nt1 f4 = [r5]
ldfe.c.nc.nt1 f4 = [r5], r6
ldfe.c.nc.nt1 f4 = [r5], -229
ldfe.c.nc.nta f4 = [r5]
ldfe.c.nc.nta f4 = [r5], r6
ldfe.c.nc.nta f4 = [r5], -216
ldf.fill f4 = [r5]
ldf.fill f4 = [r5], r6
ldf.fill f4 = [r5], -203
ldf.fill.nt1 f4 = [r5]
ldf.fill.nt1 f4 = [r5], r6
ldf.fill.nt1 f4 = [r5], -190
ldf.fill.nta f4 = [r5]
ldf.fill.nta f4 = [r5], r6
ldf.fill.nta f4 = [r5], -177
stfs [r4] = f5
stfs [r4] = f5, -164
stfs.nta [r4] = f5
stfs.nta [r4] = f5, -151
stfd [r4] = f5
stfd [r4] = f5, -138
stfd.nta [r4] = f5
stfd.nta [r4] = f5, -125
stf8 [r4] = f5
stf8 [r4] = f5, -112
stf8.nta [r4] = f5
stf8.nta [r4] = f5, -99
stfe [r4] = f5
stfe [r4] = f5, -86
stfe.nta [r4] = f5
stfe.nta [r4] = f5, -73
stf.spill [r4] = f5
stf.spill [r4] = f5, -60
stf.spill.nta [r4] = f5
stf.spill.nta [r4] = f5, -47
ldfps f4, f5 = [r5]
ldfps f4, f5 = [r5], 8
ldfps.nt1 f4, f5 = [r5]
ldfps.nt1 f4, f5 = [r5], 8
ldfps.nta f4, f5 = [r5]
ldfps.nta f4, f5 = [r5], 8
ldfps.s f4, f5 = [r5]
ldfps.s f4, f5 = [r5], 8
ldfps.s.nt1 f4, f5 = [r5]
ldfps.s.nt1 f4, f5 = [r5], 8
ldfps.s.nta f4, f5 = [r5]
ldfps.s.nta f4, f5 = [r5], 8
ldfps.a f4, f5 = [r5]
ldfps.a f4, f5 = [r5], 8
ldfps.a.nt1 f4, f5 = [r5]
ldfps.a.nt1 f4, f5 = [r5], 8
ldfps.a.nta f4, f5 = [r5]
ldfps.a.nta f4, f5 = [r5], 8
ldfps.sa f4, f5 = [r5]
ldfps.sa f4, f5 = [r5], 8
ldfps.sa.nt1 f4, f5 = [r5]
ldfps.sa.nt1 f4, f5 = [r5], 8
ldfps.sa.nta f4, f5 = [r5]
ldfps.sa.nta f4, f5 = [r5], 8
ldfps.c.clr f4, f5 = [r5]
ldfps.c.clr f4, f5 = [r5], 8
ldfps.c.clr.nt1 f4, f5 = [r5]
ldfps.c.clr.nt1 f4, f5 = [r5], 8
ldfps.c.clr.nta f4, f5 = [r5]
ldfps.c.clr.nta f4, f5 = [r5], 8
ldfps.c.nc f4, f5 = [r5]
ldfps.c.nc f4, f5 = [r5], 8
ldfps.c.nc.nt1 f4, f5 = [r5]
ldfps.c.nc.nt1 f4, f5 = [r5], 8
ldfps.c.nc.nta f4, f5 = [r5]
ldfps.c.nc.nta f4, f5 = [r5], 8
ldfpd f4, f5 = [r5]
ldfpd f4, f5 = [r5], 16
ldfpd.nt1 f4, f5 = [r5]
ldfpd.nt1 f4, f5 = [r5], 16
ldfpd.nta f4, f5 = [r5]
ldfpd.nta f4, f5 = [r5], 16
ldfpd.s f4, f5 = [r5]
ldfpd.s f4, f5 = [r5], 16
ldfpd.s.nt1 f4, f5 = [r5]
ldfpd.s.nt1 f4, f5 = [r5], 16
ldfpd.s.nta f4, f5 = [r5]
ldfpd.s.nta f4, f5 = [r5], 16
ldfpd.a f4, f5 = [r5]
ldfpd.a f4, f5 = [r5], 16
ldfpd.a.nt1 f4, f5 = [r5]
ldfpd.a.nt1 f4, f5 = [r5], 16
ldfpd.a.nta f4, f5 = [r5]
ldfpd.a.nta f4, f5 = [r5], 16
ldfpd.sa f4, f5 = [r5]
ldfpd.sa f4, f5 = [r5], 16
ldfpd.sa.nt1 f4, f5 = [r5]
ldfpd.sa.nt1 f4, f5 = [r5], 16
ldfpd.sa.nta f4, f5 = [r5]
ldfpd.sa.nta f4, f5 = [r5], 16
ldfpd.c.clr f4, f5 = [r5]
ldfpd.c.clr f4, f5 = [r5], 16
ldfpd.c.clr.nt1 f4, f5 = [r5]
ldfpd.c.clr.nt1 f4, f5 = [r5], 16
ldfpd.c.clr.nta f4, f5 = [r5]
ldfpd.c.clr.nta f4, f5 = [r5], 16
ldfpd.c.nc f4, f5 = [r5]
ldfpd.c.nc f4, f5 = [r5], 16
ldfpd.c.nc.nt1 f4, f5 = [r5]
ldfpd.c.nc.nt1 f4, f5 = [r5], 16
ldfpd.c.nc.nta f4, f5 = [r5]
ldfpd.c.nc.nta f4, f5 = [r5], 16
ldfp8 f4, f5 = [r5]
ldfp8 f4, f5 = [r5], 16
ldfp8.nt1 f4, f5 = [r5]
ldfp8.nt1 f4, f5 = [r5], 16
ldfp8.nta f4, f5 = [r5]
ldfp8.nta f4, f5 = [r5], 16
ldfp8.s f4, f5 = [r5]
ldfp8.s f4, f5 = [r5], 16
ldfp8.s.nt1 f4, f5 = [r5]
ldfp8.s.nt1 f4, f5 = [r5], 16
ldfp8.s.nta f4, f5 = [r5]
ldfp8.s.nta f4, f5 = [r5], 16
ldfp8.a f4, f5 = [r5]
ldfp8.a f4, f5 = [r5], 16
ldfp8.a.nt1 f4, f5 = [r5]
ldfp8.a.nt1 f4, f5 = [r5], 16
ldfp8.a.nta f4, f5 = [r5]
ldfp8.a.nta f4, f5 = [r5], 16
ldfp8.sa f4, f5 = [r5]
ldfp8.sa f4, f5 = [r5], 16
ldfp8.sa.nt1 f4, f5 = [r5]
ldfp8.sa.nt1 f4, f5 = [r5], 16
ldfp8.sa.nta f4, f5 = [r5]
ldfp8.sa.nta f4, f5 = [r5], 16
ldfp8.c.clr f4, f5 = [r5]
ldfp8.c.clr f4, f5 = [r5], 16
ldfp8.c.clr.nt1 f4, f5 = [r5]
ldfp8.c.clr.nt1 f4, f5 = [r5], 16
ldfp8.c.clr.nta f4, f5 = [r5]
ldfp8.c.clr.nta f4, f5 = [r5], 16
ldfp8.c.nc f4, f5 = [r5]
ldfp8.c.nc f4, f5 = [r5], 16
ldfp8.c.nc.nt1 f4, f5 = [r5]
ldfp8.c.nc.nt1 f4, f5 = [r5], 16
ldfp8.c.nc.nta f4, f5 = [r5]
ldfp8.c.nc.nta f4, f5 = [r5], 16
lfetch [r4]
lfetch [r4], r5
lfetch [r4], -34
lfetch.nt1 [r4]
lfetch.nt1 [r4], r5
lfetch.nt1 [r4], -21
lfetch.nt2 [r4]
lfetch.nt2 [r4], r5
lfetch.nt2 [r4], -8
lfetch.nta [r4]
lfetch.nta [r4], r5
lfetch.nta [r4], 5
lfetch.fault [r4]
lfetch.fault [r4], r5
lfetch.fault [r4], 18
lfetch.fault.nt1 [r4]
lfetch.fault.nt1 [r4], r5
lfetch.fault.nt1 [r4], 31
lfetch.fault.nt2 [r4]
lfetch.fault.nt2 [r4], r5
lfetch.fault.nt2 [r4], 44
lfetch.fault.nta [r4]
lfetch.fault.nta [r4], r5
lfetch.fault.nta [r4], 57
lfetch.excl [r4]
lfetch.excl [r4], r5
lfetch.excl [r4], 70
lfetch.excl.nt1 [r4]
lfetch.excl.nt1 [r4], r5
lfetch.excl.nt1 [r4], 83
lfetch.excl.nt2 [r4]
lfetch.excl.nt2 [r4], r5
lfetch.excl.nt2 [r4], 96
lfetch.excl.nta [r4]
lfetch.excl.nta [r4], r5
lfetch.excl.nta [r4], 109
lfetch.fault.excl [r4]
lfetch.fault.excl [r4], r5
lfetch.fault.excl [r4], 122
lfetch.fault.excl.nt1 [r4]
lfetch.fault.excl.nt1 [r4], r5
lfetch.fault.excl.nt1 [r4], 135
lfetch.fault.excl.nt2 [r4]
lfetch.fault.excl.nt2 [r4], r5
lfetch.fault.excl.nt2 [r4], 148
lfetch.fault.excl.nta [r4]
lfetch.fault.excl.nta [r4], r5
lfetch.fault.excl.nta [r4], 161
cmpxchg1.acq r4 = [r5], r6, ar.ccv
cmpxchg1.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg1.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg1.rel r4 = [r5], r6, ar.ccv
cmpxchg1.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg1.rel.nta r4 = [r5], r6, ar.ccv
cmpxchg2.acq r4 = [r5], r6, ar.ccv
cmpxchg2.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg2.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg2.rel r4 = [r5], r6, ar.ccv
cmpxchg2.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg2.rel.nta r4 = [r5], r6, ar.ccv
cmpxchg4.acq r4 = [r5], r6, ar.ccv
cmpxchg4.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg4.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg4.rel r4 = [r5], r6, ar.ccv
cmpxchg4.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg4.rel.nta r4 = [r5], r6, ar.ccv
cmpxchg8.acq r4 = [r5], r6, ar.ccv
cmpxchg8.acq.nt1 r4 = [r5], r6, ar.ccv
cmpxchg8.acq.nta r4 = [r5], r6, ar.ccv
cmpxchg8.rel r4 = [r5], r6, ar.ccv
cmpxchg8.rel.nt1 r4 = [r5], r6, ar.ccv
cmpxchg8.rel.nta r4 = [r5], r6, ar.ccv
xchg1 r4 = [r5], r6
xchg1.nt1 r4 = [r5], r6
xchg1.nta r4 = [r5], r6
xchg2 r4 = [r5], r6
xchg2.nt1 r4 = [r5], r6
xchg2.nta r4 = [r5], r6
xchg4 r4 = [r5], r6
xchg4.nt1 r4 = [r5], r6
xchg4.nta r4 = [r5], r6
xchg8 r4 = [r5], r6
xchg8.nt1 r4 = [r5], r6
xchg8.nta r4 = [r5], r6
fetchadd4.acq r4 = [r5], -16
fetchadd4.acq.nt1 r4 = [r5], -8
fetchadd4.acq.nta r4 = [r5], -4
fetchadd8.acq r4 = [r5], -1
fetchadd8.acq.nt1 r4 = [r5], 1
fetchadd8.acq.nta r4 = [r5], 4
fetchadd4.rel r4 = [r5], 8
fetchadd4.rel.nt1 r4 = [r5], 16
fetchadd4.rel.nta r4 = [r5], -16
fetchadd8.rel r4 = [r5], -8
fetchadd8.rel.nt1 r4 = [r5], -4
fetchadd8.rel.nta r4 = [r5], -1
setf.sig f4 = r5
setf.exp f4 = r5
setf.s f4 = r5
setf.d f4 = r5
getf.sig r4 = f5
getf.exp r4 = f5
getf.s r4 = f5
getf.d r4 = f5
chk.s.m r4, _start
chk.s f4, _start
chk.a.nc r4, _start
chk.a.clr r4, _start
chk.a.nc f4, _start
chk.a.clr f4, _start
invala
fwb
mf
mf.a
srlz.d
srlz.i
sync.i
nop.m 0
nop.i 0;;
{ .mii; alloc r4 = ar.pfs, 2, 10, 16, 16;; }
{ .mii; flushrs;; }
{ .mii; loadrs }
invala.e r4
invala.e f4
fc r4
ptc.e r4
break.m 0
break.m 0x1ffff
nop.m 0
nop.m 0x1ffff
probe.r r4 = r5, r6
probe.w r4 = r5, r6
probe.r r4 = r5, 0
probe.w r4 = r5, 1
probe.r.fault r3, 2
probe.w.fault r3, 3
probe.rw.fault r3, 0
{ .mmi; itc.d r8;; nop.m 0x0; nop.i 0x0;; }
itc.i r9;;
sum 0x1234
rum 0x5aaaaa
ssm 0xffffff
rsm 0x400000
ptc.l r4, r5
{ .mmi; ptc.g r4, r5;; nop.m 0x0; nop.i 0x0 }
{ .mmi; ptc.ga r4, r5;; nop.m 0x0; nop.i 0x0 }
ptr.d r4, r5
ptr.i r4, r5
thash r4 = r5
ttag r4 = r5
tpa r4 = r5
tak r4 = r5
# instructions added by SDM2.1:
hint.m 0
hint.m @pause
hint.m 0x1ffff
cmp8xchg16.acq r4 = [r5], r6, ar25, ar.ccv
cmp8xchg16.acq.nt1 r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.acq.nta r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel.nt1 r4 = [r5], r6, ar.csd, ar.ccv
cmp8xchg16.rel.nta r4 = [r5], r6, ar.csd, ar.ccv
fc.i r4
ld16 r4, ar25 = [r5]
ld16.nt1 r4, ar.csd = [r5]
ld16.nta r4, ar.csd = [r5]
ld16.acq r4, ar25 = [r5]
ld16.acq.nt1 r4, ar.csd = [r5]
ld16.acq.nta r4, ar.csd = [r5]
st16 [r4] = r5, ar25
st16.nta [r4] = r5, ar.csd
st16.rel [r4] = r5, ar.csd
st16.rel.nta [r4] = r5, ar.csd
|
stsp/binutils-ia16
| 1,260
|
gas/testsuite/gas/ia64/xdata.s
|
// Note that most of the section names used here aren't legal as operands
// to either .section or .xdata/.xreal/.xstring (quoted strings aren't in
// general), but since generic code accepts them for .section we also test
// this here for our target specific directives. This could be viewed as a
// shortcut of a pair of .section/.secalias for each of them.
.section .xdata1, "a", @progbits
.section ".xdata2", "a", @progbits
.section ",xdata3", "a", @progbits
.section ".xdata,4", "a", @progbits
.section "\".xdata5\"", "a", @progbits
.section ".xreal\\1", "a", @progbits
.section ".xreal+2", "a", @progbits
.section ".xreal(3)", "a", @progbits
.section ".xreal[4]", "a", @progbits
.section ".xstr<1>", "a", @progbits
.section ".xstr{2}", "a", @progbits
.text
.xdata1 .xdata1, 1
.xdata2 ".xdata2", 2
.xdata4 ",xdata3", 3
.xdata8 ".xdata,4", 4
.xdata16 "\".xdata5\"", @iplt(_start)
.xdata2.ua ".xdata2", 2
.xdata4.ua ",xdata3", 3
.xdata8.ua ".xdata,4", 4
.xdata16.ua "\".xdata5\"", @iplt(_start)
.xreal4 ".xreal\\1", 1
.xreal8 ".xreal+2", 2
.xreal10 ".xreal(3)", 3
.xreal16 ".xreal[4]", 4
.xreal4.ua ".xreal\\1", 1
.xreal8.ua ".xreal+2", 2
.xreal10.ua ".xreal(3)", 3
.xreal16.ua ".xreal[4]", 4
.xstring ".xstr<1>", "abc"
.xstringz ".xstr{2}", "xyz"
|
stsp/binutils-ia16
| 7,828
|
gas/testsuite/gas/ia64/dv-waw-err.s
|
//
// Detect WAW violations. Cases taken from DV tables.
//
.text
.explicit
// AR[BSP]
mov ar.bsp = r0
mov ar.bsp = r1
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov ar.bspstore = r3
;;
// AR[CCV]
mov ar.ccv = r4
mov ar.ccv = r4
;;
// AR[EC]
br.wtop.sptk L
mov ar.ec = r0
;;
// AR[FPSR].sf0.controls
mov ar.fpsr = r0
fsetc.s0 0x7f, 0x0f
;;
// AR[FPSR].sf1.controls
mov ar.fpsr = r0
fsetc.s1 0x7f, 0x0f
;;
// AR[FPSR].sf2.controls
mov ar.fpsr = r0
fsetc.s2 0x7f, 0x0f
;;
// AR[FPSR].sf3.controls
mov ar.fpsr = r0
fsetc.s3 0x7f, 0x0f
;;
// AR[FPSR].sf0.flags
fcmp.eq.s0 p1, p2 = f3, f4
fcmp.eq.s0 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s0 p1, p2 = f3, f4
fclrf.s0
;;
// AR[FPSR].sf1.flags
fcmp.eq.s1 p1, p2 = f3, f4
fcmp.eq.s1 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s1 p1, p2 = f3, f4
fclrf.s1
;;
// AR[FPSR].sf2.flags
fcmp.eq.s2 p1, p2 = f3, f4
fcmp.eq.s2 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s2 p1, p2 = f3, f4
fclrf.s2
;;
// AR[FPSR].sf3.flags
fcmp.eq.s3 p1, p2 = f3, f4
fcmp.eq.s3 p3, p4 = f3, f4 // no DV here
;;
fcmp.eq.s3 p1, p2 = f3, f4
fclrf.s3
;;
// AR[FPSR].traps/rv plus all controls/flags
mov ar.fpsr = r0
mov ar.fpsr = r0
;;
// AR[ITC]
mov ar.itc = r1
mov ar.itc = r1
;;
// AR[RUC]
mov ar.ruc = r1
mov ar.ruc = r1
;;
// AR[K]
mov ar.k2 = r3
mov ar.k2 = r3
;;
// AR[LC]
br.cloop.sptk L
mov ar.lc = r0
;;
// AR[PFS]
mov ar.pfs = r0
br.call.sptk b0 = L
;;
// AR[RNAT] (see also AR[BSPSTORE])
mov ar.rnat = r8
mov ar.rnat = r8
;;
// AR[RSC]
mov ar.rsc = r10
mov ar.rsc = r10
;;
// AR[UNAT]
mov ar.unat = r12
st8.spill [r0] = r1
;;
// AR%
mov ar48 = r0
mov ar48 = r0
;;
// BR%
mov b1 = r0
mov b1 = r1
;;
// CFM (and others)
br.wtop.sptk L
br.wtop.sptk L
;;
// CR[CMCV]
mov cr.cmcv = r1
mov cr.cmcv = r2
;;
// CR[DCR]
mov cr.dcr = r3
mov cr.dcr = r3
;;
// CR[EOI] (and InService)
mov cr.eoi = r0
mov cr.eoi = r0
;;
srlz.d
// CR[GPTA]
mov cr.gpta = r6
mov cr.gpta = r7
;;
// CR[IFA]
mov cr.ifa = r9
mov cr.ifa = r10
;;
// CR[IFS]
mov cr.ifs = r11
cover
;;
// CR[IHA]
mov cr.iha = r13
mov cr.iha = r14
;;
// CR[IIB%]
mov cr.iib0 = r15
mov cr.iib0 = r16
;;
mov cr.iib1 = r15
mov cr.iib1 = r16
;;
// CR[IIM]
mov cr.iim = r15
mov cr.iim = r16
;;
// CR[IIP]
mov cr.iip = r17
mov cr.iip = r17
;;
// CR[IIPA]
mov cr.iipa = r19
mov cr.iipa = r20
;;
// CR[IPSR]
mov cr.ipsr = r21
mov cr.ipsr = r22
;;
// CR[IRR%] (and others)
mov r2 = cr.ivr
mov r3 = cr.ivr
;;
// CR[ISR]
mov cr.isr = r24
mov cr.isr = r25
;;
// CR[ITIR]
mov cr.itir = r26
mov cr.itir = r27
;;
// CR[ITM]
mov cr.itm = r28
mov cr.itm = r29
;;
// CR[ITV]
mov cr.itv = r0
mov cr.itv = r1
;;
// CR[IVA]
mov cr.iva = r0
mov cr.iva = r1
;;
// CR[IVR] (no explicit writers)
// CR[LID]
mov cr.lid = r0
mov cr.lid = r1
;;
// CR[LRR%]
mov cr.lrr0 = r0
mov cr.lrr1 = r0 // no DV here
;;
mov cr.lrr0 = r0
mov cr.lrr0 = r0
;;
// CR[PMV]
mov cr.pmv = r0
mov cr.pmv = r1
;;
// CR[PTA]
mov cr.pta = r0
mov cr.pta = r1
;;
// CR[TPR]
mov cr.tpr = r0
mov cr.tpr = r1
;;
// DBR#
mov dbr[r1] = r1
mov dbr[r1] = r2
;;
srlz.d
// DTC
ptc.e r0
ptc.e r1 // no DVs here
;;
ptc.e r0 // (and others)
itc.i r0
;;
srlz.d
// DTC_LIMIT
ptc.g r0, r1 // NOTE: GAS automatically emits stops after
ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
;; // longer possible in GAS-generated assembly
srlz.d
// DTR
itr.d dtr[r0] = r1 // (and others)
ptr.d r2, r3
;;
srlz.d
// FR%
mov f3 = f2
ldfs.c.clr f3 = [r1]
;;
// GR%
mov r2 = r0
ld8.c.clr r2 = [r1]
;;
// IBR#
mov ibr[r0] = r2
mov ibr[r1] = r2
;;
// InService
mov cr.eoi = r0
mov r1 = cr.ivr
;;
srlz.d
// ITC
ptc.e r0
itc.i r1
;;
srlz.i
;;
// ITR
itr.i itr[r0] = r1
ptr.i r2, r3
;;
srlz.i
;;
// PKR#
.reg.val r1, 0x1
.reg.val r2, ~0x1
mov pkr[r1] = r1
mov pkr[r2] = r1 // no DV here
;;
mov pkr[r1] = r1
mov pkr[r1] = r1
;;
// PMC#
mov pmc[r3] = r1
mov pmc[r4] = r1
;;
// PMD#
mov pmd[r3] = r1
mov pmd[r4] = r1
;;
// PR%, 1 - 15
cmp.eq p1, p0 = r0, r1
cmp.eq p1, p0 = r2, r3
;;
fcmp.eq p1, p2 = f2, f3
fcmp.eq p1, p3 = f2, f3
;;
cmp.eq.and p1, p2 = r0, r1
cmp.eq.or p1, p3 = r2, r3
;;
cmp.eq.or p1, p3 = r2, r3
cmp.eq.and p1, p2 = r0, r1
;;
cmp.eq.and p1, p2 = r0, r1
cmp.eq.and p1, p3 = r2, r3 // no DV here
;;
cmp.eq.or p1, p2 = r0, r1
cmp.eq.or p1, p3 = r2, r3 // no DV here
;;
// PR63
br.wtop.sptk L
br.wtop.sptk L
;;
cmp.eq p63, p0 = r0, r1
cmp.eq p63, p0 = r2, r3
;;
fcmp.eq p63, p2 = f2, f3
fcmp.eq p63, p3 = f2, f3
;;
cmp.eq.and p63, p2 = r0, r1
cmp.eq.or p63, p3 = r2, r3
;;
cmp.eq.or p63, p3 = r2, r3
cmp.eq.and p63, p2 = r0, r1
;;
cmp.eq.and p63, p2 = r0, r1
cmp.eq.and p63, p3 = r2, r3 // no DV here
;;
cmp.eq.or p63, p2 = r0, r1
cmp.eq.or p63, p3 = r2, r3 // no DV here
;;
// PSR.ac
rum (1<<3)
rum (1<<3)
;;
// PSR.be
rum (1<<1)
rum (1<<1)
;;
// PSR.bn
bsw.0 // GAS automatically emits a stop after bsw.n
bsw.0 // so this conflict is avoided
;;
// PSR.cpl
epc
br.ret.sptk b0
;;
// PSR.da (rfi is the only writer)
// PSR.db (and others)
mov psr.l = r0
mov psr.l = r1
;;
srlz.d
// PSR.dd (rfi is the only writer)
// PSR.dfh
ssm (1<<19)
ssm (1<<19)
;;
srlz.d
// PSR.dfl
ssm (1<<18)
ssm (1<<18)
;;
srlz.d
// PSR.di
rsm (1<<22)
rsm (1<<22)
;;
// PSR.dt
rsm (1<<17)
rsm (1<<17)
;;
// PSR.ed (rfi is the only writer)
// PSR.i
ssm (1<<14)
ssm (1<<14)
;;
// PSR.ia (no DV semantics)
// PSR.ic
ssm (1<<13)
ssm (1<<13)
;;
// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp (see PSR.db)
// PSR.mc (rfi is the only writer)
// PSR.mfh
mov f32 = f33
mov r10 = psr
;;
ssm (1<<5)
ssm (1<<5)
;;
ssm (1<<5)
mov psr.um = r10
;;
rum (1<<5)
rum (1<<5)
;;
mov f32 = f33
mov f34 = f35 // no DV here
;;
// PSR.mfl
mov f2 = f3
mov r10 = psr
;;
ssm (1<<4)
ssm (1<<4)
;;
ssm (1<<4)
mov psr.um = r10
;;
rum (1<<4)
rum (1<<4)
;;
mov f2 = f3
mov f4 = f5 // no DV here
;;
// PSR.pk
rsm (1<<15)
rsm (1<<15)
;;
// PSR.pp
rsm (1<<21)
rsm (1<<21)
;;
// PSR.ri (no DV semantics)
// PSR.rt (see PSR.db)
// PSR.si
rsm (1<<23)
ssm (1<<23)
;;
// PSR.sp
ssm (1<<20)
rsm (1<<20)
;;
srlz.d
// PSR.ss (rfi is the only writer)
// PSR.tb (see PSR.db)
// PSR.up
rsm (1<<2)
rsm (1<<2)
;;
rum (1<<2)
mov psr.um = r0
;;
// RR#
mov rr[r2] = r1
mov rr[r2] = r3
;;
// PR, additional cases (or.andcm and and.orcm interaction)
cmp.eq.or.andcm p6, p7 = 1, r32
cmp.eq.or.andcm p6, p7 = 5, r36 // no DV here
;;
cmp.eq.and.orcm p6, p7 = 1, r32
cmp.eq.and.orcm p6, p7 = 5, r36 // no DV here
;;
cmp.eq.or.andcm p63, p7 = 1, r32
cmp.eq.or.andcm p63, p7 = 5, r36 // no DV here
;;
cmp.eq.or.andcm p6, p63 = 1, r32
cmp.eq.or.andcm p6, p63 = 5, r36 // no DV here
;;
cmp.eq.and.orcm p63, p7 = 1, r32
cmp.eq.and.orcm p63, p7 = 5, r36 // no DV here
;;
cmp.eq.and.orcm p6, p63 = 1, r32
cmp.eq.and.orcm p6, p63 = 5, r36 // no DV here
;;
cmp.eq.or.andcm p6, p7 = 1, r32
cmp.eq.and.orcm p6, p7 = 5, r36
;;
cmp.eq.or.andcm p63, p7 = 1, r32
cmp.eq.and.orcm p63, p7 = 5, r36
;;
cmp.eq.or.andcm p6, p63 = 1, r32
cmp.eq.and.orcm p6, p63 = 5, r36
;;
// PR%, 16 - 62
cmp.eq p21, p0 = r0, r1
cmp.eq p21, p0 = r2, r3
;;
fcmp.eq p21, p22 = f2, f3
fcmp.eq p21, p23 = f2, f3
;;
cmp.eq.and p21, p22 = r0, r1
cmp.eq.or p21, p23 = r2, r3
;;
cmp.eq.or p21, p23 = r2, r3
cmp.eq.and p21, p22 = r0, r1
;;
cmp.eq.and p21, p22 = r0, r1
cmp.eq.and p21, p23 = r2, r3 // no DV here
;;
cmp.eq.or p21, p22 = r0, r1
cmp.eq.or p21, p23 = r2, r3 // no DV here
;;
// RSE
L:
|
stsp/binutils-ia16
| 9,948
|
gas/testsuite/gas/ia64/opc-a.s
|
.text
.type _start,@function
_start:
add r101 = r102, r103
(p1) add r104 = r105, r106
add r107 = r108, r109, 1
(p2) add r110 = r111, r112, 1
adds r20 = 0, r10
(p1) adds r21 = 1, r10
adds r22 = -1, r10
adds r23 = -0x2000, r10
(p2) adds r24 = 0x1FFF, r10
addl r30 = 0, r1
addl r31 = 1, r1
(p1) addl r32 = -1, r1
addl r33 = -0x2000, r1
addl r34 = 0x1FFF, r1
addl r35 = -0x200000, r1
addl r36 = 0x1FFFFF, r1
add r11 = 0, r10
add r12 = 0x1234, r10
add r13 = 0x1234, r1
add r14 = 0x12345, r1
addp4 r20 = r3, r10
(p1) addp4 r21 = 1, r10
addp4 r22 = -1, r10
sub r101 = r102, r103
(p2) sub r110 = r111, r112, 1
sub r120 = 0, r3
sub r121 = 1, r3
sub r122 = -1, r3
sub r123 = -128, r3
sub r124 = 127, r3
and r8 = r9, r10
(p3) and r11 = -128, r12
(p4) or r8 = r9, r10
or r11 = -128, r12
xor r8 = r9, r10
xor r11 = -128, r12
andcm r8 = r9, r10
andcm r11 = -128, r12
shladd r8 = r30, 1, r31
shladd r9 = r30, 2, r31
shladd r10 = r30, 3, r31
shladd r11 = r30, 4, r31
shladdp4 r8 = r30, 1, r31
shladdp4 r9 = r30, 2, r31
shladdp4 r10 = r30, 3, r31
shladdp4 r11 = r30, 4, r31
padd1 r10 = r30, r31
padd1.sss r11 = r30, r31
padd1.uus r12 = r30, r31
padd1.uuu r13 = r30, r31
padd2 r14 = r30, r31
padd2.sss r15 = r30, r31
padd2.uus r16 = r30, r31
padd2.uuu r17 = r30, r31
padd4 r18 = r30, r31
psub1 r10 = r30, r31
psub1.sss r11 = r30, r31
psub1.uus r12 = r30, r31
psub1.uuu r13 = r30, r31
psub2 r14 = r30, r31
psub2.sss r15 = r30, r31
psub2.uus r16 = r30, r31
psub2.uuu r17 = r30, r31
psub4 r18 = r30, r31
pavg1 r10 = r30, r31
pavg1.raz r10 = r30, r31
pavg2 r10 = r30, r31
pavg2.raz r10 = r30, r31
pavgsub1 r10 = r30, r31
pavgsub2 r10 = r30, r31
pcmp1.eq r10 = r30, r31
pcmp2.eq r10 = r30, r31
pcmp4.eq r10 = r30, r31
pcmp1.gt r10 = r30, r31
pcmp2.gt r10 = r30, r31
pcmp4.gt r10 = r30, r31
pshladd2 r10 = r11, 1, r12
pshladd2 r10 = r11, 3, r12
pshradd2 r10 = r11, 1, r12
pshradd2 r10 = r11, 2, r12
cmp.eq p2, p3 = r3, r4
cmp.eq p2, p3 = 3, r4
cmp.ne p2, p3 = r3, r4
cmp.ne p2, p3 = 3, r4
cmp.lt p2, p3 = r3, r4
cmp.lt p2, p3 = 3, r4
cmp.le p2, p3 = r3, r4
cmp.le p2, p3 = 3, r4
cmp.gt p2, p3 = r3, r4
cmp.gt p2, p3 = 3, r4
cmp.ge p2, p3 = r3, r4
cmp.ge p2, p3 = 3, r4
cmp.ltu p2, p3 = r3, r4
cmp.ltu p2, p3 = 3, r4
cmp.leu p2, p3 = r3, r4
cmp.leu p2, p3 = 3, r4
cmp.gtu p2, p3 = r3, r4
cmp.gtu p2, p3 = 3, r4
cmp.geu p2, p3 = r3, r4
cmp.geu p2, p3 = 3, r4
cmp.eq.unc p2, p3 = r3, r4
cmp.eq.unc p2, p3 = 3, r4
cmp.ne.unc p2, p3 = r3, r4
cmp.ne.unc p2, p3 = 3, r4
cmp.lt.unc p2, p3 = r3, r4
cmp.lt.unc p2, p3 = 3, r4
cmp.le.unc p2, p3 = r3, r4
cmp.le.unc p2, p3 = 3, r4
cmp.gt.unc p2, p3 = r3, r4
cmp.gt.unc p2, p3 = 3, r4
cmp.ge.unc p2, p3 = r3, r4
cmp.ge.unc p2, p3 = 3, r4
cmp.ltu.unc p2, p3 = r3, r4
cmp.ltu.unc p2, p3 = 3, r4
cmp.leu.unc p2, p3 = r3, r4
cmp.leu.unc p2, p3 = 3, r4
cmp.gtu.unc p2, p3 = r3, r4
cmp.gtu.unc p2, p3 = 3, r4
cmp.geu.unc p2, p3 = r3, r4
cmp.geu.unc p2, p3 = 3, r4
cmp.eq.and p2, p3 = r3, r4
cmp.eq.and p2, p3 = 3, r4
cmp.eq.or p2, p3 = r3, r4
cmp.eq.or p2, p3 = 3, r4
cmp.eq.or.andcm p2, p3 = r3, r4
cmp.eq.or.andcm p2, p3 = 3, r4
cmp.eq.orcm p2, p3 = r3, r4
cmp.eq.orcm p2, p3 = 3, r4
cmp.eq.andcm p2, p3 = r3, r4
cmp.eq.andcm p2, p3 = 3, r4
cmp.eq.and.orcm p2, p3 = r3, r4
cmp.eq.and.orcm p2, p3 = 3, r4
cmp.ne.and p2, p3 = r3, r4
cmp.ne.and p2, p3 = 3, r4
cmp.ne.or p2, p3 = r3, r4
cmp.ne.or p2, p3 = 3, r4
cmp.ne.or.andcm p2, p3 = r3, r4
cmp.ne.or.andcm p2, p3 = 3, r4
cmp.ne.orcm p2, p3 = r3, r4
cmp.ne.orcm p2, p3 = 3, r4
cmp.ne.andcm p2, p3 = r3, r4
cmp.ne.andcm p2, p3 = 3, r4
cmp.ne.and.orcm p2, p3 = r3, r4
cmp.ne.and.orcm p2, p3 = 3, r4
cmp.eq.and p2, p3 = r0, r4
cmp.eq.and p2, p3 = r4, r0
cmp.eq.or p2, p3 = r0, r4
cmp.eq.or p2, p3 = r4, r0
cmp.eq.or.andcm p2, p3 = r0, r4
cmp.eq.or.andcm p2, p3 = r4, r0
cmp.eq.orcm p2, p3 = r0, r4
cmp.eq.orcm p2, p3 = r4, r0
cmp.eq.andcm p2, p3 = r0, r4
cmp.eq.andcm p2, p3 = r4, r0
cmp.eq.and.orcm p2, p3 = r0, r4
cmp.eq.and.orcm p2, p3 = r4, r0
cmp.ne.and p2, p3 = r0, r4
cmp.ne.and p2, p3 = r4, r0
cmp.ne.or p2, p3 = r0, r4
cmp.ne.or p2, p3 = r4, r0
cmp.ne.or.andcm p2, p3 = r0, r4
cmp.ne.or.andcm p2, p3 = r4, r0
cmp.ne.orcm p2, p3 = r0, r4
cmp.ne.orcm p2, p3 = r4, r0
cmp.ne.andcm p2, p3 = r0, r4
cmp.ne.andcm p2, p3 = r4, r0
cmp.ne.and.orcm p2, p3 = r0, r4
cmp.ne.and.orcm p2, p3 = r4, r0
cmp.lt.and p2, p3 = r0, r4
cmp.lt.and p2, p3 = r4, r0
cmp.lt.or p2, p3 = r0, r4
cmp.lt.or p2, p3 = r4, r0
cmp.lt.or.andcm p2, p3 = r0, r4
cmp.lt.or.andcm p2, p3 = r4, r0
cmp.lt.orcm p2, p3 = r0, r4
cmp.lt.orcm p2, p3 = r4, r0
cmp.lt.andcm p2, p3 = r0, r4
cmp.lt.andcm p2, p3 = r4, r0
cmp.lt.and.orcm p2, p3 = r0, r4
cmp.lt.and.orcm p2, p3 = r4, r0
cmp.le.and p2, p3 = r0, r4
cmp.le.and p2, p3 = r4, r0
cmp.le.or p2, p3 = r0, r4
cmp.le.or p2, p3 = r4, r0
cmp.le.or.andcm p2, p3 = r0, r4
cmp.le.or.andcm p2, p3 = r4, r0
cmp.le.orcm p2, p3 = r0, r4
cmp.le.orcm p2, p3 = r4, r0
cmp.le.andcm p2, p3 = r0, r4
cmp.le.andcm p2, p3 = r4, r0
cmp.le.and.orcm p2, p3 = r0, r4
cmp.le.and.orcm p2, p3 = r4, r0
cmp.gt.and p2, p3 = r0, r4
cmp.gt.and p2, p3 = r4, r0
cmp.gt.or p2, p3 = r0, r4
cmp.gt.or p2, p3 = r4, r0
cmp.gt.or.andcm p2, p3 = r0, r4
cmp.gt.or.andcm p2, p3 = r4, r0
cmp.gt.orcm p2, p3 = r0, r4
cmp.gt.orcm p2, p3 = r4, r0
cmp.gt.andcm p2, p3 = r0, r4
cmp.gt.andcm p2, p3 = r4, r0
cmp.gt.and.orcm p2, p3 = r0, r4
cmp.gt.and.orcm p2, p3 = r4, r0
cmp.ge.and p2, p3 = r0, r4
cmp.ge.and p2, p3 = r4, r0
cmp.ge.or p2, p3 = r0, r4
cmp.ge.or p2, p3 = r4, r0
cmp.ge.or.andcm p2, p3 = r0, r4
cmp.ge.or.andcm p2, p3 = r4, r0
cmp.ge.orcm p2, p3 = r0, r4
cmp.ge.orcm p2, p3 = r4, r0
cmp.ge.andcm p2, p3 = r0, r4
cmp.ge.andcm p2, p3 = r4, r0
cmp.ge.and.orcm p2, p3 = r0, r4
cmp.ge.and.orcm p2, p3 = r4, r0
cmp4.eq p2, p3 = r3, r4
cmp4.eq p2, p3 = 3, r4
cmp4.ne p2, p3 = r3, r4
cmp4.ne p2, p3 = 3, r4
cmp4.lt p2, p3 = r3, r4
cmp4.lt p2, p3 = 3, r4
cmp4.le p2, p3 = r3, r4
cmp4.le p2, p3 = 3, r4
cmp4.gt p2, p3 = r3, r4
cmp4.gt p2, p3 = 3, r4
cmp4.ge p2, p3 = r3, r4
cmp4.ge p2, p3 = 3, r4
cmp4.ltu p2, p3 = r3, r4
cmp4.ltu p2, p3 = 3, r4
cmp4.leu p2, p3 = r3, r4
cmp4.leu p2, p3 = 3, r4
cmp4.gtu p2, p3 = r3, r4
cmp4.gtu p2, p3 = 3, r4
cmp4.geu p2, p3 = r3, r4
cmp4.geu p2, p3 = 3, r4
cmp4.eq.unc p2, p3 = r3, r4
cmp4.eq.unc p2, p3 = 3, r4
cmp4.ne.unc p2, p3 = r3, r4
cmp4.ne.unc p2, p3 = 3, r4
cmp4.lt.unc p2, p3 = r3, r4
cmp4.lt.unc p2, p3 = 3, r4
cmp4.le.unc p2, p3 = r3, r4
cmp4.le.unc p2, p3 = 3, r4
cmp4.gt.unc p2, p3 = r3, r4
cmp4.gt.unc p2, p3 = 3, r4
cmp4.ge.unc p2, p3 = r3, r4
cmp4.ge.unc p2, p3 = 3, r4
cmp4.ltu.unc p2, p3 = r3, r4
cmp4.ltu.unc p2, p3 = 3, r4
cmp4.leu.unc p2, p3 = r3, r4
cmp4.leu.unc p2, p3 = 3, r4
cmp4.gtu.unc p2, p3 = r3, r4
cmp4.gtu.unc p2, p3 = 3, r4
cmp4.geu.unc p2, p3 = r3, r4
cmp4.geu.unc p2, p3 = 3, r4
cmp4.eq.and p2, p3 = r3, r4
cmp4.eq.and p2, p3 = 3, r4
cmp4.eq.or p2, p3 = r3, r4
cmp4.eq.or p2, p3 = 3, r4
cmp4.eq.or.andcm p2, p3 = r3, r4
cmp4.eq.or.andcm p2, p3 = 3, r4
cmp4.eq.orcm p2, p3 = r3, r4
cmp4.eq.orcm p2, p3 = 3, r4
cmp4.eq.andcm p2, p3 = r3, r4
cmp4.eq.andcm p2, p3 = 3, r4
cmp4.eq.and.orcm p2, p3 = r3, r4
cmp4.eq.and.orcm p2, p3 = 3, r4
cmp4.ne.and p2, p3 = r3, r4
cmp4.ne.and p2, p3 = 3, r4
cmp4.ne.or p2, p3 = r3, r4
cmp4.ne.or p2, p3 = 3, r4
cmp4.ne.or.andcm p2, p3 = r3, r4
cmp4.ne.or.andcm p2, p3 = 3, r4
cmp4.ne.orcm p2, p3 = r3, r4
cmp4.ne.orcm p2, p3 = 3, r4
cmp4.ne.andcm p2, p3 = r3, r4
cmp4.ne.andcm p2, p3 = 3, r4
cmp4.ne.and.orcm p2, p3 = r3, r4
cmp4.ne.and.orcm p2, p3 = 3, r4
cmp4.eq.and p2, p3 = r0, r4
cmp4.eq.and p2, p3 = r4, r0
cmp4.eq.or p2, p3 = r0, r4
cmp4.eq.or p2, p3 = r4, r0
cmp4.eq.or.andcm p2, p3 = r0, r4
cmp4.eq.or.andcm p2, p3 = r4, r0
cmp4.eq.orcm p2, p3 = r0, r4
cmp4.eq.orcm p2, p3 = r4, r0
cmp4.eq.andcm p2, p3 = r0, r4
cmp4.eq.andcm p2, p3 = r4, r0
cmp4.eq.and.orcm p2, p3 = r0, r4
cmp4.eq.and.orcm p2, p3 = r4, r0
cmp4.ne.and p2, p3 = r0, r4
cmp4.ne.and p2, p3 = r4, r0
cmp4.ne.or p2, p3 = r0, r4
cmp4.ne.or p2, p3 = r4, r0
cmp4.ne.or.andcm p2, p3 = r0, r4
cmp4.ne.or.andcm p2, p3 = r4, r0
cmp4.ne.orcm p2, p3 = r0, r4
cmp4.ne.orcm p2, p3 = r4, r0
cmp4.ne.andcm p2, p3 = r0, r4
cmp4.ne.andcm p2, p3 = r4, r0
cmp4.ne.and.orcm p2, p3 = r0, r4
cmp4.ne.and.orcm p2, p3 = r4, r0
cmp4.lt.and p2, p3 = r0, r4
cmp4.lt.and p2, p3 = r4, r0
cmp4.lt.or p2, p3 = r0, r4
cmp4.lt.or p2, p3 = r4, r0
cmp4.lt.or.andcm p2, p3 = r0, r4
cmp4.lt.or.andcm p2, p3 = r4, r0
cmp4.lt.orcm p2, p3 = r0, r4
cmp4.lt.orcm p2, p3 = r4, r0
cmp4.lt.andcm p2, p3 = r0, r4
cmp4.lt.andcm p2, p3 = r4, r0
cmp4.lt.and.orcm p2, p3 = r0, r4
cmp4.lt.and.orcm p2, p3 = r4, r0
cmp4.le.and p2, p3 = r0, r4
cmp4.le.and p2, p3 = r4, r0
cmp4.le.or p2, p3 = r0, r4
cmp4.le.or p2, p3 = r4, r0
cmp4.le.or.andcm p2, p3 = r0, r4
cmp4.le.or.andcm p2, p3 = r4, r0
cmp4.le.orcm p2, p3 = r0, r4
cmp4.le.orcm p2, p3 = r4, r0
cmp4.le.andcm p2, p3 = r0, r4
cmp4.le.andcm p2, p3 = r4, r0
cmp4.le.and.orcm p2, p3 = r0, r4
cmp4.le.and.orcm p2, p3 = r4, r0
cmp4.gt.and p2, p3 = r0, r4
cmp4.gt.and p2, p3 = r4, r0
cmp4.gt.or p2, p3 = r0, r4
cmp4.gt.or p2, p3 = r4, r0
cmp4.gt.or.andcm p2, p3 = r0, r4
cmp4.gt.or.andcm p2, p3 = r4, r0
cmp4.gt.orcm p2, p3 = r0, r4
cmp4.gt.orcm p2, p3 = r4, r0
cmp4.gt.andcm p2, p3 = r0, r4
cmp4.gt.andcm p2, p3 = r4, r0
cmp4.gt.and.orcm p2, p3 = r0, r4
cmp4.gt.and.orcm p2, p3 = r4, r0
cmp4.ge.and p2, p3 = r0, r4
cmp4.ge.and p2, p3 = r4, r0
cmp4.ge.or p2, p3 = r0, r4
cmp4.ge.or p2, p3 = r4, r0
cmp4.ge.or.andcm p2, p3 = r0, r4
cmp4.ge.or.andcm p2, p3 = r4, r0
cmp4.ge.orcm p2, p3 = r0, r4
cmp4.ge.orcm p2, p3 = r4, r0
cmp4.ge.andcm p2, p3 = r0, r4
cmp4.ge.andcm p2, p3 = r4, r0
cmp4.ge.and.orcm p2, p3 = r0, r4
cmp4.ge.and.orcm p2, p3 = r4, r0
nop.i 0; nop.i 0
|
stsp/binutils-ia16
| 7,884
|
gas/testsuite/gas/ia64/dv-raw-err.s
|
//
// Detect RAW violations. Cases taken from DV tables.
// This test is by no means complete but tries to hit the things that are
// likely to be missed.
//
.text
.explicit
// AR[BSP]
mov ar.bspstore = r0
mov r1 = ar.bsp
;;
// AR[BSPSTORE]
mov ar.bspstore = r2
mov r3 = ar.bspstore
;;
// AR[CCV]
mov ar.ccv = r4
cmpxchg8.acq r5 = [r6],r7,ar.ccv
;;
// AR[EC]
br.wtop.sptk L
mov r8 = ar.ec
;;
// AR[FPSR].sf0.controls
fsetc.s0 0x7f, 0x0f
fpcmp.eq.s0 f2 = f3, f4
;;
// AR[FPSR].sf1.controls
fsetc.s1 0x7f, 0x0f
fpcmp.eq.s1 f2 = f3, f4
;;
// AR[FPSR].sf2.controls
fsetc.s2 0x7f, 0x0f
fpcmp.eq.s2 f2 = f3, f4
;;
// AR[FPSR].sf3.controls
fsetc.s3 0x7f, 0x0f
fpcmp.eq.s3 f2 = f3, f4
;;
// AR[FPSR].sf0.flags
fpcmp.eq.s0 f2 = f3, f4
fchkf.s0 L
;;
// AR[FPSR].sf1.flags
fpcmp.eq.s1 f2 = f3, f4
fchkf.s1 L
;;
// AR[FPSR].sf2.flags
fpcmp.eq.s2 f2 = f3, f4
fchkf.s2 L
;;
// AR[FPSR].sf3.flags
fpcmp.eq.s3 f2 = f3, f4
fchkf.s3 L
;;
// AR[FPSR].traps/rv
mov ar.fpsr = r0
fcmp.eq.s3 p1, p2 = f5, f6
;;
// AR[ITC]
mov ar.itc = r1
mov r2 = ar.itc
;;
// AR[RUC]
mov ar.ruc = r1
mov r2 = ar.ruc
;;
// AR[K]
mov ar.k1 = r3
br.ia.sptk b0
;;
// AR[LC]
br.cloop.sptk L
mov r4 = ar.lc
;;
// AR[PFS]
mov ar.pfs = r5
epc
// AR[RNAT]
mov ar.bspstore = r8
mov r9 = ar.rnat
;;
// AR[RSC]
mov ar.rsc = r10
mov r11 = ar.rnat
;;
// AR[UNAT]
mov ar.unat = r12
ld8.fill r13 = [r14]
;;
// AR%
// BR%
mov b0 = r0
mov r2 = b0
;;
// CFM
br.wtop.sptk L
fadd f2 = f1, f32 // read from rotating register region
;;
// CR[CMCV]
mov cr.cmcv = r1
mov r2 = cr.cmcv
;;
// CR[DCR]
mov cr.dcr = r3
ld8.s r4 = [r5]
;;
// CR[EOI]
// CR[GPTA]
mov cr.gpta = r6
thash r7 = r8
;;
srlz.d
// CR[IFA]
mov cr.ifa = r9
itc.i r10
;;
// CR[IFS]
mov cr.ifs = r11
mov r12 = cr.ifs
;;
// CR[IHA]
mov cr.iha = r13
mov r14 = cr.iha
;;
// CR[IIB%]
mov cr.iib0 = r15
mov r16 = cr.iib0
;;
mov cr.iib1 = r15
mov r16 = cr.iib1
;;
// CR[IIM]
mov cr.iim = r15
mov r16 = cr.iim
;;
// CR[IIP]
mov cr.iip = r17
rfi
;;
// CR[IIPA]
mov cr.iipa = r19
mov r20 = cr.iipa
;;
// CR[IPSR]
mov cr.ipsr = r21
rfi
;;
// CR[IRR%]
mov r22 = cr.ivr
mov r23 = cr.irr0
;;
// CR[ISR]
mov cr.isr = r24
mov r25 = cr.isr
;;
// CR[ITIR]
mov cr.itir = r26
itc.d r27
;;
// CR[ITM]
mov cr.itm = r28
mov r29 = cr.itm
;;
// CR[ITV]
mov cr.itv = r0
mov r1 = cr.itv
;;
// CR[IVR] (all writes are implicit in other resource usage)
// CR[IVA]
mov cr.iva = r0
mov r1 = cr.iva
;;
// CR[LID]
mov cr.lid = r0
mov r1 = cr.lid
;;
srlz.d
// CR[LRR%]
mov cr.lrr0 = r0
mov r1 = cr.lrr0
;;
// CR[PMV]
mov cr.pmv = r0
mov r1 = cr.pmv
;;
// CR[PTA]
mov cr.pta = r0
thash r1 = r2
;;
// CR[TPR]
mov cr.tpr = r0
mov r1 = cr.ivr // data
;;
srlz.d
mov cr.tpr = r2
mov psr.l = r3 // other
;;
srlz.d
// DBR#
mov dbr[r0] = r1
mov r2 = dbr[r3]
;;
srlz.d
mov dbr[r4] = r5
probe.r r6 = r7, r8
;;
srlz.d
// DTC
ptc.e r0
fc r1
;;
srlz.d
itr.i itr[r2] = r3
ptc.e r4
;;
// DTC_LIMIT/ITC_LIMIT
ptc.g r0, r1 // NOTE: GAS automatically emits stops after
ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
;; // longer possible in GAS-generated assembly
srlz.d
// DTR
itr.d dtr[r0] = r1
tak r2 = r3
;;
srlz.d
ptr.d r4, r5
tpa r6 = r7
;;
srlz.d
// FR%
ldfs.c.clr f2 = [r1]
mov f3 = f2 // no DV here
;;
mov f4 = f5
mov f6 = f4
;;
// GR%
ld8.c.clr r1 = [r1] // no DV here
mov r2 = r0
;;
mov r3 = r4
mov r5 = r3
;;
// IBR#
mov ibr[r0] = r1
mov r2 = ibr[r3]
;;
// InService
mov cr.eoi = r0
mov r1 = cr.ivr
;;
srlz.d
mov r2 = cr.ivr
mov r3 = cr.ivr // several DVs
;;
mov cr.eoi = r4
mov cr.eoi = r5
;;
// ITC
ptc.e r0
epc
;;
srlz.i
;;
// ITC_LIMIT (see DTC_LIMIT)
// ITR
itr.i itr[r0] = r1
epc
;;
srlz.i
;;
// PKR#
mov pkr[r0] = r1
probe.r r2 = r3, r4
;;
srlz.d
mov pkr[r5] = r6
mov r7 = pkr[r8]
;;
srlz.d
// PMC#
mov pmc[r0] = r1
mov r2 = pmc[r3]
;;
srlz.d
mov pmc[r4] = r5
mov r6 = pmd[r7]
;;
srlz.d
// PMD#
mov pmd[r0] = r1
mov r2 = pmd[r3]
;;
// PR%, 1 - 15
cmp.eq p1, p2 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
(p1) add r2 = r3, r4
;;
mov pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p2) add r6 = r7, r8
;;
fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br
(p5) br.cond.sptk b0
;;
cmp.eq p7, p8 = r11, r12
(p7) br.cond.sptk b1 // no DV here
;;
// PR63
br.wtop.sptk L
(p63) add r3 = r1, r2
;;
fcmp.eq p62, p63 = f2, f3
(p63) add r3 = r4, r5
;;
cmp.eq p62, p63 = r6, r7 // no DV here
(p63) br.cond.sptk b0
;;
// PSR.ac
rum (1<<3)
ld8 r2 = [r1]
;;
// PSR.be
rum (1<<1)
ld8 r2 = [r1]
;;
// PSR.bn
bsw.0
mov r1 = r15 // no DV here, since gr < 16
;;
bsw.1 // GAS automatically emits a stop after bsw.n
mov r1 = r16 // so this conflict is avoided
;;
// PSR.cpl
epc
st8 [r0] = r1
;;
epc
mov r2 = ar.itc
;;
epc
mov ar.itc = r3
;;
epc
mov r2 = ar.ruc
;;
epc
mov ar.ruc = r3
;;
epc
mov ar.rsc = r4
;;
epc
mov ar.k0 = r5
;;
epc
mov r6 = pmd[r7]
;;
epc
mov ar.bsp = r8 // no DV here
;;
epc
mov r9 = ar.bsp // no DV here
;;
epc
mov cr.ifa = r10 // any mov-to/from-cr is a DV
;;
epc
mov r11 = cr.eoi // any mov-to/from-cr is a DV
;;
// PSR.da (rfi is the only writer)
// PSR.db (also ac,be,dt,pk)
mov psr.l = r0
ld8 r1 = [r2]
;;
srlz.d
// PSR.dd (rfi is the only writer)
// PSR.dfh
mov psr.l = r0
mov f64 = f65
;;
srlz.d
// PSR.dfl
mov psr.l = r0
mov f3 = f4
;;
srlz.d
// PSR.di
rsm (1<<22)
mov r1 = psr
;;
// PSR.dt
rsm (1<<17)
ld8 r1 = [r1]
;;
// PSR.ed (rfi is the only writer)
// PSR.i
ssm (1<<14)
mov r1 = psr
;;
// PSR.ia (no DV semantics)
// PSR.ic
ssm (1<<13)
mov r1 = psr
;;
srlz.d
rsm (1<<13)
mov r1 = cr.itir
;;
srlz.d
rsm (1<<13)
mov r1 = cr.irr0 // no DV here
;;
srlz.d
// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp
mov psr.l = r0
br.ret.sptk b0
;;
// PSR.mc (rfi is the only writer)
// PSR.mfh
mov f32 = f33
mov r1 = psr
;;
// PSR.mfl
mov f2 = f3
mov r1 = psr
;;
// PSR.pk
rsm (1<<15)
ld8 r1 = [r1]
;;
rsm (1<<15)
mov r2 = psr
;;
// PSR.pp
rsm (1<<21)
mov r1 = psr
;;
// PSR.ri (no DV semantics)
// PSR.rt
mov psr.l = r0
flushrs
;;
srlz.d
// PSR.si
rsm (1<<23)
mov r1 = ar.itc
;;
rsm (1<<23)
mov r1 = ar.ruc
;;
ssm (1<<23)
mov r1 = ar.ec // no DV here
;;
// PSR.sp
ssm (1<<20)
mov r1 = pmd[r1]
;;
ssm (1<<20)
rum 0xff
;;
ssm (1<<20)
mov r1 = rr[r1]
;;
// PSR.ss (rfi is the only writer)
// PSR.tb
mov psr.l = r0
chk.s r0, L
;;
// PSR.up
rsm (1<<2)
mov r1 = psr.um
;;
srlz.d
// RR#
mov rr[r0] = r1
ld8 r2 = [r0] // data
;;
mov rr[r4] = r5
mov r6 = rr[r7] // impliedf
;;
srlz.d
;;
// RSE
// GR%, additional cases
// addl
mov r2 = r32
addl r3 = 12345, r2 // impliedf, IA64_OPND_R3_2
;;
// postinc
ld8 r2 = [r32], 8
mov r8 = r32 // impliedf
;;
// PR%, 16 - 62
cmp.eq p21, p22 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
(p21) add r2 = r3, r4
;;
mov pr = r5, 0x1ffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p22) add r6 = r7, r8
;;
mov pr.rot = 0xffff0000 // mov-to-pr-rotreg/pr-reader-nobr-nomovpr
(p23) add r9 = r10, r11
;;
fcmp.eq p25, p26 = f2, f3 // pr-writer-fp/pr-reader-br
(p25) br.cond.sptk b0
;;
cmp.eq p27, p28 = r11, r12
(p27) br.cond.sptk b1 // no DV here
;;
// postinc
st8 [r6] = r8, 16
add r7 = 8, r6 // impliedf
;;
ldfd f14 = [r6], 16
add r7 = 8, r6 // impliedf
;;
stfd [r6] = f14, 16
add r7 = r8, r6
;;
add r6 = 8, r7
ld8 r8 = [r6], 16 // impliedf, WAW
;;
add r6 = 8, r7
ldfd f14 = [r6], 16 // impliedf, WAW
;;
L:
br.ret.sptk rp
// PSR.vm. New in SDM 2.2
vmsw.0
ld8 r2 = [r1]
;;
|
stsp/binutils-ia16
| 1,152
|
gas/testsuite/gas/mmix/relax1.s
|
# Relaxation border-cases: just-within reach, just-out-of-reach, forward
# and backward. Have a few variable-length thingies in-between so it
# doesn't get too easy.
Main JMP l6
l0 JMP l6
l1 JMP l6
l01 JMP l6
GETA $7,nearfar1 % Within reach.
PUSHJ $191,nearfar2 % Within reach.
l2 JMP nearfar2 % Dummy.
.space 65530*4,0
BNP $72,l0 % Within reach
GETA $4,l1 % Within reach.
nearfar1 PUSHJ 5,l01 % Within reach.
nearfar2 GETA $9,l1 % Out of reach.
PUSHJ $11,l3 % Out of reach.
l4 BP $55,l3 % Within reach.
.space 65533*4,0
JMP l1 % Dummy.
l3 JMP l0 % Dummy.
BOD $88,l4 % Within reach.
BOD $88,l4 % Out of reach.
JMP l5 % Out of reach.
l6 JMP l5 % Within reach.
BZ $111,l3 % Dummy.
.space (256*256*256-3)*4,0
l5 JMP l8 % Dummy.
JMP l6 % Within reach
JMP l6 % Out of reach.
BNN $44,l9 % Out of reach.
l8 BNN $44,l9 % Within reach.
JMP l5 % Dummy.
JMP l5 % Dummy.
.space 65531*4,0
l10 JMP l5 % Dummy.
l9 JMP l11 % Dummy
l7 PUSHJ $33,l8 % Within reach.
PUSHJ $33,l8 % Out of reach.
l11 JMP l5 % Dummy.
JMP l8 % Dummy.
.space 65534*4,0
GETA $61,l11 % Within reach.
GETA $72,l11 % Out of reach.
|
stsp/binutils-ia16
| 5,977
|
gas/testsuite/gas/mmix/pr25331.s
|
# 1 "pr25331.c"
! mmixal:= 8H LOC Data_Section
.text ! mmixal:= 9H LOC 8B
.global f
.data ! mmixal:= 8H LOC 9B
.p2align 3
LOC @+(8-@)&7
f IS @
LOC @+8
.global g
.p2align 2
LOC @+(4-@)&3
g IS @
LOC @+4
.global h
.p2align 3
LOC @+(8-@)&7
h IS @
LOC @+8
.section .rodata
.p2align 2
LOC @+(4-@)&3
LC:0 IS @
BYTE #0
.text ! mmixal:= 9H LOC 8B
.p2align 2
LOC @+(4-@)&3
.global i
i IS @
SUBU $254,$254,240
STOU $253,$254,232
ADDU $253,$254,240
SUBU $254,$254,168
GET $1,rJ
SETL $5,#198
NEGU $5,0,$5
ADDU $4,$253,$5
STOU $0,$4,0
SUBU $0,$253,16
LDO $6,__stack_chk_guard
STOU $6,$0,0
SETL $7,#184
NEGU $7,0,$7
ADDU $0,$253,$7
PUSHJ $8,ak
PUT rJ,$1
STTU $8,$0,0
PUSHJ $8,o
PUT rJ,$1
SET $4,$8
SETL $5,#18b
NEGU $5,0,$5
ADDU $0,$253,$5
STBU $4,$0,0
PUSHJ $8,ag
PUT rJ,$1
SETL $6,#18a
NEGU $6,0,$6
ADDU $0,$253,$6
LDW $0,$0,0
SET $0,$0
SLU $0,$0,16
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
SR $0,$0,16
SET $0,$0
AND $0,$0,8
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:2
SETL $7,#168
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
CMP $0,$0,0
BZ $0,L:2
GETA $9,c
PUSHJ $8,t
PUT rJ,$1
SET $0,$8
SLU $0,$0,32
SR $0,$0,32
SETL $5,#168
NEGU $5,0,$5
ADDU $4,$253,$5
STOU $0,$4,0
L:2 IS @
SETL $6,#168
NEGU $6,0,$6
ADDU $0,$253,$6
LDO $0,$0,0
CMP $0,$0,0
BZ $0,L:3
SETL $7,#174
NEGU $7,0,$7
ADDU $0,$253,$7
SETL $1,#2
STTU $1,$0,0
JMP L:4
L:3 IS @
PUSHJ $8,u
PUT rJ,$1
JMP L:5
L:7 IS @
LDT $0,g
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:5
SETL $4,#184
NEGU $4,0,$4
ADDU $0,$253,$4
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:29
L:5 IS @
PUSHJ $8,c
PUT rJ,$1
SET $0,$8
LDO $0,$0,0
PUSHGO $8,$0,0
PUT rJ,$1
SET $0,$8
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:7
JMP L:6
L:29 IS @
SWYM 0,0,0
L:6 IS @
LDT $0,g
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:30
SWYM 0,0,0
JMP L:9
L:31 IS @
SWYM 0,0,0
JMP L:9
L:32 IS @
SWYM 0,0,0
L:9 IS @
LDO $0,f
SET $2,$0
JMP L:8
L:30 IS @
SWYM 0,0,0
L:8 IS @
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,71
BZ $0,L:10
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,71
BP $0,L:4
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,32
BZ $0,L:12
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,68
BZ $0,L:13
JMP L:4
L:12 IS @
SETL $5,#18b
NEGU $5,0,$5
ADDU $0,$253,$5
LDB $0,$0,0
SLU $0,$0,56
SR $0,$0,56
CMP $0,$0,0
BZ $0,L:14
SETL $6,#18b
NEGU $6,0,$6
ADDU $0,$253,$6
SETL $7,#20
STBU $7,$0,0
L:14 IS @
SETL $2,#198
NEGU $2,0,$2
ADDU $0,$253,$2
LDO $0,$0,0
ADDU $4,$0,8
SETL $5,#198
NEGU $5,0,$5
ADDU $2,$253,$5
STOU $4,$2,0
ADDU $2,$0,4
SETL $6,#180
NEGU $6,0,$6
ADDU $0,$253,$6
LDT $7,$2,0
STTU $7,$0,0
SETL $2,#180
NEGU $2,0,$2
ADDU $0,$253,$2
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:31
SETL $4,#180
NEGU $4,0,$4
ADDU $0,$253,$4
SETL $5,#180
NEGU $5,0,$5
ADDU $2,$253,$5
LDT $6,$2,0
STTU $6,$0,0
LDO $0,f
ADDU $2,$0,1
STOU $2,f
LDB $0,$0,0
SET $0,$0
SLU $0,$0,24
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
SR $0,$0,24
SET $2,$0
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:16
SETL $7,#198
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
ADDU $5,$0,8
SETL $6,#198
NEGU $6,0,$6
ADDU $4,$253,$6
STOU $5,$4,0
ADDU $0,$0,4
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
STOU $0,f
L:16 IS @
SETL $7,#17c
NEGU $7,0,$7
ADDU $0,$253,$7
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:32
SWYM 0,0,0
L:18 IS @
SET $0,$2
SLU $0,$0,32
SRU $0,$0,32
CMPU $0,$0,9
BNP $0,L:18
JMP L:19
L:22 IS @
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:20
AND $0,$3,6
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:21
L:20 IS @
PUSHJ $8,ak
PUT rJ,$1
SETL $4,#198
NEGU $4,0,$4
ADDU $0,$253,$4
LDO $0,$0,0
ADDU $5,$0,8
SETL $6,#198
NEGU $6,0,$6
ADDU $4,$253,$6
STOU $5,$4,0
ADDU $0,$0,4
LDT $0,$0,0
SETL $7,#178
NEGU $7,0,$7
ADDU $4,$253,$7
SETL $5,#188
NEGU $5,0,$5
ADDU $6,$253,$5
SLU $0,$0,32
SR $0,$0,32
SETL $7,#170
NEGU $7,0,$7
ADDU $5,$253,$7
SET $11,$6
SET $10,$0
LDO $9,$5,0
PUSHJ $8,ao
PUT rJ,$1
STTU $8,$4,0
JMP L:19
L:21 IS @
LDO $4,h
SETL $5,#198
NEGU $5,0,$5
ADDU $0,$253,$5
LDO $0,$0,0
ADDU $6,$0,8
SETL $7,#198
NEGU $7,0,$7
ADDU $5,$253,$7
STOU $6,$5,0
ADDU $0,$0,4
LDT $0,$0,0
STTU $0,$4,0
L:19 IS @
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BNZ $0,L:22
JMP L:4
L:13 IS @
AND $0,$3,6
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:23
SETL $1,#198
NEGU $1,0,$1
ADDU $0,$253,$1
LDO $0,$0,0
ADDU $4,$0,8
SETL $5,#198
NEGU $5,0,$5
ADDU $1,$253,$5
STOU $4,$1,0
LDO $0,$0,0
JMP L:24
L:23 IS @
AND $0,$3,4
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:25
SETL $6,#198
NEGU $6,0,$6
ADDU $0,$253,$6
LDO $0,$0,0
ADDU $4,$0,8
SETL $7,#198
NEGU $7,0,$7
ADDU $1,$253,$7
STOU $4,$1,0
ADDU $0,$0,4
LDT $0,$0,0
SET $0,$0
SLU $0,$0,48
SR $0,$0,48
JMP L:24
L:25 IS @
SETL $1,#198
NEGU $1,0,$1
ADDU $0,$253,$1
LDO $0,$0,0
ADDU $4,$0,8
SETL $5,#198
NEGU $5,0,$5
ADDU $1,$253,$5
STOU $4,$1,0
ADDU $0,$0,4
LDT $0,$0,0
SLU $0,$0,32
SR $0,$0,32
L:24 IS @
SETL $6,#158
NEGU $6,0,$6
ADDU $1,$253,$6
STOU $0,$1,0
L:10 IS @
AND $0,$3,8
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:27
SETL $7,#198
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
ADDU $3,$0,8
SETL $4,#198
NEGU $4,0,$4
ADDU $1,$253,$4
STOU $3,$1,0
SETL $5,#160
NEGU $5,0,$5
ADDU $1,$253,$5
LDO $6,$0,0
STOU $6,$1,0
L:27 IS @
SETL $7,#168
NEGU $7,0,$7
ADDU $0,$253,$7
LDO $0,$0,0
CMP $0,$0,0
BZ $0,L:4
SETL $1,#160
NEGU $1,0,$1
ADDU $0,$253,$1
LDO $0,$0,0
SRU $0,$0,63
SET $0,$0
AND $0,$0,1
SET $0,$0
SLU $0,$0,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:4
SLU $0,$2,32
SR $0,$0,32
CMP $0,$0,0
BZ $0,L:4
GETA $2,LC:0
STOU $2,h
L:4 IS @
SUBU $0,$253,16
LDO $1,$0,0
LDO $0,__stack_chk_guard
CMP $0,$1,$0
BZ $0,L:28
PUSHJ $8,__stack_chk_fail
L:28 IS @
SET $0,$2
INCL $254,#190
LDO $253,$254,0
ADDU $254,$254,8
POP 1,0
.data ! mmixal:= 8H LOC 9B
|
stsp/binutils-ia16
| 1,784
|
gas/testsuite/gas/mmix/regt-op.s
|
# All-registers, 'T'-type operands; optional third operand is
# register or constant.
Main LDA X,Y,Z
LDT $32,Y,Z
LDBU Y,$32,Z
LDTU $232,$133,Z
LDO X,Y,$73
LDOU $31,Y,$233
LDW X,$38,$212
LDWU $4,$175,$181
LDB X,Y,Z0
LDSF $32,Y,Z0
LDVTS Y,$32,Z0
LDUNC $232,$133,Z0
STHT X,Y,203
LDHT $31,Y,213
CSWAP X,$38,211
GO $4,$175,161
LDA X,Y
LDB X,Y
LDT X,Y
LDBU X,Y
LDTU X,Y
LDO X,Y
LDOU X,Y
LDW X,Y
LDWU X,Y
LDSF X,Y
LDHT X,Y
CSWAP X,Y
LDUNC X,Y
LDVTS X,Y
GO X,Y
STB X,Y
STT X,Y
STBU X,Y
STTU X,Y
STO X,Y
STOU X,Y
STW X,Y
STWU X,Y
STSF X,Y
STHT X,Y
STUNC X,Y
LDA $41,Y
LDB $121,Y
LDT $78,Y
LDBU $127,Y
LDTU $49,Y
LDO $52,Y
LDOU $42,Y
LDW $123,Y
LDWU $234,Y
LDSF $41,Y
LDHT $89,Y
CSWAP $93,Y
LDUNC $42,Y
LDVTS $33,Y
GO $59,Y
STB $59,Y
STT $59,Y
STBU $59,Y
STTU $59,Y
STO $59,Y
STOU $59,Y
STW $59,Y
STWU $59,Y
STSF $59,Y
STHT $59,Y
STUNC $59,Y
LDA X,$27
LDB X,$48
LDT X,$168
LDBU X,$234
LDTU X,$176
LDO X,$29
LDOU X,$222
LDW X,$222
LDWU X,$222
LDSF X,$222
LDHT X,$222
CSWAP X,$222
LDUNC X,$222
LDVTS X,$222
GO X,$222
STB X,$222
STT X,$222
STBU X,$222
STTU X,$222
STO X,$222
STOU X,$222
STW X,$222
STWU X,$222
STSF X,$222
STHT X,$222
STUNC X,$222
LDA $223,$219
LDB $223,$239
LDT $223,$239
LDBU $223,$29
LDTU $223,$239
LDO $23,$239
LDOU $223,$239
LDW $223,$209
LDWU $123,$239
LDSF $223,$239
LDHT $223,$29
CSWAP $223,$239
LDUNC $123,$239
LDVTS $223,$239
GO $223,$239
STB $223,$239
STT $223,$249
STBU $203,$239
STTU $73,$239
STO $223,$239
STOU $223,$39
STW $223,$239
STWU $233,$239
STSF $223,$239
STHT $223,$23
STUNC $223,$239
GO X,Y,0
LDVTS $32,Y,0
STB Y,$32,0
STUNC $232,$133,0
STWU X,Y,0
STO $31,Y,0
GO X,$38,0
CSWAP $4,$175,0
X IS $23
Y IS $12
Z IS $67
Z0 IS 176
|
stsp/binutils-ia16
| 1,122
|
gas/testsuite/gas/mmix/pushgo-op.s
|
# PUSHGO. Like T, but $X can be expressed as a constant.
# Using regt-op as a template caused this to go out of control.
Main PUSHGO X,Y,Z
PUSHGO XC,Y,Z
PUSHGO $32,Y,Z
PUSHGO 32,Y,Z
PUSHGO X,$32,Z
PUSHGO XC,$32,Z
PUSHGO $232,$133,Z
PUSHGO 232,$133,Z
PUSHGO X,Y,$73
PUSHGO XC,Y,$73
PUSHGO $31,Y,$233
PUSHGO 31,Y,$233
PUSHGO X,$38,$212
PUSHGO XC,$38,$212
PUSHGO $4,$175,$181
PUSHGO 4,$175,$181
PUSHGO X,Y,Z0
PUSHGO XC,Y,Z0
PUSHGO $32,Y,Z0
PUSHGO 32,Y,Z0
PUSHGO X,$32,Z0
PUSHGO XC,$32,Z0
PUSHGO $232,$133,Z0
PUSHGO 232,$133,Z0
PUSHGO X,Y,203
PUSHGO XC,Y,203
PUSHGO $31,Y,213
PUSHGO 31,Y,213
PUSHGO X,$38,211
PUSHGO XC,$38,211
PUSHGO $4,$175,161
PUSHGO 4,$175,161
PUSHGO X,Y
PUSHGO XC,Y
PUSHGO $41,Y
PUSHGO 241,Y
PUSHGO X,$27
PUSHGO XC,$48
PUSHGO $223,$219
PUSHGO 223,$229
PUSHGO X,Y,0
PUSHGO XC,Y,0
PUSHGO $32,Y,0
PUSHGO 32,Y,0
PUSHGO X,$32,0
PUSHGO XC,$32,0
PUSHGO $232,$133,0
PUSHGO 232,$133,0
PUSHGO X,Y,0
PUSHGO XC,Y,0
PUSHGO $31,Y,0
PUSHGO 31,Y,0
PUSHGO X,$38,0
PUSHGO XC,$38,0
PUSHGO $4,$175,0
PUSHGO 4,$175,0
X IS $23
XC IS 203
Y IS $12
Z IS $67
Z0 IS 176
|
stsp/binutils-ia16
| 1,027
|
gas/testsuite/gas/mmix/relax2.s
|
# PUSHJ stub border-cases: two with either or both stubs unreachable,
# local symbols, ditto non-local labels, similar with three PUSHJs.
# Note the absence of ":" on labels: because it's a symbol-character,
# it's concatenated with the parameter macro name and parsed as "\x:".
# This happens before gas deals with ":" as it usually does; not being
# part of the name when ending a label at the beginning of a line.
# (Since we're LABELS_WITHOUT_COLONS it inserts one for us, but
# that would be disabled with --gnu-syntax.)
Main SWYM
.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12
.section .text.a\x,"ax"
aa\x .space 4,0
a\x .space 65536*4,0
PUSHJ $33,aa\x
PUSHJ $22,a\x
.space 65535*4-4*\x
.section .text.b\x,"ax"
bbb\x .space 4,0
bb\x .space 4,0
b\x .space 65535*4
PUSHJ $12,bbb\x
PUSHJ $13,bb\x
PUSHJ $14,b\x
.space 65535*4-4*\x
.section .text.c\x,"ax"
c\x PUSHJ $100,ca\x
PUSHJ $101,cb\x
.space 65535*4-4*\x
.section .text.d\x,"ax"
d\x PUSHJ $99,da\x
PUSHJ $98,db\x
PUSHJ $97,dc\x
.space 65535*4-4*\x
.endr
|
stsp/binutils-ia16
| 1,446
|
gas/testsuite/gas/mmix/comment-1.s
|
# Check that "naked" comments are accepted and ignored on all different
# mnemonic types and pseudos. The goal is to use all combinations of
# operands where varying number of operands are allowed. If any
# combinations are missing, for simplicity, add them to another file.
Main TRAP 123 ignore; x y z
TRAP 1,23 all; x y z
TRAP 1,2,3 these; x y z
FCMP $3,$2,$1 comments; x y z
FLOT $5,6 and; x y z
FLOT $7,ROUND_UP,8 do; x y z
FIX $9,$10 nothing; x y z
FIX $11,ROUND_DOWN,$12 that; x y z
ADDU $15,$16,17 would make; x y z
LDA $18,$19 a; x y z
LDA $20,$21,22 difference; x y z
NEG $23,$24 in; x y z
NEG $25,26,$27 the; x y z
bn $28,target + 44 generated; x y z
SYNCD 29,$30,31 code; x y z
PUSHGO 32,$33,34 so; x y z
SET $35,$36 it; x y z
SETH $37,target2 + 48 is; x y z
JMP target3 + 56 as; x y z
POP 38,39 if; x y z
RESUME 40 it; x y z
PUSHJ $41,target3 had; x y z
SAVE $42,0 never; x y z
UNSAVE 0,$43 been; x y z
PUT rJ,$44 there; x y z
GET $45,rJ at all.; x y z
LOC @+4 likewise; x y z
PREFIX : with; x y z
BYTE 3,2,1,0+4 the; x y z
WYDE 7,4+8 different; x y z
TETRA 8+12 pseudo; x y z
OCTA 12+16 ops,; x y z
LOCAL 48 they; x y z
BSPEC 49 too; x y z
# Specifying an operand field (although ignored) is necessary for a comment
# with a ';' to be ignorable and not interpreted as eoln, both for GAS and
# mmixal.
ESPEC 0 ignore; x y z
GREG 50 + 1 naked; x y z
z IS 9 + 8 + 7 comments; x y z
x SWYM 34,21,56
|
stsp/binutils-ia16
| 4,890
|
gas/testsuite/gas/mmix/list-insns.s
|
#
# Somewhat complete instruction set and operand type check. No
# relocations or deferred register definitions here.
#
#
#
Main TETRA 3
TRAP 3,4,5
FCMP $12,$23,$241
FLOT $112,ROUND_OFF,$41
FLOT $112,ROUND_NEAR,141
FLOT $191,$242
FLOT $195,42
FUN $122,$203,$4
FEQL $102,$30,$40
FLOTU $102,$14
FLOTU $132,ROUND_UP,$14
FLOTU $102,ROUND_DOWN,$104
FLOTU $172,ROUND_NEAR,$140
FLOTU $1,ROUND_OFF,$134
FADD $112,$223,$41
FIX $112,ROUND_OFF,$41
FIX $11,$141
SFLOT $112,ROUND_OFF,$41
SFLOT $112,ROUND_NEAR,141
FSUB $112,$223,$41
FIXU $102,$14
FIXU $132,ROUND_UP,$14
SFLOTU $11,$141
SFLOTU $112,141
SFLOTU $112,ROUND_NEAR,141
SFLOTU $112,ROUND_OFF,$41
FMUL $102,$30,$40
FCMPE $12,$223,$1
MUL $122,$203,44
MUL $102,$30,$40
FEQLE $12,$223,$1
FUNE $12,$223,$11
MULU $122,$213,44
MULU $132,$30,$40
FDIV $12,$223,$11
FSQRT $132,ROUND_UP,$14
FSQRT $11,$141
DIV $122,$213,44
DIV $132,$30,$40
FREM $12,$223,$11
FINT $132,ROUND_UP,$14
FINT $11,$141
DIVU $12,$223,$1
DIVU $122,$203,255
ADD $12,$223,$1
ADD $122,$203,255
2ADDU $12,$223,$11
2ADDU $122,$203,0
ADDU $122,$203,255
ADDU $12,$223,$11
LDA $122,$203,255
LDA $12,$223,$11
4ADDU $122,$203,205
4ADDU $12,$223,$111
SUB $12,$223,$11
SUB $122,$203,205
8ADDU $12,$223,$11
8ADDU $122,$203,205
SUBU $2,$223,$11
SUBU $12,$20,205
16ADDU $2,$223,$11
16ADDU $12,$20,205
CMP $2,$223,$11
CMP $12,$20,205
SL $2,$223,$11
SL $12,$20,205
CMPU $2,$223,$11
CMPU $12,$20,205
SLU $2,$223,$11
SLU $12,$20,205
NEG $2,23,$11
NEG $12,0,205
NEG $192,10,205
SR $12,$20,205
SR $2,$223,$11
NEGU $2,23,$11
NEGU $12,0,205
SRU $12,$20,205
SRU $2,$223,$11
1H BN $2,2F
2H BN $2,1B
1H BNN $2,2B
2H BNN $2,1B
1H BZ $255,2F
2H BZ $255,1B
1H BNZ $255,2F
2H BNZ $255,1B
1H BP $25,2F
2H BP $25,1B
1H BNP $25,2F
2H BNP $25,1B
1H BOD $25,2F
2H BOD $25,1B
1H BEV $25,2F
2H BEV $25,1B
1H PBN $2,2F
2H PBN $2,1B
1H PBNN $2,2F
2H PBNN $2,1B
1H PBZ $12,2F
2H PBZ $22,1B
1H PBNZ $32,2F
2H PBNZ $52,1B
1H PBOD $25,2F
2H PBOD $25,1B
1H PBEV $25,2F
2H PBEV $25,1B
CSN $2,$223,$11
CSN $12,$20,205
CSNN $2,$223,$11
CSNN $12,$20,205
CSZ $2,$203,$11
CSZ $12,$200,205
CSNZ $2,$203,$11
CSNZ $12,$200,205
CSP $2,$203,$11
CSP $12,$200,205
CSNP $2,$203,$11
CSNP $12,$200,205
CSOD $2,$203,$11
CSOD $12,$200,205
CSEV $2,$203,$11
CSEV $12,$200,205
ZSN $2,$223,$11
ZSN $12,$20,205
ZSNN $2,$223,$11
ZSNN $12,$20,205
ZSZ $2,$203,$11
ZSZ $12,$200,205
ZSNZ $2,$203,$11
ZSNZ $12,$200,205
ZSP $2,$203,$11
ZSP $12,$200,205
ZSNP $2,$203,$11
ZSNP $12,$200,205
ZSOD $2,$203,$11
ZSOD $12,$200,205
ZSEV $2,$203,$11
ZSEV $12,$200,205
LDB $2,$0,$11
LDB $12,$20,205
LDT $2,$0,$11
LDT $12,$20,205
LDBU $2,$0,$11
LDBU $12,$20,205
LDTU $2,$0,$11
LDTU $12,$20,205
LDW $2,$0,$11
LDW $12,$20,205
LDO $2,$0,$11
LDO $12,$20,205
LDWU $2,$0,$11
LDWU $12,$20,205
LDOU $2,$0,$11
LDOU $12,$20,205
LDVTS $2,$0,$11
LDVTS $12,$20,205
LDHT $2,$0,$11
LDHT $12,$20,205
PRELD 112,$20,205
PRELD 112,$20,$225
CSWAP $2,$0,$11
CSWAP $12,$20,205
PREGO 112,$20,205
PREGO 112,$20,$225
LDUNC $2,$0,$11
LDUNC $12,$20,205
GO $2,$0,$11
GO $12,$20,205
STB $2,$10,$151
STB $12,$20,205
STT $32,$10,$151
STT $12,$20,205
STBU $2,$10,$151
STBU $12,$20,205
STTU $32,$10,$151
STTU $12,$20,205
STW $2,$10,$151
STW $12,$220,205
STO $32,$170,$151
STO $182,$20,245
STWU $2,$10,$151
STWU $12,$220,205
STOU $32,$170,$151
STOU $182,$20,245
STSF $32,$170,$151
STSF $182,$20,245
SYNCD 112,$20,205
SYNCD 112,$20,$225
STHT $32,$170,$151
STHT $182,$20,245
PREST 112,$20,205
PREST 112,$20,$225
STCO 32,$170,$151
STCO 182,$20,245
SYNCID 112,$20,205
SYNCID 0,$20,$225
STUNC $32,$170,$151
STUNC $182,$20,245
PUSHGO $32,$170,$151
PUSHGO $182,$20,245
SET $142,$200
OR $32,$170,$151
OR $182,$20,245
AND $32,$170,$151
AND $182,$20,245
ORN $32,$170,$151
ORN $182,$20,245
ANDN $32,$170,$151
ANDN $182,$20,245
NOR $32,$170,$151
NOR $182,$20,245
NAND $32,$170,$151
NAND $182,$20,245
XOR $32,$170,$151
XOR $182,$20,245
NXOR $32,$170,$151
NXOR $182,$20,245
BDIF $32,$170,$151
BDIF $182,$20,245
MUX $32,$170,$151
MUX $182,$20,245
WDIF $32,$170,$151
WDIF $182,$20,245
SADD $32,$170,$151
SADD $182,$0,245
TDIF $32,$170,$151
TDIF $182,$20,245
MOR $32,$170,$151
MOR $182,$20,245
ODIF $32,$170,$151
ODIF $182,$20,245
MXOR $32,$17,$151
MXOR $82,$180,24
SETH $4,65535
SETH $94,0
SETH $4,255
SETH $94,1234
SETMH $94,1234
ORH $94,1234
ORMH $94,1234
SETML $94,1234
SETL $94,1234
ORML $94,1234
ORL $94,1234
INCH $94,1234
INCMH $94,1234
ANDNH $94,1234
ANDNMH $94,1234
INCML $94,1234
INCL $94,1234
ANDNML $94,1234
0H ANDNL $94,1234
JMP 0B
JMP 0F
0H POP 42,65534
RESUME 255
RESUME 0
RESUME 1
1H PUSHJ $25,2F
2H PUSHJ $25,1B
SAVE $4,0
UNSAVE 0,$234
1H GETA $25,2F
2H GETA $25,1B
SYNC 8000001
SWYM 1,2,3
SWYM 0,0,0
PUT rJ,34
PUT rJ,$134
GET $234,rJ
TRIP 0,0,0
TRIP 5,6,7
|
stsp/binutils-ia16
| 9,316
|
gas/testsuite/gas/tic4x/allopcodes.S
|
;;;
;;; Test all opcodes and argument permuation
;;; To make our job a lot simpler, we define a couple of
;;; insn classes, that we use to generate the proper
;;; test output.
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
;;;
;;; These definitions are used within this file:
;;; TEST_C3X Enables testing of c3x opcodes
;;; TEST_C4X Enables testing of c4x opcodes
;;; TEST_ENH Enable testing of enhanced opcodes
;;; TEST_IDLE2 Enable testing of IDLE2 command
;;; TEST_LPWR Enable testing of LOPOWER commands
;;;
#include "opclasses.h"
.text
;;------------------------------------
;; C3X INSNS
;;------------------------------------
start: B_CLASS( absf, TEST_C3X )
P_CLASS( absf, stf, TEST_C3X )
A_CLASS( absi, TEST_C3X )
P_CLASS( absi, sti, TEST_C3X )
A_CLASS( addc, TEST_C3X )
TC_CLASS( addc, TEST_C3X )
B_CLASS( addf, TEST_C3X )
SC_CLASS( addf, TEST_C3X )
QC_CLASS( addf, stf, TEST_C3X )
A_CLASS( addi, TEST_C3X )
TC_CLASS( addi, TEST_C3X )
QC_CLASS( addi, sti, TEST_C3X )
AU_CLASS( and, TEST_C3X )
TC_CLASS( and, TEST_C3X )
QC_CLASS( and, sti, TEST_C3X )
AU_CLASS( andn, TEST_C3X )
T_CLASS( andn, TEST_C3X )
A_CLASS( ash, TEST_C3X )
T_CLASS( ash, TEST_C3X )
Q_CLASS( ash, sti, TEST_C3X )
J_CLASS( bC, b, TEST_C3X )
J_CLASS( bCd, bd, TEST_C3X )
.ifdef TEST_C3X
br_I: br start
brd_I: brd start
call_I: call start
call_JS: callc R0
callc start
.endif
B_CLASS( cmpf, TEST_C3X )
S2_CLASS( cmpf, TEST_C3X )
A_CLASS( cmpi, TEST_C3X )
T2_CLASS( cmpi, TEST_C3X )
D_CLASS( dbC, db, TEST_C3X )
D_CLASS( dbCd, dbd, TEST_C3X )
AF_CLASS( fix, TEST_C3X )
P_CLASS( fix, sti, TEST_C3X )
BI_CLASS( float, TEST_C3X )
P_CLASS( float, stf, TEST_C3X )
.ifdef TEST_C3X
iack_Z: iack @start
iack *+AR0(1)
idle_Z: idle
.endif
.ifdef TEST_IDLE2
idle2_Z: idle2
.endif
B_CLASS( lde, TEST_C3X )
B_CLASS( ldf, TEST_C3X )
LL_CLASS( ldf, TEST_C3X )
P_CLASS( ldf, stf, TEST_C3X )
BB_CLASS( ldfC, TEST_C3X )
B6_CLASS( ldfi, TEST_C3X )
A_CLASS( ldi, TEST_C3X )
LL_CLASS( ldi, TEST_C3X )
P_CLASS( ldi, sti, TEST_C3X )
AB_CLASS( ldiC, TEST_C3X )
A6_CLASS( ldii, TEST_C3X )
.ifdef TEST_C3X
ldp_Z: ldp start
.endif
B_CLASS( ldm, TEST_C3X )
.ifdef TEST_LPWR
lopower_Z: lopower
.endif
A_CLASS( lsh, TEST_C3X )
T_CLASS( lsh, TEST_C3X )
Q_CLASS( lsh, sti, TEST_C3X )
.ifdef TEST_LPWR
maxspeed_Z: maxspeed
.endif
B_CLASS( mpyf, TEST_C3X )
SC_CLASS( mpyf, TEST_C3X )
M_CLASS( mpyf, addf, TEST_C3X )
QC_CLASS( mpyf, stf, TEST_C3X )
M_CLASS( mpyf, subf, TEST_C3X )
A_CLASS( mpyi, TEST_C3X )
TC_CLASS( mpyi, TEST_C3X )
M_CLASS( mpyi, addi, TEST_C3X )
QC_CLASS( mpyi, sti, TEST_C3X )
M_CLASS( mpyi, subi, TEST_C3X )
A_CLASS( negb, TEST_C3X )
B_CLASS( negf, TEST_C3X )
P_CLASS( negf, stf, TEST_C3X )
A_CLASS( negi, TEST_C3X )
P_CLASS( negi, sti, TEST_C3X )
A2_CLASS( nop, TEST_C3X )
B_CLASS( norm, TEST_C3X )
AU_CLASS( not, TEST_C3X )
P_CLASS( not, sti, TEST_C3X )
AU_CLASS( or, TEST_C3X )
TC_CLASS( or, TEST_C3X )
QC_CLASS( or, sti, TEST_C3X )
R_CLASS( pop, TEST_C3X )
RF_CLASS( popf, TEST_C3X )
R_CLASS( push, TEST_C3X )
RF_CLASS( pushf, TEST_C3X )
.ifdef TEST_C3X
reti_Z: retiC
reti
rets_Z: retsC
rets
.endif
B_CLASS( rnd, TEST_C3X )
R_CLASS( rol, TEST_C3X )
R_CLASS( rolc, TEST_C3X )
R_CLASS( ror, TEST_C3X )
R_CLASS( rorc, TEST_C3X )
.ifdef TEST_C3X
rptb_I2: rptb start
.endif
A3_CLASS( rpts, TEST_C3X )
.ifdef TEST_C3X
sigi_Z: sigi
.endif
B7_CLASS( stf, TEST_C3X )
LS_CLASS( stf, TEST_C3X )
B7_CLASS( stfi, TEST_C3X )
A7_CLASS( sti, TEST_C3X )
LS_CLASS( sti, TEST_C3X )
A7_CLASS( stii, TEST_C3X )
A_CLASS( subb, TEST_C3X )
T_CLASS( subb, TEST_C3X )
A_CLASS( subc, TEST_C3X )
B_CLASS( subf, TEST_C3X )
S_CLASS( subf, TEST_C3X )
Q_CLASS( subf, stf, TEST_C3X )
A_CLASS( subi, TEST_C3X )
T_CLASS( subi, TEST_C3X )
Q_CLASS( subi, sti, TEST_C3X )
A_CLASS( subrb, TEST_C3X )
B_CLASS( subrf, TEST_C3X )
A_CLASS( subri, TEST_C3X )
.ifdef TEST_C3X
swi_Z: swi
trap_Z: trapC 10
trap 10
.endif
AU_CLASS( tstb, TEST_C3X )
T2C_CLASS( tstb, TEST_C3X )
AU_CLASS( xor, TEST_C3X )
TC_CLASS( xor, TEST_C3X )
QC_CLASS( xor, sti, TEST_C3X )
;;------------------------------------
;; C4X INSNS
;;------------------------------------
.ifdef TEST_C4X
J_CLASS( bCaf, baf, TEST_C4X )
J_CLASS( bCat, bat, TEST_C4X )
B6_CLASS( frieee, TEST_C4X )
P_CLASS( frieee, stf, TEST_C4X )
.ifdef TEST_C4X
laj_I: laj start
laj_JS: lajc R0
lajc start
lat_Z: latC 10
.endif
A_CLASS( lb0, TEST_C4X )
A_CLASS( lb1, TEST_C4X )
A_CLASS( lb2, TEST_C4X )
A_CLASS( lb3, TEST_C4X )
AU_CLASS( lbu0, TEST_C4X )
AU_CLASS( lbu1, TEST_C4X )
AU_CLASS( lbu2, TEST_C4X )
AU_CLASS( lbu3, TEST_C4X )
AY_CLASS( lda, TEST_C4X )
.ifdef TEST_C4X
ldep_Z: ldep IVTP, AR0
ldhi_Z: ldhi 35, R0
ldhi start, R0
ldpe_Z: ldpe AR0, IVTP
ldpk_Z: ldpk start
.endif
A_CLASS( lh0, TEST_C4X )
A_CLASS( lh1, TEST_C4X )
AU_CLASS( lhu0, TEST_C4X )
AU_CLASS( lhu1, TEST_C4X )
A_CLASS( lwl0, TEST_C4X )
A_CLASS( lwl1, TEST_C4X )
A_CLASS( lwl2, TEST_C4X )
A_CLASS( lwl3, TEST_C4X )
A_CLASS( lwr0, TEST_C4X )
A_CLASS( lwr1, TEST_C4X )
A_CLASS( lwr2, TEST_C4X )
A_CLASS( lwr3, TEST_C4X )
A_CLASS( mb0, TEST_C4X )
A_CLASS( mb1, TEST_C4X )
A_CLASS( mb2, TEST_C4X )
A_CLASS( mb3, TEST_C4X )
A_CLASS( mh0, TEST_C4X )
A_CLASS( mh1, TEST_C4X )
A_CLASS( mh2, TEST_C4X )
A_CLASS( mh3, TEST_C4X )
A_CLASS( mpyshi, TEST_C4X )
TC_CLASS( mpyshi, TEST_C4X )
A_CLASS( mpyuhi, TEST_C4X )
TC_CLASS( mpyuhi, TEST_C4X )
BA_CLASS( rcpf, TEST_C4X )
.ifdef TEST_C4X
retid_Z: retiCd
retid
rptb2_I2: rptb AR0
rptbd_I2: rptbd start
rptbd AR0
.endif
B_CLASS( rsqrf, TEST_C4X )
A6_CLASS( sigi, TEST_C4X )
.ifdef TEST_C4X
sti2_A7: sti -5, @start
sti -5, *+AR0(5)
stik_Z: stik -5, @start
stik -5, *+AR0(5)
.endif
B_CLASS( toieee, TEST_C4X )
P_CLASS( toieee, stf, TEST_C4X )
.endif
.end
|
stsp/binutils-ia16
| 12,646
|
gas/testsuite/gas/tic4x/addressing.s
|
;;
;; test all addressing modes and register constraints
;; (types/classes is read from include/opcodes/tic4x.h)
;;
.text
start:
;;
;; Type B - infix condition branch
;;
Type_BI:bu Type_BI ; Unconditional branch (00000)
bc Type_BI ; Carry branch (00001)
blo Type_BI ; Lower than branch (00001)
bls Type_BI ; Lower than or same branch (00010)
bhi Type_BI ; Higher than branch (00011)
bhs Type_BI ; Higher than or same branch (00100)
bnc Type_BI ; No carry branch (00100)
beq Type_BI ; Equal to branch (00101)
bz Type_BI ; Zero branch (00101)
bne Type_BI ; Not equal to branch (00110)
bnz Type_BI ; Not zero branch (00110)
blt Type_BI ; Less than branch (00111)
bn Type_BI ; Negative branch (00111)
ble Type_BI ; Less than or equal to branch (01000)
bgt Type_BI ; Greater than branch (01001)
bp Type_BI ; Positive branch (01001)
bge Type_BI ; Greater than or equal branch (01010)
bnn Type_BI ; Nonnegative branch (01010)
bnv Type_BI ; No overflow branch (01000)
bv Type_BI ; Overflow branch (01101)
bnuf Type_BI ; No underflow branch (01110)
buf Type_BI ; Underflow branch (01111)
bnlv Type_BI ; No latched overflow branch (10000)
blv Type_BI ; Latched overflow branch (10001)
bnluf Type_BI ; No latched FP underflow branch (10010)
bluf Type_BI ; Latched FP underflow branch (10011)
bzuf Type_BI ; Zero or FP underflow branch (10100)
b Type_BI ; Unconditional branch (00000)
;;
;; Type C - infix condition load
;;
Type_CI:ldiu R0,R0 ; Unconditional load (00000)
ldic R0,R0 ; Carry load (00001)
ldilo R0,R0 ; Lower than load (00001)
ldils R0,R0 ; Lower than or same load (00010)
ldihi R0,R0 ; Higher than load (00011)
ldihs R0,R0 ; Higher than or same load (00100)
ldinc R0,R0 ; No carry load (00100)
ldieq R0,R0 ; Equal to load (00101)
ldiz R0,R0 ; Zero load (00101)
ldine R0,R0 ; Not equal to load (00110)
ldinz R0,R0 ; Not zero load (00110)
ldil R0,R0 ; Less than load (00111)
ldin R0,R0 ; Negative load (00111)
ldile R0,R0 ; Less than or equal to load (01000)
ldigt R0,R0 ; Greater than load (01001)
ldip R0,R0 ; Positive load (01001)
ldige R0,R0 ; Greater than or equal load (01010)
ldinn R0,R0 ; Nonnegative load (01010)
ldinv R0,R0 ; No overflow load (01000)
ldiv R0,R0 ; Overflow load (01101)
ldinuf R0,R0 ; No underflow load (01110)
ldiuf R0,R0 ; Underflow load (01111)
ldinlv R0,R0 ; No latched overflow load (10000)
ldilv R0,R0 ; Latched overflow load (10001)
ldinluf R0,R0 ; No latched FP underflow load (10010)
ldiluf R0,R0 ; Latched FP underflow load (10011)
ldizuf R0,R0 ; Zero or FP underflow load (10100)
;;
;; Type * - Indirect (full)
;;
Type_ind:
ldi *AR0,R0 ; Indirect addressing (G=10)
ldi *+AR0(5),R0 ; with predisplacement add
ldi *-AR0(5),R0 ; with predisplacement subtract
ldi *++AR0(5),R0 ; with predisplacement add and modify
ldi *--AR0(5),R0 ; with predisplacement subtract and modify
ldi *AR0++(5),R0 ; with postdisplacement add and modify
ldi *AR0--(5),R0 ; with postdisplacement subtract and modify
ldi *AR0++(5)%,R0 ; with postdisplacement add and circular modify
ldi *AR0--(5)%,R0 ; with postdisplacement subtract and circular modify
ldi *+AR0(IR0),R0 ; with predisplacement add
ldi *-AR0(IR0),R0 ; with predisplacement subtract
ldi *++AR0(IR0),R0 ; with predisplacement add and modify
ldi *--AR0(IR0),R0 ; with predisplacement subtract and modify
ldi *AR0++(IR0),R0 ; with postdisplacement add and modify
ldi *AR0--(IR0),R0 ; with postdisplacement subtract and modify
ldi *AR0++(IR0)%,R0 ; with postdisplacement add and circular modify
ldi *AR0--(IR0)%,R0 ; with postdisplacement subtract and circular modify
ldi *AR0++(IR0)B,R0 ; with postincrement add and bit-reversed modify
ldi *AR0++,R0 ; Same as *AR0++(1)
;;
;; Type # - Direct for ldp
;;
Type_ldp:
ldp 12
ldp @start
ldp start
;;
;; Type @ - Direct
;;
Type_dir:
ldi @start,R0
ldi start,R0
ldi @16,R0
ldi @65535,R0
;;
;; Type A - Address register
;;
Type_A: dbc AR0,R0
dbc AR2,R0
dbc AR7,R0
;;
;; Type B - Unsigned integer (PC)
;;
Type_B: br start
br 0x809800
;;
;; Type C - Indirect
;;
.ifdef TEST_C4X
Type_C: addc3 *+AR0(5),R0,R0
.endif
;;
;; Type E - Register (all)
;;
Type_E: andn3 R0,R0,R0
andn3 AR0,R0,R0
addc3 DP,R0,R0
andn3 R7,R0,R0
;;
;; Type e - Register (0-11)
;;
Type_ee:subf3 R7,R0,R0
addf3 R0,R0,R0
addf3 R7,R0,R0
cmpf3 R7,R0
.ifdef TEST_C4X
addf3 R11,R0,R0
.endif
;;
;; Type F - Short float immediate
;;
Type_F: ldf 0,R0
ldf 3.5,R0
ldf -3.5,R0
ldf 0e-3.5e-1,R0
;;
;; Type G - Register (all)
;;
Type_G: andn3 R0,AR0,R0
addc3 R0,DP,R0
addc3 R0,R0,R0
andn3 R0,R7,R0
;;
;; Type g - Register (0-11)
;;
Type_gg:subf3 R0,R7,R0
addf3 R0,R0,R0
addf3 R0,R7,R0
cmpf3 R0,R7
.ifdef TEST_C4X
addf3 R0,R11,R0
.endif
;;
;; Type H - Register (0-7)
;;
Type_H: stf R0,*AR0 &|| stf R0,*AR0
stf R0,*AR0 &|| stf R2,*AR0
stf R0,*AR0 &|| stf R7,*AR0
;;
;; Type I - Indirect
;;
Type_I: addf3 *AR0,R0,R0 ; Indirect addressing (G=10)
addf3 *+AR0(1),R0,R0 ; with predisplacement add
addf3 *-AR0(1),R0,R0 ; with predisplacement subtract
addf3 *++AR0(1),R0,R0 ; with predisplacement add and modify
addf3 *--AR0(1),R0,R0 ; with predisplacement subtract and modify
addf3 *AR0++(1),R0,R0 ; with postdisplacement add and modify
addf3 *AR0--(1),R0,R0 ; with postdisplacement subtract and modify
addf3 *AR0++(1)%,R0,R0; with postdisplacement add and circular modify
addf3 *AR0--(1)%,R0,R0; with postdisplacement subtract and circular modify
addf3 *+AR0(IR0),R0,R0; with predisplacement add
addf3 *-AR0(IR0),R0,R0; with predisplacement subtract
addf3 *++AR0(IR0),R0,R0; with predisplacement add and modify
addf3 *--AR0(IR0),R0,R0; with predisplacement subtract and modify
addf3 *AR0++(IR0),R0,R0; with postdisplacement add and modify
addf3 *AR0--(IR0),R0,R0; with postdisplacement subtract and modify
addf3 *AR0++(IR0)%,R0,R0; with postdisplacement add and circular modify
addf3 *AR0--(IR0)%,R0,R0; with postdisplacement subtract and circular modify
addf3 *AR0++(IR0)B,R0,R0; with postincrement add and bit-reversed modify
addf3 *AR0++,R0,R0 ; Same as *AR0++(1)
;;
;; Type J - Indirect
;;
Type_J: addf3 R0,*AR0,R0 ; Indirect addressing (G=10)
addf3 R0,*+AR0(1),R0 ; with predisplacement add
addf3 R0,*-AR0(1),R0 ; with predisplacement subtract
addf3 R0,*++AR0(1),R0 ; with predisplacement add and modify
addf3 R0,*--AR0(1),R0 ; with predisplacement subtract and modify
addf3 R0,*AR0++(1),R0 ; with postdisplacement add and modify
addf3 R0,*AR0--(1),R0 ; with postdisplacement subtract and modify
addf3 R0,*AR0++(1)%,R0; with postdisplacement add and circular modify
addf3 R0,*AR0--(1)%,R0; with postdisplacement subtract and circular modify
addf3 R0,*+AR0(IR0),R0; with predisplacement add
addf3 R0,*-AR0(IR0),R0; with predisplacement subtract
addf3 R0,*++AR0(IR0),R0; with predisplacement add and modify
addf3 R0,*--AR0(IR0),R0; with predisplacement subtract and modify
addf3 R0,*AR0++(IR0),R0; with postdisplacement add and modify
addf3 R0,*AR0--(IR0),R0; with postdisplacement subtract and modify
addf3 R0,*AR0++(IR0)%,R0; with postdisplacement add and circular modify
addf3 R0,*AR0--(IR0)%,R0; with postdisplacement subtract and circular modify
addf3 R0,*AR0++(IR0)B,R0; with postincrement add and bit-reversed modify
addf3 R0,*AR0++,R0 ; Same as *AR0++(1)
;;
;; Type K - Register (0-7)
;;
Type_K: ldf *AR0,R0 &|| ldf *AR0,R1
ldf *AR0,R0 &|| ldf *AR0,R2
ldf *AR0,R0 &|| ldf *AR0,R7
;;
;; Type L - Register (0-7)
;;
Type_L: stf R0,*AR0 &|| stf R0,*AR0
stf R2,*AR0 &|| stf R0,*AR0
stf R7,*AR0 &|| stf R0,*AR0
;;
;; Type M - Register (2-3)
;;
Type_M: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R3
;;
;; Type N - Register (0-1)
;;
Type_N: mpyf3 *AR0,*AR0,R0 &|| addf3 R0,R0,R2
mpyf3 *AR0,*AR0,R1 &|| addf3 R0,R0,R2
;;
;; Type O - Indirect
;;
.ifdef TEST_C4X
Type_O: addc3 *+AR0(5),*+AR0(5),R0
.endif
;;
;; Type P - Displacement (PC rel)
;;
Type_P: callc start
callc 1
;;
;; Type Q - Register (all)
;;
Type_Q: ldi R0,R0
ldi AR0,R0
ldi DP,R0
ldi SP,R0
;;
;; Type q - Register (0-11)
;;
Type_qq:fix R0,R0
fix R7,R0
.ifdef TEST_C4X
fix R11,R0
absf R11,R0
.endif
;;
;; Type R - Register (all)
;;
Type_R: ldi R0,R0
ldi R0,AR0
ldi R0,DP
ldi R0,SP
;;
;; Type r - Register (0-11)
;;
Type_rr:ldf R0,R0
ldf R0,R7
.ifdef TEST_C4X
ldf R0,R11
.endif
;;
;; Type S - Signed immediate
;;
Type_S: ldi 0,R0
ldi -123,R0
ldi 6543,R0
ldi -32768, R0
;;
;; Type T - Integer
;;
.ifdef TEST_C4X
Type_T: stik 0,*AR0
stik 12,*AR0
stik -5,*AR0
.endif
;;
;; Type U - Unsigned integer
;;
Type_U: and 0,R0
and 256,R0
and 65535,R0
;;
;; Type V - Vector
;;
Type_V: trapu 12
trapu 0
trapu 31
.ifdef TEST_C4X
trapu 511
.endif
;;
;; Type W - Short int
;;
.ifdef TEST_C4X
Type_W: addc3 -3,R0,R0
addc3 5,R0,R0
.endif
;;
;; Type X - Expansion register
;;
.ifdef TEST_C4X
Type_X: ldep IVTP,R0
ldep TVTP,R0
.endif
;;
;; Type Y - Address register
;;
.ifdef TEST_C4X
Type_Y: lda R0,AR0
lda R0,DP
lda R0,SP
lda R0,IR0
.endif
;;
;; Type Z - Expansion register
;;
.ifdef TEST_C4X
Type_Z: ldpe R0,IVTP
ldpe R0,TVTP
.endif
|
stsp/binutils-ia16
| 178,320
|
gas/testsuite/gas/tic4x/opcodes.s
|
; File is autogenerated from allopcodes.S - do not edit
; Please use ./rebuild.sh to rebuild this file
;;;
;;; Test all opcodes and argument permuation
;;; To make our job a lot simpler, we define a couple of
;;; insn classes, that we use to generate the proper
;;; test output.
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
;;;
;;; These definitions are used within this file:
;;; TEST_C3X Enables testing of c3x opcodes
;;; TEST_C4X Enables testing of c4x opcodes
;;; TEST_ENH Enable testing of enhanced opcodes
;;; TEST_IDLE2 Enable testing of IDLE2 command
;;; TEST_LPWR Enable testing of LOPOWER commands
;;;
.text
;;------------------------------------
;; C3X INSNS
;;------------------------------------
start: .ifdef TEST_C3X & absf_B: & absf R1, R0 & absf R0 & absf @start, R0 & absf *+AR0(5), R0 & absf 3.5, R0 & .endif
.ifdef TEST_C3X & absf_stf_P: & absf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & absf_stf_P_enh: & absf R0, R0 &|| stf R1, *+AR1(1) & absf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf R0, R0 & stf R1, *+AR1(1) &|| absf R0 & .endif
.ifdef TEST_C3X & absi_A: & absi AR1, AR0 & absi AR0 & absi @start, AR0 & absi *+AR0(5), AR0 & absi -5, AR0 & .endif
.ifdef TEST_C3X & absi_sti_P: & absi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & absi_sti_P_enh: & absi R0, R0 &|| sti R1, *+AR1(1) & absi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi R0, R0 & sti R1, *+AR1(1) &|| absi R0 & .endif
.ifdef TEST_C3X & addc_A: & addc AR1, AR0 & addc AR0 & addc @start, AR0 & addc *+AR0(5), AR0 & addc -5, AR0 & .endif
.ifdef TEST_C3X & addc_TC: & addc AR2, AR1, AR0 & addc AR1, AR0 & addc AR1, *+AR0(1), AR0 & addc *+AR0(1), AR1, AR0 & addc *+AR0(1), AR0 & addc *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addc_TC_c4x: & addc -5, AR1, AR0 & addc -5, AR0 & addc AR1, -5, AR0 & addc *+AR0(5), AR1, AR0 & addc *+AR0(5), AR0 & addc AR1, *+AR0(5), AR0 & addc -5, *+AR0(5), AR0 & addc *+AR0(5), -5, AR0 & addc *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & addc3_TC: & addc3 AR2, AR1, AR0 & addc3 AR1, AR0 & addc3 AR1, *+AR0(1), AR0 & addc3 *+AR0(1), AR1, AR0 & addc3 *+AR0(1), AR0 & addc3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addc3_TC_c4x: & addc3 -5, AR1, AR0 & addc3 -5, AR0 & addc3 AR1, -5, AR0 & addc3 *+AR0(5), AR1, AR0 & addc3 *+AR0(5), AR0 & addc3 AR1, *+AR0(5), AR0 & addc3 -5, *+AR0(5), AR0 & addc3 *+AR0(5), -5, AR0 & addc3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & addf_B: & addf R1, R0 & addf R0 & addf @start, R0 & addf *+AR0(5), R0 & addf 3.5, R0 & .endif
.ifdef TEST_C3X & addf_SC: & addf R2, R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 & addf *+AR0(1), R1, R0 & addf *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & addf_SC_c4x: & addf *+AR0(5), R1, R0 & addf *+AR0(5), R0 & addf R1, *+AR0(5), R0 & addf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & addf3_SC: & addf3 R2, R1, R0 & addf3 R1, R0 & addf3 R1, *+AR0(1), R0 & addf3 *+AR0(1), R1, R0 & addf3 *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & addf3_SC_c4x: & addf3 *+AR0(5), R1, R0 & addf3 *+AR0(5), R0 & addf3 R1, *+AR0(5), R0 & addf3 *+AR0(5), *+AR1(5), R0 & .endif
.ifdef TEST_C3X & addf_stf_QC: & addf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_stf_QC_enh: & addf AR0, R1, R0 &|| stf R1, *+AR1(1) & addf R2, R1, R0 &|| stf R1, *+AR1(1) & addf R1, R0 &|| stf R1, *+AR1(1) & addf R0 &|| stf R1, *+AR1(1) & addf R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf AR0, R1, R0 & stf R1, *+AR1(1) &|| addf R2, R1, R0 & stf R1, *+AR1(1) &|| addf R1, R0 & stf R1, *+AR1(1) &|| addf R0 & stf R1, *+AR1(1) &|| addf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_stf_QC: & addf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_stf_QC_enh: & addf3 AR0, R1, R0 &|| stf R1, *+AR1(1) & addf3 R2, R1, R0 &|| stf R1, *+AR1(1) & addf3 R1, R0 &|| stf R1, *+AR1(1) & addf3 R0 &|| stf R1, *+AR1(1) & addf3 R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 AR0, R1, R0 & stf R1, *+AR1(1) &|| addf3 R2, R1, R0 & stf R1, *+AR1(1) &|| addf3 R1, R0 & stf R1, *+AR1(1) &|| addf3 R0 & stf R1, *+AR1(1) &|| addf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & addi_A: & addi AR1, AR0 & addi AR0 & addi @start, AR0 & addi *+AR0(5), AR0 & addi -5, AR0 & .endif
.ifdef TEST_C3X & addi_TC: & addi AR2, AR1, AR0 & addi AR1, AR0 & addi AR1, *+AR0(1), AR0 & addi *+AR0(1), AR1, AR0 & addi *+AR0(1), AR0 & addi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addi_TC_c4x: & addi -5, AR1, AR0 & addi -5, AR0 & addi AR1, -5, AR0 & addi *+AR0(5), AR1, AR0 & addi *+AR0(5), AR0 & addi AR1, *+AR0(5), AR0 & addi -5, *+AR0(5), AR0 & addi *+AR0(5), -5, AR0 & addi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & addi3_TC: & addi3 AR2, AR1, AR0 & addi3 AR1, AR0 & addi3 AR1, *+AR0(1), AR0 & addi3 *+AR0(1), AR1, AR0 & addi3 *+AR0(1), AR0 & addi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addi3_TC_c4x: & addi3 -5, AR1, AR0 & addi3 -5, AR0 & addi3 AR1, -5, AR0 & addi3 *+AR0(5), AR1, AR0 & addi3 *+AR0(5), AR0 & addi3 AR1, *+AR0(5), AR0 & addi3 -5, *+AR0(5), AR0 & addi3 *+AR0(5), -5, AR0 & addi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & addi_sti_QC: & addi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_sti_QC_enh: & addi AR0, R1, R0 &|| sti R1, *+AR1(1) & addi R2, R1, R0 &|| sti R1, *+AR1(1) & addi R1, R0 &|| sti R1, *+AR1(1) & addi R0 &|| sti R1, *+AR1(1) & addi R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi AR0, R1, R0 & sti R1, *+AR1(1) &|| addi R2, R1, R0 & sti R1, *+AR1(1) &|| addi R1, R0 & sti R1, *+AR1(1) &|| addi R0 & sti R1, *+AR1(1) &|| addi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_sti_QC: & addi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_sti_QC_enh: & addi3 AR0, R1, R0 &|| sti R1, *+AR1(1) & addi3 R2, R1, R0 &|| sti R1, *+AR1(1) & addi3 R1, R0 &|| sti R1, *+AR1(1) & addi3 R0 &|| sti R1, *+AR1(1) & addi3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 AR0, R1, R0 & sti R1, *+AR1(1) &|| addi3 R2, R1, R0 & sti R1, *+AR1(1) &|| addi3 R1, R0 & sti R1, *+AR1(1) &|| addi3 R0 & sti R1, *+AR1(1) &|| addi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & and_AU: & and AR1, AR0 & and AR0 & and @start, AR0 & and *+AR0(5), AR0 & and 5, AR0 & .endif
.ifdef TEST_C3X & and_TC: & and AR2, AR1, AR0 & and AR1, AR0 & and AR1, *+AR0(1), AR0 & and *+AR0(1), AR1, AR0 & and *+AR0(1), AR0 & and *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & and_TC_c4x: & and -5, AR1, AR0 & and -5, AR0 & and AR1, -5, AR0 & and *+AR0(5), AR1, AR0 & and *+AR0(5), AR0 & and AR1, *+AR0(5), AR0 & and -5, *+AR0(5), AR0 & and *+AR0(5), -5, AR0 & and *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & and3_TC: & and3 AR2, AR1, AR0 & and3 AR1, AR0 & and3 AR1, *+AR0(1), AR0 & and3 *+AR0(1), AR1, AR0 & and3 *+AR0(1), AR0 & and3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & and3_TC_c4x: & and3 -5, AR1, AR0 & and3 -5, AR0 & and3 AR1, -5, AR0 & and3 *+AR0(5), AR1, AR0 & and3 *+AR0(5), AR0 & and3 AR1, *+AR0(5), AR0 & and3 -5, *+AR0(5), AR0 & and3 *+AR0(5), -5, AR0 & and3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & and_sti_QC: & and *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1(1) & and R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and *+AR0(1), R0 & sti R1, *+AR1(1) &|| and R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & and_sti_QC_enh: & and AR0, R1, R0 &|| sti R1, *+AR1(1) & and R2, R1, R0 &|| sti R1, *+AR1(1) & and R1, R0 &|| sti R1, *+AR1(1) & and R0 &|| sti R1, *+AR1(1) & and R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and AR0, R1, R0 & sti R1, *+AR1(1) &|| and R2, R1, R0 & sti R1, *+AR1(1) &|| and R1, R0 & sti R1, *+AR1(1) &|| and R0 & sti R1, *+AR1(1) &|| and R0, AR0, R0 & .endif & .ifdef TEST_C3X & and3_sti_QC: & and3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & and3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| and3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & and3_sti_QC_enh: & and3 AR0, R1, R0 &|| sti R1, *+AR1(1) & and3 R2, R1, R0 &|| sti R1, *+AR1(1) & and3 R1, R0 &|| sti R1, *+AR1(1) & and3 R0 &|| sti R1, *+AR1(1) & and3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 AR0, R1, R0 & sti R1, *+AR1(1) &|| and3 R2, R1, R0 & sti R1, *+AR1(1) &|| and3 R1, R0 & sti R1, *+AR1(1) &|| and3 R0 & sti R1, *+AR1(1) &|| and3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & andn_AU: & andn AR1, AR0 & andn AR0 & andn @start, AR0 & andn *+AR0(5), AR0 & andn 5, AR0 & .endif
.ifdef TEST_C3X & andn_T: & andn AR2, AR1, AR0 & andn AR1, AR0 & andn AR1, *+AR0(1), AR0 & andn *+AR0(1), AR1, AR0 & andn *+AR0(1), AR0 & andn *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & andn_T_sc: & andn -5, AR1, AR0 & andn -5, AR0 & andn *+AR0(5), AR1, AR0 & andn *+AR0(5), AR0 & andn -5, *+AR0(5), AR0 & andn *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & andn3_T: & andn3 AR2, AR1, AR0 & andn3 AR1, AR0 & andn3 AR1, *+AR0(1), AR0 & andn3 *+AR0(1), AR1, AR0 & andn3 *+AR0(1), AR0 & andn3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & andn3_T_sc: & andn3 -5, AR1, AR0 & andn3 -5, AR0 & andn3 *+AR0(5), AR1, AR0 & andn3 *+AR0(5), AR0 & andn3 -5, *+AR0(5), AR0 & andn3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & ash_A: & ash AR1, AR0 & ash AR0 & ash @start, AR0 & ash *+AR0(5), AR0 & ash -5, AR0 & .endif
.ifdef TEST_C3X & ash_T: & ash AR2, AR1, AR0 & ash AR1, AR0 & ash AR1, *+AR0(1), AR0 & ash *+AR0(1), AR1, AR0 & ash *+AR0(1), AR0 & ash *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & ash_T_sc: & ash -5, AR1, AR0 & ash -5, AR0 & ash *+AR0(5), AR1, AR0 & ash *+AR0(5), AR0 & ash -5, *+AR0(5), AR0 & ash *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & ash3_T: & ash3 AR2, AR1, AR0 & ash3 AR1, AR0 & ash3 AR1, *+AR0(1), AR0 & ash3 *+AR0(1), AR1, AR0 & ash3 *+AR0(1), AR0 & ash3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & ash3_T_sc: & ash3 -5, AR1, AR0 & ash3 -5, AR0 & ash3 *+AR0(5), AR1, AR0 & ash3 *+AR0(5), AR0 & ash3 -5, *+AR0(5), AR0 & ash3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & ash_sti_Q: & ash R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ash_sti_Q_enh: & ash R0, R0, R0 &|| sti R1, *+AR1(1) & ash R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, R0, R0 & sti R1, *+AR1(1) &|| ash R0, R0 & .endif & .ifdef TEST_C3X & ash3_sti_Q: & ash3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ash3_sti_Q_enh: & ash3 R0, R0, R0 &|| sti R1, *+AR1(1) & ash3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, R0, R0 & sti R1, *+AR1(1) &|| ash3 R0, R0 & .endif
.ifdef TEST_C3X & bC_J: & bC R0 & bC start & b_J: & b R0 & b start & .endif
.ifdef TEST_C3X & bCd_J: & bCd R0 & bCd start & bd_J: & bd R0 & bd start & .endif
.ifdef TEST_C3X
br_I: br start
brd_I: brd start
call_I: call start
call_JS: callc R0
callc start
.endif
.ifdef TEST_C3X & cmpf_B: & cmpf R1, R0 & cmpf R0 & cmpf @start, R0 & cmpf *+AR0(5), R0 & cmpf 3.5, R0 & .endif
.ifdef TEST_C3X & cmpf_S2: & cmpf R2, R1 & cmpf R1, *+AR0(1) & cmpf *+AR0(1), R1 & cmpf *+AR0(1), *+AR1(1) & .endif & .ifdef TEST_C4X & cmpf_S2_c4x: & cmpf *+AR0(5), R1 & cmpf *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & cmpf3_S2: & cmpf3 R2, R1 & cmpf3 R1, *+AR0(1) & cmpf3 *+AR0(1), R1 & cmpf3 *+AR0(1), *+AR1(1) & .endif & .ifdef TEST_C4X & cmpf3_S2_c4x: & cmpf3 *+AR0(5), R1 & cmpf3 *+AR0(5), *+AR1(5) & .endif
.ifdef TEST_C3X & cmpi_A: & cmpi AR1, AR0 & cmpi AR0 & cmpi @start, AR0 & cmpi *+AR0(5), AR0 & cmpi -5, AR0 & .endif
.ifdef TEST_C3X & cmpi_T2: & cmpi AR2, AR1 & cmpi AR1, *+AR0(1) & cmpi *+AR0(1), AR1 & cmpi *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & cmpi_T2_c4x: & cmpi -5, AR1 & cmpi *+AR0(5), AR1 & cmpi -5, *+AR0(5) & cmpi *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & cmpi3_T2: & cmpi3 AR2, AR1 & cmpi3 AR1, *+AR0(1) & cmpi3 *+AR0(1), AR1 & cmpi3 *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & cmpi3_T2_c4x: & cmpi3 -5, AR1 & cmpi3 *+AR0(5), AR1 & cmpi3 -5, *+AR0(5) & cmpi3 *+AR0(5), *+AR1(5) & .endif
.ifdef TEST_C3X & dbC_D: & dbC AR0, R0 & dbC AR0, start & db_D: & db AR0, R0 & db AR0, start & .endif
.ifdef TEST_C3X & dbCd_D: & dbCd AR0, R0 & dbCd AR0, start & dbd_D: & dbd AR0, R0 & dbd AR0, start & .endif
.ifdef TEST_C3X & fix_AF: & fix R1, R0 & fix R0 & fix @start, AR0 & fix *+AR0(5), AR0 & fix 3.5, AR0 & .endif
.ifdef TEST_C3X & fix_sti_P: & fix *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix *+AR0(1), R0 & .endif & .ifdef TEST_ENH & fix_sti_P_enh: & fix R0, R0 &|| sti R1, *+AR1(1) & fix R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix R0, R0 & sti R1, *+AR1(1) &|| fix R0 & .endif
.ifdef TEST_C3X & float_BI: & float AR1, R0 & float R0 & float @start, R0 & float *+AR0(5), R0 & float -5, R0 & .endif
.ifdef TEST_C3X & float_stf_P: & float *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float *+AR0(1), R0 & .endif & .ifdef TEST_ENH & float_stf_P_enh: & float R0, R0 &|| stf R1, *+AR1(1) & float R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float R0, R0 & stf R1, *+AR1(1) &|| float R0 & .endif
.ifdef TEST_C3X
iack_Z: iack @start
iack *+AR0(1)
idle_Z: idle
.endif
.ifdef TEST_IDLE2
idle2_Z: idle2
.endif
.ifdef TEST_C3X & lde_B: & lde R1, R0 & lde R0 & lde @start, R0 & lde *+AR0(5), R0 & lde 3.5, R0 & .endif
.ifdef TEST_C3X & ldf_B: & ldf R1, R0 & ldf R0 & ldf @start, R0 & ldf *+AR0(5), R0 & ldf 3.5, R0 & .endif
.ifdef TEST_C3X & ldf_LL: & ldf *+AR0(1), R0 &|| ldf *+AR1(1), R1 & ldf2 *+AR0(1), R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldf_LL_enh: & ldf R0, R0 &|| ldf *+AR1(1), R1 & ldf R0 &|| ldf *+AR1(1), R1 & ldf2 R0, R0 &|| ldf1 *+AR1(1), R1 & ldf2 R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 R0, R0 & ldf1 *+AR1(1), R1 &|| ldf2 R0 & .endif
.ifdef TEST_C3X & ldf_stf_P: & ldf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldf_stf_P_enh: & ldf R0, R0 &|| stf R1, *+AR1(1) & ldf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf R0, R0 & stf R1, *+AR1(1) &|| ldf R0 & .endif
.ifdef TEST_C3X & ldfC_BB: & ldfC R1, R0 & ldfC R0 & ldfC @start, R0 & ldfC *+AR0(5), R0 & ldfC 3.5, R0 & .endif
.ifdef TEST_C3X & ldfi_B6: & ldfi @start, R0 & ldfi *+AR0(5), R0 & .endif
.ifdef TEST_C3X & ldi_A: & ldi AR1, AR0 & ldi AR0 & ldi @start, AR0 & ldi *+AR0(5), AR0 & ldi -5, AR0 & .endif
.ifdef TEST_C3X & ldi_LL: & ldi *+AR0(1), R0 &|| ldi *+AR1(1), R1 & ldi2 *+AR0(1), R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldi_LL_enh: & ldi R0, R0 &|| ldi *+AR1(1), R1 & ldi R0 &|| ldi *+AR1(1), R1 & ldi2 R0, R0 &|| ldi1 *+AR1(1), R1 & ldi2 R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 R0, R0 & ldi1 *+AR1(1), R1 &|| ldi2 R0 & .endif
.ifdef TEST_C3X & ldi_sti_P: & ldi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldi_sti_P_enh: & ldi R0, R0 &|| sti R1, *+AR1(1) & ldi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi R0, R0 & sti R1, *+AR1(1) &|| ldi R0 & .endif
.ifdef TEST_C3X & ldiC_AB: & ldiC AR1, AR0 & ldiC AR0 & ldiC @start, AR0 & ldiC *+AR0(5), AR0 & ldiC -5, AR0 & .endif
.ifdef TEST_C3X & ldii_A6: & ldii @start, AR0 & ldii *+AR0(5), AR0 & .endif
.ifdef TEST_C3X
ldp_Z: ldp start
.endif
.ifdef TEST_C3X & ldm_B: & ldm R1, R0 & ldm R0 & ldm @start, R0 & ldm *+AR0(5), R0 & ldm 3.5, R0 & .endif
.ifdef TEST_LPWR
lopower_Z: lopower
.endif
.ifdef TEST_C3X & lsh_A: & lsh AR1, AR0 & lsh AR0 & lsh @start, AR0 & lsh *+AR0(5), AR0 & lsh -5, AR0 & .endif
.ifdef TEST_C3X & lsh_T: & lsh AR2, AR1, AR0 & lsh AR1, AR0 & lsh AR1, *+AR0(1), AR0 & lsh *+AR0(1), AR1, AR0 & lsh *+AR0(1), AR0 & lsh *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & lsh_T_sc: & lsh -5, AR1, AR0 & lsh -5, AR0 & lsh *+AR0(5), AR1, AR0 & lsh *+AR0(5), AR0 & lsh -5, *+AR0(5), AR0 & lsh *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & lsh3_T: & lsh3 AR2, AR1, AR0 & lsh3 AR1, AR0 & lsh3 AR1, *+AR0(1), AR0 & lsh3 *+AR0(1), AR1, AR0 & lsh3 *+AR0(1), AR0 & lsh3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & lsh3_T_sc: & lsh3 -5, AR1, AR0 & lsh3 -5, AR0 & lsh3 *+AR0(5), AR1, AR0 & lsh3 *+AR0(5), AR0 & lsh3 -5, *+AR0(5), AR0 & lsh3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & lsh_sti_Q: & lsh R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & lsh_sti_Q_enh: & lsh R0, R0, R0 &|| sti R1, *+AR1(1) & lsh R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, R0, R0 & sti R1, *+AR1(1) &|| lsh R0, R0 & .endif & .ifdef TEST_C3X & lsh3_sti_Q: & lsh3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & lsh3_sti_Q_enh: & lsh3 R0, R0, R0 &|| sti R1, *+AR1(1) & lsh3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, R0, R0 & sti R1, *+AR1(1) &|| lsh3 R0, R0 & .endif
.ifdef TEST_LPWR
maxspeed_Z: maxspeed
.endif
.ifdef TEST_C3X & mpyf_B: & mpyf R1, R0 & mpyf R0 & mpyf @start, R0 & mpyf *+AR0(5), R0 & mpyf 3.5, R0 & .endif
.ifdef TEST_C3X & mpyf_SC: & mpyf R2, R1, R0 & mpyf R1, R0 & mpyf R1, *+AR0(1), R0 & mpyf *+AR0(1), R1, R0 & mpyf *+AR0(1), R0 & mpyf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & mpyf_SC_c4x: & mpyf *+AR0(5), R1, R0 & mpyf *+AR0(5), R0 & mpyf R1, *+AR0(5), R0 & mpyf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & mpyf3_SC: & mpyf3 R2, R1, R0 & mpyf3 R1, R0 & mpyf3 R1, *+AR0(1), R0 & mpyf3 *+AR0(1), R1, R0 & mpyf3 *+AR0(1), R0 & mpyf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & mpyf3_SC_c4x: & mpyf3 *+AR0(5), R1, R0 & mpyf3 *+AR0(5), R0 & mpyf3 R1, *+AR0(5), R0 & mpyf3 *+AR0(5), *+AR1(5), R0 & .endif
.ifdef TEST_C3X & mpyf_addf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_addf_M_enh: & mpyf R0, R0, R0 &|| addf R2, R2, R2 & mpyf R0, R0 &|| addf R2, R2, R2 & mpyf R0 &|| addf R2, R2, R2 & mpyf R0, R0 &|| addf R2, R2 & mpyf R0 &|| addf R2, R2 & mpyf R0 &|| addf R2 & mpyf AR0, AR0, R0 &|| addf R2, R2, R2 & mpyf AR0, R0, R0 &|| addf R0, AR0, R2 & mpyf R0, AR0, R0 &|| addf R0, AR0, R2 & mpyf R2, R1, R0 &|| addf AR0, AR1, R2 & mpyf AR0, R1, R0 &|| addf AR0, R3, R2 & mpyf R0, AR0, R0 &|| addf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_addf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_addf_M_enh: & mpyf3 R0, R0, R0 &|| addf R2, R2, R2 & mpyf3 R0, R0 &|| addf R2, R2, R2 & mpyf3 R0 &|| addf R2, R2, R2 & mpyf3 R0, R0 &|| addf R2, R2 & mpyf3 R0 &|| addf R2, R2 & mpyf3 R0 &|| addf R2 & mpyf3 AR0, AR0, R0 &|| addf R2, R2, R2 & mpyf3 AR0, R0, R0 &|| addf R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| addf R0, AR0, R2 & mpyf3 R2, R1, R0 &|| addf AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| addf AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| addf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf_addf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_addf3_M_enh: & mpyf R0, R0, R0 &|| addf3 R2, R2, R2 & mpyf R0, R0 &|| addf3 R2, R2, R2 & mpyf R0 &|| addf3 R2, R2, R2 & mpyf R0, R0 &|| addf3 R2, R2 & mpyf R0 &|| addf3 R2, R2 & mpyf R0 &|| addf3 R2 & mpyf AR0, AR0, R0 &|| addf3 R2, R2, R2 & mpyf AR0, R0, R0 &|| addf3 R0, AR0, R2 & mpyf R0, AR0, R0 &|| addf3 R0, AR0, R2 & mpyf R2, R1, R0 &|| addf3 AR0, AR1, R2 & mpyf AR0, R1, R0 &|| addf3 AR0, R3, R2 & mpyf R0, AR0, R0 &|| addf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_addf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_addf3_M_enh: & mpyf3 R0, R0, R0 &|| addf3 R2, R2, R2 & mpyf3 R0, R0 &|| addf3 R2, R2, R2 & mpyf3 R0 &|| addf3 R2, R2, R2 & mpyf3 R0, R0 &|| addf3 R2, R2 & mpyf3 R0 &|| addf3 R2, R2 & mpyf3 R0 &|| addf3 R2 & mpyf3 AR0, AR0, R0 &|| addf3 R2, R2, R2 & mpyf3 AR0, R0, R0 &|| addf3 R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| addf3 R0, AR0, R2 & mpyf3 R2, R1, R0 &|| addf3 AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| addf3 AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| addf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & addf_mpyf_M: & addf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_mpyf_M_enh: & addf R2, R2, R2 &|| mpyf R0, R0, R0 & addf R2, R2, R2 &|| mpyf R0, R0 & addf R2, R2, R2 &|| mpyf R0 & addf R2, R2 &|| mpyf R0, R0 & addf R2, R2 &|| mpyf R0 & addf R2 &|| mpyf R0 & addf R2, R2, R2 &|| mpyf AR0, AR0, R0 & addf R0, AR0, R2 &|| mpyf AR0, R0, R0 & addf R0, AR0, R2 &|| mpyf R0, AR0, R0 & addf AR0, AR1, R2 &|| mpyf R2, R1, R0 & addf AR0, R3, R2 &|| mpyf AR0, R1, R0 & addf AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_mpyf_M: & addf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_mpyf_M_enh: & addf3 R2, R2, R2 &|| mpyf R0, R0, R0 & addf3 R2, R2, R2 &|| mpyf R0, R0 & addf3 R2, R2, R2 &|| mpyf R0 & addf3 R2, R2 &|| mpyf R0, R0 & addf3 R2, R2 &|| mpyf R0 & addf3 R2 &|| mpyf R0 & addf3 R2, R2, R2 &|| mpyf AR0, AR0, R0 & addf3 R0, AR0, R2 &|| mpyf AR0, R0, R0 & addf3 R0, AR0, R2 &|| mpyf R0, AR0, R0 & addf3 AR0, AR1, R2 &|| mpyf R2, R1, R0 & addf3 AR0, R3, R2 &|| mpyf AR0, R1, R0 & addf3 AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf_mpyf3_M: & addf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_mpyf3_M_enh: & addf R2, R2, R2 &|| mpyf3 R0, R0, R0 & addf R2, R2, R2 &|| mpyf3 R0, R0 & addf R2, R2, R2 &|| mpyf3 R0 & addf R2, R2 &|| mpyf3 R0, R0 & addf R2, R2 &|| mpyf3 R0 & addf R2 &|| mpyf3 R0 & addf R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & addf R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & addf R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & addf AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & addf AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & addf AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_mpyf3_M: & addf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_mpyf3_M_enh: & addf3 R2, R2, R2 &|| mpyf3 R0, R0, R0 & addf3 R2, R2, R2 &|| mpyf3 R0, R0 & addf3 R2, R2, R2 &|| mpyf3 R0 & addf3 R2, R2 &|| mpyf3 R0, R0 & addf3 R2, R2 &|| mpyf3 R0 & addf3 R2 &|| mpyf3 R0 & addf3 R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & addf3 R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & addf3 R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & addf3 AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & addf3 AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & addf3 AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyf_stf_QC: & mpyf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyf_stf_QC_enh: & mpyf AR0, R1, R0 &|| stf R1, *+AR1(1) & mpyf R2, R1, R0 &|| stf R1, *+AR1(1) & mpyf R1, R0 &|| stf R1, *+AR1(1) & mpyf R0 &|| stf R1, *+AR1(1) & mpyf R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf AR0, R1, R0 & stf R1, *+AR1(1) &|| mpyf R2, R1, R0 & stf R1, *+AR1(1) &|| mpyf R1, R0 & stf R1, *+AR1(1) &|| mpyf R0 & stf R1, *+AR1(1) &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & mpyf3_stf_QC: & mpyf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyf3_stf_QC_enh: & mpyf3 AR0, R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R2, R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R0 &|| stf R1, *+AR1(1) & mpyf3 R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 AR0, R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R2, R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R0 & stf R1, *+AR1(1) &|| mpyf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyf_subf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_subf_M_enh: & mpyf R0, R0, R0 &|| subf R2, R2, R2 & mpyf R0, R0 &|| subf R2, R2, R2 & mpyf R0 &|| subf R2, R2, R2 & mpyf R0, R0 &|| subf R2, R2 & mpyf R0 &|| subf R2, R2 & mpyf R0 &|| subf R2 & mpyf AR0, AR0, R0 &|| subf R2, R2, R2 & mpyf AR0, R0, R0 &|| subf R0, AR0, R2 & mpyf R0, AR0, R0 &|| subf R0, AR0, R2 & mpyf R2, R1, R0 &|| subf AR0, AR1, R2 & mpyf AR0, R1, R0 &|| subf AR0, R3, R2 & mpyf R0, AR0, R0 &|| subf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_subf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_subf_M_enh: & mpyf3 R0, R0, R0 &|| subf R2, R2, R2 & mpyf3 R0, R0 &|| subf R2, R2, R2 & mpyf3 R0 &|| subf R2, R2, R2 & mpyf3 R0, R0 &|| subf R2, R2 & mpyf3 R0 &|| subf R2, R2 & mpyf3 R0 &|| subf R2 & mpyf3 AR0, AR0, R0 &|| subf R2, R2, R2 & mpyf3 AR0, R0, R0 &|| subf R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| subf R0, AR0, R2 & mpyf3 R2, R1, R0 &|| subf AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| subf AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| subf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf_subf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_subf3_M_enh: & mpyf R0, R0, R0 &|| subf3 R2, R2, R2 & mpyf R0, R0 &|| subf3 R2, R2, R2 & mpyf R0 &|| subf3 R2, R2, R2 & mpyf R0, R0 &|| subf3 R2, R2 & mpyf R0 &|| subf3 R2, R2 & mpyf R0 &|| subf3 R2 & mpyf AR0, AR0, R0 &|| subf3 R2, R2, R2 & mpyf AR0, R0, R0 &|| subf3 R0, AR0, R2 & mpyf R0, AR0, R0 &|| subf3 R0, AR0, R2 & mpyf R2, R1, R0 &|| subf3 AR0, AR1, R2 & mpyf AR0, R1, R0 &|| subf3 AR0, R3, R2 & mpyf R0, AR0, R0 &|| subf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_subf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_subf3_M_enh: & mpyf3 R0, R0, R0 &|| subf3 R2, R2, R2 & mpyf3 R0, R0 &|| subf3 R2, R2, R2 & mpyf3 R0 &|| subf3 R2, R2, R2 & mpyf3 R0, R0 &|| subf3 R2, R2 & mpyf3 R0 &|| subf3 R2, R2 & mpyf3 R0 &|| subf3 R2 & mpyf3 AR0, AR0, R0 &|| subf3 R2, R2, R2 & mpyf3 AR0, R0, R0 &|| subf3 R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| subf3 R0, AR0, R2 & mpyf3 R2, R1, R0 &|| subf3 AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| subf3 AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| subf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & subf_mpyf_M: & subf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_mpyf_M_enh: & subf R2, R2, R2 &|| mpyf R0, R0, R0 & subf R2, R2, R2 &|| mpyf R0, R0 & subf R2, R2, R2 &|| mpyf R0 & subf R2, R2 &|| mpyf R0, R0 & subf R2, R2 &|| mpyf R0 & subf R2 &|| mpyf R0 & subf R2, R2, R2 &|| mpyf AR0, AR0, R0 & subf R0, AR0, R2 &|| mpyf AR0, R0, R0 & subf R0, AR0, R2 &|| mpyf R0, AR0, R0 & subf AR0, AR1, R2 &|| mpyf R2, R1, R0 & subf AR0, R3, R2 &|| mpyf AR0, R1, R0 & subf AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf3_mpyf_M: & subf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_mpyf_M_enh: & subf3 R2, R2, R2 &|| mpyf R0, R0, R0 & subf3 R2, R2, R2 &|| mpyf R0, R0 & subf3 R2, R2, R2 &|| mpyf R0 & subf3 R2, R2 &|| mpyf R0, R0 & subf3 R2, R2 &|| mpyf R0 & subf3 R2 &|| mpyf R0 & subf3 R2, R2, R2 &|| mpyf AR0, AR0, R0 & subf3 R0, AR0, R2 &|| mpyf AR0, R0, R0 & subf3 R0, AR0, R2 &|| mpyf R0, AR0, R0 & subf3 AR0, AR1, R2 &|| mpyf R2, R1, R0 & subf3 AR0, R3, R2 &|| mpyf AR0, R1, R0 & subf3 AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf_mpyf3_M: & subf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_mpyf3_M_enh: & subf R2, R2, R2 &|| mpyf3 R0, R0, R0 & subf R2, R2, R2 &|| mpyf3 R0, R0 & subf R2, R2, R2 &|| mpyf3 R0 & subf R2, R2 &|| mpyf3 R0, R0 & subf R2, R2 &|| mpyf3 R0 & subf R2 &|| mpyf3 R0 & subf R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & subf R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & subf R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & subf AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & subf AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & subf AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf3_mpyf3_M: & subf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_mpyf3_M_enh: & subf3 R2, R2, R2 &|| mpyf3 R0, R0, R0 & subf3 R2, R2, R2 &|| mpyf3 R0, R0 & subf3 R2, R2, R2 &|| mpyf3 R0 & subf3 R2, R2 &|| mpyf3 R0, R0 & subf3 R2, R2 &|| mpyf3 R0 & subf3 R2 &|| mpyf3 R0 & subf3 R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & subf3 R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & subf3 R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & subf3 AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & subf3 AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & subf3 AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyi_A: & mpyi AR1, AR0 & mpyi AR0 & mpyi @start, AR0 & mpyi *+AR0(5), AR0 & mpyi -5, AR0 & .endif
.ifdef TEST_C3X & mpyi_TC: & mpyi AR2, AR1, AR0 & mpyi AR1, AR0 & mpyi AR1, *+AR0(1), AR0 & mpyi *+AR0(1), AR1, AR0 & mpyi *+AR0(1), AR0 & mpyi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyi_TC_c4x: & mpyi -5, AR1, AR0 & mpyi -5, AR0 & mpyi AR1, -5, AR0 & mpyi *+AR0(5), AR1, AR0 & mpyi *+AR0(5), AR0 & mpyi AR1, *+AR0(5), AR0 & mpyi -5, *+AR0(5), AR0 & mpyi *+AR0(5), -5, AR0 & mpyi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & mpyi3_TC: & mpyi3 AR2, AR1, AR0 & mpyi3 AR1, AR0 & mpyi3 AR1, *+AR0(1), AR0 & mpyi3 *+AR0(1), AR1, AR0 & mpyi3 *+AR0(1), AR0 & mpyi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyi3_TC_c4x: & mpyi3 -5, AR1, AR0 & mpyi3 -5, AR0 & mpyi3 AR1, -5, AR0 & mpyi3 *+AR0(5), AR1, AR0 & mpyi3 *+AR0(5), AR0 & mpyi3 AR1, *+AR0(5), AR0 & mpyi3 -5, *+AR0(5), AR0 & mpyi3 *+AR0(5), -5, AR0 & mpyi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & mpyi_addi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_addi_M_enh: & mpyi R0, R0, R0 &|| addi R2, R2, R2 & mpyi R0, R0 &|| addi R2, R2, R2 & mpyi R0 &|| addi R2, R2, R2 & mpyi R0, R0 &|| addi R2, R2 & mpyi R0 &|| addi R2, R2 & mpyi R0 &|| addi R2 & mpyi AR0, AR0, R0 &|| addi R2, R2, R2 & mpyi AR0, R0, R0 &|| addi R0, AR0, R2 & mpyi R0, AR0, R0 &|| addi R0, AR0, R2 & mpyi R2, R1, R0 &|| addi AR0, AR1, R2 & mpyi AR0, R1, R0 &|| addi AR0, R3, R2 & mpyi R0, AR0, R0 &|| addi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_addi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_addi_M_enh: & mpyi3 R0, R0, R0 &|| addi R2, R2, R2 & mpyi3 R0, R0 &|| addi R2, R2, R2 & mpyi3 R0 &|| addi R2, R2, R2 & mpyi3 R0, R0 &|| addi R2, R2 & mpyi3 R0 &|| addi R2, R2 & mpyi3 R0 &|| addi R2 & mpyi3 AR0, AR0, R0 &|| addi R2, R2, R2 & mpyi3 AR0, R0, R0 &|| addi R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| addi R0, AR0, R2 & mpyi3 R2, R1, R0 &|| addi AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| addi AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| addi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi_addi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_addi3_M_enh: & mpyi R0, R0, R0 &|| addi3 R2, R2, R2 & mpyi R0, R0 &|| addi3 R2, R2, R2 & mpyi R0 &|| addi3 R2, R2, R2 & mpyi R0, R0 &|| addi3 R2, R2 & mpyi R0 &|| addi3 R2, R2 & mpyi R0 &|| addi3 R2 & mpyi AR0, AR0, R0 &|| addi3 R2, R2, R2 & mpyi AR0, R0, R0 &|| addi3 R0, AR0, R2 & mpyi R0, AR0, R0 &|| addi3 R0, AR0, R2 & mpyi R2, R1, R0 &|| addi3 AR0, AR1, R2 & mpyi AR0, R1, R0 &|| addi3 AR0, R3, R2 & mpyi R0, AR0, R0 &|| addi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_addi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_addi3_M_enh: & mpyi3 R0, R0, R0 &|| addi3 R2, R2, R2 & mpyi3 R0, R0 &|| addi3 R2, R2, R2 & mpyi3 R0 &|| addi3 R2, R2, R2 & mpyi3 R0, R0 &|| addi3 R2, R2 & mpyi3 R0 &|| addi3 R2, R2 & mpyi3 R0 &|| addi3 R2 & mpyi3 AR0, AR0, R0 &|| addi3 R2, R2, R2 & mpyi3 AR0, R0, R0 &|| addi3 R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| addi3 R0, AR0, R2 & mpyi3 R2, R1, R0 &|| addi3 AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| addi3 AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| addi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & addi_mpyi_M: & addi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_mpyi_M_enh: & addi R2, R2, R2 &|| mpyi R0, R0, R0 & addi R2, R2, R2 &|| mpyi R0, R0 & addi R2, R2, R2 &|| mpyi R0 & addi R2, R2 &|| mpyi R0, R0 & addi R2, R2 &|| mpyi R0 & addi R2 &|| mpyi R0 & addi R2, R2, R2 &|| mpyi AR0, AR0, R0 & addi R0, AR0, R2 &|| mpyi AR0, R0, R0 & addi R0, AR0, R2 &|| mpyi R0, AR0, R0 & addi AR0, AR1, R2 &|| mpyi R2, R1, R0 & addi AR0, R3, R2 &|| mpyi AR0, R1, R0 & addi AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_mpyi_M: & addi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_mpyi_M_enh: & addi3 R2, R2, R2 &|| mpyi R0, R0, R0 & addi3 R2, R2, R2 &|| mpyi R0, R0 & addi3 R2, R2, R2 &|| mpyi R0 & addi3 R2, R2 &|| mpyi R0, R0 & addi3 R2, R2 &|| mpyi R0 & addi3 R2 &|| mpyi R0 & addi3 R2, R2, R2 &|| mpyi AR0, AR0, R0 & addi3 R0, AR0, R2 &|| mpyi AR0, R0, R0 & addi3 R0, AR0, R2 &|| mpyi R0, AR0, R0 & addi3 AR0, AR1, R2 &|| mpyi R2, R1, R0 & addi3 AR0, R3, R2 &|| mpyi AR0, R1, R0 & addi3 AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi_mpyi3_M: & addi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_mpyi3_M_enh: & addi R2, R2, R2 &|| mpyi3 R0, R0, R0 & addi R2, R2, R2 &|| mpyi3 R0, R0 & addi R2, R2, R2 &|| mpyi3 R0 & addi R2, R2 &|| mpyi3 R0, R0 & addi R2, R2 &|| mpyi3 R0 & addi R2 &|| mpyi3 R0 & addi R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & addi R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & addi R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & addi AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & addi AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & addi AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_mpyi3_M: & addi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_mpyi3_M_enh: & addi3 R2, R2, R2 &|| mpyi3 R0, R0, R0 & addi3 R2, R2, R2 &|| mpyi3 R0, R0 & addi3 R2, R2, R2 &|| mpyi3 R0 & addi3 R2, R2 &|| mpyi3 R0, R0 & addi3 R2, R2 &|| mpyi3 R0 & addi3 R2 &|| mpyi3 R0 & addi3 R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & addi3 R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & addi3 R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & addi3 AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & addi3 AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & addi3 AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyi_sti_QC: & mpyi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyi_sti_QC_enh: & mpyi AR0, R1, R0 &|| sti R1, *+AR1(1) & mpyi R2, R1, R0 &|| sti R1, *+AR1(1) & mpyi R1, R0 &|| sti R1, *+AR1(1) & mpyi R0 &|| sti R1, *+AR1(1) & mpyi R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi AR0, R1, R0 & sti R1, *+AR1(1) &|| mpyi R2, R1, R0 & sti R1, *+AR1(1) &|| mpyi R1, R0 & sti R1, *+AR1(1) &|| mpyi R0 & sti R1, *+AR1(1) &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & mpyi3_sti_QC: & mpyi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyi3_sti_QC_enh: & mpyi3 AR0, R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R2, R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R0 &|| sti R1, *+AR1(1) & mpyi3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 AR0, R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R2, R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R0 & sti R1, *+AR1(1) &|| mpyi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & mpyi_subi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_subi_M_enh: & mpyi R0, R0, R0 &|| subi R2, R2, R2 & mpyi R0, R0 &|| subi R2, R2, R2 & mpyi R0 &|| subi R2, R2, R2 & mpyi R0, R0 &|| subi R2, R2 & mpyi R0 &|| subi R2, R2 & mpyi R0 &|| subi R2 & mpyi AR0, AR0, R0 &|| subi R2, R2, R2 & mpyi AR0, R0, R0 &|| subi R0, AR0, R2 & mpyi R0, AR0, R0 &|| subi R0, AR0, R2 & mpyi R2, R1, R0 &|| subi AR0, AR1, R2 & mpyi AR0, R1, R0 &|| subi AR0, R3, R2 & mpyi R0, AR0, R0 &|| subi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_subi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_subi_M_enh: & mpyi3 R0, R0, R0 &|| subi R2, R2, R2 & mpyi3 R0, R0 &|| subi R2, R2, R2 & mpyi3 R0 &|| subi R2, R2, R2 & mpyi3 R0, R0 &|| subi R2, R2 & mpyi3 R0 &|| subi R2, R2 & mpyi3 R0 &|| subi R2 & mpyi3 AR0, AR0, R0 &|| subi R2, R2, R2 & mpyi3 AR0, R0, R0 &|| subi R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| subi R0, AR0, R2 & mpyi3 R2, R1, R0 &|| subi AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| subi AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| subi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi_subi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_subi3_M_enh: & mpyi R0, R0, R0 &|| subi3 R2, R2, R2 & mpyi R0, R0 &|| subi3 R2, R2, R2 & mpyi R0 &|| subi3 R2, R2, R2 & mpyi R0, R0 &|| subi3 R2, R2 & mpyi R0 &|| subi3 R2, R2 & mpyi R0 &|| subi3 R2 & mpyi AR0, AR0, R0 &|| subi3 R2, R2, R2 & mpyi AR0, R0, R0 &|| subi3 R0, AR0, R2 & mpyi R0, AR0, R0 &|| subi3 R0, AR0, R2 & mpyi R2, R1, R0 &|| subi3 AR0, AR1, R2 & mpyi AR0, R1, R0 &|| subi3 AR0, R3, R2 & mpyi R0, AR0, R0 &|| subi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_subi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_subi3_M_enh: & mpyi3 R0, R0, R0 &|| subi3 R2, R2, R2 & mpyi3 R0, R0 &|| subi3 R2, R2, R2 & mpyi3 R0 &|| subi3 R2, R2, R2 & mpyi3 R0, R0 &|| subi3 R2, R2 & mpyi3 R0 &|| subi3 R2, R2 & mpyi3 R0 &|| subi3 R2 & mpyi3 AR0, AR0, R0 &|| subi3 R2, R2, R2 & mpyi3 AR0, R0, R0 &|| subi3 R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| subi3 R0, AR0, R2 & mpyi3 R2, R1, R0 &|| subi3 AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| subi3 AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| subi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & subi_mpyi_M: & subi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_mpyi_M_enh: & subi R2, R2, R2 &|| mpyi R0, R0, R0 & subi R2, R2, R2 &|| mpyi R0, R0 & subi R2, R2, R2 &|| mpyi R0 & subi R2, R2 &|| mpyi R0, R0 & subi R2, R2 &|| mpyi R0 & subi R2 &|| mpyi R0 & subi R2, R2, R2 &|| mpyi AR0, AR0, R0 & subi R0, AR0, R2 &|| mpyi AR0, R0, R0 & subi R0, AR0, R2 &|| mpyi R0, AR0, R0 & subi AR0, AR1, R2 &|| mpyi R2, R1, R0 & subi AR0, R3, R2 &|| mpyi AR0, R1, R0 & subi AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi3_mpyi_M: & subi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_mpyi_M_enh: & subi3 R2, R2, R2 &|| mpyi R0, R0, R0 & subi3 R2, R2, R2 &|| mpyi R0, R0 & subi3 R2, R2, R2 &|| mpyi R0 & subi3 R2, R2 &|| mpyi R0, R0 & subi3 R2, R2 &|| mpyi R0 & subi3 R2 &|| mpyi R0 & subi3 R2, R2, R2 &|| mpyi AR0, AR0, R0 & subi3 R0, AR0, R2 &|| mpyi AR0, R0, R0 & subi3 R0, AR0, R2 &|| mpyi R0, AR0, R0 & subi3 AR0, AR1, R2 &|| mpyi R2, R1, R0 & subi3 AR0, R3, R2 &|| mpyi AR0, R1, R0 & subi3 AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi_mpyi3_M: & subi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_mpyi3_M_enh: & subi R2, R2, R2 &|| mpyi3 R0, R0, R0 & subi R2, R2, R2 &|| mpyi3 R0, R0 & subi R2, R2, R2 &|| mpyi3 R0 & subi R2, R2 &|| mpyi3 R0, R0 & subi R2, R2 &|| mpyi3 R0 & subi R2 &|| mpyi3 R0 & subi R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & subi R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & subi R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & subi AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & subi AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & subi AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi3_mpyi3_M: & subi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_mpyi3_M_enh: & subi3 R2, R2, R2 &|| mpyi3 R0, R0, R0 & subi3 R2, R2, R2 &|| mpyi3 R0, R0 & subi3 R2, R2, R2 &|| mpyi3 R0 & subi3 R2, R2 &|| mpyi3 R0, R0 & subi3 R2, R2 &|| mpyi3 R0 & subi3 R2 &|| mpyi3 R0 & subi3 R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & subi3 R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & subi3 R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & subi3 AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & subi3 AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & subi3 AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & negb_A: & negb AR1, AR0 & negb AR0 & negb @start, AR0 & negb *+AR0(5), AR0 & negb -5, AR0 & .endif
.ifdef TEST_C3X & negf_B: & negf R1, R0 & negf R0 & negf @start, R0 & negf *+AR0(5), R0 & negf 3.5, R0 & .endif
.ifdef TEST_C3X & negf_stf_P: & negf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & negf_stf_P_enh: & negf R0, R0 &|| stf R1, *+AR1(1) & negf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf R0, R0 & stf R1, *+AR1(1) &|| negf R0 & .endif
.ifdef TEST_C3X & negi_A: & negi AR1, AR0 & negi AR0 & negi @start, AR0 & negi *+AR0(5), AR0 & negi -5, AR0 & .endif
.ifdef TEST_C3X & negi_sti_P: & negi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & negi_sti_P_enh: & negi R0, R0 &|| sti R1, *+AR1(1) & negi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi R0, R0 & sti R1, *+AR1(1) &|| negi R0 & .endif
.ifdef TEST_C3X & nop_A2: & nop AR0 & nop *+AR0(5) & nop & .endif
.ifdef TEST_C3X & norm_B: & norm R1, R0 & norm R0 & norm @start, R0 & norm *+AR0(5), R0 & norm 3.5, R0 & .endif
.ifdef TEST_C3X & not_AU: & not AR1, AR0 & not AR0 & not @start, AR0 & not *+AR0(5), AR0 & not 5, AR0 & .endif
.ifdef TEST_C3X & not_sti_P: & not *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not *+AR0(1), R0 & .endif & .ifdef TEST_ENH & not_sti_P_enh: & not R0, R0 &|| sti R1, *+AR1(1) & not R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not R0, R0 & sti R1, *+AR1(1) &|| not R0 & .endif
.ifdef TEST_C3X & or_AU: & or AR1, AR0 & or AR0 & or @start, AR0 & or *+AR0(5), AR0 & or 5, AR0 & .endif
.ifdef TEST_C3X & or_TC: & or AR2, AR1, AR0 & or AR1, AR0 & or AR1, *+AR0(1), AR0 & or *+AR0(1), AR1, AR0 & or *+AR0(1), AR0 & or *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & or_TC_c4x: & or -5, AR1, AR0 & or -5, AR0 & or AR1, -5, AR0 & or *+AR0(5), AR1, AR0 & or *+AR0(5), AR0 & or AR1, *+AR0(5), AR0 & or -5, *+AR0(5), AR0 & or *+AR0(5), -5, AR0 & or *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & or3_TC: & or3 AR2, AR1, AR0 & or3 AR1, AR0 & or3 AR1, *+AR0(1), AR0 & or3 *+AR0(1), AR1, AR0 & or3 *+AR0(1), AR0 & or3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & or3_TC_c4x: & or3 -5, AR1, AR0 & or3 -5, AR0 & or3 AR1, -5, AR0 & or3 *+AR0(5), AR1, AR0 & or3 *+AR0(5), AR0 & or3 AR1, *+AR0(5), AR0 & or3 -5, *+AR0(5), AR0 & or3 *+AR0(5), -5, AR0 & or3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & or_sti_QC: & or *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or *+AR0(1), R0 &|| sti R1, *+AR1(1) & or R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or *+AR0(1), R0 & sti R1, *+AR1(1) &|| or R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & or_sti_QC_enh: & or AR0, R1, R0 &|| sti R1, *+AR1(1) & or R2, R1, R0 &|| sti R1, *+AR1(1) & or R1, R0 &|| sti R1, *+AR1(1) & or R0 &|| sti R1, *+AR1(1) & or R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or AR0, R1, R0 & sti R1, *+AR1(1) &|| or R2, R1, R0 & sti R1, *+AR1(1) &|| or R1, R0 & sti R1, *+AR1(1) &|| or R0 & sti R1, *+AR1(1) &|| or R0, AR0, R0 & .endif & .ifdef TEST_C3X & or3_sti_QC: & or3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & or3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| or3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & or3_sti_QC_enh: & or3 AR0, R1, R0 &|| sti R1, *+AR1(1) & or3 R2, R1, R0 &|| sti R1, *+AR1(1) & or3 R1, R0 &|| sti R1, *+AR1(1) & or3 R0 &|| sti R1, *+AR1(1) & or3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 AR0, R1, R0 & sti R1, *+AR1(1) &|| or3 R2, R1, R0 & sti R1, *+AR1(1) &|| or3 R1, R0 & sti R1, *+AR1(1) &|| or3 R0 & sti R1, *+AR1(1) &|| or3 R0, AR0, R0 & .endif
.ifdef TEST_C3X & pop_R: & pop AR0 & .endif
.ifdef TEST_C3X & popf_RF: & popf F0 & .endif
.ifdef TEST_C3X & push_R: & push AR0 & .endif
.ifdef TEST_C3X & pushf_RF: & pushf F0 & .endif
.ifdef TEST_C3X
reti_Z: retiC
reti
rets_Z: retsC
rets
.endif
.ifdef TEST_C3X & rnd_B: & rnd R1, R0 & rnd R0 & rnd @start, R0 & rnd *+AR0(5), R0 & rnd 3.5, R0 & .endif
.ifdef TEST_C3X & rol_R: & rol AR0 & .endif
.ifdef TEST_C3X & rolc_R: & rolc AR0 & .endif
.ifdef TEST_C3X & ror_R: & ror AR0 & .endif
.ifdef TEST_C3X & rorc_R: & rorc AR0 & .endif
.ifdef TEST_C3X
rptb_I2: rptb start
.endif
.ifdef TEST_C3X & rpts_A3: & rpts AR1 & rpts @start & rpts *+AR0(5) & rpts 5 & .endif
.ifdef TEST_C3X
sigi_Z: sigi
.endif
.ifdef TEST_C3X & stf_B7: & stf R0, @start & stf R0, *+AR0(5) & .endif
.ifdef TEST_C3X & stf_LS: & stf R0, *+AR0(1) &|| stf R1, *+AR1(1) & stf2 R0, *+AR0(1) &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, *+AR0(1) & .endif & .ifdef TEST_ENH & stf_LS_enh: & stf R0, R0 &|| stf R1, *+AR1(1) & stf R0 &|| stf R1, *+AR1(1) & stf2 R0, R0 &|| stf1 R1, *+AR1(1) & stf2 R0 &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, R0 & stf1 R1, *+AR1(1) &|| stf2 R0 & .endif
.ifdef TEST_C3X & stfi_B7: & stfi R0, @start & stfi R0, *+AR0(5) & .endif
.ifdef TEST_C3X & sti_A7: & sti AR0, @start & sti AR0, *+AR0(5) & .endif
.ifdef TEST_C3X & sti_LS: & sti R0, *+AR0(1) &|| sti R1, *+AR1(1) & sti2 R0, *+AR0(1) &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, *+AR0(1) & .endif & .ifdef TEST_ENH & sti_LS_enh: & sti R0, R0 &|| sti R1, *+AR1(1) & sti R0 &|| sti R1, *+AR1(1) & sti2 R0, R0 &|| sti1 R1, *+AR1(1) & sti2 R0 &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, R0 & sti1 R1, *+AR1(1) &|| sti2 R0 & .endif
.ifdef TEST_C3X & stii_A7: & stii AR0, @start & stii AR0, *+AR0(5) & .endif
.ifdef TEST_C3X & subb_A: & subb AR1, AR0 & subb AR0 & subb @start, AR0 & subb *+AR0(5), AR0 & subb -5, AR0 & .endif
.ifdef TEST_C3X & subb_T: & subb AR2, AR1, AR0 & subb AR1, AR0 & subb AR1, *+AR0(1), AR0 & subb *+AR0(1), AR1, AR0 & subb *+AR0(1), AR0 & subb *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subb_T_sc: & subb -5, AR1, AR0 & subb -5, AR0 & subb *+AR0(5), AR1, AR0 & subb *+AR0(5), AR0 & subb -5, *+AR0(5), AR0 & subb *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & subb3_T: & subb3 AR2, AR1, AR0 & subb3 AR1, AR0 & subb3 AR1, *+AR0(1), AR0 & subb3 *+AR0(1), AR1, AR0 & subb3 *+AR0(1), AR0 & subb3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subb3_T_sc: & subb3 -5, AR1, AR0 & subb3 -5, AR0 & subb3 *+AR0(5), AR1, AR0 & subb3 *+AR0(5), AR0 & subb3 -5, *+AR0(5), AR0 & subb3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & subc_A: & subc AR1, AR0 & subc AR0 & subc @start, AR0 & subc *+AR0(5), AR0 & subc -5, AR0 & .endif
.ifdef TEST_C3X & subf_B: & subf R1, R0 & subf R0 & subf @start, R0 & subf *+AR0(5), R0 & subf 3.5, R0 & .endif
.ifdef TEST_C3X & subf_S: & subf R2, R1, R0 & subf R1, R0 & subf R1, *+AR0(1), R0 & subf *+AR0(1), R1, R0 & subf *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & subf_S_c4x: & subf *+AR0(5), R1, R0 & subf *+AR0(5), R0 & subf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & subf3_S: & subf3 R2, R1, R0 & subf3 R1, R0 & subf3 R1, *+AR0(1), R0 & subf3 *+AR0(1), R1, R0 & subf3 *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & subf3_S_c4x: & subf3 *+AR0(5), R1, R0 & subf3 *+AR0(5), R0 & subf3 *+AR0(5), *+AR1(5), R0 & .endif
.ifdef TEST_C3X & subf_stf_Q: & subf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_stf_Q_enh: & subf R0, R0, R0 &|| stf R1, *+AR1(1) & subf R0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, R0, R0 & stf R1, *+AR1(1) &|| subf R0, R0 & .endif & .ifdef TEST_C3X & subf3_stf_Q: & subf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_stf_Q_enh: & subf3 R0, R0, R0 &|| stf R1, *+AR1(1) & subf3 R0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, R0, R0 & stf R1, *+AR1(1) &|| subf3 R0, R0 & .endif
.ifdef TEST_C3X & subi_A: & subi AR1, AR0 & subi AR0 & subi @start, AR0 & subi *+AR0(5), AR0 & subi -5, AR0 & .endif
.ifdef TEST_C3X & subi_T: & subi AR2, AR1, AR0 & subi AR1, AR0 & subi AR1, *+AR0(1), AR0 & subi *+AR0(1), AR1, AR0 & subi *+AR0(1), AR0 & subi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subi_T_sc: & subi -5, AR1, AR0 & subi -5, AR0 & subi *+AR0(5), AR1, AR0 & subi *+AR0(5), AR0 & subi -5, *+AR0(5), AR0 & subi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & subi3_T: & subi3 AR2, AR1, AR0 & subi3 AR1, AR0 & subi3 AR1, *+AR0(1), AR0 & subi3 *+AR0(1), AR1, AR0 & subi3 *+AR0(1), AR0 & subi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subi3_T_sc: & subi3 -5, AR1, AR0 & subi3 -5, AR0 & subi3 *+AR0(5), AR1, AR0 & subi3 *+AR0(5), AR0 & subi3 -5, *+AR0(5), AR0 & subi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & subi_sti_Q: & subi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_sti_Q_enh: & subi R0, R0, R0 &|| sti R1, *+AR1(1) & subi R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, R0, R0 & sti R1, *+AR1(1) &|| subi R0, R0 & .endif & .ifdef TEST_C3X & subi3_sti_Q: & subi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_sti_Q_enh: & subi3 R0, R0, R0 &|| sti R1, *+AR1(1) & subi3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, R0, R0 & sti R1, *+AR1(1) &|| subi3 R0, R0 & .endif
.ifdef TEST_C3X & subrb_A: & subrb AR1, AR0 & subrb AR0 & subrb @start, AR0 & subrb *+AR0(5), AR0 & subrb -5, AR0 & .endif
.ifdef TEST_C3X & subrf_B: & subrf R1, R0 & subrf R0 & subrf @start, R0 & subrf *+AR0(5), R0 & subrf 3.5, R0 & .endif
.ifdef TEST_C3X & subri_A: & subri AR1, AR0 & subri AR0 & subri @start, AR0 & subri *+AR0(5), AR0 & subri -5, AR0 & .endif
.ifdef TEST_C3X
swi_Z: swi
trap_Z: trapC 10
trap 10
.endif
.ifdef TEST_C3X & tstb_AU: & tstb AR1, AR0 & tstb AR0 & tstb @start, AR0 & tstb *+AR0(5), AR0 & tstb 5, AR0 & .endif
.ifdef TEST_C3X & tstb_T2C: & tstb AR2, AR1 & tstb AR1, *+AR0(1) & tstb *+AR0(1), AR1 & tstb *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & tstb_T2C_c4x: & tstb -5, AR1 & tstb AR1, -5 & tstb *+AR0(5), AR1 & tstb AR1, *+AR0(5) & tstb -5, *+AR0(5) & tstb *+AR0(5), -5 & tstb *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & tstb3_T2C: & tstb3 AR2, AR1 & tstb3 AR1, *+AR0(1) & tstb3 *+AR0(1), AR1 & tstb3 *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & tstb3_T2C_c4x: & tstb3 -5, AR1 & tstb3 AR1, -5 & tstb3 *+AR0(5), AR1 & tstb3 AR1, *+AR0(5) & tstb3 -5, *+AR0(5) & tstb3 *+AR0(5), -5 & tstb3 *+AR0(5), *+AR1(5) & .endif
.ifdef TEST_C3X & xor_AU: & xor AR1, AR0 & xor AR0 & xor @start, AR0 & xor *+AR0(5), AR0 & xor 5, AR0 & .endif
.ifdef TEST_C3X & xor_TC: & xor AR2, AR1, AR0 & xor AR1, AR0 & xor AR1, *+AR0(1), AR0 & xor *+AR0(1), AR1, AR0 & xor *+AR0(1), AR0 & xor *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & xor_TC_c4x: & xor -5, AR1, AR0 & xor -5, AR0 & xor AR1, -5, AR0 & xor *+AR0(5), AR1, AR0 & xor *+AR0(5), AR0 & xor AR1, *+AR0(5), AR0 & xor -5, *+AR0(5), AR0 & xor *+AR0(5), -5, AR0 & xor *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & xor3_TC: & xor3 AR2, AR1, AR0 & xor3 AR1, AR0 & xor3 AR1, *+AR0(1), AR0 & xor3 *+AR0(1), AR1, AR0 & xor3 *+AR0(1), AR0 & xor3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & xor3_TC_c4x: & xor3 -5, AR1, AR0 & xor3 -5, AR0 & xor3 AR1, -5, AR0 & xor3 *+AR0(5), AR1, AR0 & xor3 *+AR0(5), AR0 & xor3 AR1, *+AR0(5), AR0 & xor3 -5, *+AR0(5), AR0 & xor3 *+AR0(5), -5, AR0 & xor3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C3X & xor_sti_QC: & xor *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & xor_sti_QC_enh: & xor AR0, R1, R0 &|| sti R1, *+AR1(1) & xor R2, R1, R0 &|| sti R1, *+AR1(1) & xor R1, R0 &|| sti R1, *+AR1(1) & xor R0 &|| sti R1, *+AR1(1) & xor R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor AR0, R1, R0 & sti R1, *+AR1(1) &|| xor R2, R1, R0 & sti R1, *+AR1(1) &|| xor R1, R0 & sti R1, *+AR1(1) &|| xor R0 & sti R1, *+AR1(1) &|| xor R0, AR0, R0 & .endif & .ifdef TEST_C3X & xor3_sti_QC: & xor3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & xor3_sti_QC_enh: & xor3 AR0, R1, R0 &|| sti R1, *+AR1(1) & xor3 R2, R1, R0 &|| sti R1, *+AR1(1) & xor3 R1, R0 &|| sti R1, *+AR1(1) & xor3 R0 &|| sti R1, *+AR1(1) & xor3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 AR0, R1, R0 & sti R1, *+AR1(1) &|| xor3 R2, R1, R0 & sti R1, *+AR1(1) &|| xor3 R1, R0 & sti R1, *+AR1(1) &|| xor3 R0 & sti R1, *+AR1(1) &|| xor3 R0, AR0, R0 & .endif
;;------------------------------------
;; C4X INSNS
;;------------------------------------
.ifdef TEST_C4X
.ifdef TEST_C4X & bCaf_J: & bCaf R0 & bCaf start & baf_J: & baf R0 & baf start & .endif
.ifdef TEST_C4X & bCat_J: & bCat R0 & bCat start & bat_J: & bat R0 & bat start & .endif
.ifdef TEST_C4X & frieee_B6: & frieee @start, R0 & frieee *+AR0(5), R0 & .endif
.ifdef TEST_C4X & frieee_stf_P: & frieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee *+AR0(1), R0 & .endif & .ifdef TEST_ENH & frieee_stf_P_enh: & frieee R0, R0 &|| stf R1, *+AR1(1) & frieee R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee R0, R0 & stf R1, *+AR1(1) &|| frieee R0 & .endif
.ifdef TEST_C4X
laj_I: laj start
laj_JS: lajc R0
lajc start
lat_Z: latC 10
.endif
.ifdef TEST_C4X & lb0_A: & lb0 AR1, AR0 & lb0 AR0 & lb0 @start, AR0 & lb0 *+AR0(5), AR0 & lb0 -5, AR0 & .endif
.ifdef TEST_C4X & lb1_A: & lb1 AR1, AR0 & lb1 AR0 & lb1 @start, AR0 & lb1 *+AR0(5), AR0 & lb1 -5, AR0 & .endif
.ifdef TEST_C4X & lb2_A: & lb2 AR1, AR0 & lb2 AR0 & lb2 @start, AR0 & lb2 *+AR0(5), AR0 & lb2 -5, AR0 & .endif
.ifdef TEST_C4X & lb3_A: & lb3 AR1, AR0 & lb3 AR0 & lb3 @start, AR0 & lb3 *+AR0(5), AR0 & lb3 -5, AR0 & .endif
.ifdef TEST_C4X & lbu0_AU: & lbu0 AR1, AR0 & lbu0 AR0 & lbu0 @start, AR0 & lbu0 *+AR0(5), AR0 & lbu0 5, AR0 & .endif
.ifdef TEST_C4X & lbu1_AU: & lbu1 AR1, AR0 & lbu1 AR0 & lbu1 @start, AR0 & lbu1 *+AR0(5), AR0 & lbu1 5, AR0 & .endif
.ifdef TEST_C4X & lbu2_AU: & lbu2 AR1, AR0 & lbu2 AR0 & lbu2 @start, AR0 & lbu2 *+AR0(5), AR0 & lbu2 5, AR0 & .endif
.ifdef TEST_C4X & lbu3_AU: & lbu3 AR1, AR0 & lbu3 AR0 & lbu3 @start, AR0 & lbu3 *+AR0(5), AR0 & lbu3 5, AR0 & .endif
.ifdef TEST_C4X & lda_AY: & lda AR1, AR0 & lda @start, AR0 & lda *+AR0(5), AR0 & lda -5, AR0 & .endif
.ifdef TEST_C4X
ldep_Z: ldep IVTP, AR0
ldhi_Z: ldhi 35, R0
ldhi start, R0
ldpe_Z: ldpe AR0, IVTP
ldpk_Z: ldpk start
.endif
.ifdef TEST_C4X & lh0_A: & lh0 AR1, AR0 & lh0 AR0 & lh0 @start, AR0 & lh0 *+AR0(5), AR0 & lh0 -5, AR0 & .endif
.ifdef TEST_C4X & lh1_A: & lh1 AR1, AR0 & lh1 AR0 & lh1 @start, AR0 & lh1 *+AR0(5), AR0 & lh1 -5, AR0 & .endif
.ifdef TEST_C4X & lhu0_AU: & lhu0 AR1, AR0 & lhu0 AR0 & lhu0 @start, AR0 & lhu0 *+AR0(5), AR0 & lhu0 5, AR0 & .endif
.ifdef TEST_C4X & lhu1_AU: & lhu1 AR1, AR0 & lhu1 AR0 & lhu1 @start, AR0 & lhu1 *+AR0(5), AR0 & lhu1 5, AR0 & .endif
.ifdef TEST_C4X & lwl0_A: & lwl0 AR1, AR0 & lwl0 AR0 & lwl0 @start, AR0 & lwl0 *+AR0(5), AR0 & lwl0 -5, AR0 & .endif
.ifdef TEST_C4X & lwl1_A: & lwl1 AR1, AR0 & lwl1 AR0 & lwl1 @start, AR0 & lwl1 *+AR0(5), AR0 & lwl1 -5, AR0 & .endif
.ifdef TEST_C4X & lwl2_A: & lwl2 AR1, AR0 & lwl2 AR0 & lwl2 @start, AR0 & lwl2 *+AR0(5), AR0 & lwl2 -5, AR0 & .endif
.ifdef TEST_C4X & lwl3_A: & lwl3 AR1, AR0 & lwl3 AR0 & lwl3 @start, AR0 & lwl3 *+AR0(5), AR0 & lwl3 -5, AR0 & .endif
.ifdef TEST_C4X & lwr0_A: & lwr0 AR1, AR0 & lwr0 AR0 & lwr0 @start, AR0 & lwr0 *+AR0(5), AR0 & lwr0 -5, AR0 & .endif
.ifdef TEST_C4X & lwr1_A: & lwr1 AR1, AR0 & lwr1 AR0 & lwr1 @start, AR0 & lwr1 *+AR0(5), AR0 & lwr1 -5, AR0 & .endif
.ifdef TEST_C4X & lwr2_A: & lwr2 AR1, AR0 & lwr2 AR0 & lwr2 @start, AR0 & lwr2 *+AR0(5), AR0 & lwr2 -5, AR0 & .endif
.ifdef TEST_C4X & lwr3_A: & lwr3 AR1, AR0 & lwr3 AR0 & lwr3 @start, AR0 & lwr3 *+AR0(5), AR0 & lwr3 -5, AR0 & .endif
.ifdef TEST_C4X & mb0_A: & mb0 AR1, AR0 & mb0 AR0 & mb0 @start, AR0 & mb0 *+AR0(5), AR0 & mb0 -5, AR0 & .endif
.ifdef TEST_C4X & mb1_A: & mb1 AR1, AR0 & mb1 AR0 & mb1 @start, AR0 & mb1 *+AR0(5), AR0 & mb1 -5, AR0 & .endif
.ifdef TEST_C4X & mb2_A: & mb2 AR1, AR0 & mb2 AR0 & mb2 @start, AR0 & mb2 *+AR0(5), AR0 & mb2 -5, AR0 & .endif
.ifdef TEST_C4X & mb3_A: & mb3 AR1, AR0 & mb3 AR0 & mb3 @start, AR0 & mb3 *+AR0(5), AR0 & mb3 -5, AR0 & .endif
.ifdef TEST_C4X & mh0_A: & mh0 AR1, AR0 & mh0 AR0 & mh0 @start, AR0 & mh0 *+AR0(5), AR0 & mh0 -5, AR0 & .endif
.ifdef TEST_C4X & mh1_A: & mh1 AR1, AR0 & mh1 AR0 & mh1 @start, AR0 & mh1 *+AR0(5), AR0 & mh1 -5, AR0 & .endif
.ifdef TEST_C4X & mh2_A: & mh2 AR1, AR0 & mh2 AR0 & mh2 @start, AR0 & mh2 *+AR0(5), AR0 & mh2 -5, AR0 & .endif
.ifdef TEST_C4X & mh3_A: & mh3 AR1, AR0 & mh3 AR0 & mh3 @start, AR0 & mh3 *+AR0(5), AR0 & mh3 -5, AR0 & .endif
.ifdef TEST_C4X & mpyshi_A: & mpyshi AR1, AR0 & mpyshi AR0 & mpyshi @start, AR0 & mpyshi *+AR0(5), AR0 & mpyshi -5, AR0 & .endif
.ifdef TEST_C4X & mpyshi_TC: & mpyshi AR2, AR1, AR0 & mpyshi AR1, AR0 & mpyshi AR1, *+AR0(1), AR0 & mpyshi *+AR0(1), AR1, AR0 & mpyshi *+AR0(1), AR0 & mpyshi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyshi_TC_c4x: & mpyshi -5, AR1, AR0 & mpyshi -5, AR0 & mpyshi AR1, -5, AR0 & mpyshi *+AR0(5), AR1, AR0 & mpyshi *+AR0(5), AR0 & mpyshi AR1, *+AR0(5), AR0 & mpyshi -5, *+AR0(5), AR0 & mpyshi *+AR0(5), -5, AR0 & mpyshi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C4X & mpyshi3_TC: & mpyshi3 AR2, AR1, AR0 & mpyshi3 AR1, AR0 & mpyshi3 AR1, *+AR0(1), AR0 & mpyshi3 *+AR0(1), AR1, AR0 & mpyshi3 *+AR0(1), AR0 & mpyshi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyshi3_TC_c4x: & mpyshi3 -5, AR1, AR0 & mpyshi3 -5, AR0 & mpyshi3 AR1, -5, AR0 & mpyshi3 *+AR0(5), AR1, AR0 & mpyshi3 *+AR0(5), AR0 & mpyshi3 AR1, *+AR0(5), AR0 & mpyshi3 -5, *+AR0(5), AR0 & mpyshi3 *+AR0(5), -5, AR0 & mpyshi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C4X & mpyuhi_A: & mpyuhi AR1, AR0 & mpyuhi AR0 & mpyuhi @start, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi -5, AR0 & .endif
.ifdef TEST_C4X & mpyuhi_TC: & mpyuhi AR2, AR1, AR0 & mpyuhi AR1, AR0 & mpyuhi AR1, *+AR0(1), AR0 & mpyuhi *+AR0(1), AR1, AR0 & mpyuhi *+AR0(1), AR0 & mpyuhi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyuhi_TC_c4x: & mpyuhi -5, AR1, AR0 & mpyuhi -5, AR0 & mpyuhi AR1, -5, AR0 & mpyuhi *+AR0(5), AR1, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi AR1, *+AR0(5), AR0 & mpyuhi -5, *+AR0(5), AR0 & mpyuhi *+AR0(5), -5, AR0 & mpyuhi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C4X & mpyuhi3_TC: & mpyuhi3 AR2, AR1, AR0 & mpyuhi3 AR1, AR0 & mpyuhi3 AR1, *+AR0(1), AR0 & mpyuhi3 *+AR0(1), AR1, AR0 & mpyuhi3 *+AR0(1), AR0 & mpyuhi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyuhi3_TC_c4x: & mpyuhi3 -5, AR1, AR0 & mpyuhi3 -5, AR0 & mpyuhi3 AR1, -5, AR0 & mpyuhi3 *+AR0(5), AR1, AR0 & mpyuhi3 *+AR0(5), AR0 & mpyuhi3 AR1, *+AR0(5), AR0 & mpyuhi3 -5, *+AR0(5), AR0 & mpyuhi3 *+AR0(5), -5, AR0 & mpyuhi3 *+AR0(5), *+AR1(5), AR0 & .endif
.ifdef TEST_C4X & rcpf_BA: & rcpf AR1, R0 & rcpf R0 & rcpf @start, R0 & rcpf *+AR0(5), R0 & rcpf 3.5, R0 & .endif
.ifdef TEST_C4X
retid_Z: retiCd
retid
rptb2_I2: rptb AR0
rptbd_I2: rptbd start
rptbd AR0
.endif
.ifdef TEST_C4X & rsqrf_B: & rsqrf R1, R0 & rsqrf R0 & rsqrf @start, R0 & rsqrf *+AR0(5), R0 & rsqrf 3.5, R0 & .endif
.ifdef TEST_C4X & sigi_A6: & sigi @start, AR0 & sigi *+AR0(5), AR0 & .endif
.ifdef TEST_C4X
sti2_A7: sti -5, @start
sti -5, *+AR0(5)
stik_Z: stik -5, @start
stik -5, *+AR0(5)
.endif
.ifdef TEST_C4X & toieee_B: & toieee R1, R0 & toieee R0 & toieee @start, R0 & toieee *+AR0(5), R0 & toieee 3.5, R0 & .endif
.ifdef TEST_C4X & toieee_stf_P: & toieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee *+AR0(1), R0 & .endif & .ifdef TEST_ENH & toieee_stf_P_enh: & toieee R0, R0 &|| stf R1, *+AR1(1) & toieee R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee R0, R0 & stf R1, *+AR1(1) &|| toieee R0 & .endif
.endif
.end
|
stsp/binutils-ia16
| 1,549
|
gas/testsuite/gas/tic4x/registers.s
|
;; test all register names c3x
.text
;; Test the base names
.ifdef TEST_ALL
start: ldi R0,R0
ldi R0,R1
ldi R0,R2
ldi R0,R3
ldi R0,R4
ldi R0,R5
ldi R0,R6
ldi R0,R7
ldi R0,AR0
ldi R0,AR1
ldi R0,AR2
ldi R0,AR3
ldi R0,AR4
ldi R0,AR5
ldi R0,AR6
ldi R0,AR7
ldi R0,DP
ldi R0,IR0
ldi R0,IR1
ldi R0,BK
ldi R0,SP
ldi R0,ST
.endif
.ifdef TEST_C3X
ldi R0,IE
ldi R0,IF
ldi R0,IOF
.endif
.ifdef TEST_C4X
ldi R0,DIE
ldi R0,IIE
ldi R0,IIF
.endif
.ifdef TEST_ALL
ldi R0,RS
ldi R0,RE
ldi R0,RC
.endif
.ifdef TEST_C4X
ldi R0,R8
ldi R0,R9
ldi R0,R10
ldi R0,R11
ldpe R0,IVTP
ldpe R0,TVTP
.endif
;; Test the alternative names
.ifdef TEST_ALL
ldf F0,F0
ldf F0,F1
ldf F0,F2
ldf F0,F3
ldf F0,F4
ldf F0,F5
ldf F0,F6
ldf F0,F7
.endif
.ifdef TEST_C4X
ldf F0,F8
ldf F0,F9
ldf F0,F10
ldf F0,F11
.endif
.end
|
stsp/binutils-ia16
| 1,321
|
gas/testsuite/gas/arc/nps400-7.s
|
.text
;; mrgb
mrgb r0,r0,r1,4,5,3,8,6,2
mrgb.cl r2,r2,r1,4,5,3,8,6,2
;; mov2b
mov2b r1,r1,r2,4,3,2,8,1,6
mov2b.cl r1,r2,4,3,2,8,1,6
;; ext4b
ext4b r3,r3,r12,28,5,10,30,31
ext4b.cl r2,r13,28,5,10,30,31
;; ins4b
ins4b r3,r3,r12,5,10,30,31,28
ins4b.cl r2,r13,5,10,30,31,28
;; mov3b
mov3b r14,r14,r12, 1,0,6, 7,3,2, 20,2,21
mov3b r1,r1,r12, 4,1,1, 3,0,16, 3,3,8
mov3b r14,r14,r12, 8,2,14, 8,1,2, 14,0,3
mov3b r1,r1,r12, 12,3,1, 3,2,13, 5,1,2
;; mov3bcl
mov3bcl r0,r1, 1,0,1, 0,1,1, 12,3,0
mov3b.cl r0,r1, 2,1,5, 22,2,2, 31,2,3
mov3bcl r0,r1, 3,2,9, 23,3,6, 30,1,31
mov3b.cl r0,r1, 4,3,11, 24,0,30, 30,0,30
;; mov4b
mov4b r0,r0,r14, 10,3,20, 2,2,0, 6,1,7, 14,0,3
mov4b r0,r0,r14, 1,0,11, 12,3,4, 31,2,11, 24,1,2
mov4b r0,r0,r14, 5,1,8, 21,0,30, 3,3,31, 8,2,8
mov4b r0,r0,r14, 15,2,13, 22,1,22, 13,0,30, 4,3,4
;; mov4bl
mov4bcl r12,r13,1,1,1,2,2,2,3,3,3,4,0,4
mov4b.cl r13,r14,1,2,1,2,3,2,3,0,3,4,1,4
mov4bcl r2,r3, 1,3,1,2,0,2,3,1,3,4,2,4
mov4b.cl r1,r2, 1,0,1,2,1,2,3,2,3,4,3,4
|
stsp/binutils-ia16
| 1,827
|
gas/testsuite/gas/arc/pseudos.s
|
# Test pseudo instructions generation.
push r0
pop r1
.L1:
brgt r0, r1, @.L1 ; Encode as BRLT<.d> c,b,s9
brgt r0, -1, @.L1 ; Encode as BRGE<.d> b,u6+1,s9
brgt r0, 0x3F, @.L1 ; Encode as BRLT limm,b,s9
brgt r0, -2, @.L1 ; Encode as BRLT limm,b,s9
brgt -2, r0, @.L1 ; Encode as BRLT c,limm,s9
brgt -2, -1, @.L1 ; Encode as BRGE limm,u6+1,s9
brgt -2, 0x3E, @.L1 ; Encode as BRGE limm,u6+1,s9
brhi r1, r1, @.L1 ; BRHI<.d> b,c,s9 Encode as BRLO<.d> c,b,s9
brhi r1, -1, @.L1 ; BRHI<.d> b,u6,s9 Encode as BRHS<.d> b,u6+1,s9
brhi r1, 0x3F, @.L1 ; BRHI b,limm,s9 Encode as BRLO limm,b,s9
brhi r1, -2, @.L1 ; BRHI b,limm,s9 Encode as BRLO limm,b,s9
brhi -2, r0, @.L1 ; BRHI limm,c,s9 Encode as BRLO c,limm,s9
brhi -2, -1, @.L1 ; BRHI limm,u6,s9 Encode as BRHS limm,u6+1,s9
brhi -2, 0x3E, @.L1 ; BRHI limm,u6,s9 Encode as BRHS limm,u6+1,s9
brle r1, r1, @.L1 ; BRLE<.d> b,c,s9 Encode as BRGE<.d> c,b,s9
brle r1, -1, @.L1 ; BRLE<.d> b,u6,s9 Encode as BRLT<.d> b,u6+1,s9
brle r1, 0x3F, @.L1 ; BRLE b,limm,s9 Encode as BRGE limm,b,s9
brle r1, -2, @.L1 ; BRLE b,limm,s9 Encode as BRGE limm,b,s9
brle -2, r0, @.L1 ; BRLE limm,c,s9 Encode as BRGE c,limm,s9
brle -2, -1, @.L1 ; BRLE limm,u6,s9 Encode as BRLT limm,u6+1,s9
brle -2, 0x3E, @.L1 ; BRLE limm,u6,s9 Encode as BRLT limm,u6+1,s9
brle r1, r1, @.L1 ; BRLS<.d> b,c,s9 Encode as BRHS<.d> c,b,s9
brle r1, -1, @.L1 ; BRLS<.d> b,u6,s9 Encode as BRLO b,u6+1,s9
brle r1, 0x3F, @.L1 ; BRLS b,limm,s9 Encode as BRHS limm,b,s9
brle r1, -2, @.L1 ; BRLS limm,c,s9 Encode as BRHS c,limm,s9
brle -2, r0, @.L1 ; BRLS limm,c,s9 Encode as BRHS c,limm,s9
brle -2, -1, @.L1 ; BRLS limm,u6,s9 Encode as BRLO limm,u6+1,s9
brle -2, 0x3E, @.L1 ; BRLS limm,u6,s9 Encode as BRLO limm,u6+1,s9
|
stsp/binutils-ia16
| 1,915
|
gas/testsuite/gas/arc/nps400-12.s
|
.text
; Miscellaneous
; whash
whash r2,[cm:r0],r1
whash r5,[cm:r3],r14
whash 0,[cm:r0],r1
whash 0,[cm:r3],r14
whash r2,[cm:r0],7
whash 0,[cm:r0],7
whash r2,[cm:r0],64
whash 0,[cm:r0],64
; mcmp
mcmp r0,[cm:r0],[cm:r1],r1
mcmp.s r0,[cm:r0],[cm:r1],r1
mcmp.m r0,[cm:r0],[cm:r1],r1
mcmp.s.m r0,[cm:r0],[cm:r1],r1
mcmp r0,[cm:r0,r0],[cm:r1],r1
mcmp.s r0,[cm:r0,r0],[cm:r1],r1
mcmp.m r0,[cm:r0,r0],[cm:r1],r1
mcmp.s.m r0,[cm:r0,r0],[cm:r1],r1
mcmp r0,[cm:r0,4],[cm:r1],r1
mcmp.s r0,[cm:r0,4],[cm:r1],r1
mcmp.m r0,[cm:r0,4],[cm:r1],r1
mcmp.s.m r0,[cm:r0,4],[cm:r1],r1
mcmp r0,[cm:r0,8],[cm:r1],r1
mcmp r0,[cm:r0,12],[cm:r1],r1
mcmp r0,[cm:r0],[cm:r1],4
mcmp.s r0,[cm:r0],[cm:r1],4
mcmp.m r0,[cm:r0],[cm:r1],4
mcmp.s.m r0,[cm:r0],[cm:r1],8
mcmp r0,[cm:r0],[cm:r1],127
mcmp r0,[cm:r0,8],[cm:r1],4
mcmp.s r0,[cm:r0,8],[cm:r1],4
mcmp.m r0,[cm:r0,8],[cm:r1],4
mcmp.s.m r0,[cm:r0,8],[cm:r1],4
mcmp r0,[cm:r0,r0],[cm:r1],46
mcmp.s r0,[cm:r0,r0],[cm:r1],70
mcmp.m r0,[cm:r0,r0],[cm:r1],72
mcmp.s.m r0,[cm:r0,r0],[cm:r1],125
;asri
asri 0, r0
asri.core 0, r0
asri.clsr 0,r0
asri.all 0,r0
asri.gic 0,r0
rspi.gic 0,r0
;wkup
wkup 0,r0
wkup.cl
;getsti
getsti r2,[cm:r0]
getsti 0,[cm:r0]
label:
;getrtc
getrtc r2,[cm:r0]
getrtc 0,[cm:r0]
;b<cc>
bnj label
bnm label
bnt label
|
stsp/binutils-ia16
| 1,428
|
gas/testsuite/gas/arc/nps400-9.s
|
.text
;; dcmac
dcmac r0,[cm:r0],[cm:r0],r0
dcmac r2,[cm:r4],[cm:r4],r7
dcmac r31,[cm:r31],[cm:r31],r31
dcmac r0,[cm:r0],[cm:0x0],r0
dcmac r2,[cm:r4],[cm:0x1234],r7
dcmac r31,[cm:r31],[cm:0xffff],r31
dcmac r0,[cm:0x0],[cm:r0],r0
dcmac r2,[cm:0x4321],[cm:r4],r7
dcmac r31,[cm:0xffff],[cm:r31],r31
dcmac 0,[cm:r0],[cm:r0],r0
dcmac 0,[cm:r4],[cm:r4],r7
dcmac 0,[cm:r31],[cm:r31],r31
dcmac 0,[cm:r0],[cm:0x0],r0
dcmac 0,[cm:r4],[cm:0x1234],r7
dcmac 0,[cm:r31],[cm:0xffff],r31
dcmac 0,[cm:0x0],[cm:r0],r0
dcmac 0,[cm:0x4321],[cm:r4],r7
dcmac 0,[cm:0xffff],[cm:r31],r31
dcmac r0,[cm:r0],[cm:r0],1
dcmac r2,[cm:r4],[cm:r4],0xf
dcmac r31,[cm:r31],[cm:r31],0x3f
dcmac r0,[cm:r0],[cm:0x0],1
dcmac r2,[cm:r4],[cm:0x1234],0xf
dcmac r31,[cm:r31],[cm:0xffff],0x3f
dcmac r0,[cm:0x0],[cm:r0],1
dcmac r2,[cm:0x4321],[cm:r4],0xf
dcmac r31,[cm:0xffff],[cm:r31],0x3f
dcmac 0,[cm:r0],[cm:r0],1
dcmac 0,[cm:r4],[cm:r4],0xf
dcmac 0,[cm:r31],[cm:r31],64
dcmac 0,[cm:r0],[cm:0x0],1
dcmac 0,[cm:r4],[cm:0x1234],0xf
dcmac 0,[cm:r31],[cm:0xffff],64
dcmac 0,[cm:0x0],[cm:r0],1
dcmac 0,[cm:0x4321],[cm:r4],0xf
dcmac 0,[cm:0xffff],[cm:r31],64
|
stsp/binutils-ia16
| 12,136
|
gas/testsuite/gas/arc/nps400-11.s
|
.text
; cp16/cp32 xa
cp16.na [cm:r1],[xa:r2]
cp16 [cm:r1],[xa:r2]
cp32.na [cm:r1],[xa:r2]
cp32 [cm:r1],[xa:r2]
cp16.na [cm:r1],[xa:r2,r1]
cp16 [cm:r1],[xa:r2,r1]
cp32.na [cm:r1],[xa:r2,r1]
cp32 [cm:r1],[xa:r2,r1]
cp16.na r2, [cm:r1],[xa:r2]
cp16 r2, [cm:r1],[xa:r2]
cp32.na r2, [cm:r1],[xa:r2]
cp32 r2, [cm:r1],[xa:r2]
cp16.na r2, [cm:r1],[xa:r2,r1]
cp16 r2, [cm:r1],[xa:r2,r1]
cp32.na r2, [cm:r1],[xa:r2,r1]
cp32 r2, [cm:r1],[xa:r2,r1]
;; cp16/cp32 jid
cp32 [cm:r1],[jid:r2]
cp32 r2, [cm:r1],[jid:r2]
;; cp16/cp32 sd
cp16 [cm:r2],[sd:r1,16,0]
cp16.na [cm:r2],[sd:r1,16,0]
cp16 r1, [cm:r2],[sd:r1,16,0]
cp16.na r1, [cm:r2],[sd:r1,16,0]
cp16 [cm:r2],[sd:r1,32,0]
cp16.na [cm:r2],[sd:r1,32,0]
cp16 r1, [cm:r2],[sd:r1,32,0]
cp16.na r1, [cm:r2],[sd:r1,32,0]
cp16 [cm:r2],[sd:r1,64,0]
cp16.na [cm:r2],[sd:r1,64,0]
cp16 r1, [cm:r2],[sd:r1,64,0]
cp16.na r1, [cm:r2],[sd:r1,64,0]
cp16 [cm:r2],[sd:r1,128,0]
cp16.na [cm:r2],[sd:r1,128,0]
cp16 r1, [cm:r2],[sd:r1,128,0]
cp16.na r1, [cm:r2],[sd:r1,128,0]
cp16 [cm:r2],[sd:r1,16,0]
cp16.na [cm:r2],[sd:r1,16,0]
cp16 r1, [cm:r2],[sd:r1,16,0]
cp16.na r1, [cm:r2],[sd:r1,16,0]
cp16 [cm:r2],[sd:r1,16,16]
cp16.na [cm:r2],[sd:r1,16,16]
cp16 r1, [cm:r2],[sd:r1,16,16]
cp16.na r1, [cm:r2],[sd:r1,16,16]
cp16 [cm:r2],[sd:r1,16,32]
cp16.na [cm:r2],[sd:r1,16,32]
cp16 r1, [cm:r2],[sd:r1,16,32]
cp16.na r1, [cm:r2],[sd:r1,16,32]
cp16 [cm:r2],[sd:r1,16,48]
cp16.na [cm:r2],[sd:r1,16,48]
cp16 r1, [cm:r2],[sd:r1,16,48]
cp16.na r1, [cm:r2],[sd:r1,16,48]
cp16 [cm:r2],[sd:r1,16,64]
cp16.na [cm:r2],[sd:r1,16,64]
cp16 r1, [cm:r2],[sd:r1,16,64]
cp16.na r1, [cm:r2],[sd:r1,16,64]
cp16 [cm:r2],[sd:r1,16,0, r2]
cp16.na [cm:r2],[sd:r1,16,0, r2]
cp16 r1, [cm:r2],[sd:r1,16,0,r2]
cp16.na r1, [cm:r2],[sd:r1,16,0,r2]
cp16 [cm:r2],[sd:r1,32,0, r2]
cp16.na [cm:r2],[sd:r1,32,0, r2]
cp16 r1, [cm:r2],[sd:r1,32,0, r2]
cp16.na r1, [cm:r2],[sd:r1,32,0, r2]
cp16 [cm:r2],[sd:r1,64,0, r2]
cp16.na [cm:r2],[sd:r1,64,0, r2]
cp16 r1, [cm:r2],[sd:r1,64,0, r2]
cp16.na r1, [cm:r2],[sd:r1,64,0, r2]
cp16 [cm:r2],[sd:r1,128,0, r2]
cp16.na [cm:r2],[sd:r1,128,0, r2]
cp16 r1, [cm:r2],[sd:r1,128,0, r2]
cp16.na r1, [cm:r2],[sd:r1,128,0, r2]
cp16 [cm:r2],[sd:r1,r2,r2]
cp16.na [cm:r2],[sd:r1,r2,r2]
cp16 r1, [cm:r2],[sd:r1,r2,r2]
cp16.na r1, [cm:r2],[sd:r1,r2,r2]
cp16 [cm:r2],[sd:r1,r2,r2,r2]
cp16.na [cm:r2],[sd:r1,r2,r2,r2]
cp16 r1, [cm:r2],[sd:r1,r2,r2,r2]
cp16.na r1, [cm:r2],[sd:r1,r2,r2,r2]
cp32 [cm:r2],[sd:r1,16,0]
cp32.na [cm:r2],[sd:r1,16,0]
cp32 r1, [cm:r2],[sd:r1,16,0]
cp32.na r1, [cm:r2],[sd:r1,16,0]
cp32 [cm:r2],[sd:r1,32,0]
cp32.na [cm:r2],[sd:r1,32,0]
cp32 r1, [cm:r2],[sd:r1,32,0]
cp32.na r1, [cm:r2],[sd:r1,32,0]
cp32 [cm:r2],[sd:r1,64,0]
cp32.na [cm:r2],[sd:r1,64,0]
cp32 r1, [cm:r2],[sd:r1,64,0]
cp32.na r1, [cm:r2],[sd:r1,64,0]
cp32 [cm:r2],[sd:r1,128,0]
cp32.na [cm:r2],[sd:r1,128,0]
cp32 r1, [cm:r2],[sd:r1,128,0]
cp32.na r1, [cm:r2],[sd:r1,128,0]
cp32 [cm:r2],[sd:r1,16,0]
cp32.na [cm:r2],[sd:r1,16,0]
cp32 r1, [cm:r2],[sd:r1,16,0]
cp32.na r1, [cm:r2],[sd:r1,16,0]
cp32 [cm:r2],[sd:r1,16,16]
cp32.na [cm:r2],[sd:r1,16,16]
cp32 r1, [cm:r2],[sd:r1,16,16]
cp32.na r1, [cm:r2],[sd:r1,16,16]
cp32 [cm:r2],[sd:r1,16,32]
cp32.na [cm:r2],[sd:r1,16,32]
cp32 r1, [cm:r2],[sd:r1,16,32]
cp32.na r1, [cm:r2],[sd:r1,16,32]
cp32 [cm:r2],[sd:r1,16,48]
cp32.na [cm:r2],[sd:r1,16,48]
cp32 r1, [cm:r2],[sd:r1,16,48]
cp32.na r1, [cm:r2],[sd:r1,16,48]
cp32 [cm:r2],[sd:r1,16,64]
cp32.na [cm:r2],[sd:r1,16,64]
cp32 r1, [cm:r2],[sd:r1,16,64]
cp32.na r1, [cm:r2],[sd:r1,16,64]
cp32 [cm:r2],[sd:r1,16,0, r2]
cp32.na [cm:r2],[sd:r1,16,0, r2]
cp32 r1, [cm:r2],[sd:r1,16,0,r2]
cp32.na r1, [cm:r2],[sd:r1,16,0,r2]
cp32 [cm:r2],[sd:r1,32,0, r2]
cp32.na [cm:r2],[sd:r1,32,0, r2]
cp32 r1, [cm:r2],[sd:r1,32,0, r2]
cp32.na r1, [cm:r2],[sd:r1,32,0, r2]
cp32 [cm:r2],[sd:r1,64,0, r2]
cp32.na [cm:r2],[sd:r1,64,0, r2]
cp32 r1, [cm:r2],[sd:r1,64,0, r2]
cp32.na r1, [cm:r2],[sd:r1,64,0, r2]
cp32 [cm:r2],[sd:r1,128,0, r2]
cp32.na [cm:r2],[sd:r1,128,0, r2]
cp32 r1, [cm:r2],[sd:r1,128,0, r2]
cp32.na r1, [cm:r2],[sd:r1,128,0, r2]
cp32 [cm:r2],[sd:r1,r2,r2]
cp32.na [cm:r2],[sd:r1,r2,r2]
cp32 r1, [cm:r2],[sd:r1,r2,r2]
cp32.na r1, [cm:r2],[sd:r1,r2,r2]
cp32 [cm:r2],[sd:r1,r2,r2,r2]
cp32.na [cm:r2],[sd:r1,r2,r2,r2]
cp32 r1, [cm:r2],[sd:r1,r2,r2,r2]
cp32.na r1, [cm:r2],[sd:r1,r2,r2,r2]
; cp16/cp32 xd
cp16 [cm:r2],[xd:r1,16,0]
cp16.na [cm:r2],[xd:r1,16,0]
cp16 r1, [cm:r2],[xd:r1,16,0]
cp16.na r1, [cm:r2],[xd:r1,16,0]
cp16 [cm:r2],[xd:r1,32,0]
cp16.na [cm:r2],[xd:r1,32,0]
cp16 r1, [cm:r2],[xd:r1,32,0]
cp16.na r1, [cm:r2],[xd:r1,32,0]
cp16 [cm:r2],[xd:r1,64,0]
cp16.na [cm:r2],[xd:r1,64,0]
cp16 r1, [cm:r2],[xd:r1,64,0]
cp16.na r1, [cm:r2],[xd:r1,64,0]
cp16 [cm:r2],[xd:r1,128,0]
cp16.na [cm:r2],[xd:r1,128,0]
cp16 r1, [cm:r2],[xd:r1,128,0]
cp16.na r1, [cm:r2],[xd:r1,128,0]
cp16 [cm:r2],[xd:r1,16,0]
cp16.na [cm:r2],[xd:r1,16,0]
cp16 r1, [cm:r2],[xd:r1,16,0]
cp16.na r1, [cm:r2],[xd:r1,16,0]
cp16 [cm:r2],[xd:r1,16,16]
cp16.na [cm:r2],[xd:r1,16,16]
cp16 r1, [cm:r2],[xd:r1,16,16]
cp16.na r1, [cm:r2],[xd:r1,16,16]
cp16 [cm:r2],[xd:r1,16,32]
cp16.na [cm:r2],[xd:r1,16,32]
cp16 r1, [cm:r2],[xd:r1,16,32]
cp16.na r1, [cm:r2],[xd:r1,16,32]
cp16 [cm:r2],[xd:r1,16,48]
cp16.na [cm:r2],[xd:r1,16,48]
cp16 r1, [cm:r2],[xd:r1,16,48]
cp16.na r1, [cm:r2],[xd:r1,16,48]
cp16 [cm:r2],[xd:r1,16,64]
cp16.na [cm:r2],[xd:r1,16,64]
cp16 r1, [cm:r2],[xd:r1,16,64]
cp16.na r1, [cm:r2],[xd:r1,16,64]
cp16 [cm:r2],[xd:r1,16,0, r2]
cp16.na [cm:r2],[xd:r1,16,0, r2]
cp16 r1, [cm:r2],[xd:r1,16,0,r2]
cp16.na r1, [cm:r2],[xd:r1,16,0,r2]
cp16 [cm:r2],[xd:r1,32,0, r2]
cp16.na [cm:r2],[xd:r1,32,0, r2]
cp16 r1, [cm:r2],[xd:r1,32,0, r2]
cp16.na r1, [cm:r2],[xd:r1,32,0, r2]
cp16 [cm:r2],[xd:r1,64,0, r2]
cp16.na [cm:r2],[xd:r1,64,0, r2]
cp16 r1, [cm:r2],[xd:r1,64,0, r2]
cp16.na r1, [cm:r2],[xd:r1,64,0, r2]
cp16 [cm:r2],[xd:r1,128,0, r2]
cp16.na [cm:r2],[xd:r1,128,0, r2]
cp16 r1, [cm:r2],[xd:r1,128,0, r2]
cp16.na r1, [cm:r2],[xd:r1,128,0, r2]
cp16 [cm:r2],[xd:r1,r2,r2]
cp16.na [cm:r2],[xd:r1,r2,r2]
cp16 r1, [cm:r2],[xd:r1,r2,r2]
cp16.na r1, [cm:r2],[xd:r1,r2,r2]
cp16 [cm:r2],[xd:r1,r2,r2,r2]
cp16.na [cm:r2],[xd:r1,r2,r2,r2]
cp16 r1, [cm:r2],[xd:r1,r2,r2,r2]
cp16.na r1, [cm:r2],[xd:r1,r2,r2,r2]
cp32 [cm:r2],[xd:r1,16,0]
cp32.na [cm:r2],[xd:r1,16,0]
cp32 r1, [cm:r2],[xd:r1,16,0]
cp32.na r1, [cm:r2],[xd:r1,16,0]
cp32 [cm:r2],[xd:r1,32,0]
cp32.na [cm:r2],[xd:r1,32,0]
cp32 r1, [cm:r2],[xd:r1,32,0]
cp32.na r1, [cm:r2],[xd:r1,32,0]
cp32 [cm:r2],[xd:r1,64,0]
cp32.na [cm:r2],[xd:r1,64,0]
cp32 r1, [cm:r2],[xd:r1,64,0]
cp32.na r1, [cm:r2],[xd:r1,64,0]
cp32 [cm:r2],[xd:r1,128,0]
cp32.na [cm:r2],[xd:r1,128,0]
cp32 r1, [cm:r2],[xd:r1,128,0]
cp32.na r1, [cm:r2],[xd:r1,128,0]
cp32 [cm:r2],[xd:r1,16,0]
cp32.na [cm:r2],[xd:r1,16,0]
cp32 r1, [cm:r2],[xd:r1,16,0]
cp32.na r1, [cm:r2],[xd:r1,16,0]
cp32 [cm:r2],[xd:r1,16,16]
cp32.na [cm:r2],[xd:r1,16,16]
cp32 r1, [cm:r2],[xd:r1,16,16]
cp32.na r1, [cm:r2],[xd:r1,16,16]
cp32 [cm:r2],[xd:r1,16,32]
cp32.na [cm:r2],[xd:r1,16,32]
cp32 r1, [cm:r2],[xd:r1,16,32]
cp32.na r1, [cm:r2],[xd:r1,16,32]
cp32 [cm:r2],[xd:r1,16,48]
cp32.na [cm:r2],[xd:r1,16,48]
cp32 r1, [cm:r2],[xd:r1,16,48]
cp32.na r1, [cm:r2],[xd:r1,16,48]
cp32 [cm:r2],[xd:r1,16,64]
cp32.na [cm:r2],[xd:r1,16,64]
cp32 r1, [cm:r2],[xd:r1,16,64]
cp32.na r1, [cm:r2],[xd:r1,16,64]
cp32 [cm:r2],[xd:r1,16,0, r2]
cp32.na [cm:r2],[xd:r1,16,0, r2]
cp32 r1, [cm:r2],[xd:r1,16,0,r2]
cp32.na r1, [cm:r2],[xd:r1,16,0,r2]
cp32 [cm:r2],[xd:r1,32,0, r2]
cp32.na [cm:r2],[xd:r1,32,0, r2]
cp32 r1, [cm:r2],[xd:r1,32,0, r2]
cp32.na r1, [cm:r2],[xd:r1,32,0, r2]
cp32 [cm:r2],[xd:r1,64,0, r2]
cp32.na [cm:r2],[xd:r1,64,0, r2]
cp32 r1, [cm:r2],[xd:r1,64,0, r2]
cp32.na r1, [cm:r2],[xd:r1,64,0, r2]
cp32 [cm:r2],[xd:r1,128,0, r2]
cp32.na [cm:r2],[xd:r1,128,0, r2]
cp32 r1, [cm:r2],[xd:r1,128,0, r2]
cp32.na r1, [cm:r2],[xd:r1,128,0, r2]
cp32 [cm:r2],[xd:r1,r2,r2]
cp32.na [cm:r2],[xd:r1,r2,r2]
cp32 r1, [cm:r2],[xd:r1,r2,r2]
cp32.na r1, [cm:r2],[xd:r1,r2,r2]
cp32 [cm:r2],[xd:r1,r2,r2,r2]
cp32.na [cm:r2],[xd:r1,r2,r2,r2]
cp32 r1, [cm:r2],[xd:r1,r2,r2,r2]
cp32.na r1, [cm:r2],[xd:r1,r2,r2,r2]
;cp16/32 cm to xa
cp16 [xa:r1],[cm:r2]
cp16.na [xa:r1],[cm:r2]
cp32 [xa:r1],[cm:r2]
cp32.na [xa:r1],[cm:r2]
cp32 [jid:r1],[cm:r2]
cp16 [sd:r1,0x20,0x10],[cm:r2]
cp16.na [sd:r1,0x20,0x10],[cm:r2]
cp16 [xd:r1,0x20,0x10],[cm:r2]
cp16.na [xd:r1,0x20,0x10],[cm:r2]
cp32 [sd:r1,0x20,0x10],[cm:r2]
cp32.na [sd:r1,0x20,0x10],[cm:r2]
cp32 [xd:r1,0x20,0x10],[cm:r2]
cp32.na [xd:r1,0x20,0x10],[cm:r2]
cp16 [sd:r1,0x20,0x10,r2],[cm:r2]
cp16.na [sd:r1,0x20,0x10,r2],[cm:r2]
cp16 [xd:r1,0x20,0x10,r2],[cm:r2]
cp16.na [xd:r1,0x20,0x10,r2],[cm:r2]
cp32 [sd:r1,0x20,0x10,r2],[cm:r2]
cp32.na [sd:r1,0x20,0x10,r2],[cm:r2]
cp32 [xd:r1,0x20,0x10,r2],[cm:r2]
cp32.na [xd:r1,0x20,0x10,r2],[cm:r2]
cp16 [sd:r1,r2,r2],[cm:r2]
cp16.na [sd:r1,r2,r2],[cm:r2]
cp16 [xd:r1,r2,r2],[cm:r2]
cp16.na [xd:r1,r2,r2],[cm:r2]
cp32 [sd:r1,r2,r2],[cm:r2]
cp32.na [sd:r1,r2,r2],[cm:r2]
cp32 [xd:r1,r2,r2],[cm:r2]
cp32.na [xd:r1,r2,r2],[cm:r2]
cp16 [sd:r1,r2,r2,r2],[cm:r2]
cp16.na [sd:r1,r2,r2,r2],[cm:r2]
cp16 [xd:r1,r2,r2,r2],[cm:r2]
cp16.na [xd:r1,r2,r2,r2],[cm:r2]
cp32 [sd:r1,r2,r2,r2],[cm:r2]
cp32.na [sd:r1,r2,r2,r2],[cm:r2]
cp32 [xd:r1,r2,r2,r2],[cm:r2]
cp32.na [xd:r1,r2,r2,r2],[cm:r2]
|
stsp/binutils-ia16
| 1,185
|
gas/testsuite/gas/arc/textinsn3op.s
|
# Insn 3op .extInstruction test
.extInstruction myinsn, 0x07, 0x30, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_3OP
myinsn r0,r1,r2
myinsn r26,fp,sp
myinsn ilink1,ilink2,blink
myinsn r0,r1,0
myinsn r0,0,r2
myinsn 0,r1,r2
myinsn r0,r1,-1
myinsn r0,-1,r2
myinsn r0,r1,255
myinsn r0,255,r2
myinsn r0,r1,-256
myinsn r0,-256,r2
myinsn r0,r1,256
myinsn r0,-257,r2
myinsn r0,256,256
myinsn r0,r1,foo
myinsn.al r0,r0,r2
myinsn.ra r3,r3,r5
myinsn.eq r6,r6,r8
myinsn.z r9,r9,r11
myinsn.ne r12,r12,r14
myinsn.nz r15,r15,r17
myinsn.pl r18,r18,r20
myinsn.p r21,r21,r23
myinsn.mi r24,r24,r26
myinsn.n r27,r27,r29
myinsn.cs r30,r30,r31
myinsn.c r3,r3,r3
myinsn.lo r3,r3,r8
myinsn.cc r3,r3,r4
myinsn.nc r4,r4,r4
myinsn.hs r4,r4,r7
myinsn.vs r4,r4,r5
myinsn.v r5,r5,r5
myinsn.vc r5,r5,r5
myinsn.nv r5,r5,r5
myinsn.gt r6,r6,r0
myinsn.ge r0,r0,0
myinsn.lt r1,r1,1
myinsn.hi r3,r3,3
myinsn.ls r4,r4,4
myinsn.pnz r5,r5,5
myinsn.f r0,r1,r2
myinsn.f r0,r1,1
myinsn.f r0,1,r2
myinsn.f 0,r1,r2
myinsn.f r0,r1,512
myinsn.f r0,512,r2
myinsn.eq.f r1,r1,r2
myinsn.ne.f r0,r0,0
myinsn.lt.f r2,r2,r2
myinsn.gt.f 0,1,2
myinsn.le.f 0,512,512
myinsn.ge.f 0,512,2
|
stsp/binutils-ia16
| 3,845
|
gas/testsuite/gas/arc/taux.s
|
lr r5, [lp_start]
lr r5, [lp_end]
lr r5, [identity]
lr r5, [debug]
lr r5, [pc]
lr r5, [status32]
lr r5, [ic_ivic]
lr r5, [ic_ctrl]
lr r5, [ic_ivil]
lr r5, [ic_ram_address]
lr r5, [ic_tag]
lr r5, [ic_wp]
lr r5, [ic_data]
lr r5, [count0]
lr r5, [control0]
lr r5, [limit0]
lr r5, [dc_ivdc]
lr r5, [dc_ctrl]
lr r5, [dc_ldl]
lr r5, [dc_ivdl]
lr r5, [dc_flsh]
lr r5, [dc_ram_addr]
lr r5, [dc_tag]
lr r5, [dc_wp]
lr r5, [dc_data]
lr r5, [dccm_base_build]
lr r5, [crc_build]
lr r5, [bta_link_build]
lr r5, [vbfdw_build]
lr r5, [ea_build]
lr r5, [dataspace]
lr r5, [memsubsys]
lr r5, [vecbase_ac_build]
lr r5, [p_base_addr]
lr r5, [data_uncached_build]
lr r5, [fp_build]
lr r5, [dpfp_build]
lr r5, [mpu_build]
lr r5, [rf_build]
lr r5, [mmu_build]
lr r5, [vecbase_build]
lr r5, [d_cache_build]
lr r5, [madi_build]
lr r5, [dccm_build]
lr r5, [timer_build]
lr r5, [ap_build]
lr r5, [i_cache_build]
lr r5, [iccm_build]
lr r5, [dspram_build]
lr r5, [mac_build]
lr r5, [multiply_build]
lr r5, [swap_build]
lr r5, [norm_build]
lr r5, [minmax_build]
lr r5, [barrel_build]
lr r5, [ax0]
lr r5, [ax1]
lr r5, [ax2]
lr r5, [ax3]
lr r5, [ay0]
lr r5, [ay1]
lr r5, [ay2]
lr r5, [ay3]
lr r5, [mx00]
lr r5, [mx01]
lr r5, [mx10]
lr r5, [mx11]
lr r5, [mx20]
lr r5, [mx21]
lr r5, [mx30]
lr r5, [mx31]
lr r5, [my00]
lr r5, [my01]
lr r5, [my10]
lr r5, [my11]
lr r5, [my20]
lr r5, [my21]
lr r5, [my30]
lr r5, [my31]
lr r5, [xyconfig]
lr r5, [burstsys]
lr r5, [burstxym]
lr r5, [burstsz]
lr r5, [burstval]
lr r5, [xylsbasex]
lr r5, [xylsbasey]
lr r5, [aux_xmaclw_h]
lr r5, [aux_xmaclw_l]
lr r5, [se_ctrl]
lr r5, [se_stat]
lr r5, [se_err]
lr r5, [se_eadr]
lr r5, [se_spc]
lr r5, [sdm_base]
lr r5, [scm_base]
lr r5, [se_dbg_ctrl]
lr r5, [se_dbg_data0]
lr r5, [se_dbg_data1]
lr r5, [se_dbg_data2]
lr r5, [se_dbg_data3]
lr r5, [se_watch]
lr r5, [bpu_build]
lr r5, [isa_config]
lr r5, [hwp_build]
lr r5, [pct_build]
lr r5, [cc_build]
lr r5, [pm_bcr]
lr r5, [scq_switch_build]
lr r5, [vraptor_build]
lr r5, [dma_config]
lr r5, [simd_config]
lr r5, [vlc_build]
lr r5, [simd_dma_build]
lr r5, [ifetch_queue_build]
lr r5, [smart_build]
lr r5, [count1]
lr r5, [control1]
lr r5, [limit1]
lr r5, [timer_xx]
lr r5, [aux_irq_hint]
lr r5, [ap_amv0]
lr r5, [ap_amm0]
lr r5, [ap_ac0]
lr r5, [ap_amv1]
lr r5, [ap_amm1]
lr r5, [ap_ac1]
lr r5, [ap_amv2]
lr r5, [ap_amm2]
lr r5, [ap_ac2]
lr r5, [ap_amv3]
lr r5, [ap_amm3]
lr r5, [ap_ac3]
lr r5, [ap_amv4]
lr r5, [ap_amm4]
lr r5, [ap_ac4]
lr r5, [ap_amv5]
lr r5, [ap_amm5]
lr r5, [ap_ac5]
lr r5, [ap_amv6]
lr r5, [ap_amm6]
lr r5, [ap_ac6]
lr r5, [ap_amv7]
lr r5, [ap_amm7]
lr r5, [ap_ac7]
lr r5, [fp_status]
lr r5, [aux_dpfp1l]
lr r5, [d1l]
lr r5, [aux_dpfp1h]
lr r5, [d1h]
lr r5, [d1l]
lr r5, [aux_dpfp2l]
lr r5, [d2l]
lr r5, [d1h]
lr r5, [aux_dpfp2h]
lr r5, [d2h]
lr r5, [d2l]
lr r5, [dpfp_status]
lr r5, [d2h]
lr r5, [eret]
lr r5, [erbta]
lr r5, [erstatus]
lr r5, [ecr]
lr r5, [efa]
lr r5, [mpuen]
lr r5, [icause1]
lr r5, [icause2]
lr r5, [aux_ienable]
lr r5, [aux_itrigger]
lr r5, [xpu]
lr r5, [bta]
lr r5, [aux_irq_pulse_cancel]
lr r5, [aux_irq_pending]
lr r5, [mpuic]
lr r5, [mpufa]
lr r5, [mpurdb0]
lr r5, [mpurdp0]
lr r5, [mpurdb1]
lr r5, [mpurdp1]
lr r5, [mpurdb2]
lr r5, [mpurdp2]
lr r5, [mpurdb3]
lr r5, [mpurdp3]
lr r5, [mpurdb4]
lr r5, [mpurdp4]
lr r5, [mpurdb5]
lr r5, [mpurdp5]
lr r5, [mpurdb6]
lr r5, [mpurdp6]
lr r5, [mpurdb7]
lr r5, [mpurdp7]
lr r5, [mpurdb8]
lr r5, [mpurdp8]
lr r5, [mpurdb9]
lr r5, [mpurdp9]
lr r5, [mpurdb10]
lr r5, [mpurdp10]
lr r5, [mpurdb11]
lr r5, [mpurdp11]
lr r5, [mpurdb12]
lr r5, [mpurdp12]
lr r5, [mpurdb13]
lr r5, [mpurdp13]
lr r5, [mpurdb14]
lr r5, [mpurdp14]
lr r5, [mpurdb15]
lr r5, [mpurdp15]
|
stsp/binutils-ia16
| 2,004
|
gas/testsuite/gas/arc/nps400-1.s
|
.text
movb r0, r0, r1, 4, 5, 6
movb r0, r0, r12, 4, 5, 6
movb r15, r15, r12, 4, 5, 6
movb.cl r0, r1, 4, 5, 6
movb.cl r0, r14, 4, 5, 6
movb.cl r13, r1, 4, 5, 6
movh r0, r0, 1234
movh r3, r3, 0xffff
movh.cl r0, 1234
movh.cl r3, 0xffff
/* movbi */
movbi r14, r14, 6, 8, 4
movbi.f r23, r23, 20, 11, 1
movbi.cl r30, 10, 18, 2
movbi.f.cl r6, 9, 0, 8
/* decode1 */
decode1 r0, r0, r2, 5, 11
decode1.f r0, r0, r2, 5, 11
decode1.cl r0, r2, 11
decode1.cl.f r0, r2, 18
/* fbset */
fbset r1, r1, r3, 3, 15
fbset.f r1, r1, r3, 3, 15
/* fbclear */
fbclr r2, r2, r12, 3, 15
fbclr.f r3, r3, r12, 3, 15
/* encode0 */
encode0 r2, r1, 18, 1
encode0.f r0, r0, 0, 32
/* encode1 */
encode1 r2, r1, 31, 1
encode1.f r0, r0, 0, 32
/* rflt */
rflt r10,r12,r20
rflt r0,0x12345678,r20
rflt r6,r7,0xffffffff
rflt r8,0xffffffff,0xffffffff
rflt 0,r14,r13
rflt 0,0xffffffff,r10
rflt 0,r12,0xffffffff
rflt r4,r5,0x1
rflt r3,0x12345678,0x2
rflt 0,r1,0x4
rflt 0,0xffffffff,0x1
.macro crc_test mnem
\mnem r1,r2,r3
\mnem r4,0xffffffff,r5
\mnem r6,r7,0xffffffff
\mnem r8,0xffffffff,0xffffffff
\mnem 0,r9,r10
\mnem 0,0xffffffff,r11
\mnem 0,r12,0xffffffff
\mnem r13,r14,0x3f
\mnem r15,0xffffffff,0x3f
\mnem 0,r16,0x3f
\mnem 0,0xffffffff,0x3f
.endm
/* crc16 */
crc_test crc16
crc_test crc16.r
/* crc32 */
crc_test crc32
crc_test crc32.r
|
stsp/binutils-ia16
| 1,338
|
gas/testsuite/gas/arc/ext3op.s
|
# 3 operand insn test
dsp_fp_div r0,r1,r2
dsp_fp_div gp,fp,sp
dsp_fp_div ilink,ilink,blink
dsp_fp_div r0,r1,0
dsp_fp_div r0,0,r2
dsp_fp_div 0,r1,r2
dsp_fp_div r0,r1,-1
dsp_fp_div r0,-1,r2
dsp_fp_div r0,r1,255
dsp_fp_div r0,255,r2
dsp_fp_div r0,r1,-256
dsp_fp_div r0,-256,r2
dsp_fp_div r1,r1,256
dsp_fp_div r0,r1,0x3F
dsp_fp_div r0,-257,r2
dsp_fp_div r0,256,256
dsp_fp_div r0,r1,foo
dsp_fp_div.al r0,r0,r2
dsp_fp_div.ra r3,r3,r5
dsp_fp_div.eq r6,r6,r8
dsp_fp_div.z r9,r9,r11
dsp_fp_div.ne r12,r12,r14
dsp_fp_div.nz r15,r15,r17
dsp_fp_div.pl r18,r18,r20
dsp_fp_div.p r21,r21,r23
dsp_fp_div.mi r24,r24,r26
dsp_fp_div.n r27,r27,r29
dsp_fp_div.cs r30,r30,r31
dsp_fp_div.c r3,r3,r3
dsp_fp_div.lo r3,r3,r8
dsp_fp_div.cc r3,r3,r4
dsp_fp_div.nc r4,r4,r4
dsp_fp_div.hs r4,r4,r7
dsp_fp_div.vs r4,r4,r5
dsp_fp_div.v r5,r5,r5
dsp_fp_div.vc r5,r5,r5
dsp_fp_div.nv r5,r5,r5
dsp_fp_div.gt r6,r6,r0
dsp_fp_div.ge r0,r0,0
dsp_fp_div.lt r1,r1,1
dsp_fp_div.hi r3,r3,3
dsp_fp_div.ls r4,r4,4
dsp_fp_div.pnz r5,r5,5
dsp_fp_div.f r0,r1,r2
dsp_fp_div.f r0,r1,1
dsp_fp_div.f r0,1,r2
dsp_fp_div.f 0,r1,r2
dsp_fp_div.f r0,r1,512
dsp_fp_div.f r0,512,r2
dsp_fp_div.eq.f r1,r1,r2
dsp_fp_div.ne.f r0,r0,0
dsp_fp_div.lt.f r2,r2,r2
dsp_fp_div.gt.f 0,1,2
dsp_fp_div.le.f 0,512,512
dsp_fp_div.ge.f 0,512,2
|
stsp/binutils-ia16
| 2,044
|
gas/testsuite/gas/arc/nps400-8.s
|
.text
;; bdalc / sbdalc
bdalc r0,[cm:r0],r0,r0
bdalc r1,[cm:r2],r2,r3
bdalc r0,[cm:r0],r0,0,1
bdalc r2,[cm:r3],r3,1,1
bdalc r3,[cm:r4],r4,1,8
sbdalc r0, r0, 0
sbdalc r3, r4, 1
;; bdfre / sbdfre
bdfre 0,[cm:r0],r0,r0
bdfre 0,[cm:r1],r1,r2
bdfre 0,[cm:r0],r0,1
bdfre 0,[cm:r2],r2,8
bdfre 0,[cm:r0],r0,0,1
bdfre 0,[cm:r6],r6,0,8
bdfre 0,[cm:r0],r0,1,1
bdfre 0,[cm:r6],r6,1,8
sbdfre 0, r0, r0
sbdfre 0, r1, r2
;; bdbgt
bdbgt 0,r0,r0
bdbgt 0,r4,r6
;; idxalc / sidxalc
idxalc r0,[cm:r0],r0,r0
idxalc r1,[cm:r2],r2,r3
idxalc r4,[cm:r5],r5,2
sidxalc r0,r0
sidxalc r4,r2
;; idxfre / sidxfre
idxfre 0,[cm:r0],r0,r0
idxfre 0,[cm:r1],r1,r2
idxfre 0,[cm:r0],r0,1
idxfre 0,[cm:r2],r2,8
sidxfre 0, r0, r0
sidxfre 0, r1, r2
;; idxbgt
idxbgt 0,r0,r0
idxbgt 0,r7,r8
;; efabgt
efabgt 0,0x0,r0
efabgt 0,0xffffffff,r3
efabgt 0,r0,0x0
efabgt 0,r4,0xffffffff
efabgt 0,r0,r0
efabgt 0,r7,r8
efabgt r0,0x0,r0
efabgt r4,0xffffffff,r6
efabgt r0,r0,0x0
efabgt r2,r3,0xffffffff
efabgt r0,r0,r0
efabgt r7,r8,r9
;; jobget
jobget 0,[cjid:r0]
jobget 0,[cjid:r6]
jobget.cl 0,[cjid:r0]
jobget.cl 0,[cjid:r6]
;; jobdn
jobdn 0,[cjid:r0],r0,r0
jobdn 0,[cjid:r2],r2,r4
jobdn 0,[cjid:r0],r0,0
jobdn 0,[cjid:r2],r2,15
;; jobalc / sjobalc
jobalc r0,[cm:r0],r0,r0
jobalc r1,[cm:r2],r2,r3
jobalc r0,[cm:r0],r0,1
jobalc r1,[cm:r2],r2,4
sjobalc r0,r0
sjobalc r6,r5
;; jobbgt
jobbgt r0,r0,r0
jobbgt r2,r5,r6
;; cnljob
cnljob 0
;; qseq
qseq r0,[r0]
qseq r2,[r4]
|
stsp/binutils-ia16
| 6,388
|
gas/testsuite/gas/arc/nps400-6.s
|
.text
.macro addb_like_test mnem
\mnem r0,r0,r1,0,8,2
\mnem\().f r0,r0,r1,16,8,2
\mnem\().f.sx r0,r0,r1,8,24,6
.endm
.macro andb_like_test mnem, size
\mnem r0,r0,r1,0,8,\size
\mnem\().f r0,r0,r1,16,8,\size
.endm
.macro notb_like_test mnem
\mnem r0,r1,0,8
\mnem\().f r0,r1,16,16
.endm
.macro div_like_test mnem
\mnem r0,r0,r2,8,8
\mnem\().f r0,r0,0xf,8
.endm
.macro qcmp_test mnem
\mnem r2,r2,r0,8,8,0,1,3
\mnem r2,r2,r0,8,8,1,1
\mnem r2,r2,r0,8,8,1
\mnem r2,r2,r0,8,8
.endm
.macro calcsxd_test mnem
\mnem\() r0, r0, r0, 1
\mnem\().f r1, r1, r0, 2
\mnem\() r2, r2, r3, 4
\mnem\().f r0, r0, r0, 8
\mnem\() r3, r3, r0, 16
\mnem\().f r0, r0, r0, 32
\mnem\() r0, r0, r1, 64
\mnem\().f r2, r2, r0, 128
\mnem\() r1, r1, r2, 256
.endm
.macro calcbsxdkey_test mnem
\mnem\() r0, r0, r0
\mnem\().f r1, r1, r0
\mnem\() r1, r1, r2
\mnem\().f r3, r3, r2
.endm
.macro mxb_like_test mnem
\mnem\() r0, r1, 0, 1, 2
\mnem\() r0, r1, 7, 8, 7
\mnem\() r0, r1, 7, 7, 8
\mnem\().s r2, r3, 1, 4, 3, 2
\mnem\().s r2, r3, 7, 8, 7, 7
\mnem\().s r2, r3, 7, 7, 8, 7
\mnem\().s r2, r3, 7, 8, 7, 8
.endm
.macro addsubl_test mnem
\mnem\() r0, r0, 0
\mnem\() r2, r2, 32767
\mnem\() r5, r5, -32768
\mnem\().f r10, r10, 0
\mnem\().f r11, r11, 1
\mnem\().f r12, r12, -1
.endm
.macro andorxorl_test mnem
\mnem\() r0, r0, 0
\mnem\() r1, r1, 1
\mnem\() r2, r2, 65535
\mnem\().f r10, r10, 0
\mnem\().f r11, r11, 1
\mnem\().f r12, r12, 65535
.endm
.macro andorab_test mnem
\mnem\() r0, r0, 0, 1
\mnem\() r1, r2, 15, 16
\mnem\().f r2, r3, 0, 1
\mnem\().f r12, r13, 16, 16
\mnem\() r0, r0, r0, 0, 1
\mnem\() r1, r1, r2, 15, 16
\mnem\().f r2, r2, r3, 0, 1
\mnem\().f r12, r12, r13, 16, 16
.endm
addb_like_test addb
addb_like_test subb
addb_like_test adcb
addb_like_test sbcb
andb_like_test andb, 2
andb_like_test xorb, 2
andb_like_test orb, 2
andb_like_test shlb, 2
andb_like_test shrb, 2
andb_like_test fxorb, 8
andb_like_test wxorb, 16
notb_like_test notb
notb_like_test cntbb
div_like_test div
div_like_test mod
div_like_test divm
qcmp_test qcmp.ar
qcmp_test qcmp.al
calcsxd_test calcsd
calcsxd_test calcxd
calcbsxdkey_test calcbsd
calcbsxdkey_test calcbxd
calcbsxdkey_test calckey
calcbsxdkey_test calcxkey
mxb_like_test mxb
mxb_like_test imxb
addsubl_test addl
addsubl_test subl
andorxorl_test andl
andorxorl_test orl
andorxorl_test xorl
andorab_test andab
andorab_test orab
lbdsize r0, r1
lbdsize r2, r3
lbdsize.f r0, r1
lbdsize.f r2, r3
bdlen r0, r1, 1
bdlen r1, r3, 256
bdlen r1, r2, 240
bdlen r12, r13
bdlen.f r0, r1, 1
bdlen.f r1, r3, 256
bdlen.f r12, r13
.macro csma_like_test mnem
\mnem\() r10,r12,r20
\mnem\() r0,0x12345678,r20
\mnem\() r6,r7,0xffffffff
\mnem\() r8,0xffffffff,0xffffffff
\mnem\() 0,r14,r13
\mnem\() 0,0xffffffff,r10
\mnem\() 0,r12,0xffffffff
\mnem\() r4,r5,0x1
\mnem\() r3,0x12345678,0x2
\mnem\() 0,r1,0x4
\mnem\() 0,0xffffffff,0x1
.endm
csma_like_test csma
csma_like_test csms
csma_like_test cbba
csma_like_test cbba.f
csma_like_test tr
csma_like_test tr.f
csma_like_test utf8
csma_like_test utf8.f
csma_like_test addf
csma_like_test addf.f
.macro zncv_test mnem
\mnem\() r10,r12,r20
\mnem\() r0,0x12345678,r20
\mnem\() r6,r7,0xffffffff
\mnem\() r8,0xffffffff,0xffffffff
\mnem\() 0,r14,r13
\mnem\() 0,0xffffffff,r10
\mnem\() 0,r12,0xffffffff
\mnem\() r4,r5,0x1
\mnem\() r3,0x12345678,0x2
\mnem\() 0,r1,0x4
\mnem\() 0,0xffffffff,0x1
\mnem\() r1,r1,-1
\mnem\() 0,0xffffffff,-1
.endm
zncv_test zncv.rd
zncv_test zncv.wr
hofs r1, r2, r3
hofs.f r4, r5, r6
hofs r7, r8, 240, 0
hofs.f r7, r8, 0, 1
hash r1, r2, r3, 1, 0, 0, 0
hash r12, r13, r14, 32, 7, 1, 1
.macro hash_p_test mnem
\mnem\() r1, r2, r3, 1, 1, 0, 0
\mnem\() r12, r13, r14, 32, 8, 3, 1
.endm
hash_p_test hash.p0
hash_p_test hash.p1
hash_p_test hash.p2
hash_p_test hash.p3
e4by r0,r1,r2,0,0,0,4
e4by r7,r12,r13,1,2,3,4
e4by r20,r12,r13,7,7,7,7
.macro ldbit_test mnem
\mnem\() r0,[r1]
\mnem\() r0,[r1,1]
\mnem\() r1,[r2,-1]
\mnem\() r3,[0xffffffff,1]
\mnem\() r4,[0x12345678]
\mnem\() r5,[r6,r7]
\mnem\() r8,[r9,0xfeffffff]
\mnem\() r10,[0xffffffff,r11]
.endm
ldbit_test ldbit.di
ldbit_test ldbit.di.cl
ldbit_test ldbit.x2.di
ldbit_test ldbit.x2.di.cl
ldbit_test ldbit.x4.di
ldbit_test ldbit.x4.di.cl
|
stsp/binutils-ia16
| 1,633
|
gas/testsuite/gas/arc/dsp.s
|
#Test if disassembler correctly prints DSP instructions.
vmac2hnfr r0,r2,r4
abssh r0,r2
aslacc r0
aslsacc r0
asrsr r0,r2,r4
cbflyhf0r r0,r2,r4
cbflyhf1r r0,r2
cmacchfr r0,r2,r4
cmacchnfr r0,r2,r4
cmachfr r0,r2,r4
cmachnfr r0,r2,r4
cmpychfr r0,r2,r4
cmpychnfr r0,r2,r4
cmpyhfmr r0,r2,r4
cmpyhfr r0,r2,r4
cmpyhnfr r0,r2,r4
divacc r0
dmachbl r0,r2,r4
dmachbm r0,r2,r4
dmachf r0,r2,r4
dmachfr r0,r2,r4
dmpyhbl r0,r2,r4
dmpyhbm r0,r2,r4
dmpyhf r0,r2,r4
dmpyhfr r0,r2,r4
dmpyhwf r0,r2,r4
flagacc r0
getacc r0,r2
macf r0,r2,r4
macfr r0,r2,r4
macwhfm r0,r2,r4
macwhfmr r0,r2,r4
macwhl r0,r2,r4
macwhul r0,r2,r4
mpyf r0,r2,r4
mpyfr r0,r2,r4
mpywhfl r0,r2,r4
mpywhflr r0,r2,r4
mpywhfm r0,r2,r4
mpywhfmr r0,r2,r4
mpywhl r0,r2,r4
mpywhul r0,r2,r4
msubdf r0,r2,r4
msubf r0,r2,r4
msubfr r0,r2,r4
negsh r0,r2
normacc r0,r2
rndh r0,r2
sath r0,r2
setacc r0,r2,r4
sqrtacc r0
vabs2h r0,r2
vabss2h r0,r2
vadd4b r0,r2,r4
vadds2h r0,r2,r4
vaddsubs2h r0,r2,r4
valgn2h r0,r2,r4
vasl2h r0,r2,r4
vasls2h r0,r2,r4
vasr2h r0,r2,r4
vasrs2h r0,r2,r4
vasrsr2h r0,r2,r4
vext2bhl r0,r2
vext2bhm r0,r2
vlsr2h r0,r2,r4
vmac2h r0,r2,r4
vmac2hf r0,r2,r4
vmac2hfr r0,r2,r4
vmac2hu r0,r2,r4
vmax2h r0,r2,r4
vmin2h r0,r2,r4
vmpy2h r0,r2,r4
vmpy2hf r0,r2,r4
vmpy2hfr r0,r2,r4
vmpy2hu r0,r2,r4
vmpy2hwf r0,r2,r4
vmsub2hf r0,r2,r4
vmsub2hfr r0,r2,r4
vmsub2hnfr r0,r2,r4
vneg2h r0,r2
vnegs2h r0,r2
vnorm2h r0,r2
vrep2hl r0,r2
vrep2hm r0,r2
vsext2bhl r0,r2
vsext2bhm r0,r2
vsub4b r0,r2,r4
vsubadds2h r0,r2,r4
vsubs2h r0,r2,r4
|
stsp/binutils-ia16
| 1,600
|
gas/testsuite/gas/loongarch/4opt_op.s
|
fmadd.s $f0,$f1,$f2,$f3
fmadd.d $f0,$f1,$f2,$f3
fmsub.s $f0,$f1,$f2,$f3
fmsub.d $f0,$f1,$f2,$f3
fnmadd.s $f0,$f1,$f2,$f3
fnmadd.d $f0,$f1,$f2,$f3
fnmsub.s $f0,$f1,$f2,$f3
fnmsub.d $f0,$f1,$f2,$f3
fcmp.caf.s $fcc0,$f1,$f2
fcmp.saf.s $fcc0,$f1,$f2
fcmp.clt.s $fcc0,$f1,$f2
fcmp.slt.s $fcc0,$f1,$f2
fcmp.sgt.s $fcc0,$f2,$f1
fcmp.ceq.s $fcc0,$f1,$f2
fcmp.seq.s $fcc0,$f1,$f2
fcmp.cle.s $fcc0,$f1,$f2
fcmp.sle.s $fcc0,$f1,$f2
fcmp.sge.s $fcc0,$f2,$f1
fcmp.cun.s $fcc0,$f1,$f2
fcmp.sun.s $fcc0,$f1,$f2
fcmp.cult.s $fcc0,$f1,$f2
fcmp.cugt.s $fcc0,$f2,$f1
fcmp.sult.s $fcc0,$f1,$f2
fcmp.cueq.s $fcc0,$f1,$f2
fcmp.sueq.s $fcc0,$f1,$f2
fcmp.cule.s $fcc0,$f1,$f2
fcmp.cuge.s $fcc0,$f2,$f1
fcmp.sule.s $fcc0,$f1,$f2
fcmp.cne.s $fcc0,$f1,$f2
fcmp.sne.s $fcc0,$f1,$f2
fcmp.cor.s $fcc0,$f1,$f2
fcmp.sor.s $fcc0,$f1,$f2
fcmp.cune.s $fcc0,$f1,$f2
fcmp.sune.s $fcc0,$f1,$f2
fcmp.caf.d $fcc0,$f1,$f2
fcmp.saf.d $fcc0,$f1,$f2
fcmp.clt.d $fcc0,$f1,$f2
fcmp.slt.d $fcc0,$f1,$f2
fcmp.sgt.d $fcc0,$f2,$f1
fcmp.ceq.d $fcc0,$f1,$f2
fcmp.seq.d $fcc0,$f1,$f2
fcmp.cle.d $fcc0,$f1,$f2
fcmp.sle.d $fcc0,$f1,$f2
fcmp.sge.d $fcc0,$f2,$f1
fcmp.cun.d $fcc0,$f1,$f2
fcmp.sun.d $fcc0,$f1,$f2
fcmp.cult.d $fcc0,$f1,$f2
fcmp.cugt.d $fcc0,$f2,$f1
fcmp.sult.d $fcc0,$f1,$f2
fcmp.cueq.d $fcc0,$f1,$f2
fcmp.sueq.d $fcc0,$f1,$f2
fcmp.cule.d $fcc0,$f1,$f2
fcmp.cuge.d $fcc0,$f2,$f1
fcmp.sule.d $fcc0,$f1,$f2
fcmp.cne.d $fcc0,$f1,$f2
fcmp.sne.d $fcc0,$f1,$f2
fcmp.cor.d $fcc0,$f1,$f2
fcmp.sor.d $fcc0,$f1,$f2
fcmp.cune.d $fcc0,$f1,$f2
fcmp.sune.d $fcc0,$f1,$f2
fsel $f0,$f1,$f2,$fcc0
|
stsp/binutils-ia16
| 1,496
|
gas/testsuite/gas/loongarch/float_op.s
|
fadd.s $f0,$f1,$f2
fadd.d $f0,$f1,$f2
fsub.s $f0,$f1,$f2
fsub.d $f0,$f1,$f2
fmul.s $f0,$f1,$f2
fmul.d $f0,$f1,$f2
fdiv.s $f0,$f1,$f2
fdiv.d $f0,$f1,$f2
fmax.s $f0,$f1,$f2
fmax.d $f0,$f1,$f2
fmin.s $f0,$f1,$f2
fmin.d $f0,$f1,$f2
fmaxa.s $f0,$f1,$f2
fmaxa.d $f0,$f1,$f2
fmina.s $f0,$f1,$f2
fmina.d $f0,$f1,$f2
fscaleb.s $f0,$f1,$f2
fscaleb.d $f0,$f1,$f2
fcopysign.s $f0,$f1,$f2
fcopysign.d $f0,$f1,$f2
fabs.s $f0,$f1
fabs.d $f0,$f1
fneg.s $f0,$f1
fneg.d $f0,$f1
flogb.s $f0,$f1
flogb.d $f0,$f1
fclass.s $f0,$f1
fclass.d $f0,$f1
fsqrt.s $f0,$f1
fsqrt.d $f0,$f1
frecip.s $f0,$f1
frecip.d $f0,$f1
frsqrt.s $f0,$f1
frsqrt.d $f0,$f1
fmov.s $f0,$f1
fmov.d $f0,$f1
movgr2fr.w $f0,$r5
movgr2fr.d $f0,$r5
movgr2frh.w $f0,$r5
movfr2gr.s $r4,$f1
movfr2gr.d $r4,$f1
movfrh2gr.s $r4,$f1
movgr2fcsr $r4,$r5
movfcsr2gr $r4,$r5
movfr2cf $fcc0,$f1
movcf2fr $f0,$fcc5
movgr2cf $fcc0,$r5
movcf2gr $r4,$fcc5
fcvt.s.d $f0,$f1
fcvt.d.s $f0,$f1
ftintrm.w.s $f0,$f1
ftintrm.w.d $f0,$f1
ftintrm.l.s $f0,$f1
ftintrm.l.d $f0,$f1
ftintrp.w.s $f0,$f1
ftintrp.w.d $f0,$f1
ftintrp.l.s $f0,$f1
ftintrp.l.d $f0,$f1
ftintrz.w.s $f0,$f1
ftintrz.w.d $f0,$f1
ftintrz.l.s $f0,$f1
ftintrz.l.d $f0,$f1
ftintrne.w.s $f0,$f1
ftintrne.w.d $f0,$f1
ftintrne.l.s $f0,$f1
ftintrne.l.d $f0,$f1
ftint.w.s $f0,$f1
ftint.w.d $f0,$f1
ftint.l.s $f0,$f1
ftint.l.d $f0,$f1
ffint.s.w $f0,$f1
ffint.s.l $f0,$f1
ffint.d.w $f0,$f1
ffint.d.l $f0,$f1
frint.s $f0,$f1
frint.d $f0,$f1
|
stsp/binutils-ia16
| 3,572
|
gas/testsuite/gas/loongarch/load_store_op.s
|
ll.w $r4,$r5,0
ll.w $r4,$r5,0x3ffc
sc.w $r4,$r5,0
sc.w $r4,$r5,0x3ffc
ll.d $r4,$r5,0
ll.d $r4,$r5,0x3ffc
sc.d $r4,$r5,0
sc.d $r4,$r5,0x3ffc
ldptr.w $r4,$r5,0
ldptr.w $r4,$r5,0x3ffc
stptr.w $r4,$r5,0
stptr.w $r4,$r5,0x3ffc
ldptr.d $r4,$r5,0
ldptr.d $r4,$r5,0x3ffc
stptr.d $r4,$r5,0
stptr.d $r4,$r5,0x3ffc
ld.b $r4,$r5,0
ld.b $r4,$r5,0x7ff
ld.b $r4,$r5,-0x7ff
ld.h $r4,$r5,0
ld.h $r4,$r5,0x7ff
ld.h $r4,$r5,-0x7ff
ld.w $r4,$r5,0
ld.w $r4,$r5,0x7ff
ld.w $r4,$r5,-0x7ff
ld.d $r4,$r5,0
ld.d $r4,$r5,0x7ff
ld.d $r4,$r5,-0x7ff
st.b $r4,$r5,0
st.b $r4,$r5,0x7ff
st.b $r4,$r5,-0x7ff
st.h $r4,$r5,0
st.h $r4,$r5,0x7ff
st.h $r4,$r5,-0x7ff
st.w $r4,$r5,0
st.w $r4,$r5,0x7ff
st.w $r4,$r5,-0x7ff
st.d $r4,$r5,0
st.d $r4,$r5,0x7ff
st.d $r4,$r5,-0x7ff
ld.bu $r4,$r5,0
ld.bu $r4,$r5,0x7ff
ld.bu $r4,$r5,-0x7ff
ld.hu $r4,$r5,0
ld.hu $r4,$r5,0x7ff
ld.hu $r4,$r5,-0x7ff
ld.wu $r4,$r5,0
ld.wu $r4,$r5,0x7ff
ld.wu $r4,$r5,-0x7ff
preld 0,$r5,0
preld 31,$r5,0x7ff
preld 31,$r5,-0x7ff
fld.s $f0,$r5,0
fld.s $f0,$r5,0x7ff
fld.s $f0,$r5,-0x7ff
fst.s $f0,$r5,0
fst.s $f0,$r5,0x7ff
fst.s $f0,$r5,-0x7ff
fld.d $f0,$r5,0
fld.d $f0,$r5,0x7ff
fld.d $f0,$r5,-0x7ff
fst.d $f0,$r5,0
fst.d $f0,$r5,0x7ff
fst.d $f0,$r5,-0x7ff
ldx.b $r4,$r5,$r6
ldx.h $r4,$r5,$r6
ldx.w $r4,$r5,$r6
ldx.d $r4,$r5,$r6
stx.b $r4,$r5,$r6
stx.h $r4,$r5,$r6
stx.w $r4,$r5,$r6
stx.d $r4,$r5,$r6
ldx.bu $r4,$r5,$r6
ldx.hu $r4,$r5,$r6
ldx.wu $r4,$r5,$r6
preldx 0,$r5,$r6
preldx 31,$r5,$r6
dbar 0
dbar 0x7fff
ibar 0
ibar 0x7fff
amswap.w $r4,$r5,$r6,0
amswap.w $r4,$r6,$r5
amswap.d $r4,$r5,$r6,0
amswap.d $r4,$r6,$r5
amadd.w $r4,$r5,$r6,0
amadd.w $r4,$r6,$r5
amadd.d $r4,$r5,$r6,0
amadd.d $r4,$r6,$r5
amand.w $r4,$r5,$r6,0
amand.w $r4,$r6,$r5
amand.d $r4,$r5,$r6,0
amand.d $r4,$r6,$r5
amor.w $r4,$r5,$r6,0
amor.w $r4,$r6,$r5
amor.d $r4,$r5,$r6,0
amor.d $r4,$r6,$r5
amxor.w $r4,$r5,$r6,0
amxor.w $r4,$r6,$r5
amxor.d $r4,$r5,$r6,0
amxor.d $r4,$r6,$r5
ammax.w $r4,$r5,$r6,0
ammax.w $r4,$r6,$r5
ammax.d $r4,$r5,$r6,0
ammax.d $r4,$r6,$r5
ammin.w $r4,$r5,$r6,0
ammin.w $r4,$r6,$r5
ammin.d $r4,$r5,$r6,0
ammin.d $r4,$r6,$r5
ammax.wu $r4,$r5,$r6,0
ammax.wu $r4,$r6,$r5
ammax.du $r4,$r5,$r6,0
ammax.du $r4,$r6,$r5
ammin.wu $r4,$r5,$r6,0
ammin.wu $r4,$r6,$r5
ammin.du $r4,$r5,$r6,0
ammin.du $r4,$r6,$r5
amswap_db.w $r4,$r5,$r6,0
amswap_db.w $r4,$r6,$r5
amswap_db.d $r4,$r5,$r6,0
amswap_db.d $r4,$r6,$r5
amadd_db.w $r4,$r5,$r6,0
amadd_db.w $r4,$r6,$r5
amadd_db.d $r4,$r5,$r6,0
amadd_db.d $r4,$r6,$r5
amand_db.w $r4,$r5,$r6,0
amand_db.w $r4,$r6,$r5
amand_db.d $r4,$r5,$r6,0
amand_db.d $r4,$r6,$r5
amor_db.w $r4,$r5,$r6,0
amor_db.w $r4,$r6,$r5
amor_db.d $r4,$r5,$r6,0
amor_db.d $r4,$r6,$r5
amxor_db.w $r4,$r5,$r6,0
amxor_db.w $r4,$r6,$r5
amxor_db.d $r4,$r5,$r6,0
amxor_db.d $r4,$r6,$r5
ammax_db.w $r4,$r5,$r6,0
ammax_db.w $r4,$r6,$r5
ammax_db.d $r4,$r5,$r6,0
ammax_db.d $r4,$r6,$r5
ammin_db.w $r4,$r5,$r6,0
ammin_db.w $r4,$r6,$r5
ammin_db.d $r4,$r5,$r6,0
ammin_db.d $r4,$r6,$r5
ammax_db.wu $r4,$r5,$r6,0
ammax_db.wu $r4,$r6,$r5
ammax_db.du $r4,$r5,$r6,0
ammax_db.du $r4,$r6,$r5
ammin_db.wu $r4,$r5,$r6,0
ammin_db.wu $r4,$r6,$r5
ammin_db.du $r4,$r5,$r6,0
ammin_db.du $r4,$r6,$r5
ldgt.b $r4,$r5,$r6
ldgt.h $r4,$r5,$r6
ldgt.w $r4,$r5,$r6
ldgt.d $r4,$r5,$r6
ldle.b $r4,$r5,$r6
ldle.h $r4,$r5,$r6
ldle.w $r4,$r5,$r6
ldle.d $r4,$r5,$r6
stgt.b $r4,$r5,$r6
stgt.h $r4,$r5,$r6
stgt.w $r4,$r5,$r6
stgt.d $r4,$r5,$r6
stle.b $r4,$r5,$r6
stle.h $r4,$r5,$r6
stle.w $r4,$r5,$r6
stle.d $r4,$r5,$r6
|
stsp/binutils-ia16
| 2,451
|
gas/testsuite/gas/loongarch/fix_op.s
|
clo.w $r4,$r5
clz.w $r4,$r5
cto.w $r4,$r5
ctz.w $r4,$r5
clo.d $r4,$r5
clz.d $r4,$r5
cto.d $r4,$r5
ctz.d $r4,$r5
revb.2h $r4,$r5
revb.4h $r4,$r5
revb.2w $r4,$r5
revb.d $r4,$r5
revh.2w $r4,$r5
revh.d $r4,$r5
bitrev.4b $r4,$r5
bitrev.8b $r4,$r5
bitrev.w $r4,$r5
bitrev.d $r4,$r5
ext.w.h $r4,$r5
ext.w.b $r4,$r5
move $r4,$r5
rdtimel.w $r4,$r5
rdtimeh.w $r4,$r5
rdtime.d $r4,$r5
cpucfg $r4,$r5
asrtle.d $r5,$r6
asrtgt.d $r5,$r6
alsl.w $r4,$r5,$r6,1
alsl.w $r4,$r5,$r6,4
alsl.wu $r4,$r5,$r6,1
alsl.wu $r4,$r5,$r6,4
bytepick.w $r4,$r5,$r6,0
bytepick.w $r4,$r5,$r6,3
bytepick.d $r4,$r5,$r6,0
bytepick.d $r4,$r5,$r6,7
add.w $r4,$r5,$r6
add.d $r4,$r5,$r6
sub.w $r4,$r5,$r6
sub.d $r4,$r5,$r6
slt $r4,$r5,$r6
sltu $r4,$r5,$r6
maskeqz $r4,$r5,$r6
masknez $r4,$r5,$r6
nor $r4,$r5,$r6
and $r4,$r5,$r6
or $r4,$r5,$r6
xor $r4,$r5,$r6
orn $r4,$r5,$r6
andn $r4,$r5,$r6
sll.w $r4,$r5,$r6
srl.w $r4,$r5,$r6
sra.w $r4,$r5,$r6
sll.d $r4,$r5,$r6
srl.d $r4,$r5,$r6
sra.d $r4,$r5,$r6
rotr.w $r4,$r5,$r6
rotr.d $r4,$r5,$r6
mul.w $r4,$r5,$r6
mulh.w $r4,$r5,$r6
mulh.wu $r4,$r5,$r6
mul.d $r4,$r5,$r6
mulh.d $r4,$r5,$r6
mulh.du $r4,$r5,$r6
mulw.d.w $r4,$r5,$r6
mulw.d.wu $r4,$r5,$r6
div.w $r4,$r5,$r6
mod.w $r4,$r5,$r6
div.wu $r4,$r5,$r6
mod.wu $r4,$r5,$r6
div.d $r4,$r5,$r6
mod.d $r4,$r5,$r6
div.du $r4,$r5,$r6
mod.du $r4,$r5,$r6
crc.w.b.w $r4,$r5,$r6
crc.w.h.w $r4,$r5,$r6
crc.w.w.w $r4,$r5,$r6
crc.w.d.w $r4,$r5,$r6
crcc.w.b.w $r4,$r5,$r6
crcc.w.h.w $r4,$r5,$r6
crcc.w.w.w $r4,$r5,$r6
crcc.w.d.w $r4,$r5,$r6
break 0
break 0x7fff
dbcl 0
dbcl 0x7fff
alsl.d $r4,$r5,$r6,1
alsl.d $r4,$r5,$r6,4
slli.w $r4,$r5,0
slli.w $r4,$r5,1
slli.w $r4,$r5,0x1f
slli.d $r4,$r5,0
slli.d $r4,$r5,1
slli.d $r4,$r5,0x3f
srli.w $r4,$r5,0
srli.w $r4,$r5,1
srli.w $r4,$r5,0x1f
srli.d $r4,$r5,0
srli.d $r4,$r5,1
srli.d $r4,$r5,0x3f
srai.w $r4,$r5,0
srai.w $r4,$r5,1
srai.w $r4,$r5,0x1f
srai.d $r4,$r5,0
srai.d $r4,$r5,1
srai.d $r4,$r5,0x3f
rotri.w $r4,$r5,0
rotri.w $r4,$r5,1
rotri.w $r4,$r5,0x1f
rotri.d $r4,$r5,0
rotri.d $r4,$r5,1
rotri.d $r4,$r5,0x3f
bstrins.w $r4,$r5,0,0
bstrins.w $r4,$r5,2,1
bstrins.w $r4,$r5,31,0
bstrpick.w $r4,$r5,0,0
bstrpick.w $r4,$r5,2,1
bstrpick.w $r4,$r5,31,0
bstrins.d $r4,$r5,0,0
bstrins.d $r4,$r5,31,1
bstrins.d $r4,$r5,32,0
bstrins.d $r4,$r5,63,0
bstrpick.d $r4,$r5,0,0
bstrpick.d $r4,$r5,31,1
bstrpick.d $r4,$r5,32,0
bstrpick.d $r4,$r5,63,0
|
stsp/binutils-ia16
| 2,865
|
gas/testsuite/gas/tic6x/insns-c674x-reloc.s
|
# Test C674x instructions generating relocations.
.data
w1:
.word 1
w2:
.word 2
.text
.nocmp
.globl ext1
.globl ext2
.globl ext3
.globl a1
.globl b1
.globl f
f:
addab .D1X b14,ext1,a5
addab .D2 b15,(ext2+7),b7
addab .D1X b14,(a1),a20
addab .D2 b14,(b1),b30
addab .D1X b14,w2-w1,a15
addab .D2 b14,w4-w3,b16
addah .D1X b14,ext1,a5
addah .D2 b15,(ext2+6),b7
addah .D1X b14,(a1),a20
addah .D2 b14,(b1),b30
addah .D1X b14,w2-w1,a15
addah .D2 b14,w4-w3,b16
addaw .D1X b14,ext1,a5
addaw .D2 b15,(ext2+8),b7
addaw .D1X b14,(a1),a20
addaw .D2 b14,(b1),b30
addaw .D1X b14,w2-w1,a15
addaw .D2 b14,w4-w3,b16
addaw .D1X b14,$DSBT_INDEX(__c6xabi_DSBT_BASE),a5
addaw .D2 b15,$GOT(ext2)+8,b7
addk .S1 ext1+3,a1
addk .S2 $dpr_byte(ext2)+5,b3
addk .S1 w2-w1,a4
addk .S2 w3-w4,b5
mvk .S1 ext1+3,a1
mvk .S2 $dpr_byte(ext2)+5,b3
mvk .S1 w2-w1,a4
mvk .S2 w3-w4,b5
mvkh .S1 ext3+1,a1
mvkh .S2 $DPR_GOT(ext2)+2,b2
mvkh .S1 $DPR_BYTE(ext1)+3,a3
mvkh .S2 $DPR_HWORD(ext3)+4,b4
mvkh .S1 $DPR_WORD(ext2)+5,a5
mvkh .S2 s1-s0,b6
mvklh .S1 ext3+1,a1
mvklh .S2 $DPR_GOT(ext2)+2,b2
mvklh .S1 $DPR_BYTE(ext1)+3,a3
mvklh .S2 $DPR_HWORD(ext3)+4,b4
mvklh .S1 $DPR_WORD(ext2)+5,a5
mvklh .S2 s1-s0,b6
mvkl .S1 ext3+1,a1
mvkl .S2 $DPR_GOT(ext2)+2,b2
mvkl .S1 $DPR_BYTE(ext1)+3,a3
mvkl .S2 $DPR_HWORD(ext3)+4,b4
mvkl .S1 $DPR_WORD(ext2)+5,a5
mvkl .S2 s1-s0,b6
ldb .D2T2 *+b14(ext1),b1
ldb .D2T1 *+b15(ext2+7),a1
ldb .D2T2 *+b15(b1),b1
ldb .D2T1 *+b14(a1),a1
ldb .D2T2 *+b14(w2-w1),b1
ldb .D2T1 *+b14(w4-w3),a1
ldbu .D2T2 *+b14(ext1),b1
ldbu .D2T1 *+b15(ext2+7),a1
ldbu .D2T2 *+b15(b1),b1
ldbu .D2T1 *+b14(a1),a1
ldbu .D2T2 *+b14(w2-w1),b1
ldbu .D2T1 *+b14(w4-w3),a1
ldh .D2T2 *+b14(ext1),b1
ldh .D2T1 *+b15(ext2+6),a1
ldh .D2T2 *+b15(b1),b1
ldh .D2T1 *+b14(a1),a1
ldh .D2T2 *+b14(w2-w1),b1
ldh .D2T1 *+b14(w4-w3),a1
ldhu .D2T2 *+b14(ext1),b1
ldhu .D2T1 *+b15(ext2+6),a1
ldhu .D2T2 *+b15(b1),b1
ldhu .D2T1 *+b14(a1),a1
ldhu .D2T2 *+b14(w2-w1),b1
ldhu .D2T1 *+b14(w4-w3),a1
ldw .D2T2 *+b14(ext1),b1
ldw .D2T1 *+b15(ext2+4),a1
ldw .D2T2 *+b15(b1),b1
ldw .D2T1 *+b14(a1),a1
ldw .D2T2 *+b14(w2-w1),b1
ldw .D2T1 *+b14(w4-w3),a1
ldw .D2T2 *+b14($DSBT_INDEX(__c6xabi_DSBT_BASE)),b1
ldw .D2T1 *+b14($GOT(ext2)+4),a1
stb .D2T2 b1,*+b14(ext1)
stb .D2T1 a1,*+b15(ext2+7)
stb .D2T2 b1,*+b15(b1)
stb .D2T1 a1,*+b14(a1)
stb .D2T2 b1,*+b14(w2-w1)
stb .D2T1 a1,*+b14(w4-w3)
sth .D2T2 b1,*+b14(ext1)
sth .D2T1 a1,*+b15(ext2+6)
sth .D2T2 b1,*+b15(b1)
sth .D2T1 a1,*+b14(a1)
sth .D2T2 b1,*+b14(w2-w1)
sth .D2T1 a1,*+b14(w4-w3)
stw .D2T2 b1,*+b14(ext1)
stw .D2T1 a1,*+b15(ext2+4)
stw .D2T2 b1,*+b15(b1)
stw .D2T1 a1,*+b14(a1)
stw .D2T2 b1,*+b14(w2-w1)
stw .D2T1 a1,*+b14(w4-w3)
stw .D2T2 b1,*+b14($DSBT_INDEX(__c6xabi_DSBT_BASE))
stw .D2T1 a1,*+b14($GOT(ext2)+4)
.data
w3:
.word 3
w4:
.word 4
s0:
.space 131073
s1:
.word 5
|
stsp/binutils-ia16
| 2,636
|
gas/testsuite/gas/tic6x/insns-c674x-pcrel.s
|
# Test C674x instructions generating PC-relative relocations.
.text
.nocmp
.globl ext1
.globl ext2
.globl ext3
.globl a1
.globl b1
.globl irp
.globl nrp
f:
nop
nop
nop
nop
nop
nop
nop
addkpc .S2 f,b1,3
[a2] addkpc .S2 f+4,b3,7
addkpc .S2 g,b4,0
addkpc .S2 ext1+8,b5,4
g:
nop
nop
nop
nop
nop
f2:
nop
nop
b .S2 ext3+4
b .S1 ext2
b .S2 (nrp)
b .S2 (irp)
b .S1 (a1)
b .S2 f2
[b2] b .S2 f2+4
b .S2 g2
b .S2 (b1)
g2:
nop
nop
nop
nop
nop
f3:
nop
nop
call .S2 ext3+4
call .S1 ext2
call .S2 (nrp)
call .S2 (irp)
call .S1 (a1)
call .S2 f3
[b2] call .S2 f3+4
call .S2 g3
call .S2 (b1)
g3:
nop
nop
nop
nop
nop
f4:
nop
nop
bdec .S2 ext3+4,b2
bdec .S1 ext2,a2
bdec .S2 (nrp),b2
bdec .S2 (irp),b2
bdec .S1 (a1),a2
bdec .S2 f4,b2
[!a1] bdec .S2 f4+4,b2
bdec .S2 g4,b2
bdec .S2 (b1),b2
g4:
nop
nop
nop
nop
nop
f5:
nop
nop
bpos .S2 ext3+4,b2
bpos .S1 ext2,a2
bpos .S2 (nrp),b2
bpos .S2 (irp),b2
bpos .S1 (a1),a2
bpos .S2 f5,b2
[!b1] bpos .S2 f5+4,b2
bpos .S2 g5,b2
bpos .S2 (b1),b2
g5:
nop
nop
nop
nop
nop
f6:
nop
nop
bnop .S2 ext3+4,0
bnop .S1 ext2,1
bnop (nrp),2
bnop .S2 (irp),3
bnop .S1 (a1),4
bnop .S2 f6,5
[!b1] bnop .S2 f6+4,6
bnop g6,7
bnop .S2 (b1),0
g6:
nop
nop
nop
nop
nop
f7:
nop
nop
callnop .S2 ext3+4,0
callnop .S1 ext2,1
callnop (nrp),2
callnop .S2 (irp),3
callnop .S1 (a1),4
callnop .S2 f7,5
[a0] callnop .S2 f7+4,6
callnop g7,7
callnop .S2 (b1),0
g7:
nop
nop
nop
nop
nop
f8:
nop
nop
callp .S2 ext3+4,b3
callp .S1 ext2,a3
callp .S1 (nrp),a3
callp .S2 (irp),b3
callp .S1 (a1),a3
callp .S2 f8,b3
callp .S2 f8+4,b3
callp .S1 g8,a3
callp .S2 (b1),b3
g8:
nop
nop
nop
nop
nop
f9:
nop
nop
callret .S2 ext3+4
callret .S1 ext2
callret .S2 (nrp)
callret .S2 (irp)
callret .S1 (a1)
callret .S2 f9
[b2] callret .S2 f9+4
callret .S2 g9
callret .S2 (b1)
g9:
nop
nop
nop
nop
nop
f10:
nop
nop
ret .S2 ext3+4
ret .S1 ext2
ret .S2 (nrp)
ret .S2 (irp)
ret .S1 (a1)
ret .S2 f10
[b2] ret .S2 f10+4
ret .S2 g10
ret .S2 (b1)
g10:
nop
nop
nop
nop
nop
f11:
nop
nop
retp .S2 ext3+4,b3
retp .S1 ext2,a3
retp .S1 (nrp),a3
retp .S2 (irp),b3
retp .S1 (a1),a3
retp .S2 f11,b3
retp .S2 f11+4,b3
retp .S1 g11,a3
retp .S2 (b1),b3
g11:
nop
nop
nop
nop
nop
g12:
.word 0x3014a120
.word 0x2010a120
.word 0x00000410
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
.word 0x80801021
nop
nop
nop
nop
nop
nop
nop
nop
nop
g13:
.word 0x3014a120
.word 0x2010a120
.word 0x00000410
nop
nop
nop
nop
.word 0xe0000000
nop
nop
nop
nop
nop
nop
.word 0x80801021
.word 0xe0000000
|
stsp/binutils-ia16
| 1,536
|
gas/testsuite/gas/tic6x/insns16-lsd-unit.s
|
; Test C64x+ L, S or D-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
lsdmvto:
.short 0x0006
.short 0x000f
.short 0x0016
.short 0x0017
.short 0x000e
.short 0x0007
.short 0x0006
.short 0x100f
.short 0x1016
.short 0x1017
.short 0x100e
.short 0x1007
.short 0x1006
.short 0x100f
.word 0xefe00000 | 0x0000
lsdmvfr:
.short 0x0046
.short 0x004f
.short 0x0056
.short 0x0057
.short 0x004e
.short 0x0047
.short 0x0046
.short 0x104f
.short 0x1056
.short 0x1057
.short 0x104e
.short 0x1047
.short 0x1046
.short 0x104f
.word 0xefe00000 | 0x0000
lsdx1c:
.short 0x0866
.short 0x4967
.short 0x8ae6
.short 0xcbe7
.short 0x886e
.short 0x496f
.short 0x0aee
.short 0x6bef
.short 0xa876
.short 0xe977
.short 0xaaf6
.short 0x6bf7
.short 0x2866
.short 0x6967
.word 0xefe00000 | 0x0000
lsdx1:
.short 0x1866
.short 0x1867
.short 0x1866
.short 0x3867
.short 0x3866
.short 0x3877
.short 0x3876
.short 0xb877
.short 0xb876
.short 0xb86f
.short 0xf86e
.short 0xf86f
.short 0xf86e
.short 0xf86f
.word 0xefe00000 | 0x0000
|
stsp/binutils-ia16
| 1,151
|
gas/testsuite/gas/tic6x/insns-c674x-sploop.s
|
# Test C674x SPLOOP instructions. The present tests are placeholders
# to verify encoding that may not be valid when the full set of checks
# for invalid input are implemented and may need changing to valid
# code at that point.
.text
.nocmp
.globl f
f:
spmask
spmask l1
spmask L2
spmask s1
spmask S2
spmask D1
spmask d2
spmask M1
spmask m2
spmask D1,L1
spmask L1,D1
spmask L1,S1,D1,M1,M2,D2,S2,L2
spmask M1
||^ mv .L1 a0,a1
|| mv .D2 b0,b1
||^ mv .S1 a2,a3
spmaskr
spmaskr l1
spmaskr L2
spmaskr s1
spmaskr S2
spmaskr D1
spmaskr d2
spmaskr M1
spmaskr m2
spmaskr D1,L1
spmaskr L1,D1
spmaskr L1,S1,D1,M1,M2,D2,S2,L2
spmaskr M1
||^ mv .L1 a0,a1
|| mv .D2 b0,b1
||^ mv .S1 a2,a3
[a0] sploop 1
nop
spkernelr
[b0] sploopd 1
nop
spkernel
[!a0] sploopw 1
nop
spkernel
sploop 1
nop
spkernel 0,0
sploop 1
nop
spkernel 63,0
sploop 2
nop
spkernel 31,0
sploop 2
nop
spkernel 31,1
sploop 3
nop
spkernel 15,2
sploop 4
nop
spkernel 15,3
sploop 5
nop
spkernel 7,4
sploop 8
nop
spkernel 7,7
sploop 9
nop
spkernel 3,8
sploop 14
nop
spkernel 3,13
sploop 1
nop
spkernel 8,0
sploop 2
nop
spkernel 6,0
|
stsp/binutils-ia16
| 1,990
|
gas/testsuite/gas/tic6x/unwind-bad-2.s
|
.cfi_sections .c6xabi.exidx
.cfi_startproc
# stack pointer offset too large for personality routine
.cfi_def_cfa_offset 0x3f8
.cfi_endproc
.personalityindex 3
.endp
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
# stack frame layout does not match personality routine
.personalityindex 4
.endp
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
# stack frame layout does not match personality routine
.personalityindex 3
.endp
.cfi_startproc
stw .d2t2 B4, *B15--(8)
# unable to generate unwinding opcode for reg 20
.cfi_offset 20, 0
.cfi_endproc
.endp
.cfi_startproc
mv .s2 B3, B4
# unable to generate unwinding opcode for reg 20
.cfi_register 19, 20
.cfi_endproc
.endp
.cfi_startproc
mv .s2 B4, B3
# unable to generate unwinding opcode for reg 20
.cfi_register 20, 19
.cfi_endproc
.endp
.cfi_startproc
stw .d2t2 B10, *B15--(8)
# unable to generate unwinding opcode for reg 20
.cfi_offset 26, 0
mv .s2 B3, B10
# unable to restore return address from previously restored reg
.cfi_register 19, 26
.cfi_endproc
.endp
.cfi_startproc
nop
# unhandled CFA insn for unwinding (259)
.cfi_escape 42
.cfi_endproc
.endp
.cfi_startproc
nop
# unable to generate unwinding opcode for frame pointer reg 14
.cfi_def_cfa_register 14
.cfi_endproc
.endp
.cfi_startproc
nop
# unable to generate unwinding opcode for frame pointer offset
.cfi_def_cfa 15, 8
.cfi_endproc
.endp
.cfi_startproc
nop
# unwound stack pointer not doubleword aligned
.cfi_def_cfa_offset 12
.cfi_endproc
.endp
.cfi_startproc
nop
.cfi_offset 10, 0
# stack frame layout too complex for unwinder
.cfi_offset 11, -0x808
.cfi_def_cfa_offset 0x10000
.cfi_endproc
.endp
.cfi_startproc
nop
.cfi_offset 12, -0
.cfi_offset 11, -4
.cfi_offset 10, -8
.cfi_def_cfa_offset 8
# unwound frame has negative size
.cfi_endproc
.endp
|
stsp/binutils-ia16
| 1,745
|
gas/testsuite/gas/tic6x/insns16-d-unit.s
|
; Test C64x+ D-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
dstk: ; op = 0 | STW (.unit) src, *B15[ucst5]
; op = 1 | LDW (.unit)*B15[ucst5], dst
.short 0x8c05
.short 0x9c05
.short 0x8c05
.short 0x9c05
.short 0xcc35
.short 0xfc05
.short 0xdcf5
.short 0x8c0d
.short 0x9c0d
.short 0x8c0d
.short 0x9c0d
.short 0xcc3d
.short 0xfc0d
.short 0xdcfd
.word 0xefe00000
dx2op: ; op = 0 | ADD (.unit) src1, src2, dst (src1 = dst)
; op = 1 | SUB (.unit) src1, src2, dst (src1 = dst, dst = src1 - src2
.short 0x0036
.short 0x0037
.short 0x0836
.short 0x0837
.short 0x1036
.short 0x1837
.short 0x8036
.short 0xc037
.short 0xe836
.short 0x8837
.short 0xda36
.short 0xe037
.short 0xd236
.short 0xe3b7
.word 0xefe00000
dx5: ; ADDAW (.unit)B15, ucst5, dst
.short 0x0436
.short 0x0437
.short 0x0c36
.short 0x0c37
.short 0x1436
.short 0x1c37
.short 0x8436
.short 0xc437
.short 0xec36
.short 0x8c37
.short 0xde36
.short 0xe437
.short 0xd636
.short 0xe7b7
.word 0xefe00000
dx5p:
.short 0x0c77
.short 0x2d77
.short 0x4e77
.short 0x6f77
.short 0x8c77
.short 0xad77
.short 0xce77
.short 0xeff7
.short 0x2cf7
.short 0x4df7
.short 0x6ef7
.short 0x8ff7
.short 0xacf7
.short 0xcdf7
.word 0xefe00000
dx1:
.short 0x7876
.short 0x7877
.short 0x78f6
.short 0x79f7
.short 0x5876
.short 0x9877
.short 0xd876
.short 0x7877
.short 0x7876
.short 0x7877
.short 0x7876
.short 0x7877
.short 0x7876
.short 0x7877
.word 0xefe00000
dpp:
.short 0x0077
.short 0x4177
.short 0xa277
.short 0xe377
.short 0x2477
.short 0x6577
.short 0x8677
.short 0x0777
.short 0x11f7
.short 0x52f7
.short 0x4777
.short 0x6777
.short 0x15f7
.short 0x56f7
.word 0xefe80000
|
stsp/binutils-ia16
| 1,040
|
gas/testsuite/gas/tic6x/predicate-bad-2.s
|
# Test predicates allowed or disallowed depending on the architecture.
.text
.globl f
f:
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c64x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c64x+
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c67x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c67x+
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c674x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
.arch c62x
[A0] nop
[A1] nop
[A2] nop
[B0] nop
[B1] nop
[B2] nop
[!A0] nop
[!A1] nop
[!A2] nop
[!B0] nop
[!B1] nop
[!B2] nop
|
stsp/binutils-ia16
| 3,716
|
gas/testsuite/gas/tic6x/unwind-2.s
|
.cfi_sections .c6xabi.exidx
# standard layout
.p2align 8
f0:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# standard layout (pr0)
.p2align 8
f1:
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
.personalityindex 0
.endp
# standard layout (pr1)
.p2align 8
f2:
.cfi_startproc
stw .d2t2 B15, *B15--(24)
.cfi_def_cfa_offset 24
.cfi_offset 31, 0
stw .d2t2 B10, *+B15(20)
.cfi_offset 26, -4
stw .d2t2 B3, *+B15(16)
.cfi_offset 19, -8
stdw .d2t1 A11:A10, *+B15(8)
.cfi_offset 11, -16
.cfi_offset 10, -12
nop 4
.cfi_endproc
.personalityindex 1
.endp
# standard layout (pr3)
.p2align 8
f3:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.personalityindex 3
.endp
# compact layout
.p2align 8
f4:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# compact layout (pr0)
.p2align 8
f5:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 0
.endp
# compact layout (pr4)
.p2align 8
f6:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 4
.endp
# compact layout (aligned pair)
.p2align 8
f7:
.cfi_startproc
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, 0
.cfi_def_cfa_offset 8
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, -8
.cfi_def_cfa_offset 8
stdw .d2t1 A11:A10, *B15--(8)
.cfi_offset 11, -16
.cfi_offset 10, -12
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (aligned pair + 1)
.p2align 8
f8:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stdw .d2t1 A13:A12, *B15--(8)
.cfi_offset 13, -8
.cfi_offset 12, -4
.cfi_def_cfa_offset 16
stw .d2t1 A10, *B15--(8)
.cfi_offset 10, -16
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (misaligned pair)
.p2align 8
f9:
.cfi_startproc
stw .d2t2 B11, *B15--(8)
.cfi_offset 27, 0
.cfi_def_cfa_offset 8
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# standard frame pointer
.p2align 8
fa:
.cfi_startproc
stw .d2t1 A15, *B15--(16)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# compact frame pointer
.p2align 8
fb:
.cfi_startproc
stw .d2t1 A15, *B15--(8)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fc:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fd:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fe:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -12
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
ff:
.cfi_startproc
addk .s2 -24, B15
stw .d2t2 B3, *+B15(24)
.cfi_def_cfa_offset 24
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -20
nop 4
.cfi_endproc
.endp
|
stsp/binutils-ia16
| 3,750
|
gas/testsuite/gas/tic6x/insns16-s-unit.s
|
; Test C64x+ S-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
s3_nosat_op_0:
.short 0x000a
.short 0x201b
.short 0x512a
.short 0x713b
.short 0x824a
.short 0xa25b
.short 0xd36a
.short 0xf37b
.short 0xe28a
s3_nosat_op_1:
.short 0x0a9b
.short 0x39aa
.short 0x59bb
.short 0x68ca
.short 0x88db
.word 0xefe00000 | 0x0000
s3_sat_op_0:
.short 0x21ea
.short 0x41fb
.short 0x720a
.short 0x921b
.short 0xc32a
.short 0xe33b
.short 0xf24a
.short 0xb25b
.short 0x816a
s3_sat_op_1:
.short 0xa87b
.short 0xd88a
.short 0xfa9b
.short 0xeaaa
.short 0x7bbb
.word 0xefe00000 | 0x4000
s3i:
.short 0x040a
.short 0x251b
.short 0x362a
.short 0x573b
.short 0x444a
.short 0x655b
.short 0x766a
.short 0x9ffb
.short 0x8cea
.short 0xaddb
.short 0xbeca
.short 0xdfbb
.short 0xccaa
.short 0xed9b
.word 0xefe00000 | 0x0000
smvk8:
.short 0x0012
.short 0x1113
.short 0x2232
.short 0x3333
.short 0x4752
.short 0x5653
.short 0x6572
.short 0x78f3
.short 0x8992
.short 0x9a93
.short 0xabb2
.short 0xbed2
.short 0xcdf3
.short 0xfc92
.word 0xefe00000 | 0x0000
ssh5_nosat:
.short 0x0402
.short 0x1503
.short 0x2682
.short 0x3783
.short 0x4c22
.short 0x5d23
.short 0x6ea2
.short 0x7fa3
.short 0x8442
.short 0x9543
.short 0xa6c2
.short 0xb7c3
.short 0xcc42
.short 0xdd43
.word 0xefe00000 | 0x0000
ssh5_sat:
.short 0xec02
.short 0xfd03
.short 0xe682
.short 0xd783
.short 0xc422
.short 0xb523
.short 0xaea2
.short 0x9fa3
.short 0x8c42
.short 0x7d43
.short 0x66c2
.short 0x57c3
.short 0x4442
.short 0x3543
.word 0xefe00000 | 0x4000
s2sh:
.short 0x0462
.short 0x2563
.short 0x4662
.short 0x6f63
.short 0x8c62
.short 0xad63
.short 0xce62
.short 0xf7e3
.short 0xd4e2
.short 0xb5e3
.short 0x96e2
.short 0x7fe3
.short 0x5ce2
.short 0x3de3
.word 0xefe00000
sc5:
.short 0x0002
.short 0x1103
.short 0x2202
.short 0x3303
.short 0x4a22
.short 0x5923
.short 0x6822
.short 0x71a3
.short 0x82a2
.short 0x93c3
.short 0xa2c2
.short 0xb9c3
.short 0xc8c2
.short 0xf9c3
.word 0xefe00000
s2ext:
.short 0x0062
.short 0x2163
.short 0x4262
.short 0x6b63
.short 0x8862
.short 0xa963
.short 0xca62
.short 0xf3e3
.short 0xd0e2
.short 0xb1e3
.short 0x9ae2
.short 0x7be3
.short 0x58e2
.short 0x39e3
.word 0xefe00000
sx2op:
.short 0x002e
.short 0x212f
.short 0x522e
.short 0x732f
.short 0x802e
.short 0xa12f
.short 0xd22e
.short 0xfb2f
.short 0x082e
.short 0x292f
.short 0x5a2e
.short 0x7b2f
.short 0x882e
.short 0xa92f
.word 0xefe00000
sx5:
.short 0x042e
.short 0x152f
.short 0x262e
.short 0x372f
.short 0x4c2e
.short 0x5d2f
.short 0x6e2e
.short 0x77af
.short 0x84ae
.short 0x95af
.short 0xaeae
.short 0xbfaf
.short 0xccae
.short 0xfdaf
.word 0xefe00000
sx1:
.short 0x586e
.short 0x596f
.short 0x5a6e
.short 0x5b6f
.short 0x586e
.short 0x796f
.short 0x7a6e
.short 0x7bef
.short 0x78ee
.short 0x79ef
.short 0xdaee
.short 0xdbef
.short 0xd8ee
.short 0xd9ef
.word 0xefe00000
sx1_rs:
.short 0x586e
.short 0x596f
.short 0x5a6e
.short 0x5b6f
.short 0x586e
.short 0x796f
.short 0x7a6e
.short 0x7bef
.short 0x78ee
.short 0x79ef
.short 0xdaee
.short 0xdbef
.short 0xd8ee
.short 0xd9ef
.word 0xefe00000 | 0x00080000
sx1b:
.short 0x006e
.short 0x216f
.short 0x22ee
.short 0x43ef
.short 0x446e
.short 0x656f
.short 0x66ee
.short 0x87ef
.short 0x866e
.short 0xa56f
.short 0xa4ee
.short 0xc3ef
.short 0xc26e
.short 0xe16f
.word 0xefe00000
sx1b_rs:
.short 0x006e
.short 0x216f
.short 0x22ee
.short 0x43ef
.short 0x446e
.short 0x656f
.short 0x66ee
.short 0x87ef
.short 0x866e
.short 0xa56f
.short 0xa4ee
.short 0xc3ef
.short 0xc26e
.short 0xe16f
.word 0xefe00000 | 0x00080000
|
stsp/binutils-ia16
| 38,810
|
gas/testsuite/gas/tic6x/insns-c674x.s
|
# Test C674x instructions.
.text
.nocmp
.globl f
f:
abs .L1 a5,a7
abs .L1X b11,a14
[a1] abs .L2 b16,b19
[!b2] abs .L2X a7,b31
[b1] abs .L1 a11:a10,a19:a18
abs .L2 b13:b12,b1:b0
abs2 .L1 a9,a10
[a2] abs2 .L1X b23,a5
abs2 .L2 b3,b14
abs2 .L2X a28,b25
.word 0x0c180b20
absdp .S1 a7:a6,a25:a24
[a0] absdp .S2 b3:b2,b5:b4
.word 0x0c1feb20
abssp .S1 a9,a8
abssp .S1X b18,a16
[b0] abssp .S2 b0,b7
[!a1] abssp .S2X a1,b26
add .L1 a5,a10,a20
[!a2] add .L1X a3,b11,a4
[!b1] add .L2 b9,b8,b7
add .L2X b30,a20,b10
add .L1 a10,a11,a21:a20
add .L1X a13,b26,a15:a14
[!a0] add .L2 b29,b28,b27:b26
add .L2X b25,a24,b23:b22
[!b0] add .L1 a1,a3:a2,a5:a4
add .L1X b20,a17:a16,a15:a14
add .L2 b24,b23:b22,b21:b20
[b2] add .L2X a6,b17:b16,b15:b14
add .L1 -16,a5,a6
[a0] add .L1X 15,b11,a30
add .L2 -11,b9,b10
add .L2X 14,a5,b7
add .L1 5,a3:a2,a7:a6
[b0] add .L2 -7,b29:b28,b29:b28
[!a0] add .S1 a11,a12,a13
add .S1X a14,b15,a16
add .S2 b17,b18,b19
add .S2X b20,a30,b25
add .S1 -16,a4,a11
add .S1X 13,b9,a23
[!b0] add .S2 15,b25,b11
add .S2X -4,a1,b2
add .D1 a5,a9,a2
[a1] add .D2 b16,b17,b18
[b1] add .D1 a5,31,a6
add .D2 b22,0,b21
.word 0x01042840
[!a1] add .D1X a1,b2,a3
add .D2X b7,a8,b9
.word 0x00842af0
add .D2 b4,-5,b21
[!b1] add .D1X b5,-16,a4
add .D2X a2,15,b9
addab .D1 a5,a10,a15
[a2] addab .D2 b24,b23,b22
[b2] addab .D1 a25,31,a28
addab .D2 b4,0,b7
addab .D1X b14,32767,a5
addab .D2 b15,32,b29
addad .D1 a4,a7,a11
[!a2] addad .D2 b5,b8,b13
[!b2] addad .D1 a13,31,a4
addad .D2 b21,0,b5
addah .D1 a5,a10,a15
[a0] addah .D2 b24,b23,b22
[b0] addah .D1 a25,31,a28
addah .D2 b4,0,b7
addah .D1X b14,32767,a5
addah .D2 b15,32,b29
addaw .D1 a5,a10,a15
[!a0] addaw .D2 b24,b23,b22
[!b0] addaw .D1 a25,31,a28
addaw .D2 b4,0,b7
addaw .D1X b14,32767,a5
addaw .D2 b15,32,b29
adddp .L1 a3:a2,a15:a14,a19:a18
[b1] adddp .L1X a9:a8,b7:b6,a21:a20
adddp .L2 b3:b2,b15:b14,b19:b18
[b1] adddp .L2X b9:b8,a7:a6,b21:b20
[a1] adddp .S1 a13:a12,a25:a24,a29:a28
adddp .S1X a19:a18,b17:b16,a31:a30
[a1] adddp .S2 b13:b12,b25:b24,b29:b28
adddp .S2X b19:b18,a17:a16,b31:b30
addk .S1 -32768,a5
[!a1] addk .S2 32767,b4
addsp .L1 a5,a6,a7
[!b1] addsp .L1X a5,b10,a20
[a2] addsp .L2 b25,b24,b23
addsp .L2X b30,a20,b10
addsp .S1 a5,a6,a7
[b2] addsp .S1X a5,b10,a20
[!a2] addsp .S2 b25,b24,b23
addsp .S2X b30,a20,b10
addsub .L1 a22,a21,a25:a24
addsub .L1X a20,b19,a17:a16
addsub .L2 b4,b7,b17:b16
addsub .L2X b4,a8,b1:b0
addsub2 .L1 a22,a21,a25:a24
addsub2 .L1X a20,b19,a17:a16
addsub2 .L2 b4,b7,b17:b16
addsub2 .L2X b4,a8,b1:b0
[!b2] addu .L1 a4,a5,a7:a6
addu .L1X a20,b19,a29:a28
[a0] addu .L2 b11,b10,b9:b8
addu .L2X b4,a7,b3:b2
addu .L1 a11,a9:a8,a7:a6
[b0] addu .L1X b20,a21:a20,a23:a22
[!a0] addu .L2 b23,b21:b20,b27:b26
addu .L2X a14,b17:b16,b19:b18
add2 .S1 a7,a6,a5
[!b0] add2 .S1X a10,b9,a8
add2 .S2 b18,b17,b16
[b1] add2 .S2X b22,a29,b21
add2 .L1 a7,a6,a5
[a1] add2 .L1X a10,b9,a8
add2 .L2 b18,b17,b16
[!a1] add2 .L2X b22,a29,b21
add2 .D1 a7,a6,a5
[!b1] add2 .D1X a10,b9,a8
add2 .D2 b18,b17,b16
[a2] add2 .D2X b22,a29,b21
[b2] add4 .L1 a30,a27,a24
add4 .L1X a23,b24,a25
add4 .L2 b24,b26,b27
[!a2] add4 .L2X b14,a17,b20
[!b2] and .L1 a1,a2,a3
and .L1X a10,b3,a11
[a0] and .L2 b19,b23,b29
and .L2X b7,a8,b9
and .L1 -16,a4,a5
[b0] and .L1X 15,b6,a7
[!a0] and .L2 -3,b20,b18
and .L2X 9,a20,b18
[!b0] and .S1 a1,a2,a3
and .S1X a10,b3,a11
[a1] and .S2 b19,b23,b29
and .S2X b7,a8,b9
and .S1 -16,a4,a5
[b1] and .S1X 15,b6,a7
[!a1] and .S2 12,b20,b18
and .S2X -8,a20,b18
[!b1] and .D1 a1,a2,a3
and .D1X a10,b3,a11
[a2] and .D2 b19,b23,b29
and .D2X b7,a8,b9
and .D1 -16,a4,a5
[b2] and .D1X 15,b6,a7
[!a2] and .D2 -14,b20,b18
and .D2X 13,a20,b18
andn .L1 a20,a18,a17
[!b2] andn .L1X a16,b15,a14
[a0] andn .L2 b23,b25,b27
andn .L2X b4,a5,b8
andn .S1 a20,a18,a17
[b0] andn .S1X a16,b15,a14
[!a0] andn .S2 b23,b25,b27
andn .S2X b4,a5,b8
andn .D1 a20,a18,a17
[!b0] andn .D1X a16,b15,a14
[a1] andn .D2 b23,b25,b27
andn .D2X b4,a5,b8
avg2 .M1 a8,a11,a14
[b1] avg2 .M1X a17,b20,a23
avg2 .M2 b26,b29,b0
[!a1] avg2 .M2X b3,a6,b9
avgu4 .M1 a8,a11,a14
[!b1] avgu4 .M1X a17,b20,a23
avgu4 .M2 b26,b29,b0
[a2] avgu4 .M2X b3,a6,b9
b .S2 b4
b .S2 b3
[b2] b .S2X a4
[!a2] call .S2 b4
call .S2X a4
callret .S2 b4
[!b2] callret .S2X a4
ret .S2 b4
[a0] ret .S2X a4
[b0] b .S2 irp
[!a0] b .S2 nrp
call .S2 irp
[a0] call .S2 nrp
[b0] callret .S2 irp
callret .S2 nrp
[b0] ret .S2 irp
ret .S2 nrp
bitc4 .M1 a4,a14
[!b0] bitc4 .M1X b5,a15
bitc4 .M2 b16,b26
[b1] bitc4 .M2X a1,b31
bitr .M1 a4,a14
[a1] bitr .M1X b5,a15
bitr .M2 b16,b26
[!a1] bitr .M2X a1,b31
bnop .S2 B5,0
[!b1] bnop .S2X A20,7
callnop .S2 B5,0
[a2] callnop .S2X A20,7
clr .S1 a5,0,31,a10
[b2] clr .S2 b10,31,0,b5
[!a2] clr .S1 a7,a14,a21
clr .S1X b9,a18,a27
clr .S2 b20,b18,b16
[!b2] clr .S2X a4,b16,b31
cmpeq .L1 a1,a3,a3
[a0] cmpeq .L1X a1,b4,a7
[b0] cmpeq .L2 b10,b11,b12
cmpeq .L2X b13,a14,b15
[!a0] cmpeq .L1 -16,a16,a17
cmpeq .L1X 15,b18,a19
cmpeq .L2 3,b20,b22
[!b0] cmpeq .L2X 4,a23,b25
cmpeq .L1 a4,a7:a6,a18
[a1] cmpeq .L1X b9,a11:a10,a20
cmpeq .L2 b21,b23:b22,b25
[b1] cmpeq .L2X a19,b25:b24,b27
[!a1] cmpeq .L1 -16,a15:a14,a22
[!b1] cmpeq .L2 15,b19:b18,b17
cmpeq2 .S1 a11,a9,a10
[a2] cmpeq2 .S1X a12,b14,a15
cmpeq2 .S2 b16,b20,b24
[b2] cmpeq2 .S2X b19,a23,b22
[!a2] cmpeq4 .S1 a20,a23,a26
cmpeq4 .S1X a31,b4,a15
[!b2] cmpeq4 .S2 b9,b26,b5
cmpeq4 .S2X b3,a5,b8
cmpeqdp .S1 a9:a8,a7:a6,a5
[a0] cmpeqdp .S1X a3:a2,b1:b0,a31
[b0] cmpeqdp .S2 b21:b20,b17:b16,b25
cmpeqdp .S2X b5:b4,a7:a6,b9
cmpeqsp .S1 a20,a21,a22
[!b0] cmpeqsp .S1X a23,b24,a25
[!a0] cmpeqsp .S2 b26,b27,b28
cmpeqsp .S2X b29,a30,b31
cmpgt .L1 a1,a3,a3
[a1] cmpgt .L1X a1,b4,a7
[b1] cmpgt .L2 b10,b11,b12
cmpgt .L2X b13,a14,b15
[!a1] cmpgt .L1 -16,a16,a17
cmpgt .L1X 15,b18,a19
cmpgt .L2 3,b20,b22
[!b1] cmpgt .L2X 4,a23,b25
cmpgt .L1 a4,a7:a6,a18
[a2] cmpgt .L1X b9,a11:a10,a20
cmpgt .L2 b21,b23:b22,b25
[b2] cmpgt .L2X a19,b25:b24,b27
[!a2] cmpgt .L1 -16,a15:a14,a22
[!b2] cmpgt .L2 15,b19:b18,b17
[a1] cmpgt .L1X b4,a1,a7
cmpgt .L2X a14,b13,b15
[!a1] cmpgt .L1 a16,-16,a17
cmpgt .L1X b18,15,a19
cmpgt .L2 b20,3,b22
[!b1] cmpgt .L2X a23,4,b25
cmpgt .L1 a7:a6,a4,a18
[a2] cmpgt .L1X a11:a10,b9,a20
cmpgt .L2 b23:b22,b21,b25
[b2] cmpgt .L2X b25:b24,a19,b27
[!a2] cmpgt .L1 a15:a14,-16,a22
[!b2] cmpgt .L2 b19:b18,15,b17
cmpgt2 .S1 a16,a15,a14
[a0] cmpgt2 .S1X a13,b12,a11
cmpgt2 .S2 b10,b9,b8
[b0] cmpgt2 .S2X b7,a6,b5
[!a0] cmpgtdp .S1 a3:a2,a1:a0,a31
cmpgtdp .S1X a29:a28,b27:b26,a25
cmpgtdp .S2 b23:b22,b21:b20,b19
[!b0] cmpgtdp .S2X b17:b16,a15:a14,b13
[a1] cmpgtsp .S1 a3,a1,a31
cmpgtsp .S1X a29,b27,a25
cmpgtsp .S2 b23,b21,b19
[b1] cmpgtsp .S2X b17,a15,b13
cmpgtu .L1 a1,a3,a3
[a1] cmpgtu .L1X a1,b4,a7
[b1] cmpgtu .L2 b10,b11,b12
cmpgtu .L2X b13,a14,b15
[!a1] cmpgtu .L1 0,a16,a17
cmpgtu .L1X 31,b18,a19
cmpgtu .L2 3,b20,b22
[!b1] cmpgtu .L2X 4,a23,b25
cmpgtu .L1 a4,a7:a6,a18
[a2] cmpgtu .L1X b9,a11:a10,a20
cmpgtu .L2 b21,b23:b22,b25
[b2] cmpgtu .L2X a19,b25:b24,b27
[!a2] cmpgtu .L1 0,a15:a14,a22
[!b2] cmpgtu .L2 31,b19:b18,b17
cmpgtu4 .S1 a25,a27,a23
[a0] cmpgtu4 .S1X a21,b20,a17
cmpgtu4 .S2 b11,b13,b17
[b0] cmpgtu4 .S2X b19,a23,b29
cmplt .L1 a1,a3,a3
[a1] cmplt .L1X a1,b4,a7
[b1] cmplt .L2 b10,b11,b12
cmplt .L2X b13,a14,b15
[!a1] cmplt .L1 -16,a16,a17
cmplt .L1X 15,b18,a19
cmplt .L2 3,b20,b22
[!b1] cmplt .L2X 4,a23,b25
cmplt .L1 a4,a7:a6,a18
[a2] cmplt .L1X b9,a11:a10,a20
cmplt .L2 b21,b23:b22,b25
[b2] cmplt .L2X a19,b25:b24,b27
[!a2] cmplt .L1 -16,a15:a14,a22
[!b2] cmplt .L2 15,b19:b18,b17
[a1] cmplt .L1X b4,a1,a7
cmplt .L2X a14,b13,b15
[!a1] cmplt .L1 a16,-16,a17
cmplt .L1X b18,15,a19
cmplt .L2 b20,3,b22
[!b1] cmplt .L2X a23,4,b25
cmplt .L1 a7:a6,a4,a18
[a2] cmplt .L1X a11:a10,b9,a20
cmplt .L2 b23:b22,b21,b25
[b2] cmplt .L2X b25:b24,a19,b27
[!a2] cmplt .L1 a15:a14,-16,a22
[!b2] cmplt .L2 b19:b18,15,b17
cmplt2 .S1 a16,a15,a14
[a0] cmplt2 .S1X b12,a13,a11
cmplt2 .S2 b10,b9,b8
[b0] cmplt2 .S2X a6,b7,b5
[!a0] cmpltdp .S1 a3:a2,a1:a0,a31
cmpltdp .S1X a29:a28,b27:b26,a25
cmpltdp .S2 b23:b22,b21:b20,b19
[!b0] cmpltdp .S2X b17:b16,a15:a14,b13
[a1] cmpltsp .S1 a3,a1,a31
cmpltsp .S1X a29,b27,a25
cmpltsp .S2 b23,b21,b19
[b1] cmpltsp .S2X b17,a15,b13
cmpltu .L1 a1,a3,a3
[a1] cmpltu .L1X a1,b4,a7
[b1] cmpltu .L2 b10,b11,b12
cmpltu .L2X b13,a14,b15
[!a1] cmpltu .L1 0,a16,a17
cmpltu .L1X 31,b18,a19
cmpltu .L2 3,b20,b22
[!b1] cmpltu .L2X 4,a23,b25
cmpltu .L1 a4,a7:a6,a18
[a2] cmpltu .L1X b9,a11:a10,a20
cmpltu .L2 b21,b23:b22,b25
[b2] cmpltu .L2X a19,b25:b24,b27
[!a2] cmpltu .L1 0,a15:a14,a22
[!b2] cmpltu .L2 31,b19:b18,b17
cmpltu4 .S1 a25,a27,a23
[a0] cmpltu4 .S1X b20,a21,a17
cmpltu4 .S2 b11,b13,b17
[b0] cmpltu4 .S2X a23,b19,b29
cmpy .M1 a1,a2,a5:a4
cmpy .M1X a4,b5,a7:a6
cmpy .M2 b8,b9,b11:b10
cmpy .M2X b11,a12,b13:b12
cmpyr .M1 a1,a2,a5
cmpyr .M1X a4,b5,a7
cmpyr .M2 b8,b9,b11
cmpyr .M2X b11,a12,b13
cmpyr1 .M1 a1,a2,a5
cmpyr1 .M1X a4,b5,a7
cmpyr1 .M2 b8,b9,b11
cmpyr1 .M2X b11,a12,b13
ddotp4 .M1 a1,a2,a5:a4
ddotp4 .M1X a4,b5,a7:a6
ddotp4 .M2 b8,b9,b11:b10
ddotp4 .M2X b11,a12,b13:b12
ddotph2 .M1 a1:a0,a2,a5:a4
ddotph2 .M1X a3:a2,b5,a7:a6
ddotph2 .M2 b7:b6,b9,b11:b10
ddotph2 .M2X b11:b10,a12,b13:b12
ddotph2r .M1 a1:a0,a2,a5
ddotph2r .M1X a3:a2,b5,a7
ddotph2r .M2 b7:b6,b9,b11
ddotph2r .M2X b11:b10,a12,b13
ddotpl2 .M1 a1:a0,a2,a5:a4
ddotpl2 .M1X a3:a2,b5,a7:a6
ddotpl2 .M2 b7:b6,b9,b11:b10
ddotpl2 .M2X b11:b10,a12,b13:b12
ddotpl2r .M1 a1:a0,a2,a5
ddotpl2r .M1X a3:a2,b5,a7
ddotpl2r .M2 b7:b6,b9,b11
ddotpl2r .M2X b11:b10,a12,b13
deal .M1 a8,a9
[!a0] deal .M1X b10,a11
[!b0] deal .M2 b12,b13
deal .M2X a14,b15
dint
[a1] dmv .S1 a4,a5,a7:a6
dmv .S1X a8,b9,a11:a10
dmv .S2 b12,b13,b15:b14
[b1] dmv .S2X b16,a17,b19:b18
dotp2 .M1 a20,a15,a10
[!a1] dotp2 .M1X a10,b5,a0
dotp2 .M2 b7,b14,b21
[!b1] dotp2 .M2X b23,a20,b17
dotp2 .M1 a20,a15,a11:a10
[a2] dotp2 .M1X a10,b5,a1:a0
[b2] dotp2 .M2 b7,b14,b21:b20
dotp2 .M2X b23,a20,b17:b16
dotpn2 .M1 a20,a15,a10
[!a2] dotpn2 .M1X a10,b5,a0
dotpn2 .M2 b7,b14,b21
[!b2] dotpn2 .M2X b23,a20,b17
dotpnrsu2 .M1 a20,a15,a10
[a0] dotpnrsu2 .M1X a10,b5,a0
dotpnrsu2 .M2 b7,b14,b21
[b0] dotpnrsu2 .M2X b23,a20,b17
[!a0] dotpnrus2 .M1 a20,a15,a10
dotpnrus2 .M1X b5,a10,a0
dotpnrus2 .M2 b7,b14,b21
[!b0] dotpnrus2 .M2X a20,b23,b17
dotprsu2 .M1 a20,a15,a10
[a1] dotprsu2 .M1X a10,b5,a0
dotprsu2 .M2 b7,b14,b21
[b1] dotprsu2 .M2X b23,a20,b17
[!a1] dotprus2 .M1 a20,a15,a10
dotprus2 .M1X b5,a10,a0
dotprus2 .M2 b7,b14,b21
[!b1] dotprus2 .M2X a20,b23,b17
dotpsu4 .M1 a20,a15,a10
[a2] dotpsu4 .M1X a10,b5,a0
dotpsu4 .M2 b7,b14,b21
[b2] dotpsu4 .M2X b23,a20,b17
dotpus4 .M1 a20,a15,a10
[!a2] dotpus4 .M1X b5,a10,a0
dotpus4 .M2 b7,b14,b21
[!b2] dotpus4 .M2X a20,b23,b17
dotpu4 .M1 a20,a15,a10
[a0] dotpu4 .M1X a10,b5,a0
dotpu4 .M2 b7,b14,b21
[b0] dotpu4 .M2X b23,a20,b17
dpack2 .L1 a30,a27,a25:a24
dpack2 .L1X a21,b18,a15:a14
dpack2 .L2 b12,b9,b7:b6
dpack2 .L2X b3,a0,b29:b28
dpackx2 .L1 a30,a27,a25:a24
dpackx2 .L1X a21,b18,a15:a14
dpackx2 .L2 b12,b9,b7:b6
dpackx2 .L2X b3,a0,b29:b28
.word 0x01900118
dpint .L1 a5:a4,a3
[!a0] dpint .L2 b5:b4,b3
.word 0x0197e118
.word 0x01900138
dpsp .L1 a5:a4,a3
[!b0] dpsp .L2 b5:b4,b3
.word 0x0197e138
.word 0x0190003a
[a1] dptrunc .L1 a5:a4,a3
dptrunc .L2 b5:b4,b3
.word 0x0197e03a
ext .S1 a5,0,31,a10
[b1] ext .S2 b10,31,0,b5
[!a1] ext .S1 a7,a14,a21
ext .S1X b9,a18,a27
ext .S2 b20,b18,b16
[!b1] ext .S2X a4,b16,b31
extu .S1 a5,0,31,a10
[a2] extu .S2 b10,31,0,b5
[b2] extu .S1 a7,a14,a21
extu .S1X b9,a18,a27
extu .S2 b20,b18,b16
[!a2] extu .S2X a4,b16,b31
gmpy .M1 a25,a16,a9
gmpy .M2 b5,b12,b13
[!b2] gmpy4 .M1 a2,a3,a5
gmpy4 .M1X a7,b11,a13
gmpy4 .M2 b17,b19,b23
[a0] gmpy4 .M2X b29,a31,b5
idle
intdp .L1 a1,a3:a2
[b0] intdp .L1X b5,a7:a6
[!a0] intdp .L2 b9,b11:b10
intdp .L2X a5,b13:b12
intdpu .L1 a1,a3:a2
[!b0] intdpu .L1X b5,a7:a6
[a1] intdpu .L2 b9,b11:b10
intdpu .L2X a5,b13:b12
intsp .L1 a1,a3
[b1] intsp .L1X b5,a7
[!a1] intsp .L2 b9,b11
intsp .L2X a5,b13
intspu .L1 a1,a3
[!b1] intspu .L1X b5,a7
[a2] intspu .L2 b9,b11
intspu .L2X a5,b13
ldb .D1T1 *a5,a7
[b2] ldb .D1T2 *++a9,b11
ldb .D2T1 *--b13,a15
[!a2] ldb .D2T2 *b17++,b19
ldb .D1T1 *a21--,a23
[!b2] ldb .D2T2 *-b25[31],b27
ldb .D1T1 *+a29[0],a31
ldb .D1T1 *-a0(2),a2
ldb .D1T1 *-a4[a5],a6
ldb .D1T1 *+a7[a8],a9
ldb .D1T1 *--a10[11],a12
ldb .D1T1 *++a13(14),a15
ldb .D1T1 *a16--(17),a18
ldb .D1T1 *a19++(20),a21
ldb .D1T1 *--a22[a23],a24
ldb .D1T1 *++a25[a26],a27
ldb .D1T1 *a28--[a29],a30
ldb .D1T1 *a31++[a0],a1
[a0] ldb .D2T1 *+b14(32767),a15
ldb .D2T2 *+b15[32767],b16
ldbu .D1T1 *a5,a7
[b2] ldbu .D1T2 *++a9,b11
ldbu .D2T1 *--b13,a15
[!a2] ldbu .D2T2 *b17++,b19
ldbu .D1T1 *a21--,a23
[!b2] ldbu .D2T2 *-b25[31],b27
ldbu .D1T1 *+a29[0],a31
ldbu .D1T1 *-a0(2),a2
ldbu .D1T1 *-a4[a5],a6
ldbu .D1T1 *+a7[a8],a9
ldbu .D1T1 *--a10[11],a12
ldbu .D1T1 *++a13(14),a15
ldbu .D1T1 *a16--(17),a18
ldbu .D1T1 *a19++(20),a21
ldbu .D1T1 *--a22[a23],a24
ldbu .D1T1 *++a25[a26],a27
ldbu .D1T1 *a28--[a29],a30
ldbu .D1T1 *a31++[a0],a1
[a0] ldbu .D2T1 *+b14(32767),a15
ldbu .D2T2 *+b15[32767],b16
lddw .D1T1 *a5,a7:a6
[b2] lddw .D1T2 *++a9,b11:b10
lddw .D2T1 *--b13,a15:a14
[!a2] lddw .D2T2 *b17++,b19:b18
lddw .D1T1 *a21--,a23:a22
[!b2] lddw .D2T2 *-b25[31],b27:b26
lddw .D1T1 *+a29[0],a31:a30
lddw .D1T1 *-a0(248),a3:a2
lddw .D1T1 *-a4[a5],a7:a6
lddw .D1T1 *+a7[a8],a9:a8
lddw .D1T1 *--a10[11],a13:a12
lddw .D1T1 *++a13(16),a15:a14
lddw .D1T1 *a16--(24),a19:a18
lddw .D1T1 *a19++(32),a21:a20
lddw .D1T1 *--a22[a23],a25:a24
lddw .D1T1 *++a25[a26],a27:a26
lddw .D1T1 *a28--[a29],a31:a30
lddw .D1T1 *a31++[a0],a1:a0
ldh .D1T1 *a5,a7
[b2] ldh .D1T2 *++a9,b11
ldh .D2T1 *--b13,a15
[!a2] ldh .D2T2 *b17++,b19
ldh .D1T1 *a21--,a23
[!b2] ldh .D2T2 *-b25[31],b27
ldh .D1T1 *+a29[0],a31
ldh .D1T1 *-a0(62),a2
ldh .D1T1 *-a4[a5],a6
ldh .D1T1 *+a7[a8],a9
ldh .D1T1 *--a10[11],a12
ldh .D1T1 *++a13(14),a15
ldh .D1T1 *a16--(18),a18
ldh .D1T1 *a19++(20),a21
ldh .D1T1 *--a22[a23],a24
ldh .D1T1 *++a25[a26],a27
ldh .D1T1 *a28--[a29],a30
ldh .D1T1 *a31++[a0],a1
[a0] ldh .D2T1 *+b14(65534),a15
ldh .D2T2 *+b15[32767],b16
ldhu .D1T1 *a5,a7
[b2] ldhu .D1T2 *++a9,b11
ldhu .D2T1 *--b13,a15
[!a2] ldhu .D2T2 *b17++,b19
ldhu .D1T1 *a21--,a23
[!b2] ldhu .D2T2 *-b25[31],b27
ldhu .D1T1 *+a29[0],a31
ldhu .D1T1 *-a0(62),a2
ldhu .D1T1 *-a4[a5],a6
ldhu .D1T1 *+a7[a8],a9
ldhu .D1T1 *--a10[11],a12
ldhu .D1T1 *++a13(14),a15
ldhu .D1T1 *a16--(18),a18
ldhu .D1T1 *a19++(20),a21
ldhu .D1T1 *--a22[a23],a24
ldhu .D1T1 *++a25[a26],a27
ldhu .D1T1 *a28--[a29],a30
ldhu .D1T1 *a31++[a0],a1
[a0] ldhu .D2T1 *+b14(65534),a15
ldhu .D2T2 *+b15[32767],b16
ldndw .D1T1 *a5,a7:a6
[b2] ldndw .D1T2 *++a9,b11:b10
ldndw .D2T1 *--b13,a15:a14
[!a2] ldndw .D2T2 *b17++,b19:b18
ldndw .D1T1 *a21--,a23:a22
[!b2] ldndw .D2T2 *-b25[31],b27:b26
ldndw .D1T1 *+a29[0],a31:a30
ldndw .D1T1 *-a0(31),a3:a2
ldndw .D1T1 *-a4[a5],a7:a6
ldndw .D1T1 *+a7(a8),a9:a8
ldndw .D1T1 *--a10[11],a13:a12
ldndw .D1T1 *++a13(16),a15:a14
ldndw .D1T1 *a16--(24),a19:a18
ldndw .D1T1 *a19++(30),a21:a20
ldndw .D1T1 *--a22[a23],a25:a24
ldndw .D1T1 *++a25(a26),a27:a26
ldndw .D1T1 *a28--[a29],a31:a30
ldndw .D1T1 *a31++(a0),a1:a0
ldnw .D1T1 *a5,a7
[b2] ldnw .D1T2 *++a9,b11
ldnw .D2T1 *--b13,a15
[!a2] ldnw .D2T2 *b17++,b19
ldnw .D1T1 *a21--,a23
[!b2] ldnw .D2T2 *-b25[31],b27
ldnw .D1T1 *+a29[0],a31
ldnw .D1T1 *-a0(124),a2
ldnw .D1T1 *-a4[a5],a6
ldnw .D1T1 *+a7[a8],a9
ldnw .D1T1 *--a10[11],a12
ldnw .D1T1 *++a13(16),a15
ldnw .D1T1 *a16--(20),a18
ldnw .D1T1 *a19++(24),a21
ldnw .D1T1 *--a22[a23],a24
ldnw .D1T1 *++a25[a26],a27
ldnw .D1T1 *a28--[a29],a30
ldnw .D1T1 *a31++[a0],a1
ldw .D1T1 *a5,a7
[b2] ldw .D1T2 *++a9,b11
ldw .D2T1 *--b13,a15
[!a2] ldw .D2T2 *b17++,b19
ldw .D1T1 *a21--,a23
[!b2] ldw .D2T2 *-b25[31],b27
ldw .D1T1 *+a29[0],a31
ldw .D1T1 *-a0(124),a2
ldw .D1T1 *-a4[a5],a6
ldw .D1T1 *+a7[a8],a9
ldw .D1T1 *--a10[11],a12
ldw .D1T1 *++a13(16),a15
ldw .D1T1 *a16--(20),a18
ldw .D1T1 *a19++(24),a21
ldw .D1T1 *--a22[a23],a24
ldw .D1T1 *++a25[a26],a27
ldw .D1T1 *a28--[a29],a30
ldw .D1T1 *a31++[a0],a1
[a0] ldw .D2T1 *+b14(131068),a15
ldw .D2T2 *+b15[32767],b16
lmbd .L1 a5,a8,a13
[b0] lmbd .L1X a21,b2,a23
[!a0] lmbd .L2 b25,b16,b9
lmbd .L2X b1,a2,b3
lmbd .L1 0,a8,a13
[!b0] lmbd .L1X 1,b2,a23
[a1] lmbd .L2 15,b16,b9
lmbd .L2X -16,a2,b3
max2 .L1 a1,a2,a3
[b1] max2 .L1X a4,b5,a6
[!a1] max2 .L2 b7,b8,b9
max2 .L2X b10,a11,b12
max2 .S1 a1,a2,a3
[!b1] max2 .S1X a4,b5,a6
max2 .S2 b7,b8,b9
[a2] max2 .S2X b10,a11,b12
[b2] maxu4 .L1 a13,a14,a15
maxu4 .L1X a16,b17,a18
maxu4 .L2 b19,b20,b21
[!a2] maxu4 .L2X b22,a23,b24
min2 .L1 a1,a2,a3
[!b2] min2 .L1X a4,b5,a6
[a0] min2 .L2 b7,b8,b9
min2 .L2X b10,a11,b12
min2 .S1 a1,a2,a3
[b0] min2 .S1X a4,b5,a6
min2 .S2 b7,b8,b9
[!a0] min2 .S2X b10,a11,b12
[!b0] minu4 .L1 a13,a14,a15
minu4 .L1X a16,b17,a18
minu4 .L2 b19,b20,b21
[a1] minu4 .L2X b22,a23,b24
mpy .M1 a25,a26,a27
[b1] mpy .M1X a28,b29,a30
[!a1] mpy .M2 b31,b0,b1
mpy .M2X b2,a3,b4
[!b1] mpy .M1 -16,a5,a6
mpy .M1X 15,b7,a8
mpy .M2 5,b9,b10
[a2] mpy .M2X -4,a11,b12
mpydp .M1 a1:a0,a3:a2,a5:a4
mpydp .M2X b1:b0,a1:a0,b1:b0
[b2] mpydp .M2 b7:b6,b9:b8,b11:b10
mpyh .M1 a0,a1,a2
[!a2] mpyh .M1X a3,b4,a5
[!b2] mpyh .M2 b6,b7,b8
mpyh .M2X b9,a10,b11
mpyhi .M1 a0,a1,a3:a2
[a0] mpyhi .M1X a3,b4,a5:a4
[b0] mpyhi .M2 b6,b7,b9:b8
mpyhi .M2X b9,a10,b11:b10
mpyhir .M1 a0,a1,a2
[!a0] mpyhir .M1X a3,b4,a5
[!b0] mpyhir .M2 b6,b7,b8
mpyhir .M2X b9,a10,b11
mpyhl .M1 a0,a1,a2
[a1] mpyhl .M1X a3,b4,a5
[b1] mpyhl .M2 b6,b7,b8
mpyhl .M2X b9,a10,b11
mpyhlu .M1 a0,a1,a2
[!a1] mpyhlu .M1X a3,b4,a5
[!b1] mpyhlu .M2 b6,b7,b8
mpyhlu .M2X b9,a10,b11
mpyhslu .M1 a0,a1,a2
[a2] mpyhslu .M1X a3,b4,a5
[b2] mpyhslu .M2 b6,b7,b8
mpyhslu .M2X b9,a10,b11
mpyhsu .M1 a0,a1,a2
[!a2] mpyhsu .M1X a3,b4,a5
[!b2] mpyhsu .M2 b6,b7,b8
mpyhsu .M2X b9,a10,b11
mpyhu .M1 a0,a1,a2
[a0] mpyhu .M1X a3,b4,a5
[b0] mpyhu .M2 b6,b7,b8
mpyhu .M2X b9,a10,b11
mpyhuls .M1 a0,a1,a2
[!a0] mpyhuls .M1X a3,b4,a5
[!b0] mpyhuls .M2 b6,b7,b8
mpyhuls .M2X b9,a10,b11
mpyhus .M1 a0,a1,a2
[a1] mpyhus .M1X a3,b4,a5
[b1] mpyhus .M2 b6,b7,b8
mpyhus .M2X b9,a10,b11
[!a1] mpyi .M1 a0,a1,a2
mpyi .M1X a3,b4,a5
[!b1] mpyi .M2 b6,b7,b8
mpyi .M2X b9,a10,b11
[a2] mpyi .M1 -16,a1,a2
mpyi .M1X 15,b4,a5
[b2] mpyi .M2 7,b7,b8
mpyi .M2X -6,a10,b11
mpyid .M1 a0,a1,a3:a2
[!a2] mpyid .M1X a3,b4,a5:a4
[!b2] mpyid .M2 b6,b7,b9:b8
mpyid .M2X b9,a10,b11:b10
mpyid .M1 -16,a1,a3:a2
[a0] mpyid .M1X 2,b4,a5:a4
mpyid .M2 15,b7,b9:b8
[b0] mpyid .M2X -7,a10,b11:b10
mpyih .M1 a0,a1,a3:a2
[!a0] mpyih .M1X b4,a3,a5:a4
[!b0] mpyih .M2 b6,b7,b9:b8
mpyih .M2X a10,b9,b11:b10
[a1] mpyihr .M1 a0,a1,a2
mpyihr .M1X b4,a3,a5
[b1] mpyihr .M2 b6,b7,b8
mpyihr .M2X a10,b9,b11
mpyil .M1 a0,a1,a3:a2
[!a1] mpyil .M1X b4,a3,a5:a4
mpyil .M2 b6,b7,b9:b8
[!b1] mpyil .M2X a10,b9,b11:b10
[a2] mpyilr .M1 a0,a1,a2
mpyilr .M1X b4,a3,a5
mpyilr .M2 b6,b7,b8
[b2] mpyilr .M2X a10,b9,b11
mpylh .M1 a0,a1,a2
[!a2] mpylh .M1X a3,b4,a5
[!b2] mpylh .M2 b6,b7,b8
mpylh .M2X b9,a10,b11
mpylhu .M1 a0,a1,a2
[a0] mpylhu .M1X a3,b4,a5
[b0] mpylhu .M2 b6,b7,b8
mpylhu .M2X b9,a10,b11
mpyli .M1 a0,a1,a3:a2
[!a0] mpyli .M1X a3,b4,a5:a4
[!b0] mpyli .M2 b6,b7,b9:b8
mpyli .M2X b9,a10,b11:b10
mpylir .M1 a0,a1,a2
[a1] mpylir .M1X a3,b4,a5
mpylir .M2 b6,b7,b8
[b1] mpylir .M2X b9,a10,b11
[!a1] mpylshu .M1 a0,a1,a2
mpylshu .M1X a3,b4,a5
mpylshu .M2 b6,b7,b8
[!b1] mpylshu .M2X b9,a10,b11
mpyluhs .M1 a0,a1,a2
[a2] mpyluhs .M1X a3,b4,a5
mpyluhs .M2 b6,b7,b8
[b2] mpyluhs .M2X b9,a10,b11
mpysp .M1 a0,a1,a2
[!a2] mpysp .M1X a3,b4,a5
mpysp .M2 b6,b7,b8
[!b2] mpysp .M2X b9,a10,b11
[a0] mpyspdp .M1 a12,a15:a14,a17:a16
mpyspdp .M1X a18,b19:b18,a21:a20
mpyspdp .M2 b22,b25:b24,b27:b26
[b0] mpyspdp .M2X b29,a31:a30,b1:b0
mpysp2dp .M1 a0,a1,a3:a2
[!a0] mpysp2dp .M1X a3,b4,a5:a4
[!b0] mpysp2dp .M2 b6,b7,b9:b8
mpysp2dp .M2X b9,a10,b11:b10
[a1] mpysu .M1 a0,a1,a2
mpysu .M1X a3,b4,a5
[b1] mpysu .M2 b6,b7,b8
mpysu .M2X b9,a10,b11
[!a1] mpysu .M1 -16,a1,a2
mpysu .M1X 15,b4,a5
mpysu .M2 3,b7,b8
[!b1] mpysu .M2X -9,a10,b11
mpysu4 .M1 a0,a1,a3:a2
[!a0] mpysu4 .M1X a3,b4,a5:a4
[!b0] mpysu4 .M2 b6,b7,b9:b8
mpysu4 .M2X b9,a10,b11:b10
[a1] mpyu .M1 a0,a1,a2
mpyu .M1X a3,b4,a5
mpyu .M2 b6,b7,b8
[b1] mpyu .M2X b9,a10,b11
mpyu4 .M1 a0,a1,a3:a2
[!a1] mpyu4 .M1X a3,b4,a5:a4
[!b1] mpyu4 .M2 b6,b7,b9:b8
mpyu4 .M2X b9,a10,b11:b10
[a2] mpyus .M1 a0,a1,a2
mpyus .M1X a3,b4,a5
mpyus .M2 b6,b7,b8
[b2] mpyus .M2X b9,a10,b11
mpyus4 .M1 a0,a1,a3:a2
[!a2] mpyus4 .M1X b4,a3,a5:a4
[!b2] mpyus4 .M2 b6,b7,b9:b8
mpyus4 .M2X a10,b9,b11:b10
mpy2 .M1 a0,a1,a3:a2
[a0] mpy2 .M1X a3,b4,a5:a4
[b0] mpy2 .M2 b6,b7,b9:b8
mpy2 .M2X b9,a10,b11:b10
mpy2ir .M1 a0,a1,a3:a2
mpy2ir .M1X a3,b4,a5:a4
mpy2ir .M2 b6,b7,b9:b8
mpy2ir .M2X b9,a10,b11:b10
[!a0] mpy32 .M1 a0,a1,a2
mpy32 .M1X a3,b4,a5
mpy32 .M2 b6,b7,b8
[!b0] mpy32 .M2X b9,a10,b11
mpy32 .M1 a0,a1,a3:a2
[a1] mpy32 .M1X a3,b4,a5:a4
[b1] mpy32 .M2 b6,b7,b9:b8
mpy32 .M2X b9,a10,b11:b10
mpy32su .M1 a0,a1,a3:a2
[!a1] mpy32su .M1X a3,b4,a5:a4
[!b1] mpy32su .M2 b6,b7,b9:b8
mpy32su .M2X b9,a10,b11:b10
mpy32u .M1 a0,a1,a3:a2
[a2] mpy32u .M1X a3,b4,a5:a4
[b2] mpy32u .M2 b6,b7,b9:b8
mpy32u .M2X b9,a10,b11:b10
mpy32us .M1 a0,a1,a3:a2
[!a2] mpy32us .M1X a3,b4,a5:a4
[!b2] mpy32us .M2 b6,b7,b9:b8
mpy32us .M2X b9,a10,b11:b10
[a0] mv .L1 a5,a7
mv .L1X b8,a13
[b0] mv .L2 b12,b15
mv .L2X a17,b19
[!a0] mv .S1 a5,a7
mv .S1X b8,a13
mv .S2 b12,b15
[!b0] mv .S2X a17,b19
[a1] mv .D1 a5,a7
mv .D1X b8,a13
[b1] mv .D2 b12,b15
mv .D2X a17,b19
[a0] mvc .S2 amr,b5
mvc .S2 b6,amr
[b0] mvc .S2X a7,amr
mvc .S2 csr,b8
mvc .S2 b8,csr
mvc .S2 dnum,b9
mvc .S2 b10,ecr
mvc .S2 efr,b11
mvc .S2 fadcr,b12
mvc .S2 b13,fadcr
mvc .S2 faucr,b14
mvc .S2 b15,faucr
mvc .S2 fmcr,b16
mvc .S2 b17,fmcr
mvc .S2 gfpgfr,b18
mvc .S2 b19,gfpgfr
mvc .S2 gplya,b20
mvc .S2 b21,gplya
mvc .S2 gplyb,b22
mvc .S2 b23,gplyb
mvc .S2 b24,icr
mvc .S2 ier,b25
mvc .S2 b26,ier
mvc .S2 ierr,b27
mvc .S2 b28,ierr
mvc .S2 ifr,b29
mvc .S2 ilc,b30
mvc .S2 b31,ilc
mvc .S2 irp,b0
mvc .S2 b1,irp
mvc .S2 b2,isr
mvc .S2 istp,b3
mvc .S2 b4,istp
mvc .S2 itsr,b5
mvc .S2 b6,itsr
mvc .S2 nrp,b7
mvc .S2 b8,nrp
mvc .S2 ntsr,b9
mvc .S2 b10,ntsr
mvc .S2 pce1,b11
mvc .S2 rep,b12
mvc .S2 b13,rep
mvc .S2 rilc,b14
mvc .S2 b15,rilc
mvc .S2 ssr,b16
mvc .S2 b17,ssr
mvc .S2 tsch,b18
mvc .S2 tscl,b19
mvc .S2 b20,tscl
mvc .S2 tsr,b21
mvc .S2 b22,tsr
.word 0x0001e3e2
.word 0x0005e3e2
.word 0x0181e3a2
.word 0x0201e3a2
.word 0x0301e3a2
.word 0x0101e3a2
.word 0x0281e3a2
.word 0x0381e3a2
.word 0x004203e2
mvd .M1 a4,a5
[!a0] mvd .M1X b6,a7
[!b0] mvd .M2 b8,b9
mvd .M2X a10,b11
[!b1] mvk .S1 -32768,a5
mvk .S2 32767,b4
mvk .L1 -16,a4
[a1] mvk .L2 15,b4
[b1] mvk .D1 6,a4
mvk .D2 -9,b12
mvkh .S1 0x12345678,a6
[a2] mvkh .S2 0xfedcba98,b7
[b2] mvklh .S1 0x12345678,a6
mvklh .S2 0xfedcba98,b7
mvkl .S1 0x12345678,a6
[!a2] mvkl .S2 0xfedcba98,b7
neg .S1 a5,a6
[a0] neg .S1X b7,a8
[b0] neg .S2 b9,b10
neg .S2X a11,b12
[!a0] neg .L1 a13,a14
neg .L1X b15,a16
neg .L2 b17,b18
[!b0] neg .L2X a19,b20
[b1] neg .L1 a21:a20,a23:a22
neg .L2 b25:b24,b27:b26
nop 1
nop 2
nop
nop 3
nop 4
nop 5
nop 6
nop 7
nop 8
nop 9
[!b2] norm .L1 a4,a5
norm .L1X b6,a7
norm .L2 b8,b9
[a0] norm .L2X a10,b11
norm .L1 a5:a4,a6
[b0] norm .L2 b9:b8,b10
not .L1 a1,a2
[b2] not .L1X b3,a4
[!a2] not .L2 b5,b6
not .L2X a7,b8
[!b2] not .S1 a1,a2
not .S1X b3,a4
not .S2 b5,b6
[a0] not .S2X a7,b8
[b0] not .D1 a1,a2
not .D1X b3,a4
not .D2 b5,b6
[!a0] not .D2X a7,b8
[!a0] or .D1 a1,a2,a3
or .D1X a4,b5,a6
or .D2 b7,b8,b9
[!b0] or .D2X b10,a11,b12
or .D1 -16,a2,a3
[a1] or .D1X 11,b5,a6
[b1] or .D2 15,b8,b9
or .D2X -13,a11,b12
[!a1] or .L1 a1,a2,a3
or .L1X a4,b5,a6
or .L2 b7,b8,b9
[!b1] or .L2X b10,a11,b12
or .L1 -16,a2,a3
[a2] or .L1X 11,b5,a6
[b2] or .L2 15,b8,b9
or .L2X -13,a11,b12
[!a2] or .S1 a1,a2,a3
or .S1X a4,b5,a6
or .S2 b7,b8,b9
[!b2] or .S2X b10,a11,b12
or .S1 -16,a2,a3
[a0] or .S1X 11,b5,a6
[b0] or .S2 15,b8,b9
or .S2X -13,a11,b12
[!a0] pack2 .L1 a1,a2,a3
pack2 .L1X a5,b8,a13
pack2 .L2 b21,b2,b23
[!b0] pack2 .L2X b25,a16,b9
[a1] pack2 .S1 a1,a2,a3
pack2 .S1X a5,b8,a13
pack2 .S2 b21,b2,b23
[b1] pack2 .S2X b25,a16,b9
[!a1] packh2 .L1 a1,a2,a3
packh2 .L1X a5,b8,a13
packh2 .L2 b21,b2,b23
[!b1] packh2 .L2X b25,a16,b9
[a2] packh2 .S1 a1,a2,a3
packh2 .S1X a5,b8,a13
packh2 .S2 b21,b2,b23
[b2] packh2 .S2X b25,a16,b9
[!a2] packh4 .L1 a1,a2,a3
packh4 .L1X a5,b8,a13
packh4 .L2 b21,b2,b23
[!b2] packh4 .L2X b25,a16,b9
[a0] packhl2 .L1 a1,a2,a3
packhl2 .L1X a5,b8,a13
packhl2 .L2 b21,b2,b23
[b0] packhl2 .L2X b25,a16,b9
packhl2 .S1 a1,a2,a3
[!a0] packhl2 .S1X a5,b8,a13
[!b0] packhl2 .S2 b21,b2,b23
packhl2 .S2X b25,a16,b9
[a1] packlh2 .L1 a1,a2,a3
packlh2 .L1X a5,b8,a13
packlh2 .L2 b21,b2,b23
[b1] packlh2 .L2X b25,a16,b9
packlh2 .S1 a1,a2,a3
[!a1] packlh2 .S1X a5,b8,a13
[!b1] packlh2 .S2 b21,b2,b23
packlh2 .S2X b25,a16,b9
[a2] packl4 .L1 a1,a2,a3
packl4 .L1X a5,b8,a13
packl4 .L2 b21,b2,b23
[b2] packl4 .L2X b25,a16,b9
.word 0x03100b60
rcpdp .S1 a5:a4,a7:a6
[!a2] rcpdp .S2 b9:b8,b11:b10
.word 0x0317eb60
rcpsp .S1 a0,a1
[!b2] rcpsp .S1X b2,a3
[a0] rcpsp .S2 b4,b5
rcpsp .S2X a6,b7
rint
[b0] rotl .M1 a0,a1,a2
rotl .M1X b3,a4,a5
rotl .M2 b6,b7,b8
[!a0] rotl .M2X a9,b10,b11
rotl .M1 a12,0,a13
[!b0] rotl .M1X b14,31,a15
[a1] rotl .M2 b16,17,b17
rotl .M2X a18,25,b19
rpack2 .S1 a1,a2,a3
rpack2 .S1X a4,b5,a6
rpack2 .S2 b7,b8,b9
rpack2 .S2X b10,a11,b12
.word 0x03100ba0
rsqrdp .S1 a5:a4,a7:a6
[b1] rsqrdp .S2 b9:b8,b11:b10
.word 0x0317eba0
rsqrsp .S1 a0,a1
[!a1] rsqrsp .S1X b2,a3
[!b1] rsqrsp .S2 b4,b5
rsqrsp .S2X a6,b7
sadd .L1 a1,a2,a3
[a2] sadd .L1X a4,b5,a6
[b2] sadd .L2 b7,b8,b9
sadd .L2X b10,a11,b12
[!a2] sadd .L1 a13,a15:a14,a17:a16
sadd .L1X b18,a21:a20,a23:a22
sadd .L2 b24,b27:b26,b29:b28
[!b2] sadd .L2X a30,b1:b0,b3:b2
sadd .L1 -16,a4,a5
[a0] sadd .L1X 15,b6,a7
[b0] sadd .L2 12,b8,b9
sadd .L2X -11,a10,b11
sadd .L1 -16,a13:a12,a15:a14
[!a0] sadd .L2 15,b21:b20,b23:b22
[!b0] sadd .S1 a28,a29,a30
sadd .S1X a31,b0,a1
sadd .S2 b2,b3,b4
[a1] sadd .S2X b5,a6,b7
sadd2 .S1 a1,a2,a3
[b1] sadd2 .S1X a4,b5,a6
[!a1] sadd2 .S2 b7,b8,b9
sadd2 .S2X b10,a11,b12
saddsub .L1 a0,a1,a3:a2
saddsub .L1X a4,b5,a7:a6
saddsub .L2 b8,b9,b11:b10
saddsub .L2X b12,a13,b15:b14
saddsub2 .L1 a0,a1,a3:a2
saddsub2 .L1X a4,b5,a7:a6
saddsub2 .L2 b8,b9,b11:b10
saddsub2 .L2X b12,a13,b15:b14
[!b1] saddsu2 .S1 a16,a17,a18
saddsu2 .S1X b19,a20,a21
saddsu2 .S2 b22,b23,b24
[a2] saddsu2 .S2X a25,b26,b27
saddus2 .S1 a28,a29,a30
[b2] saddus2 .S1X a31,b0,a1
[!a2] saddus2 .S2 b2,b3,b4
saddus2 .S2X b5,a6,b7
saddu4 .S1 a28,a29,a30
[!b2] saddu4 .S1X a31,b0,a1
[a0] saddu4 .S2 b2,b3,b4
saddu4 .S2X b5,a6,b7
[b0] sat .L1 a3:a2,a20
sat .L2 b7:b6,b15
set .S1 a1,31,0,a2
[!a0] set .S2 b3,0,31,b4
set .S1 a5,a6,a7
[!b0] set .S1X b8,a9,a10
[a1] set .S2 b11,b12,b13
set .S2X a14,b15,b16
shfl .M1 a17,a18
[b1] shfl .M1X b19,a20
[!a1] shfl .M2 b21,b22
shfl .M2X a23,b24
shfl3 .L1 a0,a1,a3:a2
shfl3 .L1X a4,b5,a7:a6
shfl3 .L2 b8,b9,b11:b10
shfl3 .L2X b12,a13,b15:b14
shl .S1 a1,a2,a3
[!b1] shl .S1X b4,a5,a6
[a2] shl .S2 b7,b8,b9
shl .S2X a10,b11,b12
[b2] shl .S1 a15:a14,a16,a19:a18
shl .S2 b21:b20,b22,b25:b24
[!a2] shl .S1 a26,a27,a29:a28
shl .S1X b30,a31,a1:a0
shl .S2 b2,b3,b5:b4
[!b2] shl .S2X a6,b7,b9:b8
shl .S1 a1,0,a3
[a0] shl .S1X b4,31,a6
[b0] shl .S2 b7,17,b9
shl .S2X a10,12,b12
[!a0] shl .S1 a15:a14,0,a19:a18
shl .S2 b21:b20,31,b25:b24
[!b0] shl .S1 a26,31,a29:a28
shl .S1X b30,0,a1:a0
shl .S2 b2,5,b5:b4
[a1] shl .S2X a6,9,b9:b8
shlmb .L1 a1,a2,a3
[b1] shlmb .L1X a4,b5,a6
[!a1] shlmb .L2 b7,b8,b9
shlmb .L2X b10,a11,b12
shlmb .S1 a1,a2,a3
[!b1] shlmb .S1X a4,b5,a6
[a2] shlmb .S2 b7,b8,b9
shlmb .S2X b10,a11,b12
shr .S1 a1,a2,a3
[b2] shr .S1X b4,a5,a6
[!a2] shr .S2 b7,b8,b9
shr .S2X a10,b11,b12
[!b2] shr .S1 a15:a14,a16,a19:a18
shr .S2 b21:b20,b22,b25:b24
shr .S1 a1,0,a3
[a0] shr .S1X b4,31,a6
[b0] shr .S2 b7,17,b9
shr .S2X a10,12,b12
[!a0] shr .S1 a15:a14,0,a19:a18
shr .S2 b21:b20,31,b25:b24
shr2 .S1 a1,a2,a3
[!b0] shr2 .S1X b4,a5,a6
[a1] shr2 .S2 b7,b8,b9
shr2 .S2X a10,b11,b12
shr2 .S1 a1,31,a3
[b1] shr2 .S1X b4,0,a6
[!a1] shr2 .S2 b7,5,b9
shr2 .S2X a10,25,b12
shrmb .S1 a1,a2,a3
[!b1] shrmb .S1X a4,b5,a6
[a2] shrmb .S2 b7,b8,b9
shrmb .S2X b10,a11,b12
shru .S1 a1,a2,a3
[b2] shru .S1X b4,a5,a6
[!a2] shru .S2 b7,b8,b9
shru .S2X a10,b11,b12
[!b2] shru .S1 a15:a14,a16,a19:a18
shru .S2 b21:b20,b22,b25:b24
shru .S1 a1,0,a3
[a0] shru .S1X b4,31,a6
[b0] shru .S2 b7,17,b9
shru .S2X a10,12,b12
[!a0] shru .S1 a15:a14,0,a19:a18
shru .S2 b21:b20,31,b25:b24
shru2 .S1 a1,a2,a3
[!b0] shru2 .S1X b4,a5,a6
[a1] shru2 .S2 b7,b8,b9
shru2 .S2X a10,b11,b12
shru2 .S1 a1,31,a3
[b1] shru2 .S1X b4,0,a6
[!a1] shru2 .S2 b7,5,b9
shru2 .S2X a10,25,b12
smpy .M1 a5,a6,a7
[!b1] smpy .M1X a8,b9,a10
[a2] smpy .M2 b11,b12,b13
smpy .M2X b14,a15,b16
smpyh .M1 a5,a6,a7
[b2] smpyh .M1X a8,b9,a10
[!a2] smpyh .M2 b11,b12,b13
smpyh .M2X b14,a15,b16
smpyhl .M1 a5,a6,a7
[!b2] smpyhl .M1X a8,b9,a10
[a0] smpyhl .M2 b11,b12,b13
smpyhl .M2X b14,a15,b16
smpylh .M1 a5,a6,a7
[b0] smpylh .M1X a8,b9,a10
[!a0] smpylh .M2 b11,b12,b13
smpylh .M2X b14,a15,b16
[!b0] smpy2 .M1 a17,a18,a21:a20
smpy2 .M1X a22,b23,a25:a24
smpy2 .M2 b26,b27,b29:b28
[a1] smpy2 .M2X b30,a31,b1:b0
smpy32 .M1 a17,a18,a21
smpy32 .M1X a22,b23,a25
smpy32 .M2 b26,b27,b29
smpy32 .M2X b30,a31,b1
spack2 .S1 a1,a2,a3
[b1] spack2 .S1X a4,b5,a6
[!a1] spack2 .S2 b7,b8,b9
spack2 .S2X b10,a11,b12
spacku4 .S1 a1,a2,a3
[!b1] spacku4 .S1X a4,b5,a6
[a2] spacku4 .S2 b7,b8,b9
spacku4 .S2X b10,a11,b12
[b2] spdp .S1 a13,a15:a14
spdp .S1X b15,a17:a16
spdp .S2 b18,b21:b20
[!a2] spdp .S2X a21,b23:b22
[!b2] spint .L1 a13,a15
spint .L1X b15,a17
spint .L2 b18,b21
[a0] spint .L2X a21,b23
[b0] sptrunc .L1 a13,a15
sptrunc .L1X b15,a17
sptrunc .L2 b18,b21
[!a0] sptrunc .L2X a21,b23
sshl .S1 a1,a2,a3
[!b0] sshl .S1X b4,a5,a6
[a1] sshl .S2 b7,b8,b9
sshl .S2X a10,b11,b12
sshl .S1 a13,31,a14
[b1] sshl .S1X b15,0,a16
[!a1] sshl .S2 b17,25,b18
sshl .S2X a19,7,b20
sshvl .M1 a1,a2,a3
[!b1] sshvl .M1X b4,a5,a6
[a2] sshvl .M2 b7,b8,b9
sshvl .M2X a10,b11,b12
sshvr .M1 a1,a2,a3
[!b1] sshvr .M1X b4,a5,a6
[a2] sshvr .M2 b7,b8,b9
sshvr .M2X a10,b11,b12
[b2] ssub .L1 a1,a2,a3
ssub .L1X a4,b5,a6
ssub .L2 b7,b8,b9
[!a2] ssub .L2X b10,a11,b12
ssub .L1X b13,a14,a15
[!b2] ssub .L2X a16,b17,b18
.word 0x000003f8
ssub .L1 -16,a19,a20
[a0] ssub .L1X 15,b21,a22
[b0] ssub .L2 7,b23,b24
ssub .L2X -9,a25,b26
ssub .L1 -16,a29:a28,a31:a30
[!a0] ssub .L2 15,b1:b0,b3:b2
ssub2 .L1 a1,a2,a3
[!b0] ssub2 .L1X a4,b5,a6
[a1] ssub2 .L2 b7,b8,b9
ssub2 .L2X b10,a11,b12
stb .D1T1 a7,*a5
[b2] stb .D1T2 b11,*++a9
stb .D2T1 a15,*--b13
[!a2] stb .D2T2 b19,*b17++
stb .D1T1 a23,*a21--
[!b2] stb .D2T2 b27,*-b25[31]
stb .D1T1 a31,*+a29[0]
stb .D1T1 a2,*-a0(2)
stb .D1T1 a6,*-a4[a5]
stb .D1T1 a9,*+a7[a8]
stb .D1T1 a12,*--a10[11]
stb .D1T1 a15,*++a13(14)
stb .D1T1 a18,*a16--(17)
stb .D1T1 a21,*a19++(20)
stb .D1T1 a24,*--a22[a23]
stb .D1T1 a27,*++a25[a26]
stb .D1T1 a30,*a28--[a29]
stb .D1T1 a1,*a31++[a0]
[a0] stb .D2T1 a15,*+b14(32767)
stb .D2T2 b16,*+b15[32767]
stdw .D1T1 a7:a6,*a5
[b2] stdw .D1T2 b11:b10,*++a9
stdw .D2T1 a15:a14,*--b13
[!a2] stdw .D2T2 b19:b18,*b17++
stdw .D1T1 a23:a22,*a21--
[!b2] stdw .D2T2 b27:b26,*-b25[31]
stdw .D1T1 a31:a30,*+a29[0]
stdw .D1T1 a3:a2,*-a0(248)
stdw .D1T1 a7:a6,*-a4[a5]
stdw .D1T1 a9:a8,*+a7[a8]
stdw .D1T1 a13:a12,*--a10[11]
stdw .D1T1 a15:a14,*++a13(16)
stdw .D1T1 a19:a18,*a16--(24)
stdw .D1T1 a21:a20,*a19++(32)
stdw .D1T1 a25:a24,*--a22[a23]
stdw .D1T1 a27:a26,*++a25[a26]
stdw .D1T1 a31:a30,*a28--[a29]
stdw .D1T1 a1:a0,*a31++[a0]
sth .D1T1 a7,*a5
[b2] sth .D1T2 b11,*++a9
sth .D2T1 a15,*--b13
[!a2] sth .D2T2 b19,*b17++
sth .D1T1 a23,*a21--
[!b2] sth .D2T2 b27,*-b25[31]
sth .D1T1 a31,*+a29[0]
sth .D1T1 a2,*-a0(62)
sth .D1T1 a6,*-a4[a5]
sth .D1T1 a9,*+a7[a8]
sth .D1T1 a12,*--a10[11]
sth .D1T1 a15,*++a13(14)
sth .D1T1 a18,*a16--(18)
sth .D1T1 a21,*a19++(20)
sth .D1T1 a24,*--a22[a23]
sth .D1T1 a27,*++a25[a26]
sth .D1T1 a30,*a28--[a29]
sth .D1T1 a1,*a31++[a0]
[a0] sth .D2T1 a15,*+b14(65534)
sth .D2T2 b16,*+b15[32767]
stndw .D1T1 a7:a6,*a5
[b2] stndw .D1T2 b11:b10,*++a9
stndw .D2T1 a15:a14,*--b13
[!a2] stndw .D2T2 b19:b18,*b17++
stndw .D1T1 a23:a22,*a21--
[!b2] stndw .D2T2 b27:b26,*-b25[31]
stndw .D1T1 a31:a30,*+a29[0]
stndw .D1T1 a3:a2,*-a0(31)
stndw .D1T1 a7:a6,*-a4[a5]
stndw .D1T1 a9:a8,*+a7(a8)
stndw .D1T1 a13:a12,*--a10[11]
stndw .D1T1 a15:a14,*++a13(16)
stndw .D1T1 a19:a18,*a16--(24)
stndw .D1T1 a21:a20,*a19++(30)
stndw .D1T1 a25:a24,*--a22[a23]
stndw .D1T1 a27:a26,*++a25(a26)
stndw .D1T1 a31:a30,*a28--[a29]
stndw .D1T1 a1:a0,*a31++(a0)
stnw .D1T1 a7,*a5
[b2] stnw .D1T2 b11,*++a9
stnw .D2T1 a15,*--b13
[!a2] stnw .D2T2 b19,*b17++
stnw .D1T1 a23,*a21--
[!b2] stnw .D2T2 b27,*-b25[31]
stnw .D1T1 a31,*+a29[0]
stnw .D1T1 a2,*-a0(124)
stnw .D1T1 a6,*-a4[a5]
stnw .D1T1 a9,*+a7[a8]
stnw .D1T1 a12,*--a10[11]
stnw .D1T1 a15,*++a13(16)
stnw .D1T1 a18,*a16--(20)
stnw .D1T1 a21,*a19++(24)
stnw .D1T1 a24,*--a22[a23]
stnw .D1T1 a27,*++a25[a26]
stnw .D1T1 a30,*a28--[a29]
stnw .D1T1 a1,*a31++[a0]
stw .D1T1 a7,*a5
[b2] stw .D1T2 b11,*++a9
stw .D2T1 a15,*--b13
[!a2] stw .D2T2 b19,*b17++
stw .D1T1 a23,*a21--
[!b2] stw .D2T2 b27,*-b25[31]
stw .D1T1 a31,*+a29[0]
stw .D1T1 a2,*-a0(124)
stw .D1T1 a6,*-a4[a5]
stw .D1T1 a9,*+a7[a8]
stw .D1T1 a12,*--a10[11]
stw .D1T1 a15,*++a13(16)
stw .D1T1 a18,*a16--(20)
stw .D1T1 a21,*a19++(24)
stw .D1T1 a24,*--a22[a23]
stw .D1T1 a27,*++a25[a26]
stw .D1T1 a30,*a28--[a29]
stw .D1T1 a1,*a31++[a0]
[a0] stw .D2T1 a15,*+b14(131068)
stw .D2T2 b16,*+b15[32767]
sub .L1 a1,a2,a3
[b0] sub .L1X a4,b5,a6
[!a0] sub .L2 b7,b8,b9
sub .L2X b10,a11,b12
[!b0] sub .L1X b13,a14,a15
sub .L2X a16,b17,b18
.word 0x07b9a2f8
[a1] sub .L1 a19,a20,a23:a22
sub .L1X a24,b25,a27:a26
sub .L2 b28,b29,b31:b30
[b1] sub .L2X b0,a1,b3:b2
sub .L1X b4,a5,a7:a6
[!a1] sub .L2X a8,b9,b11:b10
.word 0x031486f8
sub .L1 -16,a12,a13
[!b1] sub .L1X 15,b14,a15
[a2] sub .L2 7,b16,b17
sub .L2X -9,a18,b19
sub .L1 -16,a21:a20,a23:a22
[b2] sub .L2 15,b25:b24,b27:b26
sub .S1 a1,a2,a3
[!a2] sub .S1X a4,b5,a6
[!b2] sub .S2 b7,b8,b9
sub .S2X b10,a11,b12
[a0] sub .S1X b13,a14,a15
sub .S2X a16,b17,b18
.word 0x07b5cd70
[b0] sub .S1 -16,a19,a20
sub .S1X 15,b21,a22
sub .S2 13,b23,b24
[!a0] sub .S2X -11,a25,b26
sub .D1 a27,a28,a29
[!b0] sub .D2 b30,b31,b0
[a1] sub .D1 a1,0,a2
sub .D2 b3,31,b4
sub .D1X a5,b6,a7
[b1] sub .D2X b8,a9,b10
.word 0x0398ab30
sub .L1 a5,16,a6
[a0] sub .L1X b11,-15,a30
sub .L2 b9,11,b10
sub .L2X a5,-14,b7
sub .L1 a3:a2,-5,a7:a6
[b0] sub .L2 b29:b28,7,b29:b28
sub .S1 a4,16,a11
sub .S1X b9,-13,a23
[!b0] sub .S2 b25,-15,b11
sub .S2X a1,4,b2
subab .D1 a1,a2,a3
[!a1] subab .D2 b4,b5,b6
subab .D1 a7,0,a8
[!b1] subab .D2 b9,31,b10
subabs4 .L1 a1,a2,a3
[a2] subabs4 .L1X a4,b5,a6
[b2] subabs4 .L2 b7,b8,b9
subabs4 .L2X b10,a11,b12
subah .D1 a1,a2,a3
[!a2] subah .D2 b4,b5,b6
[!b2] subah .D1 a7,0,a8
subah .D2 b9,31,b10
subaw .D1 a1,a2,a3
[a0] subaw .D2 b4,b5,b6
[b0] subaw .D1 a7,0,a8
subaw .D2 b9,31,b10
[!a0] subc .L1 a3,a4,a5
subc .L1X a6,b7,a8
subc .L2 b9,b10,b11
[!b0] subc .L2X b12,a13,b14
subdp .L1 a3:a2,a5:a4,a7:a6
[a1] subdp .L1X a9:a8,b11:b10,a13:a12
[b1] subdp .L2 b15:b14,b17:b16,b19:b18
subdp .L2X b21:b20,a23:a22,b25:b24
[!a1] subdp .L1X b27:b26,a29:a28,a31:a30
subdp .L2X a1:a0,b3:b2,b5:b4
.word 0x0f7343b8
subdp .S1 a3:a2,a5:a4,a7:a6
[a1] subdp .S1X a9:a8,b11:b10,a13:a12
[b1] subdp .S2 b15:b14,b17:b16,b19:b18
subdp .S2X b21:b20,a23:a22,b25:b24
[!a1] subdp .S1X b27:b26,a29:a28,a31:a30
subdp .S2X a1:a0,b3:b2,b5:b4
.word 0x0f6b8ef8
subsp .L1 a3,a5,a7
[a1] subsp .L1X a9,b11,a13
[b1] subsp .L2 b15,b17,b19
subsp .L2X b21,a23,b25
[!a1] subsp .L1X b27,a29,a31
subsp .L2X a1,b3,b5
.word 0x0ff762b8
subsp .S1 a3,a5,a7
[!b1] subsp .S1X a9,b11,a13
[a2] subsp .S2 b15,b17,b19
subsp .S2X b21,a23,b25
[b2] subsp .S1X b27,a29,a31
subsp .S2X a1,b3,b5
.word 0x0fefaeb8
subu .L1 a2,a3,a5:a4
[!a2] subu .L1X a6,b7,a9:a8
[!b2] subu .L2 b10,b11,b13:b12
subu .L2X b14,a15,b17:b16
[a0] subu .L1X b18,a19,a21:a20
subu .L2X a22,b23,b25:b24
.word 0x0a4e47f8
sub2 .L1 a1,a2,a3
[b0] sub2 .L1X a4,b5,a6
[!a0] sub2 .L2 b7,b8,b9
sub2 .L2X b10,a11,b12
sub2 .S1 a1,a2,a3
[!b0] sub2 .S1X a4,b5,a6
[a1] sub2 .S2 b7,b8,b9
sub2 .S2X b10,a11,b12
sub2 .D1 a1,a2,a3
[b1] sub2 .D1X a4,b5,a6
[!a1] sub2 .D2 b7,b8,b9
sub2 .D2X b10,a11,b12
sub4 .L1 a1,a2,a3
[!b1] sub4 .L1X a4,b5,a6
[a2] sub4 .L2 b7,b8,b9
sub4 .L2X b10,a11,b12
swap2 .L1 a3,a7
[b2] swap2 .L2 b9,b11
[!a2] swap2 .S1 a13,a15
swap2 .S2 b23,b29
[!b2] swap4 .L1 a1,a2
swap4 .L1X b3,a4
swap4 .L2 b5,b6
[a0] swap4 .L2X a7,b8
swe
swenr
unpkhu4 .L1 a1,a2
[b0] unpkhu4 .L1X b3,a4
[!a0] unpkhu4 .L2 b5,b6
unpkhu4 .L2X a7,b8
unpkhu4 .S1 a1,a2
[!b0] unpkhu4 .S1X b3,a4
[a1] unpkhu4 .S2 b5,b6
unpkhu4 .S2X a7,b8
unpklu4 .L1 a1,a2
[b1] unpklu4 .L1X b3,a4
[!a1] unpklu4 .L2 b5,b6
unpklu4 .L2X a7,b8
unpklu4 .S1 a1,a2
[!b1] unpklu4 .S1X b3,a4
[a2] unpklu4 .S2 b5,b6
unpklu4 .S2X a7,b8
xor .L1 a1,a2,a3
[b2] xor .L1X a4,b5,a6
[!a2] xor .L2 b7,b8,b9
xor .L2X b10,a11,b12
[!b2] xor .L1 -16,a13,a14
xor .L1X 15,b15,a16
xor .L2 3,b17,b18
[a0] xor .L2X -12,a19,b20
xor .S1 a1,a2,a3
[b0] xor .S1X a4,b5,a6
[!a0] xor .S2 b7,b8,b9
xor .S2X b10,a11,b12
[!b0] xor .S1 -16,a13,a14
xor .S1X 15,b15,a16
xor .S2 3,b17,b18
[a1] xor .S2X -12,a19,b20
xor .D1 a1,a2,a3
[b0] xor .D1X a4,b5,a6
[!a0] xor .D2 b7,b8,b9
xor .D2X b10,a11,b12
[!b0] xor .D1 -16,a13,a14
xor .D1X 15,b15,a16
xor .D2 3,b17,b18
[a1] xor .D2X -12,a19,b20
xormpy .M1 a1,a2,a3
xormpy .M1X a4,b5,a6
xormpy .M2 b7,b8,b9
xormpy .M2X b10,a11,b12
xpnd2 .M1 a13,a14
[b1] xpnd2 .M1X b15,a16
[!a1] xpnd2 .M2 b17,b18
xpnd2 .M2X a19,b20
xpnd4 .M1 a13,a14
[!b1] xpnd4 .M1X b15,a16
[a2] xpnd4 .M2 b17,b18
xpnd4 .M2X a19,b20
zero .L1 a1
[b2] zero .L2 b2
[!a2] zero .L1 a5:a4
zero .L2 b7:b6
zero .D1 a8
[!b2] zero .D2 b9
[a0] zero .S1 a10
zero .S2 b11
|
stsp/binutils-ia16
| 2,380
|
gas/testsuite/gas/tic6x/insns16-dinc.s
|
; Test C64x+ dinc compact instruction format
.text
dinc:
nop
.align 16
nop
.align 16
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0c05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe00000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe8c000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefe9c000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefeac000
.short 0x0e04
.short 0x1e04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefebc000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefecc000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefedc000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefeec000
.short 0x0c04
.short 0x1c04
.short 0x0e04
.short 0x0c0c
.short 0x0c05
.short 0x1c05
.short 0x0e05
.short 0x0c0d
.short 0x1c05
.short 0x0e05
.short 0x1e0d
.short 0x2e0d
.short 0x3e1d
.short 0x2e1d
.word 0xefefc000
.short 0x0c14
.short 0x1c14
.short 0x0e14
.short 0x0c1c
.short 0x0c15
.short 0x1c15
.short 0x0e15
.short 0x0c1d
.short 0x1c15
.short 0x0e15
.short 0x1e1d
.short 0x2e1d
.short 0x3e1d
.short 0x2e1d
.word 0xefefc000
|
stsp/binutils-ia16
| 5,445
|
gas/testsuite/gas/tic6x/reloc-bad-2.s
|
# Test expressions not representable by relocations.
.globl a
.globl b
.data
d:
.word $DSBT_INDEX(__c6xabi_DSBT_BASE)
.word $got(b)
.word $dpr_got(a)
.word $dpr_byte(b)
.word $dpr_hword(a)
.word $dpr_word(b)
.word $pcr_offset(b,f)
.text
.nocmp
.globl f
f:
addab .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
addab .D1X b14,$GOT(b),a5
addab .D1X b14,$DPR_GOT(b),a5
addab .D1X b14,$DPR_BYTE(b),a5
addab .D1X b14,$DPR_HWORD(b),a5
addab .D1X b14,$DPR_WORD(b),a5
addab .D1X b14,$PCR_OFFSET(b,f),a5
addah .D1X b14,$dsbt_index(__c6xabi_DSBT_BASE),a5
addah .D1X b14,$GOT(b),a5
addah .D1X b14,$DPR_GOT(b),a5
addah .D1X b14,$DPR_BYTE(b),a5
addah .D1X b14,$DPR_HWORD(b),a5
addah .D1X b14,$DPR_WORD(b),a5
addah .D1X b14,$PCR_OFFSET(b,f),a5
addaw .D1X b14,$DPR_GOT(b),a5
addaw .D1X b14,$DPR_BYTE(b),a5
addaw .D1X b14,$DPR_HWORD(b),a5
addaw .D1X b14,$DPR_WORD(b),a5
addaw .D1X b14,$PCR_OFFSET(b,f),a5
addk .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
addk .S1 $got(b),a7
addk .S1 $dpr_got(b),a7
addk .S1 $dpr_hword(b),a7
addk .S1 $dpr_word(b),a7
addk .S1 $pcr_offset(b,f),a7
mvk .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvk .S1 $got(b),a7
mvk .S1 $dpr_got(b),a7
mvk .S1 $dpr_hword(b),a7
mvk .S1 $dpr_word(b),a7
mvkh .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvkh .S1 $got(b),a7
mvklh .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvklh .S1 $got(b),a7
mvkl .S1 $dsbt_index(__c6xabi_DSBT_BASE),a7
mvkl .S1 $got(b),a7
addkpc .S2 $dsbt_index(__c6xabi_DSBT_BASE),b3,0
addkpc .S2 $GOT(b),b3,0
addkpc .S2 $DPR_GOT(b),b3,0
addkpc .S2 $DPR_BYTE(b),b3,0
addkpc .S2 $DPR_HWORD(b),b3,0
addkpc .S2 $DPR_WORD(b),b3,0
addkpc .S2 $PCR_OFFSET(b,f),b3,0
b .S1 $dsbt_index(__c6xabi_DSBT_BASE)
b .S1 $GOT(b)
b .S1 $DPR_GOT(b)
b .S1 $DPR_BYTE(b)
b .S1 $DPR_HWORD(b)
b .S1 $DPR_WORD(b)
b .S1 $PCR_OFFSET(b,f)
call .S1 $dsbt_index(__c6xabi_DSBT_BASE)
call .S1 $GOT(b)
call .S1 $DPR_GOT(b)
call .S1 $DPR_BYTE(b)
call .S1 $DPR_HWORD(b)
call .S1 $DPR_WORD(b)
call .S1 $PCR_OFFSET(b,f)
bdec .S1 $dsbt_index(__c6xabi_DSBT_BASE),a1
bdec .S1 $GOT(b),a1
bdec .S1 $DPR_GOT(b),a1
bdec .S1 $DPR_BYTE(b),a1
bdec .S1 $DPR_HWORD(b),a1
bdec .S1 $DPR_WORD(b),a1
bdec .S1 $PCR_OFFSET(b,f),a1
bpos .S2 $dsbt_index(__c6xabi_DSBT_BASE),b1
bpos .S2 $GOT(b),b1
bpos .S2 $DPR_GOT(b),b1
bpos .S2 $DPR_BYTE(b),b1
bpos .S2 $DPR_HWORD(b),b1
bpos .S2 $DPR_WORD(b),b1
bpos .S2 $PCR_OFFSET(b,f),b1
bnop .S1 $dsbt_index(__c6xabi_DSBT_BASE),1
bnop .S1 $GOT(b),1
bnop .S1 $DPR_GOT(b),1
bnop .S1 $DPR_BYTE(b),1
bnop .S1 $DPR_HWORD(b),1
bnop .S1 $DPR_WORD(b),1
bnop .S1 $PCR_OFFSET(b,f),1
callnop $dsbt_index(__c6xabi_DSBT_BASE),1
callnop $GOT(b),1
callnop $DPR_GOT(b),1
callnop $DPR_BYTE(b),1
callnop $DPR_HWORD(b),1
callnop $DPR_WORD(b),1
callnop $PCR_OFFSET(b,f),1
callp .S1 $dsbt_index(__c6xabi_DSBT_BASE),a3
callp .S1 $GOT(b),a3
callp .S1 $DPR_GOT(b),a3
callp .S1 $DPR_BYTE(b),a3
callp .S1 $DPR_HWORD(b),a3
callp .S1 $DPR_WORD(b),a3
callp .S1 $PCR_OFFSET(b,f),a3
callret .S1 $dsbt_index(__c6xabi_DSBT_BASE)
callret .S1 $GOT(b)
callret .S1 $DPR_GOT(b)
callret .S1 $DPR_BYTE(b)
callret .S1 $DPR_HWORD(b)
callret .S1 $DPR_WORD(b)
callret .S1 $PCR_OFFSET(b,f)
ret .S1 $dsbt_index(__c6xabi_DSBT_BASE)
ret .S1 $GOT(b)
ret .S1 $DPR_GOT(b)
ret .S1 $DPR_BYTE(b)
ret .S1 $DPR_HWORD(b)
ret .S1 $DPR_WORD(b)
ret .S1 $PCR_OFFSET(b,f)
retp .S1 $dsbt_index(__c6xabi_DSBT_BASE),a3
retp .S1 $GOT(b),a3
retp .S1 $DPR_GOT(b),a3
retp .S1 $DPR_BYTE(b),a3
retp .S1 $DPR_HWORD(b),a3
retp .S1 $DPR_WORD(b),a3
retp .S1 $PCR_OFFSET(b,f),a3
ldb .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldb .D2T2 *+b14($GOT(b)),b1
ldb .D2T2 *+b14($DPR_GOT(b)),b1
ldb .D2T2 *+b14($DPR_BYTE(b)),b1
ldb .D2T2 *+b14($DPR_HWORD(b)),b1
ldb .D2T2 *+b14($DPR_WORD(b)),b1
ldb .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldbu .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldbu .D2T2 *+b14($GOT(b)),b1
ldbu .D2T2 *+b14($DPR_GOT(b)),b1
ldbu .D2T2 *+b14($DPR_BYTE(b)),b1
ldbu .D2T2 *+b14($DPR_HWORD(b)),b1
ldbu .D2T2 *+b14($DPR_WORD(b)),b1
ldbu .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldh .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldh .D2T2 *+b14($GOT(b)),b1
ldh .D2T2 *+b14($DPR_GOT(b)),b1
ldh .D2T2 *+b14($DPR_BYTE(b)),b1
ldh .D2T2 *+b14($DPR_HWORD(b)),b1
ldh .D2T2 *+b14($DPR_WORD(b)),b1
ldh .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldhu .D2T2 *+b14($dsbt_index(__c6xabi_DSBT_BASE)),b1
ldhu .D2T2 *+b14($GOT(b)),b1
ldhu .D2T2 *+b14($DPR_GOT(b)),b1
ldhu .D2T2 *+b14($DPR_BYTE(b)),b1
ldhu .D2T2 *+b14($DPR_HWORD(b)),b1
ldhu .D2T2 *+b14($DPR_WORD(b)),b1
ldhu .D2T2 *+b14($PCR_OFFSET(b,f)),b1
ldw .D2T2 *+b14($DPR_GOT(b)),b1
ldw .D2T2 *+b14($DPR_BYTE(b)),b1
ldw .D2T2 *+b14($DPR_HWORD(b)),b1
ldw .D2T2 *+b14($DPR_WORD(b)),b1
ldw .D2T2 *+b14($PCR_OFFSET(b,f)),b1
stb .D2T2 b1,*+b14($dsbt_index(__c6xabi_DSBT_BASE))
stb .D2T2 b1,*+b14($GOT(b))
stb .D2T2 b1,*+b14($DPR_GOT(b))
stb .D2T2 b1,*+b14($DPR_BYTE(b))
stb .D2T2 b1,*+b14($DPR_HWORD(b))
stb .D2T2 b1,*+b14($DPR_WORD(b))
stb .D2T2 b1,*+b14($PCR_OFFSET(b,f))
sth .D2T2 b1,*+b14($dsbt_index(__c6xabi_DSBT_BASE))
sth .D2T2 b1,*+b14($GOT(b))
sth .D2T2 b1,*+b14($DPR_GOT(b))
sth .D2T2 b1,*+b14($DPR_BYTE(b))
sth .D2T2 b1,*+b14($DPR_HWORD(b))
sth .D2T2 b1,*+b14($DPR_WORD(b))
sth .D2T2 b1,*+b14($PCR_OFFSET(b,f))
stw .D2T2 b1,*+b14($DPR_GOT(b))
stw .D2T2 b1,*+b14($DPR_BYTE(b))
stw .D2T2 b1,*+b14($DPR_HWORD(b))
stw .D2T2 b1,*+b14($DPR_WORD(b))
stw .D2T2 b1,*+b14($PCR_OFFSET(b,f))
|
stsp/binutils-ia16
| 3,732
|
gas/testsuite/gas/tic6x/reloc-bad-6.s
|
# Test relocation overflow and insufficiently divisible values for
# PC-relative operands.
.text
.nocmp
f7_0:
nop
nop
nop
nop
nop
nop
nop
f7_28:
nop
f7_32:
.space 256
f7_288:
addkpc .S2 f7_32,b1,0
addkpc .S2 f7_28,b1,0
addkpc .S2 f7_32,b1,0
addkpc .S2 f7_0,b1,0
addkpc .S2 f7_544,b1,0
addkpc .S2 f7_540,b1,0
addkpc .S2 f7_288+1,b1,0
nop
f7_320:
.space 220
f7_540:
nop
f7_544:
nop
nop
nop
nop
nop
nop
nop
nop
f10_0:
nop
nop
nop
nop
nop
nop
nop
f10_28:
nop
f10_32:
.space 2048
f10_2080:
bdec .S1 f10_32,a1
bdec .S1 f10_28,a1
bdec .S1 f10_32,a1
bdec .S1 f10_0,a1
bdec .S1 f10_4128,a1
bdec .S1 f10_4124,a1
bdec .S1 f10_2080+1,a1
nop
f10_2112:
.space 2012
f10_4124:
nop
f10_4128:
nop
nop
nop
nop
nop
nop
nop
nop
g10_0:
nop
nop
nop
nop
nop
nop
nop
g10_28:
nop
g10_32:
.space 2048
g10_2080:
bpos .S1 g10_32,a1
bpos .S1 g10_28,a1
bpos .S1 g10_32,a1
bpos .S1 g10_0,a1
bpos .S1 g10_4128,a1
bpos .S1 g10_4124,a1
bpos .S1 g10_2080+1,a1
nop
g10_2112:
.space 2012
g10_4124:
nop
g10_4128:
nop
nop
nop
nop
nop
nop
nop
nop
f12_0:
nop
nop
nop
nop
nop
nop
nop
f12_28:
nop
f12_32:
.space 8192
f12_8224:
bnop f12_32,2
bnop f12_28,2
bnop f12_32,2
bnop f12_0,2
bnop f12_16416,2
bnop f12_16412,2
bnop f12_8224+1,2
nop
f12_8256:
.space 8156
f12_16412:
nop
f12_16416:
nop
nop
nop
nop
nop
nop
nop
nop
g12_0:
nop
nop
nop
nop
nop
nop
nop
g12_28:
nop
g12_32:
.space 8192
g12_8224:
callnop g12_32,2
callnop g12_28,2
callnop g12_32,2
callnop g12_0,2
callnop g12_16416,2
callnop g12_16412,2
callnop g12_8224+1,2
nop
g12_8256:
.space 8156
g12_16412:
nop
g12_16416:
nop
nop
nop
nop
nop
nop
nop
nop
f21_0:
nop
nop
nop
nop
nop
nop
nop
f21_28:
nop
f21_32:
.space 4194304
f21_4194336:
b .S1 f21_32
b .S1 f21_28
b .S1 f21_32
b .S1 f21_0
b .S1 f21_8388640
b .S1 f21_8388636
b .S1 f21_4194336+1
nop
f21_4194368:
.space 4194268
f21_8388636:
nop
f21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
g21_0:
nop
nop
nop
nop
nop
nop
nop
g21_28:
nop
g21_32:
.space 4194304
g21_4194336:
call .S1 g21_32
call .S1 g21_28
call .S1 g21_32
call .S1 g21_0
call .S1 g21_8388640
call .S1 g21_8388636
call .S1 g21_4194336+1
nop
g21_4194368:
.space 4194268
g21_8388636:
nop
g21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
h21_0:
nop
nop
nop
nop
nop
nop
nop
h21_28:
nop
h21_32:
.space 4194304
h21_4194336:
callp .S2 h21_32,b3
callp .S2 h21_28,b3
callp .S2 h21_32,b3
callp .S2 h21_0,b3
callp .S2 h21_8388640,b3
callp .S2 h21_8388636,b3
callp .S2 h21_4194336+1,b3
nop
h21_4194368:
.space 4194268
h21_8388636:
nop
h21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
i21_0:
nop
nop
nop
nop
nop
nop
nop
i21_28:
nop
i21_32:
.space 4194304
i21_4194336:
callret .S1 i21_32
callret .S1 i21_28
callret .S1 i21_32
callret .S1 i21_0
callret .S1 i21_8388640
callret .S1 i21_8388636
callret .S1 i21_4194336+1
nop
i21_4194368:
.space 4194268
i21_8388636:
nop
i21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
j21_0:
nop
nop
nop
nop
nop
nop
nop
j21_28:
nop
j21_32:
.space 4194304
j21_4194336:
ret .S1 j21_32
ret .S1 j21_28
ret .S1 j21_32
ret .S1 j21_0
ret .S1 j21_8388640
ret .S1 j21_8388636
ret .S1 j21_4194336+1
nop
j21_4194368:
.space 4194268
j21_8388636:
nop
j21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
k21_0:
nop
nop
nop
nop
nop
nop
nop
k21_28:
nop
k21_32:
.space 4194304
k21_4194336:
retp .S1 k21_32,a3
retp .S1 k21_28,a3
retp .S1 k21_32,a3
retp .S1 k21_0,a3
retp .S1 k21_8388640,a3
retp .S1 k21_8388636,a3
retp .S1 k21_4194336+1,a3
nop
k21_4194368:
.space 4194268
k21_8388636:
nop
k21_8388640:
nop
nop
nop
nop
nop
nop
nop
nop
|
stsp/binutils-ia16
| 1,317
|
gas/testsuite/gas/tic6x/insns16-s-unit-pcrel.s
|
; Test C64x+ S-unit pcrel compact instruction formats
.text
nop
.align 16
nop
.align 16
sbs7:
.short 0x000a
.short 0x004a
.short 0x214b
.short 0x428a
.short 0x63cb
.short 0x840a
.short 0xa54b
.short 0x868a
.short 0x77cb
.short 0x580a
.short 0x394b
.short 0x1a8a
.short 0x3bcb
.short 0x5c0a
.word 0xefe00000 | 0x8000
sbu8:
.short 0xcaca
.short 0xe7cb
.short 0xf84a
.short 0xcacb
.short 0xd84a
.short 0xf18b
.short 0xe84a
.short 0xd10b
.short 0xc74a
.short 0xeacb
.short 0xd18a
.short 0xea4b
.short 0xda4a
.short 0xd7cb
.word 0xefe00000 | 0x8000
scs10:
.short 0x0f1a
.short 0x1e5b
.short 0x2d9a
.short 0x3cdb
.short 0x4b9a
.short 0x5a5b
.short 0x691a
.short 0x785b
.short 0x879a
.short 0x96db
.short 0xa59a
.short 0xb45b
.short 0xc31a
.short 0xd2db
.word 0xefe00000 | 0x8000
sbs7c:
.short 0x002a
.short 0x216b
.short 0x427b
.short 0x637a
.short 0x846b
.short 0xa52a
.short 0x06bb
.short 0x07ba
.short 0x38ab
.short 0x592a
.short 0x7afb
.short 0x9bfa
.short 0xbceb
.short 0x0f2a
.word 0xefe00000 | 0x8000
sbu8c:
.short 0xc02a
.short 0xd16b
.short 0xd27b
.short 0xd37a
.short 0xc46b
.short 0xe52a
.short 0xe6bb
.short 0xe7ba
.short 0xc8ab
.short 0xf92a
.short 0xfafb
.short 0xfbfa
.short 0xcceb
.short 0xcf2a
.word 0xefe00000 | 0x8000
|
stsp/binutils-ia16
| 2,751
|
gas/testsuite/gas/tic6x/insns16-l-unit.s
|
; Test C64x+ L-unit compact instruction formats
.text
nop
.align 16
nop
.align 16
l3_nosat_l:
.short 0x0010
.short 0x2120
.short 0x4230
.short 0x6340
.short 0x8050
.short 0xa160
.short 0xc270
.short 0xeb80
.short 0x0890
.short 0x29a0
.short 0x4ab0
.short 0x6bc0
.short 0x88d0
.short 0xa9e0
.word 0xefe00000
l3_sat_h:
.short 0xc2f0
.short 0xe300
.short 0x0010
.short 0x2120
.short 0x4230
.short 0x6340
.short 0x8050
.short 0xa960
.short 0xca70
.short 0xeb80
.short 0x0890
.short 0x29a0
.short 0x4ab0
.short 0x6bc0
.word 0xefe84000
l3i:
.short 0x0410
.short 0x3520
.short 0x4630
.short 0x7740
.short 0x8550
.short 0xb660
.short 0xc770
.short 0x1c80
.short 0x2d90
.short 0x5ea0
.short 0x6fb0
.short 0x9cc0
.short 0xadd0
.short 0xdee0
.word 0xefe00000
l2c_op_000:
.short 0x0408
.short 0x2409
.short 0x4418
.short 0x6419
.short 0x9408
.short 0xb409
.short 0xd418
l2c_op_001:
.short 0xf439
.short 0x2428
.short 0x4429
.short 0x6438
.short 0x8439
.short 0xb428
.short 0xd429
.word 0xefe00000
l2c_op_010:
.short 0x0458
.short 0x2449
.short 0x4448
.short 0x6459
.short 0x9458
.short 0xb449
.short 0xd448
l2c_op_011:
.short 0xf479
.short 0x2468
.short 0x4469
.short 0x6478
.short 0x8479
.short 0xb468
.short 0xd469
.word 0xefe80000
l2c_op_100:
.short 0x0c18
.short 0x2c09
.short 0x4c08
.short 0x6c19
.short 0x9c18
.short 0xbc09
.short 0xdc08
l2c_op_101:
.short 0xfc39
.short 0x2c28
.short 0x4c29
.short 0x6c38
.short 0x8c39
.short 0xbc28
.short 0xdc29
.word 0xefe00000
l2c_op_110:
.short 0x0c58
.short 0x2c49
.short 0x4c48
.short 0x6c59
.short 0x9c58
.short 0xbc49
.short 0xdc48
l2c_op_111:
.short 0xfc79
.short 0x2c68
.short 0x4c69
.short 0x6c78
.short 0x8c79
.short 0xbc68
.short 0xdc69
.word 0xefe80000
lx5:
.short 0x0426
.short 0x2527
.short 0x46a6
.short 0x67a7
.short 0x8626
.short 0xa527
.short 0xc4a6
.short 0xf5a7
.short 0x1626
.short 0x3727
.short 0x56a6
.short 0x75a7
.short 0x9426
.short 0xb527
.word 0xefe00000
lx3c:
.short 0x0026
.short 0x2127
.short 0x42a6
.short 0x63a7
.short 0x8226
.short 0xa127
.short 0xc0a6
.short 0xe1a7
.short 0x0226
.short 0x2327
.short 0x42a6
.short 0x61a7
.short 0x8026
.short 0xa127
.word 0xefe00000
lx1c:
.short 0x1026
.short 0x3127
.short 0x52a6
.short 0x73a7
.short 0x9226
.short 0xb127
.short 0xd0a6
.short 0xf1a7
.short 0x1226
.short 0x3327
.short 0x52a6
.short 0x71a7
.short 0x9026
.short 0xb127
.word 0xefe00000
lx1:
.short 0x5b66
.short 0x5a67
.short 0x59e6
.short 0x58e7
.short 0x5866
.short 0x5967
.short 0x5ae6
.short 0x7be7
.short 0x7b66
.short 0x7a67
.short 0x79e6
.short 0x78e7
.short 0x7866
.short 0x7967
.word 0xefe00000
|
stsp/binutils-ia16
| 3,716
|
gas/testsuite/gas/tic6x/unwind-1.s
|
.cfi_sections .c6xabi.exidx
# standard layout
.p2align 8
f0:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# standard layout (pr0)
.p2align 8
f1:
.cfi_startproc
.cfi_def_cfa_offset 8
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -0
stw .d2t1 A10, *+B15(4)
.cfi_offset 10, -4
nop 4
.cfi_endproc
.personalityindex 0
.endp
# standard layout (pr1)
.p2align 8
f2:
.cfi_startproc
stw .d2t2 B15, *B15--(24)
.cfi_def_cfa_offset 24
.cfi_offset 31, 0
stw .d2t2 B10, *+B15(20)
.cfi_offset 26, -4
stw .d2t2 B3, *+B15(16)
.cfi_offset 19, -8
stdw .d2t1 A11:A10, *+B15(8)
.cfi_offset 11, -12
.cfi_offset 10, -16
nop 4
.cfi_endproc
.personalityindex 1
.endp
# standard layout (pr3)
.p2align 8
f3:
.cfi_startproc
stw .d2t2 B3, *B15--(16)
.cfi_def_cfa_offset 16
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.personalityindex 3
.endp
# compact layout
.p2align 8
f4:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# compact layout (pr0)
.p2align 8
f5:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 0
.endp
# compact layout (pr4)
.p2align 8
f6:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.personalityindex 4
.endp
# compact layout (aligned pair)
.p2align 8
f7:
.cfi_startproc
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, 0
.cfi_def_cfa_offset 8
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, -8
.cfi_def_cfa_offset 8
stdw .d2t1 A11:A10, *B15--(8)
.cfi_offset 11, -12
.cfi_offset 10, -16
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (aligned pair + 1)
.p2align 8
f8:
.cfi_startproc
stw .d2t2 B3, *B15--(8)
.cfi_offset 19, 0
.cfi_def_cfa_offset 8
stdw .d2t1 A13:A12, *B15--(8)
.cfi_offset 13, -4
.cfi_offset 12, -8
.cfi_def_cfa_offset 16
stw .d2t1 A10, *B15--(8)
.cfi_offset 10, -16
.cfi_def_cfa_offset 24
nop 4
.cfi_endproc
.endp
# compact layout (misaligned pair)
.p2align 8
f9:
.cfi_startproc
stw .d2t2 B11, *B15--(8)
.cfi_offset 27, 0
.cfi_def_cfa_offset 8
stw .d2t2 B10, *B15--(8)
.cfi_offset 26, -8
.cfi_def_cfa_offset 16
nop 4
.cfi_endproc
.endp
# standard frame pointer
.p2align 8
fa:
.cfi_startproc
stw .d2t1 A15, *B15--(16)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *+B15(12)
.cfi_offset 11, -4
nop 4
.cfi_endproc
.endp
# compact frame pointer
.p2align 8
fb:
.cfi_startproc
stw .d2t1 A15, *B15--(8)
.cfi_def_cfa_offset 8
.cfi_offset 15, 0
mv .s1x B15, A15
addk .s1 16, A15
.cfi_def_cfa 15, 0
stw .d2t1 A11, *B15--(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fc:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fd:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(8)
.cfi_offset 11, -8
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
fe:
.cfi_startproc
sub .s2 B15, 16, B15
stw .d2t2 B3, *+B15(12)
.cfi_def_cfa_offset 16
.cfi_offset 19, -4
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -12
nop 4
.cfi_endproc
.endp
# custom layout
.p2align 8
ff:
.cfi_startproc
addk .s2 -24, B15
stw .d2t2 B3, *+B15(24)
.cfi_def_cfa_offset 24
.cfi_offset 19, 0
stw .d2t1 A11, *+B15(4)
.cfi_offset 11, -20
nop 4
.cfi_endproc
.endp
|
stsp/binutils-ia16
| 28,021
|
gas/testsuite/gas/tic6x/insns-bad-1.s
|
# Test bad instructions and operands.
.text
.globl f
f:
nonesuch foo bar
nop nonconst
nop 2,
nop 2,3
nop 2 , 4
nop 2 4
nop 0
nop -1
nop 10000
nop 10
nop 15
abs .L1 a1,
abs .L1 a1
abs .S1 a1,a2
abs .L1 foo,bar
abs .L1X foo,bar
abs .L1 A0,A00
abs .L1 A32,A1
abs .L1 B1,A1
abs .L1 A1,B1
abs .L1X A1,A1
abs .L1X B1,B1
abs .L2 A3,B4
abs .L2 B4,A3
abs .L2X A7,A8
abs .L2X b9,b10
abs .L1 A2:A1,A3:A2
abs .L2 B5:B4,B2:B3
abs .L1 A3:B2,A5:A4
abs .L2 B1:B0,A5:A4
abs .L1X B1:B0,A1:A0
abs .L1 A1:A0,A11
abs2 .L1 a1
abs2 .S1 a1,a2
abs2 .L1 foo,a3:a2
abs2 .L2X b1,b2
absdp .L1 a3:a2,a1:a0
absdp .S2 b1:b0
absdp .S2 b1,b0
absdp .S2X a1:a0,b1:b0
abssp .L1 a0,a0
abssp .S1 a1:a0
abssp .S1X a0,a1
abssp .S2 a1,b0
add .M1 a0,a0,a0
add .L1 a0,b0,a0
add .L1X a0,a0,a0
add .L1 a1:a0,a3:a2,a5:a4
add .L1X 16,b2,a3
add .L1X -17,b2,a3
add .L1X 5,a3:a2,a7:a6
add .L2 100,b5:b4,b9:b8
add .L1 a0,a0
add .S1 a0,a0,a1:a0
add .S2 b1,b2
add .S1X 4,a5,a7
add .S2X -17,a9,b11
add .S1 16,a14,a13
add .D1T1 a1,a1,a1
add .D1 a1,a1
add .D2 b1,-17,b2
add .D2 b1,32,b4
add .D1X b1,b1,a1
add .D2X a5,-17,b1
add .D2X a20,16,b4
addab .L1 a4,a5,a6
addab .D1X a7,a8,a9
addab .D1 a2,a3
addab .D2 a1,b2,b3
addab .D1 a1,-1,a2
addab .D2 b1,32,b2
addab .D1X b14,-1,a2
addab .D2 b15,32768,b20
addab .D1 a14,32,a20
addad .D1X a4,a5,a6
addad .S1 a10,a9,a8
addad .D1 a1,a2,a3,a4
addad .D2 b4,-1,b4
addad .D2 b4,32,b3
addad .D1 a1,b2,a3
addad .D2 b14,foo,b4
addah .L1 a4,a5,a6
addah .D1X a7,a8,a9
addah .D1 a2,a3
addah .D2 a1,b2,b3
addah .D1 a1,-1,a2
addah .D2 b1,32,b2
addah .D1X b14,-1,a2
addah .D2 b15,32768,b20
addah .D1 a14,32,a20
addaw .L1 a4,a5,a6
addaw .D1X a7,a8,a9
addaw .D1 a2,a3
addaw .D2 a1,b2,b3
addaw .D1 a1,-1,a2
addaw .D2 b1,32,b2
addaw .D1X b14,-1,a2
addaw .D2 b15,32768,b20
addaw .D1 a14,32,a20
adddp .D1 a1:a0,a1:a0,a1:a0
adddp .L1 a1:a0,a1:a0
adddp .L2 b1,b1,b1
adddp .L1 a1:a0,b1:b0,a1:a0
adddp .L2X b1:b0,b3:b2,b5:b4
addk .L1 0,a1
addk .S2 32768,b1
addk .S1 -32769,a1
addk .S2 0
addk .S2X 0,a1
mvk .M1 0,a1
mvk .S2 32768,b1
mvk .S1 -32769,a1
mvk .S2 0,b1,0
mvk .S1X 0,b1
mvkh .L1 0,a1
mvkh .S2 0,b1,0
mvkh .S1X 0,b1
mvklh .L1 0,a1
mvklh .S2 0,b1,0
mvklh .S1X 0,b1
mvkl .L1 0,a1
mvkl .S2 0,b1,0
mvkl .S1X 0,b1
addkpc .S1 f,a1,0
addkpc .S2X f,a1,0
addkpc .S2 0,b2,0
addkpc .S2 f,b2
addkpc .S2 f,b2,-1
addkpc .S2 f,b2,8
b .L1 f
b .S1X f
b .S1 f,0
b .S1 0
call .L1 f
call .S1X f
call .S1 f,0
call .S1 0
bdec .L1 f,a1
bdec .S1X f,b1
bdec .S1 f,b1
bdec .S2 0,b2
bdec .S2 f,b1,0
bpos .L1 f,a1
bpos .S1X f,b1
bpos .S1 f,b1
bpos .S2 0,b2
bpos .S2 f,b1,0
bnop .L1 f,0
bnop .S1X f,0
bnop f,-1
bnop 0,0
bnop f,8
callnop .L1 f,0
callnop .S1X f,0
callnop f,-1
callnop 0,0
callnop f,8
callp .L1 f,a3
callp .S1X f,b3
callp .S1 f,a4
callp .S1 0,a3
callp .S1 f,b3
callp .S2 f,a3
addsp .D1 a1,a2,a3
addsp .L1 a1
addsp .L2 a2,0
addsp .L1 b1,a1,a3
addsp .S2X b1,b2,b3
addsub .M1 a2,a3,a5:a4
addsub .L1 a1
addsub .L1 a1,a2,a3
addsub .L2 a1,b1,b3:b2
addsub2 .M1 a2,a3,a5:a4
addsub2 .L1 a1
addsub2 .L1 a1,a2,a3
addsub2 .L2 a1,b1,b3:b2
addu .D2 b4,b5,b7:b6
addu .L2 b1,b2
addu .L1 b1,a1,a3:a2
addu .L2X a4,b7:b6,b5
add2 .M1 a1,a2,a3
add2 .S1 a1,a2,a3,a4
add2 .L1 b1,a1,a2
add2 .D2X b1,b2,b3
add4 .S1 a1,a2,a3
add4 .L1 a1,a2,a3,a4
add4 .L1 b1,a1,a2
add4 .L2X b1,b2,b3
and .M2 b1,b2,b3
and .L1 -17,a4,a5
and .L2 16,b3,b4
and .S1X -17,b4,a5
and .S2X 16,a3,b4
and .D1 -17,a4,a5
and .D2 16,b3,b4
and .D1 b1,a2,a3
andn .M1 a1,a2,a3
andn .S1 a1
andn .D1X b2,b2,a3
andn .S2 0,b2,b3
avg2 .S1 a1,a2,a3
avg2 .M1 a1,a2
avg2 .M1 b1,a2,a2
avg2 .M2X a1,a2,b3
avgu4 .S1 a1,a2,a3
avgu4 .M1 a1,a2
avgu4 .M1 b1,a2,a2
avgu4 .M2X a1,a2,b3
b .L2 b1
b .S2 b1,0
call .M2 b1
call .S2 b1,0
callret .D2 b1
callret .S2 b1,0
ret .L2 b1
ret .S2 b1,0
b .S2X irp
b .L2 irp
b .S2X nrp
b .M2 nrp
bitc4 .M1 a1,a2,a3
bitc4 .L1 a1,a2
bitc4 .M2 b2,a1
bitc4 .M2X b3,b4
bitr .M1 a1
bitr .S1 a1,a2
bitr .M2 b2,a1
bitr .M2X b3,b4
bnop .M1 a5,0
bnop .S1X b5,0
bnop .S2 b3,-1
bnop .S2 b3,8
bnop .S2 b3
callnop .M1 a5,0
callnop .S1X b5,0
callnop .S2 b3,-1
callnop .S2 b3,8
callnop .S2 b3
clr .L1 a1,0,1,a2
clr .M2 b1,b2,b3
clr .S1 a1,a1
clr .S1X a1,0,0,a1
clr .S2 b1,a1,b1
cmpeq .S1 a1,a2,a3
cmpeq .L1 a1,a2,a3,a4
cmpeq .L1 a1:a0,a3:a2,a5
cmpeq .L2 -17,b4,b5
cmpeq .L2 16,b4,b5
cmpeq .L1 -17,a5:a4,a3
cmpeq .L1 16,a5:a4,a3
cmpeq .L1X -16,a5:a4,a3
cmpeq2 .L1 a1,a2,a3
cmpeq2 .S1 a1,a2
cmpeq2 .S1 a1,b2,a3
cmpeq2 .S2X b1,b2,b3
cmpeq4 .D1 a1,a2,a3
cmpeq4 .S1 a1
cmpeq4 .S2 a1,b2,b3
cmpeq4 .S1X a4,a5,a6
cmpeqdp .M1 a3:a2,a1:a0,a5
cmpeqdp .S1 a3:a2
cmpeqdp .S1 a3,a2,a1
cmpeqdp .S2 a3:a2,b1:b0,b5
cmpeqdp .S2X b3:b2,b1:b0,b31
cmpeqsp .S1 a1
cmpeqsp .M2 b1,b2,b3
cmpeqsp .S2X b1,b2,b3
cmpeqsp .S1 b1,a2,a3
cmpgt .S1 a1,a2,a3
cmpgt .L1 a1,a2,a3,a4
cmpgt .L1 a1:a0,a3:a2,a5
cmpgt .L2 -17,b4,b5
cmpgt .L2 16,b4,b5
cmpgt .L1 -17,a5:a4,a3
cmpgt .L1 16,a5:a4,a3
cmpgt .L1X -16,a5:a4,a3
cmpgt2 .L1 a1,a2,a3
cmpgt2 .S1 a1,a2
cmpgt2 .S1 b1,a2,a3
cmpgt2 .S2X b1,b3,b3
cmpgtdp .L1 a1:a0,a1:a0,a0
cmpgtdp .S1 a1:a0
cmpgtdp .S1 b1:b0,a1:a0,a2
cmpgtdp .S2X b5:b4,b3:b2,b1
cmpgtsp .L1 a1,a1,a0
cmpgtsp .S1 a1
cmpgtsp .S1 b1,a1,a2
cmpgtsp .S2X b5,b3,b1
cmpgtu .S1 a1,a2,a3
cmpgtu .L1 a1,a2,a3,a4
cmpgtu .L1 a1:a0,a3:a2,a5
cmpgtu .L2 -1,b4,b5
cmpgtu .L2 32,b4,b5
cmpgtu .L1 -1,a5:a4,a3
cmpgtu .L1 32,a5:a4,a3
cmpgtu .L1X 0,a5:a4,a3
cmpgtu4 .D1 a1,a2,a3
cmpgtu4 .S1 a1,a2
cmpgtu4 .S1 a1,a2,b3
cmpgtu4 .S2X b1,b2,b3
cmplt .S1 a1,a2,a3
cmplt .L1 a1,a2,a3,a4
cmplt .L1 a1:a0,a3:a2,a5
cmplt .L2 -17,b4,b5
cmplt .L2 16,b4,b5
cmplt .L1 -17,a5:a4,a3
cmplt .L1 16,a5:a4,a3
cmplt .L1X -16,a5:a4,a3
cmplt2 .L1 a1,a2,a3
cmplt2 .S1 a1,a2
cmplt2 .S1 a2,b1,a3
cmplt2 .S2X b1,b3,b3
cmpltdp .L1 a1:a0,a1:a0,a0
cmpltdp .S1 a1:a0
cmpltdp .S1 b1:b0,a1:a0,a2
cmpltdp .S2X b5:b4,b3:b2,b1
cmpltsp .L1 a1,a1,a0
cmpltsp .S1 a1
cmpltsp .S1 b1,a1,a2
cmpltsp .S2X b5,b3,b1
cmpltu .S1 a1,a2,a3
cmpltu .L1 a1,a2,a3,a4
cmpltu .L1 a1:a0,a3:a2,a5
cmpltu .L2 -1,b4,b5
cmpltu .L2 32,b4,b5
cmpltu .L1 -1,a5:a4,a3
cmpltu .L1 32,a5:a4,a3
cmpltu .L1X 0,a5:a4,a3
cmpltu4 .D1 a1,a2,a3
cmpltu4 .S1 a1,a2
cmpltu4 .S1 a1,a2,b3
cmpltu4 .S2X b1,b2,b3
cmpy .S1 a1,a2,a5:a4
cmpy .M1 a1,a2
cmpy .M1 b1,a1,a3:a2
cmpy .M2X b3,b4,b7:b6
cmpyr .S1 a1,a2,a5
cmpyr .M1 a1,a2
cmpyr .M1 b1,a1,a3
cmpyr .M2X b3,b4,b7
cmpyr1 .L1 a1,a2,a5
cmpyr1 .M1 a1,a2
cmpyr1 .M1 b1,a1,a3
cmpyr1 .M2X b3,b4,b7
ddotp4 .D1 a1,a3,a5:a4
ddotp4 .M1 a1,a3
ddotp4 .M1X a1,a2,a5:a4
ddotp4 .M2 a1,b1,b3:b2
ddotph2 .L1 a1:a0,a3,a5:a4
ddotph2 .M1 a1:a0,a3
ddotph2 .M1X a1:a0,a2,a5:a4
ddotph2 .M2 a1:a0,b1,b3:b2
ddotph2r .S1 a1:a0,a3,a5
ddotph2r .M1 a1:a0,a3
ddotph2r .M1X a1:a0,a2,a5
ddotph2r .M2 a1:a0,b1,b3
ddotpl2 .L1 a1:a0,a3,a5:a4
ddotpl2 .M1 a1:a0,a3
ddotpl2 .M1X a1:a0,a2,a5:a4
ddotpl2 .M2 a1:a0,b1,b3:b2
ddotpl2r .L1 a1:a0,a3,a5
ddotpl2r .M1 a1:a0,a3
ddotpl2r .M1X a1:a0,a2,a5
ddotpl2r .M2 a1:a0,b1,b3
deal .D1 a1,a2
deal .M1 a1,a2,a3
deal .M2 b1,a1
deal .M2X b1,b2
dint .S1
dint a1
dmv .M1 a1,a2,a5:a4
dmv .S1 a1,a2
dmv .S2 a1,b2,b5:b4
dmv .S2X b1,b2,b5:b4
dotp2 .L1 a1,a2,a3
dotp2 .M1 a1,a2
dotp2 .M1 b1,a2,a3
dotp2 .M1X a1,a2,a3
dotp2 .M2 a1,b2,b5:b4
dotp2 .M2X b3,b4,b7:b6
dotpn2 .L1 a1,a2,a3
dotpn2 .M1 a1,a2
dotpn2 .M1 b1,a2,a3
dotpn2 .M1X a1,a2,a3
dotpnrsu2 .L1 a1,a2,a3
dotpnrsu2 .M1 a1,a2
dotpnrsu2 .M1 b1,a2,a3
dotpnrsu2 .M1X a1,a2,a3
dotpnrus2 .L1 a1,a2,a3
dotpnrus2 .M1 a1,a2
dotpnrus2 .M1 a2,b1,a3
dotpnrus2 .M1X a1,a2,a3
dotprsu2 .L1 a1,a2,a3
dotprsu2 .M1 a1,a2
dotprsu2 .M1 b1,a2,a3
dotprsu2 .M1X a1,a2,a3
dotprus2 .L1 a1,a2,a3
dotprus2 .M1 a1,a2
dotprus2 .M1 a2,b1,a3
dotprus2 .M1X a1,a2,a3
dotpsu4 .L1 a1,a2,a3
dotpsu4 .M1 a1,a2
dotpsu4 .M1 b1,a2,a3
dotpsu4 .M1X a1,a2,a3
dotpus4 .L1 a1,a2,a3
dotpus4 .M1 a1,a2
dotpus4 .M1 a2,b1,a3
dotpus4 .M1X a1,a2,a3
dotpu4 .L1 a1,a2,a3
dotpu4 .M1 a1,a2
dotpu4 .M1 b1,a2,a3
dotpu4 .M1X a1,a2,a3
dpack2 .M1 a0,a1,a3:a2
dpack2 .L1 a0,a1
dpack2 .L1 a1,a2,b3:b2
dpack2 .L2X b3,b4,b7:b6
dpackx2 .M1 a0,a1,a3:a2
dpackx2 .L1 a0,a1
dpackx2 .L1 a1,a2,b3:b2
dpackx2 .L2X b3,b4,b7:b6
dpint .S1 a5:a4,a3
dpint .L1X b5:b4,a3
dpint .L2 a5:a4,b3
dpsp .S1 a5:a4,a3
dpsp .L1X b5:b4,a3
dpsp .L2 a5:a4,b3
dptrunc .S1 a5:a4,a3
dptrunc .L1X b5:b4,a3
dptrunc .L2 a5:a4,b3
ext .L1 a1,0,1,a2
ext .M2 b1,b2,b3
ext .S1 a1,a1
ext .S1X a1,0,0,a1
ext .S2 b1,a1,b1
clr .S1 a0,-1,0,a1
clr .S1 a0,32,0,a1
clr .S1 a0,0,-1,a1
clr .S1 a0,0,32,a1
ext .S1 a0,-1,0,a1
ext .S1 a0,32,0,a1
ext .S1 a0,0,-1,a1
ext .S1 a0,0,32,a1
extu .L1 a1,0,1,a2
extu .M2 b1,b2,b3
extu .S1 a1,a1
extu .S1X a1,0,0,a1
extu .S2 b1,a1,b1
extu .S1 a0,-1,0,a1
extu .S1 a0,32,0,a1
extu .S1 a0,0,-1,a1
extu .S1 a0,0,32,a1
gmpy .L1 a1,a2,a3
gmpy .M1 a1,a2
gmpy .M1X a1,a2,a3
gmpy .M2 a1,b2,b3
gmpy4 .S1 a1,a2,a3
gmpy4 .M1 a1,a2,a3,a4
gmpy4 .M1 b1,a1,a2
gmpy4 .M2X b1,b2,b3
idle .S1
idle a0
intdp .S1 a5,a3:a2
intdp .L1 a5
intdp .L2 b0,a1:a0
intdp .L1X b5,b3:b2
intdpu .D1 a5,a3:a2
intdpu .L1 a5
intdpu .L2 b0,a1:a0
intdpu .L1X b5,b3:b2
intsp .S1 a5,a3
intsp .L1 a5
intsp .L2 b0,a1
intsp .L1X b5,b3
intspu .D1 a5,a3
intspu .L1 a5
intspu .L2 b0,a1
intspu .L1X b5,b3
cmtl .D2T1 *b0,a0
cmtl .D1T1 *a0,a1
cmtl .L1 *a0,a1
cmtl .D2T2 *+b0(0),b1
cmtl .D2T2 *-b0[0],b1
cmtl .D2T2 *++b0,b1
cmtl .D2T2 *--b0,b1
cmtl .D2T2 *b0++,b1
cmtl .D2T2 *b0--,b1
cmtl .D2T2 *+b0[b1],b2
cmtl .D2T2 *a0,b1
cmtl .D2T2 *b0,a1
ll .D2T1 *b0,a0
ll .D1T1 *a0,a1
ll .S1 *a0,a1
ll .D2T2 *+b0(0),b1
ll .D2T2 *-b0[0],b1
ll .D2T2 *++b0,b1
ll .D2T2 *--b0,b1
ll .D2T2 *b0++,b1
ll .D2T2 *b0--,b1
ll .D2T2 *+b0[b1],b2
ll .D2T2 *a0,b1
ll .D2T2 *b0,a1
sl .D2T1 a0,*b0
sl .D1T1 a1,*a0
sl .L1 a1,*a0
sl .D2T2 b1,*+b0(0)
sl .D2T2 b1,*-b0[0]
sl .D2T2 b1,*++b0
sl .D2T2 b1,*--b0
sl .D2T2 b1,*b0++
sl .D2T2 b1,*b0--
sl .D2T2 b2,*+b0[b1]
sl .D2T2 b1,*a0
sl .D2T2 a1,*b0
ldb .L1 *a1,a0
ldb .D1T1 *a1,b1
ldb .D1T1 *b1,a1
ldb .D2T2 *a1,b1
ldb .D2T2 *b1,a1
ldb .D1T1 *a1
ldb .D1T1 *+a1[b1],a2
ldb .D1T1 *+a1,a2
ldb .D1T1 *-a1,a2
ldb .D1T1 *a1++[32],a2
ldb .D1T1 *a1++(32),a2
ldb .D1T1 *--a1[-1],a2
ldb .D1T1 *--a1(-1),a2
ldb .D1T1 *+a1(a2),a3
ldb .D2T2 *+b14[foo],b16
ldbu .S1 *a1,a0
ldbu .D1T1 *a1,b1
ldbu .D1T1 *b1,a1
ldbu .D2T2 *a1,b1
ldbu .D2T2 *b1,a1
ldbu .D1T1 *a1
ldbu .D1T1 *+a1[b1],a2
ldbu .D1T1 *+a1,a2
ldbu .D1T1 *-a1,a2
ldbu .D1T1 *a1++[32],a2
ldbu .D1T1 *a1++(32),a2
ldbu .D1T1 *--a1[-1],a2
ldbu .D1T1 *--a1(-1),a2
ldbu .D1T1 *+a1(a2),a3
ldbu .D2T2 *+b14[foo],b16
lddw .L1 *a1,a1:a0
lddw .D1T1 *a1,b1:b0
lddw .D1T1 *b1,a1:a0
lddw .D2T2 *a1,b1:b0
lddw .D2T2 *b1,a1:a0
lddw .D1T1 *a1
lddw .D1T1 *+a1[b1],a3:a2
lddw .D1T1 *+a1,a3:a2
lddw .D1T1 *-a1,a3:a2
lddw .D1T1 *a1++[32],a3:a2
lddw .D1T1 *a1++(256),a3:a2
lddw .D1T1 *--a1[-1],a3:a2
lddw .D1T1 *--a1(-8),a3:a2
lddw .D1T1 *+a1(a2),a3:a2
lddw .D2T2 *+b14[foo],b17:b16
lddw .D1T1 *+a1(1),a3:a2
lddw .D2T2 *+b14(b15),b17:b16
ldh .M1 *a1,a0
ldh .D1T1 *a1,b1
ldh .D1T1 *b1,a1
ldh .D2T2 *a1,b1
ldh .D2T2 *b1,a1
ldh .D1T1 *a1
ldh .D1T1 *+a1[b1],a2
ldh .D1T1 *+a1,a2
ldh .D1T1 *-a1,a2
ldh .D1T1 *a1++[32],a2
ldh .D1T1 *a1++(64),a2
ldh .D1T1 *--a1[-1],a2
ldh .D1T1 *--a1(-2),a2
ldh .D1T1 *+a1(a2),a3
ldh .D2T2 *+b14[foo],b16
ldh .D2T2 *+b1(1),b2
ldhu .S1 *a1,a0
ldhu .D1T1 *a1,b1
ldhu .D1T1 *b1,a1
ldhu .D2T2 *a1,b1
ldhu .D2T2 *b1,a1
ldhu .D1T1 *a1
ldhu .D1T1 *+a1[b1],a2
ldhu .D1T1 *+a1,a2
ldhu .D1T1 *-a1,a2
ldhu .D1T1 *a1++[32],a2
ldhu .D1T1 *a1++(64),a2
ldhu .D1T1 *--a1[-1],a2
ldhu .D1T1 *--a1(-2),a2
ldhu .D1T1 *+a1(a2),a3
ldhu .D2T2 *+b14[foo],b16
ldhu .D2T2 *+b1(1),b2
ldndw .L1 *a1,a1:a0
ldndw .D1T1 *a1,b1:b0
ldndw .D1T1 *b1,a1:a0
ldndw .D2T2 *a1,b1:b0
ldndw .D2T2 *b1,a1:a0
ldndw .D1T1 *a1
ldndw .D1T1 *+a1[b1],a3:a2
ldndw .D1T1 *+a1,a3:a2
ldndw .D1T1 *-a1,a3:a2
ldndw .D1T1 *a1++[32],a3:a2
ldndw .D1T1 *a1++(32),a3:a2
ldndw .D1T1 *--a1[-1],a3:a2
ldndw .D1T1 *--a1(-1),a3:a2
ldndw .D2T2 *+b14[foo],b17:b16
ldnw .S1 *a1,a0
ldnw .D1T1 *a1,b1
ldnw .D1T1 *b1,a1
ldnw .D2T2 *a1,b1
ldnw .D2T2 *b1,a1
ldnw .D1T1 *a1
ldnw .D1T1 *+a1[b1],a2
ldnw .D1T1 *+a1,a2
ldnw .D1T1 *-a1,a2
ldnw .D1T1 *a1++[32],a2
ldnw .D1T1 *a1++(128),a2
ldnw .D1T1 *--a1[-1],a2
ldnw .D1T1 *--a1(-4),a2
ldnw .D1T1 *+a1(a2),a3
ldnw .D2T2 *+b14[foo],b16
ldnw .D2T2 *+b1(2),b2
ldw .S1 *a1,a0
ldw .D1T1 *a1,b1
ldw .D1T1 *b1,a1
ldw .D2T2 *a1,b1
ldw .D2T2 *b1,a1
ldw .D1T1 *a1
ldw .D1T1 *+a1[b1],a2
ldw .D1T1 *+a1,a2
ldw .D1T1 *-a1,a2
ldw .D1T1 *a1++[32],a2
ldw .D1T1 *a1++(128),a2
ldw .D1T1 *--a1[-1],a2
ldw .D1T1 *--a1(-4),a2
ldw .D1T1 *+a1(a2),a3
ldw .D2T2 *+b14[foo],b16
ldw .D2T2 *+b1(2),b2
ldb .D2T2 *+b14[-1],b1
ldb .D2T2 *+b14[32768],b1
ldbu .D2T2 *+b14[-1],b1
ldbu .D2T2 *+b14[32768],b1
ldh .D2T2 *+b14[-1],b1
ldh .D2T2 *+b14[32768],b1
ldhu .D2T2 *+b14[-1],b1
ldhu .D2T2 *+b14[32768],b1
ldw .D2T2 *+b14[-1],b1
ldw .D2T2 *+b14[32768],b1
lmbd .S1 a1,a2,a3
lmbd .L1 a1,a2
lmbd .L1 b1,a2,a3
lmbd .L2X b1,b2,b3
lmbd .L1 -17,a1,a2
lmbd .L1 16,a1,a2
max2 .M1 a1,a2,a3
max2 .L1 a1,a2
max2 .L1 b1,a2,a3
max2 .L2X b1,b2,b3
max2 .S2X b1,b2,b3
max2 .S2 a1,b2,b3
maxu4 .S1 a1,a2,a3
maxu4 .L1 a1,a2
maxu4 .L1 b1,a2,a3
maxu4 .L2X b1,b2,b3
min2 .M1 a1,a2,a3
min2 .L1 a1,a2
min2 .L1 b1,a2,a3
min2 .L2X b1,b2,b3
min2 .S2X b1,b2,b3
min2 .S2 a1,b2,b3
minu4 .S1 a1,a2,a3
minu4 .L1 a1,a2
minu4 .L1 b1,a2,a3
minu4 .L2X b1,b2,b3
mpy .L1 a1,a2,a3
mpy .M1 a1,a2
mpy .M1 b1,a2,a3
mpy .M2X b1,b2,b3
mpy .M2 -17,b1,b2
mpy .M1 16,a1,a2
mpy .M2X 0,b2,b3
mpydp .D1 a1:a0,a1:a0,a1:a0
mpydp .M1 a1:a0,a1:a0
mpydp .M1 b1:b0,a1:a0,a3:a2
mpyh .S1 a1,a2,a3
mpyh .M1 a1,a2
mpyh .M1 b1,a2,a3
mpyh .M2X b1,b2,b3
mpyhi .D1 a1,a2,a5:a4
mpyhi .M1 a1,a2
mpyhi .M1 b1,a2,a5:a4
mpyhi .M2X b1,b2,b5:b4
mpyhir .D1 a1,a2,a3
mpyhir .M1 a1,a2
mpyhir .M1 b1,a2,a3
mpyhir .M2X b1,b2,b3
mpyhl .L1 a1,a2,a3
mpyhl .M1 a1,a2
mpyhl .M1 b1,a2,a3
mpyhl .M2X b1,b2,b3
mpyhlu .S1 a1,a2,a3
mpyhlu .M1 a1,a2
mpyhlu .M1 b1,a2,a3
mpyhlu .M2X b1,b2,b3
mpyhslu .S1 a1,a2,a3
mpyhslu .M1 a1,a2
mpyhslu .M1 b1,a2,a3
mpyhslu .M2X b1,b2,b3
mpyhsu .S1 a1,a2,a3
mpyhsu .M1 a1,a2
mpyhsu .M1 b1,a2,a3
mpyhsu .M2X b1,b2,b3
mpyhu .D1 a1,a2,a3
mpyhu .M1 a1,a2
mpyhu .M1 b1,a2,a3
mpyhu .M2X b1,b2,b3
mpyhuls .S1 a1,a2,a3
mpyhuls .M1 a1,a2
mpyhuls .M1 b1,a2,a3
mpyhuls .M2X b1,b2,b3
mpyhus .S1 a1,a2,a3
mpyhus .M1 a1,a2
mpyhus .M1 b1,a2,a3
mpyhus .M2X b1,b2,b3
mpyi .L1 a1,a2,a3
mpyi .M1 a1,a2
mpyi .M1 b1,a2,a3
mpyi .M2X b1,b2,b3
mpyi .M1 -17,a2,a3
mpyi .M2 16,b2,b3
mpyid .D1 a1,a2,a3:a2
mpyid .M1 a1,a2
mpyid .M1 b1,a2,a3:a2
mpyid .M2X b1,b2,b3:b2
mpyid .M1 -17,a2,a3:a2
mpyid .M2 16,b2,b3:b2
mpyih .D1 a1,a2,a5:a4
mpyih .M1 a1,a2
mpyih .M1 b1,a2,a5:a4
mpyih .M2X b1,b2,b5:b4
mpyihr .D1 a1,a2,a3
mpyihr .M1 a1,a2
mpyihr .M1 b1,a2,a3
mpyihr .M2X b1,b2,b3
mpyil .S1 a1,a2,a5:a4
mpyil .M1 a1,a2
mpyil .M1 b1,a2,a5:a4
mpyil .M2X b1,b2,b5:b4
mpyilr .L1 a1,a2,a3
mpyilr .M1 a1,a2
mpyilr .M1 b1,a2,a3
mpyilr .M2X b1,b2,b3
mpylh .S1 a1,a2,a3
mpylh .M1 a1,a2
mpylh .M1 b1,a2,a3
mpylh .M2X b1,b2,b3
mpylhu .D1 a1,a2,a3
mpylhu .M1 a1,a2
mpylhu .M1 b1,a2,a3
mpylhu .M2X b1,b2,b3
mpyli .S1 a1,a2,a3:a2
mpyli .M1 a1,a2
mpyli .M1 b1,a2,a3:a2
mpyli .M2X b1,b2,b3:b2
mpylir .D1 a1,a2,a3
mpylir .M1 a1,a2
mpylir .M1 b1,a2,a3
mpylir .M2X b1,b2,b3
mpylshu .L1 a1,a2,a3
mpylshu .M1 a1,a2
mpylshu .M1 b1,a2,a3
mpylshu .M2X b1,b2,b3
mpyluhs .S1 a1,a2,a3
mpyluhs .M1 a1,a2
mpyluhs .M1 b1,a2,a3
mpyluhs .M2X b1,b2,b3
mpysp .D1 a1,a2,a3
mpysp .M1 a1,a2
mpysp .M1 b1,a2,a3
mpysp .M2X b1,b2,b3
mpyspdp .L1 a1,a1:a0,a1:a0
mpyspdp .M1 a1,a1:a0,a1:a0,a1:a0
mpyspdp .M1 b1,a1:a0,a1:a0
mpyspdp .M2X b1,b1:b0,b1:b0
mpysp2dp .S1 a1,a2,a3:a2
mpysp2dp .M1 a1,a2
mpysp2dp .M1 b1,a2,a3:a2
mpysp2dp .M2X b1,b2,b3:b2
mpysu .D1 a1,a2,a3
mpysu .M1 a1,a2
mpysu .M1 b1,a2,a3
mpysu .M2X b1,b2,b3
mpysu .M1 -17,a2,a3
mpysu .M2 16,b2,b3
mpysu4 .S1 a1,a2,a3:a2
mpysu4 .M1 a1,a2
mpysu4 .M1 b1,a2,a3:a2
mpysu4 .M2X b1,b2,b3:b2
mpyu .L1 a1,a2,a3
mpyu .M1 a1,a2
mpyu .M1 b1,a2,a3
mpyu .M2X b1,b2,b3
mpyu4 .D1 a1,a2,a3:a2
mpyu4 .M1 a1,a2
mpyu4 .M1 b1,a2,a3:a2
mpyu4 .M2X b1,b2,b3:b2
mpyus .S1 a1,a2,a3
mpyus .M1 a1,a2
mpyus .M1 b1,a2,a3
mpyus .M2X b1,b2,b3
mpyus4 .L1 a1,a2,a3:a2
mpyus4 .M1 a1,a2
mpyus4 .M1 b1,a2,a3:a2
mpyus4 .M2X b1,b2,b3:b2
mpy2 .D1 a1,a2,a3:a2
mpy2 .M1 a1,a2
mpy2 .M1 b1,a2,a3:a2
mpy2 .M2X b1,b2,b3:b2
mpy2ir .L1 a1,a2,a3:a2
mpy2ir .M1 a1,a2
mpy2ir .M1 b1,a2,a3:a2
mpy2ir .M2X b1,b2,b3:b2
mpy32 .L1 a1,a2,a3
mpy32 .M1 a1,a2
mpy32 .M1 b1,a2,a3
mpy32 .M2X b1,b2,b3
mpy32 .M1 b1,a2,a3:a2
mpy32 .M1X a1,a2,a5:a4
mpy32su .L1 a1,a2,a3:a2
mpy32su .M1 a1,a2
mpy32su .M2X b1,b2,b3:b2
mpy32su .M1 b1,a2,a3:a2
mpy32u .L1 a1,a2,a3:a2
mpy32u .M1 a1,a2
mpy32u .M2X b1,b2,b3:b2
mpy32u .M1 b1,a2,a3:a2
mpy32us .L1 a1,a2,a3:a2
mpy32us .M1 a1,a2
mpy32us .M2X b1,b2,b3:b2
mpy32us .M1 b1,a2,a3:a2
mvc .L2 b2,amr
mvc .S2X amr,a1
mvc .S2 b2,nonesuch
mvc .S2 b0,dnum
mvc .S2 ecr,b0
mvc .S2 b0,efr
mvc .S2 icr,b0
mvc .S2 b0,ifr
mvc .S2 isr,b0
mvc .S2 b0,pce1
mvc .S2 b0,tsch
mv .M1 a1,a2
mv .L1 a1,a2,a3
mv .L1 a1,b2
mv .L2X b1,b2
mv .S1 a1,b2
mv .S2X b1,b2
mv .D1 a1,b2
mv .D2X b1,b2
mvd .L1 a1,a2
mvd .M1 a3,a4,a5
mvd .M1 a1,b2
mvd .M2X b3,b4
mvk .L1 -17,a0
mvk .L1 16,a0
mvk .L1X 0,a0
mvk .D2 -17,b0
mvk .D2 16,b0
mvk .D2X 0,b0
norm .S1 a1,a0
norm .L1 a1:a0,a0,a0
norm .L1X b1:b0,a1
norm .L2 b1,a1
norm .L2X b1,b1
or .M1 a1,a2,a3
or .L1 a1,a2
or .D1 -17,a0,a0
or .D1X 16,b0,a0
or .L1 -17,a0,a0
or .L1X 16,b0,a0
or .S2 -17,b0,b0
or .S2X 16,a0,b0
or .D1 a0,a0,b0
or .D2X b0,b0,b0
or .L1X a0,a0,a0
or .S2 b0,b0,a0
pack2 .D1 a0,a0,a0
pack2 .L1 a0,a0
pack2 .S1 a0,a1,b2
pack2 .L2X b0,b0,b0
packh2 .M1 a0,a0,a0
packh2 .L1 a0,a0
packh2 .S1 a0,a1,b2
packh2 .L2X b0,b0,b0
packh4 .S1 a0,a0,a0
packh4 .L1 a0,a0
packh4 .L1 a0,a1,b2
packh4 .L2X b0,b0,b0
packhl2 .M1 a0,a0,a0
packhl2 .L1 a0,a0
packhl2 .S1 a0,a1,b2
packhl2 .L2X b0,b0,b0
packlh2 .D1 a0,a0,a0
packlh2 .L1 a0,a0
packlh2 .S1 a0,a1,b2
packlh2 .L2X b0,b0,b0
packl4 .S1 a0,a0,a0
packl4 .L1 a0,a0
packl4 .L1 a0,a1,b2
packl4 .L2X b0,b0,b0
rcpdp .L1 a1:a0,a1:a0
rcpdp .S1 a1:a0
rcpdp .S1 b1:b0,a1:a0
rcpdp .S2X a1:a0,b1:b0
rcpsp .L1 a0,a0
rcpsp .S1 a0,a0,a0
rcpsp .S2 b0,a0
rcpsp .S1X a0,a0
rint .S2
rint a0
rotl .S1 a0,a0,a0
rotl .M1 a0,a0
rotl .M1 a0,b0,a0
rotl .M2X b0,b0,b0
rotl .M1 a0,-1,a0
rotl .M2 b0,32,b0
rotl .M2X b0,0,b0
rpack2 .L1 a0,a0,a0
rpack2 .S1 a0,a0
rpack2 .S2 a0,b0,b0
rpack2 .S1X a0,a0,a0
rsqrdp .L1 a1:a0,a1:a0
rsqrdp .S1 a1:a0
rsqrdp .S1 b1:b0,a1:a0
rsqrdp .S2X a1:a0,b1:b0
rsqrsp .L1 a0,a0
rsqrsp .S1 a0,a0,a0
rsqrsp .S2 b0,a0
rsqrsp .S1X a0,a0
sadd .D1 a1,a2,a3
sadd .L1 a1,a2
sadd .S1 0,a1,a2
sadd .L1X 0,a1:a0,a1:a0
sadd .L1 b0,a0,a0
sadd .L1X a0,a0,a0
sadd .L2 -17,b0,b0
sadd .L2 16,b0,b0
sadd .L1 -17,a1:a0,a1:a0
sadd .L1 16,a1:a0,a1:a0
sadd2 .L1 a0,a0,a0
sadd2 .S1 a0,a0
sadd2 .S2 a0,b0,b0
sadd2 .S2X b0,b0,b0
saddsub .S1 a0,a0,a1:a0
saddsub .L1 a0,a0
saddsub .L1 a0,a0,a0
saddsub .L2 a0,b0,b1:b0
saddsub .L2X b0,b0,b1:b0
saddsub2 .S1 a0,a0,a1:a0
saddsub2 .L1 a0,a0
saddsub2 .L1 a0,a0,a0
saddsub2 .L2 a0,b0,b1:b0
saddsub2 .L2X b0,b0,b1:b0
saddsu2 .L1 a0,a0,a0
saddsu2 .S1 a0
saddsu2 .S2 b0,a0,b0
saddsu2 .S2X b0,b0,b0
saddus2 .M1 a0,a0,a0
saddus2 .S1 a0,a0
saddus2 .S1 b0,a0,a0
saddus2 .S1X a0,a0,a0
saddu4 .D1 a0,a0,a0
saddu4 .S1 a0,a0
saddu4 .S1 b0,a0,a0
saddu4 .S1X a0,a0,a0
sat .S1 a1:a0,a0
sat .L1X b1:b0,a0
sat .L1 a1:a0
sat .L1 b1:b0,a0
set .L1 a0,0,0,a0
set .S1 a0
set .S1 a0,-1,0,a0
set .S1 a0,32,0,a0
set .S1 a0,0,-1,a0
set .S1 a0,0,32,a0
set .S1X b0,0,0,a0
set .S1X a0,a0,a0
set .S2 b0,a0,b0
shfl .S1 a0,a0
shfl .M1 a0,a0,a0
shfl .M1 a0,b0
shfl .M2X b0,b0
shfl3 .M1 a0,a0,a1:a0
shfl3 .L1 a0,a0
shfl3 .L1 b0,a0,a1:a0
shfl3 .L2X b0,b0,b1:b0
shl .L1 a0,a0,a0
shl .S1 a0,a0
shl .S1X a1:a0,a0,a1:a0
shl .S1 a0,b0,a0
shl .S2X b0,b0,b1:b0
shl .S1 a0,-1,a0
shl .S1 a0,32,a0
shl .S2 b1:b0,-1,b1:b0
shl .S2 b1:b0,32,b1:b0
shl .S1X b0,-1,a1:a0
shl .S1X b0,32,a1:a0
shlmb .D1 a0,a0,a0
shlmb .L1 a0,a0
shlmb .L1 b0,a0,a0
shlmb .L2X b0,b0,b0
shlmb .S1 b0,a0,a0
shlmb .S2X b0,b0,b0
shr .L1 a0,a0,a0
shr .S1 a0,a0
shr .S1X a1:a0,a0,a1:a0
shr .S1 a0,b0,a0
shr .S1 a0,-1,a0
shr .S1 a0,32,a0
shr .S2 b1:b0,-1,b1:b0
shr .S2 b1:b0,32,b1:b0
shr2 .L1 a0,a0,a0
shr2 .L1 a0,0,a0
shr2 .S1 a0,a0
shr2 .S1 a1,b0,a0
shr2 .S2X b0,b0,b0
shr2 .S1 a0,-1,a0
shr2 .S1 a0,32,a0
shrmb .M1 a0,a0,a0
shrmb .L1 a0,a0
shrmb .L1 b0,a0,a0
shrmb .L2X b0,b0,b0
shrmb .S1 b0,a0,a0
shrmb .S2X b0,b0,b0
shru .D1 a0,a0,a0
shru .S1 a0,a0
shru .S1X a1:a0,a0,a1:a0
shru .S1 a0,b0,a0
shru .S1 a0,-1,a0
shru .S1 a0,32,a0
shru .S2 b1:b0,-1,b1:b0
shru .S2 b1:b0,32,b1:b0
shru2 .L1 a0,a0,a0
shru2 .L1 a0,0,a0
shru2 .S1 a0,a0
shru2 .S1 a1,b0,a0
shru2 .S2X b0,b0,b0
shru2 .S1 a0,-1,a0
shru2 .S1 a0,32,a0
smpy .L1 a0,a0,a0
smpy .M1 a0,a0
smpy .M2 a0,b0,b0
smpy .M1X a0,a0,a0
smpyh .S1 a0,a0,a0
smpyh .M1 a0,a0
smpyh .M2 a0,b0,b0
smpyh .M1X a0,a0,a0
smpyhl .D1 a0,a0,a0
smpyhl .M1 a0,a0
smpyhl .M2 a0,b0,b0
smpyhl .M1X a0,a0,a0
smpylh .L1 a0,a0,a0
smpylh .M1 a0,a0
smpylh .M2 a0,b0,b0
smpylh .M1X a0,a0,a0
smpy2 .S1 a0,a0,a1:a0
smpy2 .M1 a0,a0
smpy2 .M2 a0,b0,b1:b0
smpy2 .M2X b0,b0,b1:b0
smpy32 .L1 a0,a0,a0
smpy32 .M1 a0,a0
smpy32 .M2 a0,b0,b0
smpy32 .M1X a0,a0,a0
spack2 .L1 a0,a0,a0
spack2 .S1 a0,a0
spack2 .S1 b0,a0,a0
spack2 .S2X b0,b0,b0
spacku4 .L1 a0,a0,a0
spacku4 .S1 a0,a0
spacku4 .S1 b0,a0,a0
spacku4 .S2X b0,b0,b0
spdp .M1 a0,a1:a0
spdp .S1 a0
spdp .S1 a0,b1:b0
spdp .S2X b0,b1:b0
spint .S1 a0,a0
spint .L1 a0,a0,a0
spint .L2 b0,a0
spint .L1X a0,a0
sptrunc .D1 a0,a0
sptrunc .L1 a0,a0,a0
sptrunc .L2 b0,a0
sptrunc .L1X a0,a0
sshl .L1 a0,a0,a0
sshl .S1 a0,a0
sshl .S1 a0,b0,a0
sshl .S1X a0,a0,a0
sshl .S2 b0,-1,b0
sshl .S2 b0,32,b0
sshvl .S1 a0,a0,a0
sshvl .M1 a0,a0
sshvl .M1 a0,b0,a0
sshvl .M1X a0,a0,a0
sshvr .L1 a0,a0,a0
sshvr .M1 a0,a0
sshvr .M1 a0,b0,a0
sshvr .M1X a0,a0,a0
ssub .S1 a0,a0,a0
ssub .L1 a0,a0
ssub .L1 a0,a0,b0
ssub .L1X a0,a0,a0
ssub .L2 -17,b0,b0
ssub .L2 16,b0,b0
ssub .L1X 0,a1:a0,a1:a0
ssub .L1 -17,a1:a0,a1:a0
ssub .L1 16,a1:a0,a1:a0
ssub2 .S1 a0,a0,a0
ssub2 .L1 a0,a0
ssub2 .L1 a0,b0,a0
ssub2 .L1X a0,a0,a0
stb .L1 a0,*a1
stb .D1T1 b1,*a1
stb .D1T1 a1,*b1
stb .D2T2 b1,*a1
stb .D2T2 a1,*b1
stb .D1T1 *a1
stb .D1T1 a2,*+a1[b1]
stb .D1T1 a2,*+a1
stb .D1T1 a2,*-a1
stb .D1T1 a2,*a1++[32]
stb .D1T1 a2,*a1++(32)
stb .D1T1 a2,*--a1[-1]
stb .D1T1 a2,*--a1(-1)
stb .D1T1 a3,*+a1(a2)
stb .D2T2 b16,*+b14[foo]
stb .D2T2 b1,*+b14[-1]
stb .D2T2 b1,*+b14[32768]
stdw .L1 a1:a0,*a1
stdw .D1T1 b1:b0,*a1
stdw .D1T1 a1:a0,*b1
stdw .D2T2 b1:b0,*a1
stdw .D2T2 a1:a0,*b1
stdw .D1T1 *a1
stdw .D1T1 a3:a2,*+a1[b1]
stdw .D1T1 a3:a2,*+a1
stdw .D1T1 a3:a2,*-a1
stdw .D1T1 a3:a2,*a1++[32]
stdw .D1T1 a3:a2,*a1++(256)
stdw .D1T1 a3:a2,*--a1[-1]
stdw .D1T1 a3:a2,*--a1(-8)
stdw .D1T1 a3:a2,*+a1(a2)
stdw .D2T2 b17:b16,*+b14[foo]
stdw .D1T1 a3:a2,*+a1(1)
stdw .D2T2 b17:b16,*+b14(b15)
sth .M1 a0,*a1
sth .D1T1 b1,*a1
sth .D1T1 a1,*b1
sth .D2T2 b1,*a1
sth .D2T2 a1,*b1
sth .D1T1 *a1
sth .D1T1 a2,*+a1[b1]
sth .D1T1 a2,*+a1
sth .D1T1 a2,*-a1
sth .D1T1 a2,*a1++[32]
sth .D1T1 a2,*a1++(64)
sth .D1T1 a2,*--a1[-1]
sth .D1T1 a2,*--a1(-2)
sth .D1T1 a3,*+a1(a2)
sth .D2T2 b16,*+b14[foo]
sth .D2T2 b2,*+b1(1)
sth .D2T2 b1,*+b14[-1]
sth .D2T2 b1,*+b14[32768]
stndw .L1 a1:a0,*a1
stndw .D1T1 b1:b0,*a1
stndw .D1T1 a1:a0,*b1
stndw .D2T2 b1:b0,*a1
stndw .D2T2 a1:a0,*b1
stndw .D1T1 *a1
stndw .D1T1 a3:a2,*+a1[b1]
stndw .D1T1 a3:a2,*+a1
stndw .D1T1 a3:a2,*-a1
stndw .D1T1 a3:a2,*a1++[32]
stndw .D1T1 a3:a2,*a1++(32)
stndw .D1T1 a3:a2,*--a1[-1]
stndw .D1T1 a3:a2,*--a1(-1)
stndw .D2T2 b17:b16,*+b14[foo]
stnw .S1 a0,*a1
stnw .D1T1 b1,*a1
stnw .D1T1 a1,*b1
stnw .D2T2 b1,*a1
stnw .D2T2 a1,*b1
stnw .D1T1 *a1
stnw .D1T1 a2,*+a1[b1]
stnw .D1T1 a2,*+a1
stnw .D1T1 a2,*-a1
stnw .D1T1 a2,*a1++[32]
stnw .D1T1 a2,*a1++(128)
stnw .D1T1 a2,*--a1[-1]
stnw .D1T1 a2,*--a1(-4)
stnw .D1T1 a3,*+a1(a2)
stnw .D2T2 b16,*+b14[foo]
stnw .D2T2 b2,*+b1(2)
stw .S1 a0,*a1
stw .D1T1 b1,*a1
stw .D1T1 a1,*b1
stw .D2T2 b1,*a1
stw .D2T2 a1,*b1
stw .D1T1 *a1
stw .D1T1 a2,*+a1[b1]
stw .D1T1 a2,*+a1
stw .D1T1 a2,*-a1
stw .D1T1 a2,*a1++[32]
stw .D1T1 a2,*a1++(128)
stw .D1T1 a2,*--a1[-1]
stw .D1T1 a2,*--a1(-4)
stw .D1T1 a3,*+a1(a2)
stw .D2T2 b16,*+b14[foo]
stw .D2T2 b2,*+b1(2)
stw .D2T2 b1,*+b14[-1]
stw .D2T2 b1,*+b14[32768]
neg .D1 a1,a2
neg .S1 a1:a0,a1:a0
neg .S1 a1,a1,a1
neg .S1 a1,b1
neg .S1X a1,a1
neg .L2X b1:b0,b1:b0
neg .L2 b0,a0
neg .L2X b0,b0
sub .M1 a0,a0,a0
sub .L1 a0,a0
sub .L1 b0,b0,a0
sub .L2X b0,b0,b0
sub .L1X 0,a1:a0,a1:a0
sub .L2 -17,b0,b0
sub .L2 16,b0,b0
sub .L1 -17,a1:a0,a1:a0
sub .L1 16,a1:a0,a1:a0
sub .S1 a0,a0
sub .S1 a0,a0,b0
sub .S1X a0,a0,a0
sub .S1 -17,a0,a0
sub .S1 16,a0,a0
sub .S1 0,a1:a0,a1:a0
sub .D1 a0
sub .D1 b0,a0,a0
sub .D1X a0,a0,a0
sub .D1X b0,0,a0
sub .D1 a0,-1,a0
sub .D1 a0,32,a0
subab .S1 a0,a0,a0
subab .D1 a0,a0
subab .D1 a0,b0,a0
subab .D1X a0,b0,a0
subab .D1X b0,0,a0
subab .D2 b0,-1,b0
subab .D2 b14,32,b14
subabs4 .S1 a0,a0,a0
subabs4 .L1 a0,a0
subabs4 .L1 a0,a0,b0
subabs4 .L2X b0,b0,b0
subah .M1 a0,a0,a0
subah .D1 a0,a0
subah .D1 a0,b0,a0
subah .D1X a0,b0,a0
subah .D1X b0,0,a0
subah .D2 b0,-1,b0
subah .D2 b14,32,b14
subaw .L1 a0,a0,a0
subaw .D1 a0,a0
subaw .D1 a0,b0,a0
subaw .D1X a0,b0,a0
subaw .D1X b0,0,a0
subaw .D2 b0,-1,b0
subaw .D2 b14,32,b14
subc .S1 a0,a0,a0
subc .L1 a0,a0
subc .L1 b0,a0,a0
subc .L2X b0,b0,b0
subdp .D1 a1:a0,a1:a0,a1:a0
subdp .L1 a1:a0
subdp .L1 b1:b0,a1:a0,a1:a0
subdp .L1X a1:a0,a1:a0,a1:a0
subdp .S1 b1:b0,a1:a0,a1:a0
subdp .S1X a1:a0,a1:a0,a1:a0
subsp .M1 a0,a0,a0
subsp .L1 a0,a0
subsp .L1 a0,a0,b0
subsp .L2X b0,b0,b0
subsp .S1 a0,a0
subsp .S1 a0,a0,b0
subsp .S2X b0,b0,b0
subu .S1 a0,a0,a1:a0
subu .L1 a0,a0
subu .L1 a0,a0,a0
subu .L2 b0,b0,a1:a0
subu .L1X a0,a0,a1:a0
sub2 .M1 a0,a0,a0
sub2 .L1 a0,a0
sub2 .L1 a0,a0,b0
sub2 .L2X b0,b0,b0
sub2 .S1 a0,a0
sub2 .S1 a0,a0,b0
sub2 .S2X b0,b0,b0
sub2 .D1 a0,a0
sub2 .D1 a0,a0,b0
sub2 .D2X b0,b0,b0
sub4 .S1 a0,a0,a0
sub4 .L1 a0,a0
sub4 .L1 a0,a0,b0
sub4 .L2X b0,b0,b0
swap2 .D1 a0,a0
swap2 .L1 a0,a0,a0
swap2 .L1X b0,a0
swap2 .L2 a0,b0
swap2 .S1 a0,a0,a0
swap2 .S1X b0,a0
swap2 .S2 a0,b0
swap4 .S1 a0,a0
swap4 .L1 a0
swap4 .L1 a0,b0
swap4 .L1X a0,a0
swe .S1
swe a0
swenr .L1
swenr b0
unpkhu4 .D1 a0,a0
unpkhu4 .L1 a0,a0,a0
unpkhu4 .L1 a0,b0
unpkhu4 .L2X b0,b0
unpkhu4 .S1 a0,a0,a0
unpkhu4 .S1 a0,b0
unpkhu4 .S2X b0,b0
unpklu4 .M1 a0,a0
unpklu4 .L1 a0,a0,a0
unpklu4 .L1 a0,b0
unpklu4 .L2X b0,b0
unpklu4 .S1 a0,a0,a0
unpklu4 .S1 a0,b0
unpklu4 .S2X b0,b0
not .M1 a0,a0
not .L1 a0,a0,a0
not .L1 a0,b0
not .L1X a0,a0
not .S1 a0,a0,a0
not .S1 a0,b0
not .S1X a0,a0
not .D1 a0,a0,a0
not .D1 a0,b0
not .D1X a0,a0
xor .M1 a0,a0,a0
xor .L1 a0,a0
xor .L2 b0,b0,a0
xor .L2X b0,b0,b0
xor .L1 -17,a0,a0
xor .L1 16,a0,a0
xor .S1 a0,a0
xor .S2 b0,b0,a0
xor .S2X b0,b0,b0
xor .S1 -17,a0,a0
xor .S1 16,a0,a0
xor .D1 a0,a0
xor .D2 b0,b0,a0
xor .D2X b0,b0,b0
xor .D1 -17,a0,a0
xor .D1 16,a0,a0
xormpy .L1 a0,a0,a0
xormpy .M1 a0,a0
xormpy .M1 b0,a0,a0
xormpy .M1X a0,a0,a0
xpnd2 .S1 a0,a0
xpnd2 .M1 a0,a0,a0
xpnd2 .M1 a0,b0
xpnd2 .M1X a0,a0
xpnd4 .L1 a0,a0
xpnd4 .M1 a0,a0,a0
xpnd4 .M1 a0,b0
xpnd4 .M1X a0,a0
zero .M1 a0
zero .L1 a0,a0
zero .L2 a0
zero .D1 a0,a0
zero .D2 a0
zero .S1 a0,a0
zero .S2 a0
sub .L1 a0,17,a0
sub .L1 a0,-16,a0
sub .L1 a1:a0,17,a1:a0
sub .L1 a1:a0,-16,a1:a0
sub .S1 a0,17,a0
sub .S1 a0,-16,a0
addab .D1X b13,0,a5
addah .D1X b13,0,a5
addaw .D1X b13,0,a5
|
stsp/binutils-ia16
| 2,174
|
gas/testsuite/gas/tic6x/reloc-bad-3.s
|
# Test relocation overflow and insufficiently divisible values. Note
# that divisibility checks for constant values are only applicable to
# load and store offsets, not ADDA, because constant values are
# encoded literally for ADDA, and divisbility checks for offsets from
# symbols are only applicable with REL relocations.
.data
t0:
.short b65535-b0
.short b65536-b0
.short b0-b32768
.short b32767-b65536
.byte b255-b0
.byte b256-b0
.byte b0-b128
.byte b127-b256
.text
.nocmp
.globl f
f:
addab .D1X b14,b32767-b0,a5
addab .D1X b14,b32768-b0,a5
addab .D1X b14,b127-b128,a5
addah .D1X b14,b32767-b0,a5
addah .D1X b14,b32768-b0,a5
addah .D1X b14,b127-b128,a5
addaw .D1X b14,b32767-b0,a5
addaw .D1X b14,b32768-b0,a5
addaw .D1X b14,b127-b128,a5
addk .S1 b32767-b0,a9
addk .S1 b0-b32768,a9
addk .S1 b32768-b0,a9
addk .S1 b32767-b65536,a9
mvk .S1 b32767-b0,a9
mvk .S1 b0-b32768,a9
mvk .S1 b32768-b0,a9
mvk .S1 b32767-b65536,a9
ldb .D2T2 *+b14(b32767-b0),b1
ldb .D2T2 *+b14(b32768-b0),b1
ldb .D2T2 *+b14(b32767-b32768),b1
ldbu .D2T2 *+b14(b32767-b0),b1
ldbu .D2T2 *+b14(b32768-b0),b1
ldbu .D2T2 *+b14(b32767-b32768),b1
ldh .D2T2 *+b14(h32767-h0),b1
ldh .D2T2 *+b14(h32768-h0),b1
ldh .D2T2 *+b14(h32767-h32768),b1
ldh .D2T2 *+b14(b32768-b32767),b1
ldhu .D2T2 *+b14(h32767-h0),b1
ldhu .D2T2 *+b14(h32768-h0),b1
ldhu .D2T2 *+b14(h32767-h32768),b1
ldhu .D2T2 *+b14(b32768-b32767),b1
ldw .D2T2 *+b14(w32767-w0),b1
ldw .D2T2 *+b14(w32768-w0),b1
ldw .D2T2 *+b14(w32767-w32768),b1
ldw .D2T2 *+b14(h32768-h32767),b1
stb .D2T2 b1,*+b14(b32767-b0)
stb .D2T2 b1,*+b14(b32768-b0)
stb .D2T2 b1,*+b14(b32767-b32768)
sth .D2T2 b1,*+b14(h32767-h0)
sth .D2T2 b1,*+b14(h32768-h0)
sth .D2T2 b1,*+b14(h32767-h32768)
sth .D2T2 b1,*+b14(b32768-b32767)
stw .D2T2 b1,*+b14(w32767-w0)
stw .D2T2 b1,*+b14(w32768-w0)
stw .D2T2 b1,*+b14(w32767-w32768)
stw .D2T2 b1,*+b14(h32768-h32767)
b0:
.space 127
b127:
.space 1
b128:
.space 127
b255:
.space 1
b256:
.space 32511
b32767:
.space 1
b32768:
.space 32767
b65535:
.space 1
b65536:
.word 0
h0:
.space 65534
h32767:
.space 2
h32768:
.word 0
w0:
.space 131068
w32767:
.space 4
w32768:
.word 0
|
stsp/binutils-ia16
| 2,453
|
gas/testsuite/gas/tic6x/insns16-doff4.s
|
; Test C64x+ 16 bits instructions - doff4 format
.text
.nocmp
doff4:
nop
.align 16
nop
.align 16
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefe00000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefe8c000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefe9c000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefeac000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefebc000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefecc000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefedc000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefeec000
.short 0x0004
.short 0x1004
.short 0x0204
.short 0x000c
.short 0x0005
.short 0x1005
.short 0x0205
.short 0x000d
.short 0x1005
.short 0x0205
.short 0x120d
.short 0x2a0d
.short 0x3a1d
.short 0x221d
.word 0xefefc000
.short 0x0014
.short 0x1014
.short 0x0214
.short 0x001c
.short 0x0015
.short 0x1015
.short 0x0215
.short 0x001d
.short 0x1015
.short 0x0215
.short 0x121d
.short 0x2a1d
.short 0x3a1d
.short 0x221d
.word 0xefefc000
|
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