lumees/github-code-2025-language-split · Datasets at Hugging Face

repo_id stringlengths 5 115	size int64 590 5.01M	file_path stringlengths 4 212	content stringlengths 590 5.01M
stsp/binutils-ia16	1,965	gas/testsuite/gas/sparc/hpcvis3.s	# Test HPC/VIS3 instructions .text nop nop ldx [%g3], %efsr nop 1: nop fnadds %f1, %f2, %f3 fnaddd %f2, %f4, %f6 fnmuls %f3, %f5, %f7 fnmuld %f6, %f8, %f10 fhadds %f7, %f9, %f11 fhaddd %f8, %f10, %f12 fhsubs %f9, %f11, %f13 fhsubd %f10, %f12, %f14 fnhadds %f11, %f13, %f15 fnhaddd %f12, %f14, %f16 fnsmuld %f13, %f15, %f16 fmadds %f15, %f17, %f19, %f21 fmaddd %f14, %f16, %f18, %f20 fmsubs %f17, %f19, %f21, %f23 fmsubd %f16, %f18, %f20, %f22 fnmsubs %f19, %f21, %f23, %f25 fnmsubd %f18, %f20, %f22, %f24 fnmadds %f21, %f23, %f25, %f27 fnmaddd %f20, %f22, %f24, %f26 fumadds %f23, %f25, %f27, %f29 fumaddd %f22, %f24, %f26, %f28 fumsubs %f25, %f27, %f29, %f31 fumsubd %f24, %f26, %f28, %f30 fnumsubs %f1, %f3, %f5, %f7 fnumsubd %f2, %f4, %f6, %f8 fnumadds %f3, %f5, %f7, %f9 fnumaddd %f4, %f6, %f8, %f10 addxc %g5, %g6, %g7 addxccc %o1, %o2, %o3 nop umulxhi %o5, %o6, %o7 lzcnt %i1, %i2 cmask8 %i3 cmask16 %i4 cmask32 %i5 fsll16 %f32, %f34, %f36 fsrl16 %f34, %f36, %f38 fsll32 %f36, %f38, %f40 fsrl32 %f38, %f40, %f42 fslas16 %f40, %f42, %f44 fsra16 %f42, %f44, %f46 fslas32 %f44, %f46, %f48 fsra32 %f46, %f48, %f50 pdistn %f48, %f50, %g1 fmean16 %f50, %f52, %f54 fpadd64 %f52, %f54, %f56 fchksm16 %f54, %f56, %f58 fpsub64 %f56, %f58, %f60 fpadds16 %f58, %f60, %f62 fpadds16s %f2, %f4, %f6 fpadds32 %f4, %f6, %f8 fpadds32s %f6, %f8, %f10 fpsubs16 %f8, %f10, %f12 fpsubs16s %f10, %f12, %f14 fpsubs32 %f12, %f14, %f16 fpsubs32s %f14, %f16, %f18 movdtox %f20, %g1 movstouw %f21, %g2 movstosw %f23, %g3 movxtod %g4, %f22 movwtos %g5, %f23 xmulx %o1, %o2, %o3 xmulxhi %o4, %o5, %o6 fucmple8 %f16, %f18, %g1 fucmpne8 %f18, %f20, %g2 fucmpgt8 %f20, %f22, %g3 fucmpeq8 %f22, %f24, %g4 flcmps %fcc0, %f1, %f3 flcmps %fcc1, %f3, %f5 flcmps %fcc2, %f5, %f7 flcmps %fcc3, %f7, %f9 flcmpd %fcc0, %f12, %f14 flcmpd %fcc1, %f14, %f16 flcmpd %fcc2, %f16, %f18 flcmpd %fcc3, %f18, %f20 lzd %i1, %i2
stsp/binutils-ia16	2,847	gas/testsuite/gas/sparc/splet.s	.text .global start ! Starting point start: ! test all ASRs rd %asr0, %l0 rd %asr1, %l0 rd %asr15, %l0 rd %asr17, %l0 rd %asr18, %l0 rd %asr19, %l0 ! should stop the processor rd %asr20, %l0 rd %asr21, %l0 rd %asr22, %l0 wr %l0, 0, %asr0 wr %l0, 0, %asr1 wr %l0, 0, %asr15 wr %l0, 0, %asr17 wr %l0, 0, %asr18 wr %l0, 0, %asr19 wr %l0, 0, %asr20 wr %l0, 0, %asr21 wr %l0, 0, %asr22 ! test UMUL with no overflow inside Y test_umul: umul %g1, %g2, %g3 ! test UMUL with an overflow inside Y umul %g1, %g2, %g3 ! %g3 must be equal to 0 ! test SMUL with negative result test_smul: smul %g1, %g2, %g3 ! test SMUL with positive result smul %g1, %g2, %g3 ! test STBAR: there are two possible syntaxes test_stbar: stbar ! is a valid V8 syntax, at least a synthetic ! instruction rd %asr15, %g0 ! other solution ! test UNIMP unimp 1 ! test FLUSH flush %l1 ! is the official V8 syntax ! test SCAN: find first 0 test_scan: scan %l1, 0xffffffff, %l3 ! test scan: find first 1 scan %l1, 0, %l3 ! test scan: find first bit != bit-0 scan %l1, %l1, %l3 ! test SHUFFLE test_shuffle: shuffle %l0, 0x1, %l1 shuffle %l0, 0x2, %l1 shuffle %l0, 0x4, %l1 shuffle %l0, 0x8, %l1 shuffle %l0, 0x10, %l1 shuffle %l0, 0x18, %l1 ! test UMAC test_umac: umac %l1, %l2, %l0 umac %l1, 2, %l0 umac 2, %l1, %l0 ! test UMACD test_umacd: umacd %l2, %l4, %l0 umacd %l2, 3, %l0 umacd 3, %l2, %l0 ! test SMAC test_smac: smac %l1, %l2, %l0 smac %l1, -42, %l0 smac -42, %l1, %l0 ! test SMACD test_smacd: smacd %l2, %l4, %l0 smacd %l2, 123, %l0 smacd 123, %l2, %l0 ! test UMULD test_umuld: umuld %o2, %o4, %o0 umuld %o2, 0x234, %o0 umuld 0x567, %o2, %o0 ! test SMULD test_smuld: smuld %i2, %i4, %i0 smuld %i2, -4096, %i0 smuld 4095, %i4, %i0 ! Coprocessor instructions test_coprocessor: ! %ccsr is register # 0 ! %ccfr is register # 1 ! %ccpr is register # 3 ! %cccrcr is register # 2 ! test CPUSH: just syntax cpush %l0, %l1 cpush %l0, 1 cpusha %l0, %l1 cpusha %l0, 1 ! test CPULL: just syntax cpull %l0 ! test CPRDCXT: just syntax crdcxt %ccsr, %l0 crdcxt %ccfr, %l0 crdcxt %ccpr, %l0 crdcxt %cccrcr, %l0 ! test CPWRCXT: just syntax cwrcxt %l0, %ccsr cwrcxt %l0, %ccfr cwrcxt %l0, %ccpr cwrcxt %l0, %cccrcr ! test CBccc: just syntax cbn stop nop cbn,a stop nop cbe stop nop cbe,a stop nop cbf stop nop cbf,a stop nop cbef stop nop cbef,a stop nop cbr stop nop cbr,a stop nop cber stop nop cber,a stop nop cbfr stop nop cbfr,a stop nop cbefr stop nop cbefr,a stop nop cba stop nop cba,a stop nop cbne stop nop cbne,a stop nop cbnf stop nop cbnf,a stop nop cbnef stop nop cbnef,a stop nop cbnr stop nop cbnr,a stop nop cbner stop nop cbner,a stop nop cbnfr stop nop cbnfr,a stop nop cbnefr stop nop cbnefr,a stop nop
stsp/binutils-ia16	1,832	gas/testsuite/gas/sparc/wrpr.s	# Test wrpr .text wrpr %g1,%g2,%tpc wrpr %g1,%tpc wrpr %g1,666,%tpc wrpr 666,%g1,%tpc wrpr 666,%tpc wrpr %g1,%g2,%tnpc wrpr %g1,%tnpc wrpr %g1,666,%tnpc wrpr 666,%g1,%tnpc wrpr 666,%tnpc wrpr %g1,%g2,%tstate wrpr %g1,%tstate wrpr %g1,666,%tstate wrpr 666,%g1,%tstate wrpr 666,%tstate wrpr %g1,%g2,%tt wrpr %g1,%tt wrpr %g1,666,%tt wrpr 666,%g1,%tt wrpr 666,%tt wrpr %g1,%g2,%tick wrpr %g1,%tick wrpr %g1,666,%tick wrpr 666,%g1,%tick wrpr 666,%tick wrpr %g1,%g2,%tba wrpr %g1,%tba wrpr %g1,666,%tba wrpr 666,%g1,%tba wrpr 666,%tba wrpr %g1,%g2,%pstate wrpr %g1,%pstate wrpr %g1,666,%pstate wrpr 666,%g1,%pstate wrpr 666,%pstate wrpr %g1,%g2,%tl wrpr %g1,%tl wrpr %g1,666,%tl wrpr 666,%g1,%tl wrpr 666,%tl wrpr %g1,%g2,%pil wrpr %g1,%pil wrpr %g1,666,%pil wrpr 666,%g1,%pil wrpr 666,%pil wrpr %g1,%g2,%cwp wrpr %g1,%cwp wrpr %g1,666,%cwp wrpr 666,%g1,%cwp wrpr 666,%cwp wrpr %g1,%g2,%cansave wrpr %g1,%cansave wrpr %g1,666,%cansave wrpr 666,%g1,%cansave wrpr 666,%cansave wrpr %g1,%g2,%canrestore wrpr %g1,%canrestore wrpr %g1,666,%canrestore wrpr 666,%g1,%canrestore wrpr 666,%canrestore wrpr %g1,%g2,%cleanwin wrpr %g1,%cleanwin wrpr %g1,666,%cleanwin wrpr 666,%g1,%cleanwin wrpr 666,%cleanwin wrpr %g1,%g2,%otherwin wrpr %g1,%otherwin wrpr %g1,666,%otherwin wrpr 666,%g1,%otherwin wrpr 666,%otherwin wrpr %g1,%g2,%wstate wrpr %g1,%wstate wrpr %g1,666,%wstate wrpr 666,%g1,%wstate wrpr 666,%wstate wrpr %g1,%g2,%fq wrpr %g1,%fq wrpr %g1,666,%fq wrpr 666,%g1,%fq wrpr 666,%fq wrpr %g1,%g2,%gl wrpr %g1,%gl wrpr %g1,666,%gl wrpr 666,%g1,%gl wrpr 666,%gl wrpr %g1,%g2,%pmcdper wrpr %g1,%pmcdper wrpr %g1,666,%pmcdper wrpr 666,%g1,%pmcdper wrpr 666,%pmcdper wrpr %g1,%g2,%ver wrpr %g1,%ver wrpr %g1,666,%ver wrpr 666,%g1,%ver wrpr 666,%ver
stsp/binutils-ia16	1,196	gas/testsuite/gas/sparc/xcrypto.s	# Test OSA2015 CRYPTO instructions .text xmpmul 0 xmpmul 1 xmpmul 2 xmpmul 3 xmpmul 4 xmpmul 5 xmpmul 6 xmpmul 7 xmpmul 8 xmpmul 9 xmpmul 10 xmpmul 11 xmpmul 12 xmpmul 13 xmpmul 14 xmpmul 15 xmpmul 16 xmpmul 17 xmpmul 18 xmpmul 19 xmpmul 20 xmpmul 21 xmpmul 22 xmpmul 23 xmpmul 24 xmpmul 25 xmpmul 26 xmpmul 27 xmpmul 28 xmpmul 29 xmpmul 30 xmpmul 31 xmontmul 0 xmontmul 1 xmontmul 2 xmontmul 3 xmontmul 4 xmontmul 5 xmontmul 6 xmontmul 7 xmontmul 8 xmontmul 9 xmontmul 10 xmontmul 11 xmontmul 12 xmontmul 13 xmontmul 14 xmontmul 15 xmontmul 16 xmontmul 17 xmontmul 18 xmontmul 19 xmontmul 20 xmontmul 21 xmontmul 22 xmontmul 23 xmontmul 24 xmontmul 25 xmontmul 26 xmontmul 27 xmontmul 28 xmontmul 29 xmontmul 30 xmontmul 31 xmontsqr 0 xmontsqr 1 xmontsqr 2 xmontsqr 3 xmontsqr 4 xmontsqr 5 xmontsqr 6 xmontsqr 7 xmontsqr 8 xmontsqr 9 xmontsqr 10 xmontsqr 11 xmontsqr 12 xmontsqr 13 xmontsqr 14 xmontsqr 15 xmontsqr 16 xmontsqr 17 xmontsqr 18 xmontsqr 19 xmontsqr 20 xmontsqr 21 xmontsqr 22 xmontsqr 23 xmontsqr 24 xmontsqr 25 xmontsqr 26 xmontsqr 27 xmontsqr 28 xmontsqr 29 xmontsqr 30 xmontsqr 31
stsp/binutils-ia16	1,434	gas/testsuite/gas/sparc/cbcond.s	# Test CBCOND instructions .text cwbe %o1, %o2,1f cwbe %o1, 2, 1f cxbe %o2, %o3, 1f cxbe %o2, 3, 1f cwble %o3, %o4, 1f cwble %o3, 4, 1f cxble %o4, %o5, 1f cxble %o4, 5, 1f cwbl %o5, %l0, 1f cwbl %o5, 6, 1f cxbl %l0, %l1, 1f cxbl %l0, 7, 1f cwbleu %l1, %l2, 1f cwbleu %l1, 8, 1f cxbleu %l2, %l3, 1f cxbleu %l2, 9, 1f cwbcs %l3, %l4, 1f cwbcs %l3, 10, 1f cxbcs %l4, %l5, 1f cxbcs %l4, 11, 1f cwbneg %l5, %l6, 1f cwbneg %l5, 12, 1f cxbneg %l6, %l7, 1f cxbneg %l6, 13, 1f cwbvs %l7, %i0, 1f cwbvs %l7, 14, 1f cxbvs %i0, %i1, 1f cxbvs %i0, 15, 1f cwbne %i1, %i2, 1f cwbne %i1, 16, 1f cxbne %i2, %i3, 1f cxbne %i2, 17, 1f cwbg %i3, %i4, 1f cwbg %i3, 18, 1f cxbg %i4, %i5, 1f cxbg %i4, 19, 1f cwbge %i5, %o0, 1f cwbge %i5, 20, 1f cxbge %o0, %o1, 1f cxbge %o0, 21, 1f cwbgu %o1, %o2, 1f cwbgu %o1, 22, 1f cxbgu %o2, %o3, 1f cxbgu %o2, 22, 1f cwbcc %o3, %o4, 1f cwbcc %o3, 23, 1f cxbcc %o4, %o5, 1f cxbcc %o4, 24, 1f cwbpos %o5, %l0, 1f cwbpos %o5, 25, 1f cxbpos %l0, %l1, 1f cxbpos %l0, 25, 1f cwbvc %l1, %l2, 1f cwbvc %l1, 26, 1f cxbvc %l2, %l3, 1f cxbvc %l2, 27, 1f cwbz %l3, %l4, 1f cwbz %l3, 28, 1f cxbz %l4, %l5, 1f cxbz %l4, 29, 1f cwblu %l5, %l6, 1f cwblu %l5, 28, 1f cxblu %l6, %l7, 1f cxblu %l6, 29, 1f cwbnz %l7, %o0, 1f cwbnz %l7, 30, 1f cxbnz %o0, %o1, 1f cxbnz %o0, 31, 1f cwbgeu %o1, %o2, 1f cwbgeu %o1, 1, 1f cxbgeu %o2, %o3, 1f cxbgeu %o2, 2, 1f 1: nop
stsp/binutils-ia16	1,875	gas/testsuite/gas/sparc/crypto.s	# Test CRYPTO instructions .text md5 sha1 sha256 sha512 crc32c %f2, %f4, %f6 aes_kexpand0 %f4, %f6, %f8 aes_kexpand1 %f6, %f8, 0x7, %f10 aes_kexpand1 %f6, %f8, 6, %f10 aes_kexpand2 %f8, %f10, %f12 aes_eround01 %f10, %f12, %f14, %f16 aes_eround23 %f12, %f14, %f16, %f18 aes_dround01 %f14, %f16, %f18, %f20 aes_dround23 %f16, %f18, %f20, %f22 aes_eround01_l %f18, %f20, %f22, %f24 aes_eround23_l %f20, %f22, %f24, %f26 aes_dround01_l %f22, %f24, %f26, %f28 aes_dround23_l %f24, %f26, %f28, %f30 des_ip %f32, %f34 des_iip %f34, %f36 des_kexpand %f36, 7, %f38 des_round %f38, %f40, %f42, %f44 kasumi_fi_fi %f42, %f44, %f46 kasumi_fl_xor %f44, %f46, %f48, %f50 kasumi_fi_xor %f46, %f48, %f50, %f52 camellia_fl %f50, %f52, %f54 camellia_fli %f52, %f54, %f56 camellia_f %f54, %f56, %f58, %f60 mpmul 0 mpmul 1 mpmul 2 mpmul 3 mpmul 4 mpmul 5 mpmul 6 mpmul 7 mpmul 8 mpmul 9 mpmul 10 mpmul 11 mpmul 12 mpmul 13 mpmul 14 mpmul 15 mpmul 16 mpmul 17 mpmul 18 mpmul 19 mpmul 20 mpmul 21 mpmul 22 mpmul 23 mpmul 24 mpmul 25 mpmul 26 mpmul 27 mpmul 28 mpmul 29 mpmul 30 mpmul 31 montmul 0 montmul 1 montmul 2 montmul 3 montmul 4 montmul 5 montmul 6 montmul 7 montmul 8 montmul 9 montmul 10 montmul 11 montmul 12 montmul 13 montmul 14 montmul 15 montmul 16 montmul 17 montmul 18 montmul 19 montmul 20 montmul 21 montmul 22 montmul 23 montmul 24 montmul 25 montmul 26 montmul 27 montmul 28 montmul 29 montmul 30 montmul 31 montsqr 0 montsqr 1 montsqr 2 montsqr 3 montsqr 4 montsqr 5 montsqr 6 montsqr 7 montsqr 8 montsqr 9 montsqr 10 montsqr 11 montsqr 12 montsqr 13 montsqr 14 montsqr 15 montsqr 16 montsqr 17 montsqr 18 montsqr 19 montsqr 20 montsqr 21 montsqr 22 montsqr 23 montsqr 24 montsqr 25 montsqr 26 montsqr 27 montsqr 28 montsqr 29 montsqr 30 montsqr 31
stsp/binutils-ia16	1,347	gas/testsuite/gas/sparc/set64.s	# sparc64 set insn handling (includes set, setuw, setsw, setx) foo: set foo,%g2 set 0x76543210,%g3 set 0,%g4 set 65535,%g5 setx foo,%g1,%g2 setx -1,%g1,%g3 setx 0,%g1,%g3 setx 1,%g1,%g3 setx 4095,%g1,%g3 setx 4096,%g1,%g3 setx -4096,%g1,%g3 setx -4097,%g1,%g3 setx 65535,%g1,%g3 setx -65536,%g1,%g3 setx 2147483647,%g1,%g4 setx 2147483648,%g1,%g4 setx -2147483648,%g1,%g4 setx -2147483649,%g1,%g4 setx 4294967295,%g1,%g4 setx 4294967296,%g1,%g4 ! GAS doesn't handle large base10 numbers yet. ! setx 9223372036854775807,%g1,%g5 ! setx 9223372036854775808,%g1,%g5 ! setx -9223372036854775808,%g1,%g5 ! setx -9223372036854775809,%g1,%g5 setx 0x7fffffffffffffff,%g1,%g5 setx 0x8000000000000000,%g1,%g5 ! test only hh22 needed setx 0xffffffff00000000,%g1,%g5 ! test only hm10 needed setx 0xffffffff80000000,%g1,%g5 ! test sign-ext of lower 32 setx 0xffff0000ffff0000,%g1,%g5 ! test hh22,hi22 setx 0xffff000000000001,%g1,%g5 ! test hh22,lo10 setx 0x00000001ffff0001,%g1,%g5 ! test hm10,hi22,lo10 setx 0x00000001ffff0000,%g1,%g5 ! test hm10,hi22 setx 0x0000000100000001,%g1,%g5 ! test hm10,lo10 setuw foo,%g2 setuw 0x76543210,%g3 setuw 0,%g4 setuw 65535,%g5 setsw foo,%g2 setsw 0x76543210,%g3 setsw 0,%g4 setsw 65535,%g5 setsw 0xffffffff,%g1 setsw 0x7fffffff,%g2 setsw 0xffff0000,%g3 setsw -1,%g4
stsp/binutils-ia16	1,767	gas/testsuite/gas/sparc/ldm-stm.s	# Test ldm/stm/ldma/stma .text ldmsh [%g0+%g1], %g2 ldmsh [%g1], %g3 ldmsh [%g1+102], %g3 ldmsh [102+%g1], %g3 ldmsh [102], %g3 ldmuh [%g0+%g1], %g2 ldmuh [%g1], %g3 ldmuh [%g1+102], %g3 ldmuh [102+%g1], %g3 ldmuh [102], %g3 ldmsw [%g0+%g1], %g2 ldmsw [%g1], %g3 ldmsw [%g1+102], %g3 ldmsw [102+%g1], %g3 ldmsw [102], %g3 ldmuw [%g0+%g1], %g2 ldmuw [%g1], %g3 ldmuw [%g1+102], %g3 ldmuw [102+%g1], %g3 ldmuw [102], %g3 ldmx [%g0+%g1], %g2 ldmx [%g1], %g3 ldmx [%g1+102], %g3 ldmx [102+%g1], %g3 ldmx [102], %g3 ldmux [%g0+%g1], %g2 ldmux [%g1], %g3 ldmux [%g1+102], %g3 ldmux [102+%g1], %g3 ldmux [102], %g3 ldmsha [%g1+%g2] %asi, %g3 ldmsha [%g1] %asi, %g2 ldmuha [%g1+%g2] %asi, %g3 ldmuha [%g1] %asi, %g2 ldmswa [%g1+%g2] %asi, %g3 ldmswa [%g1] %asi, %g2 ldmuwa [%g1+%g2] %asi, %g3 ldmuwa [%g1] %asi, %g2 ldmxa [%g1+%g2] %asi, %g3 ldmxa [%g1] %asi, %g2 stmh %g2, [%g0+%g1] stmh %g3, [%g1] stmh %g3, [%g1+102] stmh %g3, [102+%g1] stmh %g3, [102] stmw %g2, [%g0+%g1] stmw %g3, [%g1] stmw %g3, [%g1+102] stmw %g3, [102+%g1] stmw %g3, [102] stmx %g2, [%g0+%g1] stmx %g3, [%g1] stmx %g3, [%g1+102] stmx %g3, [102+%g1] stmx %g3, [102] stmha %g2, [%g0+%g1] %asi stmha %g3, [%g1] %asi stmwa %g2, [%g0+%g1] %asi stmwa %g3, [%g1] %asi stmxa %g2, [%g0+%g1] %asi stmxa %g3, [%g1] %asi
stsp/binutils-ia16	46,880	gas/testsuite/gas/sh/arch/sh4al-dsp.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4al-dsp but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4al_dsp: ! Instructions introduced into sh4al-dsp clrdmxy ;!/* 0000000010001000 clrdmxy /{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up} ldrc r5 ;!/ 0100mmmm00110100 ldrc <REG_M> /{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up} ldrc #4 ;!/ 10001010i81.... ldrc #<imm> /{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up} setdmx ;!/* 0000000010011000 setdmx /{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up} setdmy ;!/ 0000000011001000 setdmy /{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up} movx.w @r1,y1 ;!/ nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> / {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up} movx.w @r1+,y1 ;!/ nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> /{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up} movx.w @r1+r8,y1 ;!/ nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> /{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up} movx.w a0,@r1 ;!/ nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> / {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up} movx.w a0,@r1+ ;!/ nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ /{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up} movx.w a0,@r1+r8 ;!/ nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 /{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up} movx.l @r1,y1 ;!/ nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> / {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up} movx.l @r1+,y1 ;!/ nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> /{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up} movx.l @r1+r8,y1 ;!/ nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> /{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up} movx.l a0,@r1 ;!/ nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> / {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up} movx.l a0,@r1+ ;!/ nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ /{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up} movx.l a0,@r1+r8 ;!/ nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 /{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up} movy.w @r3,y1 ;!/ nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> / {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up} movy.w @r3+,y1 ;!/ nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> /{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up} movy.w @r3+r9,y1 ;!/ nnmm000011 movy.w @<REG_Ayx>+r9,<DSP_REG_YX> /{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up} movy.w a0,@r3 ;!/ nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> / {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up} movy.w a0,@r3+ ;!/ nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ /{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up} movy.w a0,@r3+r9 ;!/ nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r9 /{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up} movy.l @r3,y1 ;!/ nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> / {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up} movy.l @r3+,y1 ;!/ nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> /{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up} movy.l @r3+r9,y1 ;!/ nnmm100011 movy.l @<REG_Ayx>+r9,<DSP_REG_YX> /{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up} movy.l a0,@r3 ;!/ nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> / {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up} movy.l a0,@r3+ ;!/ nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ /{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up} movy.l a0,@r3+r9 ;!/ nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r9 /{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up} dct pabs x1,m0 ;!/ 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> / {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up} dct pabs y0,m0 ;!/ 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> / {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up} dct prnd x1,m0 ;!/ 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> / {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up} dct prnd y0,m0 ;!/ 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> / {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up} dct psub y0,x1,m0 ;!/ 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> / {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up} dct pswap x1,m0 ;!/ 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> / {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} dct pswap y0,m0 ;!/ 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> / {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} ! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} icbi @r4 ;!/ 0000nnnn11100011 icbi @<REG_N> /{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,MOD ;!/ 0100nnnn01011110 ldc <REG_N>,MOD /{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} ldc r4,RE ;!/ 0100nnnn01111110 ldc <REG_N>,RE /{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} ldc r4,RS ;!/ 0100nnnn01101110 ldc <REG_N>,RS /{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,MOD ;!/ 0100nnnn01010111 ldc.l @<REG_N>+,MOD /{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RE ;!/ 0100nnnn01110111 ldc.l @<REG_N>+,RE /{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RS ;!/ 0100nnnn01100111 ldc.l @<REG_N>+,RS /{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} ldre @(8,PC) ;!/ 10001110i8p2.... ldre @(<disp>,PC) /{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} ldrs @(8,PC) ;!/ 10001100i8p2.... ldrs @(<disp>,PC) /{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,DSR ;!/ 0100nnnn01101010 lds <REG_N>,DSR /{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} lds r4,A0 ;!/ 0100nnnn01111010 lds <REG_N>,A0 /{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} lds r4,X0 ;!/ 0100nnnn10001010 lds <REG_N>,X0 /{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} lds r4,X1 ;!/ 0100nnnn10011010 lds <REG_N>,X1 /{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} lds r4,Y0 ;!/ 0100nnnn10101010 lds <REG_N>,Y0 /{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} lds r4,Y1 ;!/ 0100nnnn10111010 lds <REG_N>,Y1 /{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r4+,DSR ;!/ 0100nnnn01100110 lds.l @<REG_N>+,DSR /{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} lds.l @r4+,A0 ;!/ 0100nnnn01110110 lds.l @<REG_N>+,A0 /{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X0 ;!/ 0100nnnn10000110 lds.l @<REG_N>+,X0 /{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X1 ;!/ 0100nnnn10010110 lds.l @<REG_N>+,X1 /{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y0 ;!/ 0100nnnn10100110 lds.l @<REG_N>+,Y0 /{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y1 ;!/ 0100nnnn10110110 lds.l @<REG_N>+,Y1 /{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/ 0000nnnn11000011 movca.l R0,@<REG_N> /{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movco.l r0,@r4 ;!/ 0000nnnn01110011 movco.l r0,@<REG_N> /{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} movli.l @r5,r0 ;!/ 0000mmmm01100011 movli.l @<REG_M>,r0 /{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} movua.l @r5,r0 ;!/ 0100mmmm10101001 movua.l @<REG_M>,r0 /{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} movua.l @r5+,r0 ;!/ 0100mmmm11101001 movua.l @<REG_M>+,r0 /{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/ 0000nnnn10010011 ocbi @<REG_N> /{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/ 0000nnnn10100011 ocbp @<REG_N> /{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/ 0000nnnn10110011 ocbwb @<REG_N> /{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} prefi @r4 ;!/ 0000nnnn11010011 prefi @<REG_N> /{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} setrc r4 ;!/ 0100nnnn00010100 setrc <REG_N> /{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} setrc #4 ;!/ 10000010i81.... setrc #<imm> /{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} repeat 10 20 r4 ;!/* repeat start end <REG_N> /{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} repeat 10 20 #4 ;!/ repeat start end #<imm> /{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc MOD,r4 ;!/ 0000nnnn01010010 stc MOD,<REG_N> /{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} stc RE,r4 ;!/ 0000nnnn01110010 stc RE,<REG_N> /{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} stc RS,r4 ;!/ 0000nnnn01100010 stc RS,<REG_N> /{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/ 0000nnnn00111010 stc SGR,<REG_N> /{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/ 0000nnnn11111010 stc DBR,<REG_N> /{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l MOD,@-r4 ;!/ 0100nnnn01010011 stc.l MOD,@-<REG_N> /{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} stc.l RE,@-r4 ;!/ 0100nnnn01110011 stc.l RE,@-<REG_N> /{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} stc.l RS,@-r4 ;!/ 0100nnnn01100011 stc.l RS,@-<REG_N> /{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts DSR,r4 ;!/ 0000nnnn01101010 sts DSR,<REG_N> /{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} sts A0,r4 ;!/ 0000nnnn01111010 sts A0,<REG_N> /{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} sts X0,r4 ;!/ 0000nnnn10001010 sts X0,<REG_N> /{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} sts X1,r4 ;!/ 0000nnnn10011010 sts X1,<REG_N> /{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} sts Y0,r4 ;!/ 0000nnnn10101010 sts Y0,<REG_N> /{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} sts Y1,r4 ;!/ 0000nnnn10111010 sts Y1,<REG_N> /{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l DSR,@-r4 ;!/ 0100nnnn01100110 sts.l DSR,@-<REG_N> /{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} sts.l A0,@-r4 ;!/ 0100nnnn01110110 sts.l A0,@-<REG_N> /{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} sts.l X0,@-r4 ;!/ 0100nnnn10000110 sts.l X0,@-<REG_N> /{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} sts.l X1,@-r4 ;!/ 0100nnnn10010110 sts.l X1,@-<REG_N> /{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} sts.l Y0,@-r4 ;!/ 0100nnnn10100110 sts.l Y0,@-<REG_N> /{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} sts.l Y1,@-r4 ;!/ 0100nnnn10110110 sts.l Y1,@-<REG_N> /{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} synco ;!/ 0000000010101011 synco /{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} movs.w @-r4,a1 ;!/ 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> / {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} movs.w @r4,a1 ;!/ 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> / {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} movs.w @r4+,a1 ;!/ 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> / {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} movs.w @r4+r8,a1 ;!/ 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> / {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} movs.w a1,@-r4 ;!/ 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> / {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} movs.w a1,@r4 ;!/ 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> / {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} movs.w a1,@r4+ ;!/ 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ / {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} movs.w a1,@r4+r8 ;!/ 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 / {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} movs.l @-r4,a1 ;!/ 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> / {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} movs.l @r4,a1 ;!/ 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> / {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} movs.l @r4+,a1 ;!/ 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> / {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} movs.l @r4+r8,a1 ;!/ 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> / {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} movs.l a1,@-r4 ;!/ 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> / {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} movs.l a1,@r4 ;!/ 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> / {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} movs.l a1,@r4+ ;!/ 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ / {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} movs.l a1,@r4+r8 ;!/ 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 / {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} nopx ;!/ 00000* nopx / {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} nopy ;!/ 00000 nopy / {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} movx.w @r4,x1 ;!/* nm001* movx.w @<REG_N>,<DSP_REG_X> / {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} movx.w @r4+,x1 ;!/ nm010* movx.w @<REG_N>+,<DSP_REG_X> / {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} movx.w @r4+r8,x1 ;!/ nm011* movx.w @<REG_N>+r8,<DSP_REG_X> / {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} movx.w a1,@r4 ;!/ nm101* movx.w <DSP_REG_M>,@<REG_N> / {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} movx.w a1,@r4+ ;!/ nm110* movx.w <DSP_REG_M>,@<REG_N>+ / {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} movx.w a1,@r4+r8 ;!/ nm111* movx.w <DSP_REG_M>,@<REG_N>+r8 / {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} movy.w @r6,y0 ;!/ nm001 movy.w @<REG_N>,<DSP_REG_Y> / {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} movy.w @r6+,y0 ;!/* nm010 movy.w @<REG_N>+,<DSP_REG_Y> / {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} movy.w @r6+r9,y0 ;!/* nm011 movy.w @<REG_N>+r9,<DSP_REG_Y> / {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} movy.w a1,@r6 ;!/* nm101 movy.w <DSP_REG_M>,@<REG_N> / {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} movy.w a1,@r6+ ;!/* nm110 movy.w <DSP_REG_M>,@<REG_N>+ / {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} movy.w a1,@r6+r9 ;!/* nm111 movy.w <DSP_REG_M>,@<REG_N>+r9 / {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg / {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} psubc x1,y0,m0 ;!/ 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} paddc x1,y0,m0 ;!/ 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} pcmp x1,y0 ;!/ 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> / {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} pwsb x1,y0,m0 ;!/ 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} pwad x1,y0,m0 ;!/ 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} pabs x1,m0 ;!/ 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> / {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} pabs y0,m0 ;!/ 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> / {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} prnd x1,m0 ;!/ 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> / {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} prnd y0,m0 ;!/ 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> / {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} dct pshl x1,y0,m0 ;!/ 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} pshl #4,m0 ;!/ 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> / {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} dct psha x1,y0,m0 ;!/ 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} psha #4,m0 ;!/ 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> / {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} dct psub x1,y0,m0 ;!/ 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} dct padd x1,y0,m0 ;!/ 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} dct pand x1,y0,m0 ;!/ 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} dct pxor x1,y0,m0 ;!/ 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} dct por x1,y0,m0 ;!/ 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} dct pdec x1,m0 ;!/ 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> / {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} dct pdec y0,m0 ;!/ 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> / {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} dct pinc x1,m0 ;!/ 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> / {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} dct pinc y0,m0 ;!/ 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> / {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} dct pclr m0 ;!/ 10001101xxyynnnn pclr <DSP_REG_N> / {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} dct pdmsb x1,m0 ;!/ 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> / {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} dct pdmsb y0,m0 ;!/ 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> / {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} dct pneg x1,m0 ;!/ 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> / {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} dct pneg y0,m0 ;!/ 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> / {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} dct pcopy x1,m0 ;!/ 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> / {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} dct pcopy y0,m0 ;!/ 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> / {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} dct psts MACH,m0 ;!/ 11001101xxyynnnn psts MACH,<DSP_REG_N> / {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} dct psts MACL,m0 ;!/ 11011101xxyynnnn psts MACL,<DSP_REG_N> / {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} dct plds m0,MACH ;!/ 11101101xxyynnnn plds <DSP_REG_N>,MACH / {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} dct plds m0,MACL ;!/ 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
stsp/binutils-ia16	38,442	gas/testsuite/gas/sh/arch/sh3-dsp.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3-dsp but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3_dsp: ! Instructions introduced into sh3-dsp ! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu add #4,r4 ;!/* 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,MOD ;!/ 0100nnnn01011110 ldc <REG_N>,MOD /{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} ldc r4,RE ;!/ 0100nnnn01111110 ldc <REG_N>,RE /{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} ldc r4,RS ;!/ 0100nnnn01101110 ldc <REG_N>,RS /{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,MOD ;!/ 0100nnnn01010111 ldc.l @<REG_N>+,MOD /{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RE ;!/ 0100nnnn01110111 ldc.l @<REG_N>+,RE /{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RS ;!/ 0100nnnn01100111 ldc.l @<REG_N>+,RS /{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} ldre @(8,PC) ;!/ 10001110i8p2.... ldre @(<disp>,PC) /{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} ldrs @(8,PC) ;!/ 10001100i8p2.... ldrs @(<disp>,PC) /{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,DSR ;!/ 0100nnnn01101010 lds <REG_N>,DSR /{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} lds r4,A0 ;!/ 0100nnnn01111010 lds <REG_N>,A0 /{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} lds r4,X0 ;!/ 0100nnnn10001010 lds <REG_N>,X0 /{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} lds r4,X1 ;!/ 0100nnnn10011010 lds <REG_N>,X1 /{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} lds r4,Y0 ;!/ 0100nnnn10101010 lds <REG_N>,Y0 /{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} lds r4,Y1 ;!/ 0100nnnn10111010 lds <REG_N>,Y1 /{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r4+,DSR ;!/ 0100nnnn01100110 lds.l @<REG_N>+,DSR /{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} lds.l @r4+,A0 ;!/ 0100nnnn01110110 lds.l @<REG_N>+,A0 /{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X0 ;!/ 0100nnnn10000110 lds.l @<REG_N>+,X0 /{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X1 ;!/ 0100nnnn10010110 lds.l @<REG_N>+,X1 /{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y0 ;!/ 0100nnnn10100110 lds.l @<REG_N>+,Y0 /{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y1 ;!/ 0100nnnn10110110 lds.l @<REG_N>+,Y1 /{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} setrc r4 ;!/ 0100nnnn00010100 setrc <REG_N> /{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} setrc #4 ;!/ 10000010i81.... setrc #<imm> /{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} repeat 10 20 r4 ;!/* repeat start end <REG_N> /{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} repeat 10 20 #4 ;!/ repeat start end #<imm> /{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc MOD,r4 ;!/ 0000nnnn01010010 stc MOD,<REG_N> /{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} stc RE,r4 ;!/ 0000nnnn01110010 stc RE,<REG_N> /{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} stc RS,r4 ;!/ 0000nnnn01100010 stc RS,<REG_N> /{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l MOD,@-r4 ;!/ 0100nnnn01010011 stc.l MOD,@-<REG_N> /{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} stc.l RE,@-r4 ;!/ 0100nnnn01110011 stc.l RE,@-<REG_N> /{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} stc.l RS,@-r4 ;!/ 0100nnnn01100011 stc.l RS,@-<REG_N> /{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts DSR,r4 ;!/ 0000nnnn01101010 sts DSR,<REG_N> /{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} sts A0,r4 ;!/ 0000nnnn01111010 sts A0,<REG_N> /{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} sts X0,r4 ;!/ 0000nnnn10001010 sts X0,<REG_N> /{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} sts X1,r4 ;!/ 0000nnnn10011010 sts X1,<REG_N> /{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} sts Y0,r4 ;!/ 0000nnnn10101010 sts Y0,<REG_N> /{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} sts Y1,r4 ;!/ 0000nnnn10111010 sts Y1,<REG_N> /{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l DSR,@-r4 ;!/ 0100nnnn01100110 sts.l DSR,@-<REG_N> /{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} sts.l A0,@-r4 ;!/ 0100nnnn01110110 sts.l A0,@-<REG_N> /{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} sts.l X0,@-r4 ;!/ 0100nnnn10000110 sts.l X0,@-<REG_N> /{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} sts.l X1,@-r4 ;!/ 0100nnnn10010110 sts.l X1,@-<REG_N> /{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} sts.l Y0,@-r4 ;!/ 0100nnnn10100110 sts.l Y0,@-<REG_N> /{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} sts.l Y1,@-r4 ;!/ 0100nnnn10110110 sts.l Y1,@-<REG_N> /{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} movs.w @-r4,a1 ;!/ 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> / {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} movs.w @r4,a1 ;!/ 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> / {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} movs.w @r4+,a1 ;!/ 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> / {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} movs.w @r4+r8,a1 ;!/ 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> / {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} movs.w a1,@-r4 ;!/ 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> / {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} movs.w a1,@r4 ;!/ 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> / {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} movs.w a1,@r4+ ;!/ 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ / {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} movs.w a1,@r4+r8 ;!/ 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 / {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} movs.l @-r4,a1 ;!/ 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> / {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} movs.l @r4,a1 ;!/ 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> / {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} movs.l @r4+,a1 ;!/ 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> / {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} movs.l @r4+r8,a1 ;!/ 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> / {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} movs.l a1,@-r4 ;!/ 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> / {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} movs.l a1,@r4 ;!/ 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> / {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} movs.l a1,@r4+ ;!/ 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ / {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} movs.l a1,@r4+r8 ;!/ 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 / {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} nopx ;!/ 00000* nopx / {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} nopy ;!/ 00000 nopy / {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} movx.w @r4,x1 ;!/* nm001* movx.w @<REG_N>,<DSP_REG_X> / {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} movx.w @r4+,x1 ;!/ nm010* movx.w @<REG_N>+,<DSP_REG_X> / {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} movx.w @r4+r8,x1 ;!/ nm011* movx.w @<REG_N>+r8,<DSP_REG_X> / {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} movx.w a1,@r4 ;!/ nm101* movx.w <DSP_REG_M>,@<REG_N> / {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} movx.w a1,@r4+ ;!/ nm110* movx.w <DSP_REG_M>,@<REG_N>+ / {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} movx.w a1,@r4+r8 ;!/ nm111* movx.w <DSP_REG_M>,@<REG_N>+r8 / {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} movy.w @r6,y0 ;!/ nm001 movy.w @<REG_N>,<DSP_REG_Y> / {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} movy.w @r6+,y0 ;!/* nm010 movy.w @<REG_N>+,<DSP_REG_Y> / {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} movy.w @r6+r9,y0 ;!/* nm011 movy.w @<REG_N>+r9,<DSP_REG_Y> / {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} movy.w a1,@r6 ;!/* nm101 movy.w <DSP_REG_M>,@<REG_N> / {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} movy.w a1,@r6+ ;!/* nm110 movy.w <DSP_REG_M>,@<REG_N>+ / {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} movy.w a1,@r6+r9 ;!/* nm111 movy.w <DSP_REG_M>,@<REG_N>+r9 / {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg / {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} psubc x1,y0,m0 ;!/ 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} paddc x1,y0,m0 ;!/ 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} pcmp x1,y0 ;!/ 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> / {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} pwsb x1,y0,m0 ;!/ 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} pwad x1,y0,m0 ;!/ 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} pabs x1,m0 ;!/ 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> / {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} pabs y0,m0 ;!/ 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> / {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} prnd x1,m0 ;!/ 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> / {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} prnd y0,m0 ;!/ 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> / {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} dct pshl x1,y0,m0 ;!/ 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} pshl #4,m0 ;!/ 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> / {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} dct psha x1,y0,m0 ;!/ 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} psha #4,m0 ;!/ 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> / {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} dct psub x1,y0,m0 ;!/ 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} dct padd x1,y0,m0 ;!/ 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} dct pand x1,y0,m0 ;!/ 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} dct pxor x1,y0,m0 ;!/ 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} dct por x1,y0,m0 ;!/ 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} dct pdec x1,m0 ;!/ 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> / {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} dct pdec y0,m0 ;!/ 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> / {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} dct pinc x1,m0 ;!/ 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> / {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} dct pinc y0,m0 ;!/ 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> / {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} dct pclr m0 ;!/ 10001101xxyynnnn pclr <DSP_REG_N> / {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} dct pdmsb x1,m0 ;!/ 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> / {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} dct pdmsb y0,m0 ;!/ 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> / {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} dct pneg x1,m0 ;!/ 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> / {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} dct pneg y0,m0 ;!/ 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> / {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} dct pcopy x1,m0 ;!/ 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> / {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} dct pcopy y0,m0 ;!/ 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> / {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} dct psts MACH,m0 ;!/ 11001101xxyynnnn psts MACH,<DSP_REG_N> / {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} dct psts MACL,m0 ;!/ 11011101xxyynnnn psts MACL,<DSP_REG_N> / {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} dct plds m0,MACH ;!/ 11101101xxyynnnn plds <DSP_REG_N>,MACH / {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} dct plds m0,MACL ;!/ 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
stsp/binutils-ia16	25,681	gas/testsuite/gas/sh/arch/sh4a-nofpu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4a-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4a_nofpu: ! Instructions introduced into sh4a-nofpu icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> /{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} movco.l r0,@r4 ;!/ 0000nnnn01110011 movco.l r0,@<REG_N> /{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} movli.l @r5,r0 ;!/ 0000mmmm01100011 movli.l @<REG_M>,r0 /{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} movua.l @r5,r0 ;!/ 0100mmmm10101001 movua.l @<REG_M>,r0 /{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} movua.l @r5+,r0 ;!/ 0100mmmm11101001 movua.l @<REG_M>+,r0 /{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} prefi @r4 ;!/ 0000nnnn11010011 prefi @<REG_N> /{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} synco ;!/ 0000000010101011 synco /{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/ 0000nnnn11000011 movca.l R0,@<REG_N> /{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/ 0000nnnn10010011 ocbi @<REG_N> /{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/ 0000nnnn10100011 ocbp @<REG_N> /{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/ 0000nnnn10110011 ocbwb @<REG_N> /{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/ 0000nnnn00111010 stc SGR,<REG_N> /{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/ 0000nnnn11111010 stc DBR,<REG_N> /{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	25,376	gas/testsuite/gas/sh/arch/sh2e.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2e but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2e: ! Instructions introduced into sh2e lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ! Instructions inherited from ancestors: sh sh2 add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	20,277	gas/testsuite/gas/sh/arch/sh2.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2: ! Instructions introduced into sh2 bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} ! Instructions inherited from ancestors: sh add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
stsp/binutils-ia16	39,786	gas/testsuite/gas/sh/arch/sh2a.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a: ! Instructions introduced into sh2a fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) / {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up \| arch_op32} fmov.d @(2048,r5),xd2 ;!/ 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> / {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up \| arch_op32} fmov.s fr2,@(2048,r4) ;!/ 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) / {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up \| arch_op32} fmov.s @(2048,r5),fr1 ;!/ 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> / {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up \| arch_op32} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r5,TBR ;!/ 0100mmmm01001010 ldc <REG_M>,TBR /{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/ 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ /{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} mov.b @-r5,R0 ;!/ 0100nnnn11001011 mov.b @-<REG_M>,R0 /{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} mov.b r5,@(2048,r4) ;!/ 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) / {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} mov.b @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> / {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up \| arch_op32} mov.l r5,@(8,r4) ;!/ 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ /{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} mov.l @-r5,R0 ;!/ 0100nnnn11001011 mov.l @-<REG_M>,R0 /{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} mov.l r5,@(2048,r4) ;!/ 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) / {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up \| arch_op32} mov.l @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> / {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up \| arch_op32} mov.w r5,@(R0,r4) ;!/ 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ /{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} mov.w @-r5,R0 ;!/ 0100nnnn11011011 mov.w @-<REG_M>,R0 /{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} mov.w r5,@(2048,r4) ;!/ 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) / {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up \| arch_op32} mov.w @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> / {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up \| arch_op32} .align 2 mova @(8,PC),R0 ;!/ 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc TBR,r4 ;!/ 0000nnnn01001010 stc TBR,<REG_N> / {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fabs dr2 ;!/ 1111nnn001011101 fabs <D_REG_N> /{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fadd dr4,dr2 ;!/ 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/eq dr4,dr2 ;!/ 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fcmp/gt dr4,dr2 ;!/ 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/ 1111nnn010111101 fcnvds <D_REG_N>,FPUL/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/ 1111nnn010101101 fcnvsd FPUL,<D_REG_N>/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fdiv dr4,dr2 ;!/ 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} float FPUL,dr2 ;!/ 1111nnn000101101 float FPUL,<D_REG_N>/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov xd4,xd2 ;!/ 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov xd4,@r4 ;!/ 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/ 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fmul dr4,dr2 ;!/ 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fneg dr2 ;!/ 1111nnn001001101 fneg <D_REG_N> /{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} fschg ;!/ 1111001111111101 fschg /{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt fr1 ;!/ 1111nnnn01101101 fsqrt <F_REG_N> /{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsqrt dr2 ;!/ 1111nnn001101101 fsqrt <D_REG_N> /{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} fsub dr4,dr2 ;!/ 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ftrc dr2,FPUL ;!/ 1111nnnn00111101 ftrc <D_REG_N>,FPUL/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} bclr #4, r4 ;!/ 10000110nnnn0iii bclr #<imm>, <REG_N> / {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bclr.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) / {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bld #4, r4 ;!/ 10000111nnnn1iii bld #<imm>, <REG_N> / {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bld.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) / {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bset #4, r4 ;!/ 10000110nnnn1iii bset #<imm>, <REG_N> / {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bset.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) / {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bst #4, r4 ;!/ 10000111nnnn0iii bst #<imm>, <REG_N> / {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bst.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) / {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} clips.b r4 ;!/ 0100nnnn10010001 clips.b <REG_N> / {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} clips.w r4 ;!/ 0100nnnn10010101 clips.w <REG_N> / {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up} clipu.b r4 ;!/ 0100nnnn10000001 clipu.b <REG_N> / {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up} clipu.w r4 ;!/ 0100nnnn10000101 clipu.w <REG_N> / {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up} divs R0,r4 ;!/ 0100nnnn10010100 divs R0,<REG_N> / {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up} divu R0,r4 ;!/ 0100nnnn10000100 divu R0,<REG_N> / {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up} jsr/n @r5 ;!/ 0100mmmm01001011 jsr/n @<REG_M> / {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up} jsr/n @@(8,TBR) ;!/ 10000011dddddddd jsr/n @@(<disp>,TBR) / {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up} ldbank @r5,R0 ;!/ 0100mmmm11100101 ldbank @<REG_M>,R0 / {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/ 0100mmmm11110001 movml.l <REG_M>,@-R15 / {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/ 0100mmmm11110101 movml.l @R15+,<REG_M> / {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/ 0100mmmm11110000 movml.l <REG_M>,@-R15 / {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/ 0100mmmm11110100 movml.l @R15+,<REG_M> / {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up} movrt r4 ;!/ 0000nnnn00111001 movrt <REG_N> / {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up} mulr R0,r4 ;!/ 0100nnnn10000000 mulr R0,<REG_N> / {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up} nott ;!/ 0000000001101000 nott / {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up} resbank ;!/ 0000000001011011 resbank / {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up} rts/n ;!/ 0000000001101011 rts/n / {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up} rtv/n r5 ;!/ 0000mmmm01111011 rtv/n <REG_M>/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up} stbank R0,@r4 ;!/ 0100nnnn11100001 stbank R0,@<REG_N>/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up} band.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) / {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bandnot.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bldnot.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bor.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) / {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bornot.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) / {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bxor.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) / {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} movi20 #4,r4 ;!/ 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> / {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up \| arch_op32} movi20s #1024,r4 ;!/ 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> / {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up \| arch_op32} movu.b @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> / {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up \| arch_op32} movu.w @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up \| arch_op32}
stsp/binutils-ia16	30,134	gas/testsuite/gas/sh/arch/sh2a-or-sh4.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-or-sh4 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_or_sh4: ! Instructions introduced into sh2a-or-sh4 fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> /{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd dr4,dr2 ;!/ 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq dr4,dr2 ;!/ 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt dr4,dr2 ;!/ 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/ 1111nnn010111101 fcnvds <D_REG_N>,FPUL/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/ 1111nnn010101101 fcnvsd FPUL,<D_REG_N>/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv dr4,dr2 ;!/ 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} float FPUL,dr2 ;!/ 1111nnn000101101 float FPUL,<D_REG_N>/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmov xd4,xd2 ;!/ 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov xd4,@r4 ;!/ 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/ 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmul dr4,dr2 ;!/ 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg dr2 ;!/ 1111nnn001001101 fneg <D_REG_N> /{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} fschg ;!/ 1111001111111101 fschg /{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt dr2 ;!/ 1111nnn001101101 fsqrt <D_REG_N> /{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsub dr4,dr2 ;!/ 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc dr2,FPUL ;!/ 1111nnnn00111101 ftrc <D_REG_N>,FPUL/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/ 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsqrt fr1 ;!/ 1111nnnn01101101 fsqrt <F_REG_N> /{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
stsp/binutils-ia16	22,754	gas/testsuite/gas/sh/arch/sh3-nommu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3-nommu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3_nommu: ! Instructions introduced into sh3-nommu clrs ;!/* 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	35,839	gas/testsuite/gas/sh/arch/sh-dsp.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh-dsp but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh_dsp: ! Instructions introduced into sh-dsp ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD /{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} ldc r4,RE ;!/ 0100nnnn01111110 ldc <REG_N>,RE /{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} ldc r4,RS ;!/ 0100nnnn01101110 ldc <REG_N>,RS /{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} ldc.l @r4+,MOD ;!/ 0100nnnn01010111 ldc.l @<REG_N>+,MOD /{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RE ;!/ 0100nnnn01110111 ldc.l @<REG_N>+,RE /{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RS ;!/ 0100nnnn01100111 ldc.l @<REG_N>+,RS /{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} ldre @(8,PC) ;!/ 10001110i8p2.... ldre @(<disp>,PC) /{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} ldrs @(8,PC) ;!/ 10001100i8p2.... ldrs @(<disp>,PC) /{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} lds r4,DSR ;!/ 0100nnnn01101010 lds <REG_N>,DSR /{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} lds r4,A0 ;!/ 0100nnnn01111010 lds <REG_N>,A0 /{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} lds r4,X0 ;!/ 0100nnnn10001010 lds <REG_N>,X0 /{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} lds r4,X1 ;!/ 0100nnnn10011010 lds <REG_N>,X1 /{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} lds r4,Y0 ;!/ 0100nnnn10101010 lds <REG_N>,Y0 /{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} lds r4,Y1 ;!/ 0100nnnn10111010 lds <REG_N>,Y1 /{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} lds.l @r4+,DSR ;!/ 0100nnnn01100110 lds.l @<REG_N>+,DSR /{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} lds.l @r4+,A0 ;!/ 0100nnnn01110110 lds.l @<REG_N>+,A0 /{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X0 ;!/ 0100nnnn10000110 lds.l @<REG_N>+,X0 /{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X1 ;!/ 0100nnnn10010110 lds.l @<REG_N>+,X1 /{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y0 ;!/ 0100nnnn10100110 lds.l @<REG_N>+,Y0 /{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y1 ;!/ 0100nnnn10110110 lds.l @<REG_N>+,Y1 /{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} setrc r4 ;!/ 0100nnnn00010100 setrc <REG_N> /{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} setrc #4 ;!/ 10000010i81.... setrc #<imm> /{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} repeat 10 20 r4 ;!/* repeat start end <REG_N> /{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} repeat 10 20 #4 ;!/ repeat start end #<imm> /{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} stc MOD,r4 ;!/ 0000nnnn01010010 stc MOD,<REG_N> /{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} stc RE,r4 ;!/ 0000nnnn01110010 stc RE,<REG_N> /{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} stc RS,r4 ;!/ 0000nnnn01100010 stc RS,<REG_N> /{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} stc.l MOD,@-r4 ;!/ 0100nnnn01010011 stc.l MOD,@-<REG_N> /{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} stc.l RE,@-r4 ;!/ 0100nnnn01110011 stc.l RE,@-<REG_N> /{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} stc.l RS,@-r4 ;!/ 0100nnnn01100011 stc.l RS,@-<REG_N> /{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} sts DSR,r4 ;!/ 0000nnnn01101010 sts DSR,<REG_N> /{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} sts A0,r4 ;!/ 0000nnnn01111010 sts A0,<REG_N> /{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} sts X0,r4 ;!/ 0000nnnn10001010 sts X0,<REG_N> /{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} sts X1,r4 ;!/ 0000nnnn10011010 sts X1,<REG_N> /{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} sts Y0,r4 ;!/ 0000nnnn10101010 sts Y0,<REG_N> /{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} sts Y1,r4 ;!/ 0000nnnn10111010 sts Y1,<REG_N> /{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} sts.l DSR,@-r4 ;!/ 0100nnnn01100110 sts.l DSR,@-<REG_N> /{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} sts.l A0,@-r4 ;!/ 0100nnnn01110110 sts.l A0,@-<REG_N> /{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} sts.l X0,@-r4 ;!/ 0100nnnn10000110 sts.l X0,@-<REG_N> /{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} sts.l X1,@-r4 ;!/ 0100nnnn10010110 sts.l X1,@-<REG_N> /{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} sts.l Y0,@-r4 ;!/ 0100nnnn10100110 sts.l Y0,@-<REG_N> /{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} sts.l Y1,@-r4 ;!/ 0100nnnn10110110 sts.l Y1,@-<REG_N> /{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} movs.w @-r4,a1 ;!/ 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> / {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} movs.w @r4,a1 ;!/ 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> / {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} movs.w @r4+,a1 ;!/ 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> / {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} movs.w @r4+r8,a1 ;!/ 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> / {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} movs.w a1,@-r4 ;!/ 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> / {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} movs.w a1,@r4 ;!/ 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> / {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} movs.w a1,@r4+ ;!/ 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ / {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} movs.w a1,@r4+r8 ;!/ 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 / {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} movs.l @-r4,a1 ;!/ 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> / {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} movs.l @r4,a1 ;!/ 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> / {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} movs.l @r4+,a1 ;!/ 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> / {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} movs.l @r4+r8,a1 ;!/ 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> / {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} movs.l a1,@-r4 ;!/ 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> / {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} movs.l a1,@r4 ;!/ 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> / {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} movs.l a1,@r4+ ;!/ 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ / {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} movs.l a1,@r4+r8 ;!/ 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 / {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} nopx ;!/ 00000* nopx / {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} nopy ;!/ 00000 nopy / {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} movx.w @r4,x1 ;!/* nm001* movx.w @<REG_N>,<DSP_REG_X> / {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} movx.w @r4+,x1 ;!/ nm010* movx.w @<REG_N>+,<DSP_REG_X> / {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} movx.w @r4+r8,x1 ;!/ nm011* movx.w @<REG_N>+r8,<DSP_REG_X> / {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} movx.w a1,@r4 ;!/ nm101* movx.w <DSP_REG_M>,@<REG_N> / {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} movx.w a1,@r4+ ;!/ nm110* movx.w <DSP_REG_M>,@<REG_N>+ / {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} movx.w a1,@r4+r8 ;!/ nm111* movx.w <DSP_REG_M>,@<REG_N>+r8 / {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} movy.w @r6,y0 ;!/ nm001 movy.w @<REG_N>,<DSP_REG_Y> / {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} movy.w @r6+,y0 ;!/* nm010 movy.w @<REG_N>+,<DSP_REG_Y> / {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} movy.w @r6+r9,y0 ;!/* nm011 movy.w @<REG_N>+r9,<DSP_REG_Y> / {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} movy.w a1,@r6 ;!/* nm101 movy.w <DSP_REG_M>,@<REG_N> / {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} movy.w a1,@r6+ ;!/* nm110 movy.w <DSP_REG_M>,@<REG_N>+ / {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} movy.w a1,@r6+r9 ;!/* nm111 movy.w <DSP_REG_M>,@<REG_N>+r9 / {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg / {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} psubc x1,y0,m0 ;!/ 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} paddc x1,y0,m0 ;!/ 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} pcmp x1,y0 ;!/ 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> / {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} pwsb x1,y0,m0 ;!/ 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} pwad x1,y0,m0 ;!/ 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} pabs x1,m0 ;!/ 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> / {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} pabs y0,m0 ;!/ 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> / {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} prnd x1,m0 ;!/ 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> / {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} prnd y0,m0 ;!/ 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> / {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} dct pshl x1,y0,m0 ;!/ 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} pshl #4,m0 ;!/ 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> / {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} dct psha x1,y0,m0 ;!/ 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} psha #4,m0 ;!/ 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> / {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} dct psub x1,y0,m0 ;!/ 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} dct padd x1,y0,m0 ;!/ 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} dct pand x1,y0,m0 ;!/ 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} dct pxor x1,y0,m0 ;!/ 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} dct por x1,y0,m0 ;!/ 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> / {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} dct pdec x1,m0 ;!/ 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> / {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} dct pdec y0,m0 ;!/ 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> / {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} dct pinc x1,m0 ;!/ 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> / {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} dct pinc y0,m0 ;!/ 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> / {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} dct pclr m0 ;!/ 10001101xxyynnnn pclr <DSP_REG_N> / {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} dct pdmsb x1,m0 ;!/ 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> / {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} dct pdmsb y0,m0 ;!/ 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> / {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} dct pneg x1,m0 ;!/ 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> / {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} dct pneg y0,m0 ;!/ 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> / {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} dct pcopy x1,m0 ;!/ 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> / {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} dct pcopy y0,m0 ;!/ 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> / {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} dct psts MACH,m0 ;!/ 11001101xxyynnnn psts MACH,<DSP_REG_N> / {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} dct psts MACL,m0 ;!/ 11011101xxyynnnn psts MACL,<DSP_REG_N> / {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} dct plds m0,MACH ;!/ 11101101xxyynnnn plds <DSP_REG_N>,MACH / {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} dct plds m0,MACL ;!/ 11111101xxyynnnn plds <DSP_REG_N>,MACL / {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up} ! Instructions inherited from ancestors: sh sh2 add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	28,125	gas/testsuite/gas/sh/arch/sh3e.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3e but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3e: ! Instructions introduced into sh3e ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu add #4,r4 ;!/* 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/ 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsqrt fr1 ;!/ 1111nnnn01101101 fsqrt <F_REG_N> /{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
stsp/binutils-ia16	26,032	gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-or-sh3e but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_or_sh3e: ! Instructions introduced into sh2a-or-sh3e fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> /{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/ 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
stsp/binutils-ia16	18,809	gas/testsuite/gas/sh/arch/sh.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh: ! Instructions introduced into sh add #4,r4 ;!/* 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} ! Instructions inherited from ancestors:
stsp/binutils-ia16	22,870	gas/testsuite/gas/sh/arch/sh3.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3: ! Instructions introduced into sh3 ldtlb ;!/* 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	35,808	gas/testsuite/gas/sh/arch/sh4a.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4a but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4a: ! Instructions introduced into sh4a fpchg ;!/* 1111011111111101 fpchg /{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} icbi @r4 ;!/ 0000nnnn11100011 icbi @<REG_N> /{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/ 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/ 0000nnnn11000011 movca.l R0,@<REG_N> /{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movco.l r0,@r4 ;!/ 0000nnnn01110011 movco.l r0,@<REG_N> /{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} movli.l @r5,r0 ;!/ 0000mmmm01100011 movli.l @<REG_M>,r0 /{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} movua.l @r5,r0 ;!/ 0100mmmm10101001 movua.l @<REG_M>,r0 /{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} movua.l @r5+,r0 ;!/ 0100mmmm11101001 movua.l @<REG_M>+,r0 /{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/ 0000nnnn10010011 ocbi @<REG_N> /{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/ 0000nnnn10100011 ocbp @<REG_N> /{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/ 0000nnnn10110011 ocbwb @<REG_N> /{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} prefi @r4 ;!/ 0000nnnn11010011 prefi @<REG_N> /{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/ 0000nnnn00111010 stc SGR,<REG_N> /{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/ 0000nnnn11111010 stc DBR,<REG_N> /{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} synco ;!/ 0000000010101011 synco /{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fabs dr2 ;!/ 1111nnn001011101 fabs <D_REG_N> /{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fadd dr4,dr2 ;!/ 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/eq dr4,dr2 ;!/ 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fcmp/gt dr4,dr2 ;!/ 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/ 1111nnn010111101 fcnvds <D_REG_N>,FPUL/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/ 1111nnn010101101 fcnvsd FPUL,<D_REG_N>/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fdiv dr4,dr2 ;!/ 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} fipr fv4,fv0 ;!/ 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} float FPUL,dr2 ;!/ 1111nnn000101101 float FPUL,<D_REG_N>/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov xd4,xd2 ;!/ 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov xd4,@r4 ;!/ 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/ 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fmul dr4,dr2 ;!/ 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fneg dr2 ;!/ 1111nnn001001101 fneg <D_REG_N> /{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} frchg ;!/ 1111101111111101 frchg /{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up} fsca FPUL,dr2 ;!/ 1111nnn011111101 fsca FPUL,<D_REG_N> /{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up} fschg ;!/ 1111001111111101 fschg /{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt fr1 ;!/ 1111nnnn01101101 fsqrt <F_REG_N> /{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsqrt dr2 ;!/ 1111nnn001101101 fsqrt <D_REG_N> /{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsrra fr1 ;!/ 1111nnnn01111101 fsrra <F_REG_N> /{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} fsub dr4,dr2 ;!/ 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ftrc dr2,FPUL ;!/ 1111nnnn00111101 ftrc <D_REG_N>,FPUL/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} ftrv xmtrx,fv0 ;!/ 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
stsp/binutils-ia16	24,561	gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4-nommu-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4_nommu_nofpu: ! Instructions introduced into sh4-nommu-nofpu ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} movca.l R0,@r4 ;!/ 0000nnnn11000011 movca.l R0,@<REG_N> /{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} ocbi @r4 ;!/ 0000nnnn10010011 ocbi @<REG_N> /{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/ 0000nnnn10100011 ocbp @<REG_N> /{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/ 0000nnnn10110011 ocbwb @<REG_N> /{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} stc SGR,r4 ;!/ 0000nnnn00111010 stc SGR,<REG_N> /{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/ 0000nnnn11111010 stc DBR,<REG_N> /{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	24,687	gas/testsuite/gas/sh/arch/sh4-nofpu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4_nofpu: ! Instructions introduced into sh4-nofpu ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu add #4,r4 ;!/* 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/ 0000nnnn11000011 movca.l R0,@<REG_N> /{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/ 0000nnnn10010011 ocbi @<REG_N> /{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/ 0000nnnn10100011 ocbp @<REG_N> /{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/ 0000nnnn10110011 ocbwb @<REG_N> /{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/ 0000nnnn00111010 stc SGR,<REG_N> /{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/ 0000nnnn11111010 stc DBR,<REG_N> /{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	20,848	gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_nofpu_or_sh4_nommu_nofpu: ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu add #4,r4 ;!/* 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	34,684	gas/testsuite/gas/sh/arch/sh4.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4: ! Instructions introduced into sh4 fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up} frchg ;!/ 1111101111111101 frchg /{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up} fsca FPUL,dr2 ;!/ 1111nnn011111101 fsca FPUL,<D_REG_N> /{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up} fsrra fr1 ;!/ 1111nnnn01111101 fsrra <F_REG_N> /{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} ftrv xmtrx,fv0 ;!/ 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/ 0000000001001000 clrs /{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/ 0100nnnn01011010 lds <REG_N>,FPUL /{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/ 0100nnnn01101010 lds <REG_M>,FPSCR /{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/ 0100nnnn01010110 lds.l @<REG_M>+,FPUL/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/ 0100nnnn01100110 lds.l @<REG_M>+,FPSCR/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} ldtlb ;!/ 0000000000111000 ldtlb /{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/ 0000nnnn11000011 movca.l R0,@<REG_N> /{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/ 0000nnnn10010011 ocbi @<REG_N> /{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/ 0000nnnn10100011 ocbp @<REG_N> /{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/ 0000nnnn10110011 ocbwb @<REG_N> /{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/ 0000000001011000 sets /{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/ 0000nnnn00110010 stc SSR,<REG_N> /{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/ 0000nnnn01000010 stc SPC,<REG_N> /{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/ 0000nnnn00111010 stc SGR,<REG_N> /{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/ 0000nnnn11111010 stc DBR,<REG_N> /{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/ 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> /{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/ 0000nnnn01011010 sts FPUL,<REG_N> /{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/ 0000nnnn01101010 sts FPSCR,<REG_N> /{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/ 0100nnnn01010010 sts.l FPUL,@-<REG_N>/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/ 0100nnnn01100010 sts.l FPSCR,@-<REG_N>/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> /{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/ 1111nnnn01011101 fabs <F_REG_N> /{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fabs dr2 ;!/ 1111nnn001011101 fabs <D_REG_N> /{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd fr2,fr1 ;!/ 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fadd dr4,dr2 ;!/ 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq fr2,fr1 ;!/ 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/eq dr4,dr2 ;!/ 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt fr2,fr1 ;!/ 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fcmp/gt dr4,dr2 ;!/ 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/ 1111nnn010111101 fcnvds <D_REG_N>,FPUL/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/ 1111nnn010101101 fcnvsd FPUL,<D_REG_N>/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv fr2,fr1 ;!/ 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fdiv dr4,dr2 ;!/ 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} fldi0 fr1 ;!/ 1111nnnn10001101 fldi0 <F_REG_N> /{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/ 1111nnnn10011101 fldi1 <F_REG_N> /{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/ 1111nnnn00011101 flds <F_REG_N>,FPUL/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/ 1111nnnn00101101 float FPUL,<F_REG_N>/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} float FPUL,dr2 ;!/ 1111nnn000101101 float FPUL,<D_REG_N>/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmac FR0,fr2,fr1 ;!/ 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/ 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov xd4,xd2 ;!/ 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov xd4,@r4 ;!/ 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/ 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/ 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/ 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/ 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/ 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/ 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.s @r5,fr1 ;!/ 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/ 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/ 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/ 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/ 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/ 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/ 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fmul dr4,dr2 ;!/ 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg fr1 ;!/ 1111nnnn01001101 fneg <F_REG_N> /{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fneg dr2 ;!/ 1111nnn001001101 fneg <D_REG_N> /{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} fschg ;!/ 1111001111111101 fschg /{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt fr1 ;!/ 1111nnnn01101101 fsqrt <F_REG_N> /{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsqrt dr2 ;!/ 1111nnn001101101 fsqrt <D_REG_N> /{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsts FPUL,fr1 ;!/ 1111nnnn00001101 fsts FPUL,<F_REG_N>/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/ 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} fsub dr4,dr2 ;!/ 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc fr1,FPUL ;!/ 1111nnnn00111101 ftrc <F_REG_N>,FPUL/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ftrc dr2,FPUL ;!/ 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
stsp/binutils-ia16	20,806	gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-nofpu-or-sh3-nommu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_nofpu_or_sh3_nommu: ! Instructions introduced into sh2a-nofpu-or-sh3-nommu pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ! Instructions inherited from ancestors: sh sh2 add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	29,623	gas/testsuite/gas/sh/arch/sh2a-nofpu.s	! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h \| perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_nofpu: ! Instructions introduced into sh2a-nofpu ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR /{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} mov.b R0,@r4+ ;!/ 0100nnnn10001011 mov.b R0,@<REG_N>+ /{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} mov.b @-r5,R0 ;!/ 0100nnnn11001011 mov.b @-<REG_M>,R0 /{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} mov.b r5,@(2048,r4) ;!/ 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) / {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} mov.b @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> / {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up \| arch_op32} mov.l R0,@r4+ ;!/ 0100nnnn10101011 mov.l R0,@<REG_N>+ /{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} mov.l @-r5,R0 ;!/ 0100nnnn11001011 mov.l @-<REG_M>,R0 /{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} mov.l r5,@(2048,r4) ;!/ 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) / {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up \| arch_op32} mov.l @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> / {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up \| arch_op32} mov.w R0,@r4+ ;!/ 0100nnnn10011011 mov.w R0,@<REG_N>+ /{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} mov.w @-r5,R0 ;!/ 0100nnnn11011011 mov.w @-<REG_M>,R0 /{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} mov.w r5,@(2048,r4) ;!/ 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) / {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up \| arch_op32} mov.w @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> / {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up \| arch_op32} stc TBR,r4 ;!/ 0000nnnn01001010 stc TBR,<REG_N> / {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up} bclr #4, r4 ;!/ 10000110nnnn0iii bclr #<imm>, <REG_N> / {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bclr.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) / {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bld #4, r4 ;!/ 10000111nnnn1iii bld #<imm>, <REG_N> / {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bld.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) / {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bset #4, r4 ;!/ 10000110nnnn1iii bset #<imm>, <REG_N> / {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bset.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) / {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bst #4, r4 ;!/ 10000111nnnn0iii bst #<imm>, <REG_N> / {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bst.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) / {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} clips.b r4 ;!/ 0100nnnn10010001 clips.b <REG_N> / {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} clips.w r4 ;!/ 0100nnnn10010101 clips.w <REG_N> / {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up} clipu.b r4 ;!/ 0100nnnn10000001 clipu.b <REG_N> / {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up} clipu.w r4 ;!/ 0100nnnn10000101 clipu.w <REG_N> / {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up} divs R0,r4 ;!/ 0100nnnn10010100 divs R0,<REG_N> / {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up} divu R0,r4 ;!/ 0100nnnn10000100 divu R0,<REG_N> / {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up} jsr/n @r5 ;!/ 0100mmmm01001011 jsr/n @<REG_M> / {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up} jsr/n @@(8,TBR) ;!/ 10000011dddddddd jsr/n @@(<disp>,TBR) / {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up} ldbank @r5,R0 ;!/ 0100mmmm11100101 ldbank @<REG_M>,R0 / {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/ 0100mmmm11110001 movml.l <REG_M>,@-R15 / {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/ 0100mmmm11110101 movml.l @R15+,<REG_M> / {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/ 0100mmmm11110000 movml.l <REG_M>,@-R15 / {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/ 0100mmmm11110100 movml.l @R15+,<REG_M> / {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up} movrt r4 ;!/ 0000nnnn00111001 movrt <REG_N> / {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up} mulr R0,r4 ;!/ 0100nnnn10000000 mulr R0,<REG_N> / {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up} nott ;!/ 0000000001101000 nott / {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up} resbank ;!/ 0000000001011011 resbank / {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up} rts/n ;!/ 0000000001101011 rts/n / {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up} rtv/n r5 ;!/ 0000mmmm01111011 rtv/n <REG_M>/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up} stbank R0,@r4 ;!/ 0100nnnn11100001 stbank R0,@<REG_N>/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up} band.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) / {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bandnot.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bldnot.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) / {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bor.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) / {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bornot.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) / {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} bxor.b #4,@(2048,r4) ;!/ 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) / {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up \| arch_op32} movi20 #4,r4 ;!/ 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> / {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up \| arch_op32} movi20s #1024,r4 ;!/ 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> / {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up \| arch_op32} movu.b @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> / {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up \| arch_op32} movu.w @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> / {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up \| arch_op32} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu add #4,r4 ;!/ 0111nnnni81.... add #<imm>,<REG_N> /{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> /{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/ 0011nnnnmmmm1110 addc <REG_M>,<REG_N>/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/ 0011nnnnmmmm1111 addv <REG_M>,<REG_N>/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/ 11001001i81.... and #<imm>,R0 /{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> /{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/ 11001101i81.... and.b #<imm>,@(R0,GBR)/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> /{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/ 1011i12......... bsr <bdisp12> /{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/ 10001001i8p1.... bt <bdisp8> /{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/ 10001011i8p1.... bf <bdisp8> /{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/ 10001101i8p1.... bt.s <bdisp8> /{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/ 10001101i8p1.... bt/s <bdisp8> /{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/ 10001111i8p1.... bf.s <bdisp8> /{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/ 10001111i8p1.... bf/s <bdisp8> /{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/ 0000000000101000 clrmac /{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/ 0000000000001000 clrt /{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/ 10001000i81.... cmp/eq #<imm>,R0 /{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/ 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/ 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/ 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/ 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/ 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/ 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/ 0000000000011001 div0u /{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/ 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/ 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/ 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/ 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/ 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/ 0100nnnn00000111 ldc.l @<REG_N>+,SR /{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/ 0100nnnn00010111 ldc.l @<REG_N>+,GBR /{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/ 0100nnnn00100111 ldc.l @<REG_N>+,VBR /{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/ 0100nnnn00001010 lds <REG_N>,MACH /{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/ 0100nnnn00011010 lds <REG_N>,MACL /{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/ 0100nnnn00101010 lds <REG_N>,PR /{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/ 0100nnnn00000110 lds.l @<REG_N>+,MACH/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/ 0100nnnn00010110 lds.l @<REG_N>+,MACL/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/ 0100nnnn00100110 lds.l @<REG_N>+,PR /{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/ 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/ 1110nnnni81.... mov #<imm>,<REG_N> /{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> /{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/ 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/ 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/ 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/ 10000100mmmmi41 mov.b @(<disp>,<REG_M>),R0/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i81.... mov.b @(<disp>,GBR),R0/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/ 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/ 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/ 10000000mmmmi41 mov.b R0,@(<disp>,<REG_M>)/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i81.... mov.b R0,@(<disp>,GBR)/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi44 mov.l <REG_M>,@(<disp>,<REG_N>)/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/ 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/ 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/ 0101nnnnmmmmi44 mov.l @(<disp>,<REG_M>),<REG_N>/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i84.... mov.l @(<disp>,GBR),R0/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/ 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/ 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/ 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/ 11000010i84.... mov.l R0,@(<disp>,GBR)/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/ 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/ 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/ 10000101mmmmi42 mov.w @(<disp>,<REG_M>),R0/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i82.... mov.w @(<disp>,GBR),R0/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/ 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/ 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/ 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/ 10000001mmmmi42 mov.w R0,@(<disp>,<REG_M>)/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i82.... mov.w R0,@(<disp>,GBR)/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/ 0000nnnn00101001 movt <REG_N> /{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/ 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/ 0010nnnnmmmm1111 muls <REG_M>,<REG_N>/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/ 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/ 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/ 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/ 0110nnnnmmmm1011 neg <REG_M>,<REG_N> /{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/ 0110nnnnmmmm1010 negc <REG_M>,<REG_N>/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/ 0000000000001001 nop /{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/ 0110nnnnmmmm0111 not <REG_M>,<REG_N> /{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/ 11001011i81.... or #<imm>,R0 /{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> /{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/ 11001111i81.... or.b #<imm>,@(R0,GBR)/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> /{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/ 0100nnnn00100100 rotcl <REG_N> /{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/ 0100nnnn00100101 rotcr <REG_N> /{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/ 0100nnnn00000100 rotl <REG_N> /{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/ 0100nnnn00000101 rotr <REG_N> /{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/ 0000000000101011 rte /{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/ 0000000000001011 rts /{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/ 0000000000011000 sett /{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/ 0100nnnnmmmm1100 shad <REG_M>,<REG_N>/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/ 0100nnnnmmmm1101 shld <REG_M>,<REG_N>/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/ 0100nnnn00100000 shal <REG_N> /{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/ 0100nnnn00100001 shar <REG_N> /{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/ 0100nnnn00000000 shll <REG_N> /{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/ 0100nnnn00101000 shll16 <REG_N> /{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/ 0100nnnn00001000 shll2 <REG_N> /{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/ 0100nnnn00011000 shll8 <REG_N> /{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/ 0100nnnn00000001 shlr <REG_N> /{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/ 0100nnnn00101001 shlr16 <REG_N> /{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/ 0100nnnn00001001 shlr2 <REG_N> /{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/ 0100nnnn00011001 shlr8 <REG_N> /{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/ 0000000000011011 sleep /{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/ 0000nnnn00000010 stc SR,<REG_N> /{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/ 0000nnnn00010010 stc GBR,<REG_N> /{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/ 0000nnnn00100010 stc VBR,<REG_N> /{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/ 0100nnnn00000011 stc.l SR,@-<REG_N> /{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/ 0100nnnn00100011 stc.l VBR,@-<REG_N> /{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/ 0100nnnn00010011 stc.l GBR,@-<REG_N> /{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/ 0000nnnn00001010 sts MACH,<REG_N> /{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/ 0000nnnn00011010 sts MACL,<REG_N> /{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/ 0000nnnn00101010 sts PR,<REG_N> /{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/ 0100nnnn00000010 sts.l MACH,@-<REG_N>/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/ 0100nnnn00010010 sts.l MACL,@-<REG_N>/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/ 0100nnnn00100010 sts.l PR,@-<REG_N> /{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/ 0011nnnnmmmm1000 sub <REG_M>,<REG_N> /{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/ 0011nnnnmmmm1010 subc <REG_M>,<REG_N>/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/ 0011nnnnmmmm1011 subv <REG_M>,<REG_N>/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/ 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/ 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/ 0100nnnn00011011 tas.b @<REG_N> /{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/ 11000011i81.... trapa #<imm> /{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i81.... tst #<imm>,R0 /{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> /{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/ 11001100i81.... tst.b #<imm>,@(R0,GBR)/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i81.... xor #<imm>,R0 /{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> /{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/ 11001110i81.... xor.b #<imm>,@(R0,GBR)/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/ 0100nnnn00010000 dt <REG_N> /{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/ 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/ 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/ 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/ 0000nnnn00100011 braf <REG_N> /{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/ 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
stsp/binutils-ia16	2,882	gas/testsuite/gas/hppa/reloc/funcrelocbug.s	.code .align 4 .EXPORT g,CODE .EXPORT g,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR g: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) copy %r3,%r1 copy %r30,%r3 stwm %r1,128(%r30) stw %r26,-36(%r3) stw %r25,-40(%r3) stw %r24,-44(%r3) ldw -36(%r3),%r26 ldw -40(%r3),%r25 ldw -44(%r3),%r19 copy %r19,%r22 .CALL ARGW0=GR bl $$dyncall,%r31 copy %r31,%r2 copy %r28,%r19 comiclr,<> 0,%r19,%r0 bl,n L$0002,%r0 ldw -36(%r3),%r28 bl,n L$0001,%r0 bl,n L$0003,%r0 L$0002: ldw -40(%r3),%r28 bl,n L$0001,%r0 L$0003: L$0001: ldw -20(%r3),%r2 ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND .align 4 f2___4: .PROC .CALLINFO FRAME=64,NO_CALLS,SAVE_SP,ENTRY_GR=3 .ENTRY copy %r3,%r1 copy %r30,%r3 stwm %r1,64(%r30) stw %r29,8(%r3) stw %r26,-36(%r3) stw %r25,-40(%r3) ldw -36(%r3),%r19 ldw -40(%r3),%r20 comclr,>= %r20,%r19,%r19 ldi 1,%r19 copy %r19,%r28 bl,n L$0005,%r0 L$0005: ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND .IMPORT abort,CODE .data .align 4 L$TRAMP0000: ldw 36(%r22),%r21 bb,>=,n %r21,30,.+16 depi 0,31,2,%r21 ldw 4(%r21),%r19 ldw 0(%r21),%r21 ldsid (%r21),%r1 mtsp %r1,%sr0 be 0(%sr0,%r21) ldw 40(%r22),%r29 .word 0 .word 0 .code .align 4 .EXPORT f,CODE .EXPORT f,ENTRY,PRIV_LEV=3,RTNVAL=GR f: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) copy %r3,%r1 copy %r30,%r3 stwm %r1,192(%r30) ldo 16(%r3),%r19 addil L'L$TRAMP0000-$global$,%r27 ldo R'L$TRAMP0000-$global$(%r1),%r22 ldo 40(%r0),%r20 ldws,ma 4(%r22),%r21 addib,>= -4,%r20,.-4 stws,ma %r21,4(%r19) ldil L'f2___4,%r20 ldo R'f2___4(%r20),%r19 stw %r19,52(%r3) ldo 8(%r3),%r19 stw %r19,56(%r3) ldo 16(%r3),%r19 ldo 48(%r3),%r20 fdc %r0(%r19) fdc %r0(%r20) sync ldo 32(%r19),%r22 mfsp %sr0,%r21 ldsid (%r19),%r20 mtsp %r20,%sr0 fic %r0(%sr0,%r19) fic %r0(%sr0,%r22) sync mtsp %r21,%sr0 nop nop nop nop nop nop ldo 16(%r3),%r19 ldi 1,%r26 ldi 2,%r25 copy %r19,%r24 .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl g,%r2 nop copy %r28,%r19 comiclr,<> 2,%r19,%r0 bl,n L$0006,%r0 .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl abort,%r2 nop L$0006: L$0004: ldw -20(%r3),%r2 ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND .IMPORT __main,CODE .IMPORT exit,CODE .align 4 .EXPORT main,CODE .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR main: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) copy %r3,%r1 copy %r30,%r3 stwm %r1,128(%r30) .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl __main,%r2 nop .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl f,%r2 nop copy %r0,%r26 .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl exit,%r2 nop L$0007: ldw -20(%r3),%r2 ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND
stsp/binutils-ia16	1,247	gas/testsuite/gas/hppa/reloc/reduce2.s	.SPACE $PRIVATE$ .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 .SPACE $TEXT$ .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY .IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE ; gcc_compiled.: .SPACE $TEXT$ .SUBSPA $LIT$ .align 8 L$P0000 .word 0x12345678 .word 0x0 .align 8 L$C0000 .word 0x3ff00000 .word 0x0 .SPACE $TEXT$ .SUBSPA $CODE$ .align 4 .EXPORT g,ENTRY,PRIV_LEV=3,RTNVAL=FR g .PROC .CALLINFO FRAME=0,NO_CALLS .ENTRY stw %r19,-32(%r30) ldw T'L$C0000(%r19),%r20 bv %r0(%r2) fldds 0(%r20),%fr4 .EXIT .PROCEND .IMPORT abort,CODE .IMPORT exit,CODE .SPACE $TEXT$ .SUBSPA $LIT$ .align 8 L$C0001 .word 0x3ff00000 .word 0x0 .SPACE $TEXT$ .SUBSPA $CODE$ .align 4 .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR main .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) ldo 128(%r30),%r30 stw %r19,-32(%r30) stw %r4,-128(%r30) copy %r19,%r4 .CALL bl g,%r2 copy %r4,%r19 copy %r4,%r19 ldw T'L$C0001(%r19),%r20 fldds 0(%r20),%fr8 fcmp,dbl,= %fr4,%fr8 ftest add,tr %r0,%r0,%r0 b,n L$0003 .CALL bl abort,%r2 nop L$0003 .CALL ARGW0=GR bl exit,%r2 ldi 0,%r26 nop .EXIT .PROCEND
stsp/binutils-ia16	2,026	gas/testsuite/gas/hppa/reloc/applybug.s	.IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE ; gcc_compiled.: .data .align 4 tab___2: .word L$0002 .word L$0003 .word L$0004 .code .align 4 .EXPORT execute,CODE .EXPORT execute,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR execute: .PROC .CALLINFO FRAME=0,NO_CALLS .ENTRY addil L'buf-$global$,%r27 ldo R'buf-$global$(%r1),%r20 ldil L'L$0002,%r19 movb,<> %r26,%r26,L$0002 ldo R'L$0002(%r19),%r22 copy %r0,%r21 addil L'tab___2-$global$,%r27 ldo R'tab___2-$global$(%r1),%r23 addil L'optab-$global$,%r27 ldo R'optab-$global$(%r1),%r20 L$0009: sh2add %r21,%r23,%r19 ldh 2(%r19),%r19 ldo 1(%r21),%r21 sub %r19,%r22,%r19 comib,>= 2,%r21,L$0009 sths,ma %r19,2(%r20) bv,n %r0(%r2) L$0002: ldi 120,%r19 stbs,ma %r19,1(%r20) ldhs,ma 2(%r26),%r19 add %r22,%r19,%r19 bv,n %r0(%r19) L$0003: ldi 121,%r19 stbs,ma %r19,1(%r20) ldhs,ma 2(%r26),%r19 add %r22,%r19,%r19 bv,n %r0(%r19) L$0004: ldi 122,%r19 stb %r19,0(%r20) bv %r0(%r2) stbs,mb %r0,1(%r20) .EXIT .PROCEND .IMPORT __main,CODE .IMPORT strcmp,CODE .align 4 L$C0000: .STRING "xyxyz\x00" .IMPORT abort,CODE .IMPORT exit,CODE .code .align 4 .EXPORT main,CODE .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR main: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) .CALL bl __main,%r2 ldo 128(%r30),%r30 .CALL ARGW0=GR bl execute,%r2 copy %r0,%r26 addil L'optab-$global$,%r27 copy %r1,%r19 ldo R'optab-$global$(%r19),%r21 ldh 2(%r21),%r20 ldh R'optab-$global$(%r19),%r19 addil L'p-$global$,%r27 copy %r1,%r22 sth %r20,R'p-$global$(%r22) ldo R'p-$global$(%r22),%r26 sth %r20,4(%r26) sth %r19,2(%r26) ldh 4(%r21),%r19 .CALL ARGW0=GR bl execute,%r2 sth %r19,6(%r26) addil L'buf-$global$,%r27 copy %r1,%r19 ldo R'buf-$global$(%r19),%r26 ldil L'L$C0000,%r25 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ldo R'L$C0000(%r25),%r25 comib,=,n 0,%r28,L$0011 .CALL bl abort,%r2 nop L$0011: .CALL ARGW0=GR bl exit,%r2 copy %r0,%r26 nop .EXIT .PROCEND .data optab: .comm 10 buf: .comm 10 p: .comm 10
stsp/binutils-ia16	106,210	gas/testsuite/gas/hppa/unsorted/brlenbug.s	.IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE ; gcc_compiled.: .data .align 4 done___2 .word 0 .IMPORT memset,CODE .EXPORT re_syntax_options,DATA .align 4 re_syntax_options .word 0 .align 4 re_error_msg .word 0 .word L$C0000 .word L$C0001 .word L$C0002 .word L$C0003 .word L$C0004 .word L$C0005 .word L$C0006 .word L$C0007 .word L$C0008 .word L$C0009 .word L$C0010 .word L$C0011 .word L$C0012 .word L$C0013 .word L$C0014 .word L$C0015 .code .align 4 L$C0015 .STRING "Unmatched ) or \\)\x00" .align 4 L$C0014 .STRING "Regular expression too big\x00" .align 4 L$C0013 .STRING "Premature end of regular expression\x00" .align 4 L$C0012 .STRING "Invalid preceding regular expression\x00" .align 4 L$C0011 .STRING "Memory exhausted\x00" .align 4 L$C0010 .STRING "Invalid range end\x00" .align 4 L$C0009 .STRING "Invalid content of \\{\\}\x00" .align 4 L$C0008 .STRING "Unmatched \\{\x00" .align 4 L$C0007 .STRING "Unmatched ( or \\(\x00" .align 4 L$C0006 .STRING "Unmatched [ or [^\x00" .align 4 L$C0005 .STRING "Invalid back reference\x00" .align 4 L$C0004 .STRING "Trailing backslash\x00" .align 4 L$C0003 .STRING "Invalid character class name\x00" .align 4 L$C0002 .STRING "Invalid collation character\x00" .align 4 L$C0001 .STRING "Invalid regular expression\x00" .align 4 L$C0000 .STRING "No match\x00" .EXPORT re_max_failures,DATA .data .align 4 re_max_failures .word 2000 .IMPORT malloc,CODE .IMPORT realloc,CODE .IMPORT free,CODE .IMPORT strcmp,CODE .code .align 4 L$C0016 .STRING "alnum\x00" .align 4 L$C0017 .STRING "alpha\x00" .align 4 L$C0018 .STRING "blank\x00" .align 4 L$C0019 .STRING "cntrl\x00" .align 4 L$C0020 .STRING "digit\x00" .align 4 L$C0021 .STRING "graph\x00" .align 4 L$C0022 .STRING "lower\x00" .align 4 L$C0023 .STRING "print\x00" .align 4 L$C0024 .STRING "punct\x00" .align 4 L$C0025 .STRING "space\x00" .align 4 L$C0026 .STRING "upper\x00" .align 4 L$C0027 .STRING "xdigit\x00" .IMPORT __alnum,DATA .IMPORT __ctype2,DATA .IMPORT __ctype,DATA .IMPORT at_begline_loc_p,CODE .IMPORT at_endline_loc_p,CODE .IMPORT store_op1,CODE .IMPORT insert_op1,CODE .IMPORT store_op2,CODE .IMPORT insert_op2,CODE .IMPORT compile_range,CODE .IMPORT group_in_compile_stack,CODE .code .align 4 regex_compile .PROC .CALLINFO FRAME=320,CALLS,SAVE_RP,ENTRY_GR=18 .ENTRY stw %r2,-20(%r30) ;# 8989 reload_outsi+2/6 ldo 320(%r30),%r30 ;# 8991 addsi3/2 stw %r18,-168(%r30) ;# 8993 reload_outsi+2/6 stw %r17,-164(%r30) ;# 8995 reload_outsi+2/6 stw %r16,-160(%r30) ;# 8997 reload_outsi+2/6 stw %r15,-156(%r30) ;# 8999 reload_outsi+2/6 stw %r14,-152(%r30) ;# 9001 reload_outsi+2/6 stw %r13,-148(%r30) ;# 9003 reload_outsi+2/6 stw %r12,-144(%r30) ;# 9005 reload_outsi+2/6 stw %r11,-140(%r30) ;# 9007 reload_outsi+2/6 stw %r10,-136(%r30) ;# 9009 reload_outsi+2/6 stw %r9,-132(%r30) ;# 9011 reload_outsi+2/6 stw %r8,-128(%r30) ;# 9013 reload_outsi+2/6 stw %r7,-124(%r30) ;# 9015 reload_outsi+2/6 stw %r6,-120(%r30) ;# 9017 reload_outsi+2/6 stw %r5,-116(%r30) ;# 9019 reload_outsi+2/6 stw %r4,-112(%r30) ;# 9021 reload_outsi+2/6 stw %r3,-108(%r30) ;# 9023 reload_outsi+2/6 stw %r26,-276(%r30) ;# 4 reload_outsi+2/6 ldi 0,%r9 ;# 25 reload_outsi+2/2 ldi 0,%r8 ;# 28 reload_outsi+2/2 stw %r0,-260(%r30) ;# 34 reload_outsi+2/6 ldi 0,%r10 ;# 31 reload_outsi+2/2 ldi 640,%r26 ;# 37 reload_outsi+2/2 ldw -276(%r30),%r1 ;# 8774 reload_outsi+2/5 copy %r24,%r15 ;# 8 reload_outsi+2/1 stw %r1,-296(%r30) ;# 2325 reload_outsi+2/6 copy %r23,%r5 ;# 10 reload_outsi+2/1 addl %r1,%r25,%r16 ;# 19 addsi3/1 .CALL ARGW0=GR bl malloc,%r2 ;# 39 call_value_internal_symref ldw 20(%r5),%r14 ;# 22 reload_outsi+2/5 comib,<> 0,%r28,L$0021 ;# 48 bleu+1 stw %r28,-312(%r30) ;# 43 reload_outsi+2/6 L$0953 bl L$0867,%r0 ;# 53 jump ldi 12,%r28 ;# 51 reload_outsi+2/2 L$0021 ldi 32,%r19 ;# 58 reload_outsi+2/2 stw %r19,-308(%r30) ;# 59 reload_outsi+2/6 stw %r0,-304(%r30) ;# 62 reload_outsi+2/6 stw %r15,12(%r5) ;# 65 reload_outsi+2/6 stw %r0,8(%r5) ;# 85 reload_outsi+2/6 stw %r0,24(%r5) ;# 88 reload_outsi+2/6 addil LR'done___2-$global$,%r27 ;# 92 pic2_lo_sum+1 ldw 28(%r5),%r19 ;# 68 reload_outsi+2/5 ldw RR'done___2-$global$(%r1),%r20 ;# 94 reload_outsi+2/5 depi 0,3,1,%r19 ;# 69 andsi3/2 depi 0,6,2,%r19 ;# 80 andsi3/2 comib,<> 0,%r20,L$0022 ;# 95 bleu+1 stw %r19,28(%r5) ;# 82 reload_outsi+2/6 addil LR're_syntax_table-$global$,%r27 ;# 99 pic2_lo_sum+1 ldo RR're_syntax_table-$global$(%r1),%r4 ;# 100 movhi-2 copy %r4,%r26 ;# 101 reload_outsi+2/1 ldi 0,%r25 ;# 102 reload_outsi+2/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 ;# 104 call_value_internal_symref ldi 256,%r24 ;# 103 reload_outsi+2/2 ldi 1,%r20 ;# 8732 movqi+1/2 ldo 97(%r4),%r19 ;# 8736 addsi3/2 ldo 122(%r4),%r4 ;# 8738 addsi3/2 stbs,ma %r20,1(%r19) ;# 115 movqi+1/6 L$1155 comb,>=,n %r4,%r19,L$1155 ;# 121 bleu+1 stbs,ma %r20,1(%r19) ;# 115 movqi+1/6 ldi 1,%r21 ;# 8717 movqi+1/2 addil LR're_syntax_table-$global$,%r27 ;# 8712 pic2_lo_sum+1 ldo RR're_syntax_table-$global$(%r1),%r19 ;# 8715 movhi-2 ldo 65(%r19),%r20 ;# 8721 addsi3/2 ldo 90(%r19),%r19 ;# 8723 addsi3/2 stbs,ma %r21,1(%r20) ;# 138 movqi+1/6 L$1156 comb,>=,n %r19,%r20,L$1156 ;# 144 bleu+1 stbs,ma %r21,1(%r20) ;# 138 movqi+1/6 ldi 48,%r20 ;# 151 reload_outsi+2/2 ldi 57,%r22 ;# 7976 reload_outsi+2/2 ldi 1,%r21 ;# 8707 movqi+1/2 addil LR're_syntax_table-$global$+48,%r27 ;# 8705 pic2_lo_sum+1 ldo RR're_syntax_table-$global$+48(%r1),%r19 ;# 8711 movhi-2 L$0037 ldo 1(%r20),%r20 ;# 164 addsi3/2 comb,>= %r22,%r20,L$0037 ;# 167 bleu+1 stbs,ma %r21,1(%r19) ;# 161 movqi+1/6 addil LR're_syntax_table-$global$,%r27 ;# 174 pic2_lo_sum+1 ldo RR're_syntax_table-$global$(%r1),%r19 ;# 175 movhi-2 ldi 1,%r20 ;# 176 movqi+1/2 stb %r20,95(%r19) ;# 177 movqi+1/6 addil LR'done___2-$global$,%r27 ;# 178 pic2_lo_sum+1 ldi 1,%r19 ;# 180 reload_outsi+2/2 stw %r19,RR'done___2-$global$(%r1) ;# 181 reload_outsi+2/6 L$0022 ldw 4(%r5),%r19 ;# 187 reload_outsi+2/5 comib,<>,n 0,%r19,L$0039 ;# 189 bleu+1 ldw 0(%r5),%r26 ;# 193 reload_outsi+2/5 comib,=,n 0,%r26,L$0040 ;# 195 bleu+1 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 205 call_value_internal_symref ldi 32,%r25 ;# 203 reload_outsi+2/2 bl L$1157,%r0 ;# 211 jump stw %r28,0(%r5) ;# 223 reload_outsi+2/6 L$0040 .CALL ARGW0=GR bl malloc,%r2 ;# 219 call_value_internal_symref ldi 32,%r26 ;# 217 reload_outsi+2/2 stw %r28,0(%r5) ;# 223 reload_outsi+2/6 L$1157 ldw 0(%r5),%r19 ;# 228 reload_outsi+2/5 comib,<> 0,%r19,L$0042 ;# 230 bleu+1 ldi 32,%r19 ;# 243 reload_outsi+2/2 .CALL ARGW0=GR bl free,%r2 ;# 234 call_internal_symref ldw -312(%r30),%r26 ;# 232 reload_outsi+2/5 bl L$0867,%r0 ;# 238 jump ldi 12,%r28 ;# 51 reload_outsi+2/2 L$0042 stw %r19,4(%r5) ;# 244 reload_outsi+2/6 L$0039 ldw 0(%r5),%r6 ;# 249 reload_outsi+2/5 ldw -296(%r30),%r19 ;# 7981 reload_outsi+2/5 comclr,<> %r16,%r19,%r0 ;# 7982 bleu+1 bl L$0044,%r0 copy %r6,%r12 ;# 253 reload_outsi+2/1 ldw -296(%r30),%r19 ;# 2334 reload_outsi+2/5 L$1178 ldbs,ma 1(%r19),%r7 ;# 277 zero_extendqisi2/2 comib,= 0,%r14,L$0047 ;# 282 bleu+1 stw %r19,-296(%r30) ;# 2337 reload_outsi+2/6 addl %r14,%r7,%r19 ;# 283 addsi3/1 ldb 0(%r19),%r7 ;# 286 zero_extendqisi2/2 L$0047 ldo -10(%r7),%r19 ;# 7895 addsi3/2 addi,uv -115,%r19,%r0 ;# 7896 casesi0 blr,n %r19,%r0 b,n L$0076 L$0863 bl L$0376,%r0 nop ;# 9092 switch_jump L$0954 bl L$0076,%r0 nop ;# 9095 switch_jump L$0955 bl L$0076,%r0 nop ;# 9098 switch_jump L$0956 bl L$0076,%r0 nop ;# 9101 switch_jump L$0957 bl L$0076,%r0 nop ;# 9104 switch_jump L$0958 bl L$0076,%r0 nop ;# 9107 switch_jump L$0959 bl L$0076,%r0 nop ;# 9110 switch_jump L$0960 bl L$0076,%r0 nop ;# 9113 switch_jump L$0961 bl L$0076,%r0 nop ;# 9116 switch_jump L$0962 bl L$0076,%r0 nop ;# 9119 switch_jump L$0963 bl L$0076,%r0 nop ;# 9122 switch_jump L$0964 bl L$0076,%r0 nop ;# 9125 switch_jump L$0965 bl L$0076,%r0 nop ;# 9128 switch_jump L$0966 bl L$0076,%r0 nop ;# 9131 switch_jump L$0967 bl L$0076,%r0 nop ;# 9134 switch_jump L$0968 bl L$0076,%r0 nop ;# 9137 switch_jump L$0969 bl L$0076,%r0 nop ;# 9140 switch_jump L$0970 bl L$0076,%r0 nop ;# 9143 switch_jump L$0971 bl L$0076,%r0 nop ;# 9146 switch_jump L$0972 bl L$0076,%r0 nop ;# 9149 switch_jump L$0973 bl L$0076,%r0 nop ;# 9152 switch_jump L$0974 bl L$0076,%r0 nop ;# 9155 switch_jump L$0975 bl L$0076,%r0 nop ;# 9158 switch_jump L$0976 bl L$0076,%r0 nop ;# 9161 switch_jump L$0977 bl L$0076,%r0 nop ;# 9164 switch_jump L$0978 bl L$0076,%r0 nop ;# 9167 switch_jump L$0979 bl L$0077,%r0 ;# 9170 switch_jump ldw -296(%r30),%r26 ;# 2349 reload_outsi+2/5 L$0980 bl L$0076,%r0 nop ;# 9173 switch_jump L$0981 bl L$0076,%r0 nop ;# 9176 switch_jump L$0982 bl L$0076,%r0 nop ;# 9179 switch_jump L$0983 bl L$0368,%r0 nop ;# 9182 switch_jump L$0984 bl L$0372,%r0 nop ;# 9185 switch_jump L$0985 bl L$0104,%r0 nop ;# 9188 switch_jump L$0986 bl L$1158,%r0 ;# 9191 switch_jump ldi 1026,%r19 ;# 662 reload_outsi+2/2 L$0987 bl L$0076,%r0 nop ;# 9194 switch_jump L$0988 bl L$0076,%r0 nop ;# 9197 switch_jump L$0989 bl L$0196,%r0 ;# 9200 switch_jump ldw 0(%r5),%r4 ;# 8027 reload_outsi+2/5 L$0990 bl L$0076,%r0 nop ;# 9203 switch_jump L$0991 bl L$0076,%r0 nop ;# 9206 switch_jump L$0992 bl L$0076,%r0 nop ;# 9209 switch_jump L$0993 bl L$0076,%r0 nop ;# 9212 switch_jump L$0994 bl L$0076,%r0 nop ;# 9215 switch_jump L$0995 bl L$0076,%r0 nop ;# 9218 switch_jump L$0996 bl L$0076,%r0 nop ;# 9221 switch_jump L$0997 bl L$0076,%r0 nop ;# 9224 switch_jump L$0998 bl L$0076,%r0 nop ;# 9227 switch_jump L$0999 bl L$0076,%r0 nop ;# 9230 switch_jump L$1000 bl L$0076,%r0 nop ;# 9233 switch_jump L$1001 bl L$0076,%r0 nop ;# 9236 switch_jump L$1002 bl L$0076,%r0 nop ;# 9239 switch_jump L$1003 bl L$0076,%r0 nop ;# 9242 switch_jump L$1004 bl L$0076,%r0 nop ;# 9245 switch_jump L$1005 bl L$0076,%r0 nop ;# 9248 switch_jump L$1006 bl L$0101,%r0 ;# 9251 switch_jump ldi 1026,%r19 ;# 662 reload_outsi+2/2 L$1007 bl L$0076,%r0 nop ;# 9254 switch_jump L$1008 bl L$0076,%r0 nop ;# 9257 switch_jump L$1009 bl L$0076,%r0 nop ;# 9260 switch_jump L$1010 bl L$0076,%r0 nop ;# 9263 switch_jump L$1011 bl L$0076,%r0 nop ;# 9266 switch_jump L$1012 bl L$0076,%r0 nop ;# 9269 switch_jump L$1013 bl L$0076,%r0 nop ;# 9272 switch_jump L$1014 bl L$0076,%r0 nop ;# 9275 switch_jump L$1015 bl L$0076,%r0 nop ;# 9278 switch_jump L$1016 bl L$0076,%r0 nop ;# 9281 switch_jump L$1017 bl L$0076,%r0 nop ;# 9284 switch_jump L$1018 bl L$0076,%r0 nop ;# 9287 switch_jump L$1019 bl L$0076,%r0 nop ;# 9290 switch_jump L$1020 bl L$0076,%r0 nop ;# 9293 switch_jump L$1021 bl L$0076,%r0 nop ;# 9296 switch_jump L$1022 bl L$0076,%r0 nop ;# 9299 switch_jump L$1023 bl L$0076,%r0 nop ;# 9302 switch_jump L$1024 bl L$0076,%r0 nop ;# 9305 switch_jump L$1025 bl L$0076,%r0 nop ;# 9308 switch_jump L$1026 bl L$0076,%r0 nop ;# 9311 switch_jump L$1027 bl L$0076,%r0 nop ;# 9314 switch_jump L$1028 bl L$0076,%r0 nop ;# 9317 switch_jump L$1029 bl L$0076,%r0 nop ;# 9320 switch_jump L$1030 bl L$0076,%r0 nop ;# 9323 switch_jump L$1031 bl L$0076,%r0 nop ;# 9326 switch_jump L$1032 bl L$0076,%r0 nop ;# 9329 switch_jump L$1033 bl L$0076,%r0 nop ;# 9332 switch_jump L$1034 bl L$0216,%r0 ;# 9335 switch_jump ldw -296(%r30),%r19 ;# 2418 reload_outsi+2/5 L$1035 bl L$0387,%r0 ;# 9338 switch_jump ldw -296(%r30),%r19 ;# 3797 reload_outsi+2/5 L$1036 bl L$0076,%r0 nop ;# 9341 switch_jump L$1037 bl L$0053,%r0 ;# 9344 switch_jump ldw -276(%r30),%r1 ;# 8777 reload_outsi+2/5 L$1038 bl L$0076,%r0 nop ;# 9347 switch_jump L$1039 bl L$0076,%r0 nop ;# 9350 switch_jump L$1040 bl L$0076,%r0 nop ;# 9353 switch_jump L$1041 bl L$0076,%r0 nop ;# 9356 switch_jump L$1042 bl L$0076,%r0 nop ;# 9359 switch_jump L$1043 bl L$0076,%r0 nop ;# 9362 switch_jump L$1044 bl L$0076,%r0 nop ;# 9365 switch_jump L$1045 bl L$0076,%r0 nop ;# 9368 switch_jump L$1046 bl L$0076,%r0 nop ;# 9371 switch_jump L$1047 bl L$0076,%r0 nop ;# 9374 switch_jump L$1048 bl L$0076,%r0 nop ;# 9377 switch_jump L$1049 bl L$0076,%r0 nop ;# 9380 switch_jump L$1050 bl L$0076,%r0 nop ;# 9383 switch_jump L$1051 bl L$0076,%r0 nop ;# 9386 switch_jump L$1052 bl L$0076,%r0 nop ;# 9389 switch_jump L$1053 bl L$0076,%r0 nop ;# 9392 switch_jump L$1054 bl L$0076,%r0 nop ;# 9395 switch_jump L$1055 bl L$0076,%r0 nop ;# 9398 switch_jump L$1056 bl L$0076,%r0 nop ;# 9401 switch_jump L$1057 bl L$0076,%r0 nop ;# 9404 switch_jump L$1058 bl L$0076,%r0 nop ;# 9407 switch_jump L$1059 bl L$0076,%r0 nop ;# 9410 switch_jump L$1060 bl L$0076,%r0 nop ;# 9413 switch_jump L$1061 bl L$0076,%r0 nop ;# 9416 switch_jump L$1062 bl L$0076,%r0 nop ;# 9419 switch_jump L$1063 bl L$0076,%r0 nop ;# 9422 switch_jump L$1064 bl L$0076,%r0 nop ;# 9425 switch_jump L$1065 bl L$0076,%r0 nop ;# 9428 switch_jump L$1066 bl L$0383,%r0 ;# 9431 switch_jump ldi 4608,%r20 ;# 3778 reload_outsi+2/2 L$1067 bl L$0380,%r0 nop ;# 9434 switch_jump L$1068 bl,n L$0076,%r0 ;# 7899 jump L$0053 ldw -296(%r30),%r25 ;# 2343 reload_outsi+2/5 ldo 1(%r1),%r19 ;# 306 addsi3/2 comb,=,n %r19,%r25,L$0055 ;# 308 bleu+1 bb,< %r15,28,L$0055 ;# 313 bleu+3 ldw -276(%r30),%r26 ;# 315 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl at_begline_loc_p,%r2 ;# 321 call_value_internal_symref copy %r15,%r24 ;# 319 reload_outsi+2/1 extrs %r28,31,8,%r28 ;# 324 extendqisi2 comiclr,<> 0,%r28,%r0 ;# 326 bleu+1 bl,n L$0076,%r0 L$0055 ldw 0(%r5),%r4 ;# 7986 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7989 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7987 subsi3/1 ldo 1(%r19),%r19 ;# 7988 addsi3/2 comb,>>=,n %r20,%r19,L$0060 ;# 7990 bleu+1 ldil L'65536,%r3 ;# 8701 reload_outsi+2/3 L$0061 comclr,<> %r3,%r20,%r0 ;# 357 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 367 ashlsi3+1 comb,>>= %r3,%r19,L$0066 ;# 375 bleu+1 stw %r19,4(%r5) ;# 369 reload_outsi+2/6 stw %r3,4(%r5) ;# 378 reload_outsi+2/6 L$0066 ldw 0(%r5),%r26 ;# 385 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 389 call_value_internal_symref ldw 4(%r5),%r25 ;# 387 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 397 bleu+1 stw %r28,0(%r5) ;# 393 reload_outsi+2/6 comb,= %r28,%r4,L$0059 ;# 407 bleu+1 sub %r6,%r4,%r19 ;# 409 subsi3/1 addl %r28,%r19,%r6 ;# 412 addsi3/1 sub %r12,%r4,%r19 ;# 413 subsi3/1 comib,= 0,%r10,L$0069 ;# 418 bleu+1 addl %r28,%r19,%r12 ;# 416 addsi3/1 sub %r10,%r4,%r19 ;# 419 subsi3/1 addl %r28,%r19,%r10 ;# 422 addsi3/1 L$0069 comib,= 0,%r8,L$0070 ;# 425 bleu+1 sub %r8,%r4,%r19 ;# 426 subsi3/1 addl %r28,%r19,%r8 ;# 429 addsi3/1 L$0070 comib,= 0,%r9,L$0059 ;# 432 bleu+1 sub %r9,%r4,%r19 ;# 433 subsi3/1 addl %r28,%r19,%r9 ;# 436 addsi3/1 L$0059 ldw 0(%r5),%r4 ;# 337 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 341 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 338 subsi3/1 ldo 1(%r19),%r19 ;# 339 addsi3/2 comb,<< %r20,%r19,L$0061 nop ;# 343 bleu+1 L$0060 ldi 8,%r19 ;# 458 movqi+1/2 bl L$0043,%r0 ;# 479 jump stbs,ma %r19,1(%r6) ;# 459 movqi+1/6 L$0077 comb,=,n %r16,%r26,L$0079 ;# 485 bleu+1 bb,< %r15,28,L$0079 ;# 490 bleu+3 copy %r16,%r25 ;# 494 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl at_endline_loc_p,%r2 ;# 498 call_value_internal_symref copy %r15,%r24 ;# 496 reload_outsi+2/1 extrs %r28,31,8,%r28 ;# 501 extendqisi2 comiclr,<> 0,%r28,%r0 ;# 503 bleu+1 bl,n L$0076,%r0 L$0079 ldw 0(%r5),%r4 ;# 7994 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7997 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7995 subsi3/1 ldo 1(%r19),%r19 ;# 7996 addsi3/2 comb,>>=,n %r20,%r19,L$0084 ;# 7998 bleu+1 ldil L'65536,%r3 ;# 8699 reload_outsi+2/3 L$0085 comclr,<> %r3,%r20,%r0 ;# 534 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 544 ashlsi3+1 comb,>>= %r3,%r19,L$0090 ;# 552 bleu+1 stw %r19,4(%r5) ;# 546 reload_outsi+2/6 stw %r3,4(%r5) ;# 555 reload_outsi+2/6 L$0090 ldw 0(%r5),%r26 ;# 562 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 566 call_value_internal_symref ldw 4(%r5),%r25 ;# 564 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 574 bleu+1 stw %r28,0(%r5) ;# 570 reload_outsi+2/6 comb,= %r28,%r4,L$0083 ;# 584 bleu+1 sub %r6,%r4,%r19 ;# 586 subsi3/1 addl %r28,%r19,%r6 ;# 589 addsi3/1 sub %r12,%r4,%r19 ;# 590 subsi3/1 comib,= 0,%r10,L$0093 ;# 595 bleu+1 addl %r28,%r19,%r12 ;# 593 addsi3/1 sub %r10,%r4,%r19 ;# 596 subsi3/1 addl %r28,%r19,%r10 ;# 599 addsi3/1 L$0093 comib,= 0,%r8,L$0094 ;# 602 bleu+1 sub %r8,%r4,%r19 ;# 603 subsi3/1 addl %r28,%r19,%r8 ;# 606 addsi3/1 L$0094 comib,= 0,%r9,L$0083 ;# 609 bleu+1 sub %r9,%r4,%r19 ;# 610 subsi3/1 addl %r28,%r19,%r9 ;# 613 addsi3/1 L$0083 ldw 0(%r5),%r4 ;# 514 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 518 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 515 subsi3/1 ldo 1(%r19),%r19 ;# 516 addsi3/2 comb,<< %r20,%r19,L$0085 nop ;# 520 bleu+1 L$0084 ldi 9,%r19 ;# 635 movqi+1/2 bl L$0043,%r0 ;# 656 jump stbs,ma %r19,1(%r6) ;# 636 movqi+1/6 L$0877 bl L$0110,%r0 ;# 897 jump stw %r21,-296(%r30) ;# 2391 reload_outsi+2/6 L$0101 L$1158 and %r15,%r19,%r19 ;# 663 andsi3/1 comiclr,= 0,%r19,%r0 ;# 665 bleu+1 bl,n L$0076,%r0 L$0104 comib,<> 0,%r8,L$0105 ;# 674 bleu+1 ldi 0,%r13 ;# 711 reload_outsi+2/2 extrs,>= %r15,26,1,%r0 ;# 681 bleu+3 extrs,< %r15,27,1,%r0 ;# 700 movsi-4 nop bl,n L$0076,%r0 L$0105 ldi 0,%r11 ;# 714 reload_outsi+2/2 ldi 0,%r22 ;# 716 reload_outsi+2/2 ldi 43,%r24 ;# 8688 reload_outsi+2/2 ldi 63,%r23 ;# 8690 reload_outsi+2/2 ldi 42,%r28 ;# 8692 reload_outsi+2/2 ldi 2,%r19 ;# 8694 reload_outsi+2/2 and %r15,%r19,%r25 ;# 8695 andsi3/1 ldi 92,%r26 ;# 8697 reload_outsi+2/2 L$0109 comb,= %r24,%r7,L$0112 ;# 727 bleu+1 copy %r11,%r19 ;# 8780 reload_outsi+2/1 depi -1,31,1,%r19 ;# 729 iorsi3+1/2 bl L$0113,%r0 ;# 731 jump extrs %r19,31,8,%r19 ;# 730 extendqisi2 L$0112 extrs %r11,31,8,%r19 ;# 734 extendqisi2 L$0113 L$1159 comb,= %r23,%r7,L$0114 ;# 744 bleu+1 copy %r19,%r11 ;# 737 reload_outsi+2/1 copy %r22,%r19 ;# 8783 reload_outsi+2/1 depi -1,31,1,%r19 ;# 746 iorsi3+1/2 bl L$0115,%r0 ;# 748 jump extrs %r19,31,8,%r19 ;# 747 extendqisi2 L$0114 extrs %r22,31,8,%r19 ;# 751 extendqisi2 L$0115 ldw -296(%r30),%r21 ;# 2355 reload_outsi+2/5 comb,= %r16,%r21,L$0110 ;# 757 bleu+1 copy %r19,%r22 ;# 754 reload_outsi+2/1 copy %r21,%r20 ;# 8743 reload_outsi+2/1 ldbs,ma 1(%r20),%r7 ;# 776 zero_extendqisi2/2 comib,= 0,%r14,L$0118 ;# 781 bleu+1 stw %r20,-296(%r30) ;# 2364 reload_outsi+2/6 addl %r14,%r7,%r19 ;# 782 addsi3/1 ldb 0(%r19),%r7 ;# 785 zero_extendqisi2/2 L$0118 comb,= %r28,%r7,L$0109 nop ;# 802 bleu+1 comib,<>,n 0,%r25,L$0869 ;# 807 bleu+1 comb,= %r24,%r7,L$1159 ;# 811 bleu+1 extrs %r11,31,8,%r19 ;# 734 extendqisi2 comb,= %r23,%r7,L$0109 ;# 815 bleu+1 ldw -296(%r30),%r19 ;# 2400 reload_outsi+2/5 bl,n L$1160,%r0 ;# 827 jump L$0869 comb,<> %r26,%r7,L$0126 ;# 831 bleu+1 ldw -296(%r30),%r19 ;# 2400 reload_outsi+2/5 comclr,<> %r16,%r20,%r0 ;# 835 bleu+1 bl L$0903,%r0 ldo 1(%r20),%r19 ;# 863 addsi3/2 ldb 1(%r21),%r3 ;# 860 zero_extendqisi2/2 comib,= 0,%r14,L$0129 ;# 865 bleu+1 stw %r19,-296(%r30) ;# 2379 reload_outsi+2/6 addl %r14,%r3,%r19 ;# 866 addsi3/1 ldb 0(%r19),%r3 ;# 869 zero_extendqisi2/2 L$0129 comb,= %r24,%r3,L$0109 ;# 886 bleu+1 copy %r3,%r7 ;# 903 reload_outsi+2/1 comb,<> %r23,%r3,L$0877 nop ;# 890 bleu+1 bl,n L$0109,%r0 ;# 905 jump L$0126 L$1160 ldo -1(%r19),%r19 ;# 910 addsi3/2 stw %r19,-296(%r30) ;# 2397 reload_outsi+2/6 L$0110 comiclr,<> 0,%r8,%r0 ;# 927 bleu+1 bl L$1161,%r0 ldw -296(%r30),%r19 ;# 2328 reload_outsi+2/5 comib,=,n 0,%r22,L$0137 ;# 934 bleu+1 ldw 0(%r5),%r3 ;# 8002 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8005 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8003 subsi3/1 ldo 3(%r19),%r19 ;# 8004 addsi3/2 comb,>>=,n %r20,%r19,L$0139 ;# 8006 bleu+1 ldil L'65536,%r4 ;# 8686 reload_outsi+2/3 L$0140 comclr,<> %r4,%r20,%r0 ;# 961 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 971 ashlsi3+1 comb,>>= %r4,%r19,L$0145 ;# 979 bleu+1 stw %r19,4(%r5) ;# 973 reload_outsi+2/6 stw %r4,4(%r5) ;# 982 reload_outsi+2/6 L$0145 ldw 0(%r5),%r26 ;# 989 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 993 call_value_internal_symref ldw 4(%r5),%r25 ;# 991 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1001 bleu+1 stw %r28,0(%r5) ;# 997 reload_outsi+2/6 comb,= %r28,%r3,L$0138 ;# 1011 bleu+1 sub %r6,%r3,%r19 ;# 1013 subsi3/1 addl %r28,%r19,%r6 ;# 1016 addsi3/1 sub %r12,%r3,%r19 ;# 1017 subsi3/1 comib,= 0,%r10,L$0148 ;# 1022 bleu+1 addl %r28,%r19,%r12 ;# 1020 addsi3/1 sub %r10,%r3,%r19 ;# 1023 subsi3/1 addl %r28,%r19,%r10 ;# 1026 addsi3/1 L$0148 comib,= 0,%r8,L$0149 ;# 1029 bleu+1 sub %r8,%r3,%r19 ;# 1030 subsi3/1 addl %r28,%r19,%r8 ;# 1033 addsi3/1 L$0149 comib,= 0,%r9,L$0138 ;# 1036 bleu+1 sub %r9,%r3,%r19 ;# 1037 subsi3/1 addl %r28,%r19,%r9 ;# 1040 addsi3/1 L$0138 ldw 0(%r5),%r3 ;# 941 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 945 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 942 subsi3/1 ldo 3(%r19),%r19 ;# 943 addsi3/2 comb,<< %r20,%r19,L$0140 nop ;# 947 bleu+1 L$0139 comib,= 0,%r14,L$0154 ;# 1063 bleu+1 ldw -296(%r30),%r19 ;# 2403 reload_outsi+2/5 ldb -2(%r19),%r19 ;# 1066 zero_extendqisi2/2 addl %r14,%r19,%r19 ;# 1067 addsi3/1 bl L$0947,%r0 ;# 1071 jump ldb 0(%r19),%r19 ;# 1069 movqi+1/5 L$0154 ldb -2(%r19),%r19 ;# 1075 movqi+1/5 L$0947 comib,= 0,%r14,L$0156 ;# 1079 bleu+1 extrs %r19,31,8,%r20 ;# 1076 extendqisi2 ldb 46(%r14),%r19 ;# 1081 movqi+1/5 extrs %r19,31,8,%r19 ;# 1082 extendqisi2 comb,= %r19,%r20,L$0157 ;# 1084 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 bl,n L$1162,%r0 ;# 1085 jump L$0156 ldi 46,%r19 ;# 1089 reload_outsi+2/2 comb,<> %r19,%r20,L$1162 ;# 1091 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 L$0157 comib,= 0,%r11,L$0153 ;# 1096 bleu+1 ldw -296(%r30),%r19 ;# 2409 reload_outsi+2/5 comb,<<= %r16,%r19,L$1162 ;# 1098 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 comib,=,n 0,%r14,L$0158 ;# 1100 bleu+1 ldb 0(%r19),%r19 ;# 1103 zero_extendqisi2/2 addl %r14,%r19,%r19 ;# 1104 addsi3/1 L$0158 ldb 0(%r19),%r19 ;# 1112 movqi+1/5 comib,= 0,%r14,L$0160 ;# 1116 bleu+1 extrs %r19,31,8,%r20 ;# 1113 extendqisi2 ldb 10(%r14),%r19 ;# 1118 movqi+1/5 extrs %r19,31,8,%r19 ;# 1119 extendqisi2 comb,= %r19,%r20,L$0161 ;# 1121 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 bl,n L$1162,%r0 ;# 1122 jump L$0160 comib,<> 10,%r20,L$1162 ;# 1126 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 L$0161 bb,< %r15,25,L$1162 ;# 1134 bleu+3 ldi 17,%r26 ;# 1159 reload_outsi+2/2 ldi 12,%r26 ;# 1140 reload_outsi+2/2 copy %r6,%r25 ;# 1142 reload_outsi+2/1 sub %r8,%r6,%r24 ;# 1137 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 1146 call_internal_symref ldo -3(%r24),%r24 ;# 1144 addsi3/2 bl L$0162,%r0 ;# 1151 jump ldi 1,%r13 ;# 1149 reload_outsi+2/2 L$0153 ldi 17,%r26 ;# 1159 reload_outsi+2/2 L$1162 copy %r6,%r25 ;# 1161 reload_outsi+2/1 sub %r8,%r6,%r24 ;# 1156 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 1165 call_internal_symref ldo -6(%r24),%r24 ;# 1163 addsi3/2 L$0162 ldo 3(%r6),%r6 ;# 1168 addsi3/2 L$0137 ldw 0(%r5),%r3 ;# 8010 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8013 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8011 subsi3/1 ldo 3(%r19),%r19 ;# 8012 addsi3/2 comb,>>=,n %r20,%r19,L$0164 ;# 8014 bleu+1 ldil L'65536,%r4 ;# 8684 reload_outsi+2/3 L$0165 comclr,<> %r4,%r20,%r0 ;# 1195 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 1205 ashlsi3+1 comb,>>= %r4,%r19,L$0170 ;# 1213 bleu+1 stw %r19,4(%r5) ;# 1207 reload_outsi+2/6 stw %r4,4(%r5) ;# 1216 reload_outsi+2/6 L$0170 ldw 0(%r5),%r26 ;# 1223 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1227 call_value_internal_symref ldw 4(%r5),%r25 ;# 1225 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1235 bleu+1 stw %r28,0(%r5) ;# 1231 reload_outsi+2/6 comb,= %r28,%r3,L$0163 ;# 1245 bleu+1 sub %r6,%r3,%r19 ;# 1247 subsi3/1 addl %r28,%r19,%r6 ;# 1250 addsi3/1 sub %r12,%r3,%r19 ;# 1251 subsi3/1 comib,= 0,%r10,L$0173 ;# 1256 bleu+1 addl %r28,%r19,%r12 ;# 1254 addsi3/1 sub %r10,%r3,%r19 ;# 1257 subsi3/1 addl %r28,%r19,%r10 ;# 1260 addsi3/1 L$0173 comib,= 0,%r8,L$0174 ;# 1263 bleu+1 sub %r8,%r3,%r19 ;# 1264 subsi3/1 addl %r28,%r19,%r8 ;# 1267 addsi3/1 L$0174 comib,= 0,%r9,L$0163 ;# 1270 bleu+1 sub %r9,%r3,%r19 ;# 1271 subsi3/1 addl %r28,%r19,%r9 ;# 1274 addsi3/1 L$0163 ldw 0(%r5),%r3 ;# 1175 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1179 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 1176 subsi3/1 ldo 3(%r19),%r19 ;# 1177 addsi3/2 comb,<< %r20,%r19,L$0165 nop ;# 1181 bleu+1 L$0164 ldi 14,%r26 ;# 8786 reload_outsi+2/2 comiclr,= 0,%r13,%r0 ;# 1310 beq-1/2 ldi 15,%r26 copy %r8,%r25 ;# 1312 reload_outsi+2/1 sub %r6,%r8,%r24 ;# 1314 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 1318 call_internal_symref copy %r6,%r23 ;# 1316 reload_outsi+2/1 ldi 0,%r9 ;# 1321 reload_outsi+2/2 comib,<> 0,%r11,L$0043 ;# 1326 bleu+1 ldo 3(%r6),%r6 ;# 1323 addsi3/2 ldw 0(%r5),%r3 ;# 8019 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8022 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8020 subsi3/1 ldo 3(%r19),%r19 ;# 8021 addsi3/2 comb,>>=,n %r20,%r19,L$0182 ;# 8023 bleu+1 ldil L'65536,%r4 ;# 8682 reload_outsi+2/3 L$0183 comb,= %r4,%r20,L$0944 ;# 1352 bleu+1 zdep %r20,30,31,%r19 ;# 1362 ashlsi3+1 comb,>>= %r4,%r19,L$0188 ;# 1370 bleu+1 stw %r19,4(%r5) ;# 1364 reload_outsi+2/6 stw %r4,4(%r5) ;# 1373 reload_outsi+2/6 L$0188 ldw 0(%r5),%r26 ;# 1380 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1384 call_value_internal_symref ldw 4(%r5),%r25 ;# 1382 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1392 bleu+1 stw %r28,0(%r5) ;# 1388 reload_outsi+2/6 comb,= %r28,%r3,L$0181 ;# 1402 bleu+1 sub %r6,%r3,%r19 ;# 1404 subsi3/1 addl %r28,%r19,%r6 ;# 1407 addsi3/1 sub %r12,%r3,%r19 ;# 1408 subsi3/1 comib,= 0,%r10,L$0191 ;# 1413 bleu+1 addl %r28,%r19,%r12 ;# 1411 addsi3/1 sub %r10,%r3,%r19 ;# 1414 subsi3/1 addl %r28,%r19,%r10 ;# 1417 addsi3/1 L$0191 comib,= 0,%r8,L$0192 ;# 1420 bleu+1 sub %r8,%r3,%r19 ;# 1421 subsi3/1 addl %r28,%r19,%r8 ;# 1424 addsi3/1 L$0192 comib,= 0,%r9,L$0181 ;# 1427 bleu+1 sub %r9,%r3,%r19 ;# 1428 subsi3/1 addl %r28,%r19,%r9 ;# 1431 addsi3/1 L$0181 ldw 0(%r5),%r3 ;# 1332 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1336 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 1333 subsi3/1 ldo 3(%r19),%r19 ;# 1334 addsi3/2 comb,<< %r20,%r19,L$0183 nop ;# 1338 bleu+1 L$0182 ldi 18,%r26 ;# 1454 reload_outsi+2/2 copy %r8,%r25 ;# 1456 reload_outsi+2/1 ldi 3,%r24 ;# 1458 reload_outsi+2/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 1462 call_internal_symref copy %r6,%r23 ;# 1460 reload_outsi+2/1 bl L$0043,%r0 ;# 1470 jump ldo 3(%r6),%r6 ;# 1464 addsi3/2 L$0196 ldw 4(%r5),%r20 ;# 8030 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8028 subsi3/1 ldo 1(%r19),%r19 ;# 8029 addsi3/2 comb,>>= %r20,%r19,L$0201 ;# 8031 bleu+1 copy %r6,%r8 ;# 1475 reload_outsi+2/1 ldil L'65536,%r3 ;# 8680 reload_outsi+2/3 L$0202 comb,= %r3,%r20,L$0944 ;# 1503 bleu+1 zdep %r20,30,31,%r19 ;# 1513 ashlsi3+1 comb,>>= %r3,%r19,L$0207 ;# 1521 bleu+1 stw %r19,4(%r5) ;# 1515 reload_outsi+2/6 stw %r3,4(%r5) ;# 1524 reload_outsi+2/6 L$0207 ldw 0(%r5),%r26 ;# 1531 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1535 call_value_internal_symref ldw 4(%r5),%r25 ;# 1533 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1543 bleu+1 stw %r28,0(%r5) ;# 1539 reload_outsi+2/6 comb,= %r28,%r4,L$0200 ;# 1553 bleu+1 sub %r6,%r4,%r19 ;# 1555 subsi3/1 addl %r28,%r19,%r6 ;# 1558 addsi3/1 sub %r12,%r4,%r19 ;# 1559 subsi3/1 comib,= 0,%r10,L$0210 ;# 1564 bleu+1 addl %r28,%r19,%r12 ;# 1562 addsi3/1 sub %r10,%r4,%r19 ;# 1565 subsi3/1 addl %r28,%r19,%r10 ;# 1568 addsi3/1 L$0210 comib,= 0,%r8,L$0211 ;# 1571 bleu+1 sub %r8,%r4,%r19 ;# 1572 subsi3/1 addl %r28,%r19,%r8 ;# 1575 addsi3/1 L$0211 comib,= 0,%r9,L$0200 ;# 1578 bleu+1 sub %r9,%r4,%r19 ;# 1579 subsi3/1 addl %r28,%r19,%r9 ;# 1582 addsi3/1 L$0200 ldw 0(%r5),%r4 ;# 1483 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1487 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 1484 subsi3/1 ldo 1(%r19),%r19 ;# 1485 addsi3/2 comb,<< %r20,%r19,L$0202 nop ;# 1489 bleu+1 L$0201 ldi 2,%r19 ;# 1604 movqi+1/2 bl L$0043,%r0 ;# 1617 jump stbs,ma %r19,1(%r6) ;# 1605 movqi+1/6 L$0216 comb,= %r16,%r19,L$0902 ;# 1626 bleu+1 ldi 0,%r13 ;# 1623 reload_outsi+2/2 ldw 0(%r5),%r3 ;# 8035 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8038 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8036 subsi3/1 ldo 34(%r19),%r19 ;# 8037 addsi3/2 comb,>>= %r20,%r19,L$0219 ;# 8039 bleu+1 ldil L'65536,%r4 ;# 8678 reload_outsi+2/3 L$0220 comb,= %r4,%r20,L$0944 ;# 1661 bleu+1 zdep %r20,30,31,%r19 ;# 1671 ashlsi3+1 comb,>>= %r4,%r19,L$0225 ;# 1679 bleu+1 stw %r19,4(%r5) ;# 1673 reload_outsi+2/6 stw %r4,4(%r5) ;# 1682 reload_outsi+2/6 L$0225 ldw 0(%r5),%r26 ;# 1689 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1693 call_value_internal_symref ldw 4(%r5),%r25 ;# 1691 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1701 bleu+1 stw %r28,0(%r5) ;# 1697 reload_outsi+2/6 comb,= %r28,%r3,L$0218 ;# 1711 bleu+1 sub %r6,%r3,%r19 ;# 1713 subsi3/1 addl %r28,%r19,%r6 ;# 1716 addsi3/1 sub %r12,%r3,%r19 ;# 1717 subsi3/1 comib,= 0,%r10,L$0228 ;# 1722 bleu+1 addl %r28,%r19,%r12 ;# 1720 addsi3/1 sub %r10,%r3,%r19 ;# 1723 subsi3/1 addl %r28,%r19,%r10 ;# 1726 addsi3/1 L$0228 comib,= 0,%r8,L$0229 ;# 1729 bleu+1 sub %r8,%r3,%r19 ;# 1730 subsi3/1 addl %r28,%r19,%r8 ;# 1733 addsi3/1 L$0229 comib,= 0,%r9,L$0218 ;# 1736 bleu+1 sub %r9,%r3,%r19 ;# 1737 subsi3/1 addl %r28,%r19,%r9 ;# 1740 addsi3/1 L$0218 ldw 0(%r5),%r3 ;# 1641 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1645 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 1642 subsi3/1 ldo 34(%r19),%r19 ;# 1643 addsi3/2 comb,<< %r20,%r19,L$0220 nop ;# 1647 bleu+1 L$0219 ldw 0(%r5),%r4 ;# 8043 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8046 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8044 subsi3/1 ldo 1(%r19),%r19 ;# 8045 addsi3/2 comb,>>= %r20,%r19,L$0237 ;# 8047 bleu+1 copy %r6,%r8 ;# 1763 reload_outsi+2/1 ldil L'65536,%r3 ;# 8676 reload_outsi+2/3 L$0238 comb,= %r3,%r20,L$0944 ;# 1791 bleu+1 zdep %r20,30,31,%r19 ;# 1801 ashlsi3+1 comb,>>= %r3,%r19,L$0243 ;# 1809 bleu+1 stw %r19,4(%r5) ;# 1803 reload_outsi+2/6 stw %r3,4(%r5) ;# 1812 reload_outsi+2/6 L$0243 ldw 0(%r5),%r26 ;# 1819 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1823 call_value_internal_symref ldw 4(%r5),%r25 ;# 1821 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1831 bleu+1 stw %r28,0(%r5) ;# 1827 reload_outsi+2/6 comb,= %r28,%r4,L$0236 ;# 1841 bleu+1 sub %r6,%r4,%r19 ;# 1843 subsi3/1 addl %r28,%r19,%r6 ;# 1846 addsi3/1 sub %r12,%r4,%r19 ;# 1847 subsi3/1 comib,= 0,%r10,L$0246 ;# 1852 bleu+1 addl %r28,%r19,%r12 ;# 1850 addsi3/1 sub %r10,%r4,%r19 ;# 1853 subsi3/1 addl %r28,%r19,%r10 ;# 1856 addsi3/1 L$0246 comib,= 0,%r8,L$0247 ;# 1859 bleu+1 sub %r8,%r4,%r19 ;# 1860 subsi3/1 addl %r28,%r19,%r8 ;# 1863 addsi3/1 L$0247 comib,= 0,%r9,L$0236 ;# 1866 bleu+1 sub %r9,%r4,%r19 ;# 1867 subsi3/1 addl %r28,%r19,%r9 ;# 1870 addsi3/1 L$0236 ldw 0(%r5),%r4 ;# 1771 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1775 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 1772 subsi3/1 ldo 1(%r19),%r19 ;# 1773 addsi3/2 comb,<< %r20,%r19,L$0238 nop ;# 1777 bleu+1 L$0237 copy %r6,%r22 ;# 1909 reload_outsi+2/1 ldo 1(%r6),%r6 ;# 1891 addsi3/2 ldw -296(%r30),%r19 ;# 2421 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 1893 movqi+1/5 ldi 94,%r21 ;# 1896 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 1894 extendqisi2 comb,<> %r21,%r19,L$0251 ;# 1898 bleu+1 ldi 3,%r20 ;# 8051 movqi+1/2 ldi 4,%r20 ;# 1900 movqi+1/2 L$0251 stb %r20,0(%r22) ;# 1911 movqi+1/6 ldw -296(%r30),%r20 ;# 2424 reload_outsi+2/5 ldb 0(%r20),%r19 ;# 1923 movqi+1/5 extrs %r19,31,8,%r19 ;# 1924 extendqisi2 comb,<> %r21,%r19,L$0254 ;# 1928 bleu+1 ldo 1(%r20),%r19 ;# 1930 addsi3/2 stw %r19,-296(%r30) ;# 2427 reload_outsi+2/6 L$0254 ldw 0(%r5),%r4 ;# 8052 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8055 reload_outsi+2/5 ldw -296(%r30),%r1 ;# 2433 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8053 subsi3/1 ldo 1(%r19),%r19 ;# 8054 addsi3/2 comb,>>= %r20,%r19,L$0259 ;# 8056 bleu+1 stw %r1,-268(%r30) ;# 8789 reload_outsi+2/6 ldil L'65536,%r3 ;# 8674 reload_outsi+2/3 L$0260 comb,= %r3,%r20,L$0944 ;# 1962 bleu+1 zdep %r20,30,31,%r19 ;# 1972 ashlsi3+1 comb,>>= %r3,%r19,L$0265 ;# 1980 bleu+1 stw %r19,4(%r5) ;# 1974 reload_outsi+2/6 stw %r3,4(%r5) ;# 1983 reload_outsi+2/6 L$0265 ldw 0(%r5),%r26 ;# 1990 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1994 call_value_internal_symref ldw 4(%r5),%r25 ;# 1992 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 2002 bleu+1 stw %r28,0(%r5) ;# 1998 reload_outsi+2/6 comb,= %r28,%r4,L$0258 ;# 2012 bleu+1 sub %r6,%r4,%r19 ;# 2014 subsi3/1 addl %r28,%r19,%r6 ;# 2017 addsi3/1 sub %r12,%r4,%r19 ;# 2018 subsi3/1 comib,= 0,%r10,L$0268 ;# 2023 bleu+1 addl %r28,%r19,%r12 ;# 2021 addsi3/1 sub %r10,%r4,%r19 ;# 2024 subsi3/1 addl %r28,%r19,%r10 ;# 2027 addsi3/1 L$0268 comib,= 0,%r8,L$0269 ;# 2030 bleu+1 sub %r8,%r4,%r19 ;# 2031 subsi3/1 addl %r28,%r19,%r8 ;# 2034 addsi3/1 L$0269 comib,= 0,%r9,L$0258 ;# 2037 bleu+1 sub %r9,%r4,%r19 ;# 2038 subsi3/1 addl %r28,%r19,%r9 ;# 2041 addsi3/1 L$0258 ldw 0(%r5),%r4 ;# 1942 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1946 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 1943 subsi3/1 ldo 1(%r19),%r19 ;# 1944 addsi3/2 comb,<< %r20,%r19,L$0260 nop ;# 1948 bleu+1 L$0259 ldi 32,%r19 ;# 2063 movqi+1/2 stbs,ma %r19,1(%r6) ;# 2064 movqi+1/6 copy %r6,%r26 ;# 2077 reload_outsi+2/1 ldi 0,%r25 ;# 2079 reload_outsi+2/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 ;# 2083 call_value_internal_symref ldi 32,%r24 ;# 2081 reload_outsi+2/2 ldb -2(%r6),%r19 ;# 2087 zero_extendqisi2/2 comib,<> 4,%r19,L$0274 ;# 2089 bleu+1 ldi 93,%r17 ;# 8622 reload_outsi+2/2 bb,>=,n %r15,23,L$0274 ;# 2094 movsi-4 ldb 1(%r6),%r19 ;# 2097 movqi+1/5 depi -1,29,1,%r19 ;# 2099 iorsi3+1/2 stb %r19,1(%r6) ;# 2101 movqi+1/6 L$0274 ldi 4,%r18 ;# 8628 reload_outsi+2/2 and %r15,%r18,%r1 ;# 8629 andsi3/1 stw %r1,-252(%r30) ;# 8792 reload_outsi+2/6 ldo -288(%r30),%r11 ;# 8632 addsi3/2 L$0275 ldw -296(%r30),%r20 ;# 2436 reload_outsi+2/5 L$1165 comb,= %r16,%r20,L$0902 ;# 2109 bleu+1 copy %r20,%r21 ;# 8745 reload_outsi+2/1 ldbs,ma 1(%r21),%r7 ;# 2134 zero_extendqisi2/2 comib,= 0,%r14,L$0280 ;# 2139 bleu+1 stw %r21,-296(%r30) ;# 2445 reload_outsi+2/6 addl %r14,%r7,%r19 ;# 2140 addsi3/1 ldb 0(%r19),%r7 ;# 2143 zero_extendqisi2/2 L$0280 bb,>= %r15,31,L$0285 ;# 2159 movsi-4 ldi 92,%r19 ;# 2161 reload_outsi+2/2 comb,<>,n %r19,%r7,L$0285 ;# 2163 bleu+1 comb,= %r16,%r21,L$0903 ;# 2167 bleu+1 ldo 1(%r21),%r19 ;# 2195 addsi3/2 ldb 1(%r20),%r3 ;# 2192 zero_extendqisi2/2 comib,= 0,%r14,L$0288 ;# 2197 bleu+1 stw %r19,-296(%r30) ;# 2460 reload_outsi+2/6 addl %r14,%r3,%r19 ;# 2198 addsi3/1 ldb 0(%r19),%r3 ;# 2201 zero_extendqisi2/2 L$0288 extru %r3,28,29,%r19 ;# 2216 lshrsi3/2 addl %r6,%r19,%r19 ;# 2219 addsi3/1 bl L$0948,%r0 ;# 2235 jump extru %r3,31,3,%r20 ;# 2222 andsi3/1 L$0285 comb,<>,n %r17,%r7,L$0293 ;# 2243 bleu+1 ldw -268(%r30),%r1 ;# 8798 reload_outsi+2/5 ldw -296(%r30),%r20 ;# 2466 reload_outsi+2/5 ldo 1(%r1),%r19 ;# 2244 addsi3/2 comb,<>,n %r19,%r20,L$0276 ;# 2246 bleu+1 L$0293 comib,= 0,%r13,L$0294 ;# 2253 bleu+1 ldi 45,%r1 ;# 8801 reload_outsi+2/2 comb,<> %r1,%r7,L$1163 ;# 2257 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 ldw -296(%r30),%r19 ;# 2469 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 2259 movqi+1/5 extrs %r19,31,8,%r19 ;# 2260 extendqisi2 comb,<>,n %r17,%r19,L$0895 ;# 2264 bleu+1 L$0294 ldi 45,%r1 ;# 8804 reload_outsi+2/2 comb,<> %r1,%r7,L$1163 ;# 2280 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 ldw -276(%r30),%r1 ;# 8807 reload_outsi+2/5 ldo -2(%r20),%r19 ;# 2281 addsi3/2 comb,>>,n %r1,%r19,L$1179 ;# 2283 bleu+1 ldb -2(%r20),%r19 ;# 2285 movqi+1/5 ldi 91,%r1 ;# 8810 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2286 extendqisi2 comb,= %r1,%r19,L$1163 ;# 2290 bleu+1 ldw -276(%r30),%r1 ;# 8813 reload_outsi+2/5 L$1179 ldo -3(%r20),%r19 ;# 2294 addsi3/2 comb,>>,n %r1,%r19,L$0297 ;# 2296 bleu+1 ldb -3(%r20),%r19 ;# 2298 movqi+1/5 ldi 91,%r1 ;# 8816 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2299 extendqisi2 comb,<> %r1,%r19,L$1164 ;# 2303 bleu+1 ldw -296(%r30),%r19 ;# 2487 reload_outsi+2/5 ldb -2(%r20),%r19 ;# 2305 movqi+1/5 ldi 94,%r20 ;# 2308 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2306 extendqisi2 comb,= %r20,%r19,L$1163 ;# 2310 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 L$0297 ldw -296(%r30),%r19 ;# 2487 reload_outsi+2/5 L$1164 ldb 0(%r19),%r19 ;# 2315 movqi+1/5 extrs %r19,31,8,%r19 ;# 2316 extendqisi2 comb,<> %r17,%r19,L$0302 ;# 2320 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 L$1163 ldb 0(%r20),%r19 ;# 2526 movqi+1/5 ldi 45,%r1 ;# 8819 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2527 extendqisi2 comb,<>,n %r1,%r19,L$0300 ;# 2531 bleu+1 ldb 1(%r20),%r19 ;# 2535 movqi+1/5 extrs %r19,31,8,%r19 ;# 2536 extendqisi2 comb,=,n %r17,%r19,L$0300 ;# 2540 bleu+1 comb,= %r16,%r20,L$0922 ;# 2550 bleu+1 ldo 1(%r20),%r19 ;# 2559 addsi3/2 stw %r19,-296(%r30) ;# 2561 reload_outsi+2/6 L$0302 stw %r6,-52(%r30) ;# 2588 reload_outsi+2/6 ldo -296(%r30),%r26 ;# 2590 addsi3/2 copy %r16,%r25 ;# 2592 reload_outsi+2/1 copy %r14,%r24 ;# 2594 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl compile_range,%r2 ;# 2598 call_value_internal_symref copy %r15,%r23 ;# 2596 reload_outsi+2/1 movb,= %r28,%r4,L$1165 ;# 2603 decrement_and_branch_until_zero+2/1 ldw -296(%r30),%r20 ;# 2436 reload_outsi+2/5 .CALL ARGW0=GR bl free,%r2 ;# 2607 call_internal_symref ldw -312(%r30),%r26 ;# 2605 reload_outsi+2/5 bl L$0867,%r0 ;# 2611 jump copy %r4,%r28 ;# 2609 reload_outsi+2/1 L$0300 ldw -252(%r30),%r1 ;# 8822 reload_outsi+2/5 comib,= 0,%r1,L$0309 ;# 2624 bleu+1 ldi 91,%r1 ;# 8825 reload_outsi+2/2 comb,<> %r1,%r7,L$1166 ;# 2628 bleu+1 ldi 0,%r13 ;# 3624 reload_outsi+2/2 ldw -296(%r30),%r20 ;# 2630 reload_outsi+2/5 ldb 0(%r20),%r19 ;# 2632 movqi+1/5 ldi 58,%r1 ;# 8828 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2633 extendqisi2 comb,<>,n %r1,%r19,L$1166 ;# 2637 bleu+1 comb,= %r16,%r20,L$0922 ;# 2647 bleu+1 ldo 1(%r20),%r19 ;# 2656 addsi3/2 stw %r19,-296(%r30) ;# 2658 reload_outsi+2/6 comb,= %r16,%r19,L$0902 ;# 2689 bleu+1 ldi 0,%r3 ;# 2684 reload_outsi+2/2 L$0317 ldw -296(%r30),%r19 ;# 2709 reload_outsi+2/5 comb,= %r16,%r19,L$0922 ;# 2711 bleu+1 ldo 1(%r19),%r20 ;# 2720 addsi3/2 stw %r20,-296(%r30) ;# 2722 reload_outsi+2/6 comib,= 0,%r14,L$0321 ;# 2729 bleu+1 ldb 0(%r19),%r7 ;# 2725 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 2730 addsi3/1 ldb 0(%r19),%r7 ;# 2733 zero_extendqisi2/2 L$0321 ldi 58,%r1 ;# 8831 reload_outsi+2/2 comb,= %r1,%r7,L$1167 ;# 2750 bleu+1 addl %r11,%r3,%r19 ;# 2789 addsi3/1 comb,=,n %r17,%r7,L$1167 ;# 2754 bleu+1 comb,=,n %r16,%r20,L$1167 ;# 2758 bleu+1 comib,= 6,%r3,L$1167 ;# 2760 bleu+1 copy %r3,%r20 ;# 2770 reload_outsi+2/1 ldo 1(%r20),%r19 ;# 2771 addsi3/2 extru %r19,31,8,%r3 ;# 2772 zero_extendqisi2/1 addl %r11,%r20,%r20 ;# 2776 addsi3/1 bl L$0317,%r0 ;# 2783 jump stb %r7,0(%r20) ;# 2778 movqi+1/6 L$1167 comb,<> %r1,%r7,L$0328 ;# 2796 bleu+1 stb %r0,0(%r19) ;# 2791 movqi+1/6 ldw -296(%r30),%r19 ;# 2798 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 2800 movqi+1/5 extrs %r19,31,8,%r19 ;# 2801 extendqisi2 comb,<> %r17,%r19,L$1168 ;# 2805 bleu+1 ldi 255,%r19 ;# 8069 reload_outsi+2/2 copy %r11,%r26 ;# 2813 reload_outsi+2/1 ldil LR'L$C0016,%r1 ;# 8835 add_high_const+3 ldo RR'L$C0016(%r1),%r1 ;# 8836 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2817 call_value_internal_symref copy %r1,%r25 ;# 2815 reload_outsi+2/1 copy %r11,%r26 ;# 2829 reload_outsi+2/1 ldil LR'L$C0017,%r1 ;# 8837 add_high_const+3 ldo RR'L$C0017(%r1),%r1 ;# 8838 movhi-2 copy %r1,%r25 ;# 2831 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2821 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2833 call_value_internal_symref stw %r28,-244(%r30) ;# 8841 reload_outsi+2/6 copy %r11,%r26 ;# 2845 reload_outsi+2/1 ldil LR'L$C0018,%r1 ;# 8842 add_high_const+3 ldo RR'L$C0018(%r1),%r1 ;# 8843 movhi-2 copy %r1,%r25 ;# 2847 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2837 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2849 call_value_internal_symref stw %r28,-236(%r30) ;# 8846 reload_outsi+2/6 copy %r11,%r26 ;# 2861 reload_outsi+2/1 ldil LR'L$C0019,%r1 ;# 8847 add_high_const+3 ldo RR'L$C0019(%r1),%r1 ;# 8848 movhi-2 copy %r1,%r25 ;# 2863 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2853 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2865 call_value_internal_symref stw %r28,-228(%r30) ;# 8851 reload_outsi+2/6 copy %r11,%r26 ;# 2877 reload_outsi+2/1 ldil LR'L$C0020,%r1 ;# 8852 add_high_const+3 ldo RR'L$C0020(%r1),%r1 ;# 8853 movhi-2 copy %r1,%r25 ;# 2879 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2869 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2881 call_value_internal_symref stw %r28,-220(%r30) ;# 8856 reload_outsi+2/6 copy %r11,%r26 ;# 2893 reload_outsi+2/1 ldil LR'L$C0021,%r1 ;# 8857 add_high_const+3 ldo RR'L$C0021(%r1),%r1 ;# 8858 movhi-2 copy %r1,%r25 ;# 2895 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2885 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2897 call_value_internal_symref stw %r28,-212(%r30) ;# 8861 reload_outsi+2/6 copy %r11,%r26 ;# 2909 reload_outsi+2/1 ldil LR'L$C0022,%r1 ;# 8862 add_high_const+3 ldo RR'L$C0022(%r1),%r1 ;# 8863 movhi-2 copy %r1,%r25 ;# 2911 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2901 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2913 call_value_internal_symref stw %r28,-204(%r30) ;# 8866 reload_outsi+2/6 copy %r11,%r26 ;# 2925 reload_outsi+2/1 ldil LR'L$C0023,%r1 ;# 8867 add_high_const+3 ldo RR'L$C0023(%r1),%r1 ;# 8868 movhi-2 copy %r1,%r25 ;# 2927 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2917 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2929 call_value_internal_symref stw %r28,-196(%r30) ;# 8871 reload_outsi+2/6 copy %r11,%r26 ;# 2941 reload_outsi+2/1 ldil LR'L$C0024,%r1 ;# 8872 add_high_const+3 ldo RR'L$C0024(%r1),%r1 ;# 8873 movhi-2 copy %r1,%r25 ;# 2943 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2933 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2945 call_value_internal_symref stw %r28,-188(%r30) ;# 8876 reload_outsi+2/6 copy %r11,%r26 ;# 2957 reload_outsi+2/1 ldil LR'L$C0025,%r1 ;# 8877 add_high_const+3 ldo RR'L$C0025(%r1),%r1 ;# 8878 movhi-2 copy %r1,%r25 ;# 2959 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2949 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2961 call_value_internal_symref stw %r28,-180(%r30) ;# 8881 reload_outsi+2/6 copy %r11,%r26 ;# 2973 reload_outsi+2/1 ldil LR'L$C0026,%r19 ;# 2970 add_high_const+3 ldo RR'L$C0026(%r19),%r3 ;# 2971 movhi-2 copy %r3,%r25 ;# 2975 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2965 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2977 call_value_internal_symref stw %r28,-172(%r30) ;# 8884 reload_outsi+2/6 copy %r11,%r26 ;# 2989 reload_outsi+2/1 ldil LR'L$C0027,%r19 ;# 2986 add_high_const+3 ldo RR'L$C0027(%r19),%r4 ;# 2987 movhi-2 comiclr,<> 0,%r28,%r13 ;# 2981 scc ldi 1,%r13 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2993 call_value_internal_symref copy %r4,%r25 ;# 2991 reload_outsi+2/1 copy %r11,%r26 ;# 3005 reload_outsi+2/1 ldil LR'L$C0017,%r1 ;# 8885 add_high_const+3 ldo RR'L$C0017(%r1),%r1 ;# 8886 movhi-2 comiclr,<> 0,%r28,%r7 ;# 2997 scc ldi 1,%r7 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3009 call_value_internal_symref copy %r1,%r25 ;# 3007 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3013 bleu+1 copy %r11,%r26 ;# 3018 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3022 call_value_internal_symref copy %r3,%r25 ;# 3020 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3026 bleu+1 copy %r11,%r26 ;# 3031 reload_outsi+2/1 ldil LR'L$C0022,%r1 ;# 8887 add_high_const+3 ldo RR'L$C0022(%r1),%r1 ;# 8888 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3035 call_value_internal_symref copy %r1,%r25 ;# 3033 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3039 bleu+1 copy %r11,%r26 ;# 3044 reload_outsi+2/1 ldil LR'L$C0020,%r1 ;# 8889 add_high_const+3 ldo RR'L$C0020(%r1),%r1 ;# 8890 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3048 call_value_internal_symref copy %r1,%r25 ;# 3046 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3052 bleu+1 copy %r11,%r26 ;# 3057 reload_outsi+2/1 ldil LR'L$C0016,%r1 ;# 8891 add_high_const+3 ldo RR'L$C0016(%r1),%r1 ;# 8892 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3061 call_value_internal_symref copy %r1,%r25 ;# 3059 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3065 bleu+1 copy %r11,%r26 ;# 3070 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3074 call_value_internal_symref copy %r4,%r25 ;# 3072 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3078 bleu+1 copy %r11,%r26 ;# 3083 reload_outsi+2/1 ldil LR'L$C0025,%r1 ;# 8893 add_high_const+3 ldo RR'L$C0025(%r1),%r1 ;# 8894 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3087 call_value_internal_symref copy %r1,%r25 ;# 3085 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3091 bleu+1 copy %r11,%r26 ;# 3096 reload_outsi+2/1 ldil LR'L$C0023,%r1 ;# 8895 add_high_const+3 ldo RR'L$C0023(%r1),%r1 ;# 8896 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3100 call_value_internal_symref copy %r1,%r25 ;# 3098 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3104 bleu+1 copy %r11,%r26 ;# 3109 reload_outsi+2/1 ldil LR'L$C0024,%r1 ;# 8897 add_high_const+3 ldo RR'L$C0024(%r1),%r1 ;# 8898 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3113 call_value_internal_symref copy %r1,%r25 ;# 3111 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3117 bleu+1 copy %r11,%r26 ;# 3122 reload_outsi+2/1 ldil LR'L$C0021,%r1 ;# 8899 add_high_const+3 ldo RR'L$C0021(%r1),%r1 ;# 8900 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3126 call_value_internal_symref copy %r1,%r25 ;# 3124 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3130 bleu+1 copy %r11,%r26 ;# 3135 reload_outsi+2/1 ldil LR'L$C0019,%r1 ;# 8901 add_high_const+3 ldo RR'L$C0019(%r1),%r1 ;# 8902 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3139 call_value_internal_symref copy %r1,%r25 ;# 3137 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3143 bleu+1 copy %r11,%r26 ;# 3148 reload_outsi+2/1 ldil LR'L$C0018,%r1 ;# 8903 add_high_const+3 ldo RR'L$C0018(%r1),%r1 ;# 8904 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3152 call_value_internal_symref copy %r1,%r25 ;# 3150 reload_outsi+2/1 comib,<>,n 0,%r28,L$0900 ;# 3156 bleu+1 L$0329 ldw -296(%r30),%r19 ;# 3173 reload_outsi+2/5 comb,= %r16,%r19,L$0922 ;# 3175 bleu+1 ldo 1(%r19),%r19 ;# 3184 addsi3/2 comb,= %r16,%r19,L$0902 ;# 3214 bleu+1 stw %r19,-296(%r30) ;# 3186 reload_outsi+2/6 ldi 0,%r22 ;# 3227 reload_outsi+2/2 addil LR'__alnum-$global$,%r27 ;# 8596 pic2_lo_sum+1 copy %r1,%r2 ;# 8907 reload_outsi+2/1 addil LR'__ctype2-$global$,%r27 ;# 8598 pic2_lo_sum+1 copy %r1,%r23 ;# 8910 reload_outsi+2/1 addil LR'__ctype-$global$,%r27 ;# 8600 pic2_lo_sum+1 copy %r1,%r4 ;# 8913 reload_outsi+2/1 ldi 32,%r25 ;# 8605 reload_outsi+2/2 ldi 2,%r24 ;# 8607 reload_outsi+2/2 ldi 16,%r31 ;# 8609 reload_outsi+2/2 ldi 8,%r29 ;# 8611 reload_outsi+2/2 ldi 128,%r28 ;# 8613 reload_outsi+2/2 ldi 255,%r26 ;# 8615 reload_outsi+2/2 ldw -244(%r30),%r1 ;# 8916 reload_outsi+2/5 L$1173 comib,=,n 0,%r1,L$0343 ;# 3240 bleu+1 stw %r22,RR'__alnum-$global$(%r2) ;# 3244 reload_outsi+2/6 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3248 reload_outsi+2/5 ldw RR'__ctype-$global$(%r4),%r21 ;# 3260 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3253 addsi3/1 addl %r21,%r22,%r21 ;# 3265 addsi3/1 ldb 0(%r19),%r20 ;# 3255 movqi+1/5 ldb 0(%r21),%r19 ;# 3267 movqi+1/5 extru %r20,31,1,%r20 ;# 3256 andsi3/1 and %r19,%r18,%r19 ;# 3270 andsi3/1 or %r20,%r19,%r20 ;# 3278 xordi3-1 comib,<> 0,%r20,L$1169 ;# 3280 bleu+1 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 L$0343 ldw -236(%r30),%r1 ;# 8919 reload_outsi+2/5 comib,= 0,%r1,L$0344 ;# 3285 bleu+1 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3289 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3290 addsi3/1 ldb 0(%r19),%r19 ;# 3292 movqi+1/5 bb,< %r19,31,L$1169 ;# 3296 bleu+3 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 L$0344 ldw -228(%r30),%r1 ;# 8922 reload_outsi+2/5 comib,=,n 0,%r1,L$0345 ;# 3301 bleu+1 comb,= %r25,%r22,L$1169 ;# 3305 bleu+1 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 comib,= 9,%r22,L$1170 ;# 3307 bleu+1 extru %r19,28,29,%r21 ;# 3332 lshrsi3/2 L$0345 ldw -220(%r30),%r1 ;# 8925 reload_outsi+2/5 comib,= 0,%r1,L$0341 ;# 3312 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3316 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3317 addsi3/1 ldb 0(%r19),%r19 ;# 3319 movqi+1/5 and %r19,%r25,%r19 ;# 3322 andsi3/1 comib,= 0,%r19,L$0341 ;# 3325 bleu+1 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 L$1169 extru %r19,28,29,%r21 ;# 3332 lshrsi3/2 L$1170 addl %r6,%r21,%r21 ;# 3335 addsi3/1 extru %r19,31,3,%r19 ;# 3339 andsi3/1 subi 31,%r19,%r19 ;# 3340 subsi3/2 ldb 0(%r21),%r20 ;# 3343 movqi+1/5 mtsar %r19 ;# 8928 reload_outsi+2/7 vdepi -1,1,%r20 ;# 3348 vdepi_ior stb %r20,0(%r21) ;# 3350 movqi+1/6 L$0341 ldw -212(%r30),%r1 ;# 8931 reload_outsi+2/5 comib,= 0,%r1,L$0348 ;# 3354 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3358 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3359 addsi3/1 ldb 0(%r19),%r19 ;# 3361 movqi+1/5 and %r19,%r18,%r19 ;# 3364 andsi3/1 comib,<> 0,%r19,L$1171 ;# 3367 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$0348 ldw -204(%r30),%r1 ;# 8934 reload_outsi+2/5 comib,= 0,%r1,L$0349 ;# 3372 bleu+1 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3376 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3377 addsi3/1 ldb 0(%r19),%r19 ;# 3379 movqi+1/5 and %r19,%r24,%r19 ;# 3382 andsi3/1 comib,<> 0,%r19,L$1171 ;# 3385 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$0349 ldw -196(%r30),%r1 ;# 8937 reload_outsi+2/5 comib,= 0,%r1,L$0350 ;# 3390 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3394 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3395 addsi3/1 ldb 0(%r19),%r19 ;# 3397 movqi+1/5 and %r19,%r24,%r19 ;# 3400 andsi3/1 comib,<> 0,%r19,L$1171 ;# 3403 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$0350 ldw -188(%r30),%r1 ;# 8940 reload_outsi+2/5 comib,= 0,%r1,L$0346 ;# 3408 bleu+1 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3412 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3413 addsi3/1 ldb 0(%r19),%r19 ;# 3415 movqi+1/5 and %r19,%r18,%r19 ;# 3418 andsi3/1 comib,= 0,%r19,L$0346 ;# 3421 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$1171 extru %r19,28,29,%r21 ;# 3428 lshrsi3/2 addl %r6,%r21,%r21 ;# 3431 addsi3/1 extru %r19,31,3,%r19 ;# 3435 andsi3/1 subi 31,%r19,%r19 ;# 3436 subsi3/2 ldb 0(%r21),%r20 ;# 3439 movqi+1/5 mtsar %r19 ;# 8943 reload_outsi+2/7 vdepi -1,1,%r20 ;# 3444 vdepi_ior stb %r20,0(%r21) ;# 3446 movqi+1/6 L$0346 ldw -180(%r30),%r1 ;# 8946 reload_outsi+2/5 comib,= 0,%r1,L$0353 ;# 3450 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3454 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3455 addsi3/1 ldb 0(%r19),%r19 ;# 3457 movqi+1/5 and %r19,%r31,%r19 ;# 3460 andsi3/1 comib,<> 0,%r19,L$1172 ;# 3463 bleu+1 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$0353 ldw -172(%r30),%r1 ;# 8949 reload_outsi+2/5 comib,= 0,%r1,L$0354 ;# 3468 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3472 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3473 addsi3/1 ldb 0(%r19),%r19 ;# 3475 movqi+1/5 and %r19,%r29,%r19 ;# 3478 andsi3/1 comib,<> 0,%r19,L$1172 ;# 3481 bleu+1 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$0354 comib,= 0,%r13,L$0355 ;# 3486 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3490 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3491 addsi3/1 ldb 0(%r19),%r19 ;# 3493 movqi+1/5 bb,< %r19,31,L$1172 ;# 3497 bleu+3 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$0355 comib,= 0,%r7,L$0339 ;# 3502 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3506 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3507 addsi3/1 ldb 0(%r19),%r19 ;# 3509 movqi+1/5 and %r19,%r28,%r19 ;# 3512 andsi3/1 comib,= 0,%r19,L$0339 ;# 3515 bleu+1 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$1172 extru %r19,28,29,%r21 ;# 3522 lshrsi3/2 addl %r6,%r21,%r21 ;# 3525 addsi3/1 extru %r19,31,3,%r19 ;# 3529 andsi3/1 subi 31,%r19,%r19 ;# 3530 subsi3/2 ldb 0(%r21),%r20 ;# 3533 movqi+1/5 mtsar %r19 ;# 8952 reload_outsi+2/7 vdepi -1,1,%r20 ;# 3538 vdepi_ior stb %r20,0(%r21) ;# 3540 movqi+1/6 L$0339 ldo 1(%r22),%r22 ;# 3546 addsi3/2 comb,>=,n %r26,%r22,L$1173 ;# 3233 bleu+1 ldw -244(%r30),%r1 ;# 8916 reload_outsi+2/5 bl L$0275,%r0 ;# 3559 jump ldi 1,%r13 ;# 3556 reload_outsi+2/2 L$0328 ldi 255,%r19 ;# 8069 reload_outsi+2/2 L$1168 comb,= %r19,%r3,L$0359 ;# 8070 bleu+1 copy %r19,%r21 ;# 8595 reload_outsi+2/1 L$0360 ldo -1(%r3),%r20 ;# 3571 addsi3/2 ldw -296(%r30),%r19 ;# 3583 reload_outsi+2/5 extru %r20,31,8,%r3 ;# 3572 zero_extendqisi2/1 ldo -1(%r19),%r19 ;# 3584 addsi3/2 comb,<> %r21,%r3,L$0360 ;# 3577 bleu+1 stw %r19,-296(%r30) ;# 3588 reload_outsi+2/6 L$0359 ldb 11(%r6),%r19 ;# 3599 movqi+1/5 depi -1,28,1,%r19 ;# 3601 iorsi3+1/2 stb %r19,11(%r6) ;# 3603 movqi+1/6 ldb 7(%r6),%r19 ;# 3606 movqi+1/5 ldi 0,%r13 ;# 3613 reload_outsi+2/2 depi -1,29,1,%r19 ;# 3608 iorsi3+1/2 bl L$0275,%r0 ;# 3618 jump stb %r19,7(%r6) ;# 3610 movqi+1/6 L$0309 ldi 0,%r13 ;# 3624 reload_outsi+2/2 L$1166 extru %r7,21+8-1,8,%r19 ;# 3627 extzv addl %r6,%r19,%r19 ;# 3630 addsi3/1 extru %r7,31,3,%r20 ;# 3633 andsi3/1 L$0948 subi 31,%r20,%r20 ;# 3634 subsi3/2 ldb 0(%r19),%r21 ;# 3637 movqi+1/5 mtsar %r20 ;# 8955 reload_outsi+2/7 vdepi -1,1,%r21 ;# 3642 vdepi_ior bl L$0275,%r0 ;# 3653 jump stb %r21,0(%r19) ;# 3644 movqi+1/6 L$0276 ldb -1(%r6),%r20 ;# 8074 movqi+1/5 extru %r20,31,8,%r19 ;# 8075 zero_extendqisi2/1 comib,= 0,%r19,L$0364 ;# 8076 bleu+1 addl %r19,%r6,%r19 ;# 8079 addsi3/1 ldb -1(%r19),%r19 ;# 8082 zero_extendqisi2/2 comib,<> 0,%r19,L$0364 ;# 8083 bleu+1 ldo -1(%r20),%r19 ;# 8242 addsi3/2 bl L$1183,%r0 ;# 8253 jump stb %r19,-1(%r6) ;# 3688 movqi+1/6 L$0365 ldo -1(%r19),%r19 ;# 3686 addsi3/2 stb %r19,-1(%r6) ;# 3688 movqi+1/6 L$1183 extru %r19,31,8,%r19 ;# 3662 zero_extendqisi2/1 comib,= 0,%r19,L$0364 ;# 3664 bleu+1 addl %r19,%r6,%r19 ;# 3668 addsi3/1 ldb -1(%r19),%r19 ;# 3672 zero_extendqisi2/2 comib,=,n 0,%r19,L$0365 ;# 3674 bleu+1 ldb -1(%r6),%r19 ;# 3683 movqi+1/5 L$0364 ldb -1(%r6),%r19 ;# 3700 zero_extendqisi2/2 bl L$0043,%r0 ;# 3705 jump addl %r6,%r19,%r6 ;# 3701 addsi3/1 L$0368 bb,>=,n %r15,18,L$0076 ;# 3713 movsi-4 bl L$1181,%r0 ;# 3721 jump ldw 24(%r5),%r19 ;# 3861 reload_outsi+2/5 L$0372 bb,>=,n %r15,18,L$0076 ;# 3730 movsi-4 bl,n L$0374,%r0 ;# 3738 jump L$0376 bb,>=,n %r15,20,L$0076 ;# 3747 movsi-4 bl,n L$0378,%r0 ;# 3755 jump L$0380 bb,>=,n %r15,16,L$0076 ;# 3764 movsi-4 bl,n L$0378,%r0 ;# 3772 jump L$0383 and %r15,%r20,%r19 ;# 3779 andsi3/1 comb,= %r20,%r19,L$1174 ;# 3783 bleu+1 ldi -1,%r4 ;# 5074 reload_outsi+2/2 bl,n L$0076,%r0 ;# 3791 jump L$0387 comb,=,n %r16,%r19,L$0903 ;# 3799 bleu+1 ldb 0(%r19),%r7 ;# 3831 zero_extendqisi2/2 ldo 1(%r19),%r19 ;# 3826 addsi3/2 stw %r19,-296(%r30) ;# 3828 reload_outsi+2/6 ldo -39(%r7),%r19 ;# 7446 addsi3/2 addi,uv -86,%r19,%r0 ;# 7447 casesi0 blr,n %r19,%r0 b,n L$0397 L$0817 bl L$0759,%r0 ;# 9437 switch_jump ldw 0(%r5),%r4 ;# 8204 reload_outsi+2/5 L$1069 bl L$0395,%r0 nop ;# 9440 switch_jump L$1070 bl L$0422,%r0 nop ;# 9443 switch_jump L$1071 bl L$0397,%r0 nop ;# 9446 switch_jump L$1072 bl L$0811,%r0 nop ;# 9449 switch_jump L$1073 bl L$0397,%r0 nop ;# 9452 switch_jump L$1074 bl L$0397,%r0 nop ;# 9455 switch_jump L$1075 bl L$0397,%r0 nop ;# 9458 switch_jump L$1076 bl L$0397,%r0 nop ;# 9461 switch_jump L$1077 bl L$0397,%r0 nop ;# 9464 switch_jump L$1078 bl L$0787,%r0 nop ;# 9467 switch_jump L$1079 bl L$0787,%r0 nop ;# 9470 switch_jump L$1080 bl L$0787,%r0 nop ;# 9473 switch_jump L$1081 bl L$0787,%r0 nop ;# 9476 switch_jump L$1082 bl L$0787,%r0 nop ;# 9479 switch_jump L$1083 bl L$0787,%r0 nop ;# 9482 switch_jump L$1084 bl L$0787,%r0 nop ;# 9485 switch_jump L$1085 bl L$0787,%r0 nop ;# 9488 switch_jump L$1086 bl L$0787,%r0 nop ;# 9491 switch_jump L$1087 bl L$0397,%r0 nop ;# 9494 switch_jump L$1088 bl L$0397,%r0 nop ;# 9497 switch_jump L$1089 bl L$0659,%r0 ;# 9500 switch_jump ldw 0(%r5),%r4 ;# 8164 reload_outsi+2/5 L$1090 bl L$0397,%r0 nop ;# 9503 switch_jump L$1091 bl L$0679,%r0 ;# 9506 switch_jump ldw 0(%r5),%r4 ;# 8172 reload_outsi+2/5 L$1092 bl L$0811,%r0 nop ;# 9509 switch_jump L$1093 bl L$0397,%r0 nop ;# 9512 switch_jump L$1094 bl L$0397,%r0 nop ;# 9515 switch_jump L$1095 bl L$0719,%r0 ;# 9518 switch_jump ldw 0(%r5),%r4 ;# 8188 reload_outsi+2/5 L$1096 bl L$0397,%r0 nop ;# 9521 switch_jump L$1097 bl L$0397,%r0 nop ;# 9524 switch_jump L$1098 bl L$0397,%r0 nop ;# 9527 switch_jump L$1099 bl L$0397,%r0 nop ;# 9530 switch_jump L$1100 bl L$0397,%r0 nop ;# 9533 switch_jump L$1101 bl L$0397,%r0 nop ;# 9536 switch_jump L$1102 bl L$0397,%r0 nop ;# 9539 switch_jump L$1103 bl L$0397,%r0 nop ;# 9542 switch_jump L$1104 bl L$0397,%r0 nop ;# 9545 switch_jump L$1105 bl L$0397,%r0 nop ;# 9548 switch_jump L$1106 bl L$0397,%r0 nop ;# 9551 switch_jump L$1107 bl L$0397,%r0 nop ;# 9554 switch_jump L$1108 bl L$0397,%r0 nop ;# 9557 switch_jump L$1109 bl L$0397,%r0 nop ;# 9560 switch_jump L$1110 bl L$0397,%r0 nop ;# 9563 switch_jump L$1111 bl L$0397,%r0 nop ;# 9566 switch_jump L$1112 bl L$0397,%r0 nop ;# 9569 switch_jump L$1113 bl L$0397,%r0 nop ;# 9572 switch_jump L$1114 bl L$0397,%r0 nop ;# 9575 switch_jump L$1115 bl L$0397,%r0 nop ;# 9578 switch_jump L$1116 bl L$0639,%r0 ;# 9581 switch_jump ldw 0(%r5),%r4 ;# 8156 reload_outsi+2/5 L$1117 bl L$0397,%r0 nop ;# 9584 switch_jump L$1118 bl L$0397,%r0 nop ;# 9587 switch_jump L$1119 bl L$0397,%r0 nop ;# 9590 switch_jump L$1120 bl L$0397,%r0 nop ;# 9593 switch_jump L$1121 bl L$0397,%r0 nop ;# 9596 switch_jump L$1122 bl L$0397,%r0 nop ;# 9599 switch_jump L$1123 bl L$0397,%r0 nop ;# 9602 switch_jump L$1124 bl L$0397,%r0 nop ;# 9605 switch_jump L$1125 bl L$0739,%r0 ;# 9608 switch_jump ldw 0(%r5),%r4 ;# 8196 reload_outsi+2/5 L$1126 bl L$0397,%r0 nop ;# 9611 switch_jump L$1127 bl L$0699,%r0 ;# 9614 switch_jump ldw 0(%r5),%r4 ;# 8180 reload_outsi+2/5 L$1128 bl L$0397,%r0 nop ;# 9617 switch_jump L$1129 bl L$0397,%r0 nop ;# 9620 switch_jump L$1130 bl L$0397,%r0 nop ;# 9623 switch_jump L$1131 bl L$0397,%r0 nop ;# 9626 switch_jump L$1132 bl L$0397,%r0 nop ;# 9629 switch_jump L$1133 bl L$0397,%r0 nop ;# 9632 switch_jump L$1134 bl L$0397,%r0 nop ;# 9635 switch_jump L$1135 bl L$0397,%r0 nop ;# 9638 switch_jump L$1136 bl L$0397,%r0 nop ;# 9641 switch_jump L$1137 bl L$0397,%r0 nop ;# 9644 switch_jump L$1138 bl L$0397,%r0 nop ;# 9647 switch_jump L$1139 bl L$0397,%r0 nop ;# 9650 switch_jump L$1140 bl L$0397,%r0 nop ;# 9653 switch_jump L$1141 bl L$0397,%r0 nop ;# 9656 switch_jump L$1142 bl L$0397,%r0 nop ;# 9659 switch_jump L$1143 bl L$0397,%r0 nop ;# 9662 switch_jump L$1144 bl L$0397,%r0 nop ;# 9665 switch_jump L$1145 bl L$0397,%r0 nop ;# 9668 switch_jump L$1146 bl L$0397,%r0 nop ;# 9671 switch_jump L$1147 bl L$0397,%r0 nop ;# 9674 switch_jump L$1148 bl L$0619,%r0 ;# 9677 switch_jump ldw 0(%r5),%r4 ;# 8148 reload_outsi+2/5 L$1149 bl L$0397,%r0 nop ;# 9680 switch_jump L$1150 bl L$0397,%r0 nop ;# 9683 switch_jump L$1151 bl L$0397,%r0 nop ;# 9686 switch_jump L$1152 bl L$0506,%r0 nop ;# 9689 switch_jump L$1153 bl L$0472,%r0 ;# 9692 switch_jump ldil L'33792,%r19 ;# 4724 add_high_const+3 L$1154 bl,n L$0397,%r0 ;# 7450 jump L$0395 bb,<,n %r15,18,L$0397 ;# 3853 bleu+3 ldw 24(%r5),%r19 ;# 3861 reload_outsi+2/5 L$1181 ldo 1(%r19),%r19 ;# 3862 addsi3/2 stw %r19,24(%r5) ;# 3866 reload_outsi+2/6 ldw -304(%r30),%r20 ;# 3871 reload_outsi+2/5 ldw -260(%r30),%r1 ;# 8958 reload_outsi+2/5 ldw -308(%r30),%r19 ;# 3873 reload_outsi+2/5 ldo 1(%r1),%r1 ;# 3868 addsi3/2 comb,<> %r19,%r20,L$0398 ;# 3875 bleu+1 stw %r1,-260(%r30) ;# 8961 reload_outsi+2/6 zdep %r20,28,29,%r25 ;# 3885 ashlsi3+1 sh1addl %r20,%r25,%r25 ;# 3886 ashlsi3-2 ldw -312(%r30),%r26 ;# 3890 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 3894 call_value_internal_symref zdep %r25,29,30,%r25 ;# 3892 ashlsi3+1 comib,= 0,%r28,L$0953 ;# 3903 bleu+1 stw %r28,-312(%r30) ;# 3898 reload_outsi+2/6 ldw -308(%r30),%r19 ;# 3912 reload_outsi+2/5 zdep %r19,30,31,%r19 ;# 3914 ashlsi3+1 stw %r19,-308(%r30) ;# 3916 reload_outsi+2/6 L$0398 ldw -304(%r30),%r20 ;# 3921 reload_outsi+2/5 ldw -312(%r30),%r21 ;# 3923 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 3933 reload_outsi+2/5 sh2addl %r20,%r20,%r20 ;# 3928 ashlsi3-2 sh2addl %r20,%r21,%r21 ;# 3931 ashlsi3-2 sub %r12,%r19,%r19 ;# 3934 subsi3/1 stw %r19,0(%r21) ;# 3936 reload_outsi+2/6 ldw -304(%r30),%r19 ;# 3939 reload_outsi+2/5 ldw -312(%r30),%r20 ;# 3941 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 3946 ashlsi3-2 comib,= 0,%r10,L$0400 ;# 3951 bleu+1 sh2addl %r19,%r20,%r20 ;# 3949 ashlsi3-2 ldw 0(%r5),%r19 ;# 3953 reload_outsi+2/5 sub %r10,%r19,%r19 ;# 3954 subsi3/1 ldo 1(%r19),%r19 ;# 3955 addsi3/2 bl L$0401,%r0 ;# 3958 jump stw %r19,4(%r20) ;# 3957 reload_outsi+2/6 L$0400 stw %r0,4(%r20) ;# 3962 reload_outsi+2/6 L$0401 ldw -304(%r30),%r20 ;# 3966 reload_outsi+2/5 ldw -312(%r30),%r21 ;# 3968 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 3978 reload_outsi+2/5 sh2addl %r20,%r20,%r20 ;# 3973 ashlsi3-2 sh2addl %r20,%r21,%r21 ;# 3976 ashlsi3-2 sub %r6,%r19,%r19 ;# 3979 subsi3/1 stw %r19,12(%r21) ;# 3981 reload_outsi+2/6 ldw -304(%r30),%r19 ;# 3984 reload_outsi+2/5 ldw -312(%r30),%r20 ;# 3986 reload_outsi+2/5 ldw -260(%r30),%r1 ;# 8964 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 3991 ashlsi3-2 sh2addl %r19,%r20,%r20 ;# 3994 ashlsi3-2 ldi 255,%r19 ;# 3999 reload_outsi+2/2 comb,<< %r19,%r1,L$0402 ;# 4001 bleu+1 stw %r1,16(%r20) ;# 3996 reload_outsi+2/6 ldw -304(%r30),%r20 ;# 4005 reload_outsi+2/5 ldw -312(%r30),%r21 ;# 4007 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 4017 reload_outsi+2/5 sh2addl %r20,%r20,%r20 ;# 4012 ashlsi3-2 sh2addl %r20,%r21,%r21 ;# 4015 ashlsi3-2 sub %r6,%r19,%r19 ;# 4018 subsi3/1 ldo 2(%r19),%r19 ;# 4019 addsi3/2 stw %r19,8(%r21) ;# 4021 reload_outsi+2/6 ldw 0(%r5),%r4 ;# 8087 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8090 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8088 subsi3/1 ldo 3(%r19),%r19 ;# 8089 addsi3/2 comb,>>=,n %r20,%r19,L$0407 ;# 8091 bleu+1 ldil L'65536,%r3 ;# 8593 reload_outsi+2/3 L$0408 comb,= %r3,%r20,L$0944 ;# 4049 bleu+1 zdep %r20,30,31,%r19 ;# 4059 ashlsi3+1 comb,>>= %r3,%r19,L$0413 ;# 4067 bleu+1 stw %r19,4(%r5) ;# 4061 reload_outsi+2/6 stw %r3,4(%r5) ;# 4070 reload_outsi+2/6 L$0413 ldw 0(%r5),%r26 ;# 4077 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4081 call_value_internal_symref ldw 4(%r5),%r25 ;# 4079 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4089 bleu+1 stw %r28,0(%r5) ;# 4085 reload_outsi+2/6 comb,= %r28,%r4,L$0406 ;# 4099 bleu+1 sub %r6,%r4,%r19 ;# 4101 subsi3/1 comib,= 0,%r10,L$0416 ;# 4110 bleu+1 addl %r28,%r19,%r6 ;# 4104 addsi3/1 sub %r10,%r4,%r19 ;# 4111 subsi3/1 addl %r28,%r19,%r10 ;# 4114 addsi3/1 L$0416 comib,= 0,%r8,L$0417 ;# 4117 bleu+1 sub %r8,%r4,%r19 ;# 4118 subsi3/1 addl %r28,%r19,%r8 ;# 4121 addsi3/1 L$0417 comib,= 0,%r9,L$0406 ;# 4124 bleu+1 sub %r9,%r4,%r19 ;# 4125 subsi3/1 addl %r28,%r19,%r9 ;# 4128 addsi3/1 L$0406 ldw 0(%r5),%r4 ;# 4029 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4033 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 4030 subsi3/1 ldo 3(%r19),%r19 ;# 4031 addsi3/2 comb,<< %r20,%r19,L$0408 nop ;# 4035 bleu+1 L$0407 ldi 5,%r19 ;# 4150 movqi+1/2 stbs,ma %r19,1(%r6) ;# 4151 movqi+1/6 ldb -257(%r30),%r1 ;# 4156 movqi+1/5 stbs,ma %r1,1(%r6) ;# 8968 movqi+1/6 stbs,ma %r0,1(%r6) ;# 4159 movqi+1/6 L$0402 ldi 0,%r10 ;# 4182 reload_outsi+2/2 ldi 0,%r8 ;# 4185 reload_outsi+2/2 copy %r6,%r12 ;# 4188 reload_outsi+2/1 ldw -304(%r30),%r19 ;# 4174 reload_outsi+2/5 ldi 0,%r9 ;# 4191 reload_outsi+2/2 ldo 1(%r19),%r19 ;# 4175 addsi3/2 bl L$0043,%r0 ;# 4193 jump stw %r19,-304(%r30) ;# 4179 reload_outsi+2/6 L$0422 bb,< %r15,18,L$0397 ;# 4201 bleu+3 ldw -304(%r30),%r19 ;# 4207 reload_outsi+2/5 comib,<>,n 0,%r19,L$0374 ;# 4209 bleu+1 bb,>=,n %r15,14,L$0950 ;# 4215 movsi-4 bl,n L$0397,%r0 ;# 4230 jump L$0374 comib,=,n 0,%r10,L$0427 ;# 4237 bleu+1 ldw 0(%r5),%r4 ;# 8095 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8098 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8096 subsi3/1 ldo 1(%r19),%r19 ;# 8097 addsi3/2 comb,>>=,n %r20,%r19,L$0432 ;# 8099 bleu+1 ldil L'65536,%r3 ;# 8591 reload_outsi+2/3 L$0433 comb,= %r3,%r20,L$0944 ;# 4266 bleu+1 zdep %r20,30,31,%r19 ;# 4276 ashlsi3+1 comb,>>= %r3,%r19,L$0438 ;# 4284 bleu+1 stw %r19,4(%r5) ;# 4278 reload_outsi+2/6 stw %r3,4(%r5) ;# 4287 reload_outsi+2/6 L$0438 ldw 0(%r5),%r26 ;# 4294 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4298 call_value_internal_symref ldw 4(%r5),%r25 ;# 4296 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4306 bleu+1 stw %r28,0(%r5) ;# 4302 reload_outsi+2/6 comb,= %r28,%r4,L$0431 ;# 4316 bleu+1 sub %r6,%r4,%r19 ;# 4318 subsi3/1 addl %r28,%r19,%r6 ;# 4321 addsi3/1 sub %r12,%r4,%r19 ;# 4322 subsi3/1 comib,= 0,%r10,L$0441 ;# 4327 bleu+1 addl %r28,%r19,%r12 ;# 4325 addsi3/1 sub %r10,%r4,%r19 ;# 4328 subsi3/1 addl %r28,%r19,%r10 ;# 4331 addsi3/1 L$0441 comib,= 0,%r8,L$0442 ;# 4334 bleu+1 sub %r8,%r4,%r19 ;# 4335 subsi3/1 addl %r28,%r19,%r8 ;# 4338 addsi3/1 L$0442 comib,= 0,%r9,L$0431 ;# 4341 bleu+1 sub %r9,%r4,%r19 ;# 4342 subsi3/1 addl %r28,%r19,%r9 ;# 4345 addsi3/1 L$0431 ldw 0(%r5),%r4 ;# 4246 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4250 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 4247 subsi3/1 ldo 1(%r19),%r19 ;# 4248 addsi3/2 comb,<< %r20,%r19,L$0433 nop ;# 4252 bleu+1 L$0432 ldi 19,%r19 ;# 4367 movqi+1/2 stbs,ma %r19,1(%r6) ;# 4368 movqi+1/6 uaddcm %r6,%r10,%r24 ;# 4381 adddi3+1 ldi 13,%r26 ;# 4384 reload_outsi+2/2 copy %r10,%r25 ;# 4386 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 4390 call_internal_symref ldo -3(%r24),%r24 ;# 4388 addsi3/2 L$0427 ldw -304(%r30),%r19 ;# 4395 reload_outsi+2/5 comib,<>,n 0,%r19,L$0447 ;# 4397 bleu+1 bb,<,n %r15,14,L$0076 ;# 4403 bleu+3 L$0950 .CALL ARGW0=GR bl free,%r2 ;# 4414 call_internal_symref ldw -312(%r30),%r26 ;# 4412 reload_outsi+2/5 bl L$0867,%r0 ;# 4418 jump ldi 16,%r28 ;# 4416 reload_outsi+2/2 L$0447 ldo -1(%r19),%r19 ;# 4427 addsi3/2 stw %r19,-304(%r30) ;# 4431 reload_outsi+2/6 ldw -312(%r30),%r20 ;# 4436 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 4441 ashlsi3-2 sh2addl %r19,%r20,%r20 ;# 4444 ashlsi3-2 ldw 0(%r5),%r21 ;# 4446 reload_outsi+2/5 ldw 0(%r20),%r19 ;# 4448 reload_outsi+2/5 ldw 4(%r20),%r20 ;# 4464 reload_outsi+2/5 comib,= 0,%r20,L$0450 ;# 4466 bleu+1 addl %r21,%r19,%r12 ;# 4449 addsi3/1 addl %r21,%r20,%r19 ;# 4483 addsi3/1 bl L$0451,%r0 ;# 4485 jump ldo -1(%r19),%r10 ;# 4484 addsi3/2 L$0450 ldi 0,%r10 ;# 4489 reload_outsi+2/2 L$0451 ldw -304(%r30),%r19 ;# 4493 reload_outsi+2/5 ldw -312(%r30),%r20 ;# 4495 reload_outsi+2/5 ldw 0(%r5),%r21 ;# 4505 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 4500 ashlsi3-2 sh2addl %r19,%r20,%r20 ;# 4503 ashlsi3-2 ldw 12(%r20),%r19 ;# 4507 reload_outsi+2/5 ldw 16(%r20),%r7 ;# 4523 reload_outsi+2/5 addl %r21,%r19,%r8 ;# 4508 addsi3/1 ldi 255,%r19 ;# 4529 reload_outsi+2/2 comb,<< %r19,%r7,L$0043 ;# 4531 bleu+1 ldi 0,%r9 ;# 4526 reload_outsi+2/2 ldw 8(%r20),%r19 ;# 4550 reload_outsi+2/5 ldw -260(%r30),%r1 ;# 8971 reload_outsi+2/5 addl %r21,%r19,%r19 ;# 4551 addsi3/1 sub %r1,%r7,%r20 ;# 4557 subsi3/1 stb %r20,0(%r19) ;# 4559 movqi+1/6 ldw 0(%r5),%r4 ;# 8103 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8106 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8104 subsi3/1 ldo 3(%r19),%r19 ;# 8105 addsi3/2 comb,>>=,n %r20,%r19,L$0457 ;# 8107 bleu+1 ldil L'65536,%r3 ;# 8589 reload_outsi+2/3 L$0458 comb,= %r3,%r20,L$0944 ;# 4587 bleu+1 zdep %r20,30,31,%r19 ;# 4597 ashlsi3+1 comb,>>= %r3,%r19,L$0463 ;# 4605 bleu+1 stw %r19,4(%r5) ;# 4599 reload_outsi+2/6 stw %r3,4(%r5) ;# 4608 reload_outsi+2/6 L$0463 ldw 0(%r5),%r26 ;# 4615 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4619 call_value_internal_symref ldw 4(%r5),%r25 ;# 4617 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4627 bleu+1 stw %r28,0(%r5) ;# 4623 reload_outsi+2/6 comb,= %r28,%r4,L$0456 ;# 4637 bleu+1 sub %r6,%r4,%r19 ;# 4639 subsi3/1 addl %r28,%r19,%r6 ;# 4642 addsi3/1 sub %r12,%r4,%r19 ;# 4643 subsi3/1 comib,= 0,%r10,L$0466 ;# 4648 bleu+1 addl %r28,%r19,%r12 ;# 4646 addsi3/1 sub %r10,%r4,%r19 ;# 4649 subsi3/1 addl %r28,%r19,%r10 ;# 4652 addsi3/1 L$0466 comib,= 0,%r8,L$0467 ;# 4655 bleu+1 sub %r8,%r4,%r19 ;# 4656 subsi3/1 addl %r28,%r19,%r8 ;# 4659 addsi3/1 L$0467 comib,= 0,%r9,L$0456 ;# 4662 bleu+1 sub %r9,%r4,%r19 ;# 4663 subsi3/1 addl %r28,%r19,%r9 ;# 4666 addsi3/1 L$0456 ldw 0(%r5),%r4 ;# 4567 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4571 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 4568 subsi3/1 ldo 3(%r19),%r19 ;# 4569 addsi3/2 comb,<< %r20,%r19,L$0458 nop ;# 4573 bleu+1 L$0457 ldi 6,%r19 ;# 4688 movqi+1/2 stbs,ma %r19,1(%r6) ;# 4689 movqi+1/6 stbs,ma %r7,1(%r6) ;# 4694 movqi+1/6 ldw -260(%r30),%r1 ;# 8974 reload_outsi+2/5 sub %r1,%r7,%r19 ;# 4700 subsi3/1 bl L$0043,%r0 ;# 4720 jump stbs,ma %r19,1(%r6) ;# 4702 movqi+1/6 L$0472 ldo R'33792(%r19),%r19 ;# 4725 movhi-2 and %r15,%r19,%r19 ;# 4726 andsi3/1 comib,<>,n 0,%r19,L$0397 ;# 4728 bleu+1 L$0378 bb,<,n %r15,21,L$0076 ;# 4739 bleu+3 ldw 0(%r5),%r3 ;# 8111 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8114 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8112 subsi3/1 ldo 3(%r19),%r19 ;# 8113 addsi3/2 comb,>>=,n %r20,%r19,L$0476 ;# 8115 bleu+1 ldil L'65536,%r4 ;# 8587 reload_outsi+2/3 L$0477 comb,= %r4,%r20,L$0944 ;# 4768 bleu+1 zdep %r20,30,31,%r19 ;# 4778 ashlsi3+1 comb,>>= %r4,%r19,L$0482 ;# 4786 bleu+1 stw %r19,4(%r5) ;# 4780 reload_outsi+2/6 stw %r4,4(%r5) ;# 4789 reload_outsi+2/6 L$0482 ldw 0(%r5),%r26 ;# 4796 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4800 call_value_internal_symref ldw 4(%r5),%r25 ;# 4798 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4808 bleu+1 stw %r28,0(%r5) ;# 4804 reload_outsi+2/6 comb,= %r28,%r3,L$0475 ;# 4818 bleu+1 sub %r6,%r3,%r19 ;# 4820 subsi3/1 addl %r28,%r19,%r6 ;# 4823 addsi3/1 sub %r12,%r3,%r19 ;# 4824 subsi3/1 comib,= 0,%r10,L$0485 ;# 4829 bleu+1 addl %r28,%r19,%r12 ;# 4827 addsi3/1 sub %r10,%r3,%r19 ;# 4830 subsi3/1 addl %r28,%r19,%r10 ;# 4833 addsi3/1 L$0485 comib,= 0,%r8,L$0486 ;# 4836 bleu+1 sub %r8,%r3,%r19 ;# 4837 subsi3/1 addl %r28,%r19,%r8 ;# 4840 addsi3/1 L$0486 comib,= 0,%r9,L$0475 ;# 4843 bleu+1 sub %r9,%r3,%r19 ;# 4844 subsi3/1 addl %r28,%r19,%r9 ;# 4847 addsi3/1 L$0475 ldw 0(%r5),%r3 ;# 4748 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4752 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 4749 subsi3/1 ldo 3(%r19),%r19 ;# 4750 addsi3/2 comb,<< %r20,%r19,L$0477 nop ;# 4754 bleu+1 L$0476 ldi 14,%r26 ;# 4873 reload_outsi+2/2 copy %r12,%r25 ;# 4875 reload_outsi+2/1 sub %r6,%r25,%r24 ;# 4870 subsi3/1 ldo 3(%r24),%r24 ;# 4877 addsi3/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 4881 call_internal_symref copy %r6,%r23 ;# 4879 reload_outsi+2/1 ldi 0,%r9 ;# 4884 reload_outsi+2/2 comib,= 0,%r10,L$0490 ;# 4889 bleu+1 ldo 3(%r6),%r6 ;# 4886 addsi3/2 ldi 13,%r26 ;# 4894 reload_outsi+2/2 copy %r10,%r25 ;# 4896 reload_outsi+2/1 sub %r6,%r25,%r24 ;# 4891 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 4900 call_internal_symref ldo -3(%r24),%r24 ;# 4898 addsi3/2 L$0490 ldw 0(%r5),%r3 ;# 8119 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8122 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8120 subsi3/1 ldo 3(%r19),%r19 ;# 8121 addsi3/2 comb,>>= %r20,%r19,L$0492 ;# 8123 bleu+1 copy %r6,%r10 ;# 4904 reload_outsi+2/1 ldil L'65536,%r4 ;# 8585 reload_outsi+2/3 L$0493 comb,= %r4,%r20,L$0944 ;# 4929 bleu+1 zdep %r20,30,31,%r19 ;# 4939 ashlsi3+1 comb,>>= %r4,%r19,L$0498 ;# 4947 bleu+1 stw %r19,4(%r5) ;# 4941 reload_outsi+2/6 stw %r4,4(%r5) ;# 4950 reload_outsi+2/6 L$0498 ldw 0(%r5),%r26 ;# 4957 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4961 call_value_internal_symref ldw 4(%r5),%r25 ;# 4959 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4969 bleu+1 stw %r28,0(%r5) ;# 4965 reload_outsi+2/6 comb,= %r28,%r3,L$0491 ;# 4979 bleu+1 sub %r6,%r3,%r19 ;# 4981 subsi3/1 comib,= 0,%r10,L$0501 ;# 4990 bleu+1 addl %r28,%r19,%r6 ;# 4984 addsi3/1 sub %r10,%r3,%r19 ;# 4991 subsi3/1 addl %r28,%r19,%r10 ;# 4994 addsi3/1 L$0501 comib,= 0,%r8,L$0502 ;# 4997 bleu+1 sub %r8,%r3,%r19 ;# 4998 subsi3/1 addl %r28,%r19,%r8 ;# 5001 addsi3/1 L$0502 comib,= 0,%r9,L$0491 ;# 5004 bleu+1 sub %r9,%r3,%r19 ;# 5005 subsi3/1 addl %r28,%r19,%r9 ;# 5008 addsi3/1 L$0491 ldw 0(%r5),%r3 ;# 4909 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4913 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 4910 subsi3/1 ldo 3(%r19),%r19 ;# 4911 addsi3/2 comb,<< %r20,%r19,L$0493 nop ;# 4915 bleu+1 L$0492 ldo 3(%r6),%r6 ;# 5030 addsi3/2 ldi 0,%r8 ;# 5033 reload_outsi+2/2 bl L$0043,%r0 ;# 5038 jump copy %r6,%r12 ;# 5036 reload_outsi+2/1 L$0506 bb,>= %r15,22,L$0397 ;# 5046 movsi-4 ldi 4608,%r20 ;# 5048 reload_outsi+2/2 and %r15,%r20,%r19 ;# 5049 andsi3/1 comb,= %r20,%r19,L$0397 ;# 5053 bleu+1 ldw -296(%r30),%r20 ;# 5055 reload_outsi+2/5 ldw -276(%r30),%r1 ;# 8977 reload_outsi+2/5 ldo -2(%r20),%r19 ;# 5056 addsi3/2 comb,<> %r1,%r19,L$1175 ;# 5058 bleu+1 ldi -1,%r4 ;# 5074 reload_outsi+2/2 comb,=,n %r16,%r20,L$0397 ;# 5062 bleu+1 L$1174 ldw -296(%r30),%r20 ;# 5079 reload_outsi+2/5 L$1175 copy %r4,%r11 ;# 5076 reload_outsi+2/1 comb,<> %r16,%r20,L$0517 ;# 5085 bleu+1 ldo -1(%r20),%r23 ;# 5080 addsi3/2 bb,>=,n %r15,19,L$0915 ;# 5092 movsi-4 bl L$1182,%r0 ;# 5107 jump stw %r23,-296(%r30) ;# 5968 reload_outsi+2/6 L$0517 ldo 1(%r20),%r19 ;# 5134 addsi3/2 stw %r19,-296(%r30) ;# 5136 reload_outsi+2/6 comib,= 0,%r14,L$0515 ;# 5143 bleu+1 ldb 0(%r20),%r7 ;# 5139 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5144 addsi3/1 ldb 0(%r19),%r7 ;# 5147 zero_extendqisi2/2 L$0515 addil LR'__ctype-$global$,%r27 ;# 8257 pic2_lo_sum+1 ldw RR'__ctype-$global$(%r1),%r21 ;# 8259 reload_outsi+2/5 addl %r21,%r7,%r19 ;# 8260 addsi3/1 ldb 0(%r19),%r19 ;# 8261 movqi+1/5 bb,>= %r19,29,L$0513 ;# 8265 movsi-4 ldi 4,%r20 ;# 8263 reload_outsi+2/2 copy %r20,%r22 ;# 8583 reload_outsi+2/1 L$0522 comiclr,< -1,%r11,%r0 ;# 8128 movsicc+1/1 ldi 0,%r11 sh2addl %r11,%r11,%r19 ;# 5188 ashlsi3-2 sh1addl %r19,%r7,%r19 ;# 5191 ashlsi3-2 ldw -296(%r30),%r20 ;# 5194 reload_outsi+2/5 comb,= %r16,%r20,L$0513 ;# 5196 bleu+1 ldo -48(%r19),%r11 ;# 5192 addsi3/2 ldo 1(%r20),%r19 ;# 5215 addsi3/2 stw %r19,-296(%r30) ;# 5217 reload_outsi+2/6 comib,= 0,%r14,L$0520 ;# 5224 bleu+1 ldb 0(%r20),%r7 ;# 5220 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5225 addsi3/1 ldb 0(%r19),%r7 ;# 5228 zero_extendqisi2/2 L$0520 addl %r21,%r7,%r19 ;# 5166 addsi3/1 ldb 0(%r19),%r19 ;# 5168 movqi+1/5 and %r19,%r22,%r19 ;# 5172 andsi3/1 comib,<> 0,%r19,L$0522 nop ;# 5174 bleu+1 L$0513 ldi 44,%r19 ;# 5252 reload_outsi+2/2 comb,<> %r19,%r7,L$0532 ;# 5254 bleu+1 ldw -296(%r30),%r20 ;# 5259 reload_outsi+2/5 comb,= %r16,%r20,L$0533 ;# 5261 bleu+1 ldo 1(%r20),%r19 ;# 5278 addsi3/2 stw %r19,-296(%r30) ;# 5280 reload_outsi+2/6 comib,= 0,%r14,L$0535 ;# 5287 bleu+1 ldb 0(%r20),%r7 ;# 5283 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5288 addsi3/1 ldb 0(%r19),%r7 ;# 5291 zero_extendqisi2/2 L$0535 addil LR'__ctype-$global$,%r27 ;# 8269 pic2_lo_sum+1 ldw RR'__ctype-$global$(%r1),%r21 ;# 8271 reload_outsi+2/5 addl %r21,%r7,%r19 ;# 8272 addsi3/1 ldb 0(%r19),%r19 ;# 8273 movqi+1/5 bb,>= %r19,29,L$0533 ;# 8277 movsi-4 ldi 4,%r20 ;# 8275 reload_outsi+2/2 copy %r20,%r22 ;# 8578 reload_outsi+2/1 L$0542 comiclr,< -1,%r4,%r0 ;# 8132 movsicc+1/1 ldi 0,%r4 sh2addl %r4,%r4,%r19 ;# 5332 ashlsi3-2 sh1addl %r19,%r7,%r19 ;# 5335 ashlsi3-2 ldw -296(%r30),%r20 ;# 5338 reload_outsi+2/5 comb,= %r16,%r20,L$0533 ;# 5340 bleu+1 ldo -48(%r19),%r4 ;# 5336 addsi3/2 ldo 1(%r20),%r19 ;# 5359 addsi3/2 stw %r19,-296(%r30) ;# 5361 reload_outsi+2/6 comib,= 0,%r14,L$0540 ;# 5368 bleu+1 ldb 0(%r20),%r7 ;# 5364 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5369 addsi3/1 ldb 0(%r19),%r7 ;# 5372 zero_extendqisi2/2 L$0540 addl %r21,%r7,%r19 ;# 5310 addsi3/1 ldb 0(%r19),%r19 ;# 5312 movqi+1/5 and %r19,%r22,%r19 ;# 5316 andsi3/1 comib,<> 0,%r19,L$0542 nop ;# 5318 bleu+1 L$0533 comiclr,< -1,%r4,%r0 ;# 8136 beq-1/4 zdepi -1,31,15,%r4 bl,n L$0553,%r0 ;# 5401 jump L$0532 copy %r11,%r4 ;# 5406 reload_outsi+2/1 L$0553 comib,> 0,%r11,L$0951 ;# 5410 bleu+1 zdepi -1,31,15,%r19 ;# 5412 reload_outsi+2/4 comb,<,n %r19,%r4,L$0951 ;# 5414 bleu+1 comb,<,n %r4,%r11,L$0951 ;# 5416 bleu+1 bb,< %r15,19,L$1176 ;# 5451 bleu+3 ldi 125,%r19 ;# 5514 reload_outsi+2/2 ldi 92,%r19 ;# 5455 reload_outsi+2/2 comb,<> %r19,%r7,L$0915 ;# 5457 bleu+1 ldw -296(%r30),%r20 ;# 5473 reload_outsi+2/5 comb,= %r16,%r20,L$0922 ;# 5475 bleu+1 ldo 1(%r20),%r19 ;# 5484 addsi3/2 stw %r19,-296(%r30) ;# 5486 reload_outsi+2/6 comib,= 0,%r14,L$0558 ;# 5493 bleu+1 ldb 0(%r20),%r7 ;# 5489 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5494 addsi3/1 ldb 0(%r19),%r7 ;# 5497 zero_extendqisi2/2 L$0558 ldi 125,%r19 ;# 5514 reload_outsi+2/2 L$1176 comb,=,n %r19,%r7,L$0566 ;# 5516 bleu+1 L$0951 bb,<,n %r15,19,L$0511 ;# 5523 bleu+3 .CALL ARGW0=GR bl free,%r2 ;# 5534 call_internal_symref ldw -312(%r30),%r26 ;# 5532 reload_outsi+2/5 bl L$0867,%r0 ;# 5538 jump ldi 10,%r28 ;# 5536 reload_outsi+2/2 L$0566 comib,<>,n 0,%r8,L$0569 ;# 5545 bleu+1 bb,<,n %r15,26,L$0917 ;# 5552 bleu+3 bb,>=,n %r15,27,L$0511 ;# 5571 movsi-4 copy %r6,%r8 ;# 5574 reload_outsi+2/1 L$0569 comib,<> 0,%r4,L$0574 ;# 5587 bleu+1 ldi 10,%r13 ;# 8980 reload_outsi+2/2 ldw 0(%r5),%r3 ;# 8139 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8142 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8140 subsi3/1 ldo 3(%r19),%r19 ;# 8141 addsi3/2 comb,>>=,n %r20,%r19,L$0576 ;# 8143 bleu+1 ldil L'65536,%r4 ;# 8573 reload_outsi+2/3 L$0577 comb,= %r4,%r20,L$0944 ;# 5613 bleu+1 zdep %r20,30,31,%r19 ;# 5623 ashlsi3+1 comb,>>= %r4,%r19,L$0582 ;# 5631 bleu+1 stw %r19,4(%r5) ;# 5625 reload_outsi+2/6 stw %r4,4(%r5) ;# 5634 reload_outsi+2/6 L$0582 ldw 0(%r5),%r26 ;# 5641 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 5645 call_value_internal_symref ldw 4(%r5),%r25 ;# 5643 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 5653 bleu+1 stw %r28,0(%r5) ;# 5649 reload_outsi+2/6 comb,= %r28,%r3,L$0575 ;# 5663 bleu+1 sub %r6,%r3,%r19 ;# 5665 subsi3/1 addl %r28,%r19,%r6 ;# 5668 addsi3/1 sub %r12,%r3,%r19 ;# 5669 subsi3/1 comib,= 0,%r10,L$0585 ;# 5674 bleu+1 addl %r28,%r19,%r12 ;# 5672 addsi3/1 sub %r10,%r3,%r19 ;# 5675 subsi3/1 addl %r28,%r19,%r10 ;# 5678 addsi3/1 L$0585 comib,= 0,%r8,L$0586 ;# 5681 bleu+1 sub %r8,%r3,%r19 ;# 5682 subsi3/1 addl %r28,%r19,%r8 ;# 5685 addsi3/1 L$0586 comib,= 0,%r9,L$0575 ;# 5688 bleu+1 sub %r9,%r3,%r19 ;# 5689 subsi3/1 addl %r28,%r19,%r9 ;# 5692 addsi3/1 L$0575 ldw 0(%r5),%r3 ;# 5593 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 5597 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 5594 subsi3/1 ldo 3(%r19),%r19 ;# 5595 addsi3/2 comb,<< %r20,%r19,L$0577 nop ;# 5599 bleu+1 L$0576 ldi 12,%r26 ;# 5718 reload_outsi+2/2 copy %r8,%r25 ;# 5720 reload_outsi+2/1 sub %r6,%r8,%r24 ;# 5722 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 5726 call_internal_symref copy %r6,%r23 ;# 5724 reload_outsi+2/1 bl L$0590,%r0 ;# 5730 jump ldo 3(%r6),%r6 ;# 5728 addsi3/2 L$0574 comiclr,> 2,%r4,%r0 ;# 8282 beq-1/2 ldi 20,%r13 ldw 0(%r5),%r3 ;# 8285 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8288 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8286 subsi3/1 addl %r19,%r13,%r19 ;# 8287 addsi3/1 comb,>>=,n %r20,%r19,L$0868 ;# 8289 bleu+1 ldil L'65536,%r7 ;# 8571 reload_outsi+2/3 L$0595 comb,= %r7,%r20,L$0944 ;# 5769 bleu+1 zdep %r20,30,31,%r19 ;# 5779 ashlsi3+1 comb,>>= %r7,%r19,L$0600 ;# 5787 bleu+1 stw %r19,4(%r5) ;# 5781 reload_outsi+2/6 stw %r7,4(%r5) ;# 5790 reload_outsi+2/6 L$0600 ldw 0(%r5),%r26 ;# 5797 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 5801 call_value_internal_symref ldw 4(%r5),%r25 ;# 5799 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 5809 bleu+1 stw %r28,0(%r5) ;# 5805 reload_outsi+2/6 comb,= %r28,%r3,L$0593 ;# 5819 bleu+1 sub %r6,%r3,%r19 ;# 5821 subsi3/1 addl %r28,%r19,%r6 ;# 5824 addsi3/1 sub %r12,%r3,%r19 ;# 5825 subsi3/1 comib,= 0,%r10,L$0603 ;# 5830 bleu+1 addl %r28,%r19,%r12 ;# 5828 addsi3/1 sub %r10,%r3,%r19 ;# 5831 subsi3/1 addl %r28,%r19,%r10 ;# 5834 addsi3/1 L$0603 comib,= 0,%r8,L$0604 ;# 5837 bleu+1 sub %r8,%r3,%r19 ;# 5838 subsi3/1 addl %r28,%r19,%r8 ;# 5841 addsi3/1 L$0604 comib,= 0,%r9,L$0593 ;# 5844 bleu+1 sub %r9,%r3,%r19 ;# 5845 subsi3/1 addl %r28,%r19,%r9 ;# 5848 addsi3/1 L$0593 ldw 0(%r5),%r3 ;# 5749 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 5753 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 5750 subsi3/1 addl %r19,%r13,%r19 ;# 5751 addsi3/1 comb,<< %r20,%r19,L$0595 nop ;# 5755 bleu+1 L$0868 comib,>= 1,%r4,L$0608 ;# 5872 bleu+1 ldo 5(%r6),%r19 ;# 5870 addsi3/2 sub %r19,%r8,%r19 ;# 5874 subsi3/1 bl L$0609,%r0 ;# 5876 jump ldo 2(%r19),%r24 ;# 5875 addsi3/2 L$0608 sub %r19,%r8,%r19 ;# 5879 subsi3/1 ldo -3(%r19),%r24 ;# 5880 addsi3/2 L$0609 ldi 20,%r26 ;# 5885 reload_outsi+2/2 copy %r8,%r25 ;# 5887 reload_outsi+2/1 copy %r11,%r23 ;# 5891 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op2,%r2 ;# 5893 call_internal_symref stw %r6,-52(%r30) ;# 5883 reload_outsi+2/6 ldo 5(%r6),%r6 ;# 5895 addsi3/2 ldi 22,%r26 ;# 5900 reload_outsi+2/2 copy %r8,%r25 ;# 5902 reload_outsi+2/1 ldi 5,%r24 ;# 5904 reload_outsi+2/2 copy %r11,%r23 ;# 5906 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op2,%r2 ;# 5908 call_internal_symref stw %r6,-52(%r30) ;# 5898 reload_outsi+2/6 comib,>= 1,%r4,L$0590 ;# 5913 bleu+1 ldo 5(%r6),%r6 ;# 5910 addsi3/2 ldi 21,%r26 ;# 5921 reload_outsi+2/2 copy %r6,%r25 ;# 5923 reload_outsi+2/1 sub %r8,%r6,%r24 ;# 5917 subsi3/1 ldo 2(%r24),%r24 ;# 5925 addsi3/2 ldo -1(%r4),%r4 ;# 5919 addsi3/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl store_op2,%r2 ;# 5929 call_internal_symref copy %r4,%r23 ;# 5927 reload_outsi+2/1 ldo 5(%r6),%r6 ;# 5931 addsi3/2 stw %r6,-52(%r30) ;# 5936 reload_outsi+2/6 ldi 22,%r26 ;# 5938 reload_outsi+2/2 copy %r8,%r25 ;# 5940 reload_outsi+2/1 sub %r6,%r8,%r24 ;# 5942 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op2,%r2 ;# 5946 call_internal_symref copy %r4,%r23 ;# 5944 reload_outsi+2/1 ldo 5(%r6),%r6 ;# 5948 addsi3/2 L$0590 bl L$0043,%r0 ;# 5963 jump ldi 0,%r9 ;# 5956 reload_outsi+2/2 L$0511 stw %r23,-296(%r30) ;# 5968 reload_outsi+2/6 L$1182 ldw -296(%r30),%r20 ;# 5977 reload_outsi+2/5 comb,= %r16,%r20,L$0922 ;# 5979 bleu+1 ldo 1(%r20),%r21 ;# 5988 addsi3/2 ldb 0(%r20),%r20 ;# 5992 movqi+1/5 stw %r21,-296(%r30) ;# 5990 reload_outsi+2/6 comib,= 0,%r14,L$0612 ;# 5997 bleu+1 extru %r20,31,8,%r7 ;# 5993 zero_extendqisi2/1 addl %r14,%r7,%r19 ;# 5998 addsi3/1 ldb 0(%r19),%r7 ;# 6001 zero_extendqisi2/2 L$0612 bb,< %r15,19,L$0076 ;# 6019 bleu+3 ldw -276(%r30),%r1 ;# 8983 reload_outsi+2/5 comb,>>= %r1,%r21,L$0076 ;# 6025 bleu+1 extrs %r20,31,8,%r20 ;# 6030 extendqisi2 ldi 92,%r19 ;# 6032 reload_outsi+2/2 comb,=,n %r19,%r20,L$0397 ;# 6034 bleu+1 bl,n L$0076,%r0 ;# 6042 jump L$0619 ldw 4(%r5),%r20 ;# 8151 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8149 subsi3/1 ldo 1(%r19),%r19 ;# 8150 addsi3/2 comb,>>= %r20,%r19,L$0624 ;# 8152 bleu+1 copy %r6,%r8 ;# 6047 reload_outsi+2/1 ldil L'65536,%r3 ;# 8569 reload_outsi+2/3 L$0625 comb,= %r3,%r20,L$0944 ;# 6075 bleu+1 zdep %r20,30,31,%r19 ;# 6085 ashlsi3+1 comb,>>= %r3,%r19,L$0630 ;# 6093 bleu+1 stw %r19,4(%r5) ;# 6087 reload_outsi+2/6 stw %r3,4(%r5) ;# 6096 reload_outsi+2/6 L$0630 ldw 0(%r5),%r26 ;# 6103 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6107 call_value_internal_symref ldw 4(%r5),%r25 ;# 6105 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6115 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6111 reload_outsi+2/6 comb,= %r28,%r4,L$0623 ;# 6125 bleu+1 sub %r6,%r4,%r19 ;# 6127 subsi3/1 addl %r28,%r19,%r6 ;# 6130 addsi3/1 sub %r12,%r4,%r19 ;# 6131 subsi3/1 comib,= 0,%r10,L$0633 ;# 6136 bleu+1 addl %r28,%r19,%r12 ;# 6134 addsi3/1 sub %r10,%r4,%r19 ;# 6137 subsi3/1 addl %r28,%r19,%r10 ;# 6140 addsi3/1 L$0633 comib,= 0,%r8,L$0634 ;# 6143 bleu+1 sub %r8,%r4,%r19 ;# 6144 subsi3/1 addl %r28,%r19,%r8 ;# 6147 addsi3/1 L$0634 comib,= 0,%r9,L$0623 ;# 6150 bleu+1 sub %r9,%r4,%r19 ;# 6151 subsi3/1 addl %r28,%r19,%r9 ;# 6154 addsi3/1 L$0623 ldw 0(%r5),%r4 ;# 6055 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6059 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6056 subsi3/1 ldo 1(%r19),%r19 ;# 6057 addsi3/2 comb,<< %r20,%r19,L$0625 nop ;# 6061 bleu+1 L$0624 ldi 23,%r19 ;# 6176 movqi+1/2 bl L$0043,%r0 ;# 6189 jump stbs,ma %r19,1(%r6) ;# 6177 movqi+1/6 L$0639 ldw 4(%r5),%r20 ;# 8159 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8157 subsi3/1 ldo 1(%r19),%r19 ;# 8158 addsi3/2 comb,>>= %r20,%r19,L$0644 ;# 8160 bleu+1 copy %r6,%r8 ;# 6194 reload_outsi+2/1 ldil L'65536,%r3 ;# 8567 reload_outsi+2/3 L$0645 comb,= %r3,%r20,L$0944 ;# 6222 bleu+1 zdep %r20,30,31,%r19 ;# 6232 ashlsi3+1 comb,>>= %r3,%r19,L$0650 ;# 6240 bleu+1 stw %r19,4(%r5) ;# 6234 reload_outsi+2/6 stw %r3,4(%r5) ;# 6243 reload_outsi+2/6 L$0650 ldw 0(%r5),%r26 ;# 6250 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6254 call_value_internal_symref ldw 4(%r5),%r25 ;# 6252 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6262 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6258 reload_outsi+2/6 comb,= %r28,%r4,L$0643 ;# 6272 bleu+1 sub %r6,%r4,%r19 ;# 6274 subsi3/1 addl %r28,%r19,%r6 ;# 6277 addsi3/1 sub %r12,%r4,%r19 ;# 6278 subsi3/1 comib,= 0,%r10,L$0653 ;# 6283 bleu+1 addl %r28,%r19,%r12 ;# 6281 addsi3/1 sub %r10,%r4,%r19 ;# 6284 subsi3/1 addl %r28,%r19,%r10 ;# 6287 addsi3/1 L$0653 comib,= 0,%r8,L$0654 ;# 6290 bleu+1 sub %r8,%r4,%r19 ;# 6291 subsi3/1 addl %r28,%r19,%r8 ;# 6294 addsi3/1 L$0654 comib,= 0,%r9,L$0643 ;# 6297 bleu+1 sub %r9,%r4,%r19 ;# 6298 subsi3/1 addl %r28,%r19,%r9 ;# 6301 addsi3/1 L$0643 ldw 0(%r5),%r4 ;# 6202 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6206 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6203 subsi3/1 ldo 1(%r19),%r19 ;# 6204 addsi3/2 comb,<< %r20,%r19,L$0645 nop ;# 6208 bleu+1 L$0644 ldi 24,%r19 ;# 6323 movqi+1/2 bl L$0043,%r0 ;# 6336 jump stbs,ma %r19,1(%r6) ;# 6324 movqi+1/6 L$0659 ldw 4(%r5),%r20 ;# 8167 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8165 subsi3/1 ldo 1(%r19),%r19 ;# 8166 addsi3/2 comb,>>=,n %r20,%r19,L$0664 ;# 8168 bleu+1 ldil L'65536,%r3 ;# 8565 reload_outsi+2/3 L$0665 comb,= %r3,%r20,L$0944 ;# 6366 bleu+1 zdep %r20,30,31,%r19 ;# 6376 ashlsi3+1 comb,>>= %r3,%r19,L$0670 ;# 6384 bleu+1 stw %r19,4(%r5) ;# 6378 reload_outsi+2/6 stw %r3,4(%r5) ;# 6387 reload_outsi+2/6 L$0670 ldw 0(%r5),%r26 ;# 6394 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6398 call_value_internal_symref ldw 4(%r5),%r25 ;# 6396 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6406 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6402 reload_outsi+2/6 comb,= %r28,%r4,L$0663 ;# 6416 bleu+1 sub %r6,%r4,%r19 ;# 6418 subsi3/1 addl %r28,%r19,%r6 ;# 6421 addsi3/1 sub %r12,%r4,%r19 ;# 6422 subsi3/1 comib,= 0,%r10,L$0673 ;# 6427 bleu+1 addl %r28,%r19,%r12 ;# 6425 addsi3/1 sub %r10,%r4,%r19 ;# 6428 subsi3/1 addl %r28,%r19,%r10 ;# 6431 addsi3/1 L$0673 comib,= 0,%r8,L$0674 ;# 6434 bleu+1 sub %r8,%r4,%r19 ;# 6435 subsi3/1 addl %r28,%r19,%r8 ;# 6438 addsi3/1 L$0674 comib,= 0,%r9,L$0663 ;# 6441 bleu+1 sub %r9,%r4,%r19 ;# 6442 subsi3/1 addl %r28,%r19,%r9 ;# 6445 addsi3/1 L$0663 ldw 0(%r5),%r4 ;# 6346 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6350 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6347 subsi3/1 ldo 1(%r19),%r19 ;# 6348 addsi3/2 comb,<< %r20,%r19,L$0665 nop ;# 6352 bleu+1 L$0664 ldi 25,%r19 ;# 6467 movqi+1/2 bl L$0043,%r0 ;# 6480 jump stbs,ma %r19,1(%r6) ;# 6468 movqi+1/6 L$0679 ldw 4(%r5),%r20 ;# 8175 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8173 subsi3/1 ldo 1(%r19),%r19 ;# 8174 addsi3/2 comb,>>=,n %r20,%r19,L$0684 ;# 8176 bleu+1 ldil L'65536,%r3 ;# 8563 reload_outsi+2/3 L$0685 comb,= %r3,%r20,L$0944 ;# 6510 bleu+1 zdep %r20,30,31,%r19 ;# 6520 ashlsi3+1 comb,>>= %r3,%r19,L$0690 ;# 6528 bleu+1 stw %r19,4(%r5) ;# 6522 reload_outsi+2/6 stw %r3,4(%r5) ;# 6531 reload_outsi+2/6 L$0690 ldw 0(%r5),%r26 ;# 6538 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6542 call_value_internal_symref ldw 4(%r5),%r25 ;# 6540 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6550 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6546 reload_outsi+2/6 comb,= %r28,%r4,L$0683 ;# 6560 bleu+1 sub %r6,%r4,%r19 ;# 6562 subsi3/1 addl %r28,%r19,%r6 ;# 6565 addsi3/1 sub %r12,%r4,%r19 ;# 6566 subsi3/1 comib,= 0,%r10,L$0693 ;# 6571 bleu+1 addl %r28,%r19,%r12 ;# 6569 addsi3/1 sub %r10,%r4,%r19 ;# 6572 subsi3/1 addl %r28,%r19,%r10 ;# 6575 addsi3/1 L$0693 comib,= 0,%r8,L$0694 ;# 6578 bleu+1 sub %r8,%r4,%r19 ;# 6579 subsi3/1 addl %r28,%r19,%r8 ;# 6582 addsi3/1 L$0694 comib,= 0,%r9,L$0683 ;# 6585 bleu+1 sub %r9,%r4,%r19 ;# 6586 subsi3/1 addl %r28,%r19,%r9 ;# 6589 addsi3/1 L$0683 ldw 0(%r5),%r4 ;# 6490 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6494 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6491 subsi3/1 ldo 1(%r19),%r19 ;# 6492 addsi3/2 comb,<< %r20,%r19,L$0685 nop ;# 6496 bleu+1 L$0684 ldi 26,%r19 ;# 6611 movqi+1/2 bl L$0043,%r0 ;# 6624 jump stbs,ma %r19,1(%r6) ;# 6612 movqi+1/6 L$0699 ldw 4(%r5),%r20 ;# 8183 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8181 subsi3/1 ldo 1(%r19),%r19 ;# 8182 addsi3/2 comb,>>=,n %r20,%r19,L$0704 ;# 8184 bleu+1 ldil L'65536,%r3 ;# 8561 reload_outsi+2/3 L$0705 comb,= %r3,%r20,L$0944 ;# 6654 bleu+1 zdep %r20,30,31,%r19 ;# 6664 ashlsi3+1 comb,>>= %r3,%r19,L$0710 ;# 6672 bleu+1 stw %r19,4(%r5) ;# 6666 reload_outsi+2/6 stw %r3,4(%r5) ;# 6675 reload_outsi+2/6 L$0710 ldw 0(%r5),%r26 ;# 6682 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6686 call_value_internal_symref ldw 4(%r5),%r25 ;# 6684 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6694 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6690 reload_outsi+2/6 comb,= %r28,%r4,L$0703 ;# 6704 bleu+1 sub %r6,%r4,%r19 ;# 6706 subsi3/1 addl %r28,%r19,%r6 ;# 6709 addsi3/1 sub %r12,%r4,%r19 ;# 6710 subsi3/1 comib,= 0,%r10,L$0713 ;# 6715 bleu+1 addl %r28,%r19,%r12 ;# 6713 addsi3/1 sub %r10,%r4,%r19 ;# 6716 subsi3/1 addl %r28,%r19,%r10 ;# 6719 addsi3/1 L$0713 comib,= 0,%r8,L$0714 ;# 6722 bleu+1 sub %r8,%r4,%r19 ;# 6723 subsi3/1 addl %r28,%r19,%r8 ;# 6726 addsi3/1 L$0714 comib,= 0,%r9,L$0703 ;# 6729 bleu+1 sub %r9,%r4,%r19 ;# 6730 subsi3/1 addl %r28,%r19,%r9 ;# 6733 addsi3/1 L$0703 ldw 0(%r5),%r4 ;# 6634 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6638 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6635 subsi3/1 ldo 1(%r19),%r19 ;# 6636 addsi3/2 comb,<< %r20,%r19,L$0705 nop ;# 6640 bleu+1 L$0704 ldi 27,%r19 ;# 6755 movqi+1/2 bl L$0043,%r0 ;# 6768 jump stbs,ma %r19,1(%r6) ;# 6756 movqi+1/6 L$0719 ldw 4(%r5),%r20 ;# 8191 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8189 subsi3/1 ldo 1(%r19),%r19 ;# 8190 addsi3/2 comb,>>=,n %r20,%r19,L$0724 ;# 8192 bleu+1 ldil L'65536,%r3 ;# 8559 reload_outsi+2/3 L$0725 comb,= %r3,%r20,L$0944 ;# 6798 bleu+1 zdep %r20,30,31,%r19 ;# 6808 ashlsi3+1 comb,>>= %r3,%r19,L$0730 ;# 6816 bleu+1 stw %r19,4(%r5) ;# 6810 reload_outsi+2/6 stw %r3,4(%r5) ;# 6819 reload_outsi+2/6 L$0730 ldw 0(%r5),%r26 ;# 6826 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6830 call_value_internal_symref ldw 4(%r5),%r25 ;# 6828 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6838 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6834 reload_outsi+2/6 comb,= %r28,%r4,L$0723 ;# 6848 bleu+1 sub %r6,%r4,%r19 ;# 6850 subsi3/1 addl %r28,%r19,%r6 ;# 6853 addsi3/1 sub %r12,%r4,%r19 ;# 6854 subsi3/1 comib,= 0,%r10,L$0733 ;# 6859 bleu+1 addl %r28,%r19,%r12 ;# 6857 addsi3/1 sub %r10,%r4,%r19 ;# 6860 subsi3/1 addl %r28,%r19,%r10 ;# 6863 addsi3/1 L$0733 comib,= 0,%r8,L$0734 ;# 6866 bleu+1 sub %r8,%r4,%r19 ;# 6867 subsi3/1 addl %r28,%r19,%r8 ;# 6870 addsi3/1 L$0734 comib,= 0,%r9,L$0723 ;# 6873 bleu+1 sub %r9,%r4,%r19 ;# 6874 subsi3/1 addl %r28,%r19,%r9 ;# 6877 addsi3/1 L$0723 ldw 0(%r5),%r4 ;# 6778 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6782 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6779 subsi3/1 ldo 1(%r19),%r19 ;# 6780 addsi3/2 comb,<< %r20,%r19,L$0725 nop ;# 6784 bleu+1 L$0724 ldi 28,%r19 ;# 6899 movqi+1/2 bl L$0043,%r0 ;# 6912 jump stbs,ma %r19,1(%r6) ;# 6900 movqi+1/6 L$0739 ldw 4(%r5),%r20 ;# 8199 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8197 subsi3/1 ldo 1(%r19),%r19 ;# 8198 addsi3/2 comb,>>=,n %r20,%r19,L$0744 ;# 8200 bleu+1 ldil L'65536,%r3 ;# 8557 reload_outsi+2/3 L$0745 comb,= %r3,%r20,L$0944 ;# 6942 bleu+1 zdep %r20,30,31,%r19 ;# 6952 ashlsi3+1 comb,>>= %r3,%r19,L$0750 ;# 6960 bleu+1 stw %r19,4(%r5) ;# 6954 reload_outsi+2/6 stw %r3,4(%r5) ;# 6963 reload_outsi+2/6 L$0750 ldw 0(%r5),%r26 ;# 6970 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6974 call_value_internal_symref ldw 4(%r5),%r25 ;# 6972 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6982 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6978 reload_outsi+2/6 comb,= %r28,%r4,L$0743 ;# 6992 bleu+1 sub %r6,%r4,%r19 ;# 6994 subsi3/1 addl %r28,%r19,%r6 ;# 6997 addsi3/1 sub %r12,%r4,%r19 ;# 6998 subsi3/1 comib,= 0,%r10,L$0753 ;# 7003 bleu+1 addl %r28,%r19,%r12 ;# 7001 addsi3/1 sub %r10,%r4,%r19 ;# 7004 subsi3/1 addl %r28,%r19,%r10 ;# 7007 addsi3/1 L$0753 comib,= 0,%r8,L$0754 ;# 7010 bleu+1 sub %r8,%r4,%r19 ;# 7011 subsi3/1 addl %r28,%r19,%r8 ;# 7014 addsi3/1 L$0754 comib,= 0,%r9,L$0743 ;# 7017 bleu+1 sub %r9,%r4,%r19 ;# 7018 subsi3/1 addl %r28,%r19,%r9 ;# 7021 addsi3/1 L$0743 ldw 0(%r5),%r4 ;# 6922 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6926 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6923 subsi3/1 ldo 1(%r19),%r19 ;# 6924 addsi3/2 comb,<< %r20,%r19,L$0745 nop ;# 6928 bleu+1 L$0744 ldi 10,%r19 ;# 7043 movqi+1/2 bl L$0043,%r0 ;# 7056 jump stbs,ma %r19,1(%r6) ;# 7044 movqi+1/6 L$0759 ldw 4(%r5),%r20 ;# 8207 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8205 subsi3/1 ldo 1(%r19),%r19 ;# 8206 addsi3/2 comb,>>=,n %r20,%r19,L$0764 ;# 8208 bleu+1 ldil L'65536,%r3 ;# 8555 reload_outsi+2/3 L$0765 comb,= %r3,%r20,L$0944 ;# 7086 bleu+1 zdep %r20,30,31,%r19 ;# 7096 ashlsi3+1 comb,>>= %r3,%r19,L$0770 ;# 7104 bleu+1 stw %r19,4(%r5) ;# 7098 reload_outsi+2/6 stw %r3,4(%r5) ;# 7107 reload_outsi+2/6 L$0770 ldw 0(%r5),%r26 ;# 7114 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7118 call_value_internal_symref ldw 4(%r5),%r25 ;# 7116 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7126 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7122 reload_outsi+2/6 comb,= %r28,%r4,L$0763 ;# 7136 bleu+1 sub %r6,%r4,%r19 ;# 7138 subsi3/1 addl %r28,%r19,%r6 ;# 7141 addsi3/1 sub %r12,%r4,%r19 ;# 7142 subsi3/1 comib,= 0,%r10,L$0773 ;# 7147 bleu+1 addl %r28,%r19,%r12 ;# 7145 addsi3/1 sub %r10,%r4,%r19 ;# 7148 subsi3/1 addl %r28,%r19,%r10 ;# 7151 addsi3/1 L$0773 comib,= 0,%r8,L$0774 ;# 7154 bleu+1 sub %r8,%r4,%r19 ;# 7155 subsi3/1 addl %r28,%r19,%r8 ;# 7158 addsi3/1 L$0774 comib,= 0,%r9,L$0763 ;# 7161 bleu+1 sub %r9,%r4,%r19 ;# 7162 subsi3/1 addl %r28,%r19,%r9 ;# 7165 addsi3/1 L$0763 ldw 0(%r5),%r4 ;# 7066 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7070 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7067 subsi3/1 ldo 1(%r19),%r19 ;# 7068 addsi3/2 comb,<< %r20,%r19,L$0765 nop ;# 7072 bleu+1 L$0764 ldi 11,%r19 ;# 7187 movqi+1/2 bl L$0043,%r0 ;# 7200 jump stbs,ma %r19,1(%r6) ;# 7188 movqi+1/6 L$0787 bb,< %r15,17,L$0076 ;# 7216 bleu+3 ldo -48(%r7),%r19 ;# 7224 addsi3/2 ldw -260(%r30),%r1 ;# 8986 reload_outsi+2/5 extru %r19,31,8,%r3 ;# 7225 zero_extendqisi2/1 comb,<< %r1,%r3,L$0939 ;# 7230 bleu+1 ldo -312(%r30),%r26 ;# 7244 addsi3/2 .CALL ARGW0=GR,ARGW1=GR bl group_in_compile_stack,%r2 ;# 7248 call_value_internal_symref copy %r3,%r25 ;# 7246 reload_outsi+2/1 extrs %r28,31,8,%r28 ;# 7251 extendqisi2 comib,<>,n 0,%r28,L$0076 ;# 7253 bleu+1 ldw 0(%r5),%r4 ;# 8212 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8215 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8213 subsi3/1 ldo 2(%r19),%r19 ;# 8214 addsi3/2 comb,>>= %r20,%r19,L$0795 ;# 8216 bleu+1 copy %r6,%r8 ;# 7260 reload_outsi+2/1 ldil L'65536,%r7 ;# 8553 reload_outsi+2/3 L$0796 comb,= %r7,%r20,L$0944 ;# 7288 bleu+1 zdep %r20,30,31,%r19 ;# 7298 ashlsi3+1 comb,>>= %r7,%r19,L$0801 ;# 7306 bleu+1 stw %r19,4(%r5) ;# 7300 reload_outsi+2/6 stw %r7,4(%r5) ;# 7309 reload_outsi+2/6 L$0801 ldw 0(%r5),%r26 ;# 7316 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7320 call_value_internal_symref ldw 4(%r5),%r25 ;# 7318 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7328 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7324 reload_outsi+2/6 comb,= %r28,%r4,L$0794 ;# 7338 bleu+1 sub %r6,%r4,%r19 ;# 7340 subsi3/1 addl %r28,%r19,%r6 ;# 7343 addsi3/1 sub %r12,%r4,%r19 ;# 7344 subsi3/1 comib,= 0,%r10,L$0804 ;# 7349 bleu+1 addl %r28,%r19,%r12 ;# 7347 addsi3/1 sub %r10,%r4,%r19 ;# 7350 subsi3/1 addl %r28,%r19,%r10 ;# 7353 addsi3/1 L$0804 comib,= 0,%r8,L$0805 ;# 7356 bleu+1 sub %r8,%r4,%r19 ;# 7357 subsi3/1 addl %r28,%r19,%r8 ;# 7360 addsi3/1 L$0805 comib,= 0,%r9,L$0794 ;# 7363 bleu+1 sub %r9,%r4,%r19 ;# 7364 subsi3/1 addl %r28,%r19,%r9 ;# 7367 addsi3/1 L$0794 ldw 0(%r5),%r4 ;# 7268 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7272 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7269 subsi3/1 ldo 2(%r19),%r19 ;# 7270 addsi3/2 comb,<< %r20,%r19,L$0796 nop ;# 7274 bleu+1 L$0795 ldi 7,%r19 ;# 7389 movqi+1/2 stbs,ma %r19,1(%r6) ;# 7390 movqi+1/6 bl L$0043,%r0 ;# 7405 jump stbs,ma %r3,1(%r6) ;# 7393 movqi+1/6 L$0811 bb,< %r15,30,L$0104 nop ;# 7414 bleu+3 L$0397 comib,= 0,%r14,L$0815 ;# 7429 bleu+1 addl %r14,%r7,%r19 ;# 7430 addsi3/1 bl L$0816,%r0 ;# 7434 jump ldb 0(%r19),%r19 ;# 7433 zero_extendqisi2/2 L$0815 copy %r7,%r19 ;# 7438 reload_outsi+2/1 L$0816 copy %r19,%r7 ;# 7441 reload_outsi+2/1 L$0076 comib,=,n 0,%r9,L$0820 ;# 7460 bleu+1 ldb 0(%r9),%r20 ;# 7463 zero_extendqisi2/2 addl %r9,%r20,%r19 ;# 7464 addsi3/1 ldo 1(%r19),%r19 ;# 7465 addsi3/2 comb,<> %r6,%r19,L$0820 ;# 7467 bleu+1 ldi 255,%r19 ;# 7472 reload_outsi+2/2 comb,= %r19,%r20,L$0820 ;# 7474 bleu+1 ldw -296(%r30),%r21 ;# 7476 reload_outsi+2/5 ldb 0(%r21),%r19 ;# 7478 movqi+1/5 extrs %r19,31,8,%r20 ;# 7479 extendqisi2 ldi 42,%r19 ;# 7481 reload_outsi+2/2 comb,= %r19,%r20,L$0820 ;# 7483 bleu+1 ldi 94,%r19 ;# 7490 reload_outsi+2/2 comb,=,n %r19,%r20,L$0820 ;# 7492 bleu+1 bb,>= %r15,30,L$0821 ;# 7497 movsi-4 ldi 92,%r19 ;# 7504 reload_outsi+2/2 comb,<>,n %r19,%r20,L$0822 ;# 7506 bleu+1 ldb 1(%r21),%r19 ;# 7510 movqi+1/5 extrs %r19,31,8,%r20 ;# 7511 extendqisi2 L$0821 ldi 43,%r19 ;# 7534 reload_outsi+2/2 comb,= %r19,%r20,L$0820 ;# 7536 bleu+1 ldi 63,%r19 ;# 7543 reload_outsi+2/2 comb,=,n %r19,%r20,L$0820 ;# 7545 bleu+1 L$0822 bb,>=,n %r15,22,L$0819 ;# 7553 movsi-4 bb,>= %r15,19,L$0823 ;# 7558 movsi-4 ldw -296(%r30),%r19 ;# 7560 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 7562 movqi+1/5 ldi 123,%r20 ;# 7565 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 7563 extendqisi2 comb,=,n %r20,%r19,L$0820 ;# 7567 bleu+1 ldw 0(%r5),%r4 ;# 8228 reload_outsi+2/5 bl,n L$1177,%r0 ;# 7568 jump L$0823 ldw -296(%r30),%r21 ;# 7572 reload_outsi+2/5 ldb 0(%r21),%r19 ;# 7574 movqi+1/5 ldi 92,%r20 ;# 7577 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 7575 extendqisi2 comb,<>,n %r20,%r19,L$0819 ;# 7579 bleu+1 ldb 1(%r21),%r19 ;# 7583 movqi+1/5 ldi 123,%r20 ;# 7586 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 7584 extendqisi2 comb,<>,n %r20,%r19,L$0819 ;# 7588 bleu+1 L$0820 ldw 0(%r5),%r4 ;# 8220 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8223 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8221 subsi3/1 ldo 2(%r19),%r19 ;# 8222 addsi3/2 comb,>>= %r20,%r19,L$0829 ;# 8224 bleu+1 copy %r6,%r8 ;# 7596 reload_outsi+2/1 ldil L'65536,%r3 ;# 8551 reload_outsi+2/3 L$0830 comb,= %r3,%r20,L$0944 ;# 7624 bleu+1 zdep %r20,30,31,%r19 ;# 7634 ashlsi3+1 comb,>>= %r3,%r19,L$0835 ;# 7642 bleu+1 stw %r19,4(%r5) ;# 7636 reload_outsi+2/6 stw %r3,4(%r5) ;# 7645 reload_outsi+2/6 L$0835 ldw 0(%r5),%r26 ;# 7652 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7656 call_value_internal_symref ldw 4(%r5),%r25 ;# 7654 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7664 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7660 reload_outsi+2/6 comb,= %r28,%r4,L$0828 ;# 7674 bleu+1 sub %r6,%r4,%r19 ;# 7676 subsi3/1 addl %r28,%r19,%r6 ;# 7679 addsi3/1 sub %r12,%r4,%r19 ;# 7680 subsi3/1 comib,= 0,%r10,L$0838 ;# 7685 bleu+1 addl %r28,%r19,%r12 ;# 7683 addsi3/1 sub %r10,%r4,%r19 ;# 7686 subsi3/1 addl %r28,%r19,%r10 ;# 7689 addsi3/1 L$0838 comib,= 0,%r8,L$0839 ;# 7692 bleu+1 sub %r8,%r4,%r19 ;# 7693 subsi3/1 addl %r28,%r19,%r8 ;# 7696 addsi3/1 L$0839 comib,= 0,%r9,L$0828 ;# 7699 bleu+1 sub %r9,%r4,%r19 ;# 7700 subsi3/1 addl %r28,%r19,%r9 ;# 7703 addsi3/1 L$0828 ldw 0(%r5),%r4 ;# 7604 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7608 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7605 subsi3/1 ldo 2(%r19),%r19 ;# 7606 addsi3/2 comb,<< %r20,%r19,L$0830 nop ;# 7610 bleu+1 L$0829 ldi 1,%r19 ;# 7725 movqi+1/2 stbs,ma %r19,1(%r6) ;# 7726 movqi+1/6 stbs,ma %r0,1(%r6) ;# 7729 movqi+1/6 ldo -1(%r6),%r9 ;# 7741 addsi3/2 L$0819 ldw 0(%r5),%r4 ;# 8228 reload_outsi+2/5 L$1177 ldw 4(%r5),%r20 ;# 8231 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8229 subsi3/1 ldo 1(%r19),%r19 ;# 8230 addsi3/2 comb,>>=,n %r20,%r19,L$0848 ;# 8232 bleu+1 ldil L'65536,%r3 ;# 8549 reload_outsi+2/3 L$0849 comb,= %r3,%r20,L$0944 ;# 7771 bleu+1 zdep %r20,30,31,%r19 ;# 7781 ashlsi3+1 comb,>>= %r3,%r19,L$0854 ;# 7789 bleu+1 stw %r19,4(%r5) ;# 7783 reload_outsi+2/6 stw %r3,4(%r5) ;# 7792 reload_outsi+2/6 L$0854 ldw 0(%r5),%r26 ;# 7799 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7803 call_value_internal_symref ldw 4(%r5),%r25 ;# 7801 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7811 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7807 reload_outsi+2/6 comb,= %r28,%r4,L$0847 ;# 7821 bleu+1 sub %r6,%r4,%r19 ;# 7823 subsi3/1 addl %r28,%r19,%r6 ;# 7826 addsi3/1 sub %r12,%r4,%r19 ;# 7827 subsi3/1 comib,= 0,%r10,L$0857 ;# 7832 bleu+1 addl %r28,%r19,%r12 ;# 7830 addsi3/1 sub %r10,%r4,%r19 ;# 7833 subsi3/1 addl %r28,%r19,%r10 ;# 7836 addsi3/1 L$0857 comib,= 0,%r8,L$0858 ;# 7839 bleu+1 sub %r8,%r4,%r19 ;# 7840 subsi3/1 addl %r28,%r19,%r8 ;# 7843 addsi3/1 L$0858 comib,= 0,%r9,L$0847 ;# 7846 bleu+1 sub %r9,%r4,%r19 ;# 7847 subsi3/1 addl %r28,%r19,%r9 ;# 7850 addsi3/1 L$0847 ldw 0(%r5),%r4 ;# 7751 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7755 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7752 subsi3/1 ldo 1(%r19),%r19 ;# 7753 addsi3/2 comb,<< %r20,%r19,L$0849 nop ;# 7757 bleu+1 L$0848 stbs,ma %r7,1(%r6) ;# 7872 movqi+1/6 ldb 0(%r9),%r19 ;# 7885 movqi+1/5 ldo 1(%r19),%r19 ;# 7888 addsi3/2 stb %r19,0(%r9) ;# 7890 movqi+1/6 L$0043 ldw -296(%r30),%r19 ;# 2328 reload_outsi+2/5 L$1161 comclr,= %r16,%r19,%r0 ;# 258 bleu+1 bl L$1178,%r0 ldw -296(%r30),%r19 ;# 2334 reload_outsi+2/5 L$0044 comib,= 0,%r10,L$0865 ;# 7913 bleu+1 ldi 13,%r26 ;# 7918 reload_outsi+2/2 copy %r10,%r25 ;# 7920 reload_outsi+2/1 sub %r6,%r25,%r24 ;# 7915 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 7924 call_internal_symref ldo -3(%r24),%r24 ;# 7922 addsi3/2 L$0865 ldw -304(%r30),%r19 ;# 7928 reload_outsi+2/5 comib,<>,n 0,%r19,L$0866 ;# 7930 bleu+1 .CALL ARGW0=GR bl free,%r2 ;# 7946 call_internal_symref ldw -312(%r30),%r26 ;# 7944 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 7949 reload_outsi+2/5 ldi 0,%r28 ;# 7955 reload_outsi+2/2 sub %r6,%r19,%r19 ;# 7950 subsi3/1 bl L$0867,%r0 ;# 7957 jump stw %r19,8(%r5) ;# 7952 reload_outsi+2/6 L$0895 .CALL ARGW0=GR bl free,%r2 ;# 2269 call_internal_symref ldw -312(%r30),%r26 ;# 2267 reload_outsi+2/5 bl L$0867,%r0 ;# 2273 jump ldi 11,%r28 ;# 2271 reload_outsi+2/2 L$0900 .CALL ARGW0=GR bl free,%r2 ;# 3161 call_internal_symref ldw -312(%r30),%r26 ;# 3159 reload_outsi+2/5 bl L$0867,%r0 ;# 3165 jump ldi 4,%r28 ;# 3163 reload_outsi+2/2 L$0902 .CALL ARGW0=GR bl free,%r2 ;# 3218 call_internal_symref ldw -312(%r30),%r26 ;# 3216 reload_outsi+2/5 bl L$0867,%r0 ;# 3222 jump ldi 7,%r28 ;# 3220 reload_outsi+2/2 L$0903 .CALL ARGW0=GR bl free,%r2 ;# 3803 call_internal_symref ldw -312(%r30),%r26 ;# 3801 reload_outsi+2/5 bl L$0867,%r0 ;# 3807 jump ldi 5,%r28 ;# 3805 reload_outsi+2/2 L$0915 .CALL ARGW0=GR bl free,%r2 ;# 5461 call_internal_symref ldw -312(%r30),%r26 ;# 5459 reload_outsi+2/5 bl L$0867,%r0 ;# 5465 jump ldi 9,%r28 ;# 5463 reload_outsi+2/2 L$0917 .CALL ARGW0=GR bl free,%r2 ;# 5557 call_internal_symref ldw -312(%r30),%r26 ;# 5555 reload_outsi+2/5 bl L$0867,%r0 ;# 5561 jump ldi 13,%r28 ;# 5559 reload_outsi+2/2 L$0922 bl L$0867,%r0 ;# 5983 jump ldi 14,%r28 ;# 5981 reload_outsi+2/2 L$0939 .CALL ARGW0=GR bl free,%r2 ;# 7235 call_internal_symref ldw -312(%r30),%r26 ;# 7233 reload_outsi+2/5 bl L$0867,%r0 ;# 7239 jump ldi 6,%r28 ;# 7237 reload_outsi+2/2 L$0944 bl L$0867,%r0 ;# 7775 jump ldi 15,%r28 ;# 7773 reload_outsi+2/2 L$0866 .CALL ARGW0=GR bl free,%r2 ;# 7935 call_internal_symref ldw -312(%r30),%r26 ;# 7933 reload_outsi+2/5 ldi 8,%r28 ;# 7937 reload_outsi+2/2 L$0867 ldw -340(%r30),%r2 ;# 9026 reload_outsi+2/5 ldw -168(%r30),%r18 ;# 9028 reload_outsi+2/5 ldw -164(%r30),%r17 ;# 9030 reload_outsi+2/5 ldw -160(%r30),%r16 ;# 9032 reload_outsi+2/5 ldw -156(%r30),%r15 ;# 9034 reload_outsi+2/5 ldw -152(%r30),%r14 ;# 9036 reload_outsi+2/5 ldw -148(%r30),%r13 ;# 9038 reload_outsi+2/5 ldw -144(%r30),%r12 ;# 9040 reload_outsi+2/5 ldw -140(%r30),%r11 ;# 9042 reload_outsi+2/5 ldw -136(%r30),%r10 ;# 9044 reload_outsi+2/5 ldw -132(%r30),%r9 ;# 9046 reload_outsi+2/5 ldw -128(%r30),%r8 ;# 9048 reload_outsi+2/5 ldw -124(%r30),%r7 ;# 9050 reload_outsi+2/5 ldw -120(%r30),%r6 ;# 9052 reload_outsi+2/5 ldw -116(%r30),%r5 ;# 9054 reload_outsi+2/5 ldw -112(%r30),%r4 ;# 9056 reload_outsi+2/5 ldw -108(%r30),%r3 ;# 9058 reload_outsi+2/5 bv %r0(%r2) ;# 9061 return_internal ldo -320(%r30),%r30 ;# 9060 addsi3/2 .EXIT .PROCEND .data .align 1 re_syntax_table .block 256
stsp/binutils-ia16	41,373	gas/testsuite/gas/hppa/basic/weird.s	.stabs "weird.c",0x64,0,0,Label0 Label0: .stabs "inttype:t1=bu4;0;32;",0x80,0,0,0 .stabs "sym32: !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type32:t32= !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "attr104:G404=@h !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr105:G405=@i !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "var0:G300=@a8;1",0x20,0,0, 0 .export var0 .data .align 4 var0: .long 42 .stabs "sym33:! !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym35:# !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym36:$ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym37:% !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym38:& !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym39:' !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym40:( !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym41:) !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym42:* !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym43:+ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym44:, !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym45:- !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .export attr122 .data .align 4 attr122: .long 42 .export attr123 .data .align 4 attr123: .long 42 .export attr124 .data .align 4 attr124: .long 42 .stabs "sym46:. !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym47:/ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym48:0 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym49:1 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym50:2 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "attr96:G396=@` !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr97:G397=@a !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr98:G398=@b !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr99:G399=@c !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "sym51:3 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym52:4 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym53:5 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym54:6 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym55:7 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym56:8 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym57:9 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym58:: !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym59:; !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym60:< !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym61:= !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym62:> !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym63:? !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym64:@ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym65:A !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym66:B !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym67:C !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym68:D !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym69:E !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym70:F !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym71:G !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym72:H !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym73:I !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym74:J !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym75:K !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym76:L !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym77:M !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym78:N !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym79:O !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym80:P !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym81:Q !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym82:R !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym83:S !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym84:T !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym85:U !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym86:V !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym87:W !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym88:X !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym89:Y !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym90:Z !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym91:[ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym93:] !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym94:^ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym95:_ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym96:` !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym97:a !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym98:b !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym99:c !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym100:d !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym101:e !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym102:f !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym103:g !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym104:h !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym105:i !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym106:j !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym107:k !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym108:l !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym109:m !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym110:n !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym111:o !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym112:p !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym113:q !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym114:r !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym115:s !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym116:t !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym117:u !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym118:v !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym119:w !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym120:x !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym121:y !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym122:z !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym123:{ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym124:\| !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym125:} !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "sym126:~ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type33:t33=! !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type35:t35=# !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type36:t36=$ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type37:t37=% !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type38:t38=& !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type39:t39=' !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type40:t40=( !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type41:t41=) !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type42:t42=* !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type43:t43=+ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type44:t44=, !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type45:t45=- !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type46:t46=. !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type47:t47=/ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type48:t48=0 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type49:t49=1 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type50:t50=2 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type51:t51=3 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type52:t52=4 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type53:t53=5 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type54:t54=6 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type55:t55=7 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type56:t56=8 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type57:t57=9 !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type58:t58=: !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type59:t59=; !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type60:t60=< !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type61:t61== !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type62:t62=> !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type63:t63=? !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type64:t64=@ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type65:t65=A !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type66:t66=B !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type67:t67=C !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .export attr66 .data .align 4 attr66: .long 42 .export attr67 .data .align 4 attr67: .long 42 .export attr68 .data .align 4 attr68: .long 42 .export attr69 .data .align 4 attr69: .long 42 .stabs "type68:t68=D !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type69:t69=E !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type70:t70=F !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type71:t71=G !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type72:t72=H !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type73:t73=I !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type74:t74=J !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type75:t75=K !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type76:t76=L !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type77:t77=M !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type78:t78=N !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type79:t79=O !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type80:t80=P !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type81:t81=Q !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type82:t82=R !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type83:t83=S !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type84:t84=T !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type85:t85=U !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type86:t86=V !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type87:t87=W !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "attr69:G369=@E !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr70:G370=@F !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr71:G371=@G !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "type88:t88=X !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type89:t89=Y !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type90:t90=Z !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type91:t91=[ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type93:t93=] !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type94:t94=^ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type95:t95=_ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type96:t96=` !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type97:t97=a !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type98:t98=b !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type99:t99=c !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type100:t100=d !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type101:t101=e !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type102:t102=f !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type103:t103=g !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type104:t104=h !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type105:t105=i !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type106:t106=j !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type107:t107=k !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type108:t108=l !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type109:t109=m !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type110:t110=n !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type111:t111=o !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type112:t112=p !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type113:t113=q !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type114:t114=r !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type115:t115=s !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type116:t116=t !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type117:t117=u !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type118:t118=v !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type119:t119=w !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type120:t120=x !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type121:t121=y !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type122:t122=z !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type123:t123={ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type124:t124=\| !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type125:t125=} !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type126:t126=~ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "attr32:G332=@ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr33:G333=@! !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr35:G334=@# !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "primary:G200=ered:0,green:1,blue:2,;", 0x20,0,0, 0 .stabs "attr36:G335=@$ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .export primary .data .align 4 primary: .long 42 .stabs "attr37:G337=@% !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "const69:c=e1,69", 0x80,0,0, 0 .stabs "const70:c=e190=bs2;0;16;,70", 0x80,0,0, 0 .stabs "attr38:G338=@& !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "bad_neg0type:t201=s8field0:1,0,32;field2:-534,32,64;field3:-1,96,32;;", 0x80,0,0, 0 .stabs "bad_neg0:G201", 0x20,0,0, 0 .export bad_neg0 .data .align 4 bad_neg0: .long 42 .long 43, 44, 45 .stabs "attr39:G339=@' !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr41:G341=@) !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr42:G342=@ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr43:G343=@+ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr44:G344=@, !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr46:G346=@. !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr47:G347=@/ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr58:G358=@: !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr59:G359=@;@ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr60:G360=@< !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr61:G361=@= !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr62:G362=@> !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr63:G363=@? !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr64:G364=@@ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr65:G365=@A !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr66:G366=@B !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr67:G367=@C !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr68:G368=@D !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr72:G372=@H !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr73:G373=@I !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr74:G374=@J !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr75:G375=@K !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr76:G376=@L !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr77:G377=@M !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr78:G378=@N !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr79:G379=@O !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr80:G380=@P !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr81:G381=@Q !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr82:G382=@R !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr83:G383=@S !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr84:G384=@T !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr85:G385=@U !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr86:G386=@V !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr87:G387=@W !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr88:G388=@X !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr89:G389=@Y !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr90:G390=@Z !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr91:G391=@[ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr93:G393=@] !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .export _common0 .data .align 4 _common0: .long 42 .long 24 .long 22 .export common0 .data .align 4 common0: .long 42 .long 24 .long 22 .stabs "common0",0xe2,0,0,0 .stabs "common0var0:S1", 0x20,0,0, 0 .stabs "common0var1:S1", 0x20,0,0, 4 .stabs "common0var2:S1", 0x20,0,0, 8 .stabs "common0",0xe4,0,0,0 .stabs "attr94:G394=@^ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr95:G395=@_ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr100:G400=@d !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr101:G401=@e !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr102:G402=@f !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr103:G403=@g !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr106:G406=@j !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr107:G407=@k !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr108:G408=@l !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr109:G409=@m !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr110:G410=@n !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr111:G411=@o !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr112:G412=@p !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr113:G413=@q !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr114:G414=@r !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr115:G415=@s !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr116:G416=@t !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr117:G417=@u !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr118:G418=@v !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr119:G419=@w !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr120:G420=@x !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr121:G421=@y !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr122:G422=@z !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr123:G423=@{ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr124:G424=@\| !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr125:G425=@} !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .stabs "attr126:G426=@~ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0 .export attr32 .data .align 4 attr32: .long 42 .export attr33 .data .align 4 attr33: .long 42 .export attr35 .data .align 4 attr35: .long 42 .export attr36 .data .align 4 attr36: .long 42 .export attr37 .data .align 4 attr37: .long 42 .export attr38 .data .align 4 attr38: .long 42 .export attr39 .data .align 4 attr39: .long 42 .export attr41 .data .align 4 attr41: .long 42 .export attr42 .data .align 4 attr42: .long 42 .export attr43 .data .align 4 attr43: .long 42 .export attr44 .data .align 4 attr44: .long 42 .export attr46 .data .align 4 attr46: .long 42 .export attr47 .data .align 4 attr47: .long 42 .export attr58 .data .align 4 attr58: .long 42 .export attr59 .data .align 4 attr59: .long 42 .export attr60 .data .align 4 attr60: .long 42 .export attr61 .data .align 4 attr61: .long 42 .export attr62 .data .align 4 attr62: .long 42 .export attr63 .data .align 4 attr63: .long 42 .export attr64 .data .align 4 attr64: .long 42 .export attr65 .data .align 4 attr65: .long 42 .export attr70 .data .align 4 attr70: .long 42 .export attr71 .data .align 4 attr71: .long 42 .export attr72 .data .align 4 attr72: .long 42 .export attr73 .data .align 4 attr73: .long 42 .export attr74 .data .align 4 attr74: .long 42 .export attr75 .data .align 4 attr75: .long 42 .export attr76 .data .align 4 attr76: .long 42 .export attr77 .data .align 4 attr77: .long 42 .export attr78 .data .align 4 attr78: .long 42 .export attr79 .data .align 4 attr79: .long 42 .export attr80 .data .align 4 attr80: .long 42 .export attr81 .data .align 4 attr81: .long 42 .export attr82 .data .align 4 attr82: .long 42 .export attr83 .data .align 4 attr83: .long 42 .export attr84 .data .align 4 attr84: .long 42 .stabs "float72type:t202=R87;9;", 0x80,0,0, 0 .stabs "int256var:G203=bu32;0;256;", 0x20,0,0, 0 .export int256var .data .align 4 int256var: .long 42 .long 0x2b, 0x2c, 0x2d, 0x2d, 0x2c, 0x2b, 0x2a .stabs "consth:c=e1,4294967296", 0x80,0,0, 0 .stabs "consth2:c=e1,-734723985732642758928475678987234563284937456", 0x80,0,0, 0 .stabs "bad_neg0const:c=S201,128,128,11222211343434345656565677888877", 0x80,0,0, 0 .stabs "bad_type0:t(-3,7)", 0x80,0,0, 0 .stabs "bad_type1:t(42,6)", 0x80,0,0, 0 .stabs "array_index0:t205=r1;0;5;", 0x80,0,0, 0 .stabs "array0:G206=a205;1", 0x20,0,0, 0 .export array0 .data .align 4 array0: .long 42 .long 43, 44, 45, 46, 47 .stabs "array_index1:t207=", 0x80,0,0, 0 .stabs "array1:G208=aeai1_red:0,ai1_green:1,ai1_blue:2,;;1", 0x20,0,0, 0 .export array1 .data .align 4 array1: .long 42 .long 43, 44 .stabs "inttype_one:t209=1", 0x80,0,0, 0 .stabs "inttype_two:t210=1", 0x80,0,0, 0 .stabs "one_var:G209", 0x20,0,0, 0 .export one_var .data .align 4 one_var: .long 42 .stabs "two_var:G210", 0x20,0,0, 0 .export two_var .data .align 4 two_var: .long 42 .stabs "intp:t211=1", 0x80,0,0, 0 .stabs "pointer_to_int_var:G212=1", 0x80,0,0, 0 .stabs "intp_var:G211", 0x20,0,0, 0 .export intp_var .data .align 4 intp_var: .long 42 .stabs "unrecog_const:c=xjksdflskd33,4;473;", 0x80,0,0, 0 .export attr85 .data .align 4 attr85: .long 42 .export attr86 .data .align 4 attr86: .long 42 .export attr87 .data .align 4 attr87: .long 42 .export attr88 .data .align 4 attr88: .long 42 .export attr89 .data .align 4 attr89: .long 42 .export attr90 .data .align 4 attr90: .long 42 .export attr91 .data .align 4 attr91: .long 42 .export attr92 .data .align 4 attr92: .long 42 .export attr93 .data .align 4 attr93: .long 42 .export attr94 .data .align 4 attr94: .long 42 .export attr95 .data .align 4 attr95: .long 42 .export attr96 .data .align 4 attr96: .long 42 .export attr97 .data .align 4 attr97: .long 42 .export attr98 .data .align 4 attr98: .long 42 .export attr99 .data .align 4 attr99: .long 42 .export attr100 .data .align 4 attr100: .long 42 .export attr101 .data .align 4 attr101: .long 42 .export attr102 .data .align 4 attr102: .long 42 .export attr103 .data .align 4 attr103: .long 42 .export attr104 .data .align 4 attr104: .long 42 .export attr105 .data .align 4 attr105: .long 42 .export attr106 .data .align 4 attr106: .long 42 .export attr107 .data .align 4 attr107: .long 42 .export attr108 .data .align 4 attr108: .long 42 .export attr109 .data .align 4 attr109: .long 42 .export attr110 .data .align 4 attr110: .long 42 .export attr111 .data .align 4 attr111: .long 42 .export attr112 .data .align 4 attr112: .long 42 .export attr113 .data .align 4 attr113: .long 42 .export attr114 .data .align 4 attr114: .long 42 .export attr115 .data .align 4 attr115: .long 42 .export attr116 .data .align 4 attr116: .long 42 .export attr117 .data .align 4 attr117: .long 42 .export attr118 .data .align 4 attr118: .long 42 .export attr119 .data .align 4 attr119: .long 42 .export attr120 .data .align 4 attr120: .long 42 .export attr121 .data .align 4 attr121: .long 42 .export attr125 .data .align 4 attr125: .long 42 .export attr126 .data .align 4 attr126: .long 42 .stabs "var1:G301=@s32;1",0x20,0,0, 0 .export var1 .data .align 4 var1: .long 42 .stabs "var2:G302=@p42;1",0x20,0,0, 0 .export var2 .data .align 4 var2: .long 42 .stabs "var3:G303=@P;1",0x20,0,0, 0 .export var3 .data .align 4 var3: .long 42 .stabs "v_comb:G448=s24!2,020,445=s12!1,120,444=s4x:1,0,32;;;$vb444:446=444,0;a:/01,32,32;;;0264,447=s12!1,120,444;$vb444:446,0;b:/01,32,32;;;comb:/01,128,32;;", 0x20,0,0, 0 .export v_comb .align 1 v_comb: .long v_comb_shared .long 43 .long v_comb_shared .long 44 .long 45 v_comb_shared: .long 42 .stabs "sym92:\\ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "type92:t92=\\ !#$%&'()+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~",0x80,0,0,0 .stabs "attr92:G392=@\\ !#$%&'()+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{\|}~;1",0x20,0,0, 0
stsp/binutils-ia16	1,256	gas/testsuite/gas/hppa/basic/coprmem.s	.code .align 4 ; Basic copr memory tests which also test the various ; addressing modes and completers. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. ; copr_indexing_load: cldwx,4 %r5(%sr0,%r4),%r26 cldwx,4,s %r5(%sr0,%r4),%r26 cldwx,4,m %r5(%sr0,%r4),%r26 cldwx,4,sm %r5(%sr0,%r4),%r26 clddx,4 %r5(%sr0,%r4),%r26 clddx,4,s %r5(%sr0,%r4),%r26 clddx,4,m %r5(%sr0,%r4),%r26 clddx,4,sm %r5(%sr0,%r4),%r26 copr_indexing_store: cstwx,4 %r26,%r5(%sr0,%r4) cstwx,4,s %r26,%r5(%sr0,%r4) cstwx,4,m %r26,%r5(%sr0,%r4) cstwx,4,sm %r26,%r5(%sr0,%r4) cstdx,4 %r26,%r5(%sr0,%r4) cstdx,4,s %r26,%r5(%sr0,%r4) cstdx,4,m %r26,%r5(%sr0,%r4) cstdx,4,sm %r26,%r5(%sr0,%r4) copr_short_memory: cldws,4 0(%sr0,%r4),%r26 cldws,4,mb 0(%sr0,%r4),%r26 cldws,4,ma 0(%sr0,%r4),%r26 cldds,4 0(%sr0,%r4),%r26 cldds,4,mb 0(%sr0,%r4),%r26 cldds,4,ma 0(%sr0,%r4),%r26 cstws,4 %r26,0(%sr0,%r4) cstws,4,mb %r26,0(%sr0,%r4) cstws,4,ma %r26,0(%sr0,%r4) cstds,4 %r26,0(%sr0,%r4) cstds,4,mb %r26,0(%sr0,%r4) cstds,4,ma %r26,0(%sr0,%r4) ; gas fucks this up thinks it gets the expression 4 modulo 5 ; cldwx,4 %r5(0,%r4),%r%r26
stsp/binutils-ia16	1,418	gas/testsuite/gas/hppa/basic/sh2add.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sh2add %r4,%r5,%r6 sh2add,= %r4,%r5,%r6 sh2add,< %r4,%r5,%r6 sh2add,<= %r4,%r5,%r6 sh2add,nuv %r4,%r5,%r6 sh2add,znv %r4,%r5,%r6 sh2add,sv %r4,%r5,%r6 sh2add,od %r4,%r5,%r6 sh2add,tr %r4,%r5,%r6 sh2add,<> %r4,%r5,%r6 sh2add,>= %r4,%r5,%r6 sh2add,> %r4,%r5,%r6 sh2add,uv %r4,%r5,%r6 sh2add,vnz %r4,%r5,%r6 sh2add,nsv %r4,%r5,%r6 sh2add,ev %r4,%r5,%r6 sh2addl %r4,%r5,%r6 sh2addl,= %r4,%r5,%r6 sh2addl,< %r4,%r5,%r6 sh2addl,<= %r4,%r5,%r6 sh2addl,nuv %r4,%r5,%r6 sh2addl,znv %r4,%r5,%r6 sh2addl,sv %r4,%r5,%r6 sh2addl,od %r4,%r5,%r6 sh2addl,tr %r4,%r5,%r6 sh2addl,<> %r4,%r5,%r6 sh2addl,>= %r4,%r5,%r6 sh2addl,> %r4,%r5,%r6 sh2addl,uv %r4,%r5,%r6 sh2addl,vnz %r4,%r5,%r6 sh2addl,nsv %r4,%r5,%r6 sh2addl,ev %r4,%r5,%r6 sh2addo %r4,%r5,%r6 sh2addo,= %r4,%r5,%r6 sh2addo,< %r4,%r5,%r6 sh2addo,<= %r4,%r5,%r6 sh2addo,nuv %r4,%r5,%r6 sh2addo,znv %r4,%r5,%r6 sh2addo,sv %r4,%r5,%r6 sh2addo,od %r4,%r5,%r6 sh2addo,tr %r4,%r5,%r6 sh2addo,<> %r4,%r5,%r6 sh2addo,>= %r4,%r5,%r6 sh2addo,> %r4,%r5,%r6 sh2addo,uv %r4,%r5,%r6 sh2addo,vnz %r4,%r5,%r6 sh2addo,nsv %r4,%r5,%r6 sh2addo,ev %r4,%r5,%r6
stsp/binutils-ia16	1,183	gas/testsuite/gas/hppa/basic/fmem.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fldwx %r4(%sr0,%r5),%fr6 fldwx,s %r4(%sr0,%r5),%fr6 fldwx,m %r4(%sr0,%r5),%fr6 fldwx,sm %r4(%sr0,%r5),%fr6 flddx %r4(%sr0,%r5),%fr6 flddx,s %r4(%sr0,%r5),%fr6 flddx,m %r4(%sr0,%r5),%fr6 flddx,sm %r4(%sr0,%r5),%fr6 fstwx %fr6,%r4(%sr0,%r5) fstwx,s %fr6,%r4(%sr0,%r5) fstwx,m %fr6,%r4(%sr0,%r5) fstwx,sm %fr6,%r4(%sr0,%r5) fstdx %fr6,%r4(%sr0,%r5) fstdx,s %fr6,%r4(%sr0,%r5) fstdx,m %fr6,%r4(%sr0,%r5) fstdx,sm %fr6,%r4(%sr0,%r5) fstqx %fr6,%r4(%sr0,%r5) fstqx,s %fr6,%r4(%sr0,%r5) fstqx,m %fr6,%r4(%sr0,%r5) fstqx,sm %fr6,%r4(%sr0,%r5) fldws 0(%sr0,%r5),%fr6 fldws,mb 0(%sr0,%r5),%fr6 fldws,ma 0(%sr0,%r5),%fr6 fldds 0(%sr0,%r5),%fr6 fldds,mb 0(%sr0,%r5),%fr6 fldds,ma 0(%sr0,%r5),%fr6 fstws %fr6,0(%sr0,%r5) fstws,mb %fr6,0(%sr0,%r5) fstws,ma %fr6,0(%sr0,%r5) fstds %fr6,0(%sr0,%r5) fstds,mb %fr6,0(%sr0,%r5) fstds,ma %fr6,0(%sr0,%r5) fstqs %fr6,0(%sr0,%r5) fstqs,mb %fr6,0(%sr0,%r5) fstqs,ma %fr6,0(%sr0,%r5)
stsp/binutils-ia16	1,143	gas/testsuite/gas/hppa/basic/fmemLRbug.s	.code .export f f: .proc .callinfo frame=0,no_calls .entry fstws %fr6R,0(%r26) fstws %fr6L,4(%r26) fstws %fr6,8(%r26) fstds %fr6L,4(%r26) fstds %fr6,8(%r26) fldws 0(%r26),%fr6R fldws 4(%r26),%fr6L fldws 8(%r26),%fr6 fldds 4(%r26),%fr6L fldds 8(%r26),%fr6 fstws %fr6R,0(%sr0,%r26) fstws %fr6L,4(%sr0,%r26) fstws %fr6,8(%sr0,%r26) fstds %fr6L,4(%sr0,%r26) fstds %fr6,8(%sr0,%r26) fldws 0(%sr0,%r26),%fr6R fldws 4(%sr0,%r26),%fr6L fldws 8(%sr0,%r26),%fr6 fldds 4(%sr0,%r26),%fr6L fldds 8(%sr0,%r26),%fr6 fstwx %fr6R,%r25(%r26) fstwx %fr6L,%r25(%r26) fstwx %fr6,%r25(%r26) fstdx %fr6L,%r25(%r26) fstdx %fr6,%r25(%r26) fldwx %r25(%r26),%fr6R fldwx %r25(%r26),%fr6L fldwx %r25(%r26),%fr6 flddx %r25(%r26),%fr6L flddx %r25(%r26),%fr6 fstwx %fr6R,%r25(%sr0,%r26) fstwx %fr6L,%r25(%sr0,%r26) fstwx %fr6,%r25(%sr0,%r26) fstdx %fr6L,%r25(%sr0,%r26) fstdx %fr6,%r25(%sr0,%r26) fldwx %r25(%sr0,%r26),%fr6R fldwx %r25(%sr0,%r26),%fr6L fldwx %r25(%sr0,%r26),%fr6 flddx %r25(%sr0,%r26),%fr6L flddx %r25(%sr0,%r26),%fr6 bv %r0(%r2) nop .exit .procend
stsp/binutils-ia16	1,711	gas/testsuite/gas/hppa/basic/fp_comp.s	.level 1.1 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fcpy,sgl %fr5,%fr10 fcpy,dbl %fr5,%fr10 fcpy,quad %fr5,%fr10 fcpy,sgl %fr20,%fr24 fcpy,dbl %fr20,%fr24 fabs,sgl %fr5,%fr10 fabs,dbl %fr5,%fr10 fabs,quad %fr5,%fr10 fabs,sgl %fr20,%fr24 fabs,dbl %fr20,%fr24 fsqrt,sgl %fr5,%fr10 fsqrt,dbl %fr5,%fr10 fsqrt,quad %fr5,%fr10 fsqrt,sgl %fr20,%fr24 fsqrt,dbl %fr20,%fr24 frnd,sgl %fr5,%fr10 frnd,dbl %fr5,%fr10 frnd,quad %fr5,%fr10 frnd,sgl %fr20,%fr24 frnd,dbl %fr20,%fr24 fadd,sgl %fr4,%fr8,%fr12 fadd,dbl %fr4,%fr8,%fr12 fadd,quad %fr4,%fr8,%fr12 fadd,sgl %fr20,%fr24,%fr28 fadd,dbl %fr20,%fr24,%fr28 fadd,quad %fr20,%fr24,%fr28 fsub,sgl %fr4,%fr8,%fr12 fsub,dbl %fr4,%fr8,%fr12 fsub,quad %fr4,%fr8,%fr12 fsub,sgl %fr20,%fr24,%fr28 fsub,dbl %fr20,%fr24,%fr28 fsub,quad %fr20,%fr24,%fr28 fmpy,sgl %fr4,%fr8,%fr12 fmpy,dbl %fr4,%fr8,%fr12 fmpy,quad %fr4,%fr8,%fr12 fmpy,sgl %fr20,%fr24,%fr28 fmpy,dbl %fr20,%fr24,%fr28 fmpy,quad %fr20,%fr24,%fr28 fdiv,sgl %fr4,%fr8,%fr12 fdiv,dbl %fr4,%fr8,%fr12 fdiv,quad %fr4,%fr8,%fr12 fdiv,sgl %fr20,%fr24,%fr28 fdiv,dbl %fr20,%fr24,%fr28 fdiv,quad %fr20,%fr24,%fr28 frem,sgl %fr4,%fr8,%fr12 frem,dbl %fr4,%fr8,%fr12 frem,quad %fr4,%fr8,%fr12 frem,sgl %fr20,%fr24,%fr28 frem,dbl %fr20,%fr24,%fr28 frem,quad %fr20,%fr24,%fr28 fmpyadd,sgl %fr16,%fr17,%fr18,%fr19,%fr20 fmpyadd,dbl %fr16,%fr17,%fr18,%fr19,%fr20 fmpysub,sgl %fr16,%fr17,%fr18,%fr19,%fr20 fmpysub,dbl %fr16,%fr17,%fr18,%fr19,%fr20 xmpyu %fr4,%fr5,%fr6
stsp/binutils-ia16	2,815	gas/testsuite/gas/hppa/basic/sub2.s	.LEVEL 2.0 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sub,* %r4,%r5,%r6 sub,= %r4,%r5,%r6 sub,< %r4,%r5,%r6 sub,<= %r4,%r5,%r6 sub,<< %r4,%r5,%r6 sub,<<= %r4,%r5,%r6 sub,sv %r4,%r5,%r6 sub,od %r4,%r5,%r6 sub,tr %r4,%r5,%r6 sub,<> %r4,%r5,%r6 sub,>= %r4,%r5,%r6 sub,> %r4,%r5,%r6 sub,>>= %r4,%r5,%r6 sub,>> %r4,%r5,%r6 sub,nsv %r4,%r5,%r6 sub,ev %r4,%r5,%r6 sub,tsv, %r4,%r5,%r6 sub,tsv,= %r4,%r5,%r6 sub,tsv,< %r4,%r5,%r6 sub,tsv,<= %r4,%r5,%r6 sub,tsv,<< %r4,%r5,%r6 sub,tsv,<<= %r4,%r5,%r6 sub,tsv,sv %r4,%r5,%r6 sub,tsv,od %r4,%r5,%r6 sub,tsv,tr %r4,%r5,%r6 sub,tsv,<> %r4,%r5,%r6 sub,tsv,>= %r4,%r5,%r6 sub,tsv,> %r4,%r5,%r6 sub,tsv,>>= %r4,%r5,%r6 sub,tsv,>> %r4,%r5,%r6 sub,tsv,nsv %r4,%r5,%r6 sub,tsv,ev %r4,%r5,%r6 sub,db, %r4,%r5,%r6 sub,db,= %r4,%r5,%r6 sub,db,< %r4,%r5,%r6 sub,db,<= %r4,%r5,%r6 sub,db,<< %r4,%r5,%r6 sub,db,<<= %r4,%r5,%r6 sub,db,sv %r4,%r5,%r6 sub,db,od %r4,%r5,%r6 sub,db,tr %r4,%r5,%r6 sub,db,<> %r4,%r5,%r6 sub,db,>= %r4,%r5,%r6 sub,db,> %r4,%r5,%r6 sub,db,>>= %r4,%r5,%r6 sub,db,>> %r4,%r5,%r6 sub,db,nsv %r4,%r5,%r6 sub,db,ev %r4,%r5,%r6 sub,db,tsv, %r4,%r5,%r6 sub,db,tsv,= %r4,%r5,%r6 sub,db,tsv,< %r4,%r5,%r6 sub,db,tsv,<= %r4,%r5,%r6 sub,db,tsv,<< %r4,%r5,%r6 sub,db,tsv,<<= %r4,%r5,%r6 sub,db,tsv,sv %r4,%r5,%r6 sub,db,tsv,od %r4,%r5,%r6 sub,tsv,db,tr %r4,%r5,%r6 sub,tsv,db,<> %r4,%r5,%r6 sub,tsv,db,>= %r4,%r5,%r6 sub,tsv,db,> %r4,%r5,%r6 sub,tsv,db,>>= %r4,%r5,%r6 sub,tsv,db,>> %r4,%r5,%r6 sub,tsv,db,nsv %r4,%r5,%r6 sub,tsv,db,ev %r4,%r5,%r6 sub,tc, %r4,%r5,%r6 sub,tc,= %r4,%r5,%r6 sub,tc,< %r4,%r5,%r6 sub,tc,<= %r4,%r5,%r6 sub,tc,<< %r4,%r5,%r6 sub,tc,<<= %r4,%r5,%r6 sub,tc,sv %r4,%r5,%r6 sub,tc,od %r4,%r5,%r6 sub,tc,tr %r4,%r5,%r6 sub,tc,<> %r4,%r5,%r6 sub,tc,>= %r4,%r5,%r6 sub,tc,> %r4,%r5,%r6 sub,tc,>>= %r4,%r5,%r6 sub,tc,>> %r4,%r5,%r6 sub,tc,nsv %r4,%r5,%r6 sub,tc,ev %r4,%r5,%r6 sub,tc,tsv, %r4,%r5,%r6 sub,tc,tsv,= %r4,%r5,%r6 sub,tc,tsv,< %r4,%r5,%r6 sub,tc,tsv,<= %r4,%r5,%r6 sub,tc,tsv,<< %r4,%r5,%r6 sub,tc,tsv,<<= %r4,%r5,%r6 sub,tc,tsv,sv %r4,%r5,%r6 sub,tc,tsv,od %r4,%r5,%r6 sub,tsv,tc,tr %r4,%r5,%r6 sub,tsv,tc,<> %r4,%r5,%r6 sub,tsv,tc,>= %r4,%r5,%r6 sub,tsv,tc,> %r4,%r5,%r6 sub,tsv,tc,>>= %r4,%r5,%r6 sub,tsv,tc,>> %r4,%r5,%r6 sub,tsv,tc,nsv %r4,%r5,%r6 sub,tsv,tc,*ev %r4,%r5,%r6 ;; PR gas/11395: Check for the correct assembly ;; of unconditional 32-bit and 64-bit sub instructions. sub %r1,%r1,%r1 sub,db %r1,%r1,%r1
stsp/binutils-ia16	2,161	gas/testsuite/gas/hppa/basic/imem.s	.code .align 4 .EXPORT integer_memory_tests,CODE .EXPORT integer_indexing_load,CODE .EXPORT integer_load_short_memory,CODE .EXPORT integer_store_short_memory,CODE .EXPORT main,CODE .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR ; Basic integer memory tests which also test the various ; addressing modes and completers. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. ; integer_memory_tests: ldw 0(%sr0,%r4),%r26 ldh 0(%sr0,%r4),%r26 ldb 0(%sr0,%r4),%r26 stw %r26,0(%sr0,%r4) sth %r26,0(%sr0,%r4) stb %r26,0(%sr0,%r4) ; Should make sure pre/post modes are recognized correctly. ldwm 0(%sr0,%r4),%r26 stwm %r26,0(%sr0,%r4) integer_indexing_load: ldwx %r5(%sr0,%r4),%r26 ldwx,s %r5(%sr0,%r4),%r26 ldwx,m %r5(%sr0,%r4),%r26 ldwx,sm %r5(%sr0,%r4),%r26 ldhx %r5(%sr0,%r4),%r26 ldhx,s %r5(%sr0,%r4),%r26 ldhx,m %r5(%sr0,%r4),%r26 ldhx,sm %r5(%sr0,%r4),%r26 ldbx %r5(%sr0,%r4),%r26 ldbx,s %r5(%sr0,%r4),%r26 ldbx,m %r5(%sr0,%r4),%r26 ldbx,sm %r5(%sr0,%r4),%r26 ldwax %r5(%r4),%r26 ldwax,s %r5(%r4),%r26 ldwax,m %r5(%r4),%r26 ldwax,sm %r5(%r4),%r26 ldcwx %r5(%sr0,%r4),%r26 ldcwx,s %r5(%sr0,%r4),%r26 ldcwx,m %r5(%sr0,%r4),%r26 ldcwx,sm %r5(%sr0,%r4),%r26 integer_load_short_memory: ldws 0(%sr0,%r4),%r26 ldws,mb 0(%sr0,%r4),%r26 ldws,ma 0(%sr0,%r4),%r26 ldhs 0(%sr0,%r4),%r26 ldhs,mb 0(%sr0,%r4),%r26 ldhs,ma 0(%sr0,%r4),%r26 ldbs 0(%sr0,%r4),%r26 ldbs,mb 0(%sr0,%r4),%r26 ldbs,ma 0(%sr0,%r4),%r26 ldwas 0(%r4),%r26 ldwas,mb 0(%r4),%r26 ldwas,ma 0(%r4),%r26 ldcws 0(%sr0,%r4),%r26 ldcws,mb 0(%sr0,%r4),%r26 ldcws,ma 0(%sr0,%r4),%r26 integer_store_short_memory: stws %r26,0(%sr0,%r4) stws,mb %r26,0(%sr0,%r4) stws,ma %r26,0(%sr0,%r4) sths %r26,0(%sr0,%r4) sths,mb %r26,0(%sr0,%r4) sths,ma %r26,0(%sr0,%r4) stbs %r26,0(%sr0,%r4) stbs,mb %r26,0(%sr0,%r4) stbs,ma %r26,0(%sr0,%r4) stwas %r26,0(%r4) stwas,mb %r26,0(%r4) stwas,ma %r26,0(%r4) stbys %r26,0(%sr0,%r4) stbys,b %r26,0(%sr0,%r4) stbys,e %r26,0(%sr0,%r4) stbys,b,m %r26,0(%sr0,%r4) stbys,e,m %r26,0(%sr0,%r4)
stsp/binutils-ia16	1,039	gas/testsuite/gas/hppa/basic/logical.s	.level 1.1 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. or %r4,%r5,%r6 or,= %r4,%r5,%r6 or,< %r4,%r5,%r6 or,<= %r4,%r5,%r6 or,od %r4,%r5,%r6 or,tr %r4,%r5,%r6 or,<> %r4,%r5,%r6 or,>= %r4,%r5,%r6 or,> %r4,%r5,%r6 or,ev %r4,%r5,%r6 xor %r4,%r5,%r6 xor,= %r4,%r5,%r6 xor,< %r4,%r5,%r6 xor,<= %r4,%r5,%r6 xor,od %r4,%r5,%r6 xor,tr %r4,%r5,%r6 xor,<> %r4,%r5,%r6 xor,>= %r4,%r5,%r6 xor,> %r4,%r5,%r6 xor,ev %r4,%r5,%r6 and %r4,%r5,%r6 and,= %r4,%r5,%r6 and,< %r4,%r5,%r6 and,<= %r4,%r5,%r6 and,od %r4,%r5,%r6 and,tr %r4,%r5,%r6 and,<> %r4,%r5,%r6 and,>= %r4,%r5,%r6 and,> %r4,%r5,%r6 and,ev %r4,%r5,%r6 andcm %r4,%r5,%r6 andcm,= %r4,%r5,%r6 andcm,< %r4,%r5,%r6 andcm,<= %r4,%r5,%r6 andcm,od %r4,%r5,%r6 andcm,tr %r4,%r5,%r6 andcm,<> %r4,%r5,%r6 andcm,>= %r4,%r5,%r6 andcm,> %r4,%r5,%r6 andcm,ev %r4,%r5,%r6
stsp/binutils-ia16	4,269	gas/testsuite/gas/hppa/basic/shladd.s	.level 1.1 .code .align 4 ; Basic shladd instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. shladd %r4,1,%r5,%r6 shladd,= %r4,1,%r5,%r6 shladd,< %r4,1,%r5,%r6 shladd,<= %r4,1,%r5,%r6 shladd,nuv %r4,1,%r5,%r6 shladd,znv %r4,1,%r5,%r6 shladd,sv %r4,1,%r5,%r6 shladd,od %r4,1,%r5,%r6 shladd,tr %r4,1,%r5,%r6 shladd,<> %r4,1,%r5,%r6 shladd,>= %r4,1,%r5,%r6 shladd,> %r4,1,%r5,%r6 shladd,uv %r4,1,%r5,%r6 shladd,vnz %r4,1,%r5,%r6 shladd,nsv %r4,1,%r5,%r6 shladd,ev %r4,1,%r5,%r6 shladd,l %r4,1,%r5,%r6 shladd,l,= %r4,1,%r5,%r6 shladd,l,< %r4,1,%r5,%r6 shladd,l,<= %r4,1,%r5,%r6 shladd,l,nuv %r4,1,%r5,%r6 shladd,l,znv %r4,1,%r5,%r6 shladd,l,sv %r4,1,%r5,%r6 shladd,l,od %r4,1,%r5,%r6 shladd,l,tr %r4,1,%r5,%r6 shladd,l,<> %r4,1,%r5,%r6 shladd,l,>= %r4,1,%r5,%r6 shladd,l,> %r4,1,%r5,%r6 shladd,l,uv %r4,1,%r5,%r6 shladd,l,vnz %r4,1,%r5,%r6 shladd,l,nsv %r4,1,%r5,%r6 shladd,l,ev %r4,1,%r5,%r6 shladd,tsv %r4,1,%r5,%r6 shladd,tsv,= %r4,1,%r5,%r6 shladd,tsv,< %r4,1,%r5,%r6 shladd,tsv,<= %r4,1,%r5,%r6 shladd,tsv,nuv %r4,1,%r5,%r6 shladd,tsv,znv %r4,1,%r5,%r6 shladd,tsv,sv %r4,1,%r5,%r6 shladd,tsv,od %r4,1,%r5,%r6 shladd,tsv,tr %r4,1,%r5,%r6 shladd,tsv,<> %r4,1,%r5,%r6 shladd,tsv,>= %r4,1,%r5,%r6 shladd,tsv,> %r4,1,%r5,%r6 shladd,tsv,uv %r4,1,%r5,%r6 shladd,tsv,vnz %r4,1,%r5,%r6 shladd,tsv,nsv %r4,1,%r5,%r6 shladd,tsv,ev %r4,1,%r5,%r6 shladd %r4,2,%r5,%r6 shladd,= %r4,2,%r5,%r6 shladd,< %r4,2,%r5,%r6 shladd,<= %r4,2,%r5,%r6 shladd,nuv %r4,2,%r5,%r6 shladd,znv %r4,2,%r5,%r6 shladd,sv %r4,2,%r5,%r6 shladd,od %r4,2,%r5,%r6 shladd,tr %r4,2,%r5,%r6 shladd,<> %r4,2,%r5,%r6 shladd,>= %r4,2,%r5,%r6 shladd,> %r4,2,%r5,%r6 shladd,uv %r4,2,%r5,%r6 shladd,vnz %r4,2,%r5,%r6 shladd,nsv %r4,2,%r5,%r6 shladd,ev %r4,2,%r5,%r6 shladd,l %r4,2,%r5,%r6 shladd,l,= %r4,2,%r5,%r6 shladd,l,< %r4,2,%r5,%r6 shladd,l,<= %r4,2,%r5,%r6 shladd,l,nuv %r4,2,%r5,%r6 shladd,l,znv %r4,2,%r5,%r6 shladd,l,sv %r4,2,%r5,%r6 shladd,l,od %r4,2,%r5,%r6 shladd,l,tr %r4,2,%r5,%r6 shladd,l,<> %r4,2,%r5,%r6 shladd,l,>= %r4,2,%r5,%r6 shladd,l,> %r4,2,%r5,%r6 shladd,l,uv %r4,2,%r5,%r6 shladd,l,vnz %r4,2,%r5,%r6 shladd,l,nsv %r4,2,%r5,%r6 shladd,l,ev %r4,2,%r5,%r6 shladd,tsv %r4,2,%r5,%r6 shladd,tsv,= %r4,2,%r5,%r6 shladd,tsv,< %r4,2,%r5,%r6 shladd,tsv,<= %r4,2,%r5,%r6 shladd,tsv,nuv %r4,2,%r5,%r6 shladd,tsv,znv %r4,2,%r5,%r6 shladd,tsv,sv %r4,2,%r5,%r6 shladd,tsv,od %r4,2,%r5,%r6 shladd,tsv,tr %r4,2,%r5,%r6 shladd,tsv,<> %r4,2,%r5,%r6 shladd,tsv,>= %r4,2,%r5,%r6 shladd,tsv,> %r4,2,%r5,%r6 shladd,tsv,uv %r4,2,%r5,%r6 shladd,tsv,vnz %r4,2,%r5,%r6 shladd,tsv,nsv %r4,2,%r5,%r6 shladd,tsv,ev %r4,2,%r5,%r6 shladd %r4,3,%r5,%r6 shladd,= %r4,3,%r5,%r6 shladd,< %r4,3,%r5,%r6 shladd,<= %r4,3,%r5,%r6 shladd,nuv %r4,3,%r5,%r6 shladd,znv %r4,3,%r5,%r6 shladd,sv %r4,3,%r5,%r6 shladd,od %r4,3,%r5,%r6 shladd,tr %r4,3,%r5,%r6 shladd,<> %r4,3,%r5,%r6 shladd,>= %r4,3,%r5,%r6 shladd,> %r4,3,%r5,%r6 shladd,uv %r4,3,%r5,%r6 shladd,vnz %r4,3,%r5,%r6 shladd,nsv %r4,3,%r5,%r6 shladd,ev %r4,3,%r5,%r6 shladd,l %r4,3,%r5,%r6 shladd,l,= %r4,3,%r5,%r6 shladd,l,< %r4,3,%r5,%r6 shladd,l,<= %r4,3,%r5,%r6 shladd,l,nuv %r4,3,%r5,%r6 shladd,l,znv %r4,3,%r5,%r6 shladd,l,sv %r4,3,%r5,%r6 shladd,l,od %r4,3,%r5,%r6 shladd,l,tr %r4,3,%r5,%r6 shladd,l,<> %r4,3,%r5,%r6 shladd,l,>= %r4,3,%r5,%r6 shladd,l,> %r4,3,%r5,%r6 shladd,l,uv %r4,3,%r5,%r6 shladd,l,vnz %r4,3,%r5,%r6 shladd,l,nsv %r4,3,%r5,%r6 shladd,l,ev %r4,3,%r5,%r6 shladd,tsv %r4,3,%r5,%r6 shladd,tsv,= %r4,3,%r5,%r6 shladd,tsv,< %r4,3,%r5,%r6 shladd,tsv,<= %r4,3,%r5,%r6 shladd,tsv,nuv %r4,3,%r5,%r6 shladd,tsv,znv %r4,3,%r5,%r6 shladd,tsv,sv %r4,3,%r5,%r6 shladd,tsv,od %r4,3,%r5,%r6 shladd,tsv,tr %r4,3,%r5,%r6 shladd,tsv,<> %r4,3,%r5,%r6 shladd,tsv,>= %r4,3,%r5,%r6 shladd,tsv,> %r4,3,%r5,%r6 shladd,tsv,uv %r4,3,%r5,%r6 shladd,tsv,vnz %r4,3,%r5,%r6 shladd,tsv,nsv %r4,3,%r5,%r6 shladd,tsv,ev %r4,3,%r5,%r6
stsp/binutils-ia16	1,732	gas/testsuite/gas/hppa/basic/deposit2.s	.code .align 4 ; Deposit instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. depw,z %r4,5,10,%r6 depw,z,= %r4,5,10,%r6 depw,z,< %r4,5,10,%r6 depw,z,od %r4,5,10,%r6 depw,z,tr %r4,5,10,%r6 depw,z,<> %r4,5,10,%r6 depw,z,>= %r4,5,10,%r6 depw,z,ev %r4,5,10,%r6 depw %r4,5,10,%r6 depw,= %r4,5,10,%r6 depw,< %r4,5,10,%r6 depw,od %r4,5,10,%r6 depw,tr %r4,5,10,%r6 depw,<> %r4,5,10,%r6 depw,>= %r4,5,10,%r6 depw,ev %r4,5,10,%r6 depw,z %r4,%sar,5,%r6 depw,z,= %r4,%sar,5,%r6 depw,z,< %r4,%sar,5,%r6 depw,z,od %r4,%sar,5,%r6 depw,z,tr %r4,%sar,5,%r6 depw,z,<> %r4,%sar,5,%r6 depw,z,>= %r4,%sar,5,%r6 depw,z,ev %r4,%sar,5,%r6 depw %r4,%sar,5,%r6 depw,= %r4,%sar,5,%r6 depw,< %r4,%sar,5,%r6 depw,od %r4,%sar,5,%r6 depw,tr %r4,%sar,5,%r6 depw,<> %r4,%sar,5,%r6 depw,>= %r4,%sar,5,%r6 depw,ev %r4,%sar,5,%r6 depwi -1,%sar,5,%r6 depwi,= -1,%sar,5,%r6 depwi,< -1,%sar,5,%r6 depwi,od -1,%sar,5,%r6 depwi,tr -1,%sar,5,%r6 depwi,<> -1,%sar,5,%r6 depwi,>= -1,%sar,5,%r6 depwi,ev -1,%sar,5,%r6 depwi,z -1,%sar,5,%r6 depwi,z,= -1,%sar,5,%r6 depwi,z,< -1,%sar,5,%r6 depwi,z,od -1,%sar,5,%r6 depwi,z,tr -1,%sar,5,%r6 depwi,z,<> -1,%sar,5,%r6 depwi,z,>= -1,%sar,5,%r6 depwi,z,ev -1,%sar,5,%r6 depwi -1,4,10,%r6 depwi,= -1,4,10,%r6 depwi,< -1,4,10,%r6 depwi,od -1,4,10,%r6 depwi,tr -1,4,10,%r6 depwi,<> -1,4,10,%r6 depwi,>= -1,4,10,%r6 depwi,ev -1,4,10,%r6 depwi,z -1,4,10,%r6 depwi,z,= -1,4,10,%r6 depwi,z,< -1,4,10,%r6 depwi,z,od -1,4,10,%r6 depwi,z,tr -1,4,10,%r6 depwi,z,<> -1,4,10,%r6 depwi,z,>= -1,4,10,%r6 depwi,z,ev -1,4,10,%r6
stsp/binutils-ia16	2,985	gas/testsuite/gas/hppa/basic/addi.s	.code .align 4 ; Basic add immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. addi 123,%r5,%r6 addi,= 123,%r5,%r6 addi,< 123,%r5,%r6 addi,<= 123,%r5,%r6 addi,nuv 123,%r5,%r6 addi,znv 123,%r5,%r6 addi,sv 123,%r5,%r6 addi,od 123,%r5,%r6 addi,tr 123,%r5,%r6 addi,<> 123,%r5,%r6 addi,>= 123,%r5,%r6 addi,> 123,%r5,%r6 addi,uv 123,%r5,%r6 addi,vnz 123,%r5,%r6 addi,nsv 123,%r5,%r6 addi,ev 123,%r5,%r6 addio 123,%r5,%r6 addio,= 123,%r5,%r6 addio,< 123,%r5,%r6 addio,<= 123,%r5,%r6 addio,nuv 123,%r5,%r6 addio,znv 123,%r5,%r6 addio,sv 123,%r5,%r6 addio,od 123,%r5,%r6 addio,tr 123,%r5,%r6 addio,<> 123,%r5,%r6 addio,>= 123,%r5,%r6 addio,> 123,%r5,%r6 addio,uv 123,%r5,%r6 addio,vnz 123,%r5,%r6 addio,nsv 123,%r5,%r6 addio,ev 123,%r5,%r6 addit 123,%r5,%r6 addit,= 123,%r5,%r6 addit,< 123,%r5,%r6 addit,<= 123,%r5,%r6 addit,nuv 123,%r5,%r6 addit,znv 123,%r5,%r6 addit,sv 123,%r5,%r6 addit,od 123,%r5,%r6 addit,tr 123,%r5,%r6 addit,<> 123,%r5,%r6 addit,>= 123,%r5,%r6 addit,> 123,%r5,%r6 addit,uv 123,%r5,%r6 addit,vnz 123,%r5,%r6 addit,nsv 123,%r5,%r6 addit,ev 123,%r5,%r6 addito 123,%r5,%r6 addito,= 123,%r5,%r6 addito,< 123,%r5,%r6 addito,<= 123,%r5,%r6 addito,nuv 123,%r5,%r6 addito,znv 123,%r5,%r6 addito,sv 123,%r5,%r6 addito,od 123,%r5,%r6 addito,tr 123,%r5,%r6 addito,<> 123,%r5,%r6 addito,>= 123,%r5,%r6 addito,> 123,%r5,%r6 addito,uv 123,%r5,%r6 addito,vnz 123,%r5,%r6 addito,nsv 123,%r5,%r6 addito,ev 123,%r5,%r6 addi,tsv 123,%r5,%r6 addi,tsv,= 123,%r5,%r6 addi,tsv,< 123,%r5,%r6 addi,tsv,<= 123,%r5,%r6 addi,tsv,nuv 123,%r5,%r6 addi,tsv,znv 123,%r5,%r6 addi,tsv,sv 123,%r5,%r6 addi,tsv,od 123,%r5,%r6 addi,tsv,tr 123,%r5,%r6 addi,tsv,<> 123,%r5,%r6 addi,tsv,>= 123,%r5,%r6 addi,tsv,> 123,%r5,%r6 addi,tsv,uv 123,%r5,%r6 addi,tsv,vnz 123,%r5,%r6 addi,tsv,nsv 123,%r5,%r6 addi,tsv,ev 123,%r5,%r6 addi,tc 123,%r5,%r6 addi,tc,= 123,%r5,%r6 addi,tc,< 123,%r5,%r6 addi,tc,<= 123,%r5,%r6 addi,tc,nuv 123,%r5,%r6 addi,tc,znv 123,%r5,%r6 addi,tc,sv 123,%r5,%r6 addi,tc,od 123,%r5,%r6 addi,tc,tr 123,%r5,%r6 addi,tc,<> 123,%r5,%r6 addi,tc,>= 123,%r5,%r6 addi,tc,> 123,%r5,%r6 addi,tc,uv 123,%r5,%r6 addi,tc,vnz 123,%r5,%r6 addi,tc,nsv 123,%r5,%r6 addi,tc,ev 123,%r5,%r6 addi,tc,tsv 123,%r5,%r6 addi,tc,tsv,= 123,%r5,%r6 addi,tc,tsv,< 123,%r5,%r6 addi,tc,tsv,<= 123,%r5,%r6 addi,tc,tsv,nuv 123,%r5,%r6 addi,tc,tsv,znv 123,%r5,%r6 addi,tc,tsv,sv 123,%r5,%r6 addi,tc,tsv,od 123,%r5,%r6 addi,tsv,tc,tr 123,%r5,%r6 addi,tsv,tc,<> 123,%r5,%r6 addi,tsv,tc,>= 123,%r5,%r6 addi,tsv,tc,> 123,%r5,%r6 addi,tsv,tc,uv 123,%r5,%r6 addi,tsv,tc,vnz 123,%r5,%r6 addi,tsv,tc,nsv 123,%r5,%r6 addi,tsv,tc,ev 123,%r5,%r6
stsp/binutils-ia16	2,287	gas/testsuite/gas/hppa/basic/fp_conv.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fcnvff,sgl,sgl %fr5,%fr10 fcnvff,sgl,dbl %fr5,%fr10 fcnvff,sgl,quad %fr5,%fr10 fcnvff,dbl,sgl %fr5,%fr10 fcnvff,dbl,dbl %fr5,%fr10 fcnvff,dbl,quad %fr5,%fr10 fcnvff,quad,sgl %fr5,%fr10 fcnvff,quad,dbl %fr5,%fr10 fcnvff,quad,quad %fr5,%fr10 fcnvff,sgl,sgl %fr20,%fr24 fcnvff,sgl,dbl %fr20,%fr24 fcnvff,sgl,quad %fr20,%fr24 fcnvff,dbl,sgl %fr20,%fr24 fcnvff,dbl,dbl %fr20,%fr24 fcnvff,dbl,quad %fr20,%fr24 fcnvff,quad,sgl %fr20,%fr24 fcnvff,quad,dbl %fr20,%fr24 fcnvff,quad,quad %fr20,%fr24 fcnvxf,sgl,sgl %fr5,%fr10 fcnvxf,sgl,dbl %fr5,%fr10 fcnvxf,sgl,quad %fr5,%fr10 fcnvxf,dbl,sgl %fr5,%fr10 fcnvxf,dbl,dbl %fr5,%fr10 fcnvxf,dbl,quad %fr5,%fr10 fcnvxf,quad,sgl %fr5,%fr10 fcnvxf,quad,dbl %fr5,%fr10 fcnvxf,quad,quad %fr5,%fr10 fcnvxf,sgl,sgl %fr20,%fr24 fcnvxf,sgl,dbl %fr20,%fr24 fcnvxf,sgl,quad %fr20,%fr24 fcnvxf,dbl,sgl %fr20,%fr24 fcnvxf,dbl,dbl %fr20,%fr24 fcnvxf,dbl,quad %fr20,%fr24 fcnvxf,quad,sgl %fr20,%fr24 fcnvxf,quad,dbl %fr20,%fr24 fcnvxf,quad,quad %fr20,%fr24 fcnvfx,sgl,sgl %fr5,%fr10 fcnvfx,sgl,dbl %fr5,%fr10 fcnvfx,sgl,quad %fr5,%fr10 fcnvfx,dbl,sgl %fr5,%fr10 fcnvfx,dbl,dbl %fr5,%fr10 fcnvfx,dbl,quad %fr5,%fr10 fcnvfx,quad,sgl %fr5,%fr10 fcnvfx,quad,dbl %fr5,%fr10 fcnvfx,quad,quad %fr5,%fr10 fcnvfx,sgl,sgl %fr20,%fr24 fcnvfx,sgl,dbl %fr20,%fr24 fcnvfx,sgl,quad %fr20,%fr24 fcnvfx,dbl,sgl %fr20,%fr24 fcnvfx,dbl,dbl %fr20,%fr24 fcnvfx,dbl,quad %fr20,%fr24 fcnvfx,quad,sgl %fr20,%fr24 fcnvfx,quad,dbl %fr20,%fr24 fcnvfx,quad,quad %fr20,%fr24 fcnvfxt,sgl,sgl %fr5,%fr10 fcnvfxt,sgl,dbl %fr5,%fr10 fcnvfxt,sgl,quad %fr5,%fr10 fcnvfxt,dbl,sgl %fr5,%fr10 fcnvfxt,dbl,dbl %fr5,%fr10 fcnvfxt,dbl,quad %fr5,%fr10 fcnvfxt,quad,sgl %fr5,%fr10 fcnvfxt,quad,dbl %fr5,%fr10 fcnvfxt,quad,quad %fr5,%fr10 fcnvfxt,sgl,sgl %fr20,%fr24 fcnvfxt,sgl,dbl %fr20,%fr24 fcnvfxt,sgl,quad %fr20,%fr24 fcnvfxt,dbl,sgl %fr20,%fr24 fcnvfxt,dbl,dbl %fr20,%fr24 fcnvfxt,dbl,quad %fr20,%fr24 fcnvfxt,quad,sgl %fr20,%fr24 fcnvfxt,quad,dbl %fr20,%fr24 fcnvfxt,quad,quad %fr20,%fr24
stsp/binutils-ia16	1,517	gas/testsuite/gas/hppa/basic/deposit.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. zdep %r4,5,10,%r6 zdep,= %r4,5,10,%r6 zdep,< %r4,5,10,%r6 zdep,od %r4,5,10,%r6 zdep,tr %r4,5,10,%r6 zdep,<> %r4,5,10,%r6 zdep,>= %r4,5,10,%r6 zdep,ev %r4,5,10,%r6 dep %r4,5,10,%r6 dep,= %r4,5,10,%r6 dep,< %r4,5,10,%r6 dep,od %r4,5,10,%r6 dep,tr %r4,5,10,%r6 dep,<> %r4,5,10,%r6 dep,>= %r4,5,10,%r6 dep,ev %r4,5,10,%r6 zvdep %r4,5,%r6 zvdep,= %r4,5,%r6 zvdep,< %r4,5,%r6 zvdep,od %r4,5,%r6 zvdep,tr %r4,5,%r6 zvdep,<> %r4,5,%r6 zvdep,>= %r4,5,%r6 zvdep,ev %r4,5,%r6 vdep %r4,5,%r6 vdep,= %r4,5,%r6 vdep,< %r4,5,%r6 vdep,od %r4,5,%r6 vdep,tr %r4,5,%r6 vdep,<> %r4,5,%r6 vdep,>= %r4,5,%r6 vdep,ev %r4,5,%r6 vdepi -1,5,%r6 vdepi,= -1,5,%r6 vdepi,< -1,5,%r6 vdepi,od -1,5,%r6 vdepi,tr -1,5,%r6 vdepi,<> -1,5,%r6 vdepi,>= -1,5,%r6 vdepi,ev -1,5,%r6 zvdepi -1,5,%r6 zvdepi,= -1,5,%r6 zvdepi,< -1,5,%r6 zvdepi,od -1,5,%r6 zvdepi,tr -1,5,%r6 zvdepi,<> -1,5,%r6 zvdepi,>= -1,5,%r6 zvdepi,ev -1,5,%r6 depi -1,4,10,%r6 depi,= -1,4,10,%r6 depi,< -1,4,10,%r6 depi,od -1,4,10,%r6 depi,tr -1,4,10,%r6 depi,<> -1,4,10,%r6 depi,>= -1,4,10,%r6 depi,ev -1,4,10,%r6 zdepi -1,4,10,%r6 zdepi,= -1,4,10,%r6 zdepi,< -1,4,10,%r6 zdepi,od -1,4,10,%r6 zdepi,tr -1,4,10,%r6 zdepi,<> -1,4,10,%r6 zdepi,>= -1,4,10,%r6 zdepi,ev -1,4,10,%r6
stsp/binutils-ia16	1,085	gas/testsuite/gas/hppa/basic/extract3.s	.LEVEL 2.0 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. extrd,u,* %r4,10,5,%r6 extrd,u,= %r4,10,5,%r6 extrd,u,< %r4,10,5,%r6 extrd,u,od %r4,10,5,%r6 extrd,u,tr %r4,10,5,%r6 extrd,u,<> %r4,10,5,%r6 extrd,u,>= %r4,10,5,%r6 extrd,u,ev %r4,10,5,%r6 extrd,s, %r4,10,5,%r6 extrd,s,= %r4,10,5,%r6 extrd,s,< %r4,10,5,%r6 extrd,s,od %r4,10,5,%r6 extrd,tr %r4,10,5,%r6 extrd,<> %r4,10,5,%r6 extrd,>= %r4,10,5,%r6 extrd,ev %r4,10,5,%r6 extrd,u, %r4,%sar,5,%r6 extrd,u,= %r4,%sar,5,%r6 extrd,u,< %r4,%sar,5,%r6 extrd,u,od %r4,%sar,5,%r6 extrd,u,tr %r4,%sar,5,%r6 extrd,u,<> %r4,%sar,5,%r6 extrd,u,>= %r4,%sar,5,%r6 extrd,u,ev %r4,%sar,5,%r6 extrd,s, %r4,%sar,5,%r6 extrd,s,= %r4,%sar,5,%r6 extrd,s,< %r4,%sar,5,%r6 extrd,s,od %r4,%sar,5,%r6 extrd,tr %r4,%sar,5,%r6 extrd,<> %r4,%sar,5,%r6 extrd,>= %r4,%sar,5,%r6 extrd,*ev %r4,%sar,5,%r6
stsp/binutils-ia16	3,568	gas/testsuite/gas/hppa/basic/add.s	.level 1.1 .code .align 4 ; Basic add/sh?add instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. add %r4,%r5,%r6 add,= %r4,%r5,%r6 add,< %r4,%r5,%r6 add,<= %r4,%r5,%r6 add,nuv %r4,%r5,%r6 add,znv %r4,%r5,%r6 add,sv %r4,%r5,%r6 add,od %r4,%r5,%r6 add,tr %r4,%r5,%r6 add,<> %r4,%r5,%r6 add,>= %r4,%r5,%r6 add,> %r4,%r5,%r6 add,uv %r4,%r5,%r6 add,vnz %r4,%r5,%r6 add,nsv %r4,%r5,%r6 add,ev %r4,%r5,%r6 addl %r4,%r5,%r6 addl,= %r4,%r5,%r6 addl,< %r4,%r5,%r6 addl,<= %r4,%r5,%r6 addl,nuv %r4,%r5,%r6 addl,znv %r4,%r5,%r6 addl,sv %r4,%r5,%r6 addl,od %r4,%r5,%r6 addl,tr %r4,%r5,%r6 addl,<> %r4,%r5,%r6 addl,>= %r4,%r5,%r6 addl,> %r4,%r5,%r6 addl,uv %r4,%r5,%r6 addl,vnz %r4,%r5,%r6 addl,nsv %r4,%r5,%r6 addl,ev %r4,%r5,%r6 addo %r4,%r5,%r6 addo,= %r4,%r5,%r6 addo,< %r4,%r5,%r6 addo,<= %r4,%r5,%r6 addo,nuv %r4,%r5,%r6 addo,znv %r4,%r5,%r6 addo,sv %r4,%r5,%r6 addo,od %r4,%r5,%r6 addo,tr %r4,%r5,%r6 addo,<> %r4,%r5,%r6 addo,>= %r4,%r5,%r6 addo,> %r4,%r5,%r6 addo,uv %r4,%r5,%r6 addo,vnz %r4,%r5,%r6 addo,nsv %r4,%r5,%r6 addo,ev %r4,%r5,%r6 addc %r4,%r5,%r6 addc,= %r4,%r5,%r6 addc,< %r4,%r5,%r6 addc,<= %r4,%r5,%r6 addc,nuv %r4,%r5,%r6 addc,znv %r4,%r5,%r6 addc,sv %r4,%r5,%r6 addc,od %r4,%r5,%r6 addc,tr %r4,%r5,%r6 addc,<> %r4,%r5,%r6 addc,>= %r4,%r5,%r6 addc,> %r4,%r5,%r6 addc,uv %r4,%r5,%r6 addc,vnz %r4,%r5,%r6 addc,nsv %r4,%r5,%r6 addc,ev %r4,%r5,%r6 addco %r4,%r5,%r6 addco,= %r4,%r5,%r6 addco,< %r4,%r5,%r6 addco,<= %r4,%r5,%r6 addco,nuv %r4,%r5,%r6 addco,znv %r4,%r5,%r6 addco,sv %r4,%r5,%r6 addco,od %r4,%r5,%r6 addco,tr %r4,%r5,%r6 addco,<> %r4,%r5,%r6 addco,>= %r4,%r5,%r6 addco,> %r4,%r5,%r6 addco,uv %r4,%r5,%r6 addco,vnz %r4,%r5,%r6 addco,nsv %r4,%r5,%r6 addco,ev %r4,%r5,%r6 add,l %r4,%r5,%r6 add,l,= %r4,%r5,%r6 add,l,< %r4,%r5,%r6 add,l,<= %r4,%r5,%r6 add,l,nuv %r4,%r5,%r6 add,l,znv %r4,%r5,%r6 add,l,sv %r4,%r5,%r6 add,l,od %r4,%r5,%r6 add,l,tr %r4,%r5,%r6 add,l,<> %r4,%r5,%r6 add,l,>= %r4,%r5,%r6 add,l,> %r4,%r5,%r6 add,l,uv %r4,%r5,%r6 add,l,vnz %r4,%r5,%r6 add,l,nsv %r4,%r5,%r6 add,l,ev %r4,%r5,%r6 add,tsv %r4,%r5,%r6 add,tsv,= %r4,%r5,%r6 add,tsv,< %r4,%r5,%r6 add,tsv,<= %r4,%r5,%r6 add,tsv,nuv %r4,%r5,%r6 add,tsv,znv %r4,%r5,%r6 add,tsv,sv %r4,%r5,%r6 add,tsv,od %r4,%r5,%r6 add,tsv,tr %r4,%r5,%r6 add,tsv,<> %r4,%r5,%r6 add,tsv,>= %r4,%r5,%r6 add,tsv,> %r4,%r5,%r6 add,tsv,uv %r4,%r5,%r6 add,tsv,vnz %r4,%r5,%r6 add,tsv,nsv %r4,%r5,%r6 add,tsv,ev %r4,%r5,%r6 add,c %r4,%r5,%r6 add,c,= %r4,%r5,%r6 add,c,< %r4,%r5,%r6 add,c,<= %r4,%r5,%r6 add,c,nuv %r4,%r5,%r6 add,c,znv %r4,%r5,%r6 add,c,sv %r4,%r5,%r6 add,c,od %r4,%r5,%r6 add,c,tr %r4,%r5,%r6 add,c,<> %r4,%r5,%r6 add,c,>= %r4,%r5,%r6 add,c,> %r4,%r5,%r6 add,c,uv %r4,%r5,%r6 add,c,vnz %r4,%r5,%r6 add,c,nsv %r4,%r5,%r6 add,c,ev %r4,%r5,%r6 add,c,tsv %r4,%r5,%r6 add,c,tsv,= %r4,%r5,%r6 add,c,tsv,< %r4,%r5,%r6 add,c,tsv,<= %r4,%r5,%r6 add,c,tsv,nuv %r4,%r5,%r6 add,c,tsv,znv %r4,%r5,%r6 add,c,tsv,sv %r4,%r5,%r6 add,c,tsv,od %r4,%r5,%r6 add,tsv,c,tr %r4,%r5,%r6 add,tsv,c,<> %r4,%r5,%r6 add,tsv,c,>= %r4,%r5,%r6 add,tsv,c,> %r4,%r5,%r6 add,tsv,c,uv %r4,%r5,%r6 add,tsv,c,vnz %r4,%r5,%r6 add,tsv,c,nsv %r4,%r5,%r6 add,tsv,c,ev %r4,%r5,%r6
stsp/binutils-ia16	1,037	gas/testsuite/gas/hppa/basic/extract2.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. extrw,u %r4,5,10,%r6 extrw,u,= %r4,5,10,%r6 extrw,u,< %r4,5,10,%r6 extrw,u,od %r4,5,10,%r6 extrw,u,tr %r4,5,10,%r6 extrw,u,<> %r4,5,10,%r6 extrw,u,>= %r4,5,10,%r6 extrw,u,ev %r4,5,10,%r6 extrw,s %r4,5,10,%r6 extrw,s,= %r4,5,10,%r6 extrw,s,< %r4,5,10,%r6 extrw,s,od %r4,5,10,%r6 extrw,tr %r4,5,10,%r6 extrw,<> %r4,5,10,%r6 extrw,>= %r4,5,10,%r6 extrw,ev %r4,5,10,%r6 extrw,u %r4,%sar,5,%r6 extrw,u,= %r4,%sar,5,%r6 extrw,u,< %r4,%sar,5,%r6 extrw,u,od %r4,%sar,5,%r6 extrw,u,tr %r4,%sar,5,%r6 extrw,u,<> %r4,%sar,5,%r6 extrw,u,>= %r4,%sar,5,%r6 extrw,u,ev %r4,%sar,5,%r6 extrw,s %r4,%sar,5,%r6 extrw,s,= %r4,%sar,5,%r6 extrw,s,< %r4,%sar,5,%r6 extrw,s,od %r4,%sar,5,%r6 extrw,tr %r4,%sar,5,%r6 extrw,<> %r4,%sar,5,%r6 extrw,>= %r4,%sar,5,%r6 extrw,ev %r4,%sar,5,%r6
stsp/binutils-ia16	1,823	gas/testsuite/gas/hppa/basic/deposit3.s	.LEVEL 2.0 .code .align 4 ; PA 2.0 Deposit instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. depd,z,* %r4,10,5,%r6 depd,z,= %r4,10,5,%r6 depd,z,< %r4,10,5,%r6 depd,z,od %r4,10,5,%r6 depd,z,tr %r4,10,5,%r6 depd,z,<> %r4,10,5,%r6 depd,z,>= %r4,10,5,%r6 depd,z,ev %r4,10,5,%r6 depd, %r4,10,5,%r6 depd,= %r4,10,5,%r6 depd,< %r4,10,5,%r6 depd,od %r4,10,5,%r6 depd,tr %r4,10,5,%r6 depd,<> %r4,10,5,%r6 depd,>= %r4,10,5,%r6 depd,ev %r4,10,5,%r6 depd,z, %r4,%sar,5,%r6 depd,z,= %r4,%sar,5,%r6 depd,z,< %r4,%sar,5,%r6 depd,z,od %r4,%sar,5,%r6 depd,z,tr %r4,%sar,5,%r6 depd,z,<> %r4,%sar,5,%r6 depd,z,>= %r4,%sar,5,%r6 depd,z,ev %r4,%sar,5,%r6 depd, %r4,%sar,5,%r6 depd,= %r4,%sar,5,%r6 depd,< %r4,%sar,5,%r6 depd,od %r4,%sar,5,%r6 depd,tr %r4,%sar,5,%r6 depd,<> %r4,%sar,5,%r6 depd,>= %r4,%sar,5,%r6 depd,ev %r4,%sar,5,%r6 depdi, -1,%sar,5,%r6 depdi,= -1,%sar,5,%r6 depdi,< -1,%sar,5,%r6 depdi,od -1,%sar,5,%r6 depdi,tr -1,%sar,5,%r6 depdi,<> -1,%sar,5,%r6 depdi,>= -1,%sar,5,%r6 depdi,ev -1,%sar,5,%r6 depdi,z, -1,%sar,5,%r6 depdi,z,= -1,%sar,5,%r6 depdi,z,< -1,%sar,5,%r6 depdi,z,od -1,%sar,5,%r6 depdi,z,tr -1,%sar,5,%r6 depdi,z,<> -1,%sar,5,%r6 depdi,z,>= -1,%sar,5,%r6 depdi,z,ev -1,%sar,5,%r6 depdi, -1,10,4,%r6 depdi,= -1,10,4,%r6 depdi,< -1,10,4,%r6 depdi,od -1,10,4,%r6 depdi,tr -1,10,4,%r6 depdi,<> -1,10,4,%r6 depdi,>= -1,10,4,%r6 depdi,ev -1,10,4,%r6 depdi,z, -1,10,4,%r6 depdi,z,= -1,10,4,%r6 depdi,z,< -1,10,4,%r6 depdi,z,od -1,10,4,%r6 depdi,z,tr -1,10,4,%r6 depdi,z,<> -1,10,4,%r6 depdi,z,>= -1,10,4,%r6 depdi,z,*ev -1,10,4,%r6
stsp/binutils-ia16	2,551	gas/testsuite/gas/hppa/basic/fp_fcmp.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fcmp,sgl,false? %fr4,%fr5 fcmp,sgl,false %fr4,%fr5 fcmp,sgl,? %fr4,%fr5 fcmp,sgl,!<=> %fr4,%fr5 fcmp,sgl,= %fr4,%fr5 fcmp,sgl,=T %fr4,%fr5 fcmp,sgl,?= %fr4,%fr5 fcmp,sgl,!<> %fr4,%fr5 fcmp,sgl,!?>= %fr4,%fr5 fcmp,sgl,< %fr4,%fr5 fcmp,sgl,?< %fr4,%fr5 fcmp,sgl,!>= %fr4,%fr5 fcmp,sgl,!?> %fr4,%fr5 fcmp,sgl,<= %fr4,%fr5 fcmp,sgl,?<= %fr4,%fr5 fcmp,sgl,!> %fr4,%fr5 fcmp,sgl,!?<= %fr4,%fr5 fcmp,sgl,> %fr4,%fr5 fcmp,sgl,?> %fr4,%fr5 fcmp,sgl,!<= %fr4,%fr5 fcmp,sgl,!?< %fr4,%fr5 fcmp,sgl,>= %fr4,%fr5 fcmp,sgl,?>= %fr4,%fr5 fcmp,sgl,!< %fr4,%fr5 fcmp,sgl,!?= %fr4,%fr5 fcmp,sgl,<> %fr4,%fr5 fcmp,sgl,!= %fr4,%fr5 fcmp,sgl,!=T %fr4,%fr5 fcmp,sgl,!? %fr4,%fr5 fcmp,sgl,<=> %fr4,%fr5 fcmp,sgl,true? %fr4,%fr5 fcmp,sgl,true %fr4,%fr5 fcmp,dbl,false? %fr4,%fr5 fcmp,dbl,false %fr4,%fr5 fcmp,dbl,? %fr4,%fr5 fcmp,dbl,!<=> %fr4,%fr5 fcmp,dbl,= %fr4,%fr5 fcmp,dbl,=T %fr4,%fr5 fcmp,dbl,?= %fr4,%fr5 fcmp,dbl,!<> %fr4,%fr5 fcmp,dbl,!?>= %fr4,%fr5 fcmp,dbl,< %fr4,%fr5 fcmp,dbl,?< %fr4,%fr5 fcmp,dbl,!>= %fr4,%fr5 fcmp,dbl,!?> %fr4,%fr5 fcmp,dbl,<= %fr4,%fr5 fcmp,dbl,?<= %fr4,%fr5 fcmp,dbl,!> %fr4,%fr5 fcmp,dbl,!?<= %fr4,%fr5 fcmp,dbl,> %fr4,%fr5 fcmp,dbl,?> %fr4,%fr5 fcmp,dbl,!<= %fr4,%fr5 fcmp,dbl,!?< %fr4,%fr5 fcmp,dbl,>= %fr4,%fr5 fcmp,dbl,?>= %fr4,%fr5 fcmp,dbl,!< %fr4,%fr5 fcmp,dbl,!?= %fr4,%fr5 fcmp,dbl,<> %fr4,%fr5 fcmp,dbl,!= %fr4,%fr5 fcmp,dbl,!=T %fr4,%fr5 fcmp,dbl,!? %fr4,%fr5 fcmp,dbl,<=> %fr4,%fr5 fcmp,dbl,true? %fr4,%fr5 fcmp,dbl,true %fr4,%fr5 fcmp,quad,false? %fr4,%fr5 fcmp,quad,false %fr4,%fr5 fcmp,quad,? %fr4,%fr5 fcmp,quad,!<=> %fr4,%fr5 fcmp,quad,= %fr4,%fr5 fcmp,quad,=T %fr4,%fr5 fcmp,quad,?= %fr4,%fr5 fcmp,quad,!<> %fr4,%fr5 fcmp,quad,!?>= %fr4,%fr5 fcmp,quad,< %fr4,%fr5 fcmp,quad,?< %fr4,%fr5 fcmp,quad,!>= %fr4,%fr5 fcmp,quad,!?> %fr4,%fr5 fcmp,quad,<= %fr4,%fr5 fcmp,quad,?<= %fr4,%fr5 fcmp,quad,!> %fr4,%fr5 fcmp,quad,!?<= %fr4,%fr5 fcmp,quad,> %fr4,%fr5 fcmp,quad,?> %fr4,%fr5 fcmp,quad,!<= %fr4,%fr5 fcmp,quad,!?< %fr4,%fr5 fcmp,quad,>= %fr4,%fr5 fcmp,quad,?>= %fr4,%fr5 fcmp,quad,!< %fr4,%fr5 fcmp,quad,!?= %fr4,%fr5 fcmp,quad,<> %fr4,%fr5 fcmp,quad,!= %fr4,%fr5 fcmp,quad,!=T %fr4,%fr5 fcmp,quad,!? %fr4,%fr5 fcmp,quad,<=> %fr4,%fr5 fcmp,quad,true? %fr4,%fr5 fcmp,quad,true %fr4,%fr5
stsp/binutils-ia16	5,704	gas/testsuite/gas/hppa/basic/branch.s	.level 1.1 .code .align 4 ; More branching instructions than you ever knew what to do with. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. branch_tests: bl branch_tests,%r2 bl,n branch_tests,%r2 b branch_tests b,n branch_tests gate branch_tests,%r2 gate,n branch_tests,%r2 blr %r4,%r2 blr,n %r4,%r2 blr %r4,%r0 blr,n %r4,%r0 bv %r0(%r2) bv,n %r0(%r2) be 0x1234(%sr1,%r2) be,n 0x1234(%sr1,%r2) ble 0x1234(%sr1,%r2) ble,n 0x1234(%sr1,%r2) movb_tests: movb %r4,%r26,movb_tests movb,= %r4,%r26,movb_tests movb,< %r4,%r26,movb_tests movb,od %r4,%r26,movb_tests movb,tr %r4,%r26,movb_tests movb,<> %r4,%r26,movb_tests movb,>= %r4,%r26,movb_tests movb,ev %r4,%r26,movb_tests movb_nullified_tests: movb,n %r4,%r26,movb_tests movb,=,n %r4,%r26,movb_tests movb,<,n %r4,%r26,movb_tests movb,od,n %r4,%r26,movb_tests movb,tr,n %r4,%r26,movb_tests movb,<>,n %r4,%r26,movb_tests movb,>=,n %r4,%r26,movb_tests movb,ev,n %r4,%r26,movb_tests movib_tests: movib 5,%r26,movib_tests movib,= 5,%r26,movib_tests movib,< 5,%r26,movib_tests movib,od 5,%r26,movib_tests movib,tr 5,%r26,movib_tests movib,<> 5,%r26,movib_tests movib,>= 5,%r26,movib_tests movib,ev 5,%r26,movib_tests movib_nullified_tests: movib,n 5,%r26,movib_tests movib,=,n 5,%r26,movib_tests movib,<,n 5,%r26,movib_tests movib,od,n 5,%r26,movib_tests movib,tr,n 5,%r26,movib_tests movib,<>,n 5,%r26,movib_tests movib,>=,n 5,%r26,movib_tests movib,ev,n 5,%r26,movib_tests comb_tests: comb %r0,%r4,comb_tests comb,= %r0,%r4,comb_tests comb,< %r0,%r4,comb_tests comb,<= %r0,%r4,comb_tests comb,<< %r0,%r4,comb_tests comb,<<= %r0,%r4,comb_tests comb,sv %r0,%r4,comb_tests comb,od %r0,%r4,comb_tests comb,tr %r0,%r4,comb_tests comb,<> %r0,%r4,comb_tests comb,>= %r0,%r4,comb_tests comb,> %r0,%r4,comb_tests comb,>>= %r0,%r4,comb_tests comb,>> %r0,%r4,comb_tests comb,nsv %r0,%r4,comb_tests comb,ev %r0,%r4,comb_tests comb_nullified_tests: comb,n %r0,%r4,comb_tests comb,=,n %r0,%r4,comb_tests comb,<,n %r0,%r4,comb_tests comb,<=,n %r0,%r4,comb_tests comb,<<,n %r0,%r4,comb_tests comb,<<=,n %r0,%r4,comb_tests comb,sv,n %r0,%r4,comb_tests comb,od,n %r0,%r4,comb_tests comb,tr,n %r0,%r4,comb_tests comb,<>,n %r0,%r4,comb_tests comb,>=,n %r0,%r4,comb_tests comb,>,n %r0,%r4,comb_tests comb,>>=,n %r0,%r4,comb_tests comb,>>,n %r0,%r4,comb_tests comb,nsv,n %r0,%r4,comb_tests comb,ev,n %r0,%r4,comb_tests comib_tests: comib 0,%r4,comib_tests comib,< 0,%r4,comib_tests comib,<= 0,%r4,comib_tests comib,<< 0,%r4,comib_tests comib,<<= 0,%r4,comib_tests comib,sv 0,%r4,comib_tests comib,od 0,%r4,comib_tests comib,tr 0,%r4,comib_tests comib,<> 0,%r4,comib_tests comib,>= 0,%r4,comib_tests comib,> 0,%r4,comib_tests comib,>>= 0,%r4,comib_tests comib,>> 0,%r4,comib_tests comib,nsv 0,%r4,comib_tests comib,ev 0,%r4,comb_tests comib_nullified_tests: comib,n 0,%r4,comib_tests comib,=,n 0,%r4,comib_tests comib,<,n 0,%r4,comib_tests comib,<=,n 0,%r4,comib_tests comib,<<,n 0,%r4,comib_tests comib,<<=,n 0,%r4,comib_tests comib,sv,n 0,%r4,comib_tests comib,od,n 0,%r4,comib_tests comib,tr,n 0,%r4,comib_tests comib,<>,n 0,%r4,comib_tests comib,>=,n 0,%r4,comib_tests comib,>,n 0,%r4,comib_tests comib,>>=,n 0,%r4,comib_tests comib,>>,n 0,%r4,comib_tests comib,nsv,n 0,%r4,comib_tests comib,ev,n 0,%r4,comib_tests addb_tests: addb %r1,%r4,addb_tests addb,= %r1,%r4,addb_tests addb,< %r1,%r4,addb_tests addb,<= %r1,%r4,addb_tests addb,nuv %r1,%r4,addb_tests addb,znv %r1,%r4,addb_tests addb,sv %r1,%r4,addb_tests addb,od %r1,%r4,addb_tests addb,tr %r1,%r4,addb_tests addb,<> %r1,%r4,addb_tests addb,>= %r1,%r4,addb_tests addb,> %r1,%r4,addb_tests addb,uv %r1,%r4,addb_tests addb,vnz %r1,%r4,addb_tests addb,nsv %r1,%r4,addb_tests addb,ev %r1,%r4,addb_tests addb_nullified_tests: addb,n %r1,%r4,addb_tests addb,=,n %r1,%r4,addb_tests addb,<,n %r1,%r4,addb_tests addb,<=,n %r1,%r4,addb_tests addb,nuv,n %r1,%r4,addb_tests addb,znv,n %r1,%r4,addb_tests addb,sv,n %r1,%r4,addb_tests addb,od,n %r1,%r4,addb_tests addb,tr,n %r1,%r4,addb_tests addb,<>,n %r1,%r4,addb_tests addb,>=,n %r1,%r4,addb_tests addb,>,n %r1,%r4,addb_tests addb,uv,n %r1,%r4,addb_tests addb,vnz,n %r1,%r4,addb_tests addb,nsv,n %r1,%r4,addb_tests addb,ev,n %r1,%r4,addb_tests addib_tests: addib -1,%r4,addib_tests addib,= -1,%r4,addib_tests addib,< -1,%r4,addib_tests addib,<= -1,%r4,addib_tests addib,nuv -1,%r4,addib_tests addib,znv -1,%r4,addib_tests addib,sv -1,%r4,addib_tests addib,od -1,%r4,addib_tests addib,tr -1,%r4,addib_tests addib,<> -1,%r4,addib_tests addib,>= -1,%r4,addib_tests addib,> -1,%r4,addib_tests addib,uv -1,%r4,addib_tests addib,vnz -1,%r4,addib_tests addib,nsv -1,%r4,addib_tests addib,ev -1,%r4,comb_tests addib_nullified_tests: addib,n -1,%r4,addib_tests addib,=,n -1,%r4,addib_tests addib,<,n -1,%r4,addib_tests addib,<=,n -1,%r4,addib_tests addib,nuv,n -1,%r4,addib_tests addib,znv,n -1,%r4,addib_tests addib,sv,n -1,%r4,addib_tests addib,od,n -1,%r4,addib_tests addib,tr,n -1,%r4,addib_tests addib,<>,n -1,%r4,addib_tests addib,>=,n -1,%r4,addib_tests addib,>,n -1,%r4,addib_tests addib,uv,n -1,%r4,addib_tests addib,vnz,n -1,%r4,addib_tests addib,nsv,n -1,%r4,addib_tests addib,ev,n -1,%r4,addib_tests ; Needs to check lots of stuff (like corner bit cases) bb_tests: bvb,< %r4,bb_tests bvb,>= %r4,bb_tests bvb,<,n %r4,bb_tests bvb,>=,n %r4,bb_tests bb,< %r4,5,bb_tests bb,>= %r4,5,bb_tests bb,<,n %r4,5,bb_tests bb,>=,n %r4,5,bb_tests
stsp/binutils-ia16	2,409	gas/testsuite/gas/hppa/basic/add2.s	.LEVEL 2.0 .code .align 4 ; Basic add/sh?add instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. add,* %r4,%r5,%r6 add,= %r4,%r5,%r6 add,< %r4,%r5,%r6 add,<= %r4,%r5,%r6 add,nuv %r4,%r5,%r6 add,znv %r4,%r5,%r6 add,sv %r4,%r5,%r6 add,od %r4,%r5,%r6 add,tr %r4,%r5,%r6 add,<> %r4,%r5,%r6 add,>= %r4,%r5,%r6 add,> %r4,%r5,%r6 add,uv %r4,%r5,%r6 add,vnz %r4,%r5,%r6 add,nsv %r4,%r5,%r6 add,ev %r4,%r5,%r6 add,l, %r4,%r5,%r6 add,l,= %r4,%r5,%r6 add,l,< %r4,%r5,%r6 add,l,<= %r4,%r5,%r6 add,l,nuv %r4,%r5,%r6 add,l,znv %r4,%r5,%r6 add,l,sv %r4,%r5,%r6 add,l,od %r4,%r5,%r6 add,l,tr %r4,%r5,%r6 add,l,<> %r4,%r5,%r6 add,l,>= %r4,%r5,%r6 add,l,> %r4,%r5,%r6 add,l,uv %r4,%r5,%r6 add,l,vnz %r4,%r5,%r6 add,l,nsv %r4,%r5,%r6 add,l,ev %r4,%r5,%r6 add,tsv, %r4,%r5,%r6 add,tsv,= %r4,%r5,%r6 add,tsv,< %r4,%r5,%r6 add,tsv,<= %r4,%r5,%r6 add,tsv,nuv %r4,%r5,%r6 add,tsv,znv %r4,%r5,%r6 add,tsv,sv %r4,%r5,%r6 add,tsv,od %r4,%r5,%r6 add,tsv,tr %r4,%r5,%r6 add,tsv,<> %r4,%r5,%r6 add,tsv,>= %r4,%r5,%r6 add,tsv,> %r4,%r5,%r6 add,tsv,uv %r4,%r5,%r6 add,tsv,vnz %r4,%r5,%r6 add,tsv,nsv %r4,%r5,%r6 add,tsv,ev %r4,%r5,%r6 add,dc, %r4,%r5,%r6 add,dc,= %r4,%r5,%r6 add,dc,< %r4,%r5,%r6 add,dc,<= %r4,%r5,%r6 add,dc,nuv %r4,%r5,%r6 add,dc,znv %r4,%r5,%r6 add,dc,sv %r4,%r5,%r6 add,dc,od %r4,%r5,%r6 add,dc,tr %r4,%r5,%r6 add,dc,<> %r4,%r5,%r6 add,dc,>= %r4,%r5,%r6 add,dc,> %r4,%r5,%r6 add,dc,uv %r4,%r5,%r6 add,dc,vnz %r4,%r5,%r6 add,dc,nsv %r4,%r5,%r6 add,dc,ev %r4,%r5,%r6 add,dc,tsv, %r4,%r5,%r6 add,dc,tsv,= %r4,%r5,%r6 add,dc,tsv,< %r4,%r5,%r6 add,dc,tsv,<= %r4,%r5,%r6 add,dc,tsv,nuv %r4,%r5,%r6 add,dc,tsv,znv %r4,%r5,%r6 add,dc,tsv,sv %r4,%r5,%r6 add,dc,tsv,od %r4,%r5,%r6 add,tsv,dc,tr %r4,%r5,%r6 add,tsv,dc,<> %r4,%r5,%r6 add,tsv,dc,>= %r4,%r5,%r6 add,tsv,dc,> %r4,%r5,%r6 add,tsv,dc,uv %r4,%r5,%r6 add,tsv,dc,vnz %r4,%r5,%r6 add,tsv,dc,nsv %r4,%r5,%r6 add,tsv,dc,*ev %r4,%r5,%r6 ;; PR gas/11395: Check for the correct assembly ;; of unconditional 32-bit and 64-bit add instructions. add %r1,%r1,%r1 add,dc %r1,%r1,%r1
stsp/binutils-ia16	1,272	gas/testsuite/gas/hppa/basic/unit.s	.level 1.1 .code .align 4 ; Basic unit instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. uxor %r4,%r5,%r6 uxor,sbz %r4,%r5,%r6 uxor,shz %r4,%r5,%r6 uxor,tr %r4,%r5,%r6 uxor,nbz %r4,%r5,%r6 uxor,nhz %r4,%r5,%r6 uaddcm %r4,%r5,%r6 uaddcm,sbz %r4,%r5,%r6 uaddcm,shz %r4,%r5,%r6 uaddcm,sdc %r4,%r5,%r6 uaddcm,sbc %r4,%r5,%r6 uaddcm,shc %r4,%r5,%r6 uaddcm,tr %r4,%r5,%r6 uaddcm,nbz %r4,%r5,%r6 uaddcm,nhz %r4,%r5,%r6 uaddcm,ndc %r4,%r5,%r6 uaddcm,nbc %r4,%r5,%r6 uaddcm,nhc %r4,%r5,%r6 uaddcmt %r4,%r5,%r6 uaddcmt,sbz %r4,%r5,%r6 uaddcmt,shz %r4,%r5,%r6 uaddcmt,sdc %r4,%r5,%r6 uaddcmt,sbc %r4,%r5,%r6 uaddcmt,shc %r4,%r5,%r6 uaddcmt,tr %r4,%r5,%r6 uaddcmt,nbz %r4,%r5,%r6 uaddcmt,nhz %r4,%r5,%r6 uaddcmt,ndc %r4,%r5,%r6 uaddcmt,nbc %r4,%r5,%r6 uaddcmt,nhc %r4,%r5,%r6 uaddcm,tc %r4,%r5,%r6 uaddcm,tc,sbz %r4,%r5,%r6 uaddcm,tc,shz %r4,%r5,%r6 uaddcm,tc,sdc %r4,%r5,%r6 uaddcm,tc,sbc %r4,%r5,%r6 uaddcm,tc,shc %r4,%r5,%r6 uaddcm,tc,tr %r4,%r5,%r6 uaddcm,tc,nbz %r4,%r5,%r6 uaddcm,tc,nhz %r4,%r5,%r6 uaddcm,tc,ndc %r4,%r5,%r6 uaddcm,tc,nbc %r4,%r5,%r6 uaddcm,tc,nhc %r4,%r5,%r6
stsp/binutils-ia16	1,418	gas/testsuite/gas/hppa/basic/sh1add.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sh1add %r4,%r5,%r6 sh1add,= %r4,%r5,%r6 sh1add,< %r4,%r5,%r6 sh1add,<= %r4,%r5,%r6 sh1add,nuv %r4,%r5,%r6 sh1add,znv %r4,%r5,%r6 sh1add,sv %r4,%r5,%r6 sh1add,od %r4,%r5,%r6 sh1add,tr %r4,%r5,%r6 sh1add,<> %r4,%r5,%r6 sh1add,>= %r4,%r5,%r6 sh1add,> %r4,%r5,%r6 sh1add,uv %r4,%r5,%r6 sh1add,vnz %r4,%r5,%r6 sh1add,nsv %r4,%r5,%r6 sh1add,ev %r4,%r5,%r6 sh1addl %r4,%r5,%r6 sh1addl,= %r4,%r5,%r6 sh1addl,< %r4,%r5,%r6 sh1addl,<= %r4,%r5,%r6 sh1addl,nuv %r4,%r5,%r6 sh1addl,znv %r4,%r5,%r6 sh1addl,sv %r4,%r5,%r6 sh1addl,od %r4,%r5,%r6 sh1addl,tr %r4,%r5,%r6 sh1addl,<> %r4,%r5,%r6 sh1addl,>= %r4,%r5,%r6 sh1addl,> %r4,%r5,%r6 sh1addl,uv %r4,%r5,%r6 sh1addl,vnz %r4,%r5,%r6 sh1addl,nsv %r4,%r5,%r6 sh1addl,ev %r4,%r5,%r6 sh1addo %r4,%r5,%r6 sh1addo,= %r4,%r5,%r6 sh1addo,< %r4,%r5,%r6 sh1addo,<= %r4,%r5,%r6 sh1addo,nuv %r4,%r5,%r6 sh1addo,znv %r4,%r5,%r6 sh1addo,sv %r4,%r5,%r6 sh1addo,od %r4,%r5,%r6 sh1addo,tr %r4,%r5,%r6 sh1addo,<> %r4,%r5,%r6 sh1addo,>= %r4,%r5,%r6 sh1addo,> %r4,%r5,%r6 sh1addo,uv %r4,%r5,%r6 sh1addo,vnz %r4,%r5,%r6 sh1addo,nsv %r4,%r5,%r6 sh1addo,ev %r4,%r5,%r6
stsp/binutils-ia16	4,210	gas/testsuite/gas/hppa/basic/sub.s	.level 1.1 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sub %r4,%r5,%r6 sub,= %r4,%r5,%r6 sub,< %r4,%r5,%r6 sub,<= %r4,%r5,%r6 sub,<< %r4,%r5,%r6 sub,<<= %r4,%r5,%r6 sub,sv %r4,%r5,%r6 sub,od %r4,%r5,%r6 sub,tr %r4,%r5,%r6 sub,<> %r4,%r5,%r6 sub,>= %r4,%r5,%r6 sub,> %r4,%r5,%r6 sub,>>= %r4,%r5,%r6 sub,>> %r4,%r5,%r6 sub,nsv %r4,%r5,%r6 sub,ev %r4,%r5,%r6 subo %r4,%r5,%r6 subo,= %r4,%r5,%r6 subo,< %r4,%r5,%r6 subo,<= %r4,%r5,%r6 subo,<< %r4,%r5,%r6 subo,<<= %r4,%r5,%r6 subo,sv %r4,%r5,%r6 subo,od %r4,%r5,%r6 subo,tr %r4,%r5,%r6 subo,<> %r4,%r5,%r6 subo,>= %r4,%r5,%r6 subo,> %r4,%r5,%r6 subo,>>= %r4,%r5,%r6 subo,>> %r4,%r5,%r6 subo,nsv %r4,%r5,%r6 subo,ev %r4,%r5,%r6 subb %r4,%r5,%r6 subb,= %r4,%r5,%r6 subb,< %r4,%r5,%r6 subb,<= %r4,%r5,%r6 subb,<< %r4,%r5,%r6 subb,<<= %r4,%r5,%r6 subb,sv %r4,%r5,%r6 subb,od %r4,%r5,%r6 subb,tr %r4,%r5,%r6 subb,<> %r4,%r5,%r6 subb,>= %r4,%r5,%r6 subb,> %r4,%r5,%r6 subb,>>= %r4,%r5,%r6 subb,>> %r4,%r5,%r6 subb,nsv %r4,%r5,%r6 subb,ev %r4,%r5,%r6 subbo %r4,%r5,%r6 subbo,= %r4,%r5,%r6 subbo,< %r4,%r5,%r6 subbo,<= %r4,%r5,%r6 subbo,<< %r4,%r5,%r6 subbo,<<= %r4,%r5,%r6 subbo,sv %r4,%r5,%r6 subbo,od %r4,%r5,%r6 subbo,tr %r4,%r5,%r6 subbo,<> %r4,%r5,%r6 subbo,>= %r4,%r5,%r6 subbo,> %r4,%r5,%r6 subbo,>>= %r4,%r5,%r6 subbo,>> %r4,%r5,%r6 subbo,nsv %r4,%r5,%r6 subbo,ev %r4,%r5,%r6 subt %r4,%r5,%r6 subt,= %r4,%r5,%r6 subt,< %r4,%r5,%r6 subt,<= %r4,%r5,%r6 subt,<< %r4,%r5,%r6 subt,<<= %r4,%r5,%r6 subt,sv %r4,%r5,%r6 subt,od %r4,%r5,%r6 subt,tr %r4,%r5,%r6 subt,<> %r4,%r5,%r6 subt,>= %r4,%r5,%r6 subt,> %r4,%r5,%r6 subt,>>= %r4,%r5,%r6 subt,>> %r4,%r5,%r6 subt,nsv %r4,%r5,%r6 subt,ev %r4,%r5,%r6 subto %r4,%r5,%r6 subto,= %r4,%r5,%r6 subto,< %r4,%r5,%r6 subto,<= %r4,%r5,%r6 subto,<< %r4,%r5,%r6 subto,<<= %r4,%r5,%r6 subto,sv %r4,%r5,%r6 subto,od %r4,%r5,%r6 subto,tr %r4,%r5,%r6 subto,<> %r4,%r5,%r6 subto,>= %r4,%r5,%r6 subto,> %r4,%r5,%r6 subto,>>= %r4,%r5,%r6 subto,>> %r4,%r5,%r6 subto,nsv %r4,%r5,%r6 subto,ev %r4,%r5,%r6 sub,tsv %r4,%r5,%r6 sub,tsv,= %r4,%r5,%r6 sub,tsv,< %r4,%r5,%r6 sub,tsv,<= %r4,%r5,%r6 sub,tsv,<< %r4,%r5,%r6 sub,tsv,<<= %r4,%r5,%r6 sub,tsv,sv %r4,%r5,%r6 sub,tsv,od %r4,%r5,%r6 sub,tsv,tr %r4,%r5,%r6 sub,tsv,<> %r4,%r5,%r6 sub,tsv,>= %r4,%r5,%r6 sub,tsv,> %r4,%r5,%r6 sub,tsv,>>= %r4,%r5,%r6 sub,tsv,>> %r4,%r5,%r6 sub,tsv,nsv %r4,%r5,%r6 sub,tsv,ev %r4,%r5,%r6 sub,b %r4,%r5,%r6 sub,b,= %r4,%r5,%r6 sub,b,< %r4,%r5,%r6 sub,b,<= %r4,%r5,%r6 sub,b,<< %r4,%r5,%r6 sub,b,<<= %r4,%r5,%r6 sub,b,sv %r4,%r5,%r6 sub,b,od %r4,%r5,%r6 sub,b,tr %r4,%r5,%r6 sub,b,<> %r4,%r5,%r6 sub,b,>= %r4,%r5,%r6 sub,b,> %r4,%r5,%r6 sub,b,>>= %r4,%r5,%r6 sub,b,>> %r4,%r5,%r6 sub,b,nsv %r4,%r5,%r6 sub,b,ev %r4,%r5,%r6 sub,b,tsv %r4,%r5,%r6 sub,b,tsv,= %r4,%r5,%r6 sub,b,tsv,< %r4,%r5,%r6 sub,b,tsv,<= %r4,%r5,%r6 sub,b,tsv,<< %r4,%r5,%r6 sub,b,tsv,<<= %r4,%r5,%r6 sub,b,tsv,sv %r4,%r5,%r6 sub,b,tsv,od %r4,%r5,%r6 sub,tsv,b,tr %r4,%r5,%r6 sub,tsv,b,<> %r4,%r5,%r6 sub,tsv,b,>= %r4,%r5,%r6 sub,tsv,b,> %r4,%r5,%r6 sub,tsv,b,>>= %r4,%r5,%r6 sub,tsv,b,>> %r4,%r5,%r6 sub,tsv,b,nsv %r4,%r5,%r6 sub,tsv,b,ev %r4,%r5,%r6 sub,tc %r4,%r5,%r6 sub,tc,= %r4,%r5,%r6 sub,tc,< %r4,%r5,%r6 sub,tc,<= %r4,%r5,%r6 sub,tc,<< %r4,%r5,%r6 sub,tc,<<= %r4,%r5,%r6 sub,tc,sv %r4,%r5,%r6 sub,tc,od %r4,%r5,%r6 sub,tc,tr %r4,%r5,%r6 sub,tc,<> %r4,%r5,%r6 sub,tc,>= %r4,%r5,%r6 sub,tc,> %r4,%r5,%r6 sub,tc,>>= %r4,%r5,%r6 sub,tc,>> %r4,%r5,%r6 sub,tc,nsv %r4,%r5,%r6 sub,tc,ev %r4,%r5,%r6 sub,tc,tsv %r4,%r5,%r6 sub,tc,tsv,= %r4,%r5,%r6 sub,tc,tsv,< %r4,%r5,%r6 sub,tc,tsv,<= %r4,%r5,%r6 sub,tc,tsv,<< %r4,%r5,%r6 sub,tc,tsv,<<= %r4,%r5,%r6 sub,tc,tsv,sv %r4,%r5,%r6 sub,tc,tsv,od %r4,%r5,%r6 sub,tsv,tc,tr %r4,%r5,%r6 sub,tsv,tc,<> %r4,%r5,%r6 sub,tsv,tc,>= %r4,%r5,%r6 sub,tsv,tc,> %r4,%r5,%r6 sub,tsv,tc,>>= %r4,%r5,%r6 sub,tsv,tc,>> %r4,%r5,%r6 sub,tsv,tc,nsv %r4,%r5,%r6 sub,tsv,tc,ev %r4,%r5,%r6
stsp/binutils-ia16	4,422	gas/testsuite/gas/hppa/basic/shladd2.s	.LEVEL 2.0 .code .align 4 ; PA2.0 shladd instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. shladd,* %r4,1,%r5,%r6 shladd,= %r4,1,%r5,%r6 shladd,< %r4,1,%r5,%r6 shladd,<= %r4,1,%r5,%r6 shladd,nuv %r4,1,%r5,%r6 shladd,znv %r4,1,%r5,%r6 shladd,sv %r4,1,%r5,%r6 shladd,od %r4,1,%r5,%r6 shladd,tr %r4,1,%r5,%r6 shladd,<> %r4,1,%r5,%r6 shladd,>= %r4,1,%r5,%r6 shladd,> %r4,1,%r5,%r6 shladd,uv %r4,1,%r5,%r6 shladd,vnz %r4,1,%r5,%r6 shladd,nsv %r4,1,%r5,%r6 shladd,ev %r4,1,%r5,%r6 shladd,l, %r4,1,%r5,%r6 shladd,l,= %r4,1,%r5,%r6 shladd,l,< %r4,1,%r5,%r6 shladd,l,<= %r4,1,%r5,%r6 shladd,l,nuv %r4,1,%r5,%r6 shladd,l,znv %r4,1,%r5,%r6 shladd,l,sv %r4,1,%r5,%r6 shladd,l,od %r4,1,%r5,%r6 shladd,l,tr %r4,1,%r5,%r6 shladd,l,<> %r4,1,%r5,%r6 shladd,l,>= %r4,1,%r5,%r6 shladd,l,> %r4,1,%r5,%r6 shladd,l,uv %r4,1,%r5,%r6 shladd,l,vnz %r4,1,%r5,%r6 shladd,l,nsv %r4,1,%r5,%r6 shladd,l,ev %r4,1,%r5,%r6 shladd,tsv, %r4,1,%r5,%r6 shladd,tsv,= %r4,1,%r5,%r6 shladd,tsv,< %r4,1,%r5,%r6 shladd,tsv,<= %r4,1,%r5,%r6 shladd,tsv,nuv %r4,1,%r5,%r6 shladd,tsv,znv %r4,1,%r5,%r6 shladd,tsv,sv %r4,1,%r5,%r6 shladd,tsv,od %r4,1,%r5,%r6 shladd,tsv,tr %r4,1,%r5,%r6 shladd,tsv,<> %r4,1,%r5,%r6 shladd,tsv,>= %r4,1,%r5,%r6 shladd,tsv,> %r4,1,%r5,%r6 shladd,tsv,uv %r4,1,%r5,%r6 shladd,tsv,vnz %r4,1,%r5,%r6 shladd,tsv,nsv %r4,1,%r5,%r6 shladd,tsv,ev %r4,1,%r5,%r6 shladd, %r4,2,%r5,%r6 shladd,= %r4,2,%r5,%r6 shladd,< %r4,2,%r5,%r6 shladd,<= %r4,2,%r5,%r6 shladd,nuv %r4,2,%r5,%r6 shladd,znv %r4,2,%r5,%r6 shladd,sv %r4,2,%r5,%r6 shladd,od %r4,2,%r5,%r6 shladd,tr %r4,2,%r5,%r6 shladd,<> %r4,2,%r5,%r6 shladd,>= %r4,2,%r5,%r6 shladd,> %r4,2,%r5,%r6 shladd,uv %r4,2,%r5,%r6 shladd,vnz %r4,2,%r5,%r6 shladd,nsv %r4,2,%r5,%r6 shladd,ev %r4,2,%r5,%r6 shladd,l, %r4,2,%r5,%r6 shladd,l,= %r4,2,%r5,%r6 shladd,l,< %r4,2,%r5,%r6 shladd,l,<= %r4,2,%r5,%r6 shladd,l,nuv %r4,2,%r5,%r6 shladd,l,znv %r4,2,%r5,%r6 shladd,l,sv %r4,2,%r5,%r6 shladd,l,od %r4,2,%r5,%r6 shladd,l,tr %r4,2,%r5,%r6 shladd,l,<> %r4,2,%r5,%r6 shladd,l,>= %r4,2,%r5,%r6 shladd,l,> %r4,2,%r5,%r6 shladd,l,uv %r4,2,%r5,%r6 shladd,l,vnz %r4,2,%r5,%r6 shladd,l,nsv %r4,2,%r5,%r6 shladd,l,ev %r4,2,%r5,%r6 shladd,tsv, %r4,2,%r5,%r6 shladd,tsv,= %r4,2,%r5,%r6 shladd,tsv,< %r4,2,%r5,%r6 shladd,tsv,<= %r4,2,%r5,%r6 shladd,tsv,nuv %r4,2,%r5,%r6 shladd,tsv,znv %r4,2,%r5,%r6 shladd,tsv,sv %r4,2,%r5,%r6 shladd,tsv,od %r4,2,%r5,%r6 shladd,tsv,tr %r4,2,%r5,%r6 shladd,tsv,<> %r4,2,%r5,%r6 shladd,tsv,>= %r4,2,%r5,%r6 shladd,tsv,> %r4,2,%r5,%r6 shladd,tsv,uv %r4,2,%r5,%r6 shladd,tsv,vnz %r4,2,%r5,%r6 shladd,tsv,nsv %r4,2,%r5,%r6 shladd,tsv,ev %r4,2,%r5,%r6 shladd, %r4,3,%r5,%r6 shladd,= %r4,3,%r5,%r6 shladd,< %r4,3,%r5,%r6 shladd,<= %r4,3,%r5,%r6 shladd,nuv %r4,3,%r5,%r6 shladd,znv %r4,3,%r5,%r6 shladd,sv %r4,3,%r5,%r6 shladd,od %r4,3,%r5,%r6 shladd,tr %r4,3,%r5,%r6 shladd,<> %r4,3,%r5,%r6 shladd,>= %r4,3,%r5,%r6 shladd,> %r4,3,%r5,%r6 shladd,uv %r4,3,%r5,%r6 shladd,vnz %r4,3,%r5,%r6 shladd,nsv %r4,3,%r5,%r6 shladd,ev %r4,3,%r5,%r6 shladd,l, %r4,3,%r5,%r6 shladd,l,= %r4,3,%r5,%r6 shladd,l,< %r4,3,%r5,%r6 shladd,l,<= %r4,3,%r5,%r6 shladd,l,nuv %r4,3,%r5,%r6 shladd,l,znv %r4,3,%r5,%r6 shladd,l,sv %r4,3,%r5,%r6 shladd,l,od %r4,3,%r5,%r6 shladd,l,tr %r4,3,%r5,%r6 shladd,l,<> %r4,3,%r5,%r6 shladd,l,>= %r4,3,%r5,%r6 shladd,l,> %r4,3,%r5,%r6 shladd,l,uv %r4,3,%r5,%r6 shladd,l,vnz %r4,3,%r5,%r6 shladd,l,nsv %r4,3,%r5,%r6 shladd,l,ev %r4,3,%r5,%r6 shladd,tsv, %r4,3,%r5,%r6 shladd,tsv,= %r4,3,%r5,%r6 shladd,tsv,< %r4,3,%r5,%r6 shladd,tsv,<= %r4,3,%r5,%r6 shladd,tsv,nuv %r4,3,%r5,%r6 shladd,tsv,znv %r4,3,%r5,%r6 shladd,tsv,sv %r4,3,%r5,%r6 shladd,tsv,od %r4,3,%r5,%r6 shladd,tsv,tr %r4,3,%r5,%r6 shladd,tsv,<> %r4,3,%r5,%r6 shladd,tsv,>= %r4,3,%r5,%r6 shladd,tsv,> %r4,3,%r5,%r6 shladd,tsv,uv %r4,3,%r5,%r6 shladd,tsv,vnz %r4,3,%r5,%r6 shladd,tsv,nsv %r4,3,%r5,%r6 shladd,tsv,*ev %r4,3,%r5,%r6
stsp/binutils-ia16	1,418	gas/testsuite/gas/hppa/basic/sh3add.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sh3add %r4,%r5,%r6 sh3add,= %r4,%r5,%r6 sh3add,< %r4,%r5,%r6 sh3add,<= %r4,%r5,%r6 sh3add,nuv %r4,%r5,%r6 sh3add,znv %r4,%r5,%r6 sh3add,sv %r4,%r5,%r6 sh3add,od %r4,%r5,%r6 sh3add,tr %r4,%r5,%r6 sh3add,<> %r4,%r5,%r6 sh3add,>= %r4,%r5,%r6 sh3add,> %r4,%r5,%r6 sh3add,uv %r4,%r5,%r6 sh3add,vnz %r4,%r5,%r6 sh3add,nsv %r4,%r5,%r6 sh3add,ev %r4,%r5,%r6 sh3addl %r4,%r5,%r6 sh3addl,= %r4,%r5,%r6 sh3addl,< %r4,%r5,%r6 sh3addl,<= %r4,%r5,%r6 sh3addl,nuv %r4,%r5,%r6 sh3addl,znv %r4,%r5,%r6 sh3addl,sv %r4,%r5,%r6 sh3addl,od %r4,%r5,%r6 sh3addl,tr %r4,%r5,%r6 sh3addl,<> %r4,%r5,%r6 sh3addl,>= %r4,%r5,%r6 sh3addl,> %r4,%r5,%r6 sh3addl,uv %r4,%r5,%r6 sh3addl,vnz %r4,%r5,%r6 sh3addl,nsv %r4,%r5,%r6 sh3addl,ev %r4,%r5,%r6 sh3addo %r4,%r5,%r6 sh3addo,= %r4,%r5,%r6 sh3addo,< %r4,%r5,%r6 sh3addo,<= %r4,%r5,%r6 sh3addo,nuv %r4,%r5,%r6 sh3addo,znv %r4,%r5,%r6 sh3addo,sv %r4,%r5,%r6 sh3addo,od %r4,%r5,%r6 sh3addo,tr %r4,%r5,%r6 sh3addo,<> %r4,%r5,%r6 sh3addo,>= %r4,%r5,%r6 sh3addo,> %r4,%r5,%r6 sh3addo,uv %r4,%r5,%r6 sh3addo,vnz %r4,%r5,%r6 sh3addo,nsv %r4,%r5,%r6 sh3addo,ev %r4,%r5,%r6
stsp/binutils-ia16	1,318	gas/testsuite/gas/hppa/basic/subi.s	.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. subi 123,%r5,%r6 subi,= 123,%r5,%r6 subi,< 123,%r5,%r6 subi,<= 123,%r5,%r6 subi,<< 123,%r5,%r6 subi,<<= 123,%r5,%r6 subi,sv 123,%r5,%r6 subi,od 123,%r5,%r6 subi,tr 123,%r5,%r6 subi,<> 123,%r5,%r6 subi,>= 123,%r5,%r6 subi,> 123,%r5,%r6 subi,>>= 123,%r5,%r6 subi,>> 123,%r5,%r6 subi,nsv 123,%r5,%r6 subi,ev 123,%r5,%r6 subio 123,%r5,%r6 subio,= 123,%r5,%r6 subio,< 123,%r5,%r6 subio,<= 123,%r5,%r6 subio,<< 123,%r5,%r6 subio,<<= 123,%r5,%r6 subio,sv 123,%r5,%r6 subio,od 123,%r5,%r6 subio,tr 123,%r5,%r6 subio,<> 123,%r5,%r6 subio,>= 123,%r5,%r6 subio,> 123,%r5,%r6 subio,>>= 123,%r5,%r6 subio,>> 123,%r5,%r6 subio,nsv 123,%r5,%r6 subio,ev 123,%r5,%r6 subi,tsv 123,%r5,%r6 subi,tsv,= 123,%r5,%r6 subi,tsv,< 123,%r5,%r6 subi,tsv,<= 123,%r5,%r6 subi,tsv,<< 123,%r5,%r6 subi,tsv,<<= 123,%r5,%r6 subi,tsv,sv 123,%r5,%r6 subi,tsv,od 123,%r5,%r6 subi,tsv,tr 123,%r5,%r6 subi,tsv,<> 123,%r5,%r6 subi,tsv,>= 123,%r5,%r6 subi,tsv,> 123,%r5,%r6 subi,tsv,>>= 123,%r5,%r6 subi,tsv,>> 123,%r5,%r6 subi,tsv,nsv 123,%r5,%r6 subi,tsv,ev 123,%r5,%r6
stsp/binutils-ia16	3,215	gas/testsuite/gas/hppa/parse/calldatabug.s	.code .align 4 LC$0000: .STRING "%d %lf %d\x0a\x00" .align 4 .EXPORT error__3AAAiidi .EXPORT error__3AAAiidi,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=FR,ARGW4=FU,RTNVAL=GR error__3AAAiidi: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) copy %r26,%r5 ldo -8(%r0),%r6 ldo -32(%r4),%r19 add %r19,%r6,%r7 stw %r25,0(%r7) ldo -12(%r0),%r8 ldo -32(%r4),%r19 add %r19,%r8,%r9 stw %r24,0(%r9) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -24(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -28(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) ldil L'LC$0000,%r26 ldo R'LC$0000(%r26),%r26 ldw 0(%r19),%r25 fldds 0(%r20),%fr7 .CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU bl printf,%r2 nop bl,n L$0002,%r0 bl,n L$0001,%r0 L$0002: L$0001: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT ok__3AAAidi .EXPORT ok__3AAAidi,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU,RTNVAL=GR ok__3AAAidi: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) copy %r26,%r5 ldo -8(%r0),%r6 ldo -32(%r4),%r19 add %r19,%r6,%r7 stw %r25,0(%r7) ldo -16(%r0),%r8 ldo -32(%r4),%r19 add %r19,%r8,%r9 fstds %fr7,0(%r9) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -16(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -20(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) ldil L'LC$0000,%r26 ldo R'LC$0000(%r26),%r26 ldw 0(%r19),%r25 fldds 0(%r20),%fr7 .CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU bl printf,%r2 nop bl,n L$0004,%r0 bl,n L$0003,%r0 L$0004: L$0003: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT __main,CODE .align 8 LC$0001: ; .double 5.50000000000000000000e+00 .word 1075183616 ; = 0x40160000 .word 0 ; = 0x0 .align 4 .EXPORT main .EXPORT main,PRIV_LEV=3,RTNVAL=GR main: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) .CALL bl __main,%r2 nop ldo -24(%r0),%r19 ldo -32(%r30),%r20 add %r20,%r19,%r19 ldil L'LC$0001,%r20 ldo R'LC$0001(%r20),%r21 ldw 0(%r21),%r22 ldw 4(%r21),%r23 stw %r22,0(%r19) stw %r23,4(%r19) ldo 3(%r0),%r19 stw %r19,-60(%r30) ldo 8(%r4),%r26 ldo 1(%r0),%r25 ldo 4(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl error__3AAAiidi,%r2 nop ldo 3(%r0),%r19 stw %r19,-52(%r30) ldo 8(%r4),%r26 ldo 1(%r0),%r25 ldil L'LC$0001,%r19 ldo R'LC$0001(%r19),%r20 fldds 0(%r20),%fr7 .CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU bl ok__3AAAidi,%r2 nop copy %r0,%r28 bl,n L$0005,%r0 bl,n L$0005,%r0 L$0005: ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND
stsp/binutils-ia16	110,003	gas/testsuite/gas/hppa/parse/fixup7bug.s	.IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE .code .align 4 .EXPORT alloc_type,CODE .EXPORT alloc_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR alloc_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r7,32(%r4) stw %r6,36(%r4) stw %r5,40(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0002,%r0 nop ldo 52(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r7 bl,n L$0003,%r0 L$0002: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 120(%r19),%r20 stw %r20,8(%r4) ldw 8(%r4),%r19 stw %r19,12(%r4) ldo 52(%r0),%r19 stw %r19,16(%r4) ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 16(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0004,%r0 nop ldw 12(%r4),%r26 ldw 16(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0005,%r0 L$0004: copy %r0,%r19 L$0005: ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 12(%r20),%r21 ldw 16(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 8(%r4),%r19 stw %r19,20(%r4) ldw 20(%r4),%r19 ldw 8(%r19),%r20 stw %r20,24(%r4) ldw 20(%r4),%r19 ldw 12(%r19),%r20 ldw 24(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0006,%r0 nop ldw 20(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0006: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 20(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0007,%r0 nop ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0008,%r0 L$0007: copy %r0,%r19 L$0008: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 24(%r4),%r7 L$0003: copy %r7,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop stw %r0,0(%r7) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,12(%r7) ldo -1(%r0),%r19 stw %r19,44(%r7) copy %r7,%r28 bl,n L$0001,%r0 L$0001: ldw 32(%r4),%r7 ldw 36(%r4),%r6 ldw 40(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT make_pointer_type,CODE .EXPORT make_pointer_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR make_pointer_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r9,16(%r4) stw %r8,20(%r4) stw %r7,24(%r4) stw %r6,28(%r4) stw %r5,32(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 20(%r19),%r9 comiclr,<> 0,%r9,%r0 bl L$0010,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0011,%r0 nop copy %r9,%r28 bl,n L$0009,%r0 bl,n L$0012,%r0 L$0011: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0013,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) copy %r9,%r28 bl,n L$0009,%r0 L$0013: L$0012: L$0010: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0015,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0014,%r0 nop bl,n L$0015,%r0 L$0015: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0016,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) L$0016: bl,n L$0017,%r0 L$0014: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r9 ldw 12(%r9),%r19 stw %r19,8(%r4) copy %r9,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldw 8(%r4),%r19 stw %r19,12(%r9) L$0017: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,16(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,20(%r19) ldo 4(%r0),%r19 stw %r19,8(%r9) ldo 1(%r0),%r19 stw %r19,0(%r9) ldh 32(%r9),%r19 copy %r19,%r20 depi -1,31,1,%r20 sth %r20,32(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 20(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0018,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,20(%r19) L$0018: copy %r9,%r28 bl,n L$0009,%r0 L$0009: ldw 16(%r4),%r9 ldw 20(%r4),%r8 ldw 24(%r4),%r7 ldw 28(%r4),%r6 ldw 32(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT lookup_pointer_type,CODE .EXPORT lookup_pointer_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_pointer_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl make_pointer_type,%r2 nop bl,n L$0019,%r0 L$0019: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT make_reference_type,CODE .EXPORT make_reference_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR make_reference_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r9,16(%r4) stw %r8,20(%r4) stw %r7,24(%r4) stw %r6,28(%r4) stw %r5,32(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 24(%r19),%r9 comiclr,<> 0,%r9,%r0 bl L$0021,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0022,%r0 nop copy %r9,%r28 bl,n L$0020,%r0 bl,n L$0023,%r0 L$0022: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0024,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) copy %r9,%r28 bl,n L$0020,%r0 L$0024: L$0023: L$0021: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0026,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0025,%r0 nop bl,n L$0026,%r0 L$0026: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0027,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) L$0027: bl,n L$0028,%r0 L$0025: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r9 ldw 12(%r9),%r19 stw %r19,8(%r4) copy %r9,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldw 8(%r4),%r19 stw %r19,12(%r9) L$0028: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,16(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,24(%r19) ldo 4(%r0),%r19 stw %r19,8(%r9) ldo 16(%r0),%r19 stw %r19,0(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 24(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0029,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,24(%r19) L$0029: copy %r9,%r28 bl,n L$0020,%r0 L$0020: ldw 16(%r4),%r9 ldw 20(%r4),%r8 ldw 24(%r4),%r7 ldw 28(%r4),%r6 ldw 32(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT lookup_reference_type,CODE .EXPORT lookup_reference_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_reference_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl make_reference_type,%r2 nop bl,n L$0030,%r0 L$0030: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT make_function_type,CODE .EXPORT make_function_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR make_function_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r9,16(%r4) stw %r8,20(%r4) stw %r7,24(%r4) stw %r6,28(%r4) stw %r5,32(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 28(%r19),%r9 comiclr,<> 0,%r9,%r0 bl L$0032,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0033,%r0 nop copy %r9,%r28 bl,n L$0031,%r0 bl,n L$0034,%r0 L$0033: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0035,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) copy %r9,%r28 bl,n L$0031,%r0 L$0035: L$0034: L$0032: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0037,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0036,%r0 nop bl,n L$0037,%r0 L$0037: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0038,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) L$0038: bl,n L$0039,%r0 L$0036: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r9 ldw 12(%r9),%r19 stw %r19,8(%r4) copy %r9,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldw 8(%r4),%r19 stw %r19,12(%r9) L$0039: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,16(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,28(%r19) ldo 1(%r0),%r19 stw %r19,8(%r9) ldo 6(%r0),%r19 stw %r19,0(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 28(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0040,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,28(%r19) L$0040: copy %r9,%r28 bl,n L$0031,%r0 L$0031: ldw 16(%r4),%r9 ldw 20(%r4),%r8 ldw 24(%r4),%r7 ldw 28(%r4),%r6 ldw 32(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT lookup_function_type,CODE .EXPORT lookup_function_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_function_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl make_function_type,%r2 nop bl,n L$0041,%r0 L$0041: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT smash_to_member_type,CODE .align 4 .EXPORT lookup_member_type,CODE .EXPORT lookup_member_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_member_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,8(%r4) stw %r7,12(%r4) stw %r6,16(%r4) stw %r5,20(%r4) ldo 24(%r4),%r1 fstds,ma %fr12,8(%r1) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,-16(%r30) fldws -16(%r30),%fr12 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 fstws %fr12,-16(%r30) ldw -16(%r30),%r26 ldw 0(%r19),%r25 ldw 0(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl smash_to_member_type,%r2 nop fstws %fr12,-16(%r30) ldw -16(%r30),%r28 bl,n L$0042,%r0 L$0042: ldw 8(%r4),%r8 ldw 12(%r4),%r7 ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 24(%r4),%r1 fldds,ma 8(%r1),%fr12 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT allocate_stub_method,CODE .EXPORT allocate_stub_method,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR allocate_stub_method: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldw 8(%r4),%r19 ldo 4(%r0),%r20 sth %r20,32(%r19) ldw 8(%r4),%r19 ldo 15(%r0),%r20 stw %r20,0(%r19) ldw 8(%r4),%r19 ldo 1(%r0),%r20 stw %r20,8(%r19) ldw 8(%r4),%r28 bl,n L$0043,%r0 L$0043: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT builtin_type_int,DATA .align 4 .EXPORT create_array_type,CODE .EXPORT create_array_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR create_array_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r10,56(%r4) stw %r9,60(%r4) stw %r8,64(%r4) stw %r7,68(%r4) stw %r6,72(%r4) stw %r5,76(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 ldo 2(%r0),%r20 stw %r20,0(%r19) ldw 8(%r4),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldw 8(%r4),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 0(%r20),%r20 ldw 8(%r21),%r21 stw %r20,-16(%r30) fldws -16(%r30),%fr5 stw %r21,-16(%r30) fldws -16(%r30),%fr5R xmpyu %fr5,%fr5R,%fr4 fstws %fr4R,-16(%r30) ldw -16(%r30),%r24 stw %r24,8(%r19) ldw 8(%r4),%r19 ldo 1(%r0),%r20 sth %r20,34(%r19) ldw 8(%r4),%r9 ldw 8(%r4),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0050,%r0 nop ldw 8(%r4),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,16(%r4) ldw 16(%r4),%r19 stw %r19,20(%r4) ldo 16(%r0),%r19 stw %r19,24(%r4) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 24(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0045,%r0 nop ldw 20(%r4),%r26 ldw 24(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0046,%r0 L$0045: copy %r0,%r19 L$0046: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 ldw 24(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 16(%r4),%r19 stw %r19,28(%r4) ldw 28(%r4),%r19 ldw 8(%r19),%r20 stw %r20,32(%r4) ldw 28(%r4),%r19 ldw 12(%r19),%r20 ldw 32(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0047,%r0 nop ldw 28(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0047: ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 28(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 28(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 28(%r4),%r20 ldw 28(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0048,%r0 nop ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0049,%r0 L$0048: copy %r0,%r19 L$0049: ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 32(%r4),%r10 bl,n L$0051,%r0 L$0050: ldo 16(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r10 L$0051: stw %r10,36(%r9) ldw 8(%r4),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,12(%r4) ldw 12(%r4),%r19 ldo 11(%r0),%r20 stw %r20,0(%r19) ldw 12(%r4),%r19 addil L'builtin_type_int-$global$,%r27 ldw R'builtin_type_int-$global$(%r1),%r20 stw %r20,16(%r19) ldw 12(%r4),%r19 ldo 4(%r0),%r20 stw %r20,8(%r19) ldw 12(%r4),%r19 ldo 2(%r0),%r20 sth %r20,34(%r19) ldw 12(%r4),%r9 ldw 12(%r4),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0057,%r0 nop ldw 12(%r4),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,36(%r4) ldw 36(%r4),%r19 stw %r19,40(%r4) ldo 32(%r0),%r19 stw %r19,44(%r4) ldw 40(%r4),%r19 ldw 40(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 44(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0052,%r0 nop ldw 40(%r4),%r26 ldw 44(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0053,%r0 L$0052: copy %r0,%r19 L$0053: ldw 40(%r4),%r19 ldw 40(%r4),%r20 ldw 12(%r20),%r21 ldw 44(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 36(%r4),%r19 stw %r19,48(%r4) ldw 48(%r4),%r19 ldw 8(%r19),%r20 stw %r20,52(%r4) ldw 48(%r4),%r19 ldw 12(%r19),%r20 ldw 52(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0054,%r0 nop ldw 48(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0054: ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 48(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 48(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 48(%r4),%r20 ldw 48(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0055,%r0 nop ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0056,%r0 L$0055: copy %r0,%r19 L$0056: ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 52(%r4),%r10 bl,n L$0058,%r0 L$0057: ldo 32(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r10 L$0058: stw %r10,36(%r9) ldw 12(%r4),%r19 ldw 36(%r19),%r20 stw %r0,0(%r20) ldw 12(%r4),%r19 ldo 16(%r0),%r20 ldw 36(%r19),%r21 add %r20,%r21,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldo -1(%r20),%r21 stw %r21,0(%r19) ldw 12(%r4),%r20 ldw 36(%r20),%r19 addil L'builtin_type_int-$global$,%r27 ldw R'builtin_type_int-$global$(%r1),%r20 stw %r20,8(%r19) ldw 12(%r4),%r19 ldo 16(%r0),%r20 ldw 36(%r19),%r21 add %r20,%r21,%r19 addil L'builtin_type_int-$global$,%r27 ldw R'builtin_type_int-$global$(%r1),%r20 stw %r20,8(%r19) ldw 8(%r4),%r19 ldw 36(%r19),%r20 ldw 12(%r4),%r19 stw %r19,8(%r20) ldw 8(%r4),%r19 ldo -1(%r0),%r20 stw %r20,44(%r19) ldw 8(%r4),%r28 bl,n L$0044,%r0 L$0044: ldw 56(%r4),%r10 ldw 60(%r4),%r9 ldw 64(%r4),%r8 ldw 68(%r4),%r7 ldw 72(%r4),%r6 ldw 76(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT smash_to_member_type,CODE .EXPORT smash_to_member_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR smash_to_member_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r10,16(%r4) stw %r9,20(%r4) stw %r8,24(%r4) stw %r7,28(%r4) stw %r6,32(%r4) stw %r5,36(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 stw %r20,8(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 stw %r20,12(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -12(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,40(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 1(%r0),%r20 stw %r20,8(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 14(%r0),%r20 stw %r20,0(%r19) L$0059: ldw 16(%r4),%r10 ldw 20(%r4),%r9 ldw 24(%r4),%r8 ldw 28(%r4),%r7 ldw 32(%r4),%r6 ldw 36(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT smash_to_method_type,CODE .EXPORT smash_to_method_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR smash_to_method_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r12,16(%r4) stw %r11,20(%r4) stw %r10,24(%r4) stw %r9,28(%r4) stw %r8,32(%r4) stw %r7,36(%r4) stw %r6,40(%r4) stw %r5,44(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -16(%r0),%r11 ldo -32(%r4),%r19 add %r19,%r11,%r12 stw %r23,0(%r12) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 stw %r20,8(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 stw %r20,12(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -12(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,40(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -16(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,48(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 1(%r0),%r20 stw %r20,8(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 15(%r0),%r20 stw %r20,0(%r19) L$0060: ldw 16(%r4),%r12 ldw 20(%r4),%r11 ldw 24(%r4),%r10 ldw 28(%r4),%r9 ldw 32(%r4),%r8 ldw 36(%r4),%r7 ldw 40(%r4),%r6 ldw 44(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT strncmp,CODE .align 4 LC$0000: .STRING "struct \x00" .align 4 LC$0001: .STRING "union \x00" .align 4 LC$0002: .STRING "enum \x00" .align 4 .EXPORT type_name_no_tag,CODE .EXPORT type_name_no_tag,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR type_name_no_tag: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) copy %r26,%r5 ldw 4(%r5),%r6 comiclr,<> 0,%r6,%r0 bl L$0062,%r0 nop ldw 0(%r5),%r19 comiclr,<> 4,%r19,%r0 bl L$0066,%r0 nop comiclr,>= 4,%r19,%r0 bl L$0072,%r0 nop comiclr,<> 3,%r19,%r0 bl L$0064,%r0 nop bl,n L$0070,%r0 L$0072: comiclr,<> 5,%r19,%r0 bl L$0068,%r0 nop bl,n L$0070,%r0 L$0064: copy %r6,%r26 ldil L'LC$0000,%r25 ldo R'LC$0000(%r25),%r25 ldo 7(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl strncmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0065,%r0 nop ldo 7(%r6),%r6 L$0065: bl,n L$0063,%r0 L$0066: copy %r6,%r26 ldil L'LC$0001,%r25 ldo R'LC$0001(%r25),%r25 ldo 6(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl strncmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0067,%r0 nop ldo 6(%r6),%r6 L$0067: bl,n L$0063,%r0 L$0068: copy %r6,%r26 ldil L'LC$0002,%r25 ldo R'LC$0002(%r25),%r25 ldo 5(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl strncmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0069,%r0 nop ldo 5(%r6),%r6 L$0069: bl,n L$0063,%r0 L$0070: bl,n L$0063,%r0 L$0063: L$0062: copy %r6,%r28 bl,n L$0061,%r0 L$0061: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT current_language,DATA .IMPORT strcmp,CODE .align 4 .EXPORT lookup_primitive_typename,CODE .EXPORT lookup_primitive_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_primitive_typename: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) addil L'current_language-$global$,%r27 ldw R'current_language-$global$(%r1),%r19 ldw 8(%r19),%r20 stw %r20,8(%r4) L$0074: ldw 8(%r4),%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0075,%r0 nop ldw 8(%r4),%r19 ldw 0(%r19),%r20 ldw 0(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 4(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0077,%r0 nop ldw 8(%r4),%r19 ldw 0(%r19),%r20 ldw 0(%r20),%r28 bl,n L$0073,%r0 L$0077: L$0076: ldw 8(%r4),%r19 ldo 4(%r19),%r20 stw %r20,8(%r4) bl,n L$0074,%r0 L$0075: copy %r0,%r28 bl,n L$0073,%r0 L$0073: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT lookup_symbol,CODE .IMPORT error,CODE .align 4 LC$0003: .STRING "No type named %s.\x00" .align 4 .EXPORT lookup_typename,CODE .EXPORT lookup_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR lookup_typename: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r12,8(%r4) stw %r11,12(%r4) stw %r10,16(%r4) stw %r9,20(%r4) stw %r8,24(%r4) stw %r7,28(%r4) stw %r6,32(%r4) stw %r5,36(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 1(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r11 comiclr,<> 0,%r11,%r0 bl L$0080,%r0 nop ldw 8(%r11),%r19 comiclr,= 8,%r19,%r0 bl L$0080,%r0 nop bl,n L$0079,%r0 L$0080: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl lookup_primitive_typename,%r2 nop copy %r28,%r12 comiclr,<> 0,%r12,%r0 bl L$0081,%r0 nop copy %r12,%r28 bl,n L$0078,%r0 bl,n L$0082,%r0 L$0081: comiclr,= 0,%r12,%r0 bl L$0083,%r0 nop ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0083,%r0 nop copy %r0,%r28 bl,n L$0078,%r0 bl,n L$0084,%r0 L$0083: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0003,%r26 ldo R'LC$0003(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0084: L$0082: L$0079: ldw 12(%r11),%r28 bl,n L$0078,%r0 L$0078: ldw 8(%r4),%r12 ldw 12(%r4),%r11 ldw 16(%r4),%r10 ldw 20(%r4),%r9 ldw 24(%r4),%r8 ldw 28(%r4),%r7 ldw 32(%r4),%r6 ldw 36(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT alloca,CODE .IMPORT strlen,CODE .IMPORT strcpy,CODE .align 4 LC$0004: .STRING "unsigned \x00" .align 4 .EXPORT lookup_unsigned_typename,CODE .EXPORT lookup_unsigned_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_unsigned_typename: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 ldo 10(%r19),%r20 ldo 7(%r20),%r21 copy %r21,%r19 ldo 63(%r19),%r20 extru %r20,25,26,%r19 zdep %r19,25,26,%r20 ldo -96(%r30),%r19 add %r30,%r20,%r30 ldo 7(%r19),%r20 extru %r20,28,29,%r19 zdep %r19,28,29,%r20 stw %r20,8(%r4) ldw 8(%r4),%r26 ldil L'LC$0004,%r25 ldo R'LC$0004(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 8(%r4),%r20 ldo 9(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 copy %r19,%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 8(%r4),%r26 copy %r0,%r25 copy %r0,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_typename,%r2 nop bl,n L$0085,%r0 L$0085: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0005: .STRING "signed \x00" .align 4 .EXPORT lookup_signed_typename,CODE .EXPORT lookup_signed_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_signed_typename: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 ldo 8(%r19),%r20 ldo 7(%r20),%r21 copy %r21,%r19 ldo 63(%r19),%r20 extru %r20,25,26,%r19 zdep %r19,25,26,%r20 ldo -96(%r30),%r19 add %r30,%r20,%r30 ldo 7(%r19),%r20 extru %r20,28,29,%r19 zdep %r19,28,29,%r20 stw %r20,12(%r4) ldw 12(%r4),%r26 ldil L'LC$0005,%r25 ldo R'LC$0005(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 12(%r4),%r20 ldo 7(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 copy %r19,%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 12(%r4),%r26 copy %r0,%r25 ldo 1(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_typename,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0087,%r0 nop ldw 8(%r4),%r28 bl,n L$0086,%r0 L$0087: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 copy %r0,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_typename,%r2 nop bl,n L$0086,%r0 L$0086: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0006: .STRING "No struct type named %s.\x00" .align 4 LC$0007: .STRING "This context has class, union or enum %s, not a struct.\x00" .align 4 .EXPORT lookup_struct,CODE .EXPORT lookup_struct,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_struct: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r9 comiclr,= 0,%r9,%r0 bl L$0089,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0006,%r26 ldo R'LC$0006(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0089: ldw 12(%r9),%r19 ldw 0(%r19),%r20 comiclr,<> 3,%r20,%r0 bl L$0090,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0007,%r26 ldo R'LC$0007(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0090: ldw 12(%r9),%r28 bl,n L$0088,%r0 L$0088: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0008: .STRING "No union type named %s.\x00" .align 4 LC$0009: .STRING "This context has class, struct or enum %s, not a union.\x00" .align 4 .EXPORT lookup_union,CODE .EXPORT lookup_union,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_union: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r9 comiclr,= 0,%r9,%r0 bl L$0092,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0008,%r26 ldo R'LC$0008(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0092: ldw 12(%r9),%r19 ldw 0(%r19),%r20 comiclr,<> 4,%r20,%r0 bl L$0093,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0009,%r26 ldo R'LC$0009(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0093: ldw 12(%r9),%r28 bl,n L$0091,%r0 L$0091: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0010: .STRING "No enum type named %s.\x00" .align 4 LC$0011: .STRING "This context has class, struct or union %s, not an enum.\x00" .align 4 .EXPORT lookup_enum,CODE .EXPORT lookup_enum,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_enum: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r9 comiclr,= 0,%r9,%r0 bl L$0095,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0010,%r26 ldo R'LC$0010(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0095: ldw 12(%r9),%r19 ldw 0(%r19),%r20 comiclr,<> 5,%r20,%r0 bl L$0096,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0011,%r26 ldo R'LC$0011(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0096: ldw 12(%r9),%r28 bl,n L$0094,%r0 L$0094: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT strcat,CODE .align 4 LC$0012: .STRING "<\x00" .align 4 LC$0013: .STRING " >\x00" .align 4 LC$0014: .STRING "No template type named %s.\x00" .align 4 .EXPORT lookup_template_type,CODE .EXPORT lookup_template_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR lookup_template_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r11,16(%r4) stw %r10,20(%r4) stw %r9,24(%r4) stw %r8,28(%r4) stw %r7,32(%r4) stw %r6,36(%r4) stw %r5,40(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r11 ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 4(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 add %r11,%r19,%r20 ldo 4(%r20),%r19 ldo 7(%r19),%r20 copy %r20,%r19 ldo 63(%r19),%r20 extru %r20,25,26,%r19 zdep %r19,25,26,%r20 ldo -96(%r30),%r19 add %r30,%r20,%r30 ldo 7(%r19),%r20 extru %r20,28,29,%r19 zdep %r19,28,29,%r20 stw %r20,12(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 12(%r4),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 12(%r4),%r26 ldil L'LC$0012,%r25 ldo R'LC$0012(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcat,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r4),%r26 ldw 4(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcat,%r2 nop ldw 12(%r4),%r26 ldil L'LC$0013,%r25 ldo R'LC$0013(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcat,%r2 nop ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 stw %r0,-52(%r30) ldw 12(%r4),%r26 ldw 0(%r19),%r25 ldo 1(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0098,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0014,%r26 ldo R'LC$0014(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0098: ldw 8(%r4),%r19 ldw 12(%r19),%r20 ldw 0(%r20),%r19 comiclr,<> 3,%r19,%r0 bl L$0099,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0007,%r26 ldo R'LC$0007(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0099: ldw 8(%r4),%r19 ldw 12(%r19),%r28 bl,n L$0097,%r0 L$0097: ldw 16(%r4),%r11 ldw 20(%r4),%r10 ldw 24(%r4),%r9 ldw 28(%r4),%r8 ldw 32(%r4),%r7 ldw 36(%r4),%r6 ldw 40(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT current_target,DATA .IMPORT fflush,CODE .IMPORT __iob,DATA .IMPORT fprintf,CODE .align 4 LC$0015: .STRING "Type \x00" .IMPORT type_print,CODE .align 4 LC$0016: .STRING "\x00" .align 4 LC$0017: .STRING " is not a structure or union type.\x00" .IMPORT check_stub_type,CODE .align 4 LC$0018: .STRING " has no component named \x00" .IMPORT fputs_filtered,CODE .align 4 LC$0019: .STRING ".\x00" .align 4 .EXPORT lookup_struct_elt_type,CODE .EXPORT lookup_struct_elt_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR lookup_struct_elt_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r11,24(%r4) stw %r10,28(%r4) stw %r9,32(%r4) stw %r8,36(%r4) stw %r7,40(%r4) stw %r6,44(%r4) stw %r5,48(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 1,%r20,%r0 bl L$0102,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 ldo 16(%r0),%r19 comclr,<> %r20,%r19,%r0 bl L$0102,%r0 nop bl,n L$0101,%r0 L$0102: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 16(%r20),%r21 stw %r21,0(%r19) L$0101: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 3,%r20,%r0 bl L$0103,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 4,%r20,%r0 bl L$0103,%r0 nop addil L'current_target-$global$,%r27 ldw R'current_target-$global$(%r1),%r19 ldw 76(%r19),%r11 copy %r11,%r22 .CALL ARGW0=GR bl $$dyncall,%r31 copy %r31,%r2 addil L'__iob-$global$+16,%r27 ldo R'__iob-$global$+16(%r1),%r26 .CALL ARGW0=GR bl fflush,%r2 nop addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r26 ldil L'LC$0015,%r25 ldo R'LC$0015(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl fprintf,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 ldil L'LC$0016,%r25 ldo R'LC$0016(%r25),%r25 addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r24 ldo -1(%r0),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl type_print,%r2 nop ldil L'LC$0017,%r26 ldo R'LC$0017(%r26),%r26 .CALL ARGW0=GR bl error,%r2 nop L$0103: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl check_stub_type,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 34(%r19),%r20 extrs %r20,31,16,%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) L$0104: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 ldw 8(%r4),%r20 comclr,>= %r20,%r19,%r0 bl L$0105,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 12(%r19),%r20 stw %r20,12(%r4) ldw 12(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0107,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 12(%r4),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0107,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r28 bl,n L$0100,%r0 L$0107: L$0106: ldw 8(%r4),%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) bl,n L$0104,%r0 L$0105: nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) L$0108: ldw 8(%r4),%r19 comiclr,<= 0,%r19,%r0 bl L$0109,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 8(%r19),%r26 ldw 0(%r20),%r25 copy %r0,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_struct_elt_type,%r2 nop stw %r28,16(%r4) ldw 16(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0111,%r0 nop ldw 16(%r4),%r28 bl,n L$0100,%r0 L$0111: L$0110: ldw 8(%r4),%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) bl,n L$0108,%r0 L$0109: ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0112,%r0 nop copy %r0,%r28 bl,n L$0100,%r0 L$0112: addil L'current_target-$global$,%r27 ldw R'current_target-$global$(%r1),%r19 ldw 76(%r19),%r11 copy %r11,%r22 .CALL ARGW0=GR bl $$dyncall,%r31 copy %r31,%r2 addil L'__iob-$global$+16,%r27 ldo R'__iob-$global$+16(%r1),%r26 .CALL ARGW0=GR bl fflush,%r2 nop addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r26 ldil L'LC$0015,%r25 ldo R'LC$0015(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl fprintf,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 ldil L'LC$0016,%r25 ldo R'LC$0016(%r25),%r25 addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r24 ldo -1(%r0),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl type_print,%r2 nop addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r26 ldil L'LC$0018,%r25 ldo R'LC$0018(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl fprintf,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r25 .CALL ARGW0=GR,ARGW1=GR bl fputs_filtered,%r2 nop ldil L'LC$0019,%r26 ldo R'LC$0019(%r26),%r26 .CALL ARGW0=GR bl error,%r2 nop ldo -1(%r0),%r28 bl,n L$0100,%r0 L$0100: ldw 24(%r4),%r11 ldw 28(%r4),%r10 ldw 32(%r4),%r9 ldw 36(%r4),%r8 ldw 40(%r4),%r7 ldw 44(%r4),%r6 ldw 48(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT fill_in_vptr_fieldno,CODE .EXPORT fill_in_vptr_fieldno,ENTRY,PRIV_LEV=3,ARGW0=GR fill_in_vptr_fieldno: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 44(%r19),%r20 comiclr,> 0,%r20,%r0 bl L$0114,%r0 nop ldo 1(%r0),%r19 stw %r19,8(%r4) L$0115: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 ldw 8(%r4),%r20 comclr,< %r20,%r19,%r0 bl L$0116,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r26 .CALL ARGW0=GR bl fill_in_vptr_fieldno,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r20 ldw 44(%r20),%r19 comiclr,<= 0,%r19,%r0 bl L$0118,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 8(%r4),%r21 zdep %r21,27,28,%r22 ldw 36(%r20),%r21 add %r22,%r21,%r20 ldw 8(%r20),%r21 ldw 44(%r21),%r20 stw %r20,44(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 8(%r4),%r21 zdep %r21,27,28,%r22 ldw 36(%r20),%r21 add %r22,%r21,%r20 ldw 8(%r20),%r21 ldw 40(%r21),%r20 stw %r20,40(%r19) bl,n L$0116,%r0 L$0118: L$0117: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0115,%r0 L$0116: L$0114: L$0113: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .EXPORT stub_noname_complaint,DATA .align 4 LC$0020: .STRING "stub type has NULL name\x00" .data .align 4 stub_noname_complaint: .word LC$0020 .word 0 .word 0 .IMPORT complain,CODE .IMPORT memcpy,CODE .code .align 4 .EXPORT check_stub_type,CODE .EXPORT check_stub_type,ENTRY,PRIV_LEV=3,ARGW0=GR check_stub_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 ldo 4(%r0),%r21 and %r20,%r21,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0120,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl type_name_no_tag,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0121,%r0 nop addil L'stub_noname_complaint-$global$,%r27 ldo R'stub_noname_complaint-$global$(%r1),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl complain,%r2 nop bl,n L$0119,%r0 L$0121: stw %r0,-52(%r30) ldw 8(%r4),%r26 copy %r0,%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop stw %r28,12(%r4) ldw 12(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0122,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 12(%r4),%r20 ldw 0(%r19),%r26 ldw 12(%r20),%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memcpy,%r2 nop L$0122: L$0120: L$0119: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT gdb_mangle_name,CODE .IMPORT cplus_demangle,CODE .align 4 LC$0021: .STRING "Internal: Cannot demangle mangled name `%s'.\x00" .IMPORT strchr,CODE .IMPORT parse_and_eval_type,CODE .IMPORT builtin_type_void,DATA .IMPORT free,CODE .align 4 .EXPORT check_stub_method,CODE .EXPORT check_stub_method,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR check_stub_method: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r11,64(%r4) stw %r10,68(%r4) stw %r9,72(%r4) stw %r8,76(%r4) stw %r7,80(%r4) stw %r6,84(%r4) stw %r5,88(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -12(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldw 0(%r21),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl gdb_mangle_name,%r2 nop stw %r28,12(%r4) ldw 12(%r4),%r26 ldo 3(%r0),%r25 .CALL ARGW0=GR,ARGW1=GR bl cplus_demangle,%r2 nop stw %r28,16(%r4) stw %r0,28(%r4) ldo 1(%r0),%r19 stw %r19,32(%r4) ldw 16(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0124,%r0 nop ldil L'LC$0021,%r26 ldo R'LC$0021(%r26),%r26 ldw 12(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0124: ldw 16(%r4),%r26 ldo 40(%r0),%r25 .CALL ARGW0=GR,ARGW1=GR bl strchr,%r2 nop copy %r28,%r19 ldo 1(%r19),%r20 stw %r20,20(%r4) ldw 20(%r4),%r19 stw %r19,24(%r4) L$0125: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 comiclr,<> 0,%r19,%r0 bl L$0126,%r0 nop ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 40(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0127,%r0 nop ldw 28(%r4),%r19 ldo 1(%r19),%r20 stw %r20,28(%r4) bl,n L$0128,%r0 L$0127: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0129,%r0 nop ldw 28(%r4),%r19 ldo -1(%r19),%r20 stw %r20,28(%r4) bl,n L$0130,%r0 L$0129: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 44(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0131,%r0 nop ldw 28(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0131,%r0 nop ldw 32(%r4),%r19 ldo 1(%r19),%r20 stw %r20,32(%r4) L$0131: L$0130: L$0128: ldw 24(%r4),%r19 ldo 1(%r19),%r20 stw %r20,24(%r4) bl,n L$0125,%r0 L$0126: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0137,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,44(%r4) ldw 44(%r4),%r19 stw %r19,48(%r4) ldw 32(%r4),%r20 ldo 2(%r20),%r19 zdep %r19,29,30,%r20 stw %r20,52(%r4) ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 52(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0132,%r0 nop ldw 48(%r4),%r26 ldw 52(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0133,%r0 L$0132: copy %r0,%r19 L$0133: ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 12(%r20),%r21 ldw 52(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 44(%r4),%r19 stw %r19,56(%r4) ldw 56(%r4),%r19 ldw 8(%r19),%r20 stw %r20,60(%r4) ldw 56(%r4),%r19 ldw 12(%r19),%r20 ldw 60(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0134,%r0 nop ldw 56(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0134: ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 56(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 56(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 56(%r4),%r20 ldw 56(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0135,%r0 nop ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0136,%r0 L$0135: copy %r0,%r19 L$0136: ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 60(%r4),%r11 bl,n L$0138,%r0 L$0137: ldw 32(%r4),%r20 ldo 2(%r20),%r19 zdep %r19,29,30,%r20 copy %r20,%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r11 L$0138: stw %r11,36(%r4) ldw 20(%r4),%r19 stw %r19,24(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl lookup_pointer_type,%r2 nop copy %r28,%r19 ldw 36(%r4),%r20 stw %r19,0(%r20) ldo 1(%r0),%r19 stw %r19,32(%r4) ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0139,%r0 nop stw %r0,28(%r4) L$0140: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 comiclr,<> 0,%r19,%r0 bl L$0141,%r0 nop ldw 28(%r4),%r19 comiclr,>= 0,%r19,%r0 bl L$0142,%r0 nop ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 44(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0143,%r0 nop ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0143,%r0 nop bl,n L$0142,%r0 L$0143: ldw 24(%r4),%r19 ldw 20(%r4),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r26 copy %r19,%r25 .CALL ARGW0=GR,ARGW1=GR bl parse_and_eval_type,%r2 nop copy %r28,%r19 ldw 32(%r4),%r20 zdep %r20,29,30,%r21 ldw 36(%r4),%r22 add %r21,%r22,%r20 stw %r19,0(%r20) ldw 32(%r4),%r19 ldo 1(%r19),%r20 stw %r20,32(%r4) ldw 24(%r4),%r19 ldo 1(%r19),%r20 stw %r20,20(%r4) L$0142: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 40(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0144,%r0 nop ldw 28(%r4),%r19 ldo 1(%r19),%r20 stw %r20,28(%r4) bl,n L$0145,%r0 L$0144: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0146,%r0 nop ldw 28(%r4),%r19 ldo -1(%r19),%r20 stw %r20,28(%r4) L$0146: L$0145: ldw 24(%r4),%r19 ldo 1(%r19),%r20 stw %r20,24(%r4) bl,n L$0140,%r0 L$0141: L$0139: ldo -2(%r0),%r19 ldw 24(%r4),%r20 add %r19,%r20,%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 46(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0147,%r0 nop ldw 32(%r4),%r19 zdep %r19,29,30,%r20 ldw 36(%r4),%r21 add %r20,%r21,%r19 addil L'builtin_type_void-$global$,%r27 ldw R'builtin_type_void-$global$(%r1),%r20 stw %r20,0(%r19) bl,n L$0148,%r0 L$0147: ldw 32(%r4),%r19 zdep %r19,29,30,%r20 ldw 36(%r4),%r21 add %r20,%r21,%r19 stw %r0,0(%r19) L$0148: ldw 16(%r4),%r26 .CALL ARGW0=GR bl free,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 zdep %r21,30,31,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 20(%r19),%r21 add %r20,%r21,%r19 ldw 8(%r19),%r20 stw %r20,8(%r4) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 8(%r4),%r20 add %r19,%r20,%r19 ldw 12(%r4),%r20 stw %r20,0(%r19) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 8(%r4),%r20 add %r19,%r20,%r19 ldw 4(%r19),%r20 stw %r20,40(%r4) ldw 40(%r4),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,40(%r19) ldw 40(%r4),%r19 ldw 36(%r4),%r20 stw %r20,48(%r19) ldw 40(%r4),%r19 ldw 40(%r4),%r20 ldh 32(%r20),%r21 copy %r21,%r20 depi 0,29,1,%r20 sth %r20,32(%r19) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 8(%r4),%r20 add %r19,%r20,%r19 ldw 16(%r19),%r20 copy %r20,%r21 depi 0,4,1,%r21 stw %r21,16(%r19) L$0123: ldw 64(%r4),%r11 ldw 68(%r4),%r10 ldw 72(%r4),%r9 ldw 76(%r4),%r8 ldw 80(%r4),%r7 ldw 84(%r4),%r6 ldw 88(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT allocate_cplus_struct_type,CODE .EXPORT allocate_cplus_struct_type,ENTRY,PRIV_LEV=3,ARGW0=GR allocate_cplus_struct_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r8,32(%r4) stw %r7,36(%r4) stw %r6,40(%r4) stw %r5,44(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 comclr,= %r19,%r20,%r0 bl L$0150,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r7 ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0156,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,8(%r4) ldw 8(%r4),%r19 stw %r19,12(%r4) ldo 24(%r0),%r19 stw %r19,16(%r4) ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 16(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0151,%r0 nop ldw 12(%r4),%r26 ldw 16(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0152,%r0 L$0151: copy %r0,%r19 L$0152: ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 12(%r20),%r21 ldw 16(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 8(%r4),%r19 stw %r19,20(%r4) ldw 20(%r4),%r19 ldw 8(%r19),%r20 stw %r20,24(%r4) ldw 20(%r4),%r19 ldw 12(%r19),%r20 ldw 24(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0153,%r0 nop ldw 20(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0153: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 20(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0154,%r0 nop ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0155,%r0 L$0154: copy %r0,%r19 L$0155: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 24(%r4),%r8 bl,n L$0157,%r0 L$0156: ldo 24(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r8 L$0157: stw %r8,48(%r7) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 copy %r20,%r21 ldws,ma 4(%r22),%r19 ldws,ma 4(%r22),%r20 stws,ma %r19,4(%r21) ldws,ma 4(%r22),%r19 stws,ma %r20,4(%r21) ldws,ma 4(%r22),%r20 stws,ma %r19,4(%r21) ldws,ma 4(%r22),%r19 stws,ma %r20,4(%r21) ldws,ma 4(%r22),%r20 stws,ma %r19,4(%r21) stw %r20,0(%r21) L$0150: L$0149: ldw 32(%r4),%r8 ldw 36(%r4),%r7 ldw 40(%r4),%r6 ldw 44(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT obsavestring,CODE .align 4 .EXPORT init_type,CODE .EXPORT init_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR,RTNVAL=GR init_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r14,8(%r4) stw %r13,12(%r4) stw %r12,16(%r4) stw %r11,20(%r4) stw %r10,24(%r4) stw %r9,28(%r4) stw %r8,32(%r4) stw %r7,36(%r4) stw %r6,40(%r4) stw %r5,44(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -16(%r0),%r11 ldo -32(%r4),%r19 add %r19,%r11,%r12 stw %r23,0(%r12) ldo -20(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r13 ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,0(%r13) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,8(%r13) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldh 32(%r13),%r20 ldh 2(%r19),%r19 or %r20,%r19,%r20 sth %r20,32(%r13) ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0159,%r0 nop ldo -20(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0159,%r0 nop ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r14 ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 ldo -20(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 120(%r21),%r20 ldw 0(%r14),%r26 copy %r19,%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl obsavestring,%r2 nop copy %r28,%r19 stw %r19,4(%r13) bl,n L$0160,%r0 L$0159: ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,4(%r13) L$0160: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 3,%r20,%r0 bl L$0162,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 4,%r20,%r0 bl L$0162,%r0 nop bl,n L$0161,%r0 L$0162: stw %r19,48(%r13) L$0161: copy %r13,%r28 bl,n L$0158,%r0 L$0158: ldw 8(%r4),%r14 ldw 12(%r4),%r13 ldw 16(%r4),%r12 ldw 20(%r4),%r11 ldw 24(%r4),%r10 ldw 28(%r4),%r9 ldw 32(%r4),%r8 ldw 36(%r4),%r7 ldw 40(%r4),%r6 ldw 44(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0022: .STRING "internal error - invalid fundamental type id %d\x00" .align 4 LC$0023: .STRING "internal error: unhandled type id %d\x00" .align 4 LC$0024: .STRING "void\x00" .align 4 LC$0025: .STRING "boolean\x00" .align 4 LC$0026: .STRING "string\x00" .align 4 LC$0027: .STRING "char\x00" .align 4 LC$0028: .STRING "signed char\x00" .align 4 LC$0029: .STRING "unsigned char\x00" .align 4 LC$0030: .STRING "short\x00" .align 4 LC$0031: .STRING "unsigned short\x00" .align 4 LC$0032: .STRING "int\x00" .align 4 LC$0033: .STRING "unsigned int\x00" .align 4 LC$0034: .STRING "fixed decimal\x00" .align 4 LC$0035: .STRING "long\x00" .align 4 LC$0036: .STRING "unsigned long\x00" .align 4 LC$0037: .STRING "long long\x00" .align 4 LC$0038: .STRING "signed long long\x00" .align 4 LC$0039: .STRING "unsigned long long\x00" .align 4 LC$0040: .STRING "float\x00" .align 4 LC$0041: .STRING "double\x00" .align 4 LC$0042: .STRING "floating decimal\x00" .align 4 LC$0043: .STRING "long double\x00" .align 4 LC$0044: .STRING "complex\x00" .align 4 LC$0045: .STRING "double complex\x00" .align 4 LC$0046: .STRING "long double complex\x00" .align 4 .EXPORT lookup_fundamental_type,CODE .EXPORT lookup_fundamental_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_fundamental_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r12,32(%r4) stw %r11,36(%r4) stw %r10,40(%r4) stw %r9,44(%r4) stw %r8,48(%r4) stw %r7,52(%r4) stw %r6,56(%r4) stw %r5,60(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) copy %r0,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<= 0,%r20,%r0 bl L$0165,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 25(%r0),%r19 comclr,<= %r20,%r19,%r0 bl L$0165,%r0 nop bl,n L$0164,%r0 L$0165: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0022,%r26 ldo R'LC$0022(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop bl,n L$0166,%r0 L$0164: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 196(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0167,%r0 nop ldo 104(%r0),%r11 ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r12 ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 120(%r19),%r20 stw %r20,8(%r4) ldw 8(%r4),%r19 stw %r19,12(%r4) stw %r11,16(%r4) ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 16(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0168,%r0 nop ldw 12(%r4),%r26 ldw 16(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0169,%r0 L$0168: copy %r0,%r19 L$0169: ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 12(%r20),%r21 ldw 16(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 8(%r4),%r19 stw %r19,20(%r4) ldw 20(%r4),%r19 ldw 8(%r19),%r20 stw %r20,24(%r4) ldw 20(%r4),%r19 ldw 12(%r19),%r20 ldw 24(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0170,%r0 nop ldw 20(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0170: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 20(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0171,%r0 nop ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0172,%r0 L$0171: copy %r0,%r19 L$0172: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 24(%r4),%r19 stw %r19,196(%r12) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 196(%r19),%r26 copy %r0,%r25 copy %r11,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop L$0167: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 zdep %r21,29,30,%r20 ldw 196(%r19),%r19 add %r20,%r19,%r10 ldw 0(%r10),%r9 comiclr,= 0,%r9,%r0 bl L$0173,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 addi,uv -26,%r20,%r0 blr,n %r20,%r0 b,n L$0175 L$0202: b L$0176 nop b L$0177 nop b L$0179 nop b L$0180 nop b L$0181 nop b L$0182 nop b L$0183 nop b L$0184 nop b L$0185 nop b L$0186 nop b L$0187 nop b L$0189 nop b L$0190 nop b L$0191 nop b L$0192 nop b L$0193 nop b L$0194 nop b L$0195 nop b L$0196 nop b L$0198 nop b L$0199 nop b L$0200 nop b L$0201 nop b L$0178 nop b L$0188 nop b L$0197 nop L$0175: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0023,%r26 ldo R'LC$0023(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop bl,n L$0174,%r0 L$0176: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 9(%r0),%r26 ldo 1(%r0),%r25 copy %r0,%r24 ldil L'LC$0024,%r23 ldo R'LC$0024(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0177: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0025,%r23 ldo R'LC$0025(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0178: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 12(%r0),%r26 ldo 1(%r0),%r25 copy %r0,%r24 ldil L'LC$0026,%r23 ldo R'LC$0026(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0179: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 1(%r0),%r25 copy %r0,%r24 ldil L'LC$0027,%r23 ldo R'LC$0027(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0180: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 1(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0028,%r23 ldo R'LC$0028(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0181: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 1(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0029,%r23 ldo R'LC$0029(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0182: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 2(%r0),%r25 copy %r0,%r24 ldil L'LC$0030,%r23 ldo R'LC$0030(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0183: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 2(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0030,%r23 ldo R'LC$0030(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0184: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 2(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0031,%r23 ldo R'LC$0031(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0185: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0032,%r23 ldo R'LC$0032(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0186: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0032,%r23 ldo R'LC$0032(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0187: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0033,%r23 ldo R'LC$0033(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0188: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0034,%r23 ldo R'LC$0034(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0189: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0035,%r23 ldo R'LC$0035(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0190: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0035,%r23 ldo R'LC$0035(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0191: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0036,%r23 ldo R'LC$0036(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0192: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0037,%r23 ldo R'LC$0037(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0193: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 8(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0038,%r23 ldo R'LC$0038(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0194: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 8(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0039,%r23 ldo R'LC$0039(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0195: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0040,%r23 ldo R'LC$0040(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0196: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0041,%r23 ldo R'LC$0041(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0197: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0042,%r23 ldo R'LC$0042(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0198: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 16(%r0),%r25 copy %r0,%r24 ldil L'LC$0043,%r23 ldo R'LC$0043(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0199: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0044,%r23 ldo R'LC$0044(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0200: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 16(%r0),%r25 copy %r0,%r24 ldil L'LC$0045,%r23 ldo R'LC$0045(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0201: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 16(%r0),%r25 copy %r0,%r24 ldil L'LC$0046,%r23 ldo R'LC$0046(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0174: stw %r9,0(%r10) L$0173: L$0166: copy %r9,%r28 bl,n L$0163,%r0 L$0163: ldw 32(%r4),%r12 ldw 36(%r4),%r11 ldw 40(%r4),%r10 ldw 44(%r4),%r9 ldw 48(%r4),%r8 ldw 52(%r4),%r7 ldw 56(%r4),%r6 ldw 60(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT puts_filtered,CODE .align 4 LC$0047: .STRING " \x00" .IMPORT printf_filtered,CODE .align 4 LC$0048: .STRING "1\x00" .align 4 LC$0049: .STRING "0\x00" .align 4 print_bit_vector: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,16(%r4) stw %r7,20(%r4) stw %r6,24(%r4) stw %r5,28(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) stw %r0,8(%r4) L$0204: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 8(%r4),%r20 ldw 0(%r19),%r19 comclr,< %r20,%r19,%r0 bl L$0205,%r0 nop ldw 8(%r4),%r19 ldw 8(%r4),%r20 comiclr,> 0,%r19,%r0 bl L$0208,%r0 nop ldo 7(%r19),%r19 L$0208: extrs %r19,28,29,%r19 zdep %r19,28,29,%r21 sub %r20,%r21,%r19 comiclr,= 0,%r19,%r0 bl L$0207,%r0 nop ldil L'LC$0047,%r26 ldo R'LC$0047(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0207: ldw 8(%r4),%r20 extrs %r20,28,29,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 add %r19,%r21,%r20 ldb 0(%r20),%r19 ldw 8(%r4),%r20 extru %r20,31,3,%r21 subi,>>= 31,%r21,%r20 copy %r0,%r20 mtsar %r20 vextrs %r19,32,%r19 extru %r19,31,1,%r20 comiclr,<> 0,%r20,%r0 bl L$0209,%r0 nop ldil L'LC$0048,%r26 ldo R'LC$0048(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0210,%r0 L$0209: ldil L'LC$0049,%r26 ldo R'LC$0049(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop L$0210: L$0206: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0204,%r0 L$0205: L$0203: ldw 16(%r4),%r8 ldw 20(%r4),%r7 ldw 24(%r4),%r6 ldw 28(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT recursive_dump_type,CODE .align 4 print_arg_types: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,8(%r4) stw %r7,12(%r4) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0212,%r0 nop L$0213: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0214,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 2(%r21),%r20 ldw 0(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 4(%r20),%r21 stw %r21,0(%r19) ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 9,%r20,%r0 bl L$0215,%r0 nop bl,n L$0214,%r0 L$0215: bl,n L$0213,%r0 L$0214: L$0212: L$0211: ldw 8(%r4),%r8 ldw 12(%r4),%r7 ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT printfi_filtered,CODE .align 4 LC$0050: .STRING "fn_fieldlists 0x%x\x0a\x00" .align 4 LC$0051: .STRING "[%d] name '%s' (0x%x) length %d\x0a\x00" .align 4 LC$0052: .STRING "[%d] physname '%s' (0x%x)\x0a\x00" .align 4 LC$0053: .STRING "type 0x%x\x0a\x00" .align 4 LC$0054: .STRING "args 0x%x\x0a\x00" .align 4 LC$0055: .STRING "fcontext 0x%x\x0a\x00" .align 4 LC$0056: .STRING "is_const %d\x0a\x00" .align 4 LC$0057: .STRING "is_volatile %d\x0a\x00" .align 4 LC$0058: .STRING "is_private %d\x0a\x00" .align 4 LC$0059: .STRING "is_protected %d\x0a\x00" .align 4 LC$0060: .STRING "is_stub %d\x0a\x00" .align 4 LC$0061: .STRING "voffset %u\x0a\x00" .align 4 dump_fn_fieldlists: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r8,24(%r4) stw %r7,28(%r4) stw %r6,32(%r4) stw %r5,36(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldw 48(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0050,%r25 ldo R'LC$0050(%r25),%r25 ldw 20(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop stw %r0,8(%r4) L$0217: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 2(%r20),%r21 extrs %r21,31,16,%r19 ldw 8(%r4),%r20 comclr,< %r20,%r19,%r0 bl L$0218,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldw 8(%r4),%r21 zdep %r21,30,31,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 20(%r19),%r21 add %r20,%r21,%r19 ldw 8(%r19),%r20 stw %r20,16(%r4) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 2(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldw 48(%r21),%r20 ldw 8(%r4),%r22 zdep %r22,30,31,%r21 add %r21,%r22,%r21 zdep %r21,29,30,%r21 ldw 20(%r20),%r22 add %r21,%r22,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 8(%r4),%r23 zdep %r23,30,31,%r22 add %r22,%r23,%r22 zdep %r22,29,30,%r22 ldw 20(%r21),%r23 add %r22,%r23,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 8(%r4),%r23 zdep %r23,30,31,%r22 add %r22,%r23,%r22 zdep %r22,29,30,%r22 ldw 20(%r21),%r23 add %r22,%r23,%r21 ldw 4(%r21),%r22 stw %r22,-56(%r30) copy %r19,%r26 ldil L'LC$0051,%r25 ldo R'LC$0051(%r25),%r25 ldw 8(%r4),%r24 ldw 0(%r20),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop stw %r0,12(%r4) L$0220: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldw 8(%r4),%r21 zdep %r21,30,31,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 20(%r19),%r21 add %r20,%r21,%r19 ldw 12(%r4),%r20 ldw 4(%r19),%r19 comclr,< %r20,%r19,%r0 bl L$0221,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 4(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 12(%r4),%r22 zdep %r22,29,30,%r21 add %r21,%r22,%r21 zdep %r21,29,30,%r21 ldw 16(%r4),%r22 add %r21,%r22,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) copy %r19,%r26 ldil L'LC$0052,%r25 ldo R'LC$0052(%r25),%r25 ldw 12(%r4),%r24 ldw 0(%r20),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 copy %r19,%r26 ldil L'LC$0053,%r25 ldo R'LC$0053(%r25),%r25 ldw 4(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldw 12(%r4),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 16(%r4),%r20 add %r19,%r20,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 10(%r21),%r20 ldw 4(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r22 add %r20,%r22,%r21 ldw 4(%r21),%r20 copy %r19,%r26 ldil L'LC$0054,%r25 ldo R'LC$0054(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldw 12(%r4),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 16(%r4),%r21 add %r19,%r21,%r20 ldw 4(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 48(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl print_arg_types,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 copy %r19,%r26 ldil L'LC$0055,%r25 ldo R'LC$0055(%r25),%r25 ldw 12(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,0+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0056,%r25 ldo R'LC$0056(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,1+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0057,%r25 ldo R'LC$0057(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,2+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0058,%r25 ldo R'LC$0058(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,3+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0059,%r25 ldo R'LC$0059(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,4+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0060,%r25 ldo R'LC$0060(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,8+24-1,24,%r22 ldo -2(%r22),%r20 copy %r19,%r26 ldil L'LC$0061,%r25 ldo R'LC$0061(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop L$0222: ldw 12(%r4),%r19 ldo 1(%r19),%r20 stw %r20,12(%r4) bl,n L$0220,%r0 L$0221: L$0219: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0217,%r0 L$0218: L$0216: ldw 24(%r4),%r8 ldw 28(%r4),%r7 ldw 32(%r4),%r6 ldw 36(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0062: .STRING "n_baseclasses %d\x0a\x00" .align 4 LC$0063: .STRING "nfn_fields %d\x0a\x00" .align 4 LC$0064: .STRING "nfn_fields_total %d\x0a\x00" .align 4 LC$0065: .STRING "virtual_field_bits (%d bits at 0x%x)\x00" .align 4 LC$0066: .STRING "\x0a\x00" .align 4 LC$0067: .STRING "private_field_bits (%d bits at 0x%x)\x00" .align 4 LC$0068: .STRING "protected_field_bits (%d bits at *0x%x)\x00" .align 4 print_cplus_stuff: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,16(%r4) stw %r7,20(%r4) stw %r6,24(%r4) stw %r5,28(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 0(%r21),%r22 extrs %r22,31,16,%r20 ldw 0(%r19),%r26 ldil L'LC$0062,%r25 ldo R'LC$0062(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 2(%r21),%r22 extrs %r22,31,16,%r20 ldw 0(%r19),%r26 ldil L'LC$0063,%r25 ldo R'LC$0063(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldw 48(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0064,%r25 ldo R'LC$0064(%r25),%r25 ldw 4(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 comiclr,< 0,%r19,%r0 bl L$0224,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 0(%r21),%r22 extrs %r22,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0065,%r25 ldo R'LC$0065(%r25),%r25 copy %r20,%r24 ldw 8(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 0(%r21),%r22 extrs %r22,31,16,%r20 ldw 8(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl print_bit_vector,%r2 nop ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0224: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 34(%r19),%r20 extrs %r20,31,16,%r19 comiclr,< 0,%r19,%r0 bl L$0225,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldw 12(%r20),%r19 comiclr,<> 0,%r19,%r0 bl L$0226,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0067,%r25 ldo R'LC$0067(%r25),%r25 copy %r20,%r24 ldw 12(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldw 12(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl print_bit_vector,%r2 nop ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0226: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldw 16(%r20),%r19 comiclr,<> 0,%r19,%r0 bl L$0227,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0068,%r25 ldo R'LC$0068(%r25),%r25 copy %r20,%r24 ldw 16(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldw 16(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl print_bit_vector,%r2 nop ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0227: L$0225: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 2(%r20),%r21 extrs %r21,31,16,%r19 comiclr,< 0,%r19,%r0 bl L$0228,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl dump_fn_fieldlists,%r2 nop L$0228: L$0223: ldw 16(%r4),%r8 ldw 20(%r4),%r7 ldw 24(%r4),%r6 ldw 28(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0069: .STRING "type node 0x%x\x0a\x00" .align 4 LC$0070: .STRING "name '%s' (0x%x)\x0a\x00" .align 4 LC$0071: .STRING "<NULL>\x00" .align 4 LC$0072: .STRING "code 0x%x \x00" .align 4 LC$0073: .STRING "(TYPE_CODE_UNDEF)\x00" .align 4 LC$0074: .STRING "(TYPE_CODE_PTR)\x00" .align 4 LC$0075: .STRING "(TYPE_CODE_ARRAY)\x00" .align 4 LC$0076: .STRING "(TYPE_CODE_STRUCT)\x00" .align 4 LC$0077: .STRING "(TYPE_CODE_UNION)\x00" .align 4 LC$0078: .STRING "(TYPE_CODE_ENUM)\x00" .align 4 LC$0079: .STRING "(TYPE_CODE_FUNC)\x00" .align 4 LC$0080: .STRING "(TYPE_CODE_INT)\x00" .align 4 LC$0081: .STRING "(TYPE_CODE_FLT)\x00" .align 4 LC$0082: .STRING "(TYPE_CODE_VOID)\x00" .align 4 LC$0083: .STRING "(TYPE_CODE_SET)\x00" .align 4 LC$0084: .STRING "(TYPE_CODE_RANGE)\x00" .align 4 LC$0085: .STRING "(TYPE_CODE_PASCAL_ARRAY)\x00" .align 4 LC$0086: .STRING "(TYPE_CODE_ERROR)\x00" .align 4 LC$0087: .STRING "(TYPE_CODE_MEMBER)\x00" .align 4 LC$0088: .STRING "(TYPE_CODE_METHOD)\x00" .align 4 LC$0089: .STRING "(TYPE_CODE_REF)\x00" .align 4 LC$0090: .STRING "(TYPE_CODE_CHAR)\x00" .align 4 LC$0091: .STRING "(TYPE_CODE_BOOL)\x00" .align 4 LC$0092: .STRING "(UNKNOWN TYPE CODE)\x00" .align 4 LC$0093: .STRING "length %d\x0a\x00" .align 4 LC$0094: .STRING "objfile 0x%x\x0a\x00" .align 4 LC$0095: .STRING "target_type 0x%x\x0a\x00" .align 4 LC$0096: .STRING "pointer_type 0x%x\x0a\x00" .align 4 LC$0097: .STRING "reference_type 0x%x\x0a\x00" .align 4 LC$0098: .STRING "function_type 0x%x\x0a\x00" .align 4 LC$0099: .STRING "flags 0x%x\x00" .align 4 LC$0100: .STRING " TYPE_FLAG_UNSIGNED\x00" .align 4 LC$0101: .STRING " TYPE_FLAG_SIGNED\x00" .align 4 LC$0102: .STRING " TYPE_FLAG_STUB\x00" .align 4 LC$0103: .STRING "nfields %d 0x%x\x0a\x00" .align 4 LC$0104: .STRING "[%d] bitpos %d bitsize %d type 0x%x name '%s' (0x%x)\x0a\x00" .align 4 LC$0105: .STRING "vptr_basetype 0x%x\x0a\x00" .align 4 LC$0106: .STRING "vptr_fieldno %d\x0a\x00" .align 4 LC$0107: .STRING "arg_types 0x%x\x0a\x00" .align 4 LC$0108: .STRING "cplus_stuff 0x%x\x0a\x00" .align 4 LC$0109: .STRING "type_specific 0x%x\x00" .align 4 LC$0110: .STRING " (unknown data form)\x00" .align 4 .EXPORT recursive_dump_type,CODE .EXPORT recursive_dump_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR recursive_dump_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,16(%r4) stw %r7,20(%r4) stw %r6,24(%r4) stw %r5,28(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r19),%r26 ldil L'LC$0069,%r25 ldo R'LC$0069(%r25),%r25 ldw 0(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 4(%r22),%r21 ldo -4(%r0),%r22 ldo -32(%r4),%r24 add %r24,%r22,%r23 ldw 0(%r23),%r22 ldw 4(%r22),%r23 comiclr,= 0,%r23,%r0 bl L$0230,%r0 nop ldil L'LC$0071,%r21 ldo R'LC$0071(%r21),%r21 L$0230: ldw 0(%r19),%r26 ldil L'LC$0070,%r25 ldo R'LC$0070(%r25),%r25 ldw 4(%r20),%r24 copy %r21,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0072,%r25 ldo R'LC$0072(%r25),%r25 ldw 0(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 addi,uv -19,%r20,%r0 blr,n %r20,%r0 b,n L$0251 L$0252: b L$0232 nop b L$0233 nop b L$0234 nop b L$0235 nop b L$0236 nop b L$0237 nop b L$0238 nop b L$0239 nop b L$0240 nop b L$0241 nop b L$0242 nop b L$0243 nop b L$0244 nop b L$0245 nop b L$0246 nop b L$0247 nop b L$0248 nop b L$0249 nop b L$0250 nop L$0232: ldil L'LC$0073,%r26 ldo R'LC$0073(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0233: ldil L'LC$0074,%r26 ldo R'LC$0074(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0234: ldil L'LC$0075,%r26 ldo R'LC$0075(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0235: ldil L'LC$0076,%r26 ldo R'LC$0076(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0236: ldil L'LC$0077,%r26 ldo R'LC$0077(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0237: ldil L'LC$0078,%r26 ldo R'LC$0078(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0238: ldil L'LC$0079,%r26 ldo R'LC$0079(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0239: ldil L'LC$0080,%r26 ldo R'LC$0080(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0240: ldil L'LC$0081,%r26 ldo R'LC$0081(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0241: ldil L'LC$0082,%r26 ldo R'LC$0082(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0242: ldil L'LC$0083,%r26 ldo R'LC$0083(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0243: ldil L'LC$0084,%r26 ldo R'LC$0084(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0244: ldil L'LC$0085,%r26 ldo R'LC$0085(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0245: ldil L'LC$0086,%r26 ldo R'LC$0086(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0246: ldil L'LC$0087,%r26 ldo R'LC$0087(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0247: ldil L'LC$0088,%r26 ldo R'LC$0088(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0248: ldil L'LC$0089,%r26 ldo R'LC$0089(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0249: ldil L'LC$0090,%r26 ldo R'LC$0090(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0250: ldil L'LC$0091,%r26 ldo R'LC$0091(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0251: ldil L'LC$0092,%r26 ldo R'LC$0092(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0231: ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0093,%r25 ldo R'LC$0093(%r25),%r25 ldw 8(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0094,%r25 ldo R'LC$0094(%r25),%r25 ldw 12(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0095,%r25 ldo R'LC$0095(%r25),%r25 ldw 16(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 16(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0253,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 2(%r21),%r20 ldw 16(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop L$0253: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0096,%r25 ldo R'LC$0096(%r25),%r25 ldw 20(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0097,%r25 ldo R'LC$0097(%r25),%r25 ldw 24(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0098,%r25 ldo R'LC$0098(%r25),%r25 ldw 28(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 32(%r20),%r21 extrs %r21,31,16,%r20 ldw 0(%r19),%r26 ldil L'LC$0099,%r25 ldo R'LC$0099(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 extru %r20,31,1,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0254,%r0 nop ldil L'LC$0100,%r26 ldo R'LC$0100(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0254: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 ldo 2(%r0),%r21 and %r20,%r21,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0255,%r0 nop ldil L'LC$0101,%r26 ldo R'LC$0101(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0255: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 ldo 4(%r0),%r21 and %r20,%r21,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0256,%r0 nop ldil L'LC$0102,%r26 ldo R'LC$0102(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0256: ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0103,%r25 ldo R'LC$0103(%r25),%r25 copy %r20,%r24 ldw 36(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop stw %r0,8(%r4) L$0257: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 34(%r19),%r20 extrs %r20,31,16,%r19 ldw 8(%r4),%r20 comclr,< %r20,%r19,%r0 bl L$0258,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 2(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 8(%r4),%r21 zdep %r21,27,28,%r22 ldw 36(%r20),%r21 add %r22,%r21,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 4(%r21),%r22 stw %r22,-52(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 8(%r21),%r22 stw %r22,-56(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 12(%r21),%r22 stw %r22,-60(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 12(%r21),%r22 stw %r22,-64(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 12(%r21),%r22 comiclr,= 0,%r22,%r0 bl L$0260,%r0 nop ldil L'LC$0071,%r21 ldo R'LC$0071(%r21),%r21 stw %r21,-64(%r30) L$0260: copy %r19,%r26 ldil L'LC$0104,%r25 ldo R'LC$0104(%r25),%r25 ldw 8(%r4),%r24 ldw 0(%r20),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0261,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 4(%r21),%r20 ldw 8(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop L$0261: L$0259: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0257,%r0 L$0258: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0105,%r25 ldo R'LC$0105(%r25),%r25 ldw 40(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 40(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0262,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 2(%r21),%r20 ldw 40(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop L$0262: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0106,%r25 ldo R'LC$0106(%r25),%r25 ldw 44(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 0(%r20),%r19 comiclr,<> 6,%r19,%r0 bl L$0265,%r0 nop comiclr,>= 6,%r19,%r0 bl L$0270,%r0 nop comiclr,<> 3,%r19,%r0 bl L$0266,%r0 nop bl,n L$0267,%r0 L$0270: comiclr,<> 15,%r19,%r0 bl L$0264,%r0 nop bl,n L$0267,%r0 L$0264: L$0265: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0107,%r25 ldo R'LC$0107(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 48(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl print_arg_types,%r2 nop bl,n L$0263,%r0 L$0266: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0108,%r25 ldo R'LC$0108(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl print_cplus_stuff,%r2 nop bl,n L$0263,%r0 L$0267: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0109,%r25 ldo R'LC$0109(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0268,%r0 nop ldil L'LC$0110,%r26 ldo R'LC$0110(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop L$0268: ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0263,%r0 L$0263: L$0229: ldw 16(%r4),%r8 ldw 20(%r4),%r7 ldw 24(%r4),%r6 ldw 28(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND
stsp/binutils-ia16	4,410	gas/testsuite/gas/i386/ilp32/reloc64.s	.macro bad args:vararg .ifdef _bad_ \args .endif .endm .macro ill args:vararg # This is used to mark entries that aren't handled consistently, # and thus shouldn't currently be checked for. # \args .endm .text _start: add $xtrn, %rax mov $xtrn, %eax mov $xtrn, %ax mov $xtrn, %al mov xtrn(%rbx), %eax mov xtrn(%ebx), %eax add $(xtrn - .), %rax ill mov $(xtrn - .), %eax mov $(xtrn - .), %ax mov $(xtrn - .), %al mov xtrn(%rip), %eax mov xtrn(%eip), %eax call xtrn jrcxz xtrn add $xtrn@got, %rax mov $xtrn@got, %eax bad mov $xtrn@got, %ax bad mov $xtrn@got, %al mov xtrn@got(%rbx), %eax mov xtrn@got(%ebx), %eax bad call xtrn@got bad add $xtrn@gotoff, %rax bad mov $xtrn@gotoff, %eax bad mov $xtrn@gotoff, %ax bad mov $xtrn@gotoff, %al bad mov xtrn@gotoff(%rbx), %eax bad mov xtrn@gotoff(%ebx), %eax bad call xtrn@gotoff bad movabs $xtrn@gotpcrel, %rax add $xtrn@gotpcrel, %rax mov $xtrn@gotpcrel, %eax bad mov $xtrn@gotpcrel, %ax bad mov $xtrn@gotpcrel, %al mov xtrn@gotpcrel(%rbx), %eax mov xtrn@gotpcrel(%ebx), %eax call xtrn@gotpcrel ill movabs $_GLOBAL_OFFSET_TABLE_, %rax add $_GLOBAL_OFFSET_TABLE_, %rax ill add $_GLOBAL_OFFSET_TABLE_, %eax ill add $_GLOBAL_OFFSET_TABLE_, %ax ill add $_GLOBAL_OFFSET_TABLE_, %al lea _GLOBAL_OFFSET_TABLE_(%rip), %rax lea _GLOBAL_OFFSET_TABLE_(%eip), %rax ill movabs $(_GLOBAL_OFFSET_TABLE_ - .), %rax add $(_GLOBAL_OFFSET_TABLE_ - .), %rax ill add $(_GLOBAL_OFFSET_TABLE_ - .), %eax ill add $(_GLOBAL_OFFSET_TABLE_ - .), %ax ill add $(_GLOBAL_OFFSET_TABLE_ - .), %al bad movabs $xtrn@plt, %rax add $xtrn@plt, %rax mov $xtrn@plt, %eax bad mov $xtrn@plt, %ax bad mov $xtrn@plt, %al mov xtrn@plt(%rbx), %eax mov xtrn@plt(%ebx), %eax call xtrn@plt bad jrcxz xtrn@plt bad movabs $xtrn@tlsgd, %rax add $xtrn@tlsgd, %rax mov $xtrn@tlsgd, %eax bad mov $xtrn@tlsgd, %ax bad mov $xtrn@tlsgd, %al mov xtrn@tlsgd(%rbx), %eax mov xtrn@tlsgd(%ebx), %eax call xtrn@tlsgd bad movabs $xtrn@gottpoff, %rax add $xtrn@gottpoff, %rax mov $xtrn@gottpoff, %eax bad mov $xtrn@gottpoff, %ax bad mov $xtrn@gottpoff, %al mov xtrn@gottpoff(%rbx), %eax mov xtrn@gottpoff(%ebx), %eax call xtrn@gottpoff bad movabs $xtrn@tlsld, %rax add $xtrn@tlsld, %rax mov $xtrn@tlsld, %eax bad mov $xtrn@tlsld, %ax bad mov $xtrn@tlsld, %al mov xtrn@tlsld(%rbx), %eax mov xtrn@tlsld(%ebx), %eax call xtrn@tlsld add $xtrn@dtpoff, %rax mov $xtrn@dtpoff, %eax bad mov $xtrn@dtpoff, %ax bad mov $xtrn@dtpoff, %al mov xtrn@dtpoff(%rbx), %eax mov xtrn@dtpoff(%ebx), %eax bad call xtrn@dtpoff add $xtrn@tpoff, %rax mov $xtrn@tpoff, %eax bad mov $xtrn@tpoff, %ax bad mov $xtrn@tpoff, %al mov xtrn@tpoff(%rbx), %eax mov xtrn@tpoff(%ebx), %eax bad call xtrn@tpoff .data .long xtrn .long xtrn - . .long xtrn@got bad .long xtrn@gotoff .long xtrn@gotpcrel .long _GLOBAL_OFFSET_TABLE_ .long _GLOBAL_OFFSET_TABLE_ - . .long xtrn@plt .long xtrn@tlsgd .long xtrn@gottpoff .long xtrn@tlsld .long xtrn@dtpoff .long xtrn@tpoff .slong xtrn .slong xtrn - . .slong xtrn@got bad .slong xtrn@gotoff .slong xtrn@gotpcrel .slong _GLOBAL_OFFSET_TABLE_ .slong _GLOBAL_OFFSET_TABLE_ - . .slong xtrn@plt .slong xtrn@tlsgd .slong xtrn@gottpoff .slong xtrn@tlsld .slong xtrn@dtpoff .slong xtrn@tpoff .word xtrn .word xtrn - . bad .word xtrn@got bad .word xtrn@gotoff bad .word xtrn@gotpcrel ill .word _GLOBAL_OFFSET_TABLE_ ill .word _GLOBAL_OFFSET_TABLE_ - . bad .word xtrn@plt bad .word xtrn@tlsgd bad .word xtrn@gottpoff bad .word xtrn@tlsld bad .word xtrn@dtpoff bad .word xtrn@tpoff .byte xtrn .byte xtrn - . bad .byte xtrn@got bad .byte xtrn@gotoff bad .byte xtrn@gotpcrel ill .byte _GLOBAL_OFFSET_TABLE_ ill .byte _GLOBAL_OFFSET_TABLE_ - . bad .byte xtrn@plt bad .byte xtrn@tlsgd bad .byte xtrn@gottpoff bad .byte xtrn@tlsld bad .byte xtrn@dtpoff bad .byte xtrn@tpoff .text mov xtrn@tpoff (%rbx), %eax movabsq $xtrn + 0x7fffffff, %rbx movabsq $xtrn - 0x80000000, %rbp .data .quad xtrn .quad xtrn + 0x7fffffff .quad xtrn - 0x80000000 .long xtrn@got - 4 .long xtrn@got + 4 bad .long xtrn@plt - . .text bad add $x+0x123456789, %rax bad add $x+0x123456789, %eax bad add x+0x123456789, %eax bad add x+0x123456789(%eax), %eax bad enter $x+0x123456789, $x+0x123456789 bad enter $x+0x12345, $x+0x123 .data bad .long x+0x123456789 bad .word x+0x123456789 bad .word x+0x12345 bad .byte x+0x123456789 bad .byte x+0x123
stsp/binutils-ia16	5,599	gas/testsuite/gas/i386/ilp32/x86-64.s	.text .intel_syntax noprefix # REX prefix and addressing modes. add edx,ecx add edx,r9d add r10d,ecx add rdx,rcx add r10,r9 add r8d,eax add r8w,ax add r8,rax add eax,0x44332211 add rax,0xfffffffff4332211 add ax,0x4433 add rax,0x44332211 add dl,cl add bh,dh add dil,sil add r15b,sil add dil,r14b add r15b,r14b PUSH RAX PUSH R8 POP R9 ADD AL,0x11 ADD AH,0x11 ADD SPL,0x11 ADD R8B,0x11 ADD R12B,0x11 MOV RAX,CR0 MOV R8,CR0 MOV RAX,CR8 MOV CR8,RAX REP MOVSQ #[RSI],[RDI] REP MOVSW #[RSI,[RDI] REP MOVSQ #[RSI],[RDI] MOV AL, 0x11 MOV AH, 0x11 MOV SPL, 0x11 MOV R12B, 0x11 MOV EAX,0x11223344 MOV R8D,0x11223344 MOV RAX,0x1122334455667788 MOV R8,0x1122334455667788 add eax,[rax] ADD EAX,[R8] ADD R8D,[R8] ADD RAX,[R8] ADD EAX,[0x22222222+RIP] ADD EAX,[RBP+0x00] ADD EAX,FLAT:[0x22222222] ADD EAX,[R13+0] ADD EAX,[RAX+RAX4] ADD EAX,[R8+RAX4] ADD R8D,[R8+RAX4] ADD EAX,[R8+R84] ADD [RCX+R84],R8D ADD EDX,[RAX+RAX8] ADD EDX,[RAX+RCX8] ADD EDX,[RAX+RDX8] ADD EDX,[RAX+RBX8] ADD EDX,[RAX] ADD EDX,[RAX+RBP8] ADD EDX,[RAX+RSI8] ADD EDX,[RAX+RDI8] ADD EDX,[RAX+R88] ADD EDX,[RAX+R98] ADD EDX,[RAX+R108] ADD EDX,[RAX+R118] ADD EDX,[RAX+R128] ADD EDX,[RAX+R138] ADD EDX,[RAX+R148] ADD EDX,[RAX+R158] ADD ECX,0x11 ADD DWORD PTR [RAX],0x11 ADD QWORD PTR [RAX],0x11 ADD DWORD PTR [R8],0x11 ADD DWORD PTR [RCX+RAX4],0x11 ADD DWORD PTR [R9+RAX4],0x11 ADD DWORD PTR [RCX+R84],0x11 ADD DWORD PTR [0x22222222+RIP],0x33 ADD QWORD PTR [RIP+0x22222222],0x33 ADD DWORD PTR [RIP+0x22222222],0x33333333 ADD QWORD PTR [RIP+0x22222222],0x33333333 ADD DWORD PTR [RAX8+0x22222222],0x33 ADD DWORD PTR [RAX+0x22222222],0x33 ADD DWORD PTR [RAX+0x22222222],0x33 ADD DWORD PTR [R8+RBP*8],0x33 ADD DWORD PTR FLAT:[0x22222222],0x33 #new instructions MOV AL,FLAT:[0x8877665544332211] MOV EAX,FLAT:[0x8877665544332211] MOV FLAT:[0x8877665544332211],AL MOV FLAT:[0x8877665544332211],EAX MOV RAX,FLAT:[0x8877665544332211] MOV FLAT:[0x8877665544332211],RAX cqo cdqe movsx rax, eax movsx rax, ax movsx rax, al bar: .att_syntax #testcase for symbol references. #immediates - various sizes: mov $symbol, %al mov $symbol, %ax mov $symbol, %eax mov $symbol, %rax #addressing modes: #absolute 32bit addressing mov symbol, %eax #arithmetic mov symbol(%rax), %eax #RIP relative mov symbol(%rip), %eax .intel_syntax noprefix #immediates - various sizes: mov al, offset flat:symbol mov ax, offset flat:symbol mov eax, offset flat:symbol mov rax, offset flat:symbol #parts aren't supported by the parser, yet (and not at all for symbol refs) #mov eax, high part symbol #mov eax, low part symbol #addressing modes #absolute 32bit addressing mov eax, [symbol] #arithmetic mov eax, [rax+symbol] #RIP relative mov eax, [rip+symbol] foo: .att_syntax #absolute 64bit addressing mov 0x8877665544332211,%al mov 0x8877665544332211,%ax mov 0x8877665544332211,%eax mov 0x8877665544332211,%rax mov %al,0x8877665544332211 mov %ax,0x8877665544332211 mov %eax,0x8877665544332211 mov %rax,0x8877665544332211 movb 0x8877665544332211,%al movw 0x8877665544332211,%ax movl 0x8877665544332211,%eax movq 0x8877665544332211,%rax movb %al,0x8877665544332211 movw %ax,0x8877665544332211 movl %eax,0x8877665544332211 movq %rax,0x8877665544332211 #absolute signed 32bit addressing mov 0xffffffffff332211,%al mov 0xffffffffff332211,%ax mov 0xffffffffff332211,%eax mov 0xffffffffff332211,%rax mov %al,0xffffffffff332211 mov %ax,0xffffffffff332211 mov %eax,0xffffffffff332211 mov %rax,0xffffffffff332211 movb 0xffffffffff332211,%al movw 0xffffffffff332211,%ax movl 0xffffffffff332211,%eax movq 0xffffffffff332211,%rax movb %al,0xffffffffff332211 movw %ax,0xffffffffff332211 movl %eax,0xffffffffff332211 movq %rax,0xffffffffff332211 cmpxchg16b (%rax) .intel_syntax noprefix cmpxchg16b oword ptr [rax] .att_syntax movsx %al, %si movsx %al, %esi movsx %al, %rsi movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi movsx (%rax), %dx movsbl (%rax), %edx movsbq (%rax), %rdx movsbw (%rax), %dx movswl (%rax), %edx movswq (%rax), %rdx movzx %al, %si movzx %al, %esi movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi movzx (%rax), %dx movzb (%rax), %edx movzb (%rax), %rdx movzb (%rax), %dx movzbl (%rax), %edx movzbq (%rax), %rdx movzbw (%rax), %dx movzwl (%rax), %edx movzwq (%rax), %rdx .intel_syntax noprefix movsx si,al movsx esi,al movsx rsi,al movsx esi,ax movsx rsi,ax movsx rsi,eax movsx edx,BYTE PTR [rax] movsx rdx,BYTE PTR [rax] movsx dx,BYTE PTR [rax] movsx edx,WORD PTR [rax] movsx rdx,WORD PTR [rax] movzx si,al movzx esi,al movzx rsi,al movzx esi,ax movzx rsi,ax movzx edx,BYTE PTR [rax] movzx rdx,BYTE PTR [rax] movzx dx,BYTE PTR [rax] movzx edx,WORD PTR [rax] movzx rdx,WORD PTR [rax] movq xmm1,QWORD PTR [rsp] movq xmm1,[rsp] movq QWORD PTR [rsp],xmm1 movq [rsp],xmm1 .att_syntax fnstsw fnstsw %ax fstsw fstsw %ax .intel_syntax noprefix fnstsw fnstsw ax fstsw fstsw ax .att_syntax movsx (%rax),%ax movsxb (%rax), %dx movsxb (%rax), %edx movsxb (%rax), %rdx movsxw (%rax), %edx movsxw (%rax), %rdx movsxl (%rax), %rdx movsxd (%rax),%rax movzx (%rax),%ax movzxb (%rax), %dx movzxb (%rax), %edx movzxb (%rax), %rdx movzxw (%rax), %edx movzxw (%rax), %rdx movnti %eax, (%rax) movntil %eax, (%rax) movnti %rax, (%rax) movntiq %rax, (%rax) .intel_syntax noprefix movsx ax, BYTE PTR [rax] movsx eax, BYTE PTR [rax] movsx eax, WORD PTR [rax] movsx rax, WORD PTR [rax] movsx rax, DWORD PTR [rax] movsxd rax, [rax] movzx ax, BYTE PTR [rax] movzx eax, BYTE PTR [rax] movzx eax, WORD PTR [rax] movzx rax, WORD PTR [rax] movnti dword ptr [rax], eax movnti qword ptr [rax], rax
stsp/binutils-ia16	4,519	binutils/testsuite/binutils-all/dw2-compressed.S	/* This testcase is derived from a similar test in GDB. Copyright (C) 2008-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / This tests that gdb can read compressed sections. The contents are a basic assembly file, but the .debug_abbrev section has been comrpessed using zlib. / / Dummy function to provide debug information for. / .text .globl _start _start: .int 0 .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .int 0 .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: / Debug information / .section .debug_info .Lcu1_begin: / CU header / .4byte .Lcu1_end - .Lcu1_start / Length of Compilation Unit / .Lcu1_start: .2byte 2 / DWARF Version / .4byte .Labbrev1_begin / Offset into abbrev section / .byte 4 / Pointer size / / CU die / .uleb128 1 / Abbrev: DW_TAG_compile_unit / .4byte .Lline1_begin / DW_AT_stmt_list / .4byte .Lend_text1 / DW_AT_high_pc / .4byte .Lbegin_text1 / DW_AT_low_pc / .ascii "file1.txt\0" / DW_AT_name / .ascii "GNU C 3.3.3\0" / DW_AT_producer / .byte 1 / DW_AT_language (C) / / func_cu1 / .uleb128 2 / Abbrev: DW_TAG_subprogram / .byte 1 / DW_AT_external / .byte 1 / DW_AT_decl_file / .byte 2 / DW_AT_decl_line / .ascii "func_cu1\0" / DW_AT_name / .4byte .Ltype_int-.Lcu1_begin / DW_AT_type / .4byte .Lbegin_func_cu1 / DW_AT_low_pc / .4byte .Lend_func_cu1 / DW_AT_high_pc / .byte 1 / DW_AT_frame_base: length / .byte 0x55 / DW_AT_frame_base: DW_OP_reg5 / .Ltype_int: .uleb128 3 / Abbrev: DW_TAG_base_type / .ascii "int\0" / DW_AT_name / .byte 4 / DW_AT_byte_size / .byte 5 / DW_AT_encoding / .byte 0 / End of children of CU / .Lcu1_end: / Line table / .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start / Initial length / .Lline1_start: .2byte 2 / Version / .4byte .Lline1_lines - .Lline1_hdr / header_length / .Lline1_hdr: .byte 1 / Minimum insn length / .byte 1 / default_is_stmt / .byte 1 / line_base / .byte 1 / line_range / .byte 0x10 / opcode_base / / Standard lengths / .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 / Include directories / .byte 0 / File names / .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lbegin_func_cu1 .byte 3 / DW_LNS_advance_line / .sleb128 3 / ... to 4 / .byte 1 / DW_LNS_copy / .byte 1 / DW_LNS_copy (second time as an end-of-prologue marker) / .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lend_func_cu1 .byte 0 / DW_LNE_end_of_sequence / .uleb128 1 .byte 1 .Lline1_end: / Abbrev table -- compressed */ .section .zdebug_abbrev .Labbrev1_begin: .ascii "ZLIB" .4byte 0 .2byte 0 .byte 0 .byte 51 .byte 0x78 .byte 0x5e .byte 0x63 .byte 0x14 .byte 0x64 .byte 0x14 .byte 0x60 .byte 0x13 .byte 0x62 .byte 0x14 .byte 0x64 .byte 0x64 .byte 0xe6 .byte 0x50 .byte 0xe5 .byte 0x10 .byte 0xe6 .byte 0x66 .byte 0x60 .byte 0x60 .byte 0xd2 .byte 0x63 .byte 0xb0 .byte 0xe7 .byte 0xb1 .byte 0xe2 .byte 0xb6 .byte 0xe6 .byte 0x66 .byte 0xe6 .byte 0xf0 .byte 0x14 .byte 0x16 .byte 0x64 .byte 0x14 .byte 0x62 .byte 0x74 .byte 0xe0 .byte 0x02 .byte 0x00 .byte 0x25 .byte 0x78 .byte 0x02 .byte 0x81 .byte 0x78 .byte 0x9c .byte 0x63 .byte 0x60 .byte 0x60 .byte 0x56 .byte 0x61 .byte 0x60 .byte 0xe6 .byte 0xe0 .byte 0xe6 .byte 0xb6 .byte 0xe3 .byte 0x66 .byte 0x00 .byte 0x02 .byte 0x00 .byte 0x04 .byte 0x9c .byte 0x00 .byte 0x92
stsp/binutils-ia16	1,363	binutils/testsuite/binutils-all/pr25662.s	/* PR 25662: objcopy sets invalid sh_offset for the first section in a no_contents segment containing program headers. Several conditions are required for the bug to manifest: - The first loadable segment (which contains the program headers) must only contain SHT_NOBITS sections. .bss is the SHT_NOBITS section in this test. - The next loadable segment must have a !SHT_NOBITS loadable section. .data is the !SHT_NOBITS section in this test. - .bss must be positioned after .data in the executable file itself. - The size of .data must be such that the calculated VMA of the .bss section that follows it is not congruent with the file offset of .bss, modulo the p_align of its segment, i.e.: (VMA(.data) + sizeof(.data)) % (.bss_segment.p_align) != 0 This will force the sh_offset of .bss to be aligned so it appears within .data. - The size of .data must be larger than the program headers in the first loadable segment, so that the file offset of .bss is immediately after .data, and not padded to a valid alignment by the program headers. The bug originally only manifested for ELF targets, but there's no reason not to run this testcase for other file formats. */ .section .bss aaa: .zero 0x2 .section .data ccc: .zero 0x201 .section .text .global _start _start: .long 0
stsp/binutils-ia16	35,389	binutils/testsuite/binutils-all/dw4.s	.file "main.c" .text .Ltext0: .text .globl main .type main, %function main: .LFB0: .file 1 "main.c" .loc 1 6 1 view -0 .word 1234 .word 5678 .LFE0: .size main, . - main .globl g_my_private_global .data .align 4 .type g_my_private_global, %object .size g_my_private_global, 4 g_my_private_global: .zero 4 .globl g_my_externd_global .data .align 4 .type g_my_externd_global, %object .size g_my_externd_global, 4 g_my_externd_global: .zero 4 .text .Letext0: .section .debug_info,"",%progbits .Ldebug_info0: .long .Linfo_end - .Linfo_start .Linfo_start: .short 0x4 .long .Ldebug_abbrev0 .byte 0x8 .uleb128 0x1 .long .LASF345 .byte 0xc .long .LASF346 .long .LASF347 .long .Ldebug_ranges0 + 0 .quad 0 .long .Ldebug_line0 .long .Ldebug_macro0 .Lvar_decl: .uleb128 0x2 .long .LASF343 .byte 0x1 .byte 0x2 .byte 0xc .long 0x39 .uleb128 0x3 .byte 0x4 .byte 0x5 .string "int" .uleb128 0x4 .long .Lvar_decl - .Ldebug_info0 .byte 0x3 .byte 0x5 .uleb128 .Lblock1_end - .Lblock1_start .Lblock1_start: .byte 0x3 .dc.a g_my_externd_global .Lblock1_end: .uleb128 0x5 .long .LASF344 .byte 0x1 .byte 0x4 .byte 0x5 .long 0x39 .uleb128 .Lblock2_end - .Lblock2_start .Lblock2_start: .byte 0x3 .dc.a g_my_private_global .Lblock2_end: .uleb128 0x6 .long .LASF348 .byte 0x1 .byte 0x5 .byte 0x5 .long 0x39 .quad 0 .quad 0x10 .uleb128 0x1 .byte 0x9c .byte 0 .Linfo_end: .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0xe .uleb128 0x1b .uleb128 0xe .uleb128 0x55 .uleb128 0x17 .uleb128 0x11 .uleb128 0x1 .uleb128 0x10 .uleb128 0x17 .uleb128 0x2119 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x2 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x3f .uleb128 0x19 .uleb128 0x3c .uleb128 0x19 .byte 0 .byte 0 .uleb128 0x3 .uleb128 0x24 .byte 0 .uleb128 0xb .uleb128 0xb .uleb128 0x3e .uleb128 0xb .uleb128 0x3 .uleb128 0x8 .byte 0 .byte 0 .uleb128 0x4 .uleb128 0x34 .byte 0 .uleb128 0x47 .uleb128 0x13 .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x2 .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x5 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x3f .uleb128 0x19 .uleb128 0x2 .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x6 .uleb128 0x2e .byte 0 .uleb128 0x3f .uleb128 0x19 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x27 .uleb128 0x19 .uleb128 0x49 .uleb128 0x13 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x7 .uleb128 0x40 .uleb128 0x18 .uleb128 0x2117 .uleb128 0x19 .byte 0 .byte 0 .byte 0 .section .debug_aranges,"",%progbits .long 0x2c .short 0x2 .long .Ldebug_info0 .byte 0x8 .byte 0 .short 0 .short 0 .dc.a .LFB0 .quad .LFE0 - .LFB0 .quad 0 .quad 0 .section .debug_ranges,"",%progbits .Ldebug_ranges0: .dc.a .LFB0 .dc.a .LFE0 .quad 0 .quad 0 .section .debug_macro,"",%progbits .Ldebug_macro0: .short 0x4 .byte 0x2 .long .Ldebug_line0 .byte 0x3 .uleb128 0 .uleb128 0x1 .byte 0x5 .uleb128 0x1 .long .LASF0 .byte 0x5 .uleb128 0x2 .long .LASF1 .byte 0x5 .uleb128 0x3 .long .LASF2 .byte 0x5 .uleb128 0x4 .long .LASF3 .byte 0x5 .uleb128 0x5 .long .LASF4 .byte 0x5 .uleb128 0x6 .long .LASF5 .byte 0x5 .uleb128 0x7 .long .LASF6 .byte 0x5 .uleb128 0x8 .long .LASF7 .byte 0x5 .uleb128 0x9 .long .LASF8 .byte 0x5 .uleb128 0xa .long .LASF9 .byte 0x5 .uleb128 0xb .long .LASF10 .byte 0x5 .uleb128 0xc .long .LASF11 .byte 0x5 .uleb128 0xd .long .LASF12 .byte 0x5 .uleb128 0xe .long .LASF13 .byte 0x5 .uleb128 0xf .long .LASF14 .byte 0x5 .uleb128 0x10 .long .LASF15 .byte 0x5 .uleb128 0x11 .long .LASF16 .byte 0x5 .uleb128 0x12 .long .LASF17 .byte 0x5 .uleb128 0x13 .long .LASF18 .byte 0x5 .uleb128 0x14 .long .LASF19 .byte 0x5 .uleb128 0x15 .long .LASF20 .byte 0x5 .uleb128 0x16 .long .LASF21 .byte 0x5 .uleb128 0x17 .long .LASF22 .byte 0x5 .uleb128 0x18 .long .LASF23 .byte 0x5 .uleb128 0x19 .long .LASF24 .byte 0x5 .uleb128 0x1a .long .LASF25 .byte 0x5 .uleb128 0x1b .long .LASF26 .byte 0x5 .uleb128 0x1c .long .LASF27 .byte 0x5 .uleb128 0x1d .long .LASF28 .byte 0x5 .uleb128 0x1e .long .LASF29 .byte 0x5 .uleb128 0x1f .long .LASF30 .byte 0x5 .uleb128 0x20 .long .LASF31 .byte 0x5 .uleb128 0x21 .long .LASF32 .byte 0x5 .uleb128 0x22 .long .LASF33 .byte 0x5 .uleb128 0x23 .long .LASF34 .byte 0x5 .uleb128 0x24 .long .LASF35 .byte 0x5 .uleb128 0x25 .long .LASF36 .byte 0x5 .uleb128 0x26 .long .LASF37 .byte 0x5 .uleb128 0x27 .long .LASF38 .byte 0x5 .uleb128 0x28 .long .LASF39 .byte 0x5 .uleb128 0x29 .long .LASF40 .byte 0x5 .uleb128 0x2a .long .LASF41 .byte 0x5 .uleb128 0x2b .long .LASF42 .byte 0x5 .uleb128 0x2c .long .LASF43 .byte 0x5 .uleb128 0x2d .long .LASF44 .byte 0x5 .uleb128 0x2e .long .LASF45 .byte 0x5 .uleb128 0x2f .long .LASF46 .byte 0x5 .uleb128 0x30 .long .LASF47 .byte 0x5 .uleb128 0x31 .long .LASF48 .byte 0x5 .uleb128 0x32 .long .LASF49 .byte 0x5 .uleb128 0x33 .long .LASF50 .byte 0x5 .uleb128 0x34 .long .LASF51 .byte 0x5 .uleb128 0x35 .long .LASF52 .byte 0x5 .uleb128 0x36 .long .LASF53 .byte 0x5 .uleb128 0x37 .long .LASF54 .byte 0x5 .uleb128 0x38 .long .LASF55 .byte 0x5 .uleb128 0x39 .long .LASF56 .byte 0x5 .uleb128 0x3a .long .LASF57 .byte 0x5 .uleb128 0x3b .long .LASF58 .byte 0x5 .uleb128 0x3c .long .LASF59 .byte 0x5 .uleb128 0x3d .long .LASF60 .byte 0x5 .uleb128 0x3e .long .LASF61 .byte 0x5 .uleb128 0x3f .long .LASF62 .byte 0x5 .uleb128 0x40 .long .LASF63 .byte 0x5 .uleb128 0x41 .long .LASF64 .byte 0x5 .uleb128 0x42 .long .LASF65 .byte 0x5 .uleb128 0x43 .long .LASF66 .byte 0x5 .uleb128 0x44 .long .LASF67 .byte 0x5 .uleb128 0x45 .long .LASF68 .byte 0x5 .uleb128 0x46 .long .LASF69 .byte 0x5 .uleb128 0x47 .long .LASF70 .byte 0x5 .uleb128 0x48 .long .LASF71 .byte 0x5 .uleb128 0x49 .long .LASF72 .byte 0x5 .uleb128 0x4a .long .LASF73 .byte 0x5 .uleb128 0x4b .long .LASF74 .byte 0x5 .uleb128 0x4c .long .LASF75 .byte 0x5 .uleb128 0x4d .long .LASF76 .byte 0x5 .uleb128 0x4e .long .LASF77 .byte 0x5 .uleb128 0x4f .long .LASF78 .byte 0x5 .uleb128 0x50 .long .LASF79 .byte 0x5 .uleb128 0x51 .long .LASF80 .byte 0x5 .uleb128 0x52 .long .LASF81 .byte 0x5 .uleb128 0x53 .long .LASF82 .byte 0x5 .uleb128 0x54 .long .LASF83 .byte 0x5 .uleb128 0x55 .long .LASF84 .byte 0x5 .uleb128 0x56 .long .LASF85 .byte 0x5 .uleb128 0x57 .long .LASF86 .byte 0x5 .uleb128 0x58 .long .LASF87 .byte 0x5 .uleb128 0x59 .long .LASF88 .byte 0x5 .uleb128 0x5a .long .LASF89 .byte 0x5 .uleb128 0x5b .long .LASF90 .byte 0x5 .uleb128 0x5c .long .LASF91 .byte 0x5 .uleb128 0x5d .long .LASF92 .byte 0x5 .uleb128 0x5e .long .LASF93 .byte 0x5 .uleb128 0x5f .long .LASF94 .byte 0x5 .uleb128 0x60 .long .LASF95 .byte 0x5 .uleb128 0x61 .long .LASF96 .byte 0x5 .uleb128 0x62 .long .LASF97 .byte 0x5 .uleb128 0x63 .long .LASF98 .byte 0x5 .uleb128 0x64 .long .LASF99 .byte 0x5 .uleb128 0x65 .long .LASF100 .byte 0x5 .uleb128 0x66 .long .LASF101 .byte 0x5 .uleb128 0x67 .long .LASF102 .byte 0x5 .uleb128 0x68 .long .LASF103 .byte 0x5 .uleb128 0x69 .long .LASF104 .byte 0x5 .uleb128 0x6a .long .LASF105 .byte 0x5 .uleb128 0x6b .long .LASF106 .byte 0x5 .uleb128 0x6c .long .LASF107 .byte 0x5 .uleb128 0x6d .long .LASF108 .byte 0x5 .uleb128 0x6e .long .LASF109 .byte 0x5 .uleb128 0x6f .long .LASF110 .byte 0x5 .uleb128 0x70 .long .LASF111 .byte 0x5 .uleb128 0x71 .long .LASF112 .byte 0x5 .uleb128 0x72 .long .LASF113 .byte 0x5 .uleb128 0x73 .long .LASF114 .byte 0x5 .uleb128 0x74 .long .LASF115 .byte 0x5 .uleb128 0x75 .long .LASF116 .byte 0x5 .uleb128 0x76 .long .LASF117 .byte 0x5 .uleb128 0x77 .long .LASF118 .byte 0x5 .uleb128 0x78 .long .LASF119 .byte 0x5 .uleb128 0x79 .long .LASF120 .byte 0x5 .uleb128 0x7a .long .LASF121 .byte 0x5 .uleb128 0x7b .long .LASF122 .byte 0x5 .uleb128 0x7c .long .LASF123 .byte 0x5 .uleb128 0x7d .long .LASF124 .byte 0x5 .uleb128 0x7e .long .LASF125 .byte 0x5 .uleb128 0x7f .long .LASF126 .byte 0x5 .uleb128 0x80 .long .LASF127 .byte 0x5 .uleb128 0x81 .long .LASF128 .byte 0x5 .uleb128 0x82 .long .LASF129 .byte 0x5 .uleb128 0x83 .long .LASF130 .byte 0x5 .uleb128 0x84 .long .LASF131 .byte 0x5 .uleb128 0x85 .long .LASF132 .byte 0x5 .uleb128 0x86 .long .LASF133 .byte 0x5 .uleb128 0x87 .long .LASF134 .byte 0x5 .uleb128 0x88 .long .LASF135 .byte 0x5 .uleb128 0x89 .long .LASF136 .byte 0x5 .uleb128 0x8a .long .LASF137 .byte 0x5 .uleb128 0x8b .long .LASF138 .byte 0x5 .uleb128 0x8c .long .LASF139 .byte 0x5 .uleb128 0x8d .long .LASF140 .byte 0x5 .uleb128 0x8e .long .LASF141 .byte 0x5 .uleb128 0x8f .long .LASF142 .byte 0x5 .uleb128 0x90 .long .LASF143 .byte 0x5 .uleb128 0x91 .long .LASF144 .byte 0x5 .uleb128 0x92 .long .LASF145 .byte 0x5 .uleb128 0x93 .long .LASF146 .byte 0x5 .uleb128 0x94 .long .LASF147 .byte 0x5 .uleb128 0x95 .long .LASF148 .byte 0x5 .uleb128 0x96 .long .LASF149 .byte 0x5 .uleb128 0x97 .long .LASF150 .byte 0x5 .uleb128 0x98 .long .LASF151 .byte 0x5 .uleb128 0x99 .long .LASF152 .byte 0x5 .uleb128 0x9a .long .LASF153 .byte 0x5 .uleb128 0x9b .long .LASF154 .byte 0x5 .uleb128 0x9c .long .LASF155 .byte 0x5 .uleb128 0x9d .long .LASF156 .byte 0x5 .uleb128 0x9e .long .LASF157 .byte 0x5 .uleb128 0x9f .long .LASF158 .byte 0x5 .uleb128 0xa0 .long .LASF159 .byte 0x5 .uleb128 0xa1 .long .LASF160 .byte 0x5 .uleb128 0xa2 .long .LASF161 .byte 0x5 .uleb128 0xa3 .long .LASF162 .byte 0x5 .uleb128 0xa4 .long .LASF163 .byte 0x5 .uleb128 0xa5 .long .LASF164 .byte 0x5 .uleb128 0xa6 .long .LASF165 .byte 0x5 .uleb128 0xa7 .long .LASF166 .byte 0x5 .uleb128 0xa8 .long .LASF167 .byte 0x5 .uleb128 0xa9 .long .LASF168 .byte 0x5 .uleb128 0xaa .long .LASF169 .byte 0x5 .uleb128 0xab .long .LASF170 .byte 0x5 .uleb128 0xac .long .LASF171 .byte 0x5 .uleb128 0xad .long .LASF172 .byte 0x5 .uleb128 0xae .long .LASF173 .byte 0x5 .uleb128 0xaf .long .LASF174 .byte 0x5 .uleb128 0xb0 .long .LASF175 .byte 0x5 .uleb128 0xb1 .long .LASF176 .byte 0x5 .uleb128 0xb2 .long .LASF177 .byte 0x5 .uleb128 0xb3 .long .LASF178 .byte 0x5 .uleb128 0xb4 .long .LASF179 .byte 0x5 .uleb128 0xb5 .long .LASF180 .byte 0x5 .uleb128 0xb6 .long .LASF181 .byte 0x5 .uleb128 0xb7 .long .LASF182 .byte 0x5 .uleb128 0xb8 .long .LASF183 .byte 0x5 .uleb128 0xb9 .long .LASF184 .byte 0x5 .uleb128 0xba .long .LASF185 .byte 0x5 .uleb128 0xbb .long .LASF186 .byte 0x5 .uleb128 0xbc .long .LASF187 .byte 0x5 .uleb128 0xbd .long .LASF188 .byte 0x5 .uleb128 0xbe .long .LASF189 .byte 0x5 .uleb128 0xbf .long .LASF190 .byte 0x5 .uleb128 0xc0 .long .LASF191 .byte 0x5 .uleb128 0xc1 .long .LASF192 .byte 0x5 .uleb128 0xc2 .long .LASF193 .byte 0x5 .uleb128 0xc3 .long .LASF194 .byte 0x5 .uleb128 0xc4 .long .LASF195 .byte 0x5 .uleb128 0xc5 .long .LASF196 .byte 0x5 .uleb128 0xc6 .long .LASF197 .byte 0x5 .uleb128 0xc7 .long .LASF198 .byte 0x5 .uleb128 0xc8 .long .LASF199 .byte 0x5 .uleb128 0xc9 .long .LASF200 .byte 0x5 .uleb128 0xca .long .LASF201 .byte 0x5 .uleb128 0xcb .long .LASF202 .byte 0x5 .uleb128 0xcc .long .LASF203 .byte 0x5 .uleb128 0xcd .long .LASF204 .byte 0x5 .uleb128 0xce .long .LASF205 .byte 0x5 .uleb128 0xcf .long .LASF206 .byte 0x5 .uleb128 0xd0 .long .LASF207 .byte 0x5 .uleb128 0xd1 .long .LASF208 .byte 0x5 .uleb128 0xd2 .long .LASF209 .byte 0x5 .uleb128 0xd3 .long .LASF210 .byte 0x5 .uleb128 0xd4 .long .LASF211 .byte 0x5 .uleb128 0xd5 .long .LASF212 .byte 0x5 .uleb128 0xd6 .long .LASF213 .byte 0x5 .uleb128 0xd7 .long .LASF214 .byte 0x5 .uleb128 0xd8 .long .LASF215 .byte 0x5 .uleb128 0xd9 .long .LASF216 .byte 0x5 .uleb128 0xda .long .LASF217 .byte 0x5 .uleb128 0xdb .long .LASF218 .byte 0x5 .uleb128 0xdc .long .LASF219 .byte 0x5 .uleb128 0xdd .long .LASF220 .byte 0x5 .uleb128 0xde .long .LASF221 .byte 0x5 .uleb128 0xdf .long .LASF222 .byte 0x5 .uleb128 0xe0 .long .LASF223 .byte 0x5 .uleb128 0xe1 .long .LASF224 .byte 0x5 .uleb128 0xe2 .long .LASF225 .byte 0x5 .uleb128 0xe3 .long .LASF226 .byte 0x5 .uleb128 0xe4 .long .LASF227 .byte 0x5 .uleb128 0xe5 .long .LASF228 .byte 0x5 .uleb128 0xe6 .long .LASF229 .byte 0x5 .uleb128 0xe7 .long .LASF230 .byte 0x5 .uleb128 0xe8 .long .LASF231 .byte 0x5 .uleb128 0xe9 .long .LASF232 .byte 0x5 .uleb128 0xea .long .LASF233 .byte 0x5 .uleb128 0xeb .long .LASF234 .byte 0x5 .uleb128 0xec .long .LASF235 .byte 0x5 .uleb128 0xed .long .LASF236 .byte 0x5 .uleb128 0xee .long .LASF237 .byte 0x5 .uleb128 0xef .long .LASF238 .byte 0x5 .uleb128 0xf0 .long .LASF239 .byte 0x5 .uleb128 0xf1 .long .LASF240 .byte 0x5 .uleb128 0xf2 .long .LASF241 .byte 0x5 .uleb128 0xf3 .long .LASF242 .byte 0x5 .uleb128 0xf4 .long .LASF243 .byte 0x5 .uleb128 0xf5 .long .LASF244 .byte 0x5 .uleb128 0xf6 .long .LASF245 .byte 0x5 .uleb128 0xf7 .long .LASF246 .byte 0x5 .uleb128 0xf8 .long .LASF247 .byte 0x5 .uleb128 0xf9 .long .LASF248 .byte 0x5 .uleb128 0xfa .long .LASF249 .byte 0x5 .uleb128 0xfb .long .LASF250 .byte 0x5 .uleb128 0xfc .long .LASF251 .byte 0x5 .uleb128 0xfd .long .LASF252 .byte 0x5 .uleb128 0xfe .long .LASF253 .byte 0x5 .uleb128 0xff .long .LASF254 .byte 0x5 .uleb128 0x100 .long .LASF255 .byte 0x5 .uleb128 0x101 .long .LASF256 .byte 0x5 .uleb128 0x102 .long .LASF257 .byte 0x5 .uleb128 0x103 .long .LASF258 .byte 0x5 .uleb128 0x104 .long .LASF259 .byte 0x5 .uleb128 0x105 .long .LASF260 .byte 0x5 .uleb128 0x106 .long .LASF261 .byte 0x5 .uleb128 0x107 .long .LASF262 .byte 0x5 .uleb128 0x108 .long .LASF263 .byte 0x5 .uleb128 0x109 .long .LASF264 .byte 0x5 .uleb128 0x10a .long .LASF265 .byte 0x5 .uleb128 0x10b .long .LASF266 .byte 0x5 .uleb128 0x10c .long .LASF267 .byte 0x5 .uleb128 0x10d .long .LASF268 .byte 0x5 .uleb128 0x10e .long .LASF269 .byte 0x5 .uleb128 0x10f .long .LASF270 .byte 0x5 .uleb128 0x110 .long .LASF271 .byte 0x5 .uleb128 0x111 .long .LASF272 .byte 0x5 .uleb128 0x112 .long .LASF273 .byte 0x5 .uleb128 0x113 .long .LASF274 .byte 0x5 .uleb128 0x114 .long .LASF275 .byte 0x5 .uleb128 0x115 .long .LASF276 .byte 0x5 .uleb128 0x116 .long .LASF277 .byte 0x5 .uleb128 0x117 .long .LASF278 .byte 0x5 .uleb128 0x118 .long .LASF279 .byte 0x5 .uleb128 0x119 .long .LASF280 .byte 0x5 .uleb128 0x11a .long .LASF281 .byte 0x5 .uleb128 0x11b .long .LASF282 .byte 0x5 .uleb128 0x11c .long .LASF283 .byte 0x5 .uleb128 0x11d .long .LASF284 .byte 0x5 .uleb128 0x11e .long .LASF285 .byte 0x5 .uleb128 0x11f .long .LASF286 .byte 0x5 .uleb128 0x120 .long .LASF287 .byte 0x5 .uleb128 0x121 .long .LASF288 .byte 0x5 .uleb128 0x122 .long .LASF289 .byte 0x5 .uleb128 0x123 .long .LASF290 .byte 0x5 .uleb128 0x124 .long .LASF291 .byte 0x5 .uleb128 0x125 .long .LASF292 .byte 0x5 .uleb128 0x126 .long .LASF293 .byte 0x5 .uleb128 0x127 .long .LASF294 .byte 0x5 .uleb128 0x128 .long .LASF295 .byte 0x5 .uleb128 0x129 .long .LASF296 .byte 0x5 .uleb128 0x12a .long .LASF297 .byte 0x5 .uleb128 0x12b .long .LASF298 .byte 0x5 .uleb128 0x12c .long .LASF299 .byte 0x5 .uleb128 0x12d .long .LASF300 .byte 0x5 .uleb128 0x12e .long .LASF301 .byte 0x5 .uleb128 0x12f .long .LASF302 .byte 0x5 .uleb128 0x130 .long .LASF303 .byte 0x5 .uleb128 0x131 .long .LASF304 .byte 0x5 .uleb128 0x132 .long .LASF305 .byte 0x5 .uleb128 0x133 .long .LASF306 .byte 0x5 .uleb128 0x134 .long .LASF307 .byte 0x5 .uleb128 0x135 .long .LASF308 .byte 0x5 .uleb128 0x136 .long .LASF309 .byte 0x5 .uleb128 0x137 .long .LASF310 .byte 0x5 .uleb128 0x138 .long .LASF311 .byte 0x5 .uleb128 0x139 .long .LASF312 .byte 0x5 .uleb128 0x13a .long .LASF313 .byte 0x5 .uleb128 0x13b .long .LASF314 .byte 0x5 .uleb128 0x13c .long .LASF315 .byte 0x5 .uleb128 0x13d .long .LASF316 .byte 0x5 .uleb128 0x13e .long .LASF317 .byte 0x5 .uleb128 0x13f .long .LASF318 .byte 0x5 .uleb128 0x140 .long .LASF319 .byte 0x5 .uleb128 0x141 .long .LASF320 .byte 0x5 .uleb128 0x142 .long .LASF321 .byte 0x5 .uleb128 0x143 .long .LASF322 .byte 0x5 .uleb128 0x144 .long .LASF323 .byte 0x5 .uleb128 0x145 .long .LASF324 .byte 0x5 .uleb128 0x146 .long .LASF325 .byte 0x5 .uleb128 0x147 .long .LASF326 .byte 0x5 .uleb128 0x148 .long .LASF327 .byte 0x5 .uleb128 0x149 .long .LASF328 .byte 0x5 .uleb128 0x14a .long .LASF329 .byte 0x5 .uleb128 0x14b .long .LASF330 .byte 0x5 .uleb128 0x14c .long .LASF331 .byte 0x5 .uleb128 0x14d .long .LASF332 .byte 0x5 .uleb128 0x14e .long .LASF333 .byte 0x5 .uleb128 0x14f .long .LASF334 .byte 0x5 .uleb128 0x150 .long .LASF335 .byte 0x5 .uleb128 0x151 .long .LASF336 .byte 0x5 .uleb128 0x152 .long .LASF337 .byte 0x5 .uleb128 0x153 .long .LASF338 .file 2 "/usr/include/stdc-predef.h" .byte 0x3 .uleb128 0x1f .uleb128 0x2 .byte 0x7 .long .Ldebug_macro2 .byte 0x4 .byte 0x4 .byte 0 .section .debug_macro,"G",%progbits,wm4.stdcpredef.h.19.8dc41bed5d9037ff9622e015fb5f0ce3,comdat .Ldebug_macro2: .short 0x4 .byte 0 .byte 0x5 .uleb128 0x13 .long .LASF339 .byte 0x5 .uleb128 0x26 .long .LASF340 .byte 0x5 .uleb128 0x2e .long .LASF341 .byte 0x5 .uleb128 0x3a .long .LASF342 .byte 0 .section .debug_line,"",%progbits .Ldebug_line0: .section .debug_str,"MS",%progbits,1 .LASF122: .string "__UINT_LEAST8_MAX__ 0xff" .LASF219: .string "__FLT64_HAS_DENORM__ 1" .LASF250: .string "__FLT64X_MANT_DIG__ 64" .LASF2: .string "__STDC_UTF_16__ 1" .LASF252: .string "__FLT64X_MIN_EXP__ (-16381)" .LASF126: .string "__UINT_LEAST32_MAX__ 0xffffffffU" .LASF160: .string "__FLT_EPSILON__ 1.19209289550781250000000000000000000e-7F" .LASF8: .string "__VERSION__ \"9.2.1 20190827 (Red Hat 9.2.1-1)\"" .LASF247: .string "__FLT32X_HAS_DENORM__ 1" .LASF334: .string "__unix 1" .LASF70: .string "__UINTPTR_TYPE__ long unsigned int" .LASF35: .string "__SIZEOF_POINTER__ 8" .LASF90: .string "__WCHAR_WIDTH__ 32" .LASF279: .string "__DEC128_MIN_EXP__ (-6142)" .LASF271: .string "__DEC64_MANT_DIG__ 16" .LASF272: .string "__DEC64_MIN_EXP__ (-382)" .LASF173: .string "__DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L)" .LASF141: .string "__UINT_FAST64_MAX__ 0xffffffffffffffffUL" .LASF335: .string "__unix__ 1" .LASF240: .string "__FLT32X_MAX_EXP__ 1024" .LASF184: .string "__LDBL_MAX_10_EXP__ 4932" .LASF267: .string "__DEC32_MIN__ 1E-95DF" .LASF215: .string "__FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64" .LASF249: .string "__FLT32X_HAS_QUIET_NAN__ 1" .LASF265: .string "__DEC32_MIN_EXP__ (-94)" .LASF234: .string "__FLT128_HAS_INFINITY__ 1" .LASF170: .string "__DBL_MAX_10_EXP__ 308" .LASF216: .string "__FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64" .LASF310: .string "__amd64 1" .LASF188: .string "__LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L" .LASF118: .string "__INT_LEAST32_WIDTH__ 32" .LASF144: .string "__UINTPTR_MAX__ 0xffffffffffffffffUL" .LASF19: .string "__LP64__ 1" .LASF129: .string "__UINT64_C(c) c ## UL" .LASF177: .string "__DBL_HAS_INFINITY__ 1" .LASF1: .string "__STDC_VERSION__ 201710L" .LASF321: .string "__code_model_small__ 1" .LASF239: .string "__FLT32X_MIN_10_EXP__ (-307)" .LASF117: .string "__INT32_C(c) c" .LASF245: .string "__FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32x" .LASF7: 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.LASF342: .string "__STDC_ISO_10646__ 201706L" .LASF92: .string "__PTRDIFF_WIDTH__ 64" .LASF74: .string "__SCHAR_MAX__ 0x7f" .LASF202: .string "__FLT32_MIN__ 1.17549435082228750796873653722224568e-38F32" .LASF6: .string "__GNUC_MINOR__ 2" .LASF206: .string "__FLT32_HAS_INFINITY__ 1" .LASF258: .string "__FLT64X_MIN__ 3.36210314311209350626267781732175260e-4932F64x" .LASF149: .string "__DEC_EVAL_METHOD__ 2" .LASF268: .string "__DEC32_MAX__ 9.999999E96DF" .LASF78: .string "__LONG_LONG_MAX__ 0x7fffffffffffffffLL" .LASF292: .string "__GCC_ATOMIC_BOOL_LOCK_FREE 2" .LASF36: .string "__SIZE_TYPE__ long unsigned int" .LASF308: .string "__SIZEOF_WINT_T__ 4" .LASF194: .string "__FLT32_MANT_DIG__ 24" .LASF146: .string "__GCC_IEC_559_COMPLEX 2" .LASF164: .string "__FLT_HAS_QUIET_NAN__ 1" .LASF153: .string "__FLT_MIN_EXP__ (-125)" .LASF332: .string "__linux__ 1" .LASF244: .string "__FLT32X_MIN__ 2.22507385850720138309023271733240406e-308F32x" .LASF84: .string "__SIZE_MAX__ 0xffffffffffffffffUL" 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"__DBL_DECIMAL_DIG__ 17" .LASF331: .string "__linux 1" .LASF257: .string "__FLT64X_MAX__ 1.18973149535723176502126385303097021e+4932F64x" .LASF21: .string "__SIZEOF_LONG__ 8" .LASF40: .string "__INTMAX_TYPE__ long int" .LASF191: .string "__LDBL_HAS_DENORM__ 1" .LASF210: .string "__FLT64_MIN_EXP__ (-1021)" .LASF71: .string "__has_include(STR) __has_include__(STR)" .LASF294: .string "__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2" .LASF314: .string "__SIZEOF_FLOAT80__ 16" .LASF285: .string "__REGISTER_PREFIX__ " .LASF15: .string "__ATOMIC_CONSUME 1" .LASF109: .string "__UINT64_MAX__ 0xffffffffffffffffUL" .LASF3: .string "__STDC_UTF_32__ 1" .LASF50: .string "__UINT16_TYPE__ short unsigned int" .LASF255: .string "__FLT64X_MAX_10_EXP__ 4932" .LASF127: .string "__UINT32_C(c) c ## U" .LASF319: .string "__k8 1" .LASF303: .string "__HAVE_SPECULATION_SAFE_VALUE 1" .LASF344: .string "g_my_private_global" .LASF270: .string "__DEC32_SUBNORMAL_MIN__ 0.000001E-95DF" .LASF229: .string "__FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128" .LASF73: .string "__GXX_ABI_VERSION 1013" .LASF28: .string "__CHAR_BIT__ 8" .LASF100: .string "__SIG_ATOMIC_MIN__ (-__SIG_ATOMIC_MAX__ - 1)" .LASF137: .string "__INT_FAST64_WIDTH__ 64" .LASF269: .string "__DEC32_EPSILON__ 1E-6DF" .LASF176: .string "__DBL_HAS_DENORM__ 1" .LASF235: .string "__FLT128_HAS_QUIET_NAN__ 1" .LASF222: .string "__FLT128_MANT_DIG__ 113" .LASF209: .string "__FLT64_DIG__ 15" .LASF179: .string "__LDBL_MANT_DIG__ 64" .LASF299: .string "__GCC_ATOMIC_LONG_LOCK_FREE 2" .LASF172: .string "__DBL_MAX__ ((double)1.79769313486231570814527423731704357e+308L)" .LASF102: .string "__INT8_MAX__ 0x7f" .LASF138: .string "__UINT_FAST8_MAX__ 0xff" .LASF259: .string "__FLT64X_EPSILON__ 1.08420217248550443400745280086994171e-19F64x" .LASF154: .string "__FLT_MIN_10_EXP__ (-37)" .LASF301: .string "__GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1" .LASF256: .string "__FLT64X_DECIMAL_DIG__ 21" .LASF14: .string "__ATOMIC_ACQ_REL 4" .LASF38: .string "__WCHAR_TYPE__ int" .LASF131: .string "__INT_FAST8_WIDTH__ 8" .LASF227: .string "__FLT128_MAX_10_EXP__ 4932" .LASF286: .string "__USER_LABEL_PREFIX__ " .LASF196: .string "__FLT32_MIN_EXP__ (-125)" .LASF59: .string "__UINT_LEAST32_TYPE__ unsigned int" .LASF123: .string "__UINT8_C(c) c" .LASF223: .string "__FLT128_DIG__ 33" .LASF57: .string "__UINT_LEAST8_TYPE__ unsigned char" .LASF48: .string "__INT64_TYPE__ long int" .LASF121: .string "__INT_LEAST64_WIDTH__ 64" .LASF328: .string "__SEG_FS 1" .LASF288: .string "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1" .LASF348: .string "main" .LASF108: .string "__UINT32_MAX__ 0xffffffffU" .LASF304: .string "__GCC_HAVE_DWARF2_CFI_ASM 1" .LASF313: .string "__x86_64__ 1" .LASF110: .string "__INT_LEAST8_MAX__ 0x7f" .LASF274: .string "__DEC64_MIN__ 1E-383DD" .LASF168: .string "__DBL_MIN_10_EXP__ (-307)" .LASF338: .string "__DECIMAL_BID_FORMAT__ 1" .LASF287: .string "__GNUC_STDC_INLINE__ 1" .LASF213: .string "__FLT64_MAX_10_EXP__ 308" .LASF151: .string "__FLT_MANT_DIG__ 24"
stsp/binutils-ia16	1,450	binutils/testsuite/binutils-all/testranges-ia64.s	# Test .debug_info can reference .debug_ranges entries without ordering the # offsets strictly as increasing. .text start: .byte 1 sub: .byte 2 end: .section .debug_ranges,"",@progbits range: range_sub: data4.ua @secrel(sub), @secrel(end) data4.ua 0, 0 /* range terminator / range_cu: data4.ua @secrel(start), @secrel(end) data4.ua 0, 0 / range terminator / .section .debug_info,"",@progbits data4.ua debugE - debugS / Length of Compilation Unit Info / debugS: .short 0x2 / DWARF version number / data4.ua @secrel(abbrev0) / Offset Into Abbrev. Section / .byte 0x4 / Pointer Size (in bytes) / .uleb128 0x1 / (DIE (0xb) DW_TAG_compile_unit) / data4.ua range_cu - range / DW_AT_ranges / .uleb128 0x2 / (DIE (0x6d) DW_TAG_subprogram) / .ascii "A\0" / DW_AT_name / data4.ua range_sub - range / DW_AT_ranges / debugE: .section .debug_abbrev,"",@progbits abbrev0: .uleb128 0x1 / (abbrev code) / .uleb128 0x11 / (TAG: DW_TAG_compile_unit) / .byte 0x0 / DW_children_no / .uleb128 0x55 / (DW_AT_ranges) / .uleb128 0x6 / (DW_FORM_data4) / .byte 0x0 .byte 0x0 .uleb128 0x2 / (abbrev code) / .uleb128 0x2e / (TAG: DW_TAG_subprogram) / .byte 0x0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x55 / (DW_AT_ranges) / .uleb128 0x6 / (DW_FORM_data4) / .byte 0x0 .byte 0x0 .byte 0x0 / abbrevs terminator */
stsp/binutils-ia16	1,642	binutils/testsuite/binutils-all/retain1.s	.global discard0 .section .bss.discard0,"aw" .type discard0, %object discard0: .zero 2 .global discard1 .section .bss.discard1,"aw" .type discard1, %object discard1: .zero 2 .global discard2 .section .data.discard2,"aw" .type discard2, %object discard2: .word 1 .section .bss.sdiscard0,"aw" .type sdiscard0, %object sdiscard0: .zero 2 .section .bss.sdiscard1,"aw" .type sdiscard1, %object sdiscard1: .zero 2 .section .data.sdiscard2,"aw" .type sdiscard2, %object sdiscard2: .word 1 .section .text.fndiscard0,"ax" .global fndiscard0 .type fndiscard0, %function fndiscard0: .word 0 .global retain0 .section .bss.retain0,"awR" .type retain0, %object retain0: .zero 2 .global retain1 .section .bss.retain1,"awR" .type retain1, %object retain1: .zero 2 .global retain2 .section .data.retain2,"awR" .type retain2, %object retain2: .word 1 .section .bss.sretain0,"awR" .type sretain0, %object sretain0: .zero 2 .section .bss.sretain1,"awR" .type sretain1, %object sretain1: .zero 2 .section .data.sretain2,"aRw" .type sretain2, %object sretain2: .word 1 .section .text.fnretain1,"Rax" .global fnretain1 .type fnretain1, %function fnretain1: .word 0 .section .text.fndiscard2,"ax" .global fndiscard2 .type fndiscard2, %function fndiscard2: .word 0 .section .bss.lsretain0,"awR" .type lsretain0.2, %object lsretain0.2: .zero 2 .section .bss.lsretain1,"aRw" .type lsretain1.1, %object lsretain1.1: .zero 2 .section .data.lsretain2,"aRw" .type lsretain2.0, %object lsretain2.0: .word 1 .section .text._start,"ax" .global _start .type _start, %function _start: .word 0
stsp/binutils-ia16	2,867	binutils/testsuite/binutils-all/dwo.s	/* Assembler source used to create an object file for testing readelf's and objdump's ability to process separate dwarf object files. Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / Create a .debug_str section for local use. This is also to check the ability to dump the same section twice, if it exists in both the main file and the separate debug info file. / .section .debug_str,"MS",%progbits,1 string1: .asciz "debugfile.dwo" string2: .asciz "/path/to/dwo/files" string3: .asciz "/another/path/" .balign 2 string_end: / Create a .debug_info section that contains the dwo links. / .section .debug_info,"",%progbits .4byte debugE1 - debugS1 ;# Length of Compilation Unit Info debugS1: .short 0x4 ;# DWARF version number. .4byte 0x0 ;# Offset into .debug_abbrev section. .byte 0x4 ;# Pointer Size (in bytes). .uleb128 0x1 ;# Use abbrev #1. This needs strings from the .debug_str section. .4byte string1 .4byte string2 debugE1: .4byte debugE2 - debugS2 ;# Length of Compilation Unit Info debugS2: .short 0x4 ;# DWARF version number. .4byte 0x0 ;# Offset into .debug_abbrev section. .byte 0x4 ;# Pointer Size (in bytes). .uleb128 0x2 ;# Use abbrev #2. .asciz "file.dwo" .4byte string3 .8byte 0x12345678aabbccdd ;# Minimal section alignment on alpha- is 2, so ensure no new invalid CU ;# will be started. .balign 2, 0 debugE2: .section .debug_abbrev,"",%progbits /* Create an abbrev containing a DWARF5 style dwo link. / .uleb128 0x01 ;# Abbrev code. .uleb128 0x11 ;# DW_TAG_compile_unit .byte 0x00 ;# DW_children_no .uleb128 0x76 ;# DW_AT_dwo_name .uleb128 0x0e ;# DW_FORM_strp .uleb128 0x1b ;# DW_AT_comp_dir .uleb128 0x0e ;# DW_FORM_strp .byte 0x00 ;# End of abbrev .byte 0x00 / Create an abbrev containing a GNU style dwo link. */ .uleb128 0x02 ;# Abbrev code. .uleb128 0x11 ;# DW_TAG_compile_unit .byte 0x00 ;# DW_children_no .uleb128 0x2130 ;# DW_AT_GNU_dwo_name .uleb128 0x08 ;# DW_FORM_string .uleb128 0x1b ;# DW_AT_comp_dir .uleb128 0x0e ;# DW_FORM_strp .uleb128 0x2131 ;# DW_AT_GNU_dwo_id .uleb128 0x07 ;# DW_FORM_data8 .byte 0x00 ;# End of abbrev .byte 0x00 .byte 0x0 ;# Abbrevs terminator
stsp/binutils-ia16	5,276	binutils/testsuite/binutils-all/dw2-1.S	/* This testcase is derived from a similar test in GDB. Copyright (C) 2008-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / Dummy function to provide debug information for. / .text .globl _start _start: .4byte 0 .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .4byte 0 .global func_cu1_end func_cu1_end: .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: / Debug information / .section .debug_info .Lcu1_begin: / CU header / .4byte .Lcu1_end - .Lcu1_start / Length of Compilation Unit / .Lcu1_start: .2byte 2 / DWARF Version / .4byte .Labbrev1_begin / Offset into abbrev section / .byte 4 / Pointer size / / CU die / .uleb128 1 / Abbrev: DW_TAG_compile_unit / .4byte .Lline1_begin / DW_AT_stmt_list / .4byte .Lend_text1 / DW_AT_high_pc / .4byte .Lbegin_text1 / DW_AT_low_pc / .ascii "file1.txt\0" / DW_AT_name / .ascii "GNU C 3.3.3\0" / DW_AT_producer / .byte 1 / DW_AT_language (C) / / func_cu1 / .uleb128 2 / Abbrev: DW_TAG_subprogram / .byte 1 / DW_AT_external / .byte 1 / DW_AT_decl_file / .byte 2 / DW_AT_decl_line / .ascii "func_cu1\0" / DW_AT_name / .4byte .Ltype_int-.Lcu1_begin / DW_AT_type / .4byte .Lbegin_func_cu1 / DW_AT_low_pc / .4byte .Lend_func_cu1 / DW_AT_high_pc / .byte 1 / DW_AT_frame_base: length / .byte 0x55 / DW_AT_frame_base: DW_OP_reg5 / .Ltype_int: .uleb128 3 / Abbrev: DW_TAG_base_type / .ascii "int\0" / DW_AT_name / .byte 4 / DW_AT_byte_size / .byte 5 / DW_AT_encoding / .byte 0 / End of children of CU / .Lcu1_end: / Line table / .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start / Initial length / .Lline1_start: .2byte 2 / Version / .4byte .Lline1_lines - .Lline1_hdr / header_length / .Lline1_hdr: .byte 1 / Minimum insn length / .byte 1 / default_is_stmt / .byte 1 / line_base / .byte 1 / line_range / .byte 0x10 / opcode_base / / Standard lengths / .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 / Include directories / .byte 0 / File names / .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lbegin_func_cu1 .byte 3 / DW_LNS_advance_line / .sleb128 3 / ... to 4 / .byte 1 / DW_LNS_copy / .byte 1 / DW_LNS_copy (second time as an end-of-prologue marker) / .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lend_func_cu1 .byte 0 / DW_LNE_end_of_sequence / .uleb128 1 .byte 1 .Lline1_end: / Abbrev table / .section .debug_abbrev .Labbrev1_begin: .uleb128 1 / Abbrev code / .uleb128 0x11 / DW_TAG_compile_unit / .byte 1 / has_children / .uleb128 0x10 / DW_AT_stmt_list / .uleb128 0x6 / DW_FORM_data4 / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x25 / DW_AT_producer / .uleb128 0x8 / DW_FORM_string / .uleb128 0x13 / DW_AT_language / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 2 / Abbrev code / .uleb128 0x2e / DW_TAG_subprogram / .byte 0 / has_children / .uleb128 0x3f / DW_AT_external / .uleb128 0xc / DW_FORM_flag / .uleb128 0x3a / DW_AT_decl_file / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3b / DW_AT_decl_line / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x40 / DW_AT_frame_base / .uleb128 0xa / DW_FORM_block1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 3 / Abbrev code / .uleb128 0x24 / DW_TAG_base_type / .byte 0 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0xb / DW_AT_byte_size / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3e / DW_AT_encoding / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator */
stsp/binutils-ia16	4,450	binutils/testsuite/binutils-all/dwarf-attributes.S	/* Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / This file is intended to check the encoding and decoding of DWARF attributes. Currently only numeric attributes are tested, but this file should be extended to cover other types of attribute as well. / .file "dwarf-attributes.S" .section .debug_info,"",%progbits .4byte .Ldebug_info_end - .Ldebug_info_start / Length of Compilation Unit Info. / .Ldebug_info_start: .2byte 0x5 / DWARF version number. / .byte 0x1 / DW_UT_compile. / .byte 0x4 / Pointer Size (in bytes). / .4byte .Ldebug_abbrevs / Offset Into Abbrev. Section. / / Start of DIE 0xc. / .uleb128 0x1 / Using abbrev #1 / .byte 1 / Ordering: column major. / .2byte 1 / Language: C89. / .byte 1 / Visibility: local. / .byte 1 / Inline: inlined. / .byte 1 / Accessibility: public. / .byte 1 / Calling convention: normal. / .byte 3,1,1,2 / Discriminate list: range. / .byte 1 / Encoding: address. / .byte 1 / Identifier case: up. / .byte 1 / Virtuality: virtual. / .byte 1 / Decimal sign: unsigned. / .byte 1 / Endianity: big. / .byte 1 / Defaulted: in class. / .uleb128 0x1 / Using abbrev #1 / .byte 0 / Ordering: row major / .2byte 0x0016 / Language: Go. / .byte 2 / Visibility: exported. / .byte 0 / Inline: not. / .byte 2 / Accessibility: protected. / .byte 5 / Calling convention: pass by value. / .byte 2,0,1 / Discriminate list: label. / .byte 0x12 / Encoding: ASCII. / .byte 0 / Identifier case: sensitive. / .byte 0 / Virtuality: none. / .byte 2 / Decimal sign: leading overpunch. / .byte 0 / Endianity: default. / .byte 0 / Defaulted: no. / .uleb128 0x1 / Using abbrev #1 / .byte -1 / Ordering: undefined. / .2byte 0x8001 / Language: MIPS Assembler. / .byte 3 / Visibility: qualified. / .byte 3 / Inline: declared. / .byte 3 / Accessibility: private. / .byte 0x40 / Calling convention: Renesas SH. / .byte 5,1,2,3,0,4 / Discriminate list: range and label. / .byte 0x81 / Encoding: user specified. / .byte 3 / Identifier case: insensitive. / .byte 2 / Virtuality: pure. / .byte 5 / Decimal sign: trailing separate. / .byte 0x50 / Endianity: user specified. / .byte 2 / Defaulted: out of class. / .byte 0 / End of children of DIE 0xc. / .Ldebug_info_end: .section .debug_abbrev,"",%progbits .Ldebug_abbrevs: .uleb128 0x1 / (abbrev code) / .uleb128 0x5555 / (TAG: DW_TAG_lo_user + 0x1555) / .byte 0 / DW_children_no / / Attributes to be tested. Sorted by attribute value. / .uleb128 0x9 / (DW_AT_ordering) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x13 / (DW_AT_language) / .uleb128 0x05 / (DW_FORM_data2) / .uleb128 0x17 / (DW_AT_visibility) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x20 / (DW_AT_inline) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x32 / (DW_AT_accessibility) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x36 / (DW_AT_calling_convention) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x3d / (DW_AT_discr_lists) / .uleb128 0x0a / (DW_FORM_block1) / .uleb128 0x3e / (DW_AT_encoding) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x42 / (DW_AT_identifier_case) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x4c / (DW_AT_virtuality) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x5e / (DW_AT_decimal_sign) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x65 / (DW_AT_endianity) / .uleb128 0x0b / (DW_FORM_data1) / .uleb128 0x8b / (DW_AT_defaulted) / .uleb128 0x0b / (DW_FORM_data1) / .byte 0 / End of abbreviation. / .byte 0 .byte 0 / End of abbreviations. */
stsp/binutils-ia16	1,451	binutils/testsuite/binutils-all/pr25662-pdp11.s	/* PR 25662: objcopy sets invalid sh_offset for the first section in a no_contents segment containing program headers. Several conditions are required for the bug to manifest: - The first loadable segment (which contains the program headers) must only contain SHT_NOBITS sections. .bss is the SHT_NOBITS section in this test. - The next loadable segment must have a !SHT_NOBITS loadable section. .data is the !SHT_NOBITS section in this test. - .bss must be positioned after .data in the executable file itself. - The size of .data must be such that the calculated VMA of the .bss section that follows it is not congruent with the file offset of .bss, modulo the p_align of its segment, i.e.: (VMA(.data) + sizeof(.data)) % (.bss_segment.p_align) != 0 This will force the sh_offset of .bss to be aligned so it appears within .data. - The size of .data must be larger than the program headers in the first loadable segment, so that the file offset of .bss is immediately after .data, and not padded to a valid alignment by the program headers. The bug originally only manifested for ELF targets, but there's no reason not to run this testcase for other file formats. This variant source for pdp11 uses .text rather than .section text, etc., because the latter are not supported, */ .bss a: .zero 0x2 .data c: .zero 0x201 .text .global _start _start: .long 0
stsp/binutils-ia16	21,697	binutils/testsuite/binutils-all/dw5.S	/* Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / .file "main.c" .text .Ltext0: .p2align 4,,15 .globl func .type func, %function func: .LFB0: / main.c:5 / .LM1: / BLOCK 2 freq:10000 seq:0 / / PRED: ENTRY [100.0%] (FALLTHRU) / / main.c:5 / .LM2: .dc.b 0 / SUCC: / .dc.b 0 .LFE0: .size func, .-func .section .text.startup,"ax",%progbits .p2align 4,,15 .globl main .type main, %function main: .LFB1: / main.c:6 / .LM3: .LVL0: / BLOCK 2 freq:10000 seq:0 / / PRED: ENTRY [100.0%] (FALLTHRU) / .dc.b 0 / main.c:6 / .LM4: .dc.b 0 .LVL1: .dc.b 0 .LVL2: .dc.b 0 / SUCC: EXIT [100.0%] / .dc.b 0 .LFE1: .size main, .-main .ifdef HPUX pvar .comm 8 yvar .comm 4 .else .comm pvar,8,8 .comm yvar,4,4 .endif .globl xvar .data .align 4 .type xvar, %object .size xvar, 4 xvar: .4byte 42 .text .Letext0: .section .debug_info,"",%progbits .Ldebug_info0: .4byte 0x160 / Length of Compilation Unit Info / .2byte 0x5 / DWARF version number / .byte 0x1 / DW_UT_compile / .byte 0x8 / Pointer Size (in bytes) / .4byte .Ldebug_abbrev0 / Offset Into Abbrev. Section / .uleb128 0x6 / (DIE (0xc) DW_TAG_compile_unit) / .4byte .LASF21 / DW_AT_producer: "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" / .byte 0x1d / DW_AT_language / .4byte .LASF0 / DW_AT_name: "main.c" / .4byte .LASF1 / DW_AT_comp_dir: "" / .4byte .LLRL2 / DW_AT_ranges / .8byte 0 / DW_AT_low_pc / .4byte .Ldebug_line0 / DW_AT_stmt_list / .uleb128 0x1 / (DIE (0x2a) DW_TAG_base_type) / .byte 0x1 / DW_AT_byte_size / .byte 0x8 / DW_AT_encoding / .4byte .LASF2 / DW_AT_name: "unsigned char" / .uleb128 0x1 / (DIE (0x31) DW_TAG_base_type) / .byte 0x2 / DW_AT_byte_size / .byte 0x7 / DW_AT_encoding / .4byte .LASF3 / DW_AT_name: "short unsigned int" / .uleb128 0x1 / (DIE (0x38) DW_TAG_base_type) / .byte 0x4 / DW_AT_byte_size / .byte 0x7 / DW_AT_encoding / .4byte .LASF4 / DW_AT_name: "unsigned int" / .uleb128 0x1 / (DIE (0x3f) DW_TAG_base_type) / .byte 0x8 / DW_AT_byte_size / .byte 0x7 / DW_AT_encoding / .4byte .LASF5 / DW_AT_name: "long unsigned int" / .uleb128 0x1 / (DIE (0x46) DW_TAG_base_type) / .byte 0x1 / DW_AT_byte_size / .byte 0x6 / DW_AT_encoding / .4byte .LASF6 / DW_AT_name: "signed char" / .uleb128 0x1 / (DIE (0x4d) DW_TAG_base_type) / .byte 0x2 / DW_AT_byte_size / .byte 0x5 / DW_AT_encoding / .4byte .LASF7 / DW_AT_name: "short int" / .uleb128 0x7 / (DIE (0x54) DW_TAG_base_type) / .byte 0x4 / DW_AT_byte_size / .byte 0x5 / DW_AT_encoding / .ascii "int\0" / DW_AT_name / .uleb128 0x1 / (DIE (0x5b) DW_TAG_base_type) / .byte 0x8 / DW_AT_byte_size / .byte 0x5 / DW_AT_encoding / .4byte .LASF8 / DW_AT_name: "long int" / .uleb128 0x1 / (DIE (0x62) DW_TAG_base_type) / .byte 0x8 / DW_AT_byte_size / .byte 0x7 / DW_AT_encoding / .4byte .LASF9 / DW_AT_name: "sizetype" / .uleb128 0x3 / (DIE (0x69) DW_TAG_pointer_type) / / DW_AT_byte_size (0x8) / .4byte 0x6e / DW_AT_type / .uleb128 0x1 / (DIE (0x6e) DW_TAG_base_type) / .byte 0x1 / DW_AT_byte_size / .byte 0x6 / DW_AT_encoding / .4byte .LASF10 / DW_AT_name: "char" / .uleb128 0x8 / (DIE (0x75) DW_TAG_variable) / .4byte .LASF11 / DW_AT_name: "__environ" / .byte 0x2 / DW_AT_decl_file (/usr/include/unistd.h) / .2byte 0x222 / DW_AT_decl_line / .4byte 0x81 / DW_AT_type / / DW_AT_external / / DW_AT_declaration / .uleb128 0x3 / (DIE (0x81) DW_TAG_pointer_type) / / DW_AT_byte_size (0x8) / .4byte 0x69 / DW_AT_type / .uleb128 0x2 / (DIE (0x86) DW_TAG_variable) / .4byte .LASF12 / DW_AT_name: "optarg" / / DW_AT_decl_file (3, /usr/include/getopt.h) / .byte 0x39 / DW_AT_decl_line / .4byte 0x69 / DW_AT_type / / DW_AT_external / / DW_AT_declaration / .uleb128 0x2 / (DIE (0x90) DW_TAG_variable) / .4byte .LASF13 / DW_AT_name: "optind" / / DW_AT_decl_file (3, /usr/include/getopt.h) / .byte 0x47 / DW_AT_decl_line / .4byte 0x54 / DW_AT_type / / DW_AT_external / / DW_AT_declaration / .uleb128 0x2 / (DIE (0x9a) DW_TAG_variable) / .4byte .LASF14 / DW_AT_name: "opterr" / / DW_AT_decl_file (3, /usr/include/getopt.h) / .byte 0x4c / DW_AT_decl_line / .4byte 0x54 / DW_AT_type / / DW_AT_external / / DW_AT_declaration / .uleb128 0x2 / (DIE (0xa4) DW_TAG_variable) / .4byte .LASF15 / DW_AT_name: "optopt" / / DW_AT_decl_file (3, /usr/include/getopt.h) / .byte 0x50 / DW_AT_decl_line / .4byte 0x54 / DW_AT_type / / DW_AT_external / / DW_AT_declaration / .uleb128 0x4 / (DIE (0xae) DW_TAG_variable) / .4byte .LASF16 / DW_AT_name: "xvar" / / DW_AT_decl_file (1, main.c) / .byte 0x2 / DW_AT_decl_line / .4byte 0x54 / DW_AT_type / / DW_AT_external / .uleb128 0x9 / DW_AT_location / .byte 0x3 / DW_OP_addr / .8byte 0x1234 .uleb128 0x4 / (DIE (0xc2) DW_TAG_variable) / .4byte .LASF17 / DW_AT_name: "yvar" / / DW_AT_decl_file (1, main.c) / .byte 0x3 / DW_AT_decl_line / .4byte 0x54 / DW_AT_type / / DW_AT_external / .uleb128 0x9 / DW_AT_location / .byte 0x3 / DW_OP_addr / .8byte 0x1234 .uleb128 0x4 / (DIE (0xd6) DW_TAG_variable) / .4byte .LASF18 / DW_AT_name: "pvar" / / DW_AT_decl_file (1, main.c) / .byte 0x4 / DW_AT_decl_line / .4byte 0xea / DW_AT_type / / DW_AT_external / .uleb128 0x9 / DW_AT_location / .byte 0x3 / DW_OP_addr / .8byte 0x1234 .uleb128 0x3 / (DIE (0xea) DW_TAG_pointer_type) / / DW_AT_byte_size (0x8) / .4byte 0x54 / DW_AT_type / .uleb128 0x9 / (DIE (0xef) DW_TAG_subprogram) / / DW_AT_external / .4byte .LASF22 / DW_AT_name: "main" / .byte 0x1 / DW_AT_decl_file (main.c) / .byte 0x6 / DW_AT_decl_line / / DW_AT_prototyped / .4byte 0x54 / DW_AT_type / .8byte 0x1234 / DW_AT_low_pc / .8byte 0x5678 / DW_AT_high_pc / .uleb128 0x1 / DW_AT_frame_base / .byte 0x9c / DW_OP_call_frame_cfa / / DW_AT_call_all_calls / .4byte 0x13e / DW_AT_sibling / .uleb128 0x5 / (DIE (0x110) DW_TAG_formal_parameter) / .4byte .LASF19 / DW_AT_name: "argc" / / DW_AT_decl_file (1, main.c) / / DW_AT_decl_line (0x6) / .4byte 0x54 / DW_AT_type / .4byte .LLST0 / DW_AT_location / .uleb128 0x5 / (DIE (0x11d) DW_TAG_formal_parameter) / .4byte .LASF20 / DW_AT_name: "argv" / / DW_AT_decl_file (1, main.c) / / DW_AT_decl_line (0x6) / .4byte 0x81 / DW_AT_type / .4byte .LLST1 / DW_AT_location / .uleb128 0xa / (DIE (0x12a) DW_TAG_call_site) / .8byte 0x12345 / DW_AT_call_return_pc / .4byte 0x157 / DW_AT_call_origin / .uleb128 0xb / (DIE (0x137) DW_TAG_call_site_parameter) / .uleb128 0x1 / DW_AT_location / .byte 0x55 / DW_OP_reg5 / .uleb128 0x1 / DW_AT_call_value / .byte 0x30 / DW_OP_lit0 / .byte 0 / end of children of DIE 0x12a / .byte 0 / end of children of DIE 0xef / .uleb128 0xc / (DIE (0x13e) DW_TAG_subprogram) / / DW_AT_external / .4byte .LASF23 / DW_AT_name: "func" / .byte 0x1 / DW_AT_decl_file (main.c) / .byte 0x5 / DW_AT_decl_line / / DW_AT_prototyped / .8byte 0x1234 / DW_AT_low_pc / .8byte 0x5678 / DW_AT_high_pc / .uleb128 0x1 / DW_AT_frame_base / .byte 0x9c / DW_OP_call_frame_cfa / / DW_AT_call_all_calls / .uleb128 0xd / (DIE (0x157) DW_TAG_subprogram) / / DW_AT_external / / DW_AT_declaration / .4byte .LASF24 / DW_AT_linkage_name: "alarm" / .4byte .LASF24 / DW_AT_name: "alarm" / .byte 0x2 / DW_AT_decl_file (/usr/include/unistd.h) / .2byte 0x1b3 / DW_AT_decl_line / .byte 0 / end of children of DIE 0xc / .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 / (abbrev code) / .uleb128 0x24 / (TAG: DW_TAG_base_type) / .byte 0 / DW_children_no / .uleb128 0xb / (DW_AT_byte_size) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3e / (DW_AT_encoding) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .byte 0 .byte 0 .uleb128 0x2 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 3 / (/usr/include/getopt.h) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x3c / (DW_AT_declaration) / .uleb128 0x19 / (DW_FORM_flag_present) / .byte 0 .byte 0 .uleb128 0x3 / (abbrev code) / .uleb128 0xf / (TAG: DW_TAG_pointer_type) / .byte 0 / DW_children_no / .uleb128 0xb / (DW_AT_byte_size) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 8 .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .byte 0 .byte 0 .uleb128 0x4 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 1 / (main.c) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x18 / (DW_FORM_exprloc) / .byte 0 .byte 0 .uleb128 0x5 / (abbrev code) / .uleb128 0x5 / (TAG: DW_TAG_formal_parameter) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 1 / (main.c) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 6 .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .uleb128 0x6 / (abbrev code) / .uleb128 0x11 / (TAG: DW_TAG_compile_unit) / .byte 0x1 / DW_children_yes / .uleb128 0x25 / (DW_AT_producer) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x13 / (DW_AT_language) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x1f / (DW_FORM_line_strp) / .uleb128 0x1b / (DW_AT_comp_dir) / .uleb128 0x1f / (DW_FORM_line_strp) / .uleb128 0x55 / (DW_AT_ranges) / .uleb128 0x17 / (DW_FORM_sec_offset) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x10 / (DW_AT_stmt_list) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .uleb128 0x7 / (abbrev code) / .uleb128 0x24 / (TAG: DW_TAG_base_type) / .byte 0 / DW_children_no / .uleb128 0xb / (DW_AT_byte_size) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3e / (DW_AT_encoding) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .byte 0 .byte 0 .uleb128 0x8 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0x5 / (DW_FORM_data2) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x3c / (DW_AT_declaration) / .uleb128 0x19 / (DW_FORM_flag_present) / .byte 0 .byte 0 .uleb128 0x9 / (abbrev code) / .uleb128 0x2e / (TAG: DW_TAG_subprogram) / .byte 0x1 / DW_children_yes / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x27 / (DW_AT_prototyped) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x12 / (DW_AT_high_pc) / .uleb128 0x7 / (DW_FORM_data8) / .uleb128 0x40 / (DW_AT_frame_base) / .uleb128 0x18 / (DW_FORM_exprloc) / .uleb128 0x7a / (DW_AT_call_all_calls) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x1 / (DW_AT_sibling) / .uleb128 0x13 / (DW_FORM_ref4) / .byte 0 .byte 0 .uleb128 0xa / (abbrev code) / .uleb128 0x48 / (TAG: DW_TAG_call_site) / .byte 0x1 / DW_children_yes / .uleb128 0x7d / (DW_AT_call_return_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x7f / (DW_AT_call_origin) / .uleb128 0x13 / (DW_FORM_ref4) / .byte 0 .byte 0 .uleb128 0xb / (abbrev code) / .uleb128 0x49 / (TAG: DW_TAG_call_site_parameter) / .byte 0 / DW_children_no / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x18 / (DW_FORM_exprloc) / .uleb128 0x7e / (DW_AT_call_value) / .uleb128 0x18 / (DW_FORM_exprloc) / .byte 0 .byte 0 .uleb128 0xc / (abbrev code) / .uleb128 0x2e / (TAG: DW_TAG_subprogram) / .byte 0 / DW_children_no / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x27 / (DW_AT_prototyped) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x12 / (DW_AT_high_pc) / .uleb128 0x7 / (DW_FORM_data8) / .uleb128 0x40 / (DW_AT_frame_base) / .uleb128 0x18 / (DW_FORM_exprloc) / .uleb128 0x7a / (DW_AT_call_all_calls) / .uleb128 0x19 / (DW_FORM_flag_present) / .byte 0 .byte 0 .uleb128 0xd / (abbrev code) / .uleb128 0x2e / (TAG: DW_TAG_subprogram) / .byte 0 / DW_children_no / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x3c / (DW_AT_declaration) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x6e / (DW_AT_linkage_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0x5 / (DW_FORM_data2) / .byte 0 .byte 0 .byte 0 .section .debug_loclists,"",%progbits .4byte .Ldebug_loc2-.Ldebug_loc1 / Length of Location Lists / .Ldebug_loc1: .2byte 0x5 / DWARF Version / .byte 0x8 / Address Size / .byte 0 / Segment Size / .4byte 0 / Offset Entry Count / .Ldebug_loc0: .LLST0: .byte 0x6 / DW_LLE_base_address (.LLST0) / .8byte 0x1234 /* Base address (.LLST0) / .byte 0x4 /* DW_LLE_offset_pair (.LLST0) / .uleb128 .LVL0-.LVL0 /* Location list begin address (.LLST0) / .uleb128 .LVL1-.LVL0 /* Location list end address (.LLST0) / .uleb128 0x1 /* Location expression size / .byte 0x55 / DW_OP_reg5 / .byte 0x4 / DW_LLE_offset_pair (.LLST0) / .uleb128 .LVL1-.LVL0 /* Location list begin address (.LLST0) / .uleb128 .LFE1-.LVL0 /* Location list end address (.LLST0) / .uleb128 0x4 /* Location expression size / .byte 0xa3 / DW_OP_entry_value / .uleb128 0x1 .byte 0x55 / DW_OP_reg5 / .byte 0x9f / DW_OP_stack_value / .byte 0 / DW_LLE_end_of_list (.LLST0) / .LLST1: .byte 0x6 /* DW_LLE_base_address (.LLST1) / .8byte 0x1234 /* Base address (.LLST1) / .byte 0x4 /* DW_LLE_offset_pair (.LLST1) / .uleb128 .LVL0-.LVL0 /* Location list begin address (.LLST1) / .uleb128 .LVL2-1-.LVL0 /* Location list end address (.LLST1) / .uleb128 0x1 /* Location expression size / .byte 0x54 / DW_OP_reg4 / .byte 0x4 / DW_LLE_offset_pair (.LLST1) / .uleb128 .LVL2-1-.LVL0 /* Location list begin address (.LLST1) / .uleb128 .LFE1-.LVL0 /* Location list end address (.LLST1) / .uleb128 0x4 /* Location expression size / .byte 0xa3 / DW_OP_entry_value / .uleb128 0x1 .byte 0x54 / DW_OP_reg4 / .byte 0x9f / DW_OP_stack_value / .byte 0 / DW_LLE_end_of_list (.LLST1) / .Ldebug_loc2: .section .debug_aranges,"",%progbits .4byte 0x3c /* Length of Address Ranges Info / .2byte 0x2 / DWARF Version / .4byte .Ldebug_info0 / Offset of Compilation Unit Info / .byte 0x8 / Size of Address / .byte 0 / Size of Segment Descriptor / .2byte 0 / Pad to 16 byte boundary / .2byte 0 .8byte 0x1234 / Address / .8byte 0x4567 / Length / .8byte 0x1234 / Address / .8byte 0x5678 / Length / .8byte 0 .8byte 0 .section .debug_rnglists,"",%progbits .Ldebug_ranges0: .4byte .Ldebug_ranges3-.Ldebug_ranges2 / Length of Range Lists / .Ldebug_ranges2: .2byte 0x5 / DWARF Version / .byte 0x8 / Address Size / .byte 0 / Segment Size / .4byte 0 / Offset Entry Count / .LLRL2: .byte 0x7 / DW_RLE_start_length (.LLRL2) / .8byte 0x1234 /* Range begin address (.LLRL2) / .uleb128 .Letext0-.Ltext0 /* Range length (.LLRL2) / .byte 0x7 /* DW_RLE_start_length (.LLRL2) / .8byte 0x1234 /* Range begin address (.LLRL2) / .uleb128 .LFE1-.LFB1 /* Range length (.LLRL2) / .byte 0 /* DW_RLE_end_of_list (.LLRL2) / .Ldebug_ranges3: .section .debug_line,"",%progbits .Ldebug_line0: .4byte .LELT0-.LSLT0 /* Length of Source Line Info / .LSLT0: .2byte 0x5 / DWARF Version / .byte 0x8 / Address Size / .byte 0 / Segment Size / .4byte .LELTP0-.LASLTP0 / Prolog Length / .LASLTP0: .byte 0x1 / Minimum Instruction Length / .byte 0x1 / Maximum Operations Per Instruction / .byte 0x1 / Default is_stmt_start flag / .byte 0xf6 / Line Base Value (Special Opcodes) / .byte 0xf2 / Line Range Value (Special Opcodes) / .byte 0xd / Special Opcode Base / .byte 0 / opcode: 0x1 has 0 args / .byte 0x1 / opcode: 0x2 has 1 arg / .byte 0x1 / opcode: 0x3 has 1 arg / .byte 0x1 / opcode: 0x4 has 1 arg / .byte 0x1 / opcode: 0x5 has 1 arg / .byte 0 / opcode: 0x6 has 0 args / .byte 0 / opcode: 0x7 has 0 args / .byte 0 / opcode: 0x8 has 0 args / .byte 0x1 / opcode: 0x9 has 1 arg / .byte 0 / opcode: 0xa has 0 args / .byte 0 / opcode: 0xb has 0 args / .byte 0x1 / opcode: 0xc has 1 arg / .byte 0x1 / Directory entry format count / .uleb128 0x1 / DW_LNCT_path / .uleb128 0x1f / DW_FORM_line_strp / .uleb128 0x3 / Directories count / .4byte .LASF1 / Directory Entry: 0: "" / .4byte .LASF25 / Directory Entry: 0: "" / .4byte .LASF26 / Directory Entry: 0: "/usr/include" / .byte 0x2 / File name entry format count / .uleb128 0x1 / DW_LNCT_path / .uleb128 0x1f / DW_FORM_line_strp / .uleb128 0x2 / DW_LNCT_directory_index / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x4 / File names count / .4byte .LASF0 / File Entry: 0: "main.c" / .byte 0 .4byte .LASF27 / File Entry: 0: "main.c" / .byte 0x1 .4byte .LASF28 / File Entry: 0: "unistd.h" / .byte 0x2 .4byte .LASF29 / File Entry: 0: "getopt.h" / .byte 0x2 .LELTP0: .byte 0 / set address .LM3 / .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0x1c /* line 6 / .byte 0 / set address .LM4 / .uleb128 0x9 .byte 0x2 .8byte 0x12346 .byte 0x1 /* copy line 6 / .byte 0 / set address .LFE1 / .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0 /* end sequence / .uleb128 0x1 .byte 0x1 .byte 0 / set address .LM1 / .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0x1b /* line 5 / .byte 0 / set address .LM2 / .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0x1 /* copy line 5 / .byte 0 / set address .Letext0 / .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0 /* end sequence */ .uleb128 0x1 .byte 0x1 .LELT0: .section .debug_str,"MS",%progbits,1 .LASF4: .asciz "unsigned int" .LASF15: .asciz "optopt" .LASF22: .asciz "main" .LASF6: .asciz "signed char" .LASF16: .asciz "xvar" .LASF5: .asciz "long unsigned int" .LASF14: .asciz "opterr" .LASF21: .asciz "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" .LASF2: .asciz "unsigned char" .LASF10: .asciz "char" .LASF13: .asciz "optind" .LASF8: .asciz "long int" .LASF19: .asciz "argc" .LASF3: .asciz "short unsigned int" .LASF17: .asciz "yvar" .LASF18: .asciz "pvar" .LASF11: .asciz "__environ" .LASF23: .asciz "func" .LASF12: .asciz "optarg" .LASF7: .asciz "short int" .LASF24: .asciz "alarm" .LASF9: .asciz "sizetype" .LASF20: .asciz "argv" .section .debug_line_str,"MS",%progbits,1 .LASF1: .asciz "" .LASF25: .asciz "" .LASF29: .asciz "getopt.h" .LASF28: .asciz "unistd.h" .LASF0: .asciz "main.c" .LASF27: .asciz "main.c" .LASF26: .asciz "/usr/include" .ident "GCC: (GNU) 7.0.1 20170218 (experimental)" .section .note.GNU-stack,"",%progbits
stsp/binutils-ia16	5,436	binutils/testsuite/binutils-all/dw5-op.S	/* Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / .file "main.c" .text .Letext0: .section .debug_info,"",%progbits .Ldebug_info0: .4byte 0x4e / Length of Compilation Unit Info / .2byte 0x5 / DWARF version number / .byte 0x1 / DW_UT_compile / .byte 0x8 / Pointer Size (in bytes) / .4byte .Ldebug_abbrev0 / Offset Into Abbrev. Section / .uleb128 0x3 / (DIE (0xc) DW_TAG_compile_unit) / .4byte .LASF21 / DW_AT_producer: "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" / .byte 0x1d / DW_AT_language / .4byte .LASF0 / DW_AT_name: "main.c" / .4byte .LASF1 / DW_AT_comp_dir: "" / .4byte .LLRL2 / DW_AT_ranges / .8byte 0 / DW_AT_low_pc / .4byte .Ldebug_line0 / DW_AT_stmt_list / .uleb128 0x1 / (DIE (0x2a) DW_TAG_base_type) / .byte 0x4 / DW_AT_byte_size / .byte 0x5 / DW_AT_encoding / .4byte .LASF2 / DW_AT_name: "short int" / .uleb128 0x2 / (DIE (0x31) DW_TAG_variable) / .4byte .LASF16 / DW_AT_name: "xvar" / / DW_AT_decl_file (1, main.c) / .byte 0x2 / DW_AT_decl_line / .4byte 0x2a / DW_AT_type / / DW_AT_external / .uleb128 0x9 / DW_AT_location / .byte 0x3 / DW_OP_addr / .8byte 0x1234 .uleb128 0x2 / (DIE (0x45) DW_TAG_variable) / .4byte .LASF17 / DW_AT_name: "yvar" / / DW_AT_decl_file (1, main.c) / .byte 0x3 / DW_AT_decl_line / .4byte 0x2a / DW_AT_type / / DW_AT_external / .uleb128 0x2 / DW_AT_location / .byte 0xa1 / DW_OP_addrx / .byte 0x0 .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 / (abbrev code) / .uleb128 0x24 / (TAG: DW_TAG_base_type) / .byte 0 / DW_children_no / .uleb128 0xb / (DW_AT_byte_size) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3e / (DW_AT_encoding) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .byte 0 .byte 0 .uleb128 0x2 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 1 / (main.c) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x3f / (DW_AT_external) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x18 / (DW_FORM_exprloc) / .byte 0 .byte 0 .uleb128 0x3 / (abbrev code) / .uleb128 0x11 / (TAG: DW_TAG_compile_unit) / .byte 0x1 / DW_children_yes / .uleb128 0x25 / (DW_AT_producer) / .uleb128 0xe / (DW_FORM_strp) / .uleb128 0x13 / (DW_AT_language) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x1f / (DW_FORM_line_strp) / .uleb128 0x1b / (DW_AT_comp_dir) / .uleb128 0x1f / (DW_FORM_line_strp) / .uleb128 0x55 / (DW_AT_ranges) / .uleb128 0x17 / (DW_FORM_sec_offset) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x10 / (DW_AT_stmt_list) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .byte 0 .section .debug_line,"",%progbits .Ldebug_line0: .4byte .LELT0-.LSLT0 / Length of Source Line Info / .LSLT0: .2byte 0x5 / DWARF Version / .byte 0x8 / Address Size / .byte 0 / Segment Size / .4byte .LASF0 / File Entry: 0: "main.c" */ .byte 0 .LELT0: .section .debug_str,"MS",%progbits,1 .LASF22: .asciz "main" .LASF16: .asciz "xvar" .LASF21: .asciz "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" .LASF17: .asciz "yvar" .LASF7: .asciz "short int" .section .debug_line_str,"MS",%progbits,1 .LASF1: .asciz "" .LASF25: .asciz "" .LASF0: .asciz "main.c"
stsp/binutils-ia16	2,212	binutils/testsuite/binutils-all/linkdebug.s	/* Assembler source used to create an object file for testing readelf's and objdump's ability to process separate debug information files. Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / This is the separate debug info file. / / Create .note.gnu.build-id note for use by the .gnu_debugaltlink in the main object file. / .section .note.gnu.build-id,"a",%note .balign 4 .dc.l 0x04 ;# Name size .dc.l 0x18 ;# Description size .dc.l 0x03 ;# Type .asciz "GNU" ;# Name .dc.b 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 .dc.b 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff .dc.b 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef / Create a .debug_abbrev section for use by the .debug_info section in the main object file. / .section .debug_abbrev,"",%progbits abbrevs: .uleb128 0x01 ;# Abbrev code. .uleb128 0x11 ;# DW_TAG_compile_unit .byte 0x00 ;# DW_children_no .uleb128 0x03 ;# DW_AT_name .uleb128 0x0e ;# DW_FORM_strp .byte 0x00 ;# End of abbrev .byte 0x00 .uleb128 0x02 ;# Abbrev code. .uleb128 0x2e ;# DW_TAG_subprogram .byte 0x00 ;# DW_children_no .uleb128 0x03 ;# DW_AT_name .uleb128 0x1f21 ;# DW_FORM_GNU_strp_alt .byte 0x0 ;# End of abbrev .byte 0x0 .byte 0x0 ;# Abbrevs terminator / Create a .debug_str section for remote use. This is also to check the ability to dump the same section twice, if it exists in both the main file and the separate debug info file. */ .section .debug_str,"MS",%progbits,1 string3: .asciz "string-3" .asciz "string-4" .balign 2 string_end:
stsp/binutils-ia16	1,086	binutils/testsuite/binutils-all/readelf.s	There are .* section headers, starting at offset .: Section Headers: +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 # On the normal MIPS systems, sections must be aligned to 16 byte # boundaries. On IA64, text sections are aligned to 16 byte boundaries. +\[ 1\] . +PROGBITS +00000000 0000(34\|38\|40) 0000(08\|10) 00 +AX +0 +0 +(.\|..) +\[ 2\] .rel.* +REL. +0+ 0+.* 0000.. 0. +I +.+ +1 +4 # MIPS targets put .rela.text here. #... +\[ .\] .* +PROGBITS +00000000 0000(3c\|40\|44\|48\|50) 0000(04\|10) 00 +WA +0 +0 +(.\|..) +\[ .\] .* +NOBITS +00000000 0000(40\|44\|48\|4c\|60) 000000 00 +WA +0 +0 +(.\|..) # ARM targets put .ARM.attributes here. # MIPS targets put .reginfo, .mdebug, .MIPS.abiflags and .gnu.attributes here. # v850 targets put .call_table_data and .call_table_text here. # riscv targets put .riscv.attributes here. #... +\[..\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +.+ +4 +\[..\] .strtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +1 +\[..\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +. Key to Flags: #...
stsp/binutils-ia16	11,323	binutils/testsuite/binutils-all/locview-2.s	.text .Ltext0: .LFB0: /* locview.c:1 / .LM1: / view -0 / / locview.c:2 / .LM2: / view 1 / .LVL0: / DEBUG i => 0 / / locview.c:3 / .LM3: / view 2 / / DEBUG j => 0x1 / / locview.c:4 / .LM4: / view 3 / / DEBUG i => 0x2 / / locview.c:5 / .LM5: / view 4 / / DEBUG j => 0x3 / / locview.c:6 / .LM6: / view 5 / / DEBUG k => 0x4 / / DEBUG l => 0x4 / / locview.c:7 / .LM7: / view 6 / / DEBUG k => 0x5 / / DEBUG l => 0x5 / / locview.c:8 / .LM8: / view 7 / / DEBUG k => 0x6 / / DEBUG l => 0x6 / / locview.c:9 / .LM9: / view 8 / .byte 0 .LFE0: .Letext0: .section .debug_info .Ldebug_info0: .LIbase: .4byte .LIend - .LIstart / Length of Compilation Unit Info / .LIstart: .2byte 0x5 / DWARF version number / .byte 0x1 / DW_UT_compile / .byte 0x4 / Pointer Size (in bytes) / .4byte .Ldebug_abbrev0 / Offset Into Abbrev. Section / .LIcu: .uleb128 0x2 / (DIE (cu) DW_TAG_compile_unit) / .ascii "hand-crafted based on GCC output\0" .byte 0x1d / DW_AT_language / .ascii "locview.c\0" .ascii "/tmp\0" .4byte 0 / DW_AT_low_pc / .LIsubf: .uleb128 0x3 / (DIE (subf) DW_TAG_subprogram) / .ascii "f\0" / DW_AT_name / .byte 0x1 / DW_AT_decl_file (locview.c) / .byte 0x1 / DW_AT_decl_line / .4byte .LIint-.LIbase / DW_AT_type / .4byte .LFB0 / DW_AT_low_pc / .4byte 1 / .LFE0-.LFB0 / / DW_AT_high_pc / .uleb128 0x1 / DW_AT_frame_base / .byte 0x9c / DW_OP_call_frame_cfa / / DW_AT_call_all_calls / .4byte .LIint - .LIbase / DW_AT_sibling / .LIvari: .uleb128 0x1 / (DIE (vari) DW_TAG_variable) / .ascii "i\0" / DW_AT_name / / DW_AT_decl_file (1, locview.c) / .byte 0x2 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LLST0 / DW_AT_location / .4byte .LVUS0 / DW_AT_GNU_locviews / .LIvarj: .uleb128 0x1 / (DIE (varj) DW_TAG_variable) / .ascii "j\0" / DW_AT_name / / DW_AT_decl_file (1, locview.c) / .byte 0x3 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LLST1 / DW_AT_location / .4byte .LVUS1 / DW_AT_GNU_locviews / .LIvark: .uleb128 0x5 / (DIE (vark) DW_TAG_variable) / .ascii "k\0" / DW_AT_name / / DW_AT_decl_file (1, locview.c) / .byte 0x6 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LVUS2 / DW_AT_GNU_locviews / .4byte .LLST2 / DW_AT_location / .LIvarl: .uleb128 0x6 / (DIE (varl) DW_TAG_variable) / .ascii "l\0" / DW_AT_name / / DW_AT_decl_file (1, locview.c) / .byte 0x6 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LLST3 / DW_AT_location / .byte 0 / end of children of DIE subf / .LIint: .uleb128 0x4 / (DIE (int) DW_TAG_base_type) / .byte 0x4 / DW_AT_byte_size / .byte 0x5 / DW_AT_encoding / .ascii "int\0" / DW_AT_name / .byte 0 / end of children of DIE cu / .LIend: .section .debug_abbrev .Ldebug_abbrev0: .LAbrv1: .uleb128 0x1 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 1 / (locview.c) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x17 / (DW_FORM_sec_offset) / .uleb128 0x2137 / (DW_AT_GNU_locviews) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .LAbrv2: .uleb128 0x2 / (abbrev code) / .uleb128 0x11 / (TAG: DW_TAG_compile_unit) / .byte 0x1 / DW_children_yes / .uleb128 0x25 / (DW_AT_producer) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x13 / (DW_AT_language) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x1b / (DW_AT_comp_dir) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .byte 0 .byte 0 .LAbrv3: .uleb128 0x3 / (abbrev code) / .uleb128 0x2e / (TAG: DW_TAG_subprogram) / .byte 0x1 / DW_children_yes / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x12 / (DW_AT_high_pc) / .uleb128 0x6 / (DW_FORM_data4) / .uleb128 0x40 / (DW_AT_frame_base) / .uleb128 0x18 / (DW_FORM_exprloc) / .uleb128 0x7a / (DW_AT_call_all_calls) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x1 / (DW_AT_sibling) / .uleb128 0x13 / (DW_FORM_ref4) / .byte 0 .byte 0 .LAbrv4: .uleb128 0x4 / (abbrev code) / .uleb128 0x24 / (TAG: DW_TAG_base_type) / .byte 0 / DW_children_no / .uleb128 0xb / (DW_AT_byte_size) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3e / (DW_AT_encoding) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .byte 0 .byte 0 .LAbrv5: .uleb128 0x5 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 1 / (locview.c) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x2137 / (DW_AT_GNU_locviews) / .uleb128 0x17 / (DW_FORM_sec_offset) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .LAbrv6: .uleb128 0x6 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0x21 / (DW_FORM_implicit_const) / .sleb128 1 / (locview.c) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .byte 0 .section .debug_loclists .4byte .Ldebug_loc2-.Ldebug_loc1 / Length of Location Lists / .Ldebug_loc1: .2byte 0x5 / DWARF version number / .byte 0x4 / Address Size / .byte 0 / Segment Size / .4byte 0 / Offset Entry Count / .Ldebug_loc0: .LVUS0: .uleb128 0x2 / View list begin (.LVUS0) / .uleb128 0x4 /* View list end (.LVUS0) / .uleb128 0x4 /* View list begin (.LVUS0) / .uleb128 0 /* View list end (.LVUS0) / .LLST0: .byte 0x6 /* DW_LLE_base_address (.LLST0) / .4byte .LVL0 /* Base address (.LLST0) / .byte 0x4 /* DW_LLE_offset_pair (.LLST0) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST0) / .uleb128 0 /* .LVL0-.LVL0 / / Location list end address (.LLST0) / .uleb128 0x2 /* Location expression size / .byte 0x30 / DW_OP_lit0 / .byte 0x9f / DW_OP_stack_value / .byte 0x4 / DW_LLE_offset_pair (.LLST0) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST0) / .uleb128 1 /* .LFE0-.LVL0 / / Location list end address (.LLST0) / .uleb128 0x2 /* Location expression size / .byte 0x32 / DW_OP_lit2 / .byte 0x9f / DW_OP_stack_value / .byte 0 / DW_LLE_end_of_list (.LLST0) / .LLST1: .byte 0x6 /* DW_LLE_base_address (.LLST1) / .4byte .LVL0 /* Base address (.LLST1) / .byte 0x4 /* DW_LLE_offset_pair (.LLST1) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST1) / .uleb128 0 /* .LVL0-.LVL0 / / Location list end address (.LLST1) / .uleb128 0x2 /* Location expression size / .byte 0x31 / DW_OP_lit1 / .byte 0x9f / DW_OP_stack_value / .byte 0x4 / DW_LLE_offset_pair (.LLST1) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST1) / .uleb128 1 /* .LFE0-.LVL0 / / Location list end address (.LLST1) / .uleb128 0x2 /* Location expression size / .byte 0x33 / DW_OP_lit3 / .byte 0x9f / DW_OP_stack_value / .byte 0 / DW_LLE_end_of_list (.LLST1) / .LVUS1: .uleb128 0x3 /* View list begin (.LVUS1) / .uleb128 0x5 /* View list end (.LVUS1) / .uleb128 0x5 /* View list begin (.LVUS1) / .uleb128 0 /* View list end (.LVUS1) / .LVUS2: .uleb128 0x6 /* View list begin (.LVUS2) / .uleb128 0x7 /* View list end (.LVUS2) / .uleb128 0x7 /* View list begin (.LVUS2) / .uleb128 0x8 /* View list end (.LVUS2) / .uleb128 0x8 /* View list begin (.LVUS2) / .uleb128 0 /* View list end (.LVUS2) / .LLST2: .byte 0x6 /* DW_LLE_base_address (.LLST2) / .4byte .LVL0 /* Base address (.LLST2) / .byte 0x4 /* DW_LLE_offset_pair (.LLST2) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST2) / .uleb128 0 /* .LVL0-.LVL0 / / Location list end address (.LLST2) / .uleb128 0x2 /* Location expression size / .byte 0x34 / DW_OP_lit4 / .byte 0x9f / DW_OP_stack_value / .byte 0x4 / DW_LLE_offset_pair (.LLST2) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST2) / .uleb128 0 /* .LVL0-.LVL0 / / Location list end address (.LLST2) / .uleb128 0x2 /* Location expression size / .byte 0x35 / DW_OP_lit5 / .byte 0x9f / DW_OP_stack_value / .byte 0x4 / DW_LLE_offset_pair (.LLST2) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST2) / .uleb128 1 /* .LFE0-.LVL0 / / Location list end address (.LLST2) / .uleb128 0x2 /* Location expression size / .byte 0x36 / DW_OP_lit6 / .byte 0x9f / DW_OP_stack_value / .byte 0 / DW_LLE_end_of_list (.LLST2) / .LLST3: .byte 0x6 /* DW_LLE_base_address (.LLST3) / .4byte .LVL0 /* Base address (.LLST3) / .byte 0x9 /* DW_LLE_view_pair (extension proposed for DWARF6) / .uleb128 0x6 / View list begin (.LLST3) / .uleb128 0x7 /* View list end (.LVUS3) / .byte 0x4 /* DW_LLE_offset_pair (.LLST3) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST3) / .uleb128 0 /* .LVL0-.LVL0 / / Location list end address (.LLST3) / .uleb128 0x2 /* Location expression size / .byte 0x34 / DW_OP_lit4 / .byte 0x9f / DW_OP_stack_value / .byte 0x9 / DW_LLE_view_pair / .uleb128 0x7 / View list begin (.LLST3) / .uleb128 0x8 /* View list end (.LVUS3) / .byte 0x4 /* DW_LLE_offset_pair (.LLST3) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST3) / .uleb128 0 /* .LVL0-.LVL0 / / Location list end address (.LLST3) / .uleb128 0x2 /* Location expression size / .byte 0x35 / DW_OP_lit5 / .byte 0x9f / DW_OP_stack_value / .byte 0x9 / DW_LLE_view_pair / .uleb128 0x8 / View list begin (.LLST3) / .uleb128 0x0 /* View list end (.LVUS3) / .byte 0x4 /* DW_LLE_offset_pair (.LLST3) / .uleb128 0 /* .LVL0-.LVL0 / / Location list begin address (.LLST3) / .uleb128 1 /* .LFE0-.LVL0 / / Location list end address (.LLST3) / .uleb128 0x2 /* Location expression size / .byte 0x36 / DW_OP_lit6 / .byte 0x9f / DW_OP_stack_value / .byte 0 / DW_LLE_end_of_list (.LLST3) / .Ldebug_loc2:
stsp/binutils-ia16	8,459	binutils/testsuite/binutils-all/locview-1.s	.text .Ltext0: .LFB0: /* locview.c:1 / .LM1: / view -0 / / locview.c:2 / .LM2: / view 1 / .LVL0: / DEBUG i => 0 / / locview.c:3 / .LM3: / view 2 / / DEBUG j => 0x1 / / locview.c:4 / .LM4: / view 3 / / DEBUG i => 0x2 / / locview.c:5 / .LM5: / view 4 / / DEBUG j => 0x3 / / locview.c:6 / .LM6: / view 5 / / DEBUG k => 0x4 / / DEBUG l => 0x4 / / locview.c:7 / .LM7: / view 6 / / DEBUG k => 0x5 / / DEBUG l => 0x5 / / locview.c:8 / .LM8: / view 7 / / DEBUG k => 0x6 / / DEBUG l => 0x6 / / locview.c:9 / .LM9: / view 8 / .byte 0 .LFE0: .Letext0: .section .debug_info .Ldebug_info0: .LIbase: .4byte .LIend - .LIstart / Length of Compilation Unit Info / .LIstart: .2byte 0x4 / DWARF version number / .4byte .Ldebug_abbrev0 / Offset Into Abbrev. Section / .byte 0x4 / Pointer Size (in bytes) / .LIcu: .uleb128 0x1 / (DIE (cu) DW_TAG_compile_unit) / .ascii "hand-crafted based on GCC output\0" .byte 0xc / DW_AT_language / .ascii "locview.c\0" .ascii "/tmp\0" .4byte 0 / DW_AT_low_pc / .LIsubf: .uleb128 0x2 / (DIE (subf) DW_TAG_subprogram) / .ascii "f\0" / DW_AT_name / .byte 0x1 / DW_AT_decl_file (locview.c) / .byte 0x1 / DW_AT_decl_line / .4byte .LIint-.LIbase / DW_AT_type / .4byte .LFB0 / DW_AT_low_pc / .4byte 1 / .LFE0-.LFB0 / / DW_AT_high_pc / .uleb128 0x1 / DW_AT_frame_base / .byte 0x9c / DW_OP_call_frame_cfa / / DW_AT_GNU_all_call_sites / .4byte .LIint - .LIbase / DW_AT_sibling / .LIvari: .uleb128 0x3 / (DIE (vari) DW_TAG_variable) / .ascii "i\0" / DW_AT_name / .byte 0x1 / DW_AT_decl_file (locview.c) / .byte 0x2 / DW_AT_decl_line / .4byte .LIint-.LIbase / DW_AT_type / .4byte .LLST0 / DW_AT_location / .4byte .LVUS0 / DW_AT_GNU_locviews / .LIvarj: .uleb128 0x3 / (DIE (varf) DW_TAG_variable) / .ascii "j\0" / DW_AT_name / .byte 0x1 / DW_AT_decl_file (locview.c) / .byte 0x3 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LLST1 / DW_AT_location / .4byte .LVUS1 / DW_AT_GNU_locviews / .LIvark: .uleb128 0x5 / (DIE (vark) DW_TAG_variable) / .ascii "k\0" / DW_AT_name / .byte 0x1 / DW_AT_decl_file (locview.c) / .byte 0x6 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LVUS2 / DW_AT_GNU_locviews / .4byte .LLST2 / DW_AT_location / .byte 0 / end of children of subf / .LIvarl: .uleb128 0x5 / (DIE (varl) DW_TAG_variable) / .ascii "l\0" / DW_AT_name / .byte 0x1 / DW_AT_decl_file (locview.c) / .byte 0x6 / DW_AT_decl_line / .4byte .LIint - .LIbase / DW_AT_type / .4byte .LVUS2 / DW_AT_GNU_locviews / .4byte .LLST2 / DW_AT_location / .byte 0 / end of children of subf / .LIint: .uleb128 0x4 / (DIE (int) DW_TAG_base_type) / .byte 0x4 / DW_AT_byte_size / .byte 0x5 / DW_AT_encoding / .ascii "int\0" / DW_AT_name / .byte 0 / end of children of cu / .LIend: .section .debug_abbrev .Ldebug_abbrev0: .LAbrv1: .uleb128 0x1 / (abbrev code) / .uleb128 0x11 / (TAG: DW_TAG_compile_unit) / .byte 0x1 / DW_children_yes / .uleb128 0x25 / (DW_AT_producer) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x13 / (DW_AT_language) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x1b / (DW_AT_comp_dir) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .byte 0 .byte 0 .LAbrv2: .uleb128 0x2 / (abbrev code) / .uleb128 0x2e / (TAG: DW_TAG_subprogram) / .byte 0x1 / DW_children_yes / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x11 / (DW_AT_low_pc) / .uleb128 0x1 / (DW_FORM_addr) / .uleb128 0x12 / (DW_AT_high_pc) / .uleb128 0x6 / (DW_FORM_data4) / .uleb128 0x40 / (DW_AT_frame_base) / .uleb128 0x18 / (DW_FORM_exprloc) / .uleb128 0x2117 / (DW_AT_GNU_all_call_sites) / .uleb128 0x19 / (DW_FORM_flag_present) / .uleb128 0x1 / (DW_AT_sibling) / .uleb128 0x13 / (DW_FORM_ref4) / .byte 0 .byte 0 .LAbrv3: .uleb128 0x3 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x17 / (DW_FORM_sec_offset) / .uleb128 0x2137 / (DW_AT_GNU_locviews) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .LAbrv4: .uleb128 0x4 / (abbrev code) / .uleb128 0x24 / (TAG: DW_TAG_base_type) / .byte 0 / DW_children_no / .uleb128 0xb / (DW_AT_byte_size) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3e / (DW_AT_encoding) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .byte 0 .byte 0 .LAbrv5: .uleb128 0x5 / (abbrev code) / .uleb128 0x34 / (TAG: DW_TAG_variable) / .byte 0 / DW_children_no / .uleb128 0x3 / (DW_AT_name) / .uleb128 0x8 / (DW_FORM_string) / .uleb128 0x3a / (DW_AT_decl_file) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x3b / (DW_AT_decl_line) / .uleb128 0xb / (DW_FORM_data1) / .uleb128 0x49 / (DW_AT_type) / .uleb128 0x13 / (DW_FORM_ref4) / .uleb128 0x2137 / (DW_AT_GNU_locviews) / .uleb128 0x17 / (DW_FORM_sec_offset) / .uleb128 0x2 / (DW_AT_location) / .uleb128 0x17 / (DW_FORM_sec_offset) / .byte 0 .byte 0 .byte 0 .section .debug_loc .Ldebug_loc0: .LVUS0: .uleb128 0x2 / View list begin (.LVUS0) / .uleb128 0x4 /* View list end (.LVUS0) / .uleb128 0x4 /* View list begin (.LVUS0) / .uleb128 0 /* View list end (.LVUS0) / .LLST0: .4byte .LVL0 /* Location list begin address (.LLST0) / .4byte .LVL0 /* Location list end address (.LLST0) / .2byte 0x2 /* Location expression size / .byte 0x30 / DW_OP_lit0 / .byte 0x9f / DW_OP_stack_value / .4byte .LVL0 / Location list begin address (.LLST0) / .4byte .LFE0 /* Location list end address (.LLST0) / .2byte 0x2 /* Location expression size / .byte 0x32 / DW_OP_lit2 / .byte 0x9f / DW_OP_stack_value / .4byte 0 / Location list terminator begin (.LLST0) / .4byte 0 /* Location list terminator end (.LLST0) / .LLST1: .4byte .LVL0 /* Location list begin address (.LLST1) / .4byte .LVL0 /* Location list end address (.LLST1) / .2byte 0x2 /* Location expression size / .byte 0x31 / DW_OP_lit1 / .byte 0x9f / DW_OP_stack_value / .4byte .LVL0 / Location list begin address (.LLST1) / .4byte .LFE0 /* Location list end address (.LLST1) / .2byte 0x2 /* Location expression size / .byte 0x33 / DW_OP_lit3 / .byte 0x9f / DW_OP_stack_value / .4byte 0 / Location list terminator begin (.LLST1) / .4byte 0 /* Location list terminator end (.LLST1) / .LVUS1: .uleb128 0x3 /* View list begin (.LVUS1) / .uleb128 0x5 /* View list end (.LVUS1) / .uleb128 0x5 /* View list begin (.LVUS1) / .uleb128 0 /* View list end (.LVUS1) / .LVUS2: .uleb128 0x6 /* View list begin (.LVUS2) / .uleb128 0x7 /* View list end (.LVUS2) / .uleb128 0x7 /* View list begin (.LVUS2) / .uleb128 0x8 /* View list end (.LVUS2) / .uleb128 0x8 /* View list begin (.LVUS2) / .uleb128 0 /* View list end (.LVUS2) / .LLST2: .4byte .LVL0 /* Location list begin address (.LLST2) / .4byte .LVL0 /* Location list end address (.LLST2) / .2byte 0x2 /* Location expression size / .byte 0x34 / DW_OP_lit4 / .byte 0x9f / DW_OP_stack_value / .4byte .LVL0 / Location list begin address (.LLST2) / .4byte .LVL0 /* Location list end address (.LLST2) / .2byte 0x2 /* Location expression size / .byte 0x35 / DW_OP_lit5 / .byte 0x9f / DW_OP_stack_value / .4byte .LVL0 / Location list begin address (.LLST2) / .4byte .LFE0 /* Location list end address (.LLST2) / .2byte 0x2 /* Location expression size / .byte 0x36 / DW_OP_lit6 / .byte 0x9f / DW_OP_stack_value / .4byte 0 / Location list terminator begin (.LLST2) / .4byte 0 /* Location list terminator end (.LLST2) /
stsp/binutils-ia16	1,400	binutils/testsuite/binutils-all/testranges.s	# Test .debug_info can reference .debug_ranges entries without ordering the # offsets strictly as increasing. .text start: .byte 1 sub: .byte 2 end: .section .debug_ranges,"",%progbits range: range_sub: .4byte sub, end .4byte 0, 0 ;# range terminator range_cu: .4byte start, end .4byte 0, 0 ;# range terminator .section .debug_info,"",%progbits .4byte debugE - debugS ;# Length of Compilation Unit Info debugS: .short 0x2 ;# DWARF version number .4byte abbrev0 ;# Offset Into Abbrev. Section .byte 0x4 ;# Pointer Size (in bytes) .uleb128 0x1 ;# (DIE (0xb) DW_TAG_compile_unit) .4byte range_cu - range ;# DW_AT_ranges .uleb128 0x2 ;# (DIE (0x6d) DW_TAG_subprogram) .ascii "A\0" ;# DW_AT_name .4byte range_sub - range ;# DW_AT_ranges ;# minimal section alignment on alpha-* is 2, ensure no new invalid CU ;# will be started. .balign 2 debugE: .section .debug_abbrev,"",%progbits abbrev0: .uleb128 0x1 ;# (abbrev code) .uleb128 0x11 ;# (TAG: DW_TAG_compile_unit) .byte 0x0 ;# DW_children_no .uleb128 0x55 ;# (DW_AT_ranges) .uleb128 0x6 ;# (DW_FORM_data4) .byte 0x0 .byte 0x0 .uleb128 0x2 ;# (abbrev code) .uleb128 0x2e ;# (TAG: DW_TAG_subprogram) .byte 0x0 ;# DW_children_no .uleb128 0x3 ;# (DW_AT_name) .uleb128 0x8 ;# (DW_FORM_string) .uleb128 0x55 ;# (DW_AT_ranges) .uleb128 0x6 ;# (DW_FORM_data4) .byte 0x0 .byte 0x0 .byte 0x0 ;# abbrevs terminator
stsp/binutils-ia16	3,119	binutils/testsuite/binutils-all/pr18374.s	.section .debug_info,"",%progbits .4byte 0x77 .2byte 0x4 .4byte .Ldebug_abbrev0 .byte 0x4 .uleb128 0x1 .4byte .LASF3 .byte 0xc .ascii "x.c\000" .4byte .LASF4 .4byte .Ltext0 .4byte .Letext0 .4byte .Ldebug_line0 .uleb128 0x2 .ascii "foo\000" .byte 0x1 .byte 0x2 .4byte .LFB0 .4byte .LFE0 .uleb128 0x1 .byte 0x9c .4byte 0x64 .uleb128 0x3 .ascii "b\000" .byte 0x1 .byte 0x2 .4byte 0x64 .4byte .LLST0 .uleb128 0x4 .4byte .LASF0 .byte 0x1 .byte 0x2 .4byte 0x66 .4byte .LLST1 .uleb128 0x5 .ascii "ptr\000" .byte 0x1 .byte 0x4 .4byte 0x6d .uleb128 0x1 .byte 0x50 .byte 0 .uleb128 0x6 .byte 0x4 .uleb128 0x7 .byte 0x4 .byte 0x7 .4byte .LASF1 .uleb128 0x8 .byte 0x4 .4byte 0x73 .uleb128 0x7 .byte 0x1 .byte 0x8 .4byte .LASF2 .byte 0 .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0x8 .uleb128 0x1b .uleb128 0xe .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x6 .uleb128 0x10 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x2 .uleb128 0x2e .byte 0x1 .uleb128 0x3f .uleb128 0x19 .uleb128 0x3 .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x27 .uleb128 0x19 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x6 .uleb128 0x40 .uleb128 0x18 .uleb128 0x2117 .uleb128 0x19 .uleb128 0x1 .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x3 .uleb128 0x5 .byte 0 .uleb128 0x3 .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x2 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x4 .uleb128 0x5 .byte 0 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x2 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x5 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x2 .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x6 .uleb128 0xf .byte 0 .uleb128 0xb .uleb128 0xb .byte 0 .byte 0 .uleb128 0x7 .uleb128 0x24 .byte 0 .uleb128 0xb .uleb128 0xb .uleb128 0x3e .uleb128 0xb .uleb128 0x3 .uleb128 0xe .byte 0 .byte 0 .uleb128 0x8 .uleb128 0xf .byte 0 .uleb128 0xb .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .byte 0 .byte 0 .byte 0 .section .debug_loc,"",%progbits .Ldebug_loc0: .LLST0: .4byte .LVL0 .4byte .LVL2 .2byte 0x1 .byte 0x50 .4byte .LVL2 .4byte .LFE0 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f .4byte 0 .4byte 0 .LLST1: .4byte .LVL0 .4byte .LVL1 .2byte 0x1 .byte 0x51 .4byte .LVL1 .4byte .LVL2 .2byte 0x3 .byte 0x71 .sleb128 -1 .byte 0x9f .4byte .LVL2 .4byte .LVL3 .2byte 0xb .byte 0x70 .sleb128 0 .byte 0x20 .byte 0xf3 .uleb128 0x1 .byte 0x51 .byte 0x22 .byte 0x70 .sleb128 0 .byte 0x22 .byte 0x9f .4byte .LVL3 .4byte .LFE0 .2byte 0xb .byte 0x70 .sleb128 0 .byte 0x20 .byte 0x70 .sleb128 0 .byte 0x22 .byte 0xf3 .uleb128 0x1 .byte 0x51 .byte 0x22 .byte 0x9f .4byte 0 .4byte 0
stsp/binutils-ia16	9,143	binutils/testsuite/binutils-all/dw2-3.S	/* This testcase is part of GDB, the GNU debugger. Copyright (C) 2004-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / Test a minimal file containing DWARF-2 information. This test also serves as a skeleton for other DWARF-2 tests. Most other tests will not be this extensively itemized and commented... / / Dummy function to provide debug information for. / .text .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .4byte 0 .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: / Debug information / .section .debug_info .Lcu1_begin: / CU header / .4byte .Lcu1_end - .Lcu1_start / Length of Compilation Unit / .Lcu1_start: .2byte 2 / DWARF Version / .4byte .Labbrev1_begin / Offset into abbrev section / .byte 4 / Pointer size / / CU die / .uleb128 1 / Abbrev: DW_TAG_compile_unit / .4byte .Lline1_begin / DW_AT_stmt_list / .4byte .Lend_text1 / DW_AT_high_pc / .4byte .Lbegin_text1 / DW_AT_low_pc / .ascii "file1.txt\0" / DW_AT_name / .ascii "GNU C 3.3.3\0" / DW_AT_producer / .byte 1 / DW_AT_language (C) / / func_cu1 / .uleb128 2 / Abbrev: DW_TAG_subprogram / .byte 1 / DW_AT_external / .byte 1 / DW_AT_decl_file / .byte 2 / DW_AT_decl_line / .ascii "func_cu1\0" / DW_AT_name / .4byte .Ltype_int2_in_cu2 / DW_AT_type / .4byte .Lbegin_func_cu1 / DW_AT_low_pc / .4byte .Lend_func_cu1 / DW_AT_high_pc / .byte 1 / DW_AT_frame_base: length / .byte 0x55 / DW_AT_frame_base: DW_OP_reg5 / / This type is named "int1" and not "int" to ensure it is unique, and thus we can easily ensure we expand this CU and not some other CU with "int". / .Ltype_int1_in_cu1: .uleb128 3 / Abbrev: DW_TAG_base_type / .ascii "int1\0" / DW_AT_name / .byte 4 / DW_AT_byte_size / .byte 5 / DW_AT_encoding / .Ltype_const_int1_in_cu1: .uleb128 4 / Abbrev: DW_TAG_const_type / .4byte .Ltype_int1_in_cu1-.Lcu1_begin / DW_AT_type / .uleb128 5 / Abbrev: DW_TAG_variable / .ascii "one\0" / DW_AT_name / .4byte .Ltype_const_int1_in_cu1-.Lcu1_begin / DW_AT_type / .byte 1 / DW_AT_const_value / .byte 0 / End of children of CU / .Lcu1_end: / Second compilation unit. / .Lcu2_begin: / CU header / .4byte .Lcu2_end - .Lcu2_start / Length of Compilation Unit / .Lcu2_start: .2byte 2 / DWARF Version / .4byte .Labbrev2_begin / Offset into abbrev section / .byte 4 / Pointer size / / CU die / .uleb128 1 / Abbrev: DW_TAG_compile_unit / .ascii "file1.txt\0" / DW_AT_name / .ascii "GNU C 3.3.3\0" / DW_AT_producer / .byte 1 / DW_AT_language (C) / / This type is named "int2" and not "int" to ensure it is unique, and thus we can easily ensure we expand this CU and not some other CU with "int". / .Ltype_int2_in_cu2: .uleb128 2 / Abbrev: DW_TAG_base_type / .ascii "int2\0" / DW_AT_name / .byte 4 / DW_AT_byte_size / .byte 5 / DW_AT_encoding / .Ltype_const_int2_in_cu2: .uleb128 3 / Abbrev: DW_TAG_const_type / .4byte .Ltype_int2_in_cu2-.Lcu2_begin / DW_AT_type / .uleb128 4 / Abbrev: DW_TAG_variable / .ascii "two\0" / DW_AT_name / .4byte .Ltype_const_int2_in_cu2-.Lcu2_begin / DW_AT_type / .byte 2 / DW_AT_const_value / .byte 0 / End of children of CU / .Lcu2_end: / Abbrev table / .section .debug_abbrev .Labbrev1_begin: .uleb128 1 / Abbrev code / .uleb128 0x11 / DW_TAG_compile_unit / .byte 1 / has_children / .uleb128 0x10 / DW_AT_stmt_list / .uleb128 0x6 / DW_FORM_data4 / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x25 / DW_AT_producer / .uleb128 0x8 / DW_FORM_string / .uleb128 0x13 / DW_AT_language / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 2 / Abbrev code / .uleb128 0x2e / DW_TAG_subprogram / .byte 0 / has_children / .uleb128 0x3f / DW_AT_external / .uleb128 0xc / DW_FORM_flag / .uleb128 0x3a / DW_AT_decl_file / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3b / DW_AT_decl_line / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x49 / DW_AT_type / .uleb128 0x10 / DW_FORM_ref_addr / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x40 / DW_AT_frame_base / .uleb128 0xa / DW_FORM_block1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 3 / Abbrev code / .uleb128 0x24 / DW_TAG_base_type / .byte 0 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0xb / DW_AT_byte_size / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3e / DW_AT_encoding / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 4 / Abbrev code / .uleb128 0x26 / DW_TAG_const_type / .byte 0x0 / DW_children_no / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 5 / Abbrev code / .uleb128 0x34 / DW_TAG_variable / .byte 0x0 / DW_children_no / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .uleb128 0x1c / DW_AT_const_value / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .Labbrev2_begin: .uleb128 1 / Abbrev code / .uleb128 0x11 / DW_TAG_compile_unit / .byte 1 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x25 / DW_AT_producer / .uleb128 0x8 / DW_FORM_string / .uleb128 0x13 / DW_AT_language / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 2 / Abbrev code / .uleb128 0x24 / DW_TAG_base_type / .byte 0 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0xb / DW_AT_byte_size / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3e / DW_AT_encoding / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 3 / Abbrev code / .uleb128 0x26 / DW_TAG_const_type / .byte 0x0 / DW_children_no / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 4 / Abbrev code / .uleb128 0x34 / DW_TAG_variable / .byte 0x0 / DW_children_no / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .uleb128 0x1c / DW_AT_const_value / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / / Line table / .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start / Initial length / .Lline1_start: .2byte 2 / Version / .4byte .Lline1_lines - .Lline1_hdr / header_length / .Lline1_hdr: .byte 1 / Minimum insn length / .byte 1 / default_is_stmt / .byte 1 / line_base / .byte 1 / line_range / .byte 0x10 / opcode_base / / Standard lengths / .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 / Include directories / .byte 0 / File names / .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lbegin_func_cu1 .byte 3 / DW_LNS_advance_line / .sleb128 3 / ... to 4 / .byte 1 / DW_LNS_copy / .byte 1 / DW_LNS_copy (second time as an end-of-prologue marker) / .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lend_func_cu1 .byte 0 / DW_LNE_end_of_sequence */ .uleb128 1 .byte 1 .Lline1_end:
stsp/binutils-ia16	5,206	binutils/testsuite/binutils-all/dw2-2.S	/* This testcase is derived from a similar test in GDB. Copyright (C) 2008-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / Dummy function to provide debug information for. / .text .Lbegin_text1: .globl func_cu2 .type func_cu2, %function func_cu2: .Lbegin_func_cu2: .4byte 0 .Lend_func_cu2: .size func_cu2, .-func_cu2 .Lend_text1: / Debug information / .section .debug_info .Lcu1_begin: / CU header / .4byte .Lcu1_end - .Lcu1_start / Length of Compilation Unit / .Lcu1_start: .2byte 2 / DWARF Version / .4byte .Labbrev1_begin / Offset into abbrev section / .byte 4 / Pointer size / / CU die / .uleb128 1 / Abbrev: DW_TAG_compile_unit / .4byte .Lline1_begin / DW_AT_stmt_list / .4byte .Lend_text1 / DW_AT_high_pc / .4byte .Lbegin_text1 / DW_AT_low_pc / .ascii "file1.txt\0" / DW_AT_name / .ascii "GNU C 3.3.3\0" / DW_AT_producer / .byte 1 / DW_AT_language (C) / / func_cu2 / .uleb128 2 / Abbrev: DW_TAG_subprogram / .byte 1 / DW_AT_external / .byte 1 / DW_AT_decl_file / .byte 2 / DW_AT_decl_line / .ascii "func_cu2\0" / DW_AT_name / .4byte .Ltype_int-.Lcu1_begin / DW_AT_type / .4byte .Lbegin_func_cu2 / DW_AT_low_pc / .4byte .Lend_func_cu2 / DW_AT_high_pc / .byte 1 / DW_AT_frame_base: length / .byte 0x55 / DW_AT_frame_base: DW_OP_reg5 / .Ltype_int: .uleb128 3 / Abbrev: DW_TAG_base_type / .ascii "int\0" / DW_AT_name / .byte 4 / DW_AT_byte_size / .byte 5 / DW_AT_encoding / .byte 0 / End of children of CU / .Lcu1_end: / Line table / .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start / Initial length / .Lline1_start: .2byte 2 / Version / .4byte .Lline1_lines - .Lline1_hdr / header_length / .Lline1_hdr: .byte 1 / Minimum insn length / .byte 1 / default_is_stmt / .byte 1 / line_base / .byte 1 / line_range / .byte 0x10 / opcode_base / / Standard lengths / .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 / Include directories / .byte 0 / File names / .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lbegin_func_cu2 .byte 3 / DW_LNS_advance_line / .sleb128 3 / ... to 4 / .byte 1 / DW_LNS_copy / .byte 1 / DW_LNS_copy (second time as an end-of-prologue marker) / .byte 0 / DW_LNE_set_address / .uleb128 5 .byte 2 .4byte .Lend_func_cu2 .byte 0 / DW_LNE_end_of_sequence / .uleb128 1 .byte 1 .Lline1_end: / Abbrev table / .section .debug_abbrev .Labbrev1_begin: .uleb128 1 / Abbrev code / .uleb128 0x11 / DW_TAG_compile_unit / .byte 1 / has_children / .uleb128 0x10 / DW_AT_stmt_list / .uleb128 0x6 / DW_FORM_data4 / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x25 / DW_AT_producer / .uleb128 0x8 / DW_FORM_string / .uleb128 0x13 / DW_AT_language / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 2 / Abbrev code / .uleb128 0x2e / DW_TAG_subprogram / .byte 0 / has_children / .uleb128 0x3f / DW_AT_external / .uleb128 0xc / DW_FORM_flag / .uleb128 0x3a / DW_AT_decl_file / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3b / DW_AT_decl_line / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x40 / DW_AT_frame_base / .uleb128 0xa / DW_FORM_block1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 3 / Abbrev code / .uleb128 0x24 / DW_TAG_base_type / .byte 0 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0xb / DW_AT_byte_size / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3e / DW_AT_encoding / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator */
stsp/binutils-ia16	2,386	binutils/testsuite/binutils-all/debuglink.s	/* Assembler source used to create an object file for testing readelf's and objdump's ability to process separate debug information files. Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / Create a fake .gnu_debuglink section. / .section .gnu_debuglink,"",%progbits .asciz "this_is_a_debuglink.debug" .balign 4 .4byte 0x12345678 / Create a fake .gnu_debugaltlink section. / .section .gnu_debugaltlink,"",%progbits .asciz "linkdebug.debug" .dc.b 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 .dc.b 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff .dc.b 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef / Create a .debug_str section for local use. This is also to check the ability to dump the same section twice, if it exists in both the main file and the separate debug info file. / .section .debug_str,"MS",%progbits,1 string1: .asciz "string-1" .asciz "string-2" .balign 2 string_end: / Create a .debug_info section that contains string references into the separate debug info file. Plus the abbreviations are stored in the separate file too... / .section .debug_info,"",%progbits .4byte debugE - debugS ;# Length of Compilation Unit Info debugS: .short 0x4 ;# DWARF version number. .4byte 0x0 ;# Offset into .debug_abbrev section. .byte 0x4 ;# Pointer Size (in bytes). .uleb128 0x1 ;# Use abbrev #1. This needs a string from the local string table. .4byte string1 .uleb128 0x2 ;# Use abbrev #2. This needs a string from the separate string table. .4byte 0x0 ;# Avoid complicated expression resolution and hard code the offset... ;# Minimal section alignment on alpha- is 2, so ensure no new invalid CU ;# will be started. .balign 2, 0 debugE:
stsp/binutils-ia16	4,440	binutils/testsuite/binutils-all/dw2-ranges.S	/* Copyright (C) 2015-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / / This tests makes use of the .debug_ranges section, especially, making sure that the base address encoding scheme is used. / / Dummy function to provide debug information for. / .text .globl _start _start: .4byte 0 .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .4byte 0 .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: .Lbegin_text2: .globl func_cu2 .type func_cu2, %function func_cu2: .Lbegin_func_cu2: .4byte 0 .Lend_func_cu2: .size func_cu2, .-func_cu2 .Lend_text2: / Debug information / .section .debug_info .Lcu1_begin: / CU header / .4byte .Lcu1_end - .Lcu1_start / Length of Compilation Unit / .Lcu1_start: .2byte 2 / DWARF Version / .4byte .Labbrev1_begin / Offset into abbrev section / .byte 4 / Pointer size / / CU die / .uleb128 1 / Abbrev: DW_TAG_compile_unit / .4byte .Lrange1_begin .ascii "file1.c\0" / DW_AT_name / .byte 1 / DW_AT_language (C) / / func_cu1 / .uleb128 2 / Abbrev: DW_TAG_subprogram / .ascii "func_cu1\0" / DW_AT_name / .4byte .Ltype_int-.Lcu1_begin / DW_AT_type / .4byte .Lbegin_func_cu1 / DW_AT_low_pc / .4byte .Lend_func_cu1 / DW_AT_high_pc / / func_cu1 / .uleb128 2 / Abbrev: DW_TAG_subprogram / .ascii "func_cu2\0" / DW_AT_name / .4byte .Ltype_int-.Lcu1_begin / DW_AT_type / .4byte .Lbegin_func_cu2 / DW_AT_low_pc / .4byte .Lend_func_cu2 / DW_AT_high_pc / .Ltype_int: .uleb128 3 / Abbrev: DW_TAG_base_type / .ascii "int\0" / DW_AT_name / .byte 4 / DW_AT_byte_size / .byte 5 / DW_AT_encoding / .byte 0 / End of children of CU / .Lcu1_end: .section .debug_ranges .Lrange1_begin: .4byte 0xffffffff / base address marker / .4byte .Lbegin_text1 / base address / .4byte 0 / start offset / .4byte .Lend_text1 - .Lbegin_text1 / end offset / .4byte 0xffffffff / base address marker / .4byte .Lbegin_text2 / base address / .4byte 0 / start offset / .4byte .Lend_text2 - .Lbegin_text2 / end offset / .4byte 0 / End marker (Part 1) / .4byte 0 / End marker (Part 2) / .section .debug_abbrev .Labbrev1_begin: .uleb128 1 / Abbrev code / .uleb128 0x11 / DW_TAG_compile_unit / .byte 1 / has_children / .uleb128 0x55 / DW_AT_ranges / .uleb128 0x17 / DW_FORM_sec_offset / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x13 / DW_AT_language / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 2 / Abbrev code / .uleb128 0x2e / DW_TAG_subprogram / .byte 0 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0x49 / DW_AT_type / .uleb128 0x13 / DW_FORM_ref4 / .uleb128 0x11 / DW_AT_low_pc / .uleb128 0x1 / DW_FORM_addr / .uleb128 0x12 / DW_AT_high_pc / .uleb128 0x1 / DW_FORM_addr / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .uleb128 3 / Abbrev code / .uleb128 0x24 / DW_TAG_base_type / .byte 0 / has_children / .uleb128 0x3 / DW_AT_name / .uleb128 0x8 / DW_FORM_string / .uleb128 0xb / DW_AT_byte_size / .uleb128 0xb / DW_FORM_data1 / .uleb128 0x3e / DW_AT_encoding / .uleb128 0xb / DW_FORM_data1 / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator / .byte 0x0 / Terminator */
stsp/binutils-ia16	3,702	binutils/testsuite/binutils-all/mips/mips16-undecoded.s	.text .set mips16 .globl foo .ent foo foo: # Individual major opcodes. addiu $2, $sp, 0x4011 .half 0xf008, 0x0211 .half 0xf008, 0x0231 .half 0xf008, 0x0251 .half 0xf008, 0x0291 addiu $2, $pc, 0x4011 .half 0xf008, 0x0a11 .half 0xf008, 0x0a31 .half 0xf008, 0x0a51 .half 0xf008, 0x0a91 b . + 0x8026 .half 0xf008, 0x1011 .half 0xf008, 0x1031 .half 0xf008, 0x1051 .half 0xf008, 0x1091 .half 0xf008, 0x1111 .half 0xf008, 0x1211 .half 0xf008, 0x1411 beqz $2, . + 0x8026 .half 0xf008, 0x2211 .half 0xf008, 0x2231 .half 0xf008, 0x2251 .half 0xf008, 0x2291 bnez $2, . + 0x8026 .half 0xf008, 0x2a11 .half 0xf008, 0x2a31 .half 0xf008, 0x2a51 .half 0xf008, 0x2a91 addiu $2, 0x4011 .half 0xf008, 0x4a11 .half 0xf008, 0x4a31 .half 0xf008, 0x4a51 .half 0xf008, 0x4a91 slti $2, 0x4011 .half 0xf008, 0x5211 .half 0xf008, 0x5231 .half 0xf008, 0x5251 .half 0xf008, 0x5291 sltiu $2, 0x4011 .half 0xf008, 0x5a11 .half 0xf008, 0x5a31 .half 0xf008, 0x5a51 .half 0xf008, 0x5a91 li $2, 0x4011 .half 0xf008, 0x6a11 .half 0xf008, 0x6a31 .half 0xf008, 0x6a51 .half 0xf008, 0x6a91 cmpi $2, 0x4011 .half 0xf008, 0x7211 .half 0xf008, 0x7231 .half 0xf008, 0x7251 .half 0xf008, 0x7291 lw $2, 0x4011($sp) .half 0xf008, 0x9211 .half 0xf008, 0x9231 .half 0xf008, 0x9251 .half 0xf008, 0x9291 lw $2, 0x4011($pc) .half 0xf008, 0xb211 .half 0xf008, 0xb231 .half 0xf008, 0xb251 .half 0xf008, 0xb291 sw $2, 0x4011($sp) .half 0xf008, 0xd211 .half 0xf008, 0xd231 .half 0xf008, 0xd251 .half 0xf008, 0xd291 # I8 major opcode. bteqz . + 0x8026 .half 0xf008, 0x6011 .half 0xf008, 0x6031 .half 0xf008, 0x6051 .half 0xf008, 0x6091 btnez . + 0x8026 .half 0xf008, 0x6111 .half 0xf008, 0x6131 .half 0xf008, 0x6151 .half 0xf008, 0x6191 sw $ra, 0x4011($sp) .half 0xf008, 0x6211 .half 0xf008, 0x6231 .half 0xf008, 0x6251 .half 0xf008, 0x6291 addiu $sp, 0x4011 .half 0xf008, 0x6311 .half 0xf008, 0x6331 .half 0xf008, 0x6351 .half 0xf008, 0x6391 # SHIFT major opcode sll $2, $3, 0x14 .half 0xf500, 0x3260 .half 0xf500, 0x3264 .half 0xf500, 0x3268 .half 0xf500, 0x3270 .half 0xf501, 0x3260 .half 0xf502, 0x3260 .half 0xf504, 0x3260 .half 0xf508, 0x3260 .half 0xf510, 0x3260 .half 0xf520, 0x3260 dsll $2, $3, 0x14 .half 0xf500, 0x3261 .half 0xf500, 0x3265 .half 0xf500, 0x3269 .half 0xf500, 0x3271 .half 0xf501, 0x3261 .half 0xf502, 0x3261 .half 0xf504, 0x3261 .half 0xf508, 0x3261 .half 0xf510, 0x3261 .half 0xf520, 0x3261 srl $2, $3, 0x14 .half 0xf500, 0x3262 .half 0xf500, 0x3266 .half 0xf500, 0x326a .half 0xf500, 0x3272 .half 0xf501, 0x3262 .half 0xf502, 0x3262 .half 0xf504, 0x3262 .half 0xf508, 0x3262 .half 0xf510, 0x3262 .half 0xf520, 0x3262 sra $2, $3, 0x14 .half 0xf500, 0x3263 .half 0xf500, 0x3267 .half 0xf500, 0x326b .half 0xf500, 0x3273 .half 0xf501, 0x3263 .half 0xf502, 0x3263 .half 0xf504, 0x3263 .half 0xf508, 0x3263 .half 0xf510, 0x3263 .half 0xf520, 0x3263 # RR major opcode dsrl $2, 0x14 .half 0xf500, 0xe848 .half 0xf500, 0xe948 .half 0xf500, 0xea48 .half 0xf500, 0xec48 .half 0xf501, 0xe848 .half 0xf502, 0xe848 .half 0xf504, 0xe848 .half 0xf508, 0xe848 .half 0xf510, 0xe848 .half 0xf520, 0xe848 dsra $2, 0x14 .half 0xf500, 0xe853 .half 0xf500, 0xe953 .half 0xf500, 0xea53 .half 0xf500, 0xec53 .half 0xf501, 0xe853 .half 0xf502, 0xe853 .half 0xf504, 0xe853 .half 0xf508, 0xe853 .half 0xf510, 0xe853 .half 0xf520, 0xe853 # I64 major opcode. daddiu $sp, 0x4011 .half 0xf008, 0xfb11 .half 0xf008, 0xfb31 .half 0xf008, 0xfb51 .half 0xf008, 0xfb91 .end foo # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 .space 16
stsp/binutils-ia16	2,182	binutils/testsuite/binutils-all/mips/mips16-pcrel.s	.module mips64 .set mips16 .set noreorder .set noautoextend .align 12, 0 foo0: nop nop addiu $2, $pc, 0x3fc nop nop nop lw $3, 0x3fc($pc) nop nop nop daddiu $4, $pc, 0x7c nop nop nop nop nop ld $5, 0xf8($pc) .align 12, 0 foo1: jal bar0 addiu $2, $pc, 0x3fc nop jal bar0 lw $3, 0x3fc($pc) nop jal bar0 daddiu $4, $pc, 0x7c nop nop nop jal bar0 ld $5, 0xf8($pc) .align 12, 0 foo2: jalx bar1 addiu $2, $pc, 0x3fc nop jalx bar1 lw $3, 0x3fc($pc) nop jalx bar1 daddiu $4, $pc, 0x7c nop nop nop jalx bar1 ld $5, 0xf8($pc) .align 12, 0 foo3: nop jr $16 addiu $2, $pc, 0x3fc nop nop jr $16 lw $3, 0x3fc($pc) nop nop jr $16 daddiu $4, $pc, 0x7c nop nop nop nop jr $16 ld $5, 0xf8($pc) .align 12, 0 foo4: nop jr $31 addiu $2, $pc, 0x3fc nop nop jr $31 lw $3, 0x3fc($pc) nop nop jr $31 daddiu $4, $pc, 0x7c nop nop nop nop jr $31 ld $5, 0xf8($pc) .align 12, 0 foo5: nop jalr $16 addiu $2, $pc, 0x3fc nop nop jalr $16 lw $3, 0x3fc($pc) nop nop jalr $16 daddiu $4, $pc, 0x7c nop nop nop nop jalr $16 ld $5, 0xf8($pc) .align 12, 0 foo6: nop .half 0xe860 addiu $2, $pc, 0x3fc nop nop .half 0xe860 lw $3, 0x3fc($pc) nop nop .half 0xe860 daddiu $4, $pc, 0x7c nop nop nop nop .half 0xe860 ld $5, 0xf8($pc) .align 12, 0 foo7: nop jrc $16 addiu $2, $pc, 0x3fc nop nop jrc $16 lw $3, 0x3fc($pc) nop nop jrc $16 daddiu $4, $pc, 0x7c nop nop nop nop jrc $16 ld $5, 0xf8($pc) .align 12, 0 foo8: nop jrc $31 addiu $2, $pc, 0x3fc nop nop jrc $31 lw $3, 0x3fc($pc) nop nop jrc $31 daddiu $4, $pc, 0x7c nop nop nop nop jrc $31 ld $5, 0xf8($pc) .align 12, 0 foo9: nop jalrc $16 addiu $2, $pc, 0x3fc nop nop jalrc $16 lw $3, 0x3fc($pc) nop nop jalrc $16 daddiu $4, $pc, 0x7c nop nop nop nop jalrc $16 ld $5, 0xf8($pc) .align 12, 0 fooa: nop .half 0xe960 addiu $2, $pc, 0x3fc nop nop .half 0xe960 lw $3, 0x3fc($pc) nop nop .half 0xe960 daddiu $4, $pc, 0x7c nop nop nop nop .half 0xe960 ld $5, 0xf8($pc) # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 12, 0
stsp/binutils-ia16	9,273	binutils/testsuite/binutils-all/mips/mips16-extend-insn.s	.set mips16 .set noreorder foo: extend 0x123 # ADDIUSP addiu $16, $29, 0 extend 0x123 addiu $16, $29, 128 extend 0x123 addiu $16, $29, 256 extend 0x123 addiu $16, $29, 384 extend 0x123 addiu $16, $29, 512 extend 0x123 addiu $16, $29, 640 extend 0x123 addiu $16, $29, 768 extend 0x123 addiu $16, $29, 896 extend 0x123 # ADDIUPC addiu $16, $pc, 0 extend 0x123 addiu $16, $pc, 128 extend 0x123 addiu $16, $pc, 256 extend 0x123 addiu $16, $pc, 384 extend 0x123 addiu $16, $pc, 512 extend 0x123 addiu $16, $pc, 640 extend 0x123 addiu $16, $pc, 768 extend 0x123 addiu $16, $pc, 896 extend 0x123 # B b . + 2 extend 0x123 b . + 66 extend 0x123 b . + 130 extend 0x123 b . + 194 extend 0x123 b . + 258 extend 0x123 b . + 322 extend 0x123 b . + 386 extend 0x123 b . + 450 extend 0x123 # BEQZ beqz $16, . + 2 extend 0x123 beqz $16, . + 66 extend 0x123 beqz $16, . + 130 extend 0x123 beqz $16, . + 194 extend 0x123 beqz $16, . - 254 extend 0x123 beqz $16, . - 190 extend 0x123 beqz $16, . - 126 extend 0x123 beqz $16, . - 62 extend 0x123 # BNEZ bnez $16, . + 2 extend 0x123 bnez $16, . + 66 extend 0x123 bnez $16, . + 130 extend 0x123 bnez $16, . + 194 extend 0x123 bnez $16, . - 254 extend 0x123 bnez $16, . - 190 extend 0x123 bnez $16, . - 126 extend 0x123 bnez $16, . - 62 extend 0x123 # SHIFT # SLL sll $16, $16, 8 extend 0x123 sll $16, $16, 1 extend 0x123 sll $16, $16, 2 extend 0x123 sll $16, $16, 3 extend 0x123 sll $16, $16, 4 extend 0x123 sll $16, $16, 5 extend 0x123 sll $16, $16, 6 extend 0x123 sll $16, $16, 7 extend 0x123 # DSLL dsll $16, $16, 8 extend 0x123 dsll $16, $16, 1 extend 0x123 dsll $16, $16, 2 extend 0x123 dsll $16, $16, 3 extend 0x123 dsll $16, $16, 4 extend 0x123 dsll $16, $16, 5 extend 0x123 dsll $16, $16, 6 extend 0x123 dsll $16, $16, 7 extend 0x123 # SRL srl $16, $16, 8 extend 0x123 srl $16, $16, 1 extend 0x123 srl $16, $16, 2 extend 0x123 srl $16, $16, 3 extend 0x123 srl $16, $16, 4 extend 0x123 srl $16, $16, 5 extend 0x123 srl $16, $16, 6 extend 0x123 srl $16, $16, 7 extend 0x123 # SRA sra $16, $16, 8 extend 0x123 sra $16, $16, 1 extend 0x123 sra $16, $16, 2 extend 0x123 sra $16, $16, 3 extend 0x123 sra $16, $16, 4 extend 0x123 sra $16, $16, 5 extend 0x123 sra $16, $16, 6 extend 0x123 sra $16, $16, 7 extend 0x123 # LD ld $16, 0($16) extend 0x123 # RRI-A # ADDIU addiu $16, $16, 0 extend 0x123 # DADDIU daddiu $16, $16, 0 extend 0x123 # ADDIU8 addiu $16, 0 extend 0x123 addiu $16, 32 extend 0x123 addiu $16, 64 extend 0x123 addiu $16, 96 extend 0x123 addiu $16, -128 extend 0x123 addiu $16, -96 extend 0x123 addiu $16, -64 extend 0x123 addiu $16, -32 extend 0x123 # SLTI slti $16, 0 extend 0x123 slti $16, 32 extend 0x123 slti $16, 64 extend 0x123 slti $16, 96 extend 0x123 slti $16, 128 extend 0x123 slti $16, 160 extend 0x123 slti $16, 192 extend 0x123 slti $16, 224 extend 0x123 # SLTIU sltiu $16, 0 extend 0x123 sltiu $16, 32 extend 0x123 sltiu $16, 64 extend 0x123 sltiu $16, 96 extend 0x123 sltiu $16, 128 extend 0x123 sltiu $16, 160 extend 0x123 sltiu $16, 192 extend 0x123 sltiu $16, 224 extend 0x123 # I8 # BTEQZ bteqz . + 2 extend 0x123 bteqz . + 66 extend 0x123 bteqz . + 130 extend 0x123 bteqz . + 194 extend 0x123 bteqz . - 254 extend 0x123 bteqz . - 190 extend 0x123 bteqz . - 126 extend 0x123 bteqz . - 62 extend 0x123 # BTNEZ btnez . + 2 extend 0x123 btnez . + 66 extend 0x123 btnez . + 130 extend 0x123 btnez . + 194 extend 0x123 btnez . - 254 extend 0x123 btnez . - 190 extend 0x123 btnez . - 126 extend 0x123 btnez . - 62 extend 0x123 # SWRASP sw $31, 0($29) extend 0x123 sw $31, 128($29) extend 0x123 sw $31, 256($29) extend 0x123 sw $31, 512($29) extend 0x123 sw $31, 640($29) extend 0x123 sw $31, 768($29) extend 0x123 sw $31, 896($29) extend 0x123 sw $31, 0($29) extend 0x123 # ADJSP addiu $29, 0 extend 0x123 addiu $29, 256 extend 0x123 addiu $29, 512 extend 0x123 addiu $29, 768 extend 0x123 addiu $29, -1024 extend 0x123 addiu $29, -768 extend 0x123 addiu $29, -512 extend 0x123 addiu $29, -256 extend 0x123 # SVRS # RESTORE restore 128 extend 0x123 # SAVE save 128 extend 0x123 # MOV32R move $0, $16 extend 0x123 move $0, $17 extend 0x123 # MOVR32 move $16, $0 extend 0x123 # LI li $16, 0 extend 0x123 li $16, 32 extend 0x123 li $16, 64 extend 0x123 li $16, 96 extend 0x123 li $16, 128 extend 0x123 li $16, 160 extend 0x123 li $16, 192 extend 0x123 li $16, 224 extend 0x123 # CMPI cmpi $16, 0 extend 0x123 cmpi $16, 32 extend 0x123 cmpi $16, 64 extend 0x123 cmpi $16, 96 extend 0x123 cmpi $16, 128 extend 0x123 cmpi $16, 160 extend 0x123 cmpi $16, 192 extend 0x123 cmpi $16, 224 extend 0x123 # SD sd $16, 0($16) extend 0x123 # LB lb $16, 0($16) extend 0x123 # LH lh $16, 0($16) extend 0x123 # LWSP lw $16, 0($29) extend 0x123 lw $16, 128($29) extend 0x123 lw $16, 256($29) extend 0x123 lw $16, 384($29) extend 0x123 lw $16, 512($29) extend 0x123 lw $16, 640($29) extend 0x123 lw $16, 768($29) extend 0x123 lw $16, 896($29) extend 0x123 # LW lw $16, 0($16) extend 0x123 # LBU lbu $16, 0($16) extend 0x123 # LHU lhu $16, 0($16) extend 0x123 # LWPC lw $16, 0($pc) extend 0x123 lw $16, 128($pc) extend 0x123 lw $16, 256($pc) extend 0x123 lw $16, 384($pc) extend 0x123 lw $16, 512($pc) extend 0x123 lw $16, 640($pc) extend 0x123 lw $16, 768($pc) extend 0x123 lw $16, 896($pc) extend 0x123 # LWU lwu $16, 0($16) extend 0x123 # SB sb $16, 0($16) extend 0x123 # SH sh $16, 0($16) extend 0x123 # SWSP sw $16, 0($29) extend 0x123 sw $16, 128($29) extend 0x123 sw $16, 256($29) extend 0x123 sw $16, 384($29) extend 0x123 sw $16, 512($29) extend 0x123 sw $16, 640($29) extend 0x123 sw $16, 768($29) extend 0x123 sw $16, 896($29) extend 0x123 # SW sw $16, 0($16) extend 0x123 # RRR # DADDU daddu $16, $16, $16 extend 0x123 # ADDU addu $16, $16, $16 extend 0x123 # DSUBU dsubu $16, $16, $16 extend 0x123 # SUBU subu $16, $16, $16 extend 0x123 # RR # J(AL)R(C) # JR rx jr $16 extend 0x123 # JR ra jr $31 extend 0x123 # JALR jalr $16 extend 0x123 # JRC rx jrc $16 extend 0x123 # JRC ra jrc $31 extend 0x123 # JALRC jalrc $16 extend 0x123 # SDBBP sdbbp 0 extend 0x123 # SLT slt $16, $16 extend 0x123 # SLTU sltu $16, $16 extend 0x123 # SLLV sllv $16, $16 extend 0x123 # BREAK break 0 extend 0x123 # SRLV srlv $16, $16 extend 0x123 # SRAV srav $16, $16 extend 0x123 # DSRL dsrl $16, 8 extend 0x123 dsrl $16, 1 extend 0x123 dsrl $16, 2 extend 0x123 dsrl $16, 3 extend 0x123 dsrl $16, 4 extend 0x123 dsrl $16, 5 extend 0x123 dsrl $16, 6 extend 0x123 dsrl $16, 7 extend 0x123 # ENTRY/EXIT entry extend 0x123 entry $31 extend 0x123 exit $f0 extend 0x123 exit $f0-$f1 extend 0x123 exit extend 0x123 # CMP cmp $16, $16 extend 0x123 # NEG neg $16, $16 extend 0x123 # AND and $16, $16 extend 0x123 # OR or $16, $16 extend 0x123 # XOR xor $16, $16 extend 0x123 # NOT not $16, $16 extend 0x123 # MFHI mfhi $16 extend 0x123 # CNVT # ZEB zeb $16 extend 0x123 # ZEH zeh $16 extend 0x123 # ZEW zew $16 extend 0x123 # SEB seb $16 extend 0x123 # SEH seh $16 extend 0x123 # SEW sew $16 extend 0x123 # MFLO mflo $16 extend 0x123 # DSRA dsra $16, 8 extend 0x123 dsra $16, 1 extend 0x123 dsra $16, 2 extend 0x123 dsra $16, 3 extend 0x123 dsra $16, 4 extend 0x123 dsra $16, 5 extend 0x123 dsra $16, 6 extend 0x123 dsra $16, 7 extend 0x123 # DSLLV dsllv $16, $16 extend 0x123 # DSRLV dsrlv $16, $16 extend 0x123 # DSRAV dsrav $16, $16 extend 0x123 # MULT mult $16, $16 extend 0x123 # MULTU multu $16, $16 extend 0x123 # DIV div $0, $16, $16 extend 0x123 # DIVU divu $0, $16, $16 extend 0x123 # DMULT dmult $16, $16 extend 0x123 # DMULTU dmultu $16, $16 extend 0x123 # DDIV ddiv $0, $16, $16 extend 0x123 # DDIVU ddivu $0, $16, $16 extend 0x123 # EXTEND extend 0 extend 0x123 # I64 # LDSP ld $16, 0($29) extend 0x123 # SDSP sd $16, 0($29) extend 0x123 # SDRASP sd $31, 0($29) extend 0x123 sd $31, 256($29) extend 0x123 sd $31, 512($29) extend 0x123 sd $31, 768($29) extend 0x123 sd $31, 1024($29) extend 0x123 sd $31, 1280($29) extend 0x123 sd $31, 1536($29) extend 0x123 sd $31, 1792($29) extend 0x123 # DADJSP daddiu $29, 0 extend 0x123 daddiu $29, 256 extend 0x123 daddiu $29, 512 extend 0x123 daddiu $29, 768 extend 0x123 daddiu $29, -1024 extend 0x123 daddiu $29, -768 extend 0x123 daddiu $29, -512 extend 0x123 daddiu $29, -256 extend 0x123 # LDPC ld $16, 0($pc) extend 0x123 # DADDIU5 daddiu $16, 0 extend 0x123 # DADDIUPC daddiu $16, $pc, 0 extend 0x123 # DADDIUSP daddiu $16, $sp, 0 # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 .space 16
stsp/binutils-ia16	1,478	binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s	.text func: //scale 1, size<0> check for H. #st1 {v30.h}[0], [x30] .inst 0x0d0043de \| (1 << 10) #st2 {v29.h, v30.h}[0], [x30] .inst 0x0d2043dd \| (1 << 10) #st3 {v28.h, v29.h, v30.h}[0], [x30] .inst 0x0d0063dc \| (1 << 10) #st4 {v27.h, v28.h, v29.h, v30.h}[0], [x30] .inst 0x0d2063db \| (1 << 10) //scale 2, size<1> check for S. #st1 {v30.s}[0], [x30] .inst 0x0d0083de \| (1 << 11) #st2 {v29.s, v30.s}[0], [x30] .inst 0x0d2083dd \| (1 << 11) #st3 {v28.s, v29.s, v30.s}[0], [x30] .inst 0x0d00a3dc \| (1 << 11) #st4 {v27.s, v28.s, v29.s, v30.s}[0], [x30] .inst 0x0d20a3db \| (1 << 11) //scale 2, size<1> check for D. #st1 {v30.d}[0], [x30] .inst 0x0d0087de \| (1 << 11) #st2 {v29.d, v30.d}[0], [x30] .inst 0x0d2087dd \| (1 << 11) #st3 {v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d00a7dc \| (1 << 11) #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d20a7db \| (1 << 11) //scale 2, S-bit check for D. #st1 {v30.d}[0], [x30] .inst 0x0d0087de \| (2 << 11) #st2 {v29.d, v30.d}[0], [x30] .inst 0x0d2087dd \| (2 << 11) #st3 {v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d00a7dc \| (2 << 11) #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d20a7db \| (2 << 11) //scale 2, size<1> & S-bit check for D. #st1 {v30.d}[0], [x30] .inst 0x0d0087de \| (3 << 11) #st2 {v29.d, v30.d}[0], [x30] .inst 0x0d2087dd \| (3 << 11) #st3 {v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d00a7dc \| (3 << 11) #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d20a7db \| (3 << 11)
stsp/binutils-ia16	2,178	binutils/testsuite/binutils-all/i386/compressed-1.s	.file "compressed-1.c" .section .debug_abbrev,"",@progbits .Ldebug_abbrev0: .section .debug_info,"",@progbits .Ldebug_info0: .section .debug_line,"",@progbits .Ldebug_line0: .text .Ltext0: .cfi_sections .debug_frame .p2align 4,,15 .globl foo2 .type foo2, @function foo2: .LFB1: .file 1 "compressed-1.c" .loc 1 11 0 .cfi_startproc .loc 1 12 0 rep ret .cfi_endproc .LFE1: .size foo2, .-foo2 .p2align 4,,15 .globl foo1 .type foo1, @function foo1: .LFB0: .loc 1 5 0 .cfi_startproc subl $12, %esp .cfi_def_cfa_offset 16 .loc 1 7 0 addl $12, %esp .cfi_def_cfa_offset 4 .loc 1 6 0 jmp bar .cfi_endproc .LFE0: .size foo1, .-foo1 .Letext0: .section .debug_info .long 0x46 .value 0x3 .long .Ldebug_abbrev0 .byte 0x4 .uleb128 0x1 .long .LASF2 .byte 0x1 .long .LASF3 .long .LASF4 .long .Ltext0 .long .Letext0 .long .Ldebug_line0 .uleb128 0x2 .byte 0x1 .long .LASF0 .byte 0x1 .byte 0xa .long .LFB1 .long .LFE1 .byte 0x1 .byte 0x9c .uleb128 0x2 .byte 0x1 .long .LASF1 .byte 0x1 .byte 0x4 .long .LFB0 .long .LFE0 .byte 0x1 .byte 0x9c .byte 0x0 .section .debug_abbrev .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0xe .uleb128 0x1b .uleb128 0xe .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x10 .uleb128 0x6 .byte 0x0 .byte 0x0 .uleb128 0x2 .uleb128 0x2e .byte 0x0 .uleb128 0x3f .uleb128 0xc .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x40 .uleb128 0xa .byte 0x0 .byte 0x0 .byte 0x0 .section .debug_pubnames,"",@progbits .long 0x20 .value 0x2 .long .Ldebug_info0 .long 0x4a .long 0x25 .string "foo2" .long 0x37 .string "foo1" .long 0x0 .section .debug_aranges,"",@progbits .long 0x1c .value 0x2 .long .Ldebug_info0 .byte 0x4 .byte 0x0 .value 0x0 .value 0x0 .long .Ltext0 .long .Letext0-.Ltext0 .long 0x0 .long 0x0 .section .debug_str,"MS",@progbits,1 .LASF2: .string "GNU C 4.4.4" .LASF0: .string "foo2" .LASF1: .string "foo1" .LASF4: .string "." .LASF3: .string "compressed-1.c"
stsp/binutils-ia16	1,299	binutils/testsuite/binutils-all/riscv/unknown.s	/* Copyright (C) 2021-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. / .text / The following instruction is in the area set aside for custom instruction extensions. As such it is unlikely that an upstream extension should ever clash with this. / .insn r 0x0b, 0x0, 0x0, x3, x4, x5 / Unlike the above, the following is just a reserved instruction encoding. This means that in the future an extension to the compressed instruction set might use this encoding. If/when that happens we'll need to find a different unused encoding within the compressed instruction space. */ .insn ca 0x1, 0x27, 0x2, x8, x9
stsp/binutils-ia16	1,494	binutils/testsuite/binutils-all/x86-64/pr23494a.s	.section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_X86_ISA_1_USED / .long 0xc0010002 / pr_type. / .long 5f - 4f / pr_datasz. / 4: .long 0xa 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f / name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_X86_ISA_1_NEEDED / .long 0xc0008002 / pr_type. / .long 5f - 4f / pr_datasz. / 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f / name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_X86_ISA_1_USED / .long 0xc0010002 / pr_type. / .long 5f - 4f / pr_datasz. */ 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3:
stsp/binutils-ia16	2,087	binutils/testsuite/binutils-all/x86-64/compressed-1.s	.file "compressed-1.c" .section .debug_abbrev,"",@progbits .Ldebug_abbrev0: .section .debug_info,"",@progbits .Ldebug_info0: .section .debug_line,"",@progbits .Ldebug_line0: .text .Ltext0: .cfi_sections .debug_frame .p2align 4,,15 .globl foo2 .type foo2, @function foo2: .LFB1: .file 1 "compressed-1.c" .loc 1 11 0 .cfi_startproc .loc 1 12 0 rep ret .cfi_endproc .LFE1: .size foo2, .-foo2 .p2align 4,,15 .globl foo1 .type foo1, @function foo1: .LFB0: .loc 1 5 0 .cfi_startproc .loc 1 6 0 jmp bar .cfi_endproc .LFE0: .size foo1, .-foo1 .Letext0: .section .debug_info .long 0x5e .value 0x3 .long .Ldebug_abbrev0 .byte 0x8 .uleb128 0x1 .long .LASF2 .byte 0x1 .long .LASF3 .long .LASF4 .quad .Ltext0 .quad .Letext0 .long .Ldebug_line0 .uleb128 0x2 .byte 0x1 .long .LASF0 .byte 0x1 .byte 0xa .quad .LFB1 .quad .LFE1 .byte 0x1 .byte 0x9c .uleb128 0x2 .byte 0x1 .long .LASF1 .byte 0x1 .byte 0x4 .quad .LFB0 .quad .LFE0 .byte 0x1 .byte 0x9c .byte 0x0 .section .debug_abbrev .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0xe .uleb128 0x1b .uleb128 0xe .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x10 .uleb128 0x6 .byte 0x0 .byte 0x0 .uleb128 0x2 .uleb128 0x2e .byte 0x0 .uleb128 0x3f .uleb128 0xc .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x40 .uleb128 0xa .byte 0x0 .byte 0x0 .byte 0x0 .section .debug_pubnames,"",@progbits .long 0x20 .value 0x2 .long .Ldebug_info0 .long 0x62 .long 0x2d .string "foo2" .long 0x47 .string "foo1" .long 0x0 .section .debug_aranges,"",@progbits .long 0x2c .value 0x2 .long .Ldebug_info0 .byte 0x8 .byte 0x0 .value 0x0 .value 0x0 .quad .Ltext0 .quad .Letext0-.Ltext0 .quad 0x0 .quad 0x0 .section .debug_str,"MS",@progbits,1 .LASF2: .string "GNU C 4.4.4" .LASF0: .string "foo2" .LASF1: .string "foo1" .LASF4: .string "." .LASF3: .string "compressed-1.c"
stsp/binutils-ia16	1,979	binutils/testsuite/binutils-all/x86-64/pr23494c.s	.section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_STACK_SIZE / .long 1 / pr_type. / .long 5f - 4f / pr_datasz. / 4: .dc.a -1 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f / name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_X86_ISA_1_USED / .long 0xc0010002 / pr_type. / .long 5f - 4f / pr_datasz. / 4: .long 0xa 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f / name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_X86_ISA_1_NEEDED / .long 0xc0008002 / pr_type. / .long 5f - 4f / pr_datasz. / 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f / name length. / .long 3f - 1f / data length. / / NT_GNU_PROPERTY_TYPE_0 / .long 5 / note type. / 0: .asciz "GNU" / vendor name. / 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif / GNU_PROPERTY_X86_ISA_1_USED / .long 0xc0010002 / pr_type. / .long 5f - 4f / pr_datasz. */ 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3:
stsp/binutils-ia16	42,842	zlib/contrib/inflate86/inffast.S	/* * inffast.S is a hand tuned assembler version of: * * inffast.c -- fast decoding * Copyright (C) 1995-2003 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h * * Copyright (C) 2003 Chris Anderson <christop@charm.net> * Please use the copyright conditions above. * * This version (Jan-23-2003) of inflate_fast was coded and tested under * GNU/Linux on a pentium 3, using the gcc-3.2 compiler distribution. On that * machine, I found that gzip style archives decompressed about 20% faster than * the gcc-3.2 -O3 -fomit-frame-pointer compiled version. Your results will * depend on how large of a buffer is used for z_stream.next_in & next_out * (8K-32K worked best for my 256K cpu cache) and how much overhead there is in * stream processing I/O and crc32/addler32. In my case, this routine used * 70% of the cpu time and crc32 used 20%. * * I am confident that this version will work in the general case, but I have * not tested a wide variety of datasets or a wide variety of platforms. * * Jan-24-2003 -- Added -DUSE_MMX define for slightly faster inflating. * It should be a runtime flag instead of compile time flag... * * Jan-26-2003 -- Added runtime check for MMX support with cpuid instruction. * With -DUSE_MMX, only MMX code is compiled. With -DNO_MMX, only non-MMX code * is compiled. Without either option, runtime detection is enabled. Runtime * detection should work on all modern cpus and the recomended algorithm (flip * ID bit on eflags and then use the cpuid instruction) is used in many * multimedia applications. Tested under win2k with gcc-2.95 and gas-2.12 * distributed with cygwin3. Compiling with gcc-2.95 -c inffast.S -o * inffast.obj generates a COFF object which can then be linked with MSVC++ * compiled code. Tested under FreeBSD 4.7 with gcc-2.95. * * Jan-28-2003 -- Tested Athlon XP... MMX mode is slower than no MMX (and * slower than compiler generated code). Adjusted cpuid check to use the MMX * code only for Pentiums < P4 until I have more data on the P4. Speed * improvment is only about 15% on the Athlon when compared with code generated * with MSVC++. Not sure yet, but I think the P4 will also be slower using the * MMX mode because many of it's x86 ALU instructions execute in .5 cycles and * have less latency than MMX ops. Added code to buffer the last 11 bytes of * the input stream since the MMX code grabs bits in chunks of 32, which * differs from the inffast.c algorithm. I don't think there would have been * read overruns where a page boundary was crossed (a segfault), but there * could have been overruns when next_in ends on unaligned memory (unintialized * memory read). * * Mar-13-2003 -- P4 MMX is slightly slower than P4 NO_MMX. I created a C * version of the non-MMX code so that it doesn't depend on zstrm and zstate * structure offsets which are hard coded in this file. This was last tested * with zlib-1.2.0 which is currently in beta testing, newer versions of this * and inffas86.c can be found at http://www.eetbeetee.com/zlib/ and * http://www.charm.net/~christop/zlib/ / / * if you have underscore linking problems (_inflate_fast undefined), try * using -DGAS_COFF / #if ! defined( GAS_COFF ) && ! defined( GAS_ELF ) #if defined( WIN32 ) \|\| defined( __CYGWIN__ ) #define GAS_COFF / windows object format / #else #define GAS_ELF #endif #endif / ! GAS_COFF && ! GAS_ELF / #if defined( GAS_COFF ) / coff externals have underscores / #define inflate_fast _inflate_fast #define inflate_fast_use_mmx _inflate_fast_use_mmx #endif / GAS_COFF / .file "inffast.S" .globl inflate_fast .text .align 4,0 .L_invalid_literal_length_code_msg: .string "invalid literal/length code" .align 4,0 .L_invalid_distance_code_msg: .string "invalid distance code" .align 4,0 .L_invalid_distance_too_far_msg: .string "invalid distance too far back" #if ! defined( NO_MMX ) .align 4,0 .L_mask: / mask[N] = ( 1 << N ) - 1 / .long 0 .long 1 .long 3 .long 7 .long 15 .long 31 .long 63 .long 127 .long 255 .long 511 .long 1023 .long 2047 .long 4095 .long 8191 .long 16383 .long 32767 .long 65535 .long 131071 .long 262143 .long 524287 .long 1048575 .long 2097151 .long 4194303 .long 8388607 .long 16777215 .long 33554431 .long 67108863 .long 134217727 .long 268435455 .long 536870911 .long 1073741823 .long 2147483647 .long 4294967295 #endif / NO_MMX / .text / * struct z_stream offsets, in zlib.h / #define next_in_strm 0 / strm->next_in / #define avail_in_strm 4 / strm->avail_in / #define next_out_strm 12 / strm->next_out / #define avail_out_strm 16 / strm->avail_out / #define msg_strm 24 / strm->msg / #define state_strm 28 / strm->state / / * struct inflate_state offsets, in inflate.h / #define mode_state 0 / state->mode / #define wsize_state 32 / state->wsize / #define write_state 40 / state->write / #define window_state 44 / state->window / #define hold_state 48 / state->hold / #define bits_state 52 / state->bits / #define lencode_state 68 / state->lencode / #define distcode_state 72 / state->distcode / #define lenbits_state 76 / state->lenbits / #define distbits_state 80 / state->distbits / / * inflate_fast's activation record / #define local_var_size 64 / how much local space for vars / #define strm_sp 88 / first arg: z_stream * (local_var_size + 24) / #define start_sp 92 / second arg: unsigned int (local_var_size + 28) / / * offsets for local vars on stack / #define out 60 / unsigned char* / #define window 56 / unsigned char* / #define wsize 52 / unsigned int / #define write 48 / unsigned int / #define in 44 / unsigned char* / #define beg 40 / unsigned char* / #define buf 28 / char[ 12 ] / #define len 24 / unsigned int / #define last 20 / unsigned char* / #define end 16 / unsigned char* / #define dcode 12 / code* / #define lcode 8 / code* / #define dmask 4 / unsigned int / #define lmask 0 / unsigned int / / * typedef enum inflate_mode consts, in inflate.h / #define INFLATE_MODE_TYPE 11 / state->mode flags enum-ed in inflate.h / #define INFLATE_MODE_BAD 26 #if ! defined( USE_MMX ) && ! defined( NO_MMX ) #define RUN_TIME_MMX #define CHECK_MMX 1 #define DO_USE_MMX 2 #define DONT_USE_MMX 3 .globl inflate_fast_use_mmx .data .align 4,0 inflate_fast_use_mmx: / integer flag for run time control 1=check,2=mmx,3=no / .long CHECK_MMX #if defined( GAS_ELF ) / elf info / .type inflate_fast_use_mmx,@object .size inflate_fast_use_mmx,4 #endif #endif / RUN_TIME_MMX / #if defined( GAS_COFF ) / coff info: scl 2 = extern, type 32 = function / .def inflate_fast; .scl 2; .type 32; .endef #endif .text .align 32,0x90 inflate_fast: pushl %edi pushl %esi pushl %ebp pushl %ebx pushf / save eflags (strm_sp, state_sp assumes this is 32 bits) / subl $local_var_size, %esp cld #define strm_r %esi #define state_r %edi movl strm_sp(%esp), strm_r movl state_strm(strm_r), state_r / in = strm->next_in; * out = strm->next_out; * last = in + strm->avail_in - 11; * beg = out - (start - strm->avail_out); * end = out + (strm->avail_out - 257); / movl avail_in_strm(strm_r), %edx movl next_in_strm(strm_r), %eax addl %eax, %edx / avail_in += next_in / subl $11, %edx / avail_in -= 11 / movl %eax, in(%esp) movl %edx, last(%esp) movl start_sp(%esp), %ebp movl avail_out_strm(strm_r), %ecx movl next_out_strm(strm_r), %ebx subl %ecx, %ebp / start -= avail_out / negl %ebp / start = -start / addl %ebx, %ebp / start += next_out / subl $257, %ecx / avail_out -= 257 / addl %ebx, %ecx / avail_out += out / movl %ebx, out(%esp) movl %ebp, beg(%esp) movl %ecx, end(%esp) / wsize = state->wsize; * write = state->write; * window = state->window; * hold = state->hold; * bits = state->bits; * lcode = state->lencode; * dcode = state->distcode; * lmask = ( 1 << state->lenbits ) - 1; * dmask = ( 1 << state->distbits ) - 1; / movl lencode_state(state_r), %eax movl distcode_state(state_r), %ecx movl %eax, lcode(%esp) movl %ecx, dcode(%esp) movl $1, %eax movl lenbits_state(state_r), %ecx shll %cl, %eax decl %eax movl %eax, lmask(%esp) movl $1, %eax movl distbits_state(state_r), %ecx shll %cl, %eax decl %eax movl %eax, dmask(%esp) movl wsize_state(state_r), %eax movl write_state(state_r), %ecx movl window_state(state_r), %edx movl %eax, wsize(%esp) movl %ecx, write(%esp) movl %edx, window(%esp) movl hold_state(state_r), %ebp movl bits_state(state_r), %ebx #undef strm_r #undef state_r #define in_r %esi #define from_r %esi #define out_r %edi movl in(%esp), in_r movl last(%esp), %ecx cmpl in_r, %ecx ja .L_align_long / if in < last / addl $11, %ecx / ecx = &in[ avail_in ] / subl in_r, %ecx / ecx = avail_in / movl $12, %eax subl %ecx, %eax / eax = 12 - avail_in / leal buf(%esp), %edi rep movsb / memcpy( buf, in, avail_in ) / movl %eax, %ecx xorl %eax, %eax rep stosb / memset( &buf[ avail_in ], 0, 12 - avail_in ) / leal buf(%esp), in_r / in = buf / movl in_r, last(%esp) / last = in, do just one iteration / jmp .L_is_aligned / align in_r on long boundary / .L_align_long: testl $3, in_r jz .L_is_aligned xorl %eax, %eax movb (in_r), %al incl in_r movl %ebx, %ecx addl $8, %ebx shll %cl, %eax orl %eax, %ebp jmp .L_align_long .L_is_aligned: movl out(%esp), out_r #if defined( NO_MMX ) jmp .L_do_loop #endif #if defined( USE_MMX ) jmp .L_init_mmx #endif / Runtime MMX check / #if defined( RUN_TIME_MMX ) .L_check_mmx: cmpl $DO_USE_MMX, inflate_fast_use_mmx je .L_init_mmx ja .L_do_loop / > 2 / pushl %eax pushl %ebx pushl %ecx pushl %edx pushf movl (%esp), %eax / copy eflags to eax / xorl $0x200000, (%esp) / try toggling ID bit of eflags (bit 21) * to see if cpu supports cpuid... * ID bit method not supported by NexGen but * bios may load a cpuid instruction and * cpuid may be disabled on Cyrix 5-6x86 / popf pushf popl %edx / copy new eflags to edx / xorl %eax, %edx / test if ID bit is flipped / jz .L_dont_use_mmx / not flipped if zero / xorl %eax, %eax cpuid cmpl $0x756e6547, %ebx / check for GenuineIntel in ebx,ecx,edx / jne .L_dont_use_mmx cmpl $0x6c65746e, %ecx jne .L_dont_use_mmx cmpl $0x49656e69, %edx jne .L_dont_use_mmx movl $1, %eax cpuid / get cpu features / shrl $8, %eax andl $15, %eax cmpl $6, %eax / check for Pentium family, is 0xf for P4 / jne .L_dont_use_mmx testl $0x800000, %edx / test if MMX feature is set (bit 23) / jnz .L_use_mmx jmp .L_dont_use_mmx .L_use_mmx: movl $DO_USE_MMX, inflate_fast_use_mmx jmp .L_check_mmx_pop .L_dont_use_mmx: movl $DONT_USE_MMX, inflate_fast_use_mmx .L_check_mmx_pop: popl %edx popl %ecx popl %ebx popl %eax jmp .L_check_mmx #endif / Non-MMX code / #if defined ( NO_MMX ) \|\| defined( RUN_TIME_MMX ) #define hold_r %ebp #define bits_r %bl #define bitslong_r %ebx .align 32,0x90 .L_while_test: / while (in < last && out < end) / cmpl out_r, end(%esp) jbe .L_break_loop / if (out >= end) / cmpl in_r, last(%esp) jbe .L_break_loop .L_do_loop: / regs: %esi = in, %ebp = hold, %bl = bits, %edi = out * * do { * if (bits < 15) { * hold \|= ((unsigned short )in)++ << bits; * bits += 16 * } * this = lcode[hold & lmask] / cmpb $15, bits_r ja .L_get_length_code / if (15 < bits) / xorl %eax, %eax lodsw / al = (ushort )in++ / movb bits_r, %cl / cl = bits, needs it for shifting / addb $16, bits_r / bits += 16 / shll %cl, %eax orl %eax, hold_r / hold \|= ((ushort )in)++ << bits / .L_get_length_code: movl lmask(%esp), %edx / edx = lmask / movl lcode(%esp), %ecx / ecx = lcode / andl hold_r, %edx / edx &= hold / movl (%ecx,%edx,4), %eax / eax = lcode[hold & lmask] / .L_dolen: / regs: %esi = in, %ebp = hold, %bl = bits, %edi = out * * dolen: * bits -= this.bits; * hold >>= this.bits / movb %ah, %cl / cl = this.bits / subb %ah, bits_r / bits -= this.bits / shrl %cl, hold_r / hold >>= this.bits / / check if op is a literal * if (op == 0) { * PUP(out) = this.val; * } / testb %al, %al jnz .L_test_for_length_base / if (op != 0) 45.7% / shrl $16, %eax / output this.val char / stosb jmp .L_while_test .L_test_for_length_base: / regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = len * * else if (op & 16) { * len = this.val * op &= 15 * if (op) { * if (op > bits) { * hold \|= ((unsigned short )in)++ << bits; * bits += 16 * } * len += hold & mask[op]; * bits -= op; * hold >>= op; * } / #define len_r %edx movl %eax, len_r / len = this / shrl $16, len_r / len = this.val / movb %al, %cl testb $16, %al jz .L_test_for_second_level_length / if ((op & 16) == 0) 8% / andb $15, %cl / op &= 15 / jz .L_save_len / if (!op) / cmpb %cl, bits_r jae .L_add_bits_to_len / if (op <= bits) / movb %cl, %ch / stash op in ch, freeing cl / xorl %eax, %eax lodsw / al = (ushort )in++ / movb bits_r, %cl / cl = bits, needs it for shifting / addb $16, bits_r / bits += 16 / shll %cl, %eax orl %eax, hold_r / hold \|= ((ushort )in)++ << bits / movb %ch, %cl / move op back to ecx / .L_add_bits_to_len: movl $1, %eax shll %cl, %eax decl %eax subb %cl, bits_r andl hold_r, %eax / eax &= hold / shrl %cl, hold_r addl %eax, len_r / len += hold & mask[op] / .L_save_len: movl len_r, len(%esp) / save len / #undef len_r .L_decode_distance: / regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = dist * * if (bits < 15) { * hold \|= ((unsigned short )in)++ << bits; * bits += 16 * } * this = dcode[hold & dmask]; * dodist: * bits -= this.bits; * hold >>= this.bits; * op = this.op; / cmpb $15, bits_r ja .L_get_distance_code / if (15 < bits) / xorl %eax, %eax lodsw / al = (ushort )in++ / movb bits_r, %cl / cl = bits, needs it for shifting / addb $16, bits_r / bits += 16 / shll %cl, %eax orl %eax, hold_r / hold \|= ((ushort )in)++ << bits / .L_get_distance_code: movl dmask(%esp), %edx / edx = dmask / movl dcode(%esp), %ecx / ecx = dcode / andl hold_r, %edx / edx &= hold / movl (%ecx,%edx,4), %eax / eax = dcode[hold & dmask] / #define dist_r %edx .L_dodist: movl %eax, dist_r / dist = this / shrl $16, dist_r / dist = this.val / movb %ah, %cl subb %ah, bits_r / bits -= this.bits / shrl %cl, hold_r / hold >>= this.bits / / if (op & 16) { * dist = this.val * op &= 15 * if (op > bits) { * hold \|= ((unsigned short )in)++ << bits; * bits += 16 * } * dist += hold & mask[op]; * bits -= op; * hold >>= op; / movb %al, %cl / cl = this.op / testb $16, %al / if ((op & 16) == 0) / jz .L_test_for_second_level_dist andb $15, %cl / op &= 15 / jz .L_check_dist_one cmpb %cl, bits_r jae .L_add_bits_to_dist / if (op <= bits) 97.6% / movb %cl, %ch / stash op in ch, freeing cl / xorl %eax, %eax lodsw / al = (ushort )in++ / movb bits_r, %cl / cl = bits, needs it for shifting / addb $16, bits_r / bits += 16 / shll %cl, %eax orl %eax, hold_r / hold \|= ((ushort )in)++ << bits / movb %ch, %cl / move op back to ecx / .L_add_bits_to_dist: movl $1, %eax shll %cl, %eax decl %eax / (1 << op) - 1 / subb %cl, bits_r andl hold_r, %eax / eax &= hold / shrl %cl, hold_r addl %eax, dist_r / dist += hold & ((1 << op) - 1) / jmp .L_check_window .L_check_window: / regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes * * nbytes = out - beg; * if (dist <= nbytes) { * from = out - dist; * do { * PUP(out) = PUP(from); * } while (--len > 0) { * } / movl in_r, in(%esp) / save in so from can use it's reg / movl out_r, %eax subl beg(%esp), %eax / nbytes = out - beg / cmpl dist_r, %eax jb .L_clip_window / if (dist > nbytes) 4.2% / movl len(%esp), %ecx movl out_r, from_r subl dist_r, from_r / from = out - dist / subl $3, %ecx movb (from_r), %al movb %al, (out_r) movb 1(from_r), %al movb 2(from_r), %dl addl $3, from_r movb %al, 1(out_r) movb %dl, 2(out_r) addl $3, out_r rep movsb movl in(%esp), in_r / move in back to %esi, toss from / jmp .L_while_test .align 16,0x90 .L_check_dist_one: cmpl $1, dist_r jne .L_check_window cmpl out_r, beg(%esp) je .L_check_window decl out_r movl len(%esp), %ecx movb (out_r), %al subl $3, %ecx movb %al, 1(out_r) movb %al, 2(out_r) movb %al, 3(out_r) addl $4, out_r rep stosb jmp .L_while_test .align 16,0x90 .L_test_for_second_level_length: / else if ((op & 64) == 0) { * this = lcode[this.val + (hold & mask[op])]; * } / testb $64, %al jnz .L_test_for_end_of_block / if ((op & 64) != 0) / movl $1, %eax shll %cl, %eax decl %eax andl hold_r, %eax / eax &= hold / addl %edx, %eax / eax += this.val / movl lcode(%esp), %edx / edx = lcode / movl (%edx,%eax,4), %eax / eax = lcode[val + (hold&mask[op])] / jmp .L_dolen .align 16,0x90 .L_test_for_second_level_dist: / else if ((op & 64) == 0) { * this = dcode[this.val + (hold & mask[op])]; * } / testb $64, %al jnz .L_invalid_distance_code / if ((op & 64) != 0) / movl $1, %eax shll %cl, %eax decl %eax andl hold_r, %eax / eax &= hold / addl %edx, %eax / eax += this.val / movl dcode(%esp), %edx / edx = dcode / movl (%edx,%eax,4), %eax / eax = dcode[val + (hold&mask[op])] / jmp .L_dodist .align 16,0x90 .L_clip_window: / regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes * * else { * if (dist > wsize) { * invalid distance * } * from = window; * nbytes = dist - nbytes; * if (write == 0) { * from += wsize - nbytes; / #define nbytes_r %ecx movl %eax, nbytes_r movl wsize(%esp), %eax / prepare for dist compare / negl nbytes_r / nbytes = -nbytes / movl window(%esp), from_r / from = window / cmpl dist_r, %eax jb .L_invalid_distance_too_far / if (dist > wsize) / addl dist_r, nbytes_r / nbytes = dist - nbytes / cmpl $0, write(%esp) jne .L_wrap_around_window / if (write != 0) / subl nbytes_r, %eax addl %eax, from_r / from += wsize - nbytes / / regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes, %eax = len * * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while (--nbytes); * from = out - dist; * } * } / #define len_r %eax movl len(%esp), len_r cmpl nbytes_r, len_r jbe .L_do_copy1 / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / jmp .L_do_copy1 cmpl nbytes_r, len_r jbe .L_do_copy1 / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / jmp .L_do_copy1 .L_wrap_around_window: / regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes, %eax = write, %eax = len * * else if (write < nbytes) { * from += wsize + write - nbytes; * nbytes -= write; * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while (--nbytes); * from = window; * nbytes = write; * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while(--nbytes); * from = out - dist; * } * } * } / #define write_r %eax movl write(%esp), write_r cmpl write_r, nbytes_r jbe .L_contiguous_in_window / if (write >= nbytes) / addl wsize(%esp), from_r addl write_r, from_r subl nbytes_r, from_r / from += wsize + write - nbytes / subl write_r, nbytes_r / nbytes -= write / #undef write_r movl len(%esp), len_r cmpl nbytes_r, len_r jbe .L_do_copy1 / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl window(%esp), from_r / from = window / movl write(%esp), nbytes_r / nbytes = write / cmpl nbytes_r, len_r jbe .L_do_copy1 / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / jmp .L_do_copy1 .L_contiguous_in_window: / regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes, %eax = write, %eax = len * * else { * from += write - nbytes; * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while (--nbytes); * from = out - dist; * } * } / #define write_r %eax addl write_r, from_r subl nbytes_r, from_r / from += write - nbytes / #undef write_r movl len(%esp), len_r cmpl nbytes_r, len_r jbe .L_do_copy1 / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / .L_do_copy1: / regs: %esi = from, %esi = in, %ebp = hold, %bl = bits, %edi = out * %eax = len * * while (len > 0) { * PUP(out) = PUP(from); * len--; * } * } * } while (in < last && out < end); / #undef nbytes_r #define in_r %esi movl len_r, %ecx rep movsb movl in(%esp), in_r / move in back to %esi, toss from / jmp .L_while_test #undef len_r #undef dist_r #endif / NO_MMX \|\| RUN_TIME_MMX / / MMX code / #if defined( USE_MMX ) \|\| defined( RUN_TIME_MMX ) .align 32,0x90 .L_init_mmx: emms #undef bits_r #undef bitslong_r #define bitslong_r %ebp #define hold_mm %mm0 movd %ebp, hold_mm movl %ebx, bitslong_r #define used_mm %mm1 #define dmask2_mm %mm2 #define lmask2_mm %mm3 #define lmask_mm %mm4 #define dmask_mm %mm5 #define tmp_mm %mm6 movd lmask(%esp), lmask_mm movq lmask_mm, lmask2_mm movd dmask(%esp), dmask_mm movq dmask_mm, dmask2_mm pxor used_mm, used_mm movl lcode(%esp), %ebx / ebx = lcode / jmp .L_do_loop_mmx .align 32,0x90 .L_while_test_mmx: / while (in < last && out < end) / cmpl out_r, end(%esp) jbe .L_break_loop / if (out >= end) / cmpl in_r, last(%esp) jbe .L_break_loop .L_do_loop_mmx: psrlq used_mm, hold_mm / hold_mm >>= last bit length / cmpl $32, bitslong_r ja .L_get_length_code_mmx / if (32 < bits) / movd bitslong_r, tmp_mm movd (in_r), %mm7 addl $4, in_r psllq tmp_mm, %mm7 addl $32, bitslong_r por %mm7, hold_mm / hold_mm \|= ((uint )in)++ << bits / .L_get_length_code_mmx: pand hold_mm, lmask_mm movd lmask_mm, %eax movq lmask2_mm, lmask_mm movl (%ebx,%eax,4), %eax / eax = lcode[hold & lmask] / .L_dolen_mmx: movzbl %ah, %ecx / ecx = this.bits / movd %ecx, used_mm subl %ecx, bitslong_r / bits -= this.bits / testb %al, %al jnz .L_test_for_length_base_mmx / if (op != 0) 45.7% / shrl $16, %eax / output this.val char / stosb jmp .L_while_test_mmx .L_test_for_length_base_mmx: #define len_r %edx movl %eax, len_r / len = this / shrl $16, len_r / len = this.val / testb $16, %al jz .L_test_for_second_level_length_mmx / if ((op & 16) == 0) 8% / andl $15, %eax / op &= 15 / jz .L_decode_distance_mmx / if (!op) / psrlq used_mm, hold_mm / hold_mm >>= last bit length / movd %eax, used_mm movd hold_mm, %ecx subl %eax, bitslong_r andl .L_mask(,%eax,4), %ecx addl %ecx, len_r / len += hold & mask[op] / .L_decode_distance_mmx: psrlq used_mm, hold_mm / hold_mm >>= last bit length / cmpl $32, bitslong_r ja .L_get_dist_code_mmx / if (32 < bits) / movd bitslong_r, tmp_mm movd (in_r), %mm7 addl $4, in_r psllq tmp_mm, %mm7 addl $32, bitslong_r por %mm7, hold_mm / hold_mm \|= ((uint )in)++ << bits / .L_get_dist_code_mmx: movl dcode(%esp), %ebx / ebx = dcode / pand hold_mm, dmask_mm movd dmask_mm, %eax movq dmask2_mm, dmask_mm movl (%ebx,%eax,4), %eax / eax = dcode[hold & lmask] / .L_dodist_mmx: #define dist_r %ebx movzbl %ah, %ecx / ecx = this.bits / movl %eax, dist_r shrl $16, dist_r / dist = this.val / subl %ecx, bitslong_r / bits -= this.bits / movd %ecx, used_mm testb $16, %al / if ((op & 16) == 0) / jz .L_test_for_second_level_dist_mmx andl $15, %eax / op &= 15 / jz .L_check_dist_one_mmx .L_add_bits_to_dist_mmx: psrlq used_mm, hold_mm / hold_mm >>= last bit length / movd %eax, used_mm / save bit length of current op / movd hold_mm, %ecx / get the next bits on input stream / subl %eax, bitslong_r / bits -= op bits / andl .L_mask(,%eax,4), %ecx / ecx = hold & mask[op] / addl %ecx, dist_r / dist += hold & mask[op] / .L_check_window_mmx: movl in_r, in(%esp) / save in so from can use it's reg / movl out_r, %eax subl beg(%esp), %eax / nbytes = out - beg / cmpl dist_r, %eax jb .L_clip_window_mmx / if (dist > nbytes) 4.2% / movl len_r, %ecx movl out_r, from_r subl dist_r, from_r / from = out - dist / subl $3, %ecx movb (from_r), %al movb %al, (out_r) movb 1(from_r), %al movb 2(from_r), %dl addl $3, from_r movb %al, 1(out_r) movb %dl, 2(out_r) addl $3, out_r rep movsb movl in(%esp), in_r / move in back to %esi, toss from / movl lcode(%esp), %ebx / move lcode back to %ebx, toss dist / jmp .L_while_test_mmx .align 16,0x90 .L_check_dist_one_mmx: cmpl $1, dist_r jne .L_check_window_mmx cmpl out_r, beg(%esp) je .L_check_window_mmx decl out_r movl len_r, %ecx movb (out_r), %al subl $3, %ecx movb %al, 1(out_r) movb %al, 2(out_r) movb %al, 3(out_r) addl $4, out_r rep stosb movl lcode(%esp), %ebx / move lcode back to %ebx, toss dist / jmp .L_while_test_mmx .align 16,0x90 .L_test_for_second_level_length_mmx: testb $64, %al jnz .L_test_for_end_of_block / if ((op & 64) != 0) / andl $15, %eax psrlq used_mm, hold_mm / hold_mm >>= last bit length / movd hold_mm, %ecx andl .L_mask(,%eax,4), %ecx addl len_r, %ecx movl (%ebx,%ecx,4), %eax / eax = lcode[hold & lmask] / jmp .L_dolen_mmx .align 16,0x90 .L_test_for_second_level_dist_mmx: testb $64, %al jnz .L_invalid_distance_code / if ((op & 64) != 0) / andl $15, %eax psrlq used_mm, hold_mm / hold_mm >>= last bit length / movd hold_mm, %ecx andl .L_mask(,%eax,4), %ecx movl dcode(%esp), %eax / ecx = dcode / addl dist_r, %ecx movl (%eax,%ecx,4), %eax / eax = lcode[hold & lmask] / jmp .L_dodist_mmx .align 16,0x90 .L_clip_window_mmx: #define nbytes_r %ecx movl %eax, nbytes_r movl wsize(%esp), %eax / prepare for dist compare / negl nbytes_r / nbytes = -nbytes / movl window(%esp), from_r / from = window / cmpl dist_r, %eax jb .L_invalid_distance_too_far / if (dist > wsize) / addl dist_r, nbytes_r / nbytes = dist - nbytes / cmpl $0, write(%esp) jne .L_wrap_around_window_mmx / if (write != 0) / subl nbytes_r, %eax addl %eax, from_r / from += wsize - nbytes / cmpl nbytes_r, len_r jbe .L_do_copy1_mmx / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / jmp .L_do_copy1_mmx cmpl nbytes_r, len_r jbe .L_do_copy1_mmx / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / jmp .L_do_copy1_mmx .L_wrap_around_window_mmx: #define write_r %eax movl write(%esp), write_r cmpl write_r, nbytes_r jbe .L_contiguous_in_window_mmx / if (write >= nbytes) / addl wsize(%esp), from_r addl write_r, from_r subl nbytes_r, from_r / from += wsize + write - nbytes / subl write_r, nbytes_r / nbytes -= write / #undef write_r cmpl nbytes_r, len_r jbe .L_do_copy1_mmx / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl window(%esp), from_r / from = window / movl write(%esp), nbytes_r / nbytes = write / cmpl nbytes_r, len_r jbe .L_do_copy1_mmx / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / jmp .L_do_copy1_mmx .L_contiguous_in_window_mmx: #define write_r %eax addl write_r, from_r subl nbytes_r, from_r / from += write - nbytes / #undef write_r cmpl nbytes_r, len_r jbe .L_do_copy1_mmx / if (nbytes >= len) / subl nbytes_r, len_r / len -= nbytes / rep movsb movl out_r, from_r subl dist_r, from_r / from = out - dist / .L_do_copy1_mmx: #undef nbytes_r #define in_r %esi movl len_r, %ecx rep movsb movl in(%esp), in_r / move in back to %esi, toss from / movl lcode(%esp), %ebx / move lcode back to %ebx, toss dist / jmp .L_while_test_mmx #undef hold_r #undef bitslong_r #endif / USE_MMX \|\| RUN_TIME_MMX / / USE_MMX, NO_MMX, and RUNTIME_MMX from here on / .L_invalid_distance_code: / else { * strm->msg = "invalid distance code"; * state->mode = BAD; * } / movl $.L_invalid_distance_code_msg, %ecx movl $INFLATE_MODE_BAD, %edx jmp .L_update_stream_state .L_test_for_end_of_block: / else if (op & 32) { * state->mode = TYPE; * break; * } / testb $32, %al jz .L_invalid_literal_length_code / if ((op & 32) == 0) / movl $0, %ecx movl $INFLATE_MODE_TYPE, %edx jmp .L_update_stream_state .L_invalid_literal_length_code: / else { * strm->msg = "invalid literal/length code"; * state->mode = BAD; * } / movl $.L_invalid_literal_length_code_msg, %ecx movl $INFLATE_MODE_BAD, %edx jmp .L_update_stream_state .L_invalid_distance_too_far: / strm->msg = "invalid distance too far back"; * state->mode = BAD; / movl in(%esp), in_r / from_r has in's reg, put in back / movl $.L_invalid_distance_too_far_msg, %ecx movl $INFLATE_MODE_BAD, %edx jmp .L_update_stream_state .L_update_stream_state: / set strm->msg = %ecx, strm->state->mode = %edx / movl strm_sp(%esp), %eax testl %ecx, %ecx / if (msg != NULL) / jz .L_skip_msg movl %ecx, msg_strm(%eax) / strm->msg = msg / .L_skip_msg: movl state_strm(%eax), %eax / state = strm->state / movl %edx, mode_state(%eax) / state->mode = edx (BAD \| TYPE) / jmp .L_break_loop .align 32,0x90 .L_break_loop: / * Regs: * * bits = %ebp when mmx, and in %ebx when non-mmx * hold = %hold_mm when mmx, and in %ebp when non-mmx * in = %esi * out = %edi / #if defined( USE_MMX ) \|\| defined( RUN_TIME_MMX ) #if defined( RUN_TIME_MMX ) cmpl $DO_USE_MMX, inflate_fast_use_mmx jne .L_update_next_in #endif / RUN_TIME_MMX / movl %ebp, %ebx .L_update_next_in: #endif #define strm_r %eax #define state_r %edx / len = bits >> 3; * in -= len; * bits -= len << 3; * hold &= (1U << bits) - 1; * state->hold = hold; * state->bits = bits; * strm->next_in = in; * strm->next_out = out; / movl strm_sp(%esp), strm_r movl %ebx, %ecx movl state_strm(strm_r), state_r shrl $3, %ecx subl %ecx, in_r shll $3, %ecx subl %ecx, %ebx movl out_r, next_out_strm(strm_r) movl %ebx, bits_state(state_r) movl %ebx, %ecx leal buf(%esp), %ebx cmpl %ebx, last(%esp) jne .L_buf_not_used / if buf != last / subl %ebx, in_r / in -= buf / movl next_in_strm(strm_r), %ebx movl %ebx, last(%esp) / last = strm->next_in / addl %ebx, in_r / in += strm->next_in / movl avail_in_strm(strm_r), %ebx subl $11, %ebx addl %ebx, last(%esp) / last = &strm->next_in[ avail_in - 11 ] / .L_buf_not_used: movl in_r, next_in_strm(strm_r) movl $1, %ebx shll %cl, %ebx decl %ebx #if defined( USE_MMX ) \|\| defined( RUN_TIME_MMX ) #if defined( RUN_TIME_MMX ) cmpl $DO_USE_MMX, inflate_fast_use_mmx jne .L_update_hold #endif / RUN_TIME_MMX / psrlq used_mm, hold_mm / hold_mm >>= last bit length / movd hold_mm, %ebp emms .L_update_hold: #endif / USE_MMX \|\| RUN_TIME_MMX / andl %ebx, %ebp movl %ebp, hold_state(state_r) #define last_r %ebx / strm->avail_in = in < last ? 11 + (last - in) : 11 - (in - last) / movl last(%esp), last_r cmpl in_r, last_r jbe .L_last_is_smaller / if (in >= last) / subl in_r, last_r / last -= in / addl $11, last_r / last += 11 / movl last_r, avail_in_strm(strm_r) jmp .L_fixup_out .L_last_is_smaller: subl last_r, in_r / in -= last / negl in_r / in = -in / addl $11, in_r / in += 11 / movl in_r, avail_in_strm(strm_r) #undef last_r #define end_r %ebx .L_fixup_out: / strm->avail_out = out < end ? 257 + (end - out) : 257 - (out - end)/ movl end(%esp), end_r cmpl out_r, end_r jbe .L_end_is_smaller / if (out >= end) / subl out_r, end_r / end -= out / addl $257, end_r / end += 257 / movl end_r, avail_out_strm(strm_r) jmp .L_done .L_end_is_smaller: subl end_r, out_r / out -= end / negl out_r / out = -out / addl $257, out_r / out += 257 / movl out_r, avail_out_strm(strm_r) #undef end_r #undef strm_r #undef state_r .L_done: addl $local_var_size, %esp popf popl %ebx popl %ebp popl %esi popl %edi ret #if defined( GAS_ELF ) / elf info */ .type inflate_fast,@function .size inflate_fast,.-inflate_fast #endif
stsp/binutils-ia16	15,839	zlib/contrib/gcc_gvmat64/gvmat64.S	/* ;uInt longest_match_x64( ; deflate_state s, ; IPos cur_match); // current match ; gvmat64.S -- Asm portion of the optimized longest_match for 32 bits x86_64 ; (AMD64 on Athlon 64, Opteron, Phenom ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7) ; this file is translation from gvmat64.asm to GCC 4.x (for Linux, Mac XCode) ; Copyright (C) 1995-2010 Jean-loup Gailly, Brian Raiter and Gilles Vollant. ; ; File written by Gilles Vollant, by converting to assembly the longest_match ; from Jean-loup Gailly in deflate.c of zLib and infoZip zip. ; and by taking inspiration on asm686 with masm, optimised assembly code ; from Brian Raiter, written 1998 ; ; This software is provided 'as-is', without any express or implied ; warranty. In no event will the authors be held liable for any damages ; arising from the use of this software. ; ; Permission is granted to anyone to use this software for any purpose, ; including commercial applications, and to alter it and redistribute it ; freely, subject to the following restrictions: ; ; 1. The origin of this software must not be misrepresented; you must not ; claim that you wrote the original software. If you use this software ; in a product, an acknowledgment in the product documentation would be ; appreciated but is not required. ; 2. Altered source versions must be plainly marked as such, and must not be ; misrepresented as being the original software ; 3. This notice may not be removed or altered from any source distribution. ; ; http://www.zlib.net ; http://www.winimage.com/zLibDll ; http://www.muppetlabs.com/~breadbox/software/assembly.html ; ; to compile this file for zLib, I use option: ; gcc -c -arch x86_64 gvmat64.S ;uInt longest_match(s, cur_match) ; deflate_state s; ; IPos cur_match; // current match / ; ; with XCode for Mac, I had strange error with some jump on intel syntax ; this is why BEFORE_JMP and AFTER_JMP are used / #define BEFORE_JMP .att_syntax #define AFTER_JMP .intel_syntax noprefix #ifndef NO_UNDERLINE # define match_init _match_init # define longest_match _longest_match #endif .intel_syntax noprefix .globl match_init, longest_match .text longest_match: #define LocalVarsSize 96 / ; register used : rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12 ; free register : r14,r15 ; register can be saved : rsp / #define chainlenwmask (rsp + 8 - LocalVarsSize) #define nicematch (rsp + 16 - LocalVarsSize) #define save_rdi (rsp + 24 - LocalVarsSize) #define save_rsi (rsp + 32 - LocalVarsSize) #define save_rbx (rsp + 40 - LocalVarsSize) #define save_rbp (rsp + 48 - LocalVarsSize) #define save_r12 (rsp + 56 - LocalVarsSize) #define save_r13 (rsp + 64 - LocalVarsSize) #define save_r14 (rsp + 72 - LocalVarsSize) #define save_r15 (rsp + 80 - LocalVarsSize) / ; all the +4 offsets are due to the addition of pending_buf_size (in zlib ; in the deflate_state structure since the asm code was first written ; (if you compile with zlib 1.0.4 or older, remove the +4). ; Note : these value are good with a 8 bytes boundary pack structure / #define MAX_MATCH 258 #define MIN_MATCH 3 #define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1) / ;;; Offsets for fields in the deflate_state structure. These numbers ;;; are calculated from the definition of deflate_state, with the ;;; assumption that the compiler will dword-align the fields. (Thus, ;;; changing the definition of deflate_state could easily cause this ;;; program to crash horribly, without so much as a warning at ;;; compile time. Sigh.) ; all the +zlib1222add offsets are due to the addition of fields ; in zlib in the deflate_state structure since the asm code was first written ; (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)"). ; (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0"). ; if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8"). / / you can check the structure offset by running #include <stdlib.h> #include <stdio.h> #include "deflate.h" void print_depl() { deflate_state ds; deflate_state s=&ds; printf("size pointer=%u\n",(int)sizeof(void)); printf("#define dsWSize %u\n",(int)(((char)&(s->w_size))-((char)s))); printf("#define dsWMask %u\n",(int)(((char)&(s->w_mask))-((char)s))); printf("#define dsWindow %u\n",(int)(((char)&(s->window))-((char)s))); printf("#define dsPrev %u\n",(int)(((char)&(s->prev))-((char)s))); printf("#define dsMatchLen %u\n",(int)(((char)&(s->match_length))-((char)s))); printf("#define dsPrevMatch %u\n",(int)(((char)&(s->prev_match))-((char)s))); printf("#define dsStrStart %u\n",(int)(((char)&(s->strstart))-((char)s))); printf("#define dsMatchStart %u\n",(int)(((char)&(s->match_start))-((char)s))); printf("#define dsLookahead %u\n",(int)(((char)&(s->lookahead))-((char)s))); printf("#define dsPrevLen %u\n",(int)(((char)&(s->prev_length))-((char)s))); printf("#define dsMaxChainLen %u\n",(int)(((char)&(s->max_chain_length))-((char)s))); printf("#define dsGoodMatch %u\n",(int)(((char)&(s->good_match))-((char)s))); printf("#define dsNiceMatch %u\n",(int)(((char)&(s->nice_match))-((char)s))); } / #define dsWSize 68 #define dsWMask 76 #define dsWindow 80 #define dsPrev 96 #define dsMatchLen 144 #define dsPrevMatch 148 #define dsStrStart 156 #define dsMatchStart 160 #define dsLookahead 164 #define dsPrevLen 168 #define dsMaxChainLen 172 #define dsGoodMatch 188 #define dsNiceMatch 192 #define window_size [ rcx + dsWSize] #define WMask [ rcx + dsWMask] #define window_ad [ rcx + dsWindow] #define prev_ad [ rcx + dsPrev] #define strstart [ rcx + dsStrStart] #define match_start [ rcx + dsMatchStart] #define Lookahead [ rcx + dsLookahead] //; 0ffffffffh on infozip #define prev_length [ rcx + dsPrevLen] #define max_chain_length [ rcx + dsMaxChainLen] #define good_match [ rcx + dsGoodMatch] #define nice_match [ rcx + dsNiceMatch] / ; windows: ; parameter 1 in rcx(deflate state s), param 2 in rdx (cur match) ; see http://weblogs.asp.net/oldnewthing/archive/2004/01/14/58579.aspx and ; http://msdn.microsoft.com/library/en-us/kmarch/hh/kmarch/64bitAMD_8e951dd2-ee77-4728-8702-55ce4b5dd24a.xml.asp ; ; All registers must be preserved across the call, except for ; rax, rcx, rdx, r8, r9, r10, and r11, which are scratch. ; ; gcc on macosx-linux: ; see http://www.x86-64.org/documentation/abi-0.99.pdf ; param 1 in rdi, param 2 in rsi ; rbx, rsp, rbp, r12 to r15 must be preserved ;;; Save registers that the compiler may be using, and adjust esp to ;;; make room for our stack frame. ;;; Retrieve the function arguments. r8d will hold cur_match ;;; throughout the entire function. edx will hold the pointer to the ;;; deflate_state structure during the function's setup (before ;;; entering the main loop. ; ms: parameter 1 in rcx (deflate_state* s), param 2 in edx -> r8 (cur match) ; mac: param 1 in rdi, param 2 rsi ; this clear high 32 bits of r8, which can be garbage in both r8 and rdx / mov [save_rbx],rbx mov [save_rbp],rbp mov rcx,rdi mov r8d,esi mov [save_r12],r12 mov [save_r13],r13 mov [save_r14],r14 mov [save_r15],r15 //;;; uInt wmask = s->w_mask; //;;; unsigned chain_length = s->max_chain_length; //;;; if (s->prev_length >= s->good_match) { //;;; chain_length >>= 2; //;;; } mov edi, prev_length mov esi, good_match mov eax, WMask mov ebx, max_chain_length cmp edi, esi jl LastMatchGood shr ebx, 2 LastMatchGood: //;;; chainlen is decremented once beforehand so that the function can //;;; use the sign flag instead of the zero flag for the exit test. //;;; It is then shifted into the high word, to make room for the wmask //;;; value, which it will always accompany. dec ebx shl ebx, 16 or ebx, eax //;;; on zlib only //;;; if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; mov eax, nice_match mov [chainlenwmask], ebx mov r10d, Lookahead cmp r10d, eax cmovnl r10d, eax mov [nicematch],r10d //;;; register Bytef scan = s->window + s->strstart; mov r10, window_ad mov ebp, strstart lea r13, [r10 + rbp] //;;; Determine how many bytes the scan ptr is off from being //;;; dword-aligned. mov r9,r13 neg r13 and r13,3 //;;; IPos limit = s->strstart > (IPos)MAX_DIST(s) ? //;;; s->strstart - (IPos)MAX_DIST(s) : NIL; mov eax, window_size sub eax, MIN_LOOKAHEAD xor edi,edi sub ebp, eax mov r11d, prev_length cmovng ebp,edi //;;; int best_len = s->prev_length; //;;; Store the sum of s->window + best_len in esi locally, and in esi. lea rsi,[r10+r11] //;;; register ush scan_start = (ushf)scan; //;;; register ush scan_end = (ushf)(scan+best_len-1); //;;; Posf prev = s->prev; movzx r12d,word ptr [r9] movzx ebx, word ptr [r9 + r11 - 1] mov rdi, prev_ad //;;; Jump into the main loop. mov edx, [chainlenwmask] cmp bx,word ptr [rsi + r8 - 1] jz LookupLoopIsZero LookupLoop1: and r8d, edx movzx r8d, word ptr [rdi + r82] cmp r8d, ebp jbe LeaveNow sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry1: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jz LookupLoopIsZero AFTER_JMP LookupLoop2: and r8d, edx movzx r8d, word ptr [rdi + r82] cmp r8d, ebp BEFORE_JMP jbe LeaveNow AFTER_JMP sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry2: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jz LookupLoopIsZero AFTER_JMP LookupLoop4: and r8d, edx movzx r8d, word ptr [rdi + r82] cmp r8d, ebp BEFORE_JMP jbe LeaveNow AFTER_JMP sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry4: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jnz LookupLoop1 jmp LookupLoopIsZero AFTER_JMP /* ;;; do { ;;; match = s->window + cur_match; ;;; if ((ushf)(match+best_len-1) != scan_end \|\| ;;; (ushf)match != scan_start) continue; ;;; [...] ;;; } while ((cur_match = prev[cur_match & wmask]) > limit ;;; && --chain_length != 0); ;;; ;;; Here is the inner loop of the function. The function will spend the ;;; majority of its time in this loop, and majority of that time will ;;; be spent in the first ten instructions. ;;; ;;; Within this loop: ;;; ebx = scanend ;;; r8d = curmatch ;;; edx = chainlenwmask - i.e., ((chainlen << 16) \| wmask) ;;; esi = windowbestlen - i.e., (window + bestlen) ;;; edi = prev ;;; ebp = limit / .balign 16 LookupLoop: and r8d, edx movzx r8d, word ptr [rdi + r82] cmp r8d, ebp BEFORE_JMP jbe LeaveNow AFTER_JMP sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jnz LookupLoop1 AFTER_JMP LookupLoopIsZero: cmp r12w, word ptr [r10 + r8] BEFORE_JMP jnz LookupLoop1 AFTER_JMP //;;; Store the current value of chainlen. mov [chainlenwmask], edx /* ;;; Point edi to the string under scrutiny, and esi to the string we ;;; are hoping to match it up with. In actuality, esi and edi are ;;; both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and edx is ;;; initialized to -(MAX_MATCH_8 - scanalign). / lea rsi,[r8+r10] mov rdx, 0xfffffffffffffef8 //; -(MAX_MATCH_8) lea rsi, [rsi + r13 + 0x0108] //;MAX_MATCH_8] lea rdi, [r9 + r13 + 0x0108] //;MAX_MATCH_8] prefetcht1 [rsi+rdx] prefetcht1 [rdi+rdx] / ;;; Test the strings for equality, 8 bytes at a time. At the end, ;;; adjust rdx so that it is offset to the exact byte that mismatched. ;;; ;;; We already know at this point that the first three bytes of the ;;; strings match each other, and they can be safely passed over before ;;; starting the compare loop. So what this code does is skip over 0-3 ;;; bytes, as much as necessary in order to dword-align the edi ;;; pointer. (rsi will still be misaligned three times out of four.) ;;; ;;; It should be confessed that this loop usually does not represent ;;; much of the total running time. Replacing it with a more ;;; straightforward "rep cmpsb" would not drastically degrade ;;; performance. / LoopCmps: mov rax, [rsi + rdx] xor rax, [rdi + rdx] jnz LeaveLoopCmps mov rax, [rsi + rdx + 8] xor rax, [rdi + rdx + 8] jnz LeaveLoopCmps8 mov rax, [rsi + rdx + 8+8] xor rax, [rdi + rdx + 8+8] jnz LeaveLoopCmps16 add rdx,8+8+8 BEFORE_JMP jnz LoopCmps jmp LenMaximum AFTER_JMP LeaveLoopCmps16: add rdx,8 LeaveLoopCmps8: add rdx,8 LeaveLoopCmps: test eax, 0x0000FFFF jnz LenLower test eax,0xffffffff jnz LenLower32 add rdx,4 shr rax,32 or ax,ax BEFORE_JMP jnz LenLower AFTER_JMP LenLower32: shr eax,16 add rdx,2 LenLower: sub al, 1 adc rdx, 0 //;;; Calculate the length of the match. If it is longer than MAX_MATCH, //;;; then automatically accept it as the best possible match and leave. lea rax, [rdi + rdx] sub rax, r9 cmp eax, MAX_MATCH BEFORE_JMP jge LenMaximum AFTER_JMP / ;;; If the length of the match is not longer than the best match we ;;; have so far, then forget it and return to the lookup loop. ;/////////////////////////////////// / cmp eax, r11d jg LongerMatch lea rsi,[r10+r11] mov rdi, prev_ad mov edx, [chainlenwmask] BEFORE_JMP jmp LookupLoop AFTER_JMP / ;;; s->match_start = cur_match; ;;; best_len = len; ;;; if (len >= nice_match) break; ;;; scan_end = (ushf)(scan+best_len-1); */ LongerMatch: mov r11d, eax mov match_start, r8d cmp eax, [nicematch] BEFORE_JMP jge LeaveNow AFTER_JMP lea rsi,[r10+rax] movzx ebx, word ptr [r9 + rax - 1] mov rdi, prev_ad mov edx, [chainlenwmask] BEFORE_JMP jmp LookupLoop AFTER_JMP //;;; Accept the current string, with the maximum possible length. LenMaximum: mov r11d,MAX_MATCH mov match_start, r8d //;;; if ((uInt)best_len <= s->lookahead) return (uInt)best_len; //;;; return s->lookahead; LeaveNow: mov eax, Lookahead cmp r11d, eax cmovng eax, r11d //;;; Restore the stack and return from whence we came. // mov rsi,[save_rsi] // mov rdi,[save_rdi] mov rbx,[save_rbx] mov rbp,[save_rbp] mov r12,[save_r12] mov r13,[save_r13] mov r14,[save_r14] mov r15,[save_r15] ret 0 //; please don't remove this string ! //; Your can freely use gvmat64 in any free or commercial app //; but it is far better don't remove the string in the binary! // db 0dh,0ah,"asm686 with masm, optimised assembly code from Brian Raiter, written 1998, converted to amd 64 by Gilles Vollant 2005",0dh,0ah,0 match_init: ret 0
stsp/binutils-ia16	12,418	zlib/contrib/amd64/amd64-match.S	/* * match.S -- optimized version of longest_match() * based on the similar work by Gilles Vollant, and Brian Raiter, written 1998 * * This is free software; you can redistribute it and/or modify it * under the terms of the BSD License. Use by owners of Che Guevarra * parafernalia is prohibited, where possible, and highly discouraged * elsewhere. / #ifndef NO_UNDERLINE # define match_init _match_init # define longest_match _longest_match #endif #define scanend ebx #define scanendw bx #define chainlenwmask edx / high word: current chain len low word: s->wmask / #define curmatch rsi #define curmatchd esi #define windowbestlen r8 #define scanalign r9 #define scanalignd r9d #define window r10 #define bestlen r11 #define bestlend r11d #define scanstart r12d #define scanstartw r12w #define scan r13 #define nicematch r14d #define limit r15 #define limitd r15d #define prev rcx / * The 258 is a "magic number, not a parameter -- changing it * breaks the hell loose / #define MAX_MATCH (258) #define MIN_MATCH (3) #define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1) #define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7) / stack frame offsets / #define LocalVarsSize (112) #define _chainlenwmask ( 8-LocalVarsSize)(%rsp) #define _windowbestlen (16-LocalVarsSize)(%rsp) #define save_r14 (24-LocalVarsSize)(%rsp) #define save_rsi (32-LocalVarsSize)(%rsp) #define save_rbx (40-LocalVarsSize)(%rsp) #define save_r12 (56-LocalVarsSize)(%rsp) #define save_r13 (64-LocalVarsSize)(%rsp) #define save_r15 (80-LocalVarsSize)(%rsp) .globl match_init, longest_match / * On AMD64 the first argument of a function (in our case -- the pointer to * deflate_state structure) is passed in %rdi, hence our offsets below are * all off of that. / / you can check the structure offset by running #include <stdlib.h> #include <stdio.h> #include "deflate.h" void print_depl() { deflate_state ds; deflate_state s=&ds; printf("size pointer=%u\n",(int)sizeof(void)); printf("#define dsWSize (%3u)(%%rdi)\n",(int)(((char)&(s->w_size))-((char)s))); printf("#define dsWMask (%3u)(%%rdi)\n",(int)(((char)&(s->w_mask))-((char)s))); printf("#define dsWindow (%3u)(%%rdi)\n",(int)(((char)&(s->window))-((char)s))); printf("#define dsPrev (%3u)(%%rdi)\n",(int)(((char)&(s->prev))-((char)s))); printf("#define dsMatchLen (%3u)(%%rdi)\n",(int)(((char)&(s->match_length))-((char)s))); printf("#define dsPrevMatch (%3u)(%%rdi)\n",(int)(((char)&(s->prev_match))-((char)s))); printf("#define dsStrStart (%3u)(%%rdi)\n",(int)(((char)&(s->strstart))-((char)s))); printf("#define dsMatchStart (%3u)(%%rdi)\n",(int)(((char)&(s->match_start))-((char)s))); printf("#define dsLookahead (%3u)(%%rdi)\n",(int)(((char)&(s->lookahead))-((char)s))); printf("#define dsPrevLen (%3u)(%%rdi)\n",(int)(((char)&(s->prev_length))-((char)s))); printf("#define dsMaxChainLen (%3u)(%%rdi)\n",(int)(((char)&(s->max_chain_length))-((char)s))); printf("#define dsGoodMatch (%3u)(%%rdi)\n",(int)(((char)&(s->good_match))-((char)s))); printf("#define dsNiceMatch (%3u)(%%rdi)\n",(int)(((char)&(s->nice_match))-((char)s))); } / / to compile for XCode 3.2 on MacOSX x86_64 - run "gcc -g -c -DXCODE_MAC_X64_STRUCTURE amd64-match.S" / #ifndef CURRENT_LINX_XCODE_MAC_X64_STRUCTURE #define dsWSize ( 68)(%rdi) #define dsWMask ( 76)(%rdi) #define dsWindow ( 80)(%rdi) #define dsPrev ( 96)(%rdi) #define dsMatchLen (144)(%rdi) #define dsPrevMatch (148)(%rdi) #define dsStrStart (156)(%rdi) #define dsMatchStart (160)(%rdi) #define dsLookahead (164)(%rdi) #define dsPrevLen (168)(%rdi) #define dsMaxChainLen (172)(%rdi) #define dsGoodMatch (188)(%rdi) #define dsNiceMatch (192)(%rdi) #else #ifndef STRUCT_OFFSET # define STRUCT_OFFSET (0) #endif #define dsWSize ( 56 + STRUCT_OFFSET)(%rdi) #define dsWMask ( 64 + STRUCT_OFFSET)(%rdi) #define dsWindow ( 72 + STRUCT_OFFSET)(%rdi) #define dsPrev ( 88 + STRUCT_OFFSET)(%rdi) #define dsMatchLen (136 + STRUCT_OFFSET)(%rdi) #define dsPrevMatch (140 + STRUCT_OFFSET)(%rdi) #define dsStrStart (148 + STRUCT_OFFSET)(%rdi) #define dsMatchStart (152 + STRUCT_OFFSET)(%rdi) #define dsLookahead (156 + STRUCT_OFFSET)(%rdi) #define dsPrevLen (160 + STRUCT_OFFSET)(%rdi) #define dsMaxChainLen (164 + STRUCT_OFFSET)(%rdi) #define dsGoodMatch (180 + STRUCT_OFFSET)(%rdi) #define dsNiceMatch (184 + STRUCT_OFFSET)(%rdi) #endif .text / uInt longest_match(deflate_state deflatestate, IPos curmatch) / longest_match: /* * Retrieve the function arguments. %curmatch will hold cur_match * throughout the entire function (passed via rsi on amd64). * rdi will hold the pointer to the deflate_state (first arg on amd64) / mov %rsi, save_rsi mov %rbx, save_rbx mov %r12, save_r12 mov %r13, save_r13 mov %r14, save_r14 mov %r15, save_r15 / uInt wmask = s->w_mask; / / unsigned chain_length = s->max_chain_length; / / if (s->prev_length >= s->good_match) { / / chain_length >>= 2; / / } / movl dsPrevLen, %eax movl dsGoodMatch, %ebx cmpl %ebx, %eax movl dsWMask, %eax movl dsMaxChainLen, %chainlenwmask jl LastMatchGood shrl $2, %chainlenwmask LastMatchGood: / chainlen is decremented once beforehand so that the function can / / use the sign flag instead of the zero flag for the exit test. / / It is then shifted into the high word, to make room for the wmask / / value, which it will always accompany. / decl %chainlenwmask shll $16, %chainlenwmask orl %eax, %chainlenwmask / if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; / movl dsNiceMatch, %eax movl dsLookahead, %ebx cmpl %eax, %ebx jl LookaheadLess movl %eax, %ebx LookaheadLess: movl %ebx, %nicematch / register Bytef scan = s->window + s->strstart; / mov dsWindow, %window movl dsStrStart, %limitd lea (%limit, %window), %scan /* Determine how many bytes the scan ptr is off from being / / dword-aligned. / mov %scan, %scanalign negl %scanalignd andl $3, %scanalignd / IPos limit = s->strstart > (IPos)MAX_DIST(s) ? / / s->strstart - (IPos)MAX_DIST(s) : NIL; / movl dsWSize, %eax subl $MIN_LOOKAHEAD, %eax xorl %ecx, %ecx subl %eax, %limitd cmovng %ecx, %limitd / int best_len = s->prev_length; / movl dsPrevLen, %bestlend / Store the sum of s->window + best_len in %windowbestlen locally, and in memory. / lea (%window, %bestlen), %windowbestlen mov %windowbestlen, _windowbestlen / register ush scan_start = (ushf)scan; / / register ush scan_end = (ushf)(scan+best_len-1); / / Posf prev = s->prev; / movzwl (%scan), %scanstart movzwl -1(%scan, %bestlen), %scanend mov dsPrev, %prev /* Jump into the main loop. / movl %chainlenwmask, _chainlenwmask jmp LoopEntry .balign 16 / do { * match = s->window + cur_match; * if ((ushf)(match+best_len-1) != scan_end \|\| * (ushf)match != scan_start) continue; * [...] * } while ((cur_match = prev[cur_match & wmask]) > limit * && --chain_length != 0); * * Here is the inner loop of the function. The function will spend the * majority of its time in this loop, and majority of that time will * be spent in the first ten instructions. / LookupLoop: andl %chainlenwmask, %curmatchd movzwl (%prev, %curmatch, 2), %curmatchd cmpl %limitd, %curmatchd jbe LeaveNow subl $0x00010000, %chainlenwmask js LeaveNow LoopEntry: cmpw -1(%windowbestlen, %curmatch), %scanendw jne LookupLoop cmpw %scanstartw, (%window, %curmatch) jne LookupLoop / Store the current value of chainlen. / movl %chainlenwmask, _chainlenwmask / %scan is the string under scrutiny, and %prev to the string we / / are hoping to match it up with. In actuality, %esi and %edi are / / both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is / / initialized to -(MAX_MATCH_8 - scanalign). / mov $(-MAX_MATCH_8), %rdx lea (%curmatch, %window), %windowbestlen lea MAX_MATCH_8(%windowbestlen, %scanalign), %windowbestlen lea MAX_MATCH_8(%scan, %scanalign), %prev / the prefetching below makes very little difference... / prefetcht1 (%windowbestlen, %rdx) prefetcht1 (%prev, %rdx) / * Test the strings for equality, 8 bytes at a time. At the end, * adjust %rdx so that it is offset to the exact byte that mismatched. * * It should be confessed that this loop usually does not represent * much of the total running time. Replacing it with a more * straightforward "rep cmpsb" would not drastically degrade * performance -- unrolling it, for example, makes no difference. / #undef USE_SSE / works, but is 6-7% slower, than non-SSE... / LoopCmps: #ifdef USE_SSE / Preload the SSE registers / movdqu (%windowbestlen, %rdx), %xmm1 movdqu (%prev, %rdx), %xmm2 pcmpeqb %xmm2, %xmm1 movdqu 16(%windowbestlen, %rdx), %xmm3 movdqu 16(%prev, %rdx), %xmm4 pcmpeqb %xmm4, %xmm3 movdqu 32(%windowbestlen, %rdx), %xmm5 movdqu 32(%prev, %rdx), %xmm6 pcmpeqb %xmm6, %xmm5 movdqu 48(%windowbestlen, %rdx), %xmm7 movdqu 48(%prev, %rdx), %xmm8 pcmpeqb %xmm8, %xmm7 / Check the comparisions' results / pmovmskb %xmm1, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps / this is the only iteration of the loop with a possibility of having incremented rdx by 0x108 (each loop iteration add 164 = 0x40 and (0x404)+8=0x108 / add $8, %rdx jz LenMaximum add $8, %rdx pmovmskb %xmm3, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps add $16, %rdx pmovmskb %xmm5, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps add $16, %rdx pmovmskb %xmm7, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps add $16, %rdx jmp LoopCmps LeaveLoopCmps: add %rax, %rdx #else mov (%windowbestlen, %rdx), %rax xor (%prev, %rdx), %rax jnz LeaveLoopCmps mov 8(%windowbestlen, %rdx), %rax xor 8(%prev, %rdx), %rax jnz LeaveLoopCmps8 mov 16(%windowbestlen, %rdx), %rax xor 16(%prev, %rdx), %rax jnz LeaveLoopCmps16 add $24, %rdx jnz LoopCmps jmp LenMaximum # if 0 / * This three-liner is tantalizingly simple, but bsf is a slow instruction, * and the complicated alternative down below is quite a bit faster. Sad... / LeaveLoopCmps: bsf %rax, %rax / find the first non-zero bit / shrl $3, %eax / divide by 8 to get the byte / add %rax, %rdx # else LeaveLoopCmps16: add $8, %rdx LeaveLoopCmps8: add $8, %rdx LeaveLoopCmps: testl $0xFFFFFFFF, %eax / Check the first 4 bytes / jnz Check16 add $4, %rdx shr $32, %rax Check16: testw $0xFFFF, %ax jnz LenLower add $2, %rdx shrl $16, %eax LenLower: subb $1, %al adc $0, %rdx # endif #endif / Calculate the length of the match. If it is longer than MAX_MATCH, / / then automatically accept it as the best possible match and leave. / lea (%prev, %rdx), %rax sub %scan, %rax cmpl $MAX_MATCH, %eax jge LenMaximum / If the length of the match is not longer than the best match we / / have so far, then forget it and return to the lookup loop. / cmpl %bestlend, %eax jg LongerMatch mov _windowbestlen, %windowbestlen mov dsPrev, %prev movl _chainlenwmask, %edx jmp LookupLoop / s->match_start = cur_match; / / best_len = len; / / if (len >= nice_match) break; / / scan_end = (ushf)(scan+best_len-1); / LongerMatch: movl %eax, %bestlend movl %curmatchd, dsMatchStart cmpl %nicematch, %eax jge LeaveNow lea (%window, %bestlen), %windowbestlen mov %windowbestlen, _windowbestlen movzwl -1(%scan, %rax), %scanend mov dsPrev, %prev movl _chainlenwmask, %chainlenwmask jmp LookupLoop / Accept the current string, with the maximum possible length. / LenMaximum: movl $MAX_MATCH, %bestlend movl %curmatchd, dsMatchStart / if ((uInt)best_len <= s->lookahead) return (uInt)best_len; / / return s->lookahead; / LeaveNow: movl dsLookahead, %eax cmpl %eax, %bestlend cmovngl %bestlend, %eax LookaheadRet: / Restore the registers and return from whence we came. */ mov save_rsi, %rsi mov save_rbx, %rbx mov save_r12, %r12 mov save_r13, %r13 mov save_r14, %r14 mov save_r15, %r15 ret match_init: ret
stsp/binutils-ia16	10,365	zlib/contrib/asm686/match.S	/* match.S -- x86 assembly version of the zlib longest_match() function. * Optimized for the Intel 686 chips (PPro and later). * * Copyright (C) 1998, 2007 Brian Raiter <breadbox@muppetlabs.com> * * This software is provided 'as-is', without any express or implied * warranty. In no event will the author be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. / #ifndef NO_UNDERLINE #define match_init _match_init #define longest_match _longest_match #endif #define MAX_MATCH (258) #define MIN_MATCH (3) #define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1) #define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7) / stack frame offsets / #define chainlenwmask 0 / high word: current chain len / / low word: s->wmask / #define window 4 / local copy of s->window / #define windowbestlen 8 / s->window + bestlen / #define scanstart 16 / first two bytes of string / #define scanend 12 / last two bytes of string / #define scanalign 20 / dword-misalignment of string / #define nicematch 24 / a good enough match size / #define bestlen 28 / size of best match so far / #define scan 32 / ptr to string wanting match / #define LocalVarsSize (36) / saved ebx 36 / / saved edi 40 / / saved esi 44 / / saved ebp 48 / / return address 52 / #define deflatestate 56 / the function arguments / #define curmatch 60 / All the +zlib1222add offsets are due to the addition of fields * in zlib in the deflate_state structure since the asm code was first written * (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)"). * (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0"). * if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8"). / #define zlib1222add (8) #define dsWSize (36+zlib1222add) #define dsWMask (44+zlib1222add) #define dsWindow (48+zlib1222add) #define dsPrev (56+zlib1222add) #define dsMatchLen (88+zlib1222add) #define dsPrevMatch (92+zlib1222add) #define dsStrStart (100+zlib1222add) #define dsMatchStart (104+zlib1222add) #define dsLookahead (108+zlib1222add) #define dsPrevLen (112+zlib1222add) #define dsMaxChainLen (116+zlib1222add) #define dsGoodMatch (132+zlib1222add) #define dsNiceMatch (136+zlib1222add) .file "match.S" .globl match_init, longest_match .text / uInt longest_match(deflate_state deflatestate, IPos curmatch) / .cfi_sections .debug_frame longest_match: .cfi_startproc /* Save registers that the compiler may be using, and adjust %esp to / / make room for our stack frame. / pushl %ebp .cfi_def_cfa_offset 8 .cfi_offset ebp, -8 pushl %edi .cfi_def_cfa_offset 12 pushl %esi .cfi_def_cfa_offset 16 pushl %ebx .cfi_def_cfa_offset 20 subl $LocalVarsSize, %esp .cfi_def_cfa_offset LocalVarsSize+20 / Retrieve the function arguments. %ecx will hold cur_match / / throughout the entire function. %edx will hold the pointer to the / / deflate_state structure during the function's setup (before / / entering the main loop). / movl deflatestate(%esp), %edx movl curmatch(%esp), %ecx / uInt wmask = s->w_mask; / / unsigned chain_length = s->max_chain_length; / / if (s->prev_length >= s->good_match) { / / chain_length >>= 2; / / } / movl dsPrevLen(%edx), %eax movl dsGoodMatch(%edx), %ebx cmpl %ebx, %eax movl dsWMask(%edx), %eax movl dsMaxChainLen(%edx), %ebx jl LastMatchGood shrl $2, %ebx LastMatchGood: / chainlen is decremented once beforehand so that the function can / / use the sign flag instead of the zero flag for the exit test. / / It is then shifted into the high word, to make room for the wmask / / value, which it will always accompany. / decl %ebx shll $16, %ebx orl %eax, %ebx movl %ebx, chainlenwmask(%esp) / if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; / movl dsNiceMatch(%edx), %eax movl dsLookahead(%edx), %ebx cmpl %eax, %ebx jl LookaheadLess movl %eax, %ebx LookaheadLess: movl %ebx, nicematch(%esp) / register Bytef scan = s->window + s->strstart; / movl dsWindow(%edx), %esi movl %esi, window(%esp) movl dsStrStart(%edx), %ebp lea (%esi,%ebp), %edi movl %edi, scan(%esp) /* Determine how many bytes the scan ptr is off from being / / dword-aligned. / movl %edi, %eax negl %eax andl $3, %eax movl %eax, scanalign(%esp) / IPos limit = s->strstart > (IPos)MAX_DIST(s) ? / / s->strstart - (IPos)MAX_DIST(s) : NIL; / movl dsWSize(%edx), %eax subl $MIN_LOOKAHEAD, %eax subl %eax, %ebp jg LimitPositive xorl %ebp, %ebp LimitPositive: / int best_len = s->prev_length; / movl dsPrevLen(%edx), %eax movl %eax, bestlen(%esp) / Store the sum of s->window + best_len in %esi locally, and in %esi. / addl %eax, %esi movl %esi, windowbestlen(%esp) / register ush scan_start = (ushf)scan; / / register ush scan_end = (ushf)(scan+best_len-1); / / Posf prev = s->prev; / movzwl (%edi), %ebx movl %ebx, scanstart(%esp) movzwl -1(%edi,%eax), %ebx movl %ebx, scanend(%esp) movl dsPrev(%edx), %edi /* Jump into the main loop. / movl chainlenwmask(%esp), %edx jmp LoopEntry .balign 16 / do { * match = s->window + cur_match; * if ((ushf)(match+best_len-1) != scan_end \|\| * (ushf)match != scan_start) continue; * [...] * } while ((cur_match = prev[cur_match & wmask]) > limit * && --chain_length != 0); * * Here is the inner loop of the function. The function will spend the * majority of its time in this loop, and majority of that time will * be spent in the first ten instructions. * * Within this loop: * %ebx = scanend * %ecx = curmatch * %edx = chainlenwmask - i.e., ((chainlen << 16) \| wmask) * %esi = windowbestlen - i.e., (window + bestlen) * %edi = prev * %ebp = limit / LookupLoop: andl %edx, %ecx movzwl (%edi,%ecx,2), %ecx cmpl %ebp, %ecx jbe LeaveNow subl $0x00010000, %edx js LeaveNow LoopEntry: movzwl -1(%esi,%ecx), %eax cmpl %ebx, %eax jnz LookupLoop movl window(%esp), %eax movzwl (%eax,%ecx), %eax cmpl scanstart(%esp), %eax jnz LookupLoop / Store the current value of chainlen. / movl %edx, chainlenwmask(%esp) / Point %edi to the string under scrutiny, and %esi to the string we / / are hoping to match it up with. In actuality, %esi and %edi are / / both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is / / initialized to -(MAX_MATCH_8 - scanalign). / movl window(%esp), %esi movl scan(%esp), %edi addl %ecx, %esi movl scanalign(%esp), %eax movl $(-MAX_MATCH_8), %edx lea MAX_MATCH_8(%edi,%eax), %edi lea MAX_MATCH_8(%esi,%eax), %esi / Test the strings for equality, 8 bytes at a time. At the end, * adjust %edx so that it is offset to the exact byte that mismatched. * * We already know at this point that the first three bytes of the * strings match each other, and they can be safely passed over before * starting the compare loop. So what this code does is skip over 0-3 * bytes, as much as necessary in order to dword-align the %edi * pointer. (%esi will still be misaligned three times out of four.) * * It should be confessed that this loop usually does not represent * much of the total running time. Replacing it with a more * straightforward "rep cmpsb" would not drastically degrade * performance. / LoopCmps: movl (%esi,%edx), %eax xorl (%edi,%edx), %eax jnz LeaveLoopCmps movl 4(%esi,%edx), %eax xorl 4(%edi,%edx), %eax jnz LeaveLoopCmps4 addl $8, %edx jnz LoopCmps jmp LenMaximum LeaveLoopCmps4: addl $4, %edx LeaveLoopCmps: testl $0x0000FFFF, %eax jnz LenLower addl $2, %edx shrl $16, %eax LenLower: subb $1, %al adcl $0, %edx / Calculate the length of the match. If it is longer than MAX_MATCH, / / then automatically accept it as the best possible match and leave. / lea (%edi,%edx), %eax movl scan(%esp), %edi subl %edi, %eax cmpl $MAX_MATCH, %eax jge LenMaximum / If the length of the match is not longer than the best match we / / have so far, then forget it and return to the lookup loop. / movl deflatestate(%esp), %edx movl bestlen(%esp), %ebx cmpl %ebx, %eax jg LongerMatch movl windowbestlen(%esp), %esi movl dsPrev(%edx), %edi movl scanend(%esp), %ebx movl chainlenwmask(%esp), %edx jmp LookupLoop / s->match_start = cur_match; / / best_len = len; / / if (len >= nice_match) break; / / scan_end = (ushf)(scan+best_len-1); / LongerMatch: movl nicematch(%esp), %ebx movl %eax, bestlen(%esp) movl %ecx, dsMatchStart(%edx) cmpl %ebx, %eax jge LeaveNow movl window(%esp), %esi addl %eax, %esi movl %esi, windowbestlen(%esp) movzwl -1(%edi,%eax), %ebx movl dsPrev(%edx), %edi movl %ebx, scanend(%esp) movl chainlenwmask(%esp), %edx jmp LookupLoop / Accept the current string, with the maximum possible length. / LenMaximum: movl deflatestate(%esp), %edx movl $MAX_MATCH, bestlen(%esp) movl %ecx, dsMatchStart(%edx) / if ((uInt)best_len <= s->lookahead) return (uInt)best_len; / / return s->lookahead; / LeaveNow: movl deflatestate(%esp), %edx movl bestlen(%esp), %ebx movl dsLookahead(%edx), %eax cmpl %eax, %ebx jg LookaheadRet movl %ebx, %eax LookaheadRet: / Restore the stack and return from whence we came. */ addl $LocalVarsSize, %esp .cfi_def_cfa_offset 20 popl %ebx .cfi_def_cfa_offset 16 popl %esi .cfi_def_cfa_offset 12 popl %edi .cfi_def_cfa_offset 8 popl %ebp .cfi_def_cfa_offset 4 .cfi_endproc match_init: ret
stsp/binutils-ia16	10,965	ld/emultempl/spu_ovl.S	/* Overlay manager for SPU. Copyright (C) 2006-2022 Free Software Foundation, Inc. This file is part of the GNU Binutils. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. / / MFC DMA defn's. / #define MFC_GET_CMD 0x40 #define MFC_MAX_DMA_SIZE 0x4000 #define MFC_TAG_UPDATE_ALL 2 #define MFC_TAG_ID 0 / Register usage. / #define reserved1 $75 #define parm $75 #define tab1 reserved1 #define tab2 reserved1 #define vma reserved1 #define oldvma reserved1 #define newmask reserved1 #define map reserved1 #define reserved2 $76 #define off1 reserved2 #define off2 reserved2 #define present1 reserved2 #define present2 reserved2 #define sz reserved2 #define cmp reserved2 #define add64 reserved2 #define cgbits reserved2 #define off3 reserved2 #define off4 reserved2 #define addr4 reserved2 #define off5 reserved2 #define tagstat reserved2 #define reserved3 $77 #define size1 reserved3 #define size2 reserved3 #define rv3 reserved3 #define ealo reserved3 #define cmd reserved3 #define off64 reserved3 #define tab3 reserved3 #define tab4 reserved3 #define tab5 reserved3 #define reserved4 $78 #define ovl reserved4 #define rv2 reserved4 #define rv5 reserved4 #define cgshuf reserved4 #define newovl reserved4 #define irqtmp1 reserved4 #define irqtmp2 reserved4 #define reserved5 $79 #define target reserved5 #define save1 $74 #define rv4 save1 #define rv7 save1 #define tagid save1 #define maxsize save1 #define pbyte save1 #define pbit save1 #define save2 $73 #define cur save2 #define rv6 save2 #define osize save2 #define zovl save2 #define oldovl save2 #define newvma save2 #define save3 $72 #define rv1 save3 #define ea64 save3 #define buf3 save3 #define genwi save3 #define newmap save3 #define oldmask save3 #define save4 $71 #define irq_stat save4 .text .align 4 .type __rv_pattern, @object .size __rv_pattern, 16 __rv_pattern: .word 0x00010203, 0x10111213, 0x80808080, 0x80808080 .type __cg_pattern, @object .size __cg_pattern, 16 __cg_pattern: .word 0x04050607, 0x80808080, 0x80808080, 0x80808080 .type __ovly_current, @object .size __ovly_current, 16 __ovly_current: .space 16 / * __ovly_return - stub for returning from overlay functions. * * On entry the four slots of $lr are: * __ovly_return, prev ovl index, caller return addr, undefined. * * Load the previous overlay and jump to the caller return address. * Updates __ovly_current. / .align 4 .global __ovly_return .type __ovly_return, @function __ovly_return: ila tab1, _ovly_table - 16 # 0,2 0 shlqbyi ovl, $lr, 4 # 1,4 0 #nop shlqbyi target, $lr, 8 # 1,4 1 #nop; lnop #nop; lnop shli off1, ovl, 4 # 0,4 4 #lnop #nop hbr ovly_ret9, target # 1,15 5 #nop; lnop #nop; lnop #nop lqx vma, tab1, off1 # 1,6 8 #ifdef OVLY_IRQ_SAVE nop stqd save4, -64($sp) # 1,6 9 #else #nop; lnop #endif #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop rotqbyi size1, vma, 4 # 1,4 14 #nop stqd save3, -48($sp) # 1,6 15 #nop stqd save2, -32($sp) # 1,6 16 #nop stqd save1, -16($sp) # 1,6 17 andi present1, size1, 1 # 0,2 18 stqr ovl, __ovly_current # 1,6 18 #nop; lnop #nop brz present1, do_load # 1,4 20 ovly_ret9: #nop bi target # 1,4 21 / * __ovly_load - copy an overlay partion to local store. * * On entry $75 points to a word consisting of the overlay index in * the top 14 bits, and the target address in the bottom 18 bits. * * Sets up $lr to return via __ovly_return. If $lr is already set * to return via __ovly_return, don't change it. In that case we * have a tail call from one overlay function to another. * Updates __ovly_current. / .align 3 .global __ovly_load .type __ovly_load, @function __ovly_load: #if OVL_STUB_SIZE == 8 ######## #nop lqd target, 0(parm) # 1,6 -11 #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop rotqby target, target, parm # 1,4 -5 ila tab2, _ovly_table - 16 # 0,2 -4 stqd save3, -48($sp) # 1,6 -4 #nop stqd save2, -32($sp) # 1,6 -3 #nop stqd save1, -16($sp) # 1,6 -2 rotmi ovl, target, -18 # 0,4 -1 hbr ovly_load9, target # 1,15 -1 ila rv1, __ovly_return # 0,2 0 #lnop #nop; lnop #nop lqr cur, __ovly_current # 1,6 2 shli off2, ovl, 4 # 0,4 3 stqr ovl, __ovly_current # 1,6 3 ceq rv2, $lr, rv1 # 0,2 4 lqr rv3, __rv_pattern # 1,6 4 #nop; lnop #nop; lnop #nop lqx vma, tab2, off2 # 1,6 7 ######## #else / OVL_STUB_SIZE == 16 / ######## ila tab2, _ovly_table - 16 # 0,2 0 stqd save3, -48($sp) # 1,6 0 ila rv1, __ovly_return # 0,2 1 stqd save2, -32($sp) # 1,6 1 shli off2, ovl, 4 # 0,4 2 lqr cur, __ovly_current # 1,6 2 nop stqr ovl, __ovly_current # 1,6 3 ceq rv2, $lr, rv1 # 0,2 4 lqr rv3, __rv_pattern # 1,6 4 #nop hbr ovly_load9, target # 1,15 5 #nop lqx vma, tab2, off2 # 1,6 6 #nop stqd save1, -16($sp) # 1,6 7 ######## #endif #nop; lnop #nop; lnop #nop shufb rv4, rv1, cur, rv3 # 1,4 10 #nop fsmb rv5, rv2 # 1,4 11 #nop rotqmbyi rv6, $lr, -8 # 1,4 12 #nop rotqbyi size2, vma, 4 # 1,4 13 #nop lqd save3, -48($sp) # 1,6 14 #nop; lnop or rv7, rv4, rv6 # 0,2 16 lqd save2, -32($sp) # 1,6 16 andi present2, size2, 1 # 0,2 17 #ifdef OVLY_IRQ_SAVE stqd save4, -64($sp) # 1,6 17 #else lnop # 1,0 17 #endif selb $lr, rv7, $lr, rv5 # 0,2 18 lqd save1, -16($sp) # 1,6 18 #nop brz present2, do_load # 1,4 19 ovly_load9: #nop bi target # 1,4 20 / If we get here, we are about to load a new overlay. * "vma" contains the relevant entry from _ovly_table[]. * extern struct { * u32 vma; * u32 size; * u32 file_offset; * u32 buf; * } _ovly_table[]; / .align 3 .global __ovly_load_event .type __ovly_load_event, @function __ovly_load_event: do_load: #ifdef OVLY_IRQ_SAVE ila irqtmp1, do_load10 # 0,2 -5 rotqbyi sz, vma, 8 # 1,4 -5 #nop rdch irq_stat, $SPU_RdMachStat # 1,6 -4 #nop bid irqtmp1 # 1,4 -3 do_load10: nop #else #nop rotqbyi sz, vma, 8 # 1,4 0 #endif rotqbyi osize, vma, 4 # 1,4 1 #nop lqa ea64, _EAR_ # 1,6 2 #nop lqr cgshuf, __cg_pattern # 1,6 3 / We could predict the branch at the end of this loop by adding a few instructions, and there are plenty of free cycles to do so without impacting loop execution time. However, it doesn't make a great deal of sense since we need to wait for the dma to complete anyway. / __ovly_xfer_loop: #nop rotqmbyi off64, sz, -4 # 1,4 4 #nop; lnop #nop; lnop #nop; lnop cg cgbits, ea64, off64 # 0,2 8 #lnop #nop; lnop #nop shufb add64, cgbits, cgbits, cgshuf # 1,4 10 #nop; lnop #nop; lnop #nop; lnop addx add64, ea64, off64 # 0,2 14 #lnop ila maxsize, MFC_MAX_DMA_SIZE # 0,2 15 lnop ori ea64, add64, 0 # 0,2 16 rotqbyi ealo, add64, 4 # 1,4 16 cgt cmp, osize, maxsize # 0,2 17 wrch $MFC_LSA, vma # 1,6 17 #nop; lnop selb sz, osize, maxsize, cmp # 0,2 19 wrch $MFC_EAH, ea64 # 1,6 19 ila tagid, MFC_TAG_ID # 0,2 20 wrch $MFC_EAL, ealo # 1,6 20 ila cmd, MFC_GET_CMD # 0,2 21 wrch $MFC_Size, sz # 1,6 21 sf osize, sz, osize # 0,2 22 wrch $MFC_TagId, tagid # 1,6 22 a vma, vma, sz # 0,2 23 wrch $MFC_Cmd, cmd # 1,6 23 #nop brnz osize, __ovly_xfer_loop # 1,4 24 / Now update our data structions while waiting for DMA to complete. Low bit of .size needs to be cleared on the _ovly_table entry corresponding to the evicted overlay, and set on the entry for the newly loaded overlay. Note that no overlay may in fact be evicted as _ovly_buf_table[] starts with all zeros. Don't zap .size entry for zero index! Also of course update the _ovly_buf_table entry. / #nop lqr newovl, __ovly_current # 1,6 25 #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop; lnop shli off3, newovl, 4 # 0,4 31 #lnop ila tab3, _ovly_table - 16 # 0,2 32 #lnop #nop fsmbi pbyte, 0x100 # 1,4 33 #nop; lnop #nop lqx vma, tab3, off3 # 1,6 35 #nop; lnop andi pbit, pbyte, 1 # 0,2 37 lnop #nop; lnop #nop; lnop #nop; lnop or newvma, vma, pbit # 0,2 41 rotqbyi buf3, vma, 12 # 1,4 41 #nop; lnop #nop stqx newvma, tab3, off3 # 1,6 43 #nop; lnop shli off4, buf3, 2 # 1,4 45 #lnop ila tab4, _ovly_buf_table - 4 # 0,2 46 #lnop #nop; lnop #nop; lnop #nop lqx map, tab4, off4 # 1,6 49 #nop cwx genwi, tab4, off4 # 1,4 50 a addr4, tab4, off4 # 0,2 51 #lnop #nop; lnop #nop; lnop #nop; lnop #nop rotqby oldovl, map, addr4 # 1,4 55 #nop shufb newmap, newovl, map, genwi # 0,4 56 #if MFC_TAG_ID < 16 ila newmask, 1 << MFC_TAG_ID # 0,2 57 #else ilhu newmask, 1 << (MFC_TAG_ID - 16) # 0,2 57 #endif #lnop #nop; lnop #nop; lnop stqd newmap, 0(addr4) # 1,6 60 / Save app's tagmask, wait for DMA complete, restore mask. / ila tagstat, MFC_TAG_UPDATE_ALL # 0,2 61 rdch oldmask, $MFC_RdTagMask # 1,6 61 #nop wrch $MFC_WrTagMask, newmask # 1,6 62 #nop wrch $MFC_WrTagUpdate, tagstat # 1,6 63 #nop rdch tagstat, $MFC_RdTagStat # 1,6 64 #nop sync # 1,4 65 / Any hint prior to the sync is lost. A hint here allows the branch to complete 15 cycles after the hint. With no hint the branch will take 18 or 19 cycles. / ila tab5, _ovly_table - 16 # 0,2 66 hbr do_load99, target # 1,15 66 shli off5, oldovl, 4 # 0,4 67 wrch $MFC_WrTagMask, oldmask # 1,6 67 ceqi zovl, oldovl, 0 # 0,2 68 #lnop #nop; lnop #nop fsm zovl, zovl # 1,4 70 #nop lqx oldvma, tab5, off5 # 1,6 71 #nop lqd save3, -48($sp) # 1,6 72 #nop; lnop andc pbit, pbit, zovl # 0,2 74 lqd save2, -32($sp) # 1,6 74 #ifdef OVLY_IRQ_SAVE ila irqtmp2, do_load90 # 0,2 75 #lnop andi irq_stat, irq_stat, 1 # 0,2 76 #lnop #else #nop; lnop #nop; lnop #endif andc oldvma, oldvma, pbit # 0,2 77 lqd save1, -16($sp) # 1,6 77 nop # 0,0 78 #lnop #nop stqx oldvma, tab5, off5 # 1,6 79 #nop #ifdef OVLY_IRQ_SAVE binze irq_stat, irqtmp2 # 1,4 80 do_load90: #nop lqd save4, -64($sp) # 1,6 84 #else #nop; lnop #endif .global _ovly_debug_event .type _ovly_debug_event, @function _ovly_debug_event: nop / Branch to target address. */ do_load99: bi target # 1,4 81/85 .size __ovly_load, . - __ovly_load
stsp/binutils-ia16	1,703	ld/testsuite/ld-riscv-elf/variant_cc-2.s	.text .variant_cc cc_global_default_def .variant_cc cc_global_default_undef .variant_cc cc_global_default_ifunc .variant_cc cc_global_hidden_def .variant_cc cc_global_hidden_ifunc .variant_cc cc_local2 .variant_cc cc_local2_ifunc .global cc_global_default_def .global cc_global_default_undef .global cc_global_default_ifunc .global cc_global_hidden_def .global cc_global_hidden_ifunc .global nocc_global_default_def .global nocc_global_default_undef .global nocc_global_default_ifunc .global nocc_global_hidden_def .global nocc_global_hidden_ifunc .hidden cc_global_hidden_def .hidden cc_global_hidden_ifunc .hidden nocc_global_hidden_def .hidden nocc_global_hidden_ifunc # .type cc_global_default_ifunc, %gnu_indirect_function # .type cc_global_hidden_ifunc, %gnu_indirect_function .type cc_local2_ifunc, %gnu_indirect_function # .type nocc_global_default_ifunc, %gnu_indirect_function # .type nocc_global_hidden_ifunc, %gnu_indirect_function .type nocc_local2_ifunc, %gnu_indirect_function # cc_global_default_def: # cc_global_default_undef: # cc_global_hidden_def: # cc_global_default_ifunc: # cc_global_hidden_ifunc: cc_local2: cc_local2_ifunc: # nocc_global_default_def: # nocc_global_default_undef: # nocc_global_hidden_def: # nocc_global_default_ifunc: # nocc_global_hidden_ifunc: nocc_local2: nocc_local2_ifunc: call cc_global_default_def call cc_global_default_undef call cc_global_hidden_def call cc_global_default_ifunc call cc_global_hidden_ifunc call cc_local2 call cc_local2_ifunc call nocc_global_default_def call nocc_global_default_undef call nocc_global_hidden_def call nocc_global_default_ifunc call nocc_global_hidden_ifunc call nocc_local2 call nocc_local2_ifunc
stsp/binutils-ia16	1,667	ld/testsuite/ld-riscv-elf/variant_cc-1.s	.text .variant_cc cc_global_default_def .variant_cc cc_global_default_undef .variant_cc cc_global_default_ifunc .variant_cc cc_global_hidden_def .variant_cc cc_global_hidden_ifunc .variant_cc cc_local .variant_cc cc_local_ifunc .global cc_global_default_def .global cc_global_default_undef .global cc_global_default_ifunc .global cc_global_hidden_def .global cc_global_hidden_ifunc .global nocc_global_default_def .global nocc_global_default_undef .global nocc_global_default_ifunc .global nocc_global_hidden_def .global nocc_global_hidden_ifunc .hidden cc_global_hidden_def .hidden cc_global_hidden_ifunc .hidden nocc_global_hidden_def .hidden nocc_global_hidden_ifunc .type cc_global_default_ifunc, %gnu_indirect_function .type cc_global_hidden_ifunc, %gnu_indirect_function .type cc_local_ifunc, %gnu_indirect_function .type nocc_global_default_ifunc, %gnu_indirect_function .type nocc_global_hidden_ifunc, %gnu_indirect_function .type nocc_local_ifunc, %gnu_indirect_function cc_global_default_def: # cc_global_default_undef: cc_global_hidden_def: cc_global_default_ifunc: cc_global_hidden_ifunc: cc_local: cc_local_ifunc: nocc_global_default_def: # nocc_global_default_undef: nocc_global_hidden_def: nocc_global_default_ifunc: nocc_global_hidden_ifunc: nocc_local: nocc_local_ifunc: call cc_global_default_def call cc_global_default_undef call cc_global_hidden_def call cc_global_default_ifunc call cc_global_hidden_ifunc call cc_local call cc_local_ifunc call nocc_global_default_def call nocc_global_default_undef call nocc_global_hidden_def call nocc_global_default_ifunc call nocc_global_hidden_ifunc call nocc_local call nocc_local_ifunc

stsp/binutils-ia16

1,965

gas/testsuite/gas/sparc/hpcvis3.s

# Test HPC/VIS3 instructions .text nop nop ldx [%g3], %efsr nop 1: nop fnadds %f1, %f2, %f3 fnaddd %f2, %f4, %f6 fnmuls %f3, %f5, %f7 fnmuld %f6, %f8, %f10 fhadds %f7, %f9, %f11 fhaddd %f8, %f10, %f12 fhsubs %f9, %f11, %f13 fhsubd %f10, %f12, %f14 fnhadds %f11, %f13, %f15 fnhaddd %f12, %f14, %f16 fnsmuld %f13, %f15, %f16 fmadds %f15, %f17, %f19, %f21 fmaddd %f14, %f16, %f18, %f20 fmsubs %f17, %f19, %f21, %f23 fmsubd %f16, %f18, %f20, %f22 fnmsubs %f19, %f21, %f23, %f25 fnmsubd %f18, %f20, %f22, %f24 fnmadds %f21, %f23, %f25, %f27 fnmaddd %f20, %f22, %f24, %f26 fumadds %f23, %f25, %f27, %f29 fumaddd %f22, %f24, %f26, %f28 fumsubs %f25, %f27, %f29, %f31 fumsubd %f24, %f26, %f28, %f30 fnumsubs %f1, %f3, %f5, %f7 fnumsubd %f2, %f4, %f6, %f8 fnumadds %f3, %f5, %f7, %f9 fnumaddd %f4, %f6, %f8, %f10 addxc %g5, %g6, %g7 addxccc %o1, %o2, %o3 nop umulxhi %o5, %o6, %o7 lzcnt %i1, %i2 cmask8 %i3 cmask16 %i4 cmask32 %i5 fsll16 %f32, %f34, %f36 fsrl16 %f34, %f36, %f38 fsll32 %f36, %f38, %f40 fsrl32 %f38, %f40, %f42 fslas16 %f40, %f42, %f44 fsra16 %f42, %f44, %f46 fslas32 %f44, %f46, %f48 fsra32 %f46, %f48, %f50 pdistn %f48, %f50, %g1 fmean16 %f50, %f52, %f54 fpadd64 %f52, %f54, %f56 fchksm16 %f54, %f56, %f58 fpsub64 %f56, %f58, %f60 fpadds16 %f58, %f60, %f62 fpadds16s %f2, %f4, %f6 fpadds32 %f4, %f6, %f8 fpadds32s %f6, %f8, %f10 fpsubs16 %f8, %f10, %f12 fpsubs16s %f10, %f12, %f14 fpsubs32 %f12, %f14, %f16 fpsubs32s %f14, %f16, %f18 movdtox %f20, %g1 movstouw %f21, %g2 movstosw %f23, %g3 movxtod %g4, %f22 movwtos %g5, %f23 xmulx %o1, %o2, %o3 xmulxhi %o4, %o5, %o6 fucmple8 %f16, %f18, %g1 fucmpne8 %f18, %f20, %g2 fucmpgt8 %f20, %f22, %g3 fucmpeq8 %f22, %f24, %g4 flcmps %fcc0, %f1, %f3 flcmps %fcc1, %f3, %f5 flcmps %fcc2, %f5, %f7 flcmps %fcc3, %f7, %f9 flcmpd %fcc0, %f12, %f14 flcmpd %fcc1, %f14, %f16 flcmpd %fcc2, %f16, %f18 flcmpd %fcc3, %f18, %f20 lzd %i1, %i2

stsp/binutils-ia16

2,847

gas/testsuite/gas/sparc/splet.s

.text .global start ! Starting point start: ! test all ASRs rd %asr0, %l0 rd %asr1, %l0 rd %asr15, %l0 rd %asr17, %l0 rd %asr18, %l0 rd %asr19, %l0 ! should stop the processor rd %asr20, %l0 rd %asr21, %l0 rd %asr22, %l0 wr %l0, 0, %asr0 wr %l0, 0, %asr1 wr %l0, 0, %asr15 wr %l0, 0, %asr17 wr %l0, 0, %asr18 wr %l0, 0, %asr19 wr %l0, 0, %asr20 wr %l0, 0, %asr21 wr %l0, 0, %asr22 ! test UMUL with no overflow inside Y test_umul: umul %g1, %g2, %g3 ! test UMUL with an overflow inside Y umul %g1, %g2, %g3 ! %g3 must be equal to 0 ! test SMUL with negative result test_smul: smul %g1, %g2, %g3 ! test SMUL with positive result smul %g1, %g2, %g3 ! test STBAR: there are two possible syntaxes test_stbar: stbar ! is a valid V8 syntax, at least a synthetic ! instruction rd %asr15, %g0 ! other solution ! test UNIMP unimp 1 ! test FLUSH flush %l1 ! is the official V8 syntax ! test SCAN: find first 0 test_scan: scan %l1, 0xffffffff, %l3 ! test scan: find first 1 scan %l1, 0, %l3 ! test scan: find first bit != bit-0 scan %l1, %l1, %l3 ! test SHUFFLE test_shuffle: shuffle %l0, 0x1, %l1 shuffle %l0, 0x2, %l1 shuffle %l0, 0x4, %l1 shuffle %l0, 0x8, %l1 shuffle %l0, 0x10, %l1 shuffle %l0, 0x18, %l1 ! test UMAC test_umac: umac %l1, %l2, %l0 umac %l1, 2, %l0 umac 2, %l1, %l0 ! test UMACD test_umacd: umacd %l2, %l4, %l0 umacd %l2, 3, %l0 umacd 3, %l2, %l0 ! test SMAC test_smac: smac %l1, %l2, %l0 smac %l1, -42, %l0 smac -42, %l1, %l0 ! test SMACD test_smacd: smacd %l2, %l4, %l0 smacd %l2, 123, %l0 smacd 123, %l2, %l0 ! test UMULD test_umuld: umuld %o2, %o4, %o0 umuld %o2, 0x234, %o0 umuld 0x567, %o2, %o0 ! test SMULD test_smuld: smuld %i2, %i4, %i0 smuld %i2, -4096, %i0 smuld 4095, %i4, %i0 ! Coprocessor instructions test_coprocessor: ! %ccsr is register # 0 ! %ccfr is register # 1 ! %ccpr is register # 3 ! %cccrcr is register # 2 ! test CPUSH: just syntax cpush %l0, %l1 cpush %l0, 1 cpusha %l0, %l1 cpusha %l0, 1 ! test CPULL: just syntax cpull %l0 ! test CPRDCXT: just syntax crdcxt %ccsr, %l0 crdcxt %ccfr, %l0 crdcxt %ccpr, %l0 crdcxt %cccrcr, %l0 ! test CPWRCXT: just syntax cwrcxt %l0, %ccsr cwrcxt %l0, %ccfr cwrcxt %l0, %ccpr cwrcxt %l0, %cccrcr ! test CBccc: just syntax cbn stop nop cbn,a stop nop cbe stop nop cbe,a stop nop cbf stop nop cbf,a stop nop cbef stop nop cbef,a stop nop cbr stop nop cbr,a stop nop cber stop nop cber,a stop nop cbfr stop nop cbfr,a stop nop cbefr stop nop cbefr,a stop nop cba stop nop cba,a stop nop cbne stop nop cbne,a stop nop cbnf stop nop cbnf,a stop nop cbnef stop nop cbnef,a stop nop cbnr stop nop cbnr,a stop nop cbner stop nop cbner,a stop nop cbnfr stop nop cbnfr,a stop nop cbnefr stop nop cbnefr,a stop nop

stsp/binutils-ia16

1,832

gas/testsuite/gas/sparc/wrpr.s

# Test wrpr .text wrpr %g1,%g2,%tpc wrpr %g1,%tpc wrpr %g1,666,%tpc wrpr 666,%g1,%tpc wrpr 666,%tpc wrpr %g1,%g2,%tnpc wrpr %g1,%tnpc wrpr %g1,666,%tnpc wrpr 666,%g1,%tnpc wrpr 666,%tnpc wrpr %g1,%g2,%tstate wrpr %g1,%tstate wrpr %g1,666,%tstate wrpr 666,%g1,%tstate wrpr 666,%tstate wrpr %g1,%g2,%tt wrpr %g1,%tt wrpr %g1,666,%tt wrpr 666,%g1,%tt wrpr 666,%tt wrpr %g1,%g2,%tick wrpr %g1,%tick wrpr %g1,666,%tick wrpr 666,%g1,%tick wrpr 666,%tick wrpr %g1,%g2,%tba wrpr %g1,%tba wrpr %g1,666,%tba wrpr 666,%g1,%tba wrpr 666,%tba wrpr %g1,%g2,%pstate wrpr %g1,%pstate wrpr %g1,666,%pstate wrpr 666,%g1,%pstate wrpr 666,%pstate wrpr %g1,%g2,%tl wrpr %g1,%tl wrpr %g1,666,%tl wrpr 666,%g1,%tl wrpr 666,%tl wrpr %g1,%g2,%pil wrpr %g1,%pil wrpr %g1,666,%pil wrpr 666,%g1,%pil wrpr 666,%pil wrpr %g1,%g2,%cwp wrpr %g1,%cwp wrpr %g1,666,%cwp wrpr 666,%g1,%cwp wrpr 666,%cwp wrpr %g1,%g2,%cansave wrpr %g1,%cansave wrpr %g1,666,%cansave wrpr 666,%g1,%cansave wrpr 666,%cansave wrpr %g1,%g2,%canrestore wrpr %g1,%canrestore wrpr %g1,666,%canrestore wrpr 666,%g1,%canrestore wrpr 666,%canrestore wrpr %g1,%g2,%cleanwin wrpr %g1,%cleanwin wrpr %g1,666,%cleanwin wrpr 666,%g1,%cleanwin wrpr 666,%cleanwin wrpr %g1,%g2,%otherwin wrpr %g1,%otherwin wrpr %g1,666,%otherwin wrpr 666,%g1,%otherwin wrpr 666,%otherwin wrpr %g1,%g2,%wstate wrpr %g1,%wstate wrpr %g1,666,%wstate wrpr 666,%g1,%wstate wrpr 666,%wstate wrpr %g1,%g2,%fq wrpr %g1,%fq wrpr %g1,666,%fq wrpr 666,%g1,%fq wrpr 666,%fq wrpr %g1,%g2,%gl wrpr %g1,%gl wrpr %g1,666,%gl wrpr 666,%g1,%gl wrpr 666,%gl wrpr %g1,%g2,%pmcdper wrpr %g1,%pmcdper wrpr %g1,666,%pmcdper wrpr 666,%g1,%pmcdper wrpr 666,%pmcdper wrpr %g1,%g2,%ver wrpr %g1,%ver wrpr %g1,666,%ver wrpr 666,%g1,%ver wrpr 666,%ver

stsp/binutils-ia16

1,196

gas/testsuite/gas/sparc/xcrypto.s

# Test OSA2015 CRYPTO instructions .text xmpmul 0 xmpmul 1 xmpmul 2 xmpmul 3 xmpmul 4 xmpmul 5 xmpmul 6 xmpmul 7 xmpmul 8 xmpmul 9 xmpmul 10 xmpmul 11 xmpmul 12 xmpmul 13 xmpmul 14 xmpmul 15 xmpmul 16 xmpmul 17 xmpmul 18 xmpmul 19 xmpmul 20 xmpmul 21 xmpmul 22 xmpmul 23 xmpmul 24 xmpmul 25 xmpmul 26 xmpmul 27 xmpmul 28 xmpmul 29 xmpmul 30 xmpmul 31 xmontmul 0 xmontmul 1 xmontmul 2 xmontmul 3 xmontmul 4 xmontmul 5 xmontmul 6 xmontmul 7 xmontmul 8 xmontmul 9 xmontmul 10 xmontmul 11 xmontmul 12 xmontmul 13 xmontmul 14 xmontmul 15 xmontmul 16 xmontmul 17 xmontmul 18 xmontmul 19 xmontmul 20 xmontmul 21 xmontmul 22 xmontmul 23 xmontmul 24 xmontmul 25 xmontmul 26 xmontmul 27 xmontmul 28 xmontmul 29 xmontmul 30 xmontmul 31 xmontsqr 0 xmontsqr 1 xmontsqr 2 xmontsqr 3 xmontsqr 4 xmontsqr 5 xmontsqr 6 xmontsqr 7 xmontsqr 8 xmontsqr 9 xmontsqr 10 xmontsqr 11 xmontsqr 12 xmontsqr 13 xmontsqr 14 xmontsqr 15 xmontsqr 16 xmontsqr 17 xmontsqr 18 xmontsqr 19 xmontsqr 20 xmontsqr 21 xmontsqr 22 xmontsqr 23 xmontsqr 24 xmontsqr 25 xmontsqr 26 xmontsqr 27 xmontsqr 28 xmontsqr 29 xmontsqr 30 xmontsqr 31

stsp/binutils-ia16

1,434

gas/testsuite/gas/sparc/cbcond.s

# Test CBCOND instructions .text cwbe %o1, %o2,1f cwbe %o1, 2, 1f cxbe %o2, %o3, 1f cxbe %o2, 3, 1f cwble %o3, %o4, 1f cwble %o3, 4, 1f cxble %o4, %o5, 1f cxble %o4, 5, 1f cwbl %o5, %l0, 1f cwbl %o5, 6, 1f cxbl %l0, %l1, 1f cxbl %l0, 7, 1f cwbleu %l1, %l2, 1f cwbleu %l1, 8, 1f cxbleu %l2, %l3, 1f cxbleu %l2, 9, 1f cwbcs %l3, %l4, 1f cwbcs %l3, 10, 1f cxbcs %l4, %l5, 1f cxbcs %l4, 11, 1f cwbneg %l5, %l6, 1f cwbneg %l5, 12, 1f cxbneg %l6, %l7, 1f cxbneg %l6, 13, 1f cwbvs %l7, %i0, 1f cwbvs %l7, 14, 1f cxbvs %i0, %i1, 1f cxbvs %i0, 15, 1f cwbne %i1, %i2, 1f cwbne %i1, 16, 1f cxbne %i2, %i3, 1f cxbne %i2, 17, 1f cwbg %i3, %i4, 1f cwbg %i3, 18, 1f cxbg %i4, %i5, 1f cxbg %i4, 19, 1f cwbge %i5, %o0, 1f cwbge %i5, 20, 1f cxbge %o0, %o1, 1f cxbge %o0, 21, 1f cwbgu %o1, %o2, 1f cwbgu %o1, 22, 1f cxbgu %o2, %o3, 1f cxbgu %o2, 22, 1f cwbcc %o3, %o4, 1f cwbcc %o3, 23, 1f cxbcc %o4, %o5, 1f cxbcc %o4, 24, 1f cwbpos %o5, %l0, 1f cwbpos %o5, 25, 1f cxbpos %l0, %l1, 1f cxbpos %l0, 25, 1f cwbvc %l1, %l2, 1f cwbvc %l1, 26, 1f cxbvc %l2, %l3, 1f cxbvc %l2, 27, 1f cwbz %l3, %l4, 1f cwbz %l3, 28, 1f cxbz %l4, %l5, 1f cxbz %l4, 29, 1f cwblu %l5, %l6, 1f cwblu %l5, 28, 1f cxblu %l6, %l7, 1f cxblu %l6, 29, 1f cwbnz %l7, %o0, 1f cwbnz %l7, 30, 1f cxbnz %o0, %o1, 1f cxbnz %o0, 31, 1f cwbgeu %o1, %o2, 1f cwbgeu %o1, 1, 1f cxbgeu %o2, %o3, 1f cxbgeu %o2, 2, 1f 1: nop

stsp/binutils-ia16

1,875

gas/testsuite/gas/sparc/crypto.s

# Test CRYPTO instructions .text md5 sha1 sha256 sha512 crc32c %f2, %f4, %f6 aes_kexpand0 %f4, %f6, %f8 aes_kexpand1 %f6, %f8, 0x7, %f10 aes_kexpand1 %f6, %f8, 6, %f10 aes_kexpand2 %f8, %f10, %f12 aes_eround01 %f10, %f12, %f14, %f16 aes_eround23 %f12, %f14, %f16, %f18 aes_dround01 %f14, %f16, %f18, %f20 aes_dround23 %f16, %f18, %f20, %f22 aes_eround01_l %f18, %f20, %f22, %f24 aes_eround23_l %f20, %f22, %f24, %f26 aes_dround01_l %f22, %f24, %f26, %f28 aes_dround23_l %f24, %f26, %f28, %f30 des_ip %f32, %f34 des_iip %f34, %f36 des_kexpand %f36, 7, %f38 des_round %f38, %f40, %f42, %f44 kasumi_fi_fi %f42, %f44, %f46 kasumi_fl_xor %f44, %f46, %f48, %f50 kasumi_fi_xor %f46, %f48, %f50, %f52 camellia_fl %f50, %f52, %f54 camellia_fli %f52, %f54, %f56 camellia_f %f54, %f56, %f58, %f60 mpmul 0 mpmul 1 mpmul 2 mpmul 3 mpmul 4 mpmul 5 mpmul 6 mpmul 7 mpmul 8 mpmul 9 mpmul 10 mpmul 11 mpmul 12 mpmul 13 mpmul 14 mpmul 15 mpmul 16 mpmul 17 mpmul 18 mpmul 19 mpmul 20 mpmul 21 mpmul 22 mpmul 23 mpmul 24 mpmul 25 mpmul 26 mpmul 27 mpmul 28 mpmul 29 mpmul 30 mpmul 31 montmul 0 montmul 1 montmul 2 montmul 3 montmul 4 montmul 5 montmul 6 montmul 7 montmul 8 montmul 9 montmul 10 montmul 11 montmul 12 montmul 13 montmul 14 montmul 15 montmul 16 montmul 17 montmul 18 montmul 19 montmul 20 montmul 21 montmul 22 montmul 23 montmul 24 montmul 25 montmul 26 montmul 27 montmul 28 montmul 29 montmul 30 montmul 31 montsqr 0 montsqr 1 montsqr 2 montsqr 3 montsqr 4 montsqr 5 montsqr 6 montsqr 7 montsqr 8 montsqr 9 montsqr 10 montsqr 11 montsqr 12 montsqr 13 montsqr 14 montsqr 15 montsqr 16 montsqr 17 montsqr 18 montsqr 19 montsqr 20 montsqr 21 montsqr 22 montsqr 23 montsqr 24 montsqr 25 montsqr 26 montsqr 27 montsqr 28 montsqr 29 montsqr 30 montsqr 31

stsp/binutils-ia16

1,347

gas/testsuite/gas/sparc/set64.s

# sparc64 set insn handling (includes set, setuw, setsw, setx) foo: set foo,%g2 set 0x76543210,%g3 set 0,%g4 set 65535,%g5 setx foo,%g1,%g2 setx -1,%g1,%g3 setx 0,%g1,%g3 setx 1,%g1,%g3 setx 4095,%g1,%g3 setx 4096,%g1,%g3 setx -4096,%g1,%g3 setx -4097,%g1,%g3 setx 65535,%g1,%g3 setx -65536,%g1,%g3 setx 2147483647,%g1,%g4 setx 2147483648,%g1,%g4 setx -2147483648,%g1,%g4 setx -2147483649,%g1,%g4 setx 4294967295,%g1,%g4 setx 4294967296,%g1,%g4 ! GAS doesn't handle large base10 numbers yet. ! setx 9223372036854775807,%g1,%g5 ! setx 9223372036854775808,%g1,%g5 ! setx -9223372036854775808,%g1,%g5 ! setx -9223372036854775809,%g1,%g5 setx 0x7fffffffffffffff,%g1,%g5 setx 0x8000000000000000,%g1,%g5 ! test only hh22 needed setx 0xffffffff00000000,%g1,%g5 ! test only hm10 needed setx 0xffffffff80000000,%g1,%g5 ! test sign-ext of lower 32 setx 0xffff0000ffff0000,%g1,%g5 ! test hh22,hi22 setx 0xffff000000000001,%g1,%g5 ! test hh22,lo10 setx 0x00000001ffff0001,%g1,%g5 ! test hm10,hi22,lo10 setx 0x00000001ffff0000,%g1,%g5 ! test hm10,hi22 setx 0x0000000100000001,%g1,%g5 ! test hm10,lo10 setuw foo,%g2 setuw 0x76543210,%g3 setuw 0,%g4 setuw 65535,%g5 setsw foo,%g2 setsw 0x76543210,%g3 setsw 0,%g4 setsw 65535,%g5 setsw 0xffffffff,%g1 setsw 0x7fffffff,%g2 setsw 0xffff0000,%g3 setsw -1,%g4

stsp/binutils-ia16

1,767

gas/testsuite/gas/sparc/ldm-stm.s

# Test ldm/stm/ldma/stma .text ldmsh [%g0+%g1], %g2 ldmsh [%g1], %g3 ldmsh [%g1+102], %g3 ldmsh [102+%g1], %g3 ldmsh [102], %g3 ldmuh [%g0+%g1], %g2 ldmuh [%g1], %g3 ldmuh [%g1+102], %g3 ldmuh [102+%g1], %g3 ldmuh [102], %g3 ldmsw [%g0+%g1], %g2 ldmsw [%g1], %g3 ldmsw [%g1+102], %g3 ldmsw [102+%g1], %g3 ldmsw [102], %g3 ldmuw [%g0+%g1], %g2 ldmuw [%g1], %g3 ldmuw [%g1+102], %g3 ldmuw [102+%g1], %g3 ldmuw [102], %g3 ldmx [%g0+%g1], %g2 ldmx [%g1], %g3 ldmx [%g1+102], %g3 ldmx [102+%g1], %g3 ldmx [102], %g3 ldmux [%g0+%g1], %g2 ldmux [%g1], %g3 ldmux [%g1+102], %g3 ldmux [102+%g1], %g3 ldmux [102], %g3 ldmsha [%g1+%g2] %asi, %g3 ldmsha [%g1] %asi, %g2 ldmuha [%g1+%g2] %asi, %g3 ldmuha [%g1] %asi, %g2 ldmswa [%g1+%g2] %asi, %g3 ldmswa [%g1] %asi, %g2 ldmuwa [%g1+%g2] %asi, %g3 ldmuwa [%g1] %asi, %g2 ldmxa [%g1+%g2] %asi, %g3 ldmxa [%g1] %asi, %g2 stmh %g2, [%g0+%g1] stmh %g3, [%g1] stmh %g3, [%g1+102] stmh %g3, [102+%g1] stmh %g3, [102] stmw %g2, [%g0+%g1] stmw %g3, [%g1] stmw %g3, [%g1+102] stmw %g3, [102+%g1] stmw %g3, [102] stmx %g2, [%g0+%g1] stmx %g3, [%g1] stmx %g3, [%g1+102] stmx %g3, [102+%g1] stmx %g3, [102] stmha %g2, [%g0+%g1] %asi stmha %g3, [%g1] %asi stmwa %g2, [%g0+%g1] %asi stmwa %g3, [%g1] %asi stmxa %g2, [%g0+%g1] %asi stmxa %g3, [%g1] %asi

stsp/binutils-ia16

46,880

gas/testsuite/gas/sh/arch/sh4al-dsp.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4al-dsp but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4al_dsp: ! Instructions introduced into sh4al-dsp clrdmxy ;!/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up} ldrc r5 ;!/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up} ldrc #4 ;!/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up} setdmx ;!/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up} setdmy ;!/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up} movx.w @r1,y1 ;!/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up} movx.w @r1+,y1 ;!/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up} movx.w @r1+r8,y1 ;!/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up} movx.w a0,@r1 ;!/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up} movx.w a0,@r1+ ;!/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up} movx.w a0,@r1+r8 ;!/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up} movx.l @r1,y1 ;!/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up} movx.l @r1+,y1 ;!/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up} movx.l @r1+r8,y1 ;!/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up} movx.l a0,@r1 ;!/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up} movx.l a0,@r1+ ;!/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up} movx.l a0,@r1+r8 ;!/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up} movy.w @r3,y1 ;!/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up} movy.w @r3+,y1 ;!/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up} movy.w @r3+r9,y1 ;!/* nnmm000011 movy.w @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up} movy.w a0,@r3 ;!/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up} movy.w a0,@r3+ ;!/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up} movy.w a0,@r3+r9 ;!/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up} movy.l @r3,y1 ;!/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up} movy.l @r3+,y1 ;!/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up} movy.l @r3+r9,y1 ;!/* nnmm100011 movy.l @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up} movy.l a0,@r3 ;!/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up} movy.l a0,@r3+ ;!/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up} movy.l a0,@r3+r9 ;!/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up} dct pabs x1,m0 ;!/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up} dct pabs y0,m0 ;!/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up} dct prnd x1,m0 ;!/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up} dct prnd y0,m0 ;!/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up} dct psub y0,x1,m0 ;!/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */ {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up} dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} ! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}

stsp/binutils-ia16

38,442

gas/testsuite/gas/sh/arch/sh3-dsp.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3-dsp but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3_dsp: ! Instructions introduced into sh3-dsp ! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}

stsp/binutils-ia16

25,681

gas/testsuite/gas/sh/arch/sh4a-nofpu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4a-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4a_nofpu: ! Instructions introduced into sh4a-nofpu icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

25,376

gas/testsuite/gas/sh/arch/sh2e.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2e but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2e: ! Instructions introduced into sh2e lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ! Instructions inherited from ancestors: sh sh2 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

20,277

gas/testsuite/gas/sh/arch/sh2.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2: ! Instructions introduced into sh2 bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} ! Instructions inherited from ancestors: sh add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}

stsp/binutils-ia16

39,786

gas/testsuite/gas/sh/arch/sh2a.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a: ! Instructions introduced into sh2a fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32} fmov.d @(2048,r5),xd2 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */ {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32} fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32} mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32} mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up} clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up} clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up} divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up} divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up} jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up} jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up} ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up} movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up} mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up} nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up} resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up} rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up} rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up} stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up} band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32} movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32} movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}

stsp/binutils-ia16

30,134

gas/testsuite/gas/sh/arch/sh2a-or-sh4.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-or-sh4 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_or_sh4: ! Instructions introduced into sh2a-or-sh4 fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}

stsp/binutils-ia16

22,754

gas/testsuite/gas/sh/arch/sh3-nommu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3-nommu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3_nommu: ! Instructions introduced into sh3-nommu clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

35,839

gas/testsuite/gas/sh/arch/sh-dsp.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh-dsp but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh_dsp: ! Instructions introduced into sh-dsp ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up} ! Instructions inherited from ancestors: sh sh2 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

28,125

gas/testsuite/gas/sh/arch/sh3e.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3e but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3e: ! Instructions introduced into sh3e ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}

stsp/binutils-ia16

26,032

gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-or-sh3e but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_or_sh3e: ! Instructions introduced into sh2a-or-sh3e fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}

stsp/binutils-ia16

18,809

gas/testsuite/gas/sh/arch/sh.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh: ! Instructions introduced into sh add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} ! Instructions inherited from ancestors:

stsp/binutils-ia16

22,870

gas/testsuite/gas/sh/arch/sh3.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh3 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh3: ! Instructions introduced into sh3 ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

35,808

gas/testsuite/gas/sh/arch/sh4a.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4a but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4a: ! Instructions introduced into sh4a fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up} fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up} fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}

stsp/binutils-ia16

24,561

gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4-nommu-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4_nommu_nofpu: ! Instructions introduced into sh4-nommu-nofpu ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

24,687

gas/testsuite/gas/sh/arch/sh4-nofpu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4_nofpu: ! Instructions introduced into sh4-nofpu ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

20,848

gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_nofpu_or_sh4_nommu_nofpu: ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

34,684

gas/testsuite/gas/sh/arch/sh4.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh4 but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh4: ! Instructions introduced into sh4 fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up} frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up} fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up} fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}

stsp/binutils-ia16

20,806

gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-nofpu-or-sh3-nommu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_nofpu_or_sh3_nommu: ! Instructions introduced into sh2a-nofpu-or-sh3-nommu pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} ! Instructions inherited from ancestors: sh sh2 add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

29,623

gas/testsuite/gas/sh/arch/sh2a-nofpu.s

! Generated file. DO NOT EDIT. ! ! This file was generated by gas/testsuite/gas/sh/arch/sh-opc-gen-as.pl . ! This file should contain every instruction valid on ! architecture sh2a-nofpu but no more. ! If the tests are failing because the expected results have changed then run ! 'cat ../../../../../opcodes/sh-opc.h | perl sh-opc-gen-as.pl' ! in <srcdir>/gas/testsuite/gas/sh/arch to re-generate the files. ! Make sure there are no unexpected or missing instructions. .section .text sh2a_nofpu: ! Instructions introduced into sh2a-nofpu ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32} mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32} mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32} mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up} bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up} clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up} clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up} divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up} divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up} jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up} jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up} ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up} movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up} movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up} movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up} mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up} nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up} resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up} rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up} rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up} stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up} band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32} movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32} movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} ! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} .align 2 mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} .align 2 mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up} rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}

stsp/binutils-ia16

2,882

gas/testsuite/gas/hppa/reloc/funcrelocbug.s

.code .align 4 .EXPORT g,CODE .EXPORT g,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR g: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) copy %r3,%r1 copy %r30,%r3 stwm %r1,128(%r30) stw %r26,-36(%r3) stw %r25,-40(%r3) stw %r24,-44(%r3) ldw -36(%r3),%r26 ldw -40(%r3),%r25 ldw -44(%r3),%r19 copy %r19,%r22 .CALL ARGW0=GR bl $$dyncall,%r31 copy %r31,%r2 copy %r28,%r19 comiclr,<> 0,%r19,%r0 bl,n L$0002,%r0 ldw -36(%r3),%r28 bl,n L$0001,%r0 bl,n L$0003,%r0 L$0002: ldw -40(%r3),%r28 bl,n L$0001,%r0 L$0003: L$0001: ldw -20(%r3),%r2 ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND .align 4 f2___4: .PROC .CALLINFO FRAME=64,NO_CALLS,SAVE_SP,ENTRY_GR=3 .ENTRY copy %r3,%r1 copy %r30,%r3 stwm %r1,64(%r30) stw %r29,8(%r3) stw %r26,-36(%r3) stw %r25,-40(%r3) ldw -36(%r3),%r19 ldw -40(%r3),%r20 comclr,>= %r20,%r19,%r19 ldi 1,%r19 copy %r19,%r28 bl,n L$0005,%r0 L$0005: ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND .IMPORT abort,CODE .data .align 4 L$TRAMP0000: ldw 36(%r22),%r21 bb,>=,n %r21,30,.+16 depi 0,31,2,%r21 ldw 4(%r21),%r19 ldw 0(%r21),%r21 ldsid (%r21),%r1 mtsp %r1,%sr0 be 0(%sr0,%r21) ldw 40(%r22),%r29 .word 0 .word 0 .code .align 4 .EXPORT f,CODE .EXPORT f,ENTRY,PRIV_LEV=3,RTNVAL=GR f: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) copy %r3,%r1 copy %r30,%r3 stwm %r1,192(%r30) ldo 16(%r3),%r19 addil L'L$TRAMP0000-$global$,%r27 ldo R'L$TRAMP0000-$global$(%r1),%r22 ldo 40(%r0),%r20 ldws,ma 4(%r22),%r21 addib,>= -4,%r20,.-4 stws,ma %r21,4(%r19) ldil L'f2___4,%r20 ldo R'f2___4(%r20),%r19 stw %r19,52(%r3) ldo 8(%r3),%r19 stw %r19,56(%r3) ldo 16(%r3),%r19 ldo 48(%r3),%r20 fdc %r0(%r19) fdc %r0(%r20) sync ldo 32(%r19),%r22 mfsp %sr0,%r21 ldsid (%r19),%r20 mtsp %r20,%sr0 fic %r0(%sr0,%r19) fic %r0(%sr0,%r22) sync mtsp %r21,%sr0 nop nop nop nop nop nop ldo 16(%r3),%r19 ldi 1,%r26 ldi 2,%r25 copy %r19,%r24 .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl g,%r2 nop copy %r28,%r19 comiclr,<> 2,%r19,%r0 bl,n L$0006,%r0 .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl abort,%r2 nop L$0006: L$0004: ldw -20(%r3),%r2 ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND .IMPORT __main,CODE .IMPORT exit,CODE .align 4 .EXPORT main,CODE .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR main: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP,SAVE_SP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) copy %r3,%r1 copy %r30,%r3 stwm %r1,128(%r30) .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl __main,%r2 nop .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl f,%r2 nop copy %r0,%r26 .CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO bl exit,%r2 nop L$0007: ldw -20(%r3),%r2 ldo 64(%r3),%r30 ldwm -64(%r30),%r3 bv,n %r0(%r2) .EXIT .PROCEND

stsp/binutils-ia16

1,247

gas/testsuite/gas/hppa/reloc/reduce2.s

.SPACE $PRIVATE$ .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 .SPACE $TEXT$ .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY .IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE ; gcc_compiled.: .SPACE $TEXT$ .SUBSPA $LIT$ .align 8 L$P0000 .word 0x12345678 .word 0x0 .align 8 L$C0000 .word 0x3ff00000 .word 0x0 .SPACE $TEXT$ .SUBSPA $CODE$ .align 4 .EXPORT g,ENTRY,PRIV_LEV=3,RTNVAL=FR g .PROC .CALLINFO FRAME=0,NO_CALLS .ENTRY stw %r19,-32(%r30) ldw T'L$C0000(%r19),%r20 bv %r0(%r2) fldds 0(%r20),%fr4 .EXIT .PROCEND .IMPORT abort,CODE .IMPORT exit,CODE .SPACE $TEXT$ .SUBSPA $LIT$ .align 8 L$C0001 .word 0x3ff00000 .word 0x0 .SPACE $TEXT$ .SUBSPA $CODE$ .align 4 .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR main .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP,ENTRY_GR=3 .ENTRY stw %r2,-20(%r30) ldo 128(%r30),%r30 stw %r19,-32(%r30) stw %r4,-128(%r30) copy %r19,%r4 .CALL bl g,%r2 copy %r4,%r19 copy %r4,%r19 ldw T'L$C0001(%r19),%r20 fldds 0(%r20),%fr8 fcmp,dbl,= %fr4,%fr8 ftest add,tr %r0,%r0,%r0 b,n L$0003 .CALL bl abort,%r2 nop L$0003 .CALL ARGW0=GR bl exit,%r2 ldi 0,%r26 nop .EXIT .PROCEND

stsp/binutils-ia16

2,026

gas/testsuite/gas/hppa/reloc/applybug.s

.IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE ; gcc_compiled.: .data .align 4 tab___2: .word L$0002 .word L$0003 .word L$0004 .code .align 4 .EXPORT execute,CODE .EXPORT execute,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR execute: .PROC .CALLINFO FRAME=0,NO_CALLS .ENTRY addil L'buf-$global$,%r27 ldo R'buf-$global$(%r1),%r20 ldil L'L$0002,%r19 movb,<> %r26,%r26,L$0002 ldo R'L$0002(%r19),%r22 copy %r0,%r21 addil L'tab___2-$global$,%r27 ldo R'tab___2-$global$(%r1),%r23 addil L'optab-$global$,%r27 ldo R'optab-$global$(%r1),%r20 L$0009: sh2add %r21,%r23,%r19 ldh 2(%r19),%r19 ldo 1(%r21),%r21 sub %r19,%r22,%r19 comib,>= 2,%r21,L$0009 sths,ma %r19,2(%r20) bv,n %r0(%r2) L$0002: ldi 120,%r19 stbs,ma %r19,1(%r20) ldhs,ma 2(%r26),%r19 add %r22,%r19,%r19 bv,n %r0(%r19) L$0003: ldi 121,%r19 stbs,ma %r19,1(%r20) ldhs,ma 2(%r26),%r19 add %r22,%r19,%r19 bv,n %r0(%r19) L$0004: ldi 122,%r19 stb %r19,0(%r20) bv %r0(%r2) stbs,mb %r0,1(%r20) .EXIT .PROCEND .IMPORT __main,CODE .IMPORT strcmp,CODE .align 4 L$C0000: .STRING "xyxyz\x00" .IMPORT abort,CODE .IMPORT exit,CODE .code .align 4 .EXPORT main,CODE .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR main: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) .CALL bl __main,%r2 ldo 128(%r30),%r30 .CALL ARGW0=GR bl execute,%r2 copy %r0,%r26 addil L'optab-$global$,%r27 copy %r1,%r19 ldo R'optab-$global$(%r19),%r21 ldh 2(%r21),%r20 ldh R'optab-$global$(%r19),%r19 addil L'p-$global$,%r27 copy %r1,%r22 sth %r20,R'p-$global$(%r22) ldo R'p-$global$(%r22),%r26 sth %r20,4(%r26) sth %r19,2(%r26) ldh 4(%r21),%r19 .CALL ARGW0=GR bl execute,%r2 sth %r19,6(%r26) addil L'buf-$global$,%r27 copy %r1,%r19 ldo R'buf-$global$(%r19),%r26 ldil L'L$C0000,%r25 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ldo R'L$C0000(%r25),%r25 comib,=,n 0,%r28,L$0011 .CALL bl abort,%r2 nop L$0011: .CALL ARGW0=GR bl exit,%r2 copy %r0,%r26 nop .EXIT .PROCEND .data optab: .comm 10 buf: .comm 10 p: .comm 10

stsp/binutils-ia16

106,210

gas/testsuite/gas/hppa/unsorted/brlenbug.s

.IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE ; gcc_compiled.: .data .align 4 done___2 .word 0 .IMPORT memset,CODE .EXPORT re_syntax_options,DATA .align 4 re_syntax_options .word 0 .align 4 re_error_msg .word 0 .word L$C0000 .word L$C0001 .word L$C0002 .word L$C0003 .word L$C0004 .word L$C0005 .word L$C0006 .word L$C0007 .word L$C0008 .word L$C0009 .word L$C0010 .word L$C0011 .word L$C0012 .word L$C0013 .word L$C0014 .word L$C0015 .code .align 4 L$C0015 .STRING "Unmatched ) or \\)\x00" .align 4 L$C0014 .STRING "Regular expression too big\x00" .align 4 L$C0013 .STRING "Premature end of regular expression\x00" .align 4 L$C0012 .STRING "Invalid preceding regular expression\x00" .align 4 L$C0011 .STRING "Memory exhausted\x00" .align 4 L$C0010 .STRING "Invalid range end\x00" .align 4 L$C0009 .STRING "Invalid content of \\{\\}\x00" .align 4 L$C0008 .STRING "Unmatched \\{\x00" .align 4 L$C0007 .STRING "Unmatched ( or \\(\x00" .align 4 L$C0006 .STRING "Unmatched [ or [^\x00" .align 4 L$C0005 .STRING "Invalid back reference\x00" .align 4 L$C0004 .STRING "Trailing backslash\x00" .align 4 L$C0003 .STRING "Invalid character class name\x00" .align 4 L$C0002 .STRING "Invalid collation character\x00" .align 4 L$C0001 .STRING "Invalid regular expression\x00" .align 4 L$C0000 .STRING "No match\x00" .EXPORT re_max_failures,DATA .data .align 4 re_max_failures .word 2000 .IMPORT malloc,CODE .IMPORT realloc,CODE .IMPORT free,CODE .IMPORT strcmp,CODE .code .align 4 L$C0016 .STRING "alnum\x00" .align 4 L$C0017 .STRING "alpha\x00" .align 4 L$C0018 .STRING "blank\x00" .align 4 L$C0019 .STRING "cntrl\x00" .align 4 L$C0020 .STRING "digit\x00" .align 4 L$C0021 .STRING "graph\x00" .align 4 L$C0022 .STRING "lower\x00" .align 4 L$C0023 .STRING "print\x00" .align 4 L$C0024 .STRING "punct\x00" .align 4 L$C0025 .STRING "space\x00" .align 4 L$C0026 .STRING "upper\x00" .align 4 L$C0027 .STRING "xdigit\x00" .IMPORT __alnum,DATA .IMPORT __ctype2,DATA .IMPORT __ctype,DATA .IMPORT at_begline_loc_p,CODE .IMPORT at_endline_loc_p,CODE .IMPORT store_op1,CODE .IMPORT insert_op1,CODE .IMPORT store_op2,CODE .IMPORT insert_op2,CODE .IMPORT compile_range,CODE .IMPORT group_in_compile_stack,CODE .code .align 4 regex_compile .PROC .CALLINFO FRAME=320,CALLS,SAVE_RP,ENTRY_GR=18 .ENTRY stw %r2,-20(%r30) ;# 8989 reload_outsi+2/6 ldo 320(%r30),%r30 ;# 8991 addsi3/2 stw %r18,-168(%r30) ;# 8993 reload_outsi+2/6 stw %r17,-164(%r30) ;# 8995 reload_outsi+2/6 stw %r16,-160(%r30) ;# 8997 reload_outsi+2/6 stw %r15,-156(%r30) ;# 8999 reload_outsi+2/6 stw %r14,-152(%r30) ;# 9001 reload_outsi+2/6 stw %r13,-148(%r30) ;# 9003 reload_outsi+2/6 stw %r12,-144(%r30) ;# 9005 reload_outsi+2/6 stw %r11,-140(%r30) ;# 9007 reload_outsi+2/6 stw %r10,-136(%r30) ;# 9009 reload_outsi+2/6 stw %r9,-132(%r30) ;# 9011 reload_outsi+2/6 stw %r8,-128(%r30) ;# 9013 reload_outsi+2/6 stw %r7,-124(%r30) ;# 9015 reload_outsi+2/6 stw %r6,-120(%r30) ;# 9017 reload_outsi+2/6 stw %r5,-116(%r30) ;# 9019 reload_outsi+2/6 stw %r4,-112(%r30) ;# 9021 reload_outsi+2/6 stw %r3,-108(%r30) ;# 9023 reload_outsi+2/6 stw %r26,-276(%r30) ;# 4 reload_outsi+2/6 ldi 0,%r9 ;# 25 reload_outsi+2/2 ldi 0,%r8 ;# 28 reload_outsi+2/2 stw %r0,-260(%r30) ;# 34 reload_outsi+2/6 ldi 0,%r10 ;# 31 reload_outsi+2/2 ldi 640,%r26 ;# 37 reload_outsi+2/2 ldw -276(%r30),%r1 ;# 8774 reload_outsi+2/5 copy %r24,%r15 ;# 8 reload_outsi+2/1 stw %r1,-296(%r30) ;# 2325 reload_outsi+2/6 copy %r23,%r5 ;# 10 reload_outsi+2/1 addl %r1,%r25,%r16 ;# 19 addsi3/1 .CALL ARGW0=GR bl malloc,%r2 ;# 39 call_value_internal_symref ldw 20(%r5),%r14 ;# 22 reload_outsi+2/5 comib,<> 0,%r28,L$0021 ;# 48 bleu+1 stw %r28,-312(%r30) ;# 43 reload_outsi+2/6 L$0953 bl L$0867,%r0 ;# 53 jump ldi 12,%r28 ;# 51 reload_outsi+2/2 L$0021 ldi 32,%r19 ;# 58 reload_outsi+2/2 stw %r19,-308(%r30) ;# 59 reload_outsi+2/6 stw %r0,-304(%r30) ;# 62 reload_outsi+2/6 stw %r15,12(%r5) ;# 65 reload_outsi+2/6 stw %r0,8(%r5) ;# 85 reload_outsi+2/6 stw %r0,24(%r5) ;# 88 reload_outsi+2/6 addil LR'done___2-$global$,%r27 ;# 92 pic2_lo_sum+1 ldw 28(%r5),%r19 ;# 68 reload_outsi+2/5 ldw RR'done___2-$global$(%r1),%r20 ;# 94 reload_outsi+2/5 depi 0,3,1,%r19 ;# 69 andsi3/2 depi 0,6,2,%r19 ;# 80 andsi3/2 comib,<> 0,%r20,L$0022 ;# 95 bleu+1 stw %r19,28(%r5) ;# 82 reload_outsi+2/6 addil LR're_syntax_table-$global$,%r27 ;# 99 pic2_lo_sum+1 ldo RR're_syntax_table-$global$(%r1),%r4 ;# 100 movhi-2 copy %r4,%r26 ;# 101 reload_outsi+2/1 ldi 0,%r25 ;# 102 reload_outsi+2/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 ;# 104 call_value_internal_symref ldi 256,%r24 ;# 103 reload_outsi+2/2 ldi 1,%r20 ;# 8732 movqi+1/2 ldo 97(%r4),%r19 ;# 8736 addsi3/2 ldo 122(%r4),%r4 ;# 8738 addsi3/2 stbs,ma %r20,1(%r19) ;# 115 movqi+1/6 L$1155 comb,>=,n %r4,%r19,L$1155 ;# 121 bleu+1 stbs,ma %r20,1(%r19) ;# 115 movqi+1/6 ldi 1,%r21 ;# 8717 movqi+1/2 addil LR're_syntax_table-$global$,%r27 ;# 8712 pic2_lo_sum+1 ldo RR're_syntax_table-$global$(%r1),%r19 ;# 8715 movhi-2 ldo 65(%r19),%r20 ;# 8721 addsi3/2 ldo 90(%r19),%r19 ;# 8723 addsi3/2 stbs,ma %r21,1(%r20) ;# 138 movqi+1/6 L$1156 comb,>=,n %r19,%r20,L$1156 ;# 144 bleu+1 stbs,ma %r21,1(%r20) ;# 138 movqi+1/6 ldi 48,%r20 ;# 151 reload_outsi+2/2 ldi 57,%r22 ;# 7976 reload_outsi+2/2 ldi 1,%r21 ;# 8707 movqi+1/2 addil LR're_syntax_table-$global$+48,%r27 ;# 8705 pic2_lo_sum+1 ldo RR're_syntax_table-$global$+48(%r1),%r19 ;# 8711 movhi-2 L$0037 ldo 1(%r20),%r20 ;# 164 addsi3/2 comb,>= %r22,%r20,L$0037 ;# 167 bleu+1 stbs,ma %r21,1(%r19) ;# 161 movqi+1/6 addil LR're_syntax_table-$global$,%r27 ;# 174 pic2_lo_sum+1 ldo RR're_syntax_table-$global$(%r1),%r19 ;# 175 movhi-2 ldi 1,%r20 ;# 176 movqi+1/2 stb %r20,95(%r19) ;# 177 movqi+1/6 addil LR'done___2-$global$,%r27 ;# 178 pic2_lo_sum+1 ldi 1,%r19 ;# 180 reload_outsi+2/2 stw %r19,RR'done___2-$global$(%r1) ;# 181 reload_outsi+2/6 L$0022 ldw 4(%r5),%r19 ;# 187 reload_outsi+2/5 comib,<>,n 0,%r19,L$0039 ;# 189 bleu+1 ldw 0(%r5),%r26 ;# 193 reload_outsi+2/5 comib,=,n 0,%r26,L$0040 ;# 195 bleu+1 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 205 call_value_internal_symref ldi 32,%r25 ;# 203 reload_outsi+2/2 bl L$1157,%r0 ;# 211 jump stw %r28,0(%r5) ;# 223 reload_outsi+2/6 L$0040 .CALL ARGW0=GR bl malloc,%r2 ;# 219 call_value_internal_symref ldi 32,%r26 ;# 217 reload_outsi+2/2 stw %r28,0(%r5) ;# 223 reload_outsi+2/6 L$1157 ldw 0(%r5),%r19 ;# 228 reload_outsi+2/5 comib,<> 0,%r19,L$0042 ;# 230 bleu+1 ldi 32,%r19 ;# 243 reload_outsi+2/2 .CALL ARGW0=GR bl free,%r2 ;# 234 call_internal_symref ldw -312(%r30),%r26 ;# 232 reload_outsi+2/5 bl L$0867,%r0 ;# 238 jump ldi 12,%r28 ;# 51 reload_outsi+2/2 L$0042 stw %r19,4(%r5) ;# 244 reload_outsi+2/6 L$0039 ldw 0(%r5),%r6 ;# 249 reload_outsi+2/5 ldw -296(%r30),%r19 ;# 7981 reload_outsi+2/5 comclr,<> %r16,%r19,%r0 ;# 7982 bleu+1 bl L$0044,%r0 copy %r6,%r12 ;# 253 reload_outsi+2/1 ldw -296(%r30),%r19 ;# 2334 reload_outsi+2/5 L$1178 ldbs,ma 1(%r19),%r7 ;# 277 zero_extendqisi2/2 comib,= 0,%r14,L$0047 ;# 282 bleu+1 stw %r19,-296(%r30) ;# 2337 reload_outsi+2/6 addl %r14,%r7,%r19 ;# 283 addsi3/1 ldb 0(%r19),%r7 ;# 286 zero_extendqisi2/2 L$0047 ldo -10(%r7),%r19 ;# 7895 addsi3/2 addi,uv -115,%r19,%r0 ;# 7896 casesi0 blr,n %r19,%r0 b,n L$0076 L$0863 bl L$0376,%r0 nop ;# 9092 switch_jump L$0954 bl L$0076,%r0 nop ;# 9095 switch_jump L$0955 bl L$0076,%r0 nop ;# 9098 switch_jump L$0956 bl L$0076,%r0 nop ;# 9101 switch_jump L$0957 bl L$0076,%r0 nop ;# 9104 switch_jump L$0958 bl L$0076,%r0 nop ;# 9107 switch_jump L$0959 bl L$0076,%r0 nop ;# 9110 switch_jump L$0960 bl L$0076,%r0 nop ;# 9113 switch_jump L$0961 bl L$0076,%r0 nop ;# 9116 switch_jump L$0962 bl L$0076,%r0 nop ;# 9119 switch_jump L$0963 bl L$0076,%r0 nop ;# 9122 switch_jump L$0964 bl L$0076,%r0 nop ;# 9125 switch_jump L$0965 bl L$0076,%r0 nop ;# 9128 switch_jump L$0966 bl L$0076,%r0 nop ;# 9131 switch_jump L$0967 bl L$0076,%r0 nop ;# 9134 switch_jump L$0968 bl L$0076,%r0 nop ;# 9137 switch_jump L$0969 bl L$0076,%r0 nop ;# 9140 switch_jump L$0970 bl L$0076,%r0 nop ;# 9143 switch_jump L$0971 bl L$0076,%r0 nop ;# 9146 switch_jump L$0972 bl L$0076,%r0 nop ;# 9149 switch_jump L$0973 bl L$0076,%r0 nop ;# 9152 switch_jump L$0974 bl L$0076,%r0 nop ;# 9155 switch_jump L$0975 bl L$0076,%r0 nop ;# 9158 switch_jump L$0976 bl L$0076,%r0 nop ;# 9161 switch_jump L$0977 bl L$0076,%r0 nop ;# 9164 switch_jump L$0978 bl L$0076,%r0 nop ;# 9167 switch_jump L$0979 bl L$0077,%r0 ;# 9170 switch_jump ldw -296(%r30),%r26 ;# 2349 reload_outsi+2/5 L$0980 bl L$0076,%r0 nop ;# 9173 switch_jump L$0981 bl L$0076,%r0 nop ;# 9176 switch_jump L$0982 bl L$0076,%r0 nop ;# 9179 switch_jump L$0983 bl L$0368,%r0 nop ;# 9182 switch_jump L$0984 bl L$0372,%r0 nop ;# 9185 switch_jump L$0985 bl L$0104,%r0 nop ;# 9188 switch_jump L$0986 bl L$1158,%r0 ;# 9191 switch_jump ldi 1026,%r19 ;# 662 reload_outsi+2/2 L$0987 bl L$0076,%r0 nop ;# 9194 switch_jump L$0988 bl L$0076,%r0 nop ;# 9197 switch_jump L$0989 bl L$0196,%r0 ;# 9200 switch_jump ldw 0(%r5),%r4 ;# 8027 reload_outsi+2/5 L$0990 bl L$0076,%r0 nop ;# 9203 switch_jump L$0991 bl L$0076,%r0 nop ;# 9206 switch_jump L$0992 bl L$0076,%r0 nop ;# 9209 switch_jump L$0993 bl L$0076,%r0 nop ;# 9212 switch_jump L$0994 bl L$0076,%r0 nop ;# 9215 switch_jump L$0995 bl L$0076,%r0 nop ;# 9218 switch_jump L$0996 bl L$0076,%r0 nop ;# 9221 switch_jump L$0997 bl L$0076,%r0 nop ;# 9224 switch_jump L$0998 bl L$0076,%r0 nop ;# 9227 switch_jump L$0999 bl L$0076,%r0 nop ;# 9230 switch_jump L$1000 bl L$0076,%r0 nop ;# 9233 switch_jump L$1001 bl L$0076,%r0 nop ;# 9236 switch_jump L$1002 bl L$0076,%r0 nop ;# 9239 switch_jump L$1003 bl L$0076,%r0 nop ;# 9242 switch_jump L$1004 bl L$0076,%r0 nop ;# 9245 switch_jump L$1005 bl L$0076,%r0 nop ;# 9248 switch_jump L$1006 bl L$0101,%r0 ;# 9251 switch_jump ldi 1026,%r19 ;# 662 reload_outsi+2/2 L$1007 bl L$0076,%r0 nop ;# 9254 switch_jump L$1008 bl L$0076,%r0 nop ;# 9257 switch_jump L$1009 bl L$0076,%r0 nop ;# 9260 switch_jump L$1010 bl L$0076,%r0 nop ;# 9263 switch_jump L$1011 bl L$0076,%r0 nop ;# 9266 switch_jump L$1012 bl L$0076,%r0 nop ;# 9269 switch_jump L$1013 bl L$0076,%r0 nop ;# 9272 switch_jump L$1014 bl L$0076,%r0 nop ;# 9275 switch_jump L$1015 bl L$0076,%r0 nop ;# 9278 switch_jump L$1016 bl L$0076,%r0 nop ;# 9281 switch_jump L$1017 bl L$0076,%r0 nop ;# 9284 switch_jump L$1018 bl L$0076,%r0 nop ;# 9287 switch_jump L$1019 bl L$0076,%r0 nop ;# 9290 switch_jump L$1020 bl L$0076,%r0 nop ;# 9293 switch_jump L$1021 bl L$0076,%r0 nop ;# 9296 switch_jump L$1022 bl L$0076,%r0 nop ;# 9299 switch_jump L$1023 bl L$0076,%r0 nop ;# 9302 switch_jump L$1024 bl L$0076,%r0 nop ;# 9305 switch_jump L$1025 bl L$0076,%r0 nop ;# 9308 switch_jump L$1026 bl L$0076,%r0 nop ;# 9311 switch_jump L$1027 bl L$0076,%r0 nop ;# 9314 switch_jump L$1028 bl L$0076,%r0 nop ;# 9317 switch_jump L$1029 bl L$0076,%r0 nop ;# 9320 switch_jump L$1030 bl L$0076,%r0 nop ;# 9323 switch_jump L$1031 bl L$0076,%r0 nop ;# 9326 switch_jump L$1032 bl L$0076,%r0 nop ;# 9329 switch_jump L$1033 bl L$0076,%r0 nop ;# 9332 switch_jump L$1034 bl L$0216,%r0 ;# 9335 switch_jump ldw -296(%r30),%r19 ;# 2418 reload_outsi+2/5 L$1035 bl L$0387,%r0 ;# 9338 switch_jump ldw -296(%r30),%r19 ;# 3797 reload_outsi+2/5 L$1036 bl L$0076,%r0 nop ;# 9341 switch_jump L$1037 bl L$0053,%r0 ;# 9344 switch_jump ldw -276(%r30),%r1 ;# 8777 reload_outsi+2/5 L$1038 bl L$0076,%r0 nop ;# 9347 switch_jump L$1039 bl L$0076,%r0 nop ;# 9350 switch_jump L$1040 bl L$0076,%r0 nop ;# 9353 switch_jump L$1041 bl L$0076,%r0 nop ;# 9356 switch_jump L$1042 bl L$0076,%r0 nop ;# 9359 switch_jump L$1043 bl L$0076,%r0 nop ;# 9362 switch_jump L$1044 bl L$0076,%r0 nop ;# 9365 switch_jump L$1045 bl L$0076,%r0 nop ;# 9368 switch_jump L$1046 bl L$0076,%r0 nop ;# 9371 switch_jump L$1047 bl L$0076,%r0 nop ;# 9374 switch_jump L$1048 bl L$0076,%r0 nop ;# 9377 switch_jump L$1049 bl L$0076,%r0 nop ;# 9380 switch_jump L$1050 bl L$0076,%r0 nop ;# 9383 switch_jump L$1051 bl L$0076,%r0 nop ;# 9386 switch_jump L$1052 bl L$0076,%r0 nop ;# 9389 switch_jump L$1053 bl L$0076,%r0 nop ;# 9392 switch_jump L$1054 bl L$0076,%r0 nop ;# 9395 switch_jump L$1055 bl L$0076,%r0 nop ;# 9398 switch_jump L$1056 bl L$0076,%r0 nop ;# 9401 switch_jump L$1057 bl L$0076,%r0 nop ;# 9404 switch_jump L$1058 bl L$0076,%r0 nop ;# 9407 switch_jump L$1059 bl L$0076,%r0 nop ;# 9410 switch_jump L$1060 bl L$0076,%r0 nop ;# 9413 switch_jump L$1061 bl L$0076,%r0 nop ;# 9416 switch_jump L$1062 bl L$0076,%r0 nop ;# 9419 switch_jump L$1063 bl L$0076,%r0 nop ;# 9422 switch_jump L$1064 bl L$0076,%r0 nop ;# 9425 switch_jump L$1065 bl L$0076,%r0 nop ;# 9428 switch_jump L$1066 bl L$0383,%r0 ;# 9431 switch_jump ldi 4608,%r20 ;# 3778 reload_outsi+2/2 L$1067 bl L$0380,%r0 nop ;# 9434 switch_jump L$1068 bl,n L$0076,%r0 ;# 7899 jump L$0053 ldw -296(%r30),%r25 ;# 2343 reload_outsi+2/5 ldo 1(%r1),%r19 ;# 306 addsi3/2 comb,=,n %r19,%r25,L$0055 ;# 308 bleu+1 bb,< %r15,28,L$0055 ;# 313 bleu+3 ldw -276(%r30),%r26 ;# 315 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl at_begline_loc_p,%r2 ;# 321 call_value_internal_symref copy %r15,%r24 ;# 319 reload_outsi+2/1 extrs %r28,31,8,%r28 ;# 324 extendqisi2 comiclr,<> 0,%r28,%r0 ;# 326 bleu+1 bl,n L$0076,%r0 L$0055 ldw 0(%r5),%r4 ;# 7986 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7989 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7987 subsi3/1 ldo 1(%r19),%r19 ;# 7988 addsi3/2 comb,>>=,n %r20,%r19,L$0060 ;# 7990 bleu+1 ldil L'65536,%r3 ;# 8701 reload_outsi+2/3 L$0061 comclr,<> %r3,%r20,%r0 ;# 357 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 367 ashlsi3+1 comb,>>= %r3,%r19,L$0066 ;# 375 bleu+1 stw %r19,4(%r5) ;# 369 reload_outsi+2/6 stw %r3,4(%r5) ;# 378 reload_outsi+2/6 L$0066 ldw 0(%r5),%r26 ;# 385 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 389 call_value_internal_symref ldw 4(%r5),%r25 ;# 387 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 397 bleu+1 stw %r28,0(%r5) ;# 393 reload_outsi+2/6 comb,= %r28,%r4,L$0059 ;# 407 bleu+1 sub %r6,%r4,%r19 ;# 409 subsi3/1 addl %r28,%r19,%r6 ;# 412 addsi3/1 sub %r12,%r4,%r19 ;# 413 subsi3/1 comib,= 0,%r10,L$0069 ;# 418 bleu+1 addl %r28,%r19,%r12 ;# 416 addsi3/1 sub %r10,%r4,%r19 ;# 419 subsi3/1 addl %r28,%r19,%r10 ;# 422 addsi3/1 L$0069 comib,= 0,%r8,L$0070 ;# 425 bleu+1 sub %r8,%r4,%r19 ;# 426 subsi3/1 addl %r28,%r19,%r8 ;# 429 addsi3/1 L$0070 comib,= 0,%r9,L$0059 ;# 432 bleu+1 sub %r9,%r4,%r19 ;# 433 subsi3/1 addl %r28,%r19,%r9 ;# 436 addsi3/1 L$0059 ldw 0(%r5),%r4 ;# 337 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 341 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 338 subsi3/1 ldo 1(%r19),%r19 ;# 339 addsi3/2 comb,<< %r20,%r19,L$0061 nop ;# 343 bleu+1 L$0060 ldi 8,%r19 ;# 458 movqi+1/2 bl L$0043,%r0 ;# 479 jump stbs,ma %r19,1(%r6) ;# 459 movqi+1/6 L$0077 comb,=,n %r16,%r26,L$0079 ;# 485 bleu+1 bb,< %r15,28,L$0079 ;# 490 bleu+3 copy %r16,%r25 ;# 494 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl at_endline_loc_p,%r2 ;# 498 call_value_internal_symref copy %r15,%r24 ;# 496 reload_outsi+2/1 extrs %r28,31,8,%r28 ;# 501 extendqisi2 comiclr,<> 0,%r28,%r0 ;# 503 bleu+1 bl,n L$0076,%r0 L$0079 ldw 0(%r5),%r4 ;# 7994 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7997 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7995 subsi3/1 ldo 1(%r19),%r19 ;# 7996 addsi3/2 comb,>>=,n %r20,%r19,L$0084 ;# 7998 bleu+1 ldil L'65536,%r3 ;# 8699 reload_outsi+2/3 L$0085 comclr,<> %r3,%r20,%r0 ;# 534 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 544 ashlsi3+1 comb,>>= %r3,%r19,L$0090 ;# 552 bleu+1 stw %r19,4(%r5) ;# 546 reload_outsi+2/6 stw %r3,4(%r5) ;# 555 reload_outsi+2/6 L$0090 ldw 0(%r5),%r26 ;# 562 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 566 call_value_internal_symref ldw 4(%r5),%r25 ;# 564 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 574 bleu+1 stw %r28,0(%r5) ;# 570 reload_outsi+2/6 comb,= %r28,%r4,L$0083 ;# 584 bleu+1 sub %r6,%r4,%r19 ;# 586 subsi3/1 addl %r28,%r19,%r6 ;# 589 addsi3/1 sub %r12,%r4,%r19 ;# 590 subsi3/1 comib,= 0,%r10,L$0093 ;# 595 bleu+1 addl %r28,%r19,%r12 ;# 593 addsi3/1 sub %r10,%r4,%r19 ;# 596 subsi3/1 addl %r28,%r19,%r10 ;# 599 addsi3/1 L$0093 comib,= 0,%r8,L$0094 ;# 602 bleu+1 sub %r8,%r4,%r19 ;# 603 subsi3/1 addl %r28,%r19,%r8 ;# 606 addsi3/1 L$0094 comib,= 0,%r9,L$0083 ;# 609 bleu+1 sub %r9,%r4,%r19 ;# 610 subsi3/1 addl %r28,%r19,%r9 ;# 613 addsi3/1 L$0083 ldw 0(%r5),%r4 ;# 514 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 518 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 515 subsi3/1 ldo 1(%r19),%r19 ;# 516 addsi3/2 comb,<< %r20,%r19,L$0085 nop ;# 520 bleu+1 L$0084 ldi 9,%r19 ;# 635 movqi+1/2 bl L$0043,%r0 ;# 656 jump stbs,ma %r19,1(%r6) ;# 636 movqi+1/6 L$0877 bl L$0110,%r0 ;# 897 jump stw %r21,-296(%r30) ;# 2391 reload_outsi+2/6 L$0101 L$1158 and %r15,%r19,%r19 ;# 663 andsi3/1 comiclr,= 0,%r19,%r0 ;# 665 bleu+1 bl,n L$0076,%r0 L$0104 comib,<> 0,%r8,L$0105 ;# 674 bleu+1 ldi 0,%r13 ;# 711 reload_outsi+2/2 extrs,>= %r15,26,1,%r0 ;# 681 bleu+3 extrs,< %r15,27,1,%r0 ;# 700 movsi-4 nop bl,n L$0076,%r0 L$0105 ldi 0,%r11 ;# 714 reload_outsi+2/2 ldi 0,%r22 ;# 716 reload_outsi+2/2 ldi 43,%r24 ;# 8688 reload_outsi+2/2 ldi 63,%r23 ;# 8690 reload_outsi+2/2 ldi 42,%r28 ;# 8692 reload_outsi+2/2 ldi 2,%r19 ;# 8694 reload_outsi+2/2 and %r15,%r19,%r25 ;# 8695 andsi3/1 ldi 92,%r26 ;# 8697 reload_outsi+2/2 L$0109 comb,= %r24,%r7,L$0112 ;# 727 bleu+1 copy %r11,%r19 ;# 8780 reload_outsi+2/1 depi -1,31,1,%r19 ;# 729 iorsi3+1/2 bl L$0113,%r0 ;# 731 jump extrs %r19,31,8,%r19 ;# 730 extendqisi2 L$0112 extrs %r11,31,8,%r19 ;# 734 extendqisi2 L$0113 L$1159 comb,= %r23,%r7,L$0114 ;# 744 bleu+1 copy %r19,%r11 ;# 737 reload_outsi+2/1 copy %r22,%r19 ;# 8783 reload_outsi+2/1 depi -1,31,1,%r19 ;# 746 iorsi3+1/2 bl L$0115,%r0 ;# 748 jump extrs %r19,31,8,%r19 ;# 747 extendqisi2 L$0114 extrs %r22,31,8,%r19 ;# 751 extendqisi2 L$0115 ldw -296(%r30),%r21 ;# 2355 reload_outsi+2/5 comb,= %r16,%r21,L$0110 ;# 757 bleu+1 copy %r19,%r22 ;# 754 reload_outsi+2/1 copy %r21,%r20 ;# 8743 reload_outsi+2/1 ldbs,ma 1(%r20),%r7 ;# 776 zero_extendqisi2/2 comib,= 0,%r14,L$0118 ;# 781 bleu+1 stw %r20,-296(%r30) ;# 2364 reload_outsi+2/6 addl %r14,%r7,%r19 ;# 782 addsi3/1 ldb 0(%r19),%r7 ;# 785 zero_extendqisi2/2 L$0118 comb,= %r28,%r7,L$0109 nop ;# 802 bleu+1 comib,<>,n 0,%r25,L$0869 ;# 807 bleu+1 comb,= %r24,%r7,L$1159 ;# 811 bleu+1 extrs %r11,31,8,%r19 ;# 734 extendqisi2 comb,= %r23,%r7,L$0109 ;# 815 bleu+1 ldw -296(%r30),%r19 ;# 2400 reload_outsi+2/5 bl,n L$1160,%r0 ;# 827 jump L$0869 comb,<> %r26,%r7,L$0126 ;# 831 bleu+1 ldw -296(%r30),%r19 ;# 2400 reload_outsi+2/5 comclr,<> %r16,%r20,%r0 ;# 835 bleu+1 bl L$0903,%r0 ldo 1(%r20),%r19 ;# 863 addsi3/2 ldb 1(%r21),%r3 ;# 860 zero_extendqisi2/2 comib,= 0,%r14,L$0129 ;# 865 bleu+1 stw %r19,-296(%r30) ;# 2379 reload_outsi+2/6 addl %r14,%r3,%r19 ;# 866 addsi3/1 ldb 0(%r19),%r3 ;# 869 zero_extendqisi2/2 L$0129 comb,= %r24,%r3,L$0109 ;# 886 bleu+1 copy %r3,%r7 ;# 903 reload_outsi+2/1 comb,<> %r23,%r3,L$0877 nop ;# 890 bleu+1 bl,n L$0109,%r0 ;# 905 jump L$0126 L$1160 ldo -1(%r19),%r19 ;# 910 addsi3/2 stw %r19,-296(%r30) ;# 2397 reload_outsi+2/6 L$0110 comiclr,<> 0,%r8,%r0 ;# 927 bleu+1 bl L$1161,%r0 ldw -296(%r30),%r19 ;# 2328 reload_outsi+2/5 comib,=,n 0,%r22,L$0137 ;# 934 bleu+1 ldw 0(%r5),%r3 ;# 8002 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8005 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8003 subsi3/1 ldo 3(%r19),%r19 ;# 8004 addsi3/2 comb,>>=,n %r20,%r19,L$0139 ;# 8006 bleu+1 ldil L'65536,%r4 ;# 8686 reload_outsi+2/3 L$0140 comclr,<> %r4,%r20,%r0 ;# 961 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 971 ashlsi3+1 comb,>>= %r4,%r19,L$0145 ;# 979 bleu+1 stw %r19,4(%r5) ;# 973 reload_outsi+2/6 stw %r4,4(%r5) ;# 982 reload_outsi+2/6 L$0145 ldw 0(%r5),%r26 ;# 989 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 993 call_value_internal_symref ldw 4(%r5),%r25 ;# 991 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1001 bleu+1 stw %r28,0(%r5) ;# 997 reload_outsi+2/6 comb,= %r28,%r3,L$0138 ;# 1011 bleu+1 sub %r6,%r3,%r19 ;# 1013 subsi3/1 addl %r28,%r19,%r6 ;# 1016 addsi3/1 sub %r12,%r3,%r19 ;# 1017 subsi3/1 comib,= 0,%r10,L$0148 ;# 1022 bleu+1 addl %r28,%r19,%r12 ;# 1020 addsi3/1 sub %r10,%r3,%r19 ;# 1023 subsi3/1 addl %r28,%r19,%r10 ;# 1026 addsi3/1 L$0148 comib,= 0,%r8,L$0149 ;# 1029 bleu+1 sub %r8,%r3,%r19 ;# 1030 subsi3/1 addl %r28,%r19,%r8 ;# 1033 addsi3/1 L$0149 comib,= 0,%r9,L$0138 ;# 1036 bleu+1 sub %r9,%r3,%r19 ;# 1037 subsi3/1 addl %r28,%r19,%r9 ;# 1040 addsi3/1 L$0138 ldw 0(%r5),%r3 ;# 941 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 945 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 942 subsi3/1 ldo 3(%r19),%r19 ;# 943 addsi3/2 comb,<< %r20,%r19,L$0140 nop ;# 947 bleu+1 L$0139 comib,= 0,%r14,L$0154 ;# 1063 bleu+1 ldw -296(%r30),%r19 ;# 2403 reload_outsi+2/5 ldb -2(%r19),%r19 ;# 1066 zero_extendqisi2/2 addl %r14,%r19,%r19 ;# 1067 addsi3/1 bl L$0947,%r0 ;# 1071 jump ldb 0(%r19),%r19 ;# 1069 movqi+1/5 L$0154 ldb -2(%r19),%r19 ;# 1075 movqi+1/5 L$0947 comib,= 0,%r14,L$0156 ;# 1079 bleu+1 extrs %r19,31,8,%r20 ;# 1076 extendqisi2 ldb 46(%r14),%r19 ;# 1081 movqi+1/5 extrs %r19,31,8,%r19 ;# 1082 extendqisi2 comb,= %r19,%r20,L$0157 ;# 1084 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 bl,n L$1162,%r0 ;# 1085 jump L$0156 ldi 46,%r19 ;# 1089 reload_outsi+2/2 comb,<> %r19,%r20,L$1162 ;# 1091 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 L$0157 comib,= 0,%r11,L$0153 ;# 1096 bleu+1 ldw -296(%r30),%r19 ;# 2409 reload_outsi+2/5 comb,<<= %r16,%r19,L$1162 ;# 1098 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 comib,=,n 0,%r14,L$0158 ;# 1100 bleu+1 ldb 0(%r19),%r19 ;# 1103 zero_extendqisi2/2 addl %r14,%r19,%r19 ;# 1104 addsi3/1 L$0158 ldb 0(%r19),%r19 ;# 1112 movqi+1/5 comib,= 0,%r14,L$0160 ;# 1116 bleu+1 extrs %r19,31,8,%r20 ;# 1113 extendqisi2 ldb 10(%r14),%r19 ;# 1118 movqi+1/5 extrs %r19,31,8,%r19 ;# 1119 extendqisi2 comb,= %r19,%r20,L$0161 ;# 1121 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 bl,n L$1162,%r0 ;# 1122 jump L$0160 comib,<> 10,%r20,L$1162 ;# 1126 bleu+1 ldi 17,%r26 ;# 1159 reload_outsi+2/2 L$0161 bb,< %r15,25,L$1162 ;# 1134 bleu+3 ldi 17,%r26 ;# 1159 reload_outsi+2/2 ldi 12,%r26 ;# 1140 reload_outsi+2/2 copy %r6,%r25 ;# 1142 reload_outsi+2/1 sub %r8,%r6,%r24 ;# 1137 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 1146 call_internal_symref ldo -3(%r24),%r24 ;# 1144 addsi3/2 bl L$0162,%r0 ;# 1151 jump ldi 1,%r13 ;# 1149 reload_outsi+2/2 L$0153 ldi 17,%r26 ;# 1159 reload_outsi+2/2 L$1162 copy %r6,%r25 ;# 1161 reload_outsi+2/1 sub %r8,%r6,%r24 ;# 1156 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 1165 call_internal_symref ldo -6(%r24),%r24 ;# 1163 addsi3/2 L$0162 ldo 3(%r6),%r6 ;# 1168 addsi3/2 L$0137 ldw 0(%r5),%r3 ;# 8010 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8013 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8011 subsi3/1 ldo 3(%r19),%r19 ;# 8012 addsi3/2 comb,>>=,n %r20,%r19,L$0164 ;# 8014 bleu+1 ldil L'65536,%r4 ;# 8684 reload_outsi+2/3 L$0165 comclr,<> %r4,%r20,%r0 ;# 1195 bleu+1 bl L$0944,%r0 zdep %r20,30,31,%r19 ;# 1205 ashlsi3+1 comb,>>= %r4,%r19,L$0170 ;# 1213 bleu+1 stw %r19,4(%r5) ;# 1207 reload_outsi+2/6 stw %r4,4(%r5) ;# 1216 reload_outsi+2/6 L$0170 ldw 0(%r5),%r26 ;# 1223 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1227 call_value_internal_symref ldw 4(%r5),%r25 ;# 1225 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1235 bleu+1 stw %r28,0(%r5) ;# 1231 reload_outsi+2/6 comb,= %r28,%r3,L$0163 ;# 1245 bleu+1 sub %r6,%r3,%r19 ;# 1247 subsi3/1 addl %r28,%r19,%r6 ;# 1250 addsi3/1 sub %r12,%r3,%r19 ;# 1251 subsi3/1 comib,= 0,%r10,L$0173 ;# 1256 bleu+1 addl %r28,%r19,%r12 ;# 1254 addsi3/1 sub %r10,%r3,%r19 ;# 1257 subsi3/1 addl %r28,%r19,%r10 ;# 1260 addsi3/1 L$0173 comib,= 0,%r8,L$0174 ;# 1263 bleu+1 sub %r8,%r3,%r19 ;# 1264 subsi3/1 addl %r28,%r19,%r8 ;# 1267 addsi3/1 L$0174 comib,= 0,%r9,L$0163 ;# 1270 bleu+1 sub %r9,%r3,%r19 ;# 1271 subsi3/1 addl %r28,%r19,%r9 ;# 1274 addsi3/1 L$0163 ldw 0(%r5),%r3 ;# 1175 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1179 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 1176 subsi3/1 ldo 3(%r19),%r19 ;# 1177 addsi3/2 comb,<< %r20,%r19,L$0165 nop ;# 1181 bleu+1 L$0164 ldi 14,%r26 ;# 8786 reload_outsi+2/2 comiclr,= 0,%r13,%r0 ;# 1310 beq-1/2 ldi 15,%r26 copy %r8,%r25 ;# 1312 reload_outsi+2/1 sub %r6,%r8,%r24 ;# 1314 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 1318 call_internal_symref copy %r6,%r23 ;# 1316 reload_outsi+2/1 ldi 0,%r9 ;# 1321 reload_outsi+2/2 comib,<> 0,%r11,L$0043 ;# 1326 bleu+1 ldo 3(%r6),%r6 ;# 1323 addsi3/2 ldw 0(%r5),%r3 ;# 8019 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8022 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8020 subsi3/1 ldo 3(%r19),%r19 ;# 8021 addsi3/2 comb,>>=,n %r20,%r19,L$0182 ;# 8023 bleu+1 ldil L'65536,%r4 ;# 8682 reload_outsi+2/3 L$0183 comb,= %r4,%r20,L$0944 ;# 1352 bleu+1 zdep %r20,30,31,%r19 ;# 1362 ashlsi3+1 comb,>>= %r4,%r19,L$0188 ;# 1370 bleu+1 stw %r19,4(%r5) ;# 1364 reload_outsi+2/6 stw %r4,4(%r5) ;# 1373 reload_outsi+2/6 L$0188 ldw 0(%r5),%r26 ;# 1380 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1384 call_value_internal_symref ldw 4(%r5),%r25 ;# 1382 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1392 bleu+1 stw %r28,0(%r5) ;# 1388 reload_outsi+2/6 comb,= %r28,%r3,L$0181 ;# 1402 bleu+1 sub %r6,%r3,%r19 ;# 1404 subsi3/1 addl %r28,%r19,%r6 ;# 1407 addsi3/1 sub %r12,%r3,%r19 ;# 1408 subsi3/1 comib,= 0,%r10,L$0191 ;# 1413 bleu+1 addl %r28,%r19,%r12 ;# 1411 addsi3/1 sub %r10,%r3,%r19 ;# 1414 subsi3/1 addl %r28,%r19,%r10 ;# 1417 addsi3/1 L$0191 comib,= 0,%r8,L$0192 ;# 1420 bleu+1 sub %r8,%r3,%r19 ;# 1421 subsi3/1 addl %r28,%r19,%r8 ;# 1424 addsi3/1 L$0192 comib,= 0,%r9,L$0181 ;# 1427 bleu+1 sub %r9,%r3,%r19 ;# 1428 subsi3/1 addl %r28,%r19,%r9 ;# 1431 addsi3/1 L$0181 ldw 0(%r5),%r3 ;# 1332 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1336 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 1333 subsi3/1 ldo 3(%r19),%r19 ;# 1334 addsi3/2 comb,<< %r20,%r19,L$0183 nop ;# 1338 bleu+1 L$0182 ldi 18,%r26 ;# 1454 reload_outsi+2/2 copy %r8,%r25 ;# 1456 reload_outsi+2/1 ldi 3,%r24 ;# 1458 reload_outsi+2/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 1462 call_internal_symref copy %r6,%r23 ;# 1460 reload_outsi+2/1 bl L$0043,%r0 ;# 1470 jump ldo 3(%r6),%r6 ;# 1464 addsi3/2 L$0196 ldw 4(%r5),%r20 ;# 8030 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8028 subsi3/1 ldo 1(%r19),%r19 ;# 8029 addsi3/2 comb,>>= %r20,%r19,L$0201 ;# 8031 bleu+1 copy %r6,%r8 ;# 1475 reload_outsi+2/1 ldil L'65536,%r3 ;# 8680 reload_outsi+2/3 L$0202 comb,= %r3,%r20,L$0944 ;# 1503 bleu+1 zdep %r20,30,31,%r19 ;# 1513 ashlsi3+1 comb,>>= %r3,%r19,L$0207 ;# 1521 bleu+1 stw %r19,4(%r5) ;# 1515 reload_outsi+2/6 stw %r3,4(%r5) ;# 1524 reload_outsi+2/6 L$0207 ldw 0(%r5),%r26 ;# 1531 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1535 call_value_internal_symref ldw 4(%r5),%r25 ;# 1533 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1543 bleu+1 stw %r28,0(%r5) ;# 1539 reload_outsi+2/6 comb,= %r28,%r4,L$0200 ;# 1553 bleu+1 sub %r6,%r4,%r19 ;# 1555 subsi3/1 addl %r28,%r19,%r6 ;# 1558 addsi3/1 sub %r12,%r4,%r19 ;# 1559 subsi3/1 comib,= 0,%r10,L$0210 ;# 1564 bleu+1 addl %r28,%r19,%r12 ;# 1562 addsi3/1 sub %r10,%r4,%r19 ;# 1565 subsi3/1 addl %r28,%r19,%r10 ;# 1568 addsi3/1 L$0210 comib,= 0,%r8,L$0211 ;# 1571 bleu+1 sub %r8,%r4,%r19 ;# 1572 subsi3/1 addl %r28,%r19,%r8 ;# 1575 addsi3/1 L$0211 comib,= 0,%r9,L$0200 ;# 1578 bleu+1 sub %r9,%r4,%r19 ;# 1579 subsi3/1 addl %r28,%r19,%r9 ;# 1582 addsi3/1 L$0200 ldw 0(%r5),%r4 ;# 1483 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1487 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 1484 subsi3/1 ldo 1(%r19),%r19 ;# 1485 addsi3/2 comb,<< %r20,%r19,L$0202 nop ;# 1489 bleu+1 L$0201 ldi 2,%r19 ;# 1604 movqi+1/2 bl L$0043,%r0 ;# 1617 jump stbs,ma %r19,1(%r6) ;# 1605 movqi+1/6 L$0216 comb,= %r16,%r19,L$0902 ;# 1626 bleu+1 ldi 0,%r13 ;# 1623 reload_outsi+2/2 ldw 0(%r5),%r3 ;# 8035 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8038 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8036 subsi3/1 ldo 34(%r19),%r19 ;# 8037 addsi3/2 comb,>>= %r20,%r19,L$0219 ;# 8039 bleu+1 ldil L'65536,%r4 ;# 8678 reload_outsi+2/3 L$0220 comb,= %r4,%r20,L$0944 ;# 1661 bleu+1 zdep %r20,30,31,%r19 ;# 1671 ashlsi3+1 comb,>>= %r4,%r19,L$0225 ;# 1679 bleu+1 stw %r19,4(%r5) ;# 1673 reload_outsi+2/6 stw %r4,4(%r5) ;# 1682 reload_outsi+2/6 L$0225 ldw 0(%r5),%r26 ;# 1689 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1693 call_value_internal_symref ldw 4(%r5),%r25 ;# 1691 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1701 bleu+1 stw %r28,0(%r5) ;# 1697 reload_outsi+2/6 comb,= %r28,%r3,L$0218 ;# 1711 bleu+1 sub %r6,%r3,%r19 ;# 1713 subsi3/1 addl %r28,%r19,%r6 ;# 1716 addsi3/1 sub %r12,%r3,%r19 ;# 1717 subsi3/1 comib,= 0,%r10,L$0228 ;# 1722 bleu+1 addl %r28,%r19,%r12 ;# 1720 addsi3/1 sub %r10,%r3,%r19 ;# 1723 subsi3/1 addl %r28,%r19,%r10 ;# 1726 addsi3/1 L$0228 comib,= 0,%r8,L$0229 ;# 1729 bleu+1 sub %r8,%r3,%r19 ;# 1730 subsi3/1 addl %r28,%r19,%r8 ;# 1733 addsi3/1 L$0229 comib,= 0,%r9,L$0218 ;# 1736 bleu+1 sub %r9,%r3,%r19 ;# 1737 subsi3/1 addl %r28,%r19,%r9 ;# 1740 addsi3/1 L$0218 ldw 0(%r5),%r3 ;# 1641 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1645 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 1642 subsi3/1 ldo 34(%r19),%r19 ;# 1643 addsi3/2 comb,<< %r20,%r19,L$0220 nop ;# 1647 bleu+1 L$0219 ldw 0(%r5),%r4 ;# 8043 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8046 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8044 subsi3/1 ldo 1(%r19),%r19 ;# 8045 addsi3/2 comb,>>= %r20,%r19,L$0237 ;# 8047 bleu+1 copy %r6,%r8 ;# 1763 reload_outsi+2/1 ldil L'65536,%r3 ;# 8676 reload_outsi+2/3 L$0238 comb,= %r3,%r20,L$0944 ;# 1791 bleu+1 zdep %r20,30,31,%r19 ;# 1801 ashlsi3+1 comb,>>= %r3,%r19,L$0243 ;# 1809 bleu+1 stw %r19,4(%r5) ;# 1803 reload_outsi+2/6 stw %r3,4(%r5) ;# 1812 reload_outsi+2/6 L$0243 ldw 0(%r5),%r26 ;# 1819 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1823 call_value_internal_symref ldw 4(%r5),%r25 ;# 1821 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 1831 bleu+1 stw %r28,0(%r5) ;# 1827 reload_outsi+2/6 comb,= %r28,%r4,L$0236 ;# 1841 bleu+1 sub %r6,%r4,%r19 ;# 1843 subsi3/1 addl %r28,%r19,%r6 ;# 1846 addsi3/1 sub %r12,%r4,%r19 ;# 1847 subsi3/1 comib,= 0,%r10,L$0246 ;# 1852 bleu+1 addl %r28,%r19,%r12 ;# 1850 addsi3/1 sub %r10,%r4,%r19 ;# 1853 subsi3/1 addl %r28,%r19,%r10 ;# 1856 addsi3/1 L$0246 comib,= 0,%r8,L$0247 ;# 1859 bleu+1 sub %r8,%r4,%r19 ;# 1860 subsi3/1 addl %r28,%r19,%r8 ;# 1863 addsi3/1 L$0247 comib,= 0,%r9,L$0236 ;# 1866 bleu+1 sub %r9,%r4,%r19 ;# 1867 subsi3/1 addl %r28,%r19,%r9 ;# 1870 addsi3/1 L$0236 ldw 0(%r5),%r4 ;# 1771 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1775 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 1772 subsi3/1 ldo 1(%r19),%r19 ;# 1773 addsi3/2 comb,<< %r20,%r19,L$0238 nop ;# 1777 bleu+1 L$0237 copy %r6,%r22 ;# 1909 reload_outsi+2/1 ldo 1(%r6),%r6 ;# 1891 addsi3/2 ldw -296(%r30),%r19 ;# 2421 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 1893 movqi+1/5 ldi 94,%r21 ;# 1896 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 1894 extendqisi2 comb,<> %r21,%r19,L$0251 ;# 1898 bleu+1 ldi 3,%r20 ;# 8051 movqi+1/2 ldi 4,%r20 ;# 1900 movqi+1/2 L$0251 stb %r20,0(%r22) ;# 1911 movqi+1/6 ldw -296(%r30),%r20 ;# 2424 reload_outsi+2/5 ldb 0(%r20),%r19 ;# 1923 movqi+1/5 extrs %r19,31,8,%r19 ;# 1924 extendqisi2 comb,<> %r21,%r19,L$0254 ;# 1928 bleu+1 ldo 1(%r20),%r19 ;# 1930 addsi3/2 stw %r19,-296(%r30) ;# 2427 reload_outsi+2/6 L$0254 ldw 0(%r5),%r4 ;# 8052 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8055 reload_outsi+2/5 ldw -296(%r30),%r1 ;# 2433 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8053 subsi3/1 ldo 1(%r19),%r19 ;# 8054 addsi3/2 comb,>>= %r20,%r19,L$0259 ;# 8056 bleu+1 stw %r1,-268(%r30) ;# 8789 reload_outsi+2/6 ldil L'65536,%r3 ;# 8674 reload_outsi+2/3 L$0260 comb,= %r3,%r20,L$0944 ;# 1962 bleu+1 zdep %r20,30,31,%r19 ;# 1972 ashlsi3+1 comb,>>= %r3,%r19,L$0265 ;# 1980 bleu+1 stw %r19,4(%r5) ;# 1974 reload_outsi+2/6 stw %r3,4(%r5) ;# 1983 reload_outsi+2/6 L$0265 ldw 0(%r5),%r26 ;# 1990 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 1994 call_value_internal_symref ldw 4(%r5),%r25 ;# 1992 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 2002 bleu+1 stw %r28,0(%r5) ;# 1998 reload_outsi+2/6 comb,= %r28,%r4,L$0258 ;# 2012 bleu+1 sub %r6,%r4,%r19 ;# 2014 subsi3/1 addl %r28,%r19,%r6 ;# 2017 addsi3/1 sub %r12,%r4,%r19 ;# 2018 subsi3/1 comib,= 0,%r10,L$0268 ;# 2023 bleu+1 addl %r28,%r19,%r12 ;# 2021 addsi3/1 sub %r10,%r4,%r19 ;# 2024 subsi3/1 addl %r28,%r19,%r10 ;# 2027 addsi3/1 L$0268 comib,= 0,%r8,L$0269 ;# 2030 bleu+1 sub %r8,%r4,%r19 ;# 2031 subsi3/1 addl %r28,%r19,%r8 ;# 2034 addsi3/1 L$0269 comib,= 0,%r9,L$0258 ;# 2037 bleu+1 sub %r9,%r4,%r19 ;# 2038 subsi3/1 addl %r28,%r19,%r9 ;# 2041 addsi3/1 L$0258 ldw 0(%r5),%r4 ;# 1942 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 1946 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 1943 subsi3/1 ldo 1(%r19),%r19 ;# 1944 addsi3/2 comb,<< %r20,%r19,L$0260 nop ;# 1948 bleu+1 L$0259 ldi 32,%r19 ;# 2063 movqi+1/2 stbs,ma %r19,1(%r6) ;# 2064 movqi+1/6 copy %r6,%r26 ;# 2077 reload_outsi+2/1 ldi 0,%r25 ;# 2079 reload_outsi+2/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 ;# 2083 call_value_internal_symref ldi 32,%r24 ;# 2081 reload_outsi+2/2 ldb -2(%r6),%r19 ;# 2087 zero_extendqisi2/2 comib,<> 4,%r19,L$0274 ;# 2089 bleu+1 ldi 93,%r17 ;# 8622 reload_outsi+2/2 bb,>=,n %r15,23,L$0274 ;# 2094 movsi-4 ldb 1(%r6),%r19 ;# 2097 movqi+1/5 depi -1,29,1,%r19 ;# 2099 iorsi3+1/2 stb %r19,1(%r6) ;# 2101 movqi+1/6 L$0274 ldi 4,%r18 ;# 8628 reload_outsi+2/2 and %r15,%r18,%r1 ;# 8629 andsi3/1 stw %r1,-252(%r30) ;# 8792 reload_outsi+2/6 ldo -288(%r30),%r11 ;# 8632 addsi3/2 L$0275 ldw -296(%r30),%r20 ;# 2436 reload_outsi+2/5 L$1165 comb,= %r16,%r20,L$0902 ;# 2109 bleu+1 copy %r20,%r21 ;# 8745 reload_outsi+2/1 ldbs,ma 1(%r21),%r7 ;# 2134 zero_extendqisi2/2 comib,= 0,%r14,L$0280 ;# 2139 bleu+1 stw %r21,-296(%r30) ;# 2445 reload_outsi+2/6 addl %r14,%r7,%r19 ;# 2140 addsi3/1 ldb 0(%r19),%r7 ;# 2143 zero_extendqisi2/2 L$0280 bb,>= %r15,31,L$0285 ;# 2159 movsi-4 ldi 92,%r19 ;# 2161 reload_outsi+2/2 comb,<>,n %r19,%r7,L$0285 ;# 2163 bleu+1 comb,= %r16,%r21,L$0903 ;# 2167 bleu+1 ldo 1(%r21),%r19 ;# 2195 addsi3/2 ldb 1(%r20),%r3 ;# 2192 zero_extendqisi2/2 comib,= 0,%r14,L$0288 ;# 2197 bleu+1 stw %r19,-296(%r30) ;# 2460 reload_outsi+2/6 addl %r14,%r3,%r19 ;# 2198 addsi3/1 ldb 0(%r19),%r3 ;# 2201 zero_extendqisi2/2 L$0288 extru %r3,28,29,%r19 ;# 2216 lshrsi3/2 addl %r6,%r19,%r19 ;# 2219 addsi3/1 bl L$0948,%r0 ;# 2235 jump extru %r3,31,3,%r20 ;# 2222 andsi3/1 L$0285 comb,<>,n %r17,%r7,L$0293 ;# 2243 bleu+1 ldw -268(%r30),%r1 ;# 8798 reload_outsi+2/5 ldw -296(%r30),%r20 ;# 2466 reload_outsi+2/5 ldo 1(%r1),%r19 ;# 2244 addsi3/2 comb,<>,n %r19,%r20,L$0276 ;# 2246 bleu+1 L$0293 comib,= 0,%r13,L$0294 ;# 2253 bleu+1 ldi 45,%r1 ;# 8801 reload_outsi+2/2 comb,<> %r1,%r7,L$1163 ;# 2257 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 ldw -296(%r30),%r19 ;# 2469 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 2259 movqi+1/5 extrs %r19,31,8,%r19 ;# 2260 extendqisi2 comb,<>,n %r17,%r19,L$0895 ;# 2264 bleu+1 L$0294 ldi 45,%r1 ;# 8804 reload_outsi+2/2 comb,<> %r1,%r7,L$1163 ;# 2280 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 ldw -276(%r30),%r1 ;# 8807 reload_outsi+2/5 ldo -2(%r20),%r19 ;# 2281 addsi3/2 comb,>>,n %r1,%r19,L$1179 ;# 2283 bleu+1 ldb -2(%r20),%r19 ;# 2285 movqi+1/5 ldi 91,%r1 ;# 8810 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2286 extendqisi2 comb,= %r1,%r19,L$1163 ;# 2290 bleu+1 ldw -276(%r30),%r1 ;# 8813 reload_outsi+2/5 L$1179 ldo -3(%r20),%r19 ;# 2294 addsi3/2 comb,>>,n %r1,%r19,L$0297 ;# 2296 bleu+1 ldb -3(%r20),%r19 ;# 2298 movqi+1/5 ldi 91,%r1 ;# 8816 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2299 extendqisi2 comb,<> %r1,%r19,L$1164 ;# 2303 bleu+1 ldw -296(%r30),%r19 ;# 2487 reload_outsi+2/5 ldb -2(%r20),%r19 ;# 2305 movqi+1/5 ldi 94,%r20 ;# 2308 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2306 extendqisi2 comb,= %r20,%r19,L$1163 ;# 2310 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 L$0297 ldw -296(%r30),%r19 ;# 2487 reload_outsi+2/5 L$1164 ldb 0(%r19),%r19 ;# 2315 movqi+1/5 extrs %r19,31,8,%r19 ;# 2316 extendqisi2 comb,<> %r17,%r19,L$0302 ;# 2320 bleu+1 ldw -296(%r30),%r20 ;# 2524 reload_outsi+2/5 L$1163 ldb 0(%r20),%r19 ;# 2526 movqi+1/5 ldi 45,%r1 ;# 8819 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2527 extendqisi2 comb,<>,n %r1,%r19,L$0300 ;# 2531 bleu+1 ldb 1(%r20),%r19 ;# 2535 movqi+1/5 extrs %r19,31,8,%r19 ;# 2536 extendqisi2 comb,=,n %r17,%r19,L$0300 ;# 2540 bleu+1 comb,= %r16,%r20,L$0922 ;# 2550 bleu+1 ldo 1(%r20),%r19 ;# 2559 addsi3/2 stw %r19,-296(%r30) ;# 2561 reload_outsi+2/6 L$0302 stw %r6,-52(%r30) ;# 2588 reload_outsi+2/6 ldo -296(%r30),%r26 ;# 2590 addsi3/2 copy %r16,%r25 ;# 2592 reload_outsi+2/1 copy %r14,%r24 ;# 2594 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl compile_range,%r2 ;# 2598 call_value_internal_symref copy %r15,%r23 ;# 2596 reload_outsi+2/1 movb,= %r28,%r4,L$1165 ;# 2603 decrement_and_branch_until_zero+2/1 ldw -296(%r30),%r20 ;# 2436 reload_outsi+2/5 .CALL ARGW0=GR bl free,%r2 ;# 2607 call_internal_symref ldw -312(%r30),%r26 ;# 2605 reload_outsi+2/5 bl L$0867,%r0 ;# 2611 jump copy %r4,%r28 ;# 2609 reload_outsi+2/1 L$0300 ldw -252(%r30),%r1 ;# 8822 reload_outsi+2/5 comib,= 0,%r1,L$0309 ;# 2624 bleu+1 ldi 91,%r1 ;# 8825 reload_outsi+2/2 comb,<> %r1,%r7,L$1166 ;# 2628 bleu+1 ldi 0,%r13 ;# 3624 reload_outsi+2/2 ldw -296(%r30),%r20 ;# 2630 reload_outsi+2/5 ldb 0(%r20),%r19 ;# 2632 movqi+1/5 ldi 58,%r1 ;# 8828 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 2633 extendqisi2 comb,<>,n %r1,%r19,L$1166 ;# 2637 bleu+1 comb,= %r16,%r20,L$0922 ;# 2647 bleu+1 ldo 1(%r20),%r19 ;# 2656 addsi3/2 stw %r19,-296(%r30) ;# 2658 reload_outsi+2/6 comb,= %r16,%r19,L$0902 ;# 2689 bleu+1 ldi 0,%r3 ;# 2684 reload_outsi+2/2 L$0317 ldw -296(%r30),%r19 ;# 2709 reload_outsi+2/5 comb,= %r16,%r19,L$0922 ;# 2711 bleu+1 ldo 1(%r19),%r20 ;# 2720 addsi3/2 stw %r20,-296(%r30) ;# 2722 reload_outsi+2/6 comib,= 0,%r14,L$0321 ;# 2729 bleu+1 ldb 0(%r19),%r7 ;# 2725 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 2730 addsi3/1 ldb 0(%r19),%r7 ;# 2733 zero_extendqisi2/2 L$0321 ldi 58,%r1 ;# 8831 reload_outsi+2/2 comb,= %r1,%r7,L$1167 ;# 2750 bleu+1 addl %r11,%r3,%r19 ;# 2789 addsi3/1 comb,=,n %r17,%r7,L$1167 ;# 2754 bleu+1 comb,=,n %r16,%r20,L$1167 ;# 2758 bleu+1 comib,= 6,%r3,L$1167 ;# 2760 bleu+1 copy %r3,%r20 ;# 2770 reload_outsi+2/1 ldo 1(%r20),%r19 ;# 2771 addsi3/2 extru %r19,31,8,%r3 ;# 2772 zero_extendqisi2/1 addl %r11,%r20,%r20 ;# 2776 addsi3/1 bl L$0317,%r0 ;# 2783 jump stb %r7,0(%r20) ;# 2778 movqi+1/6 L$1167 comb,<> %r1,%r7,L$0328 ;# 2796 bleu+1 stb %r0,0(%r19) ;# 2791 movqi+1/6 ldw -296(%r30),%r19 ;# 2798 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 2800 movqi+1/5 extrs %r19,31,8,%r19 ;# 2801 extendqisi2 comb,<> %r17,%r19,L$1168 ;# 2805 bleu+1 ldi 255,%r19 ;# 8069 reload_outsi+2/2 copy %r11,%r26 ;# 2813 reload_outsi+2/1 ldil LR'L$C0016,%r1 ;# 8835 add_high_const+3 ldo RR'L$C0016(%r1),%r1 ;# 8836 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2817 call_value_internal_symref copy %r1,%r25 ;# 2815 reload_outsi+2/1 copy %r11,%r26 ;# 2829 reload_outsi+2/1 ldil LR'L$C0017,%r1 ;# 8837 add_high_const+3 ldo RR'L$C0017(%r1),%r1 ;# 8838 movhi-2 copy %r1,%r25 ;# 2831 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2821 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2833 call_value_internal_symref stw %r28,-244(%r30) ;# 8841 reload_outsi+2/6 copy %r11,%r26 ;# 2845 reload_outsi+2/1 ldil LR'L$C0018,%r1 ;# 8842 add_high_const+3 ldo RR'L$C0018(%r1),%r1 ;# 8843 movhi-2 copy %r1,%r25 ;# 2847 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2837 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2849 call_value_internal_symref stw %r28,-236(%r30) ;# 8846 reload_outsi+2/6 copy %r11,%r26 ;# 2861 reload_outsi+2/1 ldil LR'L$C0019,%r1 ;# 8847 add_high_const+3 ldo RR'L$C0019(%r1),%r1 ;# 8848 movhi-2 copy %r1,%r25 ;# 2863 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2853 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2865 call_value_internal_symref stw %r28,-228(%r30) ;# 8851 reload_outsi+2/6 copy %r11,%r26 ;# 2877 reload_outsi+2/1 ldil LR'L$C0020,%r1 ;# 8852 add_high_const+3 ldo RR'L$C0020(%r1),%r1 ;# 8853 movhi-2 copy %r1,%r25 ;# 2879 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2869 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2881 call_value_internal_symref stw %r28,-220(%r30) ;# 8856 reload_outsi+2/6 copy %r11,%r26 ;# 2893 reload_outsi+2/1 ldil LR'L$C0021,%r1 ;# 8857 add_high_const+3 ldo RR'L$C0021(%r1),%r1 ;# 8858 movhi-2 copy %r1,%r25 ;# 2895 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2885 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2897 call_value_internal_symref stw %r28,-212(%r30) ;# 8861 reload_outsi+2/6 copy %r11,%r26 ;# 2909 reload_outsi+2/1 ldil LR'L$C0022,%r1 ;# 8862 add_high_const+3 ldo RR'L$C0022(%r1),%r1 ;# 8863 movhi-2 copy %r1,%r25 ;# 2911 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2901 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2913 call_value_internal_symref stw %r28,-204(%r30) ;# 8866 reload_outsi+2/6 copy %r11,%r26 ;# 2925 reload_outsi+2/1 ldil LR'L$C0023,%r1 ;# 8867 add_high_const+3 ldo RR'L$C0023(%r1),%r1 ;# 8868 movhi-2 copy %r1,%r25 ;# 2927 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2917 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2929 call_value_internal_symref stw %r28,-196(%r30) ;# 8871 reload_outsi+2/6 copy %r11,%r26 ;# 2941 reload_outsi+2/1 ldil LR'L$C0024,%r1 ;# 8872 add_high_const+3 ldo RR'L$C0024(%r1),%r1 ;# 8873 movhi-2 copy %r1,%r25 ;# 2943 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2933 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2945 call_value_internal_symref stw %r28,-188(%r30) ;# 8876 reload_outsi+2/6 copy %r11,%r26 ;# 2957 reload_outsi+2/1 ldil LR'L$C0025,%r1 ;# 8877 add_high_const+3 ldo RR'L$C0025(%r1),%r1 ;# 8878 movhi-2 copy %r1,%r25 ;# 2959 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2949 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2961 call_value_internal_symref stw %r28,-180(%r30) ;# 8881 reload_outsi+2/6 copy %r11,%r26 ;# 2973 reload_outsi+2/1 ldil LR'L$C0026,%r19 ;# 2970 add_high_const+3 ldo RR'L$C0026(%r19),%r3 ;# 2971 movhi-2 copy %r3,%r25 ;# 2975 reload_outsi+2/1 comiclr,<> 0,%r28,%r28 ;# 2965 scc ldi 1,%r28 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2977 call_value_internal_symref stw %r28,-172(%r30) ;# 8884 reload_outsi+2/6 copy %r11,%r26 ;# 2989 reload_outsi+2/1 ldil LR'L$C0027,%r19 ;# 2986 add_high_const+3 ldo RR'L$C0027(%r19),%r4 ;# 2987 movhi-2 comiclr,<> 0,%r28,%r13 ;# 2981 scc ldi 1,%r13 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 2993 call_value_internal_symref copy %r4,%r25 ;# 2991 reload_outsi+2/1 copy %r11,%r26 ;# 3005 reload_outsi+2/1 ldil LR'L$C0017,%r1 ;# 8885 add_high_const+3 ldo RR'L$C0017(%r1),%r1 ;# 8886 movhi-2 comiclr,<> 0,%r28,%r7 ;# 2997 scc ldi 1,%r7 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3009 call_value_internal_symref copy %r1,%r25 ;# 3007 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3013 bleu+1 copy %r11,%r26 ;# 3018 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3022 call_value_internal_symref copy %r3,%r25 ;# 3020 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3026 bleu+1 copy %r11,%r26 ;# 3031 reload_outsi+2/1 ldil LR'L$C0022,%r1 ;# 8887 add_high_const+3 ldo RR'L$C0022(%r1),%r1 ;# 8888 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3035 call_value_internal_symref copy %r1,%r25 ;# 3033 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3039 bleu+1 copy %r11,%r26 ;# 3044 reload_outsi+2/1 ldil LR'L$C0020,%r1 ;# 8889 add_high_const+3 ldo RR'L$C0020(%r1),%r1 ;# 8890 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3048 call_value_internal_symref copy %r1,%r25 ;# 3046 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3052 bleu+1 copy %r11,%r26 ;# 3057 reload_outsi+2/1 ldil LR'L$C0016,%r1 ;# 8891 add_high_const+3 ldo RR'L$C0016(%r1),%r1 ;# 8892 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3061 call_value_internal_symref copy %r1,%r25 ;# 3059 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3065 bleu+1 copy %r11,%r26 ;# 3070 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3074 call_value_internal_symref copy %r4,%r25 ;# 3072 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3078 bleu+1 copy %r11,%r26 ;# 3083 reload_outsi+2/1 ldil LR'L$C0025,%r1 ;# 8893 add_high_const+3 ldo RR'L$C0025(%r1),%r1 ;# 8894 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3087 call_value_internal_symref copy %r1,%r25 ;# 3085 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3091 bleu+1 copy %r11,%r26 ;# 3096 reload_outsi+2/1 ldil LR'L$C0023,%r1 ;# 8895 add_high_const+3 ldo RR'L$C0023(%r1),%r1 ;# 8896 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3100 call_value_internal_symref copy %r1,%r25 ;# 3098 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3104 bleu+1 copy %r11,%r26 ;# 3109 reload_outsi+2/1 ldil LR'L$C0024,%r1 ;# 8897 add_high_const+3 ldo RR'L$C0024(%r1),%r1 ;# 8898 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3113 call_value_internal_symref copy %r1,%r25 ;# 3111 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3117 bleu+1 copy %r11,%r26 ;# 3122 reload_outsi+2/1 ldil LR'L$C0021,%r1 ;# 8899 add_high_const+3 ldo RR'L$C0021(%r1),%r1 ;# 8900 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3126 call_value_internal_symref copy %r1,%r25 ;# 3124 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3130 bleu+1 copy %r11,%r26 ;# 3135 reload_outsi+2/1 ldil LR'L$C0019,%r1 ;# 8901 add_high_const+3 ldo RR'L$C0019(%r1),%r1 ;# 8902 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3139 call_value_internal_symref copy %r1,%r25 ;# 3137 reload_outsi+2/1 comib,= 0,%r28,L$0329 ;# 3143 bleu+1 copy %r11,%r26 ;# 3148 reload_outsi+2/1 ldil LR'L$C0018,%r1 ;# 8903 add_high_const+3 ldo RR'L$C0018(%r1),%r1 ;# 8904 movhi-2 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 ;# 3152 call_value_internal_symref copy %r1,%r25 ;# 3150 reload_outsi+2/1 comib,<>,n 0,%r28,L$0900 ;# 3156 bleu+1 L$0329 ldw -296(%r30),%r19 ;# 3173 reload_outsi+2/5 comb,= %r16,%r19,L$0922 ;# 3175 bleu+1 ldo 1(%r19),%r19 ;# 3184 addsi3/2 comb,= %r16,%r19,L$0902 ;# 3214 bleu+1 stw %r19,-296(%r30) ;# 3186 reload_outsi+2/6 ldi 0,%r22 ;# 3227 reload_outsi+2/2 addil LR'__alnum-$global$,%r27 ;# 8596 pic2_lo_sum+1 copy %r1,%r2 ;# 8907 reload_outsi+2/1 addil LR'__ctype2-$global$,%r27 ;# 8598 pic2_lo_sum+1 copy %r1,%r23 ;# 8910 reload_outsi+2/1 addil LR'__ctype-$global$,%r27 ;# 8600 pic2_lo_sum+1 copy %r1,%r4 ;# 8913 reload_outsi+2/1 ldi 32,%r25 ;# 8605 reload_outsi+2/2 ldi 2,%r24 ;# 8607 reload_outsi+2/2 ldi 16,%r31 ;# 8609 reload_outsi+2/2 ldi 8,%r29 ;# 8611 reload_outsi+2/2 ldi 128,%r28 ;# 8613 reload_outsi+2/2 ldi 255,%r26 ;# 8615 reload_outsi+2/2 ldw -244(%r30),%r1 ;# 8916 reload_outsi+2/5 L$1173 comib,=,n 0,%r1,L$0343 ;# 3240 bleu+1 stw %r22,RR'__alnum-$global$(%r2) ;# 3244 reload_outsi+2/6 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3248 reload_outsi+2/5 ldw RR'__ctype-$global$(%r4),%r21 ;# 3260 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3253 addsi3/1 addl %r21,%r22,%r21 ;# 3265 addsi3/1 ldb 0(%r19),%r20 ;# 3255 movqi+1/5 ldb 0(%r21),%r19 ;# 3267 movqi+1/5 extru %r20,31,1,%r20 ;# 3256 andsi3/1 and %r19,%r18,%r19 ;# 3270 andsi3/1 or %r20,%r19,%r20 ;# 3278 xordi3-1 comib,<> 0,%r20,L$1169 ;# 3280 bleu+1 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 L$0343 ldw -236(%r30),%r1 ;# 8919 reload_outsi+2/5 comib,= 0,%r1,L$0344 ;# 3285 bleu+1 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3289 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3290 addsi3/1 ldb 0(%r19),%r19 ;# 3292 movqi+1/5 bb,< %r19,31,L$1169 ;# 3296 bleu+3 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 L$0344 ldw -228(%r30),%r1 ;# 8922 reload_outsi+2/5 comib,=,n 0,%r1,L$0345 ;# 3301 bleu+1 comb,= %r25,%r22,L$1169 ;# 3305 bleu+1 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 comib,= 9,%r22,L$1170 ;# 3307 bleu+1 extru %r19,28,29,%r21 ;# 3332 lshrsi3/2 L$0345 ldw -220(%r30),%r1 ;# 8925 reload_outsi+2/5 comib,= 0,%r1,L$0341 ;# 3312 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3316 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3317 addsi3/1 ldb 0(%r19),%r19 ;# 3319 movqi+1/5 and %r19,%r25,%r19 ;# 3322 andsi3/1 comib,= 0,%r19,L$0341 ;# 3325 bleu+1 extru %r22,31,8,%r19 ;# 3330 zero_extendqisi2/1 L$1169 extru %r19,28,29,%r21 ;# 3332 lshrsi3/2 L$1170 addl %r6,%r21,%r21 ;# 3335 addsi3/1 extru %r19,31,3,%r19 ;# 3339 andsi3/1 subi 31,%r19,%r19 ;# 3340 subsi3/2 ldb 0(%r21),%r20 ;# 3343 movqi+1/5 mtsar %r19 ;# 8928 reload_outsi+2/7 vdepi -1,1,%r20 ;# 3348 vdepi_ior stb %r20,0(%r21) ;# 3350 movqi+1/6 L$0341 ldw -212(%r30),%r1 ;# 8931 reload_outsi+2/5 comib,= 0,%r1,L$0348 ;# 3354 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3358 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3359 addsi3/1 ldb 0(%r19),%r19 ;# 3361 movqi+1/5 and %r19,%r18,%r19 ;# 3364 andsi3/1 comib,<> 0,%r19,L$1171 ;# 3367 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$0348 ldw -204(%r30),%r1 ;# 8934 reload_outsi+2/5 comib,= 0,%r1,L$0349 ;# 3372 bleu+1 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3376 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3377 addsi3/1 ldb 0(%r19),%r19 ;# 3379 movqi+1/5 and %r19,%r24,%r19 ;# 3382 andsi3/1 comib,<> 0,%r19,L$1171 ;# 3385 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$0349 ldw -196(%r30),%r1 ;# 8937 reload_outsi+2/5 comib,= 0,%r1,L$0350 ;# 3390 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3394 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3395 addsi3/1 ldb 0(%r19),%r19 ;# 3397 movqi+1/5 and %r19,%r24,%r19 ;# 3400 andsi3/1 comib,<> 0,%r19,L$1171 ;# 3403 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$0350 ldw -188(%r30),%r1 ;# 8940 reload_outsi+2/5 comib,= 0,%r1,L$0346 ;# 3408 bleu+1 ldw RR'__ctype2-$global$(%r23),%r19 ;# 3412 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3413 addsi3/1 ldb 0(%r19),%r19 ;# 3415 movqi+1/5 and %r19,%r18,%r19 ;# 3418 andsi3/1 comib,= 0,%r19,L$0346 ;# 3421 bleu+1 extru %r22,31,8,%r19 ;# 3426 zero_extendqisi2/1 L$1171 extru %r19,28,29,%r21 ;# 3428 lshrsi3/2 addl %r6,%r21,%r21 ;# 3431 addsi3/1 extru %r19,31,3,%r19 ;# 3435 andsi3/1 subi 31,%r19,%r19 ;# 3436 subsi3/2 ldb 0(%r21),%r20 ;# 3439 movqi+1/5 mtsar %r19 ;# 8943 reload_outsi+2/7 vdepi -1,1,%r20 ;# 3444 vdepi_ior stb %r20,0(%r21) ;# 3446 movqi+1/6 L$0346 ldw -180(%r30),%r1 ;# 8946 reload_outsi+2/5 comib,= 0,%r1,L$0353 ;# 3450 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3454 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3455 addsi3/1 ldb 0(%r19),%r19 ;# 3457 movqi+1/5 and %r19,%r31,%r19 ;# 3460 andsi3/1 comib,<> 0,%r19,L$1172 ;# 3463 bleu+1 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$0353 ldw -172(%r30),%r1 ;# 8949 reload_outsi+2/5 comib,= 0,%r1,L$0354 ;# 3468 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3472 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3473 addsi3/1 ldb 0(%r19),%r19 ;# 3475 movqi+1/5 and %r19,%r29,%r19 ;# 3478 andsi3/1 comib,<> 0,%r19,L$1172 ;# 3481 bleu+1 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$0354 comib,= 0,%r13,L$0355 ;# 3486 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3490 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3491 addsi3/1 ldb 0(%r19),%r19 ;# 3493 movqi+1/5 bb,< %r19,31,L$1172 ;# 3497 bleu+3 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$0355 comib,= 0,%r7,L$0339 ;# 3502 bleu+1 ldw RR'__ctype-$global$(%r4),%r19 ;# 3506 reload_outsi+2/5 addl %r19,%r22,%r19 ;# 3507 addsi3/1 ldb 0(%r19),%r19 ;# 3509 movqi+1/5 and %r19,%r28,%r19 ;# 3512 andsi3/1 comib,= 0,%r19,L$0339 ;# 3515 bleu+1 extru %r22,31,8,%r19 ;# 3520 zero_extendqisi2/1 L$1172 extru %r19,28,29,%r21 ;# 3522 lshrsi3/2 addl %r6,%r21,%r21 ;# 3525 addsi3/1 extru %r19,31,3,%r19 ;# 3529 andsi3/1 subi 31,%r19,%r19 ;# 3530 subsi3/2 ldb 0(%r21),%r20 ;# 3533 movqi+1/5 mtsar %r19 ;# 8952 reload_outsi+2/7 vdepi -1,1,%r20 ;# 3538 vdepi_ior stb %r20,0(%r21) ;# 3540 movqi+1/6 L$0339 ldo 1(%r22),%r22 ;# 3546 addsi3/2 comb,>=,n %r26,%r22,L$1173 ;# 3233 bleu+1 ldw -244(%r30),%r1 ;# 8916 reload_outsi+2/5 bl L$0275,%r0 ;# 3559 jump ldi 1,%r13 ;# 3556 reload_outsi+2/2 L$0328 ldi 255,%r19 ;# 8069 reload_outsi+2/2 L$1168 comb,= %r19,%r3,L$0359 ;# 8070 bleu+1 copy %r19,%r21 ;# 8595 reload_outsi+2/1 L$0360 ldo -1(%r3),%r20 ;# 3571 addsi3/2 ldw -296(%r30),%r19 ;# 3583 reload_outsi+2/5 extru %r20,31,8,%r3 ;# 3572 zero_extendqisi2/1 ldo -1(%r19),%r19 ;# 3584 addsi3/2 comb,<> %r21,%r3,L$0360 ;# 3577 bleu+1 stw %r19,-296(%r30) ;# 3588 reload_outsi+2/6 L$0359 ldb 11(%r6),%r19 ;# 3599 movqi+1/5 depi -1,28,1,%r19 ;# 3601 iorsi3+1/2 stb %r19,11(%r6) ;# 3603 movqi+1/6 ldb 7(%r6),%r19 ;# 3606 movqi+1/5 ldi 0,%r13 ;# 3613 reload_outsi+2/2 depi -1,29,1,%r19 ;# 3608 iorsi3+1/2 bl L$0275,%r0 ;# 3618 jump stb %r19,7(%r6) ;# 3610 movqi+1/6 L$0309 ldi 0,%r13 ;# 3624 reload_outsi+2/2 L$1166 extru %r7,21+8-1,8,%r19 ;# 3627 extzv addl %r6,%r19,%r19 ;# 3630 addsi3/1 extru %r7,31,3,%r20 ;# 3633 andsi3/1 L$0948 subi 31,%r20,%r20 ;# 3634 subsi3/2 ldb 0(%r19),%r21 ;# 3637 movqi+1/5 mtsar %r20 ;# 8955 reload_outsi+2/7 vdepi -1,1,%r21 ;# 3642 vdepi_ior bl L$0275,%r0 ;# 3653 jump stb %r21,0(%r19) ;# 3644 movqi+1/6 L$0276 ldb -1(%r6),%r20 ;# 8074 movqi+1/5 extru %r20,31,8,%r19 ;# 8075 zero_extendqisi2/1 comib,= 0,%r19,L$0364 ;# 8076 bleu+1 addl %r19,%r6,%r19 ;# 8079 addsi3/1 ldb -1(%r19),%r19 ;# 8082 zero_extendqisi2/2 comib,<> 0,%r19,L$0364 ;# 8083 bleu+1 ldo -1(%r20),%r19 ;# 8242 addsi3/2 bl L$1183,%r0 ;# 8253 jump stb %r19,-1(%r6) ;# 3688 movqi+1/6 L$0365 ldo -1(%r19),%r19 ;# 3686 addsi3/2 stb %r19,-1(%r6) ;# 3688 movqi+1/6 L$1183 extru %r19,31,8,%r19 ;# 3662 zero_extendqisi2/1 comib,= 0,%r19,L$0364 ;# 3664 bleu+1 addl %r19,%r6,%r19 ;# 3668 addsi3/1 ldb -1(%r19),%r19 ;# 3672 zero_extendqisi2/2 comib,=,n 0,%r19,L$0365 ;# 3674 bleu+1 ldb -1(%r6),%r19 ;# 3683 movqi+1/5 L$0364 ldb -1(%r6),%r19 ;# 3700 zero_extendqisi2/2 bl L$0043,%r0 ;# 3705 jump addl %r6,%r19,%r6 ;# 3701 addsi3/1 L$0368 bb,>=,n %r15,18,L$0076 ;# 3713 movsi-4 bl L$1181,%r0 ;# 3721 jump ldw 24(%r5),%r19 ;# 3861 reload_outsi+2/5 L$0372 bb,>=,n %r15,18,L$0076 ;# 3730 movsi-4 bl,n L$0374,%r0 ;# 3738 jump L$0376 bb,>=,n %r15,20,L$0076 ;# 3747 movsi-4 bl,n L$0378,%r0 ;# 3755 jump L$0380 bb,>=,n %r15,16,L$0076 ;# 3764 movsi-4 bl,n L$0378,%r0 ;# 3772 jump L$0383 and %r15,%r20,%r19 ;# 3779 andsi3/1 comb,= %r20,%r19,L$1174 ;# 3783 bleu+1 ldi -1,%r4 ;# 5074 reload_outsi+2/2 bl,n L$0076,%r0 ;# 3791 jump L$0387 comb,=,n %r16,%r19,L$0903 ;# 3799 bleu+1 ldb 0(%r19),%r7 ;# 3831 zero_extendqisi2/2 ldo 1(%r19),%r19 ;# 3826 addsi3/2 stw %r19,-296(%r30) ;# 3828 reload_outsi+2/6 ldo -39(%r7),%r19 ;# 7446 addsi3/2 addi,uv -86,%r19,%r0 ;# 7447 casesi0 blr,n %r19,%r0 b,n L$0397 L$0817 bl L$0759,%r0 ;# 9437 switch_jump ldw 0(%r5),%r4 ;# 8204 reload_outsi+2/5 L$1069 bl L$0395,%r0 nop ;# 9440 switch_jump L$1070 bl L$0422,%r0 nop ;# 9443 switch_jump L$1071 bl L$0397,%r0 nop ;# 9446 switch_jump L$1072 bl L$0811,%r0 nop ;# 9449 switch_jump L$1073 bl L$0397,%r0 nop ;# 9452 switch_jump L$1074 bl L$0397,%r0 nop ;# 9455 switch_jump L$1075 bl L$0397,%r0 nop ;# 9458 switch_jump L$1076 bl L$0397,%r0 nop ;# 9461 switch_jump L$1077 bl L$0397,%r0 nop ;# 9464 switch_jump L$1078 bl L$0787,%r0 nop ;# 9467 switch_jump L$1079 bl L$0787,%r0 nop ;# 9470 switch_jump L$1080 bl L$0787,%r0 nop ;# 9473 switch_jump L$1081 bl L$0787,%r0 nop ;# 9476 switch_jump L$1082 bl L$0787,%r0 nop ;# 9479 switch_jump L$1083 bl L$0787,%r0 nop ;# 9482 switch_jump L$1084 bl L$0787,%r0 nop ;# 9485 switch_jump L$1085 bl L$0787,%r0 nop ;# 9488 switch_jump L$1086 bl L$0787,%r0 nop ;# 9491 switch_jump L$1087 bl L$0397,%r0 nop ;# 9494 switch_jump L$1088 bl L$0397,%r0 nop ;# 9497 switch_jump L$1089 bl L$0659,%r0 ;# 9500 switch_jump ldw 0(%r5),%r4 ;# 8164 reload_outsi+2/5 L$1090 bl L$0397,%r0 nop ;# 9503 switch_jump L$1091 bl L$0679,%r0 ;# 9506 switch_jump ldw 0(%r5),%r4 ;# 8172 reload_outsi+2/5 L$1092 bl L$0811,%r0 nop ;# 9509 switch_jump L$1093 bl L$0397,%r0 nop ;# 9512 switch_jump L$1094 bl L$0397,%r0 nop ;# 9515 switch_jump L$1095 bl L$0719,%r0 ;# 9518 switch_jump ldw 0(%r5),%r4 ;# 8188 reload_outsi+2/5 L$1096 bl L$0397,%r0 nop ;# 9521 switch_jump L$1097 bl L$0397,%r0 nop ;# 9524 switch_jump L$1098 bl L$0397,%r0 nop ;# 9527 switch_jump L$1099 bl L$0397,%r0 nop ;# 9530 switch_jump L$1100 bl L$0397,%r0 nop ;# 9533 switch_jump L$1101 bl L$0397,%r0 nop ;# 9536 switch_jump L$1102 bl L$0397,%r0 nop ;# 9539 switch_jump L$1103 bl L$0397,%r0 nop ;# 9542 switch_jump L$1104 bl L$0397,%r0 nop ;# 9545 switch_jump L$1105 bl L$0397,%r0 nop ;# 9548 switch_jump L$1106 bl L$0397,%r0 nop ;# 9551 switch_jump L$1107 bl L$0397,%r0 nop ;# 9554 switch_jump L$1108 bl L$0397,%r0 nop ;# 9557 switch_jump L$1109 bl L$0397,%r0 nop ;# 9560 switch_jump L$1110 bl L$0397,%r0 nop ;# 9563 switch_jump L$1111 bl L$0397,%r0 nop ;# 9566 switch_jump L$1112 bl L$0397,%r0 nop ;# 9569 switch_jump L$1113 bl L$0397,%r0 nop ;# 9572 switch_jump L$1114 bl L$0397,%r0 nop ;# 9575 switch_jump L$1115 bl L$0397,%r0 nop ;# 9578 switch_jump L$1116 bl L$0639,%r0 ;# 9581 switch_jump ldw 0(%r5),%r4 ;# 8156 reload_outsi+2/5 L$1117 bl L$0397,%r0 nop ;# 9584 switch_jump L$1118 bl L$0397,%r0 nop ;# 9587 switch_jump L$1119 bl L$0397,%r0 nop ;# 9590 switch_jump L$1120 bl L$0397,%r0 nop ;# 9593 switch_jump L$1121 bl L$0397,%r0 nop ;# 9596 switch_jump L$1122 bl L$0397,%r0 nop ;# 9599 switch_jump L$1123 bl L$0397,%r0 nop ;# 9602 switch_jump L$1124 bl L$0397,%r0 nop ;# 9605 switch_jump L$1125 bl L$0739,%r0 ;# 9608 switch_jump ldw 0(%r5),%r4 ;# 8196 reload_outsi+2/5 L$1126 bl L$0397,%r0 nop ;# 9611 switch_jump L$1127 bl L$0699,%r0 ;# 9614 switch_jump ldw 0(%r5),%r4 ;# 8180 reload_outsi+2/5 L$1128 bl L$0397,%r0 nop ;# 9617 switch_jump L$1129 bl L$0397,%r0 nop ;# 9620 switch_jump L$1130 bl L$0397,%r0 nop ;# 9623 switch_jump L$1131 bl L$0397,%r0 nop ;# 9626 switch_jump L$1132 bl L$0397,%r0 nop ;# 9629 switch_jump L$1133 bl L$0397,%r0 nop ;# 9632 switch_jump L$1134 bl L$0397,%r0 nop ;# 9635 switch_jump L$1135 bl L$0397,%r0 nop ;# 9638 switch_jump L$1136 bl L$0397,%r0 nop ;# 9641 switch_jump L$1137 bl L$0397,%r0 nop ;# 9644 switch_jump L$1138 bl L$0397,%r0 nop ;# 9647 switch_jump L$1139 bl L$0397,%r0 nop ;# 9650 switch_jump L$1140 bl L$0397,%r0 nop ;# 9653 switch_jump L$1141 bl L$0397,%r0 nop ;# 9656 switch_jump L$1142 bl L$0397,%r0 nop ;# 9659 switch_jump L$1143 bl L$0397,%r0 nop ;# 9662 switch_jump L$1144 bl L$0397,%r0 nop ;# 9665 switch_jump L$1145 bl L$0397,%r0 nop ;# 9668 switch_jump L$1146 bl L$0397,%r0 nop ;# 9671 switch_jump L$1147 bl L$0397,%r0 nop ;# 9674 switch_jump L$1148 bl L$0619,%r0 ;# 9677 switch_jump ldw 0(%r5),%r4 ;# 8148 reload_outsi+2/5 L$1149 bl L$0397,%r0 nop ;# 9680 switch_jump L$1150 bl L$0397,%r0 nop ;# 9683 switch_jump L$1151 bl L$0397,%r0 nop ;# 9686 switch_jump L$1152 bl L$0506,%r0 nop ;# 9689 switch_jump L$1153 bl L$0472,%r0 ;# 9692 switch_jump ldil L'33792,%r19 ;# 4724 add_high_const+3 L$1154 bl,n L$0397,%r0 ;# 7450 jump L$0395 bb,<,n %r15,18,L$0397 ;# 3853 bleu+3 ldw 24(%r5),%r19 ;# 3861 reload_outsi+2/5 L$1181 ldo 1(%r19),%r19 ;# 3862 addsi3/2 stw %r19,24(%r5) ;# 3866 reload_outsi+2/6 ldw -304(%r30),%r20 ;# 3871 reload_outsi+2/5 ldw -260(%r30),%r1 ;# 8958 reload_outsi+2/5 ldw -308(%r30),%r19 ;# 3873 reload_outsi+2/5 ldo 1(%r1),%r1 ;# 3868 addsi3/2 comb,<> %r19,%r20,L$0398 ;# 3875 bleu+1 stw %r1,-260(%r30) ;# 8961 reload_outsi+2/6 zdep %r20,28,29,%r25 ;# 3885 ashlsi3+1 sh1addl %r20,%r25,%r25 ;# 3886 ashlsi3-2 ldw -312(%r30),%r26 ;# 3890 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 3894 call_value_internal_symref zdep %r25,29,30,%r25 ;# 3892 ashlsi3+1 comib,= 0,%r28,L$0953 ;# 3903 bleu+1 stw %r28,-312(%r30) ;# 3898 reload_outsi+2/6 ldw -308(%r30),%r19 ;# 3912 reload_outsi+2/5 zdep %r19,30,31,%r19 ;# 3914 ashlsi3+1 stw %r19,-308(%r30) ;# 3916 reload_outsi+2/6 L$0398 ldw -304(%r30),%r20 ;# 3921 reload_outsi+2/5 ldw -312(%r30),%r21 ;# 3923 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 3933 reload_outsi+2/5 sh2addl %r20,%r20,%r20 ;# 3928 ashlsi3-2 sh2addl %r20,%r21,%r21 ;# 3931 ashlsi3-2 sub %r12,%r19,%r19 ;# 3934 subsi3/1 stw %r19,0(%r21) ;# 3936 reload_outsi+2/6 ldw -304(%r30),%r19 ;# 3939 reload_outsi+2/5 ldw -312(%r30),%r20 ;# 3941 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 3946 ashlsi3-2 comib,= 0,%r10,L$0400 ;# 3951 bleu+1 sh2addl %r19,%r20,%r20 ;# 3949 ashlsi3-2 ldw 0(%r5),%r19 ;# 3953 reload_outsi+2/5 sub %r10,%r19,%r19 ;# 3954 subsi3/1 ldo 1(%r19),%r19 ;# 3955 addsi3/2 bl L$0401,%r0 ;# 3958 jump stw %r19,4(%r20) ;# 3957 reload_outsi+2/6 L$0400 stw %r0,4(%r20) ;# 3962 reload_outsi+2/6 L$0401 ldw -304(%r30),%r20 ;# 3966 reload_outsi+2/5 ldw -312(%r30),%r21 ;# 3968 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 3978 reload_outsi+2/5 sh2addl %r20,%r20,%r20 ;# 3973 ashlsi3-2 sh2addl %r20,%r21,%r21 ;# 3976 ashlsi3-2 sub %r6,%r19,%r19 ;# 3979 subsi3/1 stw %r19,12(%r21) ;# 3981 reload_outsi+2/6 ldw -304(%r30),%r19 ;# 3984 reload_outsi+2/5 ldw -312(%r30),%r20 ;# 3986 reload_outsi+2/5 ldw -260(%r30),%r1 ;# 8964 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 3991 ashlsi3-2 sh2addl %r19,%r20,%r20 ;# 3994 ashlsi3-2 ldi 255,%r19 ;# 3999 reload_outsi+2/2 comb,<< %r19,%r1,L$0402 ;# 4001 bleu+1 stw %r1,16(%r20) ;# 3996 reload_outsi+2/6 ldw -304(%r30),%r20 ;# 4005 reload_outsi+2/5 ldw -312(%r30),%r21 ;# 4007 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 4017 reload_outsi+2/5 sh2addl %r20,%r20,%r20 ;# 4012 ashlsi3-2 sh2addl %r20,%r21,%r21 ;# 4015 ashlsi3-2 sub %r6,%r19,%r19 ;# 4018 subsi3/1 ldo 2(%r19),%r19 ;# 4019 addsi3/2 stw %r19,8(%r21) ;# 4021 reload_outsi+2/6 ldw 0(%r5),%r4 ;# 8087 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8090 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8088 subsi3/1 ldo 3(%r19),%r19 ;# 8089 addsi3/2 comb,>>=,n %r20,%r19,L$0407 ;# 8091 bleu+1 ldil L'65536,%r3 ;# 8593 reload_outsi+2/3 L$0408 comb,= %r3,%r20,L$0944 ;# 4049 bleu+1 zdep %r20,30,31,%r19 ;# 4059 ashlsi3+1 comb,>>= %r3,%r19,L$0413 ;# 4067 bleu+1 stw %r19,4(%r5) ;# 4061 reload_outsi+2/6 stw %r3,4(%r5) ;# 4070 reload_outsi+2/6 L$0413 ldw 0(%r5),%r26 ;# 4077 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4081 call_value_internal_symref ldw 4(%r5),%r25 ;# 4079 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4089 bleu+1 stw %r28,0(%r5) ;# 4085 reload_outsi+2/6 comb,= %r28,%r4,L$0406 ;# 4099 bleu+1 sub %r6,%r4,%r19 ;# 4101 subsi3/1 comib,= 0,%r10,L$0416 ;# 4110 bleu+1 addl %r28,%r19,%r6 ;# 4104 addsi3/1 sub %r10,%r4,%r19 ;# 4111 subsi3/1 addl %r28,%r19,%r10 ;# 4114 addsi3/1 L$0416 comib,= 0,%r8,L$0417 ;# 4117 bleu+1 sub %r8,%r4,%r19 ;# 4118 subsi3/1 addl %r28,%r19,%r8 ;# 4121 addsi3/1 L$0417 comib,= 0,%r9,L$0406 ;# 4124 bleu+1 sub %r9,%r4,%r19 ;# 4125 subsi3/1 addl %r28,%r19,%r9 ;# 4128 addsi3/1 L$0406 ldw 0(%r5),%r4 ;# 4029 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4033 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 4030 subsi3/1 ldo 3(%r19),%r19 ;# 4031 addsi3/2 comb,<< %r20,%r19,L$0408 nop ;# 4035 bleu+1 L$0407 ldi 5,%r19 ;# 4150 movqi+1/2 stbs,ma %r19,1(%r6) ;# 4151 movqi+1/6 ldb -257(%r30),%r1 ;# 4156 movqi+1/5 stbs,ma %r1,1(%r6) ;# 8968 movqi+1/6 stbs,ma %r0,1(%r6) ;# 4159 movqi+1/6 L$0402 ldi 0,%r10 ;# 4182 reload_outsi+2/2 ldi 0,%r8 ;# 4185 reload_outsi+2/2 copy %r6,%r12 ;# 4188 reload_outsi+2/1 ldw -304(%r30),%r19 ;# 4174 reload_outsi+2/5 ldi 0,%r9 ;# 4191 reload_outsi+2/2 ldo 1(%r19),%r19 ;# 4175 addsi3/2 bl L$0043,%r0 ;# 4193 jump stw %r19,-304(%r30) ;# 4179 reload_outsi+2/6 L$0422 bb,< %r15,18,L$0397 ;# 4201 bleu+3 ldw -304(%r30),%r19 ;# 4207 reload_outsi+2/5 comib,<>,n 0,%r19,L$0374 ;# 4209 bleu+1 bb,>=,n %r15,14,L$0950 ;# 4215 movsi-4 bl,n L$0397,%r0 ;# 4230 jump L$0374 comib,=,n 0,%r10,L$0427 ;# 4237 bleu+1 ldw 0(%r5),%r4 ;# 8095 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8098 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8096 subsi3/1 ldo 1(%r19),%r19 ;# 8097 addsi3/2 comb,>>=,n %r20,%r19,L$0432 ;# 8099 bleu+1 ldil L'65536,%r3 ;# 8591 reload_outsi+2/3 L$0433 comb,= %r3,%r20,L$0944 ;# 4266 bleu+1 zdep %r20,30,31,%r19 ;# 4276 ashlsi3+1 comb,>>= %r3,%r19,L$0438 ;# 4284 bleu+1 stw %r19,4(%r5) ;# 4278 reload_outsi+2/6 stw %r3,4(%r5) ;# 4287 reload_outsi+2/6 L$0438 ldw 0(%r5),%r26 ;# 4294 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4298 call_value_internal_symref ldw 4(%r5),%r25 ;# 4296 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4306 bleu+1 stw %r28,0(%r5) ;# 4302 reload_outsi+2/6 comb,= %r28,%r4,L$0431 ;# 4316 bleu+1 sub %r6,%r4,%r19 ;# 4318 subsi3/1 addl %r28,%r19,%r6 ;# 4321 addsi3/1 sub %r12,%r4,%r19 ;# 4322 subsi3/1 comib,= 0,%r10,L$0441 ;# 4327 bleu+1 addl %r28,%r19,%r12 ;# 4325 addsi3/1 sub %r10,%r4,%r19 ;# 4328 subsi3/1 addl %r28,%r19,%r10 ;# 4331 addsi3/1 L$0441 comib,= 0,%r8,L$0442 ;# 4334 bleu+1 sub %r8,%r4,%r19 ;# 4335 subsi3/1 addl %r28,%r19,%r8 ;# 4338 addsi3/1 L$0442 comib,= 0,%r9,L$0431 ;# 4341 bleu+1 sub %r9,%r4,%r19 ;# 4342 subsi3/1 addl %r28,%r19,%r9 ;# 4345 addsi3/1 L$0431 ldw 0(%r5),%r4 ;# 4246 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4250 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 4247 subsi3/1 ldo 1(%r19),%r19 ;# 4248 addsi3/2 comb,<< %r20,%r19,L$0433 nop ;# 4252 bleu+1 L$0432 ldi 19,%r19 ;# 4367 movqi+1/2 stbs,ma %r19,1(%r6) ;# 4368 movqi+1/6 uaddcm %r6,%r10,%r24 ;# 4381 adddi3+1 ldi 13,%r26 ;# 4384 reload_outsi+2/2 copy %r10,%r25 ;# 4386 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 4390 call_internal_symref ldo -3(%r24),%r24 ;# 4388 addsi3/2 L$0427 ldw -304(%r30),%r19 ;# 4395 reload_outsi+2/5 comib,<>,n 0,%r19,L$0447 ;# 4397 bleu+1 bb,<,n %r15,14,L$0076 ;# 4403 bleu+3 L$0950 .CALL ARGW0=GR bl free,%r2 ;# 4414 call_internal_symref ldw -312(%r30),%r26 ;# 4412 reload_outsi+2/5 bl L$0867,%r0 ;# 4418 jump ldi 16,%r28 ;# 4416 reload_outsi+2/2 L$0447 ldo -1(%r19),%r19 ;# 4427 addsi3/2 stw %r19,-304(%r30) ;# 4431 reload_outsi+2/6 ldw -312(%r30),%r20 ;# 4436 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 4441 ashlsi3-2 sh2addl %r19,%r20,%r20 ;# 4444 ashlsi3-2 ldw 0(%r5),%r21 ;# 4446 reload_outsi+2/5 ldw 0(%r20),%r19 ;# 4448 reload_outsi+2/5 ldw 4(%r20),%r20 ;# 4464 reload_outsi+2/5 comib,= 0,%r20,L$0450 ;# 4466 bleu+1 addl %r21,%r19,%r12 ;# 4449 addsi3/1 addl %r21,%r20,%r19 ;# 4483 addsi3/1 bl L$0451,%r0 ;# 4485 jump ldo -1(%r19),%r10 ;# 4484 addsi3/2 L$0450 ldi 0,%r10 ;# 4489 reload_outsi+2/2 L$0451 ldw -304(%r30),%r19 ;# 4493 reload_outsi+2/5 ldw -312(%r30),%r20 ;# 4495 reload_outsi+2/5 ldw 0(%r5),%r21 ;# 4505 reload_outsi+2/5 sh2addl %r19,%r19,%r19 ;# 4500 ashlsi3-2 sh2addl %r19,%r20,%r20 ;# 4503 ashlsi3-2 ldw 12(%r20),%r19 ;# 4507 reload_outsi+2/5 ldw 16(%r20),%r7 ;# 4523 reload_outsi+2/5 addl %r21,%r19,%r8 ;# 4508 addsi3/1 ldi 255,%r19 ;# 4529 reload_outsi+2/2 comb,<< %r19,%r7,L$0043 ;# 4531 bleu+1 ldi 0,%r9 ;# 4526 reload_outsi+2/2 ldw 8(%r20),%r19 ;# 4550 reload_outsi+2/5 ldw -260(%r30),%r1 ;# 8971 reload_outsi+2/5 addl %r21,%r19,%r19 ;# 4551 addsi3/1 sub %r1,%r7,%r20 ;# 4557 subsi3/1 stb %r20,0(%r19) ;# 4559 movqi+1/6 ldw 0(%r5),%r4 ;# 8103 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8106 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8104 subsi3/1 ldo 3(%r19),%r19 ;# 8105 addsi3/2 comb,>>=,n %r20,%r19,L$0457 ;# 8107 bleu+1 ldil L'65536,%r3 ;# 8589 reload_outsi+2/3 L$0458 comb,= %r3,%r20,L$0944 ;# 4587 bleu+1 zdep %r20,30,31,%r19 ;# 4597 ashlsi3+1 comb,>>= %r3,%r19,L$0463 ;# 4605 bleu+1 stw %r19,4(%r5) ;# 4599 reload_outsi+2/6 stw %r3,4(%r5) ;# 4608 reload_outsi+2/6 L$0463 ldw 0(%r5),%r26 ;# 4615 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4619 call_value_internal_symref ldw 4(%r5),%r25 ;# 4617 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4627 bleu+1 stw %r28,0(%r5) ;# 4623 reload_outsi+2/6 comb,= %r28,%r4,L$0456 ;# 4637 bleu+1 sub %r6,%r4,%r19 ;# 4639 subsi3/1 addl %r28,%r19,%r6 ;# 4642 addsi3/1 sub %r12,%r4,%r19 ;# 4643 subsi3/1 comib,= 0,%r10,L$0466 ;# 4648 bleu+1 addl %r28,%r19,%r12 ;# 4646 addsi3/1 sub %r10,%r4,%r19 ;# 4649 subsi3/1 addl %r28,%r19,%r10 ;# 4652 addsi3/1 L$0466 comib,= 0,%r8,L$0467 ;# 4655 bleu+1 sub %r8,%r4,%r19 ;# 4656 subsi3/1 addl %r28,%r19,%r8 ;# 4659 addsi3/1 L$0467 comib,= 0,%r9,L$0456 ;# 4662 bleu+1 sub %r9,%r4,%r19 ;# 4663 subsi3/1 addl %r28,%r19,%r9 ;# 4666 addsi3/1 L$0456 ldw 0(%r5),%r4 ;# 4567 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4571 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 4568 subsi3/1 ldo 3(%r19),%r19 ;# 4569 addsi3/2 comb,<< %r20,%r19,L$0458 nop ;# 4573 bleu+1 L$0457 ldi 6,%r19 ;# 4688 movqi+1/2 stbs,ma %r19,1(%r6) ;# 4689 movqi+1/6 stbs,ma %r7,1(%r6) ;# 4694 movqi+1/6 ldw -260(%r30),%r1 ;# 8974 reload_outsi+2/5 sub %r1,%r7,%r19 ;# 4700 subsi3/1 bl L$0043,%r0 ;# 4720 jump stbs,ma %r19,1(%r6) ;# 4702 movqi+1/6 L$0472 ldo R'33792(%r19),%r19 ;# 4725 movhi-2 and %r15,%r19,%r19 ;# 4726 andsi3/1 comib,<>,n 0,%r19,L$0397 ;# 4728 bleu+1 L$0378 bb,<,n %r15,21,L$0076 ;# 4739 bleu+3 ldw 0(%r5),%r3 ;# 8111 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8114 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8112 subsi3/1 ldo 3(%r19),%r19 ;# 8113 addsi3/2 comb,>>=,n %r20,%r19,L$0476 ;# 8115 bleu+1 ldil L'65536,%r4 ;# 8587 reload_outsi+2/3 L$0477 comb,= %r4,%r20,L$0944 ;# 4768 bleu+1 zdep %r20,30,31,%r19 ;# 4778 ashlsi3+1 comb,>>= %r4,%r19,L$0482 ;# 4786 bleu+1 stw %r19,4(%r5) ;# 4780 reload_outsi+2/6 stw %r4,4(%r5) ;# 4789 reload_outsi+2/6 L$0482 ldw 0(%r5),%r26 ;# 4796 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4800 call_value_internal_symref ldw 4(%r5),%r25 ;# 4798 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4808 bleu+1 stw %r28,0(%r5) ;# 4804 reload_outsi+2/6 comb,= %r28,%r3,L$0475 ;# 4818 bleu+1 sub %r6,%r3,%r19 ;# 4820 subsi3/1 addl %r28,%r19,%r6 ;# 4823 addsi3/1 sub %r12,%r3,%r19 ;# 4824 subsi3/1 comib,= 0,%r10,L$0485 ;# 4829 bleu+1 addl %r28,%r19,%r12 ;# 4827 addsi3/1 sub %r10,%r3,%r19 ;# 4830 subsi3/1 addl %r28,%r19,%r10 ;# 4833 addsi3/1 L$0485 comib,= 0,%r8,L$0486 ;# 4836 bleu+1 sub %r8,%r3,%r19 ;# 4837 subsi3/1 addl %r28,%r19,%r8 ;# 4840 addsi3/1 L$0486 comib,= 0,%r9,L$0475 ;# 4843 bleu+1 sub %r9,%r3,%r19 ;# 4844 subsi3/1 addl %r28,%r19,%r9 ;# 4847 addsi3/1 L$0475 ldw 0(%r5),%r3 ;# 4748 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4752 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 4749 subsi3/1 ldo 3(%r19),%r19 ;# 4750 addsi3/2 comb,<< %r20,%r19,L$0477 nop ;# 4754 bleu+1 L$0476 ldi 14,%r26 ;# 4873 reload_outsi+2/2 copy %r12,%r25 ;# 4875 reload_outsi+2/1 sub %r6,%r25,%r24 ;# 4870 subsi3/1 ldo 3(%r24),%r24 ;# 4877 addsi3/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 4881 call_internal_symref copy %r6,%r23 ;# 4879 reload_outsi+2/1 ldi 0,%r9 ;# 4884 reload_outsi+2/2 comib,= 0,%r10,L$0490 ;# 4889 bleu+1 ldo 3(%r6),%r6 ;# 4886 addsi3/2 ldi 13,%r26 ;# 4894 reload_outsi+2/2 copy %r10,%r25 ;# 4896 reload_outsi+2/1 sub %r6,%r25,%r24 ;# 4891 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 4900 call_internal_symref ldo -3(%r24),%r24 ;# 4898 addsi3/2 L$0490 ldw 0(%r5),%r3 ;# 8119 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8122 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8120 subsi3/1 ldo 3(%r19),%r19 ;# 8121 addsi3/2 comb,>>= %r20,%r19,L$0492 ;# 8123 bleu+1 copy %r6,%r10 ;# 4904 reload_outsi+2/1 ldil L'65536,%r4 ;# 8585 reload_outsi+2/3 L$0493 comb,= %r4,%r20,L$0944 ;# 4929 bleu+1 zdep %r20,30,31,%r19 ;# 4939 ashlsi3+1 comb,>>= %r4,%r19,L$0498 ;# 4947 bleu+1 stw %r19,4(%r5) ;# 4941 reload_outsi+2/6 stw %r4,4(%r5) ;# 4950 reload_outsi+2/6 L$0498 ldw 0(%r5),%r26 ;# 4957 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 4961 call_value_internal_symref ldw 4(%r5),%r25 ;# 4959 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 4969 bleu+1 stw %r28,0(%r5) ;# 4965 reload_outsi+2/6 comb,= %r28,%r3,L$0491 ;# 4979 bleu+1 sub %r6,%r3,%r19 ;# 4981 subsi3/1 comib,= 0,%r10,L$0501 ;# 4990 bleu+1 addl %r28,%r19,%r6 ;# 4984 addsi3/1 sub %r10,%r3,%r19 ;# 4991 subsi3/1 addl %r28,%r19,%r10 ;# 4994 addsi3/1 L$0501 comib,= 0,%r8,L$0502 ;# 4997 bleu+1 sub %r8,%r3,%r19 ;# 4998 subsi3/1 addl %r28,%r19,%r8 ;# 5001 addsi3/1 L$0502 comib,= 0,%r9,L$0491 ;# 5004 bleu+1 sub %r9,%r3,%r19 ;# 5005 subsi3/1 addl %r28,%r19,%r9 ;# 5008 addsi3/1 L$0491 ldw 0(%r5),%r3 ;# 4909 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 4913 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 4910 subsi3/1 ldo 3(%r19),%r19 ;# 4911 addsi3/2 comb,<< %r20,%r19,L$0493 nop ;# 4915 bleu+1 L$0492 ldo 3(%r6),%r6 ;# 5030 addsi3/2 ldi 0,%r8 ;# 5033 reload_outsi+2/2 bl L$0043,%r0 ;# 5038 jump copy %r6,%r12 ;# 5036 reload_outsi+2/1 L$0506 bb,>= %r15,22,L$0397 ;# 5046 movsi-4 ldi 4608,%r20 ;# 5048 reload_outsi+2/2 and %r15,%r20,%r19 ;# 5049 andsi3/1 comb,= %r20,%r19,L$0397 ;# 5053 bleu+1 ldw -296(%r30),%r20 ;# 5055 reload_outsi+2/5 ldw -276(%r30),%r1 ;# 8977 reload_outsi+2/5 ldo -2(%r20),%r19 ;# 5056 addsi3/2 comb,<> %r1,%r19,L$1175 ;# 5058 bleu+1 ldi -1,%r4 ;# 5074 reload_outsi+2/2 comb,=,n %r16,%r20,L$0397 ;# 5062 bleu+1 L$1174 ldw -296(%r30),%r20 ;# 5079 reload_outsi+2/5 L$1175 copy %r4,%r11 ;# 5076 reload_outsi+2/1 comb,<> %r16,%r20,L$0517 ;# 5085 bleu+1 ldo -1(%r20),%r23 ;# 5080 addsi3/2 bb,>=,n %r15,19,L$0915 ;# 5092 movsi-4 bl L$1182,%r0 ;# 5107 jump stw %r23,-296(%r30) ;# 5968 reload_outsi+2/6 L$0517 ldo 1(%r20),%r19 ;# 5134 addsi3/2 stw %r19,-296(%r30) ;# 5136 reload_outsi+2/6 comib,= 0,%r14,L$0515 ;# 5143 bleu+1 ldb 0(%r20),%r7 ;# 5139 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5144 addsi3/1 ldb 0(%r19),%r7 ;# 5147 zero_extendqisi2/2 L$0515 addil LR'__ctype-$global$,%r27 ;# 8257 pic2_lo_sum+1 ldw RR'__ctype-$global$(%r1),%r21 ;# 8259 reload_outsi+2/5 addl %r21,%r7,%r19 ;# 8260 addsi3/1 ldb 0(%r19),%r19 ;# 8261 movqi+1/5 bb,>= %r19,29,L$0513 ;# 8265 movsi-4 ldi 4,%r20 ;# 8263 reload_outsi+2/2 copy %r20,%r22 ;# 8583 reload_outsi+2/1 L$0522 comiclr,< -1,%r11,%r0 ;# 8128 movsicc+1/1 ldi 0,%r11 sh2addl %r11,%r11,%r19 ;# 5188 ashlsi3-2 sh1addl %r19,%r7,%r19 ;# 5191 ashlsi3-2 ldw -296(%r30),%r20 ;# 5194 reload_outsi+2/5 comb,= %r16,%r20,L$0513 ;# 5196 bleu+1 ldo -48(%r19),%r11 ;# 5192 addsi3/2 ldo 1(%r20),%r19 ;# 5215 addsi3/2 stw %r19,-296(%r30) ;# 5217 reload_outsi+2/6 comib,= 0,%r14,L$0520 ;# 5224 bleu+1 ldb 0(%r20),%r7 ;# 5220 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5225 addsi3/1 ldb 0(%r19),%r7 ;# 5228 zero_extendqisi2/2 L$0520 addl %r21,%r7,%r19 ;# 5166 addsi3/1 ldb 0(%r19),%r19 ;# 5168 movqi+1/5 and %r19,%r22,%r19 ;# 5172 andsi3/1 comib,<> 0,%r19,L$0522 nop ;# 5174 bleu+1 L$0513 ldi 44,%r19 ;# 5252 reload_outsi+2/2 comb,<> %r19,%r7,L$0532 ;# 5254 bleu+1 ldw -296(%r30),%r20 ;# 5259 reload_outsi+2/5 comb,= %r16,%r20,L$0533 ;# 5261 bleu+1 ldo 1(%r20),%r19 ;# 5278 addsi3/2 stw %r19,-296(%r30) ;# 5280 reload_outsi+2/6 comib,= 0,%r14,L$0535 ;# 5287 bleu+1 ldb 0(%r20),%r7 ;# 5283 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5288 addsi3/1 ldb 0(%r19),%r7 ;# 5291 zero_extendqisi2/2 L$0535 addil LR'__ctype-$global$,%r27 ;# 8269 pic2_lo_sum+1 ldw RR'__ctype-$global$(%r1),%r21 ;# 8271 reload_outsi+2/5 addl %r21,%r7,%r19 ;# 8272 addsi3/1 ldb 0(%r19),%r19 ;# 8273 movqi+1/5 bb,>= %r19,29,L$0533 ;# 8277 movsi-4 ldi 4,%r20 ;# 8275 reload_outsi+2/2 copy %r20,%r22 ;# 8578 reload_outsi+2/1 L$0542 comiclr,< -1,%r4,%r0 ;# 8132 movsicc+1/1 ldi 0,%r4 sh2addl %r4,%r4,%r19 ;# 5332 ashlsi3-2 sh1addl %r19,%r7,%r19 ;# 5335 ashlsi3-2 ldw -296(%r30),%r20 ;# 5338 reload_outsi+2/5 comb,= %r16,%r20,L$0533 ;# 5340 bleu+1 ldo -48(%r19),%r4 ;# 5336 addsi3/2 ldo 1(%r20),%r19 ;# 5359 addsi3/2 stw %r19,-296(%r30) ;# 5361 reload_outsi+2/6 comib,= 0,%r14,L$0540 ;# 5368 bleu+1 ldb 0(%r20),%r7 ;# 5364 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5369 addsi3/1 ldb 0(%r19),%r7 ;# 5372 zero_extendqisi2/2 L$0540 addl %r21,%r7,%r19 ;# 5310 addsi3/1 ldb 0(%r19),%r19 ;# 5312 movqi+1/5 and %r19,%r22,%r19 ;# 5316 andsi3/1 comib,<> 0,%r19,L$0542 nop ;# 5318 bleu+1 L$0533 comiclr,< -1,%r4,%r0 ;# 8136 beq-1/4 zdepi -1,31,15,%r4 bl,n L$0553,%r0 ;# 5401 jump L$0532 copy %r11,%r4 ;# 5406 reload_outsi+2/1 L$0553 comib,> 0,%r11,L$0951 ;# 5410 bleu+1 zdepi -1,31,15,%r19 ;# 5412 reload_outsi+2/4 comb,<,n %r19,%r4,L$0951 ;# 5414 bleu+1 comb,<,n %r4,%r11,L$0951 ;# 5416 bleu+1 bb,< %r15,19,L$1176 ;# 5451 bleu+3 ldi 125,%r19 ;# 5514 reload_outsi+2/2 ldi 92,%r19 ;# 5455 reload_outsi+2/2 comb,<> %r19,%r7,L$0915 ;# 5457 bleu+1 ldw -296(%r30),%r20 ;# 5473 reload_outsi+2/5 comb,= %r16,%r20,L$0922 ;# 5475 bleu+1 ldo 1(%r20),%r19 ;# 5484 addsi3/2 stw %r19,-296(%r30) ;# 5486 reload_outsi+2/6 comib,= 0,%r14,L$0558 ;# 5493 bleu+1 ldb 0(%r20),%r7 ;# 5489 zero_extendqisi2/2 addl %r14,%r7,%r19 ;# 5494 addsi3/1 ldb 0(%r19),%r7 ;# 5497 zero_extendqisi2/2 L$0558 ldi 125,%r19 ;# 5514 reload_outsi+2/2 L$1176 comb,=,n %r19,%r7,L$0566 ;# 5516 bleu+1 L$0951 bb,<,n %r15,19,L$0511 ;# 5523 bleu+3 .CALL ARGW0=GR bl free,%r2 ;# 5534 call_internal_symref ldw -312(%r30),%r26 ;# 5532 reload_outsi+2/5 bl L$0867,%r0 ;# 5538 jump ldi 10,%r28 ;# 5536 reload_outsi+2/2 L$0566 comib,<>,n 0,%r8,L$0569 ;# 5545 bleu+1 bb,<,n %r15,26,L$0917 ;# 5552 bleu+3 bb,>=,n %r15,27,L$0511 ;# 5571 movsi-4 copy %r6,%r8 ;# 5574 reload_outsi+2/1 L$0569 comib,<> 0,%r4,L$0574 ;# 5587 bleu+1 ldi 10,%r13 ;# 8980 reload_outsi+2/2 ldw 0(%r5),%r3 ;# 8139 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8142 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8140 subsi3/1 ldo 3(%r19),%r19 ;# 8141 addsi3/2 comb,>>=,n %r20,%r19,L$0576 ;# 8143 bleu+1 ldil L'65536,%r4 ;# 8573 reload_outsi+2/3 L$0577 comb,= %r4,%r20,L$0944 ;# 5613 bleu+1 zdep %r20,30,31,%r19 ;# 5623 ashlsi3+1 comb,>>= %r4,%r19,L$0582 ;# 5631 bleu+1 stw %r19,4(%r5) ;# 5625 reload_outsi+2/6 stw %r4,4(%r5) ;# 5634 reload_outsi+2/6 L$0582 ldw 0(%r5),%r26 ;# 5641 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 5645 call_value_internal_symref ldw 4(%r5),%r25 ;# 5643 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 5653 bleu+1 stw %r28,0(%r5) ;# 5649 reload_outsi+2/6 comb,= %r28,%r3,L$0575 ;# 5663 bleu+1 sub %r6,%r3,%r19 ;# 5665 subsi3/1 addl %r28,%r19,%r6 ;# 5668 addsi3/1 sub %r12,%r3,%r19 ;# 5669 subsi3/1 comib,= 0,%r10,L$0585 ;# 5674 bleu+1 addl %r28,%r19,%r12 ;# 5672 addsi3/1 sub %r10,%r3,%r19 ;# 5675 subsi3/1 addl %r28,%r19,%r10 ;# 5678 addsi3/1 L$0585 comib,= 0,%r8,L$0586 ;# 5681 bleu+1 sub %r8,%r3,%r19 ;# 5682 subsi3/1 addl %r28,%r19,%r8 ;# 5685 addsi3/1 L$0586 comib,= 0,%r9,L$0575 ;# 5688 bleu+1 sub %r9,%r3,%r19 ;# 5689 subsi3/1 addl %r28,%r19,%r9 ;# 5692 addsi3/1 L$0575 ldw 0(%r5),%r3 ;# 5593 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 5597 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 5594 subsi3/1 ldo 3(%r19),%r19 ;# 5595 addsi3/2 comb,<< %r20,%r19,L$0577 nop ;# 5599 bleu+1 L$0576 ldi 12,%r26 ;# 5718 reload_outsi+2/2 copy %r8,%r25 ;# 5720 reload_outsi+2/1 sub %r6,%r8,%r24 ;# 5722 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op1,%r2 ;# 5726 call_internal_symref copy %r6,%r23 ;# 5724 reload_outsi+2/1 bl L$0590,%r0 ;# 5730 jump ldo 3(%r6),%r6 ;# 5728 addsi3/2 L$0574 comiclr,> 2,%r4,%r0 ;# 8282 beq-1/2 ldi 20,%r13 ldw 0(%r5),%r3 ;# 8285 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8288 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 8286 subsi3/1 addl %r19,%r13,%r19 ;# 8287 addsi3/1 comb,>>=,n %r20,%r19,L$0868 ;# 8289 bleu+1 ldil L'65536,%r7 ;# 8571 reload_outsi+2/3 L$0595 comb,= %r7,%r20,L$0944 ;# 5769 bleu+1 zdep %r20,30,31,%r19 ;# 5779 ashlsi3+1 comb,>>= %r7,%r19,L$0600 ;# 5787 bleu+1 stw %r19,4(%r5) ;# 5781 reload_outsi+2/6 stw %r7,4(%r5) ;# 5790 reload_outsi+2/6 L$0600 ldw 0(%r5),%r26 ;# 5797 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 5801 call_value_internal_symref ldw 4(%r5),%r25 ;# 5799 reload_outsi+2/5 comib,= 0,%r28,L$0953 ;# 5809 bleu+1 stw %r28,0(%r5) ;# 5805 reload_outsi+2/6 comb,= %r28,%r3,L$0593 ;# 5819 bleu+1 sub %r6,%r3,%r19 ;# 5821 subsi3/1 addl %r28,%r19,%r6 ;# 5824 addsi3/1 sub %r12,%r3,%r19 ;# 5825 subsi3/1 comib,= 0,%r10,L$0603 ;# 5830 bleu+1 addl %r28,%r19,%r12 ;# 5828 addsi3/1 sub %r10,%r3,%r19 ;# 5831 subsi3/1 addl %r28,%r19,%r10 ;# 5834 addsi3/1 L$0603 comib,= 0,%r8,L$0604 ;# 5837 bleu+1 sub %r8,%r3,%r19 ;# 5838 subsi3/1 addl %r28,%r19,%r8 ;# 5841 addsi3/1 L$0604 comib,= 0,%r9,L$0593 ;# 5844 bleu+1 sub %r9,%r3,%r19 ;# 5845 subsi3/1 addl %r28,%r19,%r9 ;# 5848 addsi3/1 L$0593 ldw 0(%r5),%r3 ;# 5749 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 5753 reload_outsi+2/5 sub %r6,%r3,%r19 ;# 5750 subsi3/1 addl %r19,%r13,%r19 ;# 5751 addsi3/1 comb,<< %r20,%r19,L$0595 nop ;# 5755 bleu+1 L$0868 comib,>= 1,%r4,L$0608 ;# 5872 bleu+1 ldo 5(%r6),%r19 ;# 5870 addsi3/2 sub %r19,%r8,%r19 ;# 5874 subsi3/1 bl L$0609,%r0 ;# 5876 jump ldo 2(%r19),%r24 ;# 5875 addsi3/2 L$0608 sub %r19,%r8,%r19 ;# 5879 subsi3/1 ldo -3(%r19),%r24 ;# 5880 addsi3/2 L$0609 ldi 20,%r26 ;# 5885 reload_outsi+2/2 copy %r8,%r25 ;# 5887 reload_outsi+2/1 copy %r11,%r23 ;# 5891 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op2,%r2 ;# 5893 call_internal_symref stw %r6,-52(%r30) ;# 5883 reload_outsi+2/6 ldo 5(%r6),%r6 ;# 5895 addsi3/2 ldi 22,%r26 ;# 5900 reload_outsi+2/2 copy %r8,%r25 ;# 5902 reload_outsi+2/1 ldi 5,%r24 ;# 5904 reload_outsi+2/2 copy %r11,%r23 ;# 5906 reload_outsi+2/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op2,%r2 ;# 5908 call_internal_symref stw %r6,-52(%r30) ;# 5898 reload_outsi+2/6 comib,>= 1,%r4,L$0590 ;# 5913 bleu+1 ldo 5(%r6),%r6 ;# 5910 addsi3/2 ldi 21,%r26 ;# 5921 reload_outsi+2/2 copy %r6,%r25 ;# 5923 reload_outsi+2/1 sub %r8,%r6,%r24 ;# 5917 subsi3/1 ldo 2(%r24),%r24 ;# 5925 addsi3/2 ldo -1(%r4),%r4 ;# 5919 addsi3/2 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl store_op2,%r2 ;# 5929 call_internal_symref copy %r4,%r23 ;# 5927 reload_outsi+2/1 ldo 5(%r6),%r6 ;# 5931 addsi3/2 stw %r6,-52(%r30) ;# 5936 reload_outsi+2/6 ldi 22,%r26 ;# 5938 reload_outsi+2/2 copy %r8,%r25 ;# 5940 reload_outsi+2/1 sub %r6,%r8,%r24 ;# 5942 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl insert_op2,%r2 ;# 5946 call_internal_symref copy %r4,%r23 ;# 5944 reload_outsi+2/1 ldo 5(%r6),%r6 ;# 5948 addsi3/2 L$0590 bl L$0043,%r0 ;# 5963 jump ldi 0,%r9 ;# 5956 reload_outsi+2/2 L$0511 stw %r23,-296(%r30) ;# 5968 reload_outsi+2/6 L$1182 ldw -296(%r30),%r20 ;# 5977 reload_outsi+2/5 comb,= %r16,%r20,L$0922 ;# 5979 bleu+1 ldo 1(%r20),%r21 ;# 5988 addsi3/2 ldb 0(%r20),%r20 ;# 5992 movqi+1/5 stw %r21,-296(%r30) ;# 5990 reload_outsi+2/6 comib,= 0,%r14,L$0612 ;# 5997 bleu+1 extru %r20,31,8,%r7 ;# 5993 zero_extendqisi2/1 addl %r14,%r7,%r19 ;# 5998 addsi3/1 ldb 0(%r19),%r7 ;# 6001 zero_extendqisi2/2 L$0612 bb,< %r15,19,L$0076 ;# 6019 bleu+3 ldw -276(%r30),%r1 ;# 8983 reload_outsi+2/5 comb,>>= %r1,%r21,L$0076 ;# 6025 bleu+1 extrs %r20,31,8,%r20 ;# 6030 extendqisi2 ldi 92,%r19 ;# 6032 reload_outsi+2/2 comb,=,n %r19,%r20,L$0397 ;# 6034 bleu+1 bl,n L$0076,%r0 ;# 6042 jump L$0619 ldw 4(%r5),%r20 ;# 8151 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8149 subsi3/1 ldo 1(%r19),%r19 ;# 8150 addsi3/2 comb,>>= %r20,%r19,L$0624 ;# 8152 bleu+1 copy %r6,%r8 ;# 6047 reload_outsi+2/1 ldil L'65536,%r3 ;# 8569 reload_outsi+2/3 L$0625 comb,= %r3,%r20,L$0944 ;# 6075 bleu+1 zdep %r20,30,31,%r19 ;# 6085 ashlsi3+1 comb,>>= %r3,%r19,L$0630 ;# 6093 bleu+1 stw %r19,4(%r5) ;# 6087 reload_outsi+2/6 stw %r3,4(%r5) ;# 6096 reload_outsi+2/6 L$0630 ldw 0(%r5),%r26 ;# 6103 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6107 call_value_internal_symref ldw 4(%r5),%r25 ;# 6105 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6115 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6111 reload_outsi+2/6 comb,= %r28,%r4,L$0623 ;# 6125 bleu+1 sub %r6,%r4,%r19 ;# 6127 subsi3/1 addl %r28,%r19,%r6 ;# 6130 addsi3/1 sub %r12,%r4,%r19 ;# 6131 subsi3/1 comib,= 0,%r10,L$0633 ;# 6136 bleu+1 addl %r28,%r19,%r12 ;# 6134 addsi3/1 sub %r10,%r4,%r19 ;# 6137 subsi3/1 addl %r28,%r19,%r10 ;# 6140 addsi3/1 L$0633 comib,= 0,%r8,L$0634 ;# 6143 bleu+1 sub %r8,%r4,%r19 ;# 6144 subsi3/1 addl %r28,%r19,%r8 ;# 6147 addsi3/1 L$0634 comib,= 0,%r9,L$0623 ;# 6150 bleu+1 sub %r9,%r4,%r19 ;# 6151 subsi3/1 addl %r28,%r19,%r9 ;# 6154 addsi3/1 L$0623 ldw 0(%r5),%r4 ;# 6055 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6059 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6056 subsi3/1 ldo 1(%r19),%r19 ;# 6057 addsi3/2 comb,<< %r20,%r19,L$0625 nop ;# 6061 bleu+1 L$0624 ldi 23,%r19 ;# 6176 movqi+1/2 bl L$0043,%r0 ;# 6189 jump stbs,ma %r19,1(%r6) ;# 6177 movqi+1/6 L$0639 ldw 4(%r5),%r20 ;# 8159 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8157 subsi3/1 ldo 1(%r19),%r19 ;# 8158 addsi3/2 comb,>>= %r20,%r19,L$0644 ;# 8160 bleu+1 copy %r6,%r8 ;# 6194 reload_outsi+2/1 ldil L'65536,%r3 ;# 8567 reload_outsi+2/3 L$0645 comb,= %r3,%r20,L$0944 ;# 6222 bleu+1 zdep %r20,30,31,%r19 ;# 6232 ashlsi3+1 comb,>>= %r3,%r19,L$0650 ;# 6240 bleu+1 stw %r19,4(%r5) ;# 6234 reload_outsi+2/6 stw %r3,4(%r5) ;# 6243 reload_outsi+2/6 L$0650 ldw 0(%r5),%r26 ;# 6250 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6254 call_value_internal_symref ldw 4(%r5),%r25 ;# 6252 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6262 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6258 reload_outsi+2/6 comb,= %r28,%r4,L$0643 ;# 6272 bleu+1 sub %r6,%r4,%r19 ;# 6274 subsi3/1 addl %r28,%r19,%r6 ;# 6277 addsi3/1 sub %r12,%r4,%r19 ;# 6278 subsi3/1 comib,= 0,%r10,L$0653 ;# 6283 bleu+1 addl %r28,%r19,%r12 ;# 6281 addsi3/1 sub %r10,%r4,%r19 ;# 6284 subsi3/1 addl %r28,%r19,%r10 ;# 6287 addsi3/1 L$0653 comib,= 0,%r8,L$0654 ;# 6290 bleu+1 sub %r8,%r4,%r19 ;# 6291 subsi3/1 addl %r28,%r19,%r8 ;# 6294 addsi3/1 L$0654 comib,= 0,%r9,L$0643 ;# 6297 bleu+1 sub %r9,%r4,%r19 ;# 6298 subsi3/1 addl %r28,%r19,%r9 ;# 6301 addsi3/1 L$0643 ldw 0(%r5),%r4 ;# 6202 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6206 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6203 subsi3/1 ldo 1(%r19),%r19 ;# 6204 addsi3/2 comb,<< %r20,%r19,L$0645 nop ;# 6208 bleu+1 L$0644 ldi 24,%r19 ;# 6323 movqi+1/2 bl L$0043,%r0 ;# 6336 jump stbs,ma %r19,1(%r6) ;# 6324 movqi+1/6 L$0659 ldw 4(%r5),%r20 ;# 8167 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8165 subsi3/1 ldo 1(%r19),%r19 ;# 8166 addsi3/2 comb,>>=,n %r20,%r19,L$0664 ;# 8168 bleu+1 ldil L'65536,%r3 ;# 8565 reload_outsi+2/3 L$0665 comb,= %r3,%r20,L$0944 ;# 6366 bleu+1 zdep %r20,30,31,%r19 ;# 6376 ashlsi3+1 comb,>>= %r3,%r19,L$0670 ;# 6384 bleu+1 stw %r19,4(%r5) ;# 6378 reload_outsi+2/6 stw %r3,4(%r5) ;# 6387 reload_outsi+2/6 L$0670 ldw 0(%r5),%r26 ;# 6394 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6398 call_value_internal_symref ldw 4(%r5),%r25 ;# 6396 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6406 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6402 reload_outsi+2/6 comb,= %r28,%r4,L$0663 ;# 6416 bleu+1 sub %r6,%r4,%r19 ;# 6418 subsi3/1 addl %r28,%r19,%r6 ;# 6421 addsi3/1 sub %r12,%r4,%r19 ;# 6422 subsi3/1 comib,= 0,%r10,L$0673 ;# 6427 bleu+1 addl %r28,%r19,%r12 ;# 6425 addsi3/1 sub %r10,%r4,%r19 ;# 6428 subsi3/1 addl %r28,%r19,%r10 ;# 6431 addsi3/1 L$0673 comib,= 0,%r8,L$0674 ;# 6434 bleu+1 sub %r8,%r4,%r19 ;# 6435 subsi3/1 addl %r28,%r19,%r8 ;# 6438 addsi3/1 L$0674 comib,= 0,%r9,L$0663 ;# 6441 bleu+1 sub %r9,%r4,%r19 ;# 6442 subsi3/1 addl %r28,%r19,%r9 ;# 6445 addsi3/1 L$0663 ldw 0(%r5),%r4 ;# 6346 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6350 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6347 subsi3/1 ldo 1(%r19),%r19 ;# 6348 addsi3/2 comb,<< %r20,%r19,L$0665 nop ;# 6352 bleu+1 L$0664 ldi 25,%r19 ;# 6467 movqi+1/2 bl L$0043,%r0 ;# 6480 jump stbs,ma %r19,1(%r6) ;# 6468 movqi+1/6 L$0679 ldw 4(%r5),%r20 ;# 8175 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8173 subsi3/1 ldo 1(%r19),%r19 ;# 8174 addsi3/2 comb,>>=,n %r20,%r19,L$0684 ;# 8176 bleu+1 ldil L'65536,%r3 ;# 8563 reload_outsi+2/3 L$0685 comb,= %r3,%r20,L$0944 ;# 6510 bleu+1 zdep %r20,30,31,%r19 ;# 6520 ashlsi3+1 comb,>>= %r3,%r19,L$0690 ;# 6528 bleu+1 stw %r19,4(%r5) ;# 6522 reload_outsi+2/6 stw %r3,4(%r5) ;# 6531 reload_outsi+2/6 L$0690 ldw 0(%r5),%r26 ;# 6538 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6542 call_value_internal_symref ldw 4(%r5),%r25 ;# 6540 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6550 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6546 reload_outsi+2/6 comb,= %r28,%r4,L$0683 ;# 6560 bleu+1 sub %r6,%r4,%r19 ;# 6562 subsi3/1 addl %r28,%r19,%r6 ;# 6565 addsi3/1 sub %r12,%r4,%r19 ;# 6566 subsi3/1 comib,= 0,%r10,L$0693 ;# 6571 bleu+1 addl %r28,%r19,%r12 ;# 6569 addsi3/1 sub %r10,%r4,%r19 ;# 6572 subsi3/1 addl %r28,%r19,%r10 ;# 6575 addsi3/1 L$0693 comib,= 0,%r8,L$0694 ;# 6578 bleu+1 sub %r8,%r4,%r19 ;# 6579 subsi3/1 addl %r28,%r19,%r8 ;# 6582 addsi3/1 L$0694 comib,= 0,%r9,L$0683 ;# 6585 bleu+1 sub %r9,%r4,%r19 ;# 6586 subsi3/1 addl %r28,%r19,%r9 ;# 6589 addsi3/1 L$0683 ldw 0(%r5),%r4 ;# 6490 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6494 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6491 subsi3/1 ldo 1(%r19),%r19 ;# 6492 addsi3/2 comb,<< %r20,%r19,L$0685 nop ;# 6496 bleu+1 L$0684 ldi 26,%r19 ;# 6611 movqi+1/2 bl L$0043,%r0 ;# 6624 jump stbs,ma %r19,1(%r6) ;# 6612 movqi+1/6 L$0699 ldw 4(%r5),%r20 ;# 8183 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8181 subsi3/1 ldo 1(%r19),%r19 ;# 8182 addsi3/2 comb,>>=,n %r20,%r19,L$0704 ;# 8184 bleu+1 ldil L'65536,%r3 ;# 8561 reload_outsi+2/3 L$0705 comb,= %r3,%r20,L$0944 ;# 6654 bleu+1 zdep %r20,30,31,%r19 ;# 6664 ashlsi3+1 comb,>>= %r3,%r19,L$0710 ;# 6672 bleu+1 stw %r19,4(%r5) ;# 6666 reload_outsi+2/6 stw %r3,4(%r5) ;# 6675 reload_outsi+2/6 L$0710 ldw 0(%r5),%r26 ;# 6682 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6686 call_value_internal_symref ldw 4(%r5),%r25 ;# 6684 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6694 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6690 reload_outsi+2/6 comb,= %r28,%r4,L$0703 ;# 6704 bleu+1 sub %r6,%r4,%r19 ;# 6706 subsi3/1 addl %r28,%r19,%r6 ;# 6709 addsi3/1 sub %r12,%r4,%r19 ;# 6710 subsi3/1 comib,= 0,%r10,L$0713 ;# 6715 bleu+1 addl %r28,%r19,%r12 ;# 6713 addsi3/1 sub %r10,%r4,%r19 ;# 6716 subsi3/1 addl %r28,%r19,%r10 ;# 6719 addsi3/1 L$0713 comib,= 0,%r8,L$0714 ;# 6722 bleu+1 sub %r8,%r4,%r19 ;# 6723 subsi3/1 addl %r28,%r19,%r8 ;# 6726 addsi3/1 L$0714 comib,= 0,%r9,L$0703 ;# 6729 bleu+1 sub %r9,%r4,%r19 ;# 6730 subsi3/1 addl %r28,%r19,%r9 ;# 6733 addsi3/1 L$0703 ldw 0(%r5),%r4 ;# 6634 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6638 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6635 subsi3/1 ldo 1(%r19),%r19 ;# 6636 addsi3/2 comb,<< %r20,%r19,L$0705 nop ;# 6640 bleu+1 L$0704 ldi 27,%r19 ;# 6755 movqi+1/2 bl L$0043,%r0 ;# 6768 jump stbs,ma %r19,1(%r6) ;# 6756 movqi+1/6 L$0719 ldw 4(%r5),%r20 ;# 8191 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8189 subsi3/1 ldo 1(%r19),%r19 ;# 8190 addsi3/2 comb,>>=,n %r20,%r19,L$0724 ;# 8192 bleu+1 ldil L'65536,%r3 ;# 8559 reload_outsi+2/3 L$0725 comb,= %r3,%r20,L$0944 ;# 6798 bleu+1 zdep %r20,30,31,%r19 ;# 6808 ashlsi3+1 comb,>>= %r3,%r19,L$0730 ;# 6816 bleu+1 stw %r19,4(%r5) ;# 6810 reload_outsi+2/6 stw %r3,4(%r5) ;# 6819 reload_outsi+2/6 L$0730 ldw 0(%r5),%r26 ;# 6826 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6830 call_value_internal_symref ldw 4(%r5),%r25 ;# 6828 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6838 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6834 reload_outsi+2/6 comb,= %r28,%r4,L$0723 ;# 6848 bleu+1 sub %r6,%r4,%r19 ;# 6850 subsi3/1 addl %r28,%r19,%r6 ;# 6853 addsi3/1 sub %r12,%r4,%r19 ;# 6854 subsi3/1 comib,= 0,%r10,L$0733 ;# 6859 bleu+1 addl %r28,%r19,%r12 ;# 6857 addsi3/1 sub %r10,%r4,%r19 ;# 6860 subsi3/1 addl %r28,%r19,%r10 ;# 6863 addsi3/1 L$0733 comib,= 0,%r8,L$0734 ;# 6866 bleu+1 sub %r8,%r4,%r19 ;# 6867 subsi3/1 addl %r28,%r19,%r8 ;# 6870 addsi3/1 L$0734 comib,= 0,%r9,L$0723 ;# 6873 bleu+1 sub %r9,%r4,%r19 ;# 6874 subsi3/1 addl %r28,%r19,%r9 ;# 6877 addsi3/1 L$0723 ldw 0(%r5),%r4 ;# 6778 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6782 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6779 subsi3/1 ldo 1(%r19),%r19 ;# 6780 addsi3/2 comb,<< %r20,%r19,L$0725 nop ;# 6784 bleu+1 L$0724 ldi 28,%r19 ;# 6899 movqi+1/2 bl L$0043,%r0 ;# 6912 jump stbs,ma %r19,1(%r6) ;# 6900 movqi+1/6 L$0739 ldw 4(%r5),%r20 ;# 8199 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8197 subsi3/1 ldo 1(%r19),%r19 ;# 8198 addsi3/2 comb,>>=,n %r20,%r19,L$0744 ;# 8200 bleu+1 ldil L'65536,%r3 ;# 8557 reload_outsi+2/3 L$0745 comb,= %r3,%r20,L$0944 ;# 6942 bleu+1 zdep %r20,30,31,%r19 ;# 6952 ashlsi3+1 comb,>>= %r3,%r19,L$0750 ;# 6960 bleu+1 stw %r19,4(%r5) ;# 6954 reload_outsi+2/6 stw %r3,4(%r5) ;# 6963 reload_outsi+2/6 L$0750 ldw 0(%r5),%r26 ;# 6970 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 6974 call_value_internal_symref ldw 4(%r5),%r25 ;# 6972 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 6982 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 6978 reload_outsi+2/6 comb,= %r28,%r4,L$0743 ;# 6992 bleu+1 sub %r6,%r4,%r19 ;# 6994 subsi3/1 addl %r28,%r19,%r6 ;# 6997 addsi3/1 sub %r12,%r4,%r19 ;# 6998 subsi3/1 comib,= 0,%r10,L$0753 ;# 7003 bleu+1 addl %r28,%r19,%r12 ;# 7001 addsi3/1 sub %r10,%r4,%r19 ;# 7004 subsi3/1 addl %r28,%r19,%r10 ;# 7007 addsi3/1 L$0753 comib,= 0,%r8,L$0754 ;# 7010 bleu+1 sub %r8,%r4,%r19 ;# 7011 subsi3/1 addl %r28,%r19,%r8 ;# 7014 addsi3/1 L$0754 comib,= 0,%r9,L$0743 ;# 7017 bleu+1 sub %r9,%r4,%r19 ;# 7018 subsi3/1 addl %r28,%r19,%r9 ;# 7021 addsi3/1 L$0743 ldw 0(%r5),%r4 ;# 6922 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 6926 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 6923 subsi3/1 ldo 1(%r19),%r19 ;# 6924 addsi3/2 comb,<< %r20,%r19,L$0745 nop ;# 6928 bleu+1 L$0744 ldi 10,%r19 ;# 7043 movqi+1/2 bl L$0043,%r0 ;# 7056 jump stbs,ma %r19,1(%r6) ;# 7044 movqi+1/6 L$0759 ldw 4(%r5),%r20 ;# 8207 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8205 subsi3/1 ldo 1(%r19),%r19 ;# 8206 addsi3/2 comb,>>=,n %r20,%r19,L$0764 ;# 8208 bleu+1 ldil L'65536,%r3 ;# 8555 reload_outsi+2/3 L$0765 comb,= %r3,%r20,L$0944 ;# 7086 bleu+1 zdep %r20,30,31,%r19 ;# 7096 ashlsi3+1 comb,>>= %r3,%r19,L$0770 ;# 7104 bleu+1 stw %r19,4(%r5) ;# 7098 reload_outsi+2/6 stw %r3,4(%r5) ;# 7107 reload_outsi+2/6 L$0770 ldw 0(%r5),%r26 ;# 7114 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7118 call_value_internal_symref ldw 4(%r5),%r25 ;# 7116 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7126 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7122 reload_outsi+2/6 comb,= %r28,%r4,L$0763 ;# 7136 bleu+1 sub %r6,%r4,%r19 ;# 7138 subsi3/1 addl %r28,%r19,%r6 ;# 7141 addsi3/1 sub %r12,%r4,%r19 ;# 7142 subsi3/1 comib,= 0,%r10,L$0773 ;# 7147 bleu+1 addl %r28,%r19,%r12 ;# 7145 addsi3/1 sub %r10,%r4,%r19 ;# 7148 subsi3/1 addl %r28,%r19,%r10 ;# 7151 addsi3/1 L$0773 comib,= 0,%r8,L$0774 ;# 7154 bleu+1 sub %r8,%r4,%r19 ;# 7155 subsi3/1 addl %r28,%r19,%r8 ;# 7158 addsi3/1 L$0774 comib,= 0,%r9,L$0763 ;# 7161 bleu+1 sub %r9,%r4,%r19 ;# 7162 subsi3/1 addl %r28,%r19,%r9 ;# 7165 addsi3/1 L$0763 ldw 0(%r5),%r4 ;# 7066 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7070 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7067 subsi3/1 ldo 1(%r19),%r19 ;# 7068 addsi3/2 comb,<< %r20,%r19,L$0765 nop ;# 7072 bleu+1 L$0764 ldi 11,%r19 ;# 7187 movqi+1/2 bl L$0043,%r0 ;# 7200 jump stbs,ma %r19,1(%r6) ;# 7188 movqi+1/6 L$0787 bb,< %r15,17,L$0076 ;# 7216 bleu+3 ldo -48(%r7),%r19 ;# 7224 addsi3/2 ldw -260(%r30),%r1 ;# 8986 reload_outsi+2/5 extru %r19,31,8,%r3 ;# 7225 zero_extendqisi2/1 comb,<< %r1,%r3,L$0939 ;# 7230 bleu+1 ldo -312(%r30),%r26 ;# 7244 addsi3/2 .CALL ARGW0=GR,ARGW1=GR bl group_in_compile_stack,%r2 ;# 7248 call_value_internal_symref copy %r3,%r25 ;# 7246 reload_outsi+2/1 extrs %r28,31,8,%r28 ;# 7251 extendqisi2 comib,<>,n 0,%r28,L$0076 ;# 7253 bleu+1 ldw 0(%r5),%r4 ;# 8212 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8215 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8213 subsi3/1 ldo 2(%r19),%r19 ;# 8214 addsi3/2 comb,>>= %r20,%r19,L$0795 ;# 8216 bleu+1 copy %r6,%r8 ;# 7260 reload_outsi+2/1 ldil L'65536,%r7 ;# 8553 reload_outsi+2/3 L$0796 comb,= %r7,%r20,L$0944 ;# 7288 bleu+1 zdep %r20,30,31,%r19 ;# 7298 ashlsi3+1 comb,>>= %r7,%r19,L$0801 ;# 7306 bleu+1 stw %r19,4(%r5) ;# 7300 reload_outsi+2/6 stw %r7,4(%r5) ;# 7309 reload_outsi+2/6 L$0801 ldw 0(%r5),%r26 ;# 7316 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7320 call_value_internal_symref ldw 4(%r5),%r25 ;# 7318 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7328 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7324 reload_outsi+2/6 comb,= %r28,%r4,L$0794 ;# 7338 bleu+1 sub %r6,%r4,%r19 ;# 7340 subsi3/1 addl %r28,%r19,%r6 ;# 7343 addsi3/1 sub %r12,%r4,%r19 ;# 7344 subsi3/1 comib,= 0,%r10,L$0804 ;# 7349 bleu+1 addl %r28,%r19,%r12 ;# 7347 addsi3/1 sub %r10,%r4,%r19 ;# 7350 subsi3/1 addl %r28,%r19,%r10 ;# 7353 addsi3/1 L$0804 comib,= 0,%r8,L$0805 ;# 7356 bleu+1 sub %r8,%r4,%r19 ;# 7357 subsi3/1 addl %r28,%r19,%r8 ;# 7360 addsi3/1 L$0805 comib,= 0,%r9,L$0794 ;# 7363 bleu+1 sub %r9,%r4,%r19 ;# 7364 subsi3/1 addl %r28,%r19,%r9 ;# 7367 addsi3/1 L$0794 ldw 0(%r5),%r4 ;# 7268 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7272 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7269 subsi3/1 ldo 2(%r19),%r19 ;# 7270 addsi3/2 comb,<< %r20,%r19,L$0796 nop ;# 7274 bleu+1 L$0795 ldi 7,%r19 ;# 7389 movqi+1/2 stbs,ma %r19,1(%r6) ;# 7390 movqi+1/6 bl L$0043,%r0 ;# 7405 jump stbs,ma %r3,1(%r6) ;# 7393 movqi+1/6 L$0811 bb,< %r15,30,L$0104 nop ;# 7414 bleu+3 L$0397 comib,= 0,%r14,L$0815 ;# 7429 bleu+1 addl %r14,%r7,%r19 ;# 7430 addsi3/1 bl L$0816,%r0 ;# 7434 jump ldb 0(%r19),%r19 ;# 7433 zero_extendqisi2/2 L$0815 copy %r7,%r19 ;# 7438 reload_outsi+2/1 L$0816 copy %r19,%r7 ;# 7441 reload_outsi+2/1 L$0076 comib,=,n 0,%r9,L$0820 ;# 7460 bleu+1 ldb 0(%r9),%r20 ;# 7463 zero_extendqisi2/2 addl %r9,%r20,%r19 ;# 7464 addsi3/1 ldo 1(%r19),%r19 ;# 7465 addsi3/2 comb,<> %r6,%r19,L$0820 ;# 7467 bleu+1 ldi 255,%r19 ;# 7472 reload_outsi+2/2 comb,= %r19,%r20,L$0820 ;# 7474 bleu+1 ldw -296(%r30),%r21 ;# 7476 reload_outsi+2/5 ldb 0(%r21),%r19 ;# 7478 movqi+1/5 extrs %r19,31,8,%r20 ;# 7479 extendqisi2 ldi 42,%r19 ;# 7481 reload_outsi+2/2 comb,= %r19,%r20,L$0820 ;# 7483 bleu+1 ldi 94,%r19 ;# 7490 reload_outsi+2/2 comb,=,n %r19,%r20,L$0820 ;# 7492 bleu+1 bb,>= %r15,30,L$0821 ;# 7497 movsi-4 ldi 92,%r19 ;# 7504 reload_outsi+2/2 comb,<>,n %r19,%r20,L$0822 ;# 7506 bleu+1 ldb 1(%r21),%r19 ;# 7510 movqi+1/5 extrs %r19,31,8,%r20 ;# 7511 extendqisi2 L$0821 ldi 43,%r19 ;# 7534 reload_outsi+2/2 comb,= %r19,%r20,L$0820 ;# 7536 bleu+1 ldi 63,%r19 ;# 7543 reload_outsi+2/2 comb,=,n %r19,%r20,L$0820 ;# 7545 bleu+1 L$0822 bb,>=,n %r15,22,L$0819 ;# 7553 movsi-4 bb,>= %r15,19,L$0823 ;# 7558 movsi-4 ldw -296(%r30),%r19 ;# 7560 reload_outsi+2/5 ldb 0(%r19),%r19 ;# 7562 movqi+1/5 ldi 123,%r20 ;# 7565 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 7563 extendqisi2 comb,=,n %r20,%r19,L$0820 ;# 7567 bleu+1 ldw 0(%r5),%r4 ;# 8228 reload_outsi+2/5 bl,n L$1177,%r0 ;# 7568 jump L$0823 ldw -296(%r30),%r21 ;# 7572 reload_outsi+2/5 ldb 0(%r21),%r19 ;# 7574 movqi+1/5 ldi 92,%r20 ;# 7577 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 7575 extendqisi2 comb,<>,n %r20,%r19,L$0819 ;# 7579 bleu+1 ldb 1(%r21),%r19 ;# 7583 movqi+1/5 ldi 123,%r20 ;# 7586 reload_outsi+2/2 extrs %r19,31,8,%r19 ;# 7584 extendqisi2 comb,<>,n %r20,%r19,L$0819 ;# 7588 bleu+1 L$0820 ldw 0(%r5),%r4 ;# 8220 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 8223 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8221 subsi3/1 ldo 2(%r19),%r19 ;# 8222 addsi3/2 comb,>>= %r20,%r19,L$0829 ;# 8224 bleu+1 copy %r6,%r8 ;# 7596 reload_outsi+2/1 ldil L'65536,%r3 ;# 8551 reload_outsi+2/3 L$0830 comb,= %r3,%r20,L$0944 ;# 7624 bleu+1 zdep %r20,30,31,%r19 ;# 7634 ashlsi3+1 comb,>>= %r3,%r19,L$0835 ;# 7642 bleu+1 stw %r19,4(%r5) ;# 7636 reload_outsi+2/6 stw %r3,4(%r5) ;# 7645 reload_outsi+2/6 L$0835 ldw 0(%r5),%r26 ;# 7652 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7656 call_value_internal_symref ldw 4(%r5),%r25 ;# 7654 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7664 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7660 reload_outsi+2/6 comb,= %r28,%r4,L$0828 ;# 7674 bleu+1 sub %r6,%r4,%r19 ;# 7676 subsi3/1 addl %r28,%r19,%r6 ;# 7679 addsi3/1 sub %r12,%r4,%r19 ;# 7680 subsi3/1 comib,= 0,%r10,L$0838 ;# 7685 bleu+1 addl %r28,%r19,%r12 ;# 7683 addsi3/1 sub %r10,%r4,%r19 ;# 7686 subsi3/1 addl %r28,%r19,%r10 ;# 7689 addsi3/1 L$0838 comib,= 0,%r8,L$0839 ;# 7692 bleu+1 sub %r8,%r4,%r19 ;# 7693 subsi3/1 addl %r28,%r19,%r8 ;# 7696 addsi3/1 L$0839 comib,= 0,%r9,L$0828 ;# 7699 bleu+1 sub %r9,%r4,%r19 ;# 7700 subsi3/1 addl %r28,%r19,%r9 ;# 7703 addsi3/1 L$0828 ldw 0(%r5),%r4 ;# 7604 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7608 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7605 subsi3/1 ldo 2(%r19),%r19 ;# 7606 addsi3/2 comb,<< %r20,%r19,L$0830 nop ;# 7610 bleu+1 L$0829 ldi 1,%r19 ;# 7725 movqi+1/2 stbs,ma %r19,1(%r6) ;# 7726 movqi+1/6 stbs,ma %r0,1(%r6) ;# 7729 movqi+1/6 ldo -1(%r6),%r9 ;# 7741 addsi3/2 L$0819 ldw 0(%r5),%r4 ;# 8228 reload_outsi+2/5 L$1177 ldw 4(%r5),%r20 ;# 8231 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 8229 subsi3/1 ldo 1(%r19),%r19 ;# 8230 addsi3/2 comb,>>=,n %r20,%r19,L$0848 ;# 8232 bleu+1 ldil L'65536,%r3 ;# 8549 reload_outsi+2/3 L$0849 comb,= %r3,%r20,L$0944 ;# 7771 bleu+1 zdep %r20,30,31,%r19 ;# 7781 ashlsi3+1 comb,>>= %r3,%r19,L$0854 ;# 7789 bleu+1 stw %r19,4(%r5) ;# 7783 reload_outsi+2/6 stw %r3,4(%r5) ;# 7792 reload_outsi+2/6 L$0854 ldw 0(%r5),%r26 ;# 7799 reload_outsi+2/5 .CALL ARGW0=GR,ARGW1=GR bl realloc,%r2 ;# 7803 call_value_internal_symref ldw 4(%r5),%r25 ;# 7801 reload_outsi+2/5 comiclr,<> 0,%r28,%r0 ;# 7811 bleu+1 bl L$0953,%r0 stw %r28,0(%r5) ;# 7807 reload_outsi+2/6 comb,= %r28,%r4,L$0847 ;# 7821 bleu+1 sub %r6,%r4,%r19 ;# 7823 subsi3/1 addl %r28,%r19,%r6 ;# 7826 addsi3/1 sub %r12,%r4,%r19 ;# 7827 subsi3/1 comib,= 0,%r10,L$0857 ;# 7832 bleu+1 addl %r28,%r19,%r12 ;# 7830 addsi3/1 sub %r10,%r4,%r19 ;# 7833 subsi3/1 addl %r28,%r19,%r10 ;# 7836 addsi3/1 L$0857 comib,= 0,%r8,L$0858 ;# 7839 bleu+1 sub %r8,%r4,%r19 ;# 7840 subsi3/1 addl %r28,%r19,%r8 ;# 7843 addsi3/1 L$0858 comib,= 0,%r9,L$0847 ;# 7846 bleu+1 sub %r9,%r4,%r19 ;# 7847 subsi3/1 addl %r28,%r19,%r9 ;# 7850 addsi3/1 L$0847 ldw 0(%r5),%r4 ;# 7751 reload_outsi+2/5 ldw 4(%r5),%r20 ;# 7755 reload_outsi+2/5 sub %r6,%r4,%r19 ;# 7752 subsi3/1 ldo 1(%r19),%r19 ;# 7753 addsi3/2 comb,<< %r20,%r19,L$0849 nop ;# 7757 bleu+1 L$0848 stbs,ma %r7,1(%r6) ;# 7872 movqi+1/6 ldb 0(%r9),%r19 ;# 7885 movqi+1/5 ldo 1(%r19),%r19 ;# 7888 addsi3/2 stb %r19,0(%r9) ;# 7890 movqi+1/6 L$0043 ldw -296(%r30),%r19 ;# 2328 reload_outsi+2/5 L$1161 comclr,= %r16,%r19,%r0 ;# 258 bleu+1 bl L$1178,%r0 ldw -296(%r30),%r19 ;# 2334 reload_outsi+2/5 L$0044 comib,= 0,%r10,L$0865 ;# 7913 bleu+1 ldi 13,%r26 ;# 7918 reload_outsi+2/2 copy %r10,%r25 ;# 7920 reload_outsi+2/1 sub %r6,%r25,%r24 ;# 7915 subsi3/1 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl store_op1,%r2 ;# 7924 call_internal_symref ldo -3(%r24),%r24 ;# 7922 addsi3/2 L$0865 ldw -304(%r30),%r19 ;# 7928 reload_outsi+2/5 comib,<>,n 0,%r19,L$0866 ;# 7930 bleu+1 .CALL ARGW0=GR bl free,%r2 ;# 7946 call_internal_symref ldw -312(%r30),%r26 ;# 7944 reload_outsi+2/5 ldw 0(%r5),%r19 ;# 7949 reload_outsi+2/5 ldi 0,%r28 ;# 7955 reload_outsi+2/2 sub %r6,%r19,%r19 ;# 7950 subsi3/1 bl L$0867,%r0 ;# 7957 jump stw %r19,8(%r5) ;# 7952 reload_outsi+2/6 L$0895 .CALL ARGW0=GR bl free,%r2 ;# 2269 call_internal_symref ldw -312(%r30),%r26 ;# 2267 reload_outsi+2/5 bl L$0867,%r0 ;# 2273 jump ldi 11,%r28 ;# 2271 reload_outsi+2/2 L$0900 .CALL ARGW0=GR bl free,%r2 ;# 3161 call_internal_symref ldw -312(%r30),%r26 ;# 3159 reload_outsi+2/5 bl L$0867,%r0 ;# 3165 jump ldi 4,%r28 ;# 3163 reload_outsi+2/2 L$0902 .CALL ARGW0=GR bl free,%r2 ;# 3218 call_internal_symref ldw -312(%r30),%r26 ;# 3216 reload_outsi+2/5 bl L$0867,%r0 ;# 3222 jump ldi 7,%r28 ;# 3220 reload_outsi+2/2 L$0903 .CALL ARGW0=GR bl free,%r2 ;# 3803 call_internal_symref ldw -312(%r30),%r26 ;# 3801 reload_outsi+2/5 bl L$0867,%r0 ;# 3807 jump ldi 5,%r28 ;# 3805 reload_outsi+2/2 L$0915 .CALL ARGW0=GR bl free,%r2 ;# 5461 call_internal_symref ldw -312(%r30),%r26 ;# 5459 reload_outsi+2/5 bl L$0867,%r0 ;# 5465 jump ldi 9,%r28 ;# 5463 reload_outsi+2/2 L$0917 .CALL ARGW0=GR bl free,%r2 ;# 5557 call_internal_symref ldw -312(%r30),%r26 ;# 5555 reload_outsi+2/5 bl L$0867,%r0 ;# 5561 jump ldi 13,%r28 ;# 5559 reload_outsi+2/2 L$0922 bl L$0867,%r0 ;# 5983 jump ldi 14,%r28 ;# 5981 reload_outsi+2/2 L$0939 .CALL ARGW0=GR bl free,%r2 ;# 7235 call_internal_symref ldw -312(%r30),%r26 ;# 7233 reload_outsi+2/5 bl L$0867,%r0 ;# 7239 jump ldi 6,%r28 ;# 7237 reload_outsi+2/2 L$0944 bl L$0867,%r0 ;# 7775 jump ldi 15,%r28 ;# 7773 reload_outsi+2/2 L$0866 .CALL ARGW0=GR bl free,%r2 ;# 7935 call_internal_symref ldw -312(%r30),%r26 ;# 7933 reload_outsi+2/5 ldi 8,%r28 ;# 7937 reload_outsi+2/2 L$0867 ldw -340(%r30),%r2 ;# 9026 reload_outsi+2/5 ldw -168(%r30),%r18 ;# 9028 reload_outsi+2/5 ldw -164(%r30),%r17 ;# 9030 reload_outsi+2/5 ldw -160(%r30),%r16 ;# 9032 reload_outsi+2/5 ldw -156(%r30),%r15 ;# 9034 reload_outsi+2/5 ldw -152(%r30),%r14 ;# 9036 reload_outsi+2/5 ldw -148(%r30),%r13 ;# 9038 reload_outsi+2/5 ldw -144(%r30),%r12 ;# 9040 reload_outsi+2/5 ldw -140(%r30),%r11 ;# 9042 reload_outsi+2/5 ldw -136(%r30),%r10 ;# 9044 reload_outsi+2/5 ldw -132(%r30),%r9 ;# 9046 reload_outsi+2/5 ldw -128(%r30),%r8 ;# 9048 reload_outsi+2/5 ldw -124(%r30),%r7 ;# 9050 reload_outsi+2/5 ldw -120(%r30),%r6 ;# 9052 reload_outsi+2/5 ldw -116(%r30),%r5 ;# 9054 reload_outsi+2/5 ldw -112(%r30),%r4 ;# 9056 reload_outsi+2/5 ldw -108(%r30),%r3 ;# 9058 reload_outsi+2/5 bv %r0(%r2) ;# 9061 return_internal ldo -320(%r30),%r30 ;# 9060 addsi3/2 .EXIT .PROCEND .data .align 1 re_syntax_table .block 256

stsp/binutils-ia16

41,373

gas/testsuite/gas/hppa/basic/weird.s

.stabs "weird.c",0x64,0,0,Label0 Label0: .stabs "inttype:t1=bu4;0;32;",0x80,0,0,0 .stabs "sym32: !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type32:t32= !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "attr104:G404=@h !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr105:G405=@i !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "var0:G300=@a8;1",0x20,0,0, 0 .export var0 .data .align 4 var0: .long 42 .stabs "sym33:! !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym35:# !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym36:$ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym37:% !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym38:& !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym39:' !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym40:( !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym41:) !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym42:* !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym43:+ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym44:, !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym45:- !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .export attr122 .data .align 4 attr122: .long 42 .export attr123 .data .align 4 attr123: .long 42 .export attr124 .data .align 4 attr124: .long 42 .stabs "sym46:. !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym47:/ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym48:0 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym49:1 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym50:2 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "attr96:G396=@` !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr97:G397=@a !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr98:G398=@b !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr99:G399=@c !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "sym51:3 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym52:4 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym53:5 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym54:6 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym55:7 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym56:8 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym57:9 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym58:: !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym59:; !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym60:< !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym61:= !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym62:> !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym63:? !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym64:@ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym65:A !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym66:B !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym67:C !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym68:D !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym69:E !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym70:F !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym71:G !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym72:H !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym73:I !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym74:J !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym75:K !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym76:L !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym77:M !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym78:N !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym79:O !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym80:P !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym81:Q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym82:R !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym83:S !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym84:T !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym85:U !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym86:V !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym87:W !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym88:X !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym89:Y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym90:Z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym91:[ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym93:] !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym94:^ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym95:_ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym96:` !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym97:a !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym98:b !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym99:c !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym100:d !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym101:e !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym102:f !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym103:g !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym104:h !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym105:i !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym106:j !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym107:k !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym108:l !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym109:m !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym110:n !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym111:o !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym112:p !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym113:q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym114:r !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym115:s !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym116:t !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym117:u !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym118:v !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym119:w !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym120:x !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym121:y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym122:z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym123:{ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym124:| !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym125:} !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "sym126:~ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type33:t33=! !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type35:t35=# !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type36:t36=$ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type37:t37=% !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type38:t38=& !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type39:t39=' !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type40:t40=( !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type41:t41=) !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type42:t42=* !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type43:t43=+ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type44:t44=, !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type45:t45=- !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type46:t46=. !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type47:t47=/ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type48:t48=0 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type49:t49=1 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type50:t50=2 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type51:t51=3 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type52:t52=4 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type53:t53=5 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type54:t54=6 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type55:t55=7 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type56:t56=8 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type57:t57=9 !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type58:t58=: !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type59:t59=; !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type60:t60=< !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type61:t61== !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type62:t62=> !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type63:t63=? !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type64:t64=@ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type65:t65=A !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type66:t66=B !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type67:t67=C !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .export attr66 .data .align 4 attr66: .long 42 .export attr67 .data .align 4 attr67: .long 42 .export attr68 .data .align 4 attr68: .long 42 .export attr69 .data .align 4 attr69: .long 42 .stabs "type68:t68=D !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type69:t69=E !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type70:t70=F !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type71:t71=G !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type72:t72=H !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type73:t73=I !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type74:t74=J !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type75:t75=K !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type76:t76=L !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type77:t77=M !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type78:t78=N !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type79:t79=O !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type80:t80=P !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type81:t81=Q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type82:t82=R !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type83:t83=S !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type84:t84=T !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type85:t85=U !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type86:t86=V !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type87:t87=W !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "attr69:G369=@E !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr70:G370=@F !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr71:G371=@G !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "type88:t88=X !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type89:t89=Y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type90:t90=Z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type91:t91=[ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type93:t93=] !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type94:t94=^ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type95:t95=_ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type96:t96=` !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type97:t97=a !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type98:t98=b !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type99:t99=c !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type100:t100=d !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type101:t101=e !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type102:t102=f !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type103:t103=g !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type104:t104=h !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type105:t105=i !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type106:t106=j !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type107:t107=k !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type108:t108=l !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type109:t109=m !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type110:t110=n !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type111:t111=o !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type112:t112=p !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type113:t113=q !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type114:t114=r !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type115:t115=s !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type116:t116=t !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type117:t117=u !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type118:t118=v !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type119:t119=w !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type120:t120=x !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type121:t121=y !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type122:t122=z !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type123:t123={ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type124:t124=| !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type125:t125=} !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type126:t126=~ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "attr32:G332=@ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr33:G333=@! !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr35:G334=@# !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "primary:G200=ered:0,green:1,blue:2,;", 0x20,0,0, 0 .stabs "attr36:G335=@$ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .export primary .data .align 4 primary: .long 42 .stabs "attr37:G337=@% !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "const69:c=e1,69", 0x80,0,0, 0 .stabs "const70:c=e190=bs2;0;16;,70", 0x80,0,0, 0 .stabs "attr38:G338=@& !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "bad_neg0type:t201=s8field0:1,0,32;field2:-534,32,64;field3:-1,96,32;;", 0x80,0,0, 0 .stabs "bad_neg0:G201", 0x20,0,0, 0 .export bad_neg0 .data .align 4 bad_neg0: .long 42 .long 43, 44, 45 .stabs "attr39:G339=@' !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr41:G341=@) !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr42:G342=@* !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr43:G343=@+ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr44:G344=@, !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr46:G346=@. !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr47:G347=@/ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr58:G358=@: !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr59:G359=@;@ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr60:G360=@< !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr61:G361=@= !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr62:G362=@> !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr63:G363=@? !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr64:G364=@@ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr65:G365=@A !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr66:G366=@B !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr67:G367=@C !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr68:G368=@D !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr72:G372=@H !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr73:G373=@I !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr74:G374=@J !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr75:G375=@K !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr76:G376=@L !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr77:G377=@M !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr78:G378=@N !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr79:G379=@O !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr80:G380=@P !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr81:G381=@Q !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr82:G382=@R !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr83:G383=@S !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr84:G384=@T !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr85:G385=@U !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr86:G386=@V !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr87:G387=@W !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr88:G388=@X !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr89:G389=@Y !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr90:G390=@Z !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr91:G391=@[ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr93:G393=@] !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .export _common0 .data .align 4 _common0: .long 42 .long 24 .long 22 .export common0 .data .align 4 common0: .long 42 .long 24 .long 22 .stabs "common0",0xe2,0,0,0 .stabs "common0var0:S1", 0x20,0,0, 0 .stabs "common0var1:S1", 0x20,0,0, 4 .stabs "common0var2:S1", 0x20,0,0, 8 .stabs "common0",0xe4,0,0,0 .stabs "attr94:G394=@^ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr95:G395=@_ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr100:G400=@d !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr101:G401=@e !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr102:G402=@f !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr103:G403=@g !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr106:G406=@j !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr107:G407=@k !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr108:G408=@l !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr109:G409=@m !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr110:G410=@n !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr111:G411=@o !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr112:G412=@p !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr113:G413=@q !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr114:G414=@r !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr115:G415=@s !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr116:G416=@t !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr117:G417=@u !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr118:G418=@v !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr119:G419=@w !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr120:G420=@x !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr121:G421=@y !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr122:G422=@z !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr123:G423=@{ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr124:G424=@| !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr125:G425=@} !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .stabs "attr126:G426=@~ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0 .export attr32 .data .align 4 attr32: .long 42 .export attr33 .data .align 4 attr33: .long 42 .export attr35 .data .align 4 attr35: .long 42 .export attr36 .data .align 4 attr36: .long 42 .export attr37 .data .align 4 attr37: .long 42 .export attr38 .data .align 4 attr38: .long 42 .export attr39 .data .align 4 attr39: .long 42 .export attr41 .data .align 4 attr41: .long 42 .export attr42 .data .align 4 attr42: .long 42 .export attr43 .data .align 4 attr43: .long 42 .export attr44 .data .align 4 attr44: .long 42 .export attr46 .data .align 4 attr46: .long 42 .export attr47 .data .align 4 attr47: .long 42 .export attr58 .data .align 4 attr58: .long 42 .export attr59 .data .align 4 attr59: .long 42 .export attr60 .data .align 4 attr60: .long 42 .export attr61 .data .align 4 attr61: .long 42 .export attr62 .data .align 4 attr62: .long 42 .export attr63 .data .align 4 attr63: .long 42 .export attr64 .data .align 4 attr64: .long 42 .export attr65 .data .align 4 attr65: .long 42 .export attr70 .data .align 4 attr70: .long 42 .export attr71 .data .align 4 attr71: .long 42 .export attr72 .data .align 4 attr72: .long 42 .export attr73 .data .align 4 attr73: .long 42 .export attr74 .data .align 4 attr74: .long 42 .export attr75 .data .align 4 attr75: .long 42 .export attr76 .data .align 4 attr76: .long 42 .export attr77 .data .align 4 attr77: .long 42 .export attr78 .data .align 4 attr78: .long 42 .export attr79 .data .align 4 attr79: .long 42 .export attr80 .data .align 4 attr80: .long 42 .export attr81 .data .align 4 attr81: .long 42 .export attr82 .data .align 4 attr82: .long 42 .export attr83 .data .align 4 attr83: .long 42 .export attr84 .data .align 4 attr84: .long 42 .stabs "float72type:t202=R87;9;", 0x80,0,0, 0 .stabs "int256var:G203=bu32;0;256;", 0x20,0,0, 0 .export int256var .data .align 4 int256var: .long 42 .long 0x2b, 0x2c, 0x2d, 0x2d, 0x2c, 0x2b, 0x2a .stabs "consth:c=e1,4294967296", 0x80,0,0, 0 .stabs "consth2:c=e1,-734723985732642758928475678987234563284937456", 0x80,0,0, 0 .stabs "bad_neg0const:c=S201,128,128,11222211343434345656565677888877", 0x80,0,0, 0 .stabs "bad_type0:t(-3,7)", 0x80,0,0, 0 .stabs "bad_type1:t(42,6)", 0x80,0,0, 0 .stabs "array_index0:t205=r1;0;5;", 0x80,0,0, 0 .stabs "array0:G206=a205;1", 0x20,0,0, 0 .export array0 .data .align 4 array0: .long 42 .long 43, 44, 45, 46, 47 .stabs "array_index1:t207=", 0x80,0,0, 0 .stabs "array1:G208=aeai1_red:0,ai1_green:1,ai1_blue:2,;;1", 0x20,0,0, 0 .export array1 .data .align 4 array1: .long 42 .long 43, 44 .stabs "inttype_one:t209=1", 0x80,0,0, 0 .stabs "inttype_two:t210=1", 0x80,0,0, 0 .stabs "one_var:G209", 0x20,0,0, 0 .export one_var .data .align 4 one_var: .long 42 .stabs "two_var:G210", 0x20,0,0, 0 .export two_var .data .align 4 two_var: .long 42 .stabs "intp:t211=*1", 0x80,0,0, 0 .stabs "pointer_to_int_var:G212=*1", 0x80,0,0, 0 .stabs "intp_var:G211", 0x20,0,0, 0 .export intp_var .data .align 4 intp_var: .long 42 .stabs "unrecog_const:c=xjksdflskd33,4;473;", 0x80,0,0, 0 .export attr85 .data .align 4 attr85: .long 42 .export attr86 .data .align 4 attr86: .long 42 .export attr87 .data .align 4 attr87: .long 42 .export attr88 .data .align 4 attr88: .long 42 .export attr89 .data .align 4 attr89: .long 42 .export attr90 .data .align 4 attr90: .long 42 .export attr91 .data .align 4 attr91: .long 42 .export attr92 .data .align 4 attr92: .long 42 .export attr93 .data .align 4 attr93: .long 42 .export attr94 .data .align 4 attr94: .long 42 .export attr95 .data .align 4 attr95: .long 42 .export attr96 .data .align 4 attr96: .long 42 .export attr97 .data .align 4 attr97: .long 42 .export attr98 .data .align 4 attr98: .long 42 .export attr99 .data .align 4 attr99: .long 42 .export attr100 .data .align 4 attr100: .long 42 .export attr101 .data .align 4 attr101: .long 42 .export attr102 .data .align 4 attr102: .long 42 .export attr103 .data .align 4 attr103: .long 42 .export attr104 .data .align 4 attr104: .long 42 .export attr105 .data .align 4 attr105: .long 42 .export attr106 .data .align 4 attr106: .long 42 .export attr107 .data .align 4 attr107: .long 42 .export attr108 .data .align 4 attr108: .long 42 .export attr109 .data .align 4 attr109: .long 42 .export attr110 .data .align 4 attr110: .long 42 .export attr111 .data .align 4 attr111: .long 42 .export attr112 .data .align 4 attr112: .long 42 .export attr113 .data .align 4 attr113: .long 42 .export attr114 .data .align 4 attr114: .long 42 .export attr115 .data .align 4 attr115: .long 42 .export attr116 .data .align 4 attr116: .long 42 .export attr117 .data .align 4 attr117: .long 42 .export attr118 .data .align 4 attr118: .long 42 .export attr119 .data .align 4 attr119: .long 42 .export attr120 .data .align 4 attr120: .long 42 .export attr121 .data .align 4 attr121: .long 42 .export attr125 .data .align 4 attr125: .long 42 .export attr126 .data .align 4 attr126: .long 42 .stabs "var1:G301=@s32;1",0x20,0,0, 0 .export var1 .data .align 4 var1: .long 42 .stabs "var2:G302=@p42;1",0x20,0,0, 0 .export var2 .data .align 4 var2: .long 42 .stabs "var3:G303=@P;1",0x20,0,0, 0 .export var3 .data .align 4 var3: .long 42 .stabs "v_comb:G448=s24!2,020,445=s12!1,120,444=s4x:1,0,32;;;$vb444:446=*444,0;a:/01,32,32;;;0264,447=s12!1,120,444;$vb444:446,0;b:/01,32,32;;;comb:/01,128,32;;", 0x20,0,0, 0 .export v_comb .align 1 v_comb: .long v_comb_shared .long 43 .long v_comb_shared .long 44 .long 45 v_comb_shared: .long 42 .stabs "sym92:\\ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "type92:t92=\\ !#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~",0x80,0,0,0 .stabs "attr92:G392=@\\ !#$%&'()*+,-./0123456789:<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[]^_`abcdefghijklmnopqrstuvwxyz{|}~;1",0x20,0,0, 0

stsp/binutils-ia16

1,256

gas/testsuite/gas/hppa/basic/coprmem.s

.code .align 4 ; Basic copr memory tests which also test the various ; addressing modes and completers. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. ; copr_indexing_load: cldwx,4 %r5(%sr0,%r4),%r26 cldwx,4,s %r5(%sr0,%r4),%r26 cldwx,4,m %r5(%sr0,%r4),%r26 cldwx,4,sm %r5(%sr0,%r4),%r26 clddx,4 %r5(%sr0,%r4),%r26 clddx,4,s %r5(%sr0,%r4),%r26 clddx,4,m %r5(%sr0,%r4),%r26 clddx,4,sm %r5(%sr0,%r4),%r26 copr_indexing_store: cstwx,4 %r26,%r5(%sr0,%r4) cstwx,4,s %r26,%r5(%sr0,%r4) cstwx,4,m %r26,%r5(%sr0,%r4) cstwx,4,sm %r26,%r5(%sr0,%r4) cstdx,4 %r26,%r5(%sr0,%r4) cstdx,4,s %r26,%r5(%sr0,%r4) cstdx,4,m %r26,%r5(%sr0,%r4) cstdx,4,sm %r26,%r5(%sr0,%r4) copr_short_memory: cldws,4 0(%sr0,%r4),%r26 cldws,4,mb 0(%sr0,%r4),%r26 cldws,4,ma 0(%sr0,%r4),%r26 cldds,4 0(%sr0,%r4),%r26 cldds,4,mb 0(%sr0,%r4),%r26 cldds,4,ma 0(%sr0,%r4),%r26 cstws,4 %r26,0(%sr0,%r4) cstws,4,mb %r26,0(%sr0,%r4) cstws,4,ma %r26,0(%sr0,%r4) cstds,4 %r26,0(%sr0,%r4) cstds,4,mb %r26,0(%sr0,%r4) cstds,4,ma %r26,0(%sr0,%r4) ; gas fucks this up thinks it gets the expression 4 modulo 5 ; cldwx,4 %r5(0,%r4),%r%r26

stsp/binutils-ia16

1,418

gas/testsuite/gas/hppa/basic/sh2add.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sh2add %r4,%r5,%r6 sh2add,= %r4,%r5,%r6 sh2add,< %r4,%r5,%r6 sh2add,<= %r4,%r5,%r6 sh2add,nuv %r4,%r5,%r6 sh2add,znv %r4,%r5,%r6 sh2add,sv %r4,%r5,%r6 sh2add,od %r4,%r5,%r6 sh2add,tr %r4,%r5,%r6 sh2add,<> %r4,%r5,%r6 sh2add,>= %r4,%r5,%r6 sh2add,> %r4,%r5,%r6 sh2add,uv %r4,%r5,%r6 sh2add,vnz %r4,%r5,%r6 sh2add,nsv %r4,%r5,%r6 sh2add,ev %r4,%r5,%r6 sh2addl %r4,%r5,%r6 sh2addl,= %r4,%r5,%r6 sh2addl,< %r4,%r5,%r6 sh2addl,<= %r4,%r5,%r6 sh2addl,nuv %r4,%r5,%r6 sh2addl,znv %r4,%r5,%r6 sh2addl,sv %r4,%r5,%r6 sh2addl,od %r4,%r5,%r6 sh2addl,tr %r4,%r5,%r6 sh2addl,<> %r4,%r5,%r6 sh2addl,>= %r4,%r5,%r6 sh2addl,> %r4,%r5,%r6 sh2addl,uv %r4,%r5,%r6 sh2addl,vnz %r4,%r5,%r6 sh2addl,nsv %r4,%r5,%r6 sh2addl,ev %r4,%r5,%r6 sh2addo %r4,%r5,%r6 sh2addo,= %r4,%r5,%r6 sh2addo,< %r4,%r5,%r6 sh2addo,<= %r4,%r5,%r6 sh2addo,nuv %r4,%r5,%r6 sh2addo,znv %r4,%r5,%r6 sh2addo,sv %r4,%r5,%r6 sh2addo,od %r4,%r5,%r6 sh2addo,tr %r4,%r5,%r6 sh2addo,<> %r4,%r5,%r6 sh2addo,>= %r4,%r5,%r6 sh2addo,> %r4,%r5,%r6 sh2addo,uv %r4,%r5,%r6 sh2addo,vnz %r4,%r5,%r6 sh2addo,nsv %r4,%r5,%r6 sh2addo,ev %r4,%r5,%r6

stsp/binutils-ia16

1,183

gas/testsuite/gas/hppa/basic/fmem.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fldwx %r4(%sr0,%r5),%fr6 fldwx,s %r4(%sr0,%r5),%fr6 fldwx,m %r4(%sr0,%r5),%fr6 fldwx,sm %r4(%sr0,%r5),%fr6 flddx %r4(%sr0,%r5),%fr6 flddx,s %r4(%sr0,%r5),%fr6 flddx,m %r4(%sr0,%r5),%fr6 flddx,sm %r4(%sr0,%r5),%fr6 fstwx %fr6,%r4(%sr0,%r5) fstwx,s %fr6,%r4(%sr0,%r5) fstwx,m %fr6,%r4(%sr0,%r5) fstwx,sm %fr6,%r4(%sr0,%r5) fstdx %fr6,%r4(%sr0,%r5) fstdx,s %fr6,%r4(%sr0,%r5) fstdx,m %fr6,%r4(%sr0,%r5) fstdx,sm %fr6,%r4(%sr0,%r5) fstqx %fr6,%r4(%sr0,%r5) fstqx,s %fr6,%r4(%sr0,%r5) fstqx,m %fr6,%r4(%sr0,%r5) fstqx,sm %fr6,%r4(%sr0,%r5) fldws 0(%sr0,%r5),%fr6 fldws,mb 0(%sr0,%r5),%fr6 fldws,ma 0(%sr0,%r5),%fr6 fldds 0(%sr0,%r5),%fr6 fldds,mb 0(%sr0,%r5),%fr6 fldds,ma 0(%sr0,%r5),%fr6 fstws %fr6,0(%sr0,%r5) fstws,mb %fr6,0(%sr0,%r5) fstws,ma %fr6,0(%sr0,%r5) fstds %fr6,0(%sr0,%r5) fstds,mb %fr6,0(%sr0,%r5) fstds,ma %fr6,0(%sr0,%r5) fstqs %fr6,0(%sr0,%r5) fstqs,mb %fr6,0(%sr0,%r5) fstqs,ma %fr6,0(%sr0,%r5)

stsp/binutils-ia16

1,143

gas/testsuite/gas/hppa/basic/fmemLRbug.s

.code .export f f: .proc .callinfo frame=0,no_calls .entry fstws %fr6R,0(%r26) fstws %fr6L,4(%r26) fstws %fr6,8(%r26) fstds %fr6L,4(%r26) fstds %fr6,8(%r26) fldws 0(%r26),%fr6R fldws 4(%r26),%fr6L fldws 8(%r26),%fr6 fldds 4(%r26),%fr6L fldds 8(%r26),%fr6 fstws %fr6R,0(%sr0,%r26) fstws %fr6L,4(%sr0,%r26) fstws %fr6,8(%sr0,%r26) fstds %fr6L,4(%sr0,%r26) fstds %fr6,8(%sr0,%r26) fldws 0(%sr0,%r26),%fr6R fldws 4(%sr0,%r26),%fr6L fldws 8(%sr0,%r26),%fr6 fldds 4(%sr0,%r26),%fr6L fldds 8(%sr0,%r26),%fr6 fstwx %fr6R,%r25(%r26) fstwx %fr6L,%r25(%r26) fstwx %fr6,%r25(%r26) fstdx %fr6L,%r25(%r26) fstdx %fr6,%r25(%r26) fldwx %r25(%r26),%fr6R fldwx %r25(%r26),%fr6L fldwx %r25(%r26),%fr6 flddx %r25(%r26),%fr6L flddx %r25(%r26),%fr6 fstwx %fr6R,%r25(%sr0,%r26) fstwx %fr6L,%r25(%sr0,%r26) fstwx %fr6,%r25(%sr0,%r26) fstdx %fr6L,%r25(%sr0,%r26) fstdx %fr6,%r25(%sr0,%r26) fldwx %r25(%sr0,%r26),%fr6R fldwx %r25(%sr0,%r26),%fr6L fldwx %r25(%sr0,%r26),%fr6 flddx %r25(%sr0,%r26),%fr6L flddx %r25(%sr0,%r26),%fr6 bv %r0(%r2) nop .exit .procend

stsp/binutils-ia16

1,711

gas/testsuite/gas/hppa/basic/fp_comp.s

.level 1.1 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fcpy,sgl %fr5,%fr10 fcpy,dbl %fr5,%fr10 fcpy,quad %fr5,%fr10 fcpy,sgl %fr20,%fr24 fcpy,dbl %fr20,%fr24 fabs,sgl %fr5,%fr10 fabs,dbl %fr5,%fr10 fabs,quad %fr5,%fr10 fabs,sgl %fr20,%fr24 fabs,dbl %fr20,%fr24 fsqrt,sgl %fr5,%fr10 fsqrt,dbl %fr5,%fr10 fsqrt,quad %fr5,%fr10 fsqrt,sgl %fr20,%fr24 fsqrt,dbl %fr20,%fr24 frnd,sgl %fr5,%fr10 frnd,dbl %fr5,%fr10 frnd,quad %fr5,%fr10 frnd,sgl %fr20,%fr24 frnd,dbl %fr20,%fr24 fadd,sgl %fr4,%fr8,%fr12 fadd,dbl %fr4,%fr8,%fr12 fadd,quad %fr4,%fr8,%fr12 fadd,sgl %fr20,%fr24,%fr28 fadd,dbl %fr20,%fr24,%fr28 fadd,quad %fr20,%fr24,%fr28 fsub,sgl %fr4,%fr8,%fr12 fsub,dbl %fr4,%fr8,%fr12 fsub,quad %fr4,%fr8,%fr12 fsub,sgl %fr20,%fr24,%fr28 fsub,dbl %fr20,%fr24,%fr28 fsub,quad %fr20,%fr24,%fr28 fmpy,sgl %fr4,%fr8,%fr12 fmpy,dbl %fr4,%fr8,%fr12 fmpy,quad %fr4,%fr8,%fr12 fmpy,sgl %fr20,%fr24,%fr28 fmpy,dbl %fr20,%fr24,%fr28 fmpy,quad %fr20,%fr24,%fr28 fdiv,sgl %fr4,%fr8,%fr12 fdiv,dbl %fr4,%fr8,%fr12 fdiv,quad %fr4,%fr8,%fr12 fdiv,sgl %fr20,%fr24,%fr28 fdiv,dbl %fr20,%fr24,%fr28 fdiv,quad %fr20,%fr24,%fr28 frem,sgl %fr4,%fr8,%fr12 frem,dbl %fr4,%fr8,%fr12 frem,quad %fr4,%fr8,%fr12 frem,sgl %fr20,%fr24,%fr28 frem,dbl %fr20,%fr24,%fr28 frem,quad %fr20,%fr24,%fr28 fmpyadd,sgl %fr16,%fr17,%fr18,%fr19,%fr20 fmpyadd,dbl %fr16,%fr17,%fr18,%fr19,%fr20 fmpysub,sgl %fr16,%fr17,%fr18,%fr19,%fr20 fmpysub,dbl %fr16,%fr17,%fr18,%fr19,%fr20 xmpyu %fr4,%fr5,%fr6

stsp/binutils-ia16

2,815

gas/testsuite/gas/hppa/basic/sub2.s

.LEVEL 2.0 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sub,* %r4,%r5,%r6 sub,*= %r4,%r5,%r6 sub,*< %r4,%r5,%r6 sub,*<= %r4,%r5,%r6 sub,*<< %r4,%r5,%r6 sub,*<<= %r4,%r5,%r6 sub,*sv %r4,%r5,%r6 sub,*od %r4,%r5,%r6 sub,*tr %r4,%r5,%r6 sub,*<> %r4,%r5,%r6 sub,*>= %r4,%r5,%r6 sub,*> %r4,%r5,%r6 sub,*>>= %r4,%r5,%r6 sub,*>> %r4,%r5,%r6 sub,*nsv %r4,%r5,%r6 sub,*ev %r4,%r5,%r6 sub,tsv,* %r4,%r5,%r6 sub,tsv,*= %r4,%r5,%r6 sub,tsv,*< %r4,%r5,%r6 sub,tsv,*<= %r4,%r5,%r6 sub,tsv,*<< %r4,%r5,%r6 sub,tsv,*<<= %r4,%r5,%r6 sub,tsv,*sv %r4,%r5,%r6 sub,tsv,*od %r4,%r5,%r6 sub,tsv,*tr %r4,%r5,%r6 sub,tsv,*<> %r4,%r5,%r6 sub,tsv,*>= %r4,%r5,%r6 sub,tsv,*> %r4,%r5,%r6 sub,tsv,*>>= %r4,%r5,%r6 sub,tsv,*>> %r4,%r5,%r6 sub,tsv,*nsv %r4,%r5,%r6 sub,tsv,*ev %r4,%r5,%r6 sub,db,* %r4,%r5,%r6 sub,db,*= %r4,%r5,%r6 sub,db,*< %r4,%r5,%r6 sub,db,*<= %r4,%r5,%r6 sub,db,*<< %r4,%r5,%r6 sub,db,*<<= %r4,%r5,%r6 sub,db,*sv %r4,%r5,%r6 sub,db,*od %r4,%r5,%r6 sub,db,*tr %r4,%r5,%r6 sub,db,*<> %r4,%r5,%r6 sub,db,*>= %r4,%r5,%r6 sub,db,*> %r4,%r5,%r6 sub,db,*>>= %r4,%r5,%r6 sub,db,*>> %r4,%r5,%r6 sub,db,*nsv %r4,%r5,%r6 sub,db,*ev %r4,%r5,%r6 sub,db,tsv,* %r4,%r5,%r6 sub,db,tsv,*= %r4,%r5,%r6 sub,db,tsv,*< %r4,%r5,%r6 sub,db,tsv,*<= %r4,%r5,%r6 sub,db,tsv,*<< %r4,%r5,%r6 sub,db,tsv,*<<= %r4,%r5,%r6 sub,db,tsv,*sv %r4,%r5,%r6 sub,db,tsv,*od %r4,%r5,%r6 sub,tsv,db,*tr %r4,%r5,%r6 sub,tsv,db,*<> %r4,%r5,%r6 sub,tsv,db,*>= %r4,%r5,%r6 sub,tsv,db,*> %r4,%r5,%r6 sub,tsv,db,*>>= %r4,%r5,%r6 sub,tsv,db,*>> %r4,%r5,%r6 sub,tsv,db,*nsv %r4,%r5,%r6 sub,tsv,db,*ev %r4,%r5,%r6 sub,tc,* %r4,%r5,%r6 sub,tc,*= %r4,%r5,%r6 sub,tc,*< %r4,%r5,%r6 sub,tc,*<= %r4,%r5,%r6 sub,tc,*<< %r4,%r5,%r6 sub,tc,*<<= %r4,%r5,%r6 sub,tc,*sv %r4,%r5,%r6 sub,tc,*od %r4,%r5,%r6 sub,tc,*tr %r4,%r5,%r6 sub,tc,*<> %r4,%r5,%r6 sub,tc,*>= %r4,%r5,%r6 sub,tc,*> %r4,%r5,%r6 sub,tc,*>>= %r4,%r5,%r6 sub,tc,*>> %r4,%r5,%r6 sub,tc,*nsv %r4,%r5,%r6 sub,tc,*ev %r4,%r5,%r6 sub,tc,tsv,* %r4,%r5,%r6 sub,tc,tsv,*= %r4,%r5,%r6 sub,tc,tsv,*< %r4,%r5,%r6 sub,tc,tsv,*<= %r4,%r5,%r6 sub,tc,tsv,*<< %r4,%r5,%r6 sub,tc,tsv,*<<= %r4,%r5,%r6 sub,tc,tsv,*sv %r4,%r5,%r6 sub,tc,tsv,*od %r4,%r5,%r6 sub,tsv,tc,*tr %r4,%r5,%r6 sub,tsv,tc,*<> %r4,%r5,%r6 sub,tsv,tc,*>= %r4,%r5,%r6 sub,tsv,tc,*> %r4,%r5,%r6 sub,tsv,tc,*>>= %r4,%r5,%r6 sub,tsv,tc,*>> %r4,%r5,%r6 sub,tsv,tc,*nsv %r4,%r5,%r6 sub,tsv,tc,*ev %r4,%r5,%r6 ;; PR gas/11395: Check for the correct assembly ;; of unconditional 32-bit and 64-bit sub instructions. sub %r1,%r1,%r1 sub,db %r1,%r1,%r1

stsp/binutils-ia16

2,161

gas/testsuite/gas/hppa/basic/imem.s

.code .align 4 .EXPORT integer_memory_tests,CODE .EXPORT integer_indexing_load,CODE .EXPORT integer_load_short_memory,CODE .EXPORT integer_store_short_memory,CODE .EXPORT main,CODE .EXPORT main,ENTRY,PRIV_LEV=3,RTNVAL=GR ; Basic integer memory tests which also test the various ; addressing modes and completers. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. ; integer_memory_tests: ldw 0(%sr0,%r4),%r26 ldh 0(%sr0,%r4),%r26 ldb 0(%sr0,%r4),%r26 stw %r26,0(%sr0,%r4) sth %r26,0(%sr0,%r4) stb %r26,0(%sr0,%r4) ; Should make sure pre/post modes are recognized correctly. ldwm 0(%sr0,%r4),%r26 stwm %r26,0(%sr0,%r4) integer_indexing_load: ldwx %r5(%sr0,%r4),%r26 ldwx,s %r5(%sr0,%r4),%r26 ldwx,m %r5(%sr0,%r4),%r26 ldwx,sm %r5(%sr0,%r4),%r26 ldhx %r5(%sr0,%r4),%r26 ldhx,s %r5(%sr0,%r4),%r26 ldhx,m %r5(%sr0,%r4),%r26 ldhx,sm %r5(%sr0,%r4),%r26 ldbx %r5(%sr0,%r4),%r26 ldbx,s %r5(%sr0,%r4),%r26 ldbx,m %r5(%sr0,%r4),%r26 ldbx,sm %r5(%sr0,%r4),%r26 ldwax %r5(%r4),%r26 ldwax,s %r5(%r4),%r26 ldwax,m %r5(%r4),%r26 ldwax,sm %r5(%r4),%r26 ldcwx %r5(%sr0,%r4),%r26 ldcwx,s %r5(%sr0,%r4),%r26 ldcwx,m %r5(%sr0,%r4),%r26 ldcwx,sm %r5(%sr0,%r4),%r26 integer_load_short_memory: ldws 0(%sr0,%r4),%r26 ldws,mb 0(%sr0,%r4),%r26 ldws,ma 0(%sr0,%r4),%r26 ldhs 0(%sr0,%r4),%r26 ldhs,mb 0(%sr0,%r4),%r26 ldhs,ma 0(%sr0,%r4),%r26 ldbs 0(%sr0,%r4),%r26 ldbs,mb 0(%sr0,%r4),%r26 ldbs,ma 0(%sr0,%r4),%r26 ldwas 0(%r4),%r26 ldwas,mb 0(%r4),%r26 ldwas,ma 0(%r4),%r26 ldcws 0(%sr0,%r4),%r26 ldcws,mb 0(%sr0,%r4),%r26 ldcws,ma 0(%sr0,%r4),%r26 integer_store_short_memory: stws %r26,0(%sr0,%r4) stws,mb %r26,0(%sr0,%r4) stws,ma %r26,0(%sr0,%r4) sths %r26,0(%sr0,%r4) sths,mb %r26,0(%sr0,%r4) sths,ma %r26,0(%sr0,%r4) stbs %r26,0(%sr0,%r4) stbs,mb %r26,0(%sr0,%r4) stbs,ma %r26,0(%sr0,%r4) stwas %r26,0(%r4) stwas,mb %r26,0(%r4) stwas,ma %r26,0(%r4) stbys %r26,0(%sr0,%r4) stbys,b %r26,0(%sr0,%r4) stbys,e %r26,0(%sr0,%r4) stbys,b,m %r26,0(%sr0,%r4) stbys,e,m %r26,0(%sr0,%r4)

stsp/binutils-ia16

1,039

gas/testsuite/gas/hppa/basic/logical.s

.level 1.1 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. or %r4,%r5,%r6 or,= %r4,%r5,%r6 or,< %r4,%r5,%r6 or,<= %r4,%r5,%r6 or,od %r4,%r5,%r6 or,tr %r4,%r5,%r6 or,<> %r4,%r5,%r6 or,>= %r4,%r5,%r6 or,> %r4,%r5,%r6 or,ev %r4,%r5,%r6 xor %r4,%r5,%r6 xor,= %r4,%r5,%r6 xor,< %r4,%r5,%r6 xor,<= %r4,%r5,%r6 xor,od %r4,%r5,%r6 xor,tr %r4,%r5,%r6 xor,<> %r4,%r5,%r6 xor,>= %r4,%r5,%r6 xor,> %r4,%r5,%r6 xor,ev %r4,%r5,%r6 and %r4,%r5,%r6 and,= %r4,%r5,%r6 and,< %r4,%r5,%r6 and,<= %r4,%r5,%r6 and,od %r4,%r5,%r6 and,tr %r4,%r5,%r6 and,<> %r4,%r5,%r6 and,>= %r4,%r5,%r6 and,> %r4,%r5,%r6 and,ev %r4,%r5,%r6 andcm %r4,%r5,%r6 andcm,= %r4,%r5,%r6 andcm,< %r4,%r5,%r6 andcm,<= %r4,%r5,%r6 andcm,od %r4,%r5,%r6 andcm,tr %r4,%r5,%r6 andcm,<> %r4,%r5,%r6 andcm,>= %r4,%r5,%r6 andcm,> %r4,%r5,%r6 andcm,ev %r4,%r5,%r6

stsp/binutils-ia16

4,269

gas/testsuite/gas/hppa/basic/shladd.s

.level 1.1 .code .align 4 ; Basic shladd instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. shladd %r4,1,%r5,%r6 shladd,= %r4,1,%r5,%r6 shladd,< %r4,1,%r5,%r6 shladd,<= %r4,1,%r5,%r6 shladd,nuv %r4,1,%r5,%r6 shladd,znv %r4,1,%r5,%r6 shladd,sv %r4,1,%r5,%r6 shladd,od %r4,1,%r5,%r6 shladd,tr %r4,1,%r5,%r6 shladd,<> %r4,1,%r5,%r6 shladd,>= %r4,1,%r5,%r6 shladd,> %r4,1,%r5,%r6 shladd,uv %r4,1,%r5,%r6 shladd,vnz %r4,1,%r5,%r6 shladd,nsv %r4,1,%r5,%r6 shladd,ev %r4,1,%r5,%r6 shladd,l %r4,1,%r5,%r6 shladd,l,= %r4,1,%r5,%r6 shladd,l,< %r4,1,%r5,%r6 shladd,l,<= %r4,1,%r5,%r6 shladd,l,nuv %r4,1,%r5,%r6 shladd,l,znv %r4,1,%r5,%r6 shladd,l,sv %r4,1,%r5,%r6 shladd,l,od %r4,1,%r5,%r6 shladd,l,tr %r4,1,%r5,%r6 shladd,l,<> %r4,1,%r5,%r6 shladd,l,>= %r4,1,%r5,%r6 shladd,l,> %r4,1,%r5,%r6 shladd,l,uv %r4,1,%r5,%r6 shladd,l,vnz %r4,1,%r5,%r6 shladd,l,nsv %r4,1,%r5,%r6 shladd,l,ev %r4,1,%r5,%r6 shladd,tsv %r4,1,%r5,%r6 shladd,tsv,= %r4,1,%r5,%r6 shladd,tsv,< %r4,1,%r5,%r6 shladd,tsv,<= %r4,1,%r5,%r6 shladd,tsv,nuv %r4,1,%r5,%r6 shladd,tsv,znv %r4,1,%r5,%r6 shladd,tsv,sv %r4,1,%r5,%r6 shladd,tsv,od %r4,1,%r5,%r6 shladd,tsv,tr %r4,1,%r5,%r6 shladd,tsv,<> %r4,1,%r5,%r6 shladd,tsv,>= %r4,1,%r5,%r6 shladd,tsv,> %r4,1,%r5,%r6 shladd,tsv,uv %r4,1,%r5,%r6 shladd,tsv,vnz %r4,1,%r5,%r6 shladd,tsv,nsv %r4,1,%r5,%r6 shladd,tsv,ev %r4,1,%r5,%r6 shladd %r4,2,%r5,%r6 shladd,= %r4,2,%r5,%r6 shladd,< %r4,2,%r5,%r6 shladd,<= %r4,2,%r5,%r6 shladd,nuv %r4,2,%r5,%r6 shladd,znv %r4,2,%r5,%r6 shladd,sv %r4,2,%r5,%r6 shladd,od %r4,2,%r5,%r6 shladd,tr %r4,2,%r5,%r6 shladd,<> %r4,2,%r5,%r6 shladd,>= %r4,2,%r5,%r6 shladd,> %r4,2,%r5,%r6 shladd,uv %r4,2,%r5,%r6 shladd,vnz %r4,2,%r5,%r6 shladd,nsv %r4,2,%r5,%r6 shladd,ev %r4,2,%r5,%r6 shladd,l %r4,2,%r5,%r6 shladd,l,= %r4,2,%r5,%r6 shladd,l,< %r4,2,%r5,%r6 shladd,l,<= %r4,2,%r5,%r6 shladd,l,nuv %r4,2,%r5,%r6 shladd,l,znv %r4,2,%r5,%r6 shladd,l,sv %r4,2,%r5,%r6 shladd,l,od %r4,2,%r5,%r6 shladd,l,tr %r4,2,%r5,%r6 shladd,l,<> %r4,2,%r5,%r6 shladd,l,>= %r4,2,%r5,%r6 shladd,l,> %r4,2,%r5,%r6 shladd,l,uv %r4,2,%r5,%r6 shladd,l,vnz %r4,2,%r5,%r6 shladd,l,nsv %r4,2,%r5,%r6 shladd,l,ev %r4,2,%r5,%r6 shladd,tsv %r4,2,%r5,%r6 shladd,tsv,= %r4,2,%r5,%r6 shladd,tsv,< %r4,2,%r5,%r6 shladd,tsv,<= %r4,2,%r5,%r6 shladd,tsv,nuv %r4,2,%r5,%r6 shladd,tsv,znv %r4,2,%r5,%r6 shladd,tsv,sv %r4,2,%r5,%r6 shladd,tsv,od %r4,2,%r5,%r6 shladd,tsv,tr %r4,2,%r5,%r6 shladd,tsv,<> %r4,2,%r5,%r6 shladd,tsv,>= %r4,2,%r5,%r6 shladd,tsv,> %r4,2,%r5,%r6 shladd,tsv,uv %r4,2,%r5,%r6 shladd,tsv,vnz %r4,2,%r5,%r6 shladd,tsv,nsv %r4,2,%r5,%r6 shladd,tsv,ev %r4,2,%r5,%r6 shladd %r4,3,%r5,%r6 shladd,= %r4,3,%r5,%r6 shladd,< %r4,3,%r5,%r6 shladd,<= %r4,3,%r5,%r6 shladd,nuv %r4,3,%r5,%r6 shladd,znv %r4,3,%r5,%r6 shladd,sv %r4,3,%r5,%r6 shladd,od %r4,3,%r5,%r6 shladd,tr %r4,3,%r5,%r6 shladd,<> %r4,3,%r5,%r6 shladd,>= %r4,3,%r5,%r6 shladd,> %r4,3,%r5,%r6 shladd,uv %r4,3,%r5,%r6 shladd,vnz %r4,3,%r5,%r6 shladd,nsv %r4,3,%r5,%r6 shladd,ev %r4,3,%r5,%r6 shladd,l %r4,3,%r5,%r6 shladd,l,= %r4,3,%r5,%r6 shladd,l,< %r4,3,%r5,%r6 shladd,l,<= %r4,3,%r5,%r6 shladd,l,nuv %r4,3,%r5,%r6 shladd,l,znv %r4,3,%r5,%r6 shladd,l,sv %r4,3,%r5,%r6 shladd,l,od %r4,3,%r5,%r6 shladd,l,tr %r4,3,%r5,%r6 shladd,l,<> %r4,3,%r5,%r6 shladd,l,>= %r4,3,%r5,%r6 shladd,l,> %r4,3,%r5,%r6 shladd,l,uv %r4,3,%r5,%r6 shladd,l,vnz %r4,3,%r5,%r6 shladd,l,nsv %r4,3,%r5,%r6 shladd,l,ev %r4,3,%r5,%r6 shladd,tsv %r4,3,%r5,%r6 shladd,tsv,= %r4,3,%r5,%r6 shladd,tsv,< %r4,3,%r5,%r6 shladd,tsv,<= %r4,3,%r5,%r6 shladd,tsv,nuv %r4,3,%r5,%r6 shladd,tsv,znv %r4,3,%r5,%r6 shladd,tsv,sv %r4,3,%r5,%r6 shladd,tsv,od %r4,3,%r5,%r6 shladd,tsv,tr %r4,3,%r5,%r6 shladd,tsv,<> %r4,3,%r5,%r6 shladd,tsv,>= %r4,3,%r5,%r6 shladd,tsv,> %r4,3,%r5,%r6 shladd,tsv,uv %r4,3,%r5,%r6 shladd,tsv,vnz %r4,3,%r5,%r6 shladd,tsv,nsv %r4,3,%r5,%r6 shladd,tsv,ev %r4,3,%r5,%r6

stsp/binutils-ia16

1,732

gas/testsuite/gas/hppa/basic/deposit2.s

.code .align 4 ; Deposit instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. depw,z %r4,5,10,%r6 depw,z,= %r4,5,10,%r6 depw,z,< %r4,5,10,%r6 depw,z,od %r4,5,10,%r6 depw,z,tr %r4,5,10,%r6 depw,z,<> %r4,5,10,%r6 depw,z,>= %r4,5,10,%r6 depw,z,ev %r4,5,10,%r6 depw %r4,5,10,%r6 depw,= %r4,5,10,%r6 depw,< %r4,5,10,%r6 depw,od %r4,5,10,%r6 depw,tr %r4,5,10,%r6 depw,<> %r4,5,10,%r6 depw,>= %r4,5,10,%r6 depw,ev %r4,5,10,%r6 depw,z %r4,%sar,5,%r6 depw,z,= %r4,%sar,5,%r6 depw,z,< %r4,%sar,5,%r6 depw,z,od %r4,%sar,5,%r6 depw,z,tr %r4,%sar,5,%r6 depw,z,<> %r4,%sar,5,%r6 depw,z,>= %r4,%sar,5,%r6 depw,z,ev %r4,%sar,5,%r6 depw %r4,%sar,5,%r6 depw,= %r4,%sar,5,%r6 depw,< %r4,%sar,5,%r6 depw,od %r4,%sar,5,%r6 depw,tr %r4,%sar,5,%r6 depw,<> %r4,%sar,5,%r6 depw,>= %r4,%sar,5,%r6 depw,ev %r4,%sar,5,%r6 depwi -1,%sar,5,%r6 depwi,= -1,%sar,5,%r6 depwi,< -1,%sar,5,%r6 depwi,od -1,%sar,5,%r6 depwi,tr -1,%sar,5,%r6 depwi,<> -1,%sar,5,%r6 depwi,>= -1,%sar,5,%r6 depwi,ev -1,%sar,5,%r6 depwi,z -1,%sar,5,%r6 depwi,z,= -1,%sar,5,%r6 depwi,z,< -1,%sar,5,%r6 depwi,z,od -1,%sar,5,%r6 depwi,z,tr -1,%sar,5,%r6 depwi,z,<> -1,%sar,5,%r6 depwi,z,>= -1,%sar,5,%r6 depwi,z,ev -1,%sar,5,%r6 depwi -1,4,10,%r6 depwi,= -1,4,10,%r6 depwi,< -1,4,10,%r6 depwi,od -1,4,10,%r6 depwi,tr -1,4,10,%r6 depwi,<> -1,4,10,%r6 depwi,>= -1,4,10,%r6 depwi,ev -1,4,10,%r6 depwi,z -1,4,10,%r6 depwi,z,= -1,4,10,%r6 depwi,z,< -1,4,10,%r6 depwi,z,od -1,4,10,%r6 depwi,z,tr -1,4,10,%r6 depwi,z,<> -1,4,10,%r6 depwi,z,>= -1,4,10,%r6 depwi,z,ev -1,4,10,%r6

stsp/binutils-ia16

2,985

gas/testsuite/gas/hppa/basic/addi.s

.code .align 4 ; Basic add immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. addi 123,%r5,%r6 addi,= 123,%r5,%r6 addi,< 123,%r5,%r6 addi,<= 123,%r5,%r6 addi,nuv 123,%r5,%r6 addi,znv 123,%r5,%r6 addi,sv 123,%r5,%r6 addi,od 123,%r5,%r6 addi,tr 123,%r5,%r6 addi,<> 123,%r5,%r6 addi,>= 123,%r5,%r6 addi,> 123,%r5,%r6 addi,uv 123,%r5,%r6 addi,vnz 123,%r5,%r6 addi,nsv 123,%r5,%r6 addi,ev 123,%r5,%r6 addio 123,%r5,%r6 addio,= 123,%r5,%r6 addio,< 123,%r5,%r6 addio,<= 123,%r5,%r6 addio,nuv 123,%r5,%r6 addio,znv 123,%r5,%r6 addio,sv 123,%r5,%r6 addio,od 123,%r5,%r6 addio,tr 123,%r5,%r6 addio,<> 123,%r5,%r6 addio,>= 123,%r5,%r6 addio,> 123,%r5,%r6 addio,uv 123,%r5,%r6 addio,vnz 123,%r5,%r6 addio,nsv 123,%r5,%r6 addio,ev 123,%r5,%r6 addit 123,%r5,%r6 addit,= 123,%r5,%r6 addit,< 123,%r5,%r6 addit,<= 123,%r5,%r6 addit,nuv 123,%r5,%r6 addit,znv 123,%r5,%r6 addit,sv 123,%r5,%r6 addit,od 123,%r5,%r6 addit,tr 123,%r5,%r6 addit,<> 123,%r5,%r6 addit,>= 123,%r5,%r6 addit,> 123,%r5,%r6 addit,uv 123,%r5,%r6 addit,vnz 123,%r5,%r6 addit,nsv 123,%r5,%r6 addit,ev 123,%r5,%r6 addito 123,%r5,%r6 addito,= 123,%r5,%r6 addito,< 123,%r5,%r6 addito,<= 123,%r5,%r6 addito,nuv 123,%r5,%r6 addito,znv 123,%r5,%r6 addito,sv 123,%r5,%r6 addito,od 123,%r5,%r6 addito,tr 123,%r5,%r6 addito,<> 123,%r5,%r6 addito,>= 123,%r5,%r6 addito,> 123,%r5,%r6 addito,uv 123,%r5,%r6 addito,vnz 123,%r5,%r6 addito,nsv 123,%r5,%r6 addito,ev 123,%r5,%r6 addi,tsv 123,%r5,%r6 addi,tsv,= 123,%r5,%r6 addi,tsv,< 123,%r5,%r6 addi,tsv,<= 123,%r5,%r6 addi,tsv,nuv 123,%r5,%r6 addi,tsv,znv 123,%r5,%r6 addi,tsv,sv 123,%r5,%r6 addi,tsv,od 123,%r5,%r6 addi,tsv,tr 123,%r5,%r6 addi,tsv,<> 123,%r5,%r6 addi,tsv,>= 123,%r5,%r6 addi,tsv,> 123,%r5,%r6 addi,tsv,uv 123,%r5,%r6 addi,tsv,vnz 123,%r5,%r6 addi,tsv,nsv 123,%r5,%r6 addi,tsv,ev 123,%r5,%r6 addi,tc 123,%r5,%r6 addi,tc,= 123,%r5,%r6 addi,tc,< 123,%r5,%r6 addi,tc,<= 123,%r5,%r6 addi,tc,nuv 123,%r5,%r6 addi,tc,znv 123,%r5,%r6 addi,tc,sv 123,%r5,%r6 addi,tc,od 123,%r5,%r6 addi,tc,tr 123,%r5,%r6 addi,tc,<> 123,%r5,%r6 addi,tc,>= 123,%r5,%r6 addi,tc,> 123,%r5,%r6 addi,tc,uv 123,%r5,%r6 addi,tc,vnz 123,%r5,%r6 addi,tc,nsv 123,%r5,%r6 addi,tc,ev 123,%r5,%r6 addi,tc,tsv 123,%r5,%r6 addi,tc,tsv,= 123,%r5,%r6 addi,tc,tsv,< 123,%r5,%r6 addi,tc,tsv,<= 123,%r5,%r6 addi,tc,tsv,nuv 123,%r5,%r6 addi,tc,tsv,znv 123,%r5,%r6 addi,tc,tsv,sv 123,%r5,%r6 addi,tc,tsv,od 123,%r5,%r6 addi,tsv,tc,tr 123,%r5,%r6 addi,tsv,tc,<> 123,%r5,%r6 addi,tsv,tc,>= 123,%r5,%r6 addi,tsv,tc,> 123,%r5,%r6 addi,tsv,tc,uv 123,%r5,%r6 addi,tsv,tc,vnz 123,%r5,%r6 addi,tsv,tc,nsv 123,%r5,%r6 addi,tsv,tc,ev 123,%r5,%r6

stsp/binutils-ia16

2,287

gas/testsuite/gas/hppa/basic/fp_conv.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fcnvff,sgl,sgl %fr5,%fr10 fcnvff,sgl,dbl %fr5,%fr10 fcnvff,sgl,quad %fr5,%fr10 fcnvff,dbl,sgl %fr5,%fr10 fcnvff,dbl,dbl %fr5,%fr10 fcnvff,dbl,quad %fr5,%fr10 fcnvff,quad,sgl %fr5,%fr10 fcnvff,quad,dbl %fr5,%fr10 fcnvff,quad,quad %fr5,%fr10 fcnvff,sgl,sgl %fr20,%fr24 fcnvff,sgl,dbl %fr20,%fr24 fcnvff,sgl,quad %fr20,%fr24 fcnvff,dbl,sgl %fr20,%fr24 fcnvff,dbl,dbl %fr20,%fr24 fcnvff,dbl,quad %fr20,%fr24 fcnvff,quad,sgl %fr20,%fr24 fcnvff,quad,dbl %fr20,%fr24 fcnvff,quad,quad %fr20,%fr24 fcnvxf,sgl,sgl %fr5,%fr10 fcnvxf,sgl,dbl %fr5,%fr10 fcnvxf,sgl,quad %fr5,%fr10 fcnvxf,dbl,sgl %fr5,%fr10 fcnvxf,dbl,dbl %fr5,%fr10 fcnvxf,dbl,quad %fr5,%fr10 fcnvxf,quad,sgl %fr5,%fr10 fcnvxf,quad,dbl %fr5,%fr10 fcnvxf,quad,quad %fr5,%fr10 fcnvxf,sgl,sgl %fr20,%fr24 fcnvxf,sgl,dbl %fr20,%fr24 fcnvxf,sgl,quad %fr20,%fr24 fcnvxf,dbl,sgl %fr20,%fr24 fcnvxf,dbl,dbl %fr20,%fr24 fcnvxf,dbl,quad %fr20,%fr24 fcnvxf,quad,sgl %fr20,%fr24 fcnvxf,quad,dbl %fr20,%fr24 fcnvxf,quad,quad %fr20,%fr24 fcnvfx,sgl,sgl %fr5,%fr10 fcnvfx,sgl,dbl %fr5,%fr10 fcnvfx,sgl,quad %fr5,%fr10 fcnvfx,dbl,sgl %fr5,%fr10 fcnvfx,dbl,dbl %fr5,%fr10 fcnvfx,dbl,quad %fr5,%fr10 fcnvfx,quad,sgl %fr5,%fr10 fcnvfx,quad,dbl %fr5,%fr10 fcnvfx,quad,quad %fr5,%fr10 fcnvfx,sgl,sgl %fr20,%fr24 fcnvfx,sgl,dbl %fr20,%fr24 fcnvfx,sgl,quad %fr20,%fr24 fcnvfx,dbl,sgl %fr20,%fr24 fcnvfx,dbl,dbl %fr20,%fr24 fcnvfx,dbl,quad %fr20,%fr24 fcnvfx,quad,sgl %fr20,%fr24 fcnvfx,quad,dbl %fr20,%fr24 fcnvfx,quad,quad %fr20,%fr24 fcnvfxt,sgl,sgl %fr5,%fr10 fcnvfxt,sgl,dbl %fr5,%fr10 fcnvfxt,sgl,quad %fr5,%fr10 fcnvfxt,dbl,sgl %fr5,%fr10 fcnvfxt,dbl,dbl %fr5,%fr10 fcnvfxt,dbl,quad %fr5,%fr10 fcnvfxt,quad,sgl %fr5,%fr10 fcnvfxt,quad,dbl %fr5,%fr10 fcnvfxt,quad,quad %fr5,%fr10 fcnvfxt,sgl,sgl %fr20,%fr24 fcnvfxt,sgl,dbl %fr20,%fr24 fcnvfxt,sgl,quad %fr20,%fr24 fcnvfxt,dbl,sgl %fr20,%fr24 fcnvfxt,dbl,dbl %fr20,%fr24 fcnvfxt,dbl,quad %fr20,%fr24 fcnvfxt,quad,sgl %fr20,%fr24 fcnvfxt,quad,dbl %fr20,%fr24 fcnvfxt,quad,quad %fr20,%fr24

stsp/binutils-ia16

1,517

gas/testsuite/gas/hppa/basic/deposit.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. zdep %r4,5,10,%r6 zdep,= %r4,5,10,%r6 zdep,< %r4,5,10,%r6 zdep,od %r4,5,10,%r6 zdep,tr %r4,5,10,%r6 zdep,<> %r4,5,10,%r6 zdep,>= %r4,5,10,%r6 zdep,ev %r4,5,10,%r6 dep %r4,5,10,%r6 dep,= %r4,5,10,%r6 dep,< %r4,5,10,%r6 dep,od %r4,5,10,%r6 dep,tr %r4,5,10,%r6 dep,<> %r4,5,10,%r6 dep,>= %r4,5,10,%r6 dep,ev %r4,5,10,%r6 zvdep %r4,5,%r6 zvdep,= %r4,5,%r6 zvdep,< %r4,5,%r6 zvdep,od %r4,5,%r6 zvdep,tr %r4,5,%r6 zvdep,<> %r4,5,%r6 zvdep,>= %r4,5,%r6 zvdep,ev %r4,5,%r6 vdep %r4,5,%r6 vdep,= %r4,5,%r6 vdep,< %r4,5,%r6 vdep,od %r4,5,%r6 vdep,tr %r4,5,%r6 vdep,<> %r4,5,%r6 vdep,>= %r4,5,%r6 vdep,ev %r4,5,%r6 vdepi -1,5,%r6 vdepi,= -1,5,%r6 vdepi,< -1,5,%r6 vdepi,od -1,5,%r6 vdepi,tr -1,5,%r6 vdepi,<> -1,5,%r6 vdepi,>= -1,5,%r6 vdepi,ev -1,5,%r6 zvdepi -1,5,%r6 zvdepi,= -1,5,%r6 zvdepi,< -1,5,%r6 zvdepi,od -1,5,%r6 zvdepi,tr -1,5,%r6 zvdepi,<> -1,5,%r6 zvdepi,>= -1,5,%r6 zvdepi,ev -1,5,%r6 depi -1,4,10,%r6 depi,= -1,4,10,%r6 depi,< -1,4,10,%r6 depi,od -1,4,10,%r6 depi,tr -1,4,10,%r6 depi,<> -1,4,10,%r6 depi,>= -1,4,10,%r6 depi,ev -1,4,10,%r6 zdepi -1,4,10,%r6 zdepi,= -1,4,10,%r6 zdepi,< -1,4,10,%r6 zdepi,od -1,4,10,%r6 zdepi,tr -1,4,10,%r6 zdepi,<> -1,4,10,%r6 zdepi,>= -1,4,10,%r6 zdepi,ev -1,4,10,%r6

stsp/binutils-ia16

1,085

gas/testsuite/gas/hppa/basic/extract3.s

.LEVEL 2.0 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. extrd,u,* %r4,10,5,%r6 extrd,u,*= %r4,10,5,%r6 extrd,u,*< %r4,10,5,%r6 extrd,u,*od %r4,10,5,%r6 extrd,u,*tr %r4,10,5,%r6 extrd,u,*<> %r4,10,5,%r6 extrd,u,*>= %r4,10,5,%r6 extrd,u,*ev %r4,10,5,%r6 extrd,s,* %r4,10,5,%r6 extrd,s,*= %r4,10,5,%r6 extrd,s,*< %r4,10,5,%r6 extrd,s,*od %r4,10,5,%r6 extrd,*tr %r4,10,5,%r6 extrd,*<> %r4,10,5,%r6 extrd,*>= %r4,10,5,%r6 extrd,*ev %r4,10,5,%r6 extrd,u,* %r4,%sar,5,%r6 extrd,u,*= %r4,%sar,5,%r6 extrd,u,*< %r4,%sar,5,%r6 extrd,u,*od %r4,%sar,5,%r6 extrd,u,*tr %r4,%sar,5,%r6 extrd,u,*<> %r4,%sar,5,%r6 extrd,u,*>= %r4,%sar,5,%r6 extrd,u,*ev %r4,%sar,5,%r6 extrd,s,* %r4,%sar,5,%r6 extrd,s,*= %r4,%sar,5,%r6 extrd,s,*< %r4,%sar,5,%r6 extrd,s,*od %r4,%sar,5,%r6 extrd,*tr %r4,%sar,5,%r6 extrd,*<> %r4,%sar,5,%r6 extrd,*>= %r4,%sar,5,%r6 extrd,*ev %r4,%sar,5,%r6

stsp/binutils-ia16

3,568

gas/testsuite/gas/hppa/basic/add.s

.level 1.1 .code .align 4 ; Basic add/sh?add instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. add %r4,%r5,%r6 add,= %r4,%r5,%r6 add,< %r4,%r5,%r6 add,<= %r4,%r5,%r6 add,nuv %r4,%r5,%r6 add,znv %r4,%r5,%r6 add,sv %r4,%r5,%r6 add,od %r4,%r5,%r6 add,tr %r4,%r5,%r6 add,<> %r4,%r5,%r6 add,>= %r4,%r5,%r6 add,> %r4,%r5,%r6 add,uv %r4,%r5,%r6 add,vnz %r4,%r5,%r6 add,nsv %r4,%r5,%r6 add,ev %r4,%r5,%r6 addl %r4,%r5,%r6 addl,= %r4,%r5,%r6 addl,< %r4,%r5,%r6 addl,<= %r4,%r5,%r6 addl,nuv %r4,%r5,%r6 addl,znv %r4,%r5,%r6 addl,sv %r4,%r5,%r6 addl,od %r4,%r5,%r6 addl,tr %r4,%r5,%r6 addl,<> %r4,%r5,%r6 addl,>= %r4,%r5,%r6 addl,> %r4,%r5,%r6 addl,uv %r4,%r5,%r6 addl,vnz %r4,%r5,%r6 addl,nsv %r4,%r5,%r6 addl,ev %r4,%r5,%r6 addo %r4,%r5,%r6 addo,= %r4,%r5,%r6 addo,< %r4,%r5,%r6 addo,<= %r4,%r5,%r6 addo,nuv %r4,%r5,%r6 addo,znv %r4,%r5,%r6 addo,sv %r4,%r5,%r6 addo,od %r4,%r5,%r6 addo,tr %r4,%r5,%r6 addo,<> %r4,%r5,%r6 addo,>= %r4,%r5,%r6 addo,> %r4,%r5,%r6 addo,uv %r4,%r5,%r6 addo,vnz %r4,%r5,%r6 addo,nsv %r4,%r5,%r6 addo,ev %r4,%r5,%r6 addc %r4,%r5,%r6 addc,= %r4,%r5,%r6 addc,< %r4,%r5,%r6 addc,<= %r4,%r5,%r6 addc,nuv %r4,%r5,%r6 addc,znv %r4,%r5,%r6 addc,sv %r4,%r5,%r6 addc,od %r4,%r5,%r6 addc,tr %r4,%r5,%r6 addc,<> %r4,%r5,%r6 addc,>= %r4,%r5,%r6 addc,> %r4,%r5,%r6 addc,uv %r4,%r5,%r6 addc,vnz %r4,%r5,%r6 addc,nsv %r4,%r5,%r6 addc,ev %r4,%r5,%r6 addco %r4,%r5,%r6 addco,= %r4,%r5,%r6 addco,< %r4,%r5,%r6 addco,<= %r4,%r5,%r6 addco,nuv %r4,%r5,%r6 addco,znv %r4,%r5,%r6 addco,sv %r4,%r5,%r6 addco,od %r4,%r5,%r6 addco,tr %r4,%r5,%r6 addco,<> %r4,%r5,%r6 addco,>= %r4,%r5,%r6 addco,> %r4,%r5,%r6 addco,uv %r4,%r5,%r6 addco,vnz %r4,%r5,%r6 addco,nsv %r4,%r5,%r6 addco,ev %r4,%r5,%r6 add,l %r4,%r5,%r6 add,l,= %r4,%r5,%r6 add,l,< %r4,%r5,%r6 add,l,<= %r4,%r5,%r6 add,l,nuv %r4,%r5,%r6 add,l,znv %r4,%r5,%r6 add,l,sv %r4,%r5,%r6 add,l,od %r4,%r5,%r6 add,l,tr %r4,%r5,%r6 add,l,<> %r4,%r5,%r6 add,l,>= %r4,%r5,%r6 add,l,> %r4,%r5,%r6 add,l,uv %r4,%r5,%r6 add,l,vnz %r4,%r5,%r6 add,l,nsv %r4,%r5,%r6 add,l,ev %r4,%r5,%r6 add,tsv %r4,%r5,%r6 add,tsv,= %r4,%r5,%r6 add,tsv,< %r4,%r5,%r6 add,tsv,<= %r4,%r5,%r6 add,tsv,nuv %r4,%r5,%r6 add,tsv,znv %r4,%r5,%r6 add,tsv,sv %r4,%r5,%r6 add,tsv,od %r4,%r5,%r6 add,tsv,tr %r4,%r5,%r6 add,tsv,<> %r4,%r5,%r6 add,tsv,>= %r4,%r5,%r6 add,tsv,> %r4,%r5,%r6 add,tsv,uv %r4,%r5,%r6 add,tsv,vnz %r4,%r5,%r6 add,tsv,nsv %r4,%r5,%r6 add,tsv,ev %r4,%r5,%r6 add,c %r4,%r5,%r6 add,c,= %r4,%r5,%r6 add,c,< %r4,%r5,%r6 add,c,<= %r4,%r5,%r6 add,c,nuv %r4,%r5,%r6 add,c,znv %r4,%r5,%r6 add,c,sv %r4,%r5,%r6 add,c,od %r4,%r5,%r6 add,c,tr %r4,%r5,%r6 add,c,<> %r4,%r5,%r6 add,c,>= %r4,%r5,%r6 add,c,> %r4,%r5,%r6 add,c,uv %r4,%r5,%r6 add,c,vnz %r4,%r5,%r6 add,c,nsv %r4,%r5,%r6 add,c,ev %r4,%r5,%r6 add,c,tsv %r4,%r5,%r6 add,c,tsv,= %r4,%r5,%r6 add,c,tsv,< %r4,%r5,%r6 add,c,tsv,<= %r4,%r5,%r6 add,c,tsv,nuv %r4,%r5,%r6 add,c,tsv,znv %r4,%r5,%r6 add,c,tsv,sv %r4,%r5,%r6 add,c,tsv,od %r4,%r5,%r6 add,tsv,c,tr %r4,%r5,%r6 add,tsv,c,<> %r4,%r5,%r6 add,tsv,c,>= %r4,%r5,%r6 add,tsv,c,> %r4,%r5,%r6 add,tsv,c,uv %r4,%r5,%r6 add,tsv,c,vnz %r4,%r5,%r6 add,tsv,c,nsv %r4,%r5,%r6 add,tsv,c,ev %r4,%r5,%r6

stsp/binutils-ia16

1,037

gas/testsuite/gas/hppa/basic/extract2.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. extrw,u %r4,5,10,%r6 extrw,u,= %r4,5,10,%r6 extrw,u,< %r4,5,10,%r6 extrw,u,od %r4,5,10,%r6 extrw,u,tr %r4,5,10,%r6 extrw,u,<> %r4,5,10,%r6 extrw,u,>= %r4,5,10,%r6 extrw,u,ev %r4,5,10,%r6 extrw,s %r4,5,10,%r6 extrw,s,= %r4,5,10,%r6 extrw,s,< %r4,5,10,%r6 extrw,s,od %r4,5,10,%r6 extrw,tr %r4,5,10,%r6 extrw,<> %r4,5,10,%r6 extrw,>= %r4,5,10,%r6 extrw,ev %r4,5,10,%r6 extrw,u %r4,%sar,5,%r6 extrw,u,= %r4,%sar,5,%r6 extrw,u,< %r4,%sar,5,%r6 extrw,u,od %r4,%sar,5,%r6 extrw,u,tr %r4,%sar,5,%r6 extrw,u,<> %r4,%sar,5,%r6 extrw,u,>= %r4,%sar,5,%r6 extrw,u,ev %r4,%sar,5,%r6 extrw,s %r4,%sar,5,%r6 extrw,s,= %r4,%sar,5,%r6 extrw,s,< %r4,%sar,5,%r6 extrw,s,od %r4,%sar,5,%r6 extrw,tr %r4,%sar,5,%r6 extrw,<> %r4,%sar,5,%r6 extrw,>= %r4,%sar,5,%r6 extrw,ev %r4,%sar,5,%r6

stsp/binutils-ia16

1,823

gas/testsuite/gas/hppa/basic/deposit3.s

.LEVEL 2.0 .code .align 4 ; PA 2.0 Deposit instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. depd,z,* %r4,10,5,%r6 depd,z,*= %r4,10,5,%r6 depd,z,*< %r4,10,5,%r6 depd,z,*od %r4,10,5,%r6 depd,z,*tr %r4,10,5,%r6 depd,z,*<> %r4,10,5,%r6 depd,z,*>= %r4,10,5,%r6 depd,z,*ev %r4,10,5,%r6 depd,* %r4,10,5,%r6 depd,*= %r4,10,5,%r6 depd,*< %r4,10,5,%r6 depd,*od %r4,10,5,%r6 depd,*tr %r4,10,5,%r6 depd,*<> %r4,10,5,%r6 depd,*>= %r4,10,5,%r6 depd,*ev %r4,10,5,%r6 depd,z,* %r4,%sar,5,%r6 depd,z,*= %r4,%sar,5,%r6 depd,z,*< %r4,%sar,5,%r6 depd,z,*od %r4,%sar,5,%r6 depd,z,*tr %r4,%sar,5,%r6 depd,z,*<> %r4,%sar,5,%r6 depd,z,*>= %r4,%sar,5,%r6 depd,z,*ev %r4,%sar,5,%r6 depd,* %r4,%sar,5,%r6 depd,*= %r4,%sar,5,%r6 depd,*< %r4,%sar,5,%r6 depd,*od %r4,%sar,5,%r6 depd,*tr %r4,%sar,5,%r6 depd,*<> %r4,%sar,5,%r6 depd,*>= %r4,%sar,5,%r6 depd,*ev %r4,%sar,5,%r6 depdi,* -1,%sar,5,%r6 depdi,*= -1,%sar,5,%r6 depdi,*< -1,%sar,5,%r6 depdi,*od -1,%sar,5,%r6 depdi,*tr -1,%sar,5,%r6 depdi,*<> -1,%sar,5,%r6 depdi,*>= -1,%sar,5,%r6 depdi,*ev -1,%sar,5,%r6 depdi,z,* -1,%sar,5,%r6 depdi,z,*= -1,%sar,5,%r6 depdi,z,*< -1,%sar,5,%r6 depdi,z,*od -1,%sar,5,%r6 depdi,z,*tr -1,%sar,5,%r6 depdi,z,*<> -1,%sar,5,%r6 depdi,z,*>= -1,%sar,5,%r6 depdi,z,*ev -1,%sar,5,%r6 depdi,* -1,10,4,%r6 depdi,*= -1,10,4,%r6 depdi,*< -1,10,4,%r6 depdi,*od -1,10,4,%r6 depdi,*tr -1,10,4,%r6 depdi,*<> -1,10,4,%r6 depdi,*>= -1,10,4,%r6 depdi,*ev -1,10,4,%r6 depdi,z,* -1,10,4,%r6 depdi,z,*= -1,10,4,%r6 depdi,z,*< -1,10,4,%r6 depdi,z,*od -1,10,4,%r6 depdi,z,*tr -1,10,4,%r6 depdi,z,*<> -1,10,4,%r6 depdi,z,*>= -1,10,4,%r6 depdi,z,*ev -1,10,4,%r6

stsp/binutils-ia16

2,551

gas/testsuite/gas/hppa/basic/fp_fcmp.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. fcmp,sgl,false? %fr4,%fr5 fcmp,sgl,false %fr4,%fr5 fcmp,sgl,? %fr4,%fr5 fcmp,sgl,!<=> %fr4,%fr5 fcmp,sgl,= %fr4,%fr5 fcmp,sgl,=T %fr4,%fr5 fcmp,sgl,?= %fr4,%fr5 fcmp,sgl,!<> %fr4,%fr5 fcmp,sgl,!?>= %fr4,%fr5 fcmp,sgl,< %fr4,%fr5 fcmp,sgl,?< %fr4,%fr5 fcmp,sgl,!>= %fr4,%fr5 fcmp,sgl,!?> %fr4,%fr5 fcmp,sgl,<= %fr4,%fr5 fcmp,sgl,?<= %fr4,%fr5 fcmp,sgl,!> %fr4,%fr5 fcmp,sgl,!?<= %fr4,%fr5 fcmp,sgl,> %fr4,%fr5 fcmp,sgl,?> %fr4,%fr5 fcmp,sgl,!<= %fr4,%fr5 fcmp,sgl,!?< %fr4,%fr5 fcmp,sgl,>= %fr4,%fr5 fcmp,sgl,?>= %fr4,%fr5 fcmp,sgl,!< %fr4,%fr5 fcmp,sgl,!?= %fr4,%fr5 fcmp,sgl,<> %fr4,%fr5 fcmp,sgl,!= %fr4,%fr5 fcmp,sgl,!=T %fr4,%fr5 fcmp,sgl,!? %fr4,%fr5 fcmp,sgl,<=> %fr4,%fr5 fcmp,sgl,true? %fr4,%fr5 fcmp,sgl,true %fr4,%fr5 fcmp,dbl,false? %fr4,%fr5 fcmp,dbl,false %fr4,%fr5 fcmp,dbl,? %fr4,%fr5 fcmp,dbl,!<=> %fr4,%fr5 fcmp,dbl,= %fr4,%fr5 fcmp,dbl,=T %fr4,%fr5 fcmp,dbl,?= %fr4,%fr5 fcmp,dbl,!<> %fr4,%fr5 fcmp,dbl,!?>= %fr4,%fr5 fcmp,dbl,< %fr4,%fr5 fcmp,dbl,?< %fr4,%fr5 fcmp,dbl,!>= %fr4,%fr5 fcmp,dbl,!?> %fr4,%fr5 fcmp,dbl,<= %fr4,%fr5 fcmp,dbl,?<= %fr4,%fr5 fcmp,dbl,!> %fr4,%fr5 fcmp,dbl,!?<= %fr4,%fr5 fcmp,dbl,> %fr4,%fr5 fcmp,dbl,?> %fr4,%fr5 fcmp,dbl,!<= %fr4,%fr5 fcmp,dbl,!?< %fr4,%fr5 fcmp,dbl,>= %fr4,%fr5 fcmp,dbl,?>= %fr4,%fr5 fcmp,dbl,!< %fr4,%fr5 fcmp,dbl,!?= %fr4,%fr5 fcmp,dbl,<> %fr4,%fr5 fcmp,dbl,!= %fr4,%fr5 fcmp,dbl,!=T %fr4,%fr5 fcmp,dbl,!? %fr4,%fr5 fcmp,dbl,<=> %fr4,%fr5 fcmp,dbl,true? %fr4,%fr5 fcmp,dbl,true %fr4,%fr5 fcmp,quad,false? %fr4,%fr5 fcmp,quad,false %fr4,%fr5 fcmp,quad,? %fr4,%fr5 fcmp,quad,!<=> %fr4,%fr5 fcmp,quad,= %fr4,%fr5 fcmp,quad,=T %fr4,%fr5 fcmp,quad,?= %fr4,%fr5 fcmp,quad,!<> %fr4,%fr5 fcmp,quad,!?>= %fr4,%fr5 fcmp,quad,< %fr4,%fr5 fcmp,quad,?< %fr4,%fr5 fcmp,quad,!>= %fr4,%fr5 fcmp,quad,!?> %fr4,%fr5 fcmp,quad,<= %fr4,%fr5 fcmp,quad,?<= %fr4,%fr5 fcmp,quad,!> %fr4,%fr5 fcmp,quad,!?<= %fr4,%fr5 fcmp,quad,> %fr4,%fr5 fcmp,quad,?> %fr4,%fr5 fcmp,quad,!<= %fr4,%fr5 fcmp,quad,!?< %fr4,%fr5 fcmp,quad,>= %fr4,%fr5 fcmp,quad,?>= %fr4,%fr5 fcmp,quad,!< %fr4,%fr5 fcmp,quad,!?= %fr4,%fr5 fcmp,quad,<> %fr4,%fr5 fcmp,quad,!= %fr4,%fr5 fcmp,quad,!=T %fr4,%fr5 fcmp,quad,!? %fr4,%fr5 fcmp,quad,<=> %fr4,%fr5 fcmp,quad,true? %fr4,%fr5 fcmp,quad,true %fr4,%fr5

stsp/binutils-ia16

5,704

gas/testsuite/gas/hppa/basic/branch.s

.level 1.1 .code .align 4 ; More branching instructions than you ever knew what to do with. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. branch_tests: bl branch_tests,%r2 bl,n branch_tests,%r2 b branch_tests b,n branch_tests gate branch_tests,%r2 gate,n branch_tests,%r2 blr %r4,%r2 blr,n %r4,%r2 blr %r4,%r0 blr,n %r4,%r0 bv %r0(%r2) bv,n %r0(%r2) be 0x1234(%sr1,%r2) be,n 0x1234(%sr1,%r2) ble 0x1234(%sr1,%r2) ble,n 0x1234(%sr1,%r2) movb_tests: movb %r4,%r26,movb_tests movb,= %r4,%r26,movb_tests movb,< %r4,%r26,movb_tests movb,od %r4,%r26,movb_tests movb,tr %r4,%r26,movb_tests movb,<> %r4,%r26,movb_tests movb,>= %r4,%r26,movb_tests movb,ev %r4,%r26,movb_tests movb_nullified_tests: movb,n %r4,%r26,movb_tests movb,=,n %r4,%r26,movb_tests movb,<,n %r4,%r26,movb_tests movb,od,n %r4,%r26,movb_tests movb,tr,n %r4,%r26,movb_tests movb,<>,n %r4,%r26,movb_tests movb,>=,n %r4,%r26,movb_tests movb,ev,n %r4,%r26,movb_tests movib_tests: movib 5,%r26,movib_tests movib,= 5,%r26,movib_tests movib,< 5,%r26,movib_tests movib,od 5,%r26,movib_tests movib,tr 5,%r26,movib_tests movib,<> 5,%r26,movib_tests movib,>= 5,%r26,movib_tests movib,ev 5,%r26,movib_tests movib_nullified_tests: movib,n 5,%r26,movib_tests movib,=,n 5,%r26,movib_tests movib,<,n 5,%r26,movib_tests movib,od,n 5,%r26,movib_tests movib,tr,n 5,%r26,movib_tests movib,<>,n 5,%r26,movib_tests movib,>=,n 5,%r26,movib_tests movib,ev,n 5,%r26,movib_tests comb_tests: comb %r0,%r4,comb_tests comb,= %r0,%r4,comb_tests comb,< %r0,%r4,comb_tests comb,<= %r0,%r4,comb_tests comb,<< %r0,%r4,comb_tests comb,<<= %r0,%r4,comb_tests comb,sv %r0,%r4,comb_tests comb,od %r0,%r4,comb_tests comb,tr %r0,%r4,comb_tests comb,<> %r0,%r4,comb_tests comb,>= %r0,%r4,comb_tests comb,> %r0,%r4,comb_tests comb,>>= %r0,%r4,comb_tests comb,>> %r0,%r4,comb_tests comb,nsv %r0,%r4,comb_tests comb,ev %r0,%r4,comb_tests comb_nullified_tests: comb,n %r0,%r4,comb_tests comb,=,n %r0,%r4,comb_tests comb,<,n %r0,%r4,comb_tests comb,<=,n %r0,%r4,comb_tests comb,<<,n %r0,%r4,comb_tests comb,<<=,n %r0,%r4,comb_tests comb,sv,n %r0,%r4,comb_tests comb,od,n %r0,%r4,comb_tests comb,tr,n %r0,%r4,comb_tests comb,<>,n %r0,%r4,comb_tests comb,>=,n %r0,%r4,comb_tests comb,>,n %r0,%r4,comb_tests comb,>>=,n %r0,%r4,comb_tests comb,>>,n %r0,%r4,comb_tests comb,nsv,n %r0,%r4,comb_tests comb,ev,n %r0,%r4,comb_tests comib_tests: comib 0,%r4,comib_tests comib,< 0,%r4,comib_tests comib,<= 0,%r4,comib_tests comib,<< 0,%r4,comib_tests comib,<<= 0,%r4,comib_tests comib,sv 0,%r4,comib_tests comib,od 0,%r4,comib_tests comib,tr 0,%r4,comib_tests comib,<> 0,%r4,comib_tests comib,>= 0,%r4,comib_tests comib,> 0,%r4,comib_tests comib,>>= 0,%r4,comib_tests comib,>> 0,%r4,comib_tests comib,nsv 0,%r4,comib_tests comib,ev 0,%r4,comb_tests comib_nullified_tests: comib,n 0,%r4,comib_tests comib,=,n 0,%r4,comib_tests comib,<,n 0,%r4,comib_tests comib,<=,n 0,%r4,comib_tests comib,<<,n 0,%r4,comib_tests comib,<<=,n 0,%r4,comib_tests comib,sv,n 0,%r4,comib_tests comib,od,n 0,%r4,comib_tests comib,tr,n 0,%r4,comib_tests comib,<>,n 0,%r4,comib_tests comib,>=,n 0,%r4,comib_tests comib,>,n 0,%r4,comib_tests comib,>>=,n 0,%r4,comib_tests comib,>>,n 0,%r4,comib_tests comib,nsv,n 0,%r4,comib_tests comib,ev,n 0,%r4,comib_tests addb_tests: addb %r1,%r4,addb_tests addb,= %r1,%r4,addb_tests addb,< %r1,%r4,addb_tests addb,<= %r1,%r4,addb_tests addb,nuv %r1,%r4,addb_tests addb,znv %r1,%r4,addb_tests addb,sv %r1,%r4,addb_tests addb,od %r1,%r4,addb_tests addb,tr %r1,%r4,addb_tests addb,<> %r1,%r4,addb_tests addb,>= %r1,%r4,addb_tests addb,> %r1,%r4,addb_tests addb,uv %r1,%r4,addb_tests addb,vnz %r1,%r4,addb_tests addb,nsv %r1,%r4,addb_tests addb,ev %r1,%r4,addb_tests addb_nullified_tests: addb,n %r1,%r4,addb_tests addb,=,n %r1,%r4,addb_tests addb,<,n %r1,%r4,addb_tests addb,<=,n %r1,%r4,addb_tests addb,nuv,n %r1,%r4,addb_tests addb,znv,n %r1,%r4,addb_tests addb,sv,n %r1,%r4,addb_tests addb,od,n %r1,%r4,addb_tests addb,tr,n %r1,%r4,addb_tests addb,<>,n %r1,%r4,addb_tests addb,>=,n %r1,%r4,addb_tests addb,>,n %r1,%r4,addb_tests addb,uv,n %r1,%r4,addb_tests addb,vnz,n %r1,%r4,addb_tests addb,nsv,n %r1,%r4,addb_tests addb,ev,n %r1,%r4,addb_tests addib_tests: addib -1,%r4,addib_tests addib,= -1,%r4,addib_tests addib,< -1,%r4,addib_tests addib,<= -1,%r4,addib_tests addib,nuv -1,%r4,addib_tests addib,znv -1,%r4,addib_tests addib,sv -1,%r4,addib_tests addib,od -1,%r4,addib_tests addib,tr -1,%r4,addib_tests addib,<> -1,%r4,addib_tests addib,>= -1,%r4,addib_tests addib,> -1,%r4,addib_tests addib,uv -1,%r4,addib_tests addib,vnz -1,%r4,addib_tests addib,nsv -1,%r4,addib_tests addib,ev -1,%r4,comb_tests addib_nullified_tests: addib,n -1,%r4,addib_tests addib,=,n -1,%r4,addib_tests addib,<,n -1,%r4,addib_tests addib,<=,n -1,%r4,addib_tests addib,nuv,n -1,%r4,addib_tests addib,znv,n -1,%r4,addib_tests addib,sv,n -1,%r4,addib_tests addib,od,n -1,%r4,addib_tests addib,tr,n -1,%r4,addib_tests addib,<>,n -1,%r4,addib_tests addib,>=,n -1,%r4,addib_tests addib,>,n -1,%r4,addib_tests addib,uv,n -1,%r4,addib_tests addib,vnz,n -1,%r4,addib_tests addib,nsv,n -1,%r4,addib_tests addib,ev,n -1,%r4,addib_tests ; Needs to check lots of stuff (like corner bit cases) bb_tests: bvb,< %r4,bb_tests bvb,>= %r4,bb_tests bvb,<,n %r4,bb_tests bvb,>=,n %r4,bb_tests bb,< %r4,5,bb_tests bb,>= %r4,5,bb_tests bb,<,n %r4,5,bb_tests bb,>=,n %r4,5,bb_tests

stsp/binutils-ia16

2,409

gas/testsuite/gas/hppa/basic/add2.s

.LEVEL 2.0 .code .align 4 ; Basic add/sh?add instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. add,* %r4,%r5,%r6 add,*= %r4,%r5,%r6 add,*< %r4,%r5,%r6 add,*<= %r4,%r5,%r6 add,*nuv %r4,%r5,%r6 add,*znv %r4,%r5,%r6 add,*sv %r4,%r5,%r6 add,*od %r4,%r5,%r6 add,*tr %r4,%r5,%r6 add,*<> %r4,%r5,%r6 add,*>= %r4,%r5,%r6 add,*> %r4,%r5,%r6 add,*uv %r4,%r5,%r6 add,*vnz %r4,%r5,%r6 add,*nsv %r4,%r5,%r6 add,*ev %r4,%r5,%r6 add,l,* %r4,%r5,%r6 add,l,*= %r4,%r5,%r6 add,l,*< %r4,%r5,%r6 add,l,*<= %r4,%r5,%r6 add,l,*nuv %r4,%r5,%r6 add,l,*znv %r4,%r5,%r6 add,l,*sv %r4,%r5,%r6 add,l,*od %r4,%r5,%r6 add,l,*tr %r4,%r5,%r6 add,l,*<> %r4,%r5,%r6 add,l,*>= %r4,%r5,%r6 add,l,*> %r4,%r5,%r6 add,l,*uv %r4,%r5,%r6 add,l,*vnz %r4,%r5,%r6 add,l,*nsv %r4,%r5,%r6 add,l,*ev %r4,%r5,%r6 add,tsv,* %r4,%r5,%r6 add,tsv,*= %r4,%r5,%r6 add,tsv,*< %r4,%r5,%r6 add,tsv,*<= %r4,%r5,%r6 add,tsv,*nuv %r4,%r5,%r6 add,tsv,*znv %r4,%r5,%r6 add,tsv,*sv %r4,%r5,%r6 add,tsv,*od %r4,%r5,%r6 add,tsv,*tr %r4,%r5,%r6 add,tsv,*<> %r4,%r5,%r6 add,tsv,*>= %r4,%r5,%r6 add,tsv,*> %r4,%r5,%r6 add,tsv,*uv %r4,%r5,%r6 add,tsv,*vnz %r4,%r5,%r6 add,tsv,*nsv %r4,%r5,%r6 add,tsv,*ev %r4,%r5,%r6 add,dc,* %r4,%r5,%r6 add,dc,*= %r4,%r5,%r6 add,dc,*< %r4,%r5,%r6 add,dc,*<= %r4,%r5,%r6 add,dc,*nuv %r4,%r5,%r6 add,dc,*znv %r4,%r5,%r6 add,dc,*sv %r4,%r5,%r6 add,dc,*od %r4,%r5,%r6 add,dc,*tr %r4,%r5,%r6 add,dc,*<> %r4,%r5,%r6 add,dc,*>= %r4,%r5,%r6 add,dc,*> %r4,%r5,%r6 add,dc,*uv %r4,%r5,%r6 add,dc,*vnz %r4,%r5,%r6 add,dc,*nsv %r4,%r5,%r6 add,dc,*ev %r4,%r5,%r6 add,dc,tsv,* %r4,%r5,%r6 add,dc,tsv,*= %r4,%r5,%r6 add,dc,tsv,*< %r4,%r5,%r6 add,dc,tsv,*<= %r4,%r5,%r6 add,dc,tsv,*nuv %r4,%r5,%r6 add,dc,tsv,*znv %r4,%r5,%r6 add,dc,tsv,*sv %r4,%r5,%r6 add,dc,tsv,*od %r4,%r5,%r6 add,tsv,dc,*tr %r4,%r5,%r6 add,tsv,dc,*<> %r4,%r5,%r6 add,tsv,dc,*>= %r4,%r5,%r6 add,tsv,dc,*> %r4,%r5,%r6 add,tsv,dc,*uv %r4,%r5,%r6 add,tsv,dc,*vnz %r4,%r5,%r6 add,tsv,dc,*nsv %r4,%r5,%r6 add,tsv,dc,*ev %r4,%r5,%r6 ;; PR gas/11395: Check for the correct assembly ;; of unconditional 32-bit and 64-bit add instructions. add %r1,%r1,%r1 add,dc %r1,%r1,%r1

stsp/binutils-ia16

1,272

gas/testsuite/gas/hppa/basic/unit.s

.level 1.1 .code .align 4 ; Basic unit instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. uxor %r4,%r5,%r6 uxor,sbz %r4,%r5,%r6 uxor,shz %r4,%r5,%r6 uxor,tr %r4,%r5,%r6 uxor,nbz %r4,%r5,%r6 uxor,nhz %r4,%r5,%r6 uaddcm %r4,%r5,%r6 uaddcm,sbz %r4,%r5,%r6 uaddcm,shz %r4,%r5,%r6 uaddcm,sdc %r4,%r5,%r6 uaddcm,sbc %r4,%r5,%r6 uaddcm,shc %r4,%r5,%r6 uaddcm,tr %r4,%r5,%r6 uaddcm,nbz %r4,%r5,%r6 uaddcm,nhz %r4,%r5,%r6 uaddcm,ndc %r4,%r5,%r6 uaddcm,nbc %r4,%r5,%r6 uaddcm,nhc %r4,%r5,%r6 uaddcmt %r4,%r5,%r6 uaddcmt,sbz %r4,%r5,%r6 uaddcmt,shz %r4,%r5,%r6 uaddcmt,sdc %r4,%r5,%r6 uaddcmt,sbc %r4,%r5,%r6 uaddcmt,shc %r4,%r5,%r6 uaddcmt,tr %r4,%r5,%r6 uaddcmt,nbz %r4,%r5,%r6 uaddcmt,nhz %r4,%r5,%r6 uaddcmt,ndc %r4,%r5,%r6 uaddcmt,nbc %r4,%r5,%r6 uaddcmt,nhc %r4,%r5,%r6 uaddcm,tc %r4,%r5,%r6 uaddcm,tc,sbz %r4,%r5,%r6 uaddcm,tc,shz %r4,%r5,%r6 uaddcm,tc,sdc %r4,%r5,%r6 uaddcm,tc,sbc %r4,%r5,%r6 uaddcm,tc,shc %r4,%r5,%r6 uaddcm,tc,tr %r4,%r5,%r6 uaddcm,tc,nbz %r4,%r5,%r6 uaddcm,tc,nhz %r4,%r5,%r6 uaddcm,tc,ndc %r4,%r5,%r6 uaddcm,tc,nbc %r4,%r5,%r6 uaddcm,tc,nhc %r4,%r5,%r6

stsp/binutils-ia16

1,418

gas/testsuite/gas/hppa/basic/sh1add.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sh1add %r4,%r5,%r6 sh1add,= %r4,%r5,%r6 sh1add,< %r4,%r5,%r6 sh1add,<= %r4,%r5,%r6 sh1add,nuv %r4,%r5,%r6 sh1add,znv %r4,%r5,%r6 sh1add,sv %r4,%r5,%r6 sh1add,od %r4,%r5,%r6 sh1add,tr %r4,%r5,%r6 sh1add,<> %r4,%r5,%r6 sh1add,>= %r4,%r5,%r6 sh1add,> %r4,%r5,%r6 sh1add,uv %r4,%r5,%r6 sh1add,vnz %r4,%r5,%r6 sh1add,nsv %r4,%r5,%r6 sh1add,ev %r4,%r5,%r6 sh1addl %r4,%r5,%r6 sh1addl,= %r4,%r5,%r6 sh1addl,< %r4,%r5,%r6 sh1addl,<= %r4,%r5,%r6 sh1addl,nuv %r4,%r5,%r6 sh1addl,znv %r4,%r5,%r6 sh1addl,sv %r4,%r5,%r6 sh1addl,od %r4,%r5,%r6 sh1addl,tr %r4,%r5,%r6 sh1addl,<> %r4,%r5,%r6 sh1addl,>= %r4,%r5,%r6 sh1addl,> %r4,%r5,%r6 sh1addl,uv %r4,%r5,%r6 sh1addl,vnz %r4,%r5,%r6 sh1addl,nsv %r4,%r5,%r6 sh1addl,ev %r4,%r5,%r6 sh1addo %r4,%r5,%r6 sh1addo,= %r4,%r5,%r6 sh1addo,< %r4,%r5,%r6 sh1addo,<= %r4,%r5,%r6 sh1addo,nuv %r4,%r5,%r6 sh1addo,znv %r4,%r5,%r6 sh1addo,sv %r4,%r5,%r6 sh1addo,od %r4,%r5,%r6 sh1addo,tr %r4,%r5,%r6 sh1addo,<> %r4,%r5,%r6 sh1addo,>= %r4,%r5,%r6 sh1addo,> %r4,%r5,%r6 sh1addo,uv %r4,%r5,%r6 sh1addo,vnz %r4,%r5,%r6 sh1addo,nsv %r4,%r5,%r6 sh1addo,ev %r4,%r5,%r6

stsp/binutils-ia16

4,210

gas/testsuite/gas/hppa/basic/sub.s

.level 1.1 .code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sub %r4,%r5,%r6 sub,= %r4,%r5,%r6 sub,< %r4,%r5,%r6 sub,<= %r4,%r5,%r6 sub,<< %r4,%r5,%r6 sub,<<= %r4,%r5,%r6 sub,sv %r4,%r5,%r6 sub,od %r4,%r5,%r6 sub,tr %r4,%r5,%r6 sub,<> %r4,%r5,%r6 sub,>= %r4,%r5,%r6 sub,> %r4,%r5,%r6 sub,>>= %r4,%r5,%r6 sub,>> %r4,%r5,%r6 sub,nsv %r4,%r5,%r6 sub,ev %r4,%r5,%r6 subo %r4,%r5,%r6 subo,= %r4,%r5,%r6 subo,< %r4,%r5,%r6 subo,<= %r4,%r5,%r6 subo,<< %r4,%r5,%r6 subo,<<= %r4,%r5,%r6 subo,sv %r4,%r5,%r6 subo,od %r4,%r5,%r6 subo,tr %r4,%r5,%r6 subo,<> %r4,%r5,%r6 subo,>= %r4,%r5,%r6 subo,> %r4,%r5,%r6 subo,>>= %r4,%r5,%r6 subo,>> %r4,%r5,%r6 subo,nsv %r4,%r5,%r6 subo,ev %r4,%r5,%r6 subb %r4,%r5,%r6 subb,= %r4,%r5,%r6 subb,< %r4,%r5,%r6 subb,<= %r4,%r5,%r6 subb,<< %r4,%r5,%r6 subb,<<= %r4,%r5,%r6 subb,sv %r4,%r5,%r6 subb,od %r4,%r5,%r6 subb,tr %r4,%r5,%r6 subb,<> %r4,%r5,%r6 subb,>= %r4,%r5,%r6 subb,> %r4,%r5,%r6 subb,>>= %r4,%r5,%r6 subb,>> %r4,%r5,%r6 subb,nsv %r4,%r5,%r6 subb,ev %r4,%r5,%r6 subbo %r4,%r5,%r6 subbo,= %r4,%r5,%r6 subbo,< %r4,%r5,%r6 subbo,<= %r4,%r5,%r6 subbo,<< %r4,%r5,%r6 subbo,<<= %r4,%r5,%r6 subbo,sv %r4,%r5,%r6 subbo,od %r4,%r5,%r6 subbo,tr %r4,%r5,%r6 subbo,<> %r4,%r5,%r6 subbo,>= %r4,%r5,%r6 subbo,> %r4,%r5,%r6 subbo,>>= %r4,%r5,%r6 subbo,>> %r4,%r5,%r6 subbo,nsv %r4,%r5,%r6 subbo,ev %r4,%r5,%r6 subt %r4,%r5,%r6 subt,= %r4,%r5,%r6 subt,< %r4,%r5,%r6 subt,<= %r4,%r5,%r6 subt,<< %r4,%r5,%r6 subt,<<= %r4,%r5,%r6 subt,sv %r4,%r5,%r6 subt,od %r4,%r5,%r6 subt,tr %r4,%r5,%r6 subt,<> %r4,%r5,%r6 subt,>= %r4,%r5,%r6 subt,> %r4,%r5,%r6 subt,>>= %r4,%r5,%r6 subt,>> %r4,%r5,%r6 subt,nsv %r4,%r5,%r6 subt,ev %r4,%r5,%r6 subto %r4,%r5,%r6 subto,= %r4,%r5,%r6 subto,< %r4,%r5,%r6 subto,<= %r4,%r5,%r6 subto,<< %r4,%r5,%r6 subto,<<= %r4,%r5,%r6 subto,sv %r4,%r5,%r6 subto,od %r4,%r5,%r6 subto,tr %r4,%r5,%r6 subto,<> %r4,%r5,%r6 subto,>= %r4,%r5,%r6 subto,> %r4,%r5,%r6 subto,>>= %r4,%r5,%r6 subto,>> %r4,%r5,%r6 subto,nsv %r4,%r5,%r6 subto,ev %r4,%r5,%r6 sub,tsv %r4,%r5,%r6 sub,tsv,= %r4,%r5,%r6 sub,tsv,< %r4,%r5,%r6 sub,tsv,<= %r4,%r5,%r6 sub,tsv,<< %r4,%r5,%r6 sub,tsv,<<= %r4,%r5,%r6 sub,tsv,sv %r4,%r5,%r6 sub,tsv,od %r4,%r5,%r6 sub,tsv,tr %r4,%r5,%r6 sub,tsv,<> %r4,%r5,%r6 sub,tsv,>= %r4,%r5,%r6 sub,tsv,> %r4,%r5,%r6 sub,tsv,>>= %r4,%r5,%r6 sub,tsv,>> %r4,%r5,%r6 sub,tsv,nsv %r4,%r5,%r6 sub,tsv,ev %r4,%r5,%r6 sub,b %r4,%r5,%r6 sub,b,= %r4,%r5,%r6 sub,b,< %r4,%r5,%r6 sub,b,<= %r4,%r5,%r6 sub,b,<< %r4,%r5,%r6 sub,b,<<= %r4,%r5,%r6 sub,b,sv %r4,%r5,%r6 sub,b,od %r4,%r5,%r6 sub,b,tr %r4,%r5,%r6 sub,b,<> %r4,%r5,%r6 sub,b,>= %r4,%r5,%r6 sub,b,> %r4,%r5,%r6 sub,b,>>= %r4,%r5,%r6 sub,b,>> %r4,%r5,%r6 sub,b,nsv %r4,%r5,%r6 sub,b,ev %r4,%r5,%r6 sub,b,tsv %r4,%r5,%r6 sub,b,tsv,= %r4,%r5,%r6 sub,b,tsv,< %r4,%r5,%r6 sub,b,tsv,<= %r4,%r5,%r6 sub,b,tsv,<< %r4,%r5,%r6 sub,b,tsv,<<= %r4,%r5,%r6 sub,b,tsv,sv %r4,%r5,%r6 sub,b,tsv,od %r4,%r5,%r6 sub,tsv,b,tr %r4,%r5,%r6 sub,tsv,b,<> %r4,%r5,%r6 sub,tsv,b,>= %r4,%r5,%r6 sub,tsv,b,> %r4,%r5,%r6 sub,tsv,b,>>= %r4,%r5,%r6 sub,tsv,b,>> %r4,%r5,%r6 sub,tsv,b,nsv %r4,%r5,%r6 sub,tsv,b,ev %r4,%r5,%r6 sub,tc %r4,%r5,%r6 sub,tc,= %r4,%r5,%r6 sub,tc,< %r4,%r5,%r6 sub,tc,<= %r4,%r5,%r6 sub,tc,<< %r4,%r5,%r6 sub,tc,<<= %r4,%r5,%r6 sub,tc,sv %r4,%r5,%r6 sub,tc,od %r4,%r5,%r6 sub,tc,tr %r4,%r5,%r6 sub,tc,<> %r4,%r5,%r6 sub,tc,>= %r4,%r5,%r6 sub,tc,> %r4,%r5,%r6 sub,tc,>>= %r4,%r5,%r6 sub,tc,>> %r4,%r5,%r6 sub,tc,nsv %r4,%r5,%r6 sub,tc,ev %r4,%r5,%r6 sub,tc,tsv %r4,%r5,%r6 sub,tc,tsv,= %r4,%r5,%r6 sub,tc,tsv,< %r4,%r5,%r6 sub,tc,tsv,<= %r4,%r5,%r6 sub,tc,tsv,<< %r4,%r5,%r6 sub,tc,tsv,<<= %r4,%r5,%r6 sub,tc,tsv,sv %r4,%r5,%r6 sub,tc,tsv,od %r4,%r5,%r6 sub,tsv,tc,tr %r4,%r5,%r6 sub,tsv,tc,<> %r4,%r5,%r6 sub,tsv,tc,>= %r4,%r5,%r6 sub,tsv,tc,> %r4,%r5,%r6 sub,tsv,tc,>>= %r4,%r5,%r6 sub,tsv,tc,>> %r4,%r5,%r6 sub,tsv,tc,nsv %r4,%r5,%r6 sub,tsv,tc,ev %r4,%r5,%r6

stsp/binutils-ia16

4,422

gas/testsuite/gas/hppa/basic/shladd2.s

.LEVEL 2.0 .code .align 4 ; PA2.0 shladd instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. shladd,* %r4,1,%r5,%r6 shladd,*= %r4,1,%r5,%r6 shladd,*< %r4,1,%r5,%r6 shladd,*<= %r4,1,%r5,%r6 shladd,*nuv %r4,1,%r5,%r6 shladd,*znv %r4,1,%r5,%r6 shladd,*sv %r4,1,%r5,%r6 shladd,*od %r4,1,%r5,%r6 shladd,*tr %r4,1,%r5,%r6 shladd,*<> %r4,1,%r5,%r6 shladd,*>= %r4,1,%r5,%r6 shladd,*> %r4,1,%r5,%r6 shladd,*uv %r4,1,%r5,%r6 shladd,*vnz %r4,1,%r5,%r6 shladd,*nsv %r4,1,%r5,%r6 shladd,*ev %r4,1,%r5,%r6 shladd,l,* %r4,1,%r5,%r6 shladd,l,*= %r4,1,%r5,%r6 shladd,l,*< %r4,1,%r5,%r6 shladd,l,*<= %r4,1,%r5,%r6 shladd,l,*nuv %r4,1,%r5,%r6 shladd,l,*znv %r4,1,%r5,%r6 shladd,l,*sv %r4,1,%r5,%r6 shladd,l,*od %r4,1,%r5,%r6 shladd,l,*tr %r4,1,%r5,%r6 shladd,l,*<> %r4,1,%r5,%r6 shladd,l,*>= %r4,1,%r5,%r6 shladd,l,*> %r4,1,%r5,%r6 shladd,l,*uv %r4,1,%r5,%r6 shladd,l,*vnz %r4,1,%r5,%r6 shladd,l,*nsv %r4,1,%r5,%r6 shladd,l,*ev %r4,1,%r5,%r6 shladd,tsv,* %r4,1,%r5,%r6 shladd,tsv,*= %r4,1,%r5,%r6 shladd,tsv,*< %r4,1,%r5,%r6 shladd,tsv,*<= %r4,1,%r5,%r6 shladd,tsv,*nuv %r4,1,%r5,%r6 shladd,tsv,*znv %r4,1,%r5,%r6 shladd,tsv,*sv %r4,1,%r5,%r6 shladd,tsv,*od %r4,1,%r5,%r6 shladd,tsv,*tr %r4,1,%r5,%r6 shladd,tsv,*<> %r4,1,%r5,%r6 shladd,tsv,*>= %r4,1,%r5,%r6 shladd,tsv,*> %r4,1,%r5,%r6 shladd,tsv,*uv %r4,1,%r5,%r6 shladd,tsv,*vnz %r4,1,%r5,%r6 shladd,tsv,*nsv %r4,1,%r5,%r6 shladd,tsv,*ev %r4,1,%r5,%r6 shladd,* %r4,2,%r5,%r6 shladd,*= %r4,2,%r5,%r6 shladd,*< %r4,2,%r5,%r6 shladd,*<= %r4,2,%r5,%r6 shladd,*nuv %r4,2,%r5,%r6 shladd,*znv %r4,2,%r5,%r6 shladd,*sv %r4,2,%r5,%r6 shladd,*od %r4,2,%r5,%r6 shladd,*tr %r4,2,%r5,%r6 shladd,*<> %r4,2,%r5,%r6 shladd,*>= %r4,2,%r5,%r6 shladd,*> %r4,2,%r5,%r6 shladd,*uv %r4,2,%r5,%r6 shladd,*vnz %r4,2,%r5,%r6 shladd,*nsv %r4,2,%r5,%r6 shladd,*ev %r4,2,%r5,%r6 shladd,l,* %r4,2,%r5,%r6 shladd,l,*= %r4,2,%r5,%r6 shladd,l,*< %r4,2,%r5,%r6 shladd,l,*<= %r4,2,%r5,%r6 shladd,l,*nuv %r4,2,%r5,%r6 shladd,l,*znv %r4,2,%r5,%r6 shladd,l,*sv %r4,2,%r5,%r6 shladd,l,*od %r4,2,%r5,%r6 shladd,l,*tr %r4,2,%r5,%r6 shladd,l,*<> %r4,2,%r5,%r6 shladd,l,*>= %r4,2,%r5,%r6 shladd,l,*> %r4,2,%r5,%r6 shladd,l,*uv %r4,2,%r5,%r6 shladd,l,*vnz %r4,2,%r5,%r6 shladd,l,*nsv %r4,2,%r5,%r6 shladd,l,*ev %r4,2,%r5,%r6 shladd,tsv,* %r4,2,%r5,%r6 shladd,tsv,*= %r4,2,%r5,%r6 shladd,tsv,*< %r4,2,%r5,%r6 shladd,tsv,*<= %r4,2,%r5,%r6 shladd,tsv,*nuv %r4,2,%r5,%r6 shladd,tsv,*znv %r4,2,%r5,%r6 shladd,tsv,*sv %r4,2,%r5,%r6 shladd,tsv,*od %r4,2,%r5,%r6 shladd,tsv,*tr %r4,2,%r5,%r6 shladd,tsv,*<> %r4,2,%r5,%r6 shladd,tsv,*>= %r4,2,%r5,%r6 shladd,tsv,*> %r4,2,%r5,%r6 shladd,tsv,*uv %r4,2,%r5,%r6 shladd,tsv,*vnz %r4,2,%r5,%r6 shladd,tsv,*nsv %r4,2,%r5,%r6 shladd,tsv,*ev %r4,2,%r5,%r6 shladd,* %r4,3,%r5,%r6 shladd,*= %r4,3,%r5,%r6 shladd,*< %r4,3,%r5,%r6 shladd,*<= %r4,3,%r5,%r6 shladd,*nuv %r4,3,%r5,%r6 shladd,*znv %r4,3,%r5,%r6 shladd,*sv %r4,3,%r5,%r6 shladd,*od %r4,3,%r5,%r6 shladd,*tr %r4,3,%r5,%r6 shladd,*<> %r4,3,%r5,%r6 shladd,*>= %r4,3,%r5,%r6 shladd,*> %r4,3,%r5,%r6 shladd,*uv %r4,3,%r5,%r6 shladd,*vnz %r4,3,%r5,%r6 shladd,*nsv %r4,3,%r5,%r6 shladd,*ev %r4,3,%r5,%r6 shladd,l,* %r4,3,%r5,%r6 shladd,l,*= %r4,3,%r5,%r6 shladd,l,*< %r4,3,%r5,%r6 shladd,l,*<= %r4,3,%r5,%r6 shladd,l,*nuv %r4,3,%r5,%r6 shladd,l,*znv %r4,3,%r5,%r6 shladd,l,*sv %r4,3,%r5,%r6 shladd,l,*od %r4,3,%r5,%r6 shladd,l,*tr %r4,3,%r5,%r6 shladd,l,*<> %r4,3,%r5,%r6 shladd,l,*>= %r4,3,%r5,%r6 shladd,l,*> %r4,3,%r5,%r6 shladd,l,*uv %r4,3,%r5,%r6 shladd,l,*vnz %r4,3,%r5,%r6 shladd,l,*nsv %r4,3,%r5,%r6 shladd,l,*ev %r4,3,%r5,%r6 shladd,tsv,* %r4,3,%r5,%r6 shladd,tsv,*= %r4,3,%r5,%r6 shladd,tsv,*< %r4,3,%r5,%r6 shladd,tsv,*<= %r4,3,%r5,%r6 shladd,tsv,*nuv %r4,3,%r5,%r6 shladd,tsv,*znv %r4,3,%r5,%r6 shladd,tsv,*sv %r4,3,%r5,%r6 shladd,tsv,*od %r4,3,%r5,%r6 shladd,tsv,*tr %r4,3,%r5,%r6 shladd,tsv,*<> %r4,3,%r5,%r6 shladd,tsv,*>= %r4,3,%r5,%r6 shladd,tsv,*> %r4,3,%r5,%r6 shladd,tsv,*uv %r4,3,%r5,%r6 shladd,tsv,*vnz %r4,3,%r5,%r6 shladd,tsv,*nsv %r4,3,%r5,%r6 shladd,tsv,*ev %r4,3,%r5,%r6

stsp/binutils-ia16

1,418

gas/testsuite/gas/hppa/basic/sh3add.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. sh3add %r4,%r5,%r6 sh3add,= %r4,%r5,%r6 sh3add,< %r4,%r5,%r6 sh3add,<= %r4,%r5,%r6 sh3add,nuv %r4,%r5,%r6 sh3add,znv %r4,%r5,%r6 sh3add,sv %r4,%r5,%r6 sh3add,od %r4,%r5,%r6 sh3add,tr %r4,%r5,%r6 sh3add,<> %r4,%r5,%r6 sh3add,>= %r4,%r5,%r6 sh3add,> %r4,%r5,%r6 sh3add,uv %r4,%r5,%r6 sh3add,vnz %r4,%r5,%r6 sh3add,nsv %r4,%r5,%r6 sh3add,ev %r4,%r5,%r6 sh3addl %r4,%r5,%r6 sh3addl,= %r4,%r5,%r6 sh3addl,< %r4,%r5,%r6 sh3addl,<= %r4,%r5,%r6 sh3addl,nuv %r4,%r5,%r6 sh3addl,znv %r4,%r5,%r6 sh3addl,sv %r4,%r5,%r6 sh3addl,od %r4,%r5,%r6 sh3addl,tr %r4,%r5,%r6 sh3addl,<> %r4,%r5,%r6 sh3addl,>= %r4,%r5,%r6 sh3addl,> %r4,%r5,%r6 sh3addl,uv %r4,%r5,%r6 sh3addl,vnz %r4,%r5,%r6 sh3addl,nsv %r4,%r5,%r6 sh3addl,ev %r4,%r5,%r6 sh3addo %r4,%r5,%r6 sh3addo,= %r4,%r5,%r6 sh3addo,< %r4,%r5,%r6 sh3addo,<= %r4,%r5,%r6 sh3addo,nuv %r4,%r5,%r6 sh3addo,znv %r4,%r5,%r6 sh3addo,sv %r4,%r5,%r6 sh3addo,od %r4,%r5,%r6 sh3addo,tr %r4,%r5,%r6 sh3addo,<> %r4,%r5,%r6 sh3addo,>= %r4,%r5,%r6 sh3addo,> %r4,%r5,%r6 sh3addo,uv %r4,%r5,%r6 sh3addo,vnz %r4,%r5,%r6 sh3addo,nsv %r4,%r5,%r6 sh3addo,ev %r4,%r5,%r6

stsp/binutils-ia16

1,318

gas/testsuite/gas/hppa/basic/subi.s

.code .align 4 ; Basic immediate instruction tests. ; ; We could/should test some of the corner cases for register and ; immediate fields. We should also check the assorted field ; selectors to make sure they're handled correctly. subi 123,%r5,%r6 subi,= 123,%r5,%r6 subi,< 123,%r5,%r6 subi,<= 123,%r5,%r6 subi,<< 123,%r5,%r6 subi,<<= 123,%r5,%r6 subi,sv 123,%r5,%r6 subi,od 123,%r5,%r6 subi,tr 123,%r5,%r6 subi,<> 123,%r5,%r6 subi,>= 123,%r5,%r6 subi,> 123,%r5,%r6 subi,>>= 123,%r5,%r6 subi,>> 123,%r5,%r6 subi,nsv 123,%r5,%r6 subi,ev 123,%r5,%r6 subio 123,%r5,%r6 subio,= 123,%r5,%r6 subio,< 123,%r5,%r6 subio,<= 123,%r5,%r6 subio,<< 123,%r5,%r6 subio,<<= 123,%r5,%r6 subio,sv 123,%r5,%r6 subio,od 123,%r5,%r6 subio,tr 123,%r5,%r6 subio,<> 123,%r5,%r6 subio,>= 123,%r5,%r6 subio,> 123,%r5,%r6 subio,>>= 123,%r5,%r6 subio,>> 123,%r5,%r6 subio,nsv 123,%r5,%r6 subio,ev 123,%r5,%r6 subi,tsv 123,%r5,%r6 subi,tsv,= 123,%r5,%r6 subi,tsv,< 123,%r5,%r6 subi,tsv,<= 123,%r5,%r6 subi,tsv,<< 123,%r5,%r6 subi,tsv,<<= 123,%r5,%r6 subi,tsv,sv 123,%r5,%r6 subi,tsv,od 123,%r5,%r6 subi,tsv,tr 123,%r5,%r6 subi,tsv,<> 123,%r5,%r6 subi,tsv,>= 123,%r5,%r6 subi,tsv,> 123,%r5,%r6 subi,tsv,>>= 123,%r5,%r6 subi,tsv,>> 123,%r5,%r6 subi,tsv,nsv 123,%r5,%r6 subi,tsv,ev 123,%r5,%r6

stsp/binutils-ia16

3,215

gas/testsuite/gas/hppa/parse/calldatabug.s

.code .align 4 LC$0000: .STRING "%d %lf %d\x0a\x00" .align 4 .EXPORT error__3AAAiidi .EXPORT error__3AAAiidi,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=FR,ARGW4=FU,RTNVAL=GR error__3AAAiidi: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) copy %r26,%r5 ldo -8(%r0),%r6 ldo -32(%r4),%r19 add %r19,%r6,%r7 stw %r25,0(%r7) ldo -12(%r0),%r8 ldo -32(%r4),%r19 add %r19,%r8,%r9 stw %r24,0(%r9) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -24(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -28(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) ldil L'LC$0000,%r26 ldo R'LC$0000(%r26),%r26 ldw 0(%r19),%r25 fldds 0(%r20),%fr7 .CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU bl printf,%r2 nop bl,n L$0002,%r0 bl,n L$0001,%r0 L$0002: L$0001: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT ok__3AAAidi .EXPORT ok__3AAAidi,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU,RTNVAL=GR ok__3AAAidi: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) copy %r26,%r5 ldo -8(%r0),%r6 ldo -32(%r4),%r19 add %r19,%r6,%r7 stw %r25,0(%r7) ldo -16(%r0),%r8 ldo -32(%r4),%r19 add %r19,%r8,%r9 fstds %fr7,0(%r9) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -16(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -20(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) ldil L'LC$0000,%r26 ldo R'LC$0000(%r26),%r26 ldw 0(%r19),%r25 fldds 0(%r20),%fr7 .CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU bl printf,%r2 nop bl,n L$0004,%r0 bl,n L$0003,%r0 L$0004: L$0003: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT __main,CODE .align 8 LC$0001: ; .double 5.50000000000000000000e+00 .word 1075183616 ; = 0x40160000 .word 0 ; = 0x0 .align 4 .EXPORT main .EXPORT main,PRIV_LEV=3,RTNVAL=GR main: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) .CALL bl __main,%r2 nop ldo -24(%r0),%r19 ldo -32(%r30),%r20 add %r20,%r19,%r19 ldil L'LC$0001,%r20 ldo R'LC$0001(%r20),%r21 ldw 0(%r21),%r22 ldw 4(%r21),%r23 stw %r22,0(%r19) stw %r23,4(%r19) ldo 3(%r0),%r19 stw %r19,-60(%r30) ldo 8(%r4),%r26 ldo 1(%r0),%r25 ldo 4(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl error__3AAAiidi,%r2 nop ldo 3(%r0),%r19 stw %r19,-52(%r30) ldo 8(%r4),%r26 ldo 1(%r0),%r25 ldil L'LC$0001,%r19 ldo R'LC$0001(%r19),%r20 fldds 0(%r20),%fr7 .CALL ARGW0=GR,ARGW1=GR,ARGW2=FR,ARGW3=FU bl ok__3AAAidi,%r2 nop copy %r0,%r28 bl,n L$0005,%r0 bl,n L$0005,%r0 L$0005: ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND

stsp/binutils-ia16

110,003

gas/testsuite/gas/hppa/parse/fixup7bug.s

.IMPORT $global$,DATA .IMPORT $$dyncall,MILLICODE .code .align 4 .EXPORT alloc_type,CODE .EXPORT alloc_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR alloc_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r7,32(%r4) stw %r6,36(%r4) stw %r5,40(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0002,%r0 nop ldo 52(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r7 bl,n L$0003,%r0 L$0002: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 120(%r19),%r20 stw %r20,8(%r4) ldw 8(%r4),%r19 stw %r19,12(%r4) ldo 52(%r0),%r19 stw %r19,16(%r4) ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 16(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0004,%r0 nop ldw 12(%r4),%r26 ldw 16(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0005,%r0 L$0004: copy %r0,%r19 L$0005: ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 12(%r20),%r21 ldw 16(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 8(%r4),%r19 stw %r19,20(%r4) ldw 20(%r4),%r19 ldw 8(%r19),%r20 stw %r20,24(%r4) ldw 20(%r4),%r19 ldw 12(%r19),%r20 ldw 24(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0006,%r0 nop ldw 20(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0006: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 20(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0007,%r0 nop ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0008,%r0 L$0007: copy %r0,%r19 L$0008: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 24(%r4),%r7 L$0003: copy %r7,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop stw %r0,0(%r7) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,12(%r7) ldo -1(%r0),%r19 stw %r19,44(%r7) copy %r7,%r28 bl,n L$0001,%r0 L$0001: ldw 32(%r4),%r7 ldw 36(%r4),%r6 ldw 40(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT make_pointer_type,CODE .EXPORT make_pointer_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR make_pointer_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r9,16(%r4) stw %r8,20(%r4) stw %r7,24(%r4) stw %r6,28(%r4) stw %r5,32(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 20(%r19),%r9 comiclr,<> 0,%r9,%r0 bl L$0010,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0011,%r0 nop copy %r9,%r28 bl,n L$0009,%r0 bl,n L$0012,%r0 L$0011: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0013,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) copy %r9,%r28 bl,n L$0009,%r0 L$0013: L$0012: L$0010: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0015,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0014,%r0 nop bl,n L$0015,%r0 L$0015: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0016,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) L$0016: bl,n L$0017,%r0 L$0014: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r9 ldw 12(%r9),%r19 stw %r19,8(%r4) copy %r9,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldw 8(%r4),%r19 stw %r19,12(%r9) L$0017: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,16(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,20(%r19) ldo 4(%r0),%r19 stw %r19,8(%r9) ldo 1(%r0),%r19 stw %r19,0(%r9) ldh 32(%r9),%r19 copy %r19,%r20 depi -1,31,1,%r20 sth %r20,32(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 20(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0018,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,20(%r19) L$0018: copy %r9,%r28 bl,n L$0009,%r0 L$0009: ldw 16(%r4),%r9 ldw 20(%r4),%r8 ldw 24(%r4),%r7 ldw 28(%r4),%r6 ldw 32(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT lookup_pointer_type,CODE .EXPORT lookup_pointer_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_pointer_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl make_pointer_type,%r2 nop bl,n L$0019,%r0 L$0019: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT make_reference_type,CODE .EXPORT make_reference_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR make_reference_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r9,16(%r4) stw %r8,20(%r4) stw %r7,24(%r4) stw %r6,28(%r4) stw %r5,32(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 24(%r19),%r9 comiclr,<> 0,%r9,%r0 bl L$0021,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0022,%r0 nop copy %r9,%r28 bl,n L$0020,%r0 bl,n L$0023,%r0 L$0022: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0024,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) copy %r9,%r28 bl,n L$0020,%r0 L$0024: L$0023: L$0021: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0026,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0025,%r0 nop bl,n L$0026,%r0 L$0026: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0027,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) L$0027: bl,n L$0028,%r0 L$0025: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r9 ldw 12(%r9),%r19 stw %r19,8(%r4) copy %r9,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldw 8(%r4),%r19 stw %r19,12(%r9) L$0028: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,16(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,24(%r19) ldo 4(%r0),%r19 stw %r19,8(%r9) ldo 16(%r0),%r19 stw %r19,0(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 24(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0029,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,24(%r19) L$0029: copy %r9,%r28 bl,n L$0020,%r0 L$0020: ldw 16(%r4),%r9 ldw 20(%r4),%r8 ldw 24(%r4),%r7 ldw 28(%r4),%r6 ldw 32(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT lookup_reference_type,CODE .EXPORT lookup_reference_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_reference_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl make_reference_type,%r2 nop bl,n L$0030,%r0 L$0030: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT make_function_type,CODE .EXPORT make_function_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR make_function_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r9,16(%r4) stw %r8,20(%r4) stw %r7,24(%r4) stw %r6,28(%r4) stw %r5,32(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 28(%r19),%r9 comiclr,<> 0,%r9,%r0 bl L$0032,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0033,%r0 nop copy %r9,%r28 bl,n L$0031,%r0 bl,n L$0034,%r0 L$0033: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0035,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) copy %r9,%r28 bl,n L$0031,%r0 L$0035: L$0034: L$0032: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0037,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0036,%r0 nop bl,n L$0037,%r0 L$0037: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0038,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,0(%r19) L$0038: bl,n L$0039,%r0 L$0036: ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r9 ldw 12(%r9),%r19 stw %r19,8(%r4) copy %r9,%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldw 8(%r4),%r19 stw %r19,12(%r9) L$0039: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,16(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,28(%r19) ldo 1(%r0),%r19 stw %r19,8(%r9) ldo 6(%r0),%r19 stw %r19,0(%r9) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 28(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0040,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 stw %r9,28(%r19) L$0040: copy %r9,%r28 bl,n L$0031,%r0 L$0031: ldw 16(%r4),%r9 ldw 20(%r4),%r8 ldw 24(%r4),%r7 ldw 28(%r4),%r6 ldw 32(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT lookup_function_type,CODE .EXPORT lookup_function_type,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_function_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl make_function_type,%r2 nop bl,n L$0041,%r0 L$0041: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT smash_to_member_type,CODE .align 4 .EXPORT lookup_member_type,CODE .EXPORT lookup_member_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_member_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,8(%r4) stw %r7,12(%r4) stw %r6,16(%r4) stw %r5,20(%r4) ldo 24(%r4),%r1 fstds,ma %fr12,8(%r1) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,-16(%r30) fldws -16(%r30),%fr12 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 fstws %fr12,-16(%r30) ldw -16(%r30),%r26 ldw 0(%r19),%r25 ldw 0(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl smash_to_member_type,%r2 nop fstws %fr12,-16(%r30) ldw -16(%r30),%r28 bl,n L$0042,%r0 L$0042: ldw 8(%r4),%r8 ldw 12(%r4),%r7 ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 24(%r4),%r1 fldds,ma 8(%r1),%fr12 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT allocate_stub_method,CODE .EXPORT allocate_stub_method,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR allocate_stub_method: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldw 8(%r4),%r19 ldo 4(%r0),%r20 sth %r20,32(%r19) ldw 8(%r4),%r19 ldo 15(%r0),%r20 stw %r20,0(%r19) ldw 8(%r4),%r19 ldo 1(%r0),%r20 stw %r20,8(%r19) ldw 8(%r4),%r28 bl,n L$0043,%r0 L$0043: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT builtin_type_int,DATA .align 4 .EXPORT create_array_type,CODE .EXPORT create_array_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR create_array_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r10,56(%r4) stw %r9,60(%r4) stw %r8,64(%r4) stw %r7,68(%r4) stw %r6,72(%r4) stw %r5,76(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 ldo 2(%r0),%r20 stw %r20,0(%r19) ldw 8(%r4),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldw 8(%r4),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 0(%r20),%r20 ldw 8(%r21),%r21 stw %r20,-16(%r30) fldws -16(%r30),%fr5 stw %r21,-16(%r30) fldws -16(%r30),%fr5R xmpyu %fr5,%fr5R,%fr4 fstws %fr4R,-16(%r30) ldw -16(%r30),%r24 stw %r24,8(%r19) ldw 8(%r4),%r19 ldo 1(%r0),%r20 sth %r20,34(%r19) ldw 8(%r4),%r9 ldw 8(%r4),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0050,%r0 nop ldw 8(%r4),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,16(%r4) ldw 16(%r4),%r19 stw %r19,20(%r4) ldo 16(%r0),%r19 stw %r19,24(%r4) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 24(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0045,%r0 nop ldw 20(%r4),%r26 ldw 24(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0046,%r0 L$0045: copy %r0,%r19 L$0046: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 ldw 24(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 16(%r4),%r19 stw %r19,28(%r4) ldw 28(%r4),%r19 ldw 8(%r19),%r20 stw %r20,32(%r4) ldw 28(%r4),%r19 ldw 12(%r19),%r20 ldw 32(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0047,%r0 nop ldw 28(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0047: ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 28(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 28(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 28(%r4),%r20 ldw 28(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0048,%r0 nop ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0049,%r0 L$0048: copy %r0,%r19 L$0049: ldw 28(%r4),%r19 ldw 28(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 32(%r4),%r10 bl,n L$0051,%r0 L$0050: ldo 16(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r10 L$0051: stw %r10,36(%r9) ldw 8(%r4),%r19 ldw 12(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop stw %r28,12(%r4) ldw 12(%r4),%r19 ldo 11(%r0),%r20 stw %r20,0(%r19) ldw 12(%r4),%r19 addil L'builtin_type_int-$global$,%r27 ldw R'builtin_type_int-$global$(%r1),%r20 stw %r20,16(%r19) ldw 12(%r4),%r19 ldo 4(%r0),%r20 stw %r20,8(%r19) ldw 12(%r4),%r19 ldo 2(%r0),%r20 sth %r20,34(%r19) ldw 12(%r4),%r9 ldw 12(%r4),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0057,%r0 nop ldw 12(%r4),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,36(%r4) ldw 36(%r4),%r19 stw %r19,40(%r4) ldo 32(%r0),%r19 stw %r19,44(%r4) ldw 40(%r4),%r19 ldw 40(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 44(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0052,%r0 nop ldw 40(%r4),%r26 ldw 44(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0053,%r0 L$0052: copy %r0,%r19 L$0053: ldw 40(%r4),%r19 ldw 40(%r4),%r20 ldw 12(%r20),%r21 ldw 44(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 36(%r4),%r19 stw %r19,48(%r4) ldw 48(%r4),%r19 ldw 8(%r19),%r20 stw %r20,52(%r4) ldw 48(%r4),%r19 ldw 12(%r19),%r20 ldw 52(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0054,%r0 nop ldw 48(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0054: ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 48(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 48(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 48(%r4),%r20 ldw 48(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0055,%r0 nop ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0056,%r0 L$0055: copy %r0,%r19 L$0056: ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 52(%r4),%r10 bl,n L$0058,%r0 L$0057: ldo 32(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r10 L$0058: stw %r10,36(%r9) ldw 12(%r4),%r19 ldw 36(%r19),%r20 stw %r0,0(%r20) ldw 12(%r4),%r19 ldo 16(%r0),%r20 ldw 36(%r19),%r21 add %r20,%r21,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldo -1(%r20),%r21 stw %r21,0(%r19) ldw 12(%r4),%r20 ldw 36(%r20),%r19 addil L'builtin_type_int-$global$,%r27 ldw R'builtin_type_int-$global$(%r1),%r20 stw %r20,8(%r19) ldw 12(%r4),%r19 ldo 16(%r0),%r20 ldw 36(%r19),%r21 add %r20,%r21,%r19 addil L'builtin_type_int-$global$,%r27 ldw R'builtin_type_int-$global$(%r1),%r20 stw %r20,8(%r19) ldw 8(%r4),%r19 ldw 36(%r19),%r20 ldw 12(%r4),%r19 stw %r19,8(%r20) ldw 8(%r4),%r19 ldo -1(%r0),%r20 stw %r20,44(%r19) ldw 8(%r4),%r28 bl,n L$0044,%r0 L$0044: ldw 56(%r4),%r10 ldw 60(%r4),%r9 ldw 64(%r4),%r8 ldw 68(%r4),%r7 ldw 72(%r4),%r6 ldw 76(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT smash_to_member_type,CODE .EXPORT smash_to_member_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR smash_to_member_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r10,16(%r4) stw %r9,20(%r4) stw %r8,24(%r4) stw %r7,28(%r4) stw %r6,32(%r4) stw %r5,36(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 stw %r20,8(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 stw %r20,12(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -12(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,40(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 1(%r0),%r20 stw %r20,8(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 14(%r0),%r20 stw %r20,0(%r19) L$0059: ldw 16(%r4),%r10 ldw 20(%r4),%r9 ldw 24(%r4),%r8 ldw 28(%r4),%r7 ldw 32(%r4),%r6 ldw 36(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT smash_to_method_type,CODE .EXPORT smash_to_method_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR smash_to_method_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r12,16(%r4) stw %r11,20(%r4) stw %r10,24(%r4) stw %r9,28(%r4) stw %r8,32(%r4) stw %r7,36(%r4) stw %r6,40(%r4) stw %r5,44(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -16(%r0),%r11 ldo -32(%r4),%r19 add %r19,%r11,%r12 stw %r23,0(%r12) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 stw %r20,8(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 stw %r20,12(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -12(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,16(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,40(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -16(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,48(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 1(%r0),%r20 stw %r20,8(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 15(%r0),%r20 stw %r20,0(%r19) L$0060: ldw 16(%r4),%r12 ldw 20(%r4),%r11 ldw 24(%r4),%r10 ldw 28(%r4),%r9 ldw 32(%r4),%r8 ldw 36(%r4),%r7 ldw 40(%r4),%r6 ldw 44(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT strncmp,CODE .align 4 LC$0000: .STRING "struct \x00" .align 4 LC$0001: .STRING "union \x00" .align 4 LC$0002: .STRING "enum \x00" .align 4 .EXPORT type_name_no_tag,CODE .EXPORT type_name_no_tag,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR type_name_no_tag: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,8(%r4) stw %r5,12(%r4) copy %r26,%r5 ldw 4(%r5),%r6 comiclr,<> 0,%r6,%r0 bl L$0062,%r0 nop ldw 0(%r5),%r19 comiclr,<> 4,%r19,%r0 bl L$0066,%r0 nop comiclr,>= 4,%r19,%r0 bl L$0072,%r0 nop comiclr,<> 3,%r19,%r0 bl L$0064,%r0 nop bl,n L$0070,%r0 L$0072: comiclr,<> 5,%r19,%r0 bl L$0068,%r0 nop bl,n L$0070,%r0 L$0064: copy %r6,%r26 ldil L'LC$0000,%r25 ldo R'LC$0000(%r25),%r25 ldo 7(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl strncmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0065,%r0 nop ldo 7(%r6),%r6 L$0065: bl,n L$0063,%r0 L$0066: copy %r6,%r26 ldil L'LC$0001,%r25 ldo R'LC$0001(%r25),%r25 ldo 6(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl strncmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0067,%r0 nop ldo 6(%r6),%r6 L$0067: bl,n L$0063,%r0 L$0068: copy %r6,%r26 ldil L'LC$0002,%r25 ldo R'LC$0002(%r25),%r25 ldo 5(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl strncmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0069,%r0 nop ldo 5(%r6),%r6 L$0069: bl,n L$0063,%r0 L$0070: bl,n L$0063,%r0 L$0063: L$0062: copy %r6,%r28 bl,n L$0061,%r0 L$0061: ldw 8(%r4),%r6 ldw 12(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT current_language,DATA .IMPORT strcmp,CODE .align 4 .EXPORT lookup_primitive_typename,CODE .EXPORT lookup_primitive_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_primitive_typename: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) addil L'current_language-$global$,%r27 ldw R'current_language-$global$(%r1),%r19 ldw 8(%r19),%r20 stw %r20,8(%r4) L$0074: ldw 8(%r4),%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0075,%r0 nop ldw 8(%r4),%r19 ldw 0(%r19),%r20 ldw 0(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 4(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0077,%r0 nop ldw 8(%r4),%r19 ldw 0(%r19),%r20 ldw 0(%r20),%r28 bl,n L$0073,%r0 L$0077: L$0076: ldw 8(%r4),%r19 ldo 4(%r19),%r20 stw %r20,8(%r4) bl,n L$0074,%r0 L$0075: copy %r0,%r28 bl,n L$0073,%r0 L$0073: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT lookup_symbol,CODE .IMPORT error,CODE .align 4 LC$0003: .STRING "No type named %s.\x00" .align 4 .EXPORT lookup_typename,CODE .EXPORT lookup_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR lookup_typename: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r12,8(%r4) stw %r11,12(%r4) stw %r10,16(%r4) stw %r9,20(%r4) stw %r8,24(%r4) stw %r7,28(%r4) stw %r6,32(%r4) stw %r5,36(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 1(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r11 comiclr,<> 0,%r11,%r0 bl L$0080,%r0 nop ldw 8(%r11),%r19 comiclr,= 8,%r19,%r0 bl L$0080,%r0 nop bl,n L$0079,%r0 L$0080: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl lookup_primitive_typename,%r2 nop copy %r28,%r12 comiclr,<> 0,%r12,%r0 bl L$0081,%r0 nop copy %r12,%r28 bl,n L$0078,%r0 bl,n L$0082,%r0 L$0081: comiclr,= 0,%r12,%r0 bl L$0083,%r0 nop ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0083,%r0 nop copy %r0,%r28 bl,n L$0078,%r0 bl,n L$0084,%r0 L$0083: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0003,%r26 ldo R'LC$0003(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0084: L$0082: L$0079: ldw 12(%r11),%r28 bl,n L$0078,%r0 L$0078: ldw 8(%r4),%r12 ldw 12(%r4),%r11 ldw 16(%r4),%r10 ldw 20(%r4),%r9 ldw 24(%r4),%r8 ldw 28(%r4),%r7 ldw 32(%r4),%r6 ldw 36(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT alloca,CODE .IMPORT strlen,CODE .IMPORT strcpy,CODE .align 4 LC$0004: .STRING "unsigned \x00" .align 4 .EXPORT lookup_unsigned_typename,CODE .EXPORT lookup_unsigned_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_unsigned_typename: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 ldo 10(%r19),%r20 ldo 7(%r20),%r21 copy %r21,%r19 ldo 63(%r19),%r20 extru %r20,25,26,%r19 zdep %r19,25,26,%r20 ldo -96(%r30),%r19 add %r30,%r20,%r30 ldo 7(%r19),%r20 extru %r20,28,29,%r19 zdep %r19,28,29,%r20 stw %r20,8(%r4) ldw 8(%r4),%r26 ldil L'LC$0004,%r25 ldo R'LC$0004(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 8(%r4),%r20 ldo 9(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 copy %r19,%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 8(%r4),%r26 copy %r0,%r25 copy %r0,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_typename,%r2 nop bl,n L$0085,%r0 L$0085: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0005: .STRING "signed \x00" .align 4 .EXPORT lookup_signed_typename,CODE .EXPORT lookup_signed_typename,ENTRY,PRIV_LEV=3,ARGW0=GR,RTNVAL=GR lookup_signed_typename: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 ldo 8(%r19),%r20 ldo 7(%r20),%r21 copy %r21,%r19 ldo 63(%r19),%r20 extru %r20,25,26,%r19 zdep %r19,25,26,%r20 ldo -96(%r30),%r19 add %r30,%r20,%r30 ldo 7(%r19),%r20 extru %r20,28,29,%r19 zdep %r19,28,29,%r20 stw %r20,12(%r4) ldw 12(%r4),%r26 ldil L'LC$0005,%r25 ldo R'LC$0005(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 12(%r4),%r20 ldo 7(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 copy %r19,%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 12(%r4),%r26 copy %r0,%r25 ldo 1(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_typename,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0087,%r0 nop ldw 8(%r4),%r28 bl,n L$0086,%r0 L$0087: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 copy %r0,%r25 copy %r0,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_typename,%r2 nop bl,n L$0086,%r0 L$0086: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0006: .STRING "No struct type named %s.\x00" .align 4 LC$0007: .STRING "This context has class, union or enum %s, not a struct.\x00" .align 4 .EXPORT lookup_struct,CODE .EXPORT lookup_struct,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_struct: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r9 comiclr,= 0,%r9,%r0 bl L$0089,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0006,%r26 ldo R'LC$0006(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0089: ldw 12(%r9),%r19 ldw 0(%r19),%r20 comiclr,<> 3,%r20,%r0 bl L$0090,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0007,%r26 ldo R'LC$0007(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0090: ldw 12(%r9),%r28 bl,n L$0088,%r0 L$0088: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0008: .STRING "No union type named %s.\x00" .align 4 LC$0009: .STRING "This context has class, struct or enum %s, not a union.\x00" .align 4 .EXPORT lookup_union,CODE .EXPORT lookup_union,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_union: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r9 comiclr,= 0,%r9,%r0 bl L$0092,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0008,%r26 ldo R'LC$0008(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0092: ldw 12(%r9),%r19 ldw 0(%r19),%r20 comiclr,<> 4,%r20,%r0 bl L$0093,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0009,%r26 ldo R'LC$0009(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0093: ldw 12(%r9),%r28 bl,n L$0091,%r0 L$0091: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0010: .STRING "No enum type named %s.\x00" .align 4 LC$0011: .STRING "This context has class, struct or union %s, not an enum.\x00" .align 4 .EXPORT lookup_enum,CODE .EXPORT lookup_enum,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_enum: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r9,8(%r4) stw %r8,12(%r4) stw %r7,16(%r4) stw %r6,20(%r4) stw %r5,24(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 stw %r0,-52(%r30) ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop copy %r28,%r9 comiclr,= 0,%r9,%r0 bl L$0095,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0010,%r26 ldo R'LC$0010(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0095: ldw 12(%r9),%r19 ldw 0(%r19),%r20 comiclr,<> 5,%r20,%r0 bl L$0096,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0011,%r26 ldo R'LC$0011(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0096: ldw 12(%r9),%r28 bl,n L$0094,%r0 L$0094: ldw 8(%r4),%r9 ldw 12(%r4),%r8 ldw 16(%r4),%r7 ldw 20(%r4),%r6 ldw 24(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT strcat,CODE .align 4 LC$0012: .STRING "<\x00" .align 4 LC$0013: .STRING " >\x00" .align 4 LC$0014: .STRING "No template type named %s.\x00" .align 4 .EXPORT lookup_template_type,CODE .EXPORT lookup_template_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR lookup_template_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r11,16(%r4) stw %r10,20(%r4) stw %r9,24(%r4) stw %r8,28(%r4) stw %r7,32(%r4) stw %r6,36(%r4) stw %r5,40(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r11 ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 4(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 add %r11,%r19,%r20 ldo 4(%r20),%r19 ldo 7(%r19),%r20 copy %r20,%r19 ldo 63(%r19),%r20 extru %r20,25,26,%r19 zdep %r19,25,26,%r20 ldo -96(%r30),%r19 add %r30,%r20,%r30 ldo 7(%r19),%r20 extru %r20,28,29,%r19 zdep %r19,28,29,%r20 stw %r20,12(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 12(%r4),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcpy,%r2 nop ldw 12(%r4),%r26 ldil L'LC$0012,%r25 ldo R'LC$0012(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcat,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r4),%r26 ldw 4(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcat,%r2 nop ldw 12(%r4),%r26 ldil L'LC$0013,%r25 ldo R'LC$0013(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcat,%r2 nop ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 stw %r0,-52(%r30) ldw 12(%r4),%r26 ldw 0(%r19),%r25 ldo 1(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0098,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0014,%r26 ldo R'LC$0014(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0098: ldw 8(%r4),%r19 ldw 12(%r19),%r20 ldw 0(%r20),%r19 comiclr,<> 3,%r19,%r0 bl L$0099,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0007,%r26 ldo R'LC$0007(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0099: ldw 8(%r4),%r19 ldw 12(%r19),%r28 bl,n L$0097,%r0 L$0097: ldw 16(%r4),%r11 ldw 20(%r4),%r10 ldw 24(%r4),%r9 ldw 28(%r4),%r8 ldw 32(%r4),%r7 ldw 36(%r4),%r6 ldw 40(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT current_target,DATA .IMPORT fflush,CODE .IMPORT __iob,DATA .IMPORT fprintf,CODE .align 4 LC$0015: .STRING "Type \x00" .IMPORT type_print,CODE .align 4 LC$0016: .STRING "\x00" .align 4 LC$0017: .STRING " is not a structure or union type.\x00" .IMPORT check_stub_type,CODE .align 4 LC$0018: .STRING " has no component named \x00" .IMPORT fputs_filtered,CODE .align 4 LC$0019: .STRING ".\x00" .align 4 .EXPORT lookup_struct_elt_type,CODE .EXPORT lookup_struct_elt_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,RTNVAL=GR lookup_struct_elt_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r11,24(%r4) stw %r10,28(%r4) stw %r9,32(%r4) stw %r8,36(%r4) stw %r7,40(%r4) stw %r6,44(%r4) stw %r5,48(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 1,%r20,%r0 bl L$0102,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 ldo 16(%r0),%r19 comclr,<> %r20,%r19,%r0 bl L$0102,%r0 nop bl,n L$0101,%r0 L$0102: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 16(%r20),%r21 stw %r21,0(%r19) L$0101: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 3,%r20,%r0 bl L$0103,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 4,%r20,%r0 bl L$0103,%r0 nop addil L'current_target-$global$,%r27 ldw R'current_target-$global$(%r1),%r19 ldw 76(%r19),%r11 copy %r11,%r22 .CALL ARGW0=GR bl $$dyncall,%r31 copy %r31,%r2 addil L'__iob-$global$+16,%r27 ldo R'__iob-$global$+16(%r1),%r26 .CALL ARGW0=GR bl fflush,%r2 nop addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r26 ldil L'LC$0015,%r25 ldo R'LC$0015(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl fprintf,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 ldil L'LC$0016,%r25 ldo R'LC$0016(%r25),%r25 addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r24 ldo -1(%r0),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl type_print,%r2 nop ldil L'LC$0017,%r26 ldo R'LC$0017(%r26),%r26 .CALL ARGW0=GR bl error,%r2 nop L$0103: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl check_stub_type,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 34(%r19),%r20 extrs %r20,31,16,%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) L$0104: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 ldw 8(%r4),%r20 comclr,>= %r20,%r19,%r0 bl L$0105,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 12(%r19),%r20 stw %r20,12(%r4) ldw 12(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0107,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 12(%r4),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl strcmp,%r2 nop copy %r28,%r19 comiclr,= 0,%r19,%r0 bl L$0107,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r28 bl,n L$0100,%r0 L$0107: L$0106: ldw 8(%r4),%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) bl,n L$0104,%r0 L$0105: nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) L$0108: ldw 8(%r4),%r19 comiclr,<= 0,%r19,%r0 bl L$0109,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 8(%r19),%r26 ldw 0(%r20),%r25 copy %r0,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl lookup_struct_elt_type,%r2 nop stw %r28,16(%r4) ldw 16(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0111,%r0 nop ldw 16(%r4),%r28 bl,n L$0100,%r0 L$0111: L$0110: ldw 8(%r4),%r19 ldo -1(%r19),%r20 stw %r20,8(%r4) bl,n L$0108,%r0 L$0109: ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0112,%r0 nop copy %r0,%r28 bl,n L$0100,%r0 L$0112: addil L'current_target-$global$,%r27 ldw R'current_target-$global$(%r1),%r19 ldw 76(%r19),%r11 copy %r11,%r22 .CALL ARGW0=GR bl $$dyncall,%r31 copy %r31,%r2 addil L'__iob-$global$+16,%r27 ldo R'__iob-$global$+16(%r1),%r26 .CALL ARGW0=GR bl fflush,%r2 nop addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r26 ldil L'LC$0015,%r25 ldo R'LC$0015(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl fprintf,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 ldil L'LC$0016,%r25 ldo R'LC$0016(%r25),%r25 addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r24 ldo -1(%r0),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl type_print,%r2 nop addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r26 ldil L'LC$0018,%r25 ldo R'LC$0018(%r25),%r25 .CALL ARGW0=GR,ARGW1=GR bl fprintf,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 addil L'__iob-$global$+32,%r27 ldo R'__iob-$global$+32(%r1),%r25 .CALL ARGW0=GR,ARGW1=GR bl fputs_filtered,%r2 nop ldil L'LC$0019,%r26 ldo R'LC$0019(%r26),%r26 .CALL ARGW0=GR bl error,%r2 nop ldo -1(%r0),%r28 bl,n L$0100,%r0 L$0100: ldw 24(%r4),%r11 ldw 28(%r4),%r10 ldw 32(%r4),%r9 ldw 36(%r4),%r8 ldw 40(%r4),%r7 ldw 44(%r4),%r6 ldw 48(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT fill_in_vptr_fieldno,CODE .EXPORT fill_in_vptr_fieldno,ENTRY,PRIV_LEV=3,ARGW0=GR fill_in_vptr_fieldno: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 44(%r19),%r20 comiclr,> 0,%r20,%r0 bl L$0114,%r0 nop ldo 1(%r0),%r19 stw %r19,8(%r4) L$0115: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 ldw 8(%r4),%r20 comclr,< %r20,%r19,%r0 bl L$0116,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r26 .CALL ARGW0=GR bl fill_in_vptr_fieldno,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r20 ldw 44(%r20),%r19 comiclr,<= 0,%r19,%r0 bl L$0118,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 8(%r4),%r21 zdep %r21,27,28,%r22 ldw 36(%r20),%r21 add %r22,%r21,%r20 ldw 8(%r20),%r21 ldw 44(%r21),%r20 stw %r20,44(%r19) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 8(%r4),%r21 zdep %r21,27,28,%r22 ldw 36(%r20),%r21 add %r22,%r21,%r20 ldw 8(%r20),%r21 ldw 40(%r21),%r20 stw %r20,40(%r19) bl,n L$0116,%r0 L$0118: L$0117: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0115,%r0 L$0116: L$0114: L$0113: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .EXPORT stub_noname_complaint,DATA .align 4 LC$0020: .STRING "stub type has NULL name\x00" .data .align 4 stub_noname_complaint: .word LC$0020 .word 0 .word 0 .IMPORT complain,CODE .IMPORT memcpy,CODE .code .align 4 .EXPORT check_stub_type,CODE .EXPORT check_stub_type,ENTRY,PRIV_LEV=3,ARGW0=GR check_stub_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 ldo 4(%r0),%r21 and %r20,%r21,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0120,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl type_name_no_tag,%r2 nop stw %r28,8(%r4) ldw 8(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0121,%r0 nop addil L'stub_noname_complaint-$global$,%r27 ldo R'stub_noname_complaint-$global$(%r1),%r26 copy %r0,%r25 .CALL ARGW0=GR,ARGW1=GR bl complain,%r2 nop bl,n L$0119,%r0 L$0121: stw %r0,-52(%r30) ldw 8(%r4),%r26 copy %r0,%r25 ldo 2(%r0),%r24 copy %r0,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl lookup_symbol,%r2 nop stw %r28,12(%r4) ldw 12(%r4),%r19 comiclr,<> 0,%r19,%r0 bl L$0122,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 12(%r4),%r20 ldw 0(%r19),%r26 ldw 12(%r20),%r25 ldo 52(%r0),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memcpy,%r2 nop L$0122: L$0120: L$0119: ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT gdb_mangle_name,CODE .IMPORT cplus_demangle,CODE .align 4 LC$0021: .STRING "Internal: Cannot demangle mangled name `%s'.\x00" .IMPORT strchr,CODE .IMPORT parse_and_eval_type,CODE .IMPORT builtin_type_void,DATA .IMPORT free,CODE .align 4 .EXPORT check_stub_method,CODE .EXPORT check_stub_method,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR check_stub_method: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r11,64(%r4) stw %r10,68(%r4) stw %r9,72(%r4) stw %r8,76(%r4) stw %r7,80(%r4) stw %r6,84(%r4) stw %r5,88(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldo -12(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r19),%r26 ldw 0(%r20),%r25 ldw 0(%r21),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl gdb_mangle_name,%r2 nop stw %r28,12(%r4) ldw 12(%r4),%r26 ldo 3(%r0),%r25 .CALL ARGW0=GR,ARGW1=GR bl cplus_demangle,%r2 nop stw %r28,16(%r4) stw %r0,28(%r4) ldo 1(%r0),%r19 stw %r19,32(%r4) ldw 16(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0124,%r0 nop ldil L'LC$0021,%r26 ldo R'LC$0021(%r26),%r26 ldw 12(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop L$0124: ldw 16(%r4),%r26 ldo 40(%r0),%r25 .CALL ARGW0=GR,ARGW1=GR bl strchr,%r2 nop copy %r28,%r19 ldo 1(%r19),%r20 stw %r20,20(%r4) ldw 20(%r4),%r19 stw %r19,24(%r4) L$0125: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 comiclr,<> 0,%r19,%r0 bl L$0126,%r0 nop ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 40(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0127,%r0 nop ldw 28(%r4),%r19 ldo 1(%r19),%r20 stw %r20,28(%r4) bl,n L$0128,%r0 L$0127: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0129,%r0 nop ldw 28(%r4),%r19 ldo -1(%r19),%r20 stw %r20,28(%r4) bl,n L$0130,%r0 L$0129: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 44(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0131,%r0 nop ldw 28(%r4),%r19 comiclr,= 0,%r19,%r0 bl L$0131,%r0 nop ldw 32(%r4),%r19 ldo 1(%r19),%r20 stw %r20,32(%r4) L$0131: L$0130: L$0128: ldw 24(%r4),%r19 ldo 1(%r19),%r20 stw %r20,24(%r4) bl,n L$0125,%r0 L$0126: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0137,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,44(%r4) ldw 44(%r4),%r19 stw %r19,48(%r4) ldw 32(%r4),%r20 ldo 2(%r20),%r19 zdep %r19,29,30,%r20 stw %r20,52(%r4) ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 52(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0132,%r0 nop ldw 48(%r4),%r26 ldw 52(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0133,%r0 L$0132: copy %r0,%r19 L$0133: ldw 48(%r4),%r19 ldw 48(%r4),%r20 ldw 12(%r20),%r21 ldw 52(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 44(%r4),%r19 stw %r19,56(%r4) ldw 56(%r4),%r19 ldw 8(%r19),%r20 stw %r20,60(%r4) ldw 56(%r4),%r19 ldw 12(%r19),%r20 ldw 60(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0134,%r0 nop ldw 56(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0134: ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 56(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 56(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 56(%r4),%r20 ldw 56(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0135,%r0 nop ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0136,%r0 L$0135: copy %r0,%r19 L$0136: ldw 56(%r4),%r19 ldw 56(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 60(%r4),%r11 bl,n L$0138,%r0 L$0137: ldw 32(%r4),%r20 ldo 2(%r20),%r19 zdep %r19,29,30,%r20 copy %r20,%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r11 L$0138: stw %r11,36(%r4) ldw 20(%r4),%r19 stw %r19,24(%r4) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl lookup_pointer_type,%r2 nop copy %r28,%r19 ldw 36(%r4),%r20 stw %r19,0(%r20) ldo 1(%r0),%r19 stw %r19,32(%r4) ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0139,%r0 nop stw %r0,28(%r4) L$0140: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 comiclr,<> 0,%r19,%r0 bl L$0141,%r0 nop ldw 28(%r4),%r19 comiclr,>= 0,%r19,%r0 bl L$0142,%r0 nop ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 44(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0143,%r0 nop ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0143,%r0 nop bl,n L$0142,%r0 L$0143: ldw 24(%r4),%r19 ldw 20(%r4),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r26 copy %r19,%r25 .CALL ARGW0=GR,ARGW1=GR bl parse_and_eval_type,%r2 nop copy %r28,%r19 ldw 32(%r4),%r20 zdep %r20,29,30,%r21 ldw 36(%r4),%r22 add %r21,%r22,%r20 stw %r19,0(%r20) ldw 32(%r4),%r19 ldo 1(%r19),%r20 stw %r20,32(%r4) ldw 24(%r4),%r19 ldo 1(%r19),%r20 stw %r20,20(%r4) L$0142: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 40(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0144,%r0 nop ldw 28(%r4),%r19 ldo 1(%r19),%r20 stw %r20,28(%r4) bl,n L$0145,%r0 L$0144: ldw 24(%r4),%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 41(%r0),%r20 comclr,= %r19,%r20,%r0 bl L$0146,%r0 nop ldw 28(%r4),%r19 ldo -1(%r19),%r20 stw %r20,28(%r4) L$0146: L$0145: ldw 24(%r4),%r19 ldo 1(%r19),%r20 stw %r20,24(%r4) bl,n L$0140,%r0 L$0141: L$0139: ldo -2(%r0),%r19 ldw 24(%r4),%r20 add %r19,%r20,%r19 ldb 0(%r19),%r20 extrs %r20,31,8,%r19 ldo 46(%r0),%r20 comclr,<> %r19,%r20,%r0 bl L$0147,%r0 nop ldw 32(%r4),%r19 zdep %r19,29,30,%r20 ldw 36(%r4),%r21 add %r20,%r21,%r19 addil L'builtin_type_void-$global$,%r27 ldw R'builtin_type_void-$global$(%r1),%r20 stw %r20,0(%r19) bl,n L$0148,%r0 L$0147: ldw 32(%r4),%r19 zdep %r19,29,30,%r20 ldw 36(%r4),%r21 add %r20,%r21,%r19 stw %r0,0(%r19) L$0148: ldw 16(%r4),%r26 .CALL ARGW0=GR bl free,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 zdep %r21,30,31,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 20(%r19),%r21 add %r20,%r21,%r19 ldw 8(%r19),%r20 stw %r20,8(%r4) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 8(%r4),%r20 add %r19,%r20,%r19 ldw 12(%r4),%r20 stw %r20,0(%r19) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 8(%r4),%r20 add %r19,%r20,%r19 ldw 4(%r19),%r20 stw %r20,40(%r4) ldw 40(%r4),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 stw %r21,40(%r19) ldw 40(%r4),%r19 ldw 36(%r4),%r20 stw %r20,48(%r19) ldw 40(%r4),%r19 ldw 40(%r4),%r20 ldh 32(%r20),%r21 copy %r21,%r20 depi 0,29,1,%r20 sth %r20,32(%r19) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 8(%r4),%r20 add %r19,%r20,%r19 ldw 16(%r19),%r20 copy %r20,%r21 depi 0,4,1,%r21 stw %r21,16(%r19) L$0123: ldw 64(%r4),%r11 ldw 68(%r4),%r10 ldw 72(%r4),%r9 ldw 76(%r4),%r8 ldw 80(%r4),%r7 ldw 84(%r4),%r6 ldw 88(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 .EXPORT allocate_cplus_struct_type,CODE .EXPORT allocate_cplus_struct_type,ENTRY,PRIV_LEV=3,ARGW0=GR allocate_cplus_struct_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r8,32(%r4) stw %r7,36(%r4) stw %r6,40(%r4) stw %r5,44(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 comclr,= %r19,%r20,%r0 bl L$0150,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r7 ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0156,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 12(%r19),%r20 ldo 120(%r20),%r19 stw %r19,8(%r4) ldw 8(%r4),%r19 stw %r19,12(%r4) ldo 24(%r0),%r19 stw %r19,16(%r4) ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 16(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0151,%r0 nop ldw 12(%r4),%r26 ldw 16(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0152,%r0 L$0151: copy %r0,%r19 L$0152: ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 12(%r20),%r21 ldw 16(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 8(%r4),%r19 stw %r19,20(%r4) ldw 20(%r4),%r19 ldw 8(%r19),%r20 stw %r20,24(%r4) ldw 20(%r4),%r19 ldw 12(%r19),%r20 ldw 24(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0153,%r0 nop ldw 20(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0153: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 20(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0154,%r0 nop ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0155,%r0 L$0154: copy %r0,%r19 L$0155: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 24(%r4),%r8 bl,n L$0157,%r0 L$0156: ldo 24(%r0),%r26 .CALL ARGW0=GR bl xmalloc,%r2 nop copy %r28,%r8 L$0157: stw %r8,48(%r7) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 copy %r20,%r21 ldws,ma 4(%r22),%r19 ldws,ma 4(%r22),%r20 stws,ma %r19,4(%r21) ldws,ma 4(%r22),%r19 stws,ma %r20,4(%r21) ldws,ma 4(%r22),%r20 stws,ma %r19,4(%r21) ldws,ma 4(%r22),%r19 stws,ma %r20,4(%r21) ldws,ma 4(%r22),%r20 stws,ma %r19,4(%r21) stw %r20,0(%r21) L$0150: L$0149: ldw 32(%r4),%r8 ldw 36(%r4),%r7 ldw 40(%r4),%r6 ldw 44(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT obsavestring,CODE .align 4 .EXPORT init_type,CODE .EXPORT init_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR,RTNVAL=GR init_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r14,8(%r4) stw %r13,12(%r4) stw %r12,16(%r4) stw %r11,20(%r4) stw %r10,24(%r4) stw %r9,28(%r4) stw %r8,32(%r4) stw %r7,36(%r4) stw %r6,40(%r4) stw %r5,44(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -12(%r0),%r9 ldo -32(%r4),%r19 add %r19,%r9,%r10 stw %r24,0(%r10) ldo -16(%r0),%r11 ldo -32(%r4),%r19 add %r19,%r11,%r12 stw %r23,0(%r12) ldo -20(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl alloc_type,%r2 nop copy %r28,%r13 ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,0(%r13) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,8(%r13) ldo -12(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldh 32(%r13),%r20 ldh 2(%r19),%r19 or %r20,%r19,%r20 sth %r20,32(%r13) ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0159,%r0 nop ldo -20(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0159,%r0 nop ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r14 ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r26 .CALL ARGW0=GR bl strlen,%r2 nop copy %r28,%r19 ldo -20(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 120(%r21),%r20 ldw 0(%r14),%r26 copy %r19,%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl obsavestring,%r2 nop copy %r28,%r19 stw %r19,4(%r13) bl,n L$0160,%r0 L$0159: ldo -16(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,4(%r13) L$0160: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 3,%r20,%r0 bl L$0162,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 4,%r20,%r0 bl L$0162,%r0 nop bl,n L$0161,%r0 L$0162: stw %r19,48(%r13) L$0161: copy %r13,%r28 bl,n L$0158,%r0 L$0158: ldw 8(%r4),%r14 ldw 12(%r4),%r13 ldw 16(%r4),%r12 ldw 20(%r4),%r11 ldw 24(%r4),%r10 ldw 28(%r4),%r9 ldw 32(%r4),%r8 ldw 36(%r4),%r7 ldw 40(%r4),%r6 ldw 44(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0022: .STRING "internal error - invalid fundamental type id %d\x00" .align 4 LC$0023: .STRING "internal error: unhandled type id %d\x00" .align 4 LC$0024: .STRING "void\x00" .align 4 LC$0025: .STRING "boolean\x00" .align 4 LC$0026: .STRING "string\x00" .align 4 LC$0027: .STRING "char\x00" .align 4 LC$0028: .STRING "signed char\x00" .align 4 LC$0029: .STRING "unsigned char\x00" .align 4 LC$0030: .STRING "short\x00" .align 4 LC$0031: .STRING "unsigned short\x00" .align 4 LC$0032: .STRING "int\x00" .align 4 LC$0033: .STRING "unsigned int\x00" .align 4 LC$0034: .STRING "fixed decimal\x00" .align 4 LC$0035: .STRING "long\x00" .align 4 LC$0036: .STRING "unsigned long\x00" .align 4 LC$0037: .STRING "long long\x00" .align 4 LC$0038: .STRING "signed long long\x00" .align 4 LC$0039: .STRING "unsigned long long\x00" .align 4 LC$0040: .STRING "float\x00" .align 4 LC$0041: .STRING "double\x00" .align 4 LC$0042: .STRING "floating decimal\x00" .align 4 LC$0043: .STRING "long double\x00" .align 4 LC$0044: .STRING "complex\x00" .align 4 LC$0045: .STRING "double complex\x00" .align 4 LC$0046: .STRING "long double complex\x00" .align 4 .EXPORT lookup_fundamental_type,CODE .EXPORT lookup_fundamental_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR,RTNVAL=GR lookup_fundamental_type: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r12,32(%r4) stw %r11,36(%r4) stw %r10,40(%r4) stw %r9,44(%r4) stw %r8,48(%r4) stw %r7,52(%r4) stw %r6,56(%r4) stw %r5,60(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) copy %r0,%r9 ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<= 0,%r20,%r0 bl L$0165,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 25(%r0),%r19 comclr,<= %r20,%r19,%r0 bl L$0165,%r0 nop bl,n L$0164,%r0 L$0165: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0022,%r26 ldo R'LC$0022(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop bl,n L$0166,%r0 L$0164: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 196(%r19),%r20 comiclr,= 0,%r20,%r0 bl L$0167,%r0 nop ldo 104(%r0),%r11 ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r12 ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo 120(%r19),%r20 stw %r20,8(%r4) ldw 8(%r4),%r19 stw %r19,12(%r4) stw %r11,16(%r4) ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 16(%r19),%r19 ldw 12(%r20),%r20 sub %r19,%r20,%r19 ldw 16(%r4),%r20 comclr,< %r19,%r20,%r0 bl L$0168,%r0 nop ldw 12(%r4),%r26 ldw 16(%r4),%r25 .CALL ARGW0=GR,ARGW1=GR bl _obstack_newchunk,%r2 nop copy %r0,%r19 bl,n L$0169,%r0 L$0168: copy %r0,%r19 L$0169: ldw 12(%r4),%r19 ldw 12(%r4),%r20 ldw 12(%r20),%r21 ldw 16(%r4),%r22 add %r21,%r22,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 8(%r4),%r19 stw %r19,20(%r4) ldw 20(%r4),%r19 ldw 8(%r19),%r20 stw %r20,24(%r4) ldw 20(%r4),%r19 ldw 12(%r19),%r20 ldw 24(%r4),%r19 comclr,= %r20,%r19,%r0 bl L$0170,%r0 nop ldw 20(%r4),%r19 ldw 40(%r19),%r20 copy %r20,%r21 depi -1,1,1,%r21 stw %r21,40(%r19) L$0170: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 12(%r20),%r20 ldw 24(%r21),%r21 add %r20,%r21,%r20 ldw 20(%r4),%r21 ldw 24(%r21),%r22 uaddcm %r0,%r22,%r21 and %r20,%r21,%r20 copy %r20,%r21 stw %r21,12(%r19) ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r19),%r19 ldw 4(%r20),%r20 sub %r19,%r20,%r19 ldw 20(%r4),%r20 ldw 20(%r4),%r21 ldw 16(%r20),%r20 ldw 4(%r21),%r21 sub %r20,%r21,%r20 comclr,> %r19,%r20,%r0 bl L$0171,%r0 nop ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 16(%r20),%r21 stw %r21,12(%r19) copy %r21,%r19 bl,n L$0172,%r0 L$0171: copy %r0,%r19 L$0172: ldw 20(%r4),%r19 ldw 20(%r4),%r20 ldw 12(%r20),%r21 stw %r21,8(%r19) ldw 24(%r4),%r19 stw %r19,196(%r12) ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 196(%r19),%r26 copy %r0,%r25 copy %r11,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl memset,%r2 nop L$0167: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 zdep %r21,29,30,%r20 ldw 196(%r19),%r19 add %r20,%r19,%r10 ldw 0(%r10),%r9 comiclr,= 0,%r9,%r0 bl L$0173,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 addi,uv -26,%r20,%r0 blr,n %r20,%r0 b,n L$0175 L$0202: b L$0176 nop b L$0177 nop b L$0179 nop b L$0180 nop b L$0181 nop b L$0182 nop b L$0183 nop b L$0184 nop b L$0185 nop b L$0186 nop b L$0187 nop b L$0189 nop b L$0190 nop b L$0191 nop b L$0192 nop b L$0193 nop b L$0194 nop b L$0195 nop b L$0196 nop b L$0198 nop b L$0199 nop b L$0200 nop b L$0201 nop b L$0178 nop b L$0188 nop b L$0197 nop L$0175: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldil L'LC$0023,%r26 ldo R'LC$0023(%r26),%r26 ldw 0(%r19),%r25 .CALL ARGW0=GR,ARGW1=GR bl error,%r2 nop bl,n L$0174,%r0 L$0176: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 9(%r0),%r26 ldo 1(%r0),%r25 copy %r0,%r24 ldil L'LC$0024,%r23 ldo R'LC$0024(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0177: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0025,%r23 ldo R'LC$0025(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0178: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 12(%r0),%r26 ldo 1(%r0),%r25 copy %r0,%r24 ldil L'LC$0026,%r23 ldo R'LC$0026(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0179: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 1(%r0),%r25 copy %r0,%r24 ldil L'LC$0027,%r23 ldo R'LC$0027(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0180: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 1(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0028,%r23 ldo R'LC$0028(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0181: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 1(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0029,%r23 ldo R'LC$0029(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0182: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 2(%r0),%r25 copy %r0,%r24 ldil L'LC$0030,%r23 ldo R'LC$0030(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0183: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 2(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0030,%r23 ldo R'LC$0030(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0184: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 2(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0031,%r23 ldo R'LC$0031(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0185: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0032,%r23 ldo R'LC$0032(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0186: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0032,%r23 ldo R'LC$0032(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0187: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0033,%r23 ldo R'LC$0033(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0188: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0034,%r23 ldo R'LC$0034(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0189: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0035,%r23 ldo R'LC$0035(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0190: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0035,%r23 ldo R'LC$0035(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0191: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 4(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0036,%r23 ldo R'LC$0036(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0192: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0037,%r23 ldo R'LC$0037(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0193: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 8(%r0),%r25 ldo 2(%r0),%r24 ldil L'LC$0038,%r23 ldo R'LC$0038(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0194: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 7(%r0),%r26 ldo 8(%r0),%r25 ldo 1(%r0),%r24 ldil L'LC$0039,%r23 ldo R'LC$0039(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0195: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 4(%r0),%r25 copy %r0,%r24 ldil L'LC$0040,%r23 ldo R'LC$0040(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0196: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0041,%r23 ldo R'LC$0041(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0197: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0042,%r23 ldo R'LC$0042(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0198: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 16(%r0),%r25 copy %r0,%r24 ldil L'LC$0043,%r23 ldo R'LC$0043(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0199: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 8(%r0),%r25 copy %r0,%r24 ldil L'LC$0044,%r23 ldo R'LC$0044(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0200: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 16(%r0),%r25 copy %r0,%r24 ldil L'LC$0045,%r23 ldo R'LC$0045(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0201: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 stw %r20,-52(%r30) ldo 8(%r0),%r26 ldo 16(%r0),%r25 copy %r0,%r24 ldil L'LC$0046,%r23 ldo R'LC$0046(%r23),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl init_type,%r2 nop copy %r28,%r9 bl,n L$0174,%r0 L$0174: stw %r9,0(%r10) L$0173: L$0166: copy %r9,%r28 bl,n L$0163,%r0 L$0163: ldw 32(%r4),%r12 ldw 36(%r4),%r11 ldw 40(%r4),%r10 ldw 44(%r4),%r9 ldw 48(%r4),%r8 ldw 52(%r4),%r7 ldw 56(%r4),%r6 ldw 60(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT puts_filtered,CODE .align 4 LC$0047: .STRING " \x00" .IMPORT printf_filtered,CODE .align 4 LC$0048: .STRING "1\x00" .align 4 LC$0049: .STRING "0\x00" .align 4 print_bit_vector: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,16(%r4) stw %r7,20(%r4) stw %r6,24(%r4) stw %r5,28(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) stw %r0,8(%r4) L$0204: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 8(%r4),%r20 ldw 0(%r19),%r19 comclr,< %r20,%r19,%r0 bl L$0205,%r0 nop ldw 8(%r4),%r19 ldw 8(%r4),%r20 comiclr,> 0,%r19,%r0 bl L$0208,%r0 nop ldo 7(%r19),%r19 L$0208: extrs %r19,28,29,%r19 zdep %r19,28,29,%r21 sub %r20,%r21,%r19 comiclr,= 0,%r19,%r0 bl L$0207,%r0 nop ldil L'LC$0047,%r26 ldo R'LC$0047(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0207: ldw 8(%r4),%r20 extrs %r20,28,29,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 add %r19,%r21,%r20 ldb 0(%r20),%r19 ldw 8(%r4),%r20 extru %r20,31,3,%r21 subi,>>= 31,%r21,%r20 copy %r0,%r20 mtsar %r20 vextrs %r19,32,%r19 extru %r19,31,1,%r20 comiclr,<> 0,%r20,%r0 bl L$0209,%r0 nop ldil L'LC$0048,%r26 ldo R'LC$0048(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0210,%r0 L$0209: ldil L'LC$0049,%r26 ldo R'LC$0049(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop L$0210: L$0206: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0204,%r0 L$0205: L$0203: ldw 16(%r4),%r8 ldw 20(%r4),%r7 ldw 24(%r4),%r6 ldw 28(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT recursive_dump_type,CODE .align 4 print_arg_types: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,8(%r4) stw %r7,12(%r4) stw %r6,16(%r4) stw %r5,20(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0212,%r0 nop L$0213: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0214,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 2(%r21),%r20 ldw 0(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 4(%r20),%r21 stw %r21,0(%r19) ldw 0(%r20),%r19 ldw 0(%r19),%r20 comiclr,= 9,%r20,%r0 bl L$0215,%r0 nop bl,n L$0214,%r0 L$0215: bl,n L$0213,%r0 L$0214: L$0212: L$0211: ldw 8(%r4),%r8 ldw 12(%r4),%r7 ldw 16(%r4),%r6 ldw 20(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .IMPORT printfi_filtered,CODE .align 4 LC$0050: .STRING "fn_fieldlists 0x%x\x0a\x00" .align 4 LC$0051: .STRING "[%d] name '%s' (0x%x) length %d\x0a\x00" .align 4 LC$0052: .STRING "[%d] physname '%s' (0x%x)\x0a\x00" .align 4 LC$0053: .STRING "type 0x%x\x0a\x00" .align 4 LC$0054: .STRING "args 0x%x\x0a\x00" .align 4 LC$0055: .STRING "fcontext 0x%x\x0a\x00" .align 4 LC$0056: .STRING "is_const %d\x0a\x00" .align 4 LC$0057: .STRING "is_volatile %d\x0a\x00" .align 4 LC$0058: .STRING "is_private %d\x0a\x00" .align 4 LC$0059: .STRING "is_protected %d\x0a\x00" .align 4 LC$0060: .STRING "is_stub %d\x0a\x00" .align 4 LC$0061: .STRING "voffset %u\x0a\x00" .align 4 dump_fn_fieldlists: .PROC .CALLINFO FRAME=192,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,192(%r30) stw %r8,24(%r4) stw %r7,28(%r4) stw %r6,32(%r4) stw %r5,36(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldw 48(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0050,%r25 ldo R'LC$0050(%r25),%r25 ldw 20(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop stw %r0,8(%r4) L$0217: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 2(%r20),%r21 extrs %r21,31,16,%r19 ldw 8(%r4),%r20 comclr,< %r20,%r19,%r0 bl L$0218,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldw 8(%r4),%r21 zdep %r21,30,31,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 20(%r19),%r21 add %r20,%r21,%r19 ldw 8(%r19),%r20 stw %r20,16(%r4) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 2(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldw 48(%r21),%r20 ldw 8(%r4),%r22 zdep %r22,30,31,%r21 add %r21,%r22,%r21 zdep %r21,29,30,%r21 ldw 20(%r20),%r22 add %r21,%r22,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 8(%r4),%r23 zdep %r23,30,31,%r22 add %r22,%r23,%r22 zdep %r22,29,30,%r22 ldw 20(%r21),%r23 add %r22,%r23,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 8(%r4),%r23 zdep %r23,30,31,%r22 add %r22,%r23,%r22 zdep %r22,29,30,%r22 ldw 20(%r21),%r23 add %r22,%r23,%r21 ldw 4(%r21),%r22 stw %r22,-56(%r30) copy %r19,%r26 ldil L'LC$0051,%r25 ldo R'LC$0051(%r25),%r25 ldw 8(%r4),%r24 ldw 0(%r20),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop stw %r0,12(%r4) L$0220: ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldw 8(%r4),%r21 zdep %r21,30,31,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 20(%r19),%r21 add %r20,%r21,%r19 ldw 12(%r4),%r20 ldw 4(%r19),%r19 comclr,< %r20,%r19,%r0 bl L$0221,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 4(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 12(%r4),%r22 zdep %r22,29,30,%r21 add %r21,%r22,%r21 zdep %r21,29,30,%r21 ldw 16(%r4),%r22 add %r21,%r22,%r21 ldw 0(%r21),%r22 stw %r22,-52(%r30) copy %r19,%r26 ldil L'LC$0052,%r25 ldo R'LC$0052(%r25),%r25 ldw 12(%r4),%r24 ldw 0(%r20),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 copy %r19,%r26 ldil L'LC$0053,%r25 ldo R'LC$0053(%r25),%r25 ldw 4(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldw 12(%r4),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 16(%r4),%r20 add %r19,%r20,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 10(%r21),%r20 ldw 4(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r22 add %r20,%r22,%r21 ldw 4(%r21),%r20 copy %r19,%r26 ldil L'LC$0054,%r25 ldo R'LC$0054(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldw 12(%r4),%r20 zdep %r20,29,30,%r19 add %r19,%r20,%r19 zdep %r19,29,30,%r19 ldw 16(%r4),%r21 add %r19,%r21,%r20 ldw 4(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 48(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl print_arg_types,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 copy %r19,%r26 ldil L'LC$0055,%r25 ldo R'LC$0055(%r25),%r25 ldw 12(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,0+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0056,%r25 ldo R'LC$0056(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,1+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0057,%r25 ldo R'LC$0057(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,2+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0058,%r25 ldo R'LC$0058(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,3+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0059,%r25 ldo R'LC$0059(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,4+1-1,1,%r20 copy %r19,%r26 ldil L'LC$0060,%r25 ldo R'LC$0060(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 8(%r20),%r19 ldw 12(%r4),%r21 zdep %r21,29,30,%r20 add %r20,%r21,%r20 zdep %r20,29,30,%r20 ldw 16(%r4),%r21 add %r20,%r21,%r20 ldw 16(%r20),%r21 extru %r21,8+24-1,24,%r22 ldo -2(%r22),%r20 copy %r19,%r26 ldil L'LC$0061,%r25 ldo R'LC$0061(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop L$0222: ldw 12(%r4),%r19 ldo 1(%r19),%r20 stw %r20,12(%r4) bl,n L$0220,%r0 L$0221: L$0219: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0217,%r0 L$0218: L$0216: ldw 24(%r4),%r8 ldw 28(%r4),%r7 ldw 32(%r4),%r6 ldw 36(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0062: .STRING "n_baseclasses %d\x0a\x00" .align 4 LC$0063: .STRING "nfn_fields %d\x0a\x00" .align 4 LC$0064: .STRING "nfn_fields_total %d\x0a\x00" .align 4 LC$0065: .STRING "virtual_field_bits (%d bits at *0x%x)\x00" .align 4 LC$0066: .STRING "\x0a\x00" .align 4 LC$0067: .STRING "private_field_bits (%d bits at *0x%x)\x00" .align 4 LC$0068: .STRING "protected_field_bits (%d bits at *0x%x)\x00" .align 4 print_cplus_stuff: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,16(%r4) stw %r7,20(%r4) stw %r6,24(%r4) stw %r5,28(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 0(%r21),%r22 extrs %r22,31,16,%r20 ldw 0(%r19),%r26 ldil L'LC$0062,%r25 ldo R'LC$0062(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 2(%r21),%r22 extrs %r22,31,16,%r20 ldw 0(%r19),%r26 ldil L'LC$0063,%r25 ldo R'LC$0063(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldw 48(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0064,%r25 ldo R'LC$0064(%r25),%r25 ldw 4(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 0(%r20),%r21 extrs %r21,31,16,%r19 comiclr,< 0,%r19,%r0 bl L$0224,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 0(%r21),%r22 extrs %r22,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0065,%r25 ldo R'LC$0065(%r25),%r25 copy %r20,%r24 ldw 8(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 48(%r20),%r21 ldh 0(%r21),%r22 extrs %r22,31,16,%r20 ldw 8(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl print_bit_vector,%r2 nop ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0224: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 34(%r19),%r20 extrs %r20,31,16,%r19 comiclr,< 0,%r19,%r0 bl L$0225,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldw 12(%r20),%r19 comiclr,<> 0,%r19,%r0 bl L$0226,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0067,%r25 ldo R'LC$0067(%r25),%r25 copy %r20,%r24 ldw 12(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldw 12(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl print_bit_vector,%r2 nop ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0226: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldw 16(%r20),%r19 comiclr,<> 0,%r19,%r0 bl L$0227,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 48(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0068,%r25 ldo R'LC$0068(%r25),%r25 copy %r20,%r24 ldw 16(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 48(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldw 16(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl print_bit_vector,%r2 nop ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0227: L$0225: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 ldh 2(%r20),%r21 extrs %r21,31,16,%r19 comiclr,< 0,%r19,%r0 bl L$0228,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl dump_fn_fieldlists,%r2 nop L$0228: L$0223: ldw 16(%r4),%r8 ldw 20(%r4),%r7 ldw 24(%r4),%r6 ldw 28(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND .align 4 LC$0069: .STRING "type node 0x%x\x0a\x00" .align 4 LC$0070: .STRING "name '%s' (0x%x)\x0a\x00" .align 4 LC$0071: .STRING "<NULL>\x00" .align 4 LC$0072: .STRING "code 0x%x \x00" .align 4 LC$0073: .STRING "(TYPE_CODE_UNDEF)\x00" .align 4 LC$0074: .STRING "(TYPE_CODE_PTR)\x00" .align 4 LC$0075: .STRING "(TYPE_CODE_ARRAY)\x00" .align 4 LC$0076: .STRING "(TYPE_CODE_STRUCT)\x00" .align 4 LC$0077: .STRING "(TYPE_CODE_UNION)\x00" .align 4 LC$0078: .STRING "(TYPE_CODE_ENUM)\x00" .align 4 LC$0079: .STRING "(TYPE_CODE_FUNC)\x00" .align 4 LC$0080: .STRING "(TYPE_CODE_INT)\x00" .align 4 LC$0081: .STRING "(TYPE_CODE_FLT)\x00" .align 4 LC$0082: .STRING "(TYPE_CODE_VOID)\x00" .align 4 LC$0083: .STRING "(TYPE_CODE_SET)\x00" .align 4 LC$0084: .STRING "(TYPE_CODE_RANGE)\x00" .align 4 LC$0085: .STRING "(TYPE_CODE_PASCAL_ARRAY)\x00" .align 4 LC$0086: .STRING "(TYPE_CODE_ERROR)\x00" .align 4 LC$0087: .STRING "(TYPE_CODE_MEMBER)\x00" .align 4 LC$0088: .STRING "(TYPE_CODE_METHOD)\x00" .align 4 LC$0089: .STRING "(TYPE_CODE_REF)\x00" .align 4 LC$0090: .STRING "(TYPE_CODE_CHAR)\x00" .align 4 LC$0091: .STRING "(TYPE_CODE_BOOL)\x00" .align 4 LC$0092: .STRING "(UNKNOWN TYPE CODE)\x00" .align 4 LC$0093: .STRING "length %d\x0a\x00" .align 4 LC$0094: .STRING "objfile 0x%x\x0a\x00" .align 4 LC$0095: .STRING "target_type 0x%x\x0a\x00" .align 4 LC$0096: .STRING "pointer_type 0x%x\x0a\x00" .align 4 LC$0097: .STRING "reference_type 0x%x\x0a\x00" .align 4 LC$0098: .STRING "function_type 0x%x\x0a\x00" .align 4 LC$0099: .STRING "flags 0x%x\x00" .align 4 LC$0100: .STRING " TYPE_FLAG_UNSIGNED\x00" .align 4 LC$0101: .STRING " TYPE_FLAG_SIGNED\x00" .align 4 LC$0102: .STRING " TYPE_FLAG_STUB\x00" .align 4 LC$0103: .STRING "nfields %d 0x%x\x0a\x00" .align 4 LC$0104: .STRING "[%d] bitpos %d bitsize %d type 0x%x name '%s' (0x%x)\x0a\x00" .align 4 LC$0105: .STRING "vptr_basetype 0x%x\x0a\x00" .align 4 LC$0106: .STRING "vptr_fieldno %d\x0a\x00" .align 4 LC$0107: .STRING "arg_types 0x%x\x0a\x00" .align 4 LC$0108: .STRING "cplus_stuff 0x%x\x0a\x00" .align 4 LC$0109: .STRING "type_specific 0x%x\x00" .align 4 LC$0110: .STRING " (unknown data form)\x00" .align 4 .EXPORT recursive_dump_type,CODE .EXPORT recursive_dump_type,ENTRY,PRIV_LEV=3,ARGW0=GR,ARGW1=GR recursive_dump_type: .PROC .CALLINFO FRAME=128,CALLS,SAVE_RP .ENTRY stw %r2,-20(%r30) copy %r4,%r1 copy %r30,%r4 stwm %r1,128(%r30) stw %r8,16(%r4) stw %r7,20(%r4) stw %r6,24(%r4) stw %r5,28(%r4) ldo -4(%r0),%r5 ldo -32(%r4),%r19 add %r19,%r5,%r6 stw %r26,0(%r6) ldo -8(%r0),%r7 ldo -32(%r4),%r19 add %r19,%r7,%r8 stw %r25,0(%r8) ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r19),%r26 ldil L'LC$0069,%r25 ldo R'LC$0069(%r25),%r25 ldw 0(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r22 add %r22,%r21,%r21 ldw 0(%r21),%r22 ldw 4(%r22),%r21 ldo -4(%r0),%r22 ldo -32(%r4),%r24 add %r24,%r22,%r23 ldw 0(%r23),%r22 ldw 4(%r22),%r23 comiclr,= 0,%r23,%r0 bl L$0230,%r0 nop ldil L'LC$0071,%r21 ldo R'LC$0071(%r21),%r21 L$0230: ldw 0(%r19),%r26 ldil L'LC$0070,%r25 ldo R'LC$0070(%r25),%r25 ldw 4(%r20),%r24 copy %r21,%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0072,%r25 ldo R'LC$0072(%r25),%r25 ldw 0(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 0(%r19),%r20 addi,uv -19,%r20,%r0 blr,n %r20,%r0 b,n L$0251 L$0252: b L$0232 nop b L$0233 nop b L$0234 nop b L$0235 nop b L$0236 nop b L$0237 nop b L$0238 nop b L$0239 nop b L$0240 nop b L$0241 nop b L$0242 nop b L$0243 nop b L$0244 nop b L$0245 nop b L$0246 nop b L$0247 nop b L$0248 nop b L$0249 nop b L$0250 nop L$0232: ldil L'LC$0073,%r26 ldo R'LC$0073(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0233: ldil L'LC$0074,%r26 ldo R'LC$0074(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0234: ldil L'LC$0075,%r26 ldo R'LC$0075(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0235: ldil L'LC$0076,%r26 ldo R'LC$0076(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0236: ldil L'LC$0077,%r26 ldo R'LC$0077(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0237: ldil L'LC$0078,%r26 ldo R'LC$0078(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0238: ldil L'LC$0079,%r26 ldo R'LC$0079(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0239: ldil L'LC$0080,%r26 ldo R'LC$0080(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0240: ldil L'LC$0081,%r26 ldo R'LC$0081(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0241: ldil L'LC$0082,%r26 ldo R'LC$0082(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0242: ldil L'LC$0083,%r26 ldo R'LC$0083(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0243: ldil L'LC$0084,%r26 ldo R'LC$0084(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0244: ldil L'LC$0085,%r26 ldo R'LC$0085(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0245: ldil L'LC$0086,%r26 ldo R'LC$0086(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0246: ldil L'LC$0087,%r26 ldo R'LC$0087(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0247: ldil L'LC$0088,%r26 ldo R'LC$0088(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0248: ldil L'LC$0089,%r26 ldo R'LC$0089(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0249: ldil L'LC$0090,%r26 ldo R'LC$0090(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0250: ldil L'LC$0091,%r26 ldo R'LC$0091(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0251: ldil L'LC$0092,%r26 ldo R'LC$0092(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0231,%r0 L$0231: ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0093,%r25 ldo R'LC$0093(%r25),%r25 ldw 8(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0094,%r25 ldo R'LC$0094(%r25),%r25 ldw 12(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0095,%r25 ldo R'LC$0095(%r25),%r25 ldw 16(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 16(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0253,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 2(%r21),%r20 ldw 16(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop L$0253: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0096,%r25 ldo R'LC$0096(%r25),%r25 ldw 20(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0097,%r25 ldo R'LC$0097(%r25),%r25 ldw 24(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0098,%r25 ldo R'LC$0098(%r25),%r25 ldw 28(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 32(%r20),%r21 extrs %r21,31,16,%r20 ldw 0(%r19),%r26 ldil L'LC$0099,%r25 ldo R'LC$0099(%r25),%r25 copy %r20,%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 extru %r20,31,1,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0254,%r0 nop ldil L'LC$0100,%r26 ldo R'LC$0100(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0254: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 ldo 2(%r0),%r21 and %r20,%r21,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0255,%r0 nop ldil L'LC$0101,%r26 ldo R'LC$0101(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0255: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 32(%r19),%r20 ldo 4(%r0),%r21 and %r20,%r21,%r19 extrs %r19,31,16,%r20 comiclr,<> 0,%r20,%r0 bl L$0256,%r0 nop ldil L'LC$0102,%r26 ldo R'LC$0102(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop L$0256: ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl puts_filtered,%r2 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldh 34(%r20),%r21 extrs %r21,31,16,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 0(%r19),%r26 ldil L'LC$0103,%r25 ldo R'LC$0103(%r25),%r25 copy %r20,%r24 ldw 36(%r21),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop stw %r0,8(%r4) L$0257: ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldh 34(%r19),%r20 extrs %r20,31,16,%r19 ldw 8(%r4),%r20 comclr,< %r20,%r19,%r0 bl L$0258,%r0 nop ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldo 2(%r20),%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 8(%r4),%r21 zdep %r21,27,28,%r22 ldw 36(%r20),%r21 add %r22,%r21,%r20 ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 4(%r21),%r22 stw %r22,-52(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 8(%r21),%r22 stw %r22,-56(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 12(%r21),%r22 stw %r22,-60(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 12(%r21),%r22 stw %r22,-64(%r30) ldo -4(%r0),%r21 ldo -32(%r4),%r23 add %r23,%r21,%r22 ldw 0(%r22),%r21 ldw 8(%r4),%r22 zdep %r22,27,28,%r23 ldw 36(%r21),%r22 add %r23,%r22,%r21 ldw 12(%r21),%r22 comiclr,= 0,%r22,%r0 bl L$0260,%r0 nop ldil L'LC$0071,%r21 ldo R'LC$0071(%r21),%r21 stw %r21,-64(%r30) L$0260: copy %r19,%r26 ldil L'LC$0104,%r25 ldo R'LC$0104(%r25),%r25 ldw 8(%r4),%r24 ldw 0(%r20),%r23 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR,ARGW3=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldw 8(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0261,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 8(%r4),%r20 zdep %r20,27,28,%r21 ldw 36(%r19),%r20 add %r21,%r20,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 4(%r21),%r20 ldw 8(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop L$0261: L$0259: ldw 8(%r4),%r19 ldo 1(%r19),%r20 stw %r20,8(%r4) bl,n L$0257,%r0 L$0258: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0105,%r25 ldo R'LC$0105(%r25),%r25 ldw 40(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 40(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0262,%r0 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r20),%r21 ldo 2(%r21),%r20 ldw 40(%r19),%r26 copy %r20,%r25 .CALL ARGW0=GR,ARGW1=GR bl recursive_dump_type,%r2 nop L$0262: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0106,%r25 ldo R'LC$0106(%r25),%r25 ldw 44(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldw 0(%r19),%r20 ldw 0(%r20),%r19 comiclr,<> 6,%r19,%r0 bl L$0265,%r0 nop comiclr,>= 6,%r19,%r0 bl L$0270,%r0 nop comiclr,<> 3,%r19,%r0 bl L$0266,%r0 nop bl,n L$0267,%r0 L$0270: comiclr,<> 15,%r19,%r0 bl L$0264,%r0 nop bl,n L$0267,%r0 L$0264: L$0265: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0107,%r25 ldo R'LC$0107(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 48(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl print_arg_types,%r2 nop bl,n L$0263,%r0 L$0266: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0108,%r25 ldo R'LC$0108(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -8(%r0),%r20 ldo -32(%r4),%r21 add %r21,%r20,%r20 ldw 0(%r19),%r26 ldw 0(%r20),%r25 .CALL ARGW0=GR,ARGW1=GR bl print_cplus_stuff,%r2 nop bl,n L$0263,%r0 L$0267: ldo -8(%r0),%r19 ldo -32(%r4),%r20 add %r20,%r19,%r19 ldo -4(%r0),%r20 ldo -32(%r4),%r22 add %r22,%r20,%r21 ldw 0(%r21),%r20 ldw 0(%r19),%r26 ldil L'LC$0109,%r25 ldo R'LC$0109(%r25),%r25 ldw 48(%r20),%r24 .CALL ARGW0=GR,ARGW1=GR,ARGW2=GR bl printfi_filtered,%r2 nop ldo -4(%r0),%r19 ldo -32(%r4),%r21 add %r21,%r19,%r20 ldw 0(%r20),%r19 ldw 48(%r19),%r20 comiclr,<> 0,%r20,%r0 bl L$0268,%r0 nop ldil L'LC$0110,%r26 ldo R'LC$0110(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop L$0268: ldil L'LC$0066,%r26 ldo R'LC$0066(%r26),%r26 .CALL ARGW0=GR bl printf_filtered,%r2 nop bl,n L$0263,%r0 L$0263: L$0229: ldw 16(%r4),%r8 ldw 20(%r4),%r7 ldw 24(%r4),%r6 ldw 28(%r4),%r5 ldo 8(%r4),%r30 ldw -28(%r30),%r2 bv %r0(%r2) ldwm -8(%r30),%r4 .EXIT .PROCEND

stsp/binutils-ia16

4,410

gas/testsuite/gas/i386/ilp32/reloc64.s

.macro bad args:vararg .ifdef _bad_ \args .endif .endm .macro ill args:vararg # This is used to mark entries that aren't handled consistently, # and thus shouldn't currently be checked for. # \args .endm .text _start: add $xtrn, %rax mov $xtrn, %eax mov $xtrn, %ax mov $xtrn, %al mov xtrn(%rbx), %eax mov xtrn(%ebx), %eax add $(xtrn - .), %rax ill mov $(xtrn - .), %eax mov $(xtrn - .), %ax mov $(xtrn - .), %al mov xtrn(%rip), %eax mov xtrn(%eip), %eax call xtrn jrcxz xtrn add $xtrn@got, %rax mov $xtrn@got, %eax bad mov $xtrn@got, %ax bad mov $xtrn@got, %al mov xtrn@got(%rbx), %eax mov xtrn@got(%ebx), %eax bad call xtrn@got bad add $xtrn@gotoff, %rax bad mov $xtrn@gotoff, %eax bad mov $xtrn@gotoff, %ax bad mov $xtrn@gotoff, %al bad mov xtrn@gotoff(%rbx), %eax bad mov xtrn@gotoff(%ebx), %eax bad call xtrn@gotoff bad movabs $xtrn@gotpcrel, %rax add $xtrn@gotpcrel, %rax mov $xtrn@gotpcrel, %eax bad mov $xtrn@gotpcrel, %ax bad mov $xtrn@gotpcrel, %al mov xtrn@gotpcrel(%rbx), %eax mov xtrn@gotpcrel(%ebx), %eax call xtrn@gotpcrel ill movabs $_GLOBAL_OFFSET_TABLE_, %rax add $_GLOBAL_OFFSET_TABLE_, %rax ill add $_GLOBAL_OFFSET_TABLE_, %eax ill add $_GLOBAL_OFFSET_TABLE_, %ax ill add $_GLOBAL_OFFSET_TABLE_, %al lea _GLOBAL_OFFSET_TABLE_(%rip), %rax lea _GLOBAL_OFFSET_TABLE_(%eip), %rax ill movabs $(_GLOBAL_OFFSET_TABLE_ - .), %rax add $(_GLOBAL_OFFSET_TABLE_ - .), %rax ill add $(_GLOBAL_OFFSET_TABLE_ - .), %eax ill add $(_GLOBAL_OFFSET_TABLE_ - .), %ax ill add $(_GLOBAL_OFFSET_TABLE_ - .), %al bad movabs $xtrn@plt, %rax add $xtrn@plt, %rax mov $xtrn@plt, %eax bad mov $xtrn@plt, %ax bad mov $xtrn@plt, %al mov xtrn@plt(%rbx), %eax mov xtrn@plt(%ebx), %eax call xtrn@plt bad jrcxz xtrn@plt bad movabs $xtrn@tlsgd, %rax add $xtrn@tlsgd, %rax mov $xtrn@tlsgd, %eax bad mov $xtrn@tlsgd, %ax bad mov $xtrn@tlsgd, %al mov xtrn@tlsgd(%rbx), %eax mov xtrn@tlsgd(%ebx), %eax call xtrn@tlsgd bad movabs $xtrn@gottpoff, %rax add $xtrn@gottpoff, %rax mov $xtrn@gottpoff, %eax bad mov $xtrn@gottpoff, %ax bad mov $xtrn@gottpoff, %al mov xtrn@gottpoff(%rbx), %eax mov xtrn@gottpoff(%ebx), %eax call xtrn@gottpoff bad movabs $xtrn@tlsld, %rax add $xtrn@tlsld, %rax mov $xtrn@tlsld, %eax bad mov $xtrn@tlsld, %ax bad mov $xtrn@tlsld, %al mov xtrn@tlsld(%rbx), %eax mov xtrn@tlsld(%ebx), %eax call xtrn@tlsld add $xtrn@dtpoff, %rax mov $xtrn@dtpoff, %eax bad mov $xtrn@dtpoff, %ax bad mov $xtrn@dtpoff, %al mov xtrn@dtpoff(%rbx), %eax mov xtrn@dtpoff(%ebx), %eax bad call xtrn@dtpoff add $xtrn@tpoff, %rax mov $xtrn@tpoff, %eax bad mov $xtrn@tpoff, %ax bad mov $xtrn@tpoff, %al mov xtrn@tpoff(%rbx), %eax mov xtrn@tpoff(%ebx), %eax bad call xtrn@tpoff .data .long xtrn .long xtrn - . .long xtrn@got bad .long xtrn@gotoff .long xtrn@gotpcrel .long _GLOBAL_OFFSET_TABLE_ .long _GLOBAL_OFFSET_TABLE_ - . .long xtrn@plt .long xtrn@tlsgd .long xtrn@gottpoff .long xtrn@tlsld .long xtrn@dtpoff .long xtrn@tpoff .slong xtrn .slong xtrn - . .slong xtrn@got bad .slong xtrn@gotoff .slong xtrn@gotpcrel .slong _GLOBAL_OFFSET_TABLE_ .slong _GLOBAL_OFFSET_TABLE_ - . .slong xtrn@plt .slong xtrn@tlsgd .slong xtrn@gottpoff .slong xtrn@tlsld .slong xtrn@dtpoff .slong xtrn@tpoff .word xtrn .word xtrn - . bad .word xtrn@got bad .word xtrn@gotoff bad .word xtrn@gotpcrel ill .word _GLOBAL_OFFSET_TABLE_ ill .word _GLOBAL_OFFSET_TABLE_ - . bad .word xtrn@plt bad .word xtrn@tlsgd bad .word xtrn@gottpoff bad .word xtrn@tlsld bad .word xtrn@dtpoff bad .word xtrn@tpoff .byte xtrn .byte xtrn - . bad .byte xtrn@got bad .byte xtrn@gotoff bad .byte xtrn@gotpcrel ill .byte _GLOBAL_OFFSET_TABLE_ ill .byte _GLOBAL_OFFSET_TABLE_ - . bad .byte xtrn@plt bad .byte xtrn@tlsgd bad .byte xtrn@gottpoff bad .byte xtrn@tlsld bad .byte xtrn@dtpoff bad .byte xtrn@tpoff .text mov xtrn@tpoff (%rbx), %eax movabsq $xtrn + 0x7fffffff, %rbx movabsq $xtrn - 0x80000000, %rbp .data .quad xtrn .quad xtrn + 0x7fffffff .quad xtrn - 0x80000000 .long xtrn@got - 4 .long xtrn@got + 4 bad .long xtrn@plt - . .text bad add $x+0x123456789, %rax bad add $x+0x123456789, %eax bad add x+0x123456789, %eax bad add x+0x123456789(%eax), %eax bad enter $x+0x123456789, $x+0x123456789 bad enter $x+0x12345, $x+0x123 .data bad .long x+0x123456789 bad .word x+0x123456789 bad .word x+0x12345 bad .byte x+0x123456789 bad .byte x+0x123

stsp/binutils-ia16

5,599

gas/testsuite/gas/i386/ilp32/x86-64.s

.text .intel_syntax noprefix # REX prefix and addressing modes. add edx,ecx add edx,r9d add r10d,ecx add rdx,rcx add r10,r9 add r8d,eax add r8w,ax add r8,rax add eax,0x44332211 add rax,0xfffffffff4332211 add ax,0x4433 add rax,0x44332211 add dl,cl add bh,dh add dil,sil add r15b,sil add dil,r14b add r15b,r14b PUSH RAX PUSH R8 POP R9 ADD AL,0x11 ADD AH,0x11 ADD SPL,0x11 ADD R8B,0x11 ADD R12B,0x11 MOV RAX,CR0 MOV R8,CR0 MOV RAX,CR8 MOV CR8,RAX REP MOVSQ #[RSI],[RDI] REP MOVSW #[RSI,[RDI] REP MOVSQ #[RSI],[RDI] MOV AL, 0x11 MOV AH, 0x11 MOV SPL, 0x11 MOV R12B, 0x11 MOV EAX,0x11223344 MOV R8D,0x11223344 MOV RAX,0x1122334455667788 MOV R8,0x1122334455667788 add eax,[rax] ADD EAX,[R8] ADD R8D,[R8] ADD RAX,[R8] ADD EAX,[0x22222222+RIP] ADD EAX,[RBP+0x00] ADD EAX,FLAT:[0x22222222] ADD EAX,[R13+0] ADD EAX,[RAX+RAX*4] ADD EAX,[R8+RAX*4] ADD R8D,[R8+RAX*4] ADD EAX,[R8+R8*4] ADD [RCX+R8*4],R8D ADD EDX,[RAX+RAX*8] ADD EDX,[RAX+RCX*8] ADD EDX,[RAX+RDX*8] ADD EDX,[RAX+RBX*8] ADD EDX,[RAX] ADD EDX,[RAX+RBP*8] ADD EDX,[RAX+RSI*8] ADD EDX,[RAX+RDI*8] ADD EDX,[RAX+R8*8] ADD EDX,[RAX+R9*8] ADD EDX,[RAX+R10*8] ADD EDX,[RAX+R11*8] ADD EDX,[RAX+R12*8] ADD EDX,[RAX+R13*8] ADD EDX,[RAX+R14*8] ADD EDX,[RAX+R15*8] ADD ECX,0x11 ADD DWORD PTR [RAX],0x11 ADD QWORD PTR [RAX],0x11 ADD DWORD PTR [R8],0x11 ADD DWORD PTR [RCX+RAX*4],0x11 ADD DWORD PTR [R9+RAX*4],0x11 ADD DWORD PTR [RCX+R8*4],0x11 ADD DWORD PTR [0x22222222+RIP],0x33 ADD QWORD PTR [RIP+0x22222222],0x33 ADD DWORD PTR [RIP+0x22222222],0x33333333 ADD QWORD PTR [RIP+0x22222222],0x33333333 ADD DWORD PTR [RAX*8+0x22222222],0x33 ADD DWORD PTR [RAX+0x22222222],0x33 ADD DWORD PTR [RAX+0x22222222],0x33 ADD DWORD PTR [R8+RBP*8],0x33 ADD DWORD PTR FLAT:[0x22222222],0x33 #new instructions MOV AL,FLAT:[0x8877665544332211] MOV EAX,FLAT:[0x8877665544332211] MOV FLAT:[0x8877665544332211],AL MOV FLAT:[0x8877665544332211],EAX MOV RAX,FLAT:[0x8877665544332211] MOV FLAT:[0x8877665544332211],RAX cqo cdqe movsx rax, eax movsx rax, ax movsx rax, al bar: .att_syntax #testcase for symbol references. #immediates - various sizes: mov $symbol, %al mov $symbol, %ax mov $symbol, %eax mov $symbol, %rax #addressing modes: #absolute 32bit addressing mov symbol, %eax #arithmetic mov symbol(%rax), %eax #RIP relative mov symbol(%rip), %eax .intel_syntax noprefix #immediates - various sizes: mov al, offset flat:symbol mov ax, offset flat:symbol mov eax, offset flat:symbol mov rax, offset flat:symbol #parts aren't supported by the parser, yet (and not at all for symbol refs) #mov eax, high part symbol #mov eax, low part symbol #addressing modes #absolute 32bit addressing mov eax, [symbol] #arithmetic mov eax, [rax+symbol] #RIP relative mov eax, [rip+symbol] foo: .att_syntax #absolute 64bit addressing mov 0x8877665544332211,%al mov 0x8877665544332211,%ax mov 0x8877665544332211,%eax mov 0x8877665544332211,%rax mov %al,0x8877665544332211 mov %ax,0x8877665544332211 mov %eax,0x8877665544332211 mov %rax,0x8877665544332211 movb 0x8877665544332211,%al movw 0x8877665544332211,%ax movl 0x8877665544332211,%eax movq 0x8877665544332211,%rax movb %al,0x8877665544332211 movw %ax,0x8877665544332211 movl %eax,0x8877665544332211 movq %rax,0x8877665544332211 #absolute signed 32bit addressing mov 0xffffffffff332211,%al mov 0xffffffffff332211,%ax mov 0xffffffffff332211,%eax mov 0xffffffffff332211,%rax mov %al,0xffffffffff332211 mov %ax,0xffffffffff332211 mov %eax,0xffffffffff332211 mov %rax,0xffffffffff332211 movb 0xffffffffff332211,%al movw 0xffffffffff332211,%ax movl 0xffffffffff332211,%eax movq 0xffffffffff332211,%rax movb %al,0xffffffffff332211 movw %ax,0xffffffffff332211 movl %eax,0xffffffffff332211 movq %rax,0xffffffffff332211 cmpxchg16b (%rax) .intel_syntax noprefix cmpxchg16b oword ptr [rax] .att_syntax movsx %al, %si movsx %al, %esi movsx %al, %rsi movsx %ax, %esi movsx %ax, %rsi movsx %eax, %rsi movsx (%rax), %dx movsbl (%rax), %edx movsbq (%rax), %rdx movsbw (%rax), %dx movswl (%rax), %edx movswq (%rax), %rdx movzx %al, %si movzx %al, %esi movzx %al, %rsi movzx %ax, %esi movzx %ax, %rsi movzx (%rax), %dx movzb (%rax), %edx movzb (%rax), %rdx movzb (%rax), %dx movzbl (%rax), %edx movzbq (%rax), %rdx movzbw (%rax), %dx movzwl (%rax), %edx movzwq (%rax), %rdx .intel_syntax noprefix movsx si,al movsx esi,al movsx rsi,al movsx esi,ax movsx rsi,ax movsx rsi,eax movsx edx,BYTE PTR [rax] movsx rdx,BYTE PTR [rax] movsx dx,BYTE PTR [rax] movsx edx,WORD PTR [rax] movsx rdx,WORD PTR [rax] movzx si,al movzx esi,al movzx rsi,al movzx esi,ax movzx rsi,ax movzx edx,BYTE PTR [rax] movzx rdx,BYTE PTR [rax] movzx dx,BYTE PTR [rax] movzx edx,WORD PTR [rax] movzx rdx,WORD PTR [rax] movq xmm1,QWORD PTR [rsp] movq xmm1,[rsp] movq QWORD PTR [rsp],xmm1 movq [rsp],xmm1 .att_syntax fnstsw fnstsw %ax fstsw fstsw %ax .intel_syntax noprefix fnstsw fnstsw ax fstsw fstsw ax .att_syntax movsx (%rax),%ax movsxb (%rax), %dx movsxb (%rax), %edx movsxb (%rax), %rdx movsxw (%rax), %edx movsxw (%rax), %rdx movsxl (%rax), %rdx movsxd (%rax),%rax movzx (%rax),%ax movzxb (%rax), %dx movzxb (%rax), %edx movzxb (%rax), %rdx movzxw (%rax), %edx movzxw (%rax), %rdx movnti %eax, (%rax) movntil %eax, (%rax) movnti %rax, (%rax) movntiq %rax, (%rax) .intel_syntax noprefix movsx ax, BYTE PTR [rax] movsx eax, BYTE PTR [rax] movsx eax, WORD PTR [rax] movsx rax, WORD PTR [rax] movsx rax, DWORD PTR [rax] movsxd rax, [rax] movzx ax, BYTE PTR [rax] movzx eax, BYTE PTR [rax] movzx eax, WORD PTR [rax] movzx rax, WORD PTR [rax] movnti dword ptr [rax], eax movnti qword ptr [rax], rax

stsp/binutils-ia16

4,519

binutils/testsuite/binutils-all/dw2-compressed.S

/* This testcase is derived from a similar test in GDB. Copyright (C) 2008-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* This tests that gdb can read compressed sections. The contents are a basic assembly file, but the .debug_abbrev section has been comrpessed using zlib. */ /* Dummy function to provide debug information for. */ .text .globl _start _start: .int 0 .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .int 0 .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: /* Debug information */ .section .debug_info .Lcu1_begin: /* CU header */ .4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */ .Lcu1_start: .2byte 2 /* DWARF Version */ .4byte .Labbrev1_begin /* Offset into abbrev section */ .byte 4 /* Pointer size */ /* CU die */ .uleb128 1 /* Abbrev: DW_TAG_compile_unit */ .4byte .Lline1_begin /* DW_AT_stmt_list */ .4byte .Lend_text1 /* DW_AT_high_pc */ .4byte .Lbegin_text1 /* DW_AT_low_pc */ .ascii "file1.txt\0" /* DW_AT_name */ .ascii "GNU C 3.3.3\0" /* DW_AT_producer */ .byte 1 /* DW_AT_language (C) */ /* func_cu1 */ .uleb128 2 /* Abbrev: DW_TAG_subprogram */ .byte 1 /* DW_AT_external */ .byte 1 /* DW_AT_decl_file */ .byte 2 /* DW_AT_decl_line */ .ascii "func_cu1\0" /* DW_AT_name */ .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */ .4byte .Lbegin_func_cu1 /* DW_AT_low_pc */ .4byte .Lend_func_cu1 /* DW_AT_high_pc */ .byte 1 /* DW_AT_frame_base: length */ .byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */ .Ltype_int: .uleb128 3 /* Abbrev: DW_TAG_base_type */ .ascii "int\0" /* DW_AT_name */ .byte 4 /* DW_AT_byte_size */ .byte 5 /* DW_AT_encoding */ .byte 0 /* End of children of CU */ .Lcu1_end: /* Line table */ .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start /* Initial length */ .Lline1_start: .2byte 2 /* Version */ .4byte .Lline1_lines - .Lline1_hdr /* header_length */ .Lline1_hdr: .byte 1 /* Minimum insn length */ .byte 1 /* default_is_stmt */ .byte 1 /* line_base */ .byte 1 /* line_range */ .byte 0x10 /* opcode_base */ /* Standard lengths */ .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 /* Include directories */ .byte 0 /* File names */ .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lbegin_func_cu1 .byte 3 /* DW_LNS_advance_line */ .sleb128 3 /* ... to 4 */ .byte 1 /* DW_LNS_copy */ .byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */ .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lend_func_cu1 .byte 0 /* DW_LNE_end_of_sequence */ .uleb128 1 .byte 1 .Lline1_end: /* Abbrev table -- compressed */ .section .zdebug_abbrev .Labbrev1_begin: .ascii "ZLIB" .4byte 0 .2byte 0 .byte 0 .byte 51 .byte 0x78 .byte 0x5e .byte 0x63 .byte 0x14 .byte 0x64 .byte 0x14 .byte 0x60 .byte 0x13 .byte 0x62 .byte 0x14 .byte 0x64 .byte 0x64 .byte 0xe6 .byte 0x50 .byte 0xe5 .byte 0x10 .byte 0xe6 .byte 0x66 .byte 0x60 .byte 0x60 .byte 0xd2 .byte 0x63 .byte 0xb0 .byte 0xe7 .byte 0xb1 .byte 0xe2 .byte 0xb6 .byte 0xe6 .byte 0x66 .byte 0xe6 .byte 0xf0 .byte 0x14 .byte 0x16 .byte 0x64 .byte 0x14 .byte 0x62 .byte 0x74 .byte 0xe0 .byte 0x02 .byte 0x00 .byte 0x25 .byte 0x78 .byte 0x02 .byte 0x81 .byte 0x78 .byte 0x9c .byte 0x63 .byte 0x60 .byte 0x60 .byte 0x56 .byte 0x61 .byte 0x60 .byte 0xe6 .byte 0xe0 .byte 0xe6 .byte 0xb6 .byte 0xe3 .byte 0x66 .byte 0x00 .byte 0x02 .byte 0x00 .byte 0x04 .byte 0x9c .byte 0x00 .byte 0x92

stsp/binutils-ia16

1,363

binutils/testsuite/binutils-all/pr25662.s

/* PR 25662: objcopy sets invalid sh_offset for the first section in a no_contents segment containing program headers. Several conditions are required for the bug to manifest: - The first loadable segment (which contains the program headers) must only contain SHT_NOBITS sections. .bss is the SHT_NOBITS section in this test. - The next loadable segment must have a !SHT_NOBITS loadable section. .data is the !SHT_NOBITS section in this test. - .bss must be positioned after .data in the executable file itself. - The size of .data must be such that the calculated VMA of the .bss section that follows it is not congruent with the file offset of .bss, modulo the p_align of its segment, i.e.: (VMA(.data) + sizeof(.data)) % (.bss_segment.p_align) != 0 This will force the sh_offset of .bss to be aligned so it appears within .data. - The size of .data must be larger than the program headers in the first loadable segment, so that the file offset of .bss is immediately after .data, and not padded to a valid alignment by the program headers. The bug originally only manifested for ELF targets, but there's no reason not to run this testcase for other file formats. */ .section .bss aaa: .zero 0x2 .section .data ccc: .zero 0x201 .section .text .global _start _start: .long 0

stsp/binutils-ia16

35,389

binutils/testsuite/binutils-all/dw4.s

.file "main.c" .text .Ltext0: .text .globl main .type main, %function main: .LFB0: .file 1 "main.c" .loc 1 6 1 view -0 .word 1234 .word 5678 .LFE0: .size main, . - main .globl g_my_private_global .data .align 4 .type g_my_private_global, %object .size g_my_private_global, 4 g_my_private_global: .zero 4 .globl g_my_externd_global .data .align 4 .type g_my_externd_global, %object .size g_my_externd_global, 4 g_my_externd_global: .zero 4 .text .Letext0: .section .debug_info,"",%progbits .Ldebug_info0: .long .Linfo_end - .Linfo_start .Linfo_start: .short 0x4 .long .Ldebug_abbrev0 .byte 0x8 .uleb128 0x1 .long .LASF345 .byte 0xc .long .LASF346 .long .LASF347 .long .Ldebug_ranges0 + 0 .quad 0 .long .Ldebug_line0 .long .Ldebug_macro0 .Lvar_decl: .uleb128 0x2 .long .LASF343 .byte 0x1 .byte 0x2 .byte 0xc .long 0x39 .uleb128 0x3 .byte 0x4 .byte 0x5 .string "int" .uleb128 0x4 .long .Lvar_decl - .Ldebug_info0 .byte 0x3 .byte 0x5 .uleb128 .Lblock1_end - .Lblock1_start .Lblock1_start: .byte 0x3 .dc.a g_my_externd_global .Lblock1_end: .uleb128 0x5 .long .LASF344 .byte 0x1 .byte 0x4 .byte 0x5 .long 0x39 .uleb128 .Lblock2_end - .Lblock2_start .Lblock2_start: .byte 0x3 .dc.a g_my_private_global .Lblock2_end: .uleb128 0x6 .long .LASF348 .byte 0x1 .byte 0x5 .byte 0x5 .long 0x39 .quad 0 .quad 0x10 .uleb128 0x1 .byte 0x9c .byte 0 .Linfo_end: .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0xe .uleb128 0x1b .uleb128 0xe .uleb128 0x55 .uleb128 0x17 .uleb128 0x11 .uleb128 0x1 .uleb128 0x10 .uleb128 0x17 .uleb128 0x2119 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x2 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x3f .uleb128 0x19 .uleb128 0x3c .uleb128 0x19 .byte 0 .byte 0 .uleb128 0x3 .uleb128 0x24 .byte 0 .uleb128 0xb .uleb128 0xb .uleb128 0x3e .uleb128 0xb .uleb128 0x3 .uleb128 0x8 .byte 0 .byte 0 .uleb128 0x4 .uleb128 0x34 .byte 0 .uleb128 0x47 .uleb128 0x13 .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x2 .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x5 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x3f .uleb128 0x19 .uleb128 0x2 .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x6 .uleb128 0x2e .byte 0 .uleb128 0x3f .uleb128 0x19 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x39 .uleb128 0xb .uleb128 0x27 .uleb128 0x19 .uleb128 0x49 .uleb128 0x13 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x7 .uleb128 0x40 .uleb128 0x18 .uleb128 0x2117 .uleb128 0x19 .byte 0 .byte 0 .byte 0 .section .debug_aranges,"",%progbits .long 0x2c .short 0x2 .long .Ldebug_info0 .byte 0x8 .byte 0 .short 0 .short 0 .dc.a .LFB0 .quad .LFE0 - .LFB0 .quad 0 .quad 0 .section .debug_ranges,"",%progbits .Ldebug_ranges0: .dc.a .LFB0 .dc.a .LFE0 .quad 0 .quad 0 .section .debug_macro,"",%progbits .Ldebug_macro0: .short 0x4 .byte 0x2 .long .Ldebug_line0 .byte 0x3 .uleb128 0 .uleb128 0x1 .byte 0x5 .uleb128 0x1 .long .LASF0 .byte 0x5 .uleb128 0x2 .long .LASF1 .byte 0x5 .uleb128 0x3 .long .LASF2 .byte 0x5 .uleb128 0x4 .long .LASF3 .byte 0x5 .uleb128 0x5 .long .LASF4 .byte 0x5 .uleb128 0x6 .long .LASF5 .byte 0x5 .uleb128 0x7 .long .LASF6 .byte 0x5 .uleb128 0x8 .long .LASF7 .byte 0x5 .uleb128 0x9 .long .LASF8 .byte 0x5 .uleb128 0xa .long .LASF9 .byte 0x5 .uleb128 0xb .long .LASF10 .byte 0x5 .uleb128 0xc .long .LASF11 .byte 0x5 .uleb128 0xd .long .LASF12 .byte 0x5 .uleb128 0xe .long .LASF13 .byte 0x5 .uleb128 0xf .long .LASF14 .byte 0x5 .uleb128 0x10 .long .LASF15 .byte 0x5 .uleb128 0x11 .long .LASF16 .byte 0x5 .uleb128 0x12 .long .LASF17 .byte 0x5 .uleb128 0x13 .long .LASF18 .byte 0x5 .uleb128 0x14 .long .LASF19 .byte 0x5 .uleb128 0x15 .long .LASF20 .byte 0x5 .uleb128 0x16 .long .LASF21 .byte 0x5 .uleb128 0x17 .long .LASF22 .byte 0x5 .uleb128 0x18 .long .LASF23 .byte 0x5 .uleb128 0x19 .long .LASF24 .byte 0x5 .uleb128 0x1a .long .LASF25 .byte 0x5 .uleb128 0x1b .long .LASF26 .byte 0x5 .uleb128 0x1c .long .LASF27 .byte 0x5 .uleb128 0x1d .long .LASF28 .byte 0x5 .uleb128 0x1e .long .LASF29 .byte 0x5 .uleb128 0x1f .long .LASF30 .byte 0x5 .uleb128 0x20 .long .LASF31 .byte 0x5 .uleb128 0x21 .long .LASF32 .byte 0x5 .uleb128 0x22 .long .LASF33 .byte 0x5 .uleb128 0x23 .long .LASF34 .byte 0x5 .uleb128 0x24 .long .LASF35 .byte 0x5 .uleb128 0x25 .long .LASF36 .byte 0x5 .uleb128 0x26 .long .LASF37 .byte 0x5 .uleb128 0x27 .long .LASF38 .byte 0x5 .uleb128 0x28 .long .LASF39 .byte 0x5 .uleb128 0x29 .long .LASF40 .byte 0x5 .uleb128 0x2a .long .LASF41 .byte 0x5 .uleb128 0x2b .long .LASF42 .byte 0x5 .uleb128 0x2c .long .LASF43 .byte 0x5 .uleb128 0x2d .long .LASF44 .byte 0x5 .uleb128 0x2e .long .LASF45 .byte 0x5 .uleb128 0x2f .long .LASF46 .byte 0x5 .uleb128 0x30 .long .LASF47 .byte 0x5 .uleb128 0x31 .long .LASF48 .byte 0x5 .uleb128 0x32 .long .LASF49 .byte 0x5 .uleb128 0x33 .long .LASF50 .byte 0x5 .uleb128 0x34 .long .LASF51 .byte 0x5 .uleb128 0x35 .long .LASF52 .byte 0x5 .uleb128 0x36 .long .LASF53 .byte 0x5 .uleb128 0x37 .long .LASF54 .byte 0x5 .uleb128 0x38 .long .LASF55 .byte 0x5 .uleb128 0x39 .long .LASF56 .byte 0x5 .uleb128 0x3a .long .LASF57 .byte 0x5 .uleb128 0x3b .long .LASF58 .byte 0x5 .uleb128 0x3c .long .LASF59 .byte 0x5 .uleb128 0x3d .long .LASF60 .byte 0x5 .uleb128 0x3e .long .LASF61 .byte 0x5 .uleb128 0x3f .long .LASF62 .byte 0x5 .uleb128 0x40 .long .LASF63 .byte 0x5 .uleb128 0x41 .long .LASF64 .byte 0x5 .uleb128 0x42 .long .LASF65 .byte 0x5 .uleb128 0x43 .long .LASF66 .byte 0x5 .uleb128 0x44 .long .LASF67 .byte 0x5 .uleb128 0x45 .long .LASF68 .byte 0x5 .uleb128 0x46 .long .LASF69 .byte 0x5 .uleb128 0x47 .long .LASF70 .byte 0x5 .uleb128 0x48 .long .LASF71 .byte 0x5 .uleb128 0x49 .long .LASF72 .byte 0x5 .uleb128 0x4a .long .LASF73 .byte 0x5 .uleb128 0x4b .long .LASF74 .byte 0x5 .uleb128 0x4c .long .LASF75 .byte 0x5 .uleb128 0x4d .long .LASF76 .byte 0x5 .uleb128 0x4e .long .LASF77 .byte 0x5 .uleb128 0x4f .long .LASF78 .byte 0x5 .uleb128 0x50 .long .LASF79 .byte 0x5 .uleb128 0x51 .long .LASF80 .byte 0x5 .uleb128 0x52 .long .LASF81 .byte 0x5 .uleb128 0x53 .long .LASF82 .byte 0x5 .uleb128 0x54 .long .LASF83 .byte 0x5 .uleb128 0x55 .long .LASF84 .byte 0x5 .uleb128 0x56 .long .LASF85 .byte 0x5 .uleb128 0x57 .long .LASF86 .byte 0x5 .uleb128 0x58 .long .LASF87 .byte 0x5 .uleb128 0x59 .long .LASF88 .byte 0x5 .uleb128 0x5a .long .LASF89 .byte 0x5 .uleb128 0x5b .long .LASF90 .byte 0x5 .uleb128 0x5c .long .LASF91 .byte 0x5 .uleb128 0x5d .long .LASF92 .byte 0x5 .uleb128 0x5e .long .LASF93 .byte 0x5 .uleb128 0x5f .long .LASF94 .byte 0x5 .uleb128 0x60 .long .LASF95 .byte 0x5 .uleb128 0x61 .long .LASF96 .byte 0x5 .uleb128 0x62 .long .LASF97 .byte 0x5 .uleb128 0x63 .long .LASF98 .byte 0x5 .uleb128 0x64 .long .LASF99 .byte 0x5 .uleb128 0x65 .long .LASF100 .byte 0x5 .uleb128 0x66 .long .LASF101 .byte 0x5 .uleb128 0x67 .long .LASF102 .byte 0x5 .uleb128 0x68 .long .LASF103 .byte 0x5 .uleb128 0x69 .long .LASF104 .byte 0x5 .uleb128 0x6a .long .LASF105 .byte 0x5 .uleb128 0x6b .long .LASF106 .byte 0x5 .uleb128 0x6c .long .LASF107 .byte 0x5 .uleb128 0x6d .long .LASF108 .byte 0x5 .uleb128 0x6e .long .LASF109 .byte 0x5 .uleb128 0x6f .long .LASF110 .byte 0x5 .uleb128 0x70 .long .LASF111 .byte 0x5 .uleb128 0x71 .long .LASF112 .byte 0x5 .uleb128 0x72 .long .LASF113 .byte 0x5 .uleb128 0x73 .long .LASF114 .byte 0x5 .uleb128 0x74 .long .LASF115 .byte 0x5 .uleb128 0x75 .long .LASF116 .byte 0x5 .uleb128 0x76 .long .LASF117 .byte 0x5 .uleb128 0x77 .long .LASF118 .byte 0x5 .uleb128 0x78 .long .LASF119 .byte 0x5 .uleb128 0x79 .long .LASF120 .byte 0x5 .uleb128 0x7a .long .LASF121 .byte 0x5 .uleb128 0x7b .long .LASF122 .byte 0x5 .uleb128 0x7c .long .LASF123 .byte 0x5 .uleb128 0x7d .long .LASF124 .byte 0x5 .uleb128 0x7e .long .LASF125 .byte 0x5 .uleb128 0x7f .long .LASF126 .byte 0x5 .uleb128 0x80 .long .LASF127 .byte 0x5 .uleb128 0x81 .long .LASF128 .byte 0x5 .uleb128 0x82 .long .LASF129 .byte 0x5 .uleb128 0x83 .long .LASF130 .byte 0x5 .uleb128 0x84 .long .LASF131 .byte 0x5 .uleb128 0x85 .long .LASF132 .byte 0x5 .uleb128 0x86 .long .LASF133 .byte 0x5 .uleb128 0x87 .long .LASF134 .byte 0x5 .uleb128 0x88 .long .LASF135 .byte 0x5 .uleb128 0x89 .long .LASF136 .byte 0x5 .uleb128 0x8a .long .LASF137 .byte 0x5 .uleb128 0x8b .long .LASF138 .byte 0x5 .uleb128 0x8c .long .LASF139 .byte 0x5 .uleb128 0x8d .long .LASF140 .byte 0x5 .uleb128 0x8e .long .LASF141 .byte 0x5 .uleb128 0x8f .long .LASF142 .byte 0x5 .uleb128 0x90 .long .LASF143 .byte 0x5 .uleb128 0x91 .long .LASF144 .byte 0x5 .uleb128 0x92 .long .LASF145 .byte 0x5 .uleb128 0x93 .long .LASF146 .byte 0x5 .uleb128 0x94 .long .LASF147 .byte 0x5 .uleb128 0x95 .long .LASF148 .byte 0x5 .uleb128 0x96 .long .LASF149 .byte 0x5 .uleb128 0x97 .long .LASF150 .byte 0x5 .uleb128 0x98 .long .LASF151 .byte 0x5 .uleb128 0x99 .long .LASF152 .byte 0x5 .uleb128 0x9a .long .LASF153 .byte 0x5 .uleb128 0x9b .long .LASF154 .byte 0x5 .uleb128 0x9c .long .LASF155 .byte 0x5 .uleb128 0x9d .long .LASF156 .byte 0x5 .uleb128 0x9e .long .LASF157 .byte 0x5 .uleb128 0x9f .long .LASF158 .byte 0x5 .uleb128 0xa0 .long .LASF159 .byte 0x5 .uleb128 0xa1 .long .LASF160 .byte 0x5 .uleb128 0xa2 .long .LASF161 .byte 0x5 .uleb128 0xa3 .long .LASF162 .byte 0x5 .uleb128 0xa4 .long .LASF163 .byte 0x5 .uleb128 0xa5 .long .LASF164 .byte 0x5 .uleb128 0xa6 .long .LASF165 .byte 0x5 .uleb128 0xa7 .long .LASF166 .byte 0x5 .uleb128 0xa8 .long .LASF167 .byte 0x5 .uleb128 0xa9 .long .LASF168 .byte 0x5 .uleb128 0xaa .long .LASF169 .byte 0x5 .uleb128 0xab .long .LASF170 .byte 0x5 .uleb128 0xac .long .LASF171 .byte 0x5 .uleb128 0xad .long .LASF172 .byte 0x5 .uleb128 0xae .long .LASF173 .byte 0x5 .uleb128 0xaf .long .LASF174 .byte 0x5 .uleb128 0xb0 .long .LASF175 .byte 0x5 .uleb128 0xb1 .long .LASF176 .byte 0x5 .uleb128 0xb2 .long .LASF177 .byte 0x5 .uleb128 0xb3 .long .LASF178 .byte 0x5 .uleb128 0xb4 .long .LASF179 .byte 0x5 .uleb128 0xb5 .long .LASF180 .byte 0x5 .uleb128 0xb6 .long .LASF181 .byte 0x5 .uleb128 0xb7 .long .LASF182 .byte 0x5 .uleb128 0xb8 .long .LASF183 .byte 0x5 .uleb128 0xb9 .long .LASF184 .byte 0x5 .uleb128 0xba .long .LASF185 .byte 0x5 .uleb128 0xbb .long .LASF186 .byte 0x5 .uleb128 0xbc .long .LASF187 .byte 0x5 .uleb128 0xbd .long .LASF188 .byte 0x5 .uleb128 0xbe .long .LASF189 .byte 0x5 .uleb128 0xbf .long .LASF190 .byte 0x5 .uleb128 0xc0 .long .LASF191 .byte 0x5 .uleb128 0xc1 .long .LASF192 .byte 0x5 .uleb128 0xc2 .long .LASF193 .byte 0x5 .uleb128 0xc3 .long .LASF194 .byte 0x5 .uleb128 0xc4 .long .LASF195 .byte 0x5 .uleb128 0xc5 .long .LASF196 .byte 0x5 .uleb128 0xc6 .long .LASF197 .byte 0x5 .uleb128 0xc7 .long .LASF198 .byte 0x5 .uleb128 0xc8 .long .LASF199 .byte 0x5 .uleb128 0xc9 .long .LASF200 .byte 0x5 .uleb128 0xca .long .LASF201 .byte 0x5 .uleb128 0xcb .long .LASF202 .byte 0x5 .uleb128 0xcc .long .LASF203 .byte 0x5 .uleb128 0xcd .long .LASF204 .byte 0x5 .uleb128 0xce .long .LASF205 .byte 0x5 .uleb128 0xcf .long .LASF206 .byte 0x5 .uleb128 0xd0 .long .LASF207 .byte 0x5 .uleb128 0xd1 .long .LASF208 .byte 0x5 .uleb128 0xd2 .long .LASF209 .byte 0x5 .uleb128 0xd3 .long .LASF210 .byte 0x5 .uleb128 0xd4 .long .LASF211 .byte 0x5 .uleb128 0xd5 .long .LASF212 .byte 0x5 .uleb128 0xd6 .long .LASF213 .byte 0x5 .uleb128 0xd7 .long .LASF214 .byte 0x5 .uleb128 0xd8 .long .LASF215 .byte 0x5 .uleb128 0xd9 .long .LASF216 .byte 0x5 .uleb128 0xda .long .LASF217 .byte 0x5 .uleb128 0xdb .long .LASF218 .byte 0x5 .uleb128 0xdc .long .LASF219 .byte 0x5 .uleb128 0xdd .long .LASF220 .byte 0x5 .uleb128 0xde .long .LASF221 .byte 0x5 .uleb128 0xdf .long .LASF222 .byte 0x5 .uleb128 0xe0 .long .LASF223 .byte 0x5 .uleb128 0xe1 .long .LASF224 .byte 0x5 .uleb128 0xe2 .long .LASF225 .byte 0x5 .uleb128 0xe3 .long .LASF226 .byte 0x5 .uleb128 0xe4 .long .LASF227 .byte 0x5 .uleb128 0xe5 .long .LASF228 .byte 0x5 .uleb128 0xe6 .long .LASF229 .byte 0x5 .uleb128 0xe7 .long .LASF230 .byte 0x5 .uleb128 0xe8 .long .LASF231 .byte 0x5 .uleb128 0xe9 .long .LASF232 .byte 0x5 .uleb128 0xea .long .LASF233 .byte 0x5 .uleb128 0xeb .long .LASF234 .byte 0x5 .uleb128 0xec .long .LASF235 .byte 0x5 .uleb128 0xed .long .LASF236 .byte 0x5 .uleb128 0xee .long .LASF237 .byte 0x5 .uleb128 0xef .long .LASF238 .byte 0x5 .uleb128 0xf0 .long .LASF239 .byte 0x5 .uleb128 0xf1 .long .LASF240 .byte 0x5 .uleb128 0xf2 .long .LASF241 .byte 0x5 .uleb128 0xf3 .long .LASF242 .byte 0x5 .uleb128 0xf4 .long .LASF243 .byte 0x5 .uleb128 0xf5 .long .LASF244 .byte 0x5 .uleb128 0xf6 .long .LASF245 .byte 0x5 .uleb128 0xf7 .long .LASF246 .byte 0x5 .uleb128 0xf8 .long .LASF247 .byte 0x5 .uleb128 0xf9 .long .LASF248 .byte 0x5 .uleb128 0xfa .long .LASF249 .byte 0x5 .uleb128 0xfb .long .LASF250 .byte 0x5 .uleb128 0xfc .long .LASF251 .byte 0x5 .uleb128 0xfd .long .LASF252 .byte 0x5 .uleb128 0xfe .long .LASF253 .byte 0x5 .uleb128 0xff .long .LASF254 .byte 0x5 .uleb128 0x100 .long .LASF255 .byte 0x5 .uleb128 0x101 .long .LASF256 .byte 0x5 .uleb128 0x102 .long .LASF257 .byte 0x5 .uleb128 0x103 .long .LASF258 .byte 0x5 .uleb128 0x104 .long .LASF259 .byte 0x5 .uleb128 0x105 .long .LASF260 .byte 0x5 .uleb128 0x106 .long .LASF261 .byte 0x5 .uleb128 0x107 .long .LASF262 .byte 0x5 .uleb128 0x108 .long .LASF263 .byte 0x5 .uleb128 0x109 .long .LASF264 .byte 0x5 .uleb128 0x10a .long .LASF265 .byte 0x5 .uleb128 0x10b .long .LASF266 .byte 0x5 .uleb128 0x10c .long .LASF267 .byte 0x5 .uleb128 0x10d .long .LASF268 .byte 0x5 .uleb128 0x10e .long .LASF269 .byte 0x5 .uleb128 0x10f .long .LASF270 .byte 0x5 .uleb128 0x110 .long .LASF271 .byte 0x5 .uleb128 0x111 .long .LASF272 .byte 0x5 .uleb128 0x112 .long .LASF273 .byte 0x5 .uleb128 0x113 .long .LASF274 .byte 0x5 .uleb128 0x114 .long .LASF275 .byte 0x5 .uleb128 0x115 .long .LASF276 .byte 0x5 .uleb128 0x116 .long .LASF277 .byte 0x5 .uleb128 0x117 .long .LASF278 .byte 0x5 .uleb128 0x118 .long .LASF279 .byte 0x5 .uleb128 0x119 .long .LASF280 .byte 0x5 .uleb128 0x11a .long .LASF281 .byte 0x5 .uleb128 0x11b .long .LASF282 .byte 0x5 .uleb128 0x11c .long .LASF283 .byte 0x5 .uleb128 0x11d .long .LASF284 .byte 0x5 .uleb128 0x11e .long .LASF285 .byte 0x5 .uleb128 0x11f .long .LASF286 .byte 0x5 .uleb128 0x120 .long .LASF287 .byte 0x5 .uleb128 0x121 .long .LASF288 .byte 0x5 .uleb128 0x122 .long .LASF289 .byte 0x5 .uleb128 0x123 .long .LASF290 .byte 0x5 .uleb128 0x124 .long .LASF291 .byte 0x5 .uleb128 0x125 .long .LASF292 .byte 0x5 .uleb128 0x126 .long .LASF293 .byte 0x5 .uleb128 0x127 .long .LASF294 .byte 0x5 .uleb128 0x128 .long .LASF295 .byte 0x5 .uleb128 0x129 .long .LASF296 .byte 0x5 .uleb128 0x12a .long .LASF297 .byte 0x5 .uleb128 0x12b .long .LASF298 .byte 0x5 .uleb128 0x12c .long .LASF299 .byte 0x5 .uleb128 0x12d .long .LASF300 .byte 0x5 .uleb128 0x12e .long .LASF301 .byte 0x5 .uleb128 0x12f .long .LASF302 .byte 0x5 .uleb128 0x130 .long .LASF303 .byte 0x5 .uleb128 0x131 .long .LASF304 .byte 0x5 .uleb128 0x132 .long .LASF305 .byte 0x5 .uleb128 0x133 .long .LASF306 .byte 0x5 .uleb128 0x134 .long .LASF307 .byte 0x5 .uleb128 0x135 .long .LASF308 .byte 0x5 .uleb128 0x136 .long .LASF309 .byte 0x5 .uleb128 0x137 .long .LASF310 .byte 0x5 .uleb128 0x138 .long .LASF311 .byte 0x5 .uleb128 0x139 .long .LASF312 .byte 0x5 .uleb128 0x13a .long .LASF313 .byte 0x5 .uleb128 0x13b .long .LASF314 .byte 0x5 .uleb128 0x13c .long .LASF315 .byte 0x5 .uleb128 0x13d .long .LASF316 .byte 0x5 .uleb128 0x13e .long .LASF317 .byte 0x5 .uleb128 0x13f .long .LASF318 .byte 0x5 .uleb128 0x140 .long .LASF319 .byte 0x5 .uleb128 0x141 .long .LASF320 .byte 0x5 .uleb128 0x142 .long .LASF321 .byte 0x5 .uleb128 0x143 .long .LASF322 .byte 0x5 .uleb128 0x144 .long .LASF323 .byte 0x5 .uleb128 0x145 .long .LASF324 .byte 0x5 .uleb128 0x146 .long .LASF325 .byte 0x5 .uleb128 0x147 .long .LASF326 .byte 0x5 .uleb128 0x148 .long .LASF327 .byte 0x5 .uleb128 0x149 .long .LASF328 .byte 0x5 .uleb128 0x14a .long .LASF329 .byte 0x5 .uleb128 0x14b .long .LASF330 .byte 0x5 .uleb128 0x14c .long .LASF331 .byte 0x5 .uleb128 0x14d .long .LASF332 .byte 0x5 .uleb128 0x14e .long .LASF333 .byte 0x5 .uleb128 0x14f .long .LASF334 .byte 0x5 .uleb128 0x150 .long .LASF335 .byte 0x5 .uleb128 0x151 .long .LASF336 .byte 0x5 .uleb128 0x152 .long .LASF337 .byte 0x5 .uleb128 0x153 .long .LASF338 .file 2 "/usr/include/stdc-predef.h" .byte 0x3 .uleb128 0x1f .uleb128 0x2 .byte 0x7 .long .Ldebug_macro2 .byte 0x4 .byte 0x4 .byte 0 .section .debug_macro,"G",%progbits,wm4.stdcpredef.h.19.8dc41bed5d9037ff9622e015fb5f0ce3,comdat .Ldebug_macro2: .short 0x4 .byte 0 .byte 0x5 .uleb128 0x13 .long .LASF339 .byte 0x5 .uleb128 0x26 .long .LASF340 .byte 0x5 .uleb128 0x2e .long .LASF341 .byte 0x5 .uleb128 0x3a .long .LASF342 .byte 0 .section .debug_line,"",%progbits .Ldebug_line0: .section .debug_str,"MS",%progbits,1 .LASF122: .string "__UINT_LEAST8_MAX__ 0xff" .LASF219: .string "__FLT64_HAS_DENORM__ 1" .LASF250: .string "__FLT64X_MANT_DIG__ 64" .LASF2: .string "__STDC_UTF_16__ 1" .LASF252: .string "__FLT64X_MIN_EXP__ (-16381)" .LASF126: .string "__UINT_LEAST32_MAX__ 0xffffffffU" .LASF160: .string "__FLT_EPSILON__ 1.19209289550781250000000000000000000e-7F" .LASF8: .string "__VERSION__ \"9.2.1 20190827 (Red Hat 9.2.1-1)\"" .LASF247: .string "__FLT32X_HAS_DENORM__ 1" .LASF334: .string "__unix 1" .LASF70: .string "__UINTPTR_TYPE__ long unsigned int" .LASF35: .string "__SIZEOF_POINTER__ 8" .LASF90: .string "__WCHAR_WIDTH__ 32" .LASF279: .string "__DEC128_MIN_EXP__ (-6142)" .LASF271: .string "__DEC64_MANT_DIG__ 16" .LASF272: .string "__DEC64_MIN_EXP__ (-382)" .LASF173: .string "__DBL_MIN__ ((double)2.22507385850720138309023271733240406e-308L)" .LASF141: .string "__UINT_FAST64_MAX__ 0xffffffffffffffffUL" .LASF335: .string "__unix__ 1" .LASF240: .string "__FLT32X_MAX_EXP__ 1024" .LASF184: .string "__LDBL_MAX_10_EXP__ 4932" .LASF267: .string "__DEC32_MIN__ 1E-95DF" .LASF215: .string "__FLT64_MAX__ 1.79769313486231570814527423731704357e+308F64" .LASF249: .string "__FLT32X_HAS_QUIET_NAN__ 1" .LASF265: .string "__DEC32_MIN_EXP__ (-94)" .LASF234: .string "__FLT128_HAS_INFINITY__ 1" .LASF170: .string "__DBL_MAX_10_EXP__ 308" .LASF216: .string "__FLT64_MIN__ 2.22507385850720138309023271733240406e-308F64" .LASF310: .string "__amd64 1" .LASF188: .string "__LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L" .LASF118: .string "__INT_LEAST32_WIDTH__ 32" .LASF144: .string "__UINTPTR_MAX__ 0xffffffffffffffffUL" .LASF19: .string "__LP64__ 1" .LASF129: .string "__UINT64_C(c) c ## UL" .LASF177: .string "__DBL_HAS_INFINITY__ 1" .LASF1: .string "__STDC_VERSION__ 201710L" .LASF321: .string "__code_model_small__ 1" .LASF239: .string "__FLT32X_MIN_10_EXP__ (-307)" .LASF117: .string "__INT32_C(c) c" .LASF245: .string "__FLT32X_EPSILON__ 2.22044604925031308084726333618164062e-16F32x" .LASF7: .string "__GNUC_PATCHLEVEL__ 1" .LASF261: .string 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.LASF136: .string "__INT_FAST64_MAX__ 0x7fffffffffffffffL" .LASF343: .string "g_my_externd_global" .LASF31: .string "__ORDER_BIG_ENDIAN__ 4321" .LASF69: .string "__INTPTR_TYPE__ long int" .LASF182: .string "__LDBL_MIN_10_EXP__ (-4931)" .LASF135: .string "__INT_FAST32_WIDTH__ 64" .LASF260: .string "__FLT64X_DENORM_MIN__ 3.64519953188247460252840593361941982e-4951F64x" .LASF199: .string "__FLT32_MAX_10_EXP__ 38" .LASF187: .string "__LDBL_MAX__ 1.18973149535723176502126385303097021e+4932L" .LASF23: .string "__SIZEOF_SHORT__ 2" .LASF159: .string "__FLT_MIN__ 1.17549435082228750796873653722224568e-38F" .LASF298: .string "__GCC_ATOMIC_INT_LOCK_FREE 2" .LASF220: .string "__FLT64_HAS_INFINITY__ 1" .LASF114: .string "__INT16_C(c) c" .LASF262: .string "__FLT64X_HAS_INFINITY__ 1" .LASF336: .string "unix 1" .LASF155: .string "__FLT_MAX_EXP__ 128" .LASF275: .string "__DEC64_MAX__ 9.999999999999999E384DD" .LASF225: .string "__FLT128_MIN_10_EXP__ (-4931)" .LASF76: .string "__INT_MAX__ 0x7fffffff" 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.string "__INT8_TYPE__ signed char" .LASF87: .string "__INT_WIDTH__ 32" .LASF49: .string "__UINT8_TYPE__ unsigned char" .LASF98: .string "__INTMAX_WIDTH__ 64" .LASF41: .string "__UINTMAX_TYPE__ long unsigned int" .LASF5: .string "__GNUC__ 9" .LASF341: .string "__STDC_IEC_559_COMPLEX__ 1" .LASF46: .string "__INT16_TYPE__ short int" .LASF297: .string "__GCC_ATOMIC_SHORT_LOCK_FREE 2" .LASF9: .string "__GNUC_RH_RELEASE__ 1" .LASF195: .string "__FLT32_DIG__ 6" .LASF282: .string "__DEC128_MAX__ 9.999999999999999999999999999999999E6144DL" .LASF347: .string "/home/nickc/work/builds/binutils/current/x86_64-pc-linux-gnu/tests" .LASF112: .string "__INT_LEAST8_WIDTH__ 8" .LASF58: .string "__UINT_LEAST16_TYPE__ short unsigned int" .LASF61: .string "__INT_FAST8_TYPE__ signed char" .LASF169: .string "__DBL_MAX_EXP__ 1024" .LASF236: .string "__FLT32X_MANT_DIG__ 53" .LASF147: .string "__FLT_EVAL_METHOD__ 0" .LASF94: .string "__INTMAX_MAX__ 0x7fffffffffffffffL" .LASF12: .string "__ATOMIC_ACQUIRE 2" .LASF67: .string "__UINT_FAST32_TYPE__ long unsigned int" .LASF200: .string "__FLT32_DECIMAL_DIG__ 9" .LASF116: .string "__INT_LEAST32_MAX__ 0x7fffffff" .LASF293: .string "__GCC_ATOMIC_CHAR_LOCK_FREE 2" .LASF283: .string "__DEC128_EPSILON__ 1E-33DL" .LASF158: .string "__FLT_MAX__ 3.40282346638528859811704183484516925e+38F" .LASF307: .string "__SIZEOF_WCHAR_T__ 4" .LASF242: .string "__FLT32X_DECIMAL_DIG__ 17" .LASF62: .string "__INT_FAST16_TYPE__ long int" .LASF65: .string "__UINT_FAST8_TYPE__ unsigned char" .LASF104: .string "__INT32_MAX__ 0x7fffffff" .LASF315: .string "__SIZEOF_FLOAT128__ 16" .LASF337: .string "__ELF__ 1" .LASF211: .string "__FLT64_MIN_10_EXP__ (-307)" .LASF180: .string "__LDBL_DIG__ 18" .LASF340: .string "__STDC_IEC_559__ 1" .LASF284: .string "__DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL" .LASF316: .string "__ATOMIC_HLE_ACQUIRE 65536" .LASF326: .string "__SSE_MATH__ 1" .LASF132: .string "__INT_FAST16_MAX__ 0x7fffffffffffffffL" .LASF113: .string "__INT_LEAST16_MAX__ 0x7fff" .LASF208: .string "__FLT64_MANT_DIG__ 53" .LASF278: .string "__DEC128_MANT_DIG__ 34" .LASF88: .string "__LONG_WIDTH__ 64" .LASF93: .string "__SIZE_WIDTH__ 64" .LASF91: .string "__WINT_WIDTH__ 32" .LASF228: .string "__FLT128_DECIMAL_DIG__ 36" .LASF80: .string "__WCHAR_MIN__ (-__WCHAR_MAX__ - 1)" .LASF289: .string "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1" .LASF183: .string "__LDBL_MAX_EXP__ 16384" .LASF251: .string "__FLT64X_DIG__ 18" .LASF237: .string "__FLT32X_DIG__ 15" .LASF320: .string "__k8__ 1" .LASF43: .string "__CHAR32_TYPE__ unsigned int" .LASF96: .string "__UINTMAX_MAX__ 0xffffffffffffffffUL" .LASF201: .string "__FLT32_MAX__ 3.40282346638528859811704183484516925e+38F32" .LASF77: .string "__LONG_MAX__ 0x7fffffffffffffffL" .LASF339: .string "_STDC_PREDEF_H 1" .LASF53: .string "__INT_LEAST8_TYPE__ signed char" .LASF125: .string "__UINT16_C(c) c" .LASF75: .string "__SHRT_MAX__ 0x7fff" .LASF311: .string "__amd64__ 1" .LASF24: .string "__SIZEOF_FLOAT__ 4" .LASF291: .string "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1" .LASF79: .string "__WCHAR_MAX__ 0x7fffffff" .LASF232: .string "__FLT128_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966F128" .LASF0: .string "__STDC__ 1" .LASF32: .string "__ORDER_PDP_ENDIAN__ 3412" .LASF302: .string "__GCC_ATOMIC_POINTER_LOCK_FREE 2" .LASF30: .string "__ORDER_LITTLE_ENDIAN__ 1234" .LASF39: .string "__WINT_TYPE__ unsigned int" .LASF333: .string "linux 1" .LASF10: .string "__ATOMIC_RELAXED 0" .LASF17: .string "__FINITE_MATH_ONLY__ 0" .LASF81: .string "__WINT_MAX__ 0xffffffffU" .LASF346: .string "main.c" .LASF264: .string "__DEC32_MANT_DIG__ 7" .LASF276: .string "__DEC64_EPSILON__ 1E-15DD" .LASF327: .string "__SSE2_MATH__ 1" .LASF145: .string "__GCC_IEC_559 2" .LASF27: .string "__SIZEOF_SIZE_T__ 8" .LASF246: .string "__FLT32X_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F32x" .LASF322: .string "__MMX__ 1" .LASF105: .string "__INT64_MAX__ 0x7fffffffffffffffL" .LASF83: .string "__PTRDIFF_MAX__ 0x7fffffffffffffffL" .LASF329: .string "__SEG_GS 1" .LASF99: .string "__SIG_ATOMIC_MAX__ 0x7fffffff" .LASF312: .string "__x86_64 1" .LASF323: .string "__SSE__ 1" .LASF66: .string "__UINT_FAST16_TYPE__ long unsigned int" .LASF248: .string "__FLT32X_HAS_INFINITY__ 1" .LASF133: .string "__INT_FAST16_WIDTH__ 64" .LASF205: .string "__FLT32_HAS_DENORM__ 1" .LASF150: .string "__FLT_RADIX__ 2" .LASF140: .string "__UINT_FAST32_MAX__ 0xffffffffffffffffUL" .LASF163: .string "__FLT_HAS_INFINITY__ 1" .LASF101: .string "__SIG_ATOMIC_WIDTH__ 32" .LASF134: .string "__INT_FAST32_MAX__ 0x7fffffffffffffffL" .LASF214: .string "__FLT64_DECIMAL_DIG__ 17" .LASF89: .string "__LONG_LONG_WIDTH__ 64" .LASF218: .string "__FLT64_DENORM_MIN__ 4.94065645841246544176568792868221372e-324F64" .LASF243: .string "__FLT32X_MAX__ 1.79769313486231570814527423731704357e+308F32x" .LASF97: .string "__UINTMAX_C(c) c ## UL" .LASF171: .string "__DBL_DECIMAL_DIG__ 17" .LASF331: .string "__linux 1" .LASF257: .string "__FLT64X_MAX__ 1.18973149535723176502126385303097021e+4932F64x" .LASF21: .string "__SIZEOF_LONG__ 8" .LASF40: .string "__INTMAX_TYPE__ long int" .LASF191: .string "__LDBL_HAS_DENORM__ 1" .LASF210: .string "__FLT64_MIN_EXP__ (-1021)" .LASF71: .string "__has_include(STR) __has_include__(STR)" .LASF294: .string "__GCC_ATOMIC_CHAR16_T_LOCK_FREE 2" .LASF314: .string "__SIZEOF_FLOAT80__ 16" .LASF285: .string "__REGISTER_PREFIX__ " .LASF15: .string "__ATOMIC_CONSUME 1" .LASF109: .string "__UINT64_MAX__ 0xffffffffffffffffUL" .LASF3: .string "__STDC_UTF_32__ 1" .LASF50: .string "__UINT16_TYPE__ short unsigned int" .LASF255: .string "__FLT64X_MAX_10_EXP__ 4932" .LASF127: .string "__UINT32_C(c) c ## U" .LASF319: .string "__k8 1" .LASF303: .string "__HAVE_SPECULATION_SAFE_VALUE 1" .LASF344: .string "g_my_private_global" .LASF270: .string "__DEC32_SUBNORMAL_MIN__ 0.000001E-95DF" .LASF229: .string "__FLT128_MAX__ 1.18973149535723176508575932662800702e+4932F128" .LASF73: .string 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.string "__FLT128_MAX_10_EXP__ 4932" .LASF286: .string "__USER_LABEL_PREFIX__ " .LASF196: .string "__FLT32_MIN_EXP__ (-125)" .LASF59: .string "__UINT_LEAST32_TYPE__ unsigned int" .LASF123: .string "__UINT8_C(c) c" .LASF223: .string "__FLT128_DIG__ 33" .LASF57: .string "__UINT_LEAST8_TYPE__ unsigned char" .LASF48: .string "__INT64_TYPE__ long int" .LASF121: .string "__INT_LEAST64_WIDTH__ 64" .LASF328: .string "__SEG_FS 1" .LASF288: .string "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1" .LASF348: .string "main" .LASF108: .string "__UINT32_MAX__ 0xffffffffU" .LASF304: .string "__GCC_HAVE_DWARF2_CFI_ASM 1" .LASF313: .string "__x86_64__ 1" .LASF110: .string "__INT_LEAST8_MAX__ 0x7f" .LASF274: .string "__DEC64_MIN__ 1E-383DD" .LASF168: .string "__DBL_MIN_10_EXP__ (-307)" .LASF338: .string "__DECIMAL_BID_FORMAT__ 1" .LASF287: .string "__GNUC_STDC_INLINE__ 1" .LASF213: .string "__FLT64_MAX_10_EXP__ 308" .LASF151: .string "__FLT_MANT_DIG__ 24"

stsp/binutils-ia16

1,450

binutils/testsuite/binutils-all/testranges-ia64.s

# Test .debug_info can reference .debug_ranges entries without ordering the # offsets strictly as increasing. .text start: .byte 1 sub: .byte 2 end: .section .debug_ranges,"",@progbits range: range_sub: data4.ua @secrel(sub), @secrel(end) data4.ua 0, 0 /* range terminator */ range_cu: data4.ua @secrel(start), @secrel(end) data4.ua 0, 0 /* range terminator */ .section .debug_info,"",@progbits data4.ua debugE - debugS /* Length of Compilation Unit Info */ debugS: .short 0x2 /* DWARF version number */ data4.ua @secrel(abbrev0) /* Offset Into Abbrev. Section */ .byte 0x4 /* Pointer Size (in bytes) */ .uleb128 0x1 /* (DIE (0xb) DW_TAG_compile_unit) */ data4.ua range_cu - range /* DW_AT_ranges */ .uleb128 0x2 /* (DIE (0x6d) DW_TAG_subprogram) */ .ascii "A\0" /* DW_AT_name */ data4.ua range_sub - range /* DW_AT_ranges */ debugE: .section .debug_abbrev,"",@progbits abbrev0: .uleb128 0x1 /* (abbrev code) */ .uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */ .byte 0x0 /* DW_children_no */ .uleb128 0x55 /* (DW_AT_ranges) */ .uleb128 0x6 /* (DW_FORM_data4) */ .byte 0x0 .byte 0x0 .uleb128 0x2 /* (abbrev code) */ .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ .byte 0x0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x55 /* (DW_AT_ranges) */ .uleb128 0x6 /* (DW_FORM_data4) */ .byte 0x0 .byte 0x0 .byte 0x0 /* abbrevs terminator */

stsp/binutils-ia16

1,642

binutils/testsuite/binutils-all/retain1.s

.global discard0 .section .bss.discard0,"aw" .type discard0, %object discard0: .zero 2 .global discard1 .section .bss.discard1,"aw" .type discard1, %object discard1: .zero 2 .global discard2 .section .data.discard2,"aw" .type discard2, %object discard2: .word 1 .section .bss.sdiscard0,"aw" .type sdiscard0, %object sdiscard0: .zero 2 .section .bss.sdiscard1,"aw" .type sdiscard1, %object sdiscard1: .zero 2 .section .data.sdiscard2,"aw" .type sdiscard2, %object sdiscard2: .word 1 .section .text.fndiscard0,"ax" .global fndiscard0 .type fndiscard0, %function fndiscard0: .word 0 .global retain0 .section .bss.retain0,"awR" .type retain0, %object retain0: .zero 2 .global retain1 .section .bss.retain1,"awR" .type retain1, %object retain1: .zero 2 .global retain2 .section .data.retain2,"awR" .type retain2, %object retain2: .word 1 .section .bss.sretain0,"awR" .type sretain0, %object sretain0: .zero 2 .section .bss.sretain1,"awR" .type sretain1, %object sretain1: .zero 2 .section .data.sretain2,"aRw" .type sretain2, %object sretain2: .word 1 .section .text.fnretain1,"Rax" .global fnretain1 .type fnretain1, %function fnretain1: .word 0 .section .text.fndiscard2,"ax" .global fndiscard2 .type fndiscard2, %function fndiscard2: .word 0 .section .bss.lsretain0,"awR" .type lsretain0.2, %object lsretain0.2: .zero 2 .section .bss.lsretain1,"aRw" .type lsretain1.1, %object lsretain1.1: .zero 2 .section .data.lsretain2,"aRw" .type lsretain2.0, %object lsretain2.0: .word 1 .section .text._start,"ax" .global _start .type _start, %function _start: .word 0

stsp/binutils-ia16

2,867

binutils/testsuite/binutils-all/dwo.s

/* Assembler source used to create an object file for testing readelf's and objdump's ability to process separate dwarf object files. Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* Create a .debug_str section for local use. This is also to check the ability to dump the same section twice, if it exists in both the main file and the separate debug info file. */ .section .debug_str,"MS",%progbits,1 string1: .asciz "debugfile.dwo" string2: .asciz "/path/to/dwo/files" string3: .asciz "/another/path/" .balign 2 string_end: /* Create a .debug_info section that contains the dwo links. */ .section .debug_info,"",%progbits .4byte debugE1 - debugS1 ;# Length of Compilation Unit Info debugS1: .short 0x4 ;# DWARF version number. .4byte 0x0 ;# Offset into .debug_abbrev section. .byte 0x4 ;# Pointer Size (in bytes). .uleb128 0x1 ;# Use abbrev #1. This needs strings from the .debug_str section. .4byte string1 .4byte string2 debugE1: .4byte debugE2 - debugS2 ;# Length of Compilation Unit Info debugS2: .short 0x4 ;# DWARF version number. .4byte 0x0 ;# Offset into .debug_abbrev section. .byte 0x4 ;# Pointer Size (in bytes). .uleb128 0x2 ;# Use abbrev #2. .asciz "file.dwo" .4byte string3 .8byte 0x12345678aabbccdd ;# Minimal section alignment on alpha-* is 2, so ensure no new invalid CU ;# will be started. .balign 2, 0 debugE2: .section .debug_abbrev,"",%progbits /* Create an abbrev containing a DWARF5 style dwo link. */ .uleb128 0x01 ;# Abbrev code. .uleb128 0x11 ;# DW_TAG_compile_unit .byte 0x00 ;# DW_children_no .uleb128 0x76 ;# DW_AT_dwo_name .uleb128 0x0e ;# DW_FORM_strp .uleb128 0x1b ;# DW_AT_comp_dir .uleb128 0x0e ;# DW_FORM_strp .byte 0x00 ;# End of abbrev .byte 0x00 /* Create an abbrev containing a GNU style dwo link. */ .uleb128 0x02 ;# Abbrev code. .uleb128 0x11 ;# DW_TAG_compile_unit .byte 0x00 ;# DW_children_no .uleb128 0x2130 ;# DW_AT_GNU_dwo_name .uleb128 0x08 ;# DW_FORM_string .uleb128 0x1b ;# DW_AT_comp_dir .uleb128 0x0e ;# DW_FORM_strp .uleb128 0x2131 ;# DW_AT_GNU_dwo_id .uleb128 0x07 ;# DW_FORM_data8 .byte 0x00 ;# End of abbrev .byte 0x00 .byte 0x0 ;# Abbrevs terminator

stsp/binutils-ia16

5,276

binutils/testsuite/binutils-all/dw2-1.S

/* This testcase is derived from a similar test in GDB. Copyright (C) 2008-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* Dummy function to provide debug information for. */ .text .globl _start _start: .4byte 0 .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .4byte 0 .global func_cu1_end func_cu1_end: .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: /* Debug information */ .section .debug_info .Lcu1_begin: /* CU header */ .4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */ .Lcu1_start: .2byte 2 /* DWARF Version */ .4byte .Labbrev1_begin /* Offset into abbrev section */ .byte 4 /* Pointer size */ /* CU die */ .uleb128 1 /* Abbrev: DW_TAG_compile_unit */ .4byte .Lline1_begin /* DW_AT_stmt_list */ .4byte .Lend_text1 /* DW_AT_high_pc */ .4byte .Lbegin_text1 /* DW_AT_low_pc */ .ascii "file1.txt\0" /* DW_AT_name */ .ascii "GNU C 3.3.3\0" /* DW_AT_producer */ .byte 1 /* DW_AT_language (C) */ /* func_cu1 */ .uleb128 2 /* Abbrev: DW_TAG_subprogram */ .byte 1 /* DW_AT_external */ .byte 1 /* DW_AT_decl_file */ .byte 2 /* DW_AT_decl_line */ .ascii "func_cu1\0" /* DW_AT_name */ .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */ .4byte .Lbegin_func_cu1 /* DW_AT_low_pc */ .4byte .Lend_func_cu1 /* DW_AT_high_pc */ .byte 1 /* DW_AT_frame_base: length */ .byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */ .Ltype_int: .uleb128 3 /* Abbrev: DW_TAG_base_type */ .ascii "int\0" /* DW_AT_name */ .byte 4 /* DW_AT_byte_size */ .byte 5 /* DW_AT_encoding */ .byte 0 /* End of children of CU */ .Lcu1_end: /* Line table */ .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start /* Initial length */ .Lline1_start: .2byte 2 /* Version */ .4byte .Lline1_lines - .Lline1_hdr /* header_length */ .Lline1_hdr: .byte 1 /* Minimum insn length */ .byte 1 /* default_is_stmt */ .byte 1 /* line_base */ .byte 1 /* line_range */ .byte 0x10 /* opcode_base */ /* Standard lengths */ .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 /* Include directories */ .byte 0 /* File names */ .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lbegin_func_cu1 .byte 3 /* DW_LNS_advance_line */ .sleb128 3 /* ... to 4 */ .byte 1 /* DW_LNS_copy */ .byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */ .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lend_func_cu1 .byte 0 /* DW_LNE_end_of_sequence */ .uleb128 1 .byte 1 .Lline1_end: /* Abbrev table */ .section .debug_abbrev .Labbrev1_begin: .uleb128 1 /* Abbrev code */ .uleb128 0x11 /* DW_TAG_compile_unit */ .byte 1 /* has_children */ .uleb128 0x10 /* DW_AT_stmt_list */ .uleb128 0x6 /* DW_FORM_data4 */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x25 /* DW_AT_producer */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x13 /* DW_AT_language */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 2 /* Abbrev code */ .uleb128 0x2e /* DW_TAG_subprogram */ .byte 0 /* has_children */ .uleb128 0x3f /* DW_AT_external */ .uleb128 0xc /* DW_FORM_flag */ .uleb128 0x3a /* DW_AT_decl_file */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3b /* DW_AT_decl_line */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x40 /* DW_AT_frame_base */ .uleb128 0xa /* DW_FORM_block1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 3 /* Abbrev code */ .uleb128 0x24 /* DW_TAG_base_type */ .byte 0 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0xb /* DW_AT_byte_size */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3e /* DW_AT_encoding */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */

stsp/binutils-ia16

4,450

binutils/testsuite/binutils-all/dwarf-attributes.S

/* Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* This file is intended to check the encoding and decoding of DWARF attributes. Currently only numeric attributes are tested, but this file should be extended to cover other types of attribute as well. */ .file "dwarf-attributes.S" .section .debug_info,"",%progbits .4byte .Ldebug_info_end - .Ldebug_info_start /* Length of Compilation Unit Info. */ .Ldebug_info_start: .2byte 0x5 /* DWARF version number. */ .byte 0x1 /* DW_UT_compile. */ .byte 0x4 /* Pointer Size (in bytes). */ .4byte .Ldebug_abbrevs /* Offset Into Abbrev. Section. */ /* Start of DIE 0xc. */ .uleb128 0x1 /* Using abbrev #1 */ .byte 1 /* Ordering: column major. */ .2byte 1 /* Language: C89. */ .byte 1 /* Visibility: local. */ .byte 1 /* Inline: inlined. */ .byte 1 /* Accessibility: public. */ .byte 1 /* Calling convention: normal. */ .byte 3,1,1,2 /* Discriminate list: range. */ .byte 1 /* Encoding: address. */ .byte 1 /* Identifier case: up. */ .byte 1 /* Virtuality: virtual. */ .byte 1 /* Decimal sign: unsigned. */ .byte 1 /* Endianity: big. */ .byte 1 /* Defaulted: in class. */ .uleb128 0x1 /* Using abbrev #1 */ .byte 0 /* Ordering: row major */ .2byte 0x0016 /* Language: Go. */ .byte 2 /* Visibility: exported. */ .byte 0 /* Inline: not. */ .byte 2 /* Accessibility: protected. */ .byte 5 /* Calling convention: pass by value. */ .byte 2,0,1 /* Discriminate list: label. */ .byte 0x12 /* Encoding: ASCII. */ .byte 0 /* Identifier case: sensitive. */ .byte 0 /* Virtuality: none. */ .byte 2 /* Decimal sign: leading overpunch. */ .byte 0 /* Endianity: default. */ .byte 0 /* Defaulted: no. */ .uleb128 0x1 /* Using abbrev #1 */ .byte -1 /* Ordering: undefined. */ .2byte 0x8001 /* Language: MIPS Assembler. */ .byte 3 /* Visibility: qualified. */ .byte 3 /* Inline: declared. */ .byte 3 /* Accessibility: private. */ .byte 0x40 /* Calling convention: Renesas SH. */ .byte 5,1,2,3,0,4 /* Discriminate list: range and label. */ .byte 0x81 /* Encoding: user specified. */ .byte 3 /* Identifier case: insensitive. */ .byte 2 /* Virtuality: pure. */ .byte 5 /* Decimal sign: trailing separate. */ .byte 0x50 /* Endianity: user specified. */ .byte 2 /* Defaulted: out of class. */ .byte 0 /* End of children of DIE 0xc. */ .Ldebug_info_end: .section .debug_abbrev,"",%progbits .Ldebug_abbrevs: .uleb128 0x1 /* (abbrev code) */ .uleb128 0x5555 /* (TAG: DW_TAG_lo_user + 0x1555) */ .byte 0 /* DW_children_no */ /* Attributes to be tested. Sorted by attribute value. */ .uleb128 0x9 /* (DW_AT_ordering) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x13 /* (DW_AT_language) */ .uleb128 0x05 /* (DW_FORM_data2) */ .uleb128 0x17 /* (DW_AT_visibility) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x20 /* (DW_AT_inline) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x32 /* (DW_AT_accessibility) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x36 /* (DW_AT_calling_convention) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x3d /* (DW_AT_discr_lists) */ .uleb128 0x0a /* (DW_FORM_block1) */ .uleb128 0x3e /* (DW_AT_encoding) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x42 /* (DW_AT_identifier_case) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x4c /* (DW_AT_virtuality) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x5e /* (DW_AT_decimal_sign) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x65 /* (DW_AT_endianity) */ .uleb128 0x0b /* (DW_FORM_data1) */ .uleb128 0x8b /* (DW_AT_defaulted) */ .uleb128 0x0b /* (DW_FORM_data1) */ .byte 0 /* End of abbreviation. */ .byte 0 .byte 0 /* End of abbreviations. */

stsp/binutils-ia16

1,451

binutils/testsuite/binutils-all/pr25662-pdp11.s

/* PR 25662: objcopy sets invalid sh_offset for the first section in a no_contents segment containing program headers. Several conditions are required for the bug to manifest: - The first loadable segment (which contains the program headers) must only contain SHT_NOBITS sections. .bss is the SHT_NOBITS section in this test. - The next loadable segment must have a !SHT_NOBITS loadable section. .data is the !SHT_NOBITS section in this test. - .bss must be positioned after .data in the executable file itself. - The size of .data must be such that the calculated VMA of the .bss section that follows it is not congruent with the file offset of .bss, modulo the p_align of its segment, i.e.: (VMA(.data) + sizeof(.data)) % (.bss_segment.p_align) != 0 This will force the sh_offset of .bss to be aligned so it appears within .data. - The size of .data must be larger than the program headers in the first loadable segment, so that the file offset of .bss is immediately after .data, and not padded to a valid alignment by the program headers. The bug originally only manifested for ELF targets, but there's no reason not to run this testcase for other file formats. This variant source for pdp11 uses .text rather than .section text, etc., because the latter are not supported, */ .bss a: .zero 0x2 .data c: .zero 0x201 .text .global _start _start: .long 0

stsp/binutils-ia16

21,697

binutils/testsuite/binutils-all/dw5.S

/* Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ .file "main.c" .text .Ltext0: .p2align 4,,15 .globl func .type func, %function func: .LFB0: /* main.c:5 */ .LM1: /* BLOCK 2 freq:10000 seq:0 */ /* PRED: ENTRY [100.0%] (FALLTHRU) */ /* main.c:5 */ .LM2: .dc.b 0 /* SUCC: */ .dc.b 0 .LFE0: .size func, .-func .section .text.startup,"ax",%progbits .p2align 4,,15 .globl main .type main, %function main: .LFB1: /* main.c:6 */ .LM3: .LVL0: /* BLOCK 2 freq:10000 seq:0 */ /* PRED: ENTRY [100.0%] (FALLTHRU) */ .dc.b 0 /* main.c:6 */ .LM4: .dc.b 0 .LVL1: .dc.b 0 .LVL2: .dc.b 0 /* SUCC: EXIT [100.0%] */ .dc.b 0 .LFE1: .size main, .-main .ifdef HPUX pvar .comm 8 yvar .comm 4 .else .comm pvar,8,8 .comm yvar,4,4 .endif .globl xvar .data .align 4 .type xvar, %object .size xvar, 4 xvar: .4byte 42 .text .Letext0: .section .debug_info,"",%progbits .Ldebug_info0: .4byte 0x160 /* Length of Compilation Unit Info */ .2byte 0x5 /* DWARF version number */ .byte 0x1 /* DW_UT_compile */ .byte 0x8 /* Pointer Size (in bytes) */ .4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */ .uleb128 0x6 /* (DIE (0xc) DW_TAG_compile_unit) */ .4byte .LASF21 /* DW_AT_producer: "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" */ .byte 0x1d /* DW_AT_language */ .4byte .LASF0 /* DW_AT_name: "main.c" */ .4byte .LASF1 /* DW_AT_comp_dir: "" */ .4byte .LLRL2 /* DW_AT_ranges */ .8byte 0 /* DW_AT_low_pc */ .4byte .Ldebug_line0 /* DW_AT_stmt_list */ .uleb128 0x1 /* (DIE (0x2a) DW_TAG_base_type) */ .byte 0x1 /* DW_AT_byte_size */ .byte 0x8 /* DW_AT_encoding */ .4byte .LASF2 /* DW_AT_name: "unsigned char" */ .uleb128 0x1 /* (DIE (0x31) DW_TAG_base_type) */ .byte 0x2 /* DW_AT_byte_size */ .byte 0x7 /* DW_AT_encoding */ .4byte .LASF3 /* DW_AT_name: "short unsigned int" */ .uleb128 0x1 /* (DIE (0x38) DW_TAG_base_type) */ .byte 0x4 /* DW_AT_byte_size */ .byte 0x7 /* DW_AT_encoding */ .4byte .LASF4 /* DW_AT_name: "unsigned int" */ .uleb128 0x1 /* (DIE (0x3f) DW_TAG_base_type) */ .byte 0x8 /* DW_AT_byte_size */ .byte 0x7 /* DW_AT_encoding */ .4byte .LASF5 /* DW_AT_name: "long unsigned int" */ .uleb128 0x1 /* (DIE (0x46) DW_TAG_base_type) */ .byte 0x1 /* DW_AT_byte_size */ .byte 0x6 /* DW_AT_encoding */ .4byte .LASF6 /* DW_AT_name: "signed char" */ .uleb128 0x1 /* (DIE (0x4d) DW_TAG_base_type) */ .byte 0x2 /* DW_AT_byte_size */ .byte 0x5 /* DW_AT_encoding */ .4byte .LASF7 /* DW_AT_name: "short int" */ .uleb128 0x7 /* (DIE (0x54) DW_TAG_base_type) */ .byte 0x4 /* DW_AT_byte_size */ .byte 0x5 /* DW_AT_encoding */ .ascii "int\0" /* DW_AT_name */ .uleb128 0x1 /* (DIE (0x5b) DW_TAG_base_type) */ .byte 0x8 /* DW_AT_byte_size */ .byte 0x5 /* DW_AT_encoding */ .4byte .LASF8 /* DW_AT_name: "long int" */ .uleb128 0x1 /* (DIE (0x62) DW_TAG_base_type) */ .byte 0x8 /* DW_AT_byte_size */ .byte 0x7 /* DW_AT_encoding */ .4byte .LASF9 /* DW_AT_name: "sizetype" */ .uleb128 0x3 /* (DIE (0x69) DW_TAG_pointer_type) */ /* DW_AT_byte_size (0x8) */ .4byte 0x6e /* DW_AT_type */ .uleb128 0x1 /* (DIE (0x6e) DW_TAG_base_type) */ .byte 0x1 /* DW_AT_byte_size */ .byte 0x6 /* DW_AT_encoding */ .4byte .LASF10 /* DW_AT_name: "char" */ .uleb128 0x8 /* (DIE (0x75) DW_TAG_variable) */ .4byte .LASF11 /* DW_AT_name: "__environ" */ .byte 0x2 /* DW_AT_decl_file (/usr/include/unistd.h) */ .2byte 0x222 /* DW_AT_decl_line */ .4byte 0x81 /* DW_AT_type */ /* DW_AT_external */ /* DW_AT_declaration */ .uleb128 0x3 /* (DIE (0x81) DW_TAG_pointer_type) */ /* DW_AT_byte_size (0x8) */ .4byte 0x69 /* DW_AT_type */ .uleb128 0x2 /* (DIE (0x86) DW_TAG_variable) */ .4byte .LASF12 /* DW_AT_name: "optarg" */ /* DW_AT_decl_file (3, /usr/include/getopt.h) */ .byte 0x39 /* DW_AT_decl_line */ .4byte 0x69 /* DW_AT_type */ /* DW_AT_external */ /* DW_AT_declaration */ .uleb128 0x2 /* (DIE (0x90) DW_TAG_variable) */ .4byte .LASF13 /* DW_AT_name: "optind" */ /* DW_AT_decl_file (3, /usr/include/getopt.h) */ .byte 0x47 /* DW_AT_decl_line */ .4byte 0x54 /* DW_AT_type */ /* DW_AT_external */ /* DW_AT_declaration */ .uleb128 0x2 /* (DIE (0x9a) DW_TAG_variable) */ .4byte .LASF14 /* DW_AT_name: "opterr" */ /* DW_AT_decl_file (3, /usr/include/getopt.h) */ .byte 0x4c /* DW_AT_decl_line */ .4byte 0x54 /* DW_AT_type */ /* DW_AT_external */ /* DW_AT_declaration */ .uleb128 0x2 /* (DIE (0xa4) DW_TAG_variable) */ .4byte .LASF15 /* DW_AT_name: "optopt" */ /* DW_AT_decl_file (3, /usr/include/getopt.h) */ .byte 0x50 /* DW_AT_decl_line */ .4byte 0x54 /* DW_AT_type */ /* DW_AT_external */ /* DW_AT_declaration */ .uleb128 0x4 /* (DIE (0xae) DW_TAG_variable) */ .4byte .LASF16 /* DW_AT_name: "xvar" */ /* DW_AT_decl_file (1, main.c) */ .byte 0x2 /* DW_AT_decl_line */ .4byte 0x54 /* DW_AT_type */ /* DW_AT_external */ .uleb128 0x9 /* DW_AT_location */ .byte 0x3 /* DW_OP_addr */ .8byte 0x1234 .uleb128 0x4 /* (DIE (0xc2) DW_TAG_variable) */ .4byte .LASF17 /* DW_AT_name: "yvar" */ /* DW_AT_decl_file (1, main.c) */ .byte 0x3 /* DW_AT_decl_line */ .4byte 0x54 /* DW_AT_type */ /* DW_AT_external */ .uleb128 0x9 /* DW_AT_location */ .byte 0x3 /* DW_OP_addr */ .8byte 0x1234 .uleb128 0x4 /* (DIE (0xd6) DW_TAG_variable) */ .4byte .LASF18 /* DW_AT_name: "pvar" */ /* DW_AT_decl_file (1, main.c) */ .byte 0x4 /* DW_AT_decl_line */ .4byte 0xea /* DW_AT_type */ /* DW_AT_external */ .uleb128 0x9 /* DW_AT_location */ .byte 0x3 /* DW_OP_addr */ .8byte 0x1234 .uleb128 0x3 /* (DIE (0xea) DW_TAG_pointer_type) */ /* DW_AT_byte_size (0x8) */ .4byte 0x54 /* DW_AT_type */ .uleb128 0x9 /* (DIE (0xef) DW_TAG_subprogram) */ /* DW_AT_external */ .4byte .LASF22 /* DW_AT_name: "main" */ .byte 0x1 /* DW_AT_decl_file (main.c) */ .byte 0x6 /* DW_AT_decl_line */ /* DW_AT_prototyped */ .4byte 0x54 /* DW_AT_type */ .8byte 0x1234 /* DW_AT_low_pc */ .8byte 0x5678 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_AT_frame_base */ .byte 0x9c /* DW_OP_call_frame_cfa */ /* DW_AT_call_all_calls */ .4byte 0x13e /* DW_AT_sibling */ .uleb128 0x5 /* (DIE (0x110) DW_TAG_formal_parameter) */ .4byte .LASF19 /* DW_AT_name: "argc" */ /* DW_AT_decl_file (1, main.c) */ /* DW_AT_decl_line (0x6) */ .4byte 0x54 /* DW_AT_type */ .4byte .LLST0 /* DW_AT_location */ .uleb128 0x5 /* (DIE (0x11d) DW_TAG_formal_parameter) */ .4byte .LASF20 /* DW_AT_name: "argv" */ /* DW_AT_decl_file (1, main.c) */ /* DW_AT_decl_line (0x6) */ .4byte 0x81 /* DW_AT_type */ .4byte .LLST1 /* DW_AT_location */ .uleb128 0xa /* (DIE (0x12a) DW_TAG_call_site) */ .8byte 0x12345 /* DW_AT_call_return_pc */ .4byte 0x157 /* DW_AT_call_origin */ .uleb128 0xb /* (DIE (0x137) DW_TAG_call_site_parameter) */ .uleb128 0x1 /* DW_AT_location */ .byte 0x55 /* DW_OP_reg5 */ .uleb128 0x1 /* DW_AT_call_value */ .byte 0x30 /* DW_OP_lit0 */ .byte 0 /* end of children of DIE 0x12a */ .byte 0 /* end of children of DIE 0xef */ .uleb128 0xc /* (DIE (0x13e) DW_TAG_subprogram) */ /* DW_AT_external */ .4byte .LASF23 /* DW_AT_name: "func" */ .byte 0x1 /* DW_AT_decl_file (main.c) */ .byte 0x5 /* DW_AT_decl_line */ /* DW_AT_prototyped */ .8byte 0x1234 /* DW_AT_low_pc */ .8byte 0x5678 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_AT_frame_base */ .byte 0x9c /* DW_OP_call_frame_cfa */ /* DW_AT_call_all_calls */ .uleb128 0xd /* (DIE (0x157) DW_TAG_subprogram) */ /* DW_AT_external */ /* DW_AT_declaration */ .4byte .LASF24 /* DW_AT_linkage_name: "alarm" */ .4byte .LASF24 /* DW_AT_name: "alarm" */ .byte 0x2 /* DW_AT_decl_file (/usr/include/unistd.h) */ .2byte 0x1b3 /* DW_AT_decl_line */ .byte 0 /* end of children of DIE 0xc */ .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 /* (abbrev code) */ .uleb128 0x24 /* (TAG: DW_TAG_base_type) */ .byte 0 /* DW_children_no */ .uleb128 0xb /* (DW_AT_byte_size) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3e /* (DW_AT_encoding) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .byte 0 .byte 0 .uleb128 0x2 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 3 /* (/usr/include/getopt.h) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x3c /* (DW_AT_declaration) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .byte 0 .byte 0 .uleb128 0x3 /* (abbrev code) */ .uleb128 0xf /* (TAG: DW_TAG_pointer_type) */ .byte 0 /* DW_children_no */ .uleb128 0xb /* (DW_AT_byte_size) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 8 .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .byte 0 .byte 0 .uleb128 0x4 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 1 /* (main.c) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .byte 0 .byte 0 .uleb128 0x5 /* (abbrev code) */ .uleb128 0x5 /* (TAG: DW_TAG_formal_parameter) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 1 /* (main.c) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 6 .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .uleb128 0x6 /* (abbrev code) */ .uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x25 /* (DW_AT_producer) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x13 /* (DW_AT_language) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x1f /* (DW_FORM_line_strp) */ .uleb128 0x1b /* (DW_AT_comp_dir) */ .uleb128 0x1f /* (DW_FORM_line_strp) */ .uleb128 0x55 /* (DW_AT_ranges) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x10 /* (DW_AT_stmt_list) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .uleb128 0x7 /* (abbrev code) */ .uleb128 0x24 /* (TAG: DW_TAG_base_type) */ .byte 0 /* DW_children_no */ .uleb128 0xb /* (DW_AT_byte_size) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3e /* (DW_AT_encoding) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .byte 0 .byte 0 .uleb128 0x8 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0x5 /* (DW_FORM_data2) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x3c /* (DW_AT_declaration) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .byte 0 .byte 0 .uleb128 0x9 /* (abbrev code) */ .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x27 /* (DW_AT_prototyped) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x12 /* (DW_AT_high_pc) */ .uleb128 0x7 /* (DW_FORM_data8) */ .uleb128 0x40 /* (DW_AT_frame_base) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .uleb128 0x7a /* (DW_AT_call_all_calls) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x1 /* (DW_AT_sibling) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .byte 0 .byte 0 .uleb128 0xa /* (abbrev code) */ .uleb128 0x48 /* (TAG: DW_TAG_call_site) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x7d /* (DW_AT_call_return_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x7f /* (DW_AT_call_origin) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .byte 0 .byte 0 .uleb128 0xb /* (abbrev code) */ .uleb128 0x49 /* (TAG: DW_TAG_call_site_parameter) */ .byte 0 /* DW_children_no */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .uleb128 0x7e /* (DW_AT_call_value) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .byte 0 .byte 0 .uleb128 0xc /* (abbrev code) */ .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ .byte 0 /* DW_children_no */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x27 /* (DW_AT_prototyped) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x12 /* (DW_AT_high_pc) */ .uleb128 0x7 /* (DW_FORM_data8) */ .uleb128 0x40 /* (DW_AT_frame_base) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .uleb128 0x7a /* (DW_AT_call_all_calls) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .byte 0 .byte 0 .uleb128 0xd /* (abbrev code) */ .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ .byte 0 /* DW_children_no */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x3c /* (DW_AT_declaration) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x6e /* (DW_AT_linkage_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0x5 /* (DW_FORM_data2) */ .byte 0 .byte 0 .byte 0 .section .debug_loclists,"",%progbits .4byte .Ldebug_loc2-.Ldebug_loc1 /* Length of Location Lists */ .Ldebug_loc1: .2byte 0x5 /* DWARF Version */ .byte 0x8 /* Address Size */ .byte 0 /* Segment Size */ .4byte 0 /* Offset Entry Count */ .Ldebug_loc0: .LLST0: .byte 0x6 /* DW_LLE_base_address (*.LLST0) */ .8byte 0x1234 /* Base address (*.LLST0) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */ .uleb128 .LVL0-.LVL0 /* Location list begin address (*.LLST0) */ .uleb128 .LVL1-.LVL0 /* Location list end address (*.LLST0) */ .uleb128 0x1 /* Location expression size */ .byte 0x55 /* DW_OP_reg5 */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */ .uleb128 .LVL1-.LVL0 /* Location list begin address (*.LLST0) */ .uleb128 .LFE1-.LVL0 /* Location list end address (*.LLST0) */ .uleb128 0x4 /* Location expression size */ .byte 0xa3 /* DW_OP_entry_value */ .uleb128 0x1 .byte 0x55 /* DW_OP_reg5 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0 /* DW_LLE_end_of_list (*.LLST0) */ .LLST1: .byte 0x6 /* DW_LLE_base_address (*.LLST1) */ .8byte 0x1234 /* Base address (*.LLST1) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */ .uleb128 .LVL0-.LVL0 /* Location list begin address (*.LLST1) */ .uleb128 .LVL2-1-.LVL0 /* Location list end address (*.LLST1) */ .uleb128 0x1 /* Location expression size */ .byte 0x54 /* DW_OP_reg4 */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */ .uleb128 .LVL2-1-.LVL0 /* Location list begin address (*.LLST1) */ .uleb128 .LFE1-.LVL0 /* Location list end address (*.LLST1) */ .uleb128 0x4 /* Location expression size */ .byte 0xa3 /* DW_OP_entry_value */ .uleb128 0x1 .byte 0x54 /* DW_OP_reg4 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0 /* DW_LLE_end_of_list (*.LLST1) */ .Ldebug_loc2: .section .debug_aranges,"",%progbits .4byte 0x3c /* Length of Address Ranges Info */ .2byte 0x2 /* DWARF Version */ .4byte .Ldebug_info0 /* Offset of Compilation Unit Info */ .byte 0x8 /* Size of Address */ .byte 0 /* Size of Segment Descriptor */ .2byte 0 /* Pad to 16 byte boundary */ .2byte 0 .8byte 0x1234 /* Address */ .8byte 0x4567 /* Length */ .8byte 0x1234 /* Address */ .8byte 0x5678 /* Length */ .8byte 0 .8byte 0 .section .debug_rnglists,"",%progbits .Ldebug_ranges0: .4byte .Ldebug_ranges3-.Ldebug_ranges2 /* Length of Range Lists */ .Ldebug_ranges2: .2byte 0x5 /* DWARF Version */ .byte 0x8 /* Address Size */ .byte 0 /* Segment Size */ .4byte 0 /* Offset Entry Count */ .LLRL2: .byte 0x7 /* DW_RLE_start_length (*.LLRL2) */ .8byte 0x1234 /* Range begin address (*.LLRL2) */ .uleb128 .Letext0-.Ltext0 /* Range length (*.LLRL2) */ .byte 0x7 /* DW_RLE_start_length (*.LLRL2) */ .8byte 0x1234 /* Range begin address (*.LLRL2) */ .uleb128 .LFE1-.LFB1 /* Range length (*.LLRL2) */ .byte 0 /* DW_RLE_end_of_list (*.LLRL2) */ .Ldebug_ranges3: .section .debug_line,"",%progbits .Ldebug_line0: .4byte .LELT0-.LSLT0 /* Length of Source Line Info */ .LSLT0: .2byte 0x5 /* DWARF Version */ .byte 0x8 /* Address Size */ .byte 0 /* Segment Size */ .4byte .LELTP0-.LASLTP0 /* Prolog Length */ .LASLTP0: .byte 0x1 /* Minimum Instruction Length */ .byte 0x1 /* Maximum Operations Per Instruction */ .byte 0x1 /* Default is_stmt_start flag */ .byte 0xf6 /* Line Base Value (Special Opcodes) */ .byte 0xf2 /* Line Range Value (Special Opcodes) */ .byte 0xd /* Special Opcode Base */ .byte 0 /* opcode: 0x1 has 0 args */ .byte 0x1 /* opcode: 0x2 has 1 arg */ .byte 0x1 /* opcode: 0x3 has 1 arg */ .byte 0x1 /* opcode: 0x4 has 1 arg */ .byte 0x1 /* opcode: 0x5 has 1 arg */ .byte 0 /* opcode: 0x6 has 0 args */ .byte 0 /* opcode: 0x7 has 0 args */ .byte 0 /* opcode: 0x8 has 0 args */ .byte 0x1 /* opcode: 0x9 has 1 arg */ .byte 0 /* opcode: 0xa has 0 args */ .byte 0 /* opcode: 0xb has 0 args */ .byte 0x1 /* opcode: 0xc has 1 arg */ .byte 0x1 /* Directory entry format count */ .uleb128 0x1 /* DW_LNCT_path */ .uleb128 0x1f /* DW_FORM_line_strp */ .uleb128 0x3 /* Directories count */ .4byte .LASF1 /* Directory Entry: 0: "" */ .4byte .LASF25 /* Directory Entry: 0: "" */ .4byte .LASF26 /* Directory Entry: 0: "/usr/include" */ .byte 0x2 /* File name entry format count */ .uleb128 0x1 /* DW_LNCT_path */ .uleb128 0x1f /* DW_FORM_line_strp */ .uleb128 0x2 /* DW_LNCT_directory_index */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x4 /* File names count */ .4byte .LASF0 /* File Entry: 0: "main.c" */ .byte 0 .4byte .LASF27 /* File Entry: 0: "main.c" */ .byte 0x1 .4byte .LASF28 /* File Entry: 0: "unistd.h" */ .byte 0x2 .4byte .LASF29 /* File Entry: 0: "getopt.h" */ .byte 0x2 .LELTP0: .byte 0 /* set address *.LM3 */ .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0x1c /* line 6 */ .byte 0 /* set address *.LM4 */ .uleb128 0x9 .byte 0x2 .8byte 0x12346 .byte 0x1 /* copy line 6 */ .byte 0 /* set address *.LFE1 */ .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0 /* end sequence */ .uleb128 0x1 .byte 0x1 .byte 0 /* set address *.LM1 */ .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0x1b /* line 5 */ .byte 0 /* set address *.LM2 */ .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0x1 /* copy line 5 */ .byte 0 /* set address *.Letext0 */ .uleb128 0x9 .byte 0x2 .8byte 0x1234 .byte 0 /* end sequence */ .uleb128 0x1 .byte 0x1 .LELT0: .section .debug_str,"MS",%progbits,1 .LASF4: .asciz "unsigned int" .LASF15: .asciz "optopt" .LASF22: .asciz "main" .LASF6: .asciz "signed char" .LASF16: .asciz "xvar" .LASF5: .asciz "long unsigned int" .LASF14: .asciz "opterr" .LASF21: .asciz "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" .LASF2: .asciz "unsigned char" .LASF10: .asciz "char" .LASF13: .asciz "optind" .LASF8: .asciz "long int" .LASF19: .asciz "argc" .LASF3: .asciz "short unsigned int" .LASF17: .asciz "yvar" .LASF18: .asciz "pvar" .LASF11: .asciz "__environ" .LASF23: .asciz "func" .LASF12: .asciz "optarg" .LASF7: .asciz "short int" .LASF24: .asciz "alarm" .LASF9: .asciz "sizetype" .LASF20: .asciz "argv" .section .debug_line_str,"MS",%progbits,1 .LASF1: .asciz "" .LASF25: .asciz "" .LASF29: .asciz "getopt.h" .LASF28: .asciz "unistd.h" .LASF0: .asciz "main.c" .LASF27: .asciz "main.c" .LASF26: .asciz "/usr/include" .ident "GCC: (GNU) 7.0.1 20170218 (experimental)" .section .note.GNU-stack,"",%progbits

stsp/binutils-ia16

5,436

binutils/testsuite/binutils-all/dw5-op.S

/* Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ .file "main.c" .text .Letext0: .section .debug_info,"",%progbits .Ldebug_info0: .4byte 0x4e /* Length of Compilation Unit Info */ .2byte 0x5 /* DWARF version number */ .byte 0x1 /* DW_UT_compile */ .byte 0x8 /* Pointer Size (in bytes) */ .4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */ .uleb128 0x3 /* (DIE (0xc) DW_TAG_compile_unit) */ .4byte .LASF21 /* DW_AT_producer: "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" */ .byte 0x1d /* DW_AT_language */ .4byte .LASF0 /* DW_AT_name: "main.c" */ .4byte .LASF1 /* DW_AT_comp_dir: "" */ .4byte .LLRL2 /* DW_AT_ranges */ .8byte 0 /* DW_AT_low_pc */ .4byte .Ldebug_line0 /* DW_AT_stmt_list */ .uleb128 0x1 /* (DIE (0x2a) DW_TAG_base_type) */ .byte 0x4 /* DW_AT_byte_size */ .byte 0x5 /* DW_AT_encoding */ .4byte .LASF2 /* DW_AT_name: "short int" */ .uleb128 0x2 /* (DIE (0x31) DW_TAG_variable) */ .4byte .LASF16 /* DW_AT_name: "xvar" */ /* DW_AT_decl_file (1, main.c) */ .byte 0x2 /* DW_AT_decl_line */ .4byte 0x2a /* DW_AT_type */ /* DW_AT_external */ .uleb128 0x9 /* DW_AT_location */ .byte 0x3 /* DW_OP_addr */ .8byte 0x1234 .uleb128 0x2 /* (DIE (0x45) DW_TAG_variable) */ .4byte .LASF17 /* DW_AT_name: "yvar" */ /* DW_AT_decl_file (1, main.c) */ .byte 0x3 /* DW_AT_decl_line */ .4byte 0x2a /* DW_AT_type */ /* DW_AT_external */ .uleb128 0x2 /* DW_AT_location */ .byte 0xa1 /* DW_OP_addrx */ .byte 0x0 .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 /* (abbrev code) */ .uleb128 0x24 /* (TAG: DW_TAG_base_type) */ .byte 0 /* DW_children_no */ .uleb128 0xb /* (DW_AT_byte_size) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3e /* (DW_AT_encoding) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .byte 0 .byte 0 .uleb128 0x2 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 1 /* (main.c) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x3f /* (DW_AT_external) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .byte 0 .byte 0 .uleb128 0x3 /* (abbrev code) */ .uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x25 /* (DW_AT_producer) */ .uleb128 0xe /* (DW_FORM_strp) */ .uleb128 0x13 /* (DW_AT_language) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x1f /* (DW_FORM_line_strp) */ .uleb128 0x1b /* (DW_AT_comp_dir) */ .uleb128 0x1f /* (DW_FORM_line_strp) */ .uleb128 0x55 /* (DW_AT_ranges) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x10 /* (DW_AT_stmt_list) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .byte 0 .section .debug_line,"",%progbits .Ldebug_line0: .4byte .LELT0-.LSLT0 /* Length of Source Line Info */ .LSLT0: .2byte 0x5 /* DWARF Version */ .byte 0x8 /* Address Size */ .byte 0 /* Segment Size */ .4byte .LASF0 /* File Entry: 0: "main.c" */ .byte 0 .LELT0: .section .debug_str,"MS",%progbits,1 .LASF22: .asciz "main" .LASF16: .asciz "xvar" .LASF21: .asciz "GNU C11 7.0.1 20170218 (experimental) -mtune=generic -march=x86-64 -gdwarf-5 -O2" .LASF17: .asciz "yvar" .LASF7: .asciz "short int" .section .debug_line_str,"MS",%progbits,1 .LASF1: .asciz "" .LASF25: .asciz "" .LASF0: .asciz "main.c"

stsp/binutils-ia16

2,212

binutils/testsuite/binutils-all/linkdebug.s

/* Assembler source used to create an object file for testing readelf's and objdump's ability to process separate debug information files. Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* This is the separate debug info file. */ /* Create .note.gnu.build-id note for use by the .gnu_debugaltlink in the main object file. */ .section .note.gnu.build-id,"a",%note .balign 4 .dc.l 0x04 ;# Name size .dc.l 0x18 ;# Description size .dc.l 0x03 ;# Type .asciz "GNU" ;# Name .dc.b 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 .dc.b 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff .dc.b 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef /* Create a .debug_abbrev section for use by the .debug_info section in the main object file. */ .section .debug_abbrev,"",%progbits abbrevs: .uleb128 0x01 ;# Abbrev code. .uleb128 0x11 ;# DW_TAG_compile_unit .byte 0x00 ;# DW_children_no .uleb128 0x03 ;# DW_AT_name .uleb128 0x0e ;# DW_FORM_strp .byte 0x00 ;# End of abbrev .byte 0x00 .uleb128 0x02 ;# Abbrev code. .uleb128 0x2e ;# DW_TAG_subprogram .byte 0x00 ;# DW_children_no .uleb128 0x03 ;# DW_AT_name .uleb128 0x1f21 ;# DW_FORM_GNU_strp_alt .byte 0x0 ;# End of abbrev .byte 0x0 .byte 0x0 ;# Abbrevs terminator /* Create a .debug_str section for remote use. This is also to check the ability to dump the same section twice, if it exists in both the main file and the separate debug info file. */ .section .debug_str,"MS",%progbits,1 string3: .asciz "string-3" .asciz "string-4" .balign 2 string_end:

stsp/binutils-ia16

1,086

binutils/testsuite/binutils-all/readelf.s

There are .* section headers, starting at offset .*: Section Headers: +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 # On the normal MIPS systems, sections must be aligned to 16 byte # boundaries. On IA64, text sections are aligned to 16 byte boundaries. +\[ 1\] .* +PROGBITS +00000000 0000(34|38|40) 0000(08|10) 00 +AX +0 +0 +(.|..) +\[ 2\] .rel.* +REL. +0+ 0+.* 0000.. 0. +I +.+ +1 +4 # MIPS targets put .rela.text here. #... +\[ .\] .* +PROGBITS +00000000 0000(3c|40|44|48|50) 0000(04|10) 00 +WA +0 +0 +(.|..) +\[ .\] .* +NOBITS +00000000 0000(40|44|48|4c|60) 000000 00 +WA +0 +0 +(.|..) # ARM targets put .ARM.attributes here. # MIPS targets put .reginfo, .mdebug, .MIPS.abiflags and .gnu.attributes here. # v850 targets put .call_table_data and .call_table_text here. # riscv targets put .riscv.attributes here. #... +\[..\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +.+ +4 +\[..\] .strtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +1 +\[..\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +. Key to Flags: #...

stsp/binutils-ia16

11,323

binutils/testsuite/binutils-all/locview-2.s

.text .Ltext0: .LFB0: /* locview.c:1 */ .LM1: /* view -0 */ /* locview.c:2 */ .LM2: /* view 1 */ .LVL0: /* DEBUG i => 0 */ /* locview.c:3 */ .LM3: /* view 2 */ /* DEBUG j => 0x1 */ /* locview.c:4 */ .LM4: /* view 3 */ /* DEBUG i => 0x2 */ /* locview.c:5 */ .LM5: /* view 4 */ /* DEBUG j => 0x3 */ /* locview.c:6 */ .LM6: /* view 5 */ /* DEBUG k => 0x4 */ /* DEBUG l => 0x4 */ /* locview.c:7 */ .LM7: /* view 6 */ /* DEBUG k => 0x5 */ /* DEBUG l => 0x5 */ /* locview.c:8 */ .LM8: /* view 7 */ /* DEBUG k => 0x6 */ /* DEBUG l => 0x6 */ /* locview.c:9 */ .LM9: /* view 8 */ .byte 0 .LFE0: .Letext0: .section .debug_info .Ldebug_info0: .LIbase: .4byte .LIend - .LIstart /* Length of Compilation Unit Info */ .LIstart: .2byte 0x5 /* DWARF version number */ .byte 0x1 /* DW_UT_compile */ .byte 0x4 /* Pointer Size (in bytes) */ .4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */ .LIcu: .uleb128 0x2 /* (DIE (cu) DW_TAG_compile_unit) */ .ascii "hand-crafted based on GCC output\0" .byte 0x1d /* DW_AT_language */ .ascii "locview.c\0" .ascii "/tmp\0" .4byte 0 /* DW_AT_low_pc */ .LIsubf: .uleb128 0x3 /* (DIE (subf) DW_TAG_subprogram) */ .ascii "f\0" /* DW_AT_name */ .byte 0x1 /* DW_AT_decl_file (locview.c) */ .byte 0x1 /* DW_AT_decl_line */ .4byte .LIint-.LIbase /* DW_AT_type */ .4byte .LFB0 /* DW_AT_low_pc */ .4byte 1 /* .LFE0-.LFB0 */ /* DW_AT_high_pc */ .uleb128 0x1 /* DW_AT_frame_base */ .byte 0x9c /* DW_OP_call_frame_cfa */ /* DW_AT_call_all_calls */ .4byte .LIint - .LIbase /* DW_AT_sibling */ .LIvari: .uleb128 0x1 /* (DIE (vari) DW_TAG_variable) */ .ascii "i\0" /* DW_AT_name */ /* DW_AT_decl_file (1, locview.c) */ .byte 0x2 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LLST0 /* DW_AT_location */ .4byte .LVUS0 /* DW_AT_GNU_locviews */ .LIvarj: .uleb128 0x1 /* (DIE (varj) DW_TAG_variable) */ .ascii "j\0" /* DW_AT_name */ /* DW_AT_decl_file (1, locview.c) */ .byte 0x3 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LLST1 /* DW_AT_location */ .4byte .LVUS1 /* DW_AT_GNU_locviews */ .LIvark: .uleb128 0x5 /* (DIE (vark) DW_TAG_variable) */ .ascii "k\0" /* DW_AT_name */ /* DW_AT_decl_file (1, locview.c) */ .byte 0x6 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LVUS2 /* DW_AT_GNU_locviews */ .4byte .LLST2 /* DW_AT_location */ .LIvarl: .uleb128 0x6 /* (DIE (varl) DW_TAG_variable) */ .ascii "l\0" /* DW_AT_name */ /* DW_AT_decl_file (1, locview.c) */ .byte 0x6 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LLST3 /* DW_AT_location */ .byte 0 /* end of children of DIE subf */ .LIint: .uleb128 0x4 /* (DIE (int) DW_TAG_base_type) */ .byte 0x4 /* DW_AT_byte_size */ .byte 0x5 /* DW_AT_encoding */ .ascii "int\0" /* DW_AT_name */ .byte 0 /* end of children of DIE cu */ .LIend: .section .debug_abbrev .Ldebug_abbrev0: .LAbrv1: .uleb128 0x1 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 1 /* (locview.c) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .uleb128 0x2137 /* (DW_AT_GNU_locviews) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .LAbrv2: .uleb128 0x2 /* (abbrev code) */ .uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x25 /* (DW_AT_producer) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x13 /* (DW_AT_language) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x1b /* (DW_AT_comp_dir) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .byte 0 .byte 0 .LAbrv3: .uleb128 0x3 /* (abbrev code) */ .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x12 /* (DW_AT_high_pc) */ .uleb128 0x6 /* (DW_FORM_data4) */ .uleb128 0x40 /* (DW_AT_frame_base) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .uleb128 0x7a /* (DW_AT_call_all_calls) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x1 /* (DW_AT_sibling) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .byte 0 .byte 0 .LAbrv4: .uleb128 0x4 /* (abbrev code) */ .uleb128 0x24 /* (TAG: DW_TAG_base_type) */ .byte 0 /* DW_children_no */ .uleb128 0xb /* (DW_AT_byte_size) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3e /* (DW_AT_encoding) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .byte 0 .byte 0 .LAbrv5: .uleb128 0x5 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 1 /* (locview.c) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x2137 /* (DW_AT_GNU_locviews) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .LAbrv6: .uleb128 0x6 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0x21 /* (DW_FORM_implicit_const) */ .sleb128 1 /* (locview.c) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .byte 0 .section .debug_loclists .4byte .Ldebug_loc2-.Ldebug_loc1 /* Length of Location Lists */ .Ldebug_loc1: .2byte 0x5 /* DWARF version number */ .byte 0x4 /* Address Size */ .byte 0 /* Segment Size */ .4byte 0 /* Offset Entry Count */ .Ldebug_loc0: .LVUS0: .uleb128 0x2 /* View list begin (*.LVUS0) */ .uleb128 0x4 /* View list end (*.LVUS0) */ .uleb128 0x4 /* View list begin (*.LVUS0) */ .uleb128 0 /* View list end (*.LVUS0) */ .LLST0: .byte 0x6 /* DW_LLE_base_address (*.LLST0) */ .4byte .LVL0 /* Base address (*.LLST0) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST0) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST0) */ .uleb128 0x2 /* Location expression size */ .byte 0x30 /* DW_OP_lit0 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST0) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST0) */ .uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST0) */ .uleb128 0x2 /* Location expression size */ .byte 0x32 /* DW_OP_lit2 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0 /* DW_LLE_end_of_list (*.LLST0) */ .LLST1: .byte 0x6 /* DW_LLE_base_address (*.LLST1) */ .4byte .LVL0 /* Base address (*.LLST1) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST1) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST1) */ .uleb128 0x2 /* Location expression size */ .byte 0x31 /* DW_OP_lit1 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST1) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST1) */ .uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST1) */ .uleb128 0x2 /* Location expression size */ .byte 0x33 /* DW_OP_lit3 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0 /* DW_LLE_end_of_list (*.LLST1) */ .LVUS1: .uleb128 0x3 /* View list begin (*.LVUS1) */ .uleb128 0x5 /* View list end (*.LVUS1) */ .uleb128 0x5 /* View list begin (*.LVUS1) */ .uleb128 0 /* View list end (*.LVUS1) */ .LVUS2: .uleb128 0x6 /* View list begin (*.LVUS2) */ .uleb128 0x7 /* View list end (*.LVUS2) */ .uleb128 0x7 /* View list begin (*.LVUS2) */ .uleb128 0x8 /* View list end (*.LVUS2) */ .uleb128 0x8 /* View list begin (*.LVUS2) */ .uleb128 0 /* View list end (*.LVUS2) */ .LLST2: .byte 0x6 /* DW_LLE_base_address (*.LLST2) */ .4byte .LVL0 /* Base address (*.LLST2) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST2) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST2) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST2) */ .uleb128 0x2 /* Location expression size */ .byte 0x34 /* DW_OP_lit4 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST2) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST2) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST2) */ .uleb128 0x2 /* Location expression size */ .byte 0x35 /* DW_OP_lit5 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST2) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST2) */ .uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST2) */ .uleb128 0x2 /* Location expression size */ .byte 0x36 /* DW_OP_lit6 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0 /* DW_LLE_end_of_list (*.LLST2) */ .LLST3: .byte 0x6 /* DW_LLE_base_address (*.LLST3) */ .4byte .LVL0 /* Base address (*.LLST3) */ .byte 0x9 /* DW_LLE_view_pair (extension proposed for DWARF6) */ .uleb128 0x6 /* View list begin (*.LLST3) */ .uleb128 0x7 /* View list end (*.LVUS3) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST3) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST3) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST3) */ .uleb128 0x2 /* Location expression size */ .byte 0x34 /* DW_OP_lit4 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0x9 /* DW_LLE_view_pair */ .uleb128 0x7 /* View list begin (*.LLST3) */ .uleb128 0x8 /* View list end (*.LVUS3) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST3) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST3) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list end address (*.LLST3) */ .uleb128 0x2 /* Location expression size */ .byte 0x35 /* DW_OP_lit5 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0x9 /* DW_LLE_view_pair */ .uleb128 0x8 /* View list begin (*.LLST3) */ .uleb128 0x0 /* View list end (*.LVUS3) */ .byte 0x4 /* DW_LLE_offset_pair (*.LLST3) */ .uleb128 0 /* .LVL0-.LVL0 */ /* Location list begin address (*.LLST3) */ .uleb128 1 /* .LFE0-.LVL0 */ /* Location list end address (*.LLST3) */ .uleb128 0x2 /* Location expression size */ .byte 0x36 /* DW_OP_lit6 */ .byte 0x9f /* DW_OP_stack_value */ .byte 0 /* DW_LLE_end_of_list (*.LLST3) */ .Ldebug_loc2:

stsp/binutils-ia16

8,459

binutils/testsuite/binutils-all/locview-1.s

.text .Ltext0: .LFB0: /* locview.c:1 */ .LM1: /* view -0 */ /* locview.c:2 */ .LM2: /* view 1 */ .LVL0: /* DEBUG i => 0 */ /* locview.c:3 */ .LM3: /* view 2 */ /* DEBUG j => 0x1 */ /* locview.c:4 */ .LM4: /* view 3 */ /* DEBUG i => 0x2 */ /* locview.c:5 */ .LM5: /* view 4 */ /* DEBUG j => 0x3 */ /* locview.c:6 */ .LM6: /* view 5 */ /* DEBUG k => 0x4 */ /* DEBUG l => 0x4 */ /* locview.c:7 */ .LM7: /* view 6 */ /* DEBUG k => 0x5 */ /* DEBUG l => 0x5 */ /* locview.c:8 */ .LM8: /* view 7 */ /* DEBUG k => 0x6 */ /* DEBUG l => 0x6 */ /* locview.c:9 */ .LM9: /* view 8 */ .byte 0 .LFE0: .Letext0: .section .debug_info .Ldebug_info0: .LIbase: .4byte .LIend - .LIstart /* Length of Compilation Unit Info */ .LIstart: .2byte 0x4 /* DWARF version number */ .4byte .Ldebug_abbrev0 /* Offset Into Abbrev. Section */ .byte 0x4 /* Pointer Size (in bytes) */ .LIcu: .uleb128 0x1 /* (DIE (cu) DW_TAG_compile_unit) */ .ascii "hand-crafted based on GCC output\0" .byte 0xc /* DW_AT_language */ .ascii "locview.c\0" .ascii "/tmp\0" .4byte 0 /* DW_AT_low_pc */ .LIsubf: .uleb128 0x2 /* (DIE (subf) DW_TAG_subprogram) */ .ascii "f\0" /* DW_AT_name */ .byte 0x1 /* DW_AT_decl_file (locview.c) */ .byte 0x1 /* DW_AT_decl_line */ .4byte .LIint-.LIbase /* DW_AT_type */ .4byte .LFB0 /* DW_AT_low_pc */ .4byte 1 /* .LFE0-.LFB0 */ /* DW_AT_high_pc */ .uleb128 0x1 /* DW_AT_frame_base */ .byte 0x9c /* DW_OP_call_frame_cfa */ /* DW_AT_GNU_all_call_sites */ .4byte .LIint - .LIbase /* DW_AT_sibling */ .LIvari: .uleb128 0x3 /* (DIE (vari) DW_TAG_variable) */ .ascii "i\0" /* DW_AT_name */ .byte 0x1 /* DW_AT_decl_file (locview.c) */ .byte 0x2 /* DW_AT_decl_line */ .4byte .LIint-.LIbase /* DW_AT_type */ .4byte .LLST0 /* DW_AT_location */ .4byte .LVUS0 /* DW_AT_GNU_locviews */ .LIvarj: .uleb128 0x3 /* (DIE (varf) DW_TAG_variable) */ .ascii "j\0" /* DW_AT_name */ .byte 0x1 /* DW_AT_decl_file (locview.c) */ .byte 0x3 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LLST1 /* DW_AT_location */ .4byte .LVUS1 /* DW_AT_GNU_locviews */ .LIvark: .uleb128 0x5 /* (DIE (vark) DW_TAG_variable) */ .ascii "k\0" /* DW_AT_name */ .byte 0x1 /* DW_AT_decl_file (locview.c) */ .byte 0x6 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LVUS2 /* DW_AT_GNU_locviews */ .4byte .LLST2 /* DW_AT_location */ .byte 0 /* end of children of subf */ .LIvarl: .uleb128 0x5 /* (DIE (varl) DW_TAG_variable) */ .ascii "l\0" /* DW_AT_name */ .byte 0x1 /* DW_AT_decl_file (locview.c) */ .byte 0x6 /* DW_AT_decl_line */ .4byte .LIint - .LIbase /* DW_AT_type */ .4byte .LVUS2 /* DW_AT_GNU_locviews */ .4byte .LLST2 /* DW_AT_location */ .byte 0 /* end of children of subf */ .LIint: .uleb128 0x4 /* (DIE (int) DW_TAG_base_type) */ .byte 0x4 /* DW_AT_byte_size */ .byte 0x5 /* DW_AT_encoding */ .ascii "int\0" /* DW_AT_name */ .byte 0 /* end of children of cu */ .LIend: .section .debug_abbrev .Ldebug_abbrev0: .LAbrv1: .uleb128 0x1 /* (abbrev code) */ .uleb128 0x11 /* (TAG: DW_TAG_compile_unit) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x25 /* (DW_AT_producer) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x13 /* (DW_AT_language) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x1b /* (DW_AT_comp_dir) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .byte 0 .byte 0 .LAbrv2: .uleb128 0x2 /* (abbrev code) */ .uleb128 0x2e /* (TAG: DW_TAG_subprogram) */ .byte 0x1 /* DW_children_yes */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x11 /* (DW_AT_low_pc) */ .uleb128 0x1 /* (DW_FORM_addr) */ .uleb128 0x12 /* (DW_AT_high_pc) */ .uleb128 0x6 /* (DW_FORM_data4) */ .uleb128 0x40 /* (DW_AT_frame_base) */ .uleb128 0x18 /* (DW_FORM_exprloc) */ .uleb128 0x2117 /* (DW_AT_GNU_all_call_sites) */ .uleb128 0x19 /* (DW_FORM_flag_present) */ .uleb128 0x1 /* (DW_AT_sibling) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .byte 0 .byte 0 .LAbrv3: .uleb128 0x3 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .uleb128 0x2137 /* (DW_AT_GNU_locviews) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .LAbrv4: .uleb128 0x4 /* (abbrev code) */ .uleb128 0x24 /* (TAG: DW_TAG_base_type) */ .byte 0 /* DW_children_no */ .uleb128 0xb /* (DW_AT_byte_size) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3e /* (DW_AT_encoding) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .byte 0 .byte 0 .LAbrv5: .uleb128 0x5 /* (abbrev code) */ .uleb128 0x34 /* (TAG: DW_TAG_variable) */ .byte 0 /* DW_children_no */ .uleb128 0x3 /* (DW_AT_name) */ .uleb128 0x8 /* (DW_FORM_string) */ .uleb128 0x3a /* (DW_AT_decl_file) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x3b /* (DW_AT_decl_line) */ .uleb128 0xb /* (DW_FORM_data1) */ .uleb128 0x49 /* (DW_AT_type) */ .uleb128 0x13 /* (DW_FORM_ref4) */ .uleb128 0x2137 /* (DW_AT_GNU_locviews) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .uleb128 0x2 /* (DW_AT_location) */ .uleb128 0x17 /* (DW_FORM_sec_offset) */ .byte 0 .byte 0 .byte 0 .section .debug_loc .Ldebug_loc0: .LVUS0: .uleb128 0x2 /* View list begin (*.LVUS0) */ .uleb128 0x4 /* View list end (*.LVUS0) */ .uleb128 0x4 /* View list begin (*.LVUS0) */ .uleb128 0 /* View list end (*.LVUS0) */ .LLST0: .4byte .LVL0 /* Location list begin address (*.LLST0) */ .4byte .LVL0 /* Location list end address (*.LLST0) */ .2byte 0x2 /* Location expression size */ .byte 0x30 /* DW_OP_lit0 */ .byte 0x9f /* DW_OP_stack_value */ .4byte .LVL0 /* Location list begin address (*.LLST0) */ .4byte .LFE0 /* Location list end address (*.LLST0) */ .2byte 0x2 /* Location expression size */ .byte 0x32 /* DW_OP_lit2 */ .byte 0x9f /* DW_OP_stack_value */ .4byte 0 /* Location list terminator begin (*.LLST0) */ .4byte 0 /* Location list terminator end (*.LLST0) */ .LLST1: .4byte .LVL0 /* Location list begin address (*.LLST1) */ .4byte .LVL0 /* Location list end address (*.LLST1) */ .2byte 0x2 /* Location expression size */ .byte 0x31 /* DW_OP_lit1 */ .byte 0x9f /* DW_OP_stack_value */ .4byte .LVL0 /* Location list begin address (*.LLST1) */ .4byte .LFE0 /* Location list end address (*.LLST1) */ .2byte 0x2 /* Location expression size */ .byte 0x33 /* DW_OP_lit3 */ .byte 0x9f /* DW_OP_stack_value */ .4byte 0 /* Location list terminator begin (*.LLST1) */ .4byte 0 /* Location list terminator end (*.LLST1) */ .LVUS1: .uleb128 0x3 /* View list begin (*.LVUS1) */ .uleb128 0x5 /* View list end (*.LVUS1) */ .uleb128 0x5 /* View list begin (*.LVUS1) */ .uleb128 0 /* View list end (*.LVUS1) */ .LVUS2: .uleb128 0x6 /* View list begin (*.LVUS2) */ .uleb128 0x7 /* View list end (*.LVUS2) */ .uleb128 0x7 /* View list begin (*.LVUS2) */ .uleb128 0x8 /* View list end (*.LVUS2) */ .uleb128 0x8 /* View list begin (*.LVUS2) */ .uleb128 0 /* View list end (*.LVUS2) */ .LLST2: .4byte .LVL0 /* Location list begin address (*.LLST2) */ .4byte .LVL0 /* Location list end address (*.LLST2) */ .2byte 0x2 /* Location expression size */ .byte 0x34 /* DW_OP_lit4 */ .byte 0x9f /* DW_OP_stack_value */ .4byte .LVL0 /* Location list begin address (*.LLST2) */ .4byte .LVL0 /* Location list end address (*.LLST2) */ .2byte 0x2 /* Location expression size */ .byte 0x35 /* DW_OP_lit5 */ .byte 0x9f /* DW_OP_stack_value */ .4byte .LVL0 /* Location list begin address (*.LLST2) */ .4byte .LFE0 /* Location list end address (*.LLST2) */ .2byte 0x2 /* Location expression size */ .byte 0x36 /* DW_OP_lit6 */ .byte 0x9f /* DW_OP_stack_value */ .4byte 0 /* Location list terminator begin (*.LLST2) */ .4byte 0 /* Location list terminator end (*.LLST2) */

stsp/binutils-ia16

1,400

binutils/testsuite/binutils-all/testranges.s

# Test .debug_info can reference .debug_ranges entries without ordering the # offsets strictly as increasing. .text start: .byte 1 sub: .byte 2 end: .section .debug_ranges,"",%progbits range: range_sub: .4byte sub, end .4byte 0, 0 ;# range terminator range_cu: .4byte start, end .4byte 0, 0 ;# range terminator .section .debug_info,"",%progbits .4byte debugE - debugS ;# Length of Compilation Unit Info debugS: .short 0x2 ;# DWARF version number .4byte abbrev0 ;# Offset Into Abbrev. Section .byte 0x4 ;# Pointer Size (in bytes) .uleb128 0x1 ;# (DIE (0xb) DW_TAG_compile_unit) .4byte range_cu - range ;# DW_AT_ranges .uleb128 0x2 ;# (DIE (0x6d) DW_TAG_subprogram) .ascii "A\0" ;# DW_AT_name .4byte range_sub - range ;# DW_AT_ranges ;# minimal section alignment on alpha-* is 2, ensure no new invalid CU ;# will be started. .balign 2 debugE: .section .debug_abbrev,"",%progbits abbrev0: .uleb128 0x1 ;# (abbrev code) .uleb128 0x11 ;# (TAG: DW_TAG_compile_unit) .byte 0x0 ;# DW_children_no .uleb128 0x55 ;# (DW_AT_ranges) .uleb128 0x6 ;# (DW_FORM_data4) .byte 0x0 .byte 0x0 .uleb128 0x2 ;# (abbrev code) .uleb128 0x2e ;# (TAG: DW_TAG_subprogram) .byte 0x0 ;# DW_children_no .uleb128 0x3 ;# (DW_AT_name) .uleb128 0x8 ;# (DW_FORM_string) .uleb128 0x55 ;# (DW_AT_ranges) .uleb128 0x6 ;# (DW_FORM_data4) .byte 0x0 .byte 0x0 .byte 0x0 ;# abbrevs terminator

stsp/binutils-ia16

3,119

binutils/testsuite/binutils-all/pr18374.s

.section .debug_info,"",%progbits .4byte 0x77 .2byte 0x4 .4byte .Ldebug_abbrev0 .byte 0x4 .uleb128 0x1 .4byte .LASF3 .byte 0xc .ascii "x.c\000" .4byte .LASF4 .4byte .Ltext0 .4byte .Letext0 .4byte .Ldebug_line0 .uleb128 0x2 .ascii "foo\000" .byte 0x1 .byte 0x2 .4byte .LFB0 .4byte .LFE0 .uleb128 0x1 .byte 0x9c .4byte 0x64 .uleb128 0x3 .ascii "b\000" .byte 0x1 .byte 0x2 .4byte 0x64 .4byte .LLST0 .uleb128 0x4 .4byte .LASF0 .byte 0x1 .byte 0x2 .4byte 0x66 .4byte .LLST1 .uleb128 0x5 .ascii "ptr\000" .byte 0x1 .byte 0x4 .4byte 0x6d .uleb128 0x1 .byte 0x50 .byte 0 .uleb128 0x6 .byte 0x4 .uleb128 0x7 .byte 0x4 .byte 0x7 .4byte .LASF1 .uleb128 0x8 .byte 0x4 .4byte 0x73 .uleb128 0x7 .byte 0x1 .byte 0x8 .4byte .LASF2 .byte 0 .section .debug_abbrev,"",%progbits .Ldebug_abbrev0: .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0x8 .uleb128 0x1b .uleb128 0xe .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x6 .uleb128 0x10 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x2 .uleb128 0x2e .byte 0x1 .uleb128 0x3f .uleb128 0x19 .uleb128 0x3 .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x27 .uleb128 0x19 .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x6 .uleb128 0x40 .uleb128 0x18 .uleb128 0x2117 .uleb128 0x19 .uleb128 0x1 .uleb128 0x13 .byte 0 .byte 0 .uleb128 0x3 .uleb128 0x5 .byte 0 .uleb128 0x3 .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x2 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x4 .uleb128 0x5 .byte 0 .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x2 .uleb128 0x17 .byte 0 .byte 0 .uleb128 0x5 .uleb128 0x34 .byte 0 .uleb128 0x3 .uleb128 0x8 .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .uleb128 0x2 .uleb128 0x18 .byte 0 .byte 0 .uleb128 0x6 .uleb128 0xf .byte 0 .uleb128 0xb .uleb128 0xb .byte 0 .byte 0 .uleb128 0x7 .uleb128 0x24 .byte 0 .uleb128 0xb .uleb128 0xb .uleb128 0x3e .uleb128 0xb .uleb128 0x3 .uleb128 0xe .byte 0 .byte 0 .uleb128 0x8 .uleb128 0xf .byte 0 .uleb128 0xb .uleb128 0xb .uleb128 0x49 .uleb128 0x13 .byte 0 .byte 0 .byte 0 .section .debug_loc,"",%progbits .Ldebug_loc0: .LLST0: .4byte .LVL0 .4byte .LVL2 .2byte 0x1 .byte 0x50 .4byte .LVL2 .4byte .LFE0 .2byte 0x4 .byte 0xf3 .uleb128 0x1 .byte 0x50 .byte 0x9f .4byte 0 .4byte 0 .LLST1: .4byte .LVL0 .4byte .LVL1 .2byte 0x1 .byte 0x51 .4byte .LVL1 .4byte .LVL2 .2byte 0x3 .byte 0x71 .sleb128 -1 .byte 0x9f .4byte .LVL2 .4byte .LVL3 .2byte 0xb .byte 0x70 .sleb128 0 .byte 0x20 .byte 0xf3 .uleb128 0x1 .byte 0x51 .byte 0x22 .byte 0x70 .sleb128 0 .byte 0x22 .byte 0x9f .4byte .LVL3 .4byte .LFE0 .2byte 0xb .byte 0x70 .sleb128 0 .byte 0x20 .byte 0x70 .sleb128 0 .byte 0x22 .byte 0xf3 .uleb128 0x1 .byte 0x51 .byte 0x22 .byte 0x9f .4byte 0 .4byte 0

stsp/binutils-ia16

9,143

binutils/testsuite/binutils-all/dw2-3.S

/* This testcase is part of GDB, the GNU debugger. Copyright (C) 2004-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* Test a minimal file containing DWARF-2 information. This test also serves as a skeleton for other DWARF-2 tests. Most other tests will not be this extensively itemized and commented... */ /* Dummy function to provide debug information for. */ .text .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .4byte 0 .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: /* Debug information */ .section .debug_info .Lcu1_begin: /* CU header */ .4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */ .Lcu1_start: .2byte 2 /* DWARF Version */ .4byte .Labbrev1_begin /* Offset into abbrev section */ .byte 4 /* Pointer size */ /* CU die */ .uleb128 1 /* Abbrev: DW_TAG_compile_unit */ .4byte .Lline1_begin /* DW_AT_stmt_list */ .4byte .Lend_text1 /* DW_AT_high_pc */ .4byte .Lbegin_text1 /* DW_AT_low_pc */ .ascii "file1.txt\0" /* DW_AT_name */ .ascii "GNU C 3.3.3\0" /* DW_AT_producer */ .byte 1 /* DW_AT_language (C) */ /* func_cu1 */ .uleb128 2 /* Abbrev: DW_TAG_subprogram */ .byte 1 /* DW_AT_external */ .byte 1 /* DW_AT_decl_file */ .byte 2 /* DW_AT_decl_line */ .ascii "func_cu1\0" /* DW_AT_name */ .4byte .Ltype_int2_in_cu2 /* DW_AT_type */ .4byte .Lbegin_func_cu1 /* DW_AT_low_pc */ .4byte .Lend_func_cu1 /* DW_AT_high_pc */ .byte 1 /* DW_AT_frame_base: length */ .byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */ /* This type is named "int1" and not "int" to ensure it is unique, and thus we can easily ensure we expand this CU and not some other CU with "int". */ .Ltype_int1_in_cu1: .uleb128 3 /* Abbrev: DW_TAG_base_type */ .ascii "int1\0" /* DW_AT_name */ .byte 4 /* DW_AT_byte_size */ .byte 5 /* DW_AT_encoding */ .Ltype_const_int1_in_cu1: .uleb128 4 /* Abbrev: DW_TAG_const_type */ .4byte .Ltype_int1_in_cu1-.Lcu1_begin /* DW_AT_type */ .uleb128 5 /* Abbrev: DW_TAG_variable */ .ascii "one\0" /* DW_AT_name */ .4byte .Ltype_const_int1_in_cu1-.Lcu1_begin /* DW_AT_type */ .byte 1 /* DW_AT_const_value */ .byte 0 /* End of children of CU */ .Lcu1_end: /* Second compilation unit. */ .Lcu2_begin: /* CU header */ .4byte .Lcu2_end - .Lcu2_start /* Length of Compilation Unit */ .Lcu2_start: .2byte 2 /* DWARF Version */ .4byte .Labbrev2_begin /* Offset into abbrev section */ .byte 4 /* Pointer size */ /* CU die */ .uleb128 1 /* Abbrev: DW_TAG_compile_unit */ .ascii "file1.txt\0" /* DW_AT_name */ .ascii "GNU C 3.3.3\0" /* DW_AT_producer */ .byte 1 /* DW_AT_language (C) */ /* This type is named "int2" and not "int" to ensure it is unique, and thus we can easily ensure we expand this CU and not some other CU with "int". */ .Ltype_int2_in_cu2: .uleb128 2 /* Abbrev: DW_TAG_base_type */ .ascii "int2\0" /* DW_AT_name */ .byte 4 /* DW_AT_byte_size */ .byte 5 /* DW_AT_encoding */ .Ltype_const_int2_in_cu2: .uleb128 3 /* Abbrev: DW_TAG_const_type */ .4byte .Ltype_int2_in_cu2-.Lcu2_begin /* DW_AT_type */ .uleb128 4 /* Abbrev: DW_TAG_variable */ .ascii "two\0" /* DW_AT_name */ .4byte .Ltype_const_int2_in_cu2-.Lcu2_begin /* DW_AT_type */ .byte 2 /* DW_AT_const_value */ .byte 0 /* End of children of CU */ .Lcu2_end: /* Abbrev table */ .section .debug_abbrev .Labbrev1_begin: .uleb128 1 /* Abbrev code */ .uleb128 0x11 /* DW_TAG_compile_unit */ .byte 1 /* has_children */ .uleb128 0x10 /* DW_AT_stmt_list */ .uleb128 0x6 /* DW_FORM_data4 */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x25 /* DW_AT_producer */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x13 /* DW_AT_language */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 2 /* Abbrev code */ .uleb128 0x2e /* DW_TAG_subprogram */ .byte 0 /* has_children */ .uleb128 0x3f /* DW_AT_external */ .uleb128 0xc /* DW_FORM_flag */ .uleb128 0x3a /* DW_AT_decl_file */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3b /* DW_AT_decl_line */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x10 /* DW_FORM_ref_addr */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x40 /* DW_AT_frame_base */ .uleb128 0xa /* DW_FORM_block1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 3 /* Abbrev code */ .uleb128 0x24 /* DW_TAG_base_type */ .byte 0 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0xb /* DW_AT_byte_size */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3e /* DW_AT_encoding */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 4 /* Abbrev code */ .uleb128 0x26 /* DW_TAG_const_type */ .byte 0x0 /* DW_children_no */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 5 /* Abbrev code */ .uleb128 0x34 /* DW_TAG_variable */ .byte 0x0 /* DW_children_no */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .uleb128 0x1c /* DW_AT_const_value */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .Labbrev2_begin: .uleb128 1 /* Abbrev code */ .uleb128 0x11 /* DW_TAG_compile_unit */ .byte 1 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x25 /* DW_AT_producer */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x13 /* DW_AT_language */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 2 /* Abbrev code */ .uleb128 0x24 /* DW_TAG_base_type */ .byte 0 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0xb /* DW_AT_byte_size */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3e /* DW_AT_encoding */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 3 /* Abbrev code */ .uleb128 0x26 /* DW_TAG_const_type */ .byte 0x0 /* DW_children_no */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 4 /* Abbrev code */ .uleb128 0x34 /* DW_TAG_variable */ .byte 0x0 /* DW_children_no */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .uleb128 0x1c /* DW_AT_const_value */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ /* Line table */ .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start /* Initial length */ .Lline1_start: .2byte 2 /* Version */ .4byte .Lline1_lines - .Lline1_hdr /* header_length */ .Lline1_hdr: .byte 1 /* Minimum insn length */ .byte 1 /* default_is_stmt */ .byte 1 /* line_base */ .byte 1 /* line_range */ .byte 0x10 /* opcode_base */ /* Standard lengths */ .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 /* Include directories */ .byte 0 /* File names */ .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lbegin_func_cu1 .byte 3 /* DW_LNS_advance_line */ .sleb128 3 /* ... to 4 */ .byte 1 /* DW_LNS_copy */ .byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */ .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lend_func_cu1 .byte 0 /* DW_LNE_end_of_sequence */ .uleb128 1 .byte 1 .Lline1_end:

stsp/binutils-ia16

5,206

binutils/testsuite/binutils-all/dw2-2.S

/* This testcase is derived from a similar test in GDB. Copyright (C) 2008-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* Dummy function to provide debug information for. */ .text .Lbegin_text1: .globl func_cu2 .type func_cu2, %function func_cu2: .Lbegin_func_cu2: .4byte 0 .Lend_func_cu2: .size func_cu2, .-func_cu2 .Lend_text1: /* Debug information */ .section .debug_info .Lcu1_begin: /* CU header */ .4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */ .Lcu1_start: .2byte 2 /* DWARF Version */ .4byte .Labbrev1_begin /* Offset into abbrev section */ .byte 4 /* Pointer size */ /* CU die */ .uleb128 1 /* Abbrev: DW_TAG_compile_unit */ .4byte .Lline1_begin /* DW_AT_stmt_list */ .4byte .Lend_text1 /* DW_AT_high_pc */ .4byte .Lbegin_text1 /* DW_AT_low_pc */ .ascii "file1.txt\0" /* DW_AT_name */ .ascii "GNU C 3.3.3\0" /* DW_AT_producer */ .byte 1 /* DW_AT_language (C) */ /* func_cu2 */ .uleb128 2 /* Abbrev: DW_TAG_subprogram */ .byte 1 /* DW_AT_external */ .byte 1 /* DW_AT_decl_file */ .byte 2 /* DW_AT_decl_line */ .ascii "func_cu2\0" /* DW_AT_name */ .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */ .4byte .Lbegin_func_cu2 /* DW_AT_low_pc */ .4byte .Lend_func_cu2 /* DW_AT_high_pc */ .byte 1 /* DW_AT_frame_base: length */ .byte 0x55 /* DW_AT_frame_base: DW_OP_reg5 */ .Ltype_int: .uleb128 3 /* Abbrev: DW_TAG_base_type */ .ascii "int\0" /* DW_AT_name */ .byte 4 /* DW_AT_byte_size */ .byte 5 /* DW_AT_encoding */ .byte 0 /* End of children of CU */ .Lcu1_end: /* Line table */ .section .debug_line .Lline1_begin: .4byte .Lline1_end - .Lline1_start /* Initial length */ .Lline1_start: .2byte 2 /* Version */ .4byte .Lline1_lines - .Lline1_hdr /* header_length */ .Lline1_hdr: .byte 1 /* Minimum insn length */ .byte 1 /* default_is_stmt */ .byte 1 /* line_base */ .byte 1 /* line_range */ .byte 0x10 /* opcode_base */ /* Standard lengths */ .byte 0 .byte 1 .byte 1 .byte 1 .byte 1 .byte 0 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 1 .byte 0 .byte 0 .byte 0 /* Include directories */ .byte 0 /* File names */ .ascii "file1.txt\0" .uleb128 0 .uleb128 0 .uleb128 0 .byte 0 .Lline1_lines: .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lbegin_func_cu2 .byte 3 /* DW_LNS_advance_line */ .sleb128 3 /* ... to 4 */ .byte 1 /* DW_LNS_copy */ .byte 1 /* DW_LNS_copy (second time as an end-of-prologue marker) */ .byte 0 /* DW_LNE_set_address */ .uleb128 5 .byte 2 .4byte .Lend_func_cu2 .byte 0 /* DW_LNE_end_of_sequence */ .uleb128 1 .byte 1 .Lline1_end: /* Abbrev table */ .section .debug_abbrev .Labbrev1_begin: .uleb128 1 /* Abbrev code */ .uleb128 0x11 /* DW_TAG_compile_unit */ .byte 1 /* has_children */ .uleb128 0x10 /* DW_AT_stmt_list */ .uleb128 0x6 /* DW_FORM_data4 */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x25 /* DW_AT_producer */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x13 /* DW_AT_language */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 2 /* Abbrev code */ .uleb128 0x2e /* DW_TAG_subprogram */ .byte 0 /* has_children */ .uleb128 0x3f /* DW_AT_external */ .uleb128 0xc /* DW_FORM_flag */ .uleb128 0x3a /* DW_AT_decl_file */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3b /* DW_AT_decl_line */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x40 /* DW_AT_frame_base */ .uleb128 0xa /* DW_FORM_block1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 3 /* Abbrev code */ .uleb128 0x24 /* DW_TAG_base_type */ .byte 0 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0xb /* DW_AT_byte_size */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3e /* DW_AT_encoding */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */

stsp/binutils-ia16

2,386

binutils/testsuite/binutils-all/debuglink.s

/* Assembler source used to create an object file for testing readelf's and objdump's ability to process separate debug information files. Copyright (C) 2017-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* Create a fake .gnu_debuglink section. */ .section .gnu_debuglink,"",%progbits .asciz "this_is_a_debuglink.debug" .balign 4 .4byte 0x12345678 /* Create a fake .gnu_debugaltlink section. */ .section .gnu_debugaltlink,"",%progbits .asciz "linkdebug.debug" .dc.b 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 .dc.b 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff .dc.b 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef /* Create a .debug_str section for local use. This is also to check the ability to dump the same section twice, if it exists in both the main file and the separate debug info file. */ .section .debug_str,"MS",%progbits,1 string1: .asciz "string-1" .asciz "string-2" .balign 2 string_end: /* Create a .debug_info section that contains string references into the separate debug info file. Plus the abbreviations are stored in the separate file too... */ .section .debug_info,"",%progbits .4byte debugE - debugS ;# Length of Compilation Unit Info debugS: .short 0x4 ;# DWARF version number. .4byte 0x0 ;# Offset into .debug_abbrev section. .byte 0x4 ;# Pointer Size (in bytes). .uleb128 0x1 ;# Use abbrev #1. This needs a string from the local string table. .4byte string1 .uleb128 0x2 ;# Use abbrev #2. This needs a string from the separate string table. .4byte 0x0 ;# Avoid complicated expression resolution and hard code the offset... ;# Minimal section alignment on alpha-* is 2, so ensure no new invalid CU ;# will be started. .balign 2, 0 debugE:

stsp/binutils-ia16

4,440

binutils/testsuite/binutils-all/dw2-ranges.S

/* Copyright (C) 2015-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* This tests makes use of the .debug_ranges section, especially, making sure that the base address encoding scheme is used. */ /* Dummy function to provide debug information for. */ .text .globl _start _start: .4byte 0 .Lbegin_text1: .globl func_cu1 .type func_cu1, %function func_cu1: .Lbegin_func_cu1: .4byte 0 .Lend_func_cu1: .size func_cu1, .-func_cu1 .Lend_text1: .Lbegin_text2: .globl func_cu2 .type func_cu2, %function func_cu2: .Lbegin_func_cu2: .4byte 0 .Lend_func_cu2: .size func_cu2, .-func_cu2 .Lend_text2: /* Debug information */ .section .debug_info .Lcu1_begin: /* CU header */ .4byte .Lcu1_end - .Lcu1_start /* Length of Compilation Unit */ .Lcu1_start: .2byte 2 /* DWARF Version */ .4byte .Labbrev1_begin /* Offset into abbrev section */ .byte 4 /* Pointer size */ /* CU die */ .uleb128 1 /* Abbrev: DW_TAG_compile_unit */ .4byte .Lrange1_begin .ascii "file1.c\0" /* DW_AT_name */ .byte 1 /* DW_AT_language (C) */ /* func_cu1 */ .uleb128 2 /* Abbrev: DW_TAG_subprogram */ .ascii "func_cu1\0" /* DW_AT_name */ .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */ .4byte .Lbegin_func_cu1 /* DW_AT_low_pc */ .4byte .Lend_func_cu1 /* DW_AT_high_pc */ /* func_cu1 */ .uleb128 2 /* Abbrev: DW_TAG_subprogram */ .ascii "func_cu2\0" /* DW_AT_name */ .4byte .Ltype_int-.Lcu1_begin /* DW_AT_type */ .4byte .Lbegin_func_cu2 /* DW_AT_low_pc */ .4byte .Lend_func_cu2 /* DW_AT_high_pc */ .Ltype_int: .uleb128 3 /* Abbrev: DW_TAG_base_type */ .ascii "int\0" /* DW_AT_name */ .byte 4 /* DW_AT_byte_size */ .byte 5 /* DW_AT_encoding */ .byte 0 /* End of children of CU */ .Lcu1_end: .section .debug_ranges .Lrange1_begin: .4byte 0xffffffff /* base address marker */ .4byte .Lbegin_text1 /* base address */ .4byte 0 /* start offset */ .4byte .Lend_text1 - .Lbegin_text1 /* end offset */ .4byte 0xffffffff /* base address marker */ .4byte .Lbegin_text2 /* base address */ .4byte 0 /* start offset */ .4byte .Lend_text2 - .Lbegin_text2 /* end offset */ .4byte 0 /* End marker (Part 1) */ .4byte 0 /* End marker (Part 2) */ .section .debug_abbrev .Labbrev1_begin: .uleb128 1 /* Abbrev code */ .uleb128 0x11 /* DW_TAG_compile_unit */ .byte 1 /* has_children */ .uleb128 0x55 /* DW_AT_ranges */ .uleb128 0x17 /* DW_FORM_sec_offset */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x13 /* DW_AT_language */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 2 /* Abbrev code */ .uleb128 0x2e /* DW_TAG_subprogram */ .byte 0 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0x49 /* DW_AT_type */ .uleb128 0x13 /* DW_FORM_ref4 */ .uleb128 0x11 /* DW_AT_low_pc */ .uleb128 0x1 /* DW_FORM_addr */ .uleb128 0x12 /* DW_AT_high_pc */ .uleb128 0x1 /* DW_FORM_addr */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .uleb128 3 /* Abbrev code */ .uleb128 0x24 /* DW_TAG_base_type */ .byte 0 /* has_children */ .uleb128 0x3 /* DW_AT_name */ .uleb128 0x8 /* DW_FORM_string */ .uleb128 0xb /* DW_AT_byte_size */ .uleb128 0xb /* DW_FORM_data1 */ .uleb128 0x3e /* DW_AT_encoding */ .uleb128 0xb /* DW_FORM_data1 */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */ .byte 0x0 /* Terminator */

stsp/binutils-ia16

3,702

binutils/testsuite/binutils-all/mips/mips16-undecoded.s

.text .set mips16 .globl foo .ent foo foo: # Individual major opcodes. addiu $2, $sp, 0x4011 .half 0xf008, 0x0211 .half 0xf008, 0x0231 .half 0xf008, 0x0251 .half 0xf008, 0x0291 addiu $2, $pc, 0x4011 .half 0xf008, 0x0a11 .half 0xf008, 0x0a31 .half 0xf008, 0x0a51 .half 0xf008, 0x0a91 b . + 0x8026 .half 0xf008, 0x1011 .half 0xf008, 0x1031 .half 0xf008, 0x1051 .half 0xf008, 0x1091 .half 0xf008, 0x1111 .half 0xf008, 0x1211 .half 0xf008, 0x1411 beqz $2, . + 0x8026 .half 0xf008, 0x2211 .half 0xf008, 0x2231 .half 0xf008, 0x2251 .half 0xf008, 0x2291 bnez $2, . + 0x8026 .half 0xf008, 0x2a11 .half 0xf008, 0x2a31 .half 0xf008, 0x2a51 .half 0xf008, 0x2a91 addiu $2, 0x4011 .half 0xf008, 0x4a11 .half 0xf008, 0x4a31 .half 0xf008, 0x4a51 .half 0xf008, 0x4a91 slti $2, 0x4011 .half 0xf008, 0x5211 .half 0xf008, 0x5231 .half 0xf008, 0x5251 .half 0xf008, 0x5291 sltiu $2, 0x4011 .half 0xf008, 0x5a11 .half 0xf008, 0x5a31 .half 0xf008, 0x5a51 .half 0xf008, 0x5a91 li $2, 0x4011 .half 0xf008, 0x6a11 .half 0xf008, 0x6a31 .half 0xf008, 0x6a51 .half 0xf008, 0x6a91 cmpi $2, 0x4011 .half 0xf008, 0x7211 .half 0xf008, 0x7231 .half 0xf008, 0x7251 .half 0xf008, 0x7291 lw $2, 0x4011($sp) .half 0xf008, 0x9211 .half 0xf008, 0x9231 .half 0xf008, 0x9251 .half 0xf008, 0x9291 lw $2, 0x4011($pc) .half 0xf008, 0xb211 .half 0xf008, 0xb231 .half 0xf008, 0xb251 .half 0xf008, 0xb291 sw $2, 0x4011($sp) .half 0xf008, 0xd211 .half 0xf008, 0xd231 .half 0xf008, 0xd251 .half 0xf008, 0xd291 # I8 major opcode. bteqz . + 0x8026 .half 0xf008, 0x6011 .half 0xf008, 0x6031 .half 0xf008, 0x6051 .half 0xf008, 0x6091 btnez . + 0x8026 .half 0xf008, 0x6111 .half 0xf008, 0x6131 .half 0xf008, 0x6151 .half 0xf008, 0x6191 sw $ra, 0x4011($sp) .half 0xf008, 0x6211 .half 0xf008, 0x6231 .half 0xf008, 0x6251 .half 0xf008, 0x6291 addiu $sp, 0x4011 .half 0xf008, 0x6311 .half 0xf008, 0x6331 .half 0xf008, 0x6351 .half 0xf008, 0x6391 # SHIFT major opcode sll $2, $3, 0x14 .half 0xf500, 0x3260 .half 0xf500, 0x3264 .half 0xf500, 0x3268 .half 0xf500, 0x3270 .half 0xf501, 0x3260 .half 0xf502, 0x3260 .half 0xf504, 0x3260 .half 0xf508, 0x3260 .half 0xf510, 0x3260 .half 0xf520, 0x3260 dsll $2, $3, 0x14 .half 0xf500, 0x3261 .half 0xf500, 0x3265 .half 0xf500, 0x3269 .half 0xf500, 0x3271 .half 0xf501, 0x3261 .half 0xf502, 0x3261 .half 0xf504, 0x3261 .half 0xf508, 0x3261 .half 0xf510, 0x3261 .half 0xf520, 0x3261 srl $2, $3, 0x14 .half 0xf500, 0x3262 .half 0xf500, 0x3266 .half 0xf500, 0x326a .half 0xf500, 0x3272 .half 0xf501, 0x3262 .half 0xf502, 0x3262 .half 0xf504, 0x3262 .half 0xf508, 0x3262 .half 0xf510, 0x3262 .half 0xf520, 0x3262 sra $2, $3, 0x14 .half 0xf500, 0x3263 .half 0xf500, 0x3267 .half 0xf500, 0x326b .half 0xf500, 0x3273 .half 0xf501, 0x3263 .half 0xf502, 0x3263 .half 0xf504, 0x3263 .half 0xf508, 0x3263 .half 0xf510, 0x3263 .half 0xf520, 0x3263 # RR major opcode dsrl $2, 0x14 .half 0xf500, 0xe848 .half 0xf500, 0xe948 .half 0xf500, 0xea48 .half 0xf500, 0xec48 .half 0xf501, 0xe848 .half 0xf502, 0xe848 .half 0xf504, 0xe848 .half 0xf508, 0xe848 .half 0xf510, 0xe848 .half 0xf520, 0xe848 dsra $2, 0x14 .half 0xf500, 0xe853 .half 0xf500, 0xe953 .half 0xf500, 0xea53 .half 0xf500, 0xec53 .half 0xf501, 0xe853 .half 0xf502, 0xe853 .half 0xf504, 0xe853 .half 0xf508, 0xe853 .half 0xf510, 0xe853 .half 0xf520, 0xe853 # I64 major opcode. daddiu $sp, 0x4011 .half 0xf008, 0xfb11 .half 0xf008, 0xfb31 .half 0xf008, 0xfb51 .half 0xf008, 0xfb91 .end foo # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 .space 16

stsp/binutils-ia16

2,182

binutils/testsuite/binutils-all/mips/mips16-pcrel.s

.module mips64 .set mips16 .set noreorder .set noautoextend .align 12, 0 foo0: nop nop addiu $2, $pc, 0x3fc nop nop nop lw $3, 0x3fc($pc) nop nop nop daddiu $4, $pc, 0x7c nop nop nop nop nop ld $5, 0xf8($pc) .align 12, 0 foo1: jal bar0 addiu $2, $pc, 0x3fc nop jal bar0 lw $3, 0x3fc($pc) nop jal bar0 daddiu $4, $pc, 0x7c nop nop nop jal bar0 ld $5, 0xf8($pc) .align 12, 0 foo2: jalx bar1 addiu $2, $pc, 0x3fc nop jalx bar1 lw $3, 0x3fc($pc) nop jalx bar1 daddiu $4, $pc, 0x7c nop nop nop jalx bar1 ld $5, 0xf8($pc) .align 12, 0 foo3: nop jr $16 addiu $2, $pc, 0x3fc nop nop jr $16 lw $3, 0x3fc($pc) nop nop jr $16 daddiu $4, $pc, 0x7c nop nop nop nop jr $16 ld $5, 0xf8($pc) .align 12, 0 foo4: nop jr $31 addiu $2, $pc, 0x3fc nop nop jr $31 lw $3, 0x3fc($pc) nop nop jr $31 daddiu $4, $pc, 0x7c nop nop nop nop jr $31 ld $5, 0xf8($pc) .align 12, 0 foo5: nop jalr $16 addiu $2, $pc, 0x3fc nop nop jalr $16 lw $3, 0x3fc($pc) nop nop jalr $16 daddiu $4, $pc, 0x7c nop nop nop nop jalr $16 ld $5, 0xf8($pc) .align 12, 0 foo6: nop .half 0xe860 addiu $2, $pc, 0x3fc nop nop .half 0xe860 lw $3, 0x3fc($pc) nop nop .half 0xe860 daddiu $4, $pc, 0x7c nop nop nop nop .half 0xe860 ld $5, 0xf8($pc) .align 12, 0 foo7: nop jrc $16 addiu $2, $pc, 0x3fc nop nop jrc $16 lw $3, 0x3fc($pc) nop nop jrc $16 daddiu $4, $pc, 0x7c nop nop nop nop jrc $16 ld $5, 0xf8($pc) .align 12, 0 foo8: nop jrc $31 addiu $2, $pc, 0x3fc nop nop jrc $31 lw $3, 0x3fc($pc) nop nop jrc $31 daddiu $4, $pc, 0x7c nop nop nop nop jrc $31 ld $5, 0xf8($pc) .align 12, 0 foo9: nop jalrc $16 addiu $2, $pc, 0x3fc nop nop jalrc $16 lw $3, 0x3fc($pc) nop nop jalrc $16 daddiu $4, $pc, 0x7c nop nop nop nop jalrc $16 ld $5, 0xf8($pc) .align 12, 0 fooa: nop .half 0xe960 addiu $2, $pc, 0x3fc nop nop .half 0xe960 lw $3, 0x3fc($pc) nop nop .half 0xe960 daddiu $4, $pc, 0x7c nop nop nop nop .half 0xe960 ld $5, 0xf8($pc) # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 12, 0

stsp/binutils-ia16

9,273

binutils/testsuite/binutils-all/mips/mips16-extend-insn.s

.set mips16 .set noreorder foo: extend 0x123 # ADDIUSP addiu $16, $29, 0 extend 0x123 addiu $16, $29, 128 extend 0x123 addiu $16, $29, 256 extend 0x123 addiu $16, $29, 384 extend 0x123 addiu $16, $29, 512 extend 0x123 addiu $16, $29, 640 extend 0x123 addiu $16, $29, 768 extend 0x123 addiu $16, $29, 896 extend 0x123 # ADDIUPC addiu $16, $pc, 0 extend 0x123 addiu $16, $pc, 128 extend 0x123 addiu $16, $pc, 256 extend 0x123 addiu $16, $pc, 384 extend 0x123 addiu $16, $pc, 512 extend 0x123 addiu $16, $pc, 640 extend 0x123 addiu $16, $pc, 768 extend 0x123 addiu $16, $pc, 896 extend 0x123 # B b . + 2 extend 0x123 b . + 66 extend 0x123 b . + 130 extend 0x123 b . + 194 extend 0x123 b . + 258 extend 0x123 b . + 322 extend 0x123 b . + 386 extend 0x123 b . + 450 extend 0x123 # BEQZ beqz $16, . + 2 extend 0x123 beqz $16, . + 66 extend 0x123 beqz $16, . + 130 extend 0x123 beqz $16, . + 194 extend 0x123 beqz $16, . - 254 extend 0x123 beqz $16, . - 190 extend 0x123 beqz $16, . - 126 extend 0x123 beqz $16, . - 62 extend 0x123 # BNEZ bnez $16, . + 2 extend 0x123 bnez $16, . + 66 extend 0x123 bnez $16, . + 130 extend 0x123 bnez $16, . + 194 extend 0x123 bnez $16, . - 254 extend 0x123 bnez $16, . - 190 extend 0x123 bnez $16, . - 126 extend 0x123 bnez $16, . - 62 extend 0x123 # SHIFT # SLL sll $16, $16, 8 extend 0x123 sll $16, $16, 1 extend 0x123 sll $16, $16, 2 extend 0x123 sll $16, $16, 3 extend 0x123 sll $16, $16, 4 extend 0x123 sll $16, $16, 5 extend 0x123 sll $16, $16, 6 extend 0x123 sll $16, $16, 7 extend 0x123 # DSLL dsll $16, $16, 8 extend 0x123 dsll $16, $16, 1 extend 0x123 dsll $16, $16, 2 extend 0x123 dsll $16, $16, 3 extend 0x123 dsll $16, $16, 4 extend 0x123 dsll $16, $16, 5 extend 0x123 dsll $16, $16, 6 extend 0x123 dsll $16, $16, 7 extend 0x123 # SRL srl $16, $16, 8 extend 0x123 srl $16, $16, 1 extend 0x123 srl $16, $16, 2 extend 0x123 srl $16, $16, 3 extend 0x123 srl $16, $16, 4 extend 0x123 srl $16, $16, 5 extend 0x123 srl $16, $16, 6 extend 0x123 srl $16, $16, 7 extend 0x123 # SRA sra $16, $16, 8 extend 0x123 sra $16, $16, 1 extend 0x123 sra $16, $16, 2 extend 0x123 sra $16, $16, 3 extend 0x123 sra $16, $16, 4 extend 0x123 sra $16, $16, 5 extend 0x123 sra $16, $16, 6 extend 0x123 sra $16, $16, 7 extend 0x123 # LD ld $16, 0($16) extend 0x123 # RRI-A # ADDIU addiu $16, $16, 0 extend 0x123 # DADDIU daddiu $16, $16, 0 extend 0x123 # ADDIU8 addiu $16, 0 extend 0x123 addiu $16, 32 extend 0x123 addiu $16, 64 extend 0x123 addiu $16, 96 extend 0x123 addiu $16, -128 extend 0x123 addiu $16, -96 extend 0x123 addiu $16, -64 extend 0x123 addiu $16, -32 extend 0x123 # SLTI slti $16, 0 extend 0x123 slti $16, 32 extend 0x123 slti $16, 64 extend 0x123 slti $16, 96 extend 0x123 slti $16, 128 extend 0x123 slti $16, 160 extend 0x123 slti $16, 192 extend 0x123 slti $16, 224 extend 0x123 # SLTIU sltiu $16, 0 extend 0x123 sltiu $16, 32 extend 0x123 sltiu $16, 64 extend 0x123 sltiu $16, 96 extend 0x123 sltiu $16, 128 extend 0x123 sltiu $16, 160 extend 0x123 sltiu $16, 192 extend 0x123 sltiu $16, 224 extend 0x123 # I8 # BTEQZ bteqz . + 2 extend 0x123 bteqz . + 66 extend 0x123 bteqz . + 130 extend 0x123 bteqz . + 194 extend 0x123 bteqz . - 254 extend 0x123 bteqz . - 190 extend 0x123 bteqz . - 126 extend 0x123 bteqz . - 62 extend 0x123 # BTNEZ btnez . + 2 extend 0x123 btnez . + 66 extend 0x123 btnez . + 130 extend 0x123 btnez . + 194 extend 0x123 btnez . - 254 extend 0x123 btnez . - 190 extend 0x123 btnez . - 126 extend 0x123 btnez . - 62 extend 0x123 # SWRASP sw $31, 0($29) extend 0x123 sw $31, 128($29) extend 0x123 sw $31, 256($29) extend 0x123 sw $31, 512($29) extend 0x123 sw $31, 640($29) extend 0x123 sw $31, 768($29) extend 0x123 sw $31, 896($29) extend 0x123 sw $31, 0($29) extend 0x123 # ADJSP addiu $29, 0 extend 0x123 addiu $29, 256 extend 0x123 addiu $29, 512 extend 0x123 addiu $29, 768 extend 0x123 addiu $29, -1024 extend 0x123 addiu $29, -768 extend 0x123 addiu $29, -512 extend 0x123 addiu $29, -256 extend 0x123 # SVRS # RESTORE restore 128 extend 0x123 # SAVE save 128 extend 0x123 # MOV32R move $0, $16 extend 0x123 move $0, $17 extend 0x123 # MOVR32 move $16, $0 extend 0x123 # LI li $16, 0 extend 0x123 li $16, 32 extend 0x123 li $16, 64 extend 0x123 li $16, 96 extend 0x123 li $16, 128 extend 0x123 li $16, 160 extend 0x123 li $16, 192 extend 0x123 li $16, 224 extend 0x123 # CMPI cmpi $16, 0 extend 0x123 cmpi $16, 32 extend 0x123 cmpi $16, 64 extend 0x123 cmpi $16, 96 extend 0x123 cmpi $16, 128 extend 0x123 cmpi $16, 160 extend 0x123 cmpi $16, 192 extend 0x123 cmpi $16, 224 extend 0x123 # SD sd $16, 0($16) extend 0x123 # LB lb $16, 0($16) extend 0x123 # LH lh $16, 0($16) extend 0x123 # LWSP lw $16, 0($29) extend 0x123 lw $16, 128($29) extend 0x123 lw $16, 256($29) extend 0x123 lw $16, 384($29) extend 0x123 lw $16, 512($29) extend 0x123 lw $16, 640($29) extend 0x123 lw $16, 768($29) extend 0x123 lw $16, 896($29) extend 0x123 # LW lw $16, 0($16) extend 0x123 # LBU lbu $16, 0($16) extend 0x123 # LHU lhu $16, 0($16) extend 0x123 # LWPC lw $16, 0($pc) extend 0x123 lw $16, 128($pc) extend 0x123 lw $16, 256($pc) extend 0x123 lw $16, 384($pc) extend 0x123 lw $16, 512($pc) extend 0x123 lw $16, 640($pc) extend 0x123 lw $16, 768($pc) extend 0x123 lw $16, 896($pc) extend 0x123 # LWU lwu $16, 0($16) extend 0x123 # SB sb $16, 0($16) extend 0x123 # SH sh $16, 0($16) extend 0x123 # SWSP sw $16, 0($29) extend 0x123 sw $16, 128($29) extend 0x123 sw $16, 256($29) extend 0x123 sw $16, 384($29) extend 0x123 sw $16, 512($29) extend 0x123 sw $16, 640($29) extend 0x123 sw $16, 768($29) extend 0x123 sw $16, 896($29) extend 0x123 # SW sw $16, 0($16) extend 0x123 # RRR # DADDU daddu $16, $16, $16 extend 0x123 # ADDU addu $16, $16, $16 extend 0x123 # DSUBU dsubu $16, $16, $16 extend 0x123 # SUBU subu $16, $16, $16 extend 0x123 # RR # J(AL)R(C) # JR rx jr $16 extend 0x123 # JR ra jr $31 extend 0x123 # JALR jalr $16 extend 0x123 # JRC rx jrc $16 extend 0x123 # JRC ra jrc $31 extend 0x123 # JALRC jalrc $16 extend 0x123 # SDBBP sdbbp 0 extend 0x123 # SLT slt $16, $16 extend 0x123 # SLTU sltu $16, $16 extend 0x123 # SLLV sllv $16, $16 extend 0x123 # BREAK break 0 extend 0x123 # SRLV srlv $16, $16 extend 0x123 # SRAV srav $16, $16 extend 0x123 # DSRL dsrl $16, 8 extend 0x123 dsrl $16, 1 extend 0x123 dsrl $16, 2 extend 0x123 dsrl $16, 3 extend 0x123 dsrl $16, 4 extend 0x123 dsrl $16, 5 extend 0x123 dsrl $16, 6 extend 0x123 dsrl $16, 7 extend 0x123 # ENTRY/EXIT entry extend 0x123 entry $31 extend 0x123 exit $f0 extend 0x123 exit $f0-$f1 extend 0x123 exit extend 0x123 # CMP cmp $16, $16 extend 0x123 # NEG neg $16, $16 extend 0x123 # AND and $16, $16 extend 0x123 # OR or $16, $16 extend 0x123 # XOR xor $16, $16 extend 0x123 # NOT not $16, $16 extend 0x123 # MFHI mfhi $16 extend 0x123 # CNVT # ZEB zeb $16 extend 0x123 # ZEH zeh $16 extend 0x123 # ZEW zew $16 extend 0x123 # SEB seb $16 extend 0x123 # SEH seh $16 extend 0x123 # SEW sew $16 extend 0x123 # MFLO mflo $16 extend 0x123 # DSRA dsra $16, 8 extend 0x123 dsra $16, 1 extend 0x123 dsra $16, 2 extend 0x123 dsra $16, 3 extend 0x123 dsra $16, 4 extend 0x123 dsra $16, 5 extend 0x123 dsra $16, 6 extend 0x123 dsra $16, 7 extend 0x123 # DSLLV dsllv $16, $16 extend 0x123 # DSRLV dsrlv $16, $16 extend 0x123 # DSRAV dsrav $16, $16 extend 0x123 # MULT mult $16, $16 extend 0x123 # MULTU multu $16, $16 extend 0x123 # DIV div $0, $16, $16 extend 0x123 # DIVU divu $0, $16, $16 extend 0x123 # DMULT dmult $16, $16 extend 0x123 # DMULTU dmultu $16, $16 extend 0x123 # DDIV ddiv $0, $16, $16 extend 0x123 # DDIVU ddivu $0, $16, $16 extend 0x123 # EXTEND extend 0 extend 0x123 # I64 # LDSP ld $16, 0($29) extend 0x123 # SDSP sd $16, 0($29) extend 0x123 # SDRASP sd $31, 0($29) extend 0x123 sd $31, 256($29) extend 0x123 sd $31, 512($29) extend 0x123 sd $31, 768($29) extend 0x123 sd $31, 1024($29) extend 0x123 sd $31, 1280($29) extend 0x123 sd $31, 1536($29) extend 0x123 sd $31, 1792($29) extend 0x123 # DADJSP daddiu $29, 0 extend 0x123 daddiu $29, 256 extend 0x123 daddiu $29, 512 extend 0x123 daddiu $29, 768 extend 0x123 daddiu $29, -1024 extend 0x123 daddiu $29, -768 extend 0x123 daddiu $29, -512 extend 0x123 daddiu $29, -256 extend 0x123 # LDPC ld $16, 0($pc) extend 0x123 # DADDIU5 daddiu $16, 0 extend 0x123 # DADDIUPC daddiu $16, $pc, 0 extend 0x123 # DADDIUSP daddiu $16, $sp, 0 # Force some (non-delay-slot) zero bytes, to make 'objdump' print ... .align 4, 0 .space 16

stsp/binutils-ia16

1,478

binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s

.text func: //scale 1, size<0> check for H. #st1 {v30.h}[0], [x30] .inst 0x0d0043de | (1 << 10) #st2 {v29.h, v30.h}[0], [x30] .inst 0x0d2043dd | (1 << 10) #st3 {v28.h, v29.h, v30.h}[0], [x30] .inst 0x0d0063dc | (1 << 10) #st4 {v27.h, v28.h, v29.h, v30.h}[0], [x30] .inst 0x0d2063db | (1 << 10) //scale 2, size<1> check for S. #st1 {v30.s}[0], [x30] .inst 0x0d0083de | (1 << 11) #st2 {v29.s, v30.s}[0], [x30] .inst 0x0d2083dd | (1 << 11) #st3 {v28.s, v29.s, v30.s}[0], [x30] .inst 0x0d00a3dc | (1 << 11) #st4 {v27.s, v28.s, v29.s, v30.s}[0], [x30] .inst 0x0d20a3db | (1 << 11) //scale 2, size<1> check for D. #st1 {v30.d}[0], [x30] .inst 0x0d0087de | (1 << 11) #st2 {v29.d, v30.d}[0], [x30] .inst 0x0d2087dd | (1 << 11) #st3 {v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d00a7dc | (1 << 11) #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d20a7db | (1 << 11) //scale 2, S-bit check for D. #st1 {v30.d}[0], [x30] .inst 0x0d0087de | (2 << 11) #st2 {v29.d, v30.d}[0], [x30] .inst 0x0d2087dd | (2 << 11) #st3 {v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d00a7dc | (2 << 11) #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d20a7db | (2 << 11) //scale 2, size<1> & S-bit check for D. #st1 {v30.d}[0], [x30] .inst 0x0d0087de | (3 << 11) #st2 {v29.d, v30.d}[0], [x30] .inst 0x0d2087dd | (3 << 11) #st3 {v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d00a7dc | (3 << 11) #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] .inst 0x0d20a7db | (3 << 11)

stsp/binutils-ia16

2,178

binutils/testsuite/binutils-all/i386/compressed-1.s

.file "compressed-1.c" .section .debug_abbrev,"",@progbits .Ldebug_abbrev0: .section .debug_info,"",@progbits .Ldebug_info0: .section .debug_line,"",@progbits .Ldebug_line0: .text .Ltext0: .cfi_sections .debug_frame .p2align 4,,15 .globl foo2 .type foo2, @function foo2: .LFB1: .file 1 "compressed-1.c" .loc 1 11 0 .cfi_startproc .loc 1 12 0 rep ret .cfi_endproc .LFE1: .size foo2, .-foo2 .p2align 4,,15 .globl foo1 .type foo1, @function foo1: .LFB0: .loc 1 5 0 .cfi_startproc subl $12, %esp .cfi_def_cfa_offset 16 .loc 1 7 0 addl $12, %esp .cfi_def_cfa_offset 4 .loc 1 6 0 jmp bar .cfi_endproc .LFE0: .size foo1, .-foo1 .Letext0: .section .debug_info .long 0x46 .value 0x3 .long .Ldebug_abbrev0 .byte 0x4 .uleb128 0x1 .long .LASF2 .byte 0x1 .long .LASF3 .long .LASF4 .long .Ltext0 .long .Letext0 .long .Ldebug_line0 .uleb128 0x2 .byte 0x1 .long .LASF0 .byte 0x1 .byte 0xa .long .LFB1 .long .LFE1 .byte 0x1 .byte 0x9c .uleb128 0x2 .byte 0x1 .long .LASF1 .byte 0x1 .byte 0x4 .long .LFB0 .long .LFE0 .byte 0x1 .byte 0x9c .byte 0x0 .section .debug_abbrev .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0xe .uleb128 0x1b .uleb128 0xe .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x10 .uleb128 0x6 .byte 0x0 .byte 0x0 .uleb128 0x2 .uleb128 0x2e .byte 0x0 .uleb128 0x3f .uleb128 0xc .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x40 .uleb128 0xa .byte 0x0 .byte 0x0 .byte 0x0 .section .debug_pubnames,"",@progbits .long 0x20 .value 0x2 .long .Ldebug_info0 .long 0x4a .long 0x25 .string "foo2" .long 0x37 .string "foo1" .long 0x0 .section .debug_aranges,"",@progbits .long 0x1c .value 0x2 .long .Ldebug_info0 .byte 0x4 .byte 0x0 .value 0x0 .value 0x0 .long .Ltext0 .long .Letext0-.Ltext0 .long 0x0 .long 0x0 .section .debug_str,"MS",@progbits,1 .LASF2: .string "GNU C 4.4.4" .LASF0: .string "foo2" .LASF1: .string "foo1" .LASF4: .string "." .LASF3: .string "compressed-1.c"

stsp/binutils-ia16

1,299

binutils/testsuite/binutils-all/riscv/unknown.s

/* Copyright (C) 2021-2022 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ .text /* The following instruction is in the area set aside for custom instruction extensions. As such it is unlikely that an upstream extension should ever clash with this. */ .insn r 0x0b, 0x0, 0x0, x3, x4, x5 /* Unlike the above, the following is just a reserved instruction encoding. This means that in the future an extension to the compressed instruction set might use this encoding. If/when that happens we'll need to find a different unused encoding within the compressed instruction space. */ .insn ca 0x1, 0x27, 0x2, x8, x9

stsp/binutils-ia16

1,494

binutils/testsuite/binutils-all/x86-64/pr23494a.s

.section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_X86_ISA_1_USED */ .long 0xc0010002 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .long 0xa 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_X86_ISA_1_NEEDED */ .long 0xc0008002 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_X86_ISA_1_USED */ .long 0xc0010002 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3:

stsp/binutils-ia16

2,087

binutils/testsuite/binutils-all/x86-64/compressed-1.s

.file "compressed-1.c" .section .debug_abbrev,"",@progbits .Ldebug_abbrev0: .section .debug_info,"",@progbits .Ldebug_info0: .section .debug_line,"",@progbits .Ldebug_line0: .text .Ltext0: .cfi_sections .debug_frame .p2align 4,,15 .globl foo2 .type foo2, @function foo2: .LFB1: .file 1 "compressed-1.c" .loc 1 11 0 .cfi_startproc .loc 1 12 0 rep ret .cfi_endproc .LFE1: .size foo2, .-foo2 .p2align 4,,15 .globl foo1 .type foo1, @function foo1: .LFB0: .loc 1 5 0 .cfi_startproc .loc 1 6 0 jmp bar .cfi_endproc .LFE0: .size foo1, .-foo1 .Letext0: .section .debug_info .long 0x5e .value 0x3 .long .Ldebug_abbrev0 .byte 0x8 .uleb128 0x1 .long .LASF2 .byte 0x1 .long .LASF3 .long .LASF4 .quad .Ltext0 .quad .Letext0 .long .Ldebug_line0 .uleb128 0x2 .byte 0x1 .long .LASF0 .byte 0x1 .byte 0xa .quad .LFB1 .quad .LFE1 .byte 0x1 .byte 0x9c .uleb128 0x2 .byte 0x1 .long .LASF1 .byte 0x1 .byte 0x4 .quad .LFB0 .quad .LFE0 .byte 0x1 .byte 0x9c .byte 0x0 .section .debug_abbrev .uleb128 0x1 .uleb128 0x11 .byte 0x1 .uleb128 0x25 .uleb128 0xe .uleb128 0x13 .uleb128 0xb .uleb128 0x3 .uleb128 0xe .uleb128 0x1b .uleb128 0xe .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x10 .uleb128 0x6 .byte 0x0 .byte 0x0 .uleb128 0x2 .uleb128 0x2e .byte 0x0 .uleb128 0x3f .uleb128 0xc .uleb128 0x3 .uleb128 0xe .uleb128 0x3a .uleb128 0xb .uleb128 0x3b .uleb128 0xb .uleb128 0x11 .uleb128 0x1 .uleb128 0x12 .uleb128 0x1 .uleb128 0x40 .uleb128 0xa .byte 0x0 .byte 0x0 .byte 0x0 .section .debug_pubnames,"",@progbits .long 0x20 .value 0x2 .long .Ldebug_info0 .long 0x62 .long 0x2d .string "foo2" .long 0x47 .string "foo1" .long 0x0 .section .debug_aranges,"",@progbits .long 0x2c .value 0x2 .long .Ldebug_info0 .byte 0x8 .byte 0x0 .value 0x0 .value 0x0 .quad .Ltext0 .quad .Letext0-.Ltext0 .quad 0x0 .quad 0x0 .section .debug_str,"MS",@progbits,1 .LASF2: .string "GNU C 4.4.4" .LASF0: .string "foo2" .LASF1: .string "foo1" .LASF4: .string "." .LASF3: .string "compressed-1.c"

stsp/binutils-ia16

1,979

binutils/testsuite/binutils-all/x86-64/pr23494c.s

.section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_STACK_SIZE */ .long 1 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .dc.a -1 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_X86_ISA_1_USED */ .long 0xc0010002 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .long 0xa 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_X86_ISA_1_NEEDED */ .long 0xc0008002 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3: .section ".note.gnu.property", "a" .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif .long 1f - 0f /* name length. */ .long 3f - 1f /* data length. */ /* NT_GNU_PROPERTY_TYPE_0 */ .long 5 /* note type. */ 0: .asciz "GNU" /* vendor name. */ 1: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif /* GNU_PROPERTY_X86_ISA_1_USED */ .long 0xc0010002 /* pr_type. */ .long 5f - 4f /* pr_datasz. */ 4: .long 0xa0 5: .ifdef __64_bit__ .p2align 3 .else .p2align 2 .endif 3:

stsp/binutils-ia16

42,842

zlib/contrib/inflate86/inffast.S

/* * inffast.S is a hand tuned assembler version of: * * inffast.c -- fast decoding * Copyright (C) 1995-2003 Mark Adler * For conditions of distribution and use, see copyright notice in zlib.h * * Copyright (C) 2003 Chris Anderson <christop@charm.net> * Please use the copyright conditions above. * * This version (Jan-23-2003) of inflate_fast was coded and tested under * GNU/Linux on a pentium 3, using the gcc-3.2 compiler distribution. On that * machine, I found that gzip style archives decompressed about 20% faster than * the gcc-3.2 -O3 -fomit-frame-pointer compiled version. Your results will * depend on how large of a buffer is used for z_stream.next_in & next_out * (8K-32K worked best for my 256K cpu cache) and how much overhead there is in * stream processing I/O and crc32/addler32. In my case, this routine used * 70% of the cpu time and crc32 used 20%. * * I am confident that this version will work in the general case, but I have * not tested a wide variety of datasets or a wide variety of platforms. * * Jan-24-2003 -- Added -DUSE_MMX define for slightly faster inflating. * It should be a runtime flag instead of compile time flag... * * Jan-26-2003 -- Added runtime check for MMX support with cpuid instruction. * With -DUSE_MMX, only MMX code is compiled. With -DNO_MMX, only non-MMX code * is compiled. Without either option, runtime detection is enabled. Runtime * detection should work on all modern cpus and the recomended algorithm (flip * ID bit on eflags and then use the cpuid instruction) is used in many * multimedia applications. Tested under win2k with gcc-2.95 and gas-2.12 * distributed with cygwin3. Compiling with gcc-2.95 -c inffast.S -o * inffast.obj generates a COFF object which can then be linked with MSVC++ * compiled code. Tested under FreeBSD 4.7 with gcc-2.95. * * Jan-28-2003 -- Tested Athlon XP... MMX mode is slower than no MMX (and * slower than compiler generated code). Adjusted cpuid check to use the MMX * code only for Pentiums < P4 until I have more data on the P4. Speed * improvment is only about 15% on the Athlon when compared with code generated * with MSVC++. Not sure yet, but I think the P4 will also be slower using the * MMX mode because many of it's x86 ALU instructions execute in .5 cycles and * have less latency than MMX ops. Added code to buffer the last 11 bytes of * the input stream since the MMX code grabs bits in chunks of 32, which * differs from the inffast.c algorithm. I don't think there would have been * read overruns where a page boundary was crossed (a segfault), but there * could have been overruns when next_in ends on unaligned memory (unintialized * memory read). * * Mar-13-2003 -- P4 MMX is slightly slower than P4 NO_MMX. I created a C * version of the non-MMX code so that it doesn't depend on zstrm and zstate * structure offsets which are hard coded in this file. This was last tested * with zlib-1.2.0 which is currently in beta testing, newer versions of this * and inffas86.c can be found at http://www.eetbeetee.com/zlib/ and * http://www.charm.net/~christop/zlib/ */ /* * if you have underscore linking problems (_inflate_fast undefined), try * using -DGAS_COFF */ #if ! defined( GAS_COFF ) && ! defined( GAS_ELF ) #if defined( WIN32 ) || defined( __CYGWIN__ ) #define GAS_COFF /* windows object format */ #else #define GAS_ELF #endif #endif /* ! GAS_COFF && ! GAS_ELF */ #if defined( GAS_COFF ) /* coff externals have underscores */ #define inflate_fast _inflate_fast #define inflate_fast_use_mmx _inflate_fast_use_mmx #endif /* GAS_COFF */ .file "inffast.S" .globl inflate_fast .text .align 4,0 .L_invalid_literal_length_code_msg: .string "invalid literal/length code" .align 4,0 .L_invalid_distance_code_msg: .string "invalid distance code" .align 4,0 .L_invalid_distance_too_far_msg: .string "invalid distance too far back" #if ! defined( NO_MMX ) .align 4,0 .L_mask: /* mask[N] = ( 1 << N ) - 1 */ .long 0 .long 1 .long 3 .long 7 .long 15 .long 31 .long 63 .long 127 .long 255 .long 511 .long 1023 .long 2047 .long 4095 .long 8191 .long 16383 .long 32767 .long 65535 .long 131071 .long 262143 .long 524287 .long 1048575 .long 2097151 .long 4194303 .long 8388607 .long 16777215 .long 33554431 .long 67108863 .long 134217727 .long 268435455 .long 536870911 .long 1073741823 .long 2147483647 .long 4294967295 #endif /* NO_MMX */ .text /* * struct z_stream offsets, in zlib.h */ #define next_in_strm 0 /* strm->next_in */ #define avail_in_strm 4 /* strm->avail_in */ #define next_out_strm 12 /* strm->next_out */ #define avail_out_strm 16 /* strm->avail_out */ #define msg_strm 24 /* strm->msg */ #define state_strm 28 /* strm->state */ /* * struct inflate_state offsets, in inflate.h */ #define mode_state 0 /* state->mode */ #define wsize_state 32 /* state->wsize */ #define write_state 40 /* state->write */ #define window_state 44 /* state->window */ #define hold_state 48 /* state->hold */ #define bits_state 52 /* state->bits */ #define lencode_state 68 /* state->lencode */ #define distcode_state 72 /* state->distcode */ #define lenbits_state 76 /* state->lenbits */ #define distbits_state 80 /* state->distbits */ /* * inflate_fast's activation record */ #define local_var_size 64 /* how much local space for vars */ #define strm_sp 88 /* first arg: z_stream * (local_var_size + 24) */ #define start_sp 92 /* second arg: unsigned int (local_var_size + 28) */ /* * offsets for local vars on stack */ #define out 60 /* unsigned char* */ #define window 56 /* unsigned char* */ #define wsize 52 /* unsigned int */ #define write 48 /* unsigned int */ #define in 44 /* unsigned char* */ #define beg 40 /* unsigned char* */ #define buf 28 /* char[ 12 ] */ #define len 24 /* unsigned int */ #define last 20 /* unsigned char* */ #define end 16 /* unsigned char* */ #define dcode 12 /* code* */ #define lcode 8 /* code* */ #define dmask 4 /* unsigned int */ #define lmask 0 /* unsigned int */ /* * typedef enum inflate_mode consts, in inflate.h */ #define INFLATE_MODE_TYPE 11 /* state->mode flags enum-ed in inflate.h */ #define INFLATE_MODE_BAD 26 #if ! defined( USE_MMX ) && ! defined( NO_MMX ) #define RUN_TIME_MMX #define CHECK_MMX 1 #define DO_USE_MMX 2 #define DONT_USE_MMX 3 .globl inflate_fast_use_mmx .data .align 4,0 inflate_fast_use_mmx: /* integer flag for run time control 1=check,2=mmx,3=no */ .long CHECK_MMX #if defined( GAS_ELF ) /* elf info */ .type inflate_fast_use_mmx,@object .size inflate_fast_use_mmx,4 #endif #endif /* RUN_TIME_MMX */ #if defined( GAS_COFF ) /* coff info: scl 2 = extern, type 32 = function */ .def inflate_fast; .scl 2; .type 32; .endef #endif .text .align 32,0x90 inflate_fast: pushl %edi pushl %esi pushl %ebp pushl %ebx pushf /* save eflags (strm_sp, state_sp assumes this is 32 bits) */ subl $local_var_size, %esp cld #define strm_r %esi #define state_r %edi movl strm_sp(%esp), strm_r movl state_strm(strm_r), state_r /* in = strm->next_in; * out = strm->next_out; * last = in + strm->avail_in - 11; * beg = out - (start - strm->avail_out); * end = out + (strm->avail_out - 257); */ movl avail_in_strm(strm_r), %edx movl next_in_strm(strm_r), %eax addl %eax, %edx /* avail_in += next_in */ subl $11, %edx /* avail_in -= 11 */ movl %eax, in(%esp) movl %edx, last(%esp) movl start_sp(%esp), %ebp movl avail_out_strm(strm_r), %ecx movl next_out_strm(strm_r), %ebx subl %ecx, %ebp /* start -= avail_out */ negl %ebp /* start = -start */ addl %ebx, %ebp /* start += next_out */ subl $257, %ecx /* avail_out -= 257 */ addl %ebx, %ecx /* avail_out += out */ movl %ebx, out(%esp) movl %ebp, beg(%esp) movl %ecx, end(%esp) /* wsize = state->wsize; * write = state->write; * window = state->window; * hold = state->hold; * bits = state->bits; * lcode = state->lencode; * dcode = state->distcode; * lmask = ( 1 << state->lenbits ) - 1; * dmask = ( 1 << state->distbits ) - 1; */ movl lencode_state(state_r), %eax movl distcode_state(state_r), %ecx movl %eax, lcode(%esp) movl %ecx, dcode(%esp) movl $1, %eax movl lenbits_state(state_r), %ecx shll %cl, %eax decl %eax movl %eax, lmask(%esp) movl $1, %eax movl distbits_state(state_r), %ecx shll %cl, %eax decl %eax movl %eax, dmask(%esp) movl wsize_state(state_r), %eax movl write_state(state_r), %ecx movl window_state(state_r), %edx movl %eax, wsize(%esp) movl %ecx, write(%esp) movl %edx, window(%esp) movl hold_state(state_r), %ebp movl bits_state(state_r), %ebx #undef strm_r #undef state_r #define in_r %esi #define from_r %esi #define out_r %edi movl in(%esp), in_r movl last(%esp), %ecx cmpl in_r, %ecx ja .L_align_long /* if in < last */ addl $11, %ecx /* ecx = &in[ avail_in ] */ subl in_r, %ecx /* ecx = avail_in */ movl $12, %eax subl %ecx, %eax /* eax = 12 - avail_in */ leal buf(%esp), %edi rep movsb /* memcpy( buf, in, avail_in ) */ movl %eax, %ecx xorl %eax, %eax rep stosb /* memset( &buf[ avail_in ], 0, 12 - avail_in ) */ leal buf(%esp), in_r /* in = buf */ movl in_r, last(%esp) /* last = in, do just one iteration */ jmp .L_is_aligned /* align in_r on long boundary */ .L_align_long: testl $3, in_r jz .L_is_aligned xorl %eax, %eax movb (in_r), %al incl in_r movl %ebx, %ecx addl $8, %ebx shll %cl, %eax orl %eax, %ebp jmp .L_align_long .L_is_aligned: movl out(%esp), out_r #if defined( NO_MMX ) jmp .L_do_loop #endif #if defined( USE_MMX ) jmp .L_init_mmx #endif /*** Runtime MMX check ***/ #if defined( RUN_TIME_MMX ) .L_check_mmx: cmpl $DO_USE_MMX, inflate_fast_use_mmx je .L_init_mmx ja .L_do_loop /* > 2 */ pushl %eax pushl %ebx pushl %ecx pushl %edx pushf movl (%esp), %eax /* copy eflags to eax */ xorl $0x200000, (%esp) /* try toggling ID bit of eflags (bit 21) * to see if cpu supports cpuid... * ID bit method not supported by NexGen but * bios may load a cpuid instruction and * cpuid may be disabled on Cyrix 5-6x86 */ popf pushf popl %edx /* copy new eflags to edx */ xorl %eax, %edx /* test if ID bit is flipped */ jz .L_dont_use_mmx /* not flipped if zero */ xorl %eax, %eax cpuid cmpl $0x756e6547, %ebx /* check for GenuineIntel in ebx,ecx,edx */ jne .L_dont_use_mmx cmpl $0x6c65746e, %ecx jne .L_dont_use_mmx cmpl $0x49656e69, %edx jne .L_dont_use_mmx movl $1, %eax cpuid /* get cpu features */ shrl $8, %eax andl $15, %eax cmpl $6, %eax /* check for Pentium family, is 0xf for P4 */ jne .L_dont_use_mmx testl $0x800000, %edx /* test if MMX feature is set (bit 23) */ jnz .L_use_mmx jmp .L_dont_use_mmx .L_use_mmx: movl $DO_USE_MMX, inflate_fast_use_mmx jmp .L_check_mmx_pop .L_dont_use_mmx: movl $DONT_USE_MMX, inflate_fast_use_mmx .L_check_mmx_pop: popl %edx popl %ecx popl %ebx popl %eax jmp .L_check_mmx #endif /*** Non-MMX code ***/ #if defined ( NO_MMX ) || defined( RUN_TIME_MMX ) #define hold_r %ebp #define bits_r %bl #define bitslong_r %ebx .align 32,0x90 .L_while_test: /* while (in < last && out < end) */ cmpl out_r, end(%esp) jbe .L_break_loop /* if (out >= end) */ cmpl in_r, last(%esp) jbe .L_break_loop .L_do_loop: /* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out * * do { * if (bits < 15) { * hold |= *((unsigned short *)in)++ << bits; * bits += 16 * } * this = lcode[hold & lmask] */ cmpb $15, bits_r ja .L_get_length_code /* if (15 < bits) */ xorl %eax, %eax lodsw /* al = *(ushort *)in++ */ movb bits_r, %cl /* cl = bits, needs it for shifting */ addb $16, bits_r /* bits += 16 */ shll %cl, %eax orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */ .L_get_length_code: movl lmask(%esp), %edx /* edx = lmask */ movl lcode(%esp), %ecx /* ecx = lcode */ andl hold_r, %edx /* edx &= hold */ movl (%ecx,%edx,4), %eax /* eax = lcode[hold & lmask] */ .L_dolen: /* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out * * dolen: * bits -= this.bits; * hold >>= this.bits */ movb %ah, %cl /* cl = this.bits */ subb %ah, bits_r /* bits -= this.bits */ shrl %cl, hold_r /* hold >>= this.bits */ /* check if op is a literal * if (op == 0) { * PUP(out) = this.val; * } */ testb %al, %al jnz .L_test_for_length_base /* if (op != 0) 45.7% */ shrl $16, %eax /* output this.val char */ stosb jmp .L_while_test .L_test_for_length_base: /* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = len * * else if (op & 16) { * len = this.val * op &= 15 * if (op) { * if (op > bits) { * hold |= *((unsigned short *)in)++ << bits; * bits += 16 * } * len += hold & mask[op]; * bits -= op; * hold >>= op; * } */ #define len_r %edx movl %eax, len_r /* len = this */ shrl $16, len_r /* len = this.val */ movb %al, %cl testb $16, %al jz .L_test_for_second_level_length /* if ((op & 16) == 0) 8% */ andb $15, %cl /* op &= 15 */ jz .L_save_len /* if (!op) */ cmpb %cl, bits_r jae .L_add_bits_to_len /* if (op <= bits) */ movb %cl, %ch /* stash op in ch, freeing cl */ xorl %eax, %eax lodsw /* al = *(ushort *)in++ */ movb bits_r, %cl /* cl = bits, needs it for shifting */ addb $16, bits_r /* bits += 16 */ shll %cl, %eax orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */ movb %ch, %cl /* move op back to ecx */ .L_add_bits_to_len: movl $1, %eax shll %cl, %eax decl %eax subb %cl, bits_r andl hold_r, %eax /* eax &= hold */ shrl %cl, hold_r addl %eax, len_r /* len += hold & mask[op] */ .L_save_len: movl len_r, len(%esp) /* save len */ #undef len_r .L_decode_distance: /* regs: %esi = in, %ebp = hold, %bl = bits, %edi = out, %edx = dist * * if (bits < 15) { * hold |= *((unsigned short *)in)++ << bits; * bits += 16 * } * this = dcode[hold & dmask]; * dodist: * bits -= this.bits; * hold >>= this.bits; * op = this.op; */ cmpb $15, bits_r ja .L_get_distance_code /* if (15 < bits) */ xorl %eax, %eax lodsw /* al = *(ushort *)in++ */ movb bits_r, %cl /* cl = bits, needs it for shifting */ addb $16, bits_r /* bits += 16 */ shll %cl, %eax orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */ .L_get_distance_code: movl dmask(%esp), %edx /* edx = dmask */ movl dcode(%esp), %ecx /* ecx = dcode */ andl hold_r, %edx /* edx &= hold */ movl (%ecx,%edx,4), %eax /* eax = dcode[hold & dmask] */ #define dist_r %edx .L_dodist: movl %eax, dist_r /* dist = this */ shrl $16, dist_r /* dist = this.val */ movb %ah, %cl subb %ah, bits_r /* bits -= this.bits */ shrl %cl, hold_r /* hold >>= this.bits */ /* if (op & 16) { * dist = this.val * op &= 15 * if (op > bits) { * hold |= *((unsigned short *)in)++ << bits; * bits += 16 * } * dist += hold & mask[op]; * bits -= op; * hold >>= op; */ movb %al, %cl /* cl = this.op */ testb $16, %al /* if ((op & 16) == 0) */ jz .L_test_for_second_level_dist andb $15, %cl /* op &= 15 */ jz .L_check_dist_one cmpb %cl, bits_r jae .L_add_bits_to_dist /* if (op <= bits) 97.6% */ movb %cl, %ch /* stash op in ch, freeing cl */ xorl %eax, %eax lodsw /* al = *(ushort *)in++ */ movb bits_r, %cl /* cl = bits, needs it for shifting */ addb $16, bits_r /* bits += 16 */ shll %cl, %eax orl %eax, hold_r /* hold |= *((ushort *)in)++ << bits */ movb %ch, %cl /* move op back to ecx */ .L_add_bits_to_dist: movl $1, %eax shll %cl, %eax decl %eax /* (1 << op) - 1 */ subb %cl, bits_r andl hold_r, %eax /* eax &= hold */ shrl %cl, hold_r addl %eax, dist_r /* dist += hold & ((1 << op) - 1) */ jmp .L_check_window .L_check_window: /* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes * * nbytes = out - beg; * if (dist <= nbytes) { * from = out - dist; * do { * PUP(out) = PUP(from); * } while (--len > 0) { * } */ movl in_r, in(%esp) /* save in so from can use it's reg */ movl out_r, %eax subl beg(%esp), %eax /* nbytes = out - beg */ cmpl dist_r, %eax jb .L_clip_window /* if (dist > nbytes) 4.2% */ movl len(%esp), %ecx movl out_r, from_r subl dist_r, from_r /* from = out - dist */ subl $3, %ecx movb (from_r), %al movb %al, (out_r) movb 1(from_r), %al movb 2(from_r), %dl addl $3, from_r movb %al, 1(out_r) movb %dl, 2(out_r) addl $3, out_r rep movsb movl in(%esp), in_r /* move in back to %esi, toss from */ jmp .L_while_test .align 16,0x90 .L_check_dist_one: cmpl $1, dist_r jne .L_check_window cmpl out_r, beg(%esp) je .L_check_window decl out_r movl len(%esp), %ecx movb (out_r), %al subl $3, %ecx movb %al, 1(out_r) movb %al, 2(out_r) movb %al, 3(out_r) addl $4, out_r rep stosb jmp .L_while_test .align 16,0x90 .L_test_for_second_level_length: /* else if ((op & 64) == 0) { * this = lcode[this.val + (hold & mask[op])]; * } */ testb $64, %al jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */ movl $1, %eax shll %cl, %eax decl %eax andl hold_r, %eax /* eax &= hold */ addl %edx, %eax /* eax += this.val */ movl lcode(%esp), %edx /* edx = lcode */ movl (%edx,%eax,4), %eax /* eax = lcode[val + (hold&mask[op])] */ jmp .L_dolen .align 16,0x90 .L_test_for_second_level_dist: /* else if ((op & 64) == 0) { * this = dcode[this.val + (hold & mask[op])]; * } */ testb $64, %al jnz .L_invalid_distance_code /* if ((op & 64) != 0) */ movl $1, %eax shll %cl, %eax decl %eax andl hold_r, %eax /* eax &= hold */ addl %edx, %eax /* eax += this.val */ movl dcode(%esp), %edx /* edx = dcode */ movl (%edx,%eax,4), %eax /* eax = dcode[val + (hold&mask[op])] */ jmp .L_dodist .align 16,0x90 .L_clip_window: /* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes * * else { * if (dist > wsize) { * invalid distance * } * from = window; * nbytes = dist - nbytes; * if (write == 0) { * from += wsize - nbytes; */ #define nbytes_r %ecx movl %eax, nbytes_r movl wsize(%esp), %eax /* prepare for dist compare */ negl nbytes_r /* nbytes = -nbytes */ movl window(%esp), from_r /* from = window */ cmpl dist_r, %eax jb .L_invalid_distance_too_far /* if (dist > wsize) */ addl dist_r, nbytes_r /* nbytes = dist - nbytes */ cmpl $0, write(%esp) jne .L_wrap_around_window /* if (write != 0) */ subl nbytes_r, %eax addl %eax, from_r /* from += wsize - nbytes */ /* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes, %eax = len * * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while (--nbytes); * from = out - dist; * } * } */ #define len_r %eax movl len(%esp), len_r cmpl nbytes_r, len_r jbe .L_do_copy1 /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ jmp .L_do_copy1 cmpl nbytes_r, len_r jbe .L_do_copy1 /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ jmp .L_do_copy1 .L_wrap_around_window: /* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes, %eax = write, %eax = len * * else if (write < nbytes) { * from += wsize + write - nbytes; * nbytes -= write; * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while (--nbytes); * from = window; * nbytes = write; * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while(--nbytes); * from = out - dist; * } * } * } */ #define write_r %eax movl write(%esp), write_r cmpl write_r, nbytes_r jbe .L_contiguous_in_window /* if (write >= nbytes) */ addl wsize(%esp), from_r addl write_r, from_r subl nbytes_r, from_r /* from += wsize + write - nbytes */ subl write_r, nbytes_r /* nbytes -= write */ #undef write_r movl len(%esp), len_r cmpl nbytes_r, len_r jbe .L_do_copy1 /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl window(%esp), from_r /* from = window */ movl write(%esp), nbytes_r /* nbytes = write */ cmpl nbytes_r, len_r jbe .L_do_copy1 /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ jmp .L_do_copy1 .L_contiguous_in_window: /* regs: %esi = from, %ebp = hold, %bl = bits, %edi = out, %edx = dist * %ecx = nbytes, %eax = write, %eax = len * * else { * from += write - nbytes; * if (nbytes < len) { * len -= nbytes; * do { * PUP(out) = PUP(from); * } while (--nbytes); * from = out - dist; * } * } */ #define write_r %eax addl write_r, from_r subl nbytes_r, from_r /* from += write - nbytes */ #undef write_r movl len(%esp), len_r cmpl nbytes_r, len_r jbe .L_do_copy1 /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ .L_do_copy1: /* regs: %esi = from, %esi = in, %ebp = hold, %bl = bits, %edi = out * %eax = len * * while (len > 0) { * PUP(out) = PUP(from); * len--; * } * } * } while (in < last && out < end); */ #undef nbytes_r #define in_r %esi movl len_r, %ecx rep movsb movl in(%esp), in_r /* move in back to %esi, toss from */ jmp .L_while_test #undef len_r #undef dist_r #endif /* NO_MMX || RUN_TIME_MMX */ /*** MMX code ***/ #if defined( USE_MMX ) || defined( RUN_TIME_MMX ) .align 32,0x90 .L_init_mmx: emms #undef bits_r #undef bitslong_r #define bitslong_r %ebp #define hold_mm %mm0 movd %ebp, hold_mm movl %ebx, bitslong_r #define used_mm %mm1 #define dmask2_mm %mm2 #define lmask2_mm %mm3 #define lmask_mm %mm4 #define dmask_mm %mm5 #define tmp_mm %mm6 movd lmask(%esp), lmask_mm movq lmask_mm, lmask2_mm movd dmask(%esp), dmask_mm movq dmask_mm, dmask2_mm pxor used_mm, used_mm movl lcode(%esp), %ebx /* ebx = lcode */ jmp .L_do_loop_mmx .align 32,0x90 .L_while_test_mmx: /* while (in < last && out < end) */ cmpl out_r, end(%esp) jbe .L_break_loop /* if (out >= end) */ cmpl in_r, last(%esp) jbe .L_break_loop .L_do_loop_mmx: psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ cmpl $32, bitslong_r ja .L_get_length_code_mmx /* if (32 < bits) */ movd bitslong_r, tmp_mm movd (in_r), %mm7 addl $4, in_r psllq tmp_mm, %mm7 addl $32, bitslong_r por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */ .L_get_length_code_mmx: pand hold_mm, lmask_mm movd lmask_mm, %eax movq lmask2_mm, lmask_mm movl (%ebx,%eax,4), %eax /* eax = lcode[hold & lmask] */ .L_dolen_mmx: movzbl %ah, %ecx /* ecx = this.bits */ movd %ecx, used_mm subl %ecx, bitslong_r /* bits -= this.bits */ testb %al, %al jnz .L_test_for_length_base_mmx /* if (op != 0) 45.7% */ shrl $16, %eax /* output this.val char */ stosb jmp .L_while_test_mmx .L_test_for_length_base_mmx: #define len_r %edx movl %eax, len_r /* len = this */ shrl $16, len_r /* len = this.val */ testb $16, %al jz .L_test_for_second_level_length_mmx /* if ((op & 16) == 0) 8% */ andl $15, %eax /* op &= 15 */ jz .L_decode_distance_mmx /* if (!op) */ psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ movd %eax, used_mm movd hold_mm, %ecx subl %eax, bitslong_r andl .L_mask(,%eax,4), %ecx addl %ecx, len_r /* len += hold & mask[op] */ .L_decode_distance_mmx: psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ cmpl $32, bitslong_r ja .L_get_dist_code_mmx /* if (32 < bits) */ movd bitslong_r, tmp_mm movd (in_r), %mm7 addl $4, in_r psllq tmp_mm, %mm7 addl $32, bitslong_r por %mm7, hold_mm /* hold_mm |= *((uint *)in)++ << bits */ .L_get_dist_code_mmx: movl dcode(%esp), %ebx /* ebx = dcode */ pand hold_mm, dmask_mm movd dmask_mm, %eax movq dmask2_mm, dmask_mm movl (%ebx,%eax,4), %eax /* eax = dcode[hold & lmask] */ .L_dodist_mmx: #define dist_r %ebx movzbl %ah, %ecx /* ecx = this.bits */ movl %eax, dist_r shrl $16, dist_r /* dist = this.val */ subl %ecx, bitslong_r /* bits -= this.bits */ movd %ecx, used_mm testb $16, %al /* if ((op & 16) == 0) */ jz .L_test_for_second_level_dist_mmx andl $15, %eax /* op &= 15 */ jz .L_check_dist_one_mmx .L_add_bits_to_dist_mmx: psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ movd %eax, used_mm /* save bit length of current op */ movd hold_mm, %ecx /* get the next bits on input stream */ subl %eax, bitslong_r /* bits -= op bits */ andl .L_mask(,%eax,4), %ecx /* ecx = hold & mask[op] */ addl %ecx, dist_r /* dist += hold & mask[op] */ .L_check_window_mmx: movl in_r, in(%esp) /* save in so from can use it's reg */ movl out_r, %eax subl beg(%esp), %eax /* nbytes = out - beg */ cmpl dist_r, %eax jb .L_clip_window_mmx /* if (dist > nbytes) 4.2% */ movl len_r, %ecx movl out_r, from_r subl dist_r, from_r /* from = out - dist */ subl $3, %ecx movb (from_r), %al movb %al, (out_r) movb 1(from_r), %al movb 2(from_r), %dl addl $3, from_r movb %al, 1(out_r) movb %dl, 2(out_r) addl $3, out_r rep movsb movl in(%esp), in_r /* move in back to %esi, toss from */ movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */ jmp .L_while_test_mmx .align 16,0x90 .L_check_dist_one_mmx: cmpl $1, dist_r jne .L_check_window_mmx cmpl out_r, beg(%esp) je .L_check_window_mmx decl out_r movl len_r, %ecx movb (out_r), %al subl $3, %ecx movb %al, 1(out_r) movb %al, 2(out_r) movb %al, 3(out_r) addl $4, out_r rep stosb movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */ jmp .L_while_test_mmx .align 16,0x90 .L_test_for_second_level_length_mmx: testb $64, %al jnz .L_test_for_end_of_block /* if ((op & 64) != 0) */ andl $15, %eax psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ movd hold_mm, %ecx andl .L_mask(,%eax,4), %ecx addl len_r, %ecx movl (%ebx,%ecx,4), %eax /* eax = lcode[hold & lmask] */ jmp .L_dolen_mmx .align 16,0x90 .L_test_for_second_level_dist_mmx: testb $64, %al jnz .L_invalid_distance_code /* if ((op & 64) != 0) */ andl $15, %eax psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ movd hold_mm, %ecx andl .L_mask(,%eax,4), %ecx movl dcode(%esp), %eax /* ecx = dcode */ addl dist_r, %ecx movl (%eax,%ecx,4), %eax /* eax = lcode[hold & lmask] */ jmp .L_dodist_mmx .align 16,0x90 .L_clip_window_mmx: #define nbytes_r %ecx movl %eax, nbytes_r movl wsize(%esp), %eax /* prepare for dist compare */ negl nbytes_r /* nbytes = -nbytes */ movl window(%esp), from_r /* from = window */ cmpl dist_r, %eax jb .L_invalid_distance_too_far /* if (dist > wsize) */ addl dist_r, nbytes_r /* nbytes = dist - nbytes */ cmpl $0, write(%esp) jne .L_wrap_around_window_mmx /* if (write != 0) */ subl nbytes_r, %eax addl %eax, from_r /* from += wsize - nbytes */ cmpl nbytes_r, len_r jbe .L_do_copy1_mmx /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ jmp .L_do_copy1_mmx cmpl nbytes_r, len_r jbe .L_do_copy1_mmx /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ jmp .L_do_copy1_mmx .L_wrap_around_window_mmx: #define write_r %eax movl write(%esp), write_r cmpl write_r, nbytes_r jbe .L_contiguous_in_window_mmx /* if (write >= nbytes) */ addl wsize(%esp), from_r addl write_r, from_r subl nbytes_r, from_r /* from += wsize + write - nbytes */ subl write_r, nbytes_r /* nbytes -= write */ #undef write_r cmpl nbytes_r, len_r jbe .L_do_copy1_mmx /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl window(%esp), from_r /* from = window */ movl write(%esp), nbytes_r /* nbytes = write */ cmpl nbytes_r, len_r jbe .L_do_copy1_mmx /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ jmp .L_do_copy1_mmx .L_contiguous_in_window_mmx: #define write_r %eax addl write_r, from_r subl nbytes_r, from_r /* from += write - nbytes */ #undef write_r cmpl nbytes_r, len_r jbe .L_do_copy1_mmx /* if (nbytes >= len) */ subl nbytes_r, len_r /* len -= nbytes */ rep movsb movl out_r, from_r subl dist_r, from_r /* from = out - dist */ .L_do_copy1_mmx: #undef nbytes_r #define in_r %esi movl len_r, %ecx rep movsb movl in(%esp), in_r /* move in back to %esi, toss from */ movl lcode(%esp), %ebx /* move lcode back to %ebx, toss dist */ jmp .L_while_test_mmx #undef hold_r #undef bitslong_r #endif /* USE_MMX || RUN_TIME_MMX */ /*** USE_MMX, NO_MMX, and RUNTIME_MMX from here on ***/ .L_invalid_distance_code: /* else { * strm->msg = "invalid distance code"; * state->mode = BAD; * } */ movl $.L_invalid_distance_code_msg, %ecx movl $INFLATE_MODE_BAD, %edx jmp .L_update_stream_state .L_test_for_end_of_block: /* else if (op & 32) { * state->mode = TYPE; * break; * } */ testb $32, %al jz .L_invalid_literal_length_code /* if ((op & 32) == 0) */ movl $0, %ecx movl $INFLATE_MODE_TYPE, %edx jmp .L_update_stream_state .L_invalid_literal_length_code: /* else { * strm->msg = "invalid literal/length code"; * state->mode = BAD; * } */ movl $.L_invalid_literal_length_code_msg, %ecx movl $INFLATE_MODE_BAD, %edx jmp .L_update_stream_state .L_invalid_distance_too_far: /* strm->msg = "invalid distance too far back"; * state->mode = BAD; */ movl in(%esp), in_r /* from_r has in's reg, put in back */ movl $.L_invalid_distance_too_far_msg, %ecx movl $INFLATE_MODE_BAD, %edx jmp .L_update_stream_state .L_update_stream_state: /* set strm->msg = %ecx, strm->state->mode = %edx */ movl strm_sp(%esp), %eax testl %ecx, %ecx /* if (msg != NULL) */ jz .L_skip_msg movl %ecx, msg_strm(%eax) /* strm->msg = msg */ .L_skip_msg: movl state_strm(%eax), %eax /* state = strm->state */ movl %edx, mode_state(%eax) /* state->mode = edx (BAD | TYPE) */ jmp .L_break_loop .align 32,0x90 .L_break_loop: /* * Regs: * * bits = %ebp when mmx, and in %ebx when non-mmx * hold = %hold_mm when mmx, and in %ebp when non-mmx * in = %esi * out = %edi */ #if defined( USE_MMX ) || defined( RUN_TIME_MMX ) #if defined( RUN_TIME_MMX ) cmpl $DO_USE_MMX, inflate_fast_use_mmx jne .L_update_next_in #endif /* RUN_TIME_MMX */ movl %ebp, %ebx .L_update_next_in: #endif #define strm_r %eax #define state_r %edx /* len = bits >> 3; * in -= len; * bits -= len << 3; * hold &= (1U << bits) - 1; * state->hold = hold; * state->bits = bits; * strm->next_in = in; * strm->next_out = out; */ movl strm_sp(%esp), strm_r movl %ebx, %ecx movl state_strm(strm_r), state_r shrl $3, %ecx subl %ecx, in_r shll $3, %ecx subl %ecx, %ebx movl out_r, next_out_strm(strm_r) movl %ebx, bits_state(state_r) movl %ebx, %ecx leal buf(%esp), %ebx cmpl %ebx, last(%esp) jne .L_buf_not_used /* if buf != last */ subl %ebx, in_r /* in -= buf */ movl next_in_strm(strm_r), %ebx movl %ebx, last(%esp) /* last = strm->next_in */ addl %ebx, in_r /* in += strm->next_in */ movl avail_in_strm(strm_r), %ebx subl $11, %ebx addl %ebx, last(%esp) /* last = &strm->next_in[ avail_in - 11 ] */ .L_buf_not_used: movl in_r, next_in_strm(strm_r) movl $1, %ebx shll %cl, %ebx decl %ebx #if defined( USE_MMX ) || defined( RUN_TIME_MMX ) #if defined( RUN_TIME_MMX ) cmpl $DO_USE_MMX, inflate_fast_use_mmx jne .L_update_hold #endif /* RUN_TIME_MMX */ psrlq used_mm, hold_mm /* hold_mm >>= last bit length */ movd hold_mm, %ebp emms .L_update_hold: #endif /* USE_MMX || RUN_TIME_MMX */ andl %ebx, %ebp movl %ebp, hold_state(state_r) #define last_r %ebx /* strm->avail_in = in < last ? 11 + (last - in) : 11 - (in - last) */ movl last(%esp), last_r cmpl in_r, last_r jbe .L_last_is_smaller /* if (in >= last) */ subl in_r, last_r /* last -= in */ addl $11, last_r /* last += 11 */ movl last_r, avail_in_strm(strm_r) jmp .L_fixup_out .L_last_is_smaller: subl last_r, in_r /* in -= last */ negl in_r /* in = -in */ addl $11, in_r /* in += 11 */ movl in_r, avail_in_strm(strm_r) #undef last_r #define end_r %ebx .L_fixup_out: /* strm->avail_out = out < end ? 257 + (end - out) : 257 - (out - end)*/ movl end(%esp), end_r cmpl out_r, end_r jbe .L_end_is_smaller /* if (out >= end) */ subl out_r, end_r /* end -= out */ addl $257, end_r /* end += 257 */ movl end_r, avail_out_strm(strm_r) jmp .L_done .L_end_is_smaller: subl end_r, out_r /* out -= end */ negl out_r /* out = -out */ addl $257, out_r /* out += 257 */ movl out_r, avail_out_strm(strm_r) #undef end_r #undef strm_r #undef state_r .L_done: addl $local_var_size, %esp popf popl %ebx popl %ebp popl %esi popl %edi ret #if defined( GAS_ELF ) /* elf info */ .type inflate_fast,@function .size inflate_fast,.-inflate_fast #endif

stsp/binutils-ia16

15,839

zlib/contrib/gcc_gvmat64/gvmat64.S

/* ;uInt longest_match_x64( ; deflate_state *s, ; IPos cur_match); // current match ; gvmat64.S -- Asm portion of the optimized longest_match for 32 bits x86_64 ; (AMD64 on Athlon 64, Opteron, Phenom ; and Intel EM64T on Pentium 4 with EM64T, Pentium D, Core 2 Duo, Core I5/I7) ; this file is translation from gvmat64.asm to GCC 4.x (for Linux, Mac XCode) ; Copyright (C) 1995-2010 Jean-loup Gailly, Brian Raiter and Gilles Vollant. ; ; File written by Gilles Vollant, by converting to assembly the longest_match ; from Jean-loup Gailly in deflate.c of zLib and infoZip zip. ; and by taking inspiration on asm686 with masm, optimised assembly code ; from Brian Raiter, written 1998 ; ; This software is provided 'as-is', without any express or implied ; warranty. In no event will the authors be held liable for any damages ; arising from the use of this software. ; ; Permission is granted to anyone to use this software for any purpose, ; including commercial applications, and to alter it and redistribute it ; freely, subject to the following restrictions: ; ; 1. The origin of this software must not be misrepresented; you must not ; claim that you wrote the original software. If you use this software ; in a product, an acknowledgment in the product documentation would be ; appreciated but is not required. ; 2. Altered source versions must be plainly marked as such, and must not be ; misrepresented as being the original software ; 3. This notice may not be removed or altered from any source distribution. ; ; http://www.zlib.net ; http://www.winimage.com/zLibDll ; http://www.muppetlabs.com/~breadbox/software/assembly.html ; ; to compile this file for zLib, I use option: ; gcc -c -arch x86_64 gvmat64.S ;uInt longest_match(s, cur_match) ; deflate_state *s; ; IPos cur_match; // current match / ; ; with XCode for Mac, I had strange error with some jump on intel syntax ; this is why BEFORE_JMP and AFTER_JMP are used */ #define BEFORE_JMP .att_syntax #define AFTER_JMP .intel_syntax noprefix #ifndef NO_UNDERLINE # define match_init _match_init # define longest_match _longest_match #endif .intel_syntax noprefix .globl match_init, longest_match .text longest_match: #define LocalVarsSize 96 /* ; register used : rax,rbx,rcx,rdx,rsi,rdi,r8,r9,r10,r11,r12 ; free register : r14,r15 ; register can be saved : rsp */ #define chainlenwmask (rsp + 8 - LocalVarsSize) #define nicematch (rsp + 16 - LocalVarsSize) #define save_rdi (rsp + 24 - LocalVarsSize) #define save_rsi (rsp + 32 - LocalVarsSize) #define save_rbx (rsp + 40 - LocalVarsSize) #define save_rbp (rsp + 48 - LocalVarsSize) #define save_r12 (rsp + 56 - LocalVarsSize) #define save_r13 (rsp + 64 - LocalVarsSize) #define save_r14 (rsp + 72 - LocalVarsSize) #define save_r15 (rsp + 80 - LocalVarsSize) /* ; all the +4 offsets are due to the addition of pending_buf_size (in zlib ; in the deflate_state structure since the asm code was first written ; (if you compile with zlib 1.0.4 or older, remove the +4). ; Note : these value are good with a 8 bytes boundary pack structure */ #define MAX_MATCH 258 #define MIN_MATCH 3 #define MIN_LOOKAHEAD (MAX_MATCH+MIN_MATCH+1) /* ;;; Offsets for fields in the deflate_state structure. These numbers ;;; are calculated from the definition of deflate_state, with the ;;; assumption that the compiler will dword-align the fields. (Thus, ;;; changing the definition of deflate_state could easily cause this ;;; program to crash horribly, without so much as a warning at ;;; compile time. Sigh.) ; all the +zlib1222add offsets are due to the addition of fields ; in zlib in the deflate_state structure since the asm code was first written ; (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)"). ; (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0"). ; if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8"). */ /* you can check the structure offset by running #include <stdlib.h> #include <stdio.h> #include "deflate.h" void print_depl() { deflate_state ds; deflate_state *s=&ds; printf("size pointer=%u\n",(int)sizeof(void*)); printf("#define dsWSize %u\n",(int)(((char*)&(s->w_size))-((char*)s))); printf("#define dsWMask %u\n",(int)(((char*)&(s->w_mask))-((char*)s))); printf("#define dsWindow %u\n",(int)(((char*)&(s->window))-((char*)s))); printf("#define dsPrev %u\n",(int)(((char*)&(s->prev))-((char*)s))); printf("#define dsMatchLen %u\n",(int)(((char*)&(s->match_length))-((char*)s))); printf("#define dsPrevMatch %u\n",(int)(((char*)&(s->prev_match))-((char*)s))); printf("#define dsStrStart %u\n",(int)(((char*)&(s->strstart))-((char*)s))); printf("#define dsMatchStart %u\n",(int)(((char*)&(s->match_start))-((char*)s))); printf("#define dsLookahead %u\n",(int)(((char*)&(s->lookahead))-((char*)s))); printf("#define dsPrevLen %u\n",(int)(((char*)&(s->prev_length))-((char*)s))); printf("#define dsMaxChainLen %u\n",(int)(((char*)&(s->max_chain_length))-((char*)s))); printf("#define dsGoodMatch %u\n",(int)(((char*)&(s->good_match))-((char*)s))); printf("#define dsNiceMatch %u\n",(int)(((char*)&(s->nice_match))-((char*)s))); } */ #define dsWSize 68 #define dsWMask 76 #define dsWindow 80 #define dsPrev 96 #define dsMatchLen 144 #define dsPrevMatch 148 #define dsStrStart 156 #define dsMatchStart 160 #define dsLookahead 164 #define dsPrevLen 168 #define dsMaxChainLen 172 #define dsGoodMatch 188 #define dsNiceMatch 192 #define window_size [ rcx + dsWSize] #define WMask [ rcx + dsWMask] #define window_ad [ rcx + dsWindow] #define prev_ad [ rcx + dsPrev] #define strstart [ rcx + dsStrStart] #define match_start [ rcx + dsMatchStart] #define Lookahead [ rcx + dsLookahead] //; 0ffffffffh on infozip #define prev_length [ rcx + dsPrevLen] #define max_chain_length [ rcx + dsMaxChainLen] #define good_match [ rcx + dsGoodMatch] #define nice_match [ rcx + dsNiceMatch] /* ; windows: ; parameter 1 in rcx(deflate state s), param 2 in rdx (cur match) ; see http://weblogs.asp.net/oldnewthing/archive/2004/01/14/58579.aspx and ; http://msdn.microsoft.com/library/en-us/kmarch/hh/kmarch/64bitAMD_8e951dd2-ee77-4728-8702-55ce4b5dd24a.xml.asp ; ; All registers must be preserved across the call, except for ; rax, rcx, rdx, r8, r9, r10, and r11, which are scratch. ; ; gcc on macosx-linux: ; see http://www.x86-64.org/documentation/abi-0.99.pdf ; param 1 in rdi, param 2 in rsi ; rbx, rsp, rbp, r12 to r15 must be preserved ;;; Save registers that the compiler may be using, and adjust esp to ;;; make room for our stack frame. ;;; Retrieve the function arguments. r8d will hold cur_match ;;; throughout the entire function. edx will hold the pointer to the ;;; deflate_state structure during the function's setup (before ;;; entering the main loop. ; ms: parameter 1 in rcx (deflate_state* s), param 2 in edx -> r8 (cur match) ; mac: param 1 in rdi, param 2 rsi ; this clear high 32 bits of r8, which can be garbage in both r8 and rdx */ mov [save_rbx],rbx mov [save_rbp],rbp mov rcx,rdi mov r8d,esi mov [save_r12],r12 mov [save_r13],r13 mov [save_r14],r14 mov [save_r15],r15 //;;; uInt wmask = s->w_mask; //;;; unsigned chain_length = s->max_chain_length; //;;; if (s->prev_length >= s->good_match) { //;;; chain_length >>= 2; //;;; } mov edi, prev_length mov esi, good_match mov eax, WMask mov ebx, max_chain_length cmp edi, esi jl LastMatchGood shr ebx, 2 LastMatchGood: //;;; chainlen is decremented once beforehand so that the function can //;;; use the sign flag instead of the zero flag for the exit test. //;;; It is then shifted into the high word, to make room for the wmask //;;; value, which it will always accompany. dec ebx shl ebx, 16 or ebx, eax //;;; on zlib only //;;; if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; mov eax, nice_match mov [chainlenwmask], ebx mov r10d, Lookahead cmp r10d, eax cmovnl r10d, eax mov [nicematch],r10d //;;; register Bytef *scan = s->window + s->strstart; mov r10, window_ad mov ebp, strstart lea r13, [r10 + rbp] //;;; Determine how many bytes the scan ptr is off from being //;;; dword-aligned. mov r9,r13 neg r13 and r13,3 //;;; IPos limit = s->strstart > (IPos)MAX_DIST(s) ? //;;; s->strstart - (IPos)MAX_DIST(s) : NIL; mov eax, window_size sub eax, MIN_LOOKAHEAD xor edi,edi sub ebp, eax mov r11d, prev_length cmovng ebp,edi //;;; int best_len = s->prev_length; //;;; Store the sum of s->window + best_len in esi locally, and in esi. lea rsi,[r10+r11] //;;; register ush scan_start = *(ushf*)scan; //;;; register ush scan_end = *(ushf*)(scan+best_len-1); //;;; Posf *prev = s->prev; movzx r12d,word ptr [r9] movzx ebx, word ptr [r9 + r11 - 1] mov rdi, prev_ad //;;; Jump into the main loop. mov edx, [chainlenwmask] cmp bx,word ptr [rsi + r8 - 1] jz LookupLoopIsZero LookupLoop1: and r8d, edx movzx r8d, word ptr [rdi + r8*2] cmp r8d, ebp jbe LeaveNow sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry1: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jz LookupLoopIsZero AFTER_JMP LookupLoop2: and r8d, edx movzx r8d, word ptr [rdi + r8*2] cmp r8d, ebp BEFORE_JMP jbe LeaveNow AFTER_JMP sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry2: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jz LookupLoopIsZero AFTER_JMP LookupLoop4: and r8d, edx movzx r8d, word ptr [rdi + r8*2] cmp r8d, ebp BEFORE_JMP jbe LeaveNow AFTER_JMP sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry4: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jnz LookupLoop1 jmp LookupLoopIsZero AFTER_JMP /* ;;; do { ;;; match = s->window + cur_match; ;;; if (*(ushf*)(match+best_len-1) != scan_end || ;;; *(ushf*)match != scan_start) continue; ;;; [...] ;;; } while ((cur_match = prev[cur_match & wmask]) > limit ;;; && --chain_length != 0); ;;; ;;; Here is the inner loop of the function. The function will spend the ;;; majority of its time in this loop, and majority of that time will ;;; be spent in the first ten instructions. ;;; ;;; Within this loop: ;;; ebx = scanend ;;; r8d = curmatch ;;; edx = chainlenwmask - i.e., ((chainlen << 16) | wmask) ;;; esi = windowbestlen - i.e., (window + bestlen) ;;; edi = prev ;;; ebp = limit */ .balign 16 LookupLoop: and r8d, edx movzx r8d, word ptr [rdi + r8*2] cmp r8d, ebp BEFORE_JMP jbe LeaveNow AFTER_JMP sub edx, 0x00010000 BEFORE_JMP js LeaveNow AFTER_JMP LoopEntry: cmp bx,word ptr [rsi + r8 - 1] BEFORE_JMP jnz LookupLoop1 AFTER_JMP LookupLoopIsZero: cmp r12w, word ptr [r10 + r8] BEFORE_JMP jnz LookupLoop1 AFTER_JMP //;;; Store the current value of chainlen. mov [chainlenwmask], edx /* ;;; Point edi to the string under scrutiny, and esi to the string we ;;; are hoping to match it up with. In actuality, esi and edi are ;;; both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and edx is ;;; initialized to -(MAX_MATCH_8 - scanalign). */ lea rsi,[r8+r10] mov rdx, 0xfffffffffffffef8 //; -(MAX_MATCH_8) lea rsi, [rsi + r13 + 0x0108] //;MAX_MATCH_8] lea rdi, [r9 + r13 + 0x0108] //;MAX_MATCH_8] prefetcht1 [rsi+rdx] prefetcht1 [rdi+rdx] /* ;;; Test the strings for equality, 8 bytes at a time. At the end, ;;; adjust rdx so that it is offset to the exact byte that mismatched. ;;; ;;; We already know at this point that the first three bytes of the ;;; strings match each other, and they can be safely passed over before ;;; starting the compare loop. So what this code does is skip over 0-3 ;;; bytes, as much as necessary in order to dword-align the edi ;;; pointer. (rsi will still be misaligned three times out of four.) ;;; ;;; It should be confessed that this loop usually does not represent ;;; much of the total running time. Replacing it with a more ;;; straightforward "rep cmpsb" would not drastically degrade ;;; performance. */ LoopCmps: mov rax, [rsi + rdx] xor rax, [rdi + rdx] jnz LeaveLoopCmps mov rax, [rsi + rdx + 8] xor rax, [rdi + rdx + 8] jnz LeaveLoopCmps8 mov rax, [rsi + rdx + 8+8] xor rax, [rdi + rdx + 8+8] jnz LeaveLoopCmps16 add rdx,8+8+8 BEFORE_JMP jnz LoopCmps jmp LenMaximum AFTER_JMP LeaveLoopCmps16: add rdx,8 LeaveLoopCmps8: add rdx,8 LeaveLoopCmps: test eax, 0x0000FFFF jnz LenLower test eax,0xffffffff jnz LenLower32 add rdx,4 shr rax,32 or ax,ax BEFORE_JMP jnz LenLower AFTER_JMP LenLower32: shr eax,16 add rdx,2 LenLower: sub al, 1 adc rdx, 0 //;;; Calculate the length of the match. If it is longer than MAX_MATCH, //;;; then automatically accept it as the best possible match and leave. lea rax, [rdi + rdx] sub rax, r9 cmp eax, MAX_MATCH BEFORE_JMP jge LenMaximum AFTER_JMP /* ;;; If the length of the match is not longer than the best match we ;;; have so far, then forget it and return to the lookup loop. ;/////////////////////////////////// */ cmp eax, r11d jg LongerMatch lea rsi,[r10+r11] mov rdi, prev_ad mov edx, [chainlenwmask] BEFORE_JMP jmp LookupLoop AFTER_JMP /* ;;; s->match_start = cur_match; ;;; best_len = len; ;;; if (len >= nice_match) break; ;;; scan_end = *(ushf*)(scan+best_len-1); */ LongerMatch: mov r11d, eax mov match_start, r8d cmp eax, [nicematch] BEFORE_JMP jge LeaveNow AFTER_JMP lea rsi,[r10+rax] movzx ebx, word ptr [r9 + rax - 1] mov rdi, prev_ad mov edx, [chainlenwmask] BEFORE_JMP jmp LookupLoop AFTER_JMP //;;; Accept the current string, with the maximum possible length. LenMaximum: mov r11d,MAX_MATCH mov match_start, r8d //;;; if ((uInt)best_len <= s->lookahead) return (uInt)best_len; //;;; return s->lookahead; LeaveNow: mov eax, Lookahead cmp r11d, eax cmovng eax, r11d //;;; Restore the stack and return from whence we came. // mov rsi,[save_rsi] // mov rdi,[save_rdi] mov rbx,[save_rbx] mov rbp,[save_rbp] mov r12,[save_r12] mov r13,[save_r13] mov r14,[save_r14] mov r15,[save_r15] ret 0 //; please don't remove this string ! //; Your can freely use gvmat64 in any free or commercial app //; but it is far better don't remove the string in the binary! // db 0dh,0ah,"asm686 with masm, optimised assembly code from Brian Raiter, written 1998, converted to amd 64 by Gilles Vollant 2005",0dh,0ah,0 match_init: ret 0

stsp/binutils-ia16

12,418

zlib/contrib/amd64/amd64-match.S

/* * match.S -- optimized version of longest_match() * based on the similar work by Gilles Vollant, and Brian Raiter, written 1998 * * This is free software; you can redistribute it and/or modify it * under the terms of the BSD License. Use by owners of Che Guevarra * parafernalia is prohibited, where possible, and highly discouraged * elsewhere. */ #ifndef NO_UNDERLINE # define match_init _match_init # define longest_match _longest_match #endif #define scanend ebx #define scanendw bx #define chainlenwmask edx /* high word: current chain len low word: s->wmask */ #define curmatch rsi #define curmatchd esi #define windowbestlen r8 #define scanalign r9 #define scanalignd r9d #define window r10 #define bestlen r11 #define bestlend r11d #define scanstart r12d #define scanstartw r12w #define scan r13 #define nicematch r14d #define limit r15 #define limitd r15d #define prev rcx /* * The 258 is a "magic number, not a parameter -- changing it * breaks the hell loose */ #define MAX_MATCH (258) #define MIN_MATCH (3) #define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1) #define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7) /* stack frame offsets */ #define LocalVarsSize (112) #define _chainlenwmask ( 8-LocalVarsSize)(%rsp) #define _windowbestlen (16-LocalVarsSize)(%rsp) #define save_r14 (24-LocalVarsSize)(%rsp) #define save_rsi (32-LocalVarsSize)(%rsp) #define save_rbx (40-LocalVarsSize)(%rsp) #define save_r12 (56-LocalVarsSize)(%rsp) #define save_r13 (64-LocalVarsSize)(%rsp) #define save_r15 (80-LocalVarsSize)(%rsp) .globl match_init, longest_match /* * On AMD64 the first argument of a function (in our case -- the pointer to * deflate_state structure) is passed in %rdi, hence our offsets below are * all off of that. */ /* you can check the structure offset by running #include <stdlib.h> #include <stdio.h> #include "deflate.h" void print_depl() { deflate_state ds; deflate_state *s=&ds; printf("size pointer=%u\n",(int)sizeof(void*)); printf("#define dsWSize (%3u)(%%rdi)\n",(int)(((char*)&(s->w_size))-((char*)s))); printf("#define dsWMask (%3u)(%%rdi)\n",(int)(((char*)&(s->w_mask))-((char*)s))); printf("#define dsWindow (%3u)(%%rdi)\n",(int)(((char*)&(s->window))-((char*)s))); printf("#define dsPrev (%3u)(%%rdi)\n",(int)(((char*)&(s->prev))-((char*)s))); printf("#define dsMatchLen (%3u)(%%rdi)\n",(int)(((char*)&(s->match_length))-((char*)s))); printf("#define dsPrevMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_match))-((char*)s))); printf("#define dsStrStart (%3u)(%%rdi)\n",(int)(((char*)&(s->strstart))-((char*)s))); printf("#define dsMatchStart (%3u)(%%rdi)\n",(int)(((char*)&(s->match_start))-((char*)s))); printf("#define dsLookahead (%3u)(%%rdi)\n",(int)(((char*)&(s->lookahead))-((char*)s))); printf("#define dsPrevLen (%3u)(%%rdi)\n",(int)(((char*)&(s->prev_length))-((char*)s))); printf("#define dsMaxChainLen (%3u)(%%rdi)\n",(int)(((char*)&(s->max_chain_length))-((char*)s))); printf("#define dsGoodMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->good_match))-((char*)s))); printf("#define dsNiceMatch (%3u)(%%rdi)\n",(int)(((char*)&(s->nice_match))-((char*)s))); } */ /* to compile for XCode 3.2 on MacOSX x86_64 - run "gcc -g -c -DXCODE_MAC_X64_STRUCTURE amd64-match.S" */ #ifndef CURRENT_LINX_XCODE_MAC_X64_STRUCTURE #define dsWSize ( 68)(%rdi) #define dsWMask ( 76)(%rdi) #define dsWindow ( 80)(%rdi) #define dsPrev ( 96)(%rdi) #define dsMatchLen (144)(%rdi) #define dsPrevMatch (148)(%rdi) #define dsStrStart (156)(%rdi) #define dsMatchStart (160)(%rdi) #define dsLookahead (164)(%rdi) #define dsPrevLen (168)(%rdi) #define dsMaxChainLen (172)(%rdi) #define dsGoodMatch (188)(%rdi) #define dsNiceMatch (192)(%rdi) #else #ifndef STRUCT_OFFSET # define STRUCT_OFFSET (0) #endif #define dsWSize ( 56 + STRUCT_OFFSET)(%rdi) #define dsWMask ( 64 + STRUCT_OFFSET)(%rdi) #define dsWindow ( 72 + STRUCT_OFFSET)(%rdi) #define dsPrev ( 88 + STRUCT_OFFSET)(%rdi) #define dsMatchLen (136 + STRUCT_OFFSET)(%rdi) #define dsPrevMatch (140 + STRUCT_OFFSET)(%rdi) #define dsStrStart (148 + STRUCT_OFFSET)(%rdi) #define dsMatchStart (152 + STRUCT_OFFSET)(%rdi) #define dsLookahead (156 + STRUCT_OFFSET)(%rdi) #define dsPrevLen (160 + STRUCT_OFFSET)(%rdi) #define dsMaxChainLen (164 + STRUCT_OFFSET)(%rdi) #define dsGoodMatch (180 + STRUCT_OFFSET)(%rdi) #define dsNiceMatch (184 + STRUCT_OFFSET)(%rdi) #endif .text /* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */ longest_match: /* * Retrieve the function arguments. %curmatch will hold cur_match * throughout the entire function (passed via rsi on amd64). * rdi will hold the pointer to the deflate_state (first arg on amd64) */ mov %rsi, save_rsi mov %rbx, save_rbx mov %r12, save_r12 mov %r13, save_r13 mov %r14, save_r14 mov %r15, save_r15 /* uInt wmask = s->w_mask; */ /* unsigned chain_length = s->max_chain_length; */ /* if (s->prev_length >= s->good_match) { */ /* chain_length >>= 2; */ /* } */ movl dsPrevLen, %eax movl dsGoodMatch, %ebx cmpl %ebx, %eax movl dsWMask, %eax movl dsMaxChainLen, %chainlenwmask jl LastMatchGood shrl $2, %chainlenwmask LastMatchGood: /* chainlen is decremented once beforehand so that the function can */ /* use the sign flag instead of the zero flag for the exit test. */ /* It is then shifted into the high word, to make room for the wmask */ /* value, which it will always accompany. */ decl %chainlenwmask shll $16, %chainlenwmask orl %eax, %chainlenwmask /* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */ movl dsNiceMatch, %eax movl dsLookahead, %ebx cmpl %eax, %ebx jl LookaheadLess movl %eax, %ebx LookaheadLess: movl %ebx, %nicematch /* register Bytef *scan = s->window + s->strstart; */ mov dsWindow, %window movl dsStrStart, %limitd lea (%limit, %window), %scan /* Determine how many bytes the scan ptr is off from being */ /* dword-aligned. */ mov %scan, %scanalign negl %scanalignd andl $3, %scanalignd /* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */ /* s->strstart - (IPos)MAX_DIST(s) : NIL; */ movl dsWSize, %eax subl $MIN_LOOKAHEAD, %eax xorl %ecx, %ecx subl %eax, %limitd cmovng %ecx, %limitd /* int best_len = s->prev_length; */ movl dsPrevLen, %bestlend /* Store the sum of s->window + best_len in %windowbestlen locally, and in memory. */ lea (%window, %bestlen), %windowbestlen mov %windowbestlen, _windowbestlen /* register ush scan_start = *(ushf*)scan; */ /* register ush scan_end = *(ushf*)(scan+best_len-1); */ /* Posf *prev = s->prev; */ movzwl (%scan), %scanstart movzwl -1(%scan, %bestlen), %scanend mov dsPrev, %prev /* Jump into the main loop. */ movl %chainlenwmask, _chainlenwmask jmp LoopEntry .balign 16 /* do { * match = s->window + cur_match; * if (*(ushf*)(match+best_len-1) != scan_end || * *(ushf*)match != scan_start) continue; * [...] * } while ((cur_match = prev[cur_match & wmask]) > limit * && --chain_length != 0); * * Here is the inner loop of the function. The function will spend the * majority of its time in this loop, and majority of that time will * be spent in the first ten instructions. */ LookupLoop: andl %chainlenwmask, %curmatchd movzwl (%prev, %curmatch, 2), %curmatchd cmpl %limitd, %curmatchd jbe LeaveNow subl $0x00010000, %chainlenwmask js LeaveNow LoopEntry: cmpw -1(%windowbestlen, %curmatch), %scanendw jne LookupLoop cmpw %scanstartw, (%window, %curmatch) jne LookupLoop /* Store the current value of chainlen. */ movl %chainlenwmask, _chainlenwmask /* %scan is the string under scrutiny, and %prev to the string we */ /* are hoping to match it up with. In actuality, %esi and %edi are */ /* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */ /* initialized to -(MAX_MATCH_8 - scanalign). */ mov $(-MAX_MATCH_8), %rdx lea (%curmatch, %window), %windowbestlen lea MAX_MATCH_8(%windowbestlen, %scanalign), %windowbestlen lea MAX_MATCH_8(%scan, %scanalign), %prev /* the prefetching below makes very little difference... */ prefetcht1 (%windowbestlen, %rdx) prefetcht1 (%prev, %rdx) /* * Test the strings for equality, 8 bytes at a time. At the end, * adjust %rdx so that it is offset to the exact byte that mismatched. * * It should be confessed that this loop usually does not represent * much of the total running time. Replacing it with a more * straightforward "rep cmpsb" would not drastically degrade * performance -- unrolling it, for example, makes no difference. */ #undef USE_SSE /* works, but is 6-7% slower, than non-SSE... */ LoopCmps: #ifdef USE_SSE /* Preload the SSE registers */ movdqu (%windowbestlen, %rdx), %xmm1 movdqu (%prev, %rdx), %xmm2 pcmpeqb %xmm2, %xmm1 movdqu 16(%windowbestlen, %rdx), %xmm3 movdqu 16(%prev, %rdx), %xmm4 pcmpeqb %xmm4, %xmm3 movdqu 32(%windowbestlen, %rdx), %xmm5 movdqu 32(%prev, %rdx), %xmm6 pcmpeqb %xmm6, %xmm5 movdqu 48(%windowbestlen, %rdx), %xmm7 movdqu 48(%prev, %rdx), %xmm8 pcmpeqb %xmm8, %xmm7 /* Check the comparisions' results */ pmovmskb %xmm1, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps /* this is the only iteration of the loop with a possibility of having incremented rdx by 0x108 (each loop iteration add 16*4 = 0x40 and (0x40*4)+8=0x108 */ add $8, %rdx jz LenMaximum add $8, %rdx pmovmskb %xmm3, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps add $16, %rdx pmovmskb %xmm5, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps add $16, %rdx pmovmskb %xmm7, %rax notw %ax bsfw %ax, %ax jnz LeaveLoopCmps add $16, %rdx jmp LoopCmps LeaveLoopCmps: add %rax, %rdx #else mov (%windowbestlen, %rdx), %rax xor (%prev, %rdx), %rax jnz LeaveLoopCmps mov 8(%windowbestlen, %rdx), %rax xor 8(%prev, %rdx), %rax jnz LeaveLoopCmps8 mov 16(%windowbestlen, %rdx), %rax xor 16(%prev, %rdx), %rax jnz LeaveLoopCmps16 add $24, %rdx jnz LoopCmps jmp LenMaximum # if 0 /* * This three-liner is tantalizingly simple, but bsf is a slow instruction, * and the complicated alternative down below is quite a bit faster. Sad... */ LeaveLoopCmps: bsf %rax, %rax /* find the first non-zero bit */ shrl $3, %eax /* divide by 8 to get the byte */ add %rax, %rdx # else LeaveLoopCmps16: add $8, %rdx LeaveLoopCmps8: add $8, %rdx LeaveLoopCmps: testl $0xFFFFFFFF, %eax /* Check the first 4 bytes */ jnz Check16 add $4, %rdx shr $32, %rax Check16: testw $0xFFFF, %ax jnz LenLower add $2, %rdx shrl $16, %eax LenLower: subb $1, %al adc $0, %rdx # endif #endif /* Calculate the length of the match. If it is longer than MAX_MATCH, */ /* then automatically accept it as the best possible match and leave. */ lea (%prev, %rdx), %rax sub %scan, %rax cmpl $MAX_MATCH, %eax jge LenMaximum /* If the length of the match is not longer than the best match we */ /* have so far, then forget it and return to the lookup loop. */ cmpl %bestlend, %eax jg LongerMatch mov _windowbestlen, %windowbestlen mov dsPrev, %prev movl _chainlenwmask, %edx jmp LookupLoop /* s->match_start = cur_match; */ /* best_len = len; */ /* if (len >= nice_match) break; */ /* scan_end = *(ushf*)(scan+best_len-1); */ LongerMatch: movl %eax, %bestlend movl %curmatchd, dsMatchStart cmpl %nicematch, %eax jge LeaveNow lea (%window, %bestlen), %windowbestlen mov %windowbestlen, _windowbestlen movzwl -1(%scan, %rax), %scanend mov dsPrev, %prev movl _chainlenwmask, %chainlenwmask jmp LookupLoop /* Accept the current string, with the maximum possible length. */ LenMaximum: movl $MAX_MATCH, %bestlend movl %curmatchd, dsMatchStart /* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */ /* return s->lookahead; */ LeaveNow: movl dsLookahead, %eax cmpl %eax, %bestlend cmovngl %bestlend, %eax LookaheadRet: /* Restore the registers and return from whence we came. */ mov save_rsi, %rsi mov save_rbx, %rbx mov save_r12, %r12 mov save_r13, %r13 mov save_r14, %r14 mov save_r15, %r15 ret match_init: ret

stsp/binutils-ia16

10,365

zlib/contrib/asm686/match.S

/* match.S -- x86 assembly version of the zlib longest_match() function. * Optimized for the Intel 686 chips (PPro and later). * * Copyright (C) 1998, 2007 Brian Raiter <breadbox@muppetlabs.com> * * This software is provided 'as-is', without any express or implied * warranty. In no event will the author be held liable for any damages * arising from the use of this software. * * Permission is granted to anyone to use this software for any purpose, * including commercial applications, and to alter it and redistribute it * freely, subject to the following restrictions: * * 1. The origin of this software must not be misrepresented; you must not * claim that you wrote the original software. If you use this software * in a product, an acknowledgment in the product documentation would be * appreciated but is not required. * 2. Altered source versions must be plainly marked as such, and must not be * misrepresented as being the original software. * 3. This notice may not be removed or altered from any source distribution. */ #ifndef NO_UNDERLINE #define match_init _match_init #define longest_match _longest_match #endif #define MAX_MATCH (258) #define MIN_MATCH (3) #define MIN_LOOKAHEAD (MAX_MATCH + MIN_MATCH + 1) #define MAX_MATCH_8 ((MAX_MATCH + 7) & ~7) /* stack frame offsets */ #define chainlenwmask 0 /* high word: current chain len */ /* low word: s->wmask */ #define window 4 /* local copy of s->window */ #define windowbestlen 8 /* s->window + bestlen */ #define scanstart 16 /* first two bytes of string */ #define scanend 12 /* last two bytes of string */ #define scanalign 20 /* dword-misalignment of string */ #define nicematch 24 /* a good enough match size */ #define bestlen 28 /* size of best match so far */ #define scan 32 /* ptr to string wanting match */ #define LocalVarsSize (36) /* saved ebx 36 */ /* saved edi 40 */ /* saved esi 44 */ /* saved ebp 48 */ /* return address 52 */ #define deflatestate 56 /* the function arguments */ #define curmatch 60 /* All the +zlib1222add offsets are due to the addition of fields * in zlib in the deflate_state structure since the asm code was first written * (if you compile with zlib 1.0.4 or older, use "zlib1222add equ (-4)"). * (if you compile with zlib between 1.0.5 and 1.2.2.1, use "zlib1222add equ 0"). * if you compile with zlib 1.2.2.2 or later , use "zlib1222add equ 8"). */ #define zlib1222add (8) #define dsWSize (36+zlib1222add) #define dsWMask (44+zlib1222add) #define dsWindow (48+zlib1222add) #define dsPrev (56+zlib1222add) #define dsMatchLen (88+zlib1222add) #define dsPrevMatch (92+zlib1222add) #define dsStrStart (100+zlib1222add) #define dsMatchStart (104+zlib1222add) #define dsLookahead (108+zlib1222add) #define dsPrevLen (112+zlib1222add) #define dsMaxChainLen (116+zlib1222add) #define dsGoodMatch (132+zlib1222add) #define dsNiceMatch (136+zlib1222add) .file "match.S" .globl match_init, longest_match .text /* uInt longest_match(deflate_state *deflatestate, IPos curmatch) */ .cfi_sections .debug_frame longest_match: .cfi_startproc /* Save registers that the compiler may be using, and adjust %esp to */ /* make room for our stack frame. */ pushl %ebp .cfi_def_cfa_offset 8 .cfi_offset ebp, -8 pushl %edi .cfi_def_cfa_offset 12 pushl %esi .cfi_def_cfa_offset 16 pushl %ebx .cfi_def_cfa_offset 20 subl $LocalVarsSize, %esp .cfi_def_cfa_offset LocalVarsSize+20 /* Retrieve the function arguments. %ecx will hold cur_match */ /* throughout the entire function. %edx will hold the pointer to the */ /* deflate_state structure during the function's setup (before */ /* entering the main loop). */ movl deflatestate(%esp), %edx movl curmatch(%esp), %ecx /* uInt wmask = s->w_mask; */ /* unsigned chain_length = s->max_chain_length; */ /* if (s->prev_length >= s->good_match) { */ /* chain_length >>= 2; */ /* } */ movl dsPrevLen(%edx), %eax movl dsGoodMatch(%edx), %ebx cmpl %ebx, %eax movl dsWMask(%edx), %eax movl dsMaxChainLen(%edx), %ebx jl LastMatchGood shrl $2, %ebx LastMatchGood: /* chainlen is decremented once beforehand so that the function can */ /* use the sign flag instead of the zero flag for the exit test. */ /* It is then shifted into the high word, to make room for the wmask */ /* value, which it will always accompany. */ decl %ebx shll $16, %ebx orl %eax, %ebx movl %ebx, chainlenwmask(%esp) /* if ((uInt)nice_match > s->lookahead) nice_match = s->lookahead; */ movl dsNiceMatch(%edx), %eax movl dsLookahead(%edx), %ebx cmpl %eax, %ebx jl LookaheadLess movl %eax, %ebx LookaheadLess: movl %ebx, nicematch(%esp) /* register Bytef *scan = s->window + s->strstart; */ movl dsWindow(%edx), %esi movl %esi, window(%esp) movl dsStrStart(%edx), %ebp lea (%esi,%ebp), %edi movl %edi, scan(%esp) /* Determine how many bytes the scan ptr is off from being */ /* dword-aligned. */ movl %edi, %eax negl %eax andl $3, %eax movl %eax, scanalign(%esp) /* IPos limit = s->strstart > (IPos)MAX_DIST(s) ? */ /* s->strstart - (IPos)MAX_DIST(s) : NIL; */ movl dsWSize(%edx), %eax subl $MIN_LOOKAHEAD, %eax subl %eax, %ebp jg LimitPositive xorl %ebp, %ebp LimitPositive: /* int best_len = s->prev_length; */ movl dsPrevLen(%edx), %eax movl %eax, bestlen(%esp) /* Store the sum of s->window + best_len in %esi locally, and in %esi. */ addl %eax, %esi movl %esi, windowbestlen(%esp) /* register ush scan_start = *(ushf*)scan; */ /* register ush scan_end = *(ushf*)(scan+best_len-1); */ /* Posf *prev = s->prev; */ movzwl (%edi), %ebx movl %ebx, scanstart(%esp) movzwl -1(%edi,%eax), %ebx movl %ebx, scanend(%esp) movl dsPrev(%edx), %edi /* Jump into the main loop. */ movl chainlenwmask(%esp), %edx jmp LoopEntry .balign 16 /* do { * match = s->window + cur_match; * if (*(ushf*)(match+best_len-1) != scan_end || * *(ushf*)match != scan_start) continue; * [...] * } while ((cur_match = prev[cur_match & wmask]) > limit * && --chain_length != 0); * * Here is the inner loop of the function. The function will spend the * majority of its time in this loop, and majority of that time will * be spent in the first ten instructions. * * Within this loop: * %ebx = scanend * %ecx = curmatch * %edx = chainlenwmask - i.e., ((chainlen << 16) | wmask) * %esi = windowbestlen - i.e., (window + bestlen) * %edi = prev * %ebp = limit */ LookupLoop: andl %edx, %ecx movzwl (%edi,%ecx,2), %ecx cmpl %ebp, %ecx jbe LeaveNow subl $0x00010000, %edx js LeaveNow LoopEntry: movzwl -1(%esi,%ecx), %eax cmpl %ebx, %eax jnz LookupLoop movl window(%esp), %eax movzwl (%eax,%ecx), %eax cmpl scanstart(%esp), %eax jnz LookupLoop /* Store the current value of chainlen. */ movl %edx, chainlenwmask(%esp) /* Point %edi to the string under scrutiny, and %esi to the string we */ /* are hoping to match it up with. In actuality, %esi and %edi are */ /* both pointed (MAX_MATCH_8 - scanalign) bytes ahead, and %edx is */ /* initialized to -(MAX_MATCH_8 - scanalign). */ movl window(%esp), %esi movl scan(%esp), %edi addl %ecx, %esi movl scanalign(%esp), %eax movl $(-MAX_MATCH_8), %edx lea MAX_MATCH_8(%edi,%eax), %edi lea MAX_MATCH_8(%esi,%eax), %esi /* Test the strings for equality, 8 bytes at a time. At the end, * adjust %edx so that it is offset to the exact byte that mismatched. * * We already know at this point that the first three bytes of the * strings match each other, and they can be safely passed over before * starting the compare loop. So what this code does is skip over 0-3 * bytes, as much as necessary in order to dword-align the %edi * pointer. (%esi will still be misaligned three times out of four.) * * It should be confessed that this loop usually does not represent * much of the total running time. Replacing it with a more * straightforward "rep cmpsb" would not drastically degrade * performance. */ LoopCmps: movl (%esi,%edx), %eax xorl (%edi,%edx), %eax jnz LeaveLoopCmps movl 4(%esi,%edx), %eax xorl 4(%edi,%edx), %eax jnz LeaveLoopCmps4 addl $8, %edx jnz LoopCmps jmp LenMaximum LeaveLoopCmps4: addl $4, %edx LeaveLoopCmps: testl $0x0000FFFF, %eax jnz LenLower addl $2, %edx shrl $16, %eax LenLower: subb $1, %al adcl $0, %edx /* Calculate the length of the match. If it is longer than MAX_MATCH, */ /* then automatically accept it as the best possible match and leave. */ lea (%edi,%edx), %eax movl scan(%esp), %edi subl %edi, %eax cmpl $MAX_MATCH, %eax jge LenMaximum /* If the length of the match is not longer than the best match we */ /* have so far, then forget it and return to the lookup loop. */ movl deflatestate(%esp), %edx movl bestlen(%esp), %ebx cmpl %ebx, %eax jg LongerMatch movl windowbestlen(%esp), %esi movl dsPrev(%edx), %edi movl scanend(%esp), %ebx movl chainlenwmask(%esp), %edx jmp LookupLoop /* s->match_start = cur_match; */ /* best_len = len; */ /* if (len >= nice_match) break; */ /* scan_end = *(ushf*)(scan+best_len-1); */ LongerMatch: movl nicematch(%esp), %ebx movl %eax, bestlen(%esp) movl %ecx, dsMatchStart(%edx) cmpl %ebx, %eax jge LeaveNow movl window(%esp), %esi addl %eax, %esi movl %esi, windowbestlen(%esp) movzwl -1(%edi,%eax), %ebx movl dsPrev(%edx), %edi movl %ebx, scanend(%esp) movl chainlenwmask(%esp), %edx jmp LookupLoop /* Accept the current string, with the maximum possible length. */ LenMaximum: movl deflatestate(%esp), %edx movl $MAX_MATCH, bestlen(%esp) movl %ecx, dsMatchStart(%edx) /* if ((uInt)best_len <= s->lookahead) return (uInt)best_len; */ /* return s->lookahead; */ LeaveNow: movl deflatestate(%esp), %edx movl bestlen(%esp), %ebx movl dsLookahead(%edx), %eax cmpl %eax, %ebx jg LookaheadRet movl %ebx, %eax LookaheadRet: /* Restore the stack and return from whence we came. */ addl $LocalVarsSize, %esp .cfi_def_cfa_offset 20 popl %ebx .cfi_def_cfa_offset 16 popl %esi .cfi_def_cfa_offset 12 popl %edi .cfi_def_cfa_offset 8 popl %ebp .cfi_def_cfa_offset 4 .cfi_endproc match_init: ret

stsp/binutils-ia16

10,965

ld/emultempl/spu_ovl.S

/* Overlay manager for SPU. Copyright (C) 2006-2022 Free Software Foundation, Inc. This file is part of the GNU Binutils. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* MFC DMA defn's. */ #define MFC_GET_CMD 0x40 #define MFC_MAX_DMA_SIZE 0x4000 #define MFC_TAG_UPDATE_ALL 2 #define MFC_TAG_ID 0 /* Register usage. */ #define reserved1 $75 #define parm $75 #define tab1 reserved1 #define tab2 reserved1 #define vma reserved1 #define oldvma reserved1 #define newmask reserved1 #define map reserved1 #define reserved2 $76 #define off1 reserved2 #define off2 reserved2 #define present1 reserved2 #define present2 reserved2 #define sz reserved2 #define cmp reserved2 #define add64 reserved2 #define cgbits reserved2 #define off3 reserved2 #define off4 reserved2 #define addr4 reserved2 #define off5 reserved2 #define tagstat reserved2 #define reserved3 $77 #define size1 reserved3 #define size2 reserved3 #define rv3 reserved3 #define ealo reserved3 #define cmd reserved3 #define off64 reserved3 #define tab3 reserved3 #define tab4 reserved3 #define tab5 reserved3 #define reserved4 $78 #define ovl reserved4 #define rv2 reserved4 #define rv5 reserved4 #define cgshuf reserved4 #define newovl reserved4 #define irqtmp1 reserved4 #define irqtmp2 reserved4 #define reserved5 $79 #define target reserved5 #define save1 $74 #define rv4 save1 #define rv7 save1 #define tagid save1 #define maxsize save1 #define pbyte save1 #define pbit save1 #define save2 $73 #define cur save2 #define rv6 save2 #define osize save2 #define zovl save2 #define oldovl save2 #define newvma save2 #define save3 $72 #define rv1 save3 #define ea64 save3 #define buf3 save3 #define genwi save3 #define newmap save3 #define oldmask save3 #define save4 $71 #define irq_stat save4 .text .align 4 .type __rv_pattern, @object .size __rv_pattern, 16 __rv_pattern: .word 0x00010203, 0x10111213, 0x80808080, 0x80808080 .type __cg_pattern, @object .size __cg_pattern, 16 __cg_pattern: .word 0x04050607, 0x80808080, 0x80808080, 0x80808080 .type __ovly_current, @object .size __ovly_current, 16 __ovly_current: .space 16 /* * __ovly_return - stub for returning from overlay functions. * * On entry the four slots of $lr are: * __ovly_return, prev ovl index, caller return addr, undefined. * * Load the previous overlay and jump to the caller return address. * Updates __ovly_current. */ .align 4 .global __ovly_return .type __ovly_return, @function __ovly_return: ila tab1, _ovly_table - 16 # 0,2 0 shlqbyi ovl, $lr, 4 # 1,4 0 #nop shlqbyi target, $lr, 8 # 1,4 1 #nop; lnop #nop; lnop shli off1, ovl, 4 # 0,4 4 #lnop #nop hbr ovly_ret9, target # 1,15 5 #nop; lnop #nop; lnop #nop lqx vma, tab1, off1 # 1,6 8 #ifdef OVLY_IRQ_SAVE nop stqd save4, -64($sp) # 1,6 9 #else #nop; lnop #endif #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop rotqbyi size1, vma, 4 # 1,4 14 #nop stqd save3, -48($sp) # 1,6 15 #nop stqd save2, -32($sp) # 1,6 16 #nop stqd save1, -16($sp) # 1,6 17 andi present1, size1, 1 # 0,2 18 stqr ovl, __ovly_current # 1,6 18 #nop; lnop #nop brz present1, do_load # 1,4 20 ovly_ret9: #nop bi target # 1,4 21 /* * __ovly_load - copy an overlay partion to local store. * * On entry $75 points to a word consisting of the overlay index in * the top 14 bits, and the target address in the bottom 18 bits. * * Sets up $lr to return via __ovly_return. If $lr is already set * to return via __ovly_return, don't change it. In that case we * have a tail call from one overlay function to another. * Updates __ovly_current. */ .align 3 .global __ovly_load .type __ovly_load, @function __ovly_load: #if OVL_STUB_SIZE == 8 ######## #nop lqd target, 0(parm) # 1,6 -11 #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop rotqby target, target, parm # 1,4 -5 ila tab2, _ovly_table - 16 # 0,2 -4 stqd save3, -48($sp) # 1,6 -4 #nop stqd save2, -32($sp) # 1,6 -3 #nop stqd save1, -16($sp) # 1,6 -2 rotmi ovl, target, -18 # 0,4 -1 hbr ovly_load9, target # 1,15 -1 ila rv1, __ovly_return # 0,2 0 #lnop #nop; lnop #nop lqr cur, __ovly_current # 1,6 2 shli off2, ovl, 4 # 0,4 3 stqr ovl, __ovly_current # 1,6 3 ceq rv2, $lr, rv1 # 0,2 4 lqr rv3, __rv_pattern # 1,6 4 #nop; lnop #nop; lnop #nop lqx vma, tab2, off2 # 1,6 7 ######## #else /* OVL_STUB_SIZE == 16 */ ######## ila tab2, _ovly_table - 16 # 0,2 0 stqd save3, -48($sp) # 1,6 0 ila rv1, __ovly_return # 0,2 1 stqd save2, -32($sp) # 1,6 1 shli off2, ovl, 4 # 0,4 2 lqr cur, __ovly_current # 1,6 2 nop stqr ovl, __ovly_current # 1,6 3 ceq rv2, $lr, rv1 # 0,2 4 lqr rv3, __rv_pattern # 1,6 4 #nop hbr ovly_load9, target # 1,15 5 #nop lqx vma, tab2, off2 # 1,6 6 #nop stqd save1, -16($sp) # 1,6 7 ######## #endif #nop; lnop #nop; lnop #nop shufb rv4, rv1, cur, rv3 # 1,4 10 #nop fsmb rv5, rv2 # 1,4 11 #nop rotqmbyi rv6, $lr, -8 # 1,4 12 #nop rotqbyi size2, vma, 4 # 1,4 13 #nop lqd save3, -48($sp) # 1,6 14 #nop; lnop or rv7, rv4, rv6 # 0,2 16 lqd save2, -32($sp) # 1,6 16 andi present2, size2, 1 # 0,2 17 #ifdef OVLY_IRQ_SAVE stqd save4, -64($sp) # 1,6 17 #else lnop # 1,0 17 #endif selb $lr, rv7, $lr, rv5 # 0,2 18 lqd save1, -16($sp) # 1,6 18 #nop brz present2, do_load # 1,4 19 ovly_load9: #nop bi target # 1,4 20 /* If we get here, we are about to load a new overlay. * "vma" contains the relevant entry from _ovly_table[]. * extern struct { * u32 vma; * u32 size; * u32 file_offset; * u32 buf; * } _ovly_table[]; */ .align 3 .global __ovly_load_event .type __ovly_load_event, @function __ovly_load_event: do_load: #ifdef OVLY_IRQ_SAVE ila irqtmp1, do_load10 # 0,2 -5 rotqbyi sz, vma, 8 # 1,4 -5 #nop rdch irq_stat, $SPU_RdMachStat # 1,6 -4 #nop bid irqtmp1 # 1,4 -3 do_load10: nop #else #nop rotqbyi sz, vma, 8 # 1,4 0 #endif rotqbyi osize, vma, 4 # 1,4 1 #nop lqa ea64, _EAR_ # 1,6 2 #nop lqr cgshuf, __cg_pattern # 1,6 3 /* We could predict the branch at the end of this loop by adding a few instructions, and there are plenty of free cycles to do so without impacting loop execution time. However, it doesn't make a great deal of sense since we need to wait for the dma to complete anyway. */ __ovly_xfer_loop: #nop rotqmbyi off64, sz, -4 # 1,4 4 #nop; lnop #nop; lnop #nop; lnop cg cgbits, ea64, off64 # 0,2 8 #lnop #nop; lnop #nop shufb add64, cgbits, cgbits, cgshuf # 1,4 10 #nop; lnop #nop; lnop #nop; lnop addx add64, ea64, off64 # 0,2 14 #lnop ila maxsize, MFC_MAX_DMA_SIZE # 0,2 15 lnop ori ea64, add64, 0 # 0,2 16 rotqbyi ealo, add64, 4 # 1,4 16 cgt cmp, osize, maxsize # 0,2 17 wrch $MFC_LSA, vma # 1,6 17 #nop; lnop selb sz, osize, maxsize, cmp # 0,2 19 wrch $MFC_EAH, ea64 # 1,6 19 ila tagid, MFC_TAG_ID # 0,2 20 wrch $MFC_EAL, ealo # 1,6 20 ila cmd, MFC_GET_CMD # 0,2 21 wrch $MFC_Size, sz # 1,6 21 sf osize, sz, osize # 0,2 22 wrch $MFC_TagId, tagid # 1,6 22 a vma, vma, sz # 0,2 23 wrch $MFC_Cmd, cmd # 1,6 23 #nop brnz osize, __ovly_xfer_loop # 1,4 24 /* Now update our data structions while waiting for DMA to complete. Low bit of .size needs to be cleared on the _ovly_table entry corresponding to the evicted overlay, and set on the entry for the newly loaded overlay. Note that no overlay may in fact be evicted as _ovly_buf_table[] starts with all zeros. Don't zap .size entry for zero index! Also of course update the _ovly_buf_table entry. */ #nop lqr newovl, __ovly_current # 1,6 25 #nop; lnop #nop; lnop #nop; lnop #nop; lnop #nop; lnop shli off3, newovl, 4 # 0,4 31 #lnop ila tab3, _ovly_table - 16 # 0,2 32 #lnop #nop fsmbi pbyte, 0x100 # 1,4 33 #nop; lnop #nop lqx vma, tab3, off3 # 1,6 35 #nop; lnop andi pbit, pbyte, 1 # 0,2 37 lnop #nop; lnop #nop; lnop #nop; lnop or newvma, vma, pbit # 0,2 41 rotqbyi buf3, vma, 12 # 1,4 41 #nop; lnop #nop stqx newvma, tab3, off3 # 1,6 43 #nop; lnop shli off4, buf3, 2 # 1,4 45 #lnop ila tab4, _ovly_buf_table - 4 # 0,2 46 #lnop #nop; lnop #nop; lnop #nop lqx map, tab4, off4 # 1,6 49 #nop cwx genwi, tab4, off4 # 1,4 50 a addr4, tab4, off4 # 0,2 51 #lnop #nop; lnop #nop; lnop #nop; lnop #nop rotqby oldovl, map, addr4 # 1,4 55 #nop shufb newmap, newovl, map, genwi # 0,4 56 #if MFC_TAG_ID < 16 ila newmask, 1 << MFC_TAG_ID # 0,2 57 #else ilhu newmask, 1 << (MFC_TAG_ID - 16) # 0,2 57 #endif #lnop #nop; lnop #nop; lnop stqd newmap, 0(addr4) # 1,6 60 /* Save app's tagmask, wait for DMA complete, restore mask. */ ila tagstat, MFC_TAG_UPDATE_ALL # 0,2 61 rdch oldmask, $MFC_RdTagMask # 1,6 61 #nop wrch $MFC_WrTagMask, newmask # 1,6 62 #nop wrch $MFC_WrTagUpdate, tagstat # 1,6 63 #nop rdch tagstat, $MFC_RdTagStat # 1,6 64 #nop sync # 1,4 65 /* Any hint prior to the sync is lost. A hint here allows the branch to complete 15 cycles after the hint. With no hint the branch will take 18 or 19 cycles. */ ila tab5, _ovly_table - 16 # 0,2 66 hbr do_load99, target # 1,15 66 shli off5, oldovl, 4 # 0,4 67 wrch $MFC_WrTagMask, oldmask # 1,6 67 ceqi zovl, oldovl, 0 # 0,2 68 #lnop #nop; lnop #nop fsm zovl, zovl # 1,4 70 #nop lqx oldvma, tab5, off5 # 1,6 71 #nop lqd save3, -48($sp) # 1,6 72 #nop; lnop andc pbit, pbit, zovl # 0,2 74 lqd save2, -32($sp) # 1,6 74 #ifdef OVLY_IRQ_SAVE ila irqtmp2, do_load90 # 0,2 75 #lnop andi irq_stat, irq_stat, 1 # 0,2 76 #lnop #else #nop; lnop #nop; lnop #endif andc oldvma, oldvma, pbit # 0,2 77 lqd save1, -16($sp) # 1,6 77 nop # 0,0 78 #lnop #nop stqx oldvma, tab5, off5 # 1,6 79 #nop #ifdef OVLY_IRQ_SAVE binze irq_stat, irqtmp2 # 1,4 80 do_load90: #nop lqd save4, -64($sp) # 1,6 84 #else #nop; lnop #endif .global _ovly_debug_event .type _ovly_debug_event, @function _ovly_debug_event: nop /* Branch to target address. */ do_load99: bi target # 1,4 81/85 .size __ovly_load, . - __ovly_load

stsp/binutils-ia16

1,703

ld/testsuite/ld-riscv-elf/variant_cc-2.s

.text .variant_cc cc_global_default_def .variant_cc cc_global_default_undef .variant_cc cc_global_default_ifunc .variant_cc cc_global_hidden_def .variant_cc cc_global_hidden_ifunc .variant_cc cc_local2 .variant_cc cc_local2_ifunc .global cc_global_default_def .global cc_global_default_undef .global cc_global_default_ifunc .global cc_global_hidden_def .global cc_global_hidden_ifunc .global nocc_global_default_def .global nocc_global_default_undef .global nocc_global_default_ifunc .global nocc_global_hidden_def .global nocc_global_hidden_ifunc .hidden cc_global_hidden_def .hidden cc_global_hidden_ifunc .hidden nocc_global_hidden_def .hidden nocc_global_hidden_ifunc # .type cc_global_default_ifunc, %gnu_indirect_function # .type cc_global_hidden_ifunc, %gnu_indirect_function .type cc_local2_ifunc, %gnu_indirect_function # .type nocc_global_default_ifunc, %gnu_indirect_function # .type nocc_global_hidden_ifunc, %gnu_indirect_function .type nocc_local2_ifunc, %gnu_indirect_function # cc_global_default_def: # cc_global_default_undef: # cc_global_hidden_def: # cc_global_default_ifunc: # cc_global_hidden_ifunc: cc_local2: cc_local2_ifunc: # nocc_global_default_def: # nocc_global_default_undef: # nocc_global_hidden_def: # nocc_global_default_ifunc: # nocc_global_hidden_ifunc: nocc_local2: nocc_local2_ifunc: call cc_global_default_def call cc_global_default_undef call cc_global_hidden_def call cc_global_default_ifunc call cc_global_hidden_ifunc call cc_local2 call cc_local2_ifunc call nocc_global_default_def call nocc_global_default_undef call nocc_global_hidden_def call nocc_global_default_ifunc call nocc_global_hidden_ifunc call nocc_local2 call nocc_local2_ifunc

stsp/binutils-ia16

1,667

ld/testsuite/ld-riscv-elf/variant_cc-1.s

.text .variant_cc cc_global_default_def .variant_cc cc_global_default_undef .variant_cc cc_global_default_ifunc .variant_cc cc_global_hidden_def .variant_cc cc_global_hidden_ifunc .variant_cc cc_local .variant_cc cc_local_ifunc .global cc_global_default_def .global cc_global_default_undef .global cc_global_default_ifunc .global cc_global_hidden_def .global cc_global_hidden_ifunc .global nocc_global_default_def .global nocc_global_default_undef .global nocc_global_default_ifunc .global nocc_global_hidden_def .global nocc_global_hidden_ifunc .hidden cc_global_hidden_def .hidden cc_global_hidden_ifunc .hidden nocc_global_hidden_def .hidden nocc_global_hidden_ifunc .type cc_global_default_ifunc, %gnu_indirect_function .type cc_global_hidden_ifunc, %gnu_indirect_function .type cc_local_ifunc, %gnu_indirect_function .type nocc_global_default_ifunc, %gnu_indirect_function .type nocc_global_hidden_ifunc, %gnu_indirect_function .type nocc_local_ifunc, %gnu_indirect_function cc_global_default_def: # cc_global_default_undef: cc_global_hidden_def: cc_global_default_ifunc: cc_global_hidden_ifunc: cc_local: cc_local_ifunc: nocc_global_default_def: # nocc_global_default_undef: nocc_global_hidden_def: nocc_global_default_ifunc: nocc_global_hidden_ifunc: nocc_local: nocc_local_ifunc: call cc_global_default_def call cc_global_default_undef call cc_global_hidden_def call cc_global_default_ifunc call cc_global_hidden_ifunc call cc_local call cc_local_ifunc call nocc_global_default_def call nocc_global_default_undef call nocc_global_hidden_def call nocc_global_default_ifunc call nocc_global_hidden_ifunc call nocc_local call nocc_local_ifunc