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Features
• Compatible with MCS®-51 Products
(cid:129) 4K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 10,000 Write/Erase Cycles
(cid:129) 4.0V to 5.5V Operating Range
(cid:129) Fully Static Operation: 0 Hz to 33 MHz
(cid:129) Three-level Program Memory Lock
(cid:129) 128 x 8-bit Internal RAM
(cid:129) 32 Programmable I/O Lines
8-bit
(cid:129) Two 16-bit Timer/Counters
(cid:129) Six Interrupt Sources Microcontroller
(cid:129) Full Duplex UART Serial Channel
(cid:129) Low-power Idle and Power-down Modes with 4K Bytes
(cid:129) Interrupt Recovery from Power-down Mode
(cid:129) Watchdog Timer In-System
(cid:129) Dual Data Pointer
(cid:129) Power-off Flag Programmable
(cid:129) Fast Programming Time
Flash
(cid:129) Flexible ISP Programming (Byte and Page Mode)
(cid:129) Green (Pb/Halide-free) Packaging Option
AT89S51
1. Description
The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of In-System Programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the indus-
try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-
grammer. By combining a versatile 8-bit CPU with In-System Programmable Flash on
a monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
2487D–MICRO–6/08
2. Pin Configurations
| 2.1 40-lead PDIP | 2.3 | 44-lead PLCC | |
| ---------------- | --- | ------------ | --- |
)0DA( 0.0P )1DA( 1.0P )2DA( 2.0P )3DA( 3.0P
| P1.0 1 | 40 VCC | | |
| ------- | ------------- | --------------------------- | --- |
| P1.1 2 | 39 P0.0 (AD0) | 4.1P 3.1P 2.1P 1.1P 0.1P | CCV |
CN
| P1.2 3 | 38 P0.1 (AD1) | | |
| -------------- | ------------- | -------------- | ---------------- |
| P1.3 4 | 37 P0.2 (AD2) | 6 5 4 3 2 | 1 44 34 24 14 04 |
| P1.4 5 | 36 P0.3 (AD3) | (MOSI) P1.5 7 | 39 P0.4 (AD4) |
| | | (MISO) P1.6 8 | 38 P0.5 (AD5) |
| (MOSI) P1.5 6 | 35 P0.4 (AD4) | | |
| | | (SCK) P1.7 9 | 37 P0.6 (AD6) |
| (MISO) P1.6 7 | 34 P0.5 (AD5) | | |
| | | RST 10 | 36 P0.7 (AD7) |
| (SCK) P1.7 8 | 33 P0.6 (AD6) | (RXD) P3.0 11 | 35 EA/VPP |
| RST 9 | 32 P0.7 (AD7) | | |
| | | NC 12 | 34 NC |
| (RXD) P3.0 10 | 31 EA/VPP | (TXD) P3.1 13 | 33 ALE/PROG |
| (TXD) P3.1 11 | 30 ALE/PROG | (INT0) P3.2 14 | 32 PSEN |
| (INT0) P3.2 12 | 29 PSEN | (INT1) P3.3 15 | 31 P2.7 (A15) |
| (INT1) P3.3 13 | 28 P2.7 (A15) | (T0) P3.4 16 | 30 P2.6 (A14) |
| (T0) P3.4 14 | 27 P2.6 (A14) | (T1) P3.5 17 | 29 P2.5 (A13) |
81 91 02 12 22 32 42 52 62 72 82
| (T1) P3.5 15 | 26 P2.5 (A13) | | |
| ------------ | ------------- | --- | --- |
6.3P )RW( 7.3P )DR( 2LATX 1LATX DNG CN 0.2P )8A( 1.2P )9A( 2.2P )01A( 3.2P )11A( 4.2P )21A(
| (WR) P3.6 16 | 25 P2.4 (A12) | | |
| ------------ | ------------- | --- | --- |
| (RD) P3.7 17 | 24 P2.3 (A11) | | |
| XTAL2 18 | 23 P2.2 (A10) | | |
| XTAL1 19 | 22 P2.1 (A9) | | |
| GND 20 | 21 P2.0 (A8) | | |
2.2 44-lead TQFP
)0DA( 0.0P )1DA( 1.0P )2DA( 2.0P )3DA( 3.0P
| 4.1P 3.1P 2.1P 1.1P 0.1P | CCV | | |
| -------------------------- | --- | --- | --- |
CN
| 44 34 24 14 04 | 93 83 73 63 53 43 | | |
| ----------------------------------- | -------------------------------------------------------- | --- | --- |
| (MOSI) P1.5 1 | 33 P0.4 (AD4) | | |
| (MISO) P1.6 2 | 32 P0.5 (AD5) | | |
| (SCK) P1.7 3 | 31 P0.6 (AD6) | | |
| RST 4 | 30 P0.7 (AD7) | | |
| (RXD) P3.0 5 | 29 EA/VPP | | |
| NC 6 | 28 NC | | |
| (TXD) P3.1 7 | 27 ALE/PROG | | |
| (INT0) P3.2 8 | 26 PSEN | | |
| (INT1) P3.3 9 | 25 P2.7 (A15) | | |
| (T0) P3.4 10 | 24 P2.6 (A14) | | |
| (T1) P3.5 11 | 23 P2.5 (A13) | | |
| 21 31 41 51 61 | 71 81 91 02 12 22 | | |
| 6.3P )RW( 7.3P )DR( 2LATX 1LATX DNG | DNG 0.2P )8A( 1.2P )9A( 2.2P )01A( 3.2P )11A( 4.2P )21A( | | |
AT89S51
 2
2487D–MICRO–6/08
AT89S51
3. Block Diagram
| | | P0.0 - P0.7 | P2.0 - P2.7 | |
| --- | --- | ----------- | ----------- | --- |
V CC
| | | PORT 0 DRIVERS | PORT 2 DRIVERS | |
| --- | --- | -------------- | -------------- | --- |
GND
RAMADDR.
PORT 0 PORT 2
| | REGISTER | RAM LATCH | LATCH FLASH | |
| --- | -------- | --------- | ----------- | --- |
PROGRAM
| B | | | S T AC K | |
| --------- | --- | --- | ----------- | ------------- |
| REGI STER | ACC | | P O IN TE R | A D D R E S S |
R E G I S T E R
BUFFER
TMP2 TMP1
PC
| | | ALU | | INCREMENTER |
| --- | --- | --- | --- | ----------- |
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
| | | PSW | | COUNTER |
| --- | --- | --- | --- | ------- |
PSEN
TIMING
ALE/PROG INSTRUCTION
| AND | REGISTER | | | DUAL DPTR |
| --- | -------- | --- | --- | --------- |
EA / V CONTROL
PP
RST
| | WATCH | PORT 3 | PORT 1 ISP | PROGRAM |
| --- | ----- | ------ | ---------- | ------- |
| | DOG | LATCH | | |
| | | | LATCH PORT | LOGIC |
OSC
| | | PORT 3 DRIVERS | PORT 1 DRIVERS | |
| --- | --- | -------------- | -------------- | --- |
P3.0 - P3.7
P1.0 - P1.7
 3
2487D–MICRO–6/08
4. Pin Description
4.1 VCC
Supply voltage.
4.2 GND
Ground.
4.3 Port 0
Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-
ing program verification. External pull-ups are required during program verification.
4.4 Port 1
Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (I ) because of the internal pull-ups.
IL
Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin Alternate Functions
P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)
4.5 Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-
nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low
will source current (I ) because of the internal pull-ups.
IL
Port 2 emits the high-order address byte during fetches from external program memory and dur-
ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash program-
ming and verification.
4.6 Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-
AT89S51
4
2487D–MICRO–6/08
AT89S51
nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (I ) because of the pull-ups.
IL
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S51, as shown in the fol-
lowing table.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)
4.7 RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets
the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-
RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of
bit DISRTO, the RESET HIGH out feature is enabled.
4.8 ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-
ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
4.9 PSEN
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89S51 is executing code from external program memory, PSEN is activated twice
each machine cycle, except that two PSEN activations are skipped during each access to exter-
nal data memory.
4.10 EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset.
5
2487D–MICRO–6/08
EA should be strapped to V for internal program executions.
CC
This pin also receives the 12-volt programming enable voltage (V ) during Flash programming.
PP
4.11 XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
4.12 XTAL2
Output from the inverting oscillator amplifier
5. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
Table 5-1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-
mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
AT89S51
6
2487D–MICRO–6/08
AT89S51
Table 5-1. AT89S51 SFR Map and Reset Values
0F8H 0FFH
B
0F0H 0F7H
00000000
0E8H 0EFH
ACC
0E0H 0E7H
00000000
0D8H 0DFH
PSW
0D0H 0D7H
00000000
0C8H 0CFH
0C0H 0C7H
IP
0B8H 0BFH
XX000000
P3
0B0H 0B7H
11111111
IE
0A8H 0AFH
0X000000
P2 AUXR1 WDTRST
0A0H 0A7H
11111111 XXXXXXX0 XXXXXXXX
SCON SBUF
98H 9FH
00000000 XXXXXXXX
P1
90H 97H
11111111
TCON TMOD TL0 TL1 TH0 TH1 AUXR
88H 8FH
00000000 00000000 00000000 00000000 00000000 00000000 XXX00XX0
P0 SP DP0L DP0H DP1L DP1H PCON
80H 87H
11111111 00000111 00000000 00000000 00000000 00000000 0XXX0000
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-
tures. In that case, the reset or inactive values of the new bits will always be 0.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five
interrupt sources in the IP register.
7
2487D–MICRO–6/08
| Table 5-2. | AUXR: Auxiliary Register | | | | |
| ---------- | ------------------------ | --- | --- | ----------------------- | --- |
| AUXR | Address = 8EH | | | Reset Value = XXX00XX0B | |
 Not Bit Addressable
| | – – | – WDIDLE | DISRTO | – – | DISALE |
| ------ | ----------------------------- | -------- | ------ | --- | ------ |
| Bit | 7 6 | 5 4 | 3 | 2 1 | 0 |
| – | Reserved for future expansion | | | | |
| DISALE | Disable/Enable ALE | | | | |
DISALE
Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
| DISRTO | Disable/Enable Reset-out | | | | |
| ------ | ------------------------ | --- | --- | --- | --- |
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
| WDIDLE | Disable/Enable WDT in IDLE mode | | | | |
| ------ | ------------------------------- | --- | --- | --- | --- |
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-
83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should ALWAYS initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF
is set to “1” during power up. It can be set and rest under software control and is not affected by
reset.
AT89S51
 8
2487D–MICRO–6/08
AT89S51
Table 5-3. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
– – – – – – – DPS
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
6. Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
6.1 Program Memory
If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89S51, if EA is connected to V , program fetches to addresses 0000H through FFFH
CC
are directed to internal memory and fetches to addresses 1000H through FFFFH are directed to
external memory.
6.2 Data Memory
The AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.
7. Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-
flows, it will drive an output RESET HIGH pulse at the RST pin.
7.1 Using the WDT
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must reset the WDT at least
9
2487D–MICRO–6/08
every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When
WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura-
tion is 98xTOSC, where TOSC = 1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time required to
prevent a WDT reset.
7.2 WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-
down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt, which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for
the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to
reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)
as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode, the
user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter
IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
8. UART
The UART in the AT89S51 operates the same way as the UART in the AT89C51. For further
information on the UART operation, please click on the document link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
9. Timer 0 and 1
Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the
AT89C51. For further information on the timers’ operation, please click on the document link
below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
AT89S51
10
2487D–MICRO–6/08
AT89S51
10. Interrupts
The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two
timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in
Figure 10-1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.
Note that Table 10-1 shows that bit positions IE.6 and IE.5 are unimplemented. User software
should not write 1s to these bit positions, since they may be used in future AT89 products.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers
overflow. The values are then polled by the circuitry in the next cycle.
| Table 10-1. Interrupt Enable (IE) Register | | | |
| ------------------------------------------- | --- | --- | --- |
 (MSB) (LSB)
| EA | – – | ES ET1 EX1 | ET0 EX0 |
| --- | --- | ---------- | ------- |
 Enable Bit = 1 enables the interrupt.
 Enable Bit = 0 disables the interrupt.
| Symbol | Position | Function | |
| ------ | -------- | -------- | --- |
Disables all interrupts. If EA = 0, no interrupt is
acknowledged. If EA = 1, each interrupt source is
| EA | IE.7 | | |
| --- | ---- | --- | --- |
individually enabled or disabled by setting or clearing its
enable bit.
| – | IE.6 | Reserved | |
| --- | ---- | -------------------------------- | --- |
| – | IE.5 | Reserved | |
| ES | IE.4 | Serial Port interrupt enable bit | |
| ET1 | IE.3 | Timer 1 interrupt enable bit | |
| EX1 | IE.2 | External interrupt 1 enable bit | |
| ET0 | IE.1 | Timer 0 interrupt enable bit | |
| EX0 | IE.0 | External interrupt 0 enable bit | |
User software should never write 1s to reserved bits, because they may be used in future AT89
products.
 11
2487D–MICRO–6/08
Figure 10-1. Interrupt Sources
0
INT0 IE0
1
TF0
0
INT1 IE1
1
TF1
TI
RI
11. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in Figure 11-1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven, as shown in Figure 11-2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal clock-
ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
Figure 11-1. Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
AT89S51
12
2487D–MICRO–6/08
AT89S51
| Figure 11-2. | External Clock Drive Configuration | | | | |
| ------------ | ---------------------------------- | --- | ----- | --- | --- |
| | | NC | XTAL2 | | |
EXTERNAL
| | | OSCILLATOR | XTAL1 | | |
| --- | --- | ---------- | ----- | --- | --- |
SIGNAL
GND
12. Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The
mode is invoked by software. The content of the on-chip RAM and all the special function regis-
ters remain unchanged during this mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-
gram execution from where it left off, up to two machine cycles before the internal reset
algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but
access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a
port pin when idle mode is terminated by a reset, the instruction following the one that invokes
idle mode should not write to a port pin or to external memory.
13. Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down mode can be initiated
either by a hardware reset or by activation of an enabled external interrupt (INT0 or INT1). Reset
redefines the SFRs but does not change the on-chip RAM. The reset should not be activated
before V is restored to its normal operating level and must be held active long enough to allow
CC
the oscillator to restart and stabilize.
 Table 13-1.
Status of External Pins During Idle and Power-down Modes
| Mode | Program Memory | ALE PSEN | PORT0 PORT1 | PORT2 | PORT3 |
| ---------- | -------------- | -------- | ----------- | ------- | ----- |
| Idle | Internal | 1 1 | Data Data | Data | Data |
| Idle | External | 1 1 | Float Data | Address | Data |
| Power-down | Internal | 0 0 | Data Data | Data | Data |
| Power-down | External | 0 0 | Float Data | Data | Data |
 13
2487D–MICRO–6/08
14. Program Memory Lock Bits
The AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed (P)
to obtain the additional features listed in Table 14-1.
Table 14-1. Lock Bit Protection Modes
Program Lock Bits
LB1 LB2 LB3 Protection Type
1 U U U No program lock features
MOVC instructions executed from external program memory
are disabled from fetching code bytes from internal memory,
2 P U U
EA is sampled and latched on reset, and further programming
of the Flash memory is disabled
3 P P U Same as mode 2, but verify is also disabled
4 P P P Same as mode 3, but external execution is also disabled
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset.
If the device is powered up without a reset, the latch initializes to a random value and holds that
value until reset is activated. The latched value of EA must agree with the current logic level at
that pin in order for the device to function properly.
15. Programming the Flash – Parallel Mode
The AT89S51 is shipped with the on-chip Flash memory array ready to be programmed. The
programming interface needs a high-voltage (12-volt) program enable signal and is compatible
with conventional third-party Flash or EPROM programmers.
The AT89S51 code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89S51, the address, data, and control
signals should be set up according to the Flash Programming Modes table (Table 17-1) and Fig-
ure 17-1 and Figure 17-2. To program the AT89S51, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V to 12V.
PP
5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-
write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1
through 5, changing the address and data for the entire array or until the end of the
object file is reached.
Data Polling: The AT89S51 features Data Polling to indicate the end of a byte write cycle. Dur-
ing a write cycle, an attempted read of the last byte written will result in the complement of the
written data on P0.7. Once the write cycle has been completed, true data is valid on all outputs,
and the next cycle may begin. Data Polling may begin any time after a write cycle has been
initiated.
Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output
signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is
pulled high again when programming is done to indicate READY.
AT89S51
14
2487D–MICRO–6/08
AT89S51
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code
data can be read back via the address and data lines for verification. The status of the individ-
ual lock bits can be verified directly by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor-
mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to
a logic low. The values returned are as follows.
(000H) = 1EH indicates manufactured by Atmel
(100H) = 51H indicates AT89S51
(200H) = 06H
Chip Erase: In the parallel programming mode, a chip erase operation is initiated by using the
proper combination of control signals and by pulsing ALE/PROG low for a duration of 200 ns -
500 ns.
In the serial programming mode, a chip erase operation is initiated by issuing the Chip Erase
instruction. In this mode, chip erase is self-timed and takes about 500 ms.
During chip erase, a serial read from any address location will return 00H at the data output.
16. Programming the Flash – Serial Mode
The Code memory array can be programmed using the serial ISP interface while RST is pulled
to V . The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RST is
CC
set high, the Programming Enable instruction needs to be executed first before other operations
can be executed. Before a reprogramming sequence can occur, a Chip Erase operation is
required.
The Chip Erase operation turns the content of every memory location in the Code array into
FFH.
Either an external system clock can be supplied at pin XTAL1 or a crystal needs to be connected
across pins XTAL1 and XTAL2. The maximum serial clock (SCK) frequency should be less than
1/16 of the crystal frequency. With a 33 MHz oscillator clock, the maximum SCK frequency is
2 MHz.
16.1 Serial Programming Algorithm
To program and verify the AT89S51 in the serial programming mode, the following sequence is
recommended:
1. Power-up sequence:
a. Apply power between VCC and GND pins.
b. Set RST pin to “H”.
If a crystal is not connected across pins XTAL1 and XTAL2, apply a 3 MHz to 33 MHz clock to
XTAL1 pin and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Programming Enable serial instruction to pin
MOSI/P1.5. The frequency of the shift clock supplied at pin SCK/P1.7 needs to be less
than the CPU clock at XTAL1 divided by 16.
3. The Code array is programmed one byte at a time in either the Byte or Page mode. The
write cycle is self-timed and typically takes less than 0.5 ms at 5V.
4. Any memory location can be verified by using the Read instruction that returns the con-
tent at the selected address at serial output MISO/P1.6.
15
2487D–MICRO–6/08
5. At the end of a programming session, RST can be set low to commence normal device
operation.
Power-off sequence (if needed):
1. Set XTAL1 to “L” (if a crystal is not used).
2. Set RST to “L”.
3. Turn V power off.
CC
Data Polling: The Data Polling feature is also available in the serial mode. In this mode, during
a write cycle an attempted read of the last byte written will result in the complement of the MSB
of the serial output byte on MISO.
16.2 Serial Programming Instruction Set
The Instruction Set for Serial Programming follows a 4-byte protocol and is shown in the
”Serial Programming Instruction Set” on page 20.
17. Programming Interface – Parallel Mode
Every code byte in the Flash array can be programmed by using the appropriate combination of
control signals. The write operation cycle is self-timed and once initiated, will automatically time
itself to completion.
Most major worldwide programming vendors offer worldwide support for the Atmel AT89 micro-
controller series. Please contact your local programming vendor for the appropriate software
revision.
| Table 17-1. | Flash Programming Modes | | | | | | |
| ----------- | ----------------------- | --- | --- | --- | --- | --- | --- |
P2.3-0 P1.7-0
| | | ALE/ | EA/ | | | P0.7-0 | |
| ---- | ----- | --------- | ------ | --------- | --------- | ------ | ------- |
| Mode | V RST | PSEN PROG | V P2.6 | P2.7 P3.3 | P3.6 P3.7 | Data | Address |
| | CC | | PP | | | | |
(2)
| Write Code Data | 5V H | L | 12V L | H H | H H | D IN | A11-8 A7-0 |
| --------------- | ---- | --- | ----- | --- | --- | ---- | ---------- |
| Read Code Data | 5V H | L H | H L | L L | H H | D | A11-8 A7-0 |
OUT
(3)
| Write Lock Bit 1 | 5V H | L | 12V H | H H | H H | X | X X |
| ---------------- | ---- | --- | ----- | --- | --- | --- | --- |
(3)
| Write Lock Bit 2 | 5V H | L | 12V H | H H | L L | X | X X |
| ---------------- | ---- | --- | ----- | --- | --- | --- | --- |
(3)
| Write Lock Bit 3 | 5V H | L | 12V H | L H | H L | X | X X |
| ---------------- | ---- | --- | ----- | --- | --- | --- | --- |
P0.2,
Read Lock Bits
| | 5V H | L H | H H | H L | H L | P0.3, | X X |
| --- | ---- | --- | --- | --- | --- | ----- | --- |
1, 2, 3
P0.4
(1)
| Chip Erase | 5V H | L | 12V H | L H | L L | X | X X |
| ------------------------------------------------------------ | ---- | --- | ----- | --- | --- | --- | -------- |
| Read Atmel ID | 5V H | L H | H L | L L | L L | 1EH | 0000 00H |
| Read Device ID | 5V H | L H | H L | L L | L L | 51H | 0001 00H |
| Read Device ID | 5V H | L H | H L | L L | L L | 06H | 0010 00H |
| Notes: 1. Each PROG pulse is 200 ns - 500 ns for Chip Erase. | | | | | | | |
| 2. Each PROG pulse is 200 ns - 500 ns for Write Code Data. | | | | | | | |
| 3. Each PROG pulse is 200 ns - 500 ns for Write Lock Bits. | | | | | | | |
| 4. RDY/BSY signal is output on P3.0 during programming. | | | | | | | |
| 5. X = don’t care. | | | | | | | |
AT89S51
 16
2487D–MICRO–6/08
AT89S51
Figure 17-1. Programming the Flash Memory (Parallel Mode)
VCC
AT89S51
| A0-A7 | | V | |
| ----- | --------- | --- | --- |
| ADDR. | P1.0-P1.7 | CC | |
0000H/FFFH
PGM
| A8-A11 | P2.0 - P2.3 | P0 | DATA |
| ------ | ----------- | --- | ---- |
P2.6
P2.7
| SEE FLASH | | ALE | PROG |
| ----------- | ---- | --- | ---- |
| PROGRAMMING | P3.3 | | |
| MODES TABLE | P3.6 | | |
P3.7
| | XTAL2 | EA | V IH /V PP |
| --- | ----- | --- | ---------- |
3-33 MHz
RDY/
P3.0 BSY
| | XTAL1 | RST | V |
| --- | ----- | --- | --- |
IH
GND PSEN
Figure 17-2. Verifying the Flash Memory (Parallel Mode)
V
CC
AT89S51
A0-A7
| ADDR. | P1.0-P1.7 | V CC | |
| ----- | --------- | ---- | -------- |
| | | | PGM DATA |
0000H/FFFH
| A8-A11 | P2.0 - P2.3 | P0 | (USE 10K |
| ------ | ----------- | --- | -------- |
PULLUPS)
P2.6
P2.7
| SEE FLASH | | ALE | |
| ----------- | ---- | --- | --- |
| PROGRAMMING | P3.3 | | |
| MODES TABLE | P3.6 | | |
V
| | P3.7 | | IH |
| --- | ----- | --- | --- |
| | XTAL2 | EA | |
3-33 MHz
| | XTAL1 | RST | V IH |
| --- | ----- | --- | ---- |
GND PSEN
 17
2487D–MICRO–6/08
18. Flash Programming and Verification Characteristics (Parallel Mode)
| T = 20°C to 30°C, V | = 4.5 to 5.5V | | | | |
| -------------------- | -------------------------- | --- | ---- | ---- | ----- |
| A | CC | | | | |
| Symbol | Parameter | | Min | Max | Units |
| V PP | Programming Supply Voltage | | 11.5 | 12.5 | V |
| I | Programming Supply Current | | | 10 | mA |
PP
| I | V Supply Current | | | 30 | mA |
| --- | -------------------- | --- | --- | --- | --- |
| CC | CC | | | | |
| 1/t | Oscillator Frequency | | 3 | 33 | MHz |
CLCL
| t | Address Setup to PROG Low | | 48 t | | |
| ------ | ------------------------- | --- | --------- | --- | --- |
| AVGL | | | CLCL | | |
| t GHAX | Address Hold After PROG | | 48 t CLCL | | |
| t | Data Setup to PROG Low | | 48 t | | |
| DVGL | | | CLCL | | |
| t | Data Hold After PROG | | 48 t | | |
| GHDX | | | CLCL | | |
| t | P2.7 (ENABLE) High to V | | 48 t | | |
| EHSH | | PP | CLCL | | |
| t | V Setup to PROG Low | | 10 | | µs |
| SHGL | PP | | | | |
| t GHSL | V PP Hold After PROG | | 10 | | µs |
| t | PROG Width | | 0.2 | 1 | µs |
GLGH
| t | Address to Data Valid | | | 48t | |
| --- | --------------------- | --- | --- | --- | --- |
AVQV CLCL
| t | ENABLE Low to Data Valid | | | 48t | |
| --- | ------------------------ | --- | --- | --- | --- |
ELQV CLCL
| t | Data Float After ENABLE | | 0 | 48t | |
| --- | ----------------------- | --- | --- | --- | --- |
EHQZ CLCL
| t GHBL | PROG High to BUSY Low | | | 1.0 | µs |
| ------ | --------------------- | --- | --- | --- | --- |
| t | Byte Write Cycle Time | | | 50 | µs |
WC
Figure 18-1. Flash Programming and Verification Waveforms – Parallel Mode
| | | PROGRAMMING | VERIFICATION | | |
| --- | --- | ----------- | ------------ | --- | --- |
P1.0 - P1.7
| | | ADDRESS | ADDRESS | | |
| --- | --- | ------- | ------- | --- | --- |
P2.0 - P2.3
t
AVQV
| | PORT 0 | DATA IN | DATA | OUT | |
| --- | ------ | ------- | ---- | --- | --- |
t t
DVGL GHDX
| | t | | t | | |
| --- | ---- | --- | ---- | --- | --- |
| | AVGL | | GHAX | | |
ALE/PROG
| | t | | t | | |
| --- | ---- | --- | ---- | --- | --- |
| | SHGL | | GHSL | | |
t GLGH
| | | V PP | LOGIC 1 | | |
| --- | ---- | ---- | ------- | --- | --- |
| | EA/V | | LOGIC 0 | | |
PP
t
EHSH t
t ELQV EHQZ
P2.7
(ENABLE)
t
GHBL
P3.0
| | (RDY/BSY) | | BUSY | READY | |
| --- | --------- | --- | ---- | ----- | --- |
t
WC
AT89S51
 18
2487D–MICRO–6/08
AT89S51
Figure 18-2. Flash Memory Serial Downloading
V
CC
AT89S51
V
CC
INSTRUCTION
P1.5/MOSI
INPUT
DATA OUTPUT P1.6/MISO
CLOCK IN P1.7/SCK
XTAL2
3-33 MHz
XTAL1 RST V
IH
GND
19. Flash Programming and Verification Waveforms – Serial Mode
Figure 19-1. Serial Programming Waveforms
7 6 5 4 3 2 1 0
19
2487D–MICRO–6/08
20. Serial Programming Instruction Set
Instruction Format
| Instruction | | Byte 1 | Byte 2 | Byte 3 | Byte 4 | Operation |
| ----------- | --- | ------ | ------ | ------ | ------ | --------- |
xxxx xxxx
| | | | | | 0110 1001 | Enable Serial Programming |
| ------------------ | --- | ----------- | ----------- | ----------- | ------------ | -------------------------- |
| Programming Enable | | 1010 1100 | 0101 0011 | xxxx xxxx | | |
| | | | | | (Output on | while RST is high |
MISO)
Chip Erase Flash memory
| Chip Erase | | 1010 1100 | 100x xxxx | xxxx xxxx | xxxx xxxx | |
| ---------- | --- | ----------- | ----------- | ----------- | ----------- | --- |
array
| Read Program Memory | | | xxxx | | | |
| --------------------- | --- | ----------- | ------------- | ----------------------- | -------------- | ----------------------- |
| | | | 11A 01A 9A 8A | 6A 5A 3A 2A 1A | 7D | Read data from Program |
| | | 0010 0000 | | 7A 4A 0A | 6D 5D 4D 3D | 2D 1D 0D |
| (Byte Mode) | | | | | | memory in the byte mode |
| Write Program Memory | | | xxxx 11A | | | Write data to Program |
| | | 0100 0000 | 01A 9A 8A | 7A 6A 5A 4A 3A 2A 1A 0A | 7D 6D 5D 4D 3D | 2D 1D 0D |
| (Byte Mode) | | | | | | memory in the byte mode |
Write Lock Bits(1) 1010 1100 1110 00 1B 2B xxxx xxxx xxxx xxxx Write Lock bits. See Note (1).
Read back current status of
3BL 2BL 1BL
Read Lock Bits 0010 0100 xxxx xxxx xxxx xxxx xxx xx the lock bits (a programmed
lock bit reads back as a “1”)
| | | | xxxx | xxx xxx0 | | |
| --- | --- | --- | ----- | ------------- | --- | --- |
Read Signature Bytes 0010 1000 11A 01A 9A 8A 7A Signature Byte Read Signature Byte
| Read Program Memory | | | xxxx | | | Read data from Program |
| -------------------- | --- | ----------- | ------------- | ------ | ---------- | ------------------------ |
| | | | 11A 01A 9A 8A | | Byte 1... | |
| | | 0011 0000 | | Byte 0 | | memory in the Page Mode |
| (Page Mode) | | | | | Byte 255 | |
(256 bytes)
| Write Program Memory | | | | | | Write data to Program |
| --------------------- | --- | --- | --- | --- | --- | ---------------------- |
Byte 1...
0101 0000 xxxx 11A 01A 9A 8A Byte 0 memory in the Page Mode
| (Page Mode) | | | | | Byte 255 | |
| ----------- | --- | --- | --- | --- | -------- | --- |
(256 bytes)
| | | → | } | | | |
| ----- | ------------------ | ---------------------------- | --- | --- | --- | --- |
| Note: | 1. B1 = 0, B2 = 0 | Mode 1, no lock protection | | | | |
→
B1 = 0, B2 = 1 Mode 2, lock bit 1 activated Each of the lock bit modes need to be activated sequentially be-
→
| | B1 = 1, B2 = 0 | Mode 3, lock bit 2 activated | | | | |
| --- | --------------- | ------------------------------ | --- | --- | --- | --- |
fore Mode 4 can be executed.
→
| | B1 = 1, B2 = 1 | Mode 4, lock bit 3 activated | | | | |
| --- | --------------- | ----------------------------- | --- | --- | --- | --- |
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data
bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready
to be decoded.
AT89S51
 20
2487D–MICRO–6/08
AT89S51
21. Serial Programming Characteristics
| Figure 21-1. | Serial Programming Timing | | | | | |
| ------------ | ------------------------- | --- | --- | --- | --- | --- |
MOSI
| | | t | t | t | | |
| --- | --- | ---- | ---- | ---- | --- | --- |
| | | OVSH | SHOX | SLSH | | |
SCK
t
SHSL
MISO
t
SLIV
Table 21-1. Serial Programming Characteristics, T = -40⋅ C to 85⋅ C, V = 4.0 - 5.5V (Unless Otherwise Noted)
A CC
| Symbol | Parameter | | Min | Typ | Max | Units |
| ------ | -------------------- | --- | --- | --- | --- | ----- |
| 1/t | Oscillator Frequency | | 3 | | 33 | MHz |
CLCL
| t CLCL | Oscillator Period | | 30 | | | ns |
| ------ | --------------------------------- | --- | ---- | --- | --- | --- |
| t | SCK Pulse Width High | | 8 t | | | ns |
| SHSL | | | CLCL | | | |
| t | SCK Pulse Width Low | | 8 t | | | ns |
| SLSH | | | CLCL | | | |
| t | MOSI Setup to SCK High | | t | | | ns |
| OVSH | | | CLCL | | | |
| t | MOSI Hold after SCK High | | 2 t | | | ns |
| SHOX | | | CLCL | | | |
| t SLIV | SCK Low to MISO Valid | | 10 | 16 | 32 | ns |
| t | Chip Erase Instruction Cycle Time | | | | 500 | ms |
ERASE
| t | Serial Byte Write Cycle Time | | | | 64 t + 400 | µs |
| --- | ---------------------------- | --- | --- | --- | ---------- | --- |
| SWC | | | | | CLCL | |
22. Absolute Maximum Ratings*
| | | | *NOTICE: | Stresses beyond those listed under “Absolute | | |
| --- | --- | --- | -------- | --------------------------------------------- | --- | --- |
Operating Temperature..................................-55°C to +125°C
Maximum Ratings” may cause permanent dam-
Storage Temperature.....................................-65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground.....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage............................................6.6V conditions for extended periods may affect
device reliability.
DC Output Current......................................................15.0 mA
 21
2487D–MICRO–6/08
23. DC Characteristics
The values shown in this table are valid for T = -40°C to 85°C and V = 4.0V to 5.5V, unless otherwise noted.
A CC
| Symbol Parameter | Condition | | Min | Max | Units |
| ------------------------ | ----------- | --- | ---- | ---------- | ----- |
| V Input Low Voltage | (Except EA) | | -0.5 | 0.2 V -0.1 | V |
| IL | | | | CC | |
| V Input Low Voltage (EA) | | | -0.5 | 0.2 V -0.3 | V |
| IL1 | | | | CC | |
V IH Input High Voltage (Except XTAL1, RST) 0.2 V CC +0.9 V CC +0.5 V
| V Input High Voltage | (XTAL1, RST) | | 0.7 V | V +0.5 | V |
| ------------------------------------- | ------------ | --- | ----- | ------ | --- |
| IH1 | | | CC | CC | |
| V Output Low Voltage(1) (Ports 1,2,3) | I = 1.6 mA | | | 0.45 | V |
| OL | OL | | | | |
Output Low Voltage(1)
| V | I = 3.2 mA | | | 0.45 | V |
| ----------------------- | -------------- | ----------- | --- | ---- | --- |
| OL1 (Port 0, ALE, PSEN) | OL | | | | |
| | I = -60 µA, V | = 5V ± 10% | 2.4 | | V |
| | OH | CC | | | |
Output High Voltage
| V | I = -25 µA | | 0.75 V | | V |
| --------------------------- | ----------- | --- | ------ | --- | --- |
| OH (Ports 1,2,3, ALE, PSEN) | OH | | CC | | |
| | I = -10 µA | | 0.9 V | | V |
| | OH | | CC | | |
 = 5V ± 10%
| | I OH = -800 µA, V | CC | 2.4 | | V |
| --- | ------------------ | --- | --- | --- | --- |
Output High Voltage
| V | I = -300 µA | | 0.75 V | | V |
| --------------------------------------- | ------------ | --- | ------ | --- | --- |
| OH1 (Port 0 in External Bus Mode) | OH | | CC | | |
| | I = -80 µA | | 0.9 V | | V |
| | OH | | CC | | |
| I Logical 0 Input Current (Ports 1,2,3) | V = 0.45V | | | -50 | µA |
| IL | IN | | | | |
Logical 1 to 0 Transition Current
| I | V = 2V, V | = 5V ± 10% | | -300 | µA |
| ---------------- | ---------- | ------------ | --- | ---- | --- |
| TL (Ports 1,2,3) | IN | CC | | | |
±10
| I Input Leakage Current (Port 0, EA) | 0.45 < V | < V | | | µA |
| ------------------------------------ | --------------------- | --------- | --- | --- | --- |
| LI | | IN CC | | | |
| RRST Reset Pulldown Resistor | | | 50 | 300 | KΩ |
| C IO Pin Capacitance | Test Freq. = 1 MHz, T | A = 25°C | | 10 | pF |
| | Active Mode, 12 MHz | | | 25 | mA |
Power Supply Current
| I | Idle Mode, 12 MHz | | | 6.5 | mA |
| --- | ----------------- | --- | --- | --- | --- |
CC
Power-down Mode(2)
| | V = 5.5V | | | 50 | µA |
| --- | ---------- | --- | --- | --- | --- |
CC
 must be externally limited as follows:
Notes: 1. Under steady state (non-transient) conditions, I
OL
Maximum I per port pin: 10 mA
OL
Maximum I per 8-bit port:
OL
Port 0: 26 mA Ports 1, 2, 3: 15 mA
 for all output pins: 71 mA
Maximum total I OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater
OL OL
than the listed test conditions.
2. Minimum V for Power-down is 2V.
CC
AT89S51
 22
2487D–MICRO–6/08
 AT89S51
24. AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.
24.1 External Program and Data Memory Characteristics
| | | 12 MHz Oscillator | | Variable Oscillator | | |
| ------ | -------------------- | ----------------- | --- | ------------------- | --- | ----- |
| Symbol | Parameter | Min | Max | Min | Max | Units |
| 1/t | Oscillator Frequency | | | 0 | 33 | MHz |
CLCL
| t | ALE Pulse Width | 127 | | 2 t -40 | | ns |
| ------ | --------------------------------- | --- | --- | ---------- | ------------ | --- |
| LHLL | | | | CLCL | | |
| t AVLL | Address Valid to ALE Low | 43 | | t CLCL -25 | | ns |
| t | Address Hold After ALE Low | 48 | | t -25 | | ns |
| LLAX | | | | CLCL | | |
| t | ALE Low to Valid Instruction In | | 233 | | 4 t -65 | ns |
| LLIV | | | | | CLCL | |
| t | ALE Low to PSEN Low | 43 | | t -25 | | ns |
| LLPL | | | | CLCL | | |
| t | PSEN Pulse Width | 205 | | 3 t -45 | | ns |
| PLPH | | | | CLCL | | |
| t PLIV | PSEN Low to Valid Instruction In | | 145 | | 3 t CLCL -60 | ns |
| t | Input Instruction Hold After PSEN | 0 | | 0 | | ns |
PXIX
| t | Input Instruction Float After PSEN | | 59 | | t -25 | ns |
| ------ | ---------------------------------- | --- | --- | -------- | ------- | --- |
| PXIZ | | | | | CLCL | |
| t | PSEN to Address Valid | 75 | | t -8 | | ns |
| PXAV | | | | CLCL | | |
| t | Address to Valid Instruction In | | 312 | | 5 t -80 | ns |
| AVIV | | | | | CLCL | |
| t PLAZ | PSEN Low to Address Float | | 10 | | 10 | ns |
| t | RD Pulse Width | 400 | | 6 t -100 | | ns |
| RLRH | | | | CLCL | | |
| t | WR Pulse Width | 400 | | 6 t -100 | | ns |
| WLWH | | | | CLCL | | |
| t | RD Low to Valid Data In | | 252 | | 5 t -90 | ns |
| RLDV | | | | | CLCL | |
| t | Data Hold After RD | 0 | | 0 | | ns |
RHDX
| t RHDZ | Data Float After RD | | 97 | | 2 t CLCL -28 | ns |
| ------ | --------------------------- | --- | --- | ---------- | ------------ | --- |
| t | ALE Low to Valid Data In | | 517 | | 8 t -150 | ns |
| LLDV | | | | | CLCL | |
| t | Address to Valid Data In | | 585 | | 9 t -165 | ns |
| AVDV | | | | | CLCL | |
| t | ALE Low to RD or WR Low | 200 | 300 | 3 t -50 | 3 t +50 | ns |
| LLWL | | | | CLCL | CLCL | |
| t | Address to RD or WR Low | 203 | | 4 t -75 | | ns |
| AVWL | | | | CLCL | | |
| t QVWX | Data Valid to WR Transition | 23 | | t CLCL -30 | | ns |
| t | Data Valid to WR High | 433 | | 7 t -130 | | ns |
| QVWH | | | | CLCL | | |
| t | Data Hold After WR | 33 | | t -25 | | ns |
| WHQX | | | | CLCL | | |
| t | RD Low to Address Float | | 0 | | 0 | ns |
RLAZ
| t | RD or WR High to ALE High | 43 | 123 | t -25 | t +25 | ns |
| ---- | ------------------------- | --- | --- | ----- | ----- | --- |
| WHLH | | | | CLCL | CLCL | |
 23
2487D–MICRO–6/08
25. External Program Memory Read Cycle
t LHLL
ALE
t
PLPH
| | t | | | t | | |
| --- | ---- | --- | --- | ---- | --- | --- |
| | AVLL | t | | LLIV | | |
LLPL
| PSEN | | | | t | | |
| ---- | --- | --- | --- | --- | --- | --- |
PLIV
t
PXAV
t
| | | | PLAZ | t | | |
| --- | --- | --- | ---- | ---- | --- | --- |
| | | t | | PXIZ | | |
LLAX
t
PXIX
| PORT0 | | A0-A7 | | INSTRIN | | A0-A7 |
| ----- | --- | ----- | --- | ------- | --- | ----- |
t
AVIV
| PORT2 | | | A8-A15 | | | A8-A15 |
| ----- | --- | --- | ------ | --- | --- | ------ |
26. External Data Memory Read Cycle
t
LHLL
ALE
t
WHLH
PSEN
t
LLDV
t
RLRH
t
LLWL
| RD | | t | | | | |
| --- | --- | --- | --- | --- | --- | --- |
LLAX
| | | | | t | t | |
| --- | ---- | ---- | --- | ---- | ---- | --- |
| | t | | | RLDV | RHDZ | |
| | AVLL | t | | | | |
| | | RLAZ | | | t | |
RHDX
PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN
t
AVWL
t
AVDV
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
AT89S51
 24
2487D–MICRO–6/08
 AT89S51
27. External Data Memory Write Cycle
t LHLL
ALE
t
WHLH
PSEN
| | | | t | t | | |
| --- | --- | --- | ---- | ---- | --- | --- |
| | | | LLWL | WLWH | | |
WR
t LLAX
| | | t | t | | t | |
| --- | --- | ---- | ---- | --- | ---- | --- |
| | | AVLL | QVWX | | WHQX | |
t
QVWH
PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN
t
AVWL
PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
28. External Clock Drive Waveforms
t
CHCX
t
| | | CHCX | | t CLCH | | t CHCL |
| --- | --- | ---- | --- | ------ | --- | ------ |
V - 0.5V
CC
0.7 V CC
0.2 V - 0.1V
CC
0.45V
t
CLCX
t
CLCL
29. External Clock Drive
| Symbol | Parameter | | | Min | Max | Units |
| -------- | -------------------- | --- | --- | --- | --- | ----- |
| 1/t CLCL | Oscillator Frequency | | | 0 | 33 | MHz |
| t | Clock Period | | | 30 | | ns |
CLCL
| t | High Time | | | 12 | | ns |
| --- | --------- | --- | --- | --- | --- | --- |
CHCX
| t | Low Time | | | 12 | | ns |
| --- | -------- | --- | --- | --- | --- | --- |
CLCX
| t | Rise Time | | | | 5 | ns |
| --- | --------- | --- | --- | --- | --- | --- |
CLCH
| t CHCL | Fall Time | | | | 5 | ns |
| ------ | --------- | --- | --- | --- | --- | --- |
 25
2487D–MICRO–6/08
30. Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for V = 4.0V to 5.5V and Load Capacitance = 80 pF.
CC
| | | | | 12 MHz Osc | Variable Oscillator | | |
| ------ | ---------------------------------------- | --- | --- | ---------- | ------------------- | --- | ----- |
| Symbol | Parameter | | | Min Max | Min | Max | Units |
| t | Serial Port Clock Cycle Time | | | 1.0 | 12 t | | µs |
| XLXL | | | | | CLCL | | |
| t | Output Data Setup to Clock Rising Edge | | | 700 | 10 t -133 | | ns |
| QVXH | | | | | CLCL | | |
| t | Output Data Hold After Clock Rising Edge | | | 50 | 2 t -80 | | ns |
| XHQX | | | | | CLCL | | |
| t | Input Data Hold After Clock Rising Edge | | | 0 | 0 | | ns |
XHDX
t XHDV Clock Rising Edge to Input Data Valid 700 10 t CLCL -133 ns
31. Shift Register Mode Timing Waveforms
| | INSTRUCTION | 0 | 1 2 | 3 4 | 5 6 | 7 8 | |
| --- | ----------- | --- | --- | --- | --- | --- | --- |
ALE
t
XLXL
CLOCK
t
| | | QVXH | t | | | | |
| --- | --- | ---- | --- | --- | --- | --- | --- |
XHQX
WRITETOSBUF
| | | | 0 1 | 2 3 | 4 5 | 6 7 | |
| --- | --- | --- | --- | --- | --- | --- | --- |
t
| | OUTPUTDATA | | t | XHDX | | SETTI | |
| --- | ---------- | --- | --- | ---- | --- | ----- | --- |
XHDV
| | CLEARRI | | VALID VALID | VALID VALID | VALID VALID | VALID VALID | |
| --- | --------- | --- | ----------- | ----------- | ----------- | ----------- | --- |
| | INPUTDATA | | | | | SETRI | |
32. AC Testing Input/Output Waveforms(1)
V - 0.5V
| | | CC | | 0.2 V + 0.9V | | | |
| --- | --- | --- | --- | ------------------ | --- | --- | --- |
CC
TEST POINTS
0.2 V - 0.1V
| | | 0.45V | | CC | | | |
| --- | --- | ----- | --- | --- | --- | --- | --- |
Note: 1. AC Inputs during testing are driven at V - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V
| | | | CC | | | | IH |
| --- | ------------------------ | -------------------- | --- | --- | --- | --- | --- |
| | min. for a logic 1 and V | max. for a logic 0. | | | | | |
IL
33. Float Waveforms(1)
| | | | V + 0.1V | V | - 0.1V | | |
| --- | --- | --- | ----------------- | --- | ------ | --- | --- |
| | | | LOAD | | OL | | |
| | | V | Timing Reference | | | | |
LOAD
Points
| | | | V - 0.1V | V | + 0.1V | | |
| --- | --- | --- | -------- | --- | ------ | --- | --- |
| | | | LOAD | | OL | | |
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
| | float when a 100 mV change from the loaded V | | /V | level occurs. | | | |
| --- | -------------------------------------------- | --- | --- | -------------- | --- | --- | --- |
| | | | OH | OL | | | |
AT89S51
 26
2487D–MICRO–6/08
 AT89S51
34. Ordering Information
34.1 Green Package Option (Pb/Halide-free)
| Speed | Power | | | |
| ----- | ------ | ------------- | ------- | --------------- |
| (MHz) | Supply | Ordering Code | Package | Operation Range |
| | | AT89S51-24AU | 44A | |
Industrial
| 24 | 4.0V to 5.5V | AT89S51-24JU | 44J | |
| --- | ------------ | ------------ | --- | --- |
(-40°C to 85°C)
| | | AT89S51-24PU | 40P6 | |
| --- | --- | ------------ | ---- | --- |
| | | AT89S51-33AU | 44A | |
Industrial
| 33 | 4.5V to 5.5V | AT89S51-33JU | 44J | |
| --- | ------------ | ------------ | --- | --- |
(-40°C to 85°C)
| | | AT89S51-33PU | 40P6 | |
| --- | --- | ------------ | ---- | --- |
Package Type
| 44A | 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) | | | |
| ---- | ------------------------------------------------------- | --- | --- | --- |
| 44J | 44-lead, Plastic J-leaded Chip Carrier (PLCC) | | | |
| 40P6 | 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) | | | |
 27
2487D–MICRO–6/08
35. Packaging Information
35.1 44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
e E1 E
D1
D
C 0˚~7˚
A1 A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
| | SYMBOL MIN | NOM MAX | NOTE |
| --- | ---------- | ----------- | ---------- |
| | A – | – 1.20 | |
| | A1 0.05 | – 0.15 | |
| | A2 0.95 | 1.00 1.05 | |
| | D 11.75 | 12.00 12.25 | |
| | D1 9.90 | 10.00 10.10 | Note 2 |
| | E 11.75 | 12.00 12.25 | |
Notes: 1.This package conforms to JEDEC reference MS-026, Variation ACB.
| | E1 9.90 | 10.00 10.10 | Note 2 |
| --- | ------- | ----------- | ------ |
2.Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.30 – 0.45
plastic body size dimensions including mold mismatch.
| | C 0.09 | – 0.20 | |
| --- | ------ | ------ | --- |
3. Lead coplanarity is 0.10 mm maximum.
| | L 0.45 | – 0.75 | |
| --- | ------ | -------- | --- |
| | e | 0.80 TYP | |
10/5/2001
TITLE DRAWING NO.
REV.
 2325 Orchard Parkway
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
| San Jose, CA 95131 | | 44A | B |
| --------------------- | --- | --- | --- |
R 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
AT89S51
 28
2487D–MICRO–6/08
 AT89S51
35.2 44J – PLCC
1.14(0.045) X 45˚
1.14(0.045) X 45˚ PIN NO. 1
0.318(0.0125)
IDENTIFIER
0.191(0.0075)
| | | E1 E | | B1 | D2/E2 | | |
| --- | --- | ---- | --- | --- | ----- | --- | --- |
B
 e
A2
D1
| | D | | | A1 | | | |
| --- | --- | --- | --- | --- | --- | --- | --- |
 A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
| | | | SYMBOL | MIN | NOM | MAX NOTE | |
| --- | --- | --- | ------ | ------ | --- | ------------- | --- |
| | | | A | 4.191 | – | 4.572 | |
| | | | A1 | 2.286 | – | 3.048 | |
| | | | A2 | 0.508 | – | – | |
| | | | D | 17.399 | – | 17.653 | |
| | | | D1 | 16.510 | – | 16.662 Note 2 | |
| | | | E | 17.399 | – | 17.653 | |
Notes: 1.This package conforms to JEDEC reference MS-018, Variation AC.
| | | | E1 | 16.510 | – | 16.662 Note 2 | |
| --- | --- | --- | --- | ------ | --- | ------------- | --- |
2.Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 14.986 – 16.002
and E1 include mold mismatch and are measured at the extreme
| | | | B | 0.660 | – | 0.813 | |
| --- | --- | --- | --- | ----- | --- | ----- | --- |
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533
| | | | e | | 1.270 TYP | | |
| --- | --- | --- | --- | --- | --------- | --- | --- |
10/04/01
| | TITLE | | | | DRAWING NO. | | REV. |
| --- | ----- | --- | --- | --- | ----------- | --- | ------ |
 2325 Orchard Parkway
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
| San Jose, CA 95131 | | | | | | 44J | B |
| --------------------- | --- | --- | --- | --- | --- | --- | --- |
R
 29
2487D–MICRO–6/08
35.3 40P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
| | | SYMBOL MIN | NOM | MAX NOTE | |
| --- | --- | ---------- | --- | ------------- | --- |
| | eB | A – | – | 4.826 | |
| | | A1 0.381 | – | – | |
| | | D 52.070 | – | 52.578 Note 2 | |
| | | E 15.240 | – | 15.875 | |
| | | E1 13.462 | – | 13.970 Note 2 | |
| | | B 0.356 | – | 0.559 | |
| | | B1 1.041 | – | 1.651 | |
Notes: 1.This package conforms to JEDEC reference MS-011, Variation AC.
2.Dimensions D and E1 do not include mold Flash or Protrusion. L 3.048 – 3.556
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
| | | C 0.203 | – | 0.381 | |
| --- | --- | --------- | --------- | --------------- | --- |
| | | eB 15.494 | – | 17.526 | |
| | | e | 2.540 TYP | | |
09/28/01
| | TITLE | | DRAWING NO. | | REV. |
| --- | ----- | --- | ----------- | --- | ------ |
 2325 Orchard Parkway
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual
| San Jose, CA 95131 | | | | 40P6 | B |
| --------------------- | ----------------------- | --- | --- | ---- | --- |
| R | Inline Package (PDIP) | | | | |
AT89S51
 30
2487D–MICRO–6/08
| Headquarters | International | | |
| ----------------- | ------------- | ------------ | ----------- |
| Atmel Corporation | Atmel Asia | Atmel Europe | Atmel Japan |
2325 Orchard Parkway Room 1219 Le Krebs 9F, Tonetsu Shinkawa Bldg.
San Jose, CA 95131 Chinachem Golden Plaza 8, Rue Jean-Pierre Timbaud 1-24-8 Shinkawa
| USA | 77 Mody Road Tsimshatsui | BP 309 | Chuo-ku, Tokyo 104-0033 |
| --- | ------------------------ | ------ | ----------------------- |
Tel: 1(408) 441-0311 East Kowloon 78054 Saint-Quentin-en- Japan
Fax: 1(408) 487-2600 Hong Kong Yvelines Cedex Tel: (81) 3-3523-3551
| | Tel: (852) 2721-9778 | France | Fax: (81) 3-3523-7581 |
| --- | -------------------- | ------------------------ | --------------------- |
| | Fax: (852) 2722-1369 | Tel: (33) 1-30-60-70-00 | |
Fax: (33) 1-30-60-71-11
Product Contact
| | Web Site | Technical Support | Sales Contact |
| --- | ------------- | ----------------- | ---------------------- |
| | www.atmel.com | mcu@atmel.com | www.atmel.com/contacts |
Literature Requests
www.atmel.com/literature
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2487D–MICRO–6/08