text stringlengths 992 1.04M |
|---|
module conmutacion
(
input [3:0] centenas,
input [3:0] decenas,
input [3:0] unidades,
input C,
input De,
input U,
input CLKOUTseg,
output reg [1:0] mostrar,
output reg [3:0] digito
);
reg logic0;
reg [1:0] titileo;
initial
begin
titileo = 0;
end
always@(posedge CLKOUTseg)
begin
if(C &&... |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except i... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: dtysky
//
// Create Date: 2015/01/19 09:26:57
// Design Name: INST_MEM
// Module Name: INST_MEM
// Project Name: MIPS_CPU
// Target Devices:
// Tool Versions:
// Description:
//
/... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to test... |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use ... |
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partne... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
fastclk
);
input fastclk;
t_netlist tnetlist
(.also_fastclk (fastclk),
/*AUTOINST*/
// Inputs
... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- ... |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use ... |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_wrap_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module ax... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/27/2015 03:47:45 PM
// Design Name:
// Module Name: wildcard_processer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:... |
// mi_nios_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2015.05.20.08:55:19
`timescale 1 ps / 1 ps
module mi_nios_mm_interconnect_0 (
input wire clk_50_clk_c... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [7:0] a,b;
wire [7:0] z;
mytop u0 ( a, b, clk, z );
in... |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated ... |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Tue May 13 22:55:34 2014
// Host : macbook running 64-bit Arch Linux
// ... |
//
// Copyright (c) 2003 Launchbird Design Systems, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
// Redistributions of source code must retain the above copyright notice, this lis... |
// Universal Shift Register
// Created by David Tran
// Version 0.0.0.0
// Last Modified 04-03-2014
`include "shift_register_4_beh.v"
`timescale 1 ns / 1 ps
//{{ Section below this comment is automatically maintained
// and may be overwritten
//{module {shift_register_4_beh_tb}}
module shift_register_4_b... |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Found... |
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
`define RAM_BLOCK cyclonev_ram_block
`define IBUF cyclonev_io_ibuf
`define OBUF cyclonev_io_obuf
`define CLKENA cyclonev_clkena
`endif
`ifdef arriav
`define LCELL arriav_lcell_comb
`define MAC arriav_mac
`define M... |
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's des... |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distri... |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************... |
/* Memory mapped modules */
// Generate 25.00MHz
reg [1:0] clkdiv; // divider
always @(posedge sys_clk_in)
begin
case (clkdiv)
2'b11: clkdiv <= 2'b10;
2'b10: clkdiv <= 2'b00;
2'b00: clkdiv <= 2'b01;
2'b01: clkdiv <= 2'b11;
en... |
// file: clk_wiz_v3_3.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
function int f_no_no ();
int st = 2; st++; return st;
endfunction
function int f_... |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
//---------------------------------------------------------------------------------------
// uart transmit module
//
//---------------------------------------------------------------------------------------
module uart_tx
(
clock, reset,
ce_16, tx_data, new_tx_data,
ser_out, tx_busy
);
//-----------... |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
class Cls;
int value;
extern function int ext_f_np;
extern function int ext_f_p();
extern func... |
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-... |
module channel_demux
#(parameter NUM_CHAN = 2) ( //usb Side
input [31:0]usbdata_final,
input WR_final,
// TX Side
input reset,
input txclk,
output reg [NUM_CHAN:0] WR_channel,
output reg [31:0] ram_data,
output reg [NUM_CHAN:0] WR_done_channel );
/* Parse header and forward to ram */
... |
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/****************************************************************************... |
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
/... |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.or... |
`timescale 1ps / 1ps
module AXI_SPI_ROM_test(
);
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for(i = 0; 2**i < value; i = i + 1)
clogb2 = i + 1;
end
endfu... |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
/... |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge (schuyler.eldridge@gmail.com)
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
modul... |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 10 01:06:40 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, a... |
/*
* This is a post-synthesis test for the blif01a.v test. Run this
* simulation in these steps:
*
* $ iverilog -tblif -o foo.blif blif01a.v
* $ abc
* abc 01> read_blif foo.blif
* abc 02> write_verilog foo.v
* abc 03> quit
* $ iverilog -g2009 -o foo.vvp blif02a_tb.v foo.v
* $ vvp foo.vvp
*/
mo... |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
... |
`timescale 1ns / 100ps
module uartlib(
input UART_CLK, output reg UART_TX
);
integer counter;
initial
UART_TX = 1;
task write_byte;
input [7:0] data;
begin
//start bit
$display("write_byte: 0x%x (0b%b) [%c]", data, data, da... |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
// Date : Thu May 28 19:32:19 2015
// Host : Dtysky running 64-bit major release ... |
module EXMEM_Reg (
input clk,
input flush,
input stall,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] ALU_output_i,
output [32-1:0] ALU_output_o,
input [3... |
// Copyright (C) 1991-2012 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated docume... |
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/****************************************************************************************
*
* File Name: ddr3.v
* Version: 1.61
* Model: BUS Functional
*
* Dependencies: ddr3_model_parameters.vh
*
* Description: Micron SDRAM DDR3 (Double Data Rate 3)
*
* Limitation: - doesn't check for average r... |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// ... |
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming encoder
*/
module ham_15_11_encoder (d,c);
// Output signals representing the 15-bit encoded vector
output reg [14:0] c;
// Input signals representing the 11-bit input
input [10:0] d;
... |
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
//==================================================================================================
// Filename : musb_ifid_register.v
// Created On : 2014-09-27 20:34:54
// Last Modified : 2015-05-31 13:04:30
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón B... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:41:14 04/19/2014
// Design Name:
// Module Name: Image_viewer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
/... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERL... |
/*
* Copyright (C) 2007 Onno Kortmann <onno@gmx.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* T... |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.1
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
... |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of... |
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
/... |
module pkt_recomb(
input clk,
input reset,
input pkt_metadata_cut_out_valid,
input [359:0] pkt_metadata_cut_out,
input [138:0] pkt_cut_data,
input pkt_cut_data_valid,
output [7:0] pkt_cut_data_usedw,
input buf_addr_wr,
input [3:0] buf_addr,
output reg [3:0] aging_recycle_... |
/**********************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLA... |
module qsys (
clk_clk,
reset_reset_n,
sdram_clock_areset_conduit_export,
sdram_clock_c0_clk,
sdram_read_control_fixed_location,
sdram_read_control_read_base,
sdram_read_control_read_length,
sdram_read_control_go,
sdram_read_control_done,
sdram_read_control_early_done,
sdram_read_user_read_buffer,
sdram_rea... |
// See Line 54
module hangcase (/*AUTOARG*/);
//
assign w_rdat_ena = ({16{foo[ 0]}} & bar ) |
({16{foo[ 1]}} & bar ) |
({16{foo[ 2]}} & bar ) |
({16{foo[ 3]}} & bar ) |
({16{foo[ 4]}} & bar ) |
... |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2014 *)
(* \VV/ **************************************************************)
(* // * Th... |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Store Buffer FIFO ////
//// ////
//// This file is part of the OpenR... |
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not g... |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
/... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulati... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx Inc.
// Engineer: Parimal Patel
// Create Date: 06/21/2016 09:22:41 AM
// Module Name: PdmDes
// Project Name: PYNQ
/////////////////////////////////////////////////////////////////////////////////... |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_2k.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ******************************... |
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 compliant I2C Master bit-controller ////
//// ////
//// ... |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulati... |
module fpga_top
(
input wire RSTN,
input wire clk_sys,
input wire clk,
input wire SW4N,
input wire SW5N,
output wire [7:0] SEG_A,
output wire [7:0] SEG_B,
output wire [7:0] SEG_C,
output wire [7:0] SEG_D,
output wire [7:0] SEG_E,
output wire [7:0] SEG_F,
output... |
module top;
reg pass;
reg signed [7:0] neg = -2;
reg signed [7:0] m1 = -1;
reg signed [7:0] zero = 0;
reg signed [7:0] one = 1;
reg signed [7:0] pos = 2;
reg signed [7:0] pose = 2;
reg signed [7:0] poso = 3;
reg signed [7:0] res;
initial begin
pass = 1'b1;
#1;
/* Positive exponent. *... |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
modul... |
//-------------------------------------------------------------------
//-- echowire2_tb.v
//-- Banco de pruebas para el eco cableado del puerto serie y las
//-- comprobaciones de las señales DTR y RTS
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (O... |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pclk_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ====================================... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:33:50 11/11/2015
// Design Name:
// Module Name: GameWithSound
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies: ... |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:33 2019
// Host : varun-laptop running 64-bit Serv... |
// hps_design_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module hps_design_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wi... |
`define MEMORY_CONTROLLER_TAGS 1
`define MEMORY_CONTROLLER_TAG_SIZE 1
`define TAG__str 1'b0
`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 32
module memory_controller
(
clk,
memory_controller_address,
memory_controller_write_enable,
memory_controller_in,
memory_controller_out
);
inp... |
/*******************************************************************************
* Module: pll_base
* Date:2014-05-01
* Author: Andrey Filippov
* Description: PLLE2_BASE wrapper
*
* Copyright (c) 2014 Elphel, Inc.
* pll_base.v is free software; you can redistribute it and/or modify
* it under the terms of the... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
//rd0 - 128bit, aligned (also supports unaligned)
//rd1 - 64bit, aligned (also supports unaligned)
//rd2 - 64bit, aligned (also supports unaligned)
//wr0 - 128/64/32bit (4 bit enable), aligned
//wr1 - 64/32bit (2 bit enable), aligned
module reg_512x32b_3r_2w
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_d... |
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a... |
module allocator
(/*AUTOARG*/
// Outputs
allocator_cu_valid, allocator_cu_rejected, allocator_wg_id_out,
allocator_cu_id_out, allocator_wf_count, allocator_vgpr_size_out,
allocator_sgpr_size_out, allocator_lds_size_out,
allocator_gds_size_out, allocator_vgpr_start_out,
allocator_sgpr_start_out, allo... |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * Th... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 25.06.2017 19:20:37
// Design Name:
// Module Name: conversor_num_16b
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//... |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use ... |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user int... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #(PAR) m1();
m3 #(PAR) m3();
mnooverride #(10) mno();
input clk;
integ... |
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