text stringlengths 992 1.04M |
|---|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// Used for 32 bit data axi ports like GP0/GP1
module axi_master32_stub(
output M2S_AXI_ACLK,
//Read Transaction
output M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
... |
module simf_tb;
//wires
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
reg [5:0] issue_wfid;
reg [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
reg [15:0] issue_imm_value0;
reg [31:0] issue_imm_value1,... |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual pro... |
module axis_control_if
#(
parameter C_s_axis_TDATA_WIDTH = 32,
parameter C_m_axis_TDATA_WIDTH = 32,
parameter C_m_axis_START_COUNT = 32,
parameter C_S_AXIS_RXS_TDATA_WIDTH = 32,
parameter C_M_AXIS_TXC_TDATA_WIDTH = 32,
parameter C_m_axis_txc_START_COUNT = 32,
parameter ENABLE_LEN = 1
... |
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
Graying
:Function
Covert RGB images to gray-scale images.
Users can configure the multipliers by themselves.
Give the first output after mul_delay + 2 cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tia... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode=0;
reg [7:0] a;
reg [7:0] b;
reg [7:0] c;
reg [7:0... |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute,... |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
(** * Types: Type Systems *)
Require Export Smallstep.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and ... |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timesc... |
module test1(
input wire clk,
input wire reset,
input wire enabled,
input wire in,
input wire Start,
input wire Stop,
output wire sda
);
reg start, done, data;
always@( negedge Start or reset )
begin
if(~reset)
begin
start <= 1'b0;
end
else
begin
if( ena... |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a... |
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated docume... |
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
/... |
/*
* Copyright 2012, Homer Hsing <homer.hsing@gmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applica... |
`default_nettype none
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
inp... |
module bram1 #(
parameter ABITS = 8, DBITS = 8, TRANSP = 0
) (
input clk,
input [ABITS-1:0] WR_ADDR,
input [DBITS-1:0] WR_DATA,
input WR_EN,
input [ABITS-1:0] RD_ADDR,
output [DBITS-1:0] RD_DATA
);
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] I... |
/*
File: axi_slave.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <support@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
... |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:13:20 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1... |
// File: UpDown_CounterTBV.v
// Generated by MyHDL 0.10
// Date: Tue Aug 14 06:51:27 2018
`timescale 1ns/10ps
module UpDown_CounterTBV (
);
// myHDL -> Verilog Testbench for `Down_Counter` module
reg clk = 0;
reg rst = 0;
reg Trig = 0;
wire [4:0] count;
reg [0:0] Dir = 1'b0;
reg [4:0] Down_Counter0_0_1_count_i = ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not gr... |
`timescale 1ns/10ps
module PLL108_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.o... |
// Copyright (c) 2009 Bluespec, Inc. ALL RIGHTS RESERVED
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module xilinx_v5_pcie_wrapper
(
// Outputs
refclkout, cfg_to_turnoff_n, trn_tdst_dsc_n, trn_tdst_rdy_n,
trn_reof_n, cfg_interrupt_rdy_n, trn_reset_n, trn_rsrc_dsc_n,
trn_cl... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef enum logic [4:0]
{
BIT0 = 5'd0,
BIT1 = 5'd1,
BIT2 = 5'd2
} three_t;
module t (/*AUTOARG*/);
localparam FIVE = 5;
e... |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2005 Matt Ettus
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free S... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_alt2gxb_aligned_rxsync.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/strxii_pc... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/*
* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at ... |
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module adc_interface
(input clock, input reset, input enable,
input wire [6:0] serial_addr, input wire [31:0] serial_data, input serial_strobe,
input wire [11:0] rx_a_a, input wire [11:0] rx_b_a, input... |
// megafunction wizard: %LPM_COUNTER%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: coincidence_counter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ========================... |
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 1999-2008 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyrigh... |
//======================================================================
//
// hc.v
// ----
// Top level wrapper for the HC stream cipher.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2017, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modificat... |
/*
*
* Copyright (c) 2011 fpgaminer@bitcoin-mining.com
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This pr... |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated docum... |
/* note for avalon interface
bus type: nagtive
read legacy = 0 (to consistent to FIFO)
*/
module adc_ltc2308_fifo(
// avalon slave port
slave_clk,
slave_reset_n,
slave_chipselect_n,
slave_addr,
slave_read_n,
slave_wrtie_n,
slave_readdata,
slave_wriredata,
adc_clk, // max 40mhz
// adc interface
ADC_CON... |
(** * References: Typing Mutable References *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
Require Export Smallstep.
(** So far, we have considered a variety of _pure_ language features,
including functional abstraction, basic types such as numbers and
booleans, and structured types such as r... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/14/2015 05:20:43 PM
// Design Name:
// Module Name: Problem4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// R... |
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must re... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
* Decode WJX1 Wide Opcode
*/
`include "CoreDefs.v"
`include "DecWOp1.v"
module DecWOp(
/* verilator lint_off UNUSED */
clock, istrWord, opStep,
idRegN1, idRegS1, idRegT1, idImm1, idUCmd1,
idRegN2, idRegS2, idRegT2, idImm2, idUCmd2,
idRegN3, idRegS3, idRegT3, idImm3, idUCmd3,
idRegN4, idRegS4, idRegT4, idIm... |
(** * StlcProp: Properties of STLC *)
Require Export Stlc.
Module STLCProp.
Import STLC.
(** in this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * ... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant ... |
/*
* PS2 Mouse without FIFO buffer
* Copyright (C) 2010 Donna Polehn <dpolehn@verizon.net>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundat... |
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a... |
/*******************************************************************************
* *
* Copyright (C) 2009 Altera Corporation *
* ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
... |
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual proper... |
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use ... |
module mem_window (
clk,
reset,
// Memory slave port
s1_address,
s1_read,
s1_readdata,
s1_readdatavalid,
s1_write,
s1_writedata,
s1_burstcount,
s1_byteenable,
s1_waitrequest,
// Configuration register slave port
cra_write,
cra_writedata,
cra_byteenable,
// Bridged m... |
/*
*******************************************************************************
* File Name : ada_bram.v
* Project : ADA processor
* Version : 0.1
* Date : Sept 1st, 2014
* Author : Angel Terrones <angelterrones@gmail.com>
*
* Disclaimer : Copyright (c) 2014 Angel Ter... |
//////////////////////////////////////////////////////////////////////////////////
// Decoder for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <kbpark@enc.hanyang.ac.kr>
// Yong Ho Song <yhsong@enc.hanyang.ac.kr>
//
// This file is part of Cosmos OpenSSD.
... |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2021 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only... |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ... |
module test_mem_dev #(
parameter READ_FIFO_SIZE = 8,
parameter WRITE_FIFO_SIZE = 8,
parameter ADDRESS_WIDTH = 8,
parameter ENABLE_ERROR_CHECK = 1,
parameter INITIALIZE_MEM = 1
)(
input clk,
inp... |
/*
* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at ... |
//wishbone_arbiter.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, includi... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// issue2895
module t (/*AUTOARG*/);
localparam string REG_X [0:31] = '{"zero", "ra", "sp", "gp", "tp... |
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will... |
(** * Norm: Normalization of STLC *)
(* $Date: 2014-04-23 07:36:43 -0400 (Wed, 23 Apr 2014) $ *)
(* Chapter maintained by Andrew Tolmach *)
(* (Based on TAPL Ch. 12.) *)
Require Export Smallstep.
Hint Constructors multi.
(**
(This chapter is optional.)
In this chapter, we consider another fundamental theoretica... |
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distr... |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 28 10:19:23 2017
// Host : vldmr-PC running 64-bit Service ... |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major rel... |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_afi_slave.v
*
* Date : 2012-11
*
* Description : Model that acts as AFI port interface. It uses AXI3 Slave BFM
* from Cadence.
******************************************************... |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulati... |
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version... |
// megafunction wizard: %ALTDDIO_OUT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altddio_out
// ============================================================
// File Name: rgmii_out1.v
// Megafunction Name(s):
// altddio_out
// ============================================================
// ****... |
`timescale 1 ns / 1 ps
module axis_red_pitaya_adc #
(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
output wire adc_clk,
// ADC signals
output wire adc_csn,
input wire adc_clk_p,... |
/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at ... |
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_SC_top.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <jwjeong@enc.hanyang.ac.kr>
// Ilyong Jung <iyjung@enc.hanyang.ac.kr>
// Yong Ho Song <yh... |
`default_nettype none
module rom1ktest (
input wire sysclk,
input wire clk,
input wire rst,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
wire [15:0] dout;
reg [9:0] addr;
//-- Instanciar l... |
module test;
initial begin
$display("Error: \"FloatTest.bsv\", line 234, column 24: (R0001)\n Mutually exclusive rules (from the ME sets [RL_action_l234c24] and\n [RL_action_l235c24, RL_action_l236c24, RL_action_l237c24, RL_action_l238c24,\n RL_action_l239c24, RL_action_l240c24, RL_action_l241c24, RL_action_l24... |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Tue Sep 16 21:34:47 2014
// Host : ECE-411-6 running 64-bit Service Pack... |
`timescale 1ns / 1ps
module NaN_mod_64
(
input wire [1:0] operation,
input wire [63:0] data1,
input wire [63:0] data2,
output reg NaN_flag
);
always @*
begin
case(operation)
2'b00:
begin
if((data1 == 64'h7ff0000000000000) && (data2 == 64'h7ff0000000000000))
NaN_flag ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partne... |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code ... |
module crc
#(parameter BITS=8, parameter POLY=7, parameter INIT=0)
(input wire i_clk, input wire i_rst, input wire i_stb, input wire i_bit, output wire[BITS-1:0] o_crc);
//
// Сдвиговый регистр контрольной суммы.
reg[BITS-1:0] crcreg;
// Провода между регистрами.
wire[BITS-1:0] crcwires;
// Выходное значение ... |
`timescale 1ns/1ps
/*
This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
behavioral Verilog constructs only.
*/
module GP_2LUT(input IN0, IN1, output OUT);
parameter [3:0] INIT = 0;
assign OUT = INIT[{IN1, IN0}];
endmodule
module GP_3LUT(input IN0, IN1... |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH
// Engineer: Krzysztof Kapusta/Mateusz Furdyna
//
// Create Date: 17:11:37 11/01/2014
// Design Name: UART_memory
// Module Name: UART_memory
// Project Name: UART_memory
// Targ... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable la... |
`timescale 1ns / 1ps
module CORDIC_FSM_v2
(
//Input Signals
input wire clk, // Reloj del sitema.
input wire reset, // Reset del sitema.
input wire beg_FSM_CORDIC, // Señal de inicio de la maquina de estados.
input wire ACK_FSM_CORDIC, // Señal proveniente del modulo que recibe el resu... |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "utils/cdc_pulse_sync.v"
... |
module LCD (
input clk,
input [7:0] data_in,
output reg [7:0] data_out,
output reg lcd_e,
output reg lcd_r,
output LED0,
output LED1,
output LED2,
output LED3
);
// implementing a FSM
assign LED0 = state[0];
assign LED1 = state[1];
assign LED2 = state[2];
assign LED3 = state[3];
... |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:21:18 03/06/2017
// Design Name: DNlatch_NAND
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testDNlatch_NAND.v
// Project Name: Homework1
// Target Device: ... |
module test
(input wire clk,
output reg foo, bar,
input wire foo_valid, foo_in,
input wire bar_valid, bar_in
/* */);
always @(posedge clk)
begin
if (foo_valid) foo <= foo_in;
if (bar_valid) bar <= bar_in;
end
endmodule // test
module main;
reg clk;
wire foo, bar;
reg foo_valid... |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx ... |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.