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introduction riscv pronounced riskfive new instructionset architecture isa originally designed support computer architecture research education hope also become standard free open architecture industry implementations goals defining riscv include completely open isa freely available academia industry real i... | riscv-spec-20191213 | segment0 | [] | Chapter 1 | RV32ISPEC.pdf#segment0 | 2023-09-18 14:50:12 |
riscv hardware platform contain one riscvcompatible processing cores to gether nonriscvcompatible cores fixedfunction accelerators various physical mem ory structures io devices interconnect structure allow components communicate component termed core contains independent instruction fetch unit riscv compatible c... | riscv-spec-20191213 | segment1 | [] | 1.1 RISC-V Hardware Platform Terminology | RV32ISPEC.pdf#segment1 | 2023-09-18 14:50:12 |
behavior riscv program depends execution environment runs riscv execution environment interface eei defines initial state program number type harts environment including privilege modes supported harts accessibility attributes memory io regions behavior legal instructions exe cuted hart ie isa one component eei... | riscv-spec-20191213 | segment2 | [] | 1.2 RISC-V Software Execution Environments and Harts | RV32ISPEC.pdf#segment2 | 2023-09-18 14:50:12 |
riscv isa defined base integer isa must present implementation plus optional extensions base isa base integer isas similar early risc processors except branch delay slots support optional variablelength instruction encodings base carefully restricted minimal set instructions sufficient provide reasonable target com... | riscv-spec-20191213 | segment3 | [] | 1.3 RISC-V ISA Overview | RV32ISPEC.pdf#segment3 | 2023-09-18 14:50:13 |
riscv hart single byteaddressable address space 2xlen bytes memory accesses word memory defined 32 bits 4 bytes correspondingly halfword 16 bits 2 bytes doubleword 64 bits 8 bytes quadword 128 bits 16 bytes memory address space circular byte address 2xlen 1 adjacent byte address zero accordingly memory... | riscv-spec-20191213 | segment4 | [] | 1.4 Memory | RV32ISPEC.pdf#segment4 | 2023-09-18 14:50:13 |
base riscv isa fixedlength 32bit instructions must naturally aligned 32bit boundaries however standard riscv encoding scheme designed support isa extensions variablelength instructions instruction number 16bit instruction parcels length parcels naturally aligned 16bit boundaries standard compressed isa extension de... | riscv-spec-20191213 | segment5 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%201.1.jpg?raw=true"
] | 1.5 Base Instruction-Length Encoding | RV32ISPEC.pdf#segment5 | 2023-09-18 14:50:14 |
use term exception refer unusual condition occurring run time associated instruction current riscv hart use term interrupt refer external asynchronous event may cause riscv hart experience unexpected transfer control use term trap refer transfer control trap handler caused either exception interrupt instruction desc... | riscv-spec-20191213 | segment6 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%201.1.jpg?raw=true"
] | 1.6 Exceptions, Traps, and Interrupts | RV32ISPEC.pdf#segment6 | 2023-09-18 14:50:14 |
architecture fully describes implementations must constraints may cases architecture intentionally constrain implementations term unspecified explicitly used term unspecified refers behavior value intentionally unconstrained definition behaviors values open extensions platform standards implementations extension... | riscv-spec-20191213 | segment7 | [] | 1.7 UNSPECIFIED Behaviors and Values | RV32ISPEC.pdf#segment7 | 2023-09-18 14:50:14 |
rv32i base integer instruction set version 21 chapter describes version 20 rv32i base integer instruction set rv32i designed sufficient form compiler target support modern operating system environments isa also designed reduce hardware required minimal implementation rv32i contains 40 unique instructions though si... | riscv-spec-20191213 | segment8 | [] | Chapter 2 | RV32ISPEC.pdf#segment8 | 2023-09-18 14:50:14 |
figure 21 shows unprivileged state base integer isa rv32i 32 x registers 32 bits wide ie xlen32 register x0 hardwired bits equal 0 general purpose registers x1x31 hold values various instructions interpret collection boolean values two complement signed binary integers unsigned binary integers one additional un... | riscv-spec-20191213 | segment9 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.1.jpg?raw=true"
] | 2.1 Programmers’ Model for Base Integer ISA | RV32ISPEC.pdf#segment9 | 2023-09-18 14:50:14 |
base rv32i isa four core instruction formats risu shown figure 22 fixed 32 bits length must aligned fourbyte boundary memory instructionaddressmisaligned exception generated taken branch unconditional jump target address fourbyte aligned exception reported branch jump instruction target instruction instructiona... | riscv-spec-20191213 | segment10 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.2.jpg?raw=true"
] | 2.2 Base Instruction Formats | RV32ISPEC.pdf#segment10 | 2023-09-18 14:50:14 |
two variants instruction formats bj based handling imme diates shown figure 23 difference b formats 12bit immediate field used encode branch offsets multiples 2 b f ormat instead shifting bits instructionencoded immediate left one hardware conventionally done middle bits imm 101 sign bit stay fixed p ositions ... | riscv-spec-20191213 | segment11 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.3.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%202.4.jpg?raw=true"
] | 2.3 Immediate Encoding Variants | RV32ISPEC.pdf#segment11 | 2023-09-18 14:50:14 |
integer computational instructions operate xlen bits values held integer register file integer computational instructions either encoded registerimmediate operations using itype format registerregister operations using rtype format destination register rd registerimmediate registerregister instructions integer compu... | riscv-spec-20191213 | segment12 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(2.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(2.4).jpg?raw=true",
"https://github.com/merle... | 2.4 Integer Computational Instructions | RV32ISPEC.pdf#segment12 | 2023-09-18 14:50:15 |
rv32i provides two types control transfer instructions unconditional jumps conditional branches control transfer instructions rv32i architecturally visible delay slots unconditional jumps jump link jal instruction uses jtype format jimmediate encodes signed offset multiples 2 bytes offset signextended added addr... | riscv-spec-20191213 | segment13 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(2.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%202.1.jpg?raw=true",
"https://github.com/merle... | 2.5 Control Transfer Instructions | RV32ISPEC.pdf#segment13 | 2023-09-18 14:50:15 |
rv32i loadstore architecture load store instructions access memory arithmetic instructions operate cpu registers rv32i provides 32bit address space byteaddressed eei define portions address space legal access instructions eg addresses might read support word access loads destination x0 must still raise exceptio... | riscv-spec-20191213 | segment14 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.6).jpg?raw=true"
] | 2.6 Load and Store Instructions | RV32ISPEC.pdf#segment14 | 2023-09-18 14:50:16 |
fence instruction used order device io memory accesses viewed risc v harts external devices coprocessors combination device input device output memory reads r memory writes w may ordered respect combination informally riscv hart external device observe operation successor set following fence operation pre... | riscv-spec-20191213 | segment15 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.7).jpg?raw=true"
] | 2.7 Memory Ordering Instructions | RV32ISPEC.pdf#segment15 | 2023-09-18 14:50:16 |
system instructions used access system functionality might require privileged ac cess encoded using itype instruction format divided two main classes atomically readmodifywrite control status registers csrs potentially privileged instructions csr instructions described chapter 9 base unprivileged instructions de... | riscv-spec-20191213 | segment16 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(2.8).jpg?raw=true"
] | 2.8 Environment Call and Breakpoints | RV32ISPEC.pdf#segment16 | 2023-09-18 14:50:16 |
rv32i reserves large encoding space hint instructions usually used commu nicate performance hints microarchitecture hints encoded integer computational instructions rdx0 hence like nop instruction hints change architecturally visible state except advancing pc applicable performance counters implementa tions alwa... | riscv-spec-20191213 | segment17 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%202.3.jpg?raw=true"
] | 2.9 HINT Instructions | RV32ISPEC.pdf#segment17 | 2023-09-18 14:50:16 |
zifencei instructionfetch fence version 20 chapter defines zifencei extension includes fencei instruction provides explicit synchronization writes instruction memory instruction fetches hart currently instruction standard mechanism ensure stores visible hart also visible instruction fetches considered include ... | riscv-spec-20191213 | segment18 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(3).jpg?raw=true"
] | Chapter 3 | RV32ISPEC.pdf#segment18 | 2023-09-18 14:50:16 |
rv32e base integer instruction set version 19 chapter describes draft proposal rv32e base integer instruction set reduced version rv32i designed embedded systems change reduce number integer registers 16 chapter outlines differences rv32e rv32i read chapter 2 rv32e designed provide even smaller base core embedded m... | riscv-spec-20191213 | segment19 | [] | Chapter 4 | RV32ISPEC.pdf#segment19 | 2023-09-18 14:50:16 |
rv32e reduces integer register count 16 generalpurpose registers x0x15 x0 dedicated zero register found small rv32i core designs upper 16 registers consume around one quarter total area core excluding memories thus removal saves around 25 core area corresponding core power reduction change requires different c... | riscv-spec-20191213 | segment20 | [] | 4.1 RV32E Programmers’ Model | RV32ISPEC.pdf#segment20 | 2023-09-18 14:50:16 |
rv32e uses instructionset encoding rv32i except registers x0x15 provided future standard extensions make use instruction bits freed reduced registerspecifier fields available custom extensions rv32e combined current standard extensions defining f q exten sions 16entry floating point register file combined rv32e c... | riscv-spec-20191213 | segment21 | [] | 4.2 RV32E Instruction Set | RV32ISPEC.pdf#segment21 | 2023-09-18 14:50:17 |
rv64i base integer instruction set version 21 chapter describes rv64i base integer instruction set builds upon rv32i variant described chapter 2 chapter presents differences rv32i read conjunction earlier chapter | riscv-spec-20191213 | segment22 | [] | Chapter 5 | RV32ISPEC.pdf#segment22 | 2023-09-18 14:50:17 |
rv64i widens integer registers supported user address space 64 bits xlen64 figure 21 | riscv-spec-20191213 | segment23 | [] | 5.1 Register State | RV32ISPEC.pdf#segment23 | 2023-09-18 14:50:17 |
integer computational instructions operate xlenbit values additional instruction vari ants provided manipulate 32bit values rv64i indicated w suffix opcode w instructions ignore upper 32 bits inputs always produce 32bit signed values ie bits xlen1 31 equal compiler calling convention maintain invariant 32bit... | riscv-spec-20191213 | segment24 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(5.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(5.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(5.2).jpg?raw=true",
"https://github.com/merle... | 5.2 Integer Computational Instructions | RV32ISPEC.pdf#segment24 | 2023-09-18 14:50:17 |
rv64i extends address space 64 bits execution environment define portions address space legal access ld instruction loads 64bit value memory register rd rv64i lw instruction loads 32bit value memory signextends 64 bits storing register rd rv64i lwu instruction hand zeroextends 32bit value memory rv64i lh lhu def... | riscv-spec-20191213 | segment25 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(5.3).jpg?raw=true"
] | 5.3 Load and Store Instructions | RV32ISPEC.pdf#segment25 | 2023-09-18 14:50:17 |
instructions microarchitectural hints rv32i see section 29 also hints rv64i additional computational instructions rv64i expand standard custom hint encoding spaces table 51 lists rv64i hint code points 91 hint space reserved standard hints none presently defined remainder hint space reserved custom hints stand... | riscv-spec-20191213 | segment26 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%205.1.jpg?raw=true"
] | 5.4 HINT Instructions | RV32ISPEC.pdf#segment26 | 2023-09-18 14:50:17 |
rv128i base integer instruction set version 17 one mistake made computer design difficult re cover fromnot enough address bits memory addressing memory man agement bell strecker isca3 1976 chapter describes rv128i variant riscv isa supporting flat 128bit address space variant straightforward extrapolation existi... | riscv-spec-20191213 | segment27 | [] | Chapter 6 | RV32ISPEC.pdf#segment27 | 2023-09-18 14:50:17 |
standard extension integer multiplication division version 20 chapter describes standard integer multiplication division instruction extension named contains instructions multiply divide values held two integer registers separate integer multiply divide base simplify lowend implementations applications integer mu... | riscv-spec-20191213 | segment28 | [] | Chapter 7 | RV32ISPEC.pdf#segment28 | 2023-09-18 14:50:17 |
mul performs xlenbitxlenbit multiplication rs1 rs2 places lower xlen bits destination register mulh mulhu mulhsu perform multiplication re turn upper xlen bits full 2xlenbit product signedsigned unsignedunsigned signed rs1unsigned rs2 multiplication respectively high low bits product required recommended code ... | riscv-spec-20191213 | segment28 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(7.1).jpg?raw=true"
] | 7.1 Multiplication Operations | RV32ISPEC.pdf#segment28 | 2023-09-18 14:50:17 |
div divu perform xlen bits xlen bits signed unsigned integer division rs1 rs2 rounding towards zero rem remu provide remainder corresponding division operation rem sign result equals sign dividend signed unsigned division holds dividend divisor quotient remainder quotient remainder required division recommen... | riscv-spec-20191213 | segment29 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(7.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%207.1.jpg?raw=true"
] | 7.2 Division Operations | RV32ISPEC.pdf#segment29 | 2023-09-18 14:50:17 |
standard extension atomic instructions version 21 standard atomicinstruction extension named contains instructions atomically readmodifywrite memory support synchronization multiple riscv harts running memory space two forms atomic instruction provided loadreservedstore conditional instructions atomic fetchandop ... | riscv-spec-20191213 | segment30 | [] | Chapter 8 | RV32ISPEC.pdf#segment30 | 2023-09-18 14:50:18 |
base riscv isa relaxed memory model fence instruction used impose additional ordering constraints address space divided execution environment memory io domains fence instruction provides options order accesses one two address domains provide efficient support release consistency 5 atomic instruction two bits aq... | riscv-spec-20191213 | segment31 | [] | 8.1 Specifying Ordering of Atomic Instructions | RV32ISPEC.pdf#segment31 | 2023-09-18 14:50:18 |
complex atomic memory operations single memory word doubleword performed loadreserved lr storeconditional sc instructions lrw loads word address rs1 places signextended value rd registers reservation seta set bytes subsumes bytes addressed word scw conditionally writes word rs2 address rs1 scw succeeds reserva... | riscv-spec-20191213 | segment32 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(8.2).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%208.1.jpg?raw=true"
] | 8.2 Load-Reserved/Store-Conditional Instructions | RV32ISPEC.pdf#segment32 | 2023-09-18 14:50:18 |
standard extension defines constrained lrsc loops following properties loop comprises lrsc sequence code retry sequence case failure must comprise 16 instructions placed sequentially memory lrsc sequence begins lr instruction ends sc instruction dynamic code executed lr sc instructions contain instructions base ... | riscv-spec-20191213 | segment33 | [] | 8.3 Eventual Success of Store-Conditional Instructions | RV32ISPEC.pdf#segment33 | 2023-09-18 14:50:19 |
atomic memory operation amo instructions perform readmodifywrite operations mul tiprocessor synchronization encoded rtype instruction format amo in structions atomically load data value address rs1 place value register rd apply binary operator loaded value original value rs2 store result back address rs1 amos ei... | riscv-spec-20191213 | segment34 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(8.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%208.2.jpg?raw=true"
] | 8.4 Atomic Memory Operations | RV32ISPEC.pdf#segment34 | 2023-09-18 14:50:19 |
zicsr control status register csr instructions version 20 riscv defines separate address space 4096 control status registers associated hart chapter defines full set csr instructions operate csrs csrs primarily used privileged architecture several uses unprivi leged code including counters timers floatingpoint... | riscv-spec-20191213 | segment35 | [] | Chapter 9 | RV32ISPEC.pdf#segment35 | 2023-09-18 14:50:19 |
csr instructions atomically readmodifywrite single csr whose csr specifier encoded 12bit csr field instruction held bits 3120 immediate forms use 5bit zeroextended immediate encoded rs1 field csrrw atomic readwrite csr instruction atomically swaps values csrs integer registers csrrw reads old value csr zeroexten... | riscv-spec-20191213 | segment36 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(9.1).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%209.1.jpg?raw=true"
] | 9.1 CSR Instructions | RV32ISPEC.pdf#segment36 | 2023-09-18 14:50:19 |
counters riscv isas provide set 3264bit performance counters timers accessible via unprivileged xlen readonly csr registers 0xc000xc1f upper 32 bits accessed via csr registers 0xc800xc9f rv32 first three cycle time instret dedicated functions cycle count realtime clock instructionsretired respectively remai... | riscv-spec-20191213 | segment37 | [] | Chapter 10 | RV32ISPEC.pdf#segment37 | 2023-09-18 14:50:19 |
rv32i provides number 64bit readonly userlevel counters mapped 12 bit csr address space accessed 32bit pieces using csrrs instructions rv64i csr instructions manipulate 64bit csrs particular rdcycle rdtime rdinstret pseudoinstructions read full 64 bits cycle time instret counters hence rdcycleh rdtimeh rdi... | riscv-spec-20191213 | segment38 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(10.1).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%2010.1.jpg?raw=true"
] | 10.1 Base Counters and Timers | RV32ISPEC.pdf#segment38 | 2023-09-18 14:50:20 |
csr space allocated 29 additional unprivileged 64bit hardware performance coun ters hpmcounter3hpmcounter31 rv32 upper 32 bits performance counters accessible via additional csrs hpmcounter3hhpmcounter31h counters count platform specific events configured via additional privileged registers number width additional... | riscv-spec-20191213 | segment39 | [] | 10.2 Hardware Performance Counters | RV32ISPEC.pdf#segment39 | 2023-09-18 14:50:20 |
f standard extension singleprecision floatingpoint version 22 chapter describes standard instructionset extension singleprecision floatingpoint named f adds singleprecision floatingpoint computational instructions compliant ieee 7542008 arithmetic standard 7 f extension depends zicsr extension control status ... | riscv-spec-20191213 | segment40 | [] | Chapter 11 | RV32ISPEC.pdf#segment40 | 2023-09-18 14:50:20 |
f extension adds 32 floatingpoint registers f0f31 32 bits wide floatingpoint control status register fcsr contains operating mode exception status floatingpoint unit additional state shown figure 111 use term flen describe width floatingpoint registers riscv isa flen32 f singleprecision floatingpoint extension f... | riscv-spec-20191213 | segment41 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%2011.1.jpg?raw=true"
] | 11.1 F Register State | RV32ISPEC.pdf#segment41 | 2023-09-18 14:50:20 |
floatingpoint control status register fcsr riscv control status register csr 32bit readwrite register selects dynamic rounding mode floatingpoint arith metic operations holds accrued exception flags shown figure 112 fcsr register read written frcsr fscsr instructions assembler pseudoinstructions built underlying... | riscv-spec-20191213 | segment42 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/fig%2011.2.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.2.jpg?raw=true"
] | 11.2 Floating-Point Control and Status Register | RV32ISPEC.pdf#segment42 | 2023-09-18 14:50:20 |
except otherwise stated result floatingpoint operation nan canonical nan canonical nan positive sign significand bits clear except msb aka quiet bit singleprecision floatingpoint corresponds pattern 0x7fc00000 considered propagating nan payloads recommended standard decision would increased hardware cost mor... | riscv-spec-20191213 | segment43 | [] | 11.3 NaN Generation and Propagation | RV32ISPEC.pdf#segment43 | 2023-09-18 14:50:20 |
operations subnormal numbers handled accordance ieee 7542008 standard parlance ieee standard tininess detected rounding detecting tininess rounding results fewer spurious underflow signals | riscv-spec-20191213 | segment44 | [] | 11.4 Subnormal Arithmetic | RV32ISPEC.pdf#segment44 | 2023-09-18 14:50:20 |
floatingpoint loads stores use baseoffset addressing mode integer base isa base address register rs1 12bit signed byte offset flw instruction loads singleprecision floatingpoint value memory floatingpoint register rd fsw stores singleprecision value floatingpoint register rs2 memory flw fsw guaranteed execute atomi... | riscv-spec-20191213 | segment45 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.5).jpg?raw=true"
] | 11.5 Single-Precision Load and Store Instructions | RV32ISPEC.pdf#segment45 | 2023-09-18 14:50:20 |
floatingpoint arithmetic instructions one two source operands use rtype format opfp major opcode fadds fmuls perform singleprecision floatingpoint addition multiplication respectively rs1 rs2 fsubs performs singleprecision floating point subtraction rs2 rs1 fdivs performs singleprecision floatingpoint division rs1 ... | riscv-spec-20191213 | segment46 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.3.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.6).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(11.6).jpg?raw=true"
] | 11.6 Single-Precision Floating-Point Computational Instructions | RV32ISPEC.pdf#segment46 | 2023-09-18 14:50:21 |
floatingpointtointeger integertofloatingpoint conversion instructions encoded opfp major opcode space fcvtws fcvtls converts floatingpoint number floating point register rs1 signed 32bit 64bit integer respectively integer register rd fcvtsw fcvtsl converts 32bit 64bit signed integer respectively integer register ... | riscv-spec-20191213 | segment47 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.4.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.7).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(11.7).jpg?raw=true",
"https://github.com/me... | 11.7 Single-Precision Floating-Point Conversion and Move Instructions | RV32ISPEC.pdf#segment47 | 2023-09-18 14:50:21 |
floatingpoint compare instructions feqs flts fles perform specified comparison be tween floatingpoint registers rs1 rs2 rs1 rs2 rs1 rs2 writing 1 integer register rd condition holds 0 otherwise flts fles perform ieee 7542008 standard refers signaling comparisons set invalid operation exception flag eithe... | riscv-spec-20191213 | segment48 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.8).jpg?raw=true"
] | 11.8 Single-Precision Floating-Point Compare Instructions | RV32ISPEC.pdf#segment48 | 2023-09-18 14:50:21 |
fclasss instruction examines value floatingpoint register rs1 writes integer register rd 10bit mask indicates class floatingpoint number format mask described table 115 corresponding bit rd set property true clear otherwise bits rd cleared note exactly one bit rd set fclasss set floatingpoint exception flags | riscv-spec-20191213 | segment49 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(11.9).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2011.5.jpg?raw=true"
] | 11.9 Single-Precision Floating-Point Classify Instruction | RV32ISPEC.pdf#segment49 | 2023-09-18 14:50:21 |
standard extension doubleprecision floatingpoint version 22 chapter describes standard doubleprecision floatingpoint instructionset extension named adds doubleprecision floatingpoint computational instructions compliant ieee 7542008 arithmetic standard extension depends base singleprecision instruction subset f | riscv-spec-20191213 | segment50 | [] | Chapter 12 | RV32ISPEC.pdf#segment50 | 2023-09-18 14:50:21 |
extension widens 32 floatingpoint registers f0f31 64 bits flen64 fig ure 111 f registers hold either 32bit 64bit floatingpoint values described section 122 flen 32 64 128 depending f q extensions supported four different floatingpoint precisions supported including h f q | riscv-spec-20191213 | segment51 | [] | 12.1 D Register State | RV32ISPEC.pdf#segment51 | 2023-09-18 14:50:21 |
multiple floatingpoint precisions supported valid values narrower nbit types n flen represented lower n bits flenbit nan value process termed nanboxing upper bits valid nanboxed value must 1s valid nanboxed nbit values therefore appear negative quiet nans qnans viewed wider mbit value n flen operation writ... | riscv-spec-20191213 | segment52 | [] | 12.2 NaN Boxing of Narrower Values | RV32ISPEC.pdf#segment52 | 2023-09-18 14:50:21 |
fld instruction loads doubleprecision floatingpoint value memory floatingpoint register rd fsd stores doubleprecision value floatingpoint registers memory fld fsd guaranteed execute atomically effective address naturally aligned xlen64 fld fsd modify bits transferred particular payloads noncanonical nans preserved | riscv-spec-20191213 | segment53 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(12.3).jpg?raw=true"
] | 12.3 Double-Precision Load and Store Instructions | RV32ISPEC.pdf#segment53 | 2023-09-18 14:50:21 |
doubleprecision floatingpoint computational instructions defined analogously singleprecision counterparts operate doubleprecision operands produce double precision results | riscv-spec-20191213 | segment54 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.4).jpg?raw=true"
] | 12.4 Double-Precision Floating-Point Computational Instructions | RV32ISPEC.pdf#segment54 | 2023-09-18 14:50:21 |
floatingpointtointeger integertofloatingpoint conversion instructions encoded opfp major opcode space fcvtwd fcvtld converts doubleprecision floatingpoint number floatingpoint register rs1 signed 32bit 64bit integer respectively inte ger register rd fcvtdw fcvtdl converts 32bit 64bit signed integer respec tively ... | riscv-spec-20191213 | segment55 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(12.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(12.5).jpg?raw=true",
"https://github.com/me... | 12.5 Double-Precision Floating-Point Conversion and Move In- structions | RV32ISPEC.pdf#segment55 | 2023-09-18 14:50:21 |
doubleprecision floatingpoint compare instructions defined analogously single precision counterparts operate doubleprecision operands | riscv-spec-20191213 | segment56 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.6).jpg?raw=true"
] | 12.6 Double-Precision Floating-Point Compare Instructions | RV32ISPEC.pdf#segment56 | 2023-09-18 14:50:21 |
doubleprecision floatingpoint classify instruction fclassd defined analogously singleprecision counterpart operates doubleprecision operands | riscv-spec-20191213 | segment57 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(12.7).jpg?raw=true"
] | 12.7 Double-Precision Floating-Point Classify Instruction | RV32ISPEC.pdf#segment57 | 2023-09-18 14:50:21 |
q standard extension quadprecision floatingpoint version 22 chapter describes q standard extension 128bit quadprecision binary floatingpoint instructions compliant ieee 7542008 arithmetic standard quadprecision binary floatingpoint instructionset extension named q depends doubleprecision floating point extension ... | riscv-spec-20191213 | segment58 | [] | Chapter 13 | RV32ISPEC.pdf#segment58 | 2023-09-18 14:50:22 |
new 128bit variants loadfp storefp instructions added encoded new value funct3 width field flq fsq guaranteed execute atomically effective address naturally aligned xlen128 flq fsq modify bits transferred particular payloads noncanonical nans preserved | riscv-spec-20191213 | segment59 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.1).jpg?raw=true"
] | 13.1 Quad-Precision Load and Store Instructions | RV32ISPEC.pdf#segment59 | 2023-09-18 14:50:22 |
new supported format added format field instructions shown table 131 quadprecision floatingpoint c omputational nstructions efined alogously doubleprecision counterparts operate quadprecision operands produce quadprecision results | riscv-spec-20191213 | segment60 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2013.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.2).jpg?raw=true"
] | 13.2 Quad-Precision Computational Instructions | RV32ISPEC.pdf#segment60 | 2023-09-18 14:50:22 |
new floatingpointtointeger integertofloatingpoint conversion instructions added instructions defined analogously doubleprecisiontointeger integertodouble precision conversion instructions fcvtwq fcvtlq converts quadprecision floating point number signed 32bit 64bit integer respectively fcvtqw fcvtql con verts 32bit... | riscv-spec-20191213 | segment61 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(13.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(13.3).jpg?raw=true"
] | 13.3 Quad-Precision Convert and Move Instructions | RV32ISPEC.pdf#segment61 | 2023-09-18 14:50:22 |
quadprecision floatingpoint compare instructions defined analogously double precision counterparts operate quadprecision operands | riscv-spec-20191213 | segment62 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.4).jpg?raw=true"
] | 13.4 Quad-Precision Floating-Point Compare Instructions | RV32ISPEC.pdf#segment62 | 2023-09-18 14:50:22 |
quadprecision floatingpoint classify instruction fclassq defined analogously doubleprecision counterpart operates quadprecision operands | riscv-spec-20191213 | segment63 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(13.5).jpg?raw=true"
] | 13.5 Quad-Precision Floating-Point Classify Instruction | RV32ISPEC.pdf#segment63 | 2023-09-18 14:50:22 |
rvwmo memory consistency model version 01 chapter defines riscv memory consistency model memory consistency model set rules specifying values returned loads memory riscv uses memory model called rvwmo riscv weak memory ordering designed provide flexibility architects build highperformance scalable designs simult... | riscv-spec-20191213 | segment64 | [] | Chapter 14 | RV32ISPEC.pdf#segment64 | 2023-09-18 14:50:22 |
rvwmo memory model defined terms global memory order total ordering memory operations produced harts general multithreaded program many different possible executions execution corresponding global memory order global memory order defined primitive load store operations generated memory instructions subject constr... | riscv-spec-20191213 | segment65 | [] | 14.1 Definition of the RVWMO Memory Model | RV32ISPEC.pdf#segment65 | 2023-09-18 14:50:23 |
note read only csrs listed participate definition syntactic dependencies | riscv-spec-20191213 | segment65 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2014.1.jpg?raw=true"
] | 14.2 CSR Dependency Tracking Granularity | RV32ISPEC.pdf#segment65 | 2023-09-18 14:50:23 |
section provides concrete listing source destination registers instruction listings used definition syntactic dependencies section 141 term accumulating csr used describe csr source destination register carries dependency instructions carry dependency source register source registers column destination register ... | riscv-spec-20191213 | segment66 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(14.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(14.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(14.3).jpg?raw=true",
"https://github.com/me... | 14.3 Source and Destination Register Listings | RV32ISPEC.pdf#segment66 | 2023-09-18 14:50:23 |
l standard extension decimal floatingpoint version 00 chapter draft proposal ratified foundation chapter placeholder specification standard extension named l designed support decimal floatingpoint arithmetic defined ieee 7542008 standard | riscv-spec-20191213 | segment67 | [] | Chapter 15 | RV32ISPEC.pdf#segment67 | 2023-09-18 14:50:23 |
existing floatingpoint registers used hold 64bit 128bit decimal floatingpoint values existing floatingpoint load store instructions used move values memory due large opcode space required fused multiplyadd instructions decimal floating point instruction extension require five 25bit major opcodes 30bit encoding space | riscv-spec-20191213 | segment68 | [] | 15.1 Decimal Floating-Point Registers | RV32ISPEC.pdf#segment68 | 2023-09-18 14:50:23 |
c standard extension compressed instructions version 20 chapter describes current proposal riscv standard compressed instructionset extension named c reduces static dynamic code size adding short 16bit instruction encodings common operations c extension added base isas rv32 rv64 rv128 use generic term rvc ... | riscv-spec-20191213 | segment69 | [] | Chapter 16 | RV32ISPEC.pdf#segment69 | 2023-09-18 14:50:23 |
rvc uses simple compression scheme offers shorter 16bit versions common 32bit riscv instructions immediate address offset small one registers zero register x0 abi link register x1 abi stack pointer x2 destination register first source register identical registers used 8 popular ones c extension compati... | riscv-spec-20191213 | segment70 | [] | 16.1 Overview | RV32ISPEC.pdf#segment70 | 2023-09-18 14:50:23 |
table 161 shows nine compressed instruction formats cr ci css use 32 rvi registers ciw cl cs ca cb limited 8 table 162 lists popular registers correspond registers x8 x15 note separate version load store instructions use stack pointer base address register since saving restoring stack prevalent use ci css ... | riscv-spec-20191213 | segment71 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.2.jpg?raw=true"
] | 16.2 Compressed Instruction Formats | RV32ISPEC.pdf#segment71 | 2023-09-18 14:50:23 |
increase reach 16bit instructions datatransfer instructions use zeroextended immediates scaled size data bytes 4 words 8 double words 16 quad words rvc provides two variants loads stores one uses abi stack pointer x2 base address target data register reference one 8 base address registers one 8 data registers ... | riscv-spec-20191213 | segment72 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(16.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(16.3).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(16.3).jpg?raw=true",
"https://github.com/me... | 16.3 Load and Store Instructions | RV32ISPEC.pdf#segment72 | 2023-09-18 14:50:24 |
rvc provides unconditional jump instructions conditional branch instructions base rvi instructions offsets rvc control transfer instruction multiples 2 bytes cj performs unconditional control transfer offset signextended added pc form jump target address cj therefore target 2 kib range cj expands jal x0 offset ... | riscv-spec-20191213 | segment73 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(16.4).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(16.4).jpg?raw=true"
] | 16.4 Control Transfer Instructions | RV32ISPEC.pdf#segment73 | 2023-09-18 14:50:24 |
rvc provides several instructions integer arithmetic constant generation integer constantgeneration instructions two constantgeneration instructions use ci instruction format target integer register cli loads signextended 6bit immediate imm register rd cli expands addi rd x0 imm 50 cli valid rdx0 code points... | riscv-spec-20191213 | segment74 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra1(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra2(16.5).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/extra3(16.5).jpg?raw=true",
"https://github.com/me... | 16.5 Integer Computational Instructions | RV32ISPEC.pdf#segment74 | 2023-09-18 14:50:25 |
implementations support c extension compressed forms instructions per mitted inside constrained lrsc sequences described section 83 also permitted inside constrained lrsc sequences implication implementation claims support c extensions must ensure lrsc sequences containing valid c instructions eventually complete | riscv-spec-20191213 | segment75 | [] | 16.6 Usage of C Instructions in LR/SC Sequences | RV32ISPEC.pdf#segment75 | 2023-09-18 14:50:25 |
portion rvc encoding space reserved microarchitectural hints like hints rv32i base isa see section 29 instructions modify architectural state except advancing pc applicable performance counters hints executed noops implementations ignore rvc hints encoded computational instructions modify architectural state ei... | riscv-spec-20191213 | segment76 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.3.jpg?raw=true"
] | 16.7 HINT Instructions | RV32ISPEC.pdf#segment76 | 2023-09-18 14:50:25 |
table 164 shows map major opcodes rvc row table corresponds one quadrant encoding space last quadrant two leastsignificant bits set corresponds instructions wider 16 bits including base isas several instructions valid certain operands invalid marked either res indicate opcode reserved future standard extensions... | riscv-spec-20191213 | segment77 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.4.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.5.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2016.6.jpg?raw=true",
"https://github.com/me... | 16.8 RVC Instruction Set Listings | RV32ISPEC.pdf#segment77 | 2023-09-18 14:50:25 |
b standard extension bit manipulation version 00 chapter placeholder future standard extension provide bit manipulation instruc tions including instructions insert extract test bit fields rotations funnel shifts bit byte permutations although bit manipulation instructions effective application domains particu... | riscv-spec-20191213 | segment78 | [] | Chapter 17 | RV32ISPEC.pdf#segment78 | 2023-09-18 14:50:25 |
j standard extension dynamically translated languages version 00 chapter placeholder future standard extension support dynamically translated languages many popular languages usually implemented via dynamic translation including java javascript languages benefit additional isa support dynamic checks garbage collec... | riscv-spec-20191213 | segment79 | [] | Chapter 18 | RV32ISPEC.pdf#segment79 | 2023-09-18 14:50:25 |
standard extension transactional memory version 00 chapter placeholder future standard extension provide transactional memory operations despite much research last twenty years initial commercial implementations still much debate best way support atomic operations involving multiple addresses current thoughts incl... | riscv-spec-20191213 | segment80 | [] | Chapter 19 | RV32ISPEC.pdf#segment80 | 2023-09-18 14:50:25 |
p standard extension packedsimd instructions version 02 discussions 5th riscv workshop indicated desire drop packedsimd proposal floatingpoint registers favor standardizing v extension large floatingpoint simd operations however interest packedsimd fixedpoint operations use integer registers small riscv implementat... | riscv-spec-20191213 | segment81 | [] | Chapter 20 | RV32ISPEC.pdf#segment81 | 2023-09-18 14:50:25 |
v standard extension vector operations version 07 current working group draft hosted https githubcomriscvriscvvspec base vector extension intended provide general support dataparallel execution within 32bit instruction encoding space later vector extensions supporting richer functionality certain domains | riscv-spec-20191213 | segment82 | [] | Chapter 21 | RV32ISPEC.pdf#segment82 | 2023-09-18 14:50:25 |
zam standard extension misaligned atomics v01 chapter defines zam extension extends extension standardizing support misaligned atomic memory operations amos platforms implementing zam misaligned amos need execute atomically respect accesses including nonatomic loads stores address size precisely execut... | riscv-spec-20191213 | segment83 | [] | Chapter 22 | RV32ISPEC.pdf#segment83 | 2023-09-18 14:50:25 |
ztso standard extension total store ordering v01 chapter defines ztso extension riscv total store ordering rvtso memory consistency model rvtso defined delta rvwmo defined chapter 141 ztso extension meant facilitate porting code originally written x86 sparc architectures use tso default also supports implemen... | riscv-spec-20191213 | segment84 | [] | Chapter 23 | RV32ISPEC.pdf#segment84 | 2023-09-18 14:50:25 |
rv3264g instruction set listings one goal riscv project used stable software development target purpose define combination base isa rv32i rv64i plus selected standard extensions imafd zicsr zifencei generalpurpose isa use abbreviation g imafdzicsr zifencei combination instructionset extensions chapter prese... | riscv-spec-20191213 | segment85 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(1).jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2024.2(2).jpg?raw=true",
"https://github.... | Chapter 24 | RV32ISPEC.pdf#segment85 | 2023-09-18 14:50:25 |
riscv assembly programmer handbook chapter placeholder assembly programmer manual table 251 lists assembler mnemonics x f registers role first standard calling convention may future different calling conventions note registers x1 x2 x5 special meanings encoded standard isa andor compressed extension tables 252 ... | riscv-spec-20191213 | segment86 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2025.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2025.2.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2025.3.jpg?raw=true"
] | Chapter 25 | RV32ISPEC.pdf#segment86 | 2023-09-18 14:50:25 |
extending riscv addition supporting standard generalpurpose software development another goal riscv provide basis specialized instructionset extensions customized accelerators instruction encoding spaces optional variablelength instruction encoding designed make easier leverage software development effort standard is... | riscv-spec-20191213 | segment87 | [
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2026.1.jpg?raw=true",
"https://github.com/merledu/rv-spidercrab/blob/Data_Analyzer/images/Table%2026.2.jpg?raw=true"
] | Chapter 26 | RV32ISPEC.pdf#segment87 | 2023-09-18 14:50:25 |
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