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ML Foundations Development 141

ERROR: type should be string, got "https://superuser.com/questions/1735122/why-are-most-of-the-common-processors-bit-counts-powers-of-2/1735399#1735399 and other answers discuss some of the engineering problems you'd have with e.g. 24-bit words on a byte-addressable machine. (24-bit DSPs use word-addressable memory) - some 3-byte words will span wider boundaries, differing in higher bits of the address. But CPU caches and memory systems really want to group binary addresses by ignoring some low bits, not by doing a full division.\r\n\r\nIn algorithm terms, this is optimization of `i / sizeof(int)` into a right shift for unsigned `i`, and `i * sizeof(int)` into a left shift.\r\n\r\nAnother algorithm where this is relevant is a bit-array: given an integer bit-index, you need to break that up into a byte index or word index, and a bit number within the byte (to use as a shift count).\r\n\r\n```\r\n#include <limits>\r\nint get_bit(unsigned int *bit_array, size_t n)\r\n{\r\n size_t element_idx = n / std::numeric_limits<unsigned int>::digits;\r\n int bit_idx = n % std::numeric_limits<unsigned int>::digits;\r\n unsigned chunk = bit_array[element_idx];\r\n return (chunk >> bit_idx) & 1;\r\n}\r\n```\r\n\r\nWhen [`numeric_limits<unsigned int>::digits`][1] is a power of 2, like 32 on typical C++ implementations, this unsigned division and remainder become simple right-shift and bitwise AND, like `n >> 5` and `n & 31`.\r\n\r\nThis wouldn't be the case for 24-bit `unsigned int`, for example, unless you choose to only use 16 of the 24 bits per `unsigned int`. Division by a constant `24` or `3` is not *very* expensive if you have a fast multiplier, but it's non-trivial.\r\n\r\nIn hardware it's even more significant: splitting a value into multiple fields is literally just wiring. But for `n%24`, the remainder depends on all 24 bits, not just the low 5 bits, as well as requiring some significant computation.\r\n\r\n----\r\n\r\n### `std::vector`'s `.size()` member function, and indexing\r\n\r\nAnother more widely used data structure that benefits from it being very cheap to convert between element index and addresses is **[C++'s `std::vector<T>`, a dynamic array][2] that knows its size and can reallocate when push_back exceeds the current capacity.** Typical implementations have 3 pointer members, perhaps named `T *m_begin`, `m_end`, and `m_capacity`.\r\n\r\nThe API includes `.begin()` and `.data()` which are trivial, just return the the start pointer. Similarly `.end()` can just return the end pointer. (C++ library functions that loop over a range take a start and end pointer, rather than a pointer + length). `.push_back` can increment `m_end += sizeof(T)` and check `m_end < m_capacity` is still true. (The size in bytes to pass to allocator functions can be obtained by casting to `char*` before subtracting.) None of that benefits from `sizeof(T)` being a power of 2, which is good for use-cases with T = an odd sized struct.\r\n\r\nBut `std::vector` also has a `.size()` API, typically implemented as `return end - begin;`. In C++, subtracting pointers returns the distance in elements, not bytes, so in asm it typically looks like `sub r0, r1` / `sra r0, 2` or something to arithmetic right shift the subtraction result to scale by `sizeof(T)`. If `sizeof(T)` isn't a power of 2, a right shift won't work for this division. (It is at least a compile-time constant [so a multiply and shift can do the trick][3].)\r\n\r\nIt's not rare for code to do `for (size_t i = 0 ; i < vec.size() ; i++) do stuff with vec[i]`, or to use `.size()` for other things. Compilers might transform this loop into a pointer increment, avoiding the division by `sizeof(vec[0])`, but some uses of `.size()` won't optimize away.\r\n\r\nA non-power-of-2 `sizeof(T)` for common primitive types like `int` and `int *` would make some uses of vectors of those types less efficient. (But implementations would probably keep the 3-pointer design, rather than needing to multiply by `sizeof(T)` more often with one pointer and size_t length, capacity.\r\n\r\nIt would also mean `alignof(int)` had to be `1`, unless an implementation padded 3-byte `int` to a larger size. Unless you redefine alignment to mean multiple-of-3 instead of multiple-of-2.\r\n\r\n\r\nAlso, **array indexing** by an integer is normally just a left-shift to multiply by `sizeof(T)` to get a byte offset.\r\n\r\nPerhaps such a machine would include scaled-index addressing modes so asm that could scale by 3 and 6, with a shift+add like `i + (i<<1)` instead of just a shift. For example current x86-64 can do `mov eax, [rdi + rcx*4]`. (The asm syntax is a multiply, but the only valid multipliers are 1, 2, 4, and 8; the machine code uses a 2-bit shift count.) So a 24-bit machine might allow `[rx + ry * 3]` or `*6` or `*12`. Otherwise software would need to do more operations to generate addresses.\r\n\r\nMany RISCs like MIPS and RISC-V only have 1-register addressing modes so scaling needs software, but maybe they'd provide a single instruction scale-by-3 for address-generation. (Maybe also including a shift count to scale by 6 or 12 or whatever.) `3` only has two set bits, so a fixed shift (trivial in hardware) and an adder will do the trick.\r\n\r\nDividing by 3 is expensive, though.\r\n\r\nIf the caches on a byte-addressable machine with odd-sized words was still sized to a power-of-2 number of bytes, it could work a lot like a modern x86 which allows efficient unaligned loads/stores, with fairly efficient handling of cases where a load spans the boundary between two cache lines or even pages. Addresses break into offset-within-cache-line vs. index vs. tag by treating the binary address as separate fields.\r\n\r\nIf cache line sizes were a multiple of 3, like 48 bytes, none of the `int` in an array will span a cache-line boundary. (As long as the start of the array is \"aligned\" to a multiple-of-3 address!) But if addresses are still binary numbers, cache indexing is no longer simple. `index = (address / 48) % num_sets`, and `tag = (address / 48) / num_sets`. (Assuming for simplicity physical index and tagging.) Paging has a similar problem, power of 2 page size vs. multiple of 3.\r\n\r\n(This is the same problem as for a bit-array where the `unsigned int` chunks aren't a power-of-2 size.)\r\n\r\n [1]: https://en.cppreference.com/w/cpp/types/numeric_limits/digits\r\n [2]: https://en.cppreference.com/w/cpp/container/vector\r\n [3]: https://stackoverflow.com/questions/41183935/why-does-gcc-use-multiplication-by-a-strange-number-in-implementing-integer-divi"