id int64 0 328k | repository_name stringlengths 7 58 | file_path stringlengths 9 302 | class_name stringlengths 5 256 | human_written_code stringlengths 16 2.16M | class_skeleton stringlengths 18 1.49M ⌀ | total_program_units int64 1 1.76k | total_doc_str int64 0 771 | AvgCountLine float64 0 7.89k | AvgCountLineBlank float64 0 297 | AvgCountLineCode float64 0 7.89k | AvgCountLineComment float64 0 7.89k | AvgCyclomatic float64 0 130 | CommentToCodeRatio float64 0 168 | CountClassBase float64 0 40 | CountClassCoupled float64 0 583 | CountClassCoupledModified float64 0 575 | CountClassDerived float64 0 5.35k | CountDeclInstanceMethod float64 0 529 | CountDeclInstanceVariable float64 0 296 | CountDeclMethod float64 0 599 | CountDeclMethodAll float64 0 1.12k | CountLine float64 1 40.4k | CountLineBlank float64 0 8.16k | CountLineCode float64 1 25.7k | CountLineCodeDecl float64 1 8.15k | CountLineCodeExe float64 0 24.2k | CountLineComment float64 0 16.5k | CountStmt float64 1 9.71k | CountStmtDecl float64 1 8.15k | CountStmtExe float64 0 9.69k | MaxCyclomatic float64 0 759 | MaxInheritanceTree float64 0 16 | MaxNesting float64 0 34 | SumCyclomatic float64 0 2.9k |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
326,500 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/agents/circuit_creator_agent.py | circuit_synth.ai_integration.claude.agents.circuit_creator_agent.CircuitCreatorAgent | from datetime import datetime
from typing import Any, Dict, List, Optional
from pathlib import Path
import json
from ..manufacturing.jlcpcb import search_jlc_components_web
class CircuitCreatorAgent:
"""
Agent that helps users create and register pre-made circuits.
Workflow:
1. Gather requirements fro... |
class CircuitCreatorAgent:
'''
Agent that helps users create and register pre-made circuits.
Workflow:
1. Gather requirements from user
2. Suggest components with JLCPCB availability
3. Generate circuit Python code
4. Validate design (electrical rules, availability)
5. Register circuit ... | 19 | 19 | 33 | 4 | 23 | 6 | 3 | 0.28 | 0 | 9 | 0 | 0 | 18 | 3 | 18 | 18 | 616 | 88 | 422 | 98 | 383 | 120 | 171 | 71 | 152 | 11 | 0 | 3 | 58 |
326,501 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/agents/circuit_project_creator.py | circuit_synth.ai_integration.claude.agents.circuit_project_creator.CircuitProjectCreator | from ..agent_registry import register_agent
@register_agent('circuit-project-creator')
class CircuitProjectCreator:
"""Master orchestrator agent for circuit project generation workflow"""
description = 'Master orchestrator for complete circuit project generation from natural language prompts'
expertise_are... | @register_agent('circuit-project-creator')
class CircuitProjectCreator:
'''Master orchestrator agent for circuit project generation workflow'''
def get_system_prompt(self) -> str:
pass
def get_allowed_tools(self):
pass | 4 | 1 | 176 | 32 | 113 | 37 | 1 | 0.32 | 0 | 1 | 0 | 0 | 2 | 0 | 2 | 2 | 358 | 66 | 228 | 5 | 225 | 74 | 7 | 5 | 4 | 1 | 0 | 0 | 2 |
326,502 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/agents/circuit_syntax_fixer.py | circuit_synth.ai_integration.claude.agents.circuit_syntax_fixer.CircuitSyntaxFixer | from ..agent_registry import register_agent
@register_agent('circuit-syntax-fixer')
class CircuitSyntaxFixer:
"""Agent that fixes syntax errors in circuit-synth Python code"""
description = 'Circuit syntax specialist that fixes code errors while preserving design intent'
expertise_area = 'Circuit Code Synt... | @register_agent('circuit-syntax-fixer')
class CircuitSyntaxFixer:
'''Agent that fixes syntax errors in circuit-synth Python code'''
def get_system_prompt(self) -> str:
pass
def get_allowed_tools(self):
pass | 4 | 1 | 177 | 35 | 97 | 52 | 1 | 0.53 | 0 | 1 | 0 | 0 | 2 | 0 | 2 | 2 | 361 | 72 | 197 | 5 | 194 | 105 | 7 | 5 | 4 | 1 | 0 | 0 | 2 |
326,503 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/agents/circuit_validation_agent.py | circuit_synth.ai_integration.claude.agents.circuit_validation_agent.CircuitValidationAgent | from ..agent_registry import register_agent
@register_agent('circuit-validation-agent')
class CircuitValidationAgent:
"""Agent that validates circuit-synth Python code by execution"""
description = 'Circuit validation specialist that tests generated code execution'
expertise_area = 'Circuit Code Validation... | @register_agent('circuit-validation-agent')
class CircuitValidationAgent:
'''Agent that validates circuit-synth Python code by execution'''
def get_system_prompt(self) -> str:
pass
def get_allowed_tools(self):
pass | 4 | 1 | 129 | 27 | 78 | 30 | 1 | 0.38 | 0 | 1 | 0 | 0 | 2 | 0 | 2 | 2 | 265 | 56 | 158 | 5 | 155 | 60 | 7 | 5 | 4 | 1 | 0 | 0 | 2 |
326,504 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/agents/contributor_agent.py | circuit_synth.ai_integration.claude.agents.contributor_agent.ContributorAgent | from typing import Any, Dict, List, Optional
from ..agent_registry import register_agent
@register_agent('contributor')
class ContributorAgent:
"""
Specialized Claude Code agent for circuit-synth contributors.
This agent helps new and existing contributors:
- Understand the project architecture and co... | @register_agent('contributor')
class ContributorAgent:
'''
Specialized Claude Code agent for circuit-synth contributors.
This agent helps new and existing contributors:
- Understand the project architecture and codebase
- Follow coding conventions and best practices
- Write proper tests using TD... | 13 | 11 | 33 | 3 | 28 | 3 | 2 | 0.12 | 0 | 4 | 0 | 0 | 11 | 3 | 11 | 11 | 385 | 43 | 306 | 34 | 283 | 38 | 49 | 23 | 37 | 6 | 0 | 2 | 23 |
326,505 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/circuit_design_rules.py | circuit_synth.ai_integration.claude.circuit_design_rules.CircuitDesignRules | from typing import Dict, List, Optional, Tuple
class CircuitDesignRules:
"""
Comprehensive circuit design rules knowledge base.
This class provides essential design rules that must be followed
by all circuit design agents to ensure robust, manufacturable designs.
"""
@staticmethod
def get... |
class CircuitDesignRules:
'''
Comprehensive circuit design rules knowledge base.
This class provides essential design rules that must be followed
by all circuit design agents to ensure robust, manufacturable designs.
'''
@staticmethod
def get_critical_rules() -> List[DesignRule]:
''... | 13 | 7 | 60 | 1 | 57 | 2 | 3 | 0.05 | 0 | 4 | 3 | 0 | 0 | 0 | 6 | 6 | 376 | 13 | 347 | 17 | 332 | 16 | 31 | 9 | 24 | 11 | 0 | 3 | 16 |
326,506 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/circuit_design_rules.py | circuit_synth.ai_integration.claude.circuit_design_rules.ComponentRequirement | from typing import Dict, List, Optional, Tuple
from dataclasses import dataclass
@dataclass
class ComponentRequirement:
"""Specific component requirements for different applications"""
component_family: str
typical_values: Dict[str, str]
design_considerations: List[str]
common_mistakes: List[str] | @dataclass
class ComponentRequirement:
'''Specific component requirements for different applications'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 | 5 | 1 | 4 | 1 | 5 | 1 | 4 | 0 | 0 | 0 | 0 |
326,507 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/circuit_design_rules.py | circuit_synth.ai_integration.claude.circuit_design_rules.ComponentType | from enum import Enum
class ComponentType(Enum):
"""Component classification for design rules"""
MICROCONTROLLER = 'microcontroller'
POWER_MANAGEMENT = 'power_management'
ANALOG = 'analog'
DIGITAL = 'digital'
PASSIVE = 'passive'
CONNECTOR = 'connector'
SENSOR = 'sensor'
COMMUNICATIO... |
class ComponentType(Enum):
'''Component classification for design rules'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 49 | 11 | 1 | 9 | 9 | 8 | 1 | 9 | 9 | 8 | 0 | 4 | 0 | 0 |
326,508 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/circuit_design_rules.py | circuit_synth.ai_integration.claude.circuit_design_rules.DesignRule | from typing import Dict, List, Optional, Tuple
from dataclasses import dataclass
@dataclass
class DesignRule:
"""Represents a circuit design rule"""
rule_id: str
description: str
applies_to: List[ComponentType]
rationale: str
examples: List[str]
violations_cause: str
priority: str | @dataclass
class DesignRule:
'''Represents a circuit design rule'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 1 | 8 | 1 | 7 | 2 | 8 | 1 | 7 | 0 | 0 | 0 | 0 |
326,509 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/commands.py | circuit_synth.ai_integration.claude.commands.CircuitCommand | from typing import Dict, List
class CircuitCommand:
"""Represents a context-aware circuit design slash command"""
def __init__(self, name: str, description: str, content: str, allowed_tools: List[str]=None, argument_hint: str=None):
self.name = name
self.description = description
self.... |
class CircuitCommand:
'''Represents a context-aware circuit design slash command'''
def __init__(self, name: str, description: str, content: str, allowed_tools: List[str]=None, argument_hint: str=None):
pass
def to_markdown(self) -> str:
'''Convert to Claude Code slash command format'''
... | 3 | 2 | 13 | 2 | 11 | 1 | 2 | 0.09 | 0 | 1 | 0 | 0 | 2 | 5 | 2 | 2 | 29 | 5 | 22 | 16 | 12 | 2 | 13 | 9 | 10 | 3 | 0 | 1 | 4 |
326,510 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/claude/enhanced_circuit_agent.py | circuit_synth.ai_integration.claude.enhanced_circuit_agent.ValidatedCircuitGenerator | from ..validation import get_circuit_design_context, validate_and_improve_circuit
class ValidatedCircuitGenerator:
"""Circuit generator with integrated validation and context awareness."""
def __init__(self):
pass
async def generate_validated_circuit(self, prompt: str, circuit_type: str='general'... |
class ValidatedCircuitGenerator:
'''Circuit generator with integrated validation and context awareness.'''
def __init__(self):
pass
async def generate_validated_circuit(self, prompt: str, circuit_type: str='general') -> str:
'''
Generate circuit code with automatic validation and ... | 6 | 5 | 25 | 6 | 14 | 6 | 2 | 0.43 | 0 | 2 | 0 | 0 | 5 | 0 | 5 | 5 | 132 | 35 | 72 | 18 | 62 | 31 | 26 | 14 | 20 | 3 | 0 | 1 | 9 |
326,511 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/component_info/microcontrollers/modm_device_search.py | circuit_synth.ai_integration.component_info.microcontrollers.modm_device_search.MCUSearchResult | from dataclasses import dataclass
from typing import Dict, List, Optional, Set, Tuple
@dataclass
class MCUSearchResult:
"""Result from MCU search with complete device information."""
part_number: str
family: str
series: str
flash_size: int
ram_size: int
package: str
pin_count: int
t... | @dataclass
class MCUSearchResult:
'''Result from MCU search with complete device information.'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 14 | 5 | 13 | 3 | 14 | 5 | 13 | 0 | 0 | 0 | 0 |
326,512 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/component_info/microcontrollers/modm_device_search.py | circuit_synth.ai_integration.component_info.microcontrollers.modm_device_search.MCUSpecification | from typing import Dict, List, Optional, Set, Tuple
from dataclasses import dataclass
@dataclass
class MCUSpecification:
"""Microcontroller specification for search filtering."""
family: Optional[str] = None
series: Optional[str] = None
flash_min: Optional[int] = None
flash_max: Optional[int] = Non... | @dataclass
class MCUSpecification:
'''Microcontroller specification for search filtering.'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.83 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 14 | 1 | 12 | 12 | 11 | 10 | 12 | 12 | 11 | 0 | 0 | 0 | 0 |
326,513 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/component_info/microcontrollers/modm_device_search.py | circuit_synth.ai_integration.component_info.microcontrollers.modm_device_search.ModmDeviceSearch | import sys
from pathlib import Path
from typing import Dict, List, Optional, Set, Tuple
class ModmDeviceSearch:
"""
Intelligent microcontroller search using modm-devices database.
Provides comprehensive MCU search with specifications filtering,
peripheral requirements, and manufacturing constraints.
... |
class ModmDeviceSearch:
'''
Intelligent microcontroller search using modm-devices database.
Provides comprehensive MCU search with specifications filtering,
peripheral requirements, and manufacturing constraints.
'''
def __init__(self):
'''Initialize the device search system.'''
... | 15 | 15 | 29 | 5 | 20 | 5 | 6 | 0.26 | 0 | 11 | 2 | 0 | 14 | 2 | 14 | 14 | 426 | 79 | 278 | 90 | 250 | 72 | 208 | 78 | 190 | 15 | 0 | 8 | 89 |
326,514 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/logging_system.py | circuit_synth.ai_integration.logging_system.AgentExecutionLog | from datetime import datetime
from typing import Any, Dict, List, Optional
from dataclasses import asdict, dataclass
@dataclass
class AgentExecutionLog:
"""Structure for individual agent execution records"""
agent_name: str
session_id: str
start_time: datetime
end_time: Optional[datetime]
statu... | @dataclass
class AgentExecutionLog:
'''Structure for individual agent execution records'''
def to_dict(self) -> Dict[str, Any]:
'''Convert to dictionary with ISO datetime formatting'''
pass | 3 | 2 | 7 | 0 | 6 | 1 | 2 | 0.18 | 0 | 2 | 0 | 0 | 1 | 0 | 1 | 1 | 21 | 2 | 17 | 4 | 15 | 3 | 17 | 4 | 15 | 2 | 0 | 1 | 2 |
326,515 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/logging_system.py | circuit_synth.ai_integration.logging_system.CircuitWorkflowLogger | from typing import Any, Dict, List, Optional
from pathlib import Path
import json
from datetime import datetime
import uuid
class CircuitWorkflowLogger:
"""Master logging system for circuit generation workflow"""
def __init__(self, project_name: str, base_log_dir: str='logs'):
self.project_name = proj... |
class CircuitWorkflowLogger:
'''Master logging system for circuit generation workflow'''
def __init__(self, project_name: str, base_log_dir: str='logs'):
pass
def set_user_prompt(self, prompt: str):
'''Set the original user prompt for the workflow'''
pass
def start_agent_exec... | 14 | 13 | 26 | 4 | 19 | 4 | 3 | 0.21 | 0 | 8 | 1 | 0 | 13 | 8 | 13 | 13 | 358 | 64 | 250 | 81 | 221 | 53 | 133 | 60 | 119 | 11 | 0 | 3 | 40 |
326,516 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/circuit_diff.py | circuit_synth.ai_integration.memory_bank.circuit_diff.CircuitDiff | from typing import Any, Dict, List, Optional, Tuple
from dataclasses import dataclass
@dataclass
class CircuitDiff:
"""Complete diff analysis between two circuit states."""
commit_hash: str
commit_message: str
timestamp: str
component_changes: List[ComponentChange]
net_changes: List[NetChange]
... | @dataclass
class CircuitDiff:
'''Complete diff analysis between two circuit states.'''
def has_significant_changes(self) -> bool:
'''Check if this diff contains significant changes worth documenting.'''
pass | 3 | 2 | 10 | 0 | 9 | 1 | 1 | 0.13 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 20 | 2 | 16 | 2 | 14 | 2 | 9 | 2 | 7 | 1 | 0 | 0 | 1 |
326,517 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/circuit_diff.py | circuit_synth.ai_integration.memory_bank.circuit_diff.CircuitDiffAnalyzer | from typing import Any, Dict, List, Optional, Tuple
import subprocess
import json
from datetime import datetime
from pathlib import Path
class CircuitDiffAnalyzer:
"""Analyzes circuit changes between different versions."""
def __init__(self, board_path: str):
"""Initialize analyzer for specific board.... |
class CircuitDiffAnalyzer:
'''Analyzes circuit changes between different versions.'''
def __init__(self, board_path: str):
'''Initialize analyzer for specific board.'''
pass
def analyze_commit_changes(self, commit_hash: str) -> CircuitDiff:
'''Analyze circuit changes in a specific... | 14 | 14 | 32 | 4 | 25 | 3 | 4 | 0.13 | 0 | 10 | 3 | 0 | 13 | 3 | 13 | 13 | 436 | 68 | 325 | 101 | 294 | 43 | 182 | 76 | 165 | 10 | 0 | 4 | 54 |
326,518 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/circuit_diff.py | circuit_synth.ai_integration.memory_bank.circuit_diff.ComponentChange | from dataclasses import dataclass
from typing import Any, Dict, List, Optional, Tuple
@dataclass
class ComponentChange:
"""Represents a change to a component."""
reference: str
change_type: str
old_value: Optional[Dict[str, Any]] = None
new_value: Optional[Dict[str, Any]] = None
details: List[s... | @dataclass
class ComponentChange:
'''Represents a change to a component.'''
def __post_init__(self):
pass | 3 | 1 | 3 | 0 | 3 | 0 | 2 | 0.22 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 12 | 2 | 9 | 5 | 7 | 2 | 9 | 5 | 7 | 2 | 0 | 1 | 2 |
326,519 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/circuit_diff.py | circuit_synth.ai_integration.memory_bank.circuit_diff.NetChange | from dataclasses import dataclass
from typing import Any, Dict, List, Optional, Tuple
@dataclass
class NetChange:
"""Represents a change to a net connection."""
net_name: str
change_type: str
old_connections: List[str] = None
new_connections: List[str] = None
details: List[str] = None
def ... | @dataclass
class NetChange:
'''Represents a change to a net connection.'''
def __post_init__(self):
pass | 3 | 1 | 7 | 0 | 7 | 0 | 4 | 0.15 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 16 | 2 | 13 | 5 | 11 | 2 | 13 | 5 | 11 | 4 | 0 | 1 | 4 |
326,520 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/context.py | circuit_synth.ai_integration.memory_bank.context.ContextManager | import json
from typing import Any, Dict, List, Optional
from pathlib import Path
from datetime import datetime
class ContextManager:
"""Manages context switching between PCB variants."""
def __init__(self, project_root: Optional[str]=None):
"""Initialize with project root directory."""
self.p... |
class ContextManager:
'''Manages context switching between PCB variants.'''
def __init__(self, project_root: Optional[str]=None):
'''Initialize with project root directory.'''
pass
def switch_board(self, board_name: str) -> bool:
'''Switch context to specific PCB board.'''
... | 12 | 12 | 17 | 2 | 12 | 2 | 3 | 0.19 | 0 | 6 | 0 | 0 | 11 | 2 | 11 | 11 | 200 | 38 | 137 | 39 | 125 | 26 | 103 | 32 | 91 | 6 | 0 | 2 | 36 |
326,521 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/core.py | circuit_synth.ai_integration.memory_bank.core.MemoryBankManager | from .templates import TEMPLATE_FILES, generate_claude_md
from pathlib import Path
from typing import Any, Dict, List, Optional
from datetime import datetime
import json
class MemoryBankManager:
"""Manages memory-bank directory structure and file operations."""
def __init__(self, project_root: Optional[str]=N... |
class MemoryBankManager:
'''Manages memory-bank directory structure and file operations.'''
def __init__(self, project_root: Optional[str]=None):
'''Initialize with project root directory.'''
pass
def create_project_structure(self, project_name: str, board_names: List[str]=None) -> bool:
... | 10 | 10 | 28 | 6 | 19 | 4 | 3 | 0.22 | 0 | 6 | 0 | 0 | 9 | 2 | 9 | 9 | 261 | 59 | 169 | 47 | 157 | 38 | 108 | 35 | 98 | 5 | 0 | 3 | 28 |
326,522 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/core.py | circuit_synth.ai_integration.memory_bank.core.MemoryBankUpdater | from typing import Any, Dict, List, Optional
from datetime import datetime
import subprocess
from pathlib import Path
from .circuit_diff import CircuitDiffAnalyzer, format_diff_for_memory_bank
class MemoryBankUpdater:
"""Handles automatic updates to memory-bank files."""
def __init__(self, board_path: str):
... |
class MemoryBankUpdater:
'''Handles automatic updates to memory-bank files.'''
def __init__(self, board_path: str):
'''Initialize for specific board directory.'''
pass
def update_from_commit(self, commit_hash: str, commit_message: str='') -> bool:
'''Update memory-bank files based... | 14 | 14 | 29 | 4 | 21 | 4 | 5 | 0.2 | 0 | 7 | 1 | 0 | 13 | 2 | 13 | 13 | 395 | 68 | 278 | 85 | 256 | 56 | 176 | 65 | 162 | 11 | 0 | 3 | 59 |
326,523 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/memory_bank/git_integration.py | circuit_synth.ai_integration.memory_bank.git_integration.GitHookManager | from pathlib import Path
from typing import Any, Dict, Optional
class GitHookManager:
"""Manages git hooks for automatic memory-bank updates."""
def __init__(self, project_root: Optional[str]=None):
"""Initialize with project root directory."""
self.project_root = Path(project_root) if project... |
class GitHookManager:
'''Manages git hooks for automatic memory-bank updates.'''
def __init__(self, project_root: Optional[str]=None):
'''Initialize with project root directory.'''
pass
def install_post_commit_hook(self) -> bool:
'''Install post-commit git hook for automatic memor... | 4 | 4 | 25 | 4 | 18 | 4 | 3 | 0.24 | 0 | 4 | 0 | 0 | 3 | 3 | 3 | 3 | 80 | 14 | 54 | 15 | 50 | 13 | 38 | 11 | 34 | 4 | 0 | 3 | 9 |
326,524 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/ai_integration/plugins/ai_design_bridge.py | circuit_synth.ai_integration.plugins.ai_design_bridge.AIDesignBridge | from pathlib import Path
import sys
import os
from typing import Any, Dict, List, Optional
class AIDesignBridge:
"""
Bridge class to integrate circuit-synth with AI-powered design tools.
This class provides methods to:
1. Install AI design plugins into KiCad
2. Generate circuits with AI design ass... |
class AIDesignBridge:
'''
Bridge class to integrate circuit-synth with AI-powered design tools.
This class provides methods to:
1. Install AI design plugins into KiCad
2. Generate circuits with AI design assistance
3. Provide AI-assisted design feedback and optimization
4. Integrate with va... | 14 | 13 | 24 | 3 | 16 | 5 | 2 | 0.35 | 0 | 5 | 0 | 0 | 13 | 2 | 13 | 13 | 341 | 59 | 211 | 36 | 190 | 74 | 82 | 28 | 67 | 7 | 0 | 2 | 31 |
326,525 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/force_directed_layout.py | circuit_synth.component_placement.force_directed_layout.ForceDirectedLayout | from typing import Dict, List, Optional, Tuple
import math
import random
from .geometry import ComponentGeometryHandler, create_geometry_handler
from .placement import PlacementNode
class ForceDirectedLayout:
"""Force-directed layout algorithm for component placement."""
def __init__(self, attractive_force: f... |
class ForceDirectedLayout:
'''Force-directed layout algorithm for component placement.'''
def __init__(self, attractive_force: float=0.3, repulsive_force: float=100.0, damping: float=0.85, min_distance: float=15.0, max_iterations: int=100, convergence_threshold: float=0.1):
'''Initialize the force-dir... | 6 | 6 | 37 | 5 | 24 | 9 | 5 | 0.38 | 0 | 9 | 2 | 0 | 5 | 8 | 5 | 5 | 191 | 30 | 119 | 64 | 97 | 45 | 86 | 48 | 80 | 11 | 0 | 3 | 24 |
326,526 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/force_directed_layout.py | circuit_synth.component_placement.force_directed_layout.ForceVector | import math
from dataclasses import dataclass
@dataclass
class ForceVector:
"""Represents a 2D force vector."""
x: float
y: float
def __add__(self, other: 'ForceVector') -> 'ForceVector':
return ForceVector(self.x + other.x, self.y + other.y)
def scale(self, factor: float) -> 'ForceVector... | @dataclass
class ForceVector:
'''Represents a 2D force vector.'''
def __add__(self, other: 'ForceVector') -> 'ForceVector':
pass
def scale(self, factor: float) -> 'ForceVector':
pass
def magnitude(self) -> float:
pass | 5 | 1 | 2 | 0 | 2 | 0 | 1 | 0.11 | 0 | 1 | 0 | 0 | 3 | 0 | 3 | 3 | 14 | 4 | 9 | 4 | 5 | 1 | 9 | 4 | 5 | 1 | 0 | 0 | 3 |
326,527 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/geometry.py | circuit_synth.component_placement.geometry.ComponentDimensions | from dataclasses import dataclass
@dataclass
class ComponentDimensions:
"""Represents a component's dimensions."""
width: float
height: float
pin_grid: float = 2.54 | @dataclass
class ComponentDimensions:
'''Represents a component's dimensions.'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 4 | 2 | 3 | 2 | 4 | 2 | 3 | 0 | 0 | 0 | 0 |
326,528 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/geometry.py | circuit_synth.component_placement.geometry.ComponentGeometryHandler | import math
from typing import Dict, Optional, Tuple
class ComponentGeometryHandler:
"""Base class for handling component geometry and pin locations."""
def __init__(self, component_type: str):
"""Initialize with component type."""
self.component_type = component_type
self._dimensions ... |
class ComponentGeometryHandler:
'''Base class for handling component geometry and pin locations.'''
def __init__(self, component_type: str):
'''Initialize with component type.'''
pass
def _get_default_dimensions(self) -> ComponentDimensions:
'''Get default dimensions for this comp... | 6 | 6 | 9 | 1 | 6 | 2 | 1 | 0.37 | 0 | 4 | 2 | 2 | 5 | 3 | 5 | 5 | 52 | 11 | 30 | 21 | 20 | 11 | 26 | 17 | 20 | 2 | 0 | 1 | 7 |
326,529 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/geometry.py | circuit_synth.component_placement.geometry.PinLocation | from dataclasses import dataclass
@dataclass
class PinLocation:
"""Represents a pin's location relative to component center."""
x: float
y: float
side: str | @dataclass
class PinLocation:
'''Represents a pin's location relative to component center.'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 4 | 1 | 3 | 4 | 4 | 1 | 3 | 0 | 0 | 0 | 0 |
326,530 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/geometry.py | circuit_synth.component_placement.geometry.PowerSymbolGeometryHandler | class PowerSymbolGeometryHandler(ComponentGeometryHandler):
"""Geometry handler for power symbols."""
def _get_default_dimensions(self) -> ComponentDimensions:
"""Get power symbol dimensions."""
dims = ComponentDimensions(width=5.08, height=5.08)
print(f'Creating power symbol with dimen... | class PowerSymbolGeometryHandler(ComponentGeometryHandler):
'''Geometry handler for power symbols.'''
def _get_default_dimensions(self) -> ComponentDimensions:
'''Get power symbol dimensions.'''
pass
def _setup_pin_locations(self) -> None:
'''Set up power symbol pin locations.'''
... | 3 | 3 | 7 | 0 | 6 | 3 | 1 | 0.58 | 1 | 2 | 2 | 0 | 2 | 1 | 2 | 7 | 18 | 2 | 12 | 6 | 9 | 7 | 9 | 6 | 6 | 1 | 1 | 0 | 2 |
326,531 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/geometry.py | circuit_synth.component_placement.geometry.ResistorGeometryHandler | class ResistorGeometryHandler(ComponentGeometryHandler):
"""Geometry handler for resistor components."""
def _get_default_dimensions(self) -> ComponentDimensions:
"""Get resistor-specific dimensions."""
dims = ComponentDimensions(width=5.08, height=10.16)
print(f'Creating resistor with ... | class ResistorGeometryHandler(ComponentGeometryHandler):
'''Geometry handler for resistor components.'''
def _get_default_dimensions(self) -> ComponentDimensions:
'''Get resistor-specific dimensions.'''
pass
def _setup_pin_locations(self) -> None:
'''Set up resistor pin locations.'... | 3 | 3 | 9 | 0 | 7 | 4 | 1 | 0.53 | 1 | 2 | 2 | 0 | 2 | 1 | 2 | 7 | 21 | 2 | 15 | 7 | 12 | 8 | 12 | 7 | 9 | 1 | 1 | 0 | 2 |
326,532 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/placement.py | circuit_synth.component_placement.placement.ComponentPlacer | from typing import Dict, List, Optional, Set, Tuple
class ComponentPlacer:
"""Handles intelligent placement of components in a schematic."""
def __init__(self, base_x: float=77.47, base_y: float=44.45):
"""Initialize the component placer."""
self.base_x = base_x
self.base_y = base_y
... |
class ComponentPlacer:
'''Handles intelligent placement of components in a schematic.'''
def __init__(self, base_x: float=77.47, base_y: float=44.45):
'''Initialize the component placer.'''
pass
def analyze_connectivity(self, circuit: 'Circuit') -> None:
'''Build a connectivity gr... | 7 | 7 | 37 | 5 | 26 | 8 | 6 | 0.32 | 0 | 6 | 1 | 0 | 6 | 7 | 6 | 6 | 229 | 37 | 156 | 58 | 145 | 50 | 122 | 53 | 115 | 12 | 0 | 5 | 33 |
326,533 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/placement.py | circuit_synth.component_placement.placement.PlacementNode | from typing import Dict, List, Optional, Set, Tuple
from .geometry import ComponentGeometryHandler, create_geometry_handler
from dataclasses import dataclass
@dataclass
class PlacementNode:
"""Represents a component's placement information."""
component: 'Component'
x: float = 0
y: float = 0
rotati... | @dataclass
class PlacementNode:
'''Represents a component's placement information.'''
def __post_init__(self):
'''Initialize after creation.'''
pass | 3 | 2 | 8 | 0 | 7 | 1 | 3 | 0.13 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 19 | 2 | 15 | 8 | 13 | 2 | 13 | 8 | 11 | 3 | 0 | 1 | 3 |
326,534 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/wire_routing.py | circuit_synth.component_placement.wire_routing.WireRouter | from .placement import PlacementNode
from typing import Dict, List, Tuple
class WireRouter:
"""Handles routing of wires between components."""
def __init__(self):
"""Initialize the wire router."""
self.wire_segments: List[WireSegment] = []
def route_net(self, net: 'Net', placement_nodes: ... |
class WireRouter:
'''Handles routing of wires between components.'''
def __init__(self):
'''Initialize the wire router.'''
pass
def route_net(self, net: 'Net', placement_nodes: Dict[str, PlacementNode]) -> List[WireSegment]:
'''Route wires for a single net.'''
pass
... | 4 | 3 | 49 | 4 | 39 | 9 | 5 | 0.21 | 0 | 5 | 2 | 0 | 2 | 1 | 2 | 2 | 140 | 14 | 107 | 26 | 101 | 23 | 53 | 24 | 49 | 10 | 0 | 3 | 15 |
326,535 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/component_placement/wire_routing.py | circuit_synth.component_placement.wire_routing.WireSegment | from typing import Dict, List, Tuple
from dataclasses import dataclass
@dataclass
class WireSegment:
"""Represents a wire segment in the schematic."""
start: Tuple[float, float]
end: Tuple[float, float]
net_name: str
connected_pins: List[Tuple[str, str]] | @dataclass
class WireSegment:
'''Represents a wire segment in the schematic.'''
pass | 2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7 | 1 | 5 | 1 | 4 | 2 | 5 | 1 | 4 | 0 | 0 | 0 | 0 |
326,536 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/Circuit.py | circuit_synth.core.Circuit.Circuit | from .exception import CircuitSynthError, ValidationError
import re
import json
import tempfile
from .net import Net
from .reference_manager import ReferenceManager
import os
from ._logger import context_logger
from pathlib import Path
from typing import Any, Dict, List, Optional
from .netlist_exporter import NetlistEx... |
class Circuit:
def __init__(self, name=None, description=None, auto_comments=True):
pass
def validate_reference(self, ref: str) -> bool:
'''Check if reference is available in this circuit's scope'''
pass
def register_reference(self, ref: str) -> None:
'''Register a new re... | 35 | 23 | 21 | 2 | 14 | 5 | 2 | 0.38 | 0 | 20 | 10 | 0 | 26 | 10 | 27 | 27 | 615 | 85 | 398 | 121 | 342 | 150 | 229 | 100 | 189 | 9 | 0 | 6 | 69 |
326,537 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/Component.py | circuit_synth.core.Component.Component | from .pin import Pin
import re
from ._logger import context_logger
from .exception import CircuitSynthError, ComponentError, LibraryNotFound, ValidationError
from .decorators import get_current_circuit
from .simple_pin_access import PinGroup, SimplifiedPinAccess
from typing import Any, Dict, Iterator, List, Optional, U... | @dataclass
class Component(SimplifiedPinAccess):
'''
Represents an electronic component that references a KiCad symbol.
If multiple pins share the same name (e.g. "GND"), __getitem__ returns a PinGroup,
so something like:
comp["GND"] += net
will connect *all* GND pins to that net.
Additi... | 17 | 4 | 33 | 3 | 26 | 5 | 5 | 0.24 | 1 | 21 | 6 | 0 | 13 | 0 | 14 | 16 | 515 | 65 | 375 | 73 | 350 | 90 | 222 | 60 | 207 | 19 | 1 | 3 | 76 |
326,538 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/Net.py | circuit_synth.core.Net.Net | from typing import Optional, Set
from .exception import CircuitSynthError
from .decorators import get_current_circuit
class Net:
"""
A Net represents an electrical node (set of pins). The name may be auto-generated.
"""
def __init__(self, name: Optional[str]=None):
self.name = name
sel... |
class Net:
'''
A Net represents an electrical node (set of pins). The name may be auto-generated.
'''
def __init__(self, name: Optional[str]=None):
pass
@property
def pins(self):
pass
def __iadd__(self, other):
'''
net += pin => pin connects to this net
... | 6 | 2 | 9 | 1 | 6 | 2 | 3 | 0.33 | 0 | 8 | 2 | 0 | 4 | 2 | 4 | 4 | 45 | 9 | 27 | 12 | 20 | 9 | 22 | 11 | 16 | 5 | 0 | 3 | 10 |
326,539 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/Pin.py | circuit_synth.core.Pin.Pin | from ._logger import context_logger
from .net import Net
from typing import TYPE_CHECKING, Optional, Union
class Pin:
"""
Minimal Pin class for net connectivity.
- No dedicated geometry fields in the constructor
(x, y, length, orientation).
- We do accept **kwargs so geometry can be passed (and ... |
class Pin:
'''
Minimal Pin class for net connectivity.
- No dedicated geometry fields in the constructor
(x, y, length, orientation).
- We do accept **kwargs so geometry can be passed (and ignored by core),
but stored for schematic export.
'''
def __init__(self, name: str, num: str... | 17 | 7 | 13 | 1 | 9 | 3 | 3 | 0.43 | 0 | 12 | 3 | 0 | 11 | 8 | 11 | 11 | 172 | 25 | 104 | 37 | 84 | 45 | 63 | 30 | 50 | 12 | 0 | 6 | 33 |
326,540 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.AgentFactory | from abc import ABC, abstractmethod
class AgentFactory(ABC):
"""Factory for agents."""
pass |
class AgentFactory(ABC):
'''Factory for agents.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,541 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.CircuitModelFactory | from abc import ABC, abstractmethod
class CircuitModelFactory(ABC):
"""Factory for creating circuit models."""
pass |
class CircuitModelFactory(ABC):
'''Factory for creating circuit models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,542 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.ComponentModelFactory | from abc import ABC, abstractmethod
class ComponentModelFactory(ABC):
"""Factory for creating component models."""
pass |
class ComponentModelFactory(ABC):
'''Factory for creating component models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,543 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IAgent | from abc import ABC, abstractmethod
class IAgent(ABC):
"""Interface for agents."""
pass |
class IAgent(ABC):
'''Interface for agents.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,544 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IAgentManager | from abc import ABC, abstractmethod
class IAgentManager(ABC):
"""Interface for agent management."""
pass |
class IAgentManager(ABC):
'''Interface for agent management.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,545 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.ICircuitModel | from abc import ABC, abstractmethod
class ICircuitModel(ABC):
"""Interface for circuit models."""
pass |
class ICircuitModel(ABC):
'''Interface for circuit models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,546 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IComponentModel | from abc import ABC, abstractmethod
class IComponentModel(ABC):
"""Interface for component models."""
pass |
class IComponentModel(ABC):
'''Interface for component models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,547 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IFootprintLibrary | from abc import ABC, abstractmethod
class IFootprintLibrary(ABC):
"""Interface for footprint libraries."""
pass |
class IFootprintLibrary(ABC):
'''Interface for footprint libraries.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,548 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IKiCadIntegration | from abc import ABC, abstractmethod
class IKiCadIntegration(ABC):
"""Interface for KiCad integration."""
pass |
class IKiCadIntegration(ABC):
'''Interface for KiCad integration.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,549 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IKnowledgeBase | from abc import ABC, abstractmethod
class IKnowledgeBase(ABC):
"""Interface for knowledge base."""
pass |
class IKnowledgeBase(ABC):
'''Interface for knowledge base.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,550 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.ILLMManager | from abc import ABC, abstractmethod
class ILLMManager(ABC):
"""Interface for LLM management."""
pass |
class ILLMManager(ABC):
'''Interface for LLM management.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,551 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.ILLMProvider | from abc import ABC, abstractmethod
class ILLMProvider(ABC):
"""Interface for LLM providers."""
pass |
class ILLMProvider(ABC):
'''Interface for LLM providers.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,552 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.INetModel | from abc import ABC, abstractmethod
class INetModel(ABC):
"""Interface for net models."""
pass |
class INetModel(ABC):
'''Interface for net models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,553 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IPCBGenerator | from abc import ABC, abstractmethod
class IPCBGenerator(ABC):
"""Interface for PCB generation."""
pass |
class IPCBGenerator(ABC):
'''Interface for PCB generation.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,554 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IPinModel | from abc import ABC, abstractmethod
class IPinModel(ABC):
"""Interface for pin models."""
pass |
class IPinModel(ABC):
'''Interface for pin models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,555 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IPromptManager | from abc import ABC, abstractmethod
class IPromptManager(ABC):
"""Interface for prompt management."""
pass |
class IPromptManager(ABC):
'''Interface for prompt management.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,556 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.IPromptTemplate | from abc import ABC, abstractmethod
class IPromptTemplate(ABC):
"""Interface for prompt templates."""
pass |
class IPromptTemplate(ABC):
'''Interface for prompt templates.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,557 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.ISchematicGenerator | from abc import ABC, abstractmethod
class ISchematicGenerator(ABC):
"""Interface for schematic generation."""
pass |
class ISchematicGenerator(ABC):
'''Interface for schematic generation.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,558 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.ISymbolLibrary | from abc import ABC, abstractmethod
class ISymbolLibrary(ABC):
"""Interface for symbol libraries."""
pass |
class ISymbolLibrary(ABC):
'''Interface for symbol libraries.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,559 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.KnowledgeBaseFactory | from abc import ABC, abstractmethod
class KnowledgeBaseFactory(ABC):
"""Factory for knowledge base."""
pass |
class KnowledgeBaseFactory(ABC):
'''Factory for knowledge base.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,560 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.LLMProviderFactory | from abc import ABC, abstractmethod
class LLMProviderFactory(ABC):
"""Factory for LLM providers."""
pass |
class LLMProviderFactory(ABC):
'''Factory for LLM providers.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,561 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.NetModelFactory | from abc import ABC, abstractmethod
class NetModelFactory(ABC):
"""Factory for creating net models."""
pass |
class NetModelFactory(ABC):
'''Factory for creating net models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,562 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.PinModelFactory | from abc import ABC, abstractmethod
class PinModelFactory(ABC):
"""Factory for creating pin models."""
pass |
class PinModelFactory(ABC):
'''Factory for creating pin models.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,563 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_interfaces.py | circuit_synth.core._interfaces.PromptManagerFactory | from abc import ABC, abstractmethod
class PromptManagerFactory(ABC):
"""Factory for prompt managers."""
pass |
class PromptManagerFactory(ABC):
'''Factory for prompt managers.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 20 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,564 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_logger.py | circuit_synth.core._logger.ContextLogger | from typing import Any, Dict
import logging
class ContextLogger:
"""Simple context logger that wraps standard logging."""
def __init__(self, name: str='circuit_synth'):
self.logger = logging.getLogger(name)
def debug(self, message: str, **kwargs: Any) -> None:
"""Log debug message with op... |
class ContextLogger:
'''Simple context logger that wraps standard logging.'''
def __init__(self, name: str='circuit_synth'):
pass
def debug(self, message: str, **kwargs: Any) -> None:
'''Log debug message with optional context.'''
pass
def info(self, message: str, **kwargs: A... | 6 | 5 | 6 | 0 | 5 | 1 | 2 | 0.19 | 0 | 2 | 0 | 0 | 5 | 1 | 5 | 5 | 37 | 5 | 27 | 11 | 21 | 5 | 23 | 11 | 17 | 2 | 0 | 1 | 9 |
326,565 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/_logger.py | circuit_synth.core._logger.GenerationStage | class GenerationStage:
"""Placeholder for generation stages."""
pass | class GenerationStage:
'''Placeholder for generation stages.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 0 | 0 | 0 |
326,566 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/annotations.py | circuit_synth.core.annotations.Graphic | import uuid
from typing import Any, Dict, List, Optional, Tuple
class Graphic:
"""Factory class for creating graphic elements."""
@staticmethod
def rectangle(position: Tuple[float, float], width: float, height: float, style: str='solid', color: str='black', fill: bool=False, fill_color: str='white') -> Di... |
class Graphic:
'''Factory class for creating graphic elements.'''
@staticmethod
def rectangle(position: Tuple[float, float], width: float, height: float, style: str='solid', color: str='black', fill: bool=False, fill_color: str='white') -> Dict[str, Any]:
'''Create a rectangle graphic element.'''
... | 7 | 4 | 19 | 0 | 18 | 1 | 1 | 0.07 | 0 | 4 | 0 | 0 | 0 | 0 | 3 | 3 | 65 | 3 | 58 | 28 | 30 | 4 | 7 | 4 | 3 | 1 | 0 | 0 | 3 |
326,567 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/annotations.py | circuit_synth.core.annotations.Table | from dataclasses import dataclass
from typing import Any, Dict, List, Optional, Tuple
import uuid
@dataclass
class Table:
"""Tabular data display on schematic."""
data: List[List[str]]
position: Tuple[float, float]
cell_width: float = 20.0
cell_height: float = 5.0
text_size: float = 1.0
bor... | @dataclass
class Table:
'''Tabular data display on schematic.'''
def __post_init__(self):
pass
def to_dict(self) -> Dict[str, Any]:
'''Convert annotation to dictionary format for JSON export.'''
pass | 4 | 2 | 9 | 0 | 8 | 1 | 2 | 0.23 | 0 | 2 | 0 | 0 | 2 | 0 | 2 | 2 | 31 | 3 | 26 | 10 | 23 | 6 | 15 | 10 | 12 | 2 | 0 | 1 | 3 |
326,568 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/annotations.py | circuit_synth.core.annotations.TextBox | from dataclasses import dataclass
import uuid
from typing import Any, Dict, List, Optional, Tuple
@dataclass
class TextBox:
"""Text with optional background box and border."""
text: str
position: Tuple[float, float]
size: Tuple[float, float] = (40.0, 20.0)
margins: Tuple[float, float, float, float]... | @dataclass
class TextBox:
'''Text with optional background box and border.'''
def __post_init__(self):
pass
def to_dict(self) -> Dict[str, Any]:
'''Convert annotation to dictionary format for JSON export.'''
pass | 4 | 2 | 12 | 0 | 12 | 1 | 2 | 0.11 | 0 | 2 | 0 | 0 | 2 | 0 | 2 | 2 | 50 | 3 | 45 | 17 | 42 | 5 | 22 | 17 | 19 | 2 | 0 | 1 | 3 |
326,569 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/annotations.py | circuit_synth.core.annotations.TextProperty | from dataclasses import dataclass
from typing import Any, Dict, List, Optional, Tuple
import uuid
@dataclass
class TextProperty:
"""Simple text annotation for schematics."""
text: str
position: Tuple[float, float]
size: float = 1.27
bold: bool = False
italic: bool = False
color: str = 'blac... | @dataclass
class TextProperty:
'''Simple text annotation for schematics.'''
def __post_init__(self):
pass
def to_dict(self) -> Dict[str, Any]:
'''Convert annotation to dictionary format for JSON export.'''
pass | 4 | 2 | 9 | 0 | 8 | 1 | 2 | 0.27 | 0 | 2 | 0 | 0 | 2 | 0 | 2 | 2 | 31 | 3 | 26 | 10 | 23 | 7 | 15 | 10 | 12 | 2 | 0 | 1 | 3 |
326,570 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/circuit.py | circuit_synth.core.circuit.Circuit | from pathlib import Path
from ._logger import context_logger
import re
import json
from .reference_manager import ReferenceManager
from .net import Net
from .exception import CircuitSynthError, ValidationError
from .netlist_exporter import NetlistExporter
import tempfile
import os
from typing import Any, Dict, List, Op... |
class Circuit:
def __init__(self, name=None, description=None, auto_comments=True):
pass
def validate_reference(self, ref: str) -> bool:
'''Check if reference is available in this circuit's scope'''
pass
def register_reference(self, ref: str) -> None:
'''Register a new re... | 35 | 23 | 21 | 2 | 14 | 5 | 2 | 0.38 | 0 | 20 | 10 | 0 | 26 | 10 | 27 | 27 | 615 | 85 | 398 | 121 | 342 | 150 | 229 | 100 | 189 | 9 | 0 | 6 | 69 |
326,571 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/component.py | circuit_synth.core.component.Component | from .simple_pin_access import PinGroup, SimplifiedPinAccess
import re
from ._logger import context_logger
from dataclasses import dataclass, field
from .decorators import get_current_circuit
from .exception import CircuitSynthError, ComponentError, LibraryNotFound, ValidationError
from .pin import Pin
import keyword
f... | @dataclass
class Component(SimplifiedPinAccess):
'''
Represents an electronic component that references a KiCad symbol.
If multiple pins share the same name (e.g. "GND"), __getitem__ returns a PinGroup,
so something like:
comp["GND"] += net
will connect *all* GND pins to that net.
Additi... | 17 | 4 | 33 | 3 | 26 | 5 | 5 | 0.24 | 1 | 21 | 6 | 0 | 13 | 0 | 14 | 16 | 515 | 65 | 375 | 73 | 350 | 90 | 222 | 60 | 207 | 19 | 1 | 3 | 76 |
326,572 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/dependency_injection.py | circuit_synth.core.dependency_injection.DependencyContainer | from typing import Any, Callable, Dict, Generic, Optional, Type, TypeVar
from threading import Lock
import inspect
class DependencyContainer(IDependencyContainer):
"""
Concrete implementation of dependency injection container.
Provides registration and resolution of dependencies with support for
diffe... |
class DependencyContainer(IDependencyContainer):
'''
Concrete implementation of dependency injection container.
Provides registration and resolution of dependencies with support for
different lifetime scopes and automatic dependency injection.
'''
def __init__(self):
pass
def regi... | 12 | 11 | 11 | 1 | 8 | 2 | 2 | 0.31 | 1 | 7 | 2 | 0 | 11 | 4 | 11 | 38 | 138 | 24 | 88 | 26 | 76 | 27 | 66 | 26 | 54 | 8 | 5 | 3 | 23 |
326,573 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/dependency_injection.py | circuit_synth.core.dependency_injection.DependencyRegistration | from typing import Any, Callable, Dict, Generic, Optional, Type, TypeVar
class DependencyRegistration:
"""Represents a dependency registration"""
def __init__(self, interface: Type[T], implementation: Optional[Type[T]]=None, factory: Optional[Callable[[], T]]=None, instance: Optional[T]=None, lifetime: str=Li... |
class DependencyRegistration:
'''Represents a dependency registration'''
def __init__(self, interface: Type[T], implementation: Optional[Type[T]]=None, factory: Optional[Callable[[], T]]=None, instance: Optional[T]=None, lifetime: str=LifetimeScope.TRANSIENT, dependencies: Optional[Dict[str, Type]]=None):
... | 2 | 1 | 24 | 2 | 21 | 1 | 3 | 0.09 | 0 | 4 | 1 | 0 | 1 | 6 | 1 | 1 | 27 | 3 | 22 | 16 | 12 | 2 | 12 | 8 | 10 | 3 | 0 | 1 | 3 |
326,574 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/dependency_injection.py | circuit_synth.core.dependency_injection.IDependencyContainer | from abc import ABC, abstractmethod
from typing import Any, Callable, Dict, Generic, Optional, Type, TypeVar
class IDependencyContainer(ABC):
"""Abstract interface for dependency container"""
@abstractmethod
def register(self, registration: DependencyRegistration) -> None:
"""Register a dependency... |
class IDependencyContainer(ABC):
'''Abstract interface for dependency container'''
@abstractmethod
def register(self, registration: DependencyRegistration) -> None:
'''Register a dependency'''
pass
@abstractmethod
def register_singleton(self, interface: Type[T], implementation: Type... | 15 | 8 | 3 | 0 | 2 | 1 | 1 | 0.36 | 1 | 2 | 1 | 1 | 7 | 0 | 7 | 27 | 37 | 7 | 22 | 15 | 7 | 8 | 15 | 8 | 7 | 1 | 4 | 0 | 7 |
326,575 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/dependency_injection.py | circuit_synth.core.dependency_injection.LifetimeScope | class LifetimeScope:
"""Defines the lifetime scope for dependencies"""
SINGLETON = 'singleton'
TRANSIENT = 'transient'
SCOPED = 'scoped' | class LifetimeScope:
'''Defines the lifetime scope for dependencies'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 6 | 1 | 4 | 4 | 3 | 1 | 4 | 4 | 3 | 0 | 0 | 0 | 0 |
326,576 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/dependency_injection.py | circuit_synth.core.dependency_injection.ServiceLocator | from threading import Lock
from typing import Any, Callable, Dict, Generic, Optional, Type, TypeVar
class ServiceLocator:
"""
Service locator pattern implementation for global access to the container.
Provides a global point of access to the dependency container while
maintaining testability through c... |
class ServiceLocator:
'''
Service locator pattern implementation for global access to the container.
Provides a global point of access to the dependency container while
maintaining testability through container replacement.
'''
@classmethod
def set_container(cls, container: IDependencyConta... | 9 | 5 | 4 | 0 | 3 | 1 | 2 | 0.45 | 0 | 3 | 2 | 0 | 0 | 0 | 4 | 4 | 35 | 6 | 20 | 11 | 11 | 9 | 16 | 7 | 11 | 3 | 0 | 3 | 6 |
326,577 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/enhanced_netlist_exporter.py | circuit_synth.core.enhanced_netlist_exporter.EnhancedNetlistExporter | import os
import psutil
from .netlist_exporter import NetlistExporter
from typing import Any, Dict, List, Optional
import time
from ._logger import GenerationStage, context_logger, generation_logger, log_netlist_analytics, performance_logger
class EnhancedNetlistExporter(NetlistExporter):
"""
Enhanced NetlistE... |
class EnhancedNetlistExporter(NetlistExporter):
'''
Enhanced NetlistExporter with performance analytics and monitoring.
This class extends NetlistExporter to integrate with the generation
logging system, providing detailed analytics and performance monitoring
for netlist generation operations.
... | 6 | 6 | 36 | 5 | 25 | 7 | 2 | 0.31 | 1 | 8 | 2 | 0 | 5 | 2 | 5 | 14 | 194 | 31 | 127 | 32 | 117 | 39 | 64 | 26 | 58 | 5 | 1 | 4 | 12 |
326,578 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/enhanced_netlist_exporter.py | circuit_synth.core.enhanced_netlist_exporter.NetlistMetrics | from dataclasses import dataclass
from typing import Any, Dict, List, Optional
@dataclass
class NetlistMetrics:
"""Comprehensive netlist generation metrics."""
component_count: int
net_count: int
generation_time_ms: float
file_size_bytes: int
memory_usage_mb: float
cpu_usage_percent: float
... | @dataclass
class NetlistMetrics:
'''Comprehensive netlist generation metrics.'''
def to_dict(self) -> Dict[str, Any]:
pass | 3 | 1 | 13 | 0 | 13 | 0 | 1 | 0.04 | 0 | 2 | 0 | 0 | 1 | 0 | 1 | 1 | 27 | 2 | 24 | 2 | 22 | 1 | 13 | 2 | 11 | 1 | 0 | 0 | 1 |
326,579 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.CircuitSynthError | class CircuitSynthError(Exception):
"""Base exception for all Circuit Synth errors."""
pass | class CircuitSynthError(Exception):
'''Base exception for all Circuit Synth errors.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 3 | 0 | 0 |
326,580 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.ComponentError | class ComponentError(CircuitSynthError):
"""Raised when there is an error with a component or its pins."""
pass | class ComponentError(CircuitSynthError):
'''Raised when there is an error with a component or its pins.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,581 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.ConnectionError | class ConnectionError(CircuitSynthError):
"""Raised when there is an error with connections."""
pass | class ConnectionError(CircuitSynthError):
'''Raised when there is an error with connections.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,582 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.LibraryNotFound | class LibraryNotFound(CircuitSynthError):
"""Raised when a library file cannot be found."""
pass | class LibraryNotFound(CircuitSynthError):
'''Raised when a library file cannot be found.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,583 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.ParseError | class ParseError(CircuitSynthError):
"""Raised when there is an error parsing a file."""
pass | class ParseError(CircuitSynthError):
'''Raised when there is an error parsing a file.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,584 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.SymbolNotFoundError | class SymbolNotFoundError(CircuitSynthError):
"""Raised when a symbol is not found in a library."""
pass | class SymbolNotFoundError(CircuitSynthError):
'''Raised when a symbol is not found in a library.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,585 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/exception.py | circuit_synth.core.exception.ValidationError | class ValidationError(CircuitSynthError):
"""Raised when a property validation fails."""
pass | class ValidationError(CircuitSynthError):
'''Raised when a property validation fails.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 4 | 0 | 0 |
326,586 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/json_encoder.py | circuit_synth.core.json_encoder.CircuitSynthJSONEncoder | from enum import Enum
import json
class CircuitSynthJSONEncoder(json.JSONEncoder):
"""Custom JSON encoder that handles Circuit Synth specific types."""
def default(self, obj):
if isinstance(obj, Enum):
return obj.value
if hasattr(obj, 'to_dict'):
return obj.to_dict()
... |
class CircuitSynthJSONEncoder(json.JSONEncoder):
'''Custom JSON encoder that handles Circuit Synth specific types.'''
def default(self, obj):
pass | 2 | 1 | 11 | 2 | 6 | 3 | 3 | 0.57 | 1 | 2 | 0 | 0 | 1 | 0 | 1 | 5 | 14 | 3 | 7 | 2 | 5 | 4 | 7 | 2 | 5 | 3 | 2 | 1 | 3 |
326,587 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/kicad_validator.py | circuit_synth.core.kicad_validator.KiCadValidationError | class KiCadValidationError(Exception):
"""Raised when KiCad validation fails."""
pass | class KiCadValidationError(Exception):
'''Raised when KiCad validation fails.'''
pass | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 4 | 1 | 2 | 1 | 1 | 1 | 2 | 1 | 1 | 0 | 3 | 0 | 0 |
326,588 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/logging_minimal.py | circuit_synth.core.logging_minimal.SimpleContextLogger | from typing import Any, Dict, Optional
class SimpleContextLogger:
"""Simple replacement for context_logger"""
def __init__(self):
self.logger = _base_logger
def info(self, message: str, **kwargs):
self.logger.info(f'{message} {self._format_kwargs(kwargs)}')
def debug(self, message: s... |
class SimpleContextLogger:
'''Simple replacement for context_logger'''
def __init__(self):
pass
def info(self, message: str, **kwargs):
pass
def debug(self, message: str, **kwargs):
pass
def warning(self, message: str, **kwargs):
pass
def error(self, message... | 7 | 1 | 3 | 0 | 3 | 0 | 2 | 0.11 | 0 | 2 | 0 | 0 | 6 | 1 | 6 | 6 | 26 | 6 | 19 | 10 | 12 | 2 | 19 | 10 | 12 | 5 | 0 | 2 | 10 |
326,589 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/logging_minimal.py | circuit_synth.core.logging_minimal.SimplePerformanceLogger | from contextlib import contextmanager
class SimplePerformanceLogger:
"""Simple replacement for performance_logger"""
@contextmanager
def timer(self, operation: str, **kwargs):
import time
start = time.perf_counter()
timer_id = f'{operation}_{id(self)}'
try:
yiel... |
class SimplePerformanceLogger:
'''Simple replacement for performance_logger'''
@contextmanager
def timer(self, operation: str, **kwargs):
pass | 3 | 1 | 10 | 1 | 9 | 0 | 1 | 0.09 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 14 | 2 | 11 | 7 | 7 | 1 | 9 | 6 | 6 | 1 | 0 | 1 | 1 |
326,590 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/logging_minimal.py | circuit_synth.core.logging_minimal.SimpleUserContext | class SimpleUserContext:
"""Simple replacement for UserContext"""
def __init__(self, user_id: str, session_id: str):
self.user_id = user_id
self.session_id = session_id
def __enter__(self):
return self
def __exit__(self, exc_type, exc_val, exc_tb):
pass | class SimpleUserContext:
'''Simple replacement for UserContext'''
def __init__(self, user_id: str, session_id: str):
pass
def __enter__(self):
pass
def __exit__(self, exc_type, exc_val, exc_tb):
pass | 4 | 1 | 2 | 0 | 2 | 0 | 1 | 0.13 | 0 | 1 | 0 | 0 | 3 | 2 | 3 | 3 | 12 | 3 | 8 | 6 | 4 | 1 | 8 | 6 | 4 | 1 | 0 | 0 | 3 |
326,591 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/net.py | circuit_synth.core.net.Net | from .exception import CircuitSynthError
from typing import Optional, Set
from .decorators import get_current_circuit
class Net:
"""
A Net represents an electrical node (set of pins). The name may be auto-generated.
"""
def __init__(self, name: Optional[str]=None):
self.name = name
sel... |
class Net:
'''
A Net represents an electrical node (set of pins). The name may be auto-generated.
'''
def __init__(self, name: Optional[str]=None):
pass
@property
def pins(self):
pass
def __iadd__(self, other):
'''
net += pin => pin connects to this net
... | 6 | 2 | 9 | 1 | 6 | 2 | 3 | 0.33 | 0 | 8 | 2 | 0 | 4 | 2 | 4 | 4 | 45 | 9 | 27 | 12 | 20 | 9 | 22 | 11 | 16 | 5 | 0 | 3 | 10 |
326,592 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/netlist_exporter.py | circuit_synth.core.netlist_exporter.NetlistExporter | from typing import Any, Dict, List, Optional
from pathlib import Path
from .json_encoder import CircuitSynthJSONEncoder
import os
import json
import tempfile
from .exception import CircuitSynthError
class NetlistExporter:
"""
Handles all export functionality for Circuit objects.
This class is responsible ... |
class NetlistExporter:
'''
Handles all export functionality for Circuit objects.
This class is responsible for:
- Text netlist generation
- JSON export (hierarchical and flattened)
- KiCad netlist export
- KiCad project generation
- Data transformation (to_dict, to_flattened_list)
'... | 12 | 10 | 64 | 8 | 42 | 16 | 6 | 0.42 | 0 | 11 | 4 | 1 | 9 | 1 | 9 | 9 | 699 | 92 | 438 | 104 | 415 | 185 | 258 | 88 | 243 | 27 | 0 | 6 | 70 |
326,593 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/pin.py | circuit_synth.core.pin.Pin | from typing import TYPE_CHECKING, Optional, Union
from .net import Net
from ._logger import context_logger
class Pin:
"""
Minimal Pin class for net connectivity.
- No dedicated geometry fields in the constructor
(x, y, length, orientation).
- We do accept **kwargs so geometry can be passed (and ... |
class Pin:
'''
Minimal Pin class for net connectivity.
- No dedicated geometry fields in the constructor
(x, y, length, orientation).
- We do accept **kwargs so geometry can be passed (and ignored by core),
but stored for schematic export.
'''
def __init__(self, name: str, num: str... | 17 | 7 | 13 | 1 | 9 | 3 | 3 | 0.43 | 0 | 11 | 2 | 0 | 11 | 8 | 11 | 11 | 172 | 25 | 104 | 37 | 84 | 45 | 63 | 30 | 50 | 12 | 0 | 6 | 33 |
326,594 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/pin.py | circuit_synth.core.pin.PinType | from enum import Enum
class PinType(Enum):
"""Enumeration of valid pin types."""
INPUT = 'input'
OUTPUT = 'output'
BIDIRECTIONAL = 'bidirectional'
POWER_IN = 'power_in'
POWER_OUT = 'power_out'
PASSIVE = 'passive'
TRI_STATE = 'tri_state'
NO_CONNECT = 'no_connect'
UNSPECIFIED = 'u... |
class PinType(Enum):
'''Enumeration of valid pin types.'''
def __eq__(self, other) -> bool:
'''
Override equality comparison to ensure type safety.
Args:
other: The value to compare with
Returns:
bool: True if equal, False if not equal and same type
... | 6 | 5 | 15 | 3 | 4 | 8 | 2 | 1.23 | 1 | 7 | 0 | 0 | 3 | 0 | 4 | 53 | 77 | 15 | 30 | 17 | 24 | 37 | 27 | 16 | 22 | 2 | 4 | 1 | 7 |
326,595 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/reference_manager.py | circuit_synth.core.reference_manager.ReferenceManager | from .exception import ValidationError
from typing import Dict, List, Optional, Set
from ._logger import context_logger
class ReferenceManager:
"""
Manages component references within a circuit hierarchy.
Each circuit has its own ReferenceManager instance.
"""
def __init__(self, initial_counters: ... |
class ReferenceManager:
'''
Manages component references within a circuit hierarchy.
Each circuit has its own ReferenceManager instance.
'''
def __init__(self, initial_counters: Optional[dict[str, int]]=None):
pass
def set_parent(self, parent: Optional['ReferenceManager']) -> None:
... | 11 | 10 | 11 | 1 | 8 | 2 | 2 | 0.33 | 0 | 6 | 1 | 0 | 10 | 5 | 10 | 10 | 121 | 17 | 79 | 27 | 68 | 26 | 63 | 27 | 52 | 5 | 0 | 2 | 24 |
326,596 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/simple_pin_access.py | circuit_synth.core.simple_pin_access.PinGroup | class PinGroup:
"""A simple group of pins that supports the += operator for net connections."""
def __init__(self, pins):
self._pins = pins
def __iadd__(self, net):
"""Connect all pins in this group to the given net."""
for pin in self._pins:
pin += net
return s... | class PinGroup:
'''A simple group of pins that supports the += operator for net connections.'''
def __init__(self, pins):
pass
def __iadd__(self, net):
'''Connect all pins in this group to the given net.'''
pass
def __repr__(self):
pass | 4 | 2 | 3 | 0 | 3 | 0 | 1 | 0.2 | 0 | 0 | 0 | 0 | 3 | 1 | 3 | 3 | 15 | 3 | 10 | 7 | 6 | 2 | 10 | 7 | 6 | 2 | 0 | 1 | 4 |
326,597 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/simple_pin_access.py | circuit_synth.core.simple_pin_access.SimplifiedPinAccess | from .pin import Pin
from typing import Union
from .exception import ComponentError
class SimplifiedPinAccess:
"""
Simplified pin access mixin that provides cleaner pin lookup.
This replaces the over-engineered __getitem__ method with a simpler approach:
- Direct pin number lookup (primary)
- Pin ... |
class SimplifiedPinAccess:
'''
Simplified pin access mixin that provides cleaner pin lookup.
This replaces the over-engineered __getitem__ method with a simpler approach:
- Direct pin number lookup (primary)
- Pin name lookup (secondary)
- Clear error messages without excessive complexity
'... | 3 | 3 | 38 | 5 | 23 | 10 | 8 | 0.59 | 0 | 7 | 3 | 2 | 2 | 0 | 2 | 2 | 86 | 13 | 46 | 7 | 43 | 27 | 33 | 7 | 30 | 10 | 0 | 3 | 16 |
326,598 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/symbol_cache.py | circuit_synth.core.symbol_cache.SymbolDefinition | from ..kicad.core.types import Point, SchematicPin
from typing import Any, Dict, List, Optional, Tuple
from dataclasses import dataclass, field
@dataclass
class SymbolDefinition:
"""Definition of a symbol from KiCad library."""
lib_id: str
name: str
reference_prefix: str
description: str = ''
k... | @dataclass
class SymbolDefinition:
'''Definition of a symbol from KiCad library.'''
@property
def bounding_box(self) -> Tuple[float, float, float, float]:
'''Calculate bounding box from graphic elements and pins.'''
pass | 4 | 2 | 25 | 4 | 18 | 3 | 6 | 0.13 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 41 | 6 | 31 | 16 | 28 | 4 | 30 | 15 | 28 | 6 | 0 | 3 | 6 |
326,599 | circuit-synth/circuit-synth | /Users/umroot/Documents/PhD_works/PhD-Core-Contents/Class-level-dataset-curation/unseen_data/git_repos_for_analysis/circuit-synth_circuit-synth/src/circuit_synth/core/symbol_cache.py | circuit_synth.core.symbol_cache.SymbolLibraryCache | import hashlib
from pathlib import Path
from ..kicad.kicad_symbol_parser import parse_kicad_sym_file
from typing import Any, Dict, List, Optional, Tuple
from ..kicad.core.types import Point, SchematicPin
import os
import json
class SymbolLibraryCache:
"""
Cache for KiCad symbol libraries.
This class manag... |
class SymbolLibraryCache:
'''
Cache for KiCad symbol libraries.
This class manages loading and caching of symbol definitions from KiCad
symbol libraries, providing fast lookup and access to symbol data.
'''
def __init__(self, cache_dir: Optional[Path]=None):
'''
Initialize the ... | 21 | 21 | 32 | 5 | 21 | 7 | 5 | 0.35 | 0 | 11 | 3 | 0 | 20 | 7 | 20 | 20 | 671 | 112 | 419 | 116 | 395 | 145 | 294 | 103 | 272 | 15 | 0 | 6 | 93 |
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