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Home / 3 Factors That Stabilize Carbocations
A Primer On Organic Reactions
By James Ashenhurst
3 Factors That Stabilize Carbocations
Last updated: January 29th, 2025 |
Carbocations: Properties, Formation, and Stability
Carbocations are electron-deficient species with an empty p-orbital
Lacking a full octet and bearing a positive charge, they tend to be fairly high-energy (i.e. unstable) species and are often encountered as transient intermediates in many chemical reactions.
Three main factors increase the stability of carbocations:
Increasing the number of adjacent carbon atoms: methyl (least stable carbocation) < primary < secondary < tertiary (most stable carbocation)
Adjacent pi bonds that allow the carbocation p-orbital to be part of a conjugated pi-system system (“delocalization through resonance“)
Adjacent atoms with lone pairs that can provide the carbon with a full octet.
Adjacent electron withdrawing groups that are unable to donate a lone pair (e.g. CF3, NO2 ) greatly decrease the stability of carbocations.
Additionally, carbocations decrease in stability in the order alkyl (most stable) > alkenyl > alkynyl (least stable)
A few additional factors that influence carbocation stability include aromaticity / antiaromaticity, planarity (bridgehead carbocations are unstable) and special cases involving small rings.
Table of Contents
What Is A Carbocation?
Formation of Carbocations
Factors That Stabilize Carbocations – Substitution
Factors That Stabilize Carbocations – Resonance
Applying Carbocation Stability To Understand Reactions
Stabilization By Adjacent Lone Pairs
What’s More Important – Resonance Or Substitution?
Inductive Effects
Some Special Cases
Summary
Notes
Quiz Yourself!
(Advanced) References and Further Reading
1. What is A Carbocation?
A positively charged carbon atom bearing three covalent bonds and an empty orbital is called a carbocation (or more officially, a “carbenium” ion, although for our purposes we’re going to use “carbocation” [Note 1 ])
Other than the charge of +1 on the central carbon, the structure and properties of the vast majority [Note 2] of carbocations closely resemble those of neutral boron compounds.
Both carbocations and neutral boron compounds generally have
an sp2-hybridized central atom
with 6 valence electrons,
an empty p-orbital,
trigonal planar geometry
and bond angles of 120°.
[How do we know this? X-ray crystallography Note 3]
Like boron compounds, carbocations are electron-deficient Lewis acids that will readily combine with Lewis bases, resulting in a tetrahedral, sp3-hybridized atom with a full octet of electrons.
See if you can draw the curved arrow for the reaction below.
Click to Flip
Due to their trigonal planar geometry, carbocations can undergo attack from either face of the empty p-orbital.
Be alert for situations where this can result in a pair of stereoisomers.
Click to Flip
2. Formation of Carbocations
Carbocations are important intermediates in many reactions. (An intermediate, as opposed to a transition state, is a potentially isolable species in a reaction and occupies a potential energy minimum in a reaction coordinate diagram. Transition states have partial bonds, extremely short lifetimes and cannot be isolated).
Lacking a full octet of electrons around carbon and bearing a positive charge, carbocations are higher in energy and more unstable than neutral carbon compounds.
Some prominent reactions that involve carbocation intermediates are the addition of hydrogen halides (e.g. HBr, HCl, and HI) to alkenes and unimolecular substitution (SN1) and elimination (E1) reactions of alkyl halides.
In the SN1/E1 reactions, the first step is loss of a good leaving group (generally, a very weak base – See “What Makes A Good Leaving Group“) to give a carbocation. This is usually done in a highly polar solvent such as H2O or acetic acid which can help to stabilize the charged carbocation intermediate.
See if you can draw the curved arrow for formation of the carbocation from this tertiary alkyl halide, along with the transition state:
Click to Flip
In additions of hydrohalic acids to alkenes, the first step is attack of H+ by the pair of electrons in the C-C pi bond to give a carbocation intermediate.
See if you can draw the curved-arrow pushing mechanism and the transition state for this reaction:
Click to Flip
In both of these reactions, we start with a relatively low-energy starting material that passes through a high energy transition state en route to the carbocation intermediate.
In the second step, the carbocation then reacts with a Lewis base in solution to give a product where the carbon is again tetrahedral and sp3 hybridized.
A sketch of the reaction coordinates for each of these two reactions would look a little like this:
(Note that the carbocation intermediate occupies a local minimum on this reaction coordinate diagram; the two transition states are local maxima. )
Why bring this up?
Because the rate-determining step for each of these reactions is formation of the carbocation intermediate.
The more stable the carbocation intermediate, the lower in energy the transition state that leads to that carbocation, which translates into a lower activation energy and a faster reaction.
Therefore, if we understand the factors that govern the stabilityof carbocations, then it will also help us understand why certain reactions happen quickly whereas others do not!
3. Factors That Stabilize Carbocations – Substitution
The experimentally measured stability [Note 4] of carbocations shows the following trend:
Methyl (least stable) < primary < secondary < tertiary (most stable)
In other words, carbocation stability increases as C-H bonds are replaced with C-C bonds.
Being electron-poor, carbocations are stabilizedthrough donation of electron density from neighboring electron-rich atoms.
As I’ve often told my students, “when you’re poor, it helps to have rich neighbors“.
One way to rationalize this trend is through applying inductive effects.
Carbon is more electronegative (2.54) than hydrogen (2.20). So C-H bonds bear a small dipole whereby the carbon is partially negative and the hydrogen is partially positive.
The electron density from multiple C–H dipoles can add up. So the carbon of an alkyl group will have a small partial negative charge which can be donated to the adjacent carbocation, making it less electron-poor.
This isn’t possible when the carbocation is directly attached to H.
A more satisfying (to some! ) explanation comes from hyperconjugation.
Imagine lining up the two electrons in a C-H (or C-C) sigma bond with the empty p-orbital of the carbocation. Then imagine a form of “resonance” where those electrons are shared with the p-orbital to form a pi-bond (and H+).
Since electron density is being donated to an empty orbital, this should be stabilizing for the empty p-orbital (i.e. the carbocation).
We don’t have space in this article to go into all the implications of hyperconjugation in this article, but it does make some testable predictions that are borne out by experiment. [Note 3– the structure of the adamantyl carbocation is very instructive]
Whatever rationalization you prefer, the observed trend remains the same. The more substituted the carbocation, the greater its stability.
4. Factors That Stabilize Carbocations – Resonance
A good working principle in organic chemistry is that concentrated charge is generally more unstable (higher-energy) than dilute charge (lower-energy) [Note 5]
One place we’ve seen this before is in the concept of polarizability, where a big anion like iodide I(-) is more stable than a small ion like F(-) because the negative charge is spread out over a much greater volume. [This is the factor responsible for the greater acidity of H-I versus H-F and also the greater leaving group ability of I(-) ]
Another factor that results in this “spreading-out” of charges is “resonance”.
In a carbocation such as the n-propyl cation (CH3CH2CH2+) , the positive charge is localized to a single carbon.
But if a pi-bond is adjacent to the carbocation, we can then draw two resonance forms where the positive charge is either on C-1 or C-3.
In the resonance hybrid, the positive charge is shared between these two carbons, which will each have a charge density of +0.5 instead of +1. (This is what is meant by “resonance delocalization” – the charge has been smeared over multiple carbons)
The greater stability of this carbocation (known as the allyl cation) relative to the parent propyl cation is borne out by numerous measurements. [Note 4]
A similar effect is seen when a carbocation is adjacent to an aromatic ring such as benzene. The stability of this carbocation, known as the benzyl carbocation is considerably greater than that of a “normal” primary carbocation. (In fact the benzyl carbocation is roughly as stable as the t-butyl cation, Note 4)
The stability of the carbocation tends to increase as the number of potential resonance forms increases.
For example, the “trityl” cation, Ph3C(+) is so stable that it forms a crystalline salt that can be put in a bottle and stored on a shelf indefinitely.
Click to Flip
A word of warning. In order for a carbocation to be stabilized by resonance, the p-orbital of the carbocation must be able to overlap with the p-orbitals of the adjacent pi-bond. (See article – Conjugation and Resonance)
No overlap means no delocalization, which means no added stability.
Test your understanding of this concept by answering the quiz below.
Click to Flip
A common mistake is to think that carbocations directly attached to a pi-bond are resonance stabilized. This is not so! The pi-bond must be adjacent to the carbocation.
Another potentially counter-intuitive situation is when a carbocation is adjacent to a C=O (or C=N) bond. One might naively think that the carbocation is stabilized by resonance.
However, if you draw out the resonance form, you’ll find that in forming the C-C pi bond and breaking the C-O pi bond, you end up forming an electron-deficient species with only six valence electrons on oxygen. This “resonance form” is so high-energy as to make essentially no contribution to the resonance hybrid.
(Highly electronegative atoms like O are excellent at stabilizing negative charge, but they are terrible at stabilizing empty orbitals)
5. The Importance of Carbocation Stability In Reactions
Let’s return to the role of carbocations as intermediates in several key organic reactions.
The rate-determining step of the reaction below is protonationof the pi bond with H+ to give a carbocation intermediate.
Which of the two reactions do you think is faster?
Click to Flip
If you answered correctly, congratulations! You’ve shown you understand the reason behind Markovnikov’s rule! [See article – Markovnikov’s rule]
Let’s look at another one.
The rate-determining step of the reaction below is loss of a leaving group to form a carbocation.
Which of these two reactions proceeds faster?
Click to Flip
If you answered correctly, you’ve just shown an understanding one of the key factors that go into deciding whether a reaction will proceed via SN1, SN2, E1 or E2. (See article: SN1/SN2/E1/E2 – The Substrate)
6. Factors That Stabilize Carbocations – Adjacent Lone Pairs
There’s another factor that stabilizes carbocations that we haven’t touched on yet.
If a carbocation is formed adjacentto an atom bearing a lone pair (i.e. a Lewis base) then that atom can donate its pair of electrons to the carbocation, forming a new pi-bond in the process.
This is known as “pi-donation” (See article – Pi Donation)
It might seem somewhat counter-intuitive that a highly electronegative atom like oxygen or nitrogen can stabilize a carbocation.
But the net result of pi-donation is that all atoms have a full octet, which is highly stabilizing. (Note that even though oxygen and nitrogen will bear a formal charge of +1, they still have a full octet of electrons! See article – How To Calculate Formal Charge)
The extent to which an atom’s lone pair can stabilize an adjacent carbocation is proportional to its basicity. The more basic the atom, the better the pi-donor.
Across a row of the periodic table, the ability to donate a pair of electrons is inversely proportional to electronegativity. So, all other factors being equal, a lone pair from nitrogen will be more stabilizing than a lone pair from oxygen, which is more stabilizing than a lone pair from fluorine.
Going down the periodic table, the ability of an atom to donate a pair of electrons is related to the ability of the atom’s valence orbital to overlap with the empty carbon 2p orbital.
Generally, as the orbital increases in size, orbital overlap (and pi-donation ability) will decrease.
Thus fluorine is a better pi-donor to carbon than chlorine, which is a better pi-donor than bromine, which is better than iodine (in iodine the valence orbitals are the 5p and 5s orbitals, which do not match up well with the smaller 2p orbital of carbon).
This is an article about carbocation stability and I want to keep it focused, but the contents of this particular section are extraordinarily important, and will come up again and again throughout organic chemistry. One application you’ll see later – Electrophilic Aromatic Substitution.
7. Which Factor is More Important – Substitution or Resonance?
So we have two factors that influence carbocation stability: substitution (primary, secondary, tertiary) and resonance.
So which is more important?
“they’re both important” is my non-answer to this question.
The actual way to answer this question is to look at experimental results.
One way to measure carbocation stability is to take a related series of alkyl halides and measure the rate of their hydrolysis in a polar protic solvent under conditions where SN1 would be likely.
(The advantage of this method is that it more closely approximates actual reaction conditions. One disadvantage is that it is really only applicable to carbocations that can form under SN1 conditions. )
Another method is to measure what is called hydride affinity – the energy released by the reaction of the carbocation with one equivalent of hydride ion (H–). (Although this can be applied to a greater range of carbocations, it is really only applicable in the gas phase).
The hydride affinity of a primary benzylic carbocation is about 239 kcal/mol versus 231 kcal/mol for a t-butyl carbocation, so these are quite comparable in energy.
A table with some values is below. See Note 4.
8. Some Factors That Destabilize Carbocations
Since electron-donating groups help to stabilize carbocations, it would make sense to expect that electron-withdrawing groups will destabilize carbocations.
As we touched on above, electronegative atoms with lone pairs like O, N, and F that are directly attached to a carbocation will actually help to stabilize carbocations through pi-donation.
I would not consider those “electron-withdrawing groups” for these purposes.
By “electron-withdrawing groups” I would include
Carbon atoms attached to electron-withdrawing groups (e.g. CF3, CCl3)
Electronegative atoms without lone pairs (e.g. NR3(+) )
Atoms containing a pi-bond to a more electronegative atom (e.g. C=O, CN, NO2, SO2R, etc.)
Another factor that destabilizes carbocations is the amount of s-character in the carbon atom.
You may recall that alkyne C-H bonds are particularly acidic because their sp-orbitals have 50% s-character, and since the s-orbital is closer to the positively charged nucleus, this helps to stabilize the negative charge of the conjugate base (a carbanion).
Well, when it comes to the stabilization of carbocations, this all gets thrown into reverse.
The more s-character the carbocation has, the closer that empty orbital is held to the positively charged nucleus. This has the effect of making the carbon nucleus have a greater effective electronegativity. Removing a pair of electrons to form a carbocation becomes increasingly difficult as the s-character increases. (This can be quantified by measuring hydride affinity or electron affinity)
Bridgehead carbocations are also particularly unstable due to the fact that they cannot attain the ideal trigonal planar geometry, [Note 6] as are carbocations on small rings (such as the cyclopropyl cation and cyclobutyl cation). [Note 7]
9. Some Special Cases
For the sake of completeness we should probably mention one last factor that is more of a second-semester topic but has a very large impact on the stability of certain carbocations.
Some molecules have a particularly stable property known as aromaticity. (See article – Rules For Aromaticity)
A related phenomenon called antiaromaticity is responsible for the unusual instability of certain compounds. (See article – Antiaromatic Compounds and Antiaromaticity)
The heptatrienyl (“tropylium”) cation, C7H7+ is aromatic and due to its unusual stability, forms a stable salt that can be put in a bottle and sold commercially. The cyclopropenium ion C3H3+ is also aromatic and unusually stable.
On the other hand, the cyclopentadienyl cation, which by all appearances should be resonance-stabilized, is actually anti-aromatic and has only a fleeting existence under carefully controlled conditions at very low temperatures.
10. Summary
Carbocations are positively charged, six-electron carbon atoms with an empty p-orbital. They are important intermediates in many reactions and are highly reactive towards Lewis bases.
Three key factors stabilize carbocations:
First, they are stabilized by adjacent alkyl groups, which can donate electron density to the electron-deficient carbon atom.
Secondly, they can be stabilized through conjugation with pi bonds, which allows the positive charge to be delocalized through resonance.
Third, carbocations are stabilized by atoms with a lone pair capable of forming a pi bond.
Being electron-deficient, carbocations are destabilized by strongly electron-withdrawing substituents incapable of donating electron pairs (e.g. CF3, C=O). They are also destabilized if they are unable to attain the ideal trigonal planar geometry, which can happen in bridgehead carbocations. For similar reasons, carbocations that are part of highly strained rings such as cyclopropanes and cyclobutanes tend to be quite unstable.
Notes
Note 1. For most purposes, “carbocation” refers to a carbon with three bonds and an empty orbital, and in the vast majority of cases, this is the terminology that is used. There is a lot of inconsistency in the older literature as to whether these are “carbonium” or “carbenium” ions. The isolation of the CH5(+) species in extremely strong acid solution by the research group of George Olah at USC led IUPAC to define the term “carbenium ion” as a trivalent carbon and “carbonium ion” as a five-coordinate carbon. [Ref].
Note 2. Two prominent exceptions to this are the vinyl carbocation and the acylium ion.
Note that the vinyl carbocation has a linear geometry and the central carbon is sp-hybridized.
The acylium ion is an excellent example of a carbocation that is stabilized through donation of an adjacent lone pair. (For examples of the acylium ion, see – The Friedel Crafts Alkylation and Acylation).
Note 3. The structures of several carbocations have been determined through X-ray crystallography.
For example, the structure of the t-butyl cation shows a trigonal planar structure (bond angles 120°) with C-C bond length of 1.44 Angstroms [Ref] which is about halfway between a typical C-C single bond (1.50 Å) and a C-C double bond (1.40 Å)
The structure of the adamantyl cation is particularly interesting. In adamantane, all C-C bonds are approximately the same length (1.53 Å). However, in the adamantyl carbocation, the carbon directly bonded to the carbocation becomes noticably shorter (1.43 Å) while the C-C bond that is able to overlap with the p-orbital of the carbocation is noticeably longer (1.608 Å).
This is exactly what we would have predicted from using the hyperconjugation model for carbocation stabilization, where one C-C bond gains partial double bond character and another bond is weakened.
For a lot more detail on this, I highly recommend lecture 30 from Prof. David Evans’ Advanced Organic Chemistry 206 at Harvard, link here.
Note 4.One way to quantify the stability of carbocations is through measuring their hydride affinities, that is, the energy released upon reaction of the carbocation with a hydride ion. The hydride affinities of a large number of carbocations have been measured in the gas phase(where they have longer lifetimes).
A selection is provided below:
Solution-phase hydride affinities have also been measured for some of the more stable carbocations (gas phase hydride affinities in parentheses)
Ph3C(+) : 96 kcal/mol
Ph2CH(+): 105 kcal/mol
PhCH2(+): 118 kcal/mol (238 kcal/mol)
Tropylium ion: 83 kcal/mol (200 kcal/mol)
Note 5.Carbocation formation is easier in solvents with a high dielectric constant such as water or carboxylic acids (e.g. acetic acid, formic acid).
Note 6 One class of tertiary carbocations that are particularly unstable are carbocations that are constrained in a bridgehead. Ring strain prevents these carbocations from adopting a trigonal planar geometry.
Note 7. Carbocations that are part of small rings such as cyclopropyl and cyclobutyl carbocations are also unusually unstable.
Note 8.An alternative method of measuring carbocation stability is through measuring rates of hydrolysis in a nucleophilic solvent. However, as this graphic from Evans shows, these two measures do not always correlate well…
Quiz Yourself!
Become a MOC member to see the clickable quiz with answers on the back.
Become a MOC member to see the clickable quiz with answers on the back.
Become a MOC member to see the clickable quiz with answers on the back.
Become a MOC member to see the clickable quiz with answers on the back.
Become a MOC member to see the clickable quiz with answers on the back.
(Advanced) References and Further Reading
References
100 Years of Carbocations and Their Significance in Chemistry1
George A. Olah
The Journal of Organic Chemistry 2001 66 (18), 5943-5957 DOI: 10.1021/jo010438x A historical perspective from Prof. George Olah, who won the Nobel Prize in Chemistry in 1994 for “contributions to carbocation chemistry”.
2. Stabilities of carbocations in solution. 14. An extended thermochemical scale of carbocation stabilities in a common superacid Edward M. Arnett and Thomas C. Hofelich Journal of the American Chemical Society 1983, 105 (9), 2889-2895 DOI: 10.1021/ja00347a060 This paper provides a table of the stability of 39 carbocations, measured calorimetrically by heat of formation (ionization in superacid from the corresponding carbinol).
3. X-ray Crystal Structures of Carbocations Stabilized by Bridging or Hyperconjugation Thomas Laube Accounts of Chemical Research 1995 28 (10), 399-405 DOI: 10.1021/ar00058a001 Very interesting review from Prof. Laube comparing and contrasting the structures of various carbocations, including very clear evidence for hyperconjugation in the adamantyl carbocation. C-C bond shortened to 1.431 from 1.528 . C-C lengthenend to 1.608 from 1.530. 100 deg angle vs 110 deg angle
4. Carbonium Ions. I. An Acidity Function (C0) Derived from Arylcarbonium Ion Equilibria C. Deno, J. J. Jaruzelski, and Alan Schriesheim Journal of the American Chemical Society 1955, 77 (11), 3044-3051 DOI: 10.1021/ja01616a036 Carbocation stability can also be expressed in pKR+, which is defined in the paper. The carbocations studied in this paper are all relatively stable arylcarbonium ions.
5. Hydride affinities of carbenium ions in acetonitrile and dimethyl sulfoxide solution Jinpei Cheng, Kishan L. Handoo, and Vernon D. Parker Journal of the American Chemical Society 1993, 115 (7), 2655-2660 DOI: 10.1021/ja00060a014 Carbocation stabilities can also be expressed in terms of hydride affinity (R+ + H– -> RH). The carbocations studied in this paper are also fairly stable arylcarbonium ions, as these are measured electrochemically in either DMSO or acetonitrile.
6. Photoelectron spectroscopy of methyl, ethyl, isopropyl, and tert-butyl radicals. Implications for the thermochemistry and structures of the radicals and their corresponding carbonium ions A. Houle and J. L. Beauchamp Journal of the American Chemical Society 1979, 101 (15), 4067-4074 DOI: 10.1021/ja00509a010 Table III in this paper has heats of formation for the basic alkyl cations (methyl, ethyl, isopropyl, and t-butyl), but in the gas phase. The numbers agree with intuition from solution-phase experiments; stability increases from methyl -> ethyl -> isopropyl -> t-butyl.
7. Quantitative preparation and enthalpy of rearrangement of the sec-butyl cation W. Bittner, E. M. Arnett, and M. Saunders Journal of the American Chemical Society 1976, 98 (12), 3734-3735 DOI: 10.1021/ja00428a072 This paper describes a novel calorimetric method for measuring the heat of isomerization of the sec-butyl cation to the tert-butyl cation in superacid solution. Using this, the value obtained is 14.5 ± 0.5 kcal/mol.
8. Stability of Alkyl Carbocations Thomas Hansen, Pascal Vermeeren, F. Matthias Bickelhaupt, and Trevor A. Hamlin Chem. Commun.2022, 58, 12050-12053 DOI: 10.1039/D2CC04034D A theoretical study on carbocation stability trends. From the paper: “we quantitatively established a generally overlooked driving force behind the stability of carbocations, namely, that the parent substrates are substantially destabilized by the introduction of substituents, often playing a dominant role in solution. This stems from the repulsion between the substituents and the C–X bond.“
9. The Story of the Wagner-Meerwein Rearrangement
Ludmila Birladeanu
Journal of Chemical Education 2000 77 (7), 858
DOI: 10.1021/ed077p858 An article of historical interest on the development of understanding of the Wagner-Meerwein rearrangement of carbocations.
00 General Chemistry Review
Lewis Structures
Ionic and Covalent Bonding
Chemical Kinetics
Chemical Equilibria
Valence Electrons of the First Row Elements
How Concepts Build Up In Org 1 ("The Pyramid")
01 Bonding, Structure, and Resonance
How Do We Know Methane (CH4) Is Tetrahedral?
Hybrid Orbitals and Hybridization
How To Determine Hybridization: A Shortcut
Orbital Hybridization And Bond Strengths
Sigma bonds come in six varieties: Pi bonds come in one
A Key Skill: How to Calculate Formal Charge
The Four Intermolecular Forces and How They Affect Boiling Points
3 Trends That Affect Boiling Points
How To Use Electronegativity To Determine Electron Density (and why NOT to trust formal charge)
Introduction to Resonance
How To Use Curved Arrows To Interchange Resonance Forms
Evaluating Resonance Forms (1) - The Rule of Least Charges
How To Find The Best Resonance Structure By Applying Electronegativity
Evaluating Resonance Structures With Negative Charges
Evaluating Resonance Structures With Positive Charge
Exploring Resonance: Pi-Donation
Exploring Resonance: Pi-acceptors
In Summary: Evaluating Resonance Structures
Drawing Resonance Structures: 3 Common Mistakes To Avoid
How to apply electronegativity and resonance to understand reactivity
Bond Hybridization Practice
Structure and Bonding Practice Quizzes
Resonance Structures Practice
02 Acid Base Reactions
Introduction to Acid-Base Reactions
Acid Base Reactions In Organic Chemistry
The Stronger The Acid, The Weaker The Conjugate Base
Walkthrough of Acid-Base Reactions (3) - Acidity Trends
Five Key Factors That Influence Acidity
Acid-Base Reactions: Introducing Ka and pKa
How to Use a pKa Table
The pKa Table Is Your Friend
A Handy Rule of Thumb for Acid-Base Reactions
Acid Base Reactions Are Fast
pKa Values Span 60 Orders Of Magnitude
How Protonation and Deprotonation Affect Reactivity
Acid Base Practice Problems
03 Alkanes and Nomenclature
Meet the (Most Important) Functional Groups
Condensed Formulas: Deciphering What the Brackets Mean
Hidden Hydrogens, Hidden Lone Pairs, Hidden Counterions
Don't Be Futyl, Learn The Butyls
Primary, Secondary, Tertiary, Quaternary In Organic Chemistry
Branching, and Its Affect On Melting and Boiling Points
The Many, Many Ways of Drawing Butane
Wedge And Dash Convention For Tetrahedral Carbon
Common Mistakes in Organic Chemistry: Pentavalent Carbon
Table of Functional Group Priorities for Nomenclature
Summary Sheet - Alkane Nomenclature
Organic Chemistry IUPAC Nomenclature Demystified With A Simple Puzzle Piece Approach
Boiling Point Quizzes
Organic Chemistry Nomenclature Quizzes
04 Conformations and Cycloalkanes
Staggered vs Eclipsed Conformations of Ethane
Conformational Isomers of Propane
Newman Projection of Butane (and Gauche Conformation)
Introduction to Cycloalkanes
Geometric Isomers In Small Rings: Cis And Trans Cycloalkanes
Calculation of Ring Strain In Cycloalkanes
Cycloalkanes - Ring Strain In Cyclopropane And Cyclobutane
Cyclohexane Conformations
Cyclohexane Chair Conformation: An Aerial Tour
How To Draw The Cyclohexane Chair Conformation
The Cyclohexane Chair Flip
The Cyclohexane Chair Flip - Energy Diagram
Substituted Cyclohexanes - Axial vs Equatorial
Ranking The Bulkiness Of Substituents On Cyclohexanes: "A-Values"
Cyclohexane Chair Conformation Stability: Which One Is Lower Energy?
Fused Rings - Cis-Decalin and Trans-Decalin
Naming Bicyclic Compounds - Fused, Bridged, and Spiro
Bredt's Rule (And Summary of Cycloalkanes)
Newman Projection Practice
Cycloalkanes Practice Problems
05 A Primer On Organic Reactions
The Most Important Question To Ask When Learning a New Reaction
Curved Arrows (for reactions)
Nucleophiles and Electrophiles
The Three Classes of Nucleophiles
Nucleophilicity vs. Basicity
What Makes A Good Nucleophile?
What Makes A Good Leaving Group?
3 Factors That Stabilize Carbocations
Equilibrium and Energy Relationships
7 Factors that stabilize negative charge in organic chemistry
7 Factors That Stabilize Positive Charge in Organic Chemistry
What's a Transition State?
Hammond's Postulate
Learning Organic Chemistry Reactions: A Checklist (PDF)
Introduction to Oxidative Cleavage Reactions
06 Free Radical Reactions
Free Radical Reactions
3 Factors That Stabilize Free Radicals
Bond Strengths And Radical Stability
Free Radical Initiation: Why Is "Light" Or "Heat" Required?
Initiation, Propagation, Termination
Monochlorination Products Of Propane, Pentane, And Other Alkanes
Selectivity In Free Radical Reactions
Selectivity in Free Radical Reactions: Bromination vs. Chlorination
Halogenation At Tiffany's
Allylic Bromination
Bonus Topic: Allylic Rearrangements
In Summary: Free Radicals
Synthesis (2) - Reactions of Alkanes
Free Radicals Practice Quizzes
07 Stereochemistry and Chirality
Types of Isomers: Constitutional Isomers, Stereoisomers, Enantiomers, and Diastereomers
How To Draw The Enantiomer Of A Chiral Molecule
How To Draw A Bond Rotation
Introduction to Assigning (R) and (S): The Cahn-Ingold-Prelog Rules
Assigning Cahn-Ingold-Prelog (CIP) Priorities (2) - The Method of Dots
Enantiomers vs Diastereomers vs The Same? Two Methods For Solving Problems
Assigning R/S To Newman Projections (And Converting Newman To Line Diagrams)
How To Determine R and S Configurations On A Fischer Projection
The Meso Trap
Optical Rotation, Optical Activity, and Specific Rotation
Optical Purity and Enantiomeric Excess
What's a Racemic Mixture?
Chiral Allenes And Chiral Axes
Stereochemistry Practice Problems and Quizzes
08 Substitution Reactions
Nucleophilic Substitution Reactions - Introduction
Two Types of Nucleophilic Substitution Reactions
The SN2 Mechanism
Why the SN2 Reaction Is Powerful
The SN1 Mechanism
The Conjugate Acid Is A Better Leaving Group
Comparing the SN1 and SN2 Reactions
Polar Protic? Polar Aprotic? Nonpolar? All About Solvents
Steric Hindrance is Like a Fat Goalie
Common Blind Spot: Intramolecular Reactions
Substitution Practice - SN1
Substitution Practice - SN2
09 Elimination Reactions
Elimination Reactions (1): Introduction And The Key Pattern
Elimination Reactions (2): The Zaitsev Rule
Elimination Reactions Are Favored By Heat
Two Elimination Reaction Patterns
The E1 Reaction
The E2 Mechanism
E1 vs E2: Comparing the E1 and E2 Reactions
Antiperiplanar Relationships: The E2 Reaction and Cyclohexane Rings
Bulky Bases in Elimination Reactions
Comparing the E1 vs SN1 Reactions
Elimination (E1) Reactions With Rearrangements
E1cB - Elimination (Unimolecular) Conjugate Base
Elimination (E1) Practice Problems And Solutions
Elimination (E2) Practice Problems and Solutions
10 Rearrangements
Introduction to Rearrangement Reactions
Rearrangement Reactions (1) - Hydride Shifts
Carbocation Rearrangement Reactions (2) - Alkyl Shifts
Pinacol Rearrangement
The SN1, E1, and Alkene Addition Reactions All Pass Through A Carbocation Intermediate
11 SN1/SN2/E1/E2 Decision
Identifying Where Substitution and Elimination Reactions Happen
Deciding SN1/SN2/E1/E2 (1) - The Substrate
Deciding SN1/SN2/E1/E2 (2) - The Nucleophile/Base
SN1 vs E1 and SN2 vs E2 : The Temperature
Deciding SN1/SN2/E1/E2 - The Solvent
Wrapup: The Key Factors For Determining SN1/SN2/E1/E2
Alkyl Halide Reaction Map And Summary
SN1 SN2 E1 E2 Practice Problems
12 Alkene Reactions
E and Z Notation For Alkenes (+ Cis/Trans)
Alkene Stability
Alkene Addition Reactions: "Regioselectivity" and "Stereoselectivity" (Syn/Anti)
Stereoselective and Stereospecific Reactions
Hydrohalogenation of Alkenes and Markovnikov's Rule
Hydration of Alkenes With Aqueous Acid
Rearrangements in Alkene Addition Reactions
Halogenation of Alkenes and Halohydrin Formation
Oxymercuration Demercuration of Alkenes
Hydroboration Oxidation of Alkenes
m-CPBA (meta-chloroperoxybenzoic acid)
OsO4 (Osmium Tetroxide) for Dihydroxylation of Alkenes
Palladium on Carbon (Pd/C) for Catalytic Hydrogenation of Alkenes
Cyclopropanation of Alkenes
A Fourth Alkene Addition Pattern - Free Radical Addition
Alkene Reactions: Ozonolysis
Summary: Three Key Families Of Alkene Reaction Mechanisms
Synthesis (4) - Alkene Reaction Map, Including Alkyl Halide Reactions
Alkene Reactions Practice Problems
13 Alkyne Reactions
Acetylides from Alkynes, And Substitution Reactions of Acetylides
Partial Reduction of Alkynes With Lindlar's Catalyst
Partial Reduction of Alkynes With Na/NH3 To Obtain Trans Alkenes
Alkyne Hydroboration With "R2BH"
Hydration and Oxymercuration of Alkynes
Hydrohalogenation of Alkynes
Alkyne Halogenation: Bromination and Chlorination of Alkynes
Oxidation of Alkynes With O3 and KMnO4
Alkenes To Alkynes Via Halogenation And Elimination Reactions
Alkynes Are A Blank Canvas
Synthesis (5) - Reactions of Alkynes
Alkyne Reactions Practice Problems With Answers
14 Alcohols, Epoxides and Ethers
Alcohols - Nomenclature and Properties
Alcohols Can Act As Acids Or Bases (And Why It Matters)
Alcohols - Acidity and Basicity
The Williamson Ether Synthesis
Ethers From Alkenes, Tertiary Alkyl Halides and Alkoxymercuration
Alcohols To Ethers via Acid Catalysis
Cleavage Of Ethers With Acid
Epoxides - The Outlier Of The Ether Family
Opening of Epoxides With Acid
Epoxide Ring Opening With Base
Making Alkyl Halides From Alcohols
Tosylates And Mesylates
PBr3 and SOCl2
Elimination Reactions of Alcohols
Elimination of Alcohols To Alkenes With POCl3
Alcohol Oxidation: "Strong" and "Weak" Oxidants
Demystifying The Mechanisms of Alcohol Oxidations
Protecting Groups For Alcohols
Thiols And Thioethers
Calculating the oxidation state of a carbon
Oxidation and Reduction in Organic Chemistry
Oxidation Ladders
SOCl2 Mechanism For Alcohols To Alkyl Halides: SN2 versus SNi
Alcohol Reactions Roadmap (PDF)
Alcohol Reaction Practice Problems
Epoxide Reaction Quizzes
Oxidation and Reduction Practice Quizzes
15 Organometallics
What's An Organometallic?
Formation of Grignard and Organolithium Reagents
Organometallics Are Strong Bases
Reactions of Grignard Reagents
Protecting Groups In Grignard Reactions
Synthesis Problems Involving Grignard Reagents
Grignard Reactions And Synthesis (2)
Organocuprates (Gilman Reagents): How They're Made
Gilman Reagents (Organocuprates): What They're Used For
The Heck, Suzuki, and Olefin Metathesis Reactions (And Why They Don't Belong In Most Introductory Organic Chemistry Courses)
Reaction Map: Reactions of Organometallics
Grignard Practice Problems
16 Spectroscopy
Degrees of Unsaturation (or IHD, Index of Hydrogen Deficiency)
Conjugation And Color (+ How Bleach Works)
Introduction To UV-Vis Spectroscopy
UV-Vis Spectroscopy: Absorbance of Carbonyls
UV-Vis Spectroscopy: Practice Questions
Bond Vibrations, Infrared Spectroscopy, and the "Ball and Spring" Model
Infrared Spectroscopy: A Quick Primer On Interpreting Spectra
IR Spectroscopy: 4 Practice Problems
1H NMR: How Many Signals?
Homotopic, Enantiotopic, Diastereotopic
Diastereotopic Protons in 1H NMR Spectroscopy: Examples
13-C NMR - How Many Signals
Liquid Gold: Pheromones In Doe Urine
Natural Product Isolation (1) - Extraction
Natural Product Isolation (2) - Purification Techniques, An Overview
Structure Determination Case Study: Deer Tarsal Gland Pheromone
17 Dienes and MO Theory
What To Expect In Organic Chemistry 2
Are these molecules conjugated?
Conjugation And Resonance In Organic Chemistry
Bonding And Antibonding Pi Orbitals
Molecular Orbitals of The Allyl Cation, Allyl Radical, and Allyl Anion
Pi Molecular Orbitals of Butadiene
Reactions of Dienes: 1,2 and 1,4 Addition
Thermodynamic and Kinetic Products
More On 1,2 and 1,4 Additions To Dienes
s-cis and s-trans
The Diels-Alder Reaction
Cyclic Dienes and Dienophiles in the Diels-Alder Reaction
Stereochemistry of the Diels-Alder Reaction
Exo vs Endo Products In The Diels Alder: How To Tell Them Apart
HOMO and LUMO In the Diels Alder Reaction
Why Are Endo vs Exo Products Favored in the Diels-Alder Reaction?
Diels-Alder Reaction: Kinetic and Thermodynamic Control
The Retro Diels-Alder Reaction
The Intramolecular Diels Alder Reaction
Regiochemistry In The Diels-Alder Reaction
The Cope and Claisen Rearrangements
Electrocyclic Reactions
Electrocyclic Ring Opening And Closure (2) - Six (or Eight) Pi Electrons
Diels Alder Practice Problems
Molecular Orbital Theory Practice
18 Aromaticity
Introduction To Aromaticity
Rules For Aromaticity
Huckel's Rule: What Does 4n+2 Mean?
Aromatic, Non-Aromatic, or Antiaromatic? Some Practice Problems
Antiaromatic Compounds and Antiaromaticity
The Pi Molecular Orbitals of Benzene
The Pi Molecular Orbitals of Cyclobutadiene
Frost Circles
Aromaticity Practice Quizzes
19 Reactions of Aromatic Molecules
Electrophilic Aromatic Substitution: Introduction
Activating and Deactivating Groups In Electrophilic Aromatic Substitution
Electrophilic Aromatic Substitution - The Mechanism
Ortho-, Para- and Meta- Directors in Electrophilic Aromatic Substitution
Understanding Ortho, Para, and Meta Directors
Why are halogens ortho- para- directors?
Disubstituted Benzenes: The Strongest Electron-Donor "Wins"
Electrophilic Aromatic Substitutions (1) - Halogenation of Benzene
Electrophilic Aromatic Substitutions (2) - Nitration and Sulfonation
EAS Reactions (3) - Friedel-Crafts Acylation and Friedel-Crafts Alkylation
Intramolecular Friedel-Crafts Reactions
Nucleophilic Aromatic Substitution (NAS)
Nucleophilic Aromatic Substitution (2) - The Benzyne Mechanism
Reactions on the "Benzylic" Carbon: Bromination And Oxidation
The Wolff-Kishner, Clemmensen, And Other Carbonyl Reductions
More Reactions on the Aromatic Sidechain: Reduction of Nitro Groups and the Baeyer Villiger
Aromatic Synthesis (1) - "Order Of Operations"
Synthesis of Benzene Derivatives (2) - Polarity Reversal
Aromatic Synthesis (3) - Sulfonyl Blocking Groups
Birch Reduction
Synthesis (7): Reaction Map of Benzene and Related Aromatic Compounds
Aromatic Reactions and Synthesis Practice
Electrophilic Aromatic Substitution Practice Problems
20 Aldehydes and Ketones
What's The Alpha Carbon In Carbonyl Compounds?
Nucleophilic Addition To Carbonyls
Aldehydes and Ketones: 14 Reactions With The Same Mechanism
Sodium Borohydride (NaBH4) Reduction of Aldehydes and Ketones
Grignard Reagents For Addition To Aldehydes and Ketones
Wittig Reaction
Hydrates, Hemiacetals, and Acetals
Imines - Properties, Formation, Reactions, and Mechanisms
All About Enamines
Breaking Down Carbonyl Reaction Mechanisms: Reactions of Anionic Nucleophiles (Part 2)
Aldehydes Ketones Reaction Practice
21 Carboxylic Acid Derivatives
Nucleophilic Acyl Substitution (With Negatively Charged Nucleophiles)
Addition-Elimination Mechanisms With Neutral Nucleophiles (Including Acid Catalysis)
Basic Hydrolysis of Esters - Saponification
Transesterification
Proton Transfer
Fischer Esterification - Carboxylic Acid to Ester Under Acidic Conditions
Lithium Aluminum Hydride (LiAlH4) For Reduction of Carboxylic Acid Derivatives
LiAlH[Ot-Bu]3 For The Reduction of Acid Halides To Aldehydes
Di-isobutyl Aluminum Hydride (DIBAL) For The Partial Reduction of Esters and Nitriles
Amide Hydrolysis
Thionyl Chloride (SOCl2) And Conversion of Carboxylic Acids to Acid Halides
Diazomethane (CH2N2)
Carbonyl Chemistry: Learn Six Mechanisms For the Price Of One
Making Music With Mechanisms (PADPED)
Carboxylic Acid Derivatives Practice Questions
22 Enols and Enolates
Keto-Enol Tautomerism
Enolates - Formation, Stability, and Simple Reactions
Kinetic Versus Thermodynamic Enolates
Aldol Addition and Condensation Reactions
Reactions of Enols - Acid-Catalyzed Aldol, Halogenation, and Mannich Reactions
Claisen Condensation and Dieckmann Condensation
Decarboxylation
The Malonic Ester and Acetoacetic Ester Synthesis
The Michael Addition Reaction and Conjugate Addition
The Robinson Annulation
Haloform Reaction
The Hell–Volhard–Zelinsky Reaction
Enols and Enolates Practice Quizzes
23 Amines
The Amide Functional Group: Properties, Synthesis, and Nomenclature
Basicity of Amines And pKaH
5 Key Basicity Trends of Amines
The Mesomeric Effect And Aromatic Amines
Nucleophilicity of Amines
Alkylation of Amines (Sucks!)
Reductive Amination
The Gabriel Synthesis
Some Reactions of Azides
The Hofmann Elimination
The Hofmann and Curtius Rearrangements
The Cope Elimination
Protecting Groups for Amines - Carbamates
The Strecker Synthesis of Amino Acids
Introduction to Peptide Synthesis
Reactions of Diazonium Salts: Sandmeyer and Related Reactions
Amine Practice Questions
24 Carbohydrates
D and L Notation For Sugars
Pyranoses and Furanoses: Ring-Chain Tautomerism In Sugars
What is Mutarotation?
Reducing Sugars
The Big Damn Post Of Carbohydrate-Related Chemistry Definitions
The Haworth Projection
Converting a Fischer Projection To A Haworth (And Vice Versa)
Reactions of Sugars: Glycosylation and Protection
The Ruff Degradation and Kiliani-Fischer Synthesis
Isoelectric Points of Amino Acids (and How To Calculate Them)
Carbohydrates Practice
Amino Acid Quizzes
25 Fun and Miscellaneous
A Gallery of Some Interesting Molecules From Nature
Screw Organic Chemistry, I'm Just Going To Write About Cats
On Cats, Part 1: Conformations and Configurations
On Cats, Part 2: Cat Line Diagrams
On Cats, Part 4: Enantiocats
On Cats, Part 6: Stereocenters
Organic Chemistry Is Shit
The Organic Chemistry Behind "The Pill"
Maybe they should call them, "Formal Wins" ?
Why Do Organic Chemists Use Kilocalories?
The Principle of Least Effort
Organic Chemistry GIFS - Resonance Forms
Reproducibility In Organic Chemistry
What Holds The Nucleus Together?
How Reactions Are Like Music
Organic Chemistry and the New MCAT
26 Organic Chemistry Tips and Tricks
Common Mistakes: Formal Charges Can Mislead
Partial Charges Give Clues About Electron Flow
Draw The Ugly Version First
Organic Chemistry Study Tips: Learn the Trends
The 8 Types of Arrows In Organic Chemistry, Explained
Top 10 Skills To Master Before An Organic Chemistry 2 Final
Common Mistakes with Carbonyls: Carboxylic Acids... Are Acids!
Planning Organic Synthesis With "Reaction Maps"
Alkene Addition Pattern #1: The "Carbocation Pathway"
Alkene Addition Pattern #2: The "Three-Membered Ring" Pathway
Alkene Addition Pattern #3: The "Concerted" Pathway
Number Your Carbons!
The 4 Major Classes of Reactions in Org 1
How (and why) electrons flow
Grossman's Rule
Three Exam Tips
A 3-Step Method For Thinking Through Synthesis Problems
Putting It Together
Putting Diels-Alder Products in Perspective
The Ups and Downs of Cyclohexanes
The Most Annoying Exceptions in Org 1 (Part 1)
The Most Annoying Exceptions in Org 1 (Part 2)
The Marriage May Be Bad, But the Divorce Still Costs Money
9 Nomenclature Conventions To Know
Nucleophile attacks Electrophile
27 Case Studies of Successful O-Chem Students
Success Stories: How Corina Got The The "Hard" Professor - And Got An A+ Anyway
How Helena Aced Organic Chemistry
From a "Drop" To B+ in Org 2 – How A Hard Working Student Turned It Around
How Serge Aced Organic Chemistry
Success Stories: How Zach Aced Organic Chemistry 1
Success Stories: How Kari Went From C– to B+
How Esther Bounced Back From a "C" To Get A's In Organic Chemistry 1 And 2
How Tyrell Got The Highest Grade In Her Organic Chemistry Course
This Is Why Students Use Flashcards
Success Stories: How Stu Aced Organic Chemistry
How John Pulled Up His Organic Chemistry Exam Grades
Success Stories: How Nathan Aced Organic Chemistry (Without It Taking Over His Life)
How Chris Aced Org 1 and Org 2
Interview: How Jay Got an A+ In Organic Chemistry
How to Do Well in Organic Chemistry: One Student's Advice
"America's Top TA" Shares His Secrets For Teaching O-Chem
"Organic Chemistry Is Like..." - A Few Metaphors
How To Do Well In Organic Chemistry: Advice From A Tutor
Guest post: "I went from being afraid of tests to actually looking forward to them".
Comments
Comment section
98 thoughts on “3 Factors That Stabilize Carbocations”
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Hello James, thanks for the clear explanation.A question about the carbocation. We say that the more stable carbocation reacts with the nucleophile faster. Are we connecting the thermodynamic stability to the kinetics here?
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Hi Chenglin, I am assuming you are referring to the image under section 5.The overall kinetics of these reactions will be dictated by the formation of the carbocation, which is the rate-limiting step. Generally the more stable the carbocation, the lower will be the the activation energy for its formation (“late” transition state) and the faster the overall rate of reaction.
It should not be interpreted to mean that there is a relationship between the stability of the carbocation and the rate of the second (i.e. fast addition of nucleophile to carbocation) step.
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6. Cyclopropenyl cation being aromatic can be stored in bottle.but is it possible to store cyclopropyl methyl cation as it is more stable.
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7. Which carbocation is more stableCyclopropyl methyl cation or cyclopropenyl cation
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Cyclopropyl methyl. Cyclopropenyl quickly rearranges to allyl cation.
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8. thank you sir your articles are very hepful and they helped me to understand my archj-enemy O-chem better
THANK YOU!!!!
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9. From gas phase dissociation energies, the tert butyl carbocation is about 7 kcal/mol more stable (232 kcal/mol) than the benzyl carbocation (238 kcal/mol) but substituent effects can greatly change these numbers. Source: March’s Advanced Organic Chemistry 5th ed. Table 5.2 page 224.
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10. Hi Sir!I Hav a question.Which one is more stableBenzyllic cation or CH2(+)-cyclopropane??
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1. That is an EXCELLENT question and the data contradicts somewhat. Cyclopropylmethyl cations are generally considered to be more stable than benzyl. I’m looking for a better reference than just March 5th ed. p. 222, but the references therein are to good, but somewhat obscure, reviews. Hydrolysis rates suggest cyclopropylmethyl cations are more stable.
However another way to answer that is to look at 13-C NMR to determine the chemical shift of the carbocations. The more negative the chemical shift, the more unstable it is. The 2-cyclopropyl carbocation has a chemical shift of -86.8 ppm and the 2-phenylpropyl cation has a chemical shift of -61.1 indicating that the phenyl group is better at stabilizing. See
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Will a primary alkyl halide be able to undergo an SN1 reaction if it is stabilised by a neighbouring oxygen atom? Or will the carbocation still be too unstable to react in this way?
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Depends on what you mean by “neighboring”. If it’s directly attached to the same carbon (such as H3C-O-CH2Cl) then the oxygen will easily form a pi bond with C and the Cl- will be displaced easily. For an example see benzyloxymethyl chloride. (these things tend to be unstable)If by neighboring you mean an C=O on the carbon adjacent to the carbon bearing the carbocation, then this will be unstable.
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13. No matter where I surf the net… I’ll always end up here.Your way of teaching is just amazing…hats-off
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I hope this continues!
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14. Is it possible for a non-adjacent atom with a lone pair to stabilize a carbocation? There’s a question in Brown’s Organic Chemistry 8th edition that asks why CH2CHCOOH ( + HCl forms CH2ClCH2COOH rather than CH3CHClCOOH which would be expected due to the ordinarily greater stability of the secondary carbocation. I’m wondering if you can get the carbon backbone curling around upon itself ( so the lone pair on the hydroxyl oxygen can help to stabilize the primary carbocation?
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Sorry, an extra carbon snuck into those molecular models. The correct structure of the starting material is ( and the correct structure of my proposed stabilized carbocation is (
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I suppose this could also be a contributing resonance structure (
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2. Well what could happen is intramolecular nucleophilic attack to give a ring of some kind. “Anchimeric assistance”.
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15. Thank you so much, sir! You’re metaphor on money and electrons made the concept so much easier! More powers to you!
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16. Are there answers to the “apply the concept” questions?
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17. Dear James:
I have no problem with -NH2, -OH since we establish in EAS that they are electron donating in general. But i don’t understand why halides should stabilize the carbocation. It is said in all textbooks that the mistmatch between 3p and 2p atomic orbitals results in a diminished resonance delocalization, and winning of the inductive effect for halides, making them electron-withdrawing. So it removes electron density and creates a bigger positive charge in the intermediate of aromatic reaction. but we have the same halide and the same carbocation here (Except its not in a ring) but its now donating whats the difference? Thanks!
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19. So if you have a secondary carbocation that has a little bit of resonance stabilization and a tertiary carbocation (with no resonance stability), which is more stable? (My textbook says the secondary with resonance…)
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20. Hello, can you please tell me which is more stable carbocation…(CH3)3C or (C2H5)3C ?If the no of carbon atoms increases in an alkyl group…Its +I effect will decrease or increase ?
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Perhaps a sight increase in stability for tri-ethyl. The rate of ionization of the corresponding alkyl halides would tell you.
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21. I’m wondering if there an answers to the Apply questions at the bottom to check ourselves???
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22. Where are the ans of the examples?
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23. (CH3)2–C+ —COOH , can this resonate ? …i mean theres pi sigma and +ve charge conjugate system ….but yet i was doing a question and this wasn’t the answer.So why cant it resonate please answer
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The resonance form would end up with less than a full octet on oxygen, which is extremely unstable. It’s not a significant resonance form.
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2. No resonance stabilization. If you break the C=O bond to form a C=C bond you will leave behind a oxygen with only 6 electrons –> highly unstable.
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24. I don’t find any article on destabilization of carbanion
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Some factors that stabilize negative charge:
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25. Hi!
I was just wondering, which would be more stable then between a tertiatry carbocation and a carbocation stabilized by resonance? (like in #2?)
Thank you! Great article!
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26. Hey James….Why an intermediate with positively charged oxygen is less stable than a carbocation
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There are two types of intermediates with positively charged oxygen. The intermediate where oxygen has a full octet is OK (and generally speaking more stable than a carbocation). Intermediates where oxygen have less than a full octet are very unstable, because a very electronegative atom (oxygen) with less than a full octet will have tremendous potential energy (and thus instability) for pulling electrons toward the nucleus.
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2. By positively charged oxygen I mean an electron with 6 electrons. It’s a more electronegative element so there will be MUCH greater electron-affinity pulling electrons toward the nucleus. Very unstable situation.
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27. Hi James,
I would like to pick your brain a little bit. I have been banging my head against the wall with this one and I don’t seem to figure it out.Let’s say you have two secondary amines. In the first one, one substituent is a propargyl (prop-2-yn) group and the second one is methyl. In the second amine, one substituent is an (indol-2-yl)methyl group (amine is bonded through a methylene group to the position 2 of indole) and the second one is methyl. Now, in both cases a secondary carbocation is formed next to the amine nitrogen. Which one should be more stable?
In both cases the nitrogen stabilizes the positive charge via lone electron donation, but what about the alkynyl and indolyl moiety? I suppose they should both have stabylizing effects via delocalization but which one would stabilize the charged species more? What about the inductive effects? Should they play some significant roles in this case? I am so confused…
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28. Hi James,Thanks for a neat explanation. I am not an organic chemist and I have a question about stabilization of carbocations. Do you think it is probable to stabilize a carbocation by putting it next to sth that can stabilize it? Like solvation effects, or some negatively charged species?Like electrostatic stabilization?In all these 3 examples, carbocation is stabilized via intramolecular effects, how about intermolecular stabilization?Thanks.
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Carbocations are relatively stable in superacid solution. That’s how George Olah studied them, and it helped him to win the Nobel Prize.
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Thanks much.
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29. Organic chemistry has always been the most exiting and beautiful subject for a geek like me and all these articles inspire me to go more in depth of this subject.
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amen to that brother
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30. Hi there, why is a secondary allylic carbocation more stable than a tertiary carbocation? Thank you.
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Hi Monica
There’s several factors that are not always easy to judge by just looking at them – we need to do experiments. For example we know that carbocations increase in stability going from primary to secondary to tertiary.
We also know that carbocations increase in stability if they are resonance stabilized.
However – what factor is more important? substitution pattern or resonance?
There is no way to figure this out just by looking at it. We have to do experiments (and we do!) [by measuring “ionization rates”]
Those experiments tell us that secondary allylic carbocations are slightly easier to form than ordinary (non resonance stabilized) tertiary carbocations.
Why is that? Good question (and this is where it can get complicated). Probably the fact that there is more electron density being donated from an adjacent p orbital than there is from the [hyperconjugation] C-H bonds adjacent to the tertiary carbocation.
These factors can be in delicate balance. If I can make an analogy, it’s a bit like sports teams. What’s more important in football, to have a good offence or a good defence? Well, they’re both important. How do we know the relative importance of each? By playing a LOT of games and trying to figure it out by looking at the data. Thankfully with chemistry one mole of material gives us the chance to play 6x 10^23 “games” so we can figure this out pretty reliably.
hope this helps! James
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31. Hi,I was wondering if you could post the answers to these sample problems please? I’m doing them, but I have no way of checking if it’s right.Thank-you,TA Nguyen
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Hi, in each case the first carbocation is more stable. This applies the 3 factors we learned that stabilize carbocations.
tertiary carbocation more stable than secondaryallylic (resonance stabilized) carbocation more stable than non resonance stabilized carbocationcarbocation adjacent to atom with lone pairs (oxygen) more stable than carbocation not adjacent to atom with lone pairs.
Hope this helpsJames
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32. hello…i have a question can we say that the resonanse factor is more effective factor except of when the aromaticity is endangered?
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33. Can you please tell me the stability order of tertiary,benzyl and allyl free radical?
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Try looking at the strength of tertiary, benzyl, and allyl C-H bonds. Since C-H bond strengths measure homolytic cleavage, then you will then get the stability of the radicals. The weaker the C-H bond the more stable the radical.
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34. Hi! Thanks for your help : )
I have a question. Would a secondary carbocation be considered more stable than a primary carbocation bonded with a halogen? It’s on a practice test and I’m a little confused o_O
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Hard to say without seeing the exact example, but my guess is that the latter situation would be more stable, since the halogen can donate a lone pair and every atom on the molecule can have a full octet. This is a more stable situation than a free carbocation where there is an empty orbital.
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35. First of all ,thanks for explaining this so well.But, can u please tell me , generally which effect counts more, Inductive or Hyperconjugation?Like for example, if you have ethyl carbocation and if you have 2 methyl propane carbocation (primary carbocation) which will be more stable?
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It’s far more powerful to look at stabilization from the perspective of hyperconjugation, but it’s far easier to explain it from the perspective of inductive effects. If you are a major in a chemistry program I would take the time to learn hyperconjugation and apply that to your studies. It’s a very powerful concept.
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36. can u please explain why 1,3,5 hept-triene carbo cation (+ on sp3 carbon) is more stable than triphenyl carbo cation??
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Aromaticity. See:
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37. This was so much help! Organic chem is a pain, are there more explanations of other orgo subjects?like spectroscopy, I really need help on that and could use a good website like this one
Thanks.
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38. Had a hard time finding bare-bone explanation of cation stability. Thanks! Definitely bookmarking your website.
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39. Thanks. I’m now studying for my Organic Chem exam next week and this is really helpful for my studies
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40. I have only a little problem . well, which counts more, the resonance stabilisation or if its primary or secondary Carbon? Due this fact, which is more stable, +CH2-CH=CH2 or CH3CH(+)CH3? Thank you in advance xD
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Good question. In the examples you cited, the resonance counts more.
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41. Thank you very much, this has saved my life. Appreciate it.
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42. actually my main ques was about pinnacol pinnacolone rearrangement.H+ attacks on that OH which yields a more stable carbocationso which O should it attack?OH OHI ICH3—C—C—-C2H5I ICH3 C2H5
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oops the server omitted the spaces in the compound which messed it all up..it is
(CH3)2–C(OH)————-C(OH)(C2H5)2
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43. out of ch3ch2ch2+ and ch3ch2+ which is more stable carbocationboth are primary butthe former one has a bulkier alkyl group and hence more inductive effectand the latter one has more no of alpha hydrogen and hence more no of hyperconjugative structures..both the reasons are clashing……!!!!!we expect the first one out of intuition but how can we forget the fact that hyperconjugaion is more dominant tha inductive effect?
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Both are primary carbocations; they will have very similar stabilities. The propyl carbocation can rearrange through a hydride shift to give a secondary carbocation.
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so the conclusion is that propyl carbocation is more stable….bcz it can rearrange
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No – once it’s rearranged, we’re discussing a different carbocation entirely.
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44. What about the “bent or umbrella bond”? Don’t you think that bent bond participate in the stability of carbocations?
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45. Can you add carbocation shift as well to make this complete.
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Discussed in the series on rearrangments.
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46. Oh man it is totally awesome. You told every thought tat we have while studying! And my every doubt is gone now !!n!n!n!
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47. Bro, you make this shit easy. You are seriously awesome!
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48. this article rly helped me alot !! m glad u posted it :D
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49. Good article!
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50. Great article.
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51. Good explanation one can eaisly understand by reading this article
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Glad you found it helpful.
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52. can you please explain that if I have a benzyl carbocation and a t-butyl carbocationwhich will be more stable1st has stability due to benzyl resonanceand 2nd has 9 possible hyperconjugative structuresplease answer
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Dear Jeetesh! You should know that resonance is more pronounce than hyperconjugation and will stabilize the cation more as compare to hyperconjugation.
Reply
yes Iqbal,resonance is dominating mainly…..bt here it has been found that t-butyl is more stable…..
Reply
Kushal, do you have a reference for that?
Reply
Morrison boyd says this . (
As one of the commenters says, small changes in substitution can tip the balance either way.
I do not have an experimental reference, but in “Electron Flow In Organic Chemistry” Paul Scudder claims on page 65 in his “carbocation stability ranking” chart that “tertiary cation” is more stable than “benzyl cation” (the benzyl shown being primary, i.e. two H’s).
I’d imagine that a tertiary benzyl cation, the sp2 carbon bearing a phenyl group and two alkyl groups, should certainly be more stable than a tertiary cation bearing three alkyl groups (both have two hyperconjugations, however the aromatic pi donor beats the third hyperconjugation).
A secondary benzyl cation vs tertiary alkyl cation would be a little more ambiguous.
4. Dear all, carbocation stability could be inferred from the hydride affinity in gas phase. Please see Advanced Organic Chemistry: Part A 5th edition by Carey and Sundberg, Table 3.10., page 303. The lower the hydride affinity, the more stable the carbocation. (239 kcal/mol for benzylic cation VS 237 kcal/mol for t-Butyl cation)
5. I understand Rich’s explanation. It’s satisfying. Thank You.
2. This is because the phenyl groups are not in a single plane and for resonance to occur, the R groups should lie in the same plane. This distortion of shape to the compound happens due to steric hinderance of the phenyl groups in the compound
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2. Its an exceptional case, t-butyl carbocation is more stable …..
Reply
3. Benzyl carbocatian is more stable because of delocalization of charge…
Reply
53. very simple way to understand chemistry
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54. information about organic chemistry
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55. To explain science in simplest way is an art.you have done it!
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good tutorial.
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12501 | https://sites.und.edu/timothy.prescott/apex/webold/apex.Ch11.S3.html | 11 Vectors11.2 An Introduction to Vectors11.4 The Cross Product
11.3 The Dot Product
The previous section introduced vectors and described how to add them together and how to multiply them by scalars. This section introduces a multiplication on vectors called the dot product.
Definition 11.3.1 Dot Product
1.
Let and in . The dot product of and , denoted , is
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2. 2.
Let and in . The dot product of and , denoted , is
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Note how this product of vectors returns a scalar, not another vector.
We practice evaluating a dot product in the following example, then we will discuss why this product is useful.
Example 11.3.1 Evaluating dot products
1.
Let , in . Find .
2. 2.
Let and in . Find .
1.
Using Definition 11.3.1, we have
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2. 2.
Using the definition, we have
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The dot product, as shown by the preceding example, is very simple to evaluate. It is only the sum of products. While the definition gives no hint as to why we would care about this operation, there is an amazing connection between the dot product and angles formed by the vectors. Before stating this connection, we give a theorem stating some of the properties of the dot product.
Theorem 11.3.1 Properties of the Dot Product
Let , and be vectors in or and let be a scalar.
1.
Commutative Property
2. 2.
Distributive Property
3. 3.
4. 4.
5. 5.
The last statement of the theorem makes a handy connection between the magnitude of a vector and the dot product with itself. Our definition and theorem give properties of the dot product, but we are still likely wondering “What does the dot product mean?” It is helpful to understand that the dot product of a vector with itself is connected to its magnitude.
The next theorem extends this understanding by connecting the dot product to magnitudes and angles. Given vectors and in the plane, an angle is clearly formed when and are drawn with the same initial point as illustrated in Figure 11.3.1(a). (We always take to be the angle in as two angles are actually created.)
††margin: (a) (b) Figure 11.3.1: Illustrating the angle formed by two vectors with the same initial point.
The same is also true of 2 vectors in space: given and in with the same initial point, there is a plane that contains both and . (When and are co-linear, there are infinite planes that contain both vectors.) In that plane, we can again find an angle between them (and again, ). This is illustrated in Figure 11.3.1(b).
The following theorem connects this angle to the dot product of and .
Theorem 11.3.2 The Dot Product and Angles
Let and be vectors in or . Then
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where , , is the angle between and .
When is an acute angle (i.e., ), is positive; when , ; when is an obtuse angle (), is negative. Thus the sign of the dot product gives a general indication of the angle between the vectors, illustrated in Figure 11.3.2.
Figure 11.3.2: Illustrating the relationship between the angle between vectors and the sign of their dot product.
We can use Theorem 11.3.2 to compute the dot product, but generally this theorem is used to find the angle between known vectors (since the dot product is generally easy to compute). To this end, we rewrite the theorem’s equation as
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Watch the video: Vectors: The Dot Product from
We practice using this theorem in the following example.
††margin: Figure 11.3.3: Vectors used in Example 11.3.2.
Example 11.3.2 Using the dot product to find angles
Let , and , as shown in Figure 11.3.3. Find the angles , and .
SolutionWe start by computing the magnitude of each vector.
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We now apply Theorem 11.3.2 to find the angles.
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--- |
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We see from our computation that , as indicated by Figure 11.3.3. While we knew this should be the case, it is nice to see that this non-intuitive formula indeed returns the results we expected.
We do a similar example next in the context of vectors in space.
††margin: Figure 11.3.4: Vectors used in Example 11.3.3.
Example 11.3.3 Using the dot product to find angles
Let , and , as illustrated in Figure 11.3.4. Find the angle between each pair of vectors.
Solution
1.
Between and :
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--- |
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2. 2.
Between and :
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--- |
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3. 3.
Between and :
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--- |
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While our work shows that each angle is , i.e., , none of these angles looks to be a right angle in Figure 11.3.4. Such is the case when drawing three-dimensional objects on the page.
All three angles between these vectors was , or . We know from geometry and everyday life that angles are “nice” for a variety of reasons, so it should seem significant that these angles are all . Notice the common feature in each calculation (and also the calculation of in Example 11.3.2): the dot products of each pair of angles was 0. We use this as a basis for a definition of the term orthogonal, which is essentially synonymous to perpendicular.
Definition 11.3.2 Orthogonal
Vectors and are orthogonal if their dot product is 0.
††margin: Note: The term perpendicular originally referred to lines. As mathematics progressed, the concept of “being at right angles to” was applied to other objects, such as vectors and planes, and the term orthogonal was introduced. It is especially used when discussing objects that are hard, or impossible, to visualize: two vectors in 5-dimensional space are orthogonal if their dot product is 0. It is not wrong to say they are perpendicular, but common convention gives preference to the word orthogonal.
Example 11.3.4 Finding orthogonal vectors
Let and .
1.
Find two vectors in that are orthogonal to .
2. 2.
Find two non-parallel vectors in that are orthogonal to .
Solution
1.
Recall that a line perpendicular to a line with slope has slope , the “opposite reciprocal slope.” We can think of the slope of as , its “rise over run.” A vector orthogonal to will have slope . There are many such choices, though all parallel:
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2. 2.
There are infinite directions in space orthogonal to any given direction, so there are an infinite number of non-parallel vectors orthogonal to . Since there are so many, we have great leeway in finding some.
One way is to arbitrarily pick values for the first two components, leaving the third unknown. For instance, let . If is to be orthogonal to , then , so
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So is orthogonal to . We can apply a similar technique by leaving the first or second component unknown.
Another method of finding a vector orthogonal to mirrors what we did in part 1. Let . Here we switched the first two components of , changing the sign of one of them (similar to the “opposite reciprocal” concept before). Letting the third component be 0 effectively ignores the third component of , and it is easy to see that
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Clearly and are not parallel.
††margin: (a) (b) Figure 11.3.5: Developing the construction of the orthogonal projection.
An important construction is illustrated in Figure 11.3.5, where vectors and are sketched. In part (a), a dotted line is drawn from the tip of to the line containing , where the dotted line is orthogonal to . In part (b), the dotted line is replaced with the vector and is formed, parallel to . It is clear by the diagram that . What is important about this construction is this: is decomposed as the sum of two vectors, one of which is parallel to and one that is perpendicular to . It is hard to overstate the importance of this construction (as we’ll see in upcoming examples).
The vectors , and as shown in Figure 11.3.5 (b) form a right triangle, where the angle between and is labeled . We can find in terms of and .
Using trigonometry, we can state that
| | |
--- |
| | (11.3) |
We also know that is parallel to to ; that is, the direction of is the direction of , described by the unit vector . The vector is the vector in the direction with magnitude :
| | |
--- |
| | |
| Replace using Theorem 11.3.2: |
| |
| |
| Now apply Theorem 11.3.1. |
| |
Since this construction is so important, it is given a special name.
Definition 11.3.3 Orthogonal Projection
Let and be given, where . The orthogonal projection of onto , denoted , is
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| |
††margin: (a) (b) Figure 11.3.6: Graphing the vectors used in Example 11.3.5.
Example 11.3.5 Computing the orthogonal projection
1.
Let and . Find , and sketch all three vectors with initial points at the origin.
2. 2.
Let and . Find , and sketch all three vectors with initial points at the origin.
Solution
1.
Applying Definition 11.3.3, we have
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--- |
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Vectors , and are sketched in Figure 11.3.6(a). Note how the projection is parallel to ; that is, it lies on the same line through the origin as , although it points in the opposite direction. That is because the angle between and is obtuse (i.e., greater than ).
2. 2.
Apply the definition:
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--- |
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These vectors are sketched in Figure 11.3.6(b).
Consider Figure 11.3.7 where the concept of the orthogonal projection is again illustrated. It is clear that
| | |
--- |
| | (11.4) |
As we know what and are, we can solve for and state that
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| |
††margin: Figure 11.3.7: Illustrating the orthogonal projection.
This leads us to rewrite Equation (11.4) in a seemingly silly way:
| |
| |
This is not nonsense, as pointed out in the following Key Idea. (Notation note: the expression “ ” means “is parallel to .” We can use this notation to state “ ” which means “ is parallel to .” The expression “ ” means “is orthogonal to ,” and is used similarly.)
Key Idea 11.3.1 Orthogonal Decomposition of Vectors
Let and be given. Then can be written as the sum of two vectors, one of which is parallel to , and one of which is orthogonal to :
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We illustrate the use of this equality in the following example.
Example 11.3.6 Orthogonal decomposition of vectors
1.
Let and as in Example 11.3.5. Decompose as the sum of a vector parallel to and a vector orthogonal to .
2. 2.
Let and as in Example 11.3.5. Decompose as the sum of a vector parallel to and a vector orthogonal to .
Solution
1.
In Example 11.3.5, we found that . Let
| |
| |
Is orthogonal to ? (I.e, is ?) We check for orthogonality with the dot product:
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| |
Since the dot product is 0, we know . Thus:
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--- |
| | |
| | |
2. 2.
We found in Example 11.3.5 that . Applying the Key Idea 11.3.1, we have:
| |
| |
We check to see if :
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| |
Since the dot product is 0, we know the two vectors are orthogonal. We now write as the sum of two vectors, one parallel and one orthogonal to :
| | |
--- |
| | |
| | |
We give an example of where this decomposition is useful.
Example 11.3.7 Orthogonally decomposing a force vector
Consider Figure 11.3.8(a), showing a box weighing 50 lb on a ramp that rises 5 ft over a span of 20 ft. Find the components of force, and their magnitudes, acting on the box (as sketched in part (b) of the figure):
1.
in the direction of the ramp, and
2. 2.
orthogonal to the ramp.
††margin: (a) (b) Figure 11.3.8: Sketching the ramp and box in Example 11.3.7. Note: The vectors are not drawn to scale.
SolutionAs the ramp rises 5 ft over a horizontal distance of 20 ft, we can represent the direction of the ramp with the vector . Gravity pulls down with a force of 50 lb, which we represent with .
1.
To find the force of gravity in the direction of the ramp, we compute :
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--- |
| | |
| |
| |
The magnitude of is . Though the box weighs 50 lb, a force of about 12 lb is enough to keep the box from sliding down the ramp.
2. 2.
To find the component of gravity orthogonal to the ramp, we use Key Idea 11.3.1.
| | |
--- |
| | |
| |
The magnitude of this force is lb. In physics and engineering, knowing this force is important when computing things like static frictional force. (For instance, we could easily compute if the static frictional force alone was enough to keep the box from sliding down the ramp.)
Application to Work
In physics, the application of a force to move an object in a straight line a distance produces work; the amount of work is , (where is in the direction of travel). The orthogonal projection allows us to compute work when the force is not in the direction of travel.
Consider Figure 11.3.9, where a force is being applied to an object moving in the direction of . (The distance the object travels is the magnitude of .) The work done is the amount of force in the direction of , , times :
††margin: Figure 11.3.9: Finding work when the force and direction of travel are given as vectors.
| | |
--- |
| | |
| |
| |
| |
The expression will be positive if the angle between and is acute; when the angle is obtuse (hence is negative), the force is causing motion in the opposite direction of , resulting in “negative work.” We want to capture this sign, so we drop the absolute value and find that .
Definition 11.3.4 Work
Let be a constant force that moves an object in a straight line from point to point . Let . The work done by along is .
††margin: Figure 11.3.10: Computing work when sliding a box up a ramp in Example 11.3.8.
Example 11.3.8 Computing work
A man slides a box along a ramp that rises 3 ft over a distance of 15 ft by applying 50 lb of force as shown in Figure 11.3.10. Compute the work done.
SolutionThe figure indicates that the force applied makes a angle with the horizontal, so . The ramp is represented by . The work done is simply
| |
| |
Note how we did not actually compute the distance the object traveled, nor the magnitude of the force in the direction of travel; this is all inherently computed by the dot product!
The dot product is a powerful way of evaluating computations that depend on angles without actually using angles. The next section explores another “product” on vectors, the cross product. Once again, angles play an important role, though in a much different way.
Exercises 11.3
Terms and Concepts
1.
The dot product of two vectors is a , not a vector.
2. 2.
How are the concepts of the dot product and vector magnitude related?
3. 3.
How can one quickly tell if the angle between two vectors is acute or obtuse?
4. 4.
Give a synonym for “orthogonal.”
Problems
In Exercises 5–10, find the dot product of the given vectors.
5.
,
2. 6.
,
3. 7.
,
4. 8.
,
5. 9.
,
6. 10.
,
7. 11.
Create your own vectors , and in and show that .
8. 12.
Create your own vectors and in and scalar and show that .
In Exercises 13–16, find the measure of the angle between the two vectors in both radians and degrees.
13.
,
2. 14.
,
3. 15.
,
4. 16.
,
In Exercises 17–20, a vector is given. Give two vectors that are orthogonal to .
17.
18.
19.
20.
In Exercises 21–26, vectors and are given. Find , the orthogonal projection of onto , and sketch all three vectors on the same axes.
21.
,
2. 22.
,
3. 23.
,
4. 24.
,
5. 25.
,
6. 26.
,
In Exercises 27–32, vectors and are given. Write as the sum of two vectors, one of which is parallel to and one of which is perpendicular to . Note: these are the same pairs of vectors as found in Exercises 21–26.
27.
,
2. 28.
,
3. 29.
,
4. 30.
,
5. 31.
,
6. 32.
,
7. 33.
A 10lb box sits on a ramp that rises 4ft over a distance of 20ft. How much force is required to keep the box from sliding down the ramp?
8. 34.
A 10lb box sits on a 15ft ramp that makes a angle with the horizontal. How much force is required to keep the box from sliding down the ramp?
9. 35.
How much work is performed in moving a box horizontally 10ft with a force of 20lb applied at an angle of to the horizontal?
10. 36.
How much work is performed in moving a box horizontally 10ft with a force of 20lb applied at an angle of to the horizontal?
37.
How much work is performed in moving a box up the length of a ramp that rises 2ft over a distance of 10ft, with a force of 50lb applied horizontally?
12. 38.
How much work is performed in moving a box up the length of a ramp that rises 2ft over a distance of 10ft, with a force of 50lb applied at an angle of to the horizontal?
13. 39.
How much work is performed in moving a box up the length of a 10ft ramp that makes a angle with the horizontal, with 50lb of force applied in the direction of the ramp?
14. 40.
For any two vectors and use the properties of the dot product to show that
15. 41.
For any two vectors and show that Interpret this as a statement about parallelograms.
16. 42.
Consider two nonzero vectors and and the angle between them . The vectors , , and form the triangle as follows. (a) Use the Law of Cosines to show that (b) Use (a) and the previous problem to conclude the formula
17. 43.
Suppose we know that , , and the angle between and is . Determine the following. (a) . (b) . (c) . (d) .
18. 44.
Show that the two diagonals of a parallelogram intersect in right angles if and only if all four sides of the parallelogram have the same length.
19. 45.
Show that for any two vectors and we have This is called the Cauchy-Schwarz inequality.
20. 46.
Show that for any two vectors and we have This is called the triangle inequality. Explain the name. |
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12503 | https://www.tutorchase.com/answers/igcse/chemistry/what-is-the-significance-of-subscripts-in-chemical-formulae | What is the significance of subscripts in chemical formulae?
Subscripts in chemical formulae indicate the number of atoms of each element present in a compound.
In a chemical formula, each element is represented by its chemical symbol, and the number of atoms of each element in the compound is shown as a subscript. For instance, in the formula for water, H2O, the subscript '2' after the 'H' indicates that there are two hydrogen atoms in each molecule of water. The oxygen atom does not have a subscript, which means there is one oxygen atom in each water molecule.
Subscripts are crucial in understanding the composition of a compound. They provide information about the ratio of atoms in a compound, which is fundamental in stoichiometry - the study of the quantitative relationships between the amounts of reactants used and products formed in a chemical reaction. For example, the formula for glucose, C6H12O6, tells us that one molecule of glucose contains six carbon atoms, twelve hydrogen atoms, and six oxygen atoms.
Moreover, subscripts can also indicate the state of matter of a substance in a reaction. For instance, (s) for solid, (l) for liquid, (g) for gas, and (aq) for aqueous. These are not to be confused with the subscripts that denote the number of atoms.
It's important to note that subscripts should never be changed when balancing chemical equations. Changing a subscript alters the identity of the substance, while balancing an equation only involves adjusting the number of molecules or ions of a substance, which is indicated by coefficients, not subscripts.
In summary, subscripts in chemical formulae play a vital role in conveying the precise composition of compounds, aiding in the understanding of chemical reactions and stoichiometry.
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12505 | https://www.jisilu.cn/question/507310?gopage-true__page-2__item_id=5111092 | a8到a9的路径 - 集思录
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a7-a8靠几十只股票，感觉一个股超过50w就hold不住，试了试im吃贴水，信仰不够坚定，感觉高位也是贴水换时间，可转债大饼，120以上的感觉和股票差不多，以下的又慢靠脉冲。etf倒是可以，就是更考验看大势能力。
发表时间 2025-03-15 10:54 来自福建
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赞同来自: 老白汾、woshishui2016、石瓦坡格劳秀斯、投资旗舰、sunliner、一条小虫子、Abendusj、GODSAVEME、跑得快一点、qexce、萝卜青菜叶、finesz、从心出发NOBODY、行走的MM、hnr88、a416236737、逆流挽舟、jssfly、hknj、nainai23、雷蒙德91、斗南一人、J862327869、fanwen272、A0吴应宏、J311389167、兰风、Lfk168、Ponyma、在路上sss、J267342191、我是兜爸2016、眼里的星星、刘二彪、yolandalchan、dongdongw、wjwemail、cddw、hwyfbfb、瑞宇堂、菜叶子w、XIAOHULI92、刺目青虹、willeagle、滴水成海、滚雪球2020、caopanshou日记、yonghu、韭小白、NichoLin、作手十一、时间过桥、新欣欣向荣、J593036432、Y15016183958、alongside、dengdai、梦想财务自由、Q5945、superduo、ycw448、pyd001、blank赵、南海PP、丁一白、彩虹鸽、kenlee、Gerry1012010、我要开宝箱cc、云霏霏、土豆牛仔、布拉布拉、wustan、Isxq、snowea、piaji、巴木、mahout、渣渣渣渣晖蜗牛、夺命胶剪脚、执悟执、jxjfjfjckckkc、NeverFix、风0114、wugencao、弓隐、吴迅杰、dang8804、wwwkeke、sadday、farby、huihuiluo、zhuzi51、天旋111、kolanta、迅雷不及掩er、neverfailor、xiuzhenxw、hp0534、安静的小白、丢失的十年、有木有222、Romi、求是123、股息有道、k买买买、财哥投资、黑海豚猪、zhygurao、一骑绝尘1993、比不做强、学888、陈兴华、梅南居士、当下明月、yanhualuoqi、genamax、陪戎校尉、鱼和水、kanglue、致行以知、美好回忆、myrazcs、bendison、qdxmz、老韭菜鸭、hshpangpang、鸡叨叨、狂奔的奶牛、wz2105更多 »
429 个回复
0
alongside - 为无为，事无事，味无味
赞同来自:
@jian
阿段还用忽悠粉丝？他都不让别人跟贴。你的认知不会是，他高攀不上集思录了？
集思录粉丝太少，不值得在集思录炫耀。。。
2025-03-25 20:48 来自江苏引用
0
兜里响铛铛
赞同来自:
@扫地小僧
搭顺风车问问，如何实现A9到A10的路径？ 目前自己的交易模式，A9几乎已经快容不下了。。好难。。。再顺便问问，A9到A10的意义？
人生总要有点追求，另，巴菲特买比亚迪等很多十倍百倍增长的投资你都没有实现过，不检讨提高吗？我常常思考，为什么人家不但选中了，还拿住了，我的水平怎么差那么多
2025-03-25 20:17 来自陕西引用
3
twam - 捂股丰登
赞同来自: happysam2018、lucylv、alongside
@alongside
2000 年互联网泡沫破裂，网易股价暴跌，还深陷财务丑闻和美国投资者的集体诉讼，股价一度跌至 0.48 美元，甚至面临退市风险。投资过程：
段永平发现网易的现金平均到每股能分到 2 美元，且每股能盈利 0.53 美元，价值被严重低估。同时，丁磊向他提及网易正发力游戏市场，段永平安排人深入调研网易游戏的竞争力，获得了满意的反馈。他还咨询律师关于集体诉讼可能的赔偿规模，确定风险可控。大胆买入：2001...
对于极度看好的，也别轻易上杠杆
2025-03-25 19:23 来自福建引用
2
twam - 捂股丰登
赞同来自: happysam2018、eaglex
@eaglex
写的真好 文笔好 情感真
而且确实是我过去三年的真实感受
虽然过去三年投资没赚什么钱 但看到身边大部分持有房产的大跌而自己房产占比很低
心态就很很安稳 因为我的财富社会排名一定是不降反升的
一样…………23年初在高峰把自己老家房子抛售，准备买厦门，还好没买，一进一出300w
2025-03-25 19:21 来自福建引用
3
eaglex - 不过是挑个自己喜欢的结局
赞同来自: happysam2018、f2017、好奇心135
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。
许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
写的真好 文笔好 情感真
而且确实是我过去三年的真实感受
虽然过去三年投资没赚什么钱 但看到身边大部分持有房产的大跌而自己房产占比很低
心态就很很安稳 因为我的财富社会排名一定是不降反升的
2025-03-25 17:51 来自云南引用
40
易尔奇 - 安待久 渐息散
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“给时光以生命，而非给生命以时光”；好！虎躯一震。
小时候看过《百万英镑》的电影，形象地看到钱怎样作用于同一个人的不同境遇；
2009年，偶尔发现挣钱虽辛苦却没那么艰难了，不是本事，是四万亿以后钱毛了。
2014年，曾在笔记本上分别以年化10%20%和30%收益率预算过股市资产增值的时间表和路线图；
2016年，一个发小来看我，言谈中可能是我过于急功近利，他劝我要放下，我脱口而出“还没拿起何以放下？”；
2023年，本职现金流投入+投资增值收入，双轮驱动，股市绝对值十年十倍。
2024年，我去看那位发小，此时他已从某上市公司法务副总裁的岗位病退，天天在院子里摆弄金弹子为乐。他提起我们二十几岁时的一个梗，“如果突然中了100万的彩票怎么办？”——我当时说存银行当作没发生。
今天看到这个帖子“A8到A9的路径”；我的想法和办法只有一个字：信。信则灵，从年轻到中年，我真信的东西大抵都实现了。A9指日可待，时间长短而已。
我内心还附加了一个愿望：资产每上一个台阶就匿名象征性地捐一笔款。2022年已捐过一次。
其实A7A8A9都是数字游戏，对我这种物质愿望不高的土包子来说，只是想给自己青葱岁月一个交待罢了。
既然无可奈何成了全职股民，那么，炒股不识萧牧彪，便称英雄也枉然。是吧？
2025-03-25 17:46修改 来自四川引用
2
酱油面
赞同来自: happysam2018、alongside
@alongside
2000 年互联网泡沫破裂，网易股价暴跌，还深陷财务丑闻和美国投资者的集体诉讼，股价一度跌至 0.48 美元，甚至面临退市风险。投资过程：
段永平发现网易的现金平均到每股能分到 2 美元，且每股能盈利 0.53 美元，价值被严重低估。同时，丁磊向他提及网易正发力游戏市场，段永平安排人深入调研网易游戏的竞争力，获得了满意的反馈。他还咨询律师关于集体诉讼可能的赔偿规模，确定风险可控。大胆买入：2001...
要复制，你得先有资源（尤数人脉），否则无从谈起
一介小散，能和马化腾在同一屋子聊天么？或者丁磊？
2025-03-25 17:21 来自云南引用
0
起名不难
赞同来自:
最好用美元或黄金重量计算
2025-03-25 17:15 来自北京引用
2
marshalgo
赞同来自: happysam2018、alongside
@alongside
2000 年互联网泡沫破裂，网易股价暴跌，还深陷财务丑闻和美国投资者的集体诉讼，股价一度跌至 0.48 美元，甚至面临退市风险。投资过程：段永平发现网易的现金平均到每股能分到 2 美元，且每股能盈利 0.53 美元，价值被严重低估。同时，丁磊向他提及网易正发力游戏市场，段永平安排人深入调研网易游戏的竞争力，获得了满意的反馈。他还咨询律师关于集体诉讼可能的赔偿规模，确定风险可控。大胆买入：2001...
没办法他元婴突破了
2025-03-25 16:56 来自河南引用
2
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: happysam2018、alongside
@alongside
2000 年互联网泡沫破裂，网易股价暴跌，还深陷财务丑闻和美国投资者的集体诉讼，股价一度跌至 0.48 美元，甚至面临退市风险。投资过程：
段永平发现网易的现金平均到每股能分到 2 美元，且每股能盈利 0.53 美元，价值被严重低估。同时，丁磊向他提及网易正发力游戏市场，段永平安排人深入调研网易游戏的竞争力，获得了满意的反馈。他还咨询律师关于集体诉讼可能的赔偿规模，确定风险可控。大胆买入：2001...
元婴老怪怎么会控制不住融资？控制不住融资怎么化婴的？资产负债管理和现金流管理是大乘期就要解决的问题！他们控制不住的是自己的命数！
2025-03-25 16:57修改 来自新疆引用
0
henze
赞同来自:
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
感谢分享，真知灼见
2025-03-25 16:43 来自江苏引用
4
jian - 淡淡的名贵
赞同来自: happysam2018、国富同学、蓝骑士、蝶恋火2
@alongside
这里是集思录，忽悠不到多少粉丝的...所以段没有来集思录“传授经验”...
阿段还用忽悠粉丝？他都不让别人跟贴。你的认知不会是，他高攀不上集思录了？
2025-03-25 16:39 来自北京引用
4
alongside - 为无为，事无事，味无味
赞同来自: happysam2018、非凡猪、YmoKing、好奇心135
2000 年互联网泡沫破裂，网易股价暴跌，还深陷财务丑闻和美国投资者的集体诉讼，股价一度跌至 0.48 美元，甚至面临退市风险。投资过程：
段永平发现网易的现金平均到每股能分到 2 美元，且每股能盈利 0.53 美元，价值被严重低估。同时，丁磊向他提及网易正发力游戏市场，段永平安排人深入调研网易游戏的竞争力，获得了满意的反馈。他还咨询律师关于集体诉讼可能的赔偿规模，确定风险可控。大胆买入：2001 年底，段永平用 1 美元的价格买入大量网易股票，不仅投入自己的 100 万美元，还借了 100 万，最终持有 205 万股，占网易总股本的 6.8%。
2003 年网易股价涨到 70 美元，后来过了 100 美元他才陆续出手，这笔投资让他赚取 1 亿美金，也成为他投资生涯的成名战。
......
这种估计百年一遇的机会，100%杠杆，怎么复制？
很多元婴老怪陨落在杠杆上... 同样是1美100%杠杆买入，买早了，跌倒0.48美元，陨落...
2025-03-25 16:22修改 来自江苏引用
0
alongside - 为无为，事无事，味无味
赞同来自:
这里是集思录，忽悠不到多少粉丝的...
所以段没有来集思录“传授经验”...
俺用豆包总结了一下，哈哈哈：
段永平从0到千亿的投资跨越，主要源于以下几点：
深刻的价值投资理念：秉持“好生意、好公司、好价格” + “本分”的理念。寻找有宽广深厚“护城河”、持续竞争优势和盈利能力的好生意，拥有诚信能干管理团队的好公司，同时在价格合适时出手。坚持本分，即诚信、守规矩、踏实经营，认为本分的企业才能基业长青，值得长期投资。
精准的投资分析能力：善于在市场危机中发现被错杀的优质企业。如在互联网泡沫破裂后网易股价暴跌、面临退市风险时，深入研究发现其游戏业务潜力和价值被低估，大胆买入，获得超百倍回报。能洞察优秀企业的商业模式和长期发展潜力，像投资苹果，认可其将产品做到极致的模式、强大的品牌号召力、卓越的用户体验以及持续创新能力，长期持有获得高额收益。还具备对困境反转企业的准确判断能力，如投资UHAL公司，在其破产保护时经调研发现核心业务运营良好，买入后获得丰厚回报。
严格的自我约束和风险控制：段永平深知自己的能力圈，坚持“看不懂的不投，和价值观不符的不投，10年内用不到的钱才能拿来投”。他不盲目跟风，不做不懂的投资，如做空百度亏损后，认识到做空是投机行为不可取，更加坚定遵循巴菲特“不做空”原则。投资中犯错后能及时反思改正，如投资天然气指数UNG等发现问题后，亏钱了结，认识到投资前对标的深入了解的重要性。
2025-03-25 16:06 来自江苏引用
2
alongside - 为无为，事无事，味无味
赞同来自: happysam2018、XJAJX
@acgt
段永平上千亿了，不也在雪球天天发帖。最近用零花钱买了点NVDA然后卖个 covered call ，还发了十几个帖解释了好几天
这里是集思录，忽悠不到多少粉丝的...
所以段没有来集思录“传授经验”...
2025-03-25 16:03修改 来自江苏引用
2
RStone
赞同来自: happysam2018、江南1919
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
有财商，还有文笔，更重要的是，根据楼主过往的描述，估计还长的帅，人生赢家
2025-03-25 12:03 来自浙江引用
17
acgt
赞同来自: happysam2018、国富同学、fengcc、kt3020790、初学者3、machine、一生水、学无止境180、iono、人来人往777、枫林随手记、arking83、Penny、风清扬9527、lance77、sdu2011、好奇心135更多 »
@alongside
俺不相信完全靠自己搞到上亿资产（飞升）的人会吃饱了撑的来集思录分享经验...
集思录的a8的元婴老怪还是有的。
大多是 练气，金丹，级别的。
哈哈哈
凡人修仙传 啥时候继续拍下去啊，或者搞个电影？
好像继续拍下去了啊，哇哈哈，看片去啦。
段永平上千亿了，不也在雪球天天发帖。最近用零花钱买了点NVDA然后卖个 covered call ，还发了十几个帖解释了好几天
2025-03-25 11:11 来自山东引用
0
asanoya
赞同来自:
@GLZ0514
聊聊我的思考。首先，做到这个级别，对普通人的生活来说，往上是锦上添花，往下则降级的厉害。那肯定优先考虑的是在控制回撤的条件下尽可能的做收益，那一些单吊或小范围持仓、大比例的杠杆的方式就不适用了，避免暴雷返贫（仅限于还在权益市场赌身家的。有其他优厚条件的，风险承受能力更高，那怎么搞都可以的）。如果持仓的数量大了，就更需要整体性行情的出现，才容易做出收益。按A8-A9 10倍，需要30%的机会9次，...
思路清晰 急而不得
2025-03-25 11:11 来自江苏引用
0
Hph20252095
赞同来自:
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
A7怎么A8？
2025-03-25 09:20 来自移动引用
2
吴香槟
赞同来自: happysam2018
A8到A9难度极大。感觉是比其他级别的资产升级更难。
2025-03-25 08:42 来自中国引用
0
棠溪一剑
赞同来自:
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
讲的真好！点赞
2025-03-25 06:05 来自河南引用
8
夜慕光临Alex
赞同来自: happysam2018、pd34、npc小许、Kluer、好奇心135、阿戒1899、柿柿如意牛旋风、卢训更多 »
一个帖子炸出一堆大佬。想到自己从a4开始靠着打工血汗钱走到今天，真tm难啊。希望十年后的自己也有机会踏上a8到a9的征程。路在脚下，心在远方。自勉~
2025-03-24 23:24 来自广东引用
0
yanghongyong - 万物皆周期
赞同来自:
@IT民工
有个大佬可能快A11了，还整天开拖拉机
逻辑上说不通呀，请问他这个A 11是怎么来的？
2025-03-24 22:27 来自湖南引用
0
yanghongyong - 万物皆周期
赞同来自:
@扫地小僧
不是啊。我是真的想知道，A9怎么到A10。。。。我觉得我这辈子没什么希望到A10了。。。所以才想问。。。。集思录上，A9一抓一大把，A10我相信集思录上肯定也有的，5个？10个？
大佬，当你真的到了A 10档位的话，相信你就不会再纠结你工作的事情了。不过你现在已经到A9了，估计不久的将来大概率会上到A10
2025-03-24 22:24 来自湖南引用
0
我会变好
赞同来自:
@IT民工
有个大佬可能快A11了，还整天开拖拉机
哪个这个抠门
2025-03-24 21:53 来自四川引用
4
IT民工
赞同来自: happysam2018、liangzai2006、ST牧羊、我会变好
@扫地小僧
不是啊。我是真的想知道，A9怎么到A10。。。。我觉得我这辈子没什么希望到A10了。。。所以才想问。。。。集思录上，A9一抓一大把，A10我相信集思录上肯定也有的，5个？10个？
有个大佬可能快A11了，还整天开拖拉机
2025-03-24 21:29 来自福建引用
4
andjsmile - 鹰
赞同来自: happysam2018、dingpenglei、kolanta、pppppp
@alongside
俺不相信完全靠自己搞到上亿资产（飞升）的人会吃饱了撑的来集思录分享经验...
集思录的a8的元婴老怪还是有的。
大多是 练气，金丹，级别的。
哈哈哈
凡人修仙传 啥时候继续拍下去啊，或者搞个电影？
好像继续拍下去了啊，哇哈哈，看片去啦。
你可知道，上海滩一套翠湖都8千万了，可是个超级大楼盘。。我们这上亿也只是普通人。
2025-03-24 13:56 来自上海引用
4
刘刘一
赞同来自: happysam2018、eaglex、好奇心135
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
你的思想比财富更宝贵。
2025-03-24 10:46 来自辽宁引用
3
alongside - 为无为，事无事，味无味
赞同来自: happysam2018、marshalgo
俺不相信完全靠自己搞到上亿资产（飞升）的人会吃饱了撑的来集思录分享经验...
集思录的a8的元婴老怪还是有的。
大多是 练气，金丹，级别的。
哈哈哈
凡人修仙传 啥时候继续拍下去啊，或者搞个电影？
好像继续拍下去了啊，哇哈哈，看片去啦。
2025-03-24 10:26修改 来自江苏引用
3
f2017
赞同来自: happysam2018、jmjswsl、hotsosa
@扫地小僧
搭顺风车问问，如何实现A9到A10的路径？
目前自己的交易模式，A9几乎已经快容不下了。。好难。。。
再顺便问问，A9到A10的意义？
A9了我觉得意义就是赶快去多生几个，其余钱已经没意义了
2025-03-24 08:21 来自上海引用
25
打新交朋友 - 孙子的先胜；老子的不争
赞同来自: happysam2018、shoooliu、那是长安、春暖花开再开、九头、frizll、jackymin001、sdu2011、张霸气、dingo49、newbison、蒙蒙飞絮222、夏冰夏冰夏、iono、wind2012、qianziz、plan30、alongside、heaven32006、yujunlan、司马缸不方、盒饭的饭盒、lixianghui1982、ergouzizzz、realbean更多 »
@liu11liu11
你问谁？你觉得我们有a10?
按我的理解，小僧也不是真想问答案，就是那个瞬间抑制不了人性中想嘚瑟一下的冲动
2025-03-24 07:40 来自江苏引用
8
胖子打新
赞同来自: 迈达斯蓝胖、happysam2018、wwqqtang、KevinLe、好奇心135、阴影下的猫、zhangtiang2008更多 »
每次看完柠檬豪斯兄的文章，内心都会喊出一句：卧槽！太强了，而且年龄应该还小于我。
而且每次看完，说实话，我只能看懂一半左右，领悟到的就更少了。
赚钱真的是需要天赋啊。
2025-03-24 01:39 来自江苏引用
7
剃刀与哑铃
赞同来自: happysam2018、J046711778、九头、dingo49、我会变好、XIAOHULI92、marshalgo更多 »
@扫地小僧
搭顺风车问问，如何实现A9到A10的路径？ 目前自己的交易模式，A9几乎已经快容不下了。。好难。。。再顺便问问，A9到A10的意义？
不是你的朋友问了？
2025-03-23 23:33 来自北京引用
6
liu11liu11
赞同来自: wudeng、happysam2018、Lindsayjia、marshalgo、luckzpz更多 »
@扫地小僧
搭顺风车问问，如何实现A9到A10的路径？
目前自己的交易模式，A9几乎已经快容不下了。。好难。。。
再顺便问问，A9到A10的意义？
你问谁？你觉得我们有a10?
2025-03-23 20:07 来自天津引用
3
IT可乐
赞同来自: happysam2018、阴影下的猫、dxhy165
我欢乐豆都没有你们那么多
2025-03-23 19:24 来自上海引用
12
ivanin1980
赞同来自: happysam2018、eaglex、xiuzhenxw、suijimanbu、森林雪峰、gaokui16816888、coolchan、starcai、铁骨素心、冬晶的雪、好奇心135更多 »
@拉格纳罗斯
那么多的大v，要布道什么十年十倍，我没那福分。我只希望，30年30倍就好，恰好是年化12%。给下一代完成柠檬大佬父母一样的积累。让下一代也能写出如此雄文。
十年十倍目标太容易回撤了，分散投资，不加杠杆，股债平衡，如果以上几个防止回撤的手段都用上，年化12％比较现实。如果10年10倍肯定要采用以上方法之一，你能保证杠杆不爆，投资品种不踩雷，不出现权益黑天鹅？这个是我这么多年花钱买的教训，都是钱买来的
2025-03-23 18:59 来自上海引用
2
cdw654321
赞同来自: happysam2018
@扫地小僧
搭顺风车问问，如何实现A9到A10的路径？
目前自己的交易模式，A9几乎已经快容不下了。。好难。。。
再顺便问问，A9到A10的意义？
路径是夹头
意义是 快感 这是个游戏。
2025-03-23 18:05 来自浙江引用
10
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: happysam2018、zqbkzz、kolanta、marshalgo、hanbing0356、neverfailor、Tom20221130、dxhy165、理想已实现更多 »
@扫地小僧
搭顺风车问问，如何实现A9到A10的路径？
目前自己的交易模式，A9几乎已经快容不下了。。好难。。。
再顺便问问，A9到A10的意义？
前面那个答案我不知道，后面那个答案我乱猜测一下，老天爷将如此巨额金钱寄存于你手中，你当尽自己所能替天行道，把他用在最需要他的地方！
2025-03-23 17:51 来自新疆引用
3
必得大底
赞同来自: happysam2018、tidda、傻呆书生
其实路径并没有那么重要。
能到a9的人早晚都会到，只是时间问题。
2025-03-23 15:19 来自上海引用
4
卢训
赞同来自: happysam2018、wwqqtang、J059112263、好奇心135
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
写得真好，有血有肉的细节解剖，尤其是集友母亲的眼界，颇为独到。
2025-03-23 12:08 来自贵州引用
4
在路上1225
赞同来自: fstop12、happysam2018、wwqqtang、gaokui16816888
@哆啦大和
这样吧，很多人都是平台而已，你让我和王思聪，张康阳换个老爸，我至少不比他们差。王思聪，张康阳初始阶段如果是我的平台，他们可能真心远远不如我，至少我奋斗了18年，无论是学历还是金钱，周围的同龄人，起步阶段一样的话，基本上没有比我更优秀的，我基本纯粹靠自己努力。所以说，不要迷信任何人，都是投胎的平台而已。
投胎才是核心竞争力
2025-03-23 10:14 来自浙江引用
0
link2000
赞同来自:
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。
许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
感谢分享如此感悟，不仅关乎自身，更直指财富传承。
2025-03-23 09:32 来自上海引用
0
doctor123456
赞同来自:
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
还是有人带你 家里也有钱
2025-03-23 09:02 来自上海引用
0
炯菲特
赞同来自:
主要还是lucky
2025-03-23 08:59 来自上海引用
6
拉格纳罗斯
赞同来自: happysam2018、dingpenglei、addy5280、乐鱼之乐、好奇心135、朱顶红更多 »
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
那么多的大v，要布道什么十年十倍，我没那福分。我只希望，30年30倍就好，恰好是年化12%。
给下一代完成柠檬大佬父母一样的积累。让下一代也能写出如此雄文。
2025-03-23 06:30 来自辽宁引用
0
哆啦大和
赞同来自:
@ST牧羊
我也奋斗了十八年，我那年6124之后开户的，后面的故事就不需要给你说了，咱们都是故事的主角，从未抱怨本钱少，有杠杆啊，杠杆是交易技术的核心，杠杆是改变命运的关键！
谢谢，我几乎没有杠杠，稳健投资最大的弱点，就是，收益不高
2025-03-23 00:36 来自重庆引用
0
力鲨
赞同来自:
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
谢谢分享，本帖真值
2025-03-22 23:12 来自福建引用
5
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: happysam2018、dingpenglei、franckC、眼睛、好奇心135更多 »
@哆啦大和
这样吧，很多人都是平台而已，你让我和王思聪，张康阳换个老爸，我至少不比他们差。
王思聪，张康阳初始阶段如果是我的平台，他们可能真心远远不如我，至少我奋斗了18年，无论是学历还是金钱，周围的同龄人，起步阶段一样的话，基本上没有比我更优秀的，我基本纯粹靠自己努力。
所以说，不要迷信任何人，都是投胎的平台而已。
我也奋斗了十八年，我那年6124之后开户的，后面的故事就不需要给你说了，咱们都是故事的主角，从未抱怨本钱少，有杠杆啊，杠杆是交易技术的核心，杠杆是改变命运的关键！
2025-03-22 22:41 来自新疆引用
21
哆啦大和
赞同来自: happysam2018、阿戒1899、alongside、欢乐马小跳、财迷牛、kolanta、sdu2011、柿柿如意牛旋风、dingo49、剑水、困了学索隆、zhuzi51、YmoKing、dingpenglei、sasing、realbean、basementkids、nannite、听风绝弦、好奇心135、simpisbest更多 »
18年的投资经历，完全靠自己完成了资本的原始积累，然后一步一步做大
这样说嘛，集思录能有几个能够从A5起步到我现在的，难于登天吧
2025-03-22 22:00 来自重庆引用
13
哆啦大和
赞同来自: happysam2018、alongside、王的天下、剑水、neverfailor、大牌886、YmoKing、nhj2021、franckC、tangyin88、意外的角落、marshalgo、听风绝弦更多 »
@ST牧羊
命如纸薄，应有不屈之心，修行到了最后比的是信仰，不是金钱！
这样吧，很多人都是平台而已，你让我和王思聪，张康阳换个老爸，我至少不比他们差。
王思聪，张康阳初始阶段如果是我的平台，他们可能真心远远不如我，至少我奋斗了18年，无论是学历还是金钱，周围的同龄人，起步阶段一样的话，基本上没有比我更优秀的，我基本纯粹靠自己努力。
所以说，不要迷信任何人，都是投胎的平台而已。
2025-03-22 21:58 来自重庆引用
0
我怕黑天鹅 - 喜欢投资的屌丝
赞同来自:
@哆啦大和
18年前，也就是2007年的4月9日，我妈借了我15000本金，成为我进入股市的开始。柠檬的妈妈直接给了他八位数的初始本金，A5和A8的初始本金，注定了是不同的人生，不同的感悟，不同的认知。
呵呵，以你的能力，以后可以甩给你儿女一个八位数，不就好了。
2025-03-22 21:42 来自湖北引用
2
eye00
赞同来自: happysam2018、好奇心135
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
大佬年纪轻轻，对低风险投资认知这么深刻！太优秀了！年轻有为！后生可畏！
2025-03-22 21:23 来自山东引用
11
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: happysam2018、alongside、jjj5188、YmoKing、dingpenglei、wind2012、家和妈妈、彩虹鸽、好奇心135、古都独行、Qwe38rasdf更多 »
@哆啦大和
18年前，也就是2007年的4月9日，我妈借了我15000本金，成为我进入股市的开始。
柠檬的妈妈直接给了他八位数的初始本金，A5和A8的初始本金，注定了是不同的人生，不同的感悟，不同的认知。
命如纸薄，应有不屈之心，修行到了最后比的是信仰，不是金钱！
2025-03-22 21:05 来自新疆引用
3
Zackhu
赞同来自: happysam2018、彩虹鸽、好奇心135
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
lemon出品，必属精品！
2025-03-22 20:49 来自浙江引用
16
哆啦大和
赞同来自: happysam2018、alongside、YmoKing、franckC、意外的角落、平安夜、jackymin001、rank、walkerdu、幽灵资本、tongzhangji、听风绝弦、彩虹鸽、四时自由、好奇心135、古都独行更多 »
@深海1949
@Lemonhouse年纪轻轻，对财富人生有如此认知，令人羡慕！
18年前，也就是2007年的4月9日，我妈借了我15000本金，成为我进入股市的开始。
柠檬的妈妈直接给了他八位数的初始本金，A5和A8的初始本金，注定了是不同的人生，不同的感悟，不同的认知。
2025-03-22 20:38 来自重庆引用
2
gongxiaochun
赞同来自: happysam2018、彩虹鸽
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
加法和乘法的解释，真的太牛逼了！
2025-03-22 20:33 来自北京引用
2
alex9900
赞同来自: happysam2018、彩虹鸽
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
写的太好了
2025-03-22 18:58 来自广东引用
6
hotsosa
赞同来自: happysam2018、momo丁、匹诺曹Y、火龙果与榴莲、子非鱼b、好奇心135更多 »
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
金融是关于时间的理论，以财富和波动作为刻度。
2025-03-22 18:56 来自移动引用
2
深海1949
赞同来自: happysam2018、好奇心135
@Lemonhouse年纪轻轻，对财富人生有如此认知，令人羡慕！
2025-03-22 18:42 来自移动引用
10
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: 投资旗舰、happysam2018、huangke、那是长安、唐唐脱口秀、franckC、风清扬9527、彩虹鸽、好奇心135、山就在脚下更多 »
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。
许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
善哉，施主大才，三代人的努力和认知集于一生，36岁看穿金钱，看透人生，看破时间！如此天才，世间罕见！集思录中当属第一！
2025-03-22 16:47修改 来自新疆引用
2
liamcai
赞同来自: happysam2018、好奇心135
@Lemonhouse
在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算...
写的太好了
2025-03-22 16:05 来自上海引用
0
养海龟的人
赞同来自:
@天天吹泡泡
a8-a9咱不懂，我a5-a7是通过打新套利 分散投资 周期抄底实现的。周期低谷买入绝无破产清算可能的公司（央国企/低负债），景气周期翻倍甚至三五倍都很正常，具体操作就是低估非周期蓝筹（高股息/pe估值低百分位）作为打新门票 周期股分散配置，这么做牛市能大赚熊市也未必会亏（打新收益/结构性行情/周期与大盘未必同步），如果有现金流复投的话熊市能比牛市攒更多股，等到下一轮周期收益更高，最大难点是周期...
现在打新还有收益么
2025-03-22 16:00 来自江苏引用
562
Lemonhouse
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在财富攀登的道路上，回过头看，我感觉先要完成从加法到乘法得转换。靠加法是可以上千万的，但是靠加法上亿有难度。
许多人比较典型的财富路径是这样：几套房子，家人在银行里的存款，自己股市里的钱，做生意的人就算厂子投资的总金额，加一起上千万了。但是实际上这还是加法思维。怎么说呢，举个例子，我每年年初看过许多的年度投资报告，写的都特别好，但就觉得中间忽略了两个很重要的点，导致真实收益率需要重估。1.每年计算投资回报时的投资资产，在家庭总资产中究竟占比多少？2.家庭开支是否会侵蚀年度投资收益？不解决这两个问题，是无法用乘法滚动家庭总资产的。
许多年前，我妈开中老年服装店，我爸拆迁了个厂子，我们踩中了门面房的风口。靠每年挣钱的累积和收的房租，再叠加门面和房子的涨幅，以及偶发性的大额收入，加起来是可以上千万甚至两千万的。加之这个阶段需要累积本金以增加财产性收入，所以哪怕千万以后，我爸妈都继续住在楼梯间，开一个三万块的日产，在家里做饭不出去吃。
但是在这个过程中我妈发现了，做加法是有天花板的，一堆门面房子加到一起，谁知道多年以后会怎么样呢？唯有资产再配置，红利再投资，才能让家庭财富的飞轮转起来。所以她那时候最愁的一件事就变成了，以后挣了钱要怎么办？为了解决这个问题，她把我从深圳叫回来，送到L叔那里进修债券投资知识。也是从这个时候开始，我们正式开始了专业化的投资和盈利再投资之路。
现在回过头来看，我妈这个判断在数学上来说是正确的。从1千万到3千万，如果用的是加法，在以亿为目标的道路上仅仅走完了2/9，还有7个一千万需要累积。但是用乘法的话，这条路已经完成了几近一半。因为1000万到3000万是翻3倍，3000万到9000万也是翻3倍，难度增加不多，路径是可复制的，这可能就是复利的魅力吧。
所以，这个阶段我们主攻的方向是两点。第一是优化资产组合，把低效资产向高效资产迁移，把高估资产向低估资产转换。卖房炒股在情感上是无法接受的，但是先挣钱再买房延迟消费大家却可以理解。所以我们压制住买别墅买豪车的冲动，坚决不再购置门面，系统学习集思录低风险投资知识。随着时间的推移，低风险的投资回报就越来越成为家庭收入的中流砥柱。
第二是强化管理能力。做乘法的核心其实就是管理，不管是老板，金领，还是职业投资人，本质上都是对人或者对钱的管理。如果没有管理能力做背书，盲目去扩大规模，风险是巨大的。但是没有规模就没有复利，也就做不了乘法。所以越往下面走，就愈发强调人的专业性了。我妈的口头禅就变成了，财富一定要掌握在有能力的人手中。很多年前流行一句话，21世纪是人才的世纪，还真是这样。要不然就把自己变成人才，要不然就能够招纳人才，这样才能在规模化的扩张中一直复利滚下去，而不是在滚雪球的过程中被腰斩甚至被归零。多说一句，我感觉我们职业投资者是少有的可以靠个人就实现上亿的职业，其他职业且不论企业家还是金领，哪怕是攫取了流量红利的网红（流量本质上也是一种乘法），要做到资产上亿都是要靠团队靠公司了。
当可投资资产达到3000万往上走，自己是能够慢慢感受到已经基本实现财富自由了。哪怕把钱放在银行，甚至存活期坐吃山空，这辈子都很难花完。我们个人投资者和企业家不一样，我们是不用对别人的就业负责的，我们只需要顾着自己的家庭，这没有压力，但也有利有弊。所以到了这个阶段，我追求的就是稳中求进了，核心是先保住现有生活，再追求财富上的增值。所以我就不再单边下注了，而是两手准备。如果实现了预期目标，我就会获得较好的回报。如果没有实现预期目标，我也要追求结果可接受。因为瞻前的同时必须顾后，势必会影响资金的使用效率，导致我们的目标年化就要有所降低。但后来我慢慢发现，如果在投资上花的心思越多，就像从一年级读到了四年级以后，其实慢慢获取超额的能力也会变强，尤其是在散户还拥有规模优势的前提下。所以，当你可以接受少挣钱的时候，其实钱也没少挣，可能比想象中还好一点。
另一方面，到了这个阶段，家庭开销对家庭财富积累的抑制作用将逐步降低，同时随着收入的提升，消费观也会不可避免的被同步重塑。3000万只要能实现年化7个点，一年就是两百多万。而有了3000万可投资资产的人，大概率是不存在还有房贷啥的。所以，喜欢的东西，在不上当的情况下是可以买的，也可以为爱好买单，慢慢的改善生活，优化房车，出去旅行，在实践的过程中也会总结出一套适合自己的消费观出来，从不擅长消费到精通消费。
接下来一个比较重要的节点是5000万阶段，我感觉它更像是一个心理节点。从此以后，上亿已经不再是一个虚无缥缈的概念了，是可预期可量化可追溯的。我记得，当年达到的时候，我和我妈头一次提出半亿身家概念，我妈是少有的没有批评我让我低调，而是和我一起散步聊天高兴了好一阵子。
所以，越往后走，我就有了一个新的感悟，“亏就是挣”，我从不可以接受亏钱到可以接受亏钱，怎么理解呢？后来我看各种财富报告，都是从亿级开始看齐，用帕累托模型去算处于我这个财富阶段的人群数量。这个时候我就发现，所谓的千分之一甚至万分之几的概率，那就是我们中学集合升旗，一操场乌泱泱的两三千个人，这么多人里面都就出一个的概率了。所以既然知道了自己的位置，我要的点就是卡住当下排名。我可以接受跌，但是要让下跌变得有价值。我跌，大家也跌，我的排名没有变化。大家涨，我也要涨，不然我岂不是就落后了。所以我慢慢就皈依了宽基的门派中去了，从追求绝对回报，变成了相对回报。我不再搞具体的，小众的某些品种，因为这和社会平均值的偏离是比较大的，我也不在主观判断去拥抱高评级资产，而是按照统计学大小均摊。其实也对，我的投资基准与社会均值同步，我的权益类有超额，我又用超额买了购权平滑了收益率曲线，最后我还不满仓，固收都能多薅点羊毛。那就是大家涨，我跟得上，大家亏，我亏的少，可不就是亏就是挣嘛！所以过往的几年，经济持续下行，反而是咱们低风险投资者社会排名和家庭地位提升的几年。
多数人追求的投资结果是什么呢？想多挣，不想亏。我现在呢，我可以少挣，我也可以亏。所以我要的天生就让我成为了一个少数派，可咱们这个市场啊，偏偏就是对少数派有优势。而且到了这个阶段，就必须要搞懂，我挣的钱是从哪里挣到的，对方为什么愿意给我挣这个钱，思考懂了这个才能降低风险。而我对自己的考核，也已经切换为超额模式了。我觉得，相对市场均值超额取得的利润，才是推动家庭财富继续向前的真正燃料。
同时我也发现上了规模以后，挣钱有点像个数字游戏。账户金额的波动会变得很大，经常性的日波动过百万，或者波动大的时候短时间就有上千万的涨跌。年回报也变得很巨大，效益好的年头能够千万级的年回报。而消费却基本固定在之前的模式之中，钱多一点少一点，也不会从根本上改变生活。当金钱的增长和幸福的增长不再线性挂钩，当时间可以带来财富，但我却变得更加珍视时间本身。
做个计算题吧，刨掉开支，年化回报达到7%，30岁的时候拥有5000万，和40岁的时候拥有一个亿，是可以等效转换的。那么，究竟是前者更幸福，还是后者更幸福呢？
这个问题我想了很久，之前我一直认为，是30岁的时候拥有5000万更幸福，因为5000万和一个亿，给生活带来的感受并没有天壤之别，而年轻十年，生活却多了很多种可能。时间过了几年之后，我也看到了很多优秀的投资者，我明白过来了，真正的答案应该是，这两种情况都极其幸福。为什么呢？因为如果只有7%的收益率，在这样的年纪是不可能拥有这样的财富的。
和尚老师转载了一个故事，池塘的青萍一天增殖一倍，60天覆盖满整个池塘。那么，要覆盖四分之一个池塘，需要的是青萍生长的第58天。我之所以可以攀爬九位数的山峰，本质上是我爸妈用30年的坚守换来的。
这就是低风险投资的悖论。长远看，低风险投资可以带来巨大的财富。但长远看，我们都会衰老。如果要在一代人中完成财富积累，在漫长的前期，我们要如何调整自己，去穿越那片孤独压抑又充满希望的土壤？
是克制么？不是的，是热爱。12年前，我妈把我叫回县城开始投资，我那时候总是惊讶于我妈的预见性。我问我妈，你是怎么知道这些的？她和我说，那是因为她做了，想了，边做边想，慢慢就懂得了这些道理。
从24岁到36岁，我也从家庭财富的见证者，变成了家庭财富的掌舵人。从加法，到乘法，从套利投资，到套利消费，从经营财富，到经营生活。慢就是快，亏就是挣。从追求结果，到享受过程。我骄傲过，也失落过。犹豫过，也欣喜过。岁月赠予我财富，岁月也让我不复年轻。最后沉淀下来又熠熠生辉的，是波动煎熬中学会的等待，是平衡资产时领悟的舍得，在无人问津处的坚守，和逆潮流而动的勇气，这或许就是低风险投资之路最深邃的浪漫。
《三体》中改编过帕斯卡的一段话，我把原文附出来，“给时光以生命，而不是给生命以时光”。我们不是要从生命中去赢得时光，而是要在时光中去赢得生命。
2025-03-22 15:26 来自湖南引用
0
marshalgo
赞同来自:
@tiancaibob
兄弟，有点没看懂，你目前是千万级，马上要到亿级了？但看你的描述过程好像目前是百万级。
如果后期没有追加，按描述的应该是几百万
2025-03-22 14:35 来自河南引用
3
tiancaibob
赞同来自: happysam2018、必得大底、我会变好
@自由的飞
17年考上本地小城市银行开始工作18年开始接触股票，一直小打小闹，基本没赚没亏19到20年接触集思录，把集思录历史上有价值的帖子认真研究了一遍，并总结了他们赚钱路径，期间也是各种尝试，认知慢慢提高，不过资金投入少算小赚21年说服父母动用200个资金和姐姐的30个资金（基本上是家庭里的所有流动资金了），主要做可转债，收益率2.4倍22年主要还是转债，收益21%23年开始尝试其他路径，收益9%24年...
兄弟，有点没看懂，你目前是千万级，马上要到亿级了？但看你的描述过程好像目前是百万级。
2025-03-22 13:01 来自移动引用
13
yup77
赞同来自: happysam2018、花椒大料、女爰、franckC、link2000、ninja8863、janescheng、gaokui16816888、kolanta、古都独行、我心淡然、topdeck、drzb更多 »
2000年前，残疾人司马迁写道：无财作力，少有斗智，既饶争时，我琢磨分别对应A6，A7，A8
古代则是千钱以下，万钱，十万钱，可见古今差异还是很大的
2025-03-21 22:29 来自上海引用
0
力鲨
赞同来自:
@说不出的YD
以后看到这种贴先减仓为敬。
哈哈，出现没啥，关键是太火了
2025-03-21 22:27 来自福建引用
0
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自:
@sanbeishui
前几年看到过一个账户，华泰过去10年年化收益23%，打败了99.91%乐友，也就是千分之一的人投资收益率能持平甚至打败巴菲特，中国有股民2亿，这个千分之一有20万人，想想巴菲特军团有多恐怖。
十万分之一，你算错了，新疆是没有A9以上的高手的，也许ST姐夫达到了吧
2025-03-21 15:19 来自新疆引用
9
gfzhywa
赞同来自: iBer、happysam2018、阿戒1899、唐唐脱口秀、space2008、newbison、邵比格、电动自行车、pppppp更多 »
其实也不用怎么研究，基本上A9的，大部分都是靠减持达到的。我的一个朋友的亲属，上市公司的一个中层，光是近十几年的各期的员工股卖出就已经进账大几百w了，别提那些高层了
2025-03-21 14:22 来自广东引用
1
lixianghui1982
赞同来自: 风清扬9527
@说不出的YD
以后看到这种贴先减仓为敬。
毛师没提示，减仓容易错过暴涨。
2025-03-21 12:21 来自河北引用
0
月之牙
赞同来自:
@EasonSun
根据行业通用定义和权威资料（截至2025年最新信息），A8的具体含义及解释如下：一、符号解析符号含义示例金额范围AAsset（资产） 的缩写，特指个人/机构持有的可量化财产8金额位数，代表以元为单位的数字位数（不包含小数点后的金额）10,000,000 ~ 99,999,999元二、常见等级体系A6 → 十万级 (100,000元) 【基础财富门槛】A7 → 百万级 (1,000,000元...
人民币还是美元？
2025-03-21 12:13 来自新疆引用
2
说不出的YD
赞同来自: happysam2018、王旁青头兼五一
以后看到这种贴先减仓为敬。
2025-03-21 11:42 来自天津引用
2
pppppp - +---++--+-+++++++++++
赞同来自: happysam2018、风清扬9527
@sanbeishui
前几年看到过一个账户，华泰过去10年年化收益23%，打败了99.91%乐友，也就是千分之一的人投资收益率能持平甚至打败巴菲特，中国有股民2亿，这个千分之一有20万人，想想巴菲特军团有多恐怖。
中国股民这么强了；
2025-03-21 11:18 来自上海引用
2
lixianghui1982
赞同来自: happysam2018、古都独行
@ST牧羊
这是百万分之1，兄弟
又算了一下，感觉是千分之一啊。莫非我的老年痴呆又严重了
2025-03-21 08:34 来自河北引用
0
f2017
赞同来自:
@sanbeishui
前几年看到过一个账户，华泰过去10年年化收益23%，打败了99.91%乐友，也就是千分之一的人投资收益率能持平甚至打败巴菲特，中国有股民2亿，这个千分之一有20万人，想想巴菲特军团有多恐怖。
10年23%是远远落后巴菲特的，因为拉长时间比如再加10年，那么估计就只有万分之一了，再拉长10年就只有亿分之一了。
或者你和早期30年资金量相对比较小的时候比，年化就差不少了。
2025-03-21 08:30 来自上海引用
0
lixianghui1982
赞同来自:
@sanbeishui
前几年看到过一个账户，华泰过去10年年化收益23%，打败了99.91%乐友，也就是千分之一的人投资收益率能持平甚至打败巴菲特，中国有股民2亿，这个千分之一有20万人，想想巴菲特军团有多恐怖。
乐友水平相对较低，如果换到广发，估计也就打败99.52%。
2025-03-20 22:09 来自河北引用
0
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自:
@sanbeishui
前几年看到过一个账户，华泰过去10年年化收益23%，打败了99.91%乐友，也就是千分之一的人投资收益率能持平甚至打败巴菲特，中国有股民2亿，这个千分之一有20万人，想想巴菲特军团有多恐怖。
这是百万分之1，兄弟
2025-03-20 22:06 来自新疆引用
2
sanbeishui
赞同来自: happysam2018、newbison
@黎明已过
真正靠二级市场赚到一亿的人应该很少很少（亿元级别人群中低于10%）。需要1995年10万起步保持26%的收益率30年，或者2005年100万起步年化26%持续20年。1995年的10万和2005年的100万都是属于比较富裕的人。26%是巴菲特的年化收益率，中国不可能有1万人。
前几年看到过一个账户，华泰过去10年年化收益23%，打败了99.91%乐友，也就是千分之一的人投资收益率能持平甚至打败巴菲特，中国有股民2亿，这个千分之一有20万人，想想巴菲特军团有多恐怖。
2025-03-20 21:26 来自上海引用
2
bigboiii
赞同来自: happysam2018、alongside
@hotsosa
职业炒股上a9,应该不多。否则你也不会这么问了。
大家感兴趣的应该是职业炒股到A9的有多少，而不是A9的有多少是职业炒股
2025-03-20 19:55 来自浙江引用
0
hotsosa
赞同来自:
@bigboiii
A9以上，职业股民是10%，怎么理解？这也只是类似资产负债表一样的快照，而不是现金流量表这样的过程。 比如A做小生意赚到A9了，现在50多岁，生意歇下来了，专职炒股，符不符合这个统计？ 大家更想知道的是有多少A9以上资产的人是主要靠炒股成就A9的，而不是A9以上资产中有多少职业股民
职业炒股上a9,应该不多。否则你也不会这么问了。
2025-03-20 17:05 来自移动引用
0
twam - 捂股丰登
赞同来自:
@大牌886
其实真的大的叙事波动，大哥们往往会集体行动，KOL（意见领袖）跟踪策略还是很复杂的，像最近BSC的MUBARAK这种波动，这种信息传播下，不同大哥们是轮流不同逐步操作的。
对我来说不是研究某个大哥，而是更多的理解初期信息传播过程中，信息是如何在小范围的KOL集群里传播，最后从而传播到更大的圈层。
就像最初期的TRUMP的买入过程，不同KOL买入时间也是不同的。
过去我的重心是研究信息本身如何扩散，...
你需要有极强的信息获取和筛选能力
2025-03-20 15:35 来自福建引用
3
bigboiii
赞同来自: happysam2018、邵比格、好奇心135
@sanbeishui
记得好像是胡润的报告，说A9以上资产的人，主要职业，10%是职业股民，10%是职业炒房客，70%是自己当老板的，好像还有10%是高级打工皇帝。可能最近又更新过，上面数据不一定准了。
A9以上，职业股民是10%，怎么理解？这也只是类似资产负债表一样的快照，而不是现金流量表这样的过程。 比如A做小生意赚到A9了，现在50多岁，生意歇下来了，专职炒股，符不符合这个统计？
大家更想知道的是有多少A9以上资产的人是主要靠炒股成就A9的，而不是A9以上资产中有多少职业股民
2025-03-20 15:33修改 来自浙江引用
2
gwxkai
赞同来自: happysam2018、羊羊羊啊
大家能别装腔造新词了吗？真没必要。。。
2025-03-20 15:12 来自北京引用
4
EasonSun
赞同来自: happysam2018、muyeshancai、Kluer、好奇心135
@yjh2175
不是很懂，敢问大佬，A8，是指八位数的意思吗？A是代表什么意思？
根据行业通用定义和权威资料（截至2025年最新信息），A8的具体含义及解释如下：
一、符号解析
符号
含义
示例金额范围
A
Asset（资产） 的缩写，特指个人/机构持有的可量化财产
8
金额位数，代表以元为单位的数字位数（不包含小数点后的金额）
10,000,000 ~ 99,999,999元
二、常见等级体系
A6 → 十万级 (100,000元) 【基础财富门槛】
A7 → 百万级 (1,000,000元) 【中产典型标志】
A8 → 千万级 (10,000,000元) 【高净值人群】
A9 → 亿级 (100,000,000元) 【超高净值标准
2025-03-20 14:08 来自上海引用
2
酱油面
赞同来自: happysam2018、看看1028
@吉地
A9.2左右（含7000W左右的低息贷款）9.2亿-7000w=5000w 怎么做到5000w借到7000w的低息借贷？抵押了别的资产？
9.2 = 2个亿
2025-03-20 13:55 来自云南引用
2
大牌886 - 愚蠢的人类
赞同来自: happysam2018、J204705369
@大牌886
其实真的大的叙事波动，大哥们往往会集体行动，KOL（意见领袖）跟踪策略还是很复杂的，像最近BSC的MUBARAK这种波动，这种信息传播下，不同大哥们是轮流不同逐步操作的。
对我来说不是研究某个大哥，而是更多的理解初期信息传播过程中，信息是如何在小范围的KOL集群里传播，最后从而传播到更大的圈层。
就像最初期的TRUMP的买入过程，不同KOL买入时间也是不同的。
过去我的重心是研究信息本身如何扩散，...
我应该称之为：小规模市场里的KOL的信息传播与市场波动。大市场绝对没有这个功能，因为无法跟踪巨鲸的意图，巨鲸有对冲，有做市商，还有政府参与，有超大量的散户。根本没法用这种套路。巨大的市场，只能采用巨量人群集体行动跟踪（比如集体情绪），巨鲸意图揣测，或者是技术分析。。。。
从那年GME开始，我应该就该注意到这套打法最适合参与者都非常清晰的品种，浪费了我很多思考时间。
2025-03-20 13:48 来自上海引用
6
大牌886 - 愚蠢的人类
赞同来自: happysam2018、丁一白、J204705369、凡先生、好奇心135、不虚不实更多 »
@twam
关键是大哥真真假假、假假真真，而且是否有及时买卖你也不知道啊
其实真的大的叙事波动，大哥们往往会集体行动，KOL（意见领袖）跟踪策略还是很复杂的，像最近BSC的MUBARAK这种波动，这种信息传播下，不同大哥们是轮流不同逐步操作的。
对我来说不是研究某个大哥，而是更多的理解初期信息传播过程中，信息是如何在小范围的KOL集群里传播，最后从而传播到更大的圈层。
就像最初期的TRUMP的买入过程，不同KOL买入时间也是不同的。
过去我的重心是研究信息本身如何扩散，现在开始我要把重心放在KOL集群的监测和变化，从而理解叙事的早期传播过程。
所以去年读过南大一个传播学教授的论文指出要预测后续波动，就必须能够监测早期圈层的信息扩散，和最初期KOL对于信息的解读，这是最关键的重点。
从去年开始跟踪雪球几个HK小盘大哥们开始，我就开始逐步开始尝试理解这种。
因为无论HK小盘还是币圈，因为参与人数非常少，非常适合用来研究初期信息扩散的过程。
一旦到了大市场，这种模式就淹没在极大量人群下了
2025-03-20 13:41 来自上海引用
2
做时间朋友
赞同来自: happysam2018、chui810
哪里可以密名的，不然高低说几句
2025-03-20 13:35 来自浙江引用
0
heaven32006
赞同来自:
@yjh2175
不是很懂，敢问大佬，A8，是指八位数的意思吗？A是代表什么意思？
asset
2025-03-20 13:32 来自上海引用
0
yingsaiyu
赞同来自:
@范少伯
14年下半年我投入1300W本金做T0/打新/分级/股指/期权套利（含1000W借款），截至2016年初可投资金融总资产A8.3不到一点（含1000W借款）。2016年开始全职投资，尝试过主板/科创网下（底仓纯对冲/高票/指增）/港股打新/三板打新，房产套利，T0，CB/EB一级半套利/贴水套利/网下/多头择时，期货/期权/ETF波动率套利/多头择时，大宗/定增套利，期货月差/产业链/内外联动套...
你是如何借到这么多钱？能讲讲吗？有借鉴意义吗？
2025-03-20 13:04 来自浙江引用
2
吉地
赞同来自: happysam2018
A9.2左右（含7000W左右的低息贷款）9.2亿-7000w=5000w 怎么做到5000w借到7000w的低息借贷？抵押了别的资产？
不好意思，是我理解错了，2亿-7000万=1亿3000万.集思录里怎么删除或者修改自己的回复？我找半天找不到。
2025-03-20 12:58修改 来自上海引用
2
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: happysam2018、湘漓浪云
@tangyin88
A10是不是只有8千? 也按10倍减少
A10是10亿，其他的我不懂你说什么
2025-03-20 12:38 来自新疆引用
0
tangyin88
赞同来自:
@ST牧羊
不难，看你追求什么
A10是不是只有8千? 也按10倍减少
2025-03-20 12:32 来自上海引用
0
yjh2175
赞同来自:
不是很懂，敢问大佬，A8，是指八位数的意思吗？A是代表什么意思？
2025-03-20 12:27 来自浙江引用
0
antiwalker
赞同来自:
@ST牧羊
不难，看你追求什么
对于我这种知识面窄，不知道怎么思考问题的人难的很。
2025-03-20 11:05 来自上海引用
1
ST牧羊 - 此人不学无术，贪财好色，与人常做无谓口舌之争，遇事夸夸其谈百无一用，判其投胎南瞻部洲，当一股民，昼则殚精竭虑交易，夜则膏油继晷复盘，终年盘桓于三千点，账户缩水日甚一日，活活亏煞他罢了
赞同来自: 那是长安
@蓝天还是白云
全国A8有108万户，A9有8万户，难度可想而知。
不难，看你追求什么
2025-03-20 10:48 来自新疆引用
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Applied statistics and probability for engineers solution montgomery && runger
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This document is the copyright page and preface for the book "Applied Statistics and Probability for Engineers" by Douglas C. Montgomery and George C. Runger. The copyright is held by John Wiley & Sons, Inc. in 2003. This book was edited, designed, and produced by various teams at John Wiley & Sons and printed by Donnelley/Willard. The preface states that the purpose of the included Student Solutions Manual is to provide additional help for students in understanding the problem-solving processes presented in the main text.
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Image 2: Applied Statistics
and Probability
for Engineers
Third Edition
Douglas C. Montgomery
Arizona State University
George C. Runger
Arizona State University
John Wiley & Sons, Inc.
Image 3: ACQUISITIONS EDITOR Wayne Anderson
ASSISTANT EDITOR Jenny Welter
MARKETING MANAGER Katherine Hepburn
SENIOR PRODUCTION EDITOR Norine M. Pigliucci
DESIGN DIRECTOR Maddy Lesure
ILLUSTRATION EDITOR Gene Aiello
PRODUCTION MANAGEMENT SERVICES TechBooks
This book was set in Times Roman by TechBooks and printed and bound by Donnelley/Willard.
The cover was printed by Phoenix Color Corp.
This book is printed on acid-free paper. ϱ
Copyright 2003 © John Wiley & Sons, Inc. All rights reserved.
No part of this publication may be reproduced, stored in a retrieval system or transmitted
in any form or by any means, electronic, mechanical, photocopying, recording, scanning
or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States
Copyright Act, without either the prior written permission of the Publisher, or
authorization through payment of the appropriate per-copy fee to the Copyright
Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400,
fax (978) 750-4470. Requests to the Publisher for permission should be addressed to the
Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York, NY
10158-0012, (212) 850-6011, fax (212) 850-6008, E-Mail: PERMREQ@WILEY.COM.
To order books please call 1(800)-225-5945.
Library of Congress Cataloging-in-Publication Data
Montgomery, Douglas C.
Applied statistics and probability for engineers / Douglas C. Montgomery, George C.
Runger.—3rd ed.
p. cm.
Includes bibliographical references and index.
ISBN 0-471-20454-4 (acid-free paper)
1. Statistics. 2. Probabilities. I. Runger, George C. II. Title.
QA276.12.M645 2002
519.5—dc21
2002016765
Printed in the United States of America.
10 9 8 7 6 5 4 3 2 1
Image 4: SO fm.qxd 8/6/02 4:31 PM Page v
Preface
The purpose of this Student Solutions Manual is to provide you with additional help in under-
standing the problem-solving processes presented in Applied Statistics and Probability for
Engineers. The Applied Statistics text includes a section entitled “Answers to Selected
Exercises,” which contains the final answers to most odd-numbered exercises in the book.
Within the text, problems with an answer available are indicated by the exercise number
enclosed in a box.
This Student Solutions Manual provides complete worked-out solutions to a subset of the
problems included in the “Answers to Selected Exercises.” If you are having difficulty reach-
ing the final answer provided in the text, the complete solution will help you determine the
correct way to solve the problem.
Those problems with a complete solution available are indicated in the “Answers to
Selected Exercises,” again by a box around the exercise number. The complete solutions to
this subset of problems may also be accessed by going directly to this Student Solutions
Manual.
Image 5: Chapter 2 Selected Problem Solutions
Section 2-2
2-43. 3 digits between 0 and 9, so the probability of any three numbers is 1/(101010);
3 letters A to Z, so the probability of any three numbers is 1/(262626); The probability your license plate
-8
is chosen is then (1/103)(1/263) = 5.7 x 10
Section 2-3
2-49. a) P(A') = 1- P(A) = 0.7
b) P ( A ∪ B ) = P(A) + P(B) - P( A ∩ B ) = 0.3+0.2 - 0.1 = 0.4
c) P( A ′ ∩ B ) + P( A ∩ B ) = P(B). Therefore, P( A ′ ∩ B ) = 0.2 - 0.1 = 0.1
d) P(A) = P( A ∩ B ) + P( A ∩ B ′ ). Therefore, P( A ∩ B ′ ) = 0.3 - 0.1 = 0.2
e) P(( A ∪ B )') = 1 - P( A ∪ B ) = 1 - 0.4 = 0.6
f) P( A ′ ∪ B ) = P(A') + P(B) - P( A ′ ∩ B ) = 0.7 + 0.2 - 0.1 = 0.8
Section 2-4
2-61. Need data from example
a) P(A) = 0.05 + 0.10 = 0.15
P( A ∩ B) 0.04 + 0.07
b) P(A|B) = = = 0.153
P( B ) 0.72
c) P(B) = 0.72
P( A ∩ B) 0.04 + 0.07
d) P(B|A) = = = 0.733
P( B ) 0.15
e) P(A ∩ B) = 0.04 +0.07 = 0.11
f) P(A ∪ B) = 0.15 + 0.72 – 0.11 = 0.76
2-67. a) P(gas leak) = (55 + 32)/107 = 0.813
b) P(electric failure|gas leak) = (55/107)/(87/102) = 0.632
c) P(gas leak| electric failure) = (55/107)/(72/107) = 0.764
Section 2-5
2-73. Let F denote the event that a roll contains a flaw.
Let C denote the event that a roll is cotton.
P ( F ) = P( F C ) P(C ) + P( F C ′) P (C ′)
= (0.02)(0.70) + (0.03)(0.30) = 0.023
2-79. Let A denote a event that the first part selected has excessive shrinkage.
Let B denote the event that the second part selected has excessive shrinkage.
a) P(B)= P( B A )P(A) + P( B A ')P(A')
= (4/24)(5/25) + (5/24)(20/25) = 0.20
b) Let C denote the event that the second part selected has excessive shrinkage.
P(C) = P(C A ∩ B)P( A ∩ B) + P(C A ∩ B')P( A ∩ B')
+P(C A'∩B)P( A'∩B) + P(C A'∩B')P( A'∩B')
3 2 5 4 20 5 4 5 20 5 19 20
= + + +
23 24 25 23 24 25 23 24 25 23 24 25
= 0.20
Image 6: Section 2-6
2-87. It is useful to work one of these exercises with care to illustrate the laws of probability. Let Hi denote the
event that the ith sample contains high levels of contamination.
' ' ' ' ' ' ' ' ' '
a) P(H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 ) = P(H1)P(H2 )P(H3 )P(H4 )P(H5 )
by independence. Also, P(Hi' ) = 0.9 . Therefore, the answer is 0.9 5 = 0.59
b) A1 = (H1 ∩ H'2 ∩ H3 ∩ H4 ∩ H5 )
' ' '
' ' ' '
A 2 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 )
' ' ' '
A 3 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 )
' ' ' '
A 4 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 )
' ' ' '
A 5 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 )
The requested probability is the probability of the union A1 ∪ A 2 ∪ A 3 ∪ A 4 ∪ A 5 and these events
are mutually exclusive. Also, by independence P( A i ) = 0.9 4 (0.1) = 0.0656 . Therefore, the answer is
5(0.0656) = 0.328.
c) Let B denote the event that no sample contains high levels of contamination. The requested
probability is P(B') = 1 - P(B). From part (a), P(B') = 1 - 0.59 = 0.41.
2-89. Let A denote the event that a sample is produced in cavity one of the mold.
1
a) By independence, P( A1 ∩ A 2 ∩ A 3 ∩ A 4 ∩ A 5 ) = ( )5 = 0.00003
8
b) Let Bi be the event that all five samples are produced in cavity i. Because the B's are mutually
exclusive, P(B1 ∪ B 2 ∪...∪B 8 ) = P(B1) + P(B 2 )+...+P(B 8 )
1 1
From part a., P(Bi ) = ( )5 . Therefore, the answer is 8( )5 = 0.00024
8 8
1 7
c) By independence, P( A 1 ∩ A 2 ∩ A 3 ∩ A 4 ∩ A '5 ) = ( ) 4 ( ) . The number of sequences in
8 8
1 7
which four out of five samples are from cavity one is 5. Therefore, the answer is 5( ) 4 ( ) = 0.00107 .
8 8
Section 2-7
2-97. Let G denote a product that received a good review. Let H, M, and P denote products that were high,
moderate, and poor performers, respectively.
a)
P(G ) = P(G H ) P( H ) + P(G M ) P( M ) + P(G P) P( P)
= 0. 95( 0. 40) + 0. 60( 0. 35) + 0. 10( 0. 25)
= 0. 615
b) Using the result from part a.,
P ( G H ) P ( H ) 0. 95( 0. 40)
P( H G ) = = = 0. 618
P( G ) 0. 615
c) P ( H G ' ) = P ( G ' H ) P ( H ) = 0. 05( 0. 40) = 0. 052
P(G' ) 1 − 0. 615
Supplemental
2-105. a) No, P(E1 ∩ E2 ∩ E3) ≠ 0
b) No, E1′ ∩ E2′ is not ∅
c) P(E1′ ∪ E2′ ∪ E3′) = P(E1′) + P(E2′) + P(E3′) – P(E1′∩ E2′) - P(E1′∩ E3′) - P(E2′∩ E3′)
+ P(E1′ ∩ E2′ ∩ E3′)
= 40/240
Image 7: d) P(E1 ∩ E2 ∩ E3) = 200/240
e) P(E1 ∪ E3) = P(E1) + P(E3) – P(E1 ∩ E3) = 234/240
f) P(E1 ∪ E2 ∪ E3) = 1 – P(E1′ ∩ E2′ ∩ E3′) = 1 - 0 = 1
2-107. Let Ai denote the event that the ith bolt selected is not torqued to the proper limit.
a) Then,
P( A 1 ∩ A 2 ∩ A 3 ∩ A 4 ) = P( A 4 A 1 ∩ A 2 ∩ A 3 )P( A 1 ∩ A 2 ∩ A 3 )
= P( A 4 A 1 ∩ A 2 ∩ A 3 )P( A 3 A 1 ∩ A 2 )P( A 2 A 1)P( A 1)
2 3 4 5
= = 0.282
17 18 19 20
b) Let B denote the event that at least one of the selected bolts are not properly torqued. Thus, B' is the
event that all bolts are properly torqued. Then,
15 14 13 12
P(B) = 1 - P(B') = 1 − = 0.718
20 19 18 17
2-113. D = defective copy
2 73 72 73 2 72 73 72 2
a) P(D = 1) = + + = 0.0778
75 74 73 75 74 73 75 74 73
2 1 73 2 73 1 73 2 1
b) P(D = 2) = + + = 0.00108
75 74 73 75 74 73 75 74 73
2-117. Let A i denote the event that the ith washer selected is thicker than target.
30 29 28
a) = 0.207
50 49 8
b) 30/48 = 0.625
c) The requested probability can be written in terms of whether or not the first and second washer selected
are thicker than the target. That is,
' ' ' '
P( A 3 ) = P( A 1A 2 A 3 orA 1A 2 A 3 orA 1A 2 A 3 orA 1A 2 A 3 )
' '
= P( A 3 A 1 A 2 )P( A 1A 2 ) + P( A 3 A 1 A 2 )P( A 1A 2 )
' ' ' ' '
+P( A 3 A 1 'A 2 )P( A 1A 2 ) + P( A 3 A 1 A 2 )P( A 1A 2 )
' '
= P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 ) + P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 )
' ' ' ' ' ' ' '
+P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 ) + P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 )
28 30 29 29 20 30 29 20 30 30 20 19
= + + +
48 50 49 48 50 49 48 50 49 48 50 49
= 0.60
2-121. Let A i denote the event that the ith row operates. Then,
P ( A1 ) = 0. 98, P ( A 2 ) = ( 0. 99)( 0. 99) = 0. 9801, P ( A 3 ) = 0. 9801, P ( A 4 ) = 0. 98.
The probability the circuit does not operate is
P( A1' ) P( A2 ) P( A3 ) P ( A4 ) = (0.02)(0.0199)(0.0199)(0.02) = 1.58 × 10 −7
' ' '
![Image 8: Chapter 3 Selected Problem Solutions
Section 3-2
3-13.
f X (0) = P( X = 0) = 1 / 6 + 1 / 6 = 1 / 3
f X (1.5) = P( X = 1.5) = 1 / 3
f X ( 2) = 1 / 6
f X (3) = 1 / 6
3-21. P(X = 0) = 0.023 = 8 x 10-6
P(X = 1) = 3[0.98(0.02)(0.02)]=0.0012
P(X = 2) = 3[0.98(0.98)(0.02)]=0.0576
P(X = 3) = 0.983 = 0.9412
3-25. X = number of components that meet specifications
P(X=0) = (0.05)(0.02)(0.01) = 0.00001
P(X=1) = (0.95)(0.02)(0.01) + (0.05)(0.98)(0.01)+(0.05)(0.02)(0.99) = 0.00167
P(X=2) = (0.95)(0.98)(0.01) + (0.95)(0.02)(0.99) + (0.05)(0.98)(0.99) = 0.07663
P(X=3) = (0.95)(0.98)(0.99) = 0.92169
Section 3-3
3-27.
0, x < −2
1 / 8 −2 ≤ x < −1
3 / 8 −1 ≤ x < 0
F( x) =
5/8 0 ≤ x<1
7 / 8 1 ≤ x < 2
1 2≤x
a) P(X ≤ 1.25) = 7/8
b) P(X ≤ 2.2) = 1
c) P(-1.1 < X ≤ 1) = 7/8 − 1/8 = 3/4
d) P(X > 0) = 1 − P(X ≤ 0) = 1 − 5/8 = 3/8
3-31.
0 x<0 .
0.008 0 ≤ x < 1 f (0) = 0.2 3 = 0.008,
F ( x) = 0.104 1 ≤ x < 2 where f (1) = 3(0.2)(0.2)(0.8) = 0.096,
0.488 2 ≤ x < 3 f (2) = 3(0.2)(0.8)(0.8) = 0.384,
1
3≤ x f (3) = (0.8) 3 = 0.512,
3-33. a) P(X ≤ 3) = 1
b) P(X ≤ 2) = 0.5
c) P(1 ≤ X ≤ 2) = P(X=1) = 0.5
d) P(X>2) = 1 − P(X≤2) = 0.5
](
![Image 9: Section 3-4
3-37 Mean and Variance
µ = E ( X ) = 0 f (0) + 1 f (1) + 2 f (2) + 3 f (3) + 4 f (4)
= 0(0.2) + 1(0.2) + 2(0.2) + 3(0.2) + 4(0.2) = 2
V ( X ) = 0 2 f (0) + 12 f (1) + 2 2 f (2) + 3 2 f (3) + 4 2 f (4) − µ 2
= 0(0.2) + 1(0.2) + 4(0.2) + 9(0.2) + 16(0.2) − 2 2 = 2
3-41. Mean and variance for exercise 3-19
µ = E ( X ) = 10 f (10) + 5 f (5) + 1 f (1)
= 10(0.3) + 5(0.6) + 1(0.1)
= 6.1 million
V ( X ) = 10 2 f (10) + 5 2 f (5) + 12 f (1) − µ 2
= 10 2 (0.3) + 5 2 (0.6) + 12 (0.1) − 6.12
= 7.89 million 2
3-45. Determine x where range is [0,1,2,3,x] and mean is 6.
µ = E ( X ) = 6 = 0 f (0) + 1 f (1) + 2 f (2) + 3 f (3) + xf ( x)
6 = 0(0.2) + 1(0.2) + 2(0.2) + 3(0.2) + x(0.2)
6 = 1.2 + 0.2 x
4.8 = 0.2 x
x = 24
Section 3-5
3-47. E(X) = (3+1)/2 = 2, V(X) = [(3-1+1)2 -1]/12 = 0.667
3-49. X=(1/100)Y, Y = 15, 16, 17, 18, 19.
1 15 + 19
E(X) = (1/100) E(Y) = = 0.17 mm
100 2
1 (19 − 15 + 1) − 1
2 2
V (X ) = = 0.0002 mm
2
100 12
Section 3-6
10
3-57. a) P ( X = 5) = 0.5 5 (0.5) 5 = 0.2461
5
10 0 10 10 1 9 10 2 8
b) P ( X ≤ 2) = 0.5 0.5 + 0.5 0.5 + 0.5 0.5
0 1 2
= 0.510 + 10(0.5)10 + 45(0.5)10 = 0.0547
](
Image 10: 10 10
c) P( X ≥ 9) = 0.5 9 (0.5)1 + 0.510 (0.5) 0 = 0.0107
9 10
10 10
d) P(3 ≤ X < 5) = 0.530.57 + 0.54 0.56
3 4
= 120(0.5)10 + 210(0.5)10 = 0.3223
3-61. n=3 and p=0.25
3
3 27
f (0) = =
0 x<0 4 64
0.4219 0 ≤ x < 1
2
1 3 27
f (1) = 3 =
4 4 64
F ( x) = 0.8438 1 ≤ x < 2 where 2
0.9844 2 ≤ x < 3 1 3 9
f (2) = 3 =
4 4 64
1
3≤ x 3
1 1
f (3) = =
4 64
1000
3-63. = 1) =
a) P ( X 1 0.001 (0.999) = 0.3681
1 999
1000
1 0.001 (0.999 ) = 0.6323
b) P( X ≥ 1) = 1 − P( X = 0) = 1 − 1 999
1000 1000
c) P ( X ≤ 2) = 0 0.001 (0.999 ) + 1 0.001 (0.999 ) + ( 2 )0.001 0.999
0 1000 1 999 1000 2 998
= 0.9198
d ) E ( X ) = 1000(0.001) = 1
V ( X ) = 1000(0.001)(0.999) = 0.999
3-67. Let X denote the passengers with tickets that do not show up for the flight. Then, X is binomial
with n = 125 and p = 0.1.
a) P( X ≥ 5) = 1 − P( X ≤ 4)
125 0 125 1 125 2
0 0.1 (0.9 ) + 1 0.1 (0.9 ) + 2 0.1 (0.9 )
= 1 −
125 124 123
125 3 125 4 121
+ 0.1 (0.9 ) + 4 0.1 (0.9 ) = 0.9961
122
3
b) P( X > 5) = 1 − P( X ≤ 5) = 0.9886
![Image 11: 3-69. Let X denote the number of questions answered correctly. Then, X is binomial with n = 25
and p = 0.25.
25 25 25
a) P( X ≥ 20) = 0.25 20 (0.75) + 0.25 21 (0.75) + 0.25 22 (0.75)
5 4 3
21 22
20
25 25 25
+ 0.25 23 (0.75) + 0.25 24 (0.75) + 0.25 25 (0.75) ≅ 0
2 1 0
23 24 25
25 25 25
b) P( X < 5) = 0.25 0 (0.75) + 0.251 (0.75) + 0.25 2 (0.75)
25 24 23
1 2
0
25 25
+ 0.253 (0.75) + 0.25 4 (0.75) = 0.2137
22 21
3 4
Section 3-7
3-71. a. P( X= 1) = (1 − 0.5) 0 0.5 = 0.5
b. P( X= 4) = (1 − 0.5) 3 0.5 = 0.5 4 = 0.0625
c. P( X= 8) = (1 − 0.5) 7 0.5 = 0.58 = 0.0039
d. P( X≤ 2) = P ( X = 1) + P( X = 2) = (1 − 0.5) 0 0.5 + (1 − 0.5)1 0.5
= 0.5 + 0.5 2 = 0.75
e. P ( X > 2) = 1 − P ( X ≤ 2) = 1 − 0.75 = 0.25
3-75. Let X denote the number of calls needed to obtain a connection. Then, X is a geometric random variable
with p = 0.02
a) P( X = 10) = (1 − 0.02) 9 0.02 = 0.989 0.02 = 0.0167
b) P( X > 5) = 1 − P( X ≤ 4) = 1 − [ P( X = 1) + P( X = 2) + P( X = 3) + P( X = 4)]
= 1 − [0.02 + 0.98(0.02) + 0.98 2 (0.02) + 0.98 3 (0.02)]
= 1 − 0.0776 = 0.9224
c) E(X) = 1/0.02 = 50
3-77 p = 0.005 , r = 8
a. P( X = 8) = 0.0005 8 = 3.91x10 −19
1
b. µ = E( X ) = = 200 days
0.005
c Mean number of days until all 8 computers fail. Now we use p=3.91x10-19
1
µ = E (Y ) = −91
= 2.56 x1018 days or 7.01 x1015 years
3.91x10
3-81. a) E(X) = 4/0.2 = 20
19
b) P(X=20) = (0.80)16 0.24 = 0.0436
3
18
c) P(X=19) = (0.80) 0.2 = 0.0459
15 4
3
20
d) P(X=21) =
3 (0.80) 0.2 = 0.0411
17 4
](
![Image 12: e) The most likely value for X should be near µX. By trying several cases, the most likely value is x = 19.
3-83. Let X denote the number of fills needed to detect three underweight packages. Then X is a negative
binomial random variable with p = 0.001 and r = 3.
a) E(X) = 3/0.001 = 3000
b) V(X) = [3(0.999)/0.0012] = 2997000. Therefore, σX = 1731.18
Section 3-8
P( X = 1) =
( )( ) = (4 ×16 ×15 ×14) / 6 = 0.4623
4
1
16
3
( ) (20 ×19 ×18 ×17) / 24
3-87. a)
20
4
b) P ( X = 4) =
( )( ) =
4 16
4 0 1
= 0.00021
( ) (20 ×19 ×18 ×17) / 24
20
4
c)
P( X ≤ 2) = P( X = 0) + P( X = 1) + P( X = 2)
=
( )( ) + ( )( ) + ( )( )
4
0
16
4
4
1
16
3
4 16
( ) ( ) ( )
2 2
20 20 20
4 4 4
16×15×14×13 4×16×15×14 6×16×15
+ +
= 24
6
20×19×18×17
2
= 0.9866
24
d) E(X) = 4(4/20) = 0.8
V(X) = 4(0.2)(0.8)(16/19) = 0.539
3-91. Let X denote the number of men who carry the marker on the male chromosome for an increased risk for high
blood pressure. N=800, K=240 n=10
a) n=10
P( X = 1) =
( )( ) = ( )( ) = 0.1201
240 560
1 9
240! 560!
1!239! 9!551!
( ) 800
10
800!
10!790!
b) n=10
P( X > 1) = 1 − P( X ≤ 1) = 1 − [ P( X = 0) + P( X = 1)]
P( X = 0) =
( )( ) = (
240 560
0 10
240!
)( 560!
0!240! 10!560! )
= 0.0276
( ) 800
10
800!
10!790!
P( X > 1) = 1 − P( X ≤ 1) = 1 − [0.0276 + 0.1201] = 0.8523
Section 3-9
e −4 4 0
3-97. a) P( X = 0) = = e −4 = 0.0183
0!
b) P( X ≤ 2) = P( X = 0) + P ( X = 1) + P ( X = 2)
−4 e − 4 41 e − 4 4 2
=e + + = 0.2381
1! 2!
e −4 4 4
c) P( X = 4) = = 0.1954
4!
](
Image 13: e −4 4 8
d) P( X = 8) = = 0.0298
8!
3-99. P( X = 0) = e − λ = 0.05 . Therefore, λ = −ln(0.05) = 2.996.
Consequently, E(X) = V(X) = 2.996.
3-101. a) Let X denote the number of flaws in one square meter of cloth. Then, X is a Poisson random variable
e −0.1 (0.1) 2
with λ = 0.1. P( X = 2) = = 0.0045
2!
b) Let Y denote the number of flaws in 10 square meters of cloth. Then, Y is a Poisson random variable
e −111
with λ = 1. P(Y = 1) = = e −1 = 0.3679
1!
c) Let W denote the number of flaws in 20 square meters of cloth. Then, W is a Poisson random variable
P(W = 0) = e −2 = 0.1353
with λ = 2.
d) P(Y ≥ 2) = 1 − P(Y ≤ 1) = 1 − P(Y = 0) − P(Y = 1)
= 1 − e −1 − e −1
= 0.2642
3-105. a) Let X denote the number of flaws in 10 square feet of plastic panel. Then, X is a Poisson random
−0.5
variable with λ = 0.5. P ( X = 0) = e = 0.6065
b) Let Y denote the number of cars with no flaws,
10
P (Y = 10 ) = ( 0 . 3935 ) 10 ( 0 . 6065 ) 0 = 8 . 9 x10 − 5
10
c) Let W denote the number of cars with surface flaws. Because the number of flaws has a
Poisson distribution, the occurrences of surface flaws in cars are independent events with
constant probability. From part a., the probability a car contains surface flaws is 1−0.6065 =
0.3935. Consequently, W is binomial with n = 10 and p = 0.3935.
10
P (W = 0) = (0.6065) 0 (0.3935)10 = 8.9 x10 −5
0
10
P (W = 1) = (0.6065)1 (0.3935) 9 = 0.001372
1
P (W ≤ 1) = 0.000089 + 0.001372 = 0.00146
Supplemental Exercises
3-107. Let X denote the number of totes in the sample that do not conform to purity requirements. Then, X has a
hypergeometric distribution with N = 15, n = 3, and K = 2.
2 13
0 3
P( X ≥ 1) = 1 − P( X = 0) = 1 − = 1 −
13!12!
= 0.3714
15 10! !
15
3
![Image 14: 3-109. Let Y denote the number of calls needed to obtain an answer in less than 30 seconds.
a) P (Y = 4) = (1 − 0.75) 0.75 = 0.25 3 0.75 = 0.0117
3
b) E(Y) = 1/p = 1/0.75 = 1.3333
e −5 5 5
3-111. a) Let X denote the number of messages sent in one hour. P( X = 5) = = 0.1755
5!
b) Let Y denote the number of messages sent in 1.5 hours. Then, Y is a Poisson random variable with
e −7.5 (7.5)10
λ =7.5. P(Y = 10) = = 0.0858
10!
c) Let W denote the number of messages sent in one-half hour. Then, W is a Poisson random variable with
λ = 2.5. P (W < 2) = P (W = 0) + P (W = 1) = 0.2873
3-119. Let X denote the number of products that fail during the warranty period. Assume the units are
independent. Then, X is a binomial random variable with n = 500 and p = 0.02.
500
a) P(X = 0) =
0 (0.02) (0.98) = 4.1 x 10
0 500 -5
b) E(X) = 500(0.02) = 10
c) P(X >2) = 1 − P(X ≤ 1) = 0.9995
3-121. a) P(X ≤ 3) = 0.2 + 0.4 = 0.6
b) P(X > 2.5) = 0.4 + 0.3 + 0.1 = 0.8
c) P(2.7 < X < 5.1) = 0.4 + 0.3 = 0.7
d) E(X) = 2(0.2) + 3(0.4) + 5(0.3) + 8(0.1) = 3.9
e) V(X) = 22(0.2) + 32(0.4) + 52(0.3) + 82(0.1) − (3.9)2 = 3.09
3-125. Let X denote the number of orders placed in a week in a city of 800,000 people. Then X is a Poisson
random variable with λ = 0.25(8) = 2.
a) P(X ≥ 3) = 1 − P(X ≤ 2) = 1 − [e-2 + e-2(2) + (e-222)/2!] = 1 − 0.6767 = 0.3233.
b) Let Y denote the number of orders in 2 weeks. Then, Y is a Poisson random variable with λ = 4, and
P(Y<2) = P(Y ≤ 1) = e-4 + (e-441)/1! = 0.0916.
3-127. Let X denote the number of totes in the sample that exceed the moisture content. Then X is a binomial
random variable with n = 30. We are to determine p.
30 0
If P(X ≥ 1) = 0.9, then P(X = 0) = 0.1. Then ( p) (1 − p )30 = 0.1 , giving 30ln(1−p)=ln(0.1),
0
which results in p = 0.0738.
3-129. a) Let X denote the number of flaws in 50 panels. Then, X is a Poisson random variable with
λ = 50(0.02) = 1. P(X = 0) = e-1 = 0.3679.
b) Let Y denote the number of flaws in one panel, then
P(Y ≥ 1) = 1 − P(Y=0) = 1 − e-0.02 = 0.0198. Let W denote the number of panels that need to be
inspected before a flaw is found. Then W is a geometric random variable with p = 0.0198 and
E(W) = 1/0.0198 = 50.51 panels.
−0.02
c.) P (Y ≥ 1) = 1 − P (Y = 0) = 1 − e = 0.0198
Let V denote the number of panels with 2 or more flaws. Then V is a binomial random
variable with n=50 and p=0.0198
](
Image 16: Chapter 4 Selected Problem Solutions
Section 4-2
∞
∞
4-1. ∫
a) P (1 < X ) = e − x dx = (−e − x )
1
1
= e −1 = 0.3679
2.5
2.5
∫e
−x
b) P (1 < X < 2.5) = dx = (−e− x ) = e −1 − e− 2.5 = 0.2858
1
1
3
∫
c) P ( X = 3) = e − x dx = 0
3
4
4
∫
d) P ( X < 4) = e − x dx = (−e − x ) = 1 − e − = 0.9817
4
0
0
∞
∞
∫
e) P (3 ≤ X ) = e− x dx = (−e − x )
3
3
= e − 3 = 0.0498
4 4
x x2 4 2 − 32
4-3 a) P ( X < 4) = ∫ dx = = = 0.4375 , because f X ( x) = 0 for x < 3.
3
8 16 3
16
5 5
x x2 5 2 − 3.5 2
b) , P ( X > 3.5) = ∫ dx = = = 0.7969 because f X ( x) = 0 for x > 5.
3. 5
8 16 3.5
16
5 2 5
x x 52 − 4 2
c) P (4 < X < 5) = ∫ 8 dx = 16
4
=
16
= 0.5625
4
4.5 2 4.5
x x 4.5 2 − 3 2
d) P ( X < 4.5) = ∫ 8 dx = 16
3
=
16
= 0.7031
3
5 3.5 5 3.5
x x x2 x2 52 − 4.52 3.52 − 32
e) P( X > 4.5) + P( X < 3.5) = ∫ dx + ∫ dx = + = + = 0.5 .
4.5 8 3 8 16 4.5 16 3 16 16
4-9 a) P(X < 2.25 or X > 2.75) = P(X < 2.25) + P(X > 2.75) because the two events are
mutually exclusive. Then, P(X < 2.25) = 0 and
2.8
P(X > 2.75) = ∫ 2dx = 2(0.05) = 0.10 .
2.75
b) If the probability density function is centered at 2.5 meters, then f X ( x) = 2 for
2.25 < x < 2.75 and all rods will meet specifications.
Section 4-3
4-11. a) P(X<2.8) = P(X ≤ 2.8) because X is a continuous random variable.
Then, P(X<2.8) =F(2.8)=0.2(2.8) = 0.56.
b) P ( X > 1.5) = 1 − P ( X ≤ 1.5) = 1 − 0.2(1.5) = 0.7
Image 17: c) P ( X < −2) = FX (−2) = 0
d) P ( X > 6) = 1 − FX (6) = 0
x
x
−x
4-13. Now, f X ( x ) = e ∫
for 0 < x and F X ( x) = e − x dx = − e − x
0
0
= 1− e−x
0, x ≤ 0
for 0 < x. Then, FX ( x) = −x
1 − e , x > 0
x
x
4-21. F ( x) = ∫ 0.5 xdx = 0.5 x 2
2 = 0.25 x 2 for 0 < x < 2. Then,
0
0
0, x<0
F ( x) = 0.25 x 2 , 0≤ x<2
1, 2≤x
Section 4-4
5 5
x x3 53 − 33
4-25. E ( X ) = ∫ x dx = = = 4.083
3
8 24 3 24
5 5
x
V ( X ) = ∫ ( x − 4.083) 2 dx = ∫ x 2 8 dx − 4.083 2
x
3
8 3
5
x4
= − 4.083 2 = 0.3291
32 3
120
600 120
4-27. a.) E ( X ) = ∫x
100 x 2
dx = 600 ln x 100 = 109.39
120 120
600 (109.39 ) 2
V ( X ) = ∫ ( x − 109.39) 2 dx = 600 ∫ 1 − 2 (109.39 )
x
+ x2
dx
100 x2 100
120
= 600( x − 218.78 ln x − 109.39 2 x −1 ) 100
= 33.19
b.) Average cost per part = $0.50109.39 = $54.70
Image 18: Section 4-5
4-33. a) f(x)= 2.0 for 49.75 < x < 50.25.
E(X) = (50.25 + 49.75)/2 = 50.0,
(50.25 − 49.75) 2
V (X ) = = 0.0208, and σ x = 0.144 .
12
x
b) F ( x) = ∫ 2.0dx for 49.75 < x < 50.25.
49.75
Therefore,
0, x < 49.75
F ( x) = 2 x − 99.5, 49.75 ≤ x < 50.25
1, 50.25 ≤ x
c) P ( X < 50.1) = F (50.1) = 2(50.1) − 99.5 = 0.7
(1.5 + 2.2)
4-35 E( X ) = = 1.85 min
2
(2.2 − 1.5) 2
V (X ) = = 0.0408 min 2
12
2 2
1 2
b) P ( X < 2) = ∫ dx = ∫ 0.7 dx = 0.7 x 1.5 = 0.7(.5) = 0.7143
1. 5
(2.2 − 1.5) 1.5
x x
1 x
c.) F ( X ) = ∫5 (2.2 − 1.5) dx = 1∫50.7dx = 0.7 x 1.5
1. .
for 1.5 < x < 2.2. Therefore,
0, x < 1.5
F ( x) = 0.7 x − 2.14, 1.5 ≤ x < 2.2
1, 2.2 ≤ x
Section 4-6
4-41 a) P(Z < 1.28) = 0.90
b) P(Z < 0) = 0.5
c) If P(Z > z) = 0.1, then P(Z < z) = 0.90 and z = 1.28
d) If P(Z > z) = 0.9, then P(Z < z) = 0.10 and z = −1.28
e) P(−1.24 < Z < z) = P(Z < z) − P(Z < −1.24)
= P(Z < z) − 0.10749.
Therefore, P(Z < z) = 0.8 + 0.10749 = 0.90749 and z = 1.33
![Image 19: 4-43. a) P(X < 13) = P(Z < (13−10)/2)
= P(Z < 1.5)
= 0.93319
b) P(X > 9) = 1 − P(X < 9)
= 1 − P(Z < (9−10)/2)
= 1 − P(Z < −0.5)
= 1 − [1− P(Z < 0.5)]
= P(Z < 0.5)
= 0.69146.
6 − 10 14 − 10
c) P(6 < X < 14) = P
<Z<
2 2
= P(−2 < Z < 2)
= P(Z < 2) −P(Z < − 2)]
= 0.9545.
2 − 10 4 − 10
d) P(2 < X < 4) = P
<Z<
2 2
= P(−4 < Z < −3)
= P(Z < −3) − P(Z < −4)
= 0.00135
e) P(−2 < X < 8) = P(X < 8) − P(X < −2)
8 − 10 −2 − 10
= P Z <
− P Z <
2 2
= P(Z < −1) − P(Z < −6)
= 0.15866.
45 − 65
4-51. a) P(X <45) = P Z <
5
= P(Z < -3)
= 0.00135
65 − 60
b) P(X > 65) = P Z >
5
= PZ >1)
= 1- P(Z < 1)
= 1 - 0.841345
= 0.158655
x − 60
c) P(X < x) = P Z < = 0.99.
5
x − 60
Therefore, 5 = 2.33 and x = 71.6
4-55. a) P(X > 90.3) + P(X < 89.7)
90.3 − 90.2 89.7 − 90.2
= P Z > + P Z <
0.1 0.1
= P(Z > 1) + P(Z < −5)
= 1 − P(Z < 1) + P(Z < −5)
](
Image 20: =1 − 0.84134 +0
= 0.15866.
Therefore, the answer is 0.15866.
b) The process mean should be set at the center of the specifications; that is, at µ = 90.0.
89.7 − 90 90.3 − 90
c) P(89.7 < X < 90.3) = P <Z<
0.1 0.1
= P(−3 < Z < 3) = 0.9973.
The yield is 1000.9973 = 99.73%
0.0026 − 0.002
4-59. a) P(X > 0.0026) = P Z >
0.0004
= P(Z > 1.5)
= 1-P(Z < 1.5)
= 0.06681.
0.0014 − 0.002 0.0026 − 0.002
b) P(0.0014 < X < 0.0026) = P <Z<
0.0004 0.0004
= P(−1.5 < Z < 1.5)
= 0.86638.
0.0014 − 0.002 0.0026 − 0.002
c) P(0.0014 < X < 0.0026) = P <Z<
σ σ
− 0.0006 0.0006
= P <Z< .
σ σ
0.0006
Therefore, P Z <
= 0.9975. Therefore,
0 . 0006 = 2.81 and σ = 0.000214.
σ
σ
Section 4-7
4-67 Let X denote the number of errors on a web site. Then, X is a binomial random variable
with p = 0.05 and n = 100. Also, E(X) = 100 (0.05) = 5 and
V(X) = 100(0.05)(0.95) = 4.75
1− 5
P( X ≥ 1) ≅ P Z ≥
= P( Z ≥ −1.84) = 1 − P( Z < −1.84) = 1 − 0.03288 = 0.96712
4.75
4-69 Let X denote the number of hits to a web site. Then, X is a Poisson random variable with
a of mean 10,000 per day. E(X) = λ = 10,000 and V(X) = 10,000
a)
10,200 − 10,000
P( X ≥ 10,200) ≅ P Z ≥
= P ( Z ≥ 2) = 1 − P( Z < 2)
10,000
= 1 − 0.9772 = 0.0228
Image 21: Expected value of hits days with more than 10,200 hits per day is
(0.0228)365=8.32 days per year
b.) Let Y denote the number of days per year with over 10,200 hits to a web site.
Then, Y is a binomial random variable with n=365 and p=0.0228.
E(Y) = 8.32 and V(Y) = 365(0.0228)(0.9772)=8.13
15 − 8.32
P(Y > 15) ≅ P Z ≥ = P( Z ≥ 2.34) = 1 − P( Z < 2.34)
8.13
= 1 − 0.9904 = 0.0096
Section 4-9
4-77. Let X denote the time until the first call. Then, X is exponential and
λ = E (1X ) = 15 calls/minute.
1
∞ x x ∞
− −
a) P ( X > 30) = ∫
30
1
15
e 15 dx = − e 15
30
= e − 2 = 0.1353
b) The probability of at least one call in a 10-minute interval equals one minus the
probability of zero calls in
a 10-minute interval and that is P(X > 10).
− x ∞
P( X > 10) = − e 15
= e − 2 / 3 = 0.5134 .
10
Therefore, the answer is 1- 0.5134 = 0.4866. Alternatively, the requested probability is
equal to P(X < 10) = 0.4866.
x 10
− 15
c) P (5 < X < 10) = − e = e −1 / 3 − e − 2 / 3 = 0.2031
5
− t x
d) P(X < x) = 0.90 and P ( X < x) = − e 15
= 1 − e − x / 15 = 0.90 . Therefore, x = 34.54
0
minutes.
4-79. Let X denote the time to failure (in hours) of fans in a personal computer. Then, X is an
exponential random variable and λ = 1 / E ( X ) = 0.0003 .
∞ ∞
∫ 0.0003e
− x 0.0003 − x 0.0003
a) P(X > 10,000) = dx = − e = e −3 = 0.0498
10 , 000 10 , 000
7 , 000 7 , 000
∫ 0.0003e
− x 0.0003
b) P(X < 7,000) = dx = − e − x 0.0003 = 1 − e − 2.1 = 0.8775
0 0
4-81. Let X denote the time until the arrival of a taxi. Then, X is an exponential random
variable with λ = 1 / E ( X ) = 0.1 arrivals/ minute.
Image 22: ∞ ∞
∫ 0.1e dx = − e
− 0. 1 x − 0.1 x
a) P(X > 60) = = e − 6 = 0.0025
60 60
10 10
∫ 0.1e dx = − e
− 0.1 x − 0.1 x
b) P(X < 10) = = 1 − e −1 = 0.6321
0 0
4-83. Let X denote the distance between major cracks. Then, X is an exponential random
variable with λ = 1 / E ( X ) = 0.2 cracks/mile.
∞ ∞
∫ 0.2e dx = − e
− 0. 2 x − 0.2 x
a) P(X > 10) = = e − 2 = 0.1353
10 10
b) Let Y denote the number of cracks in 10 miles of highway. Because the distance
between cracks is exponential, Y is a Poisson random variable with λ = 10(0.2) = 2
cracks per 10 miles.
e −2 2 2
P(Y = 2) = = 0.2707
2!
c) σ X = 1 / λ = 5 miles.
4-87. Let X denote the number of calls in 3 hours. Because the time between calls is an
exponential random variable, the number of calls in 3 hours is a Poisson random variable.
Now, the mean time between calls is 0.5 hours and λ = 1 / 0.5 = 2 calls per hour = 6 calls in
3 hours.
P( X ≥ 4) = 1 − P( X ≤ 3) = 1 − e 6 + e 6 + e 6 + e 6 = 0.8488
−6 0 −6 1 −6 2 −6 3
0!
1! 2! 3!
Section 4-10
4-97. Let Y denote the number of calls in one minute. Then, Y is a Poisson random variable
with λ = 5 calls per minute.
e −5 5 4
a) P(Y = 4) = = 0.1755
4!
e −5 50 e −5 51 e −5 52
b) P(Y > 2) = 1 - P (Y ≤ 2) = 1 − − − = 0.8754 .
0! 1! 2!
Let W denote the number of one minute intervals out of 10 that contain more than 2
calls. Because the calls are a Poisson process, W is a binomial random variable with n =
10 and p = 0.8754.
( )
10 10 0
Therefore, P(W = 10) = 10 0.8754 (1 − 0.8754) = 0.2643 .
4-101. Let X denote the number of bits until five errors occur. Then, X has an Erlang distribution
with r = 5 and λ = 10 −5 error per bit.
![Image 23: r
a) E(X) = = 5 × 105 bits.
λ
r
b) V(X) = 2 = 5 × 10 and σ X = 5 × 10 = 223607 bits.
10 10
λ
c) Let Y denote the number of errors in 105 bits. Then, Y is a Poisson random variable
with
λ = 1 / 105 = 10−5 error per bit = 1 error per 105 bits.
−1 0
[
P(Y ≥ 3) = 1 − P(Y ≤ 2) = 1 − e 0!1 + e 1!1 + e 2!1 = 0.0803
−1 1 −1 2
]
4-105. a) Γ(6) = 5!= 120
b) Γ( 5 ) = 3 Γ( 3 ) =
2 2 2
3 1
2 2
Γ( 1 ) = 3 π 1 / 2 = 1.32934
2 4
c) Γ( 9 ) = 7 Γ( 7 ) = 7 5 3 1 Γ( 1 ) = 105 π 1 / 2 = 11.6317
2 2 2 2 2 2 2 2 16
Section 4-11
4-109. β=0.2 and δ=100 hours
E ( X ) = 100Γ(1 + 1
0. 2
) = 100 × 5!= 12,000
V ( X ) = 100 2 Γ(1 + 2
0.2
) − 100 2 [Γ(1 + 1
0.2
)]2 = 3.61 × 1010
4-111. Let X denote lifetime of a bearing. β=2 and δ=10000 hours
2
8000
− 2
a) P( X > 8000) = 1 − FX (8000) = e 10000
= e − 0.8 = 0.5273
b)
E ( X ) = 10000Γ(1 + 1 ) = 10000Γ(1.5)
2
= 10000(0.5)Γ(0.5) = 5000 π = 8862.3
= 8862.3
hours
c) Let Y denote the number of bearings out of 10 that last at least 8000 hours. Then, Y is
a
binomial random variable with n = 10 and p = 0.5273.
( )
P(Y = 10) = 10 0.527310 (1 − 0.5273) 0 = 0.00166 .
10
Section 4-12
4-117 X is a lognormal distribution with θ=5 and ω2=9
a. )
ln(13330) − 5
P( X < 13300) = P(e W < 13300) = P (W < ln(13300)) = Φ
3
= Φ(1.50) = 0.9332
b.) Find the value for which P(X≤x)=0.95
](
Image 24: ln( x) − 5
P( X ≤ x) = P(e W ≤ x) = P(W < ln( x)) = Φ = 0.95
3
ln( x) − 5
= 1.65 x = e 1.65(3) + 5 = 20952.2
3
2
c.) µ = E ( X ) = e θ +ω = e 5+ 9 / 2 = e 9.5 = 13359.7
/2
2 2
V ( X ) = e 2θ +ω (e ω − 1) = e 10 + 9 (e 9 − 1) = e 19 (e 9 − 1) = 1.45 × 1012
4-119 a.) X is a lognormal distribution with θ=2 and ω2=4
ln(500) − 2
P( X < 500) = P(e W < 500) = P(W < ln(500)) = Φ
2
= Φ(2.11) = 0.9826
b.)
P(1000 < X < 1500)
P( X < 15000 | X > 1000) =
P( X > 1000)
ln(1500) − 2 ln(1000) − 2
Φ 2
− Φ
2
=
ln(1000) − 2
1 − Φ 2
Φ(2.66) − Φ(2.45) 0.9961 − 0.9929
= = = 0.0032 / 0.007 = 0.45
(1 − Φ(2.45) ) (1 − 0.9929)
c.) The product has degraded over the first 1000 hours, so the probability of it lasting
another 500 hours is very low.
4-121 Find the values of θand ω2 given that E(X) = 100 and V(X) = 85,000
Image 25: 100 2 2
x =
y 85000 = e 2θ +ω (eω − 1)
2
let x = eθ and y = e ω
2 2 2 2
then (1) 100 = x y and (2) 85000= x y( y −1) = x y − x y
2
Square (1) 10000 = x y and substitute into (2)
85000 = 10000 ( y − 1)
y = 9 .5
100
Substitute y into (1) and solve for x x = = 32.444
9.5
θ = ln(32.444) = 3.45 and ω 2 = ln(9.5) = 2.25
Supplemental Exercises
4-127. Let X denote the time between calls. Then, λ = 1 / E ( X ) = 0.1 calls per minute.
5 5
∫
a) P ( X < 5) = 0.1e − x dx = −e − x = 1 − e − 0.5 = 0.3935
0.1 0.1
0 0
15
b) P (5 < X < 15) = −e − 0.1 x = e − 0.5 − e −1.5 = 0.3834
5
x
∫
c) P(X < x) = 0.9. Then, P ( X < x) = 0.1e − t dt = 1 − e − x = 0.9 . Now, x = 23.03
0.1 0.1
0
minutes.
4-129. a) Let Y denote the number of calls in 30 minutes. Then, Y is a Poisson random variable
e −3 3 0 e −3 31 e −3 3 2
with x = e θ . P(Y ≤ 2) = + + = 0.423 .
0! 1! 2!
b) Let W denote the time until the fifth call. Then, W has an Erlang distribution with
λ = 0.1 and r = 5.
E(W) = 5/0.1 = 50 minutes
4-137. Let X denote the thickness.
5.5 − 5
a) P(X > 5.5) = P Z > = P(Z > 2.5) = 0. 0062
0.2
4.5 − 5 5.5 − 5
b) P(4.5 < X < 5.5) = P <Z < = P (-2.5 < Z < 2.5) = 0.9876
0.2 0.2
Therefore, the proportion that do not meet specifications is 1 − P(4.5 < X < 5.5) =
0.012.
Image 26: x −5 x −5
c) If P(X < x) = 0.90, then P Z > = 0.9. Therefore, = 1.65 and x = 5.33.
0.2 0.2
4-139. If P(0.002-x < X < 0.002+x), then P(-x/0.0004 < Z < x/0.0004) = 0.9973. Therefore,
x/0.0004 = 3 and x = 0.0012. The specifications are from 0.0008 to 0.0032.
10 , 000 − µ 10, 000− µ
4-141. If P(X > 10,000) = 0.99, then P(Z > 600 ) = 0.99. Therefore, 600 = -2.33 and
µ = 11,398 .
4-143 X is an exponential distribution with E(X) = 7000 hours
5800 x 5800
1 − −
a.) P ( X < 5800) = ∫
0 7000
e 7000 dx = 1 − e 7000 = 0.5633
∞ x x
1 − −
b.) P ( X > x ) = ∫ e 7000 dx =0.9 Therefore, e 7000 = 0.9
x
7000
and x = −7000 ln(0.9) = 737.5 hours
![Image 27: Chapter 5 Selected Problem Solutions
Section 5-1
5-7.
E ( X ) = 1[ f XY (1,1) + f XY (1,2) + f XY (1,3)] + 2[ f XY (2,1) + f XY (2,2) + f XY (2,3)]
+ 3[ f XY (3,1) + f XY (3,2) + f XY (3,3)]
= (1 × 36 ) + (2 × 12 ) + (3 × 15 ) = 13 / 6 = 2.167
9
36 36
V ( X ) = (1 − 13 ) 2
6
9
36 + (2 − 13 ) 2
6
12
36 + (3 − 13 ) 2
6
15
36 = 0.639
E (Y ) = 2.167
V (Y ) = 0.639
5-11.
E ( X ) = −1( 1 ) − 0.5( 1 ) + 0.5( 1 ) + 1( 1 ) =
8 4 2 8
1
8
E (Y ) = −2( 1 ) − 1( 1 ) + 1( 1 ) + 2( 1 ) =
8 4 2 8
1
4
5-15 a) The range of (X,Y) is X ≥ 0, Y ≥ 0 and X + Y ≤ 4 . X is the number of pages with moderate
graphic content and Y is the number of pages with high graphic output out of 4.
x=0 x=1 x=2 x=3 x=4
-05
y=4 5.35x10 0 0 0 0
y=3 0.00183 0.00092 0 0 0
y=2 0.02033 0.02066 0.00499 0 0
y=1 0.08727 0.13542 0.06656 0.01035 0
y=0 0.12436 0.26181 0.19635 0.06212 0.00699
b.)
x=0 x=1 x=2 x=3 x=4
f(x) 0.2338 0.4188 0.2679 0.0725 0.0070
c.)
E(X)=
4
∑x 0
i f ( xi ) = 0(0.2338) + 1(0.4188) + 2(0.2679) + 3(0.7248) = 4(0.0070) = 1.2
f XY (3, y )
d.) f Y 3 ( y) = , fx(3) = 0.0725
f X (3)
y fY|3(y)
0 0.857
1 0.143
2 0
3 0
4 0
e) E(Y|X=3) = 0(0.857)+1(0.143) = 0.143
](
![Image 28: Section 5-2
5-17. a) P( X = 2) = f XYZ (2,1,1) + f XYZ (2,1,2) + f XYZ (2,2,1) + f XYZ (2,2,2) = 0.5
b) P( X = 1, Y = 2) = f XYZ (1,2,1) + f XYZ (1,2,2) = 0.35
c) P( Z < 1.5) = f XYZ (1,1,1) + f XYZ (1,2,2) + f XYZ (2,1,1) + f XYZ (2,2,1) = 0.5
d)
P( X = 1 or Z = 1) = P( X = 1) + P( Z = 1) − P( X = 1, Z = 1) = 0.5 + 0.5 − 0.2 = 0.8
e) E(X) = 1(0.5) + 2(0.5) = 1.5
5-25. P(X=x, Y=y, Z=z) is the number of subsets of size 4 that contain x printers with graphics enhancements, y
printers with extra memory, and z printers with both features divided by the number of subsets of size 4.
From the results on the CD material on counting techniques, it can be shown that
( )( )( )
4
x
5
y
6
z
P ( X = x, Y = y , Z = z ) =
( ) 15
for x+y+z = 4.
4
a) P ( X = 1, Y = 2, Z = 1) =
( )( )( ) = 0.1758
4 5
1 2
6
1
( ) 15
4
b) P ( X = 1, Y = 1) = P ( X = 1, Y = 1, Z = 2) =
( )( )( ) = 0.2198
4
1 1
5 6
2
( ) 15
4
c) The marginal distribution of X is hypergeometric with N = 15, n = 4, K = 4.
Therefore, E(X) = nK/N = 16/15 and V(X) = 4(4/15)(11/15)[11/14] = 0.6146.
P( X = 2, Y = 2) 0.1944
5-29 a.) P( X = 2 | Y = 2) = = = 0.7347
P(Y = 2) 0.2646
P( X = 2, Y = 2) = 0.1922
4
P(Y = 2) = 0.3 2 0.7 4 = 0.2646
2 from the binomial marginal distribution of Y
b) Not possible, x+y+z=4, the probability is zero.
c.) P( X | Y = 2) = P( X = 0 | Y = 2), P( X = 1 | Y = 2), P( X = 2 | Y = 2)
P( X = 0, Y = 2) 4!
P( X = 0 | Y = 2) = = 0.6 0 0.3 2 0.12 0.2646 = 0.0204
P(Y = 2) 0!2!2!
P ( X = 1, Y = 2) 4!
P ( X = 1 | Y = 2) = = 0.610.3 2 0.11 0.2646 = 0.2449
P(Y = 2) 1!2!1!
P( X = 2, Y = 2) 4!
P( X = 2 | Y = 2) = = 0.6 2 0.3 2 0.10 0.2646 = 0.7347
P(Y = 2) 2!2!0!
d.) E(X|Y=2)=0(0.0204)+1(0.2449)+2(0.7347) = 1.7142
5-31 a.), X has a binomial distribution with n = 3 and p = 0.01. Then, E(X) = 3(0.01) = 0.03
and V(X) = 3(0.01)(0.99) = 0.0297.
](
Image 29: P( X | Y = 2)
b.) first find
P(Y = 2) = P( X = 1, Y = 2, Z = 0) + P( X = 0, Y = 2, Z = 1)
3! 3!
= 0.01(0.04) 2 0.95 0 + 0.010 (0.04) 2 0.951 = 0.0046
1!2!0! 0!2!1!
P( X = 0, Y = 2) 3!
P( X = 0 | Y = 2) = = 0.010 0.04 2 0.951 0.004608 = 0.98958
P(Y = 2) 0!2!1!
P( X = 1, Y = 2) 3!
P( X = 1 | Y = 2) = = 0.0110.04 2 0.95 0 0.004608 = 0.01042
P(Y = 2) 1!2!1!
E ( X | Y = 2) = 0(0.98958) + 1(0.01042) = 0.01042
V ( X | Y = 2) = E ( X 2 ) − ( E ( X )) 2 = 0.01042 − (0.01042) 2 = 0.01031
Section 5-3
3 2 3
5-35. a) P( X < 2, Y < 3) = 4
81 ∫ ∫ xydxdy =
0 0
4
81 (2) ∫ ydy = 81 (2)( 9 ) = 0.4444
0
4
2
b) P(X < 2.5) = P(X < 2.5, Y < 3) because the range of Y is from 0 to 3.
3 2. 5 3
P( X < 2.5, Y < 3) = 4
81 ∫ ∫ xydxdy =
0 0
4
81 (3.125) ∫ ydy = 81 (3.125) 9 = 0.6944
4
0
2
2. 5 3 2.5 2.5
y2
c) P(1 < Y < 2.5) = 4
81 ∫ ∫ xydxdy =
1 0
4
81 (4.5) ∫ ydy = 18
1
81 2
1
=0.5833
2.5 3 2.5
2
d) P( X > 1.8,1 < Y < 2.5) = 4
81 ∫ ∫ xydxdy =
1 1.8
4
81 (2.88) ∫ ydy =
1
4
81 (2.88) ( 2.52 −1) =0.3733
3 3 3 3
2
∫∫x ∫ 9 ydy = 4 y
2
e) E( X ) = 4
81
ydxdy = 4
81 9 2
=2
0 0 0 0
4 0 4
f) P( X < 0, Y < 4) = 4
81 ∫ ∫ xydxdy = 0∫ ydy = 0
0 0 0
![Image 30: 5-37.
3 x+2 3 x+2
y2
c ∫ ∫ ( x + y )dydx = ∫ xy + 2 dx
0 x 0 x
[ ]dx
3
( x+ 2)2
= ∫ x( x + 2) + 2 − x2 − x2
2
0
3
= c ∫ (4 x + 2)dx = 2 x 2 + 2 x [ ] 3
0
= 24c
0
Therefore, c = 1/24.
5-39. a) f X (x) is the integral of f XY ( x, y ) over the interval from x to x+2. That is,
x+2
1 1 y2
x+2
x 1
f X ( x) =
24 ∫ ( x + y)dy =
x
24
xy + 2
x
= 6 + 12
for 0 < x < 3.
1
f XY (1, y )
(1+ y ) 1+ y
b) f Y 1 ( y) = f X (1) = 24
1 1 = for 1 < y < 3.
+
6 12
6
See the following graph,
y
2 f (y) defined over this line segment
Y|1
1
0 1 2 x
0
3
3 3
1+ y 1 1 y2 y3
∫ 6 61
dy = ∫ ( y + y )dy = = 2.111
2
c) E(Y|X=1) = y +
1
6 2
3 1
2
3 3
1+ y 1 1 y2
d.) P (Y > 2 | X = 1) = ∫ dy = ∫ (1 + y )dy = y + =0.4167
2 6 61 6
2 1
f XY ( x , 2 )
e.) f X 2 ( x) = fY ( 2) . Here f Y ( y) is determined by integrating over x. There are three regions of
integration. For 0< y≤2 the integration is from 0 to y. For 2< y≤3 the integration is from y-2 to y.
For 3 < y < 5 the integration is from y to 3. Because the condition is x=2, only the first integration is
y
1 1 x2 y
y2
needed. fY ( y) = ∫
24 0
( x + y )dx = 2 + xy 0 =
24
16 for 0 < y ≤ 2.
](
Image 31: y
f X|2 (x) defined over this line segment
2
1
0 1 2 x
0
1
( x + 2)
24 x+2
Therefore, fY (2) = 1 / 4 and f X 2 ( x) = = for 0 < x < 2
1/ 4 6
5-43. Solve for c
∞ x ∞ ∞
c −2 x c −2 x
c ∫ ∫ e − 2 x −3 y dyd x = ∫ e (1 − e )d x = 3 ∫ e − e d x
−3 x −5 x
0 0
30 0
c 1 1 1
= − = c. c = 10
3 2 5 10
5-49. The graph of the range of (X, Y) is
y
5
4
3
2
1
0 1 2 3 4 x
1 x +1 4 x +1
∫ ∫ cdydx + ∫ ∫ cdydx = 1
0 0 1 x −1
1 4
= c ∫ ( x + 1)dx + 2c ∫ dx
0 1
= c + 6c = 7.5c = 1
3
2
Therefore, c = 1/7.5=2/15
5-51. a. )
x +1
1 x +1
f ( x) = ∫
0
7.5
dy = for
7.5
0 < x < 1,
x +1
1 x + 1 − ( x − 1) 2
f ( x) =
x −1
∫7.5
dy =
7.5
=
7.5
for 1 < x < 4
Image 32: b. )
f XY (1, y ) 1 / 7.5
f Y | X =1 ( y ) = = = 0.5
f X (1) 2 / 7.5
f Y | X =1 ( y ) = 0.5 for 0 < y < 2
2 2
y y2
c. ) E (Y | X = 1) = ∫ dy = =1
0
2 4 0
0.5 0.5
d.) P (Y < 0.5 | X = 1) = ∫ 0.5dy = 0.5 y = 0.25
0 0
5-53 a.) µ=3.2 λ=1/3.2
∞ ∞
−
x
−
y ∞
−
x
− 352
P ( X > 5 , Y > 5 ) = 10 . 24 ∫ ∫ e 3 .2 3 .2
dydx = 3 . 2 ∫ e 3 .2 e . dx
5 5 5
−5 − 352
= e 3 .2
e .
= 0 . 0439
∞∞
−
x
−
y ∞
−
x
− 3.2
10
P( X > 10, Y > 10) = 10.24 ∫ ∫ e 3.2 3.2
dydx = 3.2 ∫ e 3.2 e dx
10 10 10
−
10
−
10
= e
3.2 e
3.2 = 0.0019
b.) Let X denote the number of orders in a 5-minute interval. Then X is a Poisson
random variable with λ=5/3.2 = 1.5625.
e −1.5625 (1.5625) 2
P( X = 2) = = 0.256
21
2
For both systems, P ( X = 2) P ( X = 2) = 0.256 = 0.0655
c.) The joint probability distribution is not necessary because the two processes are
independent and we can just multiply the probabilities.
Section 5-4
0. 5 1 1 0.5 1 0.5 0.5
∫ ∫ ∫ (8 xyz)dzdydx = ∫ ∫ (4 xy)dydx = ∫ (2 x)dx = x
2
5-55. a) P( X < 0.5) = = 0.25
0 0 0 0 0 0 0
b)
Image 33: 0.5 0.5 1
P( X < 0.5, Y < 0.5) = ∫ ∫ ∫ (8 xyz)dzdydx
0 0 0
0.5 0.5 0.5 0.5
= ∫
0 0
∫ (4 xy)dydx = ∫ (0.5 x)dx =
0
x2
4
0
= 0.0625
c) P(Z < 2) = 1, because the range of Z is from 0 to 1.
d) P(X < 0.5 or Z < 2) = P(X < 0.5) + P(Z < 2) - P(X < 0.5, Z < 2). Now, P(Z < 2) =1 and
P(X < 0.5, Z < 2) = P(X < 0.5). Therefore, the answer is 1.
1 1 1 1
e) E ( X ) = ∫ ∫ ∫ (8 x yz )dzdydx = ∫ (2 x 2 )dx =
2 2 x3
3 = 2/3
0 0 0 0
1
5-57. a) fYZ ( y, z ) = ∫ (8 xyz )dx = 4 yz for 0 < y < 1 and 0 < z < 1.
0
f XYZ ( x, y, z ) 8 x(0.5)(0.8)
Then, f X YZ ( x) = = = 2x for 0 < x < 1.
fYZ ( y, z ) 4(0.5)(0.8)
0.5
b) Therefore, P( X < 0.5 Y = 0.5, Z = 0.8) = ∫ 2 xdx = 0.25
0
5-61 Determine c such that f ( xyz ) = c is a joint density probability over the region x>0, y>0
and z>0 with x+y+z<1
1 1− x 1− x − y 1 1− x 1 2 1− x
f ( xyz ) = c ∫ c( y − xy − y ) dx
∫ ∫ dzdydx =∫ ∫ c(1 − x − y )dydx = ∫ 2 0
0 0 0 0 0 0
1
1
(1 − x) 2 1
(1 − x )2 1 x2 x3
= ∫ c
(1 − x) − x(1 − x) − dx = ∫ c dx = c x −
+
0 2
0
2
2 2 6 0
1
= c . Therefore, c = 6.
6
5-63 a.)
1− x
1− x 1− x − y 1− x
y2
f ( x) = 6 ∫ ∫ dzdy = ∫ 6(1 − x − y)dy = y − xy − 2
0 0 0 0
x2 1
= 6( − x + ) = 3( x − 1) 2 for 0 < x < 1
2 2
b.)
1− x − y
f ( x, y ) = 6 ∫ dz = 6(1 − x − y )
0
for x > 0 , y > 0 and x + y < 1
c.)
![Image 34: f ( x, y = 0.5, z = 0,5) 6
f ( x | y = 0.5, z = 0.5) = = = 1 For, x = 0
f ( y = 0.5, z = 0.5) 6
2
d. ) The marginal f Y ( y ) is similar to f X (x) and f Y ( y ) = 3(1 − y ) for 0 < y < 1.
f ( x,0.5) 6(0.5 − x)
f X |Y ( x | 0.5) = = = 4(1 − 2 x) for x < 0.5
f Y (0.5) 3(0.25)
5-65. 5-65. a) Let X denote the weight of a brick. Then,
P( X > 2.75) = P( Z > 2.75 − 3
0.25
) = P( Z > −1) = 0.84134 .
Let Y denote the number of bricks in the sample of 20 that exceed 2.75 pounds. Then, by
independence, Y has a binomial distribution with n = 20 and p = 0.84134. Therefore,
20
( ) 20
the answer is P (Y = 20) = 20 0.84134 = 0.032 .
b) Let A denote the event that the heaviest brick in the sample exceeds 3.75 pounds.
Then, P(A) = 1 - P(A') and A' is the event that all bricks weigh less than 3.75 pounds. As
in part a., P(X < 3.75) = P(Z < 3) and
P( A) = 1 − [ P( Z < 3)] 20 = 1 − 0.99865 20 = 0.0267 .
Section 5-5
5-67. E(X) = 1(3/8)+2(1/2)+4(1/8)=15/8 = 1.875
E(Y) = 3(1/8)+4(1/4)+5(1/2)+6(1/8)=37/8 = 4.625
E(XY) = [1 × 3 × (1/8)] + [1 × 4 × (1/4)] + [2 × 5 × (1/2)] + [4 × 6 × (1/8)]
= 75/8 = 9.375
σ XY = E ( XY ) − E ( X ) E (Y ) = 9.375 − (1.875)(4.625) = 0.703125
V(X) = 12(3/8)+ 22(1/2) +42(1/8)-(15/8)2 = 0.8594
V(Y) = 32(1/8)+ 42(1/4)+ 52(1/2) +62(1/8)-(15/8)2 = 0.7344
σ XY 0.703125
ρ XY = = = 0.8851
σ XσY (0.8594)(0.7344)
5-69.
3 3
∑ ∑ c( x + y) = 36c,
x =1 y =1
c = 1 / 36
2
13 13 14 14 13 −1
E( X ) = E (Y ) = E ( XY ) = σ xy = − =
6 6 3 3 6 36
16 16 23
E( X 2 ) = E (Y 2 ) = V ( X ) = V (Y ) =
3 3 36
−1
ρ= 36 = −0.0435
23 23
36 36
](
Image 35: 2 + 2 +
1 x 1 5 x 1
19 ∫ ∫
5-73. E( X ) = xdydx + ∫ ∫ xdydx = 2.614
0 0
19 1 x −1
1 x +1
2 +
5 x 1
2
19 ∫ ∫ ydydx + 19 ∫ x∫1
E (Y ) = ydydx = 2.649
0 0 1 −
1 x +1
2 +
5 x 1
2
19 ∫ ∫ xydydx + 19 ∫ x∫1
Now, E ( XY ) = xydydx = 8.7763
0 0 1 −
σ xy = 8.7763 − (2.614)(2.649) = 1.85181
E ( X 2 ) = 8.7632 E (Y 2 ) = 9.07895
V ( x) = 1.930, V (Y ) = 2.062
1.852
ρ= = 0.9279
1.930 2.062
Section 5-6
5-81. Because ρ = 0 and X and Y are normally distributed, X and Y are independent. Therefore,
µX = 0.1mm σX=0.00031mm µY = 0.23mm σY=0.00017mm
Probability X is within specification limits is
0.099535 − 0.1 0.100465 − 0.1
P(0.099535 < X < 0.100465) = P <Z <
0.00031 0.00031
= P(−1.5 < Z < 1.5) = P( Z < 1.5) − P( Z < −1.5)
= 0.8664
Probability that Y is within specification limits is
0.22966 − 0.23 0.23034 − 0.23
P(0.22966 < X < 0.23034) = P <Z<
0.00017 0.00017
= P(−2 < Z < 2) = P( Z < 2) − P( Z < −2)
= 0.9545
Probability that a randomly selected lamp is within specification limits is (0.8664)(.9594)=0.8270
Section 5-7
5-87. a) E(2X + 3Y) = 2(0) + 3(10) = 30
b) V(2X + 3Y) = 4V(X) + 9V(Y) = 97
c) 2X + 3Y is normally distributed with mean 30 and variance 97. Therefore,
P(2 X + 3Y < 30) = P( Z < 30 − 30
97
) = P( Z < 0) = 0.5
d) P(2 X + 3Y < 40) = P( Z < 40 −30
97
) = P( Z < 1.02) = 0.8461
5-89 a) Let T denote the total thickness. Then, T = X + Y and E(T) = 4 mm,
V(T) = 0.12 + 0.12 = 0.02mm 2 , and σ T = 0.1414 mm.
Image 36: b)
4.3 − 4
P(T > 4.3) = P Z > = P( Z > 2.12)
0.1414 2.12) = 1 - 0.983 = 0.017
= 1 − P( Z < 2.12) = 1 − 0.983 = 0.0170
5-93. a) Let X denote the average fill-volume of 100 cans. σ X
= 0.5 2
100 = 0.05 .
12 − 12.1
b) E( X ) = 12.1 andP( X < 12) = P Z < = P( Z < −2) = 0.023
0.05
12 − µ
c) P( X < 12) = 0.005 implies that P Z < = 0.005.
0.05
12 − µ
Then 0.05 = -2.58 and µ = 12.129 .
12 − 12.1
d.) P( X < 12) = 0.005 implies that P Z <
= 0.005.
σ / 100
Then 12 −12.1
= -2.58 and σ = 0.388 .
σ / 100
12 − 12.1
e.) P( X < 12) = 0.01 implies that P Z <
= 0.01.
0.5 / n
Then 12−12.1
0.5 / n
= -2.33 and n = 135.72 ≅ 136 .
Supplemental Exercises
5-97. a) P ( X < 0.5, Y < 1.5) = f XY (0,1) + f XY (0,0) = 1 / 8 + 1 / 4 = 3 / 8 .
b) P ( X ≤ 1) = f XY (0,0) + f XY (0,1) + f XY (1,0) + f XY (1,1) = 3 / 4
c) P (Y < 1.5) = f XY (0,0) + f XY (0,1) + f XY (1,0) + f XY (1,1) = 3 / 4
d) P ( X > 0.5, Y < 1.5) = f XY (1,0) + f XY (1,1) = 3 / 8
e) E(X) = 0(3/8) + 1(3/8) + 2(1/4) = 7/8.
V(X) = 02(3/8) + 12(3/8) + 22(1/4) - 7/82 =39/64
E(Y) = 1(3/8) + 0(3/8) + 2(1/4) = 7/8.
. V(Y) = 12(3/8) + 02(3/8) + 22(1/4) - 7/82 =39/64
1 1 1 1 1
y2
5-105. a) P( X < 1, Y < 1) = ∫ ∫ 1
18
x ydydx = ∫ 18 x 2
2 1
2
dx = 1 x3
36 3 = 108
1
0 0 0 0 0
2.5 2 2.5 2 2.5
y2
b) P( X < 2.5) = ∫∫
0 0
1
18
x 2 ydydx = ∫
0
1
18
x2 2
0
dx = 1 x3
9 3
0
= 0.5787
3 2 3 2 3
y2
c) P(1 < Y < 2.5) = ∫ ∫ 1
18
x ydydx = ∫ 18 x 2
2 1
2
dx = 12
1 x3
3 = 3
4
0 1 0 1 0
Image 37: d)
3 1.5 3 1.5 3
y2
P( X > 2,1 < Y < 1.5) = ∫ ∫ 1
18
x 2 ydydx = ∫ 18 x 2
1
2
dx = 144
5 x3
3
2 1 2 1 2
= 95
432 = 0.2199
3 2 3 3
e) E ( X ) = ∫ ∫ 18 x 3 ydydx = ∫ 18 x 3 2dx =
1 1 1 x4
9 4 = 9
4
0 0 0 0
3 2 3 3
f) E (Y ) = ∫ ∫ 18 x 2 y 2 dydx = ∫ 18 x 2 8 dx =
1 1
3
4 x3
27 3 = 4
3
0 0 0 0
5-107. The region x2 + y 2 ≤ 1 and 0 < z < 4 is a cylinder of radius 1 ( and base area π ) and height 4. Therefore,
1
the volume of the cylinder is 4 π and f XYZ ( x, y, z) = for x2 + y 2 ≤ 1 and 0 < z < 4.
4π
a) The region X 2 + Y 2 ≤ 0.5 is a cylinder of radius 0.5 and height 4. Therefore,
2 2 4 ( 0.5π )
P( X + Y ≤ 0.5) = 4π = 1/ 2 .
b) The region X 2 + Y 2 ≤ 0.5 and 0 < z < 2 is a cylinder of radius 0.5 and height 2. Therefore,
2 2 2 ( 0.5π )
P( X + Y ≤ 0.5, Z < 2) = = 1/ 4 4π
f ( x, y,1)
c) f XY 1 ( x, y ) = XYZ and f Z ( z ) = ∫∫ 41 dydx = 1 / 4
π
f Z (1) x 2 + y 2 ≤1
1 / 4π
for 0 < z < 4. Then, f XY 1 ( x, y ) = = 1
π
for x 2 + y 2 ≤ 1 .
1/ 4
4 1− x 2 4
d) f X ( x) = ∫ ∫ 1
4π
dydz = ∫ 21 1 − x 2 dz = π 1 − x 2
π
2
for -1 < x < 1
0 − 1− x 2 0
5-111. Let X, Y, and Z denote the number of problems that result in functional, minor, and no defects,
respectively.
a) P( X = 2, Y = 5) = P( X = 2, Y = 5, Z = 3) = 10!
2!5!3!
0.2 2 0.5 5 0.3 3 = 0.085
b) Z is binomial with n = 10 and p = 0.3.
c) E(Z) = 10(0.3) = 3.
5-115. Let X denote the average time to locate 10 parts. Then, E( X ) =45 and σX = 30
10
a) P( X > 60) = P ( Z > 60 − 45
30 / 10
) = P( Z > 1.58) = 0.057
b) Let Y denote the total time to locate 10 parts. Then, Y > 600 if and only if X > 60. Therefore, the
answer is the same as part a.
5-119 Let T denote the total thickness. Then, T = X1 + X2 and
a.) E(T) = 0.5+1=1.5 mm
V(T)=V(X1) +V(X2) + 2Cov(X1X2)=0.01+0.04+2(0.14)=0.078mm2
where Cov(XY)=ρσXσY=0.7(0.1)(0.2)=0.014
Image 38: 1 − 1.5
b.) P(T < 1) = P Z < = P( Z < −6.41) ≅ 0
0.078
c.) Let P denote the total thickness. Then, P = 2X1 +3 X2 and
E(P) =2(0.5)+3(1)=4 mm
V(P)=4V(X1) +9V(X2) + 2(2)(3)Cov(X1X2)=4(0.01)+9(0.04)+2(2)(3)(0.014)=0.568mm2
where Cov(XY)=ρσXσY=0.7(0.1)(0.2)=0.014
5-121 Let X and Y denote the percentage returns for security one and two respectively.
If ½ of the total dollars is invested in each then ½X+ ½Y is the percentage return.
E(½X+ ½Y)=5 million
V(½X+ ½Y)=1/4 V(X)+1/4V(Y)-2(1/2)(1/2)Cov(X,Y)
where Cov(XY)=ρσXσY=-0.5(2)(4)=-4
V(½X+ ½Y)=1/4(4)+1/4(6)-2=3
Also, E(X)=5 and V(X) = 4. Therefore, the strategy that splits between the securities has
a lower standard deviation of percentage return.
Image 39: Chapter 6 Selected Problem Solutions
Sections 6-1and 6-2
6-1. Sample average:
n
∑x
i =1
i
592.035
x= = = 74.0044 mm
n 8
Sample variance:
8
∑xi =1
i = 592.035
8
∑xi =1
2
i = 43813.18031
2
n
∑ xi
n
xi − i =1 (592.035)2
∑ 2
n
43813.18031 −
8
s 2 = i =1 =
n −1 8 −1
0.0001569
= = 0.000022414 (mm) 2
7
Sample standard deviation:
s = 0.000022414 = 0.00473 mm
The sample standard deviation could also be found using
n
2
∑ (x i − x ) 8
∑ (x i − x )
i =1 2
s= where = 0.0001569
n −1 i =1
Dot Diagram:
.. ...: .
-------+---------+---------+---------+---------+---------diameter
73.9920 74.0000 74.0080 74.0160 74.0240 74.0320
There appears to be a possible outlier in the data set.
n
∑x
i =1
i
5747
6-11. a) x= = = 7.184
n 8
Image 40: 2
n
∑ xi
n
2
∑ xi −
i =1
412.853 −
(57.47)2
n 8 0.003
b) s2 = i =1 = = = 0.000427
n −1 8 −1 7
s = 0.000427 = 0.02066
c) Examples: repeatability of the test equipment, time lag between samples, during which the pH of the
solution could change, and operator skill in drawing the sample or using the instrument.
6-13. a) x = 65.85
s = 12.16
b) Dot Diagram
: :
. . . . .. .: .: . .:..: .. :: .... ..
-+---------+---------+---------+---------+---------+-----temp
30 40 50 60 70 80
c) Removing the smallest observation (31), the sample mean and standard deviation become
x = 66.86
s = 10.74
Section 6-3
6-15 a.) Stem-and-leaf display for Problem 6-15 cycles: unit = 100 1|2 represents 1200
1 0T|3
1 0F|
5 0S|7777
10 0o|88899
22 1|000000011111
33 1T|22222223333
(15) 1F|444445555555555
22 1S|66667777777
11 1o|888899
5 2|011
2 2T|22
b) No, only 5 out of 70 coupons survived beyond 2000 cycles.
6-19. Descriptive Statistics
Variable N Median Q1 Q3
cycles 70 1436.5 1097.8 1735.0
6-25 Stem-and-leaf display for Problem 6-25. Yard: unit = 1.0
Note: Minitab has dropped the value to the right of the decimal to make this display.
4 23|2334
7 23o|677
15 24|00112444
19 24o|5578
32 25|0111122334444
45 25o|5555556677899
(15) 26|000011123334444
40 26o|566677888
31 27|0000112222233333444
12 27o|66788999
4 28|003
Image 41: 1 28o|5
n 100
∑ xii =1
∑x
i =1
i
26070
Sample Mean x= = = = 260.7 yards
n 100 100
Sample Standard Deviation
100 100
∑ xi = 26070
i =1
and ∑x
i =1
2
i =6813256
2
n
∑ xi
∑ xi − i =1 n 6813256 − (26070) 16807
n 2
2
s 2 = i =1 = 100 =
n −1 100 − 1 99
2
= 169.7677 yards
and
s = 169.7677 = 13.03 yards
Sample Median
Variable N Median
yards 100 261.15
Section 6-5
6-43. Descriptive Statistics
Variable N Mean Median Tr Mean StDev SE Mean
PMC 20 4.000 4.100 4.044 0.931 0.208
Variable Min Max Q1 Q3
PMC 2.000 5.200 3.150 4.800
a) Sample Mean: 4
b) Sample Variance: 0.867
Sample Standard Deviation: 0.931
c)
5
4
PMC
3
2
6-47.
Descriptive Statistics
Variable N Mean Median Tr Mean StDev SE Mean
temperat 24 48.125 49.000 48.182 2.692 0.549
Variable Min Max Q1 Q3
Image 42: temperat 43.000 52.000 46.000 50.000
a) Sample Mean: 48.125
Sample Median: 49
b) Sample Variance: 7.246
Sample Standard Deviation: 2.692
c)
52
51
50
49
temperatur
48
47
46
45
44
43
The data appear to be slightly skewed.
Supplemental
6-75 a) Sample 1 Range = 4
Sample 2 Range = 4
Yes, the two appear to exhibit the same variability
b) Sample 1 s = 1.604
Sample 2 s = 1.852
No, sample 2 has a larger standard deviation.
c) The sample range is a relatively crude measure of the sample variability as compared to the sample
standard deviation since the standard deviation uses the information from every data point in the sample
whereas the range uses the information contained in only two data points - the minimum and maximum.
6-79 a)Stem-and-leaf display for Problem 6-79: unit = 1 1|2 represents 12
1 0T|3
8 0F|4444555
18 0S|6666777777
(7) 0o|8888999
15 1|111
12 1T|22233
7 1F|45
5 1S|77
3 1o|899
b) Sample Average = 9.325
Sample Standard Deviation = 4.4858
Image 43: c)
20
15
springs
10
5
Index 10 20 30 40
The time series plot indicates there was an increase in the average number of nonconforming springs
made during the 40 days. In particular, the increase occurs during the last 10 days.
![Image 44: Chapter 7 Selected Problem Solutions
Section 7-2
7-7. ˆ
E ( Θ1 ) = θ No bias ˆ ˆ
V (Θ1 ) = 12 = MSE (Θ1 )
ˆ
E (Θ ) = θ No bias ˆ ˆ
V (Θ ) = 10 = MSE (Θ )
2 2 2
ˆ
E (Θ 3 ) ≠ θ Bias ˆ
MSE (Θ 3 ) = 6 [not that this includes (bias2)]
To compare the three estimators, calculate the relative efficiencies:
ˆ
MSE (Θ1 ) 12
= = 1.2 , since rel. eff. > 1 use ˆ
Θ2 as the estimator for θ
ˆ
MSE (Θ 2 ) 10
ˆ
MSE (Θ1 ) 12
= = 2, since rel. eff. > 1 use ˆ
Θ3 as the estimator for θ
ˆ
MSE (Θ 3 ) 6
ˆ
MSE (Θ 2 ) 10
= = 1.8 , since rel. eff. > 1 use ˆ
Θ3 as the estimator for θ
ˆ
MSE (Θ 3 ) 6
Conclusion:
ˆ
Θ3 is the most efficient estimator with bias, but it is biased. ˆ
Θ2 is the best “unbiased” estimator.
7-11
a.) The average of the 26 observations provided can be used as an estimator of the mean pull
force since we know it is unbiased. This value is 75.427 pounds.
b.) The median of the sample can be used as an estimate of the point that divides the population
into a “weak” and “strong” half. This estimate is 75.1 pounds.
c.) Our estimate of the population variance is the sample variance or 2.214 square pounds.
Similarly, our estimate of the population standard deviation is the sample standard deviation
or 1.488 pounds.
d.) The standard error of the mean pull force, estimated from the data provided is 0.292 pounds.
This value is the standard deviation, not of the pull force, but of the mean pull force of the
population.
e.) Only one connector in the sample has a pull force measurement under 73 pounds. Our point
estimate for the proportion requested is then 1/26 = 0.0385
7-13 a.) To see if the estimator is unbiased, find:
1 1
E[( X min + X max ) / 2] = [ E ( X min ) + E ( X max )] = ( µ + µ ) = µ
2 2
since the expected value of any observation arising from a normally distributed process is equal
to the mean. So this is an unbiased estimator of the mean.
b.) The standard error of this estimator is:
1 1 1
V [( X min + X max ) / 2 ] = [V ( X min ) + V ( X max ) + COV ( X min , X max )] = (σ 2 + σ 2 ) = σ
2 2 2
c.) This estimator is not better than the sample mean because it has larger standard error for n > 2.
This is due to the fact that this estimator uses only two observations from the available sample.
The sample mean uses all the information available to compute the estimate.
](
Image 45: 7-17
a) E(µ ) = E(αX1 + (1 − α ) X 2 ) = αE( X1) + (1 − α )E( X 2 ) = αµ + (1 − α )µ = µ
ˆ
b)
s.e.( µ ) = V (αX 1 + (1 − α ) X 2 ) = α 2 V ( X 1 ) + (1 − α ) 2 V ( X 2 )
ˆ
2 2 2 2
σ1 σ σ σ
= α2 + (1 − α ) 2 2 = α 2 1 + (1 − α ) 2 a 1
n1 n2 n1 n2
α 2 n 2 + (1 − α ) 2 an 1
=σ1
n1 n 2
c) The value of alpha that minimizes the standard error is:
an1
α=
n2 + an1
d) With a = 4 and n1=2n2, the value of alpha to choose is 8/9. The arbitrary value of α=0.5 is too
small and will result in a larger standard error. With α=8/9 the standard error is
(8 / 9 ) 2 n 2 + (1 / 9 ) 2 8 n 2 0.667σ 1
s.e.( µ ) = σ 1
ˆ 2
=
2n 2 n2
If α=0.05 the standard error is
( 0 . 5) 2 n 2 + ( 0 . 5) 2 8 n 2 1.0607 σ 1
s.e.( µ ) = σ 1
ˆ 2
=
2n 2 n2
Section 7-5
7-33. P (1 . 009 ≤ X ≤ 1 . 012 ) = P ( 1 . 009 − 1 . 01
0 . 003 / 9
≤ X −µ
σ / n
≤ 1 . 012 − 1 . 01
0 . 003 / 9
)
= P(−1 ≤ Z ≤ 2) = P( Z ≤ 2) − P( Z ≤ −1)
= 0.9772 − 0.1587 = 0.8385
σ 3.5
7-35. µ X = 75.5 psi , σ X = = = 1.429
n 6
(
P( X ≥ 75.75) = P σX/− µn ≥ 75.1.429 .5
75 − 75
)
= P( Z ≥ 0.175) = 1 − P( Z ≤ 1.75)
= 1 − 0.56945 = 0.43055
7-39 σ 2 = 25
Image 46: σ
σX =
n
2 2
5
n= σ
σ = = 11.11
X 1.5
n≅12
7-41 n = 36
a + b (3 + 1)
µX = = =2
2 2
(b − a + 1) 2 − 1 (3 − 1 + 1) 2 − 1
σX = = = 8 = 2
12 12 12 3
2/3 2/3
µ X = 2, σ X = =
36 6
X −µ
z=
σ/ n
Using the central limit theorem:
P(2.1 < X < 2.5) = P 2.1−32 < Z <
2/
2.5 − 2
2/3
6 6
= P(0.7348 < Z < 3.6742)
= P( Z < 3.6742) − P( Z < 0.7348)
= 1 − 0.7688 = 0.2312
7-43.
n1 = 16 n2 = 9 X 1 − X 2 ~ N ( µ X1 − µ X 2 , σ 2 + σ 2 )
X X 1 2
µ 1 = 75 µ 2 = 70 2
σ1 σ 2
σ1 = 8 σ 2 = 12 ~ N ( µ1 − µ 2 , + )2
n1 n2
82 12 2
~ N (75 − 70, + )
16 9
~ N (5,20)
a) P( X 1 − X 2 > 4)
P( Z > 4 − 5 ) = P( Z > −0.2236) = 1 − P( Z ≤ −0.2236)
20
= 1 − 0.4115 = 0.5885
Image 47: b) P(3.5 ≤ X 1 − X 2 ≤ 5.5)
P( 3.5205 ≤ Z ≤ 5.5205 ) = P( Z ≤ 0.1118) − P( Z ≤ −0.3354)
− −
= 0.5445 − 0.3686 = 0.1759
Supplemental Exercises
7-49. 1.52 22
X 1 − X 2 ~ N (100 − 105, + ) ~ N (−5,0.2233)
25 25
Image 48: Chapter 8 Selected Problem Solutions
Section 8-2
8-1 a.) The confidence level for x − 2.14σ / n ≤ µ ≤ x + 2.14σ / n is determined by the
by the value of z0 which is 2.14. From Table II, we find Φ(2.14) = P(Z<2.14) = 0.9793 and the
confidence level is 97.93%.
b.) The confidence level for x − 2.49σ / n ≤ µ ≤ x + 2.49σ / n is determined by the
by the value of z0 which is 2.14. From Table II, we find Φ(2.49) = P(Z<2.49) = 0.9936 and the
confidence level is 99.36%.
c.) The confidence level for x − 1.85σ / n ≤ µ ≤ x + 1.85σ / n is determined by the
by the value of z0 which is 2.14. From Table II, we find Φ(1.85) = P(Z<1.85) = 0.9678 and the
confidence level is 96.78%.
8-7 a.) The 99% CI on the mean calcium concentration would be longer.
b). No, that is not the correct interpretation of a confidence interval. The probability that µ is between
0.49 and 0.82 is either 0 or 1.
c). Yes, this is the correct interpretation of a confidence interval. The upper and lower limits of the
confidence limits are random variables.
8-13 a) 95% two sided CI on the mean compressive strength
zα/2 = z0.025 = 1.96, and x = 3250, σ2 = 1000, n=12
σ σ
x − z0.025 ≤ µ ≤ x + z0.025
n n
31.62 31.62
3250 − 1.96 ≤ µ ≤ 3250 + 1.96
12 12
3232.11 ≤ µ ≤ 3267.89
b.) 99% Two-sided CI on the true mean compressive strength
zα/2 = z0.005 = 2.58
σ σ
x − z0.005 ≤ µ ≤ x + z0.005
n n
3162
. 3162
.
3250 − 2.58 ≤ µ ≤ 3250 + 2.58
12 12
3226.5 ≤ µ ≤ 3273.5
8-15 Set the width to 6 hours with σ = 25, z0.025 = 1.96 solve for n.
1/2 width = (1.96)(25) / n = 3
49 = 3 n
2
49
n = = 266.78
3
Therefore, n=267.
Image 49: Section 8-3
8-25 a.) The data appear to be normally distributed based on examination of the normal probability plot below.
Therefore, there is evidence to support that the level of polyunsaturated fatty acid is normally distributed.
N o rm a l P ro b a b ility P lo t fo r 8 -2 5
M L E stim a te s - 9 5 % C I
99
95
90
80
70
Percent
60
50
40
30
20
10
5
1
16 17 18
D a ta
b.) 99% CI on the mean level of polyunsaturated fatty acid.
For α = 0.01, tα/2,n-1 = t0.005,5 = 4.032
s s
x − t 0.005,5 ≤ µ ≤ x + t 0.005,5
n n
0.319 0.319
16.98 − 4.032 ≤ µ ≤ 16.98 + 4.032
6 6
16.455 ≤ µ ≤ 17.505
8-29 95% lower bound confidence for the mean wall thickness
given x = 4.05 s = 0.08 n = 25
tα,n-1 = t0.05,24 = 1.711
s
x − t 0.05, 24
≤µ
n
0.08
4.05 − 1.711 ≤µ
25
4.023 ≤ µ
It may be assumed that the mean wall thickness will most likely be greater than 4.023 mm.
8-31 x = 1.10 s = 0.015 n = 25
Image 50: 95% CI on the mean volume of syrup dispensed
For α = 0.05 and n = 25, tα/2,n-1 = t0.025,24 = 2.064
s s
x − t 0.025, 24
≤ µ ≤ x + t 0.025, 24
n n
0.015 0.015
1.10 − 2.064 ≤ µ ≤ 1.10 + 2.064
25 25
1.093 ≤ µ ≤ 1.106
Section 8-4
8-35 99% lower confidence bound for σ2
2 2
For α = 0.01 and n = 15, χ α ,n −1 = χ 0.01,14 = 29.14
14(0.008) 2
<σ2
29.14
0.00003075 < σ2
8-37 95% lower confidence bound for σ2 given n = 16, s2 = (3645.94)2
For α = 0.05 and n = 16, χα,n−1 = χ2.05,15 = 25
2
0
15(3645.94) 2
<σ2
25
7,975,727.09 < σ2
8-39 95% confidence interval for σ: given n = 51, s = 0.37
First find the confidence interval for σ2 :
For α = 0.05 and n = 51, χ2 2 , n−1 = χ2.025,50 = 71.42 and χ1− α / 2 ,n −1 = χ2.975,50 = 32.36
α/ 0
2
0
50(0.37) 2 2 50(0.37) 2
≤σ ≤
(71.42) 2 (32.36) 2
0.096 ≤ σ2 ≤ 0.2115
Taking the square root of the endpoints of this interval we obtain,
0.31 < σ < 0.46
8-41 90% lower confidence bound on σ (the standard deviation of the sugar content)
given n = 10, s2 = 23.04
2 2
For α = 0.1 and n = 10, χ α ,n −1 = χ 0.1,9 = 19.02
9(23.04)
≤σ2
14.68
14.13 ≤ σ2
Take the square root of the endpoints of this interval to find the confidence interval for σ:
3.8 ≤ σ
Image 51: Section 8-7
8-63 99% tolerance interval on the polyunsaturated fatty acid in this type of margarine that has a confidence level
of 95%
x = 16.98 s = 0.319 n=6 and k = 5.775
x − ks, x + ks
16.98 − 5.775(0.319 ), 16.98 + 5.775(0.319 )
(15.14, 18.82)
The 99% tolerance interval is much wider than the 99% confidence interval on the population mean
(16.46 ≤ µ ≤ 17.51).
8-67 90% lower tolerance bound on bottle wall thickness that has confidence level 90%.
given x = 4.05 s = 0.08 n = 25 and k = 1.702
x − ks
4.05 − 1.702(0.08)
3.91
The 90% tolarance bound is (3.91, ∞)
The lower tolerance bound is of interest if we want to make sure the wall thickness is at least a certain value
so that the bottle will not break.
8-69 95% tolerance interval on the syrup volume that has 90% confidence level
x = 1.10 s = 0.015 n = 25 and k=2.474
x − ks, x + ks
1.10 − 2.474(0.015), 1.10 + 2.474(0.015)
(1.06, 1.14)
Supplemental Exercises
8-75 With σ = 8, the 95% confidence interval on the mean has length of at most 5; the error is then E = 2.5.
2 2
z0.025 2 1.96
a) n = 8 = 64 = 39.34 = 40
2.5 2.5
2 2
z0.025 2 1.96
b) n = 6 = 36 = 22.13 = 23
2.5 2.5
As the standard deviation decreases, with all other values held constant, the sample size necessary to
maintain the acceptable level of confidence and the length of the interval, decreases.
Image 52: 8-79 Normal probability plot for the coefficient of restitution
Normal Probability Plot for 8-79
ML Estimates - 95% CI
99
95
90
80
70
Percent
60
50
40
30
20
10
5
1
0.59 0.60 0.61 0.62 0.63 0.64 0.65 0.66
Data
b.) 99% CI on the true mean coefficient of restitution
x = 0.624, s = 0.013, n = 40 ta/2, n-1 = t0.005, 39 = 2.7079
s s
x − t 0.005,39 ≤ µ ≤ x + t 0.005,39
n n
0.013 0.013
0.624 − 2.7079 ≤ µ ≤ 0.624 + 2.7079
40 40
0.618 ≤ µ ≤ 0.630
b.) 99% prediction interval on the coefficient of restitution for the next baseball that will be tested.
1 1
x − t 0.005,39 s 1 + ≤ x n +1 ≤ x + t 0.005,39 s 1 +
n n
1 1
0.624 − 2.7079(0.013) 1 + ≤ x n +1 ≤ 0.624 + 2.7079(0.013) 1 +
40 40
0.588 ≤ x n +1 ≤ 0.660
c.) 99% tolerance interval on the coefficient of restitution with a 95% level of confidence
( x − ks, x + ks)
(0.624 − 3.213(0.013), 0.624 + 3.213(0.013))
(0.583, 0.665)
e.)The confidence interval in part (b) describes the confidence interval on the population mean and we may
interpret this to mean that 99% of such intervals will cover the population mean. The prediction interval
tells us that within that within a 99% probability that the next baseball will have a coefficient of restitution
between 0.588 and 0.660. The tolerance interval captures 99% of the values of the normal distribution
with a 95% level of confidence.
Image 54: Chapter 9 Selected Problems Solutions
Section 9-1
9-1 a) H 0 : µ = 25, H1 : µ ≠ 25 Yes, because the hypothesis is stated in terms of the parameter of
interest, inequality is in the alternative hypothesis, and the value in the null and alternative
hypotheses matches.
b) H 0 : σ > 10, H1 : σ = 10 No, because the inequality is in the null hypothesis.
c) H 0 : x = 50, H1 : x ≠ 50 No, because the hypothesis is stated in terms of the statistic rather
than the parameter.
d) H 0 : p = 0.1, H1 : p = 0.3 No, the values in the hull and alternative hypotheses do not match and
both of the hypotheses are equality statements.
e) H 0 : s = 30, H1 : s > 30 No, because the hypothesis is stated in terms of the statistic rather than the
parameter.
X−µ 115 − 12
.
9-3 a) α = P( X ≤ 11.5 | µ = 12) = P ≤ = P(Z ≤ −4) = 1 − P(Z ≤ 4)
σ / n 0.5 / 16
= 1 − 1 = 0.
The probability of rejecting the null, when the null is true, is approximately 0 with a sample size of 16.
X − µ 115 − 1125
. .
b) β = P( X > 11.5 | µ =11.25) = P > = P(Z > 2) = 1 − P(Z ≤ 2)
σ/ n 0.5 / 16
= 1− 0.97725 = 0.02275.
The probability of accepting the null hypothesis when it is false is 0.02275.
190 − 175
9-9 a) z= = 2.37 , Note that z is large, therefore reject the null hypothesis and conclude that the
20 / 10
mean foam height is greater than 175 mm.
b) P( X > 190 when µ = 175)
X − 175 190 − 175
= P >
20 / 10 20 / 10
= P(Z > 2.37) = 1 − P(Z ≤ 2.37)
= 1 − 0.99111
= 0.00889.
The probability that a value of at least 190 mm would be observed (if the true mean height is 175 mm) is
only 0.00889. Thus, the sample value of x = 190 mm would be an unusual result.
9-17. The problem statement implies H0: p = 0.6, H1: p > 0.6 and defines an acceptance region as
315
p≤
ˆ = 0.63 and rejection region as p > 0.63
ˆ
500
ˆ ( )
a) α = P P ≥ 0 . 63 | p = 0 . 6 = P Z ≥ 0 . 63 − 0 . 6
0 .6 ( 0 .4 )
.
500
= P (Z ≥ 1 . 37 ) = 1 − P ( Z < 1 . 37 ) = 0 . 08535
b) β = P( P ≤ 0.63 when p = 0.75) = P(Z ≤ −6.196) ≅ 0.
![Image 55: Section 9-2
9-21. a) 1) The parameter of interest is the true mean yield, µ.
2) H0 : µ = 90
3) H1 : µ ≠ 90
4) α = 0.05
x−µ
5) z0 =
σ/ n
6) Reject H0 if z0 < −z α/2 where −z0.025 = −1.96 or z0 > zα/2 where z0.025 = 1.96
7) x = 90.48 , σ = 3
90.48 − 90
z0 = = 0.36
3/ 5
8) Since −1.96 < 0.36 < 1.96 do not reject H0 and conclude the yield is not significantly different from
90% at α = 0.05.
b) P-value = 2[1 − Φ(0.36)] = 2[1 − 0.64058] = 0.71884
(
c) n = z α / 2 + z β
)σ
2 2
=
(z 0 .025 + z 0 .05 )2 3 2 =
(1 . 96 + 1 . 65 )2 9 = 4 . 67
δ 2
(85 − 90 )2 (− 5 )2
n ≅ 5.
90 − 92 90 − 92
d) β = Φ z0.025 + − Φ − z0.025 +
3/ 5 3/ 5
= Φ(1.96 + −1.491) − Φ(−1.96 + −1.491)
= Φ(0.47) − Φ(−3.45)
= Φ(0.47) − (1 − Φ(3.45))
= 0.68082 − ( 1 − 0.99972)
= 0.68054.
e) For α = 0.05, zα/2 = z0.025 = 1.96
σ σ
x − z0.025 ≤ µ ≤ x + z0.025
n n
3 3
90.48 − 1.96 ≤ µ ≤ 90.48 + 196
.
5 5
87.85 ≤ µ ≤ 93.11
With 95% confidence, we believe the true mean yield of the chemical process is between 87.85% and
93.11%.
9-25. a) 1) The parameter of interest is the true mean tensile strength, µ.
2) H0 : µ = 3500
3) H1 : µ ≠ 3500
4) α = 0.01
x−µ
5) z0 =
σ/ n
6) Reject H0 if z0 < −zα/2 where −z0.005 = −2.58 or z0 > zα/2 where z0.005 = 2.58
7) x = 3250 , σ = 60
3250 − 3500
z0 = = −14.43
60 / 12
8) Since −14.43 < −2.58, reject the null hypothesis and conclude the true mean compressive strength is
significantly different from 3500 at α = 0.01.
b) Smallest level of significance = P-value = 2[1 − Φ (14.43) ]= 2[1 − 1] = 0
](
Image 56: The smallest level of significance at which we are willing to reject the null hypothesis is 0.
c) zα/2 = z0.025 = 1.96
σ σ
x − z0.025 ≤ µ ≤ x + z0.025
n n
3162
. 3162
.
3250 − 1.96 ≤ µ ≤ 3250 + 196
.
12 12
3232.11 ≤ µ ≤ 3267.89
With 95% confidence, we believe the true mean tensile strength is between 3232.11 psi and 3267.89
psi. We can test the hypotheses that the true mean strength is not equal to 3500 by noting that the value is
not within the confidence interval.
9-27 a) 1) The parameter of interest is the true mean speed, µ.
2) H0 : µ = 100
3) H1 : µ < 100
4) α = 0.05
x−µ
5) z0 =
σ/ n
6) Reject H0 if z0 < −zα where −z0.05 = −1.65
7) x = 102.2 , σ = 4
102.2 − 100
z0 = = 1.55
4/ 8
8) Since 1.55> −1.65, do not reject the null hypothesis and conclude the there is insufficient evidence to
conclude that the true speed strength is less than 100 at α = 0.05.
(95 − 100) 8
b) β = Φ − z0.05 −
= Φ(-1.65 - −3.54) = Φ(1.89) = 1
4
Power = 1-β = 1-0.97062 = 0.02938
(z α + zβ ) σ 2
2
(z 0.05 + z 0.15 )2 σ 2 (1.65 + 1.03) 2 (4) 2
c) n = = = = 0.927,
δ2 (95 − 100) 2 (5) 2
n≅1
σ
d) x − z0.05 ≤µ
n
4
102.2 − 1.65 ≤µ
8
99.866 ≤ µ
Since the lower limit of the CI is just slightly below 100, we are confident that the mean speed is
not less than 100 m/s.
9-29 a) 1) The parameter of interest is the true average battery life, µ.
2) H0 : µ = 4
3) H1 : µ > 4
4) α = 0.05
x−µ
5) z0 =
σ/ n
6) Reject H0 if z0 > zα where z0.05 = 1.65
7) x = 4.05 , σ = 0.2
Image 57: 4.05 − 4
z0 = = 1.77
0.2 / 50
8) Since 1.77>1.65, reject the null hypothesis and conclude that the there is sufficient evidence to
conclude that the true average battery life exceeds 4 hours at α = 0.05.
(4.5 − 4) 50
b) β = Φ z0.05 −
= Φ(1.65 – 17.68) = Φ(-16.03) = 0
0.2
Power = 1-β = 1-0 = 1
c) n =
(z α + z β ) σ 2 (z0.05 + z0.1 )2 σ 2 (1.65 + 1.29) 2 (0.2) 2
2
= = = 34.7,
δ2 (4.5 − 4) 2 (0.5) 2
n ≅ 35
σ
d) x − z0.05 ≤µ
n
0.2
4.05 − 1.65 ≤µ
50
4.003 ≤ µ
Since the lower limit of the CI is just slightly above 4, we conclude that average life is greater than 4
hours at α=0.05.
Section 9-3
9-31 a. 1) The parameter of interest is the true mean female body temperature, µ.
2) H0 : µ = 98.6
3) H1 : µ ≠ 98.6
4) α = 0.05
x−µ
5) t0 =
s/ n
6) Reject H0 if |t0| > tα/2,n-1 where tα/2,n-1 = 2.064
7) x = 98.264 , s = 0.4821 n=25
98 . 264 − 98 . 6
t0 = = − 3 . 48
0 . 4821 / 25
8) Since 3.48 > 2.064, reject the null hypothesis and conclude that the there is sufficient evidence to
conclude that the true mean female body temperature is not equal to 98.6 °F at α = 0.05.
P-value = 2 0.001 = 0.002
δ | µ − µ 0 | | 98 − 98.6 |
b) d = = = = 1.24
σ σ 0.4821
Using the OC curve, Chart VI e) for α = 0.05, d = 1.24, and n = 25, we get β ≅ 0 and
power of 1−0 ≅ 1.
δ | µ − µ0 | | 98.2 − 98.6 |
c) d = = = = 0.83
σ σ 0.4821
Using the OC curve, Chart VI g) for α = 0.05, d = 0.83, and β ≅ 0.1 (Power=0.9),
n + 1 20 + 1
n = 20 . Therefore, n= = = 10.5 and n=11.
2 2
d) 95% two sided confidence interval
Image 58: s s
x − t0.025, 24 ≤ µ ≤ x + t0.025, 24
n n
0 . 4821 0 . 4821
98 . 264 − 2 .064 ≤ µ ≤ 98 .264 + 2 . 064
25 25
98 . 065 ≤ µ ≤ 98 .463
We can conclude that the mean female body temperature is not equal to 98.6 since the value is not included
inside the confidence interval.
e)
Normal Probability Plot for 9-31
ML Estimates - 95% CI
99
95
90
80
70
Percent
60
50
40
30
20
10
5
1
97 98 99
Data
Data appear to be normally distributed.
9-37. a.) In order to use t statistics in hypothesis testing, we need to assume that the underlying distribution
is normal.
1) The parameter of interest is the true mean coefficient of restitution, µ.
2) H0 : µ = 0.635
3) H1 : µ > 0.635
4) α = 0.05
x−µ
5) t0 =
s/ n
6) Reject H0 if t0 > tα,n-1 where t0.05,39 = 1.685
7) x = 0.624 s = 0.013 n = 40
0.624 − 0.635
t0 = = −5.35
0.013 / 40
8) Since –5.25 < 1.685, do not reject the null hypothesis and conclude that there is not sufficient evidence to
indicate that the true mean coefficient of restitution is greater than 0.635 at α = 0.05.
b.)The P-value > 0.4, based on Table IV. Minitab gives P-value = 1.
δ | µ − µ 0 | | 0.64 − 0.635 |
c) d = = = = 0.38
σ σ 0.013
Using the OC curve, Chart VI g) for α = 0.05, d = 0.38, and n = 40, we get β ≅ 0.25 and
power of 1−0.25 = 0.75.
δ | µ − µ 0 | | 0.638 − 0.635 |
d) d = = = = 0.23
σ σ 0.013
Using the OC curve, Chart VI g) for α = 0.05, d = 0.23, and β ≅ 0.25 (Power=0.75),
Image 59: n + 1 75 + 1
n = 75 . Therefore, n= = = 38 and n=38.
2 2
9-41 a) In order to use t statistics in hypothesis testing, we need to assume that the underlying distribution
is normal.
1) The parameter of interest is the true mean concentration of suspended solids, µ.
2) H0 : µ = 55
3) H1 : µ ≠ 55
4) α = 0.05
x−µ
5) t0 =
s/ n
6) Reject H0 if |t0 | > tα/2,n-1 where t0.025,59 =2.000
7) x = 59.87 s = 12.50 n = 60
59.87 − 55
t0 = = 3.018
12.50 / 60
8) Since 3.018 > 2.000, reject the null hypothesis and conclude that there is sufficient evidence to indicate that
the true mean concentration of suspended solids is not equal to 55 at α = 0.05.
b) From table IV the t0 value is found between the values of 0.001 and 0.0025 with 59 degrees of
freedom, so 20.001<P-value = 2 0.0025 Therefore, 0.002< P-value<0.005.
Minitab gives a p-value of 0.0038
50 − 55
c) d= = 0.4 , n=60 so, from the OC Chart VI e) for α = 0.05, d= 0.4 and n=60 we find that
12.50
β≅0.2. Therefore, the power = 1-0.2 = 0.8.
d) From the same OC chart, and for the specified power, we would need approximately 38 observations.
50 − 55
d= = 0.4 Using the OC Chart VI e) for α = 0.05, d = 0.4, and β ≅ 0.10 (Power=0.90),
12.50
n + 1 75 + 1
n = 75 . Therefore, n= = = 38 and n=38.
2 2
Section 9-4
9-43 a) In order to use the χ2 statistic in hypothesis testing and confidence interval construction, we need to
assume that the underlying distribution is normal.
1) The parameter of interest is the true standard deviation of the diameter, σ. However, the answer can
be found by performing a hypothesis test on σ2.
2) H0 : σ2 = 0.0001
3) H1 : σ2 > 0.0001
4) α = 0.01
( n − 1)s2
5) χ2 =
0
σ2
6) Reject H0 if χ2 > χα ,n −1 where χ2.01,14 = 29.14
0
2
0
7) n = 15, s2 = 0.008
( n − 1)s2
14(0.008)2
χ2 =
0 2
= = 8.96
σ 0.0001
8) Since 8.96 < 29.14 do not reject H0 and conclude there is insufficient evidence to indicate the true
standard deviation of the diameter exceeds 0.01 at α = 0.01.
b) P-value = P(χ2 > 8.96) for 14 degrees of freedom: 0.5 < P-value < 0.9
Image 60: σ 0.0125
c) λ= = = 1.25 power = 0.8, β=0.2
σ0 0.01
using chart VIk, the required sample size is 50
9-47. a) In order to use χ2 statistic in hypothesis testing and confidence interval construction, we need to assume
that the underlying distribution is normal.
1) The parameter of interest is the true standard deviation of titanium percentage, σ. However, the
answer can be found by performing a hypothesis test on σ2.
2) H0 : σ2 = (0.25)2
3) H1 : σ2 ≠ (0.25)2
4) α = 0.01
( n − 1)s2
5) χ2 =
0
σ2
6) Reject H0 if χ2 < χ1− α / 2 ,n −1 where χ2.995,50 = 27.99 or χ2 > χα ,2,n −1 where χ2.005,50 = 79.49
0
2
0 0
2
0
7) n = 51, s = 0.37
( n − 1)s2 50(0.37) 2
χ2 =
0 2
= = 109.52
σ (0.25) 2
8) Since 109.52 > 79.49 we would reject H0 and conclude there is sufficient evidence to indicate the true
standard deviation of titanium percentage is significantly different from 0.25 at α = 0.01.
b) 95% confidence interval for σ:
First find the confidence interval for σ2 :
For α = 0.05 and n = 51, χ2 2 , n−1 = χ2.025,50 = 71.42 and χ1− α / 2 ,n −1 = χ2.975,50 = 32.36
α/ 0
2
0
50(0.37) 2 50(0.37) 2
≤σ2 ≤
(71.42) 2 (32.36) 2
0.096 ≤ σ2 ≤ 0.2115
Taking the square root of the endpoints of this interval we obtain,
0.31 < σ < 0.46
Since 0.25 falls below the lower confidence bound we would conclude that the population standard
deviation is not equal to 0.25.
40
9-49 Using the chart in the Appendix, with λ= = 1.49 and β = 0.10, we find
18
n = 30.
Section 9-5
9-51 p= 0.15, p0=0.10, n=85, and zα/2=1.96
p0 − p + zα / 2 p0 (1− p0 ) / n p0 − p − zα / 2 p0 (1− p0 ) / n
β = Φ − Φ
p(1− p) / n p(1− p) / n
0.10− 0.15+1.96 0.10(1− 0.10) / 85 0.10− 0.15−1.96 0.10(1− 0.10) / 85
= Φ − Φ
0.15(1− 0.15) / 85 0.15(1− 0.15) / 85
= Φ(0.36) − Φ(−2.94) = 0.6406− 0.0016= 0.639
Image 61: 2
zα / 2 p0 (1− p0 ) − z β p(1− p)
n =
p − p0
2
1.96 0.10(1− 0.10) −1.28 0.15(1− 0.15)
=
0.15− 0.10
2
= (10.85) = 11763≅ 118
.
9-53. a) Using the information from Exercise 8-51, test
2) H0 : p = 0.05
3) H1 : p < 0.05
4) α = 0.05
x − np0 p − p0
ˆ
5) z0 = or z0 = ; Either approach will yield the same conclusion
np0 (1 − p0 ) p0 (1 − p0 )
n
6) Reject H0 if z0 < − zα where −zα = −z0.05 = −1.65
13
7) x = 13 n = 300 p =∃ = 0.043
300
x − np0 13 − 300(0.05)
z0 = = = −0.53
np0 (1 − p0 ) 300(0.05)(0.95)
8) Since −0.53 > −1.65, do not null hypothesis and conclude the true fraction of defective integrated
circuits is not significantly less than 0.05, at α = 0.05.
b) P-value = 1 − Φ(0.53) = 0.29806
9-57. The problem statement implies that H0: p = 0.6, H1: p > 0.6 and defines an acceptance region as
315
∃
p≤ ∃
= 0.63 and rejection region as p > 0.63
500
a) The probability of a type 1 error is
α = P( p ≥ 0.63 | p = 0.6 ) = P
ˆ Z ≥ 0.63 − 0.6 = P(Z ≥ 1.37 ) = 1 − P( Z < 1.37) = 0.08535 .
0.6(0.4)
500
∃
b) β = P( P ≤ 0.63 | p = 0.75) = P(Z ≤ −6.196) = 0.
Section 9-7
9-59.
Value 0 1 2 3 4
Observed Frequency 24 30 31 11 4
Expected Frequency 30.12 36.14 21.69 8.67 2.60
Since value 4 has an expected frequency less than 3, combine this category with the previous category:
Value 0 1 2 3-4
Observed Frequency 24 30 31 15
Expected Frequency 30.12 36.14 21.69 11.67
The degrees of freedom are k − p − 1 = 4 − 0 − 1 = 3
Image 62: a) 1) The variable of interest is the form of the distribution for X.
2) H0: The form of the distribution is Poisson
3) H1: The form of the distribution is not Poisson
4) α = 0.05
5) The test statistic is
χ =∑
2
k
(Oi − Ei )2
0
i =1 Ei
6) Reject H0 if χ2 > χ 2.05,3 = 7.81
o 0
7) χ 2
=
(24− 30.12)2 + (30− 36.14)2 + (31− 21.69)2 + (15−11.67)2 = 7.23
0
30.12 36.14 21.69 11.67
8) Since 7.23 < 7.81 do not reject H0. We are unable to reject the null hypothesis that the distribution of
X is Poisson.
b) The P-value is between 0.05 and 0.1 using Table III. P-value = 0.0649 (found using Minitab)
9-63 ∃
The value of p must be estimated. Let the estimate be denoted by psample
0(39 ) + 1(23) + 2(12) + 3(1)
sample mean = = 0.6667
75
sample mean 0.6667
p sample =
ˆ = = 0.02778
n 24
Value 0 1 2 3
Observed 39 23 12 1
Expected 38.1426 26.1571 8.5952 1.8010
Since value 3 has an expected frequency less than 3, combine this category with that of value 2:
Value 0 1 2-3
Observed 39 23 13
Expected 38.1426 26.1571 10.3962
The degrees of freedom are k − p − 1 = 3 − 1 − 1 = 1
a) 1) The variable of interest is the form of the distribution for the number of under-filled cartons, X.
2) H0: The form of the distribution is binomial
3) H1: The form of the distribution is not binomial
4) α = 0.05
5) The test statistic is
χ2 =
k (Oi − Ei )2
0 ∑ Ei
i =1
6) Reject H0 if χ2 > χ 2.05,1 = 384
o 0 .
7) χ2 =
(39 − 38.1426)2 + (23 − 26.1571)2 + (13 − 10.3962)2
= 1.053
0
381426
. 26.1571 10.39
8) Since 1.053 < 3.84 do not reject H0. We are unable to reject the null hypothesis that the distribution
of the number of under-filled cartons is binomial at α = 0.05.
b) The P-value is between 0.5 and 0.1 using Table III P-value = 0.3048 (found using Minitab)
Section 9-8
9-65. 1. The variable of interest is breakdowns among shift.
2. H0: Breakdowns are independent of shift.
Image 63: 3. H1: Breakdowns are not independent of shift.
4. α = 0.05
5. The test statistic is:
r c (O − Eij )
2
χ = ∑∑
2 ij
0
i =1 j =1 Eij
6. The critical value is χ .05 , 6
= 12.592
2
The calculated test statistic is χ 0 = 11.65
2
7.
8. χ 2 > χ 2.05,6 , do not reject H0 and conclude that the data provide insufficient evidence to claim that
0 / 0
machine breakdown and shift are dependent at α = 0.05.
P-value = 0.070 (using Minitab)
9-69. 1. The variable of interest is failures of an electronic component.
2. H0: Type of failure is independent of mounting position.
3. H1: Type of failure is not independent of mounting position.
4. α = 0.01
5. The test statistic is:
r c (O − Eij )
2
χ = ∑∑
2 ij
0
i =1 j =1 Eij
6. The critical value is χ .01, 3
= 11.344
2
7. The calculated test statistic is χ 0 = 10.71
2
8. χ 0 > χ 0.01,3
2
/
2
, do not reject H0 and conclude that the evidence is not sufficient to claim that the type of
failure is not independent of the mounting position at α = 0.01.
P-value = 0.013
Supplemental
α
9-75. σ = 8, δ = 204 − 200 = −4, = 0.025, z0.025 = 1.96.
2
4 20
a) n = 20: β = Φ1.96 −
= Φ( −0.28) = 1 − Φ(0.28) = 1 − 0.61026 = 0.38974
8
Therefore, power = 1 − β = 0.61026
4 50
b) n = 50: β = Φ1.96 −
= Φ ( −2.58) = 1 − Φ(2.58) = 1 − 0.99506 = 0.00494
8
Therefore, power = 1 − β = 0.995
4 100
c) n = 100: β = Φ1.96 −
= Φ( −3.04) = 1 − Φ(3.04) = 1 − 0.99882 = 0.00118
8
Therefore, power = 1 − β = 0.9988
d) As sample size increases, and all other values are held constant, the power increases because the
variance of the sample mean decreases. Consequently, the probability of a Type II error decreases, which implies the
power increases.
9-77. a) Rejecting a null hypothesis provides a stronger conclusion than failing to reject a null hypothesis.
Therefore, place what we are trying to demonstrate in the alternative hypothesis.
Assume that the data follow a normal distribution.
Image 64: b) 1) the parameter of interest is the mean weld strength, µ.
2) H0 : µ = 150
3) H1 : µ > 150
4) Not given
5) The test statistic is:
x − µ0
t0 =
s/ n
6) Since no critical value is given, we will calculate the P-value
7) x = 153.7 , s= 11.3, n=20
153.7 − 150
t0 = = 1.46
11.3 20
P-value = P( t ≥ 1.46) = 0.05 < p − value < 010
.
8) There is some modest evidence to support the claim that the weld strength exceeds 150 psi.
If we used α = 0.01 or 0.05, we would not reject the null hypothesis, thus the claim would not be
supported. If we used α = 0.10, we would reject the null in favor of the alternative and conclude the
weld strength exceeds 150 psi.
9-79 a) 1) the parameter of interest is the standard deviation, σ
2) H0 : σ2 = 400
3) H1 : σ2 < 400
4) Not given
( n − 1) s2
5) The test statistic is: χ2 =
0
σ2
6) Since no critical value is given, we will calculate the p-value
7) n = 10, s = 15.7
9(15.7) 2
χ2 =
0 = 5546
.
400
(
P-value = P χ 2 < 5546 ;
. ) 01 < P − value < 0.5
.
8) The P-value is greater than any acceptable significance level, α, therefore we do not reject the null
hypothesis. There is insufficient evidence to support the claim that the standard deviation is less than
20 microamps.
b) 7) n = 51, s = 20
50(15.7)2
χ2 =
0 = 30.81
400
(
P-value = P χ 2 < 30.81 ; ) 0.01 < P − value < 0.025
8) The P-value is less than 0.05, therefore we reject the null hypothesis and conclude that the standard
deviation is significantly less than 20 microamps.
c) Increasing the sample size increases the test statistic χ2 and therefore decreases the P-value, providing
0
more evidence against the null hypothesis.
9-85 We can divide the real line under a standard normal distribution into eight intervals with equal
probability. These intervals are [0,.32), [0.32, 0.675), [0.675, 1.15), 1.15, ∞) and their negative
counterparts. The probability for each interval is p = 1/8 = .125 so the expected cell frequencies
are E = np = (100) (0.125) = 12.5. The table of ranges and their corresponding frequencies is
completed as follows.
![Image 65: Interval Obs. Frequency. Exp. Frequency.
x ≤ 5332.5 1 12.5
5332.5< x ≤ 5357.5 4 12.5
5357.5< x ≤ 5382.5 7 12.5
5382.5< x ≤ 5407.5 24 12.5
5407.5< x ≤ 5432.5 30 12.5
5432.5< x ≤ 5457.5 20 12.5
5457.5< x ≤ 5482.5 15 12.5
x ≥ 5482.5 5 12.5
The test statistic is:
2 (1 - 12.5)2 (4 − 12.5) 2 (15 - 12.5) 2 (5 − 12.5) 2
χ0 = + +Λ + + = 63.36
12.5 12.5 12.5 12.5
and we would reject if this value exceeds χ 20.05,5 = 11.07 . Since χ o > χ 0.05,5 , reject the
2 2
hypothesis that the data are normally distributed
9-87 a) In order to use t statistics in hypothesis testing, we need to assume that the underlying distribution
is normal.
1) The parameter of interest is the true mean overall distance for this brand of golf ball, µ.
2) H0 : µ = 270
3) H1 : µ < 270
4) α = 0.05
5) Since n>>30 we can use the normal distribution
x−µ
z0 =
s/ n
6) Reject H0 if z0 <- zα where z0.05 =1.65
7) x = 1.25 s = 0.25 n = 20
260.30 − 270.0
z0 = = −7.23
13.41 / 100
8) Since –7.23<-1.65, reject the null hypothesis and conclude there is sufficient evidence to indicate that the
true mean distance is less than 270 yds at α = 0.05.
b) The P-value ≅ 0.
c) We can divide the real line under a standard normal distribution into eight intervals with equal
probability. These intervals are [0,.32), [0.32, 0.675), [0.675, 1.15), [1.15, ∞) and their
negative counterparts. The probability for each interval is p = 1/8 = .125 so the expected cell
frequencies are E = np = (100) (0.125) = 12.5. The table of ranges and their corresponding
frequencies is completed as follows.
Interval Obs. Frequency. Exp. Frequency.
x ≤ 244.88 16 12.5
244.88< x ≤ 251.25 6 12.5
251.25< x ≤ 256.01 17 12.5
256.01< x ≤ 260.30 9 12.5
260.30< x ≤ 264.59 13 12.5
264.59< x ≤ 269.35 8 12.5
269.35< x ≤ 275.72 19 12.5
x ≥ 275.72 12 12.5
Image 66: The test statistic is:
(16 − 12.5) 2 (6 − 12.5) 2 (19 − 12.5) 2 (12 − 12.5) 2
χ 2o = + +Λ + + = 12
12.5 12.5 12.5 12.5
and we would reject if this value exceeds χ 20.05,5 = 11.07 . Since it does, we can
reject the hypothesis that the data are normally distributed.
Image 67: Chapter 10 Selected Problem Solutions
Section 10-2
10-1. a) 1) The parameter of interest is the difference in fill volume, µ1 − µ 2 ( note that ∆0=0)
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
z0 =
σ1 σ 2
2
+ 2
n1 n2
6) Reject H0 if z0 < −zα/2 = −1.96 or z0 > zα/2 = 1.96
7) x1 = 16.015 x2 = 16.005
σ1 = 0.02 σ 2 = 0.025
n1 = 10 n2 = 10
(16.015 − 16.005)
z0 = = 0.99
(0.02) 2 (0.025) 2
+
10 10
8) since -1.96 < 0.99 < 1.96, do not reject the null hypothesis and conclude there is no evidence that the
two machine fill volumes differ at α = 0.05.
b) P-value = 2(1 − Φ(0.99)) = 2(1 − 0.8389) = 0.3222
c) Power = 1 − β , where
∆ − ∆0 ∆ − ∆0
β = Φ zα / 2 − − Φ − zα / 2 −
2
σ1 σ 22 σ1 σ 2
2
2
+ +
n1 n 2 n1 n2
0.04 0.04
= Φ1.96 − − Φ − 1.96 −
(0.02) 2 (0.025) 2 (0.02) 2 (0.025) 2
+ +
10 10 10 10
= Φ ( .96 − 3.95) − Φ (− 1.96 − 3.95) = Φ (− 1.99 ) − Φ (− 5.91)
1
= 0.0233 − 0
= 0.0233
Power = 1 −0.0233 = 0.9967
σ1 σ 2
2
σ2 σ 2
d) (x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2
n1 n 2 n1 n 2
(0.02) 2 (0.025) 2 (0.02) 2 (0.025) 2
(16.015 − 16.005) − 1.96 + ≤ µ1 − µ 2 ≤ (16.015 − 16.005) + 196
. +
10 10 10 10
−0.0098 ≤ µ1 − µ 2 ≤ 0.0298
With 95% confidence, we believe the true difference in the mean fill volumes is between −0.0098 and
0.0298. Since 0 is contained in this interval, we can conclude there is no significant difference between
the means.
e) Assume the sample sizes are to be equal, use α = 0.05, β = 0.05, and ∆ = 0.04
Image 68: (z + z β ) (σ 12 + σ 2 ) (1.96 + 1.645)2 ((0.02) 2 + (0.025) 2 ) = 8.33,
2 2
α /2
n≅ = n = 9,
δ2 (0.04) 2
use n1 = n2 = 9
10-5. x1 = 30.87 x2 = 30.68
σ1 = 0.10 σ 2 = 0.15
n1 = 12 n2 = 10
a) 90% two-sided confidence interval:
σ1 σ 2
2
σ2 σ 2
(x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2
n1 n 2 n1 n 2
( 010) 2 ( 015) 2
. . (010)2 (015) 2
. .
(30.87 − 30.68) − 1.645 + ≤ µ1 − µ 2 ≤ ( 30.87 − 30.68) + 1645
. +
12 10 12 10
0.0987 ≤ µ1 − µ 2 ≤ 0.2813
We are 90% confident that the mean fill volume for machine 1 exceeds that of machine 2 by between
0.0987 and 0.2813 fl. oz.
b) 95% two-sided confidence interval:
σ1 σ 2
2
σ2 σ 2
(x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2
n1 n 2 n1 n 2
(0.10) 2 (015) 2
. (010) 2 (015)2
. .
(30.87 − 30.68) − 1.96 + ≤ µ1 − µ 2 ≤ ( 30.87 − 30.68) + 196
. +
12 10 12 10
0.0812 ≤ µ1 − µ 2 ≤ 0.299
We are 95% confident that the mean fill volume for machine 1 exceeds that of machine 2 by between
0.0812 and 0.299 fl. oz.
Comparison of parts a and b:
As the level of confidence increases, the interval width also increases (with all other values held constant).
c) 95% upper-sided confidence interval:
2
σ1 σ 2
µ1 − µ 2 ≤ ( x1 − x2 ) + zα + 2
n1 n2
(010) 2 (015) 2
. .
µ1 − µ 2 ≤ ( 30.87 − 30.68) + 1.645 +
12 10
µ1 − µ 2 ≤ 0.2813
With 95% confidence, we believe the fill volume for machine 1 exceeds the fill volume of machine 2 by
no more than 0.2813 fl. oz.
10-7. x1 = 89.6 x2 = 92.5
2
σ1 = 1.5 σ 2 = 1.2
2
n1 = 15 n2 = 20
a) 95% confidence interval:
σ1 σ 2
2
σ2 σ 2
(x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2
n1 n 2 n1 n 2
Image 69: 15 1.2
. 15 12
. .
(89.6 − 92.5) − 196
. + ≤ µ1 − µ 2 ≤ (89.6 − 92.5) + 1.96 +
15 20 15 20
−3.684 ≤ µ1 − µ 2 ≤ −2.116
With 95% confidence, we believe the mean road octane number for formulation 2 exceeds that of
formulation 1 by between 2.116 and 3.684.
b) 1) The parameter of interest is the difference in mean road octane number, µ1 − µ 2 and ∆0 = 0
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 < 0 or µ1 < µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
z0 =
σ1 σ 2
2
+ 2
n1 n2
6) Reject H0 if z0 < −zα = −1.645
7) x1 = 89.6 x2 = 92.5
2
σ1 = 1.5 σ 2 = 1.2
2
n1 = 15 n2 = 20
(89.6 − 92.5) − 0
z0 = = −7.254
(15) 2 (12) 2
. .
+
15 20
8) Since −7.25 < -1.645 reject the null hypothesis and conclude the mean road octane number for formulation
2 exceeds that of formulation 1 using α = 0.05.
c) P-value = P ( z ≤ −7.25) = 1 − P ( z ≤ 7.25) = 1 − 1 ≅ 0
10-9. 95% level of confidence, E = 1, and z0.025 =1.96
2 2
z
(
n ≅ 0.025 σ 12 + σ 2 =
2
)
1.96
(1.5 + 1.2) = 10.37, n = 11, use n1 = n2 = 11
E 1
10-11. Catalyst 1 Catalyst 2
x1 = 65.22 x2 = 68.42
σ1 = 3 σ2 = 3
n1 = 10 n2 = 10
a) 95% confidence interval on µ1 − µ 2 , the difference in mean active concentration
2
σ1 σ 2 σ2 σ 2
(x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2
n1 n 2 n1 n 2
(3) 2 (3) 2 (3) 2 (3)2
(65.22 − 68.42) − 196
. + ≤ µ1 − µ 2 ≤ ( 65.22 − 68.42 ) + 1.96 +
10 10 10 10
−5.83 ≤ µ1 − µ 2 ≤ −0.57
We are 95% confident that the mean active concentration of catalyst 2 exceeds that of catalyst 1 by
between 0.57 and 5.83 g/l.
b) Yes, since the 95% confidence interval did not contain the value 0, we would conclude that the mean
active concentration depends on the choice of catalyst.
Image 70: 10-13. 1) The parameter of interest is the difference in mean active concentration, µ1 − µ 2
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
z0 =
σ1 σ 2
2
+ 2
n1 n2
6) Reject H0 if z0 < −zα/2 = −1.96 or z0 > zα/2 = 1.96
7) x1 = 750.2 x2 = 756.88 δ = 0
σ1 = 20 σ 2 = 20
n1 = 15 n2 = 8
(750.2 − 756.88) − 0
z0 = = −2.385
(20) 2 (20) 2
+
15 8
8) Since −2.385 < −1.96 reject the null hypothesis and conclude the mean active concentrations do differ
significantly at α = 0.05.
P-value = 2 (1 − Φ( 2.385)) = 2(1 − 0.99146) = 0.0171
The conclusions reached by the confidence interval of the previous problem and the test of hypothesis
conducted here are the same. A two-sided confidence interval can be thought of as representing the
“acceptance region” of a hypothesis test, given that the level of significance is the same for both
procedures. Thus if the value of the parameter under test that is specified in the null hypothesis falls outside
the confidence interval, this is equivalent to rejecting the null hypothesis.
Section 10-3
10-17 a) 1) The parameter of interest is the difference in mean rod diameter, µ1 − µ 2 , with ∆0 = 0
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
t0 =
1 1
sp +
n1 n 2
6) Reject the null hypothesis if t0 < − t α/ 2, n1 + n 2 − 2 where −t 0.025,30 = −2.042 or t0 > t α / 2, n1 + n 2 − 2 where
t 0.025,30 = 2.042
( n1 − 1)s1 + ( n2 − 1)s2
2
2
7) ) x1 = 8.73 x2 = 8.68 sp =
n1 + n 2 − 2
2 14(0.35) + 16(0.40)
s1 = 0.35 s2 = 0.40
2 = = 0.614
30
n1 = 15 n2 = 17
(8.73 − 8.68)
t0 = = 0.230
1 1
0.614 +
15 17
8) Since −2.042 < 0.230 < 2.042, do not reject the null hypothesis and conclude the two machines do not
produce rods with significantly different mean diameters at α = 0.05.
Image 71: b) P-value = 2P ( t > 0.230) > 2(0.40), P-value > 0.80
c) 95% confidence interval: t0.025,30 = 2.042
1 1 1 1
(x1 − x2 ) − t α / 2,n + n
1 2 −2
(sp ) +
n1 n 2
≤ µ1 − µ 2 ≤ (x1 − x2 ) + t α / 2, n1 + n 2 − 2 (sp ) +
n1 n2
1 1 1 1
(8.73 − 8.68) − 2.042(0.614) + ≤ µ1 − µ 2 ≤ (8.73 − 8.68) + 2.042(0.643) +
15 17 15 17
− 0.394 ≤ µ1 − µ 2 ≤ 0.494
Since zero is contained in this interval, we are 95% confident that machine 1 and machine 2 do not
produce rods whose diameters are significantly different.
10-21. a) 1) The parameter of interest is the difference in mean etch rate, µ1 − µ 2 , with ∆0 = 0
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
t0 =
1 1
sp +
n1 n 2
6) Reject the null hypothesis if t0 < − t α/ 2, n1 + n 2 − 2 where − t 0.025,18 = −2.101 or t0 > t α / 2, n1 + n 2 − 2 where
t 0.025,18 = 2.101
( n1 − 1)s1 + ( n2 − 1)s2
2
2
7) x1 = 9.97 x2 = 10.4 sp =
n1 + n 2 − 2
9(0.422) 2 + 9(0.231) 2
s1 = 0.422 s2 = 0.231 = = 0.340
18
n1 = 10 n2 = 10
(9.97 − 10.4)
t0 = = −2.83
1 1
0.340 +
10 10
8) Since −2.83 < −2.101 reject the null hypothesis and conclude the two machines mean etch rates do
significantly differ at α = 0.05.
b) P-value = 2P (t < −2.83) 2(0.005) < P-value < 2(0.010) = 0.010 < P-value < 0.020
c) 95% confidence interval: t0.025,18 = 2.101
1 1 1 1
(x1 − x2 ) − t α / 2,n + n
1 2 −2
(sp ) +
n1 n 2
≤ µ1 − µ 2 ≤ (x1 − x2 ) + t α / 2, n1 + n 2 − 2 (sp ) +
n1 n2
1 1 1 1
(9 .97 − 10 .4 ) − 2 .101 (.340 ) + ≤ µ 1 − µ 2 ≤ (9 .97 − 10 .4 ) + 2 .101(.340 ) +
10 10 10 10
− 0.749 ≤ µ1 − µ 2 ≤ −0.111
We are 95% confident that the mean etch rate for solution 2 exceeds the mean etch rate for solution 1
by between 0.1105 and 0.749.
Image 72: d) According to the normal probability plots, the assumption of normality appears to be met since the data
from both samples fall approximately along straight lines. The equality of variances does not appear to be
severely violated either since the slopes are approximately the same for both samples.
Normal Probability Plot Normal Probability Plot
.999
.999
.99
.99
.95
.95
Probability
.80
Probability
.80
.50 .50
.20 .20
.05 .05
.01 .01
.001 .001
9.5 10.0 10.5 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7
solution solution
Average: 9.97 Anderson-Darling Normality Test Average: 10.4 Anderson-Darling Normality Test
StDev: 0.421769 A-Squared: 0.269 StDev: 0.230940 A-Squared: 0.211
N: 10 P-Value: 0.595 N: 10 P-Value: 0.804
10-27 a) 1) The parameter of interest is the difference in mean wear amount, µ1 − µ 2 .
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
t0 =
s1 s2
2
+ 2
n1 n2
6) Reject the null hypothesis if t0 < −t 0.025,27 where −t 0.025,27 = −2.052 or t0 > t 0.025,27 where t 0.025,27 =
2.052 since
2
s12 s 2
2
+
n
ν= 1 n2 = 26.98
2
s12 s2
2
n
1 + n2
n1 − 1 n 2 − 1
ν ≅ 26
(truncated)
7) x1 = 20 x2 = 15 ∆0 = 0
s1 = 2 s2 = 8
n1 = 25 n2 = 25
(20 − 15) − 0
t0 = = 3.03
(2) 2 (8) 2
+
25 25
8) Since 3.03 > 2.056 reject the null hypothesis and conclude that the data support the claim that the two
companies produce material with significantly different wear at the 0.05 level of significance.
b) P-value = 2P(t > 3.03), 2(0.0025) < P-value < 2(0.005)
0.005 < P-value < 0.010
c) 1) The parameter of interest is the difference in mean wear amount, µ1 − µ 2
2) H0 : µ1 − µ 2 = 0
3) H1 : µ1 − µ 2 > 0
4) α = 0.05
Image 73: 5) The test statistic is
( x1 − x2 ) − ∆ 0
t0 =
s1 s2
2
+ 2
n1 n2
6) Reject the null hypothesis if t0 > t 0.05,27 where t 0.05, 26 = 1.706 since
7) x1 = 20 x2 = 15
s1 = 2 s2 = 8 ∆0 = 0
n1 = 25 n2 = 25
(20 − 15) − 0
t0 = = 3.03
(2) 2 (8) 2
+
25 25
8) Since 3.03 > 1.706 reject the null hypothesis and conclude that the data support the claim that the
material from company 1 has a higher mean wear than the material from company 2 using a 0.05 level
of significance.
10-29. If α = 0.01, construct a 99% lower one-sided confidence interval on the difference to answer question 10-28.
t0.005,19 = 2.878
s12 s 2
2
s12 s 2
2
(x1 − x2 ) − tα / 2 ,ν + ≤ µ 1 − µ 2 ≤ (x1 − x 2 ) + tα / 2 ,ν +
n1 n 2 n1 n 2
(10.2) 2 (20.1) 2 (10.2) 2 (20.1) 2
(103.5 − 99.7) − 2.878 + ≤ µ1 − µ 2 ≤ (103.5 − 99.7) − 2.878 +
12 13 12 13
− 14.34 ≤ µ1 − µ 2 ≤ 21.94 .
Since the interval contains 0, we are 99% confident there is no difference in the mean coating thickness
between the two temperatures; that is, raising the process temperature does not significantly reduce the
mean coating thickness.
10-31 a.)
N orm al P ro b ab ility P lo t for B ran d 1 ...B ra n d 2
M L E s tim a te s
B ra nd 1
99
B ra nd 2
95
90
80
70
Percent
60
50
40
30
20
10
5
1
244 254 264 274 284 294
D a ta
b . 1) The parameter of interest is the difference in mean overall distance, µ1 − µ 2 , with ∆0 = 0
Image 74: 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
t0 =
1 1
sp +
n1 n 2
6) Reject the null hypothesis if t0 < − t α/ 2, n1 + n 2 − 2 where − t 0.025,18 = −2.101 or t0 > t α / 2, n1 + n 2 − 2 where
t 0.025,18 = 2.101
( n1 − 1)s1 + ( n2 − 1)s2
2
2
7) x1 = 275.7 x2 = 265.3 sp =
n1 + n 2 − 2
9(8.03) 2 + 9(10.04) 2
s1 = 8.03 s2 = 10.04 = = 9.09
20
n1 = 10 n2 = 10
(275.7 − 265.3)
t0 = = 2.558
1 1
9.09 +
10 10
8) Since 2.558>2.101 reject the null hypothesis and conclude that the data do not support the claim that
both brands have the same mean overall distance at α = 0.05. It appears that brand 1 has the higher mean
differnce.
c.)P-value = 2P (t < 2.558) P-value ≈ 2(0.01)=0.02
d.) d = 5 β=0.95 Power =1-0.95=0.05
0 . 275
2 ( 9 . 09 )
3
e.) 1-β=0..75 β=0..27 d = = 0.165 n=100 n = 100 + 1 = 50 . 5
2(9.09) 2
Therefore, n=51
1 1 1 1
f.) (x1 − x 2 ) − tα ,ν s p + ≤ µ1 − µ 2 ≤ (x1 − x 2 ) + tα ,ν s p +
n1 n2 n1 n2
1 1 1 1
(275.7 − 265.3) − 2.101(9.09) + ≤ µ1 − µ 2 ≤ (275.7 − 265.3) + 2.101(9.09) +
10 10 10 10
1.86 ≤ µ1 − µ 2 ≤ 18.94
Section 10-4
10-37 d = 868.375 sd = 1290, n = 8 where di = brand 1 - brand 2
99% confidence interval:
s s
d − t α / 2 , n −1 d ≤ µ d ≤ d + t α / 2 , n −1 d
n n
Image 75: 1290 1290
868.375 − 3.499 ≤ µ d ≤ 868.375 + 3.499
8 8
−727.46 ≤ µd ≤ 2464.21
Since this confidence interval contains zero, we are 99% confident there is no significant difference between
the two brands of tire.
10-39. 1) The parameter of interest is the difference in blood cholesterol level, µd
where di = Before − After.
2) H0 : µ d = 0
3) H1 : µ d > 0
4) α = 0.05
5) The test statistic is
d
t0 =
sd / n
6) Reject the null hypothesis if t0 > t 0.05,14 where t 0.05,14 = 1.761
7) d = 26.867
sd = 19.04
n = 15
26.867
t0 = = 5.465
19.04 / 15
8) Since 5.465 > 1.761 reject the null and conclude the data support the claim that the mean difference
in cholesterol levels is significantly less after fat diet and aerobic exercise program at the 0.05 level of
significance.
Section 10-5
10-47. 1) The parameters of interest are the variances of concentration, σ1 , σ 2
2
2
2) H0 : σ1 = σ 2
2
2
3) H1 : σ1 ≠ σ 2
2
2
4) α = 0.05
5) The test statistic is
2
s1
f0 =
s2
2
6) Reject the null hypothesis if f0 < f0.975,9 ,15 where f0.975,9 ,15 = 0.265 or f0 > f0.025,9 ,15 where f0.025,9,15 =3.12
7) n1 = 10 n2 = 16
s1 = 4.7 s2 = 5.8
(4.7) 2
f0 = = 0.657
(58) 2
.
8) Since 0.265 < 0.657 < 3.12 do not reject the null hypothesis and conclude there is insufficient evidence to
indicate the two population variances differ significantly at the 0.05 level of significance.
10-51 a) 90% confidence interval for the ratio of variances:
s12 σ 2 s2
2 f 1−α / 2, n1 −1, n2 −1 ≤ 12 ≤ 12 f α / 2, n1 −1, n2 −1
s σ 2 s2
2
(0.6) 2 σ1 (0.6)2
2
(0.8) 2 0.156 ≤ σ 2 ≤ (0.8) 2 6.39
2
Image 76: 2
σ1
0.08775 ≤ ≤ 3594
.
σ2
2
b) 95% confidence interval:
s1
2
σ 2 s2
f1− α / 2, n −1, n −1 ≤ 1 ≤ 1 fα / 2, n −1, n −1
s2
2
1 2
σ 2 s2
2 2
1 2
(0.6) 2 σ1 (0.6) 2
2
(0.8) 2 0104 ≤ σ 2 ≤ ( 0.8) 2 9.60
.
2
2
σ1
0.0585 ≤ ≤ 5.4
σ2
2
The 95% confidence interval is wider than the 90% confidence interval.
c) 90% lower-sided confidence interval:
s1
2
σ2
f1− α , n −1, n −1 ≤ 1
s2
2
1 2
σ2
2
(0.6) 2 σ12
( 0.8) 2 0.243 ≤ σ 2
2
2
σ1
0.137 ≤
σ2
2
10-55 1) The parameters of interest are the thickness variances, σ1 , σ 2
2
2
2) H0 : σ1 = σ 2
2
2
3) H1 : σ1 ≠ σ 2
2
2
4) α = 0.01
5) The test statistic is
s12
f0 = 2
s2
6) Reject the null hypothesis if f0 < f 0.995,10,12 where f 0.995,10,12 =0.1766 or f0 > f 0.005,10,12 where
f 0.005,10,12 = 2.91
7) n1 = 11 n2 = 13
s1 = 10.2 s2 = 20.1
(10.2) 2
f0 = = 0.2575
(20.1) 2
8) Since 0.1766 >0.2575 > 5.0855 do not reject the null hypothesis and conclude the thickness variances are
not equal at the 0.01 level of significance.
10-59 1) The parameters of interest are the overall distance standard deviations, σ1 , σ 2
2) H0 : σ1 = σ 2
2
2
3) H1 : σ1 ≠ σ 2
2
2
4) α = 0.05
5) The test statistic is
Image 77: 2
s1
f0 =
s2
2
6) Reject the null hypothesis if f0 < f .0.975,9,9 =0.248 or f0 > f 0.025,9,9 = 4.03
7) n1 = 10 n2 = 10 s1 = 8.03 s2 = 10.04
2
(8.03)
f0 = = 0.640
(10.04) 2
8) Since 0.248 < 0.640 < 4.04 do not reject the null hypothesis and conclude there is no evidence to support
the claim that there is a difference in the standard deviation of the overall distance of the two brands at the
0.05 level of significance.
95% confidence interval:
s1
2
σ 2 s2
f1− α / 2, n −1, n −1 ≤ 1 ≤ 1 fα / 2, n −1, n −1
s2
2
1 2
σ 2 s2
2 2
1 2
σ 12
(0.640)0.248 ≤ ≤ (0.640)4.03
σ2 2
σ 12
0.159 ≤ ≤ 2.579
σ2 2
Since the value 1 is contained within this interval, we are 95% confident there is no significant difference in
the standard deviation of the overall distance of the two brands at the 0.05 level of significance.
Section 10-6
10-61. 1) the parameters of interest are the proportion of defective parts, p1 and p2
2) H0 : p1 = p2
3) H1 : p1 ≠ p2
4) α = 0.05
5) Test statistic is
p1 − p2
ˆ ˆ
z0 = where
1 1
p (1 − p ) +
ˆ ˆ
n1 n2
x + x2
p= 1
ˆ
n1 + n 2
6) Reject the null hypothesis if z0 < −z0.025 where −z0.025 = −1.96 or z0 > z0.025
where z0.025 = 1.96
7) n1 = 300 n2 = 300
x1 = 15 x2 = 8
15 + 8
p1 = 0.05 p2 = 0.0267 p= = 0.0383
300 + 300
0.05 − 0.0267
z0 = = 1.49
1 1
0.0383(1 − 0.0383) +
300 300
8) Since −1.96 < 1.49 < 1.96 do not reject the null hypothesis and conclude that yes the evidence indicates
that there is not a significant difference in the fraction of defective parts produced by the two machines
Image 78: at the 0.05 level of significance.
P-value = 2(1−P(z < 1.49)) = 0.13622
10-63. a) Power = 1 − β
1 1 1 1
z pq + − ( p1 − p 2 ) − z pq + − ( p1 − p 2 )
n n2 n
β=
α /2 α /2
1 1 n2
Φ − Φ
σ p1 − p 2
ˆˆ ˆ σ p1 − p 2
ˆˆ ˆ
300(0.05) + 300(0.01)
p= = 0.03 q = 0.97
300 + 300
0.05(1 − 0.05) 0.01(1 − 0.01)
σ p1 − p 2 = + = 0.014
300 300
1.96 0.03(0.97) 1 + 1 − (0.05− 0.01) −1.96 0.03(0.97) 1 + 1 − (0.05 − 0.01)
β= 300 300 300 300
Φ − Φ
0.014 0.014
= Φ(− 0.91) − Φ (− 4.81) = 0.18141 − 0 = 0.18141
Power = 1 − 0.18141 = 0.81859
2
zα / 2
( p1 + p2 )(q1 + q2 ) + z
p1q1 + p2 q2
2
β
b) n =
( p1 − p2 )2
2
1.96
(0.05 + 0.01)(0.95 + 0.99) + 1.29
0.05(0.95) + 0.01(0.99)
2
= = 382.11
(0.05 − 0.01)2
n = 383
10-67 95% confidence interval on the difference:
p1(1 − p1) p2 (1 − p2 ) p (1 − p1) p2 (1 − p2 )
( p1 − p2 ) − zα / 2 + ≤ p1 − p2 ≤ ( p1 − p2 ) + zα / 2 1 +
n1 n2 n1 n2
0.77(1 − 0.77) 0.6675(1 − 0.6675) 0.77(1 − 0.77) 0.6675(1 − 0.6675)
( 0.77 − 0.6675) − 196
. + ≤ p1 − p 2 ≤ ( 0.77 − 0.6675) + 196
. +
500 400 500 400
0.0434 ≤ p1 − p 2 ≤ 0.1616
Since this interval does not contain the value zero, we are 95% confident there is a significant difference in
the proportions of support for increasing the speed limit between residents of the two counties and that the
difference in proportions is between 0.0434 and 0.1616.
Supplemental Exercises
10-69 a) Assumptions that must be met are normality, equality of variance, independence of the observations and of
the populations. Normality and equality of variances appears to be reasonable, see normal probability plot. The data
appear to fall along a straight line and the slopes appear to be the same. Independence of the observations for each
sample is assumed. It is also reasonable to assume that the two populations are independent.
Image 79: Normal Probability Plot Normal Probability Plot
.999 .999
.99 .99
.95 .95
Probability
Probability
.80 .80
.50 .50
.20 .20
.05 .05
.01 .01
.001 .001
14 15 16 17 18 19 20 8 9 10 11 12 13 14 15
9-hour 1-hour
Average: 16.3556 Anderson-Darling Normality Test Average: 11.4833 Anderson-Darling Normality Test
StDev: 2.06949 A-Squared: 0.171 StDev: 2.37016 A-Squared: 0.158
N: 9 P-Value: 0.899 N: 6 P-Value: 0.903
b) x1 = 16.36 x2 = 11486
.
s1 = 2.07 s2 = 2.37
n1 = 9 n2 = 6
99% confidence interval: t α/ 2, n1 + n 2 − 2 = t 0.005,13 where t 0.005,13 = 3.012
8(2.07) 2 + 5( 2.37) 2
sp = = 2.19
13
(x1 − x2 ) − t α / 2,n + n
1 2 −2 (sp ) 1
+
1
n1 n 2
≤ µ1 − µ 2 ≤ (x1 − x2 ) + t α / 2 , n1 + n 2 − 2 sp ( ) 1
+
1
n1 n 2
1 1 1 1
(16.36 − 11.486) − 3.012(2.19) + ≤ µ1 − µ 2 ≤ (16.36 − 11486) + 3.012( 2.19)
. +
9 6 9 6
140 ≤ µ1 − µ 2 ≤ 8.36
.
c) Yes, we are 99% confident the results from the first test condition exceed the results of the second test
condition by between 1.40 and 8.36 (×106 PA).
10-73 a) 1) The parameters of interest are the proportions of children who contract polio, p1 , p2
2) H0 : p1 = p2
3) H1 : p1 ≠ p2
4) α = 0.05
5) The test statistic is
p1 − p 2
ˆ ˆ
z0 =
1 1
p (1 − p ) +
ˆ ˆ
n1 n 2
6) Reject H0 if z0 < −zα /2 or z0 > zα/2 where zα/2 = 1.96
x1 110 x1 + x 2
7) p1 = = = 0.00055 (Placebo) p= = 0.000356
n1 201299 n1 + n 2
x2 33
p2 = = = 0.00016 (Vaccine)
n2 200745
0.00055 − 0.00016
z0 = = 6.55
1 1
0.000356 (1 − 0.000356 ) +
201299 200745
8) Since 6.55 > 1.96 reject H0 and conclude the proportion of children who contracted polio is
significantly different at α = 0.05.
b) α = 0.01 Reject H0 if z0 < −zα /2 or z0 > zα/2 where zα/2 =2.33
z0 = 6.55
Since 6.55 > 2.33, reject H0 and conclude the proportion of children who contracted polio is different at
α = 0.01.
c) The conclusions are the same since z0 is so large it exceeds zα/2 in both cases.
Image 80: 10-79.
2
(0.9 + 0.6)(0.1 + 0.4)
2.575 + 1.28 0.9(0.1) + 0.6(0.4)
2
n=
(0.9 − 0.6) 2
5.346
= = 59.4
0.09
n = 60
10-81. H0 : µ1 = µ 2
H1 : µ1 ≠ µ 2
n1 = n2 =n
β = 0.10
α = 0.05
Assume normal distribution and σ1 = σ 2 = σ 2
2
2
µ1 = µ 2 + σ
| µ − µ2 | σ 1
d= 1 = =
2σ 2σ 2
From Chart VI (e), n∗ = 50
n ∗ + 1 50 + 1
n= = = 25.5
2 2
n1 = n2 =26
10-83 a) No.
Normal Probability Plot Normal Probability Plot
.999 .999
.99 .99
.95 .95
Probability
Probability
.80 .80
.50 .50
.20 .20
.05 .05
.01 .01
.001 .001
23.9 24.4 24.9 30 35 40
mercedes volkswag
Average: 24.67 Anderson-Darling Normality Test Average: 40.25 Anderson-Darling Normality Test
StDev: 0.302030 A-Squared: 0.934 StDev: 3.89280 A-Squared: 1.582
N: 10 P-Value: 0.011 N: 10 P-Value: 0.000
b) The normal probability plots indicate that the data follow normal distributions since the data appear to fall
along a straight line. The plots also indicate that the variances could be equal since the slopes appear to be
the same.
Image 81: Normal Probability Plot
Normal Probability Plot
.999
.99 .999
.95 .99
Probability .95
.80
Probability
.80
.50
.50
.20
.20
.05
.05
.01
.01
.001
.001
24.5 24.6 24.7 24.8 24.9 39.5 40.5 41.5 42.5
mercedes volkswag
Average: 24.74 Anderson-Darling Normality Test Average: 41.25 Anderson-Darling Normality Test
StDev: 0.142984 A-Squared: 0.381 StDev: 1.21952 A-Squared: 0.440
N: 10 P-Value: 0.329 N: 10 P-Value: 0.230
c) By correcting the data points, it is more apparent the data follow normal distributions. Note that one
unusual observation can cause an analyst to reject the normality assumption.
d) 95% confidence interval on the ratio of the variances, σ 2 / σ 2
V M
s2 = 149
V . f9,9 ,0.025 = 4.03
1 1
s2 = 0.0204
M f9 ,9,0.975 = = = 0.248
f9,9 ,0.025 4.03
s2 σ2 s2
V f9,9 ,0.975 < V < V f9 ,9,0.025
s2 σ M s2
2
M M
1.49 σ2V 1.49
0.248 < 2 < 4.03
0.0204 σ M 0.0204
σ2
V
18124 <
. < 294.35
σ2M
Since the does not include the value of unity, we are 95% confident that there is evidence to reject the claim
that the variability in mileage performance is different for the two types of vehicles. There is evidence that the
variability is greater for a Volkswagen than for a Mercedes.
10-85 a) Underlying distributions appear to be normal since the data fall along a straight line on the normal
probability plots. The slopes appear to be similar, so it is reasonable to assume that σ 12 = σ 2 .
2
Normal Probability Plot for tip1...tip2
ML Estimates
tip1
99
tip2
95
90
80
70
Percent
60
50
40
30
20
10
5
1
40 45 50
Data
b) 1) The parameter of interest is the difference in mean volumes, µ1 − µ 2
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
Image 82: ( x1 − x2 ) − δ
t0 =
1 1
sp +
n1 n2
6) Reject H0 if t0 < −t α / 2 , ν or z0 > t α / 2, ν where t α / 2 , ν = t 0.025,18 = 2.101
9(1.252) 2 + 9(0.843) 2
7) x1 = 752.7 x2 = 755.6 sp = = 107
.
18
s1 = 1.252 s2 = 0.843
n1 = 10 n2 = 10
(752.7 − 755.6) − 0
t0 = = −6.06
1 1
107
. +
10 10
8) Since −6.06 < −2.101, reject H0 and conclude there is a significant difference between the two wineries
with respect to the mean fill volumes.
10-89 a.) The data from both depths appear to be normally distributed, but the slopes are not equal.
Therefore, it may not be assumed that σ 12 = σ 2 .
2
Normal Probability Plot for surface...bottom
ML Estimates
surface
99
bottom
95
90
80
70
Percent
60
50
40
30
20
10
5
1
4 5 6 7 8
Data
b.) 1) The parameter of interest is the difference in mean HCB concentration, µ1 − µ 2 , with ∆0 = 0
2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2
3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2
4) α = 0.05
5) The test statistic is
( x1 − x2 ) − ∆ 0
t0 =
s1 s2
2
+ 2
n1 n2
6) Reject the null hypothesis if t0 < − t 0.025,15 where − t 0.025,15 = −2.131 or t0 > t 0.025,15 where t 0.025,15 =
2.131 since
Image 83: 2
s12 s 2
2
+
n
ν= 1 n2 = 15.06
2
s12 s2
2
n
1 + n2
n1 − 1 n 2 − 1
ν ≅ 15
(truncated)
7) x1 = 4.804 x2 = 5.839 s1 = 0.631 s2 = 1.014
n1 = 10 n2 = 10
(4.804 − 5.839)
t0 = = −2.74
(0.631) 2 (1.014) 2
+
10 10
8) Since –2.74 < -2.131 reject the null hypothesis and conclude that the data support the claim that
the mean HCB concentration is different at the two depths sampled at the 0.05 level of significance.
b) P-value = 2P(t < -2.74), 2(0.005) < P-value < 2(0.01)
0.001 < P-value < 0.02
2
c) ∆ = 2 α = 0.05 n1 = n2 = 10 d= =1
2(1)
From Chart VI (e) we find β = 0.20, and then calculate Power = 1- β = 0.80
2
d.) ∆ = 2 α = 0.05 d= = 0.5 , β = 0.0
2(1)
50 + 1
From Chart VI (e) we find n=50 and n= = 25.5 , so n=26
2
Image 84: Chapter 11 Selected Problem Solutions
Section 11-2
11-1. a) y i = β 0 + β1x1 + ε i
S xx = 157.42 − 432
14
= 25.348571
43(572 )
S xy = 1697.80 − 14
= −59.057143
S xy −59.057143
β1 = = = −2.330
S xx 25.348571
β 0 = y − β1 x = 572 43
− ( −2.3298017)( 14 ) = 48.013
14
b) ˆ ˆ ˆ
y = β 0 + β1 x
y = 48.012962 − 2.3298017(4.3) = 37.99
ˆ
c) y = 48.012962 − 2.3298017(3.7) = 39.39
ˆ
d) e = y − y = 46.1 − 39.39 = 6.71
ˆ
11-5. a)
Regression Analysis - Linear model: Y = a+bX
Dependent variable: SalePrice Independent variable: Taxes
Standard T Prob.
Parameter Estimate Error Value Level
Intercept 13.3202 2.57172 5.17948 .00003
Slope 3.32437 0.390276 8.518 .00000
Analysis of Variance
Source Sum of Squares Df Mean Square F-Ratio Prob. Level
Model 636.15569 1 636.15569 72.5563 .00000
Residual 192.89056 22 8.76775
Total (Corr.) 829.04625 23
Correlation Coefficient = 0.875976 R-squared = 76.73 percent
Stnd. Error of Est. = 2.96104
σ 2 = 8.76775
ˆ
If the calculations were to be done by hand use Equations (11-7) and (11-8).
y = 13.3202 + 3.32437 x
b) y = 13.3202 + 3.32437(7.5) = 38.253
c) y = 13.3202 + 3.32437(58980) = 32.9273
.
y = 32.9273
ˆ
e = y − y = 30.9 − 32.9273 = −2.0273
ˆ
d) All the points would lie along the 45% axis line. That is, the regression model would estimate the values exactly. At
this point, the graph of observed vs. predicted indicates that the simple linear regression model provides a reasonable fit
to the data.
Image 85: Plot of Observed values versus predicted
50
45
Predicted
40
35
30
25
25 30 35 40 45 50
Observed
11-9. a) Yes, a linear regression would seem appropriate, but one or two points appear to be outliers.
9
8
7
6
5
y
4
3
2
1
0
60 70 80 90 100
x
Predictor Coef SE Coef T P
Constant -9.813 2.135 -4.60 0.000
x 0.17148 0.02566 6.68 0.000
S = 1.408 R-Sq = 71.3% R-Sq(adj) = 69.7%
Analysis of Variance
Source DF SS MS F P
Regression 1 88.520 88.520 44.66 0.000
Residual Error 18 35.680 1.982
Total 19 124.200
b) σ 2 = 1.9818 and y = −9.8131 + 0.171484 x
ˆ ˆ
c) y = 4.76301 at x = 85
ˆ
Image 86: 11-11. a) Yes, a linear regression would seem appropriate.
40
30
20
y 10
0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
x
Predictor Coef SE Coef T P
Constant 0.470 1.936 0.24 0.811
x 20.567 2.142 9.60 0.000
S = 3.716 R-Sq = 85.2% R-Sq(adj) = 84.3%
Analysis of Variance
Source DF SS MS F P
Regression 1 1273.5 1273.5 92.22 0.000
Residual Error 16 220.9 13.8
Total 17 1494.5
b) σ 2 = 13.81
ˆ
y = 0.470467 + 20.5673 x
ˆ
c) ˆ
y = 0.470467 + 20.5673(1) = 21.038
d) ˆ
y = 10.1371 e = 1.6629
Section 11-4
11-21. Refer to ANOVA of Exercise 11-5
a) 1) The parameter of interest is the regressor variable coefficient, β1.
2) H 0 : β1 = 0
3) H1 : β1 ≠ 0
4) α = 0.05, using t-test
ˆ
β1
5) The test statistic is t0 =
ˆ
se( β1 )
6) Reject H0 if t0 < −tα/2,n-2 where −t0.025,22 = −2.074 or t0 > t0.025,22 = 2.074
7) Using the results from Exercise 11-5
3.32437
t0 = = 8.518
0.390276
8) Since 8.518 > 2.074 reject H 0 and conclude the model is useful α = 0.05.
Image 87: b) 1) The parameter of interest is the slope, β1
2) H 0 :β1 = 0
3) H 1:β1 ≠ 0
4) α = 0.05
MSR SS R / 1
5) The test statistic is f0 = =
MSE SSE / ( n − 2)
6) Reject H0 if f0 > fα,1,22 where f0.01,1,22 = 4.303
7) Using the results from Exercise 10-5
636.15569 / 1
f0 = = 72.5563
192.89056 / 22
8) Since 72.5563 > 4.303, reject H 0 and conclude the model is useful at a significance α = 0.05.
The F-statistic is the square of the t-statistic. The F-test is a restricted to a two-sided test, whereas the
t-test could be used for one-sided alternative hypotheses.
c) se ( β ) =
ˆ σ2
ˆ 8 . 7675
1 = = . 39027
S xx 57 . 5631
ˆ 1 x 1 6 . 4049 2
se ( β 0 ) = σ2 +
ˆ = 8 . 7675 + = 2 .5717
n S xx 24 57 . 5631
d) 1) The parameter of interest is the intercept, β0.
2) H 0 : β0 = 0
3) H 1 : β0 ≠ 0
4) α = 0.05, using t-test
ˆ
β0
5) The test statistic is t0 =
ˆ
se( β0 )
6) Reject H0 if t0 < −tα/2,n-2 where −t0.025,22 = −2.074 or t0 > t0.025,22 = 2.074
7) Using the results from Exercise 11-5
13 . 3201
t0 = = 5 . 2774
2 . 5717
8) Since 5.2774 > 2.074 reject H 0 and conclude the intercept is not zero at α = 0.05.
11-25. Refer to ANOVA of Exercise 11-9
a) H 0 : β1 = 0
H 1 : β1 ≠ 0
α = 0.05
f 0 = 44.6567
f .05 ,1,18 = 4.416
f 0 > f α ,1,18
Therefore, reject H0. P-value = 0.000003.
b) ˆ
se( β1 ) = 0.0256613
ˆ
se( β ) = 2.13526
0
c) H 0 : β0 = 0
H1 : β0 ≠ 0
α = 0.05
Image 88: t0 = −4.59573
t.025 ,18 = 2.101
| t0 |> t α / 2 ,18
Therefore, reject H0. P-value = 0.00022.
Sections 11-5 and 11-6
11-31. tα/2,n-2 = t0.025,12 = 2.179
a) 95% confidence interval on β1 .
ˆ
β ±t ˆ
se ( β )
1 α / 2 ,n − 2 1
− 2 .3298 ± t.025 ,12 (0 .2697 )
− 2 .3298 ± 2 .179 (0 .2697 )
− 2 .9175 . ≤ β 1 ≤ − 1 .7421 .
b) 95% confidence interval on β0 .
ˆ
β ±t ˆ
se ( β )
0 . 025 ,12 0
48 . 0130 ± 2 .179 ( 0 . 5959 )
46 . 7145 ≤ β 0 ≤ 49 . 3114 .
c) 95% confidence interval on µ when x 0 = 2.5 .
µ Y | x 0 = 48 .0130 − 2 .3298 ( 2 .5) = 42 .1885
ˆ
( x0 − x ) 2
µ Y | x 0 ± t.025 ,12 σ 2 ( 1 +
ˆ ˆ n S xx )
( 2. 5 − 3 .0714 ) 2
42 .1885 ± ( 2 .179 ) 1 .844 ( 14 +
1
25 . 3486
)
42 .1885 ± 2 .179 ( 0 .3943 )
41 .3293 ≤ µ Y | x 0 ≤ 43 .0477
ˆ
d) 95% on prediction interval when x 0 = 2.5 .
( x0 − x ) 2
y0 ± t.025,12 σ 2 (1 + n +
ˆ ˆ 1
S xx
)
( 2.5 − 3.0714 ) 2
42 .1885 ± 2.179 1.844 (1 + 14 +
1
25.348571
)
42 .1885 ± 2.179 (1.1808 )
38 .2489 ≤ y0 ≤ 46 .1281
It is wider because it depends on both the error associated with the fitted model as well as that with the
future observation.
11-35. 99 percent confidence intervals for coefficient estimates
Estimate Standard error Lower Limit Upper Limit
CONSTANT -6.33550 1.66765 -11.6219 -1.05011
Temperature 9.20836 0.03377 9.10130 9.93154
a) 9.10130 ≤ β1 ≤ 9.31543
b) −11.6219 ≤ β0 ≤ −1.04911
1 (55−46.5)2
c) 500124 ± (2.228) 3.774609( 12 +
. 3308.9994
)
500124 ± 14037586
. .
∃
498.72024 ≤ µ Y|x ≤ 50152776
. 0
1 (55− 46.5)2
d) 500124 ± (2.228) 3.774609(1 + 12 +
. 3308.9994
)
Image 89: 500.124 ± 4.5505644
495.57344 ≤ y0 ≤ 504.67456
It is wider because the prediction interval includes error for both the fitted model and from that associated
with the future observation.
11-41 a) − 43 .1964 ≤ β 1 ≤ − 30 .7272
b) 2530 .09 ≤ β 0 ≤ 2720 . 68
( 20 −13 .3375 ) 2
c) 1886 .154 ± ( 2 . 101 ) 9811 . 21( 20 +
1
1114 .6618 )
1886 . 154 ± 62 .370688
1823 . 7833 ≤ µ y | x 0 ≤ 1948 .5247
d) 1886 . 154 ± ( 2 . 101 ) 9811 . 21 (1 + 1
20 + ( 20 −13 . 3375 ) 2
1114 . 6618 )
1886 . 154 ± 217 . 25275
1668 . 9013 ≤ y 0 ≤ 2103 . 4067
Section 11-7
11-43. Use the Results of exercise 11-5 to answer the following questions.
a) SalePrice Taxes Predicted Residuals
25.9 4.9176 29.6681073 -3.76810726
29.5 5.0208 30.0111824 -0.51118237
27.9 4.5429 28.4224654 -0.52246536
25.9 4.5573 28.4703363 -2.57033630
29.9 5.0597 30.1405004 -0.24050041
29.9 3.8910 26.2553078 3.64469225
30.9 5.8980 32.9273208 -2.02732082
28.9 5.6039 31.9496232 -3.04962324
35.9 5.8282 32.6952797 3.20472030
31.5 5.3003 30.9403441 0.55965587
31.0 6.2712 34.1679762 -3.16797616
30.9 5.9592 33.1307723 -2.23077234
30.0 5.0500 30.1082540 -0.10825401
36.9 8.2464 40.7342742 -3.83427422
41.9 6.6969 35.5831610 6.31683901
40.5 7.7841 39.1974174 1.30258260
43.9 9.0384 43.3671762 0.53282376
37.5 5.9894 33.2311683 4.26883165
37.9 7.5422 38.3932520 -0.49325200
44.5 8.7951 42.5583567 1.94164328
37.9 6.0831 33.5426619 4.35733807
38.9 8.3607 41.1142499 -2.21424985
36.9 8.1400 40.3805611 -3.48056112
45.8 9.1416 43.7102513 2.08974865
b) Assumption of normality does not seem to be violated since the data appear to fall along a straight line.
Image 90: Normal Probability Plot
99.9
99
95
cumulative percent
80
50
20
5
1
0.1
-4 -2 0 2 4 6 8
Residuals
c) No serious departure from assumption of constant variance. This is evident by the random pattern of the
residuals.
Plot of Residuals versus Predicted Plot of Residuals versus Taxes
8 8
6 6
4 4
Residuals
Residuals
2 2
0 0
-2 -2
-4 -4
26 29 32 35 38 41 44 3.8 4.8 5.8 6.8 7.8 8.8 9.8
Predicted Values Taxes
d) R 2 ≡ 76.73% ;
11-47. a) R 2 = 71.27%
b) No major departure from normality assumptions.
Normal Probability Plot of the Residuals
(response is y)
3
2
1
Residual
0
-1
-2
-2 -1 0 1 2
Normal Score
c) Assumption of constant variance appears reasonable.
Image 91: R idualsVers x
es us Residuals Versus the Fitted Values
(response is y)
(response is y)
3
3
2
2
1 1
Residual
Residual
0 0
-1 -1
-2 -2
60 70 80 90 100 0 1 2 3 4 5 6 7 8
x Fitted Value
11-49. a) R 2 = 85 . 22 %
b) Assumptions appear reasonable, but there is a suggestion that variability increases with ∃
y.
Residuals Versus x
(response is y)
Residuals Versus the Fitted Values
(response is y)
5
5
Residual
Residual
0 0
-5 -5
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 10 20 30 40
x Fitted Value
c) Normality assumption may be questionable. There is some “ bending” away from a straight line in the
tails of the normal probability plot.
Normal Probability Plot of the Residuals
(response is y)
5
Residual
0
-5
-2 -1 0 1 2
Normal Score
Section 11-10
11-55. a) y = −0.0280411 + 0.990987 x
ˆ
b) H 0 : β 1 = 0
H 1 : β1 ≠ 0 α = 0.05
f 0 = 79 . 838
f . 05 ,1 ,18 = 4 . 41
f 0 >> f α ,1 ,18
Reject H0 .
Image 92: c) r = 0 . 816 = 0 . 903
d) H 0 : ρ = 0
H1 : ρ ≠ 0 α = 0.05
R n−2 0 . 90334 18
t0 = = = 8 . 9345
1− R 2
1 − 0 . 816
t .025 ,18 = 2 . 101
t 0 > t α / 2 ,18
Reject H0 .
e) H 0 : ρ = 0 . 5
H 1 : ρ ≠ 0 .5 α = 0.05
z 0 = 3 . 879
z .025 = 1 . 96
z 0 > zα / 2
Reject H0 .
z.025
f) tanh(arctanh 0.90334 -
17
) ≤ ρ ≤ tanh(arctanh 0.90334 + z.025 ) where z.025 = 196 .
17
.
0 . 7677 ≤ ρ ≤ 0 . 9615 .
11-59 n = 50 r = 0.62
a) H 0 : ρ = 0
H1 : ρ ≠ 0 α = 0.01
r n−2 0 . 62 48
t0 = = = 5 . 475
1− r 2 1 − ( 0 . 62 ) 2
t .005 , 48 = 2 . 683
t 0 > t 0 .005 , 48
Reject H 0 . P-value ≅ 0
) where z.005 = 2.575.
z.005 z.005
b) tanh(arctanh 0.62 -
47
) ≤ ρ ≤ tanh(arctanh 0.62 + 47
0 .3358 ≤ ρ ≤ 0 . 8007 .
c) Yes.
11-61. a) r = 0.933203
a) H0 :ρ = 0
H1 : ρ ≠ 0 α = 0.05
r n−2 0 . 933203 15
t0 = = 1 − ( 0 . 8709 )
= 10 . 06
1− r 2
t.025 ,15 = 2 . 131
t 0 > tα / 2 ,15
Reject H0.
c) y = 0.72538 + 0.498081x
ˆ
H 0 : β1 = 0
H 1 : β1 ≠ 0 α = 0.05
Image 93: f 0 = 101 . 16
f . 05 ,1 ,15 = 4 . 545
f 0 >> f α ,1 ,15
Reject H0. Conclude that the model is significant at α = 0.05. This test and the one in part b are identical.
d) H0 : β0 = 0
H1 : β0 ≠ 0 α = 0.05
t 0 = 0 . 468345
t . 025 ,15 = 2 . 131
t 0 > tα
/ / 2 ,15
Do not reject H0. We cannot conclude β0 is different from zero.
e) No serious problems with model assumptions are noted.
Residuals Versus x Residuals Versus the Fitted Values
(response is y) (response is y)
3 3
2 2
1 1
Residual
Residual
0 0
-1 -1
-2 -2
10 20 30 40 50 5 15 25
x Fitted Value
Normal Probability Plot of the Residuals
(response is y)
3
2
1
Residual
0
-1
-2
-2 -1 0 1 2
Normal Score
Supplemental
11-65. a) y = 93.34 + 15.64 x
ˆ
b) H 0 : β1 = 0
H 1 : β1 ≠ 0 α = 0.05
f 0 = 12.872
f 0.05,1,14 = 4.60
f 0 > f 0.05,1,14
Reject H 0 . Conclude that β 1 ≠ 0 at α = 0.05.
c) (7.961 ≤ β1 ≤ 23.322)
d) (74.758 ≤ β 0 ≤ 111.923)
ˆ
e) y = 93.34 + 15.64(2.5) = 132.44
![Image 94: 132.44 ± 2.145 136.27 16 +
1
[ ( 2.5 − 2.325 ) 2
7.017
]
132.44 ± 6.26
126.18 ≤ µ Y | x0 = 2.5 ≤ 138.70
ˆ
11-67 a)
15
10
y
5
0
0 500 1000 1500 2000 2500 3000 3500
x
b) y = −0.8819 + 0.00385 x
ˆ
c) H 0 : β1 = 0
H1 : β1 ≠ 0 α = 0.05
f 0 = 122.03
f 0 > fα ,1, 48
Reject H0 . Conclude that regression model is significant at α = 0.05
d) No, it seems the variance is not constant, there is a funnel shape.
Residuals Versus the Fitted Values
(response is y)
3
2
1
0
Residual
-1
-2
-3
-4
-5
0 5 10
Fitted Value
e) y ∗ = 0.5967 + 0.00097 x . Yes, the transformation stabilizes the variance.
ˆ
11-71 a)
110
100
90
80
days
70
60
50
40
30
16 17 18
index
](
Image 95: b) The regression equation is
ˆ
y = −193 + 15.296 x
Predictor Coef SE Coef T P
Constant -193.0 163.5 -1.18 0.258
x 15.296 9.421 1.62 0.127
S = 23.79 R-Sq = 15.8% R-Sq(adj) = 9.8%
Analysis of Variance
Source DF SS MS F P
Regression 1 1492.6 1492.6 2.64 0.127
Error 14 7926.8 566.2
Total 15 9419.4
Cannot reject Ho; therefore we conclude that the model is not significant. Therefore the seasonal
meteorological index (x) is not a reliable predictor of the number of days that the ozone level exceeds 0.20
ppm (y).
c) 95% CI on β1
ˆ ˆ
β 1 ± tα / 2 , n − 2 se ( β 1 )
15 . 296 ± t .025 ,12 ( 9 . 421 )
15 .296 ± 2 . 145 ( 9 . 421 )
− 4 . 912 ≤ β 1 ≤ 35 . 504
d) The normality plot of the residuals is satisfactory. However, the plot of residuals versus run order
exhibits a strong downward trend. This could indicate that there is another variable should be included in the
model, one that changes with time.
40
30
5
20
10
Residual
Residual
0
0
-10
-20
-30 -5
-40
2 4 6 8 10 12 14 16 920 930 940
Observation Order Fitted Value
Image 96: 11-75 a)
940
y
930
920
920 930 940
x
ˆ
b) y = 33.3 + 0.9636 x
c) Predictor Coef SE Coef T P
Constant 33.3 171.7 0.19 0.851
x 0.9639 0.1848 5.22 0.001
S = 4.805 R-Sq = 77.3% R-Sq(adj) = 74.4%
Analysis of Variance
Source DF SS MS F P
Regression 1 628.18 628.18 27.21 0.001
Residual Error 8 184.72 23.09
Total 9 812.90
Reject the hull hypothesis and conclude that the model is significant. 77.3% of the variability is explained
by the model.
d) H 0 : β1 = 1
H 1 : β1 ≠ 1 α=.05
ˆ
β 1 − 1 0.9639 − 1
t0 = = = −0.1953
ˆ
se( β 1 ) 0.1848
t a / 2,n − 2 = t .025,8 = 2.306
Since t 0 > −t a / 2,n − 2 , we cannot reject Ho and we conclude that there is not enough evidence to reject the
claim that the devices produce different temperature measurements. Therefore, we assume the devices
produce equivalent measurements.
e) The residual plots to not reveal any major problems.
2
1
Normal Score
1
Residual
0
0
-1 -1
-2
-5 0 5 2 3 4 5 6 7 8
Residual Fitted Value
Image 97: Chapter 12 Selected Problem Solutions
Section 12-1
10 223 553
12-1. a) X ′X = 223 5200.9 12352
553 12352 31729
1916.0
X ′y = 43550.8
104736.8
171.054
b) ˆ = 3.713 , so y = 171.054 + 3.714 x − 1.126 x
β ˆ
1 2
− 1.126
c) y = 171.054 + 3.714(18) − 1.126(43) = 189.481
ˆ
12-5. Predictor Coef StDev T P
Constant 33.449 1.576 21.22 0.000
xl -0.054349 0.006329 -8.59 0.000
x6 1.0782 0.6997 1.54 0.138
S = 2.834 R-Sq = 82.9% R-Sq(adj) = 81.3%
Analysis of Variance
Source DF SS MS F P
Regression 2 856.24 428.12 53.32 0.000
Error 22 176.66 8.03
Total 24 1032.90
a) ˆ
y = 33.4491 − 0.05435x1 + 1.07822 x2
b) σ 2 = 8.03
ˆ
c) ˆ
y = 33.4491 − 0.05435(300) + 1.07822(2) = 19.30 mpg.
12-7. Predictor Coef SE Coef T P
Constant 383.80 36.22 10.60 0.002
Xl -3.6381 0.5665 -6.42 0.008
X2 -0.11168 0.04338 -2.57 0.082
S = 12.35 R-Sq = 98.5% R-Sq(adj) = 97.5%
Analysis of Variance
Source DF SS MS F P
Regression 2 29787 14894 97.59 0.002
Residual Error 3 458 153
Total 5 30245
a) y = 383.80 − 3.6381x1 − 0.1119 x2
ˆ
ˆ ˆ ˆ
b) σ = 153.0 , se( β 0 ) = 36.22 , se( β1 ) = 0.5665 , and se( β 2 ) = .04338
ˆ2
c) y = 383 . 80 − 3 . 6381 ( 25 ) − 0 . 1119 (1000 ) = 180 . 95
ˆ
d) Predictor Coef SE Coef T P
Constant 484.0 101.3 4.78 0.041
Xl -7.656 3.846 -1.99 0.185
X2 -0.2221 0.1129 -1.97 0.188
X1X2 0.004087 0.003871 1.06 0.402
S = 12.12 R-Sq = 99.0% R-Sq(adj) = 97.6%
Analysis of Variance
Source DF SS MS F P
Regression 3 29951.4 9983.8 67.92 0.015
Residual Error 2 294.0 147.0
Total 5 30245.3
y = 484 . 0 − 7 . 656 x1 − 0 . 222 x 2 − 0 . 0041 x12
ˆ
![Image 98: e) ˆ ˆ ˆ ˆ ˆ
σ 2 = 147.0 , se( β 0 ) = 101.3 , se( β1 ) = 3.846 , se( β 2 ) = 0.113 and se( β12 ) = 0.0039
f) y = 484 . 0 − 7 . 656 ( 25 ) − 0 . 222 (1000 ) − 0 . 0041 ( 25 )(1000 ) = − 31 . 3
ˆ
The predicted value is smaller
12-9. Predictor Coef SE Coef T P
Constant 47.17 49.58 0.95 0.356
xl -9.735 3.692 -2.64 0.018
x2 0.4283 0.2239 1.91 0.074
x3 18.237 1.312 13.90 0.000
S = 3.480 R-Sq = 99.4% R-Sq(adj) = 99.3%
Analysis of Variance
Source DF SS MS F P
Regression 3 30532 10177 840.55 0.000
Residual Error 16 194 12
Total 19 30725
a) y = 47 174 − .9 7352 x1 + .0 4283x 2 + 18 2375x 3
. .
b) σ 2 = 12
ˆ
c) ˆ ˆ ˆ ˆ
se( β 0 ) = 49.5815 , se( β1 ) = 3.6916 , se ( β 2 ) = 0 . 2239 , and se( β 3 ) = 1.312
d) y = 47 174 − .9 7352 14.5) + 0.4283(220) + 18.2375(5) = 9143
. ( .
Section 12-2
12-13. n = 10, k = 2, p = 3, α = 0.05
H 0 : β1 = β 2 = ... = β k = 0
H 1 : β j ≠ 0 for at least one j
(1916) 2
SST = 371595.6 − = 4490
10
∑ yi 1030
X' y = ∑ xi1 yi = 21310
∑ xi 2 yi 44174
1916
â' X' y = [171.054 3.713 − 1.126] 43550.8 = 371535.9
ˆ
104736.8
2
1916
SS R = 371535.9 − = 4430.38
10
SS E = SST − SS R = 4490 − 4430.38 = 59.62
SS R
4430.38 / 2
f0 = k
SS E
= = 260.09
n− p 59.62 / 7
f 0.05, 2, 7 = 4.74
f 0 > f 0.05, 2, 7
Reject H0 and conclude that the regression model is significant at α = 0.05.
b) H 0 : β1 = 0 β2 = 0
](
Image 99: H 1 : β1 ≠ 0 β2 ≠ 0
ˆ
β1 ˆ
β2
t0 = t0 =
ˆ
se( β ) ˆ
se( β 2 )
1
3.713 − 1.126
= = 19.20 = = −13.08
0.1934 0.0861
t α / 2,7 = t.025,7 = 2.365
Reject H0 Reject H0
Both regression coefficients are significant
12-17. a) H 0 : β1 = β 6 = 0
H1 : at least one β ≠ 0
f 0 = 53.3162
fα , 2, 22 = f .05, 2, 22 = 3.44
f 0 > fα , 2, 22
Reject H0 and conclude regression model is significant at α = 0.05
b) H 0 : β1 = 0
H 1 : β1 ≠ 0
t0 = −8.59
t.025, 25 − 3 = t.025, 22 = 2.074
| t0 |> tα / 2, 22 , Reject H0 and conclude β1 is significant at α = 0.05
H0 : β6 = 0
H1 : β 6 ≠ 0
α = 0.05
t 0 = 1.5411
| t0 |> tα / 2, 22 ,
/ Do not reject H0, conclude that evidence is not significant to state β6 is significant at α = 0.05.
No, only x1 contributes significantly to the regression.
12-21. a) H 0 : β1 = β 2 = β12 = 0
H1 at least one βj ≠ 0
α = 0.05
f 0 = 67.92
fα ,3, 2 = f.05,3, 2 = 19.16
f 0 > fα ,3, 2
/
Reject H0
b) H 0 : β 12 = 0
H 1 : β12 ≠ 0
α = 0.05
Image 100: SSR ( β 12 | β 1 , β 2 ) = 29951 .4 − 29787 = 164 .4
SSR 164 .4
f0 = = = 1.07
MS E 153
f .05 ,1, 2 = 18 .51
f 0 > fα ,1, 2
/
Do not reject H0
c) σ 2 = 147.0
ˆ
σ2 (no interaction term) = 153.0
MSE ( σ 2 ) was reduced in the interaction term model due to the addition of this term.
12-23. a) H 0 : β1 = β 2 = β 3 = 0 for all j
H1 : β j ≠ 0 for at least one j
f 0 = 840.55
f.05,3,16 = 3.24
f 0 > fα ,3,16
Reject H0 and conclude regression is significant at α = 0.05
b) α = 0.05 t α / 2 , n − p = t. 025,16 = 2. 12
H 0 : β1 = 0 β2 = 0 β3 = 0
H1: β1 ≠ 0 β2 ≠ 0 β3 ≠ 0
t 0 = −2.637 t0 = 1.91 t 0 = 13. 9
| t 0 | > t α / 2 ,16 | t 0 | > t α / 2 ,16
/ | t 0 | > t α / 2 ,16
Reject H0 Do not reject H0 Reject H0
Sections 12-3 and 12-4
12-27. a) − 0.00657 ≤ β 8 ≤ −0.00122
b) σ 2 x '0 ( X' X) −1 x 0 = 0.497648 = se( µ Y | x0 )
ˆ ˆ
c) µY |x0 = −7.63449 + 0.00398(2000) + 0.24777(60) − 0.00389(1800) = 8.19
ˆ
µY |x0 ± t.025 , 24 se( µ Y | x0 )
ˆ ˆ
8.19 ± ( 2.064)(0.497648)
8.19 ± 1.03
7.16 ≤ µY |x0 ≤ 9.22
12-29. a) 95 % CI on coeficients
ˆ
β 1 ± t a / 2,n − p ( β 1 )
0.0972 ≤ β 1 ≤ 1.4174
− 1.9646 ≤ β 2 ≤ 17.0026
− 1.7953 ≤ β 3 ≤ 6.7613
− 1.7941 ≤ β 4 ≤ 0.8319
Image 101: b) µ Y | x = 290.44
ˆ 0 se( µY | x0 ) = 7.61
ˆ t.025, 7 = 2.365
µ Y | x0 ± tα / 2,n − p se( µ Y | x0 )
ˆ ˆ
290.44 ± (2.365)(7.61)
272.44 ≤ µ Y | x0 ≤ 308.44
′
c) y 0 ± tα / 2,n − p σ 2 (1 + x 0 ( X′X) −1 x 0 )
ˆ ˆ
290.44 ± 2.365(14.038)
257.25 ≤ y0 ≤ 323.64
12-31 a)95% Confidence Interval on coefficients
− 0.595 ≤ β 2 ≤ 0.535
0.229 ≤ β 3 ≤ 0.812
− 0.216 ≤ β 4 ≤ 0.013
− 7.982 ≤ β 5 ≤ 2.977
b) µ Y | x = 8.99568
ˆ 0 se( µ Y | x0 ) = 0.472445
ˆ t .025,14 = 2.145
µY | x0 ± tα / 2, n − p se( µY | x0 )
ˆ ˆ
8.99568 ± (2.145)(0.472445)
7.982 ≤ µY | x0 ≤ 10.009
c) y0 = . 99568
8 se( y 0 ) = 1.00121
ˆ
8.99568 ± 2.145(1.00121)
6.8481 ≤ y0 ≤ 11.143
12-35. a) 0. 3882 ≤ βPts ≤ 0. 5998
b) y = −5.767703 + 0.496501x Pts
ˆ
c) 0.4648 ≤ β Pts ≤ 0.5282
d) The simple linear regression model has the shorter interval. Yes, the simple linear regression model in this case is
preferable.
Section 12-5
2
12-37. a) r = 0.82897
b) Normality assumption appears valid.
Image 102: Normal Probability Plot of the Residuals
(response is y)
5
Residual
0
-5
-2 -1 0 1 2
Normal Score
c) Assumption of constant variance appears reasonable.
Residuals Versus x6 Residuals Versus xl
(response is y) (response is y)
5 5
Residual
Residual
0 0
-5 -5
1 2 3 4 100 200 300 400 500
x6 xl
Residuals Versus the Fitted Values
(response is y)
5
Residual
0
-5
10 20 30
Fitted Value
d) Yes, observations 7, 10, and 18
12-39. a) r 2 = 0.985
b) r 2 = 0.990
r2 increases with addition of interaction term. No, adding additional regressor will always increase r2
12-41 a) There is some indication of nonconstant variance since the residuals appear to “fan out” with increasing
values of y.
Image 103: Residual Plot for y
8
5
Residuals
2
-1
-4
-7
0 40 80 120 160 200 240
Predicted
b)
Source Sum of Squares DF Mean Square F-Ratio P-value
Model 30531.5 3 10177.2 840.546 .0000
Error 193.725 16 12.1078
Total (Corr.) 30725.2 19
R-squared = 0.993695 Stnd. error of est. = 3.47963
R-squared (Adj. for d.f.) = 0.992513 Durbin-Watson statistic = 1.77758
R 2 = 0 . 9937 or 99.37 %;
2
R Adj = 0 . 9925 or 99.25%;
c) Model fitting results for: log(y)
Independent variable coefficient std. error t-value sig.level
CONSTANT 6.22489 1.124522 5.5356 0.0000
x1 -0.16647 0.083727 -1.9882 0.0642
x2 -0.000228 0.005079 -0.0448 0.9648
x3 0.157312 0.029752 5.2875 0.0001
R-SQ. (ADJ.) = 0.9574 SE= 0.078919 MAE= 0.053775 DurbWat= 2.031
Previously: 0.0000 0.000000 0.000000 0.000
20 observations fitted, forecast(s) computed for 0 missing val. of dep. var.
y ∗ = 6.22489 − 016647 x1 − 0.000228x 2 + 0.157312 x 3
.
Image 104: d)
Residual Plot for log(y)
0.1
0.05
Residuals
0
-0.05
-0.1
-0.15
4 4.3 4.6 4.9 5.2 5.5
Predicted
Plot exhibits curvature
There is curvature in the plot. The plot does not give much more information as to which model is
preferable.
e)
Residual Plot for log(y)
0.1
0.05
Residuals
0
-0.05
-0.1
-0.15
3.3 5.3 7.3 9.3 11.3
x3
Plot exhibits curvature
Variance does not appear constant. Curvature is evident.
f)
Model fitting results for: log(y)
Independent variable coefficient std. error t-value sig.level
CONSTANT 6.222045 0.547157 11.3716 0.0000
x1 -0.198597 0.034022 -5.8374 0.0000
x2 0.009724 0.001864 5.2180 0.0001
1/x3 -4.436229 0.351293 -12.6283 0.0000
R-SQ. (ADJ.) = 0.9893 SE= 0.039499 MAE= 0.028896 DurbWat= 1.869
Previously: 0.9574 0.078919 0.053775 2.031
20 observations fitted, forecast(s) computed for 0 missing val. of dep. var.
Analysis of Variance for the Full Regression
Source Sum of Squares DF Mean Square F-Ratio P-value
Model 2.75054 3 0.916847 587.649 .0000
Error 0.0249631 16 0.00156020
Total (Corr.) 2.77550 19
R-squared = 0.991006 Stnd. error of est. = 0.0394993
R-squared (Adj. for d.f.) = 0.98932 Durbin-Watson statistic = 1.86891
Image 105: Residual Plot for log(y)
0.08
0.05
Residuals
0.02
-0.01
-0.04
-0.07
3.8 4.1 4.4 4.7 5 5.3
Predicted
Using 1/x3
The residual plot indicates better conformance to assumptions.
Curvature is removed when using 1/x3 as the regressor instead of x3 and the log of the response data.
Section 12-6
2
12-47. a) y = −1.633 + 1.232 x − 1.495 x
ˆ
b) f0 = 1858613, reject H0
c) t0 = −601.64, reject H 0
d) Model is acceptable, observation number 10 has large leverage.
Residuals Versus x
Residuals Versus the Fitted Values
(response is y)
(response is y)
1
1
Residual
0
Residual
0
-1 -1
0.0 0.5 1.0 1.5 2.0 2.5 -7 -6 -5 -4 -3 -2 -1 0
x Fitted Value
Normal Probability Plot of the Residuals
(response is y)
1
Residual
0
-1
-1 0 1
Normal Score
Image 106: x−x
12-49. y = 759.395 − 90.783x'−47.166( x' ) 2 , where
ˆ x' =
Sx
285 − 297.125
a) At x = 285 x' = = −1.016
11.9336
y = 759.395 − 90.783(−1.106) − 47.166(−1.106) 2 = 802.943
ˆ psi
b) y = 759.395 − 90.783( x11.9336 ) − 47.166(
ˆ − 297.125
11.9336 )
x − 297.125 2
y = 759.395 − 7.607( x − 297.125) − 0.331( x − 297.125) 2
ˆ
y = −26204.14 + 189.09 x − 0.331x 2
ˆ
c) They are the same.
d) y ' = 0.385 − 0.847 x'−0.440( x' ) 2
ˆ
y− y x− x
where y ' = and x' =
Sy Sx
The "proportion" of total variability explained is the same for both standardized and un-standardized models.
2
Therefore, R is the same for both models.
y− y x− x
y ' = β 0 + β1∗ x'+ β11 ( x' ) 2
∗ ∗
where y' = and x' = y ' = β 0 + β1∗ x'+ β11 ( x' ) 2
∗ ∗
Sy Sx
12-51 a) Predictor Coef SE Coef T P
Constant -1.769 1.287 -1.37 0.188
xl 0.4208 0.2942 1.43 0.172
x2 0.2225 0.1307 1.70 0.108
x3 -0.12800 0.07025 -1.82 0.087
x1x2 -0.01988 0.01204 -1.65 0.118
x1x3 0.009151 0.007621 1.20 0.247
x2x3 0.002576 0.007039 0.37 0.719
x1^2 -0.01932 0.01680 -1.15 0.267
x2^2 -0.00745 0.01205 -0.62 0.545
x3^3 0.000824 0.001441 0.57 0.575
S = 0.06092 R-Sq = 91.7% R-Sq(adj) = 87.0%
Analysis of Variance
Source DF SS MS F P
Regression 9 0.655671 0.072852 19.63 0.000
Residual Error 16 0.059386 0.003712
Total 25 0.715057
y = −1.769 + 0.421x1 + 0.222 x2 − 0.128 x3 − 0.02 x1 x2 + 0.009 x1 x3 +
ˆ
2 2 2
0.003x2 x3 − 0.019 x1 − 0.007 x2 + 0.001x3
b) H0 : all β 1 = β 2 = β 3 = Κ = β 33 = 0
H1: at least 1 β j ≠ 0
f 0 = 19.628
f.05,9,16 = 2.54
f 0 > fα ,9,16
Reject H0 and conclude that the model is significant at α = 0.05
c) Model is acceptable.
d) H 0 : β11 = β 22 = β 33 = β12 = β13 = β 23 = 0
Image 107: H1: at least one βij ≠ 0
SS R ( β 11 , β 22 , β 33 , β12 , β 13 , β 23 | β 1 , β 2 , β 3 , β 0 ) / r 0.0359
f0 = = 6
= 1.612
MS E 0.003712
f .05, 6,16 = 2.74
f 0 > f .05,6,16
/
Do not reject H0
SS R ( β 12 , β13 , β 23 , β11 , β 22 , β 33 | β 1 , β 2 , β 3 , β 0 ) = SS R ( β1 , β 2 , β 3 , β 12 , β 13 , β 23 , β 11 , β 22 , β 33 | β 0 ) −
SS R ( β 1 β 2 β 3 | β 0 )
= 0.65567068 − 0.619763
= 0.0359
Reduced Model: y = β 0 + β 1 x1 + β 2 x 2 + β 3 x 3
12-55. a) The min. MSE equation is x1, x2, x3, x4, x5, x6, x7, x8
MS E = 6.58 cp = 5. 88
The min. Cp x5, x8, x10
C p = 5.02 MS E = 7.97
b) ˆ
y = 34.434 − 0.048x1
MSE = 8.81 C p = 5.55
c) Same as part b.
d) y = 0.341 + 2.862 x 5 + 0.246 x 8 − 0.010 x10
ˆ
MS E = 7.97 C p = 5.02
e) Minimum Cp and backward elimination result in the same model. Stepwise and forward selection
result in the same model. Because it is much smaller, the minimum Cp model seems preferable.
12-61. a) Min. Cp
y = −3.517 + 0.486 x1 − 0.156 x9
ˆ
C p = −1.67
b) Min MSE model is x1, x7, x9, MSE = 1. 67 , C p = −0.77
y = −.5 964 + . 495x1 + . 025x7 − . 163x9
0 0 0
2
c) Max. adjusted R2 model is x1, x7, x9, Adj. R = 0.98448 Yes, same as Min. MSE model.
Supplemental Exercises
12-65. a) H 0 : β 3∗ = β 4 = β 5 = 0
H1 : β j ≠ 0 for at least one j
α = 0.01
f0 = 1323. 62
f.01, 3, 36 = 4 . 38
f0 >> fα , 3, 36
Reject H0 and conclude regression is significant.
P-value < 0.00001
Image 108: b) α = 0.01 t.005, 36 = 2 . 72
H0 :β3∗ =0 H0:β4 = 0 H 0 :β5 = 0
H1: β3∗ ≠ 0 H1:β4 ≠ 0 H1:β5 ≠ 0
t0 = −1. 32 t 0 = 19. 97 t 0 = 2 . 48
| t 0 | > t α / 2 , 36
/ | t 0 | > t α / 2 , 36 | t 0 | > tα / 2 , 36
/
Do not reject H0 Reject H0 Do not reject H0
Only regressor x4 is significant
c) Curvature is evident in the residuals vs. regressor plots from this model.
12-67. a) y = −0.908 + 5.482 x1 + 1.126 x2 − 3.920 x3 − 1.143x4
ˆ
b) H 0 : β1 = β 2 = β 3 = β 4 = 0
H1 : β j ≠ 0 for at least one j
α = 0.05
f 0 = 109.02
f.05, 4,19 = 2.90
f 0 >> fα , 4,19
Reject H0 and conclude regression is significant at α = 0.05.
α = 0.05 t. 025,19 = 2 . 093
H 0 : β1 = 0 H0 : β2 = 0 H 0 : β3 = 0 H0 : β4 = 0
H 1 : β1 ≠ 0 H1 : β 2 ≠ 0 H1 : β 3 ≠ 0 H1 : β 4 ≠ 0
t 0 = 11.27 t0 = 14.59 t 0 = −6. 98 t 0 = −8. 11
| t 0 | > t α / 2 ,19 | t 0 | > t α / 2 ,19 | t 0 | > t α / 2 ,19 | t 0 | > t α / 2 ,19
Reject H0 Reject H0 Reject H0 Reject H0
c) The residual plots are more pleasing than those in Exercise 12-66.
12-69. a) y = −3982.1 + 1.0964x1 + 0.1843x3 + 3.7456x4 + 0.8343x5 − 16.2781x6
ˆ
MS E ( p) = 694.93 C p = 5.62
b) y = −4280.2 + 1.442x1 + 0.209x3 + 0.6467x5 − 17.5103x6
ˆ
MS E ( p) = 714.20 C p = 5.57
c) Same as model b.
d) Models from parts b. and c. are identical. Model in part a. is the same with x4 added in.
MSE model in part a. = 694.93 C p = 5.62
MSE model in parts b.&c. = 714.20 C p = 5.57
12-71. ˆ∗
a) VIF(β3 ) = 51.86
ˆ
VIF ( β 4 ) = 9.11
ˆ
VIF ( β ) = 28.99
5
Yes, VIFs for x and x5 exceed 10.
3
b) Model from Exercise 12-65: y = 19.69 − 1.27 x3 + 0.005 x4 + 0.0004 x5
ˆ
Image 110: Chapter 13 Selected Problem Solutions
Section 13-2
13-1. a) Analysis of Variance for STRENGTH
Source DF SS MS F P
COTTON 4 475.76 118.94 14.76 0.000
Error 20 161.20 8.06
Total 24 636.96
Reject H0 and conclude that cotton percentage affects mean breaking strength.
b) Tensile strength seems to increase to 30% cotton and declines at 35% cotton.
25
STRENGTH
15
5
15 20 25 30 35
COTTON
c) The normal probability plot and the residual plots show that the model assumptions are reasonable.
Residuals Versus the Fitted Values
(response is STRENGTH)
Normal Probability Plot of the Residuals
(response is STRENGTH)
6
6
5
5
4
4
3
3
2
2
Residual
Residual
1
1
0 0
-1 -1
-2 -2
-3 -3
-4 -4
10 15 20 -2 -1 0 1 2
Fitted Value Normal Score
Residuals Versus COTTON
(response is STRENGTH)
6
5
4
3
2
Residual
1
0
-1
-2
-3
-4
15 25 35
COTTON
13-3. a) Analysis of Variance for STRENGTH
Source DF SS MS F P
TECHNIQU 3 489740 163247 12.73 0.000
Error 12 153908 12826
Total 15 643648
Image 111: Reject H0. Techniques affect the mean strength of the concrete.
b) P-value ≅ 0
c) Residuals are acceptable
Residuals Versus TECHNIQU Residuals Versus the Fitted Values
(response is STRENGTH) (response is STRENGTH)
200 200
100 100
Residual
Residual
0 0
-100 -100
-200 -200
1 2 3 4 2650 2750 2850 2950 3050 3150
TECHNIQU Fitted Value
Normal Probability Plot of the Residuals
(response is STRENGTH)
2
1
Normal Score
0
-1
-2
-200 -100 0 100 200
Residual
13-5. a) Analysis of Variance for CONDUCTIVITY
Source DF SS MS F P
COATINGTYPE 4 1060.5 265.1 16.35 0.000
Error 15 243.3 16.2
Total 19 1303.8
Reject H0 ; P-value ≅ 0.
b) There is some indication that the variability of the response may be increasing as the mean response
increases. There appears to be an outlier on the normal probability plot.
Residuals Versus COATINGT
(response is CONDUCTI)
Residuals Versus the Fitted Values
(response is CONDUCTI)
5
5
0
Residual
0
Residual
-5
-5
-10
-10
1 2 3 4 5 130 135 140 145
COATINGT Fitted Value
Image 112: Normal Probability Plot of the Residuals
(response is CONDUCTI)
2
1
Normal Score
0
-1
-2
-10 -5 0 5
Residual
c) 95% Confidence interval on the mean of coating type 1.
MSE MSE
y1 − t 0.025,15 ≤ µ i ≤ y1 + t 0.015,15
n n
16.2 16.2
145.00 − 2.131 ≤ µ1 ≤ 145.00 + 2.131
4 4
140.71 ≤ µ1 ≤ 149.29
d.) 99% confidence interval on the difference between the means of coating types 1 and 4.
2MSE 2MSE
y1 − y4 − t 0.005,15 ≤ µ1 − µ 4 ≤ y1 − y 4 + t 0.005,15
n n
2(16.2) 2(16.2)
(145.00 − 129.25) − 2.947 ≤ µ1 − µ 4 ≤ (145.00 − 129.25) − 2.947
4 4
7.36 ≤ µ1 − µ 4 ≤ 24.14
13-9. a) Analysis of Variance for STRENGTH
Source DF SS MS F P
AIRVOIDS 2 1230.3 615.1 8.30 0.002
Error 21 1555.8 74.1
Total 23 2786.0
Reject H0
b) P-value = 0.002
c) The residual plots show that the assumptions of equality of variance is reasonable. The normal probability
plot has some curvature in the tails.
Image 113: Residuals Versus the Fitted Values
(response is STRENGTH)
10
Residual
0
-10
75 85 95
Fitted Value
Residuals Versus AIRVOIDS
(response is STRENGTH)
10
Residual
0
-10
1 2 3
AIRVOIDS
Normal Probability Plot of the Residuals
(response is STRENGTH)
2
1
Normal Score
0
-1
-2
-10 0 10
Residual
d) 95% Confidence interval on the mean of retained strength where there is a high level of air voids
MSE MSE
y3 − t 0.025, 21 ≤ µ i ≤ y3 + t 0.015, 21
n n
74.1 74.1
8.229 − 2.080 ≤ µ 3 ≤ 8.229 + 2.080
8 8
69.17 ≤ µ1 ≤ 81.83
e) 95% confidence interval on the difference between the means of retained strength at the high level and the
low levels of air voids.
2MSE 2MSE
y1 − y3 − t 0.025,21 ≤ µ1 − µ 3 ≤ y1 − y3 + t 0.025,21
n n
2(74.1) 2(74.1)
(92.875 − 75.5) − 2.080 ≤ µ1 − µ 4 ≤ (92.875 − 75.5) − 2.080
8 8
8.42 ≤ µ1 − µ 4 ≤ 26.38
Image 114: Section 13-3
13-21 a) Analysis of Variance for OUTPUT
Source DF SS MS F P
LOOM 4 0.3416 0.0854 5.77 0.003
Error 20 0.2960 0.0148
Total 24 0.6376
Reject H0, and conclude that there are significant differences among the looms.
MS Treatments − MS E 0.0854 − 0.0148
b) σ τ2 =
ˆ = = 0.01412
n 5
c) σ = MS E = 0.0148
ˆ2
d) Residuals plots are acceptable
Residuals Versus LOOM Residuals Versus the Fitted Values
(response is OUTPUT) (response is OUTPUT)
0.2 0.2
0.1 Residual 0.1
Residual
0.0 0.0
-0.1 -0.1
-0.2 -0.2
1 2 3 4 5 3.8 3.9 4.0 4.1
LOOM Fitted Value
Normal Probability Plot of the Residuals
(response is OUTPUT)
2
1
Normal Score
0
-1
-2
-0.2 -0.1 0.0 0.1 0.2
Residual
Section 13-4
13-25. a) Analysis of Variance for SHAPE
Source DF SS MS F P
NOZZLE 4 0.102180 0.025545 8.92 0.000
VELOCITY 5 0.062867 0.012573 4.39 0.007
Error 20 0.057300 0.002865
Total 29 0.222347
Reject H0, and conclude that nozzle type affects the mean shape measurement.
Image 115: 1.15
1.15
1.05 1.05
SHAPE
SHAPE
0.95 0.95
0.85 0.85
0.75 0.75
11.73 14.37 16.59 20.43 23.46 28.74 1 2 3 4 5
VELOCITY NOZZLE
b) Fisher's pairwise comparisons
Family error rate = 0.268
Individual error rate = 0.0500
Critical value = 2.060
Intervals for (column level mean) - (row level mean)
1 2 3 4
2 -0.15412
0.01079
3 -0.20246 -0.13079
-0.03754 0.03412
4 -0.24412 -0.17246 -0.12412
-0.07921 -0.00754 0.04079
5 -0.11412 -0.04246 0.00588 0.04754
0.05079 0.12246 0.17079 0.21246
There are significant differences between nozzle types 1 and 3, 1 and 4, 2 and 4, 3 and 5,
and 4 and 5.
c) The residual analysis shows that there is some inequality of variance. The normal probability plot is
acceptable.
Residuals Versus VELOCITY Residuals Versus NOZZLE
(response is SHAPE)
(response is SHAPE)
0.1
0.1
Residual
Residual
0.0 0.0
-0.1 -0.1
10 20 30 1 2 3 4 5
VELOCITY NOZZLE
Image 116: Residuals Versus the Fitted Values
(response is SHAPE)
0.1
Residual
0.0
-0.1
0.7 0.8 0.9 1.0
Fitted Value
Normal Probability Plot of the Residuals
(response is SHAPE)
2
1
Normal Score
0
-1
-2
-0.1 0.0 0.1
Residual
Supplemental Exercises
13-31. a)Analysis of Variance for RESISTANCE
Source DF SS MS F P
ALLOY 2 10941.8 5470.9 76.09 0.000
Error 27 1941.4 71.9
Total 29 12883.2
Reject H0, the type of alloy has a significant effect on mean contact resistance.
b) Fisher's pairwise comparisons
Family error rate = 0.119
Individual error rate = 0.0500
Critical value = 2.052
Intervals for (column level mean) - (row level mean)
1 2
2 -13.58
1.98
3 -50.88 -45.08
-35.32 -29.52
There are differences in the mean resistance for alloy types 1 and 3, and 2 and 3.
c) 99% confidence interval on the mean contact resistance for alloy 3
Image 117: MSE MSE
y3 − t 0.005,271 ≤ µ i ≤ y3 + t 0.005, 27
n n
71.9 71.9
140.4 − 2.771 ≤ µ 3 ≤ 140.4 − 2.771
10 10
132.97 ≤ µ1 ≤ 147.83
d) Variability of the residuals increases with the response. The normal probability plot has some
curvature in the tails, indicating a problem with the normality assumption. A transformation of the
response should be conducted.
Residuals Versus ALLOY Residuals Versus the Fitted Values
(response is RESISTAN)) (response is RESISTAN)
30 30
20 20
10 10
Residual
Residual
0 0
-10 -10
-20 -20
1 2 3 100 110 120 130 140
ALLOY Fitted Value
Normal Probability Plot of the Residuals
(response is RESISTAN)
2
1
Normal Score
0
-1
-2
-20 -10 0 10 20 30
Residual
13-35. a)Analysis of Variance for VOLUME
Source DF SS MS F P
TEMPERATURE 2 16480 8240 7.84 0.007
Error 12 12610 1051
Total 14 29090
Reject H0.
b) P-value = 0.007
c) Fisher's pairwise comparisons
Family error rate = 0.116
Individual error rate = 0.0500
Critical value = 2.179
Intervals for (column level mean) - (row level mean)
70 75
75 -16.7
72.7
80 35.3 7.3
124.7 96.7
Image 118: There are significant differences in the mean volume for temperature levels 70 and 80, and 75 and 80. The
highest temperature (80%) results in the smallest mean volume.
d)There are some relatively small differences in the variability at the different levels of temperature. The
variability decreases with the fitted values. There is an unusual observation on the normal probability plot.
Residuals Versus TEMPERAT Residuals Versus the Fitted Values
(response is VOLUME) (response is VOLUME)
50 50
0 0
Residual
Residual
-50 -50
70 75 80 1170 1180 1190 1200 1210 1220 1230 1240 1250
TEMPERAT Fitted Value
13-37. a) Analysis of Variance for PCTERROR
Source DF SS MS F P
ALGORITH 5 2825746 565149 6.23 0.000
PROJECT 7 2710323 387189 4.27 0.002
Error 35 3175290 90723
Total 47 8711358
Reject H0 , the algorithm is significant.
b) The residuals look acceptable, except there is one unusual point.
Residuals Versus PROJECT Residuals Versus ALGORITH
(response is PCTERROR) (response is PCTERROR)
1000 1000
500 500
Residual
Residual
0 0
-500 -500
1 2 3 4 5 6 7 8 1 2 3 4 5 6
PROJECT ALGORITH
Residuals Versus the Fitted Values
(response is PCTERROR)
1000
500
Residual
0
-500
0 500 1000
Fitted Value
Image 119: Normal Probability Plot of the Residuals
(response is PCTERROR)
2
1
Normal Score
0
-1
-2
-500 0 500 1000
Residual
c) The best choice is algorithm 5 because it has the smallest mean and a low variablity.
2
13-39 a) λ = 1 + 4 ( 2 σ ) = 3
2
σ
From Chart VIII with numerator degrees of freedom = a - 1 = 4, denominator degrees of freedom = a(n - 1)
= 15, β = 0.15, and the power = 1 - β = 0.85.
b)
n λ a(n - 1) β Power = 1 - β
5 3.317 20 0.10 0.90
The sample size should be approximately n = 5
Image 120: Chapter 14 Selected Problem Solutions
Section 14-3
14-1. a) Analysis of Variance for life
Source DF SS MS F P
material 2 10683.7 5341.9 7.91 0.002
temperat 2 39118.7 19559.4 28.97 0.000
materialtemperat 4 9613.8 2403.4 3.56 0.019
Error 27 18230.7 675.2
Total 35 77647.0
Main factors and interaction are all significant.
b)The mean life for material 2 is the highest at temperature level 1, in the middle at temperature
level 2 and the lowest at temperature level 3. This shows that there is an interaction.
Interaction Plot - Means for life
material
1
150 2
3
1
2
3
Mean
100
50
1 2 3
temperat
c) There appears to be slightly more variability at temperature 1 and material 1. The normal
probability plot shows that the assumption of normality is reasonable.
Normal Probability Plot of the Residuals
(response is life)
2
1
Normal Score
0
-1
-2
-50 0 50
Residual
Image 121: Residuals Versus temperat
Residuals Versus material
(response is life)
(response is life)
50
50
0
Residual
0
Residual
-50 -50
1 2 3 1 2 3
temperat material
14-3 a) H 0 : τ1 = τ 2 = 0
H 1 : at least one τ i ≠ 0
b) Analysis of Variance for current
Source DF SS MS F P
glasstyp 1 14450.0 14450.0 273.79 0.000
phostype 2 933.3 466.7 8.84 0.004
glasstypphostype 2 133.3 66.7 1.26 0.318
Error 12 633.3 52.8
Total 17 16150.0
Main effects are significant, the interaction is not significant. Glass type 1 and phosphor type 2
lead to the high mean current (brightness).
c) There appears to be slightly more variability at phosphor type 2 and glass type 2. The normal
plot of the residuals shows that the assumption of normality is reasonable.
Residuals Versus phostype Residuals Versus glasstyp
(response is current) (response is current)
15 15
10 10
5 5
Residual
Residual
0 0
-5 -5
-10 -10
1 2 3 1.0 1.5 2.0
phostype glasstyp
Residuals Versus the Fitted Values
(response is current)
15
10
5
Residual
0
-5
-10
220 230 240 250 260 270 280 290 300
Fitted Value
Image 122: 14-7 The ratio
Normal Probability Plot of the Residuals
(response is current)
2
1
Normal Score
0
-1
-2
-10 -5 0 5 10 15
Residual
y⋅i⋅ − y⋅ j⋅ − ( µ i − µ j )
T= has a t distribution with ab(n-1) degrees of freedom
2 MS E / n
Therefore, the (1-α)% confidence interval on the difference in two treatment means is
2MSE 2MSE
y⋅i⋅ − y⋅ j⋅ − t a / 2,ab(n−1) ≤ µi − µ j ≤ y⋅i⋅ − y⋅ j⋅ + t a / 2,ab( n−1)
n n
For exercise 14-6, the mean warping at 80% copper concentration is 21.0 and the mean warping at 60%
copper concentration is 18.88 a=4, b=4, n=2 and MSE=6.78. The degrees of freedom are (4)(4)(1)=16
2 6.78 2 6.78
(21.0 − 18.88) − 2.120 ≤ µ 3 − µ 2 ≤ (21.0 − 18.88) + 2.120
2 2
− 3.40 ≤ µ3 − µ 2 ≤ 7.64
Therefore, there is no significant differences between the mean warping values at 80% and 60% copper
concentration.
Section 14-4
14-11 Parts a. and b.
Analysis of Variance for strength
Source DF SS MS F P
hardwood 2 8.3750 4.1875 7.64 0.003
cookingtime 1 17.3611 17.3611 31.66 0.000
freeness 2 21.8517 10.9258 19.92 0.000
hardwoodcookingtime 2 3.2039 1.6019 2.92 0.075
hardwoodfreeness 4 6.5133 1.6283 2.97 0.042
cookingtimefreeness 2 1.0506 0.5253 0.96 0.399
Error 22 12.0644 0.5484
Total 35 70.4200
All main factors are significant. The interaction of hardwood freeness is also significant.
c) The residual plots show no serious problems with normality or equality of variance
Image 123: Residuals Versus freeness Residuals Versus cookingt
(response is strength) (response is strength)
Residual 1 1
Residual
0 0
-1 -1
400 450 500 550 600 650 1.5 1.6 1.7 1.8 1.9 2.0
freeness cookingt
Residuals Versus hardwood Residuals Versus the Fitted Values
(response is strength) (response is strength)
1 1
Residual
0
Residual
0
-1 -1
10 15 20 96 97 98 99 100 101
hardwood Fitted Value
Normal Probability Plot of the Residuals
(response is strength)
2
1
Normal Score
0
-1
-2
-1 0 1
Residual
Section 14-5
14-13 a) Analysis of Variance for life (coded units)
Source DF SS MS F P
speed 1 1332 1332 0.49 0.502
hardness 1 28392 28392 10.42 0.010
angle 1 20592 20592 7.56 0.023
speedhardness 1 506 506 0.19 0.677
speedangle 1 56882 56882 20.87 0.000
hardnessangle 1 2352 2352 0.86 0.377
Error 9 24530 2726
Total 15 134588
b) Estimated Effects and Coefficients for life (coded units)
Image 124: Term Effect Coef SE Coef T P
Constant 413.13 12.41 33.30 0.000
speed 18.25 9.12 12.41 0.74 0.483
hardness 84.25 42.12 12.41 3.40 0.009
angle 71.75 35.87 12.41 2.89 0.020
speedhardness -11.25 -5.63 12.41 -0.45 0.662
speedangle -119.25 -59.62 12.41 -4.81 0.001
hardnessangle -24.25 -12.12 12.41 -0.98 0.357
speedhardnessangle -34.75 -17.37 12.41 -1.40 0.199
ˆ
y
= 413.125 + 9.125x1 + 45.12x2 + 35.87x3 −59.62x13
c) Analysis of the residuals shows that all assumptions are reasonable.
Normal Probability Plot of the Residuals
(response is life)
2
1
Normal Score
0
-1
-2
-50 0 50
Residual
Residuals Versus angle Residuals Versus hardness
(response is life) (response is life)
50 50
Residual
Residual
0 0
-50 -50
-1 0 1 -1 0 1
angle hardness
Residuals Versus speed Residuals Versus the Fitted Values
(response is life) (response is life)
50 50
Residual
Residual
0 0
-50 -50
-1 0 1 250 350 450 550
speed Fitted Value
Image 125: 14-19. a) Factors A, B, C, and the interaction AB appear to be significant from the normal probability plot of the
effects.
Normal Probability Plot of the Effects
(response is yield, Alpha = .10)
A: factor_A
2 B B: factor_B
C: factor_C
A D: factor_D
C E: factor_E
AB
1
Normal Score
0
-1
-2
0 10 20 30
Effect
b)
Analysis of Variance for yield (coded units)
Term Effect Coef StDev Coef T P
Constant 30.5312 0.2786 109.57 0.000
factor_A 11.8125 5.9063 0.2786 21.20 0.000
factor_B 9.6875 4.8437 0.2786 17.38 0.000
factor_D -0.8125 -0.4063 0.2786 -1.46 0.164
factor_E 0.4375 0.2187 0.2786 0.79 0.444
factor_Afactor_B 7.9375 3.9687 0.2786 14.24 0.000
factor_Afactor_C 0.4375 0.2187 0.2786 0.79 0.444
factor_Afactor_D -0.0625 -0.0313 0.2786 -0.11 0.912
factor_Afactor_E 0.9375 0.4687 0.2786 1.68 0.112
factor_Bfactor_C 0.0625 0.0313 0.2786 0.11 0.912
factor_Bfactor_D -0.6875 -0.3437 0.2786 -1.23 0.235
factor_Bfactor_E 0.5625 0.2813 0.2786 1.01 0.328
factor_Cfactor_D 0.8125 0.4062 0.2786 1.46 0.164
factor_Cfactor_E 0.3125 0.1563 0.2786 0.56 0.583
factor_Dfactor_E -1.1875 -0.5938 0.2786 -2.13 0.049
Analysis of Variance for yield
Source DF Seq SS Adj SS Adj MS F P
Main Effects 5 11087.9 11087.9 2217.58 892.61 0.000
2-Way Interactions 10 536.3 536.3 53.63 21.59 0.000
Residual Error 16 39.7 39.7 2.48
Total 31 11664.0
The analysis confirms our findings from part a)
c) The normal probability plot of the residuals is satisfactory. However their variance appears to increase
as the fitted value increases.
Image 126: Normal Probability
.999
.99
Pr .95
ob .80
abi .50
lity .20
.05
.01
.001
-3 -2 -1 0 1 2 3
RESI1
Average: 0.0000000 Anderson-Darling Normality Test
StDev: 1.59479 A-Squared: 0.387
N: 32 P-Value: 0.368
Residuals Versus the Fitted Values
(response is yield)
2
Standardized Residual
1
0
-1
-2
0 10 20 30 40 50 60
Fitted Value
.
d) All plots support the constant variance assumption , although there is a very slight indication that
variability is greater at the high level of factor B.
Residuals Versus A Residuals Versus B
(response is yield) (response is yield)
2 2
Standardized Residual
Standardized Residual
1 1
0 0
-1 -1
-2 -2
-1 0 1 -1 0 1
A B
Image 127: Residuals Versus C Residuals Versus D
(response is yield) (response is yield)
2 2
Standardized Residual
Standardized Residual
1 1
0 0
-1 -1
-2 -2
-1 0 1 -1 0 1
C D
Residuals Versus E
(response is yield)
2
Standardized Residual
1
0
-1
-2
-1 0 1
E
e) The AB interaction appears to be significant. The interaction plot from MINITAB indicates that a high
level of A and of B increases the mean yield, while low levels of both factors would lead to a reduction in the
mean yield.
Interaction P lot for yield
55
A high
45
35 A low
M ean
25
15
-1 1
B
f.) To increase yield and therefor optimize the process, we would want to set A, B, and C at their high
levels.
g) It is evident from the cube plot that we should run the process with all factors set at their high level.
Image 128: Cube Plot - Means for yield
42.50, 5 62.25,5
32.75,5 52.50,5
1
B 16.00,3 20.75,2
1
C
7.25,2 10.25,3
-1 -1
-1 1
A
14-21
Normal Probability Plot for the Main Effects
ML Estimates
99
95
90 A
80 AB
70
Percent
60
50
40
30
20
10
5
B
1
-50 0 50
Data
b) Based on the normal probability plot of the effects, factors A, B and AB are significant.
The model would include these three factors.
ˆ
c) The estimated model is: y = 400 + 40.124 x1 − 32.75 x 2 + 26.625 x12
Image 129: Section 14-6
14-25 Model with four blocks
BLOCK A B C D var_1
1 -1 -1 -1 -1 190
1 1 -1 1 -1 181
1 -1 1 -1 1 187
1 1 1 1 1 180
2 1 -1 -1 -1 174
2 -1 -1 1 -1 177
2 1 1 -1 1 185
2 -1 1 1 1 187
3 -1 1 -1 -1 181
3 1 1 1 -1 173
3 -1 -1 -1 1 198
3 1 -1 1 1 179
4 1 1 -1 -1 183
4 -1 1 1 -1 188
4 1 -1 -1 1 172
4 -1 -1 1 1 199
Term Effect Coef
Constant 183.375
Block -1.625
factor_A -10.000 -5.000
factor_B -0.750 -0.375
factor_C -0.750 -0.375
factor_D 5.000 2.500
factor_Afactor_B 4.500 2.250
factor_Afactor_C 0.500 0.250
factor_Afactor_D -3.750 -1.875
factor_Bfactor_C -1.250 -0.625
factor_Bfactor_D -1.500 -0.750
factor_Cfactor_D 1.500 0.750
factor_Afactor_Bfactor_C -6.000 -3.000
factor_Afactor_Bfactor_D 4.750 2.375
factor_Afactor_Cfactor_D -0.250 -0.125
factor_Bfactor_Cfactor_D -2.000 -1.000
Term Effect Coef StDev Coef T P
Constant 183.375 1.607 114.14 0.000
Block -1.625 1.607 -1.01 0.336
factor_A -10.000 -5.000 1.607 -3.11 0.011
factor_B -0.750 -0.375 1.607 -0.23 0.820
factor_C -0.750 -0.375 1.607 -0.23 0.820
factor_D 5.000 2.500 1.607 1.56 0.151
Analysis of Variance for var_1
Source DF Seq SS Adj SS Adj MS F P
Blocks 1 42.25 42.25 42.25 1.02 0.336
Main Effects 4 504.50 504.50 126.13 3.05 0.069
Residual Error 10 413.00 413.00 41.30
Total 15 959.75
Factor A is the only significant factor.
14-29 a) Estimated Effects and Coefficients for y
Term Effect Coef StDev Coef T P
Constant 56.37 2.633 21.41 0.000
Block 1 15.63 4.560 3.43 0.014
2 -3.38 4.560 -0.74 0.487
Image 130: 3 -10.88 4.560 -2.38 0.054
A -45.25 -22.62 2.633 -8.59 0.000
B -1.50 -0.75 2.633 -0.28 0.785
C 14.50 7.25 2.633 2.75 0.033
AB 19.00 9.50 2.633 3.61 0.011
AC -14.50 -7.25 2.633 -2.75 0.033
BC -9.25 -4.63 2.633 -1.76 0.130
Analysis of Variance for y
Source DF Seq SS Adj SS Adj MS F P
Blocks 3 1502.8 1502.8 500.9 4.52 0.055
Main Effects 3 9040.2 9040.2 3013.4 27.17 0.001
2-Way Interactions 3 2627.2 2627.2 875.7 7.90 0.017
Residual Error 6 665.5 665.5 110.9
Total 15 13835.7
Factors A, C, AB, and AC are significant.
b) Analysis of the residuals shows that the model is adequate. There is more variability on the response
associated with the low setting of factor C, but that is the only problem.
Residuals Versus A
(response is y) Residuals Versus B
(response is y)
10
10
Residual
Residual
0 0
-10 -10
-1 0 1
-1 0 1
B
A
Residuals Versus C
(response is y)
10
Residual
0
-10
-1 0 1
C
Residuals Versus the Fitted Values Normal Probability Plot of the Residuals
(response is y) (response is y)
10 10
Residual
Residual
0 0
-10 -10
10 20 30 40 50 60 70 80 90 100 110 -2 -1 0 1 2
Fitted Value Normal Score
Image 131: c.) Some of the information from the experiment is lost because the design is run in 4 blocks. This causes us to
lose information on the ABC interaction even though we have replicated the experiment twice. If it is
possible to run the experiment in only 2 blocks, there would be information on all interactions.
d) To have data on all interactions, we could run the experiment so that each replicate is a block (therefore only
2 blocks).
Section 14-7
14-31 a) Factors A, B and D are active factors.
Normal Probability Plot of the Effects
(response is color, Alpha = .10)
D
BC
1 CE
AB
Normal Score
0 A
C
-1 E
AE
B
0 2 4
Effect
b) There are no serious problems with the residual plots. The normal probability plot has a little bit of
curvature at the low end and there is a little more variability at the lower and higher ends of the fitted values.
Normal Probability Plot of the Residuals
(response is var_1) Residuals Versus the Fitted Values
(response is var_1)
2
1.5
1 1.0
Normal Score
0.5
0 0.0
Residual
-0.5
-1
-1.0
-1.5
-2
-2.0
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Residual -2.5
-2 -1 0 1 2 3 4 5 6 7
Fitted Value
3
c) Part a. indicates that only A,B, and D are important. In these factors only, the design is a 2 with two
replicates.
Estimated Effects and Coefficients for var_1
Term Effect Coef StDev Coef T P
Constant 2.7700 0.2762 10.03 0.000
factor_A 1.4350 0.7175 0.2762 2.60 0.032
Image 132: factor_B -1.4650 -0.7325 0.2762 -2.65 0.029
factor_D 4.5450 2.2725 0.2762 8.23 0.000
factor_Afactor_B 1.1500 0.5750 0.2762 2.08 0.071
factor_Afactor_D -1.2300 -0.6150 0.2762 -2.23 0.057
factor_Bfactor_D 0.1200 0.0600 0.2762 0.22 0.833
factor_Afactor_Bfactor_D -0.3650 -0.1825 0.2762 -0.66 0.527
Analysis of Variance for var_1
Source DF Seq SS Adj SS Adj MS F P
Main Effects 3 99.450 99.4499 33.1500 27.15 0.000
2-Way Interactions 3 11.399 11.3992 3.7997 3.11 0.088
3-Way Interactions 1 0.533 0.5329 0.5329 0.44 0.527
Residual Error 8 9.767 9.7668 1.2208
Pure Error 8 9.767 9.7668 1.2208
Total 15 121.149
Factors A, B, D, AB and AD are significant.
Normal Probability Plot of the Residuals Residuals Versus the Fitted Values
(response is var_1) (response is var_1)
2
1
1
Normal Score
Residual
0 0
-1
-1
-2
-3 -2 -1 0 1 2 3 4 5 6
-1 0 1
Fitted Value
Residual
The normal probability plot and the plot of the residuals versus fitted values are satisfactory.
14-35 Since factors A, B, C, and E form a word in the complete defining relation, it can be verified that the
resulting design is two replicates of a 24-1 fractional factorial. This is different than the design that results
when C and E are dropped from the 26-2 in Table 14-28 which results in a full factorial because, the factors
ABDF do not form a word in the complete defining relation
14-37 Generators D=AB, E=AC for 25-2, Resolution III
A B C D E var_1
-1 -1 -1 1 1 1900
1 -1 -1 -1 -1 900
-1 1 -1 -1 1 3500
1 1 -1 1 -1 6100
-1 -1 1 1 -1 800
1 -1 1 -1 1 1200
-1 1 1 -1 -1 3000
1 1 1 1 1 6800
Image 133: Normal Probability Plot of the Standardized Effects
(response is var_1, Alpha = .10)
factor_B
1
factor_D
Normal Score
0 factor_A
factor_E
-1
0 10 20
Standardized Effect
Estimated Effects and Coefficients for var_1 (coded units)
Term Effect Coef SE Coef T P
Constant 3025.00 90.14 33.56 0.001
factor_A 1450.00 725.00 90.14 8.04 0.015
factor_B 3650.00 1825.00 90.14 20.25 0.002
factor_C -150.00 -75.00 90.14 -0.83 0.493
factor_D 1750.00 875.00 90.14 9.71 0.010
factor_E 650.00 325.00 90.14 3.61 0.069
Analysis of Variance for var_1 (coded units)
Source DF Seq SS Adj SS Adj MS F P
Main Effects 5 37865000 37865000 7573000 116.51 0.009
Residual Error 2 130000 130000 65000
Total 7 37995000
Factors A, B and D are significant.
Supplemental Exercises
14-41 a Estimated Effects and Coefficients for var_1 (coded units)
Term Effect Coef SE Coef T P
Constant 191.563 1.158 165.49 0.000
factor_A (PH) 5.875 2.937 1.158 2.54 0.026
factor_B (CC) -0.125 -0.062 1.158 -0.05 0.958
factor_Afactor_B 11.625 5.812 1.158 5.02 0.000
Analysis of Variance for var_1 (coded units)
Source DF Seq SS Adj SS Adj MS F P
Main Effects 2 138.125 138.125 69.06 3.22 0.076
2-Way Interactions 1 540.562 540.562 540.56 25.22 0.000
Residual Error 12 257.250 257.250 21.44
Pure Error 12 257.250 257.250 21.44
Total 15 935.938
The main effect of pH and the interaction of pH and Catalyst Concentration (CC) are significant at the 0.05
level of significance.
The model used is viscosity = 191.563 + 2.937x1 − 0.062x2 + 5.812x12
Image 134: b.) The interaction plot shows that there is a strong interaction. When Factor A is at its low level, the mean
response is large at the low level of B and is small at the high level of B. However, when A is at its high
level, the results are opposite.
Interaction Plot (data m eans) for var_1
200
A high
195
Mean
190
A low
185
-1 1
factor_B
c.) The plots of the residuals show that the equality of variance assumption is reasonable.
However, there is a large gap in the middle of the normal probability plot. Sometimes, this can
indicate that there is another variable that has an effect on the response but which is not included
in the experiment. For example, in this experiment, note that the replicates in each cell have two
pairs of values that are very similar, but there is a rather large difference in the mean values of the
two pairs. (Cell 1 has 189 and 192 as one pair and 198 and 199 as the other.)
Residuals Versus factor_B
(response is var_1)
Resid uals Versus factor_A
(res ponse is var_1)
5
5
Residual
Residual
0
0
-5 -5
-1 0 1 -1 0 1
factor_A
factor_B
R esid u als Versu s th e Fitted Valu es
(response is var_1)
N o r m a l P r o b a b i l it y P l o t o f th e R e s id u a l s 5
( r e s p o n s e is v a r _ 1 )
2
Residual
1
0
Normal Score
0
-1
-5
-2 185 190 195 20 0
-5 0 5 Fitte d V a lue
R e s id u a l
14-47 a) Term Effect
V -15.75
Image 135: F 8.75
P 10.75
G -25.00
VF 3.00
VP -8.00
VG -2.75
FP -6.00
FG 3.75
PG -19.25
VFP -1.25
VFG 0.50
VPG -1.50
FPG -12.50
VFPG -4.25
b)
Normal Probability Plot of the Effects
(response is Roughnes, Alpha = .10)
1
Normal Score
0
V
-1
PG
G
-20 -10 0 10
Effect
According to the probability plot, factors V, P, and G and, PG are possibly significant.
Estimated Effects and Coefficients for roughnes (coded units)
Term Effect Coef SE Coef T P
Constant 102.75 2.986 34.41 0.000
V -15.75 -7.87 2.986 -2.64 0.046
F 8.75 4.37 2.986 1.46 0.203
P 10.75 5.37 2.986 1.80 0.132
G -25.00 -12.50 2.986 -4.19 0.009
VF 3.00 1.50 2.986 0.50 0.637
VP -8.00 -4.00 2.986 -1.34 0.238
VG -2.75 -1.38 2.986 -0.46 0.665
FP -6.00 -3.00 2.986 -1.00 0.361
FG 3.75 1.88 2.986 0.63 0.558
PG -19.25 -9.63 2.986 -3.22 0.023
Analysis of Variance for roughnes (coded units)
Analysis of Variance for Roughnes (coded units)
Source DF Seq SS Adj SS Adj MS F P
Main Effects 4 4260.7 4260.7 1065.2 7.46 0.024
Image 136: 2-Way Interactions 6 2004.7 2004.7 334.1 2.34 0.184
Residual Error 5 713.5 713.5 142.7
Total 15 6979.0
y = 102.75 − 7.87 x1 + 5.37 x3 − 12.50 x 4 − 9.63 x34
ˆ
c) From the analysis, we see that water jet pressure (P), abrasive grain size (G), and jet traverse speed (V) are
significant along with the interaction of water jet pressure and abrasive grain size
d) The residual plots appear to indicate the assumption of constant variance may not be met. The
assumption of normality appears reasonable.
14-49 The design uses G=VPF as the generator.
Alias Structure
Normal Probability Plot of the Residuals
(response is Roughnes) Residuals Versus the Fitted Values
(response is Roughnes)
2
10
1
Normal Score
0
Residual
-1 0
-2
-10 0 10
Residual
-10
65 75 85 95 105 115 125 135 145
Fitted Value
Residuals Versus V
(response is Roughnes)
10
Residuals Versus F
(response is Roughnes)
10
Residual
0
Residual
0
-10
-1 0 1 -10
V -1 0 1
F
I + VPFG
Residuals Versus P Residuals Versus G
(response is Roughnes)
(response is Roughnes)
10
10
Residual
Residual
0
0
-10
-10
-1 0 1
-1 0 1
P
G
V + PFG
P + VFG
F + VPG
G + VPF
Image 137: VP + FG
VF + PG
VG + PF
Estimated Effects and Coefficients for C9 (coded units)
Term Effect Coef SE Coef T P
Constant 102.63 6.365 16.12 0.004
V -14.75 -7.37 6.365 -1.16 0.366
P -28.25 -14.12 6.365 -2.22 0.157
F -1.25 -0.62 6.365 -0.10 0.931
G -14.75 -7.38 6.365 -1.16 0.366
PG 17.75 8.88 6.365 1.39 0.298
Analysis of Variance for C9 (coded units)
Source DF Seq SS Adj SS Adj MS F P
Main Effects 4 2469.5 2469.5 617.4 1.90 0.373
2-Way Interactions 1 630.1 630.1 630.1 1.94 0.298
Residual Error 2 648.3 648.3 324.1
Total 7 3747.9
The results do not show any significant factors. A lot of the information is lost due to the half-
fraction of the design.
14-51 Design Generators: D = AB E = AC
Alias Structure
I + ABD + ACE + BCDE
A + BD + CE + ABCDE
B + AD + CDE + ABCE
C + AE + BDE + ABCD
D + AB + BCE + ACDE
E + AC + BCD + ABDE
BC + DE + ABE + ACD
BE + CD + ABC + ADE
Design
StdOrder A B C D E
1 -1 -1 -1 1 1
2 1 -1 -1 -1 -1
3 -1 1 -1 -1 1
4 1 1 -1 1 -1
5 -1 -1 1 1 -1
6 1 -1 1 -1 1
7 -1 1 1 -1 -1
8 1 1 1 1 1
Image 138: Chapter 15 Selected Problem Solutions
Section 15-2
15-1. 1. The parameter of interest is median of pH.
~
2. H 0 : µ = 7.0
~
3 H : µ ≠ 7.0
1
4. α=0.05
5. The test statistic is the observed number of plus differences or r+ = 8.
6. We reject H0 if the P-value corresponding to r+ = 8 is less than or equal to α=0.05.
7. Using the binomial distribution with n=10 and p=0.5, P-value = 2P(R≥8|p=0.5)=0.109
8. Conclusion: we cannot reject H0. There is not enough evidence to reject the manufacturer’s claim that
the median of the pH is 7.0
15-5 a. 1. The parameter of interest is the median compressive strength
~
2. H 0 : µ = 2250
~
3. H : µ > 2250
1
4. α=0.05
5. The test statistic is the observed number of plus differences or r+ = 7.
6. We reject H0 if the P-value corresponding to r+ = 7 is less than or equal to α=0.05.
7. Using the binomial distribution with n=12 and p=0.5, P-value = P(R≥7|p=0.5)=.3872
8.Conclusion: cannot reject H0. The median compressive strength is not more than 2250.
b. 1. The parameter of interest is the median compressive strength
~
2. H 0 : µ = 2250
~
3. H : µ > 2250
1
4. α=0.05
5. Test statistic is z =
r + − 0.5n
0
0.5 n
6. We reject H0 if the |Z0| > Z0.025 = 1.96
7. Computation: z = 7 − 0.5(12) = 0.577
0
0.5 12
8. Conclusion: cannot reject H0. The median compressive strength is not more than 2250.
The P-value = 1-Φ(0.58) = 1-.7190 = 0.281
15-7. 1. The parameter of interest is the median titanium content
~
2. H 0 : µ = 8.5
3. H : µ ~ ≠ 8.5
1
4. α=0.05
r + − 0.5n
5. Test statistic is z0 =
0.5 n
6. We reject H0 if the |Z0| > Z0.025 = 1.96
7. Computation: z = 7 − 0.5(20) = −1.34
0
0.5 20
8. Conclusion: cannot reject H0. The median titanium content is 8.5.
The P-value = 2P(|Z|>1.34) = 0.1802.
15-9. 1. The parameters of interest are the median hardness readings for the two tips
~
2. H 0 : µ D = 0
~
3. H : µ ≠ 0
1 D
4. α=0.05
Image 139: 5. The test statistic is r = min( r+ , r-).
6. Since α=0.05 and n=8, Appendix,= Table VII gives the critical value of r0.05 =2. We will reject
H0 in favor of H1 if r ≤ 1.
7. r+ = 6 and r - = 2 and so r=min(6,2) = 2
8. Conclusion: cannot reject H0. There is not significant difference in the tips.
15-11. 1. The parameters of interest are the median drying times for the two formulations.
~
2. H 0 : µ D = 0
3. H : µ ~ ≠0
1 D
4. α=0.05
r + − 0.5n
5. Test statistic is z0 =
0.5 n
6. We reject H0 if the |Z0| > Z0.025 = 1.96
7. Computation: z = 15 − 0.5(20) = 2.24
0
0.5 20
8. Conclusion: reject H0. There is a difference in the median drying times between the two formulations.
The P-value = 2P(|Z|>2.24) = 0.025.
15-17. a) α = P(Z>1.96) = 0.025
b) β = P X
= 1 . 96 | µ = 1 = P ( Z < − 1 . 20 ) = 0 . 115
σ / n
c) The sign test that rejects if R− ≤ 1 has α = 0.011 based on the binomial distribution.
d) β = P(R − > 1 | µ = 1) = 0.1587 . Therefore, R− has a binomial distribution with p=0.1587
and n = 10 when µ = 1. Then β = 0.487. The value of β is greater for the sign test than for the normal
test because the Z-test was designed for the normal distribution.
Section 15-3
15-21 1. The parameter of interest is the mean titanium content
2. H 0 : µ = 8.5
3. H 1 : µ ≠ 8.5
4. α=0.05
5. The test statistic is w = min( w + , w -).
6. We will reject H0 if w ≤ w0.05 = 52, since α=0.05 and n=20, the value in Appendix A, Table VIII.
7. w+ = 71 and w - = 102 and so w=min(71,102) = 71
8. Conclusion: Since 71>52, we cannot reject H0.
15-23 1. The parameter of interest is the mean titanium content
2. H 0 : µ = 2.5
3. H 1 : µ < 2.5
4. α=0.05
5. The test statistic w = min( w + , w -).
6. We will reject H0 if w ≤ w0.05 = 65, since α=0.05 and n=22 the value in Appendix A, Table VIII.
7. w+ = 225 and w - = 8 and so w=min(225, 8) = 8
8.Conclusion: Since 8 < 65, we reject H0.
15-27. 1. The parameters of interest are the mean blood cholesterol levels.
2. H 0 : µ D = 0
3. H 1 : µ D ≠ 0
4. α=0.05
5. The test statistic is w = min( w + , w -).
Image 140:
6. We will reject H0 is w ≤ w0.05 = 25, since α=0.05 and n=15, the value in Appendix A, Table VIII.
7. w+ = 118 and w - = 1 and so w=min(118, 1) = 1 Since 1 < 25
8. Conclusion: Since 1 < 25, we reject H0.
Section 15-4
15-31. 1. The parameters of interest are the mean image brightness’.
2. H 0 : µ1 = µ 2
3. H 1 : µ1 > µ 2
4. α=0.025
5. The test statistic is z = W1 − µ w1
0
σ w1
6. We will reject H0 if Z0 > Z0.025 = 1.96
2
7. w1 = 40 , µ w1 =85.5 and σ w1 =128.25
54 − 85 . 5
z0 = = − 2 . 78
11 . 32
Since Z0 < 1.96, cannot reject H0
8. Conclusion: do not reject H0.
P-value = 0.9973
15-35. 1. The parameters of interest are the mean etch rates
2. H 0 : µ1 = µ 2
3. H 1 : µ1 ≠ µ 2
4. α=0.025
5. The test statistic is z = W1 − µ w1
0
σ w1
6. We will reject H0 if |Z0| > Z0.025 = 1.96
2
7. w1 = 55 , µ w1 =105 and σ w1 =175
55 − 105
z0 = = − 3 . 77
13 . 23
Since |Z0| < 1.96, reject H0
8. Conclusion: reject H0.
P-value = 0.0001
Section 15-5
15-37. Kruskal-Wallis Test on strength
mixingte N Median Ave Rank Z
1 4 2945 9.6 0.55
2 4 3075 12.9 2.12
3 4 2942 9.0 0.24
4 4 2650 2.5 -2.91
Overall 16 8.5
H = 10.00 DF = 3 P = 0.019
H = 10.03 DF = 3 P = 0.018 (adjusted for ties)
NOTE One or more small samples
Reject H0
Image 141: Supplemental
15-43. 1. The parameter of interest is median of surface finish.
~
2. H 0 : µ = 10.0
~
3 H : µ ≠ 10.0
1
4. α=0.05
5. The test statistic is the observed number of plus differences or r+ = 5.
6. We reject H0 if the P-value corresponding to r+ = 5 is less than or equal to α=0.05.
7. Using the binomial distribution with n=10 and p=0.5, P-value = 2P(R≥5|p=0.5)=1.0
8. Conclusion: we cannot reject H0. We cannot reject the claim that the median is 10 µin.
15-45. The parameter of interest is the median fluoride emissions
~
H0 : µ = 6
~
H :µ <6
1
α=0.05
Using Minitab (Sign Rank Test)
Sign test of median = 6.000 versus < 6.000
N Below Equal Above P Median
y 15 9 2 4 0.1334 4.000
Do not reject H0
15-47. 1. The parameters of interest are the median impurity levels.
~
2. H 0 : µ D = 0
~
3. H : µ ≠ 0
1 D
4. α=0.01
5. The test statistic is r = min( r+ , r-).
6. Since α=0.01 and n=8, Appendix,= Table VII gives the critical value of r0.01 =0. We will reject
H0 in favor of H1 if r ≤ 10.
7. r+ = 1 and r - = 7 and so r=min(1,7) = 1
8. Conclusion: cannot reject H0. There is no significant difference in the impurity levels.
15-49. The parameter of interest is the median fluoride emissions
H0 : µ = 6
H1 : µ < 6
α=0.05
Using Minitab Wilcoxon signed-rank t test
Test of median = 6.000 versus median < 6.000
N for Wilcoxon Estimated
N Test Statistic P Median
y 15 13 19.0 0.035 5.000
Reject H0
The Wilcoxon signed-rank test applies to symmetric continuous distributions. The test to applies to the
mean of the distribution.
15-51. 1. The parameters of interest are the mean volumes
2. H 0 : µ1 = µ 2
3. H 1 : µ1 ≠ µ 2
4. α=0.01
5. The test statistic is w = ( n1 + n 2 )( n1 + n 2 + 1) − w
2 1
2
6. We will reject H0 if w ≤ w0.01 = 71, since α=0.01 and n1=10 and n2=10, the value in Appendix A,
Table IX.
7. w1 = 42 and w2 = 78 and so since 42 is less than 78, we reject H0
Image 142: 8. Conclusion: reject H0
15-57. Kruskal-Wallis Test on VOLUME
TEMPERAT N Median Ave Rank Z
70 5 1245 12.4 2.69
75 5 1220 7.9 -0.06
80 5 1170 3.7 -2.63
Overall 15 8.0
H = 9.46 DF = 2 P = 0.009
H = 9.57 DF = 2 P = 0.008 (adjusted for ties)
Reject H0, P-value=0.0009
Image 143: Chapter 16 Selected Problem Solutions
Section 16-5
16-3 a) X-bar and Range - Initial Study
Charting Problem 16-3
X-bar | Range
----- | -----
UCL: + 3.0 sigma = 17.4 | UCL: + 3.0 sigma = 5.792
Centerline = 15.09 | Centerline = 2.25
LCL: - 3.0 sigma = 12.79 | LCL: - 3.0 sigma = 0
|
Test Results: X-bar One point more than 3.00 sigmas from center line.
Test Failed at points: 4 6 7 10 12 15 16 20
Test Results for R Chart:One point more than 3.00 sigmas from center line.
Test Failed at points: 19
Xbar/R Chart for x1-x3
1
20
1
Sample Mean
1
UCL=17.40
15 Mean=15.09
LCL=12.79
1 1 1
10 1
1
Subgroup 0 10 20
6 1
UCL=5.792
Sample Range
5
4
3
2 R=2.25
1
0 LCL=0
.
b. Removed points 4, 6, 7, 10, 12, 15, 16, 19, and 20 and revised the control limits
The control limits are not as wide after being revised X-bar UCL=17.96, CL=15.78
LCL=13.62 and R UCL = 5.453, R-bar=2.118, LCL=0.
The X-bar control moved down.
Xbar/R Chart for x1-x3
Revised Control Limits
18 UCL=17.95
Sample Mean
17
16 Mean=15.78
15
14
LCL=13.62
13
Subgroup 0 5 10
6
UCL=5.453
Sample Range
5
4
3
2 R=2.118
1
0 LCL=0
Image 144: c) X-bar and StDev - Initial Study
Charting Problem 16-3
X-bar | StDev
----- | -----
UCL: + 3.0 sigma = 17.42 | UCL: + 3.0 sigma = 3.051
Centerline = 15.09 | Centerline = 1.188
LCL: - 3.0 sigma = 12.77 | LCL: - 3.0 sigma = 0
|
Test Results: X-bar One point more than 3.00 sigmas from center line.
Test Failed at points: 4 6 7 10 12 15 16 20
Test Results for S Chart:One point more than 3.00 sigmas from center line.
Test Failed at points: 19
.
Xbar/S Chart for x1-x3
1
20
1
Sample Mean
1
UCL=17.42
15 Mean=15.09
LCL=12.77
1 1 1
10 1
1
Subgroup 0 10 20
1
3 UCL=3.051
Sample StDev
2
S=1.188
1
0 LCL=0
Removed points 4, 6, 7, 10, 12, 15, 16, 19, and 20 and revised the control limits
The control limits are not as wide after being revised X-bar UCL=17.95, CL=15.78
LCL=13.62 and S UCL = 2.848, S-bar=1.109, LCL=0.
The X-bar control moved down.
Xbar/S Chart for x1-x3
Revised Control Limits
18 UCL=17.95
Sample Mean
17
16 Mean=15.78
15
14
LCL=13.62
13
Subgroup 0 5 10
3 UCL=2.848
Sample StDev
2
1 S=1.109
0 LCL=0
Image 145: 7805 1200
16-5. a) x= = 223 r= = 34.286
35 35
x chart
UCL = CL + A2 r = 223 + 0.577(34.286) = 242.78
CL = 223
LCL = CL − A2 r = 223 − 0.577(34.286) = 203.22
R chart
UCL = D4 r = 2.115(34.286) = 72.51
CL = 34.286
LCL = D3r = 0(34.286) = 0
b)
µ = x = 223
ˆ
r 34.286
σ =
ˆ = = 14.74
d2 2.326
16-7 a) X-bar and Range - Initial Study
Charting Problem 16-7
X-bar | Range
----- | -----
UCL: + 3.0 sigma = 0.0634706 | UCL: + 3.0 sigma = 1.95367E-3
Centerline = 0.0629376 | Centerline = 9.24E-4
LCL: - 3.0 sigma = 0.0624046 | LCL: - 3.0 sigma = 0
|
out of limits = 5 | out of limits = 2
Chart: Both Normalize: No
25 subgroups, size 5 0 subgroups excluded
Estimated
Xbar/R Chart for x
0.064 1
1
Sample Mean
UCL=0.06347
0.063 Mean=0.06294
LCL=0.06240
1 1
0.062
1
Subgroup 0 5 10 15 20 25
0.003
1
Sample Range
1
0.002 UCL=0.001954
0.001 R=0.000924
0.000 LCL=0
Image 146: b)
Xbar/S Chart for x
0.064 1
1
Sample Mean
UCL=0.06346
0.063 Mean=0.06294
LCL=0.06241
1 1
0.062
1
Subgroup 0 5 10 15 20 25
1
0.0010
Sample StDev
1
UCL=7.66E-04
0.0005
S=3.67E-04
0.0000 LCL=0
c) There are several points out of control. The control limits need to be revised.
The points are 1, 5, 14,17, 20,21, and 22; or outside the control limits of the R chart: 6 and 15
Section 16-6
16-9. a)
Individuals and MR(2) - Initial Study
Charting Problem 15-8
Ind.x | MR(2)
----- | -----
UCL: + 3.0 sigma = 60.8887 | UCL: + 3.0 sigma = 9.63382
Centerline = 53.05 | Centerline = 2.94737
LCL: - 3.0 sigma = 45.2113 | LCL: - 3.0 sigma = 0
|
out of limits = 0 | out of limits = 0
Chart: Both Normalize: No
20 subgroups, size 1 0 subgroups excluded
Estimated
process mean = 53.05
process sigma = 2.61292
mean MR = 2.94737
Image 147: There are no points beyond the control limits. The process appears to be in control.
I and MR Chart for hardness
Individual Value UCL=60.89
60
55
Mean=53.05
50
45 LCL=45.21
Subgroup 0 10 20
10 UCL=9.630
Moving Range
5
R=2.947
0 LCL=0
b)
µ = x = 53.05
ˆ
mr 2.94737
σ =
ˆ = = 2.613
d2 1.128
Section 16-7
r 0.344
16-15. a) Assuming a normal distribution with µ = 0.14.510 and σ = = = 0148
.
d 2 2.326
LSL − µ
ˆ
P(X < LSL ) = P Z <
σˆ
14.00 − 14.51
= P Z <
0.148
= P(Z < −3.45)
= 1 − P( Z < 3.45)
= 1 − 0.99972
= 0.00028
![Image 148: USL − µ
ˆ
P ( X > USL) = P Z >
σˆ
15.00 − 14.51
= P Z >
0.148
= P( Z > 3.31)
= 1 − P ( Z < 3.31)
= 1 − 0.99953
= 0.00047
Therefore, the proportion nonconforming is given by
P(XUSL) =0.00028 + 0.00047 = 0.00075
b)
USL − LSL 15.00 − 14.00
PCR = = = 1.13
6(σ )
ˆ 6(0.148)
USL − x x − LSL
PCRK = min ,
3σ ˆ 3σ
ˆ
15.00 − 14.51 14.51 − 14.00
= min ,
3(0.148) 3(0.148)
= min[ .104,1.15]
1
= 1.104
Since PCR exceeds unity, the natural tolerance limits lie inside the specification limits and very few
defective units will be produced.
PCRK ≅ PCR the process appears to be centered.
s 13.58
16-19 a) Assuming a normal distribution with µ = 223 and σ =
ˆ = = 14.74
c 4 0.9213
LSL − µ
ˆ
P(X < LSL ) = P Z <
σˆ
170 − 223
= P Z <
14.74
= P(Z < −3.60)
= 0.00016
](
![Image 149: USL − µ
ˆ
P ( X > USL) = P Z >
σˆ
270 − 223
= P Z >
14.75
= P ( Z > 3.18)
= 1 − P ( Z < 3.18)
= 1 − 0.99926
= 0.00074
Probability of producing a part outside the specification limits is 0.00016+0.00074 = 0.0009
b
USL − LSL 270 − 220
PCR = = = 1.13
6(σ )
ˆ 6(14.75)
USL − x x − LSL
PCRK = min ,
3σˆ 3σ
ˆ
270 − 223 223 − 170
= min ,
3(14.75) 3(14.75)
= min[1.06,1.19]
= 1.06
Since PCR exceeds unity, the natural tolerance limits lie inside the specification limits and
very few defective units will be produced. The estimated proportion nonconforming is given by
P(X<LSL) + P(X>USL) =0.00016 + 0.00074=0.0009
16-23. Assuming a normal distribution with µ = 500.6 and σ = 17.17
USL − LSL 525 − 475
PCR = = = 0.49
6(σ )
ˆ 6(17.17)
USL − x x − LSL
PCRK = min ,
3σ ˆ ˆ
3σ
525 − 500.6 500.6 − 475
= min ,
3(17.17) 3(17.17)
= min[0.474,0.50]
= 0.474
Since the process capability ratios are less than unity, the process capability appears to be poor.
](
Image 150: Section 16-8
16-25.
U Chart for defects
5 1
1
4
3.0SL=3.811
Sample Count
3
2 U=1.942
1
0 -3.0SL=0.07217
0 5 10 15 20 25
Sample Number
Samples 5 and 24 have out-of-control points. The limits need to be revised.
b)
U Chart for defects_
4
UCL=3.463
3
Sample Count
2
U=1.709
1
0 LCL=0
0 10 20
Sample Number
The control limits are calculated without the out-of-control points. There are no points out of control for
the revised limits.
16-27.
C Chart for defects
1
1
20
3.0SL=19.06
Sample Count
10 C=9.708
0 -3.0SL=0.3609
0 5 10 15 20 25
Sample Number
Image 151: There are two points beyond the control limits. They are samples 5 and 24.
The U chart and the C chart both detected out-of-control points at samples 5 and 24.
Section 16-9
σˆ 2.4664
16-31. a) σ x = = = 1.103 , µ = 36
n 5
P(30.78 < X < 37.404)
30.78 − 36 X − µ 37.404 − 36
= P 1.103 < σ <
ˆx 1.103
= P (−4.73 < Z < 1.27) = P( Z < 1.27) − P( Z < −4.73)
= 0.8980 − 0 = 0.8980
The probability that this shift will be detected on the next sample is p = 1−0.8980 = 0.1020.
1 1
b) ARL = = = 9.8
p 0.102
R 6.75 σˆ 3.28
16-33. a) σ =
ˆ = = 3.28 σx = = = 1.64 , µ = 13
d 2 2.059 n 4
P (5.795 < X < 15.63)
5.795 − 13 X − µ 15.63 − 13
= P 1.64 < σ <
x 1.64
= P (−4.39 < Z < 1.60) = P( Z < 1.60) − P ( Z < −4.39)
= 0.9452 − 0 = 0.9452
The probability that this shift will be detected on the next sample is p = 1−0.9452 = 0.0548.
1 1
b) ARL = = = 18.25
p 0.0548
Section 16-10
16-39. a) σ = 0.1695
ˆ
b) The process appears to be out of control at the specified target level.
Image 152: CUSUM Chart for diameter
Upper CUSUM
0.678191
0.5
Cumulative Sum
0.0
-0.5
Lower CUSUM -6.8E-01
0 5 10 15 20 25
Subgroup Number
Supplemental
16-43. a)
X-bar and Range - Initial Study
X-bar | Range
---- | -----
UCL: + 3.0 sigma = 64.0181 | UCL: + 3.0 sigma = 0.0453972
Centerline = 64 | Centerline = 0.01764
LCL: - 3.0 sigma = 63.982 | LCL: - 3.0 sigma = 0
|
out of limits = 0 | out of limits = 0
Chart: Both Normalize: No
Estimated
process mean = 64
process sigma = 0.0104194
mean Range = 0.01764
Xbar/R Chart for diameter
64.02
UCL=64.02
Sample Mean
64.01
64.00 Mean=64.00
63.99
LCL=63.98
63.98
Subgroup 0 5 10 15 20 25
0.05
UCL=0.04438
Sample Range
0.04
0.03
0.02
R=0.01724
0.01
0.00 LCL=0
![Image 153: The process is in control.
R 0.01764
b) µ = x = 64 σ =
=ˆ = 0.0104
d2 1.693
USL − LSL 64.02 − 63.98
c) PCR = = = 0.641
6σˆ 6(0.0104)
The process does not meet the minimum capability level of PCR ≥ 1.33.
d)
USL − x x − LSL 64.02 − 64 64 − 63.98
PCRk = min , = min 3(0.0104) , 3(0.0104)
3σ ˆ 3σ
ˆ
= min[0.641,0.641] = 0.641
e) In order to make this process a “six-sigma process”, the variance σ2 would have to be decreased such that
x − LSL
PCRk = 2.0. The value of the variance is found by solving PCRk = = 2.0 for σ:
3σ
64 − 61
= 2.0
3σ
6σ = 64. − 61
64. − 61
σ = = 0.50
6
Therefore, the process variance would have to be decreased to σ2 = (0.50)2 = 0.025.
f) σ x = 0.0104
P(63.98 < X < 64.02)
63.98 − 64.01 X − µ 64.02 − 64.01
= P 0.0104 < <
σx 0.0104
= P (−2.88 < Z < 0.96) = P( Z < 0.96) − P( Z < −2.88)
= 0.8315 − 0.0020 = 0.8295
The probability that this shift will be detected on the next sample is p = 1−0.8295 = 0.1705
1 1
ARL = = = 5.87
p 0.1705
16-45. a)
P Chart - Initial Study
P Chart
UCL: + 3.0 sigma = 0.203867
Centerline = 0.11
LCL: - 3.0 sigma = 0.0161331
out of limits = 0
Estimated
mean P = 0.11
sigma = 0.031289
](
Image 154: P Chart for def
0.2 UCL=0.2039
Proportion
P=0.11
0.1
LCL=0.01613
0.0
0 10 20
Sample Number
There are no points beyond the control limits. The process is in control.
b)
P Chart - Initial Study
Sample Size, n = 200
P Chart
UCL: + 3.0 sigma = 0.176374
Centerline = 0.11
LCL: - 3.0 sigma = 0.0436261
out of limits = 1
Estimated
mean P = 0.11
sigma = 0.0221246
P Chart for def2
0.19 1
UCL=0.1764
0.14
Proportion
P=0.11
0.09
0.04 LCL=0.04363
0 10 20
Sample Number
There is one point beyond the upper control limit. The process is out of control.
The revised limits are:
P Chart - Revised Limits
Sample Size, n = 200
P Chart
UCL: + 3.0 sigma = 0.171704
Centerline = 0.106316
LCL: - 3.0 sigma = 0.0409279
out of limits = 0
Estimated
mean P = 0.106316
![Image 155: sigma = 0.021796
There are no points beyond the control limits. The process is now in control.
P Chart for def2
0.19
UCL=0.1717
0.14
Proportion
P=0.1063
0.09
0.04 LCL=0.04093
0 10 20
Sample Number
c) A larger sample size with the same number of defective items will result in more narrow control limits.
The control limits corresponding to the larger sample size are more sensitive.
16-49. ARL = 1/p where p is the probability a point falls outside the control limits.
a) µ = µ 0 + σ and n = 1
p = P( X > UCL) + P( X < LCL)
3σ 3σ
µ0 + − µ0 − σ µ0 − − µ0 − σ
n n
= P Z > + P Z <
σ/ n σ/ n
= P ( Z > 3 − n ) + P ( Z < −3 − n )
= P( Z > 2) + P ( Z < −4) when n = 1
= 1 − P( Z < 2) + [1 − P( Z < 4)] = 1 − 0.97725 + [1 − 1] = 0.02275
Therefore, ARL = 1/p = 1/0.02275 = 43.9.
b) µ = µ 0 + 2σ
](
![Image 156: P( X > UCL) + P( X < LCL)
3σ 3σ
µ0 + − µ 0 − 2σ µ0 − − µ 0 − 2σ
= P Z > n + P Z < n
σ/ n σ/ n
= P( Z > 3 − 2 n ) + P( Z < −3 − 2 n )
= P( Z > 1) + P( Z < −5) when n = 1
= 1 − P( Z < 1) + [1 − P( Z < 5)]
= 1 − 0.84134 + [1 − 1]
= 0.15866
Therefore, ARL = 1/p = 1/0.15866 = 6.30.
c) µ = µ 0 + 3σ
P( X > UCL) + P( X < LCL)
3σ 3σ
µ0 + − µ 0 − 3σ µ0 − − µ 0 − 3σ
Z > n + P Z < n
=P
σ/ n σ/ n
= P ( Z > 3 − 3 n ) + P ( Z < −3 − 3 n )
= P( Z > 0) + P( Z < −6) when n = 1
= 1 − P( Z < 0) + [1 − P( Z < 6)] = 1 − 0.50 + [1 − 1] = 0.50
Therefore, ARL = 1/p = 1/0.50 = 2.00.
d) The ARL is decreasing as the magnitude of the shift increases from σ to 2σ to 3σ. The ARL will
decrease as the magnitude of the shift increases since a larger shift is more likely to be detected earlier
than a smaller shift.
16-51. a)
X-bar and Range - Initial Study
Charting xbar
X-bar | Range
----- | -----
UCL: + 3.0 sigma = 140.168 | UCL: + 3.0 sigma = 2.48437
Centerline = 139.49 | Centerline = 1.175
LCL: - 3.0 sigma = 138.812 | LCL: - 3.0 sigma = 0
out of limits = 9 | out of limits = 0
Estimated
process mean = 139.49
process sigma = 0.505159
mean Range = 1.175
](
![Image 157: Problem 16-51
141
140 140.168
X-bar 139.49
139 138.812
138
137
0 4 8 12 16 20
2.5 2.48437
2
1.5
Range
1.175
1
0.5
0 0
0 4 8 12 16 20
subgroup
There are points beyond the control limits. The process is out of control. The points are 4, 8, 10, 13, 15,
16, and 19.
b) Revised control limits are given in the table below:
X-bar and Range - Initial Study
Charting Xbar
X-bar | Range
----- | -----
UCL: + 3.0 sigma = 140.518 | UCL: + 3.0 sigma = 2.60229
Centerline = 139.808 | Centerline = 1.23077
LCL: - 3.0 sigma = 139.098 | LCL: - 3.0 sigma = 0
out of limits = 0 | out of limits = 0
Estimated
process mean = 139.808
process sigma = 0.529136
mean Range = 1.23077
z
There are no points beyond the control limits the process is now in control.
R 123077
.
The process standard deviation estimate is given by σ = = = 0.529
d2 2.326
USL − LSL 142 − 138
c) PCR = = = 126
.
6σ 6(0.529)
USL − x x − LSL
PCR k = min ,
3σ 3σ
142 − 139.808 139.808 − 138
= min ,
3(0.529) 3(0.529)
= min[138,114]
. .
= 114
.
Since PCR exceeds unity, the natural tolerance limits lie inside the specification limits and very few
defective units will be produced.
PCR is slightly larger than PCRk indicating that the process is somewhat off center.
d) In order to make this process a “six-sigma process”, the variance σ2 would have to be decreased such that
x − LSL
PCRk = 2.0. The value of the variance is found by solving PCRk = = 2.0 for σ:
3σ
](
![Image 158: 139.808 − 138
= 2.0
3σ
6σ = 139.808 − 138
139.808 − 138
σ=
6
σ = 0.3013
Therefore, the process variance would have to be decreased to σ2 = (0.3013)2 = 0.091.
e) σ x = 0.529
p = P(139.098 < X < 140.518 | µ = 139.7)
139.098 − 139.7 X − µ 140.518 − 139.7
= P
< <
0.529 σx 0.529
= P (−1.14 < Z < 1.55) = P( Z < 1.55) − P( Z < −1.14)
= P ( Z < 1.55) − [1 − P( Z < 1.14)] = 0.93943 − [1 − 0.87285] = 0.8123
The probability that this shift will be detected on the next sample is 1−p = 1−0.8123 = 0.1877.
1 1
ARL = = = 5.33
1 − p 01877
.
](
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Applied statistics and probability for engineers solution montgomery && runger
Applied Statistics and Probability forEngineers Third Edition Douglas C. Montgomery Arizona State University George C. Runger Arizona State University John Wiley & Sons, Inc.
ACQUISITIONS EDITOR WayneAnderson ASSISTANT EDITOR Jenny Welter MARKETING MANAGER Katherine Hepburn SENIOR PRODUCTION EDITOR Norine M. Pigliucci DESIGN DIRECTOR Maddy Lesure ILLUSTRATION EDITOR Gene Aiello PRODUCTION MANAGEMENT SERVICES TechBooks This book was set in Times Roman by TechBooks and printed and bound by Donnelley/Willard. The cover was printed by Phoenix Color Corp. This book is printed on acid-free paper. ϱ Copyright 2003 © John Wiley & Sons, Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 605 Third Avenue, New York, NY 10158-0012, (212) 850-6011, fax (212) 850-6008, E-Mail: PERMREQ@WILEY.COM. To order books please call 1(800)-225-5945. Library of Congress Cataloging-in-Publication Data Montgomery, Douglas C. Applied statistics and probability for engineers / Douglas C. Montgomery, George C. Runger.—3rd ed. p. cm. Includes bibliographical references and index. ISBN 0-471-20454-4 (acid-free paper) 1. Statistics. 2. Probabilities. I. Runger, George C. II. Title. QA276.12.M645 2002 519.5—dc21 2002016765 Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1
SO fm.qxd 8/6/024:31 PM Page v Preface The purpose of this Student Solutions Manual is to provide you with additional help in under- standing the problem-solving processes presented in Applied Statistics and Probability for Engineers. The Applied Statistics text includes a section entitled “Answers to Selected Exercises,” which contains the final answers to most odd-numbered exercises in the book. Within the text, problems with an answer available are indicated by the exercise number enclosed in a box. This Student Solutions Manual provides complete worked-out solutions to a subset of the problems included in the “Answers to Selected Exercises.” If you are having difficulty reach- ing the final answer provided in the text, the complete solution will help you determine the correct way to solve the problem. Those problems with a complete solution available are indicated in the “Answers to Selected Exercises,” again by a box around the exercise number. The complete solutions to this subset of problems may also be accessed by going directly to this Student Solutions Manual.
Chapter 2 SelectedProblem Solutions Section 2-2 2-43. 3 digits between 0 and 9, so the probability of any three numbers is 1/(101010); 3 letters A to Z, so the probability of any three numbers is 1/(262626); The probability your license plate -8 is chosen is then (1/103)(1/263) = 5.7 x 10 Section 2-3 2-49. a) P(A') = 1- P(A) = 0.7 b) P ( A ∪ B ) = P(A) + P(B) - P( A ∩ B ) = 0.3+0.2 - 0.1 = 0.4 c) P( A ′ ∩ B ) + P( A ∩ B ) = P(B). Therefore, P( A ′ ∩ B ) = 0.2 - 0.1 = 0.1 d) P(A) = P( A ∩ B ) + P( A ∩ B ′ ). Therefore, P( A ∩ B ′ ) = 0.3 - 0.1 = 0.2 e) P(( A ∪ B )') = 1 - P( A ∪ B ) = 1 - 0.4 = 0.6 f) P( A ′ ∪ B ) = P(A') + P(B) - P( A ′ ∩ B ) = 0.7 + 0.2 - 0.1 = 0.8 Section 2-4 2-61. Need data from example a) P(A) = 0.05 + 0.10 = 0.15 P( A ∩ B) 0.04 + 0.07 b) P(A|B) = = = 0.153 P( B ) 0.72 c) P(B) = 0.72 P( A ∩ B) 0.04 + 0.07 d) P(B|A) = = = 0.733 P( B ) 0.15 e) P(A ∩ B) = 0.04 +0.07 = 0.11 f) P(A ∪ B) = 0.15 + 0.72 – 0.11 = 0.76 2-67. a) P(gas leak) = (55 + 32)/107 = 0.813 b) P(electric failure|gas leak) = (55/107)/(87/102) = 0.632 c) P(gas leak| electric failure) = (55/107)/(72/107) = 0.764 Section 2-5 2-73. Let F denote the event that a roll contains a flaw. Let C denote the event that a roll is cotton. P ( F ) = P( F C ) P(C ) + P( F C ′) P (C ′) = (0.02)(0.70) + (0.03)(0.30) = 0.023 2-79. Let A denote a event that the first part selected has excessive shrinkage. Let B denote the event that the second part selected has excessive shrinkage. a) P(B)= P( B A )P(A) + P( B A ')P(A') = (4/24)(5/25) + (5/24)(20/25) = 0.20 b) Let C denote the event that the second part selected has excessive shrinkage. P(C) = P(C A ∩ B)P( A ∩ B) + P(C A ∩ B')P( A ∩ B') +P(C A'∩B)P( A'∩B) + P(C A'∩B')P( A'∩B') 3 2 5 4 20 5 4 5 20 5 19 20 = + + + 23 24 25 23 24 25 23 24 25 23 24 25 = 0.20
Section 2-6 2-87. It is useful to work one of these exercises with care to illustrate the laws of probability. Let Hi denote the event that the ith sample contains high levels of contamination. ' ' ' ' ' ' ' ' ' ' a) P(H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 ) = P(H1)P(H2 )P(H3 )P(H4 )P(H5 ) by independence. Also, P(Hi' ) = 0.9 . Therefore, the answer is 0.9 5 = 0.59 b) A1 = (H1 ∩ H'2 ∩ H3 ∩ H4 ∩ H5 ) ' ' ' ' ' ' ' A 2 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 ) ' ' ' ' A 3 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 ) ' ' ' ' A 4 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 ) ' ' ' ' A 5 = (H1 ∩ H2 ∩ H3 ∩ H4 ∩ H5 ) The requested probability is the probability of the union A1 ∪ A 2 ∪ A 3 ∪ A 4 ∪ A 5 and these events are mutually exclusive. Also, by independence P( A i ) = 0.9 4 (0.1) = 0.0656 . Therefore, the answer is 5(0.0656) = 0.328. c) Let B denote the event that no sample contains high levels of contamination. The requested probability is P(B') = 1 - P(B). From part (a), P(B') = 1 - 0.59 = 0.41. 2-89. Let A denote the event that a sample is produced in cavity one of the mold. 1 a) By independence, P( A1 ∩ A 2 ∩ A 3 ∩ A 4 ∩ A 5 ) = ( )5 = 0.00003 8 b) Let Bi be the event that all five samples are produced in cavity i. Because the B's are mutually exclusive, P(B1 ∪ B 2 ∪...∪B 8 ) = P(B1) + P(B 2 )+...+P(B 8 ) 1 1 From part a., P(Bi ) = ( )5 . Therefore, the answer is 8( )5 = 0.00024 8 8 1 7 c) By independence, P( A 1 ∩ A 2 ∩ A 3 ∩ A 4 ∩ A '5 ) = ( ) 4 ( ) . The number of sequences in 8 8 1 7 which four out of five samples are from cavity one is 5. Therefore, the answer is 5( ) 4 ( ) = 0.00107 . 8 8 Section 2-7 2-97. Let G denote a product that received a good review. Let H, M, and P denote products that were high, moderate, and poor performers, respectively. a) P(G ) = P(G H ) P( H ) + P(G M ) P( M ) + P(G P) P( P) = 0. 95( 0. 40) + 0. 60( 0. 35) + 0. 10( 0. 25) = 0. 615 b) Using the result from part a., P ( G H ) P ( H ) 0. 95( 0. 40) P( H G ) = = = 0. 618 P( G ) 0. 615 c) P ( H G ' ) = P ( G ' H ) P ( H ) = 0. 05( 0. 40) = 0. 052 P(G' ) 1 − 0. 615 Supplemental 2-105. a) No, P(E1 ∩ E2 ∩ E3) ≠ 0 b) No, E1′ ∩ E2′ is not ∅ c) P(E1′ ∪ E2′ ∪ E3′) = P(E1′) + P(E2′) + P(E3′) – P(E1′∩ E2′) - P(E1′∩ E3′) - P(E2′∩ E3′) + P(E1′ ∩ E2′ ∩ E3′) = 40/240
d) P(E1 ∩E2 ∩ E3) = 200/240 e) P(E1 ∪ E3) = P(E1) + P(E3) – P(E1 ∩ E3) = 234/240 f) P(E1 ∪ E2 ∪ E3) = 1 – P(E1′ ∩ E2′ ∩ E3′) = 1 - 0 = 1 2-107. Let Ai denote the event that the ith bolt selected is not torqued to the proper limit. a) Then, P( A 1 ∩ A 2 ∩ A 3 ∩ A 4 ) = P( A 4 A 1 ∩ A 2 ∩ A 3 )P( A 1 ∩ A 2 ∩ A 3 ) = P( A 4 A 1 ∩ A 2 ∩ A 3 )P( A 3 A 1 ∩ A 2 )P( A 2 A 1)P( A 1) 2 3 4 5 = = 0.282 17 18 19 20 b) Let B denote the event that at least one of the selected bolts are not properly torqued. Thus, B' is the event that all bolts are properly torqued. Then, 15 14 13 12 P(B) = 1 - P(B') = 1 − = 0.718 20 19 18 17 2-113. D = defective copy 2 73 72 73 2 72 73 72 2 a) P(D = 1) = + + = 0.0778 75 74 73 75 74 73 75 74 73 2 1 73 2 73 1 73 2 1 b) P(D = 2) = + + = 0.00108 75 74 73 75 74 73 75 74 73 2-117. Let A i denote the event that the ith washer selected is thicker than target. 30 29 28 a) = 0.207 50 49 8 b) 30/48 = 0.625 c) The requested probability can be written in terms of whether or not the first and second washer selected are thicker than the target. That is, ' ' ' ' P( A 3 ) = P( A 1A 2 A 3 orA 1A 2 A 3 orA 1A 2 A 3 orA 1A 2 A 3 ) ' ' = P( A 3 A 1 A 2 )P( A 1A 2 ) + P( A 3 A 1 A 2 )P( A 1A 2 ) ' ' ' ' ' +P( A 3 A 1 'A 2 )P( A 1A 2 ) + P( A 3 A 1 A 2 )P( A 1A 2 ) ' ' = P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 ) + P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 ) ' ' ' ' ' ' ' ' +P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 ) + P( A 3 A 1 A 2 )P( A 2 A 1 )P( A 1 ) 28 30 29 29 20 30 29 20 30 30 20 19 = + + + 48 50 49 48 50 49 48 50 49 48 50 49 = 0.60 2-121. Let A i denote the event that the ith row operates. Then, P ( A1 ) = 0. 98, P ( A 2 ) = ( 0. 99)( 0. 99) = 0. 9801, P ( A 3 ) = 0. 9801, P ( A 4 ) = 0. 98. The probability the circuit does not operate is P( A1' ) P( A2 ) P( A3 ) P ( A4 ) = (0.02)(0.0199)(0.0199)(0.02) = 1.58 × 10 −7 ' ' '
Chapter 3 SelectedProblem Solutions Section 3-2 3-13. f X (0) = P( X = 0) = 1 / 6 + 1 / 6 = 1 / 3 f X (1.5) = P( X = 1.5) = 1 / 3 f X ( 2) = 1 / 6 f X (3) = 1 / 6 3-21. P(X = 0) = 0.023 = 8 x 10-6 P(X = 1) = 3[0.98(0.02)(0.02)]=0.0012 P(X = 2) = 3[0.98(0.98)(0.02)]=0.0576 P(X = 3) = 0.983 = 0.9412 3-25. X = number of components that meet specifications P(X=0) = (0.05)(0.02)(0.01) = 0.00001 P(X=1) = (0.95)(0.02)(0.01) + (0.05)(0.98)(0.01)+(0.05)(0.02)(0.99) = 0.00167 P(X=2) = (0.95)(0.98)(0.01) + (0.95)(0.02)(0.99) + (0.05)(0.98)(0.99) = 0.07663 P(X=3) = (0.95)(0.98)(0.99) = 0.92169 Section 3-3 3-27. 0, x < −2 1 / 8 −2 ≤ x < −1 3 / 8 −1 ≤ x < 0 F( x) = 5/8 0 ≤ x<1 7 / 8 1 ≤ x < 2 1 2≤x a) P(X ≤ 1.25) = 7/8 b) P(X ≤ 2.2) = 1 c) P(-1.1 < X ≤ 1) = 7/8 − 1/8 = 3/4 d) P(X > 0) = 1 − P(X ≤ 0) = 1 − 5/8 = 3/8 3-31. 0 x<0 . 0.008 0 ≤ x < 1 f (0) = 0.2 3 = 0.008, F ( x) = 0.104 1 ≤ x < 2 where f (1) = 3(0.2)(0.2)(0.8) = 0.096, 0.488 2 ≤ x < 3 f (2) = 3(0.2)(0.8)(0.8) = 0.384, 1 3≤ x f (3) = (0.8) 3 = 0.512, 3-33. a) P(X ≤ 3) = 1 b) P(X ≤ 2) = 0.5 c) P(1 ≤ X ≤ 2) = P(X=1) = 0.5 d) P(X>2) = 1 − P(X≤2) = 0.5
Section 3-4 3-37 Mean and Variance µ = E ( X ) = 0 f (0) + 1 f (1) + 2 f (2) + 3 f (3) + 4 f (4) = 0(0.2) + 1(0.2) + 2(0.2) + 3(0.2) + 4(0.2) = 2 V ( X ) = 0 2 f (0) + 12 f (1) + 2 2 f (2) + 3 2 f (3) + 4 2 f (4) − µ 2 = 0(0.2) + 1(0.2) + 4(0.2) + 9(0.2) + 16(0.2) − 2 2 = 2 3-41. Mean and variance for exercise 3-19 µ = E ( X ) = 10 f (10) + 5 f (5) + 1 f (1) = 10(0.3) + 5(0.6) + 1(0.1) = 6.1 million V ( X ) = 10 2 f (10) + 5 2 f (5) + 12 f (1) − µ 2 = 10 2 (0.3) + 5 2 (0.6) + 12 (0.1) − 6.12 = 7.89 million 2 3-45. Determine x where range is [0,1,2,3,x] and mean is 6. µ = E ( X ) = 6 = 0 f (0) + 1 f (1) + 2 f (2) + 3 f (3) + xf ( x) 6 = 0(0.2) + 1(0.2) + 2(0.2) + 3(0.2) + x(0.2) 6 = 1.2 + 0.2 x 4.8 = 0.2 x x = 24 Section 3-5 3-47. E(X) = (3+1)/2 = 2, V(X) = [(3-1+1)2 -1]/12 = 0.667 3-49. X=(1/100)Y, Y = 15, 16, 17, 18, 19. 1 15 + 19 E(X) = (1/100) E(Y) = = 0.17 mm 100 2 1 (19 − 15 + 1) − 1 2 2 V (X ) = = 0.0002 mm 2 100 12 Section 3-6 10 3-57. a) P ( X = 5) = 0.5 5 (0.5) 5 = 0.2461 5 10 0 10 10 1 9 10 2 8 b) P ( X ≤ 2) = 0.5 0.5 + 0.5 0.5 + 0.5 0.5 0 1 2 = 0.510 + 10(0.5)10 + 45(0.5)10 = 0.0547
10 10 c) P( X ≥ 9) = 0.5 9 (0.5)1 + 0.510 (0.5) 0 = 0.0107 9 10 10 10 d) P(3 ≤ X < 5) = 0.530.57 + 0.54 0.56 3 4 = 120(0.5)10 + 210(0.5)10 = 0.3223 3-61. n=3 and p=0.25 3 3 27 f (0) = = 0 x<0 4 64 0.4219 0 ≤ x < 1 2 1 3 27 f (1) = 3 = 4 4 64 F ( x) = 0.8438 1 ≤ x < 2 where 2 0.9844 2 ≤ x < 3 1 3 9 f (2) = 3 = 4 4 64 1 3≤ x 3 1 1 f (3) = = 4 64 1000 3-63. = 1) = a) P ( X 1 0.001 (0.999) = 0.3681 1 999 1000 1 0.001 (0.999 ) = 0.6323 b) P( X ≥ 1) = 1 − P( X = 0) = 1 − 1 999 1000 1000 c) P ( X ≤ 2) = 0 0.001 (0.999 ) + 1 0.001 (0.999 ) + ( 2 )0.001 0.999 0 1000 1 999 1000 2 998 = 0.9198 d ) E ( X ) = 1000(0.001) = 1 V ( X ) = 1000(0.001)(0.999) = 0.999 3-67. Let X denote the passengers with tickets that do not show up for the flight. Then, X is binomial with n = 125 and p = 0.1. a) P( X ≥ 5) = 1 − P( X ≤ 4) 125 0 125 1 125 2 0 0.1 (0.9 ) + 1 0.1 (0.9 ) + 2 0.1 (0.9 ) = 1 − 125 124 123 125 3 125 4 121 + 0.1 (0.9 ) + 4 0.1 (0.9 ) = 0.9961 122 3 b) P( X > 5) = 1 − P( X ≤ 5) = 0.9886
3-69. Let X denote the number of questions answered correctly. Then, X is binomial with n = 25 and p = 0.25. 25 25 25 a) P( X ≥ 20) = 0.25 20 (0.75) + 0.25 21 (0.75) + 0.25 22 (0.75) 5 4 3 21 22 20 25 25 25 + 0.25 23 (0.75) + 0.25 24 (0.75) + 0.25 25 (0.75) ≅ 0 2 1 0 23 24 25 25 25 25 b) P( X < 5) = 0.25 0 (0.75) + 0.251 (0.75) + 0.25 2 (0.75) 25 24 23 1 2 0 25 25 + 0.253 (0.75) + 0.25 4 (0.75) = 0.2137 22 21 3 4 Section 3-7 3-71. a. P( X= 1) = (1 − 0.5) 0 0.5 = 0.5 b. P( X= 4) = (1 − 0.5) 3 0.5 = 0.5 4 = 0.0625 c. P( X= 8) = (1 − 0.5) 7 0.5 = 0.58 = 0.0039 d. P( X≤ 2) = P ( X = 1) + P( X = 2) = (1 − 0.5) 0 0.5 + (1 − 0.5)1 0.5 = 0.5 + 0.5 2 = 0.75 e. P ( X > 2) = 1 − P ( X ≤ 2) = 1 − 0.75 = 0.25 3-75. Let X denote the number of calls needed to obtain a connection. Then, X is a geometric random variable with p = 0.02 a) P( X = 10) = (1 − 0.02) 9 0.02 = 0.989 0.02 = 0.0167 b) P( X > 5) = 1 − P( X ≤ 4) = 1 − [ P( X = 1) + P( X = 2) + P( X = 3) + P( X = 4)] = 1 − [0.02 + 0.98(0.02) + 0.98 2 (0.02) + 0.98 3 (0.02)] = 1 − 0.0776 = 0.9224 c) E(X) = 1/0.02 = 50 3-77 p = 0.005 , r = 8 a. P( X = 8) = 0.0005 8 = 3.91x10 −19 1 b. µ = E( X ) = = 200 days 0.005 c Mean number of days until all 8 computers fail. Now we use p=3.91x10-19 1 µ = E (Y ) = −91 = 2.56 x1018 days or 7.01 x1015 years 3.91x10 3-81. a) E(X) = 4/0.2 = 20 19 b) P(X=20) = (0.80)16 0.24 = 0.0436 3 18 c) P(X=19) = (0.80) 0.2 = 0.0459 15 4 3 20 d) P(X=21) = 3 (0.80) 0.2 = 0.0411 17 4
e) The mostlikely value for X should be near µX. By trying several cases, the most likely value is x = 19. 3-83. Let X denote the number of fills needed to detect three underweight packages. Then X is a negative binomial random variable with p = 0.001 and r = 3. a) E(X) = 3/0.001 = 3000 b) V(X) = [3(0.999)/0.0012] = 2997000. Therefore, σX = 1731.18 Section 3-8 P( X = 1) = ( )( ) = (4 ×16 ×15 ×14) / 6 = 0.4623 4 1 16 3 ( ) (20 ×19 ×18 ×17) / 24 3-87. a) 20 4 b) P ( X = 4) = ( )( ) = 4 16 4 0 1 = 0.00021 ( ) (20 ×19 ×18 ×17) / 24 20 4 c) P( X ≤ 2) = P( X = 0) + P( X = 1) + P( X = 2) = ( )( ) + ( )( ) + ( )( ) 4 0 16 4 4 1 16 3 4 16 ( ) ( ) ( ) 2 2 20 20 20 4 4 4 16×15×14×13 4×16×15×14 6×16×15 + + = 24 6 20×19×18×17 2 = 0.9866 24 d) E(X) = 4(4/20) = 0.8 V(X) = 4(0.2)(0.8)(16/19) = 0.539 3-91. Let X denote the number of men who carry the marker on the male chromosome for an increased risk for high blood pressure. N=800, K=240 n=10 a) n=10 P( X = 1) = ( )( ) = ( )( ) = 0.1201 240 560 1 9 240! 560! 1!239! 9!551! ( ) 800 10 800! 10!790! b) n=10 P( X > 1) = 1 − P( X ≤ 1) = 1 − [ P( X = 0) + P( X = 1)] P( X = 0) = ( )( ) = ( 240 560 0 10 240! )( 560! 0!240! 10!560! ) = 0.0276 ( ) 800 10 800! 10!790! P( X > 1) = 1 − P( X ≤ 1) = 1 − [0.0276 + 0.1201] = 0.8523 Section 3-9 e −4 4 0 3-97. a) P( X = 0) = = e −4 = 0.0183 0! b) P( X ≤ 2) = P( X = 0) + P ( X = 1) + P ( X = 2) −4 e − 4 41 e − 4 4 2 =e + + = 0.2381 1! 2! e −4 4 4 c) P( X = 4) = = 0.1954 4!
e −4 48 d) P( X = 8) = = 0.0298 8! 3-99. P( X = 0) = e − λ = 0.05 . Therefore, λ = −ln(0.05) = 2.996. Consequently, E(X) = V(X) = 2.996. 3-101. a) Let X denote the number of flaws in one square meter of cloth. Then, X is a Poisson random variable e −0.1 (0.1) 2 with λ = 0.1. P( X = 2) = = 0.0045 2! b) Let Y denote the number of flaws in 10 square meters of cloth. Then, Y is a Poisson random variable e −111 with λ = 1. P(Y = 1) = = e −1 = 0.3679 1! c) Let W denote the number of flaws in 20 square meters of cloth. Then, W is a Poisson random variable P(W = 0) = e −2 = 0.1353 with λ = 2. d) P(Y ≥ 2) = 1 − P(Y ≤ 1) = 1 − P(Y = 0) − P(Y = 1) = 1 − e −1 − e −1 = 0.2642 3-105. a) Let X denote the number of flaws in 10 square feet of plastic panel. Then, X is a Poisson random −0.5 variable with λ = 0.5. P ( X = 0) = e = 0.6065 b) Let Y denote the number of cars with no flaws, 10 P (Y = 10 ) = ( 0 . 3935 ) 10 ( 0 . 6065 ) 0 = 8 . 9 x10 − 5 10 c) Let W denote the number of cars with surface flaws. Because the number of flaws has a Poisson distribution, the occurrences of surface flaws in cars are independent events with constant probability. From part a., the probability a car contains surface flaws is 1−0.6065 = 0.3935. Consequently, W is binomial with n = 10 and p = 0.3935. 10 P (W = 0) = (0.6065) 0 (0.3935)10 = 8.9 x10 −5 0 10 P (W = 1) = (0.6065)1 (0.3935) 9 = 0.001372 1 P (W ≤ 1) = 0.000089 + 0.001372 = 0.00146 Supplemental Exercises 3-107. Let X denote the number of totes in the sample that do not conform to purity requirements. Then, X has a hypergeometric distribution with N = 15, n = 3, and K = 2. 2 13 0 3 P( X ≥ 1) = 1 − P( X = 0) = 1 − = 1 − 13!12! = 0.3714 15 10! ! 15 3
3-109.Let Y denote the number of calls needed to obtain an answer in less than 30 seconds. a) P (Y = 4) = (1 − 0.75) 0.75 = 0.25 3 0.75 = 0.0117 3 b) E(Y) = 1/p = 1/0.75 = 1.3333 e −5 5 5 3-111. a) Let X denote the number of messages sent in one hour. P( X = 5) = = 0.1755 5! b) Let Y denote the number of messages sent in 1.5 hours. Then, Y is a Poisson random variable with e −7.5 (7.5)10 λ =7.5. P(Y = 10) = = 0.0858 10! c) Let W denote the number of messages sent in one-half hour. Then, W is a Poisson random variable with λ = 2.5. P (W < 2) = P (W = 0) + P (W = 1) = 0.2873 3-119. Let X denote the number of products that fail during the warranty period. Assume the units are independent. Then, X is a binomial random variable with n = 500 and p = 0.02. 500 a) P(X = 0) = 0 (0.02) (0.98) = 4.1 x 10 0 500 -5 b) E(X) = 500(0.02) = 10 c) P(X >2) = 1 − P(X ≤ 1) = 0.9995 3-121. a) P(X ≤ 3) = 0.2 + 0.4 = 0.6 b) P(X > 2.5) = 0.4 + 0.3 + 0.1 = 0.8 c) P(2.7 < X < 5.1) = 0.4 + 0.3 = 0.7 d) E(X) = 2(0.2) + 3(0.4) + 5(0.3) + 8(0.1) = 3.9 e) V(X) = 22(0.2) + 32(0.4) + 52(0.3) + 82(0.1) − (3.9)2 = 3.09 3-125. Let X denote the number of orders placed in a week in a city of 800,000 people. Then X is a Poisson random variable with λ = 0.25(8) = 2. a) P(X ≥ 3) = 1 − P(X ≤ 2) = 1 − [e-2 + e-2(2) + (e-222)/2!] = 1 − 0.6767 = 0.3233. b) Let Y denote the number of orders in 2 weeks. Then, Y is a Poisson random variable with λ = 4, and P(Y<2) = P(Y ≤ 1) = e-4 + (e-441)/1! = 0.0916. 3-127. Let X denote the number of totes in the sample that exceed the moisture content. Then X is a binomial random variable with n = 30. We are to determine p. 30 0 If P(X ≥ 1) = 0.9, then P(X = 0) = 0.1. Then ( p) (1 − p )30 = 0.1 , giving 30ln(1−p)=ln(0.1), 0 which results in p = 0.0738. 3-129. a) Let X denote the number of flaws in 50 panels. Then, X is a Poisson random variable with λ = 50(0.02) = 1. P(X = 0) = e-1 = 0.3679. b) Let Y denote the number of flaws in one panel, then P(Y ≥ 1) = 1 − P(Y=0) = 1 − e-0.02 = 0.0198. Let W denote the number of panels that need to be inspected before a flaw is found. Then W is a geometric random variable with p = 0.0198 and E(W) = 1/0.0198 = 50.51 panels. −0.02 c.) P (Y ≥ 1) = 1 − P (Y = 0) = 1 − e = 0.0198 Let V denote the number of panels with 2 or more flaws. Then V is a binomial random variable with n=50 and p=0.0198
50 50 P(V ≤ 2) = 0.0198 0 (.9802) 50 + 0.01981 (0.9802) 49 0 1 50 + 0.0198 2 (0.9802) 48 = 0.9234 2
Chapter 4 SelectedProblem Solutions Section 4-2 ∞ ∞ 4-1. ∫ a) P (1 < X ) = e − x dx = (−e − x ) 1 1 = e −1 = 0.3679 2.5 2.5 ∫e −x b) P (1 < X < 2.5) = dx = (−e− x ) = e −1 − e− 2.5 = 0.2858 1 1 3 ∫ c) P ( X = 3) = e − x dx = 0 3 4 4 ∫ d) P ( X < 4) = e − x dx = (−e − x ) = 1 − e − = 0.9817 4 0 0 ∞ ∞ ∫ e) P (3 ≤ X ) = e− x dx = (−e − x ) 3 3 = e − 3 = 0.0498 4 4 x x2 4 2 − 32 4-3 a) P ( X < 4) = ∫ dx = = = 0.4375 , because f X ( x) = 0 for x < 3. 3 8 16 3 16 5 5 x x2 5 2 − 3.5 2 b) , P ( X > 3.5) = ∫ dx = = = 0.7969 because f X ( x) = 0 for x > 5. 3. 5 8 16 3.5 16 5 2 5 x x 52 − 4 2 c) P (4 < X < 5) = ∫ 8 dx = 16 4 = 16 = 0.5625 4 4.5 2 4.5 x x 4.5 2 − 3 2 d) P ( X < 4.5) = ∫ 8 dx = 16 3 = 16 = 0.7031 3 5 3.5 5 3.5 x x x2 x2 52 − 4.52 3.52 − 32 e) P( X > 4.5) + P( X < 3.5) = ∫ dx + ∫ dx = + = + = 0.5 . 4.5 8 3 8 16 4.5 16 3 16 16 4-9 a) P(X < 2.25 or X > 2.75) = P(X < 2.25) + P(X > 2.75) because the two events are mutually exclusive. Then, P(X < 2.25) = 0 and 2.8 P(X > 2.75) = ∫ 2dx = 2(0.05) = 0.10 . 2.75 b) If the probability density function is centered at 2.5 meters, then f X ( x) = 2 for 2.25 < x < 2.75 and all rods will meet specifications. Section 4-3 4-11. a) P(X<2.8) = P(X ≤ 2.8) because X is a continuous random variable. Then, P(X<2.8) =F(2.8)=0.2(2.8) = 0.56. b) P ( X > 1.5) = 1 − P ( X ≤ 1.5) = 1 − 0.2(1.5) = 0.7
c) P (X < −2) = FX (−2) = 0 d) P ( X > 6) = 1 − FX (6) = 0 x x −x 4-13. Now, f X ( x ) = e ∫ for 0 < x and F X ( x) = e − x dx = − e − x 0 0 = 1− e−x 0, x ≤ 0 for 0 < x. Then, FX ( x) = −x 1 − e , x > 0 x x 4-21. F ( x) = ∫ 0.5 xdx = 0.5 x 2 2 = 0.25 x 2 for 0 < x < 2. Then, 0 0 0, x<0 F ( x) = 0.25 x 2 , 0≤ x<2 1, 2≤x Section 4-4 5 5 x x3 53 − 33 4-25. E ( X ) = ∫ x dx = = = 4.083 3 8 24 3 24 5 5 x V ( X ) = ∫ ( x − 4.083) 2 dx = ∫ x 2 8 dx − 4.083 2 x 3 8 3 5 x4 = − 4.083 2 = 0.3291 32 3 120 600 120 4-27. a.) E ( X ) = ∫x 100 x 2 dx = 600 ln x 100 = 109.39 120 120 600 (109.39 ) 2 V ( X ) = ∫ ( x − 109.39) 2 dx = 600 ∫ 1 − 2 (109.39 ) x + x2 dx 100 x2 100 120 = 600( x − 218.78 ln x − 109.39 2 x −1 ) 100 = 33.19 b.) Average cost per part = $0.50109.39 = $54.70
Section 4-5 4-33. a) f(x)= 2.0 for 49.75 < x < 50.25. E(X) = (50.25 + 49.75)/2 = 50.0, (50.25 − 49.75) 2 V (X ) = = 0.0208, and σ x = 0.144 . 12 x b) F ( x) = ∫ 2.0dx for 49.75 < x < 50.25. 49.75 Therefore, 0, x < 49.75 F ( x) = 2 x − 99.5, 49.75 ≤ x < 50.25 1, 50.25 ≤ x c) P ( X < 50.1) = F (50.1) = 2(50.1) − 99.5 = 0.7 (1.5 + 2.2) 4-35 E( X ) = = 1.85 min 2 (2.2 − 1.5) 2 V (X ) = = 0.0408 min 2 12 2 2 1 2 b) P ( X < 2) = ∫ dx = ∫ 0.7 dx = 0.7 x 1.5 = 0.7(.5) = 0.7143 1. 5 (2.2 − 1.5) 1.5 x x 1 x c.) F ( X ) = ∫5 (2.2 − 1.5) dx = 1∫50.7dx = 0.7 x 1.5 1. . for 1.5 < x < 2.2. Therefore, 0, x < 1.5 F ( x) = 0.7 x − 2.14, 1.5 ≤ x < 2.2 1, 2.2 ≤ x Section 4-6 4-41 a) P(Z < 1.28) = 0.90 b) P(Z < 0) = 0.5 c) If P(Z > z) = 0.1, then P(Z < z) = 0.90 and z = 1.28 d) If P(Z > z) = 0.9, then P(Z < z) = 0.10 and z = −1.28 e) P(−1.24 < Z < z) = P(Z < z) − P(Z < −1.24) = P(Z < z) − 0.10749. Therefore, P(Z < z) = 0.8 + 0.10749 = 0.90749 and z = 1.33
4-43.a) P(X < 13) = P(Z < (13−10)/2) = P(Z < 1.5) = 0.93319 b) P(X > 9) = 1 − P(X < 9) = 1 − P(Z < (9−10)/2) = 1 − P(Z < −0.5) = 1 − [1− P(Z < 0.5)] = P(Z < 0.5) = 0.69146. 6 − 10 14 − 10 c) P(6 < X < 14) = P <Z< 2 2 = P(−2 < Z < 2) = P(Z < 2) −P(Z < − 2)] = 0.9545. 2 − 10 4 − 10 d) P(2 < X < 4) = P <Z< 2 2 = P(−4 < Z < −3) = P(Z < −3) − P(Z < −4) = 0.00135 e) P(−2 < X < 8) = P(X < 8) − P(X < −2) 8 − 10 −2 − 10 = P Z < − P Z < 2 2 = P(Z < −1) − P(Z < −6) = 0.15866. 45 − 65 4-51. a) P(X <45) = P Z < 5 = P(Z < -3) = 0.00135 65 − 60 b) P(X > 65) = P Z > 5 = PZ >1) = 1- P(Z < 1) = 1 - 0.841345 = 0.158655 x − 60 c) P(X < x) = P Z < = 0.99. 5 x − 60 Therefore, 5 = 2.33 and x = 71.6 4-55. a) P(X > 90.3) + P(X < 89.7) 90.3 − 90.2 89.7 − 90.2 = P Z > + P Z < 0.1 0.1 = P(Z > 1) + P(Z < −5) = 1 − P(Z < 1) + P(Z < −5)
=1 − 0.84134+0 = 0.15866. Therefore, the answer is 0.15866. b) The process mean should be set at the center of the specifications; that is, at µ = 90.0. 89.7 − 90 90.3 − 90 c) P(89.7 < X < 90.3) = P <Z< 0.1 0.1 = P(−3 < Z < 3) = 0.9973. The yield is 1000.9973 = 99.73% 0.0026 − 0.002 4-59. a) P(X > 0.0026) = P Z > 0.0004 = P(Z > 1.5) = 1-P(Z < 1.5) = 0.06681. 0.0014 − 0.002 0.0026 − 0.002 b) P(0.0014 < X < 0.0026) = P <Z< 0.0004 0.0004 = P(−1.5 < Z < 1.5) = 0.86638. 0.0014 − 0.002 0.0026 − 0.002 c) P(0.0014 < X < 0.0026) = P <Z< σ σ − 0.0006 0.0006 = P <Z< . σ σ 0.0006 Therefore, P Z < = 0.9975. Therefore, 0 . 0006 = 2.81 and σ = 0.000214. σ σ Section 4-7 4-67 Let X denote the number of errors on a web site. Then, X is a binomial random variable with p = 0.05 and n = 100. Also, E(X) = 100 (0.05) = 5 and V(X) = 100(0.05)(0.95) = 4.75 1− 5 P( X ≥ 1) ≅ P Z ≥ = P( Z ≥ −1.84) = 1 − P( Z < −1.84) = 1 − 0.03288 = 0.96712 4.75 4-69 Let X denote the number of hits to a web site. Then, X is a Poisson random variable with a of mean 10,000 per day. E(X) = λ = 10,000 and V(X) = 10,000 a) 10,200 − 10,000 P( X ≥ 10,200) ≅ P Z ≥ = P ( Z ≥ 2) = 1 − P( Z < 2) 10,000 = 1 − 0.9772 = 0.0228
Expected value ofhits days with more than 10,200 hits per day is (0.0228)365=8.32 days per year b.) Let Y denote the number of days per year with over 10,200 hits to a web site. Then, Y is a binomial random variable with n=365 and p=0.0228. E(Y) = 8.32 and V(Y) = 365(0.0228)(0.9772)=8.13 15 − 8.32 P(Y > 15) ≅ P Z ≥ = P( Z ≥ 2.34) = 1 − P( Z < 2.34) 8.13 = 1 − 0.9904 = 0.0096 Section 4-9 4-77. Let X denote the time until the first call. Then, X is exponential and λ = E (1X ) = 15 calls/minute. 1 ∞ x x ∞ − − a) P ( X > 30) = ∫ 30 1 15 e 15 dx = − e 15 30 = e − 2 = 0.1353 b) The probability of at least one call in a 10-minute interval equals one minus the probability of zero calls in a 10-minute interval and that is P(X > 10). − x ∞ P( X > 10) = − e 15 = e − 2 / 3 = 0.5134 . 10 Therefore, the answer is 1- 0.5134 = 0.4866. Alternatively, the requested probability is equal to P(X < 10) = 0.4866. x 10 − 15 c) P (5 < X < 10) = − e = e −1 / 3 − e − 2 / 3 = 0.2031 5 − t x d) P(X < x) = 0.90 and P ( X < x) = − e 15 = 1 − e − x / 15 = 0.90 . Therefore, x = 34.54 0 minutes. 4-79. Let X denote the time to failure (in hours) of fans in a personal computer. Then, X is an exponential random variable and λ = 1 / E ( X ) = 0.0003 . ∞ ∞ ∫ 0.0003e − x 0.0003 − x 0.0003 a) P(X > 10,000) = dx = − e = e −3 = 0.0498 10 , 000 10 , 000 7 , 000 7 , 000 ∫ 0.0003e − x 0.0003 b) P(X < 7,000) = dx = − e − x 0.0003 = 1 − e − 2.1 = 0.8775 0 0 4-81. Let X denote the time until the arrival of a taxi. Then, X is an exponential random variable with λ = 1 / E ( X ) = 0.1 arrivals/ minute.
∞ ∞ ∫ 0.1e dx = − e − 0. 1 x − 0.1 x a) P(X > 60) = = e − 6 = 0.0025 60 60 10 10 ∫ 0.1e dx = − e − 0.1 x − 0.1 x b) P(X < 10) = = 1 − e −1 = 0.6321 0 0 4-83. Let X denote the distance between major cracks. Then, X is an exponential random variable with λ = 1 / E ( X ) = 0.2 cracks/mile. ∞ ∞ ∫ 0.2e dx = − e − 0. 2 x − 0.2 x a) P(X > 10) = = e − 2 = 0.1353 10 10 b) Let Y denote the number of cracks in 10 miles of highway. Because the distance between cracks is exponential, Y is a Poisson random variable with λ = 10(0.2) = 2 cracks per 10 miles. e −2 2 2 P(Y = 2) = = 0.2707 2! c) σ X = 1 / λ = 5 miles. 4-87. Let X denote the number of calls in 3 hours. Because the time between calls is an exponential random variable, the number of calls in 3 hours is a Poisson random variable. Now, the mean time between calls is 0.5 hours and λ = 1 / 0.5 = 2 calls per hour = 6 calls in 3 hours. P( X ≥ 4) = 1 − P( X ≤ 3) = 1 − e 6 + e 6 + e 6 + e 6 = 0.8488 −6 0 −6 1 −6 2 −6 3 0! 1! 2! 3! Section 4-10 4-97. Let Y denote the number of calls in one minute. Then, Y is a Poisson random variable with λ = 5 calls per minute. e −5 5 4 a) P(Y = 4) = = 0.1755 4! e −5 50 e −5 51 e −5 52 b) P(Y > 2) = 1 - P (Y ≤ 2) = 1 − − − = 0.8754 . 0! 1! 2! Let W denote the number of one minute intervals out of 10 that contain more than 2 calls. Because the calls are a Poisson process, W is a binomial random variable with n = 10 and p = 0.8754. ( ) 10 10 0 Therefore, P(W = 10) = 10 0.8754 (1 − 0.8754) = 0.2643 . 4-101. Let X denote the number of bits until five errors occur. Then, X has an Erlang distribution with r = 5 and λ = 10 −5 error per bit.
r a) E(X) = = 5 × 105 bits. λ r b) V(X) = 2 = 5 × 10 and σ X = 5 × 10 = 223607 bits. 10 10 λ c) Let Y denote the number of errors in 105 bits. Then, Y is a Poisson random variable with λ = 1 / 105 = 10−5 error per bit = 1 error per 105 bits. −1 0 [ P(Y ≥ 3) = 1 − P(Y ≤ 2) = 1 − e 0!1 + e 1!1 + e 2!1 = 0.0803 −1 1 −1 2 ] 4-105. a) Γ(6) = 5!= 120 b) Γ( 5 ) = 3 Γ( 3 ) = 2 2 2 3 1 2 2 Γ( 1 ) = 3 π 1 / 2 = 1.32934 2 4 c) Γ( 9 ) = 7 Γ( 7 ) = 7 5 3 1 Γ( 1 ) = 105 π 1 / 2 = 11.6317 2 2 2 2 2 2 2 2 16 Section 4-11 4-109. β=0.2 and δ=100 hours E ( X ) = 100Γ(1 + 1 0. 2 ) = 100 × 5!= 12,000 V ( X ) = 100 2 Γ(1 + 2 0.2 ) − 100 2 [Γ(1 + 1 0.2 )]2 = 3.61 × 1010 4-111. Let X denote lifetime of a bearing. β=2 and δ=10000 hours 2 8000 − 2 a) P( X > 8000) = 1 − FX (8000) = e 10000 = e − 0.8 = 0.5273 b) E ( X ) = 10000Γ(1 + 1 ) = 10000Γ(1.5) 2 = 10000(0.5)Γ(0.5) = 5000 π = 8862.3 = 8862.3 hours c) Let Y denote the number of bearings out of 10 that last at least 8000 hours. Then, Y is a binomial random variable with n = 10 and p = 0.5273. ( ) P(Y = 10) = 10 0.527310 (1 − 0.5273) 0 = 0.00166 . 10 Section 4-12 4-117 X is a lognormal distribution with θ=5 and ω2=9 a. ) ln(13330) − 5 P( X < 13300) = P(e W < 13300) = P (W < ln(13300)) = Φ 3 = Φ(1.50) = 0.9332 b.) Find the value for which P(X≤x)=0.95
ln( x)− 5 P( X ≤ x) = P(e W ≤ x) = P(W < ln( x)) = Φ = 0.95 3 ln( x) − 5 = 1.65 x = e 1.65(3) + 5 = 20952.2 3 2 c.) µ = E ( X ) = e θ +ω = e 5+ 9 / 2 = e 9.5 = 13359.7 /2 2 2 V ( X ) = e 2θ +ω (e ω − 1) = e 10 + 9 (e 9 − 1) = e 19 (e 9 − 1) = 1.45 × 1012 4-119 a.) X is a lognormal distribution with θ=2 and ω2=4 ln(500) − 2 P( X < 500) = P(e W < 500) = P(W < ln(500)) = Φ 2 = Φ(2.11) = 0.9826 b.) P(1000 < X < 1500) P( X < 15000 | X > 1000) = P( X > 1000) ln(1500) − 2 ln(1000) − 2 Φ 2 − Φ 2 = ln(1000) − 2 1 − Φ 2 Φ(2.66) − Φ(2.45) 0.9961 − 0.9929 = = = 0.0032 / 0.007 = 0.45 (1 − Φ(2.45) ) (1 − 0.9929) c.) The product has degraded over the first 1000 hours, so the probability of it lasting another 500 hours is very low. 4-121 Find the values of θand ω2 given that E(X) = 100 and V(X) = 85,000
100 2 2 x = y 85000 = e 2θ +ω (eω − 1) 2 let x = eθ and y = e ω 2 2 2 2 then (1) 100 = x y and (2) 85000= x y( y −1) = x y − x y 2 Square (1) 10000 = x y and substitute into (2) 85000 = 10000 ( y − 1) y = 9 .5 100 Substitute y into (1) and solve for x x = = 32.444 9.5 θ = ln(32.444) = 3.45 and ω 2 = ln(9.5) = 2.25 Supplemental Exercises 4-127. Let X denote the time between calls. Then, λ = 1 / E ( X ) = 0.1 calls per minute. 5 5 ∫ a) P ( X < 5) = 0.1e − x dx = −e − x = 1 − e − 0.5 = 0.3935 0.1 0.1 0 0 15 b) P (5 < X < 15) = −e − 0.1 x = e − 0.5 − e −1.5 = 0.3834 5 x ∫ c) P(X < x) = 0.9. Then, P ( X < x) = 0.1e − t dt = 1 − e − x = 0.9 . Now, x = 23.03 0.1 0.1 0 minutes. 4-129. a) Let Y denote the number of calls in 30 minutes. Then, Y is a Poisson random variable e −3 3 0 e −3 31 e −3 3 2 with x = e θ . P(Y ≤ 2) = + + = 0.423 . 0! 1! 2! b) Let W denote the time until the fifth call. Then, W has an Erlang distribution with λ = 0.1 and r = 5. E(W) = 5/0.1 = 50 minutes 4-137. Let X denote the thickness. 5.5 − 5 a) P(X > 5.5) = P Z > = P(Z > 2.5) = 0. 0062 0.2 4.5 − 5 5.5 − 5 b) P(4.5 < X < 5.5) = P <Z < = P (-2.5 < Z < 2.5) = 0.9876 0.2 0.2 Therefore, the proportion that do not meet specifications is 1 − P(4.5 < X < 5.5) = 0.012.
x −5 x −5 c) If P(X < x) = 0.90, then P Z > = 0.9. Therefore, = 1.65 and x = 5.33. 0.2 0.2 4-139. If P(0.002-x < X < 0.002+x), then P(-x/0.0004 < Z < x/0.0004) = 0.9973. Therefore, x/0.0004 = 3 and x = 0.0012. The specifications are from 0.0008 to 0.0032. 10 , 000 − µ 10, 000− µ 4-141. If P(X > 10,000) = 0.99, then P(Z > 600 ) = 0.99. Therefore, 600 = -2.33 and µ = 11,398 . 4-143 X is an exponential distribution with E(X) = 7000 hours 5800 x 5800 1 − − a.) P ( X < 5800) = ∫ 0 7000 e 7000 dx = 1 − e 7000 = 0.5633 ∞ x x 1 − − b.) P ( X > x ) = ∫ e 7000 dx =0.9 Therefore, e 7000 = 0.9 x 7000 and x = −7000 ln(0.9) = 737.5 hours
Chapter 5 SelectedProblem Solutions Section 5-1 5-7. E ( X ) = 1[ f XY (1,1) + f XY (1,2) + f XY (1,3)] + 2[ f XY (2,1) + f XY (2,2) + f XY (2,3)] + 3[ f XY (3,1) + f XY (3,2) + f XY (3,3)] = (1 × 36 ) + (2 × 12 ) + (3 × 15 ) = 13 / 6 = 2.167 9 36 36 V ( X ) = (1 − 13 ) 2 6 9 36 + (2 − 13 ) 2 6 12 36 + (3 − 13 ) 2 6 15 36 = 0.639 E (Y ) = 2.167 V (Y ) = 0.639 5-11. E ( X ) = −1( 1 ) − 0.5( 1 ) + 0.5( 1 ) + 1( 1 ) = 8 4 2 8 1 8 E (Y ) = −2( 1 ) − 1( 1 ) + 1( 1 ) + 2( 1 ) = 8 4 2 8 1 4 5-15 a) The range of (X,Y) is X ≥ 0, Y ≥ 0 and X + Y ≤ 4 . X is the number of pages with moderate graphic content and Y is the number of pages with high graphic output out of 4. x=0 x=1 x=2 x=3 x=4 -05 y=4 5.35x10 0 0 0 0 y=3 0.00183 0.00092 0 0 0 y=2 0.02033 0.02066 0.00499 0 0 y=1 0.08727 0.13542 0.06656 0.01035 0 y=0 0.12436 0.26181 0.19635 0.06212 0.00699 b.) x=0 x=1 x=2 x=3 x=4 f(x) 0.2338 0.4188 0.2679 0.0725 0.0070 c.) E(X)= 4 ∑x 0 i f ( xi ) = 0(0.2338) + 1(0.4188) + 2(0.2679) + 3(0.7248) = 4(0.0070) = 1.2 f XY (3, y ) d.) f Y 3 ( y) = , fx(3) = 0.0725 f X (3) y fY|3(y) 0 0.857 1 0.143 2 0 3 0 4 0 e) E(Y|X=3) = 0(0.857)+1(0.143) = 0.143
Section 5-2 5-17. a) P( X = 2) = f XYZ (2,1,1) + f XYZ (2,1,2) + f XYZ (2,2,1) + f XYZ (2,2,2) = 0.5 b) P( X = 1, Y = 2) = f XYZ (1,2,1) + f XYZ (1,2,2) = 0.35 c) P( Z < 1.5) = f XYZ (1,1,1) + f XYZ (1,2,2) + f XYZ (2,1,1) + f XYZ (2,2,1) = 0.5 d) P( X = 1 or Z = 1) = P( X = 1) + P( Z = 1) − P( X = 1, Z = 1) = 0.5 + 0.5 − 0.2 = 0.8 e) E(X) = 1(0.5) + 2(0.5) = 1.5 5-25. P(X=x, Y=y, Z=z) is the number of subsets of size 4 that contain x printers with graphics enhancements, y printers with extra memory, and z printers with both features divided by the number of subsets of size 4. From the results on the CD material on counting techniques, it can be shown that ( )( )( ) 4 x 5 y 6 z P ( X = x, Y = y , Z = z ) = ( ) 15 for x+y+z = 4. 4 a) P ( X = 1, Y = 2, Z = 1) = ( )( )( ) = 0.1758 4 5 1 2 6 1 ( ) 15 4 b) P ( X = 1, Y = 1) = P ( X = 1, Y = 1, Z = 2) = ( )( )( ) = 0.2198 4 1 1 5 6 2 ( ) 15 4 c) The marginal distribution of X is hypergeometric with N = 15, n = 4, K = 4. Therefore, E(X) = nK/N = 16/15 and V(X) = 4(4/15)(11/15)[11/14] = 0.6146. P( X = 2, Y = 2) 0.1944 5-29 a.) P( X = 2 | Y = 2) = = = 0.7347 P(Y = 2) 0.2646 P( X = 2, Y = 2) = 0.1922 4 P(Y = 2) = 0.3 2 0.7 4 = 0.2646 2 from the binomial marginal distribution of Y b) Not possible, x+y+z=4, the probability is zero. c.) P( X | Y = 2) = P( X = 0 | Y = 2), P( X = 1 | Y = 2), P( X = 2 | Y = 2) P( X = 0, Y = 2) 4! P( X = 0 | Y = 2) = = 0.6 0 0.3 2 0.12 0.2646 = 0.0204 P(Y = 2) 0!2!2! P ( X = 1, Y = 2) 4! P ( X = 1 | Y = 2) = = 0.610.3 2 0.11 0.2646 = 0.2449 P(Y = 2) 1!2!1! P( X = 2, Y = 2) 4! P( X = 2 | Y = 2) = = 0.6 2 0.3 2 0.10 0.2646 = 0.7347 P(Y = 2) 2!2!0! d.) E(X|Y=2)=0(0.0204)+1(0.2449)+2(0.7347) = 1.7142 5-31 a.), X has a binomial distribution with n = 3 and p = 0.01. Then, E(X) = 3(0.01) = 0.03 and V(X) = 3(0.01)(0.99) = 0.0297.
P( X |Y = 2) b.) first find P(Y = 2) = P( X = 1, Y = 2, Z = 0) + P( X = 0, Y = 2, Z = 1) 3! 3! = 0.01(0.04) 2 0.95 0 + 0.010 (0.04) 2 0.951 = 0.0046 1!2!0! 0!2!1! P( X = 0, Y = 2) 3! P( X = 0 | Y = 2) = = 0.010 0.04 2 0.951 0.004608 = 0.98958 P(Y = 2) 0!2!1! P( X = 1, Y = 2) 3! P( X = 1 | Y = 2) = = 0.0110.04 2 0.95 0 0.004608 = 0.01042 P(Y = 2) 1!2!1! E ( X | Y = 2) = 0(0.98958) + 1(0.01042) = 0.01042 V ( X | Y = 2) = E ( X 2 ) − ( E ( X )) 2 = 0.01042 − (0.01042) 2 = 0.01031 Section 5-3 3 2 3 5-35. a) P( X < 2, Y < 3) = 4 81 ∫ ∫ xydxdy = 0 0 4 81 (2) ∫ ydy = 81 (2)( 9 ) = 0.4444 0 4 2 b) P(X < 2.5) = P(X < 2.5, Y < 3) because the range of Y is from 0 to 3. 3 2. 5 3 P( X < 2.5, Y < 3) = 4 81 ∫ ∫ xydxdy = 0 0 4 81 (3.125) ∫ ydy = 81 (3.125) 9 = 0.6944 4 0 2 2. 5 3 2.5 2.5 y2 c) P(1 < Y < 2.5) = 4 81 ∫ ∫ xydxdy = 1 0 4 81 (4.5) ∫ ydy = 18 1 81 2 1 =0.5833 2.5 3 2.5 2 d) P( X > 1.8,1 < Y < 2.5) = 4 81 ∫ ∫ xydxdy = 1 1.8 4 81 (2.88) ∫ ydy = 1 4 81 (2.88) ( 2.52 −1) =0.3733 3 3 3 3 2 ∫∫x ∫ 9 ydy = 4 y 2 e) E( X ) = 4 81 ydxdy = 4 81 9 2 =2 0 0 0 0 4 0 4 f) P( X < 0, Y < 4) = 4 81 ∫ ∫ xydxdy = 0∫ ydy = 0 0 0 0
5-37. 3 x+2 3 x+2 y2 c ∫ ∫ ( x + y )dydx = ∫ xy + 2 dx 0 x 0 x [ ]dx 3 ( x+ 2)2 = ∫ x( x + 2) + 2 − x2 − x2 2 0 3 = c ∫ (4 x + 2)dx = 2 x 2 + 2 x [ ] 3 0 = 24c 0 Therefore, c = 1/24. 5-39. a) f X (x) is the integral of f XY ( x, y ) over the interval from x to x+2. That is, x+2 1 1 y2 x+2 x 1 f X ( x) = 24 ∫ ( x + y)dy = x 24 xy + 2 x = 6 + 12 for 0 < x < 3. 1 f XY (1, y ) (1+ y ) 1+ y b) f Y 1 ( y) = f X (1) = 24 1 1 = for 1 < y < 3. + 6 12 6 See the following graph, y 2 f (y) defined over this line segment Y|1 1 0 1 2 x 0 3 3 3 1+ y 1 1 y2 y3 ∫ 6 61 dy = ∫ ( y + y )dy = = 2.111 2 c) E(Y|X=1) = y + 1 6 2 3 1 2 3 3 1+ y 1 1 y2 d.) P (Y > 2 | X = 1) = ∫ dy = ∫ (1 + y )dy = y + =0.4167 2 6 61 6 2 1 f XY ( x , 2 ) e.) f X 2 ( x) = fY ( 2) . Here f Y ( y) is determined by integrating over x. There are three regions of integration. For 0< y≤2 the integration is from 0 to y. For 2< y≤3 the integration is from y-2 to y. For 3 < y < 5 the integration is from y to 3. Because the condition is x=2, only the first integration is y 1 1 x2 y y2 needed. fY ( y) = ∫ 24 0 ( x + y )dx = 2 + xy 0 = 24 16 for 0 < y ≤ 2.
y f X|2 (x) defined over this line segment 2 1 0 1 2 x 0 1 ( x + 2) 24 x+2 Therefore, fY (2) = 1 / 4 and f X 2 ( x) = = for 0 < x < 2 1/ 4 6 5-43. Solve for c ∞ x ∞ ∞ c −2 x c −2 x c ∫ ∫ e − 2 x −3 y dyd x = ∫ e (1 − e )d x = 3 ∫ e − e d x −3 x −5 x 0 0 30 0 c 1 1 1 = − = c. c = 10 3 2 5 10 5-49. The graph of the range of (X, Y) is y 5 4 3 2 1 0 1 2 3 4 x 1 x +1 4 x +1 ∫ ∫ cdydx + ∫ ∫ cdydx = 1 0 0 1 x −1 1 4 = c ∫ ( x + 1)dx + 2c ∫ dx 0 1 = c + 6c = 7.5c = 1 3 2 Therefore, c = 1/7.5=2/15 5-51. a. ) x +1 1 x +1 f ( x) = ∫ 0 7.5 dy = for 7.5 0 < x < 1, x +1 1 x + 1 − ( x − 1) 2 f ( x) = x −1 ∫7.5 dy = 7.5 = 7.5 for 1 < x < 4
b. ) f XY (1, y ) 1 / 7.5 f Y | X =1 ( y ) = = = 0.5 f X (1) 2 / 7.5 f Y | X =1 ( y ) = 0.5 for 0 < y < 2 2 2 y y2 c. ) E (Y | X = 1) = ∫ dy = =1 0 2 4 0 0.5 0.5 d.) P (Y < 0.5 | X = 1) = ∫ 0.5dy = 0.5 y = 0.25 0 0 5-53 a.) µ=3.2 λ=1/3.2 ∞ ∞ − x − y ∞ − x − 352 P ( X > 5 , Y > 5 ) = 10 . 24 ∫ ∫ e 3 .2 3 .2 dydx = 3 . 2 ∫ e 3 .2 e . dx 5 5 5 −5 − 352 = e 3 .2 e . = 0 . 0439 ∞∞ − x − y ∞ − x − 3.2 10 P( X > 10, Y > 10) = 10.24 ∫ ∫ e 3.2 3.2 dydx = 3.2 ∫ e 3.2 e dx 10 10 10 − 10 − 10 = e 3.2 e 3.2 = 0.0019 b.) Let X denote the number of orders in a 5-minute interval. Then X is a Poisson random variable with λ=5/3.2 = 1.5625. e −1.5625 (1.5625) 2 P( X = 2) = = 0.256 21 2 For both systems, P ( X = 2) P ( X = 2) = 0.256 = 0.0655 c.) The joint probability distribution is not necessary because the two processes are independent and we can just multiply the probabilities. Section 5-4 0. 5 1 1 0.5 1 0.5 0.5 ∫ ∫ ∫ (8 xyz)dzdydx = ∫ ∫ (4 xy)dydx = ∫ (2 x)dx = x 2 5-55. a) P( X < 0.5) = = 0.25 0 0 0 0 0 0 0 b)
0.5 0.5 1 P( X < 0.5, Y < 0.5) = ∫ ∫ ∫ (8 xyz)dzdydx 0 0 0 0.5 0.5 0.5 0.5 = ∫ 0 0 ∫ (4 xy)dydx = ∫ (0.5 x)dx = 0 x2 4 0 = 0.0625 c) P(Z < 2) = 1, because the range of Z is from 0 to 1. d) P(X < 0.5 or Z < 2) = P(X < 0.5) + P(Z < 2) - P(X < 0.5, Z < 2). Now, P(Z < 2) =1 and P(X < 0.5, Z < 2) = P(X < 0.5). Therefore, the answer is 1. 1 1 1 1 e) E ( X ) = ∫ ∫ ∫ (8 x yz )dzdydx = ∫ (2 x 2 )dx = 2 2 x3 3 = 2/3 0 0 0 0 1 5-57. a) fYZ ( y, z ) = ∫ (8 xyz )dx = 4 yz for 0 < y < 1 and 0 < z < 1. 0 f XYZ ( x, y, z ) 8 x(0.5)(0.8) Then, f X YZ ( x) = = = 2x for 0 < x < 1. fYZ ( y, z ) 4(0.5)(0.8) 0.5 b) Therefore, P( X < 0.5 Y = 0.5, Z = 0.8) = ∫ 2 xdx = 0.25 0 5-61 Determine c such that f ( xyz ) = c is a joint density probability over the region x>0, y>0 and z>0 with x+y+z<1 1 1− x 1− x − y 1 1− x 1 2 1− x f ( xyz ) = c ∫ c( y − xy − y ) dx ∫ ∫ dzdydx =∫ ∫ c(1 − x − y )dydx = ∫ 2 0 0 0 0 0 0 0 1 1 (1 − x) 2 1 (1 − x )2 1 x2 x3 = ∫ c (1 − x) − x(1 − x) − dx = ∫ c dx = c x − + 0 2 0 2 2 2 6 0 1 = c . Therefore, c = 6. 6 5-63 a.) 1− x 1− x 1− x − y 1− x y2 f ( x) = 6 ∫ ∫ dzdy = ∫ 6(1 − x − y)dy = y − xy − 2 0 0 0 0 x2 1 = 6( − x + ) = 3( x − 1) 2 for 0 < x < 1 2 2 b.) 1− x − y f ( x, y ) = 6 ∫ dz = 6(1 − x − y ) 0 for x > 0 , y > 0 and x + y < 1 c.)
f ( x,y = 0.5, z = 0,5) 6 f ( x | y = 0.5, z = 0.5) = = = 1 For, x = 0 f ( y = 0.5, z = 0.5) 6 2 d. ) The marginal f Y ( y ) is similar to f X (x) and f Y ( y ) = 3(1 − y ) for 0 < y < 1. f ( x,0.5) 6(0.5 − x) f X |Y ( x | 0.5) = = = 4(1 − 2 x) for x < 0.5 f Y (0.5) 3(0.25) 5-65. 5-65. a) Let X denote the weight of a brick. Then, P( X > 2.75) = P( Z > 2.75 − 3 0.25 ) = P( Z > −1) = 0.84134 . Let Y denote the number of bricks in the sample of 20 that exceed 2.75 pounds. Then, by independence, Y has a binomial distribution with n = 20 and p = 0.84134. Therefore, 20 ( ) 20 the answer is P (Y = 20) = 20 0.84134 = 0.032 . b) Let A denote the event that the heaviest brick in the sample exceeds 3.75 pounds. Then, P(A) = 1 - P(A') and A' is the event that all bricks weigh less than 3.75 pounds. As in part a., P(X < 3.75) = P(Z < 3) and P( A) = 1 − [ P( Z < 3)] 20 = 1 − 0.99865 20 = 0.0267 . Section 5-5 5-67. E(X) = 1(3/8)+2(1/2)+4(1/8)=15/8 = 1.875 E(Y) = 3(1/8)+4(1/4)+5(1/2)+6(1/8)=37/8 = 4.625 E(XY) = [1 × 3 × (1/8)] + [1 × 4 × (1/4)] + [2 × 5 × (1/2)] + [4 × 6 × (1/8)] = 75/8 = 9.375 σ XY = E ( XY ) − E ( X ) E (Y ) = 9.375 − (1.875)(4.625) = 0.703125 V(X) = 12(3/8)+ 22(1/2) +42(1/8)-(15/8)2 = 0.8594 V(Y) = 32(1/8)+ 42(1/4)+ 52(1/2) +62(1/8)-(15/8)2 = 0.7344 σ XY 0.703125 ρ XY = = = 0.8851 σ XσY (0.8594)(0.7344) 5-69. 3 3 ∑ ∑ c( x + y) = 36c, x =1 y =1 c = 1 / 36 2 13 13 14 14 13 −1 E( X ) = E (Y ) = E ( XY ) = σ xy = − = 6 6 3 3 6 36 16 16 23 E( X 2 ) = E (Y 2 ) = V ( X ) = V (Y ) = 3 3 36 −1 ρ= 36 = −0.0435 23 23 36 36
2 + 2 + 1 x 1 5 x 1 19 ∫ ∫ 5-73. E( X ) = xdydx + ∫ ∫ xdydx = 2.614 0 0 19 1 x −1 1 x +1 2 + 5 x 1 2 19 ∫ ∫ ydydx + 19 ∫ x∫1 E (Y ) = ydydx = 2.649 0 0 1 − 1 x +1 2 + 5 x 1 2 19 ∫ ∫ xydydx + 19 ∫ x∫1 Now, E ( XY ) = xydydx = 8.7763 0 0 1 − σ xy = 8.7763 − (2.614)(2.649) = 1.85181 E ( X 2 ) = 8.7632 E (Y 2 ) = 9.07895 V ( x) = 1.930, V (Y ) = 2.062 1.852 ρ= = 0.9279 1.930 2.062 Section 5-6 5-81. Because ρ = 0 and X and Y are normally distributed, X and Y are independent. Therefore, µX = 0.1mm σX=0.00031mm µY = 0.23mm σY=0.00017mm Probability X is within specification limits is 0.099535 − 0.1 0.100465 − 0.1 P(0.099535 < X < 0.100465) = P <Z < 0.00031 0.00031 = P(−1.5 < Z < 1.5) = P( Z < 1.5) − P( Z < −1.5) = 0.8664 Probability that Y is within specification limits is 0.22966 − 0.23 0.23034 − 0.23 P(0.22966 < X < 0.23034) = P <Z< 0.00017 0.00017 = P(−2 < Z < 2) = P( Z < 2) − P( Z < −2) = 0.9545 Probability that a randomly selected lamp is within specification limits is (0.8664)(.9594)=0.8270 Section 5-7 5-87. a) E(2X + 3Y) = 2(0) + 3(10) = 30 b) V(2X + 3Y) = 4V(X) + 9V(Y) = 97 c) 2X + 3Y is normally distributed with mean 30 and variance 97. Therefore, P(2 X + 3Y < 30) = P( Z < 30 − 30 97 ) = P( Z < 0) = 0.5 d) P(2 X + 3Y < 40) = P( Z < 40 −30 97 ) = P( Z < 1.02) = 0.8461 5-89 a) Let T denote the total thickness. Then, T = X + Y and E(T) = 4 mm, V(T) = 0.12 + 0.12 = 0.02mm 2 , and σ T = 0.1414 mm.
b) 4.3 − 4 P(T > 4.3) = P Z > = P( Z > 2.12) 0.1414 2.12) = 1 - 0.983 = 0.017 = 1 − P( Z < 2.12) = 1 − 0.983 = 0.0170 5-93. a) Let X denote the average fill-volume of 100 cans. σ X = 0.5 2 100 = 0.05 . 12 − 12.1 b) E( X ) = 12.1 andP( X < 12) = P Z < = P( Z < −2) = 0.023 0.05 12 − µ c) P( X < 12) = 0.005 implies that P Z < = 0.005. 0.05 12 − µ Then 0.05 = -2.58 and µ = 12.129 . 12 − 12.1 d.) P( X < 12) = 0.005 implies that P Z < = 0.005. σ / 100 Then 12 −12.1 = -2.58 and σ = 0.388 . σ / 100 12 − 12.1 e.) P( X < 12) = 0.01 implies that P Z < = 0.01. 0.5 / n Then 12−12.1 0.5 / n = -2.33 and n = 135.72 ≅ 136 . Supplemental Exercises 5-97. a) P ( X < 0.5, Y < 1.5) = f XY (0,1) + f XY (0,0) = 1 / 8 + 1 / 4 = 3 / 8 . b) P ( X ≤ 1) = f XY (0,0) + f XY (0,1) + f XY (1,0) + f XY (1,1) = 3 / 4 c) P (Y < 1.5) = f XY (0,0) + f XY (0,1) + f XY (1,0) + f XY (1,1) = 3 / 4 d) P ( X > 0.5, Y < 1.5) = f XY (1,0) + f XY (1,1) = 3 / 8 e) E(X) = 0(3/8) + 1(3/8) + 2(1/4) = 7/8. V(X) = 02(3/8) + 12(3/8) + 22(1/4) - 7/82 =39/64 E(Y) = 1(3/8) + 0(3/8) + 2(1/4) = 7/8. . V(Y) = 12(3/8) + 02(3/8) + 22(1/4) - 7/82 =39/64 1 1 1 1 1 y2 5-105. a) P( X < 1, Y < 1) = ∫ ∫ 1 18 x ydydx = ∫ 18 x 2 2 1 2 dx = 1 x3 36 3 = 108 1 0 0 0 0 0 2.5 2 2.5 2 2.5 y2 b) P( X < 2.5) = ∫∫ 0 0 1 18 x 2 ydydx = ∫ 0 1 18 x2 2 0 dx = 1 x3 9 3 0 = 0.5787 3 2 3 2 3 y2 c) P(1 < Y < 2.5) = ∫ ∫ 1 18 x ydydx = ∫ 18 x 2 2 1 2 dx = 12 1 x3 3 = 3 4 0 1 0 1 0
d) 3 1.5 3 1.5 3 y2 P( X > 2,1 < Y < 1.5) = ∫ ∫ 1 18 x 2 ydydx = ∫ 18 x 2 1 2 dx = 144 5 x3 3 2 1 2 1 2 = 95 432 = 0.2199 3 2 3 3 e) E ( X ) = ∫ ∫ 18 x 3 ydydx = ∫ 18 x 3 2dx = 1 1 1 x4 9 4 = 9 4 0 0 0 0 3 2 3 3 f) E (Y ) = ∫ ∫ 18 x 2 y 2 dydx = ∫ 18 x 2 8 dx = 1 1 3 4 x3 27 3 = 4 3 0 0 0 0 5-107. The region x2 + y 2 ≤ 1 and 0 < z < 4 is a cylinder of radius 1 ( and base area π ) and height 4. Therefore, 1 the volume of the cylinder is 4 π and f XYZ ( x, y, z) = for x2 + y 2 ≤ 1 and 0 < z < 4. 4π a) The region X 2 + Y 2 ≤ 0.5 is a cylinder of radius 0.5 and height 4. Therefore, 2 2 4 ( 0.5π ) P( X + Y ≤ 0.5) = 4π = 1/ 2 . b) The region X 2 + Y 2 ≤ 0.5 and 0 < z < 2 is a cylinder of radius 0.5 and height 2. Therefore, 2 2 2 ( 0.5π ) P( X + Y ≤ 0.5, Z < 2) = = 1/ 4 4π f ( x, y,1) c) f XY 1 ( x, y ) = XYZ and f Z ( z ) = ∫∫ 41 dydx = 1 / 4 π f Z (1) x 2 + y 2 ≤1 1 / 4π for 0 < z < 4. Then, f XY 1 ( x, y ) = = 1 π for x 2 + y 2 ≤ 1 . 1/ 4 4 1− x 2 4 d) f X ( x) = ∫ ∫ 1 4π dydz = ∫ 21 1 − x 2 dz = π 1 − x 2 π 2 for -1 < x < 1 0 − 1− x 2 0 5-111. Let X, Y, and Z denote the number of problems that result in functional, minor, and no defects, respectively. a) P( X = 2, Y = 5) = P( X = 2, Y = 5, Z = 3) = 10! 2!5!3! 0.2 2 0.5 5 0.3 3 = 0.085 b) Z is binomial with n = 10 and p = 0.3. c) E(Z) = 10(0.3) = 3. 5-115. Let X denote the average time to locate 10 parts. Then, E( X ) =45 and σX = 30 10 a) P( X > 60) = P ( Z > 60 − 45 30 / 10 ) = P( Z > 1.58) = 0.057 b) Let Y denote the total time to locate 10 parts. Then, Y > 600 if and only if X > 60. Therefore, the answer is the same as part a. 5-119 Let T denote the total thickness. Then, T = X1 + X2 and a.) E(T) = 0.5+1=1.5 mm V(T)=V(X1) +V(X2) + 2Cov(X1X2)=0.01+0.04+2(0.14)=0.078mm2 where Cov(XY)=ρσXσY=0.7(0.1)(0.2)=0.014
1 − 1.5 b.) P(T < 1) = P Z < = P( Z < −6.41) ≅ 0 0.078 c.) Let P denote the total thickness. Then, P = 2X1 +3 X2 and E(P) =2(0.5)+3(1)=4 mm V(P)=4V(X1) +9V(X2) + 2(2)(3)Cov(X1X2)=4(0.01)+9(0.04)+2(2)(3)(0.014)=0.568mm2 where Cov(XY)=ρσXσY=0.7(0.1)(0.2)=0.014 5-121 Let X and Y denote the percentage returns for security one and two respectively. If ½ of the total dollars is invested in each then ½X+ ½Y is the percentage return. E(½X+ ½Y)=5 million V(½X+ ½Y)=1/4 V(X)+1/4V(Y)-2(1/2)(1/2)Cov(X,Y) where Cov(XY)=ρσXσY=-0.5(2)(4)=-4 V(½X+ ½Y)=1/4(4)+1/4(6)-2=3 Also, E(X)=5 and V(X) = 4. Therefore, the strategy that splits between the securities has a lower standard deviation of percentage return.
Chapter 6 SelectedProblem Solutions Sections 6-1and 6-2 6-1. Sample average: n ∑x i =1 i 592.035 x= = = 74.0044 mm n 8 Sample variance: 8 ∑xi =1 i = 592.035 8 ∑xi =1 2 i = 43813.18031 2 n ∑ xi n xi − i =1 (592.035)2 ∑ 2 n 43813.18031 − 8 s 2 = i =1 = n −1 8 −1 0.0001569 = = 0.000022414 (mm) 2 7 Sample standard deviation: s = 0.000022414 = 0.00473 mm The sample standard deviation could also be found using n 2 ∑ (x i − x ) 8 ∑ (x i − x ) i =1 2 s= where = 0.0001569 n −1 i =1 Dot Diagram: .. ...: . -------+---------+---------+---------+---------+---------diameter 73.9920 74.0000 74.0080 74.0160 74.0240 74.0320 There appears to be a possible outlier in the data set. n ∑x i =1 i 5747 6-11. a) x= = = 7.184 n 8
2 n ∑ xi n 2 ∑ xi − i =1 412.853 − (57.47)2 n 8 0.003 b) s2 = i =1 = = = 0.000427 n −1 8 −1 7 s = 0.000427 = 0.02066 c) Examples: repeatability of the test equipment, time lag between samples, during which the pH of the solution could change, and operator skill in drawing the sample or using the instrument. 6-13. a) x = 65.85 s = 12.16 b) Dot Diagram : : . . . . .. .: .: . .:..: .. :: .... .. -+---------+---------+---------+---------+---------+-----temp 30 40 50 60 70 80 c) Removing the smallest observation (31), the sample mean and standard deviation become x = 66.86 s = 10.74 Section 6-3 6-15 a.) Stem-and-leaf display for Problem 6-15 cycles: unit = 100 1|2 represents 1200 1 0T|3 1 0F| 5 0S|7777 10 0o|88899 22 1|000000011111 33 1T|22222223333 (15) 1F|444445555555555 22 1S|66667777777 11 1o|888899 5 2|011 2 2T|22 b) No, only 5 out of 70 coupons survived beyond 2000 cycles. 6-19. Descriptive Statistics Variable N Median Q1 Q3 cycles 70 1436.5 1097.8 1735.0 6-25 Stem-and-leaf display for Problem 6-25. Yard: unit = 1.0 Note: Minitab has dropped the value to the right of the decimal to make this display. 4 23|2334 7 23o|677 15 24|00112444 19 24o|5578 32 25|0111122334444 45 25o|5555556677899 (15) 26|000011123334444 40 26o|566677888 31 27|0000112222233333444 12 27o|66788999 4 28|003
1 28o|5 n 100 ∑ xii =1 ∑x i =1 i 26070 Sample Mean x= = = = 260.7 yards n 100 100 Sample Standard Deviation 100 100 ∑ xi = 26070 i =1 and ∑x i =1 2 i =6813256 2 n ∑ xi ∑ xi − i =1 n 6813256 − (26070) 16807 n 2 2 s 2 = i =1 = 100 = n −1 100 − 1 99 2 = 169.7677 yards and s = 169.7677 = 13.03 yards Sample Median Variable N Median yards 100 261.15 Section 6-5 6-43. Descriptive Statistics Variable N Mean Median Tr Mean StDev SE Mean PMC 20 4.000 4.100 4.044 0.931 0.208 Variable Min Max Q1 Q3 PMC 2.000 5.200 3.150 4.800 a) Sample Mean: 4 b) Sample Variance: 0.867 Sample Standard Deviation: 0.931 c) 5 4 PMC 3 2 6-47. Descriptive Statistics Variable N Mean Median Tr Mean StDev SE Mean temperat 24 48.125 49.000 48.182 2.692 0.549 Variable Min Max Q1 Q3
temperat 43.000 52.000 46.000 50.000 a) Sample Mean: 48.125 Sample Median: 49 b) Sample Variance: 7.246 Sample Standard Deviation: 2.692 c) 52 51 50 49 temperatur 48 47 46 45 44 43 The data appear to be slightly skewed. Supplemental 6-75 a) Sample 1 Range = 4 Sample 2 Range = 4 Yes, the two appear to exhibit the same variability b) Sample 1 s = 1.604 Sample 2 s = 1.852 No, sample 2 has a larger standard deviation. c) The sample range is a relatively crude measure of the sample variability as compared to the sample standard deviation since the standard deviation uses the information from every data point in the sample whereas the range uses the information contained in only two data points - the minimum and maximum. 6-79 a)Stem-and-leaf display for Problem 6-79: unit = 1 1|2 represents 12 1 0T|3 8 0F|4444555 18 0S|6666777777 (7) 0o|8888999 15 1|111 12 1T|22233 7 1F|45 5 1S|77 3 1o|899 b) Sample Average = 9.325 Sample Standard Deviation = 4.4858
c) 20 15 springs 10 5 Index 10 20 30 40 The time series plot indicates there was an increase in the average number of nonconforming springs made during the 40 days. In particular, the increase occurs during the last 10 days.
Chapter 7 SelectedProblem Solutions Section 7-2 7-7. ˆ E ( Θ1 ) = θ No bias ˆ ˆ V (Θ1 ) = 12 = MSE (Θ1 ) ˆ E (Θ ) = θ No bias ˆ ˆ V (Θ ) = 10 = MSE (Θ ) 2 2 2 ˆ E (Θ 3 ) ≠ θ Bias ˆ MSE (Θ 3 ) = 6 [not that this includes (bias2)] To compare the three estimators, calculate the relative efficiencies: ˆ MSE (Θ1 ) 12 = = 1.2 , since rel. eff. > 1 use ˆ Θ2 as the estimator for θ ˆ MSE (Θ 2 ) 10 ˆ MSE (Θ1 ) 12 = = 2, since rel. eff. > 1 use ˆ Θ3 as the estimator for θ ˆ MSE (Θ 3 ) 6 ˆ MSE (Θ 2 ) 10 = = 1.8 , since rel. eff. > 1 use ˆ Θ3 as the estimator for θ ˆ MSE (Θ 3 ) 6 Conclusion: ˆ Θ3 is the most efficient estimator with bias, but it is biased. ˆ Θ2 is the best “unbiased” estimator. 7-11 a.) The average of the 26 observations provided can be used as an estimator of the mean pull force since we know it is unbiased. This value is 75.427 pounds. b.) The median of the sample can be used as an estimate of the point that divides the population into a “weak” and “strong” half. This estimate is 75.1 pounds. c.) Our estimate of the population variance is the sample variance or 2.214 square pounds. Similarly, our estimate of the population standard deviation is the sample standard deviation or 1.488 pounds. d.) The standard error of the mean pull force, estimated from the data provided is 0.292 pounds. This value is the standard deviation, not of the pull force, but of the mean pull force of the population. e.) Only one connector in the sample has a pull force measurement under 73 pounds. Our point estimate for the proportion requested is then 1/26 = 0.0385 7-13 a.) To see if the estimator is unbiased, find: 1 1 E[( X min + X max ) / 2] = [ E ( X min ) + E ( X max )] = ( µ + µ ) = µ 2 2 since the expected value of any observation arising from a normally distributed process is equal to the mean. So this is an unbiased estimator of the mean. b.) The standard error of this estimator is: 1 1 1 V [( X min + X max ) / 2 ] = [V ( X min ) + V ( X max ) + COV ( X min , X max )] = (σ 2 + σ 2 ) = σ 2 2 2 c.) This estimator is not better than the sample mean because it has larger standard error for n > 2. This is due to the fact that this estimator uses only two observations from the available sample. The sample mean uses all the information available to compute the estimate.
7-17 a) E(µ ) = E(αX1 + (1 − α ) X 2 ) = αE( X1) + (1 − α )E( X 2 ) = αµ + (1 − α )µ = µ ˆ b) s.e.( µ ) = V (αX 1 + (1 − α ) X 2 ) = α 2 V ( X 1 ) + (1 − α ) 2 V ( X 2 ) ˆ 2 2 2 2 σ1 σ σ σ = α2 + (1 − α ) 2 2 = α 2 1 + (1 − α ) 2 a 1 n1 n2 n1 n2 α 2 n 2 + (1 − α ) 2 an 1 =σ1 n1 n 2 c) The value of alpha that minimizes the standard error is: an1 α= n2 + an1 d) With a = 4 and n1=2n2, the value of alpha to choose is 8/9. The arbitrary value of α=0.5 is too small and will result in a larger standard error. With α=8/9 the standard error is (8 / 9 ) 2 n 2 + (1 / 9 ) 2 8 n 2 0.667σ 1 s.e.( µ ) = σ 1 ˆ 2 = 2n 2 n2 If α=0.05 the standard error is ( 0 . 5) 2 n 2 + ( 0 . 5) 2 8 n 2 1.0607 σ 1 s.e.( µ ) = σ 1 ˆ 2 = 2n 2 n2 Section 7-5 7-33. P (1 . 009 ≤ X ≤ 1 . 012 ) = P ( 1 . 009 − 1 . 01 0 . 003 / 9 ≤ X −µ σ / n ≤ 1 . 012 − 1 . 01 0 . 003 / 9 ) = P(−1 ≤ Z ≤ 2) = P( Z ≤ 2) − P( Z ≤ −1) = 0.9772 − 0.1587 = 0.8385 σ 3.5 7-35. µ X = 75.5 psi , σ X = = = 1.429 n 6 ( P( X ≥ 75.75) = P σX/− µn ≥ 75.1.429 .5 75 − 75 ) = P( Z ≥ 0.175) = 1 − P( Z ≤ 1.75) = 1 − 0.56945 = 0.43055 7-39 σ 2 = 25
σ σX = n 2 2 5 n= σ σ = = 11.11 X 1.5 n≅12 7-41 n = 36 a + b (3 + 1) µX = = =2 2 2 (b − a + 1) 2 − 1 (3 − 1 + 1) 2 − 1 σX = = = 8 = 2 12 12 12 3 2/3 2/3 µ X = 2, σ X = = 36 6 X −µ z= σ/ n Using the central limit theorem: P(2.1 < X < 2.5) = P 2.1−32 < Z < 2/ 2.5 − 2 2/3 6 6 = P(0.7348 < Z < 3.6742) = P( Z < 3.6742) − P( Z < 0.7348) = 1 − 0.7688 = 0.2312 7-43. n1 = 16 n2 = 9 X 1 − X 2 ~ N ( µ X1 − µ X 2 , σ 2 + σ 2 ) X X 1 2 µ 1 = 75 µ 2 = 70 2 σ1 σ 2 σ1 = 8 σ 2 = 12 ~ N ( µ1 − µ 2 , + )2 n1 n2 82 12 2 ~ N (75 − 70, + ) 16 9 ~ N (5,20) a) P( X 1 − X 2 > 4) P( Z > 4 − 5 ) = P( Z > −0.2236) = 1 − P( Z ≤ −0.2236) 20 = 1 − 0.4115 = 0.5885
b)P(3.5 ≤ X 1 − X 2 ≤ 5.5) P( 3.5205 ≤ Z ≤ 5.5205 ) = P( Z ≤ 0.1118) − P( Z ≤ −0.3354) − − = 0.5445 − 0.3686 = 0.1759 Supplemental Exercises 7-49. 1.52 22 X 1 − X 2 ~ N (100 − 105, + ) ~ N (−5,0.2233) 25 25
Chapter 8 SelectedProblem Solutions Section 8-2 8-1 a.) The confidence level for x − 2.14σ / n ≤ µ ≤ x + 2.14σ / n is determined by the by the value of z0 which is 2.14. From Table II, we find Φ(2.14) = P(Z<2.14) = 0.9793 and the confidence level is 97.93%. b.) The confidence level for x − 2.49σ / n ≤ µ ≤ x + 2.49σ / n is determined by the by the value of z0 which is 2.14. From Table II, we find Φ(2.49) = P(Z<2.49) = 0.9936 and the confidence level is 99.36%. c.) The confidence level for x − 1.85σ / n ≤ µ ≤ x + 1.85σ / n is determined by the by the value of z0 which is 2.14. From Table II, we find Φ(1.85) = P(Z<1.85) = 0.9678 and the confidence level is 96.78%. 8-7 a.) The 99% CI on the mean calcium concentration would be longer. b). No, that is not the correct interpretation of a confidence interval. The probability that µ is between 0.49 and 0.82 is either 0 or 1. c). Yes, this is the correct interpretation of a confidence interval. The upper and lower limits of the confidence limits are random variables. 8-13 a) 95% two sided CI on the mean compressive strength zα/2 = z0.025 = 1.96, and x = 3250, σ2 = 1000, n=12 σ σ x − z0.025 ≤ µ ≤ x + z0.025 n n 31.62 31.62 3250 − 1.96 ≤ µ ≤ 3250 + 1.96 12 12 3232.11 ≤ µ ≤ 3267.89 b.) 99% Two-sided CI on the true mean compressive strength zα/2 = z0.005 = 2.58 σ σ x − z0.005 ≤ µ ≤ x + z0.005 n n 3162 . 3162 . 3250 − 2.58 ≤ µ ≤ 3250 + 2.58 12 12 3226.5 ≤ µ ≤ 3273.5 8-15 Set the width to 6 hours with σ = 25, z0.025 = 1.96 solve for n. 1/2 width = (1.96)(25) / n = 3 49 = 3 n 2 49 n = = 266.78 3 Therefore, n=267.
Section 8-3 8-25 a.) The data appear to be normally distributed based on examination of the normal probability plot below. Therefore, there is evidence to support that the level of polyunsaturated fatty acid is normally distributed. N o rm a l P ro b a b ility P lo t fo r 8 -2 5 M L E stim a te s - 9 5 % C I 99 95 90 80 70 Percent 60 50 40 30 20 10 5 1 16 17 18 D a ta b.) 99% CI on the mean level of polyunsaturated fatty acid. For α = 0.01, tα/2,n-1 = t0.005,5 = 4.032 s s x − t 0.005,5 ≤ µ ≤ x + t 0.005,5 n n 0.319 0.319 16.98 − 4.032 ≤ µ ≤ 16.98 + 4.032 6 6 16.455 ≤ µ ≤ 17.505 8-29 95% lower bound confidence for the mean wall thickness given x = 4.05 s = 0.08 n = 25 tα,n-1 = t0.05,24 = 1.711 s x − t 0.05, 24 ≤µ n 0.08 4.05 − 1.711 ≤µ 25 4.023 ≤ µ It may be assumed that the mean wall thickness will most likely be greater than 4.023 mm. 8-31 x = 1.10 s = 0.015 n = 25
95% CI onthe mean volume of syrup dispensed For α = 0.05 and n = 25, tα/2,n-1 = t0.025,24 = 2.064 s s x − t 0.025, 24 ≤ µ ≤ x + t 0.025, 24 n n 0.015 0.015 1.10 − 2.064 ≤ µ ≤ 1.10 + 2.064 25 25 1.093 ≤ µ ≤ 1.106 Section 8-4 8-35 99% lower confidence bound for σ2 2 2 For α = 0.01 and n = 15, χ α ,n −1 = χ 0.01,14 = 29.14 14(0.008) 2 <σ2 29.14 0.00003075 < σ2 8-37 95% lower confidence bound for σ2 given n = 16, s2 = (3645.94)2 For α = 0.05 and n = 16, χα,n−1 = χ2.05,15 = 25 2 0 15(3645.94) 2 <σ2 25 7,975,727.09 < σ2 8-39 95% confidence interval for σ: given n = 51, s = 0.37 First find the confidence interval for σ2 : For α = 0.05 and n = 51, χ2 2 , n−1 = χ2.025,50 = 71.42 and χ1− α / 2 ,n −1 = χ2.975,50 = 32.36 α/ 0 2 0 50(0.37) 2 2 50(0.37) 2 ≤σ ≤ (71.42) 2 (32.36) 2 0.096 ≤ σ2 ≤ 0.2115 Taking the square root of the endpoints of this interval we obtain, 0.31 < σ < 0.46 8-41 90% lower confidence bound on σ (the standard deviation of the sugar content) given n = 10, s2 = 23.04 2 2 For α = 0.1 and n = 10, χ α ,n −1 = χ 0.1,9 = 19.02 9(23.04) ≤σ2 14.68 14.13 ≤ σ2 Take the square root of the endpoints of this interval to find the confidence interval for σ: 3.8 ≤ σ
Section 8-7 8-63 99% tolerance interval on the polyunsaturated fatty acid in this type of margarine that has a confidence level of 95% x = 16.98 s = 0.319 n=6 and k = 5.775 x − ks, x + ks 16.98 − 5.775(0.319 ), 16.98 + 5.775(0.319 ) (15.14, 18.82) The 99% tolerance interval is much wider than the 99% confidence interval on the population mean (16.46 ≤ µ ≤ 17.51). 8-67 90% lower tolerance bound on bottle wall thickness that has confidence level 90%. given x = 4.05 s = 0.08 n = 25 and k = 1.702 x − ks 4.05 − 1.702(0.08) 3.91 The 90% tolarance bound is (3.91, ∞) The lower tolerance bound is of interest if we want to make sure the wall thickness is at least a certain value so that the bottle will not break. 8-69 95% tolerance interval on the syrup volume that has 90% confidence level x = 1.10 s = 0.015 n = 25 and k=2.474 x − ks, x + ks 1.10 − 2.474(0.015), 1.10 + 2.474(0.015) (1.06, 1.14) Supplemental Exercises 8-75 With σ = 8, the 95% confidence interval on the mean has length of at most 5; the error is then E = 2.5. 2 2 z0.025 2 1.96 a) n = 8 = 64 = 39.34 = 40 2.5 2.5 2 2 z0.025 2 1.96 b) n = 6 = 36 = 22.13 = 23 2.5 2.5 As the standard deviation decreases, with all other values held constant, the sample size necessary to maintain the acceptable level of confidence and the length of the interval, decreases.
8-79Normal probability plot for the coefficient of restitution Normal Probability Plot for 8-79 ML Estimates - 95% CI 99 95 90 80 70 Percent 60 50 40 30 20 10 5 1 0.59 0.60 0.61 0.62 0.63 0.64 0.65 0.66 Data b.) 99% CI on the true mean coefficient of restitution x = 0.624, s = 0.013, n = 40 ta/2, n-1 = t0.005, 39 = 2.7079 s s x − t 0.005,39 ≤ µ ≤ x + t 0.005,39 n n 0.013 0.013 0.624 − 2.7079 ≤ µ ≤ 0.624 + 2.7079 40 40 0.618 ≤ µ ≤ 0.630 b.) 99% prediction interval on the coefficient of restitution for the next baseball that will be tested. 1 1 x − t 0.005,39 s 1 + ≤ x n +1 ≤ x + t 0.005,39 s 1 + n n 1 1 0.624 − 2.7079(0.013) 1 + ≤ x n +1 ≤ 0.624 + 2.7079(0.013) 1 + 40 40 0.588 ≤ x n +1 ≤ 0.660 c.) 99% tolerance interval on the coefficient of restitution with a 95% level of confidence ( x − ks, x + ks) (0.624 − 3.213(0.013), 0.624 + 3.213(0.013)) (0.583, 0.665) e.)The confidence interval in part (b) describes the confidence interval on the population mean and we may interpret this to mean that 99% of such intervals will cover the population mean. The prediction interval tells us that within that within a 99% probability that the next baseball will have a coefficient of restitution between 0.588 and 0.660. The tolerance interval captures 99% of the values of the normal distribution with a 95% level of confidence.
8-83a.) 95% Confidence Interval on the population proportion n=1200 x=8 ˆ p = 0.0067 zα/2=z0.025=1.96 ˆ ˆ p (1 − p ) ˆ ˆ p (1 − p ) ˆ p − za / 2 ˆ ≤ p ≤ p + za / 2 n n 0.0067(1 − 0.0067) 0.0067(1 − 0.0067) 0.0067 − 1.96 ≤ p ≤ 0.0067 + 1.96 1200 1200 0.0021 ≤ p ≤ 0.0088 b.) Yes, there is evidence to support the claim that the fraction of defective units produced is one percent or less. This is true because the confidence interval does not include 0.01 and the upper limit of the control interval is lower than 0.01.
Chapter 9 SelectedProblems Solutions Section 9-1 9-1 a) H 0 : µ = 25, H1 : µ ≠ 25 Yes, because the hypothesis is stated in terms of the parameter of interest, inequality is in the alternative hypothesis, and the value in the null and alternative hypotheses matches. b) H 0 : σ > 10, H1 : σ = 10 No, because the inequality is in the null hypothesis. c) H 0 : x = 50, H1 : x ≠ 50 No, because the hypothesis is stated in terms of the statistic rather than the parameter. d) H 0 : p = 0.1, H1 : p = 0.3 No, the values in the hull and alternative hypotheses do not match and both of the hypotheses are equality statements. e) H 0 : s = 30, H1 : s > 30 No, because the hypothesis is stated in terms of the statistic rather than the parameter. X−µ 115 − 12 . 9-3 a) α = P( X ≤ 11.5 | µ = 12) = P ≤ = P(Z ≤ −4) = 1 − P(Z ≤ 4) σ / n 0.5 / 16 = 1 − 1 = 0. The probability of rejecting the null, when the null is true, is approximately 0 with a sample size of 16. X − µ 115 − 1125 . . b) β = P( X > 11.5 | µ =11.25) = P > = P(Z > 2) = 1 − P(Z ≤ 2) σ/ n 0.5 / 16 = 1− 0.97725 = 0.02275. The probability of accepting the null hypothesis when it is false is 0.02275. 190 − 175 9-9 a) z= = 2.37 , Note that z is large, therefore reject the null hypothesis and conclude that the 20 / 10 mean foam height is greater than 175 mm. b) P( X > 190 when µ = 175) X − 175 190 − 175 = P > 20 / 10 20 / 10 = P(Z > 2.37) = 1 − P(Z ≤ 2.37) = 1 − 0.99111 = 0.00889. The probability that a value of at least 190 mm would be observed (if the true mean height is 175 mm) is only 0.00889. Thus, the sample value of x = 190 mm would be an unusual result. 9-17. The problem statement implies H0: p = 0.6, H1: p > 0.6 and defines an acceptance region as 315 p≤ ˆ = 0.63 and rejection region as p > 0.63 ˆ 500 ˆ ( ) a) α = P P ≥ 0 . 63 | p = 0 . 6 = P Z ≥ 0 . 63 − 0 . 6 0 .6 ( 0 .4 ) . 500 = P (Z ≥ 1 . 37 ) = 1 − P ( Z < 1 . 37 ) = 0 . 08535 b) β = P( P ≤ 0.63 when p = 0.75) = P(Z ≤ −6.196) ≅ 0.
Section 9-2 9-21. a) 1) The parameter of interest is the true mean yield, µ. 2) H0 : µ = 90 3) H1 : µ ≠ 90 4) α = 0.05 x−µ 5) z0 = σ/ n 6) Reject H0 if z0 < −z α/2 where −z0.025 = −1.96 or z0 > zα/2 where z0.025 = 1.96 7) x = 90.48 , σ = 3 90.48 − 90 z0 = = 0.36 3/ 5 8) Since −1.96 < 0.36 < 1.96 do not reject H0 and conclude the yield is not significantly different from 90% at α = 0.05. b) P-value = 2[1 − Φ(0.36)] = 2[1 − 0.64058] = 0.71884 ( c) n = z α / 2 + z β )σ 2 2 = (z 0 .025 + z 0 .05 )2 3 2 = (1 . 96 + 1 . 65 )2 9 = 4 . 67 δ 2 (85 − 90 )2 (− 5 )2 n ≅ 5. 90 − 92 90 − 92 d) β = Φ z0.025 + − Φ − z0.025 + 3/ 5 3/ 5 = Φ(1.96 + −1.491) − Φ(−1.96 + −1.491) = Φ(0.47) − Φ(−3.45) = Φ(0.47) − (1 − Φ(3.45)) = 0.68082 − ( 1 − 0.99972) = 0.68054. e) For α = 0.05, zα/2 = z0.025 = 1.96 σ σ x − z0.025 ≤ µ ≤ x + z0.025 n n 3 3 90.48 − 1.96 ≤ µ ≤ 90.48 + 196 . 5 5 87.85 ≤ µ ≤ 93.11 With 95% confidence, we believe the true mean yield of the chemical process is between 87.85% and 93.11%. 9-25. a) 1) The parameter of interest is the true mean tensile strength, µ. 2) H0 : µ = 3500 3) H1 : µ ≠ 3500 4) α = 0.01 x−µ 5) z0 = σ/ n 6) Reject H0 if z0 < −zα/2 where −z0.005 = −2.58 or z0 > zα/2 where z0.005 = 2.58 7) x = 3250 , σ = 60 3250 − 3500 z0 = = −14.43 60 / 12 8) Since −14.43 < −2.58, reject the null hypothesis and conclude the true mean compressive strength is significantly different from 3500 at α = 0.01. b) Smallest level of significance = P-value = 2[1 − Φ (14.43) ]= 2[1 − 1] = 0
The smallest levelof significance at which we are willing to reject the null hypothesis is 0. c) zα/2 = z0.025 = 1.96 σ σ x − z0.025 ≤ µ ≤ x + z0.025 n n 3162 . 3162 . 3250 − 1.96 ≤ µ ≤ 3250 + 196 . 12 12 3232.11 ≤ µ ≤ 3267.89 With 95% confidence, we believe the true mean tensile strength is between 3232.11 psi and 3267.89 psi. We can test the hypotheses that the true mean strength is not equal to 3500 by noting that the value is not within the confidence interval. 9-27 a) 1) The parameter of interest is the true mean speed, µ. 2) H0 : µ = 100 3) H1 : µ < 100 4) α = 0.05 x−µ 5) z0 = σ/ n 6) Reject H0 if z0 < −zα where −z0.05 = −1.65 7) x = 102.2 , σ = 4 102.2 − 100 z0 = = 1.55 4/ 8 8) Since 1.55> −1.65, do not reject the null hypothesis and conclude the there is insufficient evidence to conclude that the true speed strength is less than 100 at α = 0.05. (95 − 100) 8 b) β = Φ − z0.05 − = Φ(-1.65 - −3.54) = Φ(1.89) = 1 4 Power = 1-β = 1-0.97062 = 0.02938 (z α + zβ ) σ 2 2 (z 0.05 + z 0.15 )2 σ 2 (1.65 + 1.03) 2 (4) 2 c) n = = = = 0.927, δ2 (95 − 100) 2 (5) 2 n≅1 σ d) x − z0.05 ≤µ n 4 102.2 − 1.65 ≤µ 8 99.866 ≤ µ Since the lower limit of the CI is just slightly below 100, we are confident that the mean speed is not less than 100 m/s. 9-29 a) 1) The parameter of interest is the true average battery life, µ. 2) H0 : µ = 4 3) H1 : µ > 4 4) α = 0.05 x−µ 5) z0 = σ/ n 6) Reject H0 if z0 > zα where z0.05 = 1.65 7) x = 4.05 , σ = 0.2
4.05 − 4 z0 = = 1.77 0.2 / 50 8) Since 1.77>1.65, reject the null hypothesis and conclude that the there is sufficient evidence to conclude that the true average battery life exceeds 4 hours at α = 0.05. (4.5 − 4) 50 b) β = Φ z0.05 − = Φ(1.65 – 17.68) = Φ(-16.03) = 0 0.2 Power = 1-β = 1-0 = 1 c) n = (z α + z β ) σ 2 (z0.05 + z0.1 )2 σ 2 (1.65 + 1.29) 2 (0.2) 2 2 = = = 34.7, δ2 (4.5 − 4) 2 (0.5) 2 n ≅ 35 σ d) x − z0.05 ≤µ n 0.2 4.05 − 1.65 ≤µ 50 4.003 ≤ µ Since the lower limit of the CI is just slightly above 4, we conclude that average life is greater than 4 hours at α=0.05. Section 9-3 9-31 a. 1) The parameter of interest is the true mean female body temperature, µ. 2) H0 : µ = 98.6 3) H1 : µ ≠ 98.6 4) α = 0.05 x−µ 5) t0 = s/ n 6) Reject H0 if |t0| > tα/2,n-1 where tα/2,n-1 = 2.064 7) x = 98.264 , s = 0.4821 n=25 98 . 264 − 98 . 6 t0 = = − 3 . 48 0 . 4821 / 25 8) Since 3.48 > 2.064, reject the null hypothesis and conclude that the there is sufficient evidence to conclude that the true mean female body temperature is not equal to 98.6 °F at α = 0.05. P-value = 2 0.001 = 0.002 δ | µ − µ 0 | | 98 − 98.6 | b) d = = = = 1.24 σ σ 0.4821 Using the OC curve, Chart VI e) for α = 0.05, d = 1.24, and n = 25, we get β ≅ 0 and power of 1−0 ≅ 1. δ | µ − µ0 | | 98.2 − 98.6 | c) d = = = = 0.83 σ σ 0.4821 Using the OC curve, Chart VI g) for α = 0.05, d = 0.83, and β ≅ 0.1 (Power=0.9), n + 1 20 + 1 n = 20 . Therefore, n= = = 10.5 and n=11. 2 2 d) 95% two sided confidence interval
s s x − t0.025, 24 ≤ µ ≤ x + t0.025, 24 n n 0 . 4821 0 . 4821 98 . 264 − 2 .064 ≤ µ ≤ 98 .264 + 2 . 064 25 25 98 . 065 ≤ µ ≤ 98 .463 We can conclude that the mean female body temperature is not equal to 98.6 since the value is not included inside the confidence interval. e) Normal Probability Plot for 9-31 ML Estimates - 95% CI 99 95 90 80 70 Percent 60 50 40 30 20 10 5 1 97 98 99 Data Data appear to be normally distributed. 9-37. a.) In order to use t statistics in hypothesis testing, we need to assume that the underlying distribution is normal. 1) The parameter of interest is the true mean coefficient of restitution, µ. 2) H0 : µ = 0.635 3) H1 : µ > 0.635 4) α = 0.05 x−µ 5) t0 = s/ n 6) Reject H0 if t0 > tα,n-1 where t0.05,39 = 1.685 7) x = 0.624 s = 0.013 n = 40 0.624 − 0.635 t0 = = −5.35 0.013 / 40 8) Since –5.25 < 1.685, do not reject the null hypothesis and conclude that there is not sufficient evidence to indicate that the true mean coefficient of restitution is greater than 0.635 at α = 0.05. b.)The P-value > 0.4, based on Table IV. Minitab gives P-value = 1. δ | µ − µ 0 | | 0.64 − 0.635 | c) d = = = = 0.38 σ σ 0.013 Using the OC curve, Chart VI g) for α = 0.05, d = 0.38, and n = 40, we get β ≅ 0.25 and power of 1−0.25 = 0.75. δ | µ − µ 0 | | 0.638 − 0.635 | d) d = = = = 0.23 σ σ 0.013 Using the OC curve, Chart VI g) for α = 0.05, d = 0.23, and β ≅ 0.25 (Power=0.75),
n +1 75 + 1 n = 75 . Therefore, n= = = 38 and n=38. 2 2 9-41 a) In order to use t statistics in hypothesis testing, we need to assume that the underlying distribution is normal. 1) The parameter of interest is the true mean concentration of suspended solids, µ. 2) H0 : µ = 55 3) H1 : µ ≠ 55 4) α = 0.05 x−µ 5) t0 = s/ n 6) Reject H0 if |t0 | > tα/2,n-1 where t0.025,59 =2.000 7) x = 59.87 s = 12.50 n = 60 59.87 − 55 t0 = = 3.018 12.50 / 60 8) Since 3.018 > 2.000, reject the null hypothesis and conclude that there is sufficient evidence to indicate that the true mean concentration of suspended solids is not equal to 55 at α = 0.05. b) From table IV the t0 value is found between the values of 0.001 and 0.0025 with 59 degrees of freedom, so 20.001<P-value = 2 0.0025 Therefore, 0.002< P-value<0.005. Minitab gives a p-value of 0.0038 50 − 55 c) d= = 0.4 , n=60 so, from the OC Chart VI e) for α = 0.05, d= 0.4 and n=60 we find that 12.50 β≅0.2. Therefore, the power = 1-0.2 = 0.8. d) From the same OC chart, and for the specified power, we would need approximately 38 observations. 50 − 55 d= = 0.4 Using the OC Chart VI e) for α = 0.05, d = 0.4, and β ≅ 0.10 (Power=0.90), 12.50 n + 1 75 + 1 n = 75 . Therefore, n= = = 38 and n=38. 2 2 Section 9-4 9-43 a) In order to use the χ2 statistic in hypothesis testing and confidence interval construction, we need to assume that the underlying distribution is normal. 1) The parameter of interest is the true standard deviation of the diameter, σ. However, the answer can be found by performing a hypothesis test on σ2. 2) H0 : σ2 = 0.0001 3) H1 : σ2 > 0.0001 4) α = 0.01 ( n − 1)s2 5) χ2 = 0 σ2 6) Reject H0 if χ2 > χα ,n −1 where χ2.01,14 = 29.14 0 2 0 7) n = 15, s2 = 0.008 ( n − 1)s2 14(0.008)2 χ2 = 0 2 = = 8.96 σ 0.0001 8) Since 8.96 < 29.14 do not reject H0 and conclude there is insufficient evidence to indicate the true standard deviation of the diameter exceeds 0.01 at α = 0.01. b) P-value = P(χ2 > 8.96) for 14 degrees of freedom: 0.5 < P-value < 0.9
σ 0.0125 c) λ= = = 1.25 power = 0.8, β=0.2 σ0 0.01 using chart VIk, the required sample size is 50 9-47. a) In order to use χ2 statistic in hypothesis testing and confidence interval construction, we need to assume that the underlying distribution is normal. 1) The parameter of interest is the true standard deviation of titanium percentage, σ. However, the answer can be found by performing a hypothesis test on σ2. 2) H0 : σ2 = (0.25)2 3) H1 : σ2 ≠ (0.25)2 4) α = 0.01 ( n − 1)s2 5) χ2 = 0 σ2 6) Reject H0 if χ2 < χ1− α / 2 ,n −1 where χ2.995,50 = 27.99 or χ2 > χα ,2,n −1 where χ2.005,50 = 79.49 0 2 0 0 2 0 7) n = 51, s = 0.37 ( n − 1)s2 50(0.37) 2 χ2 = 0 2 = = 109.52 σ (0.25) 2 8) Since 109.52 > 79.49 we would reject H0 and conclude there is sufficient evidence to indicate the true standard deviation of titanium percentage is significantly different from 0.25 at α = 0.01. b) 95% confidence interval for σ: First find the confidence interval for σ2 : For α = 0.05 and n = 51, χ2 2 , n−1 = χ2.025,50 = 71.42 and χ1− α / 2 ,n −1 = χ2.975,50 = 32.36 α/ 0 2 0 50(0.37) 2 50(0.37) 2 ≤σ2 ≤ (71.42) 2 (32.36) 2 0.096 ≤ σ2 ≤ 0.2115 Taking the square root of the endpoints of this interval we obtain, 0.31 < σ < 0.46 Since 0.25 falls below the lower confidence bound we would conclude that the population standard deviation is not equal to 0.25. 40 9-49 Using the chart in the Appendix, with λ= = 1.49 and β = 0.10, we find 18 n = 30. Section 9-5 9-51 p= 0.15, p0=0.10, n=85, and zα/2=1.96 p0 − p + zα / 2 p0 (1− p0 ) / n p0 − p − zα / 2 p0 (1− p0 ) / n β = Φ − Φ p(1− p) / n p(1− p) / n 0.10− 0.15+1.96 0.10(1− 0.10) / 85 0.10− 0.15−1.96 0.10(1− 0.10) / 85 = Φ − Φ 0.15(1− 0.15) / 85 0.15(1− 0.15) / 85 = Φ(0.36) − Φ(−2.94) = 0.6406− 0.0016= 0.639
2 zα / 2 p0 (1− p0 ) − z β p(1− p) n = p − p0 2 1.96 0.10(1− 0.10) −1.28 0.15(1− 0.15) = 0.15− 0.10 2 = (10.85) = 11763≅ 118 . 9-53. a) Using the information from Exercise 8-51, test 2) H0 : p = 0.05 3) H1 : p < 0.05 4) α = 0.05 x − np0 p − p0 ˆ 5) z0 = or z0 = ; Either approach will yield the same conclusion np0 (1 − p0 ) p0 (1 − p0 ) n 6) Reject H0 if z0 < − zα where −zα = −z0.05 = −1.65 13 7) x = 13 n = 300 p =∃ = 0.043 300 x − np0 13 − 300(0.05) z0 = = = −0.53 np0 (1 − p0 ) 300(0.05)(0.95) 8) Since −0.53 > −1.65, do not null hypothesis and conclude the true fraction of defective integrated circuits is not significantly less than 0.05, at α = 0.05. b) P-value = 1 − Φ(0.53) = 0.29806 9-57. The problem statement implies that H0: p = 0.6, H1: p > 0.6 and defines an acceptance region as 315 ∃ p≤ ∃ = 0.63 and rejection region as p > 0.63 500 a) The probability of a type 1 error is α = P( p ≥ 0.63 | p = 0.6 ) = P ˆ Z ≥ 0.63 − 0.6 = P(Z ≥ 1.37 ) = 1 − P( Z < 1.37) = 0.08535 . 0.6(0.4) 500 ∃ b) β = P( P ≤ 0.63 | p = 0.75) = P(Z ≤ −6.196) = 0. Section 9-7 9-59. Value 0 1 2 3 4 Observed Frequency 24 30 31 11 4 Expected Frequency 30.12 36.14 21.69 8.67 2.60 Since value 4 has an expected frequency less than 3, combine this category with the previous category: Value 0 1 2 3-4 Observed Frequency 24 30 31 15 Expected Frequency 30.12 36.14 21.69 11.67 The degrees of freedom are k − p − 1 = 4 − 0 − 1 = 3
a) 1) Thevariable of interest is the form of the distribution for X. 2) H0: The form of the distribution is Poisson 3) H1: The form of the distribution is not Poisson 4) α = 0.05 5) The test statistic is χ =∑ 2 k (Oi − Ei )2 0 i =1 Ei 6) Reject H0 if χ2 > χ 2.05,3 = 7.81 o 0 7) χ 2 = (24− 30.12)2 + (30− 36.14)2 + (31− 21.69)2 + (15−11.67)2 = 7.23 0 30.12 36.14 21.69 11.67 8) Since 7.23 < 7.81 do not reject H0. We are unable to reject the null hypothesis that the distribution of X is Poisson. b) The P-value is between 0.05 and 0.1 using Table III. P-value = 0.0649 (found using Minitab) 9-63 ∃ The value of p must be estimated. Let the estimate be denoted by psample 0(39 ) + 1(23) + 2(12) + 3(1) sample mean = = 0.6667 75 sample mean 0.6667 p sample = ˆ = = 0.02778 n 24 Value 0 1 2 3 Observed 39 23 12 1 Expected 38.1426 26.1571 8.5952 1.8010 Since value 3 has an expected frequency less than 3, combine this category with that of value 2: Value 0 1 2-3 Observed 39 23 13 Expected 38.1426 26.1571 10.3962 The degrees of freedom are k − p − 1 = 3 − 1 − 1 = 1 a) 1) The variable of interest is the form of the distribution for the number of under-filled cartons, X. 2) H0: The form of the distribution is binomial 3) H1: The form of the distribution is not binomial 4) α = 0.05 5) The test statistic is χ2 = k (Oi − Ei )2 0 ∑ Ei i =1 6) Reject H0 if χ2 > χ 2.05,1 = 384 o 0 . 7) χ2 = (39 − 38.1426)2 + (23 − 26.1571)2 + (13 − 10.3962)2 = 1.053 0 381426 . 26.1571 10.39 8) Since 1.053 < 3.84 do not reject H0. We are unable to reject the null hypothesis that the distribution of the number of under-filled cartons is binomial at α = 0.05. b) The P-value is between 0.5 and 0.1 using Table III P-value = 0.3048 (found using Minitab) Section 9-8 9-65. 1. The variable of interest is breakdowns among shift. 2. H0: Breakdowns are independent of shift.
3. H1: Breakdownsare not independent of shift. 4. α = 0.05 5. The test statistic is: r c (O − Eij ) 2 χ = ∑∑ 2 ij 0 i =1 j =1 Eij 6. The critical value is χ .05 , 6 = 12.592 2 The calculated test statistic is χ 0 = 11.65 2 7. 8. χ 2 > χ 2.05,6 , do not reject H0 and conclude that the data provide insufficient evidence to claim that 0 / 0 machine breakdown and shift are dependent at α = 0.05. P-value = 0.070 (using Minitab) 9-69. 1. The variable of interest is failures of an electronic component. 2. H0: Type of failure is independent of mounting position. 3. H1: Type of failure is not independent of mounting position. 4. α = 0.01 5. The test statistic is: r c (O − Eij ) 2 χ = ∑∑ 2 ij 0 i =1 j =1 Eij 6. The critical value is χ .01, 3 = 11.344 2 7. The calculated test statistic is χ 0 = 10.71 2 8. χ 0 > χ 0.01,3 2 / 2 , do not reject H0 and conclude that the evidence is not sufficient to claim that the type of failure is not independent of the mounting position at α = 0.01. P-value = 0.013 Supplemental α 9-75. σ = 8, δ = 204 − 200 = −4, = 0.025, z0.025 = 1.96. 2 4 20 a) n = 20: β = Φ1.96 − = Φ( −0.28) = 1 − Φ(0.28) = 1 − 0.61026 = 0.38974 8 Therefore, power = 1 − β = 0.61026 4 50 b) n = 50: β = Φ1.96 − = Φ ( −2.58) = 1 − Φ(2.58) = 1 − 0.99506 = 0.00494 8 Therefore, power = 1 − β = 0.995 4 100 c) n = 100: β = Φ1.96 − = Φ( −3.04) = 1 − Φ(3.04) = 1 − 0.99882 = 0.00118 8 Therefore, power = 1 − β = 0.9988 d) As sample size increases, and all other values are held constant, the power increases because the variance of the sample mean decreases. Consequently, the probability of a Type II error decreases, which implies the power increases. 9-77. a) Rejecting a null hypothesis provides a stronger conclusion than failing to reject a null hypothesis. Therefore, place what we are trying to demonstrate in the alternative hypothesis. Assume that the data follow a normal distribution.
b) 1) theparameter of interest is the mean weld strength, µ. 2) H0 : µ = 150 3) H1 : µ > 150 4) Not given 5) The test statistic is: x − µ0 t0 = s/ n 6) Since no critical value is given, we will calculate the P-value 7) x = 153.7 , s= 11.3, n=20 153.7 − 150 t0 = = 1.46 11.3 20 P-value = P( t ≥ 1.46) = 0.05 < p − value < 010 . 8) There is some modest evidence to support the claim that the weld strength exceeds 150 psi. If we used α = 0.01 or 0.05, we would not reject the null hypothesis, thus the claim would not be supported. If we used α = 0.10, we would reject the null in favor of the alternative and conclude the weld strength exceeds 150 psi. 9-79 a) 1) the parameter of interest is the standard deviation, σ 2) H0 : σ2 = 400 3) H1 : σ2 < 400 4) Not given ( n − 1) s2 5) The test statistic is: χ2 = 0 σ2 6) Since no critical value is given, we will calculate the p-value 7) n = 10, s = 15.7 9(15.7) 2 χ2 = 0 = 5546 . 400 ( P-value = P χ 2 < 5546 ; . ) 01 < P − value < 0.5 . 8) The P-value is greater than any acceptable significance level, α, therefore we do not reject the null hypothesis. There is insufficient evidence to support the claim that the standard deviation is less than 20 microamps. b) 7) n = 51, s = 20 50(15.7)2 χ2 = 0 = 30.81 400 ( P-value = P χ 2 < 30.81 ; ) 0.01 < P − value < 0.025 8) The P-value is less than 0.05, therefore we reject the null hypothesis and conclude that the standard deviation is significantly less than 20 microamps. c) Increasing the sample size increases the test statistic χ2 and therefore decreases the P-value, providing 0 more evidence against the null hypothesis. 9-85 We can divide the real line under a standard normal distribution into eight intervals with equal probability. These intervals are [0,.32), [0.32, 0.675), [0.675, 1.15), [1.15, ∞) and their negative counterparts. The probability for each interval is p = 1/8 = .125 so the expected cell frequencies are E = np = (100) (0.125) = 12.5. The table of ranges and their corresponding frequencies is completed as follows.
Interval Obs. Frequency. Exp. Frequency. x ≤ 5332.5 1 12.5 5332.5< x ≤ 5357.5 4 12.5 5357.5< x ≤ 5382.5 7 12.5 5382.5< x ≤ 5407.5 24 12.5 5407.5< x ≤ 5432.5 30 12.5 5432.5< x ≤ 5457.5 20 12.5 5457.5< x ≤ 5482.5 15 12.5 x ≥ 5482.5 5 12.5 The test statistic is: 2 (1 - 12.5)2 (4 − 12.5) 2 (15 - 12.5) 2 (5 − 12.5) 2 χ0 = + +Λ + + = 63.36 12.5 12.5 12.5 12.5 and we would reject if this value exceeds χ 20.05,5 = 11.07 . Since χ o > χ 0.05,5 , reject the 2 2 hypothesis that the data are normally distributed 9-87 a) In order to use t statistics in hypothesis testing, we need to assume that the underlying distribution is normal. 1) The parameter of interest is the true mean overall distance for this brand of golf ball, µ. 2) H0 : µ = 270 3) H1 : µ < 270 4) α = 0.05 5) Since n>>30 we can use the normal distribution x−µ z0 = s/ n 6) Reject H0 if z0 <- zα where z0.05 =1.65 7) x = 1.25 s = 0.25 n = 20 260.30 − 270.0 z0 = = −7.23 13.41 / 100 8) Since –7.23<-1.65, reject the null hypothesis and conclude there is sufficient evidence to indicate that the true mean distance is less than 270 yds at α = 0.05. b) The P-value ≅ 0. c) We can divide the real line under a standard normal distribution into eight intervals with equal probability. These intervals are [0,.32), [0.32, 0.675), [0.675, 1.15), [1.15, ∞) and their negative counterparts. The probability for each interval is p = 1/8 = .125 so the expected cell frequencies are E = np = (100) (0.125) = 12.5. The table of ranges and their corresponding frequencies is completed as follows. Interval Obs. Frequency. Exp. Frequency. x ≤ 244.88 16 12.5 244.88< x ≤ 251.25 6 12.5 251.25< x ≤ 256.01 17 12.5 256.01< x ≤ 260.30 9 12.5 260.30< x ≤ 264.59 13 12.5 264.59< x ≤ 269.35 8 12.5 269.35< x ≤ 275.72 19 12.5 x ≥ 275.72 12 12.5
The test statisticis: (16 − 12.5) 2 (6 − 12.5) 2 (19 − 12.5) 2 (12 − 12.5) 2 χ 2o = + +Λ + + = 12 12.5 12.5 12.5 12.5 and we would reject if this value exceeds χ 20.05,5 = 11.07 . Since it does, we can reject the hypothesis that the data are normally distributed.
Chapter 10 SelectedProblem Solutions Section 10-2 10-1. a) 1) The parameter of interest is the difference in fill volume, µ1 − µ 2 ( note that ∆0=0) 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 z0 = σ1 σ 2 2 + 2 n1 n2 6) Reject H0 if z0 < −zα/2 = −1.96 or z0 > zα/2 = 1.96 7) x1 = 16.015 x2 = 16.005 σ1 = 0.02 σ 2 = 0.025 n1 = 10 n2 = 10 (16.015 − 16.005) z0 = = 0.99 (0.02) 2 (0.025) 2 + 10 10 8) since -1.96 < 0.99 < 1.96, do not reject the null hypothesis and conclude there is no evidence that the two machine fill volumes differ at α = 0.05. b) P-value = 2(1 − Φ(0.99)) = 2(1 − 0.8389) = 0.3222 c) Power = 1 − β , where ∆ − ∆0 ∆ − ∆0 β = Φ zα / 2 − − Φ − zα / 2 − 2 σ1 σ 22 σ1 σ 2 2 2 + + n1 n 2 n1 n2 0.04 0.04 = Φ1.96 − − Φ − 1.96 − (0.02) 2 (0.025) 2 (0.02) 2 (0.025) 2 + + 10 10 10 10 = Φ ( .96 − 3.95) − Φ (− 1.96 − 3.95) = Φ (− 1.99 ) − Φ (− 5.91) 1 = 0.0233 − 0 = 0.0233 Power = 1 −0.0233 = 0.9967 σ1 σ 2 2 σ2 σ 2 d) (x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2 n1 n 2 n1 n 2 (0.02) 2 (0.025) 2 (0.02) 2 (0.025) 2 (16.015 − 16.005) − 1.96 + ≤ µ1 − µ 2 ≤ (16.015 − 16.005) + 196 . + 10 10 10 10 −0.0098 ≤ µ1 − µ 2 ≤ 0.0298 With 95% confidence, we believe the true difference in the mean fill volumes is between −0.0098 and 0.0298. Since 0 is contained in this interval, we can conclude there is no significant difference between the means. e) Assume the sample sizes are to be equal, use α = 0.05, β = 0.05, and ∆ = 0.04
(z + z β ) (σ 12 + σ 2 ) (1.96 + 1.645)2 ((0.02) 2 + (0.025) 2 ) = 8.33, 2 2 α /2 n≅ = n = 9, δ2 (0.04) 2 use n1 = n2 = 9 10-5. x1 = 30.87 x2 = 30.68 σ1 = 0.10 σ 2 = 0.15 n1 = 12 n2 = 10 a) 90% two-sided confidence interval: σ1 σ 2 2 σ2 σ 2 (x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2 n1 n 2 n1 n 2 ( 010) 2 ( 015) 2 . . (010)2 (015) 2 . . (30.87 − 30.68) − 1.645 + ≤ µ1 − µ 2 ≤ ( 30.87 − 30.68) + 1645 . + 12 10 12 10 0.0987 ≤ µ1 − µ 2 ≤ 0.2813 We are 90% confident that the mean fill volume for machine 1 exceeds that of machine 2 by between 0.0987 and 0.2813 fl. oz. b) 95% two-sided confidence interval: σ1 σ 2 2 σ2 σ 2 (x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2 n1 n 2 n1 n 2 (0.10) 2 (015) 2 . (010) 2 (015)2 . . (30.87 − 30.68) − 1.96 + ≤ µ1 − µ 2 ≤ ( 30.87 − 30.68) + 196 . + 12 10 12 10 0.0812 ≤ µ1 − µ 2 ≤ 0.299 We are 95% confident that the mean fill volume for machine 1 exceeds that of machine 2 by between 0.0812 and 0.299 fl. oz. Comparison of parts a and b: As the level of confidence increases, the interval width also increases (with all other values held constant). c) 95% upper-sided confidence interval: 2 σ1 σ 2 µ1 − µ 2 ≤ ( x1 − x2 ) + zα + 2 n1 n2 (010) 2 (015) 2 . . µ1 − µ 2 ≤ ( 30.87 − 30.68) + 1.645 + 12 10 µ1 − µ 2 ≤ 0.2813 With 95% confidence, we believe the fill volume for machine 1 exceeds the fill volume of machine 2 by no more than 0.2813 fl. oz. 10-7. x1 = 89.6 x2 = 92.5 2 σ1 = 1.5 σ 2 = 1.2 2 n1 = 15 n2 = 20 a) 95% confidence interval: σ1 σ 2 2 σ2 σ 2 (x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2 n1 n 2 n1 n 2
15 1.2 . 15 12 . . (89.6 − 92.5) − 196 . + ≤ µ1 − µ 2 ≤ (89.6 − 92.5) + 1.96 + 15 20 15 20 −3.684 ≤ µ1 − µ 2 ≤ −2.116 With 95% confidence, we believe the mean road octane number for formulation 2 exceeds that of formulation 1 by between 2.116 and 3.684. b) 1) The parameter of interest is the difference in mean road octane number, µ1 − µ 2 and ∆0 = 0 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 < 0 or µ1 < µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 z0 = σ1 σ 2 2 + 2 n1 n2 6) Reject H0 if z0 < −zα = −1.645 7) x1 = 89.6 x2 = 92.5 2 σ1 = 1.5 σ 2 = 1.2 2 n1 = 15 n2 = 20 (89.6 − 92.5) − 0 z0 = = −7.254 (15) 2 (12) 2 . . + 15 20 8) Since −7.25 < -1.645 reject the null hypothesis and conclude the mean road octane number for formulation 2 exceeds that of formulation 1 using α = 0.05. c) P-value = P ( z ≤ −7.25) = 1 − P ( z ≤ 7.25) = 1 − 1 ≅ 0 10-9. 95% level of confidence, E = 1, and z0.025 =1.96 2 2 z ( n ≅ 0.025 σ 12 + σ 2 = 2 ) 1.96 (1.5 + 1.2) = 10.37, n = 11, use n1 = n2 = 11 E 1 10-11. Catalyst 1 Catalyst 2 x1 = 65.22 x2 = 68.42 σ1 = 3 σ2 = 3 n1 = 10 n2 = 10 a) 95% confidence interval on µ1 − µ 2 , the difference in mean active concentration 2 σ1 σ 2 σ2 σ 2 (x1 − x2 ) − zα / 2 + 2 ≤ µ1 − µ 2 ≤ ( x1 − x2 ) + zα / 2 1 + 2 n1 n 2 n1 n 2 (3) 2 (3) 2 (3) 2 (3)2 (65.22 − 68.42) − 196 . + ≤ µ1 − µ 2 ≤ ( 65.22 − 68.42 ) + 1.96 + 10 10 10 10 −5.83 ≤ µ1 − µ 2 ≤ −0.57 We are 95% confident that the mean active concentration of catalyst 2 exceeds that of catalyst 1 by between 0.57 and 5.83 g/l. b) Yes, since the 95% confidence interval did not contain the value 0, we would conclude that the mean active concentration depends on the choice of catalyst.
10-13.1) The parameter of interest is the difference in mean active concentration, µ1 − µ 2 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 z0 = σ1 σ 2 2 + 2 n1 n2 6) Reject H0 if z0 < −zα/2 = −1.96 or z0 > zα/2 = 1.96 7) x1 = 750.2 x2 = 756.88 δ = 0 σ1 = 20 σ 2 = 20 n1 = 15 n2 = 8 (750.2 − 756.88) − 0 z0 = = −2.385 (20) 2 (20) 2 + 15 8 8) Since −2.385 < −1.96 reject the null hypothesis and conclude the mean active concentrations do differ significantly at α = 0.05. P-value = 2 (1 − Φ( 2.385)) = 2(1 − 0.99146) = 0.0171 The conclusions reached by the confidence interval of the previous problem and the test of hypothesis conducted here are the same. A two-sided confidence interval can be thought of as representing the “acceptance region” of a hypothesis test, given that the level of significance is the same for both procedures. Thus if the value of the parameter under test that is specified in the null hypothesis falls outside the confidence interval, this is equivalent to rejecting the null hypothesis. Section 10-3 10-17 a) 1) The parameter of interest is the difference in mean rod diameter, µ1 − µ 2 , with ∆0 = 0 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 t0 = 1 1 sp + n1 n 2 6) Reject the null hypothesis if t0 < − t α/ 2, n1 + n 2 − 2 where −t 0.025,30 = −2.042 or t0 > t α / 2, n1 + n 2 − 2 where t 0.025,30 = 2.042 ( n1 − 1)s1 + ( n2 − 1)s2 2 2 7) ) x1 = 8.73 x2 = 8.68 sp = n1 + n 2 − 2 2 14(0.35) + 16(0.40) s1 = 0.35 s2 = 0.40 2 = = 0.614 30 n1 = 15 n2 = 17 (8.73 − 8.68) t0 = = 0.230 1 1 0.614 + 15 17 8) Since −2.042 < 0.230 < 2.042, do not reject the null hypothesis and conclude the two machines do not produce rods with significantly different mean diameters at α = 0.05.
b) P-value =2P ( t > 0.230) > 2(0.40), P-value > 0.80 c) 95% confidence interval: t0.025,30 = 2.042 1 1 1 1 (x1 − x2 ) − t α / 2,n + n 1 2 −2 (sp ) + n1 n 2 ≤ µ1 − µ 2 ≤ (x1 − x2 ) + t α / 2, n1 + n 2 − 2 (sp ) + n1 n2 1 1 1 1 (8.73 − 8.68) − 2.042(0.614) + ≤ µ1 − µ 2 ≤ (8.73 − 8.68) + 2.042(0.643) + 15 17 15 17 − 0.394 ≤ µ1 − µ 2 ≤ 0.494 Since zero is contained in this interval, we are 95% confident that machine 1 and machine 2 do not produce rods whose diameters are significantly different. 10-21. a) 1) The parameter of interest is the difference in mean etch rate, µ1 − µ 2 , with ∆0 = 0 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 t0 = 1 1 sp + n1 n 2 6) Reject the null hypothesis if t0 < − t α/ 2, n1 + n 2 − 2 where − t 0.025,18 = −2.101 or t0 > t α / 2, n1 + n 2 − 2 where t 0.025,18 = 2.101 ( n1 − 1)s1 + ( n2 − 1)s2 2 2 7) x1 = 9.97 x2 = 10.4 sp = n1 + n 2 − 2 9(0.422) 2 + 9(0.231) 2 s1 = 0.422 s2 = 0.231 = = 0.340 18 n1 = 10 n2 = 10 (9.97 − 10.4) t0 = = −2.83 1 1 0.340 + 10 10 8) Since −2.83 < −2.101 reject the null hypothesis and conclude the two machines mean etch rates do significantly differ at α = 0.05. b) P-value = 2P (t < −2.83) 2(0.005) < P-value < 2(0.010) = 0.010 < P-value < 0.020 c) 95% confidence interval: t0.025,18 = 2.101 1 1 1 1 (x1 − x2 ) − t α / 2,n + n 1 2 −2 (sp ) + n1 n 2 ≤ µ1 − µ 2 ≤ (x1 − x2 ) + t α / 2, n1 + n 2 − 2 (sp ) + n1 n2 1 1 1 1 (9 .97 − 10 .4 ) − 2 .101 (.340 ) + ≤ µ 1 − µ 2 ≤ (9 .97 − 10 .4 ) + 2 .101(.340 ) + 10 10 10 10 − 0.749 ≤ µ1 − µ 2 ≤ −0.111 We are 95% confident that the mean etch rate for solution 2 exceeds the mean etch rate for solution 1 by between 0.1105 and 0.749.
d) According tothe normal probability plots, the assumption of normality appears to be met since the data from both samples fall approximately along straight lines. The equality of variances does not appear to be severely violated either since the slopes are approximately the same for both samples. Normal Probability Plot Normal Probability Plot .999 .999 .99 .99 .95 .95 Probability .80 Probability .80 .50 .50 .20 .20 .05 .05 .01 .01 .001 .001 9.5 10.0 10.5 10.0 10.1 10.2 10.3 10.4 10.5 10.6 10.7 solution solution Average: 9.97 Anderson-Darling Normality Test Average: 10.4 Anderson-Darling Normality Test StDev: 0.421769 A-Squared: 0.269 StDev: 0.230940 A-Squared: 0.211 N: 10 P-Value: 0.595 N: 10 P-Value: 0.804 10-27 a) 1) The parameter of interest is the difference in mean wear amount, µ1 − µ 2 . 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 t0 = s1 s2 2 + 2 n1 n2 6) Reject the null hypothesis if t0 < −t 0.025,27 where −t 0.025,27 = −2.052 or t0 > t 0.025,27 where t 0.025,27 = 2.052 since 2 s12 s 2 2 + n ν= 1 n2 = 26.98 2 s12 s2 2 n 1 + n2 n1 − 1 n 2 − 1 ν ≅ 26 (truncated) 7) x1 = 20 x2 = 15 ∆0 = 0 s1 = 2 s2 = 8 n1 = 25 n2 = 25 (20 − 15) − 0 t0 = = 3.03 (2) 2 (8) 2 + 25 25 8) Since 3.03 > 2.056 reject the null hypothesis and conclude that the data support the claim that the two companies produce material with significantly different wear at the 0.05 level of significance. b) P-value = 2P(t > 3.03), 2(0.0025) < P-value < 2(0.005) 0.005 < P-value < 0.010 c) 1) The parameter of interest is the difference in mean wear amount, µ1 − µ 2 2) H0 : µ1 − µ 2 = 0 3) H1 : µ1 − µ 2 > 0 4) α = 0.05
5) The teststatistic is ( x1 − x2 ) − ∆ 0 t0 = s1 s2 2 + 2 n1 n2 6) Reject the null hypothesis if t0 > t 0.05,27 where t 0.05, 26 = 1.706 since 7) x1 = 20 x2 = 15 s1 = 2 s2 = 8 ∆0 = 0 n1 = 25 n2 = 25 (20 − 15) − 0 t0 = = 3.03 (2) 2 (8) 2 + 25 25 8) Since 3.03 > 1.706 reject the null hypothesis and conclude that the data support the claim that the material from company 1 has a higher mean wear than the material from company 2 using a 0.05 level of significance. 10-29. If α = 0.01, construct a 99% lower one-sided confidence interval on the difference to answer question 10-28. t0.005,19 = 2.878 s12 s 2 2 s12 s 2 2 (x1 − x2 ) − tα / 2 ,ν + ≤ µ 1 − µ 2 ≤ (x1 − x 2 ) + tα / 2 ,ν + n1 n 2 n1 n 2 (10.2) 2 (20.1) 2 (10.2) 2 (20.1) 2 (103.5 − 99.7) − 2.878 + ≤ µ1 − µ 2 ≤ (103.5 − 99.7) − 2.878 + 12 13 12 13 − 14.34 ≤ µ1 − µ 2 ≤ 21.94 . Since the interval contains 0, we are 99% confident there is no difference in the mean coating thickness between the two temperatures; that is, raising the process temperature does not significantly reduce the mean coating thickness. 10-31 a.) N orm al P ro b ab ility P lo t for B ran d 1 ...B ra n d 2 M L E s tim a te s B ra nd 1 99 B ra nd 2 95 90 80 70 Percent 60 50 40 30 20 10 5 1 244 254 264 274 284 294 D a ta b . 1) The parameter of interest is the difference in mean overall distance, µ1 − µ 2 , with ∆0 = 0
2) H0 :µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 t0 = 1 1 sp + n1 n 2 6) Reject the null hypothesis if t0 < − t α/ 2, n1 + n 2 − 2 where − t 0.025,18 = −2.101 or t0 > t α / 2, n1 + n 2 − 2 where t 0.025,18 = 2.101 ( n1 − 1)s1 + ( n2 − 1)s2 2 2 7) x1 = 275.7 x2 = 265.3 sp = n1 + n 2 − 2 9(8.03) 2 + 9(10.04) 2 s1 = 8.03 s2 = 10.04 = = 9.09 20 n1 = 10 n2 = 10 (275.7 − 265.3) t0 = = 2.558 1 1 9.09 + 10 10 8) Since 2.558>2.101 reject the null hypothesis and conclude that the data do not support the claim that both brands have the same mean overall distance at α = 0.05. It appears that brand 1 has the higher mean differnce. c.)P-value = 2P (t < 2.558) P-value ≈ 2(0.01)=0.02 d.) d = 5 β=0.95 Power =1-0.95=0.05 0 . 275 2 ( 9 . 09 ) 3 e.) 1-β=0..75 β=0..27 d = = 0.165 n=100 n = 100 + 1 = 50 . 5 2(9.09) 2 Therefore, n=51 1 1 1 1 f.) (x1 − x 2 ) − tα ,ν s p + ≤ µ1 − µ 2 ≤ (x1 − x 2 ) + tα ,ν s p + n1 n2 n1 n2 1 1 1 1 (275.7 − 265.3) − 2.101(9.09) + ≤ µ1 − µ 2 ≤ (275.7 − 265.3) + 2.101(9.09) + 10 10 10 10 1.86 ≤ µ1 − µ 2 ≤ 18.94 Section 10-4 10-37 d = 868.375 sd = 1290, n = 8 where di = brand 1 - brand 2 99% confidence interval: s s d − t α / 2 , n −1 d ≤ µ d ≤ d + t α / 2 , n −1 d n n
1290 1290 868.375 − 3.499 ≤ µ d ≤ 868.375 + 3.499 8 8 −727.46 ≤ µd ≤ 2464.21 Since this confidence interval contains zero, we are 99% confident there is no significant difference between the two brands of tire. 10-39. 1) The parameter of interest is the difference in blood cholesterol level, µd where di = Before − After. 2) H0 : µ d = 0 3) H1 : µ d > 0 4) α = 0.05 5) The test statistic is d t0 = sd / n 6) Reject the null hypothesis if t0 > t 0.05,14 where t 0.05,14 = 1.761 7) d = 26.867 sd = 19.04 n = 15 26.867 t0 = = 5.465 19.04 / 15 8) Since 5.465 > 1.761 reject the null and conclude the data support the claim that the mean difference in cholesterol levels is significantly less after fat diet and aerobic exercise program at the 0.05 level of significance. Section 10-5 10-47. 1) The parameters of interest are the variances of concentration, σ1 , σ 2 2 2 2) H0 : σ1 = σ 2 2 2 3) H1 : σ1 ≠ σ 2 2 2 4) α = 0.05 5) The test statistic is 2 s1 f0 = s2 2 6) Reject the null hypothesis if f0 < f0.975,9 ,15 where f0.975,9 ,15 = 0.265 or f0 > f0.025,9 ,15 where f0.025,9,15 =3.12 7) n1 = 10 n2 = 16 s1 = 4.7 s2 = 5.8 (4.7) 2 f0 = = 0.657 (58) 2 . 8) Since 0.265 < 0.657 < 3.12 do not reject the null hypothesis and conclude there is insufficient evidence to indicate the two population variances differ significantly at the 0.05 level of significance. 10-51 a) 90% confidence interval for the ratio of variances: s12 σ 2 s2 2 f 1−α / 2, n1 −1, n2 −1 ≤ 12 ≤ 12 f α / 2, n1 −1, n2 −1 s σ 2 s2 2 (0.6) 2 σ1 (0.6)2 2 (0.8) 2 0.156 ≤ σ 2 ≤ (0.8) 2 6.39 2
2 σ1 0.08775 ≤ ≤ 3594 . σ2 2 b) 95% confidence interval: s1 2 σ 2 s2 f1− α / 2, n −1, n −1 ≤ 1 ≤ 1 fα / 2, n −1, n −1 s2 2 1 2 σ 2 s2 2 2 1 2 (0.6) 2 σ1 (0.6) 2 2 (0.8) 2 0104 ≤ σ 2 ≤ ( 0.8) 2 9.60 . 2 2 σ1 0.0585 ≤ ≤ 5.4 σ2 2 The 95% confidence interval is wider than the 90% confidence interval. c) 90% lower-sided confidence interval: s1 2 σ2 f1− α , n −1, n −1 ≤ 1 s2 2 1 2 σ2 2 (0.6) 2 σ12 ( 0.8) 2 0.243 ≤ σ 2 2 2 σ1 0.137 ≤ σ2 2 10-55 1) The parameters of interest are the thickness variances, σ1 , σ 2 2 2 2) H0 : σ1 = σ 2 2 2 3) H1 : σ1 ≠ σ 2 2 2 4) α = 0.01 5) The test statistic is s12 f0 = 2 s2 6) Reject the null hypothesis if f0 < f 0.995,10,12 where f 0.995,10,12 =0.1766 or f0 > f 0.005,10,12 where f 0.005,10,12 = 2.91 7) n1 = 11 n2 = 13 s1 = 10.2 s2 = 20.1 (10.2) 2 f0 = = 0.2575 (20.1) 2 8) Since 0.1766 >0.2575 > 5.0855 do not reject the null hypothesis and conclude the thickness variances are not equal at the 0.01 level of significance. 10-59 1) The parameters of interest are the overall distance standard deviations, σ1 , σ 2 2) H0 : σ1 = σ 2 2 2 3) H1 : σ1 ≠ σ 2 2 2 4) α = 0.05 5) The test statistic is
2 s1 f0 = s2 2 6) Reject the null hypothesis if f0 < f .0.975,9,9 =0.248 or f0 > f 0.025,9,9 = 4.03 7) n1 = 10 n2 = 10 s1 = 8.03 s2 = 10.04 2 (8.03) f0 = = 0.640 (10.04) 2 8) Since 0.248 < 0.640 < 4.04 do not reject the null hypothesis and conclude there is no evidence to support the claim that there is a difference in the standard deviation of the overall distance of the two brands at the 0.05 level of significance. 95% confidence interval: s1 2 σ 2 s2 f1− α / 2, n −1, n −1 ≤ 1 ≤ 1 fα / 2, n −1, n −1 s2 2 1 2 σ 2 s2 2 2 1 2 σ 12 (0.640)0.248 ≤ ≤ (0.640)4.03 σ2 2 σ 12 0.159 ≤ ≤ 2.579 σ2 2 Since the value 1 is contained within this interval, we are 95% confident there is no significant difference in the standard deviation of the overall distance of the two brands at the 0.05 level of significance. Section 10-6 10-61. 1) the parameters of interest are the proportion of defective parts, p1 and p2 2) H0 : p1 = p2 3) H1 : p1 ≠ p2 4) α = 0.05 5) Test statistic is p1 − p2 ˆ ˆ z0 = where 1 1 p (1 − p ) + ˆ ˆ n1 n2 x + x2 p= 1 ˆ n1 + n 2 6) Reject the null hypothesis if z0 < −z0.025 where −z0.025 = −1.96 or z0 > z0.025 where z0.025 = 1.96 7) n1 = 300 n2 = 300 x1 = 15 x2 = 8 15 + 8 p1 = 0.05 p2 = 0.0267 p= = 0.0383 300 + 300 0.05 − 0.0267 z0 = = 1.49 1 1 0.0383(1 − 0.0383) + 300 300 8) Since −1.96 < 1.49 < 1.96 do not reject the null hypothesis and conclude that yes the evidence indicates that there is not a significant difference in the fraction of defective parts produced by the two machines
at the 0.05level of significance. P-value = 2(1−P(z < 1.49)) = 0.13622 10-63. a) Power = 1 − β 1 1 1 1 z pq + − ( p1 − p 2 ) − z pq + − ( p1 − p 2 ) n n2 n β= α /2 α /2 1 1 n2 Φ − Φ σ p1 − p 2 ˆˆ ˆ σ p1 − p 2 ˆˆ ˆ 300(0.05) + 300(0.01) p= = 0.03 q = 0.97 300 + 300 0.05(1 − 0.05) 0.01(1 − 0.01) σ p1 − p 2 = + = 0.014 300 300 1.96 0.03(0.97) 1 + 1 − (0.05− 0.01) −1.96 0.03(0.97) 1 + 1 − (0.05 − 0.01) β= 300 300 300 300 Φ − Φ 0.014 0.014 = Φ(− 0.91) − Φ (− 4.81) = 0.18141 − 0 = 0.18141 Power = 1 − 0.18141 = 0.81859 2 zα / 2 ( p1 + p2 )(q1 + q2 ) + z p1q1 + p2 q2 2 β b) n = ( p1 − p2 )2 2 1.96 (0.05 + 0.01)(0.95 + 0.99) + 1.29 0.05(0.95) + 0.01(0.99) 2 = = 382.11 (0.05 − 0.01)2 n = 383 10-67 95% confidence interval on the difference: p1(1 − p1) p2 (1 − p2 ) p (1 − p1) p2 (1 − p2 ) ( p1 − p2 ) − zα / 2 + ≤ p1 − p2 ≤ ( p1 − p2 ) + zα / 2 1 + n1 n2 n1 n2 0.77(1 − 0.77) 0.6675(1 − 0.6675) 0.77(1 − 0.77) 0.6675(1 − 0.6675) ( 0.77 − 0.6675) − 196 . + ≤ p1 − p 2 ≤ ( 0.77 − 0.6675) + 196 . + 500 400 500 400 0.0434 ≤ p1 − p 2 ≤ 0.1616 Since this interval does not contain the value zero, we are 95% confident there is a significant difference in the proportions of support for increasing the speed limit between residents of the two counties and that the difference in proportions is between 0.0434 and 0.1616. Supplemental Exercises 10-69 a) Assumptions that must be met are normality, equality of variance, independence of the observations and of the populations. Normality and equality of variances appears to be reasonable, see normal probability plot. The data appear to fall along a straight line and the slopes appear to be the same. Independence of the observations for each sample is assumed. It is also reasonable to assume that the two populations are independent.
Normal Probability Plot Normal Probability Plot .999 .999 .99 .99 .95 .95 Probability Probability .80 .80 .50 .50 .20 .20 .05 .05 .01 .01 .001 .001 14 15 16 17 18 19 20 8 9 10 11 12 13 14 15 9-hour 1-hour Average: 16.3556 Anderson-Darling Normality Test Average: 11.4833 Anderson-Darling Normality Test StDev: 2.06949 A-Squared: 0.171 StDev: 2.37016 A-Squared: 0.158 N: 9 P-Value: 0.899 N: 6 P-Value: 0.903 b) x1 = 16.36 x2 = 11486 . s1 = 2.07 s2 = 2.37 n1 = 9 n2 = 6 99% confidence interval: t α/ 2, n1 + n 2 − 2 = t 0.005,13 where t 0.005,13 = 3.012 8(2.07) 2 + 5( 2.37) 2 sp = = 2.19 13 (x1 − x2 ) − t α / 2,n + n 1 2 −2 (sp ) 1 + 1 n1 n 2 ≤ µ1 − µ 2 ≤ (x1 − x2 ) + t α / 2 , n1 + n 2 − 2 sp ( ) 1 + 1 n1 n 2 1 1 1 1 (16.36 − 11.486) − 3.012(2.19) + ≤ µ1 − µ 2 ≤ (16.36 − 11486) + 3.012( 2.19) . + 9 6 9 6 140 ≤ µ1 − µ 2 ≤ 8.36 . c) Yes, we are 99% confident the results from the first test condition exceed the results of the second test condition by between 1.40 and 8.36 (×106 PA). 10-73 a) 1) The parameters of interest are the proportions of children who contract polio, p1 , p2 2) H0 : p1 = p2 3) H1 : p1 ≠ p2 4) α = 0.05 5) The test statistic is p1 − p 2 ˆ ˆ z0 = 1 1 p (1 − p ) + ˆ ˆ n1 n 2 6) Reject H0 if z0 < −zα /2 or z0 > zα/2 where zα/2 = 1.96 x1 110 x1 + x 2 7) p1 = = = 0.00055 (Placebo) p= = 0.000356 n1 201299 n1 + n 2 x2 33 p2 = = = 0.00016 (Vaccine) n2 200745 0.00055 − 0.00016 z0 = = 6.55 1 1 0.000356 (1 − 0.000356 ) + 201299 200745 8) Since 6.55 > 1.96 reject H0 and conclude the proportion of children who contracted polio is significantly different at α = 0.05. b) α = 0.01 Reject H0 if z0 < −zα /2 or z0 > zα/2 where zα/2 =2.33 z0 = 6.55 Since 6.55 > 2.33, reject H0 and conclude the proportion of children who contracted polio is different at α = 0.01. c) The conclusions are the same since z0 is so large it exceeds zα/2 in both cases.
10-79. 2 (0.9 + 0.6)(0.1 + 0.4) 2.575 + 1.28 0.9(0.1) + 0.6(0.4) 2 n= (0.9 − 0.6) 2 5.346 = = 59.4 0.09 n = 60 10-81. H0 : µ1 = µ 2 H1 : µ1 ≠ µ 2 n1 = n2 =n β = 0.10 α = 0.05 Assume normal distribution and σ1 = σ 2 = σ 2 2 2 µ1 = µ 2 + σ | µ − µ2 | σ 1 d= 1 = = 2σ 2σ 2 From Chart VI (e), n∗ = 50 n ∗ + 1 50 + 1 n= = = 25.5 2 2 n1 = n2 =26 10-83 a) No. Normal Probability Plot Normal Probability Plot .999 .999 .99 .99 .95 .95 Probability Probability .80 .80 .50 .50 .20 .20 .05 .05 .01 .01 .001 .001 23.9 24.4 24.9 30 35 40 mercedes volkswag Average: 24.67 Anderson-Darling Normality Test Average: 40.25 Anderson-Darling Normality Test StDev: 0.302030 A-Squared: 0.934 StDev: 3.89280 A-Squared: 1.582 N: 10 P-Value: 0.011 N: 10 P-Value: 0.000 b) The normal probability plots indicate that the data follow normal distributions since the data appear to fall along a straight line. The plots also indicate that the variances could be equal since the slopes appear to be the same.
Normal Probability Plot Normal Probability Plot .999 .99 .999 .95 .99 Probability .95 .80 Probability .80 .50 .50 .20 .20 .05 .05 .01 .01 .001 .001 24.5 24.6 24.7 24.8 24.9 39.5 40.5 41.5 42.5 mercedes volkswag Average: 24.74 Anderson-Darling Normality Test Average: 41.25 Anderson-Darling Normality Test StDev: 0.142984 A-Squared: 0.381 StDev: 1.21952 A-Squared: 0.440 N: 10 P-Value: 0.329 N: 10 P-Value: 0.230 c) By correcting the data points, it is more apparent the data follow normal distributions. Note that one unusual observation can cause an analyst to reject the normality assumption. d) 95% confidence interval on the ratio of the variances, σ 2 / σ 2 V M s2 = 149 V . f9,9 ,0.025 = 4.03 1 1 s2 = 0.0204 M f9 ,9,0.975 = = = 0.248 f9,9 ,0.025 4.03 s2 σ2 s2 V f9,9 ,0.975 < V < V f9 ,9,0.025 s2 σ M s2 2 M M 1.49 σ2V 1.49 0.248 < 2 < 4.03 0.0204 σ M 0.0204 σ2 V 18124 < . < 294.35 σ2M Since the does not include the value of unity, we are 95% confident that there is evidence to reject the claim that the variability in mileage performance is different for the two types of vehicles. There is evidence that the variability is greater for a Volkswagen than for a Mercedes. 10-85 a) Underlying distributions appear to be normal since the data fall along a straight line on the normal probability plots. The slopes appear to be similar, so it is reasonable to assume that σ 12 = σ 2 . 2 Normal Probability Plot for tip1...tip2 ML Estimates tip1 99 tip2 95 90 80 70 Percent 60 50 40 30 20 10 5 1 40 45 50 Data b) 1) The parameter of interest is the difference in mean volumes, µ1 − µ 2 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is
( x1 −x2 ) − δ t0 = 1 1 sp + n1 n2 6) Reject H0 if t0 < −t α / 2 , ν or z0 > t α / 2, ν where t α / 2 , ν = t 0.025,18 = 2.101 9(1.252) 2 + 9(0.843) 2 7) x1 = 752.7 x2 = 755.6 sp = = 107 . 18 s1 = 1.252 s2 = 0.843 n1 = 10 n2 = 10 (752.7 − 755.6) − 0 t0 = = −6.06 1 1 107 . + 10 10 8) Since −6.06 < −2.101, reject H0 and conclude there is a significant difference between the two wineries with respect to the mean fill volumes. 10-89 a.) The data from both depths appear to be normally distributed, but the slopes are not equal. Therefore, it may not be assumed that σ 12 = σ 2 . 2 Normal Probability Plot for surface...bottom ML Estimates surface 99 bottom 95 90 80 70 Percent 60 50 40 30 20 10 5 1 4 5 6 7 8 Data b.) 1) The parameter of interest is the difference in mean HCB concentration, µ1 − µ 2 , with ∆0 = 0 2) H0 : µ1 − µ 2 = 0 or µ1 = µ 2 3) H1 : µ1 − µ 2 ≠ 0 or µ1 ≠ µ 2 4) α = 0.05 5) The test statistic is ( x1 − x2 ) − ∆ 0 t0 = s1 s2 2 + 2 n1 n2 6) Reject the null hypothesis if t0 < − t 0.025,15 where − t 0.025,15 = −2.131 or t0 > t 0.025,15 where t 0.025,15 = 2.131 since
2 s12 s 2 2 + n ν= 1 n2 = 15.06 2 s12 s2 2 n 1 + n2 n1 − 1 n 2 − 1 ν ≅ 15 (truncated) 7) x1 = 4.804 x2 = 5.839 s1 = 0.631 s2 = 1.014 n1 = 10 n2 = 10 (4.804 − 5.839) t0 = = −2.74 (0.631) 2 (1.014) 2 + 10 10 8) Since –2.74 < -2.131 reject the null hypothesis and conclude that the data support the claim that the mean HCB concentration is different at the two depths sampled at the 0.05 level of significance. b) P-value = 2P(t < -2.74), 2(0.005) < P-value < 2(0.01) 0.001 < P-value < 0.02 2 c) ∆ = 2 α = 0.05 n1 = n2 = 10 d= =1 2(1) From Chart VI (e) we find β = 0.20, and then calculate Power = 1- β = 0.80 2 d.) ∆ = 2 α = 0.05 d= = 0.5 , β = 0.0 2(1) 50 + 1 From Chart VI (e) we find n=50 and n= = 25.5 , so n=26 2
Chapter 11 SelectedProblem Solutions Section 11-2 11-1. a) y i = β 0 + β1x1 + ε i S xx = 157.42 − 432 14 = 25.348571 43(572 ) S xy = 1697.80 − 14 = −59.057143 S xy −59.057143 β1 = = = −2.330 S xx 25.348571 β 0 = y − β1 x = 572 43 − ( −2.3298017)( 14 ) = 48.013 14 b) ˆ ˆ ˆ y = β 0 + β1 x y = 48.012962 − 2.3298017(4.3) = 37.99 ˆ c) y = 48.012962 − 2.3298017(3.7) = 39.39 ˆ d) e = y − y = 46.1 − 39.39 = 6.71 ˆ 11-5. a) Regression Analysis - Linear model: Y = a+bX Dependent variable: SalePrice Independent variable: Taxes -------------------------------------------------------------------------------- Standard T Prob. Parameter Estimate Error Value Level Intercept 13.3202 2.57172 5.17948 .00003 Slope 3.32437 0.390276 8.518 .00000 -------------------------------------------------------------------------------- Analysis of Variance Source Sum of Squares Df Mean Square F-Ratio Prob. Level Model 636.15569 1 636.15569 72.5563 .00000 Residual 192.89056 22 8.76775 -------------------------------------------------------------------------------- Total (Corr.) 829.04625 23 Correlation Coefficient = 0.875976 R-squared = 76.73 percent Stnd. Error of Est. = 2.96104 σ 2 = 8.76775 ˆ If the calculations were to be done by hand use Equations (11-7) and (11-8). y = 13.3202 + 3.32437 x b) y = 13.3202 + 3.32437(7.5) = 38.253 c) y = 13.3202 + 3.32437(58980) = 32.9273 . y = 32.9273 ˆ e = y − y = 30.9 − 32.9273 = −2.0273 ˆ d) All the points would lie along the 45% axis line. That is, the regression model would estimate the values exactly. At this point, the graph of observed vs. predicted indicates that the simple linear regression model provides a reasonable fit to the data.
Plot of Observedvalues versus predicted 50 45 Predicted 40 35 30 25 25 30 35 40 45 50 Observed 11-9. a) Yes, a linear regression would seem appropriate, but one or two points appear to be outliers. 9 8 7 6 5 y 4 3 2 1 0 60 70 80 90 100 x Predictor Coef SE Coef T P Constant -9.813 2.135 -4.60 0.000 x 0.17148 0.02566 6.68 0.000 S = 1.408 R-Sq = 71.3% R-Sq(adj) = 69.7% Analysis of Variance Source DF SS MS F P Regression 1 88.520 88.520 44.66 0.000 Residual Error 18 35.680 1.982 Total 19 124.200 b) σ 2 = 1.9818 and y = −9.8131 + 0.171484 x ˆ ˆ c) y = 4.76301 at x = 85 ˆ
11-11. a) Yes, a linear regression would seem appropriate. 40 30 20 y 10 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 x Predictor Coef SE Coef T P Constant 0.470 1.936 0.24 0.811 x 20.567 2.142 9.60 0.000 S = 3.716 R-Sq = 85.2% R-Sq(adj) = 84.3% Analysis of Variance Source DF SS MS F P Regression 1 1273.5 1273.5 92.22 0.000 Residual Error 16 220.9 13.8 Total 17 1494.5 b) σ 2 = 13.81 ˆ y = 0.470467 + 20.5673 x ˆ c) ˆ y = 0.470467 + 20.5673(1) = 21.038 d) ˆ y = 10.1371 e = 1.6629 Section 11-4 11-21. Refer to ANOVA of Exercise 11-5 a) 1) The parameter of interest is the regressor variable coefficient, β1. 2) H 0 : β1 = 0 3) H1 : β1 ≠ 0 4) α = 0.05, using t-test ˆ β1 5) The test statistic is t0 = ˆ se( β1 ) 6) Reject H0 if t0 < −tα/2,n-2 where −t0.025,22 = −2.074 or t0 > t0.025,22 = 2.074 7) Using the results from Exercise 11-5 3.32437 t0 = = 8.518 0.390276 8) Since 8.518 > 2.074 reject H 0 and conclude the model is useful α = 0.05.
b) 1) Theparameter of interest is the slope, β1 2) H 0 :β1 = 0 3) H 1:β1 ≠ 0 4) α = 0.05 MSR SS R / 1 5) The test statistic is f0 = = MSE SSE / ( n − 2) 6) Reject H0 if f0 > fα,1,22 where f0.01,1,22 = 4.303 7) Using the results from Exercise 10-5 636.15569 / 1 f0 = = 72.5563 192.89056 / 22 8) Since 72.5563 > 4.303, reject H 0 and conclude the model is useful at a significance α = 0.05. The F-statistic is the square of the t-statistic. The F-test is a restricted to a two-sided test, whereas the t-test could be used for one-sided alternative hypotheses. c) se ( β ) = ˆ σ2 ˆ 8 . 7675 1 = = . 39027 S xx 57 . 5631 ˆ 1 x 1 6 . 4049 2 se ( β 0 ) = σ2 + ˆ = 8 . 7675 + = 2 .5717 n S xx 24 57 . 5631 d) 1) The parameter of interest is the intercept, β0. 2) H 0 : β0 = 0 3) H 1 : β0 ≠ 0 4) α = 0.05, using t-test ˆ β0 5) The test statistic is t0 = ˆ se( β0 ) 6) Reject H0 if t0 < −tα/2,n-2 where −t0.025,22 = −2.074 or t0 > t0.025,22 = 2.074 7) Using the results from Exercise 11-5 13 . 3201 t0 = = 5 . 2774 2 . 5717 8) Since 5.2774 > 2.074 reject H 0 and conclude the intercept is not zero at α = 0.05. 11-25. Refer to ANOVA of Exercise 11-9 a) H 0 : β1 = 0 H 1 : β1 ≠ 0 α = 0.05 f 0 = 44.6567 f .05 ,1,18 = 4.416 f 0 > f α ,1,18 Therefore, reject H0. P-value = 0.000003. b) ˆ se( β1 ) = 0.0256613 ˆ se( β ) = 2.13526 0 c) H 0 : β0 = 0 H1 : β0 ≠ 0 α = 0.05
t0 = −4.59573 t.025 ,18 = 2.101 | t0 |> t α / 2 ,18 Therefore, reject H0. P-value = 0.00022. Sections 11-5 and 11-6 11-31. tα/2,n-2 = t0.025,12 = 2.179 a) 95% confidence interval on β1 . ˆ β ±t ˆ se ( β ) 1 α / 2 ,n − 2 1 − 2 .3298 ± t.025 ,12 (0 .2697 ) − 2 .3298 ± 2 .179 (0 .2697 ) − 2 .9175 . ≤ β 1 ≤ − 1 .7421 . b) 95% confidence interval on β0 . ˆ β ±t ˆ se ( β ) 0 . 025 ,12 0 48 . 0130 ± 2 .179 ( 0 . 5959 ) 46 . 7145 ≤ β 0 ≤ 49 . 3114 . c) 95% confidence interval on µ when x 0 = 2.5 . µ Y | x 0 = 48 .0130 − 2 .3298 ( 2 .5) = 42 .1885 ˆ ( x0 − x ) 2 µ Y | x 0 ± t.025 ,12 σ 2 ( 1 + ˆ ˆ n S xx ) ( 2. 5 − 3 .0714 ) 2 42 .1885 ± ( 2 .179 ) 1 .844 ( 14 + 1 25 . 3486 ) 42 .1885 ± 2 .179 ( 0 .3943 ) 41 .3293 ≤ µ Y | x 0 ≤ 43 .0477 ˆ d) 95% on prediction interval when x 0 = 2.5 . ( x0 − x ) 2 y0 ± t.025,12 σ 2 (1 + n + ˆ ˆ 1 S xx ) ( 2.5 − 3.0714 ) 2 42 .1885 ± 2.179 1.844 (1 + 14 + 1 25.348571 ) 42 .1885 ± 2.179 (1.1808 ) 38 .2489 ≤ y0 ≤ 46 .1281 It is wider because it depends on both the error associated with the fitted model as well as that with the future observation. 11-35. 99 percent confidence intervals for coefficient estimates -------------------------------------------------------------------------------- Estimate Standard error Lower Limit Upper Limit CONSTANT -6.33550 1.66765 -11.6219 -1.05011 Temperature 9.20836 0.03377 9.10130 9.93154 -------------------------------------------------------------------------------- a) 9.10130 ≤ β1 ≤ 9.31543 b) −11.6219 ≤ β0 ≤ −1.04911 1 (55−46.5)2 c) 500124 ± (2.228) 3.774609( 12 + . 3308.9994 ) 500124 ± 14037586 . . ∃ 498.72024 ≤ µ Y|x ≤ 50152776 . 0 1 (55− 46.5)2 d) 500124 ± (2.228) 3.774609(1 + 12 + . 3308.9994 )
500.124 ± 4.5505644 495.57344 ≤ y0 ≤ 504.67456 It is wider because the prediction interval includes error for both the fitted model and from that associated with the future observation. 11-41 a) − 43 .1964 ≤ β 1 ≤ − 30 .7272 b) 2530 .09 ≤ β 0 ≤ 2720 . 68 ( 20 −13 .3375 ) 2 c) 1886 .154 ± ( 2 . 101 ) 9811 . 21( 20 + 1 1114 .6618 ) 1886 . 154 ± 62 .370688 1823 . 7833 ≤ µ y | x 0 ≤ 1948 .5247 d) 1886 . 154 ± ( 2 . 101 ) 9811 . 21 (1 + 1 20 + ( 20 −13 . 3375 ) 2 1114 . 6618 ) 1886 . 154 ± 217 . 25275 1668 . 9013 ≤ y 0 ≤ 2103 . 4067 Section 11-7 11-43. Use the Results of exercise 11-5 to answer the following questions. a) SalePrice Taxes Predicted Residuals 25.9 4.9176 29.6681073 -3.76810726 29.5 5.0208 30.0111824 -0.51118237 27.9 4.5429 28.4224654 -0.52246536 25.9 4.5573 28.4703363 -2.57033630 29.9 5.0597 30.1405004 -0.24050041 29.9 3.8910 26.2553078 3.64469225 30.9 5.8980 32.9273208 -2.02732082 28.9 5.6039 31.9496232 -3.04962324 35.9 5.8282 32.6952797 3.20472030 31.5 5.3003 30.9403441 0.55965587 31.0 6.2712 34.1679762 -3.16797616 30.9 5.9592 33.1307723 -2.23077234 30.0 5.0500 30.1082540 -0.10825401 36.9 8.2464 40.7342742 -3.83427422 41.9 6.6969 35.5831610 6.31683901 40.5 7.7841 39.1974174 1.30258260 43.9 9.0384 43.3671762 0.53282376 37.5 5.9894 33.2311683 4.26883165 37.9 7.5422 38.3932520 -0.49325200 44.5 8.7951 42.5583567 1.94164328 37.9 6.0831 33.5426619 4.35733807 38.9 8.3607 41.1142499 -2.21424985 36.9 8.1400 40.3805611 -3.48056112 45.8 9.1416 43.7102513 2.08974865 b) Assumption of normality does not seem to be violated since the data appear to fall along a straight line.
Normal Probability Plot 99.9 99 95 cumulative percent 80 50 20 5 1 0.1 -4 -2 0 2 4 6 8 Residuals c) No serious departure from assumption of constant variance. This is evident by the random pattern of the residuals. Plot of Residuals versus Predicted Plot of Residuals versus Taxes 8 8 6 6 4 4 Residuals Residuals 2 2 0 0 -2 -2 -4 -4 26 29 32 35 38 41 44 3.8 4.8 5.8 6.8 7.8 8.8 9.8 Predicted Values Taxes d) R 2 ≡ 76.73% ; 11-47. a) R 2 = 71.27% b) No major departure from normality assumptions. Normal Probability Plot of the Residuals (response is y) 3 2 1 Residual 0 -1 -2 -2 -1 0 1 2 Normal Score c) Assumption of constant variance appears reasonable.
R idualsVers x es us Residuals Versus the Fitted Values (response is y) (response is y) 3 3 2 2 1 1 Residual Residual 0 0 -1 -1 -2 -2 60 70 80 90 100 0 1 2 3 4 5 6 7 8 x Fitted Value 11-49. a) R 2 = 85 . 22 % b) Assumptions appear reasonable, but there is a suggestion that variability increases with ∃ y. Residuals Versus x (response is y) Residuals Versus the Fitted Values (response is y) 5 5 Residual Residual 0 0 -5 -5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 10 20 30 40 x Fitted Value c) Normality assumption may be questionable. There is some “ bending” away from a straight line in the tails of the normal probability plot. Normal Probability Plot of the Residuals (response is y) 5 Residual 0 -5 -2 -1 0 1 2 Normal Score Section 11-10 11-55. a) y = −0.0280411 + 0.990987 x ˆ b) H 0 : β 1 = 0 H 1 : β1 ≠ 0 α = 0.05 f 0 = 79 . 838 f . 05 ,1 ,18 = 4 . 41 f 0 >> f α ,1 ,18 Reject H0 .
c) r =0 . 816 = 0 . 903 d) H 0 : ρ = 0 H1 : ρ ≠ 0 α = 0.05 R n−2 0 . 90334 18 t0 = = = 8 . 9345 1− R 2 1 − 0 . 816 t .025 ,18 = 2 . 101 t 0 > t α / 2 ,18 Reject H0 . e) H 0 : ρ = 0 . 5 H 1 : ρ ≠ 0 .5 α = 0.05 z 0 = 3 . 879 z .025 = 1 . 96 z 0 > zα / 2 Reject H0 . z.025 f) tanh(arctanh 0.90334 - 17 ) ≤ ρ ≤ tanh(arctanh 0.90334 + z.025 ) where z.025 = 196 . 17 . 0 . 7677 ≤ ρ ≤ 0 . 9615 . 11-59 n = 50 r = 0.62 a) H 0 : ρ = 0 H1 : ρ ≠ 0 α = 0.01 r n−2 0 . 62 48 t0 = = = 5 . 475 1− r 2 1 − ( 0 . 62 ) 2 t .005 , 48 = 2 . 683 t 0 > t 0 .005 , 48 Reject H 0 . P-value ≅ 0 ) where z.005 = 2.575. z.005 z.005 b) tanh(arctanh 0.62 - 47 ) ≤ ρ ≤ tanh(arctanh 0.62 + 47 0 .3358 ≤ ρ ≤ 0 . 8007 . c) Yes. 11-61. a) r = 0.933203 a) H0 :ρ = 0 H1 : ρ ≠ 0 α = 0.05 r n−2 0 . 933203 15 t0 = = 1 − ( 0 . 8709 ) = 10 . 06 1− r 2 t.025 ,15 = 2 . 131 t 0 > tα / 2 ,15 Reject H0. c) y = 0.72538 + 0.498081x ˆ H 0 : β1 = 0 H 1 : β1 ≠ 0 α = 0.05
f 0 =101 . 16 f . 05 ,1 ,15 = 4 . 545 f 0 >> f α ,1 ,15 Reject H0. Conclude that the model is significant at α = 0.05. This test and the one in part b are identical. d) H0 : β0 = 0 H1 : β0 ≠ 0 α = 0.05 t 0 = 0 . 468345 t . 025 ,15 = 2 . 131 t 0 > tα / / 2 ,15 Do not reject H0. We cannot conclude β0 is different from zero. e) No serious problems with model assumptions are noted. Residuals Versus x Residuals Versus the Fitted Values (response is y) (response is y) 3 3 2 2 1 1 Residual Residual 0 0 -1 -1 -2 -2 10 20 30 40 50 5 15 25 x Fitted Value Normal Probability Plot of the Residuals (response is y) 3 2 1 Residual 0 -1 -2 -2 -1 0 1 2 Normal Score Supplemental 11-65. a) y = 93.34 + 15.64 x ˆ b) H 0 : β1 = 0 H 1 : β1 ≠ 0 α = 0.05 f 0 = 12.872 f 0.05,1,14 = 4.60 f 0 > f 0.05,1,14 Reject H 0 . Conclude that β 1 ≠ 0 at α = 0.05. c) (7.961 ≤ β1 ≤ 23.322) d) (74.758 ≤ β 0 ≤ 111.923) ˆ e) y = 93.34 + 15.64(2.5) = 132.44
132.44 ± 2.145136.27 16 + 1 [ ( 2.5 − 2.325 ) 2 7.017 ] 132.44 ± 6.26 126.18 ≤ µ Y | x0 = 2.5 ≤ 138.70 ˆ 11-67 a) 15 10 y 5 0 0 500 1000 1500 2000 2500 3000 3500 x b) y = −0.8819 + 0.00385 x ˆ c) H 0 : β1 = 0 H1 : β1 ≠ 0 α = 0.05 f 0 = 122.03 f 0 > fα ,1, 48 Reject H0 . Conclude that regression model is significant at α = 0.05 d) No, it seems the variance is not constant, there is a funnel shape. Residuals Versus the Fitted Values (response is y) 3 2 1 0 Residual -1 -2 -3 -4 -5 0 5 10 Fitted Value e) y ∗ = 0.5967 + 0.00097 x . Yes, the transformation stabilizes the variance. ˆ 11-71 a) 110 100 90 80 days 70 60 50 40 30 16 17 18 index
b) The regressionequation is ˆ y = −193 + 15.296 x Predictor Coef SE Coef T P Constant -193.0 163.5 -1.18 0.258 x 15.296 9.421 1.62 0.127 S = 23.79 R-Sq = 15.8% R-Sq(adj) = 9.8% Analysis of Variance Source DF SS MS F P Regression 1 1492.6 1492.6 2.64 0.127 Error 14 7926.8 566.2 Total 15 9419.4 Cannot reject Ho; therefore we conclude that the model is not significant. Therefore the seasonal meteorological index (x) is not a reliable predictor of the number of days that the ozone level exceeds 0.20 ppm (y). c) 95% CI on β1 ˆ ˆ β 1 ± tα / 2 , n − 2 se ( β 1 ) 15 . 296 ± t .025 ,12 ( 9 . 421 ) 15 .296 ± 2 . 145 ( 9 . 421 ) − 4 . 912 ≤ β 1 ≤ 35 . 504 d) The normality plot of the residuals is satisfactory. However, the plot of residuals versus run order exhibits a strong downward trend. This could indicate that there is another variable should be included in the model, one that changes with time. 40 30 5 20 10 Residual Residual 0 0 -10 -20 -30 -5 -40 2 4 6 8 10 12 14 16 920 930 940 Observation Order Fitted Value
11-75 a) 940 y 930 920 920 930 940 x ˆ b) y = 33.3 + 0.9636 x c) Predictor Coef SE Coef T P Constant 33.3 171.7 0.19 0.851 x 0.9639 0.1848 5.22 0.001 S = 4.805 R-Sq = 77.3% R-Sq(adj) = 74.4% Analysis of Variance Source DF SS MS F P Regression 1 628.18 628.18 27.21 0.001 Residual Error 8 184.72 23.09 Total 9 812.90 Reject the hull hypothesis and conclude that the model is significant. 77.3% of the variability is explained by the model. d) H 0 : β1 = 1 H 1 : β1 ≠ 1 α=.05 ˆ β 1 − 1 0.9639 − 1 t0 = = = −0.1953 ˆ se( β 1 ) 0.1848 t a / 2,n − 2 = t .025,8 = 2.306 Since t 0 > −t a / 2,n − 2 , we cannot reject Ho and we conclude that there is not enough evidence to reject the claim that the devices produce different temperature measurements. Therefore, we assume the devices produce equivalent measurements. e) The residual plots to not reveal any major problems. 2 1 Normal Score 1 Residual 0 0 -1 -1 -2 -5 0 5 2 3 4 5 6 7 8 Residual Fitted Value
Chapter 12 SelectedProblem Solutions Section 12-1 10 223 553 12-1. a) X ′X = 223 5200.9 12352 553 12352 31729 1916.0 X ′y = 43550.8 104736.8 171.054 b) ˆ = 3.713 , so y = 171.054 + 3.714 x − 1.126 x β ˆ 1 2 − 1.126 c) y = 171.054 + 3.714(18) − 1.126(43) = 189.481 ˆ 12-5. Predictor Coef StDev T P Constant 33.449 1.576 21.22 0.000 xl -0.054349 0.006329 -8.59 0.000 x6 1.0782 0.6997 1.54 0.138 S = 2.834 R-Sq = 82.9% R-Sq(adj) = 81.3% Analysis of Variance Source DF SS MS F P Regression 2 856.24 428.12 53.32 0.000 Error 22 176.66 8.03 Total 24 1032.90 a) ˆ y = 33.4491 − 0.05435x1 + 1.07822 x2 b) σ 2 = 8.03 ˆ c) ˆ y = 33.4491 − 0.05435(300) + 1.07822(2) = 19.30 mpg. 12-7. Predictor Coef SE Coef T P Constant 383.80 36.22 10.60 0.002 Xl -3.6381 0.5665 -6.42 0.008 X2 -0.11168 0.04338 -2.57 0.082 S = 12.35 R-Sq = 98.5% R-Sq(adj) = 97.5% Analysis of Variance Source DF SS MS F P Regression 2 29787 14894 97.59 0.002 Residual Error 3 458 153 Total 5 30245 a) y = 383.80 − 3.6381x1 − 0.1119 x2 ˆ ˆ ˆ ˆ b) σ = 153.0 , se( β 0 ) = 36.22 , se( β1 ) = 0.5665 , and se( β 2 ) = .04338 ˆ2 c) y = 383 . 80 − 3 . 6381 ( 25 ) − 0 . 1119 (1000 ) = 180 . 95 ˆ d) Predictor Coef SE Coef T P Constant 484.0 101.3 4.78 0.041 Xl -7.656 3.846 -1.99 0.185 X2 -0.2221 0.1129 -1.97 0.188 X1X2 0.004087 0.003871 1.06 0.402 S = 12.12 R-Sq = 99.0% R-Sq(adj) = 97.6% Analysis of Variance Source DF SS MS F P Regression 3 29951.4 9983.8 67.92 0.015 Residual Error 2 294.0 147.0 Total 5 30245.3 y = 484 . 0 − 7 . 656 x1 − 0 . 222 x 2 − 0 . 0041 x12 ˆ
e) ˆ ˆ ˆ ˆ ˆ σ 2 = 147.0 , se( β 0 ) = 101.3 , se( β1 ) = 3.846 , se( β 2 ) = 0.113 and se( β12 ) = 0.0039 f) y = 484 . 0 − 7 . 656 ( 25 ) − 0 . 222 (1000 ) − 0 . 0041 ( 25 )(1000 ) = − 31 . 3 ˆ The predicted value is smaller 12-9. Predictor Coef SE Coef T P Constant 47.17 49.58 0.95 0.356 xl -9.735 3.692 -2.64 0.018 x2 0.4283 0.2239 1.91 0.074 x3 18.237 1.312 13.90 0.000 S = 3.480 R-Sq = 99.4% R-Sq(adj) = 99.3% Analysis of Variance Source DF SS MS F P Regression 3 30532 10177 840.55 0.000 Residual Error 16 194 12 Total 19 30725 a) y = 47 174 − .9 7352 x1 + .0 4283x 2 + 18 2375x 3 . . b) σ 2 = 12 ˆ c) ˆ ˆ ˆ ˆ se( β 0 ) = 49.5815 , se( β1 ) = 3.6916 , se ( β 2 ) = 0 . 2239 , and se( β 3 ) = 1.312 d) y = 47 174 − .9 7352 14.5) + 0.4283(220) + 18.2375(5) = 9143 . ( . Section 12-2 12-13. n = 10, k = 2, p = 3, α = 0.05 H 0 : β1 = β 2 = ... = β k = 0 H 1 : β j ≠ 0 for at least one j (1916) 2 SST = 371595.6 − = 4490 10 ∑ yi 1030 X' y = ∑ xi1 yi = 21310 ∑ xi 2 yi 44174 1916 â' X' y = [171.054 3.713 − 1.126] 43550.8 = 371535.9 ˆ 104736.8 2 1916 SS R = 371535.9 − = 4430.38 10 SS E = SST − SS R = 4490 − 4430.38 = 59.62 SS R 4430.38 / 2 f0 = k SS E = = 260.09 n− p 59.62 / 7 f 0.05, 2, 7 = 4.74 f 0 > f 0.05, 2, 7 Reject H0 and conclude that the regression model is significant at α = 0.05. b) H 0 : β1 = 0 β2 = 0
H 1 :β1 ≠ 0 β2 ≠ 0 ˆ β1 ˆ β2 t0 = t0 = ˆ se( β ) ˆ se( β 2 ) 1 3.713 − 1.126 = = 19.20 = = −13.08 0.1934 0.0861 t α / 2,7 = t.025,7 = 2.365 Reject H0 Reject H0 Both regression coefficients are significant 12-17. a) H 0 : β1 = β 6 = 0 H1 : at least one β ≠ 0 f 0 = 53.3162 fα , 2, 22 = f .05, 2, 22 = 3.44 f 0 > fα , 2, 22 Reject H0 and conclude regression model is significant at α = 0.05 b) H 0 : β1 = 0 H 1 : β1 ≠ 0 t0 = −8.59 t.025, 25 − 3 = t.025, 22 = 2.074 | t0 |> tα / 2, 22 , Reject H0 and conclude β1 is significant at α = 0.05 H0 : β6 = 0 H1 : β 6 ≠ 0 α = 0.05 t 0 = 1.5411 | t0 |> tα / 2, 22 , / Do not reject H0, conclude that evidence is not significant to state β6 is significant at α = 0.05. No, only x1 contributes significantly to the regression. 12-21. a) H 0 : β1 = β 2 = β12 = 0 H1 at least one βj ≠ 0 α = 0.05 f 0 = 67.92 fα ,3, 2 = f.05,3, 2 = 19.16 f 0 > fα ,3, 2 / Reject H0 b) H 0 : β 12 = 0 H 1 : β12 ≠ 0 α = 0.05
SSR ( β12 | β 1 , β 2 ) = 29951 .4 − 29787 = 164 .4 SSR 164 .4 f0 = = = 1.07 MS E 153 f .05 ,1, 2 = 18 .51 f 0 > fα ,1, 2 / Do not reject H0 c) σ 2 = 147.0 ˆ σ2 (no interaction term) = 153.0 MSE ( σ 2 ) was reduced in the interaction term model due to the addition of this term. 12-23. a) H 0 : β1 = β 2 = β 3 = 0 for all j H1 : β j ≠ 0 for at least one j f 0 = 840.55 f.05,3,16 = 3.24 f 0 > fα ,3,16 Reject H0 and conclude regression is significant at α = 0.05 b) α = 0.05 t α / 2 , n − p = t. 025,16 = 2. 12 H 0 : β1 = 0 β2 = 0 β3 = 0 H1: β1 ≠ 0 β2 ≠ 0 β3 ≠ 0 t 0 = −2.637 t0 = 1.91 t 0 = 13. 9 | t 0 | > t α / 2 ,16 | t 0 | > t α / 2 ,16 / | t 0 | > t α / 2 ,16 Reject H0 Do not reject H0 Reject H0 Sections 12-3 and 12-4 12-27. a) − 0.00657 ≤ β 8 ≤ −0.00122 b) σ 2 x '0 ( X' X) −1 x 0 = 0.497648 = se( µ Y | x0 ) ˆ ˆ c) µY |x0 = −7.63449 + 0.00398(2000) + 0.24777(60) − 0.00389(1800) = 8.19 ˆ µY |x0 ± t.025 , 24 se( µ Y | x0 ) ˆ ˆ 8.19 ± ( 2.064)(0.497648) 8.19 ± 1.03 7.16 ≤ µY |x0 ≤ 9.22 12-29. a) 95 % CI on coeficients ˆ β 1 ± t a / 2,n − p ( β 1 ) 0.0972 ≤ β 1 ≤ 1.4174 − 1.9646 ≤ β 2 ≤ 17.0026 − 1.7953 ≤ β 3 ≤ 6.7613 − 1.7941 ≤ β 4 ≤ 0.8319
b) µ Y| x = 290.44 ˆ 0 se( µY | x0 ) = 7.61 ˆ t.025, 7 = 2.365 µ Y | x0 ± tα / 2,n − p se( µ Y | x0 ) ˆ ˆ 290.44 ± (2.365)(7.61) 272.44 ≤ µ Y | x0 ≤ 308.44 ′ c) y 0 ± tα / 2,n − p σ 2 (1 + x 0 ( X′X) −1 x 0 ) ˆ ˆ 290.44 ± 2.365(14.038) 257.25 ≤ y0 ≤ 323.64 12-31 a)95% Confidence Interval on coefficients − 0.595 ≤ β 2 ≤ 0.535 0.229 ≤ β 3 ≤ 0.812 − 0.216 ≤ β 4 ≤ 0.013 − 7.982 ≤ β 5 ≤ 2.977 b) µ Y | x = 8.99568 ˆ 0 se( µ Y | x0 ) = 0.472445 ˆ t .025,14 = 2.145 µY | x0 ± tα / 2, n − p se( µY | x0 ) ˆ ˆ 8.99568 ± (2.145)(0.472445) 7.982 ≤ µY | x0 ≤ 10.009 c) y0 = . 99568 8 se( y 0 ) = 1.00121 ˆ 8.99568 ± 2.145(1.00121) 6.8481 ≤ y0 ≤ 11.143 12-35. a) 0. 3882 ≤ βPts ≤ 0. 5998 b) y = −5.767703 + 0.496501x Pts ˆ c) 0.4648 ≤ β Pts ≤ 0.5282 d) The simple linear regression model has the shorter interval. Yes, the simple linear regression model in this case is preferable. Section 12-5 2 12-37. a) r = 0.82897 b) Normality assumption appears valid.
Normal Probability Plotof the Residuals (response is y) 5 Residual 0 -5 -2 -1 0 1 2 Normal Score c) Assumption of constant variance appears reasonable. Residuals Versus x6 Residuals Versus xl (response is y) (response is y) 5 5 Residual Residual 0 0 -5 -5 1 2 3 4 100 200 300 400 500 x6 xl Residuals Versus the Fitted Values (response is y) 5 Residual 0 -5 10 20 30 Fitted Value d) Yes, observations 7, 10, and 18 12-39. a) r 2 = 0.985 b) r 2 = 0.990 r2 increases with addition of interaction term. No, adding additional regressor will always increase r2 12-41 a) There is some indication of nonconstant variance since the residuals appear to “fan out” with increasing values of y.
Residual Plot fory 8 5 Residuals 2 -1 -4 -7 0 40 80 120 160 200 240 Predicted b) Source Sum of Squares DF Mean Square F-Ratio P-value Model 30531.5 3 10177.2 840.546 .0000 Error 193.725 16 12.1078 Total (Corr.) 30725.2 19 R-squared = 0.993695 Stnd. error of est. = 3.47963 R-squared (Adj. for d.f.) = 0.992513 Durbin-Watson statistic = 1.77758 R 2 = 0 . 9937 or 99.37 %; 2 R Adj = 0 . 9925 or 99.25%; c) Model fitting results for: log(y) -------------------------------------------------------------------------------- Independent variable coefficient std. error t-value sig.level CONSTANT 6.22489 1.124522 5.5356 0.0000 x1 -0.16647 0.083727 -1.9882 0.0642 x2 -0.000228 0.005079 -0.0448 0.9648 x3 0.157312 0.029752 5.2875 0.0001 -------------------------------------------------------------------------------- R-SQ. (ADJ.) = 0.9574 SE= 0.078919 MAE= 0.053775 DurbWat= 2.031 Previously: 0.0000 0.000000 0.000000 0.000 20 observations fitted, forecast(s) computed for 0 missing val. of dep. var. y ∗ = 6.22489 − 016647 x1 − 0.000228x 2 + 0.157312 x 3 .
d) Residual Plot for log(y) 0.1 0.05 Residuals 0 -0.05 -0.1 -0.15 4 4.3 4.6 4.9 5.2 5.5 Predicted Plot exhibits curvature There is curvature in the plot. The plot does not give much more information as to which model is preferable. e) Residual Plot for log(y) 0.1 0.05 Residuals 0 -0.05 -0.1 -0.15 3.3 5.3 7.3 9.3 11.3 x3 Plot exhibits curvature Variance does not appear constant. Curvature is evident. f) Model fitting results for: log(y) Independent variable coefficient std. error t-value sig.level CONSTANT 6.222045 0.547157 11.3716 0.0000 x1 -0.198597 0.034022 -5.8374 0.0000 x2 0.009724 0.001864 5.2180 0.0001 1/x3 -4.436229 0.351293 -12.6283 0.0000 -------------------------------------------------------------------------------- R-SQ. (ADJ.) = 0.9893 SE= 0.039499 MAE= 0.028896 DurbWat= 1.869 Previously: 0.9574 0.078919 0.053775 2.031 20 observations fitted, forecast(s) computed for 0 missing val. of dep. var. Analysis of Variance for the Full Regression Source Sum of Squares DF Mean Square F-Ratio P-value Model 2.75054 3 0.916847 587.649 .0000 Error 0.0249631 16 0.00156020 Total (Corr.) 2.77550 19 R-squared = 0.991006 Stnd. error of est. = 0.0394993 R-squared (Adj. for d.f.) = 0.98932 Durbin-Watson statistic = 1.86891
Residual Plot forlog(y) 0.08 0.05 Residuals 0.02 -0.01 -0.04 -0.07 3.8 4.1 4.4 4.7 5 5.3 Predicted Using 1/x3 The residual plot indicates better conformance to assumptions. Curvature is removed when using 1/x3 as the regressor instead of x3 and the log of the response data. Section 12-6 2 12-47. a) y = −1.633 + 1.232 x − 1.495 x ˆ b) f0 = 1858613, reject H0 c) t0 = −601.64, reject H 0 d) Model is acceptable, observation number 10 has large leverage. Residuals Versus x Residuals Versus the Fitted Values (response is y) (response is y) 1 1 Residual 0 Residual 0 -1 -1 0.0 0.5 1.0 1.5 2.0 2.5 -7 -6 -5 -4 -3 -2 -1 0 x Fitted Value Normal Probability Plot of the Residuals (response is y) 1 Residual 0 -1 -1 0 1 Normal Score
x−x 12-49.y = 759.395 − 90.783x'−47.166( x' ) 2 , where ˆ x' = Sx 285 − 297.125 a) At x = 285 x' = = −1.016 11.9336 y = 759.395 − 90.783(−1.106) − 47.166(−1.106) 2 = 802.943 ˆ psi b) y = 759.395 − 90.783( x11.9336 ) − 47.166( ˆ − 297.125 11.9336 ) x − 297.125 2 y = 759.395 − 7.607( x − 297.125) − 0.331( x − 297.125) 2 ˆ y = −26204.14 + 189.09 x − 0.331x 2 ˆ c) They are the same. d) y ' = 0.385 − 0.847 x'−0.440( x' ) 2 ˆ y− y x− x where y ' = and x' = Sy Sx The "proportion" of total variability explained is the same for both standardized and un-standardized models. 2 Therefore, R is the same for both models. y− y x− x y ' = β 0 + β1∗ x'+ β11 ( x' ) 2 ∗ ∗ where y' = and x' = y ' = β 0 + β1∗ x'+ β11 ( x' ) 2 ∗ ∗ Sy Sx 12-51 a) Predictor Coef SE Coef T P Constant -1.769 1.287 -1.37 0.188 xl 0.4208 0.2942 1.43 0.172 x2 0.2225 0.1307 1.70 0.108 x3 -0.12800 0.07025 -1.82 0.087 x1x2 -0.01988 0.01204 -1.65 0.118 x1x3 0.009151 0.007621 1.20 0.247 x2x3 0.002576 0.007039 0.37 0.719 x1^2 -0.01932 0.01680 -1.15 0.267 x2^2 -0.00745 0.01205 -0.62 0.545 x3^3 0.000824 0.001441 0.57 0.575 S = 0.06092 R-Sq = 91.7% R-Sq(adj) = 87.0% Analysis of Variance Source DF SS MS F P Regression 9 0.655671 0.072852 19.63 0.000 Residual Error 16 0.059386 0.003712 Total 25 0.715057 y = −1.769 + 0.421x1 + 0.222 x2 − 0.128 x3 − 0.02 x1 x2 + 0.009 x1 x3 + ˆ 2 2 2 0.003x2 x3 − 0.019 x1 − 0.007 x2 + 0.001x3 b) H0 : all β 1 = β 2 = β 3 = Κ = β 33 = 0 H1: at least 1 β j ≠ 0 f 0 = 19.628 f.05,9,16 = 2.54 f 0 > fα ,9,16 Reject H0 and conclude that the model is significant at α = 0.05 c) Model is acceptable. d) H 0 : β11 = β 22 = β 33 = β12 = β13 = β 23 = 0
H1: at leastone βij ≠ 0 SS R ( β 11 , β 22 , β 33 , β12 , β 13 , β 23 | β 1 , β 2 , β 3 , β 0 ) / r 0.0359 f0 = = 6 = 1.612 MS E 0.003712 f .05, 6,16 = 2.74 f 0 > f .05,6,16 / Do not reject H0 SS R ( β 12 , β13 , β 23 , β11 , β 22 , β 33 | β 1 , β 2 , β 3 , β 0 ) = SS R ( β1 , β 2 , β 3 , β 12 , β 13 , β 23 , β 11 , β 22 , β 33 | β 0 ) − SS R ( β 1 β 2 β 3 | β 0 ) = 0.65567068 − 0.619763 = 0.0359 Reduced Model: y = β 0 + β 1 x1 + β 2 x 2 + β 3 x 3 12-55. a) The min. MSE equation is x1, x2, x3, x4, x5, x6, x7, x8 MS E = 6.58 cp = 5. 88 The min. Cp x5, x8, x10 C p = 5.02 MS E = 7.97 b) ˆ y = 34.434 − 0.048x1 MSE = 8.81 C p = 5.55 c) Same as part b. d) y = 0.341 + 2.862 x 5 + 0.246 x 8 − 0.010 x10 ˆ MS E = 7.97 C p = 5.02 e) Minimum Cp and backward elimination result in the same model. Stepwise and forward selection result in the same model. Because it is much smaller, the minimum Cp model seems preferable. 12-61. a) Min. Cp y = −3.517 + 0.486 x1 − 0.156 x9 ˆ C p = −1.67 b) Min MSE model is x1, x7, x9, MSE = 1. 67 , C p = −0.77 y = −.5 964 + . 495x1 + . 025x7 − . 163x9 0 0 0 2 c) Max. adjusted R2 model is x1, x7, x9, Adj. R = 0.98448 Yes, same as Min. MSE model. Supplemental Exercises 12-65. a) H 0 : β 3∗ = β 4 = β 5 = 0 H1 : β j ≠ 0 for at least one j α = 0.01 f0 = 1323. 62 f.01, 3, 36 = 4 . 38 f0 >> fα , 3, 36 Reject H0 and conclude regression is significant. P-value < 0.00001
b) α =0.01 t.005, 36 = 2 . 72 H0 :β3∗ =0 H0:β4 = 0 H 0 :β5 = 0 H1: β3∗ ≠ 0 H1:β4 ≠ 0 H1:β5 ≠ 0 t0 = −1. 32 t 0 = 19. 97 t 0 = 2 . 48 | t 0 | > t α / 2 , 36 / | t 0 | > t α / 2 , 36 | t 0 | > tα / 2 , 36 / Do not reject H0 Reject H0 Do not reject H0 Only regressor x4 is significant c) Curvature is evident in the residuals vs. regressor plots from this model. 12-67. a) y = −0.908 + 5.482 x1 + 1.126 x2 − 3.920 x3 − 1.143x4 ˆ b) H 0 : β1 = β 2 = β 3 = β 4 = 0 H1 : β j ≠ 0 for at least one j α = 0.05 f 0 = 109.02 f.05, 4,19 = 2.90 f 0 >> fα , 4,19 Reject H0 and conclude regression is significant at α = 0.05. α = 0.05 t. 025,19 = 2 . 093 H 0 : β1 = 0 H0 : β2 = 0 H 0 : β3 = 0 H0 : β4 = 0 H 1 : β1 ≠ 0 H1 : β 2 ≠ 0 H1 : β 3 ≠ 0 H1 : β 4 ≠ 0 t 0 = 11.27 t0 = 14.59 t 0 = −6. 98 t 0 = −8. 11 | t 0 | > t α / 2 ,19 | t 0 | > t α / 2 ,19 | t 0 | > t α / 2 ,19 | t 0 | > t α / 2 ,19 Reject H0 Reject H0 Reject H0 Reject H0 c) The residual plots are more pleasing than those in Exercise 12-66. 12-69. a) y = −3982.1 + 1.0964x1 + 0.1843x3 + 3.7456x4 + 0.8343x5 − 16.2781x6 ˆ MS E ( p) = 694.93 C p = 5.62 b) y = −4280.2 + 1.442x1 + 0.209x3 + 0.6467x5 − 17.5103x6 ˆ MS E ( p) = 714.20 C p = 5.57 c) Same as model b. d) Models from parts b. and c. are identical. Model in part a. is the same with x4 added in. MSE model in part a. = 694.93 C p = 5.62 MSE model in parts b.&c. = 714.20 C p = 5.57 12-71. ˆ∗ a) VIF(β3 ) = 51.86 ˆ VIF ( β 4 ) = 9.11 ˆ VIF ( β ) = 28.99 5 Yes, VIFs for x and x5 exceed 10. 3 b) Model from Exercise 12-65: y = 19.69 − 1.27 x3 + 0.005 x4 + 0.0004 x5 ˆ
SS R 12-73. a) R2 = SST SS R = R 2 ( SST ) = 0.94(0.50) = 0.47 SS E = SST − SS R = 0.5 − 0.47 = 0.03 H 0 : β1 = β 2 = ... = β 6 = 0 H 1 : β j ≠ 0 for at least one j. α = 0.05 SS R / k 0.47 / 6 f0 = = = 18.28 SS E / n − p 0.03 / 7 f .05, 6, 7 = 3.87 f 0 > fα , 6 , 7 Reject H0. b) k = 5 n = 14 p=6 R 2 = 0.92 SS R ' = R 2 ( SST ) = 0.92(0.50) = 0.46 SS E ' = SST − SS R ' = 0.5 − 0.46 = 0.04 SS R ( β j , β i ,i =1, 2,Λ .6,i ≠ j | β 0 ) = SS R ( full ) − SS R (reduced ) = 0.47 − 0.46 = 0.01 SS R ( β j | β i ,i =1, 2,Λ , 6,i ≠ j | β 0 ) / r 0.01 / 1 f0 = = =2 SS E ' /(n − p ) 0.04 / 8 f .05,1,8 = 5.32 f 0 > f α ,1,8 / Do not reject H0 and conclude that the evidence is insufficient to claim that the removed variable is significant at α = 0.05 SS E 0.04 c) MS E (reduced ) = = = 0.005 n− p 8 0.03 MS E ( full ) = = 0.00429 7 No, the MSE is larger for the reduced model, although not by much. Generally, if adding a variable to a model reduces the MSE it is an indication that the variable may be useful in explaining the response variable. Here the decrease in MSE is not very great because the added variable had no real explanatory power.
Chapter 13 SelectedProblem Solutions Section 13-2 13-1. a) Analysis of Variance for STRENGTH Source DF SS MS F P COTTON 4 475.76 118.94 14.76 0.000 Error 20 161.20 8.06 Total 24 636.96 Reject H0 and conclude that cotton percentage affects mean breaking strength. b) Tensile strength seems to increase to 30% cotton and declines at 35% cotton. 25 STRENGTH 15 5 15 20 25 30 35 COTTON c) The normal probability plot and the residual plots show that the model assumptions are reasonable. Residuals Versus the Fitted Values (response is STRENGTH) Normal Probability Plot of the Residuals (response is STRENGTH) 6 6 5 5 4 4 3 3 2 2 Residual Residual 1 1 0 0 -1 -1 -2 -2 -3 -3 -4 -4 10 15 20 -2 -1 0 1 2 Fitted Value Normal Score Residuals Versus COTTON (response is STRENGTH) 6 5 4 3 2 Residual 1 0 -1 -2 -3 -4 15 25 35 COTTON 13-3. a) Analysis of Variance for STRENGTH Source DF SS MS F P TECHNIQU 3 489740 163247 12.73 0.000 Error 12 153908 12826 Total 15 643648
Reject H0. Techniquesaffect the mean strength of the concrete. b) P-value ≅ 0 c) Residuals are acceptable Residuals Versus TECHNIQU Residuals Versus the Fitted Values (response is STRENGTH) (response is STRENGTH) 200 200 100 100 Residual Residual 0 0 -100 -100 -200 -200 1 2 3 4 2650 2750 2850 2950 3050 3150 TECHNIQU Fitted Value Normal Probability Plot of the Residuals (response is STRENGTH) 2 1 Normal Score 0 -1 -2 -200 -100 0 100 200 Residual 13-5. a) Analysis of Variance for CONDUCTIVITY Source DF SS MS F P COATINGTYPE 4 1060.5 265.1 16.35 0.000 Error 15 243.3 16.2 Total 19 1303.8 Reject H0 ; P-value ≅ 0. b) There is some indication that the variability of the response may be increasing as the mean response increases. There appears to be an outlier on the normal probability plot. Residuals Versus COATINGT (response is CONDUCTI) Residuals Versus the Fitted Values (response is CONDUCTI) 5 5 0 Residual 0 Residual -5 -5 -10 -10 1 2 3 4 5 130 135 140 145 COATINGT Fitted Value
Normal Probability Plotof the Residuals (response is CONDUCTI) 2 1 Normal Score 0 -1 -2 -10 -5 0 5 Residual c) 95% Confidence interval on the mean of coating type 1. MSE MSE y1 − t 0.025,15 ≤ µ i ≤ y1 + t 0.015,15 n n 16.2 16.2 145.00 − 2.131 ≤ µ1 ≤ 145.00 + 2.131 4 4 140.71 ≤ µ1 ≤ 149.29 d.) 99% confidence interval on the difference between the means of coating types 1 and 4. 2MSE 2MSE y1 − y4 − t 0.005,15 ≤ µ1 − µ 4 ≤ y1 − y 4 + t 0.005,15 n n 2(16.2) 2(16.2) (145.00 − 129.25) − 2.947 ≤ µ1 − µ 4 ≤ (145.00 − 129.25) − 2.947 4 4 7.36 ≤ µ1 − µ 4 ≤ 24.14 13-9. a) Analysis of Variance for STRENGTH Source DF SS MS F P AIRVOIDS 2 1230.3 615.1 8.30 0.002 Error 21 1555.8 74.1 Total 23 2786.0 Reject H0 b) P-value = 0.002 c) The residual plots show that the assumptions of equality of variance is reasonable. The normal probability plot has some curvature in the tails.
Residuals Versus theFitted Values (response is STRENGTH) 10 Residual 0 -10 75 85 95 Fitted Value Residuals Versus AIRVOIDS (response is STRENGTH) 10 Residual 0 -10 1 2 3 AIRVOIDS Normal Probability Plot of the Residuals (response is STRENGTH) 2 1 Normal Score 0 -1 -2 -10 0 10 Residual d) 95% Confidence interval on the mean of retained strength where there is a high level of air voids MSE MSE y3 − t 0.025, 21 ≤ µ i ≤ y3 + t 0.015, 21 n n 74.1 74.1 8.229 − 2.080 ≤ µ 3 ≤ 8.229 + 2.080 8 8 69.17 ≤ µ1 ≤ 81.83 e) 95% confidence interval on the difference between the means of retained strength at the high level and the low levels of air voids. 2MSE 2MSE y1 − y3 − t 0.025,21 ≤ µ1 − µ 3 ≤ y1 − y3 + t 0.025,21 n n 2(74.1) 2(74.1) (92.875 − 75.5) − 2.080 ≤ µ1 − µ 4 ≤ (92.875 − 75.5) − 2.080 8 8 8.42 ≤ µ1 − µ 4 ≤ 26.38
Section 13-3 13-21 a) Analysis of Variance for OUTPUT Source DF SS MS F P LOOM 4 0.3416 0.0854 5.77 0.003 Error 20 0.2960 0.0148 Total 24 0.6376 Reject H0, and conclude that there are significant differences among the looms. MS Treatments − MS E 0.0854 − 0.0148 b) σ τ2 = ˆ = = 0.01412 n 5 c) σ = MS E = 0.0148 ˆ2 d) Residuals plots are acceptable Residuals Versus LOOM Residuals Versus the Fitted Values (response is OUTPUT) (response is OUTPUT) 0.2 0.2 0.1 Residual 0.1 Residual 0.0 0.0 -0.1 -0.1 -0.2 -0.2 1 2 3 4 5 3.8 3.9 4.0 4.1 LOOM Fitted Value Normal Probability Plot of the Residuals (response is OUTPUT) 2 1 Normal Score 0 -1 -2 -0.2 -0.1 0.0 0.1 0.2 Residual Section 13-4 13-25. a) Analysis of Variance for SHAPE Source DF SS MS F P NOZZLE 4 0.102180 0.025545 8.92 0.000 VELOCITY 5 0.062867 0.012573 4.39 0.007 Error 20 0.057300 0.002865 Total 29 0.222347 Reject H0, and conclude that nozzle type affects the mean shape measurement.
1.15 1.15 1.05 1.05 SHAPE SHAPE 0.95 0.95 0.85 0.85 0.75 0.75 11.73 14.37 16.59 20.43 23.46 28.74 1 2 3 4 5 VELOCITY NOZZLE b) Fisher's pairwise comparisons Family error rate = 0.268 Individual error rate = 0.0500 Critical value = 2.060 Intervals for (column level mean) - (row level mean) 1 2 3 4 2 -0.15412 0.01079 3 -0.20246 -0.13079 -0.03754 0.03412 4 -0.24412 -0.17246 -0.12412 -0.07921 -0.00754 0.04079 5 -0.11412 -0.04246 0.00588 0.04754 0.05079 0.12246 0.17079 0.21246 There are significant differences between nozzle types 1 and 3, 1 and 4, 2 and 4, 3 and 5, and 4 and 5. c) The residual analysis shows that there is some inequality of variance. The normal probability plot is acceptable. Residuals Versus VELOCITY Residuals Versus NOZZLE (response is SHAPE) (response is SHAPE) 0.1 0.1 Residual Residual 0.0 0.0 -0.1 -0.1 10 20 30 1 2 3 4 5 VELOCITY NOZZLE
Residuals Versus theFitted Values (response is SHAPE) 0.1 Residual 0.0 -0.1 0.7 0.8 0.9 1.0 Fitted Value Normal Probability Plot of the Residuals (response is SHAPE) 2 1 Normal Score 0 -1 -2 -0.1 0.0 0.1 Residual Supplemental Exercises 13-31. a)Analysis of Variance for RESISTANCE Source DF SS MS F P ALLOY 2 10941.8 5470.9 76.09 0.000 Error 27 1941.4 71.9 Total 29 12883.2 Reject H0, the type of alloy has a significant effect on mean contact resistance. b) Fisher's pairwise comparisons Family error rate = 0.119 Individual error rate = 0.0500 Critical value = 2.052 Intervals for (column level mean) - (row level mean) 1 2 2 -13.58 1.98 3 -50.88 -45.08 -35.32 -29.52 There are differences in the mean resistance for alloy types 1 and 3, and 2 and 3. c) 99% confidence interval on the mean contact resistance for alloy 3
MSE MSE y3 − t 0.005,271 ≤ µ i ≤ y3 + t 0.005, 27 n n 71.9 71.9 140.4 − 2.771 ≤ µ 3 ≤ 140.4 − 2.771 10 10 132.97 ≤ µ1 ≤ 147.83 d) Variability of the residuals increases with the response. The normal probability plot has some curvature in the tails, indicating a problem with the normality assumption. A transformation of the response should be conducted. Residuals Versus ALLOY Residuals Versus the Fitted Values (response is RESISTAN)) (response is RESISTAN) 30 30 20 20 10 10 Residual Residual 0 0 -10 -10 -20 -20 1 2 3 100 110 120 130 140 ALLOY Fitted Value Normal Probability Plot of the Residuals (response is RESISTAN) 2 1 Normal Score 0 -1 -2 -20 -10 0 10 20 30 Residual 13-35. a)Analysis of Variance for VOLUME Source DF SS MS F P TEMPERATURE 2 16480 8240 7.84 0.007 Error 12 12610 1051 Total 14 29090 Reject H0. b) P-value = 0.007 c) Fisher's pairwise comparisons Family error rate = 0.116 Individual error rate = 0.0500 Critical value = 2.179 Intervals for (column level mean) - (row level mean) 70 75 75 -16.7 72.7 80 35.3 7.3 124.7 96.7
There are significantdifferences in the mean volume for temperature levels 70 and 80, and 75 and 80. The highest temperature (80%) results in the smallest mean volume. d)There are some relatively small differences in the variability at the different levels of temperature. The variability decreases with the fitted values. There is an unusual observation on the normal probability plot. Residuals Versus TEMPERAT Residuals Versus the Fitted Values (response is VOLUME) (response is VOLUME) 50 50 0 0 Residual Residual -50 -50 70 75 80 1170 1180 1190 1200 1210 1220 1230 1240 1250 TEMPERAT Fitted Value 13-37. a) Analysis of Variance for PCTERROR Source DF SS MS F P ALGORITH 5 2825746 565149 6.23 0.000 PROJECT 7 2710323 387189 4.27 0.002 Error 35 3175290 90723 Total 47 8711358 Reject H0 , the algorithm is significant. b) The residuals look acceptable, except there is one unusual point. Residuals Versus PROJECT Residuals Versus ALGORITH (response is PCTERROR) (response is PCTERROR) 1000 1000 500 500 Residual Residual 0 0 -500 -500 1 2 3 4 5 6 7 8 1 2 3 4 5 6 PROJECT ALGORITH Residuals Versus the Fitted Values (response is PCTERROR) 1000 500 Residual 0 -500 0 500 1000 Fitted Value
Normal Probability Plotof the Residuals (response is PCTERROR) 2 1 Normal Score 0 -1 -2 -500 0 500 1000 Residual c) The best choice is algorithm 5 because it has the smallest mean and a low variablity. 2 13-39 a) λ = 1 + 4 ( 2 σ ) = 3 2 σ From Chart VIII with numerator degrees of freedom = a - 1 = 4, denominator degrees of freedom = a(n - 1) = 15, β = 0.15, and the power = 1 - β = 0.85. b) n λ a(n - 1) β Power = 1 - β 5 3.317 20 0.10 0.90 The sample size should be approximately n = 5
Chapter 14 SelectedProblem Solutions Section 14-3 14-1. a) Analysis of Variance for life Source DF SS MS F P material 2 10683.7 5341.9 7.91 0.002 temperat 2 39118.7 19559.4 28.97 0.000 materialtemperat 4 9613.8 2403.4 3.56 0.019 Error 27 18230.7 675.2 Total 35 77647.0 Main factors and interaction are all significant. b)The mean life for material 2 is the highest at temperature level 1, in the middle at temperature level 2 and the lowest at temperature level 3. This shows that there is an interaction. Interaction Plot - Means for life material 1 150 2 3 1 2 3 Mean 100 50 1 2 3 temperat c) There appears to be slightly more variability at temperature 1 and material 1. The normal probability plot shows that the assumption of normality is reasonable. Normal Probability Plot of the Residuals (response is life) 2 1 Normal Score 0 -1 -2 -50 0 50 Residual
Residuals Versus temperat Residuals Versus material (response is life) (response is life) 50 50 0 Residual 0 Residual -50 -50 1 2 3 1 2 3 temperat material 14-3 a) H 0 : τ1 = τ 2 = 0 H 1 : at least one τ i ≠ 0 b) Analysis of Variance for current Source DF SS MS F P glasstyp 1 14450.0 14450.0 273.79 0.000 phostype 2 933.3 466.7 8.84 0.004 glasstypphostype 2 133.3 66.7 1.26 0.318 Error 12 633.3 52.8 Total 17 16150.0 Main effects are significant, the interaction is not significant. Glass type 1 and phosphor type 2 lead to the high mean current (brightness). c) There appears to be slightly more variability at phosphor type 2 and glass type 2. The normal plot of the residuals shows that the assumption of normality is reasonable. Residuals Versus phostype Residuals Versus glasstyp (response is current) (response is current) 15 15 10 10 5 5 Residual Residual 0 0 -5 -5 -10 -10 1 2 3 1.0 1.5 2.0 phostype glasstyp Residuals Versus the Fitted Values (response is current) 15 10 5 Residual 0 -5 -10 220 230 240 250 260 270 280 290 300 Fitted Value
14-7 The ratio Normal Probability Plot of the Residuals (response is current) 2 1 Normal Score 0 -1 -2 -10 -5 0 5 10 15 Residual y⋅i⋅ − y⋅ j⋅ − ( µ i − µ j ) T= has a t distribution with ab(n-1) degrees of freedom 2 MS E / n Therefore, the (1-α)% confidence interval on the difference in two treatment means is 2MSE 2MSE y⋅i⋅ − y⋅ j⋅ − t a / 2,ab(n−1) ≤ µi − µ j ≤ y⋅i⋅ − y⋅ j⋅ + t a / 2,ab( n−1) n n For exercise 14-6, the mean warping at 80% copper concentration is 21.0 and the mean warping at 60% copper concentration is 18.88 a=4, b=4, n=2 and MSE=6.78. The degrees of freedom are (4)(4)(1)=16 2 6.78 2 6.78 (21.0 − 18.88) − 2.120 ≤ µ 3 − µ 2 ≤ (21.0 − 18.88) + 2.120 2 2 − 3.40 ≤ µ3 − µ 2 ≤ 7.64 Therefore, there is no significant differences between the mean warping values at 80% and 60% copper concentration. Section 14-4 14-11 Parts a. and b. Analysis of Variance for strength Source DF SS MS F P hardwood 2 8.3750 4.1875 7.64 0.003 cookingtime 1 17.3611 17.3611 31.66 0.000 freeness 2 21.8517 10.9258 19.92 0.000 hardwoodcookingtime 2 3.2039 1.6019 2.92 0.075 hardwoodfreeness 4 6.5133 1.6283 2.97 0.042 cookingtimefreeness 2 1.0506 0.5253 0.96 0.399 Error 22 12.0644 0.5484 Total 35 70.4200 All main factors are significant. The interaction of hardwood freeness is also significant. c) The residual plots show no serious problems with normality or equality of variance
Residuals Versus freeness Residuals Versus cookingt (response is strength) (response is strength) Residual 1 1 Residual 0 0 -1 -1 400 450 500 550 600 650 1.5 1.6 1.7 1.8 1.9 2.0 freeness cookingt Residuals Versus hardwood Residuals Versus the Fitted Values (response is strength) (response is strength) 1 1 Residual 0 Residual 0 -1 -1 10 15 20 96 97 98 99 100 101 hardwood Fitted Value Normal Probability Plot of the Residuals (response is strength) 2 1 Normal Score 0 -1 -2 -1 0 1 Residual Section 14-5 14-13 a) Analysis of Variance for life (coded units) Source DF SS MS F P speed 1 1332 1332 0.49 0.502 hardness 1 28392 28392 10.42 0.010 angle 1 20592 20592 7.56 0.023 speedhardness 1 506 506 0.19 0.677 speedangle 1 56882 56882 20.87 0.000 hardnessangle 1 2352 2352 0.86 0.377 Error 9 24530 2726 Total 15 134588 b) Estimated Effects and Coefficients for life (coded units)
Term Effect Coef SE Coef T P Constant 413.13 12.41 33.30 0.000 speed 18.25 9.12 12.41 0.74 0.483 hardness 84.25 42.12 12.41 3.40 0.009 angle 71.75 35.87 12.41 2.89 0.020 speedhardness -11.25 -5.63 12.41 -0.45 0.662 speedangle -119.25 -59.62 12.41 -4.81 0.001 hardnessangle -24.25 -12.12 12.41 -0.98 0.357 speedhardnessangle -34.75 -17.37 12.41 -1.40 0.199 ˆ y = 413.125 + 9.125x1 + 45.12x2 + 35.87x3 −59.62x13 c) Analysis of the residuals shows that all assumptions are reasonable. Normal Probability Plot of the Residuals (response is life) 2 1 Normal Score 0 -1 -2 -50 0 50 Residual Residuals Versus angle Residuals Versus hardness (response is life) (response is life) 50 50 Residual Residual 0 0 -50 -50 -1 0 1 -1 0 1 angle hardness Residuals Versus speed Residuals Versus the Fitted Values (response is life) (response is life) 50 50 Residual Residual 0 0 -50 -50 -1 0 1 250 350 450 550 speed Fitted Value
14-19.a) Factors A, B, C, and the interaction AB appear to be significant from the normal probability plot of the effects. Normal Probability Plot of the Effects (response is yield, Alpha = .10) A: factor_A 2 B B: factor_B C: factor_C A D: factor_D C E: factor_E AB 1 Normal Score 0 -1 -2 0 10 20 30 Effect b) Analysis of Variance for yield (coded units) Term Effect Coef StDev Coef T P Constant 30.5312 0.2786 109.57 0.000 factor_A 11.8125 5.9063 0.2786 21.20 0.000 factor_B 9.6875 4.8437 0.2786 17.38 0.000 factor_D -0.8125 -0.4063 0.2786 -1.46 0.164 factor_E 0.4375 0.2187 0.2786 0.79 0.444 factor_Afactor_B 7.9375 3.9687 0.2786 14.24 0.000 factor_Afactor_C 0.4375 0.2187 0.2786 0.79 0.444 factor_Afactor_D -0.0625 -0.0313 0.2786 -0.11 0.912 factor_Afactor_E 0.9375 0.4687 0.2786 1.68 0.112 factor_Bfactor_C 0.0625 0.0313 0.2786 0.11 0.912 factor_Bfactor_D -0.6875 -0.3437 0.2786 -1.23 0.235 factor_Bfactor_E 0.5625 0.2813 0.2786 1.01 0.328 factor_Cfactor_D 0.8125 0.4062 0.2786 1.46 0.164 factor_Cfactor_E 0.3125 0.1563 0.2786 0.56 0.583 factor_Dfactor_E -1.1875 -0.5938 0.2786 -2.13 0.049 Analysis of Variance for yield Source DF Seq SS Adj SS Adj MS F P Main Effects 5 11087.9 11087.9 2217.58 892.61 0.000 2-Way Interactions 10 536.3 536.3 53.63 21.59 0.000 Residual Error 16 39.7 39.7 2.48 Total 31 11664.0 The analysis confirms our findings from part a) c) The normal probability plot of the residuals is satisfactory. However their variance appears to increase as the fitted value increases.
Normal Probability .999 .99 Pr .95 ob .80 abi .50 lity .20 .05 .01 .001 -3 -2 -1 0 1 2 3 RESI1 Average: 0.0000000 Anderson-Darling Normality Test StDev: 1.59479 A-Squared: 0.387 N: 32 P-Value: 0.368 Residuals Versus the Fitted Values (response is yield) 2 Standardized Residual 1 0 -1 -2 0 10 20 30 40 50 60 Fitted Value . d) All plots support the constant variance assumption , although there is a very slight indication that variability is greater at the high level of factor B. Residuals Versus A Residuals Versus B (response is yield) (response is yield) 2 2 Standardized Residual Standardized Residual 1 1 0 0 -1 -1 -2 -2 -1 0 1 -1 0 1 A B
Residuals Versus C Residuals Versus D (response is yield) (response is yield) 2 2 Standardized Residual Standardized Residual 1 1 0 0 -1 -1 -2 -2 -1 0 1 -1 0 1 C D Residuals Versus E (response is yield) 2 Standardized Residual 1 0 -1 -2 -1 0 1 E e) The AB interaction appears to be significant. The interaction plot from MINITAB indicates that a high level of A and of B increases the mean yield, while low levels of both factors would lead to a reduction in the mean yield. Interaction P lot for yield 55 A high 45 35 A low M ean 25 15 -1 1 B f.) To increase yield and therefor optimize the process, we would want to set A, B, and C at their high levels. g) It is evident from the cube plot that we should run the process with all factors set at their high level.
Cube Plot -Means for yield 42.50, 5 62.25,5 32.75,5 52.50,5 1 B 16.00,3 20.75,2 1 C 7.25,2 10.25,3 -1 -1 -1 1 A 14-21 Normal Probability Plot for the Main Effects ML Estimates 99 95 90 A 80 AB 70 Percent 60 50 40 30 20 10 5 B 1 -50 0 50 Data b) Based on the normal probability plot of the effects, factors A, B and AB are significant. The model would include these three factors. ˆ c) The estimated model is: y = 400 + 40.124 x1 − 32.75 x 2 + 26.625 x12
Section 14-6 14-25 Modelwith four blocks BLOCK A B C D var_1 1 -1 -1 -1 -1 190 1 1 -1 1 -1 181 1 -1 1 -1 1 187 1 1 1 1 1 180 2 1 -1 -1 -1 174 2 -1 -1 1 -1 177 2 1 1 -1 1 185 2 -1 1 1 1 187 3 -1 1 -1 -1 181 3 1 1 1 -1 173 3 -1 -1 -1 1 198 3 1 -1 1 1 179 4 1 1 -1 -1 183 4 -1 1 1 -1 188 4 1 -1 -1 1 172 4 -1 -1 1 1 199 Term Effect Coef Constant 183.375 Block -1.625 factor_A -10.000 -5.000 factor_B -0.750 -0.375 factor_C -0.750 -0.375 factor_D 5.000 2.500 factor_Afactor_B 4.500 2.250 factor_Afactor_C 0.500 0.250 factor_Afactor_D -3.750 -1.875 factor_Bfactor_C -1.250 -0.625 factor_Bfactor_D -1.500 -0.750 factor_Cfactor_D 1.500 0.750 factor_Afactor_Bfactor_C -6.000 -3.000 factor_Afactor_Bfactor_D 4.750 2.375 factor_Afactor_Cfactor_D -0.250 -0.125 factor_Bfactor_Cfactor_D -2.000 -1.000 Term Effect Coef StDev Coef T P Constant 183.375 1.607 114.14 0.000 Block -1.625 1.607 -1.01 0.336 factor_A -10.000 -5.000 1.607 -3.11 0.011 factor_B -0.750 -0.375 1.607 -0.23 0.820 factor_C -0.750 -0.375 1.607 -0.23 0.820 factor_D 5.000 2.500 1.607 1.56 0.151 Analysis of Variance for var_1 Source DF Seq SS Adj SS Adj MS F P Blocks 1 42.25 42.25 42.25 1.02 0.336 Main Effects 4 504.50 504.50 126.13 3.05 0.069 Residual Error 10 413.00 413.00 41.30 Total 15 959.75 Factor A is the only significant factor. 14-29 a) Estimated Effects and Coefficients for y Term Effect Coef StDev Coef T P Constant 56.37 2.633 21.41 0.000 Block 1 15.63 4.560 3.43 0.014 2 -3.38 4.560 -0.74 0.487
3 -10.88 4.560 -2.38 0.054 A -45.25 -22.62 2.633 -8.59 0.000 B -1.50 -0.75 2.633 -0.28 0.785 C 14.50 7.25 2.633 2.75 0.033 AB 19.00 9.50 2.633 3.61 0.011 AC -14.50 -7.25 2.633 -2.75 0.033 BC -9.25 -4.63 2.633 -1.76 0.130 Analysis of Variance for y Source DF Seq SS Adj SS Adj MS F P Blocks 3 1502.8 1502.8 500.9 4.52 0.055 Main Effects 3 9040.2 9040.2 3013.4 27.17 0.001 2-Way Interactions 3 2627.2 2627.2 875.7 7.90 0.017 Residual Error 6 665.5 665.5 110.9 Total 15 13835.7 Factors A, C, AB, and AC are significant. b) Analysis of the residuals shows that the model is adequate. There is more variability on the response associated with the low setting of factor C, but that is the only problem. Residuals Versus A (response is y) Residuals Versus B (response is y) 10 10 Residual Residual 0 0 -10 -10 -1 0 1 -1 0 1 B A Residuals Versus C (response is y) 10 Residual 0 -10 -1 0 1 C Residuals Versus the Fitted Values Normal Probability Plot of the Residuals (response is y) (response is y) 10 10 Residual Residual 0 0 -10 -10 10 20 30 40 50 60 70 80 90 100 110 -2 -1 0 1 2 Fitted Value Normal Score
c.) Some of the information from the experiment is lost because the design is run in 4 blocks. This causes us to lose information on the ABC interaction even though we have replicated the experiment twice. If it is possible to run the experiment in only 2 blocks, there would be information on all interactions. d) To have data on all interactions, we could run the experiment so that each replicate is a block (therefore only 2 blocks). Section 14-7 14-31 a) Factors A, B and D are active factors. Normal Probability Plot of the Effects (response is color, Alpha = .10) D BC 1 CE AB Normal Score 0 A C -1 E AE B 0 2 4 Effect b) There are no serious problems with the residual plots. The normal probability plot has a little bit of curvature at the low end and there is a little more variability at the lower and higher ends of the fitted values. Normal Probability Plot of the Residuals (response is var_1) Residuals Versus the Fitted Values (response is var_1) 2 1.5 1 1.0 Normal Score 0.5 0 0.0 Residual -0.5 -1 -1.0 -1.5 -2 -2.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 Residual -2.5 -2 -1 0 1 2 3 4 5 6 7 Fitted Value 3 c) Part a. indicates that only A,B, and D are important. In these factors only, the design is a 2 with two replicates. Estimated Effects and Coefficients for var_1 Term Effect Coef StDev Coef T P Constant 2.7700 0.2762 10.03 0.000 factor_A 1.4350 0.7175 0.2762 2.60 0.032
factor_B -1.4650 -0.7325 0.2762 -2.65 0.029 factor_D 4.5450 2.2725 0.2762 8.23 0.000 factor_Afactor_B 1.1500 0.5750 0.2762 2.08 0.071 factor_Afactor_D -1.2300 -0.6150 0.2762 -2.23 0.057 factor_Bfactor_D 0.1200 0.0600 0.2762 0.22 0.833 factor_Afactor_Bfactor_D -0.3650 -0.1825 0.2762 -0.66 0.527 Analysis of Variance for var_1 Source DF Seq SS Adj SS Adj MS F P Main Effects 3 99.450 99.4499 33.1500 27.15 0.000 2-Way Interactions 3 11.399 11.3992 3.7997 3.11 0.088 3-Way Interactions 1 0.533 0.5329 0.5329 0.44 0.527 Residual Error 8 9.767 9.7668 1.2208 Pure Error 8 9.767 9.7668 1.2208 Total 15 121.149 Factors A, B, D, AB and AD are significant. Normal Probability Plot of the Residuals Residuals Versus the Fitted Values (response is var_1) (response is var_1) 2 1 1 Normal Score Residual 0 0 -1 -1 -2 -3 -2 -1 0 1 2 3 4 5 6 -1 0 1 Fitted Value Residual The normal probability plot and the plot of the residuals versus fitted values are satisfactory. 14-35 Since factors A, B, C, and E form a word in the complete defining relation, it can be verified that the resulting design is two replicates of a 24-1 fractional factorial. This is different than the design that results when C and E are dropped from the 26-2 in Table 14-28 which results in a full factorial because, the factors ABDF do not form a word in the complete defining relation 14-37 Generators D=AB, E=AC for 25-2, Resolution III A B C D E var_1 -1 -1 -1 1 1 1900 1 -1 -1 -1 -1 900 -1 1 -1 -1 1 3500 1 1 -1 1 -1 6100 -1 -1 1 1 -1 800 1 -1 1 -1 1 1200 -1 1 1 -1 -1 3000 1 1 1 1 1 6800
Normal Probability Plotof the Standardized Effects (response is var_1, Alpha = .10) factor_B 1 factor_D Normal Score 0 factor_A factor_E -1 0 10 20 Standardized Effect Estimated Effects and Coefficients for var_1 (coded units) Term Effect Coef SE Coef T P Constant 3025.00 90.14 33.56 0.001 factor_A 1450.00 725.00 90.14 8.04 0.015 factor_B 3650.00 1825.00 90.14 20.25 0.002 factor_C -150.00 -75.00 90.14 -0.83 0.493 factor_D 1750.00 875.00 90.14 9.71 0.010 factor_E 650.00 325.00 90.14 3.61 0.069 Analysis of Variance for var_1 (coded units) Source DF Seq SS Adj SS Adj MS F P Main Effects 5 37865000 37865000 7573000 116.51 0.009 Residual Error 2 130000 130000 65000 Total 7 37995000 Factors A, B and D are significant. Supplemental Exercises 14-41 a Estimated Effects and Coefficients for var_1 (coded units) Term Effect Coef SE Coef T P Constant 191.563 1.158 165.49 0.000 factor_A (PH) 5.875 2.937 1.158 2.54 0.026 factor_B (CC) -0.125 -0.062 1.158 -0.05 0.958 factor_Afactor_B 11.625 5.812 1.158 5.02 0.000 Analysis of Variance for var_1 (coded units) Source DF Seq SS Adj SS Adj MS F P Main Effects 2 138.125 138.125 69.06 3.22 0.076 2-Way Interactions 1 540.562 540.562 540.56 25.22 0.000 Residual Error 12 257.250 257.250 21.44 Pure Error 12 257.250 257.250 21.44 Total 15 935.938 The main effect of pH and the interaction of pH and Catalyst Concentration (CC) are significant at the 0.05 level of significance. The model used is viscosity = 191.563 + 2.937x1 − 0.062x2 + 5.812x12
b.) The interactionplot shows that there is a strong interaction. When Factor A is at its low level, the mean response is large at the low level of B and is small at the high level of B. However, when A is at its high level, the results are opposite. Interaction Plot (data m eans) for var_1 200 A high 195 Mean 190 A low 185 -1 1 factor_B c.) The plots of the residuals show that the equality of variance assumption is reasonable. However, there is a large gap in the middle of the normal probability plot. Sometimes, this can indicate that there is another variable that has an effect on the response but which is not included in the experiment. For example, in this experiment, note that the replicates in each cell have two pairs of values that are very similar, but there is a rather large difference in the mean values of the two pairs. (Cell 1 has 189 and 192 as one pair and 198 and 199 as the other.) Residuals Versus factor_B (response is var_1) Resid uals Versus factor_A (res ponse is var_1) 5 5 Residual Residual 0 0 -5 -5 -1 0 1 -1 0 1 factor_A factor_B R esid u als Versu s th e Fitted Valu es (response is var_1) N o r m a l P r o b a b i l it y P l o t o f th e R e s id u a l s 5 ( r e s p o n s e is v a r _ 1 ) 2 Residual 1 0 Normal Score 0 -1 -5 -2 185 190 195 20 0 -5 0 5 Fitte d V a lue R e s id u a l 14-47 a) Term Effect V -15.75
F 8.75 P 10.75 G -25.00 VF 3.00 VP -8.00 VG -2.75 FP -6.00 FG 3.75 PG -19.25 VFP -1.25 VFG 0.50 VPG -1.50 FPG -12.50 VFPG -4.25 b) Normal Probability Plot of the Effects (response is Roughnes, Alpha = .10) 1 Normal Score 0 V -1 PG G -20 -10 0 10 Effect According to the probability plot, factors V, P, and G and, PG are possibly significant. Estimated Effects and Coefficients for roughnes (coded units) Term Effect Coef SE Coef T P Constant 102.75 2.986 34.41 0.000 V -15.75 -7.87 2.986 -2.64 0.046 F 8.75 4.37 2.986 1.46 0.203 P 10.75 5.37 2.986 1.80 0.132 G -25.00 -12.50 2.986 -4.19 0.009 VF 3.00 1.50 2.986 0.50 0.637 VP -8.00 -4.00 2.986 -1.34 0.238 VG -2.75 -1.38 2.986 -0.46 0.665 FP -6.00 -3.00 2.986 -1.00 0.361 FG 3.75 1.88 2.986 0.63 0.558 PG -19.25 -9.63 2.986 -3.22 0.023 Analysis of Variance for roughnes (coded units) Analysis of Variance for Roughnes (coded units) Source DF Seq SS Adj SS Adj MS F P Main Effects 4 4260.7 4260.7 1065.2 7.46 0.024
2-Way Interactions 6 2004.7 2004.7 334.1 2.34 0.184 Residual Error 5 713.5 713.5 142.7 Total 15 6979.0 y = 102.75 − 7.87 x1 + 5.37 x3 − 12.50 x 4 − 9.63 x34 ˆ c) From the analysis, we see that water jet pressure (P), abrasive grain size (G), and jet traverse speed (V) are significant along with the interaction of water jet pressure and abrasive grain size d) The residual plots appear to indicate the assumption of constant variance may not be met. The assumption of normality appears reasonable. 14-49 The design uses G=VPF as the generator. Alias Structure Normal Probability Plot of the Residuals (response is Roughnes) Residuals Versus the Fitted Values (response is Roughnes) 2 10 1 Normal Score 0 Residual -1 0 -2 -10 0 10 Residual -10 65 75 85 95 105 115 125 135 145 Fitted Value Residuals Versus V (response is Roughnes) 10 Residuals Versus F (response is Roughnes) 10 Residual 0 Residual 0 -10 -1 0 1 -10 V -1 0 1 F I + VPFG Residuals Versus P Residuals Versus G (response is Roughnes) (response is Roughnes) 10 10 Residual Residual 0 0 -10 -10 -1 0 1 -1 0 1 P G V + PFG P + VFG F + VPG G + VPF
VP + FG VF + PG VG + PF Estimated Effects and Coefficients for C9 (coded units) Term Effect Coef SE Coef T P Constant 102.63 6.365 16.12 0.004 V -14.75 -7.37 6.365 -1.16 0.366 P -28.25 -14.12 6.365 -2.22 0.157 F -1.25 -0.62 6.365 -0.10 0.931 G -14.75 -7.38 6.365 -1.16 0.366 PG 17.75 8.88 6.365 1.39 0.298 Analysis of Variance for C9 (coded units) Source DF Seq SS Adj SS Adj MS F P Main Effects 4 2469.5 2469.5 617.4 1.90 0.373 2-Way Interactions 1 630.1 630.1 630.1 1.94 0.298 Residual Error 2 648.3 648.3 324.1 Total 7 3747.9 The results do not show any significant factors. A lot of the information is lost due to the half- fraction of the design. 14-51 Design Generators: D = AB E = AC Alias Structure I + ABD + ACE + BCDE A + BD + CE + ABCDE B + AD + CDE + ABCE C + AE + BDE + ABCD D + AB + BCE + ACDE E + AC + BCD + ABDE BC + DE + ABE + ACD BE + CD + ABC + ADE Design StdOrder A B C D E 1 -1 -1 -1 1 1 2 1 -1 -1 -1 -1 3 -1 1 -1 -1 1 4 1 1 -1 1 -1 5 -1 -1 1 1 -1 6 1 -1 1 -1 1 7 -1 1 1 -1 -1 8 1 1 1 1 1
Chapter 15 SelectedProblem Solutions Section 15-2 15-1. 1. The parameter of interest is median of pH. ~ 2. H 0 : µ = 7.0 ~ 3 H : µ ≠ 7.0 1 4. α=0.05 5. The test statistic is the observed number of plus differences or r+ = 8. 6. We reject H0 if the P-value corresponding to r+ = 8 is less than or equal to α=0.05. 7. Using the binomial distribution with n=10 and p=0.5, P-value = 2P(R≥8|p=0.5)=0.109 8. Conclusion: we cannot reject H0. There is not enough evidence to reject the manufacturer’s claim that the median of the pH is 7.0 15-5 a. 1. The parameter of interest is the median compressive strength ~ 2. H 0 : µ = 2250 ~ 3. H : µ > 2250 1 4. α=0.05 5. The test statistic is the observed number of plus differences or r+ = 7. 6. We reject H0 if the P-value corresponding to r+ = 7 is less than or equal to α=0.05. 7. Using the binomial distribution with n=12 and p=0.5, P-value = P(R≥7|p=0.5)=.3872 8.Conclusion: cannot reject H0. The median compressive strength is not more than 2250. b. 1. The parameter of interest is the median compressive strength ~ 2. H 0 : µ = 2250 ~ 3. H : µ > 2250 1 4. α=0.05 5. Test statistic is z = r + − 0.5n 0 0.5 n 6. We reject H0 if the |Z0| > Z0.025 = 1.96 7. Computation: z = 7 − 0.5(12) = 0.577 0 0.5 12 8. Conclusion: cannot reject H0. The median compressive strength is not more than 2250. The P-value = 1-Φ(0.58) = 1-.7190 = 0.281 15-7. 1. The parameter of interest is the median titanium content ~ 2. H 0 : µ = 8.5 3. H : µ ~ ≠ 8.5 1 4. α=0.05 r + − 0.5n 5. Test statistic is z0 = 0.5 n 6. We reject H0 if the |Z0| > Z0.025 = 1.96 7. Computation: z = 7 − 0.5(20) = −1.34 0 0.5 20 8. Conclusion: cannot reject H0. The median titanium content is 8.5. The P-value = 2P(|Z|>1.34) = 0.1802. 15-9. 1. The parameters of interest are the median hardness readings for the two tips ~ 2. H 0 : µ D = 0 ~ 3. H : µ ≠ 0 1 D 4. α=0.05
5. The teststatistic is r = min( r+ , r-). 6. Since α=0.05 and n=8, Appendix,= Table VII gives the critical value of r0.05 =2. We will reject H0 in favor of H1 if r ≤ 1. 7. r+ = 6 and r - = 2 and so r=min(6,2) = 2 8. Conclusion: cannot reject H0. There is not significant difference in the tips. 15-11. 1. The parameters of interest are the median drying times for the two formulations. ~ 2. H 0 : µ D = 0 3. H : µ ~ ≠0 1 D 4. α=0.05 r + − 0.5n 5. Test statistic is z0 = 0.5 n 6. We reject H0 if the |Z0| > Z0.025 = 1.96 7. Computation: z = 15 − 0.5(20) = 2.24 0 0.5 20 8. Conclusion: reject H0. There is a difference in the median drying times between the two formulations. The P-value = 2P(|Z|>2.24) = 0.025. 15-17. a) α = P(Z>1.96) = 0.025 b) β = P X = 1 . 96 | µ = 1 = P ( Z < − 1 . 20 ) = 0 . 115 σ / n c) The sign test that rejects if R− ≤ 1 has α = 0.011 based on the binomial distribution. d) β = P(R − > 1 | µ = 1) = 0.1587 . Therefore, R− has a binomial distribution with p=0.1587 and n = 10 when µ = 1. Then β = 0.487. The value of β is greater for the sign test than for the normal test because the Z-test was designed for the normal distribution. Section 15-3 15-21 1. The parameter of interest is the mean titanium content 2. H 0 : µ = 8.5 3. H 1 : µ ≠ 8.5 4. α=0.05 5. The test statistic is w = min( w + , w -). 6. We will reject H0 if w ≤ w0.05 = 52, since α=0.05 and n=20, the value in Appendix A, Table VIII. 7. w+ = 71 and w - = 102 and so w=min(71,102) = 71 8. Conclusion: Since 71>52, we cannot reject H0. 15-23 1. The parameter of interest is the mean titanium content 2. H 0 : µ = 2.5 3. H 1 : µ < 2.5 4. α=0.05 5. The test statistic w = min( w + , w -). 6. We will reject H0 if w ≤ w0.05 = 65, since α=0.05 and n=22 the value in Appendix A, Table VIII. 7. w+ = 225 and w - = 8 and so w=min(225, 8) = 8 8.Conclusion: Since 8 < 65, we reject H0. 15-27. 1. The parameters of interest are the mean blood cholesterol levels. 2. H 0 : µ D = 0 3. H 1 : µ D ≠ 0 4. α=0.05 5. The test statistic is w = min( w + , w -).
6. We will reject H0 is w ≤ w0.05 = 25, since α=0.05 and n=15, the value in Appendix A, Table VIII. 7. w+ = 118 and w - = 1 and so w=min(118, 1) = 1 Since 1 < 25 8. Conclusion: Since 1 < 25, we reject H0. Section 15-4 15-31. 1. The parameters of interest are the mean image brightness’. 2. H 0 : µ1 = µ 2 3. H 1 : µ1 > µ 2 4. α=0.025 5. The test statistic is z = W1 − µ w1 0 σ w1 6. We will reject H0 if Z0 > Z0.025 = 1.96 2 7. w1 = 40 , µ w1 =85.5 and σ w1 =128.25 54 − 85 . 5 z0 = = − 2 . 78 11 . 32 Since Z0 < 1.96, cannot reject H0 8. Conclusion: do not reject H0. P-value = 0.9973 15-35. 1. The parameters of interest are the mean etch rates 2. H 0 : µ1 = µ 2 3. H 1 : µ1 ≠ µ 2 4. α=0.025 5. The test statistic is z = W1 − µ w1 0 σ w1 6. We will reject H0 if |Z0| > Z0.025 = 1.96 2 7. w1 = 55 , µ w1 =105 and σ w1 =175 55 − 105 z0 = = − 3 . 77 13 . 23 Since |Z0| < 1.96, reject H0 8. Conclusion: reject H0. P-value = 0.0001 Section 15-5 15-37. Kruskal-Wallis Test on strength mixingte N Median Ave Rank Z 1 4 2945 9.6 0.55 2 4 3075 12.9 2.12 3 4 2942 9.0 0.24 4 4 2650 2.5 -2.91 Overall 16 8.5 H = 10.00 DF = 3 P = 0.019 H = 10.03 DF = 3 P = 0.018 (adjusted for ties) NOTE One or more small samples Reject H0
Supplemental 15-43.1. The parameter of interest is median of surface finish. ~ 2. H 0 : µ = 10.0 ~ 3 H : µ ≠ 10.0 1 4. α=0.05 5. The test statistic is the observed number of plus differences or r+ = 5. 6. We reject H0 if the P-value corresponding to r+ = 5 is less than or equal to α=0.05. 7. Using the binomial distribution with n=10 and p=0.5, P-value = 2P(R≥5|p=0.5)=1.0 8. Conclusion: we cannot reject H0. We cannot reject the claim that the median is 10 µin. 15-45. The parameter of interest is the median fluoride emissions ~ H0 : µ = 6 ~ H :µ <6 1 α=0.05 Using Minitab (Sign Rank Test) Sign test of median = 6.000 versus < 6.000 N Below Equal Above P Median y 15 9 2 4 0.1334 4.000 Do not reject H0 15-47. 1. The parameters of interest are the median impurity levels. ~ 2. H 0 : µ D = 0 ~ 3. H : µ ≠ 0 1 D 4. α=0.01 5. The test statistic is r = min( r+ , r-). 6. Since α=0.01 and n=8, Appendix,= Table VII gives the critical value of r0.01 =0. We will reject H0 in favor of H1 if r ≤ 10. 7. r+ = 1 and r - = 7 and so r=min(1,7) = 1 8. Conclusion: cannot reject H0. There is no significant difference in the impurity levels. 15-49. The parameter of interest is the median fluoride emissions H0 : µ = 6 H1 : µ < 6 α=0.05 Using Minitab Wilcoxon signed-rank t test Test of median = 6.000 versus median < 6.000 N for Wilcoxon Estimated N Test Statistic P Median y 15 13 19.0 0.035 5.000 Reject H0 The Wilcoxon signed-rank test applies to symmetric continuous distributions. The test to applies to the mean of the distribution. 15-51. 1. The parameters of interest are the mean volumes 2. H 0 : µ1 = µ 2 3. H 1 : µ1 ≠ µ 2 4. α=0.01 5. The test statistic is w = ( n1 + n 2 )( n1 + n 2 + 1) − w 2 1 2 6. We will reject H0 if w ≤ w0.01 = 71, since α=0.01 and n1=10 and n2=10, the value in Appendix A, Table IX. 7. w1 = 42 and w2 = 78 and so since 42 is less than 78, we reject H0
8. Conclusion: rejectH0 15-57. Kruskal-Wallis Test on VOLUME TEMPERAT N Median Ave Rank Z 70 5 1245 12.4 2.69 75 5 1220 7.9 -0.06 80 5 1170 3.7 -2.63 Overall 15 8.0 H = 9.46 DF = 2 P = 0.009 H = 9.57 DF = 2 P = 0.008 (adjusted for ties) Reject H0, P-value=0.0009
Chapter 16 SelectedProblem Solutions Section 16-5 16-3 a) X-bar and Range - Initial Study Charting Problem 16-3 X-bar | Range ----- | ----- UCL: + 3.0 sigma = 17.4 | UCL: + 3.0 sigma = 5.792 Centerline = 15.09 | Centerline = 2.25 LCL: - 3.0 sigma = 12.79 | LCL: - 3.0 sigma = 0 | Test Results: X-bar One point more than 3.00 sigmas from center line. Test Failed at points: 4 6 7 10 12 15 16 20 Test Results for R Chart:One point more than 3.00 sigmas from center line. Test Failed at points: 19 Xbar/R Chart for x1-x3 1 20 1 Sample Mean 1 UCL=17.40 15 Mean=15.09 LCL=12.79 1 1 1 10 1 1 Subgroup 0 10 20 6 1 UCL=5.792 Sample Range 5 4 3 2 R=2.25 1 0 LCL=0 . b. Removed points 4, 6, 7, 10, 12, 15, 16, 19, and 20 and revised the control limits The control limits are not as wide after being revised X-bar UCL=17.96, CL=15.78 LCL=13.62 and R UCL = 5.453, R-bar=2.118, LCL=0. The X-bar control moved down. Xbar/R Chart for x1-x3 Revised Control Limits 18 UCL=17.95 Sample Mean 17 16 Mean=15.78 15 14 LCL=13.62 13 Subgroup 0 5 10 6 UCL=5.453 Sample Range 5 4 3 2 R=2.118 1 0 LCL=0
c) X-bar and StDev - Initial Study Charting Problem 16-3 X-bar | StDev ----- | ----- UCL: + 3.0 sigma = 17.42 | UCL: + 3.0 sigma = 3.051 Centerline = 15.09 | Centerline = 1.188 LCL: - 3.0 sigma = 12.77 | LCL: - 3.0 sigma = 0 | Test Results: X-bar One point more than 3.00 sigmas from center line. Test Failed at points: 4 6 7 10 12 15 16 20 Test Results for S Chart:One point more than 3.00 sigmas from center line. Test Failed at points: 19 . Xbar/S Chart for x1-x3 1 20 1 Sample Mean 1 UCL=17.42 15 Mean=15.09 LCL=12.77 1 1 1 10 1 1 Subgroup 0 10 20 1 3 UCL=3.051 Sample StDev 2 S=1.188 1 0 LCL=0 Removed points 4, 6, 7, 10, 12, 15, 16, 19, and 20 and revised the control limits The control limits are not as wide after being revised X-bar UCL=17.95, CL=15.78 LCL=13.62 and S UCL = 2.848, S-bar=1.109, LCL=0. The X-bar control moved down. Xbar/S Chart for x1-x3 Revised Control Limits 18 UCL=17.95 Sample Mean 17 16 Mean=15.78 15 14 LCL=13.62 13 Subgroup 0 5 10 3 UCL=2.848 Sample StDev 2 1 S=1.109 0 LCL=0
7805 1200 16-5. a) x= = 223 r= = 34.286 35 35 x chart UCL = CL + A2 r = 223 + 0.577(34.286) = 242.78 CL = 223 LCL = CL − A2 r = 223 − 0.577(34.286) = 203.22 R chart UCL = D4 r = 2.115(34.286) = 72.51 CL = 34.286 LCL = D3r = 0(34.286) = 0 b) µ = x = 223 ˆ r 34.286 σ = ˆ = = 14.74 d2 2.326 16-7 a) X-bar and Range - Initial Study Charting Problem 16-7 X-bar | Range ----- | ----- UCL: + 3.0 sigma = 0.0634706 | UCL: + 3.0 sigma = 1.95367E-3 Centerline = 0.0629376 | Centerline = 9.24E-4 LCL: - 3.0 sigma = 0.0624046 | LCL: - 3.0 sigma = 0 | out of limits = 5 | out of limits = 2 -------------------------------------------------------------------------------- Chart: Both Normalize: No 25 subgroups, size 5 0 subgroups excluded Estimated Xbar/R Chart for x 0.064 1 1 Sample Mean UCL=0.06347 0.063 Mean=0.06294 LCL=0.06240 1 1 0.062 1 Subgroup 0 5 10 15 20 25 0.003 1 Sample Range 1 0.002 UCL=0.001954 0.001 R=0.000924 0.000 LCL=0
b) Xbar/S Chart for x 0.064 1 1 Sample Mean UCL=0.06346 0.063 Mean=0.06294 LCL=0.06241 1 1 0.062 1 Subgroup 0 5 10 15 20 25 1 0.0010 Sample StDev 1 UCL=7.66E-04 0.0005 S=3.67E-04 0.0000 LCL=0 c) There are several points out of control. The control limits need to be revised. The points are 1, 5, 14,17, 20,21, and 22; or outside the control limits of the R chart: 6 and 15 Section 16-6 16-9. a) Individuals and MR(2) - Initial Study ------------------------------------------------------------------------------ Charting Problem 15-8 Ind.x | MR(2) ----- | ----- UCL: + 3.0 sigma = 60.8887 | UCL: + 3.0 sigma = 9.63382 Centerline = 53.05 | Centerline = 2.94737 LCL: - 3.0 sigma = 45.2113 | LCL: - 3.0 sigma = 0 | out of limits = 0 | out of limits = 0 ------------------------------------------------------------------------------ Chart: Both Normalize: No 20 subgroups, size 1 0 subgroups excluded Estimated process mean = 53.05 process sigma = 2.61292 mean MR = 2.94737
There are nopoints beyond the control limits. The process appears to be in control. I and MR Chart for hardness Individual Value UCL=60.89 60 55 Mean=53.05 50 45 LCL=45.21 Subgroup 0 10 20 10 UCL=9.630 Moving Range 5 R=2.947 0 LCL=0 b) µ = x = 53.05 ˆ mr 2.94737 σ = ˆ = = 2.613 d2 1.128 Section 16-7 r 0.344 16-15. a) Assuming a normal distribution with µ = 0.14.510 and σ = = = 0148 . d 2 2.326 LSL − µ ˆ P(X < LSL ) = P Z < σˆ 14.00 − 14.51 = P Z < 0.148 = P(Z < −3.45) = 1 − P( Z < 3.45) = 1 − 0.99972 = 0.00028
USL − µ ˆ P ( X > USL) = P Z > σˆ 15.00 − 14.51 = P Z > 0.148 = P( Z > 3.31) = 1 − P ( Z < 3.31) = 1 − 0.99953 = 0.00047 Therefore, the proportion nonconforming is given by P(XUSL) =0.00028 + 0.00047 = 0.00075 b) USL − LSL 15.00 − 14.00 PCR = = = 1.13 6(σ ) ˆ 6(0.148) USL − x x − LSL PCRK = min , 3σ ˆ 3σ ˆ 15.00 − 14.51 14.51 − 14.00 = min , 3(0.148) 3(0.148) = min[ .104,1.15] 1 = 1.104 Since PCR exceeds unity, the natural tolerance limits lie inside the specification limits and very few defective units will be produced. PCRK ≅ PCR the process appears to be centered. s 13.58 16-19 a) Assuming a normal distribution with µ = 223 and σ = ˆ = = 14.74 c 4 0.9213 LSL − µ ˆ P(X < LSL ) = P Z < σˆ 170 − 223 = P Z < 14.74 = P(Z < −3.60) = 0.00016
USL − µ ˆ P ( X > USL) = P Z > σˆ 270 − 223 = P Z > 14.75 = P ( Z > 3.18) = 1 − P ( Z < 3.18) = 1 − 0.99926 = 0.00074 Probability of producing a part outside the specification limits is 0.00016+0.00074 = 0.0009 b USL − LSL 270 − 220 PCR = = = 1.13 6(σ ) ˆ 6(14.75) USL − x x − LSL PCRK = min , 3σˆ 3σ ˆ 270 − 223 223 − 170 = min , 3(14.75) 3(14.75) = min[1.06,1.19] = 1.06 Since PCR exceeds unity, the natural tolerance limits lie inside the specification limits and very few defective units will be produced. The estimated proportion nonconforming is given by P(XUSL) =0.00016 + 0.00074=0.0009 16-23. Assuming a normal distribution with µ = 500.6 and σ = 17.17 USL − LSL 525 − 475 PCR = = = 0.49 6(σ ) ˆ 6(17.17) USL − x x − LSL PCRK = min , 3σ ˆ ˆ 3σ 525 − 500.6 500.6 − 475 = min , 3(17.17) 3(17.17) = min[0.474,0.50] = 0.474 Since the process capability ratios are less than unity, the process capability appears to be poor.
Section 16-8 16-25. U Chart for defects 5 1 1 4 3.0SL=3.811 Sample Count 3 2 U=1.942 1 0 -3.0SL=0.07217 0 5 10 15 20 25 Sample Number Samples 5 and 24 have out-of-control points. The limits need to be revised. b) U Chart for defects_ 4 UCL=3.463 3 Sample Count 2 U=1.709 1 0 LCL=0 0 10 20 Sample Number The control limits are calculated without the out-of-control points. There are no points out of control for the revised limits. 16-27. C Chart for defects 1 1 20 3.0SL=19.06 Sample Count 10 C=9.708 0 -3.0SL=0.3609 0 5 10 15 20 25 Sample Number
There are twopoints beyond the control limits. They are samples 5 and 24. The U chart and the C chart both detected out-of-control points at samples 5 and 24. Section 16-9 σˆ 2.4664 16-31. a) σ x = = = 1.103 , µ = 36 n 5 P(30.78 < X < 37.404) 30.78 − 36 X − µ 37.404 − 36 = P 1.103 < σ < ˆx 1.103 = P (−4.73 < Z < 1.27) = P( Z < 1.27) − P( Z < −4.73) = 0.8980 − 0 = 0.8980 The probability that this shift will be detected on the next sample is p = 1−0.8980 = 0.1020. 1 1 b) ARL = = = 9.8 p 0.102 R 6.75 σˆ 3.28 16-33. a) σ = ˆ = = 3.28 σx = = = 1.64 , µ = 13 d 2 2.059 n 4 P (5.795 < X < 15.63) 5.795 − 13 X − µ 15.63 − 13 = P 1.64 < σ < x 1.64 = P (−4.39 < Z < 1.60) = P( Z < 1.60) − P ( Z < −4.39) = 0.9452 − 0 = 0.9452 The probability that this shift will be detected on the next sample is p = 1−0.9452 = 0.0548. 1 1 b) ARL = = = 18.25 p 0.0548 Section 16-10 16-39. a) σ = 0.1695 ˆ b) The process appears to be out of control at the specified target level.
CUSUM Chart fordiameter Upper CUSUM 0.678191 0.5 Cumulative Sum 0.0 -0.5 Lower CUSUM -6.8E-01 0 5 10 15 20 25 Subgroup Number Supplemental 16-43. a) X-bar and Range - Initial Study -------------------------------------------------------------------------------- X-bar | Range ---- | ----- UCL: + 3.0 sigma = 64.0181 | UCL: + 3.0 sigma = 0.0453972 Centerline = 64 | Centerline = 0.01764 LCL: - 3.0 sigma = 63.982 | LCL: - 3.0 sigma = 0 | out of limits = 0 | out of limits = 0 -------------------------------------------------------------------------------- Chart: Both Normalize: No Estimated process mean = 64 process sigma = 0.0104194 mean Range = 0.01764 Xbar/R Chart for diameter 64.02 UCL=64.02 Sample Mean 64.01 64.00 Mean=64.00 63.99 LCL=63.98 63.98 Subgroup 0 5 10 15 20 25 0.05 UCL=0.04438 Sample Range 0.04 0.03 0.02 R=0.01724 0.01 0.00 LCL=0
The process isin control. R 0.01764 b) µ = x = 64 σ = =ˆ = 0.0104 d2 1.693 USL − LSL 64.02 − 63.98 c) PCR = = = 0.641 6σˆ 6(0.0104) The process does not meet the minimum capability level of PCR ≥ 1.33. d) USL − x x − LSL 64.02 − 64 64 − 63.98 PCRk = min , = min 3(0.0104) , 3(0.0104) 3σ ˆ 3σ ˆ = min[0.641,0.641] = 0.641 e) In order to make this process a “six-sigma process”, the variance σ2 would have to be decreased such that x − LSL PCRk = 2.0. The value of the variance is found by solving PCRk = = 2.0 for σ: 3σ 64 − 61 = 2.0 3σ 6σ = 64. − 61 64. − 61 σ = = 0.50 6 Therefore, the process variance would have to be decreased to σ2 = (0.50)2 = 0.025. f) σ x = 0.0104 P(63.98 < X < 64.02) 63.98 − 64.01 X − µ 64.02 − 64.01 = P 0.0104 << σx 0.0104 = P (−2.88 < Z < 0.96) = P( Z < 0.96) − P( Z < −2.88) = 0.8315 − 0.0020 = 0.8295 The probability that this shift will be detected on the next sample is p = 1−0.8295 = 0.1705 1 1 ARL = = = 5.87 p 0.1705 16-45. a) P Chart - Initial Study P Chart ----- UCL: + 3.0 sigma = 0.203867 Centerline = 0.11 LCL: - 3.0 sigma = 0.0161331 out of limits = 0 Estimated mean P = 0.11 sigma = 0.031289
P Chart fordef 0.2 UCL=0.2039 Proportion P=0.11 0.1 LCL=0.01613 0.0 0 10 20 Sample Number There are no points beyond the control limits. The process is in control. b) P Chart - Initial Study Sample Size, n = 200 P Chart ----- UCL: + 3.0 sigma = 0.176374 Centerline = 0.11 LCL: - 3.0 sigma = 0.0436261 out of limits = 1 Estimated mean P = 0.11 sigma = 0.0221246 P Chart for def2 0.19 1 UCL=0.1764 0.14 Proportion P=0.11 0.09 0.04 LCL=0.04363 0 10 20 Sample Number There is one point beyond the upper control limit. The process is out of control. The revised limits are: P Chart - Revised Limits Sample Size, n = 200 P Chart ----- UCL: + 3.0 sigma = 0.171704 Centerline = 0.106316 LCL: - 3.0 sigma = 0.0409279 out of limits = 0 Estimated mean P = 0.106316
sigma = 0.021796 There are no points beyond the control limits. The process is now in control. P Chart for def2 0.19 UCL=0.1717 0.14 Proportion P=0.1063 0.09 0.04 LCL=0.04093 0 10 20 Sample Number c) A larger sample size with the same number of defective items will result in more narrow control limits. The control limits corresponding to the larger sample size are more sensitive. 16-49. ARL = 1/p where p is the probability a point falls outside the control limits. a) µ = µ 0 + σ and n = 1 p = P( X > UCL) + P( X < LCL) 3σ 3σ µ0 + − µ0 − σ µ0 − − µ0 − σ n n = P Z > + P Z < σ/ n σ/ n = P ( Z > 3 − n ) + P ( Z < −3 − n ) = P( Z > 2) + P ( Z < −4) when n = 1 = 1 − P( Z < 2) + [1 − P( Z < 4)] = 1 − 0.97725 + [1 − 1] = 0.02275 Therefore, ARL = 1/p = 1/0.02275 = 43.9. b) µ = µ 0 + 2σ
P( X >UCL) + P( X < LCL) 3σ 3σ µ0 + − µ 0 − 2σ µ0 − − µ 0 − 2σ = P Z > n + P Z < n σ/ n σ/ n = P( Z > 3 − 2 n ) + P( Z < −3 − 2 n ) = P( Z > 1) + P( Z < −5) when n = 1 = 1 − P( Z < 1) + [1 − P( Z < 5)] = 1 − 0.84134 + [1 − 1] = 0.15866 Therefore, ARL = 1/p = 1/0.15866 = 6.30. c) µ = µ 0 + 3σ P( X > UCL) + P( X < LCL) 3σ 3σ µ0 + − µ 0 − 3σ µ0 − − µ 0 − 3σ Z > n + P Z < n =P σ/ n σ/ n = P ( Z > 3 − 3 n ) + P ( Z < −3 − 3 n ) = P( Z > 0) + P( Z < −6) when n = 1 = 1 − P( Z < 0) + [1 − P( Z < 6)] = 1 − 0.50 + [1 − 1] = 0.50 Therefore, ARL = 1/p = 1/0.50 = 2.00. d) The ARL is decreasing as the magnitude of the shift increases from σ to 2σ to 3σ. The ARL will decrease as the magnitude of the shift increases since a larger shift is more likely to be detected earlier than a smaller shift. 16-51. a) X-bar and Range - Initial Study Charting xbar X-bar | Range ----- | ----- UCL: + 3.0 sigma = 140.168 | UCL: + 3.0 sigma = 2.48437 Centerline = 139.49 | Centerline = 1.175 LCL: - 3.0 sigma = 138.812 | LCL: - 3.0 sigma = 0 out of limits = 9 | out of limits = 0 Estimated process mean = 139.49 process sigma = 0.505159 mean Range = 1.175
Problem 16-51 141 140 140.168 X-bar 139.49 139 138.812 138 137 0 4 8 12 16 20 2.5 2.48437 2 1.5 Range 1.175 1 0.5 0 0 0 4 8 12 16 20 subgroup There are points beyond the control limits. The process is out of control. The points are 4, 8, 10, 13, 15, 16, and 19. b) Revised control limits are given in the table below: X-bar and Range - Initial Study Charting Xbar X-bar | Range ----- | ----- UCL: + 3.0 sigma = 140.518 | UCL: + 3.0 sigma = 2.60229 Centerline = 139.808 | Centerline = 1.23077 LCL: - 3.0 sigma = 139.098 | LCL: - 3.0 sigma = 0 out of limits = 0 | out of limits = 0 Estimated process mean = 139.808 process sigma = 0.529136 mean Range = 1.23077 z There are no points beyond the control limits the process is now in control. R 123077 . The process standard deviation estimate is given by σ = = = 0.529 d2 2.326 USL − LSL 142 − 138 c) PCR = = = 126 . 6σ 6(0.529) USL − x x − LSL PCR k = min , 3σ 3σ 142 − 139.808 139.808 − 138 = min , 3(0.529) 3(0.529) = min[138,114] . . = 114 . Since PCR exceeds unity, the natural tolerance limits lie inside the specification limits and very few defective units will be produced. PCR is slightly larger than PCRk indicating that the process is somewhat off center. d) In order to make this process a “six-sigma process”, the variance σ2 would have to be decreased such that x − LSL PCRk = 2.0. The value of the variance is found by solving PCRk = = 2.0 for σ: 3σ
139.808 − 138 = 2.0 3σ 6σ = 139.808 − 138 139.808 − 138 σ= 6 σ = 0.3013 Therefore, the process variance would have to be decreased to σ2 = (0.3013)2 = 0.091. e) σ x = 0.529 p = P(139.098 < X < 140.518 | µ = 139.7) 139.098 − 139.7 X − µ 140.518 − 139.7 = P << 0.529 σx 0.529 = P (−1.14 < Z < 1.55) = P( Z < 1.55) − P( Z < −1.14) = P ( Z < 1.55) − [1 − P( Z < 1.14)] = 0.93943 − [1 − 0.87285] = 0.8123 The probability that this shift will be detected on the next sample is 1−p = 1−0.8123 = 0.1877. 1 1 ARL = = = 5.33 1 − p 01877 .
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12507 | https://www.youtube.com/watch?v=1MeLdnOllBk | Using Desmos to Explore Transformations of Absolute Value
Nathan Frey
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Posted: 1 Jun 2021
In this Algebra II video I go over how to use Desmos, the free graphing app that you can use on your browser or cell phone, to graph the parent function Absolute Value along with transformations of the parent function. I show how to use sliders in Desmos to explore the different parts of the h,k formula y = a|x - h| + k
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Transcript:
all right in this video we're going to use desmos in order to show transformations of the absolute value function so the first thing we're going to do is open up desmos and go over here and type in the original parent function which is y equals and if you bring up the little keyboard you can get the absolute value function type in absolute value of x and what i have here in blue is our parent function so you can see that it's a v shape and it's got its vertex here at 0 0. now we're going to do transformations of it so we're going to type in y equals and we're going to type in some variables here so i'm going to type in a absolute value x minus h inside and then plus k on the outside and then i'm going to add sliders you can do this as well so the sliders allow you to experiment to see how these variables would change everything so you can see uh right now let's let's just move this to zero if you want to change these you can just type in a number oops i got so we can type in k equals zero all right so right now i and the green one i have basically the absolute value of x minus one so you can see that if you have minus one inside the absolute value it's going to move it to the right one space and as i slide it oops i was sliding a as i slide h there is absolute value of x minus two it's moved two to the right and absolute value of x minus three has moved three to the right if i make h negative it moves it to the left that's the same as if i would have y equals absolute value of x plus three so that you can see is exactly the same so if i have a plus inside the absolute value it's going to move it to the left and then of course k here is going to move it up or down so it's plus k on the outside so if it is plus uh you know two it's going to move it up two and if it is minus two on the outside it's going to be moving down to the a here you can see is going to make it skinnier it has a vertical stretch if a goes above one it stretches more and more and if we have something between zero and one it gets wider we have a vertical compression and if we go negative the same thing applies if it's between zero and negative one then we have a vertical compression and a reflection down and if it is less than negative one then we have a vertical stretch and reflection so hopefully that helps and you can put all these pieces together and transform your function |
12508 | https://brainly.com/question/30277543 | [FREE] Is it possible to construct a triangle whose sides are 5 cm, 5 cm, and 10 cm? - brainly.com
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Is it possible to construct a triangle whose sides are 5 cm, 5 cm, and 10 cm?
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It is not possible to construct a triangle whose sides are 5cm ,5cm and 10cm , because the sum of two sides is not greater then third side .
For any three sides to form a triangle , it should satisfy the condition that , the sum of any two sides should must be greater than the third side .
We apply this condition on the given sides ,
we get ;
the sides of the triangle are ⇒ 5cm ,5cm and 10cm ;
the sum of sides : 5 + 5 = 10 which is not greater than the third side (10cm) ;
these sides do not satisfy the condition ,
Therefore , the condition to form the triangle is not satisfied , so the triangle cannot be constructed .
Learn more about Triangles here
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It is not possible to construct a triangle with sides of 5 cm, 5 cm, and 10 cm because the sum of the lengths of the two shorter sides equals the length of the longest side, and does not exceed it. The Triangle Inequality Theorem states that the sum of any two sides must be greater than the third side. In this case, 5 + 5 is not greater than 10, thus no triangle can be formed.
Explanation
To determine if we can construct a triangle with sides of 5 cm, 5 cm, and 10 cm, we need to use the Triangle Inequality Theorem. This theorem states that the sum of the lengths of any two sides of a triangle must be greater than the length of the third side.
Let’s analyze the given sides:
Sides are 5 cm, 5 cm, and 10 cm.
Now, we will apply the Triangle Inequality Theorem:
First, check the sum of the first two sides:
5+5=10
Next, check this sum against the third side:
We see that 10 is not greater than 10.
Now, we also need to check the other combinations, but since we have repeating sides (5 cm and 5 cm), the analysis remains the same. We will find that:
5+10>5 is true (15 > 5)
5+10>5 is also true (15 > 5)
However, the crucial check is 5+5>10, which fails (10 is not greater than 10).
Since the sum of the two shorter sides is not greater than the length of the longest side, the given lengths cannot form a triangle. Therefore, it is not possible to construct a triangle with these sides.
Examples & Evidence
For example, if the sides were 3 cm, 4 cm, and 5 cm, then:
3 + 4 = 7, which is greater than 5,
3 + 5 = 8, which is greater than 4,
4 + 5 = 9, which is greater than 3.
This satisfies the Triangle Inequality Theorem, meaning a triangle can be formed with these lengths.
The Triangle Inequality Theorem is a fundamental concept in geometry that states: for any three lengths to form a triangle, the sum of two lengths must always be greater than the remaining length. This theorem can be found in most geometry textbooks and is a basic principle taught in high school mathematics.
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12509 | https://engineering.stackexchange.com/questions/7316/find-acceleration-of-a-buoyancy-force-of-a-balloon-in-u-s-customary-units-1-49 | fluid mechanics - Find Acceleration Of A Buoyancy Force Of A Balloon In U.S. Customary Units (1-49E) - Engineering Stack Exchange
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Find Acceleration Of A Buoyancy Force Of A Balloon In U.S. Customary Units (1-49E)
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The problem in my text (Thermodynamics An Engineering Approach, Cengel & Boles, 2nd Ed.) is stated as follows:
Balloons are often filled with helium gas because it weighs only about one-seventh of what air weighs under identical conditions. The buoyancy force, which can be expressed as F b=ρ a i r g V b a l l o o n F b=ρ a i r g V b a l l o o n, will push the balloon upward. If the balloon has a diameter of 30 f t 30 f t and carries two people, 140 l b m 140 l b m each, determine the acceleration of the balloon when it is first released. Assume the density of air is ρ a i r=0.0724 l b m f t 3 ρ a i r=0.0724 l b m f t 3, and neglect the weight of the ropes and the cage.
Answer: 45.1 f t s 2 45.1 f t s 2
I can easily find a solution in S.I. units. It is the U.S. Customary units that I am having difficulty with.
Given:
r=15 f t m p e o p l e=2⋅140 l b m ρ a i r=0.0724 l b m f t 3 r=15 f t m p e o p l e=2⋅140 l b m ρ a i r=0.0724 l b m f t 3
Let us begin by finding V V and F b F b:
V b a l l o o n=4 3 π r 3=4 3 π(15 f t)3=14137 f t 3 F b=ρ a i r g V b a l l o o n=0.0724 l b m f t 3 32.174 l b m l b f f t s 2⋅32.174 f t s 2⋅14137 f t 3=1023 l b f V b a l l o o n=4 3 π r 3=4 3 π(15 f t)3=14137 f t 3 F b=ρ a i r g V b a l l o o n=0.0724 l b m f t 3 32.174 l b m l b f f t s 2⋅32.174 f t s 2⋅14137 f t 3=1023 l b f
Next let us find all masses:
m p e o p l e=2⋅140 l b m=280 l b m=280 l b m 32.174 f t s 2=8.703 s l u g s(Q 1:h o w d o I m a k e t h e u n i t s w o r k o u t?)m H e=ρ a i r V b a l l o o n 7=0.0724 l b m f t 3 7⋅32.174 l b m l b f f t s 2⋅14137 f t 3=4.545 s l u g s(Q 2:h o w d o I m a k e t h e u n i t s w o r k o u t?)m t o t a l=m p e o p l e+m H e=(8.703+4.545)s l u g s=13.25 s l u g s m p e o p l e=2⋅140 l b m=280 l b m=280 l b m 32.174 f t s 2=8.703 s l u g s(Q 1:h o w d o I m a k e t h e u n i t s w o r k o u t?)m H e=ρ a i r V b a l l o o n 7=0.0724 l b m f t 3 7⋅32.174 l b m l b f f t s 2⋅14137 f t 3=4.545 s l u g s(Q 2:h o w d o I m a k e t h e u n i t s w o r k o u t?)m t o t a l=m p e o p l e+m H e=(8.703+4.545)s l u g s=13.25 s l u g s
Now let us determine the F n e t F n e t and finally the acceleration by Newton's Second Law:
F t o t a l=m t o t a l g=13.25 s l u g s⋅32.174 f t s 2=426 l b f(Q 3:h o w d o I m a k e t h e u n i t s w o r k o u t?)F n e t=F b−F t o t a l=(1023−426)l b f=596.7 l b f a=F n e t m t o t a l=596.7 l b f 13.25 s l u g s=45.1 f t s 2(Q 4:h o w d o I m a k e t h e u n i t s w o r k o u t?)F t o t a l=m t o t a l g=13.25 s l u g s⋅32.174 f t s 2=426 l b f(Q 3:h o w d o I m a k e t h e u n i t s w o r k o u t?)F n e t=F b−F t o t a l=(1023−426)l b f=596.7 l b f a=F n e t m t o t a l=596.7 l b f 13.25 s l u g s=45.1 f t s 2(Q 4:h o w d o I m a k e t h e u n i t s w o r k o u t?)
I was able to duplicate the solution but I had to fudge on the units because I am not sure how to convert between l b f l b f to l b m l b m to s l u g s s l u g s. Please advise by using the very same calculations in this problem. Please select any of Q1 to Q4 to demonstrate how to use unit conversion factors in U.S. customary units.
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edited Feb 7, 2016 at 19:05
Jules MansonJules Manson
asked Feb 7, 2016 at 6:47
Jules MansonJules Manson
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1 Let me Wikipedia that for you.Wasabi –Wasabi 2016-02-07 20:49:53 +00:00 Commented Feb 7, 2016 at 20:49
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If it helps, convert the input values to whatever units you are comfortable with, then convert the answer to whatever units the question is asking for. If the question doesn't specify units for the answer, and this isn't implied from discussions in class, then answer in any reasonable units you like.
I said reasonable units, since deliberately tweaking the professor's or TA's nose is not a good idea. He might be fine with meters/second instead of feet/second or miles/hour, but furlongs/fortnight is just deliberate provocation.
In any case, pounds-force, pounds-mass, and slugs are all very common units that are well defined out there, so answering that part of your question is pointless. Go look them up. Whether you like them or not, they are units you should at least know how to use, perhaps just looking up the conversion constants when you need them.
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answered Feb 7, 2016 at 14:35
Olin LathropOlin Lathrop
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If you are good with units please help me by showing how any of the calculations seen in the problem might correctly be done with appropriate unit conversion factors. For example how do we go from lbm to slugs and back to lbf in any of the calculations above.Jules Manson –Jules Manson 2016-02-07 18:58:40 +00:00 Commented Feb 7, 2016 at 18:58
1 @Jules: That's really basic stuff. Clearly you haven't even tried to look it up.Olin Lathrop –Olin Lathrop 2016-02-07 19:52:22 +00:00 Commented Feb 7, 2016 at 19:52
Yes I did look it up at several places. The problem is that no one uses real world like examples to show how to use them. I guess I am not as smart as most engineering students.Jules Manson –Jules Manson 2016-02-08 04:16:26 +00:00 Commented Feb 8, 2016 at 4:16
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12510 | https://emedicine.medscape.com/article/204930-overview | Pernicious Anemia: Practice Essentials, Pathophysiology, Etiology
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Tools & Reference>Hematology
Pernicious Anemia
Updated: Apr 23, 2024
Author: Srikanth Nagalla, MD, MS, FACP; Chief Editor: Emmanuel C Besa, MDmore...;)
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Sections
Pernicious Anemia
Sections Pernicious Anemia
Overview
Practice Essentials
Pathophysiology
Etiology
Epidemiology
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CBC and Peripheral Blood Smear
Indirect Bilirubin and Serum Lactate Dehydrogenase
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Serum Folic Acid, Methylmalonic Acid, and Homocysteine
Intrinsic Factor Antibodies
Schilling Test
Clinical Trial of Vitamin B12
Bone Marrow Aspiration and Biopsy
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The term “pernicious anemia” is an anachronism—it dates from the era when treatment had not yet been discovered, and the disease was fatal—but it remains in use to refer to an autoimmune disorder that affects the production of intrinsic factor (IF) by the gastric mucosa. IF binds cobalamin (vitamin B12) and facilitates its transport to the terminal ileum for absorption. Impaired IF production leads to vitamin B12 deficiency andmegaloblastic anemia.
Pernicious anemia occurs as a result of autoimmune destruction of parietal cells, which secrete IF, or the development of auto-antibodies targeted against IF itself. Other conditions that can result in impaired IF production include gastrectomy and a rare congenital autosomal recessive disorder that manifests with IF deficiency without gastric atrophy.
Causes of megaloblastic anemia other than impaired IF production include folic acid deficiency, altered pH in the small intestine, and lack of absorption of vitamin B12 complexes in the terminal ileum. Thus, pernicious anemia must be differentiated from other disorders that interfere with the absorption and metabolism of vitamin B12 (seeDDx and Workup).
Clinical onset of pernicious anemia usually is insidious and vague. The classic triad of weakness, sore tongue, and paresthesias may be elicited but usually is not the chief symptom complex. Typically, medical attention is sought because of symptoms suggestive of cardiac, renal, genitourinary, gastrointestinal, infectious, mental, or neurologic disorders. Blood studies show anemia with macrocytic cellular indices. SeePresentation.
Important goals in the management and care of patients with pernicious anemia include the following:
Confirm that the patient has cobalamin deficiency.
Initiate treatment with cobalamin. Use higher doses of cobalamin in patients with vitamin B12–associated CNS impairment.
Provide concurrent treatment with folic acid and cobalamin in patients who demonstrate evidence for folic acid deficiency but also are being evaluated for pernicious anemia until the latter diagnosis has been ruled out, because although folic acid will restore blood counts, it will not prevent the development of subacute combined system degeneration in patients with pernicious anemia.
Monitor response and effectiveness of cobalamin supplementation.
Administer adequate quantities of cobalamin for the remainder of the patient's life.
Evaluate the patient periodically to rule out gastric carcinoma.
For further discussion, seeTreatment and Medication.
Go to Anemia, Iron Deficiency Anemia, and Chronic Anemia for complete information on these topics.
Next: Pathophysiology
Pathophysiology
Cobalamin is an organometallic substance containing a corrin ring, a centrally located cobalt atom, and various axial ligands (see the image below).
Pernicious anemia. The structure of cyanocobalamin is depicted. The cyanide (Cn) is in green. Other forms of cobalamin (Cbl) include hydroxocobalamin (OHCbl), methylcobalamin (MeCbl), and deoxyadenosylcobalamin (AdoCbl). In these forms, the beta-group is substituted for Cn. The corrin ring with a central cobalt atom is shown in red and the benzimidazole unit in blue. The corrin ring has 4 pyrroles, which bind to the cobalt atom. The fifth substituent is a derivative of dimethylbenzimidazole. The sixth substituent can be Cn, CC3, hydroxycorticosteroid (OH), or deoxyadenosyl. The cobalt atom can be in a +1, +2, or +3 oxidation state. In hydroxocobalamin, it is in the +3 state. The cobalt atom is reduced in a nicotinamide adenine dinucleotide (NADH)–dependent reaction to yield the active coenzyme. It catalyzes 2 types of reactions, which involve either rearrangements (conversion of l methylmalonyl coenzyme A [CoA] to succinyl CoA) or methylation (synthesis of methionine).
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The basic structure known as vitamin B12 is solely synthesized by microorganisms, but most animals are capable of converting vitamin B12 into the two coenzyme forms, adenosylcobalamin and methylcobalamin. The former is required for conversion of L- methylmalonic acid to succinyl coenzyme A (CoA), and the latter acts as a methyltransferase for conversion of homocysteine to methionine.
When either cobalamin or folate is deficient, thymidine synthase function is impaired. This leads to megaloblastic changes in all rapidly dividing cells because DNA synthesis is diminished. In erythroid precursors, macrocytosis and ineffective erythropoiesis occur.
Severe neurologic impairment, usually subacute combined system degeneration, occurs in cobalamin deficiency. However, vitamin B12 deficiency can also present as peripheral neuropathy, psychosis, or leukoencephalopathy. Neurologic manifestations may occur independently of hematologic manifestations in pernicious anemia. The biochemical impairment in neurologic degeneration may differ from hematologic changes.
Meat and milk are the main dietary sources of cobalamin. Because body stores of cobalamin usually exceed 1000 µg and the daily requirement is about 1 µg, strict adherence to a vegetarian diet for more than 5 years usually is required to produce findings of cobalamin deficiency.
Dietary cobalamin is absorbed in a series of steps, which require proteolytic release from foodstuffs and binding to IF. Subsequently, recognition of the IF-cobalamin complex by specialized ileal receptors—cubilin receptors—must occur for transport into the portal circulation, where it is bound by transcobalamin II (TCII), which serves as the plasma transporter.
The cobalamin-TCII complex binds to cell surfaces and is endocytosed. The transcobalamin is degraded within a lysozyme, and the cobalamin is released into the cytoplasm. An enzyme-mediated reduction of the cobalt occurs with either cytoplasmic methylation to form methylcobalamin or mitochondrial adenosylation to form adenosylcobalamin.
Defects of these steps produce manifestations of cobalamin dysfunction. Most defects become manifest in infancy and early childhood and result in impaired development, intellecual disability, and a macrocytic anemia. Certain defects cause methylmalonic aciduria and homocystinuria. See the image below.
Pernicious anemia. Inherited disorders of cobalamin (Cbl) metabolism are depicted. The numbers and letters correspond to the sites at which abnormalities have been identified, as follows: (1) absence of intrinsic factor (IF); (2) abnormal Cbl intestinal adsorption; and (3) abnormal transcobalamin II (TC II), (a) mitochondrial Cbl reduction (Cbl A), (b) cobalamin adenosyl transferase (Cbl B), (c and d) cytosolic Cbl metabolism (Cbl C and D), (e and g) methyl transferase Cbl utilization (Cbl E and G), and (f) lysosomal Cbl efflux (Cbl F).
View Media Gallery)
Intrinsic factor is a gastric protein secreted by parietal cells that is necessary for vitamin B12 absorption.Pernicious anemia is an autoimmune disorder that leads to insufficient intrinsic factor levels either as a result of auto-antibody mediated destruction of parietal cells and/or the intrinsic factor protein itself. Parietal cell auto-antibodies target gastric H+/K+-ATPase. Other disorders that interfere with the absorption and metabolism of vitamin B12 can also result in cobalamin deficiency, with the development of a macrocytic anemia and neurologic complications.
Antiparietal cell antibodies occur in 90% of patients with pernicious anemia but in only 5% of healthy adults. Similarly, binding and blocking antibodies to IF are found in most patients with pernicious anemia. A greater association than anticipated exists between pernicious anemia and other autoimmune diseases, including thyroid disorders, type 1 diabetes mellitus, ulcerative colitis, Addison disease, infertility, and acquired agammaglobulinemia.
An association between pernicious anemia and Helicobacter pylori infections has been postulated but not clearly proven. A higher prevalence of H pylori infection has been reported in patients with pernicious anemia, and eradication of H pylori has had potentially therapeutic effects (eg, reductions in antiparietal cell antibodies, amelioration of atrophic gastritis. However, further research on this hypothesis is warranted.
Cobalamin deficiency may result from dietary insufficiency of vitamin B12; disorders of the stomach, small bowel, and pancreas; certain infections; and abnormalities of transport, metabolism, and utilization (see Etiology). Deficiency may be observed in strict vegetarians. Breastfed infants of vegetarian mothers also are affected. Severely affected infants of vegetarian mothers who do not have overt cobalamin deficiency have been reported.
Classic pernicious anemia produces cobalamin deficiency due to failure of the stomach to secrete IF (see the image below).
Pernicious anemia. Cobalamin (Cbl) is freed from meat in the acidic milieu of the stomach where it binds R factors in competition with intrinsic factor (IF). Cbl is freed from R factors in the duodenum by proteolytic digestion of the R factors by pancreatic enzymes. The IF-Cbl complex transits to the ileum where it is bound to ileal receptors. The IF-Cbl enters the ileal absorptive cell, and the Cbl is released and enters the plasma. In the plasma, the Cbl is bound to transcobalamin II (TC II), which delivers the complex to nonintestinal cells. In these cells, Cbl is freed from the transport protein.
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In adults, pernicious anemia is associated with severe gastric atrophy and achlorhydria, which are irreversible. The achlorhydria results in a decrease in the release of cobalamin bound to dietary protein. Coexistent iron deficiency is common because achlorhydria prevents solubilization of dietary ferric iron from food. Autoimmune phenomena and thyroid disease frequently are observed. Patients with pernicious anemia have a 2- to 3-fold increased incidence of gastric carcinoma.
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Etiology
Cobalamin deficiency may result from the following:
Inadequate dietary intake (ie, vegetarian diet)
Atrophy or loss of gastric mucosa (eg, pernicious anemia, gastrectomy, ingestion of caustic material, hypochlorhydria, histamine 2 [H2] blockers)
Functionally abnormal IF
Inadequate proteolysis of dietary cobalamin
Insufficient pancreatic protease (eg, chronic pancreatitis, Zollinger-Ellison syndrome [ZES])
Bacterial overgrowth in intestine (eg, blind loop, diverticula) – The bacteria compete with the body for cobalamin
Diphyllobothrium latum (fish tapeworm) competes with the body for cobalamin
Disorders of ileal mucosa (eg, resection, ileitis, sprue, lymphoma, amyloidosis, absent IF-cobalamin receptor, Imerslünd-Grasbeck syndrome, ZES, TCII deficiency, use of certain drugs)
Disorders of plasma transport of cobalamin (eg, TCII deficiency, R binder deficiency)
Dysfunctional uptake and use of cobalamin by cells (eg, defects in cellular deoxyadenosylcobalamin [AdoCbl] and methylcobalamin [MeCbl] synthesis)
Pernicious anemia is the most common cause of severe vitamin B12 deficiency worldwide and is due to autoimmune destruction of parietal cells and/or intrinsic factor.
Children who develop cobalamin deficiency usually have a hereditary disorder, and the etiology of their cobalamin deficiency is different from the etiology observed in classic pernicious anemia. Congenital pernicious anemia is a hereditary disorder in which an absence of IF occurs without gastric atrophy due to genetic abnormalities that result in failure to secrete IF or production of defective IF. Other gastric conditions that cause cobalamin deficiency are gastrectomy, gastric stapling, and bypass procedures for obesity and extensive infiltrative disease of the gastric mucosa. Usually, these conditions are associated with a decreased ability to mobilize cobalamin from food rather than a malabsorption of cobalamin; thus, such patients may exhibit a normal finding on a Schilling test (stage I).
Pancreatic insufficiency can produce cobalamin deficiency. Nonspecific R binders chelate cobalamin in the stomach, making it unavailable for binding to IF. Pancreatic proteases degrade the R binders and release the cobalamin so that it can bind IF. The cobalamin-IF complex is formed so that it can bind ileal receptors that enable uptake by absorptive cells. Thus, patients with chronic pancreatitis may have impaired absorption of cobalamin.
Cobalamin deficiency is also reported in ZES. The mechanism is believed to be due to the acidic pH of the distal small intestine, which hinders the cobalamin-IF complex from effectively binding to the ileal receptors.
Disorders of the ileum cause cobalamin deficiency as a consequence of the loss of the ileal receptors for the cobalamin-IF complex. Thus, surgical loss of the ileum and diseases such as tropical sprue, regional enteritis, ulcerative colitis, and ileal lymphoma interfere with cobalamin absorption.
Genetic defects of the ileal receptors for IF (ie, Imerslünd-Grasbeck syndrome) and hereditary transcobalamin I (TCI) deficiency produce cobalamin deficiency from birth and are usually discovered early in life.
Many drugs impair cobalamin uptake in the ileum but are rarely a cause of symptomatic vitamin B12 deficiency, because they are not taken for long enough to deplete body stores of cobalamin. Such agents include nitrous oxide, cholestyramine, para -aminosalicylic acid, neomycin, metformin, phenformin, and colchicine.
The clinical manifestations of inherited defects of cobalamin transport and metabolism are usually observed in infancy and childhood. Thus, they are discussed only briefly in this article.
Three hereditary disorders affect absorption and transport of cobalamin, and another seven alter cellular use and coenzyme production. The three disorders of absorption and transport are TCII deficiency, IF deficiency, and IF receptor deficiency. These defects produce developmental delay and a megaloblastic anemia, which can be alleviated with pharmacologic doses of cobalamin. Serum cobalamin values are decreased in the two IF abnormalities but may be within the reference range in TCII deficiency.
The seven abnormalities of cellular use, commonly denoted by letters A through G, can be detected by the presence or absence of methylmalonic aciduria and homocystinuria. The presence of only methylmalonic aciduria indicates a block in conversion of methylmalonic CoA to succinyl CoA and results in either a genetic deficit in the methylmalonyl CoA mutase that catalyzes the reaction or a defect in synthesis of its CoA cobalamin (cobalamin A and cobalamin B deficiency).
The presence of only homocystinuria results either from poor binding of cobalamin to methionine synthase (cobalamin E deficiency) or from producing methylcobalamin from cobalamin and S adenosylmethionine (cobalamin G deficiency). This results in a reduction in methionine synthesis, with pronounced homocystinemia and homocystinuria.
Methylmalonic aciduria and homocystinuria occur when the metabolic defect impairs reduction of cobalamin III to cobalamin II (cobalamin C, cobalamin D, and cobalamin F deficiency). This reaction is essential for formation of both methylmalonic acid and homocystinuria.
Early detection of these rare disorders is important because most patients respond favorably to large doses of cobalamin. However, some of these disorders are less responsive than others, and delayed diagnosis and treatment are less efficacious.
Abnormalities in the intestinal lumen may produce cobalamin deficiency. Individuals with blind intestinal loops, stricture, and large diverticula may develop bacterial overgrowth, which sequesters dietary cobalamin for their metabolic needs. Tapeworm infestation with Diphyllobothrium latum occurs from eating poorly cooked lake fish that are infected and causes cobalamin deficiency because the parasites have a high requirement for cobalamin.
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Epidemiology
Adult pernicious anemia usually occurs in people aged 40-70 years. One study found 1.9% of patients older than 60 had undiagnosed pernicious anemia. Congenital pernicious anemia usually manifests in children younger than 2 years.
Whereas the disease originally was believed to be restricted primarily to whites of Scandinavian and Celtic origin, subsequent evidence shows that it occurs in all races. In general, the prevalence of pernicious anemia is probably underestimated, due to the complexity of the diagnosis. A female predominance has been reported in England, Scandinavia, and among persons of African descent (1.5:1). However, data in the United States show an equal sex distribution.
Pernicious anemia likely has a genetic predisposition. The disease is diagnosed more commonly in family members of patients diagnosed with pernicious anemia and is associated with human leukocyte antigen (HLA) types A2, A3, and B7 and blood group type A. Approximately 20% of relatives of patients with pernicious anemia are diagnosed with the same condition,
Patients with pernicious anemia have an increased incidence of autoimmune disorders and thyroid disease, suggesting that the disease has an immunologic component. For example, pernicious anemia may occur together with autoimmune thyroid disease, type 1A diabetes mellitus, alopecia, vitiligo, and chronic atrophic gastritis in type III polyglandular autoimmune (PGA) syndrome—one of a rare group of disorders also known as autoimmune polyendocrine syndromes (APS) and polyglandular failure syndromes.
A population-based cohort study of autoimmune disorders in 22 million individuals in the United Kingdom reported that although in general, the incidence rate of autoimmune disorders was higher in the years 2017-19 compared with 2000-02, the incidence rate of pernicious anemia declined significantly (incidence rate ratio 0.79).
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Prognosis
The term pernicious anemia dates from the mid-1800s and reflects the disease's high fatality rate at the time, when its etiology had not yet been discovered. The megaloblastic appearance of cells led many to speculate that it was a neoplastic disease. In the 1920s, however, the response of patients to liver therapy suggested that a nutritional deficiency was responsible for the disorder. This became obvious in clinical trials once vitamin B12 was isolated.
Currently, early recognition and treatment of pernicious anemia provide a normal, and usually uncomplicated, lifespan. Delayed treatment permits progression of the anemia and neurologic complications. If patients are not treated early in the disease, neurologic complications can become permanent. Severe anemia can cause congestive heart failure or precipitate coronary insufficiency.
Although vitamin B12 therapy resolves the anemia, it does not cure the atrophic gastritis, which can progress to gastric cancer. The incidence of gastric adenocarcinoma is 2- to 3-fold greater in patients with pernicious anemia than in the general population of the same age. Presently, periodic gastroscopy and/or barium roentgenographic studies are not advocated in patients with treated pernicious anemia who are asymptomatic, because such screening has not been demonstrated to prolong lifespan.
A population-based, case-control study using the Surveillance, Epidemiology, and End Results (SEER)–Medicare database found that elderly persons with pernicious anemia were not only at significantly increased risk for noncardia gastric adenocarcinoma (odds ratio [OR] 2.18) and gastric carcinoid tumors (OR, 11.43), they were also at increased risk for the following :
Tonsillar cancer (OR, 2.00)
Hypopharyngeal cancer (OR, 1.92)
Esophageal squamous cell carcinoma (OR, 2.12)
Small intestinal cancer (OR, 1.63)
Liver cancer (OR, 1.49)
Myeloma (OR, 1.55)
Acute myeloid leukemia (OR, 1.68)
Myelodysplastic syndrome (OR, 2.87)
In a longitudinal study of 199 intrinsic factor antibody (IFA)–positive and 168 IFA-negative Chinese patients, Chan et al found that despite a good hematologic response to therapy, both groups had an unsatisfactory neurologic response, and newly diagnosed hypothyroidism was found during follow-up. In addition, newly diagnosed cancers were also found (24 in IFA-positive patients, seven in IFA-negative patients), of which 20% were gastric cancer.
For the IFA-positive patients with a cancer, mean survival was 64 months; for those without a cancer, it was 129 months. Mortality was 31% in this group, in which cancer-related deaths represented 37% of the total. For the IFA-negative patients with a cancer, mean survival was 36 months. For those without a cancer, it was 126 months. Mortality was 21% in this group, in which cancer-related deaths represented 14% of the total.
Chan et al concluded that although Chinese patients treated for pernicious anemia demonstrated a good survival period, they remained at increased risk for gastric carcinoma, and IFA-positive patients had a higher risk of developing all types of cancers and cancer-related deaths than did IFA-negative patients.
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Patient Education
Lifelong compliance in obtaining adequate vitamin B12 by injection (or possibly orally) is necessary to avoid relapse of pernicious anemia.
For patient education resources, see Pernicious Anemia (Vitamin B-12 Deficiency) and Vitamin B12.
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Clinical Presentation
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References
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Murphy G, Dawsey SM, Engels EA, Ricker W, Parsons R, Etemadi A, et al. Cancer Risk After Pernicious Anemia in the US Elderly Population. Clin Gastroenterol Hepatol. 2015 Jun 14. [QxMD MEDLINE Link].
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Media Gallery
Pernicious anemia. The structure of cyanocobalamin is depicted. The cyanide (Cn) is in green. Other forms of cobalamin (Cbl) include hydroxocobalamin (OHCbl), methylcobalamin (MeCbl), and deoxyadenosylcobalamin (AdoCbl). In these forms, the beta-group is substituted for Cn. The corrin ring with a central cobalt atom is shown in red and the benzimidazole unit in blue. The corrin ring has 4 pyrroles, which bind to the cobalt atom. The fifth substituent is a derivative of dimethylbenzimidazole. The sixth substituent can be Cn, CC3, hydroxycorticosteroid (OH), or deoxyadenosyl. The cobalt atom can be in a +1, +2, or +3 oxidation state. In hydroxocobalamin, it is in the +3 state. The cobalt atom is reduced in a nicotinamide adenine dinucleotide (NADH)–dependent reaction to yield the active coenzyme. It catalyzes 2 types of reactions, which involve either rearrangements (conversion of l methylmalonyl coenzyme A [CoA] to succinyl CoA) or methylation (synthesis of methionine).
Pernicious anemia. Inherited disorders of cobalamin (Cbl) metabolism are depicted. The numbers and letters correspond to the sites at which abnormalities have been identified, as follows: (1) absence of intrinsic factor (IF); (2) abnormal Cbl intestinal adsorption; and (3) abnormal transcobalamin II (TC II), (a) mitochondrial Cbl reduction (Cbl A), (b) cobalamin adenosyl transferase (Cbl B), (c and d) cytosolic Cbl metabolism (Cbl C and D), (e and g) methyl transferase Cbl utilization (Cbl E and G), and (f) lysosomal Cbl efflux (Cbl F).
Pernicious anemia. Cobalamin (Cbl) is freed from meat in the acidic milieu of the stomach where it binds R factors in competition with intrinsic factor (IF). Cbl is freed from R factors in the duodenum by proteolytic digestion of the R factors by pancreatic enzymes. The IF-Cbl complex transits to the ileum where it is bound to ileal receptors. The IF-Cbl enters the ileal absorptive cell, and the Cbl is released and enters the plasma. In the plasma, the Cbl is bound to transcobalamin II (TC II), which delivers the complex to nonintestinal cells. In these cells, Cbl is freed from the transport protein.
Peripheral smear of blood from a patient with pernicious anemia. Macrocytes are observed, and some of the red blood cells show ovalocytosis. A 6-lobed polymorphonuclear leucocyte is present.
Bone marrow aspirate from a patient with untreated pernicious anemia. Megaloblastic maturation of erythroid precursors is shown. Two megaloblasts occupy the center of the slide with a megaloblastic normoblast above.
Response to therapy with cobalamin (Cbl) in a previously untreated patient with pernicious anemia. A reticulocytosis occurs within 5 days after an injection of 1000 mcg of Cbl and lasts for about 2 weeks. The hemoglobin (Hgb) concentration increases at a slower rate because many of the reticulocytes are abnormal and do not survive as mature erythrocytes. After 1 or 2 weeks, the Hgb concentration increases about 1 g/dL per week.
of 6
Tables
Table 1. Serum Methylmalonic Acid and Homocysteine Values Used in Differentiating Between Cobalamin and Folic Acid Deficiency;)
Table 2. Schilling test results;)
Table 1. Serum Methylmalonic Acid and Homocysteine Values Used in Differentiating Between Cobalamin and Folic Acid Deficiency
Patient ConditionMethylmalonic AcidHomocysteine
Healthy Normal Normal
Vitamin B12 deficiency Elevated Elevated
Folate deficiency Normal Elevated
Table 2. Schilling test results
Patient ConditionStage I
No Intrinsic FactorStage II
Intrinsic FactorStage III
AntibioticStage IV
Pancreatic Extract
Healthy Normal………
Pernicious anemia Low Normal……
Bacterial overgrowth Low Low Normal…
Pancreatic insufficiency Low Low Low Normal
Defect in ileum Low Low Low Low
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Contributor Information and Disclosures
Author
Srikanth Nagalla, MD, MS, FACP Chief of Benign Hematology, Miami Cancer Institute, Baptist Health South Florida; Clinical Professor of Medicine, Florida International University, Herbert Wertheim College of Medicine
Srikanth Nagalla, MD, MS, FACP is a member of the following medical societies: American Society of Hematology, Association of Specialty Professors
Disclosure: Serve(d) as a director, officer, partner, employee, advisor, consultant or trustee for: Alexion; Alnylam; Kedrion; Sanofi; Dova; Apellis; PharmacosmosServe(d) as a speaker or a member of a speakers bureau for: Sobi; Sanofi; Rigel.
Coauthor(s)
Salem Kim, MD, MPH Physician in Hematology/Oncology, Miami Cancer Institute, Baptist Health South Florida
Salem Kim, MD, MPH is a member of the following medical societies: American Society of Clinical Oncology, American Society of Hematology
Disclosure: Nothing to disclose.
Chief Editor
Emmanuel C Besa, MD Professor Emeritus, Department of Medicine, Division of Hematologic Malignancies and Hematopoietic Stem Cell Transplantation, Kimmel Cancer Center, Jefferson Medical College of Thomas Jefferson University
Emmanuel C Besa, MD is a member of the following medical societies: American Association for Cancer Education, American Society of Clinical Oncology, American College of Clinical Pharmacology, American Federation for Medical Research, American Society of Hematology, New York Academy of Sciences
Disclosure: Nothing to disclose.
Additional Contributors
Marcel E Conrad, MD Distinguished Professor of Medicine (Retired), University of South Alabama College of Medicine
Marcel E Conrad, MD is a member of the following medical societies: Alpha Omega Alpha, American Association for the Advancement of Science, American Association of Blood Banks, American Chemical Society, American College of Physicians, American Physiological Society, American Society for Clinical Investigation, American Society of Hematology, Association of American Physicians, The Society of Federal Health Professionals (AMSUS), International Society of Hematology, Society for Experimental Biology and Medicine, SWOG
Disclosure: Partner received none from No financial interests for none.
Paul Schick, MD † Emeritus Professor, Department of Internal Medicine, Jefferson Medical College of Thomas Jefferson University; Research Professor, Department of Internal Medicine, Drexel University College of Medicine; Adjunct Professor of Medicine, Lankenau Hospital
Paul Schick, MD is a member of the following medical societies: American College of Physicians, American Society of Hematology
Disclosure: Nothing to disclose.
Acknowledgements
David Aboulafia, MD Medical Director, Bailey-Boushay House, Clinical Professor, Department of Medicine, Division of Hematology, Attending Physician, Section of Hematology/Oncology, Virginia Mason Clinic; Investigator, Virginia Mason Community Clinic Oncology Program/SWOG
David Aboulafia, MD is a member of the following medical societies: American College of Physicians, American Medical Association, American Medical Directors Association, American Society of Hematology, Infectious Diseases Society of America, and Phi Beta Kappa
Disclosure: Nothing to disclose.
Troy H Guthrie, Jr, MD Director of Cancer Institute, Baptist Medical Center
Troy H Guthrie, Jr, MD is a member of the following medical societies: American Federation for Medical Research, American Medical Association, American Society of Hematology, Florida Medical Association, Medical Association of Georgia, and Southern Medical Association
Disclosure: Nothing to disclose.
Francisco Talavera, PharmD, PhD Adjunct Assistant Professor, University of Nebraska Medical Center College of Pharmacy; Editor-in-Chief, Medscape Drug Reference
Disclosure: Medscape Salary Employment
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In mathematics, the Robinson–Schensted–Knuth correspondence, also referred to as the RSK correspondence or RSK algorithm, is a combinatorial bijection between matrices A with non-negative integer entries and pairs (P,Q) of semistandard Young tableaux of equal shape, whose size equals the sum of the entries of A. More precisely the weight of P is given by the column sums of A, and the weight of Q by its row sums.
It is a generalization of the Robinson–Schensted correspondence, in the sense that taking A to be a permutation matrix, the pair (P,Q) will be the pair of standard tableaux associated to the permutation under the Robinson–Schensted correspondence.
The Robinson–Schensted–Knuth correspondence extends many of the remarkable properties of the Robinson–Schensted correspondence, notably its symmetry: transposition of the matrix A results in interchange of the tableaux P,Q.
The Robinson–Schensted–Knuth correspondence
[edit]
Introduction
[edit]
The Robinson–Schensted correspondence is a bijective mapping between permutations and pairs of standard Young tableaux, both having the same shape. This bijection can be constructed using an algorithm called Schensted insertion, starting with an empty tableau and successively inserting the values σ1, ..., σn of the permutation σ at the numbers 1, 2, ..., n; these form the second line when σ is given in two-line notation:
.
The first standard tableau P is the result of successive insertions; the other standard tableau Q records the successive shapes of the intermediate tableaux during the construction of P.
The Schensted insertion easily generalizes to the case where σ has repeated entries; in that case the correspondence will produce a semistandard tableau P rather than a standard tableau, but Q will still be a standard tableau. The definition of the RSK correspondence reestablishes symmetry between the P and Q tableaux by producing a semistandard tableau for Q as well.
Two-line arrays
[edit]
The two-line array (or generalized permutation) wA corresponding to a matrix A is defined as
in which for any pair (i,j) that indexes an entry Ai,j of A, there are Ai,j columns equal to , and all columns are in lexicographic order, which means that
, and
if and then .
Example
[edit]
The two-line array corresponding to
is
Definition of the correspondence
[edit]
By applying the Schensted insertion algorithm to the bottom line of this two-line array, one obtains a pair consisting of a semistandard tableau P and a standard tableau Q0, where the latter can be turned into a semistandard tableau Q by replacing each entry b of Q0 by the b-th entry of the top line of wA. One thus obtains a bijection from matrices A to ordered pairs, (P,Q) of semistandard Young tableaux of the same shape, in which the set of entries of P is that of the second line of wA, and the set of entries of Q is that of the first line of wA. The number of entries j in P is therefore equal to the sum of the entries in column j of A, and the number of entries i in Q is equal to the sum of the entries in row i of A.
Example
[edit]
In the above example, the result of applying the Schensted insertion to successively insert 1,3,3,2,2,1,2 into an initially empty tableau results in a tableau P, and an additional standard tableau Q0 recoding the successive shapes, given by
and after replacing the entries 1,2,3,4,5,6,7 in Q0 successively by 1,1,1,2,2,3,3 one obtains the pair of semistandard tableaux
Direct definition of the RSK correspondence
[edit]
The above definition uses the Schensted algorithm, which produces a standard recording tableau Q0, and modifies it to take into account the first line of the two-line array and produce a semistandard recording tableau; this makes the relation to the Robinson–Schensted correspondence evident. It is natural however to simplify the construction by modifying the shape recording part of the algorithm to directly take into account the first line of the two-line array; it is in this form that the algorithm for the RSK correspondence is usually described. This simply means that after every Schensted insertion step, the tableau Q is extended by adding, as entry of the new square, the b-th entry ib of the first line of wA, where b is the current size of the tableaux. That this always produces a semistandard tableau follows from the property (first observed by Knuth) that for successive insertions with an identical value in the first line of wA, each successive square added to the shape is in a column strictly to the right of the previous one.
Here is a detailed example of this construction of both semistandard tableaux. Corresponding to a matrix
one has the two-line array
The following table shows the construction of both tableaux for this example
| | | | | | | | | |
--- --- --- ---
| Inserted pair | | | | | | | | |
| P | | | | | | | | |
| Q | | | | | | | | |
Combinatorial properties of the RSK correspondence
[edit]
The case of permutation matrices
[edit]
If is a permutation matrix then RSK outputs standard Young Tableaux (SYT), of the same shape . Conversely, if are SYT having the same shape , then the corresponding matrix is a permutation matrix. As a result of this property by simply comparing the cardinalities of the two sets on the two sides of the bijective mapping we get the following corollary:
Corollary 1: For each we have
where means varies over all partitions of and is the number of standard Young tableaux of shape .
Symmetry
[edit]
Let be a matrix with non-negative entries. Suppose the RSK algorithm maps to then the RSK algorithm maps to , where is the transpose of .
In particular for the case of permutation matrices, one recovers the symmetry of the Robinson–Schensted correspondence:
Theorem 2: If the permutation corresponds to a triple , then the inverse permutation, , corresponds to .
This leads to the following relation between the number of involutions on with the number of tableaux that can be formed from (An involution is a permutation that is its own inverse):
Corollary 2: The number of tableaux that can be formed from is equal to the number of involutions on .
Proof: If is an involution corresponding to , then corresponds to ; hence . Conversely, if is any permutation corresponding to , then also corresponds to ; hence . So there is a one-one correspondence between involutions and tableaux
The number of involutions on is given by the recurrence:
Where . By solving this recurrence we can get the number of involutions on ,
Symmetric matrices
[edit]
Let and let the RSK algorithm map the matrix to the pair , where is an SSYT of shape . Let where the are non-negative integers and . Then the map establishes a bijection between symmetric matrices with and SSYT's of weight .
Applications of the RSK correspondence
[edit]
Cauchy's identity
[edit]
The Robinson–Schensted–Knuth correspondence provides a direct bijective proof of the following celebrated identity for symmetric functions:
where are Schur functions.
Kostka numbers
[edit]
Fix partitions , then
where and denote the Kostka numbers and is the number of matrices , with non-negative elements, with and .
References
[edit]
^ Jump up to: a b c Stanley, Richard P. (1999). Enumerative Combinatorics. Vol. 2. New York: Cambridge University Press. pp. 316–380. ISBN 0-521-55309-1.
^ Jump up to: a b Knuth, Donald E. (1970). "Permutations, matrices, and generalized Young tableaux". Pacific Journal of Mathematics. 34 (3): 709–727. doi:10.2140/pjm.1970.34.709. MR 0272654.
^ Jump up to: a b Knuth, Donald E. (1973). The Art of Computer Programming, Vol. 3: Sorting and Searching. London: Addison–Wesley. pp. 54–58. ISBN 0-201-03803-X.
Brualdi, Richard A. (2006). Combinatorial matrix classes. Encyclopedia of Mathematics and Its Applications. Vol. 108. Cambridge: Cambridge University Press. pp. 135–162. ISBN 0-521-86565-4. Zbl 1106.05001.
| Donald Knuth | |
--- |
| Publications | The Art of Computer Programming "The Complexity of Songs" Computers and Typesetting Concrete Mathematics Surreal Numbers Things a Computer Scientist Rarely Talks About Selected papers series |
| Software | TeX Metafont MIXAL (MIX MMIX) |
| Fonts | AMS Euler Computer Modern Concrete Roman |
| Literate programming | WEB CWEB |
| Algorithms | Knuth's Algorithm X Knuth–Bendix completion algorithm Knuth–Morris–Pratt algorithm Knuth shuffle Robinson–Schensted–Knuth correspondence Trabb Pardo–Knuth algorithm Generalization of Dijkstra's algorithm Knuth's Simpath algorithm |
| Other | Dancing Links Knuth reward check Knuth Prize Knuth's up-arrow notation Man or boy test Quater-imaginary base -yllion Potrzebie system of weights and measures |
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12512 | https://creativemeddoses.com/topics-list/renal-hypoxia-why-kidney-is-prone-to-hypoxia-and-ischemic-injury/ | Renal Hypoxia: Why kidney is prone to hypoxia and ischemic injury? - Creative Med Doses
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Renal Hypoxia: Why kidney is prone to hypoxia and ischemic injury?
Renal hypoxia can lead to acute kidney injury and chronic kidney disease.
The kidneys weigh less than 0.5% of body weight and receive 20%–25% of our cardiac output at rest. The kidneys are the most highly perfused organs in the body if we calculate blood per gram of the tissue.
Despite having an ample supply of blood, the kidney especially, the renal medulla is highly vulnerable to hypoxia and subsequent ischemia. Hypoxia and ischemia are the significant pathophysiological features of acute kidney injury and chronic kidney disease.
The S3 segment (straight segment) of the proximal tubule and the medullary thick ascending limb of the loop of Henle (mTAL)are most prone to ischemic injury. Both these tubular areas exist in relatively lower oxygen conditions. It is a trade-off to be able to get a high osmotic gradient and concentrated urine.
1.Renal tubules have high metabolic demands due to active reabsorption of sodium -Metabolic demands of renal tubules keep them hungry for oxygen, especially proximal convoluted tubules of the renal medulla are always on the verge of getting hypoxia.
The proximal convoluted tubules reabsorb most of sodium and water from tubular filtrate. Sodium reabsorption is an active process that requires energy in the form of ATP. The production of ATP is dependent upon oxygen supply. PCT cells are always in demand of oxygen, and anything which compromises the oxygen delivery to these cells causes PCT cell injury and death.
...
Hypoxic Proximal Convoluted tubular cells in Renal Hypoxia and Acute Kidney Injury
...
2.Reduced density of peritubular capillaries causes limited oxygen delivery-
Chronic kidney disease cases have capillary rarefaction. It impairs oxygen delivery and causes further tubular damage. Such kidneys are in a vicious cycle of tubular injury, inflammation, interstitial fibrosis, and capillary loss.
Peritubular capillary (PTC) rarefaction is one of the hallmarks of CKD, and the degree of PTC loss may predict the renal outcome.
PTC endothelial cells (ECs) undergo apoptosis during CKD, leading to capillary loss, tissue hypoxia, and oxidative stress.
In a normal kidney, there is a perfect balance of proangiogenic factors and anti-angiogenic factors. It maintains renal angiogenesis to the optimum level. In cases with CKD, tubular injury leads to endothelial damage and apoptosis, Which causes reduced proangiogenic factors and increased anti-angiogenic factors. It limits the kidney’s ability to recruit more capillaries in hours of need.
The endothelial injury and interstitial edema caused by tubular injury lead to vascular collapse. Reduced peritubular capillary numbers render tubules sensitive for oxygen deprivation and subsequent hypoxia. Capillary rarefaction is one of the reasons why CKD cases have an increased risk of developing acute kidney injury.
Note:Mitigating PTC rarefaction might become the practical therapeutic target to halt the progression of CKD.
3.Adult kidney has poor angiogenesis capacity
Renal endothelial cells are relatively insensitive to proangiogenic factors like VEGF (vascular endothelial growth factor.
Endothelial cells of the kidney have a poor proliferative capacity which leads to peritubular rarefaction.
It increases the risk of progression of acute kidney injury to chronic kidney disease.
4.Renal vessels have limited vasodilating capacity in response to hypoxia
Most organs under hypoxic conditions increase local blood flow by vasodilation (Functional/Reactive Hyperemia). But the renal vessels do not dilate in response to acute hypoxia. Since the kidney is the body’s critmeter and erythropoietin producer, the kidney tends to preserve these functions at the cost of protecting itself from hypoxia.
If the kidney vasodilates in response to every acute hypoxia episode, it will immediately change the Glomerular filtration rate. And extracellular fluid volume will be affected, which seems to affect every organ of the body afterward. In short, evolution has put more value on the regulation of ECF volume than it has on saving kidneys from hypoxia.
5.Oxygen shunting leads to limited oxygen delivery -
The branches of the renal arteries and veins run parallel and in close contact with each other in the renal cortex and the medulla. The blood flows in countercurrent fashion in these intimately located vessels.
This parallel arrangement facilitates oxygen to diffuse from the arterial system into the venous system before it has entered the tubular capillary bed. It is called diffusive oxygen shunting.
This oxygen shunting deprives renal tubules of oxygen and makes them vulnerable to hypoxia. The low oxygen supply impairs energy generation (ATP formation) in tubules.
Most of the tubular segments (proximal tubule and medullary thick ascending loop) have a limited capacity for anaerobic energy generation. And are dependent on oxygen for aerobic energy generation to maintain active tubular reabsorption of solutes, especially sodium.
The limited tissue oxygen supply and high oxygen demand increase the susceptibility of the kidney to hypoxia, ischemia, and acute kidney injury.
...
oxygen shunting in renal medulla and renal hypoxia
...
6.Low medullary flow to facilitate urine concentration makes the medulla vulnerable to hypoxia-
The generation of a gradient of increasing osmolality from the outer medulla to the tip of the papilla is a critical component of the urinary concentrating process.
The countercurrent arrangement of descending and ascending vasa recta creates an osmotic gradient.
The renal medulla's low blood flow is an absolute requirement for the maintenance of this solute gradient. Medullary blood flow is <1% of total renal blood flow.
If the medullary blood flow increases, the efficiency of a countercurrent system falls. Because of the reduction in transit time, the solute cannot concentrate in the medulla to create an osmotic gradient.
Low blood flow causes slow oxygen delivery, which can cause a discrepancy in medullary oxygen demand and supply. That makes the renal medulla vulnerable to hypoxia.
7.Distance between medullary vessels and medullary Thick Ascending Loop (mTAL)
Tubular-Vascular relationship in the medulla is critical for countercurrent exchange and maintenance of osmotic gradient.
The medullary thick ascending loop of Henle (mTAL) is a little distant from descending vasa recta.
According to the hypothesis, this topography has an adaptive benefit of an increased lateral osmotic gradient. It promotes sodium and water reabsorption in the thick ascending loop of Henle.
Having blood vessels a little far limits blood supply and oxygen delivery to mTAL. The mTAL has high metabolic demands because it actively reabsorbs sodium.
The high demand and sparse oxygen supply render mTAL vulnerable to hypoxia, ischemia, and acute kidney injury.
...
Renal Hypoxia: what makes kidney vulnerable to hypoxia
...
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12513 | https://www.aatbio.com/resources/faq-frequently-asked-questions/Are-the-ER-and-the-nucleus-attached | Are the ER and the nucleus attached? | AAT Bioquest
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Are the ER and the nucleus attached?
Posted August 24, 2021
Endoplasmic Reticulum (ER)Cell Structures and Organelles
Answer
Yes, the ER (endoplasmic reticulum) and the nucleus are attached through their outer membranes. Specifically, it is the rough ER that is attached to the nucleus.
The ER is a large membrane-bound organelle that is spread throughout the cytoplasm of eukaryotic cells. It is composed of one continuous, unbroken membrane that is made up of two layers.
There are two types of endoplasmic reticulum – smooth ER and rough ER. The rough ER lies immediately adjacent to the cell nucleus. The outer membrane of the rough ER is continuous with the outer membrane of the nuclear envelope. Both, the rough ER and the nuclear envelope, have numerous ribosomes attached to the outer membrane.
The perinuclear space that lies between the outer and inner membranes of the nuclear envelope is also connected with the lumen of the rough ER.
Additional resources
Endoplasmic Reticulum Structure and Interconnections with Other OrganellesCell Navigator™ Live Cell Endoplasmic Reticulum (ER) Staining Kit Blue FluorescenceEndoplasmic Reticulum (ER)
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12514 | https://dl.icdst.org/pdfs/files1/a3355db469d28b217300ad41f21a917e.pdf | 126 Perry’s Chemical Engineers’ Handbook, Eighth Edition Don W. Green (Co-editor) & Robert H. Perry (Co-editor) como referenciar este artigo: DINIS, M. A. P. - Book review of Perry’s chemical engineers’ han-dbook, eighth edition. Revista da Faculdade de Ciência e Tecnologia. Porto : Edições Universidade Fernando Pessoa. ISSN 1646-0499. 6 (2009) 126-127.
Book Description Perry´s Chemical Engineers’ Handbook was first published in 1934 and it has readily been transformed in a huge source of chemical engineering information and data. It thus became essential to chemical engineers, first, and, almost immediately, to many other engineers and scientists. It is worldwide considered as an essential desk reference. With a big assortment of theory and practical data, it contains most of the information which is needed is several areas. The use of the book in the beginning may be considered by some as difficult but once engaged on it, it serves as a powerful tool. It covers numerous items, from conversion factors, mathematical, physical and chemical data – two of the most very important sections of the book - to economics, equipment, waste management, energy and materials, which, in its Eighth Edition, are included in 25 Sections. It includes the contribution of a significant number of recognized experts in the several focused fields. The Handbook is broken into logical sections that once the reader has come to grips with the way the book is organized, makes finding information easy. They can be bought individually, which is a very interesting way to allow special aspects to be studied by anyone without acquiring the whole book.
Emphasis must be put on the fact that the latest advances in technology and processes, which came with the new millennium, namely relating aspects like distillation, liquid-liquid extraction, reactor modeling, biological processes, even chemical plants safety practices with case histories, were included now.
SI units have become more representative, since the seventh edition, and thus section 1 with conversion factors intends to help on that issue. Section 2 provides physical and che-mical data, including constants for properties correlations. Section 3 includes essential ma-thematical tools. Section 4 to 7 are about Thermodynamics, Heat and Mass Transfer, Fluid and Plastic Dynamics and Reaction Kinetics. Section 8 covers Process Control and Section 9 Process Economics, dealing about cost control, and cost estimation. Transport and Sto-rage of Fluids is treated in Section 10. Sections 11 to 21 deal with more specific aspects of chemical engineering unit operations, from Transport and Storage of Fluids in Section 11, to Solid-Solid Operations and Processing, in Section 21. Waste Management is explored in Sec-tion 22, covering 109 pages of detailed information on the subject, a very important aspect of interaction with other disciplines. In Section 23 Process Safety is investigated. Section 24 includes practical aspects of perhaps the most important issue of this century: Energy Re-sources, Conversion and Utilization and, finally, Section 25 deals with another aspect which deeply interacts with Energy, which is Materials of Construction.
127 Hundreds of detailed illustrations help the reader to understand subjects more easily and quickly.
It may be argued that to understand easily, in terms of matter and complexity, the contents of Perry’s can be, in fact, equivalent to some graduated degree in chemical engineering.
About the Authors DON W. GREEN, is Deane E. Ackers Distinguished Professor of Chemical and Petroleum En-gineering and codirector of the Tertiary Oil Recovery Project at the University of Kansas in Lawrence, Kansas, where he has taught since 1964. He received his doctorate in chemical engineering in 1963 from the University of Oklahoma, where he was Dr. Perry’s first doctoral student. Dr. Green has won several teaching awards at the University of Kansas, and he is a fellow of the American Institute of Chemical Engineers and an Honorary Member of the Society of Petroleum Engineers. He is the author of numerous articles in technical journals.
ROBERT PERRY, deceased, served as chairman of the Department of Chemical Engineering at the University of Oklahoma and program director for graduate facilities at the National Science Research Foundation. He was a consultant in various United Nations and other in-ternational organizations. From 1973 until his death in 1978, Dr. Perry devoted his time to a study of the cross impact of technologies within the next half century. The subjects under his investigation on a global basis were energy, minerals and metals, transportation and communications, medicine, food production, and the environment.
Book Details Hardcover: 2400 pages Publisher: McGraw-Hill (October 23, 2007) Language: English ISBN-10: 0071422943 ISBN-13: 978-0071422949 Maria Alzira Pimenta Dinis Universidade Fernando Pessoa, CIAGEB (UFP) madinis@ufp.edu.pt |
12515 | https://www.britannica.com/summary/atomic-number | What is an atomic number? | Britannica
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Below is the article summary. For the full article, see atomic number.
atomic number, Number of a chemical element in the systematic, ordered sequence shown in the periodic table. The elements are arranged in order of increasing number of protons in the nucleus of the atom (the same as the number of electrons in the neutral atom), and that number for each element is its atomic number.
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12516 | https://stats.stackexchange.com/questions/333353/rolling-one-die-after-another | probability - Rolling one die after another - Cross Validated
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Rolling one die after another
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If I roll 1 6 sided die, the chances of getting one number, say 6, is 1/6 or 16.6%. If I roll 2 dice simultaneously, then the probability of rolling that number twice is 1/36 or 2.7% (1/6 x 1/6).
What if I have this situation: I roll a die, and if I get a 6, then I'll roll again. What are the chances of me getting a 6 the second time? I think it's also 1/36, but the difference is that I make the second roll if I get a 6 the first time. If I roll 2 dice simultaneously, let's say I differentiate them as the first and second die, the first die can be any number other than 6 while the second die still rolls. Is it still the same?
Is not getting the 6 the first roll, and not rolling the second die, and rolling two dice simultaneously and not getting two 6s the same level of failure in terms of probability? (even if 1 die rolls a 6 the other doesn't? Say I get a 6 on the second die but not the first).
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edited Mar 14, 2018 at 2:19
Alexis
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MarcLikesMathMarcLikesMath
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1 \begingroup No You know that the first roll is a 6 so the conditional probability of getting another 6 assuming independence of the rolls is 1/6.\endgroup Michael R. Chernick –Michael R. Chernick 2018-03-14 02:11:28 +00:00 Commented Mar 14, 2018 at 2:11
\begingroup You might find the Geometric Distribution to be of interest (particularly if you care that rolling a second 6 means you roll a third die).\endgroup Alexis –Alexis 2018-03-14 02:20:34 +00:00 Commented Mar 14, 2018 at 2:20
\begingroup@MichaelChernick It's not independent. Whether or not you roll the second die depends on whether or not you get a 6 on the first roll. You get to roll if you get the first 6.\endgroup MarcLikesMath –MarcLikesMath 2018-05-17 12:18:27 +00:00 Commented May 17, 2018 at 12:18
\begingroup@Alexis How does geometric distribution affect this? Correct me if I'm wrong but isn't geometric distribution related to unrelated events? Like how likely am I to get 6 based on X amount of rolls? Because Whether or not I roll the second time depends on if I get a 6 on the first time, so it's entirely dependent.\endgroup MarcLikesMath –MarcLikesMath 2018-05-17 12:21:46 +00:00 Commented May 17, 2018 at 12:21
\begingroup It is still the case that what you get after a 6 is still just as likely to be any number 1-6.\endgroup Michael R. Chernick –Michael R. Chernick 2018-05-17 17:10:11 +00:00 Commented May 17, 2018 at 17:10
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As other people have pointed out in comments, the correct answer to the question "what is the probability of rolling another 6 given that I have rolled a 6 prior to it?" is indeed \frac{1}{6}. This is because the die rolls are assumed (very reasonably so) to be independent of each other. This means that past rolls of the die does not affect future die rolls.
Expressed mathematically, independence of two variables X and Y imply that Pr(Y=y | X = x) = Pr(Y = y).
Letting X be a variable denoting the outcome of the first die roll and Y be a variable for the second die roll, we can use the definition of independence to arrive to the conclusion that Pr(Y=6 | X = 6) = Pr(Y = 6)=1/6.
The reason that the answer is not 1/36 is due to the fact that we are making a conditional statement. We are saying "given that we already have rolled a six in the first roll". This means that we are not interested in the likelihood of that first roll occuring. We are only interested in what happens next.
It might be helpful to enumerate all possible outcomes here. I have done this below in the form {x, y}, where x is the outcome in the first roll and y in the second.
{1, 1} {1, 2} {1, 3} {1, 4} {1, 5} {1, 6}
{2, 1} {2, 2} {2, 3} {2, 4} {2, 5} {2, 6}
{3, 1} {3, 2} {3, 3} {3, 4} {3, 5} {3, 6}
{4, 1} {4, 2} {4, 3} {4, 4} {4, 5} {4, 6}
{5, 1} {5, 2} {5, 3} {5, 4} {5, 5} {5, 6}
{6, 1} {6, 2} {6, 3} {6, 4} {6, 5} {6, 6}
Now, the probability you are interested in is the event {6, 6}. If you give the information that you are in the last row (which corresponds to having rolled a 6 in the first roll), you only have six possibilities of outcomes. Only one of them is a "success", so the probability of that event is 1/6.
Edit:
After re-reading the OP's question, it appears that I have missed part of the question. The question there seems to be regarding the following scenario:
A six-sided die is rolled.
If the die rolled a 6, roll a second die. Otherwise, do not roll a second die.
The question is there: What is the probability that this procedure results in two sixes having been rolled? Equivalently: What is the probability that this procedure results in us rolling a six in step 2?
The answer to this question is indeed 1/36. Heuristically, the reason for this is that we now are not conditioning on something that has happened anymore. We are instead asking for the probability of an event that can occur after we go through a procedure.
Let us now prove that the probability is 1/36. Letting once again X be the result of the first roll and Y the result of the second roll. We are interested in Pr(Y=6). Note that if X\neq 6 then the probability that Y=6 is zero since the second die won't be rolled. Thus Pr(Y=6\mid X\neq6)=0. We use the law of total probability to note that Pr(Y=6)=\underset{x=1}{\overset{6}{\sum}}Pr(Y=6 \mid X=x) \cdot Pr(X=x).
Now since Pr(Y=6 \mid X=x)=0\forall x\neq 6, we see that
Pr(Y=6) = 0+0+0+0+0+Pr(Y=6\mid X=6)\cdot Pr(X=6).
This simplifies to Pr(Y=6) = \frac{1}{6}\cdot\frac{1}{6}=\frac{1}{36} which completes the proof.
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edited Oct 10, 2018 at 8:34
answered Oct 9, 2018 at 8:16
PhilPhil
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12517 | https://www.fq.math.ca/Scanned/20-2/spickerman.pdf | BINET'S FORMULA FOR THE TRIBONACCI SEQUENCE W. R. SPICKERMAN East Carolina University, Greenville, NC 27834 (Submitted April 1980) 1. Introduction The terms of a recursive sequence are usually defined by a recurrence pro-cedure; that is, any term is the sum of preceding terms. Such a definition might not be entirely satisfactory, because the computation of any term could require the computation of all of its predecessors. An alternative definition gives any term of a recursive sequence as a function of the index of the term. For the simplest nontrivial recursive sequence, the Fibonacci sequence, Binet's formula _ un = (l//5)(a"+1 - B"+1) defines any Fibonacci number as a function of its index and the constants a = |(1 + /I) a n d 3=-|(l-/5). In this paper, an analog of Binets formula for the Tribonacci sequence 1, 1, 2,4, 7, ..., un+1 = un + un_x + un_2, ... (see ), is derived. Binetfs formula defines any term of the Tribonacci sequence as a function of the index of the term and three constants, p, a, and T. 2. .6inet's Formula for the Tribonacci Sequence Binetfs formula is derived by determining the generating function for the difference equation Un + 1 = Un + Un-1 + Un-2 n t 2' 00 Let f(x) = u0 + u-^x'+ u2x2 + ••• + unxn 4 - • -• • = £ uix% be the generating function; then • £-o ( 1 - x - x2 - x3)f(x) = 1, so f( V = 1 _ 1 = 1 nX) i ^ . ^2 _ ^3 (1 - PE)(1 " OX) (1 - TX) P(X)' 118 [May 1982] BINET'S FORMULA FOR THE TRIBONACCI SEQUENCE 119 The roots of p(x) = 0 are 1/p, 1 / c r , and 1/T, where p, a, and x are the roots of p(:~) = ^ 3 " ^ 2 - - 1 = 0, Applying CardanTs formulas to pi — 1 = 0 yields P = j(^19 + 3/33" + s/l9 - 3/33" + l), a = |(j> - ^19 + 3/33 - ^19 - 3/33" + V3i .^19 +"3/33" - > 1 9 - 3/33"])5 and T = a, the complex conjugate of a. Approximate numerical values for p, a, and " a are: p = 1.8393, a = -0.4196 + 0.6063i, a = -0.4196 - 0.6063^. Since the roots of p(x) = 0 are distinct, by partial fractions fW = — — = i _ ^ + i _ ^ + ,. ^ \ / 1 ^ w i - \ 1 - p a ; 1 - e r a 1 - ox' (1 - px)(l - osc)(l - ax) Here A '~ - P~ and Consequently, ( • • ( ' • 1 - f )(• • 1 - 1 ) P/ - 1 ) a / (P -(a -- a)(p • -. a2 - P)(a • a2 - a)' - a) ! (>-§)('-§) . © - p ) f f - « ' , 2 oo 9 /Or) = ^ — £p^ + — 2 a i ^ + - z : ^~z Eav . .
.
. (p - a)(p - a)^ = o (a - p)(a - a)^ = °, , ( a - p ) ( a - a f = 0 i = 0 (p - a)(p - a) (a - p) (a - a) (a - p)(a - a) Thus, BinetTs formula for the Tribonacci sequence is pn+2 ^ an+2 _ , _ a n + 2 u - tL + + (p - a)(p - a) (a - p)(a - a) (a - p)(a - a) 120 BINET'S FORMULA FOR THE TRIBONACCI SEQUENCE [May 1982] Multiplying the numerators and denominators of the last two terms by (p - a) and (p - a), respectively, yields „.-^eHi- + (P-a)a"+2 + ( p - a ) a " + 2 , |p - a|2 -2£J(a)|p - a\2 2iJ(a)|p - a|2 Using the relations O = p(cos 0 + i sin 6), 0n - rn(.cos n Q + i sin n 0), e = tan1 (l(a)/i?(a)) and combining terms: p2 M , r(r - 2p cos 6) „ n u„ = - p n + — — P n cos n 0 I 1 2 I 1 2 I p - a J I p - a I , r2 cos 0 - pr(l - 2 sin2 0) „ s m 0 p - a 3?" s m n 2 Denoting the coefficients of pn, r n cos n 09 and vn sin n 0 by a, 3, and y, respectively, yields un = apn + rn((3 cos n 0 + y sin n 0). Approximate values for the constants are: p = 1.8393, 0=124.69° , r = 0.7374, a = 0.6184, 3 = 0.3816, y = 0.0374. 3. An Application Since \r\ = .7374 < 1, the nth Tribonacci number is the integer nearest apn when |pn(3 cos n 0 + y sin n 0) | < -y . Using calculus, the value of |$ cos n 0 + y sin n 0| is at a maximum when n0 = 5.60° + &TT, for fe an integer. Consequently, |pn(3 cos n 0 + y sin n 0| < — for n > 1, Since [a + .5] = 1 (where [ ] is the greatest integer function), a short form of the formula that is suitable for calculating the terms of the Tribonacci sequence is un = [apn + .5] for n >_ 0. References 1. Vorobev, N. The Fibonacci Numbers. Boston: Heath, 1963, pp. 12-15. 2. Feinberg, Mark. "Fibonacci-Tribonacci." The Fibonacci Quarterly 1, no. 1 (1963):71-74. |
12518 | https://www.ck12.org/flexi/algebra-ii/understand-quadratic-functions/lesspgreaterfind-the-x-value-of-the-axis-of-symmetry-instructions-given-the-quadratic-function-find-the-x-value-of-the-vertex-(axis-of-symmetry)-lessmathgreatery-x2-plus-4x-8less-by-mathgreater-less-by-pgreater/ | Flexi answers - Find the x-value of the axis of symmetry. Instructions: Given the quadratic function, find the x-value of the vertex (axis of symmetry). @$\begin{align}y = x^2 + 4x - 8\end{align}@$. | CK-12 Foundation
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Find the x-value of the axis of symmetry. Instructions: Given the quadratic function, find the x-value of the vertex (axis of symmetry). y=x 2+4 x−8.
Flexi Says:
The x-value of the vertex (or the axis of symmetry) for a quadratic function in the form y=a x 2+b x+c is given by the formula x=−b 2 a.
In the given function y=x 2+4 x−8, a=1 and b=4.
Substituting these values into the formula, we get:
x=−4 2∗1
@$\begin{align}x = -2\end{align}@$
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12519 | https://byjus.com/free-cat-prep/escalator-questions-for-cat/ | In CAT, Time, Speed and Distance (TSD) is an important topic in the Quantitative Aptitude (QA) section. Escalator problems are quite common from the TSD topic. CAT escalator problems are similar to “upstream” and “downstream” problems. In a stream, the direction of the flow of water is constant, whereas the escalators move in both directions. Escalator questions can be confusing as questions might not explicitly reveal the direction in which the escalator is moving. Please refer BYJU’S CAT College Predictor tool.
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In CAT, escalator questions are often repeated and sometimes give a tough time to the candidates. In this article, the escalator questions are explained in detail, along with solved examples, to help the CAT aspirants prepare more effectively. By being able to solve the escalator questions, candidates can easily score well in the CAT Quantitative Aptitude section.
Escalator questions can be categorised as the following:
It should also be noted that escalator questions might include two different cases, i.e. when 1 person is moving and when 2 persons are moving.
Let’s look at some of the escalator questions, which will help you solve the same kind of questions:
Q1. Ramu takes 40 seconds to walk upon an upward-moving escalator, but he takes 60 seconds to walk upon a downward-moving escalator. Calculate the time that Ramu will take to walk up if the escalator is not moving.
Ans. 48 seconds
Solution:
This question resembles the boats and streams questions a lot. It can be solved using the same concept.
Assume the speed of Ramu as “x” and the speed of the escalator as “y”.
Case 1: Escalator is moving upwards
In this case, Ramu’s effective speed will be = x + y
Case 2: Escalator is moving downwards
In this case, Ramu’s effective speed will be = x- y
Case 3: Escalator is not moving
At this time, Ramu’s speed will simply be his actual speed, i.e. x
Shortcut Method:
As the distance is constant, the three speeds, i.e., x + y, x, x – y, will be in arithmetic progression. Now, since time is inversely proportional to speed, the time taken in each case will be in harmonic progression.
So, calculating the harmonic mean of the given time taken will give the time taken by Ramu to walk up if the escalator is not moving, i.e., (2 40 60)/ (40 + 60).
So, the answer will be 48 seconds.
Alternative Method:
No. of steps (for case 1) = 40x + 40y—————–Eq. 1
No. of steps (for case 2) = 60x + 60y—————–Eq. 2
Now, equating both these equations,
=> x = 5y.
Putting this in Eq. 1,
No. of steps = 48x.
Now, the time taken for Ramu to walk up when the escalator is stationary = 48x/x = 48 seconds.
Q2. When Ramu walks down, he takes 1 minute on an escalator that is moving down, but he takes 40 seconds when he runs down. He takes 20 steps when he is walking, whereas he takes 30 steps when he is running. Calculate the total number of steps in the escalator.
Ans. 50 Steps
Solution:
Assume the speed of the escalator to be “a” steps per second.
As it is an escalator, the distance covered by Ramu will always be the same whether he is running or walking.
Case 1:
Distance when Ramu is walking = 20 + 60a———–Eq. 1
Here, 60a is covered by the escalator.
Case 2:
Distance when Ramu is running = 30 + 40a———–Eq. 2
Again, 40a is the distance covered by the escalator.
Now, equating both equations, the obtained equation is:
20 + 60a = 30 + 40a
=> a = 0.5
So, the total number of steps will be = 20 + 60 (0.5) = 50 steps.
Q3. Suresh and Mukesh are walking up on an upward-moving escalator. It took 60 steps for Suresh to reach the top, whereas Mukesh took 64 steps. While moving up, Mukesh took 4 steps for every 3 steps Suresh took. What was the total number of steps in that escalator?
Ans. 80 Steps
Solution:
As the ratio of their speeds is given, assume Suresh’s speed = 3x and Mukesh’s speed = 4x
Also, let the escalator’s speed = y steps per second.
Case 1:
When Suresh took 60 steps, the escalator had moved 60y/ 3x
So, the total number of steps = 60 + 60y / 3x————Eq. 1
Case 2:
When Mukesh took 64 steps, the escalator had moved 60y/ 4x
So, the total number of steps = 64 + 64y / 3x————Eq. 2
Equating both equations, it is obtained that, y = x
Now by putting this value in any of the equations, the total number of steps can be calculated.
So, the total number of steps = 64 + 16 = 80 steps.
Q4. A man can walk up a moving ‘up’ escalator in 30s. The same man can walk down this moving ‘up’ escalator in 90s. Assume that his walking speed is the same upwards and downwards. How much time will he take to walk up the escalator when it’s not moving?
Ans. 45 seconds
Solution:
The times taken ‘with’ and ‘against’ the escalator are in the ratio 1:3. Therefore, the steps thrown out of the escalator are also in the ratio 1:3.
Also, the number of stairs that he climbs on his own will also be in the ratio 1:3. Therefore, let the stairs he climbs be L and 3L, and the steps produced by the escalator be x and 3x.
Hence, L + x = 3L – 3x or L = 2x or x = L/2, total steps = L + L/2 = 3L/2. Now, the time taken for L is 30s; therefore, the time taken for 3L/2 will be 45s.
Q5. On an upward-moving escalator, Amar, Akbar and Anthony take 10 steps, 8 steps, and 5 steps, respectively, to reach the top. On the same upward-moving escalator, Amar takes 30 steps to come down from the top. Find the ratio of the time taken by Akbar and Anthony to reach the top.
Ans. 7:10
Solution:
The time taken by Amar to climb down 30 steps would be thrice the time taken to climb 10 steps. Therefore, if x is the number of steps thrown by the escalator when Amar climbs 10 steps, 3x would be the number of steps thrown by the escalator when he climbs 30 steps. The total number of stairs is the same.
Therefore, 30 – 3x = 10 + x or x = 5. So, the total number of steps = 10 + 5 = 15. For Akbar and Anthony, the steps given out by the escalator are 15 – 8 = 7 and 15 – 5 = 10. Therefore, the ratio of their time = 7: 10
The above given are some of the basic concepts of escalator questions that can help candidates to tackle the related questions effectively in the exam. CAT aspirants can also checkquantitative aptitude questions for CAT to practise different variations of questions from the different CAT topics.
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12520 | https://pmc.ncbi.nlm.nih.gov/articles/PMC7345503/ | Beta-Lactam Sensitive Bacteria Can Acquire ESBL-Resistance via Conjugation after Long-Term Exposure to Lethal Antibiotic Concentration - PMC
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. 2020 Jun 2;9(6):296. doi: 10.3390/antibiotics9060296
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Beta-Lactam Sensitive Bacteria Can Acquire ESBL-Resistance via Conjugation after Long-Term Exposure to Lethal Antibiotic Concentration
Pilvi Ruotsalainen
Pilvi Ruotsalainen
1 Nanoscience Center, Department of Biological and Environmental Science, University of Jyväskylä, P.O. Box 35, FI-40014 Jyväskylä, Finland; pilvi.ruotsalainen@gmail.com (P.R.); cindy.j.given@jyu.fi (C.G.); reetta.k.penttinen@jyu.fi (R.P.)
Find articles by Pilvi Ruotsalainen
1, Cindy Given
Cindy Given
1 Nanoscience Center, Department of Biological and Environmental Science, University of Jyväskylä, P.O. Box 35, FI-40014 Jyväskylä, Finland; pilvi.ruotsalainen@gmail.com (P.R.); cindy.j.given@jyu.fi (C.G.); reetta.k.penttinen@jyu.fi (R.P.)
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1, Reetta Penttinen
Reetta Penttinen
1 Nanoscience Center, Department of Biological and Environmental Science, University of Jyväskylä, P.O. Box 35, FI-40014 Jyväskylä, Finland; pilvi.ruotsalainen@gmail.com (P.R.); cindy.j.given@jyu.fi (C.G.); reetta.k.penttinen@jyu.fi (R.P.)
2 Faculty of Science and Engineering, Department of Biology, University of Turku, FI-20014 Turku, Finland
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1,2, Matti Jalasvuori
Matti Jalasvuori
1 Nanoscience Center, Department of Biological and Environmental Science, University of Jyväskylä, P.O. Box 35, FI-40014 Jyväskylä, Finland; pilvi.ruotsalainen@gmail.com (P.R.); cindy.j.given@jyu.fi (C.G.); reetta.k.penttinen@jyu.fi (R.P.)
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1,
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1 Nanoscience Center, Department of Biological and Environmental Science, University of Jyväskylä, P.O. Box 35, FI-40014 Jyväskylä, Finland; pilvi.ruotsalainen@gmail.com (P.R.); cindy.j.given@jyu.fi (C.G.); reetta.k.penttinen@jyu.fi (R.P.)
2 Faculty of Science and Engineering, Department of Biology, University of Turku, FI-20014 Turku, Finland
Correspondence: matti.jalasvuori@jyu.fi; Tel.: +358-50-413-509-2
Received 2020 Feb 18; Accepted 2020 May 27; Collection date 2020 Jun.
© 2020 by the authors.
Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (
PMC Copyright notice
PMCID: PMC7345503 PMID: 32498393
Abstract
Beta-lactams are commonly used antibiotics that prevent cell-wall biosynthesis. Beta-lactam sensitive bacteria can acquire conjugative resistance elements and hence become resistant even after being exposed to lethal (above minimum inhibitory) antibiotic concentrations. Here we show that neither the length of antibiotic exposure (1 to 16 h) nor the beta-lactam type (penam or cephem) have a major impact on the rescue of sensitive bacteria. We demonstrate that an evolutionary rescue can occur between different clinically relevant bacterial species (Klebsiella pneumoniae and Escherichia coli) by plasmids that are commonly associated with extended-spectrum beta-lactamase (ESBL) positive hospital isolates. As such, it is possible that this resistance dynamic may play a role in failing antibiotic therapies in those cases where resistant bacteria may readily migrate into the proximity of sensitive pathogens. Furthermore, we engineered a Clustered Regularly Interspaced Short Palindromic Repeat (CRISPR)-plasmid to encode a guiding CRISPR-RNA against the migrating ESBL-plasmid. By introducing this plasmid into the sensitive bacterium, the frequency of the evolutionarily rescued bacteria decreased by several orders of magnitude. As such, engineering pathogens during antibiotic treatment may provide ways to prevent ESBL-plasmid dispersal and hence resistance evolution.
Keywords: antibiotic resistance, Extended-spectrum beta-lactamase, evolutionary rescue, conjugative plasmid
1. Introduction
Resistance to antibiotics forms a notable burden to health care. While the evolution of resistance may appear as a seemingly simple evolutionary process, i.e., exposure to antibiotics selects for resistant mutants , the actual emergence of new resistant pathogens and the maintenance of resistance may be a result of relatively complex interbacterial interactions . This is especially relevant for horizontally transferred resistance genes that reside in conjugative plasmids .
β-lactams are antibiotics that inhibit the synthesis of the bacterial cell wall. Given their minimal side effects in humans, they are one of the most widely applied antibiotics in clinical care . Respectively, extended-spectrum β-lactamases (ESBLs) are enzymes that can hydrolyze and hence inactivate a wide range of different β-lactams . Notably, the presence of ESBL-producing bacteria allows sensitive “cheaters” to survive in a shared environment even in lethal antibiotic concentrations [6,7]. Resistant bacteria may be a part of the commensal flora and pose no threat in itself, therefore the resistance profile of the pathogen may not necessarily determine whether or not the applied antibiotic is effective [7,8,9]. This is troublesome since ESBL-carriage, i.e., the asymptomatic colonization of the gut by ESBL bacteria, has been continuously increasing both in hospital settings and in the community . As such, a more complete understanding of the evolutionary dynamics of resistances during antibiotic treatment would help us to more accurately evaluate the potential risks that may be incurred from the carriage of resistant strains.
Sensitive bacteria may acquire resistance via horizontal gene transfer (HGT) even after being exposed to lethal beta-lactam concentrations [7,11]. The physiological factors affecting the efficacy of β-lactams are currently being studied by numerous groups and can include cell-wall-lacking spheroplasts and dormant persisters [12,13]. Nevertheless, for ESBL-carriers, the evolutionary rescue may form an additional threat as the treatment of initially sensitive Gram-negative pathogens can be nullified by an accidental transfer of an ESBL-plasmid harboring bacterium from the gut flora to the site of infection.
There is variability in the potential for different conjugative plasmids with various Inc. (incompatibility)-groups and ESBL-genes to rescue susceptible bacteria . It is also dependent on the antibiotic concentration and resource availability. Rescue may occur even in antibiotic levels that exceed the minimum inhibitory concentrations by an order of magnitude, therefore the increase in dosage does not seem to provide a straightforward solution to prevent the transfer . Furthermore, sensitive bacteria will survive and become resistant when the resistant bacteria are subsequently introduced into their environment [7,11]). However, several factors potentially affecting the rescue have not been studied yet. Namely, it is unclear what the time-window is in which the transfer of an ESBL-plasmid from a harmless bacterium may still restore the growth of the sensitive pathogen, what the effect of different types of β-lactams is, whether the prevailing temperature (and hence bacterial metabolic rate) plays a part, and/or whether the species of the sensitive pathogen is relevant to the rescue. Here, we investigate how these factors affect the evolutionary rescue via a conjugative ESBL-plasmid of clinical origin. Understanding the role of these factors assists in determining how and when the ESBL-carriage status needs to be taken into account.
2. Results and Discussion
In this study, we selected a previously characterized plasmid pEC13 to investigate the evolutionary rescue in lethal β-lactam concentrations. pEC13 is a 71 kb conjugative IncFII-type plasmid, which originates from a patient-derived ESBL Escherichia coli (Figure 1; ) and carries a commonly circulating ESBL-resistance gene, blaCTX-M-14 . The majority of the pEC13-like plasmids in databases have been isolated from E. coli. Yet, there are multiple closely related plasmid sequences also in Klebsiella pneumoniae, Salmonella enterica, Citrobacter sp., Shigella sonnei and Shigella flexneri hosts, indicating that these plasmids may serve as potential agents mediating the interspecific resistance exchange.
Figure 1.
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Plasmid map of conjugative pEC13. The predicted coding regions are marked in grey. Regions involved in the conjugation (blue), replication (green) and antibiotic resistance (orange) are marked.
While pEC13 carries a single resistance gene and hence only provides resistance to non-carbapenem β-lactams, the highest similarity to pEC13 (for the matching regions) was with a K. pneumoniae plasmid pA1705-NDM (99.85%, GenBank id MH909349) encoding NDM-1, OXA-1 and CTX-M-14 β-lactamases (where NDM-1 is also able to hydrolyse carbapenems) along with resistances to fluoroquinolone, aminoglycoside, phenicol, rifampicin, sulphonamide, and tetracycline. As such, related plasmids can also confer resistances to multiple types of antibiotics. Plasmids such as pA1705-NDM may be of notable clinical relevance given that evolutionary rescue may also nullify any subsequent treatment attempts with alternative antibiotics once the initial failure occurs with β-lactams. PA1705-NDM plasmid, however, is over three times the length of pEC13. This genomic expansion appears to be due to the accumulation of several mobile elements and resistance cassettes in the plasmid backbone, and hence a direct comparison with the resistance dynamics observed for pEC13 in this study should be made with caution. Still, other similar plasmids in other species appear to have retained their size as well as gene and operon synteny with pEC13 (Figure 2), and therefore pEC13 appears to provide a relevant proxy for ESBL-plasmids that may disperse between different species of Enterobacteriaceae during the exposure to β-lactams.
Figure 2.
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Comparison of pEC13 to related plasmids in other Enterobacteriaceae. The genetic regions are color-coded according to their predicted function (the exact gene contents within the regions vary between plasmids). Plasmids with relatively similar genetic contents and synteny to pEC13 are present in various bacterial species, hence the interspecific evolutionary rescue via horizontal gene transfer.
We examined the transfer of pEC13 between two E. coli strains, as well as between E. coli and K. pneumoniae. Ampicillin or cephalothin sensitive E. coli and cephalothin sensitive K. pneumoniae strains were exposed to lethal antibiotic concentrations (50 μg/mL) for 1, 6, and 16 h before resistant E. coli harboring pEC13 plasmid was introduced into the environment (Figure 3A,B). New resistant bacteria emerged in all treatments (see Table S1). The number of evolutionarily rescued E. coli decreased with ampicillin and cephalothin in relation to longer exposure periods (Figure 3A; Table S2); a statistical difference was observed between 1 h exposure to antibiotics compared to 6 h and between 1 and 16 h (Tukey HSD, p< 0.001), but not between 6 and 16 h (Tukey HSD, p = 0.76). In K. pneumoniae, the exposure time had no effect on the evolutionary rescue (p = 0.47; Figure 3B; Table S3). The antibiotic type used had no significant effect on the evolutionary rescue of E. coli (p = 0.055). However, given the notable variance in some measurements, the statistical significance needs to be taken cautiously. Nevertheless, both strains were able to acquire pEC13 even after 16 h and become completely resistant to these antibiotics. The possibility that the result may be due to spontaneous rifampicin-resistant pEC13 donors was ruled out by testing the chloramphenicol resistance of the rescued bacteria, as only the pEC13 donor carried a non-mobilizable chloramphenicol resistance conferring plasmid pSU19. Furthermore, we observed that the viable E. coli could be isolated after one hour antibiotic exposure even when no donor was introduced. This suggests that cell-wall-lacking spheroplasts or otherwise antibiotic-withstanding phenotypes [15,16]. may persist in the presence of the tested antibiotics and still acquire the conjugative plasmid as the opportunity occurs. The media used (LB -broth) is slightly hypotonic (85.5 mM) compared to isotonic media with the molarity of physiological saline (154 mM), probably allowing the bacteria to retain osmotic stability. Bacteria are generally able to tolerate slight changes in the osmolarity of the environment even in the absence of a supporting cell-wall by adjusting their metabolism through pressure-sensitive ion channels and by regulating their fatty acid synthesis to maintain lipid membranes .
Figure 3.
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Evolutionary rescue of Escherichia coli and Klebsiella pneumoniae after differing exposure times and at different temperatures. The big dots represent the evolutionary rescue presented as the mean cell density in colony forming units (cfu)/mL of formed transconjugants after the exposure to either ampicillin (50 µg/mL) or cephalothin (50 µg/mL) and the introduction of a rescuing strain harboring beta-lactamase resistance gene against these antibiotics in conjugative plasmid pEC13. The small dots represent individual data points per treatment. For reference, the number of transconjugants in the absence of antibiotics was measured at the 1 h time point. Statistical analysis and standard deviations are presented in Table S1. Letters indicate the results from Tukey’s “Honest Significant Difference” test. Groups indicated by the same letter do not differ significantly. Different exposure times to antibiotics were tested for (A) Escherichia coli and (B) Klebsiella pneumoniae. (C) The effect of temperature (37, 22 or 4 °C) on the evolutionary rescue of E. coli was measured after 16 h exposure to ampicillin and cephalothin.
The prevailing temperature has a substantial effect on the rate at which bacteria replicate. Given that replication itself is dependent on the generation of new cell walls, it is possible that lower temperatures hinder the efficacy of cell-wall-targeting antibiotics and thus allow more bacteria to acquire the plasmid. As such, we tested whether temperature has an effect to bacterial survival via evolutionary rescue in the presence of antibiotics. E. coli was exposed to cephalothin and ampicillin at 4 °C, room temperature (22 °C), and 37 °C for 16 h before the introduction of the pEC13-harboring strain (Figure 3C; Table S4). We found no significant difference in the rescued cells between cephalothin and ampicillin (p = 0.055; Table S5), nor the temperatures used (p = 0.56; Table S5). Nevertheless, this suggests that the persisting cells are already present in the population before the exposure to antibiotics. As such, the migration of bacteria harboring conjugative resistance plasmids can also rescue susceptible bacteria in the environmental reservoirs and hospital areas that contain notable beta-lactam pollution but where bacterial growth may be reduced. Qualitatively, the results show that a rescue can occur even after 16 h exposure to commonly used antibiotics, between different bacterial species, and within a wide temperature regime.
We studied whether the evolutionary rescue of the sensitive bacteria may be prevented by introducing them to a CRISPR-Cas9 plasmid that targets the β-lactamase gene of pEC13. In other words, the incoming pEC13 should be degraded by Cas9 in the persisting clones that remain viable in the presence of the antibiotics. We first ensured that pEC13 is not able to mobilize the CRISPR plasmid by aligning the OriT and OriR sequences from pEC13 with pCas9-plasmid and establishing that they are absent in pCas9-gRNA. Indeed, the presence of a CRISPR-plasmid significantly reduced the number of transconjugants on the double-antibiotic (chloramphenicol and ampicillin) plates by at least four orders of magnitude after 2 h exposure to ampicillin (Table 1). This at least reveals the possibility that potential pathogens would be less likely to acquire resistances if they were, in one way or another, introduced to β-lactamase targeting CRISPR-elements before or simultaneously with an antibiotic treatment. Hypothetically, bacteriophages could serve as an imaginable way to deliver CRISPR-systems to bacteria, e.g., in infected wounds . Alternatively, conjugative plasmids can be engineered to transfer CRISPR-systems and hence utilized within probiotic strains to prophylactically limit the abundance of ESBL-plasmids in gut flora, and therefore the rescue events from taking place.
Table 1.
The evolutionary rescue of CRISPR-plasmid harboring antibiotic susceptible E. coli.
| Beta-Lactam Susceptible Strain | Replicate | Survivors (cfu/mL) |
:---:
| | 1 | <200 |
| E. coli DH5α (pCas9-gRNA) | 2 | <200 |
| | 3 | <200 |
| | 1 | 1.52 × 10 6 |
| E. coli DH5α (pCas9-CTRL) | 2 | 1.76 × 10 6 |
| | 3 | 2.12 × 10 6 |
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To conclude, evolutionary rescue by horizontal gene transfer is an event where susceptible bacteria may become resistant to antibiotics ‘on the fly’ after the beginning of the treatment. Here we demonstrate that the rescue of susceptible E. coli and K. pneumoniae strains may occur even after 16 h exposure to both ampicillin and cephalothin. The applicability of this observation to real life systems must be taken cautiously. Yet, it is possible that if any suspected pathogen is determined to be sensitive to β-lactams, the protection of the infected site from the migration of (even harmless) ESBL-bacteria may be crucial for the treatment outcome. Preventive measurements that block plasmid-conjugation and/or maintenance [2,3,14] or nick resistance genes (such as the aforementioned CRISPR-systems) are still in the very early stage of development for constraining evolutionary rescue and/or ESBL-carriage but may be worth considering in the future.
3. Materials and Methods
3.1. Bioinformatic Analyses
To explore the prevalence of pEC13-like plasmids, highly similar matches were searched with a NCBI BLAST Megablast-search using a nucleotide collection database (nr/nt) with a Max E-value of 10, a word size of 28, a and scoring (Match Mismatch) of 1–2. The search was performed with Geneious 11.1.5 (Biomatters Ltd.; Auckland, New Zealand). The conserved gene clusters, their arrangement, and orientation were studied for the plasmid matches from various Enterobacteriaceae species with a grade of 70% or above (a total of 40 plasmids of which six non-E. coli plasmids are presented in the study) using a whole genome alignment tool with a progressive Mauve algorithm with default settings . To ensure that the pCas9-gRNA plasmid is not transmissible by pEC13, oriTFinder was used to detect the origin of the transfer (OriT) region from pEC13. The origin of the replication (OriR) region of pEC13 was identified with Ori-Finder 2 .
3.2. Evolutionary Rescue Experiments
Conjugation assays were performed to study the impact of a delayed introduction of an ESBL-resistant donor to a culture of antibiotic sensitive bacteria under a lethal antibiotic concentration. As a conjugative plasmid, we used pEC13, IncFII plasmid encoding CTX-M-14 β-lactamase , GenBank id KU932024.1). Escherichia coli K-12 JM109(pEC13)(pSU19) was used as a donor for two different recipients: Escherichia coli K-12 HMS174 and Klebsiella pneumoniae DSM681 AmpR,RifR. DSM681 carries a gene for SHV-1 beta-lactamase, which makes the strain resistant to ampicillin, but not cephalothin. The DSM681 (or ATCC 10031) genome sequence is available at genomes.atcc.org for registered users. No other beta-lactamase genes are present in the DSM681 genome as determined with ResFinder-3.2 . We also tested the conjugation of pEC13 from E. coli to a rifampicin resistant mutant of Salmonella enterica serovar Typhimurium SL5676, but no transconjugants were observed and hence it was omitted from further experiments.
The donor and recipient strains were grown to a carrying capacity in overnight culture (37 °C, 220 rpm) in a Luria Bertani Lennox-broth (LB; Lennox 1955) with an appropriate antibiotic selection: donor in 150 µg/mL ampicillin and recipients in 50 µg/mL rifampicin. The cell density of overnight cultures was determined by serial dilutions plated on 1% LB agar plates and incubated overnight at 37 °C. Approximately 5.5 × 10 6 and 7.25 × 10 6 colony forming units (CFU) of sensitive recipient bacteria, HMS174 and DSM681, respectively, were first introduced to 5 mL of LB-broth supplemented with either 50 µg/mL of ampicillin or cephalothin. In a previous study, this concentration was shown to be clearly above MIC, as 15 µg/mL was already lethal to the same strains used here . DSM681 was exposed only to cephalothin due to its chromosomal resistance to ampicillin. After different exposure times (1, 6, and 16 h) at 37 °C, the donor bacteria (4.1 × 10 6 CFU) were added to the culture. These time points provide an estimate as to whether the protection of the sensitive bacterium from the migration of resistant bacteria early on after antibiotic administration can have an effect. As a control treatment, this assay was also done without antibiotic selection for the 1-h time point. This ‘no-antibiotics’ assay represents just the plasmid conjugation and hence not the evolutionary rescue. For the HMS174 recipient, two additional temperatures (4 and 22 °C) for the 16 h timepoint were examined. Each assay was performed at a minimum in triplicates. After the introduction of the resistant ESBL-donor, the co-culture was incubated overnight (37 °C, 220 rpm), after which the number of transconjugants was determined by plating on 1% LB-agar plates with the appropriate antibiotics: rifampicin (50 µg/mL) and either ampicillin 150 µg/mL (for HMS174) or cephalothin 50 µg/mL (for DSM681). Before the introduction of the donor, a 500 µL sample was taken from the 16 h exposure experiments to determine the presence of surviving bacteria. The sample was pelleted by centrifugation (8000 rpm, 8 min), the supernatant was removed carefully, and the pellet was resuspended in 100 µL of sterile water before being plated on the LB-agar without antibiotics. The presence of the surviving bacteria was quantified by observing the colonies on the plates after overnight cultivation at 37 °C.
We also evaluated the efficacy of CRISPR-Cas9-encoding plasmid to prevent an evolutionary rescue via horizontal gene transfer. The CRISPR-plasmid used (pCas9-gRNA) targets a conserved region in the bla CTX-M-14 gene with the spacer sequence CCGCTGGTTCTGGTGACCTATTT (described in detail in Ruotsalainen et al., 2019). The original pCas9 plasmid was a gift from Luciano Marraffini (Addgene plasmid #42876) and confers resistance to chloramphenicol. As a control, we used the same plasmid without the targeting spacer (pCas9-CTRL). These plasmids were transformed into E. coli DH5α strains by electroporation. HMS174 (pEC13) was used as a donor for the rescue experiments. A total of 5 µL of overnight grown DH5α (pCas9-gRNA) and DH5α (pCas9-CTRL) were exposed to 50 µg/mL ampicillin in 5 mL of LB-medium in 37 °C for 2 h before adding 5 µL of HMS174(pEC13). This combination was cultivated for 16 h (37 °C, 220 rpm) and plated on LB-agar with ampicillin (450 µg/mL) and chloramphenicol (75 µg/mL). Increased antibiotic concentrations were used in order to inhibit the appearance of false positive rescued colonies emerging in the plating of higher bacterial densities.
3.3. Statistical Analyses
To determine the effect of the selected antibiotics and the temperature on the evolutionary rescue of antibiotic sensitive bacteria, a two-way between-groups analysis of variance (ANOVA) with Tukey HSD as post-hoc comparisons was conducted using RStudio Cloud service. Three treatments were regarded in the analysis: the type of β-lactams antibiotics, time points, and temperatures.
4. Conclusions
Dispersal of antibiotic resistance genes plays a notable part in the emerging resistance crisis. ESBL-genes often reside in conjugative plasmids and may spread interspecifically between bacteria. Here, we show that antibiotic susceptible E. coli and K. pneumoniae exposed to inhibitory concentrations of beta-lactam antibiotics cephalotin and ampicillin for several hours can still become resistant by acquiring a conjugative plasmid from migrating resistant bacteria.
Supplementary Materials
The following are available online at Table S1: Descriptive statistics on the evolutionary rescue of E. coli and K. pneumoniae under different β-lactams (50 µg/mL ampicillin and 50 µg/mL cephalothin) and exposure time (1 h, 6 h, and 16 h). Table S2: Analysis of Variance, test effect of β-lactams (50 µg/mL ampicillin and 50 µg/mL cephalothin) and exposure time (1 h, 6 h, and 16 h) on the evolutionary rescue of E. coli., Table S3, Analysis of Variance, test effect of β-lactams (50 µg/mL ampicillin and 50 µg/mL cephalothin) and exposure time (1 h, 6 h, and 16 h) on the evolutionary rescue of K. pneumoniae. Table S4: Descriptive statistics on the evolutionary rescue of E. coli under different β-lactams (50 µg/mL ampicillin and 50 µg/mL cephalothin) and temperature (37 °C, 22 °C, and 4 °C), Table S5: Analysis of Variance, test effect of β-lactams (50 µg/mL ampicillin and 50 µg/mL cephalothin) and temperature (37 °C, 22 °C, and 4 °C) on the evolutionary rescue of E. coli.
Click here for additional data file. (699.8KB, pdf)
Author Contributions
Conceptualization, P.R., R.P. and M.J.; methodology, P.R., C.G., R.P. and M.J.; formal analysis, P.R., C.G. and M.J.; data curation, P.R., C.G. and R.P.; writing—original draft preparation, M.J.; writing—review and editing, P.R.; visualization, P.R., C.G. and R.P.; supervision, M.J.; funding acquisition, R.P and M.J. All authors have read and agreed to the published version of the manuscript.
Funding
This research was funded by the Academy of Finland (grants no.252411 and no. 297049 to MJ and no. 322204 to RP), Emil Aaltonen Foundation and Jane and Aatos Erkko Foundation.
Conflicts of Interest
The authors declare no conflict of interest.
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2. Results and Discussion
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Supplementary Materials
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12522 | https://www.reddit.com/r/MathHelp/comments/cue2qi/interval_notations_have_a_question_about_what_xx/ | Interval Notations. Have a question about what {x|x ≤ - 1} means when graphing. : r/MathHelp
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Interval Notations. Have a question about what {x|x ≤ - 1} means when graphing.
Not sure if this breaks the rules because of rule 5 and it's not a question of help for an equation. So I know how to graph the expression above ({x|x ≤ - 1} ). When I graph it I get this:
My question about this is {x|x ≤ - 1} specifically is does this just mean everything that is less than or equal to -1 for graphing? I assumed that it was which is why I graphed it like that. Because I thought it just meant (- ∞ ,-1] for interval notation.
Is that right or am I assuming incorrectly?
Edit:
Additionally, I assumed what it mean based off of x ≤ - 1 but what does {x| mean?
Edit 2:
Thank you all so much! It makes so much sense now!
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12523 | https://juejin.cn/post/7247058712195924024 | 力扣刷题：黑白翻转棋前言：锻炼自己的思想，规范自己的编程思路。 问题： 在 nm 大小的棋盘中，有黑白两种棋子，黑棋记 - 掘金
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力扣刷题：黑白翻转棋
是小刘
2023-06-21 338 阅读3分钟
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前言：锻炼自己的思想，规范自己的编程思路。
问题：
在 nm 大小的棋盘中，有黑白两种棋子，黑棋记作字母 "X", 白棋记作字母 "O"，空余位置记作 "."。当落下的棋子与其他相同颜色的棋子在行、列或对角线完全包围（中间不存在空白位置）另一种颜色的棋子，则可以翻转这些棋子的颜色。
「力扣挑战赛」黑白翻转棋项目中，将提供给选手一个未形成可翻转棋子的棋盘残局，其状态记作 chessboard。若下一步可放置一枚黑棋，请问选手最多能翻转多少枚白棋。
注意：
若翻转白棋成黑棋后，棋盘上仍存在可以翻转的白棋，将可以 继续 翻转白棋 输入数据保证初始棋盘状态无可以翻转的棋子且存在空余位置
示例：（放代码里面）
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```markdown
输入：chessboard = ["....X.","....X.","XOOO..","......","......"]
输出：3
解释：
可以选择下在 [2,4] 处，能够翻转白方三枚棋子。
```
思路：
函数先声明 m 和n获取棋盘的行数和列数 ，并初始化变量 s 为 0。变量 s 用于存储最多能翻转多少枚白棋。然后定义一个二维数组 d，表示八个方向。
接下来，定义了一个名为 BFS 的内部函数，用于在给定位置放置黑棋并计算能翻转多少枚白棋。这个函数接受两个参数sx 和 sy，表示黑棋的位置。
在BFS 函数中，首先创建一个副本G 来存储棋盘状态。然后创建一个队列 q 并将黑棋的位置加入队列。将黑棋放置在给定位置，并初始化变量 t 为 0。变量t 用于存储当前位置能翻转多少枚白棋。
然后进入循环，每次从队列中取出一个位置 [x, y]。对于每个方向，计算下一个位置 [xx, yy] 并检查是否在棋盘内且为白棋。如果是，则继续沿着当前方向搜索，并累加计数器k。如果找到了黑棋，则将计数器累加到变量t中，并将中间的白棋翻转为黑棋。
当队列为空时，循环结束。更新最大翻转数量 s = Math.max(s, t)。
最后，在主函数中遍历整个棋盘，对于每个空位，调用 BFS 函数计算能翻转多少枚白棋。最后返回最大翻转数量 s。
基于上述思考，代码如下：
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```js
/
@param {string[]} chessboard
@return {number}
/
var flipChess = function(chessboard) {
const m = chessboard.length;
const n = chessboard.length;
let s = 0;
const d = ;
function BFS(sx, sy) {
let G = chessboard.map(row => row.split(''));
let q = ;
G[sx][sy] = 'X';
let t = 0;
while (q.length) {
const [x, y] = q.shift();
for (let i = 0; i < 8; i++) {
const dx = d[i];
const dy = d[i];
let xx = x + dx;
let yy = y + dy;
let k = 0;
while (xx >= 0 && xx < m && yy >= 0 && yy < n && G[xx][yy] === 'O') {
xx += dx;
yy += dy;
k++;
}
if (xx >= 0 && xx < m && yy >= 0 && yy < n && G[xx][yy] === 'X') {
t += k;
while (k--) {
xx -= dx;
yy -= dy;
q.push([xx, yy]);
G[xx][yy] = 'X';
}
}
}
}
s = Math.max(s, t);
}
for (let i = 0; i < m; i++) {
for (let j = 0; j < n; j++) {
if (chessboard[i][j] === '.') {
BFS(i, j);
}
}
}
return s;
}
```
执行结果如下图：
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百度经验>生活/家居>生活常识
复合函数的周期怎么求
浏览：1647
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更新：2022-12-08 17:38
设y是u的函数y=f(u)，u是x的函数
如果的值全部或部分在f(u)的定义域内，则y通过u成为x的函数，记作
称为由函数y=f(u)与
复合而成的复合函数。
设y=f(u)的最小正周期为T₁,μ=φ(x)的最小正周期为T₂,则y=f(μ)的最小正周期为T₁T₂，任一周期可表示为kT₁T₂(k属于R+)。
扩展资料：
判断复合函数的单调性：
1、求复合函数的定义域；
2、将复合函数分解为若干个常见函数（一次、二次、幂、指、对函数）；
3、判断每个常见函数的单调性；
4、将中间变量的取值范围转化为自变量的取值范围；
5、求出复合函数的单调性。
参考资料来源：百度百科-复合函数
经验内容仅供参考，如果您需解决具体问题(尤其法律、医学等领域)，建议您详细咨询相关领域专业人士。
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12525 | http://s2.onmycalendar.com/Files/NE/A6RQ115266N_arithmeticsequencestasksDay2.pdf | 37, 35, 33, 31,…. a) Identify the common difference (d) b) Write the explicit formula c) Find the 26th term (a26) -34, -24, -14, -4,…. a) Identify the common difference (d) b) Write the explicit formula c) Find the 32nd term (a32) 10, 0, -10, -20,…. a) Identify the common difference (d) b) Write the explicit formula c) Find the 40th term (a40) 28, -2, -32, -62,…. a) Identify the common difference (d) b) Write the explicit formula c) Find the 18th term (a18) 3, 9, 15, 21,…. a) Identify the common difference (d) b) Write the explicit formula c) Find the 16th term (a16) 1, -29, -59, -89,…. a) Identify the common difference (d) b) Write the explicit formula c) Find the 26th term (a26) an = 8 – 9n a) Identify the common difference (d) b) Find the first 4 terms c) Find the 50th term (a50) an = 18 + 43n a) Identify the common difference (d) b) Find the first 4 terms c) Find the 29th term (a29) A case of the Zika virus was found in FL in 2 people. Each day 3 additional people were infected with the virus. a) Find the first three terms b) Write an explicit formula to represent this sequence. c) Find how many people will have the virus in 100 days (a100). ) )lskdj Mrs. Aikhuele created a Snapchat account and immediately had 10 followers. Her snaps are so funny, she gains an additional 6 followers each day. a) Find the first three terms b) Write an explicit formula to represent this sequence. c) Find how many followers she will have after 50 days (a50). Mrs. Neville has an overweight dog. Her dog started out at 87 lbs. He needs to lose 2 pounds a week to get healthy again. a) Find the first three terms b) Write an explicit formula to represent this sequence. c) Find how much her dog will weigh in 6 weeks. You really need some extra credit. Your grade in math is a 54. Mrs. Washington agreed give you 3 points of extra credit for each additional assignment you complete. a) Find the first three terms b) Write an explicit formula to represent this sequence. c) Find what your grade will be after 12 assignments ARITHMETIC SEQUENCES Task Cards! Objective: To practice finding the common difference of an arithmetic sequence, write a formula to represent an arithmetic sequence, and use a formula to solve for a specific value within the sequence. Real world problems are included. (MGSE9-12.F.BF.1a, 2) Directions: 1) Print, cut, and laminate the 12 task cards. Also, copy enough recording worksheets for each student. These are the ways I have run this activity: • Place a card at each station and have students move in groups of 3-4 from station to station after approximately 4 minutes. (This way you only have to copy one set of cards) • Students work in pairs and are given a card set. They work together to answer each card. You will need to print, cut, and laminate many sets. I typically prefer this because it leads to more one-on-one discussion. 2) Students complete each card, and record their answers on their recording worksheet. I require them to show work on a separate sheet of paper and staple to the recording worksheet. |
12526 | http://galileo.phys.virginia.edu/classes/311/notes/fluids1/node7.html | Next: Circulationvorticity, and vortices Up: The equation of continuity Previous: Incompressible flow
Streamlines and streamtubes
In problems involving electric or magnetic fields we visualize the fields by introducing field lines (often called lines of force), which have the properties that (1) they are everywhere tangent to the field vectors, and (2) the density of the field lines is proportional to the magnitude (strength) of the field. We can use the same method to visualize the velocity field by introducing streamlines, which have the following properties:
a tangent to a streamline at a point is in the direction of the fluid velocity at that point;
the density of streamlines in the vicinity of a point is proportional to the magnitude of the velocity at that point;
the streamlines cannot intersect except at a point of zero velocity, otherwise the velocity would not be uniquely determined at that point.
A streamtube is a tubular region of fluid surrounded by streamlines. Since streamlines don't intersect, the same streamlines pass through a streamtube at all points along its length. Let's take two cross-sections of a streamtube, with cross-sectional areas and (see Fig. 2.4).
Figure 2.4: A streamtube in a fluid.
If these areas are made small enough then the fluid velocities across the cross-sections will be constant; let's call the speeds and (the directions of the velocities being perpendicular to the cross-sections). The rate at which mass is entering the streamtube is ; the rate at which it is leaving is . If the mass inside the streamtube is not changing with time, so that the fluid is either incompressible or in steady-state, we have
If, in addition, the fluid is incompressible, then , and we have
so that the fluid speed increases when the cross-sectional area of the streamtube decreases. If this seems counter-intuitive, the following analogy might help. You drive down a four lane highway, and due to construction one lane on your side has been closed. The traffic crawls toward the point where the lane has been closed, with cars haphazardly merging into your lane. You finally hit the single lane, and whiz through the construction area. The cross-sectional area has decreased, and your speed has increased.
Next: Circulation and vortices Up: The equation of continuity Previous: Incompressible flow Vittorio Celli Mon Aug 11 22:46:35 EDT 1997 |
12527 | https://ojrd.biomedcentral.com/articles/10.1186/s13023-024-03115-y | Advertisement
Lymphangioleiomyomatosis in patients with tuberous sclerosis: a national centre audit
Orphanet Journal of Rare Diseases
volume 19, Article number: 137 (2024)
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Abstract
Background
Lymphangioleiomyomatosis (LAM) is common in tuberous sclerosis complex (TSC) yet under recognised with management mostly based upon evidence obtained from patients with sporadic LAM. We performed a prospective audit of patients with TSC-LAM attending a national referral centre to inform management guidelines.
Methods
The UK LAM Centre was established in 2011 and conducts a prospective audit of pre-defined quality outcomes for all subjects. Audit data are reported on all patients with TSC-LAM and a comparator population of patients with sporadic LAM.
Results
Between 2011 and 2022, 73 patients were seen with TSC-LAM. All were women with a mean (SD) age of 39 (12) years. Referral rates were similar over the study period including after the introduction of CT screening. Median age of diagnosis with TSC was 11 years (range 0–70) with one third diagnosed with TSC as adults. Compared with all TSC patients in the ‘TOSCA’ registry, TSC-LAM patients tended to have been diagnosed with TSC at an older age, had fewer neuro-cognitive manifestations and were more likely to have angiomyolipoma. The most common presentations of TSC-LAM were following workup for angiomyolipoma, pneumothorax or dyspnoea with only one fifth detected after CT screening. Baseline FEV1 and DLCO at first assessment were reduced to 77 and 63% predicted respectively and were similar to patients with sporadic LAM. During follow-up, FEV1 fell by a mean of 81 ml/year and DLCO fell by 0.309 mmol/ml/kPa/year in patients not being treated with an mTOR inhibitor. 55% required treatment with either sirolimus or Everolimus for LAM or angiomyolipoma respectively. For those treated with an mTOR inhibitor, mean FEV1 fell by 3 ml/year and DLCO increased by 0.032 mmol/ml/kPa/year and was similar to sporadic LAM. Risk of death due to LAM or need for lung transplant in patients with TSC-LAM was 0.67%/year.
Conclusions
Despite screening recommendations, LAM is often diagnosed in TSC after symptoms develop which may delay treatment. Complications including pneumothorax and loss of lung function are significant and similar to sporadic LAM. Work is needed to implement the recommended CT screening for LAM and improve respiratory care for TSC-LAM.
Introduction
Tuberous sclerosis complex (TSC) is an autosomal dominant genetic disorder which affects around 1 in 6000 live births . The disease is characterised by hamartomas in multiple organ systems, particularly the central nervous system, skin, heart, kidneys and lungs [23
.")]. The varying occurrence of TSC hamartomas can result in differing disease manifestations and severities even within families . Presentation is dependent upon the organ systems affected although the majority of patients present in infancy due to skin features, particularly hypomelanotic patches and angiofibromas or cerebral involvement causing epilepsy, intellectual impairment, autism and attention deficit hyperactivity disorder [4:243–54.
.")]. Disease features evolve with age, and angiomyolipoma, a benign tumour occurring mostly in the kidneys, tends to occur in adolescents and younger adults eventually affecting around 80% of patients [5:657–68.
.")]. Lymphangioleiomyomatosis (LAM) is a lung and lymphatic manifestation of TSC with an onset in younger adults, most commonly women which becomes more prevalent with increasing age [4:243–54.
.")]. LAM results in the accumulation of lung cysts and lymphatic abnormalities, progressively reducing lung function resulting in dyspnoea, pneumothorax, chylous collections and in some cases respiratory failure.
Until relatively recently LAM was thought to occur infrequently in TSC, considered of lesser importance and is still significantly under-diagnosed [61
.")]. However, systematic studies using CT scanning show that lung cysts consistent with LAM are present in half of women with TSC and 10–30% of men, with most women with TSC having some lung cysts by 40 years [7:591–4."),8:661–8."),9:1586–90.
.")]. For a minority of patients, often with milder cerebral manifestations, a diagnosis of TSC is delayed until adulthood after presentation with LAM or angiomyolipoma which may lead to significant morbidity, with recent large tertiary referral series suggesting that LAM is a leading cause of death among adult women with TSC [10:806–13.
."), 11:509–12.
.")].
LAM also occurs as a rare sporadic disease in the absence of TSC where somatic mutations in TSC2 are restricted to LAM cells
.")]. Sporadic LAM affects almost exclusively women with a prevalence of around 9/million women [13:971–9.
.")]. The lung and lymphatic phenotype of TSC and sporadic LAM are identical and additionally, angiomyolipoma also occur in half of patients with sporadic LAM, suggesting that sporadic LAM may represent mosaicism in TSC [14:1227–9.
."), 15:219–25.
.")]. TSC-LAM was previously thought to run a more indolent course than sporadic-LAM although analysis of patients matched for age and disease duration suggest the rates of loss of lung function are similar [16, 17:129–35.")]. Whilst the prevalence of TSC predicts that TSC-LAM should be more common than sporadic LAM, women with sporadic LAM make up the greater proportion of people receiving care at specialised LAM services [18:61.
."), 19:105–11.")]. Consequently, current management guidelines for LAM tend to be based on studies of patients with sporadic LAM. Since 2013, international TSC guidelines have recommended CT screening for LAM in women with TSC from 18 years [20:255–65.
.")]. As this is likely to identify more patients with TSC-LAM it is important to understand the clinical phenotype of these patients to both tailor treatment appropriately and ensure that LAM is detected early to minimise lung function loss. We therefore conducted an audit of patients with TSC-LAM referred to a national tertiary centre to understand how the clinical manifestations of TSC-LAM compared with sporadic LAM and how their TSC features compared with a wider group of TSC patients to aid recognition of LAM in TSC.
Methods
The audit was performed at the National Centre for lymphangioleiomyomatosis, at Nottingham University Hospitals NHS Trust, Nottingham UK. The Centre was established in 2011 as the single national centre to provide comprehensive clinical care for UK patients with LAM including TSC-LAM and is funded by NHS England highly specialised commissioning. When commissioned, pre-specified quality outcomes were defined to monitor centre performance including rate of lung function loss, rates of pneumothorax and angiomyolipoma haemorrhage, mTOR inhibitor use, lung transplant referrals and survival. These outcomes are subject to a prospective continuous audit and reported to NHS England.
All patients with TSC-LAM who were evaluated at the Centre between 2011 and 2022 were included. Patients with both sporadic and TSC-LAM undergo a comprehensive initial assessment as part of routine clinical care including a detailed history incorporating features of TSC, examination of the skin for signs of TSC, CT thorax, and cross-sectional imaging of the abdomen using CT or MRI. Lung function testing (FEV1 and DLCO) is performed according to current ATS/ERS standards [21T
.")] at a single laboratory by experienced technicians. Lung function measurements are not reported in cases where disability prevented reproducible results being obtained. Follow up visits are determined by clinical need at which clinical outcomes are recorded and FEV1 and DLCO are repeated.
A comparison group of patients with sporadic LAM evaluated at the UK LAM Centre and cared for in the same way but without TSC was also studied. This group comprised all 175 subjects with definite sporadic LAM evaluated over the same period. All subjects had baseline phenotype and lung function data and 152 had follow-up data. LAM was defined by ATS/JRS guidelines in both groups [22t
.")].
Clinical features of LAM and TSC were obtained from medical notes. Subjects were grouped by their main symptom at presentation categorised as one of dyspnoea, pneumothorax, haemoptysis, angiomyolipoma related, screened as part of TSC management, chance (when LAM is discovered during investigation of unrelated symptoms) or any other symptom. Subjects were also grouped according to the individual clinical manifestations of LAM, categorised as the presence of lymphatic involvement (chylous collections, lymphadenopathy or lymphatic masses), angiomyolipoma or pneumothorax. The need for intervention for angiomyolipoma (embolisation or any surgical procedure) and pneumothorax (any surgical intervention) are prespecified LAM Centre quality outcomes and were recorded for each patient.
Data were tested for normality using the Kolmogorov–Smirnov test and differences between means analysed using unpaired t-tests. The presence or absence of phenotypic traits within groups was compared using Fisher’s exact test. Change in lung function for individuals was calculated by the slope of a regression line of all values of FEV1 (ΔFEV1) or DLCO (ΔDLCO) stratified by the use of an mTOR inhibitor . Statistical analyses were performed using Excel (Microsoft corporation), with a p value of 0.05 accepted as significant.
Results
Seventy-five patients were seen at the UK LAM Centre for evaluation of TSC-LAM between 2011 and 2022. All were women and had a mean (SD) age of 39 (12) years at first assessment, 73 of these patients had LAM. A control cohort of patients with sporadic LAM seen at the same centre over the same period were used for comparison with the TSC-LAM cohort. The sporadic LAM cohort comprised 175 patients with definite LAM according to ATS/JRS criteria who were participating in the BioLAM observational research cohort. Sporadic LAM patients were all women, with a mean (SD) age of 47 (11) years at first assessment. The rate of referral to the service for patients with TSC-LAM was similar over the study period and did not change after the introduction of CT screening for LAM in 2013 (Fig. 1).
Referral rates of TSC and sporadic LAM cohorts. 2011 includes existing patients transferred to the LAM Centre
TSC related characteristics
The mean age of diagnosis with TSC was 17 years (median 11 years, range 0 to 70). One third of these patients were not diagnosed with TSC until adulthood including 12% after 40 years of age. Of these patients, a history of epilepsy was present in 51%, learning difficulty in 24%, TAND in 15% and SEGA in 11%. 95% of the cohort had one or more renal angiomyolipoma and 19% had renal cysts. LAM was present in all but two subjects (97%). Multifocal micronodular pneumocyte hyperplasia (MMPH) was present in 8% and co-existed with LAM in all cases. 19 patients had undergone TSC genotyping with 89% of these patients having a mutation in TSC2 (Table 1).
We compared the TSC-LAM patients evaluated at the LAM Centre with 2093 contemporaneous TSC patients currently receiving care for TSC from 31 countries recorded in the Tuberous Sclerosis registry to increase disease awareness (TOSCA) [245
.")]. Compared with patients registered in TOSCA, our cohort being evaluated for LAM tended to have been diagnosed with TSC at an older age, had a lower prevalence of neurological and cognitive manifestations, were more likely to have angiomyolipoma and more likely to have TSC2 mutations than TSC1 or no identifiable mutation (Fig. 2).
Comparison of clinical features of TSC-LAM cohorts with the TOSCA registry. 73 patients with TSC-LAM are compared with 2093 patients from the TOSCA registry. Median age at assessment and age at diagnosis of TSC in the left panel and percentage of cohort with each disease related feature in the right panel. TOSCA the Tuberous Sclerosis registry to increase disease awareness. TSC tuberous sclerosis complex. TSC1 TSC1 mutation detected. TSC2 TSC2 mutation. NMI no mutation identified. TAND Tuberous sclerosis associated neuropsychiatric disorders. MMNPH Multifocal micronodular pneumocyte hyperplasia
Presentation of LAM in TSC
We examined the presenting problems leading to a diagnosis of LAM in TSC. Most common was the discovery of LAM due to workup or management of angiomyolipoma which occurred in over a quarter of patients. Pneumothorax and dyspnoea were also common modes of presentation. CT scanning performed to investigate other respiratory and unrelated symptoms also led to the diagnosis in a smaller number of subjects (Table 2). One fifth of patients had been diagnosed after CT screening for LAM. Of all 75 patients with TSC, CT screening for LAM was not performed in 48 and screening status was unknown in a further 10 patients. Seventeen patients were screened for LAM, of these, LAM was present in 13 including four patients diagnosed with TSC as adults, one patient had negative screening at age 33 and developed LAM symptoms at age 41, a further patient had negative screening as a teenager and went on to develop LAM symptoms age 25. Two patients screened did not have LAM.
As most evidence and clinical guidelines for the management of LAM are derived from patients with sporadic LAM [25,26:1337–48.
."),27:14–26.
.")], we compared the clinical phenotype of TSC-LAM with that of sporadic LAM to determine how similar the disease manifestations were. Compared with sporadic LAM, patients with TSC-LAM were younger at their first symptom, less likely to present with dyspnoea, more likely to have angiomyolipoma, and almost twice as likely to require embolization or surgery for angiomyolipoma and surgical treatment for pneumothorax. FEV1 and DLCO at first assessment were not significantly different between the two groups (Table 2).
Outcomes
Patients with TSC-LAM were followed up over a mean duration of 49.2 months and sporadic LAM 82.3 months. Over this period, six (8.2%) patients with TSC-LAM died, in only one case due to LAM and one (1.4%) received a lung transplant. The risk of lung transplantation or death due to LAM in the TSC-LAM patients was 0.67% / year. Patients with TSC had a higher overall mortality than patients with sporadic LAM (p < 0.0001). Whilst only one patient in each group died due to LAM, the combined risk of death or transplant per year of observation was statistically higher in patients with TSC-LAM (Table 3).
Fifty-three percent required treatment with an mTOR inhibitor, 36% with sirolimus for LAM and 17% with Everolimus for angiomyolipoma (Table 3). mTOR inhibitors were initiated for TSC-LAM at a mean (SD) age of 39.2 (11) years, a mean of five years earlier than those with sporadic LAM with a mean (SD) age of 44 (9) years (p = 0.009).
Serial lung function was measured as part of clinical care. Despite lung function being attempted by experienced lung function technicians, 11 of the 75 patients with TSC were unable to perform lung function reliably and are not reported. For those patients with serial lung function data, FEV1 fell by a mean of 81 ml/year and DLCO fell by 0.309 mmol/ml/kPa/year in patients not being treated with an mTOR inhibitor.
Rates of mTOR inhibitor treatment for LAM were similar between the two groups. As some patients with TSC also required mTOR inhibitor treatment for angiomyolipoma, patients with TSC-LAM were more likely to be treated with an mTOR inhibitor overall. The choice of mTOR inhibitor used was largely determined by treatment indication: patients with active lung disease were prescribed sirolimus and patients with renal angiomyolipoma requiring treatment were generally treated with Everolimus. Of the 46 patients with TSC prescribed an mTOR inhibitor, 16 (21%) were prescribed Everolimus, all but one of these for renal angiomyolipoma, with one patient taking the drug for combined renal and lung disease. Thirty (40%) were prescribed sirolimus, 25 of whom were treated for LAM, the remainder for angiomyolipoma and of these 2 had changed from Everolimus to sirolimus (one due to funding issues and one after an adverse reaction). Lung function was lower in patients treated with sirolimus (mean (SD) percent predicted FEV1 59.9 (23), DLCO 48.0 (18)) compared to those treated with Everolimus (FEV1 80.4 (20), DLCO 66.8 (27), both p = 0.01). For those treated with either sirolimus or Everolimus, mean FEV1 fell by 3 ml/year and DLCO increased by 0.032 mmol/ml/kPa/year. Lung function decline was similar between patients with TSC-LAM and sporadic LAM in both mTOR inhibitor treated and untreated patients (Table 3).
Discussion
We observed that adult women with TSC suffered significant morbidity from LAM including pneumothorax, lung function decline, and in some cases death from respiratory failure. Despite international TSC guidelines recommending screening of adult women with TSC for LAM [202
.")], over 75% of TSC patients in the current cohort were diagnosed with LAM after developing symptoms. For patients referred to the LAM Centre, rates of loss of lung function, disease related complications and deaths due to LAM were similar to that seen in sporadic LAM. Although the numbers of patients were relatively small, more deaths overall were seen in patients with TSC-LAM.
Our findings suggest that many patients with TSC are not being screened for LAM. Although screening had not been recommended for the first two years of the current study, it is clear many patients are only assessed for LAM when symptoms have developed. In addition, almost one third of patients were diagnosed with LAM after presentation with angiomyolipoma related symptoms, and whilst we don’t have data on angiomyolipoma screening for this group, this finding suggests that angiomyolipoma screening is also not performed in a significant number of patients with TSC. As mTOR inhibitors preserve lung function and probably increase survival, failure to actively screen for and treat LAM in TSC could allow the progression of irreversible, yet preventable lung damage and disability. In addition, bronchodilators improve airflow obstruction and early intervention in LAM can improve respiratory symptoms, alert patients to the risk of pneumothorax and also to avoid oestrogen containing treatments that can exacerbate disease [279
.")]. Likewise, embolization or nephron sparing surgery to prevent angiomyolipoma bleeding and mTOR inhibitors to prevent tumour growth are effective and detecting angiomyolipoma is similarly important [28: a multicentre, randomised, double-blind, placebo-controlled trial. Lancet. 2013;381(9869):817–24.
."), 29:95–102.")]. In our current study and other series, angiomyolipoma are present in most patients with TSC-LAM [30:2003036.
."), 31:1777–82.")] and we would suggest that greater efforts are made to increase awareness of the need to screen for these manifestations of TSC and if angiomyolipoma is detected, then LAM should also be actively sought.
In our cohort, patients with TSC and sporadic LAM had broadly similar LAM symptoms and severity, although there was a significantly higher prevalence of angiomyolipoma and the need for angiomyolipoma intervention either with embolization, surgery or mTOR inhibitors in patients with TSC compared with sporadic LAM. Patients with TSC-LAM had slightly less advanced lung disease than sporadic LAM at presentation, being younger and less likely to present with dyspnoea although lung function wasn’t significantly different. Disease progression shown by rate of lung function loss, risk of death or need for lung transplant were similar in TSC and sporadic LAM. LAM was equally likely to be treated with an mTOR inhibitor with a similar benefit in preventing loss of FEV1 and DLCO although an additional 17% of TSC-LAM patients were receiving an mTOR inhibitor primarily for angiomyolipoma rather than LAM. Whilst the incidence of pneumothorax was similar in both groups, surprisingly, in this cohort, patients with TSC-LAM were twice as likely to need surgery for pneumothorax. Although management guidelines for LAM are mostly based upon studies of sporadic LAM [25,26:1337–48.
."),27:14–26.
.")], the similar disease manifestations of TSC-LAM suggest that their use in TSC is appropriate; particularly recommendations for mTOR inhibitor therapy and early surgical treatment for pneumothorax [26:1337–48.
."), 27:14–26.
.")].
We noted our TSC-LAM cohort tended to be diagnosed with TSC later than average for all patients with TSC represented in the TOSCA study. They were also less likely to have epilepsy or neuropsychiatric complications. Whilst this may be referral bias, due to patients with severe intellectual disability being less likely to complain of respiratory symptoms or be referred to a pulmonary centre, it is also possible that TSC patients with milder neurological features may be more at risk of LAM and angiomyolipoma and consequently less likely to be diagnosed with TSC in childhood. Interestingly, no men with TSC were referred because of LAM. Although CT series report that lung cysts consistent with LAM occur in 10–30% of men this seldom leads to symptoms and for this reason, men with TSC are not screened for LAM and symptomatic disease appears uncommon 97
."), [32:625–8.
.")]. We have previously identified symptom clusters or sub-phenotypes in patients with LAM [30:2003036.
.")] and this may be also true in TSC but needs further study to determine the associations and predictors of the LAM/angiomyolipoma predominant patient with TSC. As the management of childhood TSC and life expectancy improve, LAM is becoming a larger part of TSC care and the morbidity of LAM makes it an important aspect of the TSC phenotype in adults . Our findings suggest that respiratory physicians should be incorporated within the growing number of multidisciplinary TSC clinics and LAM screening should be actively pursued in this setting to address this challenge [34: expert recommendations for provision of coordinated care. Front Neurol. 2019;10:1116."), 35:91.
.")].
Our study represents a national prospective audit of patients with TSC-LAM however has some limitations. Despite including a relatively large group of patients with TSC-LAM, this is a rare disease and numbers, particularly in some sub-group analyses, are small and subject to error. In addition, patients unable to travel to the UK LAM Centre could not be included which may limit representation of some subject groups, including those with more severe disability who may find it harder to travel to a specialist centre.
In conclusion, LAM is generally diagnosed in adult women with TSC after symptoms develop rather than by screening which may delay interventions to prevent loss of lung function. Complications of LAM including pneumothorax, lung function loss and death are significant in TSC-LAM and respiratory physicians should be more involved in TSC care. Improvements in implementing the recommended CT screening for LAM in TSC are required to ensure that appropriate advice is given and mTOR inhibitors are started as soon as there is evidence of progressive lung disease [202
.")].
Availability of data and materials
Full audit data are presented in the manuscript.
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12528 | https://physics.stackexchange.com/questions/290753/can-a-stellar-black-hole-revert-into-neutron-star-or-whatever-it-was | gravity - Can a stellar black hole revert into neutron star or whatever it was? - Physics Stack Exchange
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Can a stellar black hole revert into neutron star or whatever it was?
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When a massive star cannot produce sufficient energy to counter it's weight the result is often a neutron star which is stabilized by quantum mechanical effects, say given enough mass to overcome such effects it becomes a black hole. I wonder if it can lose energy until it reverts into neutron star? If not why not?
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edited Nov 4, 2016 at 7:03
Qmechanic♦
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also see: physics.stackexchange.com/q/118930/248459Pagoda –Pagoda 2020-02-06 10:47:11 +00:00 Commented Feb 6, 2020 at 10:47
Related: Related: physics.stackexchange.com/q/734825/226902Quillo –Quillo 2022-11-07 12:49:41 +00:00 Commented Nov 7, 2022 at 12:49
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I wonder if it can lose energy until it reverts into neutron star? If not why not?
Not at the moment, because nothing leaves the black hole. To lose energy/mass something has to leave, radiation or particles, and nothing can leave except Hawking radiation from the horizon, draining energy from the black hole. This is too weak to enter the picture, unless one is talking of the end of time of the universe, then yes it could happen
A scenario with two black holes falling into each other and losing energy in gravitational waves (LIGO experiment) , would still create a new black hole where nothing substantial leaves. I do not know whether a limiting condition, where gravitational radiation is large enough but the joint mass not enough to form the new black hole, might exist. I suspect not.
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answered Nov 4, 2016 at 7:02
anna vanna v
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I'd suspect that the only cases where you have leakage from the BH interior would involve some parameter fine-tuning that produces a zero-temperature final black hole, or something like one of the fine-tuned naked singularity collapse scenarios as in ias.ac.in/article/fulltext/pram/063/04/0741-0753Zo the Relativist –Zo the Relativist 2019-01-09 16:05:17 +00:00 Commented Jan 9, 2019 at 16:05
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No it can't.
Anna is right that mostly a BH can't loose energy or equivalently mass. But it can for some conditions as Anna wrote, like the Hawking radiation and when two BHs merge, the combined mass will be less than the sum of the two because they loose energy to gravitational radiation.
But in both those cases the BHs sizes change correspondingly so they remain BHs. For the Hawking radiation the mass is reduced, but the BH then gets smaller and it remains a BH. Until the end where it is so small and evaporates so quickly that it explodes by releasing the Hawking radiation very rapidly. Then it ceases to exist. The rates of decay are well known, a function of size/mass, and as they get smaller they decay faster. Large BHs like the one at the center of our Milky Way can last for 100's of billions or trillions of years.
For the merged BHs, the resulting merged BH gets more massive, but also bigger. Since the mass of a BH is proportional to the horizon area (and so to the radius squared), which is proportional to the entropy, and the total entropy has to increase, the the mass and entropy increase for say two equal BHs combining, but the radius increases at most as the square root of what the mass and entropy increases, so it always remains a BH, as merged. In fact this type of calculation (I simplified, but it's true for all cases that it always remains a BH plus whatever gravitational radiation it releases) was used to figure out the maximum gravitational radiation that can be released, as the total entropy can not decrease [for instance if no BH remains and it all goes out as gravitational radiation or something else, the entropy would go down - per unit area a BH has the maximum entropy possible]. See Binary BHs and mergers at e.g.,
The percent of the total BH mass/energy released in gravitational waves for the first LIGO detection was about 5%. Limits possible have been calculated as I described above, and they vary depending on kinematic parameters, spins and charge if any, but they can range from about 27% to more than 50% (and I don't remember the exact numbers for the max).
As for a neutron star forming in that latter case, the radius (of the possible horizon) remaining will always be less than the (eg, for spherical symmetric, but also for the Kerr type) Schwarzschild radius, and so will already be a BH.
So no, nothing other than BHs or nothing an remains behind.
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edited Nov 6, 2016 at 1:11
answered Nov 6, 2016 at 1:00
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I was thinking of possible scenaria, when the black hole evaporates enough to reach , ( inversely in the Black Hole scenario the dark ages), the quark gluon plasma ( definitely a quantum framework) . If then the mass is below a black hole mass it might coagulate to a star. Your answer is the classical scenario.anna v –anna v 2016-11-06 05:22:31 +00:00 Commented Nov 6, 2016 at 5:22
also that some inflation might come in at that point in energy density?anna v –anna v 2016-11-06 06:20:47 +00:00 Commented Nov 6, 2016 at 6:20
There is no energy density inside a BH horizon, there is nothing. There is no quark gluon plasma, there is nothing. Yes, the classical scenario. Nobody knows anything about the quantum scenario, there is no known quantum gravity agreed to. If anything, more than likely the matter is disintegrated into at best Planck sized 'things', whatever they are. No quarks and no gluons or anything we'd recognize. Anything else is speculation. From what we know now.Bob Bee –Bob Bee 2016-11-06 06:47:52 +00:00 Commented Nov 6, 2016 at 6:47
1 Well, the quantized case has to be different. I agree that we know very little now, and all is based on the cosmological BB model, but imo nature abhors singularities :) , so a quantum mechanical frame must exist.anna v –anna v 2016-11-06 06:50:17 +00:00 Commented Nov 6, 2016 at 6:50
Agree, it has to, we just don't know what it is, and all the estimates is that the effects of quantum gravity are not significant until one gets close to the Planck scale. Not in the QCD scale.Bob Bee –Bob Bee 2016-11-06 07:22:25 +00:00 Commented Nov 6, 2016 at 7:22
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12529 | https://www.uptodate.com/contents/antithyroid-drugs-beyond-the-basics | Patient education: Antithyroid drugs (Beyond the Basics) - UpToDate
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Patient education: Antithyroid drugs (Beyond the Basics)
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ANTITHYROID DRUGS OVERVIEW
FUNCTION OF ANTITHYROID DRUGS
TYPES OF ANTITHYROID DRUGS
Methimazole
Propylthiouracil
- Antithyroid drugs during pregnancy
Antithyroid drug side effects
- Minor side effects
- Major side effects
MONITORING THYROID HORMONES DURING TREATMENT
Checking for remission and recurrence
WHERE TO GET MORE INFORMATION
Patient level information
- The Basics
- Beyond the Basics
Professional level information
REFERENCES
GRAPHICS
Figures
- Thyroid anatomy PI
RELATED TOPICS
Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)
Patient education: Thyroid nodules (Beyond the Basics)
Beta blockers in the treatment of hyperthyroidism
Cardiovascular effects of hyperthyroidism
Clinical manifestations and diagnosis of Graves disease in children and adolescents
Diagnosis of hyperthyroidism
Disorders that cause hyperthyroidism
Graves' hyperthyroidism in nonpregnant adults: Overview of treatment
Hyperthyroidism during pregnancy: Treatment
Neurologic manifestations of hyperthyroidism and Graves' disease
Overview of the clinical manifestations of hyperthyroidism in adults
Patient education: Nodular goiter (The Basics)
Patient education: Radioiodine treatment for hyperthyroidism (The Basics)
Patient education: Thyroid nodules (The Basics)
Patient education: Thyroidectomy (The Basics)
Radioiodine in the treatment of Graves' hyperthyroidism
Subclinical hyperthyroidism in nonpregnant adults
Surgical management of hyperthyroidism
Thionamides in the treatment of Graves' disease
Thionamides: Side effects and toxicities
Patient education: Antithyroid drugs (Beyond the Basics)
Author:
Douglas S Ross, MD
Section Editor:
David S Cooper, MD
Deputy Editor:
Jean E Mulder, MD
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Literature review current through: Apr 2025.
This topic last updated: Aug 13, 2024.
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ANTITHYROID DRUGS OVERVIEW
Antithyroid drugs (also called thionamides) are most often used to treat an overactive thyroid (hyperthyroidism) caused by Graves' disease. These drugs block the formation of thyroid hormone by the thyroid gland (figure 1). (See "Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)".)
Antithyroid drugs are very effective for treating hyperthyroidism. They also have some side effects. It is important to learn as much as possible about the treatment of Graves' disease and to discuss all of the possible effects of antithyroid drugs with your health care provider so you can determine which treatment is best for you. (See "Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)", section on 'Hyperthyroidism treatment'.)
FUNCTION OF ANTITHYROID DRUGS
Antithyroid drugs decrease the levels of the two hormones produced by the thyroid gland (figure 1), thyroxine (T4) and triiodothyronine (T3). (See "Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)".)
Antithyroid drugs may be used:
●As a short-term treatment in people with Graves' hyperthyroidism, to prepare for thyroid surgery or radioiodine.
●As initial treatment in Graves' disease for one to two years to see if the disease resolves. Approximately 30 percent of people with Graves' disease will have a remission after one to two years. Antithyroid drugs can be used to control hyperthyroidism while waiting to see if remission occurs.
●To treat hyperthyroidism associated with toxic multinodular goiter or a toxic adenoma ("hot nodule"), usually to prepare for thyroid surgery or radioiodine. (See "Patient education: Thyroid nodules (Beyond the Basics)".)
●To treat hyperthyroidism during pregnancy.
●For long-term treatment of hyperthyroidism due to Graves' disease, toxic multinodular goiter, or toxic adenoma when the person prefers to avoid definitive therapy with radioiodine or surgery. Approximately 80 percent of people with Graves' disease will have a remission after 10 years.
You will need to take antithyroid drugs for at least three weeks (usually six to eight weeks or longer) before your thyroid hormone levels are lowered to normal. This is because the drugs only block formation of new thyroid hormone; they do not remove thyroid hormones that are already in the thyroid and the blood stream. Antithyroid drugs need to be continued to prevent formation of new thyroid hormone, which may result in recurrent hyperthyroidism. If you frequently miss taking your antithyroid drug, thyroid hormone production may resume quickly and replenish thyroid gland stores, preventing adequate control of the hyperthyroidism.
TYPES OF ANTITHYROID DRUGS
Two antithyroid drugs are currently available in the United States: propylthiouracil and methimazole (brand name: Tapazole). Carbimazole (which is converted into methimazole in the body) is available in Europe and parts of Asia but not in the United States.
Methimazole — Methimazole is usually preferred over propylthiouracil because it reverses hyperthyroidism more quickly and has fewer side effects. Methimazole requires an average of six weeks to lower T4 levels to normal; it is often given before radioiodine treatment and usually before thyroid surgery. Methimazole can be taken once per day.
Propylthiouracil — Propylthiouracil does not correct hyperthyroidism as rapidly as methimazole, and it has more side effects. Because of its potential for liver damage, it is used only when methimazole or carbimazole are not appropriate. Propylthiouracil must be taken two to three times per day.
Antithyroid drugs during pregnancy — Propylthiouracil is the drug of choice during the first trimester of pregnancy because it causes less severe birth defects than methimazole. Because there have been rare cases of liver damage in people taking propylthiouracil, some health care providers will suggest switching to methimazole after the first trimester, while others may continue propylthiouracil.
For people who are breastfeeding, methimazole is probably a better choice than propylthiouracil (to avoid liver side effects).
If you take antithyroid drugs and are considering future pregnancy, you should discuss your treatment with your health care provider before trying to get pregnant. Having radioiodine treatment or surgery at least six months before becoming pregnant can eliminate the need for antithyroid treatment during pregnancy. (See "Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)".)
Antithyroid drug side effects — Most of the side effects of antithyroid drugs are minor, but major side effects can occur. Because there is no way to predict who will experience side effects, it is important to discuss all possible side effects before starting treatment.
If you cannot tolerate antithyroid treatments, you can consider radioiodine treatment or surgery. (See "Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)", section on 'Hyperthyroidism treatment'.)
Minor side effects — Up to 15 percent of people who take an antithyroid drug have minor side effects. Both methimazole and propylthiouracil can cause itching, rash, hives, joint pain and swelling, fever, changes in taste, nausea, and vomiting.
If one antithyroid drug causes side effects, switching to the other drug may be helpful. However, approximately one-half of people who have side effects with one drug will have similar side effects with the other. Nausea and vomiting may depend on the dose; spreading large doses out through the day can reduce side effects.
Major side effects — Fortunately, the major side effects of antithyroid drugs are very rare. They include:
●Agranulocytosis – This is a term used to describe a severe decrease in the production of white blood cells. This condition is extremely serious but affects only 1 out of every 200 to 500 people who take an antithyroid drug. Older people taking propylthiouracil and those who take high doses of methimazole may be at higher risk of this side effect.
Agranulocytosis more commonly occurs within the first three months of starting treatment with an antithyroid drug but rarely can occur later. If you develop a sore throat, fever, or other signs or symptoms of infection, you should stop your medicine and immediately call your health care provider to have a complete blood count (CBC with differential). Serious and potentially life-threatening infections, or even death, can occur before agranulocytosis resolves. However, once the antithyroid drug is stopped, agranulocytosis usually resolves within a week.
●Other – There are other very rare complications of antithyroid drugs, including liver damage (more common with propylthiouracil), pancreatitis with methimazole, aplastic anemia (failure of the bone marrow to produce blood cells), and vasculitis (inflammation of blood vessels associated with propylthiouracil).
Propylthiouracil-related liver damage typically occurs within three months of starting the drug. If you develop jaundice, dark-colored urine, light stools, abdominal pain, loss of appetite, nausea, or other evidence of liver dysfunction, you should discontinue the drug immediately and contact your health care provider for assessment of liver function. Propylthiouracil-related liver failure can be serious and potentially life threatening.
The risk of liver damage from propylthiouracil is an important concern, particularly in children. For this reason, methimazole is the first choice for treating hyperthyroidism.
MONITORING THYROID HORMONES DURING TREATMENT
During treatment, your blood thyroid hormone levels will be monitored periodically. Antithyroid drugs typically reduce levels of both triiodothyronine (T3) and thyroxine (T4), but levels of T3 may take longer to return to normal. Thyroid-stimulating hormone (TSH) levels usually take the longest to return to normal.
Approximately 30 percent of people who take an antithyroid drug for one to two years will have prolonged remission of Graves' disease. It is not known if the antithyroid drug plays an active role in this remission or if it simply controls thyroid hormone levels until Graves' disease resolves on its own.
Checking for remission and recurrence — No test can reliably predict remission of Graves' disease. While imperfect, the measurement of TSH-receptor antibodies (TRAb) is widely used in the United States and Europe to determine if a person is in remission. Other names for TRAb are TSI (thyroid stimulating immunoglobulins) or TBII (thyrotropin-binding inhibiting immunoglobulins).
Usually, after one to two years of treatment, TRAb is measured, and if low, your health care provider will recommend stopping the antithyroid drug, and the chance of a remission is 80 percent. However, if TRAb remains high, the chance of a remission is under 20 percent, and it is appropriate to reconsider definitive therapy with radioiodine or surgery or continue antithyroid drugs.
If antithyroid drugs are stopped, thyroid blood tests are usually performed four to eight weeks later. The blood tests are periodically repeated over 12 months to determine if hormone levels remain normal or increase over time (this is called a recurrence).
If your levels of T3, T4, and TSH remain normal for 12 months, the long-term prognosis is good. Recurrence after this time occurs in only 8 to 10 percent of people.
WHERE TO GET MORE INFORMATION
Your health care provider is the best source of information for questions and concerns related to your medical problem.
This article will be updated as needed on our website (www.uptodate.com/patients). Related topics for patients, as well as selected articles written for health care professionals, are also available. Some of the most relevant are listed below.
Patient level information — UpToDate offers two types of patient education materials.
The Basics — The Basics patient education pieces answer the four or five key questions a patient might have about a given condition. These articles are best for patients who want a general overview and who prefer short, easy-to-read materials.
Patient education: Thyroid nodules (The Basics)
Patient education: Nodular goiter (The Basics)
Patient education: Thyroidectomy (The Basics)
Patient education: Radioiodine treatment for hyperthyroidism (The Basics)
Beyond the Basics — Beyond the Basics patient education pieces are longer, more sophisticated, and more detailed. These articles are best for patients who want in-depth information and are comfortable with some medical jargon.
Patient education: Hyperthyroidism (overactive thyroid) (Beyond the Basics)
Patient education: Thyroid nodules (Beyond the Basics)
Professional level information — Professional level articles are designed to keep doctors and other health professionals up-to-date on the latest medical findings. These articles are thorough, long, and complex, and they contain multiple references to the research on which they are based. Professional level articles are best for people who are comfortable with a lot of medical terminology and who want to read the same materials their doctors are reading.
Beta blockers in the treatment of hyperthyroidism
Cardiovascular effects of hyperthyroidism
Clinical manifestations and diagnosis of Graves disease in children and adolescents
Hyperthyroidism during pregnancy: Treatment
Diagnosis of hyperthyroidism
Disorders that cause hyperthyroidism
Neurologic manifestations of hyperthyroidism and Graves' disease
Overview of the clinical manifestations of hyperthyroidism in adults
Radioiodine in the treatment of Graves' hyperthyroidism
Subclinical hyperthyroidism in nonpregnant adults
Surgical management of hyperthyroidism
Thionamides in the treatment of Graves' disease
Graves' hyperthyroidism in nonpregnant adults: Overview of treatment
Thionamides: Side effects and toxicities
The following organizations also provide reliable health information.
●National Library of Medicine
(www.nlm.nih.gov/medlineplus/healthtopics.html)
●The American Thyroid Association
(www.thyroid.org)
●Thyroid Foundation of Canada
(www.thyroid.ca)
●Hormone Health Network
(www.hormone.org, available in English and Spanish)
[1,2]
REFERENCES
El Kawkgi OM, Ross DS, Stan MN. Comparison of long-term antithyroid drugs versus radioactive iodine or surgery for Graves' disease: A review of the literature. Clin Endocrinol (Oxf) 2021; 95:3.
Ross DS, Burch HB, Cooper DS, et al. 2016 American Thyroid Association Guidelines for Diagnosis and Management of Hyperthyroidism and Other Causes of Thyrotoxicosis. Thyroid 2016; 26:1343.
Disclaimer: This generalized information is a limited summary of diagnosis, treatment, and/or medication information. It is not meant to be comprehensive and should be used as a tool to help the user understand and/or assess potential diagnostic and treatment options. It does NOT include all information about conditions, treatments, medications, side effects, or risks that may apply to a specific patient. It is not intended to be medical advice or a substitute for the medical advice, diagnosis, or treatment of a health care provider based on the health care provider's examination and assessment of a patient's specific and unique circumstances. Patients must speak with a health care provider for complete information about their health, medical questions, and treatment options, including any risks or benefits regarding use of medications. This information does not endorse any treatments or medications as safe, effective, or approved for treating a specific patient. UpToDate, Inc. and its affiliates disclaim any warranty or liability relating to this information or the use thereof. The use of this information is governed by the Terms of Use, available at 2025© UpToDate, Inc. and its affiliates and/or licensors. All rights reserved.
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12530 | https://links.uwaterloo.ca/amath353docs/set2.pdf | Lecture 4 Derivation of Heat Equation in higher dimensions Section 1.5 of text by Haberman We now derive the heat equation in higher dimensions, i.e., R2 (to model a thin solid plate) and R3 (a solid region). In what follows, the derivation will be in R3, but the same principles apply to R2.
Let us consider a solid that occupies a region V ⊂R3. As before, we define: e(x, t): the thermal energy density: (heat per unit volume) at a point x ∈V in the solid.
Now consider an arbitrary region D ⊂V that is enclosed by a smooth surface S. (This region D will play the role of the arbitrary segment [a, b] that we used in one dimension.) And as before, we shall also need to define: Φ(x, t): the heat flux vector at a point x ∈V . Its magnitude ∥Φ(x, t)∥is the amount of heat energy flowing per unit time per unit surface area. (The surface area would, of course, be perpendicular to the direction of the vector.) The total heat energy in D at time t will be given by Z Z Z D e(x, t) dV.
(1) We now apply the basic idea of conservation of total heat energy in region D: rate of change net heat flow heat energy of total heat = across boundary + generated inside energy in time per unit time per unit time It now remains to translate this word equation into a mathematical equation. The left hand side of this equation is d dt Z Z Z D e(x, t) dV = Z Z Z D ∂e ∂t dV.
(2) The final term in the word equation can be handled by a source function Q(x, t), the rate of heat energy per unit volume generated at x at time t, so that the total heat energy generated per unit time is Z Z Z D Q dV.
(3) 17 As for the net heat flow across the boundary surface S, recall the idea of a surface integral of a vector function Φ. At a point x ∈S, let ˆ n(x) denote the unit outward normal to S. (Of course, we have to assume that the normal vector exists, which implies that S is orientable.) And let dS denote the infinitesimal element of surface at x. Then the rate of outward heat flow across dS is given by Φ(x, t) · ˆ n(x) dS.
(4) Integration over the entire surface S yields the total outward rate of heat flow through S: Z Z S Φ · ˆ n dS.
(5) The conservation of energy for an arbitrary region D then becomes Z Z Z D ∂e ∂t dV = − Z Z S Φ · ˆ n dS + Z Z Z D Q dV.
(6) Note the negative sign in front of the surface integral since it measures outward heat flow: A positive outward heat flow from D represents a decrease in total heat energy in D.
The surface integral over S may now be converted into a volume integral over the enclosed region D by means of the Divergence Theorem – assuming, of course, that the necessary derivatives exist.
The result is Z Z S Φ · ˆ n dS = Z Z Z D ⃗ ∇· Φ dV.
(7) Eq. (6) then becomes Z Z Z D ∂e ∂t dV = − Z Z Z D ⃗ ∇· Φ dV + Z Z Z D Q dV.
(8) We now combine all terms under one integral: Z Z Z D ∂e ∂t + ⃗ ∇· Φ −Q dV = 0.
(9) From the following assumptions: 1. artibrariness of region D, 2. continuity of the integrand, we may conclude that the integrand is zero at all points of V , to give the conservation equation ∂e ∂t = −⃗ ∇· Φ + Q.
(10) 18 This is a multidimensional generalization of the one-dimensional equation derived in the previous lecture: ∂e ∂t = −∂φ ∂x + Q.
(11) We now introduce the temperature function u(x, t) and relate it to e and Φ in Eq. (10).
1. As before, the relationship between temperature and heat energy density is given by e(x, t) = c(x)ρ(x)[u(x, t) −u0], (12) where c is the specific heat, ρ is the mass density and u0 is a reference temperature.
2. The relationship between temperature and flux will be given by the three-dimensional version of the Fourier “law” for heat conduction: Φ = −K0⃗ ∇u.
(13) Here, K0 = K0(x) is once again the thermal conductivity. As before, heat travels from hotter to colder regions. At a point x, its instantaneous direction of motion is in the direction of steepest descent of the temperature function u, that is, −⃗ ∇u.
Note: Eq. (13) is actually a simplified model – it represents isotropic heat flow, i.e., the flow at a point x is the same in all directions. In other words, the coefficient K0(x), although it may depend on position, does not depend on direction. In many cases, e.g., air, water, this is a good, perhaps, excellent, approximation. However, there are situations, e.g., striated materials, in which it is not – heat will flow at different rates in different directions. In a striated material, it may flow faster in the two directions along the layers, say x andy, that across layers, say z.
In the general case, the thermal conductivity K0(x) is not a scalar, but a tensor, that can be represented as a 3 × 3 matrix. (Its action on ⃗ ∇u will produce a 3-vector. The divergence of this vector – see the next equation – will produce a scalar.) Substitution of these results into Eq. (10) yields cρ∂u ∂t = ⃗ ∇· (K0⃗ ∇u) + Q, (14) which is the multidimensional version of the “generalized heat equation” of the previous lecture.
In the special case that c, ρ and K0 are constants, and Q = 0, the above equation becomes ∂u ∂t = k∇2u, (15) 19 the “heat equation” in three dimensions, where k = K0 cρ (16) is once again the thermal diffusivity.
Diffusion equation in higher dimensions The above method of derivation also applies to the diffusion of a chemical – call it “X” – in a solution.
First, let u(x, t) represent the concentration of the chemical.
The toal amount of chemical in an arbitrary region D ⊂R3 enclosed by a smooth surface S is Z Z Z D u(x, t) dV.
(17) In what follows, we assume that there are no sources, where the chemical is being produced or possibly added from the outside or sinks, where the chemical is being either annihilated or removed from the system. Once again, we let φ(x, t) denote the flux vector at a point x and time t: Its magnitude ∥φ(x, t)∥is the amount of chemical flowing per unit time per unit surface area (normal to the direction of the vector) in the direction of the vector φ(x, t). By conservation of mass, the rate of change of the amount of chemical in region D is given by the negative of the net outward flow of chemical across the boundary S, i.e., d dt Z Z Z D u dV = Z Z Z ∂u ∂t dV = − Z Z D φ · ˆ n dS.
(18) We now apply the Divergence Theorem to the right hand side and rearrange to obtain Z Z Z D ∂u ∂t + ⃗ ∇· φ dV = 0.
(19) Once again assuming that the integrand is continuous, and using the fact that the region D is arbitrary, we obtain the equation ∂u ∂t + ⃗ ∇· φ = 0.
(20) We now need to express the flux φ in terms of u. This is done in terms of Fick’s “law” of transport, φ = −k⃗ ∇· u, (21) where k is the coefficient of diffusivity. (Note the similarity of this equation in form to Fourier’s “law” for heat conduction - after all, they are both transport equations.) Substitution of this result into Eq.
(20) yields the three-dimensional diffusion equation.
∂u ∂t = k∇2u, (22) 20 It has the same form as the three-dimensional heat equation.
“Reaction-diffusion” equations Recall that the above treatment of diffusion did not include any sources where the chemical is being produced or possibly added from the outside or sinks, where the chemical is being either annihilated or removed from the system. These effects may be incorporated into Eq. (20) by means of a source/sink term as was done for the heat equation, i.e., ∂u ∂t = k∇2u + Q(u, x, t).
(23) Note that we have also allowed Q, the rate of production/depletion, to be dependent on the con-centration u. This is generally the case when the chemical is being either produced or annhilated by chemical reactions. For example, suppose that two atoms/molecules of X combine to produce a chemical Y , i.e., X + X →Y.
(24) As you may recall from Chemistry, the “reaction-rate law” for the rate of depletion of X is du dt = −Ku2, (25) where K is the rate constant. Insertion of this term into Eq. (23) yields ∂u ∂t = k∇2u −Ku2, (26) a nonlinear PDE for u(x, t). This is an example of a reaction-diffusion equation. Suppose that we start with a “system”, for example, a solution, or perhaps a gaseous mixture, in which chemical X is initially distributed in a nonhomogeneous manner: For example, there are regions of high concentration of X as well as regions of low concentration of X. As we’ll see shortly, the diffusion term will act to spread out the concentration of X, reducing the concentration at higher regions and increasing it at lower regions. But the reaction term will reduce the concentration of X in all regions – the rate of reduction will, however, be greater at regions of higher concentration.
Electrostatics In this section, we derive a fundamental PDE of electrostatics, commonly called Maxwell’s first equa-tion, relating the electrostatic potential V that is produced by a charge density ρ. In what follows, we 21 shall let r denote the position vector associated with a point x ∈R3, i.e., r = xi + yj + zk, r = ∥r∥= p x2 + y2 + z2.
(27) First, let us recall the basic facts associated with electric charge. Suppose that a point charge Q is situated at the origin of a coordinate system in R3. The electrostatic field vector E(r) associated with this point charge is given by (in SI units) E(r) = Q 4πǫ0r3 r (28) Here, ǫ0 is the permittivity of the vacuum.
The electrostatic force exerted on a test charge q at position r is given by F(r) = qE(r) = qQ 4πǫ0r3 r.
(29) Note that: 1. if qQ < 0, i.e., q and Q are of opposite sign, then F(r) points toward the origin, i.e., the force is attractive.
2. if qQ > 0, i.e., q and Q are of the same sign, then F(r) points away from the origin, i.e., the force is repulsive.
It is a straightforward calculation that the divergence of this vector field is zero at all points except the origin: div E(r) = ⃗ ∇· E(r) = 0, r ̸= 0.
(30) It is undefined at the origin, a consequence of the infinite charge density associated with a point charge.
Also recall that E(r) = −⃗ ∇V (r), where V (r) = Q 4πǫ0r.
(31) V is known as the electrostatic potential.
Let S be a closed, smooth surface that does not contain or enclose the point charge Q. It follows from the Divergence Theorem that Z Z S E · ˆ n dS = Z Z Z V ⃗ ∇· E(r) dV = 0.
(32) 22 Here, ˆ n denotes the unit outward normal to S.
Now let SR be a sphere of radius R > 0 centered at the origin, the location of the point charge Q. A straightforward calculation shows that the total outward flux of the electrostatic field vector E through SR is given by Z Z SR E · ˆ n dS = Q ǫ0 , (33) independent of R. Note that this integral must be evaluated explicitly – we cannot use the Divergence Theorem since ⃗ ∇· E does not exist at the origin.
We can, however, use this result to prove the following: Let S be a smooth surface that encloses the origin/point charge Q. Then Z Z S E · ˆ n dS = Q ǫ0 , (34) which is known as Gauss’ Law. This result is proved by constructing a surface SR centered at Q with R sufficiently small so that SR lies entirely inside S. The Divergence Theorem may be applied to the region D′ that has SR as interior boundary and S as outer boundary. The details can be found in any vector calculus text. You will also find a discussion of the main points of this method (from the instructor’s MATH 227 Lecture Notes) posted after this set of notes on UW-ACE.
23 Lecture 5 Electrostatics (cont’d) We continue our discussion of electrostatic vector fields produced by electric charges.
Extension to several point charges: Now suppose that there are n point charges Qk situated at positions rk, k = 1, 2, · · · , n. The resulting electrostatic field vector E(r) produced by these charges is given by E(r) = n X k=1 Qk 4πǫ0∥r −rk∥3 [r −rk].
(35) It is important to step back for a moment to emphasize one point: The above result, which articulates the linear, vectorial nature of electric fields, is a physical fact that is verified from experiment (at least in the classical domain). It is not a mathematical result that can be derived from mathematical axioms.
From the basic results for a single charge, the following may be shown: Let S be an arbitrary surface in R3 that is assumed not to contain any of the points rk. Then Z Z S E · ˆ n dS = Q′ ǫ0 , (36) where Q′ is the total charge enclosed by surface S. (In other words, charges that lie outside S do not contribute to the total outward flux of E through S.) Extension to a continuous charge density: Now assume that electric charge is distributed in space according to a charge density function ρ(r). Recall the meaning of the charge density function: At a point r ∈R3, the infinitesimal amount of charge contained in an infinitesimal volume element dV centered at r is given by dq = ρ(r) dV.
(37) We assume that ρ is continuous (or at least piecewise continuous). The implication of this is that there are no point charges with infinite density. This follows from the fact that the amount of charge ∆q contained in a tiny region of volume ∆V centered at x is given by ∆q ≈ρ(r)∆V.
(38) As ∆V →0, ∆q →0.
24 Now suppose that a region D ⊂R3 enclosed by a smooth surface S represents a charged body, and that charge is distributed throughout the body according to the density function ρ(r). This means that the total charge Q in the body is given by Q = Z Z Z D ρ(r) dV.
(39) This “smeared out” charge distribution is a kind of continuous version of the previous case dealing with a finite number of point charges. Each infinitesimal element of charge dq situated at a point r′ in the body will contribute toward a net electrostatic field E(r), as we sketch below.
Suppose that position r ∈R3 is our “observation point”, P, at which we wish to determine the net electrostatic field E(r). Note that this point may be either outside or inside the body – in the sketch below, we have placed it outside the body.
P r O D E(r′, r) r′ r −r′ dq′ = ρ(r′)dV ′ Now consider an element of charge dq′ situated at a point r′ ∈D: We use primed coordinates for the charge elements in the body – eventually, we’ll have to integrate over them. We may now apply Coulomb’s law to determine the contribution of this charge element to the total field E(r). The result is E(r, r′) = dq′ 4πǫ0∥r −r′∥3 [r −r′] = ρ(r′)dV 4πǫ0∥r −r′∥3 [r −r′].
(40) (This is equivalent to considering dq′ = ρ(r′)dV ′ as a point charge situated at r′.) Note that this contribution from dq′ points in the direction of the vector r −r′, as it must, since the source of this element of field is at r′ and the observation point is at r.
The net electrostatic field E(r) at our observation point r is now obtained by integrating over all 25 charge elements dq′ on D, i.e., integrating over all r′ ∈D: E(r) = Z Z Z D E(r, r′) dr′ = 1 4πǫ0 Z Z Z D ρ(r′) ∥r −r′∥3 [r −r′] dr′.
(41) (Here, dr′ = dV ′ is the volume element in D.) OK, that’s fine, but the above result is difficult to work with. It would be nicer to have a pointwise relation between E(r) and ρ(r). Such a relation, in terms of a partial differential equation, can be found by means of volume and surface integrals, in a manner quite analogous to the derivation of the heat and diffusion equations. In place of the conservation of energy or mass, however, the basic principle that makes this relation possible is Gauss’ Law.
In order to proceed, we let S′ denote an arbitrary smooth surface that encloses a region D′ that is contained in region D, i.e., D′ ⊂D ⊂R3. (Does this sound familiar?) The total charge enclosed in by S′ is QD′ = Z Z Z D′ dq = Z Z Z D′ ρ(r) dV.
(42) (We now drop the primes from the integration variables.) Now consider the total electrostatic field vector E discussed above. From Gauss’ Law, the total outward flux of E through surface S′ is given by Z Z S′ E · ˆ n dS = QD′ ǫ0 = 1 ǫ0 Z Z Z D′ ρ(r) dV.
(43) This is completely in analogy to the case involving a finite number of point charges. Any charge element dq situated outside surface S′ will have a zero contribution to the total outward flux of E through S′.
We now have a surface integral equal to a volume integral. Sound familiar? The question: Can we convert the surface integral into a volume integral? The answer is: Yes, provided that we can take the divergence of the vector field E. Recall that we could not do this for point charges, i.e., situations where the charge density was infinite. But recall that in the case of continuous charge density functions, there are no point charges. The consequence of this – and we do not prove this result here – is that the electrostatic field vector E(r) in Eq.
(41) is both continuous as well as continuously differentiable. In other words, its divergence is a continuous function. We may therefore employ the Divergence Theorem on the surface integral in Eq. (43) to obtain Z Z Z D′ ⃗ ∇· E(r) dV = 1 ǫ0 Z Z Z D′ ρ(r) dV, (44) 26 or Z Z Z D′ ⃗ ∇· E −1 ǫ0 ρ dV = 0.
(45) Once again we assume that the integrand is continuous for all r ∈D. Because of the arbitrariness of surface S′/region D′, we may conclude, from a three-dimensional version of the Reymond-du Bois lemma, that ⃗ ∇· E(r) = 1 ǫ0 ρ(r).
(46) This result is often called Maxwell’s first equation of electrostatics. Note that the divergence of E(r) is zero at any point where there is no charge. In other words, in the absence of charge, there is zero divergence – only where there is charge is there a divergence of the electrostatic field vector. And recall that the divergence of a vector field at a point measures the net outward flow of the field at that point.
Note that Eq.
(46) is a kind of “integral version” of Eq.
(41).
If we differentiate the latter appropriately to compute the divergence of E(r), then we obtain Eq. (46).
In practical applications, one usually works with the electrostatic potential V associated with E, i.e., E(r) = −⃗ ∇V (r). Substitution into Eq. (46) yields Poisson’s equation: ∇2V (r) = −1 ǫ0 ρ(r).
(47) In the absence of charge, Poisson’s equation becomes Laplace’s equation: ∇2V (r) = 0.
(48) In some applications, one is required to solve for the potential V associated with a prescribed charge distribution ρ, in other words, solving the PDE in Eq. (47). In other applications, one is required to solve Laplace’s equation (48) associated with prescribed boundary conditions. We shall examine such problems later in the course.
27 A return to the 1D heat equation We now return to a discussion of the simplest form of the one-dimensional heat equation, namely, constant thermal properties and no sources: ∂u ∂t = k∂2u ∂x2 .
(49) Initial conditions Section 1.3 of text by Haberman The solution of the heat equation will be a function u(x, t) which describes the evolution of a temperature function on x ∈[0, L]. Without loss of generality, we assume that the evolution begins at t = 0. It seems quite obvious that we would have to provide some “initial data” in order that a unique solution to Eq. (49) would result.
This is part of the more general question of what exactly is needed in order to define a particular solution u(x, t) for t > 0.
1. Initial data: Given that the derivative in time is only a first-order derivative, i.e., ∂u ∂t , it is sufficient to prescribe the temperature distribution at time t = 0 i.e., u(x, 0) = g(x), 0 ≤x ≤L.
(50) 2. Boundary conditions: Because of the second order derivative in x, we shall need to provide two conditions on u(x) or its derivatives. In most applications, a condition is applied at each of the endpoints, i.e., x = 0 and x = L. These boundary conditions will depend upon the physical situation being studied. We examine several possible boundary conditions below.
(a) Prescribed temperatures: From a purely mathematical point of view, it might seem most natural to prescribe the values of u(x, t) at the endpoints, for example, constant temperatures, u(0, t) = T1, u(L, t) = T2.
(51) More generally, we may consider time-varying temperatures at the endpoints, i.e., u(0, t) = fB(t), u(L, t) = gB(t), (52) where the subscript “B” denotes “bath”: These boundary conditions could correspond to the situation where the ends of the rod are in thermal contact with heat baths or huge heat 28 reservoirs that can be maintained at controlled temperatures – in each case, the flow of heat from or to the rod will not affect the temperature of these reservoirs.
A side comment: The prescription of function values at the endpoints is known as the Dirichlet condition.
(b) Prescribed heat flux at ends: This would correspond to −K0(0)∂u ∂x(0+, t) = φ(0, t), −K0(L)∂u ∂x(L−, t) = φ(L, t), (53) where the endpoint fluxes φ(0, t) and φ(L, t) are prescribed. Clearly, these prescriptions involve conditions on the spatial derivative of u at the endpoints.
In the special case that these prescribed fluxes are zero, we have the conditions ∂u ∂x(0+, t) = 0, ∂u ∂x(L−, t) = 0.
(54) A particular example of such a situation is that of perfect insulation at the endpoints, so that no heat flow is allowed out of the rod or into the rod through the endpoints.
Another side comment: The prescription of derivatives at the endpoints is known as the Neumann condition.
(c) Newton’s Law of Cooling: This regards a more complicated case, for example, where an end of the rod is in contact with a moving fluid, e.g., air or water. The heat leaves the rod and is carried away from the moving fluid by convection. Experimentally, it is found that the heat flux is proportional to the temperature difference between the rod and the fluid. For example, at x = 0, φ(0, t) = −K0(0)∂u ∂x(0, t) = −H[u(0, t) −uB(t)], (55) where uB(t) is the temperature of the moving fluid and H > 0 is the heat transfer coefficient.
Note that if u(0, t) > uB(t) then heat should flow from the rod to the fluid, i.e., leftward.
The rightmost term is indeed negative in this case, implying that φ(0, t) is negative, i.e., leftward flow. (Note also that ∂u/∂x > 0.) At the other endpoint, i.e., x = L, the condition is given by φ(L, t) = −K0(L)∂u ∂x(L, t) = H[u(L, t) −uB(t)].
(56) (Exercise: Verify this yourself.) For more discussion on this condition, see Page 13 of the course text.
29 3. Mixed boundary conditions: Depending on the physical situation, it may be necessary to impose different conditions at the two endpoints, for example, (i) prescribed temperature at x = 0, (ii) prescribed flux at x = L.
30 Lecture 6 Equilibrium or “steady-state” temperature distributions: “Qualitative analysis” Section 1.4 of text by Haberman Before we become involved with methods of solving the heat equation, we step back and ask if there exists a temperature distribution that is constant in time, i.e., u(x, t) = ueq(x). Such a solution is known as an equilibrium or steady-state temperature distribution.
It is an important solution because, in many applications, it will represent the temperature distribution which all other ones will approach. In other words, if we “prepare” a rod with a certain temperature distribution u(x, 0) = f(x) by, say, pulling it out of a furnace, and then place it in a particular situation, say, insulated ends, the temperature of the rod u(x, t) will evolve in time to the equilibrium distribution ueq(x) determined by the boundary conditions.
This is the spirit of what is called “qualitative analysis”: extracting particular solutions or deter-mining the behaviour of solutions without actually solving the differential equation.
You may have already seen this idea in your earlier courses on ODEs. For example, consider the following first order ODE in the function x(t): dx dt = 1 −x.
(57) Of course, we can solve this DE, either as a linear DE or as a separable DE. But without actually solving it, we can deduce a few things. For example, when x = 1, the RHS is zero. But this means that the function x(t) = 1 is a solution to the DE since x′(t) = 0 in this case. In other words, x(t) = 1 satisfies the DE. This is the equilibrium solution to the DE.
Furthermore, note that when x > 1, dx dt < 0, implying that x(t) is decreasing. And when x < 1, dx dt > 0, implying that x(t) increasing. These two observations imply that all solutions x(t) approach the equilibrium solution x(t) = 1 as t →∞. In this case, the equilibrium solution x(t) = 1 is said to be attractive or stable.
Question: Analyze the DEs, (i) dx dt = x −1, (ii) dx dt = x2 −1, (58) in the same way as above.
31 Before extracting equilibrium solutions, let us apply some other simple qualitative analysis to the one-dimensional heat equation, ∂u ∂t = k∂2u ∂x2 , (59) where k > 0 is constant. From this equation, note that if ∂2u ∂x2 > 0 over a region, then ∂u ∂t > 0, i.e., the temperature over that region increasing. The positivity of the second derivative implies that the graph of u(x, t) over this region is concave upward. Now suppose that u(x, t) has a local minimum over this region at x = a as sketched below to the left.
local minimum at x = a ∂2u ∂x2 > 0 u(a, t) is increasing “smoothed” temperature distribution For the temperature at the minimum to increase, it means that heat will have to flow from other regions of higher temperature. The net effect is that the temperature distribution will become “smoothened”, as sketched above at the right.
The same can be said for a local maximum – the temperature there will decrease because the graph is concave downward.
The above discussion was not intended to be rigorous, but rather to show that a good deal of qualitative information can often be found in an equation that gives insights into the behaviour of its solutions.
We now return to the question: Does a solution that is constant in time, i.e., u(x, t) = ueq(x), exist for the 1D heat equation ∂u ∂t = k∂2u ∂x2 .
(60) If u = ueq(x) is going to be constant in time, then the left hand side of the equation is zero for all time. This implies that ueq(x) satisfies the ordinary differential equation d2u dx2 = 0.
(61) It is an ODE because u is time-independent.
32 Just to step back for a moment: How do we know that such a solution exists? Answer: We don’t! We’re going to assume a particular form for the solution, i.e., a time-independent solution, and see if such a solution exists.
Now the solution of the ODE in (61) is simple – we just antidifferentiate twice to obtain u(x) = C1x + C2.
(62) This is the general solution of the ODE. Are we finished? Not quite: We have to prescribe the boundary conditions of the problem.
Case 1: Prescribed endpoint temperatures Recall that this is the case where each end of the rod is in contact with a heat bath that is assumed to be maintained as some rescribed temperature. For time-independent steady-state solutions, these prescribed temperatures would have to be constants – if they were to vary in time, then the temperature distributions for 0 < x < L would have to change in time, contrary to our assumption.
So let the boundary conditions be given by u(0) = T1, u(L) = T2.
(63) We impose these conditions on the general solution u(x) = C1x + C2. From the first condition, u(0) = C1 · 0 + C2 = T1 ⇒ C2 = T1.
(64) From the second condition, u(L) = C1L + T1 = T2 ⇒ C1 = T2 −T1 L .
(65) Thus, the equilibrium solution corresponding to the case of prescribed temperatures is given by ueq(x) = T1 + T2 −T1 L x.
(66) This function is a linear interpolation of the prescribed endpoint temperature values T1 and T2.
Approach to equilibrium: Now suppose that we start with a temperature distribution u(x, 0) = f(x) that is not the equilibrium distribution ueq(x). For example, suppose that T1 = 200, T2 = 250 and we just pulled the rod out of a furnace, so that its temperature is, to a good approximation u(x, 0) = f(x) = 1000.
33 First of all, we expect the rod to cool down as heat will travel through the endpoints into the heat baths, which are assumed to have “infinite capacity”, i.e., they’ll absorb all of the heat without changing temperature. Will the temperature of the rod remain constant for all time? No, because a constant solution does not satisfy the boundary conditions. We claim, without proof at this time, that the temperature distribution of the rod will approach the equilibrium temperature distribution ueq(x) as t →∞, i.e., u(x, t) →ueq(x) = C2 + T2 −T1 L x as t →∞.
(67) Of course, there are a number of mathematical questions here: What do we mean by this limiting procedure? It’s equivalent to some kind of “distance” between the functions u(x, t) and ueq(x) going to zero, but what is this “distance” between functions? This is the subject of “functional analysis,” some of which is covered in the AMATH 331 course on Real Analysis. We’ll return to address some of these matters later in the course.
Case 2: Insulated boundaries In this case, there is zero heat flux at the endpoints, i.e., φ(0, t) = φ(L, t) = 0.
(68) This translates to the following problem ∂u ∂t = k∂2u ∂x2 , (69) IC: u(x, 0) = f(x), 0 ≤x ≤L, BC1: ∂u ∂x(0, t) = 0, BC2: ∂u ∂x(L, t) = 0.
As before, if there exists a time-independent equilibrium or steady-state solution u(x, t) = ueq(x), it would have to satisfy the following ODE with boundary conditions: d2u dx2 = 0, u′(0) = u′(L) = 0.
(70) Once again, the general solution is u(x) = C1x + C2.
(71) The condition u′(0) = 0 implies that C1 = 0. This implies that u(x) = C2, (72) 34 which automatically satisfies the boundary condition at x = L.
Therefore, the steady-state solution is not unique: There is an infinity of constant solutions ueq(x) = C2 that satisfy these boundary conditions.
From a physical point of view, this is expected: If a rod initially has an uneven temperature distribution function u(x, 0) = f(x), and no heat is allowed to flow either into the rod or out of the rod, the heat, in flowing from warmer regions to colder regions, will distribute itself throughout the rod, eventually approaching a constant solution ueq(x).
Even though the boundary conditions permit an infinity of steady-state solutions ueq(x), we suspect that a given initial temperature distribution u(x, 0) = f(x) will determine what the final constant value C2 will be. For example, if we start with a rod that has temperatures roughly in the 900-1000 range, then we expect that the equilibrium constant temperature will be somewhere in the range of 900-1000. If we start with a rod in the 2000-3000 range, then we expect the equilibrium constant temperature to be somewhere in that range.
It turns out that a given temperature distribution u(x, 0) = f(x) determines a unique equilibrium temperature ueq(x) = C2, as we now show.
We apply conservation of total thermal energy to the entire rod. Since no heat is allowed to escape or enter the rod, the total thermal energy must be constant. That makes sense physically, but let’s show it mathematically.
Recall that the thermal energy density function e(x, t) is given by e(x, t) = cρ[u(x, t) −u0], (73) where u0 is a suitable reference temperature. In the lecture, we set u0 = 0, to conform with the textbook. In these notes, however, we’ll keep u0 arbitrary, to see that it won’t make any difference.
The total thermal energy in the rod is given by E = Z L 0 cρ[u(x, t) −u0]A dx.
(74) From conservation of energy, dE dt = d dt Z L 0 cρ[u(x, t) −u0]A dx = φ(0, t) −φ(L, t) = 0 −0 = 0, (75) 35 since the flux at each end is zero, by assumption. This implies that the total energy E is constant, i.e., E(t) = cρ Z L 0 [u(x, t) −u0]A dx = E constant (76) This implies that E(t) = E must be equal to the total thermal energy at time t = 0, i.e., E = E(0) = cρ Z L 0 [u(x, 0) −u0]A dx = cρ Z L 0 [f(x) −u0]A dx = cρ Z L 0 f(x)A dx −cρu0AL.
(77) But if E is constant, and the solution u(x, t) evolves toward an equilibrium temperature distribution ueq(x) = C2, it follows that that the total thermal energy associated with ueq(x) is also equal to E, i.e., E = cρ Z L 0 [ueq(x) −u0]A dx = cρ Z L 0 [C2 −u0]A dx = cρC2AL −cρu0AL.
(78) This implies that cρC2AL −cρu0AL = cρ Z L 0 f(x)A dx −cρu0AL, (79) or C2 = 1 L Z L 0 f(x) dx.
(80) In other words, the equilibrium temperature at each point is the average value of the initial temperature distribution. This makes sense physically. Recall that in our model, temperature is proportional to heat content. If the total amount of heat energy in the rod is conserved, due to insulation of the ends, then we expect that it is simply redistributed equally throughout the rod. The value of this redistributed amount would be the average value. (Note again that the result did not depend on the choice of the reference temperature u0, which makes physical sense.) 36 |
12531 | https://math.libretexts.org/Courses/Cosumnes_River_College/Corequisite_Codex/19%3A_Systems/19.02%3A_Solving_2x2_Systems_of_Linear_Equations | 19.2: Solving 2x2 Systems of Linear Equations - Mathematics LibreTexts
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Chapter 19: Systems
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19.2: Solving 2x2 Systems of Linear Equations
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19.2: Solving 2x2 Systems of Linear Equations
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19.1: The Concepts Behind Systems of Equations
19.3: Solving 3x3 Systems of Linear Equations
Page ID 173524
Roy Simpson
Cosumnes River College
( \newcommand{\kernel}{\mathrm{null}\,})
Table of contents
1. Media
1. Videos
Definitions and Theorems
Theorem:Number of Solutions of Linear Systems
Definition: Substitution Method (of solving a system)
How To... Solve a 2x2 System Using Substitution
Definition: Elimination Method (of solving a system)
How To... Solve a 2x2 System Using Elimination
Examples
Learning Objectives
Determine Whether an Ordered Pair is a Solution of a System of Equations
SYSTEM OF LINEAR EQUATIONS
SolutionS OF A SYSTEM OF EQUATIONS
Example 19.2.1
Example 19.2.2
Example 19.2.3
Solve a System of Linear Equations by Graphing
Example 19.2.4: How to Solve a System of Equations by Graphing
Example 19.2.5
Example 19.2.6
SOLVE A SYSTEM OF LINEAR EQUATIONS BY GRAPHING.
Example 19.2.7
Example 19.2.8
Example 19.2.9
Example 19.2.10
Example 19.2.11
Example 19.2.12
Example 19.2.13
Example 19.2.14
Example 19.2.15
COINCIDENT LINES
CONSISTENT AND INCONSISTENT SYSTEMS
Example 19.2.16
Example 19.2.17
Example 19.2.18
Solve a System of Equations by Substitution
Example 19.2.19: How to Solve a System of Equations by Substitution
Example 19.2.20
Example 19.2.21
SOLVE A SYSTEM OF EQUATIONS BY SUBSTITUTION.
Example 19.2.22
Example 19.2.23
Example 19.2.24
Solve a System of Equations by Elimination
Exercise 19.2.25: How to Solve a System of Equations by Elimination
Exercise 19.2.26
Exercise 19.2.27
SOLVE A SYSTEM OF EQUATIONS BY ELIMINATION.
Exercise 19.2.28
Exercise 19.2.29
Exercise 19.2.30
Exercise 19.2.31
Exercise 19.2.32
Exercise 19.2.33
Exercise 19.2.34
Exercise 19.2.35
Exercise 19.2.36
Choose the Most Convenient Method to Solve a System of Linear Equations
Example 19.2.37
Example 19.2.38
Example 19.2.39
Key Concepts
Glossary
Hawk A.I. Section-Specific Tutor
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Media
Videos
Solving Small Systems Using the Substitution Method
Solving Small Systems Using the Elimination Method
Definitions and Theorems
Theorem:Number of Solutions of Linear Systems
A consistent linear system has either exactly one solution or an infinite number of solutions.
Definition: Substitution Method (of solving a system)
TheSubstitution Methodis a heuristic process in which we solve one equation in a system for one variable and then substitute that result into another equation in the system.
How To... Solve a 2x2 System Using Substitution
Solve one of the two equations for one of the variables in terms of the other.
Substitute the expression for this variable into the second equation, then solve for the remaining variable.
Substitute that solution into either of the original equations to find the value of the first variable. If possible, write the solution as an ordered pair.
Check the solution in both equations.
Definition: Elimination Method (of solving a system)
TheElimination Methodis an algorithmic process in which we add two equations within a system that have the opposite coefficients on the same variable so that the sum of the terms involving that variable is zero. This eliminates that variable from the system and forms a new, smaller system.
How To... Solve a 2x2 System Using Elimination
Write both equations with x- and y-variables on the left side of the equal sign and constants on the right.
Write one equation above the other, lining up corresponding variables. If one of the variables in the top equation has the opposite coefficient of the same variable in the bottom equation, add the equations together, eliminating one variable. If not, use multiplication by a nonzero number so that one of the variables in the top equation has the opposite coefficient of the same variable in the bottom equation, then add the equations to eliminate the variable.
Solve the resulting equation for the remaining variable.
Substitute that value into one of the original equations and solve for the second variable.
Check the solution by substituting the values into the other equation.
Examples
Learning Objectives
By the end of this section, you will be able to:
Determine whether an ordered pair is a solution of a system of equations
Solve a system of linear equations by graphing
Solve a system of equations by substitution
Solve a system of equations by elimination
Choose the most convenient method to solve a system of linear equations
Before you get started, take this readiness quiz.
For the equation y=2 3x−4,
ⓐ Is (6,0) a solution? ⓑ Is (−3,−2) a solution?
If you missed this problem, review [link].
2. Find the slope and y-intercept of the line 3x−y=12.
If you missed this problem, review [link].
3. Find the x- and y-intercepts of the line 2x−3y=12.
If you missed this problem, review [link].
Determine Whether an Ordered Pair is a Solution of a System of Equations
In Solving Linear Equations, we learned how to solve linear equations with one variable. Now we will work with two or more linear equations grouped together, which is known as a system of linear equations.
SYSTEM OF LINEAR EQUATIONS
When two or more linear equations are grouped together, they form a system of linear equations.
In this section, we will focus our work on systems of two linear equations in two unknowns. We will solve larger systems of equations later in this chapter.
An example of a system of two linear equations is shown below. We use a brace to show the two equations are grouped together to form a system of equations.
{2x+y=7 x−2y=6
A linear equation in two variables, such as 2x+y=7, has an infinite number of solutions. Its graph is a line. Remember, every point on the line is a solution to the equation and every solution to the equation is a point on the line.
To solve a system of two linear equations, we want to find the values of the variables that are solutions to both equations. In other words, we are looking for the ordered pairs (x,y) that make both equations true. These are called the solutions of a system of equations.
SolutionS OF A SYSTEM OF EQUATIONS
The solutions of a system of equations are the values of the variables that make all the equations true. A solution of a system of two linear equations is represented by an ordered pair (x,y).
To determine if an ordered pair is a solution to a system of two equations, we substitute the values of the variables into each equation. If the ordered pair makes both equations true, it is a solution to the system.
Example 19.2.1
Determine whether the ordered pair is a solution to the system {x−y=−1 2x−y=−5.
ⓐ (−2,−1) ⓑ (−4,−3)
Answer
ⓐ
ⓑ
Example 19.2.2
Determine whether the ordered pair is a solution to the system \left { \begin{array} 3x+y = 0 \ x+2y = −5 \end{array} \right..
ⓐ (1,−3) ⓑ (0,0)
Answer
ⓐ yes ⓑ no
Example 19.2.3
Determine whether the ordered pair is a solution to the system \left { \begin{array} x−3y = −8 \ −3x−y = 4 \end{array} \right..
ⓐ (2,−2) ⓑ (−2,2)
Answer
ⓐ no ⓑ yes
Solve a System of Linear Equations by Graphing
In this section, we will use three methods to solve a system of linear equations. The first method we’ll use is graphing.
The graph of a linear equation is a line. Each point on the line is a solution to the equation. For a system of two equations, we will graph two lines. Then we can see all the points that are solutions to each equation. And, by finding what the lines have in common, we’ll find the solution to the system.
Most linear equations in one variable have one solution, but we saw that some equations, called contradictions, have no solutions and for other equations, called identities, all numbers are solutions.
Similarly, when we solve a system of two linear equations represented by a graph of two lines in the same plane, there are three possible cases, as shown.
Figure 19.2.1
Each time we demonstrate a new method, we will use it on the same system of linear equations. At the end of the section you’ll decide which method was the most convenient way to solve this system.
Example 19.2.4: How to Solve a System of Equations by Graphing
Solve the system by graphing {2x+y=7 x−2y=6.
Answer
Example 19.2.5
Solve the system by graphing: {x−3y=−3 x+y=5.
Answer
(3,2)
Example 19.2.6
Solve the system by graphing: {−x+y=1 3x+2y=12
Answer
(2,3)
The steps to use to solve a system of linear equations by graphing are shown here.
SOLVE A SYSTEM OF LINEAR EQUATIONS BY GRAPHING.
Graph the first equation.
Graph the second equation on the same rectangular coordinate system.
Determine whether the lines intersect, are parallel, or are the same line.
Identify the solution to the system.
If the lines intersect, identify the point of intersection. This is the solution to the system.
If the lines are parallel, the system has no solution.
If the lines are the same, the system has an infinite number of solutions.
Check the solution in both equations.
In the next example, we’ll first re-write the equations into slope–intercept form as this will make it easy for us to quickly graph the lines.
Example 19.2.7
Solve the system by graphing: {3x+y=−1 2x+y=0
Answer
We’ll solve both of these equations for y so that we can easily graph them using their slopes and y-intercepts.
Solve the first equation for y.
Find the slope and y-intercept.
Solve the second equation for y.
Find the slope and y-intercept.
Graph the lines.
Determine the point of intersection.The lines intersect at (−1,2).
Check the solution in both equations.
The solution is (−1,2).
Example 19.2.8
Solve the system by graphing: {−x+y=1 2x+y=10.
Answer
(3,4)
Example 19.2.9
Solve the system by graphing: {2x+y=6 x+y=1.
Answer
(5,−4)
In all the systems of linear equations so far, the lines intersected and the solution was one point. In the next two examples, we’ll look at a system of equations that has no solution and at a system of equations that has an infinite number of solutions.
Example 19.2.10
Solve the system by graphing: {y=1 2x−3 x−2y=4.
Answer
To graph the first equation, we will use its
slope and y-intercept.
To graph the second equation, we will use
the intercepts.
Graph the lines.
Determine the points of intersection.The lines are parallel.
Since no point is on both lines, there is no
ordered pair that makes both equations
true. There is no solution to this system.
Example 19.2.11
Solve the system by graphing: {y=−1 4x+2 x+4y=4.
Answer
no solution
Example 19.2.12
Solve the system by graphing: {y=3x−1 6x−2y=6.
Answer
no solution
Sometimes the equations in a system represent the same line. Since every point on the line makes both equations true, there are infinitely many ordered pairs that make both equations true. There are infinitely many solutions to the system.
Example 19.2.13
Solve the system by graphing: {y=2x−3−6x+3y=9.
Answer
Find the slope and y-intercept of the first equation.
Find the intercepts of the second equation.
Graph the lines.
The lines are the same!
Since every point on the line makes both
equations true, there are infinitely many
ordered pairs that make both equations true.
There are infinitely many solutions to this system.
If you write the second equation in slope-intercept form, you may recognize that the equations have the same slope and same y-intercept.
Example 19.2.14
Solve the system by graphing: {y=−3x−6 6x+2y=−12.
Answer
infinitely many solutions
Example 19.2.15
Solve the system by graphing: {y=1 2x−4 2x−4y=16.
Answer
infinitely many solutions
When we graphed the second line in the last example, we drew it right over the first line. We say the two lines are coincident. Coincident lines have the same slope and same y- intercept.
COINCIDENT LINES
Coincident lines have the same slope and same y- intercept.
The systems of equations in Example and Example each had two intersecting lines. Each system had one solution.
In Example, the equations gave coincident lines, and so the system had infinitely many solutions.
The systems in those three examples had at least one solution. A system of equations that has at least one solution is called a consistent system.
A system with parallel lines, like Example, has no solution. We call a system of equations like this inconsistent. It has no solution.
CONSISTENT AND INCONSISTENT SYSTEMS
A consistent system of equations is a system of equations with at least one solution.
An inconsistent system of equations is a system of equations with no solution.
We also categorize the equations in a system of equations by calling the equations independent or dependent. If two equations are independent, they each have their own set of solutions. Intersecting lines and parallel lines are independent.
If two equations are dependent, all the solutions of one equation are also solutions of the other equation. When we graph two dependent equations, we get coincident lines.
Let’s sum this up by looking at the graphs of the three types of systems. See below and Table.
| Lines | Intersecting | Parallel | Coincident |
--- --- |
| Number of solutions | 1 point | No solution | Infinitely many |
| Consistent/inconsistent | Consistent | Inconsistent | Consistent |
| Dependent/ independent | Independent | Independent | Dependent |
Example 19.2.16
Without graphing, determine the number of solutions and then classify the system of equations.
ⓐ {y=3x−1 6x−2y=12 ⓑ {2x+y=−3 x−5y=5
Answer
ⓐ We will compare the slopes and intercepts of the two lines.
{y=3x−1 6x−2y=12 y=3x−1 The first equation is already in slope-intercept form.Write the second equation in slope-intercept form.6x−2y=12−2y=−6x+12−2y−2=−6x+12−2 y=3x−6 y=3x−1 y=3x−6 m=3 m=3 b=−1 b=−6 Find the slope and intercept of each line.Since the slopes are the same andy-intercepts are different, the lines are parallel.
ⓑ We will compare the slope and intercepts of the two lines.
{2x+y=−3 x−5y=5 Write both equations in slope–intercept form.2x+y=−3 x−5y=5 y=−2x−3−5y=−x+5−5y−5=−x+5−5 y=1 5−1 Find the slope and intercept of each line.y=−2x−3 y=1 5−1 m=−2 m=1 5 b=−3 b=−1 Since the slopes are different, the lines intersect.
A system of equations whose graphs are intersect has 1 solution and is consistent and independent.
Example 19.2.17
Without graphing, determine the number of solutions and then classify the system of equations.
ⓐ {y=−2x−4 4x+2y=9 ⓑ {3x+2y=2 2x+y=1
Answer
ⓐ no solution, inconsistent, independent ⓑ one solution, consistent, independent
Example 19.2.18
Without graphing, determine the number of solutions and then classify the system of equations.
ⓐ {y=1 3x−5 x−3y=6 ⓑ {x+4y=12−x+y=3
Answer
ⓐ no solution, inconsistent, independent ⓑ one solution, consistent, independent
Solving systems of linear equations by graphing is a good way to visualize the types of solutions that may result. However, there are many cases where solving a system by graphing is inconvenient or imprecise. If the graphs extend beyond the small grid with x and y both between −10 and 10, graphing the lines may be cumbersome. And if the solutions to the system are not integers, it can be hard to read their values precisely from a graph.
Solve a System of Equations by Substitution
We will now solve systems of linear equations by the substitution method.
We will use the same system we used first for graphing.
{2x+y=7 x−2y=6
We will first solve one of the equations for either x or y. We can choose either equation and solve for either variable—but we’ll try to make a choice that will keep the work easy.
Then we substitute that expression into the other equation. The result is an equation with just one variable—and we know how to solve those!
After we find the value of one variable, we will substitute that value into one of the original equations and solve for the other variable. Finally, we check our solution and make sure it makes both equations true.
Example 19.2.19: How to Solve a System of Equations by Substitution
Solve the system by substitution: {2x+y=7 x−2y=6
Answer
Example 19.2.20
Solve the system by substitution: {−2x+y=−11 x+3y=9
Answer
(6,1)
Example 19.2.21
Solve the system by substitution: {2x+y=−1 4x+3y=3
Answer
(−3,5)
SOLVE A SYSTEM OF EQUATIONS BY SUBSTITUTION.
Solve one of the equations for either variable.
Substitute the expression from Step 1 into the other equation.
Solve the resulting equation.
Substitute the solution in Step 3 into either of the original equations to find the other variable.
Write the solution as an ordered pair.
Check that the ordered pair is a solution to both original equations.
Be very careful with the signs in the next example.
Example 19.2.22
Solve the system by substitution: {4x+2y=4 6x−y=8
Answer
We need to solve one equation for one variable. We will solve the first equation for y.
Solve the first equation for y.
Substitute −2x+2 for y in the second equation.
Replace the y with −2x+2.
Solve the equation for x.
Substitute x=54 into 4x+2y=4 to find y.
The ordered pair is (54,−12).
Check the ordered pair in both equations.
The solution is (54,−12).
Example 19.2.23
Solve the system by substitution: {x−4y=−4−3x+4y=0
Answer
(2,32)
Example 19.2.24
Solve the system by substitution: {4x−y=0 2x−3y=5
Answer
(−12,−2)
Solve a System of Equations by Elimination
We have solved systems of linear equations by graphing and by substitution. Graphing works well when the variable coefficients are small and the solution has integer values. Substitution works well when we can easily solve one equation for one of the variables and not have too many fractions in the resulting expression.
The third method of solving systems of linear equations is called the Elimination Method. When we solved a system by substitution, we started with two equations and two variables and reduced it to one equation with one variable. This is what we’ll do with the elimination method, too, but we’ll have a different way to get there.
The Elimination Method is based on the Addition Property of Equality. The Addition Property of Equality says that when you add the same quantity to both sides of an equation, you still have equality. We will extend the Addition Property of Equality to say that when you add equal quantities to both sides of an equation, the results are equal.
For any expressions a, b, c, and d.
if a=b and c=d then a+c=b+d.
To solve a system of equations by elimination, we start with both equations in standard form. Then we decide which variable will be easiest to eliminate. How do we decide? We want to have the coefficients of one variable be opposites, so that we can add the equations together and eliminate that variable.
Notice how that works when we add these two equations together:
{3x+y=5 2x−y=0―
5x=5
The y’s add to zero and we have one equation with one variable.
Let’s try another one:
\left{ \begin{array} x+4y=2 \ 2x+5y=−2 \end{array} \right. \nonumber
This time we don’t see a variable that can be immediately eliminated if we add the equations.
But if we multiply the first equation by −2, we will make the coefficients of x opposites. We must multiply every term on both sides of the equation by −2.
Then rewrite the system of equations.
Now we see that the coefficients of the x terms are opposites, so x will be eliminated when we add these two equations.
Once we get an equation with just one variable, we solve it. Then we substitute that value into one of the original equations to solve for the remaining variable. And, as always, we check our answer to make sure it is a solution to both of the original equations.
Now we’ll see how to use elimination to solve the same system of equations we solved by graphing and by substitution.
Exercise 19.2.25: How to Solve a System of Equations by Elimination
Solve the system by elimination: {2x+y=7 x−2y=6
Answer
Exercise 19.2.26
Solve the system by elimination: {3x+y=5 2x−3y=7
Answer
(2,−1)
Exercise 19.2.27
Solve the system by elimination: {4x+y=−5−2x−2y=−2
Answer
(−2,3)
The steps are listed here for easy reference.
SOLVE A SYSTEM OF EQUATIONS BY ELIMINATION.
Write both equations in standard form. If any coefficients are fractions, clear them.
Make the coefficients of one variable opposites.
Decide which variable you will eliminate.
Multiply one or both equations so that the coefficients of that variable are opposites.
Add the equations resulting from Step 2 to eliminate one variable.
Solve for the remaining variable.
Substitute the solution from Step 4 into one of the original equations. Then solve for the other variable.
Write the solution as an ordered pair.
Check that the ordered pair is a solution to both original equations.
Now we’ll do an example where we need to multiply both equations by constants in order to make the coefficients of one variable opposites.
Exercise 19.2.28
Solve the system by elimination: {4x−3y=9 7x+2y=−6
Answer
In this example, we cannot multiply just one equation by any constant to get opposite coefficients. So we will strategically multiply both equations by different constants to get the opposites.
Both equations are in standard form.
To get opposite coefficients of y, we will
multiply the first equation by 2 and the
second equation by 3.
Simplify.
Add the two equations to eliminate y.
Solve for x.
Substitute x=0x=0 into one of the original equations.
Solve for y.
Write the solution as an ordered pair.The ordered pair is (0,−3).
Check that the ordered pair is a solution to
both original equations.
The solution is (0,−3).
Exercise 19.2.29
Solve the system by elimination: {3x−4y=−9 5x+3y=14
Answer
(1,3)
Exercise 19.2.30
Solve each system by elimination: {7x+8y=4 3x−5y=27
Answer
(4,−3)
When the system of equations contains fractions, we will first clear the fractions by multiplying each equation by the LCD of all the fractions in the equation.
Exercise 19.2.31
Solve the system by elimination: {x+1 2y=6 3 2x+2 3y=17 2
Answer
In this example, both equations have fractions. Our first step will be to multiply each equation by the LCD of all the fractions in the equation to clear the fractions.
To clear the fractions, multiply each
equation by its LCD.
Simplify.
Now we are ready to eliminate one
of the variables. Notice that both equations are in
standard form.
We can eliminate y by multiplying the top equation by −4.
Simplify and add.
Substitute x=3 into one of the original equations.
Solve for y.
Write the solution as an ordered pair.The ordered pair is (3,6).
Check that the ordered pair is a solution to
both original equations.
The solution is (3,6).
Exercise 19.2.32
Solve each system by elimination: {1 3x−1 2y=1 3 4x−y=5 2
Answer
(6,2)
Exercise 19.2.33
Solve each system by elimination: {x+3 5y=−1 5−1 2x−2 3y=5 6
Answer
(1,−2)
When we solved the system by graphing, we saw that not all systems of linear equations have a single ordered pair as a solution. When the two equations were really the same line, there were infinitely many solutions. We called that a consistent system. When the two equations described parallel lines, there was no solution. We called that an inconsistent system.
The same is true using substitution or elimination. If the equation at the end of substitution or elimination is a true statement, we have a consistent but dependent system and the system of equations has infinitely many solutions. If the equation at the end of substitution or elimination is a false statement, we have an inconsistent system and the system of equations has no solution.
Exercise 19.2.34
Solve the system by elimination: {3x+4y=12 y=3−3 4x
Answer
{3x+4y=12 y=3−3 4x Write the second equation in standard form.{3x+4y=12 3 4x+y=3 Clear the fractions by multiplying the second equation by 4.{3x+4y=12 4(3 4x+y)=4(3)Simplify.{3x+4y=12 3x+4y=12 To eliminate a variable, we multiply the second equation by−1. Simplify and add.{3x+4y=12−3x−4y=−12―0=0
This is a true statement. The equations are consistent but dependent. Their graphs would be the same line. The system has infinitely many solutions.
After we cleared the fractions in the second equation, did you notice that the two equations were the same? That means we have coincident lines.
Exercise 19.2.35
Solve the system by elimination: {5x−3y=15 5y=−5+5 3x
Answer
infinitely many solutions
Exercise 19.2.36
Solve the system by elimination: {x+2y=6 y=−1 2x+3
Answer
infinitely many solutions
Choose the Most Convenient Method to Solve a System of Linear Equations
When you solve a system of linear equations in in an application, you will not be told which method to use. You will need to make that decision yourself. So you’ll want to choose the method that is easiest to do and minimizes your chance of making mistakes.
Choose the Most Convenient Method to Solve a System of Linear Equations Graphing―Substitution―Elimination―Use when you need a Use when one equation is Use when the equations a picture of the situation.already solved or can be rein standard form.easily solved for one variable.
Example 19.2.37
For each system of linear equations, decide whether it would be more convenient to solve it by substitution or elimination. Explain your answer.
ⓐ {3x+8y=40 7x−4y=−32 ⓑ {5x+6y=12 y=2 3x−1
Answer
ⓐ
{3x+8y=40 7x−4y=−32
Since both equations are in standard form, using elimination will be most convenient.
ⓑ
{5x+6y=12 y=2 3x−1
Since one equation is already solved for y, using substitution will be most convenient.
Example 19.2.38
For each system of linear equations decide whether it would be more convenient to solve it by substitution or elimination. Explain your answer.
ⓐ {4x−5y=−32 3x+2y=−1 ⓑ {x=2y−1 3x−5y=−7
Answer
ⓐ Since both equations are in standard form, using elimination will be most convenient. ⓑ Since one equation is already solved for x, using substitution will be most convenient.
Example 19.2.39
For each system of linear equations decide whether it would be more convenient to solve it by substitution or elimination. Explain your answer.
ⓐ {y=2x−1 3x−4y=−6 ⓑ {6x−2y=12 3x+7y=−13
Answer
ⓐ Since one equation is already solved for y, using substitution will be most convenient. ⓑ Since both equations are in standard form, using elimination will be most convenient.
Key Concepts
How to solve a system of linear equations by graphing.
Graph the first equation.
Graph the second equation on the same rectangular coordinate system.
Determine whether the lines intersect, are parallel, or are the same line.
Identify the solution to the system.
If the lines intersect, identify the point of intersection. This is the solution to the system.
If the lines are parallel, the system has no solution.
If the lines are the same, the system has an infinite number of solutions.
5. Check the solution in both equations.
How to solve a system of equations by substitution.
Solve one of the equations for either variable.
Substitute the expression from Step 1 into the other equation.
Solve the resulting equation.
Substitute the solution in Step 3 into either of the original equations to find the other variable.
Write the solution as an ordered pair.
Check that the ordered pair is a solution to both original equations.
How to solve a system of equations by elimination.
Write both equations in standard form. If any coefficients are fractions, clear them.
Make the coefficients of one variable opposites.
Decide which variable you will eliminate.
Multiply one or both equations so that the coefficients of that variable are opposites.
3. Add the equations resulting from Step 2 to eliminate one variable.
4. Solve for the remaining variable.
5. Substitute the solution from Step 4 into one of the original equations. Then solve for the other variable.
6. Write the solution as an ordered pair.
7. Check that the ordered pair is a solution to both original equations. Choose the Most Convenient Method to Solve a System of Linear Equations Graphing―Substitution―Elimination―Use when one equation is Use when you need a already solved or can be Use when the equations a picture of the situation.easily solved for one rein standard form.variable.
Glossary
coincident linesCoincident lines have the same slope and same y-intercept.consistent and inconsistent systemsConsistent system of equations is a system of equations with at least one solution; inconsistent system of equations is a system of equations with no solution.solutions of a system of equationsSolutions of a system of equations are the values of the variables that make all the equations true; solution is represented by an ordered pair (x,y).(x,y).system of linear equationsWhen two or more linear equations are grouped together, they form a system of linear equations.
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19.1: The Concepts Behind Systems of Equations
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12532 | http://physics.bu.edu/~pankajm/PY571/Chapter2.pdf | 2 CHEMICAL KINETICS I: BASICS c1 In the previous chapter, we c2discussed some the fundamental biological pro-cesses c3undertaken by cells such as transcription and translation. The purpose of this chapter is to introduce the basic concepts needed to model the dynamics of such processes. c4These next two chapters explain how to describe chemical re-actions mathematically, both at a deterministic level where stochastic effects are ignored, as well as probabilistically where stochasticity is explicitly incorporated.
2.1 Law of mass action Consider a reaction where two kinds of molecules, c5 A and B, irreversibly re-act to produce a third kind c6of molecule, C. Schematically, such a reaction is represented as A + B k ! C.
(2.1) The parameter k is the rate of the reaction. c7In general, kinetic parameters such as k depend on the environment through thermodynamic quantities such as the pressure and temperature. However, since cells often operate in environments where these quantities do not vary much, for simplicity, we will neglect these dependencies in what follows. According to the law of mass action,the rate of increase of the concentration of the product is given by d[C] dt = k[A][B] (2.2) where we follow the standard convention in chemistry texts: the concentration of the chemical X is represented by [X]. Note that the accompanied decrease of the concentrations of A and B is given by the same expression: k[A][B]. Namely, d[A] dt = d[B] dt = −k[A][B] (2.3) c1Pankaj: This is a test c2Pankaj: have introduced some of the basic c3Pankaj: Text added.
c4Pankaj: Text added.
c5Pankaj: Text added.
c6Pankaj: Text added.
c7Pankaj: in general, depends upon the temperature 18 LAW OF MASS ACTION 19 The law of mass action applies to elementary reactions where molecules of type A and of type B collide, with the collision event giving rise to the prod-uct C with a probability related to the rate constant k. c8 The basic intuition behind the law of mass action is that the probability per unit time of collision is proportional to the concentrations of A and B. The crucial c9assumption un-derlying these equations is that, for most practical purposes, the formation of C can be considered as a one step process rather than a process with multiple intermediates.
Since the reaction 2.1 is irreversible, eventually, either molecules of type A or of type B will be completely depleted and the reaction will stop. Each time this reaction takes place, we reduce the number of A and B molecules by one each.
Therefore, if we start with a certain amount of A and B, c1 the species with the smaller number of molecules will be depleted first. Let us see how c2this works mathematically by explicitly solving the c3corresponding di↵erential equation.
Initially, at time t = 0, assume [A] = A0, [B] = B0 and [C] = 0. Furthermore, without loss of generality, we assume B0 > A0. For convenience, we introduce the following notation for the time dependent concentrations of A, B and C c4at time t: [A] = a(t), [B] = b(t), [C] = c(t) c5. Notice that the equations 2.2 and 2.3 imply that the conservation laws a(t) + c(t) = A0, (2.4) b(t) + c(t) = B0.
(2.5) c6These conservation laws reflect the fact that in order to produce a single molecule of C, one has to consume a molecule of A and a molecule of B. A direct consequence of the equations above is that b(t) −a(t) = B0 −A0 ⌘∆ (2.6) is also a constant.
We can now use the conservation laws to write equation 2.2 as a di↵erential equation constraining a single variable.
d dt(A0 −a(t)) = dc(t) dt = ka(t)b(t) = ka(t)(∆+ a(t)) (2.7) or c8Pankaj: Text added.
c9Pankaj: aspect of such reactions c1Pankaj: which will be ultimately depleted depends upon which had the smaller number of molecules in the beginning c2Pankaj: that works out c3Pankaj: Text added.
c4Pankaj: Text added.
c5Pankaj: for arbitrary time t c6Pankaj: Text added.
20 CHEMICAL KINETICS I: BASICS Fig. 2.1. Depletion of A with time.
da(t) dt = −ka(t)(∆+ a(t)) (2.8) We now solve this equation by the method of separation of variable: Z a(t) A0 da a(∆+ a) = −k Z t 0 dt0 (2.9) implying h ln a ∆+ a ia(t) A0 = −∆kt.
(2.10) which, after some algebraic manipulations, can be rewritten as a(t) = A0∆ B0e∆kt −A0 .
(2.11) c1. Since the time dependence in eqn 2.11 comes in only through the combination ∆kt, the problem has a characteristic time scale given by (∆k)−1 To understand the significance of this time scale, consider the the asymptotic dependence of a(t) on t. For large t, a(t) ⇡const. exp(−∆kt). Thus, (∆k)−1 sets the char-acteristic time scale for the decay of particles due to depletion of the reactant c1Pankaj: I significantly reworked paragraph and added clarifications REVERSIBLE REACTIONS 21 molecules. This is depicted graphically in Fig. 2.1 where we have plotted the so-lution to the equations above for the initial conditions A0 = 2, B0 = 3 and k = 1.
c2.
Exercise: As an aside, one could ask, what happens when ∆= 0. A re-alistic way to be in this situation is have a dimerization reaction, 2A!C. Show that, in that case, a(t) goes to zero as 1/t ( and not as an exponential) in the long time limit.
2.2 Reversible reactions Now consider the reversible reaction where A and B combine to make C but C can also dissociate back into A and B.
A + B k+ ⌦ k− C, (2.12) c1with k+ and k−the rate constants for the forward and backward reactions, respectively. In the case of the irreversible reaction discussed in the previous section, one of the two reactants gets completely depleted as time goes by. For a reversible reaction, an equilibrium with nonzero concentrations of all three species of chemicals is reached. c2 In particular, eqn 2.2 must be modified to include the reverse reaction and becomes d[C] dt = k+[A][B] −k−[C] (2.13) c3By definition, at equilibrium, the concentration of C does not change with time and d[C]/dt = 0, implying k+[A][B] = k−[C].
(2.14) Assume, once more that initially at time t = 0, [A] = A0, [B] = B0 and [C] = 0.
The conservation laws (eqns 2.4, 2.5 and 2.6) c4derived for the irreversible case are are valid even in the reversible case as well and imply that at equilibrium [A] + [C] = A0. c5We begin by rewriting equation 2.14 as [C] [A] = [B] Keq , (2.15) c2Pankaj: I think we should more explicit about exercises and mark them c1Pankaj: Text added.
c2Pankaj: Changed wording c3Pankaj: Text added.
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22 CHEMICAL KINETICS I: BASICS where c6we have defined the equilibrium constant, Keq = k−/k+. Using the equations above, it is easy to see that [C] A0 = [C] [C] + [A] = [B] [B] + Keq or [C] = A0[B] [B] + Keq , (2.16) c1where in writing the first equality we have used the conservation law 2.4.
Fig. 2.2. Saturation as a function of the concentration of reactant B for a reversible reaction.
Let us take a moment to ponder what equation 2.16 is telling us. It gives us a relation between the amount of C and the amount of free B (as opposed to initial amount of B, B0) at equilibrium. When [B] << Keq, we have an approximately linear relation between [C] and [B]. On the other hand, when [B] >> Keq, we have [C] approaches A0, as expected. The crossover between the two limits is depicted in Fig. 2.2.
c2 In practice, it is often useful to also have an expression for the equilibrium value of C as a function of the initial concentration of B0 and not just the concentration of free B, [B]. That expression is a solution of a quadratic equation and a bit more complicated than the rational functions in eqn 2.16. However, c6Pankaj: Text added.
c1Pankaj: Text added.
c2Pankaj: reworded this paragraph and added excercise REVERSIBLE REACTIONS 23 there are many situations where there is much more B than A, [B] ≫[A]. In this case, the di↵erence between [B] and B0 is negligible and we can replace [B] with B0.
Exercise: Derive an exact expression for the concentration of the product C as a function of B0. Show that when [B] ≫[A], replacing [B] with B0 in equation 2.16 is a good approximation.
c1 Now consider a more complicated reaction scheme: A + B k+ ⌦ k− C k ! A + D (2.17) When k = 0, the equation reduces to the reversible reaction considered above. In this case, we know that A, B and C would reach equilibrium with the equilibrium concentration of C given by equation 2.2. Now consider the case where k is much smaller than k+ and k−. In this case, A,B, and C will still quickly equilibrate since the production of D from C is slow compared to the reversible reaction.
Hence, a good approximation for the kinetics when k is nonzero but still small (k ⌧k±) is to model the the production rate of D as k times the equilibrium value of [C].
d[D] dt ⇡k[C] (2.18) When C is in equilibrium, we know that (k−+ k)[C] = k+[A][B].
(2.19) This equation is identical to equation 2.14 except for the replacement k−!
k−+ k. Hence, we know that the equilibrium value of [C] is given by Equation 2.16 except now Keq = (k−+ k)/k+. Thus, we can approximate the kinetics as d[D] dt ⇡k[C] = kA0[B] [B] + Keq .
(2.20) The approximation employed above is often referred to as the quasi-equilibrium approximation and will be discussed more below.
It is worth comparing equation 2.20 with equation 2.2 for the mass action kinetics of an irreversible process with no intermediate steps. Notice that where as the production rate of the product in equation 2.2 is linear in the concentration [B], the production rate of the product in equation 2.20 saturates as a function of [B] at large concentrations. This saturation e↵ect arises because the production of D is a multistep process and lies at the heart of Michaelis Menten kinetics discussed below. c2When [B] ≫[A], all the A molecules are quickly bound by the excess B molecules and the kinetics is limited only by the concentration of [A].
c1Pankaj: Completely reworded the rest of the section and added more clarifications, in particular clarified what is meant by Keq c2Pankaj: Text added.
24 CHEMICAL KINETICS I: BASICS 2.3 Michaelis Menten kinetics The reaction scheme 2.17 is nothing other than a generic catalytic reaction where B is converted into D by the catalyst A. A special class of catalytic reactions of great importance in biology are enzymes acting on their substrates. Written in more conventional notation, eqn 2.17 becomes E + S k+ ⌦ k− ES kcat ! E + P.
(2.21) The enzyme E captures the substrate S and makes a complex ES reversibly.
Occasionally the complex gives rise to the product P, a modification of the sub-strate, and releases the enzyme for further action. The rate of product formation is often expressed as d[P] dt = kcat[E]total[S] [S] + KM , (2.22) c1with KM = (k−+ kcat)/k.
In the conventional derivation of equation 2.22 from the reaction 2.21, one makes some implicit assumptions: • For calculating the rate of product formation, often called the initial ve-locity, the concentration of product can be neglected compared to that of the substrate (i.e [P] << [S]).
• The amount of the intermediate ES is approximately at equilibrium (the quasi-equilibrium condition).
The last assumption says that the loss of ES c2due to disassociation is balanced by the formation of new complexes..
(k−+ kcat)[ES] ⇡k+[E][S].
(2.23) This equation in conjunction with the exact conservation condition [E] + [ES] = [E]total (2.24) immediately imply that [ES] [E]total = 1 1 + k−+kcat k+[S] (2.25) Since d[P]/dt = kcat[ES], Michaelis Menten equation follows, once we identify the Michaelis constant KM to be (k−+ kcat)/k+. In practical applications, it is often assumed, in addition to conditions mentioned above, that the concentration c1Pankaj: Text added.
c2Pankaj: compensates the gain MICHAELIS MENTEN KINETICS 25 of substrate is in large excess over that of the enzyme (i.e. [E] << [S]), allowing us to ignore the di↵erence between the total amount of substrate molecules and the amount that is free.
c3 Exercise: This exercise examines the validity of the quasi-equilibrium condi-tion.
a) Derive a di↵erential equation for d[S] dt as a function of [S] within the quasi-equilibrium approximation.
b) Explicitly solve the di↵erential equation for [S] as a function of time for the initial conditions [P] = [ES] = 0 and [S] = S0 at t = 0.
c) Show that this solution does not satisfy the initial condition [ES] = 0 at t = 0.
d) Discuss what goes wrong with the quasi-equilibrium assumption. For a de-tailed explanation see Chapter 6 of Murray.
Much ink has been spent on the conditions under which this standard deriva-tion holds, or on how to derive it better. Instead of delving into these details, we will think of this formula as a phenomenological description, capturing the intuitive expectations in the limits of small or of large amount of substrates. For a small amount of substrates, the bottleneck is the enzyme and the substrate finding each other. Hence the rate is proportional to the product of [E]total and [S]. In the other limit, there is so much substrate that almost all the enzymes are in the complex ES. Hence the rate is just kcat[E]total. The Michelis constant, KM can be thought of, operationally, as the substrate concentration where the rate is half of the maximum value.
For a fixed amount of enzyme, [E]total, the velocity, v([S]) = d[P]/dt, satisfies 1 v([S]) = 1 vmax + KM vmax 1 [S].
(2.26) with vmax = kcat[E]total. Thus, the plotting inverse of velocity against inverse of substrate concentration is expected to produce a straight line. This plot, known as Lineweaver-Burk plot, is often used in enzyme kinetics. The slope and the intercept of the straight line fit to the data can be used to extract parameters like vmax and KM.
The tables 2.1 and 2.2 show that the values for the parameters KM and kcat vary widely from molecule to molecule. Note that when the concentration of the substrate is low compared to KM, the product formation rate is c1 kcat KM [E]total[S] = k+[E]total[S] ⇥ ✓ kcat kcat + k− ◆ .
(2.27) c3Pankaj: added excercise c1Pankaj: reworked paragraph below to separate efficiency from collisions more explicitly 26 CHEMICAL KINETICS I: BASICS Enzyme Substrate KM(µM) Chymotrypsin Acetyl-L-tryptophanamide 5000 Lysozyme Hexa-N-acetylglucosamine 6 β-Galactosidase Lactose 4000 Threonine deaminase Threonine 5000 Carbonic anhydrase CO2 8000 Penicillinase Benzylpenicillin 50 Pyruvate carboxylase Pyruvate 400S HCO− 3 1000 ATP 60 Arginine-tRNA synthetase Arginine 3 tRNA 0.4 ATP 300 Table 2.1 KM values for some enzymes and substrates (based on Biochem-istry by Berg, Tymoczko and Stryer ) c2This equation has a simple interpretation as the rate of collisions between en-zyme and substrate, k+[E]total[S], times the probability that a collision gives rise to a product. Thus, we see that the rate of the reaction is bounded above by the rate at which the substrate collides with the reactive pocket of the en-zyme. The chance of collision, on the other hand, is limited by the di↵usion rate (see exercise below). The highest observed values (kcat/KM) turns out to be in the range 108 −109s−1M−1. c3These numbers are the same order of magnitude expected from diffusion limited kinetics. These enzymes are believed to have achieved kinetic perfection, in the sense that every encounter with a substrate is highly likely to lead to the product. We will return to di↵usion-limited rates in the next chapter (also see exercise below).
c1 Excercise: This problem explores di↵usion limited fluxes. Consider a spherical cell of radius a immersed in a medium that contains molecules of a species X in a law concentration with di↵usion constant D. Furthermore, assume that the cell is a perfect sink. Show that the steady-state current of molecules into the cell is given by J = 4⇡aDc1, (2.28) where c1 is the concentration far from the cell assumed to be maintained at steady state. (Hint: Think about the analogy between the time-independent dif-fusion equation and Laplaces equation and use Gauss’s law.) Use the expression above to estimate the di↵usion limited value of kcat/KM for a small molecule substrate hitting the reactive pocket of an enzyme.
c2Pankaj: Text added.
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c1Pankaj: added excercise COOPERATIVITY 27 Enzyme kcat(s−1) Carbonic anhydrase 600,000 3-Ketosteroid isomerase 280,000 Acetylcholinesterase 25,000 Penicillinase 2,000 Lactate dehydrogenase 1,000 Chymotrypsin 100 DNA polymerase I 15 Tryptophan synthetase 2 Lysozyme 0.5 Table 2.2 kcat values for some enzymes (based on Biochemistry by Berg, Tymoczko and Stryer ) 2.4 Cooperativity In Michaelis Menten equation, the velocity rises approximately linearly with substrate abundance, till it reaches KM. For some reactions, the dependence of the rate on the substrate is strongly sigmoidal. A well known example, displaying such cooperativity, is th O2 binding of hemoglobin. c2. Cooperativity arises in proteins with multiple binding sites where the binding of ligand to binding site increases the affinity of the remaining binding sites for the substrate (see Exercise below on the MWC model). Regardless of the details of how cooperativity arises, the resulting sigmoidal behavior is often phenomenologically described using a Hill Function. We now give a brief derivation of the Hill equation and discuss how its used in chemical kinetics.
Consider a reaction scheme where the protein has to bind multiple substrate molecules before being productive.
E k1+[S] ⌦ k1− ES k2+[S] ⌦ k2− ES2 k3+[S] ⌦ k3− · · · kp+[S] ⌦ kp− ESp kcat ! E + P + other things.
(2.29) To solve of this problem in the quasi-equilibrium approach, we find that [ESl] [ESl−1] = kl+[S] kl− ) [ESl] = El (2.30) where, Kl = l Y i=1 ki− ki+ !1/l .
(2.31) Since the number of enzymes [E]total is conserved, this yields c2Pankaj: changed this around 28 CHEMICAL KINETICS I: BASICS Fig. 2.3. Velocity as a function of substrate concentration [S]: Hill equation compared to Michaelis Menten equation [ESp] [E]total = [ESp] [E] + [ES] + [ES2] + · · · + [ESp−1] + [ESp] = ) [S]/Kp)p 1 + ([S]/K1) + ([S]/K2)2 + · · · + ([S]/Kp−1)p−1 + ([S]/Kp)p (2.32) In the extreme case of cooperativity, binding of single substrate is unlikely, but once achieved, helps binding of additional substrates, which, in turn, makes further substrate binding easier. Thus, the protein spends most of its time in one of two states: E or ESp. In this case, the denominator in equation 2.32 is dominated by the constant term and the term going as [S]p and the velocity of product formation is given by v = d[P] dt = kcat[ESp] = vmax ) [S]/Kp)p 1 + ([S]/Kp)p , (2.33) with vmax = kcat[E]total. Equation 2.33 is called the Hill equation and p the Hill coefficient. Kp, like Michaelis constant, can be defined as the substrate concen-tration corresponding to the rate that is half of the maximum possible. Figure 2.3 shows how having a Hill coefficient of 4 gives a much more sigmoidal response when compared to the Michaelis Menten form.
In practice, the Hill coefficient is used as an extra parameter that is used provide better phenomenological description of a reaction rate. Therefore you COOPERATIVITY 29 should not be surprised to see, say, fractional Hill coefficients. These coefficients are often detemined from the slope of the Hill plot: ln[v/(vmax −v)] versus ln[S].
If the system is described by Hill equation, then ln v vmax −v = ln( [S] Kp )p = p ln[S] −p ln Kp.
(2.34) Unlike the Lineweaver-Burk plot, Hill plot requires one to estimate vmax, making fitting data a slightly more involved exercise.
Cooperative e↵ects in chemical reactions, like those described above, have important consequence for the dynamics of the whole network. As we will see later, biomolecular networks with strong cooperative e↵ects can, sometimes, show switch like behavior, a feature biological systems use to accomplish certain goals.
The Hill equation will play an important role in description of such systems.
c1 Exercise: This exercise introduces the Monod-Wyman-Changeux (MWC) model of allosteric interactions. The MWC model was first proposed to explain the sigmoidal response of hemoglobin to oxygen and has since become one of the canonical models allostery in biochemistry and biophysics. The main idea of the model is that an enzyme or protein can exist in multiple, interconvertible conformations with the probability that the enzyme is in a given confirmation determined by thermal equilibrium. The presence of ligands biases the enzyme towards one of these confirmations by shifting the relative free energies of the underlying protein confirmations.
In this exercise, we will derive the main results of the MWC model from simple thermodynamic and statistical mechanical arguments. This problem assumes knowledge of partition functions.
a) Consider an protein with a single conformational state that can bind a ligand [L] from the environment. In thermal equilibrium, show that the free energy di↵erence, ∆F, between the bound and unbound state is given by ∆F = −log [L] KD , (2.35) with KD = k−/k+, k+ the ligand binding rate, and k−is the ligand unbinding rate. KD is called the binding affinity of the protein b) Now consider a protein that can exist in two states, an active state A, and an inactive state I. In the absence of ligand, the free energy of the active state is ✏A and the inactive state is ✏I. Furthermore, denote the binding affinity of the pro-tein in the active state by KA D and the binding affinity in the inactive state KI D.
Calculate the probability that the protein is in the active state. Show that in the limit where ligand binding strongly favors the active state KI D ≫[L] ≫KA D, this expression reduces to a form similar to the Michaelis Menten equation. Briefly c1Pankaj: Added a problem on MWC model because I think every biophysicist should know this model 30 CHEMICAL KINETICS I: BASICS discuss the meaning of KM and the relationship to the Michaelis Metin equation.
c) Generalize the calculation in b) to the case when the protein is composed on 2 independent, identical subunits each of which can bind ligand. For this case, there are 8 total possible states: the protein can be active or inactive with 0,1, or 2 ligands bound to the protein. Show that when KI D ≫[L] ≫KA D, your ex-pression reduces to a form similar to the Hill equation with a Hill coefficient of 2. Discuss the relationship of the MWC model to the derivation in the main text.
d) Repeat the calculation in c) for the case a protein is composed of p inde-pendent subunits each of which can bind a ligand molecule.
For an interesting application of the MWC model to describe quantitative data on bacterial chemotaxis, see the papers by Wingreen.
c2 Exercise: In this exercise, we will explore the concept of kinetic proof reading.
Kinetic proofreading is an error-correction mechanism introduced by John Hop-field to understand the high fidelity of translation. The original paper Hopfield 1974 is considered a classic and deserves a close reading.
Kinetic proofreading allows enzyme to discriminate between two substrates with a small free energy di↵erences with higher specificity than would be ex-pected by simple thermodynamic arguments. The basic idea behind kinetic proof-reading is to introduce extra “irreversible” steps leading to the formation of the product. Since at each step the true substrate is much less likely to disassociate from the complex than the wrong substrate, the addition of extra intermediate steps leads to increased specificity. In particular, for each extra step, the speci-ficity can be increased by a factor proportional to the ratio of the disassociation constants of the two substrates.
To see how this works, consider an enzyme E that can bind two substrates A and B found in equal concentrations with kinetic constants kA ± and kB ±, with A the “correct” substrate and B, the “incorrect” substrate: E + A kA + ⌦ kA − EA k ! AP + E (2.36) E + B kB + ⌦ kB − EB k ! BP + E.
(2.37) In general, since the forward rates are often di↵usion limited, it is reasonable to assume kA + ⇡kB + and the di↵erence in specificity between the two substrates comes from a di↵erence in disassociation constants, kB −> kA −. This gives a lower-bound on the error rate.
a) Use the quasi-equilibrium approximation to calculate the error rate, F. In c2Pankaj: Added a problem on Kinetic proofreading because it is a good application and really important idea COOPERATIVITY 31 particular, show that F = F0 = KA/KB where KA and KB are the equilibrium constants for the two reactions.
b) Now consider a reaction scheme where one forms an irreversible intermediate.
In practice, this is often done by explicitly consuming energy through phospho-rylating the intermediate. The reaction schemes now take the form E + A kA + ⌦ kA − EB m ! EA⇤ # kA − E + A k !AP + E, (2.38) with an analogous scheme for B. Again, assuming a quasi-equilibrium approxi-mation for the intermediates, show that the error rate is now given by F = F 2 0 .
What is the error rate when the intermediate is formed by a reversible reaction?
c) How does the answer generalize for the case on m high-energy intermediates? |
12533 | https://math.libretexts.org/Bookshelves/Combinatorics_and_Discrete_Mathematics/Applied_Discrete_Structures_(Doerr_and_Levasseur)/03%3A_Logic/3.03%3A_Equivalence_and_Implication | Skip to main content
3.3: Equivalence and Implication
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: Aug 16, 2021
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3.2: Truth Tables and Propositions Generated by a Set
3.4: The Laws of Logic
Page ID
: 80506
Al Doerr & Ken Levasseur
University of Massachusetts Lowell
( \newcommand{\kernel}{\mathrm{null}\,})
Consider two propositions generated by and and At first glance, they are different propositions. In form, they are different, but they have the same meaning. One way to see this is to substitute actual propositions for and such as I've been to Toronto; and I've been to Chicago.
Then translates to “I haven't been to both Toronto and Chicago,” while is “I haven't been to Toronto or I haven't been to Chicago.” Determine the truth values of these propositions. Naturally, they will be true for some people and false for others. What is important is that no matter what truth values they have, and will have the same truth value. The easiest way to see this is by examining the truth tables of these propositions.
Table : Truth Tables for and
| | | (\neg (p\land q)\0 | |
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In all four cases, and have the same truth value. Furthermore, when the biconditional operator is applied to them, the result is a value of true in all cases. A proposition such as this is called a tautology.
Tautologies and Contradictions
Definition: Tautology
An expression involving logical variables that is true in all cases is a tautology. The number 1 is used to symbolize a tautology.
Example : Some Tautologies
All of the following are tautologies because their truth tables consist of a column of 1's.
Definition: Contradiction
An expression involving logical variables that is false for all cases is called a contradiction. The number 0 is used to symbolize a contradiction.
Example : Some Contradictions
and are contradictions.
Equivalence
Definition: Equivalence
Let be a set of propositions and let and be propositions generated by and are equivalent if and only if is a tautology. The equivalence of and is denoted
Equivalence is to logic as equality is to algebra. Just as there are many ways of writing an algebraic expression, the same logical meaning can be expressed in many different ways.
Example : Some Equivalences
The following are all equivalences:
All tautologies are equivalent to one another.
Example : An Equivalence to
All contradictions are equivalent to one another.
Example : An Equivalence to
Implication
Consider the two propositions:
Table
| |
| : The money is behind Door A; and |
| : The money is behind Door A or Door B |
Imagine that you were told that there is a large sum of money behind one of two doors marked A and B, and that one of the two propositions and is true and the other is false. Which door would you choose? All that you need to realize is that if is true, then will also be true. Since we know that this can't be the case, must be the true proposition and the money is behind Door B.
This is an example of a situation in which the truth of one proposition leads to the truth of another. Certainly, can be true when is false; but can't be true when is false. In this case, we say that implies
Consider the truth table of Table 3.1.1. If implies then the third case can be ruled out, since it is the case that makes a conditional proposition false.
Definition: Implication
Let be a set of propositions and let and be propositions generated by We say that implies if is a tautology. We write to indicate this implication.
Example : Disjunctive Addition
A commonly used implication called “disjunctive addition” is which is verified by truth table Table .
Table : Truth Table to verify that
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If we let represent “The money is behind Door A” and represent “The money is behind Door B,” is a formalized version of the reasoning used in Example . A common name for this implication is disjunctive addition. In the next section we will consider some of the most commonly used implications and equivalences.
When we defined what we mean by a Proposition Generated by a Set, Definition 3.2.1, we didn't include the conditional and biconditional operators. This was because of the two equivalences and Therefore, any proposition that includes the conditional or biconditional operators can be written in an equivalent way using only conjunction, disjunction, and negation. We could even dispense with disjunction since is equivalent to a proposition that uses only conjunction and negation.
Universal Operation
We close this section with a final logical operation, the Sheffer Stroke, that has the interesting property that all other logical operations can be created from it. You can explore this operation in Exercise
Definition: The Sheffer Stroke
The Sheffer Stroke is the logical operator defined by the following truth table:
Table : Truth Table for the Sheffer Stroke
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Exercises
Exercise
Given the following propositions generated by and which are equivalent to one another?
Answer
Exercise
Construct the truth table for
Give an example other than itself of a proposition generated by and that is equivalent to
Give an example of a proposition other than that implies
Give an example of a proposition other than that is implied by
Exercise
Is an implication equivalent to its converse? Verify your answer using a truth table.
Answer
: No. In symbolic form the question is: Is
This table indicates that an implication is not always equivalent to its converse.
Exercise
Suppose that is a proposition generated by and that is equivalent to Write out the truth table for
Exercise
How large is the largest set of propositions generated by and with the property that no two elements are equivalent?
Answer
: Let be any proposition generated by and The truth table for has 4 rows and there are 2 choices for a truth value for for each row, so there are possible propositions.
Exercise
Find a proposition that is equivalent to and uses only conjunction and negation.
Exercise
Explain why a contradiction implies any proposition and any proposition implies a tautology.
Answer
: and are tautologies.
Exercise
The significance of the Sheffer Stroke is that it is a “universal” operation in that all other logical operations can be built from it.
Prove that is equivalent to
Prove that
Build using only the Sheffer Stroke.
Build using only the Sheffer Stroke.
3.2: Truth Tables and Propositions Generated by a Set
3.4: The Laws of Logic |
12534 | https://kolypto.github.io/campbell-biology/chapters/07-Membrane-Structure-and-Function.html | View on GitHub
campbell-biology
Campbell Biology. 11th Edition (2017)
Chapter 7. Membrane Structure and Function
7.1. Cellular membranes are fluid mosaics of lipids and proteins
The currently accepted model of the plasma membrane: the fluid mosaic model. It is continually being refined.
Membranes are composed of: lipids, proteins, some carbohydrates.
Phospholipids have an ability to form membranes between two aqueous compartments: it is inherent in their molecular structure. They are amphipathic: have a hydrophilic and a hydrophobic region.
Most membrane proteins are amphipathic as well: their orientation maximizes contact of hydrophilic regions with water, while providing their hydrophobic parts with a nonaqueous environment.
Proteins are not randomly distributed: they are often grouped in long-lasting, specialized patches, where they carry out common functions.
The Fluidity of Membranes
Most of the lipids and some proteins in the membrane can shift about sideways because the membrane is held together by weak hydrophobic bonds. Like partygoers elbowing their way through a crowded room.
The movement is rapid: a phospholipid can travel the length of a typical bacteria (2μm) in 1 second. Proteins are larger and move more slowly, when they move. Many membrane proteins seem to be held immobile by their attachment to the cytoskeleton or to the extracellular matrix.
Some proteins drift in the membrane; others seem to move in a highly directed manner, perhaps driven along cytoskeletal fibers by motor proteins.
Very rarely, also, a lipid may flip-flop across the membrane, switching from one phospholipid layer to the other.
A membrane remains fluid until temperature decreases to a certain point, when it solidifies. This point depends on the types of lipids it’s made of: unsaturated hydrocarbon tails have kinks that cannot pack as closely together, making the membrane more fluid.
Embedded cholesterol also controls membrane fluidity: at high temperatures (37℃) it makes the membrane less fluid by restraining phospholipid movement, and it also hinders the close packing of phospholipids at lower temperatures, lowering the temperature required for the membrane to solidify.
Thus, cholesterol can be thought of a “fluidity buffer” for the membrane, resisting changes in membrane fluidity that can be caused by changes in temperature.
Membranes must be fluid to work properly: the fluidity of a membrane affects both its permeability and the ability of membrane proteins to move to where their function is needed.
Usually, membranes are about as fluid as olive oil.
Membrane Lipid Composition Adaptation
The ability to change the lipid composition of cell membranes in response to changing temperatures has evolved in organisms that live where temperatures vary. In many plants that tolerate extreme cold, such as winter wheat, the percentage of unsaturated phospholipids increases in autumn: an adjustment that keeps the membranes from solidifying during winter.
Cold-water fishes have a high proportion of unsaturated phospholipids in their membranes as well. As the other extreme, some bacteria that thrive in thermal hot springs include unusual lipids that may prevent excessive fluidity at such high temperatures.
Membrane Proteins and Their Functions
More than 50 kinds of proteins have been found in the plasma membrane of red blood cells.
Proteins determine most of the membrane’s functions.
The majority of integral proteins (that are inserted into the membrane) are transmembrane proteins, which span the membrane. Their hydrophobic regions consist of stretches of nonpolar amino acids, usually coiled into α-helices, while the hydrophilic parts of the molecule are exposed to the aqueous solutions. Some proteins also have hydrophilic channels that allow pasaage through the membrane of hydrophilic substances, even of water itself.
Bacteriorhodopsin: a bacterial transfer protein.
Peripheral proteins are not embedded in the lipid bilayer at all: they are loosely boudn to the surface of the membrane, often to exposed parts of integral proteins.
On the cytoplasmic side of the membrane, some proteins are held in place by attachment to the cytoskeleton. On the outside, membrane proteins may attach to other materials: e.g. in animal cells, membrane proteins may be attached to fibers of the extracellular matrix to give animal cells a stronger framework than the plasma membrane alone could provide.
The following figure illustrates 6 major functions performed by proteins of the plasma membrane. A protein may carry out multiple functions.
Surface proteins are important in the medical field. For example, it was discovered that some people, despite multiple exposures to HIV, do not develop AIDS and show no evidence of HIV-infected cells. Comparing their genes with the genes of infected individuals, researchers learned that resistant people have an unusual form of a gene that codes for an immune cell-surface protein called CCR5. Further work showed that although the CD4 protein on the surface of immune cells helps HIV infect those cells, HIV must also bind to CCR5 as a “co-receptor” to infect most cells. An absence of CCR5 on the cells of resistant individuals, due to gene alteration, prevents the virus from entering the cells.
This information has been key to developing a treatment for HIV: interfering with CD4 causes dangerous side-effects because of its many important functions in cells; CCR5 is a safer target for development of drugs that mask this protein and block HIV entry.
The Role of Membrane Carbohydrates in Cell-Cell Recognition
Cell recognition is a cell’s ability to distinguish one type of neighboring cell from another. It is important, for example, in the sorting of cells into tissues and organs in an animal embryo. It is also the basis for the rejection of foreign cells by the immune system.
Cells recognize other cells by binding to molecules on the surface of the plasma membrane. These molecules are usually short, branched, chains of carbohydrates, bonded to lipids (forming glycolipids) or proteins (forming glycoproteins).
These carbohydrate tags vary from species to species; they also vary among individuals of the same species; they even vary from one cell type to another in a single individual. Such diversity makes them sufficiently unique to function as markers that distinguish one cell from another.
For example, the four human blood types, designated A, B, AB, and O, reflect variation in the carbohydrate part of the glycoproteins on the surface of red blood cells.
Synthesis and Sidedness of Membranes
The two lipid layers of the membrane may differ in lipid composition, and each integral protein has directional orientation in the membrane. The asymmetrical arrangement is determined as the membrane is being built.
7.2. Membrane structure results in selective permeability
A membrane exhibits selective permeability: that is, it allows some substances to cross more easily than others.
The Permeability of the Lipid Bilayer
Nonpolar molecules (CO₂, O₂, lipids) are hydrophobic and can therefore dissolve in the lipid bilayer and cross it easily without the aid of membrane proteins.
Polar molecules (sugars, water) can still cross the membrane, but slowly. A charged atom or molecule and its surrounding shell of water are even less likely to penetrate the hydrophobic interior of the membrane.
Transport Proteins
Channel proteins create a hydrophilic channel that some polar molecules and ions can use as a tunnel through the membrane.
For example, aquaporins facilitate the passage of water molecules in certain cells. Molecules can pass through it single-file. It allows ~3 billion water molecules per second. Without aquaporins, only a tiny fraction of these water molecules would pass through the same area of the cell membrane.
Carrier proteins hold on to their passengers and change shape in a way that shuttles them across the membrane.
A transport protein is specific for the substance it translocates (moves). For instance, a glucose transport protein in the plasma membrane of red blood cells is so selective that it even rejects fructose, its structural isomer.
7.3. Passive transport is diffusion of a substance across a membrane with no energy investment
7.4. Active transport uses energy to move solutes against their gradients
7.5. Bulk transport across the plasma membrane occurs by exocytosis and endocytosis |
12535 | https://www.expii.com/t/factoring-quadratic-xbxc-negative-b-4499 | Expii
Factoring Quadratic x²+bx+c Negative b - Expii
The signs in a quadratic determine the sign of the factors. If b is negative and c is positive in x^2+bx+c, the factors will have a -.
Explanations (3)
Vinitha Ranganeni
Text
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When tasked with factoring a polynomial of the form x2+bx+c (where b is negative), you first must determine what two numbers equal c when multiplied together but equal b when added together. Remember, this is different from x2+bx+c, when b is positive.
For instance, let's say that we want to factor the polynomial x2+bx+c (again, where b is negative), and let's also say that we have found two numbers d and e such that −d⋅−e=c and −d+(−e)=b.
We then rewrite our polynomial as
x2−dx−ex+c, use parentheses to group x2−dx and ex−c, and factor out greatest common factors from both those pairs of terms.
This should give us an expression that consists of two terms, both of which are being multiplied by the same binomial. Once we have factored out that binomial, we should be left with an expression consisting of two binomials that are being multiplied together: this is the factored form of our polynomial.
Example 1:
x2−3x+2
Since −2⋅−1=2 and −2+(−1)=−3, we can rewrite our polynomial as follows:
x2−2x−1x+2
Now, we factor out greatest common factors from our polynomial's first two terms and from our polynomial's last two terms:
x(x−2)−1(x−2)
Finally, we factor the binomial x−2 out of our expression (note that we are only able to do this because our expression consists of two terms that are both being multiplied by the binomial x−2):
(x−1)(x−2)
Example 2:
x2−6x+9
=x2−3x−3x+9
=x(x−3)−3(x−3)
=(x−3)(x−3)
=(x−3)2
This one looks like a perfect square trinomial!
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Factor Perfect Square Trinomial - Examples & Practice
Factoring Quadratic x²+bx+c with c<0
Factoring Difference of Squares - Definition & Examples
Factoring Quadratic ax²+bx+c with ac<0
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Stefan Cuevas
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Visual Model of Factoring
Take notice of what b<0 and c>0 mean. This means the coefficient in front of x, which we call b is less than 0, and the constant that stands alone is greater than 0. In other words, b is negative and c is positive. This means, when we factor ax2−bx+c=(?x−?)(?x−?). Let's look at a modeling example of the factoring of x2−5x+6.
Image source: by Stefan Cuevas
This pattern for factoring can be used for any quadratic equation that follows the pattern ax2−bx+c.
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Alex Federspiel
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(Video) Factoring Trinomials
by mathman1024
This video by mathman1024 goes over some examples of factoring quadratics that contain a mix of addition and subtraction.
Summary
The first quadratic our instructor shows us how to factor is x2−10x+21. As he demonstrates in the video above, in order to begin factoring this quadratic, we must look at the quadratic's first term (x2) and figure out what two terms multiply to it.
Since our main goal in factoring our quadratic is to rewrite the expression as the product of two binomials, and since both of those binomial factors must contain at least one term that consists of one or more variables, our quadratic's first term can only be broken down into the terms x and x. We then use those two terms as the first two terms of our quadratic's factors:
x2−10x+21=(x )(x )
Now, we need to figure out what signs our quadratic's factors will contain. We know that the last terms of our quadratic's factors will have to multiply to 21, a positive number. We also know that multiplying two numbers only yields a positive result when those two numbers are either both positive or both negative. This means that the last terms of our quadratic's factors must be either both positive or both negative.
We determine this by looking to our quadratic's middle term, −10x. Since the last terms of our quadratic's factors must add up to the coefficient of our quadratic's middle term, and since adding two positive numbers together will never give us a negative number, it must be the case that our quadratic's factors have last terms that are both negative:
x2−10x+21=(x− )(x− )
Next, in order to figure out the numeric value of those last terms, we first must list all the pairs of values we can break our quadratic's last term into. In other words, we need to list the factors of 21:
12137
Again, when factoring a quadratic, we must ensure that the last terms of the quadratic's factors add up to the coefficient of its middle term.
So, which of those pairs of factors we listed above adds up to 10? Yup, it's 3 and 7. We now take those two values and use them to complete our quadratic's factors:
x2−10x+21=(x−3)(x−7)
After factoring the quadratic x2−10x+21, our instructor goes over some additional factoring examples that require you to pay close attention to sign.
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What is the difference between oxygenation and oxidation?
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Oxygenation and oxidation are related concepts in chemistry, but they refer to different processes:
Oxygenation
Definition: Oxygenation is the process of adding oxygen to a substance or system.
Context: It often refers to biological processes, such as the oxygenation of blood, where oxygen is absorbed into the bloodstream from the lungs.
Example: In environmental science, oxygenation can refer to the dissolution of oxygen in water, which is crucial for aquatic life.
Oxidation
Definition: Oxidation is a chemical reaction that involves the loss of electrons from a substance. It is often associated w
Continue Reading
Oxygenation and oxidation are related concepts in chemistry, but they refer to different processes:
Oxygenation
Definition: Oxygenation is the process of adding oxygen to a substance or system.
Context: It often refers to biological processes, such as the oxygenation of blood, where oxygen is absorbed into the bloodstream from the lungs.
Example: In environmental science, oxygenation can refer to the dissolution of oxygen in water, which is crucial for aquatic life.
Oxidation
Definition: Oxidation is a chemical reaction that involves the loss of electrons from a substance. It is often associated with the addition of oxygen to a compound, but it can also occur without oxygen.
Context: Oxidation is a key concept in redox (reduction-oxidation) reactions, which are fundamental to many chemical processes, including combustion, respiration, and corrosion.
Example: When iron rusts, it undergoes oxidation as it reacts with oxygen in the presence of water to form iron oxide.
Summary
Oxygenation: Focuses on the addition of oxygen, especially in biological or environmental contexts.
Oxidation: Involves the loss of electrons and can occur with or without oxygen, playing a central role in chemical reactions.
Understanding the distinction is important in fields like biochemistry, environmental science, and chemistry.
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What is the difference between oxydation and oxygenation?
Oxidation has nothing to do with oxygen. Is it the right statement? If yes then how?
Why does oxygen cause oxidation?
When something reacts with oxygen, does oxidation happen?
What is the difference between oxide and oxygen?
Tomás Bohn Pessatti
Ph.D in Biochemistry&Molecular Biology, Federal University of Santa Catarina (UFSC) (Graduated 2022) · Upvoted by
Jerome Zoeller
, Ph.D. Chemistry, The University of Texas at Austin (1968) · Author has 107 answers and 304.7K answer views
·7y
Oxygenation, as stated before, is adding gaseous oxygen (O2) to a system. Also can describe chemical reactions involving molecular oxygen.
On the other hand, oxidation does not necessarily involves the presence of oxygen. Oxidation (and reduction) are a type of chemical reaction called redox reaction. These reactions always involve an electron transfer between a pair of substances , one being oxidized (losing electrons), and the other being reduced (accepting electrons). You can find more about oxidation state at Oxidation state - Wikipedia. Long story made short: oxidation is to lose electrons
Continue Reading
Oxygenation, as stated before, is adding gaseous oxygen (O2) to a system. Also can describe chemical reactions involving molecular oxygen.
On the other hand, oxidation does not necessarily involves the presence of oxygen. Oxidation (and reduction) are a type of chemical reaction called redox reaction. These reactions always involve an electron transfer between a pair of substances , one being oxidized (losing electrons), and the other being reduced (accepting electrons). You can find more about oxidation state at Oxidation state - Wikipedia. Long story made short: oxidation is to lose electrons, while reduction is to accept them, but this reactions are always coupled!!!
The thing is, in a redox reaction, the chemical species being reduced (accepting electrons) is also oxidizing the other reactant, so it’s called the oxidizing agent. The other way around, the chemical species being oxidized (loosing electrons) is also reducing the other reactant, thus being called the reducing agent.
Making it simpel:
Oxidizing agent: = the chemical species that gets reduced (gets electrons) by oxidizing the other reactant.
Reducing agent = the chemical species that gets oxidized (gives electrons) by reducing the other reactant.
As oxygen has a very strong affinity for electrons, it is usually involved in redox reactions as the oxidizing agent, but NOT ALL REDOX REACTIONS involve oxygen! You cant read more about it at Redox - Wikipedia.
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Arsh
Studied at Kendriya Vidyalaya · Author has 58 answers and 210.5K answer views
·5y
Originally Answered: What is the difference between oxidation and oxygenation? ·
Hope it may be helpful for you.
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Hope it may be helpful for you.
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Guy Clentsmith
Studied Chemistry at The University of British Columbia · Author has 9.7K answers and 1.4M answer views
·Jul 6
Well, oxygenation involves the reaction of a species with dioxygen. And oxidation involves an INCREASE in the oxidation of the element as the free element or the element in the reactant species, that is an INDICATOR in elemental . ovidation number. Sometimes, both processes occur in the same reaction.
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Does an oxidation reaction always involve oxygen?
How does oxidation occur without oxygen?
What does the word "oxi" mean in "oxidation" and "antioxidant"? Does it have to do with oxygen?
Are oxidation and discolouration the same thing?
What is oxidation, and what are some examples?
James Harvey
BSc in Chemistry, The University of York (Graduated 2021) · Author has 93 answers and 503.1K answer views
·7y
Originally Answered: What is the difference between oxide and oxygen? ·
Oxygen is a molecule of 2 oxygen atoms covalently bonded together with a double-bond. It exists as a molecule in the atmosphere.
Each oxygen atom shares 2 electrons with the other, which makes it a double bond.
Oxide is a singular oxygen atom with 2 electrons added (an ion). It exists inside ionic compounds like iron oxide, copper oxide etc.
Continue Reading
Oxygen is a molecule of 2 oxygen atoms covalently bonded together with a double-bond. It exists as a molecule in the atmosphere.
Each oxygen atom shares 2 electrons with the other, which makes it a double bond.
Oxide is a singular oxygen atom with 2 electrons added (an ion). It exists inside ionic compounds like iron oxide, copper oxide etc.
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Mike Adams
Forty years of research. · Upvoted by
Łukasz Golon
, PhD student of chemistry · Author has 6.5K answers and 3.6M answer views
·8y
Oxygenation is a physical property that refers to the amount of dissolved oxygen in a system; or the process of increasing it. Oxidation is a chemical concept that originally referred to the addition of oxygen to an element or compound, but now is usually take to mean the loss of electrons or an increase in oxidation state.
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Ahmad Umama Jafri
Studied Bachelor of Medicine and Bachelor of Surgery Degrees · Author has 749 answers and 869.5K answer views
·5y
Oxygenation is a type of oxidation. If oxygenation is taking place then it's an oxidation but if oxidation is taking place then it's not necessary that it's oxygenation as well.
Oxidation is the increase in oxidation number. It maybe Lead losing electrons and becoming Pb+2 as in big batteries or the corrosion of iron. But oxygenation is that type of oxidation in which there is addition of Oxygen in the compound, as in addition of Oxygen to carbon resulting in formation of carbon dioxide.
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Stuart Herring
Author has 11.7K answers and 8.2M answer views
·7y
Originally Answered: What is the difference between oxgenation and oxidation? ·
What is the difference between oxygenation and oxidation?
Oxygenation is the adding of oxygen to a mixture or solution.
Oxidation is the chemical combination of oxygen with another kind of atom.
(Oxidation also refers to the removal of electrons from an atom, by the action of a more electronegative atom. It does not require actual oxygen, though; sulfur and the halogens, for example, are also good oxidizers.)
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Jaap Folmer
Lives in Raleigh, NC (1999–present) · Author has 8.8K answers and 10M answer views
·5y
Originally Answered: What is the difference between oxydation and oxygenation? ·
Oxygenation is the process of increasing the concentration on dissolved molecular O 2 O 2 , e.g. by bubbling air through water.
Oxidation is the increase in oxidation number of a species or atom by depriving it of one or more valence electrons.
Oxidation does not have to involve molecular oxygen at all, although it can. It is a chemical reaction. Oxygenation is not.
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Myriam Kobylkevich
Analytical Chemist (1978–present) · Author has 2.8K answers and 4.1M answer views
·5y
Originally Answered: What is the difference between oxydation and oxygenation? ·
You oxygenate the water of your aquarium by dissolving in the water some air (containing about 21% oxygen). That is just dissolving oxygen in the air so the fish can breathe.
You oxidize an iron nail by letting the iron chemicallycombine with oxygen to form rust in a chemical reaction.
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Neeraj Kumar Jat
Physics Teacher at Privet Job (2016–present)
·6y
Originally Answered: What is the difference between oxygen and oxide? ·
Oxygen is the single element found in p-block of periodic table. And oxide is the compound of oxygen and other element from periodic table.
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Guy Clentsmith
Chemistry tutor... at Self-Employment (2018–present) · Author has 26.5K answers and 19.7M answer views
·Updated 6y
Related
Oxidation has nothing to do with oxygen. Is it the right statement? If yes then how?
Oxygen gas is an oxidizing agent; in fact it is a POTENT oxidizing agent, however, oxidation DOES NOT require oxygen.
Oxidation signifies the formal loss of electrons, or an increase in so-called oxidation number oxidation number, and this a number conceived to be the number of electrons LOST or GAINED in a redox process. And we introduce electrons to represent the change in the number of electrons lost (oxi
Continue Reading
Oxygen gas is an oxidizing agent; in fact it is a POTENT oxidizing agent, however, oxidation DOES NOT require oxygen.
Oxidation signifies the formal loss of electrons, or an increase in so-called oxidation number oxidation number, and this a number conceived to be the number of electrons LOST or GAINED in a redox process. And we introduce electrons to represent the change in the number of electrons lost (oxidation), or electrons gained (reduction) during a redox reaction.
Again, in the oxidation of say carbon to carbon dioxide, elemental carbon, the which has formal oxidation number of 0 0 (i.e. the element has neither lost nor gained electrons) is OXIDIZED to C(+I V)C(+I V) in carbon dioxide…
C(s)+2 H 2 O→C O 2+4 H++4 e−C(s)+2 H 2 O→C O 2+4 H++4 e−
And dioxygen gas, O(0)O(0), is REDUCED to O 2−O 2−, a two electron reduction…
1 2 O 2+2 e−→O 2−1 2 O 2+2 e−→O 2−
For BOTH redox equations, charge and mass are balanced ABSOLUTELY… we add the oxidation equation to TWO EQUIV of the reduction equation in order to eliminate the electrons, which are virtual particles of convenience… and so …
[math]C(s)+O_{2} +4e^{-} +2H_{2}O \rightarrow CO_{2...
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Harold Zwanepol
Former Natural Selection Intervention Specialist · Author has 8K answers and 14.7M answer views
·5y
Originally Answered: What is the difference between oxydation and oxygenation? ·
Oxydation is the French form of the English word oxidation, a form of chemical reaction.
Oxygenation is the addition of oxygen to a system.
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Related questions
What is the difference between oxydation and oxygenation?
Oxidation has nothing to do with oxygen. Is it the right statement? If yes then how?
Why does oxygen cause oxidation?
When something reacts with oxygen, does oxidation happen?
What is the difference between oxide and oxygen?
Does an oxidation reaction always involve oxygen?
How does oxidation occur without oxygen?
What does the word "oxi" mean in "oxidation" and "antioxidant"? Does it have to do with oxygen?
Are oxidation and discolouration the same thing?
What is oxidation, and what are some examples?
What is the difference between oxidation and oxydization?
If I put 9 ventilators in a room, will it improve oxygenation?
What does rapid oxidation mean?
What's the difference between ionisation and oxidation?
If oxygen is vital for life, then why is oxidation so deadly?
Related questions
What is the difference between oxydation and oxygenation?
Oxidation has nothing to do with oxygen. Is it the right statement? If yes then how?
Why does oxygen cause oxidation?
When something reacts with oxygen, does oxidation happen?
What is the difference between oxide and oxygen?
Does an oxidation reaction always involve oxygen?
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The edges of a parallelepiped are of unit length and are parallel to non-coplanar unit vectors $\hat{a},\hat{b},\hat{c}$ such that $\hat{a}\cdot \hat{b}=\hat{b}\cdot \hat{c}=\hat{c}\cdot \hat{a}=\dfrac{1}{2}$ then the volume of the parallelepiped is, (a) $\dfrac{1}{\sqrt{2}}$ (b) $\dfrac{1}{2\sqrt{2}}$ (c) $\dfrac{\sqrt{3}}{2}$ (d) $\dfrac{1}{\sqrt{3}}$
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Volume
How to Calculate the Volume of a Rectangular Prism
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Plus practice problems for finding a rectangular prism’s volume
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Finding Volume
| Using Cube Units
| Sample Problems
| Common Mistakes
| What is a rectangular prism?
| Other Volume Formulas
| FAQs
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Volume is the amount of three-dimensional space taken up by an object. The computer or phone you're using right now has volume, and even you have volume! Finding the volume of a rectangular prism is actually really easy. Just multiply the length, the width, and the height of the rectangular prism or box that you want the volume of. That's all you have to do! But, this article will walk you through every step of this calculation, including what to do if you don’t know the dimensions of the prism. Calculators at the ready!
Volume of a Rectangular Prism: Formula
Calculate the volume of a rectangular prism by multiplying its width, length, and height together (in any order). Make sure all units are the same across the dimensions, then plug them into the formula Volume = W x L x H.
Steps
Section 1 of 7:
Finding the Volume of a Rectangular Prism (With Known Dimensions)
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1
Identify the length, width, and height of the rectangular prism. If you’ve been given a rectangular prism with stated dimensions, then it should be easy to find the length, width, and height of the box. If your box isn’t already labeled, draw a rectangular prism on a piece of paper and label the length, width, and height so they’re easier to keep track of throughout your calculations.
The length is the longest side of the flat surface of the rectangle on the top or bottom of the rectangular prism.
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The width is the shorter side of the flat surface of the rectangle on the top or bottom of the rectangular prism.
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The height is the part of the rectangular prism that rises up. Imagine that the height is what stretches up a flat rectangle until it becomes a three-dimensional shape.
For example, your box may have these dimensions: length (l) = 5 inches, width (w) = 4 inches, and height (h) = 3 inches.
2. 2
Multiply together the length, width, and height to find the volume. Multiply the three dimensions of a rectangular prism in any order to get the shape’s total volume. This calculation can also be done by plugging the dimensions into the formula for finding the volume of a rectangular prism, which is Volume = length x height x width, or V = l x h x w.
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For example, let’s say that your rectangular prism has the dimensions length (l) = 5 inches, width (w) = 4 inches, and height (h) = 3 inches.
To calculate this rectangular prisms volume, multiply 5 x 4 x 3 = 60. The volume of this box is 60.
These numbers can be calculated in any order. For instance, multiplying 3 x 5 x 4 would produce the same final value of 60.
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3. 3
Write your final answer in cubic units. Since you're calculating volume, you're working in a three-dimensional space. As a result, you must state your answer in cubic units.
X
Research source Identify whether the original dimensions of the rectangular prism were in feet, inches, centimeters, or another unit of measurement.
Then, write the number value of your volume, followed by that measurement with the exponent 3 attached to it.
For example, the rectangular prism in our example has its dimensions stated in inches. Therefore, our final answer with units would be Volume = 60 in3.
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Section 2 of 7:
Finding the Volume of a Rectangular Prism (With Cube Units)
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If you’re only given cube units, start by identifying the side length of a single cube. The space inside of a rectangular prism is made up of cube units, meaning that a rectangular prism can be visualized as a 3D shape with many smaller cubes fitting inside it—almost like a 3-dimensional grid inside the prism.
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Research source If you’ve been given a rectangular prism problem where the prism is divided up into cubes and you’re only given the side length of each cube, follow this set of steps.
Start by making note of the given side length of each small cube inside the rectangular prism.
In our example, we’ll say that each of the cubes in the prism has a side length of 1 inch.
2. 2
Decide how many cubes make up the bottom layer of the prism. Look at the bottom layer of the rectangular prism. Count how many cubes are included in the long side of the prism. Then, count how many cubes are included on the short side.
For example, our rectangular prism has a 9 cubes on its long side and 2 cubes on its short side.
If you’re struggling to visualize this process by counting cubes on the 3-dimensional shape, imagine what it would look like if you picked up the prism and looked at the bottom. What would the dimensions of that bottom rectangle be?
In our example, you would see a 9 by 2 rectangle.
If you have MathLink Cubes or something similar on hand, it may be helpful to physically build your prism out of cubes to better visualize it and its dimensions.
3. 3
Determine the length and width of the prism’s bottom layer. Now that you know how many cubes make up the long and short sides of the prism’s bottom layer, you can determine the prism’s total length and width.
To find the length, multiply the side length of your cubes by the number of cubes on the long side of the bottom layer.
+ For example, our rectangular prism has cubes with a side length of 1 inch, and there are 9 cubes on the long side of the rectangle. Therefore, our prism’s length = 1 inch x 9 = 9 inches.
To find the width, multiply the side length of your cubes by the number of cubes on the short side of the bottom layer.
+ For example, our rectangular prism has cubes with a side length of 1 inch, and there are 2 cubes on the long side of the rectangle. Therefore, our prism’s length = 1 inch x 2 = 2 inches.
4. 4
Calculate the volume of the rectangular prism’s bottom layer. You now have the length and width of the bottom layer of your prism. You also know that layer’s height, which is equal to the side length of a single cube. To find the volume of that layer (just that layer—not the entire prism), multiply length by width by height.
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For example, in a rectangular prism with a bottom layer whose dimensions are 9 inches (length) by 2 inches (width) by 1 inch (height), you’d calculate Volume = 9 x 2 x 1 = 18.
Since our original cube side-length was given in inches and volume is always measured in cubic units, our bottom layer’s final volume with units would be Volume = 18 inches3
5. 5
Add together the volume of each layer to find the prism’s total volume. You now know the volume of the bottom layer of the prism. The great news is that every layer has the same volume—so we’re almost there! Count the total number of layers in your prism, then add together your volume answer from the previous amount of steps that amount of times.
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For example, let’s say that our rectangular prism has 2 layers of cubes.
Since we already know that the bottom layer has a volume of 18 inches3, all we have to do is add that value together 2 times.
Therefore, the total volume of the rectangular prism is 18 inches3 + 18 inches3 = 36 inches3
6. 6
Make sure to include cubic units when writing down your final answer. Determine the original units of the rectangular prism (e.g, inches, centimeters, feet, etc.). Write the final volume in cubic units matching your original units.
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If your original units were in inches: in3
If your original units were in centimeters: cm3
If your original units were in feet: ft3
In our example, the original units were given in inches, making our final answer 36 in3.
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Section 3 of 7:
Practice Questions for Rectangular Prism Volume
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Problem #1: Find the volume of a rectangular prism with these dimensions: length = 6 inches, width = 10 inches, height = 8 inches. Solution:
Write down the formula for the volume of a rectangular prism: Volume = length x height x width, or V = l x h x w.
Plug your dimensions into the formula: Volume = 6 x 8 x 10.
Solve the formula through multiplication: V = 480.
Add cubic units to match the original units (in this case, inches): V = 480 inches3.
The final volume of this rectangular prism is 480 inches3.
2. 2
Problem #2: Find the volume of a cube with a side length of 6 feet. Solution:
Identify the length, width, and height of the cube: Cubes have faces and sides that are all equal to each other. Therefore, the side length of the cube being 6 feet means that all of the cubes side lengths (including length, width, and height) are 6 feet.
Write down the formula for the volume of a rectangular prism: Volume = length x height x width, or V = l x h x w.
Plug your dimensions into the formula: Volume = 6 x 6 x 6.
Solve the formula through multiplication: V = 216.
Add cubic units to match the original units (in this case, feet): V = 216 feet3.
The final volume of this rectangular prism is 216 feet3.
3. 3
Problem #3: Find the volume of a rectangular prism with these dimensions: length = 4 meters, width = 2 meters, height = 50 centimeters. Solution:
Convert your dimensions into the same units: Note that all dimensions must be in the same unit before calculating the volume of a rectangular prism.
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Research source Since our height is given in centimeters (not meters), we must convert this number into meters before continuing:
50 centimeters = 0.5 meters.
If you can’t convert units off of the top of your head, use a unit conversation calculator.
Write down the formula for the volume of a rectangular prism: Volume = length x height x width, or V = l x h x w.
Plug your adjusted dimensions into the formula: Volume = 4 x 2 x 0.5.
Solve the formula through multiplication: V = 4.
Add cubic units to match the original units (in this case, meters): V = 4 meters3.
The final volume of this rectangular prism is 4 meters3.
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Section 4 of 7:
Common Mistakes When Solving for Volume
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Calculating surface area instead of volume Surface area and volume are two different ways to measure a rectangular prism. Surface area is the total area of the rectangular faces on the outside of the shape, while volume is the total space within the shape.
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2. 2
Writing incorrect units or forgetting to include units When writing a measurement, you must always include the units along with the number value. For volume, always use cubic units: e.g., in3, cm3, mm3, m3, etc.
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3. 3
Calculating volume with mismatched units To calculate the volume of a rectangular prism (or any shape), all of the measurements must be in the same units. For example, let’s say a prism has the dimensions 1 inch x 2 inch x 3 feet. The 3 feet must be converted into inches before volume can be calculated.
If you’re studying for a test, it may be best to memorize the unit conversions you’ll need for your exam.
Otherwise, however, you can always use a unit converter calculator to fix your units.
4. 4
Thinking that converting units affects the volume If you calculate the volume of a rectangular prism with its dimensions written in centimeters, you’ll get a different number value as an answer than if you calculated the same rectangular prism’s volume with its dimensions written in meters. However, this difference doesn’t change the actual value of the prism’s volume, or the amount of space it's taking up.
The difference in numbers only has to do with the differing units—not because the actual volume of the prism has changed.
Consider if you had a cardboard box in front of you. You could use a ruler to measure that box in inches or a measuring tape to measure it in feet. You would get a different answer, but the size of the box wouldn’t actually change.
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Section 5 of 7:
What is a rectangular prism?
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A rectangular prism is a 3D shape with all rectangular faces. Also known as a box or a cuboid, a rectangular prism is a 3-dimensional shape with 8 vertices, 12 edges, and 6 faces.
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Research source Some real-life examples of a rectangular prism include the storage area of a truck, a chest of drawers, an aquarium, a book, and any square-shaped cardboard box.
A cube is also a type of rectangular prism.
Section 6 of 7:
More Formulas for Volume & Rectangular Prisms
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Review or learn related math formulas and skills. Here are some handy formulas to know when calculating the surface area, volume, and other dimensions of important shapes (plus, you can see the entire step-by-step process by clicking on the links below):
Calculate the Area of a Rectangle: A = width (w) x length (l)
Find the Surface Area of a Rectangular Prism: SA = 2(wl+hl+hw)
Calculate Volume of a Prism: V = B (base) x h (height)
Calculate Volume of a Cube: V = a3, where a = edge
Calculate Volume of a Triangular Prism: V = 0.5 x B x h x l
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Section 7 of 7:
Frequently Asked Questions About Volume & Rectangular Prisms
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When can the formula for finding the volume of a rectangular prism be used in real life? The formula for the volume of a rectangular prism can be used for any real-life scenario where you need to know how much space is inside of or taken up by a 3D rectangular shape or box.
For instance, say you bought a box-shaped fish tank. If you want to know how much water you need to fill that tank, use the rectangular prism volume formula.
In another example, you may want to construct a raised garden bed and fill it with potting soil. To know how much potting soil you’ll need, plug the dimensions of your bed into the rectangular prism volume formula.
Or, maybe you’re going on a dream vacation and need to choose between two suitcases. If you want to know which suitcase would fit more inside it, calculate the volume of each one and see which number value is largest.
2. 2
How do I find the height of a rectangular prism when given its volume? If you are given the volume of the rectangular prism but not its height, you can use this formula to solve for height: Volume (V) = base area (B) x height (h).
For example, if you know that the volume of a prism is 200 cubic units and the base area is 20 square units, then plug those values into the equation.
Then, you’ll have the formula 200 = 20 x h.
To solve for h, divide both sides of the equation by 20 to be left with 10 = h.
Therefore, the height of the rectangular prism is 10 units!
3. 3
What happens to the volume of a rectangular prism if its length, width, and height are doubled? If the length, width, and height of a rectangular prism are all doubled, then its volume will be eight times its original value.
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To explain this result, consider the original formula for the volume of a rectangular prism: V = length x width x height.
If all of the dimensions are doubled, the volume will then be (2l) x (2w) x (2h) = 8lwh = 8 x V.
As a result, the volume will be 8 x V, or 8 times its original value.
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If l=45, w=15, h=x, how do I find the volume?
Donagan
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You have to know the height. Otherwise, you'd have to say the volume is 675x cubic units.
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Can you give me another example? I still don't get it.
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Remember that length x width x height. A rectangular prism that is five inches high, ten inches long, and two inches deep will have a volume of 100 square in. 5x10x2=100.
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How can I calculate the dimension when I know the volume?
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The rectangle's area, times the prism's height vertical to the rectangle, gives the volume; various combinations of dimensions give the same volume, so if you know the volume, and want the dimensions, you will find many sets of dimensions. For example volume 24 could give the length, width, and height of 2, 2, and 6; or 2, 3, 4; or 1, 1, 24; and so on.
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In the United States public school system, calculating the volume of a rectangular prism is typically first taught as a math skill in the 5th grade (according to Common Core State Standards). Then, it’s reinforced and expanded upon in 6th grade.
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If you’re teaching a student how to calculate the volume of a rectangular prism, try to focus on activities that show the cube units within a rectangular prism so that the student can really understand why volume is calculated the way it is. Be sure to also teach real-life applications for this problem to students.
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About This Article
Reviewed by:
Grace Imson, MA
Math Teacher
This article was reviewed by Grace Imson, MA and by wikiHow staff writer, Sophie Burkholder, BA. Grace Imson is a math teacher with over 40 years of teaching experience. Grace is currently a math instructor at the City College of San Francisco and was previously in the Math Department at Saint Louis University. She has taught math at the elementary, middle, high school, and college levels. She has an MA in Education, specializing in Administration and Supervision from Saint Louis University. This article has been viewed 1,312,918 times.
9 votes - 80%
Co-authors: 36
Updated: August 14, 2024
Views: 1,312,918
Categories: Volume
Article SummaryX
Find the length, width, and height of the rectangular prism.
Multiply the length, width, and height to get the volume.
Write the answer in cubic units.
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Reviewed by:
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Co-authors: 36
Updated: August 14, 2024
Views: 1,312,918
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"I thought I was going to have some more late homework, not anymore. This is my first year for accelerated seventh grade math. This really helped, thanks."..." more
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Top 3 Methods for Solving Systems of Equations
Top 3 Methods for Solving Systems of Equations (Video)
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Hey, guys! Welcome to this video over comparing different methods for solving a system of equations.
If you recall, a system of equations is when you have more than one equation with unknown variables in a given problem. So, in order to solve that problem, you need to be able to find the value of all the variables in each equation.
Substitution, Elimination, and Augmented Matrix
There are three different ways that you could do this: the substitution method, elimination method, and using an augmented matrix.
In this video, I’m assuming that you already know how to perform each method, so I want to spend a lot of time explaining not how to do them but rather when to use each method.
First, I will verbally tell you when to use each method, then I will write out three different examples, and we will decide together which method is most efficient for each system.
When to Use the Substitution Method
You should use the substitution method when one of the variables in one of your equations has already been isolated (it has a coefficient of 1).
When to Use the Elimination Method
You should use the elimination method when the same variables in all of the equations share the same coefficient, or when they share the same but negative coefficient.
When to Use an Augmented Matrix
You would use an augmented matrix when the substitution and elimination method are either impractical or impossible altogether.
Now, let’s look at three different systems, and use what we’ve just learned to think through which method is most useful for each system.
EXAMPLE SYSTEM #1 (5x – 58y = -883) (-5x + 2y = -13)
EXAMPLE SYSTEM #2 (9x + 4y = 65) (x – 18y = -2)
EXAMPLE SYSTEM #3 (2x + 7y – 3z = 47) (x – 4y + 8z = -33) (7x + 2y +10z = 11)
So, what we will do is go through each system, decide which method would be most efficient, and then solve with that method.
Elimination Method Example
Alright, let’s look at this first equation.
(5x – 58y = -883)(-5x + 2y = -13)
Now, thinking back to the explanation I gave on when to use each method, notice what I said about elimination: “You should use the elimination method when the same variables in all of the equations share the same coefficient, or when they share the same but negative coefficient.”
Well this exact thing is true in the case of this particular system. So, let’s solve this system using elimination.
(-56y = -896)(y = 16)
Now, we plug our (y)-variable back into one of the original equations. I’ll plug it into the first.
(5x – 58(16) = -883)(5x – 928 = -883)(5x = 45)(x = 9)
Great, so we’ve solved this system using elimination, because our same two variables had the same coefficient or when they share the same but negative coefficient (like in our case).
Substitution Method Example
Let’s move on to system #2.
(9x + 4y = 65)(x – 18y = -2)
Alright, so again, let’s think back on what was said in our explanation on when to use each method. Recall what was said about substitution: “You should use the substitution method when one of the variables in one of your equations has already been isolated.”
Well, such is the case with this system. Our (x)-variable in our second equation has a coefficient of 1. So, let’s solve this system using substitution.
(9(18y – 2) + 4y = 65)(162y – 18 + 4y = 65)(166y = 83)(y = \frac{1}{2})(x = 18(\frac{1}{2}) – 2)(x = 7)
That was very simple to solve using substitution. Remember, the signifier to help you know when to use it is if one of the equations has a variable that is already isolated.
Augmented Matrix Example
Let’s look at our last system, system #3.
(2x + 7y – 3z = 47)(x – 4y + 8z = -33)(7x + 2y +10z = 11)
Remember, what we said about when to use an augmented matrix. Well, right now is a good time. Using elimination or substitution for that matter would take a lot more work than would using an augmented matrix.
So, let’s set up our matrix and solve.
(\begin{bmatrix} \left.\begin{matrix} 2& 7& -3\ 1& -4& 8\ 7& 2& 10 \end{matrix}\right| & \begin{matrix} 47\ -33\ 11 \end{matrix} \end{bmatrix})(R_{1}\leftrightarrow R_{2})(\begin{bmatrix} \left.\begin{matrix} 1& -4& 8\ 2& 7& -3\ 7& 2& 10 \end{matrix}\right| & \begin{matrix} -33\ 47\ 11 \end{matrix} \end{bmatrix}) (\begin{matrix} \ -2R_{1}+R_{2}=R_{2}\ -7R_{1}+R_{3}=R_{3} \end{matrix}\begin{bmatrix} \left.\begin{matrix} 1& -4& 8\ 0& 15& -19\ 0& 30& -46 \end{matrix}\right| & \begin{matrix} -33\ 113\ 242 \end{matrix} \end{bmatrix}) (\begin{matrix} \ \frac{R_{2}}{15}=R_{2}\ \end{matrix}\begin{bmatrix} \left.\begin{matrix} 1& -4& 8\ 0& 1& \frac{-19}{15}\ 0& 30& -46 \end{matrix}\right| & \begin{matrix} -33\ \frac{113}{15}\ 242 \end{matrix} \end{bmatrix}) (\begin{matrix} 4R_{2}+R_{1}=R_{1}\ \ -30R_{2}+R_{3}=R_{3} \end{matrix}\begin{bmatrix} \left.\begin{matrix} 1& 0& \frac{44}{15}\ 0& 1& \frac{-19}{15}\ 0& 0& -8 \end{matrix}\right| & \begin{matrix} \frac{-43}{15}\ \frac{113}{15}\ 16 \end{matrix} \end{bmatrix}) (\begin{matrix} \ \ \frac{R_{3}}{-8}=R_{3} \end{matrix}\begin{bmatrix} \left.\begin{matrix} 1& 0& \frac{44}{15}\ 0& 1& \frac{-19}{15}\ 0& 0& 1 \end{matrix}\right| & \begin{matrix} \frac{-43}{15}\ \frac{113}{15}\ -2 \end{matrix} \end{bmatrix}) (\begin{matrix} -\frac{44}{15}R_{3}+R_{1}=R_{1}\ \frac{19}{15}R_{3}+R_{2}=R_{2}\ \end{matrix}\begin{bmatrix} \left.\begin{matrix} 1& 0& 0\ 0& 1& 0\ 0& 0& 1 \end{matrix}\right| & \begin{matrix} 3\ 5\ -2 \end{matrix} \end{bmatrix}\begin{bmatrix} x\ y\ z \end{bmatrix})
(x=3), (y=5), (z=-2)
I hope that this video over the comparison of methods for solving systems was helpful for you.
See you guys next time!
Frequently Asked Questions
Q
What is a system of equations?
A
Systems of equations are two or more equations that can be used to solve one another.
Example:
(\begin{align}3x+4 &= y\ 2x+3y &= -9\end{align})
Q
How do you do the substitution method?
A
The substitution method of solving linear equations involves substituting one equation for a variable in the other equation, solving for one of the variables, and then using that variable and one of the original equations to solve for the other variable.
Example:
Solve: (2x + 3y = 15) and (y = 2x + 1)
Substitute (2x + 1) for (y)
(2x + 3(2x + 1) = 15)
Solve for (x)
(2x + 3(2x + 1) = 152x + 6x + 3 = 158x + 3 = 158x = 12x = 3)
Solve for (y) by substituting 3 for (x) in either original equation
(y = 2(3) + 1 = 6 + 1 = 7)
The solution to these two equations is the point ((3, 7)).
Q
How do you do the elimination method?
A
To use the elimination method of solving systems of equations, manipulate one of the equations so it can be added to, or subtracted from, the other equation where one variable will cancel out. Then, solve for the other variable. Finally, use that variable to solve for the one that originally was eliminated.
Ex. Solve: (\begin{align}3x-2y &= 14\ 6x-7y &= 11\end{align})
First, multiply the top equation by -2.
(-2(3x-2y=14))(-6x+4y=-28)
Then, add the two equations.Solve for y by dividing by -3 on both sides.
(y=\dfrac{17}{3})
Then, substitute y in either original equation to solve for x.
(3x-2(\frac{17}{3})=14)(3x-\frac{34}{3}=14)(3x-\frac{34}{4}=\frac{42}{3})(3x=\frac{76}{3})(x=\frac{76}{9})
The solution to this system is the point ((\frac{76}{9},\frac{17}{3})).
Q
What is an augmented matrix?
A
An augmented matrix is formed by appending the entries from one matrix onto the end of another.
Example:
(M=\begin{bmatrix}1&2\3&4\end{bmatrix}, I=\begin{bmatrix}1&0\0&1\end{bmatrix})
Augmented Matrix:
(\begin{bmatrix}1&2&|1&0\3&4&|0&1\end{bmatrix})
Systems of Equations Practice Questions
Question #1:
Solve the system of equations by substitution: (2x-y=12) (x-y=3)
((3, 2))
((6, 9))
((12, 3))
((9, 6))
Answer:
The correct answer is D: ((9, 6)).Let’s start by solving the second equation for (x).(x−y=3) becomes (x=3+y).
Now that we have isolated (x), we can substitute this in for “(x)” in the other equation in order to solve for (y).(2x−y=12) becomes (2(3+y)−y=12)
From here we can solve for (y) because we are now only dealing with one variable.(2(3+y)−y=12) becomes (y=6)
Now that we have solved for (y), we can plug this value into one of the original equations in order to solve for (x). Let’s use the first original equation: (2x−y=12).
(2x−y=12) becomes (2x−6=12) and when we isolate the variable (x), we end up with (x=9).Our solution is the ordered pair ((9, 6)).
Question #2:
Solve the system of equations using substitution. (2x+3y=12) (x+y=5)
((2, 3))
((3, 2))
((5, 12))
((12, 5))
Answer:
The correct answer is B: ((3, 2)).
Let’s start by solving the second equation for x. (x+y=5) becomes (x=−y+5)
Now that we have isolated x, we can substitute this in for “x” in the other equation in order to solve for y. (2x+3y=12) becomes (2(−y+5)+3y=12)
From here we can solve for y because we are now only dealing with one variable.(2(−y+5)+3y=12) becomes (y=2)
Now that we have solved for y, we can plug this value into one of the original equations in order to solve for x. Let’s use the second original equation: (x+y=5).
(x+y=5) becomes (x+(2)=5) and when we isolate the variable x, we end up with (x=3).
Our solution is the ordered pair ((3, 2)).
Question #3:
Solve the system of equations by elimination: (2x+3y=15) (x−3y=3)
((1, 6))
((3, 5))
((6, 1))
((5, 3))
Answer:
The correct answer is C: ((6, 1)).
Elimination is a useful strategy for this system of equations because we can see that the terms 3y and -3>em>y will cancel out. Let’s begin the process by adding the two equations.
Since 3y and -3y cancel out, we are left with (3x=18), which simplifies to (x=6). From this point we can simply plug in 6 for “x” in either equation in order to solve for “y”.
Let’s use the second original equation: (x−3y=3).(x−3y=3) becomes ((6)−3y=3)
From here we can isolate the variable y. (y=1)
The solution is the ordered pair ((6, 1)).
Question #4:
The admission fee at an amusement park is $2.50 for children and $4.50 for adults. On Monday 2,000 people entered the amusement park and $8,000 was collected. How many children and how many adults went to the amusement park on Monday?
1,000 Children and 1,000 Adults
500 Children and 1,500 Adults
400 Children and 1,600 Adults
800 Children and 1,200 Adults
Answer:
The correct answer is B: 500 Children and 1,500 Adults.
We can solve for the number of adults and children by setting up a system of equations. Let’s set up two equations, one for the number of people and one for the cost. Let’s have “a” represent adults and “c” represent children.
(a+c=2,000)(4.5a+2.5c=8,000)
From here it appears that the substitution method would be most efficient because we have coefficients of 1. Let’s solve the first equation for a. Now we have (a=2,000–c).
We can plug in this value for “a” into the other equation.
(4.5(2,000-c)+2.5c=8,000)
From here we can isolate the variable c.
(c=500)
Now that we have solved for c, we can plug 500 in for c in either of the original equations. Let’s use the first equation. (a+c=2,000) becomes (a+500=2,000) which means (a=1,500)
The number of children is 500 and the number of adults is 1,500.
Question #5:
A potter is selling bowls and cups at an art fair. This morning he sold 30 bowls and 4 cups and made a total of $1,040. Later in the afternoon he sold 8 bowls for a total of $256. Find the price per bowl and cup.
Bowl = $32, Cup = $20
Bowl = $35, Cup = $22
Bowl = $12, Cup = $30
Bowl = $34, Cup = $24
Answer:
The correct answer is A: Bowl = $32, Cup = $20.
We can solve for the number of cups and bowls by setting up a system of equations. Two equations that match the scenario would be: (30B+4C=1,040) and (8B=256) where “B” represents bowls and “C” represents cups.
Let’s solve the second equation for B. (8B=256) becomes (B=32)
From this point we can substitute 32 into the other equation for “B”. (30B+4C=1,040) becomes (30(32)+4C=1,040)
We can now solve for C. (C=20)
Bowls cost $32 and cups cost $20.
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Polymorphism and Classes in Python
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Asked 8 years, 5 months ago
Modified8 years, 5 months ago
Viewed 2k times
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I am having trouble completing this assignment for school. This picture is what the output should be when complete.
Here is the problem I am tasked with:
"In the main.py file creates four objects. (vehicle, sedan, truck, hatchback) The main.py should have a main function and a function to display the contents of each object. It should also use the isinstance function to test for valid data (Tennis shoes is not a vehicle!) In the vehicle.py file create a superclass called Automobile and three subclasses (sedan, truck, and hatchback) The Automobile class should have three attributes (make,engine_type and drive_type. Figure 2 shows the values for these attributes as Basic Sedan, 6 cylinders, Front Wheel. Sedan subclass should inherit the Automobile class and override the engine type. Truck and hatchback subclasses should inherit the Automobile class and override both the engine type and drive type."
Here is my classes file named vehicles
```python
create a superclass named Automobile
class Automobile:
#the __init__method accepts an argument for the automobiles make
def __init__(self, make, engine_type, drive_type):
self.__make = make
self.__engine_type = engine_type
self.__drive_type = drive_type
def show_make(self):
print('Automobile Make:', self.__make)
def show_drive_type(self):
print(self.__drive_type)
def show_engine_type(self):
print(self.__engine_type)
class Sedan(Automobile):
def __init__(self, make, engine_type, drive_type):
Automobile.__init__(self, make, engine_type, drive_type)
def engine_type(self):
print('4 cylinder')
def drive_type(self):
Automobile.__init__(self)
class Truck(Automobile):
def __init__(self, make, engine_type, drive_type):
Automobile.__init__(self, make, engine_type, drive_type)
def engine_type(self):
print('8 cylinder')
def drive_type(self):
print('Four Wheel')
class Hatchback(Automobile):
def __init__(self, make, engine_type, drive_type):
Automobile.__init__(self, make, engine_type, drive_type)
def engine_type(self):
print('Electric')
def drive_type(self):
print('All Wheel')
```
And here is my main file with my main function inside
```python
import the vehicles file with classes
import vehicles
define the main function
def main():
#create an Automobile object, and all subclass objects
automobile = vehicles.Automobile('Sedan', '6 Cylinder', 'Front Wheel')
sedan = vehicles.Sedan()
truck = vehicles.Truck()
hatchback = vehicles.Hatchback()
#display information about each one
print('Here are some vehicles and their engine types.')
print()
show_auto_info(automobile)
print()
show_auto_info(sedan)
print()
show_auto_info(truck)
print()
show_auto_info(hatchback)
print()
show_auto_info('Tennis Shoes')
define the show_auto_info function
def show_auto_info(car):
if isinstance(car, vehicles.Automobile):
car.show_make()
car.show_drive_type()
car.show_engine_type()
else:
print(car, 'is not a vehicle!')
main()
```
This is the error that i'm getting:
Automobile.__init__(self)
TypeError: __init__() missing 3 required positional arguments: 'make', 'engine_type', and 'drive_type'
Process finished with exit code 1
python
class
polymorphism
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edited Apr 18, 2017 at 20:53
ClassicalclownClassicalclown
asked Apr 18, 2017 at 20:33
ClassicalclownClassicalclown
73 1 1 gold badge 3 3 silver badges 11 11 bronze badges
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if you are using python 3, you can use super().__init__()lmiguelvargasf –lmiguelvargasf 2017-04-18 20:34:24 +00:00 Commented Apr 18, 2017 at 20:34
I haven't learned that yet and not sure how I would implement that into my code to fix my error Classicalclown –Classicalclown 2017-04-18 20:35:22 +00:00 Commented Apr 18, 2017 at 20:35
the problem is that you are inheriting from class Automobile, so the signature in the child class should match the signature of the parent class.lmiguelvargasf –lmiguelvargasf 2017-04-18 20:36:35 +00:00 Commented Apr 18, 2017 at 20:36
so should I change the arguments under the functions for each under the automobile class? Such as def show_make, show_engine_type, show_drive_type?Classicalclown –Classicalclown 2017-04-18 20:39:54 +00:00 Commented Apr 18, 2017 at 20:39
I have provided a answer, I hope this helps.lmiguelvargasf –lmiguelvargasf 2017-04-18 20:41:14 +00:00 Commented Apr 18, 2017 at 20:41
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Okey... you are a little lost here... your code brokes, but it will be broken again, so I will be some steps ahead:
```python
create a superclass named Automobile
class Automobile:
#the __init__method accepts an argument for the automobiles make
def __init__(self, make, engine_type, drive_type):
self.__make = make
self.__engine_type = engine_type
self.__drive_type = drive_type
def show_make(self):
print('Automobile Make:', self.__make)
def show_drive_type(self):
print(self.__drive_type)
def show_engine_type(self):
print(self.__engine_type)
class Sedan(Automobile):
def __init__(self, make, engine_type, drive_type):
Automobile.__init__(self, make, engine_type, drive_type)
def engine_type(self):
self.__engine_type = '4 cylinder'
return self.__engine_type
def drive_type(self):
return self.drive_type
class Truck(Automobile):
def __init__(self):
Automobile.__init__(self, 'Truck', None, None)
def engine_type(self):
self.__engine_type = '8 cylinder'
return self.__engine_type
def drive_type(self):
self.__drive_type = 'Four Wheel'
return self.__drive_type
class Hatchback(Automobile):
... same here
```
Notice that I put some return inside the methods, that's because you latter must do some extra method that print you the car description.
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edited Apr 18, 2017 at 20:56
answered Apr 18, 2017 at 20:47
developer_hatchdeveloper_hatch
16.3k 3 3 gold badges 46 46 silver badges 79 79 bronze badges
3 Comments
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Classicalclown
ClassicalclownOver a year ago
So I tried this and it still doesn't work. Do i need to change anything inside the main function?
2017-04-18T21:02:37.647Z+00:00
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developer_hatchOver a year ago
Yes, obviuesley... I let the Hatch car work so you can work with it, all the other problems are solved, tell me if you don't understand something from the code
2017-04-19T19:34:08.067Z+00:00
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developer_hatchOver a year ago
I add to you the Main Class, but it will work with my previus code, ok?
2017-04-19T19:36:45.343Z+00:00
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The problem is that your subclass does not have the same signature as your parent class, so considering Automobile class is this:
```python
class Automobile:
#the __init__method accepts an argument for the automobiles make
def __init__(self, make, engine_type, drive_type):
self.__make = make
self.__engine_type = engine_type
self.__drive_type = drive_type
# rest of the class
```
Your child class let's say Sedan should be:
```python
class Sedan(Automobile):
def __init__(self, make, engine_type, drive_type):
super().__init__(make, engine_type, drive_type)
```
However, if you want to make this code compatible with Python 2 and 3 you could use:
```python
class Sedan(Automobile):
def __init__(self, make, engine_type, drive_type):
Automobile.__init__(self, make, engine_type, drive_type)
```
If you want more information about extending a class in Python you can check this.
Update:
When creating an object of your subclass, use this
python
sedan = vehicles.Sedan('make_value', 'engine_type_value', 'drive_type_value')
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edited May 23, 2017 at 11:54
CommunityBot
1 1 1 silver badge
answered Apr 18, 2017 at 20:38
lmiguelvargasflmiguelvargasf
71k 55 55 gold badges 231 231 silver badges 239 239 bronze badges
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Classicalclown
ClassicalclownOver a year ago
Oh okay, so each class needs to have the exact same arguments as the superclass? Will this be the same if i need to overwrite certain aspects of the superclass with each subclass such as a different engine_type etc?
2017-04-18T20:41:21.653Z+00:00
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lmiguelvargasf
lmiguelvargasfOver a year ago
@Classicalclown, at least the same arguments in the superclass, you can add more arguments that are specific to your subclass.
2017-04-18T20:42:12.03Z+00:00
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Classicalclown
ClassicalclownOver a year ago
I went ahead and did what you said but I'm still getting an error
2017-04-18T20:53:39.033Z+00:00
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Classicalclown
ClassicalclownOver a year ago
The same as before. I updated my code and when I run the main function, it still does the same thing. I also provided a picture of what the output should be.
2017-04-18T21:09:00.67Z+00:00
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lmiguelvargasf
lmiguelvargasfOver a year ago
@Clasicalclown, I have updated my answer, your problem is that when you create an object of a child class you are not passing all the parameters.
2017-04-18T21:11:33.643Z+00:00
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This is how the Main Method should look like, you must end the rest of the code by yourself with this, if you don't understand my code, write me again and I will explain to you
Main Class:
```python
import the vehicles file with classes
import vehicles
define the main function
def main():
#create an Automobile object, and all subclass objects
automobile = vehicles.Automobile('Sedan', '6 Cylinder', 'Front Wheel')
sedan = vehicles.Sedan('Sedan', '24 Cylinder', 'amaizing car')
truck = vehicles.Truck()
#display information about each one
print('Here are some vehicles and their engine types.')
print()
show_auto_info(automobile)
print()
show_auto_info(sedan)
print()
show_auto_info(truck)
show_auto_info('Tennis Shoes')
define the show_auto_info function
def show_auto_info(car):
if isinstance(car, vehicles.Automobile):
car.show_make()
car.show_drive_type()
car.show_engine_type()
else:
print(car, 'is not a vehicle!')
main()
```
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answered Apr 19, 2017 at 19:35
developer_hatchdeveloper_hatch
16.3k 3 3 gold badges 46 46 silver badges 79 79 bronze badges
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Classicalclown
ClassicalclownOver a year ago
The only problem with your code is that you aren't overwriting the basic sedan superclass, you're just passing arguments for different attributes into the main function when I need to just pass the arguments that are different for each type of vehicle
2017-04-19T21:13:20.74Z+00:00
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developer_hatch
developer_hatchOver a year ago
Mmmm, I'm not follow, could you write for me please what's you wished String output after the main() execution? What shoul it be? Maybe I didn't understand the ptoblem
2017-04-20T13:20:51.2Z+00:00
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12541 | https://hellothinkster.com/math-tutor/lcm/lcm-of-3-and-4 | Math Tutor Explains: What is the LCM of 3 and 4? | Thinkster Math
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Lcm Of 3 And 4
Math Tutor Explains: What is the LCM of 3 and 4?
Your math tutor is here to explain! The Least Common Multiple (LCM) of two or more numbers is the smallest number that all the given numbers can divide into evenly. In other words, the LCM of 3 and 4 is the smallest value that both 3 and 4 can divide exactly, without leaving a remainder. Let’s explore how to find it!
Math Tutor Solution: The LCM of 3 and 4 is 12
Methods
How to find the LCM of 3 and 4 using Prime Factorization
As your math tutor, I'm here to guide you through this problem! To find the LCM of 3 and 4, one effective method is comparing their prime factorizations. Start by breaking each number down into its prime factors. Follow these steps to determine the prime factorization of each number:
What are the Factors of 3?
What are the Factors of 4?
Here is the prime factorization of 3:
3 1 3^1 3 1
And this is the prime factorization of 4:
2 2 2^2 2 2
When you compare the prime factorization of these two numbers, you want to look for the highest power that each prime factor is raised to. In this case, there are these prime factors to consider: 3, 2
2 2×3 1=12 2^2 × 3^1 = 12 2 2×3 1=12
Through this we see that the LCM of 3 and 4 is 12.
How to Find the LCM of 3 and 4 by Listing Common Multiples
The first step to this method of finding the Least Common Multiple of 3 and 4 is to begin to list a few multiples for each number. If you need a refresher on how to find the multiples of these numbers, you can see the walkthroughs in the links below for each number.
Let’s take a look at the multiples for each of these numbers, 3 and 4:
What are the Multiples of 3?
What are the Multiples of 4?
Let’s take a look at the first 10 multiples for each of these numbers, 3 and 4:
First 10 Multiples of 3: 3, 6, 9, 12, 15, 18, 21, 24, 27, 30
First 10 Multiples of 4: 4, 8, 12, 16, 20, 24, 28, 32, 36, 40
You can continue to list out the multiples of these numbers as long as needed to find a match. Once you do find a match, or several matches, the smallest of these matches would be the Least Common Multiple. For instance, the first matching multiple(s) of 3 and 4 are 12, 24, 36. Because 12 is the smallest, it is the least common multiple.
The LCM of 3 and 4 is 12.
Math Tutor Suggests: Find the LCM of Other Number Pairs
Want more practice? As a math tutor, I encourage you to try some of these other LCM problems:
What is the LCM of 94 and 31?
What is the LCM of 129 and 43?
What is the LCM of 76 and 42?
What is the LCM of 78 and 91?
What is the LCM of 80 and 134?
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12542 | https://brilliant.org/wiki/quadratic-equations/ | Quadratic Equations
Ashish Menon,
Sandeep Bhardwaj,
Arron Kau,
and
Rishik Jain
Sravanth C.
Akshay Yadav
Hobart Pao
Yash Dev Lamba
Mehul Arora
Omkar Kulkarni
Skanda Prasad
A Former Brilliant Member
Jimin Khim
Calvin Lin
contributed
Contents
Solving by Factoring
Finding Quadratic Equation from Roots
Solving by Completing the Square
Solving by Quadratic Formula
Parabolas
Nature of Roots of Quadratic Equation
Word Problems - Basic
Biquadratic Equations
Quadratic Equations - Problem Solving
See Also
Solving by Factoring
Main Article: Factoring Polynomials
We can solve quadratics using factoring and the zero product property. In general, we can rewrite a quadratic as the product of two linear factors such that ax2+bx+c=a(x+p)(x+q). By the zero product property,
if ax2+bx+c=a(x+p)(x+q)=0, then either x=−p or x=−q.
Now, to factorise a quadratic equation, follow these steps.
1) We have to break b (the coefficient of x) into two terms in such a way that their sum is b and their product is ac:
ax2+bx+c=0⟹ax2+(b1+b2)x+c=0 such that b1+b2=b and b1×b2=ac.
2) Next we need to group ax2+b1x and b2x+c and factorize them in a way that they both have one factor common.
Now we will have the equation transformed into factors. From here on, the solution is easy. We use the zero product property and equate each factor to 0, i.e. (x−α)=0⟹x=α and (x−β)=0⟹x=β.
Solve x2+5x+6=0 for x by the method of factoring.
Following the steps mentioned above, we first break the coefficient of x in two terms such that their sum equals 5 and their product equals 1×6=6:
x2+(2+3)x+6=0,
where we can observe that 2+3=5 and 2×3=6:
x2+2x+3x+6x(x+2)+3(x+2)=0=0.
Taking out (x+2) as a common factor, we have
(x+3)(x+2)x+3x+2=0=0⟹x=−3=0⟹x=−2.
Therefore the two roots of the given equation are −3 and −2. □
Method of Solving a Quadratic Equation by Factorizing:
Step 1. Make the given equation free from fractions and radicals and put it into the standard form ax2+bx+c=0.
Step 2. Factorize ax2+bx+c into two linear factors.
Step 3. Put each linear factor equal to 0 (to apply the zero product rule).
Step 4. Solve these linear equations and get two roots of the given quadratic equation.
Solve x2−x−6=0 by the method of factoring.
We have x2−x−6=(x−3)(x+2), which gives x=3 or x=−2. □
Note that the factors of x2−x−6 are 1,x2−x−6,x−3, and x+2.
Solve the equation x2+3x+2=0 for x.
We have
x2+3x+2x2+2x+x+2x(x+2)+1(x+2)(x+2)(x+1)=0=0=0=0.
So,
(x+2)=0 or (x+1)=0x=−2 or x=−1. □
Note: We cannot always factor into linear factors using only real numbers. For some quadratics (e.g., x2+1), the linear factors require complex numbers:
x2+1=(x+i)(x−i).
Try the following problems:
x=1,−1
x=2,−2
x=−2
x=0
What are the solutions to the equation
x2=4?
The correct answer is: x=2,−2
Find the positive root of the equation x2+x−20=0.
The correct answer is: 4
If the value of a2+6a−6 is a, then find the minimum value of a.
The correct answer is: -6
Finding Quadratic Equation from Roots
When two places of the variable are given, we have to write them of the form (variable - value = 0).
To find the equation from the roots:
Step 1. If the variable x is given, and two values x=a and x=b are given, then we have to simplify them to x−a=0 and x−b=0.
Step 2. Multiplying the equations and simplifying them, we arrive at this:
(x−a)(x−b)x2−(a+b)x+ab=0=0.
Find the quadratic equation whose roots are 2 and −3
Considering the equation in variable x, we have the following:
x=2x=−3⟹(x−2)=0⟹(x+3)=0.
Multiplying both the equations, we have
(x−2)(x+3)x(x+3)−2(x+3)x2+3x−2x−6x2+x−6=0=0=0=0. □
Find the quadratic equation whose roots are 5 and 6
Considering the equation in variable x, we have the following:
xx=5⟹x−5=0=6⟹x−6=0.
Multiplying both the equations gives
[\begin{align}
(x-5)(x-6) & =0\
x(x-6)-5(x-6) & =0\
x^2-6x-5x+30 & =0\
x^2-11x+30 & =0.\ _\square
\end{align}]
Solving by Completing the Square
Main Article: Completing The Square
For a quadratic polynomial f(x)=ax2+bx+c, completing the square means finding an expression of the form
f(x)=a(x−b)2+c.
Complete the square for the quadratic x2+8x+10.
Since our middle term is 8x, we know that we will want a perfect square with the form (x+4)2, which expands to x2+8x+16.
Thus, we can do the following:
x2+8x+10=x2+8x+16−16+10=(x2+8x+16)−6=(x+4)2−6. □
Solve this equation 2x2+3x+1=0 by method of completing square.
First take 2 as common: 2(x2+23x)+1=0. Since our middle term is 23x, we know that we will want a perfect square with the form
(x+43)2=x2+23x+169.
So rewrite the whole equation as
2(x+23x+169−169)+12(x+23x+(43)2−169)+12(x+43)2−81(x+43)2=0=0=0=161.
Thus we have
x+43⇒x=±41=−21 or x=−1. □
Find the minimum value of 4x2+8x+16 for real x.
The correct answer is: 12
Solving by Quadratic Formula
Main Article: Quadratic Formula
The quadratic formula states that for the equation ax2+bx+c=0, the values of x are given by the following:
x=2a−b±b2−4ac.
To see how this formula is derived via completing the square, see Quadratic Formula.
Solve 5x2−2x−3=0 for x.
Here, a=5,b=−2,c=−3. Using the quadratic formula, we get
[\begin{align}
x &= \dfrac{-b \pm \sqrt{b^2 -4ac}}{2a}\
& = \dfrac {-(-2) \pm \sqrt{(-2)^2 - 4×5×-3}}{2×5}\
& = \dfrac {2 \pm \sqrt{4 +60}}{10} = \dfrac {2 \pm \sqrt{64}}{10}\
& = \dfrac {2 \pm 8}{10}\
\Rightarrow x & = -0.6 \, \text{ or }\, x=1.\ _\square
\end{align}]
Solve x2−4x+1 for x.
Here, a=1,b=−4,c=1. Using the quadratic formula, we get
x⇒x=2a−b±b2−4ac=2×1−(−4)±(−4)2−4×1×1=24±16−4=24±12=24±2×3=2+3 or x=2−3. □
Solve x2−20x−69=0 for x.
Substituting the values a=1,b=−20,c=−69 in the quadratic formula, we get
x⇒x=2×1−(−20)±(−20)2−4×1×−69=220±400+276=220±676=220±26=23 or x=−3. □
Try the following problems:
24841+69, 2−(4841−69)
24681−69, 2−4681+69
23,−3
31−10, −(31+10)
x=2a−b±b2−4ac
Using the quadratic formula above, find the roots of the equation
x2−20x−69=0.
The correct answer is: 23,−3
x=53±42
x=±3.8
x=±7
Solve the quadratic equation
(5x−3)2=32.
Check out the set: 2016 Problems.
The correct answer is: x=53±42
Parabolas
Main Article: Parabolas
Here is an example illustrating the above.
Find the equation of a parabola with vertex at (0,0) if its axis of symmetry is the y-axis and its graph contains the point (2−1,2).
We write the vertex form of the parabola as y=A(x2). Plug in the coordinates of the given point to find A
2A⇒y=A×(2−1)2=8=8x2. □
Try the following problems:
0.84
1.05
1.00
0.95
If the McDonald's logo were stored as a set of pixels, enlargement would quickly result in distorted or pixelated images, which are an eyesore. As such, companies often make vector images of their logos, in which the information is stored as mathematical formulae. Such vector images are easily scaled while maintaining sharp, crisp images.
As a first approximation, the logo is deconstructed and approximated as 2 parabolic curves of the form y=−A(x−5)2 and y=−A(x+5)2. The McDonald's logo has a height to length ratio of 1.05. What is A?
The correct answer is: 0.84
The 2 parabolas intersect when x=0, which determines the middle point. As such, the left most point is x=−10 and the rightmost point is x=10.
Consider the point on the second parabola with x=−10. The y -value, which is A×52, must be equal to the height, which is 5×4×1.05. This gives us A=0.84
0
41
21
1
As x ranges over all real values, what is the minimum of
x2+(x+1)2?
The correct answer is: 21
Nature of Roots of Quadratic Equation
The nature of roots of a quadratic equation can be determined by observing the quadratic formula closely. It basically consists of a discriminant which actually makes the difference in formula and leads us two roots.
We know the quadratic formula is
x=2a−b±b2−4ac
for any quadratic equation written in standard form of ax2+bx+c=0. The discriminant D for the quadratic equation is
D=b2−4ac,
where
⎩⎨⎧b2−4ac>0:b2−4ac=0:b2−4ac<0:two distinct real rootsequal and real rootsimaginary roots.
Determine the nature of roots of the following two quadratic equations:
2x2+x−1x2−4x+4=0=0.
For the quadratic equation 2x2+x−1=0:
Since a=2,b=1,c=−1,
b2−4ac=12−4×2×−1=9>0,
which implies that the roots are real and distinct.
For the quadratic equation x2−4x+4=0:
Since a=1,b=−4,c=4,
b2−4ac=(−4)2−4×1×4=0,
which implies that the roots are real and repeated. □
Find the value of k for which the following quadratic polynomial has repeated roots:
x2+4x+k.
We know that if D=0, then the quadratic polynomial has repeated roots. So,
b2−4ac(4)2−4(1)(k)k=0=0=4. □
Show that the equation x2+dx−1=0 has real and distinct roots for all real values of d.
Here, a=1,b=d, and c=−1. So the discriminant would be
D=d2−4×1×−1=d2+4.
Since d2 is a perfect square, it is always greater than or equal to 0. So,
D=d2+4≥4.
Thus, the discriminant is always greater than 0, implying that this equation has distinct real roots for any real value of d. □
Word Problems - Basic
Two years ago, a man's age was three times the square of his son's age. In three years, his age will be four times his son's age. Find their present ages.
Let the present age of the son be x. Then the son's age two years ago was x−2, and his father's age two years ago was 3×(x−2)2. This implies the present age of the father is [3×(x−2)2]+2, and hence in three years his age will be [3×(x−2)2]+2+3=[3×(x−2)2]+5. The son's age in 3 years will be x+3.
According to given conditions, the following holds:
3(x−2)2+5⇒3x2−16x+5⇒(3x−1)(x−5)⇒x=4(x+3)=0=0=31,5.
If x = 31, then the son's age 2 years ago would become negative, which is impossible.
So, the son's present age is x=5, which implies that the present age of the man is
3×(x−2)2+2=3×(5−2)2+2=3×32+2=3×9+2=27+2=29. □
Find two numbers whose sum is 40, and product 375.
Let one number be x. Then, according to the first condition, the second number is 40−x. Substituting, the value in the second condition, we get
x(40−x)40x−x2x2−40x+375x2−25x−15x+375x(x−25)−15(x−25)(x−15)(x−25)⇒x=375=375=0=0=0=0=15,x=25.
Therefore, the smaller number is 15 and the larger one is 25. □
The product of two consecutive positive integers is 90. What is their sum?
Since the integers are consecutive, we can rewrite the expression above as n(n+1)=90. This gives us the following quadratic equation: n2+n−90=0. Factoring, we can see that
n2+n−90=(n−9)(n+10)=0,
which implies n=9. Then the two numbers are 9 and 10, and their sum is 19. □
Try the following problems:
600
655
None of the above
625
A teacher, on attempting to arrange the students in the form of a solid square for a mass drill, found that 24 students were left out. When he increased the size of the square by one, he found that he was short of 25 students. Find the number of students.
The correct answer is: 600
The difference of the cubes of two consecutive odd positive integers is 400 more than the sum of their squares. Find the sum of the two integers.
Clarification: The odd positive integers are 1,3,5,7,9,…. Two consecutive odd positive integers refer to two consecutive numbers in this sequence. It does not refer to two consecutive integers (of which one will not be odd).
Biquadratic Equations
Sometimes, the quadratic formula could be useful in solving equations of larger degree.
Solve x4−3x2+1=0.
That equation isn't something you'd want to factor. So, you could make the substitution u=x2. Then the equation would read
u2−3u+1=0.
We can solve that with the quadratic formula:
u=23±5.
But we're not done yet. We want x, not u. Since u=x2=23±5, solving that equation for x gives
x=±23±5. □
Quadratic Equations - Problem Solving
This section contains miscellaneous problems on quadratic equations for you to try, which will eventually enhance your problem solving skills.
See Also
Factoring Polynomials
Completing The Square
Quadratic Formula
Cite as:
Quadratic Equations.
Brilliant.org.
Retrieved
11:33, September 5, 2025,
from |
12543 | https://www.metrohm.com/content/dam/metrohm/shared/documents/application-bulletins/AB-233_4.pdf | Page 1 of 9 Application Bulletin 233/4 e Potentiometric determination of anionic and cationic surfactants with surfactant electrodes Branch General analytical chemistry, private laboratories; organic chemistry, chemistry; pharmaceutical industry; metals, electroplating; detergents, surfactants cosmetics Keywords Anionic and cationic surfactants; titration; 6.0507.120; 6.0507.150; branch 1; branch 3; branch 4; branch 10; branch 12 Summary Anionic surfactants can be titrated with cationic surfactants and vice versa. This Bulletin describes a wide range of substances that can be determined and lists the relevant working conditions and parameters. In contrast to the classical «two-phase titration» according to Epton, the titration with the anionic and cationic surfactants electrodes can be performed without chloroform. Further, in some cases the titration equivalence point with the Epton method is difficult to detect and the titration cannot be automated. The surfactant ISE provides help here in many cases and also benefits the environment. It has been specially developed for surfactant determinations using potentiometric indication. Instruments Titrator with DET mode 20 mL buret Rod Stirrer Electrode Ionic Surfactant electrode 6.0507.120 Cationic Surfactant electrode 6.0507.150 Ag/AgCl Reference Electrode 6.0726.100 Reagents Buffers and solvents Buffer solution pH = 2.0 citrate/HCl Buffer solution pH = 3.0 citrate/HCl Buffer solution pH = 6.0 citrate/NaOH Buffer solution pH = 7.0 phosphate, e.g. Metrohm no. 6.2305.020 Buffer solution pH = 10.0 boric acid /KCl/NaOH Hydrochloric acid c(HCl) = 2 mol/L Hydrochloric acid c(HCl) = 0.1 mol/L Sodium hydroxide c(NaOH) = 2 mol/L Methanol puriss p.a. Formaldehyde 35% Titrants for anionic surfactants TEGO®trant A 100 1,3-didecyl-2-methylimidazolium chloride (DDMICl) Metrohm no.: 6.2317.000 (6 g) or 6.2317.010 (60 g) HDPCl Hexadecylpyridinium chloride (HDPCI · H2O), also called cetylpyridinium chloride (CPCl) Fluka no.: 52349 Hyamine® 1622 Benzethonium chloride Merck no.: 112058 Titrants for cationic surfactants Sodium dodecylsulfate SDS Sodium lauryl sulfate LAS Merck no.: 112533 or Sigma no.: 71725; stabilized against bacterial growth by 0.5% formaldehyde. Dioctylsodium sulfosuccinate DOSS Bis(2-ethylhexyl)-sodium sulfo-succinate Fluka no.: 86139 Note: May saponify at higher pH values Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 2 of 9 Preparation of Titrants General The right selection of the titrant is very important. The lower the solubility of the formed compounds (the greater their oleophilic properties), the larger and steeper the potential jump of the titration curve. Advantage should be taken of this effect when formulations are titrated. (Additives can lead to considerable flattening of the potential jumps.) Work is preferably performed with titrants of concentration 0.005 mol/L; only in exceptional cases a concentration of 0.02 mol/L is used. The weight of reagents required for one liter is given by: Weight [in g] = Mt × ct ×100 pt Mt: Molar mass of titrant ct: titrant concentration, here 0.005 or 0.02 mol/L 100: conversion factor [L] pt: Purity of the titrant in % Weigh in the required amount of titrant (plus slight excess) exactly and dissolve in dist. water, warming gently if necessary. By their nature, the substances do not contain 100% active substance. The major by-product is usually water. The water mass fraction can amount up to 8% and is very difficult to remove. It is essential to take these circumstances into account when weighing in the titrant. Make up to 1 liter with dist. water at 20 °C. The titer is determined against an anionic or cationic surfactant. As long as the solution in the reagent bottle and the buret has not stabilized, the titer is also not stable (surfactants tend to adhere to surfaces; this is characteristic particularly to cationic surfactants). Consequently, use always the same reagent bottles and other equipment (e.g. buret) and allow the solution to stand for one day before determining the titer. Preparation of c(TEGO®trant A100) = 0.005 mol/L Approx. 2.12 g of TEGO®trant A100 is weighed into a glass beaker with an accuracy of 0.1 mg and dissolved in approx. 150 mL water. This solution is transferred quantitatively with dist. water to a 1 L volumetric flask and fille up to the mark. Detailed information can be found on the leaflet which is delivered with the TEGO®trant. Preparation of the comparison standard solutions from sodium dodecyl sulfate (SDS) The raw substances contain some impurities e.g water. Therefore it is recommended to take the purity of the raw material into the calculation of the weigh in. Approx. 1.44 g of sodium dodecyl sulfate is weighed into a glass beaker with an accuracy of 0.1 mg and dissolved in approx. 200 mL water. This solution is transferred quantitatively with water to a 1 L volumetric flask, the flask is filled to the mark and its contents are carefully mixed. The exact sample weight must be noted as it is needed for the subsequent titer calculation. Titer determination of the TEGO®trant A100 10.0 mL of the corresponding sodium dodecyl sulfate standard solution is pipetted into a glass beaker. Followed by adding of 5 mL methanol, 75 mL water and 10 mL buffer solution pH = 3.0. The sample solution is efficiently stirred and then titrated using the corresponding TEGO®trant A100 solution as titrant with the following instrument settings: Pause 30 s Signal drift 50 mV/min Measuring point density 4 Min. increment 10.0 µL Stop volume 20 mL EP recognition all The results may be used only if just one equivalence point is recognized. If this is not the case, additional titrations must be performed. Calculation of the titer A threefold determination is always performed. The resulting mean value is calculated to four decimal places. f = ms × VS × CS VEP1 × MS × 100 × cTEGOtrant f: Titer of the titrant VEP1: Titrant consumption in mL mS: Sample weight of SDS standard in g VS: Added volume of SDS solution in mL, here 10.0 CS: Active substance content of the SDS used in %, here 99.2 MS: Molecular weight of reference substance; here 288.4 g/mol 100: Conversion factor due to % cTEGOtrant: Theoretical concentration of the titrant in mol/L; here 0.005 Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 3 of 9 Preparation of c(sodium dodecyl sulfate) = 0.005 mol/L A titer determination in the usual manner cannot be performed for anionic titrants as there are no suitable primary standards. Cationic surfactants are normally quaternary ammonium compounds that usually cannot be prepared with the purity required for a primary standard. The degree of quaternization of these compounds would have to be 100%, but this is never the case. In addition, most of these compounds are highly hygroscopic. As a result, owing to water uptake, the active substance content changes each time the container is opened. As a titer determination in the normal sense is not possible, the standard solutions are prepared by very exact weighing in of sodium dodecyl sulfate. 1.44 g of SDS is weighed exactly into a glass beaker and dissolved in approx. 250 mL dist. water. This solution is rinsed quantitatively into a 1 L volumetric flask with dist. water, 10 mL w(HCHO) = 35% is added and the flask is filled to the mark with dist. water. The addition of formaldehyde prevents bacterial decomposition of the titrant without having an adverse effect on the surfactant titration. The disinfecting action of the quantity specified is sufficient to keep the titer stable for at least three months. To guarantee thorough mixing, a magnetic stirring bar is added to the flask and the solution is stirred on a magnetic stirrer ensuring that foam formation is kept to a minimum. The titrant can then be transferred to the buret. Preparation of c(DOSS) = 0.02 mol/L or 0.005 mol/L As a titer determination in the normal sense is not possible, the standard solutions are prepared by very exact weighing in of dioctylsodium sulfosuccinate. 8.89 g for 0.02 mol/L or 2.22 g for 0.005 mol/L DOSS is weighed exactly into a glass beaker and dissolved in approx. 250 mL dist. water. This solution is rinsed quantitatively into a 1 L volumetric flask with dist. water, 10 mL w(HCHO) = 35% is added and the flask is filled to the mark with dist. water. pH ranges for some detergents Anionic surfactants Fig. 1 Titration recommendations for anionic surfactants In the case of samples that contain both sulfosuccinates and betaines, the sulfosuccinates are titrated at pH = 3.0. For the determination of sulfosuccinates, the following pH values are adjusted for titration o sulfonate group at pH = 2.0 o sulfonate and carboxylate group at pH = 10.0 Cationic surfactants Fig. 2 Titration recommendations for cationic surfactants For the determination of the degree of quaternary amines, an additional titration is performed at pH = 3.0 to obtain the sum of the quaternary ammonium compounds and the tertiary starting amine. The ester quats contained in softeners are usually titrated at pH = 2.0. However, some ester quats exhibit their greatest stability at pH = 5 or pH = 7 and should thus be determined at these pH values. Here, it should be noted that the pH has to be adjusted immediately following the sample weighing. Slightly alkaline conditions can very quickly lead to ester cleavage Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 4 of 9 resulting in the ester losing its surfactant properties. This would lead to erroneous results. Betaines and amphoteric surfactants cannot be titrated. However, when present in the protonated form (at pH = 0 – 1), they can interfere with the determination of other surfactants. Theory behind the electrode The surfactant ISE electrode is a PVC liquid membrane electrode with a membrane composition (ionophore/plasticizer) that has been specially optimized for the determination of ionic surfactants. The electrode potential is due to a specific interaction between the ion carrier incorporated in the PVC membrane and the analyte ions (surfactants) in the analysis solution. This interaction leads in an equilibrium reaction to a potential crossing of the analyte ions from the analysis solution into the membrane and – as a result of this – to the formation of an electrical potential difference at the phase boundary analysis solution/membrane, which can be measured at zero current (potentiometrically) against a reference electrode. The extent of ion transfer from the analysis solution into the membrane depends on the concentration. The relation between the analyte ion concentration and the electrical potential is described by the Nernst equation: E = E0 + s × ln ( cox cred ) In the equation, «s» represents the electrode slope. In the ideal case it is ca. 59 mV per concentration decade for monovalent anions and cations at 25 °C. In practice, lower slopes are frequently observed. Owing to a variety of circumstances (membrane composition, special properties of the surfactants such as boundary activity, substantivity [= tendency to absorb on surfaces], formation of micelles), Nernstian behavior cannot always be assumed for the surfactant electrodes. In practice, this means that the electrode is not suitable for direct potentiometric concentration determinations and the titration should always be evaluated using the inflection point of the S-shaped titration curve. End point titrations are usually not to be recommended. Preparation, maintenance and storage of the surfactant electrode The electrode is stored dry. The electrode is best conditioned by two to three titrations whose results should be ignored. Adherent deposits are removed with a soft paper towel, moistened in methanol. In sample changer operation, the electrodes are dipped briefly in methanol, while stirring. The electrode (PVC membrane) is not resistant towards almost any organic solvents. Chloroform, hydrocarbons, acetone, MIBK, tetrahydrofuran, etc. destroys the electrode. High proportions of methanol (30 – 40%) or ethanol (20%) in the solvent shorten the lifetime of the electrode. Several thousand titrations can be performed with the electrode under normal conditions. Evidence of a decrease in the responding behavior of the electrode is shown in flatter titration curves and a shortened potential range. For a short time, such an electrode can be regenerated by submerging it for 30 min. in a sodium dodecyl sulfate solution (0.005 mol/L). If this does not help, the electrode must be replaced. Analysis The dynamic equivalence titration (DET) is the most suitable as it allows the fastest titrations and offers the best reproducibility. An amount of sample that corresponds to a titrant consumption of at least 10 mL is weighed into a beaker and approx. 50 mL dist. water are added. Following addition of 10 mL buffer solution and 5 mL methanol, the titration is started (examples in the Practical examples). In the case of concentrates and raw materials, for reasons of accuracy a dilution should first be made. In order to prevent formation of micelles, about 5 – 20 % vol. methanol are added. An aliquot of the initial dilution is then used for the titration (take into account the methanol fraction of the initial dilution). Anionic surfactants Anionic surfactants are normally titrated with a cationic surfactant at pH = 3.0. For special cases, see Fig. 1. Soaps (sodium or potassium salts of higher fatty acids) must be titrated with TEGO®trant A 100 at pH values >10. Other cationic titrants produce poor titration curves that are often impossible to evaluate. In mixtures, anionic surfactants and soaps are determined as a sum. With decreasing pH value, the fraction of the soaps determined by titration becomes increasingly smaller. Complete separation is achieved by acidifying the sample to pH = 2.0 (allow the sample to stand 13 – 30 min for the reaction to run to completion). In the titration with TEGO®trant A 100 only the anionic surfactants are then determined. The pH value for the sum titration depends on the sample used and must be Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 5 of 9 determined by preliminary titrations (pH = 10 – 13). Two potential jumps result with the second being used to determine the sum of the soaps and anionic surfactants content together. Cationic surfactants Cationic surfactants are normally titrated with an anionic surfactant at pH = 10.0. For special cases see Fig. 2. Samples that contain amine hydrochlorides are titrated at pH = 3.0. If the content without amine hydrochlorides is required, the titration is performed at pH = 10.0. Calculation For raw materials or known formulations: wSurfactant = VEP1 × MS × ct × f × 100 mS wsurfactant: Content of surfactant in % VEP1: mL titrant consumed to reach the first EP MS: Molar mass of Surfactant in g/mol ct: concentration of the titrant in mol/L f: Titer of the titrant 100: Conversion factor due to % mS: Sample weight in mg If the molar mass of the surfactant under investigation is unknown or if the total surfactant content needs to be determined (without using an average molar mass), the analysis result can also be specified in mmol surfactant / 100 g sample or as sulphur equivalent: mmol 100 g = VEP1 × 1000 × ct × f × 100 mS mmol/100g: Content in mmol surfactant per 100 g sample VEP1: mL titrant consumed to reach the first EP 1000: Conversion factor mol to mmol ct: concentration of the titrant in mol/L f: Titer of the titrant 100: Conversion factor due to 100 g mS: Sample weight in mg wsurfactant-S = VEP1 × 100 × MSulphur × ct × f mS wSurfactant-S: Content of surfactant as sulphur equivalent in % VEP1: mL titrant consumed to reach the first EP MSulphur: Molecular weight of sulphur, 32.064 g/mol 100: Conversion factor due to % ct: concentration of the titrant in mol/L f: Titer of the titrant mS: Sample weight in mg Calculation for cationic surfactants in formulations (3.2): meq g ester quats = VEP1 × ct mS meq/g ester quats : Molar equivalence ester quats per 1 g of sample VEP1: mL titrant consumed to reach the first EP mS: sample weight in g ct: concentration of the titrant, here 0.02 mol/L or 0.005 mol/L Calculation for cetylpyridinium chloride (3.2.6): mg L CPCI = VEP1 × CF1 × 1000 VS VEP1: mL c(SDS) = 0.005 mol/L consumed to reach the first equivalence point VS: sample volume in mL CF1: 1.79005 (conversion factor: 1 mL c(SDS) = 0.005 mol/L ≙ 1. 79005 mg CPCl) 1000: Conversion factor due to g to mg Equivalence calculation 1 mL anionic surfactant 0.005 mol/L = 1.9985 mg Tego®trant = 1.7901 mg HDPCl = 2.2405 mg Hyamine® 1622 1 mL cationic surfactant 0.005 mol/L = 1.4419 mg sodium dodecylsulfate = 2.2229 mg DOSS Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 6 of 9 Practical examples 1. Titration parameters Table 1: different settings for different sample types Curve shape Steep titration curve Intermediate titration curve Flat titration curve Mode DET U DET U DET U Pause 30 s 30 s 30 s Signal drift 30 mV/min 50 mV/min 50 mV/min Max. waiting time 38 s 26 s 26 s MPD 5 3 2 Stop volume 20 mL 20 mL 20 mL EP criterion 5 5 5 EP recognition greatest greatest greatest ) The waiting time of 30 s is necessary to allow the electrode to adapt to the titration solution. 2. Analysis of raw materials 2.1 Determination of anionic surfactants 2.1.1 Fatty alcohol ether sulfates 5 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL; Titration parameters «intermediate titration curve». 2.1.2 Fatty alcohol sulfates 5 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL (if sample is based on coconut fat: 12 mL); Titration parameters «intermediate titration curve». 2.1.3 Sulfosuccinate monoesters 5 mL methanol, 10 mL buffer solution pH = 1.0 or pH = 2.0 if only the sulfonate group needs to be determined. 10 mL buffer solution pH = 10 if the sulfonate and carboxylate groups need to be determined, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL; Titration parameters «intermediate» or «flat titration curve» (depending on the number of Polyoxyethylene units (POE)); take into consideration the hydrolysis stability of the ester group! 2.1.4 Sulfosuccinate diesters 5 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL; parameters «steep titration curve»; take into account the hydrolysis stability of the ester group! 2.1.5 α-olefin sulfonates 5 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 8 mL; parameters «intermediate titration curve»; values may be too high in comparison with the two-phase titration. 2.1.6 Secondary alkanesulfonates 5 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL; parameters «intermediate titration curve»; values may be too high in comparison with the two-phase titration. 2.1.7 Linear alkylbenzene sulfonates 5 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL; parameters «steep titration curve». 2.1.8 Isethionates 10 mL methanol, 10 mL buffer solution pH = 3.0, approx. 40 mL of dist. Water; minimum consumption of c(TEGO®trant) = 0.005 mol/L: 10 mL; parameters «intermediate titration curve». Dissolve coconut fat isethionates in 5 mL methanol and 5 mL dist. water with gentle warming (allow to stand 3 – 5 min); then add 90 mL dist. water and 2 mL c(HCl) = 0.1 mol/L and titrate immediately. ) With the potentiometric titration, it is easily recognized that titration is performed according to decreasing oleophilic character. In particular, the differentiated titration curve indicates different inflection points with several products (e.g. C-12 – C-10 – C-8). This could be one of the reasons why somewhat higher values (up to 3%) are found in comparison with the two-phase titration. 2.2 Determination of cationic surfactants 2.2.1 Benzalkonium halides 10mL methanol, 10 mL buffer solution pH = 3.0 or pH = 10.0, approx. 40 mL of dist. Water; minimum consumption of c(SDS) = 0.005 mol/L: 6 mL, with bis(2-ethylhexyl)-sodium sulfosuccinate c(DOSS) = 0.005 mol/L: 4 mL; parameters «intermediate titration curve»; 2.2.2 Quaternary ammonium compounds 10 mL methanol, 10 mL buffer solution pH = 10.0, approx. 40 mL of dist. Water; minimum consumption of c(SDS) = Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 7 of 9 0.005 mol/L: 10 mL; parameters «intermediate titration curve»; 3. Analysis of formulations 3.1. Determination of anionic surfactants in formulations 3.1.1 Rinse-off formulations without sulfosuccinates Weigh in 100 – 300 mg sample, add 10 mL buffer solution pH = 5.0, 40 mL dist. water and dissolve sample. Add 5 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters for «intermediate» or «flat titration curve>> depending on the formulation,; perform at least three determinations (turbidities caused by pearl lustre concentrates do not interfere). 3.1.2 Rinse-off formulations with sulfosuccinates Weigh in 100 – 300 mg sample, add 10 mL buffer solution pH = 3.0, 40 mL dist. water and dissolve sample. Add 5 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 10 mL; depending on the formulation, parameters for «intermediate» or «flat titration curve»; perform at least three determinations (turbidities caused by pearl lustre concentrates do not interfere). 3.1.3 Mouth wash solutions on a dodecyl sulfate basis To 5 – 10 g sample add 10 mL buffer solution pH = 3.0 and 40 mL dist. water, then add 5 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «intermediate titration curve». 3.1.4 Toothpastes on a dodecyl sulfate basis To 1 – 2 g sample add 10 mL buffer solution pH = 3.0 and 40 mL dist. water, then homogenize with Polytron high frequency mixer; rinse the Polytron with 10 mL methanol and titrate sample solution with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «intermediate titration curve». 3.1.5 Anionic surfactants (dioctyl sulfosuccinates) in glass/window cleaning agent To 6 – 7 g sample add 10 mL buffer solution pH = 3.0 and 40 mL dist. water, then add 5 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; parameters «intermediate titration curve». 3.1.6 Anionic surfactants in toilet cleaning agent To 2.5 – 3.5 g sample add 10 mL buffer solution pH = 3.0 and 40 mL dist. water, then add 10 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «steep titration curve». 3.1.7 Anionic surfactants in dishwashing concentrate To ca. 3 g sample add 10 mL buffer solution pH = 5.0 and 40 mL dist. water, then add 10 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «steep titration curve». 3.1.8 Anionic surfactants and soaps in all-purpose cleaning agents To ca. 3 g sample add 10 mL buffer solution pH = 5.0 (for the determination of the anionic surfactants) or 10 mL buffer solution pH = 10.0 (for the determination of the anionic surfactants and soaps) and 40 mL dist. water; then add 10 mL methanol and titrate with c(TEGO®trant) = 0.005 mol/L; minimum consumption of titrant: 8 mL; parameters «intermediate» to «flat titration curve». 3.1.9 Sum of the anionic surfactants in a shampoo and shower gel (non oil, fat free) Weigh ca. 200 mg sample exactly into a beaker and dissolve in 45 mL dist. water and 3 mL methanol; add 5 mL buffer solution pH = 3.0 and titrate with c(TEGO®trant) = 0.005 mol/L; parameters «intermediate» (shower gel) to «steep titration curve» (shampoo). 3.2 Determination of cationic surfactants in formulations 3.2.1 Hair conditioner To 0.5 – 2 g sample add 10 mL buffer solution pH = 2.0 to pH = 10.0 (test and match to the particular formulation) and 40 mL dist. water and homogenize with a Polytron; rinse the Polytron with 10 mL methanol and titrate sample solution with c(SDS) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «flat titration curve»; 3.2.2 Mouth wash solution on a benzalkonium basis To 100 – 300 mg sample add 10 mL buffer solution pH = 3.0 or pH = 10.0 (test and match to the particular formulation) and 40 mL dist. water, then add 10 mL methanol and titrate with c(DOSS) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «intermediate titration curve»; 3.2.3 Mouth/dental wash solutions on an amino fluoride basis To 5 – 10 g sample add 10 mL buffer solution pH = 3.0 and 30 mL dist. water, then add 10 mL methanol and titrate with c(DOSS) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «flat titration curve»; 3.2.4 Toothpastes on an amino fluoride basis To 1 – 2 g sample add 10 mL buffer solution pH = 3.0 and 40 mL dist. water and homogenize with a Polytron; rinse the Polytron with 10 mL methanol and titrate sample solution Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 8 of 9 with c(SDS) = 0.005 mol/L; minimum consumption of titrant: 10 mL; parameters «flat titration curve». 3.2.5 Cationic surfactants (ester quats) in a fabric softener Dissolve ca. 1 g sample in 90 mL dist. water and 5 mL methanol; add 5 mL buffer solution pH = 3.0 and 1 mL c(HCl) = 2 mol/L and titrate with c(DOSS) = 0.02 mol/L; parameters «flat titration curve». 3.2.6 Cetylpyridinium chloride (CPCl) in a mouth/dental wash solution Pipet 10.0 mL sample into a beaker, add 40 mL dist. water and 5 mL buffer solution pH = 3.0 and titrate with c(SDS) = 0.005 mol/L. Example determination Fig. 3 Titration curve (steep) for the determination of the anionic surfactants in a shampoo. (blue = titration curve, pink = ERC) Fig. 3 Titration curve (Intermediate) for the determination of the anionic surfactants in a shower gel. (blue = titration curve, pink = ERC) Comments If the surfactant electrode is left in the titrated sample solution for too long, it will either not respond at all or wrongly during the next titration. In such cases, rinse it with methanol and place it in c(SDS) = 0.005 mol/L for a few minutes. It is always advisable to immerse the electrode in the sample solution for 20 – 40 s before each titration to allow adaption to the sample matrix. You can extend the lifetime of the electrode by storing it dry. The titrant TEGO®trant A 100 provides much steeper titration curves and larger potential jumps than other titrants. These advantages are particularly apparent with surfactants and soaps that produce only very weak potential jumps when using Hyamine® 1622. With TEGO®trant A 100 lower detergent concentrations can thus be determined. If sufficient sample is available, the sample weight should be chosen to produce a titrant consumption of at least 10 mL. Only this guarantees determination of the total amount of surfactants. While lower sample weights give better titration curves, they sometimes lead to values that are too low. Addition of methanol is absolutely necessary, particularly in finished formulations (e.g. shampoos, shower gels, softeners). In some cases it may even be necessary to increase the methanol content drastically in order to obtain precise results. Possible micelle and Application Bulletin 233/4 e Titrimetric/potentiometric determination of anionic and cationic surfactants with the anionic and cationic surfactant electrode Page 9 of 9 foam formation can be prevented in this way (see also examples in the Practical determinations). The determination limit for ionic surfactants in waste waters lies at approx. 3 – 5 mg/L. For this purpose the titrant must be diluted to 0.002 mol/L. Measure 100 mL of the sample solution and adjust its optimum pH value with NaOH or HCl. Do not add methanol! These surfactant electrodes are not suitable for fatty or oily products (e.g. drilling and cutting oils, cooling lubricants, cleaning baths, special household cleaning agents and furniture polishes, shower gels and bath salts). Here a Surfactrode must be used. See Application Bulletin No. 269. The surfactant concentration is considerable higher in the foam phase than in the aqueous solution beneath it. Surfactant solution with a head of foam on top should only be used for analysis after the foam has collapsed. Refernces R. Schulz, R. Gerhards, Optimization of the potentiometric titration of ionic detergents, American Laboratory 26/11, (1994) 40-44 and International Laboratory 24/10, (1994) 10-14. Schulz, R. Gerhards, H.-D. Käseborn, Die potentiometrische Bestimmung von Anionentensiden in Rinse-off-Produkten, SÖFW-Journal 120/13, (1994) 776-783. R. Schulz, R. Gerhards, A new titrant for the potentiometric titration of anionic detergents, Tenside/Detergents, issue 1, 1995. S. Selig, The potentiometric titration of surfactants and soaps using ionselective electrodes, Fresenius J. Anal. Chem. 300, (1980) 183-188. G. C. Dilley, Determination of anionactive matter in detergents by potentiometric titration, Analyst 105, (1980) 713-719. K. Kosswig, H. Stache, Die Tenside, Carl Hanser Verlag, Müchen/Wien, 1993, ISBN 3-446-16201-1. Stache, K. Kosswig, Tensid-Taschenbuch, 3. Auflage, Carl Hanser Verlag, München/Wien, 1990, ISBN 3-446-15704-2. M. Schmitt, Analysis of Surfactants, Surfactant Science Series Vol. 40, Marcel Dekker Inc., New York, 1992, ISBN 0-8247-8580-0. D. C. Cullum, Introduction to Surfactant Analysis, Blackie Academic & Professional, London, 1994, ISBN 0-7514-0025-4. ASTM D 4251-89, Standard Test Method for Active Matter in Anionic Surfactants by Potentiometric Titration. ASTM D 5070-90, Standard Test Method for Synthetic Quaternary Ammonium Salt in Fabric Softeners by Potentiometric Titration. R. Schulz, Th. Goldschmidt AG, Zentralbereich Forschung/Analytik, Goldschmidtstrasse 100, D-45127 Essen, Fax +49 201 173 19 97, Numerous personal communications regarding his work and lecture material. R. Schulz, P. Bruttel Bestimmung ionischer Tenside in Mundpflegeprodukten SÖFW-Journal 124/3, (1998) 138-146. R. Schulz, P. Bruttel Analytik ionischer Tenside in Haarpflegeprodukten SÖFW-Journal 125/2, (1999). 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Directly Proportional and Inversely Proportional
🎬 Math Angel Video: Direct Proportion vs Inverse Proportion
What Does “Directly Proportional” Mean? (0:01)
🔮 Directly Proportionality Definition:
When two quantities are directly proportional, as one increases or decreases, the other increases or decreases by the same factor.
🔮 Key Features of Direct Proportionality
If you double one quantity, the other will also double.
If you triple one, the other will triple too.
If you halve one, the other will also halve.
🌟 Example of Direct Proportionality
Imagine you are buying watermelons at a shop. Each watermelon costs £4.
The total cost is directly proportional to the number of watermelons you buy, because each one costs the same amount.
| Number of Watermelons | Total Cost |
--- |
| 1 | £4 = 1 x £4 |
| 3 | £12 = 3 x £4 |
| 5 | £20 = 5 x £4 |
| 8 | £32 = 8 x £4 |
| 10 | £40 = 10 x £4 |
You can calculate the total cost using this formula:
$$\text{Total Cost} = \text{Number of Watermelons} \times £4$$
🔎 How to Spot Direct Proportionality
If you divide one quantity by the other, you always get the same answer.
For example, if you divide the total cost by the number of watermelons, you always get £4.
This means the cost is directly proportional to the number of watermelons.
What Is Inversely Proportional? (1:15)
🔮 Inverse Proportionality Definition
When two quantities are inversely proportional, it means that as one increases, the other decreases in such a way that their product always stays the same.
In simple words: If you make one quantity bigger, the other gets smaller by just the right amount to keep the answer the same when you multiply them.
🔮 Key Features of Inverse Proportionality
If you double one quantity, the other is halved.
If you triple one, the other becomes one third as much.
The product (when you multiply the two quantities together) is always the same.
🌟 Example of Inverse Proportionality
Imagine you are working on a job.
If 5 people work together, it takes 6 hours to finish.
If only 3 people work, it takes 10 hours to finish.
If 30 people work, it only takes 1 hour to finish.
| Number of Workers | Hours Needed | Product (Workers × Hours) |
---
| 5 | 6 | 30 |
| 3 | 10 | 30 |
| 30 | 1 | 30 |
| 15 | 2 | 30 |
Notice that if you multiply the number of workers by the number of hours, you always get the same result: 30.
Therefore, the number of workers and the number of hours needed to finish this task is inversely proportional.
You can calculate the number of workers or hours needed using this formula:
$$ \text{Number of Workers} \times \text{Hours Needed} = \text{Constant}$$
Exam Tip: If the product of the two quantities always stays the same, they are inversely proportional!
📂 Flashcards: Direct Proportional and Inverse Proportional Concepts and Examples
🍪 Quiz: Practice Solving Directly Proportional and Inversely Proportional Questions
0%
🎩 Stuck on Proportionality Problems? Ask Our AI Solver
Need math help? Chat with our AI Math Solver at the bottom right — available 24/7 for instant answers.
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12545 | https://www.ncbi.nlm.nih.gov/books/NBK557784/ | Genetics, Chromosomes - StatPearls - NCBI Bookshelf
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StatPearls [Internet]. Treasure Island (FL): StatPearls Publishing; 2025 Jan-.
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Genetics, Chromosomes
Isha Pathak; Bruno Bordoni.
Author Information and Affiliations
Authors
Isha Pathak 1; Bruno Bordoni 2.
Affiliations
1 Saint Louis University
2 Foundation Don Carlo Gnocchi IRCCS
Last Update: April 3, 2023.
Go to:
Introduction
A chromosome is a DNA molecule that contains the genetic information for an organism. The chromosomal structure is composed of the organism's DNA and special proteins to form the dense, coiled architecture. The chromosome's tertiary structure is a crucial component in transcription regulation and cellular replication, and division.
Go to:
Development
W. Waldeyer coined the term "chromosome" in 1888.Sexual chromosomes are essential in development. The sexual organs that will develop will depend on the presence or absence of the Y chromosome in the cells of the embryo. With a Y chromosome, the embryo will become a boy, while with two Xs, a girl will grow.
We can find many different chromosomes. Chromosome 1 is the largest of the human chromosomes, made up of approximately 249 million base pairs of the nucleotide, and accounts for approximately 8% of the entire DNA within a human cell.
By convention, chromosomes are numbered based on the quantity of nucleotides present (size):
Chromosome 2 with about 243 million nucleotides
Chromosome 3 is the third largest and has nearly 200 million nucleotides.
Chromosome 4 has approximately 192 million nucleotides
Chromosome 5 with 181 million nucleotides
Chromosome 6 with about 170 million nucleotides
Chromosome 7 with about 158 million nucleotides
Chromosome 8 has over 146 million nucleotides
Chromosome 9 has over 140 million nucleotides
Chromosome 10 has about 135 million nucleotides
Chromosome 11 has just under 135 million nucleotides
Chromosome 12 has approximately 132 million nucleotides
Chromosome 13 has about 114 million nucleotides
Chromosome 14 has approximately 106 million nucleotides
Chromosome 15 has around 100 million nucleotides
Chromosome 16 has approximately 89 million nucleotides
Chromosome 17 has approximately 79 million nucleotides
Chromosome 18 has about 76 million nucleotides
Chromosome 19 has nearly 64 million nucleotides
Chromosome 20 has approximately 62 million nucleotides
Chromosome 21 has approximately 47 million nucleotides
Chromosome 22 has approximately 50 million nucleotides
Syndromes associated with changes in the structure or number of chromosomes in humans:
Trisomy 2
Trisomy 8
Trisomy 9
Trisomy 13
Trisomy 16
Trisomy 18
Trisomy 21
Go to:
Molecular Level
DNA is the biological molecule used by cells to store the cell's genetic information. The DNA molecule is made of nitrogenous bases, cytosine, and thymine, which are pyrimidines, and adenine, and guanine, which are purines. These strands of DNA are paired and form a double helix structure, in which the strands arrange in an antiparallel fashion. The antiparallel orientation of the strands means that the beginning 5' end of one strand's orientation is opposite the 3' end of the second strand, which is necessary for the eukaryotic DNA replication mechanism.
These DNA strands then wrap around proteins called histones. The eight histone proteins are two of each of the following: H2A, H2B, H3, and H4. This structure of the DNA wrapped around the eight histone proteins is called a nucleosome. These nucleosome structures are related to each other via another histone protein, H1, which serves the function of further compacting the DNA material and creating a more complex chromatin structure called a solenoid. These solenoids then further form more complex structures via coiling to form supercoils, allowing for the formation of the structure known as the chromosome via specialized protein-protein interactions and intermolecular forces. A region called the centromere is a constriction in the middle of the chromosome. This region serves as an anchor point for joining sister chromatids and is also where the machinery attaches to separating chromatids during cell division and replication.
Further exploring the structure of chromosomes, a chromosome can be characterized by the position of the centromere, resulting in telocentric, acrocentric, submetacentric, and metacentric chromosomes. Telocentric chromosomes classify as having the centromere at the terminal end of the arm of the chromosome. Due to this positioning, a shorter and longer arm is created; the shorter arm is referred to as the 'p' arm, and the longer arm is the 'q' arm. Acrocentric chromosomes are characterized by the centromere being very near the end of the chromosome, forming a very short p arm and long q arm. Submetacentric chromosomes have the centromere slightly away from the median, resulting in a slightly shorter p arm and minorly elongated q arm. Metacentric chromosomes have the centromere in the middle of the chromosome, with both arms nearly equal in length.
An additional feature of eukaryotic chromosomes is telomeres. These are specialized structures at the end of DNA molecules and allow for continued replication to occur. They consist of many repeats on the 3' end of DNA molecules for stability and elongation. The replication machinery has the unfortunate consequence of losing genetic material from the 3' end in each replication cycle, as it is not able to replicate the entirety of a DNA strand, making the telomere essential to not losing genetic material that encodes for crucial proteins. Also, the telomerase enzyme allows for species-dependent terminal sequences to be added to the 3' end, allowing some protection against this inevitable loss of the end of the DNA sequence.
Chromosomes can exist in the previously described tightly packed structure, referred to as heterochromatin, in which methylation of the DNA and other intermolecular forces keep the structure coiled and condensed. For transcription to occur with RNA polymerase and the other required proteins, the tight heterochromatin structure must unwrap to allow the transcription machinery to access the DNA strands. This looser structure with accessible DNA is referred to as euchromatin.
When describing how many chromosomes are present within a cell, the cell type will determine how many copies of the chromosomes are present. For example, in a human somatic cell, there are 46 total chromosomes, or 23 pairs of chromosomes, in which each pair has one copy of the chromosome from the mother and the second copy from the father. Of the 23 pairs, 22 are autosomal chromosomes, and the last pair are the sex chromosomes. In autosomal chromosomes, these individual chromosomes are homologous as they contain genes that encode for similar traits. These somatic cells are referred to as diploid cells because they contain these homologous pairs within the nucleus. In contrast, haploid cells do not contain these pairs and only contain one set of chromosomes. Examples of haploid cells include germs cells such as sperm and ova. The sex chromosomes are X and Y, with the possible pairs being XX in females and XY in males. The Y chromosome is smaller in size compared to the X chromosome and contains specific genes whose products confer 'maleness' to the being, for example, the SRY gene. Traits encoded on the X chromosome are referred to as X-linked, and females can be homozygous dominant, homozygous recessive, or heterozygous due to the XX genotype. In contrast, males can only be the hemizygous genotype due to the XY genotype.
During cell division and replication, the chromosomes within the cell undergo a variety of changes to form a new identical cell. Various morphologies of the chromosome can be examined in the metaphase and anaphase portions of cell division, as the chromosomes assume a tightly contracted configuration during these phases. Prior to mitosis, the chromosomes duplicate themselves and form pairs of the genetic material. At the beginning of the cell division process, in the prophase, the chromosomal genetic material is in the early stage of condensation. During metaphase, the chromosomes align in the middle of the cell, consisting of two sister chromatids. These sister chromatids are attached to each other by the centromere, and this is the anchor point at which two chromatids become separated during anaphase as the individual chromatids move to opposite poles. After telophase and cytokinesis, the resulting two cells will have the same structures and number of chromosomes as the original parent cell.
Go to:
Testing
The literature references many tests capable of identifying the cause of the non-physiological alteration of a structure before the disease develops or forensically to understand the causes.
Go to:
Pathophysiology
Mosaic trisomy 2 characterized by a highly variable phenotype
Sindrome di Warkany 2 o trisomy 8
Trisomy 9 presents several non-physiological abnormalities, including Coffin-Siris syndrome and malformation of Dandy-Walker
Patau syndrome or trisomy 13
16p13.3 microduplication syndrome
Edwards syndrome or trisomy 18
Down syndrome or trisomy 21
22q11.2 microduplication syndrome
Go to:
Clinical Significance
Throughout the DNA replication and mitosis process, there are many points in this cycle at which errors can occur, such as duplications, deletions, or translocations of whole chromosomes or parts of chromosomes, or failure of a chromosome to migrate to a particular pole, resulting in aneuploidies such trisomy 21 and Turner syndrome.
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Review Questions
Access free multiple choice questions on this topic.
Comment on this article.
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References
1.
Portin P. The birth and development of the DNA theory of inheritance: sixty years since the discovery of the structure of DNA. J Genet. 2014 Apr;93(1):293-302. [PubMed: 24840850]
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McGhee JD, Rau DC, Charney E, Felsenfeld G. Orientation of the nucleosome within the higher order structure of chromatin. Cell. 1980 Nov;22(1 Pt 1):87-96. [PubMed: 7428043]
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Tessarz P, Kouzarides T. Histone core modifications regulating nucleosome structure and dynamics. Nat Rev Mol Cell Biol. 2014 Nov;15(11):703-8. [PubMed: 25315270]
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Luger K, Dechassa ML, Tremethick DJ. New insights into nucleosome and chromatin structure: an ordered state or a disordered affair? Nat Rev Mol Cell Biol. 2012 Jun 22;13(7):436-47. [PMC free article: PMC3408961] [PubMed: 22722606]
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Perea-Resa C, Blower MD. Centromere Biology: Transcription Goes on Stage. Mol Cell Biol. 2018 Sep 15;38(18) [PMC free article: PMC6113603] [PubMed: 29941491]
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Turner KJ, Vasu V, Griffin DK. Telomere Biology and Human Phenotype. Cells. 2019 Jan 19;8(1) [PMC free article: PMC6356320] [PubMed: 30669451]
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Singh PB. Heterochromatin and the molecular mechanisms of 'parent-of-origin' effects in animals. J Biosci. 2016 Dec;41(4):759-786. [PubMed: 27966495]
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Luger K, Richmond TJ. The histone tails of the nucleosome. Curr Opin Genet Dev. 1998 Apr;8(2):140-6. [PubMed: 9610403]
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Makałowski W. The human genome structure and organization. Acta Biochim Pol. 2001;48(3):587-98. [PubMed: 11833767]
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van der Horst A, Lens SM. Cell division: control of the chromosomal passenger complex in time and space. Chromosoma. 2014 Mar;123(1-2):25-42. [PMC free article: PMC3967068] [PubMed: 24091645]
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MacLennan M, Crichton JH, Playfoot CJ, Adams IR. Oocyte development, meiosis and aneuploidy. Semin Cell Dev Biol. 2015 Sep;45:68-76. [PMC free article: PMC4828587] [PubMed: 26454098]
Disclosure:Isha Pathak declares no relevant financial relationships with ineligible companies.
Disclosure:Bruno Bordoni declares no relevant financial relationships with ineligible companies.
Introduction
Development
Molecular Level
Testing
Pathophysiology
Clinical Significance
Review Questions
References
Copyright © 2025, StatPearls Publishing LLC.
This book is distributed under the terms of the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) ( which permits others to distribute the work, provided that the article is not altered or used commercially. You are not required to obtain permission to distribute this article, provided that you credit the author and journal.
Bookshelf ID: NBK557784 PMID: 32491716
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12546 | https://www.zengrc.com/blog/common-risk-management-strategies-risk-avoidance-vs-risk-reduction/ | Common Risk Management Strategies: Risk Avoidance vs. Risk Reduction - ZenGRC
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Common Risk Management Strategies: Risk Avoidance vs. Risk Reduction
ZenGRC Team · August 30, 2024 ·
Home » Common Risk Management Strategies: Risk Avoidance vs. Risk Reduction
Risk is a fact of life for every enterprise. It refers to the possibility that an unexpected event may cause unexpected results. These results are usually undesirable and often harmful. To prevent such harm, it’s crucial to manage and control risk so that it remains at acceptable levels.
This is where enterprise risk management (ERM) enters the picture.
An organization’s ERM program aims to manage risks and mitigate their potential harm. To achieve this goal, the business can employ several risk strategies, also known as risk responses. Two common responses are _risk avoidance_ and _risk reduction_. Other strategies are _risk acceptance_ and _risk transfer_.
How do risk avoidance and risk reduction differ from each other? Which strategy should organizations adopt?
Let’s explore.
What Is Risk?
Risk is the probability that an unexpected situation may arise and affect the organization and its business processes, units, resources, or people. Most organizations face many types of risks. These include:
Strategic risk: The risk that the organization may not be able to achieve its objectives
Operational risk: The risk of loss due to disrupted business operations that might be caused by failed or faulty processes, systems, or people
Financial risk: The possibility that a company may lose money or fail to fulfill its financial obligations, such as servicing debt
Cybersecurity risk: The risk of a cyberattack or data breach compromising business-critical systems or data
Compliance risk: The chance that the organization might behave in a way that violates laws, regulations, or contractual obligations
Environmental risk: Natural disasters or climate change disrupting operations and affecting business continuity
In addition, some organizations face other kinds of risks, such as geopolitical, fraud, health and safety, and reputational risks.
What Is Enterprise Risk Management?
ERM is a holistic and continuous approach to managing risk throughout the organization. It is a disciplined method of identifying risks, preparing the company for future hazards, and enabling the achievement of strategic objectives.
An ERM program should include strategies to manage all the risks applicable to the company. It should assess what kind of future events constitute a risk by considering five key elements:
Risk event: An event that, if realized, might cause unexpected results
Risk factors: Events that might trigger the risk event
Risk probability: The likelihood of the risk event happening
Risk impact: The potential outcome of the risk event
Risk timeframe: The time period during which the risk event might occur and result in unexpected outcomes
An effective risk management process allows the organization to consider, understand, and assess the full range of risks it faces. It examines the potential harm of each identified risk. It also determines which risk management strategy is best suited to minimize and mitigate undesirable consequences.
Two such strategies are _risk avoidance_ and _risk reduction_.
What Is Risk Avoidance?
For robust ERM, risk identification and an assessment of likelihood and impact are only the preliminary steps. It’s also essential to _address_ each specific risk to minimize the possibility of adverse consequences. There are many ways to handle different kinds of risks. One such way is _risk avoidance_.
Risk avoidance means completely eliminating any hazard that might harm the organization, its assets, or its stakeholders; and removing the chance that the risk might become a reality. This strategy aims to deflect as many threats as possible to avoid their costly consequences.
It is commonly assumed that risk avoidance means ignoring or failing to identify business risks and project risks. This is not true. Risk avoidance is a _deliberate_ tactic. Like any other risk management strategy, it requires a systematic approach; and consists of the following steps:
Identify risks
Assess the probability and potential impact of each risk
Calculate risk exposure by quantifying the potential losses that may result if the risk is realized
Take steps to eliminate the risk
Examples of Risk Avoidance
An organization may decide not to make a risky investment. After analyzing the investment risks and rewards, risk managers may deem the project – say, buying a smaller company and integrating its technology into yours – too risky and not worth the potentially high reward. Thus, by choosing not to invest, they can avoid the risk of loss.
Or a company may choose to implement a proven and pre-tested technology instead of adopting a new, untested technology. The newer solution may cost less or have innovative features that could improve the organization’s performance, but could also present a higher risk of breakdowns or data breaches. The company can avoid these risks by going with the older, proven technology.
When to Use the Risk Avoidance Strategy
Risk avoidance can be the best risk management strategy when a risk could cause substantial or irreparable harm to the organization. On the other hand, when a risk isn’t likely to have a significant impact, avoidance may end up being too costly. The organization may miss out on positive opportunities, such as lower expenses or operational improvements.
To assure that the strategy is applied correctly to each risk, a thorough risk analysis and risk assessment are essential. It’s also important to determine exactly how the risk will be avoided and how that strategy could benefit the company.
The avoidance strategy may not be feasible for long-term threats. If avoidance increases costs or causes other problems, the organization should re-evaluate this response and consider different responses that could minimize the potential for loss.
What Is Risk Reduction?
While risk avoidance is about removing a risk completely, risk reduction is about lowering the risk to make its consequences less severe. The main goal is to limit the potential harm that may be caused by a risk.
The terms _risk reduction_ and _risk mitigation_ are frequently used interchangeably, although they are not the same. Risk mitigation refers to reducing the expected loss if a risk event happens. Generally, mitigation implies that the risk event or risky activity is still there, but the organization has created a risk mitigation plan to make it less risky.
Reducing risk is about reducing the expected loss from a risk or reducing the likelihood that the risk may occur. It includes the possibility of avoiding the risk altogether, but doesn’t require total avoidance. For example, you can mitigate the impact of a natural disaster, but you can’t reduce the likelihood of a natural disaster happening.
Examples of Risk Reduction
An organization may implement a quality management system (QMS) to assure that its goods and services meet pre-defined specifications or quality standards. This risk reduction strategy aims to lower the risk that output quality will be poor or undesirable to stakeholders.
Another example is implementing a digital platform such asZenGRCto track regulatory requirements, implement the required controls to maintain compliance, and reduce the risks of non-compliance.
Other examples of risk reduction include:
Changing a process to reduce health and safety-related risks
Changing the organizational culture to reduce the risk of high employee turnover
Performing due diligence on third parties to assure that the party doesn’t pose excessive security or compliance risks
When to Use the Risk Reduction Strategy
If a risk cannot be entirely avoided, reduction may be the most suitable option. For example, it’s almost impossible to avoid the risk of a cyberattack entirely. Organizations can, however, reduce the likelihood of a security event by implementing antivirus and anti-malware software, firewalls, endpoint detection and response (EDR), and other security solutions.
Risk Avoidance vs. Risk Reduction
Risk avoidance is the only risk management strategy where the goal is to eliminate all probability of a risk from happening. It is usually adopted when the risk can potentially inflict catastrophic damage or when the costs of risk mitigation are higher than the benefits.
On the other hand, risk reduction requires taking specific actions to minimize the likelihood of the possible risk. It may involve implementing controls, policies, or procedures to reduce the chances of harm and make the risk less severe and more manageable. The risk does now, however, disappear completely; the organization has to find a way to “live” with it.
How Risk Avoidance and Risk Reduction Are Part of a Risk Management Plan
Whether a firm adopts a risk avoidance or risk reduction strategy depends on the type of risk in question and its potential impact on the company’s finances, processes, security, workforce, and customers.
To choose the right strategy, it’s vital to identify the risks that affect (or may affect) the organization. It’s also critical to quantify each risk to assess its potential impact.
In general, the success of both strategies depends on:
Creating and communicating policies
Implementing proper procedures
Leveraging the right technology to support the strategy
Training employees to assure that they behave in risk-appropriate ways
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12547 | https://www.tu-braunschweig.de/index.php?eID=dumpFile&t=f&f=138377&token=ce78f1a73be3528669c0a5a4a6675d0e3284b02e | The Boltzmann factor: A simplified derivation
Rainer M¨ uller
Technische Universit¨ at Braunschweig, Physikdidaktik, Bienroder Weg 82, D-38106 Braunschweig, Germany E-mail: rainer.mueller@tu-bs.de
Abstract. We give a simple derivation of the Boltzmann factor from amicrocanonical point of view. The derivation is similar to Boltzmann’s own approach but avoids the use of Lagrangian multipliers. In the Boltzmann-Einstein model, we consider an assembly of n + 1 boxes. One of the boxes represents the system under consideration, the others act as a thermal reservoir. Energy is distributed over the combined system in discrete portions, not necessarily of quantum character. We derive the probability for the system to have a certain number of energy portions by counting the number of compatible states, thus arriving at the Boltzmann factor. PACS numbers: 01.40.-d, 05.20.-y The Boltzmann factor: A simplified derivation 2
Introduction
The Boltzmann distribution law for the probability of a system to be in a state with a certain energy E is generally considered as one of the most important laws of statistical physics. Feynman calls it the “summit of statistical mechanics”. Indeed, the applications of the Boltzmann law range from the most theoretical to the most practical: from astroparticle physics over chemistry to solid state technology. Any book on statistical mechanics gives a derivation of the Boltzmann factor. There are a number of different approaches that are common in the literature: (i) Lagrangian multiplier approach: This method dates back to Boltzmann’s famous 1877 paper . Portions of energy are distributed over the discrete energy levels of an assembly of “atoms” or “oscillators”. The probability of an energy distribution is proportional to the number of ways it can be realized. The most probable distribution is found by a Lagrangian multiplier method which accounts for the constraints of fixed energy and particle number. (ii) Use of symmetry arguments: There is a method of unparalleled simplicity for finding the Maxwell-Boltzmann velocity distribution. It was already given by Maxwell in his original 1860 paper . Because of symmetry, the probability distribution for the velocity components factors into a product of three terms (one for each spatial direction). Furthermore the distribution must not depend on the vector components themselves but only on the coordinate-independent scalar ~v2. With this argument, Maxwell obtains a functional equation for the probability distribution which is only fulfilled for the exponential function. (iii) Quasicontiuum approach: When passing from the microcanonical to the canonical ensemble, most books in Theoretical Physics consider a small system coupled to a heat bath. The combined system has a quasicontinuous distribution of energy levels. Because the probability factorizes, the probability for the system of being in a state with energy Ej is proportional to the number of microstates available to the reservoir with energy Etot − Ej . A first-order Taylor expansion of the logarithm of the probability leads to the Boltzmann factor. In addition to the classic approaches described above, there are a number of alternative arguments for the Boltzmann factor: Feynman appealed to the barometric formula; Leff considers a two-level system coupled to a reservoir with the probabilities interpreted as fraction of time the system is in the corresponding state. A version of the quasicontinuum approach is presented Kittel and Kroemer , and similarly by Moore . They relate the probability to the entropy via Boltzmann’s formula and then perform a first-order expansion of the entropy. Hannay treats a model with statistical jumps and determines the stationary energy distribution. L´ opez-Ruiz, Sa˜ nudo and Calbet give a geometrical derivation, and McDowell calculates the Boltzmann factor via the change in entropy when a small portion of energy is added to the system. In addition, there are a number of heuristic arguments (e. g. ). The Boltzmann factor: A simplified derivation 3The approach by Boltzmann is probably the one which imparts the deepest insights into the nature of the statistical approach. It sheds light on the stunning fact that the basic operation in statistical mechanics is counting . However, it needs the Lagrangian multiplier method which is beyond the mathematical capabilities for most students in introductory courses. In this paper, we give a derivation of the Boltzmann factor which is similar to Boltzmann’s own approach but avoids the use of Lagrangian multipliers. We consider the Boltzmann-Einstein model (also called the Einstein solid) which is mathematically simple but sufficiently abstract to serve as a model for many real systems. Within the model, we describe a small system in thermal equilibrium with a large reservoir. Concentrating on the small system alone, we ask for the probability for a state with energy Ej if the reservoir’s temperature is T . In contrast to the third approach mentioned above, we will not assume a quasicontinuum of states because we do not want to abandon the idea of counting discrete states. Within the microcanonical formalism, we arrive at the Boltzmann factor by combinatorial arguments. The model is similar to the one used, for example, by Callen , Dugdale , and Moore and Schroeder when they derive a microscopic foundation for thermodynamic variables like entropy and temperature. Essentially the same approach has been taken by Friedman and Grubbs . However, the complicated combinatorial formulas in their paper are likely to overwhelm the students. We have tried to keep the mathematics as simple as possible to make the method more accessible to students.
The model
The model we use is often called the Einstein solid . We consider an assembly of
n “atoms” or “boxes” which can hold an integral number of energy portions ǫ. Their possible energy values are 0, ǫ, 2 ǫ, 3 ǫ, . . . . The model is characterized by two integer numbers: n, the number of atoms, and u, the number of energy portions. The internal energy of the system is U = u · ǫ.The obvious physical realization of the model is a collection of quantum mechanical harmonic oscillators. Nevertheless, the model is not so quantum mechanical as it may seem. In fact it was introduced already by Boltzmann to model continuous degrees of freedom: He used it as a vehicle to derive the Maxwell-Boltzmann velocity distribution for gas molecules . By choosing ǫ arbitrarily small, we can approximate any continuous energy value by a rational number. For the sake of simplicity, we continue to speak of atoms, although for historical correctness, we will refer to the model as the Boltzmann-Einstein model. There is no direct interaction between the atoms. In accordance with the basic postulate of statistical mechanics, transitions between states with the same total energy
U are thought to be induced by minute interactions with the environment. Callen gives a clever method to determine the number of ways in which u
portions of energy can be distributed among n boxes. Each energy portion is represented by a marble while n − 1 match sticks act as “dividers” between two boxes. Thus the The Boltzmann factor: A simplified derivation 4
eee
=
^
sticks marbles
Figure 1. Construction for finding the number of possibilities for distributing u
portions of energy among natoms
problem is equivalent to finding the number of permutations of u marbles and n − 1match sticks arranged in a row (Fig. 1). The number of possible energy distributions is called the multiplicity Ω( u, n ). It is given by: Ω( u, n ) = (n − 1 + u)!
u! ( n − 1)! . (1) This quantity is thermodynamically significant because it is related to the entropy via
S = kB ln Ω, where kB is Boltzmann’s constant. We stress that with this method of counting there is no need to impose additional constraints for keeping the energy and the particle number constant. They are automatically accounted for.
An atom plus a reservoir
We now consider an assembly of n + 1 atoms. One of them is singled out as a probe, the remaining n atoms constitute the reservoir. In the following the probe atom is simply referred to as “the atom”. Our goal is to determine the probability pj to find it in a state with energy Ej = j · ǫ in thermal equilibrium. There are u energy portions to distribute over the system (which consists of the atom plus the reservoir). We have to ask in how many ways this can be done, given that the atom has a share of j energy portions. Because the atom and the reservoir are only weakly coupled, there are no energy portions that are shared between the atom and the reservoir in the form of binding energy. The multiplicity can therefore be written as a product: Ω( j, u, n + 1) =number of ways to distribute j portions over the atom
× number of ways to distribute u − j portions over the reservoir .
(2) The first factor equals 1 because we are dealing with a single state of the atom with a unique distribution of energy. Thus, the multiplicity is just the number of reservoir states with energy ( u − j)ǫ. With Eq. (1) we obtain: Ω( j, u, n + 1) = (n − 1 + u − j)!
(u − j)! ( n − 1)! . (3) In a teaching situation, it is helpful to explore the possible energy distributions for small n and u with concrete numbers. Moore and Schroeder point out an insightful The Boltzmann factor: A simplified derivation 5
„Atom“
eeeeeee
( . .+1) W!j !u !n
eeeeeee
eeeeeee
eeeeeee
e e eeeee
e eeee ee
e eee eee
j= 0
j= 1
j= 2
j= 3
j= 4
j= 5
j= 6
eeeeeee
j= 7 1716 924 462 210 84 28 710.5 0.27 0.13 0.06 0.02 0.008 0.002 0.0003
pj
Figure 2. Distributing u= 7 energy portions over n+ 1 = 8 boxes. The total number of states is Ω( u, n + 1) = 3432. The rows represent the number of states with jenergy portions in the atom.
way to do this with the help of spreadsheet software. The students are able at this point to qualitatively understand the form of the Boltzmann distribution. If there is more energy concentrated in the atom, there is less energy left to be distributed over the reservoir. Since the multiplicity grows with the number of energy portions, atom states with a higher energy are less probable because there are less available reservoir states. An example with u = 7 energy portions distributed over n + 1 = 8 boxes is shown in Fig. 2. The multiplicities have been calculated with Eq. (3). Before making this argument quantitative we have to define a temperature for the system. The entropy of n + 1 atoms with internal energy u · ǫ is:
S = kB ln Ω( u, n + 1) = kB ln (n + u)!
u! n! (4) (cf. Eq (1)). For large n and u, this expression can be simplified with Stirling’s formula ln m! ≈ m ln m − m. We obtain
S = kB
[
n ln
(
1 + u
n
)
u ln
(
1 + n
u
)]
. (5) The Boltzmann factor: A simplified derivation 6This expression for S(u, n ) is the fundamental equation for the model from which all macroscopic thermodynamic information can be derived . The temperature can be defined if we treat u for the moment as a continuous variable: 1
T = ∂S
∂(uǫ ). (6) We find: ǫ
kBT = ln
(
1 + n
u
)
, (7) which takes a more familiar when we solve for U = u · ǫ:
U = n · ǫ
e ǫ
kBT
− 1. (8) We now return to our primary question: finding the probability pj for the atom to be in a state with energy j · ǫ. It is given by ratio of Ω( j, u, n + 1) to the total number of states available to a system with n + 1 atoms and energy u · ǫ:
pj = Ω( j, u, n + 1)
Ω( u, n + 1) = (n − 1 + u − j)! u! n!
(u − j)! ( n − 1)! ( n + u)! = n · (n − 1 + u − j)! u!
(u − j)! ( n + u)! . (9) We now apply Stirling’s formula to the logarithm of pj . It is useful to separate beforehand a factor ( n + u) from the factorial in the last term of Eq. (9):
pj = n
n + u · (n − 1 + u − j)! u!
(u − j)! ( n + u − 1)! , (10) We thereby accomplish that the linear part of ln m! ≈ m ln m − m does not contribute at all because all the terms cancel. We obtain: ln
(
pj
n + u
n
)
= ( n+u−j−1) ln( n+u−j−1)+ u ln u−(u−j) ln( u−j)−(n+u−1) ln( n+u−1) .
(11) Within the slowly varying logarithms, we approximate u − j ≈ u. This is equivalent to assuming that for a large reservoir, the reservoir does not “feel” the energy taken away by a single atom. A huge cancellation of terms occurs, and we end up with: ln
(
pj
n + u
n
)
= −j ln
(
1 + n
u
)
. (12) With Eq. (7), the last factor is identified as the inverse temperature of the system so that we can write: ln
(
pj
n + u
n
)
= −j ǫ
kBT . (13) Solving for pj , we obtain our result,
pj = n
n + u exp
(
− j · ǫ
kBT
)
, (14) The Boltzmann factor: A simplified derivation 7which is the well-known Boltzmann factor:
pj ∝ exp
(
− Ej
kBT
)
, (15) Expression (14) is already properly normalized if we allow j to vary to infinity:
∞
∑
j=0
pj = n
n + u
∞
∑
j=0
exp
(
− j · ǫ
kBT
)
= n
n + u
∞
∑
j=0
( u
u + n
)j
= 1 . (16)
Conclusion
Within the Boltzmann-Einstein model, we have derived the Boltzmann factor as the probability for an atom coupled to a reservoir to hold j out of u energy portions. We arrived at our result by the most simple of all mathematical operations—by counting. In a combinatorial analysis we counted the subset of the total available states in which the atom has j energy portions. While the exact formula is given by Eq. (10), the well-known exponential form of Eq. (14) is an excellent approximation if the reservoir is large.
References
R. P. Feynman, Statistical mechanics: A set of lectures (edited by Jacob Shaham), Redwood City: Addison-Wesley (1990). L. Boltzmann, ¨Uber die Beziehung zwischen dem zweiten Hauptsatz der mechanis-chen W¨ armetheorie und der Wahrscheinlichkeitsrechung respektive den S¨ atzen ¨uber das W¨ armegleichgewicht, Wien. Ber. 76 , 373-435 (1877). J. C. Maxwell, Illustrations of the dynamical theory of gases, Philosophical Magazine 19 , 19-32 (1860). H. S. Leff, Answer to Question ♯14, Am. J. Phys. 63 , 877-878 (1995). C. Kittel, H. Kroemer, Thermal physics, New York: Freeman (1980). T. Moore, Six Ideas that shaped physics, Unit T – Some processes are irreversible, New York: McGraw Hill (2003). J. H. Hannay, Answer to Question ♯14, Am. J. Phys. 63 , 877 (1995). R. L´ opez-Ruiz, J. Sa˜ nudo, X. Calbet, A geometrical derivation of the Boltzmann factor, Am. J. Phys. 76 , 780 (2008). S. A. C. McDowell, A Simple Derivation of the Boltzmann Distribution, J. Chem. Educ. 76 ,1393-1394 (1999). C. A. Whitney, Answer to Question ♯14, Am. J. Phys. 63 , 876-877 (1995). H. B. Callen, Thermodynamics and an Introduction to Thermostatistics, 2nd Edition, New York: Wiley & Sons (1985), Chapter 15. J. S. Dugdale, Entropy and its physical meaning, London: Taylor & Francis (1996), Chapter 7. T. A. Moore, Daniel V. Schroeder, A different approach to introducing statistical mechanics Am. J. Phys. 65 , 26-36 (1997). E. Friedman, W. T. Grubbs, The Boltzmann Distribution and Pascal’s Triangle, Chem. Educator
8, 116-121 (2003). |
12548 | https://openstax.org/books/biology-2e/pages/3-chapter-summary | Ch. 3 Chapter Summary - Biology 2e | OpenStax
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Biology 2e
Chapter Summary
Biology 2eChapter Summary
Contents Contents
Highlights
Table of contents
Preface
The Chemistry of Life
1 The Study of Life
2 The Chemical Foundation of Life
3 Biological Macromolecules
Introduction
3.1 Synthesis of Biological Macromolecules
3.2 Carbohydrates
3.3 Lipids
3.4 Proteins
3.5 Nucleic Acids
Key Terms
Chapter Summary
Visual Connection Questions
Review Questions
Critical Thinking Questions
The Cell
Genetics
Evolutionary Processes
Biological Diversity
Plant Structure and Function
Animal Structure and Function
Ecology
A | The Periodic Table of Elements
B | Geological Time
C | Measurements and the Metric System
Index
Search for key terms or text.
Close
3.1 Synthesis of Biological Macromolecules ------------------------------------------
Proteins, carbohydrates, nucleic acids, and lipids are the four major classes of biological macromolecules—large molecules necessary for life that are built from smaller organic molecules. Macromolecules are comprised of single units scientists call monomers that are joined by covalent bonds to form larger polymers. The polymer is more than the sum of its parts: it acquires new characteristics, and leads to an osmotic pressure that is much lower than that formed by its ingredients. This is an important advantage in maintaining cellular osmotic conditions. A monomer joins with another monomer with water molecule release, leading to a covalent bond forming. Scientists call these dehydration or condensation reactions. When polymers break down into smaller units (monomers), they use a water molecule for each bond broken by these reactions. Such reactions are hydrolysis reactions. Dehydration and hydrolysis reactions are similar for all macromolecules, but each monomer and polymer reaction is specific to its class. Dehydration reactions typically require an investment of energy for new bond formation, while hydrolysis reactions typically release energy by breaking bonds.
3.2 Carbohydrates -----------------
Carbohydrates are a group of macromolecules that are a vital energy source for the cell and provide structural support to plant cells, fungi, and all of the arthropods that include lobsters, crabs, shrimp, insects, and spiders. Scientists classify carbohydrates as monosaccharides, disaccharides, and polysaccharides depending on the number of monomers in the molecule. Monosaccharides are linked by glycosidic bonds that form as a result of dehydration reactions, forming disaccharides and polysaccharides with eliminating a water molecule for each bond formed. Glucose, galactose, and fructose are common monosaccharides; whereas, common disaccharides include lactose, maltose, and sucrose. Starch and glycogen, examples of polysaccharides, are the storage forms of glucose in plants and animals, respectively. The long polysaccharide chains may be branched or unbranched. Cellulose is an example of an unbranched polysaccharide; whereas, amylopectin, a constituent of starch, is a highly branched molecule. Glucose storage, in the form of polymers like starch of glycogen, makes it slightly less accessible for metabolism; however, this prevents it from leaking out of the cell or creating a high osmotic pressure that could cause the cell to uptake excessive water.
3.3 Lipids ----------
Lipids are a class of macromolecules that are nonpolar and hydrophobic in nature. Major types include fats and oils, waxes, phospholipids, and steroids. Fats are a stored form of energy and are also known as triacylglycerols or triglycerides. Fats are comprised of fatty acids and either glycerol or sphingosine. Fatty acids may be unsaturated or saturated, depending on the presence or absence of double bonds in the hydrocarbon chain. If only single bonds are present, they are saturated fatty acids. Unsaturated fatty acids may have one or more double bonds in the hydrocarbon chain. Phospholipids comprise the membrane's matrix. They have a glycerol or sphingosine backbone to which two fatty acid chains and a phosphate-containing group are attached. Steroids are another class of lipids. Their basic structure has four fused carbon rings. Cholesterol is a type of steroid and is an important constituent of the plasma membrane, where it helps to maintain the membrane's fluid nature. It is also the precursor of steroid hormones such as testosterone.
3.4 Proteins ------------
Proteins are a class of macromolecules that perform a diverse range of functions for the cell. They help in metabolism by acting as enzymes, carriers, or hormones, and provide structural support. The building blocks of proteins (monomers) are amino acids. Each amino acid has a central carbon that bonds to an amino group, a carboxyl group, a hydrogen atom, and an R group or side chain. There are 20 commonly occurring amino acids, each of which differs in the R group. A peptide bond links each amino acid to its neighbors. A long amino acid chain is a polypeptide.
Proteins are organized at four levels: primary, secondary, tertiary, and (optional) quaternary. The primary structure is the amino acids' unique sequence. The polypeptide's local folding to form structures such as the α-helix and β-pleated sheet constitutes the secondary structure. The overall three-dimensional structure is the tertiary structure. When two or more polypeptides combine to form the complete protein structure, the configuration is the protein's quaternary structure. Protein shape and function are intricately linked. Any change in shape caused by changes in temperature or pH may lead to protein denaturation and a loss in function.
3.5 Nucleic Acids -----------------
Nucleic acids are molecules comprised of nucleotides that direct cellular activities such as cell division and protein synthesis. Pentose sugar, a nitrogenous base, and a phosphate group comprise each nucleotide. There are two types of nucleic acids: DNA and RNA. DNA carries the cell's genetic blueprint and passes it on from parents to offspring (in the form of chromosomes). It has a double-helical structure with the two strands running in opposite directions, connected by hydrogen bonds, and complementary to each other. RNA is a single-stranded polymer composed of linked nucleotides made up of a pentose sugar (ribose), a nitrogenous base, and a phosphate group. RNA is involved in protein synthesis and its regulation. Messenger RNA (mRNA) copies from the DNA, exports itself from the nucleus to the cytoplasm, and contains information for constructing proteins. Ribosomal RNA (rRNA) is a part of the ribosomes at the site of protein synthesis; whereas, transfer RNA (tRNA) carries the amino acid to the site of protein synthesis. The microRNA regulates using mRNA for protein synthesis.
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12549 | https://app.jove.com/science-education/v/12480/reduction-of-benzene-to-cyclohexane-catalytic-hydrogenation | Video: Reduction of Benzene to Cyclohexane: Catalytic Hydrogenation
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18.21 : Reduction of Benzene to Cyclohexane: Catalytic Hydrogenation
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18.21 : Reduction of Benzene to Cyclohexane: Catalytic Hydrogenation
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Unlike the easy catalytic hydrogenation of an alkene double bond, hydrogenation of a benzene double bond under similar reaction conditions does not take place easily. For example, in the reduction of stilbene, the benzene ring remains unaffected while the alkene bond gets reduced. Hydrogenation of an alkene double bond is exothermic and a favorable process. In contrast, to hydrogenate the first unsaturated bond of benzene, an energy input is needed; that is, the process is endothermic. This is because of resonance stabilization of the ring, that makes the ring extra stable the bond inert to regular hydrogenation conditions. Hydrogenation of the benzene ring requires extreme conditions of temperature and pressure, along with the use of specific catalysts. For example, benzene can be reduced to cyclohexane using three moles of hydrogen with nickel catalyst at 100 atm and 150 °C. The intermediates cyclohexadienes and cyclohexene are highly reactive and cannot be isolated because they are very reactive than benzene. In the case of disubsitutued benzenes, catalytic hydrogenation yields a mixture of cis and trans isomers.
Transcript
Recall that catalytic hydrogenation of an alkene double bond occurs under normal reaction conditions. Under similar conditions, however, a benzene double bond will not be reduced.
This is illustrated in the hydrogenation of stilbene, where under normal conditions, only the olefinic bond is selectively reduced, leaving the benzene rings unaffected.
Hydrogenation of an alkene double bond is exothermic, whereas hydrogenating the first unsaturated bond in benzene is an endothermic process. This is because the benzene ring is highly stabilized by resonance and resists hydrogenation.
Hydrogenation of the benzene ring becomes possible if extreme conditions of temperature and pressure and specific catalysts are used.
For instance, reducing the benzene double bonds to give a cyclohexane ring requires 3 moles of hydrogen and a nickel catalyst at 100 atm and 150 °C.
The reaction proceeds through highly reactive intermediates that are far more reactive than benzene, and therefore, cannot be isolated.
Benzene undergoes step-wise hydrogenation, with the Δ H° of the first hydrogenation step being positive. This explains why extreme reaction conditions are required to completely reduce benzene to cyclohexane.
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Catalytic HydrogenationBenzeneCyclohexaneAlkeneResonance StabilizationTemperaturePressureNickel CatalystCyclohexadienesCyclohexeneDisubstituted BenzenesCis And Trans Isomers
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12550 | https://www.youtube.com/watch?v=yfoTKF-gTYg | How to Restrict the Domain so the Inverse is a Function
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In this video we discuss 2 examples to show you how to restrict the domain so that the inverse is a function. We discuss the vertical and horizontal line test, domain and range, graphically what the inverse of the function looks like, and more.
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Transcript:
in this video you're going to learn how to restrict the domain so that the inverse is a function and we're going to go through two examples together so let's start with this first example if we have f of x is equal to the quantity X plus 3 squared let's just graph this to get a sense of what this graph looks like now we know that x squared that's a parabola shape and the plus 3 here is going to have the opposite effect it's going to shift the graph left 3. so this graph is going to look something like this roughly okay now when you do the vertical line test what the vertical line test it tests to see if this graph here is a function meaning for every x value there's only one y value and you can see that it passes that vertical line test but there's something called the horizontal line test where you take a line like this and you scan up and down and you see if the graph crosses more than once and in this case you can see that it does cross more than once which means that it fails that horizontal line test meaning that the inverse is not a function so for every y value see how there's more than one x value so what we're going to do is we're going to restrict the domain now we have two options with this problem we can either say that we're going to look at just this right branch of the graph this part right here or the left branch of the graph because if I just look at one half of this Parabola it would pass that horizontal line test meaning the horizontal line would only cross the graph at most once so let's do this problem two different ways so you can see both ways so here at negative 3 if we restrict the domain and say where X is greater than or equal to negative three and we find the inverse now what we're going to do is we're going to Interchange the X and the Y and we're going to solve for the new y so when you think of f of x you can think of this as our output or our y value so we inch interchange the input in the output or the X and the Y and then we solve for the new y so here what I'm going to do is I'm going to take the square root of both sides okay the square and the square root cancel remember when you take the square root of both sides of the equation you get two answers plus or minus okay positive or negative and so now we're down to Y plus 3 is equal to positive or negative square root of x and then if I subtract 3 from both sides this comes out to let's see plus or minus square root of x minus 3 equals y or let's just flip it over so we can see it from a different perspective here y equals plus or minus the square root of x minus three now going back to this original graph here let me make this a little bit darker see we said the domain is what the axis can be X is greater than or equal to negative 3. the range is what the Y's can be and here you can see that Y is greater than or equal to zero but what happens when you interchange the X and the Y the domain and the range switch as well because the domain is associated with the X and the range is associated with the Y right so what happens here is we're going to look at this graph and when you find the inverse you're reflecting that graph over the line Y is equal to X that's what happens when you find the inverse and so if you look at this branch of the the right branch of this graph when I fold it over this line Y equals X we're going to get a graph that looks something that looks like that okay it's just the mirror image now when you look at this here you say oh okay so that means that this is y is equal to the positive square root of x minus 3 okay and you could write this in the inverse notation F inverse of X that's what this minus 1 represents equals square root of x minus 3 and that's this Branch right here now if we were to do this another way here by looking at the left Branch okay so let's maybe draw this as a dashed or dotted line like that now we're saying okay let's let X be less than or equal to negative three when we take this Dash graph and we fold it over the line Y equals X we're going to get this graph right here which this graph is the graph y is equal to negative square root of x minus 3. so depending on which part of the graph that you use you have to kind of pay attention when you find the inverse now what's interesting is see here I've written this in inequality notation let's write it in the interval notation so the domain is going to be from negative 3 to infinity and the range is going to be from 0 to Infinity but what happens when we find our our inverse graph okay over here remember how we said the domain and the range switch so this range here would really become the domain here and that's going to be uh where X is greater than or equal to zero or you could say from 0 to infinity and you can see that's what's happening right here for for the domain now as far as the range of this inverse function the range would be negative 3 to positive infinity and you can see this is going from negative 3 and upward like that so what you can see is that if you find the domain in the range on the original graph by interchanging those you'll know what the domain and the range are on the inverse graph and so that'll help you when you're graphing and it'll just help you when you're writing your notation let's take a look at another example okay for example number two now we have f of x is equal to 2 times the absolute value of x minus 1 plus 2. let's start off by graphing this to get a sense of what this looks like we know that this graph is going to be going right one up two and so this is where the vertex of the absolute value graph is and we know it's being stretched vertically by a factor of two so this is going to have kind of like a slope of two you're going up two over one up two over one and so there's our absolute value graph okay now when we look at this we can see that it's failing that horizontal line test right so that tells you for a given y value you can see there's more than one x value which means that the inverse is not going to be a function so what we're going to do in order to make the inverse a function we're going to restrict the domain meaning what the X values can be and so let's take a look at this right branch of the graph right here let's see right here where X is one if we just go to where it's right of one just this right Branch let me make it a little bit thicker a little bit wider here so we can see it a little bit better now when we do the horizontal line test you can see it crosses only at most once so that tells us that the inverse will be a function so let's go ahead and put our restriction here let's say when X is greater than or equal to 1 or we'll just say from for our domain we'll say 1 to Infinity now the range is going to be the Y values you can see that that's going to be from 2 to Infinity now let's go ahead and find the inverse so when we find the inverse remember we switch the X and the Y and we solve for the new y so if I do that we get X is equal to now let's take a look at this line for a moment so this this is really like a line half of this absolute value graph and this line you can see if I kind of continue it down like this okay that's our line and so it has a slope of 2 and a y intercept of zero so really the equation of this line is just Y is equal to 2x plus 0 or just y equals 2x so I'm just going to Interchange the X and the Y and solve for the new y so to get this y by itself I'm going to multiply both sides by one half and so now we get one half X is equal to y or if I flip it Y is equal to one half X or we can write it in the inverse notation by saying F inverse of X is equal to one half X now remember when you find the inverse graphically what it looks like it's a reflection over the line Y equals X so the line Y equals X is this 45 degree line it has like a slope of one so I'll try to draw it accurately here for us so it looks something like like that right let's label that Y equals X and when I fold that right Branch over that graph it's going to look something like this right and it's going to be the line Y equals one half X but notice the domain and the range are switching so the range becomes the domain over here so this is going to be X is greater than or equal to 2 or you could in interval notation you could say from 2 to infinity and the range is going to be from 1 to Infinity so basically we're graphing this line Y equals one half X okay which would look like this rise one run two rise one run two okay but we only want the part of this line where it's greater than or equal to two so basically from here onwards we just want this part of the line okay now looking at the other half of the absolute value graph the part of this graph here I've drawn is a dashed or dotted line we're going to look at where X is less than or equal to one or to the left of one here so if we do that we're going to be looking at a domain of negative Infinity to one and the range is still going to be from 2 to positive Infinity but when you look at this dashed or dotted line what's the equation of that line well it has a y intercept of four and has a slope of negative two so our equation is really Y is equal to negative two X plus four to find the inverse we interchange the X and the Y and we solve for that new y so I'm going to subtract 4 from both sides and multiply everything by negative one-half so that's going to give us negative one half X plus two is equal to y or we can flip it and use the inverse notation F inverse of X is equal to negative one half X plus 2 and we want to keep in mind that when we find this inverse the domain and the range switch right so what happens is the range actually becomes the domain of our inverse function so we could say x is greater than or equal to 2 or if you're using the interval notation you can say from 2 to infinity and our range is going to be from negative Infinity to 1. now graphically what that looks like when you fold the stashed or dotted line over the line Y equals X is going to look like this equation right here negative one half X plus two now here's the Y intercept of 2 slope of negative one half that's down one over two okay down one over two and what's interesting though is we only want to start when X is greater than or equal to 2. so we just want this part of the graph right here I should have drawn that as a dashed or dotted line just to show you that it matches up with this Dash or dotted line so you can see if we were to take this whole absolute value graph and reflect it we would get this V shape graph on its side and it would fail the vertical line test meaning that you know that this is not a function with the horizontal line test says before you do that if you do the horizontal line test if it crosses more than once then without having to graph this you can see it's going to pass or fail the vertical line test so it's just a shortcut technique but here what we're talking about is how to restrict that domain so that the inverse is a function if you want to see more examples follow me to another video I did on this topic right there and we'll get some more practice I'll see over in that video |
12551 | https://davidwills.us/math103/Symmetry/ | Symmetry
Symmetric pair of points:
| | Y-axis symmetry: (x,y) and (-x,y) are symmetric w.r.t. the Y-axis. As are (-x,-y) and (x,-y). The x's are negatives of each other. They "jump"/"flip" across the Y axis. A horizontal line connects them. X-axis symmetry: (x,y) and (x,-y) are symmetric w.r.t. the X-axis. As are (-x,-y) and (-x,y). The y's are negatives of each other. They "jump"/"flip" across the X axis. A vertical line connects them. Origin symmetry: (x,y) and (-x,-y) are symmetric about the origin. As are (-x,y) and (x,-y). Both the x's and the y's are negatives of each other. They "jump"/"flip" across both the X axis and the Y axis, in either order. They are both X-axis symmetric and Y-axis symmetric. Equivalently, they rotate 180° around/about the origin. A line through the origin connects them. |
Whichever symmetry, the pair of points are the same distance from the X-axis, the same distance from the Y-axis, and the same distance from the origin.
Symmetries of the graph of an equation (or restricted to a function):
Y-axis symmetry: flipping every point across the Y-axis gives the same graph. Every (x,y) iff (-x,y). A reflection across the Y axis. The mirror image looking at the mirror on the Y axis. A horizontal line connects each pair of symmetric points. f(x)=f(-x) and -f(x)=-f(-x) i.e. Even function.
X-axis symmetry: flipping every point across the X-axis gives the same graph. Every (x,y) iff (x,-y). A reflection across the X axis. The mirror image looking at the mirror on the X axis. A vertical line connects each pair of symmetric points. NB. A function cannot be symmetric about the X-axis. Multiplying a function by -1, i.e. -f(x), flips it over X axis.
Origin symmetry: flipping every point across both the X-axis and the Y-axis (in either order) or, equivalently, rotating every point 180° about origin gives the same graph. Every (x,y) iff (-x,-y). ≡ . A reflection across X axis and across Y axis, in either order. A line through the origin connects each pair of symmetric points. f(-x)=-f(x) and f(x)=-f(-x) i.e. Odd function.
A graph can be none, one, or all three of these symmetries. i.e. 0, 1, or 3 of them. If is X-axis symmetric and Y-axis symmetric, then is Origin symmetric: X & Y → Origin. (but Origin symmetry does not necessarily imply X and Y symmetry.) If a graph is any two of these symmetries, it is also the third (i.e. can not be symmetric with only two of them). The graph of a function can be one or none (either Y symmetry, or Origin symmetry, or neither).
Algebraic testing for symmetries: (If not a function) Test the equation for X-axis symmetry: replace y by -y; if this new equation equals the original, the equation is X-axis symmetric.
Test for Y-axis symmetry: replace x by -x; if this new equation equals the original, the equation is Y-axis symmetric. For a function: if f(x) = f(-x) then ƒ is symmetric about Y-axis; it is an even function; Stop.
If the graph is neither X nor Y symmetric, Test for Origin symmetry: replace x by -x and y by -y. (If the graph is both X and Y symmetric, it is also Origin symmetric.) For a function: if ƒ is not even, test if -f(x) = f(-x) then ƒ is symmetric about origin (if the function is even, can't also be Origin); it is an odd function.
Summary:
Function: if Y? then "Y" else if O? then "O" else "None" Equation (relation): if X? then if Y? then "XYO" else "X" else if Y? then "Y" else if O? then "O" else "None"
Example function symmetries, or not.
| f(x) | f(-x) | -f(x) [-y] | -f(-x) | type of symmetry |
--- ---
| = | = | | | Y-axis. EVEN function |
| | | = | = |
| | = | = | | Origin. ODD function |
| = | | | = |
|
| 2x | -2x | -2x | 2x | Origin, Odd. Linear thru origin. |
| 2x-2 | -2x-2 | -2x+2 | 2x+2 | Neither. Linear not thru origin. |
| 2x2-3 | 2x2-3 | -2x2+3 | -2x2+3 | Y-axis, Even. Quadratic, no bx term. |
| 2x2+2x-3 | 2x2-2x-3 | -2x2-2x+3 | -2x2+2x+3 | Neither. Quadratic, with bx term. |
| x3 | (-x)3 | -x3 | -(-x)3 | Origin, Odd. Cubic, no other terms. |
| ∛x | ∛-x | -∛x | -∛-x | Origin, Odd. |
| ex | e-x | -ex | -e-x | Neither. |
| 1/x | -1/x | -1/x | 1/x | Origin, Odd. |
| 1/x2 | 1/(-x)2 | -1/x2 | -1/(-x)2 | Y-axis, Even. |
| sin x | sin -x | -sin x | -sin -x | Origin, Odd. |
| cos x | cos -x | -cos x | -cos -x | Y-axis, Even. |
|
|
Another kind of symmetry: across the y=x main diagonal line.
| | |
--- |
| | (a,b) and (b,a). Interchange/swap the coordinates. The line connecting the points is perpendicular to the y=x line. It is y=-x+(a+b) The points are |a-b|/√2 from the y=x line. The points are √(a2+b2) from the origin. See inverse functions Self-inverse functions such as y=x, y=-x, y=1/x, y=-1/x, y=(x+1)/(x-1) have this symmetry. Graphs with this symmetry: Every (x,y) iff (y,x). Circles centered on the y=x line. Tilted parabolas whose axis is symmetry is y=x. Tilted ellipses with either axis on the y=x line. | |
12552 | https://www.doubtnut.com/qna/100314245 | Prove that ∣∣ ∣ ∣∣(a+b)2cabcca(b+c)2abbcab(c+a)2∣∣ ∣ ∣∣=2abc(a+b+c)3
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Similar Questions
Using properties of determinants, show the following:
∣∣
∣
∣∣(b+c)2abcaab(a+c)2bcacbc(a+b)2∣∣
∣
∣∣=2abc(a+b+c)3
. Prove that (a +b+ c) (ab+ bc + ca) > 9abc.
Prove that :∣∣
∣
∣∣b2c2bcb+cc2a2cac+aa2b2aba+b∣∣
∣
∣∣=0
Prove that: ∣∣
∣
∣∣bc−a2ca−b2ab−c2ca−b2ab−c2bc−a2ab−c2bc−a2ca−b2∣∣
∣
∣∣
is divisible by a+b+c
and find the quotient.
Prove that: ∣∣
∣
∣∣bc−a2ca−b2ab−c2ca−b2ab−c2bc−a2ab−c2bc−a2ca−b2∣∣
∣
∣∣
is divisible by a+b+c
and find the quotient.
Prove that: ∣∣
∣
∣∣bc−a2ca−b2ab−c2ca−b2ab−c2bc−a2ab−c2bc−a2ca−b2∣∣
∣
∣∣
is divisible by a+b+c
and find the quotient.
Prove that ∣∣
∣
∣∣1aa2−bc1bb2−ca1cc2−ab∣∣
∣
∣∣=0
Prove that : ∣∣
∣
∣∣abca2b2c2bccaab∣∣
∣
∣∣=(a−b)(b−c)(c−a)(ab+bc+ca)
If a,b,c
are in A.P., prove that:
i.(a−c)2=4(a−b)(b−c)
ii.a2+c2+4ac=2(ab+bc+ca)
iii.a3+c3+6abc=8b3
Prove that ∣∣
∣
∣∣111abca2−bcb2−cac2−ab∣∣
∣
∣∣=0
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12553 | https://math.stackexchange.com/questions/2820029/area-of-a-triangle-bounded-by-diagonal-of-a-square-and-a-second-intersecting-lin | euclidean geometry - Area of a triangle bounded by diagonal of a square and a second intersecting line - Mathematics Stack Exchange
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Area of a triangle bounded by diagonal of a square and a second intersecting line
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Given the following image, Determine the area of FEC given that the total area is 1 area unit. The correct answer should be 1/12 a.u. but I cannot get all the way to that conclusion. Note, one's not allowed to use sin or cos, which would make for an ugly solution any how..
The obvious parts here are that FEC and ABF are mirror images. Resulting in proportional lengths for each. Meaning:
FE/FB = FC/FA = EC/AB
Area of Δ = baseheight/2
The base being EC=AB/2, and the height being..?
I'm certain that I've missed some vital part of the puzzle. Any hint the the right direction would be much appreciated.
Best regards
euclidean-geometry
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asked Jun 14, 2018 at 21:37
RaoulRaoul
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Is E the mid-point of CD? Is ABCD a square or can it also be a rectangle? I think you are missing some information here.user625 –user625 2018-06-14 21:45:57 +00:00 Commented Jun 14, 2018 at 21:45
Yes, ED = AB/2, so half way. And ABCD is a square specifically. Though a general solution would be interesting too.Raoul –Raoul 2018-06-14 21:50:23 +00:00 Commented Jun 14, 2018 at 21:50
I added solution for square below. Same logic (and answer) applies to a rectangle also. Just assume the adjacent sides are l and w (instead of 1 each) and follow along.user625 –user625 2018-06-14 22:15:29 +00:00 Commented Jun 14, 2018 at 22:15
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I assume ABCD is a square and E is mid-point of CD. As you found out FEC and FBA are similar triangles. Now EC = AB/2, thus the height of FEC = half of height of FBA. Also, height of FEC + height of FBA = 1 = length of side of the square. Thus, height of FEC = 1/3. We already know EC = 1 2 1 2. So, area of FEC = 1 2 1 3 1 2 1 2 1 3 1 2 = 1 12 1 12
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answered Jun 14, 2018 at 22:10
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If we draw the line DF and then create four triangles, AFD, DFC, CFB, and BFA, and pair together the opposite triangles (AFD with BFC; CFA with DFC), we can easily realize that these pairs both compromise half of the total area of the square because each base is one and if you sum the heights they sum to one, meaning the combined area is 111/2 for each of these pairs. Now, using mass geometry and assuming each corner point has mass one, point E has mass 2, meaning the ratio of BF to FE is 1:2. Now note that AFB is similar to CFE due to AAA (because opposite sides of squares are parallel and then AC and BE are transversals). The ratio of similarity is then 1:2, so the ratio of areas between AFB and DFC is 1:4. Note that since EC = DE, that the area of EFC is 1/2 of the area of DFC.
Now, we know from the beginning that AFB + CFD is 1/2 and DFE has the same area as EFC, so this can be rewritten as AFB + 2EFC, and because the ratio of the areas EFC to AFB is 1:4, then EFC can be rewritten as 1/4AFB yielding AFB + 1/2AFB = 1/2. Simplifying this equation yields AFB = 1/3.
Now we're almost done, because AFB + 2EFC = 1/2 and AFB = 1/3, then 2EFC = 1/6 so finally EFC = 1/12
This may not be the most time-efficient solution however as far as I'm aware it's fully rigorous
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answered Jun 14, 2018 at 22:15
MichaelMichael
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12554 | http://203.201.63.46:8080/jspui/bitstream/123456789/5541/9/Microelectronic%20Circuits%20by%20Sedra%20and%20Smith%206th%20Edition.pdf | CHAPTER 1 Signals and Amplifiers 4 CHAPTER 2 Operational Amplifiers 52 CHAPTER 3 Semiconductors 124 CHAPTER 4 Diodes 164 CHAPTER 5 MOS Field-Effect Transistors (MOSFETs) 230 CHAPTER 6 Bipolar Junction Transistors (BJTs) 350 PART I Devices and Basic Circuits 3 art I, Devices and Basic Circuits, includes the most fundamental and essential topics for the study of electronic circuits. At the same time, it constitutes a complete pack-age for a first course on the subject.
The heart of Part I is the study of the three basic semiconductor devices: the diode (Chapter 4); the MOS transistor (Chapter 5); and the bipolar transistor (Chapter 6). In each case, we study the device operation, its characterization, and its basic circuit applications.
For those who have not had a prior course on device physics, Chapter 3 provides an over-view of semiconductor concepts at a level sufficient for the study of electronic circuits. A review of Chapter 3 should prove useful even for those with prior knowledge of semi-conductors.
Since the purpose of electronic circuits is the processing of signals, an understanding is essential of signals, their characterization in the time and frequency domains, and their analog and digital representations. This is provided in Chapter 1, which also introduces the most common signal-processing function, amplification, and the characterization and types of amplifiers.
Besides diodes and transistors, the basic electronic devices, the op amp is studied in Part I. Although not an electronic device in the most fundamental sense, the op amp is commercially available as an integrated circuit (IC) package and has well-defined termi-nal characteristics. Thus, despite the fact that the op amp’s internal circuit is complex, typ-ically incorporating 20 or more transistors, its almost-ideal terminal behavior makes it possible to treat the op amp as a circuit element and to use it in the design of powerful circuits, as we do in Chapter 2, without any knowledge of its internal construction. We should mention, however, that the study of op amps can be delayed to a later point, and Chapter 2 can be skipped with no loss of continuity.
The foundation of this book, and of any electronics course, is the study of the two transistor types in use today: the MOS transistor in Chapter 5 and the bipolar transistor in Chapter 6. These two chapters have been written to be completely independent of one another and thus can be studied in either order as desired. Furthermore, the two chap-ters have the same structure, making it easier and faster to study the second device, as well as to draw comparisons between the two device types.
After the study of Part I, the reader will be fully prepared to undertake the study of either integrated-circuit amplifiers in Part II or digital integrated circuits in Part III.
P CHAPTER 1 Signals and Amplifiers Introduction 5 1.1 Signals 6 1.2 Frequency Spectrum of Signals 9 1.3 Analog and Digital Signals 11 1.4 Amplifiers 14 1.5 Circuit Models for Amplifiers 21 1.6 Frequency Response of Amplifiers 30 Summary 41 Problems 42 5 IN THIS CHAPTER YOU WILL LEARN 1. That electronic circuits process signals, and thus understanding electri-cal signals is essential to appreciating the material in this book.
2. The Thévenin and Norton representations of signal sources.
3. The representation of a signal as the sum of sine waves.
4. The analog and digital representations of a signal.
5. The most basic and pervasive signal-processing function: signal amplifi-cation, and correspondingly, the signal amplifier.
6. How amplifiers are characterized (modeled) as circuit building blocks independent of their internal circuitry.
7. How the frequency response of an amplifier is measured, and how it is calculated, especially in the simple but common case of a single-time-constant (STC) type response.
Introduction The subject of this book is modern electronics, a field that has come to be known as micro-electronics. Microelectronics refers to the integrated-circuit (IC) technology that at the time of this writing is capable of producing circuits that contain hundreds of millions of components in a small piece of silicon (known as a silicon chip) whose area is on the order of 100 mm2. One such microelectronic circuit, for example, is a complete digital computer, which accordingly is known as a microcomputer or, more generally, a microprocessor.
In this book we shall study electronic devices that can be used singly (in the design of dis-crete circuits) or as components of an integrated-circuit (IC) chip. We shall study the design and analysis of interconnections of these devices, which form discrete and integrated circuits of varying complexity and perform a wide variety of functions. We shall also learn about available IC chips and their application in the design of electronic systems.
The purpose of this first chapter is to introduce some basic concepts and terminology. In particular, we shall learn about signals and about one of the most important signal-processing functions electronic circuits are designed to perform, namely, signal amplification. We shall then look at circuit representations or models for linear amplifiers. These models will be employed in subsequent chapters in the design and analysis of actual amplifier circuits.
6 Chapter 1 Signals and Amplifiers In addition to motivating the study of electronics, this chapter serves as a bridge between the study of linear circuits and that of the subject of this book: the design and analysis of electronic circuits.
1.1 Signals Signals contain information about a variety of things and activities in our physical world.
Examples abound: Information about the weather is contained in signals that represent the air temperature, pressure, wind speed, etc. The voice of a radio announcer reading the news into a microphone provides an acoustic signal that contains information about world affairs.
To monitor the status of a nuclear reactor, instruments are used to measure a multitude of relevant parameters, each instrument producing a signal.
To extract required information from a set of signals, the observer (be it a human or a machine) invariably needs to process the signals in some predetermined manner. This signal processing is usually most conveniently performed by electronic systems. For this to be possi-ble, however, the signal must first be converted into an electrical signal, that is, a voltage or a current. This process is accomplished by devices known as transducers. A variety of trans-ducers exist, each suitable for one of the various forms of physical signals. For instance, the sound waves generated by a human can be converted into electrical signals by using a micro-phone, which is in effect a pressure transducer. It is not our purpose here to study transducers; rather, we shall assume that the signals of interest already exist in the electrical domain and represent them by one of the two equivalent forms shown in Fig. 1.1. In Fig. 1.1(a) the signal is represented by a voltage source vs(t) having a source resistance Rs. In the alternate representa-tion of Fig. 1.1(b) the signal is represented by a current source is(t) having a source resistance Rs. Although the two representations are equivalent, that in Fig. 1.1(a) (known as the Thévenin form) is preferred when Rs is low. The representation of Fig. 1.1(b) (known as the Norton form) is preferred when Rs is high. The reader will come to appreciate this point later in this chapter when we study the different types of amplifiers. For the time being, it is important to be familiar with Thévenin’s and Norton’s theorems (for a brief review, see Appendix D) and to note that for the two representations in Fig. 1.1 to be equivalent, their parameters are related by vs t ( ) Rsis t ( ) = Example 1.1 The output resistance of a signal source, although inevitable, is an imperfection that limits the ability of the source to deliver its full signal strength to a load. To see this point more clearly, consider the signal source when connected to a load resistance RL as shown in Fig. 1.2. For the case in which the source is represented (b) Rs is(t) Figure 1.1 Two alternative representations of a signal source: (a) the Thévenin form; (b) the Norton form.
vs(t) Rs (a) 1.1 Signals 7 by its Thévenin equivalent form, find the voltage vo that appears across RL, and hence the condition that Rs must satisfy for vo to be close to the value of vs. Repeat for the Norton-represented source; in this case finding the current io that flows through RL and hence the condition that Rs must satisfy for io to be close to the value of is.
Solution For the Thévenin-represented signal source shown in Fig. 1.2(a), the output voltage vo that appears across the load resistance RL can be found from the ratio of the voltage divider formed by Rs and RL, From this equation we see that for the source resistance Rs must be much lower than the load resistance RL, Thus, for a source represented by its Thévenin equivalent, ideally Rs = 0, and as Rs is increased, relative to the load resistance RL with which this source is intended to operate, the voltage vo that appears across the load becomes smaller, not a desirable outcome.
Next, we consider the Norton-represented signal source in Fig. 1.2(b). To obtain the current io that flows through the load resistance RL, we utilize the ratio of the current divider formed by Rs and RL, From this relationship we see that for the source resistance Rs must be much larger that RL, Thus for a signal source represented by its Norton equivalent, ideally Rs = ∞, and as Rs is reduced, relative to the load resistance RL with which this source is intended to operate, the current io that flows through the load becomes smaller, not a desirable outcome.
Finally, we note that although circuit designers cannot usually do much about the value of Rs; they may have to devise a circuit solution that minimizes or eliminates the loss of signal strength that results when the source is connected to the load.
vs vo Rs RL (a) (b) Rs RL is io Figure 1.2 Circuits for Example 1.1.
vo vs RL RL Rs + ------------------= vo vs Rs RL io is Rs Rs RL + ------------------= io is Rs RL 8 Chapter 1 Signals and Amplifiers From the discussion above, it should be apparent that a signal is a time-varying quantity that can be represented by a graph such as that shown in Fig. 1.3. In fact, the information content of the signal is represented by the changes in its magnitude as time progresses; that is, the information is contained in the “wiggles” in the signal waveform. In general, such waveforms are difficult to characterize mathematically. In other words, it is not easy to describe succinctly an arbitrary-looking waveform such as that of Fig. 1.3. Of course, such a description is of great importance for the purpose of designing appropriate signal-processing circuits that perform desired functions on the given signal. An effective approach to signal characterization is studied in the next section.
Figure 1.3 An arbitrary voltage signal vs(t).
1.1 For the signal-source representations shown in Figs. 1.1(a) and 1.1(b), what are the open-circuit output voltages that would be observed? If, for each, the output terminals are short-circuited (i.e., wired together), what current would flow? For the representations to be equivalent, what must the re-lationship be between vs, is, and Rs?
Ans. For (a), voc = vs(t); for (b), voc = Rsis(t); for (a), for (b), isc = is(t); for equivalency, vs(t) = Rsis(t) 1.2 A signal source has an open-circuit voltage of 10 mV and a short-circuit current of 10 μA. What is the source resistance?
Ans. 1 kΩ 1.3 A signal source that is most conveniently represented by its Thévenin equivalent has vs = 10 mV and Rs = 1 kΩ. If the source feeds a load resistance RL, find the voltage vo that appears across the load for RL = 100 kΩ, 10 kΩ, 1 kΩ, and 100 Ω. Also, find the lowest permissible value of RL for which the output voltage is at least 80% of the source voltage.
Ans. 9.9 mV; 9.1 mV; 5 mV; 0.9 mV; 4 kΩ 1.4 A signal source that is most conveniently represented by its Norton equivalent form has is = 10 μA and Rs = 100 kΩ. If the source feeds a load resistance RL, find the current io that flows through the load for RL = 1 kΩ, 10 kΩ, 100 kΩ, and 1 MΩ. Also, find the largest permissible value of RL for which the load current is at least 80% of the source current.
Ans. 9.9 μA; 9.1 μA; 5 μA; 0.9 μA; 25 kΩ isc vs t ( ) Rs ⁄ ; = EXERCISES 1.2 Frequency Spectrum of Signals 9 1.2 Frequency Spectrum of Signals An extremely useful characterization of a signal, and for that matter of any arbitrary function of time, is in terms of its frequency spectrum. Such a description of signals is obtained through the mathematical tools of Fourier series and Fourier transform.1 We are not inter-ested here in the details of these transformations; suffice it to say that they provide the means for representing a voltage signal vs(t) or a current signal is(t) as the sum of sine-wave signals of different frequencies and amplitudes. This makes the sine wave a very important signal in the analysis, design, and testing of electronic circuits. Therefore, we shall briefly review the properties of the sinusoid.
Figure 1.4 shows a sine-wave voltage signal va(t), (1.1) where Va denotes the peak value or amplitude in volts and ω denotes the angular frequency in radians per second; that is, rad/s, where f is the frequency in hertz, f = 1/T Hz, and T is the period in seconds.
The sine-wave signal is completely characterized by its peak value Va, its frequency ω, and its phase with respect to an arbitrary reference time. In the case depicted in Fig. 1.4, the time origin has been chosen so that the phase angle is 0. It should be mentioned that it is com-mon to express the amplitude of a sine-wave signal in terms of its root-mean-square (rms) value, which is equal to the peak value divided by Thus the rms value of the sinusoid va(t) of Fig. 1.4 is For instance, when we speak of the wall power supply in our homes as being 120 V, we mean that it has a sine waveform of volts peak value. Returning now to the representation of signals as the sum of sinusoids, we note that the Fou-rier series is utilized to accomplish this task for the special case of a signal that is a periodic func-tion of time. On the other hand, the Fourier transform is more general and can be used to obtain the frequency spectrum of a signal whose waveform is an arbitrary function of time.
The Fourier series allows us to express a given periodic function of time as the sum of an infinite number of sinusoids whose frequencies are harmonically related. For instance, the symmetrical square-wave signal in Fig. 1.5 can be expressed as (1.2) 1The reader who has not yet studied these topics should not be alarmed. No detailed application of this material will be made until Chapter 9. Nevertheless, a general understanding of Section 1.2 should be very helpful in studying early parts of this book.
va t ( ) Va ωt sin = ω 2πf = 2.
Va 2 ⁄ .
120 2 v t ( ) 4V π -------( ω0t 1 3 --3ω0t 1 5 --5ω0t . . .) + sin + sin + sin = Figure 1.4 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency rad/s.
ω 2πf = 10 Chapter 1 Signals and Amplifiers where V is the amplitude of the square wave and (T is the period of the square wave) is called the fundamental frequency. Note that because the amplitudes of the harmonics progressively decrease, the infinite series can be truncated, with the truncated series providing an approximation to the square waveform.
The sinusoidal components in the series of Eq. (1.2) constitute the frequency spectrum of the square-wave signal. Such a spectrum can be graphically represented as in Fig. 1.6, where the horizontal axis represents the angular frequency ω in radians per second. The Fourier transform can be applied to a nonperiodic function of time, such as that depicted in Fig. 1.3, and provides its frequency spectrum as a continuous function of fre-quency, as indicated in Fig. 1.7. Unlike the case of periodic signals, where the spectrum con-sists of discrete frequencies (at ω0 and its harmonics), the spectrum of a nonperiodic signal contains in general all possible frequencies. Nevertheless, the essential parts of the spectra of practical signals are usually confined to relatively short segments of the frequency (ω) axis—an observation that is very useful in the processing of such signals. For instance, the spectrum of audible sounds such as speech and music extends from about 20 Hz to about 20 kHz—a frequency range known as the audio band. Here we should note that although some musical tones have frequencies above 20 kHz, the human ear is incapable of hearing frequencies that are much above 20 kHz. As another example, analog video signals have their spectra in the range of 0 MHz to 4.5 MHz. Figure 1.5 A symmetrical square-wave signal of amplitude V.
Figure 1.6 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.5.
ω0 = 2π T ⁄ 1.3 Analog and Digital Signals 11 We conclude this section by noting that a signal can be represented either by the manner in which its waveform varies with time, as for the voltage signal va(t) shown in Fig. 1.3, or in terms of its frequency spectrum, as in Fig. 1.7. The two alternative representations are known as the time-domain representation and the frequency-domain representation, respectively. The frequency-domain representation of va(t) will be denoted by the symbol Va(ω). 1.3 Analog and Digital Signals The voltage signal depicted in Fig. 1.3 is called an analog signal. The name derives from the fact that such a signal is analogous to the physical signal that it represents. The magni-tude of an analog signal can take on any value; that is, the amplitude of an analog signal exhibits a continuous variation over its range of activity. The vast majority of signals in the Figure 1.7 The frequency spectrum of an arbitrary waveform such as that in Fig.
1.3.
1.5 Find the frequencies f and ω of a sine-wave signal with a period of 1 ms.
Ans.
1.6 What is the period T of sine waveforms characterized by frequencies of (a) f = 60 Hz? (b) f = 10−3 Hz?
(c) f = 1 MHz? Ans. 16.7 ms; 1000 s; 1 μs 1.7 The UHF (ultra high frequency) television broadcast band begins with channel 14 and extends from 470 MHz to 806 MHz. If 6 MHz is allocated for each channel, how many channels can this band accommodate?
Ans. 56; channels 14 to 69 1.8 When the square-wave signal of Fig. 1.5, whose Fourier series is given in Eq. (1.2), is applied to a resis-tor, the total power dissipated may be calculated directly using the relationship or indirectly by summing the contribution of each of the harmonic components, that is, P = P1 + P3 + P5 + …, which may be found directly from rms values. Verify that the two approaches are equivalent.
What fraction of the energy of a square wave is in its fundamental? In its first five harmonics? In its first seven? First nine? In what number of harmonics is 90% of the energy? (Note that in counting harmonics, the fundamental at ω0 is the first, the one at 2ω0 is the second, etc.) Ans. 0.81; 0.93; 0.95; 0.96; 3 f = 1000 Hz; ω 2π 103 rad/s × = P 1 T ∫T 0 ⁄ v2 R ⁄ ( ) dt = EXERCISES 12 Chapter 1 Signals and Amplifiers world around us are analog. Electronic circuits that process such signals are known as ana-log circuits. A variety of analog circuits will be studied in this book.
An alternative form of signal representation is that of a sequence of numbers, each num-ber representing the signal magnitude at an instant of time. The resulting signal is called a digital signal. To see how a signal can be represented in this form—that is, how signals can be converted from analog to digital form—consider Fig. 1.8(a). Here the curve represents a voltage signal, identical to that in Fig. 1.3. At equal intervals along the time axis, we have marked the time instants t0, t1, t2, and so on. At each of these time instants, the magnitude of the signal is measured, a process known as sampling. Figure 1.8(b) shows a representation of the signal of Fig. 1.8(a) in terms of its samples. The signal of Fig. 1.8(b) is defined only at the sampling instants; it no longer is a continuous function of time; rather, it is a discrete-time signal. However, since the magnitude of each sample can take any value in a continuous range, the signal in Fig. 1.8(b) is still an analog signal.
Now if we represent the magnitude of each of the signal samples in Fig. 1.8(b) by a number having a finite number of digits, then the signal amplitude will no longer be continuous; rather, it is said to be quantized, discretized, or digitized. The resulting digital signal then is simply a sequence of numbers that represent the magnitudes of the successive signal samples.
The choice of number system to represent the signal samples affects the type of digital signal produced, and has a profound effect on the complexity of the digital circuits required to process the signals. It turns out that the binary number system results in the simplest pos-sible digital signals and circuits. In a binary system, each digit in the number takes on one of Figure 1.8 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).
(a) 1.3 Analog and Digital Signals 13 only two possible values, denoted 0 and 1. Correspondingly, the digital signals in binary sys-tems need have only two voltage levels, which can be labeled low and high. As an example, in some of the digital circuits studied in this book, the levels are 0 V and +5 V. Figure 1.9 shows the time variation of such a digital signal. Observe that the waveform is a pulse train with 0 V representing a 0 signal, or logic 0, and +5 V representing logic 1.
If we use N binary digits (bits) to represent each sample of the analog signal, then the dig-itized sample value can be expressed as (1.3) where b0, b1, …, bN–1, denote the N bits and have values of 0 or 1. Here bit b0 is the least significant bit (LSB), and bit bN–1 is the most significant bit (MSB). Conventionally, this binary number is written as bN–1 bN–2 … b0. We observe that such a representation quantizes the analog sample into one of 2N levels. Obviously the greater the number of bits (i.e., the larger the N), the closer the digital word D approximates the magnitude of the analog sample. That is, increasing the number of bits reduces the quantization error and increases the resolution of the analog-to-digital conversion. This improvement is, however, usually obtained at the expense of more com-plex and hence more costly circuit implementations. It is not our purpose here to delve into this topic any deeper; we merely want the reader to appreciate the nature of analog and digital signals.
Nevertheless, it is an opportune time to introduce a very important circuit building block of mod-ern electronic systems: the analog-to-digital converter (A/D or ADC) shown in block form in Fig. 1.10 The ADC accepts at its input the samples of an analog signal and provides for each input sample the corresponding N-bit digital representation (according to Eq. 1.3) at its N output terminals. Thus although the voltage at the input might be, say, 6.51 V, at each of the output ter-minals (say, at the ith terminal), the voltage will be either low (0 V) or high (5 V) if bi is supposed Figure 1.9 Variation of a particular binary digital signal with time.
Figure 1.10 Block-diagram representation of the analog-to-digital converter (ADC).
5 0 1 1 1 1 0 0 0 0 v (t) Time, Logic values t D b02 0 b12 1 b22 2 … + + + + bN−12 N−1 = Analog input A/D converter Digital output b0 b1 bN1 vA 14 Chapter 1 Signals and Amplifiers to be 0 or 1, respectively. The dual circuit of the ADC is the digital-to-analog converter (D/A or DAC). It converts an N-bit digital input to an analog output voltage.
Once the signal is in digital form, it can be processed using digital circuits. Of course digital circuits can deal also with signals that do not have an analog origin, such as the sig-nals that represent the various instructions of a digital computer.
Since digital circuits deal exclusively with binary signals, their design is simpler than that of analog circuits. Furthermore, digital systems can be designed using a relatively few different kinds of digital circuit blocks. However, a large number (e.g., hundreds of thousands or even mil-lions) of each of these blocks are usually needed. Thus the design of digital circuits poses its own set of challenges to the designer but provides reliable and economic implementations of a great variety of signal-processing functions, many of which are not possible with analog circuits. At the present time, more and more of the signal-processing functions are being performed digitally.
Examples around us abound: from the digital watch and the calculator to digital audio systems, digital cameras and, more recently, digital television. Moreover, some longstanding analog sys-tems such as the telephone communication system are now almost entirely digital. And we should not forget the most important of all digital systems, the digital computer.
The basic building blocks of digital systems are logic circuits and memory circuits. We shall study both in this book, beginning in Chapter 13.
One final remark: Although the digital processing of signals is at present all-pervasive, there remain many signal-processing functions that are best performed by analog circuits.
Indeed, many electronic systems include both analog and digital parts. It follows that a good electronics engineer must be proficient in the design of both analog and digital circuits, or mixed-signal or mixed-mode design as it is currently known. Such is the aim of this book.
1.4 Amplifiers In this section, we shall introduce the most fundamental signal-processing function, one that is employed in some form in almost every electronic system, namely, signal amplification.
We shall study the amplifier as a circuit building-block; that is, we shall consider its external characteristics and leave the design of its internal circuit to later chapters.
1.4.1 Signal Amplification From a conceptual point of view the simplest signal-processing task is that of signal amplifica-tion. The need for amplification arises because transducers provide signals that are said to be “weak,” that is, in the microvolt (μV) or millivolt (mV) range and possessing little energy. Such 1.9 Consider a 4-bit digital word D = b3b2b1b0 (see Eq. 1.3) used to represent an analog signal vA that varies between 0 V and +15 V.
(a) Give D corresponding to vA = 0 V, 1 V, 2 V, and 15 V.
(b) What change in vA causes a change from 0 to 1 in (i) b0, (ii) b1, (iii) b2, and (iv) b3?
(c) If vA = 5.2 V, what do you expect D to be? What is the resulting error in representation?
Ans. (a) 0000, 0001, 0010, 1111; (b) +1 V, +2 V, +4 V, +8 V; (c) 0101, –4% EXERCISE 1.4 Amplifiers 15 signals are too small for reliable processing, and processing is much easier if the signal magni-tude is made larger. The functional block that accomplishes this task is the signal amplifier.
It is appropriate at this point to discuss the need for linearity in amplifiers. Care must be exercised in the amplification of a signal, so that the information contained in the signal is not changed and no new information is introduced. Thus when we feed the signal shown in Fig.
1.3 to an amplifier, we want the output signal of the amplifier to be an exact replica of that at the input, except of course for having larger magnitude. In other words, the “wiggles” in the output waveform must be identical to those in the input waveform. Any change in waveform is considered to be distortion and is obviously undesirable. An amplifier that preserves the details of the signal waveform is characterized by the rela-tionship (1.4) where vi and vo are the input and output signals, respectively, and A is a constant representing the magnitude of amplification, known as amplifier gain. Equation (1.4) is a linear relation-ship; hence the amplifier it describes is a linear amplifier. It should be easy to see that if the relationship between vo and vi contains higher powers of vi, then the waveform of vo will no longer be identical to that of vi. The amplifier is then said to exhibit nonlinear distortion.
The amplifiers discussed so far are primarily intended to operate on very small input signals.
Their purpose is to make the signal magnitude larger and therefore are thought of as voltage amplifiers. The preamplifier in the home stereo system is an example of a voltage amplifier.
At this time we wish to mention another type of amplifier, namely, the power amplifier.
Such an amplifier may provide only a modest amount of voltage gain but substantial current gain. Thus while absorbing little power from the input signal source to which it is connected, often a preamplifier, it delivers large amounts of power to its load. An example is found in the power amplifier of the home stereo system, whose purpose is to provide sufficient power to drive the loudspeaker, which is the amplifier load. Here we should note that the loudspeaker is the output transducer of the stereo system; it converts the electric output signal of the system into an acoustic signal. A further appreciation of the need for linearity can be acquired by reflecting on the power amplifier. A linear power amplifier causes both soft and loud music passages to be reproduced without distortion.
1.4.2 Amplifier Circuit Symbol The signal amplifier is obviously a two-port network. Its function is conveniently represented by the circuit symbol of Fig. 1.11(a). This symbol clearly distinguishes the input and output ports and indicates the direction of signal flow. Thus, in subsequent diagrams it will not be necessary to label the two ports “input” and “output.” For generality we have shown the amplifier to have two input terminals that are distinct from the two output terminals. A more common situation is illustrated in Fig. 1.11(b), where a common terminal exists between the input and output ports of the amplifier. This common terminal is used as a reference point and is called the circuit ground.
1.4.3 Voltage Gain A linear amplifier accepts an input signal vI(t) and provides at the output, across a load resis-tance RL (see Fig. 1.12(a)), an output signal vO(t) that is a magnified replica of vI(t). The voltage gain of the amplifier is defined by (1.5) vo t ( ) Avi t ( ) = Voltage gain Av ( ) ≡ vO vI -----16 Chapter 1 Signals and Amplifiers Fig. 1.12(b) shows the transfer characteristic of a linear amplifier. If we apply to the input of this amplifier a sinusoidal voltage of amplitude we obtain at the output a sinusoid of amplitude 1.4.4 Power Gain and Current Gain An amplifier increases the signal power, an important feature that distinguishes an amplifier from a transformer. In the case of a transformer, although the voltage delivered to the load could be greater than the voltage feeding the input side (the primary), the power delivered to the load (from the secondary side of the transformer) is less than or at most equal to the power supplied by the signal source. On the other hand, an amplifier provides the load with power greater than that obtained from the signal source. That is, amplifiers have power gain. The power gain of the amplifier in Fig. 1.12(a) is defined as (1.6) (1.7) Figure 1.11 (a) Circuit symbol for amplifier. (b) An amplifier with a common terminal (ground) between the input and output ports.
Figure 1.12 (a) A voltage amplifier fed with a signal vI (t) and connected to a load resistance RL. (b) Transfer characteristic of a linear voltage amplifier with voltage gain Av.
(a) V ˆ, AvV ˆ.
Power gain Ap ( ) ≡ load power PL ( ) input power PI ( ) -----------------------------------------= vOiO vIiI ----------(a) 1.4 Amplifiers 17 where iO is the current that the amplifier delivers to the load (RL), iO = vO/RL, and iI is the cur-rent the amplifier draws from the signal source. The current gain of the amplifier is defined as (1.8) From Eqs. (1.5) to (1.8) we note that (1.9) 1.4.5 Expressing Gain in Decibels The amplifier gains defined above are ratios of similarly dimensioned quantities. Thus they will be expressed either as dimensionless numbers or, for emphasis, as V/V for the voltage gain, A/A for the current gain, and W/W for the power gain. Alternatively, for a number of reasons, some of them historic, electronics engineers express amplifier gain with a logarith-mic measure. Specifically the voltage gain Av can be expressed as and the current gain Ai can be expressed as Since power is related to voltage (or current) squared, the power gain Ap can be expressed in decibels as The absolute values of the voltage and current gains are used because in some cases Av or Ai will be a negative number. A negative gain Av simply means that there is a 180° phase dif-ference between input and output signals; it does not imply that the amplifier is attenuating the signal. On the other hand, an amplifier whose voltage gain is, say, –20 dB is in fact atten-uating the input signal by a factor of 10 (i.e., Av = 0.1 V/V).
1.4.6 The Amplifier Power Supplies Since the power delivered to the load is greater than the power drawn from the signal source, the question arises as to the source of this additional power. The answer is found by observ-ing that amplifiers need dc power supplies for their operation. These dc sources supply the extra power delivered to the load as well as any power that might be dissipated in the inter-nal circuit of the amplifier (such power is converted to heat). In Fig. 1.12(a) we have not explicitly shown these dc sources.
Figure 1.13(a) shows an amplifier that requires two dc sources: one positive of value VCC and one negative of value VEE. The amplifier has two terminals, labeled V + and V –, for connec-tion to the dc supplies. For the amplifier to operate, the terminal labeled V + has to be con-nected to the positive side of a dc source whose voltage is VCC and whose negative side is connected to the circuit ground. Also, the terminal labeled V – has to be connected to the nega-tive side of a dc source whose voltage is VEE and whose positive side is connected to the circuit ground. Now, if the current drawn from the positive supply is denoted ICC and that from the negative supply is IEE (see Fig. 1.13a), then the dc power delivered to the amplifier is Current gain Ai ( ) ≡ iO iI ----Ap Av Ai = Voltage gain in decibels 20 log A v = dB Current gain in decibels 20 log Ai = dB Power gain in decibels 10 log Ap = dB 18 Chapter 1 Signals and Amplifiers If the power dissipated in the amplifier circuit is denoted Pdissipated, the power-balance equa-tion for the amplifier can be written as where PI is the power drawn from the signal source and PL is the power delivered to the load.
Since the power drawn from the signal source is usually small, the amplifier power effi-ciency is defined as (1.10) The power efficiency is an important performance parameter for amplifiers that handle large amounts of power. Such amplifiers, called power amplifiers, are used, for example, as out-put amplifiers of stereo systems.
In order to simplify circuit diagrams, we shall adopt the convention illustrated in Fig.1.13(b).
Here the V + terminal is shown connected to an arrowhead pointing upward and the V – terminal to an arrowhead pointing downward. The corresponding voltage is indicated next to each arrow-head. Note that in many cases we will not explicitly show the connections of the amplifier to the dc power sources. Finally, we note that some amplifiers require only one power supply.
Figure 1.13 An amplifier that requires two dc supplies (shown as batteries) for operation.
Pdc VCCICC VEEIEE + = Pdc PI + PL Pdissipated + = η ≡ PL Pdc -------100 × (a) VCC VEE IEE ICC (b) ICC IEE VCC VEE Example 1.2 Consider an amplifier operating from ±10-V power supplies. It is fed with a sinusoidal voltage having 1 V peak and delivers a sinusoidal voltage output of 9 V peak to a 1-kΩ load. The amplifier draws a current of 9.5 mA from each of its two power supplies. The input current of the amplifier is found to be sinusoidal with 0.1 mA peak. Find the voltage gain, the current gain, the power gain, the power drawn from the dc supplies, the power dissipated in the amplifier, and the amplifier efficiency.
Solution Av 9 1 ---9 V/V = = 1.4 Amplifiers 19 From the above example we observe that the amplifier converts some of the dc power it draws from the power supplies to signal power that it delivers to the load.
1.4.7 Amplifier Saturation Practically speaking, the amplifier transfer characteristic remains linear over only a limited range of input and output voltages. For an amplifier operated from two power supplies the out-put voltage cannot exceed a specified positive limit and cannot decrease below a specified neg-ative limit. The resulting transfer characteristic is shown in Fig. 1.14, with the positive and negative saturation levels denoted L+ and L–, respectively. Each of the two saturation levels is usually within a fraction of a volt of the voltage of the corresponding power supply.
Obviously, in order to avoid distorting the output signal waveform, the input signal swing must be kept within the linear range of operation, In Fig. 1.14, which shows two input waveforms and the corresponding output waveforms, the peaks of the larger waveform have been clipped off because of amplifier saturation.
L− Av ----- vI L+ Av -----≤ ≤ or or or Av 20 log 9 19.1 dB = = Io ˆ 9 V 1 kΩ ------------9 mA = = Ai Io ˆ Ii ˆ ----9 0.1 -------90 A/A = = = Ai 20 log 90 39.1 dB = = PL VormsIorms 9 2 ------- 9 2 -------40.5 mW = = = PI VirmsIirms 1 2 -------0.1 2 -------0.05 mW = = = Ap PL PI ------40.5 0.05 ----------810 W/W = = = Ap 10 log 810 29.1 dB = = Pdc 10 9.5 × 10 + 9.5 × 190 mW = = Pdissipated Pdc PI PL – + = = 190 0.05 40.5 – + 149.6 mW = η PL Pdc -------= 100 × 21.3% = 20 Chapter 1 Signals and Amplifiers 1.4.8 Symbol Convention At this point, we draw the reader’s attention to the terminology we shall employ throughout the book. To illustrate the terminology, Fig. 1.15 shows the waveform of a current iC(t) that is flowing through a branch in a particular circuit. The current iC(t) consists of a dc compo-nent IC on which is superimposed a sinusoidal component ic(t) whose peak amplitude is Ic.
Observe that at a time t, the total instantaneous current iC(t) is the sum of the dc current IC and the signal current , (1.11) where the signal current is given by Thus, we state some conventions: Total instantaneous quantities are denoted by a lowercase symbol with uppercase subscript(s), for example, iC(t), vDS(t). Direct-current (dc) quantities are denoted by an uppercase symbol with uppercase subscript(s), for example IC, VDS. Incremental Figure 1.14 An amplifier transfer characteristic that is linear except for output saturation.
ic t ( ) iC t ( ) IC ic t ( ) + = ic t ( ) Ic ωt sin = 1.5 Circuit Models for Amplifiers 21 signal quantities are denoted by a lowercase symbol with lowercase subscript(s), for example, ic(t), vgs(t). If the signal is a sine wave, then its amplitude is denoted by an uppercase symbol with lowercase subscript(s), for example Ic, Vgs. Finally, although not shown in Fig. 1.15, dc power supplies are denoted by an uppercase letter with a double-letter uppercase subscript, for example, VCC, VDD. A similar notation is used for the dc current drawn from the power supply, for example, ICC, IDD. 1.5 Circuit Models for Amplifiers A substantial part of this book is concerned with the design of amplifier circuits that use transis-tors of various types. Such circuits will vary in complexity from those using a single transistor to those with 20 or more devices. In order to be able to apply the resulting amplifier circuit as a building block in a system, one must be able to characterize, or model, its terminal behavior. In this section, we study simple but effective amplifier models. These models apply irrespective of the complexity of the internal circuit of the amplifier. The values of the model parameters can be found either by analyzing the amplifier circuit or by performing measurements at the amplifier terminals.
Figure 1.15 Symbol convention employed throughout the book.
0 t iC iC IC ic Ic 1.10 An amplifier has a voltage gain of 100 V/V and a current gain of 1000 A/A. Express the voltage and current gains in decibels and find the power gain.
Ans. 40 dB; 60 dB; 50 dB 1.11 An amplifier operating from a single 15-V supply provides a 12-V peak-to-peak sine-wave signal to a 1-kΩ load and draws negligible input current from the signal source. The dc current drawn from the 15-V supply is 8 mA. What is the power dissipated in the amplifier, and what is the amplifier efficiency?
Ans. 102 mW; 15% EXERCISES 22 Chapter 1 Signals and Amplifiers 1.5.1 Voltage Amplifiers Figure 1.16(a) shows a circuit model for the voltage amplifier. The model consists of a volt-age-controlled voltage source having a gain factor , an input resistance Ri that accounts for the fact that the amplifier draws an input current from the signal source, and an output resistance Ro that accounts for the change in output voltage as the amplifier is called upon to supply output current to a load. To be specific, we show in Fig. 1.16(b) the amplifier model fed with a signal voltage source vs having a resistance Rs and connected at the output to a load resistance RL. The nonzero output resistance Ro causes only a fraction of to appear across the output. Using the voltage-divider rule we obtain Thus the voltage gain is given by (1.12) It follows that in order not to lose gain in coupling the amplifier output to a load, the out-put resistance Ro should be much smaller than the load resistance RL. In other words, for a given RL one must design the amplifier so that its Ro is much smaller than RL. Further-more, there are applications in which RL is known to vary over a certain range. In order to keep the output voltage vo as constant as possible, the amplifier is designed with Ro much smaller than the lowest value of RL. An ideal voltage amplifier is one with Ro = 0. Equa-tion (1.12) indicates also that for RL = ∞, . Thus is the voltage gain of the unloaded amplifier, or the open-circuit voltage gain. It should also be clear that in spec-ifying the voltage gain of an amplifier, one must also specify the value of load resistance Figure 1.16 (a) Circuit model for the voltage amplifier. (b) The voltage amplifier with input signal source and load.
Avo Avovi vo Avovi = RL RL Ro + ------------------Av vo vi ----≡ Avo = RL RL Ro + ------------------Av Avo = Avo (a) vo 1 2 vs (b) vo ii io 1.5 Circuit Models for Amplifiers 23 at which this gain is measured or calculated. If a load resistance is not specified, it is nor-mally assumed that the given voltage gain is the open-circuit gain The finite input resistance Ri introduces another voltage-divider action at the input, with the result that only a fraction of the source signal vs actually reaches the input terminals of the amplifier; that is, (1.13) It follows that in order not to lose a significant portion of the input signal in coupling the signal source to the amplifier input, the amplifier must be designed to have an input resis-tance Ri much greater than the resistance of the signal source, Furthermore, there are applications in which the source resistance is known to vary over a certain range. To minimize the effect of this variation on the value of the signal that appears at the input of the amplifier, the design ensures that Ri is much greater than the largest value of Rs. An ideal voltage amplifier is one with Ri = ∞. In this ideal case both the current gain and power gain become infinite.
The overall voltage gain (vo/vs) can be found by combining Eqs. (1.12) and (1.13), There are situations in which one is interested not in voltage gain but only in a significant power gain. For instance, the source signal can have a respectable voltage but a source resis-tance that is much greater than the load resistance. Connecting the source directly to the load would result in significant signal attenuation. In such a case, one requires an amplifier with a high input resistance (much greater than the source resistance) and a low output resistance (much smaller than the load resistance) but with a modest voltage gain (or even unity gain).
Such an amplifier is referred to as a buffer amplifier. We shall encounter buffer amplifiers often throughout this book.
Avo.
vi vs Ri Ri Rs + ----------------= Ri Rs · .
vo vs ----Avo Ri Ri Rs + ----------------RL RL Ro + ------------------= 1.12 A transducer characterized by a voltage of 1 V rms and a resistance of 1 MΩ is available to drive a 10-Ω load. If connected directly, what voltage and power levels result at the load? If a unity-gain (i.e., ) buffer amplifier with 1-MΩ input resistance and 10-Ω output resistance is interposed between source and load, what do the output voltage and power levels become? For the new arrangement, find the voltage gain from source to load, and the power gain (both expressed in decibels).
Ans. 10 μV rms; 10−11 W; 0.25 V; 6.25 mW; −12 dB; 44 dB 1.13 The output voltage of a voltage amplifier has been found to decrease by 20% when a load resistance of 1 kΩ is connected. What is the value of the amplifier output resistance?
Ans. 250 Ω 1.14 An amplifier with a voltage gain of +40 dB, an input resistance of 10 kΩ, and an output resistance of 1 kΩ is used to drive a 1-kΩ load. What is the value of ? Find the value of the power gain in decibels.
Ans. 100 V/V; 44 dB Avo 1 = Avo EXERCISES 24 Chapter 1 Signals and Amplifiers 1.5.2 Cascaded Amplifiers To meet given amplifier specifications, we often need to design the amplifier as a cascade of two or more stages. The stages are usually not identical; rather, each is designed to serve a specific purpose. For instance, in order to provide the overall amplifier with a large input resistance, the first stage is usually required to have a large input resistance. Also, in order to equip the overall amplifier with a low output resistance, the final stage in the cascade is usu-ally designed to have a low output resistance. To illustrate the analysis and design of cas-caded amplifiers, we consider a practical example.
Example 1.3 Figure 1.17 depicts an amplifier composed of a cascade of three stages. The amplifier is fed by a signal source with a source resistance of 100 kΩ and delivers its output into a load resistance of 100 Ω. The first stage has a relatively high input resistance and a modest gain factor of 10. The second stage has a higher gain factor but lower input resistance. Finally, the last, or output, stage has unity gain but a low output resistance.
We wish to evaluate the overall voltage gain, that is, vL/vs, the current gain, and the power gain.
Solution The fraction of source signal appearing at the input terminals of the amplifier is obtained using the volt-age-divider rule at the input, as follows: The voltage gain of the first stage is obtained by considering the input resistance of the second stage to be the load of the first stage; that is, Similarly, the voltage gain of the second stage is obtained by considering the input resistance of the third stage to be the load of the second stage, Figure 1.17 Three-stage amplifier for Example 1.3.
vi1 vs ------1 MΩ 1 MΩ 100 kΩ + ----------------------------------------0.909 V/V = = Av1 vi2 vi1 ------≡ 10 100 kΩ 100 kΩ 1 kΩ + -------------------------------------9.9 V/V = = Av2 vi3 vi2 ------≡ 100 10 kΩ 10 kΩ 1 kΩ + ----------------------------------90.9 V/V = = 1.5 Circuit Models for Amplifiers 25 A few comments on the cascade amplifier in the above example are in order. To avoid losing signal strength at the amplifier input where the signal is usually very small, the first stage is designed to have a relatively large input resistance (1 MΩ), which is much larger than the source resistance. The trade-off appears to be a moderate voltage gain (10 V/V). The second stage does not need to have such a high input resistance; rather, here we need to realize the bulk of the required voltage gain. The third and final, or output, stage is not asked to provide any voltage gain; rather, it functions as a buffer amplifier, providing a relatively large input resistance and a low out-put resistance, much lower than RL. It is this stage that enables connecting the amplifier to the 10-Ω load. These points can be made more concrete by solving the following exercises. In so doing, observe that in finding the gain of an amplifier stage in a cascade amplifier, the loading effect of the succeeding amplifier stage must be taken into account as we have done in the above example.
Finally, the voltage gain of the output stage is as follows: The total gain of the three stages in cascade can be now found from or 58.3 dB.
To find the voltage gain from source to load, we multiply Av by the factor representing the loss of gain at the input; that is, or 57.4 dB.
The current gain is found as follows: or 138.3 dB.
The power gain is found from or 98.3 dB. Note that Av3 vL vi3 ------≡ 1 100 Ω 100 Ω 10 Ω + ----------------------------------0.909 V/V = = Av vL vi1 ------≡ Av1Av2Av3 818 V/V = = vL vs -----vL vi1 ------vi1 vs ------Av vi1 vs ------= = 818 0.909 × = 743.6 V/V = Ai io ii ---≡ vL/ 100 Ω vi1 1 MΩ ⁄ --------------------------= 104 Av × = 8.18 106 A/A × = Ap PL PI ------≡ vLio vi1ii ----------= Av Ai = 818 8.18 106 × × 66.9 108 W/W × = = Ap dB ( ) 1 2 --- Av dB ( ) Ai dB ( ) + [ ] = 26 Chapter 1 Signals and Amplifiers 1.5.3 Other Amplifier Types In the design of an electronic system, the signal of interest—whether at the system input, at an intermediate stage, or at the output—can be either a voltage or a current. For instance, some trans-ducers have very high output resistances and can be more appropriately modeled as current sources. Similarly, there are applications in which the output current rather than the voltage is of Table 1.1 The Four Amplifier Types Type Circuit Model Gain Parameter Ideal Characteristics Voltage Amplifier Open-Circuit Voltage Gain Ri = ∞ Ro = 0 Current Amplifier Short-Circuit Current Gain Ri = 0 Ro = ∞ Transconductance Amplifier Short-Circuit Transconductance Ri = ∞ Ro = ∞ Transresistance Amplifier Open-Circuit Transresistance Ri = 0 Ro = 0 vo io Ri v i Ro Avovi Avo vo vi -----≡ io=0 V/V ( ) vo io ii Ri Ro Aisii Ais io ii ---≡ vo=0 A/A ( ) vo io Ri v i vi Ro G m Gm io vi ----≡ vo=0 A/V ( ) vo io Ri Ro ii ii Rm Rm vo ii -----≡ io=0 V/A ( ) 1.15 What would the overall voltage gain of the cascade amplifier in Example 1.3 be without stage 3?
Ans. 81.8 V/V 1.16 For the cascade amplifier of Example 1.3, let vs be 1 mV. Find vi1, vi2, vi3, and vL.
Ans. 0.91 mV; 9 mV; 818 mV; 744 mV 1.17 (a) Model the three-stage amplifier of Example 1.3 (without the source and load), using the voltage amplifier model. What are the values of Ri, Av o, and Ro?
(b) If RL varies in the range 10 Ω to 1000 Ω, find the corresponding range of the overall voltage gain, vo/vs.
Ans. 1 MΩ, 900 V/V, 10 Ω; 409 V/V to 810 V/V EXERCISES 1.5 Circuit Models for Amplifiers 27 interest. Thus, although it is the most popular, the voltage amplifier considered above is just one of four possible amplifier types. The other three are the current amplifier, the transconductance ampli-fier, and the transresistance amplifier. Table 1.1 shows the four amplifier types, their circuit mod-els, the definition of their gain parameters, and the ideal values of their input and output resistances.
1.5.4 Relationships between the Four Amplifier Models Although for a given amplifier a particular one of the four models in Table 1.1 is most pref-erable, any of the four can be used to model any amplifier. In fact, simple relationships can be derived to relate the parameters of the various models. For instance, the open-circuit volt-age gain Av o can be related to the short-circuit current gain Ais as follows: The open-circuit output voltage given by the voltage amplifier model of Table 1.1 is Av ovi. The current ampli-fier model in the same table gives an open-circuit output voltage of Aisii Ro. Equating these two values and noting that ii = vi /Ri gives (1.14) Similarly, we can show that (1.15) and (1.16) The expressions in Eqs. (1.14) to (1.16) can be used to relate any two of the gain parameters Avo, Ais, Gm, and Rm.
1.5.5 Determining Ri and Ro From the amplifier circuit models given in Table 1.1, we observe that the input resistance Ri of the amplifier can be determined by applying an input voltage vi and measuring (or calculating) the input current ii; that is, Ri = vi /ii. The output resistance is found as the ratio of the open-circuit output voltage to the short-circuit output current. Alternatively, the output resistance can be found by eliminating the input signal source (then ii and vi will both be zero) and apply-ing a voltage signal vx to the output of the amplifier, as shown in Fig. 1.18. If we denote the current drawn from vx into the output terminals as ix (note that ix is opposite in direction to io), then Ro = vx/ix. Although these techniques are conceptually correct, in actual practice more refined methods are employed in measuring Ri and Ro.
Avo Ais Ro Ri -----⎝ ⎠ ⎛ ⎞ = Avo GmRo = Avo Rm Ri ------= vx ix Ro vx ix Figure 1.18 Determining the output resistance.
28 Chapter 1 Signals and Amplifiers 1.5.6 Unilateral Models The amplifier models considered above are unilateral; that is, signal flow is unidirectional, from input to output. Most real amplifiers show some reverse transmission, which is usually undesirable but must nonetheless be modeled. We shall not pursue this point further at this time except to mention that more complete models for linear two-port networks are given in Appendix C. Also, in later chapters, we will find it necessary in certain cases to augment the models of Table 1.1 to take into account the nonunilateral nature of some transistor amplifiers.
The bipolar junction transistor (BJT), which will be studied in Chapter 6, is a three-terminal device that when powered-up by a dc source (battery) and operated with small signals can be modeled by the lin-ear circuit shown in Fig. 1.19(a). The three terminals are the base (B), the emitter (E), and the collector (C). The heart of the model is a transconductance amplifier represented by an input resistance between B and E (denoted rπ ), a short-circuit transconductance gm, and an output resistance ro.
(a) With the emitter used as a common terminal between input and output, Fig. 1.19(b) shows a tran-sistor amplifier known as a common-emitter or grounded-emitter circuit. Derive an expression for the voltage gain vo/vs, and evaluate its magnitude for the case Rs = 5 kΩ, rπ = 2.5 kΩ, gm = 40 mA/V, ro = 100 kΩ, and RL = 5 kΩ. What would the gain value be if the effect of ro were neglected?
(b) An alternative model for the transistor in which a current amplifier rather than a transconductance am-plifier is utilized is shown in Fig. 1.19(c). What must the short-circuit current gain β be? Give both an expression and a value.
Figure 1.19 (a) Small-signal circuit model for a bipolar junction transistor (BJT). (b) The BJT connected as an amplifier with the emitter as a common terminal between input and output (called a common-emitter amplifier). (c) An alternative small-signal circuit model for the BJT.
(a) C E B ro gmvbe rp vbe (b) C E B ro RL Rs gmvbe rp vbe 1 2 vo 1 2 vs 1 2 (c) C E B ro ib rp vbe 1 2 bib Example 1.4 1.5 Circuit Models for Amplifiers 29 Solution (a) Refer to Fig. 1.19(b). We use the voltage-divider rule to determine the fraction of input signal that appears at the amplifier input as (1.17) Next we determine the output voltage vo by multiplying the current (gmvbe) by the resistance (RL || ro), (1.18) Substituting for vbe from Eq. (1.17) yields the voltage-gain expression (1.19) Observe that the gain is negative, indicating that this amplifier is inverting. For the given component values, Neglecting the effect of ro, we obtain which is quite close to the value obtained including ro. This is not surprising, since (b) For the model in Fig. 1.19(c) to be equivalent to that in Fig. 1.19(a), βib = gmvbe But ; thus, β = gmrπ For the values given, β = 40 mA/V × 2.5 kΩ = 100 A/A vbe vs rπ rπ Rs + ----------------= vo gmvbe RL ro || ( ) – = vo vs -----rπ rπ Rs + ----------------gm RL ro || ( ) – = vo vs ----- = 2.5 2.5 5 + ----------------– 40 5 100 || ( ) × × 63.5 V/V – = vo vs ----- 2.5 2.5 5 + ----------------40 5 × × – 66.7 V/V – = ro RL.
ib vbe rπ ⁄ = 1.18 Consider a current amplifier having the model shown in the second row of Table 1.1. Let the ampli-fier be fed with a signal current-source is having a resistance Rs, and let the output be connected to a load resistance RL. Show that the overall current gain is given by 1.19 Consider the transconductance amplifier whose model is shown in the third row of Table 1.1. Let a voltage signal source vs with a source resistance Rs be connected to the input and a load resistance RL be connected to the output. Show that the overall voltage-gain is given by io is ---Ais Rs Rs Ri + ----------------Ro Ro RL + ------------------= vo vs -----Gm Ri Ri Rs + ---------------- Ro RL || ( ) = EXERCISES 30 Chapter 1 Signals and Amplifiers 1.6 Frequency Response of Amplifiers2 From Section 1.2 we know that the input signal to an amplifier can always be expressed as the sum of sinusoidal signals. It follows that an important characterization of an amplifier is in terms of its response to input sinusoids of different frequencies. Such a characterization of amplifier performance is known as the amplifier frequency response.
1.6.1 Measuring the Amplifier Frequency Response We shall introduce the subject of amplifier frequency response by showing how it can be measured. Figure 1.20 depicts a linear voltage amplifier fed at its input with a sine-wave signal of amplitude Vi and frequency ω. As the figure indicates, the signal measured at the amplifier output also is sinusoidal with exactly the same frequency ω. This is an important point to note: Whenever a sine-wave signal is applied to a linear circuit, the resulting output is sinusoidal with the same frequency as the input. In fact, the sine wave is the only signal that does not change shape as it passes through a linear circuit. Observe, however, that the output sinusoid will in general have a different amplitude and will be shifted in phase relative to the input. The ratio of the amplitude of the output sinusoid (Vo) to the amplitude of the input sinusoid (Vi) is the magnitude of the amplifier gain (or transmission) at the test fre-quency ω. Also, the angle φ is the phase of the amplifier transmission at the test frequency ω. If we denote the amplifier transmission, or transfer function as it is more commonly 2Except for its use in the study of the frequency response of op-amp circuits in Sections 2.5 and 2.7, the material in this section will not be needed in a substantial manner until Chapter 9. 1.20 Consider a transresistance amplifier having the model shown in the fourth row of Table 1.1. Let the amplifier be fed with a signal current-source is having a resistance Rs, and let the output be connected to a load resistance RL. Show that the overall gain is given by 1.21 Find the input resistance between terminals B and G in the circuit shown in Fig. E1.21. The voltage vx is a test voltage with the input resistance Rin defined as Rin ≡ vx/ ix.
Ans. Rin = rπ + (β + 1)Re vo is -----Rm Rs Rs Ri + ---------------- RL RL Ro + ------------------= Rin ix Figure E1.21 1.6 Frequency Response of Amplifiers 31 known, by T(ω), then The response of the amplifier to a sinusoid of frequency ω is completely described by |T(ω)| and ∠T(ω). Now, to obtain the complete frequency response of the amplifier we simply change the frequency of the input sinusoid and measure the new value for |T | and ∠T. The end result will be a table and/or graph of gain magnitude [|T(ω)|] versus frequency and a table and/or graph of phase angle [∠T(ω)] versus frequency. These two plots together constitute the frequency response of the amplifier; the first is known as the magnitude or amplitude response, and the second is the phase response. Finally, we should mention that it is a common practice to express the magnitude of transmission in decibels and thus plot 20 log |T(ω)| versus frequency.
1.6.2 Amplifier Bandwidth Figure 1.21 shows the magnitude response of an amplifier. It indicates that the gain is almost constant over a wide frequency range, roughly between ω1 and ω2. Signals whose frequencies are below ω1 or above ω2 will experience lower gain, with the gain decreasing as we move farther away from ω1 and ω2. The band of frequencies over which the gain of the amplifier is almost constant, to within a certain number of decibels (usually 3 dB), is called the amplifier bandwidth. Normally the amplifier is designed so that its bandwidth coincides with the spectrum of the signals it is required to amplify. If this were not the case, the amplifier would distort the frequency spectrum of the input signal, with different components of the input signal being amplified by different amounts.
1.6.3 Evaluating the Frequency Response of Amplifiers Above, we described the method used to measure the frequency response of an amplifier.
We now briefly discuss the method for analytically obtaining an expression for the fre-quency response. What we are about to say is just a preview of this important subject, whose detailed study is in Chapter 9.
Figure 1.20 Measuring the frequency response of a linear amplifier: At the test frequency ω, the amplifier gain is characterized by its magnitude (Vo/Vi) and phase φ.
vo Vo sin (t ) vi Vi sin t Linear amplifier T ω ( ) Vo Vi -----= T ω ( ) ∠ φ = 32 Chapter 1 Signals and Amplifiers To evaluate the frequency response of an amplifier, one has to analyze the amplifier equivalent circuit model, taking into account all reactive components.3 Circuit analysis proceeds in the usual fashion but with inductances and capacitances represented by their reactances. An inductance L has a reactance or impedance jωL, and a capacitance C has a reactance or impedance or, equivalently, a susceptance or admittance jωC. Thus in a frequency-domain analysis we deal with impedances and/or admittances. The result of the analysis is the amplifier transfer function T(ω) where Vi(ω) and Vo(ω) denote the input and output signals, respectively. T(ω) is generally a complex function whose magnitude |T(ω)| gives the magnitude of transmission or the mag-nitude response of the amplifier. The phase of T(ω) gives the phase response of the ampli-fier.
In the analysis of a circuit to determine its frequency response, the algebraic manipulations can be considerably simplified by using the complex frequency variable s. In terms of s, the impedance of an inductance L is sL and that of a capacitance C is Replacing the reactive elements with their impedances and performing standard circuit analysis, we obtain the transfer function T(s) as Subsequently, we replace s by jω to determine the transfer function for physical frequen-cies, T( jω). Note that T( jω) is the same function we called T(ω) above4; the additional j is included in order to emphasize that T( jω) is obtained from T(s) by replacing s with jω.
Figure 1.21 Typical magnitude response of an amplifier: |T(ω)| is the magnitude of the amplifier transfer function—that is, the ratio of the output Vo(ω) to the input Vi(ω).
3Note that in the models considered in previous sections no reactive components were included. These were simplified models and cannot be used alone to predict the amplifier frequency response.
4At this stage, we are using s simply as a shorthand for jω. We shall not require detailed knowledge of s-plane concepts until Chapter 9. A brief review of s-plane analysis is presented in Appendix F.
1 jωC ⁄ T ω ( ) Vo ω ( ) Vi ω ( ) ---------------= 1 sC.
⁄ T s ( ) Vo s ( ) Vi s ( ) -------------≡ 1.6 Frequency Response of Amplifiers 33 1.6.4 Single-Time-Constant Networks In analyzing amplifier circuits to determine their frequency response, one is greatly aided by knowledge of the frequency-response characteristics of single-time-constant (STC) networks.
An STC network is one that is composed of, or can be reduced to, one reactive component (inductance or capacitance) and one resistance. Examples are shown in Fig. 1.22. An STC network formed of an inductance L and a resistance R has a time constant The time constant τ of an STC network composed of a capacitance C and a resistance R is given by τ = CR.
Appendix E presents a study of STC networks and their responses to sinusoidal, step, and pulse inputs. Knowledge of this material will be needed at various points throughout this book, and the reader will be encouraged to refer to the appendix. At this point we need in particular the frequency response results; we will, in fact, briefly discuss this important topic, now.
Most STC networks can be classified into two categories,5 low pass (LP) and high pass (HP), with each of the two categories displaying distinctly different signal responses. As an example, the STC network shown in Fig. 1.22(a) is of the low-pass type and that in Fig.
1.22(b) is of the high-pass type. To see the reasoning behind this classification, observe that the transfer function of each of these two circuits can be expressed as a voltage-divider ratio, with the divider composed of a resistor and a capacitor. Now, recalling how the impedance of a capacitor varies with frequency , it is easy to see that the transmission of the circuit in Fig. 1.22(a) will decrease with frequency and approach zero as ω approaches ∞. Thus the circuit of Fig. 1.22(a) acts as a low-pass filter6; it passes low-frequency, sine-wave inputs with little or no attenuation (at ω = 0, the transmission is unity) and attenuates high-frequency input sinusoids. The circuit of Fig. 1.22(b) does the opposite; its transmission is unity at ω = ∞ and decreases as ω is reduced, reaching 0 for ω = 0. The latter circuit, therefore, performs as a high-pass filter.
Table 1.2 provides a summary of the frequency-response results for STC networks of both types.7 Also, sketches of the magnitude and phase responses are given in Figs. 1.23 and 1.24. These frequency-response diagrams are known as Bode plots and the 3-dB frequency 5An important exception is the all-pass STC network studied in Chapter 16.
6A filter is a circuit that passes signals in a specified frequency band (the filter passband) and stops or severely attenuates (filters out) signals in another frequency band (the filter stopband). Filters will be studied in Chapter 16.
7The transfer functions in Table 1.2 are given in general form. For the circuits of Fig. 1.22, K = 1 and ω 0 = 1/CR.
τ L R ⁄ .
= (Z 1 jωC ⁄ ) = R Vi (a) C Vo R Vi (b) C Vo Figure 1.22 Two examples of STC networks: (a) a low-pass network and (b) a high-pass network.
34 Chapter 1 Signals and Amplifiers Table 1.2 Frequency Response of STC Networks Low-Pass (LP) High-Pass (HP) Transfer Function T(s) Transfer Function (for physical frequencies) T( jω) Magnitude Response |T( jω)| Phase Response ∠T( jω) Transmission at ω = 0 (dc) K 0 Transmission at ω = ∞ 0 K 3-dB Frequency ω0 = 1/τ; τ ≡ time constant τ = CR or L/R Bode Plots in Fig. 1.23 in Fig. 1.24 K 1 s ω0 ⁄ ( ) + --------------------------Ks s ω0 + --------------K 1 j ω ω0 ⁄ ( ) + ------------------------------K 1 j ω0 ω ⁄ ( ) – ------------------------------K 1 ω ω0 ⁄ ( )2 + -----------------------------------K 1 ω0 ω ⁄ ( )2 + -----------------------------------tan 1 – ω ω0 ⁄ ( ) – tan 1 – ω0 ω ⁄ ( ) (a) (b) Figure 1.23 (a) Magnitude and (b) phase response of STC networks of the low-pass type.
1.6 Frequency Response of Amplifiers 35 (ω0) is also known as the corner frequency, break frequency, or pole frequency. The reader is urged to become familiar with this information and to consult Appendix E if further clarifications are needed. In particular, it is important to develop a facility for the rapid determination of the time constant τ of an STC circuit. The process is very simple: Set the independent voltge or current source to zero; “grab hold” of the two terminals of the reactive element (capacitor C or inductor L); and determine the equivalent resistance R that appears between these two terminals. The time-constant is then CR or L/R.
(a) (b) Figure 1.24 (a) Magnitude and (b) phase response of STC networks of the high-pass type.
36 Chapter 1 Signals and Amplifiers Example 1.5 Figure 1.25 shows a voltage amplifier having an input resistance Ri , an input capacitance Ci , a gain factor μ, and an output resistance Ro. The amplifier is fed with a voltage source Vs having a source resistance Rs, and a load of resistance RL is connected to the output.
(a) Derive an expression for the amplifier voltage gain as a function of frequency. From this find expressions for the dc gain and the 3-dB frequency.
(b) Calculate the values of the dc gain, the 3-dB frequency, and the frequency at which the gain becomes 0 dB (i.e., unity) for the case Rs = 20 kΩ, Ri = 100 kΩ, Ci = 60 pF, Ro = 200 Ω, and RL = 1 kΩ.
(c) Find vo(t) for each of the following inputs: (i) vi = 0.1 sin 102 t, V (ii) vi = 0.1 sin 105 t, V (iii) vi = 0.1 sin 106 t, V (iv) vi = 0.1 sin 108 t, V Solution (a) Utilizing the voltage-divider rule, we can express Vi in terms of Vs as follows where Z i is the amplifier input impedance. Since Zi is composed of two parallel elements, it is obviously easier to work in terms of . Toward that end we divide the numerator and denominator by Zi , thus obtaining Thus, Figure 1.25 Circuit for Example 1.5.
Ro Vs Vi RL Rs Vi Ri Ci Vo Vo Vs ⁄ μ 144 V/V, = Vi Vs Zi Zi Rs + ----------------= Yi 1 Zi ⁄ = Vi Vs 1 1 RsYi + -------------------= Vs 1 1 Rs 1 Ri ⁄ ( ) sCi + [ ] + ---------------------------------------------------= Vi Vs -----1 1 Rs Ri ⁄ ( ) sCiRs + + ------------------------------------------------= 1.6 Frequency Response of Amplifiers 37 This expression can be put in the standard form for a low-pass STC network (see the top line of Table 1.2) by extracting from the denominator; thus we have (1.20) At the output side of the amplifier we can use the voltage-divider rule to write This equation can be combined with Eq. (1.20) to obtain the amplifier transfer function as (1.21) We note that only the last factor in this expression is new (compared with the expression derived in the last section). This factor is a result of the input capacitance Ci, with the time constant being (1.22) We could have obtained this result by inspection: From Fig. 1.25 we see that the input circuit is an STC network and that its time constant can be found by reducing Vs to zero, with the result that the resistance seen by Ci is Ri in parallel with Rs. The transfer function in Eq. (1.21) is of the form which corresponds to a low-pass STC network. The dc gain is found as (1.23) The 3-dB frequency ω0 can be found from (1.24) Since the frequency response of this amplifier is of the low-pass STC type, the Bode plots for the gain magnitude and phase will take the form shown in Fig. 1.23, where K is given by Eq. (1.23) and ω0 is given by Eq. (1.24).
(b) Substituting the numerical values given into Eq. (1.23) results in Thus the amplifier has a dc gain of 40 dB. Substituting the numerical values into Eq. (1.24) gives the 3-dB frequency 1 Rs Ri ⁄ ( ) + [ ] Vi Vs -----1 1 Rs Ri ⁄ ( ) + ----------------------------1 1 sCi RsRi ( ) Rs Ri + ( ) ⁄ [ ] + ----------------------------------------------------------------= Vo μVi RL RL Ro + ------------------= Vo Vs -----μ 1 1 Rs Ri ⁄ ( ) + ----------------------------1 1 Ro RL ⁄ ( ) + ------------------------------1 1 sCi RsRi ( ) Rs Ri + ( ) ⁄ [ ] + ----------------------------------------------------------------= τ Ci RsRi Rs Ri + ----------------= Ci Rs || Ri ( ) = K 1 s ω0 ⁄ ( ) + ( ) ⁄ , K Vo Vs ----- s 0 = ( ) ≡ μ 1 1 Rs Ri ⁄ ( ) + ----------------------------1 1 Ro RL ⁄ ( ) + ------------------------------= ω0 1 τ ---1 Ci Rs || Ri ( ) ---------------------------= = K 144 1 1 20 100 ⁄ ( ) + ---------------------------------1 1 200 1000 ⁄ ( ) + ---------------------------------------100 V/V = = ω0 = 1 60 pF 20 kΩ//100 kΩ ( ) × ---------------------------------------------------------------1 60 10 12 – 20 100 20 100 + ( ) ⁄ × ( ) 103 × × × ------------------------------------------------------------------------------------------------------= = 106 rad/s 38 Chapter 1 Signals and Amplifiers 1.6.5 Classification of Amplifiers Based on Frequency Response Amplifiers can be classified based on the shape of their magnitude-response curve. Figure 1.26 shows typical frequency-response curves for various amplifier types. In Fig. 1.26(a) the gain remains constant over a wide frequency range, but falls off at low and high frequencies. This type of frequency response is common in audio amplifiers.
As will be shown in later chapters, internal capacitances in the device (a transistor) cause the falloff of gain at high frequencies, just as Ci did in the circuit of Example 1.5. On the other hand, the falloff of gain at low frequencies is usually caused by coupling capacitors used to connect one amplifier stage to another, as indicated in Fig. 1.27. This practice is usu-ally adopted to simplify the design process of the different stages. The coupling capacitors Example 1.5 continued Thus, Since the gain falls off at the rate of –20 dB/decade, starting at ω 0 (see Fig. 1.23a) the gain will reach 0 dB in two decades (a factor of 100); thus we have (c) To find vo(t) we need to determine the gain magnitude and phase at 102, 105, 106, and 108 rad/s. This can be done either approximately utilizing the Bode plots of Fig. 1.23 or exactly utilizing the expression for the amplifier transfer function, We shall do both: (i) For ω = 102 rad/s, which is the Bode plots of Fig. 1.23 suggest that |T| = K = 100 and φ = 0°. The transfer function expression gives |T| 100 and φ = –tan–1 10–4 0°. Thus, vo(t) = 10 sin 102t, V (ii) For ω = 105 rad/s, which is , the Bode plots of Fig. 1.23 suggest that |T| K = 100 and φ = −5.7°. The transfer function expression gives |T| = 99.5 and φ = −tan−1 0.1 = −5.7°. Thus, vo(t) = 9.95 sin(105t – 5.7°), V (iii) For ω = 106 rad/s = ω0, or 37 dB and φ = −45°. Thus, vo(t) = 7.07 sin(106t − 45°), V (iv) For ω = 108 rad/s, which is (100ω 0), the Bode plots suggest that |T| = 1 and φ = –90°. The transfer function expression gives |T | 1 and φ = −tan–1 100 = −89.4° Thus, vo(t) = 0.1 sin(108t − 89.4°), V f0 106 2π --------159.2 kHz = = Unity-gain frequency 100 ω 0 × 108 rad/s or 15.92 MHz = = T jω ( ) Vo Vs ----- jω ( ) ≡ 100 1 j ω 106 ⁄ ( ) + --------------------------------= ω0 10 ⁄ 4 ( ), ω0 10 ⁄ ( ) T 100 2 ⁄ 70.7 V/V = = 1.6 Frequency Response of Amplifiers 39 are usually chosen quite large (a fraction of a microfarad to a few tens of microfarads) so that their reactance (impedance) is small at the frequencies of interest. Nevertheless, at suffi-ciently low frequencies the reactance of a coupling capacitor will become large enough to cause part of the signal being coupled to appear as a voltage drop across the coupling capac-itor, thus not reaching the subsequent stage. Coupling capacitors will thus cause loss of gain at low frequencies and cause the gain to be zero at dc. This is not at all surprising, since from Figure 1.26 Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.
(a) (b) (c) s Figure 1.27 Use of a capacitor to couple amplifier stages.
40 Chapter 1 Signals and Amplifiers Fig. 1.27 we observe that the coupling capacitor, acting together with the input resistance of the subsequent stage, forms a high-pass STC circuit. It is the frequency response of this high-pass circuit that accounts for the shape of the amplifier frequency response in Fig.
1.26(a) at the low-frequency end.
There are many applications in which it is important that the amplifier maintain its gain at low frequencies down to dc. Furthermore, monolithic integrated-circuit (IC) technology does not allow the fabrication of large coupling capacitors. Thus IC amplifiers are usually designed as directly coupled or dc amplifiers (as opposed to capacitively coupled, or ac amplifiers). Figure 1.26(b) shows the frequency response of a dc amplifier. Such a frequency response characterizes what is referred to as a low-pass amplifier.
In a number of applications, such as in the design of radio and TV receivers, the need arises for an amplifier whose frequency response peaks around a certain frequency (called the center frequency) and falls off on both sides of this frequency, as shown in Fig. 1.26(c). Amplifiers with such a response are called tuned amplifiers, bandpass amplifiers, or bandpass filters.
A tuned amplifier forms the heart of the front-end or tuner of a communication receiver; by adjusting its center frequency to coincide with the frequency of a desired communications channel (e.g., a radio station), the signal of this particular channel can be received while those of other channels are attenuated or filtered out. 1.22 Consider a voltage amplifier having a frequency response of the low-pass STC type with a dc gain of 60 dB and a 3-dB frequency of 1000 Hz. Find the gain in dB at f = 10 Hz, 10 kHz, 100 kHz, and 1 MHz.
Ans. 60 dB; 40 dB; 20 dB; 0 dB D1.23 Consider a transconductance amplifier having the model shown in Table 1.1 with Ri = 5 kΩ, Ro = 50 kΩ, and Gm = 10 mA/V. If the amplifier load consists of a resistance RL in parallel with a capaci-tance CL, convince yourself that the voltage transfer function realized, Vo/Vi, is of the low-pass STC type. What is the lowest value that RL can have while a dc gain of at least 40 dB is obtained?
With this value of RL connected, find the highest value that CL can have while a 3-dB bandwidth of at least 100 kHz is obtained.
Ans. 12.5 kΩ; 159.2 pF D1.24 Consider the situation illustrated in Fig. 1.27. Let the output resistance of the first voltage ampli-fier be 1 kΩ and the input resistance of the second voltage amplifier (including the resistor shown) be 9 kΩ. The resulting equivalent circuit is shown in Fig. E1.24 where Vs and Rs are the output voltage and output resistance of the first amplifier, C is a coupling capacitor, and Ri is the input resistance of the second amplifier. Convince yourself that V2/Vs is a high-pass STC function. What is the smallest value for C that will ensure that the 3-dB frequency is not higher than 100 Hz?
Ans. 0.16 μF Vs C V2 Rs 1 k Ri 9 k Figure E1.24 EXERCISES 1.6 Frequency Response of Amplifiers 41 Summary An electrical signal source can be represented in either the Thévenin form (a voltage source vs in series with a source resistance Rs) or the Norton form (a current source is in parallel with a source resistance Rs). The Thévenin volt-age vs is the open-circuit voltage between the source ter-minals; the Norton current is is equal to the short-circuit current between the source terminals. For the two repre-sentations to be equivalent, vs and Rsis must be equal.
A signal can be represented either by its waveform versus time or as the sum of sinusoids. The latter representation is known as the frequency spectrum of the signal.
The sine-wave signal is completely characterized by its peak value (or rms value which is the peak / ), its fre-quency (ω in rad/s or f in Hz; ω = 2πf and f = 1/T, where T is the period in seconds), and its phase with respect to an arbitrary reference time.
Analog signals have magnitudes that can assume any value. Electronic circuits that process analog signals are called analog circuits. Sampling the magnitude of an an-alog signal at discrete instants of time and representing each signal sample by a number results in a digital signal.
Digital signals are processed by digital circuits.
The simplest digital signals are obtained when the binary system is used. An individual digital signal then assumes one of only two possible values: low and high (say, 0 V and +5 V), corresponding to logic 0 and logic 1, respec-tively.
An analog-to-digital converter (ADC) provides at its output the digits of the binary number representing the analog signal sample applied to its input. The output dig-ital signal can then be processed using digital circuits.
Refer to Fig. 1.10 and Eq. (1.3).
The transfer characteristic, vO versus vI, of a linear ampli-fier is a straight line with a slope equal to the voltage gain. Refer to Fig. 1.12.
Amplifiers increase the signal power and thus require dc power supplies for their operation.
The amplifier voltage gain can be expressed as a ratio Av in V/V or in decibels, 20 log|Av|, dB. Similarly, for current gain: Ai A/A or 20 log|Ai|, dB. For power gain: Ap W/W or 10 log Ap, dB.
Depending on the signal to be amplified (voltage or cur-rent) and on the desired form of output signal (voltage or current), there are four basic amplifier types: voltage, current, transconductance, and transresistance amplifi-ers. For the circuit models and ideal characteristics of these four amplifier types, refer to Table 1.1. A given am-plifier can be modeled by any one of the four models, in which case their parameters are related by the formulas in Eqs. (1.14) to (1.16).
A sinusoid is the only signal whose waveform is un-changed through a linear circuit. Sinusoidal signals are used to measure the frequency response of amplifiers.
The transfer function of a voltage amplifier can be determined from circuit analysis. Sub-stituting s = jω gives T( jω), whose magnitude |T( jω)| is the magnitude response, and whose phase φ (ω) is the phase response, of the amplifier.
Amplifiers are classified according to the shape of their frequency response, |T( jω)|. Refer to Fig. 1.26.
Single-time-constant (STC) networks are those networks that are composed of, or can be reduced to, one reactive component (L or C) and one resistance (R). The time con-stant τ is either L/R or CR.
STC networks can be classified into two categories: low-pass (LP) and high-pass (HP). LP networks pass dc and low frequencies and attenuate high frequencies. The op-posite is true for HP networks.
The gain of an LP (HP) STC circuit drops by 3 dB below the zero-frequency (infinite-frequency) value at a fre-quency ω0 = 1/τ. At high frequencies (low frequencies) the gain falls off at the rate of 6 dB/octave or 20 dB/de-cade. Refer to Table 1.2 on page 34 and Figs. 1.23 and 1.24. Further details are given in Appendix E.
2 T s ( ) Vo s ( ) Vi ⁄ s ( ) ≡ Computer Simulation Problems Problems involving design are marked with D throughout the text. As well, problems are marked with asterisks to describe their degree of difficulty. Difficult problems are marked with an asterisk (); more difficult problems with two asterisks (); and very challenging and/or time-consuming problems with three asterisks ().
Circuit Basics As a review of the basics of circuit analysis and in order for the readers to gauge their preparedness for the study of elec-tronic circuits, this section presents a number of relevant cir-cuit analysis problems. For a summary of Thévenin’s and Norton’s theorems, refer to Appendix D. The problems are grouped in appropriate categories.
Resistors and Ohm’s Law 1.1 Ohm’s law relates V, I, and R for a resistor. For each of the situations following, find the missing item: (a) R = 1 kΩ, V = 10 V (b) V = 10 V, I = 1 mA (c) R = 10 kΩ, I = 10 mA (d) R = 100 Ω, V = 10 V 1.2 Measurements taken on various resistors are shown below. For each, calculate the power dissipated in the resistor and the power rating necessary for safe operation using stan-dard components with power ratings of 1/8 W, 1/4 W, 1/2 W, 1 W, or 2 W: (a) 1 kΩ conducting 30 mA (b) 1 kΩ conducting 40 mA (c) 10 kΩ conducting 3 mA (d) 10 kΩ conducting 4 mA (e) 1 kΩ dropping 20 V (f) 1 kΩ dropping 11 V 1.3 Ohm’s law and the power law for a resistor relate V, I, R, and P, making only two variables independent. For each pair identified below, find the other two: (a) R = 1 kΩ, I = 10 mA (b) V = 10 V, I = 1 mA (c) V = 10 V, P = 1 W (d) I = 10 mA, P = 0.1 W (e) R = 1 kΩ, P = 1 W Combining Resistors 1.4 You are given three resistors whose values are 10 kΩ, 20 kΩ, and 40 kΩ. How many different resistances can you create using series and parallel combinations of these three?
List them in value order, lowest first. Be thorough and organized. (Hint: In your search, first consider all parallel com-binations, then consider series combinations, and then consider series-parallel combinations, of which there are two kinds).
1.5 In the analysis and test of electronic circuits, it is of-ten useful to connect one resistor in parallel with another to obtain a nonstandard value, one which is smaller than the smaller of the two resistors. Often, particularly during circuit testing, one resistor is already installed, in which case the second, when connected in parallel, is said to “shunt” the first. If the original resistor is 10 kΩ, what is the value of the shunting resistor needed to reduce the combined value by 1%, 5%, 10%, and 50%? What is the re-sult of shunting a 10-kΩ resistor by 1 MΩ? By 100 kΩ? By 10 kΩ?
Voltage Dividers 1.6 Figure P1.6(a) shows a two-resistor voltage divider.
Its function is to generate a voltage VO (smaller than the power-supply voltage VDD) at its output node X. The cir-cuit looking back at node X is equivalent to that shown in Fig. P1.6(b). Observe that this is the Thévenin equivalent of the voltage divider circuit. Find expressions for VO and RO.
Figure P1.6 1.7 A two-resistor voltage divider employing a 3.3-kΩ and a 6.8-kΩ resistor is connected to a 9-V ground-refer-enced power supply to provide a relatively low voltage (close to 3V). Sketch the circuit. Assuming exact-valued resistors, what output voltage (measured to ground) and equivalent output resistance result? If the resistors used are not ideal but have a ±5% manufacturing tolerance, what are the extreme output voltages and resistances that can result?
(a) VO RO R1 VDD X R2 (b) VO RO X PROBLEMS Problems 43 CHAPTER 1 PR OBLE MS 1.8 You are given three resistors, each of 10 kΩ, and a 9-V battery whose negative terminal is connected to ground. With a voltage divider using some or all of your resistors, how many positive-voltage sources of magnitude less than 9 V can you design? List them in order, smallest first. What is the out-put resistance (i.e., the Thévenin resistance) of each?
D 1.9 Two resistors, with nominal values of 4.7 kΩ and 10 kΩ, are used in a voltage divider with a +15-V supply to create a nominal +10-V output. Assuming the resistor values to be exact, what is the actual output voltage produced? Which resistor must be shunted (paralleled) by what third resistor to create a voltage-divider output of 10.00 V? If an output resistance of exactly 3.33 kΩ is also required, what do you suggest? What should be done if the original 4.7-kΩ and 10-kΩ resistors are used but the requirement is 10.00 V and 3.00 kΩ?
Current Dividers 1.10 Current dividers play an important role in circuit design.
Therefore it is important to develop a facility for dealing with current dividers in circuit analysis. Figure P1.10 shows a two-resistor current divider fed with an ideal current source I.
Show that and find the voltage V that develops across the current divider.
Figure P1.10 D 1.11 Design a simple current divider that will reduce the current provided to a 1-kΩ load to 20% of that available from the source.
D 1.12 A designer searches for a simple circuit to provide one-third of a signal current I to a load resistance R. Sug-gest a solution using one resistor. What must its value be?
What is the input resistance of the resulting current divider? For a particular value R, the designer discovers that the otherwise-best-available resistor is 10% too high.
Suggest two circuit topologies using one additional resistor that will solve this problem. What is the value of the resistor required? What is the input resistance of the current divider in each case?
D 1.13 A particular electronic signal source generates cur-rents in the range 0 mA to 1 mA under the condition that its load voltage not exceed 1 V. For loads causing more than 1 V to appear across the generator, the output current is no longer assured but will be reduced by some unknown amount. This circuit limitation, occurring, for example, at the peak of a sine-wave signal, will lead to undesirable signal distortion that must be avoided. If a 10-kΩ load is to be connected, what must be done? What is the name of the circuit you must use? How many resistors are needed? What is (are) the(ir) value(s)?
Thévenin Equivalent Circuits 1.14 For the circuit in Fig. P1.14, find the Thévenin equiva-lent circuit between terminals (a) 1 and 2, (b) 2 and 3, and (c) 1 and 3.
Figure P1.14 1.15 Through repeated application of Thévenin’s theorem, find the Thévenin equivalent of the circuit in Fig. P1.15 between node 4 and ground, and hence find the current that flows through a load resistance of 1.5 kΩ connected between node 4 and ground.
Figure P1.15 Circuit Analysis 1.16 For the circuit shown in Fig. P1.16, find the current in all resistors and the voltage (with respect to ground) at their common node using two methods: I1 R2 R1 R2 + ------------------I = I2 R1 R1 R2 + ------------------I = I R2 R1 V 1 2 I2 I1 1 k 1 k 1 2 3 3 V 1 2 3 4 10 V 10 k 10 k 10 k 10 k 10 k 10 k 44 Chapter 1 Signals and Amplifiers CHAPTER 1 P ROBL EMS (a) Current: Define branch currents I1 and I2 in R1 and R2, respectively; identify two equations; and solve them.
(b) Voltage: Define the node voltage V at the common node; identify a single equation; and solve it.
Which method do you prefer? Why?
Figure P1.16 1.17 The circuit shown in Fig. P1.17 represents the equiva-lent circuit of an unbalanced bridge. It is required to calculate the current in the detector branch (R5) and the voltage across it. Although this can be done by using loop and node equa-tions, a much easier approach is possible: Find the Thévenin equivalent of the circuit to the left of node 1 and the Thévenin equivalent of the circuit to the right of node 2. Then solve the resulting simplified circuit.
Figure P1.17 1.18 For the circuit in Fig. P1.18, find the equivalent resis-tance to ground, Req. To do this, apply a voltage Vx between terminal X and ground and find the current drawn from Vx.
Note that you can use particular special properties of the circuit to get the result directly! Now, if R4 is raised to 1.2 kΩ, what does Req become?
AC Circuits 1.19 The periodicity of recurrent waveforms, such as sine waves or square waves, can be completely specified using only one of three possible parameters: radian frequency, ω, in radians per second (rad/s); (conventional) frequency, f, in hertz (Hz); or period T, in seconds (s). As well, each of the parameters can be specified numerically in one of several ways: using letter prefixes associated with the basic units, using scientific notation, or using some combination of both.
Thus, for example, a particular period may be specified as 100 ns, 0.1 μs, 10–1 μs, 105 ps, or 1 × 10 –7 s. (For the defini-tion of the various prefixes used in electronics, see Appendix H) For each of the measures listed below, express the trio of terms in scientific notation associated with the basic unit (e.g., 10–7 s rather than 10–1 μs).
(a) T = 10–4 ms (b) f = 1 GHz (c) ω = 6.28 × 102 rad/s (d) T = 10 s (e) f = 60 Hz (f) ω = 1 krad/s (g) f = 1900 MHz 1.20 Find the complex impedance, Z, of each of the follow-ing basic circuit elements at 60 Hz, 100 kHz, and 1 GHz: (a) R = 1 kΩ (b) C = 10 nF (c) C = 2 pF (d) L = 10 mH (e) L = 1 nH 1.21 Find the complex impedance at 10 kHz of the following networks: (a) 1 kΩ in series with 10 nF (b) 1 kΩ in parallel with 0.01 μF R1 10 k R3 2 k R2 5 k 10 V 15 V 19 V R4 11 kV R2 1.2 kV R5 3 kV 1 2 R3 9.1 kV R1 1 kV R5 X 1 kV Req R3 1 kV R1 1 kV R4 1 kV R2 1 kV Figure P1.18 Problems 45 CHAPTER 1 PR OBLE MS (c) 100 kΩ in parallel with 100 pF (d) 100 Ω in series with 10 mH Section 1.1: Signals 1.22 Any given signal source provides an open-circuit volt-age, voc, and a short-circuit current isc. For the following sources, calculate the internal resistance, Rs; the Norton cur-rent, is; and the Thévenin voltage, vs: (a) voc = 10 V, isc = 100 μA (b) voc = 0.1 V, isc = 10 μA 1.23 A particular signal source produces an output of 30 mV when loaded by a 100-kΩ resistor and 10 mV when loaded by a 10-kΩ resistor. Calculate the Thévenin voltage, Norton cur-rent, and source resistance.
1.24 A temperature sensor is specified to provide 2 mV/°C.
When connected to a load resistance of 10 kΩ, the output voltage was measured to change by 10 mV , corresponding to a change in temperature of 10°C. What is the source resistance of the sensor?
1.25 Refer to the Thévenin and Norton representations of the signal source (Fig. 1.1). If the current supplied by the source is denoted io and the voltage appearing between the source output terminals is denoted vo, sketch and clearly label vo ver-sus io for 0 ≤ io ≤ is.
1.26 The connection of a signal source to an associated signal processor or amplifier generally involves some degree of signal loss as measured at the processor or amplifier input. Considering the two signal-source representations shown in Fig. 1.1, provide two sketches showing each signal-source representation con-nected to the input terminals (and corresponding input resis-tance) of a signal processor. What signal-processor input resistance will result in 90% of the open-circuit voltage being delivered to the processor? What input resistance will result in 90% of the short-circuit signal current entering the processor?
Section 1.2: Frequency Spectrum of Signals 1.27 To familiarize yourself with typical values of angular frequency ω, conventional frequency f, and period T, com-plete the entries in the following table: 1.28 For the following peak or rms values of some important sine waves, calculate the corresponding other value: (a) 117 V rms, a household-power voltage in North America (b) 33.9 V peak, a somewhat common peak voltage in recti-fier circuits (c) 220 V rms, a household-power voltage in parts of Europe (d) 220 kV rms, a high-voltage transmission-line voltage in North America 1.29 Give expressions for the sine-wave voltage signals having: (a) 10-V peak amplitude and 10-kHz frequency (b) 120-V rms and 60-Hz frequency (c) 0.2-V peak-to-peak and 1000-rad/s frequency (d) 100-mV peak and 1-ms period 1.30 Using the information provided by Eq. (1.2) in associ-ation with Fig. 1.5, characterize the signal represented by v(t) = 1/2 + 2/π (sin 2000πt + sin 6000πt + sin 10,000π t + ...).
Sketch the waveform. What is its average value? Its peak-to-peak value? Its lowest value? Its highest value? Its frequency?
Its period?
1.31 Measurements taken of a square-wave signal using a frequency-selective voltmeter (called a spectrum analyzer) show its spectrum to contain adjacent components (spectral lines) at 98 kHz and 126 kHz of amplitudes 63 mV and 49 mV, respectively. For this signal, what would direct measure-ment of the fundamental show its frequency and amplitude to be? What is the rms value of the fundamental? What are the peak-to-peak amplitude and period of the originating square wave?
1.32 What is the fundamental frequency of the highest-frequency square wave for which the fifth harmonic is barely audible by a relatively young listener? What is the fundamen-tal frequency of the lowest-frequency square wave for which the fifth and some of the higher harmonics are directly heard?
(Note that the psychoacoustic properties of human hearing allow a listener to sense the lower harmonics as well.) 1.33 Find the amplitude of a symmetrical square wave of period T that provides the same power as a sine wave of peak amplitude and the same frequency. Does this result depend on equality of the frequencies of the two waveforms?
Section 1.3: Analog and Digital Signals 1.34 Give the binary representation of the following decimal numbers: 0, 5, 8, 25, and 57.
1.35 Consider a 4-bit digital word b3b2b1b0 in a format called signed-magnitude, in which the most significant bit, b3, is interpreted as a sign bit—0 for positive and 1 for negative val-ues. List the values that can be represented by this scheme.
What is peculiar about the representation of zero? For a par-ticular analog-to-digital converter (ADC), each change in b0 corresponds to a 0.5-V change in the analog input. What is the full range of the analog signal that can be represented? What signed-magnitude digital code results for an input of +2.5 V?
For −3.0 V? For +2.7 V? For −2.8 V?
Case v (rad/s) f (Hz) T (s) a 1 × 109 b 1 × 109 c 1 × 10–10 d 60 e 6.28 × 103 f 1 × 10–6 1 3 ---1 5 ---V ˆ 46 Chapter 1 Signals and Amplifiers CHAPTER 1 P ROBL EMS 1.36 Consider an N-bit ADC whose analog input varies between 0 and VFS (where the subscript FS denotes “full scale”).
(a) Show that the least significant bit (LSB) corresponds to a change in the analog signal of This is the resolution of the converter.
(b) Convince yourself that the maximum error in the con-version (called the quantization error) is half the resolution; that is, the quantization error = (c) For VFS = 10 V, how many bits are required to obtain a resolution of 5 mV or better? What is the actual resolution obtained? What is the resulting quantization error?
1.37 Figure P1.37 shows the circuit of an N-bit digital-to-analog converter (DAC). Each of the N bits of the digital word to be converted controls one of the switches. When the bit is 0, the switch is in the position labeled 0; when the bit is 1, the switch is in the position labeled 1. The analog output is the current iO. Vref is a constant reference voltage.
(a) Show that (b) Which bit is the LSB? Which is the MSB?
(c) For Vref = 10 V, R = 5 kΩ, and N = 6, find the maximum value of iO obtained. What is the change in iO resulting from the LSB changing from 0 to 1?
1.38 In compact-disc (CD) audio technology, the audio sig-nal is sampled at 44.1 kHz. Each sample is represented by 16 bits. What is the speed of this system in bits per second?
Section 1.4: Amplifiers 1.39 Various amplifier and load combinations are measured as listed below using rms values. For each, find the voltage, current, and power gains (Av, Ai, and Ap, respectively) both as ratios and in dB: (a) vI = 100 mV, iI = 100 μA, vO = 10 V, RL = 100 Ω (b) v = 10 μV, iI = 100 nA, vO = 2 V, RL = 10 kΩ (c) vI = 1 V, iI = 1 mA, vO = 10 V, RL = 10 Ω 1.40 An amplifier operating from ±3-V supplies provides a 2.2-V peak sine wave across a 100-Ω load when pro-vided with a 0.2-V peak input from which 1.0 mA peak is drawn. The average current in each supply is measured to be 20 mA. Find the voltage gain, current gain, and power gain expressed as ratios and in decibels as well as the supply power, amplifier dissipation, and amplifier efficiency.
1.41 An amplifier using balanced power supplies is known to saturate for signals extending within 1.2 V of either supply.
For linear operation, its gain is 500 V/V. What is the rms value of the largest undistorted sine-wave output available, and input needed, with ±5-V supplies? With ±10-V supplies?
With ±15-V supplies?
1.42 Symmetrically saturating amplifiers, operating in the so-called clipping mode, can be used to convert sine waves to pseudo-square waves. For an amplifier with a small-signal gain of 1000 and clipping levels of ±9 V, what peak value of input sinusoid is needed to produce an output whose extremes are just at the edge of clipping? Clipped 90% of the time?
Clipped 99% of the time?
Section 1.5: Circuit Models for Amplifiers 1.43 Consider the voltage-amplifier circuit model shown in Fig. 1.16(b), in which Av o = 10 V/V under the following conditions: (a) Ri = 10Rs, RL = 10Ro (b) Ri = Rs, RL = Ro (c) Ri = Rs/10, RL = Ro/10 Calculate the overall voltage gain vo/vs in each case, expressed both directly and in decibels.
1.44 An amplifier with 40 dB of small-signal, open-circuit voltage gain, an input resistance of 1 MΩ, and an output resistance of 10 Ω, drives a load of 100 Ω. What voltage and power gains (expressed in dB) would you expect with the load connected? If the amplifier has a peak output-current limitation of 100 mA, what is the rms value of the largest sine-wave input for which an undistorted output is possible?
What is the corresponding output power available?
1.45 A 10-mV signal source having an internal resistance of 100 kΩ is connected to an amplifier for which the input resis-tance is 10 kΩ, the open-circuit voltage gain is 1000 V/V, and the output resistance is 1 kΩ. The amplifier is connected in turn to a 100-Ω load. What overall voltage gain results as VFS 2 N 1 – ( ) ⁄ .
VFS 2 2 N 1 – ( ).
⁄ iO = Vref R -------- b1 2 1 -----b2 2 2 -----. . . + bN 2 N -----+ + ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ Vref b1 0 1 2R 4R 8R 2NR b2 0 1 b3 0 1 bN iO 0 1 Figure P1.37 Problems 47 CHAPTER 1 PR OBLE MS measured from the source internal voltage to the load? Where did all the gain go? What would the gain be if the source was connected directly to the load? What is the ratio of these two gains? This ratio is a useful measure of the benefit the ampli-fier brings.
1.46 A buffer amplifier with a gain of 1 V/V has an input resistance of 1 MΩ and an output resistance of 10 Ω. It is connected between a 1-V, 100-kΩ source and a 100-Ω load.
What load voltage results? What are the corresponding volt-age, current, and power gains (in dB)?
1.47 Consider the cascade amplifier of Example 1.3. Find the overall voltage gain vo/vs obtained when the first and sec-ond stages are interchanged. Compare this value with the result in Example 1.3, and comment.
1.48 You are given two amplifiers, A and B, to connect in cascade between a 10-mV, 100-kΩ source and a 100-Ω load.
The amplifiers have voltage gain, input resistance, and output resistance as follows: for A, 100 V/V, 10 kΩ, 10 kΩ, respec-tively; for B, 1 V/V, 100 kΩ, 100 Ω, respectively. Your prob-lem is to decide how the amplifiers should be connected. To proceed, evaluate the two possible connections between source S and load L, namely, SABL and SBAL. Find the volt-age gain for each both as a ratio and in decibels. Which ampli-fier arrangement is best?
D 1.49 A designer has available voltage amplifiers with an input resistance of 10 kΩ, an output resistance of 1 kΩ, and an open-circuit voltage gain of 10. The signal source has a 10-kΩ resistance and provides a 10-mV rms signal, and it is required to provide a signal of at least 2 V rms to a 1-kΩ load.
How many amplifier stages are required? What is the output voltage actually obtained.
D 1.50 Design an amplifier that provides 0.5 W of signal power to a 100-Ω load resistance. The signal source provides a 30-mV rms signal and has a resistance of 0.5 MΩ. Three types of voltage-amplifier stages are available: (a) A high-input-resistance type with Ri = 1 MΩ, Avo = 10, and Ro = 10 kΩ (b) A high-gain type with Ri = 10 kΩ, Avo = 100, and Ro = 1 kΩ (c) A low-output-resistance type with Ri = 10 kΩ, Av o = 1, and Ro = 20 Ω Design a suitable amplifier using a combination of these stages. Your design should utilize the minimum number of stages and should ensure that the signal level is not reduced below 10 mV at any point in the amplifier chain. Find the load voltage and power output realized.
D 1.51 It is required to design a voltage amplifier to be driven from a signal source having a 10-mV peak amplitude and a source resistance of 10 kΩ to supply a peak output of 3 V across a 1-kΩ load.
(a) What is the required voltage gain from the source to the load?
(b) If the peak current available from the source is 0.1 μA, what is the smallest input resistance allowed? For the design with this value of Ri, find the overall current gain and power gain.
(c) If the amplifier power supply limits the peak value of the output open-circuit voltage to 5 V, what is the largest output resistance allowed?
(d) For the design with Ri as in (b) and Ro as in (c), what is the required value of open-circuit voltage gain of the amplifier?
(e) If, as a possible design option, you are able to increase Ri to the nearest value of the form 1 × 10n Ω and to decrease Ro to the nearest value of the form 1 × 10m Ω, find (i) the input resistance achievable; (ii) the output resistance achiev-able; and (iii) the open-circuit voltage gain now required to meet the specifications.
D 1.52 A voltage amplifier with an input resistance of 10 kΩ, an output resistance of 200 Ω, and a gain of 1000 V/V is connected between a 100-kΩ source with an open-circuit voltage of 10 mV and a 100-Ω load. For this situation: (a) What output voltage results?
(b) What is the voltage gain from source to load?
(c) What is the voltage gain from the amplifier input to the load?
(d) If the output voltage across the load is twice that needed and there are signs of internal amplifier overload, suggest the location and value of a single resistor that would produce the desired output. Choose an arrangement that would cause minimum disruption to an operating circuit. (Hint: Use par-allel rather than series connections.) 1.53 A current amplifier for which Ri = 1 kΩ, Ro = 10 kΩ, and Ais = 100 A/A is to be connected between a 100-mV source with a resistance of 100 kΩ and a load of 1 kΩ. What are the values of current gain io/ii, of voltage gain vo /vs, and of power gain expressed directly and in decibels?
1.54 A transconductance amplifier with Ri = 2 kΩ, Gm = 40 mA/V, and Ro = 20 kΩ is fed with a voltage source having a source resistance of 2 kΩ and is loaded with a 1-kΩ resis-tance. Find the voltage gain realized.
D 1.55 A designer is required to provide, across a 10-kΩ load, the weighted sum, vO = 10v1 + 20v2, of input signals v1 and v2, each having a source resistance of 10 kΩ. She has a number of transconductance amplifiers for which the input and output resistances are both 10 kΩ and Gm = 20 mA/V, together with a selection of suitable resistors. Sketch an appropriate amplifier topology with additional resistors selected to provide the desired result. (Hint: In your design, arrange to add currents.) 1.56 Figure P1.56 shows a transconductance amplifier whose output is fed back to its input. Find the input resistance i.e., vo vi -----RL ∞ = ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ 48 Chapter 1 Signals and Amplifiers CHAPTER 1 P ROBL EMS Rin of the resulting one-port network. (Hint: Apply a test volt-age vx between the two input terminals, and find the current ix drawn from the source. Then, D 1.57 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide a proportional voltage across a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 kΩ to 10 kΩ. Also, the load resistance varies in the range of 1 kΩ to 10 kΩ. The change in load voltage corre-sponding to the specified change in Rs should be 10% at most.
Similarly, the change in load voltage corresponding to the specified change in RL should be limited to 10%. Also, corre-sponding to a 10-mV transducer open-circuit output voltage, the amplifier should provide a minimum of 1 V across the load. What type of amplifier is required? Sketch its circuit model, and specify the values of its parameters. Specify appropriate values for Ri and Ro of the form 1 × 10m Ω.
D 1.58 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a proportional current through a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 kΩ to 10 kΩ. Similarly, the load resistance is known to vary over the range of 1 kΩ to 10 kΩ. The change in load current corresponding to the specified change in Rs is required to be limited to 10%. Similarly, the change in load current corresponding to the specified change in RL should be 10% at most. Also, for a nominal short-circuit output current of the transducer of 10 μA, the amplifier is required to pro-vide a minimum of 1 mA through the load. What type of amplifier is required? Sketch the circuit model of the ampli-fier, and specify values for its parameters. Select appropriate values for Ri and Ro in the form 1 × 10m Ω.
D 1.59 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide a proportional current through a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 kΩ to 10 kΩ. Also, the load resistance is known to vary in the range of 1 kΩ to 10 kΩ. The change in the current supplied to the load corresponding to the specified change in Rs is to be 10% at most. Similarly, the change in load current corresponding to the specified change in RL is to be 10% at most. Also, for a nominal transducer open-circuit output volt-age of 10 mV, the amplifier is required to provide a minimum of 1 mA current through the load. What type of amplifier is required? Sketch the amplifier circuit model, and specify val-ues for its parameters. For Ri and Ro, specify values in the form 1 × 10m Ω.
D 1.60 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a proportional voltage across a load resistor. The equivalent source resistance of the transducer is specified to vary in the range of 1 kΩ to 10 kΩ. Similarly, the load resistance is known to vary in the range of 1 kΩ to 10 kΩ. The change in load voltage corresponding to the specified change in Rs should be 10% at most. Similarly, the change in load voltage corresponding to the specified change in RL is to be limited to 10%. Also, for a nominal transducer short-circuit output cur-rent of 10 μA, the amplifier is required to provide a minimum voltage across the load of 1 V. What type of amplifier is required? Sketch its circuit model, and specify the values of the model parameters. For Ri and Ro, specify appropriate val-ues in the form 1 × 10m Ω.
1.61 For the circuit in Fig. P1.61, show that and Figure P1.61 1.62 An amplifier with an input resistance of 10 kΩ, when driven by a current source of 1 μA and a source resistance of 100 kΩ, has a short-circuit output current of 10 mA and an open-circuit output voltage of 10 V. The device is driving a 4-kΩ load. Give the values of the Rin Figure P1.56 Rin vx ix ⁄ .) ≡ vc vb -----βRL – rπ β 1 + ( )RE + -----------------------------------= ve vb -----RE RE rπ β 1 + ( ) ⁄ [ ] + --------------------------------------------= vb 2 1 RE 1 2 1 2 ve C B ib rp E RL vc bib Problems 49 CHAPTER 1 PR OBLE MS voltage gain, current gain, and power gain expressed as ratios and in decibels?
1.63 Figure P1.63(a) shows two transconductance amplifi-ers connected in a special configuration. Find vo in terms of v1 and v2. Let gm = 100 mA/V and R = 5 kΩ. If v1 = v2 = 1 V, find the value of vo. Also, find vo for the case v1 = 1.01 V and v2 = 0.99 V. (Note: This circuit is called a differential amplifier and is given the symbol shown in Fig. P1.63(b). A particular type of differential amplifier known as an operational ampli-fier will be studied in Chapter 2.) Figure P1.63 1.64 Any linear two-port network including linear amplifi-ers can be represented by one of four possible parameter sets, given in Appendix C. For the voltage amplifier, the most convenient representation is in terms of the g parame-ters. If the amplifier input port is labeled as port 1 and the output port as port 2, its g-parameter representation is described by the two equations: Figure P1.64 shows an equivalent circuit representation of these two equations. By comparing this equivalent circuit to that of the voltage amplifier in Fig. 1.16(a), identify cor-responding currents and voltages as well as the correspon-dence between the parameters of the amplifier equivalent circuit and the g parameters. Hence give the g parameter that corresponds to each of Ri, Av o and Ro. Notice that there is an additional g parameter with no correspondence in the amplifier equivalent circuit. Which one? What does it sig-nify? What assumption did we make about the amplifier that resulted in the absence of this particular g parameter from the equivalent circuit in Fig. 1.16(a)?
Section 1.6: Frequency Response of Amplifiers 1.65 Use the voltage-divider rule to derive the transfer func-tions of the circuits shown in Fig. 1.22, and show that the transfer functions are of the form given at the top of Table 1.2.
1.66 Figure P1.66 shows a signal source connected to the input of an amplifier. Here Rs is the source resistance, and Ri and Ci are the input resistance and input capacitance, respectively, of the amplifier. Derive an expression for and show that it is of the low-pass STC type.
Find the 3-dB frequency for the case Rs = 20 kΩ, Ri = 80 kΩ, and Ci = 5 pF.
Figure P1.66 (a) (b) vo I1 g11V1 g12I2 + = V2 g21V1 g22I2 + = 2 1 V1 V2 1 2 1 2 g12I2 g21V1 g22 1 g11 I1 I2 Figure P1.64 T s ( ) Vo s ( ) Vi s ( ) ⁄ ≡ Vi s ( ) Vs s ( ) ⁄ , 2 1 Vs Rs Ri Ci 1 2 Vi 50 Chapter 1 Signals and Amplifiers CHAPTER 1 P ROBL EMS 1.67 For the circuit shown in Fig. P1.67, find the transfer function and arrange it in the appropri-ate standard form from Table 1.2. Is this a high-pass or a low-pass network? What is its transmission at very high frequen-cies? [Estimate this directly, as well as by letting in your expression for T(s).] What is the corner frequency ω0?
For R1 = 10 kΩ, R2 = 40 kΩ, and C = 0.1 μF, find f0. What is the value of Figure P1.67 D 1.68 It is required to couple a voltage source Vs with a resistance Rs to a load RL via a capacitor C. Derive an expression for the transfer function from source to load (i.e., ), and show that it is of the high-pass STC type.
For Rs = 5 kΩ and RL = 20 kΩ, find the smallest coupling capacitor that will result in a 3-dB frequency no greater than 10 Hz.
1.69 Measurement of the frequency response of an amplifier yields the data in the following table: Provide plausible approximate values for the missing entries.
Also, sketch and clearly label the magnitude frequency response (i.e., provide a Bode plot) for this amplifier.
1.70 Measurement of the frequency response of an amplifier yields the data in the following table: Provide approximate plausible values for the missing table entries. Also, sketch and clearly label the magnitude fre-quency response (Bode plot) of this amplifier.
1.71 The unity-gain voltage amplifiers in the circuit of Fig.
P1.71 have infinite input resistances and zero output resis-tances and thus function as perfect buffers. Convince yourself that the overall gain will drop by 3 dB below the value at dc at the frequency for which the gain of each RC circuit is 1.0 dB down. What is that frequency in terms of CR?
1.72 A manufacturing error causes an internal node of a high-frequency amplifier whose Thévenin-equivalent node resistance is 100 kΩ to be accidentally shunted to ground by a capacitor (i.e., the node is connected to ground through a capacitor). If the measured 3-dB bandwidth of the amplifier is reduced from the expected 6 MHz to 120 kHz, estimate the value of the shunting capacitor. If the original cutoff fre-quency can be attributed to a small parasitic capacitor at the same internal node (i.e., between the node and ground), what would you estimate it to be?
D 1.73 A designer wishing to lower the overall upper 3-dB frequency of a three-stage amplifier to 10 kHz considers shunting one of two nodes: Node A, between the output of the first stage and the input of the second stage, and Node B, between the output of the second stage and the input of the third stage, to ground with a small capacitor. While measur-ing the overall frequency response of the amplifier, she con-nects a capacitor of 1 nF, first to node A and then to node B, lowering the 3-dB frequency from 2 MHz to 150 kHz and 15 kHz, respectively. If she knows that each amplifier stage has an input resistance of 100 kΩ, what output resistance must the driving stage have at node A? At node B? What capacitor value should she connect to which node to solve her design problem most economically?
D 1.74 An amplifier with an input resistance of 100 kΩ and an output resistance of 1 kΩ is to be capacitor-coupled to a 10-kΩ source and a 1-kΩ load. Available capacitors have val-ues only of the form 1 × 10–n F. What are the values of the f (Hz) | T| (dB) ∠ T (°) 0 40 0 100 40 0 1000 104 37 −45 105 20 0 T s ( ) Vo s ( ) Vi s ( ) ⁄ , = s ∞ → T(jω0) ?
R C 1 R2 Vo Vi VL Vs ⁄ f (Hz) 10 102 103 104 105 106 107 | T| (dB) 0 20 37 40 37 20 0 Vo Vi ⁄ Vi Vo Figure P1.71 Problems 51 CHAPTER 1 PR OBLE MS smallest capacitors needed to ensure that the corner frequency associated with each is less than 100 Hz? What actual corner frequencies result? For the situation in which the basic ampli-fier has an open-circuit voltage gain of 100 V/V, find an expression for 1.75 A voltage amplifier has the transfer function Using the Bode plots for low-pass and high-pass STC net-works (Figs. 1.23 and 1.24), sketch a Bode plot for |Av|. Give approximate values for the gain magnitude at f = 10 Hz, 102 Hz, 103 Hz, 104 Hz, 105 Hz, 106 Hz, and 107 Hz. Find the band-width of the amplifier (defined as the frequency range over which the gain remains within 3 dB of the maximum value).
1.76 For the circuit shown in Fig. P1.76 first, evaluate and the corresponding cutoff (corner) frequency. Second, evaluate and the corresponding cutoff frequency. Put each of the transfer functions in the standard form (see Table 1.2), and com-bine them to form the overall transfer function, Provide a Bode magnitude plot for What is the bandwidth between 3-dB cutoff points?
D 1.77 A transconductance amplifier having the equiva-lent circuit shown in Table 1.1 is fed with a voltage source Vs having a source resistance Rs, and its output is connected to a load consisting of a resistance RL in parallel with a capaci-tance CL. For given values of Rs, RL, and CL, it is required to specify the values of the amplifier parameters Ri, Gm, and Ro to meet the following design constraints: (a) At most, x% of the input signal is lost in coupling the sig-nal source to the amplifier (b) The 3-dB frequency of the amplifier is equal to or greater than a specified value f3dB.
(c) The dc gain is equal to or greater than a specified value A0.
Show that these constraints can be met by selecting Find Ri, Ro, and Gm for Rs = 10 kΩ, x = 20%, Ao = 80, RL = 10 kΩ, CL = 10 pF, and f3dB = 3 MHz.
1.78 Use the voltage-divider rule to find the transfer func-tion of the circuit in Fig. P1.78. Show that the transfer function can be made independent of frequency if the condition C1R1 = C2 R2 applies. Under this condition the circuit is called a compensated attenuator and is fre-quently employed in the design of oscilloscope probes. Find the transmission of the compensated attenuator in terms of R1 and R2.
1.79 An amplifier with a frequency response of the type shown in Fig. 1.21 is specified to have a phase shift of magni-tude no greater than 11.4° over the amplifier bandwidth, which extends from 100 Hz to 1 kHz. It has been found that the gain falloff at the low-frequency end is determined by the response of a high-pass STC circuit and that at the high-frequency end it is determined by a low-pass STC circuit.
What do you expect the corner frequencies of these two cir-cuits to be? What is the drop in gain in decibels (relative to the maximum gain) at the two frequencies that define the ampli-fier bandwidth? What are the frequencies at which the drop in gain is 3 dB?
Avo ( ) T s ( ) Vo s ( ) Vs s ( ).
⁄ = Av 100 1 j f 104 --------+ ⎝ ⎠ ⎛ ⎞1 102 jf --------+ ⎝ ⎠ ⎛ ⎞ -----------------------------------------------------= Ti s ( ) Vi s ( ) Vs s ( ) ⁄ = To s ( ) Vo s ( ) Vi s ( ) ⁄ = T s ( ) Ti s ( ) To s ( ) × .
= T(jω) .
R1 1 M Gm 100 mA V C 10 pF 1 C 100 nF 2 Vi Vs R 10 k 2 R 20 k 3 Vo GmVi Figure P1.76 i.e., Vi 1 x 100 ⁄ ( ) – [ ]Vs ≥ ( ).
Vo Vs ⁄ Ri 100 x ---------1 – ⎝ ⎠ ⎛ ⎞Rs ≥ Ro 1 2πf3dBCL 1 RL ⁄ ( ) – ----------------------------------------------≤ Gm A0 1 x 100 ⁄ ( ) – [ ] ⁄ RL Ro || ( ) --------------------------------------------≥ Vo s ( ) Vi s ( ) ⁄ Vo C1 Vi R2 R1 C2 Figure P1.78 CHAPTER 2 Operational Amplifiers Introduction 53 2.1 The Ideal Op Amp 54 2.2 The Inverting Configuration 58 2.3 The Noninverting Configuration 67 2.4 Difference Amplifiers 71 2.5 Integrators and Differentiators 80 2.6 DC Imperfections 88 2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 97 2.8 Large-Signal Operation of Op Amps 102 Summary 107 Problems 108 53 IN THIS CHAPTER YOU WILL LEARN 1. The terminal characteristics of the ideal op amp.
2. How to analyze circuits containing op amps, resistors, and capacitors.
3. How to use op amps to design amplifiers having precise characteristics.
4. How to design more sophisticated op-amp circuits, including summing amplifiers, instrumentation amplifiers, integrators, and differentiators.
5. Important nonideal characteristics of op amps and how these limit the performance of basic op-amp circuits.
Introduction Having learned basic amplifier concepts and terminology, we are now ready to undertake the study of a circuit building block of universal importance: The operational amplifier (op amp).
Op amps have been in use for a long time, their initial applications being primarily in the areas of analog computation and sophisticated instrumentation. Early op amps were constructed from discrete components (vacuum tubes and then transistors, and resistors), and their cost was prohibitively high (tens of dollars). In the mid-1960s the first integrated-circuit (IC) op amp was produced. This unit (the μA 709) was made up of a relatively large number of transistors and resistors all on the same silicon chip. Although its characteristics were poor (by today’s standards) and its price was still quite high, its appearance signaled a new era in electronic cir-cuit design. Electronics engineers started using op amps in large quantities, which caused their price to drop dramatically. They also demanded better-quality op amps. Semiconductor manu-facturers responded quickly, and within the span of a few years, high-quality op amps became available at extremely low prices (tens of cents) from a large number of suppliers.
One of the reasons for the popularity of the op amp is its versatility. As we will shortly see, one can do almost anything with op amps! Equally important is the fact that the IC op amp has characteristics that closely approach the assumed ideal. This implies that it is quite easy to design circuits using the IC op amp. Also, op-amp circuits work at performance levels that are quite close to those predicted theoretically. It is for this reason that we are studying op amps at this early stage. It is expected that by the end of this chapter the reader should be able to design nontrivial circuits successfully using op amps.
As already implied, an IC op amp is made up of a large number (tens or more) of tran-sistors, resistors, and (usually) one capacitor connected in a rather complex circuit. Since 54 Chapter 2 Operational Amplifiers we have not yet studied transistor circuits, the circuit inside the op amp will not be dis-cussed in this chapter. Rather, we will treat the op amp as a circuit building block and study its terminal characteristics and its applications. This approach is quite satisfactory in many op-amp applications. Nevertheless, for the more difficult and demanding applications it is quite useful to know what is inside the op-amp package. This topic will be studied in Chap-ter 12. More advanced applications of op amps will appear in later chapters.
2.1 The Ideal Op Amp 2.1.1 The Op-Amp Terminals From a signal point of view the op amp has three terminals: two input terminals and one output terminal. Figure 2.1 shows the symbol we shall use to represent the op amp. Terminals 1 and 2 are input terminals, and terminal 3 is the output terminal. As explained in Section 1.4, amplifiers require dc power to operate. Most IC op amps require two dc power supplies, as shown in Fig. 2.2. Two terminals, 4 and 5, are brought out of the op-amp package and connected to a pos-itive voltage VCC and a negative voltage −VEE, respectively. In Fig. 2.2(b) we explicitly show the two dc power supplies as batteries with a common ground. It is interesting to note that the refer-ence grounding point in op-amp circuits is just the common terminal of the two power supplies; that is, no terminal of the op-amp package is physically connected to ground. In what follows we will not, for simplicity, explicitly show the op-amp power supplies.
Figure 2.2 The op amp shown connected to dc power supplies.
Figure 2.1 Circuit symbol for the op amp.
V CC V EE V CC V EE 2.1 The Ideal Op Amp 55 In addition to the three signal terminals and the two power-supply terminals, an op amp may have other terminals for specific purposes. These other terminals can include terminals for frequency compensation and terminals for offset nulling; both functions will be explained in later sections. 2.1.2 Function and Characteristics of the Ideal Op Amp We now consider the circuit function of the op amp. The op amp is designed to sense the dif-ference between the voltage signals applied at its two input terminals (i.e., the quantity v2 − v1), multiply this by a number A, and cause the resulting voltage A(v2 − v1) to appear at out-put terminal 3. Thus v3 = A(v2 − v1). Here it should be emphasized that when we talk about the voltage at a terminal we mean the voltage between that terminal and ground; thus v1 means the voltage applied between terminal 1 and ground.
The ideal op amp is not supposed to draw any input current; that is, the signal current into terminal 1 and the signal current into terminal 2 are both zero. In other words, the input impedance of an ideal op amp is supposed to be infinite.
How about the output terminal 3? This terminal is supposed to act as the output termi-nal of an ideal voltage source. That is, the voltage between terminal 3 and ground will always be equal to A(v2 − v1), independent of the current that may be drawn from terminal 3 into a load impedance. In other words, the output impedance of an ideal op amp is supposed to be zero. Putting together all of the above, we arrive at the equivalent circuit model shown in Fig. 2.3. Note that the output is in phase with (has the same sign as) v2 and is out of phase with (has the opposite sign of) v1. For this reason, input terminal 1 is called the inverting input terminal and is distinguished by a “−” sign, while input terminal 2 is called the nonin-verting input terminal and is distinguished by a “+” sign. As can be seen from the above description, the op amp responds only to the difference signal v2 − v1 and hence ignores any signal common to both inputs. That is, if v1 = v2 = 1 V, then the output will (ideally) be zero. We call this property common-mode rejection, and we conclude that an ideal op amp has zero common-mode gain or, equivalently, infinite com-mon-mode rejection. We will have more to say about this point later. For the time being note that the op amp is a differential-input, single-ended-output amplifier, with the lat-ter term referring to the fact that the output appears between terminal 3 and ground.1 1Some op amps are designed to have differential outputs. This topic will not be discussed in this book. Rather, we confine ourselves here to single-ended-output op amps, which constitute the vast majority of commercially available op amps.
2.1 What is the minimum number of terminals required by a single op amp? What is the minimum number of terminals required on an integrated-circuit package containing four op amps (called a quad op amp)?
Ans. 5; 14 EXERCISE 56 Chapter 2 Operational Amplifiers Furthermore, gain A is called the differential gain, for obvious reasons. Perhaps not so obvi-ous is another name that we will attach to A: the open-loop gain. The reason for this name will become obvious later on when we “close the loop” around the op amp and define another gain, the closed-loop gain.
An important characteristic of op amps is that they are direct-coupled or dc amplifiers, where dc stands for direct-coupled (it could equally well stand for direct current, since a direct-coupled amplifier is one that amplifies signals whose frequency is as low as zero). The fact that op amps are direct-coupled devices will allow us to use them in many important applications. Unfortunately, though, the direct-coupling property can cause some serious practical problems, as will be discussed in a later section.
How about bandwidth? The ideal op amp has a gain A that remains constant down to zero frequency and up to infinite frequency. That is, ideal op amps will amplify signals of any frequency with equal gain, and are thus said to have infinite bandwidth.
We have discussed all of the properties of the ideal op amp except for one, which in fact is the most important. This has to do with the value of A. The ideal op amp should have a gain A whose value is very large and ideally infinite. One may justifiably ask: If the gain A is infinite, how are we going to use the op amp? The answer is very simple: In almost all applications the op amp will not be used alone in a so-called open-loop configuration.
Rather, we will use other components to apply feedback to close the loop around the op amp, as will be illustrated in detail in Section 2.2.
For future reference, Table 2.1 lists the characteristics of the ideal op amp.
Figure 2.3 Equivalent circuit of the ideal op amp.
Table 2.1 Characteristics of the Ideal Op Amp 1. Infinite input impedance 2. Zero output impedance 3. Zero common-mode gain or, equivalently, infinite common-mode rejection 4. Infinite open-loop gain A 5. Infinite bandwidth Inverting input Noninverting input Output 2.1 The Ideal Op Amp 57 2.1.3 Differential and Common-Mode Signals The differential input signal vId is simply the difference between the two input signals v1 and v2; that is, (2.1) The common-mode input signal vIcm is the average of the two input signals v1 and v2; namely, (2.2) Equations (2.1) and (2.2) can be used to express the input signals v1 and v2 in terms of their differential and common-mode components as follows: (2.3) and (2.4) These equations can in turn lead to the pictorial representation in Fig. 2.4. Figure 2.4 Representation of the signal sources v1 and v2 in terms of their differential and common-mode components.
vId v2 v1 – = vIcm 1 2 --- v1 v2 + ( ) = v1 vIcm vId 2 ⁄ – = v2 vIcm vId 2 ⁄ + = v1 1 v2 2 vId2 1 2 vIcm vId2 2.2 Consider an op amp that is ideal except that its open-loop gain A = 103. The op amp is used in a feed-back circuit, and the voltages appearing at two of its three signal terminals are measured. In each of the following cases, use the measured values to find the expected value of the voltage at the third ter-minal. Also give the differential and common-mode input signals in each case. (a) v2 = 0 V and v3 = 2 V; (b) v2 = +5 V and v3 = −10 V; (c) v1 = 1.002 V and v2 = 0.998 V; (d) v1 = −3.6 V and v3 = −3.6 V.
Ans. (a) v1 = −0.002 V, vId = 2 mV, vIcm = −1 mV; (b) v1 = +5.01 V, vId = −10 mV, vIcm = 5.005 5 V; (c) v3 = −4 V, vId = −4 mV, vIcm = 1 V; (d) v2 = −3.6036 V, vId = −3.6 mV, vIcm −3.6 V EXERCISES 58 Chapter 2 Operational Amplifiers 2.2 The Inverting Configuration As mentioned above, op amps are not used alone; rather, the op amp is connected to passive components in a feedback circuit. There are two such basic circuit configurations employing an op amp and two resistors: the inverting configuration, which is studied in this section, and the noninverting configuration, which we shall study in the next section.
Figure 2.5 shows the inverting configuration. It consists of one op amp and two resistors R1 and R2. Resistor R2 is connected from the output terminal of the op amp, terminal 3, back to the inverting or negative input terminal, terminal 1. We speak of R2 as applying negative feedback; if R2 were connected between terminals 3 and 2 we would have called this positive feedback.
Note also that R2 closes the loop around the op amp. In addition to adding R2, we have grounded terminal 2 and connected a resistor R1 between terminal 1 and an input signal source with a volt-age vI. The output of the overall circuit is taken at terminal 3 (i.e., between terminal 3 and 2.3 The internal circuit of a particular op amp can be modeled by the circuit shown in Fig. E2.3. Express v3 as a function of v1 and v2. For the case Gm = 10 mA/V, R = 10 kΩ, and μ = 100, find the value of the open-loop gain A.
Ans. v3 = μGmR(v2 − v1); A = 10,000 V/V or 80 dB Figure E2.3 2.2 The Inverting Configuration 59 ground). Terminal 3 is, of course, a convenient point from which to take the output, since the impedance level there is ideally zero. Thus the voltage vO will not depend on the value of the cur-rent that might be supplied to a load impedance connected between terminal 3 and ground.
2.2.1 The Closed-Loop Gain We now wish to analyze the circuit in Fig. 2.5 to determine the closed-loop gain G, defined as We will do so assuming the op amp to be ideal. Figure 2.6(a) shows the equivalent circuit, and the analysis proceeds as follows: The gain A is very large (ideally infinite). If we assume that the circuit is “working” and producing a finite output voltage at terminal 3, then the voltage between the op-amp input terminals should be negligibly small and ideally zero.
Specifically, if we call the output voltage vO, then, by definition, It follows that the voltage at the inverting input terminal (v1) is given by v1 = v2. That is, because the gain A approaches infinity, the voltage v1 approaches and ideally equals v2. We speak of this as the two input terminals “tracking each other in potential.” We also speak of a “virtual short circuit” that exists between the two input terminals. Here the word virtual should be emphasized, and one should not make the mistake of physically shorting terminals 1 and 2 together while analyzing a circuit. A virtual short circuit means that whatever voltage is at 2 will automatically appear at 1 because of the infinite gain A. But terminal 2 happens to be con-nected to ground; thus v2 = 0 and v1 = 0. We speak of terminal 1 as being a virtual ground— that is, having zero voltage but not physically connected to ground. Now that we have determined v1 we are in a position to apply Ohm’s law and find the current i1 through R1 (see Fig. 2.6) as follows: Where will this current go? It cannot go into the op amp, since the ideal op amp has an infinite input impedance and hence draws zero current. It follows that i1 will have to flow through R2 to the low-impedance terminal 3. We can then apply Ohm’s law to R2 and determine vO; that is, Thus, Figure 2.5 The inverting closed-loop configuration.
G vO vI -----≡ v2 v1 – vO A -----0 = = i1 vI v1 – R1 ---------------vI 0 – R1 -------------vI R1 -----= = = vO v1 i1R2 – = 0 = vI R1 -----R2 – vO vI -----R2 R1 -----– = 60 Chapter 2 Operational Amplifiers which is the required closed-loop gain. Figure 2.6(b) illustrates these steps and indicates by the circled numbers the order in which the analysis is performed.
We thus see that the closed-loop gain is simply the ratio of the two resistances R2 and R1.
The minus sign means that the closed-loop amplifier provides signal inversion. Thus if and we apply at the input (vI) a sine-wave signal of 1 V peak-to-peak, then the output vO will be a sine wave of 10 V peak-to-peak and phase-shifted 180° with respect to the input sine wave. Because of the minus sign associated with the closed-loop gain, this config-uration is called the inverting configuration.
Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.
5 6 4 1 3 2 R2 R1 ⁄ = 10 2.2 The Inverting Configuration 61 The fact that the closed-loop gain depends entirely on external passive components (resistors R1 and R2) is very significant. It means that we can make the closed-loop gain as accurate as we want by selecting passive components of appropriate accuracy. It also means that the closed-loop gain is (ideally) independent of the op-amp gain. This is a dra-matic illustration of negative feedback: We started out with an amplifier having very large gain A, and through applying negative feedback we have obtained a closed-loop gain that is much smaller than A but is stable and predictable. That is, we are trading gain for accuracy.
2.2.2 Effect of Finite Open-Loop Gain The points just made are more clearly illustrated by deriving an expression for the closed-loop gain under the assumption that the op-amp open-loop gain A is finite. Figure 2.7 shows the analysis. If we denote the output voltage vO, then the voltage between the two input terminals of the op amp will be Since the positive input terminal is grounded, the voltage at the negative input terminal must be The current i1 through R1 can now be found from The infinite input impedance of the op amp forces the current i1 to flow entirely through R2. The output voltage vO can thus be determined from Collecting terms, the closed-loop gain G is found as (2.5) We note that as A approaches ∞, G approaches the ideal value of Also, from Fig. 2.7 we see that as A approaches ∞, the voltage at the inverting input terminal approaches zero.
This is the virtual-ground assumption we used in our earlier analysis when the op amp was R2 R1 ⁄ vO A.
⁄ vO A.
⁄ – i1 vI vO A ⁄ – ( ) – R1 -------------------------------vI vO A ⁄ + R1 ------------------------= = Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp.
vO vO A -----– i1R2 – = vO A ----- – = vI vO A ⁄ + R1 ------------------------⎝ ⎠ ⎛ ⎞ – R2 G vO vI -----≡ R2 R1 ⁄ – 1 1 R2 R1 ⁄ + ( ) A ⁄ + ----------------------------------------------= R – 2 R1 ⁄ .
62 Chapter 2 Operational Amplifiers assumed to be ideal. Finally, note that Eq. (2.5) in fact indicates that to minimize the dependence of the closed-loop gain G on the value of the open-loop gain A, we should make 2.2.3 Input and Output Resistances Assuming an ideal op amp with infinite open-loop gain, the input resistance of the closed-loop inverting amplifier of Fig. 2.5 is simply equal to R1. This can be seen from Fig. 2.6(b), where Now recall that in Section 1.5 we learned that the amplifier input resistance forms a voltage divider with the resistance of the source that feeds the amplifier. Thus, to avoid the loss of signal strength, voltage amplifiers are required to have high input resistance. In the case of the invert-ing op-amp configuration we are studying, to make Ri high we should select a high value for R1.
However, if the required gain is also high, then R2 could become impractically large (e.g., greater than a few megohms). We may conclude that the inverting configuration suffers from a low input resistance. A solution to this problem is discussed in Example 2.2 below. 1 R2 R1 ----- A + Consider the inverting configuration with R1 = 1 kΩ and R2 = 100 kΩ.
(a) Find the closed-loop gain for the cases A = 103, 104, and 105. In each case determine the percentage error in the magnitude of G relative to the ideal value of (obtained with A = ∞). Also deter-mine the voltage v1 that appears at the inverting input terminal when vI = 0.1 V.
(b) If the open-loop gain A changes from 100,000 to 50,000 (i.e., drops by 50%), what is the correspond-ing percentage change in the magnitude of the closed-loop gain G?
Solution (a) Substituting the given values in Eq. (2.5), we obtain the values given in the following table, where the percentage error ε is defined as The values of v1 are obtained from with vI = 0.1 V.
(b) Using Eq. (2.5), we find that for A = 50,000, |G| = 99.80. Thus a −50% change in the open-loop gain results in a change of only −0.1% in the closed-loop gain!
A |G| ε v1 103 90.83 −9.17% −9.08 mV 104 99.00 −1.00% −0.99 mV 105 99.90 −0.10% −0.10 mV R2 R1 ⁄ ε G R2 R1 ⁄ ( ) – R2 R1 ⁄ ( ) ----------------------------------100 × ≡ v1 = vO A ⁄ – GvI A ⁄ = Example 2.1 Ri vI i1 ----≡ vI vI R1 ⁄ --------------R1 = = R2 R1 ⁄ 2.2 The Inverting Configuration 63 Since the output of the inverting configuration is taken at the terminals of the ideal voltage source A(v2 − v1) (see Fig. 2.6a), it follows that the output resistance of the closed-loop ampli-fier is zero.
Assuming the op amp to be ideal, derive an expression for the closed-loop gain of the circuit shown in Fig. 2.8. Use this circuit to design an inverting amplifier with a gain of 100 and an input resistance of 1 MΩ. Assume that for practical reasons it is required not to use resistors greater than 1 MΩ. Compare your design with that based on the inverting configuration of Fig. 2.5.
Figure 2.8 Circuit for Example 2.2. The circled numbers indicate the sequence of the steps in the analysis.
vO vI ⁄ 4 5 7 6 3 1 2 8 vx x Solution The analysis begins at the inverting input terminal of the op amp, where the voltage is Here we have assumed that the circuit is “working” and producing a finite output voltage vO. Know-ing v1, we can determine the current i1 as follows: Since zero current flows into the inverting input terminal, all of i1 will flow through R2, and thus Now we can determine the voltage at node x: v1 vO – A ---------vO – ∞ ---------0 = = = i1 vI v1 – R1 ---------------vI 0 – R1 -------------vI R1 -----= = = i2 i1 vI R1 -----= = vx v1 i2R2 – 0 vI R1 -----– R2 R2 R1 -----vI – = = = Example 2.2 64 Chapter 2 Operational Amplifiers Example 2.2 continued This in turn enables us to find the current i3: Next, a node equation at x yields i4: Finally, we can determine vO from Thus the voltage gain is given by which can be written in the form Now, since an input resistance of 1 MΩ is required, we select R1 = 1 MΩ. Then, with the limita-tion of using resistors no greater than 1 MΩ, the maximum value possible for the first factor in the gain expression is 1 and is obtained by selecting R2 = 1 MΩ. To obtain a gain of −100, R3 and R4 must be selected so that the second factor in the gain expression is 100. If we select the maximum allowed (in this example) value of 1 MΩ for R4, then the required value of R3 can be calculated to be 10.2 kΩ. Thus this circuit utilizes three 1-MΩ resistors and a 10.2-kΩ resistor. In comparison, if the inverting configuration were used with R1 = 1 MΩ we would have required a feedback resis-tor of 100 MΩ, an impractically large value!
Before leaving this example it is insightful to inquire into the mechanism by which the circuit is able to realize a large voltage gain without using large resistances in the feedback path. Toward that end, observe that because of the virtual ground at the inverting input terminal of the op amp, R2 and R3 are in effect in parallel. Thus, by making R3 lower than R2 by, say, a factor k (i.e., where k > 1), R3 is forced to carry a current k-times that in R2. Thus, while i2 = i1, i3 = ki1 and i4 = (k + 1)i1. It is the current multiplication by a factor of (k + 1) that enables a large voltage drop to develop across R4 and hence a large vO without using a large value for R4. Notice also that the current through R4 is independent of the value of R4. It follows that the circuit can be used as a current amplifier as shown in Fig. 2.9. i3 0 vx – R3 -------------R2 R1R3 ------------vI = = i4 i2 i3 + vI R1 -----R2 R1R3 ------------vI + = = vO vx i4R4 – = R2 R1 -----– vI = vI R1 -----R2 R1R3 ------------vI + ⎝ ⎠ ⎛ ⎞R4 – vO vI ------R2 R1 -----R4 R1 ----- 1 R2 R3 ------+ ⎝ ⎠ ⎛ ⎞ + – = vO vI ------R2 R1 ----- 1 R4 R2 -----R4 R3 -----+ + ⎝ ⎠ ⎛ ⎞ – = iI R2 R3 R4 v1 0 i2 iI i4 R2 R3 i3 iI R2 R3 i4 1 iI Figure 2.9 A current amplifier based on the circuit of Fig. 2.8. The amplifier delivers its output current to R4. It has a current gain of (1 + R2/R3), a zero input resistance, and an infi-nite output resistance. The load (R4), however, must be floating (i.e., neither of its two termi-nals can be connected to ground).
2.2 The Inverting Configuration 65 2.2.4 An Important Application—The Weighted Summer A very important application of the inverting configuration is the weighted-summer cir-cuit shown in Fig. 2.10. Here we have a resistance Rf in the negative-feedback path (as before); but we have a number of input signals v1, v2, . . . , vn each applied to a corre-sponding resistor R1, R2, . . . , Rn, which are connected to the inverting terminal of the op amp. From our previous discussion, the ideal op amp will have a virtual ground appearing D2.4 Use the circuit of Fig. 2.5 to design an inverting amplifier having a gain of −10 and an input resist-ance of 100 kΩ. Give the values of R1 and R2.
Ans. R1 = 100 kΩ; R2 = 1 MΩ 2.5 The circuit shown in Fig. E2.5(a) can be used to implement a transresistance amplifier (see Table 1.1 in Section 1.5). Find the value of the input resistance Ri, the transresistance Rm, and the output resistance Ro of the transresistance amplifier. If the signal source shown in Fig. E2.5(b) is connected to the input of the transresistance amplifier, find its output voltage.
Ans. Ri = 0; Rm = −10 kΩ; Ro = 0; vO = −5 V Figure E2.5 2.6 For the circuit in Fig. E2.6 determine the values of v1, i1, i2, vO, iL, and iO. Also determine the voltage gain current gain and power gain Ans. 0 V; 1 mA; 1 mA; −10 V; −10 mA; −11 mA; −10 V/V (20 dB), −10 A/A (20 dB); 100 W/W (20 dB) vO vI ⁄ , iL iI ⁄ , PO PI ⁄ .
iL v1 vO 10 k 1 k 1 k i2 iO i1 1 V Figure E2.6 EXERCISES 66 Chapter 2 Operational Amplifiers at its negative input terminal. Ohm’s law then tells us that the currents i1, i2, . . . , in are given by All these currents sum together to produce the current i; that is, (2.6) will be forced to flow through Rf (since no current flows into the input terminals of an ideal op amp). The output voltage vO may now be determined by another application of Ohm’s law, Thus, (2.7) That is, the output voltage is a weighted sum of the input signals v1, v2, . . . , vn. This circuit is therefore called a weighted summer. Note that each summing coefficient may be inde-pendently adjusted by adjusting the corresponding “feed-in” resistor (R1 to Rn). This nice property, which greatly simplifies circuit adjustment, is a direct consequence of the virtual ground that exists at the inverting op-amp terminal. As the reader will soon come to appreci-ate, virtual grounds are extremely “handy.” In the weighted summer of Fig. 2.10 all the sum-ming coefficients must be of the same sign. The need occasionally arises for summing signals with opposite signs. Such a function can be implemented, however, using two op amps as shown in Fig. 2.11. Assuming ideal op amps, it can be easily shown that the output voltage is given by (2.8) Figure 2.10 A weighted summer.
i1 v1 R1 -----i2 , v2 R2 -----. . . in , , vn Rn -----= = = 0 i i1 i2 … in + + + = vO 0 iRf – iRf – = = vO Rf R1 -----v1 Rf R2 -----v2 … Rf Rn -----vn + + + ⎝ ⎠ ⎛ ⎞ – = vO v1 Ra R1 -----⎝ ⎠ ⎛ ⎞Rc Rb -----⎝ ⎠ ⎛ ⎞ v2 Ra R2 -----⎝ ⎠ ⎛ ⎞Rc Rb -----⎝ ⎠ ⎛ ⎞ v3 Rc R3 -----⎝ ⎠ ⎛ ⎞ – v4 Rc R4 -----⎝ ⎠ ⎛ ⎞ – + = 2.3 The Noninverting Configuration 67 2.3 The Noninverting Configuration The second closed-loop configuration we shall study is shown in Fig. 2.12. Here the input signal vI is applied directly to the positive input terminal of the op amp while one terminal of R1 is connected to ground. 2.3.1 The Closed-Loop Gain Analysis of the noninverting circuit to determine its closed-loop gain is illustrated in Fig. 2.13. Again the order of the steps in the analysis is indicated by circled numbers.
Assuming that the op amp is ideal with infinite gain, a virtual short circuit exists between its two input terminals. Hence the difference input signal is Thus the voltage at the inverting input terminal will be equal to that at the noninverting input terminal, which is the applied voltage vI. The current through R1 can then be determined as . Because of the infinite input impedance of the op amp, this current will flow through R2, as shown in Fig. 2.13. Now the output voltage can be determined from Figure 2.11 A weighted summer capable of implementing summing coefficients of both signs.
v1 Ra R1 Rb v2 R2 v3 vO R3 v4 R4 Rc vO vI ⁄ ( ) vId vO A -----0 for A ∞ = = = vI R1 ⁄ vO vI vI R1 -----⎝ ⎠ ⎛ ⎞R2 + = D2.7 Design an inverting op-amp circuit to form the weighted sum vO of two inputs v1 and v2. It is required that vO = − (v1 + 5v2). Choose values for R1, R2, and Rf so that for a maximum output volt-age of 10 V the current in the feedback resistor will not exceed 1 mA.
Ans. A possible choice: R1 = 10 kΩ, R2 = 2 kΩ, and Rf = 10 kΩ D2.8 Use the idea presented in Fig. 2.11 to design a weighted summer that provides Ans. A possible choice: R1 = 5 kΩ, R2 = 10 kΩ, Ra = 10 kΩ, Rb = 10 kΩ, R3 = 2.5 kΩ, Rc = 10 kΩ. vO 2v1 v2 4v3 – + = EXERCISES 68 Chapter 2 Operational Amplifiers which yields (2.9) Further insight into the operation of the noninverting configuration can be obtained by considering the following: Since the current into the op-amp inverting input is zero, the cir-cuit composed of R1 and R2 acts in effect as a voltage divider feeding a fraction of the output voltage back to the inverting input terminal of the op amp; that is, (2.10) Then the infinite op-amp gain and the resulting virtual short circuit between the two input termi-nals of the op amp forces this voltage to be equal to that applied at the positive input terminal; thus, which yields the gain expression given in Eq. (2.9).
This is an appropriate point to reflect further on the action of the negative feedback present in the noninverting circuit of Fig. 2.12. Let vI increase. Such a change in vI will cause vId to increase, and vO will correspondingly increase as a result of the high (ideally infinite) gain of the op amp. However, a fraction of the increase in vO will be fed back to the inverting input terminal of the op amp through the (R1, R2) voltage divider. The result of this feedback will be to counter-act the increase in vId, driving vId back to zero, albeit at a higher value of vO that corresponds to the increased value of vI. This degenerative action of negative feedback gives it the alternative name degenerative feedback. Finally, note that the argument above applies equally well if vI decreases. A formal and detailed study of feedback is presented in Chapter 10. Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in the analysis is indicated by the circled numbers.
Figure 2.12 The noninverting configuration.
vO vI R2 R1 vId 0 V vI vO R2 vI R1 R1 vI R1 vI vI vI 1 R2 R1 0 3 5 2 1 4 6 vO vI -----1 R2 R1 -----+ = v1 vO R1 R1 R2 + -----------------⎝ ⎠ ⎛ ⎞ = vO R1 R1 R2 + -----------------⎝ ⎠ ⎛ ⎞ vI = 2.3 The Noninverting Configuration 69 2.3.2 Effect of Finite Open-Loop Gain As we have done for the inverting configuration, we now consider the effect of the finite op-amp open-loop gain A on the gain of the noninverting configuration. Assuming the op amp to be ideal except for having a finite open-loop gain A, it can be shown that the closed-loop gain of the noninverting amplifier circuit of Fig. 2.12 is given by (2.11) Observe that the denominator is identical to that for the case of the inverting configuration (Eq. 2.5). This is no coincidence; it is a result of the fact that both the inverting and the non-inverting configurations have the same feedback loop, which can be readily seen if the input signal source is eliminated (i.e., short-circuited). The numerators, however, are different, for the numerator gives the ideal or nominal closed-loop gain ( for the inverting con-figuration, and for the noninverting configuration). Finally, we note (with reas-surance) that the gain expression in Eq. (2.11) reduces to the ideal value for A = ∞. In fact, it approximates the ideal value for This is the same condition as in the inverting configuration, except that here the quantity on the right-hand side is the nominal closed-loop gain.The expressions for the actual and ideal values of the closed-loop gain G in Eqs. (2.11) and (2.9), respectively, can be used to deter-mine the percentage error in G resulting from the finite op-amp gain A as Percent gain error (2.12) Thus, as an example, if an op amp with an open-loop gain of 1000 is used to design a nonin-verting amplifier with a nominal closed-loop gain of 10, we would expect the closed-loop gain to be about 1% below the nominal value.
2.3.3 Input and Output Resistance The gain of the noninverting configuration is positive—hence the name noninverting. The input impedance of this closed-loop amplifier is ideally infinite, since no current flows into the positive input terminal of the op amp. The output of the noninverting amplifier is taken at the terminals of the ideal voltage source A(v2 − v1) (see the op-amp equivalent circuit in Fig. 2.3), thus the output resistance of the noninverting configuration is zero.
2.3.4 The Voltage Follower The property of high input impedance is a very desirable feature of the noninverting configura-tion. It enables using this circuit as a buffer amplifier to connect a source with a high imped-ance to a low-impedance load. We have discussed the need for buffer amplifiers in Section 1.5.
In many applications the buffer amplifier is not required to provide any voltage gain; rather, it is used mainly as an impedance transformer or a power amplifier. In such cases we may make R2 = 0 and R1 = ∞ to obtain the unity-gain amplifier shown in Fig. 2.14(a). This circuit is commonly referred to as a voltage follower, since the output “follows” the input. In the ideal case, vO = vI, Rin = ∞, Rout = 0, and the follower has the equivalent circuit shown in Fig. 2.14(b). G vO vI -----≡ 1 R2 R1 ⁄ ( ) + 1 1 R2 R1 ⁄ ( ) + A -----------------------------+ ---------------------------------------= R2 R1 ⁄ – 1 R2 R1 ⁄ + A 1 > R2 R1 -----+ > > 1 R2 R1 ⁄ ( ) + A 1 R2 R1 ⁄ ( ) + + ----------------------------------------100 × – = 70 Chapter 2 Operational Amplifiers Since in the voltage-follower circuit the entire output is fed back to the inverting input, the circuit is said to have 100% negative feedback. The infinite gain of the op amp then acts to make vId = 0 and hence vO = vI. Observe that the circuit is elegant in its simplicity! Since the noninverting configuration has a gain greater than or equal to unity, depending on the choice of , some prefer to call it “a follower with gain.” Figure 2.14 (a) The unity-gain buffer or follower amplifier. (b) Its equivalent circuit model.
vO vI vI (a) 1 vI vI vO (b ) R2 R1 ⁄ 2.9 Use the superposition principle to find the output voltage of the circuit shown in Fig. E2.9.
Ans. vO = 6v1 + 4v2 2.10 If in the circuit of Fig. E2.9 the 1-kΩ resistor is disconnected from ground and connected to a third signal source v3, use superposition to determine vO in terms of v1, v2, and v3.
Ans. vO = 6v1 + 4v2 − 9v3 D2.11 Design a noninverting amplifier with a gain of 2. At the maximum output voltage of 10 V the cur-rent in the voltage divider is to be 10 μA.
Ans. R1 = R2 = 0.5 MΩ 2.12 (a) Show that if the op amp in the circuit of Fig. 2.12 has a finite open-loop gain A, then the closed-loop gain is given by Eq. (2.11). (b) For R1 = 1 kΩ and R2 = 9 kΩ find the percentage deviation ε of the closed-loop gain from the ideal value of for the cases A = 103, 104, and 105.
For vI = 1 V, find in each case the voltage between the two input terminals of the op amp.
Ans. ε = −1%, − 0.1%, − 0.01%; v2 − v1 = 9.9 mV, 1 mV, 0.1 mV Figure E2.9 1 R2 R1 ⁄ + ( ) EXERCISES 2.4 Difference Amplifiers 71 2.4 Difference Amplifiers Having studied the two basic configurations of op-amp circuits together with some of their direct applications, we are now ready to consider a somewhat more involved but very important application. Specifically, we shall study the use of op amps to design difference or differential amplifiers.2 A difference amplifier is one that responds to the difference between the two signals applied at its input and ideally rejects signals that are common to the two inputs. The representation of signals in terms of their differential and common-mode com-ponents was given in Fig. 2.4. It is repeated here in Fig. 2.15 with slightly different symbols to serve as the input signals for the difference amplifiers we are about to design. Although ideally the difference amplifier will amplify only the differential input signal vId and reject completely the common-mode input signal vIcm, practical circuits will have an output voltage vO given by (2.13) where Ad denotes the amplifier differential gain and Acm denotes its common-mode gain (ide-ally zero). The efficacy of a differential amplifier is measured by the degree of its rejection of common-mode signals in preference to differential signals. This is usually quantified by a measure known as the common-mode rejection ratio (CMRR), defined as (2.14) 2The terms difference and differential are usually used to describe somewhat different amplifier types. For our purposes at this point, the distinction is not sufficiently significant. We will be more precise near the end of this section.
vO AdvId AcmvIcm + = CMRR 20 log Ad Acm ------------= 2.13 For the circuit in Fig. E2.13 find the values of iI, v1, i1, i2, vO, iL, and iO. Also find the voltage gain the current gain and the power gain Ans. 0; 1 V; 1 mA; 1 mA; 10 V; 10 mA; 11 mA; 10 V/V (20 dB); ∞; ∞ 2.14 It is required to connect a transducer having an open-circuit voltage of 1 V and a source resistance of 1 MΩ to a load of 1-kΩ resistance. Find the load voltage if the connection is done (a) directly and (b) through a unity-gain voltage follower.
Ans. (a) 1 mV; (b) 1 V vO vI, ⁄ iL iI ⁄ , PL PI ⁄ .
iL v1 vO 9 k 1 k 1 k i2 i1 iO iI vI 1 V Figure E2.13 72 Chapter 2 Operational Amplifiers The need for difference amplifiers arises frequently in the design of electronic systems, espe-cially those employed in instrumentation. As a common example, consider a transducer pro-viding a small (e.g., 1 mV) signal between its two output terminals while each of the two wires leading from the transducer terminals to the measuring instrument may have a large interference signal (e.g., 1 V) relative to the circuit ground. The instrument front end obvi-ously needs a difference amplifier.
Before we proceed any further we should address a question that the reader might have: The op amp is itself a difference amplifier; why not just use an op amp? The answer is that the very high (ideally infinite) gain of the op amp makes it impossible to use by itself. Rather, as we did before, we have to devise an appropriate feedback network to connect to the op amp to create a circuit whose closed-loop gain is finite, predictable, and stable.
2.4.1 A Single-Op-Amp Difference Amplifier Our first attempt at designing a difference amplifier is motivated by the observation that the gain of the noninverting amplifier configuration is positive, while that of the inverting configuration is negative, . Combining the two configurations together is then a step in the right direction⎯namely, getting the difference between two input signals.
Of course, we have to make the two gain magnitudes equal in order to reject common-mode signals. This, however, can be easily achieved by attenuating the positive input signal to reduce the gain of the positive path from to . The resulting circuit would then look like that shown in Fig. 2.16, where the attenuation in the positive input path is achieved by the voltage divider (R3, R4). The proper ratio of this voltage divider can be determined from which can be put in the form This condition is satisfied by selecting (2.15) vIcm vId2 vId2 vId vI2 vI1 vIcm (vI1 vI2) vI1 vIcm vId2 vI2 vIcm vId2 1 2 Figure 2.15 Representing the input signals to a differential amplifier in terms of their differential and common-mode components.
1 R2 R1 ⁄ + ( ), R2 R1 ⁄ – ( ) 1 R2 R1 ⁄ + ( ) R2 R1 ⁄ ( ) R4 R4 R3 + ----------------- 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ R2 R1 -----= R4 R4 R3 + -----------------R2 R2 R1 + -----------------= R4 R3 -----R2 R1 -----= 2.4 Difference Amplifiers 73 This completes our work. However, we have perhaps proceeded a little too fast! Let’s step back and verify that the circuit in Fig. 2.16 with R3 and R4 selected according to Eq. (2.15) does in fact function as a difference amplifier. Specifically, we wish to determine the output voltage vO in terms of vI1 and vI 2. Toward that end, we observe that the circuit is linear, and thus we can use superposition.
To apply superposition, we first reduce vI 2 to zero⎯that is, ground the terminal to which vI2 is applied⎯and then find the corresponding output voltage, which will be due entirely to vI1. We denote this output voltage vO1. Its value may be found from the circuit in Fig. 2.17(a), which we recognize as that of the inverting configuration. The existence of R3 and R4 does not affect the gain expression, since no current flows through either of them.
Thus, Next, we reduce vI1 to zero and evaluate the corresponding output voltage vO2. The circuit will now take the form shown in Fig. 2.17(b), which we recognize as the noninverting con-figuration with an additional voltage divider, made up of R3 and R4, connected to the input vI2. The output voltage vO2 is therefore given by where we have utilized Eq. (2.15).
The superposition principle tells us that the output voltage vO is equal to the sum of vO1 and vO2. Thus we have (2.16) Thus, as expected, the circuit acts as a difference amplifier with a differential gain Ad of (2.17) Of course this is predicated on the op amp being ideal and furthermore on the selection of R3 and R4 so that their ratio matches that of R1 and R2 (Eq. 2.15). To make this matching requirement a little easier to satisfy, we usually select vI1 vI2 Figure 2.16 A difference amplifier.
vO1 R2 R1 -----vI1 – = vO2 vI2 R4 R3 R4 + ----------------- 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ R2 R1 -----vI2 = = vO R2 R1 ----- vI2 vI1 – ( ) R2 R1 -----vId = = Ad R2 R1 -----= 74 Chapter 2 Operational Amplifiers Let’s next consider the circuit with only a common-mode signal applied at the input, as shown in Fig. 2.18. The figure also shows some of the analysis steps. Thus, (2.18) The output voltage can now be found from Substituting i2 = i1 and for i1 from Eq. (2.18), Thus, (2.19) For the design with the resistor ratios selected according to Eq. (2.15), we obtain as expected. Note, however, that any mismatch in the resistance ratios can make Acm nonzero, and hence CMRR finite. In addition to rejecting common-mode signals, a difference amplifier is usually required to have a high input resistance. To find the input resistance between the two input terminals Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.
vI1 vI2 R3 R1 and R4 R2 = = i1 1 R1 ----- vIcm R4 R4 R3 + -----------------vIcm – = vIcm R3 R4 R3 + ----------------- 1 R1 -----= vO R4 R4 R3 + -----------------vIcm i2R2 – = vO R4 R4 R3 + -----------------vIcm R2 R1 -----R3 R4 R3 + -----------------vIcm – = R4 R4 R3 + ----------------- 1 R2 R1 ----- R3 R4 -----– ⎝ ⎠ ⎛ ⎞vIcm = Acm vO vIcm --------≡ R4 R4 R3 + -----------------⎝ ⎠ ⎛ ⎞1 R2 R1 ----- R3 R4 -----– ⎝ ⎠ ⎛ ⎞ = Acm 0 = 2.4 Difference Amplifiers 75 (i.e., the resistance seen by vId), called the differential input resistance Rid, consider Fig. 2.19.
Here we have assumed that the resistors are selected so that and Now Since the two input terminals of the op amp track each other in potential, we may write a loop equation and obtain Thus, (2.20) Note that if the amplifier is required to have a large differential gain , then R1 of necessity will be relatively small and the input resistance will be correspondingly low, a drawback of this circuit. Another drawback of the circuit is that it is not easy to vary the dif-ferential gain of the amplifier. Both of these drawbacks are overcome in the instrumentation amplifier discussed next. Figure 2.18 Analysis of the difference amplifier to determine its common-mode gain vO i1 R2 R4 R1 R3 i2 vIcm vIcm R4 R4 R3 Acm vO vIcm ⁄ .
≡ R3 R1 = R4 R2 = Rid vId iI ------≡ vId R1iI 0 R1iI + + = Rid 2R1 = R2 R1 ⁄ ( ) vId Rid I I Figure 2.19 Finding the input resis-tance of the difference amplifier for the case R3 = R1 and R4 = R2.
76 Chapter 2 Operational Amplifiers 2.4.2 A Superior Circuit—The Instrumentation Amplifier The low-input-resistance problem of the difference amplifier of Fig. 2.16 can be solved by using voltage followers to buffer the two input terminals; that is, a voltage follower of the type in Fig. 2.14 is connected between each input terminal and the corresponding input terminal of the difference amplifier. However, if we are going to use two additional op amps, we should ask the question: Can we get more from them than just impedance buffering? An obvious answer would be that we should try to get some voltage gain. It is especially interesting that we can achieve this without com-promising the high input resistance simply by using followers with gain rather than unity-gain fol-lowers. Achieving some or indeed the bulk of the required gain in this new first stage of the (a) R1 R2 R1 X vI1 R2 R3 R3 R4 vI2 1 R2 R1 vI1 1 R2 R1 A1 R4 vI2 vO A2 A3 Figure 2.20 A popular circuit for an instrumentation amplifier. (a) Initial approach to the circuit (b) The circuit in (a) with the connection between node X and ground removed and the two resistors R1 and R1 lumped together. This simple wiring change dramatically improves performance. (c) Analysis of the circuit in (b) assuming ideal op amps.
2.15 Consider the difference-amplifier circuit of Fig. 2.16 for the case R1 = R3 = 2 kΩ and R2 = R4 = 200 kΩ. (a) Find the value of the differential gain Ad. (b) Find the value of the differential input resistance Rid and the output resistance Ro. (c) If the resistors have 1% tolerance (i.e., each can be within ±1% of its nominal value), use Eq. (2.19) to find the worst-case common-mode gain Acm and hence the corresponding value of CMRR.
Ans. (a) 100 V/V (40 dB); (b) 4 kΩ, 0 Ω; (c) 0.04 V/V, 68 dB D2.16 Find values for the resistances in the circuit of Fig. 2.16 so that the circuit behaves as a difference amplifier with an input resistance of 20 kΩ and a gain of 10.
Ans. R1 = R3 = 10 kΩ; R2 = R4 = 100 kΩ EXERCISES 2.4 Difference Amplifiers 77 differential amplifier eases the burden on the difference amplifier in the second stage, leaving it to its main task of implementing the differencing function and thus rejecting common-mode signals.
The resulting circuit is shown in Fig. 2.20(a). It consists of two stages in cascade. The first stage is formed by op amps A1 and A2 and their associated resistors, and the second stage is the by-now-familiar difference amplifier formed by op amp A3 and its four associated resistors.
Observe that as we set out to do, each of A1 and A2 is connected in the noninverting configura-tion and thus realizes a gain of . It follows that each of vI1 and vI2 is amplified by this factor, and the resulting amplified signals appear at the outputs of A1 and A2, respectively.
The difference amplifier in the second stage operates on the difference signal = and provides at its output Thus the differential gain realized is (2.21) (b) vI1 vI2 A1 R2 2R1 A2 R3 R4 A3 vO R4 R3 R2 (c) vI1 vI2 R2 R3 R4 A3 A2 A1 vI1 vI2 0 0 vId/2R1 vId/2R1 R2 (vI2 vI1) vId 2R1 vId R3 R4 2R1 0 V 0 V vId 2R1 2R2 1 vO1 vO2 vO R4 R3 vId R2 R1 1 Figure 2.20 (Continued) 1 R2 R1 ⁄ + ( ) 1 R2 R1 ⁄ + ( ) vI2 vI1 – ( ) 1 R2 R1 ⁄ + ( )vId vO R4 R3 ----- 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞vId = Ad R4 R3 -----⎝ ⎠ ⎛ ⎞ = 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ 78 Chapter 2 Operational Amplifiers The common-mode gain will be zero because of the differencing action of the second-stage amplifier.
The circuit in Fig. 2.20(a) has the advantage of very high (ideally infinite) input resis-tance and high differential gain. Also, provided A1 and A2 and their corresponding resistors are matched, the two signal paths are symmetric⎯a definite advantage in the design of a dif-ferential amplifier. The circuit, however, has three major disadvantages: 1. The input common-mode signal vIcm is amplified in the first stage by a gain equal to that experienced by the differential signal vId. This is a very serious issue, for it could result in the signals at the outputs of A1 and A3 being of such large magnitudes that the op amps saturate (more on op-amp saturation in Section 2.8). But even if the op amps do not saturate, the difference amplifier of the second stage will now have to deal with much larger common-mode signals, with the result that the CMRR of the overall amplifier will inevitably be reduced.
2. The two amplifier channels in the first stage have to be perfectly matched, otherwise a spurious signal may appear between their two outputs. Such a signal would get amplified by the difference amplifier in the second stage.
3. To vary the differential gain Ad, two resistors have to be varied simultaneously, say the two resistors labeled R1. At each gain setting the two resistors have to be perfectly matched: a difficult task.
All three problems can be solved with a very simple wiring change: Simply disconnect the node between the two resistors labeled R1, node X, from ground. The circuit with this small but functionally profound change is redrawn in Fig. 2.20(b), where we have lumped the two resistors (R1 and R1) together into a single resistor (2R1).
Analysis of the circuit in Fig. 2.20(b), assuming ideal op amps, is straightforward, as is illustrated in Fig. 2.20(c). The key point is that the virtual short circuits at the inputs of op amps A1 and A2 cause the input voltages vI1 and vI2 to appear at the two terminals of resistor (2R1). Thus the differential input voltage vI2 − vI1 ≡ vId appears across 2R1 and causes a current to flow through 2R1 and the two resistors labeled R2. This current in turn pro-duces a voltage difference between the output terminals of A1 and A2 given by The difference amplifier formed by op amp A3 and its associated resistors senses the voltage difference (vO2 − vO1) and provides a proportional output voltage vO : Thus the overall differential voltage-gain is given by (2.22) Observe that proper differential operation does not depend on the matching of the two resistors labeled R2. Indeed, if one of the two is of different value, say R2 ′, the expression for Ad becomes (2.23) i vId 2R1 ⁄ = vO2 vO1 – 1 2R2 2R1 ---------+ ⎝ ⎠ ⎛ ⎞vId = vO R4 R3 ----- vO2 vO1 – ( ) = R4 R3 ----- 1 R2 R1 ------+ ⎝ ⎠ ⎛ ⎞vId = Ad vO vId ------≡ R4 R3 ----- 1 R2 R1 ------+ ⎝ ⎠ ⎛ ⎞ = Ad R4 R3 -----= 1 R2 R′ 2 + 2R1 -------------------+ ⎝ ⎠ ⎛ ⎞ 2.4 Difference Amplifiers 79 Consider next what happens when the two input terminals are connected together to a common-mode input voltage vIcm. It is easy to see that an equal voltage appears at the negative input terminals of A1 and A2, causing the current through 2R1 to be zero. Thus there will be no current flowing in the R2 resistors, and the voltages at the output terminals of A1 and A2 will be equal to the input (i.e., vIcm).
Thus the first stage no longer amplifies vIcm; it simply propagates vIcm to its two output terminals, where they are subtracted to produce a zero common-mode output by A3. The difference amplifier in the second stage, however, now has a much improved situation at its input: The difference signal has been amplified by while the common-mode voltage remained unchanged.
Finally, we observe from the expression in Eq. (2.22) that the gain can be varied by changing only one resistor, 2R1. We conclude that this is an excellent differential amplifier circuit and is widely employed as an instrumentation amplifier; that is, as the input amplifier used in a variety of electronic instruments.
1 R2 R1 ⁄ + ( ) Design the instrumentation amplifier circuit in Fig. 2.20(b) to provide a gain that can be varied over the range of 2 to 1000 utilizing a 100-kΩ variable resistance (a potentiometer, or “pot” for short).
Solution It is usually preferable to obtain all the required gain in the first stage, leaving the second stage to perform the task of taking the difference between the outputs of the first stage and thereby rejecting the common-mode signal. In other words, the second stage is usually designed for a gain of 1. Adopting this approach, we select all the second-stage resistors to be equal to a practically convenient value, say 10 kΩ. The problem then reduces to designing the first stage to realize a gain adjustable over the range of 2 to 1000. Implementing 2R1 as the series combination of a fixed resistor R1f and the vari-able resistor R1v obtained using the 100-kΩ pot (Fig. 2.21), we can write Thus, and These two equations yield R1f = 100.2 Ω and R2 = 50.050 kΩ. Other practical values may be selected; for instance, R1f = 100 Ω and R2 = 49.9 kΩ (both values are available as standard 1%-tolerance metal-film resistors; see Appendix H) results in a gain covering approximately the required range.
1 2R2 R1f R1 v + ---------------------+ 2 to 1000 = 1 2R2 R1f ---------+ = 1000 1 2R2 R1f 100 kΩ + --------------------------------+ 2 = R1v 2R1 R1f 100 k pot Figure 2.21 To make the gain of the circuit in Fig. 2.20(b) variable, 2R1 is implemented as the series combination of a fixed resistor R1f and a variable resistor R1v. Resistor R1f ensures that the maximum available gain is limited.
Example 2.3 80 Chapter 2 Operational Amplifiers 2.5 Integrators and Differentiators The op-amp circuit applications we have studied thus far utilized resistors in the op-amp feedback path and in connecting the signal source to the circuit, that is, in the feed-in path.
As a result, circuit operation has been (ideally) independent of frequency. By allowing the use of capacitors together with resistors in the feedback and feed-in paths of op-amp cir-cuits, we open the door to a very wide range of useful and exciting applications of the op amp. We begin our study of op-amp–RC circuits by considering two basic applications, namely, signal integrators and differentiators.
2.5.1 The Inverting Configuration with General Impedances To begin with, consider the inverting closed-loop configuration with impedances Z1(s) and Z2(s) replacing resistors R1 and R2, respectively. The resulting circuit is shown in Fig. 2.22 and, for an ideal op amp, has the closed-loop gain or, more appropriately, the closed-loop transfer function (2.24) As explained in Section 1.6, replacing s by jω provides the transfer function for physical fre-quencies ω, that is, the transmission magnitude and phase for a sinusoidal input signal of frequency ω. Figure 2.22 The inverting configuration with general impedances in the feedback and the feed-in paths.
2.17 Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +5 V (dc) and a differential input signal of 10-mV-peak sine wave. Let (2R1) = 1 kΩ, R2 = 0.5 MΩ, and R3 = R4 = 10 kΩ. Find the voltage at every node in the circuit.
Ans. vI1 = 5 − 0.005 sin ωt; vI2 = 5 + 0.005 sin ωt; v– (op amp A1) = 5 − 0.005 sin ωt; v– (op amp A2) = 5 + 0.005 sin ωt; vO1 = 5 − 5.005 sin ωt; vO2 = 5 + 5.005 sin ωt; v– (A3) = v + (A3) = 2.5 + 2.5025 sin ωt; vO = 10.01 sin ωt (all in volts) EXERCISE V o s ( ) V i s ( ) -------------−Z2 s ( ) Z1 s ( ) ------------= 2.5 Integrators and Differentiators 81 For the circuit in Fig. 2.23, derive an expression for the transfer function Show that the transfer function is that of a low-pass STC circuit. By expressing the transfer function in the stan-dard form shown in Table 1.2 on page 34, find the dc gain and the 3-dB frequency. Design the circuit to obtain a dc gain of 40 dB, a 3-dB frequency of 1 kHz, and an input resistance of 1 kΩ. At what fre-quency does the magnitude of transmission become unity? What is the phase angle at this frequency?
Solution To obtain the transfer function of the circuit in Fig. 2.23, we substitute in Eq. (2.24), Z1 = R1 and Since Z2 is the parallel connection of two components, it is more convenient to work in terms of Y2; that is, we use the following alternative form of the transfer function: and substitute Z1 = R1 and to obtain This transfer function is of first order, has a finite dc gain and has zero gain at infinite frequency. Thus it is the transfer function of a low-pass STC network and can be expressed in the standard form of Table 1.2 as follows: from which we find the dc gain K to be V o s ( ) V i s ( ) ⁄ .
Figure 2.23 Circuit for Example 2.4.
Z2 R2|| 1 sC2 ⁄ ( ).
= V o s ( ) V i s ( ) -------------1 Z1 s ( )Y2 s ( ) --------------------------– = Y2 s ( ) 1 R2 ⁄ ( ) sC2 + = V o s ( ) V i s ( ) -------------1 R1 R2 -----sC2R1 + ---------------------------– = at s 0 V o V i ⁄ , R2 R1 ⁄ – = = ( ), V o s ( ) V i s ( ) -------------R2 R1 ⁄ – 1 sC2R2 + ------------------------= K = R2 R1 -----– Example 2.4 82 Chapter 2 Operational Amplifiers 2.5.2 The Inverting Integrator By placing a capacitor in the feedback path (i.e., in place of Z2 in Fig. 2.22) and a resistor at the input (in place of Z1), we obtain the circuit of Fig. 2.24(a). We shall now show that this circuit realizes the mathematical operation of integration. Let the input be a time-varying function vI (t). The virtual ground at the inverting op-amp input causes vI(t) to appear in effect across R, and thus the current i1(t) will be This current flows through the capacitor C, causing charge to accumulate on C. If we assume that the circuit begins opera-tion at time t = 0, then at an arbitrary time t the current i1(t) will have deposited on C a charge equal to Thus the capacitor voltage vC(t) will change by If the initial voltage on C (at t = 0) is denoted VC, then Now the output voltage vO(t) = −vC(t); thus, (2.25) Thus the circuit provides an output voltage that is proportional to the time integral of the input, with VC being the initial condition of integration and CR the integrator time constant.
Note that, as expected, there is a negative sign attached to the output voltage, and thus this vI t ( ) R.
⁄ ∫i t 0 1 t ( ) dt.
1 C ----∫i t 0 1 t ( ) dt.
vC t ( ) V C 1 C ----i1 t ( ) t d 0 t ∫ + = vO t ( ) 1 CR --------– vI t ( ) t d 0 t ∫ V C – = Example 2.4 continued and the 3-dB frequency ω 0 as We could have found all this from the circuit in Fig. 2.23 by inspection. Specifically, note that the capacitor behaves as an open circuit at dc; thus at dc the gain is simply Furthermore, because there is a virtual ground at the inverting input terminal, the resistance seen by the capacitor is R2, and thus the time constant of the STC network is C2R2.
Now to obtain a dc gain of 40 dB, that is, 100 V/V, we select For an input resis-tance of 1 kΩ, we select R1 = 1 kΩ, and thus R2 = 100 kΩ. Finally, for a 3-dB frequency f0 = 1 kHz, we select C2 from which yields C2 = 1.59 nF.
The circuit has gain and phase Bode plots of the standard form in Fig. 1.23. As the gain falls off at the rate of –20 dB/decade, it will reach 0 dB in two decades, that is, at f = 100f0 = 100 kHz. As Fig.
1.23(b) indicates, at such a frequency which is much greater than f0, the phase is approximately −90°.
To this, however, we must add the 180° arising from the inverting nature of the amplifier (i.e., the negative sign in the transfer function expression). Thus at 100 kHz, the total phase shift will be −270° or, equivalently, +90°.
ω0 = 1 C2R2 ------------R2 – R1 ⁄ ( ).
R2 R1 ⁄ = 100.
2π 1 103 × × 1 C2 100 103 × × ------------------------------------= 2.5 Integrators and Differentiators 83 integrator circuit is said to be an inverting integrator. It is also known as a Miller integra-tor after an early worker in this field.
The operation of the integrator circuit can be described alternatively in the frequency domain by substituting Z1(s) = R and in Eq. (2.24) to obtain the transfer function (2.26) For physical frequencies, s = jω and (2.27) Thus the integrator transfer function has magnitude (2.28) Figure 2.24 (a) The Miller or inverting integrator. (b) Frequency response of the integrator.
vC i1 C R 0 Vo Vi 1 sCR vO(t) vI(t) dtVC i1 1 t CR 0 vO(t) vI(t) (a) 0 V (b) Z2 s ( ) = 1 sC ⁄ V o s ( ) V i s ( ) -------------1 sCR ----------– = V o jω ( ) Vi jω ( ) ------------------1 jωCR --------------– = V o V i -----1 ωCR ------------= 84 Chapter 2 Operational Amplifiers and phase (2.29) The Bode plot for the integrator magnitude response can be obtained by noting from Eq. (2.28) that as ω doubles (increases by an octave) the magnitude is halved (decreased by 6 dB).
Thus the Bode plot is a straight line of slope –6 dB/octave (or, equivalently, –20 dB/ decade). This line (shown in Fig. 2.24b) intercepts the 0-dB line at the frequency that makes which from Eq. (2.28) is (2.30) The frequency ωint is known as the integrator frequency and is simply the inverse of the integrator time constant.
Comparison of the frequency response of the integrator to that of an STC low-pass net-work indicates that the integrator behaves as a low-pass filter with a corner frequency of zero.
Observe also that at ω = 0, the magnitude of the integrator transfer function is infinite. This indicates that at dc the op amp is operating with an open loop. This should also be obvious from the integrator circuit itself. Reference to Fig. 2.24(a) shows that the feedback element is a capacitor, and thus at dc, where the capacitor behaves as an open circuit, there is no nega-tive feedback! This is a very significant observation and one that indicates a source of prob-lems with the integrator circuit: Any tiny dc component in the input signal will theoretically produce an infinite output. Of course, no infinite output voltage results in practice; rather, the output of the amplifier saturates at a voltage close to the op-amp positive or negative power supply (L+ or L−), depending on the polarity of the input dc signal. The dc problem of the integrator circuit can be alleviated by connecting a resistor RF across the integrator capacitor C, as shown in Fig. 2.25 and thus the gain at dc will be –RF /R rather than infinite. Such a resistor provides a dc feedback path. Unfortunately, however, the integration is no longer ideal, and the lower the value of RF, the less ideal the integrator circuit becomes. This is because RF causes the frequency of the integrator pole to move from its ideal location at ω = 0 to one determined by the corner frequency of the STC network (RF, C). Spe-cifically, the integrator transfer function becomes φ +90° = V o V i ⁄ = 1, ωint 1 CR --------= V o s ( ) V i s ( ) -------------RF R ⁄ 1 sCRF + ----------------------– = C vO R RF (t) vI (t) Figure 2.25 The Miller integrator with a large resistance RF connected in parallel with C in order to provide negative feed-back and hence finite gain at dc.
2.5 Integrators and Differentiators 85 as opposed to the ideal function of The lower the value we select for RF, the higher the corner frequency will be and the more nonideal the integrator becomes. Thus selecting a value for RF presents the designer with a trade-off between dc performance and signal performance. The effect of RF on integrator performance is investi-gated further in the Example 2.5.
1 sCR ⁄ .
– 1 CRF ⁄ ( ) Find the output produced by a Miller integrator in response to an input pulse of 1-V height and 1-ms width [Fig. 2.26(a)]. Let R = 10 kΩ and C = 10 nF. If the integrator capacitor is shunted by a 1-MΩ resistor, how will the response be modified? The op amp is specified to saturate at ±13 V.
Solution In response to a 1-V, 1-ms input pulse, the integrator output will be where we have assumed that the initial voltage on the integrator capacitor is 0. For C = 10 nF and R = 10 kΩ, CR = 0.1 ms, and which is the linear ramp shown in Fig. 2.26(b). It reaches a magnitude of −10 V at t = 1 ms and remains constant thereafter.
That the output is a linear ramp should also be obvious from the fact that the 1-V input pulse produces a constant current through the capacitor of . This constant current I = 0.1 mA supplies the capacitor with a charge and thus the capacitor voltage changes linearly as resulting in It is worth remembering that charging a capacitor with a constant current produces a linear voltage across it.
Next consider the situation with resistor connected across C. As before, the 1-V pulse will provide a constant current I = 0.1 mA. Now, however, this current is supplied to an STC network composed of RF in parallel with C. Thus, the output will be an exponential heading toward −100 V with a time constant of CRF = 10 10−9 1 106 = 10 ms, Of course, the exponential will be interrupted at the end of the pulse, that is, at t = 1 ms, and the out-put will reach the value The output waveform is shown in Fig. 2.26(c), from which we see that including RF causes the ramp to be slightly rounded such that the output reaches only −9.5 V, 0.5 V short of the ideal value of −10 V.
Furthermore, for t > 1 ms, the capacitor discharges through RF with the relatively long time-constant of 10 ms. Finally, we note that op amp saturation, specified to occur at ±13 V, has no effect on the opera-tion of this circuit.
vO t ( ) 1 CR --------1 t, d 0 t ∫ – = 0 t 1 ms ≤≤ vO t ( ) 10t, – = 0 t 1 ms ≤≤ 1 V 10 kΩ ⁄ 0.1 mA = It, It C ⁄ ( ), vO I C ⁄ ( )t – .
= RF 1 MΩ = vO t ( ) 100 1 e t – 10 ⁄ – ( ), 0 t 1 ms ≤≤ – = vO 1 ms ( ) 100 1 e 1 – 10 ⁄ – ( ) – 9.5 V – = = Example 2.5 86 Chapter 2 Operational Amplifiers .
Figure 2.26 Waveforms for Example 2.5: (a) Input pulse. (b) Output linear ramp of ideal integrator with time con-stant of 0.1 ms. (c) Output exponential ramp with resistor RF connected across integrator capacitor.
(a) 1 V 0 0 1 ms t vI(t) (b) 10 V to 0 V to 100 V Exponentials with time constant of 10 ms 0 t vO(t) 1 ms (c) 9.5 V 0 t 1 ms vO(t) Example 2.5 continued The preceding example hints at an important application of integrators, namely, their use in providing triangular waveforms in response to square-wave inputs. This application is explored in Exercise 2.18. Integrators have many other applications, including their use in the design of filters (Chapter 16).
2.5 Integrators and Differentiators 87 2.5.3 The Op-Amp Differentiator Interchanging the location of the capacitor and the resistor of the integrator circuit results in the circuit in Fig. 2.27(a), which performs the mathematical function of differ-entiation. To see how this comes about, let the input be the time-varying function , and note that the virtual ground at the inverting input terminal of the op amp causes to appear in effect across the capacitor C. Thus the current through C will be and this current flows through the feedback resistor R providing at the op-amp output a voltage (2.31) The frequency-domain transfer function of the differentiator circuit can be found by substi-tuting in Eq. (2.24), and to obtain (2.32) which for physical frequencies yields (2.33) Figure 2.27 (a) A differentiator. (b) Frequency response of a differentiator with a time-constant CR. vI t ( ) vI t ( ) C dvI dt ⁄ ( ), vO t ( ), vO t ( ) CRdvI t ( ) dt --------------– = Z1 s ( ) = 1 sC ⁄ Z2 s ( ) = R V o s ( ) V i s ( ) -------------sCR – = s = jω V o jω ( ) V i jω ( ) ------------------jωCR – = C R Vo Vi sCR vI(t) vO(t) vO(t) CR C i(t) dvI(t) dt dvI(t) dt (a) i i 0 0 V (b) (dB) 0 1 CR (log scale) 6 dB/octave Vo Vi 88 Chapter 2 Operational Amplifiers Thus the transfer function has magnitude (2.34) and phase (2.35) The Bode plot of the magnitude response can be found from Eq. (2.34) by noting that for an octave increase in ω, the magnitude doubles (increases by 6 dB). Thus the plot is simply a straight line of slope +6 dB/octave (or, equivalently, +20 dB/decade) intersecting the 0-dB line (where at where CR is the differentiator time-constant [see Fig. 2.27(b)]. The frequency response of the differentiator can be thought of as that of an STC highpass filter with a corner frequency at infinity (refer to Fig. 1.24). Finally, we should note that the very nature of a differentiator circuit causes it to be a “noise magnifier.” This is due to the spike introduced at the output every time there is a sharp change in such a change could be interference coupled electromagnetically (“picked up”) from adjacent signal sources. For this reason and because they suffer from stability problems (Chapter 10), differ-entiator circuits are generally avoided in practice. When the circuit of Fig. 2.27(a) is used, it is usually necessary to connect a small-valued resistor in series with the capacitor. This modification, unfortunately, turns the circuit into a nonideal differentiator. 2.6 DC Imperfections Thus far we have considered the op amp to be ideal. The only exception has been a brief dis-cussion of the effect of the op-amp finite gain A on the closed-loop gain of the inverting and noninverting configurations. Although in many applications the assumption of an ideal op Vo Vi ----- = ωCR φ 90° – = V o Vi ⁄ = 1) ω 1 CR ⁄ , = vI t ( ); 2.18 Consider a symmetrical square wave of 20-V peak-to-peak, 0 average, and 2-ms period applied to a Miller integrator. Find the value of the time constant CR such that the triangular waveform at the output has a 20-V peak-to-peak amplitude.
Ans. 0.5 ms D2.19 Use an ideal op amp to design an inverting integrator with an input resistance of 10 kΩ and an integration time constant of 10−3 s. What is the gain magnitude and phase angle of this circuit at 10 rad/s and at 1 rad/s? What is the frequency at which the gain magnitude is unity?
Ans. R = 10 kΩ, C = 0.1 μF; at ω = 10 rad/s: V/V and φ = +90°; at ω = 1 rad/s: 1,000 V/V and φ = +90°; 1000 rad/s D2.20 Design a differentiator to have a time constant of 10−2 s and an input capacitance of 0.01 μF. What is the gain magnitude and phase of this circuit at 10 rad/s, and at 103 rad/s? In order to limit the high-frequency gain of the differentiator circuit to 100, a resistor is added in series with the ca-pacitor. Find the required resistor value.
Ans. C = 0.01 μF; R = 1 MΩ; at ω = 10 rad/s: V/V and φ = −90°; at ω = 1000 rad/s: V/V and φ = −90°; 10 kΩ V o Vi ⁄ = 100 Vo Vi ⁄ = V o Vi ⁄ = 0.1 V o Vi ⁄ = 10 EXERCISES 2.6 DC Imperfections 89 amp is not a bad one, a circuit designer has to be thoroughly familiar with the characteristics of practical op amps and the effects of such characteristics on the performance of op-amp cir-cuits. Only then will the designer be able to use the op amp intelligently, especially if the application at hand is not a straightforward one. The nonideal properties of op amps will, of course, limit the range of operation of the circuits analyzed in the previous examples.
In this and the two sections that follow, we consider some of the important nonideal properties of the op amp.3 We do this by treating one nonideality at a time, beginning in this section with the dc problems to which op amps are susceptible.
2.6.1 Offset Voltage Because op amps are direct-coupled devices with large gains at dc, they are prone to dc problems. The first such problem is the dc offset voltage. To understand this problem con-sider the following conceptual experiment: If the two input terminals of the op amp are tied together and connected to ground, it will be found that despite the fact that vId = 0, a finite dc voltage exists at the output. In fact, if the op amp has a high dc gain, the output will be at either the positive or negative saturation level. The op-amp output can be brought back to its ideal value of 0 V by connecting a dc voltage source of appropriate polarity and magnitude between the two input terminals of the op amp. This external source balances out the input offset voltage of the op amp. It follows that the input offset voltage (VOS) must be of equal magnitude and of opposite polarity to the voltage we applied externally. The input offset voltage arises as a result of the unavoidable mismatches Present in the input differential stage inside the op amp. In later chapters (in particular Chapters 8 and 12) we shall study this topic in detail. Here, however, our concern is to investigate the effect of VOS on the oper-ation of closed-loop op-amp circuits. Toward that end, we note that general-purpose op amps exhibit VOS in the range of 1 mV to 5 mV. Also, the value of VOS depends on temperature. The op-amp data sheets usually specify typical and maximum values for VOS at room temperature as well as the temperature coefficient of VOS (usually in μV/°C). They do not, however, specify the polarity of VOS because the component mismatches that give rise to VOS are obviously not known a priori; different units of the same op-amp type may exhibit either a positive or a negative VOS.
To analyze the effect of VOS on the operation of op-amp circuits, we need a circuit model for the op amp with input offset voltage. Such a model is shown in Fig. 2.28. It consists of a 3We should note that real op amps have nonideal effects additional to those discussed in this chapter.
These include finite (nonzero) common-mode gain or, equivalently, noninfinite CMRR, noninfinite input resistance, and nonzero output resistance. The effect of these, however, on the performance of most of the closed-loop circuits studied here is not very significant, and their study will be postponed to later chapters (in particular Chapters 8, 9, and 12). Figure 2.28 Circuit model for an op amp with input offset voltage VOS.
90 Chapter 2 Operational Amplifiers dc source of value VOS placed in series with the positive input lead of an offset-free op amp.
The justification for this model follows from the description above. Analysis of op-amp circuits to determine the effect of the op-amp VOS on their perfor-mance is straightforward: The input voltage signal source is short-circuited and the op amp is replaced with the model of Fig. 2.28. (Eliminating the input signal, done to sim-plify matters, is based on the principle of superposition.) Following this procedure, we find that both the inverting and the noninverting amplifier configurations result in the same circuit, that shown in Fig. 2.29, from which the output dc voltage due to VOS is found to be (2.36) This output dc voltage can have a large magnitude. For instance, a noninverting amplifier with a closed-loop gain of 1000, when constructed from an op amp with a 5-mV input offset voltage, will have a dc output voltage of +5 V or −5 V (depending on the polarity of VOS) rather than the ideal value of 0 V. Now, when an input signal is applied to the 2.21 Use the model of Fig. 2.28 to sketch the transfer characteristic vO versus vId (vO ≡ v3 and vId ≡ v2 − v1) of an op amp having an open-loop dc gain A0 = 104 V/V, output saturation levels of ±10 V, and VOS of +5 mV.
Ans. See Fig. E2.21. Observe that true to its name, the input offset voltage causes an offset in the voltage-transfer characteristic; rather than passing through the origin it is now shifted to the left by VOS.
Figure E2.21 Transfer characteristic of an op amp with VOS = 5 mV.
EXERCISE V O V OS 1 R2 R1 -----+ = 2.6 DC Imperfections 91 amplifier, the corresponding signal output will be superimposed on the 5-V dc. Obvi-ously then, the allowable signal swing at the output will be reduced. Even worse, if the signal to be amplified is dc, we would not know whether the output is due to V OS or to the signal!
Some op amps are provided with two additional terminals to which a specified circuit can be connected to trim to zero the output dc voltage due to V OS. Figure 2.30 shows such an arrangement that is typically used with general-purpose op amps. A potentiometer is connected between the offset-nulling terminals with the wiper of the potentiometer con-nected to the op-amp negative supply. Moving the potentiometer wiper introduces an imbalance that counteracts the asymmetry present in the internal op-amp circuitry and that gives rise to V OS. We shall return to this point in the context of our study of the internal cir-cuitry of op amps in Chapter 12. It should be noted, however, that even though the dc out-put offset can be trimmed to zero, the problem remains of the variation (or drift) of V OS with temperature.
One way to overcome the dc offset problem is by capacitively coupling the amplifier.
This, however, will be possible only in applications where the closed-loop amplifier is not required to amplify dc or very-low-frequency signals. Figure 2.31(a) shows a capacitively coupled amplifier. Because of its infinite impedance at dc, the coupling capacitor will cause the gain to be zero at dc. As a result the equivalent circuit for determining the dc output Figure 2.29 Evaluating the output dc offset voltage due to VOS in a closed-loop amplifier.
VO 1 VO VOS VOS R2 R2 R1 R1 Offset-free op amp V V To rest of circuit Offset-nulling terminals Figure 2.30 The output dc offset voltage of an op amp can be trimmed to zero by connecting a potentiometer to the two offset-nulling terminals. The wiper of the potentiometer is connected to the negative supply of the op amp.
92 Chapter 2 Operational Amplifiers voltage resulting from the op-amp input offset voltage VOS will be that shown in Fig. 2.31(b).
Thus VOS sees in effect a unity-gain voltage follower, and the dc output voltage VO will be equal to VOS rather than which is the case without the coupling capacitor.
As far as input signals are concerned, the coupling capacitor C forms together with R1 an STC high-pass circuit with a corner frequency of Thus the gain of the capacitively coupled amplifier will fall off at the low-frequency end [from a magnitude of at high frequencies] and will be 3 dB down at ω0.
Figure 2.31 (a) A capacitively coupled inverting amplifier. (b) The equivalent circuit for determining its dc output offset voltage VO.
(a) (b) R2 VOS VO VOS Offset free V OS 1 R2 R1 ⁄ + ( ), ω0 = 1 CR1.
⁄ 1 R2 R1 ⁄ + ( ) 2.22 Consider an inverting amplifier with a nominal gain of 1000 constructed from an op amp with an input offset voltage of 3 mV and with output saturation levels of ±10 V. (a) What is (approximately) the peak sine-wave input signal that can be applied without output clipping? (b) If the effect of VOS is nulled at room temperature (25°C), how large an input can one now apply if: (i) the circuit is to operate at a constant temperature? (ii) the circuit is to operate at a temperature in the range 0°C to 75°C and the temperature coefficient of VOS is 10 μV/°C?
Ans. (a) 7 mV; (b) 10 mV, 9.5 mV 2.23 Consider the same amplifier as in Exercise 2.22—that is, an inverting amplifier with a nominal gain of 1000 constructed from an op amp with an input offset voltage of 3 mV and with output saturation levels of ±10 V—except here let the amplifier be capacitively coupled as in Fig. 2.31(a). (a) What is the dc offset voltage at the output, and what (approximately) is the peak sine-wave signal that can be applied at the input without output clipping? Is there a need for offset trimming? (b) If R1 = 1 kΩ and R2 = 1 MΩ, find the value of the coupling capacitor C1 that will ensure that the gain will be greater than 57 dB down to 100 Hz.
Ans. (a) 3 mV, 10 mV, no need for offset trimming; (b) 1.6 μF EXERCISES 2.6 DC Imperfections 93 2.6.2 Input Bias and Offset Currents The second dc problem encountered in op amps is illustrated in Fig. 2.32. In order for the op amp to operate, its two input terminals have to be supplied with dc currents, termed the input bias currents.4 In Fig. 2.32 these two currents are represented by two current sources, IB1 and IB2, connected to the two input terminals. It should be emphasized that the input bias currents are independent of the fact that a real op amp has finite (though large) input resis-tance (not shown in Fig. 2.32). The op-amp manufacturer usually specifies the average value of IB1 and IB2 as well as their expected difference. The average value IB is called the input bias current, and the difference is called the input offset current and is given by Typical values for general-purpose op amps that use bipolar transistors are IB = 100 nA and IOS = 10 nA.
We now wish to find the dc output voltage of the closed-loop amplifier due to the input bias currents. To do this we ground the signal source and obtain the circuit shown in Fig. 2.33 for both the inverting and noninverting configurations. As shown in Fig. 2.33, the output dc voltage is given by (2.37) This obviously places an upper limit on the value of R2. Fortunately, however, a technique exists for reducing the value of the output dc voltage due to the input bias currents. The method consists of introducing a resistance R3 in series with the noninverting input lead, as 4This is the case for op amps constructed using bipolar junction transistors (BJTs). Those using MOSFETs in the first (input) stage do not draw an appreciable input bias current; nevertheless, the input terminals should have continuous dc paths to ground. More on this in later chapters.
IB IB1 IB2 + 2 -------------------= IOS IB1 − IB2 = V O IB1R2 IBR2 = Figure 2.32 The op-amp input bias currents represented by two current sources IB1 and IB2.
94 Chapter 2 Operational Amplifiers shown in Fig. 2.34. From a signal point of view, R3 has a negligible effect (ideally no effect).
The appropriate value for R3 can be determined by analyzing the circuit in Fig. 2.34, where analysis details are shown, and the output voltage is given by (2.38) Consider first the case IB1 = IB2 = IB, which results in Figure 2.33 Analysis of the closed-loop amplifier, taking into account the input bias currents.
Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R3.
V O −IB2R3 R2 IB1 IB2R3 R1 ⁄ – ( ) + = V O IB R2 R3 1 R2 R1 ⁄ + ( ) – [ ] = 2.6 DC Imperfections 95 Thus we can reduce VO to zero by selecting R3 such that (2.39) That is, R3 should be made equal to the parallel equivalent of R1 and R2. Having selected R3 as above, let us evaluate the effect of a finite offset current IOS. Let and and substitute in Eq. (2.38). The result is (2.40) which is usually about an order of magnitude smaller than the value obtained without R3 (Eq. 2.37). We conclude that to minimize the effect of the input bias currents, one should place in the positive lead a resistance equal to the equivalant dc resistance seen by the inverting terminal. We emphasize the word dc in the last statement; note that if the ampli-fier is ac-coupled, we should select R3 = R2, as shown in Fig. 2.35.
While we are on the subject of ac-coupled amplifiers, we should note that one must always provide a continuous dc path between each of the input terminals of the op amp and ground. This is the case no matter how small IB is. For this reason the ac-coupled noninverting amplifier of Fig. 2.36 will not work without the resistance R3 to ground.
Unfortunately, including R3 lowers considerably the input resistance of the closed-loop amplifier. R3 R2 1 R2 R1 ⁄ + ------------------------R1R2 R1 R2 + -----------------= = I B1 = I B I OS 2 ⁄ + I B2 = IB I OS 2 ⁄ , – V O IOSR2 = Figure 2.35 In an ac-coupled amplifier the dc resistance seen by the inverting terminal is R2; hence R3 is chosen equal to R2.
R2 Figure 2.36 Illustrating the need for a continuous dc path for each of the op-amp input terminals. Specifi-cally, note that the amplifier will not work without resistor R3.
96 Chapter 2 Operational Amplifiers 2.6.3 Effect of VOS and IOS on the Operation of the Inverting Integrator Our discussion of the inverting integrator circuit in Section 2.5.2 mentioned the susceptibility of this circuit to saturation in the presence of small dc voltages or currents. It behooves us therefore to consider the effect of the op-amp dc offsets on its operation. As will be seen, these effects can be quite dramatic.
To see the effect of the input dc offset voltage V OS, consider the integrator circuit in Fig.
2.38, where for simplicity we have short-circuited the input signal source. Analysis of the circuit is straightforward and is shown in Fig. 2.37. Assuming for simplicity that at time t = 0 the voltage across the capacitor is zero, the output voltage as a function of time is given by (2.41) Thus vO increases linearly with time until the op amp saturates—clearly an unacceptable sit-uation! As should be expected, the dc input offset current IOS produces a similar problem.
Figure 2.38 illustrates the situation. Observe that we have added a resistance R in the op-amp positive-input lead in order to keep the input bias current IB from flowing through C.
Nevertheless, the offset current IOS will flow through C and cause vO to ramp linearly with time until the op amp saturates.
As mentioned in Section 2.5.2 the dc problem of the integrator circuit can be allevi-ated by connecting a resistor RF across the integrator capacitor C, as shown in Fig. 2.25.
2.24 Consider an inverting amplifier circuit designed using an op amp and two resistors, R1 = 10 kΩ and R2 = 1 MΩ. If the op amp is specified to have an input bias current of 100 nA and an input offset current of 10 nA, find the output dc offset voltage resulting and the value of a resistor R3 to be placed in series with the positive input lead in order to minimize the output offset voltage. What is the new value of VO?
Ans. 0.1 V; 9.9 kΩ ( 10 kΩ); 0.01 V EXERCISE vO = V OS V OS CR -------- t + t Figure 2.37 Determining the effect of the op-amp input offset volage VOS on the Miller integra-tor circuit. Note that since the output rises with time, the op amp eventually saturates.
2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 97 Such a resistor provides a dc path through which the dc currents and IOS can flow, with the result that vO will now have a dc component instead of rising linearly. To keep the dc offset at the output small, one would select a low value for RF. Unfortunately, however, the lower the value of RF, the less ideal the integrator circuit becomes. 2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 2.7.1 Frequency Dependence of the Open-Loop Gain The differential open-loop gain A of an op amp is not infinite; rather, it is finite and decreases with frequency. Figure 2.39 shows a plot for , with the numbers typical of some commer-cially available general-purpose op amps (such as the popular 741-type op amp, available from many semiconductor manufacturers; its internal circuit is studied in Chapter 12).
Note that although the gain is quite high at dc and low frequencies, it starts to fall off at a rather low frequency (10 Hz in our example). The uniform –20-dB/decade gain rolloff shown is typical of internally compensated op amps. These are units that have a network (usually a single capacitor) included within the same IC chip whose function is to cause the op-amp gain to have the single-time-constant (STC) low-pass response shown. This (VOS R ⁄ ) [VOS 1 RF R ⁄ + ( ) IOSRF] + vO R R IB2 IB1 (IB1 IB2) IOS IB2RR IB2 C vO IB2R IOS C t IB2R Figure 2.38 Effect of the op-amp input bias and offset currents on the performance of the Miller integrator circuit.
2.25 Consider a Miller integrator with a time constant of 1 ms and an input resistance of 10 kΩ. Let the op amp have VOS = 2 mV and output saturation voltages of ±12 V. (a) Assuming that when the power supply is turned on the capacitor voltage is zero, how long does it take for the amplifier to saturate? (b) Select the largest possible value for a feedback resistor RF so that at least ±10 V of output signal swing remains available. What is the corner frequency of the resulting STC net-work?
Ans. (a) 6 s; (b) 10 MΩ, 0.16 Hz EXERCISE A 98 Chapter 2 Operational Amplifiers process of modifying the open-loop gain is termed frequency compensation, and its purpose is to ensure that op-amp circuits will be stable (as opposed to oscillatory). The subject of stability of op-amp circuits—or, more generally, of feedback amplifiers—will be studied in Chapter 10.
By analogy to the response of low-pass STC circuits (see Section 1.6 and, for more detail, Appendix E), the gain A(s) of an internally compensated op amp may be expressed as (2.42) which for physical frequencies, s = jω, becomes (2.43) where A0 denotes the dc gain and ωb is the 3-dB frequency (corner frequency or “break” fre-quency). For the example shown in Fig. 2.39, A0 = 105 and ωb = 2π × 10 rad/s. For frequencies ω ωb (about 10 times and higher) Eq. (2.43) may be approximated by (2.44) Thus, (2.45) from which it can be seen that the gain |A| reaches unity (0 dB) at a frequency denoted by ωt and given by (2.46) Figure 2.39 Open-loop gain of a typical general-purpose internally compensated op amp.
A s ( ) A0 1 s ωb ⁄ + ---------------------= A jω ( ) A0 1 jω ωb ⁄ + -------------------------= A jω ( ) A0ωb jω ------------A jω ( ) A0ωb ω ------------= ωt A0ωb = 2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 99 Substituting in Eq. (2.44) gives (2.47) The frequency is usually specified on the data sheets of commercially available op amps and is known as the unity-gain bandwidth.5 Also note that for ω ωb the open-loop gain in Eq. (2.42) becomes (2.48) The gain magnitude can be obtained from Eq. (2.47) as (2.49) Thus if ft is known (106 Hz in our example), one can easily determine the magnitude of the op-amp gain at a given frequency f. Furthermore, observe that this relationship correlates with the Bode plot in Fig. 2.39. Specifically, for f fb, doubling f (an octave increase) results in halving the gain (a 6-dB reduction). Similarly, increasing f by a factor of 10 (a decade increase) results in reducing |A| by a factor of 10 (20 dB).
As a matter of practical importance, we note that the production spread in the value of ft between op-amp units of the same type is usually much smaller than that observed for A0 and fb. For this reason ft is preferred as a specification parameter. Finally, it should be mentioned that an op amp having this uniform –6-dB/octave (or equivalently –20-dB/decade) gain rolloff is said to have a single-pole model. Also, since this single pole dominates the ampli-fier frequency response, it is called a dominant pole. For more on poles (and zeros), the reader may wish to consult Appendix F.
2.7.2 Frequency Response of Closed-Loop Amplifiers We next consider the effect of limited op-amp gain and bandwidth on the closed-loop transfer functions of the two basic configurations: the inverting circuit of Fig. 2.5 and the noninverting circuit of Fig. 2.12. The closed-loop gain of the inverting amplifier, assuming a finite op-amp open-loop gain A, was derived in Section 2.2 and given in Eq. (2.5), which we repeat here as (2.50) 5Since ft is the product of the dc gain A0 and the 3-dB bandwidth fb (where fb = ωb/2π), it is also known as the gain–bandwidth product (GB). The reader is cautioned, however, that in some amplifiers, the unity-gain frequency and the gain-bandwidth product are not equal.
A jω ( ) ωt jω ------ft = ωt 2π ⁄ A s ( ) ωt s -----A jω ( ) ωt ω -----f t f --= Vo Vi -----R2 R1 ⁄ – 1 1 R2 R1 ⁄ + ( ) A ⁄ + ----------------------------------------------= 2.26 An internally compensated op amp is specified to have an open-loop dc gain of 106 dB and a unity-gain bandwidth of 3 MHz. Find fb and the open-loop gain (in dB) at fb, 300 Hz, 3 kHz, 12 kHz, and 60 kHz.
Ans. 15 Hz; 103 dB; 80 dB; 60 dB; 48 dB; 34 dB EXERCISE 100 Chapter 2 Operational Amplifiers Substituting for A from Eq. (2.42) and using Eq. (2.46) gives (2.51) For which is usually the case, (2.52) which is of the same form as that for a low-pass STC network (see Table 1.2, page 34). Thus the inverting amplifier has an STC low-pass response with a dc gain of magnitude equal to R2/R1. The closed-loop gain rolls off at a uniform –20-dB/decade slope with a corner fre-quency (3-dB frequency) given by (2.53) Similarly, analysis of the noninverting amplifier of Fig. 2.12, assuming a finite open-loop gain A, yields the closed-loop transfer function (2.54) Substituting for A from Eq. (2.42) and making the approximation results in (2.55) Thus the noninverting amplifier has an STC low-pass response with a dc gain of and a 3-dB frequency given also by Eq. (2.53).
Vo s ( ) Vi s ( ) -------------R2 R1 ⁄ – 1 1 A0 ----- 1 R2 R1 ------+ ⎝ ⎠ ⎛ ⎞ s ωt 1 R2 R1 ⁄ + ( ) ⁄ ---------------------------------------+ + -----------------------------------------------------------------------------------= A0 @ 1 R2 R1 ⁄ , + > > Vo s ( ) Vi s ( ) -------------R2 R1 ⁄ – 1 s ωt 1 R2 R1 ⁄ + ( ) ⁄ ---------------------------------------+ ------------------------------------------------≈ ω3dB ωt 1 R2 R1 ⁄ + ------------------------= Vo Vi -----1 R2 R1 ⁄ + 1 1 R2 R1 ⁄ + ( ) A ⁄ + ----------------------------------------------= A0 @ 1 R2 R1 ⁄ + > > Vo s ( ) Vi s ( ) ------------- 1 R2 R1 ⁄ + 1 s ωt 1 R2 R1 ⁄ + ( ) ⁄ ---------------------------------------+ ------------------------------------------------1 R2 R1 ⁄ + ( ) Consider an op amp with ft = 1 MHz. Find the 3-dB frequency of closed-loop amplifiers with nomi-nal gains of +1000, +100, +10, +1, −1, −10, −100, and −1000. Sketch the magnitude frequency response for the amplifiers with closed-loop gains of +10 and –10.
Solution We use Eq. (2.53) to obtain the results given in the following table.
Closed-Loop Gain R2 ⁄ R1 f3 dB = ft / (1 + R2 ⁄R1) +1000 999 1 kHz +100 99 10 kHz +10 9 100 kHz +1 0 1 MHz −1 1 0.5 MHz −10 10 90.9 kHz −100 100 9.9 kHz −1000 1000 1 kHz Example 2.6 2.7 Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 101 The table in Example 2.6 above clearly illustrates the trade-off between gain and band-width: For a given op amp, the lower the closed-loop gain required, the wider the bandwidth achieved. Indeed, the noninverting configuration exhibits a constant gain–bandwidth product equal to ft of the op amp. An interpretation of these results in terms of feedback theory will be given in Chapter 10.
Figure 2.40 shows the frequency response for the amplifier whose nominal dc gain is +10 (20 dB), and Fig. 2.41 shows the frequency response for the –10 (also 20 dB) case. An interest-ing observation follows from the table above: The unity-gain inverting amplifier has a 3-dB fre-quency of ft/2 as compared to ft for the unity-gain noninverting amplifier (the unity-gain voltage follower). Figure 2.41 Frequency response of an amplifier with a nominal gain of −10 V/V.
Figure 2.40 Frequency response of an amplifier with a nominal gain of +10 V/V.
102 Chapter 2 Operational Amplifiers 2.8 Large-Signal Operation of Op Amps In this section, we study the limitations on the performance of op-amp circuits when large output signals are present.
2.8.1 Output Voltage Saturation Similar to all other amplifiers, op amps operate linearly over a limited range of output volt-ages. Specifically, the op-amp output saturates in the manner shown in Fig. 1.14 with L+ and L– within 1 V or so of the positive and negative power supplies, respectively. Thus, an op amp that is operating from ±15-V supplies will saturate when the output voltage reaches about +13 V in the positive direction and –13 V in the negative direction. For this particular op amp the rated output voltage is said to be ±13 V. To avoid clipping off the peaks of the output waveform, and the resulting waveform distortion, the input signal must be kept corre-spondingly small.
2.8.2 Output Current Limits Another limitation on the operation of op amps is that their output current is limited to a specified maximum. For instance, the popular 741 op amp is specified to have a maximum output current of ±20 mA. Thus, in designing closed-loop circuits utilizing the 741, the designer has to ensure that under no condition will the op amp be required to supply an out-put current, in either direction, exceeding 20 mA. This, of course, has to include both the current in the feedback circuit as well as the current supplied to a load resistor. If the circuit requires a larger current, the op-amp output voltage will saturate at the level corresponding to the maximum allowed output current.
2.27 An internally compensated op amp has a dc open-loop gain of 106 V/V and an ac open-loop gain of 40 dB at 10 kHz. Estimate its 3-dB frequency, its unity-gain frequency, its gain–bandwidth product, and its expected gain at 1 kHz.
Ans. 1 Hz; 1 MHz; 1 MHz; 60 dB 2.28 An op amp having a 106-dB gain at dc and a single-pole frequency response with ft = 2 MHz is used to design a noninverting amplifier with nominal dc gain of 100. Find the 3-dB frequency of the closed-loop gain.
Ans. 20 kHz EXERCISES 2.8 Large-Signal Operation of Op Amps 103 Consider the noninverting amplifier circuit shown in Fig. 2.42. As shown, the circuit is designed for a nominal gain It is fed with a low-frequency sine-wave signal of peak voltage Vp and is connected to a load resistor RL. The op amp is specified to have output saturation voltages of ±13 V and output current limits of ±20 mA.
(a) For Vp = 1 V and RL = 1 kΩ, specify the signal resulting at the output of the amplifier.
(b) For Vp = 1.5 V and RL = 1 kΩ, specify the signal resulting at the output of the amplifier.
(c) For RL = 1 kΩ, what is the maximum value of Vp for which an undistorted sine-wave output is obtained?
(d) For Vp = 1 V, what is the lowest value of RL for which an undistorted sine-wave output is obtained?
Solution (a) For Vp = 1 V and RL = 1 kΩ, the output will be a sine wave with peak value of 10 V. This is lower than output saturation levels of ±13 V, and thus the amplifier is not limited that way. Also, when the output is at its peak (10 V), the current in the load will be kΩ = 10 mA, and the current in the feedback network will be 10 kΩ = 1 mA, for a total op-amp output current of 11 mA, well under its limit of 20 mA.
(b) Now if Vp is increased to 1.5 V, ideally the output would be a sine wave of 15-V peak. The op amp, however, will saturate at ±13 V, thus clipping the sine-wave output at these levels. Let’s next check on the op-amp output current: At 13-V output and RL = 1 kΩ, iL = 13 mA and iF = 1.3 mA; thus iO = 14.3 mA, again under the 20-mA limit. Thus the output will be a sine wave with its peaks clipped off at ±13 V, as shown in Fig. 2.42(b).
Figure 2.42 (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at ±13-V output voltage and has ±20-mA output current limits. (b) When the input sine wave has a peak of 1.5 V, the output is clipped off at ±13 V.
1 R2 R1 ⁄ + ( ) 10 V/V.
= iF vO R2 9 k 1 k R1 iO iL RL vI t 0 0 Vp vO 15 V 13 V 15 V 13 V t (a) (b) 10 V 1 ⁄ V 9 1 + ( ) ⁄ Example 2.7 104 Chapter 2 Operational Amplifiers 2.8.3 Slew Rate Another phenomenon that can cause nonlinear distortion when large output signals are present is slew-rate limiting. The name refers to the fact that there is a specific maximum rate of change possible at the output of a real op amp. This maximum is known as the slew rate (SR) of the op amp and is defined as (2.56) and is usually specified on the op-amp data sheet in units of V/μs. It follows that if the input signal applied to an op-amp circuit is such that it demands an output response that is faster than the specified value of SR, the op amp will not comply. Rather, its output will change at the maximum possible rate, which is equal to its SR. As an example, consider an op amp connected in the unity-gain voltage-follower configuration shown in Fig. 2.43(a), and let the input signal be the step voltage shown in Fig. 2.43(b). The output of the op amp will not be able to rise instantaneously to the ideal value V; rather, the output will be the linear ramp of slope equal to SR, shown in Fig. 2.43(c). The amplifier is then said to be slewing, and its output is slew-rate limited.
In order to understand the origin of the slew-rate phenomenon, we need to know about the internal circuit of the op amp, and we will study it in Chapter 12. For the time being, however, it is sufficient to know about the phenomenon and to note that it is distinct from the finite op-amp bandwidth that limits the frequency response of the closed-loop amplifi-ers, studied in the previous section. The limited bandwidth is a linear phenomenon and does not result in a change in the shape of an input sinusoid; that is, it does not lead to non-linear distortion. The slew-rate limitation, on the other hand, can cause nonlinear distortion to an input sinusoidal signal when its frequency and amplitude are such that the corre-sponding ideal output would require vO to change at a rate greater than SR. This is the ori-gin of another related op-amp specification, its full-power bandwidth, to be explained later.
Before leaving the example in Fig. 2.43, however, we should point out that if the step input voltage V is sufficiently small, the output can be the exponentially rising ramp shown in Fig. 2.43(d). Such an output would be expected from the follower if the only limitation on its dynamic performance were the finite op-amp bandwidth. Specifically, the transfer function of the follower can be found by substituting R1 = ∞ and R2 = 0 in Eq. (2.55) to obtain (2.57) SR dvO dt ---------max = Vo Vi -----1 1 s ωt ⁄ + ---------------------= Example 2.7 continued (c) For RL = 1 kΩ, the maximum value of Vp for undistorted sine-wave output is 1.3 V. The output will be a 13-V peak sine wave, and the op-amp output current at the peaks will be 14.3 mA.
(d) For Vp = 1 V and RL reduced, the lowest value possible for RL while the output is remaining an undistorted sine wave of 10-V peak can be found from which results in iOmax 20 mA 10 V RLmin ------------= = 10 V 9 kΩ 1 kΩ + --------------------------------+ RLmin 526 Ω = 2.8 Large-Signal Operation of Op Amps 105 which is a low-pass STC response with a time constant Its step response would there-fore be (see Appendix E) (2.58) The initial slope of this exponentially rising function is (ωtV). Thus, as long as V is suffi-ciently small so that ωtV ≤ SR, the output will be as in Fig. 2.43(d).
t 0 v1 V (b) t 0 vO Slope SR V (c) t 0 vO Slope tV SR V (d) Figure 2.43 (a) Unity-gain follower. (b) Input step waveform. (c) Linearly rising output waveform obtained when the amplifier is slew-rate limited. (d) Exponentially rising output waveform obtained when V is sufficiently small so that the initial slope (ωtV) is smaller than or equal to SR.
1 ωt ⁄ .
vO t ( ) V 1 e ωtt – – ( ) = 2.29 An op amp that has a slew rate of 1 V/μs and a unity-gain bandwidth ft of 1 MHz is connected in the unity-gain follower configuration. Find the largest possible input voltage step for which the output waveform will still be given by the exponential ramp of Eq. (2.58). For this input voltage, what is the 10% to 90% rise time of the output waveform? If an input step 10 times as large is applied, find the 10% to 90% rise time of the output waveform.
Ans. 0.16 V; 0.35 μs; 1.28 μs EXERCISE 106 Chapter 2 Operational Amplifiers 2.8.4 Full-Power Bandwidth Op-amp slew-rate limiting can cause nonlinear distortion in sinusoidal waveforms. Consider once more the unity-gain follower with a sine-wave input given by The rate of change of this waveform is given by with a maximum value of This maximum occurs at the zero crossings of the input sinusoid. Now if exceeds the slew rate of the op amp, the output waveform will be distorted in the manner shown in Fig. 2.44. Observe that the output cannot keep up with the large rate of change of the sinusoid at its zero crossings, and the op amp slews. The op-amp data sheets usually specify a frequency fM called the full-power bandwidth.
It is the frequency at which an output sinusoid with amplitude equal to the rated output volt-age of the op amp begins to show distortion due to slew-rate limiting. If we denote the rated output voltage then fM is related to SR as follows: Thus, (2.59) It should be obvious that output sinusoids of amplitudes smaller than will show slew-rate distortion at frequencies higher than ωM. In fact, at a frequency ω higher than ωM, the maximum amplitude of the undistorted output sinusoid is given by (2.60) Figure 2.44 Effect of slew-rate limiting on output sinusoidal waveforms.
vI V i ˆ sinωt = dvI dt -------ωV i ˆ cosωt = ωV ˆi.
ωV ˆi Vomax, ωMVomax SR = f M SR 2π V omax -------------------= V omax V o V omax ωM ω -------⎝ ⎠ ⎛ ⎞ = 2.8 Large-Signal Operation of Op Amps 107 2.30 An op amp has a rated output voltage of ±10 V and a slew rate of 1 V/μs. What is its full-power bandwidth? If an input sinusoid with frequency f = 5fM is applied to a unity-gain follower con-structed using this op amp, what is the maximum possible amplitude that can be accommodated at the output without incurring SR distortion?
Ans. 15.9 kHz; 2 V (peak) EXERCISE Summary The IC op amp is a versatile circuit building block. It is easy to apply, and the performance of op-amp circuits closely matches theoretical predictions.
The op-amp terminals are the inverting input terminal (1), the noninverting input terminal (2), the output ter-minal (3), the positive-supply terminal (4) to be con-nected to the positive power supply (VCC), and the negative-supply terminal (5) to be connected to the negative supply (−VEE). The common terminal of the two supplies is the circuit ground.
The ideal op amp responds only to the difference input signal, that is, providing at the output, be-tween terminal 3 and ground, a signal where A, the open-loop gain, is very large (104 to 106) and ide-ally infinite; and has an infinite input resistance and a zero output resistance. (See Table 3.1.) Negative feedback is applied to an op amp by connecting a passive component between its output terminal and its inverting (negative) input terminal. Negative feedback causes the voltage between the two input terminals to become very small and ideally zero. Correspondingly, a virtual short circuit is said to exist between the two input terminals. If the positive input terminal is connected to ground, a virtual ground appears on the negative input terminal.
The two most important assumptions in the analysis of op-amp circuits, presuming negative feedback exists and the op amps are ideal, are as follows: the two input terminals of the op amp are at the same voltage, and zero current flows into the op-amp input terminals.
With negative feedback applied and the loop closed, the closed-loop gain is almost entirely determined by external components: For the inverting configuration, and for the noninverting configuration, The noninverting closed-loop configuration features a very high input resistance. A special case is the unity-gain fol-lower, frequently employed as a buffer amplifier to con-nect a high-resistance source to a low-resistance load.
The difference amplifier of Fig. 2.16 is designed with , resulting in .
The instrumentation amplifier of Fig. 2.20(b) is a very popular circuit. It provides . It is usually designed with , and and selected to provide the required gain. If an adjust-able gain is needed, part of can be made variable.
The inverting Miller integrator of Fig. 2.24 is a popular cir-cuit, frequently employed in analog signal-processing func-tions such as filters (Chapter 16) and oscillators (Chapter 17).
The input offset voltage, VOS, is the magnitude of dc volt-age that when applied between the op amp input termi-nals, with appropriate polarity, reduces the dc offset voltage at the output to zero.
The effect of VOS on performance can be evaluated by including in the analysis a dc source VOS in series with the op-amp positive input lead. For both the inverting and the noninverting configurations, VOS results in a dc offset voltage at the output of Capacitively coupling an op amp reduces the dc offset voltage at the output considerably.
The average of the two dc currents, IB1 and IB2, that flow in the input terminals of the op amp, is called the input bias current, IB. In a closed-loop amplifier, IB gives rise to a dc offset voltage at the output of magnitude IBR2. This voltage can be reduced to IOSR2 by connecting a resistance in se-ries with the positive input terminal equal to the total dc re-sistance seen by the negative input terminal. IOS is the input offset current; that is, v2 v1 – ( ); A v2 v1 – ( ),“ V o Vi ⁄ R2 R1; ⁄ – = V o V i ⁄ 1 R2 R1.
⁄ + = R4 R3 ⁄ R2 R1 ⁄ = vO R2 R1 ⁄ ( ) = vI2 vI1 – ( ) vO 1 R2 R1 ⁄ + ( ) R4 R3 ⁄ ( ) = vI2 vI1 – ( ) R3 R4 = R1 R2 R1 VOS 1 R2 R1 ⁄ + ( ).
IOS IB1 IB2 – .
= 108 Chapter 2 Operational Amplifiers Connecting a large resistance in parallel with the capaci-tor of an op-amp inverting integrator prevents op-amp saturation (due to the effect of VOS and IB).
For most internally compensated op amps, the open-loop gain falls off with frequency at a rate of −20 dB/decade, reaching unity at a frequency ft (the unity-gain band-width). Frequency ft is also known as the gain–bandwidth product of the op amp: ft = A0 fb, where A0 is the dc gain, and fb is the 3-dB frequency of the open-loop gain. At any frequency f ( f fb), the op-amp gain For both the inverting and the noninverting closed-loop configurations, the 3-dB frequency is equal to The maximum rate at which the op-amp output voltage can change is called the slew rate. The slew rate, SR, is usually specified in V/μs. Op-amp slewing can result in nonlinear distortion of output signal waveforms.
The full-power bandwidth, fM, is the maximum frequency at which an output sinusoid with an amplitude equal to the op-amp rated output voltage (Vomax) can be produced without distortion: A f t f.
⁄ f t 1 R2 R1 ⁄ + ( ) ⁄ .
f M SR 2πV omax.
⁄ = PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multism simu-lations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption. difficult prob-lem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 2.1: The Ideal Op Amp 2.1 What is the minimum number of pins required for a so-called dual-op-amp IC package, one containing two op amps? What is the number of pins required for a so-called quad-op-amp package, one containing four op-amps?
2.2 The circuit of Fig. P2.2 uses an op amp that is ideal except for having a finite gain A. Measurements indicate vO = 4.0 V when vI = 2.0 V. What is the op-amp gain A?
2.3 Measurement of a circuit incorporating what is thought to be an ideal op amp shows the voltage at the op-amp output to be −2.000 V and that at the negative input to be −1.000 V.
For the amplifier to be ideal, what would you expect the volt-age at the positive input to be? If the measured voltage at the positive input is −1.010 V, what is likely to be the actual gain of the amplifier?
2.4 A set of experiments is run on an op amp that is ideal except for having a finite gain A. The results are tabulated below. Are the results consistent? If not, are they reason-able, in view of the possibility of experimental error? What do they show the gain to be? Using this value, predict values of the measurements that were accidentally omitted (the blank entries).
Experiment # v1 v2 vO 1 0.00 0.00 0.00 2 1.00 1.00 0.00 3 1.00 1.00 4 1.00 1.10 10.1 5 2.01 2.00 −0.99 6 1.99 2.00 1.00 7 5.10 −5.10 Figure P2.2 Problems 109 CHAPTER 2 P ROBL EMS 2.5 Refer to Exercise 2.3. This problem explores an alter-native internal structure for the op amp. In particular, we wish to model the internal structure of a particular op amp using two transconductance amplifiers and one transresistance amplifier. Suggest an appropriate topology. For equal transconductances Gm and a transresistance Rm, find an expression for the open-loop gain A. For Gm = 10 mA/V and Rm = 2 106 Ω, what value of A results?
2.6 The two wires leading from the output terminals of a transducer pick up an interference signal that is a 60-Hz, 1-V sinusoid. The output signal of the transducer is sinusoi-dal of 10-mV amplitude and 1000-Hz frequency. Give expressions for vcm, vd, and the total signal between each wire and the system ground.
2.7 Nonideal (i.e., real) operational amplifiers respond to both the differential and common-mode components of their input signals (refer to Fig. 2.4 for signal representa-tion). Thus the output voltage of the op amp can be expressed as where Ad is the differential gain (referred to simply as A in the text) and Acm is the common-mode gain (assumed to be zero in the text). The op amp’s effectiveness in reject-ing common-mode signals is measured by its CMRR, defined as Consider an op amp whose internal structure is of the type shown in Fig. E2.3 except for a mismatch ΔGm between the transconductances of the two channels; that is, Find expressions for Ad, Acm, and CMRR. If Ad is 80 dB and the two transconductances are matched to within 0.1% of each other, calculate Acm and CMRR.
Section 2.2: The Inverting Configuration 2.8 Assuming ideal op amps, find the voltage gain and input resistance Rin of each of the circuits in Fig. P2.8.
2.9 A particular inverting circuit uses an ideal op amp and two 10-kΩ resistors. What closed-loop gain would you expect? If a dc voltage of +1.00 V is applied at the input, what output result? If the 10-kΩ resistors are said to be “1% resistors,” having values somewhere in the range (1 ± 0.01) times the nominal value, what range of outputs would you expect to actually measure for an input of pre-cisely 1.00 V?
2.10 You are provided with an ideal op amp and three 10-kΩ resistors. Using series and parallel resistor combinations, how many different inverting-amplifier circuit topologies are possible? What is the largest (noninfinite) available voltage vO AdvId AcmvIcm + = CMRR = 20 log Ad Acm --------Gm1 Gm 1 2 -- Gm Δ – = Gm2 Gm 1 2 -- Gm Δ + = vo vi ⁄ (a) (b) (c) (d) Figure P2.8 CHAPTER 2 PR OBLE MS 110 Chapter 2 Operational Amplifiers gain? What is the smallest (nonzero) available gain? What are the input resistances in these two cases? 2.11 For ideal op amps operating with the following feedback networks in the inverting configuration, what closed-loop gain results?
(a) (b) (c) (d) (e) D 2.12 Given an ideal op amp, what are the values of the resistors R1 and R2 to be used to design amplifiers with the closed-loop gains listed below? In your designs, use at least one 10-kΩ resistor and another equal or larger resistor.
(a) −1 V/V (b) −2 V/V (c) −0.5 V/V (d) −100 V/V D 2.13 Design an inverting op-amp circuit for which the gain is −4 V/V and the total resistance used is 100 kΩ. D 2.14 Using the circuit of Fig. 2.5 and assuming an ideal op amp, design an inverting amplifier with a gain of 26 dB having the largest possible input resistance under the con-straint of having to use resistors no larger than 1 MΩ. What is the input resistance of your design?
2.15 An ideal op amp is connected as shown in Fig. 2.5 with R1 = 10 kΩ and R2 = 100 kΩ. A symmetrical square-wave signal with levels of 0 V and 1 V is applied at the input. Sketch and clearly label the waveform of the resulting output voltage. What is its average value? What is its high-est value? What is its lowest value?
2.16 For the circuit in Fig. P2.16, assuming an ideal op amp, find the currents through all branches and the voltages at all nodes. Since the current supplied by the op amp is greater than the current drawn from the input signal source, where does the additional current come from?
2.17 An inverting op-amp circuit is fabricated with the resistors R1 and R2 having x% tolerance (i.e., the value of each resistance can deviate from the nominal value by as much as ± x%). What is the tolerance on the realized closed-loop gain? Assume the op amp to be ideal. If the nominal closed-loop gain is −100 V/V and x = 1, what is the range of gain values expected from such a circuit? 2.18 An ideal op amp with 5-kΩ and 15-kΩ resistors is used to create a +5-V supply from a −15-V reference.
Sketch the circuit. What are the voltages at the ends of the 5-kΩ resistor? If these resistors are so-called 1% resistors, whose actual values are the range bounded by the nominal value ±1%, what are the limits of the output voltage pro-duced? If the −15-V supply can also vary by ±1%, what is the range of the output voltages that might be found?
2.19 An inverting op-amp circuit for which the required gain is −50 V/V uses an op amp whose open-loop gain is only 300 V/V. If the larger resistor used is 100 kΩ, to what must the smaller be adjusted? With what resistor must a 2-kΩ resistor connected to the input be shunted to achieve this goal? (Note that a resistor Ra is said to be shunted by resistor Rb when Rb is placed in parallel with Ra.) D 2.20 (a) Design an inverting amplifier with a closed-loop gain of −100 V/V and an input resistance of 1 kΩ.
(b) If the op amp is known to have an open-loop gain of 2000 V/V, what do you expect the closed-loop gain of your circuit to be (assuming the resistors have precise values)?
(c) Give the value of a resistor you can place in parallel (shunt) with R1 to restore the closed-loop gain to its nominal value. Use the closest standard 1% resistor value (see Appendix H).
2.21 An op amp with an open-loop gain of 2000 V/V is used in the inverting configuration. If in this application the output voltage ranges from −10 V to +10 V, what is the maximum voltage by which the “virtual ground node” departs from its ideal value?
2.22 The circuit in Fig. P2.22 is frequently used to provide an output voltage vo proportional to an input signal current ii.
R1 = 10 kΩ, R2 = 10 kΩ R1 = 10 kΩ, R2 = 100 kΩ R1 = 10 kΩ, R2 = 1 kΩ R1 = 100 kΩ, R2 = 10 MΩ R1 = 100 kΩ, R2 = 1 MΩ 10 kV 2 kV 1 kV 2 1 1 2 20.5 V Figure P2.16 vo 1 2 vi Figure P2.22 Problems 111 CHAPTER 2 P ROBL EMS Derive expressions for the transresistance and the input resistance for the following cases: (a) A is infinite.
(b) A is finite.
2.23 Show that for the inverting amplifier if the op-amp gain is A, the input resistance is given by 2.24 For an inverting amplifier with nominal closed-loop gain , find the minimum value that the op-amp open-loop gain A must have (in terms of ) so that the gain error is limited to 0.1%, 1%, and 10%. In each case find the value of a resistor RIa such that when it is placed in shunt with Ri, the gain is restored to its nominal value.
2.25 Figure P2.25 shows an op amp that is ideal except for having a finite open-loop gain and is used to realize an invert-ing amplifier whose gain has a nominal magnitude To compensate for the gain reduction due to the finite A, a resistor Rc is shunted across R1. Show that perfect compensation is achieved when Rc is selected according to Figure P2.25 D 2.26 (a) Use Eq. (2.5) to obtain the amplifier open-loop gain A required to realize a specified closed-loop gain within a specified gain error ε, (b) Design an inverting amplifer for a nominal closed-loop gain of −100, an input resistance of 2 kΩ, and a gain error of 10%. Specify R1, R2, and the minimum A required.
2.27 (a) Use Eq. (2.5) to show that a reduction in the op-amp gain A gives rise to a reduction in the magnitude of the closed-loop gain G with and related by (b) If in a closed-loop amplifier with a nominal gain (i.e, ) of 100, A decreases by 50%, what is the minimum nominal A required to limit the percentage change in to 0.5%?
2.28 Consider the circuit in Fig. 2.8 with R1 = R2 = R4 = 1 MΩ, and assume the op amp to be ideal. Find values for R3 to obtain the following gains: (a) −200 V/V (b) −20 V/V (c) −2 V/V D 2.29 An inverting op-amp circuit using an ideal op amp must be designed to have a gain of −1000 V/V using resis-tors no larger than 100 kΩ.
(a) For the simple two-resistor circuit, what input resis-tance would result?
(b) If the circuit in Fig. 2.8 is used with three resistors of maximum value, what input resistance results? What is the value of the smallest resistor needed?
2.30 The inverting circuit with the T network in the feed-back is redrawn in Fig. P2.30 in a way that emphasizes the observation that R2 and R3 in effect are in parallel (because the ideal op amp forces a virtual ground at the inverting input terminal). Use this observation to derive an expression for the gain by first finding and For the latter use the voltage-divider rule applied to R4 and (R2 || R3).
2.31 The circuit in Fig. P2.31 can be considered to be an extension of the circuit in Fig. 2.8.
(a) Find the resistances looking into node 1, R1; node 2, R2; node 3, R3; and node 4, R4.
(b) Find the currents I1, I2, I3, and I4, in terms of the input current I.
(c) Find the voltages at nodes 1, 2, 3, and 4, that is, V1, V2, V3, and V4 in terms of (IR).
Rm vo ii ⁄ ≡ Ri vi ii ⁄ ≡ Rin R1 R2 A 1 + -------------+ = R2 R1 ⁄ R2 R1 ⁄ G R2 R1 ⁄ = .
Rc R1 -----A G – 1 G + --------------= Vi R2 R1 Rc Vo Gnominal R – 2 R1 ⁄ = ( ) ε G Gnominal – Gnominal ----------------------------≡ ≤ A Δ G Δ G Δ A Δ G G ⁄ Δ A A ⁄ Δ ----------------------1 R2 R1 ⁄ + A -------------------------= R2 R1 ⁄ G vO vI ⁄ ( ) vX vI ⁄ ( ) vO vX ⁄ ( ).
0 V vI vX vO iI R2 R4 R3 R1 Figure P2.30 CHAPTER 2 PR OBLE MS 112 Chapter 2 Operational Amplifiers 2.32 The circuit in Fig. P2.32 utilizes an ideal op amp.
(a) Find I1, I2, I3, IL, and Vx.
(b) If VO is not to be lower than −13 V, find the maximum allowed value for RL.
(c) If RL is varied in the range 100 Ω to 1 kΩ, what is the corresponding change in IL and in VO?
2.33 Use the circuit in Fig. P2.32 as an inspiration to design a circuit that supplies a constant current I of 3.1 mA to a variable resistance RL. Assume the availability of a 1.5 V battery and design so that the current drawn from the battery is 0.1 mA. For the smallest resistance in the circuit, use 500 Ω. If the op amp saturates at ±12 V, what is the maximum value that RL can have while the current-source supplying it operates properly?
D 2.34 Assuming the op amp to be ideal, it is required to design the circuit shown in Fig. P2.34 to implement a cur-rent amplifier with gain (a) Find the required value for R.
(b) What are the input and the output resistance of this current amplifier?
(c) If RL = 1 kΩ and the op amp operates in an ideal man-ner as long as vO is in the range ±12 V, what range of iI is possible?
(d) If the amplifier is fed with a current source having a current of 0.2 mA and a source resistance of 10 kΩ, find iL.
D 2.35 Design the circuit shown in Fig. P2.35 to have an input resistance of 100 kΩ and a gain that can be varied 1 0 V R 2 1 I1 R1 2 R/2 I2 R2 3 R/2 R R R I3 R3 4 R/2 I4 R4 I Ideal Figure P2.31 1 V V X VO I1 10 kV 10 kV 100 V RL 2 1 I2 I3 IL Figure P2.32 iL iI ⁄ 10 A/A.
= vO iI 10 kV R RL 2 1 iL Figure P2.34 vO vI R2 R4 R1 2 1 R3 Figure P2.35 Problems 113 CHAPTER 2 P ROBL EMS from −1 V/V to −10 V/V using the 10-kΩ potentiometer R4.
What voltage gain results when the potentiometer is set exactly at its middle value?
2.36 A weighted summer circuit using an ideal op amp has three inputs using 100-kΩ resistors and a feedback resistor of 50 kΩ. A signal v1 is connected to two of the inputs while a signalv2 is connected to the third. Express vO in terms of v1 and v2. If v1 = 2 V and v2 = –2 V, what is vO?
D 2.37 Design an op amp circuit to provide an output Choose relatively low values of resistors but ones for which the input current (from each input signal source) does not exceed 0.1 mA for 1-V input signals.
D 2.38 Use the scheme illustrated in Fig. 2.10 to design an op-amp circuit with inputs v1, v2, and v3, whose output is vO = −(2v1 + 4v2 + 8v3) using small resistors but no smaller than 10 kΩ.
D 2.39 An ideal op amp is connected in the weighted summer configuration of Fig. 2.10. The feedback resistor Rf = 10 kΩ, and six 10-kΩ resistors are connected to the inverting input terminal of the op amp. Show, by sketching the various circuit configurations, how this basic circuit can be used to implement the following functions: (a) (b) (c) (d) In each case find the input resistance seen by each of the signal sources supplying v1, v2, v3, and v4. Suggest at least two additional summing functions that you can realize with this circuit. How would you realize a summing coefficient that is 0.5? D 2.40 Give a circuit, complete with component values, for a weighted summer that shifts the dc level of a sine-wave sig-nal of 3 sin(ωt) V from zero to −3 V. Assume that in addition to the sine-wave signal you have a dc reference voltage of 1.5 V available. Sketch the output signal waveform.
D 2.41 Use two ideal op amps and resistors to implement the summing function D 2.42 In an instrumentation system, there is a need to take the difference between two signals, one of v1 = 2 sin(2π × 60t) + 0.01 sin(2π × 1000t) volts and another of v2 = 2 sin(2π × 60t) − 0.01 sin(2π × 1000t) volts. Draw a circuit that finds the required difference using two op amps and mainly 100-kΩ resistors. Since it is desirable to amplify the 1000-Hz component in the process, arrange to provide an overall gain of 100 as well. The op amps available are ideal except that their output voltage swing is limited to ±10 V.
2.43 Figure P2.43 shows a circuit for a digital-to-analog converter (DAC). The circuit accepts a 4-bit input binary word a3a2a1a0, where a0, a1, a2, and a3 take the values of 0 or 1, and it provides an analog output voltage vO propor-tional to the value of the digital input. Each of the bits of the input word controls the correspondingly numbered switch. For instance, if a2 is 0 then switch S2 connects the 20-kΩ resistor to ground, while if a2 is 1 then S2 connects the 20-kΩ resistor to the +5-V power supply. Show that vO is given by where Rf is in kilohms. Find the value of Rf so that vO ranges from 0 to −12 volts.
Section 2.3: The Noninverting Configuration D 2.44 Given an ideal op amp to implement designs for the following closed-loop gains, what values of resistors (R1, R2) should be used? Where possible, use at least one 10-kΩ resistor as the smallest resistor in your design.
vO 2v1 v2 2 ⁄ ( ) + [ ].
– = vO v1 2v2 3v3 + + ( ) – = vO v1 v2 2v3 2v4 + + + ( ) – = vO v1 5v2 + ( ) – = vO 6 – v1 = vO v1 2v2 3v3 – 4v4 – + = vO Rf 16 ------ 20a0 21a1 22a2 23a3 + + + [ ] – = Figure P2.43 CHAPTER 2 PR OBLE MS 114 Chapter 2 Operational Amplifiers (a) +1 V/V (b) +2 V/V (c) +11 V/V (d) +100 V/V D 2.45 Design a circuit based on the topology of the non-inverting amplifier to obtain a gain of +1.5 V/V, using only 10-kΩ resistors. Note that there are two possibilities. Which of these can be easily converted to have a gain of either +1.0 V/V or +2.0 V/V simply by short-circuiting a single resistor in each case?
D 2.46 Figure P2.46 shows a circuit for an analog voltme-ter of very high input resistance that uses an inexpensive moving-coil meter. The voltmeter measures the voltage V applied between the op amp’s positive-input terminal and ground. Assuming that the moving coil produces full-scale deflection when the current passing through it is 100 μA, find the value of R such that full-scale reading is obtained when V is +10 V. Does the meter resistance shown affect the voltmeter calibration?
Figure P2.46 D 2.47 (a) Use superposition to show that the output of the circuit in Fig. P2.47 is given by where RN = RN1||RN2|| . . . ||RNn and RP = RP1||RP2|| . . . ||RPn||RP0 (b) Design a circuit to obtain The smallest resistor used should be 10 kΩ.
D 2.48 Design a circuit, using one ideal op amp, whose out-put is vO = vI1 + 3vI2 – 2(vI3 + 3vI4). (Hint: Use a structure sim-ilar to that shown in general form in Fig. P2.47.) 2.49 Derive an expression for the voltage gain, of the circuit in Fig. P2.49.
2.50 For the circuit in Fig. P2.50, use superposition to find vO in terms of the input voltages v1 and v2. Assume an ideal op amp. For find vO. D 2.51 The circuit shown in Fig. P2.51 utilizes a 10-kΩ potentiometer to realize an adjustable-gain amplifier. Derive an expression for the gain as a function of the potentiometer V vO Rf RN1 --------vN1 Rf RN2 --------vN2 . . .
Rf RNn --------vNn + + + – = 1 Rf RN ------+ + RP RP1 --------vP1 RP RP2 --------vP2 . . .
RP RPn --------vPn + + + vO 3vN1 – vP1 2vP2 + + = RP0 Figure P2.47 vO vI ⁄ , R2 R4 R1 R3 2 1 1 2 vO 1 2 vI Figure P2.49 v1 = 10 2π × 60t ( ) 0.1sin 2π × 1000t ( ) volts , – sin v2 = 10 2π 60t × ( ) 0.1sin 2π × 1000t ( ) volts , + sin Problems 115 CHAPTER 2 P ROBL EMS setting x. Assume the op amp to be ideal. What is the range of gains obtained? Show how to add a fixed resistor so that the gain range can be 1 to 11 V/V. What should the resistor value be?
D 2.52 Given the availability of resistors of value 1 kΩ and 10 kΩ only, design a circuit based on the noninverting configuration to realize a gain of +10 V/V.
2.53 It is required to connect a 10-V source with a source resistance of 100 kΩ to a 1-kΩ load. Find the voltage that will appear across the load if: (a) The source is connected directly to the load. (b) A unity-gain op-amp buffer is inserted between the source and the load.
In each case find the load current and the current supplied by the source. Where does the load current come from in case (b)?
2.54 Derive an expression for the gain of the voltage fol-lower of Fig. 2.14, assuming the op amp to be ideal except for having a finite gain A. Calculate the value of the closed-loop gain for A = 1000, 100, and 10. In each case find the percentage error in gain magnitude from the nomi-nal value of unity.
2.55 Complete the following table for feedback amplifiers created using one ideal op amp. Note that Rin signifies input resistance and R1 and R2 are feedback-network resistors as labelled in the inverting and noninverting configurations.
D 2.56 A noninverting op-amp circuit with nominal gain of 10 V/V uses an op amp with open-loop gain of 50 V/V and a lowest-value resistor of 10 kΩ. What closed-loop gain actually results? With what value resistor can which resistor be shunted to achieve the nominal gain? If in the manufac-turing process, an op amp of gain 100 V/V were used, what closed-loop gain would result in each case (the uncompen-sated one, and the compensated one)? 2.57 Use Eq. (2.11) to show that if the reduction in the closed-loop gain G from the nominal value is to be kept less than x% of G0, then the open-loop gain of the op amp must exceed G0 by at least a factor F = Find the required F for x = 0.01, 0.1, 1, and 10. Utilize these results to find for each value of x the minimum required open-loop gain to obtain closed-loop gains of 1, 10, 102, 103, and 104 V/V.
2.58 For each of the following combinations of op-amp open-loop gain A and nominal closed-loop gain G0, calculate the actual closed-loop gain G that is achieved. Also, calcu-late the percentage by which falls short of the nominal gain magnitude 20R 20R Figure P2.50 Figure P2.51 Case Gain Rin R1 R2 a −10 V/V 10 kΩ b −1 V/V 100 kΩ c −2 V/V 100 kΩ d +1 V/V ∞ e +2 V/V 10 kΩ f +11 V/V 100 kΩ g −0.5 V/V 10 kΩ G0 1 R2 R1 ⁄ + = (100 x) 1 – ⁄ 100 x ⁄ .
G Case G0 (V/V) A (V/V) a −1 10 b +1 10 c −1 100 d +10 10 e −10 100 f −10 1000 g +1 2 G0 .
CHAPTER 2 PR OBLE MS 116 Chapter 2 Operational Amplifiers 2.59 Figure P2.59 shows a circuit that provides an output voltage vO whose value can be varied by turning the wiper of the 100-kΩ potentiometer. Find the range over which vO can be varied. If the potentiometer is a “20-turn” device, find the change in vO corresponding to each turn of the pot.
Figure P2.59 Section 2.4: Difference Amplifiers 2.60 Find the voltage gain for the difference amplifier of Fig. 2.16 for the case R1 = R3 = 10 kΩ and R2 = R4 = 100 kΩ. What is the differential input resistance Rid? If the two key resistance ratios and are dif-ferent from each other by 1%, what do you expect the common-mode gain Acm to be? Also, find the CMRR in this case. Neglect the effect of the ratio mismatch on the value of Ad.
D 2.61 Using the difference amplifier configuration of Fig. 2.16 and assuming an ideal op amp, design the circuit to provide the following differential gains. In each case, the differential input resistance should be 20 kΩ.
(a) 1 V/V (b) 2 V/V (c) 100 V/V (d) 0.5 V/V 2.62 For the circuit shown in Fig. P2.62, express vO as a function of v1 and v2. What is the input resistance seen by v1 alone? By v2 alone? By a source connected between the two input terminals? By a source connected to both input termi-nals simultaneously?
2.63 Consider the difference amplifier of Fig. 2.16 with the two input terminals connected together to an input common-mode signal source. For show that the input common-mode resistance is 2.64 Consider the circuit of Fig. 2.16, and let each of the vI1 and vI2 signal sources have a series resistance Rs. What condition must apply in addition to the condition in Eq.
(2.15) in order for the amplifier to function as an ideal dif-ference amplifier?
2.65 For the difference amplifier shown in Fig. P2.62, let all the resistors be 10 kΩ ± x%. Find an expression for the worst-case common-mode gain that results. Evaluate this for x = 0.1, 1, and 5. Also, evaluate the resulting CMRR in each case. Neglect the effect of resistor tolerances on Ad.
2.66 For the difference amplifier of Fig. 2.16, show that if each resistor has a tolerance of ±100 ε % (i.e., for, say, a 5% resistor, ε = 0.05) then the worst-case CMRR is given approximately by where K is the nominal (ideal) value of the ratios and Calculate the value of worst-case CMRR for an amplifier designed to have a differential gain of ideally 100 V/V, assuming that the op amp is ideal and that 1% resistors are used.
D 2.67 Design the difference amplifier circuit of Fig. 2.16 to realize a differential gain of 100, a differential input resis-tance of 20 kΩ, and a minimum CMRR of 80 dB. Assume the op amp to be ideal. Specify both the resistor values and their required tolerance (e.g., better than x%).
2.68 (a) Find Ad and Acm for the difference amplifier cir-cuit shown in Fig. P2.68. (b) If the op amp is specified to operate properly as long as the common-mode voltage at its positive and negative inputs falls in the range ±2.5 V, what is the corresponding limitation on the range of the input common-mode signal vIcm? (This is known as the common-mode range of the differential amplifier.) vO vId ⁄ R2 R1 ⁄ ( ) R4 R3 ⁄ ( ) R2 R1 ⁄ R4 R3 ⁄ , = R3 R4 + ( ) R1 R2 + ( ).
|| CMRR 20 log K 1 + 4ε -------------R2 R1 ⁄ ( ) R4 R3 ⁄ ( ).
Figure P2.62 Problems 117 CHAPTER 2 P ROBL EMS (c) The circuit is modified by connecting a 10-kΩ resistor between node A and ground, and another 10-kΩ resistor between node B and ground. What will now be the values of Ad, Acm, and the input common-mode range?
Figure P2.68 2.69 To obtain a high-gain, high-input-resistance differ-ence amplifier, the circuit in Fig. P2.69 employs positive feed-back, in addition to the negative feedback provided by the resistor R connected from the output to the negative input of the op amp. Specifically, a voltage divider (R5, R6) connected across the output feeds a fraction β of the output, that is, a volt-age βvO, back to the positive-input terminal of the op amp through a resistor R. Assume that R5 and R6 are much smaller than R so that the current through R is much lower than the current in the voltage divider, with the result that Show that the differential gain is given by (Hint: Use superposition.) Design the circuit to obtain a differential gain of 10 V/V and differential input resistance of 2 MΩ. Select values for R, R5, and R6, such that 2.70 Figure P2.70 shows a modified version of the differ-ence amplifier. The modified circuit includes a resistor RG, which can be used to vary the gain. Show that the differen-tial voltage gain is given by (Hint: The virtual short circuit at the op-amp input causes the current through the R1 resistors to be Figure P2.70 D 2.71 The circuit shown in Fig. P2.71 is a representation of a versatile, commercially available IC, the INA105, manu-factured by Burr-Brown and known as a differential ampli-fier module. It consists of an op amp and precision, laser-trimmed, metal-film resistors. The circuit can be configured for a variety of applications by the appropriate connection of terminals A, B, C, D, and O.
(a) Show how the circuit can be used to implement a dif-ference amplifier of unity gain.
(b) Show how the circuit can be used to implement sin-gle-ended amplifiers with gains: (i) −1 V/V (ii) +1 V/V (iii) +2 V/V (iv) +1/2 V/V Avoid leaving a terminal open-circuited, for such a terminal may act as an “antenna,” picking up interference and noise 100 kV 100 kV 100 kV 100 kV B A 2 1 vI1 vI2 vO β R6 R5 R6 + ( ).
Ad vO vId ------≡ 1 1 β – ------------= R5 R6 + ( ) R 100.
⁄ ≤ R R5 bvO v1 v2 R6 R R R 2 1 vO 2 1 vId Figure P2.69 vO vId ------2R2 R1 ----- 1 R2 RG ------+ – = vId 2R1 ⁄ .) vId 25 kV 25 kV 25 kV 25 kV 2 1 A B O C D Figure P2.71 CHAPTER 2 PR OBLE MS 118 Chapter 2 Operational Amplifiers through capacitive coupling. Rather, find a convenient node to connect such a terminal in a redundant way. When more than one circuit implementation is possible, comment on the relative merits of each, taking into account such consider-ations as dependence on component matching and input resistance.
2.72 Consider the instrumentation amplifier of Fig. 2.20(b) with a common-mode input voltage of +2 V (dc) and a dif-ferential input signal of 80-mV peak sine wave. Let 2R1 = 2 kΩ, R2 = 50 kΩ, R3 = R4 = 10 kΩ. Find the voltage at every node in the circuit.
2.73 (a) Consider the instrumentation amplifier circuit of Fig. 2.20(a). If the op amps are ideal except that their out-puts saturate at ±14 V, in the manner shown in Fig. 1.14, find the maximum allowed input common-mode signal for the case R1 = 1 kΩ and R2 = 100 kΩ.
(b) Repeat (a) for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.
2.74 (a) Expressing vI1 and vI2 in terms of differential and common-mode components, find vO1 and vO2 in the circuit in Fig. 2.20(a) and hence find their differential component vO2 − vO1 and their common-mode component Now find the differential gain and the common-mode gain of the first stage of this instrumentation ampli-fier and hence the CMRR.
(b) Repeat for the circuit in Fig. 2.20(b), and comment on the difference between the two circuits.
2.75 For an instrumentation amplifier of the type shown in Fig. 2.20(b), a designer proposes to make R2 = R3 = R4 = 100 kΩ, and 2R1 = 10 kΩ. For ideal components, what difference-mode gain, common-mode gain, and CMRR result? Reevaluate the worst-case values for these for the sit-uation in which all resistors are specified as ±1% units.
Repeat the latter analysis for the case in which 2R1 is reduced to 1 kΩ. What do you conclude about the effect of the gain of the first stage on CMRR? (Hint: Eq. (2.19) can be used to evaluate Acm of the second stage.) D 2.76 Design the instrumentation-amplifier circuit of Fig. 2.20(b) to realize a differential gain, variable in the range 1 to 100, utilizing a 100-kΩ pot as variable resistor.
(Hint: Design the second stage for a gain of 0.5.) 2.77 The circuit shown in Fig. P2.77 is intended to supply a voltage to floating loads (those for which both ter-minals are ungrounded) while making greatest possible use of the available power supply.
(a) Assuming ideal op amps, sketch the voltage wave-forms at nodes B and C for a 1-V peak-to-peak sine wave applied at A. Also sketch vO.
(b) What is the voltage gain (c) Assuming that the op amps operate from ±15-V power supplies and that their output saturates at ±14 V (in the man-ner shown in Fig. 1.14), what is the largest sine-wave out-put that can be accommodated? Specify both its peak-to-peak and rms values.
2.78 The two circuits in Fig. P2.78 are intended to function as voltage-to-current converters; that is, they supply the load impedance ZL with a current proportional to vI and independent of the value of ZL. Show that this is indeed the case, and find for each circuit iO as a function of vI. Comment on the differences between the two circuits.
Section 2.5: Integrators and Differentiators 2.79 A Miller integrator incorporates an ideal op amp, a resistor R of 100 kΩ, and a capacitor C of 1 nF. A sine-wave signal is applied to its input.
(a) At what frequency (in Hz) are the input and output signals equal in amplitude?
(b) At that frequency, how does the phase of the output sine wave relate to that of the input?
(c) If the frequency is lowered by a factor of 10 from that found in (a), by what factor does the output voltage change, and in what direction (smaller or larger)?
(d) What is the phase relation between the input and out-put in situation (c)?
D 2.80 Design a Miller integrator with a time constant of 0.1 s and an input resistance of 100 kΩ. A dc voltage of −1 volt is applied at the input at time 0, at which moment vO = −10 V. How long does it take the output to reach 0 V? +10 V?
1 2 -- vO1 vO2 + ( ).
vO vI ⁄ ?
20 k 30 k Figure P2.77 Problems 119 CHAPTER 2 P ROBL EMS 2.81 An op-amp-based inverting integrator is measured at 1 kHz to have a voltage gain of −100 V/V. At what fre-quency is its gain reduced to −1 V/V? What is the integrator time constant?
D 2.82 Design a Miller integrator that has a unity-gain fre-quency of 1 krad/s and an input resistance of 100 kΩ. Sketch the output you would expect for the situation in which, with output initially at 0 V, a 2-V, 2-ms pulse is applied to the input. Characterize the output that results when a sine wave 2 sin 1000t is applied to the input.
D 2.83 Design a Miller integrator whose input resistance is 20 kΩ and unity-gain frequency is 10 kHz. What components are needed? For long-term stability, a feedback resistor is introduced across the capacitor, limits the dc gain to 40 dB.
What is its value? What is the associated lower 3-dB fre-quency? Sketch and label the output that results with a 0.1-ms, 1-V positive-input pulse (initially at 0 V) with (a) no dc stabilization (but with the output initially at 0 V) and (b) the feedback resistor connected.
2.84 A Miller integrator whose input and output voltages are initially zero and whose time constant is 1 ms is driven by the signal shown in Fig. P2.84. Sketch and label the out-put waveform that results. Indicate what happens if the input levels are ±2 V, with the time constant the same (1 ms) and with the time constant raised to 2 ms.
2.85 Consider a Miller integrator having a time constant of 1 ms and an output that is initially zero, when fed with a string of pulses of 10-μs duration and 1-V amplitude rising from 0 V (see Fig. P2.85). Sketch and label the output wave form resulting. How many pulses are required for an output voltage change of 1 V?
(a) (b) R vI ZL iO vI iO R1 R1 R ZL R1 R1 Figure P2.78 Figure P2.84 Figure P2.85 CHAPTER 2 PR OBLE MS 120 Chapter 2 Operational Amplifiers D 2.86 Figure P2.86 shows a circuit that performs a low-pass STC function. Such a circuit is known as a first-order, low-pass active filter. Derive the transfer function and show that the dc gain is and the 3-dB frequency Design the circuit to obtain an input resis-tance of 10 kΩ, a dc gain of 20 dB, and a 3-dB frequency of 10 kHz. At what frequency does the magnitude of the trans-fer function reduce to unity?
2.87 Show that a Miller integrator implemented with an op amp with open-loop gain A0 has a low-pass STC transfer func-tion. What is the pole frequency of the STC function? How does this compare with the pole frequency of the ideal integra-tor? If an ideal Miller integrator is fed with a –1-V pulse signal with a width T = CR, what will the output voltage be at t = T?
Assume that at t = 0, vO = 0. Repeat for an integrator with an op amp having A0 = 1000. 2.88 A differentiator utilizes an ideal op amp, a 10-kΩ resis-tor, and a 0.01-μF capacitor. What is the frequency f0 (in Hz) at which its input and output sine-wave signals have equal magnitude? What is the output signal for a 1-V peak-to-peak sine-wave input with frequency equal to 10f0?
2.89 An op-amp differentiator with 1-ms time constant is driven by the rate-controlled step shown in Fig. P2.89. Assum-ing vO to be zero initially, sketch and label its waveform.
Figure P2.89 2.90 An op-amp differentiator, employing the circuit shown in Fig. 2.27(a), has R = 10 kΩ and C = 0.1 µF. When a triangle wave of ±1-V peak amplitude at 1 kHz is applied to the input, what form of output results? What is its fre-quency? What is its peak amplitude? What is its average value? What value of R is needed to cause the output to have a 10-V peak amplitude?
2.91 Use an ideal op amp to design a differentiation circuit for which the time constant is 10−3 s using a 10-nF capacitor.
What are the gains and phase shifts found for this circuit at one-tenth and 10 times the unity-gain frequency? A series input resistor is added to limit the gain magnitude at high frequencies to 100 V/V. What is the associated 3-dB fre-quency? What gain and phase shift result at 10 times the unity-gain frequency?
D 2.92 Figure P2.92 shows a circuit that performs the high-pass, single-time-constant function. Such a circuit is known as a first-order high-pass active filter. Derive the transfer function and show that the high-frequency gain is and the 3-dB frequency Design the circuit to obtain a high-frequency input resistance of 10 kΩ, a high-frequency gain of 40 dB, and a 3-dB frequency of 500 Hz. At what frequency does the magnitude of the transfer function reduce to unity?
D 2.93 Derive the transfer function of the circuit in Fig. P2.93 (for an ideal op amp) and show that it can be written in the form where and Assuming that the circuit is designed such that ω2 ω1, find approximate expressions for the transfer function in the following fre-quency regions: (a) ω ω1 (b) ω1 ω ω 2 (c) ω ω2 R2 R1 ⁄ – ( ) ω0 1 CR2.
⁄ = Vo Figure P2.86 R2 R1 ⁄ – ( ) ω0 1 CR1 ⁄ .
= Vo Figure P2.92 Vo Vi -----R2 R1 ⁄ – 1 ω1 jω ⁄ ( ) + [ ] 1 j ω ω2 ⁄ ( ) + [ ] -----------------------------------------------------------------------= ω1 1 C1R1 ⁄ = ω2 1 C2R2 ⁄ .
= Problems 121 CHAPTER 2 P ROBL EMS Use these approximations to sketch a Bode plot for the mag-nitude response. Observe that the circuit performs as an amplifier whose gain rolls off at the low-frequency end in the manner of a high-pass STC network, and at the high-frequency end in the manner of a low-pass STC network.
Design the circuit to provide a gain of 40 dB in the “middle frequency range,” a low-frequency 3-dB point at 100 Hz, a high-frequency 3-dB point at 100 kHz, and an input resis-tance (at ω ω1) of 1 kΩ.
Section 2.6: DC Imperfections 2.94 An op amp wired in the inverting configuration with the input grounded, having R2 = 100 kΩ and R1 = 1 kΩ, has an output dc voltage of –0.4 V. If the input bias current is known to be very small, find the input offset voltage.
2.95 A noninverting amplifier with a gain of 200 uses an op amp having an input offset voltage of ±2 mV. Find the output when the input is 0.01 sin ωt, volts.
2.96 A noninverting amplifier with a closed-loop gain of 1000 is designed using an op amp having an input off-set voltage of 5 mV and output saturation levels of ±13 V. What is the maximum amplitude of the sine wave that can be applied at the input without the output clip-ping? If the amplifier is capacitively coupled in the man-ner indicated in Fig. 2.36, what would the maximum possible amplitude be?
2.97 An op amp connected in a closed-loop inverting con-figuration having a gain of 1000 V/V and using relatively small-valued resistors is measured with input grounded to have a dc output voltage of –1.4 V. What is its input offset voltage? Prepare an offset-voltage-source sketch resembling that in Fig. 2.28. Be careful of polarities.
2.98 A particular inverting amplifier with nominal gain of –100 V/V uses an imperfect op amp in conjunction with 100-kΩ and 10-MΩ resistors. The output voltage is found to be +9.31 V when measured with the input open and +9.09 V with the input grounded.
(a) What is the bias current of this amplifier? In what direction does it flow?
(b) Estimate the value of the input offset voltage.
(c) A 10-MΩ resistor is connected between the positive-input terminal and ground. With the input left floating (disconnected), the output dc voltage is measured to be –0.8 V. Estimate the input offset current.
D 2.99 A noninverting amplifier with a gain of +10 V/V using 100 kΩ as the feedback resistor operates from a 5-kΩ source. For an amplifier offset voltage of 0 mV, but with a bias current of 1 μA and an offset current of 0.1 µA, what range of outputs would you expect? Indicate where you would add an additional resistor to compensate for the bias currents. What does the range of possible outputs then become? A designer wishes to use this amplifier with a 15-kΩ source. In order to compensate for the bias current in this case, what resistor would you use? And where?
D 2.100 The circuit of Fig. 2.36 is used to create an ac-coupled noninverting amplifier with a gain of 200 V/V using resistors no larger than 100 kΩ. What values of R1, R2, and R3 should be used? For a break frequency due to C1 at 100 Hz, and that due to C2 at 10 Hz, what values of C1 and C2 are needed?
2.101 Consider the difference amplifier circuit in Fig. 2.16.
Let R1 = R3 = 10 kΩ and R2 = R4 = 1 MΩ. If the op amp has VOS = 4 mV, IB = 0.5 µA, and IOS = 0.1 µA, find the worst-case (largest) dc offset voltage at the output.
2.102 The circuit shown in Fig. P2.102 uses an op amp having a ±4-mV offset. What is its output offset voltage?
What does the output offset become with the input ac cou-pled through a capacitor C? If, instead, a large capacitor is placed in series with 1-kΩ resistor, what does the output offset become?
Figure P2.102 2.103 Using offset-nulling facilities provided for the op amp, a closed-loop amplifier with gain of +1000 is adjusted Vo Figure P2.93 CHAPTER 2 PR OBLE MS 122 Chapter 2 Operational Amplifiers at 25°C to produce zero output with the input grounded. If the input offset-voltage drift of the op amp is specified to be 10 µV/°C, what output would you expect at 0°C and at 75°C? While nothing can be said separately about the polar-ity of the output offset at either 0 or 75°C, what would you expect their relative polarities to be?
2.104 An op amp is connected in a closed loop with gain of +100 utilizing a feedback resistor of 1 MΩ.
(a) If the input bias current is 100 nA, what output volt-age results with the input grounded?
(b) If the input offset voltage is ±1 mV and the input bias current as in (a), what is the largest possible output that can be observed with the input grounded?
(c) If bias-current compensation is used, what is the value of the required resistor? If the offset current is no more than one-tenth the bias current, what is the resulting out-put offset voltage (due to offset current alone)?
(d) With bias-current compensation as in (c) in place what is the largest dc voltage at the output due to the com-bined effect of offset voltage and offset current?
2.105 An op amp intended for operation with a closed-loop gain of –100 V/V uses resistors of 10 kΩ and 1 MΩ with a bias-current-compensation resistor R3. What should the value of R3 be? With input grounded, the output offset voltage is found to be +0.21 V. Estimate the input offset cur-rent assuming zero input offset voltage. If the input offset voltage can be as large as 1 mV of unknown polarity, what range of offset current is possible?
2.106 A Miller integrator with R = 10 kΩ and C = 10 nF is implemented by using an op amp with VOS = 3 mV, IB = 0.1 μA, and IOS = 10 nA. To provide a finite dc gain, a 1-MΩ resistor is connected across the capacitor.
(a) To compensate for the effect of IB, a resistor is con-nected in series with the positive-input terminal of the op amp. What should its value be?
(b) With the resistor of (a) in place, find the worst-case dc output voltage of the integrator when the input is grounded.
Section 2.7: Effect of Finite Open-Loop Gain and Bandwidth on Circuit Performance 2.107 The data in the following table apply to internally compensated op amps. Fill in the blank entries.
2.108 A measurement of the open-loop gain of an inter-nally compensated op amp at very low frequencies shows it to be 92 dB; at 100 kHz, this shows it is 40 dB. Estimate val-ues for A0, fb, and ft.
2.109 Measurements of the open-loop gain of a compen-sated op amp intended for high-frequency operation indicate that the gain is 5.1 × 103 at 100 kHz and 8.3 × 103 at 10 kHz.
Estimate its 3-dB frequency, its unity-gain frequency, and its dc gain.
2.110 Measurements made on the internally compensated amplifiers listed below provide the dc gain and the fre-quency at which the gain has dropped by 20 dB. For each, what are the 3 dB and unity-gain frequencies?
(a) 3 × 105 V/V and 6 × 102 Hz (b) 50 × 105 V/V and 10 Hz (c) 1500 V/V and 0.1 MHz (d) 100 V/V and 0.1 GHz (e) 25 V/mV and 25 kHz 2.111 An inverting amplifier with nominal gain of −20 V/V employs an op amp having a dc gain of 104 and a unity-gain frequency of 106 Hz. What is the 3-dB frequency f3dB of the closed-loop amplifier? What is its gain at 0.1 f3dB and at 10 f3dB?
2.112 A particular op amp, characterized by a gain–band-width product of 10 MHz, is operated with a closed-loop gain of +100 V/V. What 3-dB bandwidth results? At what frequency does the closed-loop amplifier exhibit a −6° phase shift? A −84° phase shift?
2.113 Find the ft required for internally compensated op amps to be used in the implementation of closed-loop amplifiers with the following nominal dc gains and 3-dB bandwidths: (a) −100 V/V; 100 kHz (b) +100 V/V; 100 kHz (c) +2 V/V; 10 MHz (d) −2 V/V; 10 MHz (e) −1000 V/V; 20 kHz (f) +1 V/V; 1 MHz (g) −1 V/V; 1 MHz 2.114 A noninverting op-amp circuit with a gain of 96 V/V is found to have a 3-dB frequency of 8 kHz. For a particular system application, a bandwidth of 24 kHz is required. What is the highest gain available under these conditions?
2.115 Consider a unity-gain follower utilizing an internally compensated op amp with ft = 1 MHz. What is the 3-dB fre-quency of the follower? At what frequency is the gain of the follower 1% below its low-frequency magnitude? If the input to the follower is a 1-V step, find the 10% to 90% rise time of the output voltage. (Note: The step response of STC low-pass networks is discussed in Appendix E.) A0 fb (Hz) ft (Hz) 105 102 106 106 103 108 10−1 106 2 × 105 10 Problems 123 CHAPTER 2 P ROBL EMS D 2.116 It is required to design a noninverting amplifier with a dc gain of 10. When a step voltage of 100 mV is applied at the input, it is required that the output be within 1% of its final value of 1 V in at most 100 ns. What must the ft of the op amp be? (Note: The step response of STC low-pass networks is discussed in Appendix E.) D 2.117 This problem illustrates the use of cascaded closed-loop amplifiers to obtain an overall bandwidth greater than can be achieved using a single-stage amplifier with the same overall gain.
(a) Show that cascading two identical amplifier stages, each having a low-pass STC frequency response with a 3-dB frequency f1, results in an overall amplifier with a 3-dB frequency given by (b) It is required to design a noninverting amplifier with a dc gain of 40 dB utilizing a single internally compensated op amp with ft = 1 MHz. What is the 3-dB frequency obtained?
(c) Redesign the amplifier of (b) by cascading two identical noninverting amplifiers each with a dc gain of 20 dB. What is the 3-dB frequency of the overall amplifier? Compare this to the value obtained in (b) above. D 2.118 A designer, wanting to achieve a stable gain of 100 V/V at 5 MHz, considers her choice of amplifier topolo-gies. What unity-gain frequency would a single operational amplifier require to satisfy her need? Unfortunately, the best available amplifier has an ft of 40 MHz. How many such amplifiers connected in a cascade of identical noninverting stages would she need to achieve her goal? What is the 3-dB frequency of each stage she can use? What is the overall 3-dB frequency?
2.119 Consider the use of an op amp with a unity-gain fre-quency ft in the realization of: (a) An inverting amplifier with dc gain of magnitude K.
(b) A noninverting amplifier with a dc gain of K. In each case find the 3-dB frequency and the gain-bandwidth product (GBP ≡ |Gain| × f3dB). Comment on the results.
2.120 Consider an inverting summer with two inputs V1 and V2 and with Vo = −(V1 + 2V2). Find the 3-dB frequency of each of the gain functions and in terms of the op amp ft. (Hint: In each case, the other input to the summer can be set to zero—an application of superposition.) Section 2.8: Large-Signal Operation of Op Amps 2.121 A particular op amp using ±15-V supplies operates linearly for outputs in the range −12 V to +12 V. If used in an inverting amplifier configuration of gain –100, what is the rms value of the largest possible sine wave that can be applied at the input without output clipping?
2.122 Consider an op amp connected in the inverting configu-ration to realize a closed-loop gain of –100 V/V utilizing resis-tors of 1 kΩ and 100 kΩ. A load resistance RL is connected from the output to ground, and a low-frequency sine-wave sig-nal of peak amplitude Vp is applied to the input. Let the op amp be ideal except that its output voltage saturates at ±10 V and its output current is limited to the range ±20 mA.
(a) For RL = 1 kΩ, what is the maximum possible value of Vp while an undistorted output sinusoid is obtained?
(b) Repeat (a) for RL = 100 Ω.
(c) If it is desired to obtain an output sinusoid of 10-V peak amplitude, what minimum value of RL is allowed?
2.123 An op amp having a slew rate of 10 V/µs is to be used in the unity-gain follower configuration, with input pulses that rise from 0 to 5 V. What is the shortest pulse that can be used while ensuring full-amplitude output? For such a pulse, describe the output resulting.
2.124 For operation with 10-V output pulses with the require-ment that the sum of the rise and fall times represent only 20% of the pulse width (at half amplitude), what is the slew-rate requirement for an op amp to handle pulses 2 µs wide?
(Note: The rise and fall times of a pulse signal are usually mea-sured between the 10%- and 90%-height points.) 2.125 What is the highest frequency of a triangle wave of 20-V peak-to-peak amplitude that can be reproduced by an op amp whose slew rate is 10 V/µs? For a sine wave of the same frequency, what is the maximum amplitude of output signal that remains undistorted?
2.126 For an amplifier having a slew rate of 60 V/µs, what is the highest frequency at which a 20-V peak-to-peak sine wave can be produced at the output?
D 2.127 In designing with op amps one has to check the limitations on the voltage and frequency ranges of operation of the closed-loop amplifier, imposed by the op-amp finite bandwidth ( ft), slew rate (SR), and output saturation (V omax).
This problem illustrates the point by considering the use of an op amp with ft = 2 MHz, SR = 1 V/µs, and V omax = 10 V in the design of a noninverting amplifier with a nominal gain of 10. Assume a sine-wave input with peak amplitude Vi.
(a) If Vi = 0.5 V, what is the maximum frequency before the output distorts?
(b) If f = 20 kHz, what is the maximum value of Vi before the output distorts?
(c) If Vi = 50 mV, what is the useful frequency range of operation?
(d) If f = 5 kHz, what is the useful input voltage range?
f 3dB 2 1 – f1 = V o V 1 ⁄ V o V2 ⁄ CHAPTER 3 Semiconductors Introduction 125 3.1 Intrinsic Semiconductors 126 3.2 Doped Semiconductors 129 3.3 Current Flow in Semiconductors 132 3.4 The pn Junction with Open-Circuit Terminals (Equilibrium) 138 3.5 The pn Junction with Applied Voltage 145 3.6 Capacitive Effects in the pn Junction 154 Summary 157 Problems 159 125 IN THIS CHAPTER YOU WILL LEARN 1. The basic properties of semiconductors and in particular silicon, which is the material used to make most of today’s electronic circuits.
2. How doping a pure silicon crystal dramatically changes its electrical con-ductivity, which is the fundamental idea underlying the use of semicon-ductors in the implementation of electronic devices.
3. The two mechanisms by which current flows in semiconductors: drift and diffusion of charge carriers.
4. The structure and operation of the pn junction; a basic semiconductor struc-ture that implements the diode and plays a dominant role in transistors.
Introduction Thus far we have dealt with electronic circuits, and notably amplifiers, as system building blocks. For instance, in Chapter 2 we learned how to use op amps to design interesting and useful circuits, taking advantage of the terminal characteristics of the op amp and without any knowledge of what is inside the op amp package. Though interesting and motivating, this approach has its limitations. Indeed, to achieve our goal of preparing the reader to become a proficient circuit designer, we have to go beyond this black-box or system-level abstraction and learn about the basic devices from which electronic circuits are assembled, namely, diodes (Chapter 4) and transistors (Chapters 5 and 6). These solid-state devices are made using semiconductor materials, predominantly silicon.
In this chapter, we briefly introduce the properties and physics of semiconductors. The objective is to provide a basis for understanding the physical operation of diodes and transistors in order to enable their effective use in the design of circuits. Although many of the concepts studied in this chapter apply to semiconductor materials in general, our treatment is heavily biased toward silicon, simply because it is the material used in the vast majority of microelec-tronic circuits. To complement the material presented here, Appendix A provides a description of the integrated-circuit fabrication process. As discussed in Appendix A, whether our circuit con-sists of a single transistor or is an integrated circuit containing more than 2 billion transistors, it is fabricated in a single silicon crystal, which gives rise to the name monolithic circuit. This chapter therefore begins with a study of the crystal structure of semiconductors and introduces the two types of charge carriers available for current conduction: electrons and holes. The most significant property of semiconductors is that their conductivity can be varied over a very wide range through the introduction of controlled amounts of impurity atoms into the semiconductor crystal in a process called doping. Doped semiconductors are discussed in Section 3.2. This is 126 Chapter 3 Semiconductors followed by the study in Section 3.3 of the two mechanisms for current flow in semiconductors, namely, carrier drift and carrier diffusion.
Armed with these basic semiconductor concepts, we spend the remainder of the chapter on the study of an important semiconductor structure; the pn junction. In addition to being essentially a diode, the pn junction is the basic element of the bipolar junction transistor (BJT, Chapter 6) and plays an important role in the operation of field-effect transistors (FETs, Chapter 5).
3.1 Intrinsic Semiconductors As their name implies, semiconductors are materials whose conductivity lies between that of conductors, such as copper, and insulators, such as glass. There are two kinds of semicon-ductors: single-element semiconductors, such as germanium and silicon, which are in group IV in the periodic table; and compound semiconductors, such as gallium-arsenide, which are formed by combining elements from groups III and V or groups II and VI. Compound semi-conductors are useful in special electronic circuit applications as well as in applications that involve light, such as light-emitting diodes (LEDs). Of the two elemental semiconductors, germanium was used in the fabrication of very early transistors (late 1940s, early 1950s). It was quickly supplanted, however, with silicon, on which today’s integrated-circuit technol-ogy is almost entirely based. For this reason, we will deal mostly with silicon devices throughout this book.1 A silicon atom has four valence electrons, and thus it requires another four to complete its outermost shell. This is achieved by sharing one of its valence electrons with each of its four neighboring atoms. Each pair of shared electrons forms a covalent bond. The result is that a crystal of pure or intrinsic silicon has a regular lattice structure, where the atoms are held in their position by the covalent bonds. Figure 3.1 shows a two-dimensional representa-tion of such a structure.
At sufficiently low temperatures, approaching absolute zero (0 K), all the covalent bonds are intact and no electrons are available to conduct electric current. Thus, at such low temperatures, the intrinsic silicon crystal behaves as an insulator.
At room temperature, sufficient thermal energy exists to break some of the covalent bonds, a process known as thermal generation. As shown in Fig. 3.2, when a covalent bond is broken, an electron is freed. The free electron can wander away from its parent atom, and it becomes available to conduct electric current if an electric field is applied to the crystal. As the electron leaves its parent atom, it leaves behind a net positive charge, equal to the magnitude of the elec-tron charge. Thus, an electron from a neighboring atom may be attracted to this positive charge, and leaves its parent atom. This action fills up the “hole” that existed in the ionized atom but creates a new hole in the other atom. This process may repeat itself, with the result that we effectively have a positively charged carrier, or hole, moving through the silicon crystal struc-ture and being available to conduct electric current. The charge of a hole is equal in magnitude to the charge of an electron. We can thus see that as temperature increases, more covalent bonds are broken and electron–hole pairs are generated. The increase in the numbers of free electrons and holes results in an increase in the conductivity of silicon.
1An exception is the subject of gallium arsenide (GaAs) circuits, which though not covered in this edi-tion of the book, is studied in some detail in material provided on the text website and on the disc accompanying the text.
3.1 Intrinsic Semiconductors 127 Thermal generation results in free electrons and holes in equal numbers and hence equal concentrations, where concentration refers to the number of charge carriers per unit volume (cm3). The free electrons and holes move randomly through the silicon crystal structure, and in the process some electrons may fill some of the holes. This process, called recombination, results in the disappearance of free electrons and holes. The recombination rate is Valence electrons Covalent bonds Silicon atoms 4 4 4 4 4 4 4 4 4 Figure 3.1 Two-dimensional representation of the silicon crystal. The circles represent the inner core of silicon atoms, with +4 indicating its positive charge of +4q, which is neutralized by the charge of the four valence electrons. Observe how the covalent bonds are formed by sharing of the valence electrons. At 0 K, all bonds are intact and no free electrons are available for current conduction.
Valence electrons Free electron Covalent bond Silicon atoms Hole Broken covalent bond 4 4 4 4 4 4 4 4 4 Figure 3.2 At room temperature, some of the covalent bonds are broken by thermal generation. Each bro-ken bond gives rise to a free electron and a hole, both of which become available for current conduction.
128 Chapter 3 Semiconductors proportional to the number of free electrons and holes, which in turn is determined by the thermal generation rate. The latter is a strong function of temperature. In thermal equilib-rium, the recombination rate is equal to the generation rate, and one can conclude that the concentration of free electrons n is equal to the concentration of holes p, (3.1) where denotes the number of free electrons and holes in a unit volume (cm3) of intrinsic silicon at a given temperature. Results from semiconductor physics gives as e–Eg/2kT (3.2) where B is a material-dependent parameter that is for silicon; Eg, a parameter known as the bandgap energy, is 1.12 electron volt (eV) for silicon2; and k is Boltzmann’s constant ( eV/K). It is interesting to know that the bandgap energy Eg is the minimum energy required to break a covalent bond and thus generate an electron-hole pair. Finally, it is useful for future purposes to express the product of the hole and free-electron concentration as (3.3) where for silicon at room temperature, . As will be seen shortly, this relationship extends to extrinsic or doped silicon as well.
2 Note that 1 eV J.
n p ni = = ni ni ni BT 3 2 ⁄ = 7.3 1015cm 3 – × K 3 2 ⁄ – 1.6 10 19 – × = 8.62 10 5 – × Example 3.1 Calculate the value of for silicon at room temperature ( K).
Solution Substituting the values given above in Eq. (3.1) provides Although this number seems large, to place it into context note that silicon has atoms/cm3. Thus at room temperature only one in about atoms is ionized and contributing a free electron and a hole!
ni T 300 ni 7.3 1015 × 300 ( )3 2 ⁄ e 1.12 2 8.62 10 5 – 300 × × × ( ) ⁄ – = 1.5 1010 × carriers cm3 ⁄ = 5 1022 × 5 1012 × pn ni 2 = ni 1.5 1010 × cm3 ⁄ 3.2 Doped Semiconductors 129 3.2 Doped Semiconductors The intrinsic silicon crystal described above has equal concentrations of free electrons and holes, generated by thermal generation. These concentrations are far too small for silicon to conduct appreciable current at room temperature. Also, the carrier concentrations and hence the conductivity are strong functions of temperature, not a desirable property in an elec-tronic device. Fortunately, a method was developed to change the carrier concentration in a semiconductor crystal substantially and in a precisely controlled manner. This process is known as doping, and the resulting silicon is referred to as doped silicon.
Doping involves introducing impurity atoms into the silicon crystal in sufficient num-bers to substantially increase the concentration of either free electrons or holes but with little or no change in the crystal properties of silicon. To increase the concentration of free elec-trons, n, silicon is doped with an element with a valence of 5, such as phosphorus. The result-ing doped silicon is then said to be of n type. To increase the concentration of holes, p, silicon is doped with an element having a valence of 3, such as boron, and the resulting doped silicon is said to be of p type.
Figure 3.3 shows a silicon crystal doped with phosphorus impurity. The dopant (phos-phorus) atoms replace some of the silicon atoms in the crystal structure. Since the phosphorus atom has five electrons in its outer shell, four of these electrons form covalent bonds with the Covalent bonds Pentavalent impurity atom (donor) Free electron donated by impurity atom 4 4 4 5 4 4 4 4 4 Valence electrons Silicon atoms Figure 3.3 A silicon crystal doped by a pentavalent element. Each dopant atom donates a free electron and is thus called a donor. The doped semiconductor becomes n type.
3.1 Calculate the intrinsic carrier density for silicon at T = 50 K and 350 K.
Ans.
; ni 9.6 10 39 – cm3 ⁄ × 4.15 1011 × cm3 ⁄ EXERCISE 130 Chapter 3 Semiconductors neighboring atoms, and the fifth electron becomes a free electron. Thus each phosphorus atom donates a free electron to the silicon crystal, and the phosphorus impurity is called a donor. It should be clear, though, that no holes are generated by this process. The positive charge associated with the phosphorus atom is a bound charge that does not move through the crystal.
If the concentration of donor atoms is , where is usually much greater than ni, the concentration of free electrons in the n-type silicon will be (3.4) where the subscript n denotes n-type silicon. Thus is determined by the doping concen-tration and not by temperature. This is not the case, however, for the hole concentration. All the holes in the n-type silicon are those generated by thermal ionization. Their concentration can be found by noting that the relationship in Eq. (3.3) applies equally well for doped silicon, provided thermal equilibrium is achieved. Thus for n-type silicon Substituting for from Eq. (3.4), we obtain for (3.5) Thus will have the same dependence on temperature as that of . Finally, we note that in n-type silicon the concentration of free electrons will be much larger than that of holes. Hence electrons are said to be the majority charge carriers and holes the minority charge carriers in n-type silicon.
To obtain p-type silicon in which holes are the majority charge carriers, a trivalent impu-rity such as boron is used. Figure 3.4 shows a silicon crystal doped with boron. Note that the boron atoms replace some of the silicon atoms in the silicon crystal structure. Since each ND ND nn ND nn pn pnnn ni 2 = nn pn pn ni 2 ND -------pn ni 2 nn Valence electrons Covalent bonds Silicon atom Trivalent impurity atom (acceptor) Electron accepted from this atom, thus creating a hole 4 4 4 4 4 4 3 4 4 Figure 3.4 A silicon crystal doped with a trivalent impurity. Each dopant atom gives rise to a hole, and the semiconductor becomes p type.
3.2 Doped Semiconductors 131 Consider an n-type silicon for which the dopant concentration . Find the electron and hole concentrations at T = 300 K.
Solution The concentration of the majority electrons is The concentration of the minority holes is In Example 3.1 we found that at T = 300 K, . Thus, Observe that and that is vastly higher than .
ND 1017 cm3 ⁄ = nn ND 1017 cm3 ⁄ = pn ni 2 ND -------ni 1.5 1010 × cm3 ⁄ = pn 1.5 1010 × ( ) 2 1017 -------------------------------= 2.25 103 × cm3 ⁄ = nn ni nn pn Example 3.2 boron atom has three electrons in its outer shell, it accepts an electron from a neighboring atom, thus forming covalent bonds. The result is a hole in the neighboring atom and a bound negative charge at the acceptor (boron) atom. It follows that each acceptor atom provides a hole. If the acceptor doping concentration is , where the hole concentration becomes (3.6) where the subscript p denotes p-type silicon. Thus, here the majority carriers are holes and their concentration is determined by NA. The concentration of minority electrons can be found by using the relationship and substituting for from Eq. (3.6), (3.7) Thus, the concentration of the minority electrons will have the same temperature depen-dence as that of .
It should be emphasized that a piece of n-type or p-type silicon is electrically neutral; the charge of the majority free carriers (electrons in the n-type and holes in the p-type silicon) are neutralized by the bound charges associated with the impurity atoms.
NA NA ni; pp NA ppnp ni 2 = pp np ni 2 NA ------ni 2 132 Chapter 3 Semiconductors 3.3 Current Flow in Semiconductors There are two distinctly different mechanisms for the movement of charge carriers and hence for current flow in semiconductors: drift and diffusion.
3.3.1 Drift Current When an electrical field E is established in a semiconductor crystal, holes are accelerated in the direction of E, and free electrons are accelerated in the direction opposite to that of E.
This situation is illustrated in Fig. 3.5. The holes acquire a velocity vp-drift given by vp-drift = μpE (3.8) where μp is a constant called the hole mobility: It represents the degree of ease by which holes move through the silicon crystal in response to the electrical field E. Since velocity has the units of centimeters per second and E has the units of volts per centimeter, we see from Eq. (3.8) that the mobility μp must have the units of centimeters squared per volt-second (cm2/V.s). For intrinsic silicon cm2/V . s.
The free electrons acquire a drift velocity given by vn-drift = –μnE (3.9) where the result is negative because the electrons move in the direction opposite to E. Here is the electron mobility, which for intrinsic silicon is about 1350 cm2/V.s. Note that is about 2.5 times μp, signifying that electrons move with much greater ease through the sil-icon crystal than do holes.
μp 480 = vn-drift μn μn V Holes Electrons E x Figure 3.5 An electric field E established in a bar of silicon causes the holes to drift in the direc-tion of E and the free electrons to drift in the oppo-site direction. Both the hole and electron drift currents are in the direction of E.
3.2 For the situation in Example 3.2, find the electron and hole concentrations at 350 K. You may use the value of at T = 350 K found in Exercise 3.1.
Ans.
, 3.3 For a silicon crystal doped with boron, what must be if at T = 300 K the electron concentration drops below the intrinsic level by a factor of ?
Ans.
ni nn 1017 cm3 ⁄ = pn 1.72 106 × cm3 ⁄ = NA 106 NA 1.5 1016 × cm3 ⁄ = EXERCISES 3.3 Current Flow in Semiconductors 133 Let’s now return to the single-crystal silicon bar shown in Fig. 3.5. Let the concentration of holes be p and that of free electrons n. We wish to calculate the current component due to the flow of holes. Consider a plane perpendicular to the x direction. In one second, the hole charge that crosses that plane will be (Aqpvp-drift) coulombs, where A is the cross-sectional area of the silicon bar and q is the magnitude of electron charge. This then must be the hole component of the drift current flowing through the bar, Ip = Aqpvp-drift (3.10) Substituting for vp-drift from Eq. (3.9), we obtain We are usually interested in the current density Jp, which is the current per unit cross-sectional area, (3.11) The current component due to the drift of free electrons can be found in a similar manner.
Note, however, that electrons drifting from right to left result in a current component from left to right. This is because of the convention of taking the direction of current flow as the direc-tion of flow of positive charge and opposite to the direction of flow of negative charge. Thus, In = –Aqnvn-drift Substituting for vn-drift from Eq. (3.9), we obtain the current density as (3.12) The total drift current density can now be found by summing and from Eqs. (3.11) and (3.12), (3.13) This relationship can be written as (3.14) or (3.15) where the conductivity is given by (3.16) and the resistivity is given by (3.17) Observe that Eq. (3.15) is a form of Ohm’s law and can be written alternately as (3.18) Thus the units of are ohm.centimeters .
Ip AqpμpE = Jp Ip A ----qpμpE = = Jn In A ⁄ = Jn qnμnE = Jp Jn J Jp Jn q pμP nμn + ( )E = + = J σE = J E ρ ⁄ = σ σ q pμp nμn + ( ) = ρ ρ 1 σ ---≡ 1 q pμp nμn + ( ) --------------------------------= ρ E J ---= ρ Ω cm V cm ⁄ A cm2 ⁄ -----------------= ⋅ ⎝ ⎠ ⎛ ⎞ 134 Chapter 3 Semiconductors Find the resistivity of (a) intrinsic silicon and (b) p-type silicon with . Use , and assume that for intrinsic silicon .s and .s, and for the doped silicon .s and .s.
(Note that doping results in reduced carrier mobilities).
Solution (a) For intrinsic silicon, Thus, . cm (b) For the p-type silicon × 104/cm3 Thus, . cm Observe that the resistivity of the p-type silicon is determined almost entirely by the doping concen-tration. Also observe that doping the silicon reduces its resistivity by a factor of about , a truly remarkable change.
NA 1016 cm3 ⁄ = ni 1.5 1010 × cm3 ⁄ = μn 1350 cm2 V ⁄ = μp 480 cm2 V ⁄ = μn 1110 cm2 V ⁄ = μp 400 cm2 V ⁄ = p n ni 1.5 1010 × cm3 ⁄ = = = ρ 1 q pμp nμn + ( ) --------------------------------= ρ 1 1.6 10 19 – 1.5 1010 480 1.5 1010 1350 × × + × × ( ) × -----------------------------------------------------------------------------------------------------------------------= 2.28 105 × Ω = pp NA 1016 cm3 ⁄ = np ni 2 NA ------1.5 1010 × ( ) 2 1016 -------------------------------2.25 = = ρ 1 q pμp nμn + ( ) --------------------------------= 1 1.6 10 19 – 1016 400 2.25 104 1110 × × + × ( ) × -----------------------------------------------------------------------------------------------------------= 1 1.6 10 19 – 1016 400 × × × ----------------------------------------------------------1.56 Ω = 105 Example 3.3 3.3 Current Flow in Semiconductors 135 3.3.2 Diffusion Current Carrier diffusion occurs when the density of charge carriers in a piece of semiconductor is not uniform. For instance, if by some mechanism the concentration of, say, holes, is made higher in one part of a piece of silicon than in another, then holes will diffuse from the region of high concentration to the region of low concentration. Such a diffusion process is like that observed if one drops a few ink drops in a water-filled tank. The diffusion of charge carriers gives rise to a net flow of charge, or diffusion current.
As an example, consider the bar of silicon shown in Fig. 3.6(a): By some unspecified process, we have arranged to inject holes into its left side. This continuous hole injection gives rise to and maintains a hole concentration profile such as that shown in Fig. 3.6(b).
This profile in turn causes holes to diffuse from left to right along the silicon bar, resulting in a hole current in the x direction. The magnitude of the current at any point is proportional to the slope of the concentration profile, or the concentration gradient, at that point, (3.19) 3.4 A uniform bar of n-type silicon of 2 μm length has a voltage of 1 V applied across it. If and .s, find (a) the electron drift velocity, (b) the time it takes an electron to cross the 2-μm length, (c) the drift-current density, and (d) the drift current in the case the silicon bar has a cross sectional area of .
Ans. cm/s; 30 ps; ; 27 μA ND 1016 cm3 ⁄ = μn 1350 cm2 V ⁄ = 0.25 μm2 6.75 106 × 1.08 104 × A cm2 ⁄ EXERCISE Jp qDp dp x ( ) dx --------------– = (a) (b) Hole injection 0 Hole concentration, p Hole diffusion Hole current x x Figure 3.6 A bar of silicon (a) into which holes are injected, thus creating the hole concentration profile along the x axis, shown in (b). The holes diffuse in the posi-tive direction of x and give rise to a hole-diffusion current in the same direction.
Note that we are not showing the circuit to which the silicon bar is connected.
136 Chapter 3 Semiconductors where is the hole-current density ( ), q is the magnitude of electron charge, is a constant called the diffusion constant or diffusivity of holes; and is the hole concentration at point x. Note that the gradient is negative, resulting in a positive current in the x direction, as should be expected.
In the case of electron diffusion resulting from an electron concentration gradient (see Fig. 3.7), a similar relationship applies, giving the electron-current density, (3.20) where is the diffusion constant or diffusivity of electrons. Observe that a negative (dn/dx) gives rise to a negative current, a result of the convention that the positive direction of current is taken to be that of the flow of positive charge (and opposite to that of the flow of negative charge). For holes and electrons diffusing in intrinsic silicon, typical values for the diffusion constants are Dp = 12 cm2/s and Dn = 35 cm2/s.
At this point the reader is probably wondering where the diffusion current in the silicon bar in Fig. 3.6(a) goes. A good question as we are not showing how the right-side end of the bar is connected to the rest of the circuit. We will address this and related questions in detail in our discussion of the pn junction in later sections. Jp A cm2 ⁄ Dp p x ( ) dp dx ⁄ ( ) Jn qDn dn x ( ) dx --------------= Dn Electron diffusion Electron current 0 Electron concentration, n x Figure 3.7 If the electron-concentration profile shown is established in a bar of silicon, electrons diffuse in the x direction, giving rise to an electron-diffusion current in the negative -x direction.
Consider a bar of silicon in which a hole concentration profile described by is established. Find the hole-current density at x = 0. Let and μm. If the cross-sectional area of the bar is 100 μm2, find the current Ip.
p x ( ) p0 e x LP ⁄ – = p0 1016 cm3 ⁄ = Lp 1 = Example 3.4 3.3 Current Flow in Semiconductors 137 3.5 The linear electron-concentration profile shown in Fig. E3.5 has been established in a piece of sili-con. If and W = 1 μm, find the electron-current density in micro amperes per micron squared (μA/μm2). If a diffusion current of 1 mA is required what must the cross-sectional area (in a direction perpendicular to the page) be?
Ans. 56 μA/μm2; 18 μm2 n0 1017 cm3 ⁄ = 0 n0 W x n(x) Figure E3.5 EXERCISE Solution Thus, The current can be found from = 192 μA Jp qDp dp x ( ) dx --------------– = qDp d dx ------ p0e x LP ⁄ – [ ] – = Jp 0 ( ) q Dp Lp ------p0 = 1.6 10 19 – × 12 1 10 4 – × -------------------× 1016 × = 192 A cm2 ⁄ = Ip Ip Jp A × = 192 100 10 × × 8 – = 138 Chapter 3 Semiconductors 3.3.3 Relationship between D and m A simple but powerful relationship ties the diffusion constant with the mobility, (3.21) where . The parameter is known as the thermal voltage. At room tempera-ture, K and mV. We will encounter repeatedly throughout this book.
The relationship in Eq. (3.21) is known as the Einstein relationship.
3.4 The pn Junction with Open-Circuit Terminals (Equilibrium) Having learned important semiconductor concepts, we are now ready to consider our first practical semiconductor structure—the pn junction. As mentioned previously, the pn junc-tion implements the diode (Chapter 4) and plays the dominant role in the structure and oper-ation of the bipolar junction transistor (BJT). As well, understanding pn junctions is very important to the study of the MOSFET operation (Chapter 5).
3.4.1 Physical Structure Figure 3.8 shows a simplified physical structure of the pn junction. It consists of p-type semiconductor (e.g., silicon) brought into close contact with an n-type semiconductor mate-rial (also silicon). In actual practice, both the p and n regions are part of the same silicon crystal; that is, the pn junction is formed within a single silicon crystal by creating regions of different dopings (p and n regions). Appendix A provides a description of the fabrication process of integrated circuits including pn junctions. As indicated in Fig. 3.8, external wire connections are made to the p and n regions through metal (aluminum) contacts. If the pn junction is used as a diode, these constitute the diode terminals and are therefore labeled “anode” and “cathode” in keeping with diode terminology.3 3This terminology in fact is a carryover from that used with vacuum-tube technology, which was the technology for making diodes and other electronic devices until the invention of the transistor in 1947.
This event ushered in the era of solid-state electronics, which changed not only electronics, communi-cations, and computers but indeed the world!
Dn μn ------Dp μp ------VT = = VT kT q ⁄ = VT T 300 VT = 25.9 VT 3.6 Use the Einstein relationship to find and for intrinsic silicon using and .
Ans. 35 cm2/s; 12.4 cm2/s Dn Dp μn 1350 cm2 V s ⋅ ⁄ = μp 480 cm2 V s ⋅ ⁄ = EXERCISE 3.5 The Junction with an Applied Voltage 139 pn 3.4.2 Operation with Open-Circuit Terminals Figure 3.9 shows a pn junction under open-circuit conditions—that is, the external termi-nals are left open. The “+” signs in the p-type material denote the majority holes. The charge of these holes is neutralized by an equal amount of bound negative charge associ-ated with the acceptor atoms. For simplicity, these bound charges are not shown in the diagram. Also not shown are the minority electrons generated in the p-type material by thermal ionization. In the n-type material the majority electrons are indicated by “–” signs. Here also, the bound positive charge, which neutralizes the charge of the majority electrons, is not shown in order to keep the diagram simple. The n-type material also contains minority holes gener-ated by thermal ionization but not shown in the diagram.
The Diffusion Current ID Because the concentration of holes is high in the p region and low in the n region, holes diffuse across the junction from the p side to the n side; similarly, electrons diffuse across the junction from the n side to the p side. These two current compo-nents add together to form the diffusion current ID, whose direction is from the p side to the n side, as indicated in Fig. 3.9.
The Depletion Region The holes that diffuse across the junction into the n region quickly recombine with some of the majority electrons present there and thus disappear from the scene. This recombination process results also in the disappearance of some free electrons from the n-type material. Thus some of the bound positive charge will no longer be neutral-ized by free electrons, and this charge is said to have been uncovered. Since recombination takes place close to the junction, there will be a region close to the junction that is depleted of free electrons and contains uncovered bound positive charge, as indicated in Fig. 3.9.
The electrons that diffuse across the junction into the p region quickly recombine with some of the majority holes there, and thus disappear from the scene. This results also in the disappearance of some majority holes, causing some of the bound negative charge to be uncovered (i.e., no longer neutralized by holes). Thus, in the p material close to the junction, there will be a region depleted of holes and containing uncovered bound negative charge, as indicated in Fig. 3.9. From the above it follows that a carrier-depletion region will exist on both sides of the junction, with the n side of this region positively charged and the p side negatively charged.
This carrier-depletion region—or, simply, depletion region—is also called the space-charge region. The charges on both sides of the depletion region cause an electric field E to be Figure 3.8 Simplified physical structure of the pn junction. (Actual geometries are given in Appendix A.) As the pn junction implements the junction diode, its terminals are labeled anode and cathode.
Metal contact Metal contact Anode p-type silicon n-type silicon Cathode 140 Chapter 3 Semiconductors established across the region in the direction indicated in Fig. 3.9. Hence a potential difference results across the depletion region, with the n side at a positive voltage relative to the p side, as shown in Fig. 3.9(b). Thus the resulting electric field opposes the diffusion of holes into the n region and electrons into the p region. In fact, the voltage drop across the depletion region acts as a barrier that has to be overcome for holes to diffuse into the n region and electrons to dif-fuse into the p region. The larger the barrier voltage, the smaller the number of carriers that will be able to overcome the barrier and hence the lower the magnitude of diffusion current.
Thus it is the appearance of the barrier voltage V0 that limits the carrier diffusion process. It follows that the diffusion current ID depends strongly on the voltage drop V0 across the deple-tion region.
The Drift Current IS and Equilibrium In addition to the current component ID due to majority-carrier diffusion, a component due to minority carrier drift exists across the junc-tion. Specifically, some of the thermally generated holes in the n material move toward the junction and reach the edge of the depletion region. There, they experience the electric field in the depletion region, which sweeps them across that region into the p side. Similarly, some of the minority thermally generated electrons in the p material move to the edge of the deple-tion region and get swept by the electric field in the depletion region across that region into the n side. These two current components—electrons moved by drift from p to n and holes moved by drift from n to p—add together to form the drift current IS, whose direction is from the n side to the p side of the junction, as indicated in Fig. 3.9. Since the current IS is carried Figure 3.9 (a) The pn junction with no applied voltage (open-circuited terminals). (b) The potential distri-bution along an axis perpendicular to the junction.
E (b) 3.5 The Junction with an Applied Voltage 141 pn by thermally generated minority carriers, its value is strongly dependent on temperature; however, it is independent of the value of the depletion-layer voltage V0. This is due to the fact that the drift current is determined by the number of minority carriers that make it to the edge of the depletion region; any minority carriers that manage to get to the edge of the deple-tion region will be swept across by E irrespective of the value of E or, correspondingly, of V0.
Under open-circuit conditions (Fig. 3.9) no external current exists; thus the two opposite currents across the junction must be equal in magnitude: This equilibrium condition4 is maintained by the barrier voltage V0. Thus, if for some reason ID exceeds IS, then more bound charge will be uncovered on both sides of the junction, the deple-tion layer will widen, and the voltage across it (V0) will increase. This in turn causes ID to decrease until equilibrium is achieved with ID = IS. On the other hand, if IS exceeds ID, then the amount of uncovered charge will decrease, the depletion layer will narrow, and the voltage across it (V0) will decrease. This causes ID to increase until equilibrium is achieved with ID = IS.
The Junction Built-In Voltage With no external voltage applied, the barrier voltage V0 across the pn junction can be shown to be given by5 (3.22) where NA and ND are the doping concentrations of the p side and n side of the junction, respectively. Thus V0 depends both on doping concentrations and on temperature. It is known as the junction built-in voltage. Typically, for silicon at room temperature, V0 is in the range of 0.6 V to 0.9 V.
When the pn junction terminals are left open-circuited, the voltage measured between them will be zero. That is, the voltage V0 across the depletion region does not appear between the junction terminals. This is because of the contact voltages existing at the metal-semiconductor junctions at the terminals, which counter and exactly balance the barrier volt-age. If this were not the case, we would have been able to draw energy from the isolated pn junction, which would clearly violate the principle of conservation of energy.
Width of and Charge Stored in the Depletion Region Figure 3.10 provides fur-ther illustration of the situation that obtains in the pn junction when the junction is in equi-librium. In Fig. 3.10(a) we show a junction in which , a typical situation in practice.
This is borne out by the carrier concentration on both sides of the junction, as shown in Fig 3.10(b). Note that we have denoted the minority carrier concentrations in both sides by and pn0, with the additional subscript “0” signifying equilibrium (i.e., before external volt-ages are applied as will be seen in the next section). Observe that the depletion region extends in both the p and n materials and that equal amounts of charge exist on both sides ( and in Fig. 3.10c). However, since usually unequal dopings and are used, as in the case illustrated in Fig. 3.10, the width of the depletion layer will not be the same on the two sides. Rather, to uncover the same amount of charge, the depletion layer will extend deeper into the more lightly doped material. Specifically, if we denote the width of the 4In fact, in equilibrum the equality of drift and diffusion currents applies not just to the total currents but also to their individual components. That is, the hole drift current must equal the hole diffusion current and, similarly, the electron drift current must equal the electron diffusion current.
5The derivation of this formula and of a number of others in this chapter can be found in textbooks deal-ing with devices, such as that by Streetman and Bannerjee (see the reading list in Appendix G).
ID IS = V0 VT NAND ni 2 -------------⎝ ⎠ ⎛ ⎞ ln = NA ND > np0 Q+ Q– N A ND 142 Chapter 3 Semiconductors p n 0 ID pp NA nn ND IS E W xp xn 0 xp xp xn 0 xp xn xn x Carrier concentration Q Aq NDxn Q Aq NAxp Change density x Voltage (d) (c) (b) (a) np0 pn0 ni 2 ND ni 2 NA VO W Figure 3.10 (a) A pn junction with the terminals open circuited. (b) Carrier concentrations; note that NA ND. (c) The charge stored in both sides of the depletion region; QJ = |Q+| = |Q–|. (d) The built-in voltage V0.
3.5 The Junction with an Applied Voltage 143 pn depletion region in the p side by and in the n side by xn, we can express the magnitude of the charge on the n side of the junction as (3.23) and that on the p side of the junction as (3.24) where A is the cross-sectional area of the junction in the plane perpendicular to the page.
The charge equality condition can now be written as which can be rearranged to yield (3.25) In actual practice, it is usual for one side of the junction to be much more heavily doped than the other, with the result that the depletion region exists almost entirely on one side (the lightly doped side).
The width W of the depletion layer can be shown to be given by (3.26) where is the electrical permittivity of silicon F/cm = F/cm. Typically W is in the range 0.1 μm to 1 μm. Eqs. (3.25) and (3.26) can be used to obtain and in terms of W as (3.27) (3.28) The charge stored on either side of the depletion region can be expressed in terms of W by utilizing Eqs. (3.23) and (3.27) to obtain (3.29) Finally, we can substitute for W from Eq. (3.26) to obtain (3.30) These expressions for will prove useful in subsequent sections.
xp Q+ qAxnND = Q– qAxpNA = qAxnND qAxpNA = xn xp ---- NA ND -------= W xn xp 2εs q -------1 NA ------1 ND -------+ ⎝ ⎠ ⎛ ⎞V0 = + = εs 11.7ε0 11.7 8.85 10 14 – × × = = 1.04 10 12 – × xn xp xn W NA NA ND + --------------------= xp W ND NA ND + --------------------= QJ Q+ Q– = = QJ Aq NAND NA ND + --------------------⎝ ⎠ ⎛ ⎞W = QJ A 2εsq NAND NA ND + --------------------⎝ ⎠ ⎛ ⎞V0 = QJ 144 Chapter 3 Semiconductors Consider a pn junction in equilibrium at room temperature (T = 300 K) for which the doping concen-trations are and and the cross-sectional area A = 10–4 cm2. Calculate , , , , , W, , , and . Use .
Solution To find we use Eq. (3.22), where V Thus, To determine W we use Eq. (3.26): μm To determine and we use Eq. (3.27) and (3.28), respectively: μm μm Finally, to determine the charge stored on either side of the depletion region, we use Eq. (3.29) C = 5.18 pC NA 1018 cm3 ⁄ = ND 1016 cm3 ⁄ = pp np0 nn pn0 V0 xn xp QJ ni 1.5 1010 × cm3 ⁄ = pp NA 1018 cm 3 – = np0 ni 2 pp ----- ni 2 NA ------1.5 1010 × ( ) 1018 ----------------------------2 2.25 102 cm 3 – × = = = nn ND 1016 cm 3 – = pn0 ni 2 nn ----- ni 2 ND ------- 1.5 1010 × ( ) 2 1016 ------------------------------- 2.25 104 × cm 3 – = = = V0 V O VT ln NAND ni 2 --------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞ = VT kT q ------8.62 10 5 – 300 eV ( ) × × q e ( ) --------------------------------------------------------= = 25.9 10 3 – × = V0 25.9 10 3 – ln × 1018 1016 × 2.25 1020 × ---------------------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞ = 0.814 V = W 2 1.04 10 12 – × × 1.6 10 19 – × --------------------------------------1 1018 ----------1 1016 ----------+ ⎝ ⎠ ⎛ ⎞ 0.814 × = 3.27 10 5 – × cm 0.327 = = xn xp xn W NA NA ND + --------------------= 0.327 1018 1018 1016 + ---------------------------0.324 = = xp W ND NA ND + --------------------= 0.327 1016 1018 1016 + ---------------------------0.003 = = QJ 10 4 – 1.6 10 19 – × × 1018 1016 × 1018 1016 + ---------------------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞ 0.327 10 4 – × × = 5.18 10 12 – × = Example 3.5 3.5 The Junction with an Applied Voltage 145 pn 3.5 The pn Junction with an Applied Voltage Having studied the open-circuited pn junction in detail, we are now ready to apply a dc volt-age between its two terminals to find its electrical conduction properties. If the voltage is applied so that the p side is made more positive than the n side, it is referred to as a forward-bias6 voltage. Conversely, if our applied dc voltage is such that it makes the n side more pos-itive than the p side, it is said to be a reverse-bias voltage. As will be seen, the pn junction exhibits vastly different conduction properties in its forward and reverse directions.
Our plan is as follows. We begin by a simple qualitative description in Section 3.5.1 and then consider an analytical description of the characteristic of the junction in Section 3.5.2.
3.5.1 Qualitative Description of Junction Operation Figure 3.11 shows the pn junction under three different conditions: (a) the open-circuit or equilibrium condition studied in the previous section; (b) the reverse-bias condition, where a dc voltage is applied; and (c) the forward-bias condition where a dc voltage is applied.
Observe that in the open-circuit case, a barrier voltage develops, making n more positive than p, and limiting the diffusion current to a value exactly equal to the drift current , 6For the time being, we take the term bias to refer simply to the application of a dc voltage. We will see in later chapters that it has a deeper meaning in the design of electronic circuits.
i v – VR VF V0 ID IS 3.7 Show that 3.8 Show that for a pn junction in which the p side is much more heavily doped than the n side, (i.e.
), referred to as a diode, Eqs. (3.26), (3.27), (3.28), (3.29), and (3.30) can be simpli-fied as follows: (3.26′) (3.27′) (3.28′) (3.29′) (3.30′) 3.9 If in the fabrication of the pn junction in Example 3.5, it is required to increase the minority carrier concentration in the n region by a factor of 2, what must be done?
Ans. Lower by a factor of 2.
V0 1 2 --- q εs ----⎝ ⎠ ⎛ ⎞ NAND NA ND + --------------------⎝ ⎠ ⎛ ⎞W2 = NA ND p+n W 2εs qND ----------V0 xn W xp W NA ND ⁄ ( ) ⁄ ( ) QJ AqNDW QJ A 2εsqNDV0 ND EXERCISES 146 Chapter 3 Semiconductors p (a) Open-circuit (Equilibrium) (b) Reverse Bias (c) Forward Bias n p n p n VF VR ID IS ID IS ID IS V0 (V 0 V R) (V 0 V F) Figure 3.11 The pn junction in: (a) equilibrium; (b) reverse bias; (c) forward bias. 3.5 The Junction with an Applied Voltage 147 pn thus resulting in a zero current at the junction terminals, as should be the case since the ter-minals are open circuited. Also, as mentioned previously, the barrier voltage , though it establishes the current equilibrium across the junction, does not in fact appear between the junction terminals.
Consider now the reverse-bias case in (b). The externally applied reverse-bias voltage is in the direction to add to the barrier voltage, and it does, thus increasing the effective barrier voltage to as shown. This reduces the number of holes that diffuse into the n region and the number of electrons that diffuse into the p region. The end result is that the diffusion current is dramatically reduced. As will be seen shortly, a reverse-bias voltage of a volt or so is sufficient to cause , and the current across the junction and through the external circuit will be equal to . Recalling that is the current due to the drift across the depletion region of the thermally generated minority carriers, we expect to be very small and to be strongly dependent on temperature. We will show this to be the case very shortly.
We thus conclude that in the reverse direction, the pn junction conducts a very small and almost-constant current equal to .
Before leaving the reverse-bias case, observe that the increase in barrier voltage will be accompanied by a corresponding increase in the stored uncovered charge on both sides of the depletion region. This in turn means a wider depletion region, needed to uncover the additional charge required to support the larger barrier voltage . Analytically, these results can be obtained easily by a simple extension of the results of the equilibrium case. Thus the width of the depletion region can be obtained by replacing in Eq. (3.26) by , (3.31) and the magnitude of the charge stored on either side of the depletion region can be deter-mined by replacing in Eq. (3.30) by , (3.32) We next consider the forward-bias case shown in Fig. 3.11(c). Here the applied voltage is in the direction that subtracts from the built-in voltage , resulting in a reduced barrier volt-age across the depletion region. This reduced barrier voltage will be accompanied by reduced depletion-region charge and correspondingly narrower depletion-region width W. Most importantly, the lowering of the barrier voltage will enable more holes to diffuse from p to n and more electrons to diffuse from n to p. Thus the diffusion current increases substantially and, as will be seen shortly, can become many orders of magnitude larger than the drift current The current I in the external circuit is of course the difference between and and it flows in the forward direction of the junction, from p to n. We thus conclude that the pn junction can conduct a substantial current in the forward-bias region and that current is mostly a diffusion current whose value is determined by the forward-bias voltage 3.5.2 The Current–Voltage Relationship of the Junction We are now ready to find an analytical expression that describes the current–voltage rela-tionship of the pn junction. In the following we consider a junction operating with a V0 VR V0 VR + ( ) ID ID 0 IS IS IS IS V0 VR + ( ) V0 V0 VR + ( ) W xn xp 2εs q -------1 NA ------1 ND -------+ ⎝ ⎠ ⎜ ⎟ ⎛ ⎞V0 VR + ( ) = + = V0 V0 VR + ( ) QJ A 2εsq NAND NA ND + --------------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞V0 VR + ( ) = VF V 0 V0 V F – ( ) ID IS.
ID IS, I ID IS – = V F.
148 Chapter 3 Semiconductors forward applied voltage V and derive an expression for the current I that flows in the for-ward direction (from p to n). However, our derivation is general and will be seen to yield the reverse current when the applied voltage V is made negative.
From the qualitative description above we know that a forward-bias voltage V subtracts from the built-in voltage , thus resulting in a lower barrier voltage . The lowered barrier in turn makes it possible for a greater number of holes to overcome the barrier and dif-fuse into the n region. A similar statement can be made about electrons from the n region dif-fusing into the p region. Let us now consider the holes injected into the n region. The concentration of holes in the n region at the edge of the depletion region will increase considerably. In fact, an impor-tant result from device physics shows that the steady-state concentration at the edge of the depletion region will be (3.33) That is, the concentration of the minority holes increases from the equilibrium value of (see Fig. 3.10) to the much larger value determined by the value of V, given by Eq. (3.33).
We describe this situation as follows: The forward-bias voltage V results in an excess concentration of minority holes at given by Excess concentration = (3.34) The increase in minority carrier concentration in Eqs. (3.33) and (3.34) occurs at the edge of the depletion region . As the injected holes diffuse into the n material, some will recombine with the majority electrons and disappear. Thus, the excess hole concentration will decay exponentially with distance. As a result, in the total hole concentration in the n material will be given by Substituting for the “Excess concentration” from Eq. (3.34) gives (3.35) The exponential decay is characterized by the constant Lp, which is called the diffusion length of holes in the n material. The smaller the value of Lp, the faster the injected holes will recombine with the majority electrons, resulting in a steeper decay of minority carrier concentration.
Figure 3.12 shows the steady-state minority carrier concentration profiles on both sides of a pn junction in which . Let’s stay a little longer with the diffusion of holes into the n region.
Note that the shaded region under the exponential represents the excess minority carriers (holes).
From our study of diffusion in Section 3.3, we know that the establishment of a carrier concentra-tion profile such as that in Fig. 3.12 is essential to support a steady-state diffusion current. In fact, we can now find the value of the hole–diffusion current density by applying Eq. (3.19), Substituting for from Eq. (3.35) gives (3.36) V0 V0 V – ( ) pn xn ( ) pn0e V VT ⁄ = pn0 x xn, = pn0e V VT ⁄ pn0 – p = n0 e V VT ⁄ 1 – ( ) x xn = ( ) pn x ( ) pn0 Excess concentration ( )e x xn – ( ) Lp ⁄ – + = pn x ( ) pn0 pn0 e V VT ⁄ 1 – ( )e x xn – ( ) Lp ⁄ – + = NA ND Jp x ( ) qDp dpn x ( ) dx ----------------– = pn x ( ) Jp x ( ) q Dp LP ------⎝ ⎠ ⎛ ⎞pn0 e V VT ⁄ 1 – ( )e x xn – ( ) LP ⁄ – = 3.5 The Junction with an Applied Voltage 149 pn As expected, is highest at , (3.37) and decays exponentially for , as the minority holes recombine with the majority elec-trons. This recombination, however, means that the majority electrons will have to be replen-ished by a current that injects electrons from the external circuit into the n region of the junction. This latter current component has the same direction as the hole current (because electrons moving from right to left give rise to current in the direction from left to right). It follows that as decreases, the electron current component increases by exactly the same amount, making the total current in the n material constant at the value given by Eq. (3.37).
An exactly parallel development can be applied to the electrons that are injected from the n to the p region, resulting in an electron diffusion current given by a simple adaptation of Eq.
(3.37), (3.38) Now, although the currents in Eqs. (3.37) and (3.38) are found at the two edges of the deple-tion region, their values do not change in the depletion region. Thus we can drop the location descriptors , , add the two current densities, and multiply by the junction area A to obtain the total current I as 0 Depletion region n region Excess concentration Thermal equilibrium value p region pn pn0 (xn) pn(x) pn, np np np0 (xp) xp xn x np(x) Figure 3.12 Minority-carrier distribution in a forward-biased pn junction. It is assumed that the p region is more heavily doped than the n region; NA ND.
Jp x ( ) x xn = Jp xn ( ) q Dp Lp ------⎝ ⎠ ⎛ ⎞pn0 e V VT ⁄ 1 – ( ) = x xn > Jp x ( ) Jn xp – ( ) q Dn Ln ------⎝ ⎠ ⎛ ⎞np0 e V VT ⁄ 1 – ( ) = xn ( ) xp – ( ) I A Jp Jn + ( ) = I Aq Dp Lp ------ pn0 Dn Ln ------ nP0 + ⎝ ⎠ ⎛ ⎞e V VT ⁄ 1 – ( ) = 150 Chapter 3 Semiconductors Substituting for and for gives (3.39) From this equation we note that for a negative V (reverse bias) with a magnitude of a few times (25.9 mV), the exponential term becomes essentially zero, and the current across the junction becomes negative and constant. From our qualitative description in Section 3.5.1, we know that this current must be Thus, (3.40) where (3.41) Figure (3.13) shows the I–V characteristic of the pn junction (Eq. 3.40). Observe that in the reverse direction the current saturates at a value equal to –IS. For this reason, is given the name saturation current. From Eq. (3.41) we see that IS is directly proportional to the cross-sectional area A of the junction. Thus, another name for IS, one we prefer to use in this book, is the junction scale current. Typical values for IS, for junctions of various areas, range from to A. Besides being proportional to the junction area A, the expression for in Eq. (3.41) indicates that is proportional to which is a very strong function of temperature (see Eq. 3.2).
pn0 ni 2 ND ⁄ = np0 ni 2 NA ⁄ = I Aqni 2 Dp LpND -------------Dn LnNA ------------+ ⎝ ⎠ ⎜ ⎟ ⎛ ⎞e V VT ⁄ 1 – ( ) = VT IS.
I IS e V VT ⁄ 1 – ( ) = IS Aqni 2 Dp LpND -------------Dn LnNA ------------+ ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ = IS 10 18 – 10 12 – IS IS ni 2 0 IS 0 V I Figure 3.13 The pn junction I–V characteristic.
3.5 The Junction with an Applied Voltage 151 pn For the pn junction considered in Example 3.5 for which , , , , let μm, μm, (in the n region) = .s, and (in the p region) .s. The pn junction is forward biased and conducting a current I = 0.1 mA. Calculate: (a) ; (b) the forward-bias voltage V; and (c) the component of the current I due to hole injection and that due to electron injection across the junction.
Solution (a) Using Eq. (3.41), we find as (b) In the forward direction, Thus, For I = 0.1 mA, = 0.605 V (c) The hole-injection component of I can be found using Eq. (3.37) Similarly can be found using Eq. (3.39), Thus, For our case, NA 1018 cm3 ⁄ = ND 1016 cm3 ⁄ = A 10 4 – cm2 = ni 1.5 1010 × cm3 ⁄ = Lp 5 = Ln 10 = Dp 10 cm2 V ⁄ Dn 18 cm2 V ⁄ = IS IS IS 10 4 – 1.6 10 19 – × × 1.5 1010 × ( ) × 2 × = 10 5 10 4 – 1016 × × ------------------------------------18 10 10 4 – 1018 × × ---------------------------------------+ ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ 7.3 = 10 15 – × A I IS e V VT ⁄ 1 – ( ) = ISe V VT ⁄ V VT ln I IS ----⎝⎠ ⎛⎞ = V 25.9 10 3 – × ln 0.1 10 3 – × 7.3 10 15 – × --------------------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞ = Ip Aq Dp Lp ------= pn0 e V VT ⁄ 1 – ( ) Aq Dp Lp ------= ni 2 ND ------- e V VT ⁄ 1 – ( ) In In AqDn Ln ------ ni 2 NA ------ e V VT ⁄ 1 – ( ) = Ip In ----Dp Dn ------⎝ ⎠ ⎛ ⎞ Ln Lp -----⎝ ⎠ ⎛ ⎞ NA ND -------⎝ ⎠ ⎛ ⎞ = Ip In ---- 10 18 ------10 5 ------× 1018 1016 ----------× = 1.11 102 × 111 = = Example 3.6 152 Chapter 3 Semiconductors 3.5.3 Reverse Breakdown The description of the operation of the pn junction in the reverse direction, and the relationship of the junction in Eq. (3.40), indicate that at a reverse-bias voltage –V, with , the reverse current that flows across the junction is approximately equal to and thus is very small. However, as the magnitude of the reverse-bias voltage V is increased, a value is reached at which a very large reverse current flows as shown in Fig. 3.14. Observe that as V reaches the value VZ , the dramatic increase in reverse current is accompanied by a very small increase in the reverse voltage; that is, the reverse voltage across the junction remains very close to the value VZ. The phenomenon that occurs at is known as junction breakdown. It is not a destructive phenomenon. That is, the pn junction can be repeatedly operated in the breakdown region without a permanent effect on its characteristics. This, how-ever, is predicated on the assumption that the magnitude of the reverse-breakdown current is I V – V VT IS V VZ = Example 3.6 continued Thus most of the current is conducted by holes injected into the n region.
Specifically, mA mA This stands to reason, since the p material has a doping concentration 100 times that of the n material.
Ip 111 112 ---------0.1 0.0991 = × = In 1 112 ---------0.1 0.0009 = × = 3.10 Show that if , 3.11 For the pn junction in Example 3.6, find the value of and that of the current I at V = 0.605 V (same voltage found in Example 3.6 at a current I = 0.1 mA) if is reduced by a factor of 2.
Ans. A; 0.2 mA 3.12 For the pn junction considered in Examples 3.5 and 3.6, find the width of the depletion region W cor-responding to the forward-bias voltage found in Example 3.6. (Hint: Use the formula in Eq. (3.31) with replaced with .) Ans. 0.166 μm 3.13 For the pn junction considered in Examples 3.5 and 3.6, find the width of the depletion region W and the charge stored in the depletion region when a 2-V reverse bias is applied. Also find the value of the reverse current I.
Ans. 0.608 μm; 9.63 pC; A NA ND IS Aqni 2 Dp LpND -------------IS ND 1.46 10 14 – × VR VF – QJ 7.3 10 15 – × EXERCISES 3.5 The Junction with an Applied Voltage 153 pn limited by the external circuit to a “safe” value. The “safe” value is one that results in the limi-tation of the power dissipated in the junction to a safe, allowable level.
There are two possible mechanisms for pn junction breakdown: the zener effect7 and the avalanche effect. If a pn junction breaks down with a breakdown voltage V, the break-down mechanism is usually the zener effect. Avalanche breakdown occurs when is greater than approximately 7 V. For junctions that break down between 5 V and 7 V, the breakdown mechanism can be either the zener or the avalanche effect or a combination of the two.
Zener breakdown occurs when the electric field in the depletion layer increases to the point of breaking covalent bonds and generating electron-hole pairs. The electrons generated in this way will be swept by the electric field into the n side and the holes into the p side. Thus these electrons and holes constitute a reverse current across the junction. Once the zener effect starts, a large number of carriers can be generated, with a negligible increase in the junction voltage. Thus the reverse current in the breakdown region will be large and its value must be determined by the external circuit, while the reverse voltage appearing between the diode terminals will remain close to the specified breakdown voltage VZ.
The other breakdown mechanism, avalanche breakdown, which occurs when the minority carriers that cross the depletion region under the influence of the electric field gain sufficient kinetic energy to be able to break covalent bonds in atoms with which they collide.
The carriers liberated by this process may have sufficiently high energy to be able to cause other carriers to be liberated in another ionizing collision. This process keeps repeating in the fashion of an avalanche, with the result that many carriers are created that are able to support any value of reverse current, as determined by the external circuit, with a negligible change in the voltage drop across the junction.
7 Named after an early worker in the area. Note that the subscript Z in VZ denotes zener. We will use VZ to denote the breakdown voltage whether the breakdown mechanism is the zener effect or the avalanche effect.
Figure 3.14 The I-V characteristic of the pn junction showing the rapid increase in reverse current in the breakdown region.
0 VZ V I VZ 5 < VZ 154 Chapter 3 Semiconductors As will be seen in Chapter 4, some pn junction diodes are fabricated to operate specifi-cally in the breakdown region, where use is made of the nearly constant voltage VZ.
3.6 Capacitive Effects in the pn Junction There are two charge storage mechanisms in the pn junction. One is associated with the charge stored in the depletion region, and the other associated with the minority carrier charge stored in the n and p materials as a result of the concentration profiles established by car-rier injection. While the first is easier to see when the pn junction is reverse biased, the sec-ond is in effect only when the junction is forward biased.
3.6.1 Depletion or Junction Capacitance When a pn junction is reverse biased with a voltage VR, the charge stored on either side of the depletion region is given by Eq. (3.32), Thus, for a given pn junction, (3.42) where is given by (3.43) QJ A 2εsq NAND NA ND + -------------------- V0 VR + ( ) = QJ α V0 VR + = α α A 2εsq NAND NA ND + --------------------= 0 VQ Q Reverse voltage,V R Bias point Slope CJ Charge stored in depletion layer, QJ Figure 3.15 The charge stored on either side of the depletion layer as a function of the reverse voltage VR.
3.6 Capacitive Effects in the Junction 155 pn Thus is nonlinearly related to VR, as shown in Fig. (3.15). This nonlinear relationship makes it difficult to define a capacitance that accounts for the need to change whenever is changed. We can, however, assume that the junction is operating at a point such as Q, as indicated in Fig. 3.15, and define a capacitance that relates the change in the charge to a change in the voltage , (3.44) This incremental-capacitance approach turns out to be quite useful in electronic circuit design, as we shall see throughout this book.
Using Eq. (3.44) together with Eq. (3.42) yields (3.45) The value of at zero reverse-bias can be obtained from Eq. (3.45) as (3.46) which enables us to express as (3.47) where is given by Eq. (3.46) or alternatively if we substitute for from Eq. (3.43) by (3.48) Before leaving the subject of depletion-region or junction capacitance we point out that in the pn junction we have been studying, the doping concentration is made to change abruptly at the junction boundary. Such a junction is known as an abrupt junction. There is another type of pn junction in which the carrier concentration is made to change gradually from one side of the junction to the other. To allow for such a graded junction, the formula for the junction capacitance (Eq. 3.47) can be written in the more general form (3.49) where m is a constant called the grading coefficient, whose value ranges from 1/3 to 1/2 depending on the manner in which the concentration changes from the p to the n side. QJ QJ VR Cj QJ VR Cj dQJ dVR ---------VR VQ = = Cj α 2 V0 VR + --------------------------= Cj Cj0 α 2 V0 -------------= Cj Cj Cj0 1 VR V0 ------+ --------------------= Cj0 α Cj0 A εsq 2 -------⎝ ⎠ ⎛ ⎞ NAND NA ND + --------------------⎝ ⎠ ⎛ ⎞ 1 V0 ------⎝ ⎠ ⎛ ⎞ = Cj Cj0 1 VR V0 ------+ ⎝ ⎠ ⎛ ⎞ m -------------------------= 3.12 For the pn junction considered in Examples 3.5 and 3.6, find and at V. Recall that V, , and .
Ans. 3.2 pF; 1.7 pF Cj0 Cj VR 2 = V0 0.814 = NA 1018 cm3 ⁄ = ND 1016 cm3 ⁄ = A 10 4 – cm2 = EXERCISE 156 Chapter 3 Semiconductors 3.6.2 Diffusion Capacitance Consider a forward-biased pn junction. In steady-state, minority carrier distributions in the p and n materials are established, as shown in Fig. 3.12. Thus a certain amount of excess minority carrier charge is stored in each of the p and n bulk regions (outside the depletion region). If the terminal voltage V changes, this charge will have to change before a new steady state is achieved. This charge-storage phenomenon gives rise to another capacitive effect, distinctly different from that due to charge storage in the depletion region.
To calculate the excess minority carrier charge, refer to Fig. 3.12. The excess hole charge stored in the n region can be found from the shaded area under the exponential as follows:8 shaded area under the curve substituting for from Eq. (3.33) and using Eq. (3.37) enables us to express as (3.50) The factor that relates to is a useful device parameter that has the dimension of time (s) and is denoted (3.51) Thus, (3.52) The time constant is known as the excess minority carrier (hole) lifetime. It is the average time it takes for a hole injected into the n region to recombine with a majority elec-tron. This definition of implies that the entire charge disappears and has to be replen-ished every seconds. The current that accomplishes the replenishing is . This is an alternate derivation for Eq. (3.52).
A relationship similar to that in Eq. (3.52) can be developed for the electron charge stored in the p region, (3.53) where is the electron lifetime in the p region. The total excess minority carrier charge can be obtained by adding together and , (3.54) This charge can be expressed in terms of the diode current as (3.55) where is called the mean transit time of the junction. Obviously, is related to and . Furthermore, for most practical devices, one side of the junction is much more heavily doped than the other. For instance, if , one can show that , , , , and thus . 8Recall that the area under an exponential curve is equal to AB.
Ae x B ⁄ – Qp Aq × = pn x ( ) Aq pn xn ( ) pn0 – [ ]Lp = pn xn ( ) Qp Qp Lp 2 Dp ------ Ip = Lp 2 Dp ⁄ ( ) Qp Ip τp τp Lp 2 Dp ------= Qp τpIp = τp τp Qp τp Ip Qp τp ⁄ = Qn τnIn = τn Qp Qn Q τpIp τnIn + = I Ip In + = Q τTI = τT τT τp τn NA ND Ip In I Ip Qp Qn Q Qp τT τp 3.6 Capacitive Effects in the Junction 157 pn 3.15 Use the definition of in Eq. (3.56) to derive the expression in Eq. (3.57) by means of Eqs. (3.55) and (3.40).
3.16 For the pn junction considered in Examples 3.5 and 3.6 for which , and μm, find and at a forward-bias current of 0.1 mA. Recall that for this junction, .
Ans. 25 ns; 96.5 pF Cd Dp 10 cm2 V s ⋅ ⁄ = Lp 5 = τp Cd Ip I EXERCISES For small changes around a bias point, we can define an incremental diffusion capacitance as (3.56) and can show that (3.57) where I is the forward-bias current. Note that is directly proportional to the forward cur-rent I and thus is negligibly small when the diode is reverse biased. Also note that to keep small, the transit time must be made small, an important requirement for a pn junc-tion intended for high-speed or high-frequency operation.
Cd Cd dQ dV -------= Cd τT VT -------⎝ ⎠ ⎛ ⎞I = Cd Cd τT 158 Chapter 3 Semiconductors Summary Today’s microelectronics technology is almost entirely based on the semiconductor material silicon. If a circuit is to be fabricated as a monolithic integrated circuit (IC) it is made using a single silicon crystal, no matter how large the circuit is [a recent chip (2009) contains 2.3 billion transistors].
In a crystal of intrinsic or pure silicon, the atoms are held in position by covalent bonds. At very low temperatures, all the bonds are intact, and no charge carriers are avail-able to conduct electrical current. Thus, at such low tem-peratures, silicon behaves as an insulator.
At room temperature, thermal energy causes some of the covalent bonds to break, thus generating free electrons and holes that become available for current conduction.
Current in semiconductors is carried by free electrons and holes. Their numbers are equal and relatively small in intrinsic silicon.
The conductivity of silicon can be increased dramatically by introducing small amounts of appropriate impurity materials into the silicon crystal in a process called doping.
There are two kinds of doped semiconductor: n-type, in which electrons are abundant, and p-type, in which holes are abundant.
There are two mechanisms for the transport of charge car-riers in semiconductor: drift and diffusion.
Carrier drift results when an electric field E is applied across a piece of silicon. The electric field accelerate the holes in the direction of E and the electrons in the direc-tion opposite to E. These two current components add together to produce a drift current in the direction of E.
Carrier diffusion occurs when the concentration of charge carriers is made higher in one part of the silicon crystal than in other parts. To establish a steady-state diffusion current, a carrier concentration gradient must be main-tained in the silicon crystal.
A basic semiconductor structure is the pn junction. It is fabricated in a silicon crystal by creating a p region in close proximity to an n region. The pn junction is a diode and plays a dominant role in the structure and operation of transistors.
When the terminals of the pn junction are left open, no current flows externally. However, two equal and opposite currents, and , flow across the junction, and equilibrium is maintained by a built-in voltage that develops across the junction, with the n side positive relative to the p side. Note, however, that the voltage across an open junction is 0 V, since V0 is cancelled by potentials appearing at the metal-to-semiconductor con-nection interfaces.
The voltage appears across the depletion region, which extends on both sides of the junction.
The diffusion current is carried by holes diffusing from p to n and electrons diffusing from n to p. flows from p to n, which is the forward direction of the junction.
Its value depends on V0.
The drift current is carried by thermally generated minority electrons in the p material that are swept across the depletion layer into the n side, and by ther-mally generated minority holes in the n side that are swept across the depletion region into the p side. flows from n to p, in the reverse direction of the junc-tion, and its value is a strong function of temperature but independent of V0.
Forward biasing the pn junction, that is, applying an exter-nal voltage V that makes p more positive than n, reduces the barrier voltage to and results in an exponential increase in while remains unchanged. The net result is a substantial current that flows across the junction and through the external circuit. Applying a negative V reverse-biases the junction and increases the barrier voltage, with the result that is reduced to almost zero and the net current across the junc-tion becomes the very small reverse current IS.
If the reverse voltage is increased in magnitude to a value specific to the particular junction, the junction breaks down, and a large reverse current flows. The value of the reverse current must be limited by the external circuit.
Whenever the voltage across a pn junction is changed, some time has to pass before steady state is reached. This is due to the charge-storage effects in the junction, which are modeled by two capacitances: the junction capacitance and the diffusion capacitance For future reference, we present in Table 3.1 a summary of pertinent relationships and the values of physical constants.
ID IS V0 V0 ID ID IS IS V0 V – ID IS I ID IS – = ID VZ Cj Cd.
3.6 Capacitive Effects in the Junction 159 pn Table 3.1 Summary of Important Equations Quantity Relationship Values of Constants and Parameters (for Intrinsic Si at T = 300 K) Carrier concentration in intrinsic silicon (cm–3) Diffusion current density (A/cm2) Drift current density (A/cm2) /V⋅s /V⋅s Resistivity (Ω⋅cm) μp and μn decrease with the increase in doping concentration Relationship between mobility and diffusivity Carrier concentration in n-type silicon (cm –3 ) Carrier concentration in p-type silicon (cm –3 ) Junction built-in voltage (V) Width of depletion region (cm) Charge stored in depletion layer (coulomb) Forward current (A) Saturation current (A) I-V Relationship ni BT 3/2e Eg 2kT ⁄ – = B 7.3 10 15 × cm 3 – K 3/2 – = Eg 1.12 eV = k 8.62 10 5 – × eV/K = ni 1.5 1010 × /cm3 = Jp qDp dp dx ------– = Jn qDn dn dx ------= q 1.60 10 19 – × coulomb = Dp 12 cm2/s = Dn 34 cm 2/s = Jdrift q pμp nμn + ( )E = μp 480 cm2 = μn 1350 cm 2 = ρ 1 q pμp nμn + ( ) [ ] ⁄ = Dn μn ------Dp μp ------VT = = VT kT q ⁄ = 25.8 mV nn0 ND pn0 ni 2 ND ⁄ = pp0 NA np0 ni 2 NA ⁄ = V0 VT ln NAND ni 2 --------------⎝ ⎠ ⎛ ⎞ = xn xp ----NA ND -------= W xn xp + = 2εs q -------1 NA ------1 ND -------+ ⎝ ⎠ ⎛ ⎞V0 VR + ( ) = εs 11.7ε0 = ε0 8.854 10 14 – × F/cm = QJ q NAND NA ND + --------------------AW = I Ip In + = Ip Aq ni 2 Dp LpND ------------- e V VT ⁄ 1 – ( ) = In Aq ni 2 Dn LnNA ------------ e V VT ⁄ 1 – ( ) = IS Aq ni 2 Dp LpND -------------Dn LnNA ------------+ ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ = I IS eV VT ⁄ 1 – ( ) = 160 Chapter 3 Semiconductors Table 3.1 continued Quantity Relationship Values of Constants and Parameters (for Intrinsic Si at T = 300 K) Minority-carrier lifetime (s) Minority-carrier charge storage (coulomb) Depletion capacitance (F) Diffusion capacitance (F) τp Lp 2 Dp ⁄ τn Ln 2 Dn ⁄ = = Lp Ln , 1 μm to 100 μm = τp τn , 1 ns to 10 4 ns = Qp τpIp Qn τnIn = = Q Qp Qn + τTI = = Cj0 A εsq 2 -------⎝ ⎠ ⎛ ⎞ NAND NA N + D --------------------⎝ ⎠ ⎛ ⎞1 V0 -----= Cj Cj0 1 VR V0 ------+ ⎝ ⎠ ⎛ ⎞ m = m 1 3 --- to 1 2 ---= Cd τT VT ------⎝ ⎠ ⎛ ⎞I = PROBLEMS Problems are marked with asterisks to describe their degree of difficulty. Difficult problems are marked with an asterisk (); more difficult problems with two asterisks (); and very challenging and/or time-consuming problems with three asterisks (). Also, if in the following problems the need arises for the values of particular parameters or physical constants that are not stated, please consult Table 3.1.
Section 3.1: Intrinsic Semiconductors 3.1 Find values of the intrinsic carrier concentration for silicon at C, C, C, C, and C. At each temperature, what fraction of the atoms is ionized?
Recall that a silicon crystal has approximately atoms/cm3. 3.2 Calculate the value of for gallium arsenide (GaAs) at T = 300 K. The constant and the bandgap voltage Eg = 1.42 eV.
Section 3.2: Doped Semiconductors 3.3 For a p-type silicon in which the dopant concentration , find the hole and electron concentrations at T = 300 K.
3.4 For a silicon crystal doped with phosphorus, what must be if at T = 300 K the hole concentration drops below the intrinsic level by a factor of ?
3.5 In a phosphorus-doped silicon layer with impurity concentration of , find the hole and electron con-centrations at and .
Section 3.3: Current Flow in Semiconductors 3.6 A young designer, aiming to develop intuition con-cerning conducting paths within an integrated circuit, exam-ines the end-to-end resistance of a connecting bar 10 μm long, 3 μm wide, and 1 μm thick, made of various materials.
The designer considers: ni 70° – 0° 20° 100° 125° 5 1022 × ni B 3.56 1014 × = cm 3 – K 3 2 ⁄ – ( ) NA 1018 cm3 ⁄ = ND 107 1016 cm3 ⁄ 27°C 125°C Problems 161 CHAPTER 3 PR OBLEM S (a) intrinsic silicon (b) n-doped silicon with (c) n-doped silicon with (d) p-doped silicon with (e) aluminum with resistivity of 2.8 .cm Find the resistance in each case. For intrinsic silicon, use the data in Table 3.1. For doped silicon, assume V.s. (Recall that ) 3.7 Contrast the electron and hole drift velocities through a 10-μm layer of intrinsic silicon across which a voltage of 5 V is imposed. Let V.s and V.s.
3.8 Find the current that flows in a silicon bar of 10-μm length having a cross section and having free electron and hole densities of and , respectively, when a 1 V is applied end-to-end. Use V.s and V.s.
3.9 In a 10-μm long bar of donor-doped silicon, what donor concentration is needed to realize a current density of in response to an applied voltage of 1 V. (Note: Although the carrier mobilities change with doping concen-tration, as a first approximation you may assume to be constant and use the value for intrinsic silicon, V.s).
3.10 Holes are being steadily injected into a region of n-type silicon (connected to other devices, the details of which are not important for this question). In the steady state, the excess-hole concentration profile shown in Fig. P3.10 is established in the n-type silicon region. Here “excess” means over and above the thermal-equilibrium concentra-tion (in the absence of hole injection), denoted . If , , , and W = 0.1 μm, find the density of the current that will flow in the x direction. 3.11 Both the carrier mobility and diffusivity decrease as the doping concentration of silicon is increased. The table below provides a few data points for and versus dop-ing concentration. Use the Einstein relationship to obtain the corresponding values for and .
Section 3.4: The pn Junction with Open-Circuit Terminals (Equilibrium) 3.12 Calculate the built-in voltage of a junction in which the p and n regions are doped equally with atoms/cm3.
Assume . With the terminals left open, what is the width of the depletion region, and how far does it extend into the p and n regions? If the cross-sectional area of the junction is 100 μm2, find the magnitude of the charge stored on either side of the junction.
3.13 If, for a particular junction, the acceptor concentra-tion is and the donor concentration is , find the junction built-in voltage. Assume ni = . Also, find the width of the depletion region (W) and its extent in each of the p and n regions when the junction terminals are left open. Calculate the magnitude of the charge stored on either side of the junc-tion. Assume that the junction area is 400 μm2.
ND 1016 cm3 ⁄ = ND 1018 cm3 ⁄ = NA 1016 cm3 ⁄ = μΩ μn 2.5μp = 1200 cm2 ⁄ = R ρL A ⁄ = μn 1350 = cm2 ⁄ μp 480 cm2⁄ = 5-μm 4-μm × 105 cm3 ⁄ 1015 cm3 ⁄ μn 1200 cm2⁄ = μp 500 cm2⁄ = 1 mA μm2 ⁄ μn 1350 cm2⁄ pn0 ND 1016 cm3 ⁄ = ni 1.5 1010 × cm3 ⁄ = Dn = 12 cm2 s ⁄ pn(x) 108 pn0 pn0 0 W n region x Figure P3.10 Doping Concentration (carriers/cm3) mn (cm2/V·s) mp (cm2/V·s) Dn (cm2/s) Dp (cm2/s) Intrinsic 1350 480 1100 400 700 260 360 150 10 16 10 17 10 18 Table P3.11 μn μp Dn Dp 1016 ni 1.5 1010 × cm3 ⁄ = 1016 cm3 ⁄ 1015 cm3 ⁄ 1.5 1010 × cm3 ⁄ CHAPTER 3 PROB LEMS 162 Chapter 3 Semiconductors 3.14 Estimate the total charge stored in a 0.1-μm depletion layer on one side of a junction. The dop-ing concentration on that side of the junction is .
3.15 In a pn junction for which , and the deple-tion layer exists mostly on the shallowly doped side with W = 0.3 μm, find if . Also calculate .
3.16 By how much does change if or is increased by a factor of 10?
Section 3.5: The pn Junction with an Applied Voltage 3.17 If a 5-V reverse-bias voltage is applied across the junction specified in Problem 3.13, find W and .
3.18 Show that for a pn junction reverse-biased with a voltage , the depletion-layer width W and the charge stored on either side of the junction, , can be expressed as where and are the values in equilibrium.
3.19 In a forward-biased pn junction show that the ratio of the current component due to hole injection across the junc-tion to the component due to electron injection is given by Evaluate this ratio for the case , , μm, μm, Dp = , and , and hence find and for the case in which the pn junction is conducting a for-ward current I = 1 mA.
3.20 Calculate and the current I for V = 700 mV for a pn junction for which , , A = 200 μm2, , μm, μm, , and .
3.21 Assuming that the temperature dependence of arises mostly because is proportional to , use the expression for in Eq. (3.2) to determine the factor by which changes as T changes from 300 K to 305 K. This will be approximately the same factor by which changes for a C rise in temperature. What is the factor?
3.22 A junction is one in which the doping concentra-tion in the p region is much greater than that in the n region.
In such a junction, the forward current is mostly due to hole injection across the junction. Show that For the specific case in which , , μm, and μm2, find and the voltage V obtained when I = 0.5 mA. Assume operation at 300 K where .
3.23 A pn junction for which the breakdown voltage is 12 V has a rated (i.e., maximum allowable) power dissipation of 0.25 W. What continuous current in the breakdown region will raise the dissipation to half the rated value? If break-down occurs for only 10 ms in every 20 ms, what average breakdown current is allowed?
Section 3.6: Capacitive Effects in the pn Junction 3.24 For the pn junction specified in Problem 3.13, find and at V.
3.25 For a particular junction for which pF, V, and m = 1/3, find at reverse-bias voltages of 1 V and 10 V.
3.26 The junction capacitance can be thought of as that of a parallel-plate capacitor and thus given by Show that this approach leads to a formula identical to that obtained by combining Eqs. (3.43) and (3.45) [or equiva-lently, by combining Eqs. (3.47) and (3.48)].
3.27 A pn junction operating in the forward-bias region with a current I of 1 mA is found to have a diffusion capaci-tance of 10 pF. What diffusion capacitance do you expect this junction to have at I = 0.1 mA? What is the mean transit time for this junction?
3.28 For the p+n junction specified in Problem 3.22, find and calculate the excess minority carrier charge and the value of the diffusion capacitance at I = 0.2 mA.
10-μm 10-μm × 1016 cm3 ⁄ NA ND V0 ND 1016 cm3 ⁄ = QJ V0 NA ND QJ VR QJ W W0 1 VR V0 ------+ = QJ QJ0 1 VR V0 ------+ = W0 QJ0 Ip In ---- Dp Dn ------ Ln Lp ----- NA ND -------= NA 1018 cm3 ⁄ = ND 1016 cm3 ⁄ = Lp 5 = Ln 10 = 10 cm2 s ⁄ Dn 20 cm2 s ⁄ = Ip In IS NA 1017 cm3 ⁄ = ND 1016 cm3 ⁄ = ni 1.5 1010 × cm3 ⁄ = Lp 5 = Ln 10 = Dp 10 cm2 s ⁄ = Dn 18 cm2 s ⁄ = IS IS ni 2 ni ni 2 IS 5° p+n I Ip Aqni 2 Dp LpND ------------- e V VT ⁄ 1 – ( ) = ND 1016 cm3 ⁄ = Dp 10 cm2 s ⁄ = Lp 10 = A 104 = IS ni 1.5 1010 × cm3 ⁄ = Cj0 Cj VR 5 = Cj0 0.6 = V0 0.75 = Cj Cj Cj εA W ------= τp Problems 163 CHAPTER 3 PR OBLEM S 3.29 A short-base diode is one where the widths of the p and n regions are much smaller than and , respec-tively. As a result, the excess minority carrier distribution in each region is a straight line rather than the exponentials shown in Fig. 3.12.
(a) For the short-base diode, sketch a figure corresponding to Fig. 3.12 and assume as in Fig. 3.12 that .
(b) Following a derivation similar to that given in Section 3.5.2, show that if the widths of the p and n regions are denoted and then and , for (c) Also, assuming , , show that where (d) If a designer wishes to limit to 8 pF at I = 1 mA, what should be? Assume .
Ln Lp NA ND Wp Wn I Aqni 2 Dp Wn xn – ( )ND ------------------------------Dn Wp xp – ( )NA ------------------------------+ e V VT ⁄ 1 – ( ) = Qp 1 2 --- Wn xn – ( )2 Dp -------------------------Ip = 1 2 ---W n 2 Dp --------Ip Wn xn Q Qp I Ip Cd τT VT ------I = τT 1 2 ---Wn 2 Dp -------= Cd Wn Dp 10 cm2 s ⁄ = CHAPTER 4 Diodes Introduction 165 4.1 The Ideal Diode 166 4.2 Terminal Characteristics of Junction Diodes 173 4.3 Modeling the Diode Forward Characteristic 179 4.4 Operation in the Reverse Breakdown Region—Zener Diodes 189 4.5 Rectifier Circuits 194 4.6 Limiting and Clamping Circuits 207 4.7 Special Diode Types 213 Summary 215 Problems 216 165 IN THIS CHAPTER YOU WILL LEARN 1. The characteristics of the ideal diode and how to analyze and design cir-cuits containing multiple ideal diodes together with resistors and dc sources to realize useful and interesting nonlinear functions.
2. The details of the i–v characteristic of the junction diode (which was de-rived in Chapter 3) and how to use it to analyze diode circuits operating in the various bias regions: forward, reverse, and breakdown.
3. A simple but effective model of the diode i–v characteristic in the for-ward direction; the constant-voltage-drop model.
4. A powerful technique for the application and modeling of the diode (and in later chapters, transistors): dc-biasing the diode and modeling its op-eration for small signals around the dc operating point by means of the small-signal model.
5. The use of a string of forward-biased diodes and of diodes operating in the breakdown region (zener diodes), to provide constant dc voltages (voltage regulators).
6. Application of the diode in the design of rectifier circuits, which convert ac voltages to dc as needed for powering electronic equipment.
7. A number of other practical and important applications of diodes.
Introduction In Chapters 1 and 2 we dealt almost entirely with linear circuits; any nonlinearity, such as that introduced by amplifier output saturation, was treated as a problem to be solved by the circuit designer. However, there are many other signal-processing functions that can be implemented only by nonlinear circuits. Examples include the generation of dc voltages from the ac power supply, and the generation of signals of various waveforms (e.g., sinusoids, square waves, pulses). Also, digital logic and memory circuits constitute a special class of nonlinear circuits.
The simplest and most fundamental nonlinear circuit element is the diode. Just like a resistor, the diode has two terminals; but unlike the resistor, which has a linear (straight-line) relationship between the current flowing through it and the voltage appearing across it, the diode has a nonlinear i–v characteristic.
166 Chapter 4 Diodes This chapter is concerned with the study of diodes. In order to understand the essence of the diode function, we begin with a fictitious element, the ideal diode. We then introduce the silicon junction diode, explain its terminal characteristics, and provide techniques for the analysis of diode circuits. The latter task involves the important subject of device modeling.
Our study of modeling the diode characteristics will lay the foundation for our study of mod-eling transistor operation in the next two chapters.
Of the many applications of diodes, their use in the design of rectifiers (which convert ac to dc) is the most common. Therefore we shall study rectifier circuits in some detail and briefly look at a number of other diode applications. Further nonlinear circuits that utilize diodes and other devices will be found throughout the book, but particularly in Chapter 17.
The junction diode is nothing more than the pn junction we studied in Chapter 3, and most of this chapter is concerned with the study of silicon pn-junction diodes. In the last sec-tion, however, we briefly consider some specialized diode types, including the photodiode and the light-emitting diode.
4.1 The Ideal Diode 4.1.1 Current–Voltage Characteristic The ideal diode may be considered to be the most fundamental nonlinear circuit element. It is a two-terminal device having the circuit symbol of Fig. 4.1(a) and the i–v characteristic shown in Fig. 4.1(b). The terminal characteristic of the ideal diode can be interpreted as fol-lows: If a negative voltage (relative to the reference direction indicated in Fig. 4.1a) is applied to the diode, no current flows and the diode behaves as an open circuit (Fig. 4.1c).
Diodes operated in this mode are said to be reverse biased, or operated in the reverse direc-tion. An ideal diode has zero current when operated in the reverse direction and is said to be cut off, or simply off.
On the other hand, if a positive current (relative to the reference direction indicated in Fig.
4.1a) is applied to the ideal diode, zero voltage drop appears across the diode. In other words, the ideal diode behaves as a short circuit in the forward direction (Fig. 4.1d); it passes any cur-rent with zero voltage drop. A forward-biased diode is said to be turned on, or simply on.
From the above description it should be noted that the external circuit must be designed to limit the forward current through a conducting diode, and the reverse voltage across a cutoff diode, to predetermined values. Figure 4.2 shows two diode circuits that illustrate this point. In the circuit of Fig. 4.2(a) the diode is obviously conducting. Thus its voltage drop will be zero, and the current through it will be determined by the +10-V supply and the 1-kΩ resistor as 10 mA.
The diode in the circuit of Fig. 4.2(b) is obviously cut off, and thus its current will be zero, which in turn means that the entire 10-V supply will appear as reverse bias across the diode.
The positive terminal of the diode is called the anode and the negative terminal the cathode, a carryover from the days of vacuum-tube diodes. The i–v characteristic of the ideal diode (conducting in one direction and not in the other) should explain the choice of its arrow like circuit symbol. As should be evident from the preceding description, the i–v characteristic of the ideal diode is highly nonlinear; although it consists of two straight-line segments, they are at 90° to one another. A nonlinear curve that consists of straight-line segments is said to be piecewise linear. If a device having a piecewise-linear characteristic is used in a particular application in such a way that the signal across its terminals swings along only one of the linear 4.1 The Ideal Diode 167 segments, then the device can be considered a linear circuit element as far as that particular circuit application is concerned. On the other hand, if signals swing past one or more of the break points in the characteristic, linear analysis is no longer possible.
4.1.2 A Simple Application: The Rectifier A fundamental application of the diode, one that makes use of its severely nonlinear i–v curve, is the rectifier circuit shown in Fig. 4.3(a). The circuit consists of the series connection of a diode D and a resistor R. Let the input voltage vI be the sinusoid shown in Fig. 4.3(b), and assume the Figure 4.1 The ideal diode: (a) diode circuit symbol; (b) i–v characteristic; (c) equivalent circuit in the reverse direction; (d) equivalent circuit in the forward direction.
i v (a) (b) Figure 4.2 The two modes of operation of ideal diodes and the use of an external circuit to limit (a) the forward current and (b) the reverse voltage.
168 Chapter 4 Diodes diode to be ideal. During the positive half-cycles of the input sinusoid, the positive vI will cause current to flow through the diode in its forward direction. It follows that the diode voltage vD will be very small—ideally zero. Thus the circuit will have the equivalent shown in Fig. 4.3(c), and the output voltage vO will be equal to the input voltage vI. On the other hand, during the negative half-cycles of vI , the diode will not conduct. Thus the circuit will have the equivalent shown in Fig. 4.3(d), and vO will be zero. Thus the output voltage will have the waveform shown in Fig. 4.3(e). Note that while vI alternates in polarity and has a zero average value, vO is unidirectional and has a finite average value or a dc compo-nent. Thus the circuit of Fig. 4.3(a) rectifies the signal and hence is called a rectifier. It can be used to generate dc from ac. We will study rectifier circuits in Section 4.5.
Figure 4.3 (a) Rectifier circuit. (b) Input waveform. (c) Equivalent circuit when vI ≥ 0. (d) Equivalent circuit when vI ≤ 0. (e) Output waveform.
D (a) (b) vI 0 (d) vI 0 (c) (e) 4.1 The Ideal Diode 169 4.1 For the circuit in Fig. 4.3(a), sketch the transfer characteristic vO versus vI.
Ans. See Fig. E4.1.
4.2 For the circuit in Fig. 4.3(a), sketch the waveform of vD.
Ans. vD = vI – vO, resulting in the waveform in Fig. E4.2 4.3 In the circuit of Fig. 4.3(a), let vI have a peak value of 10 V and R = 1 kΩ. Find the peak value of iD and the dc component of vO.
Ans. 10 mA; 3.18 V Figure E4.1 Figure E4.2 EXERCISES Figure 4.4(a) shows a circuit for charging a 12-V battery. If vS is a sinusoid with 24-V peak ampli-tude, find the fraction of each cycle during which the diode conducts. Also, find the peak value of the diode current and the maximum reverse-bias voltage that appears across the diode.
Example 4.1 170 Chapter 4 Diodes 4.1.3 Another Application: Diode Logic Gates Diodes together with resistors can be used to implement digital logic functions. Figure 4.5 shows two diode logic gates. To see how these circuits function, consider a positive-logic system in which voltage values close to 0 V correspond to logic 0 (or low) and voltage values close to +5 V correspond to logic 1 (or high). The circuit in Fig. 4.5(a) has three inputs, vA, vB, and vC. It is easy to see that diodes connected to +5-V inputs will conduct, thus clamping the output vY to a value equal to +5 V. This positive voltage at the output will keep the diodes whose inputs are low (around 0 V) cut off. Thus the output will be high if one or more of the inputs are high. The circuit therefore implements the logic OR function, which in Boolean notation is expressed as Similarly, the reader is encouraged to show that using the same logic system mentioned above, the circuit of Fig. 4.5(b) implements the logic AND function, Y A B C + + = Y A B C ⋅ ⋅ = Example 4.1 continued Solution The diode conducts when vS exceeds 12 V, as shown in Fig. 4.4(b). The conduction angle is 2θ, where θ is given by Thus θ = 60° and the conduction angle is 120°, or one-third of a cycle.
The peak value of the diode current is given by The maximum reverse voltage across the diode occurs when vS is at its negative peak and is equal to 24 + 12 = 36 V.
Figure 4.4 Circuit and waveforms for Example 4.1.
(a) (b) 24 cosθ 12 = Id 24 12 – 100 ------------------0.12 A = = 4.1 The Ideal Diode 171 Assuming the diodes to be ideal, find the values of I and V in the circuits of Fig. 4.6.
Solution In these circuits it might not be obvious at first sight whether none, one, or both diodes are conducting.
In such a case, we make a plausible assumption, proceed with the analysis, and then check whether we end up with a consistent solution. For the circuit in Fig. 4.6(a), we shall assume that both diodes are conducting. It follows that VB = 0 and V = 0. The current through D2 can now be determined from Figure 4.6 Circuits for Example 4.2.
D D (a) D D (b) Figure 4.5 Diode logic gates: (a) OR gate; (b) AND gate (in a positive-logic system).
(a) (b) Example 4.2 172 Chapter 4 Diodes Example 4.2 continued Writing a node equation at B, results in I = 1 mA. Thus D1 is conducting as originally assumed, and the final result is I = 1 mA and V = 0 V.
For the circuit in Fig. 4.6(b), if we assume that both diodes are conducting, then VB = 0 and V = 0. The current in D2 is obtained from The node equation at B is which yields I = −1 mA. Since this is not possible, our original assumption is not correct. We start again, assuming that D1 is off and D2 is on. The current ID2 is given by and the voltage at node B is Thus D1 is reverse biased as assumed, and the final result is I = 0 and V = 3.3 V.
ID2 10 0 – 10 ---------------1 mA = = I 1 + 0 10 – ( ) – 5 -----------------------= ID2 10 0 – 5 ---------------2 mA = = I 2 + 0 10 – ( ) – 10 -----------------------= ID2 10 10 – ( ) – 15 --------------------------1.33 mA = = VB –10 10 1.33 × + +3.3 V = = EXERCISES 4.4 Find the values of I and V in the circuits shown in Fig. E4.4.
(a) (b) (d) (c) Figure E4.4 (c) 4.2 Terminal Characteristics of Junction Diodes 173 4.2 Terminal Characteristics of Junction Diodes The most common implementation of the diode utilizes a pn junction. We have studied the physics of the pn junction and derived its i–v characteristic in Chapter 3. That the pn junc-tion is used to implement the diode function should come as no surprise: the pn junction can conduct substantial current in the forward direction and almost no current in the reverse direction. In this section we study the i–v characteristic of the pn junction diode in detail in order to prepare ourselves for diode circuit applications.
Figure 4.7 shows the i–v characteristic of a silicon junction diode. The same characteris-tic is shown in Fig. 4.8 with some scales expanded and others compressed to reveal details.
Note that the scale changes have resulted in the apparent discontinuity at the origin.
Ans. (a) 2 mA, 0 V; (b) 0 mA, 5 V; (c) 0 mA, 5 V; (d) 2 mA, 0 V; (e) 3 mA, +3 V; (f) 4 mA, +1 V 4.5 Figure E4.5 shows a circuit for an ac voltmeter. It utilizes a moving-coil meter that gives a full-scale read-ing when the average current flowing through it is 1 mA. The moving-coil meter has a 50-Ω resistance.
Find the value of R that results in the meter indicating a full-scale reading when the input sine-wave voltage vI is 20 V peak-to-peak. (Hint: The average value of half-sine waves is Vp/π.) Ans. 3.133 kΩ (e) (f) Figure E4.4 (Continued) Moving-coil meter Figure E4.5 174 Chapter 4 Diodes As indicated, the characteristic curve consists of three distinct regions: 1. The forward-bias region, determined by v > 0 2. The reverse-bias region, determined by v < 0 3. The breakdown region, determined by v < –VZK These three regions of operation are described in the following sections.
Figure 4.7 The i–v characteristic of a silicon junction diode.
Figure 4.8 The diode i–v relationship with some scales expanded and others compressed in order to reveal details.
4.2 Terminal Characteristics of Junction Diodes 175 4.2.1 The Forward-Bias Region The forward-bias—or simply forward—region of operation is entered when the terminal voltage v is positive. In the forward region the i–v relationship is closely approximated by (4.1) In this equation1 IS is a constant for a given diode at a given temperature. A formula for IS in terms of the diode’s physical parameters and temperature was given in Eq.(3.41). The cur-rent IS is usually called the saturation current (for reasons that will become apparent shortly). Another name for IS , and one that we will occasionally use, is the scale current.
This name arises from the fact that IS is directly proportional to the cross-sectional area of the diode. Thus doubling of the junction area results in a diode with double the value of IS and, as the diode equation indicates, double the value of current i for a given forward voltage v. For “small-signal” diodes, which are small-size diodes intended for low-power applica-tions, IS is on the order of 10–15 A. The value of IS is, however, a very strong function of tem-perature. As a rule of thumb, IS doubles in value for every 5°C rise in temperature.
The voltage VT in Eq. (4.1) is a constant called the thermal voltage and is given by (4.2) where k = Boltzmann’s constant = 8.62 × 10–5 eV/K = 1.38 × 10–23 joules/kelvin T = the absolute temperature in kelvins = 273 + temperature in °C q = the magnitude of electronic charge = 1.60 × 10–19 coulomb Substituting k = 8.62 × 10–5 eV/K into Eq. (4.2) gives mV (4.2a) Thus, at room temperature (20°C) the value of VT is 25.3 mV. In rapid approximate circuit analysis we shall use VT 25 mV at room temperature.2 For appreciable current i in the forward direction, specifically for i IS , Eq. (4.1) can be approximated by the exponential relationship i ISev/V T (4.3) This relationship can be expressed alternatively in the logarithmic form (4.4) where ln denotes the natural (base e) logarithm.
1Equation (4.1), the diode equation, is sometimes written to include a constant n in the exponential, i = IS (ev/nkt–1) with n having a value between 1 and 2, depending on the material and the physical structure of the diode.
Diodes using the standard integrated-circuit fabrication process exhibit n = 1 when operated under nor-mal conditions. For simplicity, we shall use n = 1 throughout this book, unless otherwise specified.
2A slightly higher ambient temperature (25°C or so) is usually assumed for electronic equipment oper-ating inside a cabinet. At this temperature, VT 25.8 mV. Nevertheless, for the sake of simplicity and to promote rapid circuit analysis, we shall use the more arithmetically convenient value of VT 25 mV throughout this book.
i IS ev VT ⁄ 1 – ( ) = VT kT q ------= VT 0.0862T, = v VT i IS ----ln = 176 Chapter 4 Diodes The exponential relationship of the current i to the voltage v holds over many decades of current (a span of as many as seven decades—i.e., a factor of 107—can be found). This is quite a remarkable property of junction diodes, one that is also found in bipolar junction tran-sistors and that has been exploited in many interesting applications.
Let us consider the forward i–v relationship in Eq. (4.3) and evaluate the current I1 corresponding to a diode voltage V1: Similarly, if the voltage is V2, the diode current I2 will be These two equations can be combined to produce which can be rewritten as or, in terms of base-10 logarithms, (4.5) This equation simply states that for a decade (factor of 10) change in current, the diode volt-age drop changes by 2.3VT , which is approximately 60 mV. This also suggests that the diode i–v relationship is most conveniently plotted on semilog paper. Using the vertical, linear axis for v and the horizontal, log axis for i, one obtains a straight line with a slope of 60 mV per decade of current.
A glance at the i–v characteristic in the forward region (Fig. 4.8) reveals that the current is negligibly small for v smaller than about 0.5 V. This value is usually referred to as the cut-in voltage. It should be emphasized, however, that this apparent threshold in the characteris-tic is simply a consequence of the exponential relationship. Another consequence of this rela-tionship is the rapid increase of i. Thus, for a “fully conducting” diode, the voltage drop lies in a narrow range, approximately 0.6 V to 0.8 V. This gives rise to a simple “model” for the diode where it is assumed that a conducting diode has approximately a 0.7-V drop across it.
Diodes with different current ratings (i.e., different areas and correspondingly different IS) will exhibit the 0.7-V drop at different currents. For instance, a small-signal diode may be considered to have a 0.7-V drop at i = 1 mA, while a higher-power diode may have a 0.7-V drop at i = 1 A. We will study the topics of diode-circuit analysis and diode models in the next section.
I1 ISe V1 VT ⁄ = I2 ISe V2 VT ⁄ = I2 I1 ----e V2 V1 – ( ) VT ⁄ = V2 V1 – VT I2 I1 ----ln = V2 V1 – 2.3VT I2 I1 ----log = A silicon diode said to be a 1-mA device displays a forward voltage of 0.7 V at a current of 1 mA.
Evaluate the junction scaling constant IS. What scaling constants would apply for a 1-A diode of the same manufacture that conducts 1 A at 0.7 V?
Example 4.3 4.2 Terminal Characteristics of Junction Diodes 177 4.6 Find the change in diode voltage if the current changes from 0.1 mA to 10 mA.
Ans. 120 mV 4.7 A silicon junction diode has v = 0.7 V at i = 1 mA. Find the voltage drop at i = 0.1 mA and i = 10 mA.
Ans. 0.64 V; 0.76 V 4.8 Using the fact that a silicon diode has IS = 10−14 A at 25°C and that IS increases by 15% per °C rise in temperature, find the value of IS at 125°C. Ans. 1.17 × 10−8 A EXERCISES Solution Since then For the 1-mA diode: IS = 10−3e−700/25 = 6.9 × 10−16 A The diode conducting 1 A at 0.7 V corresponds to one-thousand 1-mA diodes in parallel with a total junction area 1000 times greater. Thus IS is also 1000 times greater, IS = 6.9 × 10−13 A Since both IS and VT are functions of temperature, the forward i–v characteristic varies with tem-perature, as illustrated in Fig. 4.9. At a given constant diode current, the voltage drop across the diode decreases by approximately 2 mV for every 1°C increase in temperature. The change in diode volt-age with temperature has been exploited in the design of electronic thermometers.
i ISev VT ⁄ = IS ie v VT ⁄ – = Figure 4.9 Temperature dependence of the diode forward characteristic. At a constant current, the voltage drop decreases by approxi-mately 2 mV for every 1°C increase in tempera-ture.
178 Chapter 4 Diodes 4.2.2 The Reverse-Bias Region The reverse-bias region of operation is entered when the diode voltage v is made negative. Equa-tion (4.1) predicts that if v is negative and a few times larger than VT (25 mV) in magnitude, the exponential term becomes negligibly small compared to unity, and the diode current becomes i –IS That is, the current in the reverse direction is constant and equal to IS. This constancy is the reason behind the term saturation current.
Real diodes exhibit reverse currents that, though quite small, are much larger than IS. For instance, a small-signal diode whose IS is on the order of 10−14 A to 10−15 A could show a reverse current on the order of 1 nA. The reverse current also increases somewhat with the increase in magnitude of the reverse voltage. Note that because of the very small magnitude of the current, these details are not clearly evident on the diode i–v characteristic of Fig. 4.8. A large part of the reverse current is due to leakage effects. These leakage currents are proportional to the junction area, just as IS is. Their dependence on temperature, however, is different from that of IS. Thus, whereas IS doubles for every 5°C rise in temperature, the corre-sponding rule of thumb for the temperature dependence of the reverse current is that it dou-bles for every 10°C rise in temperature.
4.2.3 The Breakdown Region The third distinct region of diode operation is the breakdown region, which can be easily identified on the diode i–v characteristic in Fig. 4.8. The breakdown region is entered when the magnitude of the reverse voltage exceeds a threshold value that is specific to the particular diode, called the breakdown voltage. This is the voltage at the “knee” of the i–v curve in Fig. 4.8 and is denoted VZK, where the subscript Z stands for zener (see Section 3.5.3) and K denotes knee.
4.9 The diode in the circuit of Fig. E4.9 is a large high-current device whose reverse leakage is reasonably independent of voltage. If V = 1 V at 20°C, find the value of V at 40°C and at 0°C.
Ans. 4 V; 0.25 V Figure E4.9 EXERCISE 4.3 Modeling the Diode Forward Characteristic 179 As can be seen from Fig. 4.8, in the breakdown region the reverse current increases rap-idly, with the associated increase in voltage drop being very small. Diode breakdown is nor-mally not destructive, provided the power dissipated in the diode is limited by external circuitry to a “safe” level. This safe value is normally specified on the device data sheets. It therefore is necessary to limit the reverse current in the breakdown region to a value consis-tent with the permissible power dissipation.
The fact that the diode i–v characteristic in breakdown is almost a vertical line enables it to be used in voltage regulation. This subject will be studied in Section 4.5.
4.3 Modeling the Diode Forward Characteristic Having studied the diode terminal characteristics we are now ready to consider the analysis of circuits employing forward-conducting diodes. Figure 4.10 shows such a circuit. It consists of a dc source VDD, a resistor R, and a diode. We wish to analyze this circuit to determine the diode voltage VD and current ID. Toward that end we consider developing a variety of models for the operation of the diode. We already know of two such models: the ideal-diode model, and the exponential model. In the following discussion we shall assess the suitability of these two mod-els in various analysis situations. Also, we shall develop and comment on other models. This material, besides being useful in the analysis and design of diode circuits, establishes a founda-tion for the modeling of transistor operation that we will study in the next two chapters.
4.3.1 The Exponential Model The most accurate description of the diode operation in the forward region is provided by the exponential model. Unfortunately, however, its severely nonlinear nature makes this model the most difficult to use. To illustrate, let’s analyze the circuit in Fig. 4.10 using the exponential diode model.
Assuming that VDD is greater than 0.5 V or so, the diode current will be much greater than IS, and we can represent the diode i–v characteristic by the exponential relationship, resulting in (4.6) The other equation that governs circuit operation is obtained by writing a Kirchhoff loop equation, resulting in (4.7) Assuming that the diode parameter IS is known, Eqs. (4.6) and (4.7) are two equations in the two unknown quantities ID and VD. Two alternative ways for obtaining the solution are graphical analysis and iterative analysis.
ID ISe VD VT ⁄ = ID VDD VD – R ---------------------= Figure 4.10 A simple circuit used to illustrate the analysis of circuits in which the diode is forward conducting.
180 Chapter 4 Diodes Example 4.4 4.3.2 Graphical Analysis Using the Exponential Model Graphical analysis is performed by plotting the relationships of Eqs. (4.6) and (4.7) on the i–v plane. The solution can then be obtained as the coordinates of the point of intersection of the two graphs. A sketch of the graphical construction is shown in Fig. 4.11. The curve rep-resents the exponential diode equation (Eq. 4.6), and the straight line represents Eq. (4.7).
Such a straight line is known as the load line, a name that will become more meaningful in later chapters. The load line intersects the diode curve at point Q, which represents the operating point of the circuit. Its coordinates give the values of ID and VD.
Graphical analysis aids in the visualization of circuit operation. However, the effort involved in performing such an analysis, particularly for complex circuits, is too great to be justi-fied in practice.
4.3.3 Iterative Analysis Using the Exponential Model Equations (4.6) and (4.7) can be solved using a simple iterative procedure, as illustrated in the following example.
Figure 4.11 Graphical analysis of the circuit in Fig. 4.10 using the exponential diode model.
Determine the current ID and the diode voltage VD for the circuit in Fig. 4.10 with VDD = 5 V and R = 1 kΩ. Assume that the diode has a current of 1 mA at a voltage of 0.7 V.
Solution To begin the iteration, we assume that VD = 0.7 V and use Eq. (4.7) to determine the current, ID VDD VD – R ----------------------= 5 0.7 – 1 ----------------4.3 mA = = 4.3 Modeling the Diode Forward Characteristic 181 4.3.4 The Need for Rapid Analysis The iterative analysis procedure utilized in the example above is simple and yields accurate results after two or three iterations. Nevertheless, there are situations in which the effort and time required are still greater than can be justified. Specifically, if one is doing a pencil-and-paper design of a relatively complex circuit, rapid circuit analysis is a necessity. Through quick analysis, the designer is able to evaluate various possibilities before deciding on a suitable circuit design. To speed up the analysis process one must be content with less precise results. This, however, is seldom a problem, because the more accurate analysis can be post-poned until a final or almost-final design is obtained. Accurate analysis of the almost-final design can be performed with the aid of a computer circuit-analysis program such as SPICE (see Appendix B and the disc). The results of such an analysis can then be used to further refine or “fine-tune” the design.
To speed up the analysis process, we must find a simpler model for the diode forward characteristic.
4.3.5 The Constant-Voltage-Drop Model The simplest and most widely used diode model is the constant-voltage-drop model. This model is based on the observation that a forward-conducting diode has a voltage drop that varies in a relatively narrow range, say 0.6 to 0.8 V. The model assumes this voltage to be constant at a value, say, 0.7 V. This development is illustrated in Fig. 4.12.
We then use the diode equation to obtain a better estimate for VD. This can be done by employing Eq. (4.5), namely, Subsituting 2.3VT = 60 mV, we have Substituting V1 = 0.7 V, I1 = 1 mA, and I2 = 4.3 mA results in V2 = 0.738 V. Thus the results of the first iter-ation are ID = 4.3 mA and VD = 0.738 V. The second iteration proceeds in a similar manner: Thus the second iteration yields ID = 4.262 mA and VD = 0.738 V. Since these values are very close to the values obtained after the first iteration, no further iterations are necessary, and the solution is ID = 4.262 mA and VD = 0.738 V.
V2 V1 – 2.3VT I2 I1 ----log = V2 V1 0.06 + I2 I1 ----log = ID 5 0.738 – 1 ----------------------4.262 mA = = V2 0.738 0.06 log 4.262 4.3 -------------+ = 0.738 V = 182 Chapter 4 Diodes The constant-voltage-drop model is the one most frequently employed in the initial phases of analysis and design. This is especially true if at these stages one does not have detailed information about the diode characteristics, which is often the case.
Finally, note that if we employ the constant-voltage-drop model to solve the problem in Example 4.4, we obtain and which are not very different from the values obtained before with the more elaborate expo-nential model.
(c) vD i 0, vD 0.7 V i (a) (b) i v 0.7 V 0 i v 0.7 V 0 Figure 4.12 Development of the diode constant-voltage-drop model: (a) the exponential character-stic; (b) approximating the exponential characteristic by a constant voltage, usually about 0.7 Vi; (c) the resulting model of the foward–conducting diodes.
VD 0.7 V = ID VDD 0.7 – R ----------------------= 5 0.7 – 1 ----------------= 4.3 mA = 4.3 Modeling the Diode Forward Characteristic 183 4.3.6 The Ideal-Diode Model In applications that involve voltages much greater than the diode voltage drop (0.6 V–0.8 V), we may neglect the diode voltage drop altogether while calculating the diode current. The result is the ideal-diode model, which we studied in Section 4.1. For the circuit in Examples 4.4 (i.e., Fig. 4.10 with VDD = 5 V and R = 1 kΩ), utilization of the ideal-diode model leads to which for a very quick analysis would not be bad as a gross estimate. However, with almost no additional work, the 0.7-V-drop model yields much more realistic results. We note, how-ever, that the greatest utility of the ideal-diode model is in determining which diodes are on and which are off in a multidiode circuit, such as those considered in Section 4.1.
VD 0 V = ID 5 0 – 1 ------------5 mA = = 4.10 For the circuit in Fig. 4.10, find ID and VD for the case VDD = 5 V and R = 10 kΩ. Assume that the diode has a voltage of 0.7 V at 1-mA current. Use (a) iteration and (b) the constant-voltage-drop model with VD = 0.7 V.
Ans. (a) 0.43 mA, 0.68 V; (b) 0.43 mA, 0.7 V D4.11 Design the circuit in Fig. E4.11 to provide an output voltage of 2.4 V. Assume that the diodes available have 0.7-V drop at 1 mA.
Ans. R = 139 Ω 4.12 Repeat Exercise 4.4 using the 0.7-V-drop model to obtain better estimates of I and V than those found in Exercise 4.4 (using the ideal-diode model).
Ans. (a) 1.72 mA, 0.7 V; (b) 0 mA, 5 V; (c) 0 mA, 5 V; (d) 1.72 mA, 0.7 V; (e) 2.3 mA, +2.3 V; (f) 3.3 mA, +1.7 V Figure E4.11 EXERCISES 184 Chapter 4 Diodes 4.3.7 The Small-Signal Model There are applications in which a diode is biased to operate at a point on the forward i–v characteristic and a small ac signal is superimposed on the dc quantities. For this situation, we first have to determine the dc operating point (VD and ID) of the diode using one of the models discussed above. Most frequently, the 0.7-V-drop model is utilized. Then, for small-signal operation around the dc bias point, the diode is modeled by a resistance equal to the inverse of the slope of the tangent to the exponential i–v characteristic at the bias point.
The technique of biasing a nonlinear device and restricting signal excursion to a short, almost-linear segment of its characteristic around the bias point is central to designing linear amplifiers using transistors, as will be seen in the next two chapters. In this section, we develop such a small-signal model for the junction diode and illustrate its application. Figure 4.13 Development of the diode small-signal model.
4.3 Modeling the Diode Forward Characteristic 185 Consider the conceptual circuit in Fig. 4.13(a) and the corresponding graphical represen-tation in Fig. 4.13(b). A dc voltage V D, represented by a battery, is applied to the diode, and a time-varying signal vd(t), assumed (arbitrarily) to have a triangular waveform, is superimposed on the dc voltage V D. In the absence of the signal vd(t), the diode voltage is equal to V D, and correspondingly, the diode will conduct a dc current ID given by (4.8) When the signal vd(t) is applied, the total instantaneous diode voltage vD(t) will be given by (4.9) Correspondingly, the total instantaneous diode current iD(t) will be (4.10) Substituting for vD from Eq. (4.9) gives (4.11) which can be rewritten Using Eq. (4.8) we obtain (4.12) Now if the amplitude of the signal vd(t) is kept sufficiently small such that (4.13) then we may expand the exponential of Eq. (4.12) in a series and truncate the series after the first two terms to obtain the approximate expression (4.14) This is the small-signal approximation. It is valid for signals whose amplitudes are smaller than about 5 mV (see Eq. 4.13, and recall that VT = 25 mV).3 From Eq. (4.14) we have (4.15) Thus, superimposed on the dc current ID, we have a signal current component directly pro-portional to the signal voltage vd. That is, (4.16) where (4.17) 3For vd = 5 mV, . Thus the next term in the series expansion of the exponential will be × 0.22 = 0.02, a factor of 10 lower than the linear term we kept.
ID ISe VD VT ⁄ = vD t ( ) V D vd t ( ) + = iD t ( ) ISevD VT ⁄ = iD t ( ) ISe VD+vd ( ) VT ⁄ = iD t ( ) ISe VD VT ⁄ evd VT ⁄ = iD t ( ) IDevd VT ⁄ = vd VT ----- 1 iD t ( ) ID 1 vd VT -----+ ⎝ ⎠ ⎛ ⎞ vd VT ⁄ = 0.2 1 2 ---iD t ( ) ID ID VT -----vd + = iD ID id + = id ID VT -----vd = 186 Chapter 4 Diodes The quantity relating the signal current id to the signal voltage vd has the dimensions of con-ductance, mhos ( ), and is called the diode small-signal conductance. The inverse of this parameter is the diode small-signal resistance, or incremental resistance, rd, (4.18) Note that the value of rd is inversely proportional to the bias current ID.
Let us return to the graphical representation in Fig. 4.13(b). It is easy to see that using the small-signal approximation is equivalent to assuming that the signal amplitude is sufficiently small such that the excursion along the i–v curve is limited to a short almost-linear segment.
The slope of this segment, which is equal to the slope of the tangent to the i–v curve at the operating point Q, is equal to the small-signal conductance. The reader is encouraged to prove that the slope of the i–v curve at i = ID is equal to which is that is, (4.19) From the preceding we conclude that superimposed on the quantities VD and ID that define the dc bias point, or quiescent point, of the diode will be the small-signal quantities vd(t) and id(t), which are related by the diode small-signal resistance rd evaluated at the bias point (Eq.
4.18). Thus the small-signal analysis can be performed separately from the dc bias analysis, a great convenience that results from the linearization of the diode characteristics inherent in the small-signal approximation. Specifically, after the dc analysis is performed, the small-signal equivalent circuit is obtained by eliminating all dc sources (i.e., short-circuiting dc voltage sources and open-circuiting dc current sources) and replacing the diode by its small-signal resis-tance. The following example should illustrate the application of the small-signal model.
Ω rd VT ID -----= ID VT, ⁄ 1 rd; ⁄ rd = 1 ∂iD ∂vD ---------iD=ID Consider the circuit shown in Fig. 4.14(a) for the case in which R = 10 kΩ. The power supply V+ has a dc value of 10 V on which is superimposed a 60-Hz sinusoid of 1-V peak amplitude. (This “signal” compo-nent of the power-supply voltage is an imperfection in the power-supply design. It is known as the power-supply ripple. More on this later.) Calculate both the dc voltage of the diode and the amplitude of the sine-wave signal appearing across it. Assume the diode to have a 0.7-V drop at 1-mA current.
Figure 4.14 (a) Circuit for Example 4.5. (b) Circuit for calculating the dc operating point. (c) Small-signal equivalent circuit.
(a) (b) R ID 10 V VD (c) R vd vs rd Example 4.5 4.3 Modeling the Diode Forward Characteristic 187 Finally, we note that while rd models the small-signal operation of the diode at low frequen-cies, its dynamic operation is modeled by the capacitances Cj and Cd, which we studied in Sec-tion 3.6 and which also are small-signal parameters. A complete model of the diode includes Cj and Cd in parallel with rd.
4.3.8 Use of the Diode Forward Drop in Voltage Regulation A further application of the diode small-signal model is found in a popular diode application, namely, the use of diodes to create a regulated voltage. A voltage regulator is a circuit whose purpose is to provide a constant dc voltage between its output terminals. The output voltage is required to remain as constant as possible in spite of (a) changes in the load current drawn from the regulator output terminal and (b) changes in the dc power-supply voltage that feeds the regulator circuit. Since the forward-voltage drop of the diode remains almost constant at approximately 0.7 V while the current through it varies by relatively large amounts, a forward-biased diode can make a simple voltage regulator. For instance, we have seen in Example 4.5 that while the 10-V dc supply voltage had a ripple of 2 V peak-to-peak (a ±10% variation), the corresponding ripple in the diode voltage was only about ±2.7 mV (a ±0.4% variation). Regu-lated voltages greater than 0.7 V can be obtained by connecting a number of diodes in series.
For example, the use of three forward-biased diodes in series provides a voltage of about 2 V.
One such circuit is investigated in the following example, which utilizes the diode small-signal model to quantify the efficacy of the voltage regulator that is realized.
Solution Considering dc quantities only, we assume VD 0.7 V and calculate the diode dc current Since this value is very close to 1 mA, the diode voltage will be very close to the assumed value of 0.7 V. At this operating point, the diode incremental resistance rd is The signal voltage across the diode can be found from the small-signal equivalent circuit in Fig. 4.14(c). Here vs denotes the 60-Hz 1-V peak sinusoidal component of V +, and vd is the cor-responding signal across the diode. Using the voltage-divider rule provides the peak amplitude of vd as follows: Finally we note that since this value is quite small, our use of the small-signal model of the diode is justified.
ID = 10 0.7 – 10 -------------------0.93 mA = rd VT ID ------25 0.93 ----------26.9 Ω = = = vd peak ( ) V ˆ s rd R rd + --------------= 1 0.0269 10 0.0269 + ----------------------------= 2.68 mV = 188 Chapter 4 Diodes Consider the circuit shown in Fig. 4.15. A string of three diodes is used to provide a constant voltage of about 2.1 V. We want to calculate the percentage change in this regulated voltage caused by (a) a ±10% change in the power-supply voltage and (b) connection of a 1-kΩ load resistance.
Solution With no load, the nominal value of the current in the diode string is given by Thus each diode will have an incremental resistance of Thus, The three diodes in series will have a total incremental resistance of This resistance, along with the resistance R, forms a voltage divider whose ratio can be used to cal-culate the change in output voltage due to a ±10% (i.e., ±1-V) change in supply voltage. Thus the peak-to-peak change in output voltage will be peak-to-peak That is, corresponding to the ±1-V (±10%) change in supply voltage, the output voltage will change by ±9.5 mV or ±0.5%. Since this implies a change of about ±3.2 mV per diode, our use of the small-signal model is justified.
When a load resistance of 1 kΩ is connected across the diode string, it draws a current of approximately 2.1 mA. Thus the current in the diodes decreases by 2.1 mA, resulting in a decrease in voltage across the diode string given by vO 10 1 V R = 1 k RL = 1 k Figure 4.15 Circuit for Example 4.6.
I 10 2.1 – 1 -------------------7.9 mA = = rd VT I ------= rd 25 7.9 -------3.2 Ω = = r 3rd 9.6 Ω = = ΔvO 2 r r R + ------------2 0.0096 0.0096 1 + -------------------------19 mV = = = ΔvO 2.1 r × – 2.1 9.6 × – 20 mV – = = = Example 4.6 4.4 Operation in the Reverse Breakdown Region—Zener Diodes 189 Since this implies that the voltage across each diode decreases by about 6.7 mV, our use of the small-signal model is not entirely justified. Nevertheless, a detailed calculation of the voltage change using the exponential model results in which is not too different from the approximate value obtained using the incremental model.
ΔvO = 23 mV, – 4.13 Find the value of the diode small-signal resistance rd at bias currents of 0.1 mA, 1 mA, and 10 mA.
Ans. 250 Ω; 25 Ω; 2.5 Ω 4.14 Consider a diode biased at 1 mA. Find the change in current as a result of changing the voltage by (a) −10 mV, (b) −5 mV, (c) +5 mV, and (d) +10 mV. In each case, do the calculations (i) using the small-signal model and (ii) using the exponential model.
Ans. (a) −0.40, −0.33 mA; (b) −0.20, −0.18 mA; (c) +0.20, +0.22 mA; (d) +0.40, +0.49 mA D4.15 Design the circuit of Fig. E4.15 so that VO = 3 V when IL = 0, and VO changes by 20 mV per 1 mA of load current. (a) Use the small-signal model of the diode to find the value of R.
(b) Specify the value of IS of each of the diodes.
(c) For this design, use the diode exponential model to determine the actual change in VO when a current IL = 1 mA is drawn from the regulator.
Ans. (a) R = 2.4 kΩ; (b) IS = 4.7 1016 A; (c) 22.3 mV 15 V VO IL R EXERCISES 4.4 Operation in the Reverse Breakdown Region—Zener Diodes The very steep i–v curve that the diode exhibits in the breakdown region (Fig. 4.8) and the almost-constant voltage drop that this indicates, suggest that diodes operating in the breakdown region can be used in the design of voltage regulators. From the previous section, the reader Figure E4.15 190 Chapter 4 Diodes will recall that voltage regulators are circuits that provide a constant dc output voltage in the face of changes in their load current and in the system power-supply voltage. This in fact turns out to be an important application of diodes operating in the reverse-breakdown region, and special diodes are manufactured to operate specifically in the breakdown region. Such diodes are called breakdown diodes or, more commonly, as noted earlier, zener diodes.
Figure 4.16 shows the circuit symbol of the zener diode. In normal applications of zener diodes, current flows into the cathode, and the cathode is positive with respect to the anode.
Thus IZ and VZ in Fig. 4.16 have positive values.
4.4.1 Specifying and Modeling the Zener Diode Figure 4.17 shows details of the diode i–v characteristic in the breakdown region. We observe that for currents greater than the knee current IZK (specified on the data sheet of the zener diode), the i–v characteristic is almost a straight line. The manufacturer usually specifies the voltage across the zener diode VZ at a specified test current, IZT. We have indi-cated these parameters in Fig. 4.17 as the coordinates of the point labeled Q. Thus a 6.8-V IZ VZ Figure 4.16 Circuit symbol for a zener diode.
v IZT I VZ0 VZK IZK i 0 Q rz V V I VZ Slope 1 rz (test current) Figure 4.17 The diode i–v characteristic with the breakdown region shown in some detail.
4.4 Operation in the Reverse Breakdown Region—Zener Diodes 191 zener diode will exhibit a 6.8-V drop at a specified test current of, say, 10 mA. As the cur-rent through the zener deviates from IZT, the voltage across it will change, though only slightly. Figure 4.17 shows that corresponding to current change ΔI the zener voltage changes by ΔV, which is related to ΔI by where rz is the inverse of the slope of the almost-linear i–v curve at point Q. Resistance rz is the incremental resistance of the zener diode at operating point Q. It is also known as the dynamic resistance of the zener, and its value is specified on the device data sheet. Typi-cally, rz is in the range of a few ohms to a few tens of ohms. Obviously, the lower the value of rz is, the more constant the zener voltage remains as its current varies, and thus the more ideal its performance becomes in the design of voltage regulators. In this regard, we observe from Fig. 4.17 that while rz remains low and almost constant over a wide range of current, its value increases considerably in the vicinity of the knee. Therefore, as a general design guideline, one should avoid operating the zener in this low-current region.
Zener diodes are fabricated with voltages VZ in the range of a few volts to a few hundred volts. In addition to specifying VZ (at a particular current IZT), rz, and IZK, the manufacturer also specifies the maximum power that the device can safely dissipate. Thus a 0.5-W, 6.8-V zener diode can operate safely at currents up to a maximum of about 70 mA.
The almost-linear i–v characteristic of the zener diode suggests that the device can be modeled as indicated in Fig. 4.18. Here VZ 0 denotes the point at which the straight line of slope intersects the voltage axis (refer to Fig. 4.17). Although VZ0 is shown in Fig. 4.17 to be slightly different from the knee voltage VZK, in practice their values are almost equal.
The equivalent circuit model of Fig. 4.18 can be analytically described by (4.20) and it applies for IZ > IZK and, obviously, VZ > VZ 0.
4.4.2 Use of the Zener as a Shunt Regulator We now illustrate, by way of an example, the use of zener diodes in the design of shunt reg-ulators, so named because the regulator circuit appears in parallel (shunt) with the load.
ΔV rz ΔI = 1 rz ⁄ VZ VZ0 rzIZ + = Figure 4.18 Model for the zener diode.
192 Chapter 4 Diodes The 6.8-V zener diode in the circuit of Fig. 4.19(a) is specified to have VZ = 6.8 V at IZ = 5 mA, rz = 20 Ω, and IZK = 0.2 mA. The supply voltage V + is nominally 10 V but can vary by ±1 V.
(a) Find VO with no load and with V + at its nominal value.
(b) Find the change in VO resulting from the ±1-V change in V +. Note that , usually expressed in mV/V, is known as line regulation.
(c) Find the change in VO resulting from connecting a load resistance RL that draws a current IL = 1 mA, and hence find the load regulation in mV/mA.
(d) Find the change in VO when RL = 2 kΩ.
(e) Find the value of VO when RL = 0.5 kΩ.
(f) What is the minimum value of RL for which the diode still operates in the breakdown region?
Solution First we must determine the value of the parameter VZ0 of the zener diode model. Substituting VZ = 6.8 V, IZ = 5 mA, and rz = 20 Ω in Eq. (4.20) yields Figure 4.19(b) shows the circuit with the zener diode replaced with its model.
(a) With no load connected, the current through the zener is given by Thus, Figure 4.19 (a) Circuit for Example 4.7. (b) The circuit with the zener diode replaced with its equivalent circuit model.
(a) 1 V) (b) I IZ VO IL ΔVO Δ ⁄ V+ ( ) ΔVO ΔIL ⁄ ( ) VZ0 6.7 V.
= IZ I V+ VZ0 – R rz + --------------------= = 10 6.7 – 0.5 0.02 + ------------------------= 6.35 mA = VO VZ0 IZrz + = 6.7 6.35 0.02 × + = 6.83 V = Example 4.7 4.4 Operation in the Reverse Breakdown Region—Zener Diodes 193 (b) For a ±1-V change in V+, the change in output voltage can be found from Thus, Line regulation = 38.5 mV/V (c) When a load resistance RL that draws a load current IL = 1 mA is connected, the zener current will decrease by 1 mA. The corresponding change in zener voltage can be found from Thus the load regulation is (d) When a load resistance of 2 kΩ is connected, the load current will be approximately 6.8 V/2 kΩ = 3.4 mA. Thus the change in zener current will be ΔIZ = −3.4 mA, and the correspond-ing change in zener voltage (output voltage) will thus be This calculation, however, is approximate, because it neglects the change in the current I. A more accurate estimate of ΔVO can be obtained by analyzing the circuit in Fig. 4.19(b). The result of such an analysis is ΔVO = −70 mV.
(e) An RL of 0.5 kΩ would draw a load current of = 13.6 mA. This is not possible, because the current I supplied through R is only 6.4 mA (for V+ = 10 V). Therefore, the zener must be cut off.
If this is indeed the case, then VO is determined by the voltage divider formed by RL and R (Fig. 4.19a), Since this voltage is lower than the breakdown voltage of the zener, the diode is indeed no longer operating in the breakdown region.
(f ) For the zener to be at the edge of the breakdown region, IZ = IZK = 0.2 mA and VZ VZK 6.7 V.
At this point the lowest (worst-case) current supplied through R is and thus the load current is 4.6 − 0.2 = 4.4 mA. The corresponding value of RL is ΔVO ΔV+ rz R rz + --------------= 1 20 500 20 + ---------------------× ± = 38.5 mV ± = ΔVO rz ΔIZ = 20 1 – × = 20 mV – = Load regulation ΔVO ΔIL ----------≡ 20 mV/mA – = ΔVO rz ΔIZ = 20 3.4 – × = 68 mV – = 6.8 0.5 ⁄ VO V+ RL R RL + ----------------= 10 0.5 0.5 0.5 + ---------------------= 5 V = 9 6.7 – ( ) 0.5 ⁄ 4.6 mA, = RL 6.7 4.4 ------- 1.5 kΩ = 194 Chapter 4 Diodes 4.4.3 Temperature Effects The dependence of the zener voltage VZ on temperature is specified in terms of its tempera-ture coefficient TC, or temco as it is commonly known, which is usually expressed in mV/°C. The value of TC depends on the zener voltage, and for a given diode the TC varies with the operating current. Zener diodes whose VZ are lower than about 5 V exhibit a nega-tive TC. On the other hand, zeners with higher voltages exhibit a positive TC. The TC of a zener diode with a VZ of about 5 V can be made zero by operating the diode at a specified current. Another commonly used technique for obtaining a reference voltage with low tem-perature coefficient is to connect a zener diode with a positive temperature coefficient of about 2 mV/°C in series with a forward-conducting diode. Since the forward-conducting diode has a voltage drop of 0.7 V and a TC of about −2 mV/°C, the series combination will provide a voltage of (VZ + 0.7) with a TC of about zero.
4.4.4 A Final Remark Though simple and useful, zener diodes have lost a great deal of their popularity in recent years. They have been virtually replaced in voltage-regulator design by specially designed integrated circuits (ICs) that perform the voltage regulation function much more effectively and with greater flexibility than zener diodes.
4.5 Rectifier Circuits One of the most important applications of diodes is in the design of rectifier circuits. A diode rectifier forms an essential building block of the dc power supplies required to power electronic equipment. A block diagram of such a power supply is shown in Fig. 4.20. As indicated, the power supply is fed from the 120-V (rms) 60-Hz ac line, and it delivers a dc voltage VO (usually in the range of 5 V to 20 V) to an electronic circuit represented by the 4.16 A zener diode whose nominal voltage is 10 V at 10 mA has an incremental resistance of 50 Ω. What voltage do you expect if the diode current is halved? Doubled? What is the value of VZ0 in the zener model?
Ans. 9.75 V; 10.5 V; 9.5 V 4.17 A zener diode exhibits a constant voltage of 5.6 V for currents greater than five times the knee cur-rent. IZK is specified to be 1 mA. The zener is to be used in the design of a shunt regulator fed from a 15-V supply. The load current varies over the range of 0 mA to 15 mA. Find a suitable value for the resistor R. What is the maximum power dissipation of the zener diode?
Ans. 470 Ω; 112 mW 4.18 A shunt regulator utilizes a zener diode whose voltage is 5.1 V at a current of 50 mA and whose incremental resistance is 7 Ω. The diode is fed from a supply of 15-V nominal voltage through a 200-Ω resistor. What is the output voltage at no load? Find the line regulation and the load regulation.
Ans. 5.1 V; 33.8 mV/V; −7 mV/mA EXERCISES 4.5 Rectifier Circuits 195 load block. The dc voltage VO is required to be as constant as possible in spite of variations in the ac line voltage and in the current drawn by the load.
The first block in a dc power supply is the power transformer. It consists of two separate coils wound around an iron core that magnetically couples the two windings. The primary winding, having N1 turns, is connected to the 120-V ac supply, and the secondary winding, having N2 turns, is connected to the circuit of the dc power supply. Thus an ac voltage vS of V (rms) develops between the two terminals of the secondary winding. By selecting an appropriate turns ratio for the transformer, the designer can step the line voltage down to the value required to yield the particular dc voltage output of the supply.
For instance, a secondary voltage of 8-V rms may be appropriate for a dc output of 5 V. This can be achieved with a 15:1 turns ratio.
In addition to providing the appropriate sinusoidal amplitude for the dc power supply, the power transformer provides electrical isolation between the electronic equipment and the power-line circuit. This isolation minimizes the risk of electric shock to the equipment user.
The diode rectifier converts the input sinusoid vS to a unipolar output, which can have the pulsating waveform indicated in Fig. 4.20. Although this waveform has a nonzero aver-age or a dc component, its pulsating nature makes it unsuitable as a dc source for electronic circuits, hence the need for a filter. The variations in the magnitude of the rectifier output are considerably reduced by the filter block in Fig. 4.20. In the following sections we shall study a number of rectifier circuits and a simple implementation of the output filter.
The output of the rectifier filter, though much more constant than without the filter, still contains a time-dependent component, known as ripple. To reduce the ripple and to stabilize the magnitude of the dc output voltage of the supply against variations caused by changes in load current, a voltage regulator is employed. Such a regulator can be imple-mented using the zener shunt regulator configuration studied in Section 4.4. Alternatively, and much more commonly at present, an integrated-circuit regulator can be used.
4.5.1 The Half-Wave Rectifier The half-wave rectifier utilizes alternate half-cycles of the input sinusoid. Figure 4.21(a) shows the circuit of a half-wave rectifier. This circuit was analyzed in Section 4.1 (see Fig. 4.3) assuming an ideal diode. Using the more realistic constant-voltage-drop diode model, we obtain vO = 0, vS < V D (4.21a) vO = vS – V D, vS V t (4.21b) Figure 4.20 Block diagram of a dc power supply.
t 120 N2 N1 ⁄ ( ) N1 N2 ⁄ ( ) 196 Chapter 4 Diodes The transfer characteristic represented by these equations is sketched in Fig. 4.21(b), where VD = 0.7 V or 0.8 V. Figure 4.21(c) shows the output voltage obtained when the input vS is a sinusoid.
In selecting diodes for rectifier design, two important parameters must be specified: the current-handling capability required of the diode, determined by the largest current the diode is expected to conduct, and the peak inverse voltage (PIV) that the diode must be able to withstand without breakdown, determined by the largest reverse voltage that is expected to appear across the diode. In the rectifier circuit of Fig. 4.21(a), we observe that when vS is negative the diode will be cut off and vO will be zero. It follows that the PIV is equal to the peak of vS , (4.22) It is usually prudent, however, to select a diode that has a reverse breakdown voltage at least 50% greater than the expected PIV.
Figure 4.21 (a) Half-wave rectifier. (b) Transfer characteristic of the rectifier circuit. (c) Input and output waveforms.
(a) vO R D vS vS VD 0 Slope 1 (b) vO v (c) VD vO Vs VD vS t PIV V s = 4.5 Rectifier Circuits 197 Before leaving the half-wave rectifier, the reader should note two points. First, it is pos-sible to use the diode exponential characteristic to determine the exact transfer characteristic of the rectifier (see Problem 4.65). However, the amount of work involved is usually too great to be justified in practice. Of course, such an analysis can be easily done using a com-puter circuit-analysis program such as SPICE. Second, whether we analyze the circuit accurately or not, it should be obvious that this circuit does not function properly when the input signal is small. For instance, this circuit cannot be used to rectify an input sinusoid of 100-mV amplitude. For such an application one resorts to a so-called precision rectifier, a circuit utilizing diodes in conjunction with op amps. One such circuit is presented in Section 4.5.5.
4.5.2 The Full-Wave Rectifier The full-wave rectifier utilizes both halves of the input sinusoid. To provide a unipolar out-put, it inverts the negative halves of the sine wave. One possible implementation is shown in Fig. 4.22(a). Here the transformer secondary winding is center-tapped to provide two equal voltages vS across the two halves of the secondary winding with the polarities indicated.
Note that when the input line voltage (feeding the primary) is positive, both of the signals labeled vS will be positive. In this case D1 will conduct and D2 will be reverse biased. The current through D1 will flow through R and back to the center tap of the secondary. The cir-cuit then behaves like a half-wave rectifier, and the output during the positive half-cycles when D1 conducts will be identical to that produced by the half-wave rectifier.
Now, during the negative half-cycle of the ac line voltage, both of the voltages labeled vS will be negative. Thus D1 will be cut off while D2 will conduct. The current conducted by D2 will flow through R and back to the center tap. It follows that during the negative half-cycles while D2 conducts, the circuit behaves again as a half-wave rectifier. The important point, however, is that the current through R always flows in the same direction, and thus vO will be unipolar, as indicated in Fig. 4.22(c). The output waveform shown is obtained by assum-ing that a conducting diode has a constant voltage drop VD. Thus the transfer characteristic of the full-wave rectifier takes the shape shown in Fig. 4.22(b).
The full-wave rectifier obviously produces a more “energetic” waveform than that pro-vided by the half-wave rectifier. In almost all rectifier applications, one opts for a full-wave type of some kind.
4.19 For the half-wave rectifier circuit in Fig. 4.21(a), show the following: (a) For the half-cycles during which the diode conducts, conduction begins at an angle θ = sin−1 and terminates at (π − θ), for a total conduction angle of (π − 2θ). (b) The average value (dc component) of vO is (c) The peak diode current is Find numerical values for these quantities for the case of 12-V (rms) sinusoidal input, VD 0.7 V, and R = 100 Ω. Also, give the value for PIV.
Ans. (a) θ = 2.4°, conduction angle = 175°; (b) 5.05 V; (c) 163 mA; 17 V VD Vs ⁄ ( ) VO 1 π ⁄ ( )Vs VD 2.
⁄ – Vs VD – ( ) R ⁄ ).
EXERCISE 198 Chapter 4 Diodes To find the PIV of the diodes in the full-wave rectifier circuit, consider the situation dur-ing the positive half-cycles. Diode D1 is conducting, and D2 is cut off. The voltage at the cath-ode of D2 is vO, and that at its anode is −vS. Thus the reverse voltage across D2 will be (vO + vS), which will reach its maximum when vO is at its peak value of (Vs − VD), and vS is at its peak value of Vs; thus, PIV = 2Vs − VD which is approximately twice that for the case of the half-wave rectifier.
Figure 4.22 Full-wave rectifier utilizing a transformer with a center-tapped secondary winding: (a) circuit; (b) transfer characteristic assuming a constant-voltage-drop model for the diodes; (c) input and output waveforms.
R ac line voltage vO (a) vS vS Center tap D1 D2 vS VD 0 Slope 1 (b) vO 2VD Slope 21 v (c) vO Vs VD 2vS t vS 4.20 For the full-wave rectifier circuit in Fig. 4.22(a), show the following: (a) The output is zero for an an-gle of 2 sin−1 centered around the zero-crossing points of the sine-wave input. (b) The VD Vs ⁄ ( ) EXERCISE 4.5 Rectifier Circuits 199 4.5.3 The Bridge Rectifier An alternative implementation of the full-wave rectifier is shown in Fig. 4.23(a). This cir-cuit, known as the bridge rectifier because of the similarity of its configuration to that of the Wheatstone bridge, does not require a center-tapped transformer, a distinct advantage over the full-wave rectifier circuit of Fig. 4.22. The bridge rectifier, however, requires four diodes as compared to two in the previous circuit. This is not much of a disadvantage, because diodes are inexpensive and one can buy a diode bridge in one package.
The bridge rectifier circuit operates as follows: During the positive half-cycles of the input voltage, vS is positive, and thus current is conducted through diode D1, resistor R, and diode D2. Meanwhile, diodes D3 and D4 will be reverse biased. Observe that there are two diodes in series in the conduction path, and thus vO will be lower than vS by two diode drops (compared to one drop in the circuit previously discussed). This is somewhat of a disadvan-tage of the bridge rectifier.
Figure 4.23 The bridge rectifier: (a) circuit; (b) input and output waveforms.
average value (dc component) of vO is (c) The peak current through each di-ode is . Find the fraction (percentage) of each cycle during which vO > 0, the value of VO, the peak diode current, and the value of PIV, all for the case in which vS is a 12-V (rms) sinusoid, VD 0.7 V, and R = 100 Ω.
Ans. 97.4%; 10.1 V; 163 mA; 33.2 V VO 2 π ⁄ ( )Vs VD.
– Vs VD – ( ) R ⁄ R ac line voltage D3 (a) vS vO D1 D4 D2 v (b) vO Vs 2 VD vS t vS 200 Chapter 4 Diodes Next, consider the situation during the negative half-cycles of the input voltage. The sec-ondary voltage vS will be negative, and thus −vS will be positive, forcing current through D3, R, and D4. Meanwhile, diodes D1 and D2 will be reverse biased. The important point to note, though, is that during both half-cycles, current flows through R in the same direction (from right to left), and thus vO will always be positive, as indicated in Fig. 4.23(b).
To determine the peak inverse voltage (PIV) of each diode, consider the circuit during the positive half-cycles. The reverse voltage across D3 can be determined from the loop formed by D3, R, and D2 as Thus the maximum value of vD3 occurs at the peak of vO and is given by Observe that here the PIV is about half the value for the full-wave rectifier with a center-tapped transformer. This is another advantage of the bridge rectifier.
Yet one more advantage of the bridge rectifier circuit over that utilizing a center-tapped transformer is that only about half as many turns are required for the secondary winding of the transformer. Another way of looking at this point can be obtained by observing that each half of the secondary winding of the center-tapped transformer is utilized for only half the time. These advantages have made the bridge rectifier the most popular rectifier circuit configuration.
4.5.4 The Rectifier with a Filter Capacitor—The Peak Rectifier The pulsating nature of the output voltage produced by the rectifier circuits discussed above makes it unsuitable as a dc supply for electronic circuits. A simple way to reduce the varia-tion of the output voltage is to place a capacitor across the load resistor. It will be shown that this filter capacitor serves to reduce substantially the variations in the rectifier output voltage.
To see how the rectifier circuit with a filter capacitor works, consider first the simple cir-cuit shown in Fig. 4.24. Let the input vI be a sinusoid with a peak value V p, and assume the diode to be ideal. As vI goes positive, the diode conducts and the capacitor is charged so that vO = vI. This situation continues until vI reaches its peak value V p. Beyond the peak, as vI decreases the diode becomes reverse biased and the output voltage remains constant at the value V p. In fact, theoretically speaking, the capacitor will retain its charge and hence its volt-age indefinitely, because there is no way for the capacitor to discharge. Thus the circuit pro-vides a dc voltage output equal to the peak of the input sine wave. This is a very encouraging result in view of our desire to produce a dc output.
vD3 reverse ( ) vO vD2 forward ( ) + = PIV Vs 2VD – VD + Vs VD – = = 4.21 For the bridge rectifier circuit of Fig. 4.23(a), use the constant-voltage-drop diode model to show that (a) the average (or dc component) of the output voltage is and (b) the peak diode current is Find numerical values for the quantities in (a) and (b) and the PIV for the case in which vS is a 12-V (rms) sinusoid, VD 0.7 V, and R = 100 Ω.
Ans. 9.4 V; 156 mA; 16.3 V VO 2 π ⁄ ( )Vs 2VD – Vs 2VD – ( ) R ⁄ ).
EXERCISE 4.5 Rectifier Circuits 201 Next, we consider the more practical situation where a load resistance R is connected across the capacitor C, as depicted in Fig. 4.25(a). However, we will continue to assume the diode to be ideal. As before, for a sinusoidal input, the capacitor charges to the peak of the input V p. Then the diode cuts off, and the capacitor discharges through the load resistance R. The capacitor discharge will continue for almost the entire cycle, until the time at which vI exceeds the capacitor voltage. Then the diode turns on again and charges the capacitor up to the peak of vI, and the process repeats itself. Observe that to keep the output voltage from decreasing too much during capacitor discharge, one selects a value for C so that the time constant CR is much greater than the discharge interval. We are now ready to analyze the circuit in detail. Figure 4.25(b) shows the steady-state input and output voltage waveforms under the assumption that CR T, where T is the period of the input sinusoid. The waveforms of the load current (4.23) and of the diode current (when it is conducting) (4.24) (4.25) Figure 4.24 (a) A simple circuit used to illustrate the effect of a filter capacitor. (b) Input and output waveforms assuming an ideal diode. Note that the circuit provides a dc voltage equal to the peak of the input sine wave. The circuit is therefore known as a peak rectifier or a peak detector.
D (a) (b) 0 iL vO R ⁄ = iD iC iL + = C dvI dt -------iL + = 202 Chapter 4 Diodes are shown in Fig. 4.25(c). The following observations are in order: 1. The diode conducts for a brief interval, Δt, near the peak of the input sinusoid and supplies the capacitor with charge equal to that lost during the much longer dis-charge interval. The latter is approximately equal to the period T.
2. Assuming an ideal diode, the diode conduction begins at time t1, at which the input vI equals the exponentially decaying output vO. Conduction stops at t2 shortly after the peak of vI; the exact value of t2 can be determined by setting iD = 0 in Eq. (4.25).
Figure 4.25 Voltage and current waveforms in the peak rectifier circuit with CR T. The diode is assumed ideal.
vI vO C R (a) iD iC iL D t2 (c) T t Conduction interval t t (b) vI iL vO vI t1 Vp iD t t Vr 4.5 Rectifier Circuits 203 3. During the diode-off interval, the capacitor C discharges through R, and thus vO decays exponentially with a time constant CR. The discharge interval begins just past the peak of vI. At the end of the discharge interval, which lasts for almost the entire period T, vO = Vp − Vr, where Vr is the peak-to-peak ripple voltage. When CR T, the value of Vr is small.
4. When Vr is small, vO is almost constant and equal to the peak value of vI. Thus the dc output voltage is approximately equal to V p. Similarly, the current iL is almost con-stant, and its dc component IL is given by (4.26) If desired, a more accurate expression for the output dc voltage can be obtained by taking the average of the extreme values of vO, (4.27) With these observations in hand, we now derive expressions for V r and for the average and peak values of the diode current. During the diode-off interval, vO can be expressed as At the end of the discharge interval we have Now, since CR T, we can use the approximation to obtain (4.28) We observe that to keep Vr small we must select a capacitance C so that CR T. The ripple voltage Vr in Eq. (4.28) can be expressed in terms of the frequency as (4.29a) Using Eq. (4.26) we can express Vr by the alternate expression (4.29b) Note that an alternative interpretation of the approximation made above is that the capacitor discharges by means of a constant current . This approximation is valid as long as Vr V p.
Assuming that diode conduction ceases almost at the peak of vI, we can determine the conduction interval Δt from where is the angular frequency of vI. Since (ω Δt) is a small angle, we can employ the approximation to obtain (4.30) We note that when Vr Vp, the conduction angle ω Δt will be small, as assumed.
IL Vp R -----= VO Vp 1 2 ---Vr – = vO Vpe t CR ⁄ – = Vp Vr Vpe T CR ⁄ – – e T CR ⁄ – 1 T CR ⁄ – Vr Vp T CR --------f 1 T ⁄ = Vr Vp fCR ----------= Vr IL fC ------= IL Vp R ⁄ = Vp ω Δt ( ) cos Vp Vr – = ω 2πf 2π T ⁄ = = ω Δt ( ) 1 1 2 --- ω Δt ( ) 2 – cos ω Δt 2Vr Vp ⁄ 204 Chapter 4 Diodes To determine the average diode current during conduction, iDav, we equate the charge that the diode supplies to the capacitor, where from Eq. (4.24), to the charge that the capacitor loses during the discharge interval, to obtain, using Eqs. (4.30) and (4.29a), (4.31) Observe that when Vr Vp, the average diode current during conduction is much greater than the dc load current. This is not surprising, since the diode conducts for a very short interval and must replenish the charge lost by the capacitor during the much longer interval in which it is discharged by IL.
The peak value of the diode current, iDmax, can be determined by evaluating the expres-sion in Eq. (4.25) at the onset of diode conduction—that is, at t = t1 = −Δt (where t = 0 is at the peak). Assuming that iL is almost constant at the value given by Eq. (4.26), we obtain (4.32) From Eqs. (4.31) and (4.32), we see that for Vr Vp, iDmax 2iDav, which correlates with the fact that the waveform of iD is almost a right-angle triangle (see Fig. 4.25c).
Qsupplied = iCav Δt iCav = iDav IL – Qlost = CVr iDav = IL 1 π 2Vp Vr ⁄ + ( ) iDmax = IL 1 2π 2Vp Vr ⁄ + ( ) Consider a peak rectifier fed by a 60-Hz sinusoid having a peak value Vp = 100 V. Let the load resis-tance R = 10 kΩ. Find the value of the capacitance C that will result in a peak-to-peak ripple of 2 V.
Also, calculate the fraction of the cycle during which the diode is conducting and the average and peak values of the diode current.
Solution From Eq. (4.29a) we obtain the value of C as The conduction angle ω Δt is found from Eq. (4.30) as Thus the diode conducts for of the cycle. The average diode current is obtained from Eq. (4.31), where as The peak diode current is found using Eq. (4.32), C Vp Vr fR ------------100 2 60 10 103 × × × ------------------------------------------83.3 μF = = = ω Δt 2 2 100 ⁄ × 0.2 rad = = 0.2 2π ⁄ ( ) 100 × = 3.18% IL = 100 10 ⁄ = 10 mA, iDav 10 1 π 2 100 2 ⁄ × + ( ) 324 mA = = iDmax 10 1 2π 2 100 2 ⁄ × + ( ) 638 mA = = Example 4.8 4.5 Rectifier Circuits 205 The circuit of Fig. 4.25(a) is known as a half-wave peak rectifier. The full-wave recti-fier circuits of Figs. 4.22(a) and 4.23(a) can be converted to peak rectifiers by including a capacitor across the load resistor. As in the half-wave case, the output dc voltage will be almost equal to the peak value of the input sine wave (Fig. 4.26). The ripple frequency, how-ever, will be twice that of the input. The peak-to-peak ripple voltage, for this case, can be derived using a procedure identical to that above but with the discharge period T replaced by , resulting in (4.33) While the diode conduction interval, Δt, will still be given by Eq. (4.30), the average and peak currents in each of the diodes will be given by (4.34) (4.35) Comparing these expressions with the corresponding ones for the half-wave case, we note that for the same values of V p, f, R, and Vr (and thus the same IL), we need a capacitor half the size of that required in the half-wave rectifier. Also, the current in each diode in the full-wave rectifier is approximately half that which flows in the diode of the half-wave circuit.
The analysis above assumed ideal diodes. The accuracy of the results can be improved by taking the diode voltage drop into account. This can be easily done by replacing the peak voltage Vp to which the capacitor charges with (Vp − VD) for the half-wave circuit and the full-wave cir-cuit using a center-tapped transformer and with (Vp − 2VD) for the bridge-rectifier case.
We conclude this section by noting that peak-rectifier circuits find application in signal-processing systems where it is required to detect the peak of an input signal. In such a case, the circuit is referred to as a peak detector. A particularly popular application of the peak detector is in the design of a demodulator for amplitude-modulated (AM) signals. We shall not discuss this application further here. Figure 4.26 Waveforms in the full-wave peak rectifier.
T 2 ⁄ Vr Vp 2fCR -------------= iDav = IL 1 π Vp 2Vr ⁄ + ( ) iDmax = IL 1 2π Vp 2Vr ⁄ + ( ) 4.22 Derive the expressions in Eqs. (4.33), (4.34), and (4.35).
4.23 Consider a bridge-rectifier circuit with a filter capacitor C placed across the load resistor R for the case in which the transformer secondary delivers a sinusoid of 12 V (rms) having a 60-Hz frequency and EXERCISES 206 Chapter 4 Diodes 4.5.5 Precision Half-Wave Rectifier—The Superdiode 4 The rectifier circuits studied thus far suffer from having one or two diode drops in the signal paths. Thus these circuits work well only when the signal to be rectified is much larger than the voltage drop of a conducting diode (0.7 V or so). In such a case, the details of the diode forward characteristics or the exact value of the diode voltage do not play a prominent role in determining circuit performance. This is indeed the case in the application of rectifier cir-cuits in power-supply design. There are other applications, however, where the signal to be rectified is small (e.g., on the order of 100 mV or so) and thus clearly insufficient to turn on a diode. Also, in instrumentation applications, the need arises for rectifier circuits with very precise and predictable transfer characteristics. For these applications, a class of circuits has been developed utilizing op amps (Chapter 2) together with diodes to provide precision rec-tification. In the following discussion, we study one such circuit, leaving a more comprehen-sive study of op amp–diode circuits to Chapter 17.
Figure 4.27(a) shows a precision half-wave rectifier circuit consisting of a diode placed in the negative-feedback path of an op amp, with R being the rectifier load resistance. The op amp, of course, needs power supplies for its operation. For simplicity, these are not shown in the circuit diagram. The circuit works as follows: If vI goes positive, the output voltage vA of the op amp will go positive and the diode will conduct, thus establishing a closed feedback path between the op amp’s output terminal and the negative input terminal. This negative-feedback path will cause a virtual short circuit to appear between the two input terminals of 4This section requires knowledge of operational amplifiers (Chapter 2).
Figure 4.27 The “superdiode” precision half-wave rectifier and its almost-ideal transfer characteristic.
Note that when and the diode conducts, the op amp supplies the load current, and the source is conve-niently buffered, an added advantage. Not shown are the op-amp power supplies.
assuming VD = 0.8 V and a load resistance R = 100 Ω. Find the value of C that results in a ripple voltage no larger than 1 V peak-to-peak. What is the dc voltage at the output? Find the load current.
Find the diodes’ conduction angle. Provide the average and peak diode currents What is the peak reverse voltage across each diode? Specify the diode in terms of its peak current and its PIV.
Ans. 1281 μF; 15.4 V or (a better estimate) 14.9 V; 0.15 A; 0.36 rad (20.7°); 1.45 A; 2.74 A; 16.2 V. Thus select a diode with 3.5-A to 4-A peak current and a 20-V PIV rating.
(a) (b) vI 0 > Limiting and Clamping Circuits 207 the op amp. Thus the voltage at the negative input terminal, which is also the output voltage vO, will equal (to within a few millivolts) that at the positive input terminal, which is the input voltage vI, Note that the offset voltage (0.7 V) exhibited in the simple half-wave rectifier circuit of Fig. 4.21 is no longer present. For the op-amp circuit to start operation, vI has to exceed only a negligibly small voltage equal to the diode drop divided by the op amp’s open-loop gain.
In other words, the straight-line transfer characteristic vO–vI almost passes through the ori-gin. This makes this circuit suitable for applications involving very small signals.
Consider now the case when vI goes negative. The op amp’s output voltage vA will tend to follow and go negative. This will reverse-bias the diode, and no current will flow through resistance R, causing vO to remain equal to 0 V. Thus, for vI < 0, vO = 0. Since in this case the diode is off, the op amp will be operating in an open-loop fashion, and its output will be at its negative saturation level.
The transfer characteristic of this circuit will be that shown in Fig. 4.27(b), which is almost identical to the ideal characteristic of a half-wave rectifier. The nonideal diode charac-teristics have been almost completely masked by placing the diode in the negative-feedback path of an op amp. This is another dramatic application of negative feedback, a subject we will study formally in Chapter 10. The combination of diode and op amp, shown in the dotted box in Fig. 4.27(a), is appropriately referred to as a “superdiode.” 4.6 Limiting and Clamping Circuits In this section, we shall present additional nonlinear circuit applications of diodes.
4.6.1 Limiter Circuits Figure 4.28 shows the general transfer characteristic of a limiter circuit. As indicated, for inputs in a certain range, , the limiter acts as a linear circuit, providing an output proportional to the input, vO = KvI. Although in general K can be greater than 1, the cir-cuits discussed in this section have K ≤ 1 and are known as passive limiters. (Examples of active limiters will be presented in Chapter 17.) If vI exceeds the upper threshold , the output voltage is limited or clamped to the upper limiting level L+. On the other hand, if vI is vO vI vI 0 ≥ = 4.24 Consider the operational rectifier or superdiode circuit of Fig. 4.27(a), with R = 1 kΩ. For vI = 10 mV, 1 V, and −1 V, what are the voltages that result at the rectifier output and at the output of the op amp?
Assume that the op amp is ideal and that its output saturates at ±12 V. The diode has a 0.7-V drop at 1-mA current.
Ans. 10 mV, 0.59 V; 1 V, 1.7 V; 0 V, −12 V 4.25 If the diode in the circuit of Fig. 4.27(a) is reversed, find the transfer characteristic vO as a function of vI.
Ans. for for vO 0 = vI 0; ≥ vO vI = vI 0 ≤ EXERCISES L−K vI L+ K ⁄ ≤ ≤ ⁄ L+ K ⁄ ( ) 208 Chapter 4 Diodes reduced below the lower limiting threshold , the output voltage vO is limited to the lower limiting level .
The general transfer characteristic of Fig. 4.28 describes a double limiter—that is, a limiter that works on both the positive and negative peaks of an input waveform. Single lim-iters, of course, exist. Finally, note that if an input waveform such as that shown in Fig. 4.29 is fed to a double limiter, its two peaks will be clipped off. Limiters therefore are sometimes referred to as clippers.
The limiter whose characteristics are depicted in Fig. 4.28 is described as a hard limiter.
Soft limiting is characterized by smoother transitions between the linear region and the sat-uration regions and a slope greater than zero in the saturation regions, as illustrated in Fig.
4.30. Depending on the application, either hard or soft limiting may be preferred.
Limiters find application in a variety of signal-processing systems. One of their simplest applications is in limiting the voltage between the two input terminals of an op amp to a value lower than the breakdown voltage of the transistors that make up the input stage of the op-amp circuit. We will have more to say on this and other limiter applications at later points in this book.
Diodes can be combined with resistors to provide simple realizations of the limiter function. A number of examples are depicted in Fig. 4.31. In each part of the figure both the circuit and its transfer characteristic are given. The transfer characteristics are obtained using the constant-voltage-drop (VD = 0.7 V) diode model but assuming a smooth transition between the linear and saturation regions of the transfer characteristic. Figure 4.29 Applying a sine wave to a limiter can result in clipping off its two peaks.
Figure 4.28 General transfer characteristic for a limiter circuit.
L−K ⁄ ( ) L− Limiting and Clamping Circuits 209 The circuit in Fig. 4.31(a) is that of the half-wave rectifier except that here the output is taken across the diode. For vI < 0.5 V, the diode is cut off, no current flows, and the voltage drop across R is zero; thus vO = vI. As vI exceeds 0.5 V, the diode turns on, eventually limiting Figure 4.30 Soft limiting.
Figure 4.31 A variety of basic limiting circuits.
210 Chapter 4 Diodes vO to one diode drop (0.7 V). The circuit of Fig. 4.31(b) is similar to that in Fig. 4.31(a) except that the diode is reversed.
Double limiting can be implemented by placing two diodes of opposite polarity in paral-lel, as shown in Fig. 4.31(c). Here the linear region of the characteristic is obtained for For this range of vI, both diodes are off and vO = vI. As vI exceeds 0.5 V, D1 turns on and eventually limits vO to +0.7 V. Similarly, as vI goes more negative than –0.5 V, D2 turns on and eventually limits vO to –0.7 V.
The thresholds and saturation levels of diode limiters can be controlled by using strings of diodes and/or by connecting a dc voltage in series with the diode(s). The latter idea is illus-trated in Fig. 4.31(d). Finally, rather than strings of diodes, we may use two zener diodes in series, as shown in Fig. 4.31(e). In this circuit, limiting occurs in the positive direction at a voltage of VZ 2 + 0.7, where 0.7 V represents the voltage drop across zener diode Z1 when conducting in the forward direction. For negative inputs, Z1 acts as a zener, while Z2 conducts in the forward direction. It should be mentioned that pairs of zener diodes connected in series are available commercially for applications of this type under the name double-anode zener.
More flexible limiter circuits are possible if op amps are combined with diodes and resistors. Examples of such circuits are discussed in Chapter 17.
4.6.2 The Clamped Capacitor or DC Restorer If in the basic peak-rectifier circuit, the output is taken across the diode rather than across the capacitor, an interesting circuit with important applications results. The circuit, called a dc restorer, is shown in Fig. 4.32 fed with a square wave. Because of the polarity in which the diode is connected, the capacitor will charge to a voltage vC with the polarity indicated in Fig. 4.32 and equal to the magnitude of the most negative peak of the input signal. Subse-quently, the diode turns off and the capacitor retains its voltage indefinitely. If, for instance, the input square wave has the arbitrary levels −6 V and +4 V, then vC will be equal to 6 V.
Now, since the output voltage vO is given by it follows that the output waveform will be identical to that of the input, except that it is shifted upward by vC volts. In our example the output will thus be a square wave with levels of 0 V and +10 V.
0.5 V – vI 0.5 V.
≤ ≤ 4.26 Assuming the diodes to be ideal, describe the transfer characteristic of the circuit shown in Fig. E4.26.
Ans.
Figure E4.26 vO vI for 5 – vI +5 ≤ ≤ = vO 1 2 ---vI 2.5 for vI 5 – ≤ – = vO 1 2 ---vI 2.5 for vI +5 ≥ + = EXERCISE vO vI vC + = Limiting and Clamping Circuits 211 Another way of visualizing the operation of the circuit in Fig. 4.32 is to note that because the diode is connected across the output with the polarity shown, it prevents the output voltage from going below 0 V (by conducting and charging up the capacitor, thus causing the output to rise to 0 V), but this connection will not constrain the positive excursion of vO. The output waveform will therefore have its lowest peak clamped to 0 V, which is why the circuit is called a clamped capacitor. It should be obvious that reversing the diode polarity will provide an output waveform whose highest peak is clamped to 0 V. In either case, the output waveform will have a finite average value or dc component. This dc component is entirely unrelated to the average value of the input waveform. As an application, consider a pulse signal being transmitted through a capac-itively coupled or ac-coupled system. The capacitive coupling will cause the pulse train to lose whatever dc component it originally had. Feeding the resulting pulse waveform to a clamping circuit provides it with a well-determined dc component, a process known as dc restoration. This is why the circuit is also called a dc restorer.
Restoring dc is useful because the dc component or average value of a pulse waveform is an effective measure of its duty cycle.5 The duty cycle of a pulse waveform can be modulated (in a process called pulsewidth modulation) and made to carry information. In such a system, detection or demodulation could be achieved simply by feeding the received pulse waveform to a dc restorer and then using a simple RC low-pass filter to separate the average of the out-put waveform from the superimposed pulses.
When a load resistance R is connected across the diode in a clamping circuit, as shown in Fig. 4.33, the situation changes significantly. While the output is above ground, a current must flow in R. Since at this time the diode is off, this current obviously comes from the capacitor, thus causing the capacitor to discharge and the output voltage to fall.
This is shown in Fig. 4.33 for a square-wave input. During the interval t0 to t1, the output voltage falls exponentially with time constant CR. At t1 the input decreases by Va volts, and the output attempts to follow. This causes the diode to conduct heavily and to quickly charge the capacitor. At the end of the interval t1 to t2, the output voltage would normally be a few tenths of a volt negative (e.g., −0.5 V). Then, as the input rises by Va volts (at t2), the output follows, and the cycle repeats itself. In the steady state the charge lost by the capac-itor during the interval t0 to t1 is recovered during the interval t1 to t2. This charge equilibrium enables us to calculate the average diode current as well as the details of the output waveform.
Figure 4.32 The clamped capacitor or dc restorer with a square-wave input and no load.
5The duty cycle of a pulse waveform is the proportion of each cycle occupied by the pulse. In other words, it is the pulse width expressed as a fraction of the pulse period.
vC (a) (b) (c) 212 Chapter 4 Diodes 4.6.3 The Voltage Doubler Figure 4.34(a) shows a circuit composed of two sections in cascade: a clamped capacitor formed by C1 and D1, and a peak rectifier formed by D2 and C2. When excited by a Figure 4.33 The clamped capacitor with a load resistance R.
Figure 4.34 Voltage doubler: (a) circuit; (b) waveform of the voltage across D1.
(a) (b) (c) D D (a) (b) 4.7 Special Diode Types 213 sinusoid of amplitude V p the clamping section provides the voltage waveform shown, assuming ideal diodes, in Fig. 4.34(b). Note that while the positive peaks are clamped to 0 V, the negative peak reaches −2V p. In response to this waveform, the peak-detector section provides across capacitor C2 a negative dc voltage of magnitude 2V p.
Because the output voltage is double the input peak, the circuit is known as a voltage doubler. The technique can be extended to provide output dc voltages that are higher multiples of V p.
4.7 Special Diode Types In this section, we discuss briefly some important special types of diodes.
4.7.1 The Schottky-Barrier Diode (SBD) The Schottky-barrier diode (SBD) is formed by bringing metal into contact with a mod-erately doped n-type semiconductor material. The resulting metal–semiconductor junc-tion behaves like a diode, conducting current in one direction (from the metal anode to the semiconductor cathode) and acting as an open circuit in the other, and is known as the Schottky-barrier diode or simply the Schottky diode. In fact, the current–voltage characteristic of the SBD is remarkably similar to that of a pn-junction diode, with two important exceptions: 1. In the SBD, current is conducted by majority carriers (electrons). Thus the SBD does not exhibit the minority-carrier charge-storage effects found in forward-biased pn junctions. As a result, Schottky diodes can be switched from on to off, and vice versa, much faster than is possible with pn-junction diodes.
2. The forward voltage drop of a conducting SBD is lower than that of a pn-junc-tion diode. For example, an SBD made of silicon exhibits a forward voltage drop of 0.3 V to 0.5 V, compared to the 0.6 V to 0.8 V found in silicon pn-junc-tion diodes. SBDs can also be made of gallium arsenide (GaAs) and, in fact, play an important role in the design of GaAs circuits.6 Gallium-arsenide SBDs exhibit forward voltage drops of about 0.7 V.
Apart from GaAs circuits, Schottky diodes find application in the design of a special form of bipolar-transistor logic circuits, known as Schottky-TTL, where TTL stands for transistor-transistor logic.
Before leaving the subject of Schottky-barrier diodes, it is important to note that not every metal–semiconductor contact is a diode. In fact, metal is commonly deposited on 6 The disc accompanying this text contain material on GaAs circuits.
4.27 If the diode in the circuit of Fig. 4.32 is reversed, what will the dc component of vO become?
Ans. −5 V EXERCISE 214 Chapter 4 Diodes the semiconductor surface in order to make terminals for the semiconductor devices and to connect different devices in an integrated-circuit chip. Such metal–semiconductor contacts are known as ohmic contacts to distinguish them from the rectifying contacts that result in SBDs. Ohmic contacts are usually made by depositing metal on very heavily doped (and thus low-resistivity) semiconductor regions. (Recall that SBDs use moderately doped material.) 4.7.2 Varactors In Chapter 3 we learned that reverse-biased pn junctions exhibit a charge-storage effect that is modeled with the depletion-layer or junction capacitance Cj. As Eq. (3.44) indicates, Cj is a function of the reverse-bias voltage VR. This dependence turns out to be useful in a number of applications, such as the automatic tuning of radio receivers. Special diodes are therefore fabricated to be used as voltage-variable capacitors known as varactors. These devices are optimized to make the capacitance a strong function of voltage by arranging that the grading coefficient m is 3 or 4.
4.7.3 Photodiodes If a reverse-biased pn junction is illuminated—that is, exposed to incident light—the pho-tons impacting the junction cause covalent bonds to break, and thus electron–hole pairs are generated in the depletion layer. The electric field in the depletion region then sweeps the liberated electrons to the n side and the holes to the p side, giving rise to a reverse current across the junction. This current, known as photocurrent, is proportional to the intensity of the incident light. Such a diode, called a photodiode, can be used to convert light signals into electrical signals.
Photodiodes are usually fabricated using a compound semiconductor7 such as gallium arsenide. The photodiode is an important component of a growing family of circuits known as optoelectronics or photonics. As the name implies, such circuits utilize an optimum com-bination of electronics and optics for signal processing, storage, and transmission. Usually, electronics is the preferred means for signal processing, whereas optics is most suited for transmission and storage. Examples include fiber-optic transmission of telephone and televi-sion signals and the use of optical storage in CD-ROM computer disks. Optical transmission provides very wide bandwidths and low signal attenuation. Optical storage allows vast amounts of data to be stored reliably in a small space.
Finally, we should note that without reverse bias, the illuminated photodiode functions as a solar cell. Usually fabricated from low-cost silicon, a solar cell converts light to electri-cal energy.
4.7.4 Light-Emitting Diodes (LEDs) The light-emitting diode (LED) performs the inverse of the function of the photodiode; it converts a forward current into light. The reader will recall from Chapter 3 that in a forward-biased pn junction, minority carriers are injected across the junction and diffuse into the p 7Whereas an elemental semiconductor, such as silicon, uses an element from column IV of the periodic table, a compound semiconductor uses a combination of elements from columns III and V or II and VI.
For example, GaAs is formed of gallium (column III) and arsenic (column V) and is thus known as a III-V compound.
4.7 Special Diode Types 215 and n regions. The diffusing minority carriers then recombine with the majority carriers.
Such recombination can be made to give rise to light emission. This can be done by fabricat-ing the pn junction using a semiconductor of the type known as direct-bandgap materials.
Gallium arsenide belongs to this group and can thus be used to fabricate light-emitting diodes.
The light emitted by an LED is proportional to the number of recombinations that take place, which in turn is proportional to the forward current in the diode.
LEDs are very popular devices. They find application in the design of numerous types of displays, including the displays of laboratory instruments such as digital voltmeters. They can be made to produce light in a variety of colors. Furthermore, LEDs can be designed so as to produce coherent light with a very narrow bandwidth. The resulting device is a laser diode.
Laser diodes find application in optical communication systems and in CD players, among other things.
Combining an LED with a photodiode in the same package results in a device known as an optoisolator. The LED converts an electrical signal applied to the optoisolator into light, which the photodiode detects and converts back to an electrical signal at the output of the optoisolator. Use of the optoisolator provides complete electrical isolation between the elec-trical circuit that is connected to the isolator’s input and the circuit that is connected to its out-put. Such isolation can be useful in reducing the effect of electrical interference on signal transmission within a system, and thus optoisolators are frequently employed in the design of digital systems. They can also be used in the design of medical instruments to reduce the risk of electrical shock to patients.
Note that the optical coupling between an LED and a photodiode need not be accom-plished inside a small package. Indeed, it can be implemented over a long distance using an optical fiber, as is done in fiber-optic communication links.
Summary In the forward direction, the ideal diode conducts any current forced by the external circuit while displaying a zero voltage drop. The ideal diode does not conduct in the reverse direction; any applied voltage appears as re-verse bias across the diode.
The unidirectional-current-flow property makes the di-ode useful in the design of rectifier circuits.
The forward conduction of practical silicon-junction diodes is accurately characterized by the relationship A silicon diode conducts a negligible current until the forward voltage is at least 0.5 V. Then the current in-creases rapidly, with the voltage drop increasing by 60 mV for every decade of current change.
In the reverse direction, a silicon diode conducts a current on the order of 10−9 A. This current is much greater than IS and increases with the magnitude of reverse voltage.
Beyond a certain value of reverse voltage (that depends on the diode), breakdown occurs, and current increases rapidly with a small corresponding increase in voltage.
Diodes designed to operate in the breakdown region are called zener diodes. They are employed in the design of voltage regulators whose function is to provide a con-stant dc voltage that varies little with variations in power supply voltage and/or load current.
In many applications, a conducting diode is modeled as having a constant voltage drop, usually approximately 0.7 V.
A diode biased to operate at a dc current ID has a small-signal resistance Rectifiers convert ac voltages into unipolar voltages.
Half-wave rectifiers do this by passing the voltage in half of each cycle and blocking the opposite-polarity voltage in the other half of the cycle. Full-wave rectifiers i IS ev VT ⁄ .
= rd VT ID ⁄ .
= 216 Chapter 4 Diodes accomplish the task by passing the voltage in half of each cycle and inverting the voltage in the other half-cycle.
The bridge-rectifier circuit is the preferred full-wave rec-tifier configuration.
The variation of the output waveform of the rectifier is reduced considerably by connecting a capacitor C across the output load resistance R. The resulting circuit is the peak rectifier. The output waveform then consists of a dc voltage almost equal to the peak of the input sine wave, , on which is superimposed a ripple component of fre-quency 2f (in the full wave case) and of peak-to-peak amplitude . To reduce this ripple volt-age further a voltage regulator is employed.
Combination of diodes, resistors, and possibly reference voltages can be used to design voltage limiters that prevent one or both extremities of the output waveform from going beyond predetermined values, the limiting level(s).
Applying a time-varying waveform to a circuit consist-ing of a capacitor in series with a diode and taking the output across the diode provides a clamping function.
Specifically, depending on the polarity of the diode ei-ther the positive or negative peaks of the signal will be clamped to the voltage at the other terminal of the diode (usually ground). In this way the output waveform has a non zero average or dc component and the circuit is known as a dc restorer.
By cascading a clamping circuit with a peak-rectifier cir-cuit, a voltage doubler is realized.
Vp Vr Vp 2fCR ⁄ = PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and nonlinear distortion.
Instructions to assist in setting up PSpice and Multisim sim-ulations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 4.1: The Ideal Diode 4.1 An AA flashlight cell, whose Thévenin equivalent is a voltage source of 1.5 V and a resistance of 1 Ω, is connected to the terminals of an ideal diode. Describe two possible situations that result. What are the diode current and terminal voltage when (a) the connection is between the diode cathode and the positive terminal of the battery and (b) the anode and the positive terminal are connected?
4.2 For the circuits shown in Fig. P4.2 using ideal diodes, find the values of the voltages and currents indicated.
4.3 For the circuits shown in Fig. P4.3 using ideal diodes, find the values of the labeled voltages and currents 4.4 In each of the ideal-diode circuits shown in Fig. P4.4, vI is a 1-kHz, 10-V peak sine wave. Sketch the waveform resulting at vO. What are its positive and negative peak values?
4.5 The circuit shown in Fig. P4.5 is a model for a battery charger. Here vI is a 10-V peak sine wave, D1 and D2 are (c) 5 5 5 5 (d) 5 5 (a) 5 5 (b) Figure P4.2 CHAPTER 4 PR OBLE MS Problems 217 (a) vI 1 kV D1 vO (b) vI 1 kV D1 D2 vO (c) vI 1 kV D1 D2 vO (d) vI 1 kV D1 D2 vO (e) vI 1 kV D2 D1 vO (f) vI 1 kV D3 D1 D2 vO 5 2 (a) D D 2 5 2 2 (b) Figure P4.3 Figure P4.4 (g) vI 1 kV D1 vO (h) vI 1 kV D1 vO D2 (i) vI 1 kV 1 kV D1 vO CHAPTER 4 P RO BL E MS 218 Chapter 4 Diodes ideal diodes, I is a 60-mA current source, and B is a 3-V bat-tery. Sketch and label the waveform of the battery current iB.
What is its peak value? What is its average value? If the peak value of vI is reduced by 10%, what do the peak and average values of iB become?
4.6 The circuits shown in Fig. P4.6 can function as logic gates for input voltages that are either high or low. Using “1” to denote the high value and “0” to denote the low value, prepare a table with four columns including all possible input combinations and the resulting values of X and Y. What logic function is X of A and B? What logic function is Y of A and B?
For what values of A and B do X and Y have the same value?
For what values of A and B do X and Y have opposite values?
D 4.7 For the logic gate of Fig. 4.5(a), assume ideal diodes and input voltage levels of 0 V and +5 V. Find a suitable value for R so that the current required from each of the input signal sources does not exceed 0.2 mA.
D 4.8 Repeat Problem 4.7 for the logic gate of Fig. 4.5(b).
4.9 Assuming that the diodes in the circuits of Fig. P4.9 are ideal, find the values of the labeled voltages and currents.
4.10 Assuming that the diodes in the circuits of Fig.
P4.10 are ideal, utilize Thévenin’s theorem to simplify the circuits and thus find the values of the labeled cur-rents and voltages.
D 4.11 For the rectifier circuit of Fig. 4.3(a), let the input sine wave have 120-V rms value and assume the diode to be ideal. Select a suitable value for R so that the peak diode current does not exceed 50 mA. What is the greatest reverse voltage that will appear across the diode?
I B vI vO iB D2 D1 Figure P4.5 (a) I A X D1 D2 B (b) I A Y D3 D4 B Figure P4.6 1 3 V 2 3 V D D (a) 1 3 V 2 3 V D D (b) Figure P4.9 ( j) vI 1 kV D1 vO 1 kV (k) 1 mA 115 V vI vO D2 D1 1 kV Figure P4.4 (Contd.) CHAPTER 4 PR OBLE MS Problems 219 4.12 Consider the rectifier circuit of Fig. 4.3 in the event that the input source vI has a source resistance Rs. For the case Rs = R and assuming the diode to be ideal, sketch and clearly label the transfer characteristic vO versus vI.
4.13 A symmetrical square wave of 4-V peak-to-peak ampli-tude and zero average is applied to a circuit resembling that in Fig. 4.3(a) and employing a 100-Ω resistor. What is the peak output voltage that results? What is the average output voltage that results? What is the peak diode current? What is the aver-age diode current? What is the maximum reverse voltage across the diode?
4.14 Repeat Problem 4.13 for the situation in which the average voltage of the square wave is 1 V, while its peak-to-peak value remains at 4 V.
D 4.15 Design a battery-charging circuit, resembling that in Fig. 4.4 and using an ideal diode, in which current flows to the 12-V battery 20% of the time with an average value of 100 mA. What peak-to-peak sine-wave voltage is required?
What resistance is required? What peak diode current flows? What peak reverse voltage does the diode endure? If resistors can be specified to only one significant digit, and the peak-to-peak voltage only to the nearest volt, what design would you choose to guarantee the required charging current? What fraction of the cycle does diode current flow?
What is the average diode current? What is the peak diode current? What peak reverse voltage does the diode endure?
4.16 The circuit of Fig. P4.16 can be used in a signalling sys-tem using one wire plus a common ground return. At any moment, the input has one of three values: +3 V, 0 V, −3 V.
What is the status of the lamps for each input value? (Note that the lamps can be located apart from each other and that there may be several of each type of connection, all on one wire!) Section 4.2: Terminal Characteristics of Junction Diodes 4.17 Calculate the value of the thermal voltage, VT, at –40ºC, 0ºC, +40ºC, and +150ºC. At what temperature is VT exactly 25 mV? 4.18 At what forward voltage does a diode conduct a cur-rent equal to 1000IS? In terms of IS, what current flows in the same diode when its forward voltage is 0.7 V?
4.19 A diode for which the forward voltage drop is 0.7 V at 1.0 mA is operated at 0.5 V. What is the value of the current?
4.20 A particular diode is found to conduct 0.5 mA with a junction voltage of 0.7 V. What is its saturation current IS?
What current will flow in this diode if the junction voltage is raised to 0.71 V? To 0.8 V? If the junction voltage is low-ered to 0.69 V? To 0.6 V? What change in junction voltage will increase the diode current by a factor of 10?
4.21 The following measurements are taken on particular junction diodes for which V is the terminal voltage and I is the diode current. For each diode, estimate values of IS and the terminal voltage at 10% of the measured current. (a) V = 0.700 V at I = 1.00 A (b) V = 0.650 V at I = 1.00 mA (c) V = 0.650 V at I = 10 μA (d) V = 0.700 V at I = 10 mA 4.22 Listed below are the results of measurements taken on several different junction diodes. For each diode, the data provided are the diode current I and the corresponding diode voltage V. In each case, estimate IS , and the diode voltage at 10I and I/10.
(a) 6 V 6 V 5 V 10 k 10 k 10 k 10 k I V (b) Figure P4.10 D D Figure P4.16 CHAPTER 4 P RO BL E MS 220 Chapter 4 Diodes (a) 10.0 mA, 700 mV (b) 1.0 mA, 700 mV (c) 10 A, 800 mV (d) 1 mA, 700 mV (e) 10 μA, 700 mV 4.23 The circuit in Fig. P4.23 utilizes three identical diodes having IS = 10−16 A. Find the value of the current I required to obtain an output voltage VO = 2.4 V. If a current of 1 mA is drawn away from the output terminal by a load, what is the change in output voltage?
4.24 A junction diode is operated in a circuit in which it is supplied with a constant current I. What is the effect on the forward voltage of the diode if an identical diode is con-nected in parallel?
4.25 In the circuit shown in Fig. P4.25, D1 has 10 times the junction area of D2. What value of V results? To obtain a value for V of 50 mV, what current I2 is needed? 4.26 For the circuit shown in Fig. P4.26, both diodes are identical. Find the value of R for which V = 80 mV.
4.27 A diode fed with a constant current I = 1 mA has a voltage V = 690 mV at . Find the diode voltage at and at .
4.28 In the circuit shown in Fig. P4.28, D1 is a large-area, high-current diode whose reverse leakage is high and indepen-dent of applied voltage, while D2 is a much smaller, low-current diode. At an ambient temperature of 20°C, resistor R1 is adjusted to make VR1 = V2 = 520 mV. Subsequent measurement indicates that R1 is 520 kΩ. What do you expect the voltages VR1 and V2 to become at 0°C and at 40°C?
4.29 When a 15-A current is applied to a particular diode, it is found that the junction voltage immediately becomes 700 mV. However, as the power being dissipated in the diode raises its temperature, it is found that the voltage Figure P4.23 V D1 D2 I 2 mA 2 I 10 mA 1 Figure P4.25 V D1 D2 I 10 mA R Figure P4.26 20° C 20 – ° C +70° C D1 R1 10 V D2 V1 V2 Figure P4.28 CHAPTER 4 PR OBLE MS Problems 221 decreases and eventually reaches 600 mV. What is the apparent rise in junction temperature? What is the power dissipated in the diode in its final state? What is the temper-ature rise per watt of power dissipation? (This is called the thermal resistance.) 4.30 A designer of an instrument that must operate over a wide supply-voltage range, noting that a diode’s junction-voltage drop is relatively independent of junc-tion current, considers the use of a large diode to estab-lish a small relatively constant voltage. A power diode, for which the nominal current at 0.8 V is 10 A, is avail-able. If the current source feeding the diode changes in rhe range 0.5 mA to 1.5 mA and if, in addition, the tempera-ture changes by ±25°C, what is the expected range of diode voltage?
4.31 As an alternative to the idea suggested in Problem 4.30, the designer considers a second approach to producing a relatively constant small voltage from a variable current supply: It relies on the ability to make quite accurate copies of any small current that is available (using a process called current mirroring). The designer proposes to use this idea to supply two diodes of different junction areas with the same current and to measure their junction-voltage difference.
Two types of diodes are available; for a forward voltage of 700 mV, one conducts 0.1 mA, while the other conducts 1 A.
Now, for identical currents in the range of 0.5 mA to 1.5 mA supplied to each, what range of difference voltages result? What is the effect of a temperature change of ±25°C on this arrangement?
Section 4.3: Modeling the Diode Forward Characteristic 4.32 Consider the graphical analysis of the diode circuit of Fig. 4.10 with VDD = 1 V, R = 1 kΩ, and a diode having IS = 10−15 A. Calculate a small number of points on the diode characteristic in the vicinity of where you expect the load line to intersect it, and use a graphical process to refine your estimate of diode current. What value of diode current and voltage do you find? Analytically, find the voltage corre-sponding to your estimate of current. By how much does it differ from the graphically estimated value?
4.33 Use the iterative-analysis procedure to determine the diode current and voltage in the circuit of Fig. 4.10 for VDD = 1 V, R = 1 kΩ, and a diode having IS = 10−15 A.
4.34 A “1-mA diode” (i.e., one that has vD = 0.7 V at iD = 1 mA) is connected in series with a 200-Ω resistor to a 1.0-V supply.
(a) Provide a rough estimate of the diode current you would expect.
(b) Estimate the diode current more closely using iterative analysis.
D 4.35 Assuming the availability of diodes for which vD = 0.7 V at iD = 1 mA, design a circuit that utilizes four diodes connected in series, in series with a resistor R connected to a 10-V power supply. The voltage across the string of diodes is to be 3.0 V.
4.36 A diode operates in a series circuit with R and V.
A designer, considering using a constant-voltage model, is uncertain whether to use 0.7 V or 0.6 V for VD. For what value of V is the difference in the calculated values of cur-rent only 1%? For V = 2 V and R = 1 kΩ, what two currents would result from the use of the two values of VD? What is their percentage difference?
4.37 A designer has a supply of diodes for which a current of 2 mA flows at 0.7 V. Using a 1-mA current source, the designer wishes to create a reference voltage of 1.25 V. Sug-gest a combination of series and parallel diodes that will do the job as well as possible. How many diodes are needed?
What voltage is actually achieved?
4.38 Solve the problems in Example 4.2 using the constant-voltage-drop (VD = 0.7 V) diode model. 4.39 For the circuits shown in Fig. P4.2, using the constant-voltage-drop (VD = 0.7 V) diode model, find the voltages and currents indicated.
4.40 For the circuits shown in Fig. P4.3, using the constant-voltage-drop (VD = 0.7 V) diode model, find the voltages and currents indicated.
4.41 For the circuits in Fig. P4.9, using the constant-voltage-drop (VD = 0.7 V) diode model, find the values of the labeled currents and voltages. 4.42 For the circuits in Fig. P4.10, utilize Thévenin’s theo-rem to simplify the circuits and find the values of the labeled currents and voltages. Assume that conducting diodes can be represented by the constant-voltage-drop model (VD = 0.7 V).
D 4.43 Repeat Problem 4.11, representing the diode by the constant-voltage-drop (VD = 0.7 V) model. How different is the resulting design?
4.44 The small-signal model is said to be valid for voltage variations of about 5 mV. To what percentage current change does this correspond? (Consider both positive and negative signals.) What is the maximum allowable voltage signal (posi-tive or negative) if the current change is to be limited to 10%?
4.45 In a particular circuit application, ten “20-mA diodes” (a 20-mA diode is a diode that provides a 0.7-V drop when the current through it is 20 mA) connected in parallel CHAPTER 4 P RO BL E MS 222 Chapter 4 Diodes operate at a total current of 0.1 A. For the diodes closely matched, what current flows in each? What is the corre-sponding small-signal resistance of each diode and of the combination? Compare this with the incremental resistance of a single diode conducting 0.1 A. If each of the 20-mA diodes has a series resistance of 0.2 Ω associated with the wire bonds to the junction, what is the equivalent resistance of the 10 parallel-connected diodes? What connection resis-tance would a single diode need in order to be totally equiv-alent? (Note: This is why the parallel connection of real diodes can often be used to advantage.) 4.46 In the circuit shown in Fig. P4.46, I is a dc current and vs is a sinusoidal signal. Capacitors C1 and C2 are very large; their function is to couple the signal to and from the diode but block the dc current from flowing into the signal source or the load (not shown). Use the diode small-signal model to show that the signal component of the output voltage is If vs = 10 mV, find vo for I = 1 mA, 0.1 mA, and 1 μA. Let Rs = 1 kΩ. At what value of I does vo become one-half of vs?
Note that this circuit functions as a signal attenuator with the attenuation factor controlled by the value of the dc current I.
4.47 In the attenuator circuit of Fig. P4.46, let Rs = 10 kΩ.
The diode is a 1-mA device; that is, it exhibits a voltage drop of 0.7 V at a dc current of 1 mA. For small input sig-nals, what value of current I is needed for 0.50?
0.10? 0.01? 0.001? In each case, what is the largest input signal that can be used while ensuring that the signal com-ponent of the diode current is limited to ±10% of its dc cur-rent? What output signals correspond?
4.48 In the capacitor-coupled attenuator circuit shown in Fig.
P4.48, I is a dc current that varies from 0 mA to 1 mA, and C1 and C2 are large coupling capacitors. For very small input sig-nals, so that the diodes can be representedby their small-signal resistances rd1 and rd2, show that and hence that , where I is in mA. Find for I = 0 μA, 1 μA, 10 μA, 100 μA, 500 μA, 600 μA, 900 μA, 990 μA, and 1 mA.
4.49 In the circuit shown in Fig. P4.49, diodes D1 through D4 are identical and each exhibits a voltage drop of 0.7 V at a 1-mA current.
vo vs VT VT IRs + --------------------= C1 C2 vo Figure P4.46 vo vs ⁄ = vo vi -----rd2 rd1 rd2 + --------------------= vo vi -----I = vo vi ⁄ vo C2 C1 D2 D1 I vi 1 mA Figure P4.48 vo vi 10 k D3 I I D4 D2 D1 Figure P4.49 CHAPTER 4 PR OBLE MS Problems 223 (a) For small input signals (e.g., 10 mV peak), find values of the small-signal transmission for various values of I : 0 μA, 1 μA, 10 μA, 100 μA, 1 mA, and 10 mA.
(b) For a forward-conducting diode, what is the largest signal-voltage magnitude that it can support while the corre-sponding signal current is limited to 10% of the dc bias cur-rent. Now, for the circuit in Fig. P4.49, for 10-mV peak input, what is the smallest value of I for which the diode currents remain within ±10% of their dc value?
(c) For I = 1 mA, what is the largest possible output signal for which the diode currents deviate by at most 10% of their dc values? What is the corresponding peak input? What is the total current in each diode?
4.50 In Problem 4.49 we investigated the operation of the circuit in Fig. P4.49 for small input signals. In this prob-lem we wish to find the voltage transfer characteristic (VTC) versus for for the case I = 1 mA and each of the diodes exhibits a voltage drop of 0.7 V at a current of 1 mA. Toward this end, use the diode expo-nential characteristic to construct a table that gives the val-ues of: the current in the 10-k resistor, the current in each of the four diodes, the voltage drop across each of the four diodes, and the input voltage , for , +1 V, +2 V, +5 V, +9 V, +9.9 V, +9.99 V, +10.5 V, +11 V, and +12 V. Use these data, with extrapolation to negative values of and , to sketch the required VTC. Also sketch the VTC that results if I is reduced to 0.5 mA.
4.51 In the circuit shown in Fig. P4.51, I is a dc cur-rent and vi is a sinusoidal signal with small amplitude (less than 10 mV) and a frequency of 100 kHz. Representing the diode by its small-signal resistance rd, which is a function of I, sketch the circuit for determining the sinusoidal output voltage Vo, and thus find the phase shift between Vi and Vo.
Find the value of I that will provide a phase shift of −45°, and find the range of phase shift achieved as I is varied over the range of 0.1 times to 10 times this value. 4.52 Consider the voltage-regulator circuit shown in Fig. P4.52. The value of R is selected to obtain an output voltage VO (across the diode) of 0.7 V. (a) Use the diode small-signal model to show that the change in output voltage corresponding to a change of 1 V in V + is This quantity is known as the line regulation and is usually expressed in mV/V.
(b) Generalize the expression above for the case of m diodes connected in series and the value of R adjusted so that the voltage across each diode is 0.7 V (and VO = 0.7m V).
(c) Calculate the value of line regulation for the case V + = 10 V (nominally) and (i) m = 1 and (ii) m = 3.
4.53 Consider the voltage-regulator circuit shown in Fig P4.52 under the condition that a load current IL is drawn from the output terminal.
(a) If the value of IL is sufficiently small that the corre-sponding change in regulator output voltage ΔVO is small enough to justify using the diode small-signal model, show that This quantity is known as the load regulation and is usually expressed in mV/mA.
(b) If the value of R is selected such that at no load the volt-age across the diode is 0.7 V and the diode current is ID, show that the expression derived in (a) becomes Select the lowest possible value for ID that results in a load regulation ≤ 5 mV/mA. If V + is nominally 10 V, what value vo vi ⁄ vO vI 12 V vI 12 V ≤ ≤ – iO Ω vI vO 0 = vI vO I C 10 nF vi vo Figure P4.51 ΔVO ΔV + -----------VT V + + VT 0.7 – --------------------------------= R V VO Figure P4.52 ΔVO IL ----------rd || R ( ) – = ΔVO IL ----------VT ID ------– V + − 0.7 V + − 0.7 VT + --------------------------------- = CHAPTER 4 P RO BL E MS 224 Chapter 4 Diodes of R is required? Also, specify the diode required in terms of its IS.
(c) Generalize the expression derived in (b) for the case of m diodes connected in series and R adjusted to obtain VO = 0.7m V at no load.
4.54 Design a diode voltage regulator to supply 1.5 V to a 150-Ω load. Use two diodes specified to have a 0.7-V drop at a current of 10 mA. The diodes are to be connected to a +5-V supply through a resistor R. Specify the value for R. What is the diode current with the load connected? What is the increase resulting in the output voltage when the load is dis-connected? What change results if the load resistance is reduced to 100 Ω? To 75 Ω? To 50 Ω? (Hint: Use the small-signal diode model to calculate all changes in ouput voltage.) 4.55 A voltage regulator consisting of two diodes in series fed with a constant-current source is used as a replacement for a single carbon-zinc cell (battery) of nominal voltage 1.5 V. The regulator load current varies from 2 mA to 7 mA.
Constant-current supplies of 5 mA, 10 mA, and 15 mA are available. Which would you choose, and why? What change in output voltage would result when the load current varies over its full range?
4.56 A particular design of a voltage regulator is shown in Fig. P4.56. Diodes D1 and D2 are 10-mA units; that is, each has a voltage drop of 0.7 V at a current of 10 mA. Use the diode exponential model and iterative analysis to answer the following questions: (a) What is the regulator output voltage VO with the 150-Ω load connected?
(b) Find VO with no load.
(c) With the load connected, to what value can the 5-V sup-ply be lowered while maintaining the loaded output voltage within 0.1 V of its nominal value?
(d) What does the loaded output voltage become when the 5-V supply is raised by the same amount as the drop found in (c)?
(e) For the range of changes explored in (c) and (d), by what percentage does the output voltage change for each percentage change of supply voltage in the worst case?
Section 4.4: Operation in the Reverse Breakdown Region—Zener Diodes 4.57 Partial specifications of a collection of zener diodes are provided below. For each, identify the missing parameter, and estimate its value. Note from Fig. 4.17 that (a) VZ = 10.0 V, VZK = 9.6 V, and IZT = 50 mA (b) IZT = 10 mA, VZ = 9.1 V, and rz = 30 Ω (c) rz = 2 Ω, VZ = 6.8 V, and VZK = 6.6 V (d) VZ = 18 V, IZT = 5 mA, and VZK = 17.6 V (e) IZT = 200 mA, VZ = 7.5 V, and rz = 1.5 Ω Assuming that the power rating of a breakdown diode is established at about twice the specified zener current (IZT), what is the power rating of each of the diodes described above?
D 4.58 A designer requires a shunt regulator of approxi-mately 20 V. Two kinds of zener diodes are available: 6.8-V devices with rz of 10 Ω and 5.1-V devices with rz of 30 Ω.
For the two major choices possible, find the load regulation. In this calculation neglect the effect of the regulator resistance R.
4.59 A shunt regulator utilizing a zener diode with an incremental resistance of 5 Ω is fed through an 82-Ω resis-tor. If the raw supply changes by 1.0 V, what is the corre-sponding change in the regulated output voltage? 4.60 A 9.1-V zener diode exhibits its nominal voltage at a test current of 28 mA. At this current the incremental resis-tance is specified as 5 Ω. Find VZ0 of the zener model. Find the zener voltage at a current of 10 mA and at 100 mA.
D 4.61 Design a 7.5-V zener regulator circuit using a 7.5-V zener specified at 12 mA. The zener has an incremental resistance rz = 30 Ω and a knee current of 0.5 mA. The regu-lator operates from a 10-V supply and has a 1.2-kΩ load.
What is the value of R you have chosen? What is the regula-tor output voltage when the supply is 10% high? Is 10% low? What is the output voltage when both the supply is 10% high and the load is removed? What is the smallest possible load resistor that can be used while the zener oper-ates at a current no lower than the knee current while the supply is 10% low? What is the load voltage in this case?
D 4.62 Provide two designs of shunt regulators utilizing the 1N5235 zener diode, which is specified as follows: VZ = 6.8 V and rz = 5 Ω for IZ = 20 mA; at IZ = 0.25 mA (nearer the knee), rz = 750 Ω. For both designs, the supply voltage is nominally 9 V and varies by ±1 V. For the first design, assume that the availability of supply current is not a problem, 180 5 V D1 D2 VO 150 Figure P4.56 VZK VZ0.
CHAPTER 4 PR OBLE MS Problems 225 and thus operate the diode at 20 mA. For the second design, assume that the current from the raw supply is limited, and therefore you are forced to operate the diode at 0.25 mA. For the purpose of these initial designs, assume no load. For each design find the value of R and the line regulation.
D 4.63 A zener shunt regulator employs a 9.1-V zener diode for which VZ = 9.1 V at IZ = 9 mA, with rz = 30 Ω and IZK = 0.3 mA. The available supply voltage of 15 V can vary as much as ±10%. For this diode, what is the value of VZ0? For a nominal load resistance RL of 1 kΩ and a nominal zener current of 10 mA, what current must flow in the supply resistor R? For the nominal value of supply voltage, select a value for resistor R, specified to one significant digit, to provide at least that current.
What nominal output voltage results? For a ±10% change in the supply voltage, what variation in output voltage results? If the load current is reduced by 50%, what increase in VO results?
What is the smallest value of load resistance that can be tolerated while maintaining regulation when the supply voltage is low?
What is the lowest possible output voltage that results? Calculate values for the line regulation and for the load regulation for this circuit using the numerical results obtained in this problem.
D 4.64 It is required to design a zener shunt regulator to provide a regulated voltage of about 10 V. The available 10-V, 1-W zener of type 1N4740 is specified to have a 10-V drop at a test current of 25 mA. At this current, its rz is 7 Ω.
The raw supply, VS , available has a nominal value of 20 V but can vary by as much as ±25%. The regulator is required to supply a load current of 0 mA to 20 mA. Design for a minimum zener current of 5 mA.
(a) Find VZ0.
(b) Calculate the required value of R.
(c) Find the line regulation. What is the change in VO ex-pressed as a percentage, corresponding to the ±25% change in VS?
(d) Find the load regulation. By what percentage does VO change from the no-load to the full-load condition?
(e) What is the maximum current that the zener in your design is required to conduct? What is the zener power dis-sipation under this condition?
Section 4.5: Rectifier Circuits 4.65 Consider the half-wave rectifier circuit of Fig. 4.21(a) with the diode reversed. Let vS be a sinusoid with 12-V peak amplitude, and let R = 1.5 kΩ. Use the constant-voltage-drop diode model with VD = 0.7 V.
(a) Sketch the transfer characteristic.
(b) Sketch the waveform of vO.
(c) Find the average value of vO.
(d) Find the peak current in the diode.
(e) Find the PIV of the diode.
4.66 Using the exponential diode characteristic, show that for vS and vO both greater than zero, the circuit of Fig. 4.21(a) has the transfer characteristic where vS and vO are in volts and R is in kilohms. Note that this relationship can be used to obtain the voltage transfer characteristic vO vs vS by finding vS corresponding to vari-ous values of vO.
4.67 Consider a half-wave rectifier circuit with a triangular-wave input of 5-V peak-to-peak amplitude and zero average, and with R = 1 kΩ. Assume that the diode can be represented by the constant-voltage-drop model with VD = 0.7 V. Find the average value of vO.
4.68 A half-wave rectifier circuit with a 1-kΩ load oper-ates from a 120-V (rms) 60-Hz household supply through a 10-to-1 step-down transformer. It uses a silicon diode that can be modeled to have a 0.7-V drop for any current.
What is the peak voltage of the rectified output? For what fraction of the cycle does the diode conduct? What is the average output voltage? What is the average current in the load?
4.69 A full-wave rectifier circuit with a 1-kΩ load operates from a 120-V (rms) 60-Hz household supply through a 5-to-1 transformer having a center-tapped secondary winding. It uses two silicon diodes that can be modeled to have a 0.7-V drop for all currents. What is the peak voltage of the recti-fied output? For what fraction of a cycle does each diode conduct? What is the average output voltage? What is the average current in the load?
4.70 A full-wave bridge rectifier circuit with a 1-kΩ load operates from a 120-V (rms) 60-Hz household supply through a 10-to-1 step-down transformer having a single secondary winding. It uses four diodes, each of which can be modeled to have a 0.7-V drop for any current. What is the peak value of the rectified voltage across the load? For what fraction of a cycle does each diode conduct? What is the average voltage across the load? What is the average current through the load?
4.71 It is required to design a full-wave rectifier circuit using the circuit of Fig. 4.22 to provide an average output voltage of: (a) 10 V (b) 100 V In each case find the required turns ratio of the transformer.
Assume that a conducting diode has a voltage drop of 0.7 V.
The ac line voltage is 120 V rms.
vO vS vD at iD 1 mA = ( ) – VT ln vO R ⁄ ( ) – = CHAPTER 4 P RO BL E MS 226 Chapter 4 Diodes 4.72 Repeat Problem 4.71 for the bridge rectifier circuit of Fig. 4.23.
D 4.73 Consider the full-wave rectifier in Fig. 4.22 when the transformer turns ratio is such that the voltage across the entire secondary winding is 24 V rms. If the input ac line voltage (120 V rms) fluctuates by as much as ±10%, find the required PIV of the diodes. (Remember to use a factor of safety in your design.) 4.74 The circuit in Fig. P4.74 implements a complemen-tary-output rectifier. Sketch and clearly label the waveforms of and Assume a 0.7-V drop across each conducting diode. If the magnitude of the average of each output is to be 15 V, find the required amplitude of the sine wave across the entire secondary winding. What is the PIV of each diode?
4.75 Augment the rectifier circuit of Problem 4.68 with a capacitor chosen to provide a peak-to-peak ripple voltage of (i) 10% of the peak output and (ii) 1% of the peak output. In each case: (a) What average output voltage results?
(b) What fraction of the cycle does the diode conduct?
(c) What is the average diode current?
(d) What is the peak diode current?
4.76 Repeat Problem 4.75 for the rectifier in Problem 4.69.
4.77 Repeat Problem 4.75 for the rectifier in Problem 4.70.
D 4.78 It is required to use a peak rectifier to design a dc power supply that provides an average dc output voltage of 15 V on which a maximum of ±1-V ripple is allowed. The rectifier feeds a load of 150 Ω. The rectifier is fed from the line voltage (120 V rms, 60 Hz) through a transformer. The diodes available have 0.7-V drop when conducting. If the designer opts for the half-wave circuit: (a) Specify the rms voltage that must appear across the transformer secondary.
(b) Find the required value of the filter capacitor.
(c) Find the maximum reverse voltage that will appear across the diode, and specify the PIV rating of the diode.
(d) Calculate the average current through the diode during conduction.
(e) Calculate the peak diode current.
D 4.79 Repeat Problem 4.78 for the case in which the designer opts for a full-wave circuit utilizing a center-tapped transformer.
D 4.80 Repeat Problem 4.78 for the case in which the designer opts for a full-wave bridge rectifier circuit.
D 4.81 Consider a half-wave peak rectifier fed with a volt-age vS having a triangular waveform with 20-V peak-to-peak amplitude, zero average, and 1-kHz frequency.
Assume that the diode has a 0.7-V drop when conducting.
Let the load resistance R = 100 Ω and the filter capacitor C = 100 μF. Find the average dc output voltage, the time interval during which the diode conducts, the average diode current during conduction, and the maximum diode current.
D 4.82 Consider the circuit in Fig. P4.74 with two equal filter capacitors placed across the load resistors R. Assume that the diodes available exhibit a 0.7-V drop when con-ducting. Design the circuit to provide ±15-V dc output voltages with a peak-to-peak ripple no greater than 1 V.
Each supply should be capable of providing 200 mA dc current to its load resistor R. Completely specify the capac-itors, diodes and the transformer.
4.83 The op amp in the precision rectifier circuit of Fig. P4.83 is ideal with output saturation levels of ±12 V. Assume that when conducting the diode exhibits a constant voltage drop of 0.7 V. Find v−, vO, and vA for: (a) vI = +1 V (b) vI = +2 V (c) vI = −1 V (d) vI = −2 V vO + v− O.
D D D D Figure P4.74 CHAPTER 4 PR OBLE MS Problems 227 Also, find the average output voltage obtained when vI is a symmetrical square wave of 1-kHz frequency, 3-V ampli-tude, and zero average.
4.84 The op amp in the circuit of Fig. P4.84 is ideal with output saturation levels of ±12 V. The diodes exhibit a con-stant 0.7-V drop when conducting. Find v−, vA, and vO for: (a) vI = +1 V (b) vI = +2 V (c) vI = −1 V (d) vI = −2 V Section 4.6: Limiting and Clamping Circuits 4.85 Sketch the transfer characteristic vO versus vI for the limiter circuits shown in Fig. P4.85. All diodes begin con-ducting at a forward voltage drop of 0.5 V and have voltage drops of 0.7 V when conducting a current iD 1 mA.
4.86 The circuits in Fig. P4.85(a) and (d) are connected as follows: The two input terminals are tied together, and the two output terminals are tied together. Sketch the transfer characteristic of the circuit resulting, assuming that the cut-in voltage of the diodes is 0.5 V and their voltage drop when conducting a current iD 1 mA is 0.7 V.
4.87 Repeat Problem 4.86 for the two circuits in Fig.
P4.85(a) and (b) connected together as follows: The two input terminals are tied together, and the two output terminals are tied together.
4.88 Sketch and clearly label the transfer characteristic of the circuit in Fig. P4.88 for −20 V vI +20 V. Assume that the diodes can be represented by the constant-voltage-D vI vA R R vO v RL Figure P4.83 R D1 D2 vI vO v vA R Figure P4.84 1 k 2 V vO vI (a) 1 k 2 V vO vI (b) 1 k 2 V vO vI (d) 1 k 2 V vO vI (c) Figure P4.85 CHAPTER 4 P RO BL E MS 228 Chapter 4 Diodes drop model with VD = 0.7 V. Also assume that the zener voltage is 8.2 V and that rz is negligibly small.
4.89 Plot the transfer characteristic of the circuit in Fig.P4.89 by evaluating vI corresponding to vO = 0.5 V, 0.6 V, 0.7 V, 0.8 V, 0 V, −0.5 V, −0.6 V, −0.7 V, and −0.8 V.
Assume that the diodes have 0.7-V drops at 1-mA currents.
Characterize the circuit as a hard or soft limiter. What is the value of K? Estimate L+ and L−.
4.90 Design limiter circuits using only diodes and 10-kΩ resistors to provide an output signal limited to the range: (a) −0.7 V and above (b) −2.1 V and above (c) ±1.4 V Assume that each diode has a 0.7-V drop when conducting.
4.91 Design a two-sided limiting circuit using a resistor, two diodes, and two power supplies to feed a 1-kΩ load with nominal limiting levels of ±3 V. Use diodes modeled by a constant 0.7 V. In the nonlimiting region, the voltage gain should be at least 0.95 V/V.
4.92 In the circuit shown in Fig. P4.92, the diodes exhibit a 0.7-V drop at 0.1 mA. For inputs over the range of ±5 V, provide a calibrated sketch of the voltages at outputs B and C versus vA. For a 5-V peak, 100-Hz sinusoid applied at A, sketch the signals at nodes B and C.
4.93 Sketch and label the voltage transfer characteristic vO versus vI of the circuit shown in Fig. P4.93 over a ±10-V range of input signals. All diodes are 1-mA units (i.e., each exhibits a 0.7-V drop at a current of 1 mA). What are the slopes of the characteristic at the extreme ±10-V levels? 4.94 A clamped capacitor using an ideal diode with cathode grounded is supplied with a sine wave of 10-V rms. What is the average (dc) value of the resulting output?
4.95 For the circuits in Fig. P4.95, each utilizing an ideal diode (or diodes), sketch the output for the input shown.
Label the most positive and most negative output levels.
Assume CR T.
D D D D Figure P4.88 Figure P4.89 D2 D1 D3 D C A B 1 k 5 k 4 Figure P4.92 1 k 3 k 1 k D1 vO vI 1 V 2 V D2 D3 Figure P4.93 CHAPTER 4 PR OBLE MS Problems 229 Figure P4.95 (a) (b) (c) (d) (e) (f) (g) (h) CHAPTER 5 MOS Field-Effect Transistors (MOSFETs) Introduction 231 5.1 Device Structure and Physical Operation 232 5.2 Current—Voltage Characteristics 247 5.3 MOSFET Circuits at DC 258 5.4 Applying the MOSFET in Amplifier Design 268 5.5 Small-Signal Operation and Models 276 5.6 Basic MOSFET Amplifier Configurations 291 5.7 Biasing in MOS Amplifier Circuits 306 5.8 Discrete-Circuit MOS Amplifiers 314 5.9 The Body Effect and Other Topics 323 Summary 328 Problems 329 231 IN THIS CHAPTER YOU WILL LEARN 1. The physical structure of the MOS transistor and how it works.
2. How the voltage between two terminals of the transistor controls the current that flows through the third terminal, and the equations that de-scribe these current–voltage characteristics.
3. How to analyze and design circuits that contain MOS transistors, resis-tors, and dc sources.
4. How the transistor can be used to make an amplifier, and how it can be used as a switch in digital circuits.
5. How to obtain linear amplification from the fundamentally nonlinear MOS transistor.
6. The three basic ways for connecting a MOSFET to construct amplifiers with different properties.
7. Practical circuits for MOS–transistor amplifiers that can be constructed us-ing discrete components.
Introduction Having studied the junction diode, which is the most basic two-terminal semiconductor device, we now turn our attention to three-terminal semiconductor devices. Three-terminal devices are far more useful than two-terminal ones because they can be used in a multitude of applications, ranging from signal amplification to digital logic and memory. The basic principle involved is the use of the voltage between two terminals to control the current flowing in the third terminal. In this way a three-terminal device can be used to realize a controlled source, which as we have learned in Chapter 1 is the basis for amplifier design.
Also, in the extreme, the control signal can be used to cause the current in the third terminal to change from zero to a large value, thus allowing the device to act as a switch. As we shall see in Chapter 13, the switch is the basis for the realization of the logic inverter, the basic element of digital circuits.
There are two major types of three-terminal semiconductor devices: the metal-oxide-semiconductor field-effect transistor (MOSFET), which is studied in this chapter, and the 232 Chapter 5 MOS Field-Effect Transistors (MOSFETs) bipolar junction transistor (BJT), which we shall study in Chapter 6. Although each of the two transistor types offers unique features and areas of application, the MOSFET has become by far the most widely used electronic device, especially in the design of integrated circuits (ICs), which are entire circuits fabricated on a single silicon chip.
Compared to BJTs, MOSFETs can be made quite small (i.e., requiring a small area on the silicon IC chip), and their manufacturing process is relatively simple (see Appendix A).
Also, their operation requires comparatively little power. Furthermore, circuit designers have found ingenious ways to implement digital and analog functions utilizing MOSFETs almost exclusively (i.e., with very few or no resistors). All of these properties have made it possible to pack large numbers of MOSFETs (as many as 2 billion!) on a single IC chip to implement very sophisticated, very-large-scale-integrated (VLSI) digital circuits such as those for memory and microprocessors. Analog circuits such as amplifiers and filters can also be implemented in MOS technology, albeit in smaller, less-dense chips. Also, both ana-log and digital functions are increasingly being implemented on the same IC chip, in what is known as mixed-signal design.
The objective of this chapter is to develop in the reader a high degree of familiarity with the MOSFET: its physical structure and operation, terminal characteristics, circuit models, and basic circuit applications. Although discrete MOS transistors exist, and the material stud-ied in this chapter will enable the reader to design discrete MOS circuits, our study of the MOSFET is strongly influenced by the fact that most of its applications are in integrated-cir-cuit design. The design of IC analog and digital MOS circuits occupies a large proportion of the remainder of this book.
5.1 Device Structure and Physical Operation The enhancement-type MOSFET is the most widely used field-effect transistor. Except for the last section, this chapter is devoted to the study of the enhancement-type MOSFET. We begin in this section by learning about its structure and physical operation. This will lead to the current–voltage characteristics of the device, studied in the next section.
5.1.1 Device Structure Figure 5.1, shows the physical structure of the n-channel enhancement-type MOSFET. The meaning of the names “enhancement” and “n-channel” will become apparent shortly. The transistor is fabricated on a p-type substrate, which is a single-crystal silicon wafer that pro-vides physical support for the device (and for the entire circuit in the case of an integrated circuit). Two heavily doped n-type regions, indicated in the figure as the n+ source1 and the n+ drain regions, are created in the substrate. A thin layer of silicon dioxide (SiO2) of thick-ness tox (typically 1 to 10 nm),2 which is an excellent electrical insulator, is grown on the sur-face of the substrate, covering the area between the source and drain regions. Metal is deposited on top of the oxide layer to form the gate electrode of the device. Metal contacts are also made to the source region, the drain region, and the substrate, also known as the 1The notation n+ indicates heavily doped n-type silicon. Conversely, n− is used to denote lightly doped n-type silicon. Similar notation applies for p-type silicon.
2A nanometer (nm) is 10−9 m or 0.001 μm. A micrometer (μm), or micron, is 10−6 m. Sometimes the oxide thickness is expressed in angstroms. An angstrom (Å) is 10−1 nm, or 10−10 m.
5.1 Device Structure and Physical Operation 233 body.3 Thus four terminals are brought out: the gate terminal (G), the source terminal (S), the drain terminal (D), and the substrate or body terminal (B).
At this point it should be clear that the name of the device (metal-oxide-semiconductor FET) is derived from its physical structure. The name, however, has become a general one and Figure 5.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross sec-tion. Typically L = 0.03 μm to 1 μm, W = 0.1 μm to 100 μm, and the thickness of the oxide layer (tox) is in the range of 1 to 10 nm.
3In Fig. 5.1, the contact to the body is shown on the bottom of the device. This will prove helpful in Section 5.9 in explaining a phenomenon known as the “body effect.” It is important to note, however, that in actual ICs, contact to the body is made at a location on the top of the device.
W S G D B Source region Drain region (a) n Oxide (SiO2) Metal L n p-type substrate (Body) Channel region n L Metal Channel region Oxide (SiO2) (thickness tox) p-type substrate (Body) n Source (S) Gate (G) Drain (D) Body (B) (b) 234 Chapter 5 MOS Field-Effect Transistors (MOSFETs) is used also for FETs that do not use metal for the gate electrode. In fact, most modern MOS-FETs are fabricated using a process known as silicon-gate technology, in which a certain type of silicon, called polysilicon, is used to form the gate electrode (see Appendix A). Our description of MOSFET operation and characteristics applies irrespective of the type of gate electrode.
Another name for the MOSFET is the insulated-gate FET or IGFET. This name also arises from the physical structure of the device, emphasizing the fact that the gate electrode is electrically insulated from the device body (by the oxide layer). It is this insulation that causes the current in the gate terminal to be extremely small (of the order of 10−15 A).
Observe that the substrate forms pn junctions with the source and drain regions. In normal operation these pn junctions are kept reverse-biased at all times. Since, as we shall see shortly, the drain will always be at a positive voltage relative to the source, the two pn junctions can be effectively cut off by simply connecting the substrate terminal to the source terminal. We shall assume this to be the case in the following description of MOSFET operation. Thus, here, the substrate will be considered as having no effect on device operation, and the MOSFET will be treated as a three-terminal device, with the terminals being the gate (G), the source (S), and the drain (D). It will be shown that a voltage applied to the gate controls current flow between source and drain. This current will flow in the longitudinal direction from drain to source in the region labeled “channel region.” Note that this region has a length L and a width W, two important parameters of the MOSFET. Typically, L is in the range of 0.03 μm to 1 μm, and W is in the range of 0.1 μm to 100 μm. Finally, note that the MOSFET is a symmetrical device; thus its source and drain can be interchanged with no change in device characteristics.
5.1.2 Operation with Zero Gate Voltage With zero voltage applied to the gate, two back-to-back diodes exist in series between drain and source. One diode is formed by the pn junction between the n+ drain region and the p-type substrate, and the other diode is formed by the pn junction between the p-type substrate and the n+ source region. These back-to-back diodes prevent current conduction from drain to source when a voltage vDS is applied. In fact, the path between drain and source has a very high resistance (of the order of 1012 Ω).
5.1.3 Creating a Channel for Current Flow Consider next the situation depicted in Fig. 5.2. Here we have grounded the source and the drain and applied a positive voltage to the gate. Since the source is grounded, the gate voltage appears in effect between gate and source and thus is denoted vGS. The positive voltage on the gate causes, in the first instance, the free holes (which are positively charged) to be repelled from the region of the substrate under the gate (the channel region). These holes are pushed downward into the substrate, leaving behind a carrier-depletion region. The depletion region is populated by the bound negative charge associated with the acceptor atoms. These charges are “uncovered” because the neutralizing holes have been pushed downward into the substrate.
As well, the positive gate voltage attracts electrons from the n+ source and drain regions (where they are in abundance) into the channel region. When a sufficient number of electrons accumulate near the surface of the substrate under the gate, an n region is in effect created, connecting the source and drain regions, as indicated in Fig. 5.2. Now if a voltage is applied between drain and source, current flows through this induced n region, carried by the mobile electrons. The induced n region thus forms a channel for current flow from drain to source and is aptly called so. Correspondingly, the MOSFET of Fig. 5.2 is called an n-channel MOSFET or, alternatively, an NMOS transistor. Note that an n-channel MOSFET is 5.1 Device Structure and Physical Operation 235 formed in a p-type substrate: The channel is created by inverting the substrate surface from p type to n type. Hence the induced channel is also called an inversion layer.
The value of at which a sufficient number of mobile electrons accumulate in the channel region to form a conducting channel is called the threshold voltage and is denoted Vt.4 Obviously, Vt for an n-channel FET is positive. The value of Vt is controlled during device fabrication and typically lies in the range of 0.3 V to 1.0 V.
The gate and the channel region of the MOSFET form a parallel-plate capacitor, with the oxide layer acting as the capacitor dielectric. The positive gate voltage causes positive charge to accumulate on the top plate of the capacitor (the gate electrode). The correspond-ing negative charge on the bottom plate is formed by the electrons in the induced channel.
An electric field thus develops in the vertical direction. It is this field that controls the amount of charge in the channel, and thus it determines the channel conductivity and, in turn, the current that will flow through the channel when a voltage vDS is applied. This is the origin of the name “field-effect transistor” (FET).
The voltage across this parallel-plate capacitor, that is, the voltage across the oxide, must exceed for a channel to form. When as in Fig. 5.2, the voltage at every point along the channel is zero, and the voltage across the oxide (i.e., between the gate and the points along the channel) is uniform and equal to . The excess of over is termed the effective voltage or the overdrive voltage and is the quantity that determines the charge in the channel. In this book, we shall denote by , (5.1) We can express the magnitude of the electron charge in the channel by (5.2) Figure 5.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.
4Some texts use VT to denote the threshold voltage. We use Vt to avoid confusion with the thermal voltage VT.
L Oxide (SiO2) Gate electrode Induced n-type channel Depletion region n p-type substrate n S G D vGS B vGS Vt vDS 0, = vGS vGS Vt vGS Vt – ( ) vOV vGS Vt vOV ≡ – Q Cox WL ( )vOV = 236 Chapter 5 MOS Field-Effect Transistors (MOSFETs) where , called the oxide capacitance, is the capacitance of the parallel-plate capacitor per unit gate area (in units of F/m2), W is the width of the channel, and L is the length of the channel. The oxide capacitance is given by (5.3) where is the permittivity of the silicon dioxide, F/m The oxide thickness is determined by the process technology used to fabricate the MOS-FET. As an example, for a process with nm, F/m2 It is much more convenient to express per micron squared. For our example, this yields 8.6 fF/μm2, where fF denotes femtofarad ( F). For a MOSFET fabricated in this tech-nology with a channel length L = 0.18 μm and a channel width W = 0.72 μm, the total capac-itance between gate and channel is fF Finally, note from Eq. (5.2) that as is increased, the magnitude of the channel charge increases proportionately. Sometimes this is depicted as an increase in the depth of the chan-nel; that is, the larger the overdrive voltage, the deeper the channel.
5.1.4 Applying a Small vDS Having induced a channel, we now apply a positive voltage vDS between drain and source, as shown in Fig. 5.3. We first consider the case where vDS is small (i.e., 50 mV or so). The voltage vDS causes a current iD to flow through the induced n channel. Current is carried by free elec-trons traveling from source to drain (hence the names source and drain). By convention, the direction of current flow is opposite to that of the flow of negative charge. Thus the current in the channel, iD, will be from drain to source, as indicated in Fig. 5.3. We now wish to calculate the value of . Toward that end, we first note that because is small, we can continue to assume that the voltage between the gate and various points along the channel remains approximately constant and equal to the value at the source end, . Thus, the effective voltage between the gate and the various points along the channel remains equal to , and the channel charge Q is still given by Eq. (5.2). Of particular interest in calculating the current is the charge per unit channel length, which can be found from Eq. (5.2) as (5.4) The voltage establishes an electric field E across the length of the channel, (5.5) This electric field in turn causes the channel electrons to drift toward the drain with a veloc-ity given by Electron drift velocity = μn = μn (5.6) Cox Cox Cox εox tox --------= εox εox 3.9ε0 3.9 8.854 10 12 – × × 3.45 10 11 – × = = = tox tox 4 = Cox 3.45 10 11 – × 4 10 9 – × -----------------------------8.6 10 3 – × = = Cox 10 15 – C CoxWL 8.6 0.18 0.72 × × 1.1 = = = vOV iD vDS vGS vOV iD Q unit channel length ----------------------------------------------------CoxWvOV = vDS E vDS L --------= E vDS L --------5.1 Device Structure and Physical Operation 237 n+ n+ iD where μn is the mobility of the electrons at the surface of the channel. It is a physical parameter whose value depends on the fabrication process technology. The value of can now be found by multiplying the charge per unit channel length (Eq. 5.4) by the electron drift velocity (Eq. 5.6), (5.7) Thus, for small , the channel behaves as a linear resistance whose value is controlled by the overdrive voltage , which in turn is determined by : (5.8) The conductance of the channel can be found from Eq. (5.7) or (5.8) as (5.9) or (5.10) Observe that the conductance is determined by the product of three factors: , (W/L), and (or equivalently, ). To gain insight into MOSFET operation, we consider each of the three factors in turn.
The first factor, , is determined by the process technology used to fabricate the MOSFET. It is the product of the electron mobility, μn, and the oxide capacitance, . It makes physical sense for the channel conductance to be proportional to each of μn and Figure 5.3 An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a resistance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS − Vt, and thus iD is proportional to (vGS − Vt)vDS. Note that the depletion region is not shown (for simplicity).
iD iD μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞vOV vDS = vDS vOV vGS iD μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞vGS Vt – ( ) vDS = gDS gDS μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞vOV = gDS μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞vGS Vt – ( ) = μnCox ( ) vOV vGS Vt – μnCox ( ) Cox Cox 238 Chapter 5 MOS Field-Effect Transistors (MOSFETs) (why?) and hence to their product, which is termed the process transconductance parameter5 and given the symbol where the subscript n denotes n channel, (5.11) It can be shown that with μn having the dimensions of meters squared per volt-second (m2/V·s) and having the dimensions of farads per meter squared (F/m2), the dimensions of are amperes per volt squared (A/V2). The second factor in the expression for the conductance in Eqs. (5.9) and (5.10) is the transistor aspect ratio (W/L). That the channel conductance is proportional to the channel width W and inversely proportional to the channel length L should make perfect physical sense. The (W/L) ratio is obviously a dimensionless quantity that is determined by the device designer. Indeed, the values of W and L can be selected by the device designer to give the device the characteristics desired. For a given fabrication process, however, there is a minimum channel length, Lmin. In fact, the minimum channel length that is possible with a given fabrication process is used to characterize the process and is being continually reduced as technology advances. For instance, in 2009 the state-of-the-art in commercially available MOS technology was a 45-nm process, meaning that for this process the minimum channel length possible was 45 nm. Finally, we should note that the oxide thickness scales down with Lmin. Thus, for a 0.13-μm technology, is 2.7 nm, but for the modern 45-nm technol-ogy is about 1.4 nm. The product of the process transconductance parameter and the transistor aspect ratio (W/L) is the MOSFET transconductance parameter , (W/L) (5.12a) or (W/L) (5.12b) The MOSFET parameter has the dimensions of A/V2.
The third term in the expression of the channel conductance is the overdrive voltage . This is hardly surprising since directly determines the magnitude of electron charge in the channel. As will be seen, is a very important circuit-design parameter. In this book, we will use and interchangeably.
We conclude this subsection by noting that with kept small, the MOSFET behaves as a linear resistance whose value is controlled by the gate voltage (5.13a) (5.13b) The operation of the MOSFET as a voltage-controlled resistance is further illustrated in Fig. 5.4, which is a sketch of versus for various values of . Observe that the 5This name arises from the fact that determines the transconductance of the MOSFET, as will be seen shortly.
kn ′ μnCox ( ) kn ′ μnCox = Cox kn ′ gDS i v – tox tox tox k′ n kn kn k′ n = kn μnCox ( ) = kn gDS vOV vOV vOV vOV vGS Vt – vDS rDS vGS, rDS 1 gDS --------= rDS 1 μnCox ( ) W L ⁄ ( )vOV ---------------------------------------------= rDS 1 μnCox ( ) W L ⁄ ( ) vGS Vt – ( ) -------------------------------------------------------------= iD vDS vGS 5.1 Device Structure and Physical Operation 239 resistance is infinite for and decreases as is increased above . It is interest-ing to note that although is used as the parameter for the set of graphs in Fig. 5.4, the graphs in fact depend only on (and, of course, ).
The description above indicates that for the MOSFET to conduct, a channel has to be induced. Then, increasing above the threshold voltage Vt enhances the channel, hence the names enhancement-mode operation and enhancement-type MOSFET. Finally, we note that the current that leaves the source terminal (iS) is equal to the current that enters the drain terminal (iD), and the gate current iG = 0.
5.1.5 Operation as vDS Is Increased We next consider the situation as is increased. For this purpose, let be held constant at a value greater than ; that is, let the MOSFET be operated at a constant overdrive voltage .
Refer to Fig. 5.5, and note that appears as a voltage drop across the length of the channel.
That is, as we travel along the channel from source to drain, the voltage (measured relative to the source) increases from zero to . Thus the voltage between the gate and points along the chan-nel decreases from at the source end to at the drain end. Since the channel depth depends on this voltage, and specifically on the amount by which this voltage exceeds , we find that the channel is no longer of uniform depth; rather, the channel will take the tapered shape shown in Fig. 5.5, being deepest at the source end (where the depth is proportional to ) and shallowest at the drain end6 (where the depth is propor-tional to ). This point is further illustrated in Fig. 5.6.
Figure 5.4 The iD–vDS characteristics of the MOSFET in Fig. 5.3 when the voltage applied between drain and source, vDS, is kept small. The device operates as a linear resistance whose value is controlled by vGS.
6For simplicity, we do not show in Fig. 5.5 the depletion region. Physically speaking, it is the widening of the depletion region as a result of the increased that makes the channel shallower near the drain.
vGS Vt vGS Vt + VOV1 vGS iD 0 Slope gDS = kn VOV vGS Vt + VOV2 vGS Vt + VOV3 vDS vGS Vt ≤ vGS Vt vGS vOV kn vGS vDS vGS Vt VOV vDS vDS vGS Vt VOV + = vGD vGS vDS – Vt VOV vDS – + = = Vt VOV vDS VOV vDS – 5.1 A 0.18-μm fabrication process is specified to have nm, μn = 450 cm2/V•s, and V.
Find the value of the process transconductance parameter . For a MOSFET with minimum length fabricated in this process, find the required value of W so that the device exhibits a channel resistance of 1 k at V.
Ans. 388 μA/V2; 0.93 μm tox 4 = Vt 0.5 = k ′ n rDS Ω vGS 1 = EXERCISE 240 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Figure 5.5 Operation of the enhancement NMOS transistor as is increased. The induced channel acquires a tapered shape, and its resistance increases as is increased. Here, is kept constant at a value > Vt; n n vDS vDS vGS vGS Vt VOV.
+ = Source x (a) L 2 Drain Drain 0 L vGD vDS VOV VOV (VOV VGS Voltage Vt Average = 1 vDS Voltage drop along the channel 2 2 1vDS) (VOV vDS) Source (b) Channel Figure 5.6 (a) For a MOSFET with vGS = Vt + VOV, application of vDS causes the voltage drop along the channel to vary linearly, with an average value of vDS at the midpoint. Since vGD > Vt, the channel still exists at the drain end. (b) The channel shape corresponding to the situation in (a). While the depth of the channel at the source end is still proportional to VOV, that at the drain end is proporational to (VOV – vDS).
1 2 --5.1 Device Structure and Physical Operation 241 As is increased, the channel becomes more tapered and its resistance increases cor-respondingly. Thus, the curve does not continue as a straight line but bends as shown in Fig. 5.7. The equation describing this portion of the curve can be easily derived by utilizing the information in Fig. 5.6. Specifically, note that the charge in the tapered channel is proportional to the channel cross-sectional area shown in Fig. 5.6(b). This area in turn can be easily seen as proportional to or . Thus, the relationship between and can be found by replacing in Eq. (5.7) by , (5.14) This relationship describes the semiparabolic portion of the curve in Fig. 5.7. It applies to the entire segment down to . Specifically, note that as is reduced, we can neglect relative to in the factor in parentheses, and the expression reduces to that in Eq. (5.7). The latter of course is an approximation and applies only for small (i.e., near the origin).
There is another useful interpretation of the expression in Eq. (5.14). From Fig. 5.6(a) we see that the average voltage along the channel is . Thus, the average voltage that gives rise to channel charge and hence to is no longer but , which is indeed the factor that appears in Eq. (5.14). Finally, we note that Eq. (5.14) is frequently written in the alternate form (5.15) Furthermore, for an arbitrary value of , we can replace by and rewrite Eq.
(5.15) as (5.16) Figure 5.7 The drain current iD versus the drain-to-source voltage vDS for an enhancement-type NMOS transistor operated with vGS = Vt + VOV.
iD V DS sat (vDS VOV) vGS = + Vt 0 Triode Saturation (vDS VOV) Curve bends because the channel resistance increases with vDS Almost a straight line with slope proportional to VOV VOV Current saturates because the channel is pinched off at the drain end, and vDS no longer affects the channel.
vDS VOV vDS iD vDS – iD vDS – 1 2 - VOV VOV vDS – ( ) + [ ] VOV 1 2 -vDS – ( ) iD vDS VOV VOV 1 2 -vDS – ( ) iD k′ n W L -----⎝ ⎠ ⎛ ⎞VOV 1 2 ---vDS – ⎝ ⎠ ⎛ ⎞vDS = iD vDS – vDS 0 = vDS 1 2 -vDS VOV vDS 1 2 -vDS iD VOV VOV 1 2 -vDS – ( ) iD k ′ n W L -----⎝ ⎠ ⎛ ⎞VOV vDS 1 2 ---– vDS 2 ⎝ ⎠ ⎛ ⎞ = VOV VOV vGS Vt – ( ) iD k ′ n W L -----⎝ ⎠ ⎛ ⎞ vGS Vt – ( )vDS 1 2 ---vDS 2 – = 242 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.1.6 Operation for vDSVOV The above description of operation assumed that even though the channel became tapered, it still had a finite (nonzero) depth at the drain end. This in turn is achieved by keeping sufficiently small that the voltage between the gate and the drain, , exceeds . This is indeed the situation shown in Fig. 5.6(a). Note that for this situation to obtain, must not exceed , for as , , and the channel depth at the drain end reduces to zero.
Figure 5.8 shows reaching and correspondingly reaching . The zero depth of the channel at the drain end gives rise to the term channel pinch-off. Increasing beyond this value (i.e., ) has no effect on the channel shape and charge, and the current through the channel remains constant at the value reached for . The drain current thus saturates at the value found by substituting in Eq. (5.14), (5.17) The MOSFET is then said to have entered the saturation region (or, equivalently, the satu-ration mode of operation). The voltage at which saturation occurs is denoted , (5.18) It should be noted that channel pinch-off does not mean channel blockage: Current contin-ues to flow through the pinched-off channel, and the electrons that reach the drain end of the vDS vGD Vt vDS VOV vDS VOV = vGD Vt = vDS VOV vGD Vt vDS vDS VOV > Source x Voltage drop along the channel (a) L 2 Drain Drain 0 L vGD = Vt vDS = VOV VOV Voltage Vt Average = 1 VOV 2 2 1 VOV Source (b) Channel VGS Figure 5.8 Operation of MOSFET with vGS = Vt + VOV, as vDS is increased to V OV. At the drain end, vGD decreases to Vt and the channel depth at the drain end reduces to zero (pinch off). At this point, the MOSFET enters the saturation mode of operation. Further increasing vDS (beyond VDsat = VOV) has no effect on the channel shape and iD remains constant.
vDS VOV = vDS VOV = iD 1 2 ---k ′ n W L -----⎝ ⎠ ⎛ ⎞VOV 2 = vDS VDSsat VDSsat VOV VGS Vt – = = 5.1 Device Structure and Physical Operation 243 channel are accelerated through the depletion region that exists there (not shown in Fig. 5.5) and into the drain terminal. Any increase in above appears as a voltage drop across the depletion region. Thus, both the current through the channel and the voltage drop across it remain constant in saturation. The saturation portion of the curve is, as expected, a horizontal straight line, as indicated in Fig. 5.7. Also indicated in Fig. 5.7 is the name of the region of operation obtained with a continuous (non-pinched-off) channel, the triode region. This name is a carryover from the days of vacuum-tube devices, whose operation a FET resembles.
Finally, we note that the relationship in saturation can be generalized by replac-ing the constant overdrive voltage by a variable one, : (5.19) Also, can be replaced by to obtain the alternate expression for saturation-mode , (5.20) vDS VDSsat iD vDS – iD vDS – VOV vOV iD 1 2 ---k ′ n W L -----⎝ ⎠ ⎛ ⎞vOV 2 = vOV vGS Vt – ( ) iD iD 1 2 ---k ′ n W L -----⎝ ⎠ ⎛ ⎞vGS Vt – ( )2 = Consider a process technology for which Lmin = 0.4 μm, tox = 8 nm, μn = 450 cm2/V⋅s, and Vt = 0.7 V.
(a) Find Cox and .
(b) For a MOSFET with , calculate the values of VOV, VGS, and VDSmin needed to operate the transistor in the saturation region with a dc current ID = 100 μA.
(c) For the device in (b), find the values of VOV and VGS required to cause the device to operate as a 1000- resistor for very small vDS.
Solution (a) (b) For operation in the saturation region, Thus, which results in kn ′ W L ⁄ 8 μm 0.8 ⁄ μm = Cox εox tox -------3.45 10 11 – × 8 10 9 – × -----------------------------4.32 10 3 – × F/m2 = = = 4.32 fF/μm2 = kn ′ = μnCox = 450 cm2/V⋅s ( ) 4.32 fF/μm2 ( ) × 450 108 μm2/V⋅s ( ) × 4.32 10 15 – × × F/μm2 ( ) = 194 10 6 – × F/V⋅s ( ) = 194 μA/V2 = iD = 1 2 --- kn ′W L -----vOV 2 100 1 2 ---194 8 0.8 -------VOV × × 2 = VOV 0.32 V = Example 5.1 244 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.1.7 The p-Channel MOSFET Figure 5.9(a) shows a cross-sectional view of a p-channel enhancement-type MOSFET. The structure is similar to that of the NMOS device except that here the substrate is n type and the source and the drain regions are p+ type; that is, all semiconductor regions are reversed in polarity relative to their counterparts in the NMOS case. The PMOS and NMOS transistor are said to be complementary devices.
To induce a channel for current flow between source and drain, a negative voltage is applied to the gate, that is, between gate and source, as indicated in Fig. 5.9(b). By increasing the magni-Example 5.1 continued Thus, and (c) For the MOSFET in the triode region with vDS very small, Thus which yields Thus, VGS Vt VOV 1.02 = V + = VDSmin VOV 0.32 V = = rDS 1 k′n W L -----VOV ----------------------= 1000 1 194 10 6 – 10 × VOV × × -------------------------------------------------------= VOV 0.52 V = VGS 1.22 V = 5.2 For a 0.8-μm process technology for which tox = 15 nm and μn = 550 cm2/V⋅s, find Cox, , and the overdrive voltage required to operate a transistor having in saturation with ID = 0.2 mA. What is the minimum value of VDS needed?
Ans. 2.3 fF/μm2; 0.40 V; 0.40 V D5.3 A circuit designer intending to operate a MOSFET in saturation is considering the effect of chang-ing the device dimensions and operating voltages on the drain current . Specifically, by what fac-tor does change in each of the following cases?
(a) The channel length is doubled.
(b) The channel width is doubled.
(c) The overdrive voltage is doubled.
(d) The drain-to-source voltage is doubled.
(e) Changes (a), (b), (c), and (d) are made simultaneously.
Which of these cases might cause the MOSFET to leave the saturation region?
Ans. 0.5; 2; 4; no change; 4; case (c) if is smaller than 2 kn ′ VOV W L ⁄ = 20 127 μA/V2; ID ID vDS VOV EXERCISES 5.1 Device Structure and Physical Operation 245 tude of the negative beyond the magnitude of the threshold voltage , which by convention is negative, a p channel is established as shown in Fig. 5.9(b). This condition can be described as or, to avoid dealing with negative signs, Now, to cause a current to flow in the p channel, a negative voltage is applied to the drain. The current is carried by holes and flows through the channel from source to drain.
As we have done for the NMOS transistor, we define the process transconductance parame-ter for the PMOS device as vGS Vtp vGS Vtp ≤ vGS Vtp ≥ iD vDS iD k′ p μpCox = D G B S S n-type substrate p+ p+ D G B n-type substrate induced p channel (a) p+ p+ iD iG = 0 iD vGS vDS iD Figure 5.9 (a) Physical structure of the PMOS transistor. Note that it is similar to the NMOS transistor shown in Fig. 5.1(b) except that all semiconductor regions are reversed in polarity. (b) A negative voltage vGS of magnitude greater than |Vtp| induces a p channel, and a negative vDS causes a current iD to flow from source to drain.
246 Chapter 5 MOS Field-Effect Transistors (MOSFETs) where μp is the mobility of the holes in the induced p channel. Typically, μp = 0.25 μn to 0.5 μn and is process technology dependent. The transistor transconductance parameter is obtained by multiplying by the aspect ratio W/L, The remainder of the description of the physical operation of the p-channel MOSFET follows that for the NMOS device, except of course for the sign reversals of all voltages. We will present the complete current–voltage characteristics of both NMOS and PMOS transis-tors in the next section.
PMOS technology originally dominated MOS integrated-circuit manufacturing, and the original microprocessors utilized PMOS transistors. As the technological difficulties of fabricating NMOS transistors were solved, NMOS completely supplanted PMOS. The main reason for this change is that electron mobility μn is higher by a factor of 2 to 4 than the hole mobility μp, resulting in NMOS transistors having greater gains and speeds of operation than PMOS devices. Subsequently, a technology was developed that permits the fabrication of both NMOS and PMOS transistors on the same chip. Appropriately called complementary MOS, or CMOS, this technology is currently the dominant electronics technology.
5.1.8 Complementary MOS or CMOS As the name implies, complementary MOS technology employs MOS transistors of both polarities. Although CMOS circuits are somewhat more difficult to fabricate than NMOS, the availability of complementary devices makes possible many powerful circuit con-figurations. Indeed, at the present time CMOS is the most widely used of all the IC tech-nologies. This statement applies to both analog and digital circuits. CMOS technology has virtually replaced designs based on NMOS transistors alone. Furthermore, by 2009 CMOS technology had taken over many applications that just a few years earlier were possible only with bipolar devices. Throughout this book, we will study many CMOS circuit techniques.
Figure 5.10 shows a cross section of a CMOS chip illustrating how the PMOS and NMOS transistors are fabricated. Observe that while the NMOS transistor is implemented directly in the p-type substrate, the PMOS transistor is fabricated in a specially created n region, known as an n well. The two devices are isolated from each other by a thick region of oxide that functions as an insulator. Not shown on the diagram are the connections made to the p-type body and to the n well. The latter connection serves as the body terminal for the PMOS transistor.
5.1.9 Operating the MOS Transistor in the Subthreshold Region The above description of the n-channel MOSFET operation implies that for vGS < Vt, no cur-rent flows and the device is cut off. This is not entirely true, for it has been found that for values of vGS smaller than but close to Vt, a small drain current flows. In this subthreshold region of operation, the drain current is exponentially related to vGS, much like the iC–vBE relationship of a BJT, as will be shown in the next chapter.
Although in most applications the MOS transistor is operated with vGS > Vt, there are special, but a growing number of, applications that make use of subthreshold operation. In Chapter 13, we will briefly consider subthreshold operation.
kp k′ p kp k′ p W L ⁄ ( ) = 5.2 Current–Voltage Characteristics 247 5.2 Current–Voltage Characteristics Building on the physical foundation established in the previous section for the operation of the enhancement MOS transistor, in this section we present its complete current–voltage characteristics. These characteristics can be measured at dc or at low frequencies and thus are called static characteristics. The dynamic effects that limit the operation of the MOSFET at high frequencies and high switching speeds will be discussed in Chapter 9.
5.2.1 Circuit Symbol Figure 5.11(a) shows the circuit symbol for the n-channel enhancement-type MOSFET.
Observe that the spacing between the two vertical lines that represent the gate and the chan-nel indicates the fact that the gate electrode is insulated from the body of the device. The polarity of the p-type substrate (body) and the n channel is indicated by the arrowhead on the Figure 5.10 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.
Figure 5.11 (a) Circuit symbol for the n-channel enhancement-type MOSFET. (b) Modified circuit sym-bol with an arrowhead on the source terminal to distinguish it from the drain and to indicate device polarity (i.e., n channel). (c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the body on device operation is unimportant.
G D n n PMOS S SiO2 Thick SiO2 (isolation) G Polysilicon S Gate oxide NMOS D SiO2 p-type body n well p p (a) B D S G (b) B D S G (c) D S G 248 Chapter 5 MOS Field-Effect Transistors (MOSFETs) line representing the body (B). This arrowhead also indicates the polarity of the transistor, namely, that it is an n-channel device.
Although the MOSFET is a symmetrical device, it is often useful in circuit design to des-ignate one terminal as the source and the other as the drain (without having to write S and D beside the terminals). This objective is achieved in the modified circuit symbol shown in Fig. 5.11(b). Here an arrowhead is placed on the source terminal, thus distinguishing it from the drain terminal. The arrowhead points in the normal direction of current flow and thus indicates the polarity of the device (i.e., n channel). Observe that in the modified symbol, there is no need to show the arrowhead on the body line. Although the circuit symbol of Fig. 5.11(b) clearly distinguishes the source from the drain, in practice it is the polarity of the voltage impressed across the device that determines source and drain; the drain is always positive relative to the source in an n-channel FET.
In applications where the source is connected to the body of the device, a further simplifica-tion of the circuit symbol is possible, as indicated in Fig. 5.11(c). This symbol is also used in appli-cations when the effect of the body on circuit operation is not important, as will be seen later.
5.2.2 The iD–vDS Characteristics Table 5.1 provides a compilation of the conditions and the formulas for the operation of the NMOS transistor in each of the three possible regions: the cutoff region, the triode region, and the saturation region. The first two are useful if the MOSFET is to be utilized as a switch.
On the other hand, if the MOSFET is to be used to design an amplifier, it must be operated in the saturation region. The rationale for these choices will be addressed in Section 5.4.
At the top of Table 5.1 we show a circuit consisting of an NMOS transistor and two dc supplies providing and . This conceptual circuit can be used to measure the iD– characteristic curves of the NMOS transistor. Each curve is measured by setting to a desired constant value, varying , and measuring the corresponding . Two of these char-acteristic curves are shown in the accompanying diagram: one for and the other for (Note that we now use to denote the threshold voltage of the NMOS transistor, to distinguish it from that of the PMOS transistor, denoted .) As Table 5.1 shows, the boundary between the triode region and the saturation region is determined by whether is less or greater than the overdrive voltage at which the transistor is operating. An equivalent way to check for the region of operation is to examine the relative values of the drain and gate voltages. To operate in the triode region, the gate volt-age must exceed the drain voltage by at least volts, which ensures that the channel remains continuous (not pinched off). On the other hand, to operate in saturation, the channel must be pinched off at the drain end; pinch-off is achieved here by keeping higher than that is, not allowing to fall below by more than volts. The graphical construction of Fig. 5.12 should serve to remind the reader of these conditions.
A set of characteristics for the NMOS transistor is shown in Fig. 5.13. Observe that each graph is obtained by setting above by a specific value of overdrive voltage, denoted , , , and . This in turn is the value of at which the corresponding graph saturates, and the value of the resulting saturation current is directly determined by the value of , namely, , , . . . The reader is advised to commit to memory both the structure of these graphs and the coordinates of the saturation points.
Finally, observe that the boundary between the triode and the saturation regions, that is, the locus of the saturation points, is a parabolic curve described by vGS vDS vDS vGS vDS iD vGS Vtn < vGS Vtn vOV.
+ = Vtn Vtp vDS vOV Vtn vD vG Vtn, – vD vG Vtn iD vDS – vGS Vtn VOV1 VOV2 VOV3 VOV4 vDS vOV 1 2 -k′ nVOV1 2 1 2 -k′ nVOV2 2 iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vDS 2 = 5.2 Current–Voltage Characteristics 249 Table 5.1 Regions of Operation of the Enhancement NMOS Transistor : no channel; transistor in cut-off; : a channel is induced; transistor operates in the triode region or the saturation region depend-ing on whether the channel is continuous or pinched-off at the drain end; + + + − − − vGS vGD vDS vDS < vOV v 2 OV kn vGS < Vtn vGS = Vtn + vOV vDS ≥ vOV vOV vDS Cut-off 0 Triode Saturation Slope = 1 2 W ( ) L iD iD v OV = kn W ( ) L gDS = 1 rDS vGS Vtn < iD 0 = vGS Vtn vOV + = Triode Region Continuous channel, obtained by: or equivalently: Then, or equivalently, Saturation Region Pinched-off channel, obtained by: or equivalently: Then or equivalently, vGD Vtn > vDS vOV < iD k′ n W L -----⎝ ⎠ ⎛ ⎞ vGS Vtn – ( )vDS 1 2 ---vDS 2 – = iD k′ n W L -----⎝ ⎠ ⎛ ⎞vOV 1 2 ---vDS – ⎝ ⎠ ⎛ ⎞vDS = vGD Vtn vDS vOV iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vGS Vtn – ( )2 = iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vOV 2 = Overdrive voltage VOV Figure 5.12 The relative levels of the terminal voltages of the enhancement NMOS transistor for opera-tion in the triode region and in the saturation region.
250 Chapter 5 MOS Field-Effect Transistors (MOSFETs) vDS vOV Saturation region vDS vOV Triode region vDS = vOV iD = kn ( ) vDS W L 1 2 2 vGS = Vt + VOV3 vGS = Vt + VOV2 vGS = Vt + VOV1 vDS vGS Vt (Cutoff) vGS = Vt + VOV4 VOV1 0 VOV2 VOV3 VOV4 W L kn ( ) VO 2 V1 1 2 W L kn ( ) VO 2 V2 1 2 W L kn ( ) VO 2 V3 1 2 W L kn ( ) VO 2 V4 1 2 iD Figure 5.13 The iD– characteristics for an enhancement-type NMOS transistor.
vDS 5.2.3 The iD– vGS Characteristic When the MOSFET is used to design an amplifier, it is operated in the saturation region. As Fig. 5.13 indicates, in saturation the drain current is constant determined by (or ) and is independent of That is, the MOSFET operates as a constant-current source where the value of the current is determined by In effect, then, the MOSFET operates as a voltage-controlled current source with the control relationship described by (5.21) or in terms of , (5.22) This is the relationship that underlies the application of the MOSFET as an amplifier. That it is nonlinear should be of concern to those interested in designing linear amplifiers. Never-theless, later in this chapter, we will see how one can obtain linear amplification from this nonlinear control or transfer characteristic.
Figure 5.14 shows the iD– characteristic of an NMOS transistor operating in satura-tion. Note that if we are interested in a plot of versus , we simply shift the origin to the point .
The view of the MOSFET in the saturation region as a voltage-controlled current source is illustrated by the equivalent-circuit representation shown in Fig. 5.15. For reasons that will become apparent shortly, the circuit in Fig. 5.15 is known as a large-signal equivalent cir-cuit. Note that the current source is ideal, with an infinite output resistance representing the independence, in saturation, of from This, of course, has been assumed in the idealized model of device operation utilized thus far. We are about to rectify an important shortcoming of this model. First, however, we present an example.
vGS vOV vDS.
vGS.
iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vGS Vtn – ( )2 = vOV iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vOV 2 = vGS iD vOV vGS Vtn = iD vDS.
5.2 Current–Voltage Characteristics 251 k tn tn tn Figure 5.15 Large-signal equivalent-circuit model of an n-channel MOSFET operating in the saturation RS RG Y RD 5 V X Z Figure 5.14 The iD–vGS characteristic of an NMOS transistor operating in the saturation region. The iD–vOV characteristic can be obtained by simply re-labelling the horizontal axis; that is, shifting the origin to the point vGS = Vtn.
vDS vGS – Vtn vGS vOV Vtn iD 0 0 Consider an NMOS transistor fabricated in a 0.18-μm process with L = 0.18 μm and W = 2 μm. The pro-cess technology is specified to have fF/μm2, μn = 450 cm2/ and V.
(a) Find and that result in the MOSFET operating at the edge of saturation with μA.
(b) If is kept constant, find that results in μA.
(c) To investigate the use of the MOSFET as a linear amplifier, let it be operating in saturation with V. Find the change in resulting from changing from 0.7 V by V and by V.
Cox 8.6 = V s, ⋅ Vtn 0.5 = VGS VDS ID 100 = VGS VDS ID 50 = VDS 0.3 = iD vGS +0.01 0.01 – Example 5.2 252 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Solution First we determine the process transconductance parameter A/V2 = 387 μA/V2 and the transistor transconductance parameter , mA/V2 (a) With the transistor operating in saturation, Thus, which results in V Thus, V and since operation is at the edge of saturation, V (b) With kept constant at 0.72 V and reduced from the value obtained at the edge of saturation, the MOSFET will now be operating in the triode region, thus which can be rearranged to the form This quadratic equation has two solutions V and V The second answer is greater than and thus is physically meaningless, since we know that the transis-tor is operating in the triode region. Thus we have V k′ n k′ n μnCox = 450 10 4 – × 8.6 10 15 – × × 1012 × = kn kn k′ n W L -----⎝ ⎠ ⎛ ⎞ = 387 2 0.18 ----------⎝ ⎠ ⎛ ⎞ = 4.3 = ID 1 2 ---knVOV 2 = 100 1 2 ---4.3 103 × × VOV 2 × = VOV 0.22 = VGS Vtn VOV + 0.5 0.22 + 0.72 = = = VDS VOV 0.22 = = VGS ID ID kn VOV VDS 1 2 ---VDS 2 – = 50 4.3 103 × 0.22VDS 1 2 ---VDS 2 – = VDS 2 0.44VDS – 0.023 + 0 = VDS 0.06 = VDS 0.39 = VOV VDS 0.06 = 5.2 Current–Voltage Characteristics 253 5.2.4 Finite Output Resistance in Saturation Equation (5.21) and the corresponding large-signal equivalent circuit in Fig. 5.15, as well as the graphs in Fig. 5.13, indicate that in saturation, iD is independent of vDS. Thus, a change ΔvDS in the drain-to-source voltage causes a zero change in iD, which implies that the incre-mental resistance looking into the drain of a saturated MOSFET is infinite. This, however, is an idealization based on the premise that once the channel is pinched off at the drain end, further increases in vDS have no effect on the channel’s shape. But, in practice, increasing vDS beyond vOV does affect the channel somewhat. Specifically, as vDS is increased, the channel pinch-off point is moved slightly away from the drain, toward the source. This is illustrated in Fig. 5.16, from which we note that the voltage across the channel remains constant at vOV, and the additional voltage applied to the drain appears as a voltage drop across the narrow depletion region between the end of the channel and the drain region. This voltage acceler-ates the electrons that reach the drain end of the channel and sweeps them across the deple-tion region into the drain. Note, however, that (with depletion-layer widening) the channel Example 5.2 continued (c) For V, V, and since V, the transistor is operating in saturation and = 86 μA Now for V, V and μA and for V, V, and μA Thus, with V, μA; and for V, μA.
We conclude that the two changes are almost equal, an indication of almost-linear operation when the changes in are kept small. This is just a preview of the “small-signal operation” of the MOSFET stud-ied in Sections 5.4 and 5.5.
vGS 0.7 = VOV 0.2 = VDS 0.3 = ID 1 2 ---knVOV 2 = 1 2 ---4300 0.04 × × = vGS 0.710 = vOV 0.21 = iD 1 2 ---4300 0.212 × × 94.8 = = vGS 0.690 = vOV 0.19 = iD 1 2 ---4300 0.192 × × 77.6 = = VGS Δ +0.01 = iD Δ 8.8 = VGS Δ 0.01 – = iD Δ 8.4 – = vGS 5.4 An NMOS transistor is operating at the edge of saturation with an overdrive voltage and a drain current If is doubled, and we must maintain operation at the edge of saturation, what should be changed to? What value of drain current results?
Ans. 2 ; 4 5.5 An n-channel MOSFET operating with V exhibits a linear resistance = 1 k when is very small. What is the value of the device transconductance parameter kn? What is the value of the current obtained when is increased to 0.5 V? and to 1 V?
Ans. 2 mA/V2; 0.25 mA; 0.25 mA VOV ID.
VOV VDS VOV ID VOV 0.5 = rDS Ω vDS ID vDS EXERCISES 254 Chapter 5 MOS Field-Effect Transistors (MOSFETs) length is in effect reduced, from L to , a phenomenon known as channel-length modulation. Now, since iD is inversely proportional to the channel length (Eq. 5.21), iD increases with vDS. This effect can be accounted for in the expression for by including a factor or, for simplicity, (5.23) Here is a device parameter having the units of reciprocal volts . The value of depends both on the process technology used to fabricate the device and on the channel length L that the circuit designer selects. Specifically, the value of is much larger for newer submicron technol-ogies than for older technologies. This makes intuitive sense: Newer technologies have very short channels, and are thus much greatly impacted by the channel-length modulation effect.
Also, for a given process technology, is inversely proportional to L. A typical set of iD–vDS characteristics showing the effect of channel-length modulation is displayed in Fig. 5.17. The observed linear dependence of iD on vDS in the saturation region is represented in Eq. (5.23) by the factor (1 + λvDS). From Fig. 5.17 we observe that when the straight-line iD–vDS characteristics are extrapolated, they intercept the vDS axis at the point, vDS = −VA, where VA is a positive voltage. Equation (5.23), however, indicates that iD = 0 at It follows that and thus VA is a device parameter with the dimensions of V. For a given process, VA is pro-portional to the channel length L that the designer selects for a MOSFET. We can isolate the dependence of VA on L by expressing it as where is entirely process-technology dependent with the dimensions of volts per micron.
Typically, falls in the range of 5 V/μm to 50 V/μm. The voltage VA is usually referred to as the Early voltage, after J. M. Early, who discovered a similar phenomenon for the BJT (Chapter 6). Equation (5.23) indicates that when channel-length modulation is taken into account, the saturation values of iD depend on vDS. Thus, for a given vGS, a change ΔvDS yields a corresponding change ΔiD in the drain current iD. It follows that the output resistance of the current source representing iD in saturation is no longer infinite. Defining the output resistance ro as7 7In this book we use ro to denote the output resistance in saturation, and rDS to denote the drain-to-source resistance in the triode region, for small vDS.
Drain Source L L L Channel vOV vDS vOV L Figure 5.16 Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by ΔL).
L ΔL – iD 1 λ vDS vOV – ( ) + 1 λ vDS + ( ), iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vGS Vtn – ( )2 1 λ vDS + ( ) = λ V 1 – ( ) λ λ λ vDS 1 λ.
⁄ – = VA 1 λ ---= VA VA ′ L = VA ′ VA ′ 5.2 Current–Voltage Characteristics 255 (5.24) and using Eq. (5.23) results in (5.25) which can be written as (5.26) or, equivalently, (5.27) where ID is the drain current without channel-length modulation taken into account; that is, (5.27′) Figure 5.17 Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the pro-cess technology and, for a given process, is proportional to the channel length L.
Figure 5.18 Large-signal equivalent circuit model of the n-channel MOSFET in saturation, incorporating the output resistance ro. The output resistance models the linear dependence of iD on vDS and is given by Eq. (5.23). Triode Saturation 0 Slope VOV 1 ro vDS VA 1/ iD vGS tn ro ∂iD ∂vDS -----------vGS constant 1 – ≡ ro λkn ′ 2 ------W L ----- VGS Vtn – ( ) 2 1 – = ro 1 λID --------= ro VA ID ------= ID = 1 2 --- kn ′ W L ------ VGS Vtn – ( ) 2 256 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Thus the output resistance is inversely proportional to the drain current. Finally, we show in Fig. 5.18 the large-signal, equivalent-circuit model incorporating ro.
5.2.5 Characteristics of the p-Channel MOSFET The circuit symbol for the p-channel enhancement-type MOSFET is shown in Fig. 5.19(a).
Figure 5.19(b) shows a modified circuit symbol in which an arrowhead pointing in the nor-mal direction of current flow is included on the source terminal. For the case where the source is connected to the substrate, the simplified symbol of Fig. 5.19(c) is usually used. The regions of operation of the PMOS transistor and the corresponding conditions and expression for are shown in Table 5.2. Observe that the equations are written in a way that emphasizes physical intuition and avoids the confusion of negative signs. Thus while is by convention negative, we use , and the voltages and are posi-tive. Also, in all of our circuit diagrams we will always draw p-channel devices with their sources on top so that current flows from top to bottom. Finally, we note that PMOS devices also suffer from the channel-length modulation effect. This can be taken into account by including a factor in the saturation-region expression for as follows (5.28) Figure 5.19 (a) Circuit symbol for the p-channel enhancement-type MOSFET. (b) Modified symbol with an arrowhead on the source lead. (c) Simplified circuit symbol for the case where the source is connected to the body.
5.6 An NMOS transistor is fabricated in a 0.4-μm process having μnCox = 200 μA/V2 and of channel length. If L = 0.8 μm and W = 16 μm, find VA and λ. Find the value of ID that results when the device is operated with an overdrive voltage VOV = 0.5 V and VDS = 1 V. Also, find the value of ro at this operating point. If VDS is increased by 2 V, what is the corresponding change in ID?
Ans. 40 V; 0.025 V−1; 0.51 mA; 80 kΩ; 0.025 mA V′ A 50 V/μm = EXERCISE B S D G (a) (b) S G B D (c) iD Vtp Vtp vSG vSD 1 λ vSD + ( ) iD iD 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞vSG Vtp – ( )2 1 λ vSD + ( ) = 257 or equivalently (5.29) where and (the Early voltage for the PMOS transistor) are by convention negative quantities, hence we use and .
Finally, we should note that for a given CMOS fabrication process and are gener-ally not equal, and similarly for and To recap, to turn a PMOS transistor on, the gate voltage has to be made lower than that of the source by at least To operate in the triode region, the drain voltage has to exceed that of the gate by at least otherwise, the PMOS operates in saturation. Finally, Fig. 5.20 provides a pictorial representation of these operating conditions. Table 5.2 Regions of Operation of the Enhancement PMOS Transistor : no channel; transistor in cut-off; : a channel is induced; transistor operates in the triode region or in the saturation region depending on whether the channel is continuous or pinched-off at the drain end; iD 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞vSG Vtp – ( )2 1 vSD VA ---------+ ⎝ ⎠ ⎛ ⎞ = λ VA λ VA λn λp VAn VAp .
Vtp .
Vtp ; + + − + − − vSG vSD vDG vSD < |vOV| v 2 OV kp vSG < |Vtp| vSG = |Vtp| + |vOV| vSD ≥ |vOV| Cut-off 0 Triode Saturation Slope = 1 2 W ( ) L iD iD |v OV| |v OV| v SD = kp W ( ) L gDS = 1 rDS vSG Vtp < iD 0 = vSG Vtp vOV + = Triode Region Continuous channel, obtained by: or equivalently: Then, or equivalently Saturation Region Pinched-off channel, obtained by: or equivalently Then or equivalently vDG Vtp > vSD vOV < iD kp ′ W L -----⎝ ⎠ ⎛ ⎞ vSG Vtp – ( )vSD 1 2 ---vSD 2 – = iD kp ′ W L -----⎝ ⎠ ⎛ ⎞ vOV 1 2 ---vSD – ⎝ ⎠ ⎛ ⎞vSD = vDG Vtp vSD vOV iD 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞vSG Vtp – ( ) 2 = iD 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞vOV 2 = 258 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.3 MOSFET Circuits at DC Having studied the current–voltage characteristics of MOSFETs, we now consider circuits in which only dc voltages and currents are of concern. Specifically, we shall present a series of design and analysis examples of MOSFET circuits at dc. The objective is to instill in the reader a familiarity with the device and the ability to perform MOSFET circuit analysis both rapidly and effectively.
In the following examples, to keep matters simple and thus focus attention on the essence of MOSFET circuit operation, we will generally neglect channel-length modulation; that is, we will assume λ = 0. We will find it convenient to work in terms of the overdrive voltage; VOV = VGS − Vtn for NMOS and for PMOS.
Vtp VOV Voltage S G D Triode Saturation Threshold Vtp Overdrive voltage Figure 5.20 The relative levels of the terminal voltages of the enhancement-type PMOS transis-tor for operation in the triode region and in the saturation region.
5.7 The PMOS transistor shown in Fig. E5.7 has and (a) Find the range of VG for which the transistor conducts. (b) In terms of VG, find the range of VD for which the transistor operates in the triode region. (c) In terms of VG, find the range of VD for which the transistor operates in saturation. (d) Neglecting channel-length modulation (i.e., assuming λ = 0), find the values of and VG and the corresponding range of VD to operate the transistor in the saturation mode with ID = 75 μA. (e) If λ = −0.02 V−1, find the value of ro corresponding to the overdrive voltage determined in (d). (f) For λ = −0.02 V−1 and for the value of VOV determined in (d), find ID at VD = +3 V and at VD = 0 V; hence, calculate the value of the apparent output resistance in saturation. Compare to the value found in (e).
Ans. (a) (b) (c) (d) 0.5 V, 3.5 V, ≤4.5 V; (e) 0.67 MΩ; (f) 78 μA, 82.5 μA, 0.67 MΩ (same) Vtp 1 V, k′ p = – 60 μA/ V2, = W L ⁄ 10.
= VOV 5 V VG VD ID Figure E5.7 VG +4 V; ≤ VD VG 1; + ≥ VD VG 1; + ≤ EXERCISE VOV VSG Vtp – = 5.3 MOSFET Circuits at DC 259 Design the circuit of Fig. 5.21, that is, determine the values of and , so that the transistor operates at ID = 0.4 mA and VD = +0.5 V. The NMOS transistor has Vt = 0.7 V, μnCox = 100 μA/V2, L = 1 μm, and W = 32 μm. Neglect the channel-length modulation effect (i.e., assume that λ = 0). To establish a dc voltage of +0.5 V at the drain, we must select RD as follows: To determine the value required for , we need to know the voltage at the source, which can be easily found if we know . This in turn can be determined from . Toward that end, we note that since VD = 0.5 V is greater than VG, the NMOS transistor is operating in the saturation region, and we can use the sat-uration-region expression of iD to determine the required value of VOV, Then substituting ID = 0.4 mA = 400 μA, μnCox = 100 μA/V2, and gives which results in Thus, Referring to Fig. 5.21, we note that the gate is at ground potential. Thus, the source must be at −1.2 V, and the required value of RS can be determined from Solution RD RS VDD 2.5 V VSS 2.5 V Figure 5.21 Circuit for Example 5.3.
RD VDD VD – ID -----------------------= 2.5 0.5 – 0.4 ---------------------= 5 kΩ = RS VGS VOV ID 1 2 ---μnCox W L -----VOV 2 = W L ⁄ 32 1 ⁄ = 400 1 2 ---100 32 1 ------× × VOV 2 = VOV 0.5 V = VGS Vt VOV + 0.7 0.5 + 1.2 V = = = RS VS VSS – ID --------------------= −1.2 2.5 – ( ) – 0.4 ----------------------------------= 3.25 kΩ = Example 5.3 260 Chapter 5 MOS Field-Effect Transistors (MOSFETs) D5.8 Redesign the circuit of Fig. 5.21 for the following case: VDD = −VSS = 2.5 V, Vt = 1 V, μnCox = 60 μA/V2, ID = 0.3 mA, and VD = +0.4 V.
Ans. RD = 7 kΩ; RS = 3.3 kΩ W L ⁄ 120 μm 3 ⁄ μm, = EXERCISE Figure 5.22 shows an NMOS transistor with its drain and gate terminals connected together. Find the relationship of the resulting two-terminal device in terms of the MOSFET parameters and Neglect channel-length modulation (i.e., . Note that this two-terminal device is known as a diode-connected transistor.
Solution Since implies operation in the saturation mode, Now, and , thus Replacing by results in i v – kn k′ n W L ⁄ ( ) = Vtn.
λ 0) = i v Figure 5.22 vD vG = iD 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞vGS Vtn – ( )2 = i iD = v vGS = i 1 2 ---k′ n W L -----⎝ ⎠ ⎛ ⎞v Vtn – ( )2 = k′ n W L -----⎝ ⎠ ⎛ ⎞ kn i 1 2 ---kn v Vtn – ( )2 = Example 5.4 5.3 MOSFET Circuits at DC 261 D5.9 For the circuit in Fig. E5.9, find the value of R that results in V. The MOSFET has V, mA/V2, and Ans. 13.9 k D5.10Figure E5.10, shows a circuit obtained by augmenting the circuit of Fig. E5.9 considered in Exer-cise 5.9 with a transistor identical to and a resistance . Find the value of that results in operating at the edge of the saturation region. Use your solution to Exercise 5.9.
Ans. 20.8 k VD 0.8 = Vtn 0.5 = μnCox 0.4 = W L ⁄ 0.72 μm 0.18 μm ---------------------, = λ 0.
= Ω Q1 1.8 V R VD Figure E5.9 Q2 Q1 R2 R2 Q2 Ω Q1 Q2 R2 VDD1.8 V R Figure E5.10 EXERCISES Design the circuit in Fig. 5.23 to establish a drain voltage of 0.1 V. What is the effective resistance between drain and source at this operating point? Let and .
Vtn = 1 V kn ′ W L ⁄ ( ) 1 mA/V2 = ID RD VD 0.1 V VDD 5 V Figure 5.23 Circuit for Example 5.5.
Example 5.5 262 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Example 5.5 continued Solution Since the drain voltage is lower than the gate voltage by 4.9 V and the MOSFET is operating in the triode region. Thus the current ID is given by The required value for RD can be found as follows: In a practical discrete-circuit design problem, one selects the closest standard value available for, say, 5% resistors—in this case, 12 kΩ; see Appendix G. Since the transistor is operating in the triode region with a small VDS, the effective drain-to-source resistance can be determined as follows: Vtn 1 V, = ID = kn ′W L -----VGS Vtn – ( )VDS 1 2 ---VDS 2 – ID 1 5 1 – ( ) 0.1 1 2 ---0.01 × – × × = 0.395 mA = RD VDD VD – ID -----------------------= 5 0.1 – 0.395 ----------------12.4 kΩ = = rDS VDS ID ---------= 0.1 0.395 -------------253 Ω = = 5.11 If in the circuit of Example 5.5 the value of RD is doubled, find approximate values for ID and VD.
Ans. 0.2 mA; 0.05 V EXERCISE 5.3 MOSFET Circuits at DC 263 Analyze the circuit shown in Fig. 5.24(a) to determine the voltages at all nodes and the currents through all branches. Let and Neglect the channel-length modulation effect (i.e., assume Solution Since the gate current is zero, the voltage at the gate is simply determined by the voltage divider formed by the two 10-MΩ resistors, With this positive voltage at the gate, the NMOS transistor will be turned on. We do not know, however, whether the transistor will be operating in the saturation region or in the triode region. We shall assume saturation-region operation, solve the problem, and then check the validity of our assumption. Obviously, if our assumption turns out not to be valid, we will have to solve the problem again for triode-region operation.
Refer to Fig. 5.24(b). Since the voltage at the gate is 5 V and the voltage at the source is we have Thus, ID is given by which results in the following quadratic equation in ID: Figure 5.24 (a) Circuit for Example 5.6. (b) The circuit with some of the analysis details shown.
Vtn 1 V = kn ′ W L ⁄ ( ) 1 mA/V2.
= λ 0).
= (a) RS 6 k RG1 10 M RG2 10 M RD 6 k VDD 10 V (b) 10 V 10 M 5 V 0 0.5 μA ID 6 k 10 6 ID 6 ID 10 M 6 k ID VG VDD RG2 RG2 RG1 + ------------------------10 10 10 10 + ------------------× +5 V = = = ID mA ( ) 6 kΩ ( ) × 6ID, = VGS 5 6ID – = ID 1 2 ---kn ′ W L ----- VGS Vtn – ( )2 = 1 2 ---1 × 5 6ID – 1 – ( )2 × = 18ID 2 25ID 8 0 = + – Example 5.6 264 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Example 5.6 continued This equation yields two values for ID: 0.89 mA and 0.5 mA. The first value results in a source voltage of which is greater than the gate voltage and does not make physical sense as it would imply that the NMOS transistor is cut off. Thus, Since the transistor is operating in saturation, as initially assumed.
6 0.89 × 5.34 V, = ID 0.5 mA = VS 0.5 6 +3 V = × = VGS 5 3 – 2 V = = VD 10 6 0.5 × – +7 V = = VD VG Vtn, – > 5.12 For the circuit of Fig. 5.24, what is the largest value that RD can have while the transistor remains in the saturation mode?
Ans. 12 kΩ D5.13 Redesign the circuit of Fig. 5.24 for the following requirements: VS = 1.6 V, VD = 3.4 V, with a 1-μA current through the voltage divider RG1, RG2. Assume the same MOSFET as in Example 5.6.
Ans. RG1 = 1.6 MΩ; RG2 = 3.4 MΩ, RS = RD = 5 kΩ VDD +5 V, = ID 0.32 mA, = EXERCISES Design the circuit of Fig. 5.25 so that the transistor operates in saturation with and Let the enhancement-type PMOS transistor have and 1 mA/V2.
Assume λ = 0. What is the largest value that RD can have while maintaining saturation-region operation?
ID 0.5 mA = VD +3 V.
= Vtp 1 V – = kp ′ W L ⁄ ( ) = VDD 5 V RG1 RG2 RD VD 3 V ID 0.5 mA Figure 5.25 Circuit for Example 5.7.
Example 5.7 5.3 MOSFET Circuits at DC 265 D5.14 For the circuit in Fig. E5.14, find the value of R that results in the PMOS transistor operating with an overdrive voltage V. The threshold voltage is V, the process transcon-ductance parameter mA/V2, and W/L = 10 μm/0.18 μm.
Ans. 800 VOV 0.6 = Vtp 0.4 – = kp′ 0.1 = Ω 1.8 V R Figure E5.14 EXERCISE Solution Since the MOSFET is to be in saturation, we can write Substituting ID = 0.5 mA and we obtain and Since the source is at +5 V, the gate voltage must be set to +3 V. This can be achieved by the appropriate selection of the values of RG1 and RG2. A possible selection is RG1 = 2 MΩ and RG2 = 3 MΩ.
The value of RD can be found from Saturation-mode operation will be maintained up to the point that VD exceeds VG by that is, until This value of drain voltage is obtained with RD given by ID 1 2 --- kp ′W L ----- V OV 2 = kp ′W L ⁄ 1 mA/V2, = VOV 1 V = VSG Vtp VOV + 1 1 + 2 V = = = RD VD ID ------3 0.5 -------6 kΩ = = = Vtp ; VDmax 3 1 + 4 V = = RD 4 0.5 -------8 kΩ = = 266 Chapter 5 MOS Field-Effect Transistors (MOSFETs) The NMOS and PMOS transistors in the circuit of Fig. 5.26(a) are matched, with and Assuming for both devices, find the drain cur-rents iDN and iDP, as well as the voltage vO, for and Solution Figure 5.26(b) shows the circuit for the case We note that since QN and QP are perfectly matched and are operating at equal values of (2.5 V), the circuit is symmetrical, which dictates that Thus both QN and QP are operating with and, hence, in saturation. The drain cur-rents can now be found from Figure 5.26 Circuits for Example 5.8.
kn ′ Wn Ln ⁄ ( ) = kp ′ Wp Lp ⁄ ( ) 1 mA/V2 = Vtn Vtp – 1 V.
= = λ 0 = vI 0 V, = +2.5 V, 2.5 V.
– (a) vI vO iDP iDN QN 10 k QP 2.5 V 2.5 V (b) 0 V vO IDP IDN QN 10 k QP 2.5 V 2.5 V (c) 2.5 V vO QN 10 k IDN IDN 2.5 V (d) 2.5 V vO IDP IDP 10 k QP 2.5 V vI 0 V.
= VGS vO 0 V.
= VDG 0 = IDP IDN 1 2 ---1 2.5 1 – ( )2 × × 1.125 mA = = = Example 5.8 5.3 MOSFET Circuits at DC 267 Next, we consider the circuit with Transistor QP will have a VSG of zero and thus will be cut off, reducing the circuit to that shown in Fig. 5.26(c). We note that vO will be negative, and thus vGD will be greater than causing QN to operate in the triode region. For simplicity we shall assume that vDS is small and thus use IDN From the circuit diagram shown in Fig. 5.26(c), we can also write These two equations can be solved simultaneously to yield Note that which is small as assumed.
Finally, the situation for the case [Fig. 5.26(d)] will be the exact complement of the case Transistor QN will be off. Thus QP will be operating in the triode region with and vI +2.5 V.
= Vtn, kn ′ Wn Ln ⁄ ( ) VGS Vtn – ( )VDS 1 2.5 2.5 – ( ) 1 – – [ ] vO 2.5 – ( ) – [ ] = IDN mA ( ) 0 vO – 10 kΩ ( ) --------------------= IDN 0.244 mA = vO 2.44 V – = VDS −2.44 2.5 – ( ) – 0.06 V, = = vI 2.5 V – = vI +2.5 V: = IDN 0, = IDP 2.44 mA = vO +2.44 V.
= 5.15 The NMOS and PMOS transistors in the circuit of Fig. E5.15 are matched with and Assuming for both devices, find the drain currents iDN and iDP and the voltage vO for +2.5 V, and −2.5 V.
Ans. vI = 0 V: 0 mA, 0 mA, 0 V; vI = +2.5 V: 0.104 mA, 0 mA, 1.04 V; vI = −2.5 V: 0 mA, 0.104 mA, −1.04 V kn ′ Wn Ln ⁄ ( ) = kp ′ Wp Lp ⁄ ( ) 1 mA/V2 = Vtn V – tp 1 V.
= = λ 0 = vI 0 V, = vI vO iDN iDP QP 10 k QN 2.5 V 2.5 V Figure E5.15 EXERCISE 268 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.4 Applying the MOSFET in Amplifier Design We now begin our study of the utilization of the MOSFET in the design of amplifiers. The basis for this important application is that when operated in saturation, the MOSFET func-tions as voltage-controlled current source: The gate-to-source voltage controls the drain current . Although the control relationship is nonlinear (square law), we will shortly devise a method for obtaining almost-linear amplification from this fundamentally nonlinear device.
5.4.1 Obtaining a Voltage Amplifier In the introduction to amplifier circuits in Section 1.5, we learned that a voltage-controlled current source can serve as a transconductance amplifier; that is, an amplifier whose input signal is a voltage and whose output signal is a current. More commonly, however, one is interested in voltage amplifiers. A simple way to convert a transconductance amplifier to a voltage amplifier is to pass the output current through a resistor and take the voltage across the resistor as the output. Doing this for a MOSFET results in the simple amplifier circuit shown in Fig. 5.27(a). Here is the input voltage, (known as a load resistance) con-verts the drain current to a voltage ( ), and is the supply voltage that powers up the amplifier and, together with establishes operation in the saturation region, as will be shown shortly.
In the amplifier circuit of Fig. 5.27(a) the output voltage is taken between the drain and ground, rather than simply across . This is done because of the need to maintain a ground reference throughout the circuit. The output voltage is given by (5.30) Thus it is an inverted version (note the minus sign) of that is shifted by the constant value of the supply voltage .
5.4.2 The Voltage Transfer Characteristic (VTC) A very useful tool that yields great insight into the operation of an amplifier circuit is its voltage transfer characteristic (VTC). This is simply a plot (or a clearly labeled sketch) of the output voltage versus the input voltage. For the MOS amplifier in Fig. 5.27(a), this is the plot of versus shown in Fig. 5.27(b).
Observe that for , the transistor is cut off, and, from Eq. (5.30), . As exceeds , the transistor turns on and decreases. However, since ini-tially is still high, the MOSFET will be operating in saturation. This continues as is increased until the value of is reached that results in becoming lower than by volts (point B on the VTC in Fig. 5.27b). For greater than that at point B, the transistor operates in the triode region and decreases more slowly.
The VTC in Fig. 5.27(b) indicates that the segment of greatest slope (and hence poten-tially the largest amplifier gain) is that labeled AB, which corresponds to operation in the sat-uration region. An expression for the segment AB can be obtained by substituting for iD in Eq. (5.30) by its saturation-region value (5.31) vGS iD vGS RD iD iDRD VDD RD, RD vDS vDS VDD iDRD – = iDRD VDD vDS vGS vGS Vt < iD 0 = vDS VDD = vGS Vt vDS vDS vGS vGS vDS vGS Vt vGS vDS iD 1 2 ---kn vGS Vt – ( )2 = 5.4 Applying the MOSFET in Amplifier Design 269 where we have for simplicity neglected channel-length modulation. The result is (5.32) This is obviously a nonlinear relationship. Nevertheless, linear (or almost-linear) amplifica-tion can be obtained by using the technique of biasing the MOSFET. Before considering biasing, however, it is useful to determine the coordinates of point B, which is at the bound-ary between the saturation and the triode regions of operation. These can be obtained by substituting in Eq. (5.32), and . The result is (5.33) 5.4.3 Biasing the MOSFET to Obtain Linear Amplification Biasing enables us to obtain almost-linear amplification from the MOSFET. The technique is illustrated in Fig. 5.28(a). A dc voltage is selected to obtain operation at a point Q on the segment AB of the VTC. How to select an appropriate location for the bias point Q will be discussed shortly. For the time being, observe that the coordinates of Q are the dc VDD RD iD vO = vDS vGS – + (a) Vt 0 VGS B VGS B–Vt VDS B vDS VDD VDD vGS Saturation B (b) A C Cut-off Triode Figure 5.27 (a) Simple MOSFET amplifier with input vGS and output vDS. (b) The voltage transfer char-acteristic (VTC) of the amplifier in (a). The three segments of the VTC correspond to the three regions of operation of the MOSFET.
vDS VDD 1 2 ---knRD vGS Vt – ( )2 – = vGS VGS B = vDS VDS B VGS B Vt – = = VGS B Vt 2knRDVDD 1 + 1 – knRD ------------------------------------------------+ = 5.16 Consider the amplifier of Fig. 5.27(a) with V, k , and with a MOSFET specified to have V, mA/V2, and . Determine the coordinates of the end points of the saturation-region segment of the VTC. Also, determine assuming .
Ans. A: 0.4 V, 1.8 V; B: 0.613 V, 0.213 V; mV VDD 1.8 = RD 17.5 = Ω Vt 0.4 = kn 4 = λ 0 = VDS C VGS C VDD = VDS C 18 = EXERCISE VGS 270 Chapter 5 MOS Field-Effect Transistors (MOSFETs) voltages and , which are related by (5.34) Point Q is known as the bias point or the dc operating point. Also, since at Q no signal com-ponent is present, it is also known as the quiescent point (which is the origin of the symbol Q).
Next, the signal to be amplified, , a function of time , is superimposed on the bias voltage , as shown in Fig. 5.29(a). Thus the total instantaneous value of becomes The resulting can be obtained by substituting for into Eq. (5.32). Graphically, we can use the VTC to obtain point-by-point, as illustrated in Fig. 5.29(b). Here we show the case of being a triangular wave of “small” amplitude. Specifically, the ampli-tude of is small enough to restrict the excursion of the instantaneous operating point to a short, almost-linear segment of the VTC around the bias point Q. The shorter the segment, the greater the linearity achieved, and the closer to an ideal triangular wave the signal com-ponent at the output, , will be. This is the essence of obtaining linear amplification from the nonlinear MOSFET. 5.4.4 The Small-Signal Voltage Gain If the input signal is kept small, the corresponding signal at the output will be nearly proportional to with the constant of proportionality being the slope of the almost-linear segment of the VTC around Q. This is the voltage gain of the amplifier, and its value can be determined by evaluating the slope of the tangent to the VTC at the bias point Q, (5.35) Utilizing Eq. (5.32) we obtain (5.36) which can be expressed in terms of the overdrive voltage at the bias point as (5.37) V GS V DS VDS VDD 1 2 ---knRD VGS Vt – ( )2 – = vgs t VGS vGS vGS t ( ) VGS vgs t ( ) + = vDS t ( ) vGS t ( ) vDS t ( ) vgs vgs vds C Vt 0 VGS VDS vDS VDD vGS VDD VDD RD ID VDS VGS – – + + B Q (b) (a) A Figure 5.28 Biasing the MOSFET amplifier at a point Q located on the segment AB of the VTC.
vgs vds vgs Av dvDS dvGS -----------vGS VGS = ≡ Av kn VGS Vt – ( )RD – = VOV Av knVOVRD – = 5.4 Applying the MOSFET in Amplifier Design 271 (b) vGS vDS V DD V GS V DS V DD V t A Q B C Slope at Q 5 voltage gain Time Time vds vgs Figure 5.29 The MOSFET amplifier with a small time-varying signal vgs(t) superimposed on the dc bias voltage VGS.
The MOSFET operates on a short almost-linear segment of the VTC around the bias point Q and provides an output volt-age vds = Av vgs.
iD vDS RD VDD vgs vGS VGS (a) 272 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Consider the amplifier circuit shown in Fig. 5.29(a). The transistor is specified to have V, mA/V2, W/L = 10, and . Also, let V, k , and V.
(a) For (and hence ), find , , , and .
(b) What is the maximum symmetrical signal swing allowed at the drain? Hence find the maximum allowable amplitude of a sinusoidal .
Solution (a) With V, V. Thus, mA V Vt 0.4 = kn ′ 0.4 = λ 0 = VDD 1.8 = RD 17.5 = Ω VGS 0.6 = vgs 0 = vds 0 = VOV ID VDS Av vgs VGS 0.6 = VOV 0.6 0.4 – 0.2 = = ID 1 2 ---0.4 10 0.22 × × × 0.08 = = VDS VDD RDID – = 1.8 17.5 0.08 × – = 0.4 = Example 5.9 We make the following observations on this expression for the voltage gain.
1. The gain is negative, which signifies that the amplifier is inverting; that is, there is a 180 phase shift between the input and the output. This inversion is obvious in Fig.
5.29(b) and should have been anticipated from Eq. (5.32). 2. The gain is proportional to the load resistance , to the transistor transconduc-tance parameter , and to the overdrive voltage . This all makes intuitive sense.
Another simple and insightful expression for the voltage gain can be derived by recalling that the dc current in the drain at the bias point is related to by This equation can be combined with Eq. (5.37) to yield (5.38) That is, the gain is simply the ratio of the dc voltage drop across the load resistance to . This relationship allows one to find an absolute upper limit on the magnitude of voltage gain achievable from this amplifier circuit. Simply note that can approach but never exceed the power-supply voltage ; thus, For modern CMOS technologies is usually no lower than about 0.2 V, with the result that the maximum achievable gain is about 10 . Thus for a 0.13-μm CMOS technology that utilizes V, the approximate value of is 13 V/V. In actual circuits, how-ever, the maximum gain achievable is lower than this absolute maximum.
° RD kn VOV Av V OV ID 1 2 ---knVOV 2 = Av IDRD VOV 2 ⁄ ----------------– = RD VOV 2 ⁄ IDRD VDD Avmax VDD VOV 2 ⁄ ----------------= VOV VDD VDD 1.3 = Amax 5.4 Applying the MOSFET in Amplifier Design 273 Since is greater than , the transistor is indeed operating in saturation. The voltage gain can be found from Eq. (5.37), V/V An identical result can be found using Eq. (5.38).
(b) Since V and V, we see that the maximum allowable negative signal swing at the drain is 0.2 V. In the positive direction, a swing of V would not cause the transistor to cut off and thus is allowed. Thus the maximum symmetrical signal swing allowable at the drain is V. The corre-sponding amplitude of can be found from mV Since , the operation will be reasonably linear (more on this in later sections).
Greater insight into the issue of allowable signal swing can be obtained by examining the signal waveforms shown in Fig. 5.30. Note that for the MOSFET to remain in saturation at the negative peak of , we must ensure that that is, which results in mV This is a more precise result than the one obtained earlier.
VDS VOV Av knVOVRD – = 0.4 10 0.2 17.5 × × × – = 14 – = VOV 0.2 = VDS 0.4 = +0.2 0.2 ± vgs v ˆ gs v ˆ ds Av --------0.2 V 14 -------------14.2 = = = v ˆ gs VOV vds vDSmin vGSmax Vt – ≥ 0.4 Av v ˆ gs 0.6 v ˆ gs 0.4 – + ≥ – v ˆ gs 0.2 Av 1 + ------------------≤ 13.3 = t Vt VGS t VDS 0 vGS vgs 0 vDS vDSmin = VDS v ˆds vGSmax = VGS v ˆgs vds Figure 5.30 Signal waveforms at gate and drain for the amplifier in Example 5.9. Note that to ensure operation in the saturation region at all times, vDSmin vGSmax – Vt .
274 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.4.5 Determining the VTC by Graphical Analysis Figure 5.31 shows a graphical method for determining the VTC of the amplifier of Fig.
5.29(a). Although graphical analysis of transistor circuits is rarely employed in practice, it is useful for us at this stage for gaining greater insight into circuit operation, especially in answering the question of where to locate the bias point Q.
The graphical analysis is based on the observation that for each value of , the circuit will be operating at the point of intersection of the graph corresponding to the partic-ular value of and the straight line representing Eq. (5.30), which can be rewritten in the form (5.39) Figure 5.31 Graphical construction to determine the voltage transfer characteristic of the amplifier in Fig. 5.29(a).
vGS iD vDS – vGS iD VDD RD ----------1 RD ------vDS – = vDS 0 iD ID V DD V DS V DS B V GS B V t V DS C C B Q A Load-line slope 1RD vGS VDD vGS ...
vGS VGS B vGS ...
vGS VGS vGS … Triode Saturation 5.17 For the amplifier circuit studied in Example 5.9, provide two alternative designs, each providing a voltage gain of 10 by (a) changing while keeping constant, and (b) changing while keeping constant. For each design, specify , , , and .
Ans. (a) 0.6 V, 0.08 mA, 12.5 k , 0.8 V; (b) 0.54 V, 0.04 mA, 17.5 k , 1.1 V RD VOV VOV RD VGS ID RD VDS Ω Ω EXERCISE 5.4 Applying the MOSFET in Amplifier Design 275 The straight line representing this relationship is superimposed on the characteristics in Fig. 5.31. It intersects the horizontal axis at and has a slope of Since this straight line represents in effect the load resistance , it is called the load line. The VTC is then determined point by point. Note that we have labeled four important points: point A at which , point Q at which the MOSFET can be biased for amplifier operation ( and ), point B at which the MOSFET leaves saturation and enters the triode region, and point C, which is deep into the triode region and for which . If the MOSFET is to be used as a switch, then operating points A and C are applicable: At A the transistor is off (open switch), and at C the transistor operates as a low-valued resistance and has a small voltage drop (closed switch). The incremental resistance at point C is also known as the closure resistance. The operation of the MOSFET as a switch is illustrated in Fig. 5.32. A detailed study of the application of the MOSFET as a switch is undertaken in Chapter 13 dealing with CMOS digital logic circuits.
5.4.6 Locating the Bias Point Q The bias point Q is determined by the value of and that of the load resistance . Two important considerations in deciding on the location of Q are the required gain and the allowable signal swing at the output. To illustrate, consider the VTC shown in Fig. 5.29(b).
Here the value of is fixed and the only variable remaining is the value of . Since the slope increases as we move closer to point B, we obtain higher gain by locating Q as close to B as possible. However, the closer Q is to the boundary point B, the smaller the allowable magnitude of negative signal swing. Thus, as often happens in engineering design, we encounter a situation requiring a trade-off.
In deciding on a value for , it is useful to refer to the plane. Figure 5.33 shows two load lines resulting in two extreme bias points: Point is too close to , resulting in a severe constraint on the positive signal swing of Exceeding the allowable positive maxi-mum results in the positive peaks of the signal being clipped off, since the MOSFET will turn off for the part of each cycle near the positive peak. We speak of this situation by saying that the circuit does not have sufficient “headroom.” Similarly, point is too close to the bound-ary of the triode region, thus severely limiting the allowable negative signal swing of Exceeding this limit would result in the transistor entering the triode region for part of each cycle near the negative peaks, resulting in a distorted output signal. In this situation we say that the circuit does not have sufficient “legroom.” We will have more to say on bias design in the Section 5.7. Figure 5.32 Operation of the MOSFET in Figure 5.29(a) as a switch: (a) Open, corre-sponding to point A in Figure 5.31; (b) Closed, corresponding to point C in Figure 5.31. The closure resistance is approximately equal to rDS because VDS is usually very small.
VDD RD (a) (b) 0 vDS = VDD vGS ≤ Vt rDS VDD RD vGS = VDD vDS = VDS C iD vDS – vDS VDD = 1 RD ⁄ .
– RD vGS Vt = vGS VGS = vDS VDS = vGS VDD = rDS VGS RD RD VGS RD iD vDS – Q1 VDD vds.
Q2 vds.
276 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.5 Small-Signal Operation and Models In our study of the operation of the MOSFET amplifier in Section 5.4 we learned that linear amplification can be obtained by biasing the MOSFET to operate in the saturation region and by keeping the input signal small. In this section, we explore the small-signal operation in some detail. For this purpose we utilize the conceptual amplifier circuit shown in Fig. 5.34. Here the MOS transistor is biased by applying a dc voltage8 VGS, and the input sig-nal to be amplified, vgs, is superimposed on the dc bias voltage VGS. The output voltage is taken at the drain. 5.5.1 The DC Bias Point The dc bias current ID can be found by setting the signal vgs to zero; thus, (5.40) where we have neglected channel-length modulation (i.e., we have assumed λ = 0). Here is the overdrive voltage at which the MOSFET is biased to operate. The dc Figure 5.33 Two load lines and corresponding bias points. Bias point Q1 does not leave sufficient room for positive signal swing at the drain (too close to VDD). Bias point Q2 is too close to the boundary of the tri-ode region and might not allow for sufficient negative signal swing.
8Practical biasing arrangments will be studied in Section 5.7.
V DD Q1 vGS ...
vDS iD Q2 0 ID = 1 2 ---kn VGS Vt – ( ) 2 = 1 2 ---knVOV 2 VOV VGS Vt – = 5.5 Small-Signal Operation and Models 277 voltage at the drain, VDS, will be (5.41) To ensure saturation-region operation, we must have Furthermore, since the total voltage at the drain will have a signal component superimposed on VDS, VDS has to be sufficiently greater than to allow for the required signal swing.
5.5.2 The Signal Current in the Drain Terminal Next, consider the situation with the input signal vgs applied. The total instantaneous gate-to-source voltage will be (5.42) resulting in a total instantaneous drain current iD, (5.43) The first term on the right-hand side of Eq. (5.43) can be recognized as the dc bias current ID (Eq.
5.40). The second term represents a current component that is directly proportional to the input signal vgs. The third term is a current component that is proportional to the square of the input sig-nal. This last component is undesirable because it represents nonlinear distortion. To reduce the nonlinear distortion introduced by the MOSFET, the input signal should be kept small so that iD vDS RD VDD vgs vGS VGS Figure 5.34 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal amplifier.
VDS VDD RDID – = VDS VOV > VOV ( ) vGS VGS vgs + = iD = 1 2 --- kn VGS vgs Vt – + ( ) 2 = 1 2 ---kn VGS Vt – ( ) 2 + kn VGS Vt – ( )vgs 1 2 ---kn vgs 2 + 1 2 ---kn vgs 2 kn VGS Vt – ( )vgs 278 Chapter 5 MOS Field-Effect Transistors (MOSFETs) resulting in (5.44) or, equivalently, (5.45) If this small-signal condition is satisfied, we may neglect the last term in Eq. (5.43) and express iD as (5.46) where The parameter that relates id and vgs is the MOSFET transconductance gm, (5.47) or in terms of the overdrive voltage VOV, (5.48) Figure 5.35 presents a graphical interpretation of the small-signal operation of the MOSFET amplifier. Note that gm is equal to the slope of the iD −vGS characteristic at the bias point, (5.49) Figure 5.35 Small-signal operation of the MOSFET amplifier.
vgs 2 VGS Vt – ( ) vgs 2VOV iD · ID id + id = kn VGS Vt – ( )vgs gm id vgs ------ = kn VGS Vt – ( ) ≡ gm = knVOV gm ∂iD ∂vGS -----------vGS = VGS ≡ V OV 0 Q VGS 5.5 Small-Signal Operation and Models 279 This is the formal definition of gm, which can be shown to yield the expressions given in Eqs. (5.47) and (5.48).
5.5.3 The Voltage Gain Returning to the circuit of Fig. 5.34, we can express the total instantaneous drain voltage vDS as follows: Under the small-signal condition, we have which can be rewritten as Thus the signal component of the drain voltage is (5.50) which indicates that the voltage gain is given by (5.51) The minus sign in Eq. (5.51) indicates that the output signal vds is 180° out of phase with respect to the input signal vgs. This is illustrated in Fig. 5.36, which shows vGS and vDS. The input signal is assumed to have a triangular waveform with an amplitude much smaller than 2(VGS – Vt), the small-signal condition in Eq. (5.44), to ensure linear operation. For operation in the saturation region at all times, the minimum value of vDS should not fall below the corre-sponding value of vGS by more than Vt. Also, the maximum value of vDS should be smaller than VDD; otherwise the FET will enter the cutoff region and the peaks of the output signal wave-form will be clipped off.
Finally, we note that by substituting for gm from Eq. (5.48) the voltage gain expression in Eq. (5.51) becomes identical to that derived in Section 5.4—namely, Eq. (5.37).
5.5.4 Separating the DC Analysis and the Signal Analysis From the preceding analysis, we see that under the small-signal approximation, signal quan-tities are superimposed on dc quantities. For instance, the total drain current iD equals the dc current ID plus the signal current id, the total drain voltage vDS = VDS + vds, and so on. It follows that the analysis and design can be greatly simplified by separating dc or bias calcu-lations from small-signal calculations. That is, once a stable dc operating point has been established and all dc quantities calculated, we may then perform signal analysis ignoring dc quantities.
vDS VDD RDiD – = vDS VDD RD ID id + ( ) – = vDS VDS RDid – = vds idRD g – mvgsRD = – = Av vds vgs ------gmRD – = ≡ 280 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.5.5 Small-Signal Equivalent-Circuit Models From a signal point of view, the FET behaves as a voltage-controlled current source. It accepts a signal vgs between gate and source and provides a current gmvgs at the drain terminal.
The input resistance of this controlled source is very high—ideally, infinite. The output resistance—that is, the resistance looking into the drain—also is high, and we have assumed it to be infinite thus far. Putting all of this together, we arrive at the circuit in Fig. 5.37(a), which represents the small-signal operation of the MOSFET and is thus a small-signal model or a small-signal equivalent circuit.
In the analysis of a MOSFET amplifier circuit, the transistor can be replaced by the equivalent circuit model shown in Fig. 5.37(a). The rest of the circuit remains unchanged except that ideal constant dc voltage sources are replaced by short circuits. This is a result of the fact that the voltage across an ideal constant dc voltage source does not change, and thus there will always be a zero voltage signal across a constant dc voltage source. A dual statement applies for constant dc current sources; namely, the signal current of an ideal con-stant dc current source will always be zero, and thus an ideal constant dc current source can be replaced by an open circuit in the small-signal equivalent circuit of the amplifier. The Figure 5.36 Total instantaneous voltages vGS and vDS for the circuit in Fig. 5.34.
vGS (gmRD) V 0 vDSmax VDS min vGSmax Vt vDS 0 vGS VGS V t t (V GS Vt) V 2 2 VDD vDS 5.5 Small-Signal Operation and Models 281 circuit resulting can then be used to perform any required signal analysis, such as calculating voltage gain.
The most serious shortcoming of the small-signal model of Fig. 5.37(a) is that it assumes the drain current in saturation to be independent of the drain voltage. From our study of the MOSFET characteristics in saturation, we know that the drain current does in fact depend on vDS in a linear manner. Such dependence was modeled by a finite resistance ro between drain and source, whose value was given by Eq. (5.27) in Section 5.2.4, which we repeat here as (5.52) where is a MOSFET parameter that either is specified or can be measured. It should be recalled that for a given process technology, VA is proportional to the MOSFET channel length. The current ID is the value of the dc drain current without the channel-length modulation taken into account; that is, (5.53) Typically, ro is in the range of 10 kΩ to 1000 kΩ. It follows that the accuracy of the small-signal model can be improved by including ro in parallel with the controlled source, as shown in Fig. 5.37(b).
It is important to note that the small-signal model parameters gm and ro depend on the dc bias point of the MOSFET.
Returning to the amplifier of Fig. 5.34, we find that replacing the MOSFET with the small-signal model of Fig. 5.37(b) results in the voltage-gain expression (5.54) Thus, the finite output resistance ro results in a reduction in the magnitude of the voltage gain.
Although the analysis above is performed on an NMOS transistor, the results, and the equivalent circuit models of Fig. 5.37, apply equally well to PMOS devices, except for using and and replacing with Figure 5.37 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in satura-tion (the channel-length modulation effect); and (b) including the effect of channel-length modulation, mod-eled by output resistance (a) G D S vgs gm vgs (b) G D S ro vgs vgs gm ro VA ID ⁄ .
= ro VA ID ---------= VA 1/λ = ID = 1 2 --- kn VOV 2 Av vds vgs ------gm RD ||ro ( ) – = = VGS , Vt , VOV , VA kn kp.
282 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.5.6 The Transconductance gm We shall now take a closer look at the MOSFET transconductance given by Eq. (5.47), which we rewrite with (W/L) as follows: (5.55) This relationship indicates that gm is proportional to the process transconductance parameter and to the W/L ratio of the MOS transistor; hence to obtain relatively large trans-conductance the device must be short and wide. We also observe that for a given device the transconductance is proportional to the overdrive voltage, , the amount by which the bias voltage VGS exceeds the threshold voltage Vt. Note, however, that increas-ing gm by biasing the device at a larger VGS has the disadvantage of reducing the allowable voltage signal swing at the drain.
Another useful expression for gm can be obtained by substituting for VOV in Eq. (5.55) by [from Eq. (5.40)]: (5.56) This expression shows two things: 1. For a given MOSFET, gm is proportional to the square root of the dc bias current.
2. At a given bias current, gm is proportional to .
In contrast, the transconductance of the bipolar junction transistor (BJT) studied in Chapter 6 is proportional to the bias current and is independent of the physical size and geometry of the device.
To gain some insight into the values of gm obtained in MOSFETs consider an inte-grated-circuit device operating at ID = 0.5 mA and having . Equation (5.56) shows that for W/L = 1, gm = 0.35 mA/V, whereas a device for which W/L = 100 has gm = 3.5 mA/V. In contrast, a BJT operating at a collector current of 0.5 mA has gm = 20 mA/V.
Yet another useful expression for gm of the MOSFET can be obtained by substituting for (W/L) in Eq. (5.55) by 2ID/(VGS − Vt)2: (5.57) A convenient graphical construction that clearly illustrates this relationship is shown in Fig. 5.38.
In summary, there are three different relationships for determining gm—Eqs. (5.55), (5.56), and (5.57)—and there are three design parameters—(W/L), VOV, and ID, any two of which can be chosen independently. That is, the designer may choose to operate the MOSFET with a certain overdrive voltage VOV and at a particular current ID; the required W/L ratio can then be found and the resulting gm determined.
kn kn ′ = gm = kn ′ W L ⁄ ( ) VGS Vt – ( ) = kn ′ W L ⁄ ( )VOV kn ′ = μnCox VOV VGS Vt – = 2ID (kn ′ W L ⁄ ( )) ⁄ gm 2kn ′ W L ⁄ = ID W L ⁄ kn ′ = 120 μA/V2 kn ′ gm 2ID VGS Vt – ---------------------2ID VOV ---------= = 5.5 Small-Signal Operation and Models 283 Figure 5.38 The slope of the tangent at the bias point Q intersects the vOV axis at VOV. Thus, gm=ID/( VOV).
Slope ID VOV Q 0 iD vOV ID gm = VOV 1 2 VOV 1 2 1 2 ---1 2 ---Figure 5.39(a) shows a discrete common-source MOSFET amplifier utilizing a drain-to-gate resistance RG for biasing purposes. Such a biasing arrangement will be studied in Section 5.7. The input signal vi is coupled to the gate via a large capacitor, and the output signal at the drain is coupled to the load resistance RL via another large capacitor. We wish to analyze this amplifier circuit to determine its small-signal volt-age gain, its input resistance, and the largest allowable input signal. The transistor has Vt = 1.5 V, (W/L) = 0.25 mA/V2, and VA = 50 V. Assume the coupling capacitors to be sufficiently large so as to act as short circuits at the signal frequencies of interest.
kn ′ (a) VDD = Example 5.10 284 Chapter 5 MOS Field-Effect Transistors (MOSFETs) RD VDS VGS ID RG IG = 0 VDD (b) ID (ii−gmvgs) gmvgs (d) vi RG Rin= R L=RL || RD || ro R L ii vi ii vgs=vi vo (c) Figure 5.39 Example 5.10: (a) amplifier circuit; (b) circuit for determining the dc operating point; (c) the amplifier small-signal equivalent circuit; (d) a simplified version of the circuit in (c).
Example 5.10 continued 5.5 Small-Signal Operation and Models 285 Solution We first determine the dc operating point. For this purpose, we eliminate the input signal , and open-circuit the two coupling capacitors (since they block dc currents). The result is the circuit shown in Fig.
5.39(b). We note that since , the dc voltage drop across will be zero, and (5.58) With , the NMOS transistor will be operating in saturation. Thus, (5.59) where, for simplicity, we have neglected the effect of channel-length modulation on the dc operating point. Substituting V, k , mA/V2, and V in Eqs. (5.58) and (5.59), and substituting for from Eq. (5.58) into Eq. (5.59) results in a quadratic equation in . Solv-ing the latter and discarding the root that is not physically meaningful yields the solution mA which corresponds to V and V Next we proceed with the small-signal analysis of the amplifier. Toward that end we replace the MOSFET with its small-signal model to obtain the small-signal equivalent circuit of the amplifier, shown in Fig. 5.39(c). Observe that we have replaced the coupling capacitors with short circuits. The dc voltage supply has also been replaced with a short circuit to ground.
The values of the transistor small-signal parameters and can be determined by using the dc bias quantities found above, as follows: mA/V k Next we use the equivalent circuit of Fig. 5.39(c) to determine the input resistance and the voltage gain Toward that end we simplify the circuit by combining the three parallel resis-tances , , and in a single resistance , k as shown in Fig. 5.39(d). For the latter circuit we can write the two equations (5.60) vi IG 0 = RG VGS VDS VDD RDID – = = VDS VGS = ID 1 2 ---kn VGS Vt – ( )2 = VDD 15 = RD 10 = Ω kn 0.25 = Vt 1.5 = VGS ID ID 1.06 = VGS VDS 4.4 = = VOV 4.4 1.5 2.9 = – = VDD gm ro gm knVOV = 0.25 2.9 0.725 = × = ro VA ID ------= 50 1.06 ----------47 = = Ω Rin vi ii ⁄ ≡ Av vo vi ⁄ .
= ro RD RL R′ L R′ L RL RD ro = 10 10 47 4.52 = = Ω vo ii gmvgs – ( )R′ L = 286 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Example 5.10 continued and (5.61) Substituting for from Eq. (5.61) into Eq. (5.60) results in the following expression for the voltage gain : Since is very large, and (the reader can easily verify this), and the gain expression can be approximated as Av (5.62) Substituting, mA/V and k yields V/V To obtain the input resistance, we substitute in Eq. (5.61) for , then use to obtain (5.63) This is an interesting relationship: The input resistance decreases as the gain is increased. The value of can now be determined; it is which is still very large.
The largest allowable input signal is constrained by the need to keep the transistor in saturation at all times; that is, Enforcing this condition with equality at the point is maximum and is minimum, we write Since , we obtain This is a general relationship that applies to this circuit irrespective of the component values. Observe that it simply states that the maximum signal swing is determined by the fact that the bias arrangement makes and thus, to keep the MOSFET out of the triode region, the signal between D and G is con-strained to be equal to . For our particular design, V A modification of this circuit that increases the allowable signal swing is investigated in Problem 5.80.
ii vgs vo – RG -----------------= ii Av vo vi ⁄ vo vgs ⁄ = ≡ Av gmR′ L – = 1 1 gmRG ⁄ ( ) – 1 R′ L RG ⁄ ( ) + -------------------------------RG gmRG 1 R′ L RG ⁄ 1 gmR′ L – gm 0.725 = R′ L 4.52 = Ω Av 3.3 – = vo Avvgs g – mR′ Lvgs = = Rin vi ii ⁄ ≡ vgs ii ⁄ = Rin RG 1 gmR′ L + ---------------------= gmR′ L ( ) Rin Rin 10 MΩ 1 3.3 + ------------------2.33 MΩ = = v ˆ i vDS vGS Vt – ≥ vGS vDS vDSmin vGSmax Vt – = VDS Av v ˆ i VGS v ˆ i Vt – + = – VDS VGS = v ˆ i Vt Av 1 + ------------------= VD VG = Vt v ˆ i 1.5 3.3 1 + ----------------= 0.35 = 5.5 Small-Signal Operation and Models 287 5.5.7 The T Equivalent-Circuit Model Through a simple circuit transformation it is possible to develop an alternative equiva-lent-circuit model for the MOSFET. The development of such a model, known as the T model, is illustrated in Fig. 5.40. Figure 5.40(a) shows the equivalent circuit studied Figure 5.40 Development of the T equivalent-circuit model for the MOSFET. For simplicity, ro has been omitted; however, it may be added between D and S in the T model of (d).
D5.18 Consider the amplifier circuit of Fig. 5.39(a) without the load resistance and with channel length modulation neglected. Let V, V, and mA/V2. Find , , and to obtain a voltage gain of 25 V/V and an input resistance of 0.5 M . What is the maxi-mum allowable input signal, ?
Ans. 0.319 V; 50.7 μA; 78.5 k ; 13 M ; 27 mV RL VDD 5 = Vt 0.7 = kn 1 = VOV ID, RD RG Ω v ˆ i Ω Ω EXERCISE G D S (a) (b) (c) (d) is ig 0 id vgs gmvgs G D S is ig 0 id vgs gmvgs gmvgs X G D S is ig 0 id vgs gmvgs gmvgs X G D S is id vgs gmvgs 1/gm ig 0 288 Chapter 5 MOS Field-Effect Transistors (MOSFETs) above without ro. In Fig. 5.40(b) we have added a second gmvgs current source in series with the original controlled source. This addition obviously does not change the termi-nal currents and is thus allowed. The newly created circuit node, labeled X, is joined to the gate terminal G in Fig. 5.40(c). Observe that the gate current does not change—that is, it remains equal to zero—and thus this connection does not alter the terminal charac-teristics. We now note that we have a controlled current source gmvgs connected across its control voltage vgs. We can replace this controlled source by a resistance as long as this resistance draws an equal current as the source. (See the source-absorption theorem in Appendix D.) Thus the value of the resistance is = . This replacement is shown in Fig. 5.40(d), which depicts the alternative model. Observe that ig is still zero, and , all the same as in the original model in Fig. 5.40(a).
The model of Fig. 5.40(d) shows that the resistance between gate and source look-ing into the source is This observation and the T model prove useful in many applications. Note that the resistance between gate and source, looking into the gate, is infinite.
In developing the T model we did not include ro. If desired, this can be done by incor-porating in the circuit of Fig. 5.40(d) a resistance ro between drain and source, as shown in Fig. 5.41(a). An alternative representation of the T model, in which the voltage-controlled current source is replaced with a current-controlled current source, is shown in Fig. 5.41(b).
Finally, we should note that in order to distinguish the model of Fig. 5.37(b) from the equivalent T model, the former is sometimes referred to as the hybrid-π model, a carryover from the bipolar transistor literature. The origin of this name will be explained in the next chapter.
vgs gmvgs ⁄ 1 gm ⁄ id gmvgs, = is vgs 1 gm ⁄ ( ) ⁄ gmvgs = = 1 gm ⁄ .
Figure 5.42(a) shows a MOSFET amplifier biased by a constant-current source I. Assume that the values of I and are such that the MOSFET operates in the saturation region. The input signal is coupled to RD vi Example 5.11 ro g G S D m 1/gm vgs vgs (a) ro 1 i G S D i (b) 1/gm Figure 5.41 (a) The T model of the MOSFET augmented with the drain-to-source resistance ro. (b) An alternative representation of the T model.
5.5 Small-Signal Operation and Models 289 the source terminal by utilizing a large capacitor . Similarly, the output signal at the drain is taken through a large coupling capacitor . Find the input resistance and the voltage gain . Neglect channel-length modulation.
Solution Replacing the MOSFET with its T equivalent-circuit model results in the amplifier equivalent circuit shown in Fig. 5.42(b). Observe that the dc current source I is replaced with an open circuit and the dc voltage source is replaced by a short circuit. The large coupling capacitors have been replaced by short circuits. From the equivalent circuit-model we determine and Thus, We note that this amplifier, known as the common-gate amplifier because the gate at ground potential is common to both the input and output ports, has a low input resistance and a noninverting gain.
We shall study this amplifier type in Section 5.6.5.
CC1 CC2 Rin vo vi ⁄ RD CC2 CC1 VDD I −VSS vo vi vi RD G 1i D vo Rin Rin gm 1 i S (a) (b) Figure 5.42 (a) Amplifier circuit for Example 5.11; (b) Small-signal equivalent circuit of the amplifier in (a).
VDD Rin vi i – ----1 gm ⁄ = = vo iRD – vi 1 gm ⁄ -------------⎝ ⎠ ⎛ ⎞RD gmRDvi = = = Av vo vi ----≡ gmRD = 1 gm ⁄ ( ) 5.19 Use the T model of Fig. 5.41(b) to show that a MOSFET whose drain is connected to its gate exhib-its an incremental resistance equal to .
Ans. See Fig. E5.19.
1 gm ⁄ ( ) ro || [ ] EXERCISE 290 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.5.8 Summary We conclude this section by presenting in Table 5.3 a summary of the formulas for calculating the values of the small-signal MOSFET parameters. Observe that for gm we have three different formulas, each providing the circuit designer with insight regarding design choices. We shall make frequent comments on these in later sections and chapters.
Table 5.3 Small-Signal Equivalent-Circuit Models for the MOSFET Small-Signal Parameters NMOS transistors Transconductance: Output resistance: PMOS transistors Same formulas as for NMOS except using |VOV|, |VA|, and replacing μn with μp.
Small-Signal Equivalent Circuit Models Q ro r ( ro 0 i i gm 1 gm 1 (a) (b) )|| Figure E5.19 Circuits for Exercise 5.19. Note that the bias arrangement of Q is not shown.
gm μnCoxW L -----VOV 2μnCoxW L -----ID 2ID VOV ---------= = = ro VA ID ⁄ 1 λID ⁄ = = vgs ro S G D gmvgs ro G D gmvgs 1 gm S vgs ro G D i 1 gm S i Hybrid-π model T models 5.6 Basic MOSFET Amplifier Configurations 291 5.6 Basic MOSFET Amplifier Configurations It is useful at this point to take stock of where we are and where we are going in our study of MOSFET amplifiers. In Section 5.4 we examined the essence of the use of the MOS-FET as an amplifier. There we found that almost-linear amplification can be obtained by biasing the MOSFET at an appropriate point in its saturation region of operation and by keeping the signal small. We then took a closer look at the small-signal operation of the MOSFET in Section 5.5 and developed circuit models to represent the transistor, thus facilitating the determination of amplifier parameters such as voltage gain and input and output resistances. 5.20 For the amplifier in Fig. 5.34, let VDD = 5 V, RD = 10 kΩ, Vt = 1 V, μA/V2, W/L = 20, VGS = 2 V, and λ = 0. (a) Find the dc current ID and the dc voltage VDS. (b) Find gm. (c) Find the voltage gain. (d) If vgs = 0.2 sin ωt volts, find vds assuming that the small-signal approximation holds. What are the minimum and maximum values of vDS? (e) Use Eq. (5.43) to determine the various components of iD. Using the identity (sin2ωt = cos 2ωt), show that there is a slight shift in ID (by how much?) and that there is a second-harmonic com-ponent (i.e., a component with frequency 2ω). Express the amplitude of the second-harmonic com-ponent as a percentage of the amplitude of the fundamental. (This value is known as the second-harmonic distortion.) Ans. (a) 200 μA, 3 V; (b) 0.4 mA/V; (c) −4 V/V; (d) vds = −0.8 sinωt volts, 2.2 V, 3.8 V; (e) iD = (204 + 80 sinωt − 4 cos 2ωt) μA, 5% 5.21 An NMOS transistor has μnCox = 60 μA/V2, W/L = 40, Vt = 1 V, and VA = 15 V. Find gm and ro when (a) the bias voltage VGS = 1.5 V, (b) the bias current ID = 0.5 mA.
Ans. (a) 1.2 mA/V, 50 kΩ; (b) 1.55 mA/V, 30 kΩ 5.22 A MOSFET is to operate at ID = 0.1 mA and is to have gm = 1 mA/V. If = 50 μA/V2, find the required W/L ratio and the overdrive voltage.
Ans. 100; 0.2 V 5.23 For a fabrication process for which μp 0.4μn, find the ratio of the width of a PMOS transistor to the width of an NMOS transistor so that the two devices have equal gm for the same bias conditions.
The two devices have equal channel lengths.
Ans. 2.5 5.24 A PMOS transistor has Vt = −1 V, = 60 μA/V2, and W/L = 16 μm. Find ID and gm when the device is biased at VGS = −1.6 V. Also, find the value of ro if λ (at L = 1 μm) = −0.04 V−1.
Ans. 216 μA; 0.72 mA/V; 92.6 kΩ 5.25 Use the formulas in Table 5.3 to derive an expression for (gmro) in terms of VA and VOV. As we shall see in Chapter 7, this is an important transistor parameter and is known as the intrinsic gain. Evaluate the value of gmro for an NMOS transistor fabricated in a 0.8-μm CMOS process for which = 12.5 V/μm of channel length. Let the device have minimum channel length and be operated at an overdrive voltage of 0.2 V.
Ans.
100 V/V k′ n 20 = 1 2 --1 2 --– kn ′ kp ′ μm 0.8 ⁄ VA ′ gmro 2VA VOV; ⁄ = EXERCISES vgs 292 Chapter 5 MOS Field-Effect Transistors (MOSFETs) We are now ready to consider the various possible configurations of MOSFET amplifiers, and we will do that in the present section. To focus our attention on the salient features of the var-ious configurations, we shall present them in their most simple, or “stripped down” version.
Thus, we will not show the dc biasing arrangements, leaving the study of bias design to the next section. Finally, in Section 5.8 we will bring everything together and present practical circuits for discrete-circuit MOSFET amplifiers; namely, those amplifer circuits that can be constructed using discrete components. The study of integrated-circuit amplifiers begins in Chapter 7.
5.6.1 The Three Basic Configurations There are three basic configurations for connecting the MOSFET as an amplifier. Each of these configurations is obtained by connecting one of the three MOSFET terminals to ground, thus cre-ating a two-port network with the grounded terminal being common to the input and output ports.
Figure 5.43 shows the resulting three configurations with the biasing arrangements omitted.
In the circuit of Fig. 5.43(a) the source terminal is connected to ground, the input voltage sig-nal is applied between the gate and ground, and the output voltage signal is taken between the drain and ground, across the resistance . This configuration, therefore, is called the grounded-source or common-source (CS) amplifier. It is by far the most popular MOS amplifier configuration and is the one we utilized in Sections 5.4 and 5.5 to study MOS amplifier operation.
The common-gate (CG) or grounded-gate amplifier is shown in Fig. 5.43(b). It is obtained by connecting the gate to ground, applying the input between the source and Figure 5.43 The three basic MOSFET amplifier configurations.
vi vo RD vi RD vi vo RD vo vi (a) Common Source (CS) (b) Common Gate (CG) vo vi RL (c) Common Drain (CD) 5.6 Basic MOSFET Amplifier Configurations 293 ground, and taking the output across the resistance connected between the drain and ground. We encountered a CG amplifier in Example 5.11.
Finally, Fig. 5.43(c) shows the common-drain (CD) or grounded-drain amplifier. It is obtained by connecting the drain terminal to ground, applying the input voltage signal between gate and ground, and taking the output voltage signal between the source and ground, across a load resistance . For reasons that will become apparent shortly, this con-figuration is more commonly called the source follower. Our study of the three basic MOS amplifier configurations will reveal that each has dis-tinctly different attributes and hence areas of application.
5.6.2 Characterizing Amplifiers Before we begin our study of the different MOSFET amplifier configurations, we consider how to characterize the performance of an amplifier as a circuit building block. An introduc-tion to this topic was presented in Section 1.5.
Figure 5.44(a) shows an amplifier fed with a signal source having an open-circuit volt-age and an internal resistance . These can be the parameters of an actual signal source or, in a cascade amplifier, the Thévenin equivalent of the output circuit of another amplifier stage preceding the one under study. The amplifier is shown with a load resistance Figure 5.44 Characterization of the amplifier as a functional block: (a) An amplifier fed with a voltage signal vsig having a source resistance Rsig, and feeding a load resistance RL; (b) Equivalent-circuit representa-tion of the circuit in (a); (c) Determining the amplifier output resistance Ro.
vo RD vi RL vsig Rsig RL Rsig Rsig Avovi vsig vsig RL RL Rin ii ii ix io vo vi vi vx vo vi Ro (a) (b) RL (c) Ro io 0 294 Chapter 5 MOS Field-Effect Transistors (MOSFETs) connected to the output terminal. Here, can be an actual load resistance or the input resis-tance of a succeeding amplifier stage in a cascade amplifier.
Figure 5.44(b) shows the amplifier circuit with the amplifier block replaced by its equiv-alent-circuit model. The input resistance represents the loading effect of the amplifier input on the signal source. It is found from and together with the resistance forms a voltage divider that reduces to the value that appears at the amplifier input, (5.65) All the amplifier circuits studied in this section are unilateral. That is, they do not contain internal feedback, and thus will be independent of . However, as will be seen in subse-quent chapters, this is not always the case.
The second parameter in characterizing amplifier performance is the open-circuit volt-age gain , defined as The third and final parameter is the output resistance . Observe from Fig. 5.44(b) that is the resistance seen looking back into the amplifier output terminal with set to zero.
Thus can be determined, at least conceptually, as indicated in Fig. 5.44(c) with The controlled source and the output resistance represent the Thévenin equiva-lent of the amplifier output circuit, and the output voltage can be found from (5.66) Thus the voltage gain of the amplifier proper, , can be found as (5.67) and the overall voltage gain , can be determined by combining Eqs. (5.65) and (5.67): (5.68) 5.6.3 The Common-Source (CS) Amplifier Of the three basic MOS amplifier configurations, the common source is the most widely used. Typically, in an amplifier formed by cascading a number of stages, the bulk of the voltage gain is obtained by using one or more common-source stages in the cascade.
RL Rin Rin vi ii ----≡ Rsig vsig vi vi Rin Rin Rsig + ----------------------vsig = Rin RL Avo Avo vo vi ----RL ∞ = ≡ Ro Ro vi Ro Ro vx ix ----= Avovi Ro vo vo RL RL Ro + ------------------ Avovi = Av Av vo vi ----Avo RL RL Ro + ------------------= ≡ Gv Gv vo vsig -------≡ Gv Rin Rin Rsig + ---------------------- Avo RL RL Ro + ------------------= 5.6 Basic MOSFET Amplifier Configurations 295 Figure 5.45(a) shows a common-source amplifier (with the biasing arrangement omitted) fed with a signal source having a source resistance . We wish to analyze this circuit to determine , , , and . For this purpose we shall assume that is part of the amplifier; thus if a load resistance is connected to the amplifier output, it appears in par-allel with .
Characteristic Parameters of the CS Amplifier Replacing the MOSFET with its hybrid- model, we obtain the CS amplifier equivalent circuit shown in Fig 5.45(b). We shall use this equivalent circuit to determine the characteristic parameters and as follows.
The input resistance is obviously infinite, (5.69) The output voltage is found by multiplying the current by the total resistance between the output node and ground, Since , the open-circuit voltage gain can be obtained as (5.70) Observe that the transistor output resistance reduces the magnitude of the voltage gain. In discrete-circuit amplifiers, which are of interest to us in this chapter, is usually much Figure 5.45 (a) Common-source amplifier fed with a signal vsig from a generator with a resistance Rsig. The bias circuit is omitted. (b) The common-source amplifier with the MOSFET replaced with its hybrid- model.
Rin vi vo Rin vgs vi gmvgs vo RoRD || ro Ro vsig vsig Rsig Rsig (a) (b) RD RD ro π vsig Rsig Rin Avo Ro Gv RD RL RD π Rin, Avo, Ro Rin Rin ∞ = vo gmvgs ( ) vo gmvgs ( ) RD ro || ( ) – = vgs vi = Avo vo vi ⁄ ≡ Avo gm RD ro || ( ) – = ro RD 296 Chapter 5 MOS Field-Effect Transistors (MOSFETs) lower than and the effect of on reducing is slight (less than 10% or so). Thus in many cases we can neglect and express simply as (5.71) The reader is cautioned, however, that neglecting is allowed only in discrete-circuit design. As will be seen in Chapter 7, plays a central role in IC amplifiers. The output resistance is the resistance seen looking back into the output terminal with set to zero. From Fig. 5.45(b) we see that with set to zero, will be zero, and thus will be zero, resulting in (5.72) Here, has the beneficial effect of reducing the value of . In discrete circuits, however, this effect is slight and we can make the approximation (5.73) This concludes the analysis of the CS amplifier proper. We can now make the following observations.
1. The input resistance is ideally infinite.
2. The output resistance is moderate to high (in the kilohms to tens of kilohms range).
Reducing to lower is not a viable proposition, since the voltage gain is also reduced. Alternatively, if a low output resistance (in the ohms to tens of ohms range) is needed, a source follower stage is called for, as will be discussed in Section 5.6.6.
3. The open-circuit voltage gain can be high, making the CS configuration the work-horse in MOS amplifier design. Unfortunately, however, the bandwidth of the CS ampli-fier is severely limited. We shall study amplifier frequency response in Chapter 9.
Overall Voltage Gain To determine the overall voltage gain , we first note that the infinite input resistance will make the entire signal appear at the amplifier input, (5.74) an obviously ideal situation. At this point we should remind the reader that to maintain a rea-sonably linear operation, and hence should be kept much smaller than If a load resistance is connected to the output terminal of the amplifier, this resis-tance will appear in parallel with It follows that the voltage gain can be obtained by simply replacing in the expression for in Eq. (5.70) by , (5.75) This expression together with the fact that , provides the overall voltage gain, (5.76) ro ro Avo ro Avo Avo gmRD – ( ) ro ro Ro vi vi vgs gmvgs Ro RD ro || = ro Ro Ro RD RD Ro Avo Gv vsig vi vsig = vi vsig 2VOV.
RL RD.
Av RD Avo RD RL || Av gm RD RL ro || || ( ) – = vi vsig = Gv Av gm RD RL ro || || ( ) – = = 5.26 Use in Eq. (5.70) together with in Eq. (5.72) to obtain Show that the result is identical to that in Eq. (5.75).
Avo Ro Av.
EXERCISE 5.6 Basic MOSFET Amplifier Configurations 297 Performing the Analysis Directly on the Circuit Diagram Although small-signal, equivalent-circuit models provide a systematic process for the analysis of any amplifier cir-cuit, the effort involved in drawing the equivalent circuit is sometimes not justified. That is, in simple situations and after a lot of practice, one can perform the small-signal analysis directly on the circuit schematic. Because in this way one remains closer to the actual cir-cuit, the direct analysis can yield greater insight into circuit operation. Figure 5.46 shows the direct analysis of the CS amplifier. Observe that we have “pulled out” the resistance from the transistor, thus making the transistor drain conduct while still accounting for the effect of .
5.6.4 The Common-Source Amplifier with a Source Resistance It is often beneficial to insert a resistance in the source lead of the common-source ampli-fier as shown in Fig. 5.47(a). The corresponding small-signal equivalent circuit is shown in Fig. 5.47(b), where we note that the MOSFET has been replaced with its T equivalent-cir-cuit model. The T model is used in preference to the model because it makes the analysis in this case somewhat simpler. In general, whenever a resistance is connected in the source lead, the T model is preferred. The source resistance then simply appears in series with the resistance and can be added to it.
It should be noted that we have not included in the equivalent-circuit model.
Including would complicate the analysis considerably; would connect the output node of the amplifier to the input side and thus would make the amplifier nonunilateral.
Figure 5.46 Performing the analysis directly on the circuit diagram with the MOSFET model used implicitly.
Rin vgs vi vgs vsig gmvgs RoRD || ro vo vsig Rsig ro RD vo gmvgs(RD || ro) 0 ro gmvgs ro 5.27 A CS amplifier utilizes a MOSFET biased at mA with V and k .
The device has V. The amplifier is fed with a source having k , and a 20-k load is connected to the output. Find , , , , and . If to maintain reasonable linearity, the peak of the input sine-wave signal is limited to 10% of what is the peak of the sine-wave voltage at the output?
Ans.
; V/V; 18.2 k ; V/V; V/V; 0.95 V ID 0.25 = VOV 0.25 = RD 20 = Ω VA 50 = Rsig 100 = Ω Ω Rin Avo Ro Av Gv 2VOV ( ) ∞ 36.4 – Ω 19 – 19 – EXERCISE Rs π 1 gm ⁄ ro ro ro 298 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Fortunately, it turns out that the effect of on the operation of the discrete-circuit amplifier is not important. This can be verified by computer simulation, using for instance SPICE. This is not the case, however, for the integrated-circuit version of the circuit, where plays a major role and must be taken into account, as we shall do in Chapter 7.
From Fig. 5.47(b) we see that the input resistance is infinite and thus Unlike the CS amplifier, however, here only a fraction of appears between gate and source as . It can be determined from the voltage divider composed of and that appears across the amplifier input, as follows: (5.77) Thus we can use the value of to control the magnitude of the signal and thereby ensure that does not become too large and cause unacceptably high nonlinear distortion.
This is the first benefit of including resistor . Other benefits will be encountered in later sections and chapters. For instance, it will be shown in Chapter 9 that causes the useful bandwidth of the amplifier to be extended. The mechanism by which causes such improvements in amplifier performance is negative feedback. To see how introduces Figure 5.47 The CS amplifier with a source resistance Rs: (a) Circuit without bias details; (b) Equivalent cir-cuit with the MOSFET represented by its T model.
Rin vi vgs Rin vi vsig vsig Rsig Rsig RoRD 0 vo vo RD Rs RD Rs G D S i i gm 1 (a) (b) Ro ro ro Rin vi vsig.
= vi vgs 1 gm ⁄ Rs vgs vi 1 gm ⁄ 1 gm ⁄ Rs + -------------------------vi 1 gmRs + ---------------------= = Rs vgs vgs Rs Rs Rs Rs 5.6 Basic MOSFET Amplifier Configurations 299 negative feedback, refer to Fig. 5.47(a): If while keeping constant, for some reason the drain current increases, the source current also will increase, resulting in an increased volt-age drop across . Thus the source voltage rises, and the gate-to-source voltage decreases.
The latter effect causes the drain current to decrease, counteracting the initially assumed change, an indication of the presence of negative feedback. In Chapter 10 we shall study negative feedback formally. There we will learn that the improvements that negative feed-back provides are obtained at the expense of a reduction in gain. We will now show this to be the case in the circuit of Fig. 5.47.
The output voltage is obtained by multiplying the controlled-source current i by , The current i in the source lead can be found by dividing by the total resistance in the source, (5.78) Thus, the voltage gain can be found as (5.79) which can also be expressed as (5.80) Equation (5.80) indicates that including the resistance reduces the voltage gain by the factor . This is the price paid for the improvements that accrue as a result of It is interesting to note that in Chapter 10, we will find that the factor is the “amount of negative feedback” introduced by . It is also the same factor by which band-width and other performance parameters improve. Because of the negative-feedback action of it is known as a source-degeneration resistance. There is another useful interpretation of the expression for the drain current in Eq.
(5.78): The quantity between brackets on the right-hand side can be thought of as the “effec-tive transconductance with included.” Thus, including reduces the transconductance by the factor This, of course, is simply the result of the fact that only a fraction of appears as (see Eq. 5.77.).
The alternative gain expression in Eq. (5.79) has a powerful and insightful interpretation: The voltage gain between gate and drain is equal to the ratio of the total resistance in the drain to the total resistance in the source , Voltage gain from gate to drain = (5.81) This is a general expression. For instance, setting in Eq. (5.79) yields of the CS amplifier.
Finally, we consider the situation of a load resistance connected at the output. We can obtain the gain using the open-circuit voltage gain together with the output resis-tance which can be found by inspection to be vi Rs vo RD vo i RD – = vi i vi 1 gm ⁄ Rs + -------------------------gm 1 gmRs + ---------------------⎝ ⎠ ⎛ ⎞vi = = Avo Avo vo vi ----RD 1 gm ⁄ Rs + -------------------------– = = Avo gmRD 1 gmRs + ---------------------– = Rs 1 gmRs + ( ) Rs.
1 gmRs + ( ) Rs Rs Rs Rs 1 gmRs + ( ).
1 1 gmRs + ( ) ⁄ vi vgs RD ( ) 1 gm Rs + ⁄ ( ) Total resistance in drain Total resistance in source -------------------------------------------------------------– Rs 0 = Avo RL Av Avo Ro, Ro RD = 300 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Alternatively, can be obtained by simply replacing in Eq. (5.79) or (5.80) by ; thus, (5.82) or (5.83) Observe that Eq. (5.82) is a direct application of the ratio of total resistance rule of Eq. (5.81).
Finally, note that because is infinite, and the overall voltage gain is equal to .
5.6.5 The Common-Gate (CG) Amplifier Figure 5.48(a) shows a common-gate amplifier with the biasing circuit omitted. The amplifier is fed with a signal source characterized by and . Since appears in series with the source, it is more convenient to represent the transistor with the T model than with the model. Doing this, we obtain the amplifier equivalent circuit shown in Fig. 5.48(b). Note that we have not included This would have complicated the analysis considerably, for would have appeared between the output and the input side of the amplifier. Fortunately, it Figure 5.48 (a) Common-gate (CG) amplifier with bias arrangement omitted. (b) Equivalent circuit of the CG amplifier with the MOSFET replaced with its T model.
Av RD RD RL || ( ) Av RD RL || 1 gm ⁄ R + s -------------------------– = Av gm RD RL || ( ) 1 gmRs + -----------------------------– = Rin vi vsig = Gv Av 5.28 In Exercise 5.27 we applied an input signal of 50 mV peak and obtained an output signal of approximately 1 V peak. Assume that for some reason we now have an input signal that is 0.2 V peak and that we wish to modify the circuit to keep unchanged, and thus keep the nonlinear distortion from increasing. What value should we use for ? What value of will result? What will the peak signal at the output become? Assume .
Ans. 1.5 k ; V/V; 1 V vsig vsig vgs Rs Gv ro ∞ = Ω 5 – EXERCISE vsig Rsig Rsig π ro: ro Rin vi Rin vi vsig Rsig Rsig vsig Ro RD vo vo RD G D (a) (b) RD 1/gm 1/gm Ro i i S 5.6 Basic MOSFET Amplifier Configurations 301 turns out that the effect of on the performance of a discrete CG amplifier is very small. We will consider the effect of when we study the IC form of the CG amplifier in Chapter 7.
From inspection of the equivalent circuit of Fig. 5.48(b), we see that the input resistance (5.84) This should have been expected, since we are looking into the source and the gate is grounded.
Typically is a few hundred ohms; thus the CG amplifier has a low input resistance. To determine the voltage gain , we write at the drain node and substitute for the source current i from to obtain (5.85) which except for the positive sign is identical to the expression for of the CS amplifier (when is neglected). The output resistance of the CG circuit can be found by inspection of the circuit in Fig.
5.48(b) as (5.86) which is the same as in the case of the CS amplifier (with neglected).
Although the gain of the CG amplifier proper has the same magnitude as that of the CS amplifier, this is usually not the case as far as the overall voltage gain is concerned. The low input resistance of the CG amplifier can cause the input signal to be severely attenuated. Specifically, (5.87) from which we see that except for situations in which is on the order of , the signal transmission factor can be very small and the overall voltage gain can be corre-spondingly small. Specifically, with a resistance connected at the output Thus, (5.88) Observe that the overall voltage gain is simply the ratio of the total resistance in the drain circuit to the total resistance in the source circuit. If is of the same order as and , will be very small.
Because of its low input resistance, the CG amplifier alone has very limited application.
One such application is to amplify high-frequency signals that come from sources with rela-tively low resistances. These include cables, where it is usually necessary for the input ro ro Rin 1 gm ------= 1 gm ⁄ Avo vo iRD – = i vi 1 gm ⁄ -------------– = Avo vo vi ----gmRD = ≡ Avo ro Ro RD = ro vi vsig ------- Rin Rin Rsig + ---------------------- 1 gm ⁄ 1 gm ⁄ Rsig + ----------------------------= = Rsig 1 gm ⁄ vi vsig ⁄ Gv RL Gv 1 gm ⁄ Rsig 1 gm ⁄ + ---------------------------- gm RD RL || ( ) [ ] = Gv RD RL || ( ) Rsig 1 gm ⁄ + ----------------------------= Rsig RD RL Gv 302 Chapter 5 MOS Field-Effect Transistors (MOSFETs) resistance of the amplifier to match the characteristic resistance of the cable. As will be shown in Chapter 9, the CG amplifier has excellent high-frequency response. Thus it can be com-bined with the CS amplifier in a very beneficial way that takes advantage of the best features of each of the two configurations. A very significant circuit of this kind will be studied in Chapter 7.
.
5.6.6 The Common-Drain Amplifier or Source Follower The last of the basic MOSFET amplifier configurations is the common-drain amplifier, an important circuit that finds application in the design of both small-signal amplifiers as well as amplifiers that are required to handle large signals and deliver substantial amounts of sig-nal power to a load. This latter variety will be studied in Chapter 11. The common drain amplifier is more commonly known as the source follower. The reason behind this name will become apparent shortly.
The Need for Voltage Buffers Before embarking on the analysis of the source fol-lower, it is useful to look at one of its more common applications. Consider the situation depicted in Fig. 5.49(a). A signal source delivering a signal of reasonable strength (1 V) Figure 5.49 Illustrating the need for a unity-gain buffer amplifier.
5.29 A CG amplifier is required to match a signal source with . At what current should the MOSFET be biased if it is operated at an overdrive voltage of 0.20 V? If the total resistance in the drain circuit is 2 k , what overall voltage gain is realized?
Ans. 1 mA; 10 V/V Rsig 100 Ω = ID Ω EXERCISE Rsig 1 M Rsig 1 M vsig 1V vsig 1V vo 1 mV RL 1 k RL 1 k (a) (b) Rin very large Ro 100 Rsig 1 M vsig 1V RL 1 k vo 0.9V (c) 1V Avo1 5.6 Basic MOSFET Amplifier Configurations 303 with an internal resistance of 1 M is to be connected to a 1-k load resistance. Connecting the source to the load directly as in Fig. 5.49(b) would result in severe attenuation of the sig-nal; the signal appearing across the load will be only of the input signal or about 1 mV. An alternative course of action is suggested in Fig. 5.49(c). Here we have inter-posed an amplifier between the source and the load. Our amplifier, however, is unlike the amplifiers we have been studying in this chapter thus far; it has a voltage gain of only unity.
This is because our signal is already of sufficient strength and we do not need to increase its amplitude. Note, however, that our amplifier has a very large input resistance, thus almost all of (i.e., 1 V) will appear at the input of the amplifier proper. Since the amplifier has a low output resistance (100 ), 90% of this signal (0.9 V) will appear at the output, obviously a very significant improvement over the situation without the amplifier. As will be seen shortly, the source follower can easily implement the unity-gain buffer amplifier shown in Fig. 5.49(c).
Characteristic Parameters of the Source Follower Figure 5.50(a) shows a source follower with the bias circuit omitted. The source follower is fed with a signal generator ( , ) and has a load resistance connected between the source terminal and ground.
We shall assume that includes both the actual load and any other resistance that may be present between the source terminal and ground (e.g., for biasing purposes). Normally, the actual load resistance would be much lower in value than such other resistances and thus would dominate.
Since the MOSFET has a resistance connected in its source terminal, it is most con-venient to use the T model, as shown in Fig. 5.50(b). Note that we have included , simply because it is very easy to do so. However, since in effect appears in parallel with , and since in discrete circuits , we can neglect and obtain the simplified equivalent cir-cuit shown in Fig. 5.50(c). From the latter circuit we can write by inspection and obtain from the voltage divider formed by and as (5.89) Setting we obtain (5.90) The output resistance is found by setting (i.e., by grounding the gate). Now look-ing back into the output terminal, excluding , we simply see , thus (5.91) The unity open-circuit voltage gain together with in Eq. (5.91) can be used to find when a load resistance is connected. The result is simply the expression in Eq. (5.89).
Finally, because of the infinite , , and the overall voltage gain is (5.92) Thus will be lower than unity. However, because is usually low, the voltage gain can be close to unity. The unity open-circuit voltage gain in Eq. (5.90) indicates that the Ω Ω 1 1000 1 + ( ) ⁄ vsig Ω vsig Rsig RL RL RL ro ro RL ro RL ro Rin ∞ = Av 1 gm ⁄ RL Av vo vi ----≡ RL RL 1 gm ⁄ + -------------------------= RL ∞ = Avo 1 = Ro vi 0 = RL 1 gm ⁄ Ro 1 gm ⁄ = Ro Av RL Rin vi vsig = Gv Av RL RL 1 gm ⁄ + -------------------------= = Gv 1 gm ⁄ 304 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Ro Rin vi vo (a) vsig Rsig RL RL ro vo vi gm 1 i i (b) vsig Rsig 0 RL Ro vo vi Rin gm 1 gm 1 i i (c) vsig Rsig 0 Figure 5.50 (a) Common-drain amplifier or source follower. (b) Equivalent circuit of the source follower obtained by replacing the MOSFET with its T model. Note that ro appears in parallel with RL and in discrete circuits, ro RL. Neglecting ro, we obtain the simplified equivalent circuit in (c).
5.6 Basic MOSFET Amplifier Configurations 305 voltage at the source terminal will follow that at the input, hence the name source fol-lower.
In conclusion, the source follower features a very high input resistance (ideally, infi-nite), a relatively low output resistance, and an open-circuit voltage gain that is near unity (ideally, unity). Thus the source follower is ideally suited for implementing the unity-gain voltage buffer of Fig. 5.49(c). The source follower is also used as the output (i.e., last) stage in a multistage amplifier, where its function is to equip the overall amplifier with a low output resistance, thus enabling it to supply relatively large load currents without loss of gain (i.e., with little reduction of output signal level). The design of output stages is studied in Chapter 11.
5.6.7 Summary and Comparisons For easy reference and to enable comparisons, we present in Table 5.4 the formulas for deter-mining the characteristic parameters of discrete MOS amplifiers. Note that has been neglected throughout. This is because our interest in this chapter is primarily in discrete-circuit amplifiers. As already mentioned, has a relatively small effect on the performance of dis-crete-circuit amplifiers and can usually be neglected. In some cases, however, it is very easy to take into account, such as in the case of the CS and CD amplifiers, and one is encouraged to do so. For integrated-circuit amplifiers, must always be taken into account.
D5.30 It is required to design a source follower that implements the buffer amplifier shown in Fig.
5.49(c). If the MOSFET is operated with an overdrive voltage V, at what drain cur-rent should it be biased? Find the output signal amplitude and the signal amplitude between gate and source.
Ans. 1.25 mA; 0.91 V; 91 mV D5.31 A MOSFET is connected in the source-follower configuration and employed as the output stage of a cascade amplifier. It is required to provide an output resistance of 200 . If the MOSFET has mA/V2 and is operated at V, find the required W/L ratio. Also specify the dc bias current If the amplifier load resistance varies over the range 1 k to 10 k what is the range of of the source follower?
Ans. 50; 0.625 mA; 0.83 V/V to 0.98 V/V 5.32 Refer to Fig. 5.50(b). Show that taking into account results in Now, recalling that and , find in terms of and . For a technology for which V, what is the maximum at which the transistor can be oper-ated while obtaining V/V?
Ans. ; 0.4 V VOV 0.25 = Ω k′ n 0.4 = VOV 0.25 = ID.
Ω Ω, Gv ro Avo ro ro 1 gm ⁄ + ------------------------= ro VA ID ⁄ = gm 2ID VOV ⁄ = Avo VA VOV VA 20 = VOV Avo 0.99 ≥ Avo 1 1 VOV 2VA ⁄ + [ ] ⁄ = EXERCISES ro ro ro ro 306 Chapter 5 MOS Field-Effect Transistors (MOSFETs) In addition to the remarks already made throughout this section about the characteristics and areas of applicability of the various configurations, we make the following concluding points: 1. The CS configuration is the best suited for realizing the bulk of the gain required in an amplifier. Depending on the magnitude of the gain required, either a single stage or a cascade of two or three stages can be used.
2. Including a resistor in the source lead of the CS stage provides a number of per-formance improvements at the expense of gain reduction.
3. The low input resistance of the CG amplifier makes it useful only in specific applications.
As we shall see in Chapter 9, it has a much better high-frequency response than the CS amplifier. This superiority makes it useful as a high-frequency amplifier, especially when combined with the CS circuit. We shall see one such combination in Chapter 7.
4. The source follower finds application as a voltage buffer for connecting a high-resistance source to a low-resistance load and as the output stage in a multistage amplifier where its purpose is to equip the amplifier with a low output resistance.
5.7 Biasing in MOS Amplifier Circuits As discussed in Section 5.4, an essential step in the design of a MOSFET amplifier circuit is the establishment of an appropriate dc operating point for the transistor. This is the step known as biasing or bias design. An appropriate dc operating point or bias point is charac-terized by a stable and predictable dc drain current ID and by a dc drain-to-source voltage VDS that ensures operation in the saturation region for all expected input-signal levels. Table 5.4 Characteristics of MOSFET Amplifiers Characteristicsa, b Amplifier type Common source (Fig. 5.45) Common source with (Fig. 5.47) Common gate (Fig. 5.48) Source follower (Fig. 5.50) 1 a For the interpretation of Rin, Avo, and Ro, refer to Fig. 5.44(b).
b The MOSFET output resistance ro has been neglected, as is permitted in the discrete-circuit amplifiers studied in this chapter. For IC amplifiers, ro must always be taken into account.
Rin Avo Ro Av Gv ∞ gmRD – RD gm RD RL || ( ) – gm RD RL || ( ) – Rs ∞ gmRD 1 gmRs + ---------------------– RD gm RD RL || ( ) – 1 gmRs + ---------------------------------RD RL || 1 gm ⁄ Rs + -------------------------– gm RD RL || ( ) 1 gmRs + -----------------------------– RD RL || 1 gm ⁄ Rs + -------------------------– 1 gm ------gmRD RD gm RD RL || ( ) RD RL || Rsig 1 gm ⁄ + ----------------------------∞ 1 gm ------RL RL 1 gm ⁄ + -------------------------RL RL 1 gm ⁄ + -------------------------Rs 5.7 Biasing in MOS Amplifier Circuits 307 5.7.1 Biasing by Fixing VGS The most straightforward approach to biasing a MOSFET is to fix its gate-to-source voltage VGS to the value required9 to provide the desired ID. This voltage value can be derived from the power-supply voltage VDD through the use of an appropriate voltage divider. Alternatively, it can be derived from another suitable reference voltage that might be available in the system.
Independent of how the voltage VGS may be generated, this is not a good approach to biasing a MOSFET. To understand the reason for this statement, recall that and note that the values of the threshold voltage Vt, the oxide-capacitance Cox, and (to a lesser extent) the transistor aspect ratio vary widely among devices of supposedly the same size and type. This is certainly the case for discrete devices, in which large spreads in the values of these parameters occur among devices of the same manufacturer’s part number.
The spread is also large in integrated circuits, especially among devices fabricated on differ-ent wafers and certainly between different batches of wafers. Furthermore, both Vt and μn depend on temperature, with the result that if we fix the value of VGS, the drain current ID becomes very much temperature dependent.
To emphasize the point that biasing by fixing VGS is not a good technique, we show in Fig. 5.51 two iD–vGS characteristic curves representing extreme values in a batch of MOSFETs of the same type. Observe that for the fixed value of VGS, the resultant spread in the values of the drain current can be substantial.
9That is indeed what we were doing in Section 5.4. However, the amplifier circuits studied there were conceptual ones, not actual practical circuits. Our purpose in this section is to study the latter.
Figure 5.51 The use of fixed bias (constant VGS) can result in a large variability in the value of ID. Devices 1 and 2 represent extremes among units of the same type.
ID 1 2 ---μnCoxW L ----- VGS Vt – ( ) 2 = W L ⁄ iD vGS VGS ID1 0 ID2 Device 2 Device 1 308 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.7.2 Biasing by Fixing VG and Connecting a Resistance in the Source An excellent biasing technique for discrete MOSFET circuits consists of fixing the dc volt-age at the gate, VG, and connecting a resistance in the source lead, as shown in Fig. 5.52(a).
For this circuit we can write (5.93) Now, if VG is much greater than VGS, ID will be mostly determined by the values of VG and RS. However, even if VG is not much larger than VGS, resistor RS provides negative feedback, which acts to stabilize the value of the bias current ID. To see how this comes about, consider what happens when ID increases for whatever reason. Equation (5.93) indicates that since VG is constant, VGS will have to decrease. This in turn results in a decrease in ID, a change that is Figure 5.52 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a) basic arrangement; (b) reduced variability in ID; (c) practical implementation using a single supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical implementation using two supplies.
VG VGS RSID + = (a) VG VGS RS ID ID Slope 1RS Device 2 iD ID2 ID1 VGS2 0 VGS1 VG vGS Device 1 (b) (c) VGS 0 RG1 RG2 VG RD RS ID VDD ID (d) RD VDD RS RG2 CC1 RG1 vsig Rsig (e) ID VDD RD VSS ID 0 RS VGS RG 5.7 Biasing in MOS Amplifier Circuits 309 opposite to that initially assumed. Thus the action of RS works to keep ID as constant as pos-sible. This negative feedback action of RS gives it the name degeneration resistance, a name that we will appreciate much better at a later point in this text.10 Figure 5.52(b) provides a graphical illustration of the effectiveness of this biasing scheme. Here too we show the iD–vGS characteristics for two devices that represent the extremes of a batch of MOSFETs. Superimposed on the device characteristics is a straight line that represents the constraint imposed by the bias circuit—namely, Eq. (5.93). The inter-section of this straight line with the iD–vGS characteristic curve provides the coordinates (ID and VGS) of the bias point. Observe that compared to the case of fixed VGS, here the variabil-ity obtained in ID is much smaller. Also, note that the variability decreases as VG and RS are made larger (thus providing a bias line that is less steep).
Two possible practical discrete implementations of this bias scheme are shown in Fig. 5.52(c) and (e). The circuit in Fig. 5.52(c) utilizes one power-supply VDD and derives VG through a voltage divider (RG1, RG2). Since IG = 0, RG1 and RG2 can be selected to be very large (in the megohm range), allowing the MOSFET to present a large input resis-tance to a signal source that may be connected to the gate through a coupling capacitor, as shown in Fig. 5.52(d). Here capacitor CC1 blocks dc and thus allows us to couple the signal vsig to the amplifier input without disturbing the MOSFET dc bias point. The value of CC1 should be selected large enough to approximate a short circuit at all signal fre-quencies of interest. We shall study capacitively coupled MOSFET amplifiers, which are suitable only in discrete circuit design, in Section 5.8. Finally, note that in the circuit of Fig. 5.52(c), resistor RD is selected to be as large as possible to obtain high gain but small enough to allow for the desired signal swing at the drain while keeping the MOSFET in saturation at all times. When two power supplies are available, as is often the case, the somewhat simpler bias arrangement of Fig. 5.52(e) can be utilized. This circuit is an implementation of Eq. (5.93), with VG replaced by VSS. Resistor RG establishes a dc ground at the gate and presents a high input resistance to a signal source that may be connected to the gate through a coupling capacitor.
10The action of in stabilizing the value of the bias current is not unlike that of the resistance , which we included in the source lead of a CS amplifier in Section 5.6.4. In the latter case also, works to reduce the change in with the result that the amplifier gain is reduced.
RS ID Rs Rs iD It is required to design the circuit of Fig. 5.52(c) to establish a dc drain current ID = 0.5 mA. The MOSFET is specified to have Vt = 1 V and For simplicity, neglect the channel-length modulation effect (i.e., assume λ = 0). Use a power-supply VDD = 15 V. Calculate the percentage change in the value of ID obtained when the MOSFET is replaced with another unit having the same but Vt = 1.5 V.
Solution As a rule of thumb for designing this classical biasing circuit, we choose RD and RS to provide one-third of the power-supply voltage VDD as a drop across each of RD, the transistor (i.e., VDS) and RS. For VDD = 15 V, kn ′W L ⁄ = 1 mA/V2.
kn ′W L ⁄ Example 5.12 310 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Example 5.12 continued this choice makes VD = +10 V and VS = +5 V. Now, since ID is required to be 0.5 mA, we can find the val-ues of RD and RS as follows: The required value of VGS can be determined by first calculating the overdrive voltage VOV from which yields VOV = 1 V, and thus, Now, since VS = +5 V, VG must be To establish this voltage at the gate we may select RG1 = 8 MΩ and RG2 = 7 MΩ. The final circuit is shown in Fig. 5.53. Observe that the dc voltage at the drain (+10 V) allows for a positive signal swing of +5 V (i.e., up to VDD) and a negative signal swing of –4 V [i.e., down to (VG – Vt)]. RD VDD VD – ID -----------------------15 10 – 0.5 ------------------10 kΩ = = = RS VS RS -----5 0.5 -------10 kΩ = = = ID = 1 2 ---kn ′ W L ⁄ ( )VOV 2 0.5 1 2 ---1 × VOV 2 × = VGS Vt VOV + 1 1 + 2 V = = = VG VS VGS + 5 2 + 7 V = = = Figure 5.53 Circuit for Example 5.12.
VG 7 V 8 M 7 M VD 10 V RD 10 k VDD 15 V VS 5 V RS 10 k ID 0.5 mA ID 0.5 mA 5.7 Biasing in MOS Amplifier Circuits 311 5.7.3 Biasing Using a Drain-to-Gate Feedback Resistor A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor con-nected between the drain and the gate is shown in Fig. 5.54. Here the large feedback resis-tance RG (usually in the megohm range) forces the dc voltage at the gate to be equal to that at the drain (because IG = 0). Thus we can write which can be rewritten in the form (5.96) If the NMOS transistor is replaced with another having Vt = 1.5 V, the new value of ID can be found as follows: (5.94) (5.95) Solving Eqs. (5.94) and (5.95) together yields Thus the change in ID is which is ID 1 2 ---1 VGS 1.5 – ( )2 × × = VG VGS IDRS + = 7 VGS 10ID + = ID 0.455 mA = ID Δ 0.455 0.5 – 0.045 mA – = = 0.045 – 0.5 -----------------100 × 9% change.
– = 5.33 Consider the MOSFET in Example 5.12 when fixed-VGS bias is used. Find the required value of VGS to establish a dc bias current ID = 0.5 mA. Recall that the device parameters are Vt = 1 V, and λ = 0. What is the percentage change in ID obtained when the transistor is replaced with another having Vt = 1.5 V?
Ans. VGS = 2 V; −75% D5.34 Design the circuit of Fig. 5.52(e) to operate at a dc drain current of 0.5 mA and VD = +2 V. Let Vt = 1 V, λ = 0, VDD = VSS = 5 V. Use standard 5% resistor values (see Appendix G), and give the resulting values of ID, VD, and VS.
Ans. RD = RS = 6.2 kΩ; ID = 0.49 mA, VS = −1.96 V, and VD = +1.96 V. RG can be selected in the range of 1 MΩ to 10 MΩ.
kn ′W L ⁄ = 1 mA/V2, kn ′W L ⁄ = 1 mA/V2, EXERCISES VGS VDS VDD RDID – = = VDD VGS RDID + = 312 Chapter 5 MOS Field-Effect Transistors (MOSFETs) which is identical in form to Eq. (5.93), which describes the operation of the bias scheme discussed above [that in Fig. 5.52(a)]. Thus, here too, if ID for some reason changes, say increases, then Eq. (5.96) indicates that VGS must decrease. The decrease in VGS in turn causes a decrease in ID, a change that is opposite in direction to the one originally assumed.
Thus the negative feedback or degeneration provided by RG works to keep the value of ID as constant as possible.
The circuit of Fig. 5.54 can be utilized as an amplifier by applying the input voltage signal to the gate via a coupling capacitor so as not to disturb the dc bias conditions already estab-lished. The amplified output signal at the drain can be coupled to another part of the circuit, again via a capacitor. We have considered such an amplifier circuit in Section 5.5 (Example 5.10).
5.7.4 Biasing Using a Constant-Current Source The most effective scheme for biasing a MOSFET amplifier is that using a constant-current source. Figure 5.55(a) shows such an arrangement applied to a discrete MOSFET. Here RG (usually in the megohm range) establishes a dc ground at the gate and presents a large resis-tance to an input signal source that can be capacitively coupled to the gate. Resistor RD establishes an appropriate dc voltage at the drain to allow for the required output signal swing while ensuring that the transistor always remains in the saturation region.
Figure 5.54 Biasing the MOSFET using a large drain-to-gate feedback resistance, RG.
RD RG VDD ID ID 0 VDS VGS D5.35 Design the circuit in Fig. 5.54 to operate at a dc drain current of 0.5 mA. Assume VDD = +5 V, Vt = 1 V, and λ = 0. Use a standard 5% resistance value for RD, and give the actual values obtained for ID and VD.
Ans. RD = 6.2 kΩ; k′ nW L ⁄ = 1 mA/V2, ID 0.49 mA; VD 1.96 V EXERCISE 5.7 Biasing in MOS Amplifier Circuits 313 A circuit for implementing the constant-current source I is shown in Fig. 5.55(b). The heart of the circuit is transistor Q1, whose drain is shorted to its gate, and thus is operating in the saturation region, such that (5.97) where we have neglected channel-length modulation (i.e., assumed λ = 0). The drain current of Q1 is supplied by VDD through resistor R. Since the gate currents are zero, (5.98) where the current through R is considered to be the reference current of the current source and is denoted IREF. Given the parameter values of Q1 and a desired value for IREF, Eqs. (5.97) and (5.98) can be used to determine the value of R. Now consider transistor Q2: It has the same VGS as Q1; thus if we assume that it is operating in saturation, its drain current, which is the desired current I of the current source, will be (5.99) where we have neglected channel-length modulation. Equations (5.98) and (5.99) enable us to relate the current I to the reference current IREF, (5.100) Thus I is related to IREF by the ratio of the aspect ratios of Q1 and Q2. This circuit, known as a current mirror, is very popular in the design of IC MOS amplifiers and will be studied in great detail in Chapter 7.
Figure 5.55 (a) Biasing the MOSFET using a constant-current source I. (b) Implementation of the constant-current source I using a current mirror.
I I I D RD RG Q VDD VSS (a) (b) VGS VSS Q2 Q1 R 0 To source of transistor Q in Fig. 5.55 (a) VDD ID1 ID2 IREF ID1 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ 1 VGS Vt – ( ) 2 = ID1 IREF VDD VSS VGS – + R --------------------------------------= = I ID2 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ 2 VGS Vt – ( ) 2 = = I IREF W L ⁄ ( )2 W L ⁄ ( )1 -------------------= 314 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.7.5 A Final Remark The bias circuits studied in this section are intended for discrete-circuit applications.
The only exception is the current mirror circuit of Fig. 5.55(b) which, as mentioned above, is extensively used in IC design. Bias arrangements for IC MOS amplifiers will be studied in Chapter 7.
5.8 Discrete-Circuit MOS Amplifiers With our study of MOS amplifier basics complete, we now put everything together by presenting practical circuits for discrete-circuit amplifiers. These circuits, which utilize the amplifier configurations studied in Section 5.6 and one of the biasing methods of Sec-tion 5.7, can be assembled using off-the-shelf discrete transistors, resistors, and capaci-tors. Though practical and carefully selected to illustrate some important points, the circuits presented in this section should be regarded only as examples of discrete-circuit MOS amplifiers. Indeed, there is a great variety of such circuits, a number of which are explored in the end-of-chapter problems. We should, however, caution the reader that MOS transistors are primarily used in integrated circuit design, as we shall see in Chapter 7 and beyond.
In this section we present a series of exercise problems, Exercises 5.37 to 5.41, that are carefully designed to illustrate important aspects of the amplifier circuits studied. These exer-cises are also intended to enable the reader to see more clearly the differences between the various circuit configurations. We strongly urge the reader to solve these exercises. As usual, the answers are provided.
5.8.1 The Basic Structure Figure 5.56 shows the basic circuit we shall utilize to implement the various configurations of discrete-circuit MOS amplifiers. Among the various schemes for biasing MOS amplifiers (Section 5.7), we have selected, for both its effectiveness and its simplicity, the one employ-ing constant-current biasing. Figure 5.56 indicates the dc current and the dc voltages result-ing at various nodes.
D5.36 Using two transistors Q1 and Q2 having equal lengths but widths related by design the circuit of Fig. 5.55(b) to obtain I = 0.5 mA. Let VDD = −VSS = 5 V, Vt = 1 V, and λ = 0. Find the required value for R. What is the voltage at the gates of Q1 and Q2? What is the lowest voltage allowed at the drain of Q2 while Q2 remains in the saturation region?
Ans. 85 kΩ; −3.5 V; −4.5 V W2 W1 ⁄ = 5, kn ′ W L ⁄ ( )1 = 0.8 mA/V2, EXERCISE 5.8 Discrete-Circuit MOS Amplifiers 315 5.37 Consider the circuit of Fig. 5.56 for the case VDD = VSS = 10 V, I = 0.5 mA, RG = 4.7 MΩ, RD = 15 kΩ, Vt = 1.5 V, and (W/L) = 1 mA/V2. Find VOV, VGS, VG, VS, and VD. Also, calculate the values of gm and ro, assuming that VA = 75 V. What is the maximum possible signal swing at the drain for which the MOSFET remains in saturation?
Ans. See Fig. E5.37; without taking into account the signal swing at the gate, the drain can swing to −1.5 V, a negative signal swing of 4 V kn ′ (a) 0 mA 4.7 M 0.5 mA 0 V 2.5 V 10 V VOV 1 V VGS 2.5 V 2.5 V 10 V 15 k 0.5 mA (b) G D gm 1 mAV ro 150 k 1gm 1 k ro vgs gmvgs S (c) ro G S D gm 1 i i Figure E5.37 EXERCISE 316 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.8.2 The Common-Source (CS) Amplifier As mentioned in Section 5.6, the common-source (CS) configuration is the most widely used of all MOSFET amplifier circuits. A common-source amplifier realized using the circuit of Fig. 5.56 is shown in Fig. 5.57(a). Observe that to establish a signal ground, or an ac ground as it is sometimes called, at the source, we have connected a large capacitor, CS, between the source and ground. This capacitor, usually in the microfarad range, is required to provide a very small impedance (ideally, zero impedance; i.e., in effect, a short circuit) at all signal fre-quencies of interest. In this way, the signal current passes through CS to ground and thus bypasses the output resistance of current source I (and any other circuit component that might be connected to the MOSFET source); hence, CS is called a bypass capacitor. Obviously, the lower the signal frequency, the less effective the bypass capacitor becomes. This issue will be studied in Section 9.1. For our purposes here we shall assume that CS is acting as a perfect short circuit and thus is establishing a zero signal voltage at the MOSFET source.
In order not to disturb the dc bias current and voltages, the signal to be amplified, shown as voltage source vsig with an internal resistance Rsig, is connected to the gate through a large capacitor CC1. Capacitor CC1, known as a coupling capacitor, is required to act as a perfect short circuit at all signal frequencies of interest while blocking dc. Here again, we note that as the signal frequency is lowered, the impedance of CC1 (i.e., ) will increase and its effectiveness as a coupling capacitor will be correspondingly reduced. This problem too will be considered in Section 9.1 when the dependence of the amplifier operation on frequency is studied. For our purposes here we shall assume CC1 is acting as a perfect short circuit as far as the signal is concerned. Before leaving CC1, we should point out that when the signal source can provide an appropriate dc path to ground, the gate can be connected directly to the signal source and both RG and CC1 can be dispensed with.
The voltage signal resulting at the drain is coupled to the load resistance RL via another coupling capacitor CC2. We shall assume that CC2 acts as a perfect short circuit at all signal frequencies of interest and thus that the output voltage vo = vd. Note that RL can be either an actual load resistor, to which the amplifier is required to provide its output voltage signal, or it can be the input resistance of another amplifier stage in cases where more than one stage of amplification is needed. (We will study multistage amplifiers in Chapter 8.) 1 jωCC1 ⁄ RD RG I VSS 0 V VGS VDD ID I VD VDD RD ID VGS Vt VOV VOV 2Ik n W L Figure 5.56 Basic structure of the circuit used to realize single-stage, discrete-circuit MOS amplifier configurations.
5.8 Discrete-Circuit MOS Amplifiers 317 To determine the terminal characteristics of the CS amplifier—that is, its input resistance, voltage gain, and output resistance—we replace the MOSFET with its small-signal model.
The resulting circuit is shown in Fig. 5.57(b).
We observe that the only difference between this circuit and the stripped-down version studied in Section 5.6.3 (Fig. 5.45) is that here we have the bias resistance . Since appears across the input terminals of the amplifier, the input resistance will no longer be infinite, rather To keep high, a large value of (in the megohm range) is usually selected. The finite will affect the overall voltage gain which becomes (5.101) Finally, to encourage the reader to do the analysis directly on the circuit diagram, with the MOSFET model used implicitly, we show some of the analysis on the circuit in Fig. 5.57(a).
Figure 5.57 (a) Common-source amplifier based on the circuit of Fig. 5.56. (b) Equivalent circuit of the amplifier for small-signal analysis.
(a) VSS VDD CC1 CS Rsig vsig vo vi RL Ro 0 V CC2 I ii 0 RG Rin vgs = vi RD vd (0 V) (b) RG S Rsig vsig ig 0 G ii gmvgs Rin RG Ro = RD ro vi vgs ro RD D RL vo = gm vgs (RD RL ro) RG RG Rin RG = Rin RG Rin Gv Gv RG RG Rsig + --------------------- gm RD RL ro || || ( ) – = 318 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.8.3 The Common-Source Amplifier with a Source Resistance As demonstrated in Section 5.6.4, a number of beneficial results can be obtained by connecting a resistance in the source lead of the transistor in the CS amplifier. This is shown in Fig.
5.58(a), where is, of course, unbypassed. Figure 5.58(b) shows the small-signal equivalent-circuit model. Observe that the only difference between this circuit and the simplified version studied in Section 5.6.4 is the bias resistance that appears across the input terminals and makes finite. This will in turn affect the overall voltage gain , which becomes (5.102) Finally, note that much of the analysis is shown both on the actual circuit in Fig. 5.58(a) and on the equivalent circuit in Fig. 5.58(b).
5.8.4 The Common-Gate (CG) Amplifier Figure 5.59(a) shows a CG amplifier obtained from the circuit of Fig. 5.56. Observe that since both the dc and ac voltages at the gate are to be zero, we have connected the gate directly to ground, thus eliminating resistor RG altogether. Coupling capacitors CC1 and CC2 perform simi-lar functions to those in the CS circuit. The small-signal, equivalent circuit model of the CG amplifier is shown in Fig. 5.59(b).
We note that this circuit is identical to the equivalent circuit of the stripped-down version of the CG amplifier, in Fig. 5.48(b). Thus the analysis performed and the results obtained in Section 5.6.5 apply directly here. A substantial portion of the analysis is also shown in Fig. 5.59.
5.38 Consider a CS amplifier based on the circuit analyzed in Exercise 5.37. Specifically, refer to the results of that exercise shown in Fig. E5.37. Find Rin, Avo, and Ro, both without and with ro taken into account. Then calculate the overall voltage gain Gv, with ro taken into account, for the case Rsig = 100 kΩ and RL = 15 kΩ. If vsig is a 0.4-V peak-to-peak sinusoid, what output signal vo results?
Ans. Without ro: Rin = 4.7 MΩ, Avo = −15 V/V, and Ro = 15 kΩ; with ro: Rin = 4.7 MΩ, Avo = −13.6 V/V, and Ro = 13.6 kΩ; ; vo is a 2.8-V peak-to-peak sinusoid superimposed on a dc drain voltage of +2.5 V.
Gv 7 V/V – = EXERCISE Rs Rs RG Rin Gv Gv RG RG Rsig + --------------------- RD RL || 1 gm ⁄ Rs + -------------------------– = 5.39 In Exercise 5.38 we applied an input signal of 0.4 V peak-to-peak, which resulted in an output sig-nal of the CS amplifier of 2.8 V peak-to-peak. Assume that for some reason we now have an input signal three times as large as before (i.e., 1.2 V p-p) and that we wish to modify the circuit to keep the output signal level unchanged. What value should we use for Rs?
Ans. 2.15 kΩ EXERCISE 5.8 Discrete-Circuit MOS Amplifiers 319 Figure 5.58 (a) Common-source amplifier with a resistance RS in the source lead. (b) Small-signal equiv-alent circuit with ro neglected.
(a) vi 0 0 V (0 V) 0 VSS VDD CC1 Rsig vsig I RG RD Rs CS vo vd RL CC2 Ro RD Rin RG vi vi Rs 1 gm 1gm vi Rs 1 gm (b) id i RG S Rs RD RL Rsig vsig G D 0 i i 1 gm Rin RG vi vgs vo vd Ro RD i vi Rs 1 gm vi Rs 1 gm 320 Chapter 5 MOS Field-Effect Transistors (MOSFETs) (a) VSS VDD CC2 I RD CC1 Rsig vsig RL vo vd Ro RD ii ii 0 1 gm Rin vi 1 gm vsig ii gmvi Rsig 1 gm (0 V) (b) id i RD RL Rsig vsig ii S D i i 1 gm G 1 gm Rin vi vo vd Ro RD Figure 5.59 (a) A common-gate amplifier based on the circuit of Fig. 5.56. (b) A small-signal equivalent circuit of the amplifier in (a).
5.40 Consider a CG amplifier designed using the circuit of Fig. 5.56, which is analyzed in Exercise 5.37 with the analysis results displayed in Fig. E5.37. Note that and RD = 15 kΩ. Find Rin, Ro, Avo, Av, and Gv for RL = 15 kΩ and Rsig = 50 Ω. What will the overall voltage gain become for Rsig = 1 kΩ? 10 kΩ? 100 kΩ?
Ans. 1 kΩ, 15 kΩ, , , ; ; ; gm = 1 mA/V +15 V/V +7.5 V/V +7.1 V/V +3.75 V/V 0.68 V/V 0.07 V/V EXERCISE 5.8 Discrete-Circuit MOS Amplifiers 321 5.8.5 The Source Follower Figure 5.60(a) shows a common-drain amplifier based on the circuit of Fig. 5.56. Since the drain is to function as a signal ground, there is no need for resistor RD, and it has therefore been eliminated. The input signal is coupled via capacitor CC1 to the MOSFET gate, and the output signal at the MOSFET source is coupled via capacitor CC2 to a load resistor RL. Replacing the MOSFET with its T model results in the equivalent circuit in Fig. 5.60(b).
We note that the only difference between this circuit and that in Fig. 5.50(b) is the bias resis-tance that appears across the input terminals. Thus, here too, the input resistance will no longer be infinite and the overall voltage gain will become (5.103) Figure 5.60 (a) A source-follower amplifier. (b) Small-signal, equivalent-circuit model.
RG Gv RG RG Rsig + ---------------------RL ro || ( ) RL ro || ( ) 1 gm ⁄ + ----------------------------------------= (b) RG S RL ro Rsig vsig 0 G D vo i i 1 gm Rin RG vi Ro = gm 1 ro (a) VSS VDD CC1 vo RL CC2 Rsig vsig Rin Ro I vi RG 322 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.8.6 The Amplifier Frequency Response Thus far, we have assumed that the gain of MOS amplifiers is constant, independent of the frequency of the input signal. This would imply that MOS amplifiers have infinite band-width, which of course is not true. To illustrate, we show in Fig. 5.61 a sketch of the mag-nitude of the gain of a common-source amplifier versus frequency. Observe that there is indeed a wide frequency range over which the gain remains almost constant. This obvi-ously is the useful frequency range of operation for the particular amplifier. Thus far, we have been assuming that our amplifiers are operating in this frequency band, called the midband.
Figure 5.61 indicates that at lower frequencies, the magnitude of amplifier gain falls off.
This is because the coupling and bypass capacitors no longer have low impedances. Recall that we assumed that their impedances were small enough to act as short circuits. Although this can be true at midband frequencies, as the frequency of the input signal is lowered, the reactance of each of these capacitors becomes significant, and it can be shown that this results in the overall voltage gain of the amplifier decreasing.
Figure 5.61 indicates also that the gain of the amplifier falls off at the high-frequency end. This is due to the internal capacitive effects in the MOSFET. We have had a brief intro-duction to such capacitive effects in our study of the pn junction in Chapter 3. In Chapter 9, we shall study the internal capacitive effects of the MOSFET and will augment the hybrid-model with capacitances that model these effects.
We will undertake a detailed study of the frequency response of MOS amplifiers in Chapter 9. For the time being, however, it is important for the reader to realize that for every MOS amplifier there is a finite band over which the gain is almost constant. The boundaries of this useful frequency band or midband, are the two frequencies and , at which the gain drops by a certain number of decibels (usually 3 dB) below its value at midband. As indicated in Fig. 5.61, the amplifier bandwidth, or 3-dB bandwidth, is defined as the differ-ence between the lower ( ) and the upper or higher ( ) 3-dB frequencies: (5.104) and since usually , (5.105) 1 jωC ⁄ π fL fH fL fH BW fH fL – = fL fH BW fH 5.41 Consider a source follower such as that in Fig. 5.60(a) designed on the basis of the circuit of Fig. 5.56, the results of whose analysis are displayed in Fig. E5.37. Specifically, note that and ro = 150 kΩ. Let Rsig = 1 MΩ and RL = 15 kΩ. (a) Find Rin, Avo, Av, and Ro without and with ro taken into account. (b) Find the overall small-signal voltage gain Gv with ro taken into account.
Ans. (a) Rin = 4.7 MΩ; (without ro), (with ro); Av = 0.938 (without ro), 0.932 V (with ro); Ro = 1 kΩ (without ro), 0.993 kΩ (with ro); (b) gm = 1 mA/V Avo = 1 V/V 0.993 V/V 0.768 V/V EXERCISE 5.9 The Body Effect and Other Topics 323 A figure of merit for the amplifier is its gain–bandwidth product, defined as (5.106) where is the magnitude of the amplifier gain in the midband. It will be seen in Chapter 9 that in amplifier design it is usually possible to trade off gain for bandwidth. One way to accom-plish this, for instance, is by including resistance in the source of the CS amplifier.
5.9 The Body Effect and Other Topics11 In this section we briefly consider a number of important though secondary issues.
5.9.1 The Role of the Substrate—The Body Effect In many applications the source terminal is connected to the substrate (or body) terminal B, which results in the pn junction between the substrate and the induced channel (review Fig.
5.5) having a constant zero (cutoff) bias. In such a case the substrate does not play any role in circuit operation and its existence can be ignored altogether.
In integrated circuits, however, the substrate is usually common to many MOS transis-tors. In order to maintain the cutoff condition for all the substrate-to-channel junctions, the substrate is usually connected to the most negative power supply in an NMOS circuit (the most positive in a PMOS circuit). The resulting reverse-bias voltage between source and body (VSB in an n-channel device) will have an effect on device operation. To appreciate this fact, consider an NMOS transistor and let its substrate be made negative relative to the Figure 5.61 A sketch of the frequency response of a CS amplifier delineating the three frequency bands of interest.
11This section can be omitted in a first reading with little or no loss of continuity. Some of this material, however, will be required for the study of digital circuits in Chapter 13.
Vo (dB) Low-frequency band Vsig Midband • All capacitances can be neglected • Gain falls off due to the internal capacitive effects of the MOSFET High-frequency band • Gain falls off due to the effect of CC1, CS, and CC2 3 dB 20 log |AM| (dB) fL fH f (Hz) GB AM BW = AM Rs 324 Chapter 5 MOS Field-Effect Transistors (MOSFETs) source. The reverse-bias voltage will widen the depletion region (refer to Fig. 5.2). This in turn reduces the channel depth. To return the channel to its former state, vGS has to be increased.
The effect of VSB on the channel can be most conveniently represented as a change in the threshold voltage Vt. Specifically, it has been shown that increasing the reverse substrate bias voltage VSB results in an increase in Vt according to the relationship (5.107) where Vt 0 is the threshold voltage for VSB = 0; φf is a physical parameter with (2φf) typically 0.6 V; γ is a fabrication-process parameter given by (5.108) where q is the electron charge (1.6 × 10−19 C), NA is the doping concentration of the p-type sub-strate, and εs is the permittivity of silicon (11.7ε0 = 11.7 × 8.854 × 10−14 = 1.04 × 10−12 F/cm).
The parameter γ has the dimension of and is typically 0.4 V1/2. Finally, note that Eq. (5.107) applies equally well for p-channel devices with VSB replaced by the reverse bias of the substrate, VBS (or, alternatively, replace VSB by ) and note that γ is negative. Also, in evaluating γ, NA must be replaced with ND, the doping concentration of the n well in which the PMOS is formed. For p-channel devices, 2φf is typically 0.75 V, and γ is typically −0.5 V1/2.
Equation (5.107) indicates that an incremental change in VSB gives rise to an incremental change in Vt , which in turn results in an incremental change in iD even though vGS might have been kept constant. It follows that the body voltage controls iD; thus the body acts as another gate for the MOSFET, a phenomenon known as the body effect. Here we note that the parameter γ is known as the body-effect parameter.
5.9.2 Modeling the Body Effect As mentioned above the body effect occurs in a MOSFET when the source is not tied to the substrate (which is always connected to the most negative power supply in the integrated circuit for n-channel devices and to the most positive for p-channel devices). Thus the sub-strate (body) will be at signal ground, but since the source is not, a signal voltage vbs devel-ops between the body (B) and the source (S). The substrate then acts as a “second gate” or a backgate for the MOSFET. Thus the signal vbs gives rise to a drain-current component, which we shall write as gmbvbs, where gmb is the body transconductance, defined as (5.109) Recalling that iD depends on vBS through the dependence of Vt on VBS, we can show that Vt Vt0 γ 2φf VSB + 2φf – [ ] + = γ 2qNAεs Cox ----------------------= V V SB 5.42 An NMOS transistor has Vt0 = 0.8 V, 2φf = 0.7 V, and γ = 0.4 V1/2. Find Vt when VSB = 3 V.
Ans. 1.23 V EXERCISE gmb ∂iD ∂vBS -----------≡ vGS constant = vDS constant = 5.9 The Body Effect and Other Topics 325 gmb = χgm (5.110) where (5.111) Typically the value of χ lies in the range 0.1 to 0.3.
Figure 5.62 shows the MOSFET model augmented to include the controlled source gmbvbs that models the body effect. Ideally, this is the model to be used whenever the source is not connected to the substrate. It has been found, however, that except in some very particular situations, the body effect can generally be ignored in the initial, pencil-and-paper design of MOSFET amplifiers.
Finally, although the analysis above was performed on a NMOS transistor, the results and the equivalent circuit of Fig. 5.62 apply equally well to PMOS transistors, except for using |VGS|, |Vt|, |VOV|, |VA|, |VSB|, |γ|, and |λ| and replacing with in the appropriate formula.
5.9.3 Temperature Effects Both Vt and are temperature sensitive. The magnitude of Vt decreases by about 2 mV for every 1°C rise in temperature. This decrease in gives rise to a corresponding increase in drain current as temperature is increased. However, because decreases with temperature and its effect is a dominant one, the overall observed effect of a temperature increase is a decrease in drain current. This very interesting result is put to use in applying the MOSFET in power circuits (Chapter 11).
5.9.4 Breakdown and Input Protection As the voltage on the drain is increased, a value is reached at which the pn junction between the drain region and substrate suffers avalanche breakdown (see Section 3.5.3). This break-down usually occurs at voltages of 20 V to 150 V and results in a somewhat rapid increase in current (known as a weak avalanche).
Figure 5.62 Small-signal, equivalent-circuit model of a MOSFET in which the source is not connected to the body.
D G B S (a) D (b) χ ∂Vt ∂VSB -----------≡ γ 2 2φf VSB + -----------------------------= kn ′ kp ′ k′ Vt k′ 326 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Another breakdown effect that occurs at lower voltages (about 20 V) in modern devices is called punch-through. It occurs in devices with relatively short channels when the drain voltage is increased to the point that the depletion region surrounding the drain region extends through the channel to the source. The drain current then increases rapidly. Normally, punch-through does not result in permanent damage to the device. Yet another kind of breakdown occurs when the gate-to-source voltage exceeds about 30 V. This is the breakdown of the gate oxide and results in permanent damage to the device. Although 30 V may seem high, it must be remembered that the MOSFET has a very high input resistance, and a very small input capacitance, and thus small amounts of static charge accumulating on the gate capacitor can cause its breakdown voltage to be exceeded.
To prevent the accumulation of static charge on the gate capacitor of a MOSFET, gate-protection devices are usually included at the input terminals of MOS integrated circuits. The protection mechanism invariably makes use of clamping diodes.
5.9.5 Velocity Saturation At high longitudinal electric fields, the drift velocity of charge carriers in the channel reaches an upper limit (approximately 107 cm/s for electrons and holes in silicon). This effect, which in modern very-short-channel devices can occur for vDS lower than 1 V, is called velocity saturation. It can be shown be that when velocity saturation occurs, the cur-rent iD will no longer be related to vGS by the square-law relationship. Rather, iD becomes lin-early dependent on vGS and the transconductance gm becomes constant and independent of vGS. In Chapter 13, we shall consider velocity saturation in our study of deep submicron (i.e., L < 0.25 μm) CMOS digital circuits.
5.9.6 The Depletion-Type MOSFET We conclude this section with a brief discussion of another type of MOSFET, the deple-tion-type MOSFET. Its structure is similar to that of the enhancement-type MOSFET with one important difference: The depletion MOSFET has a physically implanted channel. Thus an n-channel depletion-type MOSFET has an n-type silicon region con-necting the n+ source and the n+ drain regions at the top of the p-type substrate. Thus if a voltage vDS is applied between drain and source, a current iD flows for vGS = 0. In other words, there is no need to induce a channel, unlike the case of the enhancement MOSFET.
The channel depth and hence its conductivity can be controlled by vGS in exactly the same manner as in the enhancement-type device. Applying a positive vGS enhances the chan-nel by attracting more electrons into it. Here, however, we also can apply a negative vGS, which causes electrons to be repelled from the channel, and thus the channel becomes shal-lower and its conductivity decreases. The negative vGS is said to deplete the channel of its charge carriers, and this mode of operation (negative vGS) is called depletion mode. As the magnitude of vGS is increased in the negative direction, a value is reached at which the chan-nel is completely depleted of charge carriers and iD is reduced to zero even though vDS may be still applied. This negative value of vGS is the threshold voltage of the n-channel depletion-type MOSFET.
The description above suggests (correctly) that a depletion-type MOSFET can be oper-ated in the enhancement mode by applying a positive vGS and in the depletion mode by 5.9 The Body Effect and Other Topics 327 applying a negative vGS. This is illustrated in Fig. 5.63, which shows both the circuit symbol for the depletion NMOS transistor (Fig. 5.63a) and its iD–vGS characteristic. Observe that here the threshold voltage Vtn is negative. The iD–vDS characteristics (not shown) are similar to those for the enhancement-type MOSFET except for the negative Vtn. Finally, note that the device symbol denotes the existing channel via the shaded area next to the vertical line. Depletion-type MOSFETs can be fabricated on the same IC chip as enhancement-type devices, resulting in circuits with improved characteristics, as will be shown in a later chapter.
Figure 5.63 The circuit symbol (a) and the iD–vGS characteristic in saturation; (b) for an n-channel depletion-type MOSFET.
vGS S G iG 0 iD vDS D (a) IDSS vGS vDS Vt vGS Vt iD Depletion mode Enhancement mode (b) 0 5.43 For a depletion-type NMOS transistor with Vt = −2 V and , find the minimum vDS required to operate in the saturation region when vGS = +1 V. What is the corresponding value of iD?
Ans. 3 V; 9 mA kn ′ W L ⁄ ( ) = 2 mA/V2 EXERCISE 328 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Summary The enhancement-type MOSFET is currently the most widely used semiconductor device. It is the basis of CMOS technology, which is the most popular IC fabri-cation technology at this time. CMOS provides both n-channel (NMOS) and p-channel (PMOS) transistors, which increases design flexibility. The minimum MOS-FET channel length achievable with a given CMOS pro-cess is used to characterize the process. This figure has been continually reduced and is currently 45 nm.
The overdrive voltage, , is the key quantity that governs the operation of the MOSFET. For the MOSFET to operate in the saturation region, which is the region for amplifier application, , and the resulting (for NMOS; replace with for PMOS). If , the MOSFET operates in the triode region, which together with cutoff is used for operating the MOSFET as a switch.
Tables 5.1 and 5.2 provide summaries of the conditions and relationships that describe the operation of NMOS and PMOS transistors, respectively.
In saturation, shows some linear dependence on as a result of the change in channel length. This channel-length modulation phenomenon becomes more pro-nounced as L decreases. It is modeled by ascribing an out-put resistance to the MOSFET model.
Although the effect of on the operation of discrete-cir-cuit MOS amplifiers is small, that is not the case in IC amplifiers (Chapter 7).
The essence of the use of the MOSFET as an amplifier is that in saturation controls in the manner of a voltage-controlled current source. When the device is dc biased in the saturation region and the signal is kept small, the operation of the MOSFET becomes al-most linear.
A systematic procedure to analyze a MOS amplifier cir-cuit consists of replacing the MOSFET with one of its small-signal, equivalent-circuit models (Refer to Table 5.3). DC voltage sources are replaced by short circuits, and dc current sources by open circuits. The analysis is then performed on the resulting equivalent circuit.
In cases where a resistance is connected in series with the source lead of the MOSFET, the T model is the most con-venient to use.
The three basic configurations of MOS amplifiers are shown in Fig. 5.43 (without the bias arrangements).
Their characteristic parameter values are provided in Table 5.4.
The CS amplifier has (ideally) infinite input resistance and a reasonably high gain but a rather high output resis-tance and a limited high-frequency response. It is used to obtain most of the gain in a cascade amplifier.
Adding a resistance in the source lead of the CS am-plifier can lead to beneficial results.
The CG amplifier has a low input resistance and thus it alone has limited and specialized applications. Howev-er, its excellent high-frequency response makes it at-tractive in combination with the CS amplifier (Chapters 7 and 9).
The source follower has (ideally) infinite input resis-tance, a voltage gain lower than but close to unity, and a low output resistance. It is employed as a voltage buffer and as the output stage of a multistage amplifier.
A key step in the design of transistor amplifiers is to bias the transistor to operate at an appropriate point in the sat-uration region. A good bias design ensures that the param-eters of the bias point, ID, V OV, and V DS, are predictable and stable, and do not vary by a large amount when the tran-sistor is replaced by another of the same type.
As evidenced by the example circuits given in Section 5.8, discrete-circuit MOS amplifiers utilize large cou-pling and bypass capacitors. As will be seen in Chapter 7, this is not the case in IC amplifiers.
The depletion-type MOSFET has an implanted chan-nel and thus can be operated in either the depletion or enhancement modes. It is characterized by the same equations used for the enhancement device except for having a negative Vt (positive Vt for depletion PMOS transistors).
vOV vGS Vt – ≡ vDS vOV ≥ iD 1 2 --μnCox W/L ( )vOV 2 = μn μp vDS vOV < iD vDS ro VA ID ⁄ = ro vGS iD vgs Rs Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multisim sim-ulations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 5.1: Device Structure and Physical Operation 5.1 MOS technology is used to fabricate a capacitor, utiliz-ing the gate metallization and the substrate as the capacitor electrodes. Find the area required per 1-pF capacitance for oxide thickness ranging from 2 nm to 10 nm. For a square plate capacitor of 10 pF, what dimensions are needed?
5.2 Calculate the total charge stored in the channel of an NMOS transistor having fF/μm2, L = 0.25 μm, and W = 2.5 μm, and operated at V and V.
5.3 Use dimensional analysis to show that the units of the pro-cess transconductance parameter are A/V2. What are the dimensions of the MOSFET transconductance parameter kn?
5.4 An NMOS transistor that is operated with a small is found to exhibit a resistance . By what factor will change in each of the following situations?
(a) is doubled.
(b) The device is replaced with another fabricated in the same technology but with double the width.
(c) The device is replaced with another fabricated in the same technology but with both the width and length doubled.
(d) The device is replaced with another fabricated in a more advanced technology for which the oxide thickness is halved and similarly for W and L (assume μn remains unchanged).
D 5.5 An NMOS transistor fabricated in a technology for which μA/V2 and V is required to oper-ate with a small as a variable resistor ranging in value from 200 to 1 k . Specify the range required for the control volt-age and the required transistor width W. It is required to use the smallest possible device, as limited by the minimum channel length of this technology ( μm) and the maximum allowed voltage of 1.8 V.
5.6 Sketch a set of characteristic curves for an NMOS transistor operating with a small (in the manner shown in Fig. 5.4). Let the MOSFET have mA/V2 and V. Sketch and clearly label the graphs for , 1.0, 1.5, 2.0, and 2.5 V. Let be in the range 0 to 50 mV. Give the value of obtained for each of the five values of . Although only a sketch, your diagram should be drawn to scale as much as possible.
D 5.7 An n-channel MOS device in a technology for which oxide thickness is 20 nm, minimum channel length is 1 μm, and Vt = 0.8 V operates in the triode region, with small vDS and with the gate−source voltage in the range 0 V to +5 V. What device width is needed to ensure that the minimum available resistance is 1 kΩ?
5.8 Consider an NMOS transistor operating in the triode region with an overdrive voltage . Find an expression for the incremental resistance Give the values of in terms of and for , 0.5 , 0.8 , and .
5.9 An NMOS transistor with mA/V2 and V is operated with V. At what value of does the transistor enter the saturation region? What value of is obtained in saturation? 5.10 Consider a CMOS process for which Lmin = 0.25 μm, tox = 6 nm, μn = 460 cm2/V⋅s, and Vt = 0.5 V.
(a) Find Cox and (b) For an NMOS transistor with W/L = 15 μm/0.25 μm, calculate the values of V OV, V GS, and V DSmin needed to operate the transistor in the saturation region with a dc current ID = 0.8 mA.
(c) For the device in (b), find the value of VOV and VGS required to cause the device to operate as a 500-Ω resistor for very small vDS.
5.11 A p-channel MOSFET with a threshold voltage V has its source connected to ground.
(a) What should the gate voltage be for the device to operate with an overdrive voltage of V? (b) With the gate voltage as in (b), what is the highest volt-age allowed at the drain while the device operates in the sat-uration region?
(c) If the drain current obtained in (b) is 1 mA, what would the current be for mV and for 5.12 With the knowledge that μp 0.4μn, what must be the relative width of n-channel and p-channel devices if they are to have equal drain currents when operated in the saturation mode with overdrive voltages of the same magnitude?
Cox 6 = VOV 0.5 = VDS 0 = k′ n vDS rDS rDS VOV k′ n 400 = Vt 0.4 = vDS Ω Ω VGS Lmin 0.18 = iD vDS – vDS kn 5 = Vt 0.5 = VGS 0.5 = VDS rDS VGS kn ′ = 100 μA/V 2 , VOV rds 1 ∂iD ∂vDS -----------⁄ vDS VDS = ≡ rds kn VOV VDS 0 = VOV VOV VOV kn 1 = Vt 1 = VGS 2.5 = VDS ID kn ′ .
Vtp 0.7 – = V OV 0.5 = VD 10 – = VD 2V?
– = PROBLEMS CHAPTER 5 PR OBLE MS 330 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.13 An n-channel device has Vt = 0.8 V, and W/L = 20. The device is to operate as a switch for small vDS, utilizing a control voltage vGS in the range 0 V to 5 V.
Find the switch closure resistance, rDS, and closure voltage, VDS, obtained when vGS = 5 V and iD = 1 mA. Recalling that μp 0.4μn, what must W/L be for a p-channel device that provides the same performance as the n-channel device in this application?
5.14 Consider an n-channel MOSFET with tox = 9 nm, μn = 500 cm2/V⋅s, Vt = 0.7 V, and W/L = 10. Find the drain cur-rent in the following cases: (a) vGS = 5 V and vDS = 1 V (b) vGS = 2 V and vDS = 1.3 V (c) vGS = 5 V and vDS = 0.2 V (d) vGS = vDS = 5 V 5.15 This problem illustrates the central point in the elec-tronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moore’s law.
The table below shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and are scaled by the same factor. The power supply utilized is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons, cannot be scaled similarly.
Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of obtained with ; row 10 asks for the power dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-μm technology (n).
kn ′ = 50 μA/V 2, tox VDD Vt ID VGS VDS VDD = = P VDDID = 1 L (μm) 0.5 0.25 0.18 0.13 2 (nm) 10 3 (fF/μm2) 4 (μA/V2) (μn = 500 cm2/ ) 5 (mA/V2) for W/L = 10 6 Device area, A (μm2) 7 (V) 5 8 (V) 0.7 0.5 0.4 0.4 9 (mA) For 10 P (mW) 11 P/A (mW/ μm2) 12 Devices per chip n tox Cox k′ n V s ⋅ kn VDD Vt ID VGS VDS VDD = = Problems 331 CHAPTER 5 P ROBL EMS Section 5.2: Current–Voltage Characteristics In the following problems, when λ is not specified, assume it is zero.
5.16 Show that when channel-length modulation is neglected (i.e., ), plotting versus for various values of , and plotting versus for , results in universal representation of the and char-acteristics of the NMOS transistor. That is, the resulting graphs are both technology and device independent. Further-more, these graphs apply equally well to the PMOS transistor by a simple relabeling of variables. (How?) What is the slope at of each of the versus graphs? For the versus graph, find the slope at a point vOV = VOV.
5.17 An NMOS transistor having Vt = 1 V is operated in the triode region with vDS small. With VGS = 1.5 V, it is found to have a resistance rDS of 1 kΩ. What value of VGS is required to obtain rDS = 200 Ω? Find the corresponding resistance values obtained with a device having twice the value of W.
5.18 A particular enhancement MOSFET for which Vt = 0.5 V and (W/L) = 0.1 mA/V2 is to be operated in the saturation region. If iD is to be 12.5 μA, find the required vGS and the minimum required vDS. Repeat for iD = 50 μA.
5.19 A particular n-channel enhancement MOSFET is measured to have a drain current of 0.4 mA at VGS = VDS = 2 V and of 0.1 mA at VGS = VDS = 1.5 V. What are the values of and Vt for this device?
D 5.20 For a particular IC-fabrication process, the trans-conductance parameter = 400 μA/V2, and Vt = 0.4 V. In an application in which vGS = vDS = Vsupply = 1.8 V, a drain cur-rent of 2 mA is required of a device of minimum length of 0.18 μm. What value of channel width must the design use?
5.21 An NMOS transistor, operating in the linear-resistance region with vDS = 0.1 V, is found to conduct 60 μA for vGS = 2 V and 160 μA for vGS = 4 V. What is the apparent value of threshold voltage Vt? If = 50 μA/V2, what is the device W/L ratio? What current would you expect to flow with vGS = 3 V and vDS = 0.15 V? If the device is oper-ated at vGS = 3 V, at what value of vDS will the drain end of the MOSFET channel just reach pinch-off, and what is the corresponding drain current?
5.22 For an NMOS transistor, for which Vt = 0.5 V, operat-ing with vGS in the range of 0.8 V to 1.8 V, what is the larg-est value of vDS for which the channel remains continuous?
5.23 An NMOS transistor, fabricated with W = 100 μm and L = 5 μm in a technology for which = 50 μA/V2 and Vt = 1 V, is to be operated at very low values of vDS as a linear resistor. For vGS varying from 1.1 V to 11 V, what range of resistor values can be obtained? What is the available range if (a) the device width is halved?
(b) the device length is halved?
(c) both the width and length are halved?
5.24 When the drain and gate of a MOSFET are connected together, a two-terminal device known as a “diode-connected transistor” results. Figure P5.24 shows such devices obtained from MOS transistors of both polarities. Show that (a) the i–v relationship is given by (b) the incremental resistance r for a device biased to oper-ate at is given by Figure P5.24 5.25 For the circuit in Fig. P5.25, sketch versus for varying from 0 to . Clearly label your sketch.
5.26 For the circuit in Fig. P5.26, find an expression for in terms of . Sketch and clearly label a graph for versus .
λ 0 = iD kn ⁄ vDS vOV iD kn ⁄ vOV vDS vOV ≥ iD vDS – iD vGS – vDS 0 = iD kn ⁄ vDS iD kn ⁄ vGS kn ′ kn kn ′ kn ′ kn ′ i 1 2 ---k′ W L ----- v Vt – ( ) 2 = v Vt VOV + = r 1 ∂i ∂v ------≡ 1 k′W L -----VOV ⎝ ⎠ ⎛ ⎞ = i v (a) i v (b) iD vS vS VDD iD VDD vS Figure P5.25 vDS iD vDS iD CHAPTER 5 PR OBLE MS 332 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.27 The table below lists 10 different cases labeled (a) to (j) for operating an NMOS transistor with V. In each case the voltages at the source, gate, and drain (relative to the circuit ground) are specified. You are required to com-plete the table entries. Note that if you encounter a case for which is negative, you should exchange the drain and source before solving the problem. You can do this because the MOSFET is a symmetric device.
5.28 The NMOS transistor in Fig. P5.28 has V and . Sketch and clearly label versus with varying in the range 0 to V. Give equations for the various portions of the resulting graph.
5.29 Fig. P5.29 shows two NMOS transistors operating in saturation at equal and .
(a) If the two devices are matched except for a maximum possible mismatch in their W/L ratios of 2%, what is the maximum resulting mismatch in the drain currents?
(b) If the two devices are matched except for a maximum possible mismatch in their values of 10 mV, what is the maximum resulting mismatch in the drain currents? Assume that the nominal value of is 1 V.
5.30 For a particular MOSFET operating in the satura-tion region at a constant vGS, iD is found to be 1 mA for iD vDS Figure P5.26 1V iD vG Figure P5.28 Vt 1 = vDS Vt 0.4 = kn ′ W L ⁄ ( ) 1 mA V2 ⁄ = iD vG vG +1.8 VGS VDS Vt Vt ID1 ID2 2V 5V Q1 Q2 Figure P5.29 Case Voltage (V) VS VG VD VGS VOV VDS Region of operation a b c d e f g h i j +1.0 +1.0 +2.0 +1.0 +2.5 +2.0 +1.0 +2.5 +1.5 +1.0 +1.5 0 0 +2.5 1.0 +1.0 +1.0 +1.0 1.0 – 0 0 1.5 – 0 0 1.0 – 0 +1.0 +0.5 +2.0 +0.5 Problems 333 CHAPTER 5 P ROBL EMS vDS = 1 V and 1.05 mA for vDS = 2 V. What values of ro, VA, and λ correspond?
5.31 A particular MOSFET has VA = 50 V. For operation at 0.1 mA and 1 mA, what are the expected output resistances?
In each case, for a change in vDS of 1 V, what percentage change in drain current would you expect?
D 5.32 In a particular IC design in which the standard chan-nel length is 2 μm, an NMOS device with W/L of 5 operat-ing at 100 μA is found to have an output resistance of 0.5 MΩ, about of that needed. What dimensional change can be made to solve the problem? What is the new device length? The new device width? The new W/L ratio? What is VA for the standard device in this IC? The new device?
D 5.33 For a particular n-channel MOS technology, in which the minimum channel length is 1 μm, the associated value of λ is 0.02 V−1. If a particular device for which L is 3 μm operates at vDS = 1 V with a drain current of 80 μA, what does the drain current become if vDS is raised to 5 V?
What percentage change does this represent? What can be done to reduce the percentage by a factor of 2?
5.34 An NMOS transistor is fabricated in a 0.8-μm pro-cess having = 130 μA/V2 and = 20 V/μm of channel length. If L = 1.6 μm and W = 16 μm, find VA and λ. Find the value of ID that results when the device is operated with an overdrive voltage of 0.5 V and VDS = 2 V. Also, find the value of ro at this operating point. If VDS is increased by 1 V, what is the corresponding change in ID?
5.35 If in an NMOS transistor, both W and L are quadru-pled and is halved, by what factor does change?
D 5.36 Consider the circuit in Fig. P5.29 with both transistors perfectly matched but with the dc voltage at the drain of lowered to V. If the two drain currents are to be matched within 1% (i.e., the maximum difference allowed between the two currents is 1%), what is the minimum required value of ? If the technology is specified to have V/μm, what is the minimum channel length the designer must use?
5.37 Complete the missing entries in the following table, which describes characteristics of suitably biased NMOS transistors: 5.38 An enhancement PMOS transistor has = Vt = −1.5 V, and λ = −0.02 V−1. The gate is con-nected to ground and the source to +5 V. Find the drain cur-rent for vD = +4 V, +1.5 V, 0 V, and −5 V.
5.39 A p-channel transistor for which and 50 V operates in saturation with 4 V, and iD = 3 mA. Find corresponding signed values for vGS, vSG, vDS, vSD, Vt, VA, λ, and (W/L).
5.40 The table below lists the terminal voltages of a PMOS transistor in six cases, labeled a, b, c, d, e, and f. The transis-tor has . Complete the table entries.
1 4 ---kn ′ VA ′ VOV ro MOS 1 2 3 4 (V−1) 0.01 VA (V) 10 200 ID (mA) 1 0.1 ro (kΩ) 30 100 1000 Q1 +2 VA V′ A 100 = λ kp ′ W/L ( ) 80 μA/V 2, Vt = 1 V VA = vGS 3 V, vDS = = kp ′ Vtp 1 V – = VS VG VD VSG |VOV| VSD Region of operation a 0 b 0 c 0 0 d 0 e 0 f 0 +2 +2 +2 +1 +2 +2 +1 +2 +1.5 +2 +2 CHAPTER 5 PR OBLE MS 334 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.41 The PMOS transistor in Fig. P5.41 has V.
As the gate voltage is varied from V to 0 V, the transistor moves through all of its three possible modes of operation. Specify the value of at which the device changes modes of operation.
5.42 (a) Using the expression for iD in saturation and neglecting the channel-length modulation effect (i.e., let λ = 0), derive an expression for the per unit change in iD per °C in terms of the per unit change in per °C , the temperature coefficient of Vt in V/°C and VGS and Vt.
(b) If Vt decreases by 2 mV for every °C rise in temperature, find the temperature coefficient of that results in iD decreasing by 0.2%/°C when the NMOS transistor with Vt = 1 V is operated at VGS = 5 V.
5.43 Various NMOS and PMOS transistors, numbered 1 to 4, are measured in operation, as shown in the table at the bottom of the page. For each transistor, find the value of μCoxW/L and Vt that apply and complete the table, with V in volts, I in μA, and μCoxW/L in μA/V2.
5.44 All the transistors in the circuits shown in Fig. P5.44 have the same values of , W/L, and λ. Moreover, λ is negligibly small. All operate in saturation at ID = I and Find the voltages V1, V2, V3, and V4. If and I = 0.1 mA, how large a resistor can be inserted in series with each drain connection while main-taining saturation? What is the largest resistor that can be placed in series with each gate? If the current source I requires at least 0.5 V between its terminals to operate properly, what is the largest resistor that can be placed in series with each MOSFET source while ensuring saturated-mode operation of each transistor at ID = I? In the latter lim-iting situation, what do V1, V2, V3, and V4 become?
Vtp 0.5 – = vG +2.5 vG 1 V 2.5 V vG Figure P5.41 ∂iD iD ⁄ ( ) ∂T ⁄ [ ] kn ′ ∂kn ′ / kn ′ ( )/∂T [ ] ∂Vt ∂T ⁄ ( ), kn ′ Vt , k′ VGS VDS 1 V.
= = Vt 0.5 V = (a) Q1 V1 2.5 V I (b) V2 Q2 1 V 1.5 V 1 V I (c) Q3 V3 2.5 V I (d) V4 Q4 1.25 V 1.25 V I Figure P5.44 Case Transistor VS VG VD ID Type Mode μ CoxW/L Vt a 1 0 2 5 100 1 0 3 5 400 b 2 5 3 −4.5 50 2 5 2 −0.5 450 c 3 5 3 4 200 3 5 2 0 800 d 4 −2 0 0 72 4 −4 0 −3 270 Problems 335 CHAPTER 5 P ROBL EMS Section 5.3: MOSFET Circuits at DC Note: If λ is not specified, assume it is zero.
D 5.45 Design the circuit of Fig. 5.21 to establish a drain current of 0.25 mA and a drain voltage of 0 V. The MOSFET has Vt = 1 V, μnCox = 60 μA/V2, L = 3 μm, and W = 100 μm.
D 5.46 For the circuit in Fig. E5.10, assume that and are matched except for having different widths, and .
Let V, mA/V2, μm, μm, and .
(a) Find the value of R required to establish a current of 90 μA in .
(b) Find and so that operates at the edge of satura-tion with a current of 0.9 mA.
5.47 The transistor in the circuit of Fig. P5.47 has mA/V2, V, and . Show that oper-ation at the edge of saturation is obtained when the follow-ing condition is satisfied: 5.48 It is required to operate the transistor in the circuit of Fig. P5.47 at the edge of saturation with mA. If V, find the required value of .
D 5.49 The PMOS transistor in the circuit of Fig. P5.49 has Vt = −0.6 V, μpCox = 100 μA/V2, L = 0.25 μm, and λ = 0.
Find the values required for W and R in order to establish a drain current of 0.8 mA and a voltage VD of 1.5 V.
D 5.50 The NMOS transistors in the circuit of Fig. P5.50 have Vt = 0.5 V, μnCox = 250 μA/V2, λ = 0, and L1 = L2 = 0.25 μm. Find the required values of gate width for each of Q1 and Q2, and the value of R, to obtain the voltage and current values indicated.
.
D 5.51 The NMOS transistors in the circuit of Fig. P5.51 have Vt = 1 V, μnCox = 120 μA/V2, λ = 0, and L1 = L2 = L3 = 1 μm. Find the required values of gate width for each of Q1, Q2, and Q3 to obtain the voltage and current values indicated.
Q1 Q2 W1 W2 Vt 0.5 = k′ n 0.4 = L1 L2 0.36 = = W1 1.8 = λ 0 = Q1 W2 R2 Q2 kn′ 0.4 = Vt 0.5 = λ 0 = W L -----⎝ ⎠ ⎛ ⎞RD 1.5 kΩ = RD 1.8 V Figure P5.47 ID 1 = Vt 0.5 = RD Figure P5.49 2.5 V Figure P5.50 2.5 V 1.8 V 1.0 V 0.25 mA Figure P5.51 5 V 3.5 V 1.5 V 120 A CHAPTER 5 PR OBLE MS 336 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.52 Consider the circuit of Fig. 5.24(a). In Example 5.5 it was found that when Vt = 1 V and (W/L) = 1 mA/V2, the drain current is 0.5 mA and the drain voltage is +7 V. If the transistor is replaced with another having Vt = 2 V and (W/L) = 2 mA/V2, find the new values of ID and VD.
Comment on how tolerant (or intolerant) the circuit is to changes in device parameters.
D 5.53 Using an enhancement-type PMOS transistor with Vt = −1.5 V, (W/L) = 1 mA/V2, and λ = 0, design a circuit that resembles that in Fig. 5.24(a). Using a 10-V supply, design for a gate voltage of +6 V, a drain current of 0.5 mA, and a drain voltage of +5 V. Find the values of RS and RD.
5.54 The MOSFET in Fig. P5.54 has Vt = 0.5 V, = 400 μA/V2, and λ = 0. Find the required values of W/L and of R so that when vI = VDD = +1.8 V, rDS = 50 Ω, and vO = 50 mV.
5.55 In the circuits shown in Fig. P5.55, transistors are characterized by = 2 V, W/L = 1 mA/V2, and λ = 0.
(a) Find the labeled voltages V1 through V7.
(b) In each of the circuits, replace the current source with a resistor. Select the resistor value to yield a current as close to that of the current source as possible, while using resistors specified in the 1% table provided in Appendix G. Find the new values of V1 to V7.
5.56 For each of the circuits in Fig. P5.56, find the labeled node voltages. For all transistors, (W/L) = 0.5 mA/V2, Vt = 0.8 V, and λ = 0.
kn ′ kn ′ kp ′ kn ′ R vO vI VDD Figure P5.54 Vt k′ kn ′ (b) V3 10 V 1 mA (c) V4 V5 10 V 10 V 2 mA 2.5 k (d) 2 mA V6 V7 10 V Figure P5.55 (a) 10 V 4 k 2 mA V2 V1 10 V Problems 337 CHAPTER 5 P ROBL EMS 5.57 For each of the circuits shown in Fig. P5.57, find the labeled node voltages. The NMOS transistors have Vt = 1 V and W/L = 5 mA/V2.
5.58 For the PMOS transistor in the circuit shown in Fig. P5.58, W/L = 25, and For I = 100 μA, find the voltages VSD and VSG for R = 0, 10 kΩ, 30 kΩ, and 100 kΩ. For what value of R is VSD = VSG? VSD = VSG /2? VSD = VSG/10? 5 V V1 (a) 10 A 5 V V2 (b) 100 A 5 V 1 mA V3 (c) V4 (d) 10 A 1 mA V5 (e) 100 k V6 (f) 5 V 1 k V7 (g) 5 V 100 k (h) V8 5 V 5 V Figure P5.56 kn ′ Figure P5.57 (a) V2 V1 2.5 V 5 V Q1 Q2 2.5 V 1 k (b) V5 V4 V3 5 V Q1 Q2 1 k 1 k kp ′ = 8 μA/V2, Vtp 1 V.
= Figure P5.58 V R I SD VSG 10 V CHAPTER 5 PR OBLE MS 338 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5.59 For the circuits in Fig. P5.59, μnCox = 2.5 μpCox = 20 μA/V2, λ = 0, L = 10 μm, and W = 30 μm, unless otherwise specified. Find the labeled currents and voltages.
5.60 For the devices in the circuits of Fig. P5.60, 1 V, λ = 0, μnCox = 50 μA/V2, L = 1 μm, and W = 10 μm. Find V2 and I2. How do these values change if Q3 and Q4 are made to have W = 100 μm?
5.61 In the circuit of Fig. P5.61, transistors Q1 and Q2 have Vt = 1 V, and the process transconductance parameter Find V1, V2, and V3 for each of the following cases: (a) (b) Section 5.4: Applying the MOSFET in Amplifier Design 5.62 Consider the amplifier of Fig. 5.27(a) with V and with the MOSFET having V, mA/V2 and W/L = 40.
(a) Find the value of that will result in the segment AB of the VTC extending over the range to 2.5 V. (b) What are the corresponding values of ?
(c) Find which corresponds to . What is the MOSFET’s resistance at operating point C?
(d) If the amplifier is biased to operate at V, find and the voltage gain.
5.63 For the amplifier of Fig. 5.29(a) find an expression for the bias voltage at which the magnitude of voltage gain is at its largest value. What is the value of the gain? What is the maximum allowable signal swing at this bias point?
Comment on the practical suitability of this bias point.
5.64 Consider the amplifier of Fig. 5.29(a) for the case VDD = 5 V, RD = 24 kΩ, (W/L) = 1 mA/V2, and Vt = 1 V.
(a) Find the coordinates of the two end points of the satura-tion-region segment of the amplifier transfer characteristic, that is, points A and B on the sketch of Fig. 5.29(b).
Vt 1 V, = (a) 3 V V2 I1 3 V I3 (b) V4 3 V (c) I6 W V5 Figure P5.59 Vt = kn ′ = 100 μA/V2.
W/L ( )1 W/L ( )2 20 = = W/L ( )1 1.5 W/L ( )2 20 = = VDD 2.5 = Vt 0.5 = k′n 0.25 = 5 V V2 Q3 Q1 Q4 Q2 I2 Figure P5.60 Figure P5.61 V1 Q1 Q2 5 V 40 k V2 40 k V3 200 A RD vDS 0.5 = vGS vDS|C vGS VDD = rDS VGS 0.8 = VDS VGS kn ′ Problems 339 CHAPTER 5 P ROBL EMS (b) If the amplifier is biased to operate with an overdrive voltage VOV of 0.5 V, find the coordinates of the bias point Q on the transfer characteristic. Also, find the value of ID and of the incremental gain Av at the bias point.
(c) For the situation in (b), and disregarding the distortion caused by the MOSFET’s square-law characteristic, what is the largest amplitude of a sine-wave voltage signal that can be applied at the input while the transistor remains in satura-tion? What is the amplitude of the output voltage signal that results? What gain value does the combination of these amplitudes imply? By what percentage is this gain value dif-ferent from the incremental gain value calculated above?
Why is there a difference?
5.65 Various measurements are made on an NMOS ampli-fier for which the drain resistor RD is 20 kΩ. First, dc mea-surements show the voltage across the drain resistor, VRD, to be 1.5 V and the gate-to-source bias voltage to be 0.7 V.
Then, ac measurements with small signals show the voltage gain to be −10 V/V. What is the value of Vt for this transistor?
If the process transconductance parameter is 200 μA/V2, what is the MOSFET’s W/L?
D 5.66 Refer to the expression for the incremental volt-age gain in Eq. (5.38). Various design considerations place a lower limit on the value of the overdrive voltage VOV. For our purposes here, let this lower limit be 0.2 V. Also, assume that VDD = 5 V.
(a) Without allowing any room for output voltage swing, what is the maximum voltage gain achievable?
(b) If we are required to allow for an output voltage swing of ±0.5 V, what dc bias voltage should be established at the drain to obtain maximum gain? What gain value is achiev-able? What input signal results in a ±0.5-V output swing?
(c) For the situation in (b), find W/L of the transistor to establish a dc drain current of 100 μA. For the given process technology, = 100 μA/V2.
(d) Find the required value of RD.
5.67 The expression for the incremental voltage gain Av given in Eq. (5.38) can be written in as where VDS is the bias voltage at the drain. This expression indicates that for given values of VDD and VOV, the gain mag-nitude can be increased by biasing the transistor at a lower VDS. This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak that is achievable while the transistor remains saturated is = For VDD = 5 V and VOV = 0.5 V, provide a table of values for Av, , and the corresponding for VDS = 1 V, 1.5 V, 2 V, and 2.5 V. If W/L = 1 mA/V2, find ID and RD for the design for which VDS = 1 V.
5.68 Figure P5.68 shows an amplifier in which the load resistor RD has been replaced with another NMOS transistor Q2 connected as a two-terminal device. Note that because vDG of Q2 is zero, it will be operating in saturation at all times, even when vI = 0 and iD2 = iD1 = 0. Note also that the two tran-sistors conduct equal drain currents. Using iD1 = iD2, show that for the range of vI over which Q1 is operating in saturation, that is, for the output voltage will be given by where we have assumed Vt1 = Vt2 = Vt. Thus the circuit func-tions as a linear amplifier, even for large input signals. For = ( μm) and = ( μm), find the voltage gain.
kn ′ kn ′ Av 2 VDD VDS – ( ) VOV ---------------------------------– = v ˆ o v ˆ o VDS VOV – ( ) 1 1 Av --------+ ⎝ ⎠ ⎛ ⎞ v ˆ o v ˆi kn ′ Vt1 vI vO Vt1 + ≤ ≤ vO VDD Vt – W L ⁄ ( )1 W L ⁄ ( )2 ------------------- Vt W L ⁄ ( )1 W L ⁄ ( )2 -------------------vI – + = W L ⁄ ( )1 50 μm 0.5 ⁄ W L ⁄ ( )2 5 μm 0.5 ⁄ Figure P5.68 iD2 Q2 Q1 VDD vO vI iD1 CHAPTER 5 PR OBLE MS 340 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Section 5.5: Small-Signal Operation and Models 5.69 This problem investigates the nonlinear distortion introduced by a MOSFET amplifier. Let the signal vgs be a sine wave with amplitude Vgs, and substitute vgs = Vgs sin ω t in Eq.
(5.43). Using the trigonometric identity show that the ratio of the signal at frequency 2ω to that at frequency ω, expressed as a percentage (known as the second-harmonic distortion) is If in a particular application Vgs is 10 mV, find the mini-mum overdrive voltage at which the transistor should be operated so that the second-harmonic distortion is kept to less than 1%.
5.70 Consider an NMOS transistor having = 10 mA/V2.
Let the transistor be biased at VOV = 0.5 V. For operation in saturation, what dc bias current ID results? If a 0.05-V signal is superimposed on VGS, find the corresponding increment in col-lector current by evaluating the total collector current iD and subtracting the dc bias current ID. Repeat for a −0.05-V signal.
Use these results to estimate gm of the FET at this bias point.
Compare with the value of gm obtained using Eq. (5.48).
5.71 Consider the FET amplifier of Fig. 5.34 for the case Vt = 0.4 V, = 4 mA/V2, VGS = 0.65 V, VDD = 1.8 V, and RD = 8 kΩ.
(a) Find the dc quantities ID and VD.
(b) Calculate the value of gm at the bias point.
(c) Calculate the value of the voltage gain.
(d) If the MOSFET has λ = 0.1 V−1, find ro at the bias point and calculate the voltage gain.
D 5.72 An NMOS amplifier is to be designed to provide a 0.50-V peak output signal across a 50-kΩ load that can be used as a drain resistor. If a gain of at least 5 V/V is needed, what gm is required? Using a dc supply of 1.8 V, what values of ID and VOV would you choose? What W/L ratio is required if μnCox = 200 μA/V2? If Vt = 0.4 V, find VGS.
D 5.73 In this problem we investigate an optimum design of the CS amplifier circuit of Fig. 5.34. First, use the voltage gain expression together with Eq. (5.57) for gm to show that Next, let the maximum positive input signal be . To keep the second-harmonic distortion to an acceptable level, we bias the MOSFET to operate at an overdrive voltage VOV . Let . Now, to maximize the voltage gain we design for the lowest possible VD. Show that the mini-mum VD that is consistent with allowing a negative signal voltage swing at the drain of while maintaining satura-tion-mode operation is given by Now, find VOV, VD, Av, and for the case VDD = 2.5 V, = and m = 15. If it is desired to operate this transis-tor at ID = 100 μA, find the values of RD and W/L, assuming that for this process technology 5.74 In the table below, for enhancement MOS transistors operating under a variety of conditions, complete as many entries as possible. Although some data is not available, it is always possible to calculate gm using one of Eqs. (5.55), (5.56) or (5.57). Assume μn = 500 cm2/V·s, μp = 250 cm2/V·s, and Cox = 0.4 fF/μm2.
5.75 An NMOS technology has μnCox = 250 μA/V2 and Vt = 0.5 V. For a transistor with L = 0.5 μm, find the value of W that results in gm = 1 mA/V at ID = 0.25 mA. Also, find the required VGS.
sin2θ = 1 2 ---1 2 ---2θ, cos – Second-harmonic distortion = 1 4 --- Vgs VOV ---------100 × kn kn Av gmRD – = Av 2IDRD VOV ---------------– 2 VDD VD – ( ) VOV -------------------------------– = = v ˆi v ˆi VOV mv ˆi = Av , Av v ˆi VD VOV v ˆ i 2VDD v ˆi VOV ⁄ ( ) + + 1 2 v ˆi VOV ⁄ ( ) + --------------------------------------------------------------= v ˆo v ˆi 20 mV, kn ′ = 100 μA/V 2.
Voltages (V) Dimensions (μm) Case Type ID (mA) VOV W L W/L k′(W/L) gm(mA/V) a N 1 3 2 1 b N 1 0.7 0.5 50 c N 10 2 1 d N 0.5 0.5 e N 0.1 10 2 f N 1.8 0.8 40 4 g P 0.5 2 25 h P 3 1 0.5 i P 10 4000 2 j P 10 4 k P 1 30 3 l P 0.1 5 0.008 VGS Vt Problems 341 CHAPTER 5 P ROBL EMS 5.76 For the NMOS amplifier in Fig. P5.76, replace the transistor with its T equivalent circuit, assuming .
Derive expressions for the voltage gains and 5.77 In the circuit of Fig. P5.77, the NMOS transis-tor has = 0.5 V and VA = 50 V and operates with VD = 1 V. What is the voltage gain ? What do VD and the gain become for I increased to 1 mA?
5.78 For a 0.8-μm CMOS fabrication process: Vtn = 0.8 V, Vtp = −0.9 V, μnCox = 90 μA/V2, μpCox = 30 μA/V2, Cox = 1.9 fF/μm2, VA (n-channel devices) = 8L (μm), and (p-channel devices) = 12L (μm). Find the small-sig-nal model parameters (gm and ro) for both an NMOS and a PMOS transistor having W/L = 20 μm/2 μm and operating at ID = 100 μA. Also, find the overdrive voltage at which each device must be operating.
5.79 Figure P5.79 shows a discrete-circuit amplifier. The input signal vsig is coupled to the gate through a very large capacitor (shown as infinite). The transistor source is con-nected to ground at signal frequencies via a very large capacitor (shown as infinite). The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite).
(a) If the transistor has Vt = 1 V, and = 2 mA/V2, verify that the bias circuit establishes VGS = 2 V, ID = 1 mA, and VD = +7.5 V. That is, assume these values, and verify that they are consistent with the values of the circuit components and the device parameters.
(b) Find gm and ro if VA = 100 V.
(c) Draw a complete small-signal equivalent circuit for the amplifier, assuming all capacitors behave as short circuits at signal frequencies.
(d) Find Rin, , , and .
.
λ 0 = vs vi ⁄ vd vi ⁄ .
Figure P5.76 Vt vo vi ⁄ VA vo Figure P5.77 kn vgs vsig ⁄ vo vgs ⁄ vo vsig ⁄ 15 V 10 M Rsig 100 k 7.5 k 3 k 10 k 5 M vsig vgs vo Rin Figure P5.79 CHAPTER 5 PR OBLE MS 342 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Section 5.6: Basic MOSFET Amplifier Configurations 5.80 An amplifier with an input resistance of 100 k , an open-circuit voltage gain of 100 V/V and an output resis-tance of 100 is connected between a 10-k signal source and a 1-k load. Find the overall voltage gain . Also find the current gain, defined as the ratio of the load current to the current drawn from the signal source.
D 5.81 Specify the parameters , and of an ampli-fier that is to be connected between a 100-k source and a 2-k load and is required to meet the following specifica-tions: (a) No more than 10% of the signal strength is lost in the connection to the amplifier input; (b) If the load resistance changes from the nominal value of 2 k to a low value of 1 k , the change in output voltage is limited to 10% of nominal value; and (c) The nominal overall voltage gain is 10 V/V.
5.82 Figure P5.82 shows an alternative equivalent circuit representation of an amplifier. If this circuit is to be equiva-lent to that in Fig. 5.44(b) show that . Also convince yourself that the transconductance is defined as and hence is known as the short-circuit transconductance.
Now, if the amplifier is fed with a signal source and is connected to a load resistance show that the gain of the amplifier proper is given by and the overall voltage gain is given by 5.83 An alternative equivalent circuit of an amplifier fed with a signal source and connected to a load is shown in Fig. P5.83. Here is the open-circuit overall voltage gain, and is the output resistance with set to zero. This is different than . Show that where .
Also show that the overall voltage gain is 5.84 Most practical amplifiers have internal feedback that make them non-unilateral. In such a case, depends on . To illustrate this point we show in Fig. P5.84 the equivalent circuit of an amplifier where a feedback resis-tance models the internal feedback mechanism that is present in this amplifier. It is that makes the amplifier non-unilateral. Show that Evaluate , and for the case k , M , mA/V, and k .
Which of the amplifier characteristic parameters is most affected by (that is, relative to the case with )?
Ω Ω Ω Ω Gv Rin Avo Ro Ω Ω Ω Ω Gm Avo Ro ⁄ = Gm Gm io vi ----RL 0 = = vsig, Rsig ( ) RL Rin vi Ro Gmvi vo Io Figure P5.82 Av Av Gm Ro RL || ( ) = Gv Gv Rin Rin Rsig + ---------------------- Gm Ro RL || ( ) = vsig, Rsig ( ) RL Gvo Gvo vo vsig -------RL ∞ = = Rout vsig Ro Gvo Ri Ri Rsig + -------------------- Avo = Ri Rin RL ∞ = = Gv Gvo RL RL Rout + ---------------------= Rsig Rout vsig Rin Gvovsig RL io vo vi Figure P5.83 Rin RL Rf Rf Rin R1 Rf R2 RL || ( ) + 1 gm R2 RL || ( ) + --------------------------------------|| = Avo gmR2 1 1 gmRf ( ) ⁄ – 1 R2 Rf ⁄ ( ) + --------------------------------– = Ro R2 || Rf = Rin Avo Ro R1 100 = Ω Rf 1 = Ω gm 100 = R2 100 = Ω RL 1 = Ω Rf Rf ∞ = Problems 5.80 to 5.84 are identical to Problems 6.107 to 6.111.
Problems 343 CHAPTER 5 P ROBL EMS For k determine the overall voltage gain, , with and without present.
5.85 Calculate the overall voltage gain of a CS amplifier fed with a 1-M source and connected to a 20-k load. The MOSFET has mA/V and k , and a drain resistance k is utilized.
5.86 A CS amplifier utilizes a MOSFET with μA/V2, W/L = 10, and V. It is biased at mA and uses k . Find , , and . Also, if a load resistance of 10 k is connected to the output, what overall voltage gain is realized? Now, if a 0.2-V peak sine-wave signal is required at the output, what must the peak amplitude of be?
5.87 A common-source amplifier utilizes a MOSFET for which V and is operated at V.
What is the value of its ? The amplifier feeds a load resistance k . The designer selects . If it is required to realize an overall voltage gain of V/ V what is needed? Also specify the bias current . If, to increase the output signal swing, is reduced to , what does become?
5.88 Two identical CS amplifiers are connected is cascade.
The first stage is fed with a source having a resistance k . A load resistance k is con-nected to the drain of the second stage. Each MOSFET is biased at mA and operates with V.
Assume is very large. Each stage utilizes a drain resis-tance k . (a) Sketch the equivalent circuit of the two-stage amplifier.
(b) Calculate the overall voltage gain .
5.89 In discrete-circuit amplifiers, is usually much smaller than , and thus can be neglected in deter-mining the voltage gain of the CS amplifier. Nevertheless, it is useful to note that poses an absolute upper limit on the voltage gain of a CS amplifier. Find this upper limit by let-ting . Express the maximum achievable gain in terms of and .
5.90 A MOSFET connected in the CS configuration has a transconductance mA/V. When a resistance is connected in the source lead, the effective transconductance is reduced to 1 mA/V. What do you estimate the value of to be?
5.91 A CS amplifier using an NMOS transistor with 4 mA/V is found to have an overall voltage gain of V/V.
What value should a resistance inserted in the source lead have to reduce the overall voltage gain to V/V?
5.92 The overall voltage gain of a CS amplifier with a resistance k in the source lead was measured and found to be V/V. When is shorted, but the circuit operation remained linear, the gain doubled. What must be? What value of is needed to obtain an overall voltage gain of V/V?
5.93 A CG amplifier using an NMOS transistor for which mA/V has a 5-k drain resistance and a 5-k load resistance . The amplifier is driven by a voltage source having a 500 resistance. What is the input resis-tance of the amplifier? What is the overall voltage gain ?
By what factor must the bias current of the MOSFET be changed so that matches ?
5.94 A CG amplifier when fed with a signal source having is found to have an overall voltage gain of 10 V/V. When a 200- resistance is added in series with the sig-nal generator the overall voltage gain decreased to 8 V/V. What must of the MOSFET be? If the MOSFET is biased at mA, at what overdrive voltage it must be operating?
D 5.95 A source follower is required to connect a high-resistance source to a load whose resistance is nominally 2 k but can be as low as 1 k and as high as 3 k . What is the maximum output resistance that the source follower must have if the output voltage is to remain within % of nominal value? If the MOSFET has mA/V2, at R1 Rf Rsig vsig gmvi Rin R2 RL vo vi ii Figure P5.84 Rsig 100 = Ω Gv Rf Ω Ω gm 2 = ro 50 = Ω RD 10 = Ω μnCox 400 = VA 10 = ID 0.2 = RD 6 = Ω Rin Avo Ro Ω Gv vsig VA 12.5 = VOV 0.25 = gmro ( ) RL 15 = Ω RD 2RL = Gv 10 – gm ID RD RD RL = Gv vsig Rsig 100 = Ω RL 10 = Ω ID 0.25 = VOV 0.25 = VA RD 10 = Ω Gv RD RL || ( ) ro ro ro RD RL ∞ = || VA VOV gm 5 = Rs Rs gm = 16 – Rs 8 – Rs 1 = Ω 15 – Rs gm Rs 10 – gm 4 = Ω RD Ω RL Ω Gv ID Rin Rsig Rsig 200 = Ω Ω gm ID 0.2 = Ω Ω Ω 20 ± kn 16 = CHAPTER 5 PR OBLE MS 344 Chapter 5 MOS Field-Effect Transistors (MOSFETs) what current must it be biased? At what overdrive volt-age is the MOSFET operating?
5.96 Refer to the source-follower equivalent circuit shown in Fig. 5.50(b). Show that Now, with removed, the voltage gain is carefully mea-sured and found to be 0.98. Then, when is connected and its value is varied, it is found that the gain is halved at . If the amplifier remained linear throughout this measurement, what must the values of and be?
D 5.97 A source follower is required to deliver a 0.5-V peak sinusoid to 2-kΩ load. If the peak amplitude of is to be limited to 50 mV, what is the lowest value of at which the MOSFET can be biased? At this bias current, what are the maximum and minimum currents that the MOSFET will be conducting (at the positive and negative peaks of the out-put sine wave)? What must the peak amplitude of be?
Section 5.7: Biasing in MOS Amplifier Circuits D 5.98 Consider the classical biasing scheme shown in Fig. 5.52(c), using a 9-V supply. For the MOSFET, Vt = 1 V, λ = 0, and . Arrange that the drain current is 1 mA, with about one-third of the supply voltage across each of RS and RD. Use 22 MΩ for the larger of RG1 and RG2. What are the values of RG1, RG2, RS, and RD that you have chosen?
Specify them to two significant digits. For your design, how far is the drain voltage from the edge of saturation?
D 5.99 Using the circuit topology displayed in Fig.
5.52(e), arrange to bias the NMOS transistor at ID = 1 mA with VD midway between cutoff and the beginning of tri-ode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 1.0 V, λ = 0, and .
Use a gate-bias resistor of 10 MΩ. Specify RS and RD to two significant digits.
D 5.100 In an electronic instrument using the biasing scheme shown in Fig. 5.52(c), a manufacturing error reduces RS to zero. Let VDD = 12 V, RG1 = 5.6 MΩ, and RG2 = 2.2 MΩ. What is the value of VG created? If supplier specifi-cations allow to vary from 0.2 to 0.3 mA/V2 and Vt to vary from 1.0 V to 1.5 V, what are the extreme values of ID that may result? What value of RS should have been installed to limit the maximum value of ID to 0.5 mA? Choose an appropriate standard 5% resistor value (refer to Appendix G).
What extreme values of current now result?
5.101 An enhancement NMOS transistor is connected in the bias circuit of Fig. 5.52(c), with VG = 4 V and RS = 2 kΩ.
The transistor has Vt = 1 V and = 2 mA/V2. What bias current results? If a transistor for which is 50% higher is used, what is the resulting percentage increase in ID?
5.102 The bias circuit of Fig. 5.52(c) is used in a design with VG = 5 V and RS = 2 kΩ. For an enhancement MOSFET with = 2 mA/V2, the source voltage was mea-sured and found to be 2 V. What must Vt be for this device?
If a device for which Vt is 0.5 V less is used, what does VS become? What bias current results?
D 5.103 Design the circuit of Fig. 5.52(e) for an enhance-ment MOSFET having Vt = 1 V and = 2 mA/V2. Let VDD = VSS = 5 V. Design for a dc bias current of 1 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero.
D 5.104 Design the circuit in Fig. P5.104 so that the transistor operates in saturation with VD biased 1 V from the edge of the triode region, with ID = 1 mA and VD = 3 V, for each of the following two devices (use a 10-μA current in the voltage divider): (a) and W/L = 0.5 mA/V2 (b) and W/L = 1.25 mA/V2 For each case, specify the values of VG, VD, VS, R1, R2, RS, and RD.
D 5.105 A very useful way to characterize the stability of the bias current ID is to evaluate the sensitivity of ID rela-tive to a particular transistor parameter whose variability might be large. The sensitivity of ID relative to the MOSFET parameter is defined as ID Gv vo vsig -------RL ro || RL ro || ( ) 1 gm ------+ ---------------------------------= ≡ RL RL RL 500 = Ω gm ro vgs ID vsig kn 2 mA/V2 = kn 2 mA/V2 = kn kn kn kn kn Vt = 1 V kp ′ Vt = 2 V kp ′ Figure P5.104 10 V RS VD VS VG RD R1 R2 K 1 2 ---k′ W L ⁄ ( ) ≡ S ID K ID ID ⁄ ∂ K K ⁄ ∂ -----------------∂ID ∂K --------- K ID -----= ≡ Problems 345 CHAPTER 5 P ROBL EMS and its value, when multiplied by the variability (or toler-ance) of K, provides the corresponding expected variability of ID. The purpose of this problem is to investigate the use of the sensitivity function in the design of the bias circuit of Fig. 5.52(e).
(a) Show that for Vt constant, (b) For a MOSFET having K = 100 μA/V2 with a variability of ±10% and Vt = 1 V, find the value of RS that would result in ID = 100 μA with a variability of ±1%. Also, find VGS and the required value of VSS.
(c) If the available supply VSS = 5 V, find the value of RS for ID = 100 μA. Evaluate the sensitivity function, and give the expected variability of ID in this case.
5.106 For the circuit in Fig. 5.55(a) with I = 0.2 mA, RG = 0, RD = 10 kΩ, and VDD = 2.5 V, consider the behavior in each of the following two cases. In each case, find the voltages VS, VD, and VDS that result.
(a) Vt = 1 V and = 1.6 mA/V2 (b) Vt = 0.8 V and = 1.25 mA/V2 5.107 In the circuit of Fig. 5.54, let RG = 10 MΩ, RD = 10 kΩ, and VDD = 10 V. For each of the following two transis-tors, find the voltages VD and VG.
(a) Vt = 1 V and = 0.5 mA/V2 (b) Vt = 2 V and = 1.25 mA/V2 D 5.108 Using the feedback bias arrangement shown in Fig. 5.54 with a 5-V supply and an NMOS device for which Vt = 1 V and = 0.6 mA/V2, find RD to establish a drain current of 0.2 mA. If resistor values are limited to those on the 5% resistor scale (see Appendix G), what value would you choose? What values of current and VD result?
D 5.109 Figure P5.109 shows a variation of the feedback-bias circuit of Fig. 5.54. Using a 5-V supply with an NMOS transistor for which Vt = 1 V, = 6.25 mA/V2 and λ = 0, provide a design that biases the transistor at ID = 2 mA, with VDS large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 MΩ as the largest resistor in the feedback-bias network. What values of RD, RG1, and RG2 have you chosen? Specify all resistors to two significant digits.
Section 5.8: Discrete-Circuit MOS Amplifiers 5.110 Calculate the overall voltage gain Gv of a common-source amplifier for which gm = 2 mA/V, ro = 50 kΩ, RD = 10 kΩ, and RG = 10 MΩ. The amplifier is fed from a signal source with a Thévenin resistance of 0.5 MΩ, and the ampli-fier output is coupled to a load resistance of 20 kΩ.
D 5.111 This problem investigates a redesign of the common-source amplifier of Exercise 5.38 whose bias design was done in Exercise 5.37 and shown in Fig. E5.37. Please refer to these two exercises.
(a) The open-circuit voltage gain of the CS amplifier can be written as Verify that this expression yields the results in Exercise 5.38 (i.e., Avo = −15 V/V).
(b) Avo can be doubled by reducing VOV by a factor of 2, (i.e., from 1 V to 0.5 V) while VD is kept unchanged. What corresponding values for ID, RD, gm, and ro apply?
(c) Find Avo and Ro with ro taken into account.
(d) For the same value of signal-generator resistance Rsig = 100 kΩ, the same value of gate-bias resistance RG = 4.8 MΩ, and the same value of load resistance RL = 15 kΩ, eval-uate the new value of overall voltage gain Gv with ro taken into account.
(e) Compare your results to those obtained in Exercises 5.37 and 5.38, and comment.
5.112 The NMOS transistor in the CS amplifier shown in Fig. P5.112 has V and V.
(a) Neglecting the Early effect, verify that the MOSFET is operating in saturation with mA and V. What must the MOSFET’s be? What is the dc voltage at the drain?
(b) Find and .
(c) If is a sinusoid with a peak amplitude , find the maximum allowable value of for which the transistor remains in saturation. What is the corresponding amplitude of the output voltage?
(d) What is the value of resistance that needs to be inserted in series with capacitor in order to allow us to S ID K = 1 1 2 KIDRS + ( ) ⁄ kn kn kn kn kn kn Figure P5.109 RD VDD RG1 RG2 Avo 2 VDD VD – ( ) VOV -------------------------------– = Vt 0.7 = VA 50 = ID 0.5 = VOV 0.3 = kn Rin Gv vsig v ˆ sig v ˆ sig Rs CS CHAPTER 5 PR OBLE MS 346 Chapter 5 MOS Field-Effect Transistors (MOSFETs) double the input signal ? What output voltage now results?
D 5.113 The PMOS transistor in the CS amplifier of Fig. P5.113 has V and a very large .
(a) Select a value for to bias the transistor at ID = 0.3 mA and V. Assume to have a zero dc compo-nent.
(b) Select a value for that results in V/V.
(c) Find the largest sinusoid that the amplifier can han-dle while remaining in the saturation region. What is the corresponding signal at the output?
(d) If to obtain reasonably linear operation, is limited to 50 mV, what value can be increased to while maintaining saturation-region operation? What is the new value of ?
5.114 Figure P5.114 shows a scheme for coupling and amplifying a high-frequency pulse signal. The circuit utilizes two MOSFETs whose bias details are not shown and a 50-Ω coaxial cable. Transistor Q1 operates as a CS ampli-fier and Q2 as a CG amplifier. For proper operation, transis-tor Q2 is required to present a 50-Ω resistance to the cable.
This situation is known as “proper termination” of the cable and ensures that there will be no signal reflection coming back on the cable. When the cable is properly terminated, its input resistance is 50 Ω. What must gm2 be? If Q1 is biased at the same point as Q2, what is the amplitude of the current pulses in the drain of Q1? What is the amplitude of the volt-age pulses at the drain of Q1? What value of RD is required to provide 1-V pulses at the drain of Q2?
CC2 CS CC1 5 V 300 k 120 k 5 k 2 k 5 k 200 k vsig vo Rin Figure P5.112 v ˆ sig Vtp 0.7 – = VA RS VOV 0.3 = vsig RD Gv 10 – = v ˆ sig v ˆ sig RD Gv 2.5 V 2.5 V RS CS CC vsig vo Rsig RD Figure P5.113 Q1 Q2 vi vd1 5 mV vo id RD 50- Coaxial cable VDD Ri2 50 Figure P5.114 Problems 347 CHAPTER 5 P ROBL EMS D 5.115 The MOSFET in the circuit of Fig. P5.115 has Vt = 1 V, = 0.8 mA/V2, and VA = 40 V.
(a) Find the values of RS, RD, and RG so that ID = 0.1 mA, the largest possible value for RD is used while a maximum sig-nal swing at the drain of ±1 V is possible, and the input resistance at the gate is 10 MΩ. Neglect the Early effect.
(b) Find the values of gm and ro at the bias point.
(c) If terminal Z is grounded, terminal X is connected to a signal source having a resistance of 1 MΩ, and terminal Y is connected to a load resistance of 40 kΩ, find the voltage gain from signal source to load.
(d) If terminal Y is grounded, find the voltage gain from X to Z with Z open-circuited. What is the output resistance of the source follower?
(e) If terminal X is grounded and terminal Z is connected to a current source delivering a signal current of 10 μA and having a resistance of 100 kΩ, find the voltage signal that can be measured at Y. For simplicity, neglect the effect of ro.
5.116 (a) The NMOS transistor in the source-follower circuit of Fig. P5.116(a) has gm = 5 mA/V and a large ro.
Find the open-circuit voltage gain and the output resistance.
(b) The NMOS transistor in the common-gate amplifier of Fig. P5.116(b) has gm = 5 mA/V and a large ro. Find the input resistance and the voltage gain.
(c) If the output of the source follower in (a) is connected to the input of the common-gate amplifier in (b), use the results of (a) and (b) to obtain the overall voltage gain .
5.117 In this problem we investigate the large-signal oper-ation of the source follower of Fig. 5.60(a). Specifically, con-sider the situation when negative input signals are applied.
Let the negative signal voltage at the output be −V. The cur-rent in RL will flow away from ground and will have a value of V/RL. This current will subtract from the bias current I, resulting in a transistor current of (I − V/RL). One can use this current value to determine vGS. Now, the signal at the transis-tor source terminal will be −V, superimposed on the dc volt-age, which is −VGS (corresponding to a drain current of I). We can thus find the signal voltage at the gate vi. For the circuit analyzed in Exercise 5.41, find vi for vo = −1 V, −5 V, −6 V, and −7 V. At each point, find the voltage gain vo/vi and compare to the small-signal value found in Exercise 5.41.
What is the largest possible negative-output signal?
kn Figure P5.115 RS RG Y RD 5 V 5 V X Z vo vi ⁄ (a) 10 k vo1 vi vo vi2 2 k 10 k 5 k (b) Figure P5.116 CHAPTER 5 PR OBLE MS 348 Chapter 5 MOS Field-Effect Transistors (MOSFETs) Section 5.9: The Body Effect and Other Topics 5.118 In a particular application, an n-channel MOSFET operates with in the range 0 V to 4 V. If is nominally 1.0 V, find the range of that results if and V. If the gate oxide thickness is increased by a factor of 4, what does the threshold voltage become?
5.119 A p-channel transistor operates in saturation with its source voltage 3 V lower than its substrate. For V, and V, find .
5.120 For an NMOS transistor with V, , and V, find If the transistor is biased at mA with V, find and .
5.121 A depletion-type n-channel MOSFET with mA/V2 and V has its source and gate grounded. Find the region of operation and the drain current for V, 1 V, 3 V, and 5 V. Neglect the channel-length-modulation effect.
5.122 For a particular depletion-mode NMOS device, V, μA/V2, and .
When operated at , what is the drain current that flows for V, 2 V, 3 V, and 10 V? What does each of these currents become if the device width is doubled with L the same? With L also doubled? 5.123 Neglecting the channel-length-modulation effect show that for the depletion-type NMOS transistor of Fig.
P5.123, the relationship is given by , for for (Recall that is negative). Sketch the relationship for the case: V and mA/V2. General Problems 5.124 The circuits shown in Fig. P5.124 employ negative feedback, a subject we shall study in detail in Chapter 10.
Assume that each transistor is sized and biased so that gm = 1 mA/V and ro = 100 kΩ. Otherwise, ignore all dc bias-ing detail and concentrate on small-signal operation result-ing in response to the input signal vsig. For RL = 10 kΩ, R1 = 500 kΩ, and R2 = 1 MΩ, find the overall voltage gain vo/vsig and the input resistance Rin for each circuit. Neglect the body effect. Do these circuits remind you of op-amp circuits? Comment.
VSB Vt0 Vt γ 0.5 V1 2 ⁄ = 2φf 0.6 = γ 0.5 V1 2 ⁄ , = 2φf 0.75 = Vt0 0.7 – = Vt 2φf 0.6 = γ 0.5 V1 2 ⁄ , = VSB 4 = χ gmb gm ⁄ .
= ID 0.5 = VOV 0.25 = gm gmb k′nW L ⁄ 2 = Vt 3 – = vD 0.1 = Vt 2 – = k′nW L ⁄ 200 = λ 0.02 V 1 – = vGS 0 = vDS 1 = i v – i 1 2 ---k′ n W L ⁄ ( ) v2 2Vtv – ( ) = v Vt ≥ i 1 2 ---– k′ n W L ⁄ ( )Vt 2 = v Vt ≤ Vt i v – Vt 2 – = k ′ n W L ⁄ ( ) 2 = v i Figure P5.123 (a) R1 R2 RL VDD vsig vo Rin (b) R2 R1 RL VDD vsig vo Rin Figure P5.124 Problems 349 CHAPTER 5 P ROBL EMS 5.125 For the two circuits in Problem 5.124 (shown in Fig. P5.124), we wish to consider their dc bias design. Since vsig has a zero dc component, we short-circuit its generator.
For NMOS transistors with Vt = 0.6 V, find VOV, and VA to bias each device at ID = 0.1 mA and to obtain the values of gm and ro specified in Problem 5.124: namely, gm = 1 mA/V and ro = 100 kΩ. For R1 = 0.5 MΩ, R2 = 1 MΩ, and RL = 10 kΩ, find the required value of VDD.
5.126 In the amplifier shown in Fig. P5.126, transistors having Vt = 0.6 V and VA = 20 V are operated at VGS = 0.8 V using the appropriate choice of W/L ratio. In a particular application, Q1 is to be sized to operate at 10 μA, while Q2 is intended to operate at 1 mA. For RL = 2 kΩ, the (R1, R2) net-work sized to consume only 1% of the current in RL, vsig, having zero dc component, and I1 = 10 μA, find the values of R1 and R2 that satisfy all the requirements. (Hint: VO must be +2 V.) What is the voltage gain vo/vi? Using a result from a theorem known as Miller’s theorem (Chapter 9), find the input resistance Rin as Now, calculate the value of the overall voltage gain vo/vsig. Does this result remind you of the inverting configuration of the op amp?
Comment. How would you modify the circuit at the input by using an additional resistor and a very large capacitor to raise the gain vo/vsig to −5 V/V? Neglect the body effect.
5.127 Consider the bias design of the circuit of Problem 5.126 (shown in Fig. P5.126). For = 200 μA/V2 and VDD = 3.3 V, find and to obtain the operating con-ditions specified in Problem 5.126.
kn ′ W L ⁄ ( ), R2 1 v – o vi ⁄ ( ).
⁄ VDD RL R1 R2 I1 Q2 Q1 vo vi Rin vsig Figure P5.126 kn ′ W/L ( )1 W/L ( )2 CHAPTER 6 Bipolar Junction Transistors (BJTs) Introduction 351 6.1 Device Structure and Physical Operation 352 6.2 Current–Voltage Characteristics 365 6.3 BJT Circuits at DC 378 6.4 Applying the BJT in Amplifier Design 396 6.5 Small-Signal Operation and Models 403 6.6 Basic BJT Amplifier Configurations 422 6.7 Biasing in BJT Amplifier Circuits 446 6.8 Discrete-Circuit BJT Amplifiers 453 6.9 Transistor Breakdown and Temperature Effects 463 Summary 465 Problems 466 351 IN THIS CHAPTER YOU WILL LEARN 1. The physical structure of the bipolar transistor and how it works.
2. How the voltage between two terminals of the transistor controls the current that flows through the third terminal, and the equations that describe these current–voltage characteristics.
3. How to analyze and design circuits that contain bipolar transistors, resis-tors, and dc sources.
4. How the transistor can be used to make an amplifier.
5. How to obtain linear amplification from the fundamentally nonlinear BJT.
6. The three basic ways for connecting a BJT to be able to construct am-plifiers with different properties.
7. Practical circuits for bipolar-transistor amplifiers that can be construct-ed by using discrete components.
Introduction In this chapter, we study the other major three-terminal device: the bipolar junction transistor (BJT). The presentation of the material in this chapter parallels but does not rely on that for the MOSFET in Chapter 5; thus, if desired, the BJT can be studied before the MOSFET.
Three-terminal devices are far more useful than two-terminal ones, such as the diodes studied in Chapter 4, because they can be used in a multitude of applications, ranging from signal amplification to the design of digital logic and memory circuits. The basic principle involved is the use of the voltage between two terminals to control the current flowing in the third terminal. In this way, a three-terminal device can be used to realize a controlled source, which as we learned in Chapter 1 is the basis for amplifier design. Also, in the extreme, the control signal can be used to cause the current in the third terminal to change from zero to a large value, thus allowing the device to act as a switch. The switch is the basis for the realization of the logic inverter, the basic element of digital circuits.
The invention of the BJT in 1948 at the Bell Telephone Laboratories ushered in the era of solid-state circuits, which led to electronics changing the way we work, play, and indeed, live. The invention of the BJT also eventually led to the dominance of information technology and the emergence of the knowledge-based economy.
The bipolar transistor enjoyed nearly three decades as the device of choice in the design of both discrete and integrated circuits. Although the MOSFET had been known 352 Chapter 6 Bipolar Junction Transistors (BJTs) very early on, it was not until the 1970s and 1980s that it became a serious competitor to the BJT. By 2009, the MOSFET was undoubtedly the most widely used electronic device, and CMOS technology the technology of choice in the design of integrated circuits. Nev-ertheless, the BJT remains a significant device that excels in certain applications. For instance, the reliability of BJT circuits under severe environmental conditions makes them the dominant device in certain automotive applications. The BJT remains popular in discrete-circuit design, in which a very wide selection of BJT types are available to the designer. Here we should mention that the characteristics of the bipolar transistor are so well understood that one is able to design transistor circuits whose performance is remarkably predictable and quite insensitive to variations in device parameters.
The BJT is still the preferred device in very demanding analog circuit applications, both integrated and discrete. This is especially true in very-high-frequency applications, such as radio-frequency (RF) circuits for wireless systems. A very-high-speed digital logic-circuit family based on bipolar transistors, namely, emitter-coupled logic, is still in use. Finally, bipolar transistors can be combined with MOSFETs to create innovative circuits that take advantage of the high-input-impedance and low-power operation of MOSFETs and the very-high-frequency operation and high-current-driving capability of bipolar transistors.
The resulting technology is known as BiCMOS, and it is finding increasingly larger areas of application (see Chapters 7, 8, 12, and 14).
In this chapter, we shall start with a description of the physical operation of the BJT.
Though simple, this physical description provides considerable insight regarding the perfor-mance of the transistor as a circuit element. We then quickly move from describing current flow in terms of electrons and holes to a study of the transistor terminal characteristics.
Circuit models for transistor operation in different modes will be developed and utilized in the analysis and design of transistor circuits. The main objective of this chapter is to develop in the reader a high degree of familiarity with the BJT. Thus, by the end of the chapter, the reader should be able to perform rapid first-order analysis of transistor circuits and to design single-stage transistor amplifiers.
6.1 Device Structure and Physical Operation 6.1.1 Simplified Structure and Modes of Operation Figure 6.1 shows a simplified structure for the BJT. A practical transistor structure will be shown later (see also Appendix A, which deals with fabrication technology).
As shown in Fig. 6.1, the BJT consists of three semiconductor regions: the emitter region (n type), the base region (p type), and the collector region (n type). Such a transistor is called an npn transistor. Another transistor, a dual of the npn as shown in Fig. 6.2, has a p-type emitter, an n-type base, and a p-type collector, and is appropriately called a pnp transistor.
A terminal is connected to each of the three semiconductor regions of the transistor, with the terminals labeled emitter (E), base (B), and collector (C).
The transistor consists of two pn junctions, the emitter–base junction (EBJ) and the collector–base junction (CBJ). Depending on the bias condition (forward or reverse) of each of these junctions, different modes of operation of the BJT are obtained, as shown in Table 6.1. The active mode is the one used if the transistor is to operate as an amplifier.
Switching applications (e.g., logic circuits) utilize both the cutoff mode and the saturation mode. As the name implies, in the cutoff mode no current flows because both junctions are reverse biased.
6.1 Device Structure and Physical Operation 353 As we will see shortly, charge carriers of both polarities—that is, electrons and holes— participate in the current-conduction process in a bipolar transistor, which is the reason for the name bipolar.1 6.1.2 Operation of the npn Transistor in the Active Mode Of the three modes of operation of the BJT, the active mode is the most important. Therefore, we begin our study of the BJT by considering its physical operation in the active mode.2 This situation is illustrated in Fig. 6.3 for the npn transistor. Two external voltage sources (shown as batteries) are used to establish the required bias conditions for active-mode operation. The voltage Figure 6.1 A simplified structure of the npn transistor.
Figure 6.2 A simplified structure of the pnp transistor.
Table 6.1 BJT Modes of Operation Mode EBJ CBJ Cutoff Reverse Reverse Active Forward Reverse Saturation Forward Forward 1This should be contrasted with the situation in the MOSFET, where current is conducted by charge carriers of one type only; electrons in n-channel devices or holes in p-channel devices. In earlier days, some referred to FETs as unipolar devices.
2The material in this section assumes that the reader is familiar with the operation of the pn junction under forward-bias conditions (Section 3.5).
n-type n-type Emitter region Emitter–base junction (EBJ) Collector–base junction (CBJ) Collector (C) Emitter (E) Metal contact Collector region p-type Base region Base (B) Metal contact E B C Emitter region Base region Collector region p p n 354 Chapter 6 Bipolar Junction Transistors (BJTs) VBE causes the p-type base to be higher in potential than the n-type emitter, thus forward-biasing the emitter–base junction. The collector–base voltage VCB causes the n-type collector to be at a higher potential than the p-type base, thus reverse-biasing the collector–base junction.
Current Flow The forward bias on the emitter–base junction will cause current to flow across this junction. Current will consist of two components: electrons injected from the emitter into the base, and holes injected from the base into the emitter. As will become apparent shortly, it is highly desirable to have the first component (electrons from emitter to base) at a much higher level than the second component (holes from base to emitter). This can be accomplished by fabricating the device with a heavily doped emitter and a lightly doped base; that is, the device is designed to have a high density of electrons in the emitter and a low density of holes in the base.
The current that flows across the emitter–base junction will constitute the emitter current iE, as indicated in Fig. 6.3. The direction of iE is “out of” the emitter lead, which, following the usual conventions, is in the direction of the positive-charge flow (hole current) and opposite to the direction of the negative-charge flow (electron current), with the emitter current iE being equal to the sum of these two components. However, since the electron component is much larger than the hole component, the emitter current will be dominated by the electron component.
Let us now consider the electrons injected from the emitter into the base. These electrons will be minority carriers in the p-type base region. Because the base is usually very thin, in the steady state the excess minority carrier (electron) concentration in the base will have an almost-straight-line profile, as indicated by the solid straight line in Fig. 6.4. The electron concentration will be highest [denoted by np(0)] at the emitter side and lowest (zero) at the collector side.3 As in the case of any forward-biased pn junction (Section 3.5), the concentration will be proportional to Figure 6.3 Current flow in an npn transistor biased to operate in the active mode. (Reverse current components due to drift of thermally generated minority carriers are not shown.) 3This minority carrier distribution in the base results from the boundary conditions imposed by the two junctions. It is not an exponentially decaying distribution, which would result if the base region were infinitely thick. Rather, the thin base causes the distribution to decay linearly. Furthermore, the reverse bias on the collector–base junction causes the electron concentration at the collector side of the base to be zero.
VCB B C v CB v BE iE iE iC iC iB iB iB2 iC iE Recombined electrons (iB2) Injected holes (iB1) E Forward-biased iE iC n p n Reverse-biased – + – + VBE Injected electrons Diffusing electrons Collected electrons np 0 ( ) e vBE VT ⁄ , 6.1 Device Structure and Physical Operation 355 (6.1) where is the thermal-equilibrium value of the minority carrier (electron) concentration in the base region, vBE is the forward base–emitter bias voltage, and VT is the thermal voltage, which is equal to approximately 25 mV at room temperature. The reason for the zero con-centration at the collector side of the base is that the positive collector voltage vCB causes the electrons at that end to be swept across the CBJ depletion region.
The tapered minority-carrier concentration profile (Fig. 6.4) causes the electrons injected into the base to diffuse through the base region toward the collector. This electron diffusion current In is directly proportional to the slope of the straight-line concentration profile, (6.2) where AE is the cross-sectional area of the base–emitter junction (in the direction perpendi-cular to the page), q is the magnitude of the electron charge, Dn is the electron diffusivity in the base, and W is the effective width of the base. Observe that the negative slope of the minority carrier concentration results in a negative current In across the base; that is, In flows from right to left (in the negative direction of x), which corresponds to the usual convention, namely, opposite to the direction of electron flow.
Some of the electrons that are diffusing through the base region will combine with holes, which are the majority carriers in the base. However, since the base is usually very thin and lightly doped, the proportion of electrons “lost” through this recombination process will be quite small. Nevertheless, the recombination in the base region causes the excess minority car-rier concentration profile to deviate from a straight line and take the slightly concave shape indicated by the broken line in Fig. 6.4. The slope of the concentration profile at the EBJ is Figure 6.4 Profiles of minority-carrier concentrations in the base and in the emitter of an npn transistor operating in the active mode: and Emitter (n) EBJ depletion region Base (p) CBJ depletion region Collector (n) Carrier concentration Hole concentration Effective base width W Distance (x) np (0) Electron concentration np (ideal) np (with recombination) pn (0) pn0 vBE 0 > vCB 0 ≥ .
np 0 ( ) np0e vBE VT ⁄ = np0 In AEqDn dnp x ( ) dx ----------------= AEqDn np 0 ( ) W --------------– ⎝ ⎠ ⎛ ⎞ = 356 Chapter 6 Bipolar Junction Transistors (BJTs) slightly higher than that at the CBJ, with the difference accounting for the small number of electrons lost in the base region through recombination.
The Collector Current From the description above we see that most of the diffusing elec-trons will reach the boundary of the collector–base depletion region. Because the collector is more positive than the base (by vCB volts), these successful electrons will be swept across the CBJ depletion region into the collector. They will thus get “collected” to constitute the col-lector current iC. Thus iC = In, which will yield a negative value for iC, indicating that iC flows in the negative direction of the x axis (i.e., from right to left). Since we will take this to be the positive direction of iC, we can drop the negative sign in Eq. (6.2). Doing this and substituting for np(0) from Eq. (6.1), we can thus express the collector current iC as (6.3) where the saturation current IS is given by Substituting where ni is the intrinsic carrier density and NA is the doping con-centration in the base, we can express IS as (6.4) An important observation to make here is that the magnitude of iC is independent of vCB.
That is, as long as the collector is positive with respect to the base, the electrons that reach the collector side of the base region will be swept into the collector and register as collector current.
The saturation current IS is inversely proportional to the base width W and is directly proportional to the area of the EBJ. Typically IS is in the range of 10−12 A to 10−18 A (depend-ing on the size of the device). Because IS is proportional to it is a strong function of tem-perature, approximately doubling for every 5°C rise in temperature. (For the dependence of on temperature, refer to Eq. 3.37.) Since IS is directly proportional to the junction area (i.e., the device size), it will also be referred to as the scale current. Two transistors that are identical except that one has an EBJ area, say, twice that of the other will have saturation currents with that same ratio (i.e., 2).
Thus for the same value of vBE the larger device will have a collector current twice that in the smaller device. This concept is frequently employed in integrated-circuit design.
The Base Current The base current iB is composed of two components. The first compo-nent iB1 is due to the holes injected from the base region into the emitter region. This current component is proportional to The second component of base current, iB2, is due to holes that have to be supplied by the external circuit in order to replace the holes lost from the base through the recombination process. Because iB2 is proportional to the number of elec-trons injected into the base, it also will be proportional to Thus the total base current, iB = iB1 + iB2, will be proportional to and can be expressed as a fraction of the collector current iC as follows: (6.5) iC ISe vBE VT ⁄ = IS AEqDnnp0 W ⁄ = np0 ni 2 NA ⁄ , = IS AEqDnni 2 NAW ---------------------= ni 2, ni 2 evBE VT ⁄ .
evBE VT ⁄ .
evBE VT ⁄ , iB iC β ----= 6.1 Device Structure and Physical Operation 357 That is, (6.6) where β is a transistor parameter.
For modern npn transistors, β is in the range 50 to 200, but it can be as high as 1000 for special devices. For reasons that will become clear later, the parameter β is called the common-emitter current gain.
The above description indicates that the value of β is highly influenced by two factors: the width of the base region, W, and the relative dopings of the base region and the emitter region, To obtain a high β (which is highly desirable since β represents a gain parameter) the base should be thin (W small) and lightly doped and the emitter heavily doped For modern integrated circuit fabrication technologies, W is in the nanometer range.
The Emitter Current Since the current that enters a transistor must leave it, it can be seen from Fig. 6.3 that the emitter current iE is equal to the sum of the collector current iC and the base current iB; that is, (6.7) Use of Eqs. (6.5) and (6.7) gives (6.8) That is, (6.9) Alternatively, we can express Eq. (6.8) in the form (6.10) where the constant α is related to β by (6.11) Thus the emitter current in Eq. (6.9) can be written (6.12) Finally, we can use Eq. (6.11) to express β in terms of α, that is, (6.13) It can be seen from Eq. (6.11) that α is a constant (for a particular transistor) that is less than but very close to unity. For instance, if β = 100, then α 0.99. Equation (6.13) reveals an important fact: Small changes in α correspond to very large changes in β. This mathemat-ical observation manifests itself physically, with the result that transistors of the same type iB IS β ----⎝⎠ ⎛⎞e vBE VT ⁄ = NA ND ⁄ .
making NA ND ⁄ small ( ).
iE iC iB + = iE β 1 + β ------------iC = iE β 1 + β ------------ISe vBE VT ⁄ = iC αiE = α β β 1 + ------------= iE IS α ⁄ ( )e vBE VT ⁄ = β α 1 α – ------------= 358 Chapter 6 Bipolar Junction Transistors (BJTs) may have widely different values of β. For reasons that will become apparent later, α is called the common-base current gain.
Recapitulation and Equivalent-Circuit Models We have presented a first-order model for the operation of the npn transistor in the active mode. Basically, the forward-bias voltage vBE causes an exponentially related current iC to flow in the collector terminal. The collector current iC is independent of the value of the collector voltage as long as the collector–base junction remains reverse biased; that is, vCB ≥ 0. Thus in the active mode the collector terminal behaves as an ideal constant-current source where the value of the current is determined by vBE. The base current iB is a factor 1/β of the collector current, and the emitter current is equal to the sum of the collector and base currents. Since iB is much smaller than iC (i.e., β 1), iE iC. More precisely, the collector current is a fraction α of the emitter current, with α smaller than, but close to, unity.
This first-order model of transistor operation in the active mode can be represented by the equivalent circuit shown in Fig. 6.5(a). Here, diode DE has a scale current ISE equal to and thus provides a current iE related to vBE according to Eq. (6.12). The current of the controlled source, which is equal to the collector current, is controlled by vBE accord-ing to the exponential relationship indicated, a restatement of Eq. (6.3). This model is in essence a nonlinear voltage-controlled current source. It can be converted to the current-controlled current-source model shown in Fig. 6.5(b) by expressing the current of the con-trolled source as α iE. Note that this model is also nonlinear because of the exponential Figure 6.5 Large-signal equivalent-circuit models of the npn BJT operating in the forward active mode.
IS α ⁄ ( ) (ISE ISa) ISevBE VT C E B iB iE vBE DE ( (a) iC (ISE ISa) C E B iB iC DE (b) iE vBE aiE iE E B C iB DB (ISB ISb) ISevBEVT iC iE vBE (c) E B iB biB iE vBE (d) C iC iB DB (ISB ISb) 6.1 Device Structure and Physical Operation 359 relationship of the current iE through diode DE and the voltage vBE. From this model we observe that if the transistor is used as a two-port network with the input port between E and B and the output port between C and B (i.e., with B as a common terminal), then the current gain observed is equal to α. Thus α is called the common-base current gain. Two other equivalent circuit models, shown in Fig. 6.5(c) and (d), may be used to represent the operation of the BJT. The model of Fig. 6.5(c) is essentially a voltage-controlled current source. However, here diode DB conducts the base current and thus its current scale factor is IS/β, resulting in the iB –vBE relationship given in Eq. (6.6). By simply expressing the collector current as βiΒ we obtain the current-controlled current-source model shown in Fig. 6.5(d). From this lat-ter model we observe that if the transistor is used as a two-port network with the input port between B and E and the output port between C and E (i.e., with E as the common terminal), then the current gain observed is equal to β. Thus β is called the common-emitter current gain.
Finally, we note that the models in Fig. 6.5 apply for any positive value of vBE. That is, unlike the models we will be discussing in Section 6.5, here there is no limitation on the size of vBE, and thus these models are referred to as large-signal models.
An npn transistor having A and is connected as follows: The emitter is grounded, the base is fed with a constant-current source supplying a dc current of 10 μA, and the collector is con-nected to a 5-V dc supply via a resistance RC of 3 k . Assuming that the transistor is operating in the active mode, find and . Use these values to verify active-mode operation. Replace the current source with a resistance connected from the base to the 5-V dc supply. What resistance value is needed to result in the same operating conditions?
Solution If the transistor is operating in the active mode, it can be represented by one of the four possible equivalent-circuit models shown in Fig. 6.5. Because the emitter is grounded, either the model in Fig. 6.5(c) or that in Fig. 6.5(d) would be suitable. Since we know the base current the model of Fig. 6.5(d) is the most suitable. Figure 6.6 Circuits for Example 6.1.
IS 10 15 – = β 100 = Ω VBE VCE IB, VBE VCE IC IB E B C DB RC 3 k VCC 5V 10 A bIB (a) VBE VCE IC IB E B C DB RC RB VCC 5V bIB (b) Example 6.1 360 Chapter 6 Bipolar Junction Transistors (BJTs) Example 6.1 continued Figure 6.6(a) shows the circuit as described with the transistor represented by the model of Fig.
6.5(d). We can determine from the exponential characteristic of as follows: = 690 mV = 0.69 V Next we determine the value of from where A = 1 mA Thus, Since at +2 V is higher than at 0.69 V, the transistor is indeed operating in the active mode.
Now, replacing the 10-μA current source with a resistance connected from the base to the 5-V dc supply , as in Fig. 6.6(b), the value of must be VBE DB VBE VT IB IS β ⁄ -----------ln = 25 10 10 6 – × 10 17 – ------------------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞ ln = VCE VCE VCC RCIC – = IC βIB 100 10 × 10 6 – × 10 3 – = = = VCE 5 3 1 + 2 V = × – = VC VB RB VCC RB RB VCC VBE – IB --------------------------= 5 0.69 – 10 μA -------------------= 431 kΩ = 6.1 Consider an npn transistor with vBE = 0.7 V at iC = 1 mA. Find vBE at iC = 0.1 mA and 10 mA.
Ans. 0.64 V; 0.76 V 6.2 Transistors of a certain type are specified to have β values in the range 50 to 150. Find the range of their α values.
Ans. 0.980 to 0.993 6.3 Measurement of an npn BJT in a particular circuit shows the base current to be 14.46 μA, the emit-ter current to be 1.460 mA, and the base–emitter voltage to be 0.7 V. For these conditions, calculate α, β, and IS.
Ans. 0.99; 100; 10–15 A 6.4 Calculate β for two transistors for which α = 0.99 and 0.98. For collector currents of 10 mA, find the base current of each transistor.
Ans. 99; 49; 0.1 mA; 0.2 mA EXERCISES 6.1 Device Structure and Physical Operation 361 6.1.3 Structure of Actual Transistors Figure 6.7 shows a more realistic (but still simplified) cross section of an npn BJT. Note that the collector virtually surrounds the emitter region, thus making it difficult for the electrons injected into the thin base to escape being collected. In this way, the resulting α is close to unity and β is large. Also, observe that the device is not symmetrical, and thus the emitter and collector cannot be interchanged.4 For more detail on the physical structure of actual devices, the reader is referred to Appendix A.
The structure in Fig. 6.7 indicates also that the CBJ has a much larger area than the EBJ. Thus the CB diode DC has a saturation current ISC that is much larger than the saturation current of the EB diode DE. Typically, ISC is 10 to 100 times larger than ISE (recall that ISE = IS /α IS). 4If the emitter and collector are reversed—that is, the CBJ is forward biased and the EBJ is reverse biased—the device operates in a mode called the “reverse-active mode.” The resulting values of α and β, denoted αR and βR (with R denoting reverse), are much lower than the values of α and β, respectively, obtained in the “forward” active mode discussed above. Hence, the reverse-active mode has no practical application. The MOSFET, on the other hand, being a perfectly symmetrical device, can operate equally well with its drain and source terminals interchanged. Figure 6.7 Cross-section of an npn BJT.
6.5 A transistor for which IS = 10–16 A and β = 100 is conducting a collector current of 1 mA. Find vBE.
Also, find ISE and ISB for this transistor.
Ans. 747.5 mV; ; 10–18A 6.6 For the circuit in Fig. 6.6(a) analyzed in Example 6.1, find the maximum value of that will still result in active-mode operation.
Ans. 4.31 k 1.01 10 16 – × A RC Ω E B C n n p 6.7 A particular transistor has and . If the CBJ area is 100 times the area of the EBJ, find the collector scale current Ans. A IS 10 15 – A = α 1 ISC.
10 13 – EXERCISE 362 Chapter 6 Bipolar Junction Transistors (BJTs) 6.1.4 Operation in the Saturation Mode5 As mentioned above, for the BJT to operate in the active mode, the CBJ must be reverse biased. Thus far, we have stated this condition for the npn transistor as . However, we know that a pn junction does not effectively become forward biased until the forward voltage across it exceeds approximately 0.4 V. It follows that one can maintain active-mode operation of an npn transistor for negative down to approximately V. This is illus-trated in Fig. 6.8, which is a sketch of versus for an npn transistor operated with a constant emitter current . As expected, is independent of in the active mode, a sit-uation that extends for going negative to approximately V. Below this value of , the CBJ begins to conduct sufficiently that the transistor leaves the active mode and enters the saturation mode of operation, where decreases.
To see why decreases in saturation, we can construct a model for the saturated npn transistor as follows. We augment the model of Fig. 6.5(c) with the forward-conducting CBJ diode , as shown in Fig. 6.9. Observe that the current will subtract from the con-trolled-source current, resulting in the reduced collector current given by (6.14) The second term will play an increasing role as exceeds 0.4 V or so, causing to decrease and eventually reach zero. Figure 6.9 also indicates that in saturation the base current will increase to the value (6.15) 5Saturation in a BJT means something completely different from that in a MOSFET. The saturation mode of operation of the BJT is analogous to the triode region of operation of the MOSFET. On the other hand, the saturation region of operation of the MOSFET corresponds to the active mode of BJT operation.
Figure 6.8 The iC–vCB characteristic of an npn transistor fed with a constant emitter current IE. The transis-tor enters the saturation mode of operation for vCB < –0.4 V, and the collector current diminishes.
vCB 0 ≥ vCB 0.4 – iC vCB IE iC vCB vCB 0.4 – vCB iC iC DC iBC iC iC ISe vBE VT ⁄ ISCe vBC VT ⁄ – = vBC iC iB IS β ⁄ ( )e vBE VT ⁄ ISCe vBC VT ⁄ + = vCB iC Saturation mode Active mode aIE iE IE Expanded scale 0.4 V 0 6.1 Device Structure and Physical Operation 363 Equations (6.14) and (6.15) can be combined to obtain the ratio for a saturated transistor.
We observe that this ratio will be lower than the value of Furthermore, the ratio will decrease as is increased and the transistor is driven deeper into saturation. Because of a satu-rated transistor can be set to any desired value lower than by adjusting this ratio is known as forced β and denoted βforced, (6.16) As will be shown later, in analyzing a circuit we can determine whether the BJT is in the saturation mode by either of the following two tests: 1. Is the CBJ forward biased by more than 0.4 V? 2. Is the ratio lower than ?
The collector-to-emitter voltage of a saturated transistor can be found from Fig. 6.9 as the difference between the forward-bias voltages of the EBJ and the CBJ, (6.17) Recalling that the CBJ has a much larger area than the EBJ, will be smaller than by 0.1 to 0.3 V. Thus, to 0.3 V Typically we will assume that a transistor at the edge of saturation has V, while a transistor deep in saturation has V.
vBE DB DC B C E vBE /VT ISe vBC /VT ISC e iC iB Figure 6.9 Modeling the operation of an npn tran-sistor in saturation by augmenting the model of Fig. 6.5(c) with a forward conducting diode DC. Note that the current through DC increases iB and reduces iC.
iC iB ⁄ β.
vBC iC iB ⁄ β vBC, βforced iC iB ----saturation = β ≤ iC iB ⁄ β vCE VCEsat VBE VBC – = VBC VBE VCEsat 0.1 VCEsat 0.3 = VCEsat 0.2 = 6.8 Use Eq. (6.14) to show that reaches zero at Calculate for a transistor whose CBJ has 100 times the area of the EBJ.
Ans. 115 mV 6.9 Use Eqs. (6.14), (6.15), and (6.16) to show that a BJT operating in saturation with has a forced given by Find βforced for , , and V.
Ans. 22.2 iC VCE VT ISC IS ⁄ ( ) ln = VCE V CE VCEsat = β βforced β e VCEsat VT ⁄ ISC IS ⁄ – e VCEsat VT ⁄ βISC IS ⁄ + ----------------------------------------------= β 100 = ISC IS ⁄ 100 = VCEsat 0.2 = EXERCISES 364 Chapter 6 Bipolar Junction Transistors (BJTs) 6.1.5 The pnp Transistor The pnp transistor operates in a manner similar to that of the npn device described above.
Figure 6.10 shows a pnp transistor biased to operate in the active mode. Here the voltage VEB causes the p-type emitter to be higher in potential than the n-type base, thus forward-biasing the emitter–base junction. The collector–base junction is reverse biased by the voltage V BC, which keeps the p-type collector lower in potential than the n-type base. Unlike the npn transistor, current in the pnp device is mainly conducted by holes injected from the emitter into the base as a result of the forward-bias voltage V EB. Since the component of emitter current contributed by electrons injected from base to emitter is kept small by using a lightly doped base, most of the emitter current will be due to holes. The electrons injected from base to emitter give rise to the first component of base current, iB1.
Also, a number of the holes injected into the base will recombine with the majority carri-ers in the base (electrons) and will thus be lost. The disappearing base electrons will have to be replaced from the external circuit, giving rise to the second component of base cur-rent, iB2. The holes that succeed in reaching the boundary of the depletion region of the collector–base junction will be attracted by the negative voltage on the collector. Thus these holes will be swept across the depletion region into the collector and appear as col-lector current.
It can easily be seen from the above description that the current–voltage relationship of the pnp transistor will be identical to that of the npn transistor except that vBE has to be replaced by vEB. Also, the large-signal, active-mode operation of the pnp transistor can be modeled by any of four equivalent circuits similar to those for the npn transistor in Fig.
6.5. Two of these four circuits are shown in Fig. 6.11. Finally, we note that the pnp tran-sistor can operate in the saturation mode in a manner analogous to that described for the npn device.
Figure 6.10 Current flow in a pnp transistor biased to operate in the active mode.
VEB VBC B C v BC v EB iE iE iE iC iC iB iB iB1 iB2 iC Recombined holes Injected electrons E Forward-biased iE iC p n p Reverse-biased + + – – Injected holes Diffusing holes Collected holes 6.2 Current–Voltage Characteristics 365 6.2 Current–Voltage Characteristics 6.2.1 Circuit Symbols and Conventions The physical structure used thus far to explain transistor operation is rather cumbersome to employ in drawing the schematic of a multitransistor circuit. Fortunately, a very descriptive and convenient circuit symbol exists for the BJT. Figure 6.12(a) shows the symbol for the npn transistor; the pnp symbol is given in Fig. 6.12(b). In both symbols the emitter is distin-guished by an arrowhead. This distinction is important because, as we have seen in the last section, practical BJTs are not symmetric devices. The polarity of the device—npn or pnp—is indicated by the direction of the arrowhead on the emitter. This arrowhead points in the direction of normal current flow in the emitter, which is also the forward direction of the base–emitter junction. Since we have adopted a drawing convention by which currents flow from top to bottom, we will always draw pnp transistors in the manner shown in Fig. 6.12(b) (i.e., with their emitters on top).
Figure 6.13 shows npn and pnp transistors biased to operate in the active mode. It should be mentioned in passing that the biasing arrangement shown, utilizing two dc voltage sources, Figure 6.11 Two large-signal models for the pnp transistor operating in the active mode.
E B C DB iE iB iC (b) vEB VT IS e (ISb) vEB (ISaF) D iB (a) vEBVT IS e iE iC 6.10 Consider the model in Fig. 6.11(a) applied in the case of a pnp transistor whose base is grounded, the emitter is fed by a constant-current source that supplies a 2-mA current into the emitter terminal, and the collector is connected to a –10-V dc supply. Find the emitter voltage, the base current, and the collector current if for this transistor β = 50 and IS = 10–14 A.
Ans. 0.650 V; 39.2 μA; 1.96 mA 6.11 For a pnp transistor having IS = 10–11 A and β = 100, calculate vEB for iC = 1.5 A.
Ans. 0.643 V EXERCISES 366 Chapter 6 Bipolar Junction Transistors (BJTs) is not a usual one and is used here merely to illustrate operation. Practical biasing schemes will be presented in Section 6.7. Figure 6.13 also indicates the reference and actual directions of current flow throughout the transistor. Our convention will be to take the reference direction to coincide with the normal direction of current flow. Hence, normally, we should not encounter a negative value for iE, iB, or iC.
The convenience of the circuit-drawing convention that we have adopted should be obvious from Fig. 6.13. Note that currents flow from top to bottom and that voltages are higher at the top and lower at the bottom. The arrowhead on the emitter also implies the polarity of the emitter–base voltage that should be applied in order to forward bias the emitter– base junction. Just a glance at the circuit symbol of the pnp transistor, for example, indicates that we should make the emitter higher in voltage than the base (by vEB) in order to cause current to flow into the emitter (downward). Note that the symbol vEB means the voltage by which the emitter (E) is higher than the base (B). Thus for a pnp transistor operating in the active mode vEB is positive, while in an npn transistor vBE is positive.
Figure 6.13 Voltage polarities and current flow in transistors biased in the active mode.
npn (a) pnp (b) Figure 6.12 Circuit symbols for BJTs.
(a) (b) 6.2 Current–Voltage Characteristics 367 From the discussion of Section 6.1 it follows that an npn transistor whose EBJ is forward biased will operate in the active mode as long as the collector voltage does not fall below that of the base by more than approximately 0.4 V. Otherwise, the transistor leaves the active mode and enters the saturation region of operation.6 In a parallel manner, the pnp transistor will operate in the active mode if the EBJ is for-ward biased and the collector voltage is not allowed to rise above that of the base by more than 0.4 V or so. Otherwise, the CBJ becomes forward biased, and the pnp transistor enters the saturation region of operation.
For easy reference, we present in Table 6.2 a summary of the BJT current–voltage rela-tionships in the active mode of operation.
The Collector–Base Reverse Current (ICBO) In our discussion of current flow in tran-sistors we ignored the small reverse currents carried by thermally generated minority carriers.
Although such currents can be safely neglected in modern transistors, the reverse current across the collector–base junction deserves some mention. This current, denoted ICBO, is the reverse current flowing from collector to base with the emitter open-circuited (hence the subscript O). This current is usually in the nanoampere range, a value that is many times high-er than its theoretically predicted value. As with the diode reverse current, ICBO contains a sub-stantial leakage component, and its value is dependent on vCB. ICBO depends strongly on temperature, approximately doubling for every 10°C rise.7 Table 6.2 Summary of the BJT Current–Voltage Relationships in the Active Mode Note: For the pnp transistor, replace vBE with vEB.
VT = thermal voltage at room temperature 6It is interesting to contrast the active-mode operation of the BJT with the corresponding mode of oper-ation of the MOSFET: The BJT needs a minimum vCE of about 0.3 V, and the MOSFET needs a mini-mum vDS equal to VOV, which for modern technologies is in the range 0.2 V to 0.3 V. Thus we see a great deal of similarity! Also note that reverse biasing the CBJ of the BJT corresponds to pinching off the channel of the MOSFET. This condition results in the collector current (drain current in the MOSFET) being independent of the collector voltage (the drain voltage in the MOSFET).
7 The temperature coefficient of ICBO is different from that of IS because ICBO contains a substantial leakage component.
iC ISe vBE VT ⁄ = iB iC β ----IS β ----⎝⎠ ⎛⎞e vBE VT ⁄ = = iE iC α ----IS α ----⎝⎠ ⎛⎞e vBE VT ⁄ = = iC αiE = iB 1 α – ( )iE iE β 1 + ------------= = iC βiB = iE β 1 + ( )iB = β α 1 α – ------------= α β β 1 + ------------= kT q ------ 25 mV = 368 Chapter 6 Bipolar Junction Transistors (BJTs) The transistor in the circuit of Fig. 6.14(a) has β = 100 and exhibits a vBE of 0.7 V at iC = 1 mA. Design the circuit so that a current of 2 mA flows through the collector and a voltage of +5 V appears at the collector.
Solution Refer to Fig. 6.14(b). We note at the outset that since we are required to design for VC = +5 V, the CBJ will be reverse biased and the BJT will be operating in the active mode. To obtain a voltage VC = +5 V, the voltage drop across RC must be 15 – 5 = 10 V. Now, since IC = 2 mA, the value of RC should be selected according to Since vBE = 0.7 V at iC = 1 mA, the value of vBE at iC = 2 mA is Since the base is at 0 V, the emitter voltage should be For β = 100, Thus the emitter current should be Now the value required for RE can be determined from Figure 6.14 Circuit for Example 6.2.
15 V 15 V RE RC (a) (b) 15 V 15 V RE VBE RC IB VE VC VBE 0.02 mA 5 V 2 mA IE IC IB 2.02 mA 2 IC RC 10 V 2 mA --------------5 kΩ = = VBE 0.7 VT ln 2 1 ---⎝⎠ ⎛⎞ + 0.717 V = = VE 0.717 – V = α 100 101 ⁄ 0.99.
= = IE IC α ----2 0.99 ----------2.02 mA = = = RE VE − 15 – ( ) IE ---------------------------= Example 6.2 6.2 Current–Voltage Characteristics 369 This completes the design. We should note, however, that the calculations above were made with a degree of precision that is usually neither necessary nor justified in practice in view, for instance, of the expected tolerances of component values. Nevertheless, we chose to do the design precisely in order to illustrate the various steps involved.
0.717 – 15 + 2.02 ------------------------------= 7.07 kΩ = D6.12 Repeat Example 6.2 for a transistor fabricated in a modern integrated-circuit process. Such a proc-ess yields devices that exhibit larger at the same because they have much smaller junction areas. The dc power supplies utilized in modern IC technologies fall in the range of 1 V to 3 V.
Design a circuit similar to that shown in Fig. 6.14 except that now the power supplies are V and the BJT has and exhibits of 0.8 V at mA. Design the circuit so that a current of 2 mA flows through the collector and a voltage of V appears at the collector.
Ans. ; 6.13 In the circuit shown in Fig. E6.13, the voltage at the emitter was measured and found to be –0.7 V. If β = 50, find IE, IB, IC, and VC.
Ans. 0.93 mA; 18.2 μA; 0.91 mA; +5.45 V 6.14 In the circuit shown in Fig. E6.14, measurement indicates VB to be +1.0 V and VE to be +1.7 V.
What are α and β for this transistor? What voltage VC do you expect at the collector?
vBE iC 1.5 ± β 100 = vBE iC 1 = +0.5 RC 500 = Ω RE 338 = Ω VC IC IE IB VE 10 V 10 V 10 k 5 k Figure E6.13 EXERCISES 370 Chapter 6 Bipolar Junction Transistors (BJTs) 6.2.2 Graphical Representation of Transistor Characteristics It is sometimes useful to describe the transistor i–v characteristics graphically. Figure 6.15 shows the iC–vBE characteristic, which is the exponential relationship which is identical to the diode i–v relationship. The iE–vBE and iB–vBE characteristics are also exponential but with different scale currents: for iE, and for iB. Since the constant of the exponential characteristic, is quite high ( 40), the curve rises very sharply. For vBE smaller than about 0.5 V, the current is negligibly small.8 Also, over most of the normal current range vBE lies in the range of 0.6 V to 0.8 V. In performing rapid first-order dc calculations, we normally will assume that VBE 0.7 V, which is similar to the approach used in the analysis of diode circuits (Chapter 4). For a pnp tran-sistor, the iC–vEB characteristic will look identical to that of Fig. 6.15 with vBE replaced with vEB.
As in silicon diodes, the voltage across the emitter–base junction decreases by about 2 mV for each rise of 1°C in temperature, provided the junction is operating at a constant cur-rent. Figure 6.16 illustrates this temperature dependence by depicting iC–vBE curves for an npn transistor at three different temperatures.
8The iC–vBE characteristic is the BJT’s counterpart of the iD–vGS characteristic of the MOSFET. They share an important attribute: In both cases the voltage has to exceed a “threshold” for the device to con-duct appreciably. In the case of the MOSFET, there is a formal threshold voltage, Vt, which lies typi-cally in the range of 0.4 V to 0.8 V. For the BJT, there is an “apparent threshold” of approximately 0.5 V. The iD–vGS characteristic of the MOSFET is parabolic, and thus is less steep than the iC–vBE characteristic of the BJT. This difference has a direct and significant implication for the value of transconductance gm realized with each device.
Ans. 0.994; 165; –1.75 V 10 V 10 V 5 k 100 k 5 k VE VB VC Figure E6.14 iC ISe vBE VT ⁄ = IS α ⁄ IS β ⁄ 1 VT ⁄ , 6.2 Current–Voltage Characteristics 371 6.2.3 Dependence of iC on the Collector Voltage—The Early Effect When operated in the active region, practical BJTs show some dependence of the collector current on the collector voltage, with the result that, unlike the graph shown in Fig. 6.8, their iC–vCB characteristics are not perfectly horizontal straight lines. To see this dependence more clearly, consider the conceptual circuit shown in Fig. 6.17(a). The transistor is connected in Figure 6.15 The iC–vBE characteristic for an npn transistor.
Figure 6.16 Effect of temperature on the iC–vBE characteristic. At a constant emitter current (broken line), vBE changes by 2 mV/°C.
– 6.15 Consider a pnp transistor with vEB = 0.7 V at iE = 1 mA. Let the base be grounded, the emitter be fed by a 2-mA constant-current source, and the collector be connected to a –5-V supply through a 1-kΩ resistance. If the temperature increases by 30°C, find the changes in emitter and collector volt-ages. Neglect the effect of ICBO.
Ans. –60 mV; 0 V.
EXERCISE 372 Chapter 6 Bipolar Junction Transistors (BJTs) the common-emitter configuration; that is, here the emitter serves as a common terminal between the input and output ports. The voltage VBE can be set to any desired value by adjust-ing the dc source connected between base and emitter. At each value of VBE, the correspond-ing iC–vCE characteristic curve can be measured point by point by varying the dc source connected between collector and emitter and measuring the corresponding collector current.
The result is the family of iC–vCE characteristic curves shown in Fig. 6.17(b) and known as common-emitter characteristics.
At low values of vCE (lower than about 0.3 V), as the collector voltage goes below that of the base by more than 0.4 V, the collector–base junction becomes forward biased and the transistor leaves the active mode and enters the saturation mode. Shortly, we shall look at the details of the iC–vCE curves in the saturation region. At this time, however, we wish to examine the characteristic curves in the active region in detail. We observe that the charac-teristic curves, though still straight lines, have finite slope. In fact, when extrapolated, the characteristic lines meet at a point on the negative vCE axis, at vCE = –VA. The voltage VA, a positive number, is a parameter for the particular BJT, with typical values in the range of 10 V to 100 V. It is called the Early voltage, after J. M. Early, the engineering scientist who first studied this phenomenon.
At a given value of vBE, increasing vCE increases the reverse-bias voltage on the collector– base junction, and thus increases the width of the depletion region of this junction (refer to Fig. 6.3). This in turn results in a decrease in the effective base width W. Recalling that IS is inversely proportional to W (Eq. 6.4), we see that IS will increase and that iC increases pro-portionally. This is the Early effect. For obvious reasons, it is also known as the base-width moduation effect.9 Figure 6.17 (a) Conceptual circuit for measuring the iC–vCE characteristics of the BJT.
(b) The iC–vCE characteristics of a practical BJT.
9 Recall that the MOSFET’s counterpart is the channel-length modulation effect. These two effects are remarkably similar and have been assigned the same name, Early effect.
6.2 Current–Voltage Characteristics 373 The linear dependence of iC on vCE can be explicitly accounted for by assuming that IS remains constant and including the factor in the equation for iC as follows: (6.18) The nonzero slope of the iC−vCE straight lines indicates that the output resistance looking into the collector is not infinite. Rather, it is finite and defined by (6.19) Using Eq. (6.18) we can show that (6.20) where IC and VCE are the coordinates of the point at which the BJT is operating on the partic-ular iC– vCE curve (i.e., the curve obtained for vBE equal to constant value at which Eq. (6.19) is evaluated). Alternatively, we can write (6.21) where is the value of the collector current with the Early effect neglected; that is, (6.22) It is rarely necessary to include the dependence of iC on vCE in dc bias design and analysis that is performed by hand. Such an effect, however, can be easily included in the SPICE simulation of circuit operation, which is frequently used to “fine-tune” pencil-and-paper analysis or design.
The finite output resistance ro can have a significant effect on the gain of transistor amplifiers. This is particularly the case in integrated–circuit amplifiers, as will be shown in chapter 7. Fortunately, there are many situations in which ro can be included relatively easily in pencil-and-paper analysis.
The output resistance ro can be included in the circuit model of the transistor. This is illus-trated in Fig. 6.18, where we show the two large-signal circuit models of a common-emitter npn transistor operating in the active mode, those in Fig 6.5(c) and (d), with the resistance ro connected between the collector and the emitter terminals. 1 vCE VA ⁄ + ( ) iC ISe vBE VT ⁄ 1 vCE VA -------+ ⎝ ⎠ ⎛ ⎞ = ro ∂iC ∂vCE ----------vBE = constant 1 – ≡ ro VA VCE + IC ---------------------= VBE ro VA I′ C ------= I′ C I′ C ISe VBE VT ⁄ = 6.16 Use the circuit model in Fig. 6.18(a) to express IC in terms of and vCE and thus show that this circuit is a direct representation of Eq. (6.18).
6.17 Find the output resistance of a BJT for which VA = 100 V at IC = 0.1, 1, and 10 mA.
Ans. 1 MΩ; 100 kΩ; 10 kΩ 6.18 Consider the circuit in Fig. 6.17(a). At VCE = 1 V, VBE is adjusted to yield a collector current of 1 mA.
Then, while VBE is kept constant, VCE is raised to 11 V. Find the new value of IC. For this transistor, VA = 100 V.
Ans. 1.1 mA e vBE VT ⁄ EXERCISES 374 Chapter 6 Bipolar Junction Transistors (BJTs) 6.2.4 An Alternative Form of the Common-Emitter Characteristics An alternative way of expressing the transistor common-emitter characteristics is illustrated in Fig. 6.19. Here the base current iB rather than the base−emitter voltage vBE is used as a parame-ter. That is, each iC−vCE curve is measured with the base fed with a constant current IB. The resulting characteristics, shown in Fig. 6.19(b), look similar to those in Fig. 6.17. Figure 6.19(c) shows an expanded view of the characteristics in the saturation region.
The Common-Emitter Current Gain β In the active region of the characteristics shown in Fig. 6.19(b) we have identified a particular point Q. Note that this operating point for the transistor is characterized by a base current a collector current and a collector–emitter voltage .
The ratio is the transistor β. However, there is another way to measure β : change the base current by an increment and measure the resulting increment while keeping con-stant. This is illustrated in Fig. 6.19(b). The ratio should, according to our study thus far, yield an identical value for β. It turns out, however, that the latter value of β (called incremental, or ac, β ) is a little different from the dc β (i.e., ). Such a distinction, however, is too subtle for our needs in this book. We shall use β to denote both dc and incremental values.10 The Saturation Voltage VCEsat and Saturation Resistance RCEsat Refer next to the expanded view of the common-emitter characteristics in the saturation region shown in Fig.
6.19(c). The “bunching together” of the curves in the saturation region implies that the in-cremental β is lower there than in the active region. A possible operating point in the satu-ration region is that labeled X. It is characterized by a base current IB, a collector current ICsat, and a collector–emitter voltage VCEsat. From our previous discussion of saturation, recall that ICsat = β forced IB, where β forced < β.
The iC−vCE curves in saturation are rather steep, indicating that the saturated transistor exhibits a low collector-to-emitter resistance RCEsat, (6.23) Typically, RCEsat ranges from a few ohms to a few tens of ohms.
Figure 6.18 Large-signal equivalent-circuit models of an npn BJT operating in the active mode in the common-emitter configuration with the output resistance ro included.
10Manufacturers of bipolar transistors use hFE to denote the dc value of β and hfe to denote the incremen-tal β. These symbols come from the h-parameter description of two-port networks (see Appendix C), with the subscript F(f) denoting forward and E(e) denoting common emitter.
ro E B C iB DB (ISb) ISevBEVT iC iE vBE (a) ro E B iB DB (ISb) biB iE vBE (b) C iC IB, IC, V CE IC IB ⁄ iB Δ iC, Δ V CE iC iB Δ ⁄ Δ IC IB ⁄ RCEsat ∂vCE ∂iC ----------iC = ICsat iB = IB ≡ 6.2 Current–Voltage Characteristics 375 That the collector-to-emitter resistance of a saturated BJT is small should have been anticipated from the fact that between C and E we now have two forward-conducting diodes in series11 (see also Fig. 6.9).
Figure 6.19 Common-emitter characteristics. (a) Basic CE circuit; note that in (b) the horizontal scale is expanded around the origin to show the saturation region in some detail. A much greater expansion of the saturation region is shown in (c).
11In the corresponding mode of operation for the MOSFET, the triode region, the resistance between drain and source is small because it is the resistance of the continuous (non-pinched-off) channel.
Q 0 (a) (b) iB = IB + ΔiB ΔiC iB = IB iB = 0 VCE IC iC iC iB IB iB = . . .
iB = IB1 . . .
iB = IB2 . . .
Saturation region Active region vCE vCE X bIB ICsat VCEsat Slope RCEsat 1 iB IB (c) 376 Chapter 6 Bipolar Junction Transistors (BJTs) A simple model for the saturated BJT is shown in Fig. 6.20. Here is assumed con-stant (approximately 0.7 V) and also is assumed constant, V. That is, we have neglected the small saturation resistance for the sake of making the model sim-ple for hand calculations. VBE VCE VCEsat 0.2 RCEsat E 0.2 V B IB ICsat VBE 0.7 V VCEsat Figure 6.20 A simplified equivalent-circuit model of the saturated transistor.
For the circuit in Fig. 6.21, it is required to determine the value of the voltage that results in the tran-sistor operating (a) in the active mode with V (b) at the edge of saturation (c) deep in saturation with For simplicity, assume that remains constant at 0.7 V. The transistor β is specified to be 50.
Solution (a) To operate in the active mode with V, mA V BB VCE 5 = βforced 10 = VBE VBB RC 1 k RB 10 k VCC 10V VBE VCE IC IB Figure 6.21 Circuit for Example 6.3.
VCE 5 = IC VCC VCE – RC --------------------------= 10 5 – 1 kΩ ---------------5 = = Example 6.3 6.2 Current–Voltage Characteristics 377 mA Now the required value of can be found as follows: (b) Operation at the edge of saturation is obtained with V. Thus mA Since, at the edge of saturation, and are still related by β, mA The required value of can be determined as V (c) To operate deep in saturation, V Thus, mA We then use the value of forced β to determine the required value of as mA and the required can now be found as V Observe that once the transistor is in saturation, increasing and thus results in negligible change in since will change only slightly. Thus is said to saturate, which is the origin of the name “saturation mode of operation.” IB IC β ----5 50 ------0.1 = = = VBB VBB IBRB VBE + = 0.1 10 0.7 + × 1.7 V = = VCE 0.3 = IC 10 0.3 – 1 -------------------9.7 = = IC IB IB 9.7 50 -------= 0.194 = VBB V BB 0.194 10 0.7 2.64 = + × = VCE VCEsat 0.2 = IC 10 0.2 – 1 -------------------9.8 = = IB IB IC βforced --------------9.8 10 -------0.98 = = = VBB VBB 0.98 10 0.7 10.5 = + × = VBB IB IC VCEsat IC 6.19 Repeat Example 6.3 for k Ans. 0.8 V; 0.894 V; 1.68 V 6.20 For the circuit in Fig. 6.21, find for V.
Ans. + 10 V 6.21 For the circuit in Fig. 6.21, let be set to the value obtained in Example 6.3, part (a), namely, V. Verify that the transistor is indeed operating in the active mode. Now, while keeping constant, find that value to which should be increased in order to obtain (a) operation at the edge of saturation, and (b) operation deep in saturation with .
Ans. (a) 1.94 k (b) 9.8 k RC 10 = Ω.
VCE VBB 0 = VBB VBB 1.7 = V BB RC βforced 10 = Ω; Ω EXERCISES 378 Chapter 6 Bipolar Junction Transistors (BJTs) 6.3 BJT Circuits at DC We are now ready to consider the analysis of BJT circuits to which only dc voltages are applied. In the following examples we will use the simple model in which of a con-ducting transistor is 0.7 V and of a saturated transistor is 0.2 V, and we will neglect the Early effect. Better models can, of course, be used to obtain more accurate results. This, however, is usually achieved at the expense of speed of analysis, and more importantly, it could impede the circuit designer’s ability to gain insight regarding circuit behavior. Accu-rate results using elaborate models can be obtained using circuit simulation with SPICE.
This is almost always done in the final stages of a design and certainly before circuit fabrica-tion. Computer simulation, however, is not a substitute for quick pencil-and-paper circuit analysis, an essential ability that aspiring circuit designers must muster. The following series of examples is a step in that direction.
As will be seen, in analyzing a circuit the first question that one must answer is: In which mode is the transistor operating? In some cases, the answer will be obvious. For instance, a quick check of the terminal voltages will indicate whether the transistor is cut off or conducting. If it is conducting, we have to determine whether it is operating in the active mode or in saturation. In some cases, however, this may not be obvious. Needless to say, as the reader gains practice and experience in transistor circuit analysis and design, the answer will be apparent in a much larger proportion of problems. The answer, however, can always be determined by utilizing the following procedure: Assume that the transistor is operating in the active mode, and proceed to determine the various voltages and currents that correspond. Then check for consistency of the results with the assumption of active-mode operation; that is, is vCB of an npn transistor greater than −0.4 V (or vCB of a pnp transistor lower than 0.4 V)? If the answer is yes, then our task is complete. If the answer is no, assume saturation-mode operation, and proceed to determine currents and voltages and then to check for consistency of the results with the assumption of saturation-mode operation. Here the test is usually to compute the ratio and to verify that it is lower than the transistor β (i.e., βforced < β ). Since β for a given transistor type varies over a wide range,12 one must use the lowest specified β for this test. Finally, note that the order of these two assumptions can be reversed. As a further aid to the reader, we provide in Table 6.3 a summary of the conditions and models for the operation of the BJT in its three possible modes.
12That is, if one buys BJTs of a certain part number, the manufacturer guarantees only that their values of β fall within a certain range, say 50 to 150.
VBE VCE IC IB ⁄ 6.3 BJT Circuits at DC 379 Table 6.3 Conditions and Models for the Operation of the BJT in Various Modes npn pnp Cutoff EJB: Reverse Biased CBJ: Reverse Biased Active EBJ: Forward Biased CBJ: Reverse Biased Saturation EBJ: Forward Biased CBJ: Forward Biased IB IC VBE VBC VCE IB IC VCB VEB VEC IB O IC O VBE < 0.5 V VBC < 0.4 V E B C VEB < 0.5 V IB O IC O VCB < 0.4 V E C B IC bIB IB > 0 E B C VBE 0.7 V bIB VBC < 0.4 V VCE > 0.3 V IC bIB IB > 0 E B C VEB 0.7 V bIB VCB < 0.4 V VEC > 0.3 V IC bforced IB IB > 0 E B C VBE 0.7 V VBC 0.5 V VCEsat 0.2 V IB > 0 E B C IC = bforcedIB VEB 0.7 V VCB 0.5 V VECsat 0.2 V 380 Chapter 6 Bipolar Junction Transistors (BJTs) Consider the circuit shown in Fig. 6.22(a), which is redrawn in Fig. 6.22(b) to remind the reader of the convention employed throughout this book for indicating connections to dc sources. We wish to analyze this circuit to determine all node voltages and branch currents. We will assume that β is specified to be 100.
Solution Glancing at the circuit in Fig. 6.22(a), we note that the base is connected to +4 V and the emitter is con-nected to ground through a resistance RE. Therefore, it is safe to conclude that the base–emitter junction Figure 6.22 Analysis of the circuit for Example 6.4: (a) circuit; (b) circuit redrawn to remind the reader of the con-vention used in this book to show connections to the power supply; (c) analysis with the steps numbered.
(a) 10 V 4 V RE 3.3 k RC 4.7 k IC IE VE VC IB (b) 4 V 10 V RC 4.7 k RE 3.3 k 10 V 4 V 3.3 k 4.7 k 0.99 1 0.99 mA 1.00 0.99 0.01 mA 10 0.99 4.7 5.3 V 4 0.7 3.3 V 1 mA 3.3 3.3 1 2 3 4 5 (c) Example 6.4 6.3 BJT Circuits at DC 381 will be forward biased. Assuming that this is the case and assuming that VBE is approximately 0.7 V, it fol-lows that the emitter voltage will be We are now in an opportune position; we know the voltages at the two ends of RE and thus can determine the current IE through it, Since the collector is connected through RC to the +10-V power supply, it appears possible that the collec-tor voltage will be higher than the base voltage, which implies active-mode operation. Assuming that this is the case, we can evaluate the collector current from The value of α is obtained from Thus IC will be given by We are now in a position to use Ohm’s law to determine the collector voltage VC, Since the base is at +4 V, the collector–base junction is reverse biased by 1.3 V, and the transistor is indeed in the active mode as assumed.
It remains only to determine the base current IB, as follows: Before leaving this example we wish to emphasize strongly the value of carrying out the analysis directly on the circuit diagram. Only in this way will one be able to analyze complex circuits in a reason-able length of time. Figure 6.22(c) illustrates the above analysis on the circuit diagram, with the order of the analysis steps indicated by the circled numbers. VE 4 VBE 4 – 0.7 – 3.3 V = = IE VE 0 – RE ---------------3.3 3.3 -------1 mA = = = IC αIE = α β β 1 + ------------100 101 --------- 0.99 = = IC 0.99 1 0.99 mA = × = VC 10 ICRC – 10 0.99 4.7 5.3 V + × – = = IB IE β 1 + ------------1 101 --------- 0.01 mA = = 382 Chapter 6 Bipolar Junction Transistors (BJTs) We wish to analyze the circuit of Fig. 6.23(a) to determine the voltages at all nodes and the currents through all branches. Note that this circuit is identical to that of Fig. 6.22 except that the voltage at the base is now +6 V. Assume that the transistor β is specified to be at least 50.
Figure 6.23 Analysis of the circuit for Example 6.5. Note that the circled numbers indicate the order of the analy-sis steps.
(a) 10 V 6 V 4.7 k 3.3 k (b) 10 V 6 V 4.7 k 3.3 k 1.6 mA 5.3 1.6 mA 1 2 3 4 10 1.6 4.7 2.48 Impossible, not in active mode 6 0.7 5.3 V 3.3 (c) Example 6.5 6.3 BJT Circuits at DC 383 Solution With +6 V at the base, the base–emitter junction will be forward biased; thus, and Now, assuming active-mode operation, IC = αIE IE; thus, The details of the analysis performed above are illustrated in Fig. 6.23(b).
Since the collector voltage calculated appears to be less than the base voltage by 3.52 V, it follows that our original assumption of active-mode operation is incorrect. In fact, the transistor has to be in the saturation mode. Assuming this to be the case, the values of VE and IE will remain unchanged. The collec-tor voltage, however, becomes from which we can determine IC as and IB can now be found as Thus the transistor is operating at a forced β of Since βforced is less than the minimum specified value of β, the transistor is indeed saturated. We should emphasize here that in testing for saturation the minimum value of β should be used. By the same token, if we are designing a circuit in which a transistor is to be saturated, the design should be based on the minimum specified β. Obviously, if a transistor with this minimum β is saturated, then transistors with higher values of β will also be saturated. The details of the analysis are shown in Fig. 6.23(c), where the order of the steps used is indicated by the circled numbers.
VE +6 VBE 6 0.7 5.3 V = – – = IE 5.3 3.3 -------1.6 mA = = VC +10 4.7 IC 10 7.52 – × – 2.48 V = = VC VE VCEsat +5.3 0.2 + + +5.5 V = = IC +10 5.5 – 4.7 -----------------------0.96 mA = = IB IE IC – 1.6 0.96 0.64 mA = – = = βforced IC IB ----0.96 0.64 ----------1.5 = = = 384 Chapter 6 Bipolar Junction Transistors (BJTs) We wish to analyze the circuit in Fig. 6.24(a) to determine the voltages at all nodes and the currents through all branches. Note that this circuit is identical to that considered in Examples 6.4 and 6.5 except that now the base voltage is zero.
Solution Since the base is at zero volts and the emitter is connected to ground through RE, the base–emitter junction can-not conduct and the emitter current is zero. Note that this situation will obtain as long as the voltage at the base is less than 0.5 V or so. Also, the collector–base junction cannot conduct, since the n-type collector is connected through RC to the positive power supply while the p-type base is at ground. It follows that the collector current will be zero. The base current will also have to be zero, and the transistor is in the cutoff mode of operation.
The emitter voltage will be zero, while the collector voltage will be equal to +10 V, since the voltage drops across RE and RC are zero. Figure 6.24(b) shows the analysis details.
Figure 6.24 Example 6.6: (a) circuit; (b) analysis, with the order of the analysis steps indicated by circled numbers.
(a) (b) 1 2 Example 6.6 D6.22 For the circuit in Fig. 6.22(a), find the highest voltage to which the base can be raised while the transistor remains in the active mode. Assume α 1.
Ans. +4.7 V D6.23 Redesign the circuit of Fig. 6.22(a) (i.e., find new values for RE and RC) to establish a collector current of 0.5 mA and a reverse-bias voltage on the collector–base junction of 2 V. Assume α 1.
Ans. RE = 6.6 kΩ; RC = 8 kΩ 6.24 For the circuit in Fig. 6.23(a), find the value to which the base voltage should be changed so that the transistor operates in saturation with a forced β of 5.
Ans. +5.18 V EXERCISES 6.3 BJT Circuits at DC 385 We want to analyze the circuit of Fig. 6.25(a) to determine the voltages at all nodes and the currents through all branches.
Solution The base of this pnp transistor is grounded, while the emitter is connected to a positive supply (V+ = +10 V) through RE. It follows that the emitter–base junction will be forward biased with Thus the emitter current will be given by Since the collector is connected to a negative supply (more negative than the base voltage) through RC, it is possible that this transistor is operating in the active mode. Assuming this to be the case, we obtain Since no value for β has been given, we shall assume β = 100, which results in α = 0.99. Since large vari-ations in β result in small differences in α, this assumption will not be critical as far as determining the value of IC is concerned. Thus, The collector voltage will be Figure 6.25 Example 6.7: (a) circuit; (b) analysis, with the steps indicated by circled numbers.
V 10 V RE 2 k RC 1 k V 10 V (a) 10 V 2 k 0.05 mA 10 0.7 2 4.65 mA 0.7 V 1 2 3 4 5 1 k 10 V 0.99 4.65 4.6 mA 10 4.6 1 5.4 V (b) VE VEB 0.7 V = IE V+ VE – RE ------------------10 0.7 – 2 -------------------4.65 mA = = = IC αIE = IC 0.99 4.65 × 4.6 mA = = VC V − ICRC + = = −10 4.6 1 × + 5.4 V – = Example 6.7 386 Chapter 6 Bipolar Junction Transistors (BJTs) EXAMPLE 5.7 Thus the collector–base junction is reverse biased by 5.4 V, and the transistor is indeed in the active mode, which supports our original assumption.
It remains only to calculate the base current, Obviously, the value of β critically affects the base current. Note, however, that in this circuit the value of β will have no effect on the mode of operation of the transistor. Since β is generally an ill-specified parameter, this circuit represents a good design. As a rule, one should strive to design the circuit such that its perfor-mance is as insensitive to the value of β as possible. The analysis details are illustrated in Fig. 6.25(b).
IB IE β 1 + ------------4.65 101 ---------- 0.05 mA = = D6.25 For the circuit in Fig. 6.25(a), find the largest value to which RC can be raised while the transistor remains in the active mode.
Ans. 2.26 kΩ D6.26 Redesign the circuit of Fig. 6.25(a) (i.e., find new values for RE and RC) to establish a collector current of 1 mA and a reverse bias on the collector–base junction of 4 V. Assume α 1.
Ans. RE = 9.3 kΩ; RC = 6 kΩ EXERCISES We want to analyze the circuit in Fig. 6.26(a) to determine the voltages at all nodes and the currents in all branches. Assume β = 100.
Figure 6.26 Example 6.8: (a) circuit; (b) analysis, with the steps indicated by the circled numbers.
(a) (b) Example 6.8 6.3 BJT Circuits at DC 387 Solution The base–emitter junction is clearly forward biased. Thus, Assume that the transistor is operating in the active mode. We now can write The collector voltage can now be determined as Since the base voltage VB is it follows that the collector–base junction is reverse-biased by 0.7 V and the transistor is indeed in the active mode. The emitter current will be given by We note from this example that the collector and emitter currents depend critically on the value of β. In fact, if β were 10% higher, the transistor would leave the active mode and enter saturation. Therefore this clearly is a bad design. The analysis details are illustrated in Fig. 6.26(b).
IB +5 VBE – RB --------------------- 5 0.7 – 100 ----------------0.043 mA = = IC βIB 100 0.043 × 4.3 mA = = = VC +10 ICRC – 10 4.3 2 × – +1.4 V = = = VB VBE +0.7 V = IE β 1 + ( )IB 101 0.043 4.3 mA × = = D6.27 The circuit of Fig. 6.26(a) is to be fabricated using a transistor type whose β is specified to be in the range of 50 to 150. That is, individual units of this same transistor type can have β values anywhere in this range. Redesign the circuit by selecting a new value for RC so that all fabricated circuits are guaranteed to be in the active mode. What is the range of collector voltages that the fabricated circuits may exhibit?
Ans. RC = 1.5 kΩ; VC = 0.3 V to 6.8 V EXERCISE 388 Chapter 6 Bipolar Junction Transistors (BJTs) We want to analyze the circuit of Fig. 6.27 to determine the voltages at all nodes and the currents through all branches. The minimum value of β is specified to be 30.
Solution A quick glance at this circuit reveals that the transistor will be either active or saturated. Assuming active-mode operation and neglecting the base current, we see that the base voltage will be approximately zero volts, the emitter voltage will be approximately +0.7 V, and the emitter current will be approximately 4.3 mA. Since the maximum current that the collector can support while the transistor remains in the active mode is approximately 0.5 mA, it follows that the transistor is definitely saturated.
Assuming that the transistor is saturated and denoting the voltage at the base by VB (refer to Fig.
6.27b), it follows that Figure 6.27 Example 6.9: (a) circuit; (b) analysis with steps numbered.
10 k 5 V 10 k 1 k 5 V (a) VB 5 V 5 V 10 k 1 k 10 k VEC sat 0.5 10 VB VB VC 0.2 V VE 0.7 VB IB /10 VB 5 ( 1 VB 0.7) IE 0.5 (5) 1 2 3 4 5 6 7 IC (b) VE VB VEB VB 0.7 + + = VC VE VECsat VB 0.7 0.2 – + – VB 0.5 + = = IE +5 VE – 1 -------------------5 VB – 0.7 – 1 ----------------------------4.3 VB mA – = = = IB VB 10 ------0.1VB mA = = IC VC – 5 – ( ) 10 -----------------------VB 0.5 5 + + 10 -----------------------------0.1VB 0.55 mA + = = = Example 6.9 6.3 BJT Circuits at DC 389 Using the relationship IE = IB + IC, we obtain which results in Substituting in the equations above, we obtain from which we see that the transistor is saturated, since the value of forced β is which is much smaller than the specified minimum β.
4.3 VB – 0.1VB 0.1VB 0.55 + + = VB 3.75 1.2 ---------- 3.13 V = VE 3.83 V = VC 3.63 V = IE 1.17 mA = IC 0.86 mA = IB 0.31 mA = βforced 0.86 0.31 ---------- 2.8 = 390 Chapter 6 Bipolar Junction Transistors (BJTs) We want to analyze the circuit of Fig. 6.28(a) to determine the voltages at all nodes and the currents through all branches. Assume β = 100.
Solution The first step in the analysis consists of simplifying the base circuit using Thévenin’s theorem. The result is shown in Fig. 6.28(b), where RB1 100 k RB2 50 k (a) RC 5 k RE 3 k 15 V RC 5 k RE 3 k (b) VBB 5 V RBB 33.3 k L IB IE 15 V (c) 15 V 1.28 mA 5 V 0.013 mA 4.57 V 1.29 mA 33.3 k 3 k 3.87 V 8.6 V 5 k (d) 15 V 100 k 50 k 0.103 mA 0.013 mA 4.57 V 0.09 mA Figure 6.28 Circuits for Example 6.10.
VBB +15 RB2 RB1 RB2 + -----------------------15 50 100 50 + ---------------------+5 V = = = Example 6.10 6.3 BJT Circuits at DC 391 To evaluate the base or the emitter current, we have to write a loop equation around the loop labeled L in Fig. 6.28(b). Note, however, that the current through RBB is different from the current through RE. The loop equation will be Now, assuming active-mode operation, we replace IB with and rearrange the equation to obtain For the numerical values given we have The base current will be The base voltage is given by We can evaluate the collector current as The collector voltage can now be evaluated as It follows that the collector is higher in potential than the base by 4.03 V, which means that the transistor is in the active mode, as had been assumed. The results of the analysis are given in Fig. 6.28(c, d).
RBB RB1 || RB2 100 || 50 33.3 kΩ = = = VBB IBRBB VBE IERE + + = IB IE β 1 + ------------= IE VBB VBE – RE RBB β 1 + ( ) ⁄ [ ] + ------------------------------------------------= IE 5 0.7 – 3 33.3 101 ⁄ ( ) + -------------------------------------1.29 mA = = IB 1.29 101 ----------0.0128 mA = = VB VBE IERE + = 0.7 1.29 + 3 × = 4.57 V = IC αIE 0.99 1.29 × 1.28 mA = = = VC +15 ICRC – 15 1.28 5 × – 8.6 V = = = 6.28 If the transistor in the circuit of Fig. 6.28(a) is replaced with another having half the value of β (i.e., β = 50), find the new value of IC, and express the change in IC as a percentage.
Ans. IC = 1.15 mA; −10% EXERCISE 392 Chapter 6 Bipolar Junction Transistors (BJTs) We want to analyze the circuit in Fig. 6.29(a) to determine the voltages at all nodes and the currents through all branches.
Solution We first recognize that part of this circuit is identical to the circuit we analyzed in Example 6.10—namely, the circuit of Fig. 6.28(a). The difference, of course, is that in the new circuit we have an additional Figure 6.29 Circuits for Example 6.11.
RB2 (a) 2 k IC2 2.7 k RC1 IE2 RC2 RE 5 k 100 k 50 k 3 k RB1 IC1 IB2 RE2 15 V Q1 Q2 (b) 15 V Q1 Q2 100 k 5 k 2 k 50 k 3 k 2.7 k 0.103 mA 1.252 mA 2.78 mA 9.44 V 8.74 V 0.0275 mA 1.28 mA 4.57 V 0.013 mA 3.87 V 7.43 V 0.09 mA 1.29 mA 2.75 mA Example 6.11 6.3 BJT Circuits at DC 393 transistor Q2 together with its associated resistors RE2 and RC2. Assume that Q1 is still in the active mode.
The following values will be identical to those obtained in the previous example: VB1 = +4.57 V IE1 = 1.29 mA IB1 = 0.0128 mA IC1 = 1.28 mA However, the collector voltage will be different than previously calculated, since part of the collector cur-rent IC1 will flow in the base lead of Q2 (IB2). As a first approximation we may assume that IB2 is much smaller than IC1; that is, we may assume that the current through RC1 is almost equal to IC1. This will enable us to calculate VC1: Thus Q1 is in the active mode, as had been assumed.
As far as Q2 is concerned, we note that its emitter is connected to +15 V through RE2. It is therefore safe to assume that the emitter–base junction of Q2 will be forward biased. Thus the emitter of Q2 will be at a voltage VE2 given by The emitter current of Q2 may now be calculated as Since the collector of Q2 is returned to ground via RC2, it is possible that Q2 is operating in the active mode. Assume this to be the case. We now find IC2 as The collector voltage of Q2 will be which is lower than VB2 by 0.98 V. Thus Q2 is in the active mode, as assumed.
It is important at this stage to find the magnitude of the error incurred in our calculations by the assumption that IB2 is negligible. The value of IB2 is given by which is indeed much smaller than IC1 (1.28 mA). If desired, we can obtain more accurate results by iter-ating one more time, assuming IB2 to be 0.028 mA. The new values will be VC1 +15 IC1RC1 – 15 1.28 5 × – = +8.6 V = VE2 VC1 VEB Q2 8.6 0.7 + + +9.3 V = = IE2 +15 VE2 – RE2 ------------------------15 9.3 – 2 -------------------2.85 mA = = = IC2 α2IE2 = 0.99 2.85 × = 2.82 mA = assuming β2 100 = ( ) VC2 IC2RC2 2.82 2.7 × 7.62 V = = = IB2 IE2 β2 1 + --------------2.85 101 ----------0.028 mA = = = Current in RC1 IC1 IB2 – 1.28 0.028 – 1.252 mA = = = VC1 15 5 1.252 × – 8.74 V = = VE2 8.74 0.7 + 9.44 V = = IE2 15 9.44 – 2 ----------------------2.78 mA = = 394 Chapter 6 Bipolar Junction Transistors (BJTs) In the above examples, we frequently used a precise value of α to calculate the collector current. Since α 1, the error in such calculations will be very small if one assumes α = 1 and IC = IE. Therefore, except in calculations that depend critically on the value of α (e.g., the calcula-tion of base current), one usually assumes α 1.
Example 6.11 continued Note that the new value of IB2 is very close to the value used in our iteration, and no further iterations are warranted. The final results are indicated in Fig. 6.29(b).
The reader justifiably might be wondering about the necessity for using an iterative scheme in solv-ing a linear (or linearized) problem. Indeed, we can obtain the exact solution (if we can call anything we are doing with a first-order model exact!) by writing appropriate equations. The reader is encouraged to find this solution and then compare the results with those obtained above. It is important to emphasize, however, that in most such problems it is quite sufficient to obtain an approximate solution, provided we can obtain it quickly and, of course, correctly.
IC2 0.99 2.78 × 2.75 mA = = VC2 2.75 2.7 × 7.43 V = = IB2 2.78 101 ----------0.0275 mA = = 6.29 For the circuit in Fig. 6.29, find the total current drawn from the power supply. Hence find the power dissipated in the circuit.
Ans. 4.135 mA; 62 mW 6.30 The circuit in Fig. E6.30 is to be connected to the circuit in Fig. 6.29(a) as indicated; specifically, the base of Q3 is to be connected to the collector of Q2. If Q3 has β = 100, find the new value of VC2 and the values of VE3 and IC3.
Ans. +7.06 V; +6.36 V; 13.4 mA 6.29 Figure E6.30 EXERCISES 6.3 BJT Circuits at DC 395 We desire to evaluate the voltages at all nodes and the currents through all branches in the circuit of Fig.
6.30(a). Assume β = 100.
Solution By examining the circuit, we conclude that the two transistors Q1 and Q2 cannot be simultaneously conducting.
Thus if Q1 is on, Q2 will be off, and vice versa. Assume that Q2 is on. It follows that current will flow from ground through the 1-kΩ resistor into the emitter of Q2. Thus the base of Q2 will be at a negative voltage, and base current will be flowing out of the base through the 10-kΩ resistor and into the +5-V supply. This is impos-sible, since if the base is negative, current in the 10-kΩ resistor will have to flow into the base. Thus we con-clude that our original assumption—that Q2 is on—is incorrect. It follows that Q2 will be off and Q1 will be on.
The question now is whether Q1 is active or saturated. The answer in this case is obvious: Since the base is fed with a +5-V supply and since base current flows into the base of Q1, it follows that the base of Q1 will be at a voltage lower than +5 V. Thus the collector–base junction of Q1 is reverse biased and Q1 is in the active mode. It remains only to determine the currents and voltages using tech-niques already described in detail. The results are given in Fig. 6.30(b). Figure 6.30 Example 6.12: (a) circuit; (b) analysis with the steps numbered.
(a) (b) 3.9 mA 0 –5V Off 0 5 – 0.7 10 + 101 × 1 0.039 mA = On Example 6.12 6.31 Solve the problem in Example 6.12 for the case of a voltage of –5 V feeding the bases. What voltage appears at the emitters?
Ans. –3.9 V 6.32 Solve the problem in Example 6.12 with the voltage feeding the bases changed to +10 V. Assume that βmin = 30, and find VE, VB, IC1, and IC2.
Ans. +4.8 V; +5.5 V; 4.35 mA; 0 EXERCISES 396 Chapter 6 Bipolar Junction Transistors (BJTs) 6.4 Applying the BJT in Amplifier Design We now begin our study of the utilization of the BJT in the design of amplifiers.13 The basis for this important application is that when operated in the active mode, the BJT functions as a voltage-controlled current source: the base–emitter voltage controls the collector current . Although the control relationship is nonlinear (exponential), we will shortly devise a method for obtaining almost-linear amplification from this fundamentally nonlinear device.
6.4.1 Obtaining a Voltage Amplifier In the introduction to amplifiers in Section 1.5, we learned that a voltage-controlled current source can serve as a transconductance amplifier, that is, an amplifier whose input signal is a voltage and whose output signal is a current. More commonly, however, one is interested in voltage amplifiers. A simple way to convert a transconductance amplifier to a voltage ampli-fier is to pass the output current through a resistor and take the voltage across the resistor as the output. Doing this for a BJT results in the simple amplifier circuit shown in Fig. 6.31(a). Here is the input voltage, (known as a load resistance) converts the collector current to a voltage ( ), and is the supply voltage that powers up the amplifier and, together with , establishes operation in the active mode, as will be shown shortly.
In the amplifier circuit of Fig. 6.31(a), the output voltage is taken between the collector and ground, rather than simply across . This is done because of the need to maintain a ground reference throughout the circuit. The output voltage is given by (6.24) Thus it is an inverted version (note the minus sign) of that is shifted by the constant value of the supply voltage 13An introduction to amplifiers from an external terminals perspective is presented in Sections 1.4 and 1.5. It would be helpful for readers unfamiliar with basic amplifier concepts to review this material be-fore proceeding with the study of BJT amplifiers.
vBE iC vBE RC iC iCRC VCC RC vBE vO vCE RC VCC 0 0.5 V vBE X Y Z iC 0.3 V Edge of Saturation Cut off Saturation Active mode Figure 6.31 (a) Simple BJT amplifier with input vBE and output vCE. (b) The voltage transfer characteristic (VTC) of the amplifier in (a). The three segments of the VTC correspond to the three modes of operation of the BJT.
RC vCE vCE VCC iCRC – = iCRC VCC.
6.4 Applying the BJT in Amplifier Design 397 6.4.2 The Voltage Transfer Characteristic (VTC) A very useful tool that yields great insight into the operation of an amplifier circuit is its voltage transfer characteristic (VTC). This is simply a plot (or a clearly labeled sketch) of the output voltage versus the input voltage. For the BJT amplifier in Fig. 6.31(a), this is the plot of versus shown in Fig. 6.31(b).
Observe that for lower than about 0.5 V, the transistor is cut off, , and, from Eq. (6.24), As rises, the transistor turns on and decreases. However, since initially will still be high, the BJT will be operating in the active mode. This con-tinues as is increased until it reaches a value that results in becoming lower than by 0.4 volt or so (point Z on the VTC in Fig. 6.31b). For greater than that at point Z, the transistor operates in the saturation region and decreases very slowly. The VTC in Fig. 6.31(b) indicates that the segment of greatest slope (and hence poten-tially the largest amplifier gain) is that labeled YZ, which corresponds to operation in the active mode. An expression for the segment YZ can be obtained by substituting for in Eq.
(6.24) by its active-mode value (6.25) where we have for simplicity neglected base-width modulation (the Early effect). The result is (6.26) This is obviously a nonlinear relationship. Nevertheless, linear (or almost-linear) amplifica-tion can be obtained by using the technique of biasing the BJT. 6.4.3 Biasing the BJT to Obtain Linear Amplification Biasing enables us to obtain almost-linear amplification from the BJT. The technique is illustrated in Fig. 6.32(a). A dc voltage is selected to obtain operation at a point Q on the segment YZ of the VTC. How to select an appropriate location for the bias point Q will be discussed shortly. For the time being, observe that the coordinates of Q are the dc vCE vBE vBE iC 0 = vCE VCC.
= vBE vCE vCE vBE vCE vBE vBE vCE iC iC IS e vBE VT ⁄ = vCE VCC RCIS e vBE VT ⁄ – = V BE VBE VCE RC VCC VCC vCE 0 VBE vBE X Y IC VCE Z Q Figure 6.32 Biasing the BJT amplifier at a point Q located on the active-mode segment of the VTC.
398 Chapter 6 Bipolar Junction Transistors (BJTs) voltages and , which are related by (6.27) Point Q is known as the bias point or the dc operating point. Also, since at Q no signal component is present, it is also known as the quiescent point (which is the origin of the symbol Q). Note that a transistor operating at Q will have a collector current given by (6.28) Next, the signal to be amplified a function of time is superimposed on the bias voltage as shown in Fig. 6.33(a). Thus the total instantaneous value of becomes The resulting can be obtained by substituting this expression for into Eq. (6.25).
Graphically, we can use the VTC to obtain point by point, as illustrated in Fig. 6.33(b).
VBE VCE VCE VCC RCIS e VBE VT ⁄ – = IC IC IS e VBE VT ⁄ = vbe.
t, V BE, vBE vBE t ( ) VBE vbe t ( ) + = vCE t ( ) vBE t ( ) vCE t ( ), (a) RC VCC vBE vbe VBE vCE iC (b) vBE vce Q Z X Slope Av Time Time 0 vCE VCC VCE vbe Cutoff Saturation Active mode 0.5 Y VBE Figure 6.33 BJT amplifier biased at a point Q, with a small voltage signal vbe superimposed on the dc bias voltage VBE.
The resulting output signal vce appears superimposed on the dc collector voltage VCE. The amplitude of vce is larger than that of vbe by the voltage gain Av.
6.4 Applying the BJT in Amplifier Design 399 Here we show the case when is a sine wave of “small” amplitude. Specifically, the amplitude of is small enough to restrict the excursion of the instantaneous operating point to a short almost-linear segment of the VTC around the bias point Q. The shorter the segment, the greater the linearity achieved, and the closer to an ideal sine wave the signal component at the output, will be. This is the essence of obtaining linear amplification from the nonlinear BJT.
6.4.4 The Small-Signal Voltage Gain If the input signal is kept small, the corresponding signal at the output will be nearly proportional to with the constant of proportionality being the slope of the almost-linear segment of the VTC around Q. This is the voltage gain of the amplifier, and its value can be determined by evaluating the slope of the tangent to the VTC at the bias point Q, (6.29) Utilizing Eq. (6.26) together with Eq. (6.28), we obtain (6.30) We make the following observations on this expression for the voltage gain: 1. The gain is negative, which signifies that the amplifier is inverting; that is, there is a 180 phase shift between the input and the output. This inversion is obvious in Fig.
6.33(b) and should have been anticipated from Eq. (6.26). 2. The gain is proportional to the collector bias current and to the load resistance Additional insight into the voltage gain Av can be obtained by expressing Eq. (6.30) as (6.31) where VRC is the dc voltage drop across RC, (6.32) The simple expression in Eq. (6.31) indicates that the voltage gain of the amplifier is the ratio of the dc voltage drop across RC to the thermal voltage V T ( 25 mV at room temperature).
It follows that to maximize the voltage gain we should use as large a voltage drop across RC as possible. For a given value of VCC, Eq. (6.32) indicates that to increase V RC we have to operate at a lower V CE. However, reference to Fig. 6.33(b) shows that a lower V CE means a bias point Q close to the end of the active-region segment, which might not leave sufficient room for the negative-output signal swing without the amplifier entering the saturation region. If this happens, the negative peaks of the waveform of vce will be flattened. Indeed, it is the need to allow sufficient room for output signal swing that determines the most effec-tive placement of the bias point Q on the active-region segment, YZ, of the transfer curve.
Placing Q too high on this segment not only results in reduced gain (because VRC is lower) but could possibly limit the available range of positive signal swing. At the positive end, the limitation is imposed by the BJT cutting off, in which event the positive-output peaks would be clipped off at a level equal to V CC. Finally, it is useful to note that the theoretical vbe vbe vce, vbe vce vbe Av dvCE dvBE -----------vBE VBE = ≡ Av IC VT ------⎝ ⎠ ⎛ ⎞RC – = ° IC RC.
Av ICRC VT -----------– VRC VT --------– = = VRC VCC −VCE = 400 Chapter 6 Bipolar Junction Transistors (BJTs) maximum gain Av is obtained by biasing the BJT at the edge of saturation, which of course would not leave any room for negative signal swing. The resulting gain is given by (6.33) Thus, (6.34) Although the gain can be increased by using a larger supply voltage, other considerations come into play when one is determining an appropriate value for V CC. In fact, the trend has been toward using lower and lower supply voltages, currently approaching 1 V or so. At such low supply voltages, large gain values can be obtained by replacing the resistance RC with a constant-current source, as will be seen in Chapter 7.
Av VCC −VCEsat VT -----------------------------– = Avmax VCC VT ---------Consider an amplifier circuit using a BJT having IS = 10−15 A, a collector resistance RC = 6.8 kΩ, and a power supply V CC = 10 V.
(a) Determine the value of the bias voltage VBE required to operate the transistor at VCE = 3.2 V. What is the corresponding value of IC?
(b) Find the voltage gain Av at this bias point. If an input sine-wave signal of 5-mV peak amplitude is superimposed on V BE, find the amplitude of the output sine-wave signal (assume linear operation).
(c) Find the positive increment in vBE (above V BE) that drives the transistor to the edge of saturation, where vCE = 0.3 V.
(d) Find the negative increment in vBE that drives the transistor to within 1% of cutoff (i.e., to vCE = 0.99VCC).
Solution (a) The value of VBE can be determined from which results in IC VCC VCE – RC -------------------------= 10 3.2 – 6.8 -------------------1 mA = = 1 10 3 – × 10 15 – e VBE VT ⁄ = VBE 690.8 mV = Example 6.13 6.4 Applying the BJT in Amplifier Design 401 6.4.5 Determining the VTC by Graphical Analysis Figure 6.34 shows a graphical method for determining the VTC of the amplifier of Figure 6.33(a). Although graphical analysis of transistor circuits is rarely employed in practice, it is useful for us at this stage in gaining greater insight into circuit operation, especially in answering the question of where to locate the bias point Q.
(b) (c) For vCE = 0.3 V, To increase iC from 1 mA to 1.617 mA, vBE must be increased by = 12 mV (d) For vCE = 0.99VCC = 9.9 V, To decrease iC from 1 mA to 0.0147 mA, vBE must change by Av VCC VCE – VT -------------------------– = 10 3.2 – 0.025 -------------------– 272 V/V – = = V ˆce 272 0.005 1.36 V = × = iC 10 0.3 – 6.8 -------------------1.617 mA = = ΔvBE VT 1.617 1 -------------⎝ ⎠ ⎛ ⎞ ln = iC 10 9.9 – 6.8 -------------------0.0147 mA = = ΔvBE VT 0.0147 1 ----------------⎝ ⎠ ⎛ ⎞ ln = 105.5 mV – = 6.33 For the situation described in Example 6.13, while keeping IC unchanged at 1 mA, find the value of RC that will result in a voltage gain of What is the largest negative signal swing allowed at the output (assume that vCE is not to decrease below 0.3 V)? What (approximately) is the corre-sponding input signal amplitude? (Assume linear operation.) Ans. 8 kΩ; 1.7 V; 5.3 mV 320 V/V.
– EXERCISE 402 Chapter 6 Bipolar Junction Transistors (BJTs) The graphical analysis is based on the observation that for each value of , the circuit will be operating at the point of intersection of the corresponding graph and the straight line representing Eq. (6.24), which can be rewritten in the form (6.35) The straight line representing this relationship is superimposed on the characteris-tics in Fig. 6.34. It intersects the horizontal axis at and has a slope of .
Since this straight line represents in effect the load resistance , it is called the load line.
The VTC is then determined point by point. Note that we have labeled three important points: point Y at which V, point Q at which the BJT can be biased for amplifier operation ( and ), and point Z at which the BJT leaves the active mode and enters the saturation region. If the BJT is to be used as a switch, then operating points Y and Z are applicable: At Y the transistor is off (open switch), and at Z the transistor operates as a low valued resistance and has a small voltage drop (closed switch). It should be noted, however, that because of the long delay time needed to turn off a saturated BJT, mod-ern digital integrated circuits no longer utilize the saturated mode of operation. Nonsaturated BJT digital circuits will be studied in Chapter 14.
6.4.6 Locating the Bias Point Q The bias point Q is determined by the value of and that of the load resistance Two important considerations in deciding on the location of Q are the gain and the allowable signal swing at the output. To illustrate, consider the VTC shown in Fig. 6.33(b). Here the value of is fixed, and the only variable remaining is the value of Since the slope increases as we move closer to point Z, we obtain higher gain by locating Q as close to Z as possible. However, the closer Q is to the boundary point Z, the smaller the allowable magnitude of negative signal swing. Thus, as usual in engineering design, we encounter a situation requiring a trade-off.
In deciding on a value for it is useful to refer to the plane. Figure 6.35 shows two load lines resulting in two extreme bias points: Point , is too close to , resulting in a severe constraint on the positive signal swing of Exceeding the allowable positive vBE iC vCE – iC VCC RC ---------1 RC ------vCE – = . . .
iC IC V Z Y CE VCC vCE Load line Slope 1 RC Q 0 vBE . . .
vBE . . .
vBE vBE Figure 6.34 Graphical construction for determining the VTC of the amplifier circuit of Fig. 6.33(a).
iC vCE – vCE V CC = 1 RC ⁄ – RC vBE 0.5 = vBE VBE = vCE VCE = RCEsat V BE RC.
RC V BE.
RC iC vCE – QA V CC vce.
6.5 Small-Signal Operation and Models 403 maximum results in the positive peaks of the signal being clipped off, since the BJT will turn off for the part of each cycle near the positive peak. We speak of this situation as the circuit not having sufficient “headroom.” Similarly, point is too close to the boundary of the saturation region, thus severely limiting the allowable negative signal swing of Exceeding this limit would result in the transistor entering the saturation region for part of each cycle near the negative peaks, resulting in a distorted output signal. We speak of this situation as the circuit not having sufficient “legroom.” We will have more to say on bias design in Section 6.7.
6.5 Small-Signal Operation and Models Having learned the basis for the operation of the BJT as an amplifier, we now take a closer look at the small-signal operation of the transistor. Toward that end, consider once more the conceptual amplifier circuit shown in Fig. 6.36(a). Here the base–emitter junction is forward biased by a dc voltage V BE (battery). The reverse bias of the collector–base junction is estab-lished by connecting the collector to another power supply of voltage V CC through a resistor RC. The input signal to be amplified is represented by the voltage source vbe that is superim-posed on V BE.
We consider first the dc bias conditions by setting the signal vbe to zero. The circuit reduces to that in Fig. 6.36(b), and we can write the following relationships for the dc cur-rents and voltages: (6.36) (6.37) QB vce.
iC vCE Load-line A QB QA VCE QB VCE VCC Load-line B QA . . .
vBE . . .
vBE vBE VBE Figure 6.35 Effect of bias-point location on allowable signal swing: Load line A results in bias point QA with a corresponding VCE that is too close to VCC and thus limits the positive swing of vCE. At the other extreme, load line B results in an operating point, QB, too close to the saturation region, thus limiting the neg-ative swing of vCE.
IC ISe VBE VT ⁄ = IE IC α ⁄ = 404 Chapter 6 Bipolar Junction Transistors (BJTs) (6.38) (6.39) Obviously, for active-mode operation, VC should be greater than (VB − 0.4) by an amount that allows for the required signal swing at the collector.
6.5.1 The Collector Current and the Transconductance If a signal vbe is applied as shown in Fig. 6.36(a), the total instantaneous base–emitter volt-age vBE becomes Correspondingly, the collector current becomes Use of Eq. (6.36) yields (6.40) Now, if vbe VT, we may approximate Eq. (6.40) as (6.41) Here we have expanded the exponential in Eq. (6.40) in a series and retained only the first two terms. This approximation, which is valid only for vbe less than approximately 10 mV, is referred to as the small-signal approximation. Under this approximation, the total collector current is given by Eq. (6.41) and can be rewritten (6.42) Figure 6.36 (a) Conceptual circuit to illustrate the operation of the transistor as an amplifier. (b) The cir-cuit of (a) with the signal source vbe eliminated for dc (bias) analysis.
V v vCE RC iB iE VCC vBE BE be iC (a) V IC VCE BE RC IB IE VCC (b) IB IC β ⁄ = VCE VCC ICRC – = vBE VBE vbe + = iC ISe vBE VT ⁄ ISe VBE vbe + ( ) VT ⁄ = = ISe VBE VT ⁄ e vbe VT ⁄ = iC ICe vbe VT ⁄ = iC IC 1 vbe VT ------+ ⎝ ⎠ ⎛ ⎞ iC IC IC VT -----vbe + = 6.5 Small-Signal Operation and Models 405 Thus the collector current is composed of the dc bias value IC and a signal component ic, (6.43) This equation relates the signal current in the collector to the corresponding base–emitter signal voltage. It can be rewritten as (6.44) where gm is called the transconductance, and from Eq. (6.43), it is given by (6.45) We observe that the transconductance of the BJT is directly proportional to the collector bias current IC. Thus to obtain a constant predictable value for gm, we need a constant predictable IC. Finally, we note that BJTs have relatively high transconductance (as compared to MOS-FETs, which we studied in Chapter 5); for instance, at IC = 1 mA, A graphical interpretation for gm is given in Fig. 6.37, where it is shown that gm is equal to the slope of the iC –vBE characteristic curve at iC = IC (i.e., at the bias point Q). Thus, (6.46) Figure 6.37 Linear operation of the transistor under the small-signal condition: A small signal vbe with a triangular waveform is superimposed on the dc voltage VBE. It gives rise to a collector signal current ic, also of triangular waveform, superimposed on the dc current IC. Here, ic = gmvbe, where gm is the slope of the iC–vBE curve at the bias point Q.
ic IC VT -----vbe = ic gmvbe = gm IC VT -----= gm 40 mA/V.
gm ∂iC ∂vBE -----------iC=IC = Q 406 Chapter 6 Bipolar Junction Transistors (BJTs) The small-signal approximation implies keeping the signal amplitude sufficiently small that operation is restricted to an almost-linear segment of the iC–vBE exponential curve. Increas-ing the signal amplitude will result in the collector current having components nonlinearly related to vbe. This, of course, is the same approximation that we discussed in the context of the amplifier transfer curve in Section 6.4.
The analysis above suggests that for small signals (vbe VT), the transistor behaves as a voltage-controlled current source. The input port of this controlled source is between base and emitter, and the output port is between collector and emitter. The transconductance of the controlled source is gm, and the output resistance is infinite. The latter ideal property is a result of our first-order model of transistor operation in which the collector voltage has no effect on the collector current in the active mode. As we have seen in Section 6.2, practical BJTs have finite output resistance because of the Early effect. The effect of the output resis-tance on amplifier performance will be considered later. 6.5.2 The Base Current and the Input Resistance at the Base To determine the resistance seen by vbe, we first evaluate the total base current iB using Eq. (6.42), as follows: Thus, (6.47) where IB is equal to and the signal component ib is given by (6.48) Substituting for by gm gives (6.49) The small-signal input resistance between base and emitter, looking into the base, is denoted by rπ and is defined as (6.50) 6.34 Use Eq. (6.46) to derive the expression for gm in Eq. (6.45).
6.35 Calculate the value of gm for a BJT biased at IC = 0.5 mA.
Ans. 20 mA/V EXERCISES iB iC β ----IC β ----1 β --- IC VT -----vbe + = = iB IB ib + = IC β ⁄ ib 1 β --- IC VT -----vbe = IC VT ⁄ ib gm β -----vbe = rπ vbe ib ------≡ 6.5 Small-Signal Operation and Models 407 Using Eq. (6.49) gives (6.51) Thus rπ is directly dependent on β and is inversely proportional to the bias current IC. Substi-tuting for gm in Eq. (6.51) from Eq. (6.45) and replacing IC /β by IB gives an alternative expression for rπ, (6.52) 6.5.3 The Emitter Current and the Input Resistance at the Emitter The total emitter current iE can be determined from Thus, (6.53) where IE is equal to IC /α and the signal current ie is given by (6.54) If we denote the small-signal resistance between base and emitter looking into the emitter by re, it can be defined as (6.55) Using Eq. (6.54) we find that re, called the emitter resistance, is given by (6.56) Comparison with Eq. (6.45) reveals that (6.57) rπ β gm -----= rπ VT IB -----= 6.36 A BJT amplifier is biased to operate at a constant collector current mA irrespective of the value . If the transistor manufacturer specifies to range from 50 to 200, give the expected range of , and Ans. is constant at 20 mA/V; μA to 2.5 μA; k to 10 k IC 0.5 = β β gm IB, rπ.
gm IB 10 = rπ 2.5 = Ω Ω EXERCISE iE iC α ----IC α ----ic α ---+ = = iE IE ie + = ie ic α ---IC αVT ----------vbe IE VT -----vbe = = = re vbe ie ------≡ re VT IE -----= re α gm ----- 1 gm -----= 408 Chapter 6 Bipolar Junction Transistors (BJTs) The relationship between rπ and re can be found by combining their respective definitions in Eqs. (6.50) and (6.55) as Thus, which yields (6.58) Figure 6.38 illustrates the definition of rπ and re.
6.5.4 Voltage Gain We have established above that the transistor senses the base–emitter signal vbe and causes a proportional current gmvbe to flow in the collector lead at a high (ideally infinite) impedance level. In this way the transistor is acting as a voltage-controlled current source. To obtain an output voltage signal, we may force this current to flow through a resistor, as is done in Fig.
6.36(a). Then the total collector voltage vCE will be (6.59) Figure 6.38 Illustrating the definition of rπ and re.
vbe ibrπ iere = = rπ ie ib ⁄ ( )re = rπ β 1 + ( )re = vbe vbe r vbe vbe re ib ib ie ie 6.37 A BJT having β = 100 is biased at a dc collector current of 1 mA. Find the value of gm, re, and rπ at the bias point.
Ans. 40 mA/V; 25 Ω; 2.5 kΩ EXERCISE vCE VCC iCRC – = VCC IC ic + ( )RC – = VCC ICRC – ( ) icRC – = VCE icRC – = 6.5 Small-Signal Operation and Models 409 Here the quantity VCE is the dc bias voltage at the collector, and the signal voltage is given by (6.60) Thus the voltage gain of this amplifier Av is (6.61) Here again we note that because gm is directly proportional to the collector bias current, the gain will be as stable as the collector bias current is made. Substituting for gm from Eq. (6.45) enables us to express the gain in the form (6.62) which is identical to the expression we derived in Section 6.4 (Eq. 6.31). 6.5.5 Separating the Signal and the DC Quantities The analysis above indicates that every current and voltage in the amplifier circuit of Fig. 6.36(a) is composed of two components: a dc component and a signal component. For instance, vBE = VBE + vbe, IC = IC + ic, and so on. The dc components are determined from the dc circuit given in Fig. 6.36(b) and from the relationships imposed by the transistor (Eqs. 6.36 through 6.38). On the other hand, a representation of the signal operation of the BJT can be obtained by eliminating the dc sources, as shown in Fig. 6.39. Observe that since the volt-age of an ideal dc supply does not change, the signal voltage across it will be zero. For this reason we have replaced VCC and VBE with short circuits. Had the circuit contained ideal dc vce ic – RC gm – vbeRC = = gm – RC ( )vbe = Av vce vbe ------≡ gm – RC = Av ICRC VT -----------– = 6.38 In the circuit of Fig. 6.36(a), VBE is adjusted to yield a dc collector current of 1 mA. Let VCC = 15 V, RC = 10 kΩ, and β = 100. Find the voltage gain If vbe = 0.005 sinωt volt, find vC(t) and iB(t).
Ans. 5 – 2 sinωt volts; 10 + 2 sinωt μA vce vbe.
⁄ 400 V/V; – EXERCISE vce RC vbe vbe B E C ic ie re ib vbe /r vbe gm vbe Figure 6.39 The amplifier circuit of Fig. 6.36(a) with the dc sources (VBE and VCC) eliminated (short-circuited). Thus only the signal components are present. Note that this is a rep-resentation of the signal operation of the BJT and not an actual amplifier circuit.
410 Chapter 6 Bipolar Junction Transistors (BJTs) current sources, these would have been replaced by open circuits. Note, however, that the circuit of Fig. 6.39 is useful only in so far as it shows the various signal currents and volt-ages; it is not an actual amplifier circuit, since the dc bias circuit is not shown.
Figure 6.39 also shows the expressions for the current increments (ic, ib, and ie) obtained when a small signal vbe is applied. These relationships can be represented by a circuit. Such a cir-cuit should have three terminals—C, B, and E—and should yield the same terminal currents indi-cated in Fig. 6.39. The resulting circuit is then equivalent to the transistor as far as small-signal operation is concerned, and thus it can be considered an equivalent small-signal circuit model.
6.5.6 The Hybrid-π Model An equivalent circuit model for the BJT is shown in Fig. 6.40(a). This model represents the BJT as a voltage-controlled current source and explicitly includes the input resistance looking into the base, r π. The model obviously yields ic = gmvbe and Not so obvious, however, is the fact that the model also yields the correct expression for ie. This can be shown as follows: At the emitter node we have A slightly different equivalent-circuit model can be obtained by expressing the current of the controlled source (gmvbe) in terms of the base current ib as follows: This results in the alternative equivalent-circuit model shown in Fig. 6.40(b). Here the tran-sistor is represented as a current-controlled current source, with the control current being ib.
Figure 6.40 Two slightly different versions of the hybrid-π model for the small-signal operation of the BJT. The equivalent circuit in (a) represents the BJT as a voltage-controlled current source (a transcon-ductance amplifier), and that in (b) represents the BJT as a current-controlled current source (a current amplifier).
ib = vbe rπ.
⁄ ie vbe rπ ------gmvbe + vbe rπ ------ 1 gmrπ + ( ) = = vbe rπ ------ 1 β + ( ) = vbe rπ 1 β + ------------⎝ ⎠ ⎛ ⎞ = vbe re ⁄ = gmvbe gm ibrπ ( ) = gmrπ ( )ib = βib = (a) gm = IC/VT rp = b/gm E B C + – ib ic ie vbe rp gmvbe + B C E – rp bib ic ib ie vbe 6.5 Small-Signal Operation and Models 411 The two models of Fig. 6.40 are simplified versions of what is known as the hybrid-π model. This is the most widely used model for the BJT.
It is important to note that the small-signal equivalent circuits of Fig. 6.40 model the operation of the BJT at a given bias point. This should be obvious from the fact that the model parameters gm and rπ depend on the value of the dc bias current IC, as indicated in Fig. 6.40. It is interesting and useful to note that the models of Fig. 6.40 (a) and (b) are the small-signal versions of the models of Fig. 6.5(c) and (d), respectively. Specifically, observe that rπ is the incremental resistance of DB.
6.5.7 The T Model Although the hybrid-π model (in one of its two variants shown in Fig. 6.40) can be used to carry out small-signal analysis of any transistor circuit, there are situations in which an alternative model, shown in Fig. 6.41, is much more convenient. This model, called the T model, is shown in two versions in Fig. 6.41. The model of Fig. 6.41(a) represents the BJT as a voltage-controlled current source with the control voltage being vbe. Here, however, the resistance between base and emitter, looking into the emitter, is explicitly shown. From Fig. 6.41(a) we see clearly that the model yields the correct expressions for ic and ie. For ib we note that at the base node we have Figure 6.41 Two slightly different versions of what is known as the T model of the BJT. The circuit in (a) is a voltage-controlled current source representation and that in (b) is a current-controlled current source representation. These models explicitly show the emitter resistance re rather than the base resistance rπ featured in the hybrid-π model.
6.39 For the model in Fig. 6.40(b) show that ic = gmvbe and ie = vbe re.
⁄ EXERCISE (a) C B E ic ib vbe ie r e ie (b) 412 Chapter 6 Bipolar Junction Transistors (BJTs) as should be the case.
If in the model of Fig. 6.41(a) the current of the controlled source is expressed in terms of the emitter current as we obtain the alternative T model shown in Fig. 6.41(b). Here the BJT is represented as a current-controlled current source but with the control signal being ie.
It is interesting and useful to note that the models of Fig. 6.41(a) and (b) are the small-signal versions of the models in Fig. 6.5(a) and (b), respectively. Specifically observe that re is the incremental resistance of DE.
6.5.8 Small-Signal Models of the pnp Transistor Although the small-signal models in Figs. 6.40 and 6.41 were developed for the case of the npn transistor, they apply equally well to the pnp transistor with no change in polarities.
6.5.9 Application of the Small-Signal Equivalent Circuits The availability of the small-signal BJT circuit models makes the analysis of transistor amplifier circuits a systematic process. The process consists of the following steps: 1. Eliminate the signal source and determine the dc operating point of the BJT and in par-ticular the dc collector current IC.
2. Calculate the values of the small-signal model parameters: and 3. Eliminate the dc sources by replacing each dc voltage source with a short circuit and each dc current source with an open circuit.
4. Replace the BJT with one of its small-signal equivalent circuit models. Although any one of the models can be used, one might be more convenient than the others for the par-ticular circuit being analyzed. This point will be made clearer later in this chapter.
5. Analyze the resulting circuit to determine the required quantities (e.g., voltage gain, input resistance). The process will be illustrated by the following examples.
ib vbe re ------gmvbe – vbe re ------ 1 gmre – ( ) = = vbe re ------ 1 α – ( ) vbe re ------ 1 β β 1 + ------------– ⎝ ⎠ ⎛ ⎞ = = vbe β 1 + ( )re ----------------------= vbe rπ ------= gmvbe gm iere ( ) = gmre ( )ie = αie = gm = IC VT, ⁄ rπ = β gm, ⁄ re = VT IE ⁄ = α gm.
⁄ 6.5 Small-Signal Operation and Models 413 We wish to analyze the transistor amplifier shown in Fig. 6.42(a) to determine its voltage gain .
Assume β = 100.
Solution We shall follow the five-step process outlined above: 1. The first step in the analysis consists of determining the quiescent operating point. For this pur-pose we assume that vi = 0 and thus obtain the dc circuit shown in Fig. 6.42(b). The dc base cur-rent will be Figure 6.42 Example 6.14: (a) amplifier circuit; (b) circuit for dc analysis; (c) amplifier circuit with dc sources replaced by short circuits; (d) amplifier circuit with transistor replaced by its hybrid-π, small-signal models.
vo vi ⁄ 3 V V C V BB V CC 10 V v i vo R BB 100 k R C 3 k (a ) 10 V 100 k 3 k 2.3 mA 3 V 0.023 mA 0.7 V 2.323 mA 3.1 V (b) r vi (d) gm 100 k 3 k RBB B E C vbe vo vbe RC vo (c) Re vi RBB Example 6.14 414 Chapter 6 Bipolar Junction Transistors (BJTs) Example 6.14 continued The dc collector current will be The dc voltage at the collector will be = +10 − 2.3 × 3 = +3.1 V Since V B at +0.7 V is less than V C, it follows that in the quiescent condition the transistor will be operating in the active mode. The dc analysis is illustrated in Fig. 6.42(b).
2. Having determined the operating point, we can now proceed to determine the small-signal model parameters: 3. Replacing V BB and V CC with short circuits results in the circuit in Fig. 6.42(c).
4. To carry out the small-signal analysis, it is equally convenient to employ either of the two hybrid-π, equivalent-circuit models of Fig. 6.40 to replace the transistor in the circuit of Fig. 6.42(c).
Using the first results in the amplifier equivalent circuit given in Fig. 6.42(d). 5. Analysis of the equivalent circuit in Fig. 6.42(d) proceeds as follows: (6.63) The output voltage vo is given by Thus the voltage gain will be (6.64) IB VBB VBE – RBB ------------------------= 3 0.7 – 100 ----------------0.023 mA = IC βIB = 100 0.023 × 2.3 mA = = VC VCC ICRC – = re VT IE ------25 mV 2.3 0.99 ⁄ ( ) mA --------------------------------------10.8 Ω = = = gm IC VT ------2.3 mA 25 mV ------------------92 mA/V = = = rπ β gm ------100 92 ---------1.09 kΩ = = = vbe vi rπ rπ RBB + --------------------= vi 1.09 101.09 ----------------= 0.011vi = vo g – mvbeRC = 92 0.011vi 3 × × – = 3.04 – vi = Av vo vi ----3.04 – V/V = = 6.5 Small-Signal Operation and Models 415 To gain more insight into the operation of transistor amplifiers, we wish to consider the waveforms at var-ious points in the circuit analyzed in the previous example. For this purpose assume that vi has a triangular waveform. First determine the maximum amplitude that vi is allowed to have. Then, with the amplitude of vi set to this value, give the waveforms of the total quantities iB(t), vBE(t), iC(t), and vC(t).
Solution One constraint on signal amplitude is the small-signal approximation, which stipulates that vbe should not exceed about 10 mV. If we take the triangular waveform vbe to be 20 mV peak-to-peak and work back-ward, Eq. (6.63) can be used to determine the maximum possible peak of vi, To check whether the transistor remains in the active mode with vi having a peak value we have to evaluate the collector voltage. The voltage at the collector will consist of a trian-gular wave vo superimposed on the dc value VC = 3.1 V. The peak voltage of the triangular waveform will be It follows that when the output swings negative, the collector voltage reaches a minimum of 3.1 – 2.77 = 0.33 V, which is lower than the base voltage by less than 0.4 V. Thus the transistor will remain in the active mode with vi having a peak value of 0.91 V. Nevertheless, to be on the safe side, we will use a somewhat lower value for of approximately 0.8 V, as shown in Fig. 6.43(a), and complete the analysis of this problem utilizing the equivalent circuit in Fig. 6.42(d). The signal current in the base will be trian-gular, with a peak value of This triangular-wave current will be superimposed on the quiescent base current IB, as shown in Fig.
6.43(b). The base–emitter voltage will consist of a triangular-wave component superimposed on the dc VBE that is approximately 0.7 V. The peak value of the triangular waveform will be The total vBE is sketched in Fig. 6.43(c).
The signal current in the collector will be triangular in waveform, with a peak value given by This current will be superimposed on the quiescent collector current IC (=2.3 mA), as shown in Fig.
6.43(d).
The signal voltage at the collector can be obtained by multiplying vi by the voltage gain; that is, Figure 6.43(e) shows a sketch of the total collector voltage vC versus time. Note the phase reversal between the input signal vi and the output signal vo.
Finally, we observe that each of the total quantities is the sum of a dc quantity (found from the dc cir-cuit in Fig. 6.42b), and a signal quantity (found from the circuit in Fig. 6.42d).
v ˆ o vbe 0.011 -------------10 0.011 -------------0.91 V = = = v ˆ i 0.91 V, = v ˆ o v ˆ i gain × 0.91 3.04 × 2.77 V = = = v ˆ i i ˆ b i ˆb v ˆ i RBB rπ + --------------------0.8 100 1.09 + -------------------------0.008 mA = = = v ˆ be v ˆ i rπ rπ RBB + --------------------0.8 1.09 100 1.09 + -------------------------8.6 mV = = = i ˆc i ˆc βi ˆb 100 0.008 × 0.8 mA = = = v ˆ o 3.04 0.8 × 2.43 V = = Example 6.15 416 Chapter 6 Bipolar Junction Transistors (BJTs) t vi vi (a) 0.8 V 0.8 V ˆ 0 iB (mA) (b) ib 0.03 0.02 0.01 0.023 mA iB 0.008 mA ˆ 0 ib IB t t (c) vbe 0.7 V vBE VBE 0 vbe 8.6 mV ˆ vBE iC (mA) (d) iC IC ic 0.8 mA ic IC 2.3 mA ˆ 3 2 1 0 t t vC (V) (e) 0 vC 2.43 V VC ˆ 4 2 vo vo vo 3.1 V 0.67 V 6 Figure 6.43 Signal waveforms in the circuit of Fig. 6.42.
Example 6.15 continued 6.5 Small-Signal Operation and Models 417 We need to analyze the circuit of Fig. 6.44(a) to determine the voltage gain and the signal waveforms at various points. The capacitor CC1 is a coupling capacitor whose purpose is to couple the signal vi to the emitter while blocking dc. In this way the dc bias established by V + and V – together with RE and RC will not be disturbed when the signal vi is connected. For the purpose of this example, CC1 will be assumed to be very large so as to act as a perfect short circuit at signal frequencies of interest. Simi-larly, another very large capacitor CC2 is used to couple the output signal vo to other parts of the system. Figure 6.44 (a) circuit; (b) dc analysis; (c) circuit with the dc sources eliminated; (d) small-signal analysis using the T model for the BJT.
vi (c) RE R vo C (d) vi vo ieRC ie E re B ie C ie vo vi re RC RE vi re RC CC1 CC2 V 10 V RE 10 k RC 5 k V 10 V (a) vi vo 10 V 10 k 5.4 V 5 k 0.93 mA 0.7 V 0.92 mA (b) 10 V Example 6.16 418 Chapter 6 Bipolar Junction Transistors (BJTs) Example 6.16 continued Solution Here again we shall follow the five-step process outlined at the beginning of Section 6.5.9: 1. Figure 6.44(b) shows the circuit with the signal source and the coupling capacitors eliminated.
The dc operating point can be determined as follows: Assuming β = 100, then α = 0.99, and Thus the transistor is in the active mode.
2. We now determine the small-signal parameters as follows: mA/V 3. To prepare the circuit for small-signal analysis, we replace the dc sources with short circuits. The resulting circuit is shown in Fig. 6.44(c). Observe that we have also eliminated the two coupling capacitors, since they are assumed to be acting as perfect short circuits.
4. We are now ready to replace the BJT with one of the four equivalent circuit models of Figs. 6.40 and 6.41. Although any of the four will work, the T models of Fig. 6.41 will be more convenient because the base is grounded. Selecting the version in Fig. 6.41(b) results in the amplifier equiv-alent circuit shown in Fig. 6.44(d).
5. Analysis of the circuit in Fig. 6.44(d) to determine the output voltage vo and hence the voltage gain is straightforward and is given in the figure. The result is Note that the voltage gain is positive, indicating that the output is in phase with the input signal.
This property is due to the fact that the input signal is applied to the emitter rather than to the base, as was done in Example 6.14. We should emphasize that the positive gain has nothing to do with the fact that the transistor used in this example is of the pnp type.
Returning to the question of allowable signal magnitude, we observe from Fig. 6.44(d) that veb = vi.
Thus, if small-signal operation is desired (for linearity), then the peak of vi should be limited to approxi-mately 10 mV. With set to this value, as shown for a sine-wave input in Fig. 6.45, the peak amplitude at the collector, will be IE +10 VE – RE ---------------------- +10 0.7 – 10 -----------------------0.93 mA = = IC 0.99IE 0.92 mA = = VC −10 ICRC + = −10 0.92 5 × + = 5.4 – V = gm IC VT ------= 0.92 0.025 -------------36.8 = = re VT IE ------= 0.025 0.92 -------------27.2 Ω = = β 100 = α 0.99 = rπ β gm ------100 36.8 ----------2.72 kΩ = = = vo vi ⁄ Av vo vi ----183.3 V/V = = V ˆi V ˆo, V ˆo 183.3 0.01 × 1.833 V = = 6.5 Small-Signal Operation and Models 419 6.5.10 Performing Small-Signal Analysis Directly on the Circuit Diagram In most cases one should explicitly replace each BJT with its small-signal model and ana-lyze the resulting circuit, as we have done in the examples above. This systematic procedure is particularly recommended for beginning students. Experienced circuit designers, how-ever, often perform a first-order analysis directly on the circuit. Figure 6.46 illustrates this process for the two circuits we analyzed in Examples 6.14 and 6.16. The reader is urged to follow this direct analysis procedure (the steps are numbered). Observe that the equivalent-circuit model is implicitly utilized; we are only saving the step of drawing the circuit with the BJT replaced by its model. Direct analysis, however, has an additional very important benefit: It Figure 6.45 Input and output waveforms for the circuit of Fig. 6.44. Observe that this amplifier is noninverting, a property of the grounded base configuration.
1.83 6.40 To increase the voltage gain of the amplifier analyzed in Example 6.16, the collector resistance RC is increased to 7.5 kΩ. Find the new values of V C, Av, and the peak amplitude of the output sine wave corresponding to an input sine wave vi of 10-mV peak.
Ans. –3.1 V; 275 V/V; 2.75 V EXERCISE 420 Chapter 6 Bipolar Junction Transistors (BJTs) provides insight regarding the signal transmission through the circuit. Such insight can prove invaluable in design, particularly at the stage of selecting a circuit configuration appropriate for a given application.
6.5.11 Augmenting the Small-Signal Models to Account for the Early Effect The Early effect, discussed in Section 6.2, causes the collector current to depend not only on vBE but also on vCE. The dependence on vCE can be modeled by assigning a finite output resis-tance to the controlled current source in the hybrid-π model, as shown in Fig. 6.47. The output resistance ro was defined in Eq. (6.19); its value is given by where VA is the Early voltage and is the dc bias current without taking the Early effect into account. We will nor-mally drop the prime and just use . Note that in the models of Fig. 6.47 we have renamed vbe as vπ, in order to conform with the literature.
vi ib ic b ib vo RC ic b RC ib ic RBB RC r 1 3 4 b RC RBB r Av 5 RBB r b RC ib 2 RBB r vi vo vi (a) vi vi ic ie vo ic RC ie RE re RC 1 3 4 5 vo vi Av re RC re RC ie 2 re vi vi vi re (b) Figure 6.46 Performing signal analysis directly on the circuit diagram with the BJT small-signal model implicitly employed: (a) Circuit for Example 6.14; (b) Circuit for Example 6.16.
ro V = A I′ C, ⁄ I′ C ro V = A IC ⁄ 6.5 Small-Signal Operation and Models 421 The question arises as to the effect of ro on the operation of the transistor as an amplifier.
In amplifier circuits in which the emitter is grounded (as in the circuit of Fig. 6.42), ro simply appears in parallel with RC. Thus, if we include ro in the equivalent circuit of Fig. 6.42(d), for example, the output voltage vo becomes Thus the gain will be somewhat reduced. Obviously if ro RC, the reduction in gain will be negligible, and one can ignore the effect of ro. In general, in such a configuration ro can be neglected if it is greater than 10RC.
When the emitter of the transistor is not grounded, including ro in the model can compli-cate the analysis. We will make comments regarding ro and its inclusion or exclusion on fre-quent occasions throughout the book. We should also note that in integrated-circuit BJT amplifiers, ro plays a dominant role and cannot be neglected, as will be seen in Chapter 7. Of course, if one is performing an accurate analysis of an almost-final design using computer-aided analysis, then ro can be easily included. Finally, it should be noted that either of the T models in Fig. 6.41 can be augmented to account for the Early effect by including ro between collector and emitter.
Figure 6.47 The hybrid-π small-signal model, in its two versions, with the resistance ro included. (a) gmv B C E v r ro B C E (b) r ro ib ib vo gmvbe RC || ro ( ) – = 6.41 The transistor in Fig. E6.41 is biased with a constant current source I = 1 mA and has β = 100 and VA = 100 V. (a) Find the dc voltages at the base, emitter, and collector. (b) Find gm, rπ , and ro. (c) If terminal Z is connected to ground, X to a signal source vsig with a source resistance Rsig = 2 kΩ, and Y to an 8-kΩ load resistance, use the hybrid-π model of Fig. 6.47(a), to draw the small-signal equivalent circuit of the amplifier. (Note that the current source I should be replaced with an open circuit.) Calculate the overall voltage gain vy/vsig. If ro is neglected, what is the error in estimating the gain magnitude? (Note: An infinite capacitance is used to indicate that the capacitance is suffi-ciently large that it acts as a short circuit at all signal frequencies of interest. However, the capacitor still blocks dc.) EXERCISE 422 Chapter 6 Bipolar Junction Transistors (BJTs) 6.5.12 Summary The analysis and design of BJT amplifier circuits is greatly facilitated if the relationships between the various small-signal model parameters are at your fingertips. For easy refer-ence, these are summarized in Table 6.4. Over time, however, we expect the reader to be able to recall these from memory. Finally, note that the material in Table 6.4 applies equally well to both the npn and the pnp transistors with no change in polarities.
6.6 Basic BJT Amplifier Configurations It is useful at this point to take stock of where we are and where we are going in our study of BJT amplifiers. In Section 6.4 we examined the essence of the use of the BJT as an amplifier. There we found that almost-linear amplification can be obtained by biasing the BJT at an appropriate point in its active region of operation and by keeping the signal (or ) small. Then in Section 6.5 we took a closer look at the small-signal operation of the BJT and developed circuit models to represent the transistor, thus facilitating the determination of amplifier parameters such as voltage gain and input and output resistances. We are now ready to consider the various possible configurations of BJT amplifiers, and we will do that in the present section. To focus our attention on the salient features of the various configurations, we shall present them in their most simple, or “stripped-down,” version. Thus, we will not show the dc biasing arrangements, leaving the study of bias design to the next section. Finally, in Section 6.8 we will bring everything together and present practical circuits for discrete-circuit BJT amplifiers, namely, those amplifier circuits that can be constructed using discrete components. The study of integrated-circuit amplifiers begins in Chapter 7.
Ans. (a) −0.1 V, −0.8 V, +2 V; (b) 40 mA/V, 2.5 kΩ, 100 kΩ; (c) −77 V/V, +3.9% Figure E6.41 vbe vπ 6.6 Basic BJT Amplifier Configurations 423 Table 6.4 Small-Signal Models of the BJT Hybrid-π Model (gmvπ) Version (gmvπ) Version (α i) Version Model Parameters in Terms of DC Bias Currents In Terms of gm In Terms of re Relationships between α and β βib ( ) Version r ro gmv E B C v r ro ib E B C ib re ro E C B gmv v re ro E C B i i gm IC VT ------= re VT IE ------α VT IC ------= = rπ VT IB ------β VT IC ------= = ro VA IC ---------= re α gm ------= rπ β gm ------= gm α re ----= rπ β 1 + ( )re = gm 1 rπ ----+ 1 re ----= β α 1 α – ------------= α β β 1 + ------------= β 1 + 1 1 α – ------------= 424 Chapter 6 Bipolar Junction Transistors (BJTs) 6.6.1 The Three Basic Configurations There are three basic configurations for connecting the BJT as an amplifier. Each of these con-figurations is obtained by connecting one of the three BJT terminals to ground, thus creating a two-port network with the grounded terminal being common to the input and output ports. Fig-ure 6.48 shows the resulting three configurations with the biasing arrangements omitted.
In the circuit of Fig. 6.48(a) the emitter terminal is connected to ground, the input voltage signal is applied between the base and ground, and the output voltage signal is taken between the collector and ground, across the resistance . This configuration, therefore, is called the grounded-emitter or common-emitter (CE) amplifier. It is by far the most popu-lar BJT amplifier configuration and is the one we have utilized in Sections 6.4 and 6.5 to study BJT amplifier operation.
vi vo RC vi RC (a) Common-Emitter (CE) vo vi RC (b) Common-Base (CB) vo vi RL (c) Common-Collector (CC) or Emitter Follower vo Figure 6.48 The three basic configurations of BJT amplifier. The biasing arrangements are not shown.
6.6 Basic BJT Amplifier Configurations 425 The common-base (CB) or grounded-base amplifier is shown in Fig. 6.48(b). It is obtained by connecting the base to ground, applying the input between the emitter and ground, and taking the output across the resistance connected between the collector and ground. We have encountered a CB amplifier in Example 6.14.
Finally, Fig. 6.48(c) shows the common-collector (CC) or grounded-collector amplifier.
It is obtained by connecting the collector terminal to ground, applying the input voltage sig-nal between base and ground, and taking the output voltage signal between the emitter and ground, across a load resistance . For reasons that will become apparent shortly, this configuration is more commonly called the emitter follower. Our study of the three basic BJT amplifier configurations will reveal that each has dis-tinctly different attributes and hence areas of application.14 6.6.2 Characterizing Amplifiers15 Before we begin our study of the different BJT amplifier configurations, we consider how to characterize the performance of an amplifier as a circuit building block. An introduction to this topic was presented in Section 1.5.
Figure 6.49(a) shows an amplifier fed with a signal source having an open-circuit voltage and an internal resistance These can be the parameters of an actual signal source or, in a cascade amplifier, the Thévenin equivalent of the output circuit of another stage pre-ceding the one under study. The amplifier is shown with a load resistance connected to the output terminal. Here, can be an actual load resistance or the input resistance of a succeeding amplifier stage in a cascade amplifier.
Figure 6.49(b) shows the amplifier circuit with the amplifier block replaced by its equivalent-circuit model. The input resistance represents the loading effect of the amplifier input on the signal source. It is found from and together with the resistance forms a voltage divider that reduces to the value that appears at the input of the amplifier proper, (6.65) It is important to note that in general may depend on the load resistance One of the three configurations we are studying in this section, the emitter follower, exhibits such dependence.
The second parameter for characterizing amplifier performance is the open-circuit volt-age gain defined as The third and final parameter is the output resistance Observe from Fig. 6.49(b) that is the resistance seen looking back into the amplifier output terminal with set to zero.
Thus can be determined, at least conceptually, as indicated in Fig. 6.49(c) with 14The CE, CB, and CC configurations are the BJT counterparts of the MOSFET CS, CG, and CD con-figurations, respectively.
15This section can be skipped if the reader has already studied Section 5.6.2; it presents substantially the same material.
vi vo RC vi vo RL vsig Rsig.
RL RL Rin Rin vi ii ----≡ Rsig vsig vi vi Rin Rin Rsig + ----------------------vsig = Rin RL.
Avo, Avo vo vi ----RL ∞ = ≡ Ro.
Ro vi Ro Ro vx ix ----= 426 Chapter 6 Bipolar Junction Transistors (BJTs) Because is determined with its value does not depend on The controlled source and the output resistance represent the Thévenin equiva-lent of the amplifier output circuit, and the output voltage can be found from (6.66) Thus the voltage gain of the amplifier proper, can be found as (6.67) and the overall voltage gain , can be determined by combining Eqs. (6.65) and (6.66), (6.68) vi 0 vx ix Ro Rsig vi vsig Rin Ro RL Avovi io vo vi vsig vo Rsig RL io ii (a) (b) (c) Figure 6.49 (a) An amplifier fed with a signal source (vsig, Rsig) and providing its output across a load resistance RL.(b) The circuit in (a) with the amplifier represented by its equivalent circuit model. (c) Deter-mining the output resistance Ro of the amplifier.
Ro vi 01 = Rsig.
Avovi Ro vo vo RL RL Ro + ------------------ Avovi = Av, Av vo vi ----Avo RL RL Ro + ------------------= ≡ Gv Gv vo vsig -------≡ Gv Rin Rin Rsig + ---------------------- Av = 6.6 Basic BJT Amplifier Configurations 427 6.6.3 The Common-Emitter (CE) Amplifier Of the three basic BJT amplifier configurations, the common emitter is the most widely used.
Typically, in an amplifier formed by cascading a number of stages, the bulk of the voltage gain is obtained by using one or more common-emitter stages in the cascade.
Figure 6.50(a) shows a common-emitter amplifier (with the biasing arrangement omitted) fed with a signal source having a source resistance We wish to analyze the circuit to determine and For this purpose we shall assume that is part of the amplifier; thus if a load resistance is connected to the amplifier output, it appears in par-allel with Characteristic Parameters of the CE Amplifier Replacing the BJT with its hybrid-model, we obtain the CE amplifier equivalent circuit shown in Fig. 6.50(b). We shall use this equiv-alent circuit to determine the characteristic parameters of the amplifier , , and as follows.
The input resistance is found by inspection to be (6.69) Observe that does not depend on the output side of the amplifier; hence, this amplifier is said to be unilateral.
The output voltage can be found by multiplying the current by the total resis-tance between the output node and ground, vsig Rsig.
Rin, Avo, Ro, Gv.
RC RL RC.
vi Rin Ro vo RC (a) vsig Rsig v vi r Rin r vsig Rsig vo Ro RC||ro gmvp RC ro (b) Figure 6.50 (a) Common-emitter amplifier fed with a signal vsig from a generator with a resistance Rsig.
(b) The common-emitter amplifier circuit with the BJT relaced with its hybrid-π model.
π Rin Avo Ro Rin Rin rπ = Rin vo gmvπ ( ) vo gmvπ ( ) RC ro || ( ) – = 428 Chapter 6 Bipolar Junction Transistors (BJTs) Since , the open-circuit voltage gain can be obtained as (6.70) Observe that the transistor output resistance reduces the magnitude of the voltage gain. In discrete-circuit amplifiers, which are of interest to us in this chapter, is usually much lower than and the effect of on reducing is slight (less than 10% or so). Thus in many cases we can neglect and express simply as (6.71) The reader is cautioned, however, that neglecting is allowed only in discrete-circuit design. As will be seen in Chapter 7, plays a central role in IC amplifiers. The output resistance is the resistance seen looking back into the output terminal with set to zero. From Fig. 6.50(b) we see that with set to zero, will be zero and will be zero, resulting in (6.72) Here has the beneficial effect of reducing the value of In discrete circuits, however, this effect is slight and we can make the approximation (6.73) This concludes the analysis of the amplifier proper. Now, we can make the following observa-tions: 1. The input resistance is moderate to low in value (typically, in the kilohm range). Obviously is directly dependent on and is inversely proportional to the collector bias current . To obtain a higher input resistance, the bias current can be lowered, but this also lowers the gain. This is a significant design trade-off. If a much higher input resistance is desired, then a modification of the CE configuration (to be discussed shortly) or an emitter-follower stage can be employed.
2. The output resistance is moderate to high in value (typically, in the kilohm range). Reducing to lower is usually not a viable proposition because the volt-age gain is also reduced. Alternatively, if a very low output resistance (in the ohms to tens of ohms range) is needed, an emitter-follower stage is called for, as will be dis-cussed in Section 6.6.6.
3. The open-circuit voltage gain can be high, making the CE configuration the work-horse in BJT amplifier design. Unfortunately, however, the bandwidth of the CE ampli-fier is severely limited. We shall study amplifier frequency response in Chapter 9.
Overall Voltage Gain To determine the overall voltage gain we first determine the fraction of that appears at the amplifier input proper, that is, ; (6.74) Depending on the relative values of and significant loss of signal strength can occur at the input, which is obviously undesirable and can be avoided by raising the input vπ vi = Avo vo vi ⁄ ≡ Avo gm RC ro || ( ) – = ro RC ro ro Avo ro Avo Avo gmRC – ( ) ro ro Ro vi vi vπ gmvπ Ro RC ro || = ro Ro.
Ro RC Rin rπ β gm ⁄ = = Rin β IC Ro RC RC Ro Avo Gv vsig vi vi vsig rπ rπ Rsig + -------------------= rπ Rsig, 6.6 Basic BJT Amplifier Configurations 429 resistance, as discussed above. At this point, we should remind the reader that to maintain a reasonably linear operation, should not exceed about 5 mV to 10 mV, which poses a con-straint on the value of If a load resistance is connected to the output terminal of the amplifier, this resistance will appear in parallel with It follows that the voltage gain can be obtained by sim-ply replacing in the expression of in Eq. (6.70) by , (6.75) We can now use this expression for together with from Eq. (6.74) to obtain the overall voltage gain as (6.76) Alternative Gain Expressions There are alternative forms for and that can yield considerable insight besides being intuitive and easy to remember. The expression for can be obtained by replacing in Eq. (6.75) with ; (6.77) Observing that is the total resistance in the collector and is the total resis-tance in the emitter, this expression simply states that the voltage gain from base to collector is given by (6.78) The reason for the factor is that the collector current is times the emitter current. Of course and can usually be neglected, and the expression in Eq. (6.78) is simply stated as a resistance ratio. This expression is a general one and applies to any BJT amplifier cir-cuit for finding the voltage gain from base to collector.
A corresponding expression for can be obtained by replacing in the numera-tor of Eq. (6.76) with (6.79) which can be expressed in words as (6.80) vi vsig.
RL RC.
Av RC Avo RC RL || Av gm RC RL ro || || ( ) – = Av vi vsig ⁄ ( ) Gv Gv vo vsig -------rπ rπ Rsig + ------------------- gm RC RL ro || || ( ) – = ≡ 6.41 Use in Eq. (6.70) together with in Eq. (6.72) to obtain Show that the result is identical to that in Eq. (6.75).
Avo Ro Av.
EXERCISE Av Gv Av gm α re ⁄ Av α RC RL ro || || ( ) re ---------------------------------– = RC RL ro || || ( ) re Av α Total resistance in collector Total resistance in emitter ------------------------------------------------------------------– = α α α 1 Gv gmrπ ( ) β, Gv β RC RL ro || || ( ) Rsig rπ + ---------------------------------– = Gv β Total resistance in collector Total resistance in base ------------------------------------------------------------------– = 430 Chapter 6 Bipolar Junction Transistors (BJTs) Observe that here the multiplicative factor is which is the ratio of to this makes sense because we are using the ratio of resistances in the collector and the base. The reader is urged to reflect on these expressions while referring to Fig. 6.50.
Performing the Analysis Directly on the Circuit As mentioned in Section 6.5, with practice one can dispense with the explicit use of the BJT equivalent circuit and perform the analysis directly on the circuit schematic. Because in this way one remains closer to the actual circuit, this direct analysis can yield greater insight into circuit operation. Although at this stage in learning electronic circuits it is perhaps a little early to follow this direct analysis route, we show in Fig. 6.51 the CE amplifier circuit prepared for direct analysis. Observe that we have “pulled out” the resistance from the transistor, thus making the transistor collector conduct while still accounting for the effect of .
β, ic ib; ro gmvπ ro v vi vo ib Rin r Ro RC ||ro vo gmv (RC ||ro) bib gmv vsig Rsig RC ro Figure 6.51 Performing the analysis directly on the circuit with the BJT model used implicitly.
A CE amplifier utilizes a BJT with and V, is biased at mA and has a collector resistance k Find and If the amplifier is fed with a signal source having a resistance of 5 k and a load resistance k is connected to the output terminal, find the resulting and If is to be limited to 5 mV, what are the corresponding and with the load connected?
Solution At mA, mA/V k k β 100 = VA 100 = IC 1 = RC 5 = Ω.
Rin, Ro, Avo.
Ω, RL 5 = Ω Av Gv.
v ˆ π v ˆ sig v ˆ o IC 1 = gm IC VT ------1 mA 0.025 V -------------------40 = = = rπ β gm ------100 40 mA/V ----------------------2.5 = = = Ω ro VA IC ------100 V 1 mA ---------------100 = = = Ω Example 6.17 6.6 Basic BJT Amplifier Configurations 431 The amplifier characteristic parameters can now be found as k With a load resistance connected at the output, we can find by either of the following two approaches: V/V or V/V The overall voltage gain can now be determined as V/V If the maximum amplitude of is to be 5 mV, the corresponding value of will be mV and the amplitude of the signal at the output will be V Rin rπ = 2.5 = Ω Avo gm RC ro || ( ) – = 40 mA/V – = 5 kΩ 100 kΩ || ( ) 190.5 V/V – = Ro RC ro || = 5 100 4.76 kΩ = || = RL 5 kΩ = Av Av Avo RL RL Ro + ------------------= 190.5 5 5 4.76 + -------------------× 97.6 – = – = Av gm RC RL ro || || ( ) – = 40 5 5 100 || || ( ) 97.6 – = – = Gv Gv Rin Rin Rsig + ---------------------- Av = 2.5 2.5 5 + ----------------97.6 32.5 – = – × = vπ v ˆ sig v ˆ sig Rin Rsig + Rin ----------------------⎝ ⎠ ⎛ ⎞v ˆ π 2.5 5 + 2.5 ----------------5 15 = × = = v ˆ o Gvv ˆ sig 32.5 0.015 0.49 = × = = 6.42. The designer of the amplifier in Example 6.17 decides to lower the bias current to half its original value in order to raise the input resistance and hence increase the fraction of that appears at the input of the amplifier proper. In an attempt to maintain the voltage gain, the designer decides to double the value of For the new design, determine and If the peak amplitude of is to be limited to 5 mV, what are the corresponding values of and (with the load connected)?
Ans. 5 k V/V; 9.5 k V/V; V/V; 10 mV; 0.33 V vsig RC.
Rin, Avo, Ro, Av, Gv.
vπ v ˆ sig v ˆ o Ω; 190.5 – Ω; 65.6 – 32.8 – EXERCISE 432 Chapter 6 Bipolar Junction Transistors (BJTs) 6.6.4 The Common-Emitter Amplifier with an Emitter Resistance Including a resistance in the emitter as shown in Fig. 6.52(a) can lead to significant changes in the amplifier characteristics. Thus, such a resistor can be an effective design tool for tai-loring the amplifier characteristics to fit the design requirements.
Analysis of the circuit in Fig. 6.52(a) can be performed by replacing the BJT with one of its small-signal models. Although any one of the models of Figs. 6.40 and 6.41 can be used, the most convenient for this application is one of the two T models. This is because the resistance in the emitter will appear in series with the emitter resistance of the T model and can thus be added to it, simplifying the analysis considerably. In fact, whenever there is a resistance in the emitter lead, the T model should prove more convenient to use than the hybrid- model.
Replacing the BJT with the T model of Fig. 6.41(b) results in the amplifier small-signal, equivalent-circuit model shown in Fig. 6.52(b). Note that we have not included the BJT out-put resistance ; because this would complicate the analysis considerably. Since for the discrete amplifier at hand it turns out that the effect of on circuit performance is small, we shall not include it in the analysis here. This is not the case, however, for the IC version of this circuit, and we shall indeed take into account in the analysis in Chapter 7.
vi vo Rin Ro vsig Rsig Re RC vi vo Rin Ro (b) ic ib ie vsig Rsig B E C RC re Re ie Figure 6.52 The CE amplifier with an emitter resistance Re; (a) Circuit without bias details; (b) Equivalent circuit with the BJT replaed with its T model.
Re re π ro ro ro 6.6 Basic BJT Amplifier Configurations 433 To determine the amplifier input resistance we note from Fig. 6.52(b) that where (6.81) and (6.82) Thus, (6.83) This is a very important result. It states that the input resistance looking into the base is times the total resistance in the emitter, and is known as the resistance-reflection rule. The factor arises because the base current is times the emitter cur-rent. The expression for in Eq. (6.83) shows clearly that including a resistance in the emitter can substantially increase . Indeed, the value of is increased by the ratio (6.84) Thus the circuit designer can use the value of to control the value of To determine the voltage gain we see from Fig. 6.52(b) that Substituting for from Eq. (6.82) gives (6.85) which is a simple application of the general expression in Eq. (6.78). Here, of course, the total resistance in the emitter is The open-circuit voltage gain in Eq. (6.85) can be expressed alternatively as (6.86) Thus, including reduces the voltage gain by the factor , which is the same fac-tor by which is increased. This points out an interesting trade-off between gain and input resistance, a trade-off that the designer can exercise through the choice of an appropriate value for The output resistance can be found from the circuit in Fig. 6.52(b) by inspection: Rin, Rin vi ib ----≡ ib 1 α – ( )ie ie β 1 + ------------= = ie vi re Re + ----------------= Rin β 1 + ( ) re Re + ( ) = β 1 + ( ) β 1 + ( ) 1 β 1 + ( ) ⁄ Rin Re Rin Rin Rin with Re included ( ) Rin without Re ( ) -----------------------------------------------------β 1 + ( ) re Re + ( ) β 1 + ( )re ---------------------------------------= 1 Re re ----- 1 gmRe + + = Re Rin.
Avo, vo icRC – = αieRC – = ie Avo α RC re Re + ----------------– = re R + e.
Avo α re ----RC 1 Re re ⁄ + -----------------------– = Avo gmRC 1 Re re ⁄ + ----------------------- gmRC 1 gmRe + ---------------------– – = Re 1 gmRe + ( ) Rin Re.
Ro Ro RC = 434 Chapter 6 Bipolar Junction Transistors (BJTs) If a load resistance is connected at the amplifier output, can be found as (6.87) which could have been written directly using Eq. (6.78). The overall voltage gain can now be found: Substituting for from Eq. (6.83) and replacing with results in (6.88) which is a direct application of the general expression presented in Eq. (6.80). We observe that the overall voltage gain is lower than the value without because of the additional term in the denominator. The gain, however, is less sensitive to the value of a desirable result.
Another important consequence of including the resistance in the emitter is that it enables the amplifier to handle larger input signals without incurring nonlinear distortion.
This is because only a fraction of the input signal at the base, appears between the base and the emitter. Specifically, from the circuit in Fig. 6.52(b), we see that (6.89) Thus, for the same , the signal at the input terminal of the amplifier, can be greater than for the CE amplifier by the factor To summarize, including a resistance in the emitter of the CE amplifier results in the following characteristics: 1. The input resistance is increased by the factor 2. The voltage gain from base to collector, is reduced by the factor 3. For the same nonlinear distortion, the input signal can be increased by the factor 4. The overall voltage gain is less dependent on the value of 5. The high-frequency response is significantly improved (as we shall see in Chapter 9).
With the exception of gain reduction, these characteristics represent performance improvements.
Indeed, the reduction in gain is the price paid for obtaining the other performance improvements.
In many cases this is a good bargain; it is the underlying philosophy for the use of negative feed-back. That the resistance introduces negative feedback in the amplifier circuit can be seen by reference to Fig. 6.52(a): While keeping constant, assume that for some reason the collector current increases; the emitter current also will increase, resulting in an increased voltage drop across Thus the emitter voltage rises, and the base–emitter voltage decreases. The latter effect causes the collector current to decrease, counteracting the initially assumed change, an indication of the presence of negative feedback. In Chapter 10, where we shall study negative RL Av Av Avo RL RL Ro + ------------------= α RC re Re + ----------------RL RL RC + -------------------– = α RC RL || re Re + ------------------– = Gv Gv Rin Rin Rsig + ----------------------α RC RL || re Re + ------------------– × = Rin α β β 1 + ( ) ⁄ Gv β RC RL || Rsig β 1 + ( ) re Re + ( ) + ------------------------------------------------------– = Gv Re β 1 + ( )Re β, Re vi, vπ vi -----re re Re + ---------------- 1 1 gmRe + ---------------------= vπ vi, 1 gmRe + ( ).
Re Rin 1 gmRe + ( ).
Av, 1 gmRe + ( ).
vi 1 gmRe + ( ).
β.
Re vi Re.
6.6 Basic BJT Amplifier Configurations 435 feedback formally, we will find that the factor which appears repeatedly, is the “amount of negative-feedback” introduced by Finally, we note that the negative-feedback action of gives it the name emitter degeneration resistance.
1 gmRe + ( ), Re.
Re For the CE amplifier specified in Example 6.17, what value of is needed to raise to a value four times that of ? With included, find and Also, if is limited to 5 mV, what are the corresponding values of and Solution To obtain , the required is found from With Thus, V/V (unchanged) V/V V/V For mV, mV Thus, while has decreased to about a third of its original value, the amplifier is able to produce as large an output signal as before for the same nonlinear distortion.
Re Rin Rsig Re Avo, Ro, Av, Gv.
v ˆ π v ˆ sig v ˆ o?
Rin 4 = Rsig 4 5 20 kΩ = × = Re 20 β 1 + ( ) = re Re + ( ) β 100, = re Re 200 Ω + Re 200 25 175 Ω = – = Avo α RC re Re + ----------------– = 5000 25 175 + ---------------------– ⎝ ⎠ ⎛ ⎞ 25 – = Ro RC = 5 kΩ = Av Avo RL RL Ro + ------------------= 25 5 5 5 + ------------× 12.5 – = – = Gv Rin Rin Rsig + ----------------------= Av 20 20 5 + ---------------12.5 × 10 – = – = v ˆ π 5 = v ˆi v ˆπ re Re + re ----------------⎝ ⎠ ⎛ ⎞ = 5 1 175 25 ---------+ ⎝ ⎠ ⎛ ⎞ 40 = = v ˆ sig v ˆ i Rin Rsig + Rin ----------------------= 40 1 5 20 ------+ ⎝ ⎠ ⎛ ⎞ 50 mV = = v ˆ o v ˆ sig Gv × = 50 10 500 mV = 0.5 V = × = Gv Example 6.18 436 Chapter 6 Bipolar Junction Transistors (BJTs) 6.6.5 The Common-Base (CB) Amplifier Figure 6.53(a) shows a common-base amplifier with the biasing circuit omitted. The amplifier is fed with a signal source characterized by and Since appears in series with the emitter, it is more convenient to represent the transistor with the T model than with the hybrid-π model. Doing this, we obtain the amplifier equivalent circuit shown in Fig. 6.53(b). Note that we have not included . This is because including would complicate the analysis consider-ably, for it would appear between the output and input of the amplifier. Fortunately, it turns out that the effect of on the performance of a discrete CB amplifier is very small. We will con-sider the effect of when we study the IC form of the CB amplifier in Chapter 7.
6.43 Show that with included, and limited to a maximum value the maximum allowable input signal, is given by If the transistor is biased at mA and has a of 100, what value of is needed to permit an input signal of 100 mV from a source with a resistance while limiting to 10 mV? What is for this amplifier? If the total resistance in the collector is 10 k what value results?
Ans. 350 ; 40.4 k ; V/V Re vπ v ˆ π, v ˆ sig, v ˆ sig v ˆ π 1 Re re -----Rsig rπ --------+ + ⎝ ⎠ ⎛ ⎞ = IC 0.5 = β Re v ˆ sig Rsig 10 kΩ = v ˆ π Rin Ω, Gv Ω Ω 19.8 – EXERCISE vsig Rsig.
Rsig ro ro ro ro vi vo Ro RC Rin re vsig Rsig RC (b) ie ie re Figure 6.53 (a) CB amplifier with bias details omitted; (b) Amplifier equivalent circuit with the BJT represented by its T Model.
vi vo Ro vsig Rsig Rin RC (a) 6.6 Basic BJT Amplifier Configurations 437 From inspection of the equivalent circuit in Fig. 6.53(b), we see that the input resistance is (6.90) This should have been expected, since we are looking into the emitter and the base is grounded. Typically is a few ohms to a few tens of ohms; thus the CB amplifier has a low input resistance.
To determine the voltage gain, we write at the collector node and substitute for the emitter current from to obtain (6.91) which except for its positive sign is identical to the expression for for the CE amplifier.
The output resistance of the CB circuit can be found by inspection of the circuit in Fig.
6.53(b) as (6.92) which is the same as in the case of the CE amplifier (with neglected).
Although the gain of the CB amplifier proper has the same magnitude as that of the CE amplifier, this is usually not the case for the overall voltage gain. The low input resistance of the CB amplifier can cause the input signal to be severely attenuated, specifically, (6.93) from which we see that except for situations in which is on the order of the signal transmission factor can be very small. It is useful at this point to mention that one of the applications of the CB circuit is to amplify high-frequency signals that appear on a coax-ial cable. To prevent signal reflection on the cable, the CB amplifier is required to have an input resistance equal to the characteristic resistance of the cable, which is usually in the range of 50 to 75 If a load resistance is connected to the amplifier output terminal, it will appear in par-allel with and thus can be determined as The overall voltage gain can now be obtained by multiplying with the expression for in Eq. (6.93), (6.94) Since , we see that the overall voltage gain is simply the ratio of the total resistance in the collector circuit to the total resistance in the emitter circuit. We also note that the overall Rin re = re vo αieRC – = ie vi re ----– = Avo vo vi ----α re ----RC gmRC = = ≡ Avo Ro RC = ro vi vsig -------Rin Rsig Rin + ----------------------re Rsig re + -------------------= = Rsig re, vi vsig ⁄ Ω Ω.
RL RC Av Av gm RC RL || ( ) = Gv Av vi vsig ⁄ Gv re Rsig re + ------------------- gm RC RL || ( ) = α RC RL || Rsig re + -------------------= α 1 438 Chapter 6 Bipolar Junction Transistors (BJTs) voltage gain is almost independent of the value of (except through the small dependence of on ), a desirable property. Observe that for of the same order as and , the gain will be very small.
In summary, the CB amplifier exhibits a very low input resistance , an open-circuit voltage gain that is positive and equal in magnitude to that of the CE amplifier ( ), and, like the CE amplifier, a relatively high output resistance . Because of its very low input resistance, the CB circuit alone is not attractive as a voltage amplifier except in specialized applications, such as the cable amplifier mentioned above. The CB amplifier has excellent high-frequency performance, which as we shall see in Chapters 7 and 9, makes it useful in combination with other circuits in the implementation of high-frequency amplifiers.
6.6.6 The Common-Collector Amplifier or Emitter Follower The last of the basic BJT amplifier configurations is the common-collector amplifier, a very important circuit that finds frequent application in the design of both small-signal amplifiers and amplifiers that are required to handle large signals and deliver substantial amounts of signal power to a load. This latter variety will be studied in Chapter 11. As well, the common-collector amplifier is utilized in a significant family of digital logic circuits (Chapter 14).
The circuit is more commonly known by the alternative name emitter follower; the reason for this will become apparent shortly. The Need for Voltage Buffers Before delving into the analysis of the emitter follower, it is useful to look at one of its most common applications. Consider the situation depicted in Fig.
6.54(a). A signal source delivering a signal of reasonable strength (200 mV) with an internal resistance of 100 k is to be connected to a 1-k load resistance. Connecting the source to the load directly as in Fig. 6.54(b) would result in severe attenuation of the signal; the signal appearing across the load will be only of the input signal, or about 2 mV. An alternative course of action is suggested in Fig. 6.54(c). Here we have interposed an amplifier between the source and the load. Our amplifier, however, is unlike the amplifiers we have been studying in this chapter thus far; it has a voltage gain of unity. This is because our signal is already of sufficient strength and we do not need to increase its amplitude.
Note, however, that our amplifier has an input resistance of 100 k thus half the input sig-nal (100 mV) will appear at the input of the amplifier proper. Since the amplifier has a low β α β Rsig RC RL re ( ) gmRC RC ( ) 6.44 Consider a CB amplifier utilizing a BJT biased at mA and with k Determine and If the amplifier is loaded in k what value of results? What is obtained if k ?
Ans. 25 ; 200 V/V; 5 k ; V/V; 0.5 V/V 6.45 A CB amplifier is required to amplify a signal delivered by a coaxial cable having a characteristic resistance of 50 What bias current should be utilized to obtain that is matched to the cable resistance? To obtain an overall voltage gain of of 40 V/V, what should the total resistance in the collector (i.e., ) be?
Ans. 0.5 mA; 4 k IC 1 = RC 5 = Ω.
Rin, Avo, Ro, RL 5 = Ω, Av Gv Rsig 5 = Ω Ω Ω 100 Ω.
IC Rin Gv RC RL || Ω EXERCISES Ω, Ω 1 100 1 + ( ) ⁄ Ω; 6.6 Basic BJT Amplifier Configurations 439 output resistance (10 ), 99% of this signal (99 mV) will appear at the output. This is a sig-nificant improvement over the situation with the source connected directly to the load. As will be seen shortly, the emitter follower can easily implement the unity-gain buffer ampli-fier shown in Fig. 6.54(c).
Characteristic Parameters of the Emitter Follower Figure 6.55(a) shows a common-collector amplifier or emitter follower, as we will refer to it henceforth. Note that the biasing circuit is not shown. The emitter follower is fed with a signal source ( ) and has a load resistance connected between emitter and ground. To keep things simple, we are as-suming that includes both the actual load and any other resistance that may be present be-tween emitter and ground. Normally the actual would be much lower in value than such other resistances and thus would dominate.
Since the BJT has a resistance connected in its emitter, it is most convenient to use the T model to represent the BJT. Doing this results in the emitter-follower equivalent cir-cuit shown in Fig. 6.55(b). We have included simply because it is very easy to do so.
However, note that appears in parallel with , and in discrete circuits is much larger than and can thus be neglected. The resulting simplified circuit shown in Fig. 6.55(c), can now be used to determine the characteristic parameters of the amplifier. The input resistance is found from Substituting for where is given by Ω RL 1 k (a) vsig 200 mV Rsig 100 k RL 1 k (b) vsig 200 mV Rsig 100 k 2 mV RL 1 k (c) vsig 200 mV vo 99 mV Rsig 100 k Ro 10 Rin 100 k Avo 1 Figure 6.54 Illustrating the need for a unity-gain buffer amplifer.
vsig, Rsig RL RL RL RL ro ro RL RL Rin Rin vi ib ----= ib ie β 1 + ( ) ⁄ = ie ie vi re RL + ----------------= 440 Chapter 6 Bipolar Junction Transistors (BJTs) vsig Rsig RL Ro (a) Rin vo vi vsig Rsig ro re ie aie (b) RL vi vo vsig Rsig re ie (c) RL vo vi Rin (b1) (re RL) ie Ro re ib (1a) ie ie/ b1 Figure 6.55 (a) Common-collector amplifier or emitter-follower. (b) Equivalent circuit obtained by replacing the BJT with its T model. Note that ro appears in parallel with RL. Since in discrete circuits r0 RL, we shall neglect it, thus obtaining the simplified circuit in (c).
6.6 Basic BJT Amplifier Configurations 441 we obtain (6.95) a result that we could have written directly, utilizing the resistance-reflection rule. Note that as expected the emitter follower takes the low load resistance and reflects it to the base side, where the signal source is, after increasing its value by a factor It is this impedance transformation property of the emitter follower that makes it useful in connecting a low-resistance load to a high-resistance source, that is, to implement a buffer amplifier.
The voltage gain is given by (6.96) Setting yields (6.97) Thus, as expected, the open-circuit voltage gain of the emitter follower proper is unity16 which means that the signal voltage at the emitter follows that at the base; which is the origin of the name “emitter follower.” To determine refer to Fig. 6.55(c) and look back into the emitter (i.e., behind or exclud-ing ) while setting (i.e., grounding the base). You will see of the BJT, thus (6.98) This result together with yields in Eq. (6.96), thus confirming our earlier analysis.
Overall Voltage Gain We now proceed to determine the overall voltage gain as follows: Substituting for from Eq. (6.96), results in (6.99) This equation indicates that the overall gain, though lower than one, can be close to one if is larger or comparable in value to This again confirms the action of the emit-ter follower in delivering a large proportion of to a low-valued load resistance even though can be much larger than . The key point is that is multiplied by 16In practice, the value of will be lower than, but close to unity. For one thing, which we have neglected, would make . Also, as already mentioned, there may be other resistances (e.g., for biasing purposes) attached to the emitter.
Rin β 1 + ( ) re RL + ( ) = β 1 + ( ).
Av Av vo vi ----RL RL re + ----------------= ≡ RL ∞ = Avo, Avo 1 = Avo ro, Avo ro ro re + ( ) ⁄ = Ro, RL vi 0 = re Ro re = Avo 1 = Av Gv, vi vsig -------Rin Rin Rsig + ----------------------= β 1 + ( ) re RL + ( ) β 1 + ( ) re RL + ( ) Rsig + ------------------------------------------------------= Gv vo vsig --------vi vsig --------Av × = ≡ Av Gv β 1 + ( )RL β 1 + ( )RL β 1 + ( )re Rsig + + -------------------------------------------------------------------= β 1 + ( )RL Rsig.
vsig RL Rsig RL RL β 1 + ( ) 442 Chapter 6 Bipolar Junction Transistors (BJTs) before it is “presented to the source.” Figure 6.56(a) shows an equivalent circuit of the emitter follower obtained by simply reflecting and to the base side. The overall voltage gain can be determined directly and very simply from this circuit by using the voltage divider rule. The result is the expression for already given in Eq. (6.99).
Dividing all resistances in the circuit of Fig. 6.56(a) by does not change the voltage ratio Thus we obtain another equivalent circuit, shown in Fig. 6.56(b), that can be used to determine of the emitter follower. A glance at this circuit reveals that it is simply the equivalent circuit obtained by reflecting and from the base side to the emitter side. In this reflection, does not change, but is divided by . Thus, we either reflect to the base side and obtain the circuit in Fig. 6.56(a) or reflect to the emitter side and obtain the circuit in Fig. 6.56(b). From the latter, can be found as (6.100) Observe that this expression is the same as that in Eq. (6.99) except for dividing both the numerator and denominator by .
The expression for in Eq. (6.100) has an interesting interpretation: The emitter fol-lower reduces by the factor before “presenting it to the load resistance ”: an impedance transformation that has the same buffering effect.
At this point it is important to note that although the emitter follower does not provide voltage gain it has a current gain of .
Thévenin Representation of the Emitter-Follower Output A more general repre-sentation of the emitter-follower output is shown in Fig. 6.57(a). Here is the overall open-circuit voltage gain that can be obtained by setting in the circuit of Fig.
6.56(b), as illustrated in Fig. 6.57(b). The result is . The output resistance is dif-ferent from To determine we set to zero (rather than setting to zero). Again we can use the equivalent circuit in Fig. 6.56(b) to do this, as illustrated in Fig. 6.57(c). We see that (6.101) re RL Gv vo vsig ⁄ ≡ Gv β 1 + vo vsig.
⁄ Gv vo vsig ⁄ ≡ vsig Rsig vsig Rsig β 1 + Gv (a) vo vsig Rsig (b1) re (b1) RL re RL (b) vo vsig Rsig /(b1) Figure 6.56 Simple equivalent circuits for the emitter follower obtained by (a) reflecting re and RL to the base side, and (b) reflecting vsig and Rsig to the emitter side. Note that the circuit in (b) can be obtained from that in (a) by simply dividing all resistances by ( ).
β 1 + Gv vo vsig -------RL RL re Rsig β 1 + ( ) ⁄ + + -----------------------------------------------------= ≡ β 1 + Gv Rsig β 1 + ( ) RL β 1 + Gvo RL ∞ = Gvo 1 = Rout Ro.
Rout vsig vi Rout re Rsig β 1 + ------------+ = 6.6 Basic BJT Amplifier Configurations 443 Finally, we show in Fig. 6.57(d) the emitter-follower circuit together with its and Observe that is determined by reflecting and to the base side (by multiply-ing their values by ). To determine grab hold of the emitter and walk (or just look!) backward while You will see in series with which because it is in the base must be divided by We note that unlike the CE and CB amplifiers we studied earlier, the emitter follower is not unilateral. This is manifested by the fact that depends on and depends on Rin Rout.
Rin re RL RL (a) vo Gvo vsig Rout (b) vo vsig vsig Rsig /(b1) Gvo 1 re (c) Rsig/(b1) re E Rout re Rsig b1 (d) Rsig RL Rin (b1) (reRL) Rout re Rsig (b1) vsig re Figure 6.57 (a) Thévenin representation of the output of the emitter follower. (b) Obtaining Gvo from the equivalent circuit in Fig. 6.56(b). (c) Obtaining Rout from the equivalent circuit in Fig. 6.56(b) with vsig set to zero. (d) The emitter follower with Rin and Rout determined simply by looking into the input and output ter-minals, respectively.
β 1 + Rout, vsig 0.
= re Rsig, β 1 + ( ).
Rin RL Rout Rsig.
It is required to design an emitter follower to implement the buffer amplifier of Fig. 6.54(c). Specify the required bias current and the minimum value the transistor must have. Determine the maximum allowed value of if is to be limited to 5 mV in order to obtain reasonably linear operation. With mV, determine the signal voltage at the output if is changed to 2 k and to 0.5 k IE β vsig vπ vsig 200 = RL Ω, Ω.
Example 6.19 444 Chapter 6 Bipolar Junction Transistors (BJTs) Solution The emitter-follower circuit is shown in Fig. 6.58. To obtain we bias the transistor to obtain Thus, mA The input resistance will be Thus, the BJT should have a with a minimum value of 98. A higher would obviously be beneficial.
The overall voltage gain can be determined from Assuming , the value of obtained is Thus when mV, the signal at the output will be 100 mV. Since the 100 mV appears across the 1-k load, the signal across the base–emitter junction can be found from mV If mV then can be increased by a factor of 5, resulting in V.
To obtain as the load is varied, we use the Thévenin equivalent of the emitter follower, shown in Fig. 6.57(a) with and Ro 10 Ω, = re 10 Ω.
= Ro 10 vo Rin 100 k Rsig 100 k 200 mV vsig RL 1 k Figure 6.58 Circuit for Example 6.19. Example 6.19 continued 10 Ω VT IE ------= IE 2.5 = Rin Rin β 1 + ( ) re RL + ( ) = 100 β 1 + ( ) 0.01 1 + ( ) = β β Gv vo vsig -------RL RL re Rsig β 1 + ( ) -----------------+ + -----------------------------------------= ≡ β 100 = Gv Gv 0.5 = vsig 200 = Ω vπ vo RL ------re × = 100 1000 ------------10 1 = × = v ˆπ 5 = vsig v ˆ sig 1 = vo Gvo 1 = Rout Rsig β 1 + ------------re 100 101 ---------0.01 1 kΩ = + = + = 6.6 Basic BJT Amplifier Configurations 445 6.6.7 Summary and Comparisons For easy reference and to enable comparisons, we present in Table 6.5 the formulas for determining the characteristic parameters of discrete BJT amplifiers. Note that has been neglected throughout. As has already been mentioned, this is possible in discrete-circuit amplifiers. In addition to the remarks made throughout this section about the characteristics and applicability of the various configurations, we make the following concluding points.
1. The CE configuration is the one best suited for realizing the bulk of the gain required in an amplifier. Depending on the magnitude of the gain required, either a single stage or a cascade of two or three stages can be used.
2. Including a resistor in the emitter lead of the CE stage provides a number of perfor-mance improvements at the expense of gain reduction.
3. The low input resistance of the CB amplifier makes it useful only in specific applications.
As we shall see in Chapter 9, it has a much better high-frequency response than the CE amplifier. This superiority will make it useful as a high-frequency amplifier, especially when combined with the CE circuit. We shall see one such combination in Chapter 7.
4. The emitter follower finds application as a voltage buffer for connecting a high-resistance source to a low-resistance load and as the output stage in a multistage amplifier, where its purpose is to equip the amplifier with a low output-resistance.
to obtain For and for vo vsig RL RL Rout + ---------------------= RL 2 kΩ, = vo 200 mV 2 2 1 + ------------× 133.3 mV = = RL 0.5 kΩ, = vo 200 mV 0.5 0.5 1 + ----------------× 66.7 mV = = 6.46 An emitter follower utilizes a transistor with and is biased at mA. It operates be-tween a source having a resistance of 10 k and a load of 1 k Find and What is the peak amplitude of that results in having a peak amplitude of 5 mV? Find the resulting peak amplitude at the output.
Ans. 101.5 k ; 1 V/V; 104 ; 0.91 V/V; 1.1 V; 1 V β 100 = IC 5 = Ω Ω.
Rin, Gvo, Rout, Gv.
vsig vπ Ω Ω EXERCISE ro Re 446 Chapter 6 Bipolar Junction Transistors (BJTs) .
6.7 Biasing in BJT Amplifier Circuits Having studied the various configurations of BJT amplifiers, we now address the important question of biasing and its relationship to small-signal behavior. The biasing problem is that of establishing a constant dc current in the collector of the BJT. This current has to be calcu-lable, predictable, and insensitive to variations in temperature and to the large variations in the value of β encountered among transistors of the same type. Another important consider-ation in bias design is locating the dc bias point in the iC–vCE plane to allow for maximum output signal swing (see the discussion in Section 6.4.6). In this section, we shall deal with various approaches to solving the bias problem in transistor circuits designed with discrete devices. Bias methods for integrated-circuit design are presented in Chapter 7.
Before presenting the “good” biasing schemes, we should point out why two obvious arrangements are not good. First, attempting to bias the BJT by fixing the voltage V BE by, for instance, using a voltage divider across the power supply V CC, as shown in Fig. 6.59(a), is not a viable approach: The very sharp exponential relationship iC–vBE means that any small and inevitable differences in V BE from the desired value will result in large differences in IC and in V CE. Second, biasing the BJT by establishing a constant current in the base, as shown in Fig. 6.59(b), where is also not a recommended approach. Here the typically large variations in the value of β among units of the same device type will result in correspondingly large variations in IC and hence in V CE.
TABLE 6.5 Characteristics of BJT Amplifiersa, b, c Common emitter (Fig. 6.50) Common emitter with (Fig. 6.52) Common base (Fig. 6.53) Emitter follower (Fig. 6.55) 1 a For the interpretation of Rm, Avo, and Ro refer to Fig. 6.49.
b The BJT output resistance ro has been neglected, which is permitted in the discrete-circuit amplifiers studied in this chapter. For integrated-circuit ampli-fiers (Chapter 7), ro must always be taken into account.
c Setting β = (α = 1) and replacing re with 1/gm, RC with RD, and Re with Rs results in the corresponding formulas for MOSFET amplifiers (Table 5.4).
Rin Avo Ro Av Gv β 1 + ( )re gmRC – RC gm RC RL || ( ) – αRC RL || re ------------------– β RC RL || Rsig β 1 + ( )re + -------------------------------------– Re β 1 + ( ) re Re + ( ) gmRC 1 gmRe + ---------------------– RC gm RC RL || ( ) – 1 gmRe + --------------------------------αRC RL || re Re + ------------------– β RC RL || Rsig β 1 + ( ) re Re + ( ) + ------------------------------------------------------– re gmRC RC gm RC RL || ( ) αRC RL || re ------------------α RC RL || Rsig re + -------------------β 1 + ( ) re RL + ( ) re RL RL re + ----------------RL RL re Rsig β 1 + ( ) ⁄ + + -----------------------------------------------------Gvo 1 = Rout re Rsig β 1 + ------------+ = ∞ IB VCC 0.7 – ( ) RB, ⁄ ( 6.7 Biasing in BJT Amplifier Circuits 447 6.7.1 The Classical Discrete-Circuit Bias Arrangement Figure 6.60(a) shows the arrangement most commonly used for biasing a discrete-circuit transistor amplifier if only a single power supply is available. The technique consists of sup-plying the base of the transistor with a fraction of the supply voltage VCC through the voltage divider R1, R2. In addition, a resistor RE is connected to the emitter.
Figure 6.60(b) shows the same circuit with the voltage divider network replaced by its Thévenin equivalent, (6.102) Figure 6.59 Two obvious schemes for biasing the BJT: (a) by fixing VBE; (b) by fixing IB. Both result in wide variations in IC and hence in VCE and therefore are considered to be “bad.” Neither scheme is recommended.
Figure 6.60 Classical biasing for BJTs using a single power supply: (a) circuit; (b) circuit with the voltage divider supplying the base replaced with its Thévenin equivalent.
(a) RB2 RB1 VBE RC VCC IC IB VCE (b) RB RC VCC IC IB VCE VBE R1 (a) RE R2 VCC RC VBB VCC R1 R2 R2 RB R1 R2 L IB IE IC RC RE VCC (b) VBB R2 R1 R2 + -----------------VCC = 448 Chapter 6 Bipolar Junction Transistors (BJTs) (6.103) The current IE can be determined by writing a Kirchhoff loop equation for the base–emitter– ground loop, labeled L, and substituting (6.104) To make IE insensitive to temperature and β variation,17 we design the circuit to satisfy the following two constraints: (6.105) (6.106) Condition (6.105) ensures that small variations in V BE ( 0.7 V) will be swamped by the much larger V BB. There is a limit, however, on how large V BB can be: For a given value of the supply voltage V CC, the higher the value we use for V BB, the lower will be the sum of voltages across RC and the collector–base junction (V CB). On the other hand, we want the voltage across RC to be large in order to obtain high voltage gain and large signal swing (before tran-sistor cutoff). We also want V CB (or V CE) to be large to provide a large signal swing (before transistor saturation). Thus, as is the case in any design, we have a set of conflicting require-ments, and the solution must be a trade-off. As a rule of thumb, one designs for V BB about V CB (or V CE) about and IC RC about Condition (6.106) makes IE insensitive to variations in β and could be satisfied by select-ing RB small. This in turn is achieved by using low values for R1 and R2. Lower values for R1 and R2, however, will mean a higher current drain from the power supply, and will result in a lowering of the input resistance of the amplifier (if the input signal is coupled to the base),18 which is the trade-off involved in this part of the design. It should be noted that condition (6.106) means that we want to make the base voltage independent of the value of β and determined solely by the voltage divider. This will obviously be satisfied if the current in the divider is made much larger than the base current. Typically one selects R1 and R2 such that their current is in the range of IE to 0.1IE.
Further insight regarding the mechanism by which the bias arrangement of Fig. 6.60(a) sta-bilizes the dc emitter (and hence collector) current is obtained by considering the feedback action provided by RE. Consider that for some reason the emitter current increases. The voltage drop across RE, and hence V E will increase correspondingly. Now, if the base voltage is deter-mined primarily by the voltage divider R1, R2, which is the case if RB is small, it will remain constant, and the increase in V E will result in a corresponding decrease in V BE. This in turn reduces the collector (and emitter) current, a change opposite to that originally assumed. Thus RE provides a negative feedback action that stabilizes the bias current. This should remind the reader of the resistance Re that we included in the emitter lead of the CE amplifier in Section 6.6.4. We shall study negative feedback formally in Chapter 10.
17Bias design seeks to stabilize either IE or IC since IC = αIE and α varies very little. That is, a stable IE will result in an equally stable IC, and vice versa.
18If the input signal is coupled to the transistor base, the two bias resistances R1 and R2 effectively appear in parallel between the base and ground. Thus, low values for R1 and R2 will result in lowering Rin.
RB R1R2 R1 R2 + -----------------= IB IE β 1 + ( ) ⁄ : = IE VBB VBE – RE RB β 1 + ( ) ⁄ + ----------------------------------------= VBB VBE RE RB β 1 + ------------ 1 3 --VCC, 1 3 ---V CC, 1 3 ---VCC.
6.7 Biasing in BJT Amplifier Circuits 449 19 19Although reducing RE restores IE to the design value of 1 mA, it does not solve the problem of the dependence of the value of IE on β. See Exercise 6.47.
We wish to design the bias network of the amplifier in Fig. 6.60 to establish a current IE = 1 mA using a power supply VCC = +12 V. The transistor is specified to have a nominal β value of 100.
Solution We shall follow the rule of thumb mentioned above and allocate one-third of the supply voltage to the voltage drop across R2 and another one-third to the voltage drop across RC, leaving one-third for possible negative signal swing at the collector. Thus, and RE is determined from From the discussion above we select a voltage divider current of Neglecting the base current, we find and Thus R2 = 40 kΩ and R1 = 80 kΩ. At this point, it is desirable to find a more accurate estimate for IE, taking into account the nonzero base current. Using Eq. (6.104), This is quite a bit lower than 1 mA, the value we are aiming for. It is easy to see from the above equa-tion that a simple way to restore IE to its nominal value would be to reduce RE from 3.3 kΩ by the magni-tude of the second term in the denominator (0.267 kΩ). Thus a more suitable value for RE in this case would be RE = 3 kΩ, which results in IE = 1.01 mA 1 mA.19 It should be noted that if we are willing to draw a higher current from the power supply and to accept a lower input resistance for the amplifier, then we may use a voltage-divider current equal, say, to IE (i.e., 1 mA), resulting in R1 = 8 kΩ and R2 = 4 kΩ. We shall refer to the circuit using these latter values as design 2, for which the actual value of IE using the initial value of RE of 3.3 kΩ will be VB +4 V = VE 4 VBE 3.3 V – = RE VE IE ------3.3 1 -------3.3 kΩ = = = 0.1IE 0.1 1 × 0.1 mA.
= = R1 R2 + 12 0.1 -------120 kΩ = = R2 R1 R2 + ------------------VCC 4 V = IE 4 0.7 – 3.3 kΩ ( ) 80 || 40 ( ) kΩ ( ) 101 ----------------------------------+ --------------------------------------------------------------0.93 mA = = IE 4 0.7 – 3.3 0.027 + ---------------------------0.99 1 mA = = Example 6.20 450 Chapter 6 Bipolar Junction Transistors (BJTs) 6.7.2 A Two-Power-Supply Version of the Classical Bias Arrangement A somewhat simpler bias arrangement is possible if two power supplies are available, as shown in Fig. 6.61. Writing a loop equation for the loop labeled L gives (6.107) Example 6.20 continued In this case, design 2, we need not change the value of RE.
Finally, the value of RC can be determined from Substituting results, for both designs, in RC 12 VC – IC ------------------= IC αIE = 0.99 1 × 0.99 mA 1 mA = = RC 12 8 – 1 ---------------4 kΩ = = 6.47 For design 1 in Example 6.20, calculate the expected range of IE if the transistor used has β in the range of 50 to 150. Express the range of IE as a percentage of the nominal value (IE 1 mA) ob-tained for β = 100. Repeat for design 2.
Ans. For design 1: 0.94 mA to 1.04 mA, a 10% range; for design 2: 0.984 mA to 0.995 mA, a 1.1% range.
EXERCISE IE VEE VBE – RE RB β 1 + ( ) ⁄ + ----------------------------------------= Figure 6.61 Biasing the BJT using two power supplies. Resistor RB is needed only if the signal is to be capacitively coupled to the base. Other-wise, the base can be connected directly to ground, or to a grounded signal source, resulting in almost total β-independence of the bias current.
6.7 Biasing in BJT Amplifier Circuits 451 This equation is identical to Eq. (6.104) except for VEE replacing VBB. Thus the two constraints of Eqs. (6.105) and (6.106) apply here as well. Note that if the transistor is to be used with the base grounded (i.e., in the common-base configuration), then RB can be eliminated altogether.
On the other hand, if the input signal is to be coupled to the base, then RB is needed. We shall study complete circuits of the various BJT amplifier configurations in Section 6.8.
6.7.3 Biasing Using a Collector-to-Base Feedback Resistor Figure 6.62(a) shows a simple but effective alternative biasing arrangement suitable for common-emitter amplifiers. The circuit employs a resistor RB connected between the collec-tor and the base. Resistor RB provides negative feedback, which helps to stabilize the bias point of the BJT. We shall study feedback formally in Chapter 10.
Analysis of the circuit is shown in Fig. 6.62(b), from which we can write Thus the emitter bias current is given by (6.108) D6.48 The bias arrangement of Fig. 6.61 is to be used for a common-base amplifier. Design the circuit to establish a dc emitter current of 1 mA and provide the highest possible voltage gain while al-lowing for a maximum signal swing at the collector of ±2 V. Use +10-V and −5-V power supplies.
Ans. RB = 0; RE = 4.3 kΩ; RC = 8.4 kΩ EXERCISE (a) (b) Figure 6.62 (a) A common-emitter transistor amplifier biased by a feedback resistor RB. (b) Analysis of the circuit in (a).
VCC IERC IBRB VBE + + = IERC IE β 1 + ------------RB VBE + + = IE VCC VBE – RC RB β 1 + ( ) ⁄ + ----------------------------------------= 452 Chapter 6 Bipolar Junction Transistors (BJTs) It is interesting to note that this equation is identical to Eq. (6.109), which governs the operation of the traditional bias circuit, except that VCC replaces VBB and RC replaces RE. It follows that to obtain a value of IE that is insensitive to variation of β, we select Note, however, that the value of RB determines the allowable negative signal swing at the collector since (6.109) 6.7.4 Biasing Using a Constant-Current Source The BJT can be biased using a constant-current source I as indicated in the circuit of Fig.
6.63(a). This circuit has the advantage that the emitter current is independent of the values of β and RB. Thus RB can be made large, enabling an increase in the input resistance at the base without adversely affecting bias stability. Further, current-source biasing leads to significant design simplification, as will become obvious in later sections and chapters.
A simple implementation of the constant-current source I is shown in Fig. 6.63(b). The circuit utilizes a pair of matched transistors Q1 and Q2, with Q1 connected as a diode by shorting its collector to its base. If we assume that Q1 and Q2 have high β values, we can neglect their base currents. Thus the current through Q1 will be approximately equal to IREF, (6.110) Figure 6.63 (a) A BJT biased using a constant-current source I. (b) Circuit for implementing the current source I.
RB β 1 + ( ) ⁄ RC.
VCB IBRB IE RB β 1 + ------------= = D6.49 Design the circuit of Fig. 6.62 to obtain a dc emitter current of 1 mA, maximum gain, and a ±2-V signal swing at the collector; that is, design for VCE = +2.3 V. Let VCC = 10 V and β = 100.
Ans. RB = 162 kΩ; RC = 7.7 kΩ. Note that if standard 5% resistor values are used (Appendix G) we select RB = 160 kΩ and RC = 7.5 kΩ. This results in IE = 1.02 mA and VC = +2.3 V.
EXERCISE IREF VCC VEE – ( ) – VBE – R ------------------------------------------------= (a) VBE VEE Q2 Q1 I V R VCC IREF (b) 6.8 Discrete-Circuit BJT Amplifiers 453 Now, since Q1 and Q2 have the same V BE, their collector currents will be equal, resulting in (6.111) Neglecting the Early effect in Q2, the collector current will remain constant at the value given by this equation as long as Q2 remains in the active region. This can be guaranteed by keeping the voltage at the collector, V, greater than that at the emitter (−VEE) by at least 0.3V.
The connection of Q1 and Q2 in Fig. 6.63(b) is known as a current mirror. We will study current mirrors in detail in Chapter 7. 6.8 Discrete-Circuit BJT Amplifiers With our study of BJT amplifier basics complete, we now put everything together by present-ing practical circuits for discrete-circuit amplifiers. These circuits, which utilize the amplifier configurations studied in Section 6.6 and one of the biasing methods of Section 6.7, can be assembled using off-the-shelf discrete transistors, resistors, and capacitors. Though practical and carefully selected to illustrate some important points, the circuits presented in this section should be regarded as examples of discrete-circuit, bipolar-transistor amplifiers. Indeed, there is a great variety of such circuits, a number of which are explored in the end-of-chapter problems.
In this section we present a series of exercise problems, Exercises 6.51 to 6.55, which are carefully designed to illustrate important aspects of the amplifier circuits studied. These exer-cises are also intended to enable the reader to see more clearly the differences between the var-ious circuit configurations. We strongly urge the reader to solve these exercises. As usual, the answers are provided.
6.8.1 The Basic Structure Figure 6.64 shows the basic circuit that we shall utilize to implement the various configura-tions of discrete BJT amplifiers. Among the various biasing schemes possible for discrete BJT amplifiers (Section 6.7), we have selected, for simplicity and effectiveness, the one employing constant-current biasing. Figure 6.64 indicates the dc currents in all branches and the dc volt-ages at all nodes. We should note that one would want to select a large value for RB in order to keep the input resistance at the base large. However, we also want to limit the dc voltage drop across RB and even more importantly the variability of this dc voltage resulting from the varia-tion in β values among transistors of the same type. The dc voltage VB determines the allow-able negative signal swing at the collector. I IREF VCC VEE VBE – + R --------------------------------------= = 6.50 For the circuit in Fig. 6.63(a) with VCC = 10 V, I = 1 mA, β = 100, RB = 100 kΩ, and RC = 7.5 kΩ, find the dc voltage at the base, the emitter, and the collector. For VEE = 10 V, and neglecting base currents, find the required value of R in order for the circuit of Fig. 6.63(b) to implement the current source I.
Ans. −1 V; −1.7 V; +2.6 V; 19.3 kΩ EXERCISE 454 Chapter 6 Bipolar Junction Transistors (BJTs) Figure 6.64 Basic structure of the circuit used to realize single-stage, discrete-circuit BJT amplifier con-figurations.
RB VBE RC I VCC VEE IB I( 1) IC I VC VCC RCI 1 VB IRB 1 VE VBE IRB 6.51 Consider the circuit of Fig. 6.64 for the case VCC = VEE = 10 V, I = 1 mA, RB = 100 kΩ, RC = 8 kΩ, and β = 100. Find all dc currents and voltages. What are the allowable signal swings at the collector in both directions? How do these values change as β is changed to 50? To 200? Find the values of the BJT small-signal parameters at the bias point (with β = 100). The Early voltage VA = 100 V.
Ans. See Fig. E6.51. Signal swing: for β = 100, +8 V, –3.4 V; for β = 50, +8 V, –4.4 V; for β = 200, +8 V, –2.9 V.
(a) 100 k 8 k 1 mA 10 V 10 V 0.01 mA 2 V 1.7 V 1 V 0.99 1 mA b 100 a 0.99 (b) gm 40 mAV re 25 ro 100 k rp 2.5 k VA 100 V rp ro gmvp E B C vp E C re i B ai ro Figure E6.51 EXERCISE 6.8 Discrete-Circuit BJT Amplifiers 455 6.8.2 The Common-Emitter (CE) Amplifier As mentioned in Section 6.6, the CE configuration is the most widely used of all BJT amplifier circuits. Figure 6.65(a) shows a CE amplifier implemented using the circuit of Fig. 6.64. To establish a signal ground (or an ac ground, as it is sometimes called) at the emitter, a large capacitor CE, usually in the range of microfarads or tens of microfarads is connected between emitter and ground. This capacitor is required to provide a very low impedance to ground (ideally, zero impedance; i.e., in effect, a short circuit) at all signal frequencies of interest. In this way, the emitter signal current passes through CE to ground and thus bypasses the output resistance of the current source I (and any other circuit com-ponent that might be connected to the emitter); hence CE is called a bypass capacitor.
Obviously, the lower the signal frequency, the less effective the bypass capacitor becomes.
This issue will be studied in Section 9.1.2. For our purposes here we shall assume that CE Figure 6.65 (a) A common-emitter amplifier using the structure of Fig. 6.64. (b) Equivalent circuit obtained by replacing the transistor with its hybrid-π model.
(a) VEE VCC (0 V) CC1 CE 0 V Rsig vsig vo RL CC2 I RB RC Rin Ro vi ii vc vp vi (b) RB E rp Rsig vsig B ii gmvp Ro = RC||ro Rin = RB||rp = –gmv (RC || RL || ro) Rib = rp vi vo vp ro RC C RL 456 Chapter 6 Bipolar Junction Transistors (BJTs) is acting as a perfect short circuit and thus is establishing a zero signal voltage at the emitter.
In order not to disturb the dc bias currents and voltages, the signal to be amplified, shown as a voltage source vsig with an internal resistance Rsig, is connected to the base through a large capacitor CC1. Capacitor CC1, known as a coupling capacitor, is required to act as a perfect short circuit at all signal frequencies of interest while blocking dc. Here again we shall assume this to be the case and defer discussion of imperfect signal cou-pling, arising as a result of the rise of the impedance of CC1 at low frequencies, to Section 9.1.2. At this juncture, we should point out that in situations where the signal source can provide a dc path for the dc base current IB without significantly changing the bias point, we may connect the source directly to the base, thus dispensing with CC1 as well as RB. Eliminat-ing RB has the added beneficial effect of raising the input resistance of the amplifier.
The voltage signal resulting at the collector, vc, is coupled to the load resistance RL via another coupling capacitor CC2. We shall assume that CC2 also acts as a perfect short circuit at all signal frequencies of interest; thus the output voltage vo = vc. Note that RL can be an actual load resistor to which the amplifier is required to provide its output voltage signal, or it can be the input resistance of a subsequent amplifier stage in cases where more than one stage of amplification is needed. (We will study multistage amplifiers in Chapter 8.) To determine the characteristic parameters of the CE amplifier, that is, its input resis-tance, voltage gain, and output resistance, we replace the BJT with its hybrid-π, small-signal model. The resulting small-signal equivalent circuit of the CE amplifier is shown in Fig.
6.65(b). The equivalent circuit of Fig. 6.65(b) can be used to determine the amplifier characteris-tic parameters , , , and in exactly the same way we used for the “stripped-down” version of the CE amplifier in Section 6.6.3. We also show some of the analysis done directly on the circuit itself in Fig. 6.65(a).
Observe that the only difference between the circuit in Fig. 6.65(b) and the simplified version in Fig. 6.50(b) is the bias resistance that appears across the amplifier input and thus changes to (6.112) If we can neglect its effect, and we are back to the simpler circuit of Fig. 6.50(b) and the formulas derived in Section 6.6.3. Those formulas, with neglected, were pre-sented in the CE entry in Table 6.4.
If is not much greater than , then it must be taken into account in the analysis. This is a simple task, and we urge the readers to just work their way through the circuit rather than relying on memorized formulas. As a check, however, there is a simple approach to adapt the CE formulas of Table 6.4 to the case at hand: Apply the Thévenin theorem to the network composed of and thus reducing it to a generator and a resistance Now the formulas in the CE entry in Table 6.4 can be changed as follows: Replace the expression for by that in Eq. (6.112); multiply the expression for by the factor and replace in that expres-sion by Rin Av Ro Gv RB Rin Rin RB rπ || = RB rπ ro RB rπ vsig, Rsig, RB, v ′ sig = RB RB Rsig + ( ) ⁄ ( )vsig R′sig Rsig RB.
|| = Rin Gv RB RB Rsig + ( ) ⁄ ; Rsig Rsig RB || ( ).
6.8 Discrete-Circuit BJT Amplifiers 457 6.8.3 The Common-Emitter Amplifier with an Emitter Resistance As demonstrated in Section 6.6.4, a number of beneficial results can be obtained by connect-ing a resistance in the emitter of the transistor. This is shown in Fig. 6.66(a) where is, of course, unbypassed. Figure 6.66(b) shows the small-signal, equivalent-circuit model.
Observe that the only difference between this circuit and the simplified version studied in Section 6.6.4 is the inclusion of the bias resistance , which unfortunately can limit the increase in due to since (6.113) The analysis of the circuits in Fig. 6.66 is straightforward and is illustrated in the figure. The formulas given in Table 6.4 can be adapted to apply to the circuit here by replacing the for-mula for with that in Eq. (6.113), replacing by and multiplying the expression for by the factor Once again, we do not recommend this approach of plugging into formulas; rather, since each circuit the reader will encounter will be different, it is much more useful to work one’s way through the circuit using the analysis methods studied as a guide.
6.52 Consider the CE amplifier of Fig. 6.65(a) when biased as in Exercise 6.51. In particular, refer to Fig. E6.51 for the bias currents and the values of the elements of the BJT model at the bias point. Eval-uate Rin (without and with RB taken into account), Avo (without and with ro taken into account), and Ro (without and with ro taken into account). For RL = 5 kΩ, find Av. If Rsig = 5 kΩ, find the overall voltage gain Gv. If the sine-wave vπ is to be limited to 5 mV peak, what is the maximum allowed peak amplitude of vsig and the corresponding peak amplitude of vo?
Ans. 2.5 kΩ, 2.4 kΩ; –320 V/V, –296 V/V; 8 kΩ, 7.4 kΩ; –119 V/V; –39 V/V; 15 mV; 0.6 V EXERCISE Re Re RB Rin Re, Rin RB β 1 + ( ) re Re + ( ) [ ] || = Rin Rsig R′ sig Rsig RB, || = Gv RB RB Rsig + ( ) ⁄ .
6.53 Consider the emitter-degenerated CE circuit of Fig. 6.66 when biased as in Exercise 6.51. In par-ticular, refer to Fig. E6.51 for the bias currents and for the values of the elements of the BJT model at the bias point. Let the amplifier be fed from a source having Rsig = 5 kΩ, and let RL = 5 kΩ. Find the value of Re that results in Rin equal to four times the source resistance Rsig. For this value of Re, find Avo, Ro, Av, and Gv. If vπ is to be limited to 5 mV, what is the maximum value vsig can have with and without Re included? Find the corresponding vo.
Ans. 225 Ω; –32 V/V; 8 kΩ; –12.3 V/V; –9.8 V/V; 62.5 mV; 15 mV; 0.6 V EXERCISE 458 Chapter 6 Bipolar Junction Transistors (BJTs) Figure 6.66 (a) A common-emitter amplifier with an emitter resistance Re. (b) Equivalent circuit obtained by replacing the transistor with its T model.
(a) VCC (0 V) VEE CE Re 0 V Rsig vsig vo RL CC2 CC1 I RB RC Rin Ro vi ii Rib ib vo vp ie vi re Re = –
ie(RC||RL) = ie ic (b) ic RB E Re RC RL Rsig vsig B ib ii aie ie re Rin = RB||Rib Rib = (b + 1)(re + Re) vi vp vo Ro = RC C ie vi re Re = –
ie(RC||RL) 6.8 Discrete-Circuit BJT Amplifiers 459 6.8.4 The Common-Base (CB) Amplifier Figure 6.67(a) shows a CB amplifier based on the circuit of Fig. 6.64. Observe that since both the dc and ac voltages at the base are zero, we have connected the base directly to ground, thus eliminating resistor RB altogether. Coupling capacitors CC1 and CC2 perform similar functions to those in the CE circuit.
The small-signal, equivalent-circuit model of the amplifier is shown in Fig. 6.67(b). This circuit is identical to that in Fig. 6.53(b), which we analyzed in detail in Section 6.6.5. Thus the analysis of Section 6.6.5, and indeed the results summarized in the CB entry in Table 6.4, apply directly here.
(a) CC2 I RC CC1 Rsig vsig RL vo vo Ro ii ie Rin vi re aie VCC (0 V) VEE (b) RC RL Rsig vsig ii E C aie ie = –vi /re re B Rin= re vi vo Ro = RC = –
ie (RC ||RL ) Figure 6.67 (a) A common-base amplifier using the structure of Fig. 6.64. (b) Equivalent circuit obtained by replacing the transistor with its T model.
460 Chapter 6 Bipolar Junction Transistors (BJTs) 6.8.5 The Emitter Follower An emitter-follower circuit based on the structure of Fig. 6.64 is shown in Fig. 6.68(a).
Observe that since the collector is to be at signal ground, we have eliminated the collector resistance RC. The input signal is capacitively coupled to the base, and the output signal is capacitively coupled from the emitter to a load resistance RL. 6.54 Consider the CB amplifier of Fig. 6.66(a) when designed using the BJT and component values specified in Exercise 6.51. Specifically, refer to Fig. E6.51 for the bias quantities and the values of the components of the BJT small-signal model. Let Rsig = RL = 5 kΩ. Find the values of Rin, Avo, Ro, Av, and Gv. To what value should Rsig be reduced (usually not possible to do!) to obtain an overall voltage gain equal to that found for the CE amplifier in Exercise 6.52, that is, –39 V/V?
Ans. 25 Ω; +320 V/V; 8 kΩ; +123 V/V; 0.005 V/V; 0.6 V/V; 54 Ω vi vsig ⁄ , EXERCISE (a) VEE VCC CC1 RL CC2 Rsig vsig Rin Ro, Rout I vo RB (b) RB re RL Rsig vsig aie ie Rin vi vo ib (1 a)ie ie b 1 Rib Ro, Rout Figure 6.68 (a) An emitter-follower circuit based on the structure of Fig. 6.64. (b) Small-signal equiva-lent circuit of the emitter follower with the transistor replaced by its T model.
6.8 Discrete-Circuit BJT Amplifiers 461 Replacing the BJT with its T model and neglecting we obtain the equivalent circuit shown in Fig. 6.68(b). This circuit is identical to that in the stripped-down case analyzed in Section 6.6.6 except here we have the bias resistance Note that it is very important to select as large a value for as permitted by dc bias considerations, since a low could defeat the purpose of the emitter follower. To appreciate this point recall that the most important feature of the emitter follower is that it multiplies by , thus presenting a high input resistance to the signal source. Here, however, appears in parallel with this increased resistance, resulting in (6.114) Thus ideally, should be much larger than Again we urge the reader to analyze the circuit being studied (here, Fig. 6.68) directly, without the need to refer back to memorized formulas. As a check, however, we note that the results presented in Table 6.4 in the emitter-follower entry apply to the circuit in Fig.
6.68(b) with the following adaptations: Replace the expression for with that in Eq.
(6.114); multiply the expression for by the factor and replace in the expression for by Also, the equivalent circuits in Fig. 6.56 can be adapted to the circuit in Fig. 6.68 by replacing by and by Finally, the Thévenin equivalent in Fig 6.57(a) can be made to apply to the circuit in Fig.
6.67 by using and 6.8.6 The Amplifier Frequency Response Thus far, we have assumed that the gain of BJT amplifiers is constant independent of the frequency of the input signal. This would imply that BJT amplifiers have infinite bandwidth, which of course is not true. To illustrate, we show in Fig. 6.69 a sketch of the magnitude of the gain of a common-emitter amplifier versus frequency. Observe that there is indeed a wide frequency range over which the gain remains almost constant. This obviously is the useful frequency range of operation for the particular amplifier. Thus far, we have been assuming that our amplifiers are operating in this frequency band, called the midband.
ro, RB.
RB RB RL β 1 + ( ) RB Rin RB β 1 + ( ) re RL + ( ) || = RB β 1 + ( ) re RL + ( ).
Rin Gv RB RB Rsig + ( ) ⁄ ; Rsig Gv Rsig RB || ( ).
vsig RB RB Rsig + ( ) ⁄ ( )vsig Rsig Rsig RB || ( ).
Gvo RB RB Rsig + ( ) ⁄ = Rout re Rsig RB || ( ) β 1 + ( ) ⁄ .
+ = 6.55 The emitter follower in Fig. 6.68(a) is used to connect a source with Rsig = 10 kΩ to a load RL = 1 kΩ.
The transistor is biased at I = 5 mA, utilizes a resistance RB = 40 kΩ, and has β = 100. Find Rib, Rin, Gv, Gvo, and Rout. If in order to limit nonlinear distortion, the base–emitter signal voltage is limited to 10 mV peak, what is the corresponding amplitude at the output? What will the overall voltage gain become if RL is changed to 2 kΩ? To 500 Ω?
Ans. 101.5 kΩ; 28.7 kΩ; 0.738 V/V; 0.8 V/V; 84 Ω; 2 V; 0.768 V/V; 0.685 V/V.
EXERCISE 462 Chapter 6 Bipolar Junction Transistors (BJTs) Figure 6.69 indicates that at lower frequencies, the magnitude of amplifier gain falls off.
This is because the coupling and bypass capacitors no longer have low impedances. Recall that we assumed that their impedances were small enough to act as short circuits. Although this can be true at midband frequencies, as the frequency of the input signal is lowered, the reactance of each of these capacitors becomes significant, and it can be shown that this results in the overall voltage gain of the amplifier decreasing.
Figure 6.69 indicates also that the gain of the amplifier falls off at the high-frequency end. This is due to the internal capacitive effects in the BJT. In Chapter 3 we briefly intro-duced such capacitive effects in our study of the pn junction. In Chapter 9 we shall study the internal capacitive effects of the BJT and will augment the hybrid-π model with capaci-tances that model these effects.
We will undertake a detailed study of the frequency response of BJT amplifiers in Chap-ter 9. For the time being, however, it is important for the reader to realize that for every BJT amplifier, there is a finite band over which the gain is almost constant. The boundaries of this useful frequency band or midband, are the two frequencies fL and fH at which the gain drops by a certain number of decibels (usually 3 dB) below its value at midband. As indi-cated in Fig. 6.69, the amplifier bandwidth, or 3-dB bandwidth, is defined as the difference between the lower ( fL) and upper or higher ( fH) 3-dB frequencies: (6.115) and since usually (6.116) A figure-of-merit for the amplifier is its gain–bandwidth product, defined as (6.117) where is the magnitude of the amplifier gain in the midband. It will be seen in Chapter 9 that in amplifier design it is usually possible to trade off gain for bandwidth. One way to accom-plish this, for instance, is by including resistance in the emitter of the CE amplifier.
fL fH f (Hz) (log scale) (dB) V o V sig Low-frequency band Midband • Gain falls off due to the effects of CC1, CC2, and CE High-frequency band • Gain falls off due to the internal capacitive effects in the BJT • All capacitances can be neglected 3 dB 20 log AM (dB) Figure 6.69 Sketch of the magnitude of the gain of a CE amplifier versus frequency. The graph delineates the three frequency bands relevant to frequency-response determination.
1 jωC ⁄ BW fH fL – = fL fH, BW fH GB AM BW = AM Re 6.9 Transistor Breakdown and Temperature Effects 463 6.9 Transistor Breakdown and Temperature Effects We conclude this chapter with a brief discussion of two important nonideal effects in the BJT: voltage breakdown, and the dependence of on and temperature.
6.9.1 Transistor Breakdown The maximum voltages that can be applied to a BJT are limited by the EBJ and CBJ break-down effects that follow the avalanche multiplication mechanism described in Section 3.5.3.
Consider first the common-base configuration. The iC−vCB characteristics in Fig. 6.70(b) indicate that for iE = 0 (i.e., with the emitter open-circuited) the collector–base junction breaks down at a voltage denoted by BV CBO. For iE > 0, breakdown occurs at voltages smaller than BV CBO. Typically, for discrete BJTs, BV CBO is greater than 50 V.
Next consider the common-emitter characteristics of Fig. 6.71, which show breakdown occurring at a voltage BV CEO. Here, although breakdown is still of the avalanche type, the effects on the characteristics are more complex than in the common-base configuration. We will not explain these in detail; it is sufficient to point out that typically BV CEO is about half BV CBO. On transistor data sheets, BV CEO is sometimes referred to as the sustaining voltage LV CEO.
Breakdown of the CBJ in either the common-base or common-emitter configuration is not destructive as long as the power dissipation in the device is kept within safe limits. This, how-ever, is not the case with the breakdown of the emitter–base junction. The EBJ breaks down in an avalanche manner at a voltage BVEBO much smaller than BV CBO. Typically, BV EBO is in the range of 6 V to 8 V, and the breakdown is destructive in the sense that the β of the transistor is permanently reduced. This does not prevent use of the EBJ as a zener diode to generate refer-ence voltages in IC design. In such applications one is not concerned with the β-degradation effect. A circuit arrangement to prevent EBJ breakdown in IC amplifiers will be discussed in Chapter 12. Transistor breakdown and the maximum allowable power dissipation are important parameters in the design of power amplifiers (Chapter 11) .
.
β IC vCB (a) iE iC iE IE1 aIE1 aIE2 iE IE2 iE 0 Saturation region Active region Expanded scale 0.4 0.5 V iC 0 vCB BVCBO (b) Figure 6.70 The BJT common-base characteristics including the transistor breakdown region.
464 Chapter 6 Bipolar Junction Transistors (BJTs) 6.9.2 Dependence of β on IC and Temperature Throughout this chapter we have assumed that the transistor common-emitter dc current gain, or , is constant for a given transistor. In fact, depends on the dc current at which the tran-sistor is biased, as shown in Fig. 6.72. The physical processes that give rise to this dependence are beyond the scope of this book. Note, however, that there is a current range over which is highest. Normally, one biases the transistor to operate at a current within this range.
Figure 6.72 also shows the dependence of on temperature. The fact that increases with temperature can lead to serious problems in transistors that operate at large power lev-els (see Chapter 11).
Figure 6.71 The BJT common-emitter characteristics including the breakdown region.
6.56 What is the output voltage of the circuit in Fig. E6.56 if the transistor BV BCO = 70 V?
Ans. –60 V μA Figure E6.56 EXERCISE β hFE β β β β 6.9 Transistor Breakdown and Temperature Effects 465 Summary Depending on the bias conditions on its two junctions, the BJT can operate in one of three possible modes: cut-off (both junctions reverse biased), active (the EBJ for-ward biased and the CBJ reverse biased), and saturation (both junctions forward biased). Refer to Table 6.1.
For amplifier applications, the BJT is operated in the ac-tive mode. Switching applications make use of the cut-off and saturation modes. A BJT operating in the active mode provides a collector current The base current and the emitter current iE = iC + iB. Also, iC = α iE, and thus and See Table 6.2.
To ensure operation in the active mode, the collector voltage of an npn transistor must be kept higher than ap-proximately 0.4 V below the base voltage. For a pnp transistor the collector voltage must be lower than ap-proximately 0.4 V above the base voltage. Otherwise, the CBJ becomes forward biased, and the transistor en-ters the saturation region.
At a constant collector current, the magnitude of the base–emitter voltage decreases by about 2 mV for every 1°C rise in temperature.
The BJT will be at the edge of saturation when is reduced to about 0.3 V. In saturation, V, and the ratio of to is lower than (i.e., In the active mode, shows a slight dependence on This phenomenon, known as the Early effect, is modeled by ascribing a finite (i.e., noninfinite) output resistance to the BJT: , where is the Early voltage and is the dc collector current without the Early effect taken into account. In discrete circuits, plays a minor role and can usually be neglected. This is not the case, however, in integrated-circuit design (Chapter 7).
The dc analysis of transistor circuits is greatly simpli-fied by assuming that 0.7 V. Refer to Table 6.3. To operate as a linear amplifier, the BJT is biased in the active region and the signal vbe is kept small (vbe VT).
For small signals, the BJT functions as a linear voltage-controlled current source with a transconductance The input resistance between base and emitter, looking into the base, is The input resist-ence between base and emitter, looking into the emitter is . Table 6.4 provides a summary of the small-signal models and the equations for determining their pa-rameters.
Bias design seeks to establish a dc collector current that is as independent of the value of β as possible.
The three basic BJT amplifier configurations are shown in Fig. 6.48. A summary of their characteristic parame-ters is provided in Table 6.5.
μ Figure 6.72 Typical dependence of β on IC and on temperature in an integrated-circuit npn silcon transis-tor intended for operation around 1 mA.
iC ISe vBE /VT.
= iB iC β ⁄ , = β α 1 α – ( ) ⁄ = α β β 1 + ( ) ⁄ .
= vCE vCE 0.2 iC iB β βforced β < ) iC vCE.
ro VA I′C ⁄ = VA I′C ro VBE gm = IC VT ⁄ .
rπ β gm ⁄ .
= re 1 g ⁄ m 466 Chapter 6 Bipolar Junction Transistors (BJTs) The CE amplifier is used to obtain the bulk of the re-quired voltage gain in a cascade amplifier. It has a large voltage gain and a moderate input resistance but a rela-tively high output resistance and limited high-frequency response (Chapter 9).
The input resistance of the common-emitter amplifier can be increased by including an unbypassed resistance in the emitter lead. This emitter-degeneration resistance provides other performance improvements at the ex-pense of reduced voltage gain.
The CB amplifier has a very low input resistance and is useful in a limited number of special applications. It does, however, have an excellent high-frequency response (Chapter 9) and thus can be combined with the CE ampli-fier to obtain an excellent amplifier circuit (Chapter 7).
The emitter follower has a high input resistance and a low output resistance. Thus, it is useful as a buffer am-plifier to connect a high-resistance signal source to a low-resistance load. Another important application of the emitter follower is as the last stage (called the output stage) of a cascade amplifier.
A systematic procedure to analyze an amplifier circuit con-sists of replacing each BJT with one of its small-signal, equivalent circuit models. DC voltage sources are replaced by short circuits and dc current sources by open circuits.
The analysis can then be performed on the resulting equiv-alent circuit. If a resistance is connected in series with the emitter lead of the BJT, the T model is the most convenient to use. Otherwise, the hybrid- model is employed.
The resistance reflection rule is a powerful tool in the anal-ysis of BJT amplifier circuits: All resistances in the emitter circuit including the emitter resistance can be reflected to the base side by multiplying them by . Con-versely, we can reflect all resistances in the base circuit to the emitter side by dividing them by .
Discrete-circuit BJT amplifiers utilize large coupling and bypass capacitors. Example circuits are given in Section 6.8. As will be seen in Chapter 7, this is not the case in IC amplifiers.
π re β 1 + ( ) β 1 + ( ) PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to demon-strate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very challenging and/ or time-consuming; D: design problem.
Section 6.1: Device Structure and Physical operation 6.1 The terminal voltages of various npn transistors are measured during operation in their respective circuits with the following results: In this table, where the entries are in volts, 0 indicates the reference terminal to which the black (negative) probe of the voltmeter is connected. For each case, identify the mode of operation of the transistor.
6.2 Two transistors, fabricated with the same technology but having different junction areas, when operated at a base-emitter voltage of 0.75 V, have collector currents of 0.2 mA and 5 mA. Find IS for each device. What are the relative junc-tion areas?
6.3 In a particular technology, a small BJT operating at conducts a collector current of 100 μA. What is the corresponding saturation current? For a transistor in the same technology but with an emitter junction that is 32 times larger, what is the saturation current? What current will this transistor conduct at ? What is the base–emitter voltage of the latter transistor at iC = 1 mA?
Assume active-mode operation in all cases.
6.4 Two transistors have EBJ areas as follows: AE1 = AE1 = 400 μm × 400 μm and AE2 = 0.4 μm × 0.2 μm. If the two transistors are operated in the active mode and conduct equal collector currents, what do you expect the difference in their values to be?
6.5 Find the collector currents that you would expect for operation at mV for transistors for which Case E B C Mode 1 0 0.7 0.7 2 0 0.8 0.1 3 −0.7 0 0.7 4 −0.7 0 −0.6 5 −2.7 −2.0 0 6 0 0 5.0 vBE 28VT = vBE 28VT = vBE vBE 700 = Problems 467 CHAPTER 6 P RO BL E MS A and A. For the transistor with the larger EBJ, what is the required to provide a collector current equal to that provided by the smaller transistor at mV? Assume active-mode operation in all cases.
6.6 In this problem, we contrast two BJT integrated-circuit fabrication technologies: For the “old” technology, a typical npn transistor has A, and for the “new” tech-nology a typical npn transistor has A. These typical devices have vastly different junction areas and base width. For our purpose here we wish to determine the required to establish a collector current of 1 mA in each of the two typical devices. Assume active-mode operation.
6.7 Consider an npn transistor whose base–emitter drop is 0.76 V at a collector current of 10 mA. What current will it conduct at vBE = 0.70 V? What is its base–emitter voltage for iC = 10 μA?
6.8 In a particular BJT, the base current is 10 μA, and the collector current is 600 μA. Find β and α for this device.
6.9 Find the values of β that correspond to α values of 0.5, 0.8, 0.9, 0.95, 0.99, 0.995, and 0.999.
6.10 Find the values of α that correspond to β values of 1, 2, 10, 20, 100, 200, 1000, and 2000.
6.11 Show that for a transistor with α close to unity, if α changes by a small per-unit amount , the corre-sponding per-unit change in β is given approximately by 6.12 An npn transistor of a type whose β is specified to range from 60 to 300 is connected in a circuit with emitter grounded, collector at +9 V, and a current of 20 μA injected into the base.
Calculate the range of collector and emitter currents that can result. What is the maximum power dissipated in the transistor?
(Note: Perhaps you can see why this is a bad way to establish the operating current in the collector of a BJT.) 6.13 A BJT is specified to have A and that falls in the range of 50 to 200. If the transistor is oper-ated in the active mode with set to 0.650 V, find the expected range of and 6.14 Measurements made on a number of transistors oper-ating in the active mode with mA indicate base cur-rents of 50 μA, 10 μA, and 25 μA. For each device, find and 6.15 Measurement of VBE and two terminal currents taken on a number of npn transistors operating in the active mode are tabulated below. For each, calculate the missing current value as well as α, β, and IS as indicated by the table.
6.16 A particular BJT when operated in the active mode conducts a collector current of 10 mA and has vBE = 0.70 V and iB = 100 μA. Use these data to create specific transistor models of the form shown in Figs. 6.5(a) to (d).
6.17 Using the npn transistor model of Fig. 6.5(b), con-sider the case of a transistor for which the base is connected to ground, the collector is connected to a 10-V dc source through a 2-kΩ resistor, and a 3-mA current source is con-nected to the emitter with the polarity so that current is drawn out of the emitter terminal. If β = 100 and IS = 10–15 A, find the voltages at the emitter and the collector and cal-culate the base current.
D 6.18 Consider an npn transistor operated in the active mode and represented by the model of Fig. 6.5(d). Let the transistor be connected as indicated by the equivalent cir-cuit shown in Fig. 6.6(b). It is required to calculate the val-ues of and that will establish a collector current of 1 mA and a collector-to-emitter voltage of 1 V.
The BJT is specified to have and A.
6.19 An npn transistor has a CBJ with an area 150 times that of the EBJ. If A, find the voltage drop across EBJ and across CBJ when each is forward biased and con-ducting a current of 1 mA. Also find the forward current each junction would conduct when forward biased with 0.5 V.
6.20 We wish to investigate the operation of the npn tran-sistor in saturation using the model of Fig. 6.9. Let A, V, and ISC/IS 100. For each of three values of (namely, 0.4 V, 0.3 V, and 0.1 V), find and Also find that results in .
6.21 Use Eqs. (6.14), (6.15), and (6.16) to show that an npn transistor operated in saturation exhibits a collector-to-emitter voltage, given by IS 10 12 – = IS 10 18 – = vBE vBE 700 = IS 5 10 15 – × = IS 5 10 18 – × = vBE Δα α ⁄ ( ) Δβ β ------- β Δα α -------⎝ ⎠ ⎛ ⎞ IS 5 10 15 – × = β vBE iC, iB, iE.
iE 1 = iC, β, α.
Transistor a b c d e VBE (mV) 690 690 580 780 820 IC (mA) 1.000 1.000 10.10 IB (μA) 50 7 120 1050 IE (mA) 1.070 0.137 75.00 α β IS RB RC IC VCE β 125 = IS 5 10 15 – × = IS 5 10 15 – × = IS 10 15 – = vBE 0.7 = β 100 = = vCE vBC, iBC, iB, iC, iC iB ⁄ .
vCE iC 0 = V CEsat VCEsat VT ISC IS -------⎝ ⎠ ⎛ ⎞1 βforced + 1 βforced β ⁄ – ------------------------------ln = CHAPTER 6 P RO BL E MS 468 Chapter 6 Bipolar Junction Transistors (BJTs) Use this relationship to evaluate for , 10, 5, and 1 for a transistor with and with a CBJ area 100 times that of the EBJ.
6.22 Consider the pnp large-signal model of Fig. 6.11(b) applied to a transistor having IS = 10−13 A and β = 40. If the emitter is connected to ground, the base is connected to a current source that pulls 20 μA out of the base terminal, and the collector is connected to a negative supply of −10 V via a 10-kΩ resistor, find the collector voltage, the emitter cur-rent, and the base voltage.
6.23 A pnp transistor has vEB = 0.8 V at a collector current of 1 A. What do you expect vEB to become at iC = 10 mA? At iC = 5 A?
6.24 A pnp transistor modeled with the circuit in Fig. 6.11 (b) is connected with its base at ground, collector at –1.0 V, and a 10-mA current is injected into its emitter. If the tran-sistor is said to have β = 10, what are its base and collector currents? In which direction do they flow? If IS = 10–15 A, what voltage results at the emitter? What does the collector current become if a transistor with β = 1000 is substituted?
(Note: The fact that the collector current changes by less than 10% for a large change of β illustrates that this is a good way to establish a specific collector current.) 6.25 A pnp power transistor operates with an emitter-to-collector voltage of 5 V, an emitter current of 10 A, and VEB = 0.85 V. For β = 15, what base current is required? What is IS for this transistor? Compare the emitter–base junction area of this transistor with that of a small-signal transistor that conducts iC = 1 mA with vEB = 0.70 V. How much larger is it?
6.26 While Fig. 6.5 provides four possible large-signal equivalent circuits for the npn transistor, only two equivalent circuits for the pnp transistor are provided in Fig. 6.11. Sup-ply the missing two. 6.27 By analogy to the npn case shown in Fig. 6.9, give the equivalent circuit of a pnp transistor in saturation.
Section 6.2: Current–Voltage Characteristics 6.28 For the circuits in Fig. P6.28, assume that the transis-tors have very large β. Some measurements have been made on these circuits, with the results indicated in the figure.
Find the values of the other labeled voltages and currents. 6.29 Measurements on the circuits of Fig. P6.29 produce labeled voltages as indicated. Find the value of β for each transistor.
6.30 A very simple circuit for measuring of an npn transistor is shown in Fig. P6.30. In a particular design, is provided by a 9-V battery; M is a current meter with a 50-μA full scale and relatively low resistance that you can neglect for our purposes here. Assuming that the transistor has V at mA, what value of R would establish a resistor current of 1 mA? Now, to what value of does a meter reading of full scale correspond?
What is if the meter reading is 1/5 of full scale? 1/10 of full scale?
6.31 Repeat Exercise 6.13 for the situation in which the power supplies are reduced to V.
VCEsat βforced 50 = β 100 = V2 (b) 2.4 k 5.6 k 4 V V3 (c) 15 k 10 k 0 V I5 V4 (d) 15 k 5 k V7 I6 0.7 V Figure P6.28 β VCC VBE 0.7 = IE 1 = β β 1.5 ± Problems 469 CHAPTER 6 P RO BL E MS D 6.32 Design the circuit in Fig. P6.32 to establish a cur-rent of 1 mA in the emitter and a voltage of V at the col-lector. The transistor V at mA, and . To what value can be increased while the collector current remains unchanged?
D 6.33 Examination of the table of standard values for resistors with 5% tolerance in Appendix G reveals that the closest values to those found in the design of Example 6.20 are 5.1 kΩ and 6.8 kΩ. For these values use approximate calculations (e.g., VBE 0.7 V and α 1) to determine the values of collector current and collector voltage that are likely to result.
D 6.34 Design the circuit in Fig. P6.34 to establish mA and V. The transistor exhibits of 0.8 V at mA, and .
(a) 200 k 1 k (b) (c) 100 k 6.3 V 7 V Figure P6.29 VCC M RC Figure P6.30 1 – vEB 0.64 = IE 0.1 = β 100 = RC IC 0.1 = VC 0.5 = vBE iC 1 = β 100 = 5 V 5 V RE RC Figure P6.32 1.5 V 1.5 V RC RE VC IC Figure P6.34 CHAPTER 6 P RO BL E MS 470 Chapter 6 Bipolar Junction Transistors (BJTs) 6.35 For each of the circuits shown in Fig. P6.35, find the emitter, base, and collector voltages and currents. Use β = 50, but assume independent of current level.
6.36 The current ICBO of a small transistor is measured to be 10 nA at 25°C. If the temperature of the device is raised to 125°C, what do you expect ICBO to become?
6.37 Augment the model of the npn BJT shown in Fig.
6.18(a) by a current source representing ICBO. Assume that ro is very large and thus can be neglected. In terms of this addi-tion, what do the terminal currents iB, iC, and iE become? If the base lead is open-circuited while the emitter is connected to ground, and the collector is connected to a positive sup-ply, find the emitter and collector currents.
6.38 A BJT whose emitter current is fixed at 1 mA has a base–emitter voltage of 0.69 V at 25°C. What base–emitter voltage would you expect at 0°C? At 100°C?
6.39 A particular pnp transistor operating at an emitter current of 0.5 mA at 20°C has an emitter–base voltage of 692 mV.
(a) What does vEB become if the junction temperature rises to 50°C?
(b) If the transistor is operated at a fixed emitter–base voltage of 700 mV, what emitter current flows at 20°C? At 50°C?
6.40 Consider a transistor for which the base–emitter voltage drop is 0.7 V at 10 mA. What current flows for vBE = 0.5 V?
Evaluate the ratio of the slopes of the iC–vBE curve at vBE = 700 mV and at vBE = 500 mV. The large ratio confirms the point that the BJT has an “apparent threshold” at .
6.41 In Problem 6.40, the stated voltages are measured at 25°C. What values correspond at –25°C? At 125°C?
6.42 Use Eq. (6.18) to plot iC versus vCE for an npn transis-tor having IS = 10−15 A and VA = 100 V. Provide curves for vBE = 0.65, 0.70, 0.72, 0.73, and 0.74 volts. Show the charac-teristics for vCE up to 15 V.
6.43 In the circuit shown in Fig. P6.43, current source I is 1.1 mA, and at 25 C mV at mA. At 25 C with , what currents flow in and ?
What voltage would you expect at node E? Noting that the tem-perature coefficient of for constant is mV/ C, what is the TC of ? For an ambient temperature of 75 C, what voltage would you expect at node E? Clearly state any simplifying assumptions you make.
6.44 For a particular npn transistor operating at a vBE of 670 mV and IC = 2 mA, the iC–vCE characteristic has a slope of 2 × . To what value of output resistance does this correspond? What is the value of the Early voltage for this transistor? For operation at 20 mA, what would the output resistance become?
VBE 0.8 V = 1.5 V 1.5 V 2.2 k 2.2 k Q1 (a) 1.5 V 1.5 V 1 k 1 k Q2 (b) 3 V 1.0 V 1.1 k 560 Q3 (c) 3 V 1.5 V 1 k 470 Q4 (d) Figure P6.35 vBE 0.5V ° vBE 680 = iC 1 = ° β 100 = R1 R2 vBE IC 2 – ° vE ° I R2 68 k R1 6.8 k E Figure P6.43 10 5 – Ω Problems 471 CHAPTER 6 P RO BL E MS 6.45 For a BJT having an Early voltage of 150 V, what is its output resistance at 1 mA? At 100 μA?
6.46 Measurements of the iC–vCE characteristic of a small-signal transistor operating at vBE = 720 mV show that iC = 1.8 mA at vCE = 2 V and that iC = 2.4 mA at vCE = 14 V. What is the corresponding value of iC near saturation? At what value of vCE is iC = 2.0 mA? What is the value of the Early voltage for this transistor? What is the output resistance that corresponds to operation at vBE = 720 mV?
6.47 Give the pnp equivalent circuit models that corre-spond to those shown in Fig. 6.18 for the npn case.
6.48 A BJT operating at iB = 8 μA and iC = 1.2 mA under-goes a reduction in base current of 0.8 μA. It is found that when vCE is held constant, the corresponding reduction in collector current is 0.1 mA. What are the values of β and the incremental β or βac that apply? If the base current is increased from 8 μA to 10 μA and vCE is increased from 8 V to 10 V, what collector current results? Assume VA = 100 V.
6.49 For the circuit in Fig. P6.49 let V, k and k The BJT has Find the value of that results in the transistor operating (a) in the active mode with V; (b) at the edge of saturation; (c) deep in saturation with D 6.50 Consider the circuit of Fig. P6.49 for the case . If the BJT is saturated, use the equivalent circuit of Fig. 6.20 to derive an expression for in terms of and . Also derive an expression for the total power dissipated in the circuit. For V, design the circuit to obtain operation at a forced as close to 10 as possible while limiting the power dissipation to no larger than 20 mW. Use 1% resistors (see Appendix G).
6.51 The pnp transistor in the circuit in Fig. P6.51 has . Show that the BJT is operating in the saturation mode and find and To what value should be increased in order for the transistor to operate at the edge of saturation?
Section 6.3: BJT Circuits at DC 6.52 The transistor in the circuit of Fig. P6.52 has a very high β. Find VE and VC for VB (a) +1.5 V, (b) +1 V, and (c) 0 V. 6.53 The transistor in the circuit of Fig. P6.52 has a very high β. Find the highest value of VB for which the transistor still operates in the active mode. Also, find the value of VB for which the transistor operates in saturation with a forced β of 1.
6.54 Consider the operation of the circuit shown in Fig.
P6.54 for VB at –1 V, 0 V, and +1 V. Assume that β is very high. What values of VE and VC result? At what value of VB does the emitter current reduce to one-tenth of its value for VB = 0 V? For what value of VB is the transistor just at the edge of conduction? What values of VE and VC correspond?
VCC 5 = RC 1 = Ω, RB 20 = Ω.
β 50.
= V BB VC 1 = βforced 10.
= VBB RB RC VCC VC IC Figure P6.49 VBB VCC = βforced VCC RB RC ⁄ ( ) VCC 5 = β β 50 = βforced VC.
RB RB 10 k 1 k 3 V VC Figure P6.51 Figure P6.52 1 k 1 k VB VC VE 3 V CHAPTER 6 P RO BL E MS 472 Chapter 6 Bipolar Junction Transistors (BJTs) For what value of VB does the transistor reach the edge of saturation? What values of VC and VE correspond? Find the value of VB for which the transistor operates in saturation with a forced β of 2.
6.55 For the transistor shown in Fig. P6.55, assume α 1 and vBE = 0.5 V at the edge of conduction. What are the values of VE and VC for VB = 0 V? For what value of VB does the tran-sistor cut off? Saturate? In each case, what values of VE and VC result?
D 6.56 Consider the circuit in Fig. P6.52 with the base voltage VB obtained using a voltage divider across the 3-V supply. Assuming the transistor β to be very large (i.e., ignoring the base current), design the voltage divider to obtain VB = 1.5 V. Design for a 0.1-mA current in the volt-age divider. Now, if the BJT β = 100, analyze the circuit to determine the collector current and the collector voltage.
6.57 A single measurement indicates the emitter voltage of the transistor in the circuit of Fig. P5.57 to be 1.2 V.
Under the assumption that = 0.7 V, what are VB, IB, IE, IC, VC, β, and α? (Note: Isn’t it surprising what a little mea-surement can lead to?) D 6.58 Design a circuit using a pnp transistor for which α 1 using two resistors connected appropriately to ±5 V so that IE = 2 mA and VBC = 2.5 V. What exact values of RE and RC would be needed? Now, consult a table of standard 5% resistor values (e.g., that provided in Appendix G) to select suitable practical values. What values of resistors have you chosen?
What are the values of IE and VBC that result?
6.59 In the circuit shown in Fig. P6.59, the transistor has β = 50. Find the values of VB, VE, and VC. If RB is raised to 100 kΩ, what voltages result? With RB = 100 kΩ, what value of β would return the voltages to the values first calculated?
5 V 5 V 2 k 2 k VE VC VB Figure P6.54 5 mA 1 k 1 k 1 mA VB VC VE Figure P6.55 VBE 5 k 50 k 5 k VB VE VC 5 V 5 V Figure P6.57 5 V 5 V VE VC VB RE 2.2 k RB 20 k RC 2.2 k Figure P6.59 Problems 473 CHAPTER 6 P RO BL E MS 6.60 In the circuit shown in Fig. P6.59, the transistor has β = 50. Find the values of VB, VE, and VC, and verify that the transistor is operating in the active mode. What is the largest value that RC can have while the transistor remains in the active mode?
6.61 For the circuit in Fig. P6.61, find VB, VE, and VC for RB = 100 kΩ, 10 kΩ, and 1 kΩ. Let β = 100.
6.62 For the circuits in Fig. P6.62, find values for the labeled node voltages and branch currents. Assume β to be very high.
6.63 Repeat the analysis of the circuits in Problem 6.62 using β = 100. Find all the labeled node voltages and branch currents.
D 6.64 It is required to design the circuit in Fig. P6.64 so that a current of 1 mA is established in the emitter and a voltage of −5 V appears at the collector. The transistor type used has a nominal β of 100. However, the β value can be as low as 50 and as high as 150. Your design should ensure that the specified emitter current is obtained when β = 100 and that at the extreme values of β the emitter current does not change by more than 10% of its nominal value. Also, design for as large a value for RB as possible. Give the values of RB, RE, and RC to the nearest kilohm. What is the expected range of collector current and collector voltage corresponding to the full range of β values?
D 6.65 The pnp transistor in the circuit of Fig. P6.65 has β = 50. Find the value for RC to obtain VC = +3 V. What hap-pens if the transistor is replaced with another having β = 100? Figure P6.61 1 mA V1 V2 1.6 k 22 k 3 V (a) Figure P6.62 I4 2.2 k 1.6 k 3 V V3 3 V (b) V5 2.2 k V6 1.6 k 3 V 3 V 22 k V7 (c) 56 k V9 5.1 k 3.3 k 3 V 3 V V8 0.7 V (d) V12 V11 150 k V10 91 k 5.1 k 3.3 k 3 V 3 V (e) CHAPTER 6 P RO BL E MS 474 Chapter 6 Bipolar Junction Transistors (BJTs) 6.66 Consider the circuit shown in Fig. P6.66. It resembles that in Fig. 6.29 but includes other features. First, note diodes D1 and D2 are included to make design (and analysis) easier and to provide temperature compensation for the emitter–base volt-ages of Q1 and Q2. Second, note resistor R whose purpose is to provide negative feedback (more on this later in the book!).
Using and VD = 0.7 V independent of current and β = ∞, find the voltages VB1, VE1, VC1, VB2, VE2, and VC2, initially with R open-circuited and then with R connected. Repeat for β = 100, initially with R open-circuited then connected.
6.67 For the circuit shown in Fig. P6.67, find the labeled node voltages for: (a) β = ∞ (b) β = 100 D 6.68 Using β = ∞, design the circuit shown in Fig. P6.68 so that the bias currents in Q1, Q2, and Q3 are 1 mA, 1 mA, and 2 mA, respectively, and V3 = 0, V5 = −2 V, and V7 = 1 V.
For each resistor, select the nearest standard value utilizing the table of standard values for 5% resistors in Appendix G.
Now, for β = 100, find the values of V3, V4, V5, V6, and V7.
6.69 For the circuit in Fig. P6.69, find VB and VE for vI = 0 V, +2 V, −2.5 V, and −5 V. The BJTs have β = 100.
6.70 Find approximate values for the collector volt-ages in the circuits of Fig. P6.70. Also, calculate forced β for each of the transistors. (Hint: Initially, assume all transistors are operating in saturation, and verify the assumption.
C E Figure P6.64 5V Figure P6.65 VBE 80 k 40 k 2 k 2 k 2 k 100 100 9 V Q2 D2 R D1 Q1 Figure P6.66 V4 V5 9.1 k 9.1 k V2 Q1 Q2 V1 V3 100 k 4.3 k 5.1 k 5 V 5 V Figure P6.67 Problems 475 CHAPTER 6 P RO BL E MS Section 6.4: Applying the BJT in Amplifier Design 6.71 A BJT amplifier circuit such as that in Fig. 6.33(a) is operated with VCC = +5 V and is biased at VCE = +1 V.
Find the voltage gain, the maximum allowed output nega-tive swing without the transistor entering saturation, and the corresponding maximum input signal permitted.
6.72 For the amplifier circuit in Fig. 6.33(a) with VCC = +5 V and RC = 1 kΩ, find VCE and the voltage gain at the following dc collector bias currents: 0.5 mA, 1 mA, 2.5 mA, 4 mA, and 4.5 mA. For each, give the maximum possible positive- and negative-output signal swing as determined by the need to keep the transistor in the active region. Present your results in a table.
D 6.73 Consider the CE amplifier circuit of Fig. 6.33(a) when operated with a dc supply VCC = +5 V. It is required to find the point at which the transistor should be biased; that is, find the value of VCE so that the output sine-wave signal vce resulting from an input sine-wave signal vbe of 5-mV peak amplitude has the maximum possible magnitude. What is the 5 V 5 V V2 Q1 V3 V5 Q2 V4 Q3 V7 V6 R6 R4 R1 R2 R3 R5 Figure P6.68 2.5 V 2.5 V Figure P6.69 5 V 5 V Figure P6.70 5 V 5 V CHAPTER 6 P RO BL E MS 476 Chapter 6 Bipolar Junction Transistors (BJTs) peak amplitude of the output sine wave and the value of the gain obtained? Assume linear operation around the bias point.
(Hint: To obtain the maximum possible output amplitude for a given input, you need to bias the transistor as close to the edge of saturation as possible without entering saturation at any time, that is, without vCE decreasing below 0.3 V.) 6.74 A designer considers a number of low-voltage BJT amplifier designs utilizing power supplies with voltage of 1.0, 1.5, 2.0, or 3.0 V. For transistors that saturate at V, what is the largest possible voltage gain achievable with each of these supply voltages? If in each case biasing is adjusted so that , what gains are achieved? If a negative-going output signal swing of 0.4V is required, at what should the tran-sistor be biased to obtain maximum gain? What is the gain achieved with each of the supply voltages? Notice that all of these gains are independent of the value of chosen!) D 6.75 A BJT amplifier such as that in Fig. 6.33(a) is to be designed to support relatively undistorted sine-wave output signals of peak amplitudes P volt without the BJT entering saturation or cutoff and to have a voltage gain of V/V.
Show that the minimum supply voltage needed is given by Also, find , specified to the nearest 0.5 V, for the fol-lowing situations: (a) V/V, V (b) V/V, V (c) V/V, V (d) V/V, V (e) V/V, V (f) V/V, V (g) V/V, V 6.76 The transistor in the circuit of Fig. P6.76 is biased at a dc collector current of 0.4 mA. What is the voltage gain?
(Hint: Use Thévenin’s theorem to convert the circuit to the form in Fig. 6.33a).
6.77 Sketch and label the voltage transfer characteristics of the pnp common-emitter amplifiers shown in Fig. P6.77.
6.78 In deriving the expression for small-signal volt-age gain Av in Eq. (6.31) we neglected the Early effect.
Derive this expression including the Early effect, by sub-stituting in Eq. (6.24) and including the factor in Eq.
(6.28). Show that the gain expression changes to For the case VCC = 5 V and VCE = 2.5 V, what is the gain without and with the Early effect taken into account? Let VA = 100 V.
6.79 When the amplifier circuit of Fig. 6.33(a) is biased with a certain VBE, the dc voltage at the collector is found to be +2 V. For VCC = +5 V and RC = 1 kΩ, find IC and the small-signal voltage gain. For a change ΔvBE = +5 mV, cal-culate the resulting ΔvO. Calculate it two ways: by finding VCC VCE 0.3 = VCE VCC 2 ⁄ = VCE IC Av VCC VCC VCEsat P Av VT + + = VCC Av 20 – = P 0.2 = Av 50 – = P 0.5 = Av 100 – = P 0.5 = Av 100 – = P 1.0 = Av 200 – = P 1.0 = Av 500 – = P 1.0 = Av 500 – = P 2.0 = 5 V 10 k 10 k vI vO Figure P6.76 (a) RC VCC 5 V vI vO Figure P6.77 (b) RC VCC 5 V vI vO iC ISe vBE VT ⁄ 1 vCE VA --------+ ⎝ ⎠ ⎛ ⎞ = 1 vCE VA ⁄ + ( ) Av I – CRC VT ⁄ 1 ICRC VA VCE + ---------------------+ ------------------------------------VCC VCE – ( ) V ⁄ T 1 VCC VCE – VA VCE + ------------------------+ ---------------------------------------– = = Problems 477 CHAPTER 6 P RO BL E MS ΔiC using the transistor exponential characteristic, and approximately using the small-signal voltage gain. Repeat for ΔvBE = –5 mV. Summarize your results in a table.
6.80 Consider the amplifier circuit of Fig. 6.33(a) when operated with a supply voltage VCC = +3V.
(a) What is the theoretical maximum voltage gain that this amplifier can provide?
(b) What value of VCE must this amplifier be biased at to provide a voltage gain of –80 V/V?
(c) If the dc collector current IC at the bias point in (b) is to be 0.5 mA, what value of RC should be used?
(d) What is the value of VBE required to provide the bias point mentioned above? Assume that the BJT has IS = 10–15 A.
(e) If a sine-wave signal vbe having a 5-mV peak amplitude is superimposed on VBE, find the corresponding output volt-age signal vce that will be superimposed on VCE assuming lin-ear operation around the bias point.
(f) Characterize the signal current ic that will be super-imposed on the dc bias current IC.
(g) What is the value of the dc base current IB at the bias point? Assume β = 100. Characterize the signal current ib that will be superimposed on the base current IB.
(h) Dividing the amplitude of vbe by the amplitude of ib, evaluate the incremental (or small-signal) input resistance of the amplifier.
(i) Sketch and clearly label correlated graphs for vBE, vCE, iC, and iB. Note that each graph consists of a dc or average value and a superimposed sine wave. Be careful of the phase rela-tionships of the sine waves.
6.81 The essence of transistor operation is that a change in vBE, ΔvBE, produces a change in iC, ΔiC. By keeping ΔvBE small, ΔiC is approximately linearly related to ΔvBE, ΔiC = gmΔvBE, where gm is known as the transistor transconduc-tance. By passing ΔiC through RC, an output voltage signal ΔvO is obtained. Use the expression for the small-signal voltage gain in Eq. (6.30) to derive an expression for gm.
Find the value of gm for a transistor biased at IC = 1 mA.
6.82 The purpose of this problem is to illustrate the appli-cation of graphical analysis to the circuit shown in Fig.
P6.82. Sketch characteristic curves for the BJT for μA, 10 μA, 20 μA, and 40 μA. Assume the lines to be horizontal (i.e., neglect the Early effect), and let . For V and k sketch the load line. What peak-to-peak collector voltage swing will result for varying over the range 10 μA to 40 μA? If the BJT is biased at find the value of and If at this current V and if k find the required value of .
6.83 Sketch the iC−vCE characteristics of an npn transistor having β = 100 and VA = 100 V. Sketch characteristic curves for iB = 20 μA, 50 μA, 80 μA, and 100 μA. For the purpose of this sketch, assume that iC = βiB at vCE = 0. Also, sketch the load line obtained for VCC = 10 V and RC = 1 kΩ. If the dc bias current into the base is 50 μA, write the equation for the corresponding iC−vCE curve. Also, write the equation for the load line, and solve the two equations to obtain VCE and IC. If the input signal causes a sinusoidal signal of 30-μA peak amplitude to be superimposed on IB, find the corre-sponding signal components of iC and vCE.
6.84 Consider the operation of the circuit shown in Fig.
P6.84 as vB rises slowly from zero. For this transistor, assume β = 50, vBE at which the transistor conducts is 0.5 V, vBE when fully conducting is 0.7 V, saturation begins at vBC = 0.4 V, and the transistor is deeply in saturation at vBC = 0.6V.
Sketch and label vE and vC versus vB. For what range of vB is iC essentially zero? What are the values of vE, iE, iC, and vC for vB = 1 V and 3 V? For what value of vB does saturation begin?
What is iB at this point? For vB = 4 V and 6 V, what are the values of vE, vC, iE, iC, and iB? Augment your sketch by adding a plot of iB.
iC vCE – iB 1 = β 100 = VCC 5 = RC 1 = Ω, iB VCE 1 2 --- VCC, = IC IB.
VBE 0.7 = RB 100 = Ω, VBB VBB RB RC VCC iC iB vCE Figure P6.82 6 V 1 k 1 k vB vE vC Figure P6.84 CHAPTER 6 P RO BL E MS 478 Chapter 6 Bipolar Junction Transistors (BJTs) Section 6.5: Small-Signal Operation and Models 6.85 Consider a transistor biased to operate in the active mode at a dc collector current IC. Calculate the collector sig-nal current as a fraction of IC (i.e., for input signals vbe of +1 mV, −1 mV, +2 mV, −2 mV, +5 mV, −5 mV, +8 mV, −8 mV, +10 mV, −10 mV, +12 mV, and −12 mV. In each case do the calculation two ways: (a) using the exponential characteristic, and (b) using the small-signal approximation. Present your results in the form of a table that includes a col-umn for the error introduced by the small-signal approxima-tion. Comment on the range of validity of the small-signal approximation.
6.86 An npn BJT with grounded emitter is operated with VBE = 0.700 V, at which the collector current is 0.5 mA. A 10-kΩ resistor connects the collector to a +10-V supply. What is the resulting collector voltage VC? Now, if a signal applied to the base raises vBE to 705 mV, find the resulting total collector current iC and total collector voltage vC using the exponential iC–vBE relationship. For this situation, what are vbe and vc? Cal-culate the voltage gain Compare with the value obtained using the small-signal approximation, that is, −gmRC.
6.87 A transistor with β = 120 is biased to operate at a dc collector current of 0.6 mA. Find the values of gm, rπ , and re.
Repeat for a bias current of 60 μA. 6.88 A pnp BJT is biased to operate at IC = 1.0 mA. What is the associated value of gm? If β = 100, what is the value of the small-signal resistance seen looking into the emitter (re)?
Into the base (rπ)? If the collector is connected to a 5-kΩ load, with a signal of 5-mV peak applied between base and emitter, what output signal voltage results?
D 6.89 A designer wishes to create a BJT amplifier with a gm of 25 mA/V and a base input resistance of 3000 Ω or more. What emitter-bias current should he choose? What is the minimum β he can tolerate for the transistor used? 6.90 A transistor operating with nominal gm of 50 mA/V has a β that ranges from 50 to 150. Also, the bias circuit, being less than ideal, allows a ±20% variation in IC. What are the extreme values found of the resistance looking into the base? 6.91 In the circuit of Fig. 6.36, VBE is adjusted so that VC = 1 V. If VCC = 3 V, RC = 2 kΩ, and a signal vbe = 0.005 sin ωt volts is applied, find expressions for the total instantaneous quantities iC (t), vC (t), and iB (t). The transistor has β = 80.
What is the voltage gain?
D 6.92 We wish to design the amplifier circuit of Fig. 6.36 under the constraint that VCC is fixed. Let the input signal vbe = sinωt, where is the maximum value for accept-able linearity. For the design that results in the largest signal at the collector, without the BJT leaving the active region, show that and find an expression for the voltage gain obtained. For VCC = 3 V and = 5 mV, find the dc voltage at the collector, the amplitude of the output voltage signal, and the voltage gain.
6.93 The table below summarizes some of the basic attributes of a number of BJTs of different types, operating as amplifiers under various conditions. Provide the missing entries. (Note: Isn’t it remarkable how much two parameters can reveal?) 6.94 A BJT is biased to operate in the active mode at a dc collector current of 0.5 mA. It has a β of 100. Give the four small-signal models (Figs. 6.40 and 6.41) of the BJT com-plete with the values of their parameters.
6.95 The transistor amplifier in Fig. P6.95 is biased with a current source I and has a very high β. Find the dc voltage at the collector, VC. Also, find the value of gm. Replace the transistor with the simplified hybrid-π model of Fig. 6.40(a) ic IC) ⁄ vc vbe ⁄ .
V ˆbe V ˆbe RCIC VCC 0.3 – V ˆbe – ( ) 1 V ˆbe VT ------+ ⎝ ⎠ ⎛ ⎞ = V ˆbe Transistor a b c d e f g α 1.000 0.90 β 100 ∞ IC (mA) 1.00 1.00 IE (mA) 1.00 5 IB (mA) 0.020 1.10 gm (mA/V) 700 re (Ω) 25 100 rπ (Ω) 10.1 kΩ Problems 479 CHAPTER 6 P RO BL E MS (note that the dc current source I should be replaced with an open circuit). Hence find the voltage gain 6.96 For the conceptual circuit shown in Fig. 6.39, RC = 3 kΩ, gm = 50 mA/V, and β = 100. If a peak-to-peak output voltage of 1 V is measured at the collector, what are the peak-to-peak values of vbe and ib?
6.97 Figure P6.97 shows the circuit of an amplifier fed with a signal source with a source resistance The bias circuitry is not shown. Replace the BJT with its hybrid- equivalent circuit of Fig. 6.40(a). Find the input resis-tance , the voltage transmission from source to amplifier input, and the voltage gain from base to collector, . Use these to show that the overall voltage gain is given by 6.98 Figure P6.98 shows a transistor with the collector con-nected to the base. The bias arrangement is not shown. Since a zero implies operation in the active mode, the BJT can be replaced by one of the small-signal models of Figs. 6.40 and 6.41. Use the model of Fig. 6.41(b) and show that the resulting two-terminal device, known as a diode connected transistor, has a small-signal resistance r equal to 6.99 Figure P6.99 shows a particular configuration of BJT amplifiers, known as “emitter follower.” The bias arrange-ment is not shown. Replace the BJT with its T equivalent-circuit model of Fig. 6.41(b). Show that 6.100 For the circuit shown in Fig. P6.100, draw a com-plete small-signal equivalent circuit utilizing an appropriate T model for the BJT (use α = 0.99). Your circuit should show the values of all components, including the model parameters. What is the input resistance Rin? Calculate the overall voltage gain 6.101 In the circuit shown in Fig. P6.101, the transistor has a β of 200. What is the dc voltage at the collector? Find the input resistances Rib and Rin and the overall voltage gain vc vi.
⁄ 8.2 k I 0.5 mA Figure P6.95 vsig Rsig.
π Rin vπ ib ⁄ ≡ vπ vsig ⁄ , vo vπ ⁄ vo vsig ⁄ vo vsig -------βRC rπ Rsig + -------------------– = v Rin vo ib RC vsig Rsig Figure P6.97 vBC re.
vx ix r = vx ix Figure P6.98 Rin vi ib ----β 1 + ( ) re Re + ( ) = ≡ vo vi ----Re Re re + ----------------= Re vi vo Rin ib Figure P6.99 vo vsig ⁄ ( ).
CHAPTER 6 P RO BL E MS 480 Chapter 6 Bipolar Junction Transistors (BJTs) For an output signal of ±0.4 V, what values of vsig and vb are required?
6.102 Consider the augmented hybrid-π model shown in Fig. 6.47(a). Disregarding how biasing is to be done, what is the largest possible voltage gain available for a signal source connected directly to the base and a very-high-resistance load? Calculate the value of the maximum possible gain for VA = 25 V and VA = 250 V.
6.103 Reconsider the amplifier shown in Fig. 6.42 and ana-lyzed in Example 6.14 under the condition that β is not well controlled. For what value of β does the circuit begin to satu-rate? We can conclude that large β is dangerous in this circuit.
Now, consider the effect of reduced β, say, to β = 25. What values of re, gm, and rπ result? What is the overall voltage gain?
(Note: You can see that this circuit, using base-current con-trol of bias, is very β-sensitive and usually not recommended.) 6.104 Reconsider the circuit shown in Fig. 6.44(a) under the condition that the signal source has an internal resistance of 100 Ω. What does the overall voltage gain become? What is the largest input signal voltage that can be used without output-signal clipping?
D 6.105 Redesign the circuit of Fig. 6.44 by raising the resistor values by a factor n to increase the resistance seen by the input vi to 75 Ω. What value of voltage gain results?
Grounded-base circuits of this kind are used in systems such as cable TV, in which, for highest-quality signaling, load resistances need to be “matched” to the equivalent resis-tances of the interconnecting cables.
D 6.106 Design an amplifier using the configuration of Fig. 6.44(a). The power supplies available are ±5 V. The input signal source has a resistance of 50 Ω, and it is required that the amplifier input resistance match this value.
(Note that Rin = re || RE re.) The amplifier is to have the greatest possible voltage gain and the largest possible output signal but retain small-signal linear operation (i.e., the signal component across the base–emitter junction should be lim-ited to no more than 10 mV). Find appropriate values for RE and RC. What is the value of voltage gain realized?
6.107 The transistor in the circuit shown in Fig. P6.107 is biased to operate in the active mode. Assuming that β is very large, find the collector bias current IC. Replace the transistor with the small-signal equivalent circuit model of Fig. 6.41(b) (remember to replace the dc power supply with a short circuit). Analyze the resulting amplifier equivalent cir-cuit to show that RL Rsig C1 Q1 C2 10 k 10 k 50 vsig vo 0.5 mA 9 V Rin Figure P6.100 vo vsig ⁄ ( ).
RC 100 1 k 10 k 10 mA Rin 5 V 1.5 V Rib Rsig vsig vb vo Figure P6.101 vo1 vi -------RE RE re + ----------------= 5 V 3.3 3.6 Figure P6.107 Problems 481 CHAPTER 6 P RO BL E MS Find the values of these voltage gains (for α 1). Now, if the terminal labeled vo1 is connected to ground, what does the voltage gain become?
Section 6.6: Basic BJT Amplifier Configurations 6.108 An amplifier with an input resistance of 100 k , an open-circuit voltage gain of 100 V/V, and an output resis-tance of 100 is connected between a 10-k signal source and a 1-k load. Find the overall voltage gain Also find the current gain, defined as the ratio of the load current to the current drawn from the signal source.
D 6.109 Specify the parameters and of an amplifier that is to be connected between a 100-k source and a 2-k load. The amplifier is required to meet the fol-lowing specifications: (a) No more than 10% of the signal strength is lost in the connection to the amplifier input.
(b) If the load resistance changes from the nominal value of 2 k to a low value of 1 k , the change in output voltage is limited to 10% of nominal value.
(c) The nominal overall voltage gain is 10 V/V.
6.110 Figure P6.110 shows an alternative equivalent circuit representation of an amplifier. If this circuit is to be equivalent to that in Fig. 6.50(b) show that Also con-vince yourself that the transconductance is defined as and hence is known as the short-circuit transconductance.
Now if the amplifier is fed with a signal source and is connected to a load resistance , show that the gain of the amplifier proper is given by and the overall voltage gain is given by 6.111 An alternative equivalent circuit of an amplifier fed with a signal source and connected to a load is shown in Fig. P6.111. Here is the open-circuit overall voltage gain, and is the output resistance with set to zero. This is different from Show that where .
Also show that the overall voltage gain 6.112 Most practical amplifiers have internal feedback that make them nonunilateral. In such a case, depends on To illustrate this point we show in Fig. P6.112 the equivalent circuit of an amplifier in which a feedback resis-tance models the internal feedback mechanism that is present in this amplifier. It is that makes the amplifier nonunilateral. Show that vo2 vi -------αR – C RE re + ----------------= vo2 vi ⁄ Problems 6.108 to 6.111 are identical to problems 5.80 to 5.84.
† † Ω Ω, Ω Ω Gv.
Rin, Avo, Ro Ω Ω Ω Ω Gm Avo Ro.
⁄ = Gm Gm io vi ----RL 0 = = vsig, Rsig ( ) RL Av Av Gm Ro RL || ( ) = Gv Gv Rin Rin Rsig + ---------------------- Gm Ro RL || ( ) = Rin vi Ro Gmvi vo io Figure P6.110 vsig, Rsig ( ) RL Gvo Gvo vo vsig -------RL ∞ = = Rout vsig Ro.
Gvo Ri Ri Rsig + -------------------- Avo = Ri Rin RL ∞ = = Gv Gvo RL RL Rout + ---------------------= Rsig Rout vsig Rin Gvovsig RL io vo vi Figure P6.111 Rin RL.
Rf Rf Rin R1 Rf R2 RL || ( ) + 1 gm R2 RL || ( ) + --------------------------------------|| = CHAPTER 6 P RO BL E MS 482 Chapter 6 Bipolar Junction Transistors (BJTs) Evaluate and for the case k M mA/V, and k Which of the amplifier characteristic parame-ters is most affected by (i.e., relative to the case with )? For k , determine the overall volt-age gain, with and without present.
6.113 A CE amplifier utilizes a BJT with and V, biased at mA; it has a collector resis-tance k Assume . Find and If the amplifier is fed with a signal source having a resis-tance of 10 k and a load resistance k is con-nected to the output terminal, find the resulting and . If the peak voltage of the sine wave appearing between base and emitter is to be limited to 5 mV, what is allowed, and what output voltage signal appears across the load?
D 6.114 In this problem we investigate the effect of the inevitable variability of on the realized gain of the CE amplifier. For this purpose, use the overall gain expression in Eq. (6.79). Assume is sufficiently large to be negligi-ble and thus show that where .
Consider the case k and k and let the BJT be biased at mA. The BJT has a nominal of 100. (a) What is the nominal value of ? (b) If can be anywhere between 50 and 150, what is the corresponding range of ?
(c) If in a particular design, it is required to maintain within % of its nominal value, what is the maximum allowable range of ?
(d) If it is not possible to restrict to the range found in (c), and the designer has to contend with in the range 50 to 150, what value of bias current would result in fall-ing in a range of % of a new nominal value? What is the nominal value of in this case?
D 6.115 In this problem, we investigate the effect of chang-ing the bias current on the overall voltage gain of a CE amplifier. Consider the situation of a CE amplifier oper-ating with a signal source having k and having k The BJT is specified to have and V. Use Eq. (6.79) to find at mA, 0.2 mA, 0.5 mA, 1.0 mA, and 1.25 mA. Observe the effect of on limiting as is increased. Find the value of that results in V/V. 6.116 Two identical CE amplifiers are connected in cas-cade. The first stage is fed with a source having a resis-tance k A load resistance k is connected to the collector of the second stage. Each BJT is biased at mA and has and a very large Each stage utilizes a collector resistance k (a) Sketch the equivalent circuit of the two-stage amplifier.
(b) Calculate the voltage transmission from the signal source to the input of the first stage.
(c) Calculate the voltage gain of the first stage, .
(d) Calculate the voltage gain of the second stage, (e) Find the overall voltage gain, 6.117 A CE amplifier utilizes a BJT with biased at mA and has a collector resistance k and a resistance connected in the emitter.
Find and If the amplifier is fed with a signal source having a resistance of 10 k , and a load resistance k is connected to the output terminal, find the resulting and If the peak voltage of the sine wave appearing between base and emitter is to be limited to 5 mV, what is allowed, and what output voltage signal appears across the load?
R1 Rf Ro Rsig vsig gmvi Rin R2 RL vo vi ii Figure P6.112 Avo gmR2 1 1 gmRf ⁄ ( ) – 1 R2 Rf ⁄ ( ) + --------------------------------– = Ro R2 Rf || = Rin, Avo, Ro R1 100 = Ω, Rf 1 = Ω, gm 100 = R2 100 = Ω, RL 1 = Ω.
Rf Rf ∞ = Rsig 100 = Ω Gv, Rf β 100 = VA 50 = IC 0.5 = RC 10 = Ω.
RB rπ Rin, Ro, Avo.
Ω, RL 10 = Ω Av Gv v ˆ sig β ro Gv R′ L Rsig β ⁄ ( ) 1 gm ⁄ ( ) + ---------------------------------------------R′ L RL RC || = RL ′ 10 = Ω Rsig 10 = Ω, IC 1 = β Gv β Gv Gv 20 ± β β β IC Gv 20 ± Gv IC Gv Rsig 10 = Ω RC RL 10 = || Ω.
β 100 = VA 25 = Gv IC 0.1 = ro Gv IC IC Gv 50 = vsig Rsig 10 = Ω.
RL 10 = Ω IC 0.25 = β 100 = VA.
RC 10 = Ω.
Av1 Av2.
vo2 vsig ⁄ .
β 100 = IC 0.5 = RC 10 = Ω Re 150 Ω = Rin, Avo, Ro.
Ω RL 10 = Ω Av Gv.
v ˆ sig Problems 483 CHAPTER 6 P RO BL E MS D 6.118 Design a CE amplifier with a resistance in the emitter to meet the following specifications: (i) Input resistance k (ii) When fed from a signal source with a peak amplitude of 0.1 V and a source resistance of 20 k , the peak amplitude of is 5 mV.
Specify and the bias current . The BJT has If the total resistance in the collector is 5 k , find the over-all voltage gain and the peak amplitude of the output signal D 6.119 Inclusion of an emitter resistance reduces the variability of the gain due to the inevitable wide variance in the value of . Consider a CE amplifier operating between a signal source with k and a total collector resistance of 10 k . The BJT is biased at mA and its is specified to be nominally 100 but can lie in the range of 50 to 150. First determine the nominal value and the range of without resistance Then select a value for that will ensure that be within % of its new nominal value. Specify the value of , the new nominal value of , and the expected range of D 6.120 A CB amplifier is operating with k k and At what current should the transistor be biased for the input resistance to equal that of the signal source? What is the resulting overall voltage gain? Assume .
6.121 For the circuit in Fig. P6.121, let and . Find 6.122 A CB amplifier is biased at mA with k and is driven by a signal source with k Find the overall voltage gain If the maximum signal amplitude of the voltage between base and emitter is limited to 10 mV, what are the corresponding amplitudes of and Assume .
D 6.123 An emitter follower is required to deliver a -V peak sinusoid to a -k load. If the peak amplitude of is to be limited to 5 mV, what is the lowest value of at which the BJT can be biased? At this bias current, what are the maximum and minimum currents that the BJT will be conducting (at the positive and negative peaks of the output sine wave)? If the resistance of the signal source is 200 k what value of is obtained? Thus determine the required amplitude of .
6.124 An emitter follower with a BJT biased at mA and having is connected between a source with k and a load k (a) Find and (b) If the signal amplitude across the base–emitter junction is to be limited to 10 mV, what is the corresponding ampli-tude of and (c) Find the open-circuit voltage gain and the output resistance Use these values first to verify the value of obtained in (a), then to find the value of obtained with reduced to 500 6.125 An emitter follower is operating at a collector bias current of 0.25 mA and is used to connect a -k source to a 1-k load. If the nominal value of is 100, what out-put resistance and overall voltage gain result? Now if transistor is specified to lie in the range 50 to 150, find the corresponding range of and 6.126 An emitter follower, when driven from a 10-k source, was found to have an output resistance of 200 . The output resistance increased to 300 when the source resistance was increased to 20 k . Find the overall voltage gain when the follower is driven by a 30-k source and loaded by a 1-k resistor.
6.127 For the general amplifier circuit shown in Fig.
P6.127 neglect the Early effect.
(a) Find expressions for and (b) If is disconnected from node X, node X is grounded, and node Y is disconnected from ground and connected to find the new expression for Section 6.7: Biasing in BJT Amplifier Circuits D 6.128 For the circuit in Fig. 6.59(a), neglect the base current IB in comparison with the current in the voltage divider. It is required to bias the transistor at IC = 1 mA, which requires selecting RB1 and RB2 so that VBE = 0.690 V. If VCC = 3 V, what must the ratio be? Now, if RB1 and Re Rin 20 = Ω.
Ω vπ Re IC β 100.
= Ω Gv vo.
Re Gv β Rsig 10 = Ω RC RL || Ω IC 1 = β Gv Re.
Re Gv 20 ± Re Gv Gv .
RL 10 = Ω, RC 10 = Ω, Rsig 100 = Ω.
IC Rin α 1 Rsig re α 1 vo.
vo RC isig Rsig Figure P6.121 IE 0.25 = RC RL = 10 = Ω Rsig 1 = Ω.
Gv.
vsig vo?
α1 0.5 2 Ω vbe IE Ω, Gv vsig IC 1 = β 100 = Rsig 20 = Ω RL 1 = Ω.
Rin, vb vsig ⁄ , vo vsig ⁄ .
vsig vo?
Gvo Rout.
Gv Gv RL Ω.
10 Ω Ω β Rout Gv β Rout Gv.
Ω Rout Ω Ω Ω Ω Ω vc vsig ⁄ ve vsig ⁄ .
vsig vsig, vc vsig ⁄ .
RB1 RB2 ⁄ CHAPTER 6 P RO BL E MS 484 Chapter 6 Bipolar Junction Transistors (BJTs) RB2 are 1% resistors, that is, each can be in the range of 0.99 to 1.01 of its nominal value, what is the range obtained for VBE? What is the corresponding range of IC? If RC = 2 kΩ, what is the range obtained for VCE? Comment on the efficacy of this biasing arrangement.
D 6.129 It is required to bias the transistor in the circuit of Fig. 6.59(b) at IC = 1 mA. The transistor β is specified to be nominally 100, but it can fall in the range of 50 to 150. For VCC = +3 V and RC = 2 kΩ, find the required value of RB to achieve IC = 1 mA for the “nominal” transistor. What is the expected range for IC and VCE? Comment on the efficacy of this bias design.
D 6.130 Consider the single-supply bias network shown in Fig. 6.60(a). Provide a design using a 9-V supply in which the supply voltage is equally split between RC, VCE, and RE with a collector current of 0.6 mA. The transistor β is specified to have a minimum value of 90. Use a voltage divider current of or slightly higher. Since a reason-able design should operate for the best transistors for which β is very high, do your initial design with β = ∞. Then choose suitable 5% resistors (see Appendix H), making the choice in a way that will result in a VBB that is slightly higher than the ideal value. Specify the values you have chosen for RE, RC, R1, and R2. Now, find VB, VE, VC, and IC for your final design using β = 90.
D 6.131 Repeat Problem 6.130, but use a voltage divider current that is Check your design at β = 90. If you have the data available, find how low β can be while the value of IC does not fall below that obtained with the design of Problem 6.130 for β = 90.
D 6.132 It is required to design the bias circuit of Fig. 6.60 for a BJT whose nominal β = 100.
(a) Find the largest ratio that will guarantee IE remain within ±10% of its nominal value for β as low as 50 and as high as 150.
(b) If the resistance ratio found in (a) is used, find an expression for the voltage that will result in a voltage drop of across RE.
(c) For VCC = 5 V, find the required values of R1, R2, and RE to obtain IE = 0.5 mA and to satisfy the requirement for sta-bility of IE in (a).
(d) Find RC so that VCE = 1.5 V for β equal to its nominal value. Check your design by evaluating the resulting range of IE.
D 6.133 Consider the two-supply bias arrangement shown in Fig. 6.61 using ±3-V supplies. It is required to design the circuit so that IC = 0.6 mA and VC is placed mid-way between VCC and VE.
(a) For β = ∞, what values of RE and RC are required?
(b) If the BJT is specified to have a minimum β of 90, find the largest value for RB consistent with the need to limit the voltage drop across it to one-tenth the voltage drop across RE.
(c) What standard 5% resistor values (see Appendix H) would you use for RB, RE, and RC? In making your selection, use somewhat lower values in order to compensate for the low-β effects.
(d) For the values you selected in (c), find IC, VB, VE, and VC for β = ∞ and for β = 90.
D 6.134 Utilizing ±3-V power supplies, it is required to design a version of the circuit in Fig. 6.61 in which the signal will be coupled to the emitter and thus RB can be set to zero.
Find values for RE and RC so that a dc emitter current of 0.5 mA is obtained and so that the gain is maximized while allowing ±1 V of signal swing at the collector. If temperature increases from the nominal value of 25°C to 125°C, estimate the percentage change in collector bias current. In addition to the −2 mV/°C change in VBE, assume that the transistor β changes over this temperature range from 50 to 150.
D 6.135 Using a 3-V power supply, design a version of the circuit of Fig. 6.62 to provide a dc emitter current of 0.5 mA and to allow a ±1-V signal swing at the collector.
The BJT has a nominal β = 100. Use standard 5% resistor values (see Appendix H). If the actual BJT used has β = 50, what emitter current is obtained? Also, what is the allowable signal swing at the collector? Repeat for β = 150.
D 6.136 (a) Using a 3-V power supply, design the feed-back bias circuit of Fig. 6.62 to provide IC = 3 mA and for β = 90.
(b) Select standard 5% resistor values, and reevaluate VC and IC for β = 90.
(c) Find VC and IC for β = ∞.
(d) To improve the situation that obtains when high-β tran-sistors are used, we have to arrange for an additional current to flow through RB. This can be achieved by connecting a resistor between base and emitter, as shown in Fig. P6.136.
Figure P6.127 vc ve ie ib RC RB RE Y X vsig ic IE 10 ⁄ , IE 2 ⁄ .
RB RE ⁄ ( ) VBB VCC R2 R1 R2 + ( ) ⁄ ≡ VCC 3 ⁄ VC VCC 2 ⁄ = Problems 485 CHAPTER 6 P RO BL E MS Design this circuit for β = 90. Use a current through RB2 equal to the base current. Now, what values of VC and IC result with β = ∞?
D 6.137 A circuit that can provide a very large voltage gain for a high-resistance load is shown in Fig. P6.137. Find the values of I and RB to bias the BJT at IC = 1 mA and VC = 1.5 V. Let β = 100.
6.138 The circuit in Fig. P6.138 provides a constant cur-rent IO as long as the circuit to which the collector is con-nected maintains the BJT in the active mode. Show that D 6.139 The current-source biasing circuit shown in Fig.
P6.139 provides a bias current to that is determined by the current source formed by , and The bias current is independent of and nearly independent of (as long as both and operate in the active mode). It is required to design the circuit using -V dc supplies to establish mA and V, in the ideal sit-uation of infinite and In designing the current source, use 2-V dc voltage drop across and impose the require-ment that remain within 5% of its ideal value for as low as 50. In selecting a value for ensure that for the low-est value of is 2.5 V. Use standard 5% resis-tor values (see Appendix H). What values for , and do you choose? What values of and result for 100, and 200?
RC VC VCC RB2 RB1 IC Figure P6.136 VC VCC RB IC I Figure P6.137 IO αVCC R2 R1 R2 + ( ) ⁄ [ ] VBE – RE R1||R2 ( ) β 1 + ( ) ⁄ + --------------------------------------------------------------= Figure P6.138 Q1 Q2, R1 R2, RE.
RB β1 Q1 Q2 5 ± IC1 0.1 = VCE1 1.5 = β1 β2.
RE IE2 β2 RB, β1 50, = VCE2 R1 R2, RE, RB, RC IC1 VCE1 β1 β2 50, = = RE RC RB R R Q2 Q1 R1 R 2 VCC V EE Figure P6.139 CHAPTER 6 P RO BL E MS 486 Chapter 6 Bipolar Junction Transistors (BJTs) D 6.140 For the circuit in Fig. P6.140, assuming all transistors to be identical with β infinite, derive an expression for the output current IO, and show that by select-ing and keeping the current in each junction the same, the cur-rent IO will be which is independent of VBE. What must the relationship of RE to R1 and R2 be? For VCC = 10 V and VBE = 0.7 V, design the circuit to obtain an output current of 0.5 mA. What is the lowest voltage that can be applied to the collector of Q3?
D 6.141 For the circuit in Fig. P6.141 find the value of R that will result in IO 1 mA. What is the largest voltage that can be applied to the collector? Assume = 0.7 V.
Section 6.8: Discrete-Circuit BJT Amplifiers 6.142 For the common-emitter amplifier shown in Fig. P6.142, let VCC = 15 V, R1 = 27 kΩ, R2 = 15 kΩ, RE = 2.4 kΩ, and RC = 3.9 kΩ. The transistor has β = 100. Calculate the dc bias current IC. If the amplifier operates between a source for which Rsig = 2 kΩ and a load of 2 kΩ, replace the transistor with its hybrid-π model, and find the values of Rin, and the overall voltage gain D 6.143 Using the topology of Fig. P6.142, design an amplifier to operate between a 2-kΩ source and a 2-kΩ load with a gain of −40 V/V. The power supply available is 15 V. Use an emitter current of approximately 2 mA and a current of about one-tenth of that in the voltage divider that feeds the base, with the dc voltage at the base about one-third of the supply. The transistor available has β = 100. Use standard 5% resistor (see Appendix H).
6.144 A designer, having examined the situation described in Problem 6.142 and estimating the available gain to be approximately −36.6 V/V, wants to explore the possibility of improvement by reducing the loading of the source by the amplifier input. As an experiment, the designer varies the resistance levels by a factor of approximately 3: R1 to 82 kΩ, R2 to 47 kΩ, RE to 7.2 kΩ, and RC to 12 kΩ (standard values of 5%-tolerance resistors). With VCC = 15 V, Rsig =2 kΩ, RL = 2 kΩ, and β = 100, what does the gain become? Comment.
D 6.145 Consider the CE amplifier circuit of Fig. 6.65(a).
It is required to design the circuit (i.e., find values for I, RB, and RC) to meet the following specifications: (a) Rin 5 kΩ.
R1 = R2 IO VCC 2RE ---------= Figure P6.140 VBE vo vsig ⁄ .
vo vsig ⁄ Figure P6.141 Rin Rsig vsig vo Figure P6.142 Problems 487 CHAPTER 6 P RO BL E MS (b) The dc voltage drop across RB is approximately 0.2 V.
(c) The open-circuit voltage gain from base to collector is the maximum possible, consistent with the requirement that the collector voltage never falls by more than approximately 0.4 V below the base voltage with the signal between base and emitter being as high as 5 mV.
Assume that vsig is a sinusoidal source, the available supply VCC = 3 V, and the transistor has β = 100. Use standard 5% resistance values, and specify the value of I to one signifi-cant digit. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 10 kΩ, what is the overall voltage gain?
D 6.146 In the circuit of Fig. P6.146, vsig is a small sine-wave signal with zero average. The transistor β is 100.
(a) Find the value of RE to establish a dc emitter current of about 0.5 mA.
(b) Find RC to establish a dc collector voltage of about +1 V.
(c) For RL = 10 kΩ, draw the small-signal equivalent circuit of the amplifier and determine its overall voltage gain.
6.147 The amplifier of Fig. P6.147 consists of two identical common-emitter amplifiers connected in cascade. Observe that the input resistance of the second stage, Rin2, constitutes the load resistance of the first stage.
(a) For VCC = 9 V, R1 = 100 kΩ, R2 = 47 kΩ, RE = 3.9 kΩ, RC = 6.8 kΩ, and β = 100, determine the dc collector current and dc collector voltage of each transistor.
(b) Draw the small-signal equivalent circuit of the entire amplifier and give the values of all its components.
(c) Find Rin1 and for Rsig = 5 kΩ.
(d) Find Rin2 and (e) For RL = 2 kΩ, find (f) Find the overall voltage gain 6.148 In the circuit of Fig. P6.148, vsig is a small sine-wave signal. Find Rin and the gain Assume β = 100. If the amplitude of the signal vbe is to be limited to 5 mV, what is the largest signal at the input? What is the cor-responding signal at the output?
6.149 The BJT in the circuit of Fig. P6.149 has β = 100.
(a) Find the dc collector current and the dc voltage at the collector.
in in Rsig vsig Figure P6.147 vb1 vsig ⁄ vb2 vb1 ⁄ .
Rsig 2.5 k vsig 5 V 5 V Figure P6.146 vo vb2 ⁄ .
vo vsig ⁄ .
vo vsig ⁄ .
CHAPTER 6 P RO BL E MS 488 Chapter 6 Bipolar Junction Transistors (BJTs) (b) Replacing the transistor by its T model, draw the small-signal equivalent circuit of the amplifier. Analyze the result-ing circuit to determine the voltage gain D 6.150 Consider the CB amplifier of Fig. 6.67(a) with the collector voltage signal coupled to a 1-kΩ load resis-tance through a large capacitor. Let the power supplies be ±3 V. The source has a resistance of 50 Ω. Design the circuit so that the amplifier input resistance is matched to that of the source and the output signal swing is as large as possible with relatively low distortion (vbe limited to 10 mV). Find I and RC and calculate the overall voltage gain obtained and the output signal swing. Assume α 1.
6.151 For the circuit in Fig. P6.151, find the input resis-tance Rin and the voltage gain Assume that the source provides a small signal vsig and that β = 100.
6.152 For the emitter-follower circuit shown in Fig. P6.152, the BJT used is specified to have β values in the range of 50 to 200 (a distressing situation for the circuit designer). For the two extreme values of β (β = 50 and β = 200), find: (a) IE, VE, and VB.
(b) the input resistance Rin.
(c) the voltage gain 6.153 For the emitter follower in Fig. P6.153, the signal source is directly coupled to the transistor base. If the dc component of vsig is zero, find the dc emitter current.
Assume β = 100. Neglecting ro, find Rin, the voltage gain the current gain and the output resistance Rout.
20 k 100 k vsig 0.2 mA Rin 20 k 20 k 125 5 Figure P6.148 1 mA 200 k 20 k 225 Figure P6.149 vo vi ⁄ .
vo vsig ⁄ .
Figure P6.151 vsig Rin 0.5 mA Rsig 75 2 k vo vsig ⁄ .
in vsig + 5 V Figure P6.152 vo vsig ⁄ , io ii ⁄ , Problems 489 CHAPTER 6 P RO BL E MS 6.154 For the circuit in Fig. P6.154, called a boot-strapped follower: (a) Find the dc emitter current and gm, re, and rπ. Use β = 100.
(b) Replace the BJT with its T model (neglecting ro), and analyze the circuit to determine the input resistance Rin and the voltage gain (c) Repeat (b) for the case when capacitor CB is open-cir-cuited. Compare the results with those obtained in (b) to find the advantages of bootstrapping.
6.155 For the follower circuit in Fig. P6.155, let transis-tor Q1 have β = 50 and transistor Q2 have β = 100, and neglect the effect of ro. Use VBE = 0.7 V.
(a) Find the dc emitter currents of Q1 and Q2. Also, find the dc voltages VB1 and VB2.
(b) If a load resistance RL = 1 kΩ is connected to the output terminal, find the voltage gain from the base to the emitter of Q2, and find the input resistance Rib2 looking into the base of Q2. (Hint: Consider Q2 as an emitter follower fed by a voltage vb2 at its base.) (c) Replacing Q2 with its input resistance Rib2 found in (b), analyze the circuit of emitter follower Q1 to determine its input resistance Rin, and the gain from its base to its emitter, (d) If the circuit is fed with a source having a 100-kΩ resis-tance, find the transmission to the base of Q1, (e) Find the overall voltage gain D 6.156 A CE amplifier has a midband voltage gain of V/V, a lower 3-dB frequency of Hz, and a higher 3-dB frequency MHz. In Chapter 9 we will learn that connecting a resistance in the emitter of the BJT results in lowering and raising by the fac-tor If the BJT is biased at mA, find that will result in at least equal to 5 MHz. What will the new values of and be?
Rin Rout vsig 2 Figure P6.153 vo vsig ⁄ .
Rin vsig Figure P6.154 vo vb2 ⁄ , ve1 vb1 ⁄ .
vb1 vsig ⁄ .
vo vsig ⁄ .
Rin 50 A 5 mA 5 Figure P6.155 AM 100 = fL 100 = fL 100 = Re fL fH 1 gmRe + ( ).
IC 1 = Re fH fL AM CHAPTER 7 Building Blocks of IC Amplifiers 492 CHAPTER 8 Differential and Multistage Amplifiers 586 CHAPTER 9 Frequency Response 686 CHAPTER 10 Feedback 802 CHAPTER 11 Output Stages and Power Amplifiers 910 CHAPTER 12 Operational-Amplifier Circuits 974 PART II Integrated-Circuit Amplifiers 491 aving studied the MOSFET and the BJT and become familiar with their basic circuit applications, we are now ready to consider their use in the design of practical am-plifier circuits that can be fabricated in integrated-circuit (IC) form. Part II is devoted to this rich subject. Its six chapters constitute a coherent treatment of IC amplifier design and can thus serve as a second course in electronic circuits.
Beginning with a brief introduction to the philosophy of IC design, Chapter 7 presents the basic circuit building blocks that are utilized in the design of IC amplifiers.
However, the most important building block of all, the differential pair configuration, is deferred to Chapter 8, where it is the main topic. Chapter 8 also considers the design of amplifiers that require a number of cascaded stages. As mentioned at various points in Part I, amplifiers have finite bandwidths. Chapter 9 is devoted to the frequency-response analysis of amplifiers; it provides a comprehensive study of the mechanisms that limit the bandwidth and the tools and methods that are utilized to estimate it for a wide variety of amplifier circuit configurations. While the study of the first half or so of Chapter 9 is essential, some of its later sections can be post-poned to a later point in the course or even to subsequent courses.
An essential tool in amplifier design is the judicious use of feedback. Chapter 10 deals with this exceedingly important subject. A thorough understanding of feedback concepts, insight into feedback configurations, and proficiency in the use of the feed-back analysis method are invaluable to the serious circuit designer.
In Chapter 11, we switch gears from dealing with primarily small-signal amplifiers to those that are required to handle large signals and large amounts of power. Finally, Chapter 12 brings together all the topics of Part II in an important application: namely, the design of operational amplifier circuits. We will then have come full circle, from con-sidering the op amp as a black box in Chapter 2 to understanding what is inside the box in Chapter 12.
Throughout Part II, MOSFET and BJT circuits are treated side-by-side. Because over 90% of ICs today employ the MOSFET, its circuits are presented first. Nevertheless, BJT circuits are presented with equal depth, although sometimes somewhat more briefly. In this regard, we draw the reader’s attention to Appendix 7.A, which presents a valuable compilation of the properties of both types of transistors, allowing interesting compari-sons to be made. As well, typical device parameter values are provided for a number of CMOS and bipolar fabrication process technologies.
H CHAPTER 7 Building Blocks of Integrated-Circuit Amplifiers Introduction 493 7.1 IC Design Philosophy 494 7.2 The Basic Gain Cell 495 7.3 The Cascode Amplifier 506 7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 526 7.5 Current-Mirror Circuits with Improved Performance 537 7.6 Some Useful Transistor Pairings 546 Summary 553 Appendix 7.A: Comparison of the MOSFET and the BJT 554 Problems 569 493 IN THIS CHAPTER YOU WILL LEARN 1. The basic integrated-circuit (IC) design philosophy and how it differs from that for discrete-circuit design.
2. The basic gain cells of IC amplifiers, namely, the CS and CE amplifiers with current-source loads.
3. How to increase the gain realized in the basic gain cells by employing the principle of cascoding.
4. Analysis and design of the cascode amplifier and the cascode current source in both their MOS and bipolar forms.
5. How current sources are used to bias IC amplifiers and how the refer-ence current generated in one location is replicated at various other locations on the IC chip by using current mirrors.
6. Some ingenious analog circuit design techniques that result in current mirrors with vastly improved characteristics.
7. How to pair transistors to realize amplifiers with characteristics superior to those obtained from a single-transistor stage.
Introduction Having studied the two major transistor types, the MOSFET and the BJT, and their basic discrete-circuit amplifier configurations, we are now ready to begin the study of integrated-circuit (IC) amplifiers. This chapter is devoted to the design of the basic building blocks of IC amplifiers.
We begin with a brief section on the design philosophy of integrated circuits and how it differs from that of discrete circuits. Throughout this chapter, MOS and bipolar circuits are presented side by side, which allows a certain economy in presentation and, more impor-tantly, provides an opportunity to compare and contrast the two circuit types. Toward that end, Appendix 7.A provides a comprehensive comparison of the attributes of the two tran-sistor types. This should serve both as a condensed review and as a guide to very interesting similarities and differences between the two devices. Appendix 7.A can be consulted at any time during the study of this or any of the remaining chapters of the book.
The heart of this chapter is the material in Sections 7.2 to 7.4. In Section 7.2 we present the basic gain cell of IC amplifiers, namely, the current-source-loaded common-source (common-emitter) amplifier. We then ask the question of how to increase its gain. This leads naturally and seamlessly to the principle of cascoding and its application in amplifier 494 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers design: namely, the cascode amplifier and the cascode current source, which are very impor-tant building blocks of IC amplifiers.
Section 7.4 is devoted to IC biasing and the study of another key IC building block, the current mirror. We study a collection of current-mirror circuits with improved performance in Section 7.5, for their significance and usefulness, but also because they embody ideas that illustrate the beauty and power of analog circuit design. The chapter concludes with the pre-sentation in Section 7.6 of an interesting and useful collection of amplifier configurations, each utilizing a pair of transistors.
7.1 IC Design Philosophy Integrated-circuit fabrication technology (Appendix A) imposes constraints on—and pro-vides opportunities to—the circuit designer. Thus, while chip-area considerations dictate that large- and even moderate-value resistors are to be avoided, constant-current sources are readily available. Large capacitors, such as those we used in Sections 5.8 and 6.8 for signal coupling and bypass, are not available to be used, except perhaps as components external to the IC chip. Even then, the number of such capacitors has to be kept to a minimum; other-wise the number of chip terminals increases, and hence the cost. Very small capacitors, in the picofarad and fraction-of-a-picofarad range, however, are easy to fabricate in IC MOS tech-nology and can be combined with MOS amplifiers and MOS switches to realize a wide range of signal processing functions, both analog (Chapter 16) and digital (Chapter 14).
As a general rule, in designing IC MOS circuits, one should strive to realize as many of the functions required as possible using MOS transistors only and, when needed, small MOS capacitors. MOS transistors can be sized; that is, their W and L values can be selected to fit a wide range of design requirements. Also, arrays of transistors can be matched (or, more generally, made to have desired size ratios) to realize such useful circuit building blocks as current mirrors.
At this juncture, it is useful to mention that to pack a larger number of devices on the same IC chip, the trend has been to reduce the device dimensions. By 2009, CMOS process technologies capable of producing devices with a 45-nm minimum channel length were in use. Such small devices need to operate with dc voltage supplies close to 1 V. While low-voltage operation can help to reduce power dissipation, it poses a host of challenges to the circuit designer. For instance, such MOS transistors must be operated with overdrive volt-ages of only 0.1 V to 0.2 V. In our study of MOS amplifiers, we will make frequent com-ments on such issues.
The MOS-amplifier circuits that we shall study will be designed almost entirely using MOSFETs of both polarities—that is, NMOS and PMOS—as are readily available in CMOS technology. As mentioned earlier, CMOS is currently the most widely used IC technology for both analog and digital as well as combined analog and digital (or mixed-signal) applica-tions. Nevertheless, bipolar integrated circuits still offer many exciting opportunities to the analog design engineer. This is especially the case for general-purpose circuit packages, such as high-quality op amps that are intended for assembly on printed-circuit (pc) boards (as opposed to being part of a system-on-chip). As well, bipolar circuits can provide much higher output currents and are favored for certain applications, such as in the automotive industry, for their high reliability under severe environmental conditions. Finally, bipolar circuits can be combined with CMOS in innovative and exciting ways in what is known as BiCMOS technology.
7.2 The Basic Gain Cell 495 7.2 The Basic Gain Cell 7.2.1 The CS and CE Amplifiers with Current-Source Loads The basic gain cell in an IC amplifier is a common-source (CS) or common-emitter (CE) tran-sistor loaded with a constant-current source, as shown in Fig. 7.1(a) and (b). These circuits are similar to the CS and CE amplifiers studied in Sections 5.6 and 6.6, except that here we have replaced the resistances and with constant-current sources. This is done for two reasons: First, as mentioned in Section 7.1, it is difficult in IC technology to implement resistances with reasonably precise values; rather, it is much easier to use current sources, which are implemented using transistors, as we shall see shortly. Second, by using a constant-current source we are in effect operating the CS and CE amplifiers with a very high (ideally infinite) load resistance; thus we can obtain a much higher gain than if a finite or is used. The circuits in Fig. 7.1(a) and (b) are said to be current-source loaded or active loaded.
Before we consider the small-signal analysis of the active-loaded CS and CE amplifiers, a word on their dc bias is in order. Obviously, in each circuit is biased at and But what determines the dc voltages at the drain (collector) and at the gate (base)? Usually, these gain cells will be part of larger circuits in which negative feedback is utilized to fix the values of and ( and ). We shall be discussing dc biasing later in this chapter. As well, in the next chapter we will begin to see complete IC amplifiers including biasing. For the time being, however, we shall assume that the MOS transistor in Fig. 7.1(a) is biased to operate in the saturation region and that the BJT in Fig. 7.1(b) is biased to operate in the active region. We will often refer to both the MOSFET and the BJT as operating in the “active region.” Figure 7.1 The basic gain cells of IC amplifiers: (a) current-source- or active-loaded common-source amplifier; (b) current-source- or active-loaded common-emitter amplifier; (c) small-signal equivalent circuit of (a); and (d) small-signal equivalent circuit of (b).
RD RC RD RC Q1 ID I = IC I.
= VDS VGS VCE VBE Q1 I vo VDD (a) vi Q1 I vo VCC (b) vi gmvgs ro vgs vi vo (c) gmv ro r vi v vo (d) 496 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Small-signal analysis of the current-source-loaded CS and CE amplifiers can be per-formed by utilizing their equivalent-circuit models, shown respectively in Fig. 7.1(c) and (d). Observe that since the current-source load is assumed to be ideal, it is represented in the models by an infinite resistance. Practical current sources will have finite output resistance, as we shall see shortly. For the time being, however, note that the CS and CE amplifiers of Fig. 7.1 are in effect operating in an open-circuit fashion. The only resistance between their output node and ground is the output resistance of the transistor itself, . Thus the voltage gain obtained in these circuits is the maximum possible for a CS or a CE amplifier.
From Fig. 7.1(c) we obtain for the active-loaded CS amplifier: (7.1) (7.2) (7.3) Similarly, from Fig. 7.1(d) we obtain for the active-loaded CE amplifier: (7.4) (7.5) (7.6) Thus both circuits realize a voltage gain of magnitude . Since this is the maximum gain obtainable in a CS or CE amplifier, we refer to it as the intrinsic gain and give it the symbol Furthermore, it is useful to examine the nature of in a little more detail.
7.2.2 The Intrinsic Gain For the BJT, we can derive a formula for the intrinsic gain by using the following formulas for and (7.7) (7.8) The result is (7.9) Thus is simply the ratio of the Early voltage , which is a technology-determined parameter, and the thermal voltage , which is a physical parameter (approximately 0.025 V at room temperature). The value of ranges from 5 V to 35 V for modern IC fabrication processes to 100 V to 130 V for the older, so-called high-voltage processes (see chapter appendix, Section 7.A.1). As a result, the value of will be in the range of 200 V/V to 5000 V/V, with the lower values characteristic of modern small-feature-size devices. It is important to note that for a given bipolar-transistor fabrication process, is independent of the transistor junction area and of its bias current. This is not the case for the MOSFET, as we shall now see.
Recall from our study of the MOSFET in Section 5.5, that there are three possible expressions for . Two of these are particularly useful for our purposes here: (7.10) r o Rin ∞ = Avo gmro – = Ro ro = Rin rπ = Avo gmro – = Ro ro = gmro A0.
A0 Avo gmro = gm ro: gm IC VT ------= ro VA IC ------= A0 gmro VA VT ------= = A0 VA VT VA A0 A0 gm gm gm ID VOV 2 ⁄ ----------------= 7.2 The Basic Gain Cell 497 (7.11) For the MOSFET we have (7.12) where is the Early voltage and is the technology-dependent component of the Early volt-age. Utilizing each of the expressions together with the expression for , we obtain for (7.13) which can be expressed in the alternate forms (7.14) and (7.15) The expression in Eq. (7.13) is the one most directly comparable to that of the BJT (Eq. 7.9).
Here, however, we note the following: 1. The quantity in the denominator is , which is a design parameter. Although the value of that designers use for modern submicron technologies has been steadily decreasing, it is still about 0.15 V to 0.3 V. Thus is 0.075 V to 0.15 V, which is 3 to 6 times higher than . Furthermore, there are reasons for selecting higher values for (to be discussed in later chapters).
2. The numerator quantity is both process dependent (through ) and device depen-dent (through L), and its value has been steadily decreasing with the scaling down of the technology (see Appendix 7.A). 3. From Eq. (7.14) we see that for a given technology (i.e., a given value of ) the intrinsic gain can be increased by using a longer MOSFET and operating it at a lower . As usual, however, there are design trade-offs. For instance, we will see in Chapter 9 that increasing L and lowering result, independently, in decreasing the amplifier bandwidth.
As a result, the intrinsic gain realized in a MOSFET fabricated in a modern short-channel technology is only 20 V/V to 40 V/V, an order of magnitude lower than that for a BJT.
The alternative expression for the MOSFET given in Eq. (7.15) reveals a very inter-esting fact: For a given process technology ( and ) and a given device (W and L), the intrinsic gain is inversely proportional to . This is illustrated in Fig. 7.2, which shows a typical plot for versus the bias current The plot confirms that the gain increases as the bias current is lowered. The gain, however, levels off at very low currents. This is because the MOSFET enters the subthreshold region of operation (Section 5.1.9), where it becomes very much like a BJT with an exponential current–voltage characteristic. The intrinsic gain then becomes constant, just like that of a BJT. Note, however, that although higher gain is obtained at lower values of the price paid is a lower (Eq. 7.11), and less ability to drive capacitive loads and thus a decrease in bandwidth. This point will be studied in Chapter 9.
gm 2μnCox W L ⁄ ( ) = ID ro ro VA ID ------V′ A L ID ----------= = V A V′ A gm r o A0, A0 VA VOV 2 ⁄ ----------------= A0 2V′ A L VOV -------------= A0 V′ A 2 μnCox ( ) WL ( ) ID ----------------------------------------------= V OV 2 ⁄ V OV V OV 2 ⁄ VT V OV V′ A V′ A A0 V OV V OV A0 V′ A μnCox ID A0 ID.
ID, gm 498 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Figure 7.2 The intrinsic gain of the MOSFET versus bias current ID. Outside the subthreshold region, this is a plot of for the case: L = 2 μm, and A0 (log scale) 1000 100 10 1 106 105 104 103 10 2 Slope 1 2 Strong inversion region Subthreshold region (A) ID (log scale) A0 V′ A 2μnCoxWL ID ⁄ = μnCox 20 μA V 2 ⁄ , = V′ A 20 V μm, ⁄ = W 20 μm.
= Example 7.1 We wish to compare the values of and for a CS amplifier that is designed using an NMOS transistor with L = 0.4 μm and W = 4 μm and fabricated in a 0.25-μm technology specified to have μA/V2 and V/μm, with those for a CE amplifier designed using a BJT fabricated in a process with and V. Assume that both devices are operating at a drain (collector) current of 100 μA.
Solution For simplicity, we shall neglect the Early effect in the MOSFET in determining ; thus, resulting in V mA/V V/V gm, Rin, Ro, A0 μnC ox 267 = V′ A 10 = β 100 = VA 10 = VOV ID 1 2 --- μnCox ( ) W L ------⎝ ⎠ ⎛ ⎞VOV 2 = 100 1 2 ---267 4 0.4 -------⎝ ⎠ ⎛ ⎞ × × VOV 2 = VOV 0.27 = gm 2ID VOV ---------2 0.1 × 0.27 ----------------0.74 = = = Rin ∞ = ro V′ A L ID ----------10 0.4 × 0.1 -------------------40 kΩ = = = Ro ro 40 kΩ = = A0 gmro 0.74 40 29.6 = × = = 7.2 The Basic Gain Cell 499 7.2.3 Effect of the Output Resistance of the Current-Source Load The current-source load of the CS amplifier in Fig. 7.1(a) can be implemented using a PMOS transistor biased in the saturation region to provide the required current I, as shown in Fig. 7.3(a). We can use the large-signal MOSFET model (Section 5.2, Fig. 5.15) to model as shown in Fig. 7.3(b), where (7.16) and (7.17) Thus the current-source load no longer has an infinite resistance; rather, it has a finite output resistance This resistance will in effect appear in parallel with , as shown in the amplifier equivalent-circuit model in Fig. 7.3(c), from which we obtain (7.18) Thus, not surprisingly, the finite output resistance of the current-source load reduces the magnitude of the voltage gain from to This reduction can be sub-stantial. For instance, if has an Early voltage equal to that of and the gain is reduced by half, For the CE amplifier we have mA/V V/V gm IC VT ------0.1 mA 0.025 V -------------------4 = = = Rin rπ β gm ------100 4 ---------25 kΩ = = = = ro VA IC ------10 0.1 -------100 kΩ = = = Ro ro 100 kΩ = = A0 gmro 4 100 400 = × = = 7.1 A CS amplifier utilizes an NMOS transistor with L = 0.36 μm and W/L = 10; it was fabricated in a 0.18-μm CMOS process for which μA/V2 and V/μm. Find the values of and obtained at μA, 100 μA, and 1 mA.
Ans. 0.28 mA/V, 50 V/V; 0.88 mA/V, 15.8 V/V; 2.78 mA/V, 5 V/V μnCox 387 = V′ A 5 = gm A0 ID 10 = EXERCISE Q2 I 1 2 --- μpCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 2 VDD VG – Vtp – [ ]2 = ro2 VA2 I -----------= ro2.
ro1 Av vo vi ----gm1 ro1 ro2 || ( ) – = ≡ gm1ro1 ( ) gm1 ro1 ro2 || ( ).
Q2 Q1, ro2 ro1 = 500 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers (7.18′) Finally, we note that a similar development can be used for the bipolar case.
Figure 7.3 (a) The CS amplifier with the current-source load implemented with a p-channel MOSFET Q2; (b) the circuit with Q2 replaced with its large-signal model; and (c) small-signal equivalent circuit of the amplifier.
VG Q2 vi Q1 vo VDD (a) I ro2 Q1 vo vi VDD (b) ro1 ro2 vi vgs1 gm1vgs1 vo (c) Av 1 2 --- gmro – = A practical circuit implementation of the common-source amplifier is shown in Fig. 7.4(a). Here the current-source transistor is the output transistor of a current mirror formed by and and fed with a reference current Current mirrors were briefly introduced in Section 5.7.4 and will be stud-ied more extensively in Sections 7.4 and 7.5. For the time being, assume that and are matched.
Also assume that is a stable, well-predicted current that is generated with a special circuit on the chip. To be able to clearly see the region of over which the circuit operates as an almost-linear ampli-fier, determine the voltage transfer characteristic (VTC), that is, versus Q2 Q2 Q3 IREF.
Q2 Q3 IREF vI vO vI.
Example 7.2 7.2 The Basic Gain Cell 501 Figure 7.4 Practical implementation of the common-source amplifier: (a) circuit; (b) i−v characteristic of the active-load Q2; (c) graphical construction to determine the transfer characteristic; (d) transfer characteristic.
(c) VDD VOV2 VOA VOV2 (b) VOB Vtn VOA VDD VOV2 502 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Example 7.2 continued Solution First we concern ourselves with the current mirror, with the objective of determining the char-acteristic of the current source Toward that end, we note that the current flows through the diode-connected transistor and thus determines of which is in turn applied between the source and the gate of Thus, the characteristic of the current source will be the characteristic curve of obtained for This is shown in Fig. 7.4(b), where we note that i will be equal to at one point only, namely, at this being the only point at which the two matched transistors and have identical operating conditions. We also observe the effect of channel-length modulation in (the Early effect), which is modeled by the finite output resistance Finally, note that operates as a current source when v is equal to or greater than . This in turn is obtained when . This is the maximum permitted value of the output voltage Now, with the characteristic of the current-source load in hand, we can proceed to determine versus Figure 7.4(c) shows a graphical construction for doing this. It is based on the graphical anal-ysis method employed in Section 5.4.5 except that here the load line is not a straight line but is the characteristic curve of shifted along the axis by volts and “flipped around.” The reason for this is that The term necessitates the shift, and the minus sign of v gives rise to the “flipping around” of the load curve.
The graphical construction of Fig. 7.4(c) can be used to determine for every value of , point by point: The value of determines the particular characteristic curve of on which the operating point lies. The operating point will be at the intersection of this particular graph and the load curve. The hori-zontal coordinate of the operating point then gives the value of Proceeding in the manner just explained, we obtain the VTC shown in Fig. 7.4(d). As indicated, it has four distinct segments, labeled I, II, III, and IV. Each segment is obtained for one of the four combi-nations of the modes of operation of and which are also indicated in the diagram. Note that we have labeled two important break points on the transfer characteristic (A and B) in correspondence with the intersection points (A and B) in Fig. 7.4(c). We urge the reader to carefully study the transfer charac-teristic and its various details.
Not surprisingly, segment III is the one of interest for amplifier operation. Observe that in region III the transfer curve is almost linear and is very steep, indicating large voltage gain. In region III both the amplifying transistor and the load transistor are operating in saturation. The end points of region III are A and B: At A, defined by , enters the triode region, and at B, defined by enters the triode region. When the amplifier is biased at a point in region III, the small-signal voltage gain can be determined as we have done in Fig. 7.3(c).
The question remains as to how we are going to guarantee that the dc component of will have such a value that will result in operation in region III. That is why overall negative feedback is needed, as will be demonstrated later.
Before leaving this example it is useful to reiterate that the upper limit of the amplifier region (i.e., point A) is defined by and the lower limit (i.e., point B) is defined by , where can be approximately determined by assuming that . A more precise value for can be obtained by taking into account the Early effect in both and as will be demonstrated in the next example.
i v – Q2.
IREF Q3 VSG Q3, Q2.
i v – Q2 iD vSD – Q2 vSG VSG.
= IREF vSD2 VSG, = Q2 Q3 Q2 ro2.
Q2 VOV2 VSG Vtp – = vO VDD VOV2 – ≤ vO.
i v – Q2 vO vI.
i v – Q2 vO VDD vO VDD v – = VDD vO vI vI Q1 vO.
Q1 Q2, Q1 Q2 vO VDD VOV2 – = Q2 vO vI Vtn, – = Q1 vI VOA VDD VOV2 – = VOB VOV1 = VOV1 ID1 IREF VOB Q1 Q2, 7.2 The Basic Gain Cell 503 Consider the CMOS common-source amplifier in Fig. 7.4(a) for the case , and For all transistors, L = 0.4 μm and W = 4 μm. Also, , , and Find the small-signal voltage gain. Also, find the coordi-nates of the extremities of the amplifier region of the transfer characteristic—that is, points A and B.
Solution Thus, Approximate values for the extremities of the amplifier region of the transfer characteristic (region III) can be determined as follows: Neglecting the Early effect, all three transistors are carrying equal currents and thus we can determine the overdrive voltages at which they are operating. Transistors and will have equal overdrive voltages, , determined from Substituting, μA, μA/V2, results in V Thus, V Next we determine from Substituting, μA, μA/V2, results in V Thus, V.
More precise values for and can be determined by taking the Early effect in all transistors into account as follows.
VDD 3 V, = Vtn = Vtp = 0.6 V μnCox = 200 μA / V2, μpCox = 65 μA /V2.
VAn = 20 V VAp =10 V IREF =100 μA.
gm1 2kn ′ W L -----⎝ ⎠ ⎛ ⎞ 1 IREF = 2 200 4 0.4 -------100 × × × = 0.63 mA/V = ro1 VAn ID1 --------20 V 0.1 mA ------------------200 kΩ = = = ro2 VAp ID2 -----------10 V 0.1 mA ------------------100 kΩ = = = Av gm1 ro1 ro2 || ( ) – = 0.63 mA/V ( ) 200 100 || ( ) × kΩ ( ) – = 42 V/V – = IREF, Q2 Q3 VOV3 ID3 IREF = 1 2 --- μpCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 3 VOV3 2 IREF 100 = μpCox 65 = W L ⁄ ( )3 4 0.4 10 = ⁄ = VOV3 0.55 = VOA VDD VOV3 2.45 = – = VOV1 ID1 IREF 1 2 --- μnCox ( ) W L ------⎝ ⎠ ⎛ ⎞ 1 VOV1 2 IREF 100 = μnCox 200 = W L ⁄ ( )1 4 0.4 10 = ⁄ = VOV1 0.32 = VOB VOV1 0.32 = = VOA VOB Example 7.3 504 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Example 7.3 continued First, we determine of Q2 and Q3 corresponding to 100 μA using Thus, (7.19) where is the magnitude of the overdrive voltage at which Q3 and Q2 are operating, and we have used the fact that, for Q3, . Equation (7.19) can be manipulated to the form which by a trial-and-error process yields Thus, and To find the corresponding value of we derive an expression for versus in region III.
Noting that in region III, Q1 and Q2 are in saturation and obviously conduct equal currents, we can write Substituting numerical values, we obtain which can be manipulated to the form (7.20) This is the equation of segment III of the transfer characteristic. Although it includes the reader should not be alarmed: Because region III is very narrow, changes very little, and the characteristic is nearly linear. Substituting gives the corresponding value of ; that is, To determine the coordinates of B, we note that they are related by Substituting in Eq. (7.20) and solving gives and The width of the amplifier region is therefore and the corresponding output range is Thus, the “large-signal” voltage gain is which is very close to the small-signal value of −42, indicating that segment III of the transfer character-istic is quite linear.
VSG ID3 IREF = = ID3 = 1 2 --- kp ′ W L -----⎝ ⎠ ⎛ ⎞ 3 VSG Vtp – ( )2 1 VSD VAp -----------+ ⎝ ⎠ ⎛ ⎞ 100 1 2 ---65 4 0.4 -------⎝ ⎠ ⎛ ⎞ × VOV3 2 1 0.6 VOV3 + 10 ----------------------------+ ⎝ ⎠ ⎛ ⎞ = VOV3 V SD = VSG 0.29 V OV3 2 1 0.09 + VOV3 ( ) = VOV3 0.53 V = VSG 0.6 0.53 + 1.13 V = = VOA = VDD − VOV3 = 2.47 V vI, VIA, vO vI iD1 iD2 = 1 2 --- kn ′ W L -----⎝ ⎠ ⎛ ⎞ 1 vI −Vtn ( )2 1 vO V An -----------+ ⎝ ⎠ ⎛ ⎞ = 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞ 2 VSG Vtp – ( )2 1 VDD vO – V Ap ---------------------+ ⎝ ⎠ ⎛ ⎞ 8.55 vI 0.6 – ( )2 1 0.08vO – 1 0.05vO + -------------------------- 1 0.13vO – ( ) = vO = 7.69 65.77 vI 0.6 – ( )2 – vI 2, vI vO 2.47 V = vI VIA = 0.88 V.
V OB = VIB Vtn.
– VIB 0.93 V = VOB 0.33 V.
= vI Δ = VIB VIA – 0.05 V = vO Δ = VOB VOA – 2.14 V – = vO Δ vI Δ --------- 2.14 0.05 ----------– 42.8 – V/V = = The Basic Gain Cell 505 7.2.4 Increasing the Gain of the Basic Cell We conclude this section by considering a question: How can we increase the voltage gain obtained from the basic gain cell? The answer lies in finding a way to raise the level of the output resistance of both the amplifying transistor and the load transistor. That is, we seek a circuit that passes the current provided by the amplifying transistor right through, but increases the resistance from to a much larger value. This requirement is illustrated in Fig. 7.5. Figure 7.5(a) shows the CS amplifying transistor together with its output equiv-alent circuit. Note that for the time being we are not showing the load device. In Fig. 7.5(b) we have inserted a shaded box between the drain of and a new output terminal labeled Here again we are not showing the load to which will be connected. Our “black box” takes in the output current of and passes it to the output; thus at its output we have the equivalent circuit shown, consisting of the same controlled source but with the output resistance increased by a factor K. Now, what does the black box really do? Since it passes the current but raises the resis-tance level, it is a current buffer. It is the dual of the voltage buffer (the source and emitter followers), which passes the voltage but lowers the resistance level.
Now searching our repertoire of transistor amplifier configurations studied in Sections 5.6 and 6.6, the only candidate for implementing this current-buffering action is the common-gate (or common-base in bipolar) amplifier. Indeed, recall that the CG and CB cir-cuits have a unity current gain. What we have not yet investigated, however, is their resis-tance transformation property. We shall do this in the next section.
Two important final comments: 1. It is not sufficient to raise the output resistance of the amplifying transistor only. We also need to raise the output resistance of the current-source load. Obviously, we can use a current buffer to do this also.
2. Placing a CG (or a CB) circuit on top of the CS (or CE) amplifying transistor to implement the current-buffering action is called cascoding. We will explain the ori-gin of this name shortly.
7.2 A CMOS common-source amplifier such as that in Fig. 7.4(a), fabricated in a 0.18-μm technology, has W/L = 7.2 μm/0.36 μm for all transistors, and Find , and the voltage gain.
Ans. 1.25 mA/V; 18 kΩ; 21.6 kΩ; −12.3 V/V 7.3 Consider the active-loaded CE amplifier when the constant-current source I is implemented with a pnp transistor. Let (for both the npn and the pnp transistors), and Find (for each transistor), and the amplifier voltage gain.
Ans. 25 kΩ; 0.5 MΩ; 4 mA/V; 2000 V/V; −1000 V/V kn ′ = 387 μA/V2, kp ′ = 86 μA/V2, I REF =100 μA, V′ An = 5 V/μm, V′Ap = 6 V/μm.
gm1, ro1 ro2, I = 0.1 mA, VA = 50 V β =100.
Rin, ro gm, A0, EXERCISES gmvi ro Q1 Q1 d2.
d2 Q1 gm1vi 506 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.3 The Cascode Amplifier 7.3.1 Cascoding Cascoding refers to the use of a transistor connected in the common-gate (or the common-base) configuration to provide current buffering for the output of a common-source (or a common-emitter) amplifying transistor. Figure 7.6 illustrates the technique for the MOS case. Here the CS transistor is the amplifying transistor and connected in the CG configuration with a dc bias voltage (signal ground) at its gate, is the cascode transis-tor.1 A similar arrangement applies for the bipolar case and will be considered later.
We will show in the following that the equivalent circuit at the output of the cascode amplifier is that shown in Fig. 7.6. Thus, the cascode transistor passes the current to the output node while raising the resistance level by a factor K. We will derive an expression for K.
Figure 7.5 To increase the voltage gain realized in the basic gain cell shown in (a), a functional block, shown as a black box in (b), is connected between d1 and the load. This new block is required to pass the cur-rent gm1vi right through but raise the resistance level by a factor K. The functional block is a current buffer.
1The name cascode is a carryover from the days of vacuum tubes and is a shortened version of “cascaded cathode”; in the tube version, the anode of the amplifying tube (corresponding to the drain of ) feeds the cathode of the cascode tube (corresponding to the source of ).
To Load ro1 Q1 vi d1 ro1 gm1vi d1 (a) To Load Out ro1 In Q1 vi d2 d1 Kro1 Kro1 gm1vi d2 (b) Q1 Q2, V G 2 Q1 Q2 gm1vi 7.3 The Cascode Amplifier 507 7.3.2 The MOS Cascode Figure 7.7(a) shows the MOS cascode amplifier without a load circuit and with the gate of connected to signal ground. Thus this circuit is for the purpose of small-signal calcula-tions only. Our objective is to determine the parameters and of the equivalent circuit shown in Fig. 7.7(b), which we shall use to represent the output of the cascode amplifier.
Toward that end, observe that if node of the equivalent circuit is short-circuited to ground, the current flowing through the short circuit will be equal to It follows that we can determine by short-circuiting (from a signal point of view) the output of the cas-code amplifier to ground, as shown in Fig. 7.7(c), determine and then Now, replacing and in the circuit of Fig. 7.7(c) with their small-signal models results in the circuit in Fig. 7.7(d), which we shall analyze to determine in terms of Observe that the voltage at the ( , ) node is equal to Writing a node equation for that node, we have Thus, Since (7.21) In other words, the current of the controlled source of is equal to that of the controlled source of Next, we write an equation for the node, Figure 7.6 The current-buffering action of Fig. 7.5(a) is implemented using a transistor Q2 connected in the CG configuration. Here VG2 is a dc bias voltage. The output equivalent circuit indicates that the CG tran-sistor passes the current gm1vi through but raises the resistance level by a factor K. Transistor Q2 is called a cascode transistor.
VG2 Q1 vi d2 Q2 To Load To Load Kro1 ro1 Kro1 gm1vi d2 Q2 Gm Ro d2 Gmvi.
Gm io, Gm io vi ----= Q1 Q2 io vi.
d1 s2 vgs2.
– gm2vgs2 vgs2 ro1 ---------vgs2 ro2 ---------gm1vi = + + gm2 1 ro1 ------1 ro2 ------+ + ⎝ ⎠ ⎛ ⎞vgs2 gm1vi = gm2 1 ro1 ⁄ ( ), 1 ro2 ⁄ , gm2vgs2 gm1vi Q2 Q1.
d2 io gm2vgs2 vgs2 ro2 ---------+ = gm2 1 ro2 ------+ ⎝ ⎠ ⎛ ⎞vgs2 = 508 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Figure 7.7 (a) A MOS cascode amplifier prepared for small-signal calculations; (b) output equivalent cir-cuit of the amplifier in (a); (c) the cascode amplifier with the output short-circuited to determine ; (d) equivalent circuit of the situation in (c).
Q1 vi d2 Q2 To Load (a) Ro Gmvi d2 (b) To Load Q1 vi g2 d1, s2 d2 io Q2 (c) gm1vi ro1 vgs1 vi d1, s2 vgs2 vgs2 vgs2 /ro1 gm2vgs2 ro2 ro2 d2 (d) g2 io Gm iovi ≡ 7.3 The Cascode Amplifier 509 Thus, Using Eq. (7.21) results in Thus, (7.22) which is the result we have anticipated.
Next we need to determine For this purpose we set to zero, which results in simply reduced to its output resistance which appears in the source circuit of as shown in Fig. 7.8(a). Now, replacing with its hybrid-π model and applying a test voltage to the output node results in the equivalent circuit shown in Fig. 7.8(b). The output resis-tance can be obtained as Analysis of the circuit is greatly simplified by noting that the current exiting the source node of is equal to . Thus, the voltage at the source node, which is can be expressed in terms of as (7.23) Next we express as the sum of the voltages across and as Substituting for from Eq. (7.23) results in Thus, is given by Figure 7.8 Determining the output resistance of the MOS cascode amplifier.
io gm2vgs2 io gm1vi = Gm io vi ----gm1 = = Ro.
vi Q1 ro1, Q2, Q2 vx Ro Ro vx ix ----≡ Q2 ix vgs2, – ix vgs2 ixro1 = – vx ro2 ro1 vx ix gm2vgs2 – ( ) = ro2 ixro1 + vgs2 vx ix ro1 ro2 gm2ro2ro1 + + ( ) = Ro vx ix ⁄ ≡ Q2 Ro ro1 (a) s2 Ro (b) vgs2 g2 vx gm2vgs2 ro2 ro1 ix ix 510 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers (7.24) In this expression the last term will dominate, thus (7.25) This expression has a simple and elegant interpretation: The CG transistor raises the out-put resistance of the amplifier by the factor which is its intrinsic gain. At the same time, the CG transistor simply passes the current to the output node. Thus the CG or cascode transistor very effectively realizes the objectives we set for the current buffer (refer to Figs. 7.5 and 7.6) with Voltage Gain If the cascode amplifier is loaded with an ideal constant-current source as shown in Fig. 7.9(a), the voltage gain realized can be found from the equivalent circuit in Fig. 7.9(b) as Thus, (7.26) For the case and , (7.27) Thus cascoding results in increasing the gain magnitude from to . Figure 7.9 (a) A MOS cascode amplifier with an ideal current-source load; (b) equivalent circuit representation of the cascode output.
Ro ro1 ro2 gm2ro2ro1 + + = Ro gm2ro2 ( )ro1 Q2 gm2ro2 ( ), gm1vi ( ) K A02 gm2ro2.
= = Avo vo vi ----gm1Ro – = = Avo gm1ro1 ( ) – = gm2ro2 ( ) gm1 gm2 gm = = ro1 ro2 ro = = Avo gmro ( )2 – = A0 2 – = A0 A0 2 VG2 Q1 vi Q2 Rin ∞ Ro (gm2ro2)ro1 vo I (a) (b) Ro vo gm1vi 7.3 The Cascode Amplifier 511 Cascoding can also be employed to raise the output resistance of the current-source load as shown in Fig. 7.10. Here is the current-source transistor, and is the CG cascode transis-tor. Voltages and are dc bias voltages. The cascode transistor multiplies the output resistance of by to provide an output resistance for the cascode current source of (7.28) Combining a cascode amplifier with a cascode current source results in the circuit of Fig.
7.11(a). The equivalent circuit at the output side is shown in Fig. 7.11(b), from which the Figure 7.10 Employing a cascode transistor Q3 to raise the output resistance of the current source Q4.
Figure 7.11 A cascode amplifier with a cascode current-source load.
VG4 Q4 VG3 Q3 ro4 VDD (gm3ro3)ro4 Q4 Q3 VG3 VG4 Q3 Q4, ro4 gm3ro3 ( ) Ro gm3ro3 ( )ro4 = VG4 Q4 VG3 Q3 VG2 Q2 Q1 ro4 ro1 VDD Rop (gm3ro3) ro4 Ron (gm2ro2) ro1 vo vi (a) (b) Ron Rop vo gm1 vi 512 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers voltage gain can be easily found as Thus, (7.29) For the case in which all transistors are identical, (7.30) By comparison to the gain expression in Eq. (7.18′), we see that using the cascode configu-ration for both the amplifying transistor and the current-source load transistor results in an increase in the magnitude of gain by a factor equal to Av vo vi ----gm1 Ron Rop || [ ] – = = Av gm1 gm2ro2 ( )ro1 [ ] gm3ro3 ( )ro4 [ ] || { } – = Av 1 2 --- gmro ( )2 1 2 ---A0 2 – = – = A0.
It is required to design the cascode current-source of Fig. 7.10 to provide a current of 100 μA and an out-put resistance of 500 k Assume the availability of a 0.18-μm CMOS technology for which V, V, μA/V2 and V/μm. Use V and determine L and W/L for each transistor, and the values of the bias voltages and Solution The output resistance is given by Assuming and are identical, Using V, we write Thus we require V Now, since L we need to use a channel length of μm which is about three times the minimum channel length. With V and V, V Ω.
VDD 1.8 = Vtp 0.5 – = μpCox 90 = V′ A 5 – = VOV 0.3 = VG3 VG4.
Ro Ro gm3ro3 ( )ro4 = Q3 Q4 Ro gmro ( )ro = VA VOV 2 ⁄ --------------------VA ID ---------× = VOV 0.3 = 500 kΩ VA 0.15 ----------VA 0.1 mA ------------------× = VA 2.74 = VA V′ A = L 2.74 5 ----------0.55 = = Vt 0.5 = VOV 0.3 = VSG4 0.5 0.3 0.8 = + = Example 7.4 7.3 The Cascode Amplifier 513 and thus, V To allow for the largest possible signal swing at the output terminal, we shall use the minimum required voltage across namely, or 0.3 V. Thus, V Since the two transistors are identical and are carrying equal currents, V Thus, We note that the maximum voltage allowed at the output terminal of the current source will be con-strained by the need to allow a minimum voltage of across thus, To determine the required W/L ratios of and we use which yields VG4 1.8 0.8 1.0 = – = Q4, VOV VD4 1.8 0.3 1.5 = – = VSG3 VSG4 0.8 = = VG3 1.5 0.8 + 0.7 V = – = VOV Q3; vD3max 1.5 0.3 + 1.2 V = – = Q3 Q4, ID 1 2 --- μpCox ( ) W L -----⎝ ⎠ ⎛ ⎞VOV 2 1 VSD VA ---------+ ⎝ ⎠ ⎛ ⎞ = 100 1 2 ---90 W L -----⎝ ⎠ ⎛ ⎞ × × 0.32 × 1 0.3 2.74 ----------+ ⎝ ⎠ ⎛ ⎞ = W L -----22.3 = D7.4 If in Example 7.4, L of each of and is halved while W/L is changed to allow and to remain unchanged, find the new values of and W/L. [Hint: In computing the required (W/L), note that has changed.] Ans. 125 k 20.3 7.5 Consider the cascode amplifier of Fig. 7.11 with the dc component at the input, V, V, V, V, and V. If all devices are matched (i.e., if ), and have equal of 0.5 V, what is the overdrive voltage at which the four transistors are operating? What is the allowable voltage range at the output?
Ans. 0.2 V; 0.5 V to 1.3 V 7.6 The cascode amplifier in Fig. 7.11 is operated at a current of 0.2 mA with all devices operating at V. All devices have V. Find , the output resistance of the amplifier, and the output resistance of the current source, Also find the overall output resistance and the voltage gain realized.
Ans. 2 mA/V; 200 k 200 k 100 k V/V Q3 Q4 ID VOV Ro VA Ω; VI 0.7 = VG2 1.0 = VG3 0.8 = VG4 1.1 = VDD 1.8 = kn1 kn2 kp3 kp4 = = = Vt VOV 0.2 = VA 2 = gm1 Ron, Rop.
Ω, Ω; Ω; 200 – EXERCISES 514 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.3.3 Distribution of Voltage Gain in a Cascode Amplifier It is often useful to know how much of the overall voltage gain of a cascode amplifier is real-ized in each of its two stages: the CS stage , and the CG stage For this purpose, con-sider the cascode amplifier shown in Fig. 7.12(a). Here, for generality we have included a load resistance which represents the output resistance of the current-source load plus any addi-tional resistance that may be connected to the output node. Recalling that the cascode amplifier output can be represented with the equivalent circuit of Fig. 7.7(b), where and , the voltage gain of the amplifier in Fig. 7.12(a) can be found as Thus, (7.31) The overall gain can be expressed as the product of the voltage gains of and as (7.32) To obtain we need to find the total resistance between the drain of and ground. Referring to Fig. 7.12(b) and denoting this resistance we can express as (7.33) Observe that is the parallel equivalent of and where is the input resistance of the CG transistor We shall now derive an expression2 for For this purpose, refer to the equivalent circuit of with its load resistance shown in Fig. 7.12(c). Observe that the voltage at the source of is thus can be found from where i is the current flowing into the source of Now this is the same current that flows out of the drain of and into Summing the currents at the source node, we see that the current through is We can now express the voltage at the source node, as the sum of the voltage drops across and to obtain which can be rearranged to obtain (7.34) This is a useful expression because it provides the input resistance of a CG amplifier loaded in a resistance . Since , we can simplify as follows: (7.35) 2The reader should not jump to the conclusion that is equal to ; this is the case when we neglect As will be seen very shortly, can be vastly different from Q1 Q2.
RL, Gm gm1 = Ro gm2ro2 ( )ro1 = Av Av gm1 Ro RL || ( ) – = Av gm1 gm2ro2ro1 RL || ( ) – = Av Q1 Q2 Av Av1Av2 vo1 vi -------⎝ ⎠ ⎛ ⎞ vo vo1 -------⎝ ⎠ ⎛ ⎞ = = Av1 vo1 v ⁄ i ≡ Q1 Rd1, Av1 Av1 vo1 vi -------gm1Rd1 – = = Rd1 ro1 Rin2, Rin2 Q2.
Rin2.
Rin2 1 gm2 ⁄ ro2.
Rin2 1 gm2 ⁄ .
Q2 RL, Q2 vgs2, – Rin2 Rin2 vgs2 – i ------------= Q2.
Q2 RL.
ro2 i gm2vgs2.
+ vgs2, – ro2 RL vgs2 i gm2vgs2 + ( )ro2 iRL + = – Rin2 vgs2 i ⁄ – ≡ Rin2 RL ro2 + 1 g + m2ro2 -------------------------= RL gm2ro2 1 Rin2 Rin2 RL gm2ro2 ---------------1 gm2 --------+ 7.3 The Cascode Amplifier 515 This is a very interesting result. First, it shows that if is infinite, as was assumed in our analysis of the discrete CG amplifier in Section 5.6.5, then reduces to verifying the result we found there. If cannot be neglected, as is always the case in IC amplifiers, we see that the input resistance depends on the value of in an interesting fashion: The load resistance is divided by the factor This is of course the “flip side” of the impedance transformation action of the CG. For emphasis and future reference, we illustrate the impedance transformation properties of the CG circuit in Fig. 7.13.
Figure 7.12 (a) The cascode amplifier with a load resistance RL. Only signal quantities are shown.
(b) Determining v01. (c) Determining Rin2.
Q1 vi d1 Q2 RL vo (gm2 ro2)ro1 Rin2 vo1 ro1 (a) ro2 RL gm2 vgs2 vgs2 g2 d2 d1, s2 i i vgs2 i Rin2 (c) ro1 Rin2 Rd1 vi gm1vi g1 vo1 d1 (b) ro2 Rin2 1 gm2, ⁄ ro2 RL RL gm2ro2 ( ).
516 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Going back to the cascode amplifier in Fig. 7.12(a), having found the value of we can now obtain as (7.36) and as (7.37) Finally, we can obtain by dividing the total gain given by Eq. (7.31) by . To pro-vide insight into the effect of the value of on the overall gain of the cascode as well as on how this gain is distributed among the two stages of the cascode amplifier, we provide in Table 7.1 approximate values for the case and for four different values of (1) obtained with an ideal current-source load; (2) obtained with a cascode current-source load; (3) obtained with a simple current-source load; and (4) for completeness, that is, a signal short circuit at the output.
Figure 7.13 The impedance-transformation properties of the common-gate amplifier. Depending on the values of Rs and RL, we can sometimes write Rin RL/(gmro) and Ro (gmro)Rs. However, such approxima-tions are not always justified.
Table 7.1 Gain Distribution in the MOS Cascode Amplifier for Various Values of RL Case 1 2 3 4 0 0 0 RL Rs Ro ro Rs gm roRs ro (1 gm ro)Rs 1 gm ro 1 gm ro RL RL (1 gm ro) Rin Rin2 Rd1 Rd1 ro1 Rin2 || = Av1 Av1 gm1Rd1 gm1 ro1 Rin2 || ( ) – = – = Av2 Av Av1 RL ro1 ro2 ro = = RL: RL ∞, = RL gmro ( )ro, = RL ro, = RL 0, = RL Rin2 Rd1 Av1 Av2 Av ∞ ∞ ro gmro – gmro gmro ( )2 – gmro ( )ro ro ro 2 ⁄ 1 2 --- gmro ( ) – gmro 1 2 --- gmro ( )2 – ro 2 gm ------2 gm ------2 – 1 2 --- gmro ( ) gmro ( ) – 1 gm ------1 gm ------1 – 7.3 The Cascode Amplifier 517 Observe that while case 1 represents an idealized situation, it is useful in that it provides the theoretical maximum voltage gain achievable in a MOS cascode amplifier. Case 2, which assumes a cascode current-source load with an output resistance equal to that of the cascode amplifier, provides a realistic estimate of the gain achieved if one aims to maximize the realized gain. In certain situations, however, that is not our objective. This point is important, for as we shall see in Chapter 9, there is an entirely different application of the cascode amplifier: namely, to obtain wideband amplification by extending the upper 3-dB frequency As will be seen, for such an application one opts for the situation represented by case 3, where the gain achieved in the CS amplifier is only V/V, and of course the overall gain is now only However, as will be seen in Chapter 9, this trade-off of the overall gain to obtain extended bandwidth is in some cases a good bargain!
7.3.4 The Output Resistance of a Source-Degenerated CS Amplifier In Section 5.6.4 we discussed some of the benefits that are obtained when a resistance is included in the source lead of a CS amplifier, as in Fig. 7.14(a). Such a resistance is referred to as a source-degeneration resistance because of its action in reducing the effective transconduc-tance of the CS stage to that is, by a factor This also is the factor by which we increase a number of performance parameters such as linearity and bandwidth (as will be seen in Chapter 9). At this juncture we simply wish to point out that the expression we derived for the output resistance of the cascode amplifier applies directly to the case of a source-degenerated CS amplifier. This is because when we determine we ground the input terminal, making transistor Q appear as a CG transistor. Thus is given by (7.38) Since , the first term on the right-hand side will be much lower than the third and can be neglected, resulting in (7.39) Thus source degeneration increases the output resistance of the CS amplifier from to again by the same factor In Chapter 10, we will find that introduces negative (degenerative) feedback of an amount .
fH.
2 – gmro ( ).
– 7.7 The common-gate transistor in Fig. 7.13 is biased at a drain current of 0.25 mA and is operating with an overdrive voltage V. The transistor has an Early voltage of 5 V.
(a) Find for 1 MΩ, 100 kΩ, 20 kΩ, and 0.
(b) Find for , 1 kΩ, 10 kΩ, 20 kΩ, and 100 kΩ.
Ans. (a) , 25.5 kΩ, 3 kΩ, 1 kΩ, 0.5 kΩ; (b) 20 kΩ, 61 kΩ, 430 kΩ, 840 kΩ, 4.12 MΩ 7.8 Consider a cascode amplifier for which the CS and CG transistors are identical and are biased to operate at mA with V. Also let V. Find , and for two cases: (a) kΩ and (b) kΩ.
Ans. (a) –1.82 V/V, 10.5 V/V, –19.0 V/V; (b) –10.2 V/V, 19.6 V/V, –200 V/V VOV 0.25 = V A Rin RL ∞, = Ro Rs 0 = ∞ ID 0.1 = VOV 0.2 = VA 2 = Av1 Av2, Av RL 20 = RL 400 = EXERCISES Rs gm 1 gmRs + ( ), ⁄ 1 gmRs + ( ).
Ro, Ro Ro Rs ro gmroRs + + = gmro 1 Ro 1 gmRs + ( )ro ro 1 gmRs + ( )ro, 1 gmRs + ( ).
Rs 1 gmRs + ( ) 518 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.3.5 Double Cascoding If a still higher output resistance and correspondingly higher gain are required, it is possible to add another level of cascoding, as illustrated in Fig. 7.15. Observe that is the second cascode transistor, and it raises the output resistance by For the case of identical transistors, the output resistance will be and the voltage gain, assuming an ideal current-source load, will be Of course, we have to generate another dc bias voltage for the second cascode transistor, .
A drawback of double cascoding is that an additional transistor is now stacked between the power-supply rails. Furthermore, to realize the advantage of double cascoding, the cur-rent-source load will also need to use double cascoding with an additional transistor. Since for proper operation each transistor needs a certain minimum (at least equal to ), and recalling that modern MOS technology utilizes power supplies in the range of 1 V to 2 V, we see that there is a limit on the number of transistors in a cascode stack.
Figure 7.14 The output resistance expression of the cascode can be used to find the output resistance of a source-degenerated common-source amplifier. Here, a useful interpretation of the result is that Rs increases the output resistance by the factor (1 + gmRs).
Q Rs vi Ro Rs ro gm ro Rs (1 gm Rs ) ro Ro 7.9 Given that source degeneration reduces the transconductance of a CS amplifier from to approx-imately and increases its output resistance by approximately the same factor, what happens to the open-circuit voltage gain ? Now, find an expression for when a load resist-ance is connected to the output.
Ans. remains constant at (7.40) gm gm 1 gmRs + ( ) ⁄ Avo Av RL Avo gmro: Av gmro ( ) RL RL 1 gmRs + ( )ro + -------------------------------------------= EXERCISE Q3 gm3ro3 ( ).
gmro ( )2ro gmro ( )3 or A0 3.
Q3 vDS VOV 7.3 The Cascode Amplifier 519 7.3.6 The Folded Cascode To avoid the problem of stacking a large number of transistors across a low-voltage power sup-ply, one can use a PMOS transistor for the cascode device, as shown in Fig. 7.16. Here, as before, the NMOS transistor Q1 is operating in the CS configuration, but the CG stage is imple-mented using the PMOS transistor Q2. An additional current source is needed to bias Q2 and provide it with its active load. Note that Q1 is now operating at a bias current of .
Finally, a dc voltage VG2 is needed to provide an appropriate dc level for the gate of the cascode transistor Q2. Its value has to be selected so that Q2 and Q1 operate in the saturation region.
Figure 7.15 Double cascoding.
Q3 Q2 VG3 VG2 Q1 vi ro1 (gm2ro2)ro1 (gm3ro3)(gm2ro2)ro1 A2 0 ro vo VDD I I2 I1 I2 – ( ) VG2 I2 VDD I1 Q1 Q2 vi gmvi vo Figure 7.16 The folded cascode.
520 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers The small-signal operation of the circuit in Fig. 7.16 is similar to that of the NMOS cas-code. The difference here is that the signal current is folded down and made to flow into the source terminal of which gives the circuit the name folded cascode.3 The folded cascode is a very popular building block in CMOS amplifiers.
7.3.7 The BJT Cascode Figure 7.17(a) shows the BJT cascode amplifier with an ideal current-source load. Voltage is a dc bias voltage for the CB cascode transistor The circuit is very similar to the MOS cascode, and the small-signal analysis will follow in a parallel fashion. Our objective then is to determine the parameters and of the equivalent circuit of Fig. 7.17(b), which we shall use to represent the output of the cascode amplifier formed by and As in the case of the MOS cascode, is the short-circuit transconductance and can be determined from the circuit in Fig. 7.17(c). Here we show the cascode amplifier prepared for small-signal analysis with the output short-circuited to ground. The transconductance can be determined as Replacing and with their hybrid- equivalent-circuit models gives rise to the circuit in Fig. 7.17(d). Analysis of this circuit is straightforward and proceeds as follows: The volt-age at the node is seen to be Thus we can write a node equation for as 3The circuit itself can be thought of as having been folded. In this same vein, the regular cascode is sometimes referred to as a telescopic cascode because the stacking of transistors resembles the extension of a telescope.
gmvi Q2, 7.10 Consider the folded-cascode amplifier of Fig. 7.16 for the following case: , and To operate and at equal bias currents I, and . While current source is implemented using the simple circuit studied in Section 7.2, current source is realized using a cascoded circuit (i.e., the NMOS version of the circuit in Fig.
7.10). The transistor W/L ratios are selected so that each operates at an overdrive voltage of 0.2 V. (a) What must the relationship of to be?
(b) What is the minimum dc voltage required across current source for proper operation? Now, if a 0.1-V peak-to-peak signal swing is to be allowed at the drain of , what is the highest dc bias voltage that can be used at that node?
(c) What is the value of of , and hence what is the largest value to which can be set?
(d) What is the minimum dc voltage required across current-source for proper operation? (e) Given the results of (c) and (d), what is the allowable range of signal swing at the output?
Ans. (a) ; (b) 0.2 V, 1.55 V; (c) 0.7 V, 0.85 V; (d) 0.4 V; (e) 0.4 V to 1.35 V V DD 1.8 V = kp ′ 1 4 ⁄ kn ′, = Vtn = Vtp 0.5 V.
= – Q1 Q2 I1 2I = I2 I = I1 I2 (W/L)2 (W/L)1 I1 Q1 V SG Q2 VG2 I2 (W/L)2 = 4 (W/L)1 EXERCISE VB2 Q2.
Gm Ro Q1 Q2.
Gm Gm Gm io vi ----= Q1 Q2 π c1, e2 ( ) vπ2.
– c1, e2 ( ) gm2vπ2 vπ2 ro1 -------vπ2 ro2 -------vπ2 rπ2 -------gm1vi = + + + 7.3 The Cascode Amplifier 521 Since , and we can neglect all the terms beyond the first on the left-hand side to obtain (7.41) Next, we write a node equation at and again neglect the second term on the right-hand side to obtain Using Eq. (7.41) results in Figure 7.17 (a) A BJT cascode amplifier with an ideal current-source load; (b) small-signal equivalent-circuit representation of the output of the cascode amplifier; (c) the cascode amplifier with the output short-circuited to ground, and (d) equivalent circuit representation of (c).
VB2 Q1 vi Q2 c2 Rin r 1 vo I (a) (b) Ro c2 Gm vi b2 Q1 vi io Q2 c2 c1, e2 (c) ro1 gm1vi ro2 r 2 ro2 gm2v2 v 2 r 1 v 2 ro1 v 2 b2 r 2 v 2 io c1, e2 c2 (d) v 1 vi gm2 1 rπ2 ⁄ ( ) 1 ro1 ⁄ 1 ro2 ⁄ , gm2vπ2 gm1vi c2, io gm2vπ2 vπ2 ro2 -------+ = io gm2vπ2 io gm1vi = 522 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Thus, which is the result we have anticipated and is identical to that for the MOS case. To obtain we set which results in being reduced to its output resistance , which appears in the emitter lead of as shown in Fig. 7.18(a). Here we have applied a test voltage and will determine as Replacing with its hybrid-π model results in the circuit of Fig. 7.18(b). Before embark-ing on the analysis, it is very useful to observe first that the current flowing into the emitter node must be equal to Second, note that and appear in parallel. Thus the voltage at the emitter node, can be found as (7.42) Next we write a loop equation around the loop as Substituting for from Eq. (7.42) and collecting terms, we find as (7.43) Figure 7.18 Determining the output resistant Ro of the BJT cascode amplifier.
Gm gm1 = Ro, vi 0, = Q1 ro1 Q2 vx Ro Ro vx ix ----= Q2 ix.
ro1 rπ2 vπ2, – vπ2 ix ro1 rπ2 || ( ) = – c2 e2 – ground – vx ix gm2vπ2 – ( )ro2 ix ro1 rπ2 || ( ) + = vπ2 Ro vx ix ⁄ = Ro ro2 ro1 rπ2 || ( ) gm2ro2 ( ) ro1 rπ2 || ( ) + + = Q2 ro1 Ro vxix (a) ix vx Ro c2 e2 ro1 ro2 (b) vx r 2 ix ix gm2v2 v 2 7.3 The Cascode Amplifier 523 which can be written as (7.44) Since , we can neglect the first term on the right-hand side of Eq. (7.44), (7.45) This result is similar but certainly not identical to that for the MOS cascode. Here, because of the finite of the BJT, we have appearing in parallel with This poses a very sig-nificant constraint on of the BJT cascode. Specifically, because will always be lower than it follows that the maximum possible value of is (7.46) Thus the maximum output resistance realizable by cascoding is This means that unlike the MOS case, double cascoding with a BJT would not be useful.
Having determined and we can now find the open-circuit voltage gain of the bipolar cascode as Thus, (7.47) For the case (7.48) which will be less than in magnitude. In fact, the maximum possible gain magni-tude is obtained when and is given by (7.49) Finally, we note that to be able to realize gains approaching this level, the current-source load must also be cascoded. Figure 7.19 shows a cascode BJT amplifier with a cascode current-source load.
Ro ro2 gm2ro2 1 + ( ) ro1 rπ2 || ( ) + = ro2 gm2ro2 ( ) ro1 rπ2 || ( ) + gm2 ro1 rπ2 || ( ) 1 Ro gm2ro2 ( ) ro1 rπ2 || ( ) β rπ2 ro1.
Ro ro1 rπ2 || ( ) rπ2, Ro Ro max gm2ro2rπ2 = gm2rπ2 ( )ro2 β2ro2 = = β2ro2.
Gm Ro, Avo vo vi ----GmRo – = = Avo gm1 gm2ro2 ( ) ro1 rπ2 || ( ) – = gm1 gm2, = ro1 ro2, = Avo gmro ( ) gm ro rπ || ( ) [ ] – = gmro ( )2 ro rπ Avo max βgmro βA0 = = 7.11 Find an expression for the maximum voltage gain achieved in the amplifier of Fig. 7.19.
Ans.
7.12 Consider the BJT cascode amplifier of Fig. 7.19 when biased at a current of 0.2 mA. Assuming that npn transistors have and V and that pnp transistors have and V, find and Also use the result of Exercise 7.11 to determine the maximum achievable gain.
Ans. 1.67 M 0.762 M V/V; V/V Avmax gm1 β2ro2 β3ro3 || ( ) = β 100 = VA 5 = β 50 = VA 4 = Ron, Rop, Av.
Ω; Ω; 4186 – 5714 – EXERCISES 524 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.3.8 The Output Resistance of an Emitter-Degenerated CE Amplifier As we have done in the MOS case, we shall adapt the expression for derived for the BJT cascode (Eq. 7.43) for the case of a CE amplifier with a resistance connected in its emit-ter, as shown in Fig. 7.20(a). The output resistance is obtained from Eq. (7.43) by replacing with by by , and by (7.50) Since , we can neglect the second term relative to the third; thus, That is, (7.51) Thus, emitter degeneration multiplies the transistor output resistance by the factor .
Finally, for completeness and future reference we show in Fig. 7.20(b) the BJT equiva-lent of Fig. 7.13. Here both and of a grounded-base BJT are shown. Note that we have not provided the derivation of Figure 7.19 A BJT cascode amplifier with a cascode current source.
VB4 Q4 VB3 Q3 VB2 Q2 Q1 Av gm1(Ron||Rop) VCC Rop (gm3ro3)(ro4||r 3) Ron (gm2ro2)(ro1||r 2) Rin r1 vo vi Ro Re ro2 ro, gm2 gm, rπ2 rπ ro1 Re: Ro ro Re rπ || ( ) gmro ( ) Re rπ || ( ) + + = gmro 1 Ro ro gmro Re rπ || ( ) + Ro 1 gm Re rπ || ( ) + [ ]ro = ro 1 gm Re rπ || ( ) + [ ] Rin Ro Rin.
7.3 The Cascode Amplifier 525 7.3.9 BiCMOS Cascodes Certain advanced CMOS technologies allow the fabrication of bipolar transistors, thus per-mitting the circuit designer to combine MOS and bipolar transistors in circuits that take advantage of the unique features of each. The resulting technology is called BiCMOS, and the circuits are referred to as BiCMOS circuits.
Figure 7.20 (a) Output resistance of a CE amplifier with emitter degeneration; (b) The impedance trans-formation properties of the CB amplifier. Note that for , these formulas reduce to those for the MOSFET case (Fig. 7.13).
Ro ro (Re||r ) gm ro(Re||r ) ro [1 gm(Re||r)] Re vi (a) Ro ro (Re||r ) gm ro(Re||r ) Rin ro (1 gmro)(Re||r ) re Re RL (b) ro RL gmro 1 1 RL r RL 1 gmro , for RL bro β ∞ = 7.13 Find the output resistance of a CE amplifier biased at mA and having a resistance of 500 connected in its emitter. Let and V. What is the value of the output resistance without degeneration.?
Ans. 177 k 10 k IC 1 = Ω β 100 = VA 10 = Ω; Ω EXERCISE 526 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Figure 7.21 shows two possible BiCMOS cascode amplifiers. The circuit in Fig. 7.21(a) uses a MOS transistor for the amplifying device and a BJT for the cascode device. This cir-cuit has the advantage of an infinite input resistance compared with an input resistance of obtained in the all-bipolar case. As well, the use of a bipolar transistor for the cascode stage can result in an increased output resistance as compared to the all-MOS case [because of the bipolar transistor is usually higher than of the MOSFET].
The circuit of Fig. 7.21(b) uses a MOS transistor to implement double cascoding.
Recall that double cascoding is not possible with BJT circuits alone.
7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits Biasing in integrated-circuit design is based on the use of constant-current sources. On an IC chip with a number of amplifier stages, a constant dc current (called a reference current) is generated at one location and is then replicated at various other locations for biasing the Figure 7.21 BiCMOS cascodes.
(a) VB2 Q1 vi vo VDD I Q2 (b) Q3 VG3 vo I VB2 Q2 vi Q1 rπ, β gmro ( ) Q3 7.14 For I = 100 μA, find , , and of the BiCMOS amplifiers in Fig. 7.21. Let (for both MOS and bipolar transistors), μA/V2, and W/L = 25.
Ans. (a) 1 mA/V, 3.33 M V/V; (b) 4 mA/V, 167 M V/V Gm Ro Avo VA 5 V = β 100, = μnCox 200 = Ω, 3.33 103 × – Ω, 668 103 × – EXERCISE 7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 527 various amplifier stages through a process known as current steering. This approach has the advantage that the effort expended on generating a predictable and stable reference cur-rent, usually utilizing a precision resistor external to the chip or a special circuit on the chip, need not be repeated for every amplifier stage. Furthermore, the bias currents of the various stages track each other in case of changes in power-supply voltage or in temperature. In this section we study circuit building blocks and techniques employed in the bias design of IC amplifiers. These current-source circuits are also utilized as amplifier load ele-ments, as we have seen in Sections 7.2 and 7.3.
7.4.1 The Basic MOSFET Current Source Figure 7.22 shows the circuit of a simple MOS constant-current source. The heart of the cir-cuit is transistor Q1, the drain of which is shorted to its gate,4 thereby forcing it to operate in the saturation mode with (7.52) where we have neglected channel-length modulation. The drain current of Q1 is supplied by through resistor R, which in most cases would be outside the IC chip. Since the gate currents are zero, (7.53) where the current through R is considered to be the reference current of the current source and is denoted Equations (7.52) and (7.53) can be used to determine the value required for R.
Now consider transistor It has the same as Q1; thus, if we assume that it is oper-ating in saturation, its drain current, which is the output current of the current source, will be (7.54) 4Such a transistor is said to be diode connected.
ID1 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ 1 (V GS Vtn) – 2 = VDD ID1 IREF VDD VGS – R -------------------------= = IREF.
Q2: VGS IO IO ID2 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ 2 (V GS −V tn)2 = = I 0 0 0 REF V GS ID1 IO R VDD VO Q1 Q2 I 0 0 0 REF V GS ID1 IO R VDD VO Q1 Q2 Figure 7.22 Circuit for a basic MOSFET constant-current source. For proper operation, the output terminal, that is, the drain of Q2, must be connected to a circuit that ensures that Q2 operates in saturation.
528 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers where we have neglected channel-length modulation. Equations (7.52) and (7.54) enable us to relate the output current to the reference current as follows: (7.55) This is a simple and attractive relationship: The special connection of and provides an output current that is related to the reference current by the aspect ratios of the transistors. In other words, the relationship between and is solely determined by the geometries of the transistors. In the special case of identical transistors, and the circuit simply replicates or mirrors the reference current in the output terminal. This has given the circuit composed of and the name current mirror, a name that is used irrespective of the ratio of device dimensions.
Figure 7.23 depicts the current-mirror circuit with the input reference current shown as being supplied by a current source for both simplicity and generality. The current gain or current transfer ratio of the current mirror is given by Eq. (7.55).
Effect of VO on IO In the description above for the operation of the current source of Fig.
7.22, we assumed to be operating in saturation. This is essential if is to supply a con-stant-current output. To ensure that is saturated, the circuit to which the drain of is to be connected must establish a drain voltage that satisfies the relationship (7.56) or, equivalently, in terms of the overdrive voltage of and (7.57) In other words, the current source will operate properly with an output voltage as low as which is a few tenths of a volt.
Although thus far neglected, channel-length modulation can have a significant effect on the operation of the current source. Consider, for simplicity, the case of identical devices and The drain current of will equal the current in at the value of that causes the two devices to have the same that is, at As is increased above this value, will increase according to the incremental output resistance of This is illustrated in Fig. 7.24, which shows versus Observe that since is oper-ating at a constant (determined by passing through the matched device the IO IREF IO IREF --------- (W L ⁄ )2 (W L ⁄ ) 1 -------------------= Q1 Q2 IO IREF IO IREF IO IREF, = Q1 Q2 Q2 IREF V GS IO Q1 Q2 V O Figure 7.23 Basic MOSFET current mirror.
Q2 Q2 Q2 VO V O VGS Vtn – ≥ VOV Q1 Q2, VO V OV ≥ VO V OV, Q1 Q2.
Q2, IO, Q1, IREF, V O VDS, VO = VGS.
VO IO ro2 Q2.
IO V O.
Q2 VGS IREF Q1), 7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 529 curve in Fig. 7.24 is simply the characteristic curve of for equal to the par-ticular value In summary, the current source of Fig. 7.22 and the current mirror of Fig. 7.23 have a finite output resistance (7.58) where is given by Eq. (7.54) and is the Early voltage of Also, recall that for a given process technology, is proportional to the transistor channel length; thus, to obtain high output-resistance values, current sources are usually designed using transistors with relatively long channels. Finally, note that we can express the current as (7.59) Figure 7.24 Output characteristic of the current source in Fig. 7.22 and the current mirror of Fig. 7.23 for the case of Q2 matched to Q1.
IO V O V Slope GS IREF r 1 o V 0 tn V GS VOV iD–vDS Q2 vGS VGS.
Ro, Ro ≡ VO Δ IO Δ ---------- = ro2 = V A2 IO --------IO VA2 Q2.
VA IO IO (W L ⁄ )2 (W L ⁄ ) 1 ------------------- IREF 1 VO VGS – V A2 ---------------------+ ⎝ ⎠ ⎛ ⎞ = Given and using μA, design the circuit of Fig. 7.22 to obtain an output current whose nominal value is 100 μA. Find R if and are matched and have channel lengths of 1 μm, chan-nel widths of 10 μm, and What is the lowest possible value of Assum-ing that for this process technology, the Early voltage /μm, find the output resistance of the current source. Also, find the change in output current resulting from a +1-V change in Solution Thus, VDD = 3 V IREF =100 Q1 Q2 Vt = 0.7 V, kn ′ = 200 μA/V2 .
V O?
VA ′ = 20 V V O.
ID1 = IREF 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ 1 VOV 2 = 100 = 1 2 ---200 10VOV 2 × × VOV 0.316 V = Example 7.5 530 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.4.2 MOS Current-Steering Circuits As mentioned earlier, once a constant current has been generated, it can be replicated to pro-vide dc bias or load currents for the various amplifier stages in an IC. Current mirrors can obviously be used to implement this current-steering function. Figure 7.25 shows a simple current-steering circuit. Here together with R determine the reference current Tran-sistors and form a two-output current mirror, (7.60) (7.61) To ensure operation in the saturation region, the voltages at the drains of and are constrained as follows: (7.62) Example 7.5 continued and For the transistors used, L = 1 μm. Thus, The output current will be 100 μA at If changes by +1 V, the corresponding change in will be μA VGS Vt + VOV 0.7 0.3161 V + = = R = VDD VGS – IREF ------------------------- 3 1 – 0.1 mA ------------------ 20 kΩ = = V Omin = VOV 0.3 V VA = 20 1 20 V = × ro2 = 20 V 100 μA ------------------- 0.2 MΩ = VO = V GS 1 V.
= VO IO IO VO Δ ro2 ---------- 1 V 0.2 MΩ ------------------- 5 = = = Δ D7.15 In the current source of Example 7.5, it is required to reduce the change in output current, corresponding to a change in output voltage, of 1 V to 1% of What should the dimen-sions of and be changed to? Assume that and are to remain matched.
Ans. L = 5 μm; W = 50 μm IO, Δ VO, Δ IO.
Q1 Q2 Q1 Q2 EXERCISE Q1 IREF.
Q1, Q2, Q3 I2 = IREF (W L ⁄ )2 (W L ⁄ ) 1 -------------------I3 = IREF (W L ⁄ ) 3 (W L ⁄ ) 1 -------------------Q2 Q3 VD2 VD3 , VSS – +VGS1 −Vtn ≥ 7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 531 or, equivalently, (7.63) where is the overdrive voltage at which and are operating. In other words, the drains of and will have to remain higher than by at least the over-drive voltage, which is usually a few tenths of a volt.
Continuing our discussion of the circuit in Fig. 7.25, we see that current is fed to the input side of a current mirror formed by PMOS transistors and This mirror provides (7.64) where To keep in saturation, its drain voltage should be (7.65) where is the overdrive voltage at which is operating.
The constant current generated in the circuit of Fig. 7.25 can be used to bias a source-follower amplifier such as that implemented by transistor in Fig. 7.26(a). Similarly, the constant current can be used as the load for a common-source amplifier such as that implemented with transistor in Fig. 7.26(b).
Finally, an important point to note is that in the circuit of Fig. 7.25, while pulls its current from a circuit (not shown in Fig. 7.25), pushes its current into a circuit (not shown in Fig. 7.25). Thus is appropriately called a current source, whereas should more properly be called a current sink. In an IC, both current sources and current sinks are usually needed. The difference between a current source and a current sink is fur-ther illustrated in Fig. 7.27, where VCS min denotes the minimum voltage needed across the current source (or sink) for its proper operation.
Figure 7.25 A current-steering circuit.
Q2 Q1 R + – + – IREF I2 I3 I4 I5 Q3 Q5 VDD Q4 VSS VGS1 VSG5 VD2 VD3 , VSS – +VOV1 ≥ VOV1 Q1, Q2, Q3 Q2 Q3 VSS – I3 Q4 Q5.
I5 I4 (W L ⁄ ) 5 (W L ⁄ ) 4 -------------------= I4 I3.
= Q5 VD5 VDD −VOV5 ≤ V OV5 Q5 I2 Q6 I5 Q7 Q2 I2 Q5 I5 Q5 Q2 532 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.4.3 BJT Circuits The basic BJT current mirror is shown in Fig. 7.28. It works in a fashion very similar to that of the MOS mirror. However, there are two important differences: First, the nonzero base current of the BJT (or, equivalently, the finite β ) causes an error in the current transfer ratio Figure 7.27 (a) A current source; and (b) a current sink.
VDD VSS Q6 Q2 (a) vi6 I2 vo6 VDD VSS Q5 Q7 (b) vi7 I5 vo7 Figure 7.26 Application of the constant currents I2 and I5 generated in the current-steering circuit of Fig.
7.25. Constant-current I2 is the bias current for the source follower Q6, and constant-current I5 is the load current for the common-source amplier Q7.
VDD I (a) VO VDDVCSmin VCSmin VSS I (b) VO VSS VCSmin VCSmin D 7.16 For the circuit of Fig. 7.25, let all channel lengths = 1 μm, and For find the widths of all transistors to obtain μA, and μA. It is further required that the voltage at the drain of be allowed to go down to within 0.2 V of the negative supply and that the voltage at the drain of be allowed to go up to within 0.2 V of the positive supply.
Ans. μm; μm; μm; μm; μm V DD VSS 1.5 V, = = Vtn 0.6 V, = Vtp 0.6 – V, = kn ′ 200 μA/V2, = kp ′ 80 μA/V2, = λ 0.
= IREF 10 μA, = Ι2 60 μΑ, = Ι3 20 = I5 80 = Q2 Q5 W1 = 2.5 W2 =15 W3 = 5 W4 = 12.5 W5 = 50 EXERCISE 7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 533 of the bipolar mirror. Second, the current transfer ratio is determined by the relative areas of the emitter–base junctions of and Let us first consider the case of β sufficiently high that we can neglect the base currents.
The reference current is passed through the diode-connected transistor and thus establishes a corresponding voltage which in turn is applied between base and emitter of Now, if is matched to or, more specifically, if the EBJ area of is the same as that of , and thus has the same scale current as then the collector cur-rent of will be equal to that of that is, (7.66) For this to happen, however, must be operating in the active mode, which in turn is achieved as long as the collector voltage is 0.3 V or so higher than that of the emitter.
To obtain a current transfer ratio other than unity, say m, we simply arrange that the area of the EBJ of is m times that of In this case, (7.67) In general, the current transfer ratio is given by (7.68) Alternatively, if the area ratio m is an integer, one can think of as equivalent to m tran-sistors, each matched to and connected in parallel.
Next we consider the effect of finite transistor β on the current transfer ratio. The analysis for the case in which the current transfer ratio is nominally unity—that is, for the case in which is matched to —is illustrated in Fig. 7.29. The key point here is that since and are matched and have the same their collector currents will be equal. The rest of the analysis is straightforward. A node equation at the collector of yields Finally, since the current transfer ratio can be found as (7.69) IO VO Q2 Q1 IREF VBE IO VO Q2 Q1 IREF VBE Figure 7.28 The basic BJT current mirror.
Q1 Q2.
IREF Q1 VBE, Q2.
Q2 Q1 Q2 Q1 Q2 IS Q1, Q2 Q1; IO IREF = Q2 VO Q2 Q1.
IO mIREF = IO IREF -------- IS2 IS1 ------ Area of EBJ of Q2 Area of EBJ of Q1 ------------------------------------------= = Q2 Q1 Q2 Q1 Q1 Q2 VBE, Q1 IREF IC 2IC β ⁄ IC 1 2 β ---+ ⎝ ⎠ ⎛ ⎞ = + = IO IC, = IO IREF --------- IC IC 1 2 β ---+ ⎝ ⎠ ⎛ ⎞ ------------------------ 1 1 2 β ---+ ------------= = 534 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Note that as β approaches ∞, approaches the nominal value of unity. For typical values of β, however, the error in the current transfer ratio can be significant. For instance, results in a 2% error in the current transfer ratio. Furthermore, the error due to the finite β increases as the nominal current transfer ratio is increased. The reader is encouraged to show that for a mirror with a nominal current transfer ratio m—that is, one in which —the actual current transfer ratio is given by (7.70) In common with the MOS current mirror, the BJT mirror has a finite output resistance (7.71) where and are the Early voltage and the output resistance, respectively, of Thus, even if we neglect the error due to finite β, the output current will be at its nominal value only when has the same as namely at As is increased, will correspondingly increase. Taking both the finite β and the finite into account, we can express the output current of a BJT mirror with a nominal current transfer ratio m as (7.72) where we note that the error term due to the Early effect is expressed in a form that shows that it reduces to zero for .
IO IC VO Q2 Q1 IREF 2ICb IC1 1 b IC1 1 b IC ICb ICb Figure 7.29 Analysis of the current mirror taking into account the finite β of the BJTs.
IO IREF ⁄ β = 100 IS2 mIS1 = IO IREF --------- m 1 m 1 + β -------------+ -----------------------= Ro, Ro VO Δ IO Δ ---------- ro2 VA2 IO --------= = ≡ V A2 ro2 Q2.
IO Q2 VCE Q1, VO VBE.
= VO IO Ro IO IREF m 1 m 1 + β -------------+ -----------------------⎝ ⎠ ⎜ ⎟ ⎜ ⎟ ⎛ ⎞ 1 VO VBE – VA2 ---------------------+ ⎝ ⎠ ⎛ ⎞ = VO VBE = 7.17 Consider a BJT current mirror with a nominal current transfer ratio of unity. Let the transistors have and For find when Also, find the output resistance.
Ans. 1.02 mA; 100 kΩ IS =10 15 – A, β =100, V A =100 V.
IREF =1 mA, IO VO = 5 V.
EXERCISE 7.4 IC Biasing—Current Sources, Current Mirrors, and Current-Steering Circuits 535 A Simple Current Source In a manner analogous to that in the MOS case, the basic BJT current mirror can be used to implement a simple current source, as shown in Fig. 7.30. Here the reference current is (7.73) where is the base–emitter voltage corresponding to the desired value of IREF. The output current is given by (7.74) The output resistance of this current source is of (7.75) Current Steering To generate bias currents for different amplifier stages in an IC, the current-steering approach described for MOS circuits can be applied in the bipolar case. As an example, consider the circuit shown in Fig. 7.31. The dc reference current is gener-IREF VCC −VBE R -----------------------= VBE IO IO IREF 1 2 β ⁄ ( ) + ------------------------ 1 VO VBE – VA ---------------------+ ⎝ ⎠ ⎛ ⎞ = ro Q2, Ro ro2 = ( ) V A IO ------ VA IREF ---------Figure 7.30 A simple BJT current source.
D7.18 Assuming the availability of BJTs with scale currents β = 100, and , design the current-source circuit of Fig. 7.30 to provide an output current at The power supply Give the values of R, and Also, find at Ans. 0.497 mA; 8.71 kΩ; 0.3 V; 0.53 mA IS =10 15 – A, V A 50 V = ΙΟ 0.5 mΑ = VO 2 V.
= V CC 5 V.
= IREF, V Omin.
IO VO 5 V.
= EXERCISE IREF 536 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers ated in the branch that consists of the diode-connected transistor resistor R, and the diode-connected transistor (7.76) Now, for simplicity, assume that all the transistors have high β and thus that the base currents are negligibly small. We will also neglect the Early effect. The diode-connected transistor forms a current mirror with thus will supply a constant current I equal to Tran-sistor can supply this current to any load as long as the voltage that develops at the collec-tor does not exceed otherwise would enter the saturation region. To generate a dc current twice the value of two transistors, and each of which is matched to are connected in parallel, and the combination forms a mirror with Thus Note that the parallel combination of and is equivalent to a tran-sistor with an EBJ area double that of which is precisely what is done when this circuit is fabricated in IC form.
Transistor forms a mirror with thus provides a constant current equal to Note that while sources its current to parts of the circuit whose voltage should not exceed sinks its current from parts of the circuit whose voltage should not decrease below Finally, to generate a current three times three tran-sistors, and each of which is matched to are connected in parallel, and the combination is placed in a mirror configuration with Again, in an IC implementation, and would be replaced with a transistor having a junction area three times that of .
Figure 7.31 Generation of a number of constant currents of various magnitudes.
Q1, Q2: IREF VCC + VEE −VEB1 −VBE2 R -------------------------------------------------------= Q1 Q3; Q3 IREF.
Q3 (V CC 0.3 V – ); Q3 IREF, Q5 Q6, Q1, Q1.
I3 = 2IREF.
Q5 Q6 Q1, Q4 Q2; Q4 I2 IREF.
Q3 (VCC 0.3 V), – Q4 −V EE 0.3 V.
+ IREF, Q7, Q8, Q9, Q2, Q2.
Q7, Q8, Q9 Q2 7.5 Current-Mirror Circuits with Improved Performance 537 7.5 Current-Mirror Circuits with Improved Performance As we have seen throughout this chapter, current sources play a major role in the design of IC amplifiers: The constant-current source is used both in biasing and as active load. Simple forms of both MOS and bipolar current sources and, more generally, current mirrors were studied in Section 7.4. The need to improve the characteristics of the simple sources and mirrors has already been demonstrated. Specifically, two performance parameters need to be addressed: the accuracy of the current transfer ratio of the mirror and the output resistance of the current source.
The reader will recall from Section 7.4 that the accuracy of the current transfer ratio suffers particularly from the finite β of the BJT. The output resistance, which in the simple circuits is limited to of the MOSFET and the BJT, also reduces accuracy and, much more seriously, severely limits the gain available from cascode amplifiers (Section 7.3). In this section we study MOS and bipolar current mirrors with more accurate current transfer ratios and higher output resistances.
7.19 Figure E7.19 shows an N-output current mirror. Assuming that all transistors are matched and have finite β and ignoring the effect of finite output resistances, show that For , find the maximum number of outputs for an error not exceeding 10%.
Figure E7.19 Ans. 9 I1 I2 = . . . = IN = IREF 1 N 1 + ( ) β ⁄ + ----------------------------------= β = 100 VEE Q1 Q2 QN I1 I2 IN IREF QREF EXERCISE ro 538 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.5.1 Cascode MOS Mirrors The use of cascoding in the design of current sources was presented in Section 7.3. Figure 7.32 shows the basic cascode current mirror. Observe that in addition to the diode-connected transistor Q1, which forms the basic mirror Q1–Q2, another diode-connected transistor, Q4, is used to provide a suitable bias voltage for the gate of the cascode transis-tor Q3. To determine the output resistance of the cascode mirror at the drain of Q3, we assume that the voltages across Q1 and Q4 are constant, and thus the signal voltages at the gates of Q2 and Q3 will be zero. Thus Ro will be that of the cascode current source formed by Q2 and Q3, (7.77) Thus, as expected, cascoding raises the output resistance of the current source by the factor , which is the intrinsic gain of the cascode transistor.
A drawback of the cascode current mirror is that it consumes a relatively large portion of the steadily shrinking supply voltage . While the simple MOS mirror operates properly with a voltage as low as across its output transistor, the cascode circuit of Fig. 7.32 requires a minimum voltage of . This is because the gate of Q3 is at . Thus the minimum voltage required across the output of the cascode mirror is 1 V or so. This obviously limits the signal swing at the output of the mirror (i.e., at the out-put of the amplifier that utilizes this current source as a load). In Chapter 12 we shall study a wide-swing cascode mirror. Ro gm3ro3ro2 gm3ro3 ( ) VDD VOV Vt 2VOV + 2VGS = 2Vt 2VOV + 7.20 For a cascode MOS mirror utilizing devices with , , /μm, and μA, find the minimum voltage required at the output and the output resistance.
Ans. 0.95 V; 285 kΩ Vt 0.5 V = μnCox 387 = μA/V2 V A ′ 5 V = W/L = 3.6 μm 0.36 μm, ⁄ IREF 100 = EXERCISE VO VO Ro Figure 7.32 A cascode MOS current mirror.
7.5 Current-Mirror Circuits with Improved Performance 539 7.5.2 A Bipolar Mirror with Base-Current Compensation Figure 7.33 shows a bipolar current mirror with a current transfer ratio that is much less dependent on β than that of the simple current mirror. The reduced dependence on β is achieved by including transistor Q3, the emitter of which supplies the base currents of Q1 and Q2. The sum of the base currents is then divided by resulting in a much smaller error current that has to be supplied by Detailed analysis is shown on the cir-cuit diagram; it is based on the assumption that Q1 and Q2 are matched and thus have equal collector currents, A node equation at the node labeled x gives Since the current transfer ratio of the mirror will be (7.78) which means that the error due to finite β has been reduced from in the simple mir-ror to a tremendous improvement. Unfortunately, however, the output resistance remains approximately equal to that of the simple mirror, namely Finally, note that if a reference current is not available, we simply connect node x to the power supply. through a resistance R. The result is a reference current given by (7.79) 7.5.3 The Wilson Current Mirror A simple but ingenious modification of the basic bipolar mirror results in both reducing the β dependence and increasing the output resistance. The resulting circuit, known as the Wilson β3 1 + ( ), IREF.
IC.
IREF IC 1 2 β β 1 + ( ) ---------------------+ = IO IC = IO IREF --------- 1 1 2 β 2 β + ( ) ⁄ + ------------------------------------= 1 1 2 β 2 ⁄ + ---------------------2 β ⁄ 2 β 2 ⁄ , ro.
IREF V CC IREF VCC VBE1 – VBE3 – R ------------------------------------------= Q2 Q1 Q3 x IC IREF IC IC 2IC 2IC (1) IO IC Figure 7.33 A current mirror with base-current compensation.
540 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers mirror after its inventor George Wilson, an IC design engineer working for Tektronix, is shown in Fig. 7.34(a). The analysis to determine the effect of finite β on the current transfer ratio is shown in Fig. 7.34(a), from which we can write (7.80) This analysis assumes that and conduct equal collector currents. There is, however, a slight problem with this assumption: The collector-to-emitter voltages of and are not equal, which introduces a current offset or a systematic error. The problem can be solved Figure 7.34 The Wilson bipolar current mirror: (a) circuit showing analysis to determine the current transfer ratio; (b) determining the output resistance. (a) Q3 Q1 VEE Q2 IC IC 1 IC IC 1 IREF IC IC 2 IC 1 2 1 1 2 1 IO IC (1 2) 1 2IC Q2 Q1 ro2 ro1 ro3 b3i2 Ro vx ix v i1re1 i2 i1 i2 (b) ix Q3 vx IO IREF --------- IC 1 2 β ---+ ⎝ ⎠ ⎛ ⎞β β 1 + ( ) IC 1 1 2 β ---+ ⎝ ⎠ ⎛ ⎞ β 1 + ( ) + --------------------------------------------------------------= β 2 + β 1 β 2 + β ------------+ + ------------------------------- β 2 + β 2 2 β ---+ + ----------------------= = 1 1 2 β β 2 + ( ) ---------------------+ ------------------------------= 1 1 2 β 2 ⁄ + ---------------------Q1 Q2 Q1 Q2 7.5 Current-Mirror Circuits with Improved Performance 541 by adding a diode-connected transistor in series with the collector of , as we shall shortly show for the MOS version.
To determine the output resistance of the Wilson mirror, we set and apply a test voltage to the output node, as shown in Fig. 7.34(b). Our purpose is to determine the cur-rent and hence as Rather than replacing each transistor with its hybrid-π model, we shall do the analysis directly on the circuit diagram. For this purpose, we have “pulled out” of each transistor and shown it separately. Observe that transistor , viewed as a supernode (highlighted in color), has a current entering it and two currents and exiting it; thus, Next note that the action of current mirror – forces to be approximately equal to ; thus, Current flows into the base of and thus gives rise to a collector current in the direction indicated. We are now in a position to write a node equation at the collector of and thus determine the current through as Finally, we can express the voltage between the collector of and ground as the sum of the voltage drop across and the voltage v across , Since and and (7.81) Thus the Wilson current mirror has an output resistance times higher than that of alone. This is a result of the negative feedback obtained by feeding the collector current of back to the base of As can be seen from the above analysis, this feedback results in increasing the current through to approximately , and thus the voltage across and the output resistance increase by the same factor, . Finally, note that the factor is because only half of is mirrored back to the base of .
The Wilson mirror is preferred over the cascode circuit because the latter has the same dependence on β as the simple mirror. However, like the cascode mirror, the Wilson mir-ror requires an additional drop for its operation; that is, for proper operation we must allow for 1 V or so across the Wilson mirror output. Q2 IREF 0 = vx ix Ro Ro vx ix ⁄ = ro Q3 ix i1 i2 i1 i2 ix = + Q1 Q2 i2 i1 i2 i1 ix 2 ⁄ = i2 Q3 β3i2 Q3 ro2 ix β3i2 ix β3 ix 2 ⁄ ( ) ix β3 2 ⁄ 1 + ( ).
= + = + Q3 ro3 Q1 vx ix β3 2 -----1 + ⎝ ⎠ ⎛ ⎞ro3 i1re1 + = ix β3 2 -----1 + ⎝ ⎠ ⎛ ⎞ro3 ix 2 ---⎝⎠ ⎛⎞re1 + = ro re β3 2, vx ix β3 2 -----⎝ ⎠ ⎛ ⎞ro3 Ro β3ro3 2 ⁄ = 1 2 --β3 ( ) Q3 Q2 i2 ( ) Q3.
ro3 1 2 --β3ix ro3 1 2 --β3 1 2 --ix Q3 VBE 542 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.5.4 The Wilson MOS Mirror Figure 7.35(a) shows the MOS version of the Wilson mirror. Obviously there is no β error to reduce here, and the advantage of the MOS Wilson lies in its enhanced output resistance. To determine the output resistance of the Wilson MOS mirror, we set and apply a test voltage to the output node, as shown in Fig. 7.35(b). Our purpose is to deter-mine the current and hence as Rather than replacing each transistor with its hybrid-π, equivalent-circuit model, we shall perform the analysis directly on the circuit. For this purpose, we have “pulled out” of each transistor and shown it separately.
Observe that the current that enters the drain of must exit at its source. Thus the current that feeds the input side of the – mirror is equal to Most of this current will flow in the drain proper of (i.e., only a very small fraction flows through ) and will give rise to a voltage , where is the approximate resistance of the diode-connected transistor The current-mirror action of (Q1, Q2) forces a current equal to to flow through the drain proper of Now, since the current in the drain of is forced (by the connection to the gate of Q3) to be zero, all of must flow through resulting in a voltage This is the voltage fed back to the gate of . The drain current of can now be found as A node equation at the drain of gives the current through as Finally, we can express as the sum of the voltage drop across and the voltage v across , and obtain (7.82) 7.21 For and contrast the Wilson mirror and the simple mirror by evaluating the transfer-ratio error due to finite β, and the output resistance.
Ans. Transfer-ratio error: 0.02% for Wilson as opposed to 2% for the simple circuit; for Wilson compared to 100 kΩ for the simple circuit β 100 = ro 100 kΩ, = Ro 5 ΜΩ = EXERCISE IREF 0, = vx ix Ro Ro vx ix ⁄ = ro ix Q3 Q1 Q2 ix.
Q1 ro1 v ix gm1 ⁄ 1 gm1 ⁄ Q1.
ix Q2.
Q2 ix ro2, ixro2.
– Q3 Q3 id3 gm3vgs3 = gm3 vg3 vs3 – ( ) = gm3 ix – ro2 ix gm1 ⁄ – ( ) = gm3ro2 ( )ix – Q3 ro3 ix id3 – ( ) = ix gm3ro2ix gm3ro2ix.
+ vx ro3 Q1 vx gm3ro2ixro3 v + = gm3ro3ro2 ( )ix ix gm1 ⁄ ( ) + = g m3ro3ro2ix Ro vx ix ----gm3ro3 ( )ro2 = = 7.5 Current-Mirror Circuits with Improved Performance 543 Thus, the Wilson MOS mirror exhibits an increase of output resistance by a factor , an identical result to that achieved in the cascode mirror. Here the increase in as demon-strated in the analysis above, is a result of the negative feedback obtained by connecting the drain of to the gate of Finally, to balance the two branches of the mirror and thus avoid the systematic current error resulting from the difference in between and the circuit can be modified as shown in Fig. 7.35(c).
7.5.5 The Widlar Current Source5 Our final current-source circuit, known as the Widlar current source, is shown in Fig. 7.36. It differs from the basic current mirror circuit in an important way: A resistor RE is included in 5Named after Robert Widlar, a pioneer in analog IC design.
VO (a) Q2 Q1 Q2 Q1 ro2 ro1 ro3 id3 Ro vx ix v ix gm1 (ixro2) ix 0 (b) ix ix ix ix Q3 vx VO (c) Q2 Q1 Figure 7.35 The Wilson MOS mirror: (a) circuit; (b) analysis to determine output resistance; (c) modified circuit.
gm3ro3 ( ) Ro, Q2 Q3.
VDS Q1 Q2, 544 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers the emitter lead of Q2. Neglecting base currents we can write (7.83) and (7.84) where we have assumed that Q1 and Q2 are matched devices. Combining Eqs. (7.83) and (7.84) gives (7.85) But from the circuit we see that (7.86) Thus, (7.87) The design and advantages of the Widlar current source are illustrated in the following example.
V BE1 VT IREF IS ---------⎝ ⎠ ⎛ ⎞ ln = VBE2 = VT IO IS ----⎝ ⎠ ⎛ ⎞ ln V BE1 − V BE2 = VT IREF IO ---------⎝ ⎠ ⎛ ⎞ ln VBE1 = VBE2 IORE + IORE = VT IREF IO ---------⎝ ⎠ ⎛ ⎞ ln Figure 7.36 The Widlar current source.
The two circuits for generating a constant current IO = 10 μA shown in Fig. 7.37 operate from a 10-V supply. Determine the values of the required resistors, assuming that VBE is 0.7 V at a current of 1 mA and neglecting the effect of finite β.
Example 7.6 7.5 Current-Mirror Circuits with Improved Performance 545 From the above example we observe that using the Widlar circuit allows the generation of a small constant current using relatively small resistors. This is an important advantage that results in considerable savings in chip area. In fact the circuit of Fig. 7.37(a), requiring a 942-kΩ resistance, is totally impractical for implementation in IC form because of the very-high value of resistor R1.
Solution For the basic current-source circuit in Fig. 7.37(a) we choose a value for R1 to result in IREF = 10 μA. At this current, the voltage drop across Q1 will be Thus, For the Widlar circuit in Fig. 7.37(b) we must first decide on a suitable value for IREF. If we select IREF =1 mA, then VBE1 = 0.7 V and R2 is given by The value of R3 can be determined using Eq. (7.87) as follows: Figure 7.37 Circuits for Example 7.6.
(a) (b) VBE1 = 0.7 VT 10 μA 1 mA ---------------⎝ ⎠ ⎛ ⎞ ln + = 0.58 V R1 10 0.58 – 0.01 ----------------------942 kΩ = = R2 10 0.7 – 1 -------------------9.3 kΩ = = 10 10 6 – × R3 0.025 1 mA 10 μA ----------------⎝ ⎠ ⎛ ⎞ ln = R3 11.5 kΩ = 546 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Another important characteristic of the Widlar current source is that its output resistance is high. The increase in the output resistance, above that achieved in the basic current source, is due to the emitter-degeneration resistance RE. To determine the output resistance of Q2, we assume that since the base of is connected to ground via the small resistance of , the incremental voltage at the base will be small. Thus we can use the formula in Eq. (7.51) and adapt it for our purposes here as follows: (7.88) Thus the output resistance is increased above by a factor that can be significant. 7.6 Some Useful Transistor Pairings The cascode configuration studied in Section 7.3 combines CS and CG MOS transistors (CE and CB bipolar transistors) to great advantage. The key to the superior performance of the resulting combination is that the transistor pairing is done in a way that maximizes the advantages and minimizes the shortcomings of each of the two individual configurations. In this section we present a number of other such transistor pairings. In each case the transistor pair can be thought of as a compound device; thus the resulting amplifier may be considered as a single stage.
7.6.1 The CC–CE, CD–CS, and CD–CE Configurations Figure 7.38(a) shows an amplifier formed by cascading a common-collector (emitter follower) transistor with a common-emitter transistor This circuit has two main advantages over the CE amplifier. First, the emitter follower increases the input resis-tance by a factor equal to As a result, the overall voltage gain is increased, especially if the resistance of the signal source is large. Second, it will be shown in Chapter 9 that the CC–CE amplifier can exhibit much wider bandwidth than that obtained with the CE amplifier.
The MOS counterpart of the CC–CE amplifier, namely, the CD–CS configuration, is shown in Fig. 7.38(b). Here, since the CS amplifier alone has an infinite input resistance, the sole purpose for adding the source-follower stage is to increase the amplifier bandwidth, as will be seen in Chapter 9. Finally, Fig. 7.38(c) shows the BiCMOS version of this circuit type. Compared to the bipolar circuit in Fig. 7.38(a), the BiCMOS circuit has an infinite input resistance. Compared to the MOS circuit in Fig. 7.38(b), the BiCMOS circuit typically has a higher Q2 re Q1 Rout 1 gm RE rπ || ( ) + [ ]ro ro 7.22 Find the output resistance of each of the two current sources designed in Example 7.6. Let and .
Ans. 10 MΩ; 54 MΩ V A =100 V β 100 = EXERCISE Q1 Q2.
β1 1 + ( ).
gm2.
7.6 Some Useful Transistor Pairings 547 Figure 7.38 (a) CC–CE amplifier; (b) CD–CS amplifier; (c) CD–CE amplifier.
VCC Q1 (a) Q2 I1 I2 VDD Q1 (b) Q2 I1 I2 Q1 Q2 (c) I1 I2 For the CC–CE amplifier in Fig. 7.38(a) let mA and assume identical transistors with Find the input resistance and the overall voltage gain obtained when the amplifier is fed with a signal source having and loaded with a resistance Compare the results with those obtained with a common-emitter amplifier operating under the same conditions. Ignore Solution At an emitter current of 1 mA, and have I1 I2 1 = = β 100.
= Rin Rsig 4 kΩ = RL 4 kΩ.
= ro.
Q1 Q2 gm 40 mA/V = re 25 Ω = rπ β gm ------100 40 ---------2.5 kΩ = = = Example 7.7 548 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Example 7.7 continued Referring to Fig. 7.39 we can find Thus, For comparison, a CE amplifier operating under the same conditions will have Figure 7.39 Circuit for Example 7.7.
Q1 Q2 (c) vsig vb1 vo vb2 Rsig Rin Rin2 RL re1 Rin2 rπ2 2.5 kΩ = = Rin β1 1 + ( ) = re1 Rin2 + ( ) 101 0.025 2.5 + ( ) 255 kΩ = = vb1 vsig -------Rin Rin Rsig + ----------------------255 255 4 + ------------------0.98 V/V = = = vb2 vb1 -------Rin2 Rin2 re1 + ----------------------2.5 2.5 0.025 + ---------------------------0.99 V/V = = = vo vb2 -------gm2 RL 40 4 160 V/V – = × – = – = Gv vo vsig -------160 0.99 0.98 155 V/V – = × × – = = Rin rπ 2.5 kΩ = = Gv Rin Rin Rsig + ----------------------gmRL – ( ) = 2.5 2.5 4 + ----------------40 4 × – ( ) = 61.5 V/V – = 7.6 Some Useful Transistor Pairings 549 7.6.2 The Darlington Configuration6 Figure 7.40(a) shows a popular BJT circuit known as the Darlington configuration. It can be thought of as a variation of the CC–CE circuit with the collector of connected to that of Alternatively, the Darlington pair can be thought of as a composite transis-tor with It can therefore be used to implement a high-performance voltage fol-lower, as illustrated in Fig. 7.40(b). Note that in this application the circuit can be considered as the cascade connection of two common-collector transistors (i.e., a CC–CC configuration).
Since the transistor β depends on the dc bias current, it is possible that will be operating at a very low β, rendering the β-multiplication effect of the Darlington pair rather ineffective. A simple solution to this problem is to provide a bias current for , as shown in Fig. 7.40(c). 6Named after Sidney Darlington, a pioneer in filter design and transistor circuit design.
Figure 7.40 (a) The Darlington configuration; (b) voltage follower using the Darlington configuration; (c) the Darlington follower with a bias current I supplied to Q1 to ensure that its β remains high.
7.23 Repeat Example 7.7 for the CD–CE configuration of Fig. 7.38(c). Let , and neglect of both transistors. Find and when (as in Example 7.7) and What would of the CC–CE amplifier in Example 7.7 be-come for ?
Ans.
; V/V, independent of V/V I1 I2 1 mA, = = β2 100 = kn1 8 mA/V2; = ro Rin Gv Rsig 4 kΩ = Rsig 400 kΩ.
= Gv Rsig 400 kΩ = Rin ∞ = Gv 145.5 – = Rsig; 61.7 – EXERCISE Q1 Q2.
β β1β2.
= Q1 Q1 (a) B C E Q2 Q1 (b) RE VEE Q1 Q2 VCC vsig vo Rsig Rin Rout (c) RE I VCC VEE Q2 Q1 550 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.6.3 The CC–CB and CD–CG Configurations Cascading an emitter follower with a common-base amplifier, as shown in Fig. 7.41(a), results in a circuit with a low-frequency gain approximately equal to that of the CB but with the problem of the low input resistance of the CB solved by the buffering action of the CC stage. It will be shown in Chapter 9 that this circuit exhibits wider bandwidth than that obtained with a CE amplifier of the same gain. Note that the biasing current sources shown in Fig. 7.41(a) ensure that each of and is operating at a bias current I. We are not Figure 7.41 (a) A CC–CB amplifier. (b) Another version of the CC–CB circuit with Q2 implemented using a pnp transistor. (c) The MOSFET version of the circuit in (a).
7.24 For the Darlington voltage follower in Fig. 7.40(b), show that: Evaluate and for the case and Ans. 10.3 MΩ; 20 Ω; 0.98 V/V Rin β1 1 + ( ) re1 β2 1 + ( ) re2 RE + ( ) + [ ] = Rout RE re2 re1 Rsig β1 1 + ( ) ⁄ [ ] + β2 1 + --------------------------------------------------+ || = vo vsig ------- RE RE re2 re1 Rsig β1 1 + ( ) ⁄ + [ ] β2 1 + ( ) ⁄ + + ---------------------------------------------------------------------------------------------------= Rin, Rout, vo v sig ⁄ IE2 5 mA, = β1 β2 100, = = RE 1 kΩ, = Rsig = 100 kΩ.
EXERCISE Q1 Q2 (a) vo I 2I VEE VCC Q2 Q1 vi Rin (b) vo VBIAS VCC VEE I Q1 Q2 vi Rin (c) VDD Q2 Q1 I vo vi 2I VSS Rin 7.6 Some Useful Transistor Pairings 551 showing, however, how the dc voltage at the base of is set or the circuit that determines the dc voltage at the collector of Both issues are usually looked after in the larger cir-cuit of which the CC–CB amplifier is a part.
An interesting version of the CC–CB configuration is shown in Fig. 7.41(b). Here the CB stage is implemented with a pnp transistor. Although only one current source is now needed, observe that we also need to establish an appropriate bias voltage at the base of This circuit is part of the internal circuit of the popular 741 op amp, which will be studied in Chapter 12.
The MOSFET version of the circuit in Fig. 7.41(a) is the CD–CG amplifier shown in Fig. 7.41(c). Q1 Q2.
Q2.
For the CC–CB amplifiers in Fig. 7.41(a) and (b), find and when each amplifier is fed with a signal source having a resistance and a load resistance is connected at the output. For simplicity, neglect Solution The analysis of both circuits is illustrated in Fig. 7.42. Observe that both amplifiers have the same and The overall voltage gain can be found as Rin, vo vi ⁄ , vo vsig ⁄ Rsig, RL ro.
Rin vo vi ⁄ .
vo v ⁄ sig vo vsig -------Rin Rin Rsig + ---------------------- α2RL 2re ------------= Q1 Q2 (a) vsig vi vo vi vi 2re Rsig Rin (b11)(2re) 2vi 2re 2 RL 2re re re RL Figure 7.42 Circuits for Example 7.8. (continued on following page) Example 7.8 552 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Q1 Q2 vsig vi vo vi vi 2re Rsig Rin (b11)(2re) 2vi 2re 2 RL 2re re re RL (b) Figure 7.42 (continued) Example 7.8 continued 7.25 For the amplifiers in Example 7.8 find and for the case I = 1 mA, Ans. 5.05 100 V/V; 50 V/V D7.26 (a) Neglecting , show that the voltage gain of the CD–CG amplifier shown earlier in Fig. 7.4(c) is given by where is a load resistance connected at the output and is the overdrive voltage at which each of and is operating.
(b) For I = 0.1 mA and find W/L for each of and to obtain a gain of 10 V/V.
Assume Ans. (b) W/L = 25 Rin, vo vi ⁄ , vo v ⁄ sig β 100.
= RL Rsig 5 kΩ.
= = kΩ; ro1 vo vi ⁄ vo vi ----IRL VOV ---------= RL VOV Q1 Q2 RL 20 kΩ, = Q1 Q2 k′ n 200 μA/V2.
= EXERCISES 553 Summary Integrated-circuit fabrication technology offers the circuit designer many exciting opportunities, the most important of which is the large number of inexpensive small-area MOS transistors. An overriding concern for IC designers, however, is the minimization of chip area or “silicon real estate.” As a result, large-valued resistors and capacitors are virtually absent.
The basic gain cell of IC amplifiers is the CS (CE) amplifi-er with a current-source load. For an ideal current-source load (i.e., one with infinite output resistance), the transistor operates in an open-circuit fashion and thus provides the maximum gain possible, The intrinsic gain is given by for a BJT and for a MOSFET. For a BJT, is constant independent of bias current and device dimen-sions. For a MOSFET, is inversely proportional to (see Eq. 7.15).
Simple current-source loads reduce the gain realized in the basic gain cell because of their finite output resistance (usual-ly comparable to the value of of the amplifying transistor).
To raise the output resistance of the CS or CE transistor, we stack a CG or CB transistor on top. This is cascoding.
The CG or CB transistor in the cascode passes the current provided by the CS or CE transistor to the output but increases the resistance at the output from to in the MOS case [ in the bipolar case]. The maximum output resistance achieved in the bipolar case is A MOS cascode amplifier operating with an ideal current-source load achieves a gain of .
To realize the full advantage of cascoding, the load current-source must also be cascoded, in which case a gain as high as can be obtained.
Double cascoding is possible in the MOS case only. How-ever, the large number of transistors in the stack between the power-supply rails results in the disadvantage of a severely limited output-signal swing. The folded-cascode configuration helps resolve this issue.
A CS amplifier with a resistance in its source lead has an output resistance The corresponding formula for the BJT case is Biasing in integrated circuits utilizes current sources. As well, current sources are used as load devices. Typically an accurate and stable reference current is generated and then replicated to provide bias currents for the various amplifier stages on the chip. The heart of the current-steering circuitry utilized to perform this function is the current mirror.
The MOS current mirror has a current transfer ratio of . For a bipolar mirror, the ratio is .
Bipolar mirrors suffer from the finite , which reduces the accuracy of the current transfer ratio.
Both bipolar and MOS mirrors of the basic type have a finite output resistance equal to of the output device.
Also, for proper operation, a voltage of at least 0.3 V is required across the output transistor of a simple bipolar mirror ( for the MOS case).
Cascoding can be applied to current mirrors to increase their output resistances. An alternative that also solves the problem in the bipolar case is the Wilson circuit. The MOS Wilson mirror has an output resistance of and the BJT version has an output resistance of Both the cascode and Wilson mirrors require at least 1 V or so for proper operation.
The Widlar current source provides an area-efficient way to implement a low-valued constant-current source that also has a high output resistance.
Preceding the CE (CS) transistor with an emitter follower (a source follower) results in increased input resistance in the BJT case and wider bandwidth in both the BJT and MOS cases.
Preceding the CB (CG) transistor with an emitter follower (a source follower) solves the low-input-resistance prob-lem of the CB and CG configurations.
The Darlington configuration results in an equivalent BJT with a current gain approaching Avo gmro A – 0.
= – = A0 A0 VA VT ⁄ = A0 VA VOV 2 ⁄ ( ) ⁄ = A0 A0 ID ro gm1vi ro1 gm2ro2 ( )ro1 gm2 ro1 rπ2 || ( )ro2 β2ro2.
gmro ( )2 A0 2 = 1 2 ---A0 2 Rs Ro 1 gmRs + ( )ro.
Ro 1 gm Re rπ || ( ) + [ ] = ro.
W L ⁄ ( )2 W L ⁄ ( )1 ⁄ IS2 IS1 ⁄ β ro VOV β gmro ( )ro, 1 2 --βro.
β 2.
554 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Appendix 7.A Comparison of the MOSFET and the BJT In this appendix we present a comparison of the characteristics of the two major electronic devices: the MOSFET and the BJT. To facilitate this comparison, typical values for the important parameters of the two devices are first presented. We also discuss the design parameters available with each of the two devices, such as IC in the BJT, and ID and VOV in the MOSFET, and the trade-offs encountered in deciding on suitable values for these.
7.A.1 Typical Values of MOSFET Parameters Typical values for the important parameters of NMOS and PMOS transistors fabricated in a number of CMOS processes are shown in Table 7.A.1. Each process is characterized by the minimum allowed channel length, thus, for example, in a 0.18-μm process, the smallest transistor has a channel length L = 0.18 μm. The technologies presented in Table 7.A.1 are in descending order of channel length, with that having the shortest channel length being the most modern. Although the 0.8-μm process is now obsolete, its data are included to show trends in the values of various parameters. It should also be mentioned that although Table 7.A.1 stops at the 0.13-μm process, by 2009 there were 90-, 65-, and 45-nm processes avail-able, and processes down to 22 nm were in various stages of development. The 0.18-μm and the 0.13-μm processes, however, remained popular in the design of analog ICs. The most recently announced digital ICs utilize 65-nm and 45-nm processes and pack as many as 2.3 billion transistors onto one chip. An important caution is in order regarding the data pre-sented in Table 7.A.1: These data do not pertain to any particular commercially available process. Accordingly, these generic data are not intended for use in an actual IC design; rather, they show trends and, as we shall see, help to illustrate design trade-offs as well as enable us to work out design examples and problems with parameter values that are as real-istic as possible.
As indicated in Table 7.A.1, the trend has been to reduce the minimum allowable chan-nel length. This trend has been motivated by the desire to pack more transistors on a chip as well as to operate at higher speeds or, in analog terms, over wider bandwidths.
Observe that the oxide thickness, tox, scales down with the channel length, reaching 2.7 nm for the 0.13-μm process. (The 65-nm process, not shown in Table 7.A.1, has an oxide thickness of 1.2 nm.) Since the oxide capacitance Cox is inversely proportional to tox, Lmin; Table 7.A.1 Typical Values of CMOS Device Parameters 0.8 μm 0.5 μm 0.25 μm 0.18 μm 0.13 μm Parameter NMOS PMOS NMOS PMOS NMOS PMOS NMOS PMOS NMOS PMOS tox (nm) Cox (fF/μm2) μ (cm2/V⋅s) μCox (μA/V2) Vt0 (V) VDD (V) Cov (fF/μm) 15 2.3 550 127 0.7 5 25 0.2 15 2.3 250 58 −0.7 5 20 0.2 9 3.8 500 190 0.7 3.3 20 0.4 9 3.8 180 68 −0.8 3.3 10 0.4 6 5.8 460 267 0.5 2.5 5 0.3 6 5.8 160 93 −0.6 2.5 6 0.3 4 8.6 450 387 0.5 1.8 5 0.37 4 8.6 100 86 −0.5 1.8 6 0.33 2.7 12.8 400 511 0.4 1.3 5 0.36 2.7 12.8 100 128 –0.4 1.3 6 0.33 ⎢ V ′ A ⎢(V/μm) Appendix 7.A Comparison of the MOSFET and the BJT 555 we see that Cox increases as the technology scales down. The surface mobility μ decreases as the technology minimum-feature size is decreased, and decreases faster than As a result, the ratio of to has been decreasing with each generation of technology, falling from about 0.5 for older technologies to 0.2 or so for the newer ones. Despite the reduction of and the transconductance parameters and have been steadily increasing. As a result, modern short-channel devices achieve required levels of bias currents at lower overdrive voltages. As well, they achieve higher transconductance, a major advantage.
Although the magnitudes of the threshold voltages and have been decreasing with from about 0.7–0.8 V to 0.3–0.4 V, the reduction has not been as large as that of the power supply The latter has been reduced dramatically, from 5 V for older technol-ogies to 1.3 V for the 0.13-μm process (and approaching 1 V for the 45-nm process). This reduction has been necessitated by the need to keep the electric fields in the smaller devices from reaching very high values. Another reason for reducing is to keep power dissipa-tion as low as possible given that the IC chip now has a much larger number of transistors.7 The fact that in modern short-channel CMOS processes has become a much larger proportion of the power-supply voltage poses a serious challenge to the circuit design engi-neer. Recalling that where is the overdrive voltage, to keep reasonably small, for modern technologies is usually in the range of 0.1 V to 0.2 V. To appreciate this point further, recall that to operate a MOSFET in the saturation region, must exceed thus, to be able to have a number of devices stacked between the power-supply rails in a regime in which is only 1.8 V or lower, we need to keep as low as possible. We will shortly see, however, that operating at a low has some drawbacks.
Another significant though undesirable feature of modern deep submicron (Lmin < 0.25 μm) CMOS technologies is that the channel-length modulation effect is very pronounced. As a result, has decreased to about 5 V/μm, which combined with the decreasing values of L has caused the Early voltage to become very small. Correspondingly, short-channel MOSFETs exhibit low output resistances.
When we study the MOSFET high-frequency8 equivalent-circuit model in Section 9.2 and the high-frequency response of the common-source amplifier in Section 9.3, we will learn that two major MOSFET capacitances are and While has an overlap component,9 is entirely an overlap capacitance. Both and the overlap component of are almost equal and are denoted The last line of Table 7.A.1 provides the value of per micron of gate width. Although the normalized has been staying more or less constant with the reduction in we will shortly see that the shorter devices exhibit much higher operating speeds and wider amplifier bandwidths than the longer devices. Specifically, we will, for example, see that for a 0.25-μm NMOS transistor can be as high as 10 GHz.
7Chip power dissipation is a very serious issue, with some ICs dissipating as much as 100 W. As a result, an important current area of research concerns what is termed “power-aware design.” 8For completeness, this appendix includes material on the high-frequency models and operation of both the MOSFET and the BJT. These topics are covered in Chapter 9. The reader can easily skip the appen-dix paragraphs dealing with these topics until Chapter 9 has been studied.
9Overlap capacitances result because the gate electrode overlaps the source and drain diffusions (Fig.
5.1).
μp μn.
μp μn μn μp, kn ′ = μnCox kp ′ = μpCox Vtn Vtp Lmin VDD.
VDD Vt VGS Vt VOV , + = VOV VGS VOV VDS VOV ; VDD VOV VOV VA ′ VA = VA ′ L Cgs Cgd.
Cgs Cgd Cgd Cgs Cov.
Cov Cov Lmin, fT 556 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.A.2 Typical Values of IC BJT Parameters Table 7.A.2 provides typical values for the major parameters that characterize integrated-circuit bipolar transistors. Data are provided for devices fabricated in two different processes: the standard, old process, known as the “high-voltage process,” and an advanced, modern pro-cess, referred to as a “low-voltage process.” For each process we show the parameters of the standard npn transistor and those of a special type of pnp transistor known as a lateral pnp (as opposed to vertical, as in the npn case) (see Appendix A). In this regard we should mention that a major drawback of standard bipolar integrated-circuit fabrication processes has been the lack of pnp transistors of a quality equal to that of the npn devices. Rather, there are a number of pnp implementations for which the lateral pnp is the most economical to fabricate. Unfortu-nately, however, as should be evident from Table 7.A.2, the lateral pnp has characteristics that are much inferior to those of the vertical npn. Note in particular the lower value of β and the much larger value of the forward transit time that determines the emitter–base diffusion capacitance and, hence, the transistor speed of operation. The data in Table 7.A.2 can be used to show that the unity-gain frequency of the lateral pnp is 2 orders of magnitude lower than that of the npn transistor fabricated in the same process. Another important difference between the lateral pnp and the corresponding npn transistor is the value of collector current at which their β values reach their maximums: For the high-voltage process, for example, this current is in the tens of microamperes range for the pnp and in the milliampere range for the npn. On the positive side, the problem of the lack of high-quality pnp transistors has spurred analog circuit designers to come up with highly innovative circuit topologies that either mini-mize the use of pnp transistors or minimize the dependence of circuit performance on that of the pnp. We shall encounter some of these ingenious circuits later in this book.
The dramatic reduction in device size achieved in the advanced low-voltage process should be evident from Table 7.A.2. As a result, the scale current also has been reduced by about three orders of magnitude. Here we should note that the base width, achieved in the advanced process is on the order of 0.1 μm, as compared to a few microns in the standard high-voltage process. Note also the dramatic increase in speed; for the low-voltage npn transistor, ps as opposed to 0.35 ns in the high-voltage process. As a result, for the modern npn transistor is 10 GHz to 25 GHz, as compared to the 400 MHz to 600 MHz achieved in the high-voltage process. Although the Early voltage, for the modern process is lower than its value in the old high-voltage process, it is still reasonably high at 35 V. Another feature of the advanced process—and one that is not obvious from Table 7.A.2—is that β for the npn Table 7.A.2 Typical Parameter Values for BJTs Standard High-Voltage Process Advanced Low-Voltage Process Parameter npn Lateral pnp npn Lateral pnp AE (μm2) IS (A) β0 (A/A) VA (V) VCEO (V) τF Cje0 Cμ0 rx (Ω) 500 5 × 10−15 200 130 50 0.35 ns 1 pF 0.3 pF 200 900 2 × 10−15 50 50 60 30 ns 0.3 pF 1 pF 300 2 6 × 10−18 100 35 8 10 ps 5 fF 5 fF 400 2 6 × 10−18 50 30 18 650 ps 14 fF 15 fF 200 Adapted from Gray et al. (2001); see Appendix F.
τF Cde IS WB, τF =10 fT VA, Appendix 7.A Comparison of the MOSFET and the BJT 557 peaks at a collector current of 50 μA or so. Finally, note that as the name implies, npn transis-tors fabricated in the low-voltage process break down at collector–emitter voltages of 8 V, versus 50 V or so for the high-voltage process. Thus, while circuits designed with the stan-dard high-voltage process utilize power supplies of (e.g., in commercially available op amps of the 741 type), the total power-supply voltage utilized with modern bipolar devices is 5 V (or even 2.5 V to achieve compatibility with some of the submicron CMOS processes).
7.A.3 Comparison of Important Characteristics Table 7.A.3 provides a compilation of the important characteristics of the NMOS and the npn transistors. The material is presented in a manner that facilitates comparison. In the fol-lowing, we comment on the various items in Table 7.A.3. As well, a number of numerical examples and exercises are provided to illustrate how the wealth of information in Table 7.A.3 can be put to use. Before proceeding, note that the PMOS and the pnp transistors can be compared in a similar way. Table 7.A.3 Comparison of the MOSFET and the BJT NMOS npn Circuit Symbol To Operate in the Active Mode, Two Conditions Have to Be Satisfied (1) Induce a channel: Let (2) Pinch-off channel at drain: or equivalently, , (1) Forward-bias EBJ: (2) Reverse-bias CBJ: , or equivalently, Current–Voltage Characteristics in the Active Region Low-Frequency, Hybrid-π Model 15 V ± iG iD vDS vGD vGS iC vCE vBC vBE iB vGS Vt, ≥ Vt 0.3 0.5 V – = vGS Vt vOV + = vGD V t < vDS V OV ≥ VOV 0.1 0.3 V – = vBE VBEon, ≥ VBEon 0.5 V vBC VBCon < VBCon 0.4 V vCE 0.3 V ≥ iD 1 2 ---μnCox W L ----- vGS Vt – ( )2 1 vDS V A ---------+ ⎝ ⎠ ⎛ ⎞ = 1 2 ---μnCox W L -----vOV 2 1 vDS V A ---------+ ⎝ ⎠ ⎛ ⎞ = iG 0 = iC ISevBE VT ⁄ 1 vCE VA -------+ ⎝ ⎠ ⎛ ⎞ = iB iC β ⁄ = vgs D G S ro gmvgs vp C B E ro gmvp rp (continued) 558 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Table 7.A.3 continued NMOS npn Low-Frequency T Model Transconductance gm Output Resistance ro Intrinsic Gain Input Resistance with Source (Emitter) Grounded High-Frequency Model D S G 1 is ro is rs 1 gm C E B aie ro ie re a gm gm ID VOV 2 ⁄ ( ) ⁄ = gm μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞V OV = gm 2 μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ID = gm IC VT ⁄ = ro VA ID ⁄ VA ′ L ID ------------= = ro VA IC ⁄ = A0 gmro ≡ A0 VA VOV 2 ⁄ ( ) ⁄ = A0 2VA ′ L VOV ---------------= A0 VA ′ 2μnCoxWL ID -----------------------------------------= A0 VA VT ⁄ = rπ β gm ⁄ = Vgs D G S ro gmVgs Cgs Cgd Vp C B B ro rx gmVp rp Cp Cm E (continued) Appendix 7.A Comparison of the MOSFET and the BJT 559 Operating Conditions At the outset, note that we shall use active mode or active region to denote both the active mode of operation of the BJT and the saturation mode of operation of the MOSFET.
The conditions for operating in the active mode are very similar for the two devices: The explicit threshold of the MOSFET has as its implicit counterpart in the BJT.
Furthermore, for modern processes, and are almost equal.
Also, pinching off the channel of the MOSFET at the drain end is very similar to reverse bias-ing the CBJ of the BJT; the first makes iD nearly independent of vD, and the second makes IC nearly independent of vC. Note, however, that the asymmetry of the BJT results in and being unequal, while in the symmetrical MOSFET the operative threshold voltages at the source and the drain ends of the channel are identical Finally, for both the MOSFET and the BJT to operate in the active mode, the voltage across the device must be at least 0.1 V to 0.3 V.
Current–Voltage Characteristics The square-law control characteristic, in the MOSFET should be contrasted with the exponential control characteristic, of the BJT. Obviously, the latter is a much more sensitive relationship, with the result that can vary over a very wide range (five decades or more) within the same BJT. In the MOSFET, the range of achieved in the same device is much more limited. To appreciate this point further, consider the parabolic relationship between and and recall from our discus-sion above that is usually kept in a narrow range (0.1 V to 0.3 V).
Next we consider the effect of the device dimensions on its current. For the bipolar transistor, the control parameter is the area of the emitter–base junction (EBJ), which determines the scale current It can be varied over a relatively narrow range, such as 10 to 1. Thus, while the emitter area can be used to achieve current scaling in an IC (as we can see in Section 7.4 in connection with the design of current mirrors), its narrow range of variation reduces its significance as a design parameter. This is particularly so if we compare with its counterpart in the MOSFET, the aspect ratio W/L. MOSFET devices can be designed with W/L ratios in a wide range, such as 1.0 to 500. As a result, W/L is a very significant MOS Table 7.A.3 continued NMOS npn Capacitances Transition Frequency fT For Cgs Cgd and For Cπ Cμ and Cπ Cde, Design Parameters ID, VOV, L, IC, VBE, AE(or IS) Good Analog Switch?
Yes, because the device is symmetrical and thus the iD–vDS characteristics pass directly through the origin.
No, because the device is asymmetrical with an offset voltage VCEoff.
Cgs = 2 3 ---WLCox WLovCox + Cgd = WLovCox Cπ = Cde Cje + Cde = τFgm Cje 2Cje0 Cμ = Cμ0 1 VCB VC0 ----------+ m fT = gm 2π Cgs Cgd + ( ) -----------------------------------Cgs2 3 --WLCox, fT 1.5μnVOV 2πL2 ------------------------fT = gm 2π Cπ Cμ + ( ) -------------------------------fT 2μnVT 2πWB 2 ------------------W L -----Vt V BEon VBEon Vt V BCon VBEon Vt ( ).
(vDS, vCE) iD vGS – , iC vBE, – iC iD iD vOV, vOV AE, IS.
AE 560 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers design parameter. Like it is also used in current scaling, as we can see in Section 7.4.
Combining the possible range of variation of and W/L, one can design MOS transistors to operate over an range of four decades or so.
The channel-length modulation in the MOSFET and the base-width modulation in the BJT are similarly modeled and give rise to the dependence of on and, hence, to the finite output resistance in the active region. Two important differences, however, exist. In the BJT, is solely a process-technology parameter and does not depend on the dimensions of the BJT. In the MOSFET, the situation is quite different: , where is a process-technology parameter and L is the channel length used. Also, in modern deep submicron processes, is very low, resulting in values that are lower than the corresponding values for the BJT.
The last, and perhaps most important, difference between the current–voltage character-istics of the two devices concerns the input current into the control terminal: While at low frequencies the gate current of the MOSFET is practically zero and the input resistance looking into the gate is practically infinite, the BJT draws base current that is propor-tional to the collector current; that is, The finite base current and the correspond-ing finite input resistance looking into the base comprise a definite disadvantage of the BJT in comparison to the MOSFET. Indeed, it is the infinite input resistance of the MOSFET that has made possible analog and digital circuit applications that are not feasible with the BJT.
Examples include dynamic digital memory (Chapter 15) and switched-capacitor filters (Chapter 16).
AE, vOV iD iD iC ( ) vDS vCE ( ) ro V A V A = V A ′L VA ′ VA ′ V A iB iB = iC β ⁄ .
(a) For an NMOS transistor with W/L = 10 fabricated in the 0.18-μm process whose data are given in Table 7.A.1, find the values of and required to operate the device at μA. Ignore channel-length modulation.
(b) Find for an npn transistor fabricated in the low-voltage process specified in Table 7.A.2 and operated at μA. Ignore base-width modulation.
Solution (a) Substituting μA, W/L = 10, and, from Table 7.A.1, μA/V2 results in Thus, (b) Substituting μA and, from Table7.A.2, gives, V OV VGS ID 100 = VBE IC 100 = ID 1 2 --- μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞VOV 2 = ID 100 = μnCox 387 = 100 1 2 ---387 10 VOV 2 × × × = VOV 0.23 V = V GS = V tn V OV 0.5 0.23 0.73 V = + = + IC ISe VBE VT ⁄ = IC =100 IS 6 10 18 – × A = VBE 0.025 100 10 6 – × 6 10 18 – × ------------------------- = 0.76 V ln = Example 7.A.1 Appendix 7.A Comparison of the MOSFET and the BJT 561 Low-Frequency Small-Signal Models The low-frequency models for the two devices are very similar except, of course, for the finite base current (finite β) of the BJT, which gives rise to in the hybrid-π model and to the unequal emitter and collector currents in the T models Here it is interesting to note that the low-frequency, small-signal models become identical if one thinks of the MOSFET as a BJT with For both devices, the hybrid-π model indicates that the open-circuit voltage gain obtained from gate to drain (base to collector) with the source (emitter) grounded is It follows that is the maximum gain available from a single transistor of either type.
This important transistor parameter is given the name intrinsic gain and is denoted We will have more to say about the intrinsic gain shortly.
Although not included in the MOSFET low-frequency model shown in Table 7.A.3, the body effect can have some implications for the operation of the MOSFET as an amplifier. In simple terms, if the body (substrate) is not connected to the source, it can act as a second gate for the MOSFET. The voltage signal that develops between the body and the source, gives rise to a drain current component where the body transconductance is proportional to that is, where the factor is in the range of 0.1 to 0.2.
The body effect has no counterpart in the BJT.
The Transconductance For the BJT, the transconductance depends only on the dc collector current (Recall that is a physical constant 0.025 V at room temperature.) It is interesting to observe that does not depend on the geometry of the BJT, and its depen-dence on the EBJ area is only through the effect of the area on the total collector current Similarly, the dependence of on is only through the fact that determines the total current in the collector. By contrast, of the MOSFET depends on , and W/L.
Therefore, we use three different (but equivalent) formulas to express of the MOSFET. The first formula given in Table 7.A.3 for the MOSFET’s is the most directly compa-rable with the formula for the BJT. It indicates that for the same operating current, of the MOSFET is smaller than that of the BJT. This is because is the range of 0.05 V to 0.15 V, which is two to six times the corresponding term in the BJT’s formula, namely The second formula for the MOSFET’s indicates that for a given device (i.e., given W/L), is proportional to Thus a higher is obtained by operating the MOSFET at a higher overdrive voltage. However, we should recall the limitations imposed on the magnitude of by the limited value of Put differently, the need to obtain a reasonably high constrains the designer’s interest in reducing The third formula shows that for a given transistor (i.e., given W/L), is proportional to This should be contrasted with the bipolar case, where is directly proportional to Output Resistance The output resistance for both devices is determined by similar for-mulas, with being the ratio of to the bias current or Thus, for both transistors, 7.A.1 (a) For NMOS transistors fabricated in the 0.18-μm technology specified in Table 7.A.1, find the range of obtained for ranging from 0.2 V to 0.4 V and to 100. Neglect channel-length modulation. (b) If a similar range of current is required in an npn transistor fabricated in the low-voltage process specified in Table 7.A.2, find the corresponding change in its Ans. (a) μA and mA for a range of about 4000:1; (b) for varying over a 4000:1 range, ID VOV W/L 0.1 = V BE.
IDmin 0.8 = ΙDmax = 3.1 IC ΔVBE = 207 mV EXERCISE rπ α 1 < ( ).
β = ∞ α = 1 ( ).
gmro.
– gmro A0.
vbs, gmbvbs, gmb gm; gmb χgm, = χ gm IC.
VT gm IC.
gm VBE VBE gm ID, VOV gm gm gm VOV 2 ⁄ VT.
gm gm VOV.
gm V OV VDD.
gm V OV.
gm gm ID.
gm IC.
ro V A (ID IC).
562 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers is inversely proportional to the bias current. The difference in nature and magnitude of between the two devices has already been discussed.
Intrinsic Gain The intrinsic gain of the BJT is the ratio of , which is solely a pro-cess parameter (5 V to 100 V), and which is a physical parameter (0.025 V at room tem-perature). Thus of a BJT is independent of the device junction area and of the operating current, and its value ranges from 200 V/V to 5000 V/V. The situation in the MOSFET is very different: Table 7.A.3 provides three different (but equivalent) formulas for expressing the MOSFET’s intrinsic gain. The first formula is the one most directly comparable to that of the BJT. Here, however, we note the following: 1. The quantity in the denominator is which is a design parameter, and although it is becoming smaller in designs using short-channel technologies, it is still at least two to four times larger than Furthermore, as we have seen, there are reasons for selecting larger values for 2. The numerator quantity is both process- and device-dependent, and its value has been steadily decreasing. As a result, the intrinsic gain realized in a single MOSFET amplifier stage fabricated in a modern short-channel technology is only 20 V/V to 40 V/V, at least an order of magnitude lower than that for a BJT.
The third formula given for in Table 7.A.3 points out a very interesting fact: For a given process technology and and a given device (W/L), the intrinsic gain is inversely proportional to This is illustrated in Fig. 7.A.1, which shows a typical plot of versus the bias current The plot confirms that the gain increases as the bias current is lowered. The gain, however, levels off at very low currents. This is because the MOSFET enters the subthreshold region of operation (Section 5.1.9), where it becomes very much like a BJT with an exponential current–voltage characteristic. The intrinsic gain then becomes constant, just like that of a BJT. Note, however, that although a higher gain is achieved at lower bias currents, the price paid is a lower and less ability to drive capacitive loads and thus a decrease in bandwidth. This point will be further illustrated shortly.
Figure 7.A.1 The intrinsic gain of the MOSFET versus bias current ID. Outside the subthreshold region, this is a plot of for the case: μnCox = 20 μA/V2, L = 2 μm, and W = 20 μm.
ro V A A0 VA VT, A0 VOV 2, ⁄ VT.
VOV.
VA A0 ( VA ′ μnCox) ID.
A0 ID.
gm A0 (log scale) 1000 100 10 1 106 105 104 103 10 2 Slope 1 2 Strong inversion region Subthreshold region (A) ID (log scale) A0 VA ′ 2μnCoxWL/ID = VA ′ = 20 V/μm, Appendix 7.A Comparison of the MOSFET and the BJT 563 We wish to compare the values of input resistance at the gate (base), and for an NMOS tran-sistor fabricated in the 0.25-μm technology specified in Table 7.A.1 and an npn transistor fabricated in the low-voltage technology specified in Table 7.A.2. Assume both devices are operating at a drain (collec-tor) current of 100 μA. For the MOSFET, let L = 0.4 μm and W = 4 μm, and specify the required Solution For the NMOS transistor, Thus, For the npn transistor, gm, ro, A0 V OV.
ID 1 2 --- μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞V OV 2 = 100 1 2 --- × 267 × 4 0.4 ------- × VOV 2 = V OV 0.27 V = gm 2 μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ID = 2 × 267 × 10 × 100 0.73 mA/V = = Rin ∞ = ro VA ′ L ID ----------- 5 0.4 × 0.1 ---------------- 20 kΩ = = = A0 gmro 0.73 × 20 = 14.6 V/V = = gm IC VT ------ 0.1 mA 0.025 V ------------------- 4 mA/V = = = Rin rπ β0 gm ⁄ 100 4 mA/V ------------------- 25 kΩ = = = = ro V A IC ------ 35 0.1 mA ------------------ 350 kΩ = = = A0 gmro 4 × 350 1400 V/V = = = Example 7.A.2 7.A.2 For an NMOS transistor fabricated in the 0.5-μm process specified in Table 7.A.1 with L = 0.5 μm, find the transconductance and the intrinsic gain obtained at μA, 100 μA, and 1 mA.
Ans. 0.2 mA/V, 200 V/V; 0.6 mA/V, 62 V/V; 2 mA/V, 20 V/V ID = 10 EXERCISE 564 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers High-Frequency Operation The simplified high-frequency equivalent circuits for the MOSFET and the BJT are very similar, and so are the formulas for determining their unity-gain frequency (also called transition frequency) fT. As we shall demonstrate in Chapter 9, fT is a measure of the intrinsic bandwidth of the transistor itself and does not take into account the effects of capacitive loads. We address the issue of capacitive loads shortly.
For the time being, note the striking similarity between the approximate formulas given in Table 7.A.3 for the value of fT of the two devices. In both cases fT is inversely proportional to the square of the critical dimension of the device: the channel length for the MOSFET and the base width for the BJT. These formulas also clearly indicate that shorter-channel MOSFETs10 and narrower-base BJTs are inherently capable of a wider bandwidth of operation. It is also important to note that while for the BJT the approximate expression for fT indicates that it is entirely process determined, the corresponding expression for the MOSFET shows that is proportional to the overdrive voltage Thus we have conflicting requirements on While a higher low-frequency gain is achieved by operating at a low wider bandwidth requires an increase in Therefore the selection of a value for involves, among other considerations, a trade-off between gain and bandwidth.
For npn transistors fabricated in the modern low-voltage process, fT is in the range of 10 GHz to 20 GHz as compared to the 400 MHz to 600 MHz obtained with the standard high-voltage process. In the MOS case, NMOS transistors fabricated in a modern submicron technology, such as the 0.18-μm process, achieve fT values in the range of 5 GHz to 15 GHz.
Before leaving the subject of high-frequency operation, let’s look into the effect of a capacitive load on the bandwidth of the common-source (common-emitter) amplifier. For this purpose we shall assume that the frequencies of interest are much lower than fT of the transistor. Hence we shall not take the transistor capacitances into account. Figure 7.A.2(a) shows a common-source amplifier with a capacitive load The voltage gain from gate to drain can be found as follows: (7.A.1) Thus the gain has, as expected, a low-frequency value of and a frequency response of the single-time-constant (STC) low-pass type with a break (pole) frequency at (7.A.2) Obviously this pole is formed by and A sketch of the magnitude of gain versus fre-quency is shown in Fig. 7.A.2(b). We observe that the gain crosses the 0-dB line at frequency 10Although the reason is beyond our capabilities at this stage, fT of MOSFETs that have very short chan-nels varies inversely with L rather than with L2.
fT V OV.
V OV: V OV, V OV.
VOV CL.
V o gmV gs ro CL || ( ) – = gmV gs ro 1 sCL --------ro 1 sCL --------+ -------------------– = Av Vo Vgs ------- gmro 1 sCLro + -----------------------– = = gmro A0 = ωP 1 CLro -----------= ro CL.
ωt, ωt A0ωP gmro ( ) 1 CLro -----------= = Appendix 7.A Comparison of the MOSFET and the BJT 565 Thus, (7.A.3) That is, the unity-gain frequency or, equivalently, the gain–bandwidth product11 is the ratio of and We thus clearly see that for a given capacitive load a larger gain–bandwidth product is achieved by operating the MOSFET at a higher Identical analysis and conclusions apply to the case of the BJT. In each case, bandwidth increases as bias current is increased.
Design Parameters For the BJT there are three design parameters— and (or, equivalently, the area of the emitter–base junction)—and the designer can select any two. However, since is exponentially related to and is very sensitive to the Figure 7.A.2 Frequency response of a CS amplifier loaded with a capacitance CL and fed with an ideal voltage source. It is assumed that the transistor is operating at frequencies much lower than fT, and thus the internal capacitances are not taken into account.
11The unity-gain frequency and the gain–bandwidth product of an amplifier are the same when the frequency response is of the single-pole type; otherwise the two parameters may differ.
(a) Vo Vgs CL D S G ro gmVgs (b) 20 dBdecade 3 dB 0 20 log A0 frequency (log scale) ft 2pCL gm fP 2pCLro 1 f3dB Vo Vgs (dB) ωt gm CL ------= ωt gm CL.
CL, gm.
IC, VBE, IS IC VBE 566 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers value of changes by only 60 mV for a factor of 10 change in is much more useful than as a design parameter. As mentioned earlier, the utility of the EBJ area as a design parameter is rather limited because of the narrow range over which can vary. It follows that for the BJT there is only one effective design parameter: the collector current Finally, note that we have not considered to be a design parameter, since its effect on is only secondary. Of course, as we learned in Chapter 6, affects the output-signal swing.
For the MOSFET there are four design parameters— L, and W—and the designer can select any three. For analog circuit applications the trade-off in selecting a value for L is between the higher speed of operation (wider amplifier bandwidth) obtained at lower values of L and the higher intrinsic gain obtained at larger values of L. Usually one selects an L of about 25% to 50% greater than The second design parameter is We have already made numerous remarks about the effect of the value of on performance. Usually, for submicron technologies, is selected in the range of 0.1 V to 0.3 V.
Once values for L and have been selected, the designer is left with the selection of the value of or W (or, equivalently, W/L). For a given process and for the selected values of L and is proportional to W/L. It is important to note that the choice of or, equivalently, of W/L has no bearing on the value of intrinsic gain and the tran-sition frequency fT . However, it affects the value of and hence the gain–bandwidth product. Figure 7.A.3 illustrates this point by showing how the gain of a common-source amplifier operated at a constant varies with (or, equivalently, W/L). Note that while the dc gain remains unchanged, increasing W/L and, correspondingly, , increases the bandwidth proportionally. This, however, assumes that the load capacitance is not affected by the device size, an assumption that may not be entirely justified in some cases.
Figure 7.A.3 Increasing ID or W/L increases the bandwidth of a MOSFET amplifier operated at a constant VOV and loaded by a constant capacitance CL.
VBE (VBE IC), IC VBE AE IC.
VCE IC VCE ID, VOV, Lmin.
VOV.
VOV VOV VOV ID VOV, ID ID A0 gm VOV ID ID CL 20 log A0 f (log scale) ft 2CL gm f3dB 2CLro 1 Gain (dB) ID and W L 0 Appendix 7.A Comparison of the MOSFET and the BJT 567 In this example we investigate the gain and the high-frequency response of an npn transistor and an NMOS transistor. For the npn transistor, assume that it is fabricated in the low-voltage process specified in Table 7.A.2, and assume that For μA, 100 μA, and 1 mA, find and Also, for each value of find the gain–bandwidth product ft of a common-emitter amplifier loaded by a 1-pF capacitance, neglecting the internal capacitances of the transistor. For the NMOS transistor, assume that it is fabricated in the 0.25-μm CMOS process with L = 0.4 μm. Let the transistor be operated at Find W/L that is required to obtain μA, 100 μA, and 1 mA. At each value of find and Also, for each value of determine the gain–bandwidth product ft of a common-source amplifier loaded by a 1-pF capacitance, neglecting the internal capacitances of the transistor.
Solution For the npn transistor, A/V V/V fF fF We thus obtain the following results: For the NMOS transistor, ro (k
) 10 μA 100 μA 1 mA 0.4 4 40 3500 350 35 1400 1400 1400 4 40 400 10 10 10 14 50 410 5 5 5 3.4 11.6 15.3 64 640 6400 CμCμ0.
IC = 10 gm, ro, A0, Cde, Cje, Cπ, Cμ, fT.
IC, VOV = 0.25 V.
ID 10 = ID, gm, ro, A0, Cgs, Cgd, fT.
ID, gm IC V T ------ IC 0.025 ------------- 40IC = = = ro VA IC ------ 35 IC ------ Ω = = A0 V A V T ------ 35 0.025 ------------- 1400 = = = Cde τFgm 10 10 12 – × 40IC 0.4 10 9 – × = × IC F = = Cje 2Cje0 = 10 Cπ Cde Cje + = Cμ Cμ0 5 = fT gm 2π Cπ Cμ + ( ) -------------------------------= ft gm 2πCL ------------- gm 2π × 1 × 10 12 – ------------------------------------= = IC gm (mA/V) A0 (V/V) Cde (f F) Cje (f F) Cπ (f F) Cμ (f F) fT (GHz) ft (MHz) ID 1 2 ---μnCox W L -----VOV 2 = 1 2 ---267 W L -----× × 1 16 ------× = Example 7.A.3 568 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.A.4 Combining MOS and Bipolar Transistors—BiCMOS Circuits From the discussion above it should be evident that the BJT has the advantage over the MOSFET of a much higher transconductance at the same value of dc bias current.
Thus, in addition to realizing higher voltage gains per amplifier stage, bipolar transistor amplifiers have superior high-frequency performance compared to their MOS counterparts.
On the other hand, the practically infinite input resistance at the gate of a MOSFET makes it possible to design amplifiers with extremely high input resistances and an almost zero input bias current. Also, as mentioned earlier, the MOSFET provides an excellent Example 7.A.3 continued Thus, A/V V/V We thus obtain the following results: W/L ro (k
) 10 μA 100 μA 1 mA 1.2 12 120 0.08 0.8 8 200 20 2 16 16 16 1.03 10.3 103 0.29 2.9 29 9.7 9.7 9.7 12.7 127 1270 W L ----- 0.12ID = gm ID VOV 2 ⁄ ---------------- ID 0.25 2 ⁄ ----------------- 8ID = = = ro VA ′ L ID ----------- 5 0.4 × ID ---------------- 2 ID ----- Ω = = = A0 gmro =16 = Cgs 2 3 ---WLCox Cov 2 3 ---W 0.4 5.8 0.6W + × × = + = Cgd = Cov = 0.6W fT = gm 2π Cgs Cgd + ( ) -----------------------------------ft = gm 2πCL -------------ID gm (mA/V) A0 (V/V) Cgs (fF) Cgd (fF) fT (GHz) ft (MHz) 7.A.3 Find , and fT for an NMOS transistor fabricated in the 0.5-μm CMOS technology specified in Table 7.A.1. Let L = 0.5 μm, W = 5 μm, and Ans. 85.5 μA; 0.57 mA/V; 66.7 kΩ; 38 V/V; 8.3 fF; 2 fF; 8.8 GHz ID, gm, ro, A0, Cgs, Cgd VOV 0.3 V.
= EXERCISE gm ( ) Appendix 7.A Comparison of the MOSFET and the BJT 569 PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multism simu-lations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 7.2: The Basic Gain Cell 7.1 Find , , , and for the CE amplifier of Fig.
7.1(b) when operated at I = 10 μA, 100 μA, and 1 mA. Assume and remains constant as I is varied, and that V. Present your results in a table.
7.2 Consider the CE amplifiers of Fig. 7.1(b) for the case of I = 1 mA, , and V. Find and If it is required to raise by a factor of 4 by changing I, what value of I is required, assuming that remains unchanged? What are the new values of and If the amplifier is fed with a signal source having k and is connected to a load of 100-k resistance, find the overall voltage gain, 7.3 Find the intrinsic gain of an NMOS transistor fabricated in a process for which μA/V2 and V μm.
The transistor has a 0.5-μm channel length and is operated at V. If a 2-mA/V transconductance is required, what must and W be?
gm rπ ro A0 β 100 = VA 10 = β 100 = VA 100 = Rin, Avo, Ro.
Rin β Avo Ro?
Rsig 5 = Ω Ω vo v ⁄ sig.
k′ n 200 = V′ A 20 = VOV 0.25 = ID implementation of a switch, a fact that has made CMOS technology capable of realizing a host of analog circuit functions that are not possible with bipolar transistors.
It can thus be seen that each of the two transistor types has its own distinct and unique advantages: Bipolar technology has been extremely useful in the design of very-high-quality general-purpose circuit building blocks, such as op amps. On the other hand, CMOS, with its very high packing density and its suitability for both digital and analog circuits, has become the technology of choice for the implementation of very-large-scale integrated circuits. Neverthe-less, the performance of CMOS circuits can be improved if the designer has available (on the same chip) bipolar transistors that can be employed in functions that require their high and excellent current-driving capability. A technology that allows the fabrication of high-quality bipolar transistors on the same chip as CMOS circuits is aptly called BiCMOS. At appropriate locations throughout this book we present interesting and useful BiCMOS circuit blocks.
7.A.5 Validity of the Square-Law MOSFET Model We conclude this appendix with a comment on the validity of the simple square-law model we have been using to describe the operation of the MOS transistor. While this simple model works well for devices with relatively long channels (>1 μm), it does not provide an accurate representation of the operation of short-channel devices. This is because a number of physical phenomena come into play in these submicron devices, resulting in what are called short-channel effects. Although a detailed study of short-channel effects is beyond the scope of this book, it should be mentioned that MOSFET models have been developed that take these effects into account. However, they are understandably quite complex and do not lend themselves to hand analysis of the type needed to develop insight into circuit oper-ation. Rather, these models are suitable for computer simulation and are indeed used in SPICE (Appendix B). For quick, manual analysis, however, we will continue to use the square-law model, which is the basis for the comparison of Table 7.A.3.
gm CHAPTER 7 PR OBLE MS 570 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.4 An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 80 V/V when operated at an of 100 μA. Find the intrinsic gain for μA and μA. For each of these currents, find the factor by which changes from its value at μA.
D 7.5 Consider an NMOS transistor fabricated in a 0.18-μm technology for which μA/V2 and V/μm.
It is required to obtain an intrinsic gain of 25 V/V and a of 1 mA/V. Using V, find the required values of L, W/L, and the bias current I. D 7.6 Sketch the circuit for a current-source-loaded CS amplifier that uses a PMOS transistor for the amplifying device. Assume the availability of a single -V dc supply.
If the transistor is operated with V, what is the highest instantaneous voltage allowed at the drain?
D 7.7 An NMOS transistor is fabricated in the 0.18-μm pro-cess whose parameters are given in Table 7.A.1 on page 554.
The device has a channel length twice the minimum and is operated at V and μA.
(a) What values of and are obtained?
(b) If is increased to 100 μA, what do and become?
(c) If the device is redesigned with a new value of W so that it operates at V for μA, what do , , and become?
(d) If the redesigned device in (c) is operated at 10 μA, find and (e) Which designs and operating conditions produce the lowest and highest values of ? What are these values? In each of these two cases, if W/L is held at the same value but L is made 10 times larger, what gains result?
D 7.8 Find for an NMOS transistor fabricated in a CMOS process for which 200 μA/V2 and V/μm.
The transistor has a 0.4-μm channel length and is operated with an overdrive voltage of 0.25 V. What must W be for the NMOS transistor to operate at μA? Also, find the values of and . Repeat for L = 0.8 μm.
D 7.9 Using a CMOS technology for which μA/V2 and V/μm, design a current-source-loaded CS ampli-fier for operation at I = 50 μA with V. The ampli-fier is to have an open-circuit voltage gain of V/V.
Assume that the current-source load is ideal. Specify L and W/L. D 7.10 The circuit in Fig. 7.3(a) is fabricated in a process for which μA/V2, 20 V/μm, V, and V. The two transistors have L = 0.5 μm and are to be operated at μA and V. Find the required values of , , and D 7.11 The circuit in Fig. 7.3(a) is fabricated in a 0.18-μm CMOS technology for which μA/V2, μA/V2, V, V/μm, V/μm, and V. It is required to design the circuit to obtain a voltage gain V/V. Use devices of equal length L operating at I = 100 μA and V.
Determine the required values of L, , and .
7.12 Figure P7.12 shows an IC MOS amplifier formed by cascading two common-source stages. Assuming that and that the biasing current sources have output resistances equal to those of and find an expression for the overall voltage gain in terms of and of and 7.13 The NMOS transistor in the circuit of Fig. P7.13 has V, mA/V2, and V.
(a) Neglecting the dc current in the feedback network and the effect of find Then find the dc current in the feedback network and Verify that you were justified in neglecting the current in the feedback network when you found .
ID ID 25 = ID 400 = gm ID 100 = k′ n 387 = V′ A 5 = gm VOV 0.2 = +1.8 VOV 0.3 = VOV 0.25 = ID 10 = gm, ro, A0 ID VOV, gm, ro, A0 VOV 0.25 = ID 100 = gm ro A0 VOV, gm, ro, A0.
A0 A0 k′ n = V′ A 20 = ID 100 = gm r o k′ n 200 = V′ A 20 = VOV 0.2 = 100 – μnCox 2μpC ox 200 = = V′ An V′ Ap = = Vtn V tp 0.5 = – = VDD 2.5 = ID 100 = VOV 0.3 = VG, W L ⁄ ( )1 W L ⁄ ( )2 Av.
μnCox 387 = μpCox 86 = Vtn Vtp 0.5 = – = V′ An 5 = V′ Ap 6 = V DD 1.8 = Av 40 – = VOV 0.2 = VG, W L ⁄ ( )1 W L ⁄ ( )2 V An V Ap = Q1 Q2, gm ro Q1 Q2.
Figure P7.12 Vt 0.5 = k′ n W L ⁄ 2 = V A 20 = 2 M vo vi 200 A 3 M Rin Figure P7.13 ro, VGS.
VDS.
VGS Problems 571 CHAPTER 7 PR OBLE MS (b) Find the small-signal voltage gain, vo/vi. What is the peak of the largest output sinewave signal that is possible while the NMOS transistor remains in saturation? What is the corre-sponding input signal? (c) Find the small-signal input resistance D 7.14 Consider the CMOS amplifier of Fig. 7.4(a) when fabricated with a process for which and Find and to obtain a voltage gain of −40 V/V and an output resistance of 100 kΩ. If Q2 and Q3 are to be operated at the same overdrive voltage as Q1, what must their W/L ratios be?
7.15 Consider the CMOS amplifier analyzed in Example 7.3. If consists of a dc bias component on which is super-imposed a sinusoidal signal, find the value of the dc component that will result in the maximum possible signal swing at the output with almost-linear operation. What is the amplitude of the output sinusoid resulting? (Note: In practice, the amplifier would have a feedback circuit that causes it to operate at a point near the middle of its linear region.) 7.16 The power supply of the CMOS amplifier analyzed in Example 7.3 is increased to 5 V. What will the extent of the lin-ear region at the output become?
7.17 Consider the circuit shown in Fig. 7.4(a), using a 3.3-V supply and transistors for which and L = 1 μm. For Q1, and W = 20 μm. For Q2 and Q3, and For Q2, W = 40 μm. For Q3, W = 10 μm.
(a) If Q1 is to be biased at 100 μA, find For simplic-ity, ignore the effect of (b) What are the extreme values of for which Q1 and Q2 just remain in saturation?
(c) What is the large-signal voltage gain?
(d) Find the slope of the transfer characteristic at (e) For operation as a small-signal amplifier around a bias point at find the small-signal voltage gain and output resistance.
7.18 The MOSFETs in the circuit of Fig. P7.18 are matched, having and The resistance (a) For G and D open, what are the drain currents and (b) For what is the voltage gain of the amplifier from G to D? [Hint: Replace the transistors with their small-signal models.] (c) For finite what is the voltage gain from G to D and the input resistance at G?
(d) If G is driven (through a large coupling capacitor) from a source having a resistance of 100 kΩ, find the voltage gain (e) For what range of output signals do Q1 and Q2 remain in the saturation region? 7.19 Transistor Q1 in the circuit of Fig. P7.19 is operating as a CE amplifier with an active load provided by transistor Q2, which is the output transistor in a current mirror formed by Q2 and Q3. (Note that the biasing arrangement for Q1 is not shown.) (a) Neglecting the finite base currents of Q2 and Q3 and assuming that their and that Q2 has five times the area of Q3, find the value of I.
(b) If Q1 and Q2 are specified to have find and and hence the total resistance at the collector of Q1.
(c) Find and assuming that (d) Find and Rin.
kn ′ = 2.5kp ′ = 250 μA/V 2, Vt = 0.6 V, VA = 10 V.
IREF W L ⁄ ( )1 vI Vt = 0.8 V kn ′ = 100 μA/V 2 , VA = 100 V, kp ′ = 50 μA/V 2 VA = 50 V.
I REF.
VA.
vO vO = VDD 2.
⁄ vO = VDD 2, ⁄ kn ′ W L ⁄ ( )1 = kp ′ W L ⁄ ( )2 = 1 mA/V 2 Vt = 0.5 V.
R = 1 MΩ.
ID1 ID2?
ro = ∞, ro( VA = 20 V), vsig vd vsig ⁄ .
G D R Q1 Q2 1.5 V 1.5 V Figure P7.18 vo vi Q1 Q2 Q3 I 23 k 3 V VCC 3 V Figure P7.19 VBE 0.7 V VA = 50 V, ro1 ro2 rπ1 gm1 β1 = 50.
Rin, Av, Ro.
CHAPTER 7 PR OBLE MS 572 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers D 7.20 It is required to design the CMOS amplifier of Fig.
7.4(a) utilizing a 0.18-μm process for which μA/V2, μA/V2, V, V, V/μm, and V/μm. The output voltage must be able to swing to within approximately 0.2 V of the power-supply rails (i.e., from 0.2 V to 1.6 V) and the voltage gain must be at least 10 V/V. Design for a dc bias current of 50 μA, and use devices with the same channel length. If the channel length is an integer multiple of the minimum 0.18 μm, what channel length is needed and what W/L ratios are required? If it is required to raise the gain by a factor of 2, what channel length would be required, and by what factor does the total gate area of the circuit increase?
Section 7.3: The Cascode Amplifier D 7.21 In a MOS cascode amplifier, the cascode transistor is required to raise the output resistance by a factor of 40. If the transistor is operated at V, what must its be? If the process technology specifies as 5 V/μm, what channel length must the transistor have?
D 7.22 For a cascode current source such as that in Fig. 7.10, show that if the two transistors are identical, the current I sup-plied by the current source and the output resistance are related by . Now consider the case of transistors that have V and are operated at of 0.2 V. Also, let μA/V2. Find the W/L ratios required and the output resistance realized for the two cases: (a) I = 0.1 mA and (b) I = 0.5 mA. Assume that for the two devices is the minimum required (i.e., ).
D 7.23 For a cascode current source, such as that in Fig.
7.10, show that if the two transistors are identical, the current I supplied by the current source and the output resistance are related by Now consider the case of a 0.18-μm technology for which V/μm and let the transistors be operated at V. Find the figure-of-merit for the three cases of L equal to the minimum channel length, twice the min-imum, and three times the minimum. Complete the entries of the table at the bottom of the page. Give W/L and the area 2WL in terms of n. In the table, Av denotes the gain obtained in a cas-code amplifier such as that in Fig. 7.11 that utilizes our current source as load and which has the same values of gm and Ro as the current-source transistors.
(a) For each current value, what is price paid for the increase in and obtained as L is increased? (b) For each value of L, what advantage is obtained as I is increased, and what is the price paid? (c) Contrast the performance obtained from the circuit with the largest area with that obtained from the circuit with the smallest area.
D 7.24 Design the cascode amplifier of Fig. 7.9(a) to obtain mA/V and k . Use a 0.18-μm technol-ogy for which V, V/μm and μA/V2. Determine L, W/L, , and I. Use identical transistors operated at V, and design for the maximum possi-ble negative signal swing at the output. What is the value of the minimum permitted output voltage?
7.25 The cascode amplifier of Fig. 7.11 is operated at a cur-rent of 0.1 mA with all devices operating at V.
k′ n 387 = k′ p 86 = Vtn Vtp 0.5 = – = V DD 1.8 = V′ An 5 = V′ Ap 6 – = V OV 0.2 = V A V′ A Ro IRo 2 VA 2 VOV ⁄ = VA 4 = VOV μpC ox 100 = VSD VOV Ro IRo 2 V′ A 2 VOV ----------------L2 = V′ A 5 = VOV 0.2 = IRo Ro Av (mA/V) (k ) (V/V) 2WL (mA/V) (k ) (V/V) 2WL (mA/V) (k ) (V/V) 2WL I = 0.01 mA W/L = n I = 0.1 mA W/L = I = 1.0 mA W/L = L Lmin 0.18 μm = = IRo V = L 2Lmin 0.36 μm = = IRo V = L 3Lmin 0.54 μm = = IRo V = gm Ro Ω Av μm2 ( ) gm Ro Ω Av μm2 ( ) gm Ro Ω Av μm2 ( ) gm1 1 = Ro 400 = Ω Vtn 0.5 = V′ A 5 = k′ n 400 = VG2 VOV 0.2 = VOV 0.25 = Problems 573 CHAPTER 7 PR OBLE MS All devices have V. Find the output resistance of the amplifier, the output resistance of the current source, the overall output resistance, and the voltage gain, D 7.26 Design the CMOS cascode amplifier in Fig. 7.11 for the following specifications: mA/V and V/V. Assume that for the available fabrication process, V/μm for both NMOS and PMOS devices and that μA/V2. Use the same channel length L for all devices and operate all four devices at V. Determine the required channel length L, the bias current I, and the W/L ratio for each of four transistors.
Assume that suitable bias voltages have been chosen, and neglect the Early effect in determining the W/L ratios.
D 7.27 Design the circuit of Fig. 7.10 to provide an output current of 100 μA. Use and assume the PMOS transistors to have and The current source is to have the widest possible signal swing at its output. Design for and spec-ify the values of the transistor W/L ratios and of VG3 and VG4.
What is the highest allowable voltage at the output? What is the value of Ro?
7.28 The cascode transistor can be thought of as providing a “shield” for the input transistor from the voltage variations at the output. To quantify this “shielding” property of the cascode, consider the situation in Fig. P7.28. Here we have grounded the input terminal (i.e., reduced vi to zero), applied a small change vx to the output node, and denoted the voltage change that results at the drain of Q1 by vy . By what factor is vy smaller than vx?
7.29 In this problem we investigate whether, as an alterna-tive to cascoding, we can simply increase the channel length L of the CS MOSFET. Specifically, we wish to compare the two circuits shown in Fig. P7.29(b) and (c). The circuit in Fig.
P7.29(b) is a CS amplifier in which the channel length has been quadrupled relative to that of the original CS amplifier in Fig. P7.29(a) while the drain bias current has been kept constant.
(a) Show that for this circuit is double that of the origi-nal circuit, gm is half that of the original circuit, and A0 is double that of the original circuit.
(b) Compare these values to those of the cascode circuit in Fig. P7.29(c), which is operating at the same bias current and has the same minimum voltage requirement at the drain as in the circuit of Fig. P7.29(b).
7.30 Consider the cascode amplifier of Fig. 7.11 with the dc component at the input V, V, V, V, and V. If all devices are matched, that is , and have equal of 0.5 V, what is the overdrive voltage at which the four transistors are operating? What is the allowable voltage range at the output?
7.31 Figure P7.31 shows a CG transistor fed with a signal source (vsig, Rsig) and loaded with a resistance (a) Find (b) Noting that the current through is equal to the input cur-rent i, find an expression for the overall voltage gain .
(c) Determine the values of and for the case of k and k VA 4 = gm1, Ron, Rop, Ro, Av.
gm1 2 = Av 200 – = V′ A 5 = μnC ox 4 = μpC ox 400 = VOV 0.2 = VDD = 3.3 V, μpCox = 60 μA/V 2, Vtp = 0.8 V – , VA = 5 V.
VOV = 0.2 V, vy Q2 Q1 vx ix Figure P7.28 (a) vo vi I WL Figure P7.29 (c) vo VBIAS WL vi WL I (b) vo vi W4L I V OV VI 0.8 = VG2 1.2 = VG3 1.3 = VG4 1.7 = VDD 2.5 = kn1 kn2 kp3 kp4 = = = Vt RL.
Rin.
RL v o v sig ⁄ Rin v o vsig ⁄ RL r o 10 = = Ω, A0 20, = Rsig 1 = Ω.
CHAPTER 7 PR OBLE MS 574 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers 7.32 The CG transistor in Fig. P7.31 can be replaced by an equivalent circuit consisting of a controlled-source and an output resistance as shown in Fig. P7.32. Here is the short-circuit transconductance. Its value can be determined by short-circuiting d to ground, finding the value of i, and dividing it by The value of is that of a CG transistor with a resistance in its source (Refer to Fig.
7.13).
(a) Find expressions for and (b) For the case k , and k find and 7.33 A CMOS cascode amplifier has identical CS and CG transistors that have W/L = 5.4 μm/0.36 μm and biased at I = 0.2 mA. The fabrication process has , μA/V2, and = 5 V/μm. At what value of does the gain become –100 V/V? What is the voltage gain of the common-source stage?
7.34 The purpose of this problem is to investigate the signal currents and voltages at various points throughout a cascode amplifier circuit. Knowledge of this signal distribution is very useful in designing the circuit so as to allow for the required signal swings. Figure P7.34 shows a CMOS cascode amplifier with all dc voltages replaced with signal grounds. As well, we have explicitly shown the resistance of each of the four tran-sistors. For simplicity, we are assuming that the four transistors have the same and The amplifier is fed with a signal (a) Determine R1, R2, and R3.
(b) Determine , , and all in terms of .
(c) Determine v1, v2, and v3, all in terms of vi.
(d) If is a 5-mV peak sine wave and , sketch and clearly label the waveforms of , and .
Q RL vsig Rsig Rin vo i i d Figure P7.31 Gmvsig Ro, Gm vsig.
Ro Rsig Gm Ro.
RL ro 10 = = Ω, gmr o 20 = Rsig 1 = Ω, Gm, Ro, vo vsig ⁄ .
Ro RL Gmvsig vo d Figure P7.32 μnCox 4 = μpCox 400 = V′ A RL ro gm ro.
vi.
i1 i2, i3, i4, i5 i6, i7, vi vi gmro 20 = v1 v2, v3 ro Q4 ro Q3 ro Q2 ro Q1 vi v1 v3 R1 R2 R3 i7 i6 i5 i1 i2 i3 v2 i4 Figure P7.34 Problems 575 CHAPTER 7 PR OBLE MS 7.35 Figure P7.35 shows a CS amplifier with a resistance in the source lead and with the drain short-circuited to ground.
Determine the short-circuit transconductance Hence pro-vide the output equivalent circuit of the source-degenerated CS amplifier, and show that the open-circuit voltage gain 7.36 A CS amplifier operating with a of 2 mA/V and having k has a 2-k resistance connected in its source lead. Find the output resistance Recalling that the open-circuit voltage gain remains unchanged at find the gain obtained with k D 7.37 Design the double-cascode current source shown in Fig. P7.37 to provide I = 0.1 mA and the largest possible signal swing at the output; that is, design for the minimum allowable voltage across each transistor. The 0.18-μm CMOS fabrication process available has V, V/μm, and μA/V2. Use devices with L = 0.5 μm, and oper-ate at V. Specify , and the W/L ratios of the transistors. What is the value of achieved?
7.38 Figure P7.38 shows a folded-cascode CMOS amplifier utilizing a simple current source supplying a current 2I, and a cascoded current-source ( ) supplying a current I.
Assume, for simplicity, that all transistors have equal parame-ters and (a) Give approximate expressions for all the resistances indicated.
(b) Find the amplifier output resistance (c) Show that the short-circuit transconductance is approximately equal to (d) Find the overall voltage gain and evaluate its value for the case mA/V and 7.39 A cascode current source formed of two pnp transis-tors for which and V supplies a current of 0.5 mA. What is the output resistance?
7.40 Use Eq. (7.45) to show that for a BJT cascode current source utilizing identical pnp transistors and supplying a cur-rent I, Rs Gm.
Avo A – 0.
= vi io Rs Figure P7.35 gm ro 20 = Ω Ω Rs Ro.
A0, RL 100 = Ω.
Vtp 0.5 – = V′ A 6 – = μpCox 100 = VOV 0.2 = VG1 VG2, VG3, Ro Q2, Q4, Q5 gm ro.
Ro.
Gm gm1.
vo vi ⁄ gm1 2 = A0 20.
= β 50 = VA 5 = Q1 Q2 Q3 Ro VG1 VDD 1.8 V VG2 VG3 I Figure P7.37 Q2 Q3 Q5 Q4 Q1 VG2 VG3 VDD vi VG4 VG5 Ro1 Rin3 Ro2 Ro4 Ro Ro5 Ro3 vo Figure P7.38 IRo VA VT VA ⁄ ( ) 1 β ⁄ ( ) + --------------------------------------------= CHAPTER 7 PR OBLE MS 576 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers Evaluate the figure-of-merit for the case V and Now find for the cases of I = 0.1, 0.5, and 1.0 mA.
7.41 Consider the BJT cascode amplifier of Fig. 7.19 for the case all transistors have equal and Show that the voltage gain can be expressed in the form Evaluate for the case V and Note that except for the fact that depends on I as a second-order effect, the gain is independent of the bias current I! 7.42 A bipolar cascode amplifier has a current-source load with an output resistance Let , V, and I = 0.1 mA. Find the voltage gain 7.43 Find the value of the resistance which, when con-nected in the emitter lead of a CE BJT amplifier, raises the out-put resistance by a factor of (a) 5, (b) 10, and (c) 50. What is the maximum possible factor by which the output resistance can be raised, and at what value of is it achieved? Assume the BJT has and is biased at mA.
7.44 Consider the CE amplifier with an emitter-degeneration resistance shown in Fig. P7.44(a). It is required to represent the output circuit of the amplifier with the equivalent circuit shown in Fig. P7.44(b). Here is the open-circuit voltage gain and is the output resistance (given by Eq. 7.50). Replace the BJT with its hybrid- model, set (i.e., open-circuit the collector), and show that Now, use this result to find the overall short-circuit transcon-ductance (see Fig. P7.44c) and show that State clearly all the approximations you made to arrive at this expression for For a BJT with and k biased at mA and having a resistance in its emitter, find and Also calculate the voltage gain obtained with k D 7.45 Figure P7.45 shows four possible realizations of the folded cascode amplifier. Assume that the BJTs have and that both the BJTs and the MOSFETs have V. Let I = 100 μA, and assume that the MOSFETs are operating at V. Assume the current sources are ideal. For each circuit determine, and Comment on your results.
Section 7.4: IC Biasing—Current Sources, Cur-rent Mirrors, and Current-Steering Circuits D 7.46 For and using it is required to design the circuit of Fig. 7.22 to obtain an output current whose nominal value is 100 μA. Find R if Q1 and Q2 are matched with channel lengths of 0.5 μm, channel widths of 4 μm, and What is the lowest possible value of VO? Assuming that for this process technol-ogy the Early voltage V/μm, find the output resis-tance of the current source. Also, find the change in output current resulting from a +0.5-V change in VO.
D 7.47 Using and a pair of matched MOS-FETs, design the current-source circuit of Fig. 7.22 to provide IRo VA 5 = β 50.
= Ro β ro.
Av Av 1 2 ---VA VT ⁄ VT VA ⁄ ( ) 1 β ⁄ ( ) + ---------------------------------------------– = Av VA 5 = β 50.
= β βro.
β 100 = VA 100 = Av.
Re, Re β 100 = IC 0.5 = Re, Avo vo vi ⁄ [ ]RL ∞ = , Ro π RL ∞ = Avo gmro – = 1 Re βro ⁄ – 1 Re rπ ⁄ + ---------------------------Gm Gm gm 1 gmRe + ---------------------Gm.
β 100 = ro 100 = Ω IC 0.2 = Re 250 Ω = Ro, Avo, Gm.
Av RL 10 = Ω.
β 100 = VA 5 = VOV 0.2 = Rin, Ro, Avo.
(a) vi vo Re RL Figure P7.44 (b) RL Ro vo Avovi (c) RL Ro vo Gmvi VDD = 1.8 V IREF = 100 μA, Vt = 0.5 V, kn ′ = 400 μA/V 2 .
VA ′ = 10 VDD = 1.8 V Problems 577 CHAPTER 7 PR OBLE MS an output current of 200-μA nominal value. To simplify mat-ters, assume that the nominal value of the output current is obtained at . It is further required that the circuit operate for VO in the range of 0.2 V to VDD and that the change in IO over this range be limited to 5% of the nominal value of IO.
Find the required value of R and the device dimensions. For the fabrication-process technology utilized, μA/V2, V/μm, and V.
7.48 Sketch the p-channel counterpart of the current-source circuit of Fig. 7.22. Note that while the circuit of Fig. 7.22 should more appropriately be called a current sink, the corre-sponding PMOS circuit is a current source. Let Q1 and Q2 be matched, and μA/V2.
Find the device W/L ratios and the value of the resistor that sets the value of so that a nominally 80-μA output current is obtained. The current source is required to operate for VO as high as 1.6 V. Neglect channel-length modulation.
7.49 Consider the current-mirror circuit of Fig. 7.23 with two transistors having equal channel lengths but with Q2 having a width five times that of Q1. If is 20 μA and the transistors are operating at an overdrive voltage of 0.2 V, what IO results? What is the minimum allowable value of VO for proper operation of the current source? If V, at what value of VO will the nominal value of IO be obtained? If VO increases by 1 V, what is the corresponding increase in IO? Let V.
7.50 For the current-steering circuit of Fig. P7.50, find IO in terms of and device W/L ratios.
Figure P7.45 (a) I VBIAS 2I Q1 Q2 vI vo I VBIAS 2I Q1 Q2 vI vo (b) I VBIAS 2I Q1 Q2 vI vo (c) 2I Q1 vI I VBIAS Q2 vo (d) VO VGS μnCox = 400 VA ′ = 10 Vt = 0.5 VDD = 1.8 V, Vt = 0.5 V, μpCox = 100 IREF IREF Vt = 0.5 VA = 20 IREF Q3 Q4 Q2 VDD I REF Q1 IO Figure P7.50 CHAPTER 7 PR OBLE MS 578 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers D 7.51 The current-steering circuit of Fig. P7.51 is fabricated in a CMOS technology for which 10V/ μm, and If all devices have L = 0.8 μm, design the circuit so that and Use the minimum possi-ble device widths needed to achieve proper operation of the current source Q2 for voltages at its drain as high as +1.3 V and proper operation of the current sink Q5 with voltages at its drain as low as −1.3 V. Specify the widths of all devices and the value of R. Find the output resistance of the current source Q2 and the output resistance of the current sink Q5.
7.52 A PMOS current mirror consists of three PMOS tran-sistors, one diode connected and two used as current outputs.
All transistors have μA/V2, and L = 1.0 μm but three different widths, namely, 10 μm, 20 μm, and 40 μm. When the diode-connected transistor is supplied from a 100-μA source, how many different output currents are avail-able? Repeat with two of the transistors diode connected and the third used to provide current output. For each possible input-diode combination, give the values of the output currents and of the that results.
7.53 Although thus far we have focused only on their appli-cation in dc biasing, current mirrors can also be used as signal-current amplifiers. One such application is illustrated in Fig.
P7.53. Here Q1 is a common-source amplifier fed with , where is the gate-to-source dc bias voltage of Q1 and is a small signal to be amplified. Find the signal component of the output voltage and hence the small-signal voltage gain . For this purpose, you may neglect all ro’s.
Also, find the small-signal resistance of the diode-connected transistor Q2 in terms of gm2 and ro2, and hence the total resistance between the drain of Q1 and ground. What is the volt-age gain of the CS amplifier Q1?
7.54 Consider the basic bipolar current mirror of Fig. 7.28 for the case in which Q1 and Q2 are identical devices having (a) Assuming the transistor β is very high, find the range of and IO corresponding to increasing from 10 μA to 10 mA. Assume that Q2 remains in the active mode, and neglect the Early effect.
(b) Find the range of IO corresponding to in the range of 10 μA to 10 mA, taking into account the finite β. Assume that β remains constant at 100 over the current range 0.1 mA to 5 mA but that at 10 μA and at Specify IO corresponding to 0.1 mA, 1 mA, and 10 mA. Note that β variation with current causes the current transfer ratio to vary with current.
7.55 Consider the basic BJT current mirror of Fig. 7.28 for the case in which Q2 has m times the area of Q1. Show that the current transfer ratio is given by Eq. (7.69). If β is specified to be a minimum of 50, what is the largest current transfer ratio possible if the error introduced by the finite β is limited to 10%?
7.56 Give the circuit for the pnp version of the basic current mirror of Fig. 7.28. If β of the pnp transistor is 20, what is the current gain (or transfer ratio) for the case of identical transistors, neglecting the Early effect?
7.57 Consider the basic BJT current mirror of Fig. 7.28 when Q1 and Q2 are matched and Neglecting the effect of finite β, find the change in IO, both as an absolute value and as a percentage, corresponding to VO changing from 1 V to 10 V. The Early voltage is 90 V.
D 7.58 The current-source circuit of Fig. P7.58 utilizes a pair of matched pnp transistors having , and V. It is required to design the circuit to provide an output current mA at VO = 2 V. What values of μnCox = 200 μA/V2, μpCox = 80 μA/V 2, Vtn = 0.6 V, Vtp = 0.6 – V, VAn ′ = VAp ′ = 12 V/μm.
IREF = 20 μA, I2 = 100 μA, I3 = I4 = 20 μA, I5 = 50 μA.
1.5 V 1.5 V I5 I2 IREF Q5 Q3 Q2 Q1 Q4 R Figure P7.51 Vt = 0.6 V, k′ p = 100 VSG vI = VGS vi + VGS vi vO vo vi ⁄ vI RL vO Q2 Q3 Q1 W2 L W3 L VDD Figure P7.53 IS = 10 16 – A.
VBE IREF IREF IC 10 mA, β = 50.
IREF = 10 μA, IO IREF ⁄ IREF = 2 mA.
IS = 10 15 – A β = 50, VA = 50 IO = 1 IREF Problems 579 CHAPTER 7 PR OBLE MS and R are needed? What is the maximum allowed value of VO while the current source continues to operate properly? What change occurs in IO corresponding to VO changing from the maximum positive value to −5 V?
7.59 Find the voltages at all nodes and the currents through all branches in the circuit of Fig. P7.59. Assume V and 7.60 For the circuit in Fig. P7.60, let and Find I, V1, V2, V3, V4, and V5 for (a) and (b) .
Q2 R Q1 VO IO IREF VCC 5 V Figure P7.58 Figure P7.58 VBE = 0.7 β = ∞.
VBE = 0.7 V β = ∞.
R = 10 kΩ R = 100 kΩ + 3.7 V – 5.7 V Figure P7.60 R2 5 k R3 3.6 k R1 20 k R4 2 k R5 3 k Figure P7.59 CHAPTER 7 PR OBLE MS 580 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers D 7.61 Using the ideas embodied in Fig. 7.31, design a multiple-mirror circuit using power supplies of ±5 V to create source currents of 0.2 mA, 0.4 mA, and 0.8 mA and sink currents of 0.5 mA, 1 mA, and 2 mA. Assume that the BJTs have and large β. What is the total power dissi-pated in your circuit?
7.62 Figure P7.62 shows a current-mirror circuit prepared for small-signal analysis. Replace the BJTs with their hybrid-models and find expressions for and where is the output short-circuit current. Assume 7.63 For the constant-current source circuit shown in Fig. P7.63, find the collector current I and the output resis-tance. The BJT is specified to have β = 100 and If the collector voltage undergoes a change of 10 V while the BJT remains in the active mode, what is the corresponding change in collector current?
7.64 For the MOS cascode current mirror of Fig. 7.32 with V, mA/V2, V, and 100μA, find and the minimum allowable voltage at the output. At what value of is equal to What does become at V?
Section 7.5: Current-Mirror Circuits with Improved Performance 7.65 In a particular cascoded current mirror, such as that shown in Fig. 7.32, all transistors have L = 1 μm, and Width 4 μm, and The reference current IREF is 20 μA. What output current results? What are the voltages at the gates of Q2 and Q3? What is the lowest voltage at the output for which current-source operation is possible? What are the values of gm and ro of Q2 and Q3? What is the output resistance of the mirror?
7.66 Find the output resistance of the double-cascode current mirror of Fig. P7.66.
7.67 For the base-current-compensated mirror of Fig. 7.33, let the three transistors be matched and specified to have a col-lector current of 1 mA at For IREF of 100 μA and assuming β = 200, what will the voltage at node x be? If IREF is increased to 1 mA, what is the change in Vx? What is the value of IO obtained with in both cases? Give the percent-age difference between the actual and ideal value of IO. What is the lowest voltage at the output for which proper current-source operation is maintained?
D 7.68 Extend the current-mirror circuit of Fig. 7.33 to n outputs. What is the resulting current transfer ratio from the input to each output, IO/IREF? If the deviation from unity is to be kept at 0.1% or less, what is the maximum possible number of outputs for BJTs with β = 100?
V BE 0.7 V π Rin io ii ⁄ , io ro rπ.
Q1 Q2 Rin io ii Figure P7.62 V A = 100 V.
4.3 k 5 V I Figure P7.63 Vt 0.5 = kn 4 = VA 10 = IREF = Ro VO IO IREF?
IO VO 5 = Vt = 0.6 V, μnCox = 160 μA/V2, VA = 10 V.
W1 W4 = = W2 = W3 = 40 μm.
Figure P7.66 V BE = 0.7 V.
VO = Vx Problems 581 CHAPTER 7 PR OBLE MS 7.69 For the base-current-compensated mirror of Fig. 7.33, show that the incremental input resistance (seen by the refer-ence current source) is approximately 2 VT/IREF. Evaluate Rin for IREF = 100 μA. [Hint: Q3 is operating at a current IE3 = 2IC/β, where IC is the operating current of each of Q1 and Q2. Replace each transistor with its T model and neglect r0.] 7.70 Consider the Wilson current-mirror circuit of Fig. 7.34 when supplied with a reference current IREF of 1 mA.
What is the change in IO corresponding to a change of +10 V in the voltage at the collector of Q3? Give both the absolute value and the percentage change. Let β = 100 and VA = 100 V.
D 7.71 (a) The circuit in Fig. P7.71 is a modified version of the Wilson current mirror. Here the output transistor is “split” into two matched transistors, Q3 and Q4. Find IO1 and IO2 in terms of IREF. Assume all transistors to be matched with current gain β.
(b) Use this idea to design a circuit that generates currents of 0.1 mA, 0.2 mA, and 0.4 mA, using a reference current source of 0.7 mA. What are the actual values of the currents generated for β = 50?
D 7.72 Use the pnp version of the Wilson current mirror to design a 0.2-mA current source. The current source is required to operate with the voltage at its output terminal as low as −2.5 V. If the power supplies available are ±2.5 V, what is the highest voltage possible at the output terminal?
7.73 For the Wilson current mirror of Fig. 7.34, show that the incremental input resistance seen by IREF is approximately 2 VT /IREF. (Neglect the Early effect in this derivation.) Evaluate Rin for IREF = 100 μA.
7.74 Consider the Wilson MOS mirror of Fig. 7.35(a) for the case of all transistors identical, with W/L = 12.5, μA/V2, and V. The mirror is fed with μA.
(a) Obtain an estimate of and at which the three transistors are operating, by neglecting the Early effect.
(b) Noting that and are operating at different obtain an approximate value for the difference in their cur-rents and hence determine (c) To eliminate the systematic error between and caused by the difference in between and a diode-connected transistor can be added to the circuit as shown in Fig. 7.35(c). What do you estimate now to be?
(d) What is the minimum allowable voltage at the output node of the mirror?
(e) Convince yourself that will have no effect on the output resistance of the mirror. Find (f) What is the change in (both absolute value and percent-age) that results from V?
7.75 Show that the input resistance (seen by ) for the Wilson MOS mirror of Fig. 7.35(a) is given by .
Assume that all three transistors are identical and neglect the Early effect. [Hint: Replace all transistors by their T model and remember that is equivalent to a resistance .] D 7.76 (a) Utilizing a reference current of 100 μA, design a Widlar current source to provide an output current of 10 μA.
Let the BJTs have vBE = 0.8 V at 1-mA current, and assume β to be high.
(b) If β = 200 and VA = 50 V, find the value of the output resis-tance, and find the change in output current corresponding to a 5-V change in output voltage.
D 7.77 Design three Widlar current sources, each having a 100-μA reference current: one with a current transfer ratio of 0.9, one with a ratio of 0.10, and one with a ratio of 0.01, all assuming high β. For each, find the output resistance, and contrast it with ro of the basic unity-ratio source for which RE = 0. Use β = ∞ and VA = 50 V.
7.78 The BJT in the circuit of Fig. P7.78 has VBE = 0.7 V, β = 100, and VA = 50 V. Find Ro.
D 7.79 (a) For the circuit in Fig. P7.79, assume BJTs with high β and vBE = 0.8 V at 1 mA. Find the value of R that will result in IO = 10 μA.
(b) For the design in (a), find Ro assuming β = 100 and VA = 50 V.
D 7.80 If the pnp transistor in the circuit of Fig. P7.80 is characterized by its exponential relationship with a scale current Figure P7.71 μnC ox 400 = VA 20 = IREF 100 = VOV VGS Q1 Q2 VDS, IO.
IO IREF VDS Q1 Q2, Q4 IO Q4 Ro.
IO ΔVO 1 = IREF 2 gm ⁄ Q1 1 gm ⁄ CHAPTER 7 PR OBLE MS 582 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers IS, show that the dc current I is determined by IR = VT ln(I/IS).
Assume Q1 and Q2 to be matched and Q3, Q4, and Q5 to be matched. Find the value of R that yields a current I = 100 μA.
For the BJT, VEB = 0.7 V at IE = 1 mA.
Section 7.6: Some Useful Transistor Pairings 7.81 The transistors in the circuit of Fig. P7.81 have and V.
(a) Find and the overall voltage gain.
(b) What is the effect of increasing the bias currents by a factor of 10 on and the power dissipation?
D 7.82 Consider the BiCMOS amplifier shown in Fig.
P7.82. The BJT has V and . The MOS-FET has V and mA/V2. Neglect the Early effect in both devices.
(a) Consider the dc bias circuit. Neglect the base current in in determining the current in Find the dc bias cur-rents in and and show that they are approximately 100 μA and 1 mA, respectively.
(b) Evaluate the small-signal parameters of and at their bias points.
(c) Determine the voltage gain For this pur-pose you can neglect 10 k Ro Figure P7.78 Ro 10 A R IO Q3 Q1 Q2 Figure P7.79 Figure P7.80 β 100 = VA 100 = Rin Rin, Gv, vsig vo Q1 100 A 100 A 5 V Q2 Rsig 500 k Rin Figure P7.81 VBE 0.7 = β 200 = Vt 1 = kn 2 = Rin C1 Vsig yi 5 V yo 1 k 100 k 6.8 k RG 10 M C2 Q2 Q1 3 k ∞ ∞ Figure P7.82 Q2 Q1.
Q1 Q2 Q1 Q2 Av vo vi ⁄ .
= RG.
Problems 583 CHAPTER 7 PR OBLE MS (d) Noting that is connected between the input node where the voltage is and the output node where the volt-age is , find and hence the overall voltage gain (e) To considerably reduce the effect of on and hence on consider the effect of adding another resistor in series with the existing one and placing a large bypass capacitor between their joint node and ground. What will and become?
7.83 The BJTs in the Darlington follower of Fig. P7.83 have β = 100. If the follower is fed with a source having a 100-kΩ resistance and is loaded with 1 kΩ, find the input resistance and the output resistance (excluding the load). Also find the overall voltage gain, both open-circuited and with load.
7.84 For the amplifier in Fig. 7.41(a), let I = 1 mA and β = 120, and neglect ro. Assume that a load resistance of 10 kΩ is connected to the output terminal. If the amplifier is fed with a signal vsig having a source resistance find Gv. 7.85 Consider the CD–CG amplifier of Fig. 7.41(c) for the case gm = 5 mA/V, and Rsig = RL = 20 kΩ. Neglecting ro, find Gv.
7.86 In each of the six circuits in Fig. P7.86, let β = 100, and neglect ro. Calculate the overall voltage gain.
RG vi Avvi Rin vo vsig ⁄ .
RG Rin Gv, 10-MΩ Rin Gv Rsig = 20 kΩ, Figure P7.83 vsig vo (a) vsig vo (b) vsig vo (c) vsig vo (d) vsig vo (e) vsig vo (f) Figure P7.86 CHAPTER 7 PR OBLE MS 584 Chapter 7 Building Blocks of Integrated-Circuit Amplifiers APPENDIX 7.A: Comparison of the MOSFET and the BJT 7.87 Find the range of ID obtained in a particular NMOS tran-sistor as its overdrive voltage is increased from 0.15 V to 0.4 V.
If the same range is required in IC of a BJT, what is the corre-sponding change in VBE?
7.88 What range of IC is obtained in an npn transistor as a result of changing the area of the emitter–base junction by a factor of 10 while keeping VBE constant? If IC is to be kept con-stant, by what amount must VBE change?
7.89 For each of the CMOS technologies specified in Table 7.A.1, find the and hence the required to operate a device with a W/L of 10 at a drain current ID = 100 μA. Ignore channel-length modulation. 7.90 Consider NMOS and PMOS devices fabricated in the 0.25-μm process specified in Table 7.A.1. If both devices are to operate at and ID = 100 μA, what must their W/L ratios be?
7.91 Consider NMOS and PMOS transistors fabricated in the 0.25-μm process specified in Table 7.A.1. If the two devices are to be operated at equal drain currents, what must the ratio of (W/L)p to (W/L)n be to achieve equal values of gm?
7.92 An NMOS transistor fabricated in the 0.18-μm CMOS process specified in Table 7.A.1 is operated at Find the required W/L and ID to obtain a gm of 10 mA/V. At what value of IC must an npn transistor be operated to achieve this value of gm?
7.93 For each of the CMOS process technologies specified in Table 7.A.1, find the gm of an NMOS and a PMOS transistor with W/L = 10 operated at ID = 100 μA.
7.94 An NMOS transistor operated with an overdrive volt-age of 0.25 V is required to have a gm equal to that of an npn transistor operated at IC = 0.1 mA. What must ID be? What value of gm is realized?
7.95 It is required to find the incremental (i.e., small-signal) resistance of each of the diode-connected transistors shown in Fig. P7.95. Assume that the dc bias current I = 0.1 mA. For the MOSFET, let μA/V2 and W/L = 10.
7.96 For an NMOS transistor with L = 1 μm fabricated in the 0.8-μm process specified in Table 7.A.1, find gm, and if the device is operated with and ID = 100 μA.
Also, find the required device width W.
7.97 For an NMOS transistor with L = 0.3 μm fabricated in the 0.18-μm process specified in Table 7.A.1, find gm, and obtained when the device is operated at ID = 100 μA with Also, find W.
7.98 Fill in the table below. For the BJT, let β = 100 and VA = 100 V. For the MOSFET, let W/L = 40, and VA = 10 V. Note that Rin refers to the input resistance at the control input terminal (gate, base) with the (source, emitter) grounded.
7.99 For an NMOS transistor fabricated in the 0.18-μm pro-cess specified in Table 7.A.1 with L = 0.3 μm and W = 6 μm, find the value of fT obtained when the transistor is operated at Use both the formula in terms of and and the approximate formula. Why does the approximate for-mula overestimate fT?
7.100 An NMOS transistor fabricated in the 0.18-μm pro-cess specified in Table 7.A.1 and having L = 0.3 μm and W = 6 μm is operated at and used to drive a capaci-tive load of 100 fF. Find , (or ), and . At what ID value is the transistor operating? If it is required to double , what must ID become? What happens to and in this case?
7.101 For an npn transistor fabricated in the high-voltage process specified in Table 7.A.2, evaluate at 100 μA, and 1 mA. Assume . Repeat for the low-voltage process.
VOV VGS VOV = 0.25 V VOV = 0.2 V.
μnCox = 200 ro, A0 VOV = 0.5 V ro, BJT MOSFET Bias Current IC = 0.1 mA IC = 1 mA ID = 0.1 mA ID = 1 mA gm (mA/V) ro (kΩ) A0 (V/V) Rin (kΩ) (a) I Figure P7.95 (b) I A0 VOV = 0.2 V.
μnCox = 200 μA/V 2, VOV = 0.2 V.
Cgs Cgd VOV = 0.2 V A0 fP f3dB ft ft A0 fP fT IC = 10 μA, Cμ Cμ0 Problems 585 CHAPTER 7 PR OBLE MS 7.102 Consider an NMOS transistor fabricated in the 0.8-μm process specified in Table 7.A.1. Let the transistor have L = 1 μm, and assume it is operated at (a) For find W, and fT.
(b) To what must be changed to double fT? Find the new values of W, and 7.103 For a lateral pnp transistor fabricated in the high-voltage process specified in Table 7.A.2, find fT if the device is operated at a collector bias current of 1 mA. Compare to the value obtained for a vertical npn.
7.104 Show that for a MOSFET the selection of L and determines and fT. In other words, show that and fT will not depend on ID and W. 7.105 Consider an NMOS transistor fabricated in the 0.18-μm technology specified in Table 7.A.1. Let the transistor be operated at Find and fT for L = 0.2 μm, 0.3 μm, and 0.4 μm.
D 7.106 Consider an NMOS transistor fabricated in the 0.5-μm process specified in Table 7.A.1. Let L = 0.5 μm and 0.3 V. If the MOSFET is connected as a common-source amplifier with a load capacitance (as in Fig.
7.A.2a), find the required transistor width W and bias current ID to obtain a unity-gain bandwidth of 100 MHz. Also, find and .
General Problem: 7.107 The circuit shown in Fig. P7.107 is known as a cur-rent conveyor.
(a) Assuming that Y is connected to a voltage V, a current I is forced into X, and terminal Z is connected to a voltage that keeps Q5 in the active region, show that a current equal to I flows through terminal Y, that a voltage equal to V appears at terminal X, and that a current equal to I flows through terminal Z. Assume to be large. Corresponding transistors are matched, and all transistors are operating in the active region.
(b) With Y connected to ground, show that a virtual ground appears at X. Now, if X is connected to a +5-V supply through a 10-k resistor, what current flows through Z?
ID = 100 μA.
VOV = 0.25 V, gm, ro, A0, Cgs, Cgd, VOV gm, ro, A0, Cgs, Cgd.
VOV A0 A0 VOV = 0.2 V.
A0 V OV = CL = 1 pF A0 f3dB β Ω Q1 Q3 Q4 VEE Q2 Y Q5 X Z Figure P7.107 CHAPTER 8 Differential and Multistage Amplifiers Introduction 587 8.1 The MOS Differential Pair 588 8.2 Small-Signal Operation of the MOS Differential Pair 599 8.3 The BJT Differential Pair 612 8.4 Other Nonideal Characteristics of the Differential Amplifier 629 8.5 The Differential Amplifier with Active Load 635 8.6 Multistage Amplifiers 651 Summary 666 Problems 667 587 IN THIS CHAPTER YOU WILL LEARN 1. The essence of the operation of the MOS and the bipolar differential amplifiers: how they reject common-mode noise or interference and amplify differential signals.
2. The analysis and design of MOS and BJT differential amplifiers.
3. Differential-amplifier circuits of varying complexity; utilizing passive resistive loads, current-source loads, and cascodes—the building blocks we studied in Chapter 7.
4. An ingenious and highly popular differential-amplifier circuit that utilizes a current-mirror load.
5. The structure, analysis, and design of amplifiers composed of two or more stages in cascade. Two practical examples are studied in detail: a two-stage CMOS op amp and a four-stage bipolar op amp.
Introduction The differential-pair or differential-amplifier configuration is the most widely used building block in analog integrated-circuit design. For instance, the input stage of every op amp is a differential amplifier. Also, the BJT differential amplifier is the basis of a very-high-speed logic circuit family, studied briefly in Chapter 14, called emitter-coupled logic (ECL).
Initially invented in the 1940s for use with vacuum tubes, the basic differential-amplifier configuration was subsequently implemented with discrete bipolar transistors.
However, it was the advent of integrated circuits that has made the differential pair extremely popular in both bipolar and MOS technologies. There are two reasons why differ-ential amplifiers are so well suited for IC fabrication: First, as we shall shortly see, the per-formance of the differential pair depends critically on the matching between the two sides of the circuit. Integrated-circuit fabrication is capable of providing matched devices whose parameters track over wide ranges of changes in environmental conditions. Second, by their very nature, differential amplifiers utilize more components (approaching twice as many) than single-ended circuits. Here again, the reader will recall from the discussion in Section 7.1 that a significant advantage of integrated-circuit technology is the availability of large numbers of transistors at relatively low cost.
We assume that the reader is familiar with the basic concept of a differential ampli-fier as presented in Section 2.1. Nevertheless it is worthwhile to answer the question: Why differential? Basically, there are two reasons for using differential in preference to single-ended amplifiers. First, differential circuits are much less sensitive to noise and 588 Chapter 8 Differential and Multistage Amplifiers interference than single-ended circuits. To appreciate this point, consider two wires carrying a small differential signal as the voltage difference between the two wires. Now, assume that there is an interference signal that is coupled to the two wires, either capacitively or inductively. As the two wires are physically close together, the interference voltages on the two wires (i.e., between each of the two wires and ground) will be equal. Since, in a differential system, only the difference signal between the two wires is sensed, it will contain no interference component!
The second reason for preferring differential amplifiers is that the differential configura-tion enables us to bias the amplifier and to couple amplifier stages together without the need for bypass and coupling capacitors such as those utilized in the design of discrete-circuit amplifiers (Sections 5.8 and 6.8). This is another reason why differential circuits are ideally suited for IC fabrication where large capacitors are impossible to fabricate economically.
The major topic of this chapter is the differential amplifier in both its MOS and bipolar implementations. As will be seen, the design and analysis of differential amplifiers makes extensive use of the material on single-stage amplifiers presented in Chapters 5 through 7.
We will follow the study of differential amplifiers with examples of practical multistage amplifiers, again in both MOS and bipolar technologies. 8.1 The MOS Differential Pair Figure 8.1 shows the basic MOS differential-pair configuration. It consists of two matched transistors, Q1 and Q2, whose sources are joined together and biased by a constant-current source I. The latter is usually implemented by a MOSFET circuit of the type studied in Sections 7.4 and 7.5. For the time being, we assume that the current source is ideal and that it has infinite output resistance. Although each drain is shown connected to the positive supply through a resistance RD, in most cases active (current-source) loads are employed, as will be seen shortly. For the time being, however, we will explain the essence of the differential-pair operation utilizing simple resistive loads. Whatever type of load is used, it is essential that the MOSFETs not enter the triode region of operation.
Figure 8.1 The basic MOS differential-pair configuration.
VDD vD2 vD1 RD RD I VSS Q1 Q2 vG1 vG2 iD1 iD2 iD1 iD2 8.1 The MOS Differential Pair 589 8.1.1 Operation with a Common-Mode Input Voltage To see how the differential pair works, consider first the case when the two gate terminals are joined together and connected to a voltage VCM, called the common-mode voltage. That is, as shown in Fig. 8.2, vG1 = vG2 = VCM. Since Q1 and Q2 are matched, the current I will divide equally between the two transistors. Thus, iD1 = iD2 = , and the voltage at the sources, VS, will be VS = VCM − VGS (8.1) where VGS is the gate-to-source voltage corresponding to a drain current of . Neglecting channel-length modulation, VGS and are related by (8.2) or in terms of the overdrive voltage , (8.3) (8.4) (8.5) The voltage at each drain will be (8.6) Thus, the difference in voltage between the two drains will be zero.
Now, let us vary the value of the common-mode voltage V CM. We see that, as long as Q1 and Q2 remain in the saturation region, the current I will divide equally between Q1 and Q2 and the voltages at the drains will not change. Thus the differential pair does not respond to (i.e., it rejects) common-mode input signals.
Figure 8.2 The MOS differential pair with a common-mode input voltage V CM.
I 2 ⁄ I 2 ⁄ I 2 ⁄ I 2 ---1 2 --- kn ′ = W L ----- VGS Vt – ( ) 2 V OV V OV VGS Vt – = I 2 ---1 2 --- kn ′ = W L -----VOV 2 V OV = I kn ′ W/L ( ) ⁄ vD1 = vD2 = VDD I 2 ---RD – VSS VDD VGS VGS RD RD I Q1 Q2 VCM vD2 VDD RD VGS Vt VOV VS VCM V GS V t Ikn L W I2 I2 I2 I2 vD1 VDD RD I 2 I 2 590 Chapter 8 Differential and Multistage Amplifiers An important specification of a differential amplifier is its input common-mode range.
This is the range of V CM over which the differential pair operates properly. The highest value of V CM is limited by the requirement that Q1 and Q2 remain in saturation, thus (8.7) The lowest value of V CM is determined by the need to allow for a sufficient voltage across the current source I for it to operate properly. If a voltage V CS is needed across the current source, then (8.8) VCMmax Vt VDD I 2 ---RD – + = VCMmin V – SS VCS Vt V OV + + + = For the MOS differential pair with a common-mode voltage V CM applied, as shown in Fig. 8.2, let VDD = V SS = 1.5 V, , V t = 0.5 V, I = 0.4 mA, and RD = 2.5 kΩ, and neglect channel-length modulation. Assume that the current source I requires a minimum voltage of 0.4 V to operate properly.
(a) Find VOV and VGS for each transistor.
(b) For VCM = 0, find VS, ID1, ID2, VD1, and VD2.
(c) Repeat (b) for VCM = +1 V. (d) Repeat (b) for VCM = −0.2 V.
(e) What is the highest permitted value of VCM?
(f) What is the lowest value allowed for VCM?
Solution (a) With , we see that . Now, since the transistors are matched, I will divide equally between the two transistors, Thus, which results in and thus, V kn ′ W/L ( ) 4 mA/V2 = vG1 vG2 VCM = = VGS1 V GS2 = ID1 ID2 I 2 ---= = I 2 ---1 2 ---k′ n W L ⁄ ( )VOV 2 = 0.4 2 -------1 2 ---4 × VOV 2 = VOV 0.316 V = VGS Vt VOV 0.5 0.316 0.82 + = + = Example 8.1 8.1 The MOS Differential Pair 591 (b) The analysis for the case is shown in Fig. 8.3(a) from which we see that V mA (b) 1.5 V 1 V 0.82 V 0.82 V 1 V 2.5 k 0.4 mA 1.5 V 0.18 V 2.5 k Q1 Q2 0.2 mA 0.2 mA 0.2 mA 0.2 mA 1 V 1 V (a) 1.5 V 1 V 0.82 V 0.82 V 1 V 2.5 k 0.4 mA 1.5 V 0.82 V 2.5 k Q1 Q2 0.2 mA 0.2 mA 0.2 mA 0.2 mA Figure 8.3 Circuits for Example 8.1. Effects of varying VCM on the operation of the differential pair.
0.2 V 0.2 V (c) 1.5 V 1 V 0.82 V 0.82 V 1 V 2.5 k 0.4 mA 1.5 V 1.02 V 2.5 k 0.2 mA 0.2 mA 0.2 mA 0.2 mA Q1 Q2 VCM 0 = VS VG VGS 0 0.82 0.82 – = – = – = ID1 ID2 I 2 ---0.2 = = = 592 Chapter 8 Differential and Multistage Amplifiers Example 8.1 continued V (c) The analysis for the case V is shown in Fig. 8.3(b) from which we see that V mA Observe that the transistors remain in the saturation region as assumed. Also observe that , , , and remain unchanged even though the common-mode voltage changed by 1 V.
(d) The analysis for the case V is shown in Fig. 8.3(c), from which we see that V It follows that the current source I now has a voltage across it of V which is greater than the minimum required value of 0.4 V. Thus, the current source is still operating properly and delivering a constant current I = 0.4 mA and hence mA V So, here again the differential circuit is not responsive to the change in the common-mode voltage .
(e) The highest value of is that which causes and to leave saturation and enter the triode region. Thus, V (f) The lowest value allowed for is that which reduces the voltage across the current source I to the minimum required of V. Thus, V Thus, the input common-mode range is V VD1 VD2 VDD I 2 --- RD – = = 1.5 0.2 2.5 1 = × – = VCM +1 = VS VG VGS 1 0.82 + 0.18 = – = – = ID1 ID2 I 2 ---0.2 = = = VD1 VD2 VDD I 2 --- RD 1.5 0.2 2.5 × = +1 V – = – = = ID1 ID2 VD1 VD2 VCM VCM 0.2 – = VS VG VGS 0.2 – 0.82 1.02 – = – = – = VCS VS – VSS – ( ) 1.02 – 1.5 0.48 = + = – = ID1 ID1 I 2 ---0.2 = = = VD1 VD2 VDD I 2 --- RD +1 = – = = VCM VCM Q1 Q2 VCMmax Vt VD + = 0.5 1 +1.5 = + = VCM VCS 0.4 = VCMmin –VSS VCS VGS + + = 1.5 – 0.4 0.82 0.28 – = + + = 0.28 V VCM +1.5 ≤ ≤ – 8.1 The MOS Differential Pair 593 8.1.2 Operation with a Differential Input Voltage Next we apply a difference or differential input voltage by grounding the gate of Q2 (i.e., set-ting vG2 = 0) and applying a signal vid to the gate of Q1, as shown in Fig. 8.4. We can see that since vid = vGS1 – vGS2, if vid is positive, vGS1 will be greater than vGS2 and hence iD1 will be greater than iD2 and the difference output voltage (vD2 – vD1) will be positive. On the other hand, when vid is negative, vGS1 will be lower than vGS2, iD1 will be smaller than iD2, and corre-spondingly vD1 will be higher than vD2; in other words, the difference or differential output voltage (vD2 – vD1) will be negative.
From the above, we see that the differential pair responds to difference-mode or differ-ential input signals by providing a corresponding differential output signal between the two drains. At this point, it is useful to inquire about the value of vid that causes the entire bias current I to flow in one of the two transistors. In the positive direction, this happens when vGS1 reaches the value that corresponds to iD1 = I, and vGS2 is reduced to a value equal to the threshold voltage Vt, at which point vS = –Vt. The value of vGS1 can be found from Figure 8.4 The MOS differential pair with a differential input signal vid applied. With vid positive: vGS1 > vGS2, iD1 > iD2, and vD1 < vD2; thus (vD2 − vD1) will be positive. With vid negative: vGS1 < vGS2, iD1 < iD2, and vD1 > vD2; thus (vD2 − vD1) will be negative.
8.1 For the amplifier in Example 8.1, find the input common-mode range for the case in which the two drain resistances are increased by a factor of 2. Ans. V to 1.0 V RD 0.28 – EXERCISE I 1 2 --- kn ′ W L -----⎝ ⎠ ⎛ ⎞vGS1 Vt – ( ) 2 = V SS VDD vD2 vD1 vGS1 vGS2 vS RD RD I Q1 Q2 vid iD1 iD2 594 Chapter 8 Differential and Multistage Amplifiers as (8.9) where VOV is the overdrive voltage corresponding to a drain current of (Eq. 8.5). Thus, the value of vid at which the entire bias current I is steered into Q1 is (8.10) If vid is increased beyond , iD1 remains equal to I, vGS1 remains equal to ( ), and vS rises correspondingly, thus keeping Q2 off. In a similar manner we can show that in the neg-ative direction, as vid reaches , Q1 turns off and Q2 conducts the entire bias current I.
Thus the current I can be steered from one transistor to the other by varying vid in the range which defines the range of differential-mode operation. Finally, observe that we have assumed that Q1 and Q2 remain in saturation even when one of them is conducting the entire current I.
To use the differential pair as a linear amplifier, we keep the differential input signal vid small.
As a result, the current in one of the transistors (Q1 when vid is positive) will increase by an incre-ment ΔI proportional to vid, to ( + ΔI). Simultaneously, the current in the other transistor will decrease by the same amount to become ( − ΔI). A voltage signal –ΔIRD develops at one of the drains and an opposite-polarity signal, ΔIRD, develops at the other drain. Thus the output volt-age taken between the two drains will be 2ΔIRD, which is proportional to the differential input sig-nal vid. The small-signal operation of the differential pair will be studied in detail in Section 8.2.
8.1.3 Large-Signal Operation We shall now derive expressions for the drain currents iD1 and iD2 in terms of the input differ-ential signal vid ≡ vG1 – vG2. The derivation assumes that the differential pair is perfectly matched and neglects channel-length modulation (λ = 0). Thus these expressions do not depend on the details of the circuit to which the drains are connected, and we do not show vGS1 Vt 2I kn ′ ⁄ W/L ( ) + = Vt 2VOV + = I 2 ⁄ vidmax vGS1 vS + = Vt 2VOV Vt – + = 2VOV = 2V OV Vt 2V OV + 2 – V OV 2V OV – vid 2V OV ≤ ≤ 8.2 For the MOS differential pair specified in Example 8.1 find (a) the value of vid that causes Q1 to con-duct the entire current I, and the corresponding values of vD1 and vD2; (b) the value of vid that causes Q2 to conduct the entire current I, and the corresponding values of vD1 and vD2; (c) the corresponding range of the differential output voltage (vD2 – vD1).
Ans. (a) +0.45 V, 0.5 V, 1.5 V; (b) –0.45 V, 1.5 V, 0.5 V; (c) +1 V to –1 V EXERCISE I 2 ⁄ I 2 ⁄ 8.1 The MOS Differential Pair 595 these connections in Fig. 8.5; we simply assume that the circuit maintains Q1 and Q2 in the saturation region of operation at all times.
To begin with, we express the drain currents of Q1 and Q2 as (8.11) (8.12) Taking the square roots of both sides of each of Eqs. (8.11) and (8.12), we obtain (8.13) (8.14) Subtracting Eq. (8.14) from Eq. (8.13) and substituting (8.15) results in (8.16) The constant-current bias imposes the constraint (8.17) Equations (8.16) and (8.17) are two equations in the two unknowns iD1 and iD2 and can be solved as follows: Squaring both sides of Eq. (8.16) and substituting for iD1 + iD2 = I gives Q1 Q2 Figure 8.5 The MOSFET differential pair for the purpose of deriving the transfer characteristics, iD1 and iD2 versus vid = vG1 – vG2.
iD1 1 2 --- kn ′ W L ----- vGS1 Vt – ( ) 2 = iD2 1 2 --- kn ′ W L ----- vGS2 Vt – ( ) 2 = iD1 1 2 --- k′ nW L ----- vGS1 Vt – ( ) = iD2 1 2 ---k′ n W L ----- vGS2 Vt – ( ) = vGS1 vGS2 – vG1 vG2 – vid = = iD1 iD2 – 1 2 --- k′ nW L -----vid = iD1 iD2 + I = 2 iD1iD2 I 1 2 --- k′ nW L -----v2 id – = 596 Chapter 8 Differential and Multistage Amplifiers Substituting for iD2 from Eq. (8.17) as iD2 = I – iD1 and squaring both sides of the resulting equation provides a quadratic equation in iD1 that can be solved to yield Now, since the increment in iD1 above the bias value of must have the same polarity as vid , only the root with the “+” sign in the second term is physically meaningful; thus, (8.18) The corresponding value of iD2 is found from iD2 = I – iD1 as (8.19) At the bias (quiescent) point, vid = 0, leading to (8.20) Correspondingly, (8.21) where (8.22) This relationship enables us to replace in Eqs. (8.18) and (8.19) with to express iD1 and iD2 in the alternative form (8.23) (8.24) These two equations describe the effect of applying a differential input signal vid on the cur-rents iD1 and iD2. They can be used to obtain the normalized plots, and versus shown in Fig. 8.6. Note that at vid = 0, the two currents are equal to . Making vid positive causes iD1 to increase and iD2 to decrease by equal amounts, to keep the sum constant, iD1 + iD2 = I. The current is steered entirely into Q1 when vid reaches the value , as we found out earlier. For vid negative, identical statements can be made by interchanging iD1 and iD2. In this case, steers the current entirely into Q2. Finally, note that the plots in Fig. 8.6 are universal, as they apply to any MOS differential pair.
iD1 I 2 ---k′ nW L ----- I vid 2 -----⎝ ⎠ ⎛ ⎞1 vid 2 ⁄ ( ) 2 I k′ nW L -----⁄ -------------------– ± = I 2 ⁄ iD1 I 2 ---k′ nW L -----I vid 2 -----⎝ ⎠ ⎛ ⎞1 vid 2 ⁄ ( ) 2 I k′ nW L -----⁄ -------------------– + = iD2 I 2 ---k′ n W L -----I vid 2 -----⎝ ⎠ ⎛ ⎞1 vid 2 ⁄ ( ) 2 I k′ nW L -----⁄ -------------------– – = iD1 iD2 I 2 ---= = vGS1 vGS2 VGS = = I 2 --- = 1 2 ---k′ nW L ----- V GS Vt – ( ) 2 = 1 2 ---k′ nW L ----- VOV 2 k′ n(W L) ⁄ I VOV 2 ⁄ iD1 = I 2 --- I V OV ---------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ 1 vid 2 ⁄ V OV ------------⎝ ⎠ ⎛ ⎞ 2 – + iD2 I 2 ---I V OV ---------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ 1 vid 2 ⁄ V OV ------------⎝ ⎠ ⎛ ⎞ 2 – – = iD1 I ⁄ iD2 I ⁄ vid V OV ⁄ , I 2 ⁄ 2V OV vid = 2V OV – 8.1 The MOS Differential Pair 597 The transfer characteristics of Eqs. (8.23) and (8.24) and Fig. 8.6 are obviously nonlinear.
This is due to the term involving . Since we are interested in obtaining linear amplification from the differential pair, we will strive to make this term as small as possible. For a given value of V OV, the only thing we can do is keep ( ) much smaller than V OV, which is the condition for the small-signal approximation. It results in (8.25) and (8.26) which, as expected, indicate that iD1 increases by an increment id, and iD2 decreases by the same amount, id, where id is proportional to the differential input signal vid, (8.27) Recalling from our study of the MOSFET in Chapter 5 (also refer to Table 7.A.3), that a MOSFET biased at a current ID has a transconductance , we recognize the factor ( ) in Eq. (8.27) as gm of each of Q1 and Q2, which are biased at ID = . Now, why Simply because vid divides equally between the two devices with vgs1 = and vgs2 = – , which causes Q1 to have a current increment id and Q2 to have a current decrement id. We shall analyze Figure 8.6 Normalized plots of the currents in a MOSFET differential pair. Note that VOV is the overdrive voltage at which Q1 and Q2 operate when conducting drain currents equal to , the equilibrium situation.
Note that these graphs are universal and apply to any MOS differential pair.
VOV VOV VOV I 2 ⁄ vid 2 vid 2 ⁄ iD1 I 2 ---I V OV ---------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ + iD2 I 2 ---I V OV ---------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ – id I V OV ---------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ = gm 2ID VOV ⁄ = I VOV ⁄ I 2 ⁄ vid 2?
⁄ vid 2 ⁄ vid 2 ⁄ 598 Chapter 8 Differential and Multistage Amplifiers the small-signal operation of the MOS differential pair shortly. At this time, however, we wish to return to Eqs. (8.23) and (8.24) and note that for a given , linearity can be increased by increas-ing the overdrive voltage V OV at which each of Q1 and Q2 is operating. This can be done by using smaller ratios. The price paid for the increased linearity is a reduction in gm and hence a reduction in gain. In this regard, we observe that the normalized plot of Fig. 8.6, though compact, masks this design degree of freedom. Figure 8.7 shows plots of the transfer characteristics iD1,2/I versus vid for various values of V OV. These graphs clearly illustrate the linearity–transconductance trade-off obtained by changing the value of V OV: The linear range of operation can be extended by operating the MOSFETs at a higher V OV (by using smaller ratios) at the expense of reducing gm and hence the gain. This trade-off is based on the assumption that the bias current I is being kept constant. The bias current can, of course, be increased to obtain a higher gm. The expense for doing this, however, is increased power dissipation, a serious limitation in IC design. Figure 8.7 The linear range of operation of the MOS differential pair can be extended by operating the transistor at a higher value of VOV .
500 400 300 200 100 0 100 0.9 0.8 0.7 0.3 0.2 0.1 200 300 400 500 1.0 iD I iD1 I vid (mV) iD2 I 0.5 V OV 0.4 V V OV 0.3 V V OV 0.2 V V OV 0.4 V V OV 0.3 V V OV 0.2 V vid W L ⁄ W L ⁄ 8.3 A MOS differential pair is operated at a bias current I of 0.4 mA. If μnCox = 0.2 mA/V2, find the required values of and the resulting gm if the MOSFETs are operated at VOV = 0.2, 0.3, and 0.4 V.
For each value, give the maximum for which the term involving in Eqs. (8.23) and (8.24), namely is limited to 0.1.
Ans. VOV (V) W/L (mA/V) (mV) 0.2 50 2 126 0.3 22.2 1.33 190 0.4 12.5 1 253 W L ⁄ vid vid 2 ((vid / 2)/ V OV)2, gm vid max EXERCISE 8.2 Small-Signal Operation of the MOS Differential Pair 599 8.2 Small-Signal Operation of the MOS Differential Pair In this section we build on the understanding gained of the basic operation of the differential pair and consider in some detail its operation as a linear amplifier.
8.2.1 Differential Gain Figure 8.8(a) shows the MOS differential amplifier with input voltages (8.28) Figure 8.8 Small-signal analysis of the MOS differential amplifier. (a) The circuit with a common-mode voltage applied to set the dc bias voltage at the gates and with vid applied in a complementary (or balanced) manner. (b) The circuit prepared for small-signal analysis. (c) An alternative way of looking at the small-signal operation of the circuit.
vG1 = V CM 1 2 ---vid + Q1 Q2 RD RD I V DD VSS vD2 vG1 VCM vid vD1 (a) vod vG1 vG2 2 1 vG2 VCM vid 2 1 Q1 Q2 RD RD vo2 gmRD(vid2) vo1 gmRD(vid2) vid2 vid2 (b) gm(vid2) vod gmRDvid gm(vid2) 0 V vgs1 vid2 vgs2 vid2 Biased at I2 RD RD G1 G2 vo2 vo1 (c) id id 1 gm 1 gm vid vid (2gm) vod Q1 Q2 600 Chapter 8 Differential and Multistage Amplifiers and (8.29) Here, V CM denotes a common-mode dc voltage within the input common-mode range of the differential amplifier. It is needed in order to set the dc voltage of the MOSFET gates.
Typically V CM is at the middle value of the power supply. Thus, for our case, where two com-plementary supplies are utilized, V CM is typically 0 V.
The differential input signal vid is applied in a complementary (or balanced) manner; that is, vG1 is increased by and vG2 is decreased by . This would be the case, for instance, if the differential amplifier were fed from the output of another differential-amplifier stage. Some-times, however, the differential input is applied in a single-ended fashion, as we saw earlier in Fig. 8.4. The difference in the performance resulting is too subtle a point for our current needs.
As indicated in Fig. 8.8(a) the amplifier output can be taken either between one of the drains and ground or between the two drains. In the first case, the resulting single-ended outputs vo1 and vo2 will be riding on top of the dc voltages at the drains, This is not the case when the output is taken between the two drains; the resulting differential out-put vod (having a 0-V dc component) will be entirely a signal component. We will see shortly that there are other significant advantages to taking the output voltage differentially.
Our objective now is to analyze the small-signal operation of the differential amplifier of Fig. 8.8(a) to determine its voltage gain in response to the differential input signal vid.
Toward that end we show in Fig. 8.8(b) the circuit with the power supplies grounded, the bias current source I removed, and V CM eliminated; that is, only signal quantities are indi-cated. For the time being we will neglect the effect of the MOSFET ro. Finally note that each of Q1 and Q2 is biased at a dc current of and is operating at an overdrive voltage V OV.
From the symmetry of the circuit and because of the balanced manner in which vid is applied, we observe that the signal voltage at the joint source connection must be zero, acting as a sort of virtual ground. Thus Q1 has a gate-to-source voltage signal vgs1 = and Q2 has vgs2 = − . Assuming the condition for the small-signal approximation, the changes resulting in the drain currents of Q1 and Q2 will be proportional to vgs1 and vgs2, respectively. Thus Q1 will have a drain current increment gm( ) and Q2 will have a drain current decrement gm( ), where gm denotes the equal transconduc-tances of the two devices, (8.30) These results correspond to those obtained earlier using the large-signal transfer characteristics and imposing the small-signal condition, Eqs. (8.25) to (8.27).
It is useful at this point to observe again that a signal ground is established at the source terminals of the transistors without resorting to the use of a large bypass capacitor, clearly a major advantage of the differential-pair configuration.
The essence of differential-pair operation is that it provides complementary current signals in the drains; what we do with the resulting pair of complementary current signals is, in a sense, a separate issue. Here, of course, we are simply passing the two current signals through a pair of matched resistors, RD, and thus obtaining the drain voltage signals (8.31) and (8.32) vG2 = VCM 1 2 ---vid – vid 2 ⁄ vid 2 ⁄ V DD I 2 ---RD – ( ).
I 2 ⁄ vid 2 ⁄ vid 2 ⁄ vid 2 ⁄ V OV, vid 2 ⁄ vid 2 ⁄ gm 2ID VOV ---------2 I 2 ⁄ ( ) VOV -----------------I VOV ---------= = = vo1 gm vid 2 -----RD – = vo2 +gm vid 2 -----RD = 8.2 Small-Signal Operation of the MOS Differential Pair 601 If the output is taken in a single-ended fashion, the resulting gain becomes (8.33) or (8.34) Alternatively, if the output is taken differentially, the gain becomes (8.35) Thus another advantage of taking the output differentially is an increase in gain by a factor of 2 (6 dB). It should be noted, however, that although differential outputs are preferred, a single-ended output is needed in some applications. We will have more to say about this later. An alternative and useful way of viewing the operation of the differential pair in response to a differential input signal vid is illustrated in Fig. 8.8(c). Here we are making use of the fact that the resistance between gate and source of a MOSFET, looking into the source, is . As a result, between G1 and G2 we have a total resistance, in the source cir-cuit, of . It follows that we can obtain the current id simply by dividing vid by , as indicated in the figure.
8.2.2 The Differential Half-Circuit When a symmetrical differential amplifier is fed with a differential signal in a balanced manner, as in the case in Fig. 8.8, the performance can be determined by considering only half the circuit. The equivalent differential half-circuit is shown in Fig. 8.9. It has a grounded source, a result of the virtual ground that appears on the common sources’ termi-nal of the MOSFETs in the differential pair. Note that is operating at a drain bias current of (I/2) and an overdrive voltage The differential gain can be determined directly from the half-circuit. For instance, if we wish to take of and into account, we can use the half-circuit with the follow-ing result: (8.36) vo1 vid ------–1 2 ---gmRD = vo2 vid ------1 2 ---gmRD = Ad vod vid ------vo2 vo1 – vid -------------------= ≡ gmRD = 1 gm ⁄ 2 gm ⁄ 2 gm ⁄ Q1 VOV.
Ad ro Q1 Q2 Ad gm RD ro || ( ) = RD vid 2 vod 2 Q1 Figure 8.9 The equivalent differential half-circuit of the differential amplifier of Fig. 8.8. Here Q1 is biased at I/2 and is operating at VOV. This circuit can be used to determine the differential voltage gain of the differential amplifier Ad = vod/vid. 602 Chapter 8 Differential and Multistage Amplifiers More significantly, the frequency response of the differential gain can be determined by analyzing the half-circuit, as we shall do in Chapter 9.
Give the differential half-circuit of the differential amplifier shown in Fig. 8.10(a). Assume that and are perfectly matched. Neglecting , determine the differential voltage gain Solution Since the circuit is symmetrical and is fed with in a balanced manner, the differential half-circuit will be as shown in Fig. 8.10(b). Observe that because the line of symmetry passes through the middle of the half-circuit has a resistance connected between drain and ground. Also note that the virtual ground appears on the node between the two resistances As a result, the half-circuit has a source-degeneration resistance Now, neglecting of the half-circuit transistor , we can obtain the gain as the ratio of the total resistance in the drain to the total resistance in the source as with the result that (8.37) Q1 Q2 ro Ad vod vid ⁄ .
≡ RL RD I RD VSS VDD VCM Rs Rs vid 2 Q1 Q2 VCM vid 2 (a) vod RD Rs vid 2 vod Q1 (b) 2 RL 2 Figure 8.10 (a) Differential amplifier for Example 8.2. (b) Differential half-circuit.
vid RL, RL 2 ⁄ Rs.
Rs.
ro Q1 vod 2 ⁄ – vid 2 ⁄ -----------------RD RL 2 ⁄ ( ) || 1 gm ⁄ Rs + ------------------------------– = Ad vod vid -------RD RL 2 ⁄ ( ) || 1 gm ⁄ Rs + ------------------------------= ≡ Example 8.2 8.2 Small-Signal Operation of the MOS Differential Pair 603 8.2.3 The Differential Amplifier with Current-Source Loads To obtain higher gain, the passive resistances can be replaced with current sources, as shown in Fig. 8.11(a). Here the current sources are realized with PMOS transistors and , and is a dc bias voltage that ensures that and each conducts a current equal to I/2. The differential voltage gain can be found from the differential half-circuit shown in Fig. 8.11(b) as 8.4 A MOS differential amplifier is operated at a total current of 0.8 mA, using transistors with a W/L ratio of 100, V, and k Find , and Ans. 0.2 V; 4 mA/V; 50 k 18.2 V/V μnCox 0.2 mA V2 ⁄ , = VA 20 = RD 5 = Ω.
VOV gm, ro, Ad.
Ω; EXERCISE RD Q3 Q4 VG Q3 Q4 Ad Ad vod vid -------gm1 ro1 ro3 || ( ) = ≡ VG Q3 Q4 Q2 Q1 VCM vid 2 VCM vid 2 I VSS VDD vod (a) vid 2 vod 2 Q3 Q1 (b) Figure 8.11 (a) Differential amplifier with current-source loads formed by Q3 and Q4. (b) Differential half-circuit of the amplifier in (a).
604 Chapter 8 Differential and Multistage Amplifiers 8.2.4 Cascode Differential Amplifier The gain of the differential amplifier can be increased by utilizing the cascode configuration studied in Section 7.3. Figure 8.12(a) shows a CMOS differential amplifier with cascoding 8.5 The differential amplifier of Fig. 8.11(a) is fabricated in a 0.18-μm CMOS technology for which μA/V2, V, and V/μm. If the bias current I = 200 μA and all transistors have a channel length twice the minimum and are operating at V, find W/L for each of , , , and and determine the differential voltage gain Ans.
; ; V/V μnCox 4μpCox 400 = = Vt 0.5 = V ′ A 10 = VOV 0.2 = Q1 Q2 Q3 Q4, Ad.
W L ⁄ ( )1,2 12.5 = W L ⁄ ( )3,4 50 = Ad 18 = EXERCISE VG3 Q7 Q5 Q3 Q1 Q8 VG2 Q6 VG1 Q4 Q2 VCM vid 2 VCM vid 2 VDD vod I – VSS (a) Q7 Q5 Q3 Q1 (b) Rop Ron vod 2 vid 2 Figure 8.12 (a) Cascode differential amplifier; and (b) its differential half circuit.
8.2 Small-Signal Operation of the MOS Differential Pair 605 applied to the amplifying transistors and via transistors and and to the current-source transistors and via transistors and The differential voltage gain can be found from the differential half-circuit shown in Fig. 8.12(b) as (8.38) where (8.39) and, (8.40) 8.2.5 Common-Mode Gain and Common-Mode Rejection Ratio (CMRR) Thus far, we have seen that the differential amplifier responds to a differential input signal and completely rejects a common-mode signal. This latter point was made very clearly at the outset of our discussion of differential amplifiers and was illustrated in Example 8.1, where we saw that changes in over a wide range resulted in no change in the voltage at either of the two drains. This highly desirable result is, however, a consequence of our assumption that the current source that supplies the bias current I is ideal. As we shall now show, if we consider the more realistic situation of the current source having a finite output resistance , the common-mode gain will no longer be zero.
Figure 8.13(a) shows a MOS differential amplifier biased with a current source having an output resistance As before, the dc voltage at the input is defined by Here, how-ever, we also have an incremental signal applied to both input terminals. This common-mode input signal can represent an interference signal or noise that is picked up by both inputs and is clearly undesirable. Our objective now is to find how much of makes its way to the output of the amplifier.
Before we determine the common-mode gain of the amplifier, we wish to address the question of the effect of on the bias current of and . That is, with set to zero, the bias current in each of and will no longer be I/2 but will be larger than I/2 by an amount determined by and However, since is usually very large, this addi-tional dc current in each of and is usually small and we shall neglect it, thus assuming Q1 Q2 Q3 Q4, Q7 Q8 Q5 Q6.
Ad vod vid -------gm1 Ron Rop || ( ) = ≡ Ron gm3ro3 ( )ro1 = Rop gm5ro5 ( )ro7 = 8.6 The CMOS cascode differential amplifier of Fig. 8.12(a) is fabricated in a 0.18-μm technology for which μA/V2, V, and V/μm. If the bias current I = 200 μA, and all transistors have a channel length twice the minimum and are operating at V, find W/L for each of to , and determine the differential voltage gain .
Ans.
; ; V/V μnCox 4μpCox 400 = = Vt 0.5 = V ′ A 10 = VOV 0.2 = Q1 Q8 Ad W L ⁄ ( )1,2,3,4 12.5 = W L ⁄ ( )5,6,7,8 50 = Ad 648 = EXERCISE VCM RSS RSS.
VCM.
vicm vicm RSS Q1 Q2 vicm Q1 Q2 VCM RSS.
RSS Q1 Q2 606 Chapter 8 Differential and Multistage Amplifiers Q1 Q2 VCM vicm VD vo1 VD vo2 VCM vicm VDD vod I VSS (a) RD RD RSS Q1 Q2 vicm vicm (b) RD RD RSS vo1 vo2 vod 2i i i (c) RD RD 2 RSS i i vicm vicm i i g2 g1 gm 1 gm 1 vo1 vo2 vod 2i Q1 Q2 vicm vicm (d) RD RD 2RSS 2RSS Biased at I/2 vo1 vo2 i i Figure 8.13 (a) A MOS differential amplifier with a common-mode input signal vicm superimposed on the input dc common-mode voltage VCM. (b) The amplifier circuit prepared for small-signal analysis. (c) The amplifier circuit with the transistors replaced with their T model and ro neglected. (d) The circuit in (b) split into its two halves; each half is called the “CM half circuit.” 8.2 Small-Signal Operation of the MOS Differential Pair 607 that and continue to operate at a bias current of I/2. The reader might also be wonder-ing about the effect of on the differential gain. The answer here is very simple: The vir-tual ground that develops on the common-source terminal results in a zero signal current through ; hence has no effect on the value of .
To determine the response of the differential amplifier to the common-mode input signal , consider the circuit in Fig. 8.13(b), where we have replaced each of and by a short circuit and I by an open circuit. The circuit is obviously symmetrical, and thus the two transistors will carry equal signal currents, denoted i. The value of i can be easily determined by replacing each of and with its T model and, for simplicity, neglecting . The resulting equivalent circuit is shown in Fig. 8.13(c), from which we can write (8.41) Thus, (8.42) The voltages at the drain of and can now be found as resulting in (8.43) It follows that both and will be corrupted by the common-mode signal and will be given approximately by (8.44) where we have assumed that Nevertheless, because the differen-tial output voltage will remain free of common-mode interference: (8.45) Thus the circuit still rejects common-mode signals! Unfortunately, however, this will not be the case if the circuit is not perfectly symmetrical, as we shall now show.
Before proceeding further, it is useful to observe that all the above results can be obtained by considering only half the differential amplifier. Figure 8.13(d) shows the two half-circuits of the differential amplifier that apply for common-mode analysis. To see the equiv-alence, observe that each of the two half-circuits indeed carries a current i given by Eq.
(8.42) and the voltages at the source terminals are equal . Thus the two sources can be joined, returning the circuit to the original form in Fig. 8.13(b). Each of the circuits in Fig. 8.13(d) is known as the common-mode half-circuit. Note the difference between the CM half-circuit and the differential half-circuit.
Effect of RD Mismatch When the two drain resistances exhibit a mismatch as they inevitably do, the common-mode voltages at the two drains will no longer be equal. Rather, if the load of is and that of is the drain signal voltages arising from will be (8.46) Q1 Q2 RSS RSS RSS Ad vicm VDD VSS Q1 Q2 ro vicm i gm ------2iRSS + = i vicm 1 gm ⁄ 2RSS + -------------------------------= Q1 Q2 vo1 vo2 RDi – = = vo1 vo2 RD 1 gm ⁄ 2RSS + -------------------------------vicm – = = vo1 vo2 vicm vo1 vicm ---------vo2 vicm --------- RD 2RSS -----------– = 2RSS 1 gm ⁄ .
vo1 vo2, = vod vod vo2 vo1 0 = – = vs 2iRSS = ( ) RD, Δ Q1 RD Q2 RD RD Δ + ( ), vicm vo1 RD 2RSS -----------vicm – 608 Chapter 8 Differential and Multistage Amplifiers and (8.47) Thus, (8.48) and we can find the common-mode gain as (8.49) which can be expressed in the alternate form (8.49′) It follows that a mismatch in the drain resistances causes the differential amplifier to have a finite common-mode gain. Thus, a portion of the interference or noise signal will appear as a component of A measure of the effectiveness of the differential amplifier in amplifying differential-mode signals and rejecting common-mode interference is the ratio of the magnitude of its differential gain to the magnitude of its common-mode gain .
This ratio is termed common-mode rejection ratio (CMRR). Thus, (8.50a) and is usually expressed in decibels, (8.50b) For the case of a MOS differential amplifier with drain resistances that exhibit a mis-match the CMRR can be found as the ratio of in Eq. (8.35) to in Eq. (8.49), thus (8.50c) It follows that to obtain a high CMRR, we should utilize a bias current source with a high output resistance , and we should strive to obtain a high degree of matching between the drain resistances (i.e., keep small).
Effect of gm Mismatch on CMRR Another possible mismatch between the two halves of the MOS differential pair is a mismatch in of the two transistors. For the purpose of vo2 RD RD Δ + 2RSS -----------------------vicm – vod vo2 vo1 RD Δ 2RSS -----------vicm – = – = Acm Acm vod vicm ---------RD Δ 2RSS -----------– = ≡ Acm RD 2RSS -----------⎝ ⎠ ⎛ ⎞ RD Δ RD ----------⎝ ⎠ ⎛ ⎞ – = vicm vod.
Ad Acm CMRR Ad Acm ------------≡ CMRR (dB) 20 log Ad Acm -----------= RD RD, Δ Ad Acm CMRR 2gmRSS ( ) RD RD ⁄ Δ ( ) = RSS RD RD ⁄ Δ 8.7 A MOS differential pair operated at a bias current of 0.8 mA employs transistors with W/L = 100 and mA/V2, using k and k Find the differential gain, the common-mode gain when the drain resistances have a 1% mismatch, and the CMRR.
Ans. 20 V/V; 0.001 V/V; 86 dB μn Cox 0.2 = RD 5 = Ω RSS 25 = Ω.
EXERCISE gm 8.2 Small-Signal Operation of the MOS Differential Pair 609 finding the effect of a mismatch on CMRR, let (8.51) (8.52) That is, (8.53) Since the circuit is no longer symmetrical, we cannot employ the common-mode half-circuit. Rather, we shall return to the original circuit of Fig. 8.13(a) and replace each of and with its T equivalent-circuit model. The result is the equivalent circuit shown in Fig.
8.14. Examination of this circuit reveals that the voltages between gate and source for the two transistors are equal (and equal to ). Thus, (8.54) From which we can obtain as (8.55) RD RD RSS i1 i1 i2 i2 vicm vicm g2 g1 gm2 1 gm1 1 S vo1 vo2 vod (i1 i2) Figure 8.14 Analysis of the MOS differential amplifier with an input common-mode signal vicm in the case the two transistors have a gm mismatch.
gm gm1 gm 1 2 --- gm Δ + = gm2 gm 1 2 ---– gm Δ = gm1 gm2 gm Δ = – Q1 Q2 vicm vs – i1 1 gm1 ⁄ ( ) i2 1 gm2 ⁄ ( ) = i1 i2 + i1 i2 i1 1 gm2 gm1 --------+ ⎝ ⎠ ⎛ ⎞ = + 610 Chapter 8 Differential and Multistage Amplifiers Now the voltage between the gate of and ground which is equal to can be expressed as which can be rearranged to obtain in terms of as (8.56) We can then use Eq. (8.54) together with Eq. (8.56) to express as (8.57) The voltages and can now be obtained: (8.58) (8.59) The differential output voltage is then obtained as (8.60) Substituting for and from Eqs. (8.51) and (8.52), respectively, gives Thus the common-mode gain resulting from a mismatch can be expressed as (8.61) which can be approximated by (8.62) and the corresponding CMRR will be (8.63) Thus to keep CMRR high, we have to use a biasing current source with a high output resis-tance and, of course, strive to maintain a high degree of matching between and Q1 vicm vicm i1 gm1 ⁄ i1 i2 + ( )RSS + = i1 gm1 ⁄ i1 1 gm2 gm1 --------+ ⎝ ⎠ ⎛ ⎞RSS + = i1 vicm i1 gm1vicm 1 gm1 gm2 + ( )RSS + ----------------------------------------------= i2 i2 gm2vicm 1 gm1 gm2 + ( )RSS + ----------------------------------------------= vo1 vo2 vo1 i1RD gm1RD 1 gm1 gm2 + ( )RSS + ----------------------------------------------vicm – = – = vo2 i2RD gm2RD 1 gm1 gm2 + ( )RSS + ----------------------------------------------vicm – = – = vod vod vo2 vo1 gm1 gm2 – ( )RD 1 gm1 gm2 + ( )RSS + ----------------------------------------------vicm = – = gm1 gm2 vod gmRD Δ 1 2 gmRSS + -----------------------------vicm = gm Δ Acm vod vicm ---------gmRD Δ 1 2 gmRSS + -----------------------------= ≡ Acm RD 2RSS -----------⎝ ⎠ ⎛ ⎞ gm Δ gm ---------⎝ ⎠ ⎛ ⎞ CMRR 2gmRSS ( ) gm Δ gm ---------⎝ ⎠ ⎛ ⎞ = RSS Q1 Q2.
8.8 For the MOS amplifier specified in Exercise 8.7, compute the CMRR resulting from a 1% mis-match in Ans. 86 dB gm.
EXERCISE 8.2 Small-Signal Operation of the MOS Differential Pair 611 In this example we consider the design of the current source that supplies the bias current of a MOS differential amplifier. Let it be required to achieve a CMRR of 100 dB and assume that the only source of mismatch between and is a 2% mismatch in their W/L ratios. Let I = 200 μA and assume that all transistors are to be operated at V. For the 0.18-μm CMOS fabrication process available, V/μm. If a simple current source is utilized for I, what channel length is required? If a cascode current source is utilized, what channel length is needed for the two transis-tors in the cascode?
Solution A mismatch in W/L results in a mismatch that can be found from the expression of (8.64) It can be seen that an error of 2% in W/L will result in an error in of 1%. That is, the 2% mis-match in the W/L ratios of and will result in a 1% mismatch in their values. The resulting CMRR can be found from Eq. (8.64), repeated here: Now, a 100-dB CMRR corresponds to a ratio of ; thus, (8.65) The value of can be found from mA/V Substituting in Eq. (8.65) gives k Now if the current source is implemented with a single transistor, its must be k Thus, k Substituting I = 200 μA, we find the required value of as V Since , the required value of L will be L = 20 μm which is very large!
Q1 Q2 VOV 0.2 = V′ A 5 = gm gm: gm 2 μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ID = gm Q1 Q2 gm CMRR 2gmRSS ( ) gm Δ gm ---------⎝ ⎠ ⎛ ⎞ ⁄ = 105 105 2gmRSS ( ) 0.01 ⁄ = gm gm 2ID VOV ---------2 I 2 ⁄ ( ) × VOV -----------------------= = 2 0.1 × 0.2 ----------------1 = = RSS 500 = Ω ro ro RSS 500 = = Ω VA I ------500 = Ω VA VA 100 = VA V ′ A L 5L = = Example 8.3 612 Chapter 8 Differential and Multistage Amplifiers Differential versus Single-Ended Output The above study of common-mode rejec-tion was predicated on the assumption that the output of the differential amplifier is taken differentially, that is, between the drains of and In some cases one might decide to take the output single-endedly; that is, between one of the drains and ground. If this is done, the CMRR is reduced dramatically. This can be seen from the above analysis, where the common-mode gain in the absence of mismatches is zero if the output is taken differentially and finite (Eq. 8.44) if the output is taken single-endedly. When mismatches are taken into account, the CM gain for the differential-output case departs from zero but remains much lower than the value obtained for single-ended output (Eq. 8.44).
We conclude that to obtain a large CMRR, the output of the differential amplifier must be taken differentially. The subject of converting the output signal from differential to single-ended without loss of CMRR will be studied in Section 8.5.
8.3 The BJT Differential Pair Figure 8.15 shows the basic BJT differential-pair configuration. It is very similar to the MOSFET circuit and consists of two matched transistors, Q1 and Q2, whose emitters are joined together and biased by a constant-current source I. The latter is usually implemented by a transistor circuit of the type studied in Sections 7.4 and 7.5. Although each collector is shown connected to the positive supply voltage VCC through a resistance RC, this connection is not essential to the operation of the differential pair—that is, in some applications the two collectors may be connected to current sources rather than resistive loads. It is essential, though, that the collector circuits be such that Q1 and Q2 never enter saturation.
Example 8.3 continued Using a cascode current source, we have where mA/V Thus, k and the required now becomes V which implies a channel length for each of the two transistors in the cascode of μm a considerable reduction from the case of a simple current source.
RSS gmro ( )ro = gm 2I VOV ---------2 0.2 × 0.2 ----------------2 = = = 500 2 ro 2 × = ro 15.81 = Ω VA 15.81 VA I ------VA 0.2 -------= = VA 3.16 = L 3.16 V ′ A ----------3.16 5 ----------0.63 = = = Q1 Q2.
8.3 The BJT Differential Pair 613 8.3.1 Basic Operation To see how the BJT differential pair works, consider first the case of the two bases joined together and connected to a common-mode voltage V CM. That is, as shown in Fig. 8.16(a), vB1 = vB2 = V CM. Since Q1 and Q2 are matched, and assuming an ideal bias current source I with infi-nite output resistance, it follows that the current I will remain constant and from symmetry that I will divide equally between the two devices. Thus iE1 = iE2 = , and the voltage at the + – + – Figure 8.15 The basic BJT differential-pair configuration.
VEE (a) (b) VEE I 0 Figure 8.16 Different modes of operation of the BJT differential pair: (a) the differential pair with a common-mode input voltage V CM; (b) the differential pair with a “large” differential input signal; (c) the dif-ferential pair with a large differential input signal of polarity opposite to that in (b); (d) the differential pair with a small differential input signal vi. Note that we have assumed the bias current source I to be ideal (i.e., it has an infinite output resistance) and thus I remains constant with the change in V CM.
I 2 ⁄ 614 Chapter 8 Differential and Multistage Amplifiers emitters will be VCM − VBE, where VBE is the base–emitter voltage (assumed in Fig 8.16a to be approximately 0.7 V) corresponding to an emitter current of . The voltage at each collector will be , and the difference in voltage between the two collectors will be zero.
Now let us vary the value of the common-mode input voltage V CM. Obviously, as long as Q1 and Q2 remain in the active region, and the current source I has sufficient voltage across it to operate properly, the current I will still divide equally between Q1 and Q2, and the volt-ages at the collectors will not change. Thus the differential pair does not respond to (i.e., it rejects) changes in the common-mode input voltage.
As another experiment, let the voltage vB2 be set to a constant value, say, zero (by grounding B2), and let vB1 = +1 V (see Fig. 8.16b). With a bit of reasoning it can be seen that Q1 will be on and conducting all of the current I and that Q2 will be off. For Q1 to be on (with VBE1 = 0.7 V), the emitter has to be at approximately +0.3 V, which keeps the EBJ of Q2 reverse-biased. The collector voltages will be vC1 = VCC − αIRC and vC2 = V CC.
Let us now change vB1 to −1 V (Fig. 8.16c). Again with some reasoning it can be seen that Q1 will turn off, and Q2 will carry all the current I. The common emitter will be at −0.7 V, which means that the EBJ of Q1 will be reverse biased by 0.3 V. The collector voltages will be vC1 = VCC and vC2 = VCC − αIRC.
From the foregoing, we see that the differential pair certainly responds to large difference-mode (or differential) signals. In fact, with relatively small difference voltages we are able to steer the entire bias current from one side of the pair to the other. This current-steering property of the differential pair allows it to be used in logic circuits, as will be demonstrated in Chapter 14. To use the BJT differential pair as a linear amplifier, we apply a very small differential signal (a few millivolts), which will result in one of the transistors conducting a current of ; the current in the other transistor will be , with ΔI being proportional to the difference input voltage (see Fig. 8.16d). The output voltage taken between the two collectors will be 2α ΔIRC, which is proportional to the differential input signal vi. The small-signal operation of the differential pair will be studied shortly.
Figure 8.16 continued.
VEE (c) VEd (d) I 2 ⁄ V CC 1 2 ---αIRC – I 2 ΔI + ⁄ I 2 ΔI – ⁄ 8.3 The BJT Differential Pair 615 8.3.2 Input Common-Mode Range Refer to the circuit in Fig. 8.16(a). The allowable range of is determined at the upper end by and leaving the active mode and entering saturation. Thus (8.66) The lower end of the range is determined by the need to provide a certain minimum voltage across the current source I to ensure its proper operation. Thus, (8.67) 8.9 Find vE, vC1, and vC2 in the circuit of Fig. E8.9. Assume that of a conducting transistor is ap-proximately 0.7 V and that α 1.
Ans. +0.7 V; −5 V; −0.7 V vBE 5 V 1 k 0.5 V vC1 1 k 5 V vC2 vE Q1 Q2 1 k Figure E8.9 EXERCISE VCM Q1 Q2 VCMmax VC 0.4 VCC α I 2 ---RC – 0.4 + = + VCM VCS VCMmin VEE – VCS VBE + + = 8.10 Determine the input common-mode range for a bipolar differential amplifier operating from -V power supplies and biased with a simple current source that delivers a constant current of 0.4 mA and requires a minimum of 0.3 V for its proper operation. The collector resistances k Ans. V to +1.9 V 2.5 ± RC 5 = Ω.
1.5 – EXERCISE 616 Chapter 8 Differential and Multistage Amplifiers 8.3.3 Large-Signal Operation We now present a general analysis of the BJT differential pair of Fig. 8.15. If we denote the voltage at the common emitter by vE and neglecting the Early effect, the exponential rela-tionship applied to each of the two transistors may be written (8.68) (8.69) These two equations can be combined to obtain which can be manipulated to yield (8.70) (8.71) The circuit imposes the additional constraint (8.72) Using Eq. (8.72) together with Eqs. (8.70) and (8.71) and substituting vB1 − vB2 = vid gives (8.73) (8.74) The collector currents iC1 and iC2 can be obtained simply by multiplying the emitter currents in Eqs. (8.73) and (8.74) by α, which is normally very close to unity.
The fundamental operation of the differential amplifier is illustrated by Eqs. (8.73) and (8.74). First, note that the amplifier responds only to the difference voltage vid. That is, if vB1 = vB2 = VCM, the current I divides equally between the two transistors irrespective of the value of the common-mode voltage V CM. This is the essence of differential-amplifier opera-tion, which also gives rise to its name.
Another important observation is that a relatively small difference voltage vid will cause the current I to flow almost entirely in one of the two transistors. Figure 8.17 shows a plot of the two collector currents (assuming α 1) as a function of the differential input signal. This is a normalized plot that can be used universally. Observe that a difference voltage of about 4VT (100 mV) is sufficient to switch the current almost entirely to one side of the BJT pair.
Note that this is much smaller than the corresponding voltage for the MOS pair, VOV. The fact that such a small signal can switch the current from one side of the BJT differential pair to the other means that the BJT differential pair can be used as a fast current switch (Chapter 14).
iE1 IS α ----e vB1−vE ( ) VT ⁄ = iE2 IS α ----e vB2−vE ( ) VT ⁄ = iE1 iE2 ------e vB1−vB2 ( ) VT ⁄ = iE1 iE1 iE2 + ------------------1 1 e vB2−vB1 ( ) VT ⁄ + ------------------------------------= iE2 iE1 iE2 + ------------------1 1 e vB1−vB2 ( ) VT ⁄ + ------------------------------------= iE1 iE2 + I = iE1 I 1 e −vid VT ⁄ + -------------------------= iE2 I 1 e vid VT ⁄ + -----------------------= 2 8.3 The BJT Differential Pair 617 The nonlinear transfer characteristics of the differential pair, shown in Fig. 8.17, will not be utilized any further in this chapter. Rather, in the following we shall be interested specif-ically in the application of the differential pair as a small-signal amplifier. For this purpose, the difference input signal is limited to less than about in order that we may operate on a linear segment of the characteristics around the midpoint x (in Fig. 8.17).
Before leaving the large-signal operation of the differential BJT pair, we wish to point out an effective technique frequently employed to extend the linear range of operation. It consists of including two equal resistances Re in series with the emitters of Q1 and Q2, as shown in Fig. 8.18(a). The resulting transfer characteristics for three different values of Re are sketched in Fig. 8.18(b). Observe that expansion of the linear range is obtained at the expense of reduced Gm (which is the slope of the transfer curve at vid = 0) and hence reduced gain. This result should come as no surprise; Re here is performing in exactly the same way as the emitter resistance Re does in the CE amplifier with emitter degeneration (see Section 6.6.4). Finally, we also note that this linearization technique is in effect the bipolar counterpart of the technique employed for the MOS differential pair (Fig. 8.7). In the latter case, however, VOV was varied by changing the transistors’ ratio, a design tool with no counterpart in the BJT. Figure 8.17 Transfer characteristics of the BJT differential pair of Fig. 8.15 assuming α 1.
vid VT iC I VT 2 ⁄ W L ⁄ 8.11 For the BJT differential pair of Fig. 8.15, find the value of input differential signal that is sufficient to cause iE1 = 0.99I.
Ans. 115 mV EXERCISE 618 Chapter 8 Differential and Multistage Amplifiers 8.3.4 Small-Signal Operation In this section we shall study the application of the BJT differential pair in small-signal amplification. Figure 8.19 shows the BJT differential pair with a difference voltage signal vid applied between the two bases. Implied is that the dc level at the input—that is, the common-mode input voltage—has been somehow established. For instance, one of the two input terminals can be grounded and vid applied to the other input terminal. Alternatively, the differential amplifier may be fed from the output of another differential amplifier. In the latter case, the voltage at one of the input terminals will be while that at the other input terminal will be .
(a) I Re RC Q1 Q2 RC VCC Re vB1 vC1 iC1 vB2 vC2 iC2 Figure 8.18 The transfer characteristics of the BJT differential pair (a) can be linearized (b) (i.e., the linear range of operation can be extended) by including resistances in the emitters.
(b) 4 8 12 16 20 24 1.0 0.2 0 0.4 0.6 Normalized collector current, iCI 0.8 0 4 8 12 16 20 24 vidVT iC2I iC1I IRe 0 IRe 20VT IRe 10VT IRe 0 IRe 10VT IRe 20VT V CM vid 2 ⁄ + V CM vid 2 ⁄ – 8.3 The BJT Differential Pair 619 The Collector Currents When vid Is Applied For the circuit of Fig. 8.19, we may use Eqs. (8.73) and (8.74) to write (8.75) (8.76) Multiplying the numerator and the denominator of the right-hand side of Eq. (8.75) by gives Assume that vid 2VT. We may thus expand the exponential in a series and retain only the first two terms: iC1 Thus (8.77) Similar manipulations can be applied to Eq. (8.76) to obtain (8.78) Equations (8.77) and (8.78) tell us that when vid = 0, the bias current I divides equally between the two transistors of the pair. Thus each transistor is biased at an emitter current of . When a “small-signal” vid is applied differentially (i.e., between the two bases), the collector current Figure 8.19 The currents and voltages in the differential amplifier when a small differential input signal vid is applied.
vid vid vid vid vid vid vid vid vid V iC1 αI 1 e −vid VT ⁄ + -------------------------= iC2 αI 1 e vid VT ⁄ + -----------------------= evid 2VT ⁄ iC1 αIe vid 2VT ⁄ e vid 2VT ⁄ e −vid 2V T ⁄ + -----------------------------------------= e vid 2V T ⁄ ± αI 1 vid 2VT ⁄ + ( ) 1 vid 2VT 1 vid 2VT ⁄ – + ⁄ + --------------------------------------------------------------iC1 αI 2 ------αI 2VT ---------vid 2 -----+ = iC2 αI 2 ------ − αI 2VT ---------vid 2 -----= I 2 ⁄ 620 Chapter 8 Differential and Multistage Amplifiers of Q1 increases by an increment ic and that of Q2 decreases by an equal amount. This ensures that the sum of the total currents in Q1 and Q2 remains constant, as constrained by the current-source bias. The incremental (or signal) current component ic is given by (8.79) Equation (8.79) has an easy interpretation. First, note from the symmetry of the circuit (Fig. 8.19) that the differential signal vid should divide equally between the base–emitter junctions of the two transistors. Thus the total base–emitter voltages will be where VBE is the dc BE voltage corresponding to an emitter current of . Therefore, the col-lector current of Q1 will increase by and the collector current of Q2 will decrease by . Here gm denotes the transconductance of Q1 and of Q2, which are equal and given by (8.80) Thus Eq. (8.79) simply states that ic = gmvid/2.
An Alternative Viewpoint There is an extremely useful alternative interpretation of the results above. Assume the current source I to be ideal. Its incremental resistance then will be infinite. Thus the voltage vid appears across a total resistance of 2re, where (8.81) Correspondingly there will be a signal current ie, as illustrated in Fig. 8.20, given by (8.82) Figure 8.20 A simple technique for determining the signal currents in a differential amplifier excited by a differential voltage signal vid; dc quantities are not shown.
ic αI 2V T ---------vid 2 -----= vBE Q1 V BE + vid 2 -----= vBE Q2 V BE − vid 2 -----= I 2 ⁄ gmvid 2 ⁄ gmvid 2 ⁄ gm IC VT -----αI 2 ⁄ VT -------------= = re V T IE -----VT I 2 ⁄ ---------= = ie vid 2re -------= RC RC ib Rid vid 2re avid 2re vid avid 2re vod RC avid 2re RC avid 2re ib vid (b 1)2re re VT I2 Q1 Q2 8.3 The BJT Differential Pair 621 Thus the collector of Q1 will exhibit a current increment ic and the collector of Q2 will exhibit a current decrement ic: (8.83) Note that in Fig. 8.20 we have shown signal quantities only. It is implied, of course, that each transistor is biased at an emitter current of .
This method of analysis is particularly useful when resistances are included in the emit-ters, as shown in Fig. 8.21. For this circuit we have (8.84) Input Differential Resistance Unlike the MOS differential amplifier, which has an infinite input resistance, the bipolar differential pair exhibits a finite input resistance, a result of the finite β of the BJT.
The input differential resistance is the resistance seen between the two bases; that is, it is the resistance seen by the differential input signal vid. For the differential amplifier in Figs. 8.19 and 8.20 it can be seen that the base current of Q1 shows an increment ib and the base current of Q2 shows an equal decrement, (8.85) Thus the differential input resistance Rid is given by (8.86) Figure 8.21 A differential amplifier with emitter resistances. Only signal quantities are shown (in color).
RC Re Re RC Rid vid avid 2(re Re) vid 2re 2Re avid 2(re Re) ib vid 2(b 1) (re Re) ib vid 2(b 1) (re Re) Q1 Q2 2(re Re) aRC vid 2(re Re) aRC vid vod ic αie αvid 2re ---------gm vid 2 -----= = = I 2 ⁄ ie vid 2re 2Re + ----------------------= ib ie β 1 + ------------vid 2re ⁄ β 1 + -----------------= = Rid vid ib -----≡ β + 1 ( )2re 2rπ = = 622 Chapter 8 Differential and Multistage Amplifiers This result is just a restatement of the familiar resistance-reflection rule; namely, the resistance seen between the two bases is equal to the total resistance in the emitter circuit multiplied by (β + 1).
We can employ this rule to find the input differential resistance for the circuit in Fig. 8.21 as (8.87) Differential Voltage Gain We have established that for small difference input voltages (vid 2VT; i.e., vid smaller than about 20 mV), the collector currents are given by (8.88) (8.89) where (8.90) Thus the total voltages at the collectors will be (8.91) (8.92) The quantities in parentheses are simply the dc voltages at each of the two collectors.
As in the MOS case, the output voltage signal of a bipolar differential amplifier can be taken differentially (i.e., between the two collectors, vod = vc2 – vc1). The differential gain of the dif-ferential amplifier will be (8.93) For the differential amplifier with resistances in the emitter leads (Fig. 8.21), the differ-ential gain is given by (8.94) This equation is a familiar one: It states that the voltage gain is equal to the ratio of the total resistance in the collector circuit (2RC) to the total resistance in the emitter circuit (2re + 2Re ).
The Differential Half-Circuit As in the MOS case, the differential gain of the BJT dif-ferential amplifier can be obtained by considering its differential half-circuit. Figure 8.22(a) shows a differential amplifier fed by a differential signal vid that is applied in a complementary (push–pull or balanced) manner. That is, while the base of Q1 is raised by , the base of Q2 is lowered by . We have also included the output resistance REE of the bias current source. From symmetry, it follows that the signal voltage at the emitters will be zero. Thus the circuit is equivalent to the two common-emitter amplifiers shown in Fig. 8.22(b), where each of the two transistors is biased at an emitter current of . Note that the finite output resistance REE of the current source will have no effect on the operation. The equivalent circuit in Fig.
8.22(b) is valid for differential operation only.
In many applications the differential amplifier is not fed in a complementary fashion; rather, the input signal may be applied to one of the input terminals while the other terminal Rid β 1 + ( ) 2re 2Re + ( ) = iC1 IC gm vid 2 -----+ = iC2 IC − gm vid 2 -----= IC αI 2 ------= vC1 VCC ICRC – ( ) gmRC – vid 2 -----= vC2 VCC ICRC – ( ) gmRC + vid 2 -----= Ad vod vid ------gmRC = = Ad α 2RC ( ) 2re 2Re + ---------------------- RC re Re + ----------------= vid 2 ⁄ vid 2 ⁄ I 2 ⁄ 8.3 The BJT Differential Pair 623 is grounded, as shown in Fig. 8.23. In this case the signal voltage at the emitters will not be zero, and thus the resistance REE will have an effect on the operation. Nevertheless, if REE is large (REE re), as is usually the case,1 then vid will still divide equally (approximately) between the two junctions, as shown in Fig. 8.23. Thus the operation of the differential amplifier in this case will be almost identical to that in the case of symmetric feed, and the common-emitter equivalence can still be employed. Since in Fig. 8.22, vo2 = −vo1 = vod /2, the two common-emitter transistors in Fig. 8.22(b) yield similar results about the performance of the differential amplifier. Thus only one is needed to analyze the differential small-signal operation of the differential amplifier, and it Figure 8.22 Equivalence of the BJT differential amplifier in (a) to the two common-emitter amplifiers in (b). This equivalence applies only for differential input signals. Either of the two common-emitter amplifiers in (b) can be used to find the differential gain, differential input resistance, frequency response, and so on, of the differential amplifier.
1Note that REE appears in parallel with the much smaller re of Q2. RC RC vo2 vo1 REE Q1 Q2 0 V vid 2 vid 2 (a) vod RC RC vo2 = Q1 Q2 vid 2 vod 2 vo1 = vod 2 vid 2 (b) Biased at I 2 RC RC vo2 vo1 ve vid 2 REE REE re Q1 Q2 vid 2 vid vid 2 REE ve i 0 vod Figure 8.23 The differential amplifier fed in a single-ended fashion.
624 Chapter 8 Differential and Multistage Amplifiers is known as the differential half-circuit. If we take the common-emitter transistor fed with +vid /2 as the differential half-circuit and replace the transistor with its low-frequency, equivalent-circuit model, the circuit in Fig. 8.24 results. In evaluating the model parameters rπ, gm, and ro, we must recall that the half-circuit is biased at I/2. The voltage gain of the differential amplifier is equal to the voltage gain of the half-circuit—that is, vo1/(vid/2). Here, we note that including ro will modify the gain expression in Eq. (8.93) to (8.95) The input differential resistance of the differential amplifier is twice that of the half-circuit— that is, 2rπ. Finally, we note that the differential half-circuit of the amplifier of Fig. 8.21 is a common-emitter transistor with a resistance Re in the emitter lead.
8.3.5 Common-Mode Gain and CMRR Figure 8.25 shows a bipolar differential amplifier with an input common-mode signal Here is the output resistance of the bias current source I. We wish to find the voltages that result from at the collectors of and and and between the two collectors, Toward that end, we make use of the common-mode half-circuits shown in Fig. 8.25(b). The signal that appears at the collector of in response to will be (8.96) Similarly, will be (8.97) where we have neglected the transistor for simplicity. The differential output signal can be obtained as Thus, while the voltages at the two collectors will contain common-mode noise or interfer-ence components, the output differential voltage will be free from such interference. This condition, however, is based on the assumption of perfect matching between the two sides of the differential amplifier. Any mismatch will result in acquiring a component propor-tional to For example, consider the case of a mismatch between the two collector resistances: If the collector of has a collector resistance Figure 8.24 Equivalent-circuit model of the differential half-circuit formed by Q1 in Fig. 8.22(b).
vo1 = vod 2 Ad gm RC ro || ( ) = vicm.
REE vicm Q1 Q2, vo1 vo2, vod.
vo1 Q1 vicm vo1 αRC re 2REE + -----------------------vicm – = vo2 vo2 αRC re 2REE + -----------------------vicm – = ro, vod vod vo2 vo1 0 = – = vod vicm.
RC Δ Q1 RC, 8.3 The BJT Differential Pair 625 and the collector of has a collector resistance then the differential output voltage will be and the common-mode gain will be (8.98) Since , Eq. (8.98) can be approximated and written in the form (8.99) The common-mode rejection ratio can now be found from together with using Eqs. (8.93) and (8.99), with the result that (8.100) RC RC vo2 vicm vicm vo1 (a) REE Q1 Q2 (b) RC RC vo2 vicm vicm vo1 2REE 2REE Biased at I2 Q1 Q2 vod Figure 8.25 (a) The differential amplifier fed by a common-mode input signal vicm. (b) Equivalent “half-circuits” for common-mode calculations.
vo1 αRC 2REE re + -----------------------vicm – = Q2 RC RC Δ + ( ), vo2 α RC RC Δ + ( ) 2REE re + --------------------------------vicm – = vod vod vo2 vo1 – ≡ α RC Δ 2REE re + -----------------------vicm – = Acm vod vicm ---------α RC Δ 2REE re + -----------------------– = ≡ α 1 re 2REE, Acm RC 2REE ------------⎝ ⎠ ⎛ ⎞ RC Δ RC ----------⎝ ⎠ ⎛ ⎞ – CMRR Ad Acm -----------= CMRR 2gmREE ( ) RC Δ RC ----------⎝ ⎠ ⎛ ⎞ = 626 Chapter 8 Differential and Multistage Amplifiers which is similar in form to the expression for the MOS pair [Eq. (8.50)]. Thus, to obtain a high CMRR, we design the current source to have a large output resistance and strive for close matching of the collector resistances.
Common-Mode Input Resistance The definition of the common-mode input resistance is illustrated in Fig. 8.26(a). Figure 8.26(b) shows the equivalent common-mode half-circuit; its input resistance is The value of can be determined by analyzing the circuit of Fig. 8.26(b) while taking into account (because and can be equal to, or larger than, ). The analysis is straightforward but tedious and can be shown [Problem 8.79] to yield the following result (8.101) Figure 8.26 (a) Definition of the input common-mode resistance Ricm. (b) The equivalent common-mode half-circuit.
REE Ricm Q1 Q2 vicm + – 2REE vicm 2Ricm (b) REE Ricm 2Ricm.
2Ricm ro REE RC ro Ricm βREE 1 RC βro ⁄ + 1 RC 2REE + ro -------------------------+ -----------------------------------The differential amplifier in Fig. 8.27 uses transistors with β = 100. Evaluate the following: (a) The input differential resistance Rid.
(b) The overall differential voltage gain vod/ vsig (neglect the effect of ro).
(c) The worst-case common-mode gain if the two collector resistances are accurate to within ±1%.
(d) The CMRR, in dB.
(e) The input common-mode resistance (assuming that the Early voltage VA = 100 V).
Example 8.4 8.3 The BJT Differential Pair 627 Solution (a) Each transistor is biased at an emitter current of 0.5 mA. Thus The input differential resistance can now be found as (b) The voltage gain from the signal source to the bases of Q1 and Q2 is The voltage gain from the bases to the output is Figure 8.27 Circuit for Example 8.4.
vid Rid vod + + – – re1 re2 VT IE ------25 mV 0.5 mA ------------------50 Ω = = = = Rid 2 β 1 + ( ) re RE + ( ) = 2 101 50 150 + ( ) × × 40 kΩ = vid vsig -------Rid Rsig Rid + ----------------------= 40 5 5 40 + + ------------------------= 0.8 V/V = vod vid ------- Total resistance in the collectors Total resistance in the emitters -----------------------------------------------------------------------------628 Chapter 8 Differential and Multistage Amplifiers Example 8.4 continued The overall differential voltage gain can now be found as (c) Using Eq. (8.99), where ΔRC = 0.02RC in the worst case. Thus, (d) (e) Using Eq. (8.101), = 2RC 2 r e RE + ( ) ------------------------- = 2 10 × 2 50 150 + ( ) 10–3 × ---------------------------------------------- = 50 V/V Ad vod vsig -------= = vid vsig -------vod vid ------- = 0.8 50 = 40 × V/V Acm = RC 2REE ------------ ΔRC RC ----------Acm 10 2 200 × ------------------0.02 5 10–4 × = × V/V = CMRR 20 log Ad Acm -----------= 20 = log 40 5 10–4 × -------------------98 dB = ro V A I 2 ⁄ ---------100 0.5 ---------200 kΩ = = = Ricm 6.6 = MΩ 8.12 For the circuit in Fig. 8.19, let I = 1 mA, VCC = 15 V, RC = 10 kΩ, with α = 1, and let the input voltages be: vB1 = 5 + 0.005 sin 2π × 1000t, volts, and vB2 = 5 − 0.005 sin 2π × 1000t, volts. (a) If the BJTs are specified to have vBE of 0.7 V at a collector current of 1 mA, find the voltage at the emitters. (b) Find gm for each of the two transistors. (c) Find iC for each of the two transistors. (d) Find vC for each of the two transistors. (e) Find the voltage between the two collectors. (f) Find the gain experienced by the 1000-Hz signal.
Ans. (a) 4.317 V; (b) 20 mA/V; (c) iC1 = 0.5 + 0.1 sin 2π × 1000t, mA and iC2 = 0.5 – 0.1 sin 2π × 1000t, mA; (d) vC1 = 10 – 1 sin 2π × 1000t, V and vC2 = 10 + 1 sin 2π × 1000t, V; (e) vC2 – vC1 = 2 sin 2π × 1000t, V; (f) 200 V/V 8.13 A bipolar differential amplifier utilizes a simple (i.e., a single CE transistor) current source to supply a bias current I of 200 μA, and simple current-source loads formed by pnp transistors. For all tran-sistors, and V. Find , CMRR (if the two load transistors exhibit a 1% mismatch in their ’s), and Ans. 4 mA/V; 100 k ; 400 V/V; 50 k 50 k 86 dB; 1.67 M β 100 = VA 10 = gm, RC, Ad Rid, REE, ro Ricm.
Ω Ω, Ω; Ω EXERCISES 8.4 Other Nonideal Characteristics of the Differential Amplifier 629 8.4 Other Nonideal Characteristics of the Differential Amplifier 8.4.1 Input Offset Voltage of the MOS Differential Pair Consider the basic MOS differential amplifier with both inputs grounded, as shown in Fig. 8.28(a). If the two sides of the differential pair were perfectly matched (i.e., Q1 and Q2 identical and RD1 = RD2 = RD), then current I would split equally between Q1 and Q2, and V O would be zero. But practical circuits exhibit mismatches that result in a dc output voltage V O even with both inputs grounded. We call VO the output dc offset voltage. More commonly, we divide VO by the differential gain of the amplifier, Ad, to obtain a quantity known as the input offset voltage, VOS, VOS = VO/Ad (8.102) We can see that if we apply a voltage –VOS between the input terminals of the differential amplifier, then the output voltage will be reduced to zero (see Fig. 8.28b). This observation gives rise to the usual definition of the input offset voltage. It should be noted, however, that since the offset voltage is a result of device mismatches, its polarity is not known a priori.
Three factors contribute to the dc offset voltage of the MOS differential pair: mismatch in load resistances, mismatch in W/L, and mismatch in Vt. We shall consider the three contrib-uting factors one at a time.
For the differential pair shown in Fig. 8.28(a) consider first the case where Q1 and Q2 are perfectly matched but RD1 and RD2 show a mismatch ΔRD; that is, (8.103) Figure 8.28 (a) The MOS differential pair with both inputs grounded. Owing to device and resistor mismatches, a finite dc output voltage VO results. (b) Application of a voltage equal to the input offset voltage VOS to the input terminals with opposite polarity reduces VO to zero.
RD1 RD ΔRD 2 ----------+ = (a) VOS Q1 Q2 0 V (b) RD1 RD2 VDD I 630 Chapter 8 Differential and Multistage Amplifiers (8.104) Because Q1 and Q2 are matched, the current I will split equally between them. Nevertheless, because of the mismatch in load resistances, the output voltages VD1 and VD2 will be Thus the differential output voltage VO will be (8.105) The corresponding input offset voltage is obtained by dividing VO by the gain gmRD and sub-stituting for gm from Eq. (8.30). The result is (8.106) Thus the offset voltage is directly proportional to VOV and, of course, to ΔR D/RD. As an exam-ple, consider a differential pair in which the two transistors are operating at an overdrive voltage of 0.2 V and each drain resistance is accurate to within ±1%. It follows that the worst-case resistor mismatch will be and the resulting input offset voltage will be Next, consider the effect of a mismatch in the W/L ratios of Q1 and Q2, expressed as (8.107) (8.108) Such a mismatch causes the current I to no longer divide equally between Q1 and Q2. Rather, because VGS1 = VGS2, the current conducted by each of Q1 and Q2 will be proportional to its W/L ratio, and we can easily show that (8.109) (8.110) Dividing the current difference, RD2 RD ΔRD 2 ----------– = V D1 = V DD I 2 --- RD ΔRD 2 ----------+ ⎝ ⎠ ⎛ ⎞ – V D2 = V DD I 2 --- RD ΔRD 2 ----------– ⎝ ⎠ ⎛ ⎞ – VO VD2 VD1 – = = I 2 ---⎝⎠ ⎛⎞ΔRD V OS V OV 2 ---------⎝ ⎠ ⎛ ⎞ΔRD RD ----------⎝ ⎠ ⎛ ⎞ = ΔRD RD ----------0.02 = V OS 0.1 0.02 × 2 mV = = W L -----⎝ ⎠ ⎛ ⎞ 1 W L -----1 2 ---Δ W L -----⎝ ⎠ ⎛ ⎞ + = W L -----⎝ ⎠ ⎛ ⎞ 2 W L -----1 2 ---Δ W L -----⎝ ⎠ ⎛ ⎞ – = I1 I 2 --- 1 Δ(W L) ⁄ 2(W L) ⁄ ---------------------+ = I2 I 2 --- 1 Δ(W L) ⁄ 2(W L) ⁄ ---------------------– = I 2 --- Δ(W L) ⁄ (W L) ⁄ ---------------------8.4 Other Nonideal Characteristics of the Differential Amplifier 631 by gm gives the input offset voltage (due to the mismatch in W/L values).2 Thus (8.111) Here again we note that VOS, resulting from a (W/L) mismatch, is proportional to VOV and, as expected, Δ(W/L).
Finally, we consider the effect of a mismatch ΔVt between the two threshold voltages, (8.112) (8.113) The current I1 will be given by which, for ΔVt 2(VGS – V t ) [that is, ΔV t 2VOV], can be approximated as Similarly, We recognize that and the current increment (decrement) in Q2 (Q1) is Dividing the current difference 2ΔI by gm gives the input offset voltage (due to ΔVt). Thus, VOS = ΔVt (8.114) a very logical result! For modern MOS technology ΔVt can be as high as a few mV. Finally, we note that since the three sources for offset voltage are not correlated, an estimate of the total input offset voltage can be found as (8.115) 2We are skipping a step in the derivation: Rather than multiplying the current difference by RC and di-viding the resulting output offset by Ad = gmRC, we are simply dividing the current difference by gm.
V OS V OV 2 ---------⎝ ⎠ ⎛ ⎞Δ(W L) ⁄ (W L) ⁄ ---------------------⎝ ⎠ ⎛ ⎞ = V t1 V t ΔV t 2 --------+ = V t2 V t ΔV t 2 --------– = I1 1 2 ---k n′ W L ----- V GS Vt ΔV t 2 --------– – ⎝ ⎠ ⎛ ⎞ 2 = 1 2 ---kn ′ W L ----- V GS V t – ( ) 2 1 ΔV t 2 V GS V t – ( ) ---------------------------– 2 = I1 1 2 ---kn ′ W L ----- V GS V t – ( ) 2 1 ΔV t V GS V t – -------------------– ⎝ ⎠ ⎛ ⎞ I2 1 2 ---kn ′ W L ----- V GS V t – ( ) 2 1 ΔV t V GS Vt – -------------------+ ⎝ ⎠ ⎛ ⎞ 1 2 ---kn ′ W L ----- V GS V t – ( ) 2 I 2 ---= ΔI I 2 --- ΔV t VGS V t – -------------------I 2 --- ΔVt V OV ---------= = V OS V OV 2 --------- ΔRD RD ----------⎝ ⎠ ⎛ ⎞ 2 V OV 2 --------- Δ(W L) ⁄ W L ⁄ ---------------------⎝ ⎠ ⎛ ⎞ 2 ΔVt ( ) 2 + + = 632 Chapter 8 Differential and Multistage Amplifiers 8.4.2 Input Offset Voltage of the Bipolar Differential Amplifier The offset voltage of the bipolar differential pair shown in Fig. 8.29(a) can be determined in a manner analogous to that used above for the MOS pair. Note, however, that in the bipolar case there is no analog to the Vt mismatch of the MOSFET pair. Here the output offset results from mismatches in the load resistances RC1 and RC2 and from junction area, β, and other mismatches in Q1 and Q2. Consider first the effect of the load mismatch. Let (8.116) (8.117) and assume that Q1 and Q2 are perfectly matched. It follows that current I will divide equally between Q1 and Q2, and thus Figure 8.29 (a) The BJT differential pair with both inputs grounded. Device mismatches result in a finite dc output V O. (b) Application of the input offset voltage VOS ≡ VO/Ad to the input terminals with opposite polarity reduces VO to zero.
8.14 For the MOS differential pair specified in Exercise 8.4, find the three components of the input offset voltage. Let ΔRD/RD = 2%, Δ(W/L)/(W/L) = 2%, and ΔVt = 2 mV. Use Eq. (8.115) to obtain an esti-mate of the total VOS.
Ans. 2 mV; 2 mV; 2 mV; 3.5 mV EXERCISE RC1 RC ΔRC 2 ----------+ = RC2 RC ΔRC 2 ----------– = VCC RC1 RC2 VO B1 B2 Q1 Q2 I (a) VCC RC1 RC 2 VOS Q1 Q2 I 0 V (b) 8.4 Other Nonideal Characteristics of the Differential Amplifier 633 Thus the output voltage will be and the input offset voltage will be (8.118) Substituting Ad = gmRC and gives (8.119) An important point to note is that in comparison to the corresponding expression for the MOS pair (Eq. 8.106) here the offset is proportional to VT rather than VOV/ 2. VT at 25 mV is 3 to 6 times lower than VOV/ 2. Hence bipolar differential pairs exhibit lower offsets than their MOS counterparts. As an example, consider the situation of collector resistors that are accurate to within ±1%. Then the worst case mismatch will be and the resulting input offset voltage will be Next consider the effect of mismatches in transistors Q1 and Q2. In particular, let the transistors have a mismatch in their emitter–base junction areas. Such an area mismatch gives rise to a proportional mismatch in the scale currents IS, (8.120) (8.121) Refer to Fig. 8.29(a) and note that VBE1 = VBE2. Thus, the current I will split between Q1 and Q2 in proportion to their IS values, resulting in (8.122) (8.123) It follows that the output offset voltage will be V C1 V CC αI 2 ------⎝ ⎠ ⎛ ⎞RC ΔRC 2 ----------+ ⎝ ⎠ ⎛ ⎞ – = V C2 V CC αI 2 ------⎝ ⎠ ⎛ ⎞RC ΔRC 2 ----------– ⎝ ⎠ ⎛ ⎞ – = V O V C2 V C1 – α I 2 ---⎝⎠ ⎛⎞ΔRC ( ) = = V OS α I 2 ⁄ ( ) ΔRC ( ) Ad ---------------------------------= gm αI 2 ⁄ VT -------------= V OS VT ΔRC RC ----------⎝ ⎠ ⎛ ⎞ = ΔRC RC ----------0.02 = V OS 25 0.02 × 0.5 mV = = IS1 IS ΔIS 2 --------+ = IS2 IS ΔIS 2 --------– = IE1 I 2 --- 1 ΔIS 2IS --------+ ⎝ ⎠ ⎛ ⎞ = IE2 I 2 --- 1 ΔIS 2IS --------– ⎝ ⎠ ⎛ ⎞ = V O α I 2 ---⎝⎠ ⎛⎞ΔIS IS --------⎝ ⎠ ⎛ ⎞RC = 634 Chapter 8 Differential and Multistage Amplifiers and the corresponding input offset voltage will be (8.124) As an example, an area mismatch of 4% gives rise to ΔIS /IS = 0.04 and an input offset voltage of 1 mV. Here again we note that the offset voltage is proportional to VT rather than to the much larger VOV, which determines the offset of the MOS pair due to Δ(W/L) mismatch.
Since the two contributions to the input offset voltage are usually not correlated, an esti-mate of the total input offset voltage can be found as (8.125) There are other possible sources for input offset voltage such as mismatches in the val-ues of β and ro. Some of these are investigated in the end-of-chapter problems. Finally, it should be noted that there is a popular scheme for compensating for the offset voltage. It involves introducing a deliberate mismatch in the values of the two collector resistances such that the differential output voltage is reduced to zero when both input terminals are grounded. Such an offset-nulling scheme is explored in Problem 8.81.
8.4.3 Input Bias and Offset Currents of the Bipolar Differential Amplifier In a perfectly symmetric differential pair the two input terminals carry equal dc currents; that is, (8.126) This is the input bias current of the differential amplifier.
Mismatches in the amplifier circuit and most importantly a mismatch in β make the two input dc currents unequal. The resulting difference is the input offset current, IOS, given as (8.127) Let then (8.128) (8.129) V OS V T ΔIS IS --------⎝ ⎠ ⎛ ⎞ = V OS VT ΔRC RC ----------⎝ ⎠ ⎛ ⎞ 2 VT ΔIS IS --------⎝ ⎠ ⎛ ⎞ 2 + = VT ΔRC RC ----------⎝ ⎠ ⎛ ⎞ 2 ΔIS IS --------⎝ ⎠ ⎛ ⎞ 2 + = IB1 IB2 I 2 ⁄ β 1 + ------------= = IOS IB1 IB2 – = β1 β Δβ 2 -------+ = β2 β Δβ 2 -------– = IB1 I 2 ---1 β 1 Δβ 2 ⁄ + + --------------------------------- I 2 ---1 β 1 + ------------ 1 Δβ 2β -------– ⎝ ⎠ ⎛ ⎞ = IB2 I 2 ---1 β 1 Δβ 2 ⁄ – + -------------------------------- I 2 ---1 β 1 + ------------ 1 Δβ 2β -------+ ⎝ ⎠ ⎛ ⎞ = 8.5 The Differential Amplifier with Active Load 635 (8.130) Formally, the input bias current IB is defined as follows: (8.131) Thus (8.132) As an example, a 10% β mismatch results in an offset current that is one-tenth the value of the input bias current.
Finally note that a great advantage of the MOS differential pair is that it does not suffer from a finite input bias current or from mismatches thereof!
8.4.4 A Concluding Remark We conclude this section by noting that the definitions presented here are identical to those presented in Chapter 2 for op amps. In fact, as will be seen in Chapter 12, it is the input differential stage in an op-amp circuit that primarily determines the op-amp dc offset volt-age, input bias and offset currents, and input common-mode range.
8.5 The Differential Amplifier with Active Load The differential amplifiers we have studied thus far have been of the differential output vari-ety; that is, the output is taken between the two drains (or two collectors) rather than between one of the drains (collectors) and ground. Taking the output differentially has two major advantages: 1. It decreases the common-mode gain and increases the common-mode rejection ratio (CMRR) dramatically. Recall that while the drain (collector) voltages change some-what in response to a common-mode input signal, the difference between the drain (collector) voltages remains essentially zero except for a small change due to the mismatches inevitably present in the circuit.
2. It increases the differential gain by a factor of 2 (6 dB) because the output is the dif-ference between two voltages of equal magnitude and opposite sign.
IOS I 2 β 1 + ( ) -------------------- Δβ β -------⎝ ⎠ ⎛ ⎞ = IB IB1 IB2 + 2 -------------------≡ I 2 β 1 + ( ) --------------------= IOS IB Δβ β -------⎝ ⎠ ⎛ ⎞ = 8.15 For a BJT differential amplifier utilizing transistors having β = 100, matched to 10% or better, and areas that are matched to 10% or better, along with collector resistors that are matched to 2% or better, find VOS, IB, and IOS. The dc bias current I is 100 μA.
Ans. 2.55 mV; 0.5 μA; 50 nA EXERCISE 636 Chapter 8 Differential and Multistage Amplifiers These advantages are sufficiently compelling that at least the first stage in an IC amplifier such as an op amp is differential-in, differential-out. The differential transmission of the signal on the chip also minimizes its susceptibility to corruption with noise and interference, which usually occur in a common-mode fashion. Nevertheless, it is usually required at some point to convert the signal from differential to single-ended; for instance, to connect it to an off-chip load. Figure 8.30 shows a block diagram of a three-stage amplifier in which the first two stages are of the differential-in, differential out type, and the third has a single-ended output, that is, an output that is referenced to ground. We now address the question of con-version from differential to single-ended.
8.5.1 Differential to Single-Ended Conversion Figure 8.31 illustrates the simplest, most basic approach for differential-to-single-ended conversion. It consists of simply ignoring the drain current signal of Q1 and eliminating its drain resistor altogether, and taking the output between the drain of Q2 and ground. The obvious drawback of this scheme is that we lose a factor of 2 (or 6 dB) in gain as a result of “wasting” the drain signal current of Q1. A much better approach would be to find a way of utilizing the drain-current signal of Q1, and that is exactly what the circuit we are about to discuss accomplishes.
A1 A2 A3 vid vo Figure 8.30 A three-stage amplifier consisting of two differential-in, differential-out stages, A1 and A2, and a differential-in, single-ended-out stage A3.
VSS VDD vo RD I vid2 vid2 Q1 Q2 Figure 8.31 A simple but inefficient approach for differential to single-ended conversion.
8.5 The Differential Amplifier with Active Load 637 8.5.2 The Active-Loaded MOS Differential Pair Figure 8.32(a) shows a MOS differential pair formed by transistors Q1 and Q2, loaded by a current mirror formed by transistors Q3 and Q4. To see how this circuit operates consider first the quiescent or equilibrium state with the two input terminals connected to a dc voltage equal to the common-mode equilibrium value, in this case 0 V, as shown in Fig. 8.32(b).
Assuming perfect matching, the bias current I divides equally between Q1 and Q2. The drain current of Q1, , is fed to the input transistor of the mirror, Q3. Thus, a replica of this cur-rent is provided by the output transistor of the mirror, Q4. Observe that at the output node the two currents balance each other out, leaving a zero current to flow out to the next stage or to a load (not shown). If Q4 is perfectly matched to Q3, its drain voltage will track the volt-age at the drain of Q3; thus in equilibrium the voltage at the output will be VDD − VSG3. It Figure 8.32 (a) The active-loaded MOS differential pair. (b) The circuit at equilibrium assuming perfect matching. (c) The circuit with a differential input signal applied and neglecting the ro of all transistors.
I 2 ⁄ I 2 ⁄ vO vG2 vG1 I VSS VDD Q1 Q2 Q3 Q4 (a) (b) VO VDD VSG3 I VDD Q1 Q2 Q4 Q3 0 VSG3 I2 I2 I2 I2 I2 (c) vo vid2 vid2 Q1 Q2 Q3 Q4 2i 0 V i i i 638 Chapter 8 Differential and Multistage Amplifiers should be noted, however, that in practical implementations, there will always be mis-matches, resulting in a net dc current at the output. In the absence of a load resistance, this current will flow into the output resistances of Q2 and Q4 and thus can cause a large devia-tion in the output voltage from the ideal value. Therefore, this circuit is always designed so that the dc bias voltage at the output node is defined by a feedback circuit rather than by sim-ply relying on the matching of Q4 and Q3. We shall see how this is done later.
Next, consider the circuit with a differential input signal vid applied to the input, as shown in Fig. 8.32(c). Since we are now investigating the small-signal operation of the circuit, we have removed the dc supplies (including the current source I). Also, for the time being let us ignore ro of all transistors. As Fig. 8.32(c) shows, a virtual ground will develop at the common-source terminal of Q1 and Q2. Transistor Q1 will conduct a drain signal current i = gm1vid/ 2, and transistor Q2 will conduct an equal but opposite current i. The drain signal cur-rent i of Q1 is fed to the input of the Q3 − Q4 mirror, which responds by providing a replica in the drain of Q4. Now, at the output node we have two currents, each equal to i, which sum together to provide an output current 2i. It is this factor of 2, which is a result of the current-mirror action, that makes it possible to convert the signal to single-ended form (i.e., between the output node and ground) with no loss of gain! If a load resistance is connected to the out-put node, the current 2i flows through it and thus determines the output voltage vo. In the absence of a load resistance, the output voltage is determined by the output current 2i and the output resistance of the circuit, as we shall shortly see.
8.5.3 Differential Gain of the Active-Loaded MOS Pair As we learned in Chapter 7, the output resistance ro of the transistor plays a significant role in the operation of active-loaded amplifiers. Therefore, we shall now take ro into account and derive an expression for the differential gain vo/vid of the active-loaded MOS differential pair. Unfortunately, because the circuit is not symmetrical a virtual ground will not develop at the common source terminal, contrary to the qualitative description presented above (where the ro’s were neglected). Thus we will not be able to use the differential half-circuit technique. Rather, we shall perform the derivation from first principles: We will represent the output of the circuit by the equivalent circuit shown in Fig. 8.33 and find the short-circuit transconductance Gm and the output resistance Ro. Then, the gain will be determined as GmRo.
Determining the Transconductance Gm Figure 8.34(a) shows the circuit3 prepared for determining Gm. Note that we have short-circuited the output to ground in order to find Gm as 3Note that rather than replacing each transistor with its small-signal model, we are, for simplicity, using the models implicitly. Thus we have “pulled ro out” of each transistor and shown it separately so that the drain current becomes gmvgs.
Ro Gm vid vo Figure 8.33 Output equivalent circuit of the amplifier in Fig. 8.32(a) for differential input signals.
8.5 The Differential Amplifier with Active Load 639 io/ vid. Although the original circuit is not symmetrical, when the output is shorted to ground, the circuit becomes almost symmetrical. This is because the voltage between the drain of Q1 and ground is very small. This in turn is due to the low resistance between that node and ground which is almost equal to 1/gm3. Thus, we can now invoke symmetry and assume that a virtual ground will appear at the source of Q1 and Q2 and in this way obtain the equivalent cir-cuit shown in Fig. 8.34(b). Here we have replaced the diode-connected transistor Q3 by its equivalent resistance The voltage vg3 that develops at the common-gate node of the mirror can be found by multiplying the drain current of Q1 (gm1vid/2), by the total resistance between the drain of Q1 and ground. (8.133) which for the usual case of ro1 and reduces to (8.134) This voltage controls the drain current of Q4 resulting in a current of gm4vg3. Note that the ground at the output node causes the currents in ro2 and ro4 to be zero. Thus the output current io will be (8.135) Substituting for vg3 from Eq. (8.134) gives Now, since gm3 = gm4 and gm1 = gm2 = gm, the current io becomes Figure 8.34 Determining the short-circuit transconductance of the active-loaded MOS dif-ferential pair.
(a) 1gm3 Q1 Q2 vid2 vid2 vg3 ro1 ro2 ro4 ro3 Q4 Q3 0 V io (b) Q1 Q2 vid2 vid2 vg3 ro1 ro2 ro4 io gm1vid2 gm4vg3 gm2vid2 0 0 1 gm3 ro3 Gm io vid ⁄ ≡ [(1 gm3 ⁄ )||ro3].
vg3 gm1 vid 2 -----⎝ ⎠ ⎛ ⎞ 1 gm3 -------- || ro3 || ro1 ⎝ ⎠ ⎛ ⎞ – = ro3 (1 gm3 ⁄ ) vg3 gm1 gm3 --------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ – io –gm4vg3 gm2 vid 2 -----⎝ ⎠ ⎛ ⎞ + = io gm1 gm4 gm3 --------⎝ ⎠ ⎛ ⎞vid 2 -----⎝ ⎠ ⎛ ⎞ gm2 vid 2 -----⎝ ⎠ ⎛ ⎞ + = io gmvid = 640 Chapter 8 Differential and Multistage Amplifiers from which Gm is found to be (8.136) Thus the short-circuit transconductance of the circuit is equal to gm of each of the two tran-sistors of the differential pair.4 Here we should note that in the absence of the current-mirror action, Gm would be equal to .
Determining the Output Resistance Ro Figure 8.35 shows the circuit for determining the output resistance . Observe that we have set to zero, resulting in the ground con-nections at the gates of and . We have applied a test voltage in order to determine Analysis of this circuit is considerably simplified by observing the current transmission around the circuit by simply following the circled numbers. The current i that enters must exist at its source. It then enters , exiting at the drain to feed the mirror.
Since for the diode-connected transistor is much smaller than most of the current i flows into the drain proper of The mirror responds by providing an equal cur-rent i in the drain of The relationship between i and can be determined by observing that at the output node where is the output resistance of Now, is a CG transistor and has in its source lead the input resistance of the CG transistor . Noting that the load resistance of 4Because the circuit of Fig. 8.34(a) is not perfectly symmetrical, the voltage at the common-source ter-minal will not be exactly zero. Nevertheless, it can be shown that the voltage will be very small and the transconductance Gm will indeed be very close to gm.
Gm gm = gm 2 ⁄ Ro vid Q1 Q2 vx Ro, Ro vx ix ----≡ 1gm3 1gm3 Q1 Q2 Ro ro1 ro2 Ro2 i ix i i vx ro4 ro3 Q4 Q3 Rin1 i i 1 3 4 5 2 Figure 8.35 Circuit for determining Ro. The circled numbers indicate the order of the analysis steps.
Q2 Q1 Q3 Q4 – Q3, 1 gm3 ⁄ ro3.
Q3.
Q4.
vx i vx Ro2 ⁄ = Ro2 Q2.
Q2 Rin1 Q1 Q1 8.5 The Differential Amplifier with Active Load 641 is , which is approximately we can obtain by using the expres-sion for the input resistance of a CG transistor (adapt Eq. 7.35 by replacing the subscript 2 by 1), We then use this value of to determine using the expression in Eq. (7.38) as follows: which, for and , yields (8.137) Returning to the output node, we write Substituting for from Eq. (8.137), we obtain Thus, (8.138) which is an intuitively appealing result.
Determining the Differential Gain Equations (8.136) and (8.138) can be combined to obtain the differential gain Ad as (8.139) For the case ro2 = ro4 = ro, (8.140) where A0 is the intrinsic gain of the MOS transistor.
8.5.4 Common-Mode Gain and CMRR Although its output is single-ended, the active-loaded MOS differential amplifier has a low common-mode gain and, correspondingly, a high CMRR. Figure 8.36(a) shows the circuit with vicm applied and with the power supplies eliminated except, of course, for the output resistance RSS of the bias-current source I. Although the circuit is not symmetrical and hence 1 gm3 ⁄ ( ) ro3 || [ ] 1 gm3 ⁄ , Rin1 Rin1 ro1 RL + gm1ro1 -------------------= 1 gm1 --------1 gm3 ⁄ gm1ro1 --------------- 1 gm1 --------+ = Rin1 Ro2 Ro2 Rin1 r + o2 gm2ro2Rin1 + = 1 gm1 --------ro2 + gm2 gm1 --------⎝ ⎠ ⎛ ⎞ro2 + = gm1 gm2 gm = = gm2ro2 1 Ro2 2ro2 ix i i vx ro4 ------+ + = 2i vx ro4 ------2 vx Ro2 --------vx ro4 ------+ = + = Ro2 ix 2 vx 2ro2 ----------vx ro4 ------+ = Ro vx ix ----ro2 ro4 || = ≡ Ad vo vid -----≡ GmRo gm ro2 ||ro4 ( ) = = Ad 1 2 ---gmro A0 2 -----= = 642 Chapter 8 Differential and Multistage Amplifiers we cannot use the common-mode half-circuit, we can split RSS equally between Q1 and Q2 as shown in Fig. 8.36b. It can now be seen that each of Q1 and Q2 is a CS transistor with a large source degeneration resistance 2RSS.
Each of and together with their degeneration resistances can be replaced by equiva-lent circuits composed of a controlled source and an output resistance Ro1,2, as shown in Fig. 8.36(c). To determine we short circuit the drain to ground, as shown in Fig. 8.36(d) for . Observe that and appear in parallel. Thus the voltage at the source terminal can be found from the voltage divider consisting of and as Figure 8.36 Analysis of the active-loaded MOS differential amplifier to determine its common-mode gain.
(a) vo Q1 Q2 vicm vicm RSS ro1 ro2 ro4 ro3 Q4 Q3 (b) vo Q1 Q2 vicm vicm 2RSS 2RSS ro1 ro2 ro4 ro3 Q4 Q3 vg3 (c) Q3 Q4 ro3 Ro1 Ro2 ro4 Gmcmvicm Gmcm vicm i4 vo d1 1/gm3 (d) Q1 2RSS ro1 vicm Ro1 io vs io gm1 1 Q1 Q2 Gmcmvicm Gmcm Q1 2RSS ro1 1 gm1 ⁄ 2RSS ro1 || ( ) 8.5 The Differential Amplifier with Active Load 643 The short-circuit drain current can be seen to be equal to the current through ; thus, which leads to (8.141) The output resistance can be determined using the expression for of a CS transistor with an emitter-degeneration resistance (Eq. 7.38) to obtain (8.142) Similar results can be obtained for namely, the same and an output resistance given by (8.143) Returning to the circuit in Fig. 8.36(c), the voltage can be obtained by multiplying by the total resistance between the node and ground, (8.144) This voltage in turn determines the current as Thus, (8.145) Finally, we can obtain the output voltage by writing for the output node, Substituting for from Eq. (8.145) and for from Eq. (8.141) yields Since and we can neglect both. Also, substituting we obtain the following expression for (8.146) This expression can be further simplified by noting that and with the result that (8.146′) vs vicm 2RSS ro1 || ( ) 2RSS ro1 || ( ) 1 gm1 ⁄ ( ) + -------------------------------------------------------= vicm io 2RSS io vicm 2RSS -----------= Gmcm io vicm ---------1 2RSS -----------= ≡ Ro1 Ro Ro1 2RSS ro1 gm1ro1 ( ) 2RSS ( ) + + = Q2, Gmcm Ro2 Ro2 2RSS ro2 gm2ro2 ( ) 2RSS ( ) + + = vg3 Gmcmvicm d1 vg3 Gmcmvicm Ro1 ro3 1 gm3 --------|| || ⎝ ⎠ ⎛ ⎞ – = i4 i4 gm4vgs3 gm4vg3 = = i4 gm4Gmcmvicm Ro1 ro3 1 gm3 --------|| || ⎝ ⎠ ⎛ ⎞ – = vo Gmcmvicm i4 vo Ro2 --------vo ro4 ------0 = + + + i4 Gmcm vo vicm ro4 Ro2 || 2RSS -------------------- 1 gm4 Ro1 ro3 1 gm3 --------|| || ⎝ ⎠ ⎛ ⎞ – – = Ro2 r o4 Ro1 r o3, gm4 gm3, = Acm, Acm vo vicm --------- ro4 2RSS -----------1 1 gm3ro3 + -------------------------– ≡ gm3ro3 1 ro3 ro4 = Acm 1 2gm3RSS --------------------– 644 Chapter 8 Differential and Multistage Amplifiers Since RSS is usually large, at least equal to ro, Acm will be small. The common-mode rejection ratio (CMRR) can now be obtained by utilizing Eqs. (8.139) and (8.146′), (8.147) which for ro2 = ro4 = ro and gm3 = gm simplifies to (8.148) We observe that to obtain a large CMRR, we select an implementation of the biasing current source I that features a high output resistance. Such circuits include the cascode current source and the Wilson current source studied in Section 7.5. 8.5.5 The Bipolar Differential Pair with Active Load The bipolar version of the active-loaded differential pair is shown in Fig. 8.37(a). The circuit structure and operation are very similar to those of its MOS counterpart except that here we have to contend with the effects of finite β and the resulting finite input resistance at the base, r π . For the time being, however, we shall ignore the effect of finite β on the dc bias of the four transistors and assume that in equilibrium all transistors are operating at a dc current of I/2.
Differential Gain To obtain an expression for the differential gain, we apply an input dif-ferential signal vid as shown in the equivalent circuit in Fig. 8.37(b). Note that the output is con-nected to ground in order to determine the overall short-circuit transconductance Also, as in the MOS case, we have assumed that the circuit is sufficiently balanced so that a virtual ground develops on the common emitter terminal. This assumption is predicated on the fact that the voltage signal at the collector of Q1 will be small as a result of the low resistance between that node and ground (approximately equal to re3). The voltage vb3 can be found from Of the four resistances in the parallel equivalent on the right-hand side, re3 is much smaller than the other three and thus dominates, with the result that (8.149) Since vb4 = vb3, the collector current of Q4 will be (8.150) CMRR Ad Acm -----------≡ gm ro2 ||ro4 ( ) [ ] 2gm3RSS [ ] = CMRR gmro ( ) = gmRSS ( ) 8.16 An active-loaded MOS differential amplifier of the type shown in Fig. 8.32(a) is specified as follows: (W/L)n = 100, (W/L)p = 200, μnCox = 2μpCox = 0.2 mA/V2, I = 0.8 mA, RSS = 25 kΩ.
Calculate Gm, Ro, Ad, and CMRR.
Ans. 4 mA/V; 25 kΩ; 100 V/V; 0.005 V/V; 20,000 or 86 dB V An = V Ap = 20 V, Acm , EXERCISE Gm io vid ⁄ .
≡ vb3 gm1 vid 2 -----⎝ ⎠ ⎛ ⎞re3 ||ro3||ro1||rπ4 ( ) – = vb3 gm1re3 vid 2 -----⎝ ⎠ ⎛ ⎞ – gm4vb4 gm4gm1re3 vid 2 -----⎝ ⎠ ⎛ ⎞ – = 8.5 The Differential Amplifier with Active Load 645 The output current io can be found from a node equation at the output as (8.151) Using Eq. (8.150), we obtain (8.152) Since all devices are operating at the same bias current, gm1 = gm2 = gm4 = gm, where Figure 8.37 (a) Active-loaded bipolar differential pair. (b) Small-signal equivalent circuit for determining the transconductance (c) Equivalent circuit for determining the output resistance (a) VEE vB2 vB1 Q1 Q2 Q4 Q3 vO VCC I ro1 rp4 rp1 rp2 vb4 vb3 gm4vb4 ro2 0 0 ro4 io gm2 vid 2 gm1 vid 2 (re3 ro3) vid2 vid2 (b) (c) Q2 Q4 (re3 ro3) ro4 Q1 Ro ire3 ire3re4 i ro2 ro1 Ro2 2ro2 re1 i i vx i ix Gm io vid ⁄ .
≡ Ro vx ix ⁄ .
≡ io gm2 vid 2 -----⎝ ⎠ ⎛ ⎞ gm4vb4 – = io gm2 vid 2 -----⎝ ⎠ ⎛ ⎞ gm4gm1re3 vid 2 -----⎝ ⎠ ⎛ ⎞ + = 646 Chapter 8 Differential and Multistage Amplifiers (8.153) and Thus, for Gm, Eq. (8.152) yields (8.154) which is identical to the result found for the MOS circuit.
Next we determine the output resistance of the amplifier utilizing the equivalent circuit shown in Fig. 8.37(c). We urge the reader to carefully examine this circuit and to note that the analysis is very similar to that for the MOS pair. Note specifically that the total resistance between the collector of Q1 and ground is approximately re3. Now, since this is a relatively low resistance, the input resistance of the CB transistor Q1 will be approximately equal to its re, that is, re1. Then, the output resistance Ro2 of transistor Q2 can be found using Eq. (7.50) by noting that the resistance Re in the emitter of Q2 is approximately equal to re1; thus, (8.155) where we made use of the fact that corresponding parameters of all four transistors are equal.
The current i can now be found as (8.156) and the current ix can be obtained from a node equation at the output as Thus, (8.157) This expression simply says that the output resistance of the amplifier is equal to the parallel equivalent of the output resistance of the differential pair and the output resistance of the current mirror; a result identical to that obtained for the MOS pair.
Equations (8.154) and (8.157) can now be combined to obtain the differential gain, (8.158) and since ro2 = ro4 = ro, we can simplify Eq. (8.158) to (8.159) Although this expression is identical to that found for the MOS circuit, the gain here is much larger because gmro for the BJT is more than an order of magnitude greater than gmro of a MOSFET. The downside, however, lies in the low input resistance of BJT amplifiers.
Indeed, the equivalent circuit of Fig. 8.37(b) indicates that, as expected, the differential input resistance of the differential amplifier is equal to 2r π, (8.160) in sharp contrast to the infinite input resistance of the MOS amplifier. Thus, while the voltage gain realized in an active-loaded BJT amplifier stage is large, when a subsequent BJT stage is gm I 2 ⁄ VT ---------re3 α3 gm3 ⁄ α gm ⁄ 1 gm.
⁄ = = Gm gm = Ro2 ro2 1 gm2 re1 || rπ2 ( ) + [ ] ro2 1 gm2re1 + ( ) 2ro2 i vx Ro2 -------vx 2ro2 ---------= = ix 2i vx ro4 ------+ vx ro2 ------vx ro4 ------+ = = Ro vx ix ----≡ ro2 || ro4 = Ad vo vid -----≡ GmRo gm ro2 || ro4 ( ) = = Ad 1 2 ---gmro = Rid 2rπ = 8.5 The Differential Amplifier with Active Load 647 connected to the output, its inevitably low input resistance will drastically reduce the overall voltage gain.
Common-Mode Gain and CMRR The common-mode gain Acm and the common-mode rejection ratio (CMRR) can be found following a procedure identical to that utilized in the MOS case. Figure 8.38 shows the circuit prepared for common-mode signal analysis. As we have done in the MOS case, we will represent each of Q1 and Q2 together with their emitter resistances by a short-circuit output current i1,2 and an output resistance Ro1,2. The short-circuit output currents of Q1 and Q2 are given by (8.161) It can be shown that the output resistances of Q1 and Q2, Ro1 and Ro2, are very large compared with the other resistances between the collector nodes of Q1 and Q2 ground, and hence can be neglected. Then, the voltage vb3 at the common base connection of Q3 and Q4 can be found by multiplying i1 by the total resistance between the common base node and ground as (8.162) In response to vb3 transistor Q4 provides a collector current gm4vb3. At the output node we can write the equation (8.163) Substituting for vb3 from Eq. (8.162) and for i1 and i2 from Eq. (8.161) gives (8.164) i1 i2 vicm 2REE ------------2REE Q1 ro1 vicm vb3 Ro1 Ro2 rp4 2REE Q2 Q4 ro2 ro4 vicm vo i1 i2 gm4vb3 1 gm3 rp3 ro3 Figure 8.38 Analysis of the bipolar active-loaded differential amplifier to determine the common-mode gain.
vb3 i1 1 gm3 --------||rπ3 ||ro3 ||rπ4 ⎝ ⎠ ⎛ ⎞ – = vo ro4 ------gm4vb3 i2 + + = 0 Acm vo vicm -------≡ ro4 2REE ------------ gm4 1 gm3 --------||rπ3 ||ro3 ||rπ4 ⎝ ⎠ ⎛ ⎞ 1 – = ro4 2REE ------------1 rπ3 ------1 rπ4 ------1 ro3 ------+ + gm3 1 rπ3 ------1 rπ4 ------1 ro3 ------+ + + -----------------------------------------------– = 648 Chapter 8 Differential and Multistage Amplifiers where we have assumed gm3 = gm4. Now, for rπ4 = rπ3 and rπ4, Eq. (8.164) gives (8.165) Using Ad from Eq. (8.158) enables us to obtain the CMRR as (8.166) For ro2 = ro4 = ro, (8.167) from which we observe that to obtain a large CMRR, the circuit implementing the bias current source should have a large output resistance REE. This is possible with, say, a Wilson current mirror (Section 7.5.3). Before leaving the subject of the CM gain of the active-loaded differential amplifier, it is useful to reflect on the origin of its finite common-mode gain: It is simply due to the current transmission error introduced by the current-mirror load. In the case of the MOS circuit, this error is due to the finite ro3; in the case of the bipolar mirror, the error is due to the finite β [Problem 8.98].
Systematic Input Offset Voltage In addition to the random offset voltages that result from the mismatches inevitably present in the differential amplifier, the active-loaded bipolar differential pair suffers from a systematic offset voltage. This is due to the error in the current transfer ratio of the current-mirror load caused by the finite β of the pnp transistors that make up the mirror. To see how this comes about, refer to Fig. 8.39. Here the inputs are grounded and the transistors are assumed to be perfectly matched. Thus, the bias current I will divide equally between Q1 and Q2 with the result that their two collectors conduct equal currents of The collector current of Q1 is fed to the input of the current mirror. From Section 7.4 we know that the current-transfer ratio of the mirror is (8.168) ro3 rπ3, Acm ro4 2REE -----------– 2 rπ3 ------gm3 2 rπ3 ------+ --------------------- ro4 2REE -----------– 2 β3 -----ro4 β3REE --------------– = CMRR Ad Acm -----------≡ gm ro2 || ro4 ( ) β3REE ro4 --------------⎝ ⎠ ⎛ ⎞ = CMRR 1 2 ---β3gmREE = 8.17 For the active-loaded BJT differential amplifier let I = 0.8 mA, VA = 100 V, and β = 160. Find Gm, Ro, Ad, and Rid. If the bias current source is implemented with a simple npn current mirror, find REE, Acm, and CMRR.
Ans. 16 mA/V; 125 kΩ; 2000 V/V; 20 kΩ; 125 kΩ; −0.0125 V/V; 160,000 or 104 dB EXERCISE αI 2.
⁄ I4 I3 ----1 1 2 βP -----+ ---------------= 8.5 The Differential Amplifier with Active Load 649 where βP is the value of β of the pnp transistors Q3 and Q4. Thus the collector current of Q4 will be (8.169) which does not exactly balance the collector current of Q2. It follows that the current differ-ence Δi will flow into the output terminal of the amplifier with (8.170) To reduce this output current to zero, an input voltage VOS has to be applied with a value of Substituting for Δi from Eq. (8.170) and for we obtain for the input offset voltage the expression (8.171) Q1 Q2 Q4 Q3 VCC I i aI2 aI2 aI2 I2 I2 1 2 bP Figure 8.39 The active-loaded BJT differential pair suffers from a systematic input offset voltage resulting from the error in the current-transfer ratio of the current mirror.
I4 αI 2 ⁄ 1 2 βP -----+ ---------------= Δi αI 2 ------αI 2 ⁄ 1 2 βP -----+ ---------------– = αI 2 ------ 2 βP ⁄ 1 2 βP -----+ ---------------= αI βP ------V OS Δi Gm -------– = Gm gm αI 2 ⁄ ( ) VT ⁄ , = = V OS αI βP ⁄ αI 2VT ⁄ -------------------– 2VT βP ---------– = = 650 Chapter 8 Differential and Multistage Amplifiers As an example, for βP = 50, VOS = −1 mV. To reduce VOS, an improved current mirror such as the Wilson circuit studied in Section 7.5.3 should be used. Such a circuit pro-vides the added advantage of increased output resistance and hence voltage gain. How-ever, to realize the full advantage of the higher output resistance of the active load, the output resistance of the differential pair should be raised by utilizing a cascode stage. Figure 8.40 shows such an arrangement: A folded cascode stage formed by pnp transistors Q3 and Q4 is utilized to raise the output resistance looking into the collector of Q4 to β4ro4. A Wilson mirror formed by transistors Q5, Q6, and Q7 is used to implement the active load. From Section 7.5.3 we know that the output resistance of the Wilson mirror (i.e., looking into the collector of Q5) is Thus the output resistance of the amplifier is given by (8.172) The transconductance Gm remains equal to gm of Q1 and Q2. Thus the differential voltage gain becomes (8.173) which can be very large. Further examples of improved-performance differential amplifiers will be studied in Chapter 12.
Figure 8.40 An active-loaded bipolar differential amplifier employing a folded cascode stage (Q3 and Q4) and a Wilson current-mirror load (Q5, Q6, and Q7).
I I I Q1 Q2 Q6 vid VEE VCC VBIAS Q3 Q4 Q5 Q7 vo β5 ro5 2 ⁄ ( ).
Ro β4ro4 || β5 ro5 2 ------= Ad gm β4ro4 || β5 ro5 2 ------= 8.6 Multistage Amplifiers 651 8.6 Multistage Amplifiers Practical transistor amplifiers usually consist of a number of stages connected in cas-cade. In addition to providing gain, the first (or input) stage is usually required to pro-vide a high input resistance in order to avoid loss of signal level when the amplifier is fed from a high-resistance source. In a differential amplifier the input stage must also provide large common-mode rejection. The function of the middle stages of an amplifier cascade is to provide the bulk of the voltage gain. In addition, the middle stages provide such other functions as the conversion of the signal from differential mode to single-ended mode (unless, of course, the amplifier output also is differential) and the shifting of the dc level of the signal in order to allow the output signal to swing both positive and negative. These two functions and others will be illustrated later in this section and in greater detail in Chapter 12.
Finally, the main function of the last (or output) stage of an amplifier is to provide a low output resistance in order to avoid loss of gain when a low-valued load resistance is con-nected to the amplifier. Also, the output stage should be able to supply the current required by the load in an efficient manner—that is, without dissipating an unduly large amount of power in the output transistors. We have already studied one type of amplifier configuration suitable for implementing output stages, namely, the source follower and the emitter fol-lower. It will be shown in Chapter 11 that the source and emitter followers are not optimum from the point of view of power efficiency and that other, more appropriate circuit configu-rations exist for output stages that are required to supply large amounts of output power. In fact, we will encounter some such output stages in the op-amp circuit examples studied in Chapter 12.
To illustrate the circuit structure and the method of analysis of multistage amplifiers, we will present two examples: a two-stage CMOS op amp and a four-stage bipolar op amp.
8.6.1 A Two-Stage CMOS Op Amp Figure 8.41 shows a popular structure for CMOS op amps known as the two-stage configu-ration. The circuit utilizes two power supplies, which can range from ±2.5 V for the 0.5-μm technology down to ±0.9 V for the 0.18-μm technology. A reference bias current IREF is gen-erated either externally or using on-chip circuits. One such circuit will be discussed shortly.
The current mirror formed by Q8 and Q5 supplies the differential pair Q1 − Q2 with bias cur-rent. The W/L ratio of Q5 is selected to yield the desired value for the input-stage bias current I (or I/2 for each of Q1 and Q2). The input differential pair is actively loaded with the current mirror formed by Q3 and Q4. Thus the input stage is identical to that studied in Section 8.5 8.18 Find Gm and Ro4, Ro5, Ro, and Ad for the differential amplifier in Fig. 8.40 under the following con-ditions: I = 1 mA, βP = 50, βN = 100, and VA = 100 V.
Ans. 20 mA/V; 10 MΩ; 10 MΩ; 5 MΩ; 105 V/V or 100 dB EXERCISE 652 Chapter 8 Differential and Multistage Amplifiers (except that here the differential pair is implemented with PMOS transistors and the current mirror with NMOS).
The second stage consists of Q6, which is a common-source amplifier loaded with the cur-rent-source transistor Q7. A capacitor CC is included in the negative-feedback path of the second stage. Its function will be explained in Chapter 9, when we study the frequency response of amplifiers.
A striking feature of the circuit in Fig. 8.41 is that it does not have a low-output-resistance stage. In fact, the output resistance of the circuit is equal to (ro6 || ro7) and is thus rather high. This circuit, therefore, is not suitable for driving low-impedance loads. Never-theless, the circuit is very popular and is used frequently for implementing op amps in VLSI circuits, where the op amp needs to drive only a small capacitive load, for example, in switched-capacitor circuits (Chapter 17). The simplicity of the circuit results in an op amp of reasonably good quality realized in a very small chip area.
Voltage Gain The voltage gain of the first stage was found in Section 8.5 to be given by (8.174) where gm1 is the transconductance of each of the transistors of the first stage, that is, Q1 and Q2.
The second stage is current-source-loaded, common-source amplifier whose voltage gain is given by (8.175) The dc open-loop gain of the op amp is the product of A1 and A2.
CC D6 D2 I Figure 8.41 Two-stage CMOS op-amp configuration.
A1 gm1 ro2 ro4 || ( ) – = A2 gm6 ro6 ro7 || ( ) – = 8.6 Multistage Amplifiers 653 Consider the circuit in Fig. 8.41 with the following device geometries (in μm).
Let IREF = 90 μA, Vtn = 0.7 V, Vtp = –0.8 V, μnCox = 160 μA/V2, μpCox = 40 μA/V2, (for all devices) = 10 V, VDD = VSS = 2.5 V. For all devices, evaluate ID, , , gm, and ro. Also find A1, A2, the dc open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of on bias current.
Solution Refer to Fig. 8.41. Since Q8 and Q5 are matched, I = IREF. Thus Q1, Q2, Q3, and Q4 each conducts a current equal to I/2 = 45 μA. Since Q7 is matched to Q5 and Q8, the current in Q7 is equal to IREF = 90 μA. Finally, Q6 conducts an equal current of 90 μA.
With ID of each device known, we use to determine for each transistor. Then we find from = + . The results are given in Table 8.1.
The transconductance of each device is determined from The value of ro is determined from The resulting values of gm and ro are given in Table 8.1.
The voltage gain of the first stage is determined from The voltage gain of the second stage is determined from Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/L 20/0.8 20/0.8 5/0.8 5/0.8 40/0.8 10/0.8 40/0.8 40/0.8 Table 8.1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 ID (μA) 45 45 45 45 90 90 90 90 (V) 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 (V) 1.1 1.1 1 1 1.1 1 1.1 1.1 gm (mA/V) 0.3 0.3 0.3 0.3 0.6 0.6 0.6 0.6 ro (kΩ) 222 222 222 222 111 111 111 111 VA V OV V GS V A ID 1 2 --- (μCox)(W/L)V2 OV = V OV V GS V GS Vt V OV gm 2ID V OV ⁄ = ro VA ID ⁄ = A1 gm1 ro2 ro4 || ( ) – = 0.3 222 222 || ( ) – = 33.3 V/V – = A2 gm6 ro6 ro7 || ( ) – = 0.6 111 111 || ( ) – = 33.3 V/V – = V OV V GS Example 8.5 654 Chapter 8 Differential and Multistage Amplifiers Input Offset Voltage The device mismatches inevitably present in the input stage give rise to an input offset voltage. The components of this input offset voltage can be calcu-lated using the methods developed in Section 8.4.1. Because device mismatches are random, the resulting offset voltage is referred to as random offset. This is to distinguish it from another type of input offset voltage that can be present even if all appropriate devices are perfectly matched. This predictable or systematic offset can be minimized by careful design. Although it occurs also in BJT op amps, and we have encountered it in Section 8.5.5, it is usually much more pronounced in CMOS op amps because their gain-per-stage is rather low.
To see how systematic offset can occur in the circuit of Fig. 8.41, let the two input termi-nals be grounded. If the input stage is perfectly balanced, then the voltage appearing at the drain of Q4 will be equal to that at the drain of Q3, which is (–VSS + VGS4). Now this is also the voltage that is fed to the gate of Q6. In other words, a voltage equal to VGS4 appears between gate and source of Q6. Thus the drain current of Q6, I6, will be related to the drain current of Q4, which is equal to I/2, by the relationship (8.176) In order for no offset voltage to appear at the output, this current must be exactly equal to the current supplied by Q7. The latter current is related to the current I of the parallel transistor Q5 by (8.177) Now, the condition for making I6 = I7 can be found from Eqs. (8.176) and (8.177) as (8.178) Example 8.5 continued Thus the overall dc open-loop gain is or 20 log1109 = 61 dB The lower limit of the input common-mode range is the value of input voltage at which Q1 and Q2 leave the saturation region. This occurs when the input voltage falls below the voltage at the drain of Q1 by volts. Since the drain of Q1 is at −2.5 + 1 = −1.5 V, then the lower limit of the input common-mode range is −2.3 V. The upper limit of the input common-mode range is the value of input voltage at which Q5 leaves the sat-uration region. Since for Q5 to operate in saturation the voltage across it (i.e., VSD5) should at least be equal to the overdrive voltage at which it is operating (i.e., 0.3 V), the highest voltage permitted at the drain of Q5 should be +2.2 V. It follows that the highest value of vICM should be The highest allowable output voltage is the value at which Q7 leaves the saturation region, which is VDD − = 2.5 − 0.3 = 2.2 V. The lowest allowable output voltage is the value at which Q6 leaves saturation, which is −VSS + VOV6 = −2.5 + 0.3 = −2.2 V. Thus, the output voltage range is −2.2 V to +2.2 V.
A0 A1A2 33.3 – ( ) 33.3 – ( ) 1109 V/V = × = = V tp vICMmax 2.2 1.1 – 1.1 V = = V OV7 I6 (W/L)6 (W/L)4 -----------------(I/ 2) = I7 (W/L)7 (W/L)5 -----------------I = (W/L)6 (W/L)4 -----------------2(W/L)7 (W/L)5 -----------------= 8.6 Multistage Amplifiers 655 If this condition is not met, a systematic offset will result. From the specification of the device geometries in Example 8.5, we can verify that condition (8.178) is satisfied, and, therefore, the op amp analyzed in that example should not exhibit a systematic input offset voltage.
A Bias Circuit That Stabilizes gm We conclude this section by presenting a bias circuit for the two-stage CMOS op amp. The circuit presented has the interesting and useful property of providing a bias current whose value is independent of both the supply voltage and the MOSFET threshold voltage. Furthermore, the transconductances of the transistors biased by this circuit have values that are determined only by a single resistor and the device dimensions.
The bias circuit is shown in Fig. 8.42. It consists of two deliberately mismatched transis-tors, Q12 and Q13, with Q12 usually about four times wider than Q13. A resistor RB is connected in series with the source of Q12. Since, as will be shown, RB determines both the bias current IB and the transconductance gm12, its value should be accurate and stable; in most applica-tions, RB would be an off-chip resistor. In order to minimize the channel-length modulation effect on Q12, we include a cascode transistor Q10 and a matched diode-connected transistor Q11 to provide a bias voltage for Q10. Finally, a p-channel current mirror formed by a pair of matched devices, Q8 and Q9, both replicates the current IB back to Q11 and Q13, and provides a bias line for Q5 and Q7 of the CMOS op-amp circuit of Fig. 8.41.5 The circuit operates as follows: The current mirror (Q8, Q9) causes Q13 to conduct a cur-rent equal to that in Q12, that is, IB. Thus, (8.179) and, (8.180) From the circuit, we see that the gate-source voltages of Q12 and Q13 are related by 5We denote the bias current of this circuit by IB. If this circuit is utilized to bias the CMOS op amp of Fig. 8.41, then IB becomes the reference current IREF.
8.19 Consider the CMOS op amp of Fig. 8.41 when fabricated in a 0.8-μm CMOS technology for which μnCox = 3μpCox = 90 μA/V2, |Vt| = 0.8 V, and VDD = VSS = 2.5 V. For a particular design, I = 100 μA, (W/L)1 = (W/L)2 = (W/L)5 = 200, and (W/L)3 = (W/L)4 = 100.
(a) Find the (W/L) ratios of Q6 and Q7 so that I6 = 100 μA.
(b) Find the overdrive voltage, |VOV|, at which each of Q1, Q2, and Q6 is operating.
(c) Find gm for Q1, Q2, and Q6.
(d) If |VA| = 10 V, find ro2, ro4, ro6, and ro7.
(e) Find the voltage gains A1 and A2, and the overall gain A.
Ans. (a) (W/L)6 = (W/L)7 = 200; (b) 0.129 V, 0.129 V, 0.105 V; (c) 0.775 mA/V, 0.775 mA/V, 1.90 mA/V; (d) 200 kΩ, 200 kΩ, 100 kΩ, 100 kΩ; (e) –77.5 V/V, –95 V/V, 7363 V/V EXERCISE IB 1 2 ---μnCox W L -----⎝ ⎠ ⎛ ⎞ 12 V GS12 V t – ( ) 2 = IB 1 2 ---μnCox W L -----⎝ ⎠ ⎛ ⎞ 13 V GS13 V t – ( ) 2 = V GS13 V GS12 IB RB + = 656 Chapter 8 Differential and Multistage Amplifiers Subtracting Vt from both sides of this equation and using Eqs. (8.179) and (8.180) to replace (VGS12 – Vt) and (VGS13 – Vt) results in (8.181) This equation can be rearranged to yield (8.182) from which we observe that IB is determined by the dimensions of Q12 and the value of RB and by the ratio of the dimensions of Q12 and Q13. Furthermore, Eq. (8.182) can be rearranged to the form in which we recognize the factor as gm12; thus, (8.183) This is a very interesting result: gm12 is determined solely by the value of RB and the ratio of the dimensions of Q12 and Q13. Furthermore, since gm of a MOSFET is proportional to each transistor biased by the circuit of Fig. 8.42; that is, each transistor whose bias current is derived from IB will have a gm value that is a multiple of gm12. Specifically, the ith n-channel MOSFET will have IB IB Q8 VDD Q9 VSS Q10 Q11 Q12 Q13 RB Figure 8.42 Bias circuit for the CMOS op amp.
2IB μnCox(W/L)13 ---------------------------------2IB μnCox(W/L)12 ---------------------------------= IB RB + IB 2 μnCox(W/L)12RB 2 ----------------------------------------(W/L)12 (W/L)13 -------------------1 – ⎝ ⎠ ⎛ ⎞ 2 = RB 2 2μnCox(W/L)12IB ----------------------------------------------(W/L)12 (W/L)13 -------------------1 – ⎝ ⎠ ⎛ ⎞ = 2μnCox(W/L)12IB gm12 2 RB ------(W/L)12 (W/L)13 -------------------1 – ⎝ ⎠ ⎛ ⎞ = I D(W/L), gmi gm12 IDi (W/L)i IB(W/L)12 ------------------------= 8.6 Multistage Amplifiers 657 and the ith p-channel device will have Finally, it should be noted that the bias circuit of Fig. 8.42 employs positive feedback, and thus care should be exercised in its design to avoid unstable performance. Instability is avoided by making Q12 wider than Q13, as has already been pointed out. Nevertheless, some form of instability may still occur; in fact, the circuit can operate in a stable state in which all currents are zero. To get it out of this state, current needs to be injected into one of its nodes, to “kick start” its operation. Feedback and stability will be studied in Chapter 10. 8.6.2 A Bipolar Op Amp Our second example of multistage amplifiers is the four-stage bipolar op amp shown in Fig. 8.43. The circuit consists of four stages. The differential-in, differential-out input stage consists of transistors Q1 and Q2, which are biased by current source Q3. The second stage is also a differential-input amplifier, but its output is taken single-endedly at the col-lector of Q5. This stage is formed by Q4 and Q5, which are biased by the current source Q6.
Note that the conversion from differential to single-ended as performed by the second stage results in a loss of gain by a factor of 2. In the more elaborate method for accom-plishing this conversion studied in Section 8.5, a current mirror was used as an active load.
In addition to providing some voltage gain, the third stage, consisting of the pnp transis-tor Q7, provides the essential function of shifting the dc level of the signal. Thus, while the signal at the collector of Q5 is not allowed to swing below the voltage at the base of Q5 (+10 V), the signal at the collector of Q7 can swing negatively (and positively, of course). From our study of op amps in Chapter 2, we know that the output terminal of the op amp should be capable of both positive and negative voltage swings. Therefore every op-amp circuit in-cludes a level-shifting arrangement. Although the use of the complementary pnp transistor provides a simple solution to the level-shifting problem, other forms of level shifter exist, one of which will be discussed in Chapter 12. Furthermore, note that level shifting is gmi gm12 μpIDi (W/L)i μnIB(W/L)12 ------------------------------= 8.20 Consider the bias circuit of Fig. 8.42 for the case of (W/L)8 = (W/L)9 = (W/L)10 = (W/L)11 = (W/L)13 = 20 and (W/L)12 = 80. The circuit is fabricated in a process technology for which μnCox = 90 μA/V2.
Find the value of RB that results in a bias current IB = 10 μA. Also, find the transconductance gm12.
Ans. 5.27 kΩ; 0.379 mA/V D8.21 Design the bias circuit of Fig. 8.42 to operate with the CMOS op amp of Example 8.5. Use Q8 and Q9 as identical devices with Q8 having the dimensions given in Example 8.5. Transistors Q10, Q11, and Q13 are to be identical, with the same gm as Q8 and Q9. Transistor Q12 is to be four times as wide as Q13. Find the required value of RB. What is the voltage drop across RB? Also give the val-ues of the dc voltages at the gates of Q12, Q10, and Q8.
Ans. 1.67 kΩ; 150 mV; −1.5 V; −0.5 V; +1.4 V EXERCISES 658 Chapter 8 Differential and Multistage Amplifiers accomplished in the CMOS op amp we have been studying by using complementary devices for the two stages: that is, p-channel for the first stage and n-channel for the second stage.
The output stage of the op amp consists of emitter follower Q8. As we know from our study of op amps in Chapter 2, ideally the output operates around zero volts. This and other features of the BJT op amp will be illustrated in Example 8.6.
Figure 8.43 A four-stage bipolar op amp.
In this example, we analyze the dc bias of the bipolar op-amp circuit of Fig. 8.43. Toward that end, Fig.
8.44 shows the circuit with the two input terminals connected to ground.
(a) Perform an approximate dc analysis (assuming β 1, 0.7 V, and neglecting the Early effect) to calculate the dc currents and voltages everywhere in the circuit. Note that Q6 has four times the area of each of Q9 and Q3.
(b) Calculate the quiescent power dissipation in this circuit. V BE Example 8.6 8.6 Multistage Amplifiers 659 (c) If transistors Q1 and Q2 have β = 100, calculate the input bias current of the op amp.
(d) What is the input common-mode range of this op amp?
Solution (a) The values of all dc currents and voltages are indicated on the circuit diagram. These values were calcu-lated by ignoring the base current of every transistor—that is, by assuming β to be very high. The analysis starts by determining the current through the diode-connected transistor Q9 to be 0.5 mA. Then we see that transistor Q3 conducts 0.5 mA and transistor Q6 conducts 2 mA. The current-source transistor Q3 feeds the differential pair (Q1, Q2) with 0.5 mA. Thus each of Q1 and Q2 will be biased at 0.25 mA. The collectors of Q1 and Q2 will be at [+15 – 0.25 × 20] = +10 V.
Proceeding to the second differential stage formed by Q4 and Q5, we find the voltage at their emitters to be [+10 – 0.7] = 9.3 V. This differential pair is biased by the current-source transistor Q6, which sup-plies a current of 2 mA; thus Q4 and Q5 will each be biased at 1 mA. We can now calculate the voltage at the collector of Q5 as [+15 – 1 × 3] = +12 V. This will cause the voltage at the emitter of the pnp transis-tor Q7 to be +12.7 V, and the emitter current of Q7 will be (+15 – 12.7)/2.3 = 1 mA.
The collector current of Q7, 1 mA, causes the voltage at the collector to be [–15 + 1 × 15.7] = +0.7 V.
The emitter of Q8 will be 0.7 V below the base; thus output terminal 3 will be at 0 V. Finally, the emitter current of Q8 can be calculated to be [0 – (–15)]/3 = 5 mA.
Figure 8.44 Circuit for Example 8.6.
660 Chapter 8 Differential and Multistage Amplifiers Example 8.6 continued (b) To calculate the power dissipated in the circuit in the quiescent state (i.e., with zero input signal) we simply evaluate the dc current that the circuit draws from each of the two power supplies. From the +15 V supply the dc current is I+ = 0.25 + 0.25 + 1 + 1 + 1 + 5 = 8.5 mA. Thus the power supplied by the positive power supply is P+ = 15 × 8.5 = 127.5 mW. The –15-V supply provides a current I – given by I – = 0.5 + 0.5 + 2 + 1 + 5 = 9 mA. Thus the power provided by the negative supply is P– = 15 × 9 = 135 mW. Adding P+ and P– provides the total power dissipated in the circuit PD: PD = P+ + P– = 262.5 mW.
(c) The input bias current of the op amp is the average of the dc currents that flow in the two input ter-minals (i.e., in the bases of Q1 and Q2). These two currents are equal (because we have assumed matched devices); thus the bias current is given by (d) The upper limit on the input common-mode voltage is determined by the voltage at which Q1 and Q2 leave the active mode and enter saturation. This will happen if the input voltage exceeds the collector volt-age, which is +10 V, by about 0.4 V. Thus the upper limit of the common-mode range is +10.4 V.
The lower limit of the input common-mode range is determined by the voltage at which Q3 leaves the active mode and thus ceases to act as a constant-current source. This will happen if the collector volt-age of Q3 goes below the voltage at its base, which is –14.3 V, by more than 0.4 V. It follows that the input common-mode voltage should not go lower than –14.7 + 0.7 = –14 V. Thus the common-mode range is –14 V to +10.4 V.
IB IE1 β 1 + ------------ = 2.5 μA Use the dc bias quantities evaluated in Example 8.6 to analyze the circuit in Fig. 8.43, to determine the input resistance, the voltage gain, and the output resistance.
Solution The input differential resistance Rid is given by Since Q1 and Q2 are each operating at an emitter current of 0.25 mA, it follows that Assume β = 100; then Thus, Rid = 20.2 kΩ To evaluate the gain of the first stage, we first find the input resistance of the second stage, Ri2, Q4 and Q5 are each operating at an emitter current of 1 mA; thus Rid rπ1 rπ2 + = re1 re2 25 0.25 ----------100 Ω = = = rπ1 rπ2 101 100 × 10.1 kΩ = = = Ri2 rπ4 rπ5 + = re4 re5 25 Ω = = Example 8.7 8.6 Multistage Amplifiers 661 Thus Ri2 = 5.05 kΩ. This resistance appears between the collectors of Q1 and Q2, as shown in Fig. 8.45.
Thus the gain of the first stage will be Figure 8.46 shows an equivalent circuit for calculating the gain of the second stage. As indicated, the input voltage to the second stage is the output voltage of the first stage, vo1. Also shown is the resis-tance Ri3, which is the input resistance of the third stage formed by Q7. The value of Ri3 can be found by Figure 8.46 Equivalent circuit for calculating the gain of the second stage of the amplifier in Fig. 8.43.
Figure 8.45 Equivalent circuit for calculating the gain of the input stage of the amplifier in Fig. 8.43.
rπ4 rπ5 101 25 × 2.525 = kΩ = = A1 vo1 vid -------≡ Total resistance in collector circuit Total resistance in emitter circuit -----------------------------------------------------------------------------------Ri2 R1 R2 + ( ) || re1 re2 + -----------------------------------= 5.05 kΩ 40 kΩ || 200 Ω -----------------------------------------= 22.4 V/V = Ri3 vo1 vo2 R3 Q4 Q5 662 Chapter 8 Differential and Multistage Amplifiers Example 8.7 continued multiplying the total resistance in the emitter of Q7 by (β + 1): Since Q7 is operating at an emitter current of 1 mA, We can now find the gain A2 of the second stage as the ratio of the total resistance in the collector circuit to the total resistance in the emitter circuit: To obtain the gain of the third stage we refer to the equivalent circuit shown in Fig. 8.47, where Ri4 is the input resistance of the output stage formed by Q8. Using the resistance-reflection rule, we calculate the value of Ri4 as where Ri3 β 1 + ( ) R4 re7 + ( ) = re7 25 1 ------25 Ω = = Ri3 101 2.325 234.8 kΩ = × = A2 vo2 vo1 ------- R3 Ri3 || re4 re5 + -------------------– ≡ 3 kΩ 234.8 kΩ || 50 Ω -----------------------------------------– = 59.2 V/V – = Ri4 β 1 + ( ) re8 R6 + ( ) = re8 25 5 ------5 Ω = = Ri4 101 5 3000 + ( ) 303.5 kΩ = = Figure 8.47 Equivalent circuit for evaluating the gain of the third stage in the amplifier circuit of Fig. 8.43.
8.6 Multistage Amplifiers 663 The gain of the third stage is given by Finally, to obtain the gain A4 of the output stage we refer to the equivalent circuit in Fig. 8.48 and write The overall voltage gain of the amplifier can then be obtained as follows: or 78.6 dB.
To obtain the output resistance Ro we “grab hold” of the output terminal in Fig. 8.43 and look back into the circuit. By inspection we find which gives Ro = 152 Ω Figure 8.48 Equivalent circuit of the output stage of the amplifier cir-cuit of Fig. 8.43.
A3 vo3 vo2 ------- R5 Ri4 || re7 R4 + -------------------– ≡ 15.7 kΩ 303.5 kΩ || 2.325 kΩ -------------------------------------------------– = 6.42 V/V – = A4 vo vo3 -------≡ R6 R6 re8 + -------------------= 3000 3000 5 + ---------------------= 0.998 1 = vo vid ------A1A2A3A4 8513 V/V = = Ro R6 || re8 R5 β 1 + ( ) ⁄ + [ ] = 664 Chapter 8 Differential and Multistage Amplifiers Analysis Using Current Gains There is an alternative method for the analysis of bipolar multistage amplifiers that can be somewhat easier to perform in some cases. The method makes use of current gains or more appropriately current-transmission factors. In effect, one traces the transmission of the signal current throughout the amplifier cascade, evaluating all the current transmission factors in turn. We shall illustrate the method by using it to analyze the amplifier circuit of the preceding example.
Figure 8.49 shows the amplifier circuit prepared for small-signal analysis. We have indi-cated on the circuit diagram the signal currents through all the circuit branches. Also indi-cated are the input resistances of all four stages of the amplifier. These should be evaluated before commencing the following analysis.
The purpose of the analysis is to determine the overall voltage gain (vo/vid). Toward that end, we express vo in terms of the signal current in the emitter of Q8, ie8, and vid in terms of the input signal current ii, as follows: Thus, the voltage gain can be expressed in terms of the current gain (ie8/ii) as 8.22 Use the results of Example 8.7 to calculate the overall voltage gain of the amplifier in Fig. 8.43 when it is connected to a source having a resistance of 10 kΩ and a load of 1 kΩ.
Ans. 4943 V/V EXERCISE vo R6ie8 = vid Ri1ii = vo vid -----R6 Ri1 -------ie8 ii -----= R1 R2 Q1 Q2 ii ii ic1 = ic2 ic2 ic5 ib4 ib5 Q5 Q4 vid Ri1 Ri2 ib5 R3 Ri3 ib7 Q7 R4 R6 R5 ic7 ib8 Q8 vo Ri4 ie8 Figure 8.49 The circuit of the multistage amplifier of Fig. 8.43 prepared for small-signal analysis. Indicated are the signal currents throughout the amplifier and the input resistances of the four stages.
8.6 Multistage Amplifiers 665 Next, we expand the current gain (ie8/ii) in terms of the signal currents throughout the circuit as follows: Each of the current-transmission factors on the right-hand side is either the current gain of a transistor or the ratio of a current divider. Thus, reference to Fig. 8.49 enables us to find these factors by inspection: These ratios can be easily evaluated and their values used to determine the voltage gain. With a little practice, it is possible to carry out such an analysis very quickly, forgoing explicitly labeling the signal currents on the circuit diagram. One simply “walks through” the circuit, from input to output, or vice versa, determining the current-transmission factors one at a time, in a chainlike fashion.
ie8 ii -----ie8 ib8 -----ib8 ic7 -----× ic7 ib7 -----× ib7 ic5 -----× ic5 ib5 -----× ib5 ic2 -----× ic2 ii -----× = ie8 ib8 -----β8 1 + = ib8 ic7 -----R5 R5 Ri4 + -------------------= ic7 ib7 -----β7 = ib7 ic5 -----R3 R3 Ri3 + -------------------= ic5 ib5 -----β5 = ib5 ic2 -----R1 R2 + ( ) R1 R2 + ( ) Ri2 + ------------------------------------= ic2 ii -----β2 = 8.23 Use the values of input resistance found in Example 8.7 to evaluate the seven current-transmission factors and hence the overall current gain and voltage gain.
Ans. The current-transmission factors in the order of their listing are 101, 0.0492, 100, 0.0126, 100, 0.8879, 100 A/A; the overall current gain is 55993 A/A; the voltage gain is 8256 V/V. This value differs slightly from that found in Example 8.7, because of the various approximations made in the example (e.g., ).
α1 EXERCISE 666 Chapter 8 Differential and Multistage Amplifiers Summary The differential-pair or differential-amplifier configuration is the most widely used building block in analog IC design.
The input stage of every op amp is a differential amplifier.
There are two reasons for preferring differential to sin-gle-ended amplifiers: Differential amplifiers are insensi-tive to interference, and they do not need bypass and coupling capacitors.
For a MOS (bipolar) pair biased by a current source I, each device operates at a drain (collector, assuming α = 1) current of and a corresponding overdrive voltage VOV (no analog in bipolar). Each device has ( for bipolar) and With the two input terminals connected to a suitable dc voltage V CM, the bias current I of a perfectly symmetri-cal differential pair divides equally between the two transistors of the pair, resulting in a zero voltage differ-ence between the two drains (collectors). To steer the current completely to one side of the pair, a difference input voltage vid of at least (4VT for bipolar) is needed.
Superimposing a differential input signal vid on the dc common-mode input voltage VCM such that and causes a virtual signal ground to appear on the common-source (common-emitter) connection. In response to vid, the current in Q1 increases by and the current in Q2 decreases by Thus, voltage signals of develop at the two drains (collectors, with RD replaced by RC). If the output voltage is taken single-endedly, that is, between one of the drains (collectors) and ground, a differential gain of is realized. When the output is taken differentially, that is, between the two drains (collectors), the differential gain realized is twice as large: The analysis of a differential amplifier to determine differential gain, differential input resistance, fre-quency response of differential gain, and so on is facilitated by employing the differential half-circuit, which is a common-source (common-emitter) transistor biased at An input common-mode signal vicm gives rise to drain (collector) voltage signals that are ideally equal and giv-en by for the bipolar pair], where RSS (REE) is the output resistance of the cur-rent source that supplies the bias current I. When the out-put is taken single-endedly, a common-mode gain of magnitude ( for the bipolar case) results. Taking the output differentially results, in the perfectly matched case, in zero Acm (infinite CMRR).
Mismatches between the two sides of the pair make Acm finite even when the output is taken differentially: A mismatch ΔRD causes a mismatch causes Corresponding expressions apply for the bi-polar pair.
While the input differential resistance Rid of the MOS pair is infinite, that for the bipolar pair is only 2rπ but can be increased to 2(β + 1)(re + Re) by including resis-tances Re in the two emitters. The latter action, howev-er, lowers Ad.
Mismatches between the two sides of a differential pair result in a differential dc output voltage VO even when the two input terminals are tied together and connected to a dc voltage V CM. This signifies the presence of an input offset voltage In a MOS pair there are three main sources for V OS: For the bipolar pair there are two main sources: A popular circuit in both MOS and bipolar analog ICs is the current-mirror-loaded differential pair. It realizes a high differential gain and a low common-mode gain, for the MOS circuit ( for the bipolar circuit), as well as per-forming the differential-to-single-ended conversion with no loss of gain.
The CMOS two-stage amplifier studied in Section 8.6.1 is intended for use as part of an IC system and thus is re-quired to drive only small capacitive loads. Therefore it does not have an output stage with a low output resistance.
A multistage amplifier typically consists of three or more stages: an input stage having a high input resistance, a reasonably high gain, and, if differential, a high CMRR; one or two intermediate stages that realize the bulk of the gain; and an output stage having a low output resistance.
In designing and analyzing a multistage amplifier, the loading effect of each stage on the one that precedes it, must be taken into account.
I 2 ⁄ gm I V OV ⁄ = αI 2VT, ⁄ ro V A I 2 ⁄ ( ) ⁄ .
= 2V OV vI1 VCM + = vid 2 ⁄ vI2 V CM vid 2 ⁄ – = gmvid 2 ⁄ gmvid 2 ⁄ .
gm RD ro || ( )vid 2 ⁄ ± 1 2 --- gm RD ro || ( ) gm RD ro || ( ).
I 2 ⁄ .
vicm RD 2RSS ⁄ ( ) [ vicm RC 2REE ⁄ ( ) – – Acm RD 2RSS ⁄ = RC 2REE ⁄ Acm RD 2RSS ⁄ ( ) RD Δ RD ⁄ ( ); = gm Δ Acm RD 2RSS ⁄ ( ) = gm Δ gm ⁄ ( ).
V OS V O Ad.
⁄ ≡ RD Δ V OS ⇒ V OV 2 ---------RD Δ RD ----------= (W/L) Δ V OS ⇒ V OV 2 ---------(W/L) Δ W/L -------------------= V Δ t V OS ⇒ ΔVt = R Δ C V OS ⇒ VT RC Δ RC ----------= IS Δ V OS ⇒ VT IS Δ IS -------= Ad gm Ro pair Ro mirror || ( ) = Acm 1 2 --- gm3RSS = ro4 β3REE ⁄ PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multisim sim-ulations for all the indicated problems can be found in the corresponding files on the CD. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption. difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 8.1: The MOS Differential Pair 8.1 For an NMOS differential pair with a common-mode voltage VCM applied, as shown in Fig. 8.2, let VDD = VSS = 1.0 V, = 0.4 mA/V2, (W/L)1,2 = 12.5, Vtn = 0.5 V, I = 0.2 mA, RD = 10 kΩ, and neglect channel-length modulation.
(a) Find VOV and VGS for each transistor.
(b) For VCM = 0, find VS, ID1, ID2, VD1, and VD2.
(c) Repeat (b) for VCM = +0.3 V.
(d) Repeat (b) for VCM = −0.1 V.
(e) What is the highest value of VCM for which Q1 and Q2 remain in saturation?
(f) If current source I requires a minimum voltage of 0.2 V to operate properly, what is the lowest value allowed for VS and hence for VCM?
8.2 For the PMOS differential amplifier shown in Fig.
P8.2 let Vtp = −0.8 V and = 4 mA/V2. Neglect channel-length modulation.
(a) For vG1 = vG2 = 0 V, find VOV and VGS for each of Q1 and Q2. Also find VS, VD1, and VD2.
(b) If the current source requires a minimum voltage of 0.5 V, find the input common-mode range.
8.3 For the differential amplifier specified in Problem 8.1 let vG2 = 0 and vG1 = vid. Find the value of vid that corresponds to each of the following situations: (a) iD1 = iD2 = 0.1 mA; (b) iD1 = 0.15 mA and iD2 = 0.05 mA; (c) iD1 = 0.2 mA and iD2 = 0 (Q2 just cuts off); (d) iD1 = 0.05 mA and iD2 = 0.15 mA; (e) iD1 = 0 mA (Q1 just cuts off ) and iD2 = 0.2 mA. For each case, find vS, vD1, vD2, and (vD2 − vD1).
8.4 For the differential amplifier specified in Prob-lem 8.2, let vG2 = 0 and vG1 = vid. Find the range of vid needed to steer the bias current from one side of the pair to the other. At each end of this range, give the value of the volt-age at the common-source terminal and the drain voltages.
8.5 Consider the differential amplifier specified in Prob-lem 8.1 with G2 grounded and vG1 = vid. Let vid be adjusted to the value that causes iD1 = 0.11 mA and iD2 = 0.09 mA. Find the corresponding values of vGS2, vS, vGS1, and hence vid.
What is the difference output voltage vD2−vD1? What is the voltage gain (vD2 − vD1) ⁄vid? What value of vid results in iD1 = 0.09 mA and iD2 = 0.11 mA?
D 8.6 Design the circuit in Fig. P8.6 to obtain a dc voltage of +0.2V at each of the drains of and when V. Operate all transistors at V and assume that for the process technology in which the cir-cuit is fabricated, V and μA/V2.
Neglect channel-length modulation. Determine the values of R, and the W/L ratios of , and What is the input common-mode voltage range for your design?
k′ n k′ pW/L vD1 vG1 vS vG2 2.5 V 2.5 V 0.5 mA 4 k vD2 4 k Q1 Q2 Figure P8.2 Q1 Q2 vG1 vG2 = 0 = VOV 0.2 = Vtn 0.5 = μnCox 250 = RD, Q1 Q2, Q3, Q4.
Q1 Q2 vG1 vG2 Q3 VDD 1.2 V VSS 1.2 V 1.2 V RD RD Q4 R 0.1 mA 0.4 mA Figure P8.6 CHAPTER 8 P RO BL E MS 668 Chapter 8 Differential and Multistage Amplifiers 8.7 The table providing the answers to Exercise 8.3 shows that as the maximum input signal to be applied to the differ-ential pair is increased, linearity is maintained at the same level by operating at a higher VOV. If |vid|max is to be 160 mV, use the data in the table to determine the required VOV and the corresponding values of W/L and gm.
8.8 Use Eq. (8.23) to show that if the term involving is to be kept to a maximum value of k then the maximum possible fractional change in the transistor current is given by and the corresponding maximum value of vid is given by Evaluate both expressions for k = 0.01, 0.1, and 0.2.
8.9 An NMOS differential amplifier utilizes a bias current of 400 μA. The devices have Vt = 0.5 V, W = 20 μm, and L = 0.5 μm, in a technology for which μnCox = 200 μA/V2. Find VGS, and gm in the equilibrium state. Also find the value of vid for full-current switching. To what value should the bias current be changed in order to double the value of vid for full-current switching?
D 8.10 Design the MOS differential amplifier of Fig.
8.5 to operate at VOV = 0.25 V and to provide a transcon-ductance gm of 1 mA/V. Specify the W/L ratios and the bias current. The technology available provides Vt = 0.8 V and μnCox = 100 μA/V2.
8.11 Consider the NMOS differential pair illustrated in Fig. 8.5 under the conditions that I = 100 μA, using FETs for which and Vt = 1 V. What is the voltage on the common-source connection for vG1 = vG2 = 0?
2 V? What is the relation between the drain currents in each of these situations? Now for vG2 = 0 V, at what voltages must vG1 be placed to reduce iD2 by 10%? to increase iD2 by 10%?
What is the differential voltage, vid = vG2 − vG1, for which the ratio of drain currents iD2 ⁄iD1 is 1.0? 0.5? 0.9? 0.99? For the current ratio iD1 ⁄iD2 = 20.0, what differential input is required?
8.12 (a) For the MOS differential amplifier of Fig. 8.1 with and use Eqns. (8.23) and (8.24) to derive an expression for the out-put differential voltage in terms of the input differential voltage (b) Sketch and clearly label the voltage transfer characteristic (VTC), that is, versus , over the range , where is the overdrive volt-age at which each transistor is operating in the equilibrium state. What is the slope of the nearly linear portion of the VTC near the origin? This is the differential voltage gain.
(c) Show on the same coordinates how the VTC changes if the bias current I is doubled? What is the change in the dif-ferential voltage gain?
(d) Prepare another sketch for case (b). Show on the same coordinates what happens to the VTC if the W/L ratio of each transistor is doubled. What is the change in the differ-ential voltage gain?
Section 8.2: Small-Signal Operation of the MOS Differential Pair 8.13 An NMOS differential amplifier is operated at a bias current I of 0.4 mA and has a W/L ratio of 32, μnCox = 200 μA/V2, VA = 10 V, and RD = 5 kΩ. Find VOV, gm, ro, and Ad.
D 8.14 It is required to design an NMOS differential amplifier to operate with a differential input voltage that can be as high as 0.1 V while keeping the nonlinear term under the square root in Eq. (8.23) to a maximum of 0.05. A transconductance gm of 1 mA/V is needed. Find the required values of VOV, I, and W/L. Assume that the technology available has μnCox = 200 μA/V2. What differential gain Ad results when RD = 10 kΩ? Assume λ = 0. What is the resulting output signal corresponding to vid at its maximum value?
D 8.15 Design a MOS differential amplifier to operate from -V power supplies and dissipate no more than 2 mW in the equilibrium state. The differential voltage gain is to be 5 V/V and the output common-mode dc voltage is to be 0.5 V. (Note: This is the dc voltage at the drains).
Assume μA/V2 and neglect the Early effect.
Specify I, and W/L. D 8.16 Design a MOS differential amplifier to operate from supplies and dissipate no more than 2 mW in its equi-librium state. Select the value of so that the value of that steers the current from one side of the pair to the other is 0.4 V. The differential voltage gain is to be 5 V/V.
Assume μA/V2 and neglect the Early effect. Spec-ify the required values of I, and W/L. 8.17 An NMOS differential amplifier employing equal drain resistors, k , has a differential gain of 20 V/V.
(a) What is the value of for each of the two transistors? (b) If each of the two transistors is operating at an overdrive voltage V, what must the value of I be?
(c) For what is the dc voltage across each (d) If is 20-mV peak-to-peak sine wave applied in a bal-anced manner but superimposed on V, what is vid 2 ΔImax I 2 ⁄ -------------2 k 1 k – ( ) = vidmax 2 kV OV = kn ′ (W/L) = 400 μA/V 2, vG1 VCM vid 2 ⁄ + = vG2 VCM vid 2 ⁄ , – = vod vD2 vD1 – ≡ vid.
vod vid 2VOV vid 2VOV ≤ ≤ – VOV 1 ± Ad μnCox 400 = RD, 1-V ± VOV vid Ad k′ n 400 = RD, RD 47 = Ω Ad gm VOV 0.2 = vid 0, = RD?
vid VCM 0.5 = Problems 669 CHAPTER 8 P RO BL E MS the lowest value that must have to ensure saturation-mode operation for and at all times? Assume V.
8.18 A MOS differential amplifier is designed to have a differential gain equal to the voltage gain obtained from a common-source amplifier. Both amplifiers utilize the same values of and supply voltages, and all the transis-tors have the same W/L ratios. What must the bias current I of the differential pair be relative to the bias current of the CS amplifier? What is the ratio of the power dissipation of the two circuits?
8.19 A differential amplifier is designed to have a differen-tial voltage gain equal to the voltage gain of a common-source amplifier. Both amplifiers use the same values of and supply voltages and are designed to dissipate equal amounts of power in their equilibrium or quiescent state. As well, all the transistors use the same channel length. What must the width W of the differential-pair transistors be rela-tive to the width of the CS transistor?
D 8.20 Figure P8.20 shows a MOS differential amplifer with the drain resistors implemented using diode-connected PMOS transistors, and . Let and be matched, and and be matched.
(a) Find the differential half-circuit and use it to derive an expression for in terms of and (b) Neglecting the effect of the output resistances find in terms of and (c) If and all four transistors have the same chan-nel length, find that results in V/V.
8.21 Find the differential half-circuit for the differential amplifier shown in Fig. P8.21 and use it to derive an expres-sion for the differential gain in terms of , , and . Neglect the Early effect. What is the gain with ? What is the value of (in terms of ) that reduces the gain to half this value?
8.22 The resistance in the circuit of Fig. P8.21 can be implemented by using a MOSFET operated in the triode region, as shown in Fig. P8.22. Here implements with the value of determined by the voltage at the gate of .
VDD Q1 Q2 Vt 0.5 = Ad RD ID RD RD Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 VDD I vid 2 vid 2 Figure P8.20 Ad gm1,2, gm3,4, ro1,2, ro3,4.
ro, Ad μn, μp, W L ⁄ ( )1 2 , , W L ⁄ ( )3 4 , .
μn 4μp = W1 2 , W3 4 , ⁄ ( ) Ad 10 = Ad vod vid ⁄ ≡ gm RD Rs Rs 0 = Rs 1 gm ⁄ Q1 Q2 VDD vod VSS RD RD Rs – I 2 – I 2 vid 2 vid 2 Figure P8.21 Rs Q3 Rs, Rs VC Q3 Q1 Q2 Q3 VDD – VSS VC RD RD – I 2 – I 2 vG1 vG2 vod Figure P8.22 CHAPTER 8 P RO BL E MS 670 Chapter 8 Differential and Multistage Amplifiers (a) With V, and assuming that and are operating in saturation, what dc voltages appear at the sources of and Express these in terms of the over-drive voltage at which each of and operates, and . (b) For the situation in (a), what current flows in What overdrive voltage is operating at, in terms of , , and ?
(c) Now consider the case and , where is a small signal. Convince yourself that now conducts current and operates in the triode region with a small What resistance does it have, expressed in terms of the overdrive voltage at which it is operating. This is the resistance Now if all three transistors have the same W/L, express in terms of , and (d) Find and hence that result in (i) (ii) 8.23 The circuit of Fig. P8.23 shows an effective way of implementing the resistance needed for the circuit in Fig. P8.21. Here is realized as the series equivalent of two MOSFETs and that are operated in the triode region, thus, + Assume that and are matched and operate in saturation at an overdrive volt-age that corresponds to a drain bias current of I/2.
Also, assume that and are matched.
(a) With V, what dc voltages appear at the sources of and What current flows through and At what overdrive voltages are and oper-ating? Find an expression for for each of and and hence for in terms of and .
(b) Now with and where is a small signal, find an expression of the voltage gain in terms of and D 8.24 Figure P8.24 shows a circuit for a differential amplifier with an active load. Here Q1 and Q2 form the differ-ential pair, while the current source transistors Q4 and Q5 form the active loads for Q1 and Q2, respectively. The dc bias circuit that establishes an appropriate dc voltage at the drains of Q1 and Q2 is not shown. It is required to design the circuit to meet the following specifications: (a) Differential gain Ad = 80 V/V.
(b) IREF = I = 100 μA.
(c) The dc voltage at the gates of Q6 and Q3 is +1.5 V.
(d) The dc voltage at the gates of Q7, Q4, and Q5 is −1.5 V.
The technology available is specified as follows: μnCox = 3μpCox = 90 μA/V2; Vtn = = 0.7 V, VAn = = 20 V.
Specify the required value of R and the W/L ratios for all transistors. Also specify ID and at which each transis-tor is operating. For dc bias calculations you may neglect channel-length modulation.
vG1 vG2 0 = = Q1 Q2 Q1 Q2.
VOV Q1 Q2 Vt Q3?
VOV3 Q3 VC VOV Vt vG1 + vid 2 ⁄ = vG2 – vid 2 ⁄ = vid Q3 vDS.
rDS VOV3 Rs.
Rs VOV VOV3, gm1, 2.
VOV3 VC Rs 1 gm1 2 , ; ⁄ = Rs 0.5 gm1,2 ⁄ .
= Rs Rs Q3 Q4 Rs rDS3 = rDS4.
Q1 Q2 VOV Q3 Q4 Q1 Q3 Q4 Q2 VDD –VSS RD RD – I 2 – I 2 vG1 vG2 vod Figure P8.23 vG1 vG2 = 0 = Q1 Q2?
Q3 Q4?
Q3 Q4 rDS Q3 Q4 Rs W L ⁄ ( )1 2 , , W L ⁄ ( )3 4 , , gm1,2 vG1 vid 2 ⁄ = vG2 vid 2, ⁄ – = vid Ad vod vid ⁄ ≡ gm1,2, RD, W L ⁄ ( )1 2 , , W L ⁄ ( )3 4 , .
Vtp V Ap V GS R Q3 Q6 Q7 Q4 Q5 Q2 Q1 I IREF 2.5 V 2.5 V vid2 vid2 vod Figure P8.24 Problems 671 CHAPTER 8 P RO BL E MS 8.25 A design error has resulted in a gross mismatch in the circuit of Fig. P8.25. Specifically, Q2 has twice the W/L ratio of Q1. If vid is a small sine-wave signal, find: (a) ID1 and ID2.
(b) VOV for each of Q1 and Q2.
(c) The differential gain Ad in terms of RD, I, and VOV.
D 8.26 For the cascode differential amplifier of Fig.
8.12(a) show that if all transistors have the same channel length and are operated at the same and assuming that , the differential gain is given by Now design the amplifier to obtain a differential gain of 1000 V/V. Use V. If V/μm, spec-ify the required channel length L. If is to be as high as possible but the power dissipation in the amplifier (in equi-librium) is to be limited to 1 mW, what bias current I would you use? Let V.
8.27 An NMOS differential pair is biased by a cur-rent source I = 0.2 mA having an output resistance RSS = 100 kΩ. The amplifier has drain resistances RD = 10 kΩ, using transistors with = 3 mA/V2, and ro that is large.
If the output is taken differentially and there is a 1% mis-match between the drain resistances, find , and CMRR.
8.28 For the differential amplifier shown in Fig. P8.2, let Q1 and Q2 have = 4 mA/V2, and assume that the bias current source has an output resistance of 30 kΩ.
Find , gm, , , and the CMRR (in dB) obtained with the output taken differentially. The drain resistances are known to have a mismatch of 2%.
D 8.29 The differential amplifier in Fig. P8.29 uti-lizes a resistor RSS to establish a 1-mA dc bias current. Note that this amplifier uses a single 5-V supply and thus the dc common-mode voltage VCM cannot be zero. Transistors Q1 and Q2 have = 2.5 mA/V2, Vt = 0.7 V, and λ = 0.
(a) Find the required value of VCM.
(b) Find the value of RD that results in a differential gain Ad of 8 V/V.
(c) Determine the dc voltage at the drains.
(d) Determine the common-mode gain . (Hint: You need to take into account.) (e) Use the common-mode gain found in (d) to determine the change in VCM that results in Q1 and Q2 entering the tri-ode region.
8.30 The objective of this problem is to determine the common-mode gain and hence the CMRR of the differen-tial pair arising from a simultaneous mismatch in gm and in RD.
(a) Refer to the circuit in Fig. 8.13(a) and its equivalent in Fig. 8.14, and let the two drain resistors be denoted RD1 and RD2 where RD1 = RD + and RD2 = RD − Also let gm1 = gm + and gm2 = gm − Follow an analysis process similar to that used to derive Eq.
(8.63) to show that Q1 Q2 RD RD I VDD VSS vid2 vid2 WL 2WL vod Figure P8.25 VOV V′ An V′ Ap V′ A = = Ad Ad 2 VA VOV ⁄ ( )2 = VOV 0.2 = V′ A 10 = gm VDD VSS 0.9 = – = k′ nW/L Ad Acm , k′ p W/L ( ) VOV Ad Acm k′ nW/L ΔVD1 ΔV CM ⁄ 1 g ⁄ m Q1 Q2 RD RD VDD 5 V RSS 1 k VCM vid 1 mA vod Figure P8.29 (ΔRD 2) ⁄ (ΔRD 2) ⁄ .
(Δgm 2) ⁄ (Δgm 2).
⁄ CHAPTER 8 P RO BL E MS 672 Chapter 8 Differential and Multistage Amplifiers Note that this equation indicates that RD can be deliberately varied to compensate for the initial variability in gm and RD, that is, to minimize Acm.
(b) In a MOS differential amplifier for which RD = 5 kΩ and RSS = 25 kΩ, the common-mode gain is measured and found to be 0.002 V/V. Find the percentage change required in one of the two drain resistors so as to reduce Acm to zero (or close to zero).
D 8.31 A MOS differential amplifier utilizing a simple current source to provide the bias current I is found to have a CMRR of 60 dB. If it is required to raise the CMRR to 100 dB by adding a cascode transistor to the current source, what must the intrinsic gain of the cascode transistor be?
If the cascode transistor is operated at V, what must its be? If for the specific technology utilized V/μm, specify the channel length L of the cascode transistor.
Section 8.3: The BJT Differential Pair 8.32 For the differential amplifier of Fig. 8.16(a) let I = 0.5 mA, VCC = VEE = 2.5 V, VCM = −1 V, RC = 8 kΩ, and β = 100. Assume that the BJTs have vBE = 0.7 V at iC = 1 mA. Find the voltage at the emitters and at the outputs.
8.33 An npn differential amplifier with I = 0.5 mA, V, and k utilizes BJTs with and V at mA. If , find , and obtained with V, and with V. Assume that the current source requires a minimum of 0.3 V for proper operation.
8.34 An npn differential amplifier with I = 0.5 mA, V, and k utilizes BJTs with and V at mA. Assuming that the bias current is obtained by a simple current source and that all transistors require a minimum of 0.3 V for operation in the active mode, find the input common-mode range.
8.35 Repeat Exercise 8.9 for an input of −0.3 V.
8.36 An npn differential pair employs transistors for which mV at mA, and . The transistors leave the active mode at V. The col-lector resistors k and the power supplies are V. The bias current I = 20 μA and is supplied with a simple current source.
(a) For V, find , and .
(b) Find the input common-mode range.
(c) If find the value of that increases the cur-rent in by 10%.
8.37 Consider the BJT differential amplifier when fed with a common-mode voltage as shown in Fig. 8.16(a).
As is often the case, the supply voltage may not be pure dc but might include a ripple component of small ampli-tude and a frequency of 120 Hz (see Section 4.5). Thus the supply voltage becomes . Find the ripple compo-nent of the collector voltages, and as well as of the difference output voltage . Comment on the differential amplifier response to this undesirable power-supply ripple.
D 8.38 Consider the differential amplifier of Fig. 8.15 and let the BJT β be very large: (a) What is the largest input common-mode signal that can be applied while the BJTs remain comfortably in the active region with vCB = 0?
(b) If an input difference signal is applied that is large enough to steer the current entirely to one side of the pair, what is the change in voltage at each collector (from the condition for which vid = 0)?
(c) If the available power supply VCC is 2.5 V, what value of IRC should you choose in order to allow a common-mode input signal of ±1.0 V?
(d) For the value of IRC found in (c), select values for I and RC. Use the largest possible value for I subject to the con-straint that the base current of each transistor (when I divides equally) should not exceed 2 μA. Let β = 100.
8.39 To provide insight into the possibility of nonlinear dis-tortion resulting from large differential input signals applied to the differential amplifier of Fig. 8.15, evaluate the normal-ized change in the current iE1, , for differential input signals vid of 5, 10, 20, 30, and 40 mV. Pro-vide a tabulation of the ratio , which represents the proportional transconductance gain of the differential pair, versus vid. Comment on the linearity of the differential pair as an amplifier.
D 8.40 Design the circuit of Fig. 8.15 to provide a differ-ential output voltage (i.e., one taken between the two collec-tors) of 1 V when the differential input signal is 10 mV. A current source of 1 mA and a positive supply of +5 V are available. What is the largest possible input common-mode voltage for which operation is as required? Assume α 1.
D 8.41 One of the trade-offs available in the design of the basic differential amplifier circuit of Fig. 8.15 is between the value of the voltage gain and the range of common-mode input voltage. The purpose of this problem is to demonstrate this trade-off.
(a) Use Eqs. (8.73) and (8.74) to obtain iC1 and iC2 correspond-ing to a differential input signal of 5 mV (i.e., vB1 − vB2 = 5 mV). Assume β to be very high. Find the resulting voltage dif-Acm RD 2RSS -----------⎝ ⎠ ⎛ ⎞Δgm gm ----------ΔRD RD ----------+ ⎝ ⎠ ⎛ ⎞ A0 VOV 0.2 = VA V′ A 10 = VCC VEE 2.5 = = RC 8 = Ω β 100 = vBE 0.7 = iC 1 = vB2 0 = VE, VC1 VC2 vB1 + 0.5 = vB1 0.5 – = VCC VEE 2.5 = = RC 8 = Ω β 100 = vBE 0.7 = iC 1 = vCE vBE 690 = iC 1 = β 50 = vCE 0.3 ≤ RC 82 = Ω, 1.2 ± vB1 vB2 VCM 0 = = = VE, VC1 VC2 vB2 0, = vB1 Q1 VCM VCC vr VCC vr + vC1 vC2, vod vC2 vC1 – ≡ ΔiE1 I ⁄ iE1 I 2 ⁄ ( ) – ( ) I ⁄ = ΔiE1 I ⁄ ( ) vid ⁄ Problems 673 CHAPTER 8 P RO BL E MS ference between the two collectors (vC2 − vC1), and divide this value by 5 mV to obtain the voltage gain in terms of (IRC).
(b) Find the maximum permitted value for VCM while the transistors remain comfortably in the active mode with vCB = 0. Express this maximum in terms of VCC and the gain, and hence show that for a given value of VCC, the higher the gain achieved, the lower the common-mode range. Use this expres-sion to find VCMmax corresponding to a gain magnitude of 100, 200, 300, and 400 V/V. For each value, also give the required value of IRC and the value of RC for I = 1 mA. As an example, discuss what can be achieved with VCC = 10 V.
8.42 For the circuit in Fig. 8.15, assuming α = 1 and IRC = 5 V, use Eqs. (8.70) and (8.71) to find iC1 and iC2, and hence determine vod = vC2 − vC1 for input differential signals vid ≡ vB1 − vB2 of 5 mV, 10 mV, 15 mV, 20 mV, 25 mV, 30 mV, 35 mV, and 40 mV. Plot vo versus vid, and hence comment on the amplifier linearity. As another way of visualizing lin-earity, determine the gain versus vid. Comment on the resulting graph.
8.43 In a differential amplifier using a 3-mA emitter bias current source, the two BJTs are not matched. Rather, one has twice the emitter junction area of the other. For a differ-ential input signal of zero volts, what do the collector cur-rents become? What difference input is needed to equalize the collector currents? Assume α = 1.
8.44 This problem explores the linearization of the transfer characteristics of the differential pair achieved by including emitter-degeneration resistances in the emitters (see Fig.
8.18). Consider the case I = 200 μA with the transistors exhib-iting mV at mA and assume .
(a) With no emitter resistances what value of results when (b) With no emitter resistances use the large-signal model to find and when mV.
(c) Now find the value of that will result in the same and as in (b) but with mV. Use the large-signal model.
(d) Calculate the effective transconductance as the inverse of the total resistances in the emitter circuits in the cases with-out and with the ’s. By what factor is reduced? How does this factor relate to the increase in Comment.
8.45 A BJT differential amplifier uses a 200-μA bias cur-rent. What is the value of gm of each device? If β is 150, what is the differential input resistance?
D 8.46 Design the basic BJT differential amplifier circuit of Fig. 8.19 to provide a differential input resistance of at least 10 kΩ and a differential voltage gain of 100 V/V. The transis-tor β is specified to be at least 100. The available positive power supply is 5 V.
8.47 For a differential amplifier to which a total difference signal of 10 mV is applied, what is the equivalent signal to its corresponding CE half-circuit? If the emitter current source I is 100 μA, what is re of the half-circuit? For a load resistance of 10 kΩ in each collector, what is the half-circuit gain?
What magnitude of signal output voltage would you expect at each collector? Between the two collectors?
8.48 A BJT differential amplifier is biased from a 1-mA constant-current source and includes a 200-Ω resistor in each emitter. The collectors are connected to VCC via 12-kΩ resistors.
A differential input signal of 0.1 V is applied between the two bases.
(a) Find the signal current in the emitters (ie) and the signal voltage vbe for each BJT.
(b) What is the total emitter current in each BJT?
(c) What is the signal voltage at each collector? Assume α = 1.
(d) What is the voltage gain realized when the output is taken between the two collectors?
D 8.49 Design a BJT differential amplifier to amplify a dif-ferential input signal of 0.2 V and provide a differential output signal of 5 V. To ensure adequate linearity, it is required to limit the signal amplitude across each base–emitter junction to a maximum of 5 mV. Another design requirement is that the differential input resistance be at least 50 kΩ. The BJTs available are specified to have β ≥ 100. Give the circuit con-figuration and specify the values of all its components.
D 8.50 Design a bipolar differential amplifier such as that in Fig. 8.19 to operate from V power supplies and to provide differential gain of 40 V/V. The power dissipation in the quiescent state should not exceed 2 mW. (a) Specify the values of I and What dc voltage appears at the collectors?
(b) If what is the input differential resistance?
(c) For mV, what is the signal voltage at each of the collectors?
(d) For the situation in (c), what is the maximum allowable value of the input common mode voltage, ? Recall that to maintain an npn BJT in saturation, should not exceed by more than 0.4 V.
D 8.51 In this problem we explore the trade-off between input common-mode range and differential gain in the design of the bipolar BJT. Consider the bipolar differential amplifier in Fig. 8.15 with the input voltages (a) Bearing in mind that for a BJT to remain in the active mode, should not exceed 0.4 V, show that when vo vid ⁄ ( ) Re vBE 690 = iC 1 = α1 Re, VBE vid 0?
= Re, iC1 iC2 vid 20 = Re iC1 iC2 vid 200 = Gm Re Gm vid?
2.5 ± RC.
β 100, = vid 20 = VCM vB vC vB1 VCM vid 2 ⁄ ( ) + = vB2 VCM vid 2 ⁄ ( ) – = vBC vid CHAPTER 8 P RO BL E MS 674 Chapter 8 Differential and Multistage Amplifiers has a peak , the maximum input common-mode voltage is given by (b) For the case V and mV, use the relationship above to determine for the case V/V. Also find the peak output signal and the required value of . Now if the power dissipation in the circuit is to be limited to 5 mW in the quiescent state (i.e., with vid = 0), find I and (Remember to include the power drawn from the negative power supply V.) (c) If is to be 0 V, and all other conditions remain the same, what gain is achievable?
8.52 For the differential amplifier of Fig. 8.15, let V and V. Find the differential gain . Sketch and clearly label the waveforms for the total col-lector voltages and for the following two cases: (a) (b) 8.53 Consider a bipolar differential amplifier in which the collector resistors are replaced with simple current sources implemented using pnp transistors. Sketch the circuit and give its differential half-circuit. If V for all transistors, find the differential voltage gain achieved.
8.54 For each of the emitter-degenerated differential amplifiers shown in Fig. P8.54, find the differential half-circuit and derive expressions for the differential gain and differential input resistance For each circuit, what dc voltage appears across the bias current source(s) in the quiescent state (i.e., with ). Hence, which of the two circuits will allow a larger negative ?
8.55 Consider a bipolar differential amplifier that, in addi-tion to the collector resistances has a load resistance connected between the two collectors. What does the differ-ential gain become?
8.56 A bipolar differential amplifier having resistance inserted in series with each emitter (as in Fig. 8.21) is biased with a constant current I. When both input terminals are grounded, the dc voltage measured across each is found to be 4 and that measured across each is found to be 40 . What differential voltage gain do you expect the amplifier to have?
8.57 A bipolar differential amplifier with emitter degener-ation resistances and is fed with the arrangement shown in Fig. P8.57. Derive an expression for the overall differential voltage gain If is of such a value that find the gain in terms of v ˆ id VCM max VCMmax VCC 0.4 v ˆ id 2 ------– Ad VT v ˆ id 2 ------+ ⎝ ⎠ ⎛ ⎞ – + = VCC 5 = v ˆ id 10 = VCMmax Ad 100 = v ˆ od IRC RC.
VEE 5 – = – VCMmax Ad VCC + 5 = IRC 4 = Ad vC1 vC2 vB1 1 0.005 sin ωt ( ) + = vB2 1 0.005 – sin ωt ( ) = vB1 1 0.1 sin ωt ( ) + = vB2 1 0.1 – sin ωt ( ) = RC VA 10 = Ad Rid.
vid 0 = VCM VCC VEE RC RC Re Re I VCM vid 2 VCM vid 2 vod (a) Figure P8.54 VEE VCC RC RC 2 Re VCM vid 2 VCM vid 2 – I 2 – I 2 (b) vod RC, RL Ad Re Re VT RC VT Ad Re Re, Gv vod vsig.
⁄ ≡ Rsig vid 0.5vsig, = Gv RC, Problems 675 CHAPTER 8 P RO BL E MS , , and . Now if is doubled, by what factor does increase?
8.58 A particular differential amplifier operates from an emit-ter current source whose output resistance is 0.5 MΩ. What resistance is associated with each common-mode half-circuit?
For collector resistors of 20 kΩ and 1% tolerance, what is the resulting common-mode gain for output taken (a) single-endedly? and (b) differentially?
8.59 Find the voltage gain and the input resistance of the amplifier shown in Fig. P8.59 assuming β = 100.
8.60 Find the voltage gain and input resistance of the amplifier in Fig. P8.60 assuming that β = 100.
8.61 Derive an expression for the small-signal voltage gain of the circuit shown in Fig. P8.61 in two different ways: (a) as a differential amplifier (b) as a cascade of a common-collector stage Q1 and a common-base stage Q2 Assume that the BJTs are matched and have a current gain α, and neglect the Early effect. Verify that both approaches lead to the same result.
8.62 The differential amplifier circuit of Fig. P8.62 utilizes a resistor connected to the negative power supply to estab-lish the bias current I.
(a) For vB1 = vid ⁄ 2 and vB2 = −vid ⁄ 2, where vid is a small sig-nal with zero average, find the magnitude of the differential gain, .
(b) For vB1 = vB2 = vicm, where vicm has a zero average, find the magnitude of the common-mode gain, .
(c) Calculate the CMRR.
(d) If vB1 = 0.1 sin 2π × 60t + 0.005 sin 2π × 1000t volts, and vB2 = 0.1 sin 2π × 60t − 0.005 sin 2π × 1000t, volts, find vo.
re Re α β Gv VCM vid Rsig2 Rsig2 – – vsig 2 vsig 2 Figure P8.57 10 V 25 k vo vi 125 125 0.4 mA Rin Q1 Q2 Figure P8.59 vo vi ⁄ Rin 10 V 25 k vi 0.2 mA 0.2 mA 250 vo Figure P8.60 vo vid ⁄ vo vicm ⁄ Figure P8.61 CHAPTER 8 P RO BL E MS 676 Chapter 8 Differential and Multistage Amplifiers 8.63 For the differential amplifier shown in Fig. P8.63, iden-tify and sketch the differential half-circuit and the common-mode half-circuit. Find the differential gain, the differential input resistance, the common-mode gain assuming the resis-tances RC have 1% tolerance, and the common-mode input resistance. For these transistors, β = 100 and VA = 100 V.
8.64 Consider the basic differential circuit in which the transistors have β = 100 and VA = 100 V, with I = 0.5 mA, REE = 200 kΩ, and RC = 20 kΩ. The collector resistances are matched to within 1%. Find: (a) the differential gain (b) the differential input resistance (c) the common-mode gain (d) the common-mode rejection ratio (e) the input common-mode resistance 8.65 In a differential-amplifier circuit resembling that shown in Fig. 8.26(a), the current generator represented by I and REE consists of a simple common-emitter transistor operating at 100 μA. For this transistor, and those used in the differential pair, VA = 20 V and β = 50. What common-mode input resistance would result?
8.66 A bipolar differential amplifier with I = 0.5 mA uti-lizes transistors for which V and The collector resistances k and are matched to within 2%. Find: (a) the differential gain (b) the common-mode gain and the CMRR if the bias cur-rent I is generated using a simple current mirror (c) the common-mode gain and the CMRR if the bias cur-rent I is generated using a Wilson mirror. (Refer to Eq. 7.81 for Ro of the Wilson mirror.) D 8.67 It is required to design a differential amplifier to pro-vide the largest possible signal to a pair of 10-kΩ load resis-tances. The input differential signal is a sinusoid of 5-mV peak amplitude, which is applied to one input terminal while the other input terminal is grounded. The power supply available is 10 V. To determine the required bias current I, derive an expression for the total voltage at each of the collectors in terms of VCC and I in the presence of the input signal. Then impose the condition that both transistors should remain well out of satura-tion with a minimum vCB of approximately 0 V. Thus determine the required value of I. For this design, what differential gain is achieved? What is the amplitude of the signal voltage obtained between the two collectors? Assume α 1.
D 8.68 Design a BJT differential amplifier that provides two single-ended outputs (at the collectors). The amplifier is to have a differential gain (to each of the two outputs) of at least 100 V/V, a differential input resistance ≥10 kΩ, and a common-mode gain (to each of the two outputs) no greater than 0.1 V/V. Use a 2-mA current source for bias-ing. Give the complete circuit with component values and suitable power supplies that allow for ±2 V swing at each collector. Specify the minimum value that the output resis-tance of the bias current source must have. The BJTs avail-able have β ≥100. What is the value of the input common-mode resistance when the bias source has the lowest acceptable resistance?
8.69 When the output of a BJT differential amplifier is taken differentially, its CMRR is found to be 40 dB higher than when the output is taken single-endedly. If the only source of common-mode gain when the output is taken dif-ferentially is the mismatch in collector resistances, what must this mismatch be (in percent)?
8.70 In a particular BJT differential amplifier, a produc-tion error results in one of the transistors having an emitter– Figure P8.62 Figure P8.63 Q 0.5 mA 0.5 mA 10 k vod 20 k 300 200 k 200 k 10 k 10 V 1 Q2 RC RL RE RC VA 10 = β 100.
= RC 10 = Ω Problems 677 CHAPTER 8 P RO BL E MS base junction area that is twice that of the other. With the inputs grounded, how will the emitter bias current split between the two transistors? If the output resistance of the current source is 500 kΩ and the resistance in each collector (RC) is 12 kΩ, find the common-mode gain obtained when the output is taken differentially. Assume α 1.
Section 8.4: Other Nonideal Characteristics of the Differential Amplifier D 8.71 An NMOS differential pair is to be used in an amplifier whose drain resistors are 10 kΩ ± 1%. For the pair, W/L = 4 mA/V2. A decision is to be made concerning the bias current I to be used, whether 160 μA or 360 μA.
Contrast the differential gain and input offset voltage for the two possibilities.
D 8.72 An NMOS amplifier, whose designed operating point is at VOV = 0.2 V, is suspected to have a variability of Vt of ±5 mV, and of W/L and RD (independently) of ±2%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the out-put offset to zero and thereby compensate for the uncertainties (including that of the other RD), what percentage change from nominal would you require? If by selection you reduced the contribution of the worst cause of offset by a factor of 10, what change in RD would be needed?
8.73 An NMOS differential pair operating at a bias current I of 100 μA uses transistors for which and W/L = 10. Find the three components of input offset voltage under the conditions that = 5%, Δ(W/L)⁄(W/L) = 5%, and In the worst case, what might the total offset be? For the usual case of the three effects being independent, what is the offset likely to be?
8.74 A bipolar differential amplifier uses two well-matched transistors but collector load resistors that are mis-matched by 8%. What input offset voltage is required to reduce the differential output voltage to zero?
8.75 A bipolar differential amplifier uses two transistors whose scale currents IS differ by 10%. If the two collector resis-tors are well matched, find the resulting input offset voltage. 8.76 Modify Eq. (8.119) for the case of a differential amplifier having a resistance RE connected in the emitter of each transistor. Let the bias current source be I.
8.77 A differential amplifier uses two transistors whose β values are β1 and β2. If everything else is matched, show that the input offset voltage is approximately . Evaluate VOS for β1 = 100 and β2 = 200. Assume the differential source resistance to be zero.
8.78 Two possible differential amplifier designs are con-sidered, one using BJTs and the other MOSFETs. In both cases, the collector (drain) resistors are maintained within % of nominal value. The MOSFETs are operated at mV. What input offset voltage results in each case? What does the MOS become if the devices are increased in width by a factor of 4?
8.79 A differential amplifier uses two transistors having VA values of 100 V and 300 V. If everything else is matched, find the resulting input offset voltage. Assume that the two transis-tors are intended to be biased at a VCE of about 10 V.
8.80 A differential amplifier is fed in a balanced or push–pull manner, and the source resistance in series with each base is Rs. Show that a mismatch ΔRs between the val-ues of the two source resistances gives rise to an input offset voltage of approximately (I/2β)ΔRs / [1 + (gm Rs)/β].
8.81 One approach to “offset correction” involves the adjustment of the values of RC1 and RC2 so as to reduce the differential output voltage to zero when both input terminals are grounded. This offset-nulling process can be accom-plished by utilizing a potentiometer in the collector circuit, as shown in Fig. P8.81. We wish to find the potentiometer set-ting, represented by the fraction x of its value connected in series with RC1, that is required for nulling the output offset voltage that results from: (a) RC1 being 4% higher than nominal and RC2 4% lower than nominal (b) Q1 having an area 20% larger than that of Q2 kn ′ k′ n = 250 μA/V 2 R Δ D RD ⁄ Vt Δ = 5 mV.
VT[(1 β1 ⁄ ) (1 β2 ⁄ – )] 2 ± VOV 300 = VOS 1 mA RC1 5 k 1 k RC2 5 k VCC (x) (1 x) Q1 Q2 Figure P8.81 CHAPTER 8 P RO BL E MS 678 Chapter 8 Differential and Multistage Amplifiers 8.82 A differential amplifier for which the total emitter bias current is 500 μA uses transistors for which β is specified to lie between 80 and 200. What is the largest possible input bias current? The smallest possible input bias current? The largest possible input offset current?
8.83 In a particular BJT differential amplifier, a produc-tion error results in one of the transistors having an emitter– base junction area twice that of the other. With both inputs grounded, find the current in each of the two transistors and hence the dc offset voltage at the output, assuming that the collector resistances are equal. Use small-signal analysis to find the input voltage that would restore current balance to the differential pair. Repeat using large-signal analysis and compare results. D 8.84 A large fraction of mass-produced differential-amplifier modules employing 20-kΩ collector resistors is found to have an input offset voltage ranging from +3 mV to −3 mV. By what amount must one collector resistor be adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistor while correspondingly lowering the other, what resistance change is needed? If a potentiometer connected as shown in Fig.
P8.81 is used, what value of potentiometer resistance (speci-fied to 1 significant digit) is needed?
Section 8.5: The Differential Amplifier with Active Load D 8.85 In an active-loaded differential amplifier of the form shown in Fig. 8.32(a), all transistors are characterized by k′ W/L = 3.2 mA/V2, and Find the bias current I for which the gain = 100 V/V. D 8.86 It is required to design the active-loaded differ-ential MOS amplifier of Fig. 8.32 to obtain a differential gain of 50 V/V. The technology available provides μnCox = μA/V2, V, and V/μm and operates from V supplies. Use a bias current I = 200 μA and operate all devices at V.
(a) Find the W/L ratios of the four transistors.
(b) Specify the channel length required of all transistors.
(c) If , what is the allowable range of ?
(d) If I is delivered by a simple NMOS current source operated at the same and having the same channel length as the other four transistors, determine the CMRR obtained.
8.87 Consider the active-loaded MOS differential ampli-fier of Fig. 8.32(a) in two cases: (a) Current source I is implemented with a simple current mirror.
(b) Current source I is implemented with the modified Wilson current mirror shown in Fig. P8.87.
Recalling that for the simple mirror and for the Wilson mirror and assuming that all tran-sistors have the same and show that for case (a) and for case (b) where VOV is the overdrive voltage that corresponds to a drain current of For I = 1 mA, and find CMRR for both cases.
D 8.88 Consider an active-loaded differential amplifier such as that shown in Fig. 8.32(a) with the bias current source implemented with the modified Wilson mirror of Fig.
P8.87 with I = 200 μA. The transistors have and k′ W/L = 5 mA/V2. What is the lowest value of the total power supply (VDD + VSS) that allows each transistor to oper-ate with 8.89 (a) Sketch the circuit of an active-loaded MOS dif-ferential amplifier in which the input transistors are cas-coded and a cascode current mirror is used for the load.
(b) Show that if all transistors are operated at an overdrive voltage VOV and have equal Early voltages the gain is given by V A 20 V.
= vo vid ⁄ 4μpCox 400 = Vt 0.5 = V′ A 20 = 1 ± VOV 0.2 = VCM 0 = vO VOV RSS ro QS = RSS gm7ro7ro5, V A k′W/L, CMRR 2 V A V OV ---------⎝ ⎠ ⎛ ⎞ 2 = CMRR 2 2 V A V OV ---------⎝ ⎠ ⎛ ⎞ 3 = I 2.
⁄ k′W/L 10 mA/V 2 , = VA 10 V, = Q5 Q8 Q6 Q7 RSS I I Figure P8.87 Vt = 0.5 V V DS V GS ?
≥ V A , Ad 2 V A V OV ⁄ ( ) 2 = Problems 679 CHAPTER 8 P RO BL E MS Evaluate the gain for V OV = 0.25 V and V A = 20 V.
8.90 Figure P8.90 shows the active-loaded MOS differen-tial amplifier prepared for small-signal analysis. To help the reader we have already indicated approximate values for some of the node voltages. For instance, the output voltage , which we have derived in the text. The voltage at the common sources has been found to be approx-imately , which is very far from the virtual ground one might assume. Also, the voltage at the gate of the mirror is approximately confirming our contention that the voltage there is vastly different from the output voltage, hence the lack of balance in the circuit and the unavailability of a differential half-circuit. Find the currents labeled to Determine their values in the sequence of their number-ing and reflect on the results. You will find that there is some inconsistency, which is a result of the approximations we have made. Note that all transistors are assumed to be operating at the same .
8.91 An active-loaded NMOS differential amplifier oper-ates with a bias current I of 100 μA. The NMOS transistors are operated at V and the PMOS devices at V. The Early voltages are 20 V for the NMOS and 12 V for the PMOS transistors. Find and For what value of load resistance is the gain reduced by a factor of 2?
8.92 This problem investigates the effect of transistor mis-matches on the input offset voltage of the active-loaded MOS differential amplifier of Fig. 8.32(a). For this purpose, ground both input terminals and short-circuit the output node to ground.
(a) If the amplifying transistors and exhibit a W/L mismatch of find the resulting short-circuit out-put current and hence show that the corresponding is given by where is the overdrive voltage at which and are operating.
(b) Repeat for a mismatch in the ratios of the mirror transistor and to show that the corre-sponding is given by where is the overdrive voltage at which and are operating.
(c) For a circuit in which all transistors are operated at V and all W/L ratios are accurate to within % of nominal, find the worst-case total offset voltage .
8.93 The differential amplifier in Fig. 8.37(a) is operated with I = 400 μA, with devices for which VA = 16 V and β = 100. What differential input resistance, output resistance, equivalent transconductance, and open-circuit voltage gain would you expect? What will the voltage gain be if the input resistance of the subsequent stage is equal to Rid of this stage?
vo 1 2 --- gmro ( )vid = +vid 4 ⁄ vid 4 ⁄ , – i1 i13.
VOV (vid2) (vid2) Q3 Q4 Q1 Q2 ro ro ro ro vo (gmro) vid vg3 vid4 vsvid4 i2 i12 i6 i11 i1 i13 i9 i4 i10 i7 i3 i8 i5 1 2 Figure P8.90 VOV 0.2 = VOV 0.3 = Gm, Ro, Ad.
Q1 Q2 W L ⁄ ( )A, Δ VOS VOS1 VOV 2 ⁄ ( ) = W L ⁄ ( )A Δ W L ⁄ ( )A -----------------------VOV Q1 Q2 W L ⁄ ( )M Δ W L ⁄ Q3 Q4 VOS VOS2 VOV 2 ⁄ ( ) = W L ⁄ ( )M Δ W L ⁄ ( )M ------------------------VOV Q1 Q2 VOV 0.2 = 1 ± VOS CHAPTER 8 P RO BL E MS 680 Chapter 8 Differential and Multistage Amplifiers D 8.94 Design the circuit of Fig. 8.37(a) using a basic cur-rent mirror to implement the current source I. It is required that the equivalent transconductance be 4 mA/V. Use ±5-V power supplies and BJTs that have β = 125 and VA = 100 V. Give the complete circuit with component values and specify the differential input resistance Rid, the output resistance Ro, the open-circuit voltage gain Ad, the input bias current, the input common-mode range, the common-mode gain, and the CMRR.
D 8.95 Repeat the design of the amplifier specified in Problem 8.94 utilizing a Widlar current source [Fig. 7.36] to supply the bias current. Assume that the largest resistance available is 2 kΩ.
D 8.96 Modify the design of the amplifier in Problem 8.94 by connecting emitter-degeneration resistances of val-ues that result in Rid = 125 kΩ. What does Ad become?
8.97 An active-loaded bipolar differential amplifier such as that shown in Fig. 8.37(a) has I = 0.5 mA, VA = 30 V, and β = 150. Find Gm, Ro, Ad, and Rid. If the bias-current source is implemented with a simple npn current mirror, find REE, Acm, and CMRR. If the amplifier is fed differentially with a source having a total of 20 kΩ resistance (i.e., 10 kΩ in series with the base lead of each of Q1 and Q2), find the overall differential voltage gain.
8.98 This problem provides a general approach to the determination of the common-mode gain of the active-loaded differential amplifier of either type (MOS and BJT).
The method is illustrated in Fig. P8.98, in which we have replaced each of and together with their source (emitter) resistances with a controlled source and an output resistance For the MOS case, ; for the bipolar case. Usually and are much larger than the resis-tances at the respective nodes and can be neglected. The cur-rent mirror has been replaced by an equivalent circuit consisting of an input resistance a controlled source with current gain and an output resistance (a) Show that the common-mode gain is given approxi-mately by (b) For the simple MOS mirror consisting of and as in Fig. 8.32(a), show that and hence derive the expression for the common-mode gain given in Eq. (8.146).
(c) For the simple bipolar mirror consisting of and as in Fig. 8.37(a), show that and hence derive the expression for the CM gain given in Eq. (8.165).
8.99 For the active-loaded MOS differential pair, replac-ing the simple current-mirror load by the Wilson mirror of Fig. 7.35(a), find the CM gain. [Hint: Use the general for-mula in Problem 8.98, namely, where is the output resistance of the mirror and is its current transfer ratio. Note, however, that this formula will overestimate because we are neglecting ] 8.100 For the active-loaded bipolar differential pair, replacing the simple current-mirror load by the base-current-compensated mirror of Fig. 7.33, find the expected system-atic input offset voltage. Evaluate for 8.101 For the active-loaded bipolar differential pair, replac-ing the simple current-mirror load by the Wilson mirror of Fig. 7.34(a), find the expected systematic input offset volt-age. Evaluate for 8.102 Figure P8.102 shows a differential cascode ampli-fier with an active load formed by a Wilson current mirror.
Utilizing the expressions derived in Chapter 7 for the output resistance of a bipolar cascode and the output resistance of the Wilson mirror, and assuming all transistors to be identi-cal, show that the differential voltage gain Ad is given approximately by Q1 Q2 2RSS 2REE ( ) Gmcmvicm Ro1, 2.
Gmcm vicm 2RSS ⁄ = vicm 2REE ⁄ Ro1 Ro2 Rin, Am, Rom.
Acm vo vicm --------- GmcmRom Am 1 – ( ) ≡ Q3 Q4, Am 1 1 1 gm3ro3 ---------------+ = Acm Q3 Q4, Am 1 1 2 βP ------+ ⎝ ⎠ ⎛ ⎞ = Ro2 Ro1 Current Mirror Gmcmvicm Gmcmvicm vo Rin Rom Amii ii Figure P8.98 Acm Acm Rom 2REE ------------ Am 1 – ( ) = Rom Am Acm Ro2.
VOS βP 50.
= VOS βP 50.
= Ad 1 3 ---βgmro = Problems 681 CHAPTER 8 P RO BL E MS Evaluate Ad for the case of β = 100 and VA = 30 V.
D 8.103 Consider the bias design of the Wilson-loaded cascode differential amplifier shown in Fig. P8.102.
(a) What is the largest signal voltage possible at the output without Q7 saturating? Assume that the CB junction con-ducts when the voltage across it exceeds 0.4 V.
(b) What should the dc bias voltage established at the out-put (by an arrangement not shown) be in order to allow for positive output signal swing of 1.5 V?
(c) What should the value of VBIAS be in order to allow for a negative output signal swing of 1.5 V?
(d) What is the upper limit on the input common-mode voltage vCM?
8.104 Figure P8.104 shows a modified cascode differ-ential amplifier. Here Q3 and Q4 are the cascode transistors.
However, the manner in which Q3 is connected with its base current feeding the current mirror Q7–Q8 results in very interesting input properties. Note that for simplicity the cir-cuit is shown with the base of Q2 grounded.
(a) With vI = 0 V dc, find the input bias current IB assuming all transistors have equal value of β. Compare the case with-out the Q7–Q8 connection.
(b) With vI = 0 V (dc) + vid, find the input signal current ii and hence the input differential resistance Rid. Compare with the case without the Q7–Q8 connection. By what factor does Rid increase?
8.105 For the folded-cascode differential amplifier of Fig.
8.40, find the value of VBIAS that results in the largest possi-ble positive output swing, while keeping Q3, Q4, and the pnp transistors that realize the current sources out of saturation.
Assume VCC = VEE = 5 V. If the dc level at the output is 0 V, find the maximum allowable output signal swing. For I = 0.4 mA, βP = 50, βN = 150, and VA = 120 V find Gm, Ro4, Ro5, Ro, and Ad.
8.106 For the BiCMOS differential amplifier in Fig.
P8.106 let VDD = VSS = 3 V, I = 0.4 mA, for p-channel MOSFETs is 10 V, for npn transistors is 30 V. Find Gm, Ro, and Ad.
vo Q6 Q4 Q3 Q5 Q1 Q2 Q7 I VCC 5 VEE 5 V vd VBIAS Figure P8.102 VEE Q7 Q8 Q5 vO vI IB I Q3 Q1 Q4 Q6 VCC Q2 Figure P8.104 kp ′ W/L = 6.4 mA/V2; VA V A CHAPTER 8 P RO BL E MS 682 Chapter 8 Differential and Multistage Amplifiers Section 8.6: Multistage Amplifiers 8.107 Consider the circuit in Fig. 8.41 with the device geometries (in μm) shown in the Table P8.107. Let IREF = 225 μA, = 0.75 V for all devices, μnCox = 180 μA/V2, μpCox = 60 μA/V2, = 9 V for all devices, VDD = VSS = 1.5 V. Determine the width of Q6, W, that will ensure that the op amp will not have a systematic offset voltage. Then, for all devices evaluate ID, gm, and ro. Provide your results in a table similar to Table 8.1. Also find A1, A2, the open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of VA on the bias current.
D 8.108 The two-stage CMOS op amp in Fig. P8.108 is fabricated in a 0.18-μm technology having 400 μA/V2, V.
(a) With A and B grounded, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain cur-rent of 200 μA. Design so that all transistors operate at 0.2 V-overdrive voltages. Specify the W/L ratio required for each MOSFET. Present your results in tabular form. What is the dc voltage at the output (ideally)?
(b) Find the input common-mode range.
(c) Find the allowable range of the output voltage.
(s) With and , find the voltage gain . Assume an Early voltage of 5 V.
D 8.109 In a particular design of the CMOS op amp of Fig. 8.41 the designer wishes to investigate the effects of increasing the W/L ratio of both Q1 and Q2 by a factor of 4.
Assuming that all other parameters are kept unchanged, refer to Example 8.5 to help you answer the following questions: (a) Find the resulting change in and in gm of Q1 and Q2.
(b) What change results in the voltage gain of the input stage? In the overall voltage gain?
(c) What is the effect on the input offset voltages? (You might wish to refer to Section 8.4).
8.110 Consider the amplifier of Fig. 8.41, whose parame-ters are specified in Example 8.5. If a manufacturing error results in the W/L ratio of Q7 being 50/0.8, find the current that Q7 will now conduct. Thus find the systematic offset voltage that will appear at the output. (Use the results of Example 8.5.) Assuming that the open-loop gain will remain approximately unchanged from the value found in Example 8.5, find the corresponding value of input offset voltage, VOS. 8.111 Consider the input stage of the CMOS op amp in Fig. 8.41 with both inputs grounded. Assume that the two sides of the input stage are perfectly matched except that the threshold voltages of Q3 and Q4 have a mismatch Show that a current gm3 appears at the output of the first stage. What is the corresponding input offset volt-age?
8.112 Figure P8.112 shows a bipolar op-amp circuit that resembles the CMOS op amp of Fig. 8.41. Here, the input differential pair Q1–Q2 is loaded in a current mirror formed by Q3 and Q4. The second stage is formed by the current-source-loaded common-emitter transistor Q5. Unlike the CMOS circuit, here there is an output stage formed by the emitter follower Q6. The function of capacitor CC will be explained later in Chapter 10. All transistors have β = 100, = 0.7 V, and (a) For inputs grounded and output held at 0 V (by negative feedback, not shown) find the emitter currents of all transis-tors.
(b) Calculate the gain of the amplifier with RL = 10 kΩ.
Q1 Q4 Q3 Q2 VDD I vo VSS Figure P8.106 Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/L 30/ 0.5 30/ 0.5 10/ 0.5 10/ 0.5 60/ 0.5 W/ 0.5 60/ 0.5 60/ 0.5 Table P8.107 Vt VA VOV , VGS , k′ n 4k′ p = = Vtn Vtp 0.4 = – = vA vid 2 ⁄ = vB vid 2 ⁄ – = vo vid ⁄ VOV Vt .
Δ Vt Δ VBE ro ∞.
= Problems 683 CHAPTER 8 P RO BL E MS D 8.113 It is required to design the circuit of Fig. 8.42 to provide a bias current IB of 225 μA with Q8 and Q9 as matched devices having W/L = 60/0.5. Transistors Q10, Q11, and Q13 are to be identical and must have the same gm as Q8 and Q9. Transistor Q12 is to be four times as wide as Q13.
Let and VDD = VSS = 1.5 V. Find the required value of RB. What is the voltage drop across RB? Also specify the W/L ratios of Q10, Q11, Q12, and Q13 and give the expected dc voltages at the gates of Q12, Q10, and Q8.
8.114 A BJT differential amplifier, biased to have re = 100 Ω and utilizing two 100-Ω emitter resistors and 5-kΩ loads, drives a second differential stage biased to have re = 50 Ω. All BJTs have β = 100. What is the voltage gain of the first stage? Also find the input resistance of the first stage, and A B Q3 Q4 Q1 Q2 VDD 1 V VSS 1 V Q6 Q5 Q8 IREF 200 A Q7 vo Figure P8.108 Q3 Q2 Q1 0.2 mA Q4 Q5 Q6 RL CC 0.5 mA 1 mA 5 V 5 V vo Figure P8.112 kn ′ = 3kp ′ = 180 μA/V 2, CHAPTER 8 P RO BL E MS 684 Chapter 8 Differential and Multistage Amplifiers the current gain from the input of the first stage to the col-lectors of the second stage.
8.115 In the multistage amplifier of Fig. 8.43, emitter resis-tors are to be introduced—100 Ω in the emitter lead of each of the first-stage transistors and 25 Ω for each of the second-stage transistors. What is the effect on input resistance, the voltage gain of the first stage, and the overall voltage gain?
Use the bias values found in Example 8.6.
D 8.116 Consider the circuit of Fig. 8.43 and its output resis-tance. Which resistor has the most effect on the output resis-tance? What should this resistor be changed to if the output resistance is to be reduced by a factor of 2? What will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to approximately its prior value?
D 8.117 (a) If, in the multistage amplifier of Fig. 8.43, the resistor R5 is replaced by a constant-current source 1 mA, such that the bias situation is essentially unaffected, what does the overall voltage gain of the amplifier become?
Assume that the output resistance of the current source is very high. Use the results of Example 8.7.
(b) With the modification suggested in (a), what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 Ω to ground? The original amplifier (before modification) has an output resistance of 152 Ω and a voltage gain of 8513 V/V. What is its gain when loaded by 100 Ω? Comment.
Use β = 100.
8.118 Figure P8.118 shows a three-stage amplifier in which the stages are directly coupled. The amplifier, however, utilizes bypass capacitors, and, as such, its frequency response falls off at low frequencies. For our purposes here, we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest.
(a) Find the dc bias current in each of the three transistors.
Also find the dc voltage at the output. Assume β = 100, and neglect the Early effect.
(b) Find the input resistance and the output resistance.
(c) Use the current-gain method to evaluate the voltage gain vo ⁄vi.
8.119 The MOS differential amplifier shown in Fig.
P8.119 utilizes three current mirrors for signal transmission: has a transmission factor of 2 [i.e., ], has a transmission fac-tor of 1, and has a transmission factor of 2. All transistors are sized to operate at the same overdrive volt-age, . All transistors have the same Early voltage .
(a) Provide in tabular form the values of and of each of the eight transistors in terms of I, and .
(b) Show that the differential voltage gain is given by (c) Show that the CM gain is given by where is the output resistance of the bias current source I.
[Hint: Replace each of and together with their source resistance with a controlled current-source and an output resistance. For each current mir-ror, the current transfer ratio is given by (ideal) where and are the parameters of the input transistor of the mirror.] vi vo 82 k 100 k 9.5 k 5.1 k 10.6 k 10 k 10 V 10 V 4.5 k Q1 Q2 Q3 Figure P8.118 VBE = 0.7 V, Q4 Q6 – W L ⁄ ( )6 W L ⁄ ( )4 ⁄ 2 = Q3 Q5 – Q7 Q8 – VOV VA ID, gm, ro VOV, VA Ad Ad 2gm1 ro6 ro8 || ( ) VA VOV ⁄ = = Acm ro6 ro8 || RSS -------------------1 gm7ro7 ---------------RSS Q1 Q2 2RSS vicm 2RSS ⁄ Figure P8.119 Q3 Q4 Q1 Q2 VDD VDD Q6 Q7 Q5 Q8 vo I Ai Ai 1 1 gmro -----------– ⎝ ⎠ ⎛ ⎞ gm ro Problems 685 CHAPTER 8 P RO BL E MS (d) If the current-source I is implemented using a simple mirror and the MOS transistor is operated at the same , show that the CMRR is given by (e) Find the input CM range and the output linear range in terms of , and .
D 8.120 For the circuit shown in Fig. P8.120, which uses a folded cascode involving transistor Q3, all transistors have for the currents involved, VA = 200 V, and β = 100. The circuit is relatively conventional except for Q5, which operates in a Class B mode (we will study this in Chapter 11) to provide an increased negative output swing for low-resistance loads.
(a) Perform a bias calculation assuming high β, VA = ∞, v+ = v− = 0 V, and vO is stabilized by feedback to about 0 V. Find R so that the reference current IREF is 100 μA. What are the voltages at all the labeled nodes?
(b) Provide in tabular form the bias currents in all transistors together with gm and ro for the signal transistors (Q1, Q2, Q3, Q4, and Q5) and ro for QC, QD, and QG.
(c) Now, using β = 100, find the voltage gain vo ⁄(v+ − v−), and in the process, verify the polarity of the input terminals.
(d) Find the input and output resistances.
(e) Find the input common-mode range for linear operation.
(f ) For no load, what is the range of available output volt-ages, assuming (g) Now consider the situation with a load resistance con-nected from the output to ground. At the positive and negative limits of the output signal swing, find the smallest load resis-tance that can be driven if one or the other of Q1 or Q2 is allowed to cut off.
D 8.121 In the CMOS op amp shown in Fig. P8.121, all MOS devices have μnCox = 2μpCox = 40 μA/V2, and L = 5 μm. Device widths are indicated on the diagram as multiples of W, where W = 5 μm.
(a) Design R to provide a 10-μA reference current.
(b) Assuming vO = 0 V, as established by external feedback, perform a bias analysis, finding all the labeled node volt-ages, VGS and ID for all transistors.
(c) Provide in table form ID, VGS, gm, and ro for all devices.
(d) Calculate the voltage gain the input resis-tance, and the output resistance.
(e) What is the input common-mode range?
(f ) What is the output signal range for no load?
(g) For what load resistance connected to ground is the out-put negative voltage limited to −1 V before Q7 begins to con-duct?
(h) For a load resistance one-tenth of that found in (g), what is the output signal swing?
VOV CMRR 4 VA VOV ⁄ ( )2 = VDD Vt VOV Q1 QA QE QF QG QD Q5 Q4 QB QC IREF Q2 Q3 v v 1 1 1 10 2 5 V 5 V vO D B C G A R E 1 2 F Figure P8.120 VBE = 0.7 V VBE = 0.7 V, V CEsat = 0.3 V?
Vt = 1 V, VA = 50 V, vo v+ −v− ( ) ⁄ , QA QB QF QE IREF 1W 1W 1W 1W 1W 2W 2W 2W 4W QC Q7 Q1 Q3 Q4 Q5 10W Q6 Q2 1W 20W QD 5W R vO v v B C D G H A E F 5 V 5 V Figure P8.121 CHAPTER 9 Frequency Response Introduction 687 9.1 Low-Frequency Response of the CS and CE Amplifiers 689 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 701 9.3 High-Frequency Response of the CS and CE Amplifiers 711 9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 721 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 731 9.6 High-Frequency Response of the CG and Cascode Amplifiers 746 9.7 High-Frequency Response of the Source and Emitter Followers 756 9.8 High-Frequency Response of Differential Amplifiers 760 9.9 Other Wideband Amplifier Configurations 770 9.10 Multistage Amplifier Examples 779 Summary 784 Problems 785 687 IN THIS CHAPTER YOU WILL LEARN 1. How coupling and bypass capacitors cause the gain of discrete-circuit amplifiers to fall off at low frequencies, and how to obtain an estimate of the frequency fL at which the gain decreases by 3 dB below its value at midband.
2. The internal capacitive effects present in the MOSFET and the BJT and how to model these effects by adding capacitances to the hybrid-model of each of the two transistor types.
3. The high-frequency limitation on the gain of the CS and CE amplifiers and how the gain falloff and the upper 3-dB frequency fH are mostly determined by the small capacitance between the drain and gate (collector and base).
4. Powerful methods for the analysis of the high-frequency response of amplifier circuits of varying complexity.
5. How the cascode amplifier studied in Chapter 7 can be designed to ob-tain wider bandwidth than is possible with the CS and CE amplifiers.
6. The high-frequency performance of the source and emitter followers.
7. The high-frequency performance of differential amplifiers.
8. Circuit configurations for obtaining wideband amplification.
Introduction Except for brief comments in Sections 5.6.8 and 6.6.8, our study of transistor amplifiers in Chapters 5 through 8 has assumed that their gain is constant independent of the frequency of the input signal. This would imply that their bandwidth is infinite, which of course is not true! To illustrate, we show in Fig. 9.1 a sketch of the magnitude of the gain versus the fre-quency of the input signal of a discrete-circuit BJT or MOS amplifier. Observe that there is indeed a wide frequency range over which the gain remains almost constant. This is the use-ful frequency range of operation for the particular amplifier. Thus far, we have been assum-ing that our amplifiers are operating in this band, called the middle-frequency band or midband. The amplifier is designed so that its midband coincides with the frequency spec-trum of the signals it is required to amplify. If this were not the case, the amplifier would distort the frequency spectrum of the input signal, with different components of the input signal being amplified by different amounts.
π 688 Chapter 9 Frequency Response Figure 9.1 indicates that at lower frequencies, the magnitude of the amplifier gain falls off. This occurs because the coupling and bypass capacitors no longer have low impedances.
Recall that we assumed that their impedances were small enough to act as short circuits.
Although this can be true at midband frequencies, as the frequency of the input signal is lowered, the reactance 1/jωC of each of these capacitors becomes significant and, as will be shown in Section 9.1, this results in a decrease in the overall voltage gain of the amplifier.
In the analysis of the low-frequency response of discrete-circuit amplifiers in Section 9.1 we will be particularly interested in the determination of the frequency fL, which defines the lower end of the midband. It is usually defined as the frequency at which the gain drops by 3 dB below its value in midband. Integrated-circuit amplifiers do not utilize coupling and bypass capacitors, and thus their midband extends down to zero frequency (dc).
Figure 9.1 indicates also that the gain of the amplifier falls off at the high-frequency end.
This is due to internal capacitive effects in the BJT and in the MOSFET. We shall study these effects in Section 9.2 and model them with capacitances that we will add to the hybrid-π model of the BJT and the MOSFET. The resulting high-frequency device models will be utilized in Section 9.3 in the analysis of the high-frequency response of the CS and CE amplifiers, both discrete and integrated. We will be specifically interested in the determination of the frequency fH, which defines the upper end of the midband. It is defined as the frequency at which the gain drops by 3 dB below its midband value. Thus, the amplifier bandwidth is defined by fL and fH (0 and fH for IC amplifiers).
The remainder of this chapter will be concerned with the frequency response analysis of a variety of amplifier configurations of varying degrees of complexity. Of particular interest to us are ways to extend the amplifier bandwidth (i.e., increase fH) either by adding specific cir-cuit components, such as source and emitter degeneration resistances, or by changing the cir-cuit configuration altogether.
Before embarking on the study of this chapter, the reader is urged to review Section 1.6, which introduces the subject of amplifier frequency response and the extremely important topic of single-time-constant (STC) circuits. More details on STC circuits can be found in Figure 9.1 Sketch of the magnitude of the gain of a discrete-circuit BJT or MOS amplifier versus fre-quency. The graph delineates the three frequency bands relevant to frequency-response determination.
fL fH f (Hz) (log scale) (dB) V o V sig Low-frequency band Midband • Gain falls off due to the effects of coupling and bypass capacitors High-frequency band • Gain falls off due to the internal capacitive effects of the BJT or the MOSFET • All capacitances can be neglected 3 dB 20 log AM (dB) 9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 689 Appendix E. As well, Appendix F provides a review of important tools from circuit and sys-tem theory: poles, zeros, and Bode plots.
9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 9.1.1 The CS Amplifier Figure 9.2(a) shows a discrete-circuit, common-source amplifier utilizing coupling capaci-tors and and bypass capacitor CS. We wish to determine the effect of these capaci-tances on the gain of the amplifier. As mentioned before, at midband frequencies, these capacitances have negligibly small impedances and can be assumed to be perfect short circuits for the purpose of calculating the midband gain. At low frequencies, however, the reactance 1/jωC of each of the three capacitances increases and the amplifier gain decreases, as we shall now show.
Determining Vo/Vsig To determine the low-frequency gain or transfer function of the common-source amplifier, we show in Fig. 9.2(b) the circuit with the dc sources eliminated (current source I open-circuited and voltage source VDD short-circuited). We shall perform the small-signal analysis directly on this circuit. However, we will ignore ro. This is done in order to keep the analysis simple and thus focus attention on significant issues. The effect of ro on the low-frequency operation of this amplifier is minor, as can be verified by a SPICE simulation. To determine the gain Vo/Vsig, we start at the signal source and work our way through the circuit, determining Vg, Id, Io, and Vo, in this order.1 To find the fraction of Vsig that appears at the transistor gate, Vg, we use the voltage divider rule at the input to write which can be written in the alternate form (9.1) Thus we see that the expression for the signal transmission from signal generator to ampli-fier input has acquired a frequency-dependent factor. From our study of frequency response in Section 1.6 (see also Appendix E), we recognize this factor as the transfer function of an STC circuit of the high-pass type with a break or corner frequency Thus the effect of the coupling capacitor CC1 is to introduce a high-pass STC response with a 1Note that since we are now dealing with quantities that are functions of frequency, or, equivalently, the Laplace variable s, we are using capital letters with lowercase subscripts for our symbols. This conforms with the symbol notation introduced in Chapter 1. CC1 CC2, Vo Vsig ⁄ Vg Vsig RG RG 1 sCC1 -----------Rsig + + ---------------------------------------= Vg Vsig RG RG Rsig + ---------------------s s 1 CC1 RG Rsig + ( ) -----------------------------------+ ---------------------------------------------= ω0 = 1 CC1 RG Rsig + ( ).
⁄ 690 Chapter 9 Frequency Response break frequency that we shall denote ωP1, (9.2) Continuing with the analysis, we next determine the drain current Id by dividing Vg by the total impedance in the source circuit, which is to obtain Figure 9.2 (a) Capacitively coupled common-source amplifier. (b) Analysis of the CS amplifier to deter-mine its low-frequency transfer function. For simplicity, ro is neglected.
(a) VSS VDD CC1 CS Rsig Vsig Vo RL CC2 I RG RD (b) Vsig RG RD Rsig CC1 CC2 CS Vg Vo Id RL Id Io 1 gm ωP1 ω0 1 CC1 RG Rsig + ( ) -----------------------------------= = 1 gm ⁄ ( ) 1 sCS ⁄ ( ) + [ ] 9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 691 which can be written in the alternate form (9.3) We observe that CS introduces a frequency-dependent factor, which is also of the STC high-pass type. Thus the amplifier acquires another break frequency, (9.4) To complete the analysis, we find Vo by first using the current divider rule to determine the fraction of Id that flows through RL, and then multiplying Io by RL to obtain (9.5) from which we see that CC2 introduces a third STC high-pass factor, giving the amplifier a third break frequency at (9.6) The overall low-frequency transfer function of the amplifier can be found by combining Eqs. (9.1), (9.3), and (9.5) and replacing the break frequencies by their symbols from Eqs.
(9.2), (9.4), and (9.6): (9.7) which can be expressed in the form (9.8) where the midband gain, is given by Id Vg 1 gm -----1 sCS --------+ ---------------------= Id gmVg s s gm CS ------+ --------------= ωP2 gm CS ------= Io Id – RD RD 1 sCC2 -----------RL + + ------------------------------------= Vo IoRL I – d RDRL RD RL + ------------------ s s 1 CC2 RD RL + ( ) --------------------------------+ -----------------------------------------= = ωP3 1 CC2 RD RL + ( ) --------------------------------= Vo Vsig --------RG RG Rsig + ---------------------⎝ ⎠ ⎛ ⎞gm RD RL || ( ) [ ] s s ωP1 + -----------------⎝ ⎠ ⎛ ⎞ s s ωP2 + -----------------⎝ ⎠ ⎛ ⎞ s s ωP3 + -----------------⎝ ⎠ ⎛ ⎞ – = Vo Vsig --------AM s s ωP1 + -----------------⎝ ⎠ ⎛ ⎞ s s ωP2 + -----------------⎝ ⎠ ⎛ ⎞ s s ωP3 + -----------------⎝ ⎠ ⎛ ⎞ = AM, 692 Chapter 9 Frequency Response (9.9) which is the value we would have obtained, had we assumed that and were acting as perfect short circuits. In this regard, note that at midband frequencies—that is, at frequencies much higher than and —Eq. (9.8) shows that approaches , as should be the case.
Determining the Lower 3-dB Frequency, fL The magnitude of the amplifier gain, at frequency can be obtained by substituting in Eq. (9.8) and evaluating the magnitude of the transfer function. In this way, the frequency response of the amplifier can be plotted versus frequency, and the lower 3-dB frequency fL can be determined as the frequency at which drops to . A simpler approach, however, is possible if the break frequencies and are sufficiently separated. In this case, we can employ the Bode plot rules (see Appendix F) to sketch a Bode plot for the gain magnitude.
Such a plot is shown in Fig. 9.3. Observe that since the break frequencies are sufficiently separated, their effects appear distinct. At each break frequency, the slope of the asymptote to the gain function increases by 20 dB/decade. Readers familiar with poles and zeros will recognize fP1, fP2, and fP3 as the frequencies of the three real-axis, low-frequency poles of the amplifier. (For a brief review of poles and zeros, refer to Appendix F.) Figure 9.3 Sketch of the low-frequency magnitude response of a CS amplifier for which the three pole fre-quencies are sufficiently separated for their effects to appear distinct.
AM RG RG Rsig + ---------------------– gm RD RL || ( ) [ ] = CC1, CC2, CS s jω = ωP1, ωP2, ωP3 Vo Vsig ⁄ AM – Vo Vsig ⁄ ω s jω = Vo Vsig ⁄ AM 2 ⁄ ωP1, ωP2, ωP3 Vo Vsig (dB) f (Hz) (log scale) 20 dBdecade 3 dB fL 20 log AM 40 dBdecade 60 dBdecade 0 fP1 fP3 fP2 9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 693 A quick way for estimating the 3-dB frequency fL is possible if the highest-frequency pole (here, fP2) is separated from the nearest pole (here, fP3) by at least a factor of 4 (two octaves). In such a case, fL is approximately equal to the highest of the pole frequencies, Usually, the highest-frequency pole is the one caused by This is because interacts with which is relatively low (see Eq. 9.4).
Determining the Pole Frequencies by Inspection Before leaving this section, we present a simple method for finding the time constant and hence the pole frequency associ-ated with each of the three capacitors. The procedure is simple: 1. Reduce Vsig to zero.
2. Consider each capacitor separately; that is, assume that the other two capacitors are acting as perfect short circuits.
3. For each capacitor, find the total resistance seen between its terminals. This is the resistance that determines the time constant associated with this capacitor.
The reader is encouraged to apply this procedure to CC1, CS, and CC2 and thus see that Eqs. (9.2), (9.4), and (9.6) can be written by inspection.
Selecting Values for the Coupling and Bypass Capacitors We now address the design issue of selecting appropriate values for CC1, CS, and CC2. The design objective is to place the lower 3-dB frequency fL at a specified value while minimizing the capacitor values. Since as mentioned above CS results in the highest of the three pole frequencies, the total capacitance is minimized by selecting CS so that its pole frequency fP2 = fL. We then decide on the loca-tion of the other two pole frequencies, say 5 to 10 times lower than the frequency of the domi-nant pole, fP2. However, the values selected for fP1 and fP3 should not be too low, for that would require larger values for CC1 and CC2 than may be necessary. The design procedure will be illustrated by an example.
fL fP2 CS.
CS 1 gm, ⁄ We wish to select appropriate values for the coupling capacitors CC1 and CC2 and the bypass capaci-tor CS for a CS amplifier for which RG = 4.7 MΩ, RD = RL = 15 kΩ, Rsig = 100 kΩ, and gm = 1 mA/V.
It is required to have fL at 100 Hz and that the nearest break frequency be at least a decade lower.
Solution We select CS so that Thus, For fP1 = fP3 = 10 Hz, we obtain fP2 1 2π CS gm ⁄ ( ) ----------------------------fL = = CS gm 2πfL -----------1 10 3 – × 2π × 100 --------------------------1.6 μF = = = 10 1 2πCC1 0.1 4.7 + ( ) 106 × ---------------------------------------------------------= Example 9.1 694 Chapter 9 Frequency Response 9.1.2 The CE Amplifier Figure 9.4 shows a common-emitter amplifier that utilizes coupling capacitors and and emitter bypass capacitor . As in the case of the MOS amplifier, the effect of these capacitors is felt only at low frequencies. Our objective is to determine the amplifier gain or transfer function with these three capacitances taken into account. Toward that end, we show in Fig. 9.4(b) the circuit with the dc sources eliminated. We shall perform the small-signal analysis directly on the circuit. To keep the analysis simple, we shall neglect the effect of , as we have done in the MOS case.
The analysis of the circuit in Fig. 9.4(b) is somewhat more complicated than that for the CS case. This is a result of the finite β of the BJT, which causes the input impedance at the base to be a function of . Thus the effects of and are no longer separable.
Although one can certainly still derive an expression for the overall transfer function, the result will be quite complicated, making it difficult to obtain design insight. Therefore we shall pursue an approximate alternative approach.
Considering the Effect of Each of the Three Capacitors Separately Our first cut at the analysis of the circuit in Fig. 9.4(b) is to consider the effect of the three capacitors CC1, CE, and CC2 one at a time. That is, when finding the effect of CC1, we shall assume that CE and CC2 are acting as perfect short circuits, and when considering CE, we assume that CC1 and CC2 are perfect short circuits, and so on. This is obviously a major simplifying assump-tion—and one that might not be justified. However, it should serve as a first cut at the anal-ysis, enabling us to gain insight into the effect of these capacitances.
Figure 9.5(a) shows the circuit with CE and CC2 replaced with short circuits. The voltage Vπ at the base of the transistor can be written as CC1 CC2 CE Vo Vsig ⁄ ro CE CC1 CE V π V sig RB rπ || RB rπ || ( ) Rsig 1 sCC1 -----------+ + -----------------------------------------------------= 9.1 A CS amplifier has CC1 = CS = CC2 = 1 μF, RG = 10 MΩ, Rsig = 100 kΩ, gm = 2 mA/V, RD = RL = 10 kΩ.
Find AM, fP1, fP2, fP3, and fL.
Ans. –9.9 V/V; 0.016 Hz; 318.3 Hz; 8 Hz; 318.3 Hz EXERCISE Example 9.1 continued which yields and which results in CC1 3.3 nF = 10 1 2πCC2 15 15 + ( ) 103 × ------------------------------------------------------= CC2 0.53 μF = 9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 695 and the output voltage is obtained as These two equations can be combined to obtain the voltage gain including the effect of CC1 as (9.10) Figure 9.4 (a) A capacitively coupled common-emitter amplifier. (b) The circuit prepared for small-signal analysis.
(a) VEE VCC CC1 CE Rsig Vsig Vo RL CC2 I RB RC (b) CC1 CE Rsig Vsig Vo RL CC2 RB RC V o Vo gmVπ RC RL || ( ) – = Vo Vsig ⁄ Vo Vsig --------RB rπ || ( ) RB rπ || ( ) Rsig + -----------------------------------gm RC RL || ( ) s s 1 CC1 RB rπ || ( ) Rsig + [ ] -------------------------------------------------+ ----------------------------------------------------------– = 696 Chapter 9 Frequency Response from which we observe that the effect of CC1 is to introduce the frequency-dependent fac-tor between the square brackets on the right-hand side of Eq. (9.10). We recognize this factor as the transfer fraction of a single-time-constant (STC) circuit of the high-pass type (see Section 1.6 and Appendix E) with a corner (or break or pole) frequency ωP1, (9.11) Note that is the resistance seen between the terminals of CC1 when Vsig is set to zero. The STC high-pass factor introduced by CC1 will cause the amplifier gain to roll off at low frequencies at the rate of 6 dB/octave (20 dB/decade) with a 3-dB frequency at , as indicated in Fig. 9.5(a). Also note that we have denoted the midband gain AM, (9.12) Next, we consider the effect of CE. For this purpose we assume that CC1 and CC2 are acting as perfect short circuits and thus obtain the circuit in Fig. 9.5(b). Reflecting re and CE into the base circuit and utilizing the Thévenin theorem enables us to obtain the base current as The collector current can then be found as βIb and the output voltage as Thus the voltage gain including the effect of CE can be expressed as2 (9.13) We observe that CE introduces the STC high-pass factor on the extreme right-hand side.
Thus CE causes the gain to fall off at low frequency at the rate of 6 dB/octave with a 3-dB frequency equal to the corner (or pole) frequency of the high-pass STC function; that is, (9.14) Observe that is the resistance seen between the two terminals of CE when Vsig is set to zero. The effect of CE on the amplifier frequency response is illus-trated by the sketch in Fig. 9.5(b).
2 It can be shown that the factor multiplying the high-pass transfer function in Eq. (9.13) is equal to AM of Eq. (9.12).
ωP1 1 CC1 RB rπ || ( ) Rsig + [ ] -------------------------------------------------= RB rπ || ( ) Rsig + [ ] fP1 ωP1 2π ⁄ = AM RB rπ || ( ) RB rπ || ( ) Rsig + -----------------------------------gm RC RL || ( ) – = Ib Vsig RB RB Rsig + --------------------1 RB Rsig || ( ) β 1 + ( ) re 1 sCE ---------+ ⎝ ⎠ ⎛ ⎞ + --------------------------------------------------------------------------= Vo βIb RC RL || ( ) – = = RB RB Rsig + --------------------– β RC RL || ( ) RB Rsig || ( ) β 1 + ( ) re 1 sCE ---------+ ⎝ ⎠ ⎛ ⎞ + --------------------------------------------------------------------------Vsig Vo Vsig --------RB RB Rsig + --------------------– = β RC RL || ( ) RB Rsig || ( ) β 1 + ( )re + ----------------------------------------------------s s 1 CE re RB Rsig || β 1 + -------------------+ ⎝ ⎠ ⎛ ⎞ ⁄ + ---------------------------------------------------------------ωP2 1 CE re RB Rsig || β 1 + -------------------+ ------------------------------------------= re ((RB Rsig)/ β 1 + ( )) || + [ ] 9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 697 Finally, we consider the effect of CC2. The circuit with CC1 and CE assumed to be acting as perfect short circuits is shown in Fig. 9.5(c), for which we can write and Figure 9.5 Analysis of the low-frequency response of the CE amplifier of Fig. 9.4: (a) the effect of CC1 is determined with CE and CC2 assumed to be acting as perfect short circuits; (b) the effect of CE is determined with CC1 and CC2 assumed to be acting as perfect short circuits; (a) CC1 Rsig Vsig Vo RL RB RC V p rp gmVp fP1 f (Hz, log scale) (dB) V o V sig 3 dB 6 dBoctave 20 dBdecade 20 log AM fP1 12p CC1 [(RBrp) Rsig] (b) Rsig Vsig Vo RL RB CE RC bIb fP2 f (Hz, log scale) (dB) V o V sig 3 dB 6 dBoctave 20 dBdecade 20 log AM fP2 12pCE re RBRsig b 1 Ib (b 1) re 1 sCE Vπ Vsig RB rπ || RB rπ || ( ) Rsig + -----------------------------------= Vo gmVπ RC RC 1 sCC2 -----------RL + + ------------------------------------RL – = 698 Chapter 9 Frequency Response These two equations can be combined to obtain the low-frequency gain including the effect of CC2 as (9.15) We observe that CC2 introduces the frequency-dependent factor between the square brack-ets, which we recognize as the transfer function of a high-pass STC circuit with a pole fre-quency ωP3, (9.16) Figure 9.5 (continued) (c) the effect of CC2 is determined with CC1 and CE assumed to be acting as perfect short circuits; (d) sketch of the low-frequency gain under the assumptions that CC1, CE, and CC2 do not inter-act and that their break (or pole) frequencies are widely separated.
(d) fP3 fP1 fP2 f (Hz, log scale) (dB) V o V sig 3 dB, fL fP2 6 dB/octave 12 dB/octave 18 dB/octave 20 log AM (c) fP3 f (Hz, log scale) (dB) V o V sig 3 dB 6 dBoctave 20 dBdecade 20 log AM fP3 12p CC2 (RC RL) Rsig Vsig Vo RL RB RC V p rp gmVp CC2 Vo Vsig --------RB rπ || RB rπ || ( ) Rsig + -----------------------------------gm RC RL || ( ) s s 1 CC2 RC RL + ( ) --------------------------------+ -----------------------------------------– = ωP3 1 CC2 RC RL + ( ) --------------------------------= 9.1 Low-Frequency Response of the Common-Source and Common-Emitter Amplifiers 699 Here we note that as expected, (RC + RL) is the resistance seen between the terminals of CC2 when Vsig is set to zero. Thus capacitor CC2 causes the low-frequency gain of the amplifier to decrease at the rate of 6 dB/octave with a 3-dB frequency at as illustrated by the sketch in Fig. 9.5(c).
Determining the Lower 3-dB Frequency, fL Now that we have determined the effects of each of CC1, CE, and CC2 acting alone, the question becomes what will happen when all three are present at the same time. This question has two parts: First, what happens when all three capacitors are present but do not interact? The answer is that the amplifier low-frequency gain can be expressed as (9.17) from which we see that it acquires three poles with frequencies fP1, fP2, and fP3, all in the low-frequency band. If the three frequencies are widely separated, their effects will be distinct, as indicated by the sketch in Fig. 9.5(d). The important point to note here is that the 3-dB frequency fL is determined by the highest of the three pole frequencies. This is usually the pole caused by the bypass capacitor CE, simply because the resistance that it sees is usually quite small. Thus, even if one uses a large value for CE, fP2 is usually the highest of the three pole frequencies.
If fP1, fP2, and fP3 are close together, none of the three dominates, and to determine fL, we have to evaluate in Eq. (9.17) and calculate the frequency at which it drops to The work involved in doing this, however, is usually too great and is rarely justi-fied in practice, particularly because in any case, Eq. (9.17) is an approximation based on the assumption that the three capacitors do not interact. This leads to the second part of the question: What happens when all three capacitors are present and interact? We do know that CC1 and CE usually interact and that their combined effect is two poles at frequencies that will differ somewhat from ωP1 and ωP2. Of course, one can derive the overall transfer func-tion taking this interaction into account and find more precisely the low-frequency response.
This, however, will be too complicated to yield additional insight. As an alternative, for hand calculations, we can obtain a reasonably good estimate for fL using the following formula (which we will not derive here)3: (9.18) or equivalently, (9.19) where RC1, RE, and RC2 are the resistances seen by CC1, CE, and CC2, respectively, when Vsig is set to zero and the other two capacitances are replaced with short circuits. Equations (9.18) and (9.19) provide insight regarding the relative contributions of the three capacitors to fL. Finally, we note that a far more precise determination of the low-frequency gain and the 3-dB fre-quency fL can be obtained using SPICE.
Selecting Values for CC1, CE, and CC2 We now address the design issue of selecting appropriate values for CC1, CE, and CC2. The design objective is to place the lower 3-dB fre-quency fL at a specified location while minimizing the capacitor values. Since, as mentioned above, CE usually sees the lowest of the three resistances, the total capacitance is minimized 3 The interested reader can refer to Appendix F.
fP3 ωP3 2π ⁄ , = Vo Vsig --------AM s s ωP1 + -----------------⎝ ⎠ ⎛ ⎞ s s ωP2 + -----------------⎝ ⎠ ⎛ ⎞ s s ωP3 + -----------------⎝ ⎠ ⎛ ⎞ – = Vo Vsig ⁄ AM 2 ⁄ .
fL 1 2π ------1 CC1RC1 -----------------1 CERE -------------1 CC2RC2 -----------------+ + fL f P1 f P2 f P3 + + = 700 Chapter 9 Frequency Response by selecting CE so that its contribution to fL is dominant. That is, by reference to Eq. (9.18), we may select CE such that is, say, 80% of ωL = 2π fL, leaving each of the other capacitors to contribute 10% to the value of ωL. Example 9.2 should help to illustrate this process.
EXAMPLE 9.2 1 CERE ( ) ⁄ We wish to select appropriate values for CC1, CC2, and CE for the common-emitter amplifier, which has RB = 100 kΩ, RC = 8 kΩ, RL = 5 kΩ, Rsig = 5 kΩ, β = 100, gm = 40 mA/V, and rπ = 2.5 kΩ. It is required to have fL = 100 Hz.
Solution We first determine the resistances seen by the three capacitors CC1, CE, and CC2 as follows: Now, selecting CE so that it contributes 80% of the value of ωL gives Next, if CC1 is to contribute 10% of fL, Similarly, if CC2 is to contribute 10% of fL, its value should be selected as follows: In practice, we would select the nearest standard values for the three capacitors while ensuring that fL ≤ 100 Hz.
RC1 RB rπ || ( ) Rsig + = 100 2.5 || ( ) 5 + = 7.44 kΩ = RE re RB Rsig || β 1 + --------------------+ = 0.025 100 5 || 101 -----------------+ = 0.072 kΩ 72 Ω = = RC2 RC RL + 8 5 + 13 kΩ = = = 1 CE 72 × -------------------0.8 2π 100 × × = CE 27.6 μF = 1 CC1 7.44 103 × × ----------------------------------------0.1 2π 100 × × = CC1 2.1 μF = 1 CC2 13 103 × × ------------------------------------0.1 2π 100 × × = CC2 1.2 μF = Example 9.2 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 701 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT While coupling and bypass capacitors cause the gain of transistor amplifiers to fall off at the low-frequency end, the gain falloff at high frequencies is caused by the capacitive effects internal to the transistors. In this section we shall briefly consider these effects and, more importantly, show how the device small-signal model can be augmented to take these effects into account.
9.2.1 The MOSFET From our study of the physical operation of the MOSFET in Section 5.1, we know that the device has internal capacitances. In fact, we used one of these, the gate-to-channel capacitance, in our derivation of the MOSFET characteristics. We did, however, implicitly assume that the steady-state charges on these capacitances are acquired instantaneously. In other words, we did not account for the finite time required to charge and discharge the various internal capac-itances. As a result, the device models we derived, such as the small-signal model, do not include any capacitances. The use of these models would predict constant amplifier gains independent of frequency. We know, however, that this (unfortunately) does not happen; in fact, the gain of every MOSFET amplifier falls off at some high frequency. Similarly, the MOSFET digital logic inverter (Chapter 13) exhibits a finite nonzero propagation delay. To be able to predict these results, the MOSFET model must be augmented by including inter-nal capacitances. This is the subject of this section.
To visualize the physical origin of the various internal capacitances, the reader is referred to Fig. 5.1. There are basically two types of internal capacitance in the MOSFET.
1. The gate capacitive effect: The gate electrode (polysilicon) forms a parallel-plate capacitor with the channel, with the oxide layer serving as the capacitor dielectric.
We discussed the gate (or oxide) capacitance in Section 5.1 and denoted its value per unit area as 2. The source-body and drain-body depletion-layer capacitances: These are the capac-itances of the reverse-biased pn junctions formed by the n+ source region (also called the source diffusion) and the p-type substrate and by the n+ drain region (the drain diffusion) and the substrate. Evaluation of these capacitances will utilize the material studied in Chapter 3.
These two capacitive effects can be modeled by including capacitances in the MOSFET model between its four terminals, G, D, S, and B. There will be five capacitances in total: i v – Cox.
9.2 A common-emitter amplifier has CC1 = CE = CC2 = 1 μF, RB = 100 kΩ, Rsig = 5 kΩ, gm = 40 mA/V, rπ = 2.5 kΩ, RC = 8 kΩ, and RL = 5 kΩ. Assuming that the three capacitors do not interact, find fP1, fP2, and fP3, and hence estimate fL.
Ans. 21.4 Hz; 2.21 kHz; 12.2 Hz; since fP2 fP1 and fP3, fL fP2 = 2.21 kHz; using Eq. (9.19), a some-what better estimate for fL is obtained: 2.24 kHz EXERCISE 702 Chapter 9 Frequency Response Cgs, Cgd, Cgb, Csb, and Cdb, where the subscripts indicate the location of the capacitances in the model. In the following, we show how the values of the five model capacitances can be determined. We will do so by considering each of the two capacitive effects separately.
The Gate Capacitive Effect The gate capacitive effect can be modeled by the three capacitances Cgs, Cgd, and Cgb. The values of these capacitances can be determined as follows: 1. When the MOSFET is operating in the triode region at small vDS, the channel will be of uniform depth. The gate-channel capacitance will be WL Cox and can be modeled by dividing it equally between the source and drain ends; thus, (9.20) This is obviously an approximation (as all modeling is), but it works well for triode-region operation even when vDS is not small.
2. When the MOSFET operates in saturation, the channel has a tapered shape and is pinched off at or near the drain end. It can be shown that the gate-to-channel capac-itance in this case is approximately and can be modeled by assigning this entire amount to Cgs, and a zero amount to Cgd (because the channel is pinched off at the drain); thus, (9.21) (9.22) 3. When the MOSFET is cut off, the channel disappears, and thus Cgs = Cgd = 0. How-ever, we can (after some rather complex reasoning) model the gate capacitive effect by assigning a capacitance WL Cox to the gate-body model capacitance; thus, (9.23) (9.24) 4. There is an additional small capacitive component that should be added to Cgs and Cgd in all the preceding formulas. This is the capacitance that results from the fact that the source and drain diffusions extend slightly under the gate oxide (refer to Fig. 5.1). If the overlap length is denoted Lov, we see that the overlap capacitance component is (9.25) Typically, Lov = 0.05 to 0.1 L.
The Junction Capacitances The depletion-layer capacitances of the two reverse-biased pn junctions formed between each of the source and the drain diffusions and the body can be determined using the formula developed in Section 3.6 (Eq. 3.47). Thus, for the source diffu-sion, we have the source-body capacitance, Csb, (9.26) Cgs Cgd 1 2 ---WL Cox triode region ( ) = = 2 3 ---WL Cox Cgs = 2 3 ---WL Cox Cgd = 0 ⎭ ⎬ ⎫ (saturation region) Cgs = Cgd 0 = Cgb WL Cox = ⎭ ⎬ ⎫ (cutoff) Cov WLov Cox = Csb Csb0 1 VSB V0 --------+ ----------------------= 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 703 where Csb0 is the value of Csb at zero body-source bias, VSB is the magnitude of the reverse-bias voltage, and V0 is the junction built-in voltage (0.6 V to 0.8 V). Similarly, for the drain diffusion, we have the drain-body capacitance Cdb, (9.27) where Cdb0 is the capacitance value at zero reverse-bias voltage, and VDB is the magnitude of this reverse-bias voltage. Note that we have assumed that for both junctions, the grading coefficient .
It should be noted also that each of these junction capacitances includes a component arising from the bottom side of the diffusion and a component arising from the side walls of the diffusion. In this regard, observe that each diffusion has three side walls that are in con-tact with the substrate and thus contribute to the junction capacitance (the fourth wall is in contact with the channel). In more advanced MOSFET modeling, the two components of each of the junction capacitances are calculated separately.
The formulas for the junction capacitances in Eqs. (9.26) and (9.27) assume small-signal operation. These formulas, however, can be modified to obtain approximate average values for the capacitances when the transistor is operating under large-signal conditions such as in logic circuits. Finally, typical values for the various capacitances exhibited by an n-channel MOSFET in a 0.5-μm CMOS process are given in the following exercise. The High-Frequency MOSFET Model Figure 9.6(a) shows the small-signal model of the MOSFET, including the four capacitances Cgs, Cgd, Csb, and Cdb. This model can be used to predict the high-frequency response of MOSFET amplifiers. It is, however, quite com-plex for manual analysis, and its use is limited to computer simulation using, for example, SPICE. Fortunately, when the source is connected to the body, the model simplifies consid-erably, as shown in Fig. 9.6(b). In this model, Cgd, although small, plays a significant role in determining the high-frequency response of amplifiers and thus must be kept in the model.
Capacitance Cdb, on the other hand, can usually be neglected, resulting in significant simpli-fication of manual analysis. The resulting circuit is shown in Fig. 9.6(c). The MOSFET Unity-Gain Frequency (fT) A figure of merit for the high-frequency opera-tion of the MOSFET as an amplifier is the unity-gain frequency, fT, also known as the transi-tion frequency, which gives rise to the subscript T. This is defined as the frequency at which the short-circuit current-gain of the common-source configuration becomes unity. Figure 9.7 Cdb Cdb0 1 VDB V0 ---------+ ----------------------= m = 1 2 ---9.3 For an n-channel MOSFET with tox = 10 nm, L = 1.0 μm, W = 10 μm, Lov = 0.05 μm, Csb0 = Cdb0 = 10 fF, V0 = 0.6 V, , calculate the following capacitances when the tran-sistor is operating in saturation: Cox, Cov, Cgs, Cgd, Csb, and Cdb. Ans. 3.45 fF/μm2; 1.72 fF; 24.7 fF; 1.72 fF; 6.1 fF; 4.1 fF VSB 1 V, and VDS 2 V = = EXERCISE 704 Chapter 9 Frequency Response shows the MOSFET hybrid-π model with the source as the common terminal between the input and output ports. To determine the short-circuit current gain, the input is fed with a current-source signal Ii and the output terminals are short-circuited. It can be seen that the current in the short circuit is given by Figure 9.6 (a) High-frequency, equivalent-circuit model for the MOSFET. (b) The equivalent circuit for the case in which the source is connected to the substrate (body). (c) The equivalent-circuit model of (b) with Cdb neglected (to simplify analysis).
(a) V bs Csb S B Cdb V bs Cgd Cgs gmb ro G D V gs V gs gm (b) Cdb V gs Cgd Cgs gm ro G D V gs S (c) V gs V gs Cgd Cgs gm ro G D S Io gmVgs sCgdVgs – = 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 705 Recalling that Cgd is small, at the frequencies of interest the second term in this equation can be neglected, (9.28) From Fig. 9.7, we can express Vgs in terms of the input current Ii as (9.29) Equations (9.28) and (9.29) can be combined to obtain the short-circuit current gain, (9.30) For physical frequencies s = jω, it can be seen that the magnitude of the current gain becomes unity at the frequency Thus the unity-gain frequency fT = ωT /2π is (9.31) Since fT is proportional to gm and inversely proportional to the MOSFET internal capaci-tances, the higher the value of fT, the more effective the MOSFET becomes as an amplifier.
Substituting for gm using Eq. (5.56), we can express fT in terms of the bias current ID (see Problem 9.18). Alternatively, we can substitute for gm from Eq. (5.55) to express fT in terms of the overdrive voltage VOV (see Problem 9.19). Both expressions yield additional insight into the high-frequency operation of the MOSFET. The reader is also referred to Chapter 7, Appendix 7.A for a further discussion of fT .
Typically, fT ranges from about 100 MHz for the older technologies (e.g., a 5-μm CMOS process) to many GHz for newer high-speed technologies (e.g., a 0.13-μm CMOS process).
Figure 9.7 Determining the short-circuit current gain .
Ii V gs V gs Cgd sCgd Vgs Cgs gm ro Io Io Ii ⁄ Io gmVgs Vgs Ii s ⁄ Cgs Cgd + ( ) = Io Ii ----gm s Cgs Cgd + ( ) -----------------------------= ωT gm Cgs Cgd + ( ) ⁄ = fT gm 2π Cgs Cgd + ( ) ----------------------------------= 9.4 Calculate fT for the n-channel MOSFET whose capacitances were found in Exercise 9.3. Assume op-eration at 100 μA, and that μA/V2.
Ans. 3.7 GHz.
kn ′ = 160 EXERCISE 706 Chapter 9 Frequency Response Summary We conclude this section by presenting a summary in Table 9.1.
9.2.2 The BJT In our study of the physical operation of the BJT in Section 6.1, we assumed transistor action to be instantaneous, and as a result the transistor models we developed do not include any elements (i.e., capacitors or inductors) that would cause time or frequency dependence.
Actual transistors, however, exhibit charge-storage phenomena that limit the speed and fre-quency of their operation. We have already encountered such effects in our study of the pn junction in Chapter 3, and learned that they can be modeled using capacitances. In the fol-lowing we study the charge-storage effects that take place in the BJT and take them into account by adding capacitances to the hybrid-π model. The resulting augmented BJT model will be able to predict the observed dependence of amplifier gain on frequency, and the time delays that transistor switches and logic gates exhibit.
Table 9.1 The MOSFET High-Frequency Model Model Model Parameters ro Cgs D Csb Cdb Cgd gmVgs gmbVbs G S B Vgs Vbs gm μnCox W L ----- VOV 2μnCox W L -----ID 2ID VOV -----------------= = = gmb χgm χ , 0.1 to 0.2 = = ro VA ID ⁄ = Cgs 2 3 --WLCox WLovCox + = Cgd WLovCox = Csb Csb0 1 VSB V0 ----------+ -----------------------= Cdb Cdb0 1 VDB V0 ----------+ -----------------------= fT gm 2π Cgs Cgd + ( ) ------------------------------= 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 707 The Base-Charging or Diffusion Capacitance Cde When the transistor is operating in the active mode, minority carrier charge is stored in the base region. For an npn tran-sistor, the stored electron charge in the base, Qn, can be expressed in terms of the collec-tor current iC as (9.32) where τF is a device constant with the dimension of time. It is known as the forward base-transit time and represents the average time a charge carrier (electron) spends in crossing the base. Typically, τF is in the range of 10 ps to 100 ps. Equation (9.32) applies for large signals and, since iC is exponentially related to vBE, Qn will similarly depend on vBE. Thus this charge-storage mechanism represents a nonlinear capacitive effect. However, for small signals we can define the small-signal diffusion capacitance Cde, (9.33) resulting in (9.34) Thus, whenever vBE changes by vbe, the collector current changes by gmvbe and the charge stored in the base changes by Cde vbe = (τF gm) vbe. The Base–Emitter Junction Capacitance Cje A change in not only changes the charge stored in the base region but also the charge stored in the base–emitter depletion layer. This distinct charge-storage effect is represented by the EBJ depletion-layer capaci-tance, . From the development in Chapter 3, we know that for a forward-biased junction, which the EBJ is, the depletion-layer capacitance is given approximately by (9.35) where is the value of at zero EBJ voltage.
The Collector–Base Junction Capacitance Cμ In active-mode operation, the CBJ is reverse biased, and its junction or depletion capacitance, usually denoted Cμ, can be found from (9.36) where Cμ0 is the value of Cμ at zero voltage; VCB is the magnitude of the CBJ reverse-bias voltage, V0c is the CBJ built-in voltage (typically, 0.75 V), and m is its grading coefficient (typically, 0.2–0.5). The High-Frequency Hybrid-π Model Figure 9.8 shows the hybrid-π model of the BJT, including capacitive effects. Specifically, there are two capacitances: the emitter–base capacitance Cπ = Cde + Cje and the collector–base capacitance Cμ . Typically, Cπ is in the Qn τFiC = Cde dQn dvBE -----------≡ τF diC dvBE -----------= Cde τFgm τF IC VT ------= = vBE Cje Cje 2Cje0 Cje0 Cje Cμ Cμ0 1 VCB V0c --------+ ⎝ ⎠ ⎛ ⎞ m --------------------------= 708 Chapter 9 Frequency Response range of a few picofarads to a few tens of picofarads, and Cμ is in the range of a fraction of a picofarad to a few picofarads.4 Note that we have also added a resistor rx to model the resis-tance of the silicon material of the base region between the base terminal B and a fictitious internal, or intrinsic, base terminal that is right under the emitter region (refer to Fig.
6.6). Typically, rx is a few tens of ohms, and its value depends on the current level in a rather complicated manner. Since (usually) rx rπ, its effect is negligible at low frequencies. Its presence is felt, however, at high frequencies, as will become apparent later.
The values of the hybrid-π, equivalent-circuit parameters can be determined at a given bias point using the formulas presented in this section and in Chapter 6. They can also be found from the terminal measurements specified on the BJT data sheets. For computer sim-ulation, SPICE uses the parameters of the given IC technology to evaluate the BJT model parameters (see Appendix B).
The Cutoff Frequency The transistor data sheets do not usually specify the value of Cπ.
Rather, the behavior of β (or hfe) versus frequency is normally given. In order to determine Cπ and Cμ , we shall derive an expression for hfe, the CE short-circuit current gain, as a func-tion of frequency in terms of the hybrid-π components. For this purpose consider the circuit shown in Fig. 9.9, in which the collector is shorted to the emitter. A node equation at C pro-vides the short-circuit collector current Ic as (9.37) A relationship between Vπ and Ib can be established by multiplying Ib by the impedance seen between and E: (9.38) Thus hfe can be obtained by combining Eqs. (9.37) and (9.38): Figure 9.8 The high-frequency hybrid-π model.
4 These values apply for discrete devices and devices fabricated with a relatively old IC process tech-nology (the so-called high-voltage process, see Appendix 7.A). For modern IC fabrication processes, Cπ and Cμ are in the range of tens of femtofarads (fF ).
B′ Ic gm sCμ – ( )Vπ = B′ Vπ Ib rπ Cπ Cμ ( ) Ib 1/rπ sCπ sCμ + + ----------------------------------------= = hfe Ic Ib ----≡ gm sCμ – 1/rπ s Cπ Cμ + ( ) + ------------------------------------------= 9.2 Internal Capacitive Effects and the High-Frequency Model of the MOSFET and the BJT 709 At the frequencies for which this model is valid, ω Cμ gm; thus we can neglect the sCμ term in the numerator and write Thus, (9.39) where β0 is the low-frequency value of β. Thus hfe has a single-pole (or STC) response with a 3-dB frequency at ω = ωβ, where (9.40) Figure 9.10 shows a Bode plot for From the –6-dB/octave slope, it follows that the fre-quency at which drops to unity, which is called the unity-gain bandwidth ωT, is given by (9.41) Thus, (9.42) Figure 9.9 Circuit for deriving an expression for Figure 9.10 Bode plot for hfe s ( ) I ≡ c Ib.
⁄ hfe gmrπ 1 s Cπ Cμ + ( )rπ + ----------------------------------------hfe β0 1 s Cπ Cμ + ( )rπ + ----------------------------------------= ωβ 1 Cπ Cμ + ( )rπ ----------------------------= hfe .
hfe ωT β 0ω β = ωT gm Cπ Cμ + ------------------= hfe .
710 Chapter 9 Frequency Response and (9.43) This expression is very similar to that of fT for the MOSFET (Eq. 9.31) with Cπ replacing Cgs and Cμ replacing Cgd.
The unity-gain bandwidth fT , also known as the transition frequency, which gives rise to the subscript T, is usually specified on the data sheets of a transistor. In some cases fT is given as a function of IC and VCE. To see how fT changes with IC, recall that gm is directly proportional to IC, but only part of Cπ (the diffusion capacitance Cde) is directly proportional to IC. It follows that fT decreases at low currents, as shown in Fig. 9.11. However, the decrease in fT at high cur-rents, also shown in Fig. 9.11, cannot be explained by this argument; rather, it is due to the same phenomenon that causes β0 to decrease at high currents (Section 6.9.2). In the region where fT is almost constant, Cπ is dominated by the diffusion part.
Typically, fT is in the range of 100 MHz to tens of gigahertz. The value of fT can be used in Eq. (9.43) to determine Cπ + Cμ. The capacitance Cμ is usually determined sepa-rately by measuring the capacitance between base and collector at the desired reverse-bias voltage VCB.
Before leaving this section, we should mention that the hybrid-π model of Fig. 9.8 characterizes transistor operation fairly accurately up to a frequency of about 0.2 fT. At higher frequencies one has to add other parasitic elements to the model as well as refine the model to account for the fact that the transistor is in fact a distributed-parameter net-work that we are trying to model with a lumped-component circuit. One such refinement consists of splitting rx into a number of parts and replacing Cμ by a number of capacitors, each connected between the collector and one of the taps of rx. This topic is beyond the scope of this book.
An important observation to make from the high-frequency model of Fig. 9.8 is that at frequencies above 5 to 10 fβ, one may ignore the resistance rπ. It can be seen then that rx becomes the only resistive part of the input impedance at high frequencies. Thus rx plays an important role in determining the frequency response of transistor circuits at high frequen-cies. It follows that an accurate determination of rx can be made only from a high-frequency measurement.
Figure 9.11 Variation of fT with IC.
fT gm 2π Cπ Cμ + ( ) ------------------------------= 9.3 High-Frequency Response of the CS and CE Amplifiers 711 Summary For convenient reference, Table 9.2 provides a summary of the relationships used to deter-mine the values of the parameters of the BJT high-frequency model.
9.3 High-Frequency Response of the CS and CE Amplifiers Equipped with equivalent-circuit models that represent the high-frequency operation of the MOSFET and the BJT, we now address the question of the high-frequency performance of the CS and CE amplifiers. Our objective is to identify the mechanism that limits the high-frequency performance of these important amplifier configurations. As well, we need to find a simple approach to estimate the frequency at which the gain falls by 3 dB below its value at midband frequencies, .
Table 9.2 The BJT High-Frequency Model B B C E gmV V C C r ro rx gm IC VT ⁄ = ro VA IC ⁄ = rπ β0 gm ⁄ = Cπ Cμ + gm 2πfT -----------= Cπ Cde Cje + = Cde τFgm = Cje 2Cje0 Cμ Cjc0 1 VCB V0c ------------+ ⎝ ⎠ ⎛ ⎞ m , m 0.3–0.5 = = fH AM 9.5 Find Cde, Cje, Cπ, Cμ, and fT for a BJT operating at a dc collector current IC = 1 mA and a CBJ reverse bias of 2 V. The device has τF = 20 ps, Cje0 = 20 fF, Cμ0 = 20 fF, V0e = 0.9 V, V0c = 0.5 V, and mCBJ = 0.33.
Ans. 0.8 pF; 40 fF; 0.84 pF; 12 fF; 7.47 GHz 9.6 For a BJT operated at IC = 1 mA, determine fT and Cπ if Cμ = 2 pF and = 10 at 50 MHz. Ans. 500 MHz; 10.7 pF 9.7 If Cπ of the BJT in Exercise 9.6 includes a relatively constant depletion-layer capacitance of 2 pF, find fT of the BJT when operated at IC = 0.1 mA.
Ans. 130.7 MHz hfe EXERCISES 712 Chapter 9 Frequency Response The analysis presented here applies equally well to discrete-circuit, capacitively coupled amplifiers and to IC amplifiers. The frequency response of the first was shown in Figs. 5.61 and 6.69 and that of the latter is shown in Fig. 9.12. At the frequencies of interest to us here (the high-frequency band), all coupling and bypass capacitors behave as perfect short cir-cuits and amplifiers of both types have identical high-frequency equivalent circuits.
9.3.1 The Common-Source Amplifier Figure 9.13(a) shows the high-frequency, equivalent-circuit model of a CS amplifier. It is obtained by replacing the MOSFET in an amplifier circuit such as that in Fig. 9.2 by its high-frequency, equivalent-circuit model of Fig. 9.6(c), while as always eliminating dc sources.
Observe that the circuit in Fig. 9.13(a) is general; for instance, it includes a resistance , which arises only in the case of a discrete-circuit amplifier. Also, can be either a passive resistance or the output resistance of a current-source load, and similarly for .
The equivalent circuit of Fig. 9.13(a) can be simplified by utilizing Thévenin theorem at the input side and by combining the three parallel resistances at the output side. The result-ing simplified circuit is shown in Fig. 9.13(b). The midband gain can be found from this circuit by setting and to zero. The result is (9.44) The equivalent circuit in Fig. 9.13(b) can be further simplified if we can find a way to deal with the bridging capacitor Cgd that connects the output node to the input side. Toward that end, consider first the output node. It can be seen that the load current is (gmVgs − Igd), where (gmVgs) is the output current of the transistor and Igd is the current supplied through the very small capacitance Cgd. At frequencies in the vicinity of fH, which defines the edge of the mid-band, it is reasonable to assume that Igd is still much smaller than (gmVgs), with the result that Vo can be given approximately by (9.45) Figure 9.12 Frequency response of a direct-coupled (dc) amplifier. Observe that the gain does not fall off at low frequencies, and the midband gain AM extends down to zero frequency.
3 dB f fH (or f3dB) 20 log AM A (dB) 0 RG RD RL AM Cgs Cgd AM Vo Vsig -------- RG RG Rsig + --------------------- gmR′ L ( ) – = = Vo gmVgs ( )RL ′ = g – mRL ′ Vgs – 9.3 High-Frequency Response of the CS and CE Amplifiers 713 where Since Vo = Vds, Eq. (9.45) indicates that the gain from gate to drain is −gmRL ′ , the same value as in the midband. The current Igd can now be found as Now, the left-hand side of the circuit in Fig. 9.13(b), at XX′, knows of the existence of Cgd only through the current Igd. Therefore, we can replace Cgd by an equivalent capacitance Ceq between the gate and ground as long as Ceq draws a current equal to Igd. That is, Figure 9.13 Determining the high-frequency response of the CS amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at the input and the output; (Continued) (a) Vsig Cgs gmVgs RG Rsig G D S Cgd ro RD RL Vgs Vo R L (b) Vsig V sig = Cgs gmVgs R sig RsigRG R L roRDRL G Cgd Igd R L Vgs Vo Igd RG RG Rsig X X RL ′ = ro RD RL || || Igd sCgd Vgs Vo – ( ) = sCgd Vgs gm – RL ′ Vgs ( ) – [ ] = sCgd 1 gmRL ′ + ( )Vgs = sCeqVgs sCgd 1 gmRL ′ + ( )Vgs = 714 Chapter 9 Frequency Response which results in (9.46) Thus Cgd gives rise to a much larger capacitance Ceq, which appears at the amplifier input.
The multiplication effect that Cgd undergoes comes about because it is connected between circuit nodes g and d, whose voltages are related by a large negative gain (− gmRL ′ ). This effect is known as the Miller effect, and (1 + gm RL ′ ) is known as the Miller multiplier. We will study Miller’s theorem more formally in Section 9.4.
Using Ceq enables us to simplify the equivalent circuit at the input side to that shown in Fig. 9.13(c). We recognize the circuit of Fig. 9.13(c) as a single-time-constant (STC) circuit Figure 9.13 (Continued) (c) the equivalent circuit with Cgd replaced at the input side with the equivalent capacitance Ceq; (d) the frequency response plot, which is that of a low-pass, single-time-constant circuit.
(c) Vsig Cgs R sig G X X Igd Vgs Ceq RG RG Rsig Ceq Cgd (1 gmR L) R L Vo gm R L Vgs Cin gmVgs (d) 20 log AM fH f (Hz) (log scale) 20 dBdecade 3 dB Vo Vsig (dB) Ceq Cgd 1 gmRL ′ + ( ) = 9.3 High-Frequency Response of the CS and CE Amplifiers 715 of the low-pass type (Section 1.6 and Appendix E). Reference to Table 1.2 enables us to express the output voltage Vgs of the STC circuit in the form (9.47) where ω0 is the corner frequency, the break frequency, or the pole frequency of the STC circuit, (9.48) with (9.49) and (9.50) Combining Eqs. (9.45) and (9.47) results in the following expression for the high-frequency gain of the CS amplifier, (9.51) which can be expressed in the form (9.52) where the midband gain AM is given by Eq. (9.44) and ωH is the upper 3-dB frequency, (9.53) and (9.54) We thus see that the high-frequency response will be that of a low-pass STC network with a 3-dB frequency fH determined by the time constant . Figure 9.13(d) shows a sketch of the magnitude of the high-frequency gain.
Before leaving this section we wish to make a number of observations: 1. The upper 3-dB frequency is determined by the interaction of and . Since the bias resistance RG is usually very large, it can be neglected, resulting in the resistance of the signal source. It fol-lows that a large value of Rsig will cause fH to be lowered.
2. The total input capacitance Cin is usually dominated by Ceq, which in turn is made large by the multiplication effect that Cgd undergoes. Thus, although Cgd is usually a very small capacitance, its effect on the amplifier frequency response can be very significant as a result of its multiplication by the factor ( ), which is approximately equal Vgs RG RG Rsig + ---------------------Vsig ⎝ ⎠ ⎛ ⎞ 1 1 s ω0 ------+ ---------------= ω0 1 CinR′sig ⁄ = Cin Cgs Ceq + Cgs Cgd 1 gmRL ′ + ( ) + = = Rsig ′ = Rsig RG || Vo Vsig --------RG RG Rsig + ---------------------⎝ ⎠ ⎛ ⎞ – gmRL ′ ( ) 1 1 s ω0 ------+ ---------------= Vo Vsig --------AM 1 s ωH -------+ ----------------= ωH ω0 1 CinR ′sig -----------------= = fH ωH 2π -------1 2πCinR′sig ------------------------= = CinRsig ′ Rsig ′ = Rsig RG || Cin Cgs Cgd 1 gmRL ′ + ( ) + = Rsig ′ Rsig, 1 gmRL ′ + 716 Chapter 9 Frequency Response to the midband gain of the amplifier. This is the Miller effect, which causes the CS amplifier to have a large total input capacitance Cin and hence a low fH.
3. To extend the high-frequency response of a MOSFET amplifier, we have to find configurations in which the Miller effect is absent or at least reduced. We shall return to this subject at great length in Section 9.6 and beyond.
4. The above analysis, resulting in an STC or a single-pole response, is approximate.
Specifically, it is based on neglecting Igd relative to gmVgs, an assumption that applies well at frequencies not too much higher than fH. An exact analysis of the circuit in Fig. 9.13(a) will be carried out in Section 9.5. The results above, however, are more than sufficient for a quick estimate of fH. As well, the approximate approach helps to reveal the primary limitation on the high-frequency response: the Miller effect.
Find the midband gain AM and the upper 3-dB frequency fH of a CS amplifier fed with a signal source having an internal resistance Rsig = 100 kΩ. The amplifier has , RD = RL = 15 kΩ, , , , and .
Solution where .
Thus, The equivalent capacitance, Ceq, is found as The total input capacitance Cin can be now obtained as The upper 3-dB frequency fH is found from RG = 4.7 MΩ gm = 1 mA/V ro = 150 kΩ Cgs = 1 pF Cgd = 0.4 pF AM RG RG Rsig + ---------------------– gmRL ′ = RL ′ = ro RD RL || || 150 15 15 || || 7.14 kΩ = = gmRL ′ = 1 7.14 × 7.14 V/V = AM 4.7 4.7 0.1 + ---------------------7.14 7 – V/V = × – = Ceq 1 gmRL ′ + ( )Cgd = 1 7.14 + ( ) 0.4 3.26 pF = × = Cin Cgs Ceq + 1 3.26 + 4.26 pF = = = fH 1 2πCin Rsig RG || ( ) ----------------------------------------= 1 2π × 4.26 10 12 – 0.1 4.7 || ( ) 106 × × -----------------------------------------------------------------------------------= 382 kHz = Example 9.3 9.3 High-Frequency Response of the CS and CE Amplifiers 717 9.3.2 The Common-Emitter Amplifier Figure 9.14(a) shows the high-frequency equivalent circuit of a CE amplifier. It is obtained by replacing the BJT in a circuit such as that in Fig. 9.4(a) with its high-frequency, equivalent-circuit model of Fig. 9.8, and, as usual, eliminating all dc sources. Observe that the circuit in Fig. 9.14(a) is general and applies to both discrete and IC amplifiers. Thus, it includes , which is usually present in discrete circuits. Also can be either a passive resistance or the output resistance of a current-source load, and similarly for .
The equivalent circuit of Fig. 9.14(a) can be simplified by utilizing Thévenin theorem at the input side and by combining the three parallel resistances at the output side. Specifically, the reader should be able to show that applying Thévenin theorem twice simplifies the resis-tive network at the input side to a signal generator and a resistance , with the val-ues indicated in the figure. The equivalent circuit in Fig. 9.14(b) can be used to obtain the midband gain by set-ting and to zero. The result is (9.55) where (9.56) Next we observe that the circuit in Fig. 9.14(b) is identical to that of the CS amplifier in Fig.
9.13(b). Thus the analysis can follow the same process we used for the CS case. The analy-sis is illustrated in Fig. 9.13(c) and (d). The final result is that the CE amplifier gain at high frequencies is given approximately by (9.57) where is given by Eq. (9.55) and the 3-dB frequency is given by (9.58) RB RC RL Vsig ′ Rsig ′ AM Cπ Cμ AM Vo Vsig -------- RB RB Rsig + ---------------------rπ rπ rx Rsig RB || ( ) + + -----------------------------------------------(gmR′L) – = = R′ L ro RC RL || || = Vo Vsig -------- AM 1 s ωH -------+ ----------------= AM fH fH ωH 2π ------- 1 2πCinR′sig -------------------------= = 9.8 For the CS amplifier specified in Example 9.3, find the values of AM and fH that result when the signal-source resistance is reduced to 10 kΩ.
Ans. –7.12 V/V; 3.7 MHz 9.9 If it is possible to replace the MOSFET used in the amplifier in Example 9.3 with another having the same Cgs but a smaller Cgd, what is the maximum value that its Cgd can be in order to obtain an fH of at least 1 MHz?
Ans. 0.08 pF EXERCISES 718 Chapter 9 Frequency Response Figure 9.14 Determining the high-frequency response of the CE amplifier: (a) equivalent circuit; (b) the circuit of (a) simplified at both the input side and the output side; (c) equivalent circuit with Cμ replaced at the input side with the equivalent capacitance Ceq; (continued) (a) RB Rsig Vsig B B C RL E gmVp Vp Cp Cm Vo rp ro RC RL rx (b) R sig V sig B X X C gmV V C C Vo R L I I R L roRCRL V sig Vsig R sig r[rx (RBRsig)] RB RB Rsig r r rx (RsigRB) (c) R sig V sig B X X C gmVp Vp Cp V o R L V o gmR LVp Ceq Cin Im Cp Cm(1 gmR L) Cin Cp Ceq 9.3 High-Frequency Response of the CS and CE Amplifiers 719 where (9.59) and (9.60) Observe that is simply the sum of and the Miller capacitance . The resistance seen by can be easily found from the circuit in Fig. 9.14(a) as follows: Reduce to zero, “grab hold” of the terminals B′ and E and look back (to the left). You will see rπ in parallel with , which is in series with . This way of finding the resistance “seen by a capacitance” is very useful and spares one from tedious work! Finally, comments very similar to those made on the high-frequency response of the CS amplifier can be made here as well.
Figure 9.14 (Continued) (d) sketch of the frequency-response plot, which is that of a low-pass STC circuit.
(d) 0 f (Hz, log scale) (dB) V o V sig 3 dB 6 dBoctave 20 dBdecade 20 log AM fH fH 2pCinR sig 1 Cin Cπ Cμ 1 gmR′ L) + ( + = R′sig rπ rx RB Rsig || ( ) + [ ] || = Cin Cπ Cμ 1 gmR′ L) + ( Rsig ′ Cin Vsig rx RB Rsig || ( ) Example 9.4 It is required to find the midband gain and the upper 3-dB frequency of the common-emitter ampli-fier of Fig. 9.4(a) for the following case: VCC = VEE = 10 V, I = 1 mA, RB = 100 kΩ, RC = 8 kΩ, Rsig = 5 kΩ, RL = 5 kΩ, β0 = 100, VA = 100 V, Cμ = 1 pF, fT = 800 MHz, and rx = 50 Ω.
Solution The transistor is biased at IC 1 mA. Thus the values of its hybrid-π model parameters are gm IC VT ------1 mA 25 mV ----------------40 mA/V = = = rπ β0 gm ------100 40 mA/V -----------------------2.5 kΩ = = = ro VA IC ------100 V 1 mA ---------------100 kΩ = = = 720 Chapter 9 Frequency Response Example 9.4 continued The midband voltage gain is where Thus, and and To determine fH we first find Cin, and the effective source resistance , = 1.65 kΩ Thus, Cπ Cμ + gm ωT ------40 10 3 – × 2π 800 106 × × ---------------------------------------8 pF = = = Cμ 1 pF = Cπ 7 pF = rx 50 Ω = AM RB RB Rsig + ---------------------rπ rπ rx RB Rsig || ( ) + + -----------------------------------------------gmRL ′ – = RL ′ = ro RC RL || || 100 8 5 || || ( ) kΩ = 3 kΩ = gmRL ′ = 40 3 × 120 V/V = AM 100 100 5 + ------------------2.5 2.5 0.05 100 5 || ( ) + + ----------------------------------------------------× 120 × – = 39 V/V – = 20 log AM 32 dB = Cin Cπ Cμ (1 gmRL ′ ) + + = 7 1 1 120 + ( ) + = 128 pF = Rsig ′ Rsig ′ = rπ rx RB Rsig || ( ) + [ ] || 2.5 0.05 100 5 || ( ) + [ ] || = fH 1 2πCinRsig ′ ------------------------1 2π 128 10 12 – 1.65 103 × × × × -------------------------------------------------------------------------754 kHz = = = 9.10 For the amplifier in Example 9.4, find the value of RL that reduces the midband gain to half the value found. What value of fH results? Note the trade-off between gain and bandwidth.
Ans. 1.9 kΩ; 1.42 MHz EXERCISE 9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 721 9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers The approximate method used in the previous section to analyze the high-frequency response of the CS and CE amplifiers provides a reasonably accurate estimate of and, equally important, considerable insight into the mechanism that limits high-frequency operation. Unfortunately, however, this method is not easily extendable to more complex amplifier circuits. For this reason, we will digress briefly in this section to equip ourselves with a number of tools that will prove useful in the analysis of more complex circuits such as the cascode amplifier. We will begin by stepping back and more generally considering the amplifier high-frequency transfer function.
9.4.1 The High-Frequency Gain Function The amplifier gain, taking into account the internal transistor capacitances, can be expressed as a function of the complex-frequency variable s in the general form (9.61) where is the midband gain, which for IC amplifiers is also equal to the low-frequency or dc gain (refer to Fig. 9.12). The value of can be determined by analyzing the amplifier equiva-lent circuit while neglecting the effect of the transistor internal capacitances—that is, by assum-ing that they act as perfect open circuits. By taking these capacitances into account, we see that the gain acquires the factor which can be expressed in terms of its poles and zeros, which are usually real, as follows: (9.62) where . . . , are positive numbers representing the frequencies of the n real poles and . . . , are positive, negative, or infinite numbers representing the frequencies of the n real transmission zeros. Note from Eq. (9.62) that, as should be expected, as s approaches 0, approaches unity and the gain approaches 9.4.2 Determining the 3-dB Frequency fH The amplifier designer usually is particularly interested in the part of the high-frequency band that is close to the midband. This is because the designer needs to estimate—and if need be modify—the value of the upper 3-dB frequency (or ). Toward that end it should be mentioned that in many cases the zeros are either at infinity or such high frequencies as to be of little significance to the determination of If in addition one of the poles, say is of much lower frequency than any of the other poles, then this pole will have the greatest effect on the value of the amplifier In other words, this pole will dominate the high-frequency response of the amplifier, and the amplifier is said to have a dominant-pole response. In such cases, the function can be approximated by (9.63) which is the transfer function of a first-order (or STC) low-pass network (Appendix E). It follows that if a dominant pole exists, then the determination of is greatly simplified; (9.64) fH A s ( ) = AMFH s ( ) AM AM FH s ( ), FH s ( ) 1 s ωZ1 ⁄ + ( ) 1 s ωZ2 ⁄ + ( ) . . . 1 s ωZn ⁄ + ( ) 1 s ωP1 ⁄ + ( ) 1 s ωP2 ⁄ + ( ). . . 1 s ωPn ⁄ + ( ) -------------------------------------------------------------------------------------------------= ωP1, ωP2, ωPn ωZ1, ωZ2, ωZn FH s ( ) AM.
fH ωH; fH = ωH 2π ⁄ ωH.
ωP1, ωH.
FH s ( ) FH s ( ) 1 1 s ωP1 ⁄ + ------------------------ωH ωH ωP1 722 Chapter 9 Frequency Response This is the situation we encountered in the cases of the common-source and common-emitter amplifiers analyzed in Section 9.3. As a rule of thumb, a dominant pole exists if the lowest-frequency pole is at least two octaves (a factor of 4) away from the nearest pole or zero.
If a dominant pole does not exist, the 3-dB frequency can be determined from a plot of . Alternatively, an approximate formula for can be derived as follows: Consider, for simplicity, the case of a circuit having two poles and two zeros in the high-frequency band; that is, (9.65) Substituting and taking the squared magnitude gives By definition, at ; thus, (9.66) Since is usually smaller than the frequencies of all the poles and zeros, we may neglect the terms containing and solve for to obtain (9.67) This relationship can be extended to any number of poles and zeros as (9.68) Note that if one of the poles, say is dominant, then . . . , . . . , and Eq. (9.68) reduces to Eq. (9.69).
ωH FH jω ( ) ωH FH s ( ) 1 s ωZ1 ⁄ + ( ) 1 s ωZ2 ⁄ + ( ) 1 s ωP1 ⁄ + ( ) 1 s ωP2 ⁄ + ( ) ----------------------------------------------------------= s = jω FH jω ( ) 2 1 ω 2 ωZ1 2 ⁄ + ( ) 1 ω 2 ωZ2 2 ⁄ + ( ) 1 ω 2 ωP1 2 ⁄ + ( ) 1 ω 2 ωP2 2 ⁄ + ( ) ------------------------------------------------------------------= ω = ωH, FH 2 1 2 ---= 1 2 --- 1 ωH 2 ωZ1 2 ⁄ + ( ) 1 ωH 2 ωZ2 2 ⁄ + ( ) 1 ωH 2 ωP1 2 ⁄ + ( ) 1 ωH 2 ωP2 2 ⁄ + ( ) --------------------------------------------------------------------= 1 ωH 2 1 ωZ1 2 --------1 ωZ2 2 --------+ ⎝ ⎠ ⎛ ⎞ ωH 4 ωZ1 2 ωZ2 2 ⁄ + + 1 ωH 2 1 ωP1 2 --------1 ωP2 2 --------+ ⎝ ⎠ ⎛ ⎞ ωH 4 ωP1 2 ωP2 2 ⁄ + + ---------------------------------------------------------------------------------= ωH ωH 4 ωH ωH 1 1 ωP1 2 --------1 ωP2 2 --------2 ωZ1 2 --------– 2 ωZ2 2 --------– + ωH 1 1 ωP1 2 --------1 ωP2 2 --------. . .
+ + ⎝ ⎠ ⎛ ⎞ 2 1 ωZ1 2 --------1 ωZ2 2 --------. . .
+ + ⎝ ⎠ ⎛ ⎞ – P1, ωP1 ωP2, ωP3, ωZ1, ωZ2, The high-frequency response of an amplifier is characterized by the transfer function Determine the 3-dB frequency approximately and exactly.
F H s ( ) 1 s/105 – 1 s/104 + ( ) 1 s/4 104 × + ( ) ---------------------------------------------------------------= Example 9.5 9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 723 Solution Noting that the lowest-frequency pole at 104 rad/s is two octaves lower than the second pole and a decade lower than the zero, we find that a dominant-pole situation almost exists and 104 rad/s. A better estimate of ωH can be obtained using Eq. (9.68), as follows: The exact value of ωH can be determined from the given transfer function as 9537 rad/s. Finally, we show in Fig. 9.15 a Bode plot and an exact plot for the given transfer function. Note that this is a plot of the high-frequency response of the amplifier normalized relative to its midband gain. That is, if the midband gain is, say, 100 dB, then the entire plot should be shifted upward by 100 dB.
Figure 9.15 Normalized high-frequency response of the amplifier in Example 9.5.
ωH ωH 1 1 108 -------- + 1 16 108 × --------------------2 1010 ----------– = 9800 rad/s = 724 Chapter 9 Frequency Response 9.4.3 Using Open-Circuit Time Constants for the Approximate Determination of fH If the poles and zeros of the amplifier transfer function can be determined easily, then we can determine fH using the techniques above. In many cases, however, it is not a simple matter to determine the poles and zeros by quick hand analysis. In such cases an approximate value for fH can be obtained using the following method.
Consider the function (Eq. 9.62), which determines the high-frequency response of the amplifier. The numerator and denominator factors can be multiplied out and expressed in the alternative form (9.69) where the coefficients a and b are related to the frequencies of the zeros and poles, respec-tively. Specifically, the coefficient is given by (9.70) It can be shown [see Gray and Searle (1969)] that the value of b1 can be obtained by consid-ering the various capacitances in the high-frequency equivalent circuit one at a time while reducing all other capacitors to zero (or, equivalently, replacing them with open circuits).
That is, to obtain the contribution of capacitance Ci we reduce all other capacitances to zero, reduce the input signal source to zero, and determine the resistance Ri seen by Ci. This pro-cess is then repeated for all other capacitors in the circuit. The value of b1 is computed by summing the individual time constants, called open-circuit time constants, (9.71) where we have assumed that there are n capacitors in the high-frequency equivalent circuit. This method for determining b1 is exact; the approximation comes about in using the value of b1 to determine ωH. Specifically, if the zeros are not dominant and if one of the poles, say P1, is dominant, then from Eq. (9.70), (9.72) But, also, the upper 3-dB frequency will be approximately equal to ωP1, leading to the approximation (9.73) Here it should be pointed out that in complex circuits we usually do not know whether a dominant pole exists. Nevertheless, using Eq. (9.73) to determine ωH normally yields remarkably good results5 even if a dominant pole does not exist. The method will be illustrated by an example.
5 The method of open-circuit time constants yields good results only when all the poles are real, as is the case in this chapter.
FH s ( ) F H s ( ) FH s ( ) 1 a1s a2s 2 . . . + ans n + + + 1 b1s b2s 2 . . . + bns n + + + ----------------------------------------------------------------= b1 b1 1 ωP1 --------1 ωP2 --------. . .
1 ωPn --------+ + + = b1 CiRi i=1 n ∑ = b1 1 ωP1 --------ωH 1 b1 ----- = 1 Σ i CiRi ---------------9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 725 Figure 9.16(a) shows the high-frequency equivalent circuit of a common-source MOSFET amplifier.
The amplifier is fed with a signal generator Vsig having a resistance Rsig. Resistance RG is due to the biasing network. Resistance is the parallel equivalent of the load resistance RL, the drain bias resistance RD, and the FET output resistance ro. Capacitors Cgs and Cgd are the MOSFET internal capaci-tances. For Rsig = 100 kΩ, RG = 420 kΩ, Cgs = Cgd = 1 pF, gm = 4 mA/V, and = 3.33 kΩ, find the mid-band voltage gain, AM = Vo/Vsig and the upper 3-dB frequency, Solution The midband voltage gain is determined by assuming that the capacitors in the MOSFET model are perfect open circuits. This results in the midband equivalent circuit shown in Fig. 9.16(b), Figure 9.16 Circuits for Example 9.6: (a) high-frequency equivalent circuit of a MOSFET amplifier; (b) the equivalent circuit at midband frequencies; (c) circuit for determining the resistance seen by Cgs; (d) circuit for determining the resistance seen by Cgd.
RL ′ RL ′ f H.
(a) Rsig RG Vsig (b) Rsig Vsig RG Rsig (c) RG sig (d) Vgs Rsig Rsig RG RG Example 9.6 726 Chapter 9 Frequency Response Example 9.6 continued from which we find We shall determine ωH using the method of open-circuit time constants. The resistance Rgs seen by Cgs is found by setting Cgd = 0 and short-circuiting the signal generator Vsig. This results in the circuit of Fig.
9.16(c), from which we find that Thus the open-circuit time constant of Cgs is The resistance Rgd seen by Cgd is found by setting Cgs = 0 and short-circuiting Vsig. The result is the circuit in Fig. 9.16(d), to which we apply a test current Ix. Writing a node equation at G gives Thus, (9.74) where . A node equation at D provides Substituting for Vgs from Eq. (9.74) and rearranging terms yields Thus the open-circuit time constant of Cgd is The upper 3-dB frequency ωH can now be determined from Thus, AM Vo Vsig ---------≡ RG RG Rsig + ----------------------– (gmRL ′ ) = 420 420 100 + ------------------------4 3.33 10.8 V/V – = × × – = Rgs RG||Rsig = 420 kΩ||100 kΩ 80.8 kΩ = = τgs CgsRgs ≡ 1 10 12 – × 80.8 103 × × = 80.8 ns = Ix −V gs RG -------V gs Rsig --------– = V gs IxR′sig – = R′sig = RG Rsig || Ix = gmV gs V gs Vx + RL ′ -------------------+ Rgd Vx Ix -----≡ R′sig R′ L gm RL ′ R′sig + + 1.16 MΩ = = τgd CgdRgd ≡ 1 10 12 – × 1.16 106 × × = 1160 ns = ωH 1 τgs τgd + --------------------1 80.8 1160 + ( ) 10 9 – × --------------------------------------------------= 806 krad/s = fH ωH 2π -------128.3 kHz = = 9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 727 The method of open-circuit time constants has an important advantage in that it tells the circuit designer which of the various capacitances is significant in determining the amplifier frequency response. Specifically, the relative contribution of the various capacitances to the effective time constant b1 is immediately obvious. For instance, in the above example we see that Cgd is the domi-nant capacitance in determining fH. We also note that, in effect to increase fH either we use a MOS-FET with smaller Cgd or, for a given MOSFET, we reduce Rgd by using a smaller or . If is fixed, then for a given MOSFET the only way to increase bandwidth is by reducing the load resistance. Unfortunately, this also decreases the midband gain. This is an example of the usual trade-off between gain and bandwidth, a common circumstance which was mentioned earlier. 9.4.4 Miller’s Theorem In our analysis of the high-frequency response of the common-source and common-emitter amplifiers (Section 9.3), we employed a technique for replacing the bridging capacitance by an equivalent input capacitance. This very useful and effective technique is based on a general theorem known as Miller’s theorem, which we now present.
Consider the situation in Fig. 9.17(a). As part of a larger circuit that is not shown, we have isolated two circuit nodes, labeled 1 and 2, between which an impedance Z is connected.
Nodes 1 and 2 are also connected to other parts of the circuit, as signified by the broken lines emanating from the two nodes. Furthermore, it is assumed that somehow it has been determined that the voltage at node 2 is related to that at node 1 by (9.75) In typical situations K is a gain factor that can be positive or negative and that has a magnitude usually larger than unity. This, however, is not an assumption for Miller’s theorem.
Miller’s theorem states that impedance Z can be replaced by two impedances: connected between node 1 and ground and connected between node 2 and ground, where (9.76a) and (9.76b) to obtain the equivalent circuit shown in Fig. 9.17(b). Figure 9.17 The Miller equivalent circuit.
R′sig RL ′ R′ sig (Cgs or Cμ) V2 KV1 = Z1 Z2 Z1 Z 1 K – ( ) ⁄ = Z2 Z 1 1 K ----– ⎝ ⎠ ⎛ ⎞ = (a) V2 KV1 V1 1 2 Z I I (b) V2 KV1 V1 Z1 Z2 1 2 I2 I I1 I 1 K Z1 Z(1 K), Z2 Z 1 728 Chapter 9 Frequency Response The proof of Miller’s theorem is achieved by deriving Eq. (9.76) as follows: In the original circuit of Fig. 9.17(a), the only way that node 1 “feels the existence” of impedance Z is through the current I that Z draws away from node 1. Therefore, to keep this current unchanged in the equivalent circuit, we must choose the value of so that it draws an equal current, which yields the value of in Eq. (9.76a). Similarly, to keep the current into node 2 unchanged, we must choose the value of so that which yields the expression6 for in Eq. (9.76b).
6 Although not highlighted, the Miller equivalent circuit derived above is valid only as long as the rest of the circuit remains unchanged; otherwise the ratio of to might change. It follows that the Miller equivalent circuit cannot be used directly to determine the output resistance of an amplifier. This is because in determining output resistances it is implicitly assumed that the source signal is reduced to zero and that a test-signal source (voltage or current) is applied to the output terminals—obviously a major change in the circuit, rendering the Miller equivalent circuit no longer valid.
Z1 I1 V1 Z1 ----- I V1 KV1 – Z ---------------------= = = Z1 Z2 I2 0 V2 – Z2 -------------- 0 KV1 – Z2 ------------------- I V1 KV1 – Z ---------------------= = = = Z2 V2 V1 Figure 9.18(a) shows an ideal voltage amplifier having a gain of with an impedance Z connected between its output and input terminals. Find the Miller equivalent circuit when Z is (a) a 1-MΩ resistance and (b) a 1-pF capacitance. In each case, use the equivalent circuit to determine Solution (a) For Z = 1 MΩ, employing Miller’s theorem results in the equivalent circuit in Fig. 9.18(b), where The voltage gain can be found as follows: 100 V/V – Vo Vsig.
⁄ Z1 Z 1 K – ------------- 1000 kΩ 1 100 + --------------------- = 9.9 kΩ = = Z2 Z 1 1 K ----– ------------- 1 MΩ 1 1 100 ---------+ ------------------ = 0.99 MΩ = = Vo Vsig -------- V o Vi ----- Vi Vsig -------- 100 × Z1 Z1 Rsig + --------------------– = = 100 × 9.9 9.9 10 + ------------------- 49.7 V/V – = – = Example 9.7 9.4 Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 729 Figure 9.18 Circuits for Example 9.7.
(a) Vi Vsig Vo Rsig 10 k 1 2 Z 100 (b) Vsig Rsig 100Vi Z1 1 Vi Z2 2 Vo (c) Vsig Rsig 100Vi 1 Vi Vo Z1 Z2 (b) For Z as a 1-pF capacitance—that is, —applying Miller’s theorem allows us to replace Z by and where It follows that is a capacitance 101C = 101 pF and that is a capacitance 1.01C = 1.01 pF. The resulting equivalent circuit is shown in Fig. 9.18(c), from which the voltage gain can be found as fol-lows: Z =1 sC ⁄ =1 s 1 10 12 – × × ⁄ Z1 Z2, Z1 Z 1 K – ------------- 1 s ⁄ C 1 100 + ------------------ 1 s 101C ( ) ⁄ = = = Z2 Z 1 1 K ----– ------------- 1 1.01 ---------- 1 sC ------ 1 s 1.01C ( ) ----------------------= = = Z1 Z2 V o Vsig -------- V o Vi ----- Vi Vsig -------- 100 1 s ⁄ C1 1 sC1 ( ) ⁄ Rsig + -----------------------------------– = = 100 – 1 sC1Rsig + ---------------------------= 730 Chapter 9 Frequency Response From Example 9.7, we observe that the Miller replacement of a feedback or bridging resistance results, for a negative K, in a smaller resistance [by a factor at the input.
If the feedback element is a capacitance, its value is multiplied by to obtain the equivalent capacitance at the input side. The multiplication of a feedback capacitance by is referred to as Miller multiplication or Miller effect. We have encountered the Miller effect in the analysis of the CS and CE amplifiers in Section 9.3. 1 K – ( )] 1 K – ( ) 1 K – ( ) Example 9.7 continued This is the transfer function of a first-order low-pass network with a dc gain of −100 and a 3-dB fre-quency of 100 – 1 s 101 1 10 12 – 10 103 × × × × × + ---------------------------------------------------------------------------------= 100 – 1 s 1.01 10 6 – × × + ---------------------------------------------= f 3dB f 3dB 1 2π × 1.01 10 6 – × ---------------------------------------- =157.6 kHz = EXERCISES 9.11 A direct-coupled amplifier has a dc gain of 1000 V/V and an upper 3-dB frequency of 100 kHz. Find the transfer function and the gain–bandwidth product in hertz.
Ans. 9.12 The high-frequency response of an amplifier is characterized by two zeros at and two poles at and For find the value of k that results in the exact value of being 0.9 Repeat for Ans. 2.78; 9.88 9.13 For the amplifier described in Exercise 9.12, find the exact and approximate values (using Eq. 9.68) of (as a function of ) for the cases k = 1, 2, and 4.
Ans. 0.64, 0.71; 0.84, 0.89; 0.95, 0.97 9.14 For the amplifier in Example 9.6, find the gain–bandwidth product in megahertz. Find the value of that will result in kHz. Find the new values of the midband gain and of the gain–bandwidth product.
Ans. 1.39 MHz; 2.23 V/V; 1.30 MHz 9.15 Use Miller’s theorem to investigate the performance of the inverting op-amp circuit shown in Fig. E9.15.
Assume the op amp to be ideal except for having a finite differential gain, A. Without using any knowl-edge of op-amp circuit analysis, find , , , and , for each of the following values of A: 10 V/V, 100 V/V, 1000 V/V, and 10,000 V/V. Assume 1000 1 s 2π ×105 --------------------+ ------------------------------ 108 Hz ; s ∞ = ωP1 ωP2.
ωP2 kωP1, = ωH ωP1.
ωΗ = 0.99ωP1.
ωH ωP1 RL ′ fH =180 kΩ; 7.2 – Rin Vi V o V o V sig ⁄ Vsig 1 V.
= 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 731 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers In Section 9.3 we utilized the Miller approximation to obtain an estimate of the high-frequency 3-dB frequency of the CS and CE amplifiers. We shall now use the powerful tools we studied in the last section to revisit this subject. Specifically, we will first employ Miller’s theorem to refine the Miller approximation, thus obtaining a better estimate of .
Then we will use the method of open-circuit time constants to obtain another estimate of .
In order to assess how good these various estimates are, the exact transfer function will be derived and analyzed. Finally, we will consider the case of low source resistance with the limitation on the high-frequency response determined by the capacitance at the output node, a situation that is not uncommon in IC amplifiers.
9.5.1 The Equivalent Circuit Figure 9.19 shows a generalized high-frequency equivalent circuit for the common-source amplifier. Here, and are the Thévenin equivalent of the signal generator together with whatever bias circuit may be present at the amplifier input (e.g., in the circuit of Fig.
9.2a). Resistance represents the total resistance between the output (drain) node and ground and includes , , and (if one is present). Similarly, represents the total capacitance between the drain node and ground and includes the MOSFET’s drain-to-body capacitance ( ), the capacitance introduced by a current-source load, the input capacitance of a succeeding amplifier stage (if one is present), and in some cases, as we will see in later chapters, a deliberately introduced capacitance. In IC MOS amplifiers, can be substantial. The equivalent circuit in Fig. 9.19 can also be used to represent the CE amplifier. Thus, we will not need to repeat the analysis, rather we will adapt the CS results to the CE case by simply renaming the components (i.e., replacing by and by ).
fH fH fH Rsig V′ sig R′sig RG R′L RD ro RL CL Cdb CL Cgs Cπ Cgd Cμ A Rin Vi Vo Vo/Vsig 10 V/V 100 V/V 1000 V/V 10,000 V/V 909 Ω 99 Ω 9.99 Ω 1 Ω 476 mV 90 mV 9.9 mV 0.999 mV −4.76 V −9 V −9.9 V −9.99 V −4.76 V/V −9 V/V −9.9 V/V −9.99 V/V Vsig 10 k 1 k Rin Vo Vi Figure E9.15 Ans. 732 Chapter 9 Frequency Response 9.5.2 Analysis Using Miller’s Theorem Miller’s theorem allows us to replace the bridging capacitor by two capacitors: between the input node and ground and between the output node and ground, as shown in Fig. 9.20. The value of and can be determined using Eqs. (9.76a) and (9.76b), where Obviously, K will depend on the value of , which in turn depends on the value of K. To simplify matters, we shall adopt an iterative procedure: First, we will neglect and in Figure 9.19 Generalized high-frequency equivalent circuit for the CS amplifier.
Figure 9.20 The high-frequency equivalent circuit model of the CS amplifier after the application of Miller’s theorem to replace the bridging capacitor Cgd by two capacitors: and where V CL R Cgs Cgd G D gmVgs sig Vgs V o R sig L Cgd C1 C2 C1 C2 C1 Cgd 1 K – ( ) = C2 Cgd 1 1 K ----– ⎝ ⎠ ⎛ ⎞ = K Vo Vgs -------= C2 C2 CL Vgs Vsig Rsig Cgs Cin C1 G Vo gmVgs CL CL C2 D R L C1 Cgd 1 K – ( ) = C2 Cgd 1 1 K ⁄ – ( ), = K Vo Vgs ⁄ .
= 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 733 determining , resulting in (9.77) That is, K is given by Then we will use this value to determine and as (9.78) (9.79) Next, we use and to determine the overall transfer function . At the input side, we see that the input capacitance together with form an STC low-pass circuit with a pole frequency : (9.80) At the output sides we see that together with form an STC low-pass circuit with a pole frequency : (9.81) At this point we note that in Section 9.3 we neglected both and and thus . Thus the estimate of in Section 9.3 was based on the assumption that is given by Eq. (9.77), and thus the frequency limitation is caused entirely by the interaction of with , that is, by the input pole : (9.82) A somewhat better estimate of can be obtained by considering both and , that is, by using the approximate transfer function7 7 This transfer function is approximate because we obtained it using an iterative process with in fact only one iteration!
Vo Vo gmVgsR ′ L – K gmR ′ L – C1 C2 C1 Cgd 1 gmR ′ L + ( ) = C2 Cgd 1 1 gmR′ L --------------+ ⎝ ⎠ ⎛ ⎞ = C1 C2 Vo V′ sig ⁄ Cin Cgs C1 + = R′sig fPi fPi 1 2πCinR′sig -------------------------= C′ L CL C2 + = R′ L fPo fPo 1 2πC ′ L R′ L ---------------------= C2 CL fPo fH Vo Cin R′ sig fPi fH fPi fH fPi fPo Vo V′ sig ---------- g – mR′L 1 s ωPi --------+ ⎝ ⎠ ⎛ ⎞1 s ωPo ---------+ ⎝ ⎠ ⎛ ⎞ ------------------------------------------------= 734 Chapter 9 Frequency Response An estimate of can then be found using Eq. (9.68) as (9.83) This estimate will diverge from that in Eq. (9.82) in situations for which is not much higher than . This will be the case when is not very high and is relatively large.
fH fH 1 1 fPi 2 -----1 fPo 2 ------+ = fPi 1 fPi fPo ------⎝ ⎠ ⎛ ⎞ 2 + ----------------------------= fPo fPi R′ sig CL Consider an IC CS amplifier for which mA/V2, fF, fF, fF, k , and k . Assume that includes . Determine using (a) the Miller approximation and (b) Miller’s theorem.
Solution (a) The Miller approximation assumes and thus neglects the effect of and . In this case, where Thus, fF and will be MHz Thus, MHz (b) Using Miller’s theorem, we obtain the same as above: MHz gm 1.25 = Cgs 20 = Cgd 5 = CL 25 = R′ sig 10 = Ω R′ L 10 = Ω CL Cdb fH Vo gmR′L Vgs – = CL C2 fH fPi 1 2πCinR′ sig -----------------------= Cin Cgs C1 Cgs Cgd 1 gmR′ L + ( ) + = + = Cin 20 5 1 1.25 10 × + ( ) + = 87.5 = fPi fPi 1 2π 87.5 10 15 – 10 103 × × × × ---------------------------------------------------------------------= 181.9 = fH 181.9 fPi fPi 181.9 = Example 9.8 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 735 9.5.3 Analysis Using Open-Circuit Time Constants The method of open-circuit time constants presented in Section 9.4.3 can be directly applied to the CS equivalent circuit of Fig. 9.19, as illustrated in Fig. 9.21, from which we see that the resistance seen by , and that seen by is . The resistance seen by can be found by analyzing the circuit in Fig. 9.21(b) with the result that (9.84) Thus the effective time constant or can be found as (9.85) and the 3-dB frequency is (9.86) For situations in which is substantial, this approach yields a better estimate of than that obtained using the Miller approximation (simply because in the latter case we com-pletely neglected Cgs Rgs R′ sig = CL RL ′ Rgd Cgd Rgd = R′ sig 1 g + mRL ′ ) R′ L + ( b1 τH τH CgsRgs CgdRgd CLRCL + + = CgsR′ sig Cgd[R′ sig (1 gmRL ′ ) + + RL ′ ] + CLRL ′ + = f H f H 1 2πτH ------------CL fH CL).
But now we can take and into account. Capacitance can be determined as fF The frequency of the output pole can now be determined as MHz An estimate of can now be found from Eq. (9.83): MHz C2 CL C2 C2 Cgd 1 1 gmR′L --------------+ ⎝ ⎠ ⎛ ⎞ 5 1 1 12.5 ----------+ ⎝ ⎠ ⎛ ⎞ 5.4 = = = fPo 1 2π CL C2 + ( )R′ L -------------------------------------= fPo 1 2π 25 5.4 + ( ) 10 15 – 10 103 × × × -----------------------------------------------------------------------------= 523.5 = fH fH 181.9 1 181.9 523.5 -------------⎝ ⎠ ⎛ ⎞ 2 + ----------------------------------- 171.8 = = 736 Chapter 9 Frequency Response It is interesting and useful, however, to note that applying the open-circuit time-constants method to the Miller equivalent circuit shown in Fig. 9.20 results in a very close approxima-tion to the value of in Eq. (9.85).
Figure 9.21 Application of the open-circuit time-constants method to the CS equivalent circuit of Fig. 9.19.
R sig G Rgs (a) (b) R sig G D R L gmVgs Vgs Vx Ix Rgd Vx Ix (c) R sig G D R L V gs 0 0 RCL τH Use the method of open-circuit time constants to obtain another estimate of for the CS amplifier of Example 9.8. Solution k k k fH Rgs R′sig 10 = = Ω Rgd R′sig 1 gmR′ L + ( ) R′L + = 10 1 1.25 10 × + ( ) 10 145 = + = Ω RL ′ 10 = Ω Example 9.9 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 737 9.5.4 Exact Analysis The approximate analysis presented above provides insight regarding the mechanism by which and the extent to which the various capacitances limit the high-frequency gain of the CS amplifier. Nevertheless, given that the circuit of Fig. 9.19 is relatively simple, it is instructive to also perform an exact analysis.8 This is illustrated in Fig. 9.22. A node equa-tion at the drain provides which can be manipulated to the form (9.87) A loop equation at the input yields in which we can substitute for from a node equation at G, to obtain 8 “Exact” only in the sense that we are not making approximations in the circuit-analysis process. The reader is reminded, however, that the high-frequency model itself represents an approximation of the device performance.
sCgd(V gs V o) – = gmV gs + V o R′ L -------sCLV o + V gs V o – gmRL ′ ------------1 s CL Cgd + ( )RL ′ + 1 sCgd gm ⁄ – --------------------------------------------= V′ sig IiR′sig V gs + = Ii Ii sCgsV gs + sCgd V gs − Vo ( ) = V′ sig V gs 1 s Cgs Cgd + ( )R′sig + [ ] sCgdR′sig V o – = Thus, ps and the 3-dB frequency can be estimated at MHz We note that this estimate is considerably lower than both estimates found in Example 9.8.
Which one is closer to the exact value will be determined next.
τH CgsRgs CgdRgd CLRL ′ + + = 20 10 15 – 10 103 × × × 5 10 15 – × 145 103 × 25 10 15 – × 10 103 × × + × + = 1175 = fH fH 1 2π τH -------------- 1 2π 1175 10 12 – × × ------------------------------------------- 135.5 = = 738 Chapter 9 Frequency Response We can now substitute in this equation for from Eq. (9.87) to obtain an equation in and that can be arranged to yield the amplifier gain as (9.88) The transfer function in Eq. (9.88) has a second-order denominator, and thus the amplifier has two poles. Now, since the numerator is of the first order, it follows that one of the two trans-mission zeros is at infinite frequency. This is readily verifiable by noting that as s approaches , approaches zero. The second zero is at (9.89) That is, it is on the positive real axis of the s-plane9 and has a frequency , (9.90) Since is usually large and is usually small, is normally a very high frequency and thus has negligible effect on the value of . It is useful at this point to show a simple method for finding the value of s at which —that is, Figure 9.23 shows the circuit at By definition, and a node equation at D yields Now, since is not zero (why not?), we can divide both sides by to obtain (9.91) Before considering the poles, we should note that in Eq. (9.88), as s goes toward zero, approaches the dc gain , as should be the case. Let’s now take a closer look at the denominator polynomial. First, we observe that the coefficient of the s term is equal to the effective time constant obtained using the open-circuit time-constants method as given by Eq. (9.85). Again, this should have been expected, since it is the basis for the open-circuit Figure 9.22 Analysis of the CS high-frequency equivalent circuit.
9 Because the transmission zero is on the real axis, there is no physical frequency ω at which the trans-mission is actually zero (except ω = ∞).
V sig R sig G D Vgs Vo Cgs gmVgs CL Cgd R L Vo R L sCgsVgs Ii sCLVo sCgd(V gs V o) V gs V o V′ sig V o V′sig ------------- = (gmRL ′ ) 1 s Cgd gm ⁄ ( ) – [ ] – 1 s Cgs Cgd (1 gmRL ′ ) + + [ ] R′sig CL Cgd + ( ) RL ′ + { } s 2 CL Cgd + ( )Cgs CLCgd + [ ] R′sigRL ′ + + ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------∞(V o V′ sig ⁄ ) s sZ gm Cgd --------= = ωZ ωZ = gm Cgd ⁄ gm Cgd f Z f H V o 0 = sZ.
s sZ.
= V o 0 = sZCgdV gs gmV gs = V gs V gs sZ gm Cgd --------= V o V′ sig ⁄ ( gmRL ′) – τH 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 739 time-constants method (Section 9.4). Next, denoting the frequencies of the two poles and , we can express the denominator polynomial D(s) as (9.92) Now, if —that is, the pole at is dominant—we can approximate D(s) as (9.93) Equating the coefficients of the s term in denominator polynomial of Eq. (9.88) to that of the s term in Eq. (9.93) gives (9.94) where the approximation is that involved in Eq. (9.93). Note that the expression in Eq. (9.94) is identical to the value of ωH obtained using open-circuit time constants. Equating the coeffi-cients of s2 in Eqs. (9.88) and (9.93) and using Eq. (9.94) gives the frequency of the second pole: (9.95) Figure 9.23 The CS circuit at s = sZ. The output voltage Vo = 0, enabling us to determine sZ from a node equation at D.
V sig R sig D Vgs Vo 0 Cgs Cgd gmVgs CL R L 0 sZCgd(V gs V o) sZCgdVgs 0 ωP1 ωP2 D s ( ) 1 s ωP1 --------+ ⎝ ⎠ ⎛ ⎞1 s ωP2 --------+ ⎝ ⎠ ⎛ ⎞ = 1 s 1 ωP1 --------1 ωP2 --------+ ⎝ ⎠ ⎛ ⎞ s 2 ωP1ωP2 -----------------+ + = ωP2 ωP1 ωP1 D s ( ) 1 s ωP1 --------s 2 ωP1ωP2 -----------------+ + ωP1 1 [Cgs Cgd (1 gmRL ′ ) + + ] R′sig + CL Cgd + ( )RL ′ -----------------------------------------------------------------------------------------------------ωP2 [Cgs Cgd (1 gmRL ′) + + ] R′sig + CL Cgd + ( )RL ′ CL Cgd + ( )Cgs CLCgd + [ ]RL ′ R′sig -------------------------------------------------------------------------------------------------------= For the CS amplifier considered in Examples 9.8 and 9.9, use the exact transfer function in Eq.
(9.88) to determine the frequencies of the two poles and the zero and hence the 3-dB frequency .
Compare to the approximate values for obtained in Examples 9.8 and 9.9.
fH fH Example 9.10 740 Chapter 9 Frequency Response Example 9.10 continued Solution The frequency of the zero is determined using Eq. (9.90), GHz The frequencies of the two poles, and , are found as the roots of the equation obtained by equating the denominator polynomial of Eq. (9.88) to zero: The result is MHz and GHz Since , , a good estimate for is MHz Finally, we note that the estimate of obtained using Eq. (9.94) is 135.5 MHz, which is about 5.5% lower than the exact value. Thus, the method of open-circuit time constants underestimates by about 5.5%. The estimate from the Miller approximation is 181.9 MHz, which is about 27% higher than the exact value, and that using the refined application of Miller theorem is 171.8 MHz, which is about 20% higher than the exact value. We conclude that the estimate obtained using open-circuit time constants is remarkably good!
fZ gm 2πCgd --------------- 1.25 10 3 – × 2π 5 10 15 – × × ---------------------------------- 40 = = = ωP1 ωP2 1 1.175 10 9 – × s 7.25 10 20 – × s2 0 = + + fP1 143.4 = fP2 2.44 = fZ fP2 fP1 fH fH fP1 143.4 = fP1 fH 9.16 For the CS amplifier in Example 9.10, using the value of determined by the exact analysis, find the gain–bandwidth product. Recall that gm = 1.25 mA/V and = 10 kΩ. Also, convince yourself that this is the frequency at which the gain magnitude reduces to unity, that is, Ans. GBW = 1.79 GHz; since this is lower than , then GHz 9.17 As a way to trade gain for bandwidth, the designer of the CS amplifier in Example 9.10 connects a load resistor at the output that results in halving the value of . Find the new values of , (using of Eq. 9.94), and .
Ans. 6.25 V/V; 223 MHz; 1.4 GHz 9.18 As another way to trade dc gain for bandwidth, the designer of the CS amplifier in Example 9.10 decides to operate the amplifying transistor at double the value of by increasing the bias cur-rent fourfold. Find the new values of , , , , , and . Assume that is the parallel equivalent of ro of the amplifying transistor and that of the current-source load. Use the approximate formula for given in Eq. (9.94).
Ans. 2.5 mA/V; 2.5 kΩ; 6.25 V/V; 250 MHz; 250 MHz; 1.56 GHz f H RL ′ ft.
f P2 ft = 1.79 RL ′ AM fH f H f P1 ft V OV gm RL ′ AM f P1 f H f t RL ′ f P1 EXERCISES 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 741 9.5.5 Adapting the Formulas for the Case of the CE Amplifier Adapting the formulas presented above to the case of the CE amplifier is straightforward.
First, note from Fig. 9.24 how and relate to Vsig, Rsig, and the other equivalent-circuit parameters: (9.96) (9.97) Thus the dc gain is now given by (9.98) Using the Miller approximation, we obtain (9.99) Correspondingly, the 3-dB frequency can be estimated from (9.100) Figure 9.24 (a) High-frequency equivalent circuit of the common-emitter amplifier. (b) Equivalent circuit obtained after Thévenin theorem has been employed to simplify the resistive circuit at the input.
V′ sig R′sig Vsig ′ = V sig rπ Rsig rx rπ + + -----------------------------Rsig ′ rπ Rsig rx + ( ) || = AM rπ Rsig rx rπ + + -----------------------------(gmRL ′ ) – = Cin Cπ Cμ(1 gmRL ′) + + = f H f H 1 2πCinRsig ′ -----------------------(a) Vsig rx C B B Rsig V Vo C C gmV CL ro RL r R L (b) V sig B R sig V Vo C C gmV CL R L 742 Chapter 9 Frequency Response Alternatively, using the method of open-circuit time constants yields (9.101) from which can be estimated as (9.102) The exact analysis yields the following zero frequency: (9.103) and, assuming that a dominant pole exists, (9.104) (9.105) For , , 9.5.6 The Situation When Rsig Is Low There are applications in which the CS amplifier is fed with a low-resistance signal source.
Obviously, in such a case, the high-frequency gain will no longer be limited by the interac-tion of the source resistance and the input capacitance. Rather, the high-frequency limitation happens at the amplifier output, as we shall now show. Figure 9.25(a) shows the high-frequency equivalent circuit of the common-source amplifier in the limiting case when is zero. The voltage transfer function can be τH CπRπ CμRμ CLRCL + + = CπRsig ′ + Cμ[ 1 + gmRL ′ ( )Rsig ′ + RL ′ ] + CLRL ′ = f H f H 1 2πτH ------------fZ 1 2π ------ gm Cμ ------= f P1 1 2π ------1 Cπ Cμ (1 gm RL ′ ) + + [ ]Rsig + ′ CL Cμ + ( )RL ′ -----------------------------------------------------------------------------------------------fP2 1 2π ------[Cπ Cμ (1 gmRL ′ ) + + ] Rsig + ′ CL Cμ + ( )RL ′ Cπ CL Cμ + ( ) CLCμ + [ ]Rsig ′ RL ′ ------------------------------------------------------------------------------------------------fZ f P2 fP1 fH fP1 Rsig V o V sig ⁄ = V o V gs ⁄ 9.19 Consider a bipolar active-loaded CE amplifier having the load current source implemented with a pnp transistor. Let the circuit be operating at a 1-mA bias current. The transistors are specified as follows: , , , , , , and . The amplifier is fed with a signal source having a resistance of 36 . Determine: (a) ; (b) and using the Miller approximation; (c) using open-circuit time constants; (d) , , , and hence (use the approximate expressions in Eqs. 9.105 and 9.104); and (e) the gain–bandwidth product.
Ans. (a) ; (b) 448 pF, 82.6 kHz; (c) 75.1 kHz; (d) 21.2 GHz, 75.1 kHz, 25.2 MHz, 75.1 kHz; (e) 13.1 MHz β npn ( ) 200 = V An 130 V = VAp 50 V = Cπ 16 pF = Cμ 0.3 pF = CL 5 pF = rx 200 Ω = kΩ AM Cin f H fH fZ fP1 fP2 f H 175 V/V – EXERCISE 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 743 found by setting in Eq. (9.88). The result is (9.106) Thus, while the dc gain and the frequency of the zero do not change, the high-frequency response is now determined by a pole formed by together with . Thus the 3-dB Figure 9.25 (a) High-frequency equivalent circuit of a CS amplifier fed with a signal source having a very low (effectively zero) resistance. (b) The circuit with Vsig reduced to zero. (c) Bode plot for the gain of the circuit in (a).
(a) Vsig D G Vgs Vo Cgs Cgd gmVgs CL ro RL R L (b) Vgs 0 Cgs 0 Cgd CL R L (c) 20 dBdecade 0 f (log scale) 2(CL Cgd) gm 2Cgd gm 20 log AM ft AM f3dB fH fZ Gain (dB) 2 (CL Cgd)R L 1 1 Rsig 0 = Vo Vsig -------- ( gmRL ′ – ) 1 s Cgd gm ⁄ ( ) – [ ] 1 s CL Cgd + ( )RL ′ + -------------------------------------------------------------= CL Cgd + RL ′ 744 Chapter 9 Frequency Response frequency is now given by (9.107) To see how this pole is formed, refer to Fig. 9.25(b), which shows the equivalent circuit with the input signal source reduced to zero. Observe that the circuit reduces to a capacitance in parallel with a resistance .
As we have seen above, the transfer-function zero is usually at a very high frequency and thus does not play a significant role in shaping the high-frequency response. The gain of the CS amplifier will therefore fall off at a rate of –6 dB/octave (–20 dB/decade), reaching unity (0 dB) at a frequency , which is equal to the gain–bandwidth product, Thus, (9.108) Figure 9.25(c) shows a sketch of the high-frequency gain of the CS amplifier.
fH 1 2π CL Cgd + ( )RL ′ ---------------------------------------= CL Cgd + ( ) RL ′ ft f t AM fH = gmRL ′ 1 2π CL Cgd + ( )RL ′ ---------------------------------------= f t gm 2π CL Cgd + ( ) --------------------------------= Consider the CS amplifier specified in Example 9.8 when fed with a signal source having a negligi-ble resistance (i.e., Find , , , and . If the amplifying transistor is to be oper-ated at twice the original overdrive voltage while W and L remain unchanged, by what factor must the bias current be changed? What are the new values of , , , and ? Assume that is the parallel equivalent of ro of the amplifying transistor and that of the current-source load.
Solution In Example 9.8 we found that The 3-dB frequency can be found using Eq. (9.107), = 530.5 MHz and the unity-gain frequency, which is equal to the gain–bandwidth product, can be determined as Rsig 0).
= AM f3dB ft fZ AM f3dB ft fZ RL ′ AM gmRL ′ – = 12.5 V/V – = f H 1 2π CL Cgd + ( )RL ′ ----------------------------------------= 1 2π 25 5 + ( ) 10 15 – 10 103 × × × --------------------------------------------------------------------------= ft AM fH = 12.5 530.5 6.63 GHz = × = Example 9.11 9.5 A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 745 EXAMPLE 9.11 The frequency of the zero is Now, to double , must be quadrupled. The new values of and can be found as follows: Thus the new value of becomes That of becomes and the unity-gain frequency (i.e., the gain–bandwidth product) becomes We note that doubling results in reducing the dc gain by a factor of 2 and increasing the bandwidth by a factor of 4. Thus, the gain–bandwidth product is doubled—a good bargain!
fZ 1 2π ------ gm Cgd --------= = 1 2π ------ 1.25 10 3 – × 5 10 15 – × --------------------------- 40 GHz V OV ID gm RL ′ gm ID V OV 2 ⁄ ---------------- 2.5 mA/V = = RL ′ 1 4 ---10 × 2.5kΩ = = AM AM gmRL ′ 2.5 2.5 6.25 V/V – = × – = – = f H f H 1 2π CL Cgd + ( )RL ′ ----------------------------------------= 1 2π 25 5 + ( ) 10 15 – 2.5 103 × × × --------------------------------------------------------------------------= 2.12 GHz = f t 6.25 2.12 13.3 GHz = × = VOV 9.20 For the CS amplifier considered in Example 9.11 operating at the original values of and , find the value to which should be increased to place at 2 GHz.
Ans. 94.4 fF 9.21 Show that the CS amplifier when fed with has a transfer-function zero whose frequency is related to by V OV ID CL f t Rsig 0 = f t f Z ft ---- 1 CL Cgd --------+ = EXERCISES 746 Chapter 9 Frequency Response 9.6 High-Frequency Response of the Common-Gate and Cascode Amplifiers Although common-source and common-emitter amplifiers provide substantial gain at mid-band frequencies, their gain falls off in the high-frequency band at a relatively low fre-quency. This is primarily due to the large input capacitance , whose value is significantly increased by the Miller component. The latter is large because of the Miller multiplication effect. It follows that the key to obtaining wideband operation, that is, high , is to use cir-cuit configurations that do not suffer from the Miller effect. One such configuration is the common-gate circuit.
9.6.1 High-Frequency Response of the CG Amplifier Figure 9.26(a) shows the CG amplifier with the MOSFET internal capacitances and indicated. For generality, a capacitance is included at the output node to represent the combination of the output capacitance of a current-source load and the input capacitance of a succeeding amplifier stage. Capacitance also includes the MOSFET capacitance .
Note the appears in effect in parallel with ; therefore, in the following discussion we will lump the two capacitances together.
It is important to note at the outset that each of the three capacitances in the circuit of Fig. 9.26(a) has a grounded node. Therefore none of the capacitances undergoes the Miller multiplication effect observed in the CS stage. It follows that the CG circuit can be designed to have a much wider bandwidth than that of the CS circuit, especially when the resistance of the signal generator is large.
Analysis of the circuit in Fig. 9.26(a) is greatly simplified if can be neglected. In such a case the input side is isolated from the output side, and the high-frequency equivalent circuit takes the form shown in Fig. 9.26(b). We immediately observe that there are two poles: one at the input side with a frequency (9.109) and the other at the output side with a frequency , (9.110) The relative locations of the two poles will depend on the specific situation. However, is usually lower than ; thus can be dominant. The important point to note is that both and are usually much higher than the frequency of the dominant input pole in the CS stage.
In IC amplifiers, has to be taken into account. In these cases, the method of open-circuit time constants can be employed to obtain an estimate for the 3-dB frequency . Figure 9.27 shows the circuits for determining the resistances and seen by and (Cgd + CL), respectively. By inspection we obtain (9.111) and (9.112) Cin fH Cgs Cgd CL CL Cdb CL Cgd ro f P1, f P1 1 2πCgs Rsig 1 gm -----|| ⎝ ⎠ ⎛ ⎞ -----------------------------------------= f P2 f P2 1 2π Cgd CL + ( )RL --------------------------------------= f P2 f P1 f P2 f P1 f P2 ro f H Rgs Rgd Cgs Rgs Rsig Rin || = Rgd RL Ro || = 9.6 High-Frequency Response of the Common-Gate and Cascode Amplifiers 747 Figure 9.26 (a) The common-gate amplifier with the transistor internal capacitances shown. A load capacitance CL is also included. (b) Equivalent circuit for the case in which ro is neglected.
Figure 9.27 Circuits for determining Rgs and Rgd.
(a) ro RL Vi Vsig Cgd CL Cgs Rsig S D gmVi Vo 1 gm (b) Vsig Rsig Vi S Cgs gm 1 D RL gmVi Vo (CL Cgd) (a) ro RL S Rsig Rin Rgs (b) ro RL D Rsig Rgd Ro 748 Chapter 9 Frequency Response which can be used to obtain , (9.113) Finally note that the input resistance and output resistance of the CG amplifier were derived in Section 7.3 and are summarized in Fig. 7.13, from which we obtain (9.114) and (9.115) f H f H 1 2π CgsRgs Cgd CL + ( )Rgd + [ ] ------------------------------------------------------------------= Rin Ro Rin ro R + L 1 g + mro --------------------= Ro ro Rsig gmro ( )Rsig + + = Consider a common-gate amplifier with mA/V, k , fF, Cgd = 5 fF, fF, k , and k . Assume that includes . Determine the input resistance, the midband gain, and the upper 3-dB frequency .
Solution Figure 9.28 shows the CG amplifier circuit at midband frequencies. We note that Thus, the overall voltage gain is given by Figure 9.28 The CG amplifier circuit at midband.
gm = 1.25 ro = 20 Ω Cgs = 20 CL = 15 Rsig = 10 Ω RL = 20 Ω CL Cdb fH vo iRL = vsig i Rsig Rin + ( ) = Gv vo vsig ------- RL Rsig Rin + ----------------------= = Rin RL i vsig Rsig i vo ro Example 9.12 9.6 High-Frequency Response of the Common-Gate and Cascode Amplifiers 749 The value of Rin is found from Eq. (9.114) as k Thus, can now be determined as V/V Observe that as expected Gv is very low. This is due to the low input resistance of the CG amplifier. To obtain an estimate of the 3-dB frequency fH, we first determine Rgs and Rgd using Eqs.
(9.111) and (9.112), k where Ro is given by Eq. (9.115), k Thus, k Now we can compute the sum of the open-circuit time constants, , ps and the upper 3-dB frequency can be obtained as MHz Observe that fH is indeed much higher (more than twice) the corresponding value for the CS ampli-fier found in Example 9.9. Another important observation can be made by examining the two com-ponents of : The contribution of the input circuit is 26.6 ps, while that of the output circuit is 374 ps; thus the limitation on the high-frequency response is posed by the output circuit.
Rin ro R + L 1 g + mro --------------------= 20 20 + 1 1.25 20 × ( ) + ------------------------------------- 1.54 = = Ω Gv Gv 20 10 1.54 + ----------------------1.73 = = Rgs Rsig Rin 10 1.54 1.33 = || = || = Ω Rgd RL Ro || = Ro ro Rsig gmro ( )Rsig + + = 20 10 25 10 × + + 280 = = Ω Rgd 20 280 18.7 = || = Ω τH τH CgsRgs Cgd CL + ( )Rgd + = τΗ 20 10 15 – × 1.33 103 × × 5 15 + ( ) 10 15 – × 18.7 103 × × + = 26.6 10 12 – × = 374 10 × 12 – + 400.6 = fH fΗ 1 2πτΗ − − − − − − − 1 2π 400.6 10 12 – × × − − − − − − − − − − − − − − − − − − − − − − − − − − − − 397.3 = = = τH 750 Chapter 9 Frequency Response We conclude this section by noting that a properly designed CG circuit can have a wide bandwidth. However, the input resistance will be low and the overall midband gain can be very low. It follows that the CG circuit alone will not do the job! However, combining the CG with the CS amplifier in the cascode configuration can result in a circuit having the high input resistance and gain of the CS amplifier together with the wide bandwidth of the CG amplifier, as we shall now see.
9.6.2 High-Frequency Response of the MOS Cascode Amplifier In Section 7.3 we studied the cascode amplifier and analyzed its performance at midband frequencies. There we learned that by combining the CS and CG configurations, the cascode amplifier exhibits a very high input resistance and a voltage gain that can be as high as , where is the intrinsic gain of the MOSFET. For our purposes here, we shall see that the versatility of the cascode circuit allows us to trade off some of this high midband gain in return for a wider bandwidth.
Figure 9.29 shows the cascode amplifier with all transistor internal capacitances indi-cated. Also included is a capacitance CL at the output node to represent the combination of Cdb2, the output capacitance of a current-source load, and the input capacitance of a succeeding A0 2 A0 gmro = Q2 D2 Vo CL Cdb1 Cgd2 Cgs2 Q1 G1 D1 Cgd1 Cgs1 RL Vi Vsig Rsig Figure 9.29 The cascode circuit with the various transistor capacitances indicated.
9.22 In order to raise the midband gain of the CG amplifier in Example 9.12, the circuit designer decides to use a cascode current source for the load device, thus raising by a factor of ; that is, becomes 500 k . Find , the midband gain, and . Comment on the results.
Ans. 20 k ; 16.7 V/V; 42.7 MHz. While the midband gain has been increased substantially (by a factor of 9.7), the bandwidth has been substantially lowered (by a factor of about 9.3). Thus, the high-frequency advantage of the CG amplifier is completely lost!
RL gmro 25 = RL Ω Rin fH Ω fH EXERCISE 9.6 High-Frequency Response of the Common-Gate and Cascode Amplifiers 751 amplifier stage (if any). Note that and appear in parallel, and we shall combine them in the following analysis. Similarly, CL and Cgd2 appear in parallel and will be com-bined.
The easiest and, in fact, quite insightful approach to determining the 3-dB frequency fH is to employ the open-circuit time-constants method: 1. Capacitance sees a resistance .
2. Capacitance sees a resistance , which can be obtained by adapting the for-mula in Eq. (9.84) to (9.116) where , the total resistance at , is given by (9.117) 3. Capacitance sees a resistance . 4. Capacitance sees a resistance where Ro is given by With the resistances determined, the effective time constant can be computed as (9.118) and the 3-dB frequency f H as To gain insight regarding what limits the high-frequency gain of the MOS cascode ampli-fier, we rewrite Eq. (9.118) in the form (9.119) In the case of a large , the first term can dominate, especially if the Miller multiplier is large. This in turn happens when the load resistance is large (on the order of ), causing to be large and requiring the first stage, , to provide a large proportion of the gain (see Section 7.3.3). It follows that when Rsig is large, to extend the bandwidth we have to lower RL to the order of . This in turn lowers and hence and renders the Miller effect in Q1 insignificant. Note, however, that the dc gain of the cas-code will then be . Thus, while the dc gain will be the same as (or a little higher than) that achieved in a CS amplifier, the bandwidth will be greater. In the case when Rsig is small, the Miller effect in will not be of concern. A large value of (on the order of ) can then be used to realize the large dc gain possible with a cascode amplifier—that is, a dc gain on the order of . Equation (9.119) indicates that in this case the third term will usually be dominant. To pursue this point a little further, con-sider the case and assume that the middle term is much smaller than the third term.
It follows that Cdb1 Cgs2 Cgs1 Rsig Cgd1 Rgd1 Rgd1 1 gm1Rd1 + ( )Rsig Rd1 + = Rd1 D1 Rd1 ro1 = Rin2 || ro1 ro2 RL + gm2ro2 ------------------|| = Cdb1 Cgs2 + ( ) Rd1 CL Cgd2 + ( ) RL Ro || ( ) Ro ro2 ro1 gm2ro2 ( )ro1 + + = τH τH Cgs1Rsig Cgd1 1 gm1Rd1 + ( )Rsig Rd1 + [ ] + = Cdb1 Cgs2 + ( )Rd1 CL Cgd2 + ( ) RL Ro || ( ) + + fH 1 2πτH ------------τH Rsig Cgs1 Cgd1 1 gm1Rd1 + ( ) + [ ] + Rd1 Cgd1 Cdb1 Cgs2 + + ( ) = RL Ro || ( ) CL Cgd2 + ( ) + Rsig 1 gm1Rd1 + ( ) RL A0ro Rin2 Q1 ro Rin2 Rd1 A0 Q1 RL A0ro A0 2 Rsig 0, = τH CL Cgd2 + ( ) RL Ro || ( ) 752 Chapter 9 Frequency Response and the 3-dB frequency becomes (9.120) which is of the same form as the formula for the CS amplifier with (Eq. 9.107).
Here, however, is larger that by a factor of about . Thus the of the cas-code will be lower than that of the CS amplifier by the same factor . Figure 9.30 shows a sketch of the frequency response of the cascode and of the corresponding common-source amplifier. We observe that in this case, cascoding increases the dc gain by a factor A0 while keeping the unity-gain frequency unchanged at (9.121) Figure 9.30 Effect of cascoding on gain and bandwidth in the case Rsig = 0. Cascoding can increase the dc gain by the factor A0 while keeping the unity-gain frequency constant. Note that to achieve the high gain, the load resistance must be increased by the factor A0.
fH 1 2π CL Cgd2 + ( ) RL Ro || ( ) --------------------------------------------------------= Rsig 0 = RL Ro || ( ) RL ′ A0 f H A0 f t 1 2π ------gm CL Cgd2 + ----------------------A0 A0gmR L gmR L f3dBcascode f3dBCS ft f (log scale) Gain (dB) A0 0 Cascode CS Vi ro RL R L RL ro Vo CL Vi A0ro A0RL Vo CL Common Source Circuit DC Gain f3dB ft gmR L A0gmR L Cascode 1 2(CL Cgd)R L gm 2(CL Cgd) 1 2(CL Cgd)A0R L gm 2(CL Cgd) 9.6 High-Frequency Response of the Common-Gate and Cascode Amplifiers 753 This example illustrates the advantages of cascoding by comparing the performance of a cascode amplifier with that of a common-source amplifier in two cases: (a) The resistance of the signal source is significant, .
(b) is negligibly small.
Assume all MOSFETs have , , , Cgd = 5 fF, , and (excluding ) = 10 fF. For case (a), let for both amplifiers. For case (b), let for the CS amplifier and for the cascode amplifier. For all cases, determine , , and .
Solution (a) For the CS amplifier: where Thus, For the cascode amplifier: k V/V k k Rsig 10 kΩ = Rsig gm = 1.25 mA/V ro 20 kΩ = Cgs 20 fF = Cdb 5 fF = CL Cdb RL ro 20 kΩ = = RL ro 20 kΩ = = RL Ro = Av fH f t A0 gmro 1.25 20 25 V/V = × = = Av gm RL ro || ( ) gm ro ro || ( ) – = – = 1 2 ---A0 12.5 V/V – = – = τH CgsRsig Cgd (1 gmRL ′ + )Rsig + RL ′ [ ] + CL Cdb + ( )RL ′ + = RL ′ ro RL ro ro 10 kΩ = || = || = τH 20 10 5 1 12.5 + ( )10 10 + [ ] + × 10 5 + ( )10 + = 200 725 150 1075 ps = + + = f H 1 2π × 1075 10 12 – × -------------------------------------------- 148 MHz = = ft Av fH 12.5 148 1.85 GHz = × = = Ro 2ro gmro ( )ro = 2 20 × ( ) 25 20 × ( ) + + = 540 = Ω Av gm Rο RL || ( ) – = 1.25 540 20 || ( ) 24.1 – = – = Rin2 ro RL + gmro ----------------- ro ro + gmro --------------- 2 gm ------ 2 1.25 ---------- 1.6 = = = = = Ω Rd1 ro Rin2 20 1.6 1.48 = || = || = Ω τH Rsig = Cgs1 Cgd1 1 gm1Rd1 + ( ) + [ ] R + d1 Cgd1 Cdb1 Cgs2 + + ( ) RL Ro || ( ) CL Cdb2 Cgd2 + + ( ) + Example 9.13 754 Chapter 9 Frequency Response Example 9.13 continued ps MHz GHz Thus cascoding has increased by a factor of 2.7.
(b) For the CS amplifier: For the cascode amplifier: k V/V k k ps MHz GHz Thus cascoding increases the dc gain from 12.5 V/V to 337.5 V/V. The unity-gain frequency (which, in this case, is equal to the gain–bandwidth product), however, remains nearly constant.
10 20 5 1 1.25 1.48 × + ( ) + [ ] = 1.48 5 5 20 + + ( ) + 20 540 || ( ) 10 5 5 + + ( ) + 342.5 44.4 385.7 + + = 772.6 = fH 1 2π 772.6 10 12 – × × --------------------------------------------- 206 = = ft 24.1 206 4.96 = × = ft Av 12.5 V/V – = τH Cgd CL Cdb + + ( )RL ′ = 5 10 5 + + ( )10 = 200 ps = fH 1 2π 200 10 12 – × × ---------------------------------------- = 796 MHz = ft 12.5 796 = 9.95 GHz × = RL Ro = 540 = Ω Av gm Ro RL || ( ) – = 1.25 540 540 || ( ) 337.5 – = – = Rin2 ro RL + gmro ----------------- 20 540 + 1.25 20 × ---------------------- 22.4 = = = Ω Rd1 ro1 Rin2 20 22.4 10.6 = || = || = Ω τH Rd1 = Cgd1 Cdb1 C + gs2 + ( ) RL Ro || ( ) CL Cgd2 Cdb2 + + ( ) + 10.6 5 5 20 + + ( ) 540 540 || ( ) 10 5 5 + + ( ) + = 318 5400 5718 = + = fH 1 2π 5718 10 12 – × × ------------------------------------------- 27.8 = = ft 337.5 27.8 9.39 = × = 9.6 High-Frequency Response of the Common-Gate and Cascode Amplifiers 755 9.6.3 High-Frequency Response of the Bipolar Cascode Amplifier The analysis method studied in the previous section can be directly applied to the BJT cas-code amplifier. Figure 9.31 presents the circuits and the formulas for determining the high-frequency response of the bipolar cascode.
Figure 9.31 Determining the frequency response of the BJT cascode amplifier. Note that in addition to the BJT capacitances Cπ and Cμ, the capacitance between the collector and the substrate Ccs for each transistor are included.
R sig r1 (rx1 Rsig) R1 R sig(1 gm1Rc1) Rc1 H C1R1 C1R1 (Ccs1 C2)Rc1 (CL Ccs2 C2)(RL Ro) R1 R sig Ro 2ro2 Rc1 ro1 re2 ro2 RL ro2 RL(2 1) fH 1 2H gm(ro RL) AM r r rx Rsig C2 Vo CL Ccs2 Ccs1 C2 C2 C1 C1 C1 RL V1 Vsig Rsig Q2 Q1 9.23 In this exercise we wish to contrast the gain of a CS amplifier and a cascode amplifier. Assume that both are fed with a large source resistance Rsig that effectively determines the high-frequency re-sponse. Thus, neglect components of τH that do not include Rsig. Also assume that all transistors are operated at the same conditions and thus corresponding small-signal parameters are equal. Also, both amplifiers have equal RL = ro, and gmro = 40.
(a) Find the ratio of the low-frequency gain of the cascode amplifier to that of the CS amplifier.
(b) For the case of , find the ratio of fH of the cascode to that of the CS amplifier.
(c) Use (a) and (b) to find the ratio of of the cascode to that of the CS.
Ans. 2; 3.6; 7.2 Cgd 0.25Cgs = ft EXERCISE 756 Chapter 9 Frequency Response 9.7 High-Frequency Response of the Source and Emitter Followers In this section we study the high-frequency response of two important circuit building blocks: the source follower and the emitter follower. Both have voltage gain that is less than but close to unity. Their advantage lies in their high input resistance and low output resis-tance. They find application as the output stage of a multistage amplifier. As we will see shortly, both exhibit wide bandwidth.
9.7.1 The Source Follower A major advantage of the source follower is its excellent high-frequency response. This comes about because, as we shall now see, none of the internal capacitances suffers from the Miller effect. Figure 9.32(a) shows the high-frequency equivalent circuit of a source follower fed with a signal from a source having a resistance In addition to the MOSFET capacitances and a capacitance is included between the output node and ground to account for the source-to-body capacitance as well as any actual load capacitance.
To obtain the low-frequency gain AM and the output resistance Ro, we set all capacitances to zero. The results are (9.122) (9.123) Combining RL and ro into a single resistance we can redraw the circuit in the simplified from shown in Fig. 9.32(b). Although one can derive the transfer function of this circuit, the resulting expression will be too complicated to yield insight regarding the role that each of the three capacitances plays. Rather, we shall first determine the location of the transmission zeros and then use the method of open-circuit time constants to estimate the 3-dB frequency, Although there are three capacitances in the circuit of Fig. 9.32(b), the transfer function is of the second order. This is because the three capacitances form a continuous loop. To deter-mine the location of the two transmission zeros, refer to the circuit in Fig. 9.32(b), and note that is zero at the frequency at which has a zero impedance and thus acts as a short cir-cuit across the output, which is ω or Also, Vo will be zero at the value of s that causes V sig Rsig.
Cgs Cgd, CL Csb AM RL ro || ( ) RL ro || ( ) 1 gm ⁄ ( ) + ---------------------------------------------= Ro 1 gm ------ro || = R ′L, f3dB.
V o CL s ∞.
= 9.24 The objective of this exercise is to evaluate the effect of cascoding on the performance of the CE am-plifier of Exercise 9.19. The specifications are as follows: I = 1 mA, , , , , , , , , . Find , , , , , , , and . Compare , , and with the correspond-ing values obtained in Exercise 9.19 for the CE amplifier. What should be reduced to in order to have ?
Ans. 5.2 kΩ; 5200 V/V; 130 kΩ; 35 Ω; 26 MΩ; ; 469 kHz; 111.6 MHz. has in-creased from 175 V/V to 238 V/V; has increased from 75 kHz to 469 kHz; has increased from 13.1 MHz to 111.6 MHz. must be reduced to 1.6 pF.
β 200 = ro 130 kΩ = Cπ = 16 pF Cμ 0.3 pF = rx 200 Ω = Ccs1 Ccs2 0 = = CL 5 pF = Rsig 36 kΩ = RL = 50 kΩ Rin A0 Ro1 Rin2 Ro AM f H ft AM fH ft CL f H 1 MHz = 238 V/V – AM f H ft CL EXERCISE 9.7 High-Frequency Response of the Source and Emitter Followers 757 the current into the impedance to be zero. Since this current is Vgs, the transmission zero will be at , where (9.124) That is, the zero will be on the negative real axis of the s-plane with a frequency (9.125) Recalling that the MOSFET’s and that , we see that will be very close to , (9.126) Since the zero is at such a high frequency, we can employ the method of open-circuit time constants to obtain an estimate of fH. Specifically, we will find the resistance seen by each of three capacitances , , and and then compute the time constant associated with each. With set to zero and and assumed to be open circuited, we find by inspection that the resistance seen by is given by (9.127) Figure 9.32 Analysis of the high-frequency response of the source follower: (a) equivalent circuit; (b) simplified equivalent circuit; (c) determining the resistance Rgs seen by Cgs.
(a) Vsig Rsig S G D gmVgs ro RL CL Vgs Cgs Cgd Vo (b) Vsig Rsig D G S gmVgs R L R L = RLrO CL Cgd Vgs Cgs Vo (c) Rsig Rgs G gmVgs R L Vgs Ix Ix Vgs Ix S RL ′ CL || gm sCgs + ( ) s sZ = sZ gm Cgs -------– = ωZ gm Cgs -------= ωT gm Cgs Cgd + ( ) ⁄ = Cgd Cgs ωZ ωT fZ fT Cgd Cgs CL V sig Cgs CL Rgd Cgd Rgd Rsig = 758 Chapter 9 Frequency Response Next, we consider the effect of . The resistance seen by can be determined by straightforward analysis of the circuit in Fig. 9.32(c) to obtain (9.128) We note that the factor in the denominator will result in reducing the effective resistance with which interacts.
Finally, it is easy to see from the circuit in Fig. 9.32(b) that interacts with ; that is, which is usually low because of 1/gm. Thus the effect of will be small. Adding all three time constants, we obtain and hence , (9.129) 9.7.2 The Emitter Follower Figure 9.33(a) shows an emitter follower suitable for IC fabrication. It is biased by a constant-current source I. However, the circuit that sets the dc voltage at the base is not shown. The emitter follower is fed with a signal from a source with resistance .
The resistance , shown at the output, includes the output resistance of current source I as well as any actual load resistance. Analysis of the emitter follower of Fig. 9.32(a) to determine its low-frequency gain, input resistance, and output resistance is identical to that performed in Section 6.6.6. We shall concentrate here on the analysis of the high-frequency response of the circuit.
Figure 9.33(b) shows the high-frequency equivalent circuit. Lumping together with and together with and making a slight change in the way the circuit is drawn results in the simplified equivalent circuit shown in Fig. 9.33(c). We will follow a procedure for the analysis of this circuit similar to that used above for the source follower. Specifically, to obtain the location of the transmission zero, note that will be zero at the frequency for which the current fed to is zero: Cgs Rgs Cgs Rgs Rsig RL ′ + 1 gmRL ′ + ----------------------= (1 gmRL ′ ) + Cgs CL RL ′ 1 gm ⁄ || RCL RL ro 1 gm -----|| || = CL τH f H fH 1 2πτH ------------ 1 2π ⁄ (Cgd Rsig Cgs Rgs CLRCL) + + = = V sig Rsig RL ro RL, rx Rsig V o sZ RL ′ gmVπ Vπ rπ -----sZCπVπ = 0 + + 9.25 Consider a source follower specified as follows: mA/V, , , , fF, fF, and fF. Find , , and . Also, find , , , and hence the time constant associated with each of the three capacitances , , and . Find and the percentage contribution to it from each of three capacitances. Find .
Ans. 0.93 V/V; 8 GHz; 10 GHz; 10 kΩ; 1.48 kΩ; 0.74 kΩ; 50 ps; 30 ps; 11 ps; 91 ps; 55%; 33%; 12%; 1.75 GHz gm 1.25 = ro 20 kΩ = Rsig 10 kΩ = RL 20 kΩ = Cgs 20 = Cgd 5 = CL 15 = AM fT f Z Rgd Rgs RCL Cgd Cgs CL τH f H EXERCISE 9.7 High-Frequency Response of the Source and Emitter Followers 759 Thus, (9.130) which is on the negative real-axis of the s-plane and has a frequency (9.131) This frequency is very close to the unity-gain frequency of the transistor. The other trans-mission zero is at . This is because at this frequency, acts as a short circuit, making zero, and hence will be zero.
Next, we determine the resistances seen by and . For the reader should be able to show that the resistance it sees, , is the parallel equivalent of and the input resistance looking into that is, (9.132) Equation (9.132) indicates that , and since is usually very small, the time constant will be correspondingly small.
Figure 9.33 (a) Emitter follower. (b) High-frequency equivalent circuit. (c) Simplified equivalent circuit.
(a) VCC I RL Vo Vsig Rsig (c) Vsig R sig R sig Rsig rx R L RL ro B C R L r C V gmV Vo (b) Vsig Rsig C E B B rx V Vo C C gmV ro r RL sZ = gm 1 rπ ⁄ ( ) + Cπ ---------------------------- = 1 Cπ re -----------– – ωZ = 1 Cπ re -----------ωT s = ∞ Cμ V π V o Cμ Cπ Cμ Rμ Rsig ′ B′; Rμ = Rsig ′ [rπ β 1 + ( )RL ′] + || Rμ will be smaller than Rsig ′ Cμ CμRμ 760 Chapter 9 Frequency Response The resistance seen by can be determined using an analysis similar to that employed for the determination of in the MOSFET case. The result is (9.133) We observe that the term will usually make the denominator much greater than unity, thus rendering rather low. Thus, the time constant will be small. The end result is that the 3-dB frequency of the emitter follower, (9.134) will usually be very high. We urge the reader to solve the following exercise to gain familiarity with typical values of the various parameters that determine .
9.8 High-Frequency Response of Differential Amplifiers In this section we study the high-frequency response of the differential amplifier. We will consider the variation with frequency of both the differential gain and the common-mode gain and hence of the CMRR. We will rely heavily on the study of frequency response of single-ended amplifiers presented in the sections above. Also, we will only consider MOS circuits; the bipolar case is a straightforward extension, as we saw above on a number of occasions.
9.8.1 Analysis of the Resistively Loaded MOS Amplifier We begin with the basic, resistively loaded MOS differential pair shown in Fig. 9.34(a).
Note that we have explicitly shown transistor QS that supplies the bias current I. Although we are showing a dc bias voltage VBIAS at its gate, usually QS is part of a current mirror. This detail, however, is of no consequence to our present needs. Most importantly, we are inter-ested in the total impedance between node S and ground, ZSS. As we shall shortly see, this impedance plays a significant role in determining the common-mode gain and the CMRR of the differential amplifier. Resistance RSS is simply the output resistance of current source QS.
Capacitance CSS is the total capacitance between node S and ground and includes Cdb and Cgd of QS, as well as Csb1, and Csb2. This capacitance can be significant, especially if wide transistors are used for QS, Q1, and Q2.
Rπ Cπ Rgs Rπ = Rsig ′ + RL ′ 1 Rsig ′ rπ --------RL ′ re ------+ + -------------------------------RL ′ re ⁄ Rπ Cπ Rπ fH fH 1 2π CμRμ CπRπ + [ ] ⁄ = fH 9.26 For an emitter follower biased at mA and having , , , pF, and MHz, find the low-frequency gain, , and .
Ans. 0.965 V/V; 458 MHz; 1.09 kΩ; 51 Ω; 55 MHz IC = 1 Rsig = RL = 1 kΩ ro = 100 kΩ β = 100 Cμ = 2 fT = 400 fZ, Rμ, Rπ f H EXERCISE 9.8 High-Frequency Response of Differential Amplifiers 761 The differential half-circuit shown in Fig. 9.34(b) can be used to determine the frequency dependence of the differential gain Indeed the gain function Ad(s) of the differential amplifier will be identical to the transfer function of this common-source amplifier. We studied the frequency response of the common-source amplifier at great length in Sections 9.3 and 9.5 and will not repeat this material here.
Figure 9.34 (a) A resistively loaded MOS differential pair; the transistor supplying the bias current is explicitly shown. It is assumed that the total impedance between node S and ground, ZSS, consists of a resistance RSS in parallel with a capacitance CSS. (b) Differential half-circuit. (c) Common-mode half-circuit.
Q1 QS I S ZSS [RSSCSS] Q2 RD RD VBIAS VDD VSS (a) Vo (b) Q1 RD Vo2 Vid2 RD 2RSS Vocm Vicm (c) 2 CSS Vo Vid.
⁄ 9.27 A MOSFET differential amplifier such as that in Fig. 9.34(a) is biased with a current I = 0.8 mA.
The transistors have W/L = 100, VA = 20 V, Cgs = 50 fF, Cgd = 10 fF, and Cdb = 10 fF. The drain resistors are 5 kΩ each. Also, there is a 100-fF capacitive load between each drain and ground.
(a) Find VOV and gm for each transistor.
(b) Find the differential gain Ad.
(c) If the input signal source has a small resistance Rsig and thus the frequency response is deter-mined primarily by the output pole, estimate the 3-dB frequency fH. (Hint: Refer to Section 9.5.6 and specifically to Eq. 9.107.) (d) If, in a different situation, the amplifier is fed symmetrically with a signal source of 20 kΩ resist-ance (i.e., 10 kΩ in series with each gate terminal), use the open-circuit time-constants method to estimate fH. (Hint: Refer to Section 9.5.3 and specifically to Eqs. [(9.85) and (9.86)].) Ans. (a) 0.2 V, 4 mA/V; (b) 18.2 V/V; (c) 291 MHz; (d) 53.7 MHz kn ′ 0.2 mA/V 2, = EXERCISE 762 Chapter 9 Frequency Response The common-mode half-circuit is shown in Fig. 9.34(c). Although this circuit has other capacitances, namely Cgs, Cgd, and Cdb of the transistor in addition to other stray capaci-tances, we have chosen to show only This is because together with (2RSS) forms a real-axis zero in the common-mode gain function at a frequency much lower than those of the other poles and zeros of the circuit. This zero then dominates the frequency dependence of Acm and CMRR.
If the output of the differential amplifier is taken single-endedly, then the common-mode gain of interest is More typically, the output is taken differentially. Nevertheless, as we have seen in Section 8.2, still plays a major role in determining the common-mode gain. To be specific, consider what happens when the output is taken differentially and there is a mismatch ΔRD between the two drain resistances. The resulting common-mode gain was found in Section 8.2 to be (Eq. 8.499) (9.135) which is simply the product of and the per-unit mismatch Similar expressions can be found for the effects of other circuit mismatches. The important point to note is that the factor is always present in these expressions. Thus, the frequency dependence of Acm can be obtained by simply replacing RSS by ZSS in this factor. Doing so for the expression in Eq. (9.135) gives (9.136) from which we see that Acm acquires a zero on the negative real axis of the s-plane with frequency ωZ, (9.137) or in hertz, (9.138) As mentioned above, usually fZ is much lower than the frequencies of the other poles and zeros. As a result, the common-mode gain increases at the rate of +6 dB/octave (20 dB/ decade) starting at a relatively low frequency, as indicated in Fig. 9.35(a). Of course, Acm drops off at high frequencies because of the other poles of the common-mode half-circuit. It is, however, fZ that is significant, for it is the frequency at which the CMRR of CSS 2.
⁄ CSS 2 ⁄ ( ) V ocm V icm ⁄ .
V ocm V icm ⁄ Acm RD 2RSS -----------⎝ ⎠ ⎛ ⎞ΔRD RD ----------– = V ocm V icm ⁄ RD Δ RD ⁄ ( ).
RD 2RSS ⁄ Acm s ( ) RD 2ZSS ---------- ΔRD RD ----------⎝ ⎠ ⎛ ⎞ – = 1 2 ---– RD ΔRD RD ----------⎝ ⎠ ⎛ ⎞YSS = 1 2 ---– RD ΔRD RD ----------⎝ ⎠ ⎛ ⎞ 1 RSS -------sCSS + ⎝ ⎠ ⎛ ⎞ = RD 2RSS ----------- ΔRD RD ----------⎝ ⎠ ⎛ ⎞1 sCSSRSS + ( ) – = ωZ 1 CSSRSS ----------------= f Z ωZ 2π ------1 2πCSSRSS -----------------------= = 9.8 High-Frequency Response of Differential Amplifiers 763 Figure 9.35 Variation of (a) common-mode gain, (b) differential gain, and (c) common-mode rejection ratio with frequency.
2CSSRSS 1 (a) Acm (dB) f (log scale) (b) Ad (dB) f (log scale) (c) CMRR (dB) f (log scale) 764 Chapter 9 Frequency Response the differential amplifier begins to decrease, as indicated in Fig. 9.35(c). Note that if both Ad and Acm are expressed and plotted in dB, then CMRR in dB is simply the difference between Ad and Acm.
Although in the foregoing we considered only the common-mode gain resulting from an RD mismatch, it should be obvious that the results apply to the common-mode gain resulting from any other mismatch. For instance, it applies equally well to the case of a gm mismatch, modifying Eq. (8.63) by replacing RSS by ZSS, and so on.
Before leaving this section, it is interesting to point out an important trade-off found in the design of the current-source transistor QS: In order to operate this current source with a small VDS (to conserve the already low VDD), we desire to operate the transistor at a low over-drive voltage VOV. For a given value of the current I, however, this means using a large W/L ratio (i.e., a wide transistor). This in turn increases CSS and hence lowers fZ with the result that the CMRR deteriorates (i.e., decreases) at a relatively low frequency. Thus there is a trade-off between the need to reduce the dc voltage across QS and the need to keep the CMRR rea-sonably high at higher frequencies.
To appreciate the need for high CMRR at higher frequencies, consider the situation illustrated in Fig. 9.36: We show two stages of a differential amplifier whose power-supply voltage VDD is corrupted with high-frequency noise. Since the quiescent voltage at each of the drains of Q1 and Q2 is we see that vD1 and vD2 will have the same high-frequency noise as VDD. This high-frequency noise then constitutes a common-mode input signal to the second differential stage, formed by Q3 and Q4. If the second differential stage is perfectly matched, its differential output voltage Vo should be free of high-frequency noise. However, in practice there is no such thing as perfect matching, and the second stage will have a finite common-mode gain. Furthermore, because of the zero formed by RSS and CSS of the second stage, the common-mode gain will increase with frequency, causing some of the noise to make its way to Vo. With careful design, this undesirable component of Vo can be kept small.
Figure 9.36 The second stage in a differential amplifier, which is relied on to suppress high-frequency noise injected by the power supply of the first stage, and therefore must maintain a high CMRR at higher frequencies.
Q1 Q2 RD RD VDD V o I Q3 Q4 RD RSS CSS RD I VDD VDD RD 2 I VDD RD 2 I [V DD I/2 ( )RD – ], 9.8 High-Frequency Response of Differential Amplifiers 765 9.8.2 Analysis of the Active-Loaded MOS Amplifier We next consider the frequency response of the current-mirror-loaded MOS differential-pair circuit studied in Section 8.5. The circuit is shown in Fig. 9.37(a) with two capacitances indicated: Cm, which is the total capacitance at the input node of the current mirror, and CL, which is the total capacitance at the output node. Capacitance Cm is mainly formed by Cgs3 and Cgs4 but also includes Cgd1, Cdb1, and Cdb3, (9.139) Capacitance CL includes Cgd2, Cdb2, Cdb4, Cgd4 as well as an actual load capacitance and/or the input capacitance of a subsequent stage (Cx), (9.140) These two capacitances primarily determine the dependence of the differential gain of this amplifier on frequency.
As indicated in Fig. 9.37(a) the input differential signal Vid is applied in a balanced fashion and the output node is short-circuited to ground in order to determine the transconductance Gm.
Figure 9.37 (a) Frequency–response analysis of the active-loaded MOS differential amplifier. (b) The overall transconductance Gm as a function of frequency.
Cm Cgd1 Cdb1 Cdb3 Cgs3 Cgs4 + + + + = CL Cgd2 Cdb2 Cgd4 Cdb4 Cx + + + + = Vg3 Ro Cm CL Q1 Q3 Q4 0 V Vid2 Vid2 (a) Q2 Id1 gm Vid 2 gm3 1 Id4 Io Id2 gm Vid 2 fP2 0 Gm gm gm fZ f 1 2 (b) 9.28 The differential amplifier specified in Exercise 9.27 has RSS = 25 kΩ and CSS = 0.4 pF. Find the 3-dB frequency of the CMRR.
Ans. 15.9 MHz EXERCISE 766 Chapter 9 Frequency Response Obviously, because of the output short circuit, CL will have no effect on Gm. Transistor Q1 will conduct a drain current signal of which flows through the diode-connected transis-tor Q3 and thus through the parallel combination of and Cm, where we have neglected the resistances ro1 and ro3 which are much larger than thus (9.141) In response to Vg3, transistor Q4 conducts a drain current Id 4, Since gm3 = gm4, this equation reduces to (9.142) Now, at the output node the total output current that flows through the short circuit is (9.143) We can thus obtain as (9.144) Thus, as expected, the low-frequency value of Gm is equal to gm of Q1 and Q2. At high fre-quencies, Gm acquires a pole and a zero, the frequencies of which are (9.145) and (9.146) That is, the zero frequency is twice that of the pole. Since Cm is approximately equal to , we also have (9.147) and (9.148) gmVid 2, ⁄ 1 gm3 ⁄ ( ) 1 gm3 ⁄ ( ), Vg3 gmVid 2 ⁄ gm3 sCm + -----------------------– = Id 4 gm4Vg3 – gm4 gmVid 2 ⁄ gm3 sCm + ------------------------------= = Id4 gmVid 2 ⁄ 1 s Cm gm3 --------+ --------------------= Io Id4 Id2 + = gmVid 2 ⁄ 1 s Cm gm3 --------+ --------------------gm Vid 2 ⁄ ( ) + = Gm Gm Io Vid ------- gm 1 s Cm 2gm3 -----------+ 1 s Cm gm3 --------+ ------------------------= ≡ fP2 gm3 2πCm --------------= fZ 2gm3 2πCm --------------= Cgs2 Cgs4 2Cgs = + fP2 gm3 2πCm -------------- gm3 2π 2Cgs ( ) ----------------------- fT 2 ⁄ = fZ fT 9.8 High-Frequency Response of Differential Amplifiers 767 where is the unity-gain frequency of the MOSFET Q3. Thus, the mirror pole and zero occur at very high frequencies. Nevertheless, their effect can be significant.
Figure 9.37(b) shows a sketch of the magnitude of Gm versus frequency. It is interesting and useful to observe that the path of the signal current produced by Q1 has a transfer function different from that of the signal current produced by Q2. It is the first signal that encounters Cm and experiences the mirror pole. This observation leads to an interesting view of the effect of Cm on the overall transconductance Gm of the differential amplifier. As we learned in Section 8.5, at low frequencies Id1 is replicated by the mirror in the drain of Q4 as Id4, which adds to Id2 to provide a factor-of-2 increase in Gm (thus making Gm equal to gm, which is double the value available without the current mirror). Now, at high frequencies Cm acts as a short cir-cuit causing Vg3 to be zero, and hence Id4 will be zero, reducing Gm to , as borne out by the sketch in Fig. 9.37(b).
Having determined the short-circuit output current Io, we now multiply it by the total impedance between the output node and ground to determine the output voltage Vo, Thus, (9.149) where Thus, in addition to the pole and zero of Gm, the gain of the differential amplifier will have a pole with frequency , (9.150) This, of course, is entirely expected, and in fact this output pole is often dominant, especially when a large load capacitance is present.
fT Q3 Q4 – gm 2 ⁄ Vo Io 1 1 Ro -----sCL + ---------------------= GmVid Ro 1 sCLRo + ------------------------= Vo Vid ------- gmRo ( ) 1 s Cm 2gm3 -----------+ 1 s Cm gm3 --------+ ------------------------1 1 sCLRo + ------------------------⎝ ⎠ ⎛ ⎞ = Ro ro2 ro4 || = fP1 fP1 1 2πCLRo -------------------= Consider an active-loaded MOS differential amplifier of the type shown in Fig. 9.37(a). Assume that for all transistors, W/L = 7.2 μm/0.36 μm, Cgs = 20 fF, Cgd = 5 fF, and Cdb = 5 fF. Also, let μnCox = 387 μA/V2, μpCox = 86 μA/V2, The bias current I = 0.2 mA, and the bias current source has an output resistance RSS = 25 kΩ and an output capacitance CSS = 0.2 pF.
In addition to the capacitances introduced by the transistors at the output node, there is a capacitance Cx of 25 fF. It is required to determine the low-frequency values of Ad, Acm, and CMRR. It is also required to find the poles and zero of Ad and the dominant pole of CMRR.
VAn ′ = 5 V/μm, VAp ′ 6 V/μm.
= Example 9.14 768 Chapter 9 Frequency Response Example 9.14 continued Solution Since I = 0.2 mA, each of the four transistors is operating at a bias current of 100 μA. Thus, for Q1 and Q2, which leads to Thus, For Q3 and Q4 we have Thus, VOV3,4 = 0.34 V, and The low-frequency value of the differential gain can be determined from The low-frequency value of the common-mode gain can be determined from Eq. (8.146′) as The low-frequency value of the CMRR can now be determined as or, 20 log 369 = 51.3 dB 100 1 2 ---387 7.2 0.36 ----------× × VOV 2 × = V OV 0.16 V = gm gm1 gm2 2 0.1 × 0.16 ----------------1.25 mA/V = = = = ro1 ro2 5 0.36 × 0.1 -------------------18 kΩ = = = 100 1 2 ---86 7.2 0.36 ----------× × VOV3 4 , 2 × = gm3 gm4 2 0.1 × 0.34 ----------------0.6 mA/V = = = ro3 ro4 6 0.36 × 0.1 -------------------21.6 kΩ = = = Ad gm ro2|| ro4 ( ) = 1.25 18 ||21.6 ( ) = 12.3 V/V = Acm 1 2gm3RSS --------------------– = 1 2 0.6 25 × × -----------------------------– = 0.033 V/V – = CMRR Ad Acm -----------12.3 0.033 -------------369 = = = 9.8 High-Frequency Response of Differential Amplifiers 769 To determine the poles and zero of Ad we first compute the values of the two pertinent capacitances Cm and CL. Using Eq. (9.139), Cm = Cgd1 + Cdb1 + Cdb3 + Cgs3 + Cgs4 = 5 + 5 + 5 + 20 + 20 = 55 fF Capacitance CL is found using Eq. (9.140) as CL = Cgd2 + Cdb2 + Cgd4 + Cdb4 + Cx = 5 + 5 + 5 + 5 + 25 = 45 fF Now, the poles and zero of Ad can be found from Eqs. (9.150), (9.145), and (9.146) as = 360 MHz Thus the dominant pole is that produced by CL at the output node. As expected, the pole and zero of the mirror are at much higher frequencies.
The dominant pole of the CMRR is at the location of the common-mode-gain zero introduced by CSS and RSS, that is, = 31.8 MHz Thus, the CMRR begins to decrease at 31.8 MHz, which is much lower than fP1.
f P1 1 2πCLRo -------------------= 1 2π CL ro2 ro4 || ( ) × --------------------------------------------= 1 2π 45 10 15 – × × 18 21.6 || ( )103 -------------------------------------------------------------------------= f P2 gm3 2πCm --------------0.6 10 3 – × 2π 55 10 15 – × × --------------------------------------1.74 GHz = = = fZ 2fP2 3.5 GHz = = fZ 1 2πCSSRSS ------------------------= 1 2π 0.2 10 12 – 25 103 × × × × ------------------------------------------------------------------= 9.29 A bipolar current-mirror-loaded differential amplifier is biased with a current source I = 1 mA.
The transistors are specified to have |VA| = 100 V. The total capacitance at the output node is 2 pF. Find the dc value and the frequency of the dominant high-frequency pole of the differential voltage gain.
Ans. 2000 V/V; 0.8 MHz EXERCISE 770 Chapter 9 Frequency Response 9.9 Other Wideband Amplifier Configurations Thus far, we have studied one wideband amplifier configuration: the cascode amplifier. Cas-coding can, of course, be applied to differential amplifiers to obtain wideband differential amplification. In this section we discuss a number of other circuit configurations that are capable of achieving wide bandwidths.
9.9.1 Obtaining Wideband Amplification by Source and Emitter Degeneration As we discussed in Chapters 5 and 6, adding a resistance in the source (emitter) lead of a CS (CE) amplifier can result in a number of performance improvements at the expense of a reduction in voltage gain. Extension of the amplifier bandwidth, which is the topic of inter-est to us in this section, is among those improvements.
Figure 9.38(a) shows a common-source amplifier with a source-degeneration resistance Rs. As indicated in Fig. 9.38(b), the output of the amplifier can be modeled at low frequen-cies by a controlled current-source GmVi and an output resistance Ro, where the transconduc-tance Gm is given by (9.151) and the output resistance is given by (9.152) Thus, source degeneration reduces the transconductance and increases the output resistance by the same factor, . The low-frequency voltage gain can be obtained as (9.153) Let’s now consider the high-frequency response of the source-degenerated amplifier.
Figure 9.38(c) shows the amplifier, indicating the capacitances Cgs and Cgd. A capacitance CL that includes the MOSFET capacitance Cdb is also shown at the output. The method of open-circuit time constants can be employed to obtain an estimate of the 3-dB frequency fH.
Toward that end, we show in Fig. 9.38(d) the circuit for determining Rgd, which is the resis-tance seen by Cgd. We observe that Rgd can be determined by simply adapting the formula in Eq. (9.84) to the case with source degeneration as follows: (9.154) where (9.155) Gm gm 1 gmRs + ---------------------Ro ro 1 gmRs + ( ) 1 gmRs + ( ) AM Vo Vsig -------- Gm Ro RL || ( ) GmR′ L – = – = = Rgd Rsig(1 GmRL ′ ) + + RL ′ = RL ′ RL Ro || = 9.9 Other Wideband Amplifier Configurations 771 ~ Figure 9.38 (a) The CS amplifier circuit, with a source resistance Rs. (b) Equivalent-circuit representa-tion of the amplifier output. (c) The circuit prepared for frequency-response analysis. (d) Determining the resistance Rgd seen by the capacitance Cgd.
Rs RL Vsig (a) Rsig ro Vi Vo (b) Vo GmVi R o RL (c) Vo CL Cgd Cgs RL Rs ro Vsig Rsig (d) D D RL Rs Rsig Rgd G ro G Rgd RL GmVi Ro Rsig Vx Ix Vi Rgd R L Rsig(1 GmR L) Vx Ix R L 772 Chapter 9 Frequency Response The formula for can be seen to be simply (9.156) The formula for is the most difficult to derive, and the derivation should be performed with the hybrid- model explicitly utilized. The result is (9.157) When is relatively large, the frequency response will be dominated by the Miller multiplication of . Another way for saying this is that will be the largest of the three open-circuit time constants that make up , (9.158) enabling us to approximate as (9.159) and correspondingly to obtain as (9.160) Now, as is increased, the gain magnitude, , will decrease, causing to decrease (Eq. 9.154), which in turn causes fH to increase (Eq. 9.160). To highlight the trade-off between gain and bandwidth that affords the designer, let us simplify the expression for in Eq. (9.154) by assuming that and which can be substituted in Eq. (9.160) to obtain (9.161) which very clearly shows the gain–bandwidth trade-off. The gain–bandwidth product remains constant at (9.162) RCL RCL RL Ro R = L ′ || = Rgs π Rgs Rsig Rs + 1 gm + Rs ro ro RL + ----------------⎝ ⎠ ⎛ ⎞ -------------------------------------------Rsig Cgd Cgd Rgd τH τH Cgs Rgs Cgd Rgd CLRCL + + = τH τH Cgd Rgd f H fH 1 2πCgd Rgd ------------------------Rs AM G = mRL ′ Rgd Rs Rgd GmRL ′ 1 GmRsig 1, Rgd GmRL ′ Rsig = AM Rsig f H 1 2πCgd Rsig AM ----------------------------------= Gain–bandwidth product = AM fH 1 2πCgd Rsig ------------------------= 9.9 Other Wideband Amplifier Configurations 773 In practice, however, the other capacitances will play a role in determining , and the gain– bandwidth product will decrease somewhat as is increased. 9.9.2 The CD–CS, CC–CE and CD–CE Configurations In Section 7.6.1 we discussed the performance improvements obtained by preceding the CS and CE amplifiers by a buffer implemented by a CD or a CC amplifier, as in the circuits shown in Fig. 9.39. A major advantage of each of these circuits is wider bandwidth than that obtained in the CS or CE stage alone. To see how this comes about, consider as an example the CD–CS amplifier in Fig 9.39(a) and note that the CS transistor will still exhibit a Miller effect that results in a large input capacitance, , between its gate and ground.
However, the resistance that this capacitance interacts with will be much lower than ; the buffering action of the source follower causes a relatively low resistance, approximately equal to a , to appear between the source of and ground across .
Figure 9.39 (a) CD–CS amplifier. (b) CC–CE amplifier. (c) CD–CE amplifier.
f H Rs Q2 Cin2 Rsig 1 gm1 ⁄ Q1 Cin2 (a) VDD I2 I1 Q1 Q2 (b) VCC I2 I1 Q1 Q2 (c) VDD I2 I1 Q2 Q1 9.30 Consider a CS amplifier having , , , , , , and . (a) Find the voltage gain and the 3-dB frequency (using the method of open-circuit time constants) and hence the gain–bandwidth product. (b) Repeat (a) for the case in which a resistance is connected in series with the source terminal with a value selected so that gm Rs = 2 .
Ans. (a) −20 V/V, 61.2 MHz, 1.22 GHz; (b) −10 V/V, 109 MHz, 1.1 GHz gm 2 mA/V = ro 20 kΩ = RL 20 kΩ = Rsig 20 kΩ = Cgs = 20 fF Cgd 5 fF = CL 5 fF = AM f H Rs EXERCISE 774 Chapter 9 Frequency Response Consider a CC–CE amplifier such as that in Fig. 9.39(b) with the following specifications: and identical transistors with β = 100, MHz, and . Let the amplifier be fed with a source having a resistance , and assume a load resistance of 4 kΩ. Find the voltage gain , and estimate the 3-dB frequency, . Compare the results with those obtained with a CE amplifier operating under the same conditions. For simplicity, neglect and Solution At an emitter bias current of 1 mA, and have mA/V The voltage gain can be determined from the circuit shown in Fig. 9.40(a) as follows: Thus, To determine we use the method of open-circuit time constants. Figure 9.40(b) shows the cir-cuit with set to zero and the four capacitances indicated. Capacitance sees a resistance , I1 = I2 = 1 mA fT 400 = Cμ = 2 pF V sig Rsig 4 kΩ = AM f H ro rx.
Q1 Q2 gm 40 = re 25 Ω = rπ β gm ------ 100 40 --------- 2.5 kΩ = = = Cπ Cμ gm ωT ------ gm 2πfT -----------= = + 40 10 3 – × 2π × 400 10 × 6 --------------------------------------- 15.9 pF = = Cμ 2 pF = Cπ 13.9 pF = AM Rin2 rπ 2 2.5 kΩ = = Rin β1 1 + ( ) re1 Rin2 + ( ) = 101 0.025 2.5 + ( ) 255 kΩ = = Vb1 Vsig -------- Rin Rin Rsig + ---------------------- 255 255 4 + ------------------ 0.98 V/V = = = Vb2 Vb1 -------- Rin2 Rin2 re1 + ---------------------- 2.5 2.5 0.025 + --------------------------- 0.99 V/V = = = Vo Vb2 -------- = gm2RL = 40 4 160 V/V – = × – – AM = Vo Vsig -------- 160 0.99 0.98 155 V/V – = × × – = f H V sig Cμ1 Rμ1 Rμ1 Rsig Rin || = 4 255 3.94 kΩ = || = Example 9.15 9.9 Other Wideband Amplifier Configurations 775 To find the resistance seen by capacitance we refer to the analysis of the high-frequency response of the emitter follower in Section 9.7.2. Specifically, we adapt Eq.
(9.133) to the situation here as follows: Figure 9.40 Circuits for Example 9.14: (a) the CC–CE circuit prepared for low-frequency, small-signal analysis; (b) the circuit at high frequencies, with Vsig set to zero to enable determination of the open-circuit time constants; (c) a CE amplifier for comparison.
(a) RL Q2 Q1 Vsig Rsig Vo Rout1 re1 Vb1 Vb2 Rin2 Rin (b) RL Cp2 Cm1 Cm2 Q2 Rsig Q1 Cp1 (c) RL Cp Cm Vsig Rsig Vo Rπ1 Cπ1 Rπ1 Rsig R + in2 1 Rsig rπ1 --------Rin2 re1 ---------+ + ----------------------------------= 4000 2500 + 1 4000 2500 ------------ + 2500 25 ------------+ ---------------------------------------- = 63.4 Ω = 776 Chapter 9 Frequency Response Example 9.15 continued Capacitance sees a resistance , Capacitance sees a resistance . To determine we refer to the analysis of the frequency response of the CE amplifier in Section 9.5 to obtain We now can determine from We observe that and play a very minor role in determining the high-frequency response. As expected, through the Miller effect plays the most significant role. Also, , which interacts directly with , also plays an important role. The 3-dB frequency can be found as fol-lows: For comparison, we evaluate and of a CE amplifier operating under the same conditions.
Refer to Fig. 9.40(c). The voltage gain is given by = 251.7 kΩ Cπ 2 Rπ 2 Rπ 2 = Rin2 Rout1 || rπ2 re1 Rsig β1 1 + --------------+ || = 2500 25 4000 101 ------------+ 63 Ω = || = Cμ2 Rμ2 Rμ2 Rμ2 1 gm2 + RL ( ) Rin2 Rout1 || ( ) RL + = 1 40 4 × + ( ) 2500 25 4000 101 ------------+ ⎝ ⎠ ⎛ ⎞ || 4000 + = 14 143 Ω ·· 14.1 kΩ , = τH τH Cμ1Rμ1 Cπ1Rπ1 Cμ2Rμ2 Cπ2Rπ2 + + + = 2 3.94 13.9 0.0634 2 14.1 13.9 0.063 × + × + × + × = 7.88 = 0.88 28.2 0.88 = 37.8 ns + + + Cπ1 Cπ2 Cμ2 Cμ1 Rsig Rin || ( ) f H f H 1 2πτH ------------ 1 2π 37.8 10 9 – × × ---------------------------------------- 4.2 MHz = = = AM f H AM AM Rin Rin Rsig + ----------------------gmRL – ( ) = rπ rπ Rsig + -------------------gmRL – ( ) = 2.5 2.5 4 + ----------------40 4 × – ( ) = 61.5 V/V – = Rπ rπ Rsig 2.5 4 1.54 kΩ = || = || = Rμ 1 gmRL + ( ) Rsig rπ || ( ) RL + = 1 40 4 × + ( ) 4 2.5 || ( ) 4 + = 9.9 Other Wideband Amplifier Configurations 777 9.9.3 The CC–CB and CD–CG Configurations In Section 7.6.2 we showed that preceding a CB or CG transistor with a buffer implemented with a CC or a CD transistor solves the low-input-resistance problem of the CB and CG amplifiers. Examples of the resulting compound-transistor amplifiers are shown in Fig. 9.41.
Since in each of these circuits, neither of the two transistors suffers from the Miller effect, the resulting amplifiers have even wider bandwidths than those achieved in the compound amplifier stages of the last section. To illustrate, consider as an example the circuit in Figure 9.41 (a) A CC–CB amplifier. (b) Another version of the CC–CB circuit with Q2 implemented using a pnp transistor. (c) The MOSFET version of the circuit in (a).
(a) Vo I 2I E VEE VCC Q2 C2 C1 B1 B2 Q1 Vi Rin (b) Vo VBIAS VCC VEE I Q1 Q2 C1 C2 E B1 B2 Vi (c) VDD Q2 Q1 I Vo Vi 2I VSS Thus, = 21.4 + 503.4 = 524.8 ns Observe the dominant role played by . The 3-dB frequency is Thus, including the buffering transistor increases the gain, , from 61.5 V/V to 155 V/V—a factor of 2.5—and increases the bandwidth from 303 kHz to 4.2 MHz—a factor of 13.9! The gain–bandwidth product is increased from 18.63 MHz to 651 MHz—a factor of 35!
τH CπRπ CμRμ + = 13.9 1.54 2 251.7 × + × = Cμ fH f H 1 2πτH ------------ 1 2π 524.8 10 9 – × × ------------------------------------------- 303 kHz = = = Q1 AM 778 Chapter 9 Frequency Response Fig. 9.41(a).10 The low-frequency analysis of this circuit in Section 7.6.2 provides for the input resistance, (9.163) which for and becomes (9.164) If a load resistance is connected at the output, the voltage gain will be (9.165) Now, if the amplifier is fed with a voltage signal from a source with a resistance , the overall voltage gain will be (9.166) The high-frequency analysis is illustrated in Fig. 9.42(a). Here we have drawn the hybrid-π equivalent circuit for each of and . Recalling that the two transistors are operating at equal bias currents, their corresponding model components will be equal (i.e., , , etc.). With this in mind the reader should be able to see that and the horizontal line through the node labeled E in Fig. 9.42(a) can be deleted. Thus the circuit reduces to that in Fig. 9.42(b). This is a very attractive outcome because the circuit shows clearly the two poles that determine the high-frequency response: The pole at the input, with a frequency , is (9.167) and the pole at the output, with a frequency , is (9.168) This result is also intuitively obvious: The input impedance at of the circuit in Fig. 9.42(a) consists of the series connection of and in parallel with the series connection of and . Then there is Cμ1 in parallel. At the output, we simply have in parallel with .
Whether one of the two poles is dominant will depend on the relative values of and . If the two poles are close to each other, then the 3-dB frequency can be determined either by exact analysis—that is, finding the frequency at which the gain is down by 3 dB— or by using the approximate formula in Eq. (9.68), (9.169) 10 The results derived for the circuit in Fig. 9.41(a) apply directly to the circuit of Fig. 9.41(b) and with appropriate change of variables to the MOS circuit of Fig. 9.41(c).
Rin β1 1 + ( ) re1 re2 + ( ) = re1 re2 re = = β1 β2 β = = Rin 2rπ = RL V o Vi ⁄ V o Vi ----- α2RL re1 re2 + ------------------- 1 2 ---gmRL = = Vsig Rsig V o Vsig -------- 1 2 ---Rin Rin Rsig + ---------------------⎝ ⎠ ⎛ ⎞gmRL ( ) = Q1 Q2 rπ1 rπ2 = Cπ1 Cπ2 = Vπ1 = V – π2 fP1 fP1 1 2π Cπ 2 ------Cμ + ⎝ ⎠ ⎛ ⎞Rsig 2rπ || ( ) ------------------------------------------------------------= fP2 fP2 1 2πCμRL -------------------= B1 rπ1 rπ2 Cπ1 Cπ2 RL Cμ Rsig RL fH fH 1 1 fP1 2 ------1 fP2 2 ------+ 9.10 Multistage Amplifier Examples 779 9.10 Multistage Amplifier Examples We conclude this chapter with the frequency-response analysis of the two multistage ampli-fiers we studied in Section 8.6. As we shall see, these are relatively complex circuits: Sim-ply replacing each transistor with its high-frequency, equivalent-circuit model will make it exceedingly difficult for pencil-and-paper analysis, and will most certainly not lead to any analysis and design insight. Rather, we will use the knowledge and experience we have Figure 9.42 (a) Equivalent circuit for the amplifier in Fig. 9.41(a). (b) Simplified equivalent circuit. Note that the equivalent circuits in (a) and (b) also apply to the circuit shown in Fig. 9.41(b). In addition, they can be easily adapted for the MOSFET circuit in Fig. 9.41(c), with 2rπ eliminated, Cπ replaced with Cgs, Cμ replaced with Cgd, and Vπ replaced with Vgs.
B1 B2 C1 C2 E Vo RL Rsig Vsig (a) Vo C2 B1 RL (b) Vsig Rsig 9.31 For the CC–CB amplifier of Fig. 9.41(a), let I = 0.5 mA, , , , 10 kΩ, and . Find the low-frequency overall voltage gain AM, the frequencies of the poles, and the 3-dB frequency fH. Find fH both exactly and using the approximate formula in Eq.
(9.169).
Ans. 50 V/V; 6.4 MHz and 8 MHz; fH by exact evaluation = 4.6 MHz; fH using Eq. (9.169) = 5 MHz.
β 100 = Cπ 6 pF = Cμ 2 pF = Rsig = RL 10 kΩ = EXERCISE 780 Chapter 9 Frequency Response gained throughout this chapter to decide on ways to simplify the analysis. Our objective is multifold: to be able to pinpoint the part or parts of a circuit that limit its high-frequency performance, to understand how this limitation comes about, to obtain an estimate of the 3-dB bandwidth , and finally and most importantly, to find ways to improve the design of the circuit so as to extend its high-frequency operation. It is useful at this juncture to point out that computer simulation using PSpice and Multisim is a very valuable tool for the circuit designer, especially when frequency-response analysis is under consideration. Nevertheless, it is a tool that has to be used judiciously and certainly not as a replacement for a first-cut pencil-and-paper analysis. Circuit simulation, by utilizing sophisti-cated device models, will enable the designer to obtain a reasonably accurate prediction of what to expect after the circuit has been fabricated. If the expected performance is unsatisfactory, the designer will then have the opportunity to alter the design to meet specifications.
9.10.1 Frequency Response of the Two-Stage CMOS Op Amp Figure 9.43 shows the two-stage CMOS amplifier we studied in Section 8.6.1. Before con-tinuing with this section, we urge the reader to review Section 8.6.1 and Example 8.5. To analyze the frequency response of the two-stage op amp, consider its simplified small-signal equivalent circuit shown in Fig. 9.44. Here Gm1 is the transconductance of the input stage (Gm1 = gm1 = gm2), R1 is the output resistance of the first stage and C1 is the total capacitance at the interface between the first and second stages Gm2 is the transconductance of the second stage (Gm2 = gm6), R2 is the output resistance of the second stage and C2 is the total capacitance at the output node of the op amp Figure 9.43 Two-stage CMOS op-amp configuration.
fH R1 ro2 ro4 || = ( ), C1 Cgd4 Cdb4 Cgd2 Cdb2 Cgs6 + + + + = R2 ro6 ro7 || = ( ), C2 Cdb6 Cdb7 Cgd7 CL + + + = CC D6 D2 I 9.10 Multistage Amplifier Examples 781 where CL is the load capacitance. Usually CL is much larger than the transistor capacitances, with the result that C2 is much larger than C1. Capacitor CC is deliberately included for the pur-pose of equipping the op amp with a uniform −6-dB/octave frequency response. In the follow-ing, we shall see how this is possible and how to select a value for CC. Finally, note that in the equivalent circuit of Fig. 9.44 we should have included Cgd6 in parallel with CC. Usually, how-ever, , which is the reason we have neglected Cgd6.
To determine Vo, analysis of the circuit in Fig. 9.44 proceeds as follows. Writing a node equation at node D2 yields (9.170) Writing a node equation at node D6 yields (9.171) To eliminate Vi2 and thus determine Vo in terms of Vid, we use Eq. (9.171) to express Vi2 in terms of Vo and substitute the result into Eq. (9.170). After some straightforward manipula-tions we obtain the amplifier transfer function (9.172) First we note that for s = 0 (i.e., dc), Eq. (9.172) gives which is what we should have expected. Second, the transfer function in Eq. (9.172) indicates that the amplifier has a transmission zero at s = sZ, which is determined from Thus, (9.173) In other words, the zero is on the positive real axis with a frequency ωZ of (9.174) Figure 9.44 Equivalent circuit of the op amp in Fig. 9.43.
Vid Gm1Vid R2 C2 Vo C1 Vi2 Gm2 Vi2 R1 CC D2 D6 CC Cgd6 Gm1 V id Vi2 R1 -------sC1V i2 sCC Vi2 V o – ( ) + + + 0 = Gm2Vi2 V o R2 -----sC2V o sCC (V o Vi2) – + + + 0 = V o V id -------Gm1 Gm2 sCC – ( )R1R2 1 s C1R1 C2R2 CC Gm2R1R2 R1 R2 + + ( ) + + [ ] s 2 C1C2 CC C1 C2 + ( ) + [ ]R1R2 + + --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= Vo Vid ⁄ Gm1R1 ( ) Gm2R2 ( ), = Gm2 sZCC – 0 = sZ Gm2 CC ---------= ωZ Gm2 CC ---------= 782 Chapter 9 Frequency Response Also, the amplifier has two poles that are the roots of the denominator polynomial of Eq. (9.172). If the frequencies of the two poles are denoted ωP1 and ωP2, then the denominator polynomial can be expressed as Now if one of the poles is dominant, say with frequency ωP1, then , and D(s) can be approximated by (9.175) The frequency of the dominant pole, ωP1, can now be determined by equating the coeffi-cients of the s terms in the denominator in Eq. (9.172) and in Eq. (9.175), (9.176) We recognize the first term in the denominator as arising at the interface between the first and second stages. Here, R1, the output resistance of the first stage, is interacting with the total capac-itance at the interface. The latter is the sum of C1 and the Miller capacitance which results from connecting CC in the negative feedback path of the second stage whose gain is . Now, since R1 and R2 are usually of comparable value, we see that the first term in the denominator will be much larger than the second and we can approximate ωP1 as A further approximation is possible because C1 is usually much smaller than the Miller capacitance and 1, thus (9.177) The frequency of the second, nondominant pole can be found by equating the coefficients of the s2 terms in the denominator of Eq. (9.172) and in Eq. (9.175) and substituting for ωP1 from Eq. (9.176). The result is Since and ωP2 can be approximated as (9.178) In order to provide the op amp with a uniform gain rolloff of −20 dB/decade down to 0 dB, the value of the compensation capacitor CC is selected so that the resulting value of ωP1 (Eq. 9.177), when multiplied by the dc gain (Gm1R1Gm2R2), results in a unity-gain frequency ωt lower than ωZ and ωP2. Specifically (9.179) D s ( ) 1 s ωP1 --------+ ⎝ ⎠ ⎛ ⎞1 s ωP2 --------+ ⎝ ⎠ ⎛ ⎞ 1 s 1 ωP1 --------1 ωP2 --------+ ⎝ ⎠ ⎛ ⎞ s2 ωP1ωP2 -----------------+ + = = ωP1ωP2 D s ( ) 1 s ωP1 --------s2 ωP1ωP2 -----------------+ + ωP1 1 C1R1 C2R2 CC Gm2R2R1 R1 R2 + + ( ) + + ----------------------------------------------------------------------------------------------= 1 R1 C1 CC 1 Gm2R2 + ( ) + [ ] R2 C2 CC + ( ) + ------------------------------------------------------------------------------------------------= CC 1 Gm2R2 + ( ), Gm2R2 ωP1 1 R1 C1 CC 1 Gm2R2 + ( ) + [ ] ------------------------------------------------------------Gm2R2 ωP1 1 R1CCGm2R2 ----------------------------ωP2 Gm2CC C1C2 CC C1 C2 + ( ) + -------------------------------------------------= C1 C2 C1 CC, ωP2 Gm2 C2 ---------ωt Gm1R1Gm2R2 ( )ωP1 = = Gm1 CC ---------9.10 Multistage Amplifier Examples 783 which must be lower than and . We will have more to say about this point in Section 12.1.
9.10.2 Frequency Response of the Bipolar Op Amp of Section 8.6.2 We urge the reader to review Section 8.6.2 and Examples 8.6 and 8.7 before studying this section. The bipolar op-amp circuit shown earlier in Fig. 8.43 is rather complex. Neverthe-less, it is possible to obtain an approximate estimate of its high-frequency response. Fig-ure 9.45(a) shows an approximate equivalent circuit for this purpose. Note that we have utilized the equivalent differential half-circuit concept, with Q2 representing the input stage and Q5 representing the second stage. We observe, of course, that the second stage is not symmetrical, and strictly speaking the equivalent half-circuit does not apply. Nevertheless, we use it as an approximation so as to obtain a quick pencil-and-paper estimate of the domi-nant high-frequency pole of the amplifier. More precise results can of course be obtained using computer simulation with SPICE.
Examination of the equivalent circuit in Fig. 9.45(a) reveals that if the resistance of the source of signal Vi is small, the high-frequency limitation will not occur at the input but rather at the interface between the first and the second stages. This is because the total capacitance at node A will be high as a result of the Miller multiplication of Cμ5. Also, the third stage, formed by transistor Q7, should exhibit good high-frequency response, since Q7 has a large emitter-degeneration resistance, R3. The same is also true for the emitter-follower stage, Q8.
To determine the frequency of the dominant pole that is formed at the interface between Q2 and Q5 we show in Fig. 9.45(b) the pertinent equivalent circuit. The total resistance between node A and ground can now be found as and the total capacitance is where The frequency of the pole can be calculated from Req and Ceq as ωZ Gm2 CC ---------= ωP2 Gm2 C2 ---------Req R2 ro2 rπ5 || || = Ceq Cμ2 Cπ5 Cμ5 1 gm5RL5 + ( ) + + = RL5 R3 ro5 Ri3 || || = f P 1 2πReqCeq ----------------------= D9.32 Consider the frequency response of the op amp analyzed in Example 8.5. Let C1 = 0.1 pF and C2 = 2 pF. Find the value of CC that results in ft = 10 MHz and verify that ft is lower than fZ and fP2. Recall from the results of Example 8.5, that Gm1 = 0.3 mΑ/V and Gm2 = 0.6 mΑ/V. Ans. CC = 4.8 pF; fZ = 20 MHz; fP2 = 48 MHz EXERCISE 784 Chapter 9 Frequency Response Figure 9.45 (a) Approximate equivalent circuit for determining the high-frequency response of the op amp of Fig. 8.43. (b) Equivalent circuit of the interface between the output of Q2 and the input of Q5.
R2 Q2 Vi V o Q8 R6 R3 Q5 R4 R5 Q7 A Ri3 (a) (b) ro2 R2 r5 C2 C5(1 gm5RL5) C5 gm2Vi A 9.33 Determine Req, Ceq, and fP for the amplifier in Fig. 8.43, utilizing the facts that Q2 is biased at 0.25 mA and Q5 at 1 mA. Assume β = 100, VA = 100 V, fT = 400 MHz, and Cμ = 2 pF. Assume .
Ans. 2.21 kΩ; 258 pF; 280 kHz RL5 R3 EXERCISE Summary The coupling and bypass capacitors utilized in discrete-circuit amplifiers cause the amplifier gain to fall off at low frequencies. The frequencies of the low-frequency poles can be estimated by considering each of these ca-pacitors separately and determining the resistance seen by the capacitor. The highest-frequency pole is the one that determines the lower 3-dB frequency .
Both the MOSFET and the BJT have internal capacitive effects that can be modeled by augmenting the device hy-brid- model with capacitances. Usually at least two ca-pacitances are needed: and ( and for the BJT). A figure-of-merit for the high-frequency operation of the transistor is the frequency at which the short-cir-cuit current gain of the CS (CE) transistor reduces to fL π Cgs Cgd Cπ Cμ fT 9.10 Multistage Amplifier Examples 785 PROBLEMS unity. For the MOSFET, , and for the BJT, .
The internal capacitances of the MOSFET and the BJT cause the amplifier gain to fall off at high frequencies.
An estimate of the amplifier bandwidth is provided by the frequency at which the gain drops 3 dB below its value at midband, . A figure-of-merit for the ampli-fier is the gain–bandwidth product . Usual-ly, it is possible to trade off gain for increased bandwidth, with GB remaining nearly constant. For amplifiers with a dominant pole with frequency , the gain falls off at a uniform 6-dB/octave (20-dB/decade) rate, reaching 0 dB at .
The high-frequency response of the CS and CE ampli-fiers is severely limited by the Miller effect: The small capacitance is multiplied by a factor approx-imately equal to the gain from gate to drain (base to collector) and thus gives rise to a large capaci-tance at the amplifier input. The increased interacts with the effective signal-source resistance and causes the amplifier gain to have a 3-dB frequency .
The method of open-circuit time constants provides a simple and powerful way to obtain a reasonably good estimate of the upper 3-dB frequency . The capaci-tors that limit the high-frequency response are consid-ered one at time with and all the other capacitances set to zero (open circuited). The resistance seen by each capacitance is determined, and the overall time constant is obtained by summing the individual time constants. Then is found as 1/2 .
The CG and CB amplifiers do not suffer from the Miller effect. Thus the cascode amplifier, which consists of a cascade of a CS and CG stages (CE and CB stages), can be designed to obtain wider bandwidth than that achieved in the CS (CE) amplifier alone. The key, however, is to design the cascode so that the gain obtained in the CS (CE) stage is minimized.
The source and emitter followers do not suffer from the Miller effect and thus feature wide bandwidths.
The high-frequency response of the differential amplifier can be obtained by considering the differential and common-mode half-circuits. The CMRR falls off at a rel-atively low frequency determined by the output imped-ance of the bias current source.
The high-frequency response of the current-mirror-loaded differential amplifier is complicated by the fact that there are two signal paths between input and output: a direct path and one through the current mirror.
Combining two transistors in a way that eliminates or minimizes the Miller effect can result in a much wider bandwidth. Some such configurations are presented in Section 9.9.
The key to the analysis of the high-frequency response of a multistage amplifier is to use simple macro models to estimate the frequencies of the poles formed at the inter-face between each two stages, in addition to the input and output poles. The pole with the lowest frequency domi-nates and determines .
fT gm 2π Cgs Cgd + ( ) ⁄ = fT gm 2π Cπ Cμ + ( ) ⁄ = fH AM GB AM fH = fH ft GB = Cgd Cμ ( ) gmR′ L Cin R′ sig fH 1 2πR′ sig ⁄ Cin = fH Vsig 0 = τH fH πτH fH Computer Simulation Problems Problems identified by this icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate im-portant issues such as gain–bandwidth tradeoff. In-structions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the disc. Note that if a par-ticular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very chal-lenging and/or time-consuming; D: design problem.
Section 9.1: Low-Frequency Response of the CS and CE Amplifiers D 9.1 The amplifier in Fig. P9.1 is biased to operate at gm = 1 mA/V. Neglecting ro, find the midband gain. Find the value of CS that places fL at 20 Hz.
9.2 Consider the amplifier of Fig. 9.2(a). Let RD = 10 kΩ, ro = 100 kΩ, and RL = 10 kΩ. Find the value of CC2, specified to one significant digit, to ensure that the associated break fre-quency is at, or below, 10 Hz. If a higher-power design results in doubling ID, with both RD and ro reduced by a factor of 2, what does the corner frequency (due to CC2) become? For 786 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS increasingly higher-power designs, what is the highest corner frequency that can be associated with CC2?
9.3 The NMOS transistor in the discrete CS amplifier circuit of Fig. P9.3 is biased to have gm = 5 mA/V. Find AM, fP1, fP2, fP3, and fL.
D 9.4 Consider the low-frequency response of the CS amplifier of Fig. 9.2(a). Let Rsig = 0.5 MΩ, RG = 2 MΩ, gm = 3 mA/V, RD = 20 kΩ, and RL = 10 kΩ. Find AM. Also, design the coupling and bypass capacitors to locate the three low-frequency poles at 50 Hz, 10 Hz, and 3 Hz. Use a minimum total capacitance, with capacitors specified only to a single sig-nificant digit. What value of fL results?
D 9.5 A particular version of the CS amplifier in Fig. 9.2 uses a transistor biased to operate with mA/V. Resistances k , M , k , and k . As an initial design, the circuit designer selects μF. Find the frequencies , , and and rank them in order of frequency, highest first. Cal-culate the ratios of the first to second, and second to third. The final design requires that the first pole dominate at 10 Hz with the second a factor of 4 lower, and the third another a factor of 4 lower. Find the values of all the capacitances and the total capacitance needed. If the separation factor were 10, what capacitor values and total capacitance would be needed? (Note: You can see that the total capacitance need not be much larger to spread the poles, as is desired in certain applications.) D 9.6 Repeat Example 9.1 to find , , and that provide Hz and the other pole frequencies at 4 Hz and 1 Hz. Design to keep the total capacitance to a minimum.
D 9.7 Reconsider Exercise 9.1 with the aim of finding a bet-ter-performing design using the same total capacitance, that is, 3 μF. Prepare a design in which the break frequencies are sepa-rated by a factor of 5 (i.e., f, f/5, and f/25). What are the three capacitor values, the three break frequencies, and that you achieve?
9.8 Repeat Exercise 9.2 for the situation in which 50 μF and μF. Find the three break frequencies and estimate .
D 9.9 Repeat Example 9.2 for a related CE amplifier whose supply voltages and bias current are each reduced to half their original value but , , , and are left unchanged.
Find , , and for Hz. Minimize the total capacitance used, under the following conditions. Arrange that the contributions of , , and are 80%, 10%, and 10%, respectively. Specify capacitors to two significant digits, choosing the next highest value, in general, for a conservative design, but realizing that for , this may represent a larger capacitance increment. Check the value of that results.
[Note: An attractive approach can be to select on the small side, allowing it to contribute more than 80% to , while making and larger, since they must contribute less to .) D 9.10 A particular current-biased CE amplifier operating at 100 from -V power supplies employs k , k ; it operates between a 20-k source and a 10-k load. The transistor . Select first for a minimum value specified to one significant digit and providing up to 90% of . Then choose and , each specified to one significant digit, with the goal of minimizing the total capacitance used. What results? What total capacitance is needed?
9.11 Consider the common-emitter amplifier of Fig. P9.11 under the following conditions: Rsig = 5 kΩ, R1 = 33 kΩ, R2 = 22 kΩ, RE = 3.9 kΩ, RC = 4.7 kΩ, RL = 5.6 kΩ, VCC = 5 V. The dc emitter current can be shown to be IE 0.3 mA, at which β = 120. Find the input resistance Rin and the midband gain AM. If CC1 = CC2 = 1 μF and CE = 20 μF, find the three break fre-quencies fP1, fP2, and fP3 and an estimate for fL. Note that RE has to be taken into account in evaluating fP2.
Figure P9.1 Figure P9.3 RD 10 k Vo CS RS 6 k VSS Vi VDD VDD 47 M 10 M 100 k 4.7 k 2 k 10 k 0.01 F 10 F 0.1 F Vsig Vo gm 5 = Rsig 200 = Ω RG 10 = Ω RD 3 = Ω RL 5 = Ω CC1 CC2 CS 1 = = = fP1 fP2 fP3 CS CC1 CC2 fL 20 = fL CE = CC1 CC2 2 = = fL RB RC Rsig RL CC1 CE CC2 fL 100 = CE CC1 CC2 CE fL CE fL CC1 CC2 fL μA 3 ± RC 20 = Ω RB 200 = Ω Ω Ω β 100 = CE fL CC1 CC2 fL Problems 787 CHAPTER 9 PR OBLE MS D 9.12 For the amplifier described in Problem 9.11, design the coupling and bypass capacitors for a lower 3-dB frequency of 100 Hz. Design so that the contribution of each of CC1 and CC2 to determining fL is only 5%.
9.13 Consider the circuit of Fig. P9.11. For Rsig = 10 kΩ, rπ = 1 kΩ, β0 = 100, and RE = 1 kΩ, what is the ratio that makes their contributions to the determination of fL equal?
D 9.14 For the common-emitter amplifier of Fig. P9.14, neglect ro and assume the current source to be ideal.
(a) Derive an expression for the midband gain.
(b) Derive expressions for the break frequencies caused by CE and CC.
(c) Give an expression for the amplifier voltage gain A(s).
(d) For Rsig = RC = RL = 10 kΩ, β = 100, and I = 1 mA, find the value of the midband gain.
(e) Select values for CE and CC to place the two break frequencies a decade apart and to obtain a lower 3-dB fre-quency of 100 Hz while minimizing the total capacitance.
(f) Sketch a Bode plot for the gain magnitude, and estimate the frequency at which the gain becomes unity.
(g) Find the phase shift at 100 Hz.
9.15 The BJT common-emitter amplifier of Fig. P9.15 includes an emitter degeneration resistance Re.
(a) Assuming α 1, neglecting ro, and assuming the cur-rent source to be ideal, derive an expression for the small-signal voltage gain that applies in the mid-band and the low-frequency band. Hence find the midband gain AM and the lower 3-dB frequency fL.
(b) Show that including Re reduces the magnitude of AM by a certain factor. What is this factor?
(c) Show that including Re reduces fL by the same factor as in (b) and thus one can use Re to trade-off gain for band-width.
(d) For I = 0.25 mA, RC = 10 kΩ, and CE = 10 μF, find |AM| and fL with Re = 0. Now find the value of Re that lowers fL by a factor of 5. What will the gain become? Sketch on the same diagram a Bode plot for the gain magnitude for both cases.
Figure P9.11 Figure P9.14 RE CC1 Rsig Vsig R2 R1 CC2 Vo RL CE VCC RC Rin RB R1 R2 ≡ = 10 kΩ, CE CC1 ⁄ RL Rsig RC Vsig Vo CE CC VCC I Figure P9.15 A s ( ) Vo Vsig ⁄ ≡ Re RC VCC Vsig CE I Vo 788 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS Section 9.2: Internal Capacitative Effects and the High-Frequency Model of the MOSFET and the BJT 9.16 Refer to the MOSFET high-frequency model in Fig.
9.6(a). Evaluate the model parameters for an NMOS transis-tor operating at ID = 100 μA, VSB = 1 V, and VDS = 1.5 V.
The MOSFET has W = 20 μm, L = 1 μm, tox = 8 nm, μn = 450 cm2/Vs, γ = 0.5 V1/2, 2φf = 0.65 V, λ = 0.05 V−1, V0 = 0.7 V, Csb0 = Cdb0 = 15 fF, and Lov = 0.05 μm. (Recall that gmb = χgm, where 9.17 Find fT for a MOSFET operating at ID = 100 μA and VOV = 0.2 V. The MOSFET has Cgs = 20 fF and Cgd = 5 fF.
9.18 Starting from the expression of fT for a MOSFET, and making the approximation that Cgs Cgd and that the overlap component of Cgs is negligibly small, show that Thus note that to obtain a high fT from a given device, it must be operated at a high current. Also note that faster operation is obtained from smaller devices.
9.19 Starting from the expression for the MOSFET unity-gain frequency, and making the approximation that Cgs Cgd and that the overlap component of Cgs is negligibly small, show that for an n-channel device Observe that for a given channel length, fT can be increased by operating the MOSFET at a higher overdrive voltage. Evaluate fT for devices with L = 1.0 μm operated at overdrive voltages of 0.25 V and 0.5 V. Use μn = 450 cm2/Vs.
9.20 It is required to calculate the intrinsic gain and the unity-gain frequency of an n-channel transistor fabricated in a 0.18-μm CMOS process for which L, cm2/V.s, and V/μm. The device is oper-ated at V. Find and for devices with , 2 , 3 , 4 , and 5 . Present your results in a table.
9.21 A particular BJT operating at IC = 1 mA has Cμ = 1 pF, Cπ = 10 pF, and β = 100. What are fT and fβ for this situation?
9.22 For the transistor described in Problem 9.21, Cπ includes a relatively constant depletion-layer capacitance of 2 pF. If the device is operated at IC = 0.2 mA, what does its fT become?
9.23 An npn transistor is operated at IC = 0.5 mA and VCB = 2 V. It has β0 = 100, VA = 50 V, τF = 30 ps, Cje0 = 20 fF, Cμ 0 = 30 fF, V0c = 0.75 V, mCBJ = 0.5, and rx = 100 Ω. Sketch the com-plete hybrid-π model, and specify the values of all its compo-nents. Also, find fT.
9.24 Measurement of hfe of an npn transistor at 50 MHz shows that |hfe| = 10 at IC = 0.2 mA and 12 at IC = 1.0 mA. Furthermore, Cμ was measured and found to be 0.1 pF. Find fT at each of the two collector currents used. What must τF and Cje be?
9.25 A particular small-geometry BJT has fT of 8 GHz and Cμ = 0.1 pF when operated at IC = 1.0 mA. What is Cπ in this situa-tion? Also, find gm. For β = 160, find rπ and fβ.
9.26 For a BJT whose unity-gain bandwidth is 2 GHz and β0 = 200, at what frequency does the magnitude of hfe become 20?
What is fβ?
9.27 For a sufficiently high frequency, measurement of the complex input impedance of a BJT having (ac) grounded emitter and collector yields a real part approximating rx. For what frequency, defined in terms of ωβ, is such an estimate of rx good to within 10% under the condition that 9.28 Complete the table entries below for transistors (a) through (g), under the conditions indicated. Neglect rx.
χ γ 2 2φf VSB + ( ) ⁄ .) = fT gm 2π Cgs Cgd + ( ) ----------------------------------= fT 1.5 πL ------- μnID 2CoxWL --------------------fT gm 2π Cgs Cgd + ( ) ------------------------------------= fT 3μnVOV 4πL 2 ------------------A0 fT Lov 0.1 = μn 450 = V′ A 5 = VOV 0.2 = A0 fT L Lmin = Lmin Lmin Lmin Lmin rx rπ 10 ⁄ ?
≤ Transistor IE(mA) re(V) gm (mA/V) r p k(V) b0 fT (MHz) Cm (pF) Cp (pF) fb (MHz) (a) 1 100 400 2 (b) 25 2 10.7 4 (c) 2.525 400 13.84 (d) 10 100 400 2 (e) 0.1 100 100 2 (f) 1 10 400 2 (g) 800 1 9 80 Problems 789 CHAPTER 9 PR OBLE MS Section 9.3: High-Frequency Response of the CS and CE Amplifiers 9.29 In a particular common-source amplifier for which the midband voltage gain between gate and drain (i.e., ) is V/V, the NMOS transistor has pF and pF. What input capacitance would you expect? For what range of signal-source resistances can you expect the 3-dB frequency to exceed 10 MHz? Neglect the effect of .
D 9.30 A design is required for a CS amplifier for which the MOSFET is operated at mA/V and has pF and pF. The amplifier is fed with a signal source hav-ing k , and is very large. What is the largest value of for which the upper 3-dB frequency is at least 10 MHz? What is the corresponding value of midband gain and gain–bandwidth product? If the specification on the upper 3-dB frequency can be relaxed by a factor of 3, that is, to (10/3) MHz, what can and GB become?
9.31 Reconsider Example 9.3 for the situation in which the transistor is replaced by one whose width W is half that of the original transistor while the bias current remains unchanged. Find modified values for all the device parame-ters along with , , and the gain–bandwidth product, GB. Contrast this with the original design by calculating the ratios of new value to old for W, , , , , , , , and GB.
D 9.32 In a CS amplifier, such as that in Fig. 9.2(a), the resis-tance of the source Rsig = 100 kΩ, amplifier input resistance (which is due to the biasing network) Rin = 100 kΩ, Cgs = 1 pF, Cgd = 0.2 pF, gm = 3 mA/V, ro = 50 kΩ, RD = 8 kΩ, and RL = 10 kΩ. Determine the expected 3-dB cutoff frequency fH and the midband gain. In evaluating ways to double fH , a designer considers the alternatives of changing either RL or Rin. To raise fH as described, what separate change in each would be required? What midband voltage gain results in each case?
9.33 A discrete MOSFET common-source amplifier has RG = 1 MΩ, gm = 5 mA/V, ro = 100 kΩ, RD = 10 kΩ, Cgs = 2 pF, and Cgd = 0.4 pF. The amplifier is fed from a voltage source with an internal resistance of 500 kΩ and is connected to a 10-kΩ load. Find: (a) the overall midband gain AM (b) the upper 3-dB frequency fH 9.34 The analysis of the high-frequency response of the com-mon-source amplifier, presented in the text, is based on the assumption that the resistance of the signal source, Rsig, is large and, thus, that its interaction with the input capacitance Cin pro-duces the “dominant pole” that determines the upper 3-dB fre-quency fH. In some situations, however, the CS amplifier is fed with a very low Rsig. To investigate the high-frequency response of the amplifier in such a case, Fig. P9.34 shows the equivalent circuit when the CS amplifier is fed with an ideal voltage source Vsig having Rsig = 0. Note that CL denotes the total capac-itance at the output node. By writing a node equation at the out-put, show that the transfer function Vo/Vsig is given by At frequencies ω , the s term in the numerator can be neglected. In such case, what is the upper 3-dB frequency resulting? Compute the values of AM and fH for the case: Cgd = 0.4 pF, CL = 2 pF, gm = 5 mA/V, and RL′ = 5 kΩ.
9.35 The NMOS transistor in the discrete CS amplifier circuit of Fig. P9.3 is biased to have gm = 1 mA/V and ro = 100 kΩ. Find AM. If Cgs = 1 pF and Cgd = 0.2 pF, find fH.
9.36 A designer wishes to investigate the effect of changing the bias current I on the midband gain and high-frequency response of the CE amplifier considered in Example 9.4. Let I be doubled to 2 mA, and assume that β0 and fT remain unchanged at 100 and 800 MHz, respectively. To keep the node voltages nearly unchanged, the designer reduces RB and RC by a factor of 2, to 50 kΩ and 4 kΩ, respectively. Assume rx = 50 Ω, and recall that VA = 100 V and that Cμ remains constant at 1 pF.
As before, the amplifier is fed with a source having Rsig = 5 kΩ and feeds a load RL = 5 kΩ. Find the new values of AM, fH, and the gain–bandwidth product, Comment on the results.
Note that the price paid for whatever improvement in perfor-mance is achieved is an increase in power. By what factor does the power dissipation increase?
9.37 The purpose of this problem is to investigate the high-frequency response of the CE amplifier when it is fed with a relatively large source resistance Rsig. Refer to the amplifier in Fig. 9.4 (a) and to its high-frequency, equivalent-circuit model and the analysis shown in Fig. 9.14. Let and Under these conditions, show that: (a) the midband gain (b) the upper 3-dB frequency (c) the gain–bandwidth product Evaluate this approximate value of the gain–bandwidth product for the case Rsig = 25 kΩ and Cμ = 1 pF. Now, if the transistor is biased at IC = 1 mA and has β = 100, find the midband gain and fH for the two cases and . On gmR′ L – 29 – Cgs 0.5 = Cgd 0.1 = RG gm 5 = Cgs 5 = Cgd 1 = Rsig 1 = Ω RG R′ L AM AM fH VOV gm Cgs Cgd Cin AM fH Figure P9.34 Vo Vsig ---------gmR′ L 1 s Cgd gm ⁄ ( ) – 1 s CL Cgd + ( )R′ L + ----------------------------------------------– = gm Cgd ⁄ ( ) R L V sig V o V gs Cgs gmV gs Cgd CL AM f H.
RB Rsig, rx Rsig, Rsig rπ, gmRL ′ 1, gmRL ′ Cμ Cπ.
AM β – RL ′ Rsig ⁄ fH 1 2πCμβRL ′ ⁄ AM f H 1 2πCμRsig ⁄ RL ′ 25 kΩ = RL ′ 2.5 kΩ = 790 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS the same coordinates, sketch Bode plots for the gain magnitude versus frequency for the two cases. What fH is obtained when the gain is unity? What value of corresponds?
9.38 For a version of the CE amplifier circuit in Fig. P9.11, Rsig = 10 kΩ, R1 = 68 kΩ, R2 = 27 kΩ, RE = 2.2 kΩ, RC = 4.7 kΩ, and RL = 10 kΩ. The collector current is 0.8 mA, β = 200, fT = 1 GHz, and Cμ = 0.8 pF. Neglecting the effect of rx and ro, find the midband voltage gain and the upper 3-dB frequency fH.
9.39 A particular BJT operating at 2 mA is specified to have GHz, pF, , and . The device is used in a CE amplifier operating from a very-low-resistance voltage source. (a) If the midband gain obtained is V/V, what is the value of ? (b) If the midband gain is reduced to V/V (by changing ), what is obtained?
9.40 Repeat Example 9.4 for the situation in which the power supplies are reduced to V and the bias current is reduced to 0.5 mA. Assume that all other component values and transistor parameter values remain unchanged. Find , , and the gain–bandwidth product and compare to the values obtained in Example 9.4.
9.41 The amplifier shown in Fig. P9.41 has Rsig = RL = 1 kΩ, RC = 1 kΩ, RB = 47 kΩ, β = 100, Cμ = 0.8 pF, and fT = 600 MHz. Assume the coupling capacitors to be very large.
(a) Find the dc collector current of the transistor.
(b) Find gm and rπ.
(c) Neglecting ro, find the midband voltage gain from base to collector (neglect the effect of RB).
(d) Use the gain obtained in (c) to find the component of Rin that arises as a result of RB. Hence find Rin.
(e) Find the overall gain at midband.
(f) Find Cin.
(g) Find fH.
9.42 Figure P9.42 shows a diode-connected transistor with the bias circuit omitted. Utilizing the BJT high-frequency, hybrid-π model with rx = 0 and ro = ∞, derive an expression for Zi(s) as a function of re and Cπ. Find the frequency at which the impedance has a phase angle of 45° for the case in which the BJT has fT = 400 MHz and the bias current is relatively high.
What is the frequency when the bias current is reduced so that Cπ Cμ? Assume α = 1.
Section 9.4: Useful Tools for the Analysis of the High-Frequency Response of Amplifiers 9.43 A direct-coupled amplifier has a low-frequency gain of 40 dB, poles at 1 MHz and 10 MHz, a zero on the negative real axis at 100 MHz, and another zero at infinite frequency.
Express the amplifier gain function in the form of Eqs. (9.61) and (9.62), and sketch a Bode plot for the gain magnitude.
What do you estimate the 3-dB frequency to be?
9.44 An amplifier with a dc gain of 60 dB has a single-pole high-frequency response with a 3-dB frequency of 10 kHz. (a) Give an expression for the gain function A(s).
(b) Sketch Bode diagrams for the gain magnitude and phase. (c) What is the gain–bandwidth product?
(d) What is the unity-gain frequency?
(e) If a change in the amplifier circuit causes its transfer func-tion to acquire another pole at 100 kHz, sketch the resulting gain magnitude and specify the unity-gain frequency. Note that this is an example of an amplifier with a unity-gain band-width that is different from its gain–bandwidth product.
9.45 Consider an amplifier whose is given by with . Find the ratio for which the value of the 3-dB frequency calculated using the domi-nant-pole approximation differs from that calculated using the root-sum-of-squares formula (Eq. 9.68) by: Figure P9.41 RL ′ fT 2 = Cμ 1 = rx 100 Ω = β 120 = 10 – fH 1 – R′ L fH 5 ± AM fH Rsig CC1 Vsig RC 1.5 V CC2 Vo Rin RB RL Figure P9.42 fH FH s ( ) FH s ( ) = 1 1 s ωP1 ---------+ ⎝ ⎠ ⎛ ⎞1 s ωP2 ---------+ ⎝ ⎠ ⎛ ⎞ ------------------------------------------------ωP1 ωP2 < ωP2 ωP1 ⁄ ωH Problems 791 CHAPTER 9 PR OBLE MS (a) 10% (b) 1% 9.46 The high-frequency response of a direct-coupled ampli-fier having a dc gain of −1000 V/V incorporates zeros at ∞ and 105 rad/s (one at each frequency) and poles at 104 rad/s and 106 rad/s (one at each frequency). Write an expression for the amplifier transfer function. Find using (a) the dominant-pole approximation (b) the root-sum-of-squares approximation (Eq. 9.68).
If a way is found to lower the frequency of the finite zero to 104 rad/s, what does the transfer function become? What is the 3-dB frequency of the resulting amplifier?
9.47 A direct-coupled amplifier has a dominant pole at 1000 rad/s and three coincident poles at a much higher fre-quency. These nondominant poles cause the phase lag of the amplifier at high frequencies to exceed the 90° angle due to the dominant pole. It is required to limit the excess phase at ω = 107 rad/s to 30° (i.e., to limit the total phase angle to −120°). Find the corresponding frequency of the nondominant poles.
D 9.48 Refer to Example 9.6. Give an expression for in terms of , (note that ), and gm. If all component values except for the generator resis-tance Rsig are left unchanged, to what value must Rsig be reduced in order to raise fH to 200 kHz?
9.49 (a) For the amplifier circuit in Example 9.6, find the expression for using symbols (as opposed to numbers).
(b) For the same circuit, use the approximate method of the previous section to determine an expression for and hence the effective time constant that can be used to find as . Compare this expression of τ with that of τH in (a). What is the difference? Compute the value of the difference and express it as a percentage of τ.
9.50 If a capacitor pF is connected across the output terminals of the amplifier in Example 9.6, find the resulting increase in and hence the new value of .
9.51 A FET amplifier resembling that in Example 9.6, when operated at lower currents in a higher-impedance application, has , , mA/V, , and pF. Find the midband voltage gain AM and the 3-dB frequency fH.
9.52 Figure P9.52 shows the high-frequency equivalent cir-cuit of a CS amplifier with a resistance Rs connected in the source lead. The purpose of this problem is to show that the value of Rs can be used to control the gain and bandwidth of the amplifier, specifically to allow the designer to trade gain for increased bandwidth.
(a) Derive an expression for the low-frequency voltage gain (set and to zero).
(b) To be able to determine using the open-circuit time-constants method, derive expressions for and .
(c) Let , , and pF. Use the expressions found in (a) and (b) to determine the low-frequency gain and the 3-dB frequency fH for three cases: , 100 Ω, and 250 Ω.
In each case also evaluate the gain–bandwidth product.
Comment.
9.53 A common-source MOS amplifier, whose equivalent circuit resembles that in Fig. 9.16(a), is to be evaluated for its high-frequency response. For this particular design, , , , , Cgd = 0.1 pF, and gm = 0.5 mA/V. Estimate the midband gain and the 3-dB frequency.
9.54 For a particular amplifier modeled by the circuit of Fig.
9.16(a), gm = 5 mA/V, , RG = 0.65 MΩ, , , and . There is also a load capacitance of 30 pF. Find the corresponding mid-band voltage gain, the open-circuit time constants, and an esti-mate of the 3-dB frequency.
9.55 Consider the high-frequency response of an amplifier consisting of two identical stages in cascade, each with an input resistance of 10 kΩ and an output resistance of 2 kΩ. The two-stage amplifier is driven from a 5-kΩ source and drives a ωH ωH Cgs R′ sig R′ sig = RG Rsig || Cgd, RL, ′ τH Cin τ Cin R′ sig = ωH 1 τ ⁄ CL 20 = τH fH Rsig = 100 kΩ Rin = 1.0 MΩ gm = 2 RL ′ = 15 kΩ Cgs = Cgd 1 = Cgs Cgd ωH Rgs Rgd Rsig = 100 kΩ gm = 4 mA/V, RL ′ 5 kΩ = Cgs = Cgd = 1 Rs = 0 Ω Rsig = 1 MΩ RG = 4 MΩ RL ′ = 100 kΩ Cgs = 0.2 pF Rsig = 150 kΩ RL ′ = 10 kΩ Cgs = 2 pF Cgd = 0.5 pF Figure P9.52 Cgs Vgs Vsig Rsig R9 L S Vo Cgd gmVgs G D Rs 792 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS 1-kΩ load. Associated with each stage is a parasitic input capacitance (to ground) of 10 pF and a parasitic output capaci-tance (to ground) of 2 pF. Parasitic capacitances of 5 pF and 7 pF also are associated with the signal-source and load connec-tions, respectively. For this arrangement, find the three poles and estimate the 3-dB frequency fH.
9.56 Consider an ideal voltage amplifier with a gain of 0.9 V/ V and a resistance R = 100 kΩ connected in the feedback path—that is, between the output and input terminals. Use Miller’s theorem to find the input resistance of this circuit.
9.57 An ideal voltage amplifier with a voltage gain of − 1000 V/V has a 0.2-pF capacitance connected between its out-put and input terminals. What is the input capacitance of the amplifier? If the amplifier is fed from a voltage source having a resistance , find the transfer function as a function of the complex-frequency variable s and hence the 3-dB frequency fH and the unity-gain frequency ft.
9.58 The amplifiers listed below are characterized by the descriptor (A, C), where A is the voltage gain from input to output and C is an internal capacitor connected between input and output. For each, find the equivalent capacitances at the input and at the output as provided by the use of Miller’s theorem: (a) −1000 V/V, 1 pF (b) −10 V/V, 10 pF (c) −1 V/V, 10 pF (d) +1 V/V, 10 pF (e) +10 V/V, 10 pF Note that the input capacitance found in case (e) can be used to cancel the effect of other capacitance connected from input to ground. In (e), what capacitance can be canceled?
9.59 Figure P9.59 shows an ideal voltage amplifier with a gain of +2 V/V (usually implemented with an op amp con-nected in the noninverting configuration) and a resistance R connected between output and input.
(a) Using Miller’s theorem, show that the input resistance (b) Use Norton’s theorem to replace , , and with a signal current source and an equivalent parallel resis-tance. Show that by selecting , the equivalent paral-lel resistance becomes infinite and the current IL into the load impedance ZL becomes . The circuit then func-tions as an ideal voltage-controlled current source with an output current IL.
(c) If ZL is a capacitor C, find the transfer function and show it is that of an ideal noninverting integrator.
Section 9.5: A Closer Look at the High-Frequency Response of the CS and CE Amplifiers 9.60 A CS amplifier that can be represented by the equiva-lent circuit of Fig. 9.19 has and Find the midband gain AM , the input capacitance Cin using the Miller approximation, and hence an estimate of the 3-dB frequency fH.
Also, obtain a better estimate of fH using Miller’s theorem.
9.61 A CS amplifier that can be represented by the equiva-lent circuit of Fig. 9.19 has and Find the midband AM gain, and estimate the 3-dB frequency fH using the method of open-circuit time constants. Also, give the per-centage contribution to by each of three capacitances. (Note that this is the same amplifier considered in Problem 9.60; if you have solved Problem 9.60, compare your results.) 9.62 A CS amplifier represented by the equivalent circuit of Fig. 9.19 has 4 mA/V, and Find the exact val-ues of fZ, fP1, and fP2 using Eq. (9.88), and hence estimate fH.
Compare the values of fP1 and fP2 to the approximate values obtained using Eqs. (9.94) and (9.95). (Note that this is the same amplifier considered in Problems 9.60 and 9.61; if you have solved either or both of these problems, compare your results.) 9.63 A CS amplifier represented by the equivalent circuit of Fig. 9.19 has 4 mA/V, and It is required to find AM, fH, and the gain–bandwidth product for each of the fol-lowing values of : 5 kΩ, 10 kΩ, and 20 kΩ. Use the approximate expression for fP1 in Eq. (9.94). However, in each case, also evaluate fP2 and fZ to ensure that a dominant pole exists, and in each case, state whether the unity-gain frequency is equal to the gain–bandwidth product. Present your results in tabular form, and comment on the gain– bandwidth trade-off.
9.64 A common-emitter amplifier that can be represented by the equivalent circuit of Fig. 9.24(a) has 0.3 pF, Figure P9.59 Vsig Rsig = 1 kΩ V o Vsig ⁄ Rin = R – .
Vsig Vo Rsig R 2 Rin IL ZL V sig Rsig Rin Rsig = R V sig R ⁄ V o Vsig ⁄ Cgs = 2 pF, Cgd = 0.1 pF, CL = 2 pF, gm = 4 mA/V, R′ sig = RL ′ = 20 kΩ.
Cgs = 2 pF, Cgd = 0.1 pF, CL = 2 pF, gm = 4 mA/V, R′ sig = RL ′ = 20 kΩ.
τH Cgs = 2 pF, Cgd = 0.1 pF, , CL = 2 pF, gm = R′ sig = RL ′ = 20 kΩ.
Cgs = 2 pF, Cgd 0.1 pF, = CL = 2 pF, gm = R ′sig 20 kΩ.
= RL ′ Cπ = 10 pF, Cμ = CL = 3 pF, gm = 40 mA/V, β = 100, Problems 793 CHAPTER 9 PR OBLE MS and Find the mid-band gain AM, and an estimate of the 3-dB frequency fH using the Miller approximation. Also, obtain a better esti-mate of fH using Miller’s theorem.
9.65 A common-emitter amplifier that can be represented by the equivalent circuit of Fig. 9.24(a) has pF, pF, pF, mA/V, , , k , and k . Find the midband gain , and estimate the 3-dB frequency using the method of open-circuit time constants. Also give the per-centage contribution to of each of the three capacitances.
(Note that this is the same amplifier considered in Problem 9.64; if you have solved this problem, compare your results.) 9.66 A common-emitter amplifier that can be represented by the equivalent circuit of Fig. 9.24(a) has 0.3 pF, and Find the mid-band gain AM, the frequency of the zero fZ, and the values of the pole frequencies fP1 and fP2. Hence, estimate the 3-dB fre-quency fH. (Note that this is the same amplifier considered in Problems 6.64 and 9.65; if you have solved these problems, compare your results.) 9.67 For the current mirror in Fig. P9.67, derive an expres-sion for the current transfer function taking into account the BJT internal capacitances and neglecting and . Assume the BJTs to be identical. Observe that a signal ground appears at the collector of Q2. If the mirror is biased at 1 mA and the BJTs at this operating point are characterized by and find the frequen-cies of the pole and zero of the transfer function.
9.68 A CS amplifier modeled with the equivalent circuit of Fig 9.25(a) is specified to have , , gm = 4 mA/V, and . Find AM, f3dB, and ft.
9.69 It is required to analyze the high-frequency response of the CMOS amplifier shown in Fig. P9.69. The dc bias current is 100 μA. For Q1, μnCox = 90 μA/V2, VA = 12.8 V, W/L = 100 μm/1.6 μm, Cgs = 0.2 pF, Cgd = 0.015 pF, and Cdb = 20 fF. For Q2, Cgd = 0.015 pF, Cdb = 36 fF, and Assume that the resistance of the input signal generator is negli-gibly small. Also, for simplicity, assume that the signal voltage at the gate of Q2 is zero. Find the low-frequency gain, the fre-quency of the pole, and the frequency of the zero.
9.70 This problem investigates the use of MOSFETs in the design of wideband amplifiers (Steininger, 1990). Such ampli-fiers can be realized by cascading low-gain stages.
(a) Show that for the case Cgd Cgs and the gain of the common-source amplifier is low so that the Miller effect is negligible, the MOSFET can be modeled by the approxi-mate equivalent circuit shown in Fig. P9.70(a), where ωT is the unity-gain frequency of the MOSFET.
(b) Figure P9.70(b) shows an amplifier stage suitable for the realization of low gain and wide bandwidth. Transistors Q1 and Q2 have the same channel length L but different widths W1 and W2. They are biased at the same VGS and have the same fT. Use the MOSFET equivalent circuit of Fig.
P9.70(a) to model this amplifier stage assuming that its out-put is connected to the input of an identical stage. Show that the voltage gain is given by where Figure P9.67 rx = 100 Ω, RL ′ = 5 kΩ, Rsig = 1 kΩ.
Cπ 10 = Cμ 0.3 = CL 3 = gm 40 = β 100 = rx 100 Ω = RL 5 = Ω Rsig 1 = Ω AM fH τH Cπ = 10 pF, Cμ = CL = 3 pF, gm = 40 mA/V, β = 100, rx = 100 Ω, RL ′ = 5 kΩ, Rsig = 1 kΩ.
Io s ( ) Ii ⁄ s ( ) rx ro fT = 400 MHz, Cμ = 2 pF, β0 = ∞, Cgs = 2 pF Cgd = 0.1 pF CL = 2 pF, RL ′ = 20 kΩ Figure P9.69 Q1 Q2 Q3 IBIAS Vo Vi VA = 19.2 V.
V o V i ⁄ Vo Vi ----- = − G0 1 s ωT/ G0 1 + ( ) -----------------------------+ ---------------------------------------G0 = gm1 gm2 -------- = W1 W2 -------794 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS (c) For L = 0.5 μm, W2 = 25 μm, fT = 12 GHz, and μnCox = 200 μA/V2, design the circuit to obtain a gain of 3 V/V per stage. Bias the MOSFETs at VOV = 0.3 V. Specify the required values of W1 and I. What is the 3-dB frequency achieved?
9.71 Consider an active-loaded common-emitter amplifier.
Let the amplifier be fed with an ideal voltage source Vi, and neglect the effect of rx. Assume that the bias current source has a very high resistance and that there is a capacitance CL present between the output node and ground. This capacitance repre-sents the sum of the input capacitance of the subsequent stage and the inevitable parasitic capacitance between collector and ground. Show that the voltage gain is given by If the transistor is biased at IC = 200 μA and VA = 100 V, Cμ = 0.2 pF, and CL = 1 pF, find the dc gain, the 3-dB frequency, the frequency of the zero, and the frequency at which the gain reduces to unity. Sketch a Bode plot for the gain magnitude.
9.72 A common-source amplifier fed with a low-resistance signal source and operating with has a unity-gain frequency of 2 GHz. What additional capacitance must be connected to the drain node to reduce ft to 1 GHz?
9.73 Consider a CS amplifier loaded in a current source with an output resistance equal to of the amplifying transistor.
The amplifier is fed from a signal source with .
The transistor is biased to operate at mA/V and k ; pF. Use the Miller approximation to determine an estimate of . Repeat for the following two cases: (i) the bias current I in the entire system is reduced by a factor of 4, and (ii) the bias current I in the entire system is increased by a factor of 4. Remember that both and will change as changes.
9.74 Use the method of open-circuit time constants to find for a CS amplifier for which mA/V, pF, k , k , and k for the following cases: (a) , (b) pF, and (c) pF. Compare with the value of obtained using the Miller approximation.
Section 9.6: High-Frequency Response of the Common-Gate and Cascode Amplifiers 9.75 A CG amplifier is specified to have 0.1 pF, , and Neglecting the effects of find the low-frequency gain the frequencies of the poles fP1 and fP2, and hence an estimate of the 3-dB frequency fH.
9.76 Sketch the high-frequency equivalent circuit of a CB amplifier fed from a signal generator characterized by and Rsig and feeding a load resistance RL in parallel with a capaci-tance CL. (a) Show that for the circuit can be separated into two parts: an input part that produces a pole at and an output part that forms a pole at Note that these are the bipolar counterparts of the MOS expressions in Eqs. (9.109) and (9.110).
(b) Evaluate and and hence obtain an estimate for fH for the case , and Also, find fT of the transistor.
9.77 Consider a CG amplifier loaded in a resistance and fed with a signal source having a resistance . Also let . Use the method of open-circuit time constants to show that for , the upper 3-dB frequency is related to the MOSFET by the approximate expression Figure P9.70 (a) (b) Vo Vi ----- = gmro 1 s Cμ /gm ( ) – 1 s CL + Cμ ( )ro + ----------------------------------------– gm = 2 mA/V ro Rsig ro 2 ⁄ = gm 2 = ro 20 = Ω Cgs Cgd 0.1 = = fH Rsig RL ro fH gm 1.5 = Cgs Cgd 0.2 = = ro 20 = Ω RL 12 = Ω Rsig 100 = Ω CL 0 = CL 10 = CL 50 = fH Cgs = 2 pF, Cgd = CL = 2 pF, gm = 4 mA/V, Rsig = 1 kΩ RL ′ = 20 kΩ.
ro, vo vsig ⁄ , Vsig ro = ∞ fP1 = 1 2πCπ Rsig re || ( ) -------------------------------------fP2 = 1 2π Cμ CL + ( )RL -------------------------------------fP1 fP2 Cπ = 14 pF, Cμ = 2 pF, CL = 1 pF, IC = 1 mA, Rsig = 1 kΩ RL = 10 kΩ. RL ro = Rsig ro 2 ⁄ = CL Cgs = gm ro 1 fT Problems 795 CHAPTER 9 PR OBLE MS 9.78 For the CG amplifier in Example 9.12, how much addi-tional capacitance should be connected between the output node and ground to reduce to 300 MHz?
9.79 Find the dc gain and the 3-dB frequency of a MOS cas-code amplifier operated at mA/V and k .
The MOSFETs have fF, fF, and fF. The amplifier is fed from a signal source with k and is connected to a load resistance of 2 M . There is also a load capacitance of 40 fF. 9.80 (a) Consider a CS amplifier having CL (including Cdb) = 1 pF, and Find the low-frequency gain AM, and estimate fH using open-circuit time constants. Hence determine the gain–bandwidth product.
(b) If a CG stage is cascaded with the CS transistor in (a) to cre-ate a cascode amplifier, determine the new values of AM, fH, and gain–bandwidth product. Assume RL remains unchanged. D 9.81 It is required to design a cascode amplifier to provide a dc gain of 74 dB when driven with a low-resistance generator and utilizing NMOS transistors for which = 50, and Assuming that determine the over-drive voltage and the drain current at which the MOSFETs should be operated. Find the unity-gain frequency and the 3-dB frequency. If the cascode transistor is removed and RL remains unchanged, what will the dc gain become? 9.82 Consider a bipolar cascode amplifier biased at a current of 1 mA. The transistors used have and rx = The amplifier is fed with a signal source having The load resistance Find the low-frequency gain AM, and estimate the value of the 3-dB frequency fH. 9.83 In this problem we consider the frequency response of the bipolar cascode amplifier in the case that ro can be neglected.
(a) Refer to the circuit in Fig. 9.31, and note that the total resis-tance between the collector of Q1 and ground will be equal to re2, which is usually very small. It follows that the pole intro-duced at this node will typically be at a very high frequency and thus will have negligible effect on fH. It also follows that at the frequencies of interest the gain from the base to the collector of Q1 will be Use this to find the capacitance at the input of Q1 and hence show that the pole introduced at the input node will have a frequency Then show that the pole introduced at the output node will have a frequency (b) Evaluate fP1 and fP2, and use the sum-of-the-squares for-mula to estimate fH for the amplifier with I = 1 mA, and in the following two cases: (i) (ii) 9.84 A BJT cascode amplifier uses transistors for which , V, GHz, and pF. It operates at a bias current of 0.1 mA between a source with and a load . Let and find the overall voltage gain at dc, , and .
Section 9.7: High-Frequency Response of the Source and Emitter Followers 9.85 A source follower has and Find AM, Ro, fZ, and fH. Also, find the percentage contribution of each of the three capacitances to the time-constant τH.
9.86 Using the expression for the source follower in Eq.
(9.129) show that for situations in which is large and is small, Find for the case k , k , k , mA/V, fF, and fF.
9.87 Refer to Fig. 9.32(b). In situations in which is large, the high-frequency response of the source follower is determined by the low-pass circuit formed by and the input capacitance. An estimate of can be obtained by using the Miller approximation to replace with an input capacitance where K is the gain from gate to source. Using the low-frequency value of find and hence and an estimate of . Is this estimate higher or lower than that obtained by the method of open-circuit time constants?
9.88 For an emitter follower biased at and having and using a transistor specified to have and evaluate the low-frequency gain AM and the 3-dB frequency fH.
fH fT gmro ( ) ⁄ = fH gm 1 = ro 50 = Ω Cgs 30 = Cgd 10 = Cdb 10 = Rsig 100 = Ω Ω CL Cgd = 0.2 pF, Rsig = RL = 20 kΩ, gm = 4 mA/V, Cgs = 2 pF, Cdb = 0.2 pF, ro = 20 kΩ.
V A = 10 V, μnCox = 200 μA/V 2, W L ⁄ Cgd = 0.1 pF, CL = 1 pF.
RL = Ro, β = 100, ro = 100 kΩ, Cπ = 14 pF, Cμ = 2 pF, Ccs = 0, 50 Ω.
Rsig = 4 kΩ.
RL 2.4 kΩ.
= gm1re2 1.
– – fP1 1 2πRsig ′ Cπ1 2Cμ1 + ( ) -------------------------------------------------fP2 1 2πRL CL Ccs2 Cμ2 + + ( ) --------------------------------------------------------Cπ = 5 pF, Cμ = 5 pF, Ccs = CL = 0, β = 100, rx = 0 Rsig = 1 kΩ Rsig = 10 kΩ β 100 = VA 100 = fT 1 = Cμ 0.1 = Rsig rπ = RL βro = CL Ccs 0 = = fH ft gm = 5 mA/V, ro = 20 kΩ, Rsig = 20 kΩ, RL = 2 kΩ, Cgs = 2 pF, Cgd = 0.1 pF, CL = 1 pF.
fH Rsig RL fH 1 2πRsig Cgd Cgs 1 gmR′L + ------------------------+ -------------------------------------------------------------fH Rsig 100 = Ω RL 1 = Ω ro 20 = Ω gm 5 = Cgd 10 = Cgs 30 = Rsig Rsig Cin Cgs Ceq Cgs 1 K – ( ) = K gm R′ L /(1 gmR′ L) + = Ceq Cin fH IC = 1mA Rsig = RL = 1 kΩ, fT = 2 GHz, Cμ = 0.1 pF, rx = 100 Ω, β = 100, VA = 20 V, 796 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS 9.89 For the emitter follower shown in Fig. P9.89, find the low-frequency gain and the 3-dB frequency fH for the fol-lowing three cases: (a) (b) (c) Let and Section 9.8: High-Frequency Response of Differential Amplifiers 9.90 A MOSFET differential amplifier such as that shown in Fig. 9.34(a) is biased with a current source I = 200 μA. The transistors have W/L = 25, VA = 200 V, Cgs = 40 fF, Cgd = 5 fF, and Cdb = 5 fF. The drain resistors are 20 kΩ each. Also, there is a 100-fF capacitive load between each drain and ground.
(a) Find VOV and gm for each transistor.
(b) Find the differential gain Ad.
(c) If the input signal source has a small resistance Rsig and thus the frequency response is determined primarily by the output pole, estimate the 3-dB frequency fH.
(d) If, in a different situation, the amplifier is fed symmetri-cally with a signal source of 40 kΩ resistance (i.e., 20 kΩ in series with each gate terminal), use the open-circuit time-constants method to estimate fH.
9.91 The amplifier specified in Problem 9.90 has RSS = 80 kΩ and CSS = 0.1 pF. Find the 3-dB frequency of the CMRR.
9.92 In a particular MOS differential amplifier design, the bias current μA is provided by a single transistor operating at V with V and output capacitance of 100 fF. What is the frequency of the common-mode gain zero at which begins to rise above its low-frequency value? To meet a requirement for reduced power supply, consideration is given to reducing to 0.2 V while keeping I unchanged. Assuming the current-source capacitance to be directly proportional to the device width, what is the impact on of this proposed change?
9.93 Repeat Exercise 9.27 for the situation in which the bias current is reduced to 80 μA and is raised to 20 k For (d), let be raised from 20 k to 100 k (Note: This is a low-voltage, low-power design.) 9.94 A BJT differential amplifier operating with a 1-mA cur-rent source uses transistors for which β = 100, fT = 600 MHz, Cμ = 0.5 pF, and rx = 100 Ω. Each of the collector resistances is 10 kΩ, and ro is very large. The amplifier is fed in a symmetri-cal fashion with a source resistance of 10 kΩ in series with each of the two input terminals.
(a) Sketch the differential half-circuit and its high-frequency equivalent circuit. (b) Determine the low-frequency value of the overall differ-ential gain.
(c) Use the Miller approximation to determine the input capacitance and hence estimate the 3-dB frequency fH and the gain–bandwidth product.
9.95 A differential amplifier is biased by a current source having an output resistance of 1 MΩ and an output capacitance of 1 pF. The differential gain exhibits a dominant pole at 2 MHz. What are the poles of the CMRR?
9.96 A current-mirror-loaded MOS differential amplifier is biased with a current source I = 0.2 mA. The two NMOS transistors of the differential pair are operating at VOV = 0.2 V, and the PMOS devices of the mirror are operating at |VOV| = 0.2 V. The Early voltage The total capacitance at the input node of the mirror is 0.1 pF and that at the output node of the amplifier is 0.2 pF. Find the dc value and the frequencies of the poles and zero of the differ-ential voltage gain.
9.97 Consider the active-loaded CMOS differential amplifier of Fig. 9.37(a) for the case of all transistors operated at the same and having the same Also let the total capacitance at the output node be four times the total capacitance at the input node of the current mirror and show that the unity-gain frequency of is For V, V, I = 0.2 mA, fF, and fF, find the dc value of , and the value of and and sketch a Bode plot for Section 9.9: Other Wideband Amplifier Configurations 9.98 A CS amplifier is specified to have gm = 5 mA/V, ro = 40 kΩ, Cgs = 2 pF, Cgd = 0.1 pF, CL = 1 pF, Rsig = 20 kΩ, and RL = 40 kΩ. Figure P9.89 Rsig = 1 kΩ Rsig = 10 kΩ Rsig = 100 kΩ β = 100, fT 400 MHz, = Cμ = 2 pF.
Vsig Rsig Vo 2 mA 1 k 10 V k′ n = 200 μA/V 2, I 100 = VOV 0.5 = VA 30 = CSS fZ ( ) Acm VOV fZ RD Ω.
Rsig Ω Ω.
VAn VAp 10 V.
= = VOV VA .
CL ( ) Cm, Ad gm 2πCL ⁄ .
VA 20 = VOV 0.2 = CL 100 = Cm 25 = Ad fP1, ft, fP2, fZ Ad .
Problems 797 CHAPTER 9 PR OBLE MS (a) Find the low-frequency gain AM, and use open-circuit time constants to estimate the 3-dB frequency fH. Hence determine the gain–bandwidth product.
(b) If a 500-Ω resistance is connected in the source lead, find the new values of fH, and the gain–bandwidth product. D 9.99 (a) Use the approximate expression in Eq. (9.161) to determine the gain–bandwidth product of a CS amplifier with a source-degeneration resistance. Assume and (b) If a low-frequency gain of 20 V/V is required, what fH corresponds?
(c) For and RL = 20 kΩ, find the required value of Rs.
9.100 For the CS amplifier with a source-degeneration resis-tance Rs, show for and that where D 9.101 It is required to generate a table of fH, and ft versus for a CS amplifier with a source-degener-ation resistance Rs. The table should have entries for . . . , 15. The amplifier is specified to have 5 mA/V, 20 kΩ, and Use the for-mula for τH given in the statement for Problem 9.100. If is required, find the value needed for Rs and the corresponding value of 9.102 In this problem we investigate the bandwidth exten-sion obtained by placing a source follower between the signal source and the input of the CS amplifier. (a) First consider the CS amplifier of Fig. P9.102(a). Show that where is the total capacitance between the output node and ground. Calculate the value of AM, fH, and the gain– bandwidth product for the case gm = 1 mA/V, ro = 20 k Rsig = 20 k fF, Cgd = 5 fF, and CL = 10 fF.
(b) For the CD-CS amplifier in Fig. P9.102(b), show that Calculate the values of and the gain–bandwidth product for the same parameter values used in (a). Compare with the results of (a).
AM , Cgd = 0.1 pF Rsig = 10 kΩ.
gm = 5 mA/V, A0 =100 V/V, Rsig Rs RL = ro τH CgsRsig 1 k 2 ⁄ ( ) + -----------------------CgdRsig 1 A0 2 k + -----------+ ⎝ ⎠ ⎛ ⎞ + CL Cgd + ( )ro 1 k + 2 k + -----------⎝ ⎠ ⎛ ⎞ + k gmRs ≡ AM , k gmRs ≡ k 0, 1, 2, = gm = ro = 40 kΩ, RL = 40 kΩ, Rsig = Cgs = 2 pF, Cgd = 0.1 pF, CL = 1 pF.
fH = 2 MHz AM .
AM gmro – = τH CgsRsig Cgd Rsig 1 gmro + ( ) ro + [ ] CLro + + = CL Ω, Ω, Cgs 20 = AM ro1 1 gm1 ⁄ ro1 + ---------------------------- gm2ro2 ( ) – = Figure P9.102 Vsig (a) Rsig I V o Vsig (b) Rsig Q1 I Q2 I Vo τH Cgd1Rsig Cgs1 Rsig ro1 + 1 gm1ro1 + -------------------------Cgs2 1 gm1 --------ro1 || ⎝ ⎠ ⎛ ⎞ + + = Cgd2 1 gm1 --------ro1 || ⎝ ⎠ ⎛ ⎞1 gm2ro2 + ( ) ro2 + + C + Lro2 AM, fH, 798 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS D 9.103 The transistor in the circuit of Fig. P9.103 have β0 = 100, VA = 100 V, Cμ = 0.2 pF, and Cje = 0.8 pF. At a bias current of 100 μA, fT = 400 MHz. (Note that the bias details are not shown.) (a) Find Rin and the midband gain.
(b) Find an estimate of the upper 3-dB frequency fH. Which capacitor dominates? Which one is the second most signifi-cant?
(Hint. Use the formulas in Example 9.15.) D 9.104 Consider the BiCMOS amplifier shown in Fig. P9.104. The BJT has β = 200, Cμ = 0.8 pF, and fT = 600 MHz. The NMOS transistor has Vt = 1 V, and Cgs = Cgd = 1 pF.
(a) Consider the dc bias circuit. Neglect the base current of Q2 in determining the current in Q1. Find the dc bias currents in Q1 and Q2, and show that they are approximately 100 μA and 1 mA, respectively.
(b) Evaluate the small-signal parameters of Q1 and Q2 at their bias points.
(c) Consider the circuit at midband frequencies. First, deter-mine the small-signal voltage gain Vo/Vi. (Note that RG can be neglected in this process.) Then use Miller’s theorem on RG to determine the amplifier input resistance Rin. Finally, determine the overall voltage gain Vo/Vsig.
(d) Consider the circuit at low frequencies. Determine the frequency of the poles due to C1 and C2, and hence estimate the lower 3-dB frequency, fL.
(e) Consider the circuit at higher frequencies. Use Miller’s theorem to replace RG with a resistance at the input. (The one at the output will be too large to matter.) Use open-circuit time constants to estimate fH.
(f) To considerably reduce the effect of RG on Rin and hence on amplifier performance, consider the effect of adding another 10-MΩ resistor in series with the existing one and placing a large bypass capacitor between their joint node and ground. What will Rin, AM, and fH become?
Figure P9.103 Rsig Vsig V BE = 0.7 V, kn ′ W/L = 2 mA/V 2, Figure P9.104 Rin C1 Vsig Vi 5 V 1 F 0.1 F Vo 1 k 100 k 6.8 k RG 10 M C2 Q2 Q1 3 k Problems 799 CHAPTER 9 PR OBLE MS 9.105 Consider the circuit of Fig. P9.105 for the case: I = 200 μA and VOV = 0.2 V, Rsig = 200 kΩ, RD = 50 kΩ, Cgs = Cgd = 1 pF. Find the dc gain, the high-frequency poles, and an esti-mate of fH.
9.106 For the amplifier in Fig. 9.41(a), let I = 1 mA, β = 120, fT = 700 MHz, and Cμ = 0.5 pF, and neglect rx and ro.
Assume that a load resistance of 10 kΩ is connected to the out-put terminal. If the amplifier is fed with a signal Vsig having a source resistance find AM and fH. 9.107 Consider the CD–CG amplifier of Fig. 9.41(c) for the case gm = 5 mA/V, Cgs = 2 pF, Cgd = 0.1 pF, CL (at the output node) = 1 pF, and Rsig = RL = 20 kΩ. Neglecting ro, find AM, and fH.
9.108 In each of the six circuits in Fig. P9.108 (p. 800), let β = 100, Cμ = 2 pF, and fT = 400 MHz, and neglect rx and ro.
Calculate the midband gain AM and the 3-dB frequency fH.
Section 9.10: Multistage Amplifier Examples 9.109 Use open-circuit time constants to obtain an expression for of the amplifier in Fig. 9.44. Compare to the expression in Eq. (9.176).
9.110 For the CMOS amplifier in Fig. 9.43, whose equiva-lent circuit is shown in Fig. 9.44, let mA/V, R1 = 100 kΩ, C1 = 0.1 pF, Gm2 = 2 mA/V, R2 = 50 kΩ, and pF.
(a) Find the dc gain.
(b) Without connected, find the frequencies of the two poles in radians per seconds and sketch a Bode plot for the gain magnitude.
(c) With connected, find . Then find the value of that will result in a unity-gain frequency at least two octaves below . For this value of , find and and sketch a Bode plot for the gain magnitude.
9.111 A CMOS op amp with the topology in Fig. 9.43 has mA/V, mA/V, the total capaci-tance between node and ground is 0.2 pF, and the total capacitance between the output node and ground is 3 pF. Find the value of that results in MHz and verify that is lower than and .
Q1 Q2 RD Rsig Vsig VDD Vo I Figure P9.105 Rsig = 20 kΩ, ωH Gm1 1 = C2 2 = CC CC ωP2 CC ωt ωP2 CC ωP1 ωZ gm1 gm2 1 = = gm6 3 = D2 CC ft 50 = ft fZ fP2 800 Chapter 9 Frequency Response CHAPTER 9 P ROBL EMS Figure P9.108 Vsig Vo (a) Vsig Vo (b) Vsig Vo (c) Vsig Vo (d) Vsig Vo (e) Vsig Vo (f) Problems 801 CHAPTER 9 PR OBLE MS 9.112 Figure P9.112 shows an amplifier formed by cascading two CS stages. Note that the input bias voltage is not shown.
Each of and is operated at an overdrive voltage of 0.2 V, and V. The transistor capacitances are as fol-lows: fF, fF, and fF.
(a) Find the dc voltage gain.
(b) Find the input capacitance at the gate of using the Miller approximation.
(c) Use the capacitance in (b) to determine the frequency of the pole formed at the amplifier input. Let k .
(d) Use the Miller approximation to find the input capacitance of and hence determine the total capacitance at the drain of (e) Use the capacitance found in (d) to obtain the frequency of the pole formed at the interface between the two stages.
(f) Determine the total capacitance at the output node and hence estimate the frequency of the pole formed at the out-put node.
(g) Does the amplifier have a dominant pole? If so, at what frequency Q1 Q2 VA 10 = Cgs 20 = Cgd 5 = Cdb 5 = Q1, Rsig 10 = Ω Q2 Q1.
Figure P9.112 Q2 Q1 0.1 mA 0.1 mA V o Vsig Rsig V DD CHAPTER 10 Feedback Introduction 803 10.1 The General Feedback Structure 804 10.2 Some Properties of Negative Feedback 809 10.3 The Four Basic Feedback Topologies 814 10.4 The Feedback Voltage Amplifier (Series—Shunt) 823 10.5 The Feedback Transconductance Amplifier (Series—Series) 834 10.6 The Feedback Transresistance Amplifier (Shunt—Shunt) 846 10.7 The Feedback Current Amplifier (Shunt—Series) 855 10.8 Summary of the Feedback Analysis Method 863 10.9 Determining the Loop Gain 863 10.10 The Stability Problem 868 10.11 Effect of Feedback on the Amplifier Poles 870 10.12 Stability Study Using Bode Plots 879 10.13 Frequency Compensation 884 Summary 890 Problems 890 803 IN THIS CHAPTER YOU WILL LEARN 1. The general structure of the negative-feedback amplifier and the basic principle that underlies its operation.
2. The advantages of negative feedback, how these come about, and at what cost.
3. The appropriate feedback topology to employ with each of the four am-plifier types: voltage, current, transconductance, and transresistance amplifiers.
4. An intuitive and insightful approach for the analysis of practical feedback-amplifier circuits.
5. Why and how negative-feedback amplifiers can become unstable (i.e., oscillate) and how to design the circuit to ensure stable performance.
Introduction Most physical systems incorporate some form of feedback. It is interesting to note, though, that the theory of negative feedback has been developed by electronics engineers. In his search for methods for the design of amplifiers with stable gain for use in telephone repeaters, Harold Black, an electronics engineer with the Western Electric Company, invented the feedback amplifier in 1928. Since then the technique has been so widely used that it is almost impossible to think of electronic circuits without some form of feedback, either implicit or explicit. Furthermore, the concept of feedback and its associated theory are currently used in areas other than engineering, such as in the modeling of biological systems.
Feedback can be either negative (degenerative) or positive (regenerative). In amplifier design, negative feedback is applied to effect one or more of the following properties: 1. Desensitize the gain: that is, make the value of the gain less sensitive to variations in the values of circuit components, such as might be caused by changes in temper-ature.
2. Reduce nonlinear distortion: that is, make the output proportional to the input (in other words, make the gain constant, independent of signal level).
3. Reduce the effect of noise: that is, minimize the contribution to the output of unwanted electric signals generated, either by the circuit components themselves, or by extraneous interference.
804 Chapter 10 Feedback 4. Control the input and output resistances: that is, raise or lower the input and output resistances by the selection of an appropriate feedback topology.
5. Extend the bandwidth of the amplifier.
All of the desirable properties above are obtained at the expense of a reduction in gain. It will be shown that the gain-reduction factor, called the amount of feedback, is the factor by which the circuit is desensitized, by which the input resistance of a voltage amplifier is increased, by which the bandwidth is extended, and so on. In short, the basic idea of nega-tive feedback is to trade off gain for other desirable properties. This chapter is devoted to the study of negative-feedback amplifiers: their analysis, design, and characteristics.
Under certain conditions, the negative feedback in an amplifier can become positive and of such a magnitude as to cause oscillation. In fact, in Chapter 17 we will study the use of positive feedback in the design of oscillators and bistable circuits. Here, in this chapter, however, we are interested in the design of stable amplifiers. We shall therefore study the stability prob-lem of negative-feedback amplifiers and their potential for oscillation.
It should not be implied, however, that positive feedback always leads to instability. In fact, positive feedback is quite useful in a number of nonregenerative applications, such as the design of active filters, which are studied in Chapter 16.
Before we begin our study of negative feedback, we wish to remind the reader that we have already encountered negative feedback in a number of applications. Almost all op-amp circuits (Chapter 2) employ negative feedback. Another popular application of negative feedback is the use of the emitter resistance RE to stabilize the bias point of bipolar transis-tors and to increase the input resistance, bandwidth, and linearity of a BJT amplifier. In addition, the source follower and the emitter follower both employ a large amount of negative feedback. The question then arises about the need for a formal study of negative feedback. As will be appreciated by the end of this chapter, the formal study of feedback provides an invaluable tool for the analysis and design of electronic circuits. Also, the insight gained by thinking in terms of feedback can be extremely profitable.
10.1 The General Feedback Structure Figure 10.1 shows the basic structure of a feedback amplifier. Rather than showing voltages and currents, Fig. 10.1 is a signal-flow diagram, where each of the quantities x can repre-sent either a voltage or a current signal. The open-loop amplifier has a gain A; thus its output xo is related to the input xi by (10.1) Figure 10.1 General structure of the feedback amplifier. This is a signal-flow diagram, and the quantities x represent either voltage or current signals.
xo Axi = Source A Load Σ 10.1 The General Feedback Structure 805 The output xo is fed to the load as well as to a feedback network, which produces a sample of the output. This sample xf is related to xo by the feedback factor β, (10.2) The feedback signal xf is subtracted from the source signal xs, which is the input to the com-plete feedback amplifier,1 to produce the signal xi, which is the input to the basic amplifier, (10.3) Here we note that it is this subtraction that makes the feedback negative. In essence, nega-tive feedback reduces the signal that appears at the input of the basic amplifier.
Implicit in the description above is that the source, the load, and the feedback network do not load the basic amplifier. That is, the gain A does not depend on any of these three net-works. In practice this will not be the case, and we shall have to find a method for casting a real circuit into the ideal structure depicted in Fig. 10.1. Figure 10.1 also implies that the for-ward transmission occurs entirely through the basic amplifier and the reverse transmission occurs entirely through the feedback network.
The gain of the feedback amplifier can be obtained by combining Eqs. (10.1) through (10.3): (10.4) The quantity Aβ is called the loop gain, a name that follows from Fig. 10.1. For the feed-back to be negative, the loop gain Aβ must be positive; that is, the feedback signal xf should have the same sign as xs, thus resulting in a smaller difference signal xi. Equation (10.4) indi-cates that for positive Aβ the gain with feedback Af will be smaller than the open-loop gain A by a factor equal to 1 + Aβ, which is called the amount of feedback.
If, as is the case in many circuits, the loop gain Aβ is large, Aβ 1, then from Eq. (10.4) it follows that Af (10.5) which is a very interesting result: The gain of the feedback amplifier is almost entirely deter-mined by the feedback network. Since the feedback network usually consists of passive com-ponents, which usually can be chosen to be as accurate as one wishes, the advantage of negative feedback in obtaining accurate, predictable, and stable gain should be apparent. In other words, the overall gain will have very little dependence on the gain of the basic ampli-fier, A, a desirable property because the gain A is usually a function of many manufacturing and application parameters, some of which might have wide tolerances. We have seen a dra-matic illustration of all of these effects in op-amp circuits in Chapter 2, where the closed-loop gain (which is another name for the gain-with-feedback) is almost entirely determined by the feedback elements.
Equations (10.1) through (10.3) can be combined to obtain the following expression for the feedback signal xf: (10.6) 1In earlier chapters, we used the subscript “sig” for quantities associated with the signal source (e.g., vsig and Rsig). We did that to avoid confusion with the subscript “s,” which is usually used with FETs to de-note quantities associated with the source terminal of the transistor. At this point, however, it is expected that readers have become sufficiently familiar with the subject that the possibility of confusion is min-imal. Therefore, we will revert to using the simpler subscript s for signal-source quantities.
xf βxo = xi xs x f – = Af xo xs ----≡ A 1 Aβ + ----------------= 1 β ---xf Aβ 1 Aβ + ---------------- xs = 806 Chapter 10 Feedback Thus for Aβ 1 we see that xf xs, which implies that the signal xi at the input of the basic amplifier is reduced to almost zero. Thus if a large amount of negative feedback is employed, the feedback signal xf becomes an almost identical replica of the input signal xs. An outcome of this property is the tracking of the two input terminals of an op amp. The difference between xs and xf, which is xi, is sometimes referred to as the error signal. Accordingly, the input differencing circuit is often also called a comparison circuit. (It is also known as a mixer.) An expression for x i can be easily determined as (10.7) from which we can verify that for Aβ 1, xi becomes very small. Observe that negative feedback reduces the signal that appears at the input terminals of the basic amplifier by the amount of feedback, (1 + Aβ). As will be seen later, it is this reduction of input signal that results in the increased linearity of the feedback amplifier.2 2We have in fact already seen examples of this: adding a resistance Re in the emitter of a CE amplifier (or a resistance Rs in the source of a CS amplifier) increases the linearity of these amplifiers because for the same input signal as before, vbe and vgs are now smallar (by the amount of feedback).
xi 1 1 Aβ + ---------------- xs = The noninverting op-amp configuration shown in Fig. 10.2(a) provides a direct implementation of the feedback loop of Fig. 10.1.
Figure 10.2 (a) A non-inverting op-amp circuit for Example 10.1. (b) The circuit in (a) with the op-amp replaced with its equivalent circuit.
RL Rs Vs R1 R2 A Vo (a) Vs AVi R1 R2 Rs RL Vo V i V f (b) Example 10.1 10.1 The General Feedback Structure 807 (a) Assume that the op amp has infinite input resistance and zero output resistance. Find an expression for the feedback factor β.
(b) Find the condition under which the closed-loop gain is almost entirely determined by the feedback network.
(c) If the open-loop gain V/V, find to obtain a closed-loop gain of 10 V/V.
(d) What is the amount of feedback in decibels?
(e) If V, find , , and .
(f) If A decreases by 20%, what is the corresponding decrease in ?
Solution (a) To be able to see more clearly the direct correspondence between the circuit in Fig. 10.2(a) and the block diagram in Fig. 10.1, we replace the op amp with its equivalent-circuit model, as shown in Fig.
10.2(b). Since the op amp is assumed to have infinite input resistance and zero output resistance, its model is simply an ideal voltage-controlled voltage source of gain A. From Fig. 10.2(b) we observe that the feedback network, consisting of the voltage divider ( , ), is connected directly to the output and feeds a signal to the inverting input terminal of the op amp. It is important at this point to note that the zero output resistance of the op amp causes the output voltage to be A irrespective of the values of and and of . That is what we meant by the statement that in the block diagram of Fig. 10.1, the feedback network and the load are assumed not to load the basic amplifier. Now we can easily determine the feedback factor β from Let’s next examine how is subtracted from at the input side. The subtraction is effectively per-formed by the differential action of the op amp; by its very nature, a differential-input amplifier takes the difference between the signals at its two input terminals. Observe also that because the input resistance of the op amp is assumed to be infinite, no current flows in . Thus the value of has no bearing on ; or the source “does not load” the amplifier input. Similarly, because of the zero input current of the op amp, will depend only on the ratio and not on the absolute values of and .
(b) The closed-loop gain is given by To make nearly independent of A, we must ensure that the loop gain Aβ is much larger than unity, Since under such a condition, the condition can be stated as (c) For V/V and V/V, we see that , thus we can select and to obtain Af A 104 = R2 R1 ⁄ Af Vs 1 = Vo Vf Vi Af R1 R2 Vf Vi R1 R2 RL β Vf Vo -----R1 R1 R2 + ------------------= ≡ Vf Vs Rs Rs Vi Vf R1 R2 ⁄ R1 R2 Af Af A 1 Aβ + ----------------= Af Aβ 1 A R1 R1 R2 + ------------------⎝ ⎠ ⎛ ⎞ 1 Af 1 β ---R1 R2 + R1 ------------------1 R2 R1 -----+ = = A Af A 104 = Af 10 = A Af R1 R2 β 1 Af -----0.1 = = 808 Chapter 10 Feedback Example 10.1 continued Thus, which yields A more exact value for the ratio can be obtained from which results in and, (d) The amount of feedback is which is 60 dB.
(e) For V, V V Note that if we had used the approximate value of , we would have obtained V and V.
(f) If A decreases by 20%, thus becoming V/V the value of becomes V/V that is, it decreases by 0.025%, which is lower than the percentage change in A by approximately a factor .
1 β ---1 R2 R1 -----Af 10 = = + = R2 R1 ⁄ 9 = R2 R1 ⁄ Af A 1 Aβ + ----------------= 10 104 1 104β + ---------------------= β 0.0999 = R2 R1 -----9.01 = 1 Aβ A Af -----104 10 --------1000 = = = + Vs 1 = Vo AfVs 10 1 10 = × = = Vf βVo 0.0999 10 0.999 = × = = Vi Vo A -----10 104 --------0.001V = = = β 0.1 = Vf 1 = Vi 0 = A 0.8 104 × = Af Af 0.8 104 × 1 0.8 104 0.0999 × × + ------------------------------------------------------9.9975 = = 1 Aβ + ( ) 10.2 Some Properties of Negative Feedback 809 10.2 Some Properties of Negative Feedback The properties of negative feedback were mentioned in the Introduction. In the following, we shall consider some of these properties in more detail.
10.2.1 Gain Desensitivity The effect of negative feedback on desensitizing the closed-loop gain was demonstrated in Example 10.1, where we saw that a 20% reduction in the gain of the basic amplifier gave rise to only a 0.025% reduction in the gain of the closed-loop amplifier. This sensitivity-reduction property can be analytically established as follows.
Assume that β is constant. Taking differentials of both sides of Eq. (10.4) results in (10.8) Dividing Eq. (10.8) by Eq. (10.4) yields (10.9) which says that the percentage change in Af (due to variations in some circuit parameter) is smaller than the percentage change in A by a factor equal to the amount of feedback. For this reason, the amount of feedback, 1 + Aβ, is also known as the desensitivity factor.
10.1 Repeat Example 10.1, (c) to (f) for V/V.
Ans. (c) 10.11; (d) 20 dB; (e) 10 V, 0.9 V, 0.1 V; (f) 2.44% 10.2 Repeat Example 10.1, (c) to (f) for V/V. For (e) use V.
Ans. (c) 1110.1; (d) 20 dB; (e) 10 V, 0.009 V, 0.001 V; (f) 2.44% A 100 = Af 103 = Vs 0.01 = EXERCISES dAf dA 1 Aβ + ( ) 2 -----------------------= dAf Af --------1 1 Aβ + ( ) --------------------- dA A -------= 10.3 An amplifier with a nominal gain V/V exhibits a gain change of 10% as the operating temperature changes from C to C. If it is required to constrain the change to 0.1% by ap-plying negative feedback, what is the largest closed-loop gain possible? If three of these feedback amplifiers are placed in cascade, what overall gain and gain stability are achieved?
Ans. 10 V/V; 1000 V/V, with a maximum variability of 0.3% over the specified temperature range.
A 1000 = 25° 75° EXERCISE 810 Chapter 10 Feedback 10.2.2 Bandwidth Extension Consider an amplifier whose high-frequency response is characterized by a single pole. Its gain at mid and high frequencies can be expressed as (10.10) where AM denotes the midband gain and ωH is the upper 3-dB frequency. Application of neg-ative feedback, with a frequency-independent factor β, around this amplifier results in a closed-loop gain Af(s) given by Substituting for A(s) from Eq. (10.10) results, after a little manipulation, in (10.11) Thus the feedback amplifier will have a midband gain of and an upper 3-dB frequency ωHf given by (10.12) It follows that the upper 3-dB frequency is increased by a factor equal to the amount of feedback.
Similarly, it can be shown that if the open-loop gain is characterized by a dominant low-frequency pole giving rise to a lower 3-dB frequency ωL, then the feedback amplifier will have a lower 3-dB frequency ωLf, (10.13) Note that the amplifier bandwidth is increased by the same factor by which its midband gain is decreased, maintaining the gain–bandwidth product at a constant value. This point is further illustrated by the Bode Plot in Fig. 10.3.
Finally, note that the action of negative feedback in extending the amplifier bandwidth should not be surprising: Negative feedback works to minimize the change in gain magni-tude, including its change with frequency. A s ( ) AM 1 s ωH ⁄ + ----------------------= Af s ( ) A s ( ) 1 βA s ( ) + ------------------------= Af s ( ) AM 1 AMβ + ( ) ⁄ 1 s ωH ⁄ 1 AMβ + ( ) + -----------------------------------------------= AM 1 AMβ + ( ) ⁄ ωHf ωH 1 AMβ + ( ) = ωLf ωL 1 AMβ + -------------------= 10.4 Consider the noninverting op-amp circuit of Example 10.1. Let the open-loop gain A have a low-fre-quency value of 104 and a uniform –6-dB/octave rolloff at high frequencies with a 3-dB frequency of 100 Hz. Find the low-frequency gain and the upper 3-dB frequency of a closed-loop amplifier with R1 = 1 kΩ and R2 = 9 kΩ.
Ans. 9.99 V/V; 100.1 kHz EXERCISE 10.2 Some Properties of Negative Feedback 811 10.2.3 Interference Reduction Negative feedback can be employed to reduce the interference in an amplifier or, more pre-cisely, to increase the ratio of signal to interference. However, as we shall now explain, this interference-reduction process is possible only under certain conditions. Consider the situa-tion illustrated in Fig. 10.4. Figure 10.4(a) shows an amplifier with gain A1, an input signal Vs, and interference, Vn. It is assumed that for some reason this amplifier suffers from interference and that the interference can be assumed to be introduced at the input of the amplifier. The signal-to-interference ratio for this amplifier is (10.14) Consider next the circuit in Fig. 10.4(b). Here we assume that it is possible to build another amplifier stage with gain that does not suffer from the interference problem. If this is the case, then we may precede our original amplifier by the clean amplifier and apply negative feedback around the overall cascade of such an amount as to keep the overall gain constant. The output voltage of the circuit in Fig. 10.4(b) can be found by superposition: (10.15) Thus the signal-to-interference ratio at the output becomes (10.16) which is times higher than in the original case.
We emphasize once more that the improvement in signal-to-interference ratio by the application of feedback is possible only if one can precede the interference-prone stage Figure 10.3 Application of negative feedback reduces the midband gain, increases fH, and reduces fL, all by the same factor, (1+AMβ), which is equal to the amount of feedback. Af A 20 log (1 AMb) 20 log (AM) 20 dB/decade 20 dB/decade 20 log (AMf) log (1 AMb) fLf fLf fL fH fHf f (log scale) log (1 AMb) Gain (dB) fL 1 AMb AMf AM 1 AMb fHf fH (1 AMb) S/I Vs /Vn = A2 A1 A2 Vo = Vs A1A2 1 A1A2β + ------------------------V n A1 1 A1A2β + ------------------------+ S I --- = Vs V n -----A2 A2 812 Chapter 10 Feedback by a (relatively) interference-free stage. This situation, however, is not uncommon in practice. The best example is found in the output power-amplifier stage of an audio amplifier. Such a stage usually suffers from a problem known as power-supply hum.
The problem arises because of the large currents that this stage draws from the power supply and the difficulty of providing adequate power-supply filtering inexpensively.
The power-output stage is required to provide large power gain but little or no voltage gain. We may therefore precede the power-output stage by a small-signal amplifier that provides large voltage gain, and apply a large amount of negative feedback, thus restor-ing the voltage gain to its original value. Since the small-signal amplifier can be fed from another, less hefty (and hence better regulated) power supply, it will not suffer from the hum problem. The hum at the output will then be reduced by the amount of the voltage gain of this added preamplifier.
Figure 10.4 Illustrating the application of negative feedback to improve the signal-to-interference ratio in amplifiers.
(a) A1 (b) A2 A1 10.5 Consider a power-output stage with voltage gain an input signal and a hum of 1 V. Assume that this power stage is preceded by a small-signal stage with gain and that overall feedback with β = 1 is applied. If and remain unchanged, find the signal and inter-ference voltages at the output and hence the improvement in S/I.
Ans. 1 V; 0.01 V; 100 (40 dB) A1 = 1, V s = 1 V, V n A2 = 100 V/V V s V n EXERCISE 10.2 Some Properties of Negative Feedback 813 10.2.4 Reduction in Nonlinear Distortion Curve (a) in Fig. 10.5 shows the transfer characteristic vO versus vI of an amplifier. As indi-cated, the characteristic is piecewise linear, with the voltage gain changing from 1000 to 100 and then to 0. This nonlinear transfer characteristic will result in this amplifier generating a large amount of nonlinear distortion.
The amplifier transfer characteristic can be considerably linearized (i.e., made less non-linear) through the application of negative feedback. That this is possible should not be too surprising, since we have already seen that negative feedback reduces the dependence of the overall closed-loop amplifier gain on the open-loop gain of the basic amplifier. Thus large changes in open-loop gain (1000 to 100 in this case) give rise to much smaller corresponding changes in the closed-loop gain.
To illustrate, let us apply negative feedback with β = 0.01 to the amplifier whose open-loop voltage transfer characteristic is depicted in Fig. 10.5. The resulting transfer characteris-tic of the closed-loop amplifier, vO versus vS, is shown in Fig. 10.5 as curve (b). Here the slope of the steepest segment is given by and the slope of the next segment is given by Thus the order-of-magnitude change in slope has been considerably reduced. The price paid, of course, is a reduction in voltage gain. Thus if the overall gain has to be restored, a preamplifier should be added. This preamplifier should not present a severe nonlinear-distor-tion problem, since it will be dealing with smaller signals.
Figure 10.5 Illustrating the application of negative feedback to reduce the nonlinear distortion in ampli-fiers. Curve (a) shows the amplifier transfer characteristic (vO versus vI) without feedback. Curve (b) shows the characteristic (vO versus vS) with negative feedback (β = 0.01) applied.
vI, vS (V) Af 1 1000 1 1000 0.01 × + --------------------------------------90.9 = = Af 2 100 1 100 0.01 × + -----------------------------------50 = = 814 Chapter 10 Feedback Finally, it should be noted that negative feedback can do nothing at all about amplifier saturation, since in saturation the gain is very small (almost zero) and hence the amount of feedback is almost unity.
10.3 The Four Basic Feedback Topologies Based on the quantity to be amplified (voltage or current) and on the desired form of output (voltage or current), amplifiers can be classified into four categories. These categories were discussed in Chapter 1. In the following, we shall review this amplifier classification and point out the feedback topology appropriate in each case.
10.3.1 Voltage Amplifiers Voltage amplifiers are intended to amplify an input voltage signal and provide an output voltage signal. The voltage amplifier is essentially a voltage-controlled voltage source.
The input resistance is required to be high, and the output resistance is required to be low.
Since the signal source is essentially a voltage source, it is convenient to represent it in terms of a Thévenin equivalent circuit. In a voltage amplifier, the output quantity of inter-est is the output voltage. It follows that the feedback network should sample the output voltage, just as a voltmeter measures a voltage. Also, because of the Thévenin representa-tion of the source, the feedback signal xf should be a voltage that can be mixed with the source voltage in series.
The most suitable feedback topology for the voltage amplifier is the voltage-mixing, voltage-sampling one shown in Fig. 10.6. Because of the series connection at the input and the parallel or shunt connection at the output, this feedback topology is also known as series–shunt feedback. As will be shown, this topology not only stabilizes the voltage gain but also results in a higher input resistance (intuitively, a result of the series connection at the input) and a lower output resistance (intuitively, a result of the parallel connection at the output), which are desirable properties for a voltage amplifier.
Figure 10.6 Block diagram of a feedback voltage amplifier. Here the appropriate feedback topology is series–shunt.
Vf RL Rs 2 Vo Vs 1 Basic voltage amplifier Feedback network 10.3 The Four Basic Feedback Topologies 815 The increased input resistance results because subtracts from resulting in a smaller signal at the input of the basic amplifier. The lower in turn, causes the input current to be smaller, with the result that the resistance seen by will be larger. We shall derive a for-mula for the input resistance of the feedback voltage amplifier in the next section.
The decreased output resistance results because the feedback works to keep as con-stant as possible. Thus if the current drawn from the amplifier output changes by the change in will be lower than it would have been if feedback were not present. Thus the output resistance will be lower than that of the open-loop amplifier. In the fol-lowing section we shall derive an expression for the output resistance of the feedback volt-age amplifier.
Three examples of series–shunt feedback amplifiers are shown in Fig. 10.7. The ampli-fier in Fig. 10.7(a) is the familiar noninverting op-amp configuration. The feedback net-work, composed of the voltage divider (R1, R2), develops a voltage that is applied to the negative input terminal of the op amp. The subtraction of from is achieved by utiliz-ing the differencing action of the op-amp differential input. For the feedback to be negative, must be of the same polarity as thus resulting in a smaller signal at the input of the basic amplifier. To ascertain that this is the case, we follow the signal around the loop, as follows: As increases, increases and the voltage divider causes to increase. Thus the change in is of the same polarity as the change in and the feedback is negative.
The second feedback voltage amplifier, shown in Fig. 10.7(b), utilizes two MOSFET amplifier stages in cascade. The output voltage is sampled by the feedback network com-posed of the voltage divider ( ), and the feedback signal is fed to the source termi-nal of . The subtraction is implemented by applying to the gate of and to its source, with the result that the signal at this amplifier input . To ascertain that the feedback is negative, let increase. The drain voltage of will decrease, and since this is applied to the gate of , its drain voltage will increase. The feedback net-work will then cause to increase, which is the same change in polarity initially assumed for . Thus the feedback is indeed negative.
Figure 10.7 Examples of a feedback voltage amplifier. All these circuits employ series–shunt feedback.
Note that the dc bias circuits are only partially shown.
Vf Vs, Vi Vi, Vs V o Io, Δ Vo Δ Vo Vo Io Δ ⁄ Δ Vf Vf Vs Vf Vs, Vs Vo Vf V f V s, V o R1, R2 Vf Q1 Vs Q1 Vf Vi Vgs Vs Vf – = = Vs Q1 Q2 Vo Vf Vs R2 R1 Vo Vs Vi Vf (a) RD1 RD2 VDD Vi Q1 Vs Vo Vf R1 R2 Q2 (b) 816 Chapter 10 Feedback The third example of series–shunt feedback, shown in Fig. 10.7(c), utilizes a CG transis-tor Q with a fraction of the output voltage fed back to the gate through a voltage divider (R1, R2). Observe that the subtraction of from is effected by applying to the source, thus the input to the CG amplifier is obtained as . As usual, however, we must check the polarity of the feedback: If increases, (which is ) will increase and will correspondingly increase. Thus and change in the same direction, verifying that the feedback is negative.
10.3.2 Current Amplifiers The input signal in a current amplifier is essentially a current, and thus the signal source is most conveniently represented by its Norton equivalent. The output quantity of interest is current; hence the feedback network should sample the output current, just as a current meter measures a current. The feedback signal should be in current form so that it may be mixed in shunt with the source current. Thus the feedback topology most suitable for a cur-rent amplifier is the current-mixing, current-sampling topology, illustrated in Fig.
10.8(a). Because of the parallel (or shunt) connection at the input, and the series connection R2 R1 RD VDD Vi Vs Vo Vf Q (c) Figure 10.7 continued Vf V o Vf Vs Vs Vi Vs Vf – Vs Vd Vo Vf Vf Vs 10.6 For the circuit in Fig. 10.7(c) let Using small-signal analysis, find expressions for the open-loop gain the feedback factor and the closed loop gain . For find an approximate expression for . Neglect .
Ans.
; ; ; R1 R2 + ( ) RD.
A Vo Vi ⁄ ; ≡ β Vf Vo; ⁄ ≡ Af Vo Vs ⁄ ≡ Aβ 1, Af ro A gmRD = β R1 R1 R2 + ( ) ⁄ = Af gmRD 1 gmRDR1 R1 R2 + ( ) ⁄ + --------------------------------------------------------= 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ EXERCISE 10.3 The Four Basic Feedback Topologies 817 at the output, this feedback topology is also known as shunt–series feedback. As will be shown, this topology not only stabilizes the current gain but also results in a lower input resistance, and a higher output resistance, both desirable properties for a current amplifier.
The decrease in input resistance results because the feedback current subtracts from the input current , and thus a lower current enters the basic current amplifier. This in turn results in a lower voltage at the amplifier input, that is, across the current source . It fol-lows that the input resistance of the feedback current amplifier will be lower than that of the open-loop amplifier. We shall derive an expression for in Section 10.5.
The increase in output resistance is simply a result of the action of negative feedback in keeping the value of as constant as possible. Thus if the voltage across is changed, the resulting change in will be lower than it would have been without the feedback, which implies that the output resistance is increased. An expression for will be derived in Section 10.5.
Figure 10.8 (a) Block diagram of a feedback current amplifier. Here, the appropriate feedback topology is the shunt–series. (b) Example of a feedback current amplifier.
Io Io If If RL 2 Is Rs 1 Basic current amplifier Feedback network (a) RM RF RL If Ii Io RD VG VDD Is Q1 Q2 (b) If Is Is Rif Io RL Io Rof 818 Chapter 10 Feedback An example of a feedback current amplifier is shown in Fig. 10.8(b). It utilizes a CG stage followed by a CS stage The output current is fed to a load resistance A sample of is obtained by placing a small resistance in series with The voltage developed across is fed via a large resistance to the source node of . The feedback current that flows through is subtracted from at the source node, resulting in the input current . For the feedback to be negative, must have the same polarity as To ascertain that this is the case, we assume an increase in and follow the change around the loop: An increase in causes to increase and the drain voltage of will increase. Since this voltage is applied to the gate of the p-channel device , its increase will cause the drain current of to decrease. Thus, the voltage across will decrease, which will cause to increase. This is the same polarity assumed for the initial change in verifying that the feedback is indeed negative.
Q1 Q2.
Io RL.
Io RM RL.
RM RF Q1 If RF Is Ii Is If – = If Is.
Is Is Ii Q1 Q2 Io, Q2, RM If Is, For the feedback current amplifier shown in Fig 10.8(b), find expressions for the open-loop gain , the feedback factor and the closed-loop gain . For simplicity, neglect the Early effect in and Solution Figure 10.9 shows the circuit prepared for small-signal analysis. Some of the analysis is also indicated on the diagram. Since, as indicated, Figure 10.9 Analysis of the feedback current amplifier of Fig. 10.8(b) to obtain and A Io Ii ⁄ ≡ β If Io ⁄ ( ), = Af Io Is ⁄ ≡ Q1 Q2.
If Q1 Q2 RL RM RF Ii Io gm2vgs2 Vgs2 IiRD gm2IiRD Vi (very small) Ii Ii RD RD Is A Io Ii ⁄ ≡ β If Io ⁄ .
≡ Io gm2RDIi – = Example 10.2 10.3 The Four Basic Feedback Topologies 819 10.3.3 Transconductance Amplifiers In transconductance amplifiers the input signal is a voltage and the output signal is a current.
It follows that the appropriate feedback topology is the voltage-mixing, current-sampling topology, illustrated in Fig. 10.10(a). The presence of the series connection at both the input and the output gives this feedback topology the alternative name series–series feedback.
As in the case of the feedback voltage amplifier, the series connection at the input results in an increased input resistance. The sampling of the output current results in an increased output resistance. Thus the series–series feedback topology provides the transconductance amplifier with the desirable properties of increased input and output resistances.
Examples of feedback transconductance-amplifiers are shown in Fig. 10.10 (b) and (c).
The circuit in Fig. 10.10(b) utilizes a differential amplifier followed by a CS stage The output current is fed to and to a series resistance which develops a feedback voltage . The latter is applied to the positive input terminal of the differential amplifier . The subtraction of from is performed by the differencing action of the differential-amplifier input. At this point we must check that and have the same polarity: A positive change in will result in a negative change at the gate of which in turn causes to increase. The increase in results in a positive change in , which is the same polarity assumed for the change in verifying that the feedback is negative.
The transconductance amplpifier in Fig.10.10(c) utilizes a CS amplifier in cascade with another CS amplifier, The output current is fed to and to a series resistance the open-loop gain A is given by To obtain , we observe that is fed to a current divider formed by and . Since current mixing results in a reduced input resistance, the voltage at the source node of will be close to zero, and in effect appears in parallel with , enabling us to obtain as where the negative sign is a result of the reference directions used for and . Note, however, that the loop gain will be positive, as should always be the case in a negative feedback amplifier. We can now combine A and to obtain as A Io Ii ----gm2RD – = ≡ β Io RM RF Q2 RF RM β β If Io ---- RM RF RM + --------------------– ≡ Io If Aβ β Af Af Io Is ----gm2RD 1 gm2RD 1 RF RM -------+ ⎝ ⎠ ⎛ ⎞ + ----------------------------------------------------– = ≡ 10.7 For the feedback current amplifier of Fig. 10.8(b), analyzed in Example 10.2, find an approximate expression for the closed-loop current gain under the condition that the loop gain is large. Also, state the condition precisely.
Ans. Af 1 RF RM -------+ ⎝ ⎠ ⎛ ⎞; – gm2RD 1 RF RM -------+ ⎝ ⎠ ⎛ ⎞ EXERCISE A1 Q2.
Io RL RF, Vf A1 Vf Vs Vf Vs Vs Q2, Io Io Vf Vs, Q1 Q2.
Io RL 820 Chapter 10 Feedback that develops a feedback voltage . The latter is fed to the source of , thus utilizing the input of to implement the subtraction; . The reader is urged to verify that has the same polarity as and thus that the feedback is negative.
Figure 10.10 (a) Block diagram of a feedback transconductance amplifier. Here, the appropriate feedback topology is series–series. (b) Example of a feedback transconductance amplifier. (c) Another example.
Vf RL Rs 2 Vs 1 Basic transconductance amplifier Feedback network (a) Io Io Vs RL RF A1 Vi Vf (b) Q2 Io RD Io RL RF Vi Q1 Vs Vf Q2 (c) RF Vf Q1 Q1 Vi Vs Vf – = Vf Vs 10.8 For the circuit in Fig. 10.10(b), let the differential amplifier have an infinite input resistance.
Use small-signal analysis to obtain expressions for the open-loop gain , the feedback factor and the closed-loop gain . If the loop gain is much greater than unity, find an approximate expression for . Neglect Ans.
; ; ; A1 A Io Vi ⁄ ≡ β Vf Io ⁄ , ≡ Af Io Vs ⁄ ≡ Af ro2.
A A1gm2 = β RF = Af A1gm2 1 A1gm2RF + -------------------------------= Af 1 RF ⁄ EXERCISE 10.3 The Four Basic Feedback Topologies 821 10.3.4 Transresistance Amplifiers In transresistance amplifiers the input signal is current and the output signal is voltage.
It follows that the appropriate feedback topology is of the current-mixing, voltage-sampling type, shown in Fig. 10.11(a). The presence of the parallel (or shunt) connection at Figure 10.11 (a) Block diagram of a feedback transresistance amplifier. Here, the appropriate feedback topology is shunt–shunt. (b), (c), and (d) Examples of feedback transresistance amplifiers.
RL 2 Is 1 Basic transresistance amplifier Feedback network (a) Io Rs If If Vo Is RF Vo (b) If Ii RD1 VDD VG RF Ii Q1 Is If RD2 Vo Q2 (c) If Ii Is RC RE RF VCC Vo –VEE Q2 Q1 (d) 822 Chapter 10 Feedback both the input and the output makes this feedback topology also known as shunt–shunt feedback.
The shunt connection at the input causes the input resistance to be reduced. The shunt con-nection at the output stabilizes the output voltage and thus causes the output resistance to be reduced. Thus, the shunt–shunt topology equips the transresistance amplifier with the desir-able attributes of a low input and a low output resistance.
Three examples of feedback transresistance amplifiers are shown in Fig. 10.11(b), (c), and (d). The circuit in Fig. 10.11(b) utilizes an op amp with a feedback resistance that senses and provides a feedback current that is subtracted from at the input node. To see that the feedback is negative, let increase. The input current will increase, causing the voltage of the negative input terminal to rise. In response, the output voltage will decrease, causing an increase in . Thus and have the same polarity, and the feedback is negative.
The circuit in Fig. 10.11(c) utilizes a CG stage cascaded with a CS stage . A feed-back resistor senses and feeds a current to the input node, where the subtraction from takes place. The reader is urged to show that and have the same polarity and thus the feedback is negative.
Finally, the BJT feedback transresistance amplifier in Fig. 10.11(d) utilizes a CE stage cascaded with an emitter follower . A feedback resistor senses and feeds back a cur-rent to the input node, where it is subtracted from The reader is urged to show that the feedback is indeed negative.
10.3.5 A Concluding Remark Throughout this section we introduced examples of the four different types of feedback amplifier. However, in order to use the feedback analysis approach, we had to make a vari-ety of approximations. For instance, in Example 10.2, to find we had to assume that the input resistance of the closed-loop amplifier was very low. Also, in Exercise 10.6 we assumed that that is, that the feedback network does not load the basic amplifier. The need to make such approximations in a seemingly ad hoc manner is no doubt somewhat disconcerting to the reader. There is, however, very good news: Starting in the next section we will present a systematic approach for the analysis of feedback amplifiers that takes into account the various loading effects and thus obviates the need for ad hoc approximations.
RF Vo If Is Is Ii If If Is Q1 Q2 RF Vo If Is If Is Q1 Q2 RF Vo If Is.
10.9 For the circuit in Fig. 10.11(b), let the op amp have an open-loop gain A, a differential input re-sistance , and a zero output resistance. Analyze the circuit from first principles (i.e., do not use the feedback analysis approach) to determine . Under what conditions does ?
Ans.
; and Rid Af Vo Is ⁄ ≡ Af RF – Af RF 1 1 A ---RF ARid -----------+ + ⎝ ⎠ ⎛ ⎞ – = A 1 ARid RF EXERCISE β R1 R2 + ( ) RD, 10.4 The Feedback Voltage Amplifier (Series–Shunt) 823 10.4 The Feedback Voltage Amplifier (Series–Shunt) 10.4.1 The Ideal Case As mentioned before, series–shunt is the appropriate feedback topology for a voltage ampli-fier.The ideal structure of the series–shunt feedback amplifier is shown in Fig. 10.12(a). It consists of a unilateral open-loop amplifier (the A circuit) and an ideal voltage-sampling, voltage-mixing feedback network (the β circuit). The A circuit has an input resistance Ri, an open-circuit voltage gain A, and an output resistance Ro. It is assumed that the source and load resistances have been absorbed inside the A circuit (more on this point later). Further-more, note that the β circuit does not load the A circuit; that is, connecting the β circuit does not change the value of A (defined as ).
Figure 10.12 The series–shunt feedback amplifier: (a) ideal structure; (b) equivalent circuit.
A Vo Vi ⁄ ≡ (a) Rif Rof Ri Ro AVi Vi (b) S S Vs Rif Rof Af Vs O O Vo 824 Chapter 10 Feedback The circuit of Fig. 10.12(a) exactly follows the ideal feedback model of Fig. 10.1. There-fore the closed-loop voltage gain Af is given by (10.17) The equivalent circuit model of the series–shunt feedback amplifier is shown in Fig.
10.12(b). Observe that is the open-circuit voltage gain of the feedback amplifier, is its input resistance, and is its output resistance. Expressions for and can be derived as follows.
For , refer to the input loop of the circuit in Fig. 10.12(a). The series mixing subtracts from and thus reduces by a factor equal to the amount of feedback (Eq. 10.7), Thus the input current becomes (10.18) Since is the current drawn from the input resistance can be expressed as and using Eq. (10.18) is found to be (10.19) Thus, as expected, the series-mixing feedback results in an increase in the amplifier input resistance by a factor equal to the amount of feedback, a highly desirable property for a voltage amplifier.
It should be clear from the above derivation that the increased input resistance is a result only of the series mixing and is independent of the type of sampling. Thus, the transconduc-tance amplifier, which is the other amplifier type in which series mixing is employed, will also exhibit an increased input resistance even though the feedback network samples its out-put current (series sampling).
To determine the output resistance of the feedback amplifier in Fig. 10.12(a), we set and apply a test voltage between the output terminals, as shown in Fig. 10.13. If the current drawn from is the output resistance is (10.20) An equation for the output loop yields (10.21) From the input loop we see that Now ; thus, Af ≡V o V s ----- = A 1 Aβ + ----------------Af Rif Rof Rif Rof Rif Vf Vs Vi Vi Vs 1 Aβ + ----------------= Ii Ii Vi Ri -----Vs 1 Aβ + ( )Ri --------------------------= = Ii Vs, Rif Rif Vs Ii -----≡ Rif 1 Aβ + ( )Ri = 1 Aβ + ( ), Rof Vs 0 = Vx Vx Ix, Rof Rof Vx Ix -----≡ Ix Vx AVi – Ro --------------------= Vi Vf – = Vf βVo βVx = = 10.4 The Feedback Voltage Amplifier (Series–Shunt) 825 which when substituted in Eq. (10.21) yields Substituting this value of into Eq. (10.20) provides the following expression for , (10.22) Thus, as expected, the shunt sampling (or voltage sampling) at the output results in a decrease in the amplifier output resistance by a factor equal to the amount of negative feed-back, a highly desirable property for a voltage amplifier.
Although perhaps not entirely obvious, the reduction of the output resistance is a result only of the method of sampling the output and does not depend on the method of mixing.
Thus, the transistance amplifier, which is the other amplifier type in which shunt (or volt-age) sampling is employed, will also exhibit a reduced output resistance.
10.4.2 The Practical Case In a practical series–shunt feedback amplifier, the feedback network will not be an ideal voltage-controlled voltage source. Rather, the feedback network is usually resistive and hence will load the basic amplifier and thus affect the values of A, Ri, and Ro. In addition, the source and load resistances will affect these three parameters. Thus the problem we have is as follows: Given a series–shunt feedback amplifier represented by the block diagram of Fig. 10.14(a), find the A circuit and the β circuit.
Our problem essentially involves representing the amplifier of Fig. 10.14(a) by the ideal structure of Fig. 10.12(a). As a first step toward that end we observe that the source and load resistances should be lumped with the basic amplifier. This, together with representing the two-port feedback network in terms of its h parameters (see Appendix C), is illustrated in Fig. 10.14(b). The choice of h parameters is based on the fact that this is the only parameter set that represents the feedback network by a series network at port 1 and a parallel network at port 2. Such a representation is obviously convenient in view of the series connection at the input and the parallel connection at the output.
Examination of the circuit in Fig. 10.14(b) reveals that the current source h21I1 represents the forward transmission of the feedback network. Since the feedback network is usually Figure 10.13 Determining the output resistance of the feedback amplifier of Fig. 10.12(a): Rof = Vx/Ix.
Ix Vx S S Vi Ri Vf Vi βVx – = Ix Vx 1 Aβ + ( ) Ro ---------------------------= Ix Rof Rof Ro 1 Aβ + ----------------= 1 Aβ + ( ), 826 Chapter 10 Feedback Figure 10.14 Derivation of the A circuit and β circuit for the series–shunt feedback amplifier. (a) Block diagram of a practical series–shunt feedback amplifier. (b) The circuit in (a) with the feedback network represented by its h parameters. (c) The circuit in (b) with h21 neglected.
Rof Rout Rin Rif Basic amplifier (a) (b) Basic amplifier (c) Vs Vf Vi Rs RL Basic amplifier b circuit A circuit h11 h22 h12 Vo Vo Vo 10.4 The Feedback Voltage Amplifier (Series–Shunt) 827 passive, its forward transmission can be neglected in comparison to the much larger forward transmission of the basic amplifier. We will therefore assume that and thus omit the controlled source h21I1 altogether.
Compare the circuit of Fig. 10.14(b) (after eliminating the current source h21I1) with the ideal circuit of Fig. 10.12(a). We see that by including h11 and h22 with the basic amplifier, we obtain the circuit shown in Fig. 10.14(c), which is very similar to the ideal circuit. Now, if the basic amplifier is unilateral (or almost unilateral)—that is it does not contain internal feedback—then the circuit of Fig. 10.14(c) is equivalent to the ideal circuit. It follows then that the A circuit is obtained by augmenting the basic amplifier at the input with the source resistance Rs and the resistance h11 of the feedback network, and at the output with the load resistance RL and the conductance h22 of the feedback network.
We conclude that the loading effect of the feedback network on the basic amplifier is represented by the components h11 and h22. From the definitions of the h parameters in Appendix C we see that h11 is the resistance looking into port 1 of the feedback network with port 2 short-circuited. Since port 2 of the feedback network is connected in shunt with the output port of the amplifier, short-circuiting port 2 destroys the feedback. Similarly, h22 is the conductance looking into port 2 of the feedback network with port 1 open-circuited.
Since port 1 of the feedback network is connected in series with the amplifier input, open-circuiting port 1 destroys the feedback.
These observations suggest a simple rule for finding the loading effects of the feedback network on the basic amplifier: The loading effect is found by looking into the appropriate port of the feedback network while the other port is open-circuited or short-circuited so as to destroy the feedback. If the connection is a shunt one, we short-circuit the port; if it is a series one, we open-circuit it. In Sections 10.5, 10.6, and 10.7 it will be seen that this simple rule applies also to the other three feedback topologies.3 We next consider the determination of β. From Fig. 10.14(c), we see that β is equal to h12 of the feedback network, (10.23) Thus to measure β, one applies a voltage to port 2 of the feedback network and measures the voltage that appears at port 1 while the latter port is open-circuited. This result is intuitively appealing because the object of the feedback network is to sample the output voltage (V2 = Vo) and provide a voltage signal (V1 = Vf) that is mixed in series with the input source. The series connection at the input suggests that (as in the case of finding the loading effects of the feed-back network) β should be found with port 1 open-circuited.
10.4.3 Summary A summary of the rules for finding the A circuit and β for a given series–shunt feedback amplifier of the form in Fig. 10.14(a) is given in Fig. 10.15. As for using the feedback for-mulas in Eqs. (10.19) and (10.22) to determine the input and output resistances, it is impor-tant to note that: 1. Ri and Ro are the input and output resistances, respectively, of the A circuit in Fig. 10.15(a).
2. Rif and Rof are the input and output resistances, respectively, of the feedback ampli-fier, including Rs and RL (see Fig. 10.14a).
3A simple rule to remember: If the connection is shunt, short it; if series, sever it.
h21 network feedback h21 amplifier basic β = h12 V1 V2 -----I1=0 ≡ 828 Chapter 10 Feedback 3. The actual input and output resistances of the feedback amplifier usually exclude Rs and RL. These are denoted Rin and Rout in Fig. 10.14(a) and can be easily determined as (10.24) (10.25) Figure 10.15 Summary of the rules for finding the A circuit and β for the series–shunt case of Fig. 10.14(a).
(a) (b) 1 2 The A circuit is Rs R11 R22 RL where R11 is obtained from and R22 is obtained from Basic amplifier Feedback network and the gain A is defined A is obtained from I1 1 2 Feedback network R11 Ro R22 1 2 Feedback network Ri Vo I1 0 Vo Vi Vo Vi Vf Vf Vo Rin Rif Rs – = Rout = 1 1 Rof -------1 RL -----– ⎝ ⎠ ⎛ ⎞ Figure 10.16(a) shows an op amp connected in the noninverting configuration. The op amp has an open-loop gain μ, a differential input resistance Rid, and an output resistance ro. Recall that in our analysis of op-amp circuits in Chapter 2, we neglected the effects of Rid (assumed it to be infinite) and of ro (assumed it to be zero). Here we wish to use the feedback method to analyze the circuit taking both Rid and ro into account. Find expressions for A, β, the closed-loop gain , the input resistance Rin (see Fig. 10.16a), and the output resistance Rout. Also find numerical values, given μ = 104, Rid = 100 kΩ, ro = 1 kΩ, RL = 2 kΩ, R1 = 1 kΩ, R2 = 1 MΩ, and Rs = 10 kΩ.
Vo Vs ⁄ Example 10.3 10.4 The Feedback Voltage Amplifier (Series–Shunt) 829 Figure 10.16 Circuits for Example 10.3.
Rin Vs Rs R1 V1 Rid V1 R2 RL ro Vo Rout Rif Rof (a) 2 1 V1 V1 RL ro Ri (R R11 = R22 = 1 R2) (R2 R 1) Rs Rid Vi Vo Ro (b) Vf R1 R2 Vo I 0 (c) 830 Chapter 10 Feedback Example 10.3 continued Solution We observe that the feedback network consists of R2 and R1. This network samples the output voltage Vo and provides a voltage signal (across R1) that is mixed in series with the input source Vs.
The A circuit can be easily obtained following the rules of Fig. 10.15, and is shown in Fig. 10.16(b).
Observe that the loading effect of the feedback network at the input side is obtained by short-circuiting port 2 of the feedback network (because it is connected in shunt) and looking into port 1, with the result that . The loading effect of the feedback network at the output side is found by open-cir-cuiting port 1 (because it is connected in series) and looking into port 2, with the result that . For the resulting A circuit in Fig. 10.16(b), we can write by inspection: For the values given, we find that A 6000 V/V.
The circuit for determining β is shown in Fig. 10.16(c), from which we obtain The voltage gain with feedback can now be obtained as The input resistance Rif determined by the feedback equations is the resistance seen by the external source (see Fig. 10.16a), and is given by where Ri is the input resistance of the A circuit in Fig. 10.16(b): For the values given, Ri 111 kΩ, resulting in This, however, is not the resistance asked for. What is required is Rin, indicated in Fig. 10.16(a). To obtain Rin we subtract Rs from Rif: For the values given, Rin = 739 kΩ. The resistance Rof given by the feedback equations is the output resis-tance of the feedback amplifier, including the load resistance RL, as indicated in Fig. 10.16(a). Rof is given by where Ro is the output resistance of the A circuit. Ro can be obtained by inspection of Fig.10.16(b) as For the values given, Ro 667 Ω, and R11 R1 R2 || = R22 R2 R1 + = A ≡Vo Vi -----μ RL || R1 R2 + ( ) [RL || R1 R2 + ( )] + ro ---------------------------------------------------Rid Rid Rs (R1 || R2) + + -----------------------------------------------= β ≡V f Vo -----R1 R1 R2 + ------------------ 10 3 – V/V = Af ≡Vo Vs ----- = A 1 Aβ + ---------------- = 6000 7 ------------ = 857 V/V Rif Ri 1 Aβ + ( ) = Ri Rs Rid + (R1||R2) + = Rif 111 7 × 777 kΩ = = Rin Rif Rs – = Rof Ro 1 Aβ + ----------------= Ro ro || RL || R2 R1 + ( ) = Rof 667 7 ---------95.3 Ω = = 10.4 The Feedback Voltage Amplifier (Series–Shunt) 831 The resistance asked for, Rout, is the output resistance of the feedback amplifier excluding RL. From Fig.
10.16(a) we see that Thus Rof = Rout || RL Rout 100 Ω As another example of a series–shunt feedback amplifier, consider the circuit shown in Fig. 10.7(b) which is repeated in Fig. 10.17(a). It is required to analyze this amplifier to obtain its voltage gain , input resistance , and output resistance Find numerical values for the case mA/V, k k and k For simplicity, neglect of each of and Solution We identify the feedback network as the voltage divider ( , ). Its loading effect at the input is obtained by short circuiting its port 2 (because it is connected in shunt with the output). Then, looking into its port 1, we see . The loading effect at the output is obtained by open-circuiting port 1 of the feedback network (because it is connected in series with the input). Then, looking into port 2, we see in series with . The A circuit will therefore be as shown in Fig. 10.17(b). The gain A is determined as the product of the gain of and the gain of as follows: For the numerical values given, V/V The value of is determined from the circuit in Fig. 10.17(c), For the numerical values given, The closed-loop gain can now be found as V/V Vo Vs ⁄ Rin Rout.
gm1 gm2 4 = = RD1 RD2 10 = = Ω, R1 1 = Ω, R2 9 = Ω.
ro Q1 Q2.
R1 R2 R1 R2 || R2 R1 Q1 Q2 A1 Vd1 Vi --------= RD1 1 gm1 ⁄ R1 R2 || ( ) + --------------------------------------------gm1RD1 1 gm1 R1 R2 || ( ) + ----------------------------------------– = – = A2 Vo Vd1 --------gm2 RD2 R1 R2 + ( ) || [ ] – = = A Vo Vi -----A1A2 gm1RD1gm2 RD2 R1 R2 + ( ) || [ ] 1 gm1 R1 R2 || ( ) + ----------------------------------------------------------------------= = = A 4 10 4 10 1 9 + ( ) || [ ] × × 1 4 1 9 || ( ) + ----------------------------------------------------------173.9 = = β β β Vf Vo -----R1 R1 R2 + ------------------= ≡ β 1 1 9 + ------------0.1 = = Vo Vs ⁄ Vo Vs ----- = Af A 1 Aβ + ----------------173.9 1 173.9 0.1 × + ------------------------------------9.5 = = = Example 10.4 832 Chapter 10 Feedback Example 10.4 continued The input resistance is obviously infinite because of the infinite input resistance of the MOSFET. The output resistance is obtained as follows, where is the output resistance of the A circuit. From Fig. 10.17(b), k Figure 10.17 (a) Series–shunt feedback amplifier for Example 10.4; (b) The A circuit; (c) The β circuit.
R1 R2 RD1 Vo Rout Q1 Vs RD2 Q2 (a) 1 2 Rin R1 R2 RD1 Vi Vd1 Vo Ro Q1 RD2 R2 R1 Q2 (b) Ri R1 R2 I o Vo Vf (c) Rout Rout Rof Ro 1 Aβ + ----------------= = Ro Ro RD2 R1 R2 + ( ) || = 10 10 5 = || = Ω 10.4 The Feedback Voltage Amplifier (Series–Shunt) 833 The amount of feedback is Thus, which is relatively low given that the open-loop amplifier has .
1 Aβ 1 173.9 0.1 × ( ) 18.39 = + = + Rout 5000 18.39 -------------272 Ω = = Ro 5000 Ω = 10.10 If the op amp of Example 10.3 has a uniform –6-dB/octave high-frequency rolloff with f3dB = 1 kHz, find the 3-dB frequency of the closed-loop gain .
Ans. 7 kHz 10.11 The circuit shown in Fig. E10.11 consists of a differential stage followed by an emitter follower, with series–shunt feedback supplied by the resistors R1 and R2. Assuming that the dc component of Vs is zero, and that β of the BJTs is very high, find the dc operating current of each of the three transistors and show that the dc voltage at the output is approximately zero. Then find the values of A, β, , Rin, and Rout. Assume that the transistors have β = 100. Ans. 85.7 V/V; 0.1 V/V; 8.96 V/V; 191 kΩ; 19.1 Ω.
10.12 For the series–shunt amplifier in Fig. 10.7(c), find A, , , and Neglect of Q.
Ans.
; ; ; ; Vo Vs ⁄ Af V o Vs ⁄ ≡ Rin Rout Figure E10.11 β Af Rin, Rout.
ro A gm RD R1 R2 + ( ) || [ ] = β R1 R1 R2 + ( ) ⁄ = Af A 1 Aβ + ( ) ⁄ = Rin 1 gm ⁄ ( ) 1 Aβ + ( ) = Rout RD R1 R2 + ( ) || [ ] 1 Aβ + ( ) ⁄ = EXERCISES 834 Chapter 10 Feedback 10.5 The Feedback Transconductance Amplifier (Series–Series) 10.5.1 The Ideal Case As mentioned in Section 10.3, the series–series feedback topology stabilizes and is therefore best suited for transconductance amplifiers. Figure 10.18(a) shows the ideal structure for the series–series feedback amplifier. It consists of a unilateral open-loop amplifier (the A circuit) and an ideal feedback network. The A circuit has an input resis-tance , a short-circuit transconductance and an output resistance The circuit samples the short-circuit output current and provides a feedback voltage that is subtracted from in the series input loop. Note that the circuit presents zero resistance to the output loop, and thus does not load the amplifier output. Also, the feed-back signal is an ideal voltage source, thus the circuit does not load the amplifier input. Also observe that while A is a transconductance, is a transresistance, and thus the loop gain is, as expected, a dimensionless quantity. Finally, note that the source and the load resistances have been absorbed inside the A circuit (more on this later).
Figure 10.18 The series–series feedback amplifier: (a) ideal structure; (b) equivalent circuit.
Io Vs ⁄ Ri A Io Vi, ⁄ ≡ Ro.
β Io Vf Vs β Vf βIo = β β Aβ Vi Ri Ro A Vi S S Vs Rif AfVs Rof O Io O (b) 10.5 The Feedback Transconductance Amplifier (Series–Series) 835 Since the structure of Fig. 10.18(a) follows the ideal feedback structure of Fig. 10.1, we can obtain the closed-loop gain as (10.26) The feedback transconductance amplifier can be represented by the equivalent circuit in Fig.
10.18(b). Note that is the short-circuit transconductance. Because of the series mixing, the input resistance with feedback, , will be larger than the input resistance of the A cir-cuit, , by a factor equal to the amount of feedback, (10.27) Recall that the derivation we employed in the previous section to obtain of the series– shunt feedback amplifier did not depend on the method of sampling. Thus it applies equally well to the series–series amplifier we are considering here. Next we consider the output resistance Rof of the feedback transconductance amplifier.
From the equivalent circuit in Fig. 10.18(b) we observe that Rof is the resistance seen by breaking the output loop (say at OO′) and setting Vs to zero. Thus to find the output resis-tance Rof of the series–series feedback amplifier of Fig. 10.18(a) we reduce Vs to zero and break the output circuit to apply a test current Ix, as shown in Fig. 10.19: (10.28) In this case, Thus for the circuit in Fig. 10.19 we obtain Hence (10.29) That is, in this case the negative feedback increases the output resistance. This should have been expected, since the negative feedback tries to make Io constant in spite of changes in the output voltage, which means increased output resistance. This result also confirms our earlier observation: The relationship between Rof and Ro is a function only of the method of sampling.
Af Af Io Vs -----A 1 Aβ + ----------------= ≡ Af Rif Ri Rif Ri 1 Aβ + ( ) = Rif Rof ≡Vx Ix -----Vi = −V f βIo – βIx.
– = = Vx Ix AVi – ( )Ro Ix AβIx + ( )Ro = = Rof 1 Aβ + ( )Ro = Vi Ri Vf t S S Vx Ix Figure 10.19 Determining the output resistance Rof of the series–series feedback amplifier.
836 Chapter 10 Feedback While voltage (shunt) sampling reduces the output resistance, current (series) sampling increases it.
We conclude that the series–series feedback topology increases both the input and the output resistance, a highly desirable outcome for a transconductance amplifier. 10.5.2 The Practical Case Figure 10.20(a) shows a block diagram for a practical series–series feedback amplifier. To be able to apply the feedback equations to this amplifier, we have to represent it by the ideal structure of Fig. 10.18(a). Our objective therefore is to devise a simple method for finding A and β. Observe the definition of the amplifier input resistance Rin and output resistance Rout.
It is important to note that these are different from Rif and Rof, which are determined by the feedback equations, as will become clear shortly. The series–series amplifier of Fig. 10.20(a) is redrawn in Fig. 10.20(b) with Rs and RL shown closer to the basic amplifier, and the two-port feedback network represented by its z parameters (Appendix C). This parameter set has been chosen because it is the only one that provides a representation of the feedback network with a series circuit at the input and a series circuit at the output. This is obviously convenient in view of the series connections at input and output. The input and output resistances with feedback, Rif and Rof, are indicated on the diagram.
As we have done in the case of the series–shunt amplifier, we shall assume that the forward transmission through the feedback network is negligible in comparison to that through the basic amplifier, and thus we can dispense with the voltage source z21I1 in Fig.
10.20(b). Doing this, and redrawing the circuit to include z11 and z22 with the basic ampli-fier, results in the circuit in Fig. 10.20(c). Now if the basic amplifier is unilateral (or almost unilateral), then the circuit in Fig. 10.20(c) is equivalent to the ideal circuit of Fig. 10.18(a).
It follows that the A circuit is composed of the basic amplifier augmented at the input with Rs and z11 and augmented at the output with RL and z22. Since z11 and z22 are the imped-ances looking into ports 1 and 2, respectively, of the feedback network with the other port open-circuited, we see that finding the loading effects of the feedback network on the basic amplifier follows the rule formulated in Section 10.4. That is, we look into one port of the feedback network while the other port is open-circuited or short-circuited so as to destroy the feedback (open if series and short if shunt).
From Fig. 10.20(c) we see that β is equal to z12 of the feedback network, (10.30) This result is intuitively appealing. Recall that in this case the feedback network samples the output current [I2 = Io] and provides a voltage [Vf = V1] that is mixed in series with the input source. Again, the series connection at the input suggests that β is measured with port 1 open.
10.5.3 Summary For future reference we present in Fig. 10.21 a summary of the rules for finding A and β for a given series–series feedback amplifier of the type shown in Fig. 10.20(a). Note that Ri is the input resistance of the A circuit, and its output resistance is Ro, which can be β z12 ≡V1 I2 -----I1=0 = 10.5 The Feedback Transconductance Amplifier (Series–Series) 837 Figure 10.20 Derivation of the A circuit and the β circuit for series–series feedback amplifiers. (a) A series– series feedback amplifier. (b) The circuit of (a) with the feedback network represented by its z parameters.
(c) A redrawing of the circuit in (b) with z21 neglected.
(a) Rof Rif Rout Rin Basic amplifier Rof Rif Basic amplifier Rs Vi Basic amplifier z11 RL z22 838 Chapter 10 Feedback determined by breaking the output loop and looking between Y and while Vi is set to zero. Ri and Ro can be used in Eqs. (10.27) and (10.29) to determine Rif and Rof (see Fig.
10.20b). The input and output resistances of the feedback amplifier can then be found by subtracting Rs from Rif and RL from Rof, (10.31) (10.32) Figure 10.21 Finding the A circuit and β for the series–series feedback amplifier.
(a) (b) 1 2 The A circuit is Rs R11 R22 RL where R11 is obtained from and R22 is obtained from Basic amplifier Feedback network and the gain A is defined A is obtained from I1 0 1 2 Feedback network R11 R22 1 2 Feedback network Ri Io I1 0 Io Vi Io Vi Vf Vf Io R Y Y o Y′ Rin = Rif Rs – Rout = Rof RL – As a first example of a feedback transconductance amplifier, consider the circuit shown in Fig. 10.22(a).
This is the same circuit we presented in Fig. 10.10(b) and was the subject of Exercise 10.8. Here, for gen-erality we not only assume that has finite input and output resistances but include a source resistance . The objective is to analyze this circuit to determine its closed-loop gain , the input resis-tance of the feedback amplifier and the output resistance The latter is the resistance seen between the two terminals of looking back into the output loop.
A1 Rs Af Io Vs ⁄ ≡ Rin, Rout.
RL Example 10.5 10.5 The Feedback Transconductance Amplifier (Series–Series) 839 Solution First we identify the basic amplifier and the feedback circuit. The basic amplifier consists of the differen-tial amplifier cascaded with the CS PMOS transistor The output current is sensed by the series Figure 10.22 Circuits for Example 10.5.
Vs RL Rof RF A1 (a) Q2 S2 Rs G2 D2 D2 Io Rif Rin RF (b) 2 1 Vi Rs D2 Rid Vid RF Ri RL RF Io Vgs2 A1Vid Ro1 S2 gm2Vgs2 ro2 D2 G2 Ro (c) RF (d) Io V f I1 0 A1 Q2.
Io 840 Chapter 10 Feedback Example 10.5 continued resistance The latter is the feedback network (Fig. 10.22b). It develops a voltage that is mixed in series with the input loop.
The second step is to ascertain that the feedback is negative. We have already done this in Section 10.3.
Next, we determine an approximate value for under the assumption that the loop gain is much greater than unity. This value, found before any analysis is undertaken, will help us deter-mine at the end whether our analysis is correct: If the loop gain is found to be much greater than unity, then the final should be close to the value initially determined. From the circuit of Fig. 10.22(a), and thus for large , Next, we determine the A circuit. Since the feedback network (Fig. 10.22b) is connected in series with both the input and output loops, we include a resistance in each of these loops (which is equivalent to saying we include, at the input, the input resistance of the feedback circuit with port 2 open and, at the output, the input resistance of the feedback circuit with port 1 open). Doing this, including and in the A circuit, and replacing and with their small-signal models, results in the A circuit shown in Fig. 10.22(c). Analysis of this circuit is straightforward: (10.33) (10.34) (10.35) Combining these three equations results in (10.36) Usually , , resulting in the approximate expression for A: (10.37) The input resistance can be found by inspection as (10.38) The output resistance is found by setting and breaking the output loop at any location, say between and Thus, (10.39) Finally, can be found from Fig. 10.22(d) as RF.
Vf Af Io Vs ⁄ ≡ Aβ Af β RF = Aβ Af 1 β ---1 RF ------= RF Rs RL A1 Q2 Vid Vi Rid Rid Rs RF + + --------------------------------– = Vgs2 A1Vid = Io gm2Vgs2 ro2 ro2 RL RF + + --------------------------------– = A Io Vi -----A1gm2 ( ) Rid Rid Rs RF + + --------------------------------⎝ ⎠ ⎛ ⎞ ro2 ro2 RL RF + + --------------------------------⎝ ⎠ ⎛ ⎞ = ≡ Rid Rs RF + ( ) ro2 RL RF + ( ) A A1gm2 Ri Ri Rs Rid RF + + = Ro Vi 0, = D2 D′2.
Ro ro2 RL RF + + = β β Vf Io -----RF = ≡ 10.5 The Feedback Transconductance Amplifier (Series–Series) 841 The loop gain is thus (10.40) (10.41) With numerical values, one can now obtain the value of and determine whether it is indeed much greater than unity. We next determine the closed-loop gain Substituting for A from Eq. (10.37) and for from Eq. (10.41), we have For , which is the value we found at the outset.
The series mixing raises the input resistance with feedback, Substituting for from Eq. (10.38) and for from the full expression in Eq. (10.40), we obtain which for yields To obtain , we subtract from (see Fig. 10.22a): Usually , (10.42) which is an intuitively appealing result: The series mixing at the input raises the input resistance by a factor equal to the approximate value of To obtain , we note that the series connection at the output raises the output resistance, thus, Aβ Aβ A1gm2RF ( ) Rid Rid Rs RF + + --------------------------------⎝ ⎠ ⎛ ⎞ ro2 ro2 RL RF + + --------------------------------⎝ ⎠ ⎛ ⎞ = A1gm2RF Aβ Af A 1 Aβ + ----------------= Aβ Af A1gm2 1 A1gm2RF + -------------------------------A1gm2RF 1 Af 1 RF ------Rif Ri 1 Aβ + ( ) = Ri Aβ Rif Rs Rid RF + + ( ) 1 Aβ + ( ) = Rs = Rid RF A1gm2RFRid ro2 ro2 RL RF + + --------------------------------+ + + ro2RL RF + Rif Rs Rid RF A1gm2RFRid + + + Rin Rs Rif Rin Rid RF A1gm2RFRid + + = RF Rid Rin Rid 1 A + 1gm2RF ( ) Rid 1 Aβ + ( ).
Rof Rof Ro 1 Aβ + ( ) = ro2 RL RF + + ( ) = 1 Aβ + ( ) ro2 RL RF Aβ ro2 RL RF + + ( ) + + + = 842 Chapter 10 Feedback 4 4To avoid possible confusion of the BJT current gain and the feedback factor , we sometimes use to denote the tran-sistor .
Example 10.5 continued Substituting for from Eq. (10.40) and making the approximation , we write To obtain , which is the resistance seen by in the circuit of Fig. 10.22(a), we subtract from , usually thus, which is an intuitively appealing result: The series connection at the output raises the output resistance of ( ) by a factor equal to the amount of feedback.
Finally, we note that we have deliberately solved this problem in great detail to illustrate the beauty Aβ Rid Rs RF + ( ) Rof ro2 RL RF A1gm2RFro2 + + + Rout RL RL Rof Rout ro2 RF A1gm2RFro2 + + = RF ro2; Rout ro2 1 A1gm2RF + ( ) Q2 ro2 D10.13 For the circuit analyzed in Example 10.5, select a value for that will result in mA/V.
Now, for V/V, mA/V, k , k , and assuming that and , find the value of realized and the input and output resistances of the feedback transconductance amplifier. If for some reason drops in value by 50%, what is the corresponding percentage change in ?
Ans. 200 ; 4.94 mA/V; 8.1 M ; 1.62 M ; % RF Af 5 A1 200 = gm2 2 = Rid 100 = Ω ro2 20 = Ω Rs Rid RL ro2 Af gm2 Af Ω Ω Ω 1.25 – EXERCISE Because negative feedback extends the amplifier bandwidth, it is commonly used in the design of broad-band amplifiers. One such amplifier is the MC1553. Part of the circuit of the MC1553 is shown in Fig.
10.23(a). The circuit shown (called a feedback triple) is composed of three gain stages with series–series feedback provided by the network composed of RE1, RF, and RE2. Observe that the feedback network samples the emitter current of , and thus is the output quantity of the feedback amplifier. However, practically speaking, is rather difficult to utilize. Thus usually the collector current of , , is taken as the output. This current is of course almost equal to ; . Thus, as a transconductance amplifier with as the output current, the output resistance of interest is that labeled in Fig. 10.23(a). In some applications, is passed through a load resistance, such as , and the voltage is taken as the output. Assume that the bias circuit, which is not shown, establishes mA, mA, and mA. Also assume that for all three transistors,4 and Io Q3 Io Io Q3 Ic Io Ic αIo = Ic Rout Ic RC3 Vo IC1 0.6 = IC2 1 = IC3 4 = hfe 100 = ro ∞.
= Example 10.6 β β hfe β 10.5 The Feedback Transconductance Amplifier (Series–Series) 843 (a) Anticipating that the loop gain will be large, find an approximate expression and value for the closed-loop gain and hence for . Also find .
(b) Use feedback analysis to find A, , , , and For the calculation of assume that of is 25 k .
Solution (a) When , where the feedback factor can be found from the feedback network. The feedback network is high-lighted in Fig. 10.23(a), and the determination of the value of is illustrated in Fig. 10.23(b), from which we find Figure 10.23 Circuits for Example 10.6.
Af Io Vs ⁄ ≡ Ic Vs ⁄ Vo Vs ⁄ β Af Vo Vs ⁄ Rin, Rout.
Rout, ro Q3 Ω Aβ 1 Af Io Vs ----- 1 β ---≡ β β β Vf Io -----RE2 RE2 RF RE1 + + ------------------------------------RE1 × = ≡ 100 100 640 100 + + ---------------------------------------100 11.9 Ω = × = (a) Vs RF I Y o Vo 640 100 600 9 k 100 5 k Rin Rif RC1 RE1 RE2 RC2 Q1 Q2 Q3 Ic RC3 Rout Rof Y Vf RE2 Io RE1 RF (b) 844 Chapter 10 Feedback Example 10.6 continued Thus, mA/V mA/V V/V (b) Employing the loading rules given in Fig. 10.21, we obtain the A circuit shown in Fig. 10.23(c). To find we first determine the gain of the first stage. This can be written by inspection as Since Q1 is biased at 0.6 mA, re1 = 41.7 Ω. Transistor Q2 is biased as 1 mA; thus rπ2 = Substituting these values together with α1 = 0.99, RC1 = 9 kΩ, RE1 = 100 Ω, RF = 640 Ω, and RE2 = 100 Ω, results in Next, we determine the gain of the second stage, which can be written by inspection (noting that Vb2 = Vc1) as Figure 10.23 continued (c) RC1 RC3 RC2 Q1 Q2 Q3 Ro RF RE1 RE2 Ri RF RE2 Vi I Y o RE1 Y Q3 Rof RC2 Rout (d) Af 1 β ---1 RE2 -------- 1 RE2 RF + RE1 ---------------------+ ⎝ ⎠ ⎛ ⎞ = 1 11.9 ----------= 84 = Ic Vs ----- Io Vs -----84 = Vo Vs -----IcRC3 – Vs ----------------84 0.6 50.4 – = × – = = A Io Vi ⁄ ≡ V c1 Vi --------−α1 RC1 || rπ2 ( ) re1 RE1 || RF RE2 + ( ) [ ] + -----------------------------------------------------------= hfe gm2 ⁄ = 100 40 2.5 = ⁄ kΩ.
V c1 Vi --------14.92 V/V – = Vc2 Vc1 --------gm2 RC2 || hfe 1 + ( ) re3 RE2 || RF RE1 + ( ) ( ) + [ ] { } – = 10.5 The Feedback Transconductance Amplifier (Series–Series) 845 5 5This important point was first brought to the authors’ attention by Gordon Roberts (see Roberts and Sedra, 1992).
Substituting hfe = 100, RE2 = 100 Ω, RF = 640 Ω, and RE1 = 100 Ω, results in Finally, for the third stage we can write by inspection Combining the gains of the three stages results in The closed-loop gain Af can now be found from which we note is very close to the approximate value found in (a) above.
The voltage gain is found from which is also very close to the approximate value found in (a) above.
The input resistance of the feedback amplifier is given by where Ri is the input resistance of the A circuit. The value of Ri can be found from the circuit in Fig.
10.23(c) as follows: Thus, To determine the output resistance which is the resistance looking into the collector of we face a dilemma. The feedback does not sample and thus we cannot employ the feedback formulas directly.5 Nevertheless, we present a somewhat indirect solution to this problem below. Here we note parentheti-cally that had been a MOSFET, this problem would not have existed, since Since the feedback senses the emitter current , the output resistance given by the feedback analysis will be the resistance seen in the emitter circuit, say between Y and gm2 40 mA/V, = RC2 5 kΩ, = re3 = 25 4 ⁄ = 6.25 Ω, Vc2 Vc1 --------131.2 V/V – = Io V c2 --------Ie3 Vb3 --------1 re3 RE2 || RF RE1 + ( ) ( ) + -----------------------------------------------------------= = 1 6.25 100 || 740 ( ) + ---------------------------------------------10.6 mA/V = = A ≡Io Vi -----14.92 131.2 10.6 10 3 – × × – × – = 20.7 A/V = Af Io V s -----≡ A 1 Aβ + ----------------= = 20.7 1 20.7 11.9 × + ------------------------------------83.7 mA/V = Vo Vs -----Ic RC3 – Vs ----------------- Io RC3 – Vs ----------------- = Af RC3 – = 83.7 10 3 – × 600 50.2 V/V – = × – = Rin Rif Ri 1 Aβ + ( ) = = Ri hfe 1 + ( ) re1 RE1 || RF RE2 + ( ) ( ) + [ ] = 13.65 kΩ = Rif 13.65 1 20.7 11.9 × + ( ) 3.38 MΩ = = Rout, Q3, Ic Q1 Id Is.
= Io Y′, Rof Ro 1 Aβ + ( ) = 846 Chapter 10 Feedback 10.6 The Feedback Transresistance Amplifier (Shunt–Shunt) 10.6.1 The Ideal Case As mentioned in Section 10.3, the shunt–shunt feedback topology stabilizes and is thus best suited for transresistance amplifiers. Figure 10.24(a) shows the ideal structure for the shunt–shunt feedback amplifier. It consists of a unilateral open-loop amplifier (the A circuit) and an ideal feedback network. The A circuit has an input resistance an open-circuit transresistance and an output resistance The circuit samples the open-circuit Example 10.6 continued where can be determined from the A circuit in Fig. 10.23(c) by breaking the circuit between Y and The resistance looking between these two nodes can be found to be which, for the values given, yields Ro = 143.9 Ω. The output resistance Rof of the feedback amplifier can now be found as We can now use the value of Rof to obtain an approximate value for Rout. To do this, we assume that the effect of the feedback is to place a resistance Rof (35.6 kΩ) in the emitter of Q3, and find the output resis-tance from the equivalent circuit shown in Fig. 10.23(d). This is the output resistance of a BJT with a resistance in its emitter and a resistance in its base. The formula we have for this (Eq. 7.50) does not unfortunately account for a resistance in the base. The formula, however, can be modified (see Prob-lem 10.48) to obtain Thus is increased (from ) but not by .
Ro Y′.
Ro RE2|| RF RE1 + ( ) [ ] re3 RC2 hfe 1 + ---------------+ + = Rof Ro 1 Aβ + ( ) 143.9 1 20.7 11.9 × + ( ) 35.6 kΩ = = = Rof RC2 Rout ro3 Rof rπ3 RC2 + ( ) || [ ] + = 1 gm3ro3 rπ3 rπ3 RC2 + ----------------------+ 25 35.6 0.625 5 + ( ) || [ ] + = 1 160 25 0.625 0.625 5 + ----------------------× × + 2.19 MΩ = Rout ro3 1 Aβ + ( ) D10.14 For the feedback triple in Fig. 10.23(a), analyzed in Example 10.6, modify the value of to ob-tain a closed-loop transconductance of approximately 100 mA/V. Assume that the loop gain remains large. What is the new value of ? For this value, what is the approximate value of the voltage gain if the output voltage is taken at the collector of ? Ans. 800 ; V/V RF Io Vs ⁄ RF Q3 Ω 60 – EXERCISE Vo Is ⁄ Ri, A Vo Ii, ⁄ ≡ Ro.
β 10.6 The Feedback Transresistance Amplifier (Shunt–Shunt) 847 output voltage and provides a feedback current that is subtracted from the signal-source current at the input nodes. Note that the circuit presents an infinite impedance to the amplifier output and thus does not load the amplifier output. Also, the feedback signal is provided as an ideal current source, and thus the circuit does not load the amplifier input.
Also observe that while A is a transresistance, is a transconductance and thus the loop gain is, as expected, a dimensionless quantity. Finally, note that the source and load resistances have been absorbed inside the A circuit (more on this later).
Since the structure of Fig. 10.24(a) follows the ideal feedback structure of Fig. 10.1, we can obtain the closed-loop gain as (10.43) The feedback transresistance amplifier can be represented by the equivalent circuit in Fig.
10.24(b). Note that is the open-circuit transresistance. To obtain the input resistance , refer to the input side of the block diagram in Fig. 10.24(a). The shunt connection at the input causes the feedback current to subtract from resulting in a reduced current into the A circuit, Figure 10.24 (a) Ideal structure for the shunt–shunt feedback amplifier. (b) Equivalent circuit of the amplifier in (a). Ii Ro Ri AIi S O O S Rif S S O O (b) Rof Is Vo AfIs Vo If Is β If βVo = β β Aβ Af Af Vo Is -----A 1 Aβ + ----------------= ≡ Af Rif Is Ii Ii Is If – = 848 Chapter 10 Feedback Substituting and rearranging, results in which indicates that the shunt mixing reduces the input current by the amount of feedback.
This is, of course, a direct application of Eq. (10.7), where in the case of shunt mixing, and The input resistance with feedback, , can now be obtained from Substituting for which is the input resistance of the A circuit, results in (10.44) Thus, as expected, the shunt connection at the input lowers the input resistance by a factor equal to the amount of feedback. The lowered input resistance is a welcome result for the transresistance amplifier; the lower the input resistance, the easier it is for the signal current source that feeds the amplifier input.
Turning our attention next to the output resistance, we can follow an approach identical to that used in the case of the series–shunt amplifier (Section 10.4) to show that the shunt connec-tion at the output lowers the output resistance by a factor equal to the amount of feedback, (10.45) This also is a welcome result for the transresistance amplifier as it makes its voltage-output circuit more ideal; the output voltage will change less as we draw current from the amplifier output. Finally, note that the shunt feedback connection, whether at the input or at the out-put, always reduces the corresponding resistance.
10.6.2 The Practical Case Figure 10.25 shows a block diagram for a practical shunt–shunt feedback amplifier. To be able to apply the feedback equations to this amplifier, we have to represent it by the ideal structure of Fig. 10.24(a). Our objective therefore is to devise a simple method for finding the A circuit and . Building on the insight we have gained from our study of the series– shunt and series–series topologies, we present the method for the shunt–shunt case, without If βVo βAIi = = Ii Is 1 Aβ + ----------------= xs Is = xi Ii.
= Rif Rif Vi Is -----Vi 1 Aβ + ( )Ii -------------------------= ≡ Vi Ii ⁄ Ri, = Rif Ri 1 Aβ + ----------------= Rof Ro 1 Aβ + ----------------= β Rout Rin Rif Rof Basic amplifier Figure 10.25 Block diagram for a practical shunt–shunt feedback amplifier.
10.6 The Feedback Transresistance Amplifier (Shunt–Shunt) 849 derivation, in Fig. 10.26. As in previous cases, the method of Fig. 10.26 assumes that the basic amplifier is unilateral (or almost so) and that the feedforward transmission through the feedback network is negligibly small.
As indicated in Fig. 10.26, the A circuit is obtained by including across the input termi-nals of the amplifier and across its output terminals. The loading effect of the feedback net-work on the amplifier input is represented by the resistance and its loading effect at the output is represented by the resistance . The value of is obtained by looking into port 1 of the feedback network while port 2 is shorted (because it is connected in shunt). Similarly, is found by looking into port 2 while port 1 is shorted (because it is connected in shunt).
Finally, observe that since the feedback network senses it is fed by a voltage ; and since it delivers a current that is mixed in shunt at the input, its port 1 is short-circuited and is found as , where is the current that flows through the short circuit.
The open-loop resistances and are determined from the A circuit and are used in Eqs. (10.44) and (10.45) to determine and . Finally, the resistances and that characterize the feedback amplifier are obtained from and by reference to Fig. 10.25 as follows: (10.46) (10.47) (a) (b) 1 2 The A circuit is Rs R11 R22 RL where R11 is obtained from and R22 is obtained from Basic amplifier Feedback network and the gain A is defined A is obtained from V1 0 1 2 Feedback network R11 Ro R22 1 2 Feedback network Ri Vo V1 0 Vo Ii Vo Ii If If Vo Figure 10.26 Finding the A circuit and β for the shunt–shunt feedback amplifier in Fig. 10.25.
Rs RL R11 R22 R11 R22 Vo, Vo If β If Vo ⁄ If Ri Ro Rif Rof Rin Rout Rin Rof Rin 1 1 Rif ------1 Rs -----– ⎝ ⎠ ⎛ ⎞ = Rout 1 1 Rof -------1 RL ------– ⎝ ⎠ ⎛ ⎞ = 850 Chapter 10 Feedback Figure 10.27(a) shows a feedback transresistance amplifier. It is formed by connecting a resistance in the negative-feedback path of a voltage amplifier with gain , an input resistance , and an output resistance The amplifier can be implemented with an op amp, a simple differential amplifier, a sin-gle-ended inverting amplifier, or, in the limit, a single-transistor CE or CS amplifier. The latter case will be considered in Exercise 10.15. Of course, the higher the gain , the more ideal the characteristics of the feedback transresistance amplifier will be, simply because of the concomitant increase in loop gain.
RF μ Rid ro.
μ μ Is Rs RL m Vo (a) RF Rif Rin Rout Rof Figure 10.27 (a) A feedback transresistance amplifier; (b) the β circuit; (c) the A circuit.
If RF Vo (b) Rs Ii (c) RF Rid Ri Ro Vid RF mVid ro RL Vo Example 10.7 10.6 The Feedback Transresistance Amplifier (Shunt–Shunt) 851 (a) If the loop gain is large, find an approximate expression for the closed-loop open-circuit transresis-tance of the feedback amplifier.
(b) Find the A circuit and expressions for A, , and (c) Find expressions for the loop gain, , , , , and (d) Find the values of , A, , , , , and for the case V/V, k and k (e) If instead of a current source having a source resistance k the amplifier is fed from a voltage source having a source resistance k find an expression for and the value of the voltage gain .
Solution (a) If the loop gain is large, where can be found from the circuit in Fig. 10.27(b) as (10.48) Thus, Note that in this case the voltage at the input node (the inverting input terminal of ) will be very close to ground and thus very little, if any, current flows into the input terminal of the amplifier. Nearly all of will flow through , resulting in . This should be reminiscent of the inverting op-amp configuration studied in Section 2.2.
(b) Since the feedback network consists of , the loading effect at the amplifier input and output will simply be . This is indicated in the A circuit shown in Fig. 10.27(c). The open-loop transresistance A can be obtained as follows: (10.49) where (10.50) (10.51) Combining Eqs. (10.49) and (10.51) gives (10.52) The open-loop output resistance can be obtained by inspection of the A circuit with set to 0. We see that , and (10.53) (c) The loop gain can be obtained by combining Eqs. (10.48) and (10.52), Ri Ro.
Af Rif Rin Rof Rout.
Ri Ro, β, Af Rif Rin Rof Rout μ 104 = Rid ∞, = ro 100 Ω, = RF 10 = Ω, Rs RL 1 = = Ω.
Is Rs 1 = Ω, Vs Rs 1 = Ω, Vo Vs ⁄ Aβ Af Vo Is ----- 1 β ---≡ β β β If Vo -----1 RF ------– = ≡ Vo Is ----- RF – μ Is RF Vo 0 IsRF IsRF – = – RF RF Vid IiRi = Ri Rid RF Rs || || = Vo μVid RF RL || ( ) ro RF RL || ( ) + ---------------------------------– = A Vo Ii -----μRi RF RL || ( ) ro RF RL || ( ) + ---------------------------------– = ≡ Ii Vid 0 = Ro ro RF RL || || = Aβ Aβ μ Ri RF ------⎝ ⎠ ⎛ ⎞ RF RL || ( ) ro RF RL || ( ) + ---------------------------------= 852 Chapter 10 Feedback Example 10.7 continued Observe that although both A and are negative, is positive, a comforting fact confirming that the feedback is negative. Also note that is dimensionless, as it must always be.
The closed-loop gain can now be found as Thus (10.54) Note that the condition of which results in corresponds to (10.55) The input resistance with feedback, , is obtained by dividing by with the result or Substituting for from Eq. (10.50) and replacing by where is lower than but usually close to the value of , results in Rif = Rid || RF || Rs || (RF / ) The two terms containing can be combined, (10.56) Since , we see that Usually is large and thus (10.57) from which we observe that for large amplifier gain , the input resistance will be low. The output resistance with feedback can be found by dividing by Thus, β Aβ Aβ Af Af Vo Is -----A 1 Aβ + ----------------= ≡ Af μRi RF RL || ( ) ro RF RL || ( ) + ---------------------------------– 1 μ Ri RF ------RF RL || ( ) ro RF RL || ( ) + ---------------------------------+ ---------------------------------------------------------= Aβ 1 Af RF – μ Ri RF ------⎝ ⎠ ⎛ ⎞ RF RL || ( ) ro RF RL || ( ) + --------------------------------- 1 Rif Ri 1 Aβ + ( ) Rif Ri 1 Aβ + ----------------= 1 Rif ------1 Ri -----Aβ Ri -------1 Ri -----μ RF ------RF RL || ( ) ro RF RL || ( ) + ---------------------------------+ = + = Ri μ RF RL || ( ) ro RF RL || ( ) + [ ] μ′, μ′ μ μ′ RF Rif Rs Rid RF μ′ 1 + ( ) ⁄ [ ] || || = Rif Rs Rin || = Rin Rid RF μ′ 1 + ( ) || [ ] || = Rid Rin RF μ′ 1 + -------------- RF μ′ ------μ Rof Ro 1 Aβ + ( ): Rof Ro 1 Aβ + ----------------= 1 Rof -------1 Ro -----Aβ Ro -------+ = 1 Ro -----μ Ri RF ------RF RL || ( ) ro RF RL || ( ) + --------------------------------- 1 Ro -----+ = 10.6 The Feedback Transresistance Amplifier (Shunt–Shunt) 853 Substituting for from Eq. (10.53), Thus, Since, moreover, we obtain for Usually ; thus, from which we see that for large , the output resistance will be considerably reduced.
(d) For the numerical values given: mA/V which is very close to the ideal value of Ro 1 Rof -------1 RL ------1 RF ------1 ro ----μ Ri RF ------ 1 ro ----+ + + = 1 RL ------1 RF ------1 ro ---- 1 μ Ri RF ------+ ⎝ ⎠ ⎛ ⎞ + + = Rof RL RF ro 1 μ Ri RF ------+ --------------------|| || = Rof RL Rout || = Rout Rout RF ro 1 μ Ri RF ------+ --------------------|| = RF ro ⁄ 1 ( μ Ri ( R ⁄ F) + [ ] Rout ro 1 μ Ri RF ------+ ------------------- RF Ri ------⎝ ⎠ ⎛ ⎞ro μ ----⎝ ⎠ ⎛ ⎞ μ Ri Rid RF Rs || || = ∞ 10 1 0.91 kΩ = || || = Ro ro RF Rs || || = 0.1 10 1 90 Ω = || || = A μRi RF RL || ( ) ro RF RL || ( ) + ---------------------------------– = 104 0.91 10 1 || ( ) 0.1 10 1 || ( ) + ---------------------------------× × 8198 kΩ – = – = β 1 RF ------1 10 ------0.1 – = – = – = Aβ 819.8 = 1 Aβ 820.8 = + Af A 1 Aβ + ----------------8198 820.8 -------------9.99 kΩ – = – = = RF 10 kΩ.
– = – Rif Ri 1 Aβ + ----------------910 820.8 -------------1.11 Ω = = = Rin 1 1 Rif ------1 Ri -----– ------------------1 1 1.11 ----------1 1000 ------------– ----------------------------- 1.11 Ω – = 854 Chapter 10 Feedback Example 10.7 continued which is very low, a highly desirable property. We also have which as well is very low, another highly desirable property.
(e) If the amplifier is fed with a voltage source having a resistance , the output voltage can be found from Thus, V/V Rof Ro 1 Aβ + ----------------90 820.8 -------------0.11 Ω = = = Rout 1 1 Rof -------1 RL ------– --------------------1 1 0.11 ----------1 1000 ------------– ----------------------------- 0.11 Ω = = Vs Rs 1 kΩ = Vo Af Is Af Vs Rs -----= = Vo Vs -----Af Rs -----9.99 kΩ 1 kΩ --------------------9.99 – = – = = 10.15 For the transresistance amplifier in Fig. E10.15, replace the MOSFET with its equivalent-circuit model and use feedback analysis to show the following: (a) For large loop gain (which cannot be achieved here), .
(b) (c) Is Rs Rf Vo I (ideal) Rin Rout Q Figure E10.15 Af Vo ⁄ Is Rf – ≡ Af Rs Rf || ( )gm ro Rf || ( ) – 1 Rs Rf || ( )gm ro Rf || ( ) Rf ⁄ + ------------------------------------------------------------------= Rin Rf 1 gm ro Rf || ( ) + [ ] ----------------------------------------= EXERCISE 10.7 The Feedback Current Amplifier (Shunt–Series) 855 10.6.3 An Important Note The feedback analysis method is predicated on the assumption that all (or most) of the feed-forward transmission occurs in the basic amplifier and all (or most) of the feedback trans-mission occurs in the feedback network. The circuit considered in Exercise 10.15 above is simple and can be analyzed directly (i.e., without invoking the feedback approach) to deter-mine . In this way we can check the validity of our assumptions. This point is illustrated in Problem 10.58, where we find that for the circuit in Fig. E10.15, all of the feedback trans-mission occurs in the feedback circuit. Also, as long as is much greater than , the assumption that most of the feedforward transmission occurs in the basic amplifiers is valid, and thus the feedback analysis is reasonably accurate.
10.7 The Feedback Current Amplifier (Shunt–Series) 10.7.1 The Ideal Case As mentioned in Section 10.3, the shunt–series feedback topology is best suited for current amplifiers: The shunt connection at the input reduces the input resistance, making it easier to feed the amplifier with a current signal; the sampling of output current stabilizes , which is the output signal in a current amplifier, and the series connection at the output increases the output resistance, making the output current value less susceptible to changes in load resistance.
Figure 10.28(a) shows the ideal structure for the shunt–series feedback amplifier. It con-sists of a unilateral open-loop amplifier (the A circuit) and an ideal feedback network. The A circuit has an input resistance , a short-circuit current gain , and an output resis-tance The circuit samples the short-circuit output current and provides a feedback current that is subtracted from the signal-source current at the input node. Note that the circuit presents a zero resistance to the output loop and thus does not load the amplifier output. Also, the feedback signal is provided as an ideal current source, and thus the circuit does not load the amplifier input. Also observe that both A and are current gains and is a dimensionless quantity. Finally, note that the source and load resistances have been absorbed inside the A circuit (more on this later).
Since the structure of Fig. 10.28(a) follows the ideal feedback structure of Fig. 10.1, we can obtain the closed-loop current gain as (10.59) The feedback current amplifier can be represented by the equivalent circuit in Fig. 10.28(b).
(d) (e) For mA/V, , , and , find A, , , , , , , and Ans. (e) k ; mA/V; 3.03; (compare to the ideal value of ); 909 ; 6.67 k ; 226 ; 291 ; 1.66 k ; 1.66 k Rout ro Rf 1 gm Rs Rf || ( ) + ------------------------------------|| = gm 5 = ro 20 kΩ = Rf 10 kΩ = Rs 1 kΩ = β Aβ Af Ri Ro Rif Rin Rof, Rout.
30.3 – Ω 0.1 – 7.52 kΩ – 10 kΩ – Ω Ω Ω Ω Ω Ω Af gm 1 Rf ⁄ Io Ri A Io Ii ⁄ ≡ Ro.
β Io If Is β If βIo = β β Aβ Af Af Io Is ----A 1 Aβ + ----------------= ≡ 856 Chapter 10 Feedback Note that is the short-circuit current gain. The input resistance is found by dividing by , which is a result of the shunt connection at the input. Thus, (10.60) The output resistance is the resistance obtained by setting breaking the short-circuit output loop, at say , and measuring the resistance between the two terminals thus created. Since the series feedback connection always raises resistance, we can obtain by multiplying by (10.61) 10.7.2 The Practical Case Figure 10.29 shows a block diagram for a practical shunt–series feedback amplifier. To be able to apply the feedback equations to this amplifier, we have to represent it by the ideal structure of Fig. 10.28(a). Our objective therefore is to devise a simple method for finding the A and circuits. Building on the insight we have gained from the study of the three other topologies, we present the method for the shunt–series case without derivation, in Fig.
10.30. As in previous cases, the method of Fig. 10.30 assumes that the basic amplifier is uni-lateral (or almost so) and that the feedforward transmission in the feedback network is negli-gibly small. S S Ii Ri Ro AIi Figure 10.28 (a) Ideal structure for the shunt–series feedback amplifier. (b) Equivalent circuit of the amplifier in (a).
Rif Rof S S O O Io Is AfIs (b) Af Rif Ri 1 Aβ + ( ) Rif Ri 1 Aβ + ----------------= Rof Is 0, = OO′ Rof Ro 1 Aβ + ( ), Rof 1 Aβ + ( )Ro = β 10.7 The Feedback Current Amplifier (Shunt–Series) 857 As indicated in Fig. 10.30, the A circuit is obtained by including across the input termi-nals of the amplifier and in series with its output loop. The loading effect of the feedback network on the amplifier input is represented by the resistance , and its loading effect at the amplifier output is represented by resistance The value of is obtained by look-ing into port 1 of the feedback network while its port 2 is open-circuited (because it is con-nected in series). The value of is obtained by looking into port 2 of the feedback R Y Y L Basic amplifier Feedback network 2 1 Io Io Rs Is Rout Rof Rin Rif Figure 10.29 Block diagram for a practical shunt–series feedback amplifier.
(a) (b) 1 2 The A circuit is Rs R11 R22 RL where R11 is obtained from and R22 is obtained from Basic amplifier Feedback network and the gain A is defined as A is obtained from V1 0 1 2 Feedback network R11 R22 1 2 Feedback network Ri Io V1 0 Io Ii Io Ii If If Io Ro Y Y Figure 10.30 Finding the A circuit and β for the current-mixing current-sampling (shunt–series) feedback amplifier of Fig. 10.29.
Rs RL R11 R22.
R11 R22 858 Chapter 10 Feedback network while its port 1 is short-circuited (because it is connected in shunt). Finally, observe that since the feedback network senses it is fed by a current ; and since it delivers a current that is mixed in shunt at the input, its port 1 is short-circuited and is found as where is the current that flows through the short circuit.
The open-loop resistances and are determined from the A circuit as indicated.
Observe that is found by breaking the output loop at say and measuring the resis-tance between Y and . Resistances and are then used in Eqs. (10.60) and (10.61), respectively, to determine and . Finally, the resistances and that character-ized the feedback amplifier are obtained from and by reference to Fig. 10.29, as follows: (10.62) (10.63) Io, Io If β If Io ⁄ , If Ri Ro Ro YY′ Y′ Ri Ro Rif Rof Rin Rout Rif Rof Rin 1 1 Rif ------1 Rs -----– ⎝ ⎠ ⎛ ⎞ = Rout Rof RL – = Figure 10.31 shows a feedback current amplifier formed by cascading an inverting voltage amplifier with a MOSFET Q. The output current is the drain current of Q. The feedback network, con-sisting of resistors and , senses an exactly equal current, namely, the source current of Q, and provides a feedback current signal that is mixed with at the input node. Note that the bias arrange-ment is not shown.
μ Io R1 R2 Is m (a) R2 Rif Rin R1 Rout Rof Q Io Is Rs Io Figure 10.31 Circuit for Example 10.8.
Example 10.8 10.7 The Feedback Current Amplifier (Shunt–Series) 859 Io If R2 R1 (b) 1 2 Figure 10.31 continued (c) m R2 If Is Ii 0 Vi 0 Q IoIs 1 Is Rs R2 R1 IoIs 1 R2 R1 Is R2 Is R2 R1 R1 Io Io Q Rs Ii (d) 1/gm Rid Ri R2 R2 R1 R1 ro2 Vi Ro mVi ro1 0 860 Chapter 10 Feedback Example 10.8 continued The amplifier can be implemented in a variety of ways, including by means of an op amp, a dif-ferential amplifier, or a single-ended inverting amplifier. The simplest approach is to implement with a CS MOSFET amplifier. However, in such a case the loop gain will be very limited. Assume that the amplifier has an input resistance , an open-circuit voltage gain , and an output resistance (a) If the loop gain is large, find an approximate expression for the closed-loop gain .
(b) Find the A circuit and derive expressions for A, , and (c) Give expressions for , , , , and (d) Find numerical values for A, , , and for the following case: V/V, , , , and for Q: gm = 5 mA/ V and Solution (a) When the loop gain , . To determine refer to Fig. 10.31(b), (10.64) Thus, (10.65) To see what happens in this case more clearly, refer to Fig. 10.31(c). Here we have assumed the loop gain to be large, so that and thus Also note that because , will be close to zero.
Thus, we can easily determine the voltage at the source of Q as The current through will then be . The source current of Q will be , which means that the output cur-rent will be which confirms the expression for obtained above (Eq. 10.65).
(b) To obtain the A circuit we load the input side of the basic amplifier with and The latter in this case is simply (because port 2 of the feedback network is opened). We also load the output of the basic amplifier with which in this case is (because port 1 of the feedback network is shorted). The resulting A circuit is shown in Fig., 10.31(d), where we have replaced the amplifier with its equivalent circuit. Analysis of the A circuit is straightforward and proceeds as follows: (10.66) (10.67) (10.68) Combining Eqs. (10.67) and (10.68) results in A: (10.69) μ μ μ Rid μ ro1.
Af Io Is ⁄ ≡ Ri Ro.
Aβ, Af Rif Rin Rof Rout.
β, Aβ, Af Ri, Rif Rin, Ro, Rof, Rout μ 1000 = Rs ∞, = Rid ∞, = ro1 1 kΩ = R1 10 kΩ = R2 90 kΩ = ro 20 kΩ.
= Aβ 1 Af 1 β ⁄ β β If Io ----R1 R1 R2 + ------------------– = ≡ Af 1 β ---1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ – = Ii 0 If Is.
Ii 0 Vi If – R2 Is R2.
– R1 IsR2 R1 ⁄ Is IsR2 R1 ⁄ + ( ) – Io Io Is – 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ = Af Rs R11.
R1 R2 + R22, R1 R2 || μ Ri Rs Rid R1 R2 + ( ) || || = Vi IiRi = Io μVi 1 1 ⁄ gm R1 R2 || ro2 || ( ) + ------------------------------------------------------ro2 ro2 R1 R2 || ( ) + -----------------------------------– = A Io Ii ----μ Ri 1 gm ⁄ R1 R2 || ro2 || ( ) + ------------------------------------------------------ro2 ro2 R1 R2 || ( ) + -----------------------------------– = ≡ 10.7 The Feedback Current Amplifier (Shunt–Series) 861 For the case , Which reduces to (10.70) Noting that is the output resistance of Q, which has a resistance in its source lead, we can write (10.71) (c) The loop gain is obtained by combining Eqs. (10.64) and (10.69), (10.72) For the case (10.73) The input resistance is found as We can substitute for from the full expression in Eq. (10.72). For the approximate case, we use from Eq. (10.73): That is, Substituting for from Eq. (10.66), we write Since by definition, we can easily find as (10.74) 1 g ⁄ m R1 R2 || ro2 || ( ) A μ Ri R1 R2 || ro2 || -----------------------------ro2 ro2 R1 R2 || ( ) + -----------------------------------– A μ Ri R1 R2 || -----------------– = Ro R1 R2 || ( ) Ro ro2 R1 R2 || ( ) gmro2 ( ) R1 R2 || ( ) + + = gmro2 R1 R2 || ( ) Aβ μ Ri 1 gm ------R1 R2 || ro2 || ( ) + -----------------------------------------------ro2 ro2 R1 R2 || ( ) + -----------------------------------R1 R1 R2 + ------------------= 1 ⁄ gm R1 R2 || ro2 || ( ), Aβ μ Ri R1 R2 || -----------------R1 R1 R2 + ------------------μ Ri R2 -----= Rif Rif Ri 1 Aβ + ( ) ⁄ = 1 Rif ------1 Ri -----Aβ Ri -------+ = Aβ Aβ 1 Rif ------1 Ri -----μ R2 -----+ = Rif Ri R2 μ -----|| = Ri Rif Rs Rid R1 R2 + ( ) R2 μ -----|| || || = Rif Rs Rin || = Rin Rin Rid R1 R2 + ( ) R2 μ -----|| || = 862 Chapter 10 Feedback Example 10.8 continued Usually the third component on the right-hand side is the smallest; thus, (10.75) For the output resistance, we have Substituting for for Eq. (10.71) and for from the approximate expression in Eq. (10.73), we have (10.76) Finally, we note that (10.77) (d) For the numerical values given, Since , A/A A/A A/A which is very close to the ideal value of A/A Rin R2 μ -----Rof Ro 1 Aβ + ( ) AβRo = Ro Aβ Rof μ Ri R2 -----⎝ ⎠ ⎛ ⎞gmro2 ( ) R1 R2 || ( ) Rof μ Ri R1 R + 2 ------------------ gmro2 ( )R1 = Rout Rof μ Ri R1 R + 2 ------------------gmro2R1 = = Ri ∞ ∞ 10 90 + ( ) 100 kΩ = || || = 1 g ⁄ m 0.2 kΩ 10 90 20 || || ( ) = A μ Ri R1 R || 2 -----------------– 1000 100 10 90 || -----------------11.11 103 × – = – = β R1 R1 R + 2 ------------------10 10 90 + ------------------0.1 – = – = – = Aβ 1111 = Af 11.11 103 × 1 1111 + ----------------------------9.99 – = – = Af 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ – 1 90 10 ------+ ⎝ ⎠ ⎛ ⎞ – = 10 – = Rin R2 μ -----90 kΩ 1000 ---------------90 Ω = = = Ro gmro2 R1 R2 || ( ) = 5 20 10 90 || ( ) × 900 kΩ = = Rout 1 Aβ + ( )Ro 1112 900 1000 MΩ = × = = 10.8 Summary of the Feedback Analysis Method 863 10.8 Summary of the Feedback Analysis Method Table 10.1 provides a summary of the rules and relationships employed in the analysis and design of the four types of feedback amplifier. In addition to the wealth of information in Table 10.1, we offer the following important analysis tips.
1. Always begin the analysis by determining an approximate value for the closed-loop gain , assuming that the loop gain is large and thus This value should serve as a check on the final value you find for . How close the actual is to the approximate value will depend on how large is compared to unity.
2. The shunt connection at input or output always results in reducing the correspond-ing resistance (input or output). The series connection at input or output always results in increasing the corresponding resistance (input or output).
3. In utilizing negative feedback to improve the properties of an amplifier under design, the starting point in the design is the selection of the feedback topology appropriate for the application at hand. Then the required amount of negative feed-back can be ascertained utilizing the fact that it is this quantity that deter-mines the magnitude of improvement in the various amplifier parameters. Also, the feedback factor can be determined from 10.9 Determining the Loop Gain We have already seen that the loop gain Aβ is a very important quantity that characterizes a feedback loop. Furthermore, in the following sections it will be shown that Aβ determines whether the feedback amplifier is stable (as opposed to oscillatory). In this section, we shall describe an alternative approach to the determination of loop gain.
10.16 For the amplifier in Example 10.8, find the values of , and when the value of is 10 times lower, that is when Ans. A/A; 900 ; 100 M 10.17 If in the circuit in Fig. 10.31(a), is short-circuited, find the ideal value of . For the case give expressions for , , A, , , , and Ans. A/A; , ; ; .
Af Rin, Rout μ μ 100.
= 9.91 – Ω Ω R2 Af Rs Rid ∞, = = Ri Ro β Af Rin Rout Af 1 = Ri R1; = Ro ro2 = A μgmR1 – = β 1 – = Af μgmR1 ⁄ 1 μgmR1 + ( ); = Rin 1 μgm; ⁄ = Rout μ gmro2 ( )R1 EXERCISES Af Aβ Af 1 β ⁄ Af Af Aβ 1 Aβ + ( ) β β 1 Af ⁄ 864 Chapter 10 Feedback Table 10.1 Summary of Relationships for the Four Feedback-Amplifier Topologies Loading of Feedback Network is Obtained To Find β , Apply to Port 2 of Feedback Network Refer to Figs.
Feedback Amplifier Feedback Topology xi xo xf xs A β Af Source Form At Input At Output Rif Rof Voltage Series–shunt Vi Vo Vf Vs Thévenin By short-circuiting port 2 of feedback network By open-circuiting port 1 of feedback network a voltage, and find the open-circuit voltage at port 1 Ri(1 + Aβ) 10.6 10.12 10.14 10.15 Current Shunt–series Ii Io If Is Norton By open- circuiting port 2 of feedback network By short-circuiting port 1 of feedback network a current, and find the short-circuit current at port 1 Ro(1 + Aβ) 10.8(a) 10.28 10.29 10.30 Transconduc-tance Series–series Vi Io Vf Vs Thévenin By open- circuiting port 2 of feedback network By open- circuiting port 1 of feedback network a current, and find the open-circuit voltage at port 1 Ri(1 + Aβ) Ro(1 + Aβ) 10.10(a) 10.18 10.20 10.21 Transresistance Shunt–shunt Ii Vo If Is Norton By short-circuiting port 2 of feedback network By short-circuiting port 1 of feedback network a voltage, and find the short-circuit current at port 1 10.11(a) 10.24 10.25 10.26 Vo V i -----Vf Vo -----Vo Vs -----Ro 1 Aβ + --------------Io Ii ----If Io ----Io Is ----Ri 1 Aβ + --------------Io V i -----Vf Io -----Io Vs -----Vo Ii -----If V o -----V o Is -----Ri 1 Aβ + --------------Ro 1 Aβ + --------------10.9 Determining the Loop Gain 865 10.9.1 An Alternative Approach for Finding Aβ First, consider again the general feedback amplifier shown in Fig. 10.1. Let the external source xs be set to zero. Open the feedback loop by breaking the connection of xo to the feed-back network and apply a test signal xt. We see that the signal at the output of the feedback network is xf = βxt; that at the input of the basic amplifier is xi = −βxt; and the signal at the output of the amplifier, where the loop was broken, will be xo = −Aβxt. It follows that the loop gain Aβ is given by the negative of the ratio of the returned signal to the applied test signal; that is, It should also be obvious that this applies regardless of where the loop is broken.
However, in breaking the feedback loop of a practical amplifier circuit, we must ensure that the conditions that existed prior to breaking the loop do not change. This is achieved by termi-nating the loop where it is opened with an impedance equal to that seen before the loop was broken. To be specific, consider the conceptual feedback loop shown in Fig. 10.32(a). If we break the loop at , and apply a test voltage Vt to the terminals thus created to the left of , the terminals at the right of should be loaded with an impedance Zt as shown in Fig. 10.32(b). The impedance Zt is equal to that previously seen looking to the left of .
The loop gain Aβ is then determined from (10.78) Finally, it should be noted that in some cases it may be convenient to determine Aβ by applying a test current It and finding the returned current signal Ir. In this case, An alternative equivalent method for determining Aβ (see Rosenstark, 1986) that is usu-ally convenient to employ especially in SPICE simulations is as follows: As before, the loop is broken at a convenient point. Then the open-circuit voltage transfer function Toc is deter-mined as indicated in Fig. 10.32(c), and the short-circuit current transfer function Tsc is determined as shown in Fig. 10.32(d). These two transfer functions are then combined to obtain the loop gain Aβ, (10.79) This method is particularly useful when it is not easy to determine the termination imped-ance Zt.
To illustrate the process of determining loop gain, we consider the feedback loop shown in Fig. 10.33(a). This feedback loop represents both the inverting and the noninverting op-amp configurations. Using a simple equivalent-circuit model for the op amp, we obtain the circuit of Fig. 10.33(b). Examination of this circuit reveals that a convenient place to break the loop is at the input terminals of the op amp. The loop, broken in this manner, is shown in Fig.
10.33(c) with a test signal Vt applied to the right-hand-side terminals and a resistance Rid ter-minating the left-hand-side terminals. The returned voltage Vr is found by inspection as (10.80) This equation can be used directly to find the loop gain Since the loop gain L is generally a function of frequency, it is usual to call it loop trans-mission and to denote it by L(s) or L( jω).
Aβ xo xt ⁄ .
– = XX′ XX′ XX′ XX′ Aβ Vr Vt -----– = Aβ = Ir It ⁄ .
– Aβ 1 1 Toc -------1 Tsc ------+ ⎝ ⎠ ⎛ ⎞ – = V r μV1 RL || R2 R1 || Rid R + ( ) + [ ] { } RL || R2 R1 || Rid R + ( ) + [ ] { } ro + ------------------------------------------------------------------------------R1 || Rid R + ( ) [ ] R1 || Rid R + ( ) [ ] R2 + --------------------------------------------------Rid Rid R + -----------------– = L Aβ V r V ⁄ t – = V r V ⁄ 1.
– = = 866 Chapter 10 Feedback Finally, we note that the value of the loop gain determined using the method discussed here may differ somewhat from the value determined by the approach studied in the previ-ous sections. The difference stems from the approximations made in the feedback analysis method utilized in the previous sections. However, as the reader will find by solving the end-of-chapter problems, the difference is usually limited to a few percent.
10.9.2 Equivalence of Circuits from a Feedback-Loop Point of View From the study of circuit theory we know that the poles of a circuit are independent of the external excitation. In fact the poles, or the natural modes (which is a more appropriate Figure 10.32 A conceptual feedback loop is broken at and a test voltage Vt is applied. The imped-ance Zt is equal to that previously seen looking to the left of The loop gain Aβ = −Vr/Vt , where Vr is the returned voltage. As an alternative, Aβ can be determined by finding the open-circuit transfer function Toc, as in (c), and the short-circuit transfer function Tsc, as in (d), and combining them as indicated.
X X' Zt (a) (b) Vt Vr Zt A Vr / Vt (c) Vt Voc Vt Toc Voc It Isc A 1 1 1 Toc Tsc Tsc Isc It (d) XX′ XX′.
10.9 Determining the Loop Gain 867 name), can be determined by setting the external excitation to zero. It follows that the poles of a feedback amplifier depend only on the feedback loop. This will be confirmed in a later section, where we show that the characteristic equation (whose roots are the poles) is com-pletely determined by the loop gain. Thus, a given feedback loop may be used to generate a number of circuits having the same poles but different transmission zeros. The closed-loop gain and the transmission zeros depend on how and where the input signal is injected into the loop.
As an example, return to the feedback loop of Fig. 10.33(a). This loop can be used to generate the noninverting op-amp circuit by feeding the input voltage signal to the terminal of R that is connected to ground; that is, we lift this terminal off ground and connect it to Vs.
The same feedback loop can be used to generate the inverting op-amp circuit by feeding the input voltage signal to the terminal of R1 that is connected to ground.
Recognition of the fact that two or more circuits are equivalent from a feedback-loop point of view is very useful because (as will be shown in Section 10.10) stability is a func-tion of the loop. Thus one needs to perform the stability analysis only once for a given loop. In Chapter 16 we shall employ the concept of loop equivalence in the synthesis of active filters.
Figure 10.33 (a) A feedback loop that represents both the inverting and the noninverting op-amp config-urations; (b) equivalent circuit; (c) determination of the loop gain.
(a) (b) Rid V1 ro mV1 (c) 868 Chapter 10 Feedback 10.10 The Stability Problem 10.10.1 Transfer Function of the Feedback Amplifier In a feedback amplifier such as that represented by the general structure of Fig. 10.1, the open-loop gain A is generally a function of frequency, and it should therefore be more accurately called the open-loop transfer function, A(s). Also, we have been assuming for the most part that the feedback network is resistive and hence that the feedback factor β is constant, but this need not be always the case. We shall therefore assume that in the general case the feedback transfer function is β(s). It follows that the closed-loop transfer function Af(s) is given by (10.81) To focus attention on the points central to our discussion in this section, we shall assume that the amplifier is direct coupled with constant dc gain A0 and with poles and zeros occur-ring in the high-frequency band. Also, for the time being let us assume that at low frequen-cies β(s) reduces to a constant value. Thus at low frequencies the loop gain A(s)β(s) becomes a constant, which should be a positive number; otherwise the feedback would not be negative. The question then is: What happens at higher frequencies?
For physical frequencies s = jω, Eq. (10.81) becomes (10.82) Thus the loop gain A( jω)β( jω) is a complex number that can be represented by its magni-tude and phase, (10.83) 10.18 Find the loop gain for the feedback amplifier in Fig. 10.17 (Example 10.4). Set break the loop at the gate of apply a voltage to the gate of and determine the returned voltage at the drain of Evaluate the expression for for the values given in Example 10.4 and compare to the value obtained in Example 10.4. Neglect and Ans.
; 16.67 (compared to 17.39 obtained in Example 10.4) 10.19 Find the loop gain for the feedback amplifier in Fig. E10.15 (Exercise 10.15). Set , break the loop at the gate of Q, apply a voltage to the gate of Q, and determine the voltage that appears across . Find the value of using the component values given in Exercise 10.15, and compare to the value given in the answer to Exercise 10.15.
Ans.
; 3.22 (compared to 3.03 obtained in Exercise 10.15) Aβ Vs 0, = Q2, Vt Q2, Vr Q1.
Aβ ro1 ro2.
Aβ gm2RD2 RD2 R2 R1 1 gm2 --------|| ⎝ ⎠ ⎛ ⎞ + + ------------------------------------------------------R1RD1 R1 1 gm1 --------+ ---------------------= Aβ Is 0 = Vt Vr Rs Aβ Aβ gmroRs ro Rf Rs + + ---------------------------= EXERCISES Af s ( ) A s ( ) 1 A s ( )β s ( ) + -------------------------------= Af jω ( ) A jω ( ) 1 A jω ( )β jω ( ) + ---------------------------------------= L jω ( ) A jω ( )β jω ( ) ≡ = A jω ( )β jω ( ) e jφ ω ( ) 10.10 The Stability Problem 869 It is the manner in which the loop gain varies with frequency that determines the stability or instability of the feedback amplifier. To appreciate this fact, consider the frequency at which the phase angle becomes 180°. At this frequency, ω180, the loop gain A( jω)β( jω) will be a real number with a negative sign. Thus at this frequency the feedback will become pos-itive. If at ω = ω180 the magnitude of the loop gain is less than unity, then from Eq. (10.82) we see that the closed-loop gain Af ( jω) will be greater than the open-loop gain A( jω), since the denominator of Eq. (10.82) will be smaller than unity. Nevertheless, the feedback ampli-fier will be stable.
On the other hand, if at the frequency ω180 the magnitude of the loop gain is equal to unity, it follows from Eq. (10.82) that Af (jω) will be infinite. This means that the amplifier will have an output for zero input; this is by definition an oscillator. To visualize how this feedback loop may oscillate, consider the general loop of Fig. 10.1 with the external input xs set to zero. Any disturbance in the circuit, such as the closure of the power-supply switch, will generate a signal xi(t) at the input to the amplifier. Such a noise signal usually contains a wide range of frequen-cies, and we shall now concentrate on the component with frequency ω = ω180, that is, the sig-nal Xi sin(ω180t). This input signal will result in a feedback signal given by Since Xf is further multiplied by –1 in the summer block at the input, we see that the feed-back causes the signal Xi at the amplifier input to be sustained. That is, from this point on, there will be sinusoidal signals at the amplifier input and output of frequency ω180. Thus the amplifier is said to oscillate at the frequency ω180.
The question now is: What happens if at ω180 the magnitude of the loop gain is greater than unity? We shall answer this question, not in general, but for the restricted yet very important class of circuits in which we are interested here. The answer, which is not obvious from Eq. (10.82), is that the circuit will oscillate, and the oscillations will grow in amplitude until some nonlinearity (which is always present in some form) reduces the magnitude of the loop gain to exactly unity, at which point sustained oscillations will be obtained. This mech-anism for starting oscillations by using positive feedback with a loop gain greater than unity, and then using a nonlinearity to reduce the loop gain to unity at the desired amplitude, will be exploited in the design of sinusoidal oscillators in Chapter 17. Our objective here is just the opposite: Now that we know how oscillations could occur in a negative-feedback ampli-fier, we wish to find methods to prevent their occurrence.
10.10.2 The Nyquist Plot The Nyquist plot is a formalized approach for testing for stability based on the discussion above. It is simply a polar plot of loop gain with frequency used as a parameter. Figure 10.34 shows such a plot. Note that the radial distance is and the angle is the phase angle φ. The solid-line plot is for positive frequencies. Since the loop gain—and for that matter any gain function of a physical network—has a magnitude that is an even function of frequency and a phase that is an odd function of frequency, the Aβ plot for negative fre-quencies (shown in Fig. 10.34 as a broken line) can be drawn as a mirror image through the Re axis.
The Nyquist plot intersects the negative real axis at the frequency ω180. Thus, if this intersection occurs to the left of the point (–1, 0), we know that the magnitude of loop gain at this frequency is greater than unity and the amplifier will be unstable. On the other hand, if the intersection occurs to the right of the point (–1, 0) the amplifier will be stable.
It follows that if the Nyquist plot encircles the point (–1, 0) then the amplifier will be φ ω ( ) Xf = A jω180 ( )β jω180 ( )Xi X – i = Aβ 870 Chapter 10 Feedback unstable. It should be mentioned, however, that this statement is a simplified version of the Nyquist criterion; nevertheless, it applies to all the circuits in which we are inter-ested. For the full theory behind the Nyquist method and for details of its application, consult Haykin (1970).
10.11 Effect of Feedback on the Amplifier Poles The amplifier frequency response and stability are determined directly by its poles. There-fore we shall investigate the effect of feedback on the poles of the amplifier.6 Figure 10.34 The Nyquist plot of an unstable amplifier.
6 For a brief review of poles and zeros and related concepts, refer to Appendix F.
10.20 Consider a feedback amplifier for which the open-loop transfer function A(s) is given by Let the feedback factor β be a constant independent of frequency. Find the frequency ω180 at which the phase shift is 180°. Then, show that the feedback amplifier will be stable if the feedback factor β is less than a critical value βcr and unstable if β ≥ βcr, and find the value of βcr.
Ans.
A s ( ) 10 1 s 104 ⁄ + -----------------------⎝ ⎠ ⎛ ⎞3 = ω180 = 3 104 × rad/s; βcr 0.008 = EXERCISE 10.11 Effect of Feedback on the Amplifier Poles 871 10.11.1 Stability and Pole Location We shall begin by considering the relationship between stability and pole location. For an amplifier or any other system to be stable, its poles should lie in the left half of the s plane. A pair of complex-conjugate poles on the jω axis gives rise to sustained sinusoidal oscillations.
Poles in the right half of the s plane give rise to growing oscillations.
To verify the statement above, consider an amplifier with a pole pair at s = σ0 ± jωn. If this amplifier is subjected to a disturbance, such as that caused by closure of the power-supply switch, its transient response will contain terms of the form (10.84) This is a sinusoidal signal with an envelope . Now if the poles are in the left half of the s plane, then σ0 will be negative and the oscillations will decay exponentially toward zero, as shown in Fig. 10.35(a), indicating that the system is stable. If, on the other hand, the poles are in Figure 10.35 Relationship between pole location and transient response.
v t ( ) = e σ0t e +jωnt e jωnt – + [ ] = 2e σ0t ωnt ( ) cos e σ0t (a) (b) (c) 872 Chapter 10 Feedback the right half-plane, then σ0 will be positive, and the oscillations will grow exponentially (until some nonlinearity limits their growth), as shown in Fig. 10.35(b). Finally, if the poles are on the jω axis, then σ0 will be zero and the oscillations will be sustained, as shown in Fig. 10.35(c).
Although the discussion above is in terms of complex-conjugate poles, it can be shown that the existence of any right-half-plane poles results in instability.
10.11.2 Poles of the Feedback Amplifier From the closed-loop transfer function in Eq. (10.81), we see that the poles of the feedback amplifier are the zeros of 1 + A(s)β (s). That is, the feedback-amplifier poles are obtained by solving the equation (10.85) which is called the characteristic equation of the feedback loop. It should therefore be apparent that applying feedback to an amplifier changes its poles.
In the following, we shall consider how feedback affects the amplifier poles. For this purpose we shall assume that the open-loop amplifier has real poles and no finite zeros (i.e., all the zeros are at s = ∞). This will simplify the analysis and enable us to focus our attention on the fundamental concepts involved. We shall also assume that the feedback factor β is independent of frequency.
10.11.3 Amplifier with a Single-Pole Response Consider first the case of an amplifier whose open-loop transfer function is characterized by a single pole: (10.86) The closed-loop transfer function is given by (10.87) Thus the feedback moves the pole along the negative real axis to a frequency ωPf, (10.88) This process is illustrated in Fig. 10.36(a). Figure 10.36(b) shows Bode plots for and Note that while at low frequencies the difference between the two plots is 20 log(1 + A0β ), the two curves coincide at high frequencies. One can show that this indeed is the case by approximating Eq. (10.87) for frequencies ω ωP(1 + A0β): (10.89) Physically speaking, at such high frequencies the loop gain is much smaller than unity and the feedback is ineffective.
Figure 10.36(b) clearly illustrates the fact that applying negative feedback to an ampli-fier results in extending its bandwidth at the expense of a reduction in gain. Since the pole of the closed-loop amplifier never enters the right half of the s plane, the single-pole amplifier is stable for any value of β. Thus this amplifier is said to be unconditionally stable. This 1 A(s)β(s) + = 0 A(s) = A0 1 s ωP ⁄ + ----------------------Af (s) = A0 1 A0β + ( ) ⁄ 1 s ωP ⁄ 1 A0β + ( ) + ----------------------------------------------ωPf = ωP 1 A0β + ( ) A Af .
Af (s) A0ωP s ------------ A(s) 10.11 Effect of Feedback on the Amplifier Poles 873 result, however, is hardly surprising, since the phase lag associated with a single-pole response can never be greater than 90°. Thus the loop gain never achieves the 180° phase shift required for the feedback to become positive.
10.11.4 Amplifier with Two-Pole Response Consider next an amplifier whose open-loop transfer function is characterized by two real-axis poles: (10.90) In this case, the closed-loop poles are obtained from 1 + A(s)β = 0, which leads to (10.91) Thus the closed-loop poles are given by (10.92) From Eq. (10.92) we see that as the loop gain A0 β is increased from zero, the poles are brought closer together. Then a value of loop gain is reached at which the poles become coincident. If the loop gain is further increased, the poles become complex conjugate and move along a vertical line. Figure 10.37 shows the locus of the poles for increasing loop gain. This plot is called a root-locus diagram, where “root” refers to the fact that the poles are the roots of the characteristic equation.
Figure 10.36 Effect of feedback on (a) the pole location and (b) the frequency response of an amplifier having a single-pole, open-loop response.
(a) (b) 10.21 An op amp having a single-pole rolloff at 100 Hz and a low-frequency gain of 105 is operated in a feedback loop with β = 0.01. What is the factor by which feedback shifts the pole? To what fre-quency? If β is changed to a value that results in a closed-loop gain of +1, to what frequency does the pole shift? Ans. 1001; 100.1 kHz; 10 MHz EXERCISE A(s) = A0 (1 s ωP1 ⁄ ) 1 s ωP2 ⁄ + ( ) + ----------------------------------------------------------s 2 s ωP1 ωP2 + ( ) 1 A0β + ( )ωP1ωP2 + + = 0 s = 1 2 --- ωP1 ωP2 + ( ) – ± 1 2 ---ωP1 ωP2 + ( ) 2 4 1 A0β + ( )ωP1ωP2 – 874 Chapter 10 Feedback From the root-locus diagram of Fig. 10.37 we see that this feedback amplifier also is unconditionally stable. Again, this result should come as no surprise; the maximum phase shift of A(s) in this case is 180° (90° per pole), but this value is reached at ω = ∞. Thus there is no finite frequency at which the phase shift reaches 180°.
Another observation to make on the root-locus diagram of Fig. 10.37 is that the open-loop amplifier might have a dominant pole, but this is not necessarily the case for the closed-loop amplifier. The response of the closed-loop amplifier can, of course, always be plotted once the poles have been found from Eq. (10.92). As is the case with second-order responses generally, the closed-loop response can show a peak (see Chapter 16). To be more specific, the characteristic equation of a second-order network can be written in the standard form (10.93) where ω0 is called the pole frequency and Q is called pole Q factor. The poles are complex if Q is greater than 0.5. A geometric interpretation for ω0 and Q of a pair of complex-conjugate poles is given in Fig. 10.38, from which we note that ω0 is the radial distance of the poles from the origin and that Q indicates the distance of the poles from the jω axis. Poles on the jω axis have Q = ∞. By comparing Eqs. (10.91) and (10.93) we obtain the Q factor for the poles of the feed-back amplifier as (10.94) Figure 10.37 Root-locus diagram for a feedback amplifier whose open-loop transfer function has two real poles.
s 2 sω0 Q --------ω0 2 + + 0 = Q 1 A0β + ( )ωP1ωP2 ωP1 ω + P2 ---------------------------------------------= Figure 10.38 Definition of ω0 and Q of a pair of complex-conjugate poles.
10.11 Effect of Feedback on the Amplifier Poles 875 From the study of second-order network responses in Chapter 16, it will be seen that the response of the feedback amplifier under consideration shows no peaking for Q ≤ 0.707. The boundary case corresponding to Q = 0.707 (poles at 45° angles) results in the maximally flat response. Figure 10.39 shows a number of possible responses obtained for various val-ues of Q (or, correspondingly, various values of A0β).
Figure 10.39 Normalized gain of a two-pole feedback amplifier for various values of Q. Note that Q is determined by the loop gain according to Eq. (10.94).
0 (log scale) Normalized gain (dB) Q 1 Q 0.707 (maximally flat response) 12 dB/octave Q 0.5 Q 0.3 10.22 An amplifier with a low-frequency gain of 100 and poles at 104 rad/s and 106 rad/s is incorporated in a negative-feedback loop with feedback factor β. For what value of β do the poles of the closed-loop amplifier coincide? What is the corresponding Q of the resulting second-order system? For what value of β is a maximally flat response achieved? What is the low-frequency closed-loop gain in the maximally flat case?
Ans. 0.245; 0.5; 0.5; 1.96 V/V EXERCISE As an illustration of some of the ideas just discussed, we consider the positive-feedback circuit shown in Fig. 10.40(a). Find the loop transmission L(s) and the characteristic equation. Sketch a root-locus diagram for varying K, and find the value of K that results in a maximally flat response and the value of K that makes the circuit oscillate. Assume that the amplifier has frequency-idependent gain, infinite input imped-ance, and zero output impedance. Solution To obtain the loop transmission, we short-circuit the signal source and break the loop at the amplifier input. We then apply a test voltage Vt and find the returned voltage Vr, as indicated in Fig. 10.40(b). The Example 10.9 876 Chapter 10 Feedback loop transmission is given by (10.95) where T(s) is the transfer function of the two-port RC network shown inside the broken-line box in Fig.
10.40(b): (10.96) h Figure 10.40 Circuits and plot for Example 10.9.
K 1 Q 0.5 K 3 Q K 1.586 Q 0.707 K 3 Q K 0 Q j 45 s plane 0 45 1 3 K 1.586 Q 0.707 (c) C Vs R K Vo R C (a) V1 R K R C Vt C Vr (b) Example 10.9 continued L s ( ) A s ( )β s ( ) ≡ L s ( ) Vr Vt -----– KT s ( ) – = = T s ( ) ≡V r V 1 -----s(1 CR ⁄ ) s2 s(3 CR ⁄ ) (1 CR ⁄ )2 + + -------------------------------------------------------------= 10.11 Effect of Feedback on the Amplifier Poles 877 Example 10.9 illustrates the use of feedback (positive feedback in this case) to move the poles of an RC network from their negative real-axis locations to complex-conjugate loca-tions. One can accomplish the same task using negative feedback, as the root-locus diagram of Fig. 10.37 demonstrates. The process of pole control is the essence of active-filter design, as will be discussed in Chapter 16.
10.11.5 Amplifiers with Three or More Poles Figure 10.41 shows the root-locus diagram for a feedback amplifier whose open-loop response is characterized by three poles. As indicated, increasing the loop gain from zero moves the highest-frequency pole outward while the two other poles are brought closer together. As A0β is increased further, the two poles become coincident and then become complex and conjugate. A value of A0β exists at which this pair of complex-conjugate poles enters the right half of the s plane, thus causing the amplifier to become unstable. Thus, (10.97) The characteristic equation is (10.98) that is, (10.99) By comparing this equation to the standard form of the second-order characteristic equation (Eq.
10.93) we see that the pole frequency ω0 is given by (10.100) and the Q factor is (10.101) Thus for K = 0, the poles have and are therefore located on the negative real axis. As K is increased, the poles are brought closer together and eventually coincide (Q = 0.5, K = 1). Further increas-ing K results in the poles becoming complex and conjugate. The root locus is then a circle because the radial distance ω0 remains constant (Eq. 10.100) independent of the value of K.
The maximally flat response is obtained when Q = 0.707, which results when K = 1.586. In this case the poles are at 45° angles, as indicated in Fig. 10.40(c). The poles cross the jω axis into the right half of the s plane at the value of K that results in Q = ∞, that is, K = 3. Thus for K ≥ 3 this circuit becomes unsta-ble. This might appear to contradict our earlier conclusion that the feedback amplifier with a second-order response is unconditionally stable. Note, however, that the circuit in this example is quite different from the negative-feedback amplifier that we have been studying. Here we have an amplifier with a positive gain K and a feedback network whose transfer function T(s) is frequency dependent. This feedback is in fact positive, and the circuit will oscillate at the frequency for which the phase of T( jω) is zero.
L s ( ) s K/CR ( ) – s2 s 3/CR ( ) 1/CR ( )2 + + ---------------------------------------------------------= 1 L s ( ) + 0 = s2 s 3 CR --------1 CR --------⎝ ⎠ ⎛ ⎞ 2 s K CR --------– + + 0 = s2 s3 K – CR -------------1 CR --------⎝ ⎠ ⎛ ⎞ 2 + + 0 = ω0 1 CR --------= Q 1 3 K – -------------= Q = 1 3 ---878 Chapter 10 Feedback This result is not entirely unexpected, since an amplifier with three poles has a phase shift that reaches –270° as ω approaches ∞. Thus there exists a finite frequency, ω180, at which the loop gain has 180° phase shift.
From the root-locus diagram of Fig. 10.41, we observe that one can always maintain amplifier stability by keeping the loop gain A0β smaller than the value corresponding to the poles entering the right half-plane. In terms of the Nyquist diagram, the critical value of A0β is that for which the diagram passes through the (–1, 0) point. Reducing A0β below this value causes the Nyquist plot to shrink and thus intersect the negative real axis to the right of the (–1, 0) point, indicating stable amplifier performance. On the other hand, increasing A0β above the critical value causes the Nyquist plot to expand, thus encircling the (–1, 0) point and indicating unstable performance. For a given open-loop gain A0 the conclusions above can be stated in terms of the feed-back factor β. That is, there exists a maximum value for β above which the feedback ampli-fier becomes unstable. Alternatively, we can state that there exists a minimum value for the closed-loop gain Af0 below which the amplifier becomes unstable. To obtain lower values of closed-loop gain one needs therefore to alter the loop transfer function L(s). This is the pro-cess known as frequency compensation. We shall study the theory and techniques of fre-quency compensation in Section 10.13. Before leaving this section we point out that construction of the root-locus diagram for amplifiers having three or more poles as well as finite zeros is an involved process for which a systematic procedure exists. However, such a procedure will not be presented here, and the interested reader should consult Haykin (1970). Although the root-locus diagram provides the amplifier designer with considerable insight, other, simpler techniques based on Bode plots can be effectively employed, as will be explained in Section 10.12.
Figure 10.41 Root-locus diagram for an amplifier with three poles. The arrows indicate the pole movement as A0β is increased.
10.23 Consider a feedback amplifier for which the open-loop transfer function A(s) is given by A s ( ) 10 1 s/104 + ---------------------⎝ ⎠ ⎛ ⎞3 = EXERCISE 10.12 Stability Study Using Bode Plots 879 10.12 Stability Study Using Bode Plots 10.12.1 Gain and Phase Margins From Sections 10.10 and 10.11 we know that whether a feedback amplifier is or is not sta-ble can be determined by examining its loop gain Aβ as a function of frequency. One of the simplest and most effective means for doing this is through the use of a Bode plot for Aβ, such as the one shown in Fig. 10.42. (Note that because the phase approaches –360°, the net-work examined is a fourth-order one.) The feedback amplifier whose loop gain is plotted in Fig. 10.42 will be stable, since at the frequency of 180° phase shift, ω180, the magnitude of the loop gain is less than unity (negative dB). The difference between the value of at ω180 and unity, called the gain margin, is usually expressed in decibels. The gain margin repre-sents the amount by which the loop gain can be increased while stability is maintained.
Feedback amplifiers are usually designed to have sufficient gain margin to allow for the inevitable changes in loop gain with temperature, time, and so on. Another way to investigate the stability and to express its degree is to examine the Bode plot at the frequency for which = 1, which is the point at which the magnitude plot crosses the 0-dB line. If at this frequency the phase angle is less (in magnitude) than 180°, then the amplifier is stable. This is the situation illustrated in Fig. 10.42. The difference between the phase angle at this frequency and 180° is termed the phase margin. On the other hand, if at the frequency of unity loop-gain magnitude, the phase lag is in excess of 180°, the amplifier will be unstable.
Let the feedback factor β be frequency independent. Find the closed-loop poles as functions of β, and show that the root locus is that of Fig. E10.23. Also find the value of β at which the amplifier becomes unstable. (Note: This is the same amplifier that was considered in Exercise 10.20.) Ans. See Fig. E10.23; βcritical = 0.008 Figure 10.E23 Aβ Aβ 880 Chapter 10 Feedback 10.12.2 Effect of Phase Margin on Closed-Loop Response Feedback amplifiers are normally designed with a phase margin of at least 45°. The amount of phase margin has a profound effect on the shape of the closed-loop gain response. To see this relationship, consider a feedback amplifier with a large low-frequency loop gain, A0β 1. It follows that the closed-loop gain at low frequencies is approximately 1/β. Denot-ing the frequency at which the magnitude of loop gain is unity by ω1, we have (refer to Fig.
10.42) (10.102a) where (10.102b) Figure 10.42 Bode plot for the loop gain Aβ illustrating the definitions of the gain and phase margins.
10.24 Consider an op amp having a single-pole, open-loop response with A0 = 105 and fP = 10 Hz. Let the op amp be ideal otherwise (infinite input impedance, zero output impedance, etc.). If this am-plifier is connected in the noninverting configuration with a nominal low-frequency, closed-loop gain of 100, find the frequency at which = 1. Also, find the phase margin.
Ans. 104 Hz; 90° Aβ EXERCISE A jω1 ( )β = 1 e jθ – × θ 180° phase margin – = 10.12 Stability Study Using Bode Plots 881 At ω1 the closed-loop gain is (10.103) Substituting from Eq. (10.102a) gives (10.104) Thus the magnitude of the gain at ω1 is (10.105) For a phase margin of 45°, θ = 135°; and we obtain (10.106) That is, the gain peaks by a factor of 1.3 above the low-frequency value of 1/β. This peaking increases as the phase margin is reduced, eventually reaching ∞ when the phase margin is zero. Zero phase margin, of course, implies that the amplifier can sustain oscillations [poles on the jω axis; Nyquist plot passing through (−1, 0)].
10.12.3 An Alternative Approach for Investigating Stability Investigating stability by constructing Bode plots for the loop gain Aβ can be a tedious and time-consuming process, especially if we have to investigate the stability of a given amplifier for a variety of feedback networks. An alternative approach, which is much simpler, is to construct a Bode plot for the open-loop gain A( jω) only. Assuming for the time being that β is independent of frequency, we can plot 20 log(1/β) as a horizontal straight line on the same plane used for 20 The difference between the two curves will be (10.107) which is the loop gain (in dB). We may therefore study stability by examining the difference between the two plots. If we wish to evaluate stability for a different feedback factor, we sim-ply draw another horizontal straight line at the level 20 log(1/β).
To illustrate, consider an amplifier whose open-loop transfer function is characterized by three poles. For simplicity let the three poles be widely separated—say, at 0.1 MHz, 1 MHz, and 10 MHz, as shown in Fig. 10.43. Note that because the poles are widely separated, the Af jω1 ( ) A jω1 ( ) 1 A jω1 ( )β + ------------------------------= Af jω1 ( ) 1 β ⁄ ( )e jθ – 1 e jθ – + -----------------------= Af jω1 ( ) 1 β ⁄ 1 e jθ – + --------------------= Af jω1 ( ) 1.31 β ---= 10.25 Find the closed-loop gain at ω1 relative to the low-frequency gain when the phase margin is 30°, 60°, and 90°.
Ans. 1.93; 1; 0.707 EXERCISE A .
log 20 A jω ( ) 20 1 β --- 20 Aβ log = log – log 882 Chapter 10 Feedback phase is approximately −45° at the first pole frequency, −135° at the second, and −225° at the third. The frequency at which the phase of A( jω) is −180° lies on the −40-dB/decade segment, as indicated in Fig. 10.43.
The open-loop gain of this amplifier can be expressed as (10.108) from which can be easily determined for any frequency f (in Hz), and the phase can be obtained as (10.109) The magnitude and phase graphs shown in Fig. 10.43 are obtained using the method for constructing Bode plots (Appendix F). These graphs provide approximate values for Figure 10.43 Stability analysis using Bode plot of |A|.
72 phase margin 100 90 80 70 60 50 40 30 20 10 0 dB 10 108 102 104 105 106 107 f (Hz) 0 270 45 90 135 108 225 10 108 102 103 104 105 106 107 f (Hz) A 20 dB/decade X2 (a) (b) 20 log A 20 log 1/ 85 dB (stable) 25 dB gain margin 40 dB/decade 20 log 1/ for zero margins 60 dB/decade f180 20 log 1/ 50 dB (unstable) X1 f180 180 A 10 5 (1 jf 10 5) ⁄ + (1 jf 10 6) ⁄ + (1 jf 10 7) ⁄ + ------------------------------------------------------------------------------------------= A φ −[tan 1 – f 10 5 ⁄ ( ) tan 1 – f 10 6 ⁄ ( ) tan 1 – f 10 7 ⁄ ( )] + + = 10.12 Stability Study Using Bode Plots 883 important amplifier parameters, with more exact values obtainable from Eqs. (10.108) and (10.109). For example, the frequency f180 at which the phase angle is 180° can be found from Fig. 10.43 to be approximately 3.2 106 Hz. Using this value as a starting point, a more exact value can be found by trial and error using Eq. (10.109). The result is f180 = 3.34 × 106 Hz. At this frequency, Eq. (10.108) gives a gain magnitude of 58.2 dB, which is reasonably close to the approximate value of 60 dB given by Fig. 10.43.
Consider next the straight line labeled (a) in Fig. 10.43. This line represents a feedback factor for which 20 log(1/β) = 85 dB, which corresponds to β = 5.623 × 10−5 and a closed-loop gain of 83.6 dB. Since the loop gain is the difference between the curve and the 1/β line, the point of intersection X1 corresponds to the frequency at which Using the graphs of Fig. 10.43, this frequency can be found to be approximately 5.6 × 105 Hz. A more exact value of 4.936 × 105 can be obtained using the transfer-function equations. At this frequency the phase angle is approximately −108°. Thus the closed-loop amplifier, for which 20 log(1/β) = 85 dB, will be stable with a phase margin of 72°. The gain margin can be easily obtained from Fig. 10.43; it is 25 dB.
Next, suppose that we wish to use this amplifier to obtain a closed-loop gain of 50-dB nominal value. Since A0 = 100 dB, we see that and 20 log(A0β) 50 dB, resulting in 20 log(1/β) 50 dB. To see whether this closed-loop amplifier is or is not stable, we draw line (b) in Fig. 10.43 with a height of 50 dB. This line intersects the open-loop gain curve at point X2, where the corresponding phase is greater than 180°. Thus the closed-loop amplifier with 50-dB gain will be unstable.
In fact, it can easily be seen from Fig. 10.43 that the minimum value of 20 log(1/β) that can be used, with the resulting amplifier being stable, is 60 dB. In other words, the minimum value of stable closed-loop gain obtained with this amplifier is approximately 60 dB. At this value of gain, however, a manufactured version of this amplifier may still oscillate, since no margin is left to allow for possible changes in gain.
Since the 180°-phase point always occurs on the −40-dB/decade segment of the Bode plot for , a rule of thumb to guarantee stability is as follows: The closed-loop amplifier will be stable if the 20 log(1/β) line intersects the 20 curve at a point on the −20-dB/ decade segment. Following this rule ensures that a phase margin of at least 45° is obtained.
For the example of Fig. 10.43, the rule implies that the maximum value of β is 10−4, which corresponds to a closed-loop gain of approximately 80 dB.
The rule of thumb above can be generalized for the case in which β is a function of frequency. The general rule states that at the intersection of and the difference of slopes (called the rate of closure) should not exceed 20 dB/decade.
A Aβ 1.
= A0β 1 A log A 20 log[1 β jω ( ) ] ⁄ 20 log A jω ( ) 10.26 Consider an op amp whose open-loop gain is identical to that of Fig. 10.43. Assume that the op amp is ideal otherwise. Let the op amp be connected as a differentiator. Use the rule of thumb above to show that for stable performance the differentiator time constant should be greater than 159 ms. [Hint: Recall that for a differentiator, the Bode plot for has a slope of +20 dB/decade and intersects the 0-dB line at 1/τ, where τ is the differentiator time constant.] 1 β jω ( ) ⁄ EXERCISE 884 Chapter 10 Feedback 10.13 Frequency Compensation In this section, we shall discuss methods for modifying the open-loop transfer function A(s) of an amplifier having three or more poles so that the closed-loop amplifier is stable for a given desired value of closed-loop gain.
10.13.1 Theory The simplest method of frequency compensation consists of introducing a new pole in the function A(s) at a sufficiently low frequency, fD, such that the modified open-loop gain, intersects the 20 log curve with a slope difference of 20 dB/decade. As an example, let it be required to compensate the amplifier whose A(s) is shown in Fig. 10.44 such that closed-loop amplifiers with β as high as 10−2 (i.e., closed-loop gains as low as approximately 40 dB) will be stable. First, we draw a horizontal straight line at the 40-dB level to represent 20 log(1/β), as shown in Fig. 10.44. We then locate point Y on this line at the frequency of the first pole, fP1. From Y we draw a line with −20-dB/decade slope and determine the point at which this line intersects the dc gain line, point This latter point gives the frequency fD of the new pole that has to be introduced in the open-loop transfer function.
Figure 10.44 Frequency compensation for β = 10−2. The response labeled is obtained by introducing an additional pole at fD. The response is obtained by moving the original low-frequency pole to 100 80 60 40 20 0 10 108 102 103 104 105 106 107 dB f (Hz) Y Z A A A Y Z fD fD fP1 fP2 fP3 20 log 1/ 40 dB 60 dB/decade 40 dB/decade 20 dB/decade A ′ A″ fD ′ .
A′ s ( ), 1 β ⁄ ( ) Y′.
10.13 Frequency Compensation 885 The compensated open-loop response is indicated in Fig. 10.44. It has four poles: at fD, fP1, fP2, and fP3. Thus begins to roll off with a slope of −20 dB/decade at fD.
At fP1 the slope changes to – 40 dB/decade, at fP2 it changes to –60 dB/decade, and so on.
Since the 20 log(1/β) line intersects the curve at point Y on the −20-dB/decade segment, the closed-loop amplifier with this β value (or lower values) will be stable.
A serious disadvantage of this compensation method is that at most frequencies the open-loop gain has been drastically reduced. This means that at most frequencies the amount of feedback available will be small. Since all the advantages of negative feedback are directly proportional to the amount of feedback, the performance of the compensated amplifier will be impaired.
Careful examination of Fig. 10.44 shows that the gain is low because of the pole at fP1. If we can somehow eliminate this pole, then—rather than locating point Y, drawing and so on—we can start from point Z (at the frequency of the second pole) and draw the line . This would result in the open-loop curve which shows considerably higher gain than .
Although it is not possible to eliminate the pole at fP1, it is usually possible to shift that pole from f = fP1 to This makes the pole dominant and eliminates the need for intro-ducing an additional lower-frequency pole, as will be explained next.
10.13.2 Implementation We shall now address the question of implementing the frequency-compensation scheme discussed above. The amplifier circuit normally consists of a number of cascaded gain stages, with each stage responsible for one or more of the transfer-function poles. Through manual and/or computer analysis of the circuit, one identifies which stage introduces each of the important poles fP1, fP2, and so on. For the purpose of our discussion, assume that the first pole fP1 is introduced at the interface between the two cascaded differential stages shown in Fig. 10.45(a). In Fig. 10.45(b) we show a simple small-signal model of the circuit at this interface. Current source Ix represents the output-signal current of the Q1−Q2 stage. Resis-tance Rx and capacitance Cx represent the total resistance and capacitance between the two nodes B and . It follows that the pole fP1 is given by (10.110) Let us now connect the compensating capacitor CC between nodes B and . This will result in the modified equivalent circuit shown in Fig. 10.45(c) from which we see that the pole introduced will no longer be at fP1; rather, the pole can be at any desired lower frequency : (10.111) We thus conclude that one can select an appropriate value for CC to shift the pole frequency from fP1 to the value determined by point in Fig. 10.44.
At this juncture it should be pointed out that adding the capacitor CC will usually result in changes in the location of the other poles (those at fP2 and fP3). One might therefore need to calculate the new location of fP2 and perform a few iterations to arrive at the required value for CC.
A ′ s ( ) A ′ 20 A ′ log A ′ s ( ) YY′, ZZ′ A″ s ( ), A′ s ( ) f = fD ′ .
B′ f P1 1 2πCxRx ------------------= B′ fD ′ fD ′ 1 2π Cx CC + ( )Rx ------------------------------------= fD ′ Z′ 886 Chapter 10 Feedback A disadvantage of this implementation method is that the required value of CC is usually quite large. Thus if the amplifier to be compensated is an IC op amp, it will be difficult, and probably impossible, to include this compensating capacitor on the IC chip. (As pointed out in Chapter 7 and in Appendix A, the maximum practical size of a monolithic capacitor is about 100 pF.) An elegant solution to this problem is to connect the compensating capacitor in the feedback path of an amplifier stage. Because of the Miller effect, the compensating capacitance will be multiplied by the stage gain, resulting in a much larger effective capaci-tance. Furthermore, as explained later, another unexpected benefit accrues.
10.13.3 Miller Compensation and Pole Splitting Figure 10.46(a) shows one gain stage in a multistage amplifier. For simplicity, the stage is shown as a common-emitter amplifier, but in practice it can be a more elaborate circuit. In the feedback path of this common-emitter stage we have placed a compensating capacitor Cf .
Figure 10.46(b) shows a simplified equivalent circuit of the gain stage of Fig. 10.46(a).
Here R1 and C1 represent the total resistance and total capacitance between node B and ground. Similarly, R2 and C2 represent the total resistance and total capacitance between node C and ground. Furthermore, it is assumed that C1 includes the Miller component due to capacitance Cμ, and C2 includes the input capacitance of the succeeding amplifier stage.
Finally, Ii represents the output signal current of the preceding stage.
Figure 10.45 (a) Two cascaded gain stages of a multistage amplifier. (b) Equivalent circuit for the inter-face between the two stages in (a). (c) Same circuit as in (b), but with a compensating capacitor CC added.
Note that the analysis here applies equally well to MOS amplifiers.
(a) B B Q1 (b) B B (c) B B 10.13 Frequency Compensation 887 In the absence of the compensating capacitor Cf, we can see from Fig. 10.46(b) that there are two poles—one at the input and one at the output. Let us assume that these two poles are fP1 and fP2 of Fig. 10.44; thus, (10.112) With Cf present, analysis of the circuit yields the transfer function (10.113) The zero is usually at a much higher frequency than the dominant pole, and we shall neglect its effect. The denominator polynomial D(s) can be written in the form (10.114) where and are the new frequencies of the two poles. Normally one of the poles will be dominant; . Thus, (10.115) Equating the coefficients of s in the denominator of Eq. (10.113) and in Eq. (10.115) results in which can be approximated by (10.116) Figure 10.46 (a) A gain stage in a multistage amplifier with a compensating capacitor connected in the feedback path, and (b) an equivalent circuit. Note that although a BJT is shown, the analysis applies equally well to the MOSFET case.
(a) (b) fP1 = 1 2πC1R1 -------------------fP2 1 2πC2R2 -------------------= Vo Ii -----sCf −gm ( )R1R2 1 s C1R1 C2R2 Cf gmR1R2 R1 R2 + + ( ) + + [ ] s2 C1C2 Cf C1 C2 + ( ) + [ ]R1R2 + + -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= D s ( ) 1 s ωP1 ′ ----------+ ⎝ ⎠ ⎛ ⎞1 s ωP2 ′ ----------+ ⎝ ⎠ ⎛ ⎞ 1 s 1 ωP1 ′ ----------1 ωP2 ′ ----------+ ⎝ ⎠ ⎛ ⎞ s 2 ωP1 ′ ωP2 ′ ---------------------+ + = = ωP1 ′ ωP2 ′ ω ′ P1 ωP2 ′ D s ( ) 1 s ωP1 ′ ----------s2 ωP1 ′ ωP2 ′ ---------------------+ + ωP1 ′ 1 C1R1 C2R2 Cf gmR1R2 R1 R2 + + ( ) + + -------------------------------------------------------------------------------------------= ωP1 ′ 1 gmR2Cf R1 -------------------------888 Chapter 10 Feedback To obtain we equate the coefficients of s2 in the denominator of Eq. (10.113) and in Eq. (10.115) and use Eq. (10.116): (10.117) From Eqs. (10.116) and (10.117), we see that as Cf is increased, is reduced and is increased. This action is referred to as pole splitting. Note that the increase in is highly beneficial; it allows us to move point Z (see Fig. 10.44) further to the right, thus resulting in higher compensated open-loop gain. Finally, note from Eq. (10.116) that Cf is multiplied by the Miller-effect factor gmR2, thus resulting in a much larger effective capacitance, gmR2Cf .
In other words, the required value of Cf will be much smaller than that of CC in Fig. 10.45.
ωP2 ′ ωP2 ′ gmCf C1C2 Cf C1 C2 + ( ) + -------------------------------------------------ωP1 ′ ωP2 ′ ωP2 ′ Consider an op amp whose open-loop transfer function is identical to that shown in Fig. 10.43. We wish to compensate this op amp so that the closed-loop amplifier with resistive feedback is stable for any gain (i.e., for β up to unity). Assume that the op-amp circuit includes a stage such as that of Fig. 10.46 with C1 = 100 pF, C2 = 5 pF, and gm = 40 mA/V, that the pole at fP1 is caused by the input circuit of that stage, and that the pole at fP2 is introduced by the output circuit. Find the value of the compensating capacitor for two cases: either if it is connected between the input node B and ground, or in the feedback path of the transis-tor.
Solution First we determine R1 and R2 from Thus, Thus, If a compensating capacitor CC is connected across the input terminals of the transistor stage, then the frequency of the first pole changes from fP1 to The second pole remains unchanged at 1-MHz. The required value for is determined by drawing a −20-dB/decade line from the 1-MHz frequency point on the 20 log(1/β) = 20 log 1 = 0 dB line. This line will intersect the 100-dB dc gain line at 10 Hz. Thus, fP1 0.1 MHz 1 2πC1R1 -------------------= = R1 105 2π -------- Ω = f P2 1 MHz 1 2πC2R2 -------------------= = R2 105 π -------- Ω = fD ′ : fD ′ = 1 2π C1 CC + ( )R1 -------------------------------------fD ′ f D ′ = 10 Hz 1 2π C1 CC + ( )R1 -------------------------------------= Example 10.10 10.13 Frequency Compensation 889 which results in CC 1 μF, which is quite large and certainly cannot be included on the IC chip.
Next, if a compensating capacitor Cf is connected in the feedback path of the transistor, then both poles change location to the values given by Eqs. (10.116) and (10.117): (10.118) To determine where we should locate the first pole, we need to know the value of As an approxima-tion, let us assume that which enables us to obtain Thus it appears that this pole will move to a frequency higher than fP3 (which is 10 MHz). Let us therefore assume that the second pole will be at fP3. This requires that the first pole be located at Thus, which results in Cf = 78.5 pF. Although this value is indeed much greater than C2, we can determine the location of the pole from Eq. (10.118), which yields confirming that this pole has indeed been moved past fP3.
We conclude that using Miller compensation not only results in a much smaller compensating capac-itor but, owing to pole splitting, also enables us to place the dominant pole a decade higher in frequency.
This results in a wider bandwidth for the compensated op amp.
f′ P1 1 2πgmR2CfR1 ------------------------------- fP2 ′ gmCf 2π C1C2 Cf C1 C2 + ( ) + [ ] ------------------------------------------------------------fP2 ′ .
Cf C2, fP2 ′ gm 2π C1 C2 + ( ) ------------------------------60.6 MHz = fP1 ′ f P3 A0 ------107 Hz 105 -----------------100 Hz = = = fP1 ′ = 100 Hz 1 2πgmR2CfR1 -------------------------------= fP2 ′ fP2 = ′ 57.2 MHz, 10.27 A multipole amplifier having a first pole at 1 MHz and an open-loop gain of 100 dB is to be com-pensated for closed-loop gains as low as 20 dB by the introduction of a new dominant pole. At what frequency must the new pole be placed?
Ans. 100 Hz 10.28 For the amplifier described in Exercise 10.27, rather than introducing a new dominant pole, we can use additional capacitance at the circuit node at which the first pole is formed to reduce the frequency of the first pole. If the frequency of the second pole is 10 MHz and if it remains un-changed while additional capacitance is introduced as mentioned, find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as 20 dB. By what factor must the capacitance at the controlling node be increased?
Ans. 1000 Hz; 1000 EXERCISE 890 Chapter 10 Feedback Summary Negative feedback is employed to make the amplifier gain less sensitive to component variations; to control in-put and output impedances; to extend bandwidth; to reduce nonlinear distortion; and to enhance signal-to-interference ratio.
The advantages above are obtained at the expense of a reduction in gain and at the risk of the amplifier becom-ing unstable (that is, oscillating). The latter problem is solved by careful design.
For each of the four basic types of amplifier, there is an appropriate feedback topology. The four topologies, to-gether with their analysis procedure and their effects on input and output impedances, are summarized in Table 10.1 in Section 10.8.
The key feedback parameters are the loop gain (Aβ), which for negative feedback must be a positive dimen-sionless number, and the amount of feedback (1 + Aβ).
The latter directly determines gain reduction, gain de-sensitivity, bandwidth extension, and changes in Ri and Ro.
Since A and β are in general frequency dependent, the poles of the feedback amplifier are obtained by solving the characteristic equation 1 + A(s)β (s) = 0.
For the feedback amplifier to be stable, its poles must all be in the left half of the s plane.
Stability is guaranteed if at the frequency for which the phase angle of Aβ is 180° (i.e., ω180), is less than uni-ty; the amount by which it is less than unity, expressed in decibels, is the gain margin. Alternatively, the amplifier is stable if, at the frequency at which the phase angle is less than 180°; the difference is the phase margin.
The stability of a feedback amplifier can be analyzed by constructing a Bode plot for and superimposing on it a plot for Stability is guaranteed if the two plots inter-sect with a difference in slope no greater than 6 dB/octave.
To make a given amplifier stable for a given feedback fac-tor β, the open-loop frequency response is suitably modi-fied by a process known as frequency compensation.
A popular method for frequency compensation involves connecting a feedback capacitor across an inverting stage in the amplifier. This causes the pole formed at the input of the amplifier stage to shift to a lower frequency and thus be-come dominant, while the pole formed at the output of the amplifier stage is moved to a very high frequency and thus becomes unimportant. This process is known as pole splitting.
Aβ Aβ = 1, A 1 β ⁄ .
PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to demonstrate the value of using SPICE simulation to ver-ify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier non-linear distortion. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not spec-ified in the problem statement, you are to make a reason-able assumption. difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 10.1: The General Feedback Structure 10.1 A negative-feedback amplifier has a closed-loop gain Af = 100 and an open-loop gain A = 104. What is the feed-back factor β ? If a manufacturing error results in a reduction of A to 103, what closed-loop gain results? What is the per-centage change in Af corresponding to this factor of 10 reduc-tion in A?
10.2 Consider the op-amp circuit shown in Fig. P10.2, where the op amp has infinite input resistance and zero out-put resistance but finite open-loop gain A.
(a) Convince yourself that (b) If k , find that results in V/V for the following three cases: (i) V/V; (ii) V/V; (iii) V/V.
β R1 R1 R2 + ( ) ⁄ = R1 10 = Ω R2 Af 10 = A 1000 = A 100 = A 12 = Problems 891 CHAPTER 10 PR OBLEM S (c) For each of the three cases in (b), find the percentage change in that results when A decreases by 20%. Com-ment on the results.
10.3 The noninverting buffer op-amp configuration shown in Fig. P10.3 provides a direct implementation of the feed-back loop of Fig. 10.1. Assuming that the op amp has infi-nite input resistance and zero output resistance, what is β? If A = 1000, what is the closed-loop voltage gain? What is the amount of feedback (in dB)? For Vs = 1 V, find Vo and Vi. If A decreases by 10%, what is the corresponding percentage decrease in Af?
10.4 In a particular circuit represented by the block diagram of Fig. 10.1, a signal of 1 V from the source results in a dif-ference signal of 10 mV being provided to the amplifying ele-ment A, and 10 V applied to the load. For this arrangement, identify the values of A and β that apply.
10.5 Find the loop gain and the amount of feedback of a voltage amplifier for which Af and differ by (a) 1%, (b) 5%, (c) 10%, (d) 50%.
10.6 In a particular amplifier design, the β network con-sists of a linear potentiometer for which β is 0.00 at one end, 1.00 at the other end, and 0.50 in the middle. As the potenti-ometer is adjusted, find the three values of closed-loop gain that result when the amplifier open-loop gain is (a) 1 V/V, (b) 10 V/V, (c) 100 V/V, (d) 10,000 V/V.
10.7 A newly constructed feedback amplifier undergoes a performance test with the following results: With the feed-back connection removed, a source signal of 5 mV is required to provide a 10-V output to the load; with the feed-back connected, a 10-V output requires a 200-mV source signal. For this amplifier, identify values of A, β, Aβ, the closed-loop gain, and the amount of feedback (in dB).
Section 10.2: Some Properties of Negative Feedback 10.8 For the negative-feedback loop of Fig. 10.1, find the loop gain Aβ for which the sensitivity of closed-loop gain to open-loop gain [i.e., is –40 dB. For what value of Aβ does the sensitivity become 1/2?
D 10.9 A designer is considering two possible designs of a feedback amplifier. The ultimate goal is V/V. One design employs an amplifier for which V/V and the other uses V/V. Find and the desensitivity factor in both cases. If the amplifier units have a gain uncertainty of %, what is the gain uncertainty for the closed-loop amplifiers utilizing this amplifier type? If the same result is to be achieved with the ampli-fier, what is the maximum allowable uncertainty in its gain?
D 10.10 A designer is required to achieve a closed-loop gain of % V/V using a basic amplifier whose gain variation is %. What nominal value of A and (assumed constant) are required?
D 10.11 A circuit designer requires a gain of % V/V using an amplifier whose gain varies by a factor of 10 over temperature and time. What is the lowest gain required? The nominal gain? The value of ?
D 10.12 A power amplifier employs an output stage whose gain varies from 2 to 12 for various reasons. What is the gain of an ideal (non varying) amplifier connected to drive it so that an overall gain with feedback of % V/V can be achieved? What is the value of to be used? What are the requirements if must be held within %? For each of these situations, what preamplifier gain and feed-back factor are required if is to be 10 V/V (with the two possible tolerances)?
D 10.13 It is required to design an amplifier with a gain of 100 that is accurate to within ±1%. You have available amplifier stages with a gain of 1000 that is accurate to within ±30%. Provide a design that uses a number of these gain stages in cascade, with each stage employing negative feedback of an appropriate amount. Obviously, your design should use the lowest possible number of stages while meet-ing specification.
10.14 Consider an amplifier having a midband gain AM and a low-frequency response characterized by a pole at s = −ωL and a zero at s = 0. Let the amplifier be connected in a nega-tive-feedback loop with a feedback factor β. Find an expres-Af Vs A R1 R2 Vo Figure P10.2 A Figure P10.3 1 β ⁄ (dAf Af) ⁄ (dA A) ⁄ ⁄ ] Af 20 = A 500 = A 250 = β A 500 = 10 ± A 250 = 25 1 ± 10 ± β 25 1 ± β 100 5 ± β Af 0.5 ± β Af CHAPTER 10 PR OBLE MS 892 Chapter 10 Feedback sion for the midband gain and the lower 3-dB frequency of the closed-loop amplifier. By what factor have both changed?
D 10.15 It is required to design an amplifier to have a nominal closed-loop gain of 10 V/V using a battery-oper-ated amplifier whose gain reduces to half its normal full-bat-tery value over the life of the battery. If only 2% drop in closed-loop gain is desired, what nominal open-loop ampli-fier gain must be used in the design? (Note that since the change in A is large, it is inaccurate to use differentials.) What value of β should be chosen? If component-value vari-ation in the β network may produce as much as a ±1% varia-tion in β, to what value must A be raised to ensure the required minimum gain?
10.16 A capacitively coupled amplifier has a midband gain of 1000 V/V, a single high-frequency pole at 10 kHz, and a single low-frequency pole at 100 Hz. Negative feed-back is employed so that the midband gain is reduced to 10.
What are the upper and lower 3-dB frequencies of the closed-loop gain?
D 10.17 Low-cost audio power amplifiers often avoid direct coupling of the loudspeaker to the output stage because any resulting dc bias current in the speaker can use up (and thereby waste) its limited mechanical dynamic range. Unfortunately, the coupling capacitor needed can be large! But feedback helps. For example, for an 8-Ω loud-speaker and Hz, what size capacitor is needed?
Now, if feedback is arranged around the amplifier and the speaker so that a closed-loop gain V/V is obtained from an amplifier whose open-loop gain is 1000 V/V, what value of results? If the ultimate product-design specifi-cation requires a 50-Hz cutoff, what capacitor can be used?
D 10.18 It is required to design a dc amplifier with a low-frequency gain of 1000 and a 3-dB frequency of 0.5 MHz.
You have available gain stages with a gain of 1000 but with a dominant high-frequency pole at 10 kHz. Provide a design that employs a number of such stages in cascade, each with negative feedback of an appropriate amount. Use identical stages. [Hint: When negative feedback of an amount (1 + Aβ) is employed around a gain stage, its x-dB fre-quency is increased by the factor (1 + Aβ).] D 10.19 Design a supply-ripple-reduced power amplifier for which the output stage can be modeled by the block dia-gram of Fig. 10.4, where A1 = 0.9 V/V, and the power-sup-ply ripple VN = +1 V. A closed-loop gain of 10 V/V is desired. What is the gain of the low-ripple preamplifier needed to reduce the output ripple to ±100 mV? To ±10 mV? To ±1 mV? For each case, specify the value required for the feedback factor β.
D 10.20 Design a feedback amplifier that has a closed-loop gain of 100 V/V and is relatively insensitive to change in basic-amplifier gain. In particular, it should provide a reduction in Af to 99 V/V for a reduction in A to one-tenth its nominal value. What is the required loop gain? What nomi-nal value of A is required? What value of β should be used?
What would the closed-loop gain become if A were increased tenfold? If A were made infinite?
D 10.21 A feedback amplifier is to be designed using a feedback loop connected around a two-stage amplifier. The first stage is a direct-coupled, small-signal amplifier with a high upper 3-dB frequency. The second stage is a power-output stage with a midband gain of 10 V/V and upper and lower 3-dB frequencies of 8 kHz and 80 Hz, respectively.
The feedback amplifier should have a midband gain of 100 V/V and an upper 3-dB frequency of 40 kHz. What is the required gain of the small-signal amplifier? What value of β should be used? What does the lower 3-dB frequency of the overall amplifier become?
10.22 The complementary BJT follower shown in Fig. P10.22(a) has the approximate transfer characteristic fL 100 = Af 10 = fLf Figure P10.22 V vO vI V (a) vO 1 1 0.7 0.7 vI 0 1 1 (b) Problems 893 CHAPTER 10 PR OBLEM S shown in Fig. P10.22(b). Observe that for −0.7 V ≤ vI ≤ +0.7 V, the output is zero. This “dead band” leads to crossover distortion (see Section 11.3). Consider this follower to be driven by the output of a differential amplifier of gain 100 whose positive-input terminal is connected to the input sig-nal source vS and whose negative-input terminal is con-nected to the emitters of the follower. Sketch the transfer characteristic vO versus vS of the resulting feedback ampli-fier. What are the limits of the dead band, and what are the gains outside the dead band?
D 10.23 A particular amplifier has a nonlinear transfer characteristic that can be approximated as follows: (a) For small input signals, (b) For intermediate input signals, 10 mV ≤ (c) For large input signals, the output saturates If the amplifier is connected in a negative-feedback loop, find the feedback factor β that reduces the factor-of-10 change in gain (occurring at ) to only a 10% change. What is the transfer characteristic vO versus vS of the amplifier with feedback?
Section 10.3: The Four Basic Feedback Topologies D 10.24 For the feedback voltage amplifier of Fig. 10.7(a) let the op amp have an infinite input resistance, a zero output resistance, and a finite open-loop gain V/V. If k , find the value of that results in a closed-loop gain of 100 V/V. What does the gain become if is removed?
10.25 Consider the feedback voltage amplifier of Fig.
10.7(c). Neglect and assume that .
(a) Find expressions for A and and hence the amount of feedback.
(b) Noting that the feedback can be eliminated by removing and and connecting the gate of Q to a constant dc voltage (signal ground) give the input resistance and the output resistance of the open-loop amplifier.
(c) Using standard circuit analysis (i.e, without invoking the feedback approach), find the input resistance and the output resistance of the circuit in Fig. 10.7(b). How does relate to , and to ?
10.26 The feedback current amplifier in Fig. P10.26 uti-lizes an op amp with an input differential resistance , an open-loop gain , and an output resistance The output current that is delivered to the load resistance is sensed by the feedback network composed of the two resis-tances and , and a fraction is fed back to the amplifier input node. Find expressions for , , and , assuming that the feedback causes the voltage at the input node to be near ground. If the loop gain is large, what does the closed-loop current gain become? State precisely the condition under which this is obtained. For V/V, , , k , , and k , find A, , and .
10.27 Figure P10.27 shows a feedback transconductance amplifier utilizing an op amp with open-loop gain , very large input resistance, and a very small output resistance, and an NMOS transistor Q. The amplifier delivers its output current to . The feedback network, composed of resistor R, senses the equal current in the source terminal of Q and delivers a proportional voltage to the negative input ter-minal of the op amp.
(a) Show that the feedback is negative.
(b) Open the feedback loop by breaking the connection of R to the negative input of the op amp and grounding the nega-tive input terminal. Find an expression for .
vI 10 mV, ≤ vO vI ⁄ =10 3 vI 60 mV, ≤ ΔvO ΔvI ⁄ =10 2 vI 60 mV, ≥ vI = 10 mV A 104 = R1 1 = Ω R2 R1 ro R1 R2 + ( ) RD β R1 R2 Ri Ro Rif Rof Rif Ri Rof Ro Rid μ ro.
Io RL RM RF If A Io Ii ⁄ ≡ β If Io ⁄ ≡ Af Io Is ⁄ ≡ μ 104 = Rid 1 MΩ = ro 100 Ω = RL 10 = Ω RM 100 Ω = RF 10 = Ω β Af RF RL If Io Ii Is RM Figure P10.26 μ RL Vf Vs RL R m Vi Vf Q Io Figure P10.27 A Io Vi ⁄ ≡ CHAPTER 10 PR OBLE MS 894 Chapter 10 Feedback (c) Find an expression for .
(d) Find an expression for .
(e) What is the condition to obtain ?
10.28 Figure P10.28 shows a feedback transconductance amplifier implemented using an op amp with open-loop gain , a very large input resistance, and an output resistance The output current that is delivered to the load resistance is sensed by the feedback network composed of the three resistances , , and , and a proportional voltage is fed back to the negative-input terminal of the op amp. Find expressions for and If the loop gain is large, find an approximate expression for and state precisely the condition for which this applies.
10.29 For the feedback transresistance amplifier in Fig.
10.11(d), use small-signal analysis to find the open-loop gain , the feedback factor , and the closed-loop gain . Neglect of each of and and assume that and , and that the feedback causes the signal voltage at the input node to be nearly zero. Evaluate for the following compo-nent values: , k , and k .
10.30 For the feedback transresistance amplifier in Fig.
P10.30, let and , and assume that the feedback causes the signal voltage at the input node to be nearly zero. Derive expressions for , , and . Find the value of for the case of k , k , and the transistor current gain Section 10.4: The Feedback Voltage Amplifier (Series–Shunt) 10.31 A series−shunt feedback amplifier employs a basic amplifier with input and output resistances each of 2 kΩ and gain A = 1000 V/V. The feedback factor β = 0.1 V/V. Find the gain Af, the input resistance Rif, and the output resistance Rof of the closed-loop amplifier.
10.32 For a particular amplifier connected in a feedback loop in which the output voltage is sampled, measurement of the output resistance before and after the loop is con-nected shows a change by a factor of 100. Is the resistance with feedback higher or lower? What is the value of the loop gain Aβ? If Rof is 100 Ω, what is Ro without feedback?
10.33 The formulas for and in Eqs. (10.19) and (10.22), respectively, also apply for the case in which A is a function of frequency. In this case, the resulting impedances and will be functions of frequency. Consider the case of a series–shunt amplifier that has an input resistance , an output resistance , and open-loop gain , and a feedback factor that is independent of frequency. Find and and give an equivalent circuit for each, together with the values of all the elements in the equivalent circuits.
10.34 A series−shunt feedback amplifier utilizes the feed-back circuit shown in Fig. P10.34.
(a) Find expressions for the h parameters of the feedback circuit (see Fig. 10.14b).
(b) If R1 = 1 kΩ and β = 0.01, what are the values of all four h parameters? Give the units of each parameter.
(c) For the case Rs = 1 kΩ and RL = 1 kΩ, sketch and label an equivalent circuit following the model in Fig. 10.14(c).
β Vf Io ⁄ ≡ Af Io Vs ⁄ ≡ Io Vs R ⁄ μ ro.
Io RL RM R1 R2 Vf A Io V, ⁄ ≡ β Vf Io, ⁄ ≡ Af Io Vs ⁄ .
≡ Af R2 R1 Vi Vf Io RM RL Vs Figure P10.28 A Vo Ii ⁄ ≡ β If Vo ⁄ ≡ Af Vo Is ⁄ ≡ ro Q1 Q2 RC β2RE RE RF Vo Is ⁄ β1 β2 100 = = RC RE 10 = = Ω RF 100 = Ω RF RC ro RC A Vo Ii ⁄ ≡ β If Vo ⁄ ≡ Af Vo Is ⁄ ≡ Af RC 10 = Ω RF 100 = Ω β 100.
= If Ii Is RC RF VCC Vo Q1 Figure P10.30 Rif Rof Zif Zof Ri Ro A A0 1 s ω H ⁄ ( ) + ( ) ⁄ = β Zif Zof Figure P10.34 Problems 895 CHAPTER 10 PR OBLEM S 10.35 A feedback amplifier utilizing voltage sampling and employing a basic voltage amplifier with a gain of 1000 V/V and an input resistance of 1000 Ω has a closed-loop input resistance of 10 kΩ. What is the closed-loop gain? If the basic amplifier is used to implement a unity-gain voltage buffer, what input resistance do you expect?
10.36 In the series–shunt feedback amplifier shown in Fig. P10.36, the transistors are biased with ideal current-sources mA and mA, the devices operate with V and have The input signal has a zero dc component. Resistances , k , k , and k .
(a) If the loop gain is large, what do you expect the closed-loop gain to be? Give both an expression and its approximate value.
(b) Find the dc emitter current in each of and . Also find the dc voltage at the emitter of .
(c) Sketch the A circuit without the dc sources. Derive expressions for A, , and , and find their values.
(d) Give an expression for and find its value.
(e) Find the closed-loop gain , the input resistance , and the output resistance By what percentage does the value of differ from the approximate value found in (a)?
D 10.37 Figure P10.37 shows a series−shunt ampli-fier with a feedback factor β = 1. The amplifier is designed so that vO = 0 for vS = 0, with small deviations in vO from 0 V dc being minimized by the negative-feedback action. The technology utilized has , and V/μm.
(a) Show that the feedback is negative.
(b) With the feedback loop opened at the gate of Q2, and the gate terminals of Q1 and Q2 grounded, find the dc current and the overdrive voltage at which each of Q1 to Q5 is operating.
Ignore the Early effect. Also find the dc voltage at the output.
(c) Find gm and ro of each of the five transistors.
(d) Find the expressions and values of A and Ro. Assume that the bias current sources are ideal.
(e) Find the gain with feedback, Af , and the output resis-tance Rout.
(f) How would you modify the circuit to realize a closed loop voltage gain of 5 V/V? What is the value of output resistance obtained?
D 10.38 Figure P10.38 shows a series–shunt amplifier in which the three MOSFETs are sized to operate at V. Let V and V. The current sources utilize single transistors and thus have out-put resistances equal to (a) Show that the feedback is negative.
(b) Assuming the loop gain to be large, what do you expect the closed-loop voltage gain to be approximately?
(c) If has a zero dc component, find the dc voltages at nodes S1, G2, S3, and G3. Verify that each of the current sources has the minimum required dc voltage across it for proper operation.
(d) Find the A circuit. Calculate the gain of each of the three stages and the overall voltage gain, A. [Hint: A CS amplifier with a resistance in the source lead has an effective transconductance and an output resistance ] (e) Find .
(f) Find . By what percentage does this value differ from the approximate value obtained in (b)?
(g) Find the output resistance D 10.39 The active-loaded differential amplifier in Fig. P10.39 has a feedback network consisting of the volt-age divider , with M . The devices are sized to operate at V. For all devices, V. The input signal source has a zero dc component.
I1 0.1 = I2 1 = VBE 0.7 = β1 β2 100.
= = Vs Rs 100 Ω = R1 1 = Ω R2 10 = Ω RL 1 = Ω Vo Vs ⁄ Q1 Q2 Q2 Ri Ro β Vo Vs ⁄ Rin Rout.
Af Rin Rout Vs Rs R1 I2 I1 RL Vo Q2 Q1 R2 Figure P10.36 k′ n = 2kp ′ = 120 μA/V 2 Vt = 0.7 V, V′ A = 24 VOV 0.2 = Vt 0.5 = VA 10 = ro.
Vo Vs ⁄ Vs Rs gm 1 gmRs + ( ) ⁄ ro 1 gmRs + ( ).
β Af Vo Vs ⁄ = Rout.
R1, R2 ( ) R1 R2 1 = + Ω VOV 0.2 = VA 10 = CHAPTER 10 PR OBLE MS 896 Chapter 10 Feedback .
(a) Show that the feedback is negative.
(b) What do you expect the dc voltage at the gate of to be? At the output? (Neglect the Early effect.) (c) Find the A circuit. Derive an expression for A and find its value.
(d) Select values for and to obtain a closed-loop voltage gain V/V.
(e) Find the value of (f) Utilizing the open-circuit, closed-loop gain (5 V/V) and the value of found in (e), find the value of gain obtained when a resistance k is connected to the output.
(g) As an alternative approach to (f) above, redo the analysis of the A circuit including . Then utilize the values of and found in (d) to determine and . Compare the value of to that found in (f).
Q3 Q1 Q2 Q5 vO vS 200 A (201) (401) (201) Q4 (1201) 300 A 2.5 V 2.5 V (201) Rout 0.8 mA Figure P10.37 Rout Vs VDC 0.9 V I3 0.1 mA I2 0.1 mA 2 k 18 k R1 R2 VDD 1.8 V Vo I1 0.1 mA Q1 Q2 G2 S1 S3 G3 Q3 Figure P10.38 Q2 R1 R2 Vo Vs ⁄ 5 = Rout.
Rout RL 10 = Ω RL R1 R2 β Af Af Problems 897 CHAPTER 10 PR OBLEM S D 10.40 The CMOS op amp in Fig. P10.40(a) is fabri-cated in a 1-μm technology for which V, μA/V2, and V/μm. All transistors in the circuit have L = 1 μm.
(a) It is required to perform a dc bias design of the circuit.
For this purpose, let the two input terminals be at zero volts dc and neglect channel-length modulation (i.e, let ).
Design to obtain μA, μA, and , and operate all transistors except for the source follower at V. Assume that and are perfectly matched, and similarly for and . For each transistor, find and .
(b) What is the allowable range of input common-mode voltage?
(c) Find for each of , , and (d) For each transistor, calculate Rs Q3 Q4 Q1 Q2 VDD Rout Vo R1 R2 Vs 200 A Figure P10.39 In In Q3 Q4 Q1 Q2 VDD 2.5 V VSS 2.5 V Q5 Q7 Q6 80 k (a) Q8 Out In R1 R2 100 k (b) Out Figure P10.40 Vtn Vtp 0.75 = – = μnCox 2μpCox 100 = = V ′ A 10 = VA ∞ = ID1 ID2 50 = = ID5 250 = VO 0 = Q5 VOV 0.25 = Q1 Q2 Q3 Q4 ID W L ⁄ gm Q1 Q2 Q5.
ro.
CHAPTER 10 PR OBLE MS 898 Chapter 10 Feedback (e) The 100-k potentiometer shown in Fig. 10.40(b) is con-nected between the output terminal (Out) and the inverting input terminal (–In) to provide negative feedback whose amount is controlled by the setting of the wiper. A voltage signal is applied between the noninverting input (+In) and ground. A load resistance k is connected between the output terminal and ground. The potentiometer is adjusted to obtain a closed-loop gain V/V.
Specify the required setting of the potentiometer by giv-ing the values of and . Toward this end, find the A circuit (supply a circuit diagram), the value of A, the cir-cuit (supply a circuit diagram), and the value of . (f) What is the output resistance of the feedback amplifier, excluding ?
D 10.41 Figure P10.41 shows a series−shunt feedback amplifier without details of the bias circuit.
(a) Sketch the A circuit and the circuit for determining β.
(b) Show that if Aβ is large then the closed-loop voltage gain is given approximately by (c) If RE is selected equal to 50 Ω, find RF that will result in a closed-loop gain of approximately 25 V/V.
(d) If Q1 is biased at 1 mA, Q2 at 2 mA, and Q3 at 5 mA, and assuming that the transistors have hfe = 100, find approxi-mate values for RC1 and RC2 to obtain gains from the stages of the A circuit as follows: a voltage gain of Q1 of about −10 and a voltage gain of Q2 of about −50.
(e) For your design, what is the closed-loop voltage gain realized?
(f ) Calculate the input and output resistances of the closed-loop amplifier designed.
10.42 Figure P10.42 shows a three-stage feedback ampli-fier: has an 82-k differential input resistance, a 20-V/V open-circuit differential voltage gain, and a 3.2-k output resistance. has a 5-k input resistance, a 20-mA/V short-circuit transconductance, and a 20-k output resistance. has a 20-k input resistance, unity open-circuit voltage gain, and a 1-k output resistance.
The feedback amplifier feeds a 1-k load resistance and is fed by a signal source with a 9-k resistance. The feedback network has k and k .
(a) Show that the feedback is negative.
(b) Supply the small-signal equivalent circuit.
(c) Sketch the A circuit and determine A.
(d) Find and the amount of feedback.
(e) Find the closed-loop gain .
(f) Find the feedback amplifier’s input resistance (g) Find the feedback amplifier’s output resistance (h) If the high-frequency response of the open-loop gain A is dominated by a pole at 100 Hz, what is the upper 3-dB fre-quency of the closed-loop gain?
Ω Vs RL 100 = Ω Af Vo Vs ⁄ 10 ≡ R1 R2 β β RL VCC RC1 Q1 Q3 RE RC2 Q2 Vo Vs RF Figure P10.41 Af Vo Vs ----- RF RE + RE ------------------≡ Vs Rs Vo Rin Rout R2 A1 A2 A3 RL R1 Figure P10.42 A1 Ω Ω A2 Ω Ω A3 Ω Ω Ω Ω R1 10 = Ω R2 90 = Ω β Af Vo Vs ⁄ ≡ Rin.
Rout.
Problems 899 CHAPTER 10 PR OBLEM S (i) If for some reason drops to half its nominal value, what is the percentage change to ?
Section 10.5: The Feedback Transconductance Amplifier (Series–Series) 10.43 A series−series feedback amplifier employs a transconductance amplifier having a short-circuit transcon-ductance Gm of 0.5 A/V, input resistance of 10 kΩ, and out-put resistance of 100 kΩ. The feedback network has β = 100 Ω, an input resistance (with port 1 open-circuited) of 100 Ω, and an input resistance (with port 2 open-circuited) of 10 kΩ. The amplifier operates with a signal source having a resistance of 10 kΩ and with a load resistance of 10 kΩ.
Find Af , Rin, and Rout.
10.44 Reconsider the circuit in Fig. 10.23(a), analyzed in Example 10.6, this time with the output voltage taken at the emitter of . In this case the feedback can be considered to be of the series–shunt type. Note that should now be considered part of the basic amplifier and not of the feed-back network.
(a) Determine .
(b) Find an approximate value for assuming that the loop gain remains large (a safe assumption, since the loop in fact does not change).
[Note: If you continue with the feedback analysis, you’ll find that in fact changes somewhat; this is a result of the different approximations made in the feedback analysis approach.] D 10.45 Figure P10.45 shows a feedback triple utilizing MOSFETs. All three MOSFETs are biased and sized to operate at mA/V. You may neglect their ’s (except for the calculation of as indicated below).
(a) Considering the feedback amplifier as a transconduc-tance amplifier with output current , find the value of that results in a closed-loop transconductance of approxi-mately 100 mA/V.
(b) Sketch the A circuit and find the value of (c) Find and Compare to the value of you designed for. What is the percentage difference?
What resistance can you change to make exactly 100 mA/V, and in which direction (increase or decrease)?
(d) Assuming that k find the output resistance . Since the current sampled by the feedback network is exactly equal to the output current, you can use the feedback formula. (e) If the voltage is taken as the output, in which case the amplifier becomes series–shunt feedback, what is the value of the closed-loop voltage gain ? Assume that has the original value you selected in (a). Note that in this case should be considered part of the amplifier and not the feedback network. The feedback analysis will reveal that changes somewhat, which may be puzzling given that the feedback loop did not change. The change is due to the different approximation used.
(f) What is the closed-loop output resistance of the voltage amplifier in (e) above?
A1 Af Q3 RE2 β Af Ve3 Vs ⁄ ≡ Aβ gm 4 = ro Rout1 Vs Rout1 Rout2 Q1 Q2 RD1 Q3 10 k RD2 10 k RS1 RF 100 RS2 100 Io Vo Figure P10.45 Io RF A Io Vi ⁄ .
≡ 1 Aβ + Af Vo Is ⁄ .
≡ Af Af ro3 20 = Ω, Rout1 Vo Vo Vs ⁄ RF RS2 Aβ Rout2 CHAPTER 10 PR OBLE MS 900 Chapter 10 Feedback 10.46 Consider the circuit in Fig. P10.46 as a transconduc-tance amplifier with input and output . The transistor is specified in terms of its and (a) Sketch the small-signal equivalent circuit and convince yourself that the feedback circuit is composed of resistor . (b) Find the A circuit and the circuit.
(c) Derive expressions for A, , , , , and .
D 10.47 The transconductance amplifier in Fig. P10.47 utilizes a differential amplifier with gain and a very high input resistance. The differential amplifier drives a transistor Q characterized by its and A resistor senses the output current (a) For , find an approximate expression for the closed-loop transconductance Hence, select a value for that results in mA/V.
(b) Find the A circuit and derive an expression for A. Evalu-ate A for the case V/V, mA/V, k , and the value of you selected in (a).
(c) Give an expression for and evaluate its value and that of .
(d) Find the closed-loop gain and compare to the value you anticipated in (a) above.
(e) Find expressions and values for and .
10.48 It is required to show that the output resistance of the BJT circuit in Fig. P10.48 is given by To derive this expression, set , replace the BJT with its small-signal, hybrid-π model, apply a test voltage to the collector, and find the current drawn from and hence as Note that the bias arrangement is not shown. For the case of find the maximum possible value for Note that this theoretical maximum is obtained when is so large that the signal current in the emitter is nearly zero. In this case, with applied and , what is the current in the base, in the genera-tor, and in , all in terms of ? Show these currents on a sketch of the equivalent circuit with set to 10.49 As we found out in Example 10.6, whenever the feedback network senses the emitter current of the BJT, the feedback output resistance formula cannot predict the output resistance looking into the collector. To understand this issue more clearly, consider the feedback transconductance amplifier shown in Fig. P10.49(a). To determine the output resistance, we set and apply a test voltage to the collector, as shown in Fig. P10.49(b). Now, let be increased to the point where the feedback signal across equals the input to the positive terminal of the differential amplifier, now zero. Thus the signal current through will be zero. By replacing the BJT with its hybrid- model, show that where is the transistor . Thus for large amounts of feedback, is limited to a maximum of indepen-dent of the amount of feedback. This should be expected, since no current flows through the feedback network !
Vs Io gm ro.
RF Io Rof Vs Figure P10.46 RF β β 1 Aβ + ( ) Af Ro Rof μ gm ro.
RF Io.
Vs RF m Q Io Rof Figure P10.47 Aβ 1 Af Io Vs.
⁄ ≡ RF Af 10 μ 1000 = gm 2 = ro 20 = Ω RF Aβ 1 Aβ + Af Ro Rof Ro ro Re rπ Rb + ( ) || [ ] + = 1 gmro rπ rπ Rb + -----------------+ ⎝ ⎠ ⎛ ⎞ Vs 0 = Vx Ix Vx Ro Vx Ix ⁄ .
Rb 0, = Ro.
Re Vx Vs 0 = gmVπ ro Ix Re ∞.
Rb Re Ro Vs Figure P10.48 Vs 0 = Vx μ RF RF π Rout rπ hfe 1 + ( )ro hfero + = hfe β Rout hfero RF Problems 901 CHAPTER 10 PR OBLEM S This phenomenon does not occur in the MOSFET version of this circuit.
10.50 For the feedback transconductance amplifier of Fig.
10.10(c) derive expressions for A, , , , , and .
Evaluate and for the case of mA/V, k , k , , and k . For simplicity, neglect and take into account only when calculating output resistances.
D 10.51 For the feedback transconductance amplifier in Fig. P10.51, derive an approximate expression for the closed-loop transconductance for the case of . Hence select a value for to obtain mA/V. If Q is biased to obtain mA/V, specify the value of the gain of the differential amplifier to obtain an amount of feedback of 60 dB. If Q has k find the output resistance .
10.52 All the MOS transistors in the feedback transconductance amplifier (series–series) of Fig. P10.52 are sized to operate at V. For all transistors, V and V.
(a) If has a zero dc component, find the dc voltage at the output, at the drain of , and at the drain of .
(b) Find an approximate expression and value for for the case .
(c) Use feedback analysis to obtain a more precise value for .
(d) Find the value of .
(e) If the voltage at the source of is taken as the output, find the voltage gain using the value of obtained in (c). Also find the output resistance of this series–shunt volt-age amplifier.
Section 10.6: The Feedback Transresistance Amplifier (Shunt–Shunt) 10.53 For the transresistance amplifier analyzed in Exam-ple 10.7, use the formulas derived there to evaluate , , and when is one-tenth the value used in the example. That is, evaluate for V/V, , , , and . Com-pare to the corresponding values obtained in Example 10.7.
10.54 Use the formulas derived in Example 10.7 to solve the problem in Exercise 10.15.
10.55 The CE BJT amplifier in Fig. P10.55 employs shunt–shunt feedback: Feedback resistor senses the out-put voltage and provides a feedback current to the base node.
m Rout RF Vs (a) Figure P10.49 0 0 V m Ix Vx RF (b) β Aβ Af Ro Rof Af Rof gm1 gm2 5 = = RD 10 = Ω ro2 20 = Ω RF 100 = Ω RL 1 = Ω ro1 ro2 Af Io Vs ⁄ ≡ Aβ 1 R2 Af 100 = gm 1 = μ ro 50 = Ω, Rout Vs m Io Rout R1 100 R3 R2 Q 100 Figure P10.51 VOV 0.2 = Vt 0.4 = VA 20 = Vs Q1 Q2 Af Io Vs ⁄ ≡ Aβ 1 Af Rout Q5 Io Vs ⁄ Af Rin Rout μ μ 103 = Rid ∞ = ro 100 Ω = RF 10 kΩ = Rs RL 1 kΩ = = RF Vo CHAPTER 10 PR OBLE MS 902 Chapter 10 Feedback (a) If has a zero dc component, find the dc collector cur-rent of the BJT. Assume the transistor (b) Find the small-signal equivalent circuit of the amplifier with the signal source represented by its Norton equivalent (as we usually do when the feedback connection at the input is shunt).
(c) Find the A circuit and determine the value of A, and .
(d) Find and hence and .
(e) Find , , and and hence and (f) What voltage gain is realized? How does this value compare to the ideal value obtained if the loop gain is very large and thus the signal voltage at the base becomes almost zero (like what happens in an inverting op-amp cir-cuit). Note that this single-transistor poor-man’s op amp is not that bad!
D 10.56 The circuit in Fig. P10.56 utilizes a voltage ampli-fier with gain in a shunt–shunt feedback topology with the feedback network composed of resistor . In order to be able to use the feedback equations, you should first con-vert the signal source to its Norton representation. You will then see that all the formulas derived in Example 10.7 apply here as well. (a) If the loop gain is very large, what approximate closed-loop voltage gain is realized? If , give the value of that will result in V/V.
(b) If the amplifier has a dc gain of V/V, an input resistance , and an output resistance , find the actual realized. Also find and (indicated on the circuit diagram). You may use formulas derived in Example 10.7.
(c) If the amplifier has an upper 3-dB frequency of 1 kHz and a uniform -dB/decade gain rolloff, what is the 3-dB frequency of the gain ?
Rout Figure P10.52 Rs 10 k Rf 47 k RC 4.7 k 12 V Vo Vs Rout Rin Figure P10.55 Vs β 100.
= Ri Ro β Aβ 1 Aβ + Af Rif Rof Rin Rout.
Vo Vs ⁄ μ RF m Vs Vo Rout Rin Rs RF Figure P10.56 Vo Vs ⁄ Rs 1 kΩ = RF Vo Vs ⁄ 10 – μ 103 Rid 100 kΩ = ro 1 kΩ = Vo Vs ⁄ Rin Rout μ 20 – Vo Vs ⁄ Problems 903 CHAPTER 10 PR OBLEM S 10.57 The feedback transresistance amplifier in Fig. P10.57 utilizes two identical MOSFETs biased by ideal current sources I = 0.5 mA. The MOSFETs are sized to operate at V and have V and V. The feedback resistance .
(a) If has a zero dc component, find the dc voltage at the input, at the drain of , and at the output.
(b) Find and of and . (c) Provide the A circuit and derive an expression for A in terms of , , , , and (d) What is ? Give an expression for the loop gain and the amount of feedback (e) Derive an expression for .
(f) Derive expressions for , , , and (g) Evaluate , , , , , , , and for the component values given.
10.58 Analyze the circuit in Fig. E10.15 from first princi-ples (i.e., do not use the feedback approach) and hence show that Comparing this expression to the one given in Exercise 10.15, part (b), you will note that the only difference is that has been replaced by . Note that represents the forward transmission in the feedback net-work, which the feedback-analysis method neglects. What is the condition then for the feedback-analysis method to be reasonably accurate for this circuit?
10.59 For the shunt–shunt feedback amplifier of Fig.
10.11(c), derive expressions for , , , , , , , and in terms of , , , , and .
Neglect and . Present your expressions in a format that makes them easy to interpret (e.g., like those derived in Example 10.7 or those asked for in Exercise 10.15).
10.60 For the feedback transresistance amplifier in Fig.
10.11(d) let V, . The transistors have V and .
(a) If has a zero dc component, show that and are operating at dc collector currents of approximately 0.35 mA and 0.58 mA, respectively. What is the dc voltage at the out-put?
(b) Find the A circuit and the value of A, , and (c) Find the value of , the loop gain, and the amount of feedback.
(d) Find , the input resistance , and the out-put resistance .
D 10.61 (a) Show that for the circuit in Fig. P10.61(a), if the loop gain is large, the voltage gain is given approximately by (b) Using three cascaded stages of the type shown in Fig. P10.61(b) to implement the amplifier μ, design a feedback amplifier with a voltage gain of approximately −100 V/V. The amplifier is to operate between a source resistance Rs = 10 kΩ and a load resistance RL = 1 kΩ. Calculate the actual value of realized, the input resistance (excluding Rs), and the output resistance (excluding RL). Assume that the BJTs have hfe of 100. [Note: In practice, the three amplifier stages are not made identical, for stability reasons.] D 10.62 Negative feedback is to be used to modify the characteristics of a particular amplifier for various purposes.
Identify the feedback topology to be used if: (a) Input resistance is to be lowered and output resistance raised.
(b) Both input and output resistances are to be raised.
(c) Both input and output resistances are to be lowered.
Section 10.7: The Feedback Current Amplifier (Shunt–Series) 10.63 For the feedback current amplifier in Fig. 10.8(b): (a) Provide the A circuit and derive expressions for and A. Neglect of both transistors.
(b) Provide the circuit and an expression for (c) Find an expression for VOV 0.2 = Vt 0.5 = VA 10 = RF 10 kΩ = Is Q1 gm ro Q1 Q2 gm1 ro1 gm2 ro2 RF.
β Aβ 1 Aβ + ( ).
Af Ri Rin Ro Rout.
A β Aβ Af Ri Ro Rin Rout Vo Is VDD RF I I Rout Rin Q2 Q1 Figure P10.57 Af Vo Is ----- Rs Rf || ( ) gm 1 Rf -----– ⎝ ⎠ ⎛ ⎞ro Rf || ( ) 1 Rs Rf || ( ) gm 1 Rf -----– ⎝ ⎠ ⎛ ⎞ro Rf || ( ) Rf ⁄ + ------------------------------------------------------------------------------------– = ≡ gm gm 1 Rf ⁄ – ( ) 1 Rf ⁄ – A β Aβ Af Ri Rif Ro Rof gm1 gm2 RD1 RD2 RF ro1 ro2 VCC VEE 5 = – = RC RE RF = = = 10 kΩ VBE 0.7 = β 100 = Is Q1 Q2 Ri Ro.
β Af Vo Is ⁄ ≡ Rif Rof V o V s ⁄ Vo Vs ----- Rf Rs -----– V o V s ⁄ Ri ro β β.
Aβ.
CHAPTER 10 PR OBLE MS 904 Chapter 10 Feedback (d) For gm1 = gm2 = 5 mA/V, RD = 20 kΩ, RM = 10 kΩ, and RF = 90 kΩ, find the values of A, , , , , and .
(e) If and , find the output resis-tance as seen by .
D 10.64 Design the feedback current amplifier of Fig.
10.31(a) to meet the following specifications: (i) A/A (ii) amount of feedback dB (iii) Specify the values of , and . Assume that the ampli-fier has infinite input resistance and that . First obtain an approximate value of utilizing the approximate formulas derived in Example 10.8. Then with the knowl-edge that for the MOSFET, mA/V and , modify the value of to meet the design specifications. What is obtained? 10.65 The feedback current amplifier in Fig. P10.65 uti-lizes two identical NMOS transistors sized so that at mA they operate at V. Both devices have V and V.
(a) If has zero dc component, show that both and are operating at mA. What is the dc voltage at the input?
(b) Find and for each of and (c) Find the A circuit and the value of , A, and (d) Find the value of (e) Find and .
(f) Find and 10.66 The feedback current amplifier in Fig. P10.66(a) can be thought of as a “super” CG transistor. Note that rather than connecting the gate of to signal ground, an ampli-fier is placed between source and gate.
(a) If is very large, what is the signal voltage at the input terminal? What is the input resistance? What is the current gain ? (b) For finite but assuming that the input resistance of the amplifier is very large, find the A circuit and derive expressions for A, , and (c) What is the value of ?
(d) Find and . If is large, what is the value of ?
(e) Find and assuming the loop gain is large.
(f) The “super” CG transistor can be utilized in the cascode configuration shown in Fig. P10.66(b), where VG is a dc bias voltage. Replacing by its small-signal model, use the analogy of the resulting circuit to that in Fig. P10.66(a) to find and 10.67 Figure P10.67 shows an interesting and very useful application of feedback to improve the performance of the current mirror formed by and Rather than connect-ing the drain of to the gate, as is the case in simple cur-rent mirrors, an amplifier of gain +μ is connected between the drain and the gate. Note that the feedback loop does not include transistor The feedback loop ensures that the (a) Rf RL Voltage amplifier Vs Rs Vo (b) 7.5 k 10 k 15 V 15 k 4.7 k Figure P10.61 β Aβ Af Ri Rif ro2 20 kΩ = RL 1 kΩ = RL Af Io Is 100 – = ⁄ ≡ 40 Rin 1 kΩ R1 R2 μ μ Rs ∞ = μ gm 5 = ro 20 kΩ = μ Rout ID 0.2 = VOV 0.2 = Vt 0.5 = VA 10 = Q1 Q2 Is Io R2 14 k R1 3.5 k Rout I 0.2 m Rin Figure P10.65 Is Q1 Q2 ID 0.2 = gm ro Q1 Q2.
Ri Ro.
β.
Aβ Af Rin Rout.
Q2 μ Io Is ⁄ μ μ Ri Ro.
β Aβ Af μ Af Rin Rout Q1 Io Rout.
Q1 Q2.
Q1 Q2.
Problems 905 CHAPTER 10 PR OBLEM S value of the gate-to-source voltage of is such that equals This regulated is also applied to Thus, if W/L of is n times W/L of , This current tracking, however, is not regulated by the feedback loop.
(a) Show that the feedback is negative.
(b) If is very large and the input resistance of the ampli-fier is infinite, what dc voltage appears at the drain of ? If is to operate at an overdrive voltage of 0.2 V, what is the minimum value that must have?
(c) Replacing by its small-signal model, find an expres-sion for the small-signal input resistance assuming finite gain but infinite input resistance for the amplifier .
Note that here it is much easier to do the analysis directly than to use the feedback-analysis approach.
(d) What is the output resistance ?
10.68 The circuit in Fig. P10.68 is an implementation of a particular circuit building block known as second-generation current convoyer (CCII). It has three terminals besides ground: x, y, and z. The heart of the circuit is the feedback amplifier consisting of the differential amplifier and the complementary source follower ( , ). (Note that this feedback circuit is one we have encountered a num-ber of times in this chapter, albeit with only one source fol-lower transistor.) In the following, assume that the differential amplifier has a very large gain and infinite differential input resistance. Also, let the two current mirrors have unity current-transfer ratios.
(a) If a resistance R is connected between y and ground, a voltage signal is connected between x and ground, and z is short-circuited to ground. Find the current through the Is Rs m Q2 Io Rout Rin (a) Q2 Q1 Io VG Vi Rout (b) Figure P10.66 Q1 Io1 Is.
Vgs Q2.
Q2 Q1 Io2 nIo1 nIs.
= = Q1 Q2 Io1 Io2 VBIAS Rin Rout m Is Figure P10.67 μ μ Q1 Q1 VBIAS Q1 Rin μ Rout μ QN QP μ QN QP z y x m Q3 Q4 Q1 Q2 Figure P10.68 Vx Iz CHAPTER 10 PR OBLE MS 906 Chapter 10 Feedback short circuit. Show how this current is developed and its path for positive and for negative. (b) If x is connected to ground, a current source is con-nected to input terminal y, and z is connected to ground, what voltage appears at y and what is the input resistance seen by ? What is the current that flows through the output short circuit? Also, explain the current flow through the circuit for positive and for negative.
(c) What is the output resistance at z?
10.69 For the amplifier circuit in Fig. P10.69, assuming that Vs has a zero dc component, find the dc volt-ages at all nodes and the dc emitter currents of Q1 and Q2.
Let the BJTs have β = 100. Use feedback analysis to find and Rin. Let VBE = 0.7V.
10.70 The feedback amplifier of Fig. P10.70 consists of a common-gate amplifier formed by Q1 and RD, and a feed-back circuit formed by the capacitive divider (C1, C2) and the common-source transistor Qf. Note that the bias circuit for Qf is not shown. It is required to derive expressions for Rin, and Rout. Assume that C1 and C2 are suffi-ciently small that their loading effect on the basic amplifier can be neglected. Also neglect ro. Find the values of Af, Rin, and Rout for the case in which gm1 = 5 mA/V, RD = 10 kΩ, C1 = 0.9 pF, C2 = 0.1 pF, and gmf = 1 mA/V.
10.71 Figure P10.71 shows a feedback amplifier utilizing the shunt–series topology. All transistors have and V. Neglect except in (f).
(a) Perform a dc analysis to find the dc emitter currents in and and hence determine their small-signal parameters.
(b) Replacing the BJTs with their hybrid- models, give the equivalent circuit of the feedback amplifier.
(c) Give the A circuit and determine A, , and Note that is the resistance determined by breaking the emitter loop of and measuring the resistance between the termi-nals thus created.
(d) Find the circuit and determine the value of .
(e) Find , , , , and . Note that rep-resents the resistance that in effect appears in the emitter of as a result of the feedback.
(f) Determine and To determine use V and recall that the maximum possible output resistance looking into the collector of a BJT is approximately where is the BJT’s (see Problem 10.49).
Section 10.9: Determining the Loop Gain 10.72 Derive an expression for the loop gain of the feedback amplifier in Fig. 10.22 (a) (Example 10.5). Set , break the loop at the gate of , apply a test voltage to the gate of , and determine the voltage that appears at the output of amplifier . Put your expression in the form in Eq. (10.36) and indicate the difference.
10.73 It is required to determine the loop gain of the amplifier circuit shown in Fig. P10.41. The most convenient place to break the loop is at the base of Q2. Thus, connect a resistance equal to rπ2 between the collector of Q1 and ground, apply a test voltage Vt to the base of Q2, and deter-mine the returned voltage at the collector of Q1 (with Vs set to zero, of course). Show that Vx Vx Iy Iy Iz Iy Iy V o V s ⁄ 15 Vo Rin Figure P10.69 Af Vo Is ⁄ , ≡ β 100 = VBE 0.7 = ro Q1 Q2 C2 C1 Q1 Qf Is RD Vo VBIAS VDD Rout Rin Figure P10.70 π Ri Ro.
Ro Q2 β β Aβ 1 Aβ + Af Rif Rof Rof Q2 Iout Iin, ⁄ Rin, Rout.
Rout, VA2 75 = βro, β β Aβ Vs 0 = Q2 Vt Q2 Vr A1 Problems 907 CHAPTER 10 PR OBLEM S 10.74 Show that the loop gain of the amplifier circuit in Fig. P10.52 is where gm1,2 is the gm of each of Q1 and Q2.
10.75 Derive an expression for the loop gain of the feed-back circuit shown in Fig. P10.26. Assume that the op amp is modeled by an input resistance Rid, an open-circuit voltage gain μ, and an output resistance ro.
10.76 Find the loop gain of the feedback amplifier shown in Fig. P10.37 by breaking the loop at the gate of Q2 (and, of course, setting vS = 0). Use the values given in the statement of Problem 10.37. Determine the value of Rout.
10.77 Derive an expression for the loop gain of the feed-back amplifier shown in Fig. 10.27(a) (Example 10.7). Eval-uate for the component values given in Example 10.7 and compare to the value determined there.
10.78 Derive an expression for the loop gain of the feed-back amplifier in Fig. 10.31(a) (Example 10.8). Evaluate for the component values given in Example 10.8 and compare to the result found there.
10.79 For the feedback amplifier in Fig. P10.70, set Is = 0 and derive an expression for the loop gain by breaking the loop at the gate terminal of transistor Qf. Refer to Problem 10.70 for more details.
Section 10.10: The Stability Problem 10.80 An op amp designed to have a low-frequency gain of 105 and a high-frequency response dominated by a single pole at 100 rad/s, acquires, through a manufacturing error, a pair of additional poles at 10,000 rad/s. At what frequency does the total phase shift reach 180°? At this frequency, for what value of β, assumed to be frequency independent, does the loop gain reach a value of unity? What is the corre-sponding value of closed-loop gain at low frequencies?
10.81 For the situation described in Problem 10.80, sketch Nyquist plots for β = 1.0 and 10−3. (Plot for ω = 0 rad/s, 100 rad/s, 103 rad/s, 104 rad/s, and ∞ rad/s.) 10.82 An op amp having a low-frequency gain of 103 and a single-pole rolloff at 104 rad/s is connected in a negative-feedback loop via a feedback network having a transmission k and a two-pole rolloff at 104 rad/s. Find the value of k above which the closed-loop amplifier becomes unstable.
10.83 Consider a feedback amplifier for which the open-loop gain A(s) is given by If the feedback factor β is independent of frequency, find the frequency at which the phase shift is 180°, and find the criti-cal value of β at which oscillation will commence.
Section 10.11: Effect of Feedback on the Amplifier Poles 10.84 A dc amplifier having a single-pole response with pole frequency 10 Hz and unity-gain frequency of 1 MHz is operated in a loop whose frequency-independent feedback factor is 0.01. Find the low-frequency gain, the 3-dB Vs 15 k 10 k 100 k 8 k RC1 10 k 870 12 V Q2 10 k Q1 3.4 k Rf 1 k Iin Rs Rin RB1 RB2 RC2 RL Rout RE2 Iout Figure P10.71 Aβ gm2RC2 hfe3 1 + ( ) RC2 hfe3 1 + ( ) re3 RF RE || re1 ( ) + + [ ] + -------------------------------------------------------------------------------------------- = × α1RE RE re1 + ------------------- RC1 || rπ 2 ( ) Aβ gm1,2 ro2 || ro4 ( ) RF || ro5 RF || ro5 ( ) 1 gm5 ⁄ + ---------------------------------------------= Aβ Aβ A s ( ) 1000 1 s 10 4 ⁄ + ( ) 1 s 105 ⁄ + ( ) 2 ------------------------------------------------------------= CHAPTER 10 PR OBLE MS 908 Chapter 10 Feedback frequency, and the unity-gain frequency of the closed-loop amplifier. By what factor does the pole shift?
10.85 An amplifier having a low-frequency gain of 103 and poles at 104 Hz and 105 Hz is operated in a closed nega-tive-feedback loop with a frequency-independent β.
(a) For what value of β do the closed-loop poles become coincident? At what frequency?
(b) What is the low-frequency gain corresponding to the sit-uation in (a)? What is the value of the closed-loop gain at the frequency of the coincident poles?
(c) What is the value of Q corresponding to the situation in (a)?
(d) If β is increased by a factor of 10, what are the new pole locations? What is the corresponding pole Q?
D 10.86 A dc amplifier has an open-loop gain of 1000 and two poles, a dominant one at 1 kHz and a high-frequency one whose location can be controlled. It is required to con-nect this amplifier in a negative-feedback loop that provides a dc closed-loop gain of 10 and a maximally flat response.
Find the required value of β and the frequency at which the second pole should be placed.
10.87 Reconsider Example 10.9 with the circuit in Fig.
10.40 modified to incorporate a so-called tapered network, in which the components immediately adjacent to the ampli-fier input are raised in impedance to C/10 and 10R. Find expressions for the resulting pole frequency ω0 and Q factor.
For what value of K do the poles coincide? For what value of K does the response become maximally flat? For what value of K does the circuit oscillate?
10.88 Three identical inverting amplifier stages each char-acterized by a low-frequency gain K and a single-pole response with kHz are connected in a feedback loop with . What is the minimum value of K at which the circuit oscillates? What would the frequency of oscilla-tion be?
Section 10.12: Stability Study Using Bode Plots 10.89 Reconsider Exercise 10.24 for the case of the op amp wired as a unity-gain buffer. At what frequency is What is the corresponding phase margin?
10.90 Reconsider Exercise 10.24 for the case of a manu-facturing error introducing a second pole at 104 Hz. What is now the frequency for which What is the corre-sponding phase margin? For what values of β is the phase margin 45° or more?
10.91 For what phase margin does the gain peaking have a value of 5%? Of 10%? Of 0.1 dB? Of 1 dB? [Hint: Use the result in Eq. 10.105.] 10.92 An amplifier has a dc gain of 105 and poles at 105 Hz, 3.16 × 105 Hz, and 106 Hz. Find the value of β, and the corresponding closed-loop gain, for which a phase margin of 45° is obtained.
10.93 A two-pole amplifier for which A0 = 103 and having poles at 1 MHz and 10 MHz is to be connected as a differen-tiator. On the basis of the rate-of-closure rule, what is the smallest differentiator time constant for which operation is stable? What are the corresponding gain and phase margins?
10.94 For the amplifier described by Fig. 10.43 and with frequency-independent feedback, what is the minimum closed-loop voltage gain that can be obtained for phase mar-gins of 90° and 45°?
Section 10.13: Frequency Compensation D 10.95 A multipole amplifier having a first pole at 3 MHz and a dc open-loop gain of 60 dB is to be compensated for closed-loop gains as low as unity by the introduction of a new dominant pole. At what frequency must the new pole be placed?
D 10.96 For the amplifier described in Problem 10.95, rather than introducing a new dominant pole we can use additional capacitance at the circuit node at which the pole is formed to reduce the frequency of the first pole. If the fre-quency of the second pole is 15 MHz and if it remains unchanged while additional capacitance is introduced as mentioned, find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop gains as low as unity. By what factor is the capacitance at the controlling node increased?
10.97 Contemplate the effects of pole splitting by consid-ering Eqs. (10.112), (10.116), and (10.117) under the condi-tions that R1 R2 = R, C2 C1/10 = C, Cf C, and gm = 100/ R, by calculating ωP1, ωP2, and , .
D 10.98 An op amp with open-loop voltage gain of 104 and poles at 106 Hz, 107 Hz, and 108 Hz is to be compen-sated by the addition of a fourth dominant pole to operate stably with unity feedback (β = 1). What is the frequency of the required dominant pole? The compensation network is to consist of an RC low-pass network placed in the negative-feedback path of the op amp. The dc bias conditions are such that a 1-MΩ resistor can be tolerated in series with each of the negative and positive input terminals. What capacitor is required between the negative input and ground to implement the required fourth pole?
D 10.99 An op amp with an open-loop voltage gain of 80 dB and poles at 105 Hz, 106 Hz, and 2 × 106 Hz is to be compensated to be stable for unity β. Assume that the op f3dB 100 = β 1 = Aβ = 1?
Aβ 1?
= ωP1 ′ ωP2 ′ Problems 909 CHAPTER 10 PR OBLEM S amp incorporates an amplifier equivalent to that in Fig.
10.46, with C1 = 150 pF, C2 = 5 pF, and gm = 40 mA/V, and that fP1 is caused by the input circuit and fP2 by the output circuit of this amplifier. Find the required value of the com-pensating Miller capacitance and the new frequency of the output pole.
10.100 The op amp in the circuit of Fig. P10.100 has an open-loop gain of 105 and a single-pole rolloff with ω3dB = 10 rad/s.
(a) Sketch a Bode plot for the loop gain.
(b) Find the frequency at which and find the cor-responding phase margin.
(c) Find the closed-loop transfer function, including its zero and poles. Sketch a pole-zero plot. Sketch the magnitude of the transfer function versus frequency, and label the impor-tant parameters on your sketch.
Aβ = 1, Figure P10.100 CHAPTER 11 Output Stages and Power Amplifiers Introduction 911 11.1 Classification of Output Stages 912 11.2 Class A Output Stage 913 11.3 Class B Output Stage 918 11.4 Class AB Output Stage 924 11.5 Biasing the Class AB Circuit 929 11.6 CMOS Class AB Output Stages 933 11.7 Power BJTs 943 11.8 Variations on the Class AB Configuration 950 11.9 IC Power Amplifiers 955 11.10 MOS Power Transistors 962 Summary 967 Problems 968 911 IN THIS CHAPTER YOU WILL LEARN 1. The classification of amplifier output stages on the basis of the fraction of the cycle of an input sine wave during which the transistor conducts.
2. Analysis and design of a variety of output-stage types ranging from the simple but power-inefficient emitter follower (class A) to the popular push–pull class AB circuit in both bipolar and CMOS technologies.
3. Thermal considerations in the design and fabrication of high-output-power circuits.
4. Useful and interesting circuit techniques employed in the design of power amplifiers.
5. Special types of MOS transistors optimized for high-power applications.
Introduction An important function of the output stage is to provide the amplifier with a low output resis-tance so that it can deliver the output signal to the load without loss of gain. Since the output stage is the final stage of the amplifier, it usually deals with relatively large signals. Thus the small-signal approximations and models either are not applicable or must be used with care.
Nevertheless, linearity remains a very important requirement. In fact, a measure of goodness of the output stage is the total harmonic distortion (THD) it introduces. This is the rms value of the harmonic components of the output signal, excluding the fundamental, expressed as a percentage of the rms of the fundamental. A high-fidelity audio power amplifier features a THD of the order of a fraction of a percent. The most challenging requirement in the design of an output stage is for it to deliver the required amount of power to the load in an efficient manner. This implies that the power dis-sipated in the output-stage transistors must be as low as possible. This requirement stems mainly from the fact that the power dissipated in a transistor raises its internal junction tem-perature, and there is a maximum temperature (in the range of 150°C to 200°C for silicon devices) above which the transistor is destroyed. A high power-conversion efficiency also may be required to prolong the life of batteries employed in battery-powered circuits, to permit a smaller, lower-cost power supply, or to obviate the need for cooling fans.
We begin this chapter with a study of the various output-stage configurations employed in amplifiers that handle both low and high power. In this context, “high power” generally means greater than 1 W. We then consider the specific requirements of BJTs employed in the design of high-power output stages, called power transistors. Special attention will be paid to the thermal properties of such transistors.
912 Chapter 11 Output Stages and Power Amplifiers A power amplifier is simply an amplifier with a high-power output stage. Examples of discrete- and integrated-circuit power amplifiers will be presented. Since BJTs can han-dle much larger currents than MOSFETs, they are preferred in the design of output stages.
Nevertheless, some interesting CMOS output stages are also studied.
11.1 Classification of Output Stages Output stages are classified according to the collector current waveform that results when an input signal is applied. Figure 11.1 illustrates the classification for the case of a sinusoidal input signal. The class A stage, whose associated waveform is shown in Fig. 11.1(a), is biased at a current IC greater than the amplitude of the signal current, . Thus the transistor in a class A stage conducts for the entire cycle of the input signal; that is, the conduction angle is 360°. In contrast, the class B stage, whose associated waveform is shown in Fig. 11.1(b), is biased at zero dc current. Thus a transistor in a class B stage conducts for only half the cycle of the input sine wave, resulting in a conduction angle of 180°. As will be seen later, Figure 11.1 Collector current waveforms for transistors operating in (a) class A, (b) class B, (c) class AB, and (d) class C amplifier stages.
Îc 11.2 Class A Output Stage 913 the negative halves of the sinusoid will be supplied by another transistor that also operates in the class B mode and conducts during the alternate half-cycles. An intermediate class between A and B, appropriately named class AB, involves biasing the transistor at a nonzero dc current much smaller than the peak current of the sine-wave signal. As a result, the transistor conducts for an interval slightly greater than half a cycle, as illustrated in Fig. 11.1(c). The resulting conduction angle is greater than 180° but much less than 360°. The class AB stage has another transistor that conducts for an interval slightly greater than that of the negative half-cycle, and the currents from the two transistors are combined in the load. It follows that, during the intervals near the zero crossings of the input sinusoid, both transistors conduct.
Figure 11.1(d) shows the collector-current waveform for a transistor operated as a class C amplifier. Observe that the transistor conducts for an interval shorter than that of a half-cycle; that is, the conduction angle is less than 180°. The result is the periodically pulsating current waveform shown. To obtain a sinusoidal output voltage, this current is passed through a parallel LC circuit, tuned to the frequency of the input sinusoid. The tuned circuit acts as a bandpass filter (Chapter 16) and provides an output voltage proportional to the amplitude of the fundamental component in the Fourier-series representation of the current waveform. Class A, AB, and B amplifiers are studied in this chapter. They are employed as output stages of op amps and audio power amplifiers. In the latter application, class AB is the pre-ferred choice, for reasons that will be explained in the sections to folow. Class C amplifiers are usually employed for radio-frequency (RF) power amplification (required, e.g., in mobile phones and radio and TV transmitters). The design of class C amplifiers is a rather specialized topic and is not included in this book. However, we should point out that the tuned-resonator oscillator circuits described in Chapter 17 operate inherently in the class C mode.
Although the BJT has been used to illustrate the definition of the various output-stage classes, the same classification applies to output stages implemented with MOSFETs. Further-more, the classification above extends to amplifier stages other than those used at the output.
In this regard, all the common-emitter, common-base, and common-collector amplifiers (and their FET counterparts) studied in earlier chapters fall into the class A category.
11.2 Class A Output Stage Because of its low output resistance, the emitter follower is the most popular class A output stage. We have already studied the emitter follower in Chapter 6; in the following we con-sider its large-signal operation.
11.2.1 Transfer Characteristic Figure 11.2 shows an emitter follower Q1 biased with a constant current I supplied by transistor Q2. Since the emitter current iE1 = I + iL, the bias current I must be greater than the largest negative load current; otherwise, Q1 cuts off and class A operation will no longer be maintained.
The transfer characteristic of the emitter follower of Fig. 11.2 is described by (11.1) where vBE1 depends on the emitter current iE1 and thus on the load current iL. If we neglect the relatively small changes in vBE1 (60 mV for every factor-of-10 change in emitter current), the vO = vI vBE1 – 914 Chapter 11 Output Stages and Power Amplifiers linear transfer curve shown in Fig. 11.3 results. As indicated, the positive limit of the linear region is determined by the saturation of Q1; thus (11.2) In the negative direction, depending on the values of I and RL, the limit of the linear region is determined either by Q1 turning off, (11.3) Figure 11.3 Transfer characteristic of the emitter follower in Fig. 11.2. This linear characteristic is obtained by neglecting the change in vBE1 with iL. The maximum positive output is determined by the saturation of Q1. In the negative direction, the limit of the linear region is determined either by Q1 turning off or by Q2 saturating, depending on the values of I and RL.
Figure 11.2 An emitter follower (Q1) biased with a constant current I supplied by transistor Q2.
vOmax = VCC V CE1sat – vOmin IRL – = 11.2 Class A Output Stage 915 or by Q2 saturating, (11.4) The absolutely lowest (most negative) output voltage is that given by Eq. (11.4) and is achieved provided the bias current I is greater than the magnitude of the corresponding load current, (11.5) 11.2.2 Signal Waveforms Consider the operation of the emitter-follower circuit of Fig. 11.2 for sine-wave input.
Neglecting VCEsat, we see that if the bias current I is properly selected, the output voltage can swing from −VCC to +VCC with the quiescent value being zero, as shown in Fig. 11.4(a). Figure 11.4(b) shows the corresponding waveform of vCE1 = VCC − vO. Now, assuming that the bias current I is selected to allow a maximum negative load current of , that is, the collector current of Q1 will have the waveform shown in Fig. 11.4(c). Finally, Fig.
11.4(d) shows the waveform of the instantaneous power dissipation in Q1, (11.6) 11.2.3 Power Dissipation Figure 11.4(d) indicates that the maximum instantaneous power dissipation in Q1 is VCC I. This is equal to the power dissipation in Q1 with no input signal applied, that is, the quiescent power dissipation. Thus the emitter-follower transistor dissipates the largest amount of power when vO = 0. Since this condition (no input signal) can easily prevail for prolonged periods of time, transistor Q1 must be able to withstand a continuous power dissipation of VCCI.
vOmin −V CC V CE2sat + = I −VCC V CE2sat + RL -------------------------------------≥ D11.1 For the emitter follower in Fig. 11.2, VCC = 15 V, VCEsat = 0.2 V, VBE = 0.7 V and constant, and β is very high. Find the value of R that will establish a bias current sufficiently large to allow the largest possible output signal swing for RL = 1 kΩ. Determine the resulting output signal swing and the minimum and maximum emitter currents for Q1.
Ans. 0.97 kΩ; −14.8 V to +14.8 V; 0 to 29.6 mA 11.2 For the emitter follower of Exercise 11.1, in which I = 14.8 mA, consider the case in which vO is limited to the range −10 V to +10 V. Let Q1 have vBE = 0.6 V at iC = 1 mA, and assume α 1. Find vI corresponding to vO = −10 V, 0 V, and +10 V. At each of these points, use small-signal analysis to determine the voltage gain Note that the incremental voltage gain gives the slope of the vO-versus-vI characteristic.
Ans. −9.36 V, 0.67 V, 10.68 V; 0.995 V/V, 0.998 V/V, 0.999 V/V vo vi.
⁄ EXERCISES V CC RL ⁄ I VCC RL ⁄ = pD1 vCE1iC1 ≡ 916 Chapter 11 Output Stages and Power Amplifiers The power dissipation in Q1 depends on the value of RL. Consider the extreme case of an output open circuit, that is, RL = ∞. In this case, iC1 = I is constant and the instantaneous power dissipation in Q1 will depend on the instantaneous value of vO. The maximum power dissipation will occur when vO = −VCC, for in this case vCE1 is a maximum of 2VCC and pD1 = 2VCC I. This condition, however, would not normally persist for a prolonged interval, so the design need not be that conservative. Observe that with an open-circuit load, the average power dissipation in Q1 is VCC I. A far more dangerous situation occurs at the other extreme of RL—specifically, RL = 0. In the event of an output short circuit, a pos-itive input voltage would theoretically result in an infinite load current. In practice, a very large current may flow through Q1, and if the short-circuit condition persists, the resulting large power dissipation in Q1 can raise its junction temperature beyond the specified max-imum, causing Q1 to burn up. To guard against such a situation, output stages are usually equipped with short-circuit protection, as will be explained later.
The power dissipation in Q2 also must be taken into account in designing an emitter-follower output stage. Since Q2 conducts a constant current I, and the maximum value of vCE2 is 2VCC, the maximum instantaneous power dissipation in Q2 is 2VCC I. This maximum, however, occurs when vO = VCC, a condition that would not normally prevail for a prolonged period of time. A more significant quantity for design purposes is the average power dissipa-tion in Q2, which is VCC I.
Figure 11.4 Maximum signal waveforms in the class A output stage of Fig. 11.2 under the condition or, equivalently, Note that the transistor saturation voltages have been neglected.
(d) I V CC RL ⁄ = RL V CC I.
⁄ = 11.2 Class A Output Stage 917 11.2.4 Power-Conversion Efficiency The power-conversion efficiency of an output stage is defined as (11.7) For the emitter follower of Fig. 11.2, assuming that the output voltage is a sinusoid with the peak value , the average load power will be (11.8) Since the current in Q2 is constant (I), the power drawn from the negative supply1 is VCCI.
The average current in Q1 is equal to I, and thus the average power drawn from the positive 1This does not include the power drawn by the biasing resistor R and the diode-connected transistor Q3.
Consider the emitter follower in Fig. 11.2 with V, I = 100 mA, and (a) Find the power dissipated in and under quiescent conditions (b) For a sinusoidal output voltage of maximum possible amplitude (neglecting ), find the av-erage power dissipation in and Also find the load power.
Solution (a) Under quiescent conditions , and each of and conducts a current I = 100 mA = 0.1 A and has a voltage V, thus W (b) For a sinusoidal output voltage of maximum possible amplitude (i.e., peak), the instantaneous power dissipation in will be as shown in Fig. 11.4(d). Thus the average power dissipation in will be For , the current is constant at I = 0.1 A and the voltage at the collector will have an average value of 0 V. Thus the average voltage across will be and the average dissipation will be Finally, the power delivered to the load can be found from VCC 10 = RL 100 Ω.
= Q1 Q2 vO 0 = ( ).
VCEsat Q1 Q2.
vO 0 = Q1 Q2 VCE VCC 10 = = PD1 PD2 VCCI 10 0.1 1 = × = = = 10-V Q1 Q1 PD1 1 2 ---VCCI 1 2 ---10 0.1 0.5 = × × W = = Q2 Q2 VCC PD2 I vCE × average = I VCC × 0.1 10 1 = × W = = PL Vorms 2 RL ------------= 10 2 ⁄ ( ) 2 100 ------------------------0.5W = = Example 11.1 η Load power PL ( ) Supply power PS ( ) --------------------------------------------≡ V ˆo PL (V ˆo 2) 2 ⁄ RL -----------------------1 2 ---V ˆ o 2 RL -------= = 918 Chapter 11 Output Stages and Power Amplifiers supply is VCCI. Thus the total average supply power is (11.9) Equations (11.8) and (11.9) can be combined to yield (11.10) Since and , maximum efficiency is obtained when (11.11) The maximum efficiency attainable is 25%. Because this is a rather low figure, the class A output stage is rarely used in high-power applications (>1 W). Note also that in prac-tice the output voltage swing is limited to lower values to avoid transistor saturation and asso-ciated nonlinear distortion. Thus the efficiency achieved in practice is usually in the 10% to 20% range.
11.3 Class B Output Stage Figure 11.5 shows a class B output stage. It consists of a complementary pair of transistors (an npn and a pnp) connected in such a way that both cannot conduct simultaneously.
11.3.1 Circuit Operation When the input voltage vI is zero, both transistors are cut off and the output voltage vO is zero. As vI goes positive and exceeds about 0.5 V, QN conducts and operates as an emitter follower. In this case vO follows vI (i.e., vO = vI − vBEN) and QN supplies the load current.
Meanwhile, the emitter–base junction of QP will be reverse-biased by the VBE of QN, which is approximately 0.7 V. Thus QP will be cut off.
PS 2V CCI = η 1 4 ---V ˆo 2 IRLV CC -----------------= 1 4 --- V ˆo IRL --------⎝ ⎠ ⎛ ⎞V ˆo V CC ---------⎝ ⎠ ⎛ ⎞ = V ˆo V CC ≤ V ˆo IRL ≤ V ˆo = V CC = IRL 11.3 For the emitter follower of Fig. 11.2, let VCC = 10 V, I = 100 mA, and RL = 100 Ω. If the output voltage is an 8-V-peak sinusoid, find the following: (a) the power delivered to the load; (b) the average power drawn from the supplies; (c) the power-conversion efficiency. Ignore the loss in Q3 and R.
Ans. 0.32 W; 2 W; 16% EXERCISE 11.3 Class B Output Stage 919 If the input goes negative by more than about 0.5 V, QP turns on and acts as an emitter follower. Again vO follows vI (i.e., vO = vI + vEBP), but in this case QP supplies the load current and QN will be cut off.
We conclude that the transistors in the class B stage of Fig. 11.5 are biased at zero cur-rent and conduct only when the input signal is present. The circuit operates in a push–pull fashion: QN pushes (sources) current into the load when vI is positive, and QP pulls (sinks) current from the load when vI is negative.
11.3.2 Transfer Characteristic A sketch of the transfer characteristic of the class B stage is shown in Fig. 11.6. Note that there exists a range of vI centered around zero where both transistors are cut off and vO is zero. This dead band results in the crossover distortion illustrated in Fig. 11.7 for the case of an input sine wave. The effect of crossover distortion will be most pronounced when the Figure 11.6 Transfer characteristic for the class B output stage in Fig. 11.5.
Figure 11.5 A class B output stage.
920 Chapter 11 Output Stages and Power Amplifiers amplitude of the input signal is small. Crossover distortion in audio power amplifiers gives rise to unpleasant sounds.
11.3.3 Power-Conversion Efficiency To calculate the power-conversion efficiency, η, of the class B stage, we neglect the cross-over distortion and consider the case of an output sinusoid of peak amplitude The aver-age load power will be (11.12) The current drawn from each supply will consist of half-sine waves of peak amplitude .
Thus the average current drawn from each of the two power supplies will be . It follows that the average power drawn from each of the two power supplies will be the same, (11.13) and the total supply power will be (11.14) Thus the efficiency will be given by (11.15) Figure 11.7 Illustrating how the dead band in the class B transfer characteristic results in crossover distortion.
V ˆo.
PL 1 2 ---V ˆo 2 RL ------= (V ˆo RL ⁄ ) V ˆo πRL ⁄ PS+ PS− 1 π --- V ˆo RL ------V CC = = PS 2 π ---V ˆo RL ------V CC = η 1 2 --- V ˆo 2 RL -----⎝ ⎠ ⎛ ⎞ 2 π ---V ˆo RL -----VCC ⎝ ⎠ ⎛ ⎞ π 4 --- V ˆo V CC --------= = 11.3 Class B Output Stage 921 It follows that the maximum efficiency is obtained when is at its maximum. This maxi-mum is limited by the saturation of QN and QP to VCC − VCEsat VCC. At this value of peak output voltage, the power-conversion efficiency is (11.16) This value is much larger than that obtained in the class A stage (25%). Finally, we note that the maximum average power available from a class B output stage is obtained by substitut-ing in Eq. (11.12), (11.17) 11.3.4 Power Dissipation Unlike the class A stage, which dissipates maximum power under quiescent conditions (vO = 0), the quiescent power dissipation of the class B stage is zero. When an input signal is applied, the average power dissipated in the class B stage is given by (11.18) Substituting for PS from Eq. (11.14) and for PL from Eq. (11.12) results in (11.19) From symmetry we see that half of PD is dissipated in QN and the other half in QP. Thus QN and QP must be capable of safely dissipating watts. Since PD depends on , we must find the worst-case power dissipation, PDmax. Differentiating Eq. (11.19) with respect to and equat-ing the derivative to zero gives the value of that results in maximum average power dissi-pation as (11.20) Substituting this value in Eq. (11.19) gives (11.21) Thus, (11.22) At the point of maximum power dissipation, the efficiency can be evaluated by substituting for from Eq. (11.20) into Eq. (11.15); hence, .
Figure 11.8 shows a sketch of PD (Eq. 11.19) versus the peak output voltage . Curves such as this are usually given on the data sheets of IC power amplifiers. [Usually, however, PD is plotted versus PL, as rather than .] An interesting observation fol-lows from Fig. 11.8: Increasing beyond decreases the power dissipated in the V ˆo ηmax π 4 ---78.5% = = V ˆ o = V CC PLmax 1 2 --- V 2 CC RL -----------= PD PS PL – = PD 2 π --- V ˆ o RL -----V CC 1 2 --- V ˆo 2 RL -----– = 1 2 ---PD V ˆo V ˆo V ˆ o V ˆ o PDmax 2 π ---V CC = P Dmax 2V 2 CC π 2RL ---------------= P DNmax P DPmax V 2 CC π 2RL -----------= = V ˆ o η = 50% V ˆ o PL 1 2 --- V ˆo 2 RL ⁄ ( ), = V ˆo V ˆ o 2V CC π ⁄ 922 Chapter 11 Output Stages and Power Amplifiers class B stage while increasing the load power. The price paid is an increase in nonlinear dis-tortion as a result of approaching the saturation region of operation of QN and QP. Transistor saturation flattens the peaks of the output sine waveform. Unfortunately, this type of distor-tion cannot be significantly reduced by the application of negative feedback (see Section 10.2), and thus transistor saturation should be avoided in applications requiring low THD.
Figure 11.8 Power dissipation of the class B output stage versus amplitude of the output sinusoid.
It is required to design a class B output stage to deliver an average power of 20 W to an 8-Ω load. The power supply is to be selected such that VCC is about 5 V greater than the peak output voltage. This avoids transistor saturation and the associated nonlinear distortion, and allows for including short-circuit protec-tion circuitry. (The latter will be discussed in Section 11.8.) Determine the supply voltage required, the peak current drawn from each supply, the total supply power, and the power-conversion efficiency. Also determine the maximum power that each transistor must be able to dissipate safely.
Solution Since then Therefore we select VCC = 23 V.
The peak current drawn from each supply is PL 1 2 ---V ˆo 2 RL ------= V ˆ o 2PLRL = 2 20 8 × × = 17.9 V = I ˆ o V ˆ o RL ------17.9 8 ----------2.24 A = = = Example 11.2 11.3 Class B Output Stage 923 11.3.5 Reducing Crossover Distortion The crossover distortion of a class B output stage can be reduced substantially by employing a high-gain op amp and overall negative feedback, as shown in Fig. 11.9. The ±0.7-V dead band is reduced to volt, where A0 is the dc gain of the op amp. Nevertheless, the slew-rate limitation of the op amp will cause the alternate turning on and off of the output transistors to be noticeable, especially at high frequencies. A more practical method for reducing and almost eliminating crossover distortion is found in the class AB stage, which will be studied in the next section.
Figure 11.9 Class B circuit with an op amp connected in a negative-feedback loop to reduce crossover distortion.
Since each supply provides a current waveform of half-sinusoids, the average current drawn from each sup-ply will be Thus the average power drawn from each supply is for a total supply power of 32.8 W. The power-conversion efficiency is The maximum power dissipated in each transistor is given by Eq. (11.22); thus, I ˆo π ⁄ · .
PS+ PS− 1 π ---2.24 23 × × 16.4 W = = = η PL PS ------20 32.8 ----------100 × 61% = = = PDNmax PDPmax VCC 2 π2RL ------------= = 23 ( )2 π2 8 × --------------= 6.7 W = 0.7 A0 ⁄ ± 924 Chapter 11 Output Stages and Power Amplifiers 11.3.6 Single-Supply Operation The class B stage can be operated from a single power supply, in which case the load is capacitively coupled, as shown in Fig. 11.10. Note that to make the formulas derived in Section 11.3.4 directly applicable, the single power supply is denoted 2VCC.
11.4 Class AB Output Stage Crossover distortion can be virtually eliminated by biasing the complementary output transistors at a small nonzero current. The result is the class AB output stage shown in Fig. 11.11. A bias voltage VBB is applied between the bases of QN and QP. For vI = 0, vO = 0, and a voltage appears across the base–emitter junction of each of QN and QP. Assuming matched devices, (11.23) The value of VBB is selected to yield the required quiescent current IQ.
11.4.1 Circuit Operation When vI goes positive by a certain amount, the voltage at the base of QN increases by the same amount and the output becomes positive at an almost equal value, (11.24) Figure 11.10 Class B output stage operated with a single power supply.
11.4 For the class B output stage of Fig. 11.5, let VCC = 6 V and RL = 4 Ω. If the output is a sinusoid with 4.5-V peak amplitude, find (a) the output power; (b) the average power drawn from each supply; (c) the power efficiency obtained at this output voltage; (d) the peak currents supplied by vI, assuming that βN = βP = 50; (e) the maximum power that each transistor must be capable of dissipating safely.
Ans. (a) 2.53 W; (b) 2.15 W; (c) 59%; (d) 22.1 mA; (e) 0.91 W EXERCISE V BB 2 ⁄ iN iP IQ ISe V BB 2VT ⁄ = = = vO vI V BB 2 --------vBEN – + = 11.4 Class AB Output Stage 925 The positive vO causes a current iL to flow through RL, and thus iN must increase; that is, (11.25) The increase in iN will be accompanied by a corresponding increase in vBEN (above the quies-cent value of VBB/2). However, since the voltage between the two bases remains constant at VBB, the increase in vBEN will result in an equal decrease in vEBP and hence in iP. The relation-ship between iN and iP can be derived as follows: (11.26) Thus, as iN increases, iP decreases by the same ratio while the product remains constant.
Equations (11.25) and (11.26) can be combined to yield iN for a given iL as the solution to the quadratic equation (11.27) From the equations above, we can see that for positive output voltages, the load current is supplied by QN, which acts as the output emitter follower. Meanwhile, QP will be conducting a current that decreases as vO increases; for large vO the current in QP can be ignored altogether.
For negative input voltages the opposite occurs: The load current will be supplied by QP, which acts as the output emitter follower, while QN conducts a current that gets smaller as vI becomes more negative. Equation (11.26), relating iN and iP, holds for negative inputs as well.
We conclude that the class AB stage operates in much the same manner as the class B circuit, with one important exception: For small vI, both transistors conduct, and as vI is increased or decreased, one of the two transistors takes over the operation. Since the Figure 11.11 Class AB output stage. A bias voltage VBB is applied between the bases of QN and QP, giving rise to a bias current IQ given by Eq. (11.23). Thus, for small vI, both transistors conduct and crossover dis-tortion is almost completely eliminated.
iN iP iL + = vBEN vEBP + V BB = VT ln iN IS ----VT ln iP IS ----+ 2VT ln I Q IS ----= iNiP IQ 2 = iN 2 iLiN – IQ 2 – 0 = 926 Chapter 11 Output Stages and Power Amplifiers transition is a smooth one, crossover distortion will be almost totally eliminated. Figure 11.12 shows the transfer characteristic of the class AB stage.
The power relationships in the class AB stage are almost identical to those derived for the class B circuit in Section 11.3. The only difference is that under quiescent conditions the class AB circuit dissipates a power of VCCIQ per transistor. Since IQ is usually much smaller than the peak load current, the quiescent power dissipation is usually small. Nevertheless, it can be taken into account easily. Specifically, we can simply add the quiescent dissipation per transistor to its maximum power dissipation with an input signal applied, to obtain the total power dissipation that the transistor must be able to handle safely.
11.4.2 Output Resistance If we assume that the source supplying vI is ideal, then the output resistance of the class AB stage can be determined from the circuit in Fig. 11.13 as (11.28) where reN and reP are the small-signal emitter resistances of QN and QP, respectively. At a given input voltage, the currents iN and iP can be determined, and reN and reP are given by (11.29) (11.30) Thus, (11.31) Since as iN increases, iP decreases, and vice versa, the output resistance remains approxi-mately constant in the region around vI = 0. This, in effect, is the reason for the virtual Figure 11.12 Transfer characteristic of the class AB stage in Fig. 11.11.
Rout reN reP || = reN V T iN -----= reP V T iP -----= Rout V T iN ----- V T iP -----VT iP iN + --------------= = 11.4 Class AB Output Stage 927 absence of crossover distortion. At larger load currents, either iN or iP will be significant, and Rout decreases as the load current increases.
Figure 11.13 Determining the small-signal output resistance of the class AB circuit of Fig. 11.11.
In this example we explore the details of the transfer characteristic, versus , of the class AB circuit in Fig. 11.11. For this purpose let V, mA, and . Assume that and are matched and have . First, determine the required value of the bias voltage . Then, find the transfer characteristic for in the range V to V.
Solution To determine the required value of we use Eq. (11.23) with mA and . Thus, V The easiest way to determine the transfer characteristic is to work backward; that is, for a given we determine the corresponding value of . We shall outline the process for positive : 1. Assume a value for .
2. Determine the load current , 3. Use Eq. (11.27) to determine the current conducted by 4. Determine from 5. Determine from vO vI VCC 15 = IQ 2 = RL 100 Ω = QN QP IS 10 13 – A = VBB vO 10 – +10 VBB IQ 2 = IS 10 13 – A = VBB 2VT ln IQ IS ⁄ ( ) = 2 0.025 ln 2 10 3 – 10 13 – ⁄ × ( ) × 1.186 = = vO vI vO vO iL iL vO RL ⁄ = QN, iN.
vBEN vBEN VT ln iN IS ⁄ ( ) = vI vI vO vBEN VBB 2 ⁄ – + = Example 11.3 928 Chapter 11 Output Stages and Power Amplifiers Example 11.3 continued It is also useful to find and as follows: A similar process can be employed for negative . However, symmetry can be utilized, obviating the need to repeat the calculations. The results obtained are displayed in the following table: The table also provides values for the dc gain as well as the incremental gain at the various values of . The incremental gain is computed as follows where is the small-signal output resistance of the amplifier, given by Eq. (11.31). The incremental gain is the slope of the voltage transfer characteristic, and the magnitude of its variation over the range of is an indication of the linearity of the output stage. Observe that for , the incremental gain changes from 0.94 to 1.00, about 6%. Also observe as becomes positive, supplies more and more of and is correspondingly reduced. The opposite happens for negative iP vEBP iP iN iL – = vEBP VT ln iP IS ⁄ ( ) = vO vO (V) iL (mA) iN (mA) iP (mA) vBEN (V) vEBP (V) vI (V) v O / v I Rout (W) v o / vi +10.0 100 100.04 0.04 0.691 0.495 10.1 0.99 0.25 1.00 +5.0 50 50.08 0.08 0.673 0.513 5.08 0.98 0.50 1.00 +1.0 10 10.39 0.39 0.634 0.552 1.041 0.96 2.32 0.98 +0.5 5 5.70 0.70 0.619 0.567 0.526 0.95 4.03 0.96 +0.2 2 3.24 1.24 0.605 0.581 0.212 0.94 5.58 0.95 +0.1 1 2.56 1.56 0.599 0.587 0.106 0.94 6.07 0.94 0 0 2 2 0.593 0.593 0 — 6.25 0.94 −0.1 −1 1.56 2.56 0.587 0.599 −0.106 0.94 6.07 0.94 −0.2 −2 1.24 3.24 0.581 0.605 −0.212 0.94 5.58 0.95 −0.5 −5 0.70 5.70 0.567 0.619 −0.526 0.95 4.03 0.96 −1.0 −10 0.39 10.39 0.552 0.634 −1.041 0.96 2.32 0.98 −5.0 −50 0.08 50.08 0.513 0.673 −5.08 0.98 0.50 1.00 −10.0 −100 0.04 100.04 0.495 0.691 −10.1 0.99 0.25 1.00 vO vI ⁄ vo vi ⁄ vO vo vi ----RL RL Rout + ---------------------= Rout vO 0 vO 10 V ≤ ≤ vO QN iL QP vO.
· 11.5 To increase the linearity of the class AB output stage, the quiescent current is increased. The price paid is an increase in quiescent power dissipation. For the output stage considered in Example 11.3: (a) Find the quiescent power dissipation.
(b) If is increased to 10 mA, find at and at V, and hence the percentage change. Compare to the case in Example 11.3.
(c) Find the quiescent power dissipation for the case in (b).
Ans. (a) 60 mW; (b) 0.988 to 1.00; for a change of 1.2% compared to the 6% change in Example 11.3; (c) 300 mW IQ IQ vo vi ⁄ vO 0 = vO 10 = EXERCISE 11.5 Biasing the Class AB Circuit 929 11.5 Biasing the Class AB Circuit In this section we discuss two approaches for generating the voltage VBB required for biasing the class AB output stage.
11.5.1 Biasing Using Diodes Figure 11.14 shows a class AB circuit in which the bias voltage VBB is generated by passing a constant current IBIAS through a pair of diodes, or diode-connected transistors, D1 and D2. In cir-cuits that supply large amounts of power, the output transistors are large-geometry devices.
The biasing diodes, however, need not be large devices, and thus the quiescent current IQ established in QN and QP will be IQ = nIBIAS, where n is the ratio of the emitter–junction area of the output devices to the junction area of the biasing diodes. In other words, the saturation (or scale) current IS of the output transistors is n times that of the biasing diodes. Area ratioing is simple to implement in integrated circuits but difficult to realize in discrete-circuit designs.
When the output stage of Fig. 11.14 is sourcing current to the load, the base current of QN increases from (which is usually small) to approximately . This base current drive must be supplied by the current source IBIAS. It follows that IBIAS must be greater than the maximum anticipated base drive for QN. This sets a lower limit on the value of IBIAS. Now, since n = IQ / IBIAS, and since IQ is usually much smaller than the peak load current (<10%), we see that we cannot make n a large number. In other words, we cannot make the diodes much smaller than the output devices. This is a disadvantage of the diode biasing scheme.
From the discussion above we see that the current through the biasing diodes will decrease when the output stage is sourcing current to the load. Thus the bias voltage VBB will also decrease, and the analysis of Section 11.4 must be modified to take this effect into account.
The diode biasing arrangement has an important advantage: It can provide thermal stabiliza-tion of the quiescent current in the output stage. To appreciate this point, recall that the class AB output stage dissipates power under quiescent conditions. Power dissipation raises the internal temperature of the BJTs. From Chapter 6 we know that a rise in transistor temperature results in a decrease in its VBE (approximately −2 mV/°C) if the collector current is held constant. Alterna-tively, if VBE is held constant and the temperature increases, the collector current increases. The increase in collector current increases the power dissipation, which in turn increases the junction IBIAS D1 D2 Figure 11.14 A class AB output stage utilizing diodes for biasing. If the junction area of the out-put devices, QN and QP, is n times that of the bias-ing devices D1 and D2, a quiescent current IQ = nIBIAS flows in the output devices.
IQ βN ⁄ iL βN ⁄ 930 Chapter 11 Output Stages and Power Amplifiers temperature and hence, once more, the collector current. Thus a positive-feedback mechanism exists that can result in a phenomenon called thermal runaway. Unless checked, thermal run-away can lead to the ultimate destruction of the BJT. Diode biasing can be arranged to provide a compensating effect that can protect the output transistors against thermal runaway under quies-cent conditions. Specifically, if the diodes are in close thermal contact with the output transis-tors, their temperature will increase by the same amount as that of QN and QP. Thus VBB will decrease at the same rate as , with the result that IQ remains constant. Close thermal contact is easily achieved in IC fabrication. It is obtained in discrete circuits by mounting the bias diodes on the metal case of QN or QP.
VBEN VEBP + Consider the class AB output stage under the conditions that and the output is sinu-soidal with a maximum amplitude of 10 V. Let QN and QP be matched with and Assume that the biasing diodes have one-third the junction area of the output devices. Find the value of that guar-antees a minimum of 1 mA through the diodes at all times. Determine the quiescent current and the quiescent power dissipation in the output transistors (i.e., at ). Also find VBB for +10 V, and −10 V.
Solution The maximum current through QN is approximately equal to Thus the maximum base current in QN is approximately 2 mA. To maintain a minimum of 1 mA through the diodes, we select The area ratio of 3 yields a quiescent current of 9 mA through QN and QP. The quiescent power dissipation is For the base current of QN is leaving a current of 3 − 0.18 = 2.82 mA to flow through the diodes. Since the diodes have the voltage VBB will be At the current through the diodes will decrease to 1 mA, resulting in At the other extreme of QN will be conducting a very small current; thus its base current will be negligibly small and all of (3 mA) flows through the diodes, resulting in V CC =15 V, RL = 100 Ω, IS =10 13 – A β = 50.
IBIAS vO = 0 vO = 0, iLmax =10 V/0.1 kΩ =100 mA.
IBIAS = 3 mA.
PDQ = 2 15 9 × × = 270 mW vO = 0, 9 51 0.18 mA, ⁄ IS 1 3 --10 13 – A, × = VBB = 2VT 2.82 mA IS ---------------------ln =1.26 V vO = +10 V, V BB 1.21 V.
vO = 1 – 0 V, IBIAS VBB 1.26 V.
Example 11.4 11.6 For the circuit of Example 11.4, find iN and iP for and (Hint: Use the values found in Example 11.4.) Ans. 100.1 mA, 0.1 mA; 0.8 mA, 100.8 mA 11.7 If the collector current of a transistor is held constant, its vBE decreases by 2 mV for every 1°C rise in temperature. Alternatively, if vBE is held constant, then iC increases by approximately gm × 2 mV for every 1°C rise in temperature. For a device operating at IC = 10 mA, find the change in collector cur-rent resulting from an increase in temperature of 5°C.
Ans. 4 mA vO = +10 V vO = −10 V.
VBB EXERCISES 11.5 Biasing the Class AB Circuit 931 11.5.2 Biasing Using the VBE Multiplier An alternative biasing arrangement that provides the designer with considerably more flexi-bility in both discrete and integrated designs is shown in Fig. 11.15. The bias circuit consists of transistor Q1 with a resistor R1 connected between base and emitter and a feedback resis-tor R2 connected between collector and base. The resulting two-terminal network is fed with a constant-current source IBIAS. If we neglect the base current of Q1, then R1 and R2 will carry the same current IR, given by (11.32) and the voltage VBB across the bias network will be (11.33) Thus the circuit simply multiplies VBE1 by the factor and is known as the “VBE multiplier.” The multiplication factor is obviously under the designer’s control and can be used to establish the value of VBB required to yield a desired quiescent current IQ. In IC design it is relatively easy to control accurately the ratio of two resistances. In discrete-circuit design, a potentiometer can be used, as shown in Fig. 11.16, and is manually set to produce the desired value of IQ.
The value of VBE1 in Eq. (11.33) is determined by the portion of IBIAS that flows through the collector of Q1; that is, (11.34) Figure 11.15 A class AB output stage utilizing a VBE multiplier for biasing.
IR V BE1 R1 ----------= V BB IR R1 R2 + ( ) = VBE1 1 R2 R1 -----+ ⎝ ⎠ ⎛ ⎞ = 1 R2 R1 ⁄ + ( ) IC1 IBIAS IR – = IBIAS 932 Chapter 11 Output Stages and Power Amplifiers (11.35) where we have neglected the base current of QN, which is normally small both under quies-cent conditions and when the output voltage is swinging negative. However, for positive vO, especially at and near its peak value, the base current of QN can become sizable and will reduce the current available for the VBE multiplier. Nevertheless, since large changes in IC1 correspond to only small changes in VBE1, the decrease in current will be mostly absorbed by Q1, leaving IR, and hence VBB, almost constant.
Like the diode biasing network, the VBE–multiplier circuit can provide thermal stabiliza-tion of IQ. This is especially true if R1 = R2, and Q1 is in close thermal contact with the output transistors.
Figure 11.16 A discrete-circuit class AB output stage with a potentiometer used in the VBE multiplier. The potentiometer is adjusted to yield the desired value of quiescent current in QN and QP.
IBIAS V BE1 VT ln IC1 IS1 ------= 11.8 Consider a VBE multiplier with R1 = R2 = 1.2 kΩ, utilizing a transistor that has VBE = 0.6 V at IC = 1 mA, and a very high β. (a) Find the value of the current I that should be supplied to the multiplier to obtain a terminal voltage of 1.2 V. (b) Find the value of I that will result in the terminal voltage changing (from the 1.2-V value) by +50 mV, +100 mV, +200 mV, –50 mV, –100 mV, –200 mV.
Ans. (a) 1.5 mA; (b) 3.24 mA, 7.93 mA, 55.18 mA, 0.85 mA, 0.59 mA, 0.43 mA EXERCISE 11.6 CMOS Class AB Output Stages 933 11.6 CMOS Class AB Output Stages In this section we study CMOS class AB output stages. We begin with the CMOS counterpart of the BJT class AB output stage studied in the previous section. As we shall see, this circuit suffers from a relatively low output signal-swing, a serious limitation especially in view of the shrinking power-supply voltages characteristic of modern deep-submicron CMOS technolo-gies. We will then look at an attractive alternative circuit that overcomes this problem.
11.6.1 The Classical Configuration Figure 11.17 shows the classical CMOS class AB output stage. The circuit is the exact coun-terpart of the bipolar circuit shown in Fig. 11.14 with the biasing diodes implemented with diode-connected transistors and The constant current flowing through and establishes a dc bias voltage between the gates of and This voltage in turn It is required to redesign the output stage of Example 11.4 utilizing a VBE multiplier for biasing. Use a small-geometry transistor for Q1 with IS = 10–14 A and design for a quiescent current IQ = 2 mA.
Solution Since the peak positive current is 100 mA, the base current of QN can be as high as 2 mA. We shall there-fore select IBIAS = 3 mA, thus providing the multiplier with a minimum current of 1 mA.
Under quiescent conditions (vO = 0 and iL = 0) the base current of QN can be neglected and all of IBIAS flows through the multiplier. We now must decide on how this current (3 mA) is to be divided between IC1 and IR. If we select IR greater than 1 mA, the transistor will be almost cut off at the positive peak of vO.
Therefore, we shall select IR = 0.5 mA, leaving 2.5 mA for IC1.
To obtain a quiescent current of 2 mA in the output transistors, VBB should be We can now determine R1 + R2 as follows: At a collector current of 2.5 mA, Q1 has The value of R1 can now be determined as and R2 as V BB 2VT ln 2 10 3 – × 10 13 – -------------------1.19 V = = R1 R2 + V BB IR ---------1.19 0.5 ----------2.38 kΩ = = = V BE1 VTln 2.5 10 3 – × 10 14 – ------------------------0.66 V = = R1 0.66 0.5 ----------1.32 kΩ = = R2 2.38 1.32 – 1.06 kΩ = = Example 11.5 Q1 Q2.
IBIAS Q1 Q2 VGG QN QP.
934 Chapter 11 Output Stages and Power Amplifiers establishes the quiescent current in and Unlike the BJT circuit in Fig.
11.14, here the zero dc gate current of results in the current through and remaining constant at irrespective of the value of and the load current Thus remains constant and the circuit is more like the idealized bipolar case shown in Fig. 11.11.
The value of can be determined by utilizing the equations for the four MOS transistors for the case . Neglecting channel-length modulation, we can write for , (11.36) and for , (11.37) Equations (11.36) and (11.37) can be used to find and , which when summed yield ; thus, (11.38) We can follow a similar process for and which, for , are conducting the qui-escent current ; thus, (11.39) Equations (11.38) and (11.39) can be combined to obtain (11.40) Q2 Q1 QP QN IBIAS VGG VDD VDD VSS vI vO RL iL Figure 11.17 Classical CMOS class AB output stage. This circuit is the CMOS counterpart of the BJT circuit in Fig. 11.14 with the biasing diodes implemented with diode-connected MOSFETs, Q1 and Q2.
vO 0 = ( ) IQ QN QP.
QN Q1 Q2 IBIAS vO iL.
VGG IQ iD vGS – vO 0 = Q1 ID1 IBIAS 1 2 ---k n ′ W L ⁄ ( )1 VGS1 Vtn – ( )2 = = Q2 ID2 IBIAS 1 2 ---kp ′ W L ⁄ ( )2 VSG2 Vtp – ( )2 = = VGS1 VSG2 VGG VGG VGS1 VSG2 Vtn Vtp 2IBIAS 1 kn ′ W L ⁄ ( )1 -----------------------------1 kp ′ W L ⁄ ( )2 -----------------------------+ ⎝ ⎠ ⎛ ⎞ + + = + = QN QP vO 0 = IQ VGG VGSN VSGP Vtn Vtp 2IQ 1 kn ′ W L ⁄ ( )n ----------------------------1 kp ′ W L ⁄ ( )p ----------------------------+ ⎝ ⎠ ⎛ ⎞ + + = + = IQ IBIAS 1 kn ′ W L ⁄ ( )1 ⁄ 1 kp′ W L ⁄ ( )2 ⁄ + 1 kn ′ W L ⁄ ( )n ⁄ 1 kp′ W L ⁄ ( )p ⁄ + ------------------------------------------------------------------------------2 = 11.6 CMOS Class AB Output Stages 935 which indicates that is determined by together with the ratios of the four transistors. For the case and are matched, that is, (11.41) and and are matched, that is, (11.42) Equation (11.40) simplifies to (11.43) which is an intuitively appealing result.
A drawback of the CMOS class AB circuit of Fig. 11.17 is the restricted range of output voltage swing. To find the maximum possible value of , refer to Fig. 11.17 and assume that across the bias current source is a dc voltage of . We can write for , (11.44) The maximum value of will be limited by the need to keep to a minimum of of the transistor supplying (otherwise the current-source transistor no longer operates in saturation); thus, (11.45) Note that when is at its maximum value, will be supplying most or all of , and will be large, (11.46) where is the overdrive voltage of when it is supplying .
IQ IBIAS W L ⁄ ( ) Q1 Q2 kp ′ W L ⁄ ( )2 kn ′ W L ⁄ ( )1 = QN QP kp ′ W L ⁄ ( )p kn ′ W L ⁄ ( )n = IQ IBIAS W L ⁄ ( )n W L ⁄ ( )1 -------------------= 11.9 For the CMOS class AB output stage of Fig. 11.17, consider the case of matched and , and matched and . If mA and mA, find for each of , , , and so that in the quiescent state each transistor operates at an overdrive voltage of 0.2 V. Let V, , , and V. Also find .
Ans. 40; 100; 200; 500; 1.4 V Q1 Q2 QN QP IQ 1 = IBIAS 0.2 = W L ⁄ ( ) Q1 Q2 QN QP VDD VSS 2.5 = = kn ′ 250 μA V2 ⁄ = kp ′ 100 μA V2 ⁄ = Vtn Vtp 0.5 = – = VGG EXERCISE vO VBIAS vO vO VDD VBIAS – vGSN – = vO VBIAS VOV IBIAS vOmax VDD VOV BIAS – vGSN – = vO QN iL vGSN vOmax VDD VOV BIAS – Vtn v – OVN – = vOVN QN iLmax 936 Chapter 11 Output Stages and Power Amplifiers The minimum allowed value of can be found in a similar way. Here we note that the transistor supplying (not shown) will need a minimum voltage across it of . Thus, (11.47) where is the overdrive voltage of when sinking the maximum negative value of .
Finally, we observe that the reason for the lower allowable range of in the CMOS cir-cuit is the relatively large value of and ; that is, the large values of and required to supply the large output currents. In the BJT circuit the corresponding volt-ages, and , remain close to 0.7 V. The overdrive voltages and can be reduced by making the W/L ratios of and large. This, however, can lead to impracti-cally large devices.
11.6.2 An Alternative Circuit Utilizing Common-Source Transistors The allowable range of can be increased by replacing the source followers with a pair of complementary transistors connected in the common-source configuration, as shown in Fig.
11.18. Here supplies the load current when is positive and allows to go as high as , a much higher value than that given by Eq. (11.46). For negative , sinks the load current and allows to go as low as . This also is larger in mag-nitude than the value given by Eq. (11.47). Thus, the circuit of Fig. 11.18 provides an output voltage range that is within an overdrive voltage of each of the supplies. The disadvantage of the circuit, however, is its high output resistance, (11.48) 11.10 For the circuit specified in Exercise 11.9, find when mA. Assume that is supplying all of and that V.
Ans. 1.17 V v O max iLmax 10 = QN iLmax VOV BIAS 0.2 = EXERCISE vO vI VOV I vOmin VSS – VOV I Vtp vOVP + + + = vOVP QP iL vO vOVN vOVP vGSN vSGP vBEN vEBP vOVN vOVP QN QP vO QP vO vO VDD vOVP – ( ) vO QN vO VSS – vOVN + Rout ron rop || = QN QP VDD vO RL iL VSS Figure 11.18 An alternative CMOS output stage utilizing a pair of complementary MOSFETs connected in the common-source configuration. The driving circuit is not shown.
11.6 CMOS Class AB Output Stages 937 To reduce the output resistance, negative feedback is employed as shown in Fig. 11.19. Here an amplifier with gain is inserted between drain and gate of each of and For rea-sons that will become clear shortly, these amplifiers are called error amplifiers. To verify that the feedback around each amplifier is negative, assume that increases. The top amplifier will cause the gate voltage of to increase, thus its decreases and decreases. The decrease in causes to decrease, which is opposite to the initially assumed change, thus verifying that the feedback is negative. A similar process can be used to verify that the feedback around the bottom amplifier also is negative.
From our study of feedback in Chapter 10, we observe that each of the two feedback loops is of the series-shunt type, which is the topology appropriate for a voltage amplifier.
Thus, as we shall show shortly, the feedback will reduce the output resistance of the ampli-fier. Also, observe that if the loop gain is large, the voltage difference between the two input terminals of each feedback amplifier, the error voltage, will be small, resulting in .
Both the low output resistance and the near-unity dc gain are highly desirable properties for an output stage.
Output Resistance To derive an expression for the output resistance Rout, we consider each half of the circuit separately, find its output resistance, Routp for the top half and Routn for the bottom half, and then obtain the overall output resistance as the parallel equivalent of the two resistances, (11.49) Figure 11.20(a) shows the top half of the circuit, drawn a little differently to make the feedback topology clearer. Observe that feedback is applied by connecting the output back to the input. Thus the feedback network is the two-port shown in Fig. 11.20(b) and the feed-back factor is (11.50) Including the loading effects of the feedback network results in the A circuit shown in Fig. 11.20(c). Note that since we are now interested in incremental quantities, we have QN QP VDD VSS m m vI Rout vO RL iL iDP iDN Figure 11.19 Inserting an amplifier in the negative feedback path of each of QN and QP reduces the output resistance and makes vO vI ; both are desirable properties for the output stage.
μ QN QP.
vO QP vSG iDP iDP vO vO vI Rout Routn Routp || = β 1 = 938 Chapter 11 Output Stages and Power Amplifiers replaced with a short circuit to ground. The open-loop gain A can be found from the circuit in Fig. 11.20(c) as (11.51) where we have assumed the input resistance of the amplifier to be infinite and thus resis-tance at the input has no effect on the gain, and we have utilized implicitly the small-signal model of . The values of the small-signal parameters and are to be eval-uated at the current at which is operating. The open-loop output resistance is found by inspection as (11.52) The output resistance with feedback can now be found as (11.53) and the output resistance Routp is found by excluding from , that is (11.54) (a) vi (c) QP m RL RL Ro (b) RL vf vo vo QP m vI RL Rof Routp vO VDD Figure 11.20 Determining the output resistance; (a) The top half of the output stage showing the defini-tion of Routp and Rof; (b) The β circuit; and (c) the A circuit.
VDD A vo vi ----μ gmp rop RL || ( ) = ≡ RL QP gmp rop QP Ro Ro RL rop || = Rof Rof Ro 1 Aβ + ----------------RL rop || ( ) 1 μ gmp rop RL || ( ) + ----------------------------------------------= = RL Rof Routp 1 1 Rof -------1 RL ------– ⎝ ⎠ ⎛ ⎞ = 11.6 CMOS Class AB Output Stages 939 which results in (11.55) which can be quite low. A similar development applied to the bottom half of the circuit in Fig. 11.19 results in (11.56) Combining Eqs. (11.55) and (11.56) gives (11.57) The Voltage Transfer Characteristic Next we derive an expression for the voltage transfer characteristic, versus , of the class AB common-source buffer. Toward that end, we first consider the circuit in the quiescent state, shown in Fig. 11.21(a). Here and Each of the error amplifiers is designed to deliver to the gate of its associated MOSFET the dc voltage required to establish the desired value of quiescent current To obtain class AB operation, is usually selected to be 10% or so of the maximum output cur-rent. Referring to Fig. 11.21(a), we can write for , Substituting , where is the magnitude of the quiescent overdrive voltage of , gives (11.58) Similarly, we obtain for (11.59) Routp rop 1 μgmp ------------ 1 μgmp ------------= Routn 1 μgmn ⁄ Rout 1 μ gmp gmn + ( ) ⁄ vO vI vI 0 = vO 0.
= IQ.
IQ QP IDP IQ 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞ p VSGP Vtp – ( )2 = = (a) QN QP VDD VSS VGSN VDD VSGP VGSN VSGP 0 V 0 RL m m (b) (VSS VGSN) m(vO vI) (VDD VSGP) m(vO vI) vGSN vSGP QN QP VDD VSS vO vI RL iDN iDP m m IQ IQ iL VSS Figure 11.21 Analysis of the CMOS output stage to determine vO versus vI: (a) Quiescent conditions; (b) The situation with vI applied.
VSGP Vtp VOV + = VOV QP IQ 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞ p VOV 2 = QN IQ 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ n VOV 2 = 940 Chapter 11 Output Stages and Power Amplifiers Usually the two transistors are matched, Thus, (11.60) Next consider the situation with applied, illustrated in Fig. 11.21(b). The voltage at the output of each of the error amplifiers increases by Thus decreases by and increases by and we can write (11.61) and (11.62) At the output node we have (11.63) Substituting for and for and from Eqs. (11.61) and (11.62), and solv-ing the resulting equation to obtain , results in (11.64) Usually , enabling us to express as (11.65) Thus the gain error is (11.66) Since at the quiescent point, (11.67) the gain error can be expressed as (11.68) kp ′ W L -----⎝ ⎠ ⎛ ⎞ p kn ′ W L -----⎝ ⎠ ⎛ ⎞ n k = = IQ 1 2 ---kVOV 2 = vI μ vO vI – ( ).
vSGP μ vO vI – ( ) vGSN μ vO vI – ( ), iDP 1 2 ---k VOV μ vO vI – ( ) – [ ]2 = 1 2 ---kVOV 2 1 μ vO vI – VOV ----------------– 2 = IQ 1 μ vO vI – VOV ----------------– ⎝ ⎠ ⎛ ⎞ 2 = iDN IQ 1+ μ vO vI – VOV ----------------⎝ ⎠ ⎛ ⎞ 2 = iL iDP iDN – = iL vO RL ⁄ = iDP iDN vO vO vI 1 VOV 4μIQRL ------------------+ ----------------------------= VOV 4μIQRL ⁄ ( ) 1 vO vO vI 1 VOV 4μIQRL ------------------– ⎝ ⎠ ⎛ ⎞ Gain error vO vI VOV 4μIQRL ------------------– = – ≡ gmp gm 2IQ VOV ---------= = Gain error 1 2μgmRL -------------------– = 11.6 CMOS Class AB Output Stages 941 Thus selecting a large value for results in reducing both the gain error and the output resistance. However, a large can make the quiescent current too dependent on the input offset voltages that are inevitably present in the error amplifiers. Typically, is selected in the range 5 to 10. Trade-offs are also present in the selection of : A large reduces crossover distortion, , and gain error, at the expense of increased quiescent power dissipation. μ μ IQ μ IQ IQ Rout In this example we explore the design and operation of a class AB common-source output stage of the type shown in Fig. 11.19, required to operate from a -V power supply to feed a load resistance . The transistors available have V and The gain error is required to be less than 2.5% and IQ = 1 mA.
Solution The gain error is given by Eq. (11.66), We are given the required maximum gain error of , mA, and . In order to keep low and also obtain as high a as possible , we select to be as low as possible. Practically speaking, is usually 0.1 V to 0.2 V. Selecting V results in which yields which is within the typically recommended range.
Figure 11.22(a) shows the circuit in the quiescent state with the various dc voltages and currents indi-cated. The required (W/L) ratios of and can be found as follows: Thus, Thus and are very large transistors, not an unusual situation in a high-power output stage.
To obtain the output resistance at the quiescent point, we use Eq. (11.57), 2.5 ± RL 100 Ω = Vtn Vtp 0.5 = – = kn ′ 2.5kp ′ 250 μA V2 .
⁄ = = Gain error VOV 4μIQRL ------------------– = 0.025 – IQ 1 = RL 100 Ω = μ gm gm 2IQ VOV ⁄ = [ ] VOV VOV VOV 0.1 = 0.025 0.1 4 μ 1 10 3 – 100 × × × × ------------------------------------------------------= μ 10 = QN QP IQ 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞ pVOV 2 = 1 10 3 – × 1 2 ---0.1 10 3 – × × W L -----⎝ ⎠ ⎛ ⎞ p 0.1 ( ) × 2 = W L -----⎝ ⎠ ⎛ ⎞ p 2000 = W L -----⎝ ⎠ ⎛ ⎞ n W L ⁄ ( )p kn ′ kp ′ ⁄ -------------------2000 2.5 ------------800 = = = QN QP Rout 1 μ gmp gmn + ( ) --------------------------------= Example 11.6 942 Chapter 11 Output Stages and Power Amplifiers Example 11.6 continued (c) (a) (b) QN QP 2 V 4 mA 0 4 mA 1.8 V 0.41 V 0.4 V 2.5 V 2.5 V 100 10 10 QN QP 1.9 V 1 mA 1 mA 1.9 V 2.5 V 2.5 V 0 V RL 100 10 10 0 QP VDD vOmax vOVmax RL iLmax 0 iDP m vImax vOmax Vtp Vtp At the edge of triode region Figure 11.22 (a) Circuit in the quiescent state; (b) circuit at the point at which QN turns off; (c) conditions at vO = vOmax.
11.7 Power BJTs 943 11.7 Power BJTs Transistors that are required to conduct currents in the ampere range and to withstand power dissipation in the watts and tens-of-watts ranges differ in their physical structure, packaging, and specification from the small-signal transistors considered in earlier chapters. In this sec-tion we consider some of the important properties of power transistors, especially those where mA/V Thus Next we wish to determine the maximum and minimum allowed values of Since the circuit is symmetrical, we need to consider only either the positive-output or negative-output case. For positive, conducts more of the output current Eventually, turns off and conducts all of To find the value of at which this occurs, note that turns off when the voltage at its gate drops from the quiescent value of V (see Fig. 11.22a) to V, at which point An equal change of V appears at the output of the top amplifier, as shown in Fig. 11.22(b). Analysis of the circuit in Fig.
11.22(b) shows that mA V For V, must conduct all the current . The situation at is illustrated in Fig.
11.22(c). Analysis of this circuit results, after some straightforward but tedious manipulations, in V and mA gmp gmn 2IQ VOV ---------2 1 × 0.1 ------------20 = = = = Rout 1 10 0.02 0.02 + ( ) --------------------------------------2.5 Ω = = vO.
vO QP iL.
QN QP iL.
vO QN 1.9 – 2 – vGSN Vtn.
= 0.1 – iL iDP 4 = = vO iLRL 4 10 3 – 100 0.4 = × × = = vO 0.4 > QP iL vO vOmax = vOmax 2.05 iLmax 20.5 = 11.11 Suppose it is required to reduce the size of and in the circuit considered in the above ex-ample by a factor of 2 while keeping at 1 mA. What value should be used for ? What is the new value for the gain error and for at the quiescent point?
Ans. 0.14 V; %; 3.5 11.12 Show that in the CMOS class AB common-source output stage, turns off when and that turns off when . This is equivalent to saying that one of the transistors turns off when reaches .
QN QP IQ VOV Rout 3.5 – Ω QN vO 4IQRL = QP vO 4IQRL – = iL 4IQ EXERCISES 944 Chapter 11 Output Stages and Power Amplifiers aspects that pertain to the design of circuits of the type discussed earlier. There are, of course, other important applications of power transistors, such as their use as switching ele-ments in power inverters and motor-control circuits. Such applications are not studied in this book.
11.7.1 Junction Temperature Power transistors dissipate large amounts of power in their collector–base junctions. The dissipated power is converted into heat, which raises the junction temperature. However, the junction temperature TJ must not be allowed to exceed a specified maximum, TJmax; other-wise the transistor could suffer permanent damage. For silicon devices, TJmax is in the range of 150°C to 200°C.
11.7.2 Thermal Resistance Consider first the situation of a transistor operating in free air—that is, with no special arrangements for cooling. The heat dissipated in the transistor junction will be conducted away from the junction to the transistor case, and from the case to the surrounding environ-ment. In a steady state in which the transistor is dissipating PD watts, the temperature rise of the junction relative to the surrounding ambience can be expressed as (11.69) where θJA is the thermal resistance between junction and ambience, having the units of degrees Celsius per watt. Note that θJA simply gives the rise in junction temperature over the ambient temperature for each watt of dissipated power. Since we wish to be able to dissipate large amounts of power without raising the junction temperature above TJmax, it is desirable to have, for the thermal resistance θJA, as small a value as possible. For operation in free air, θJA depends primarily on the type of case in which the transistor is packaged. The value of θJA is usually specified on the transistor data sheet.
Equation (11.69), which describes the thermal-conduction process, is analogous to Ohm’s law, which describes the electrical-conduction process. In this analogy, power dissi-pation corresponds to current, temperature difference corresponds to voltage difference, and thermal resistance corresponds to electrical resistance. Thus, we may represent the thermal-conduction process by the electric circuit shown in Fig. 11.23.
11.7.3 Power Dissipation Versus Temperature The transistor manufacturer usually specifies the maximum junction temperature TJmax, the maximum power dissipation at a particular ambient temperature TA0 (usually, 25°C), and the T J T A – θJAP D = Figure 11.23 Electrical equivalent circuit of the thermal-conduction process; TJ − TA = PDθJΑ.
11.7 Power BJTs 945 thermal resistance θJA. In addition, a graph such as that shown in Fig. 11.24 is usually pro-vided. The graph simply states that for operation at ambient temperatures below TA0, the device can safely dissipate the rated value of PD0 watts. However, if the device is to be oper-ated at higher ambient temperatures, the maximum allowable power dissipation must be derated according to the straight line shown in Fig. 11.24. The power-derating curve is a graphical representation of Eq. (11.69). Specifically, note that if the ambient temperature is TA0 and the power dissipation is at the maximum allowed (PD0), then the junction temperature will be TJmax. Substituting these quantities in Eq. (11.69) results in (11.70) which is the inverse of the slope of the power-derating straight line. At an ambient tempera-ture TA, higher than TA0, the maximum allowable power dissipation PDmax can be obtained from Eq. (11.69) by substituting TJ = TJmax; thus, (11.71) Observe that as TA approaches TJmax, the allowable power dissipation decreases; the lower thermal gradient limits the amount of heat that can be removed from the junction. In the extreme situation of TA = TJmax, no power can be dissipated because no heat can be removed from the junction.
Figure 11.24 Maximum allowable power dissipation versus ambient temperature for a BJT operated in free air. This is known as a “power-derating” curve.
θJA T Jmax T A0 – P D0 -------------------------= P Dmax T Jmax T A – θJA -----------------------= A BJT is specified to have a maximum power dissipation PD0 of 2 W at an ambient temperature TA0 of 25°C, and a maximum junction temperature TJmax of 150°C. Find the following: (a) The thermal resistance θJA.
(b) The maximum power that can be safely dissipated at an ambient temperature of 50°C.
(c) The junction temperature if the device is operating at TA = 25°C and is dissipating 1 W.
Example 11.7 946 Chapter 11 Output Stages and Power Amplifiers 11.7.4 Transistor Case and Heat Sink The thermal resistance between junction and ambience, θJA, can be expressed as (11.72) where θJC is the thermal resistance between junction and transistor case (package) and θCA is the thermal resistance between case and ambience. For a given transistor, θJC is fixed by the device design and packaging. The device manufacturer can reduce θJC by encapsulating the device in a relatively large metal case and placing the collector (where most of the heat is dissipated) in direct contact with the case. Most high-power transistors are packaged in this fashion. Figure 11.25 shows a sketch of a typical package.
Although the circuit designer has no control over θJC (once a particular transistor has been selected), the designer can considerably reduce θCA below its free-air value (specified by the manufacturer as part of θJA). Reduction of θCA can be effected by providing means to facilitate heat transfer from case to ambience. A popular approach is to bolt the transistor to the chassis or to an extended metal surface. Such a metal surface then functions as a heat sink. Heat is easily conducted from the transistor case to the heat sink; that is, the thermal resistance θCS is usually very small. Also, heat is efficiently transferred (by convection and radiation) from the heat sink to the ambience, resulting in a low thermal resistance θSA. Thus, if a heat sink is utilized, the case-to-ambience thermal resistance given by (11.73) can be small because its two components can be made small by the choice of an appropriate heat sink.2 For example, in very high-power applications the heat sink is usually equipped with fins that further facilitate cooling by radiation and convection.
2As noted earlier, the metal case of a power transistor is electrically connected to the collector. Thus an electrically insulating material such as mica is usually placed between the metal case and the metal heat sink. Also, insulating bushings and washers are generally used in bolting the transistor to the heat sink.
Example 11.7 continued Solution (a) (b) (c) θJA T Jmax T A0 – P D0 ---------------------------150 25 – 2 ---------------------62.5°C/W = = = PDmax T Jmax T A – θJA ------------------------150 50 – 62.5 ---------------------1.6 W = = = T J T A θJAPD + 25 62.5 1 × + 87.5°C = = = θJA θJC θCA + = Figure 11.25 The popular TO3 package for power transistors. The case is metal with a diameter of about 2.2 cm; the outside dimension of the “seating plane” is about 4 cm. The seating plane has two holes for screws to bolt it to a heat sink. The collector is electrically connected to the case. Therefore an electrically insulating but thermally conducting spacer is used between the transistor case and the “heat sink.” θCA θCS θSA + = 11.7 Power BJTs 947 The electrical analog of the thermal-conduction process when a heat sink is employed is shown in Fig. 11.26, from which we can write (11.74) As well as specifying θJC, the device manufacturer usually supplies a derating curve for PDmax versus the case temperature, TC. Such a curve is shown in Fig. 11.27. Note that the slope of the power-derating straight line is −1/θJC. For a given transistor, the maximum power dissipation at a case temperature TC0 (usually 25°C) is much greater than that at an ambient temperature TA0 (usually 25°C). If the device can be maintained at a case temper-ature TC, TC0 ≤ TC ≤ T Jmax, then the maximum safe power dissipation is obtained when TJ = TJmax, (11.75) Figure 11.27 Maximum allowable power dissipation versus transistor-case temperature.
Figure 11.26 Electrical analog of the thermal conduction process when a heat sink is utilized.
T J T A – PD θJC θCS θSA + + ( ) = PDmax T Jmax T C – θJC -----------------------= 948 Chapter 11 Output Stages and Power Amplifiers A BJT is specified to have TJmax = 150°C and to be capable of dissipating maximum power as follows: Above 25°C, the maximum power dissipation is to be derated linearly with θJC = 3.12°C/W and θJA = 62.5°C/W.
Find the following: (a) The maximum power that can be dissipated safely by this transistor when operated in free air at TA = 50°C.
(b) The maximum power that can be dissipated safely by this transistor when operated at an ambient tem-perature of 50°C, but with a heat sink for which θCS = 0.5°C/W and θSA = 4°C/W. Find the temperature of the case and of the heat sink.
(c) The maximum power that can be dissipated safely if an infinite heat sink is used and TA = 50°C.
Solution (a) (b) With a heat sink, θJA becomes Thus, Figure 11.28 shows the thermal equivalent circuit with the various temperatures indicated.
Figure 11.28 Thermal equivalent circuit for Example 11.8.
40 W at T C 25°C = 2 W at T A 25°C = PDmax T Jmax T A – θJA ------------------------150 50 – 62.5 ---------------------1.6 W = = = θJA θJC θCS θSA + + = 3.12 = 0.5 4 + + 7.62°C/W = PDmax 150 50 – 7.62 ---------------------13.1 W = = Example 11.8 11.7 Power BJTs 949 The advantage of using a heat sink is clearly evident from Example 11.8: With a heat sink, the maximum allowable power dissipation increases from 1.6 W to 13.1 W. Also note that although the transistor considered can be called a “40-W transistor,” this level of power dissipation cannot be achieved in practice; it would require an infinite heat sink and an ambient temperature TA ≤ 25°C.
11.7.5 The BJT Safe Operating Area In addition to specifying the maximum power dissipation at different case temperatures, power-transistor manufacturers usually provide a plot of the boundary of the safe operating area (SOA) in the iC–vCE plane. The SOA specification takes the form illustrated by the sketch in Fig. 11.29; the following paragraph numbers correspond to the boundaries on the sketch.
1. The maximum allowable current ICmax. Exceeding this current on a continuous basis can result in melting the wires that bond the device to the package terminals.
2. The maximum power dissipation hyperbola. This is the locus of the points for which vCEiC = PDmax (at TC0). For temperatures TC > TC0, the power-derating curves described in Section 11.7.4 should be used to obtain the applicable PDmax and thus a correspondingly lower hyperbola. Although the operating point can be allowed to move temporarily above the hyperbola, the average power dissipation should not be allowed to exceed PDmax.
3. The second-breakdown limit. Second breakdown is a phenomenon that results because current flow across the emitter–base junction is not uniform. Rather, the current density is greatest near the periphery of the junction. This “current crowding” gives rise to increased localized power dissipation and hence temperature rise (at loca-tions called hot spots). Since a temperature rise causes an increase in current, a local-ized form of thermal runaway can occur, leading to junction destruction.
(c) An infinite heat sink, if it existed, would cause the case temperature TC to equal the ambient tempera-ture TA. The infinite heat sink has θCA = 0. Obviously, one cannot buy an infinite heat sink; neverthe-less, this terminology is used by some manufacturers to describe the power-derating curve of Fig. 11.27.
The abscissa is then labeled TA and the curve is called “power dissipation versus ambient temperature with an infinite heat sink.” For our example, with infinite heat sink, PDmax T Jmax T A – θJC ------------------------150 50 – 3.12 ---------------------32 W = = = 11.13 The 2N6306 power transistor is specified to have TJmax = 200°C and PDmax = 125 W for TC ≤ 25°C.
For TC ≥ 25°C, θJC = 1.4°C/W. If in a particular application this device is to dissipate 50 W and operate at an ambient temperature of 25°C, find the maximum thermal resistance of the heat sink that must be used (i.e., θSA). Assume θCS = 0.6°C/W. What is the case temperature, TC?
Ans. 1.5°C/W; 130°C EXERCISE 950 Chapter 11 Output Stages and Power Amplifiers 4. The collector-to-emitter breakdown voltage, BVCEO. The instantaneous value of vCE should never be allowed to exceed BVCEO; otherwise, avalanche breakdown of the collector–base junction may occur (see Section 6.9).
Finally, it should be mentioned that logarithmic scales are usually used for iC and vCE, leading to an SOA boundary that consists of straight lines.
11.7.6 Parameter Values of Power Transistors Owing to their large geometry and high operating currents, power transistors display typical parameter values that can be quite different from those of small-signal transistors. The important differences are as follows: 1. At high currents, the exponential iC–vBE relationship exhibits a factor of 2 reduction in the exponent; that is, .
2. β is low, typically 30 to 80, but can be as low as 5. Here, it is important to note that β has a positive temperature coefficient.
3. At high currents, rπ becomes very small (a few ohms) and rx becomes important (rx is defined and explained in Section 9.2.2).
4. fT is low (a few megahertz), Cμ is large (hundreds of picofarads), and Cπ is even larger. (These parameters are defined and explained in Section 9.2.2).
5. ICBO is large (a few tens of microamps) and, as usual, doubles for every 10°C rise in temperature.
6. BVCEO is typically 50 to 100 V but can be as high as 500 V.
7. ICmax is typically in the ampere range but can be as high as 100 A.
11.8 Variations on the Class AB Configuration In this section, we discuss a number of circuit improvements and protection techniques for the BJT class AB output stage.
Figure 11.29 Safe operating area (SOA) of a BJT.
BVCEO iC ISevBE 2V T ⁄ = 11.8 Variations on the Class AB Configuration 951 11.8.1 Use of Input Emitter Followers Figure 11.30 shows a class AB circuit biased using transistors Q1 and Q2, which also func-tion as emitter followers, thus providing the circuit with a high input resistance. In effect, the circuit functions as a unity-gain buffer amplifier. Since all four transistors are usually matched, the quiescent current (vI = 0, RL = ∞) in Q3 and Q4 is equal to that in Q1 and Q2.
Resistors R3 and R4 are usually very small and are included to compensate for possible mis-matches between Q3 and Q4 and to guard against the possibility of thermal runaway due to temperature differences between the input- and output-stage transistors. The latter point can be appreciated by noting that an increase in the current of, say, Q3 causes an increase in the voltage drop across R3 and a corresponding decrease in VBE3. Thus R3 provides negative feed-back that helps stabilize the current through Q3.
Because the circuit of Fig. 11.30 requires high-quality pnp transistors, it is not suitable for implementation in conventional monolithic IC technology. However, excellent results have been obtained with this circuit implemented in hybrid thick-film technology (Wong and Sherwin, 1979). This technology permits component trimming, for instance, to mini-mize the output offset voltage. The circuit can be used alone or together with an op amp to provide increased output driving capability. The latter application will be discussed in the next section.
Figure 11.30 A class AB output stage with an input buffer. In addition to providing a high input resis-tance, the buffer transistors Q1 and Q2 bias the output transistors Q3 and Q4.
952 Chapter 11 Output Stages and Power Amplifiers 11.8.2 Use of Compound Devices To increase the current gain of the output-stage transistors, and thus reduce the required base current drive, the Darlington configuration shown in Fig. 11.31 is frequently used to replace the npn transistor of the class AB stage. The Darlington configuration is equivalent to a sin-gle npn transistor having β β1β2, but almost twice the value of VBE.
The Darlington configuration can be also used for pnp transistors, and this is indeed done in discrete-circuit design. In IC design, however, the lack of good-quality pnp transis-tors prompted the use of the alternative compound configuration shown in Fig. 11.32. This compound device is equivalent to a single pnp transistor having β β1β 2. When fabricated with standard IC technology, Q1 is usually a lateral pnp having a low β (β = 5 − 10) and poor high-frequency response ( fT 5 MHz); see Appendix A and Appendix 7.A. The compound device, although it has a relatively high equivalent β, still suffers from a poor high-frequency response. It also suffers from another problem: The feedback loop formed by Q1 and Q2 is prone to high-frequency oscillations (with frequency near fT of the pnp device, i.e., about 5 MHz). Methods exist for preventing such oscillations. The subject of feedback-amplifier stability was studied in Chapter 10.
Figure 11.31 The Darlington configuration.
11.14 (Note: Although very instructive, this exercise is rather long.) Consider the circuit of Fig. 11.30 with R1 = R2 = 5 kΩ, R3 = R4 = 0 Ω, and VCC = 15 V. Let the transistors be matched with IS = 3.3 10−14 A and β = 200. (These are the values used in the LH002 manufactured by National Semiconductor, except that R3 = R4 = 2 Ω there.) (a) For vI = 0 and , find the quiescent current in each of the four transistors and vO. (b) For , find iC1, iC2, iC3, iC4, and vO for vI = +10 V and −10 V. (c) Repeat (b) for RL = 100 Ω.
Ans. (a) 2.87 mA; 0 V; (b) for vI = +10 V: 0.88 mA, 4.87 mA, 1.95 mA, 1.95 mA, +9.98 V; for vI = −10 V: 4.87 mA, 0.88 mA, 1.95 mA, 1.95 mA, −9.98 V; (c) for vI = +10 V: 0.38 mA, 4.87 mA, 100 mA, 0.02 mA, + 9.86 V; for vI = −10 V: 4.87 mA, 0.38 mA, 0.02 mA, 100 mA, −9.86 V RL ∞ = RL ∞ = EXERCISE 11.8 Variations on the Class AB Configuration 953 To illustrate the application of the Darlington configuration and of the compound pnp, we show in Fig. 11.33 an output stage utilizing both. Class AB biasing is achieved using a VBE multiplier. Note that the Darlington npn adds one more VBE drop, and thus the VBE multiplier is required to provide a bias voltage of about 2 V. The design of this class AB stage is inves-tigated in Problem 11.43. Figure 11.32 The compound-pnp configuration.
Figure 11.33 A class AB output stage utilizing a Darlington npn and a compound pnp. Biasing is obtained using a VBE multiplier.
IBIAS 954 Chapter 11 Output Stages and Power Amplifiers 11.8.3 Short-Circuit Protection Figure 11.34 shows a class AB output stage equipped with protection against the effect of short-circuiting the output while the stage is sourcing current. The large current that flows through Q1 in the event of a short circuit will develop a voltage drop across RE1 of sufficient value to turn Q5 on. The collector of Q5 will then conduct most of the current IBIAS, robbing Q1 of its base drive. The current through Q1 will thus be reduced to a safe operating level. This method of short-circuit protection is effective in ensuring device safety, but it has the disadvantage that under normal operation about 0.5 V drop might appear across each RE.
This means that the voltage swing at the output will be reduced by that much, in each direc-tion. On the other hand, the inclusion of emitter resistors provides the additional benefit of protecting the output transistors against thermal runaway.
11.15 (a) Refer to Fig. 11.32. Show that, for the composite pnp transistor, and Hence show that and thus the transistor has an effective scale current where ISP is the saturation current of the pnp transistor Q1.
(b) For βP = 20, βN = 50, ΙSP = 10−14 A, find the effective current gain of the compound device and its vEB when iC = 100 mA.
Ans. (b) 1000; 0.651 V iB iC βNβP ------------iE iC iC βNISPevEB/V T IS βNISP = EXERCISE D11.16 In the circuit of Fig. 11.34 let IBIAS = 2 mA. Find the value of RE1 that causes Q5 to turn on and absorb all 2 mA when the output current being sourced reaches 150 mA. For Q5, IS = 10−14 A.
If the normal peak output current is 100 mA, find the voltage drop across RE1 and the collector current of Q5.
Ans. 4.3 Ω; 430 mV; 0.3 μA EXERCISE 11.9 IC Power Amplifiers 955 11.8.4 Thermal Shutdown In addition to short-circuit protection, most IC power amplifiers are usually equipped with a circuit that senses the temperature of the chip and turns on a transistor in the event that the temperature exceeds a safe preset value. The turned-on transistor is connected in such a way that it absorbs the bias current of the amplifier, thus virtually shutting down its operation.
Figure 11.35 shows a thermal-shutdown circuit. Here, transistor Q2 is normally off. As the chip temperature rises, the combination of the positive temperature coefficient of zener diode Z1 and the negative temperature coefficient of VBE1 causes the voltage at the emitter of Q1 to rise. This in turn raises the voltage at the base of Q2 to the point at which Q2 turns on. 11.9 IC Power Amplifiers A variety of IC power amplifiers are available. Most consist of a high-gain, small-signal amplifier followed by a class AB output stage. Some have overall negative feedback already applied, resulting in a fixed closed-loop voltage gain. Others do not have on-chip feedback and are, in effect, op amps with large output-power capability. In fact, the output current-driving capability of any general-purpose op amp can be increased by cascading it with a class B or class AB output stage and applying overall negative feedback. The additional out-put stage can be either a discrete circuit or a hybrid IC such as the buffer discussed in the preceding section. In the following we discuss some power-amplifier examples.
Figure 11.34 A class AB output stage with short-circuit protection. The protection circuit shown operates in the event of an output short circuit while vO is positive.
vO IBIAS 956 Chapter 11 Output Stages and Power Amplifiers 11.9.1 A Fixed-Gain IC Power Amplifier Our first example is the LM380 (a product of National Semiconductor Corporation), which is a fixed-gain monolithic power amplifier. A simplified version of the internal circuit of the amplifier3 is shown in Fig. 11.36. The circuit consists of an input differential amplifier utiliz-ing Q1 and Q2 as emitter followers for input buffering, and Q3 and Q4 as a differential pair with an emitter resistor R3. The two resistors R4 and R5 provide dc paths to ground for the base currents of Q1 and Q2, thus enabling the input signal source to be capacitively coupled to either of the two input terminals.
The differential amplifier transistors Q3 and Q4 are biased by two separate currents: Q3 is biased by a current from the dc supply VS through the diode-connected transistor Q10, and resis-tor R1; Q4 is biased by a dc current from the output terminal through R2. Under quiescent condi-tions (i.e., with no input signal applied) the two bias currents will be equal, and the current through and the voltage across R3 will be zero. For the emitter current of Q3 we can write where we have neglected the small dc voltage drop across R4. Assuming, for simplicity, all VEB to be equal, (11.76) For the emitter current of Q4 we have (11.77) 3The main objective of showing this circuit is to point out some interesting design features. The circuit is not a detailed schematic diagram of what is actually on the chip.
Figure 11.35 Thermal-shutdown circuit.
I3 V S V EB10 – V EB3 V EB1 – – R1 -------------------------------------------------------I3 V S 3V EB – R1 -----------------------I4 = V O V EB4 – V EB2 – R2 ---------------------------------------- VO 2VEB – R2 ------------------------11.9 IC Power Amplifiers 957 where VO is the dc voltage at the output, and we have neglected the small drop across R5.
Equating I3 and I4 and using the fact that R1 = 2R2 results in (11.78) Thus the output is biased at approximately half the power-supply voltage, as desired for maximum output voltage swing. An important feature is the dc feedback from the output to the emitter of Q4, through R2. This dc feedback acts to stabilize the output dc bias voltage at the value in Eq. (11.78). Qualitatively, the dc feedback functions as follows: If for some rea-son VO increases, a corresponding current increment will flow through R2 and into the emit-ter of Q4. Thus the collector current of Q4 increases, resulting in a positive increment in the voltage at the base of Q12. This, in turn, causes the collector current of Q12 to increase, thus bringing down the voltage at the base of Q8 and hence VO.
Continuing with the description of the circuit in Fig. 11.36, we observe that the dif-ferential amplifier (Q3, Q4) has a current mirror load composed of Q5 and Q6 (refer to Section 8.5 for a discussion of active loads). The single-ended output voltage signal of the first stage appears at the collector of Q6 and thus is applied to the base of the second-stage common-emitter amplifier Q12. Transistor Q12 is biased by the constant-current source Q11, which also acts as its active load. In actual operation, however, the load of Q12 will be dominated by the reflected resistance due to RL. Capacitor C provides frequency compensa-tion (see Chapter 10).
Figure 11.36 The simplified internal circuit of the LM380 IC power amplifier. (Courtesy National Semi-conductor Corporation.) D1 D2 V O 1 2 ---VS 1 2 ---V EB + = 958 Chapter 11 Output Stages and Power Amplifiers The output stage is class AB, utilizing a compound pnp transistor (Q8 and Q9). Nega-tive feedback is applied from the output to the emitter of Q4 via resistor R2. To find the closed-loop gain consider the small-signal equivalent circuit shown in Fig. 11.37. Here, we have replaced the second-stage common-emitter amplifier and the output stage with an invert-ing amplifier block with gain A. We shall assume that the amplifier A has high gain and high input resistance, and thus the input signal current into A is negligibly small. Under this assumption, Fig. 11.37 shows the analysis details with an input signal vi applied to the inverting input terminal. The order of the analysis steps is indicated by the circled numbers.
Note that since the input differential amplifier has a relatively large resistance, R3, in the emitter circuit, most of the applied input voltage appears across R3. In other words, the signal voltages across the emitter–base junctions of Q1, Q2, Q3, and Q4 are small in compari-son to the voltage across R3. Accordingly, the voltage gain can be found by writing a node equation at the collector of Q6: which yields Figure 11.37 Small-signal analysis of the circuit in Fig. 11.36. The circled numbers indicate the order of the analysis steps.
R1 vi R2 R4 Q1 Q3 Q5 R5 2 25 k 25 k R3 1 k 0 V 0 V vo vi vi 0 vi R1/2 vi vi R3 vi R3 vi R3 vi R3 vo R2 vo R3 R3 0 0 vi vo R2 Q4 Q2 Q6 A A 0 V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vi R3 -----vo R2 -----vi R3 -----+ + 0 = vo vi ----2R2 R3 ---------– 50 V/V – = 11.9 IC Power Amplifiers 959 As was demonstrated in Chapter 10, one of the advantages of negative feedback is the reduction of nonlinear distortion. This is the case in the circuit of the LM380.
The LM380 is designed to operate from a single supply VS in the range of 12 V to 22 V.
The selection of supply voltage depends on the value of RL and the required output power PL.
The manufacturer supplies curves for the device power dissipation versus output power for a given load resistance and various supply voltages. One such set of curves for RL = 8 Ω is shown in Fig. 11.38. Note the similarity to the class B power dissipation curve of Fig. 11.8.
In fact, the reader can easily verify that the location and value of the peaks of the curves in Fig. 11.38 are accurately predicted by Eqs. (11.20) and (11.21), respectively (where ). The line labeled “3% distortion level” in Fig. 11.38 is the locus of the points on the various curves at which the distortion (THD) reaches 3%. A THD of 3% represents the onset of peak clipping due to output-transistor saturation.
The manufacturer also supplies curves for maximum power dissipation versus temperature (derating curves) similar to those discussed in Section 11.7 for discrete power transistors.
Figure 11.38 Power dissipation (PD) versus output power (PL) for the LM380 with RL = 8 Ω. (Courtesy National Semiconductor Corporation.) 11.17 Denoting the total resistance between the collector of Q6 and ground by R, show, using Fig. 11.37, that which reduces to under the condition that AR R2.
vo vi ----2R2 – R3 ⁄ 1 R2 AR ⁄ ( ) + -------------------------------= 2R2 R3 ⁄ – ( ) EXERCISE V CC 1 2 ---V S = 960 Chapter 11 Output Stages and Power Amplifiers 11.9.2 Power Op Amps Figure 11.39 shows the general structure of a power op amp. It consists of a low-power op amp followed by a class AB buffer similar to that discussed in Section 11.8.1. The buffer consists of transistors Q1, Q2, Q3, and Q4, with bias resistors R1 and R2 and emitter degeneration resistors R5 and R6. The buffer supplies the required load current until the current increases to the point that the voltage drop across R3 (in the current-sourcing mode) becomes sufficiently large to turn Q5 on. Transistor Q5 then supplies the additional load current required. In the cur-rent-sinking mode, Q4 supplies the load current until sufficient voltage develops across R4 to turn Q6 on. Then, Q6 sinks the additional load current. Thus the stage formed by Q5 and Q6 acts as a current booster. The power op amp is intended to be used with negative feedback in the usual closed-loop configurations. A circuit based on the structure of Fig. 11.39 is commer-cially available from National Semiconductor as LH0101. This op amp is capable of provid-ing a continuous output current of 2 A, and with appropriate heat sinking can provide 40 W of output power (Wong and Johnson, 1981). The LH0101 is fabricated using hybrid thick-film technology. 11.9.3 The Bridge Amplifier We conclude this section with a discussion of a circuit configuration that is popular in high-power applications. This is the bridge-amplifier configuration shown in Fig. 11.40 utilizing two power op amps, A1 and A2. While A1 is connected in the noninverting configuration with a gain K = 1 + , A2 is connected as an inverting amplifier with a gain of equal magnitude K = . The load RL is floating and is connected between the output termi-nals of the two op amps.
If vI is a sinusoid with amplitude , the voltage swing at the output of each op amp will be , and that across the load will be . Thus, with op amps operated from ±15-V supplies and capable of providing, say a ±12-V output swing, an output swing of ±24 V can be obtained across the load of the bridge amplifier. 11.18 The manufacturer specifies that for ambient temperatures below 25°C the LM380 can dissipate a maximum of 3.6 W. This is obtained under the condition that its dual-in-line package be soldered onto a printed-circuit board in close thermal contact with 6 square inches of 2-ounce copper foil.
Above TA = 25°C, the thermal resistance is θJA = 35°C/W. TJmax is specified to be 150°C. Find the maximum power dissipation possible if the ambient temperature is to be 50°C.
Ans. 2.9 W D11.19 It is required to use the LM380 to drive an 8-Ω loudspeaker. Use the curves of Fig. 11.38 to determine the maximum power supply possible while limiting the maximum power dissipation to the 2.9 W de-termined in Exercise 11.18. If for this application a 3% THD is allowed, find PL and the peak-to-peak output voltage.
Ans. 20 V; 4.2 W; 16.4 V EXERCISES R2 R1 ⁄ ( ) R4 R3 ⁄ Vi ˆ KVi ˆ ± 2KVi ˆ ± 11.9 IC Power Amplifiers 961 Figure 11.39 Structure of a power op amp. The circuit consists of an op amp followed by a class AB buffer similar to that discussed in Section 11.8.1. The output current capability of the buffer, consisting of Q1, Q2, Q3, and Q4, is further boosted by Q5 and Q6.
Figure 11.40 The bridge-amplifier configuration.
KVi vO2 A2 0 t RL A1 R2 vI vO vO1 R1 R3 R4 Vi 0 t ˆ ˆ ˆ ˆ 2KVi 0 t vO2 vO1 KVi 0 t vO R3 R2 R1 1 K vI R4 962 Chapter 11 Output Stages and Power Amplifiers In designing bridge amplifiers, note should be taken of the fact that the peak current drawn from each op amp is . This effect can be taken into account by considering the load seen by each op amp (to ground) to be 11.10 MOS Power Transistors In this section we consider the structure, characteristics, and application of a special type of MOSFET suitable for high-power applications.
11.10.1 Structure of the Power MOSFET The MOSFET structure studied in Chapter 5 (Fig. 5.1) is not suitable for high-power applications. To appreciate this fact, recall that the drain current of an n-channel MOSFET operating in the saturation region is given by (11.79) It follows that to increase the current capability of the MOSFET, its width W should be made large and its channel length L should be made as small as possible. Unfortunately, however, reducing the channel length of the standard MOSFET structure results in a drastic reduction in its breakdown voltage. Specifically, the depletion region of the reverse-biased body-to-drain junction spreads into the short channel, resulting in breakdown at a relatively low voltage. Thus the resulting device would not be capable of handling the high voltages typical of power-transistor applications. For this reason, new structures had to be found for fabricating short-channel (1- to 2-μm) MOSFETs with high breakdown voltages.
At the present time the most popular structure for a power MOSFET is the double-diffused or DMOS transistor shown in Fig. 11.41. As indicated, the device is fabricated on a lightly doped n-type substrate with a heavily doped region at the bottom for the drain con-tact. Two diffusions4 are employed, one to form the p-type body region and another to form the n-type source region.
The DMOS device operates as follows. Application of a positive gate voltage, vGS, greater than the threshold voltage Vt, induces a lateral n channel in the p-type body region underneath the gate oxide. The resulting channel is short; its length is denoted L in Fig. 11.41. Current is then conducted by electrons from the source moving through the resulting short channel to the substrate and then vertically down the substrate to the drain. This should be contrasted with the lateral current flow in the standard small-signal MOSFET structure (Chapter 5).
4See Appendix A for a description of the IC fabrication process.
2KVi ˆ RL ⁄ RL 2.
⁄ 11.20 Consider the circuit of Fig. 11.40 with R1 = R3 = 10 kΩ, R2 = 5 kΩ, R4 = 15 kΩ, and RL = 8 Ω. Find the voltage gain and the input resistance. The power supply used is ±18 V. If vI is a 20-V peak-to-peak sine wave, what is the peak-to-peak output voltage? What is the peak load current? What is the load power?
Ans. 3 V/V; 10 kΩ; 60 V; 3.75 A; 56.25 W EXERCISE iD 1 2 ---μnCox W L -----⎝ ⎠ ⎛ ⎞vGS V – t ( ) 2 = 11.10 MOS Power Transistors 963 Even though the DMOS transistor has a short channel, its breakdown voltage can be very high (as high as 600 V). This is because the depletion region between the substrate and the body extends mostly in the lightly doped substrate and does not spread into the channel. The result is a MOS transistor that simultaneously has a high current capability (50 A is possible) as well as the high breakdown voltage just mentioned. Finally, we note that the vertical struc-ture of the device provides efficient utilization of the silicon area.
An earlier structure used for power MOS transistors deserves mention. This is the V-groove MOS device [see Severns (1984)]. Although still in use, the V-groove MOSFET has lost appli-cation ground to the vertical DMOS structure of Fig. 11.41, except possibly for high-frequency applications. Because of space limitations, we shall not describe the V-groove MOSFET.
11.10.2 Characteristics of Power MOSFETs In spite of their radically different structure, power MOSFETs exhibit characteristics that are quite similar to those of the small-signal MOSFETs studied in Chapter 5. Important dif-ferences exist, however, and these are discussed next.
Power MOSFETs have threshold voltages in the range of 2 V to 4 V. In saturation, the drain current is related to vGS by the square-law characteristic of Eq. (11.80). However, as shown in Fig. 11.42, the iD–vGS characteristic becomes linear for larger values of vGS. The lin-ear portion of the characteristic occurs as a result of the high electric field along the short channel, causing the velocity of charge carriers to reach an upper limit, a phenomenon known as velocity saturation5. The linear iD–vGS relationship implies a constant gm in the velocity-saturation region.
The iD−vGS characteristic shown in Fig. 11.42 includes a segment labeled “subthreshold.” Though of little significance for power devices, the subthreshold region of operation is of interest in very-low-power applications (see Section 5.1.9). 5Velocity saturation occurs also in standard MOSFET structures when the channel length is in the sub-micron range. We shall discuss velocity saturation in some detail in Section 13.5.
Source Gate SiO2 Source n n n n p p Body Substrate Current flow Drain L Figure 11.41 Double-diffused vertical MOS transistor (DMOS). 964 Chapter 11 Output Stages and Power Amplifiers 11.10.3 Temperature Effects Of considerable interest in the design of MOS power circuits is the variation of the MOSFET characteristics with temperature, illustrated in Fig. 11.43. Observe that there is a value of vGS (in Figure 11.42 Typical iD–vGS characteristic for a power MOSFET.
Figure 11.43 The iD–vGS characteristic curve of a power MOS transistor (IRF 630, Siliconix) at case tem-peratures of –55°C, +25°C, and +125°C. (Courtesy of Siliconix Inc.) 11.10 MOS Power Transistors 965 the range of 4 V to 6 V for most power MOSFETs) at which the temperature coefficient of iD is zero. At higher values of vGS, iD exhibits a negative temperature coefficient. This is a significant property: It implies that a MOSFET operating beyond the zero-temperature-coefficient point does not suffer from the possibility of thermal runaway. This is not the case, however, at low currents (i.e., lower than the zero-temperature-coefficient point). In the (relatively) low-current region, the temperature coefficient of iD is positive, and the power MOSFET can easily suffer thermal runaway (with unhappy consequences). Since class AB output stages are biased at low currents, means must be provided to guard against thermal runaway.
The reason for the positive temperature coefficient of iD at low currents is that vOV = (vGS −Vt) is relatively low, and the temperature dependence is dominated by the negative temperature coefficient of Vt (in the range of –3 mV/°C to –6 mV/°C) which causes vOV to rise with temperature.
11.10.4 Comparison with BJTs The power MOSFET does not suffer from second breakdown, which limits the safe operating area of BJTs. Also, power MOSFETs do not require the large dc base-drive currents of power BJTs. Note, however, that the driver stage in a MOS power amplifier should be capable of supplying sufficient current to charge and discharge the MOSFET’s large and nonlinear input capacitance in the time allotted. Finally, the power MOSFET features, in general, a higher speed of operation than the power BJT. This makes MOS power transistors especially suited to switching applications—for instance, in motor-control circuits.
11.10.5 A Class AB Output Stage Utilizing Power MOSFETs As an application of power MOSFETs, we show in Fig. 11.44 a class AB output stage utilizing a pair of complementary MOSFETs and employing BJTs for biasing and in the driver stage.
The latter consists of complementary Darlington emitter followers formed by Q1 through Q4 and has the low output resistance necessary for driving the output MOSFETs at high speeds.
Of special interest in the circuit of Fig. 11.44 is the bias circuit utilizing two VBE multipli-ers formed by Q5 and Q6 and their associated resistors. Transistor Q6 is placed in direct ther-mal contact with the output transistors; this is achieved by simply mounting Q6 on their common heat sink. Thus, by the appropriate choice of the VBE multiplication factor of Q6, the bias voltage VGG (between the gates of the output transistors) can be made to decrease with temperature at the same rate as that of the sum of the threshold voltages of the output MOSFETs. In this way the overdrive voltages and hence the quiescent current of the output transistors can be stabilized against temperature variations.
Analytically, VGG is given by Since VBE6 is thermally coupled to the output devices while the other BJTs remain at con-stant temperature, we have which is the relationship needed to determine R3/R4 so that .
The other VBE multiplier is then adjusted to yield the value of VGG required for the desired quiescent current in QN and QP.
V tN V tP + ( ) V GG 1 R3 R4 -----+ ⎝ ⎠ ⎛ ⎞V BE6 1 R1 R2 -----+ ⎝ ⎠ ⎛ ⎞V BE5 4V BE – + = V GG ∂ T ∂ -----------1 R3 R4 -----+ ⎝ ⎠ ⎛ ⎞V BE6 ∂ T ∂ -------------= V GG/ T ∂ V tN + V tP ( ) ∂ = / T ∂ ∂ 966 Chapter 11 Output Stages and Power Amplifiers Figure 11.44 A class AB amplifier with MOS output transistors and BJT drivers. Resistor R3 is adjusted to provide temperature compensation while R1 is adjusted to yield the desired value of quiescent current in the output transistors. Resistors RG are used to suppress parasitic oscillations at high frequencies. Typically, RG = 100 Ω.
IBIAS 11.21 For the circuit in Fig. 11.44, find the ratio R3/R4 that provides temperature stabilization of the qui-escent current in QN and QP. Assume that changes at −3 mV/°C and that Ans. 2 11.22 For the circuit in Fig. 11.44 assume that the BJTs have a nominal VBE of 0.7 V and that the MOS-FETs have and It is required to establish a quiescent current of 100 mA in the output stage and 20 mA in the driver stage. Find , VGG, R, and . Use the value of R3 / R4 found in Exercise 11.21. Assume that the MOSFETs are represented by their square-law iD–vGS characteristics.
Ans. 3.32 V; 6.64 V; 332 Ω; 9.5 Vt VBE T 2 mV/°C.
– = ∂ ⁄ ∂ Vt 3 V = μnCox W L ⁄ ( ) 2 A/V 2.
= VGS R1 R2 ⁄ EXERCISES 11.10 MOS Power Transistors 967 Summary Output stages are classified according to the transistor conduction angle: class A (360°), class AB (slightly more than 180°), class B (180°), and class C (less than 180°).
The most common class A output stage is the emitter follower. It is biased at a current greater than the peak load current.
The class A output stage dissipates its maximum power under quiescent conditions (vO = 0). It achieves a maxi-mum power-conversion efficiency of 25%.
The class B stage is biased at zero current, and thus dis-sipates no power in quiescence.
The class B stage can achieve a power conversion effi-ciency as high as 78.5%. It dissipates its maximum power for .
The class B stage suffers from crossover distortion.
The class AB output stage is biased at a small current; thus both transistors conduct for small input signals, and crossover distortion is virtually eliminated.
Except for an additional small quiescent power dissipa-tion, the power relationships of the class AB stage are similar to those in class B.
To guard against the possibility of thermal runaway, the bias voltage of the class AB circuit is made to vary with temperature in the same manner as does VBE of the out-put transistors.
The classical CMOS class AB output stage suffers from reduced output signal-swing. This problem can be over-come by replacing the source-follower output transis-tors with a pair of complementary devices operating in the common-source configuration.
The CMOS class AB output stage with common-source transistors allows the output voltage to swing to within an overdrive voltage from each of the two power supplies. Utilizing error amplifiers in the feedback path of each of the output transistors reduces both the output resistance and gain error of the stage.
To facilitate the removal of heat from the silicon chip, power devices are usually mounted on heat sinks. The maximum power that can be safely dissipated in the device is given by where TJmax and θJC are specified by the manufacturer, while θCS and θSA depend on the heat-sink design.
Use of the Darlington configuration in the class AB out-put stage reduces the base-current drive requirement. In integrated circuits, the compound pnp configuration is commonly used.
Output stages are usually equipped with circuitry that, in the event of a short circuit, can turn on and limit the base-current drive, and hence the emitter current, of the output transistors.
IC power amplifiers consist of a small-signal voltage amplifier cascaded with a high-power output stage.
Overall feedback is applied either on-chip or externally.
The bridge amplifier configuration provides, across a floating load, a peak-to-peak output voltage which is twice that possible from a single amplifier with a grounded load.
The DMOS transistor is a short-channel power device capable of both high-current and high-voltage opera-tion.
The drain current of a power MOSFET exhibits a posi-tive temperature coefficient at low currents, and thus the device can suffer thermal runaway. At high currents the temperature coefficient of iD is negative.
V ˆ o 2 π ⁄ ( )V CC = P Dmax T Jmax T A – θJC θCS θSA + + -------------------------------------= PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multism simu-lations for all the indicated problems can be found in the corresponding files on the disc. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 11.2: Class A Output Stage 11.1 A class A emitter follower, biased using the circuit shown in Fig. 11.2, uses VCC = 5 V, R = RL = 1 kΩ, with all transistors (including Q3) identical. Assume VBE = 0.7 V, VCEsat = 0.3 V, and β to be very large. For linear operation, what are the upper and lower limits of output voltage, and the corresponding inputs? How do these values change if the emitter–base junction area of Q3 is made twice as big as that of Q2? Half as big?
11.2 A source-follower circuit using NMOS transistors is constructed following the pattern shown in Fig. 11.2. All three transistors used are identical, with Vt = 1 V and μnCox = 20 mA/V2; VCC = 5 V, R = RL = 1 kΩ. For linear operation, what are the upper and lower limits of the output voltage, and the corresponding inputs?
D 11.3 Using the follower configuration shown in Fig. 11.2 with ±9-V supplies, provide a design capable of ±7-V out-puts with a 1-kΩ load, using the smallest possible total sup-ply current. You are provided with four identical, high-β BJTs and a resistor of your choice.
D 11.4 An emitter follower using the circuit of Fig. 11.2, for which the output voltage range is ±5 V, is required using VCC = 10 V. The circuit is to be designed such that the cur-rent variation in the emitter-follower transistor is no greater than a factor of 10, for load resistances as low as 100 Ω.
What is the value of R required? Find the incremental volt-age gain of the resulting follower at vO = +5, 0, and –5 V, with a 100-Ω load. What is the percentage change in gain over this range of vO?
11.5 Consider the operation of the follower circuit of Fig. 11.2 for which when driven by a square wave such that the output ranges from +VCC to −VCC (ignoring VCEsat). For this situation, sketch the equivalent of Fig. 11.4 for vO, iC1, and pD1. Repeat for a square-wave output that has peak levels of What is the average power dissipation in Q1 in each case? Compare these results to those for sine waves of peak amplitude VCC and respectively.
11.6 Consider the situation described in Problem 11.5. For square-wave outputs having peak-to-peak values of 2VCC and VCC, and for sine waves of the same peak-to-peak values, find the average power loss in the current-source transistor Q2.
11.7 Reconsider the situation described in Exercise 11.3 for variation in VCC—specifically for VCC = 16 V, 12 V, 10 V, and 8 V. Assume VCEsat is nearly zero. What is the power-conversion efficiency in each case?
Section 11.3: Class B Output Stage 11.8 Consider the circuit of a complementary-BJT class B output stage. For what amplitude of input signal does the crossover distortion represent a 10% loss in peak amplitude?
11.9 Consider the feedback configuration with a class B output stage shown in Fig. 11.9. Let the amplifier gain A0 = 100 V/V. Derive an expression for vO versus vI, assuming that Sketch the transfer characteristic vO ver-sus vI, and compare it with that without feedback.
11.10 Consider the class B output stage, using enhancement MOSFETs, shown in Fig. P11.10. Let the devices have and μCox = 2 mA/V2. With a 10-kHz sine-wave input of 5-V peak and a high value of load resistance, what peak output would you expect? What fraction of the sine-wave period does the crossover interval represent? For what value of load resistor is the peak output voltage reduced to half the input?
11.11 Consider the complementary-BJT class B output stage and neglect the effects of finite VBE and VCEsat. For ±10-V power supplies and a 100-Ω load resistance, what is the maxi-mum sine-wave output power available? What supply power corresponds? What is the power-conversion efficiency? For output signals of half this amplitude, find the output power, the supply power, and the power-conversion efficiency.
D 11.12 A class B output stage operates from ±5-V supplies.
Assuming relatively ideal transistors, what is the output voltage W L ⁄ RL V CC I, ⁄ = V ± CC 2.
⁄ V CC 2 ⁄ , V BE 0.7 V.
= Vt 0.5 V = W L ⁄ 5 V 5 V Figure P11.10 Problems 969 CHAPTER 11 PROB LEMS for maximum power-conversion efficiency? What is the output voltage for maximum device dissipation? If each of the output devices is individually rated for 1-W dissipation, and a factor-of-2 safety margin is to be used, what is the smallest value of load resistance that can be tolerated, if operation is always at full output voltage? If operation is allowed at half the full out-put voltage, what is the smallest load permitted? What is the greatest possible output power available in each case?
D 11.13 A class B output stage is required to deliver an average power of 100 W into a 16-Ω load. The power supply should be 4 V greater than the corresponding peak sine-wave output voltage.
Determine the power-supply voltage required (to the nearest volt in the appropriate direction), the peak current from each supply, the total supply power, and the power-conver-sion efficiency. Also, determine the maximum possible power dissipation in each transistor for a sine-wave input.
11.14 Consider the class B BJT output stage with a square-wave output voltage of amplitude across a load RL and employing power supplies ±VSS. Neglecting the effects of finite VBE and VCEsat, determine the load power, the supply power, the power-conversion efficiency, the maximum attainable power-conversion efficiency and the correspond-ing value of and the maximum available load power.
Also find the value of at which the power dissipation in the transistors reaches its peak, and the corresponding value of power-conversion efficiency.
Section 11.4: Class AB Output Stage D 11.15 Design the quiescent current of a class AB BJT output stage so that the incremental voltage gain for vI in the vicinity of the origin is in excess of 0.98 V/V for loads larger than 100 Ω. Assume that the BJTs have VBE of 0.7 V at a current of 100 mA and determine the value of VBB required.
11.16 For the class AB output stage considered in Example 11.3, add two columns to the table of results as follows: the total input current drawn from ( , mA); and the large-sig-nal input resistance . Assume . Compare the values of to the approximate value obtained using the resistance reflection rule, 11.17 In this problem we investigate an important trade-off in the design of the class AB output stage of Fig. 11.11: Increasing the quiescent current reduces the nonlinearity of the transfer characteristic at the expense of increased qui-escent power dissipation. As a measure of nonlinearity, we use the maximum deviation of the stage incremental gain, which occurs at , namely (a) Show that is given by which for can be approximated by (b) If the stage is operated from power supplies of , find the quiescent power dissipation, .
(c) Show that for given and , the product of the qui-escent power dissipation and the gain error is a constant given by (d) For V and , find the required values of and if is to be 5%, 2%, and 1%.
11.18 A class AB output stage, resembling that in Fig. 11.11 but utilizing a single supply of +10 V and biased at VI = 6 V, is capacitively coupled to a 100-Ω load. For transistors for which at 1 mA and for a bias voltage VBB = 1.4 V, what quiescent current results? For a step change in output from 0 to –1 V, what input step is required? Assum-ing transistor saturation voltages of zero, find the largest possible positive-going and negative-going steps at the output.
Section 11.5: Biasing the Class AB Circuit D 11.19 Consider the diode-biased class AB circuit of Fig. 11.14. For IBIAS = 100 μA, find the relative size (n) that should be used for the output devices (in comparison to the biasing devices) to ensure that an output resistance of 10 Ω or less is obtained in the quiescent state. Neglect the resistance of the biasing diodes.
D 11.20 A class AB output stage using a two-diode bias network as shown in Fig. 11.14 utilizes diodes having the same junction area as the output transistors. For VCC = 10 V, IBIAS = 0.5 mA, RL = 100 Ω, βN = 50, and what is the quiescent current? What are the largest possible positive and negative output signal levels? To achieve a pos-itive peak output level equal to the negative peak level, what value of βN is needed if IBIAS is not changed? What value of IBIAS is needed if βN is held at 50? For this value, what does IQ become?
11.21 A class AB output stage using a two-diode bias network as shown in Fig. 11.14 utilizes diodes having the same junction area as the output transistors. At a room tem-perature of about 20°C the quiescent current is 1 mA and Through a manufacturing error, the thermal coupling between the output transistors and the biasing diode-connected transistors is omitted. After some output activity, the output devices heat up to 70°C while the bias-ing devices remain at 20°C. Thus, while the VBE of each device remains unchanged, the quiescent current in the out-put devices increases. To calculate the new current value, recall that there are two effects: IS increases by about and changes, where T = (273° + V ˆo V ˆo, V ˆ o vI iI Rin vI iI ⁄ ≡ βN βP = = β 49 = Rin Rin βRL.
IQ vO 0 = ε 1 vo vi vO 0 = ⁄ – = ε ε VT 2IQ ⁄ RL VT 2IQ ⁄ ( ) + ------------------------------------= 2IQRL VT ε VT 2IQ ⁄ RL 2 ± VCC PD VCC RL εPD VT VCC RL ---------⎝ ⎠ ⎛ ⎞ VCC 15 = RL 100 Ω = PD IQ ε V BE 0.7 V = V CEsat 0 V, = V BE 0.6 V.
= 14%/°C VT kT/q = CHAPTER 11 P RO BL E MS 970 Chapter 11 Output Stages and Power Amplifiers temperature in °C), and VT = 25 mV only at 20°C. However, you may assume that βN remains almost constant. This assumption is based on the fact that β increases with tem-perature but decreases with current. What is the new value of IQ? If the power supply is ±20 V, what additional power is dissipated? If thermal runaway occurs, and the tempera-ture of the output transistors increases by 10°C for every watt of additional power dissipation, what additional tem-perature rise and current increase result?
D 11.22 Repeat Example 11.5 for the situation in which the peak positive output current is 200 mA. Use the same gen-eral approach to safety margins. What are the values of R1 and R2 you have chosen?
11.23 A VBE multiplier is designed with equal resistances for nominal operation at a terminal current of 1 mA, with half the current flowing in the bias network. The initial design is based on β = ∞ and VBE = 0.7 V at 1 mA.
(a) Find the required resistor values and the terminal voltage.
(b) Find the terminal voltage that results when the terminal current increases to 2 mA. Assume β = ∞.
(c) Repeat (b) for the case the terminal current becomes 10 mA.
(d) Repeat (c) using the more realistic value of β = 100.
Section 11.6: CMOS Class AB Output Stages D 11.24 (a) Show that for the class AB circuit in Fig. 11.17, the small-signal output resistance in the quiescent state is given by which for matched devices becomes (b) For a circuit that utilizes MOSFETs with and find the voltage that results in D 11.25 (a) For the circuit in Fig. 11.17 in which and are matched, and and are matched, show that the small-signal voltage gain at the quiescent condition is given by where is the transconductance of each of and and where channel-length modulation is neglected.
(b) For the case , , kn = kp = nk1 = nk2, where k = μCox(W/L), and find the ratio n that results in an incremental gain of 0.98. Also find the quiescent current .
D 11.26 Design the circuit of Fig. 11.17 to operate at IQ = with . Let , , , and . Design so that and are matched and and are matched, and that in the quiescent state each operates at an overdrive voltage of 0.2 V.
(a) Specify the W/L ratio for each of the four transistors.
(b) In the quiescent state with , what must be?
(c) If is required to supply a maximum load current of 10 mA, find the maximum allowable output voltage.
Assume that the transistor supplying needs a mini-mum of 0.2 V to operate properly.
11.27 For the CMOS output stage of Fig. 11.19 with for each of and at the quiescent point, and find the output resistance at the quiescent point.
11.28 (a) Show that for the CMOS output stage of Fig. 11.19, (b) For a stage that drives a load resistance of 100 with a gain error of less than 5%, find the overdrive voltage at which and should be operated. Let and .
D 11.29 It is required to design the circuit of Fig. 11.19 to drive a load resistance of 50 while exhibiting an output resistance, around the quiescent point, of 2.5 . Operate and at and V. The technology utilized is specified to have , and VDD = VSS = 2.5 V.
(a) Specify (W/L) for each of and (b) Specify the required value of (c) What is the expected error in the stage gain?
(d) In the quiescent state, what dc voltage must appear at the output of each of the error amplifiers?
(e) At what value of positive will be supplying all the load current? Repeat for negative and supplying all the load current.
(f) What is the linear range of ?
Section 11.7: Power BJTS D 11.30 A particular transistor having a thermal resis-tance θJA = 2°C/W is operating at an ambient temperature of 30°C with a collector–emitter voltage of 20 V. If long life requires a maximum junction temperature of 130°C, what is the corresponding device power rating? What is the greatest average collector current that should be considered?
11.31 A particular transistor has a power rating at 25°C of 200 mW, and a maximum junction temperature of 150°C.
What is its thermal resistance? What is its power rating when operated at an ambient temperature of 70°C? What is Rout 1 gmn gmp + -----------------------= Rout 1 2gm ---------= Vt 0.7 V = k′ W L ⁄ ( ) 200 mA V2, ⁄ = VGG Rout 10 Ω.
= Q1 Q2 QN QP vo vi ----RL RL 2 gm ⁄ ( ) + ------------------------------= gm QN QP IBIAS 0.1 mA = RL 1 kΩ = k1 20 mA V2, ⁄ = IQ 1 mA IBIAS 0.1 mA = μnCox = 250 μA V2 ⁄ μpCox 100 μA V2 ⁄ = Vtn Vtp = – = 0.45 V VDD = VSS 2.5 V = Q1 Q2 QN QP vO 0 = vI QN IBIAS IQ 3 mA, = VOV 0.15 V = QP QN μ 5, = Gain error Rout RL ---------= Ω QP QN IQ 1 mA = μ 10 = Ω Ω QN QP IQ 1.5 mA = VOV 0.15 = kn ′ 250 μA V2, ⁄ = kp ′ 100 μA V2, ⁄ = Vtn Vtp 0.5 V = – = QN QP.
μ.
vO QP vO QN vO Problems 971 CHAPTER 11 PROB LEMS its junction temperature when dissipating 100 mW at an ambient temperature of 50°C?
11.32 A power transistor operating at an ambient temperature of 50°C, and an average emitter current of 3 A, dissipates 30 W. If the thermal resistance of the transistor is known to be less than 3°C/W, what is the greatest junction temperature you would expect? If the transistor VBE measured using a pulsed emitter current of 3 A at a junction temperature of 25°C is 0.80 V, what average VBE would you expect under normal oper-ating conditions? (Use a temperature coefficient of –2 mV/°C.) 11.33 For a particular application of the transistor specified in Example 11.7, extreme reliability is essential. To improve reliability, the maximum junction temperature is to be lim-ited to 100°C. What are the consequences of this decision for the conditions specified?
11.34 A power transistor is specified to have a maximum junction temperature of 130°C. When the device is operated at this junction temperature with a heat sink, the case temper-ature is found to be 90°C. The case is attached to the heat sink with a bond having a thermal resistance θCS = 0.5°C/W and the thermal resistance of the heat sink θSA = 0.1°C/W. If the ambient temperature is 30°C what is the power being dissipated in the device? What is the thermal resistance of the device, θJC, from junction to case?
11.35 A power transistor for which TJmax = 180°C can dissi-pate 50 W at a case temperature of 50°C. If it is connected to a heat sink using an insulating washer for which the thermal resistance is 0.6°C/W, what heat-sink temperature is necessary to ensure safe operation at 30 W? For an ambient temperature of 39°C, what heat-sink thermal resistance is required? If, for a particular extruded-aluminum-finned heat sink, the thermal resistance in still air is 4.5°C/W per centi-meter of length, how long a heat sink is needed?
Section 11.8: Variations on the Class AB Configuration 11.36 Use the results given in the answer to Exercise 11.14 to determine the input current of the circuit in Fig. 11.30 for vI = 0 and ±10 V with infinite and 100-Ω loads.
11.37 For the circuit in Fig 11.30 when operated near and fed with a signal source having zero resistance, show that the output resistance is given by Assume that the top and bottom halves of the circuit are per-fectly matched.
D 11.38 Consider the circuit of Fig. 11.30 in which Q1 and Q2 are matched, and Q3 and Q4 are matched but have three times the junction area of the others. For VCC = 10 V, find values for resistors R1 through R4 which allow for a base current of at least 10 mA in Q3 and Q4 at vI = +5 V (when a load demands it) with at most a 2-to-1 variation in currents in Q1 and Q2, and a no-load quiescent current of 40 mA in Q3 and Q4; , and For input voltages around 0 V, estimate the output resistance of the overall follower driven by a source having zero resistance. For an input volt-age of +1 V and a load resistance of 2 Ω, what output voltage results? Q1 and Q2 have of 0.7 V at a current of 10 mA.
11.39 Figure P11.39 shows a variant of the class AB circuit of Fig. 11.30. Assume that all four transistors are matched and have (a) For , find the quiescent current in and , the input current , and the output voltage (b) Since the circuit has perfect symmetry, the small-signal per-formance around can be determined by considering either the top or bottom half of the circuit only. In this case, the load on the half-circuit must be the input resistance found is and the output resistance found is Using this approach, find , , and (assuming that the circuit is fed with a zero-resistance source).
11.40 For the Darlington configuration shown in Fig.
11.31, show that for and : (a) The equivalent composite transistor has (b) If the composite transistor is operated at a current , then will be operating at a collector current approximately vI 0 = Rout 1 2 --- R3 re3 R1 re1 || ( ) β3 1 + ( ) ⁄ + + [ ] = β1 2 , 150 ≥ β3 4 , 50.
≥ V BE β 100.
= Q3 vI vO iI VCC 1 mA Q4 Q1 VCC V CC VCC 1 mA Q2 RL 100 Figure P11.39 vI 0 = Q3 Q4 iI vO.
vI 0 = 2RL, 2Rin, 2Rout.
Rin vo vi ⁄ Rout β 1 1 β 2 1 β β 1β 2.
IC Q2 CHAPTER 11 P RO BL E MS 972 Chapter 11 Output Stages and Power Amplifiers equal to and will be operating at a collector current approximately equal to .
(c) The composite transistor has a , where is the saturation current of each of and (d) The composite transistor has an equivalent (e) The composite transistor has an equivalent 11.41 For the circuit in Fig. P11.41 in which the transistors have V and : (a) Find the dc collector current for each of and (b) Find the small-signal current that results from an input signal , and hence find the voltage gain (c) Find the input resistance 11.42 The BJTs in the circuit of Fig. P11.42 have βP = 10, βN = 100, , and (a) Find the dc collector current of each transistor and the value of VC.
(b) Replacing each BJT with its hybrid-π model, show that (c) Find the values of and Rin.
D 11.43 Consider the compound-transistor class AB out-put stage shown in Fig. 11.33 in which Q2 and Q4 are matched transistors with VBE = 0.7 V at 10 mA and β = 100, Q1 and Q5 have VBE = 0.7 V at 1-mA currents and β = 100, and Q3 has VEB = 0.7 V at a 1-mA current and β = 10. Design the circuit for a quiescent current of 2 mA in Q2 and Q4, IBIAS that is 100 times the standby base current in Q1, and a cur-rent in Q5 that is nine times that in the associated resistors.
Find the values of the input voltage required to produce out-puts of ±10 V for a 1-kΩ load. Use VCC of 15 V.
11.44 Repeat Exercise 11.16 for a design variation in which transistor Q5 is increased in size by a factor of 10, all other conditions remaining the same.
11.45 Repeat Exercise 11.16 for a design in which the limiting output current and normal peak current are 50 mA and 33.3 mA, respectively.
D 11.46 The circuit shown in Fig. P11.46 operates in a manner analogous to that in Fig. 11.35 to limit the output current from Q3 in the event of a short circuit or other mis-hap. It has the advantage that the current-sensing resistor R does not appear directly at the output. Find the value of R that causes Q5 to turn on and absorb all of IBIAS = 2 mA, when the current being sourced reaches 150 mA. For Q5, IC, Q1 IC β2 ⁄ VBE 2VT ln IC IS ⁄ ( ) VT ln β2 ( ) – IS Q1 Q2.
rπ 2β1β2 VT IC ⁄ ( ).
gm 1 2 --- IC VT ⁄ ( ).
VBE 0.7 = β 100 = Q2 vo 1 M 1 k Q1 Rin 5 V vi ic Figure P11.41 Q1 Q2.
ic vi vo vi.
⁄ Rin.
V BE 0.7 V = V A 100 V.
= vo vi ----- gm1 ro1 β || N ro2 Rf || ( ) [ ] vo vi ⁄ Figure P11.42 IBIAS Figure P11.46 Problems 973 CHAPTER 11 PROB LEMS IS = 10−14 A. If the normal peak output current is 100 mA, find the voltage drop across R and the collector current in Q5.
D 11.47 Consider the thermal shutdown circuit shown in Fig. 11.35. At 25°C, Z1 is a 6.8-V zener diode with a TC of 2 mV/°C, and Q1 and Q2 are BJTs that display VBE of 0.7 V at a current of 100 μA and have a TC of −2 mV/°C. Design the circuit so that at 125°C, a current of 100 μA flows in each of Q1 and Q2. What is the current in Q2 at 25°C?
Section 11.9: IC Power Amplifiers D 11.48 In the power-amplifier circuit of Fig. 11.36 two resistors are important in controlling the overall voltage gain. Which are they? Which controls the gain alone?
Which affects both the dc output level and the gain? A new design is being considered in which the output dc level is approximately (rather than approximately ) with a gain of 50 (as before). What changes are needed?
11.49 Consider the front end of the circuit in Fig. 11.36.
For VS = 20 V, calculate approximate values for the bias cur-rents in Q1 through Q6. Assume βnpn = 100, βpnp = 20, and Also find the dc voltage at the output.
11.50 It is required to use the LM380 power amplifier to drive an 8-Ω loudspeaker while limiting the maximum possible device dissipation to 1.5 W. Use the graph of Fig. 11.38 to determine the maximum possible power-supply voltage that can be used. (Use only the given graphs; do not interpolate.) If the maximum allowed THD is to be 3%, what is the maximum possible load power? To deliver this power to the load what peak-to-peak out-put sinusoidal voltage is required?
D 11.51 Consider the power-op-amp output stage shown in Fig. 11.39. Using a ±15-V supply, provide a design that provides an output of ±11 V or more, with currents up to ±20 mA pro-vided primarily by Q3 and Q4 with a 10% contribution by Q5 and Q6, and peak output currents of 1 A at full output (+11 V). As the basis of an initial design, use β = 50 and for all devices at all currents. Also use R5 = R6 = 0.
11.52 For the circuit in Fig. P11.52, assuming all transis-tors to have large β, show that [This voltage-to-current converter is an application of a versatile circuit building block known as the current conveyor; see Sedra and Roberts (1990)]. For β = 100, by what approximate per-centage is iO actually lower than this ideal value?
D 11.53 For the bridge amplifier of Fig. 11.40, let R1 = R3 = 10 kΩ. Find R2 and R4 to obtain an overall gain of 10.
D 11.54 An alternative bridge amplifier configuration, with high input resistance, is shown in Fig. P11.54. (Note the sim-ilarity of this circuit to the front end of the instrumentation amplifier circuit shown in Fig. 2.20b.) What is the gain For op amps (using ±15-V supplies) that limit at ±13 V, what is the largest sine wave you can provide across RL? Using 1 kΩ as the smallest resistor, find resistor values that make Make sure that the signals at the outputs of the two amplifiers are complementary.
Section 11.10: MOS Power Transistors D 11.55 Consider the design of the class AB amplifier of Fig. 11.44 under the following conditions: μCox = 200 β is high, IQN = IQP = IR = 10 mA, IBIAS = 100 μA, R2 = R4, the temperature coefficient of VBE = −2 mV/°C, and the temperature coefficient of Vt = −3 mV/°C in the low-current region. Find the values of R, R1, R2, R3, and R4.
Assume Q6, QP, and QN to be thermally coupled. (RG, used to suppress parisitic oscillation at high frequency, is usu-ally 100 or so.) 1 3 ---V S 1 2 ---V S V BE 0.7 V.
= VBE 0.7 V = iO vI R.
⁄ = Figure P11.52 vO vI ⁄ ?
vO vI ⁄ 10 V/V.
= Figure P11.54 Vt = 2 V, W L ⁄ mA/V 2, VBE 0.7 V, = IQ5 IQ6 I = BIAS 2 ⁄ , = Ω CHAPTER 12 Operational-Amplifier Circuits Introduction 975 12.1 The Two-Stage CMOS Op Amp 976 12.2 The Folded-Cascode CMOS Op Amp 991 12.3 The 741 Op-Amp Circuit 1002 12.4 DC Analysis of the 741 1006 12.5 Small-Signal Analysis of the 741 1013 12.6 Gain, Frequency Response, and Slew Rate of the 741 1026 12.7 Modern Techniques for the Design of BJT Op Amps 1031 Summary 1050 Problems 1051 975 IN THIS CHAPTER YOU WILL LEARN 1. The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded-cascode circuit.
2. The complete circuit of an analog IC classic: the 741 op amp. Though 40 years old, the 741 circuit includes so many interesting and useful design techniques that its study is still a must.
3. Interesting and useful applications of negative feedback within op-amp circuits to achieve bias stability and increased CMRR.
4. How to break a large analog circuit into its recognizable blocks, to be able to make the analysis amenable to a pencil-and-paper approach, which is the best way to learn design.
5. Some of the modern techniques employed in the design of low-voltage, single-supply BJT op amps.
6. Most importantly, how the different topics we learned about in the pre-ceding chapters come together in the design of the most important analog IC, the op amp.
Introduction In this chapter, we shall study the internal circuitry of the most important analog IC, namely, the operational amplifier. The terminal characteristics and some circuit applications of op amps were covered in Chapter 2. Here, our objective is to expose the reader to some of the ingenious techniques that have evolved over the years for combining elementary analog cir-cuit building blocks to realize a complete op amp. We shall study both CMOS and bipolar op amps. The CMOS op-amp circuits considered find application primarily in the design of analog and mixed-signal VLSI circuits. Because these op amps are usually designed with a specific application in mind, they can be optimized to meet a subset of the list of desired specifications, such as high dc gain, wide bandwidth, or large output-signal swing. For instance, many CMOS op amps are utilized within an IC and do not connect to the outside terminals of the chip. As a result, the loads on their outputs are usually limited to small capacitances of at most few picofarads. Internal CMOS op amps therefore do not need to have low output resistances, and their design rarely incorporates an output stage. Also, if the op-amp input terminals are not connected to the chip terminals, there will be no danger of static charge damaging the gate oxide of the input MOSFETs. Hence, internal CMOS op amps do not need input clamping diodes for gate protection and thus do not suffer from the 976 Chapter 12 Operational-Amplifier Circuits leakage effects of such diodes. In other words, the advantage of near-infinite input resistance of the MOSFET is fully realized.
While CMOS op amps are extensively used in the design of VLSI systems, the BJT remains the device of choice in the design of general-purpose op amps. These are op amps that are utilized in a wide variety of applications and are designed to fit a wide range of specifica-tions. As a result, the circuit of a general-purpose op amp represents a compromise among many performance parameters. We shall study in detail one such circuit, the 741-type op amp.
Although the 741 has been available for nearly 40 years, its internal circuit remains as relevant and interesting today as it ever was. Nevertheless, changes in technology have introduced new requirements, such as the need for general-purpose op amps that operate from a single power supply of only 2 V to 3 V. These new requirements have given rise to exciting challenges to op-amp designers. The result has been a wealth of new ideas and design techniques. We shall present a sample of these modern design techniques in the last section.
In addition to exposing the reader to some of the ideas that make analog IC design such an exciting topic, this chapter should serve to tie together many of the concepts and methods studied thus far.
12.1 The Two-Stage CMOS Op Amp The first op-amp circuit we shall study is the two-stage CMOS topology shown in Fig. 12.1.
This simple but elegant circuit has become a classic and is used in a variety of forms in the design of VLSI systems. We have already studied this circuit in Section 8.6.1 as an example of a multistage CMOS amplifier. We urge the reader to review Section 8.6.1 before proceed-ing further. Here, our discussion will emphasize the performance characteristics of the circuit and the trade-offs involved in its design.
Figure 12.1 The basic two-stage CMOS op-amp configuration.
CC I 12.1 The Two-Stage CMOS Op Amp 977 12.1.1 The Circuit The circuit consists of two gain stages: The first stage is formed by the differential pair Q1–Q2 together with its current mirror load Q3–Q4. This differential-amplifier circuit, studied in detail in Section 8.5, provides a voltage gain that is typically in the range of 20 V/V to 60 V/V, as well as performing conversion from differential to single-ended form while providing a reasonable common-mode rejection ratio (CMRR).
The differential pair is biased by current source Q5, which is one of the two output transistors of the current mirror formed by Q8, Q5, and Q7. The current mirror is fed by a reference current IREF, which can be generated by simply connecting a precision resistor (external to the chip) to the negative supply voltage −VSS or to a more precise negative voltage reference if one is avail-able in the same integrated circuit. Alternatively, for applications with more stringent require-ments, IREF can be generated using a circuit such as that studied in Section 8.6.1 (Fig. 8.41).
The second gain stage consists of the common-source transistor Q6 and its current-source load Q7. The second stage typically provides a gain of 50 V/V to 80 V/V. In addition, it takes part in the process of frequency compensating the op amp. From Section 10.13 the reader will recall that to guarantee that the op amp will operate in a stable fashion (as opposed to oscillating) when neg-ative feedback of various amounts is applied, the open-loop gain is made to roll off with fre-quency at the uniform rate of −20 dB/decade. This in turn is achieved by introducing a pole at a relatively low frequency and arranging for it to dominate the frequency-response determination.
In the circuit we are studying, this is implemented using a compensation capacitance CC con-nected in the negative-feedback path of the second-stage amplifying transistor Q6. As will be seen, CC (together with the much smaller capacitance Cgd6 across it) is Miller-multiplied by the gain of the second stage, and the resulting capacitance at the input of the second stage interacts with the total resistance there to provide the required dominant pole (more on this later).
Unless properly designed, the CMOS op-amp circuit of Fig. 12.1 can exhibit a systematic output dc offset voltage. This point was discussed in Section 8.6.1, where it was found that the dc offset can be eliminated by sizing the transistors so as to satisfy the following constraint: (12.1) Finally, we observe that the CMOS op-amp circuit of Fig. 12.1 does not have an output stage.
This is because it is usually required to drive only small on-chip capacitive loads.
12.1.2 Input Common-Mode Range and Output Swing Refer to Fig. 12.1 and consider the situation when the two input terminals are tied together and connected to a voltage VICM. The lowest value of VICM has to be sufficiently large to keep Q1 and Q2 in saturation. Thus, the lowest value of VICM should not be lower than the voltage at the drain of Q1 (−VSS + VGS3 = −VSS + Vtn + VOV3) by more than , thus (12.2) The highest value of VICM should ensure that Q5 remains in saturation; that is, the voltage across Q5, VSD5, should not decrease below . Equivalently, the voltage at the drain of Q5 should not go higher than VDD − . Thus the upper limit of VICM is or equivalently (12.3) W L ⁄ ( )6 W L ⁄ ( )4 -------------------2 W L ⁄ ( )7 W L ⁄ ( )5 -------------------= Vtp V ICM V – SS Vtn V OV3 Vtp – + + ≥ VOV5 VOV5 V ICM VDD V OV5 – VSG1 – ≤ V ICM V DD V OV5 – Vtp – V OV1 – ≤ 978 Chapter 12 Operational-Amplifier Circuits The expressions in Eqs. (12.2) and (12.3) can be combined to express the input common-mode range as (12.4) As expected, the overdrive voltages, which are important design parameters, subtract from the dc supply voltages, thereby reducing the input common-mode range. It follows that from a VICM range point of view it is desirable to select the values of VOV as low as possible. We observe from Eq. (12.4) that the lower limit of VICM is approximately within an overdrive voltage of –VSS.The upper limit, however, is not as good; it is lower than VDD by two over-drive voltages and a threshold voltage.
The extent of the signal swing allowed at the output of the op amp is limited at the lower end by the need to keep Q6 saturated and at the upper end by the need to keep Q7 saturated, thus (12.5) Thus the ouput voltage can swing to within an overdrive voltage of each of the supply rails.
This is a reasonably wide output swing and can be maximized by selecting values for of Q6 and Q7 as low as possible. An important requirement of an op-amp circuit is that it be possible for its output terminal to be connected back to its negative input terminal so that a unity-gain amplifier is obtained.
For such a connection to be possible, there must be a substantial overlap between the allow-able range of vO and the allowable range of VICM. This is usually the case in the CMOS amplifier circuit under study.
12.1.3 Voltage Gain To determine the voltage gain and the frequency response, consider a simplified equivalent circuit model for the small-signal operation of the CMOS amplifier (Fig. 12.2), where each of the two stages is modeled as a transconductance amplifier. As expected, the input resis-tance is practically infinite, The first-stage transconductance Gm1 is equal to the transconductance of each of Q1 and Q2 (see Section 8.5), (12.6) V – SS V OV3 V tn Vtp – + + V ICM VDD ≤ Vtp – V OV1 V OV5 – – ≤ V – SS VOV6 + vO VDD ≤ V OV7 – ≤ VOV 12.1 For a particular design of the two-stage CMOS op amp of Fig. 12.1, ±1.65-V supplies are utilized and all transistors except for Q6 and Q7 are operated with overdrive voltages of 0.3-V magnitude; Q6 and Q7 use overdrive voltages of 0.5-V magnitude. The fabrication process employed provides V tn = = 0.5 V. Find the input common-mode range and the range allowed for vO. Ans. −1.35 V to 0.55 V; −1.15 V to +1.15 V V tp EXERCISE Rin ∞ = Gm1 gm1 gm2 = = 12.1 The Two-Stage CMOS Op Amp 979 Since Q1 and Q2 are operated at equal bias currents ( ) and equal overdrive voltages, VOV1 = VOV2, (12.7) Resistance R1 represents the output resistance of the first stage, thus (12.8) where (12.9) and (12.10) The dc gain of the first stage is thus (12.11) (12.12) (12.13) Observe that the magnitude of A1 is increased by operating the differential-pair transistors, Q1 and Q2, at a low overdrive voltage, and by choosing a longer channel length to obtain larger Early voltages, . Returning to the equivalent circuit in Fig. 12.2 and leaving the discussion of the various model capacitances until Section 12.1.5, we note that the second-stage transconductance Gm2 is given by (12.14) Figure 12.2 Small-signal equivalent circuit for the op amp in Fig. 12.1.
Vid Gm1Vid R2 C2 Vo C1 Vi2 Gm2 Vi2 R1 CC I 2 ⁄ Gm1 2 I 2 ⁄ ( ) V OV1 -----------------= I V OV1 -----------= R1 ro2 ro4 || = ro2 V A2 I 2 ⁄ -----------= ro4 V A4 I 2 ⁄ ---------= A1 Gm1R1 – = gm1 – ro2 ro4 || ( ) = 2 V OV1 ----------- 1 V A2 -----------1 V A4 --------+ – = VA Gm2 gm6 2ID6 VOV6 -----------= = 980 Chapter 12 Operational-Amplifier Circuits Resistance R2 represents the output resistance of the second stage, thus (12.15) where (12.16) and (12.17) The voltage gain of the second stage can now be found as (12.18) (12.19) (12.20) Here again we observe that to increase the magnitude of A2, Q6 has to be operated at a low overdrive voltage, and the channel lengths of Q6 and Q7 should be made longer. The overall dc voltage gain can be found as the product A1A2, (12.21) (12.22) Note that Av is of the order of (gmro)2. Thus the value of Av will be in the range of 500 V/V to 5000 V/V.
Finally, we note that the output resistance of the op amp is equal to the output resistance of the second stage, (12.23) Hence Ro can be large (i.e., in the tens-of-kilohms range). Nevertheless, as we learned from the study of negative feedback in Chapter 10, application of negative feedback that samples the op-amp output voltage results in reducing the ouput resistance by a factor equal to the amount of feedback (1 + Aβ ). Also, as mentioned before, CMOS op amps are rarely required to drive heavy resistive loads.
R2 ro6 ro7 || = ro6 V A6 ID6 --------= ro7 VA7 ID7 -----------VA7 ID6 -----------= = A2 Gm2R2 – = gm6 ro6 ro7 || ( ) – = 2 V OV6 ----------- 1 V A6 --------1 V A7 -----------+ – = Av A1A2 = Gm1R1Gm2R2 = gm1 ro2 ro4 || ( )gm6 ro6 ro7 || ( ) = Ro ro6 ro7 || = 12.1 The Two-Stage CMOS Op Amp 981 12.1.4 Common-Mode Rejection Ratio (CMRR) The CMRR of the two-stage op amp of Fig. 12.1 is determined by the first stage. This was analyzed in Section 8.5.4 and the result is given in Eq. (8.147), namely, (12.24) where is the output resistance of the bias current source Observe that CMRR is of the order of and thus can be reasonably high. Also, since is proportional to the CMRR is increased if long channels are used, especially for , and the transistors are operated at low overdrive voltages.
12.1.5 Frequency Response Refer to the equivalent circuit in Fig. 12.2. Capacitance C1 is the total capacitance between the output node of the first stage and ground, thus (12.25) Capacitance C2 represents the total capacitance between the output node of the op amp and ground and includes whatever load capacitance CL that the amplifier is required to drive, thus (12.26) Usually, CL is larger than the transistor capacitances, with the result that C2 becomes much larger than C1. Finally, note that Cgd6 should be shown in parallel with CC but has been ignored because CC is usually much larger.
The equivalent circuit of Fig. 12.2 was analyzed in detail in Section 9.8.2, where it was found that it has two poles and a positive real-axis zero with the following approximate frequencies: (12.27) 12.2 The CMOS op amp of Fig. 12.1 is fabricated in a process for which = = 20 V/μm. Find A1, A2, and Av if all devices are 1 μm long, VOV1 = 0.2 V, and VOV6 = 0.5 V. Also, find the op-amp output resistance obtained when the second stage is biased at 0.5 mA.
Ans. −100 V/V; −40 V/V; 4000 V/V; 20 kΩ 12.3 If the CMOS op amp in Fig. 12.1 is connected as a unity-gain buffer, show that the closed-loop out-put resistance is given by VAn ′ VAp ′ Rout 1 gm6 ⁄ gm1 ro2 ro4 || ( ) [ ] EXERCISES CMRR gm1 ro2 ro4 || ( ) [ ] 2gm3RSS [ ] = RSS Q5.
gmro ( )2 gmro VA VOV ⁄ VA ′ L VOV ⁄ , = Q5 C1 Cgd2 Cdb2 Cgd4 Cdb4 Cgs6 + + + + = C2 Cdb6 = Cdb7 Cgd7 CL + + + fP1 1 2πR1Gm2R2CC -----------------------------------982 Chapter 12 Operational-Amplifier Circuits (12.28) (12.29) Here, fP1 is the dominant pole formed by the interaction of Miller-multiplied CC [i.e., (1 + Gm2R2)CC Gm2R2CC] and R1. To achieve the goal of a uniform –20-dB/decade gain rolloff down to 0 dB, the unity-gain frequency ft, (12.30) (12.31) must be lower than fP2 and fZ, thus the design must satisfy the following two conditions (12.32) and (12.33) Simplified Equivalent Circuit The uniform –20-dB/decade gain rolloff obtained at fre-quencies f fP1 suggests that at these frequencies, the op amp can be represented by the sim-plified equivalent circuit shown in Fig. 12.3. Observe that this attractive simplification is based on the assumption that the gain of the second stage, , is large, and hence a virtual ground appears at the input terminal of the second stage. The second stage then effectively acts as an integrator that is fed with the output current signal of the first stage; Gm1Vid.
Although derived for the CMOS amplifier, this simplified equivalent circuit is general and applies to a variety of two-stage op amps, including the first two stages of the 741-type bipolar op amp studied later in this chapter.
Phase Margin The frequency compensation scheme utilized in the two-stage CMOS am-plifier is of the pole-splitting type, studied in Section 10.13.3: It provides a dominant low-frequency pole with frequency fP1 and shifts the second pole beyond ft. Figure 12.4 shows a fP2 Gm2 2πC2 -------------fZ Gm2 2πCC -------------ft Av f P1 = Gm1 2πCC -------------= Gm1 CC ---------Gm2 C2 ---------< Gm1 Gm2 < A2 CC 0 V Gm1Vid Vid Vo Figure 12.3 An approximate high-frequency equivalent circuit of the two-stage op amp. This circuit applies for frequencies f fP1.
12.1 The Two-Stage CMOS Op Amp 983 representative Bode plot for the gain magnitude and phase. Note that at the unity-gain frequency ft, the phase lag exceeds the 90° caused by the dominant pole at fP1. This so-called excess phase shift is due to the second pole, (12.34) and the right-half-plane zero, (12.35) (12.36) Thus the phase lag at f = ft will be (12.37) and thus the phase margin will be (12.38) From our study of the stability of feedback amplifiers in Section 10.12.2, we know that the magnitude of the phase margin significantly affects the closed-loop gain. Therefore, obtain-ing a desired minimum value of phase margin is usually a design requirement.
Figure 12.4 Typical frequency response of the two-stage op amp.
0 0 90º 180º fP2 fZ f (log scale) f (log scale) ft fP1 Phase margin 20 log Av 20 log A (dB) φP2 tan 1 – ft f P2 -------⎝ ⎠ ⎛ ⎞ – = φZ tan 1 – ft f Z ----⎝ ⎠ ⎛ ⎞ – = φtotal 90° tan 1 – ( ft f P2 ⁄ ) tan 1 – ( f t fZ ⁄ ) + + = Phase margin 180° φtotal – = 90° tan 1 – ( f t fP2 ⁄ ) – tan 1 – ( f t fZ ) ⁄ – = 984 Chapter 12 Operational-Amplifier Circuits The problem of the additional phase lag provided by the right-half-plane zero has a rather simple and elegant solution: By including a resistance R in series with CC, as shown in Fig. 12.5, the transmission zero can be moved to other less-harmful locations. To find the new location of the transmission zero, set Vo = 0. Then, the current through CC and R will be , and a node equation at the output yields Thus the zero is now at (12.39) We observe that by selecting we can place the zero at infinite frequency. An even better choice would be to select R greater than , thus placing the zero at a nega-tive real-axis location where the phase it introduces adds to the phase margin. 12.1.6 Slew Rate The slew-rate limitation of op amps is discussed in Chapter 2. Here, we shall illustrate the ori-gin of the slewing phenomenon in the context of the two-stage CMOS amplifier under study.
Figure 12.5 Small-signal equivalent circuit of the op amp in Fig. 12.1 with a resistance R included in series with CC.
Vid Gm1Vid R2 C2 Vo C1 Vi2 Gm2 Vi2 R1 CC R V i2 (R 1 sCC) ⁄ + ⁄ V i2 R 1 sCC ---------+ -------------------Gm2V i2 = s 1 CC 1 Gm2 ---------R – ⎝ ⎠ ⎛ ⎞ = R 1 Gm2 ⁄ , = 1 Gm2 ⁄ 12.4 A particular implementation of the CMOS amplifier of Figs. 12.1 and 12.2 provides Gm1 = 1 mA/V, Gm2 = 2 mA/V, ro2 = ro4 = 100 kΩ, ro6 = ro7 = 40 kΩ, and C2 = 1 pF.
(a) Find the value of CC that results in ft = 100 MHz. What is the 3-dB frequency of the open-loop gain?
(b) Find the value of the resistance R that when placed in series with CC causes the transmission zero to be located at infinite frequency.
(c) Find the frequency of the second pole and hence find the excess phase lag at f = ft, introduced by the second pole, and the resulting phase margin assuming that the situation in (b) pertains.
Ans. 1.6 pF; 50 kHz; 500 Ω; 318 MHz; 17.4°; 72.6° EXERCISE 12.1 The Two-Stage CMOS Op Amp 985 Consider the unity-gain follower of Fig. 12.6 with a step of, say, 1 V applied at the input.
Because of the amplifier dynamics, its output will not change in zero time. Thus, immedi-ately after the input is applied, the entire value of the step will appear as a differential signal between the two input terminals. In all likelihood, such a large signal will exceed the voltage required to turn off one side of the input differential pair ( VOV1: see earlier illustration, Fig. 8.6) and switch the entire bias current I to the other side. Reference to Fig. 12.1 shows that for our example, Q2 will turn off, and Q1 will conduct the entire current I. Thus Q4 will sink a current I that will be pulled from CC, as shown in Fig. 12.7. Here, as we did in Fig. 12.3, we are modeling the second stage as an ideal integrator. We see that the output voltage will be a ramp with a slope of : Thus the slew rate, SR, is given by (12.40) It should be pointed out, however, that this is a rather simplified model of the slewing process.
Relationship Between SR and ft A simple relationship exists between the unity-gain bandwidth ft and the slew rate SR. This relationship can be found by combining Eqs. (12.31) Figure 12.6 A unity-gain follower with a large step input. Since the output voltage cannot change imme-diately, a large differential voltage appears between the op-amp input terminals.
1 V 2 I CC ⁄ vo t ( ) I CC ------ t = SR I CC ------= CC iD4 I I 0 0 V vo Figure 12.7 Model of the two-stage CMOS op-amp of Fig. 12.1 when a large differential volt-age is applied.
986 Chapter 12 Operational-Amplifier Circuits and (12.40) and noting that Gm1 = gm1 = , to obtain (12.41) or equivalently, (12.42) Thus, for a given ωt, the slew rate is determined by the overdrive voltage at which the first-stage transistors are operated. A higher slew rate is obtained by operating Q1 and Q2 at a larger VOV. Now, for a given bias current I, a larger VOV is obtained if Q1 and Q2 are p-channel devices. This is an important reason for using p-channel rather than n-channel devices in the first stage of the CMOS op amp. Another reason is that it allows the second stage to employ an n-channel device. Now, since n-channel devices have greater transcon-ductances than corresponding p-channel devices, Gm2 will be high, resulting in a higher second-pole frequency and a correspondingly higher ωt. However, the price paid for these improvements is a lower Gm1 and hence a lower dc gain.
12.1.7 Power-Supply Rejection Ratio (PSRR) CMOS op amps are usually utilized in what are known as mixed-signal circuits: IC chips that combine analog and digital circuits. In such circuits, the switching activity in the digital portion usually results in increased ripple on the power supplies. A portion of the supply rip-ple can make its way to the op-amp output and thus corrupt the output signal. The traditional approach for reducing supply ripple by connecting large capacitances between the supply rails and ground is not viable in IC design, as such capacitances would consume most of the chip area. Instead, the analog IC designer has to pay attention to another op-amp specifica-tion that so far we have ignored, namely, the power-supply rejection ratio (PSRR). The PSRR is defined as the ratio of the amplifier differential gain to the gain experienced by a change in the power-supply voltage ( and ). For circuits utilizing two power sup-plies, we define (12.42) and (12.43) where (12.44) I V OV1 ⁄ SR 2π f tVOV = SR VOVωt = 12.5 Find SR for the CMOS op amp of Fig. 12.1 for the case f t = 100 MHz and VOV1 = 0.2 V. If CC = 1.6 pF, what must the bias current I be?
Ans. 126 V/μs; 200 μA EXERCISE vdd vss PSRR+ Ad A+ ------≡ PSRR– Ad A– --------= A+ vo vdd -------≡ 12.1 The Two-Stage CMOS Op Amp 987 (12.45) Obviously, to minimize the effect of the power-supply ripple, we require the op amp to have a large PSRR. A detailed analysis of the PSRR of the two-stage CMOS op amp is beyond the scope of this book (see Gray et al., 2009). Nevertheless, we make the following brief remarks. It can be shown that the circuit is remarkably insensitive to variations in , and thus is very high. This is not the case, however, for the negative-supply ripple , which is coupled to the output primarily through the second-stage transistors and . In particular, the por-tion of that appears at the op-amp output is determined by the voltage divider formed by the output resistances of and , (12.46) Thus, (12.47) Now utilizing from Eq. (12.22) gives (12.48) Thus, is of the form and therefore is maximized by selecting long channels L (to increase ), and operating at low .
12.1.8 Design Trade-offs The performance parameters of the two-stage CMOS amplifier are primarily determined by two design parameters: 1. The length L used for the channel of each MOSFET.
2. The overdrive voltage at which each transistor is operated. Throughout this section, we have found that a larger L and correspondingly larger increases the amplifier gain, CMRR and PSRR. We also found that operating at a lower increases these three parameters as well as increasing the input common-mode range and the allowable range of output swing. Also, although we have not analyzed the offset voltage of the op amp here, we know from our study of the subject in Section 8.4.1 that a number of the components of the input offset voltage that arises from random device mis-matches are proportional to at which the MOSFETs of the input differential pair are operated. Thus the offset is minimized by operating at a lower .
There is, however, an important MOSFET performance parameter that requires the selec-tion of a larger , namely, the transition frequency , which determines the high-fre-quency performance of the MOSFET, (12.49) A– vo vss ------= VDD PSRR+ vss Q6 Q7 vss Q6 Q7 vo vss ro7 ro6 ro7 + --------------------= A– vo vss ------ro7 ro6 ro7 + --------------------= ≡ Ad PSRR– Ad A– --------gm1 ro2 ro4 || ( )gm6ro6 = ≡ PSRR– gmro ( )2 VA VOV VOV VA VOV VOV VOV VOV fT fT gm 2π Cgs Cgd + ( ) -----------------------------------= 988 Chapter 12 Operational-Amplifier Circuits For an n-channel MOSFET, we can show that (see Appendix 7.A) (12.50) A similar relationship applies for the PMOS transistor, with and replacing and , respectively. Thus to increase and improve the high-frequency response of the op amp, we need to use a larger overdrive value and, not surprisingly, shorter channels. A larger also results in a higher op-amp slew rate SR (Eq. 12.41). Finally, note that the selection of a larger results, for the same bias current, in a smaller W/L, which com-bined with a short L leads to smaller devices and hence lower values of MOSFET capaci-tances and higher frequencies of operation.
In conclusion, the selection of presents the designer with a trade-off between improving the low-frequency performance parameters on the one hand and the high-fre-quency performance on the other. For modern submicron technologies, which require opera-tion from power supplies of 1 V to 1.5 V, overdrive voltages between 0.1 V and 0.3 V are typically utilized. For these process technologies, analog designers typically use channel lengths that are at least 1.5 to 2 times the specified value of , and even longer channels are used for current-source bias transistors.
fT 1.5μnVOV 2πL2 -----------------------μp VOV μn VOV fT VOV VOV VOV Lmin We conclude our study of the two-stage CMOS op amp with a design example. Let it be required to design the circuit to obtain a dc gain of 4000 V/V. Assume that the available fabrication technology is of the 0.5-μm type for which V tn = = 0.5 V, = 200 μA/V2, = 80 μA/V2, = = 20 V/μm, and VDD = VSS = 1.65 V. To achieve a reasonable dc gain per stage, use L = 1 μm for all devices. Also, for simplicity, operate all devices at the same , in the range of 0.2 V to 0.4 V. Use I = 200 μA, and to obtain a higher Gm2, and hence a higher fP2, use ID6 = 0.5 mA. Specify the ratios for all transistors.
Also give the values realized for the input common-mode range, the maximum possible output swing, Rin and Ro. Also determine the CMRR and PSRR realized. If C1 = 0.2 pF and C2 = 0.8 pF, find the required values of CC and the series resistance R to place the transmission zero at s = ∞ and to obtain the highest possible ft consistent with a phase margin of 75°. Evaluate the values obtained for ft and SR.
Solution Using the voltage-gain expression in Eq. (12.22), To obtain Av = 4000, given VA = 20 V, Vtp kn ′ kp ′ VAn ′ VAp ′ V OV W L ⁄ Av gm1 ro2 ro4 || ( )gm6 ro6 ro7 || ( ) = 2 I 2 ⁄ ( ) V OV -----------------1 2 ---× V A I 2 ⁄ ( ) -------------2ID6 V OV ----------× × 1 2 ---V A ID6 -------× × = V A V OV ---------⎝ ⎠ ⎛ ⎞ 2 = 4000 400 VOV 2 ---------= Example 12.1 12.1 The Two-Stage CMOS Op Amp 989 To obtain the required ( ) ratios of Q1 and Q2, Thus, and For Q3 and Q4 we write to obtain For Q5, Thus, Since Q7 is required to conduct 500 μA, its ( ) ratio should be 2.5 times that of Q5, For Q6 we write Thus, V OV 0.316 V = W L ⁄ ID1 1 2 --- kp ′ W L -----⎝ ⎠ ⎛ ⎞ 1 VOV 2 = 100 1 2 ---80 W L -----⎝ ⎠ ⎛ ⎞ × 1 0.3162 × = W L -----⎝ ⎠ ⎛ ⎞ 1 25 μm 1 μm ----------------= W L -----⎝ ⎠ ⎛ ⎞ 2 25 μm 1 μm ----------------= 100 1 2 ---200 W L -----⎝ ⎠ ⎛ ⎞ 3 0.3162 × × = W L -----⎝ ⎠ ⎛ ⎞ 3 W L -----⎝ ⎠ ⎛ ⎞ 4 10 μm 1 μm ----------------= = 200 1 2 ---80 W L -----⎝ ⎠ ⎛ ⎞ 5 0.3162 × × = W L -----⎝ ⎠ ⎛ ⎞ 5 50 μm 1 μm ----------------= W L ⁄ W L -----⎝ ⎠ ⎛ ⎞ 7 2.5 W L -----⎝ ⎠ ⎛ ⎞ 5 125 μm 1 μm -------------------= = 500 1 2 ---200 W L -----⎝ ⎠ ⎛ ⎞ 6 0.3162 × × × = W L -----⎝ ⎠ ⎛ ⎞ 6 50 μm 1 μm ----------------= 990 Chapter 12 Operational-Amplifier Circuits Example 12.1 continued Finally, let’s select thus The input common-mode range can be found using the expression in Eq. (12.4) as The maximum signal swing allowable at the output is found using the expression in Eq. (12.5) as The input resistance is practically infinite, and the output resistance is The CMRR is determined using Eq. (12.24), where . Thus, Expressed in decibels, we have dB The PSRR is determined using Eq. (12.48): or, expressed in decibels, dB To determine fP2 we use Eq. (12.28) and substitute for Gm2, Thus, IREF 20 μA, = W L -----⎝ ⎠ ⎛ ⎞ 8 0.1 W L -----⎝ ⎠ ⎛ ⎞ 5 5 μm 1 μm -------------= = 1.33 – V VICM 0.52 V ≤ ≤ 1.33 – V vO 1.33 V ≤ ≤ Ro ro6 = ro7 || 1 2 ---20 0.5 -------× 20 kΩ = = CMRR gm1 ro2 ro4 || ( ) 2gm3RSS ( ) = RSS ro5 VA ⁄ I = = CMRR 2 I 2 ⁄ ( ) VOV -----------------1 2 ---VA I 2 ⁄ ( ) -------------× × 2 2 I 2 ⁄ ( ) VOV -----------------× × VA I ------× = 2 VA VOV ---------⎝ ⎠ ⎛ ⎞ 2 2 20 0.316 -------------⎝ ⎠ ⎛ ⎞ 2 8000 = = = CMRR 20 log 8000 78 = = PSRR gm1 ro2 ro4 || ( )gm6ro6 = 2 I 2 ⁄ ( ) VOV -----------------1 2 ---VA I 2 ⁄ ( ) -------------× × 2ID6 VOV ----------× VA ID6 -------× = 2 VA VOV ---------⎝ ⎠ ⎛ ⎞ 2 2 20 0.316 -------------⎝ ⎠ ⎛ ⎞ 2 8000 = = = PSRR 20 log 8000 78 = = Gm2 gm6 2ID6 V OV ----------2 0.5 × 0.316 ----------------3.2 mA/V = = = = f P2 3.2 10 3 – × 2π 0.8 × 10 12 – × ----------------------------------------637 MHz = = 12.2 The Folded-Cascode CMOS Op Amp 991 12.2 The Folded-Cascode CMOS Op Amp In this section we study another type of CMOS op-amp circuit: the folded cascode. The cir-cuit is based on the folded-cascode amplifier studied in Section 7.3.6. There, it was men-tioned that although composed of a CS transistor and a CG transistor of opposite polarity, the folded-cascode configuration is generally considered to be a single-stage amplifier. Sim-ilarly, the op-amp circuit that is based on the cascode configuration is considered to be a single-stage op amp. Nevertheless, it can be designed to provide performance parameters that equal and in some respects exceed those of the two-stage topology studied in the preceding section. Indeed, the folded-cascode op-amp topology is currently as popular as the two-stage structure. Furthermore, the folded-cascode configuration can be used in conjunction with the two-stage structure to provide performance levels higher than those available from either circuit alone.
12.2.1 The Circuit Figure 12.8 shows the structure of the CMOS folded-cascode op amp. Here, Q1 and Q2 form the input differential pair, and Q3 and Q4 are the cascode transistors. Recall that for To move the transmission zero to we select the value of R as For a phase margin of 75°, the phase shift due to the second pole at must be 15°, that is, Thus, The value of CC can be found using Eq. (12.31), where Thus, The value of SR can now be found using Eq. (12.41) as s ∞, = R 1 Gm2 ---------1 3.2 10 3 – × ------------------------316 Ω = = = f = ft tan 1 – ft f P2 ------15° = f t 637 tan 15° × 171 MHz = = CC Gm1 2π ft ----------= Gm1 gm1 2 100 μA × 0.316 V ----------------------------0.63 mA/V = = = CC1 0.63 10 3 – × 2π 171 × 106 × ------------------------------------0.6 pF = = SR 2π 171 × 106 0.316 × × = 340 V/μs = 992 Chapter 12 Operational-Amplifier Circuits differential input signals, each of Q1 and Q2 acts as a common-source amplifier. Also note that the gate terminals of Q3 and Q4 are connected to a constant dc voltage (VBIAS1) and hence are at signal ground. Thus, for differential input signals, each of the transistor pairs Q1–Q3 and Q2–Q4 acts as a folded-cascode amplifier, such as the one in Fig. 7.16. Note that the input differential pair is biased by a constant-current source I. Thus each of Q1 and Q2 is operating at a bias current . A node equation at each of their drains shows that the bias current of each of Q3 and Q4 is Selecting forces all transistors to operate at the same bias current of For reasons that will be explained shortly, however, the value of IB is usually made somewhat greater than I.
As we learned in Chapter 7, if the full advantage of the high output-resistance achieved through cascoding is to be realized, the output resistance of the current-source load must be equally high. This is the reason for using the cascode current mirror Q5 to Q8, in the circuit of Fig. 12.8. (This current-mirror circuit was studied in Section 7.5.1.) Finally, note that capacitance CL denotes the total capacitance at the output node. It includes the internal tran-sistor capacitances, an actual load capacitance (if any), and possibly an additional capacitance deliberately introduced for the purpose of frequency compensation. In many cases, however, the load capacitance will be sufficiently large, obviating the need to provide additional capacitance to achieve the desired frequency compensation. This topic will be discussed shortly. For the time being, we note that unlike the two-stage circuit, that requires the introduction of a separate compensation capacitor CC, here the load capacitance contributes to frequency compensation.
A more complete circuit for the CMOS folded-cascode op amp is shown in Fig. 12.9.
Here we show the two transistors Q9 and Q10, which provide the constant bias currents IB, and transistor Q11, which provides the constant current I utilized for biasing the differential pair. Observe that the details for generating the bias voltages VBIAS1, VBIAS2, and VBIAS3 are not Figure 12.8 Structure of the folded-cascode CMOS op amp.
Q1 Q2 Q3 Q5 Q7 Q4 Q6 Q8 IB IB I VDD VSS VBIAS1 Input differential pair Cascode transistors Cascode current mirror CL vo I 2 ⁄ IB I 2 ⁄ – ( ).
IB = I I 2 ⁄ .
12.2 The Folded-Cascode CMOS Op Amp 993 shown. Nevertheless, we are interested in how the values of these voltages are to be selected.
Toward that end, we evaluate the input common-mode range and the allowable output swing.
12.2.2 Input Common-Mode Range and Output Swing To find the input common-mode range, let the two input terminals be tied together and con-nected to a voltage VICM. The maximum value of VICM is limited by the requirement that Q1 and Q2 operate in saturation at all times. Thus VICMmax should be at most Vtn volts above the voltage at the drains of Q1 and Q2. The latter voltage is determined by VBIAS1 and must allow for a volt-age drop across Q9 and Q10 at least equal to their overdrive voltage, = Assuming that Q9 and Q10 are indeed operated at the edge of saturation, VICMmax will be (12.51) which can be larger than VDD, a significant improvement over the case of the two-stage cir-cuit. The value of VBIAS2 should be selected to yield the required value of IB while operating Q9 and Q10 at a small value of (e.g., 0.2 V or so). The minimum value of VICM can be obtained as (12.52) The presence of the threshold voltage V t n in this expression indicates that VICMmin is not suffi-ciently low. Later in this section we shall describe an ingenious technique for solving this problem. For the time being, note that the value of VBIAS3 should be selected to provide the Figure 12.9 A more complete circuit for the folded-cascode CMOS amplifier of Fig. 12.8.
Q1 Q2 Q3 Q5 Q9 Q7 Q4 Q6 Ro6 Ro4 Q8 VBIAS3 VSS VDD VBIAS2 Q11 Q10 VBIAS1 CL vO V OV9 V OV10 .
VICMmax VDD V OV9 V tn + – = V OV VICMmin VSS V OV11 V OV1 V tn + + + – = 994 Chapter 12 Operational-Amplifier Circuits required value of I while operating Q11 at a low overdrive voltage. Combining Eqs. (12.51) and (12.52) provides (12.53) The upper end of the allowable range of vO is determined by the need to maintain Q10 and Q4 in saturation. Note that Q10 will operate in saturation as long as an overdrive voltage, appears across it. It follows that to maximize the allowable positive swing of vO (and VICMmax), we should select the value of VBIAS1 so that Q10 operates at the edge of saturation, that is, (12.54) The upper limit of vO will then be (12.55) which is two overdrive voltages below VDD. The situation is not as good, however, at the other end: Since the voltage at the gate of Q6 is −VSS + VGS7 + VGS5 or equivalently −VSS + VOV7 + VOV5 + 2Vtn, the lowest possible vO is obtained when Q6 reaches the edge of saturation, namely, when vO decreases below the voltage at the gate of Q6 by Vtn, that is, (12.56) Note that this value is two overdrive voltages plus a threshold voltage above . This is a drawback of utilizing the cascode mirror. The problem can be alleviated by using a modified mirror circuit, as we shall shortly see.
12.2.3 Voltage Gain The folded-cascode op amp is simply a transconductance amplifier with an infinite input resistance, a transconductance Gm and an output resistance Ro. Gm is equal to gm of each of the two transistors of the differential pair, (12.57) Thus, (12.58) V SS V OV11 V OV1 V tn VICM V DD VOV9 Vtn + – ≤ ≤ + + + – VOV10 , VBIAS1 VDD V OV10 V SG 4 – – = vOmax VDD V OV10 – VOV4 – = vOmin −VSS V OV7 V OV5 V t n + + + = V – SS 12.6 For a particular design of the folded-cascode op amp of Fig. 12.9, ±1.65-V supplies are utilized and all transistors are operated at overdrive voltages of 0.3-V magnitude. The fabrication process employed provides Find the input common-mode range and the range al-lowed for vO.
Ans. −0.55 V to +1.85 V; −0.55 V to +1.05 V.
Vtn = Vtp = 0.5 V.
EXERCISE Gm gm1 gm2 = = Gm 2 I 2 ⁄ ( ) V OV1 -----------------I V OV1 -----------= = 12.2 The Folded-Cascode CMOS Op Amp 995 The output resistance Ro is the parallel equivalent of the output resistance of the cascode amplifier and the output resistance of the cascode mirror, thus (12.59) Reference to Fig. 12.9 shows that the resistance Ro4 is the output resistance of the CG tran-sistor Q4. The latter has a resistance in its source lead, thus (12.60) The resistance Ro6 is the output resistance of the cascode mirror and is thus given by Eq. (7.25), thus (12.61) Combining Eqs. (12.59) to (12.61) gives (12.62) The dc open-loop gain can now be found using Gm and Ro, as (12.63) Thus, (12.64) Figure 12.10 shows the equivalent-circuit model including the load capacitance CL, which we shall take into account shortly.
Because the folded-cascode op amp is a transconductance amplifier, it has been given the name operational transconductance amplifier (OTA). Its very high output resistance, which is of the order of (see Eq. 12.62) is what makes it possible to realize a relatively high voltage gain in a single amplifier stage. However, such a high output resistance may be a cause of concern to the reader; after all, in Chapter 2, we stated that an ideal op amp has a zero output resistance! To alleviate this concern somewhat, let us find the closed-loop out-put resistance of a unity-gain follower formed by connecting the output terminal of the cir-cuit of Fig. 12.9 back to the negative input terminal. Since this feedback is of the voltage sampling type, it reduces the output resistance by the factor , where and that is, (12.65) Ro Ro4 Ro6 || = ro2 ro10 || ( ) Ro4 gm4ro4 ( ) ro2 ro10 || ( ) Ro6 gm6ro6ro8 Ro gm4ro4 ro2 ro10 || ( ) [ ] gm6ro6ro8 ( ) || = Av GmRo = Av gm1 gm4ro4 ro2 ro10 || ( ) [ ] gm6ro6ro8 ( ) || { } = gmro 2 1 Aβ + ( ) A Av = β 1, = Rof Ro 1 Av + --------------- Ro Av -----= GmVid CL Ro Vid Vo Figure 12.10 Small-signal equivalent cir-cuit of the folded-cascode CMOS amplifier.
Note that this circuit is in effect an opera-tional transconductance amplifier (OTA).
996 Chapter 12 Operational-Amplifier Circuits Substituting for Av from Eq. (12.63) gives (12.66) which is a general result that applies to any OTA to which 100% voltage feedback is applied. For our particular circuit, , thus (12.67) Since gm1 is of the order of 1 mA/V, Rof will be of the order of 1 kΩ. Although this is not very small, it is reasonable in view of the simplicity of the op-amp circuit as well as the fact that this type of op amp is not usually intended to drive low-valued resistive loads.
12.2.4 Frequency Response From Section 9.6, we know that one of the advantages of the cascode configuration is its excellent high-frequency response. It has poles at the input, at the connection between the CS and CG transistors (i.e., at the source terminals of Q3 and Q4), and at the output terminal.
Normally, the first two poles are at very high frequencies, especially when the resistance of the signal generator that feeds the differential pair is small. Since the primary purpose of CMOS op amps is to feed capacitive loads, CL is usually large, and the pole at the output becomes dominant. Even if CL is not large, we can increase it deliberately to give the op amp a dominant pole. From Fig. 12.10 we can write (12.68) Thus, the dominant pole has a frequency f P, (12.69) and the unity-gain frequency f t will be (12.70) From a design point of view, the value of CL should be such that at f = f t the excess phase resulting from the nondominant poles is small enough to permit the required phase margin to be achieved. If CL is not large enough to achieve this purpose, it can be augmented.
Rof 1 Gm -------Gm gm1 = Rof 1 gm1 ⁄ = 12.7 The CMOS op amp of Figs. 12.8 and 12.9 is fabricated in a process for which = = 20 V/μm. If all devices have 1-μm channel length and are operated at equal overdrive voltages of 0.2-V magnitude, find the voltage gain obtained. If each of Q1 to Q8 is biased at 100 μA, what value of Ro is obtained?
Ans. 13,333 V/V; 13.3 MΩ V An ′ VAp ′ EXERCISE Vo Vid -------GmRo 1 sCLRo + ------------------------= fP 1 2πCLRo -------------------= ft GmRofP Gm 2πCL -------------= = 12.2 The Folded-Cascode CMOS Op Amp 997 It is important to note the different effects of increasing the load capacitance on the oper-ation of the two op-amp circuits we have studied. In the two-stage circuit, if CL is increased, the frequency of the second pole decreases, the excess phase shift at f = f t increases, and the phase margin is reduced. Here, on the other hand, when CL is increased, f t decreases, but the phase margin increases. In other words, a heavier capacitive load decreases the bandwidth of the folded-cascode amplifier but does not impair its response (which happens when the phase margin decreases). Of course, if an increase in CL is anticipated in the two-stage case, the designer can increase CC, thus decreasing f t and restoring the phase margin to its required value.
12.2.5 Slew Rate As discussed in Section 12.1.6, slewing occurs when a large differential input signal is applied. Refer to Fig. 12.8 and consider the case of a large signal Vid applied so that Q2 cuts off and Q1 conducts the entire bias current I. We see that Q3 will now carry a current , and Q4 will conduct a current IB. The current mirror will see an input current of through Q5 and Q7 and thus its output current in the drain of Q6 will be It follows that at the output node the current that will flow into CL will be I4 − I6 = IB − Thus the output vO will be a ramp with a slope of which is the slew rate, (12.71) Note that the reason for selecting is to avoid turning off the current mirror com-pletely; if the current mirror turns off, the output distortion increases. Typically, IB is set 10% to 20% larger than I. Finally, Eqs. (12.70), (12.71), and (12.58) can be combined to obtain the following relationship between SR and f t (12.72) which is identical to the corresponding relationship in the case of the two-stage design.
Note, however, that this relationship applies only when op-amp IB I – ( ) IB I – ( ) IB I – ( ).
IB I – ( ) I.
= I CL ⁄ SR I CL ------= IB I > SR 2πft VOV1 = IB I.
Consider a design of the folded-cascode op amp of Fig. 12.9 for which I = 200 μA, IB = 250 μA, and for all transistors is 0.25 V. Assume that the fabrication process provides = 100 = 40 , and Let all transistors have and assume that Find ID, gm, ro, and W/L for all transistors. Find the allowable range of and of the output voltage swing. Determine the values of Av, f t, fP, and SR. What is the power dissipation of the op amp?
Solution From the given values of I and IB we can determine the drain current ID for each transistor. The transcon-ductance of each device is found using VOV kn ′ μA/V2, kp ′ μA/V2 V ′ A = 20 V/μm. V DD = VSS = 2.5 V, Vt 0.75 V.
= L = 1 μm CL = 5 pF.
V ICM gm 2ID VOV ---------2ID 0.25 ----------= = Example 12.2 998 Chapter 12 Operational-Amplifier Circuits Example 12.2 continued and the output resistance ro from The W/L ratio for each transistor is determined from The results are as follows: Note that for all transistors, Using the expression in Eq. (12.53), the input common-mode range is found to be The output voltage swing is found using Eqs. (12.55) and (12.56) to be To obtain the voltage gain, we first determine Ro4 using Eq. (12.60) as and Ro6 using Eq. (12.61) as The output resistance Ro can then be found as and the voltage gain The unity-gain bandwidth is found using Eq. (12.70), Thus, the dominant-pole frequency must be Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 ID (μA) 100 100 150 150 150 150 150 150 250 250 200 gm (mA/V) 0.8 0.8 1.2 1.2 1.2 1.2 1.2 1.2 2.0 2.0 1.6 ro (kΩ) 200 200 133 133 133 133 133 133 80 80 100 W/L 32 32 120 120 48 48 48 48 200 200 64 ro VA ID ---------20 ID ------= = W L -----⎝ ⎠ ⎛ ⎞ i 2IDi k′V2 OV ----------------= gmro 160 V/V = VGS 1.0 V = 1.25 – V V ICM 3 V ≤ ≤ 1.25 – V vO 2 V ≤ ≤ Ro4 160 200 80 || ( ) 9.14 MΩ = = Ro6 21.28 MΩ = Ro Ro4 Ro6 || 6.4 MΩ = = Av GmRo 0.8 10 3 – 6.4 × 106 × × = = 5120 V/V = ft 0.8 10 3 – × 2π 5 × 10 12 – × -----------------------------------25.5 MHz = = fP ft Av -----25.5 MHz 5120 -------------------------5 kHz = = = 12.2 The Folded-Cascode CMOS Op Amp 999 12.2.6 Increasing the Input Common-Mode Range: Rail-to-Rail Input Operation In Section 12.2.2 we found that while the upper limit on the input common-mode range exceeds the supply voltage VDD, the magnitude of lower limit is significantly lower than VSS.
The opposite situation occurs if the input differential amplifier is made up of PMOS transis-tors. It follows that an NMOS and a PMOS differential pair placed in parallel would provide an input stage with a common-mode range that exceeds the power supply voltage in both directions. This is known as rail-to-rail input operation. Figure 12.11 shows such an arrange-ment. To keep the diagram simple, we have not shown the parallel connection of the two dif-ferential pairs: The two positive-input terminals are to be connected together and the two negative-input terminals are to be tied together. Transistors Q5 and Q6 are the cascode tran-sistors for the Q1–Q2 pair, and transistors Q7 and Q8 are the cascode devices for the Q3–Q4 pair. The output voltage Vo is shown taken differentially between the drains of the cascode devices. To obtain a single-ended output, a differential-to-single-ended conversion circuit should be connected in cascade.
Figure 12.11 indicates by arrows the direction of the current increments that result from the application of a positive differential input signal V i d. Each of the current increments indi-cated is equal to Gm(Vid ⁄ 2) where Gm = gm1 = gm2 = gm3 = gm4. Thus the total current feeding each of the two output nodes will be GmVid. Now, if the output resistance between each of the two nodes and ground is denoted Ro, the output voltage will be (12.73) Thus the voltage gain will be (12.74) This, however, assumes that both differential pairs will be operating simultaneously. This in turn occurs only over a limited range of VICM. Over the remainder of the input common-mode range, only one of the two differential pairs will be operational, and the gain drops to half of the value in Eq. (12.74). This rail-to-rail, folded-cascode structure is utilized in a commercially available op amp.1 1The Texas Instruments OPA357.
The slew rate can be determined using Eq. (12.71), Finally, to determine the power dissipation we note that the total current is 500 μA = 0.5 mA, and the total supply voltage is 5 V, thus SR I CL ------200 10 6 – × 5 10 12 – × -------------------------40 V/μs = = = PD 5 0.5 × 2.5 mW = = Vo 2GmRoVid = Av 2GmRo = 1000 Chapter 12 Operational-Amplifier Circuits 12.2.7 Increasing the Output Voltage Range: The Wide-Swing Current Mirror In Section 12.2.2 it was found that while the output voltage of the circuit of Fig. 12.9 can swing to within of VDD, the cascode current mirror limits the negative swing to above −VSS. In other words, the cascode mirror reduces the voltage swing by Vt volts. This point is further illustrated in Fig. 12.12(a), which shows a cascode mirror (with VSS = 0, for simplicity) and indicates the voltages that result at the various nodes. Observe Figure 12.11 A folded-cascode op amp that employs two parallel complementary input stages to achieve rail-to-rail input common-mode operation. Note that the two “+” terminals are connected together and the two “–” terminals are connected together.
Q1 Q2 Q5 Q7 Q6 Q4 Q3 Q8 Vo VBIAS1 IB IB I VDD VSS IB I IB VBIAS2 12.8 For the circuit in Fig. 12.11, assume that all transistors, including those that implement the current sources, are operating at equal overdrive voltages of 0.3-V magnitude and have and that (a) Find the range over which the NMOS input stage operates.
(b) Find the range over which the PMOS input stage operates.
(c) Find the range over which both operate (the overlap range).
(d) Find the input common-mode range.
(Note that to operate properly, each of the current sources requires a minimum voltage of across its terminals.) Ans. −1.2 V to +2.9 V; −2.9 V to +1.2 V, −1.2 V to +1.2 V; −2.9 V to +2.9 V Vt 0.7 V = VDD VSS 2.5 V.
= = VOV EXERCISE 2 V OV 2 V OV Vt + [ ] 12.2 The Folded-Cascode CMOS Op Amp 1001 that because the voltage at the gate of Q3 is , the minimum voltage permitted at the output (while Q3 remains saturated) is Vt + 2V OV, hence the extra Vt. Also, observe that Q1 is operating with a drain-to-source voltage Vt + VOV, which is Vt volts greater than it needs to operate in saturation.
The observations above lead us to the conclusion that to permit the output voltage at the drain of Q3 to swing as low as 2VOV, we must lower the voltage at the gate of Q3 from 2Vt + 2VOV to Vt + 2VOV. This is exactly what is done in the modified mirror circuit in Fig.
12.12(b): The gate of Q3 is now connected to a bias voltage VBIAS = Vt + 2VOV. Thus the out-put voltage can go down to 2VOV with Q3 still in saturation. Also, the voltage at the drain of Q1 is now VOV and thus Q1 is operating at the edge of saturation. The same is true of Q2 and thus the current tracking between Q1 and Q2 will be assured. Note, however, that we can no longer connect the gate of Q2 to its drain. Rather, it is connected to the drain of Q4. This establishes a voltage of Vt + VOV at the drain of Q4 which is sufficient to operate Q4 in satura-tion (as long as Vt is greater than VOV, which is usually the case). This circuit is known as the wide-swing current mirror. Finally, note that Fig. 12.12(b) does not show the circuit for generating VBIAS. There are a number of possible circuits to accomplish this task, one of which is explored in Exercise 12.9.
Q4 Q2 Q3 Q1 IREF IO Vt VOV 2Vt 2VOV Vt VOV (a) Q4 Q2 Q3 Q1 IREF IO VOV VOV Vt VOV VBIAS Vt 2VOV Vt VOV (b) Figure 12.12 (a) Cascode current mirror with the voltages at all nodes indicated. Note that the minimum voltage allowed at the output is Vt + 2VOV. (b) A modification of the cascode mirror that results in the reduc-tion of the minimum output voltage to VOV. This is the wide-swing current mirror. The circuit requires a bias voltage VBIAS.
2Vt 2VOV + 12.9 Show that if transistor Q5 in the circuit of Fig. E12.9 has a W/L ratio equal to one-quarter that of the transistors in the wide-swing current mirror of Fig. 12.12(b), and provided the same value of IREF is utilized in both circuits, then the voltage generated, V5 is Vt + 2VOV, which is the value of VBIAS need-ed for the gates of Q3 and Q4.
EXERCISE 1002 Chapter 12 Operational-Amplifier Circuits 12.3 The 741 Op-Amp Circuit Our study of BJT op amps is in two parts: The first part (Sections 12.3–12.6) is focused on the 741 op-amp circuit, which is shown in Fig. 12.13; the second part (Section 12.7) presents some of the more recent design techniques. Note that in keeping with the IC design philosophy, the circuit in Fig. 12.13 uses a large number of transistors, but relatively few resistors, and only one capacitor. This philosophy is dictated by the economics (silicon area, ease of fabri-cation, quality of realizable components) of the fabrication of active and passive compo-nents in IC form (see Section 7.1 and Appendix A).
As is the case with most general-purpose IC op amps, the 741 requires two power supplies, and . Normally, but the circuit also operates satisfactorily with the power supplies reduced to much lower values (such as ±5 V). It is important to observe that no circuit node is connected to ground, the common terminal of the two supplies.
With a relatively large circuit such as that shown in Fig. 12.13, the first step in the analy-sis is the identification of its recognizable parts and their functions. This can be done as follows.
12.3.1 Bias Circuit The reference bias current of the 741 circuit, IREF, is generated in the branch at the extreme left of Fig. 12.13, consisting of the two diode-connected transistors Q11 and Q12 and the resistance R5. Using a Widlar current source formed by Q11, Q10, and R4, bias current for the first stage is generated in the collector of Q10. Another current mirror formed by Q8 and Q9 takes part in biasing the first stage.
The reference bias current IREF is used to provide two proportional currents in the collectors of Q13. This double-collector lateral 2 pnp transistor can be thought of as two transistors whose base–emitter junctions are connected in parallel. Thus Q12 and Q13 form a two-output current mirror: One output, the collector of Q13B, provides bias current and acts as a current-source load for Q17, and the other output, the collector of Q13A, provides bias current for the output stage of the op amp.
2See Appendix A for a description of lateral pnp transistors. Also, their characteristics were discussed in the Appendix to Chapter 7, Section 7.A.2.
IREF Q5 V5 Figure E12.9 +V CC VEE – VCC = V EE = 15 V, 12.3 The 741 Op-Amp Circuit 1003 Figure 12.13 The 741 op-amp circuit: Q11, Q12, and R5 generate a reference bias current; IREF. Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7.
The second gain stage is composed of Q16 and Q17 with Q13B acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q13A, Q18, and Q19, and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuits and are normally cut off.
1004 Chapter 12 Operational-Amplifier Circuits Two more transistors, Q18 and Q19, take part in the dc bias process. The purpose of Q18 and Q19 is to establish two VBE drops between the bases of the output transistors Q14 and Q20.
12.3.2 Short-Circuit Protection Circuitry The 741 circuit includes a number of transistors that are normally off and conduct only in the event of on attempt to draw a large current from the op-amp output terminal. This hap-pens, for example, if the output terminal is short-circuited to one of the two supplies. The short-circuit protection network consists of R6, R7, Q15, Q21, Q24, R11, and Q22. In the follow-ing we shall assume that these transistors are off. Operation of the short-circuit protection network will be explained in Section 12.5.3.
12.3.3 The Input Stage The 741 circuit consists of three stages: an input differential stage, an intermediate single-ended high-gain stage, and an output-buffering stage. The input stage consists of transistors Q1 through Q7, with biasing performed by Q8, Q9, and Q10. Transistors Q1 and Q2 act as emit-ter followers, causing the input resistance to be high and delivering the differential input sig-nal to the differential common-base amplifier formed by Q3 and Q4. Thus the input stage is the differential version of the common-collector common-base configuration discussed in Section 7.6.3.
Transistors Q5, Q6, and Q7 and resistors R1, R2, and R3 form the load circuit of the input stage. This is an elaborate current-mirror load circuit, which we will analyze in detail in Section 12.5.1. The circuit is based on the base-current-compensated mirror studied in Section 7.5, but it includes two emitter-degeneration resistors R1 and R2, and a large resistor R3 in the emitter of Q7.
It will be shown that this load circuit not only provides a high-resistance load but also converts the signal from differential to single-ended form with no loss in gain or common-mode rejec-tion. The output of the input stage is taken single-endedly at the collector of Q6.
As mentioned in Section 8.6.2, every op-amp circuit includes a level shifter whose func-tion is to shift the dc level of the signal so that the signal at the op-amp output can swing positive and negative. In the 741, level shifting is done in the first stage using the lateral pnp transistors Q3 and Q4. Although lateral pnp transistors have poor high-frequency perfor-mance, their use in the common-base configuration (which is known to have good high-frequency response) does not seriously impair the op-amp frequency response.
The use of the lateral pnp transistors Q3 and Q4 in the first stage results in an added advan-tage: protection of the input-stage transistors Q1 and Q2 against emitter–base junction break-down. Since the emitter–base junction of an npn transistor breaks down at about 7 V of reverse bias (see Section 6.9.1), regular npn differential stages suffer such a breakdown if, say, the supply voltage is accidentally connected between the input terminals. Lateral pnp transistors, however, have high emitter–base breakdown voltages (about 50 V); and because they are con-nected in series with Q1 and Q2, they provide protection of the 741 input transistors, Q1 and Q2.
Finally, note that except for using input buffer transistors, the 741 input stage is essen-tially a current-mirror-loaded differential amplifier. It is quite similar to the input stage of the CMOS amplifier in Fig. 12.1.
12.3.4 The Second Stage The second or intermediate stage is composed of Q16, Q17, Q13B, and the two resistors R8 and R9.
Transistor Q16 acts as an emitter follower, thus giving the second stage a high input 12.3 The 741 Op-Amp Circuit 1005 resistance. This minimizes the loading on the input stage and avoids loss of gain. Also, adding Q16 with its 50-kΩ emitter resistance (which is similar to Q7 and R3) increases the symmetry of the first stage and thus improves its CMRR. Transistor Q17 acts as a com-mon-emitter amplifier with a 100-Ω resistor in the emitter. Its load is composed of the high output resistance of the pnp current source Q13B in parallel with the input resistance of the output stage (seen looking into the base of Q23). Using a transistor current source as a load resistance (active load) enables one to obtain high gain without resorting to the use of large load resistances, which would occupy a large chip area and require large power-supply voltages.
The output of the second stage is taken at the collector of Q17. Capacitor CC is connected in the feedback path of the second stage to provide frequency compensation using the Miller compensation technique studied in Section 10.13. It will be shown in Section 12.5 that the relatively small capacitor CC gives the 741 a dominant pole at about 4 Hz. Furthermore, pole splitting causes other poles to be shifted to much higher frequencies, giving the op amp a uniform –20-dB/decade gain rolloff with a unity-gain bandwidth of about 1 MHz. It should be pointed out that although CC is small in value, the chip area that it occupies is about 13 times that of a standard npn transistor!
12.3.5 The Output Stage The purpose of the output stage (Chapter 11) is to provide the amplifier with a low output resistance. In addition, the output stage should be able to supply relatively large load cur-rents without dissipating an unduly large amount of power in the IC. The 741 uses an effi-cient class AB output stage, which we shall study in detail in Section 12.5.
The output stage of the 741 consists of the complementary pair Q14 and Q20, where Q20 is a substrate pnp (see Appendix A). Transistors Q18 and Q19 are fed by current source Q13A and bias the output transistors Q14 and Q20. Transistor Q23 (which is another substrate pnp) acts as an emitter follower, thus minimizing the loading effect of the output stage on the second stage.
12.3.6 Device Parameters In the following sections we shall carry out a detailed analysis of the 741 circuit. For the standard npn and pnp transistors, the following parameters will be used: In the 741 circuit the nonstandard devices are Q13, Q14, and Q20. Transistor Q13 will be assumed to be equivalent to two transistors, Q13A and Q13B, with parallel base–emitter junc-tions and having the following saturation currents: Transistors Q14 and Q20 will be assumed to each have an area three times that of a standard device. Output transistors usually have relatively large areas, to be able to supply large load currents and dissipate relatively large amounts of power with only a moderate increase in device temperature.
npn: IS 10 14 – A, β 200, V A 125 V = = = pnp: IS 10 14 – A, β 50, V A 50 V = = = ISA 0.25 10 14 – × A ISB 0.75 10 14 – × A = = 1006 Chapter 12 Operational-Amplifier Circuits 12.4 DC Analysis of the 741 In this section, we shall carry out a dc analysis of the 741 circuit to determine the bias point of each device. For the dc analysis of an op-amp circuit, the input terminals are grounded. Theoretically speaking, this should result in zero dc voltage at the output. How-ever, because the op amp has very large gain, any slight approximation in the analysis will show that the output voltage is far from being zero and is close to either +VCC or –VEE. In actual practice, an op amp left open-loop will have an output voltage saturated close to one of the two supplies. To overcome this problem in the dc analysis, it will be assumed that the op amp is connected in a negative feedback loop that stabilizes the output dc volt-age to zero volts.
12.10 For the standard npn transistor whose parameters are given in Section 12.3.6, find approximate values for the following parameters at IC = 1 mA: VBE, gm, re, rπ, and ro.
Ans. 633 mV; 40 mA/V; 25 Ω; 5 kΩ; 125 kΩ 12.11 For the circuit in Fig. E12.11, neglect base currents and use the exponential iC–vBE relationship to show that I3 I1 IS3IS4 IS1IS2 -------------= I3 I1 Q4 Q2 15 V 15 V Q3 Q1 Figure E12.11 EXERCISES 12.4 DC Analysis of the 741 1007 12.4.1 Reference Bias Current The reference bias current IREF is generated in the branch composed of the two diode-connected transistors Q11 and Q12 and resistor R5. With reference to Fig. 12.13, we can write For VCC = VEE = 15 V and VBE11 = VEB12 0.7 V, we have IREF = 0.73 mA.
12.4.2 Input-Stage Bias Transistor Q11 is biased by IREF, and the voltage developed across it is used to bias Q10, which has a series emitter resistance R4. This part of the circuit is redrawn in Fig. 12.14 and can be recognized as the Widlar current source studied in Section 7.5.5. From the circuit, and assuming β10 to be large, we have Thus (12.75) where it has been assumed that IS10 = IS11. Substituting the known values for IREF and R4, this equa-tion can be solved by trial and error to determine IC10. For our case, the result is IC10 = 19 μA.
IREF V CC V EB12 – VBE11 – V EE – ( ) – R5 ---------------------------------------------------------------------= VBE11 V BE10 – IC10R4 = VT ln IREF IC10 ---------IC10R4 = Figure 12.14 The Widlar current source that biases the input stage.
D12.12 Design the Widlar current source of Fig. 12.14 to generate a current IC10 = 10 μA given that IREF = 1 mA. If at a collector current of 1 mA, VBE = 0.7 V, find VBE11 and VBE10.
Ans. R4 = 11.5 kΩ; VBE11 = 0.7 V; VBE10 = 0.585 V EXERCISE 1008 Chapter 12 Operational-Amplifier Circuits Having determined IC10, we proceed to determine the dc current in each of the input-stage transistors. Part of the input stage is redrawn in Fig. 12.15. From symmetry, we see that Denote this current by I. We see that if the npn β is high, then and the base currents of Q3 and Q4 are equal, with a value of , where βP denotes β of the pnp devices.
The current mirror formed by Q8 and Q9 is fed by an input current of 2I. Using the result in Eq. (7.69), we can express the output current of the mirror as We can now write a node equation for node X in Fig. 12.15 and thus determine the value of I. If then this node equation gives For the 741, IC10 = 19 μA; thus I 9.5 μA. We have thus determined that At this point, we should note that transistors Q1 through Q4, Q8, and Q9 form a negative-feedback loop, which works to stabilize the value of I at approximately . To appreci-ate this fact, assume that for some reason the current I in Q1 and Q2 increases. This will Figure 12.15 The dc analysis of the 741 input stage.
I I IC1 IC2 = IE3 IE4 I = I βP 1 + ( ) ⁄ I βP ⁄ IC9 2I 1 2 βP ⁄ + ----------------------= βP 1, 2I IC10 IC1 IC2 IC3 IC4 9.5 μA = = = IC10 2 ⁄ 12.4 DC Analysis of the 741 1009 cause the current pulled from Q8 to increase, and the output current of the Q8–Q9 mirror will correspondingly increase. However, since IC10 remains constant, node X forces the combined base currents of Q3 and Q4 to decrease. This in turn will cause the emitter currents of Q3 and Q4, and hence the collector currents of Q1 and Q2, to decrease. This is opposite in direction to the change originally assumed. Hence the feedback is negative, and it stabilizes the value of I.
Figure 12.16 shows the remainder of the 741 input stage. This part of the circuit is fed by Transistors and are identical and have equal resistances and in their emitters; thus, (12.76) Now if the base currents of and can be neglected, then (12.77) and (12.78) Thus both the symmetry of and and the node equations at their collectors force their currents to be equal and to equal I. As will be shown shortly, not only are the base currents of and negligible, but their values are also reasonably close, which is an added help.
The bias current of Q7 can be determined from (12.79) Figure 12.16 The dc analysis of the 741 input stage, continued.
IB16 0 Q5 R1 VEE R3 R2 Q6 Q16 0 I/N I IC3 I IC4 I I/N I I I Q7 IC3 IC4 I.
= Q5 Q6 R1 R2 IC5 IC6 = Q7 Q16 IC5 IC3 I IC6 IC4 I Q5 Q6 Q7 Q16 IC7 IE7 2I βN ------VBE6 IR2 + R3 -------------------------+ = 1010 Chapter 12 Operational-Amplifier Circuits where βN denotes β of the npn transistors. To determine VBE6 we use the transistor exponen-tial relationship and write Substituting IS = 10−14 A and I = 9.5 μA results in VBE6 = 517 mV. Then substituting in Eq. (12.79) yields IC7 = 10.5 μA. Note that the base current of Q7 at approximately 0.05 μA is indeed negligible in comparison to the value of I, as has been assumed.
12.4.3 Input Bias and Offset Currents The input bias current of an op amp is defined (Chapters 2 and 8) as For the 741 we obtain Using βN = 200, yields IB = 47.5 nA. Note that this value is reasonably small and is typical of general-purpose op amps that use BJTs in the input stage. Much lower input bias currents (in the picoamp or femtoamp range) can be obtained using a FET input stage. Also, there exist techniques for reducing the input bias current of bipolar-input op amps.
Because of possible mismatches in the β values of Q1 and Q2, the input base currents will not be equal. Given the value of the β mismatch, one can use Eq. (8.131) to calculate the input offset current, defined as 12.4.4 Input Offset Voltage From Chapter 8 we know that the input offset voltage is determined primarily by mismatches between the two sides of the input stage. In the 741 op amp, the input offset voltage is due to mismatches between Q1 and Q2, between Q3 and Q4, between Q5 and Q6, and between R1 and R2. Evaluation of the components of VOS corresponding to the various mismatches follows the method outlined in Section 8.4. Basically, we find the current that results at the output of the first stage due to the particular mismatch being considered. Then we find the differential input voltage that must be applied to reduce the output current to zero.
12.4.5 Input Common-Mode Range The input common-mode range is the range of input common-mode voltages over which the input stage remains in the linear active mode. Refer to Fig. 12.13. We see that in the 741 circuit the input common-mode range is determined at the upper end by saturation of Q1 and Q2, and at the lower end by saturation of Q3 and Q4.
V BE6 VT ln I IS ----= IB IB1 IB2 + 2 -------------------= IB I βN ------= IOS IB1 IB2 – = 12.13 Neglect the voltage drops across R1 and R2 and assume that VCC = VEE = 15 V. Show that the input common-mode range of the 741 is approximately –12.9 V to +14.7 V. (Assume that VBE 0.6 V and that to avoid saturation VCB −0.3 V for an npn transistor, and VBC −0.3 V for a pnp transistor.) EXERCISE 12.4 DC Analysis of the 741 1011 12.4.6 Second-Stage Bias If we neglect the base current of Q23 then we see from Fig. 12.13 that the collector current of Q17 is approximately equal to the current supplied by current source Q13B. Because Q13B has a scale current 0.75 times that of Q12, its collector current will be IC13B 0.75IREF, where we have assumed that . Thus IC13B = 550 μA and IC17 550 μA. At this current level the base–emitter voltage of Q17 is The collector current of Q16 can be determined from This calculation yields IC16 = 16.2 μA. Note that the base current of Q16 at 0.08 μA will indeed be negligible compared to the input-stage bias I, as we have assumed.
12.4.7 Output-Stage Bias Figure 12.17 shows the output stage of the 741 with the short-circuit-protection circuitry omitted. Current source Q13A delivers a current of 0.25IREF (because IS of Q13A is 0.25 Figure 12.17 The 741 output stage without the short-circuit protection devices.
βP 1 V BE17 VT lnIC17 IS --------618 mV = = IC16 IE16 IB17 IE17R8 VBE17 + R9 ---------------------------------+ = 0.25IREF 1012 Chapter 12 Operational-Amplifier Circuits times the IS of Q12) to the network composed of Q18, Q19, and R10. If we neglect the base currents of Q14 and Q20, then the emitter current of Q23 will also be equal to 0.25IREF. Thus Thus we see that the base current of Q23 is only = 3.6 μA, which is negligible compared to IC17, as we have assumed.
If we assume that VBE18 is approximately 0.6 V, we can determine the current in R10 as 15 μA. The emitter current of Q18 is therefore Also, At this value of current we find that VBE18 = 588 mV, which is quite close to the value assumed. The base current of Q18 is 165/200 = 0.8 μA, which can be added to the current in R10 to determine the Q19 current as The voltage drop across the base–emitter junction of Q19 can now be determined as As mentioned in Section 12.3.5, the purpose of the Q18–Q19 network is to establish two VBE drops between the bases of the output transistors Q14 and Q20. This voltage drop, VBB, can be now calculated as Since VBB appears across the series combination of the base–emitter junctions of Q14 and Q20, we can write Using the calculated value of VBB and substituting IS14 = IS20 = 3 × 10−14 A, we determine the collector currents as This is the small current at which the class AB output stage is biased.
12.4.8 Summary For future reference, Table 12.1 provides a listing of the values of the collector bias currents of the 741 transistors. IC23 IE23 0.25IREF 180 μA = 180 50 ⁄ IE18 180 15 – 165 μA = = IC18 IE18 165 μA = IC19 IE19 15.8 μA = V BE19 VT ln IC19 IS --------530 mV = = VBB VBE18 VBE19 + 588 530 + 1.118 V = = = V BB VT ln IC14 IS14 --------VT ln IC20 IS20 --------+ = IC14 IC20 154 μA = = 12.5 Small-Signal Analysis of the 741 1013 12.5 Small-Signal Analysis of the 741 12.5.1 The Input Stage Figure 12.18 shows part of the 741 input stage for the purpose of performing small-signal analysis. Note that since the collectors of Q1 and Q2 are connected to a constant dc voltage, they are shown grounded. Also, the constant-current biasing of the bases of Q3 and Q4 is equivalent to having the common base terminal open-circuited.
The differential signal vi applied between the input terminals effectively appears across four equal emitter resistances connected in series—those of Q1, Q2, Q3, and Q4. As a result, emitter signal currents flow as indicated in Fig. 12.18 with (12.80) Table 12.1 DC Collector Currents of the 741 Circuit (μA) Q1 9.5 Q8 19 Q13B 550 Q19 15.8 Q2 9.5 Q9 19 Q14 154 Q20 154 Q3 9.5 Q10 19 Q15 0 Q21 0 Q4 9.5 Q11 730 Q16 16.2 Q22 0 Q5 9.5 Q12 730 Q17 550 Q23 180 Q6 9.5 Q13A 180 Q18 165 Q24 0 Q7 10.5 12.14 If in the circuit of Fig. 12.17 the Q18–Q19 network is replaced by two diode-connected transistors, find the current in Q14 and Q20. (Hint: Use the result of Exercise 12.11.) Ans. 540 μA EXERCISE ie vi 4re -------= Figure 12.18 Small-signal analysis of the 741 input stage.
Rid 1014 Chapter 12 Operational-Amplifier Circuits where re denotes the emitter resistance of each of Q1 through Q4. Thus Thus the four transistors Q1 through Q4 supply the load circuit with a pair of complementary current signals αie, as indicated in Fig. 12.18.
The input differential resistance of the op amp can be obtained from Fig. 12.18 as (12.81) For βN = 200, we obtain Rid = 2.1 MΩ.
Proceeding with the input-stage analysis, we show in Fig. 12.19 the load circuit fed with the complementary pair of current signals found earlier. Neglecting the signal current in the base of Q7, we see that the collector signal current of Q5 is approximately equal to the input current αie. Now, since Q5 and Q6 are identical and their bases are tied together, and since equal resistances are connected in their emitters, it follows that their collector signal currents must be equal. Thus the signal current in the collector of Q6 is forced to be equal to αie. In other words, the load circuit functions as a current mirror.
Now consider the output node of the input stage. The output current io is given by (12.82) The factor of 2 in this equation indicates that conversion from differential to single-ended is performed without losing half the signal. The trick, of course, is the use of the current mirror to invert one of the current signals and then add the result to the other current signal (see Section 8.5).
Equations (12.80) and (12.82) can be combined to obtain the transconductance of the input stage, Gm1: (12.83) Figure 12.19 The load circuit of the input stage fed by the two complementary current signals generated by Q1 through Q4 in Fig. 12.18. Circled numbers indicate the order of the analysis steps. re VT I -----25 mV 9.5 μA -----------------2.63 kΩ = = = Rid 4 βN 1 + ( )re = io 2αie = Gm1 io vi ---≡ α 2re -------= 1 2 R2 1 k R1 1 k R3 50 k ie Q5 0 Q7 Q6 io 2 ie 3 4 ie ie ie 12.5 Small-Signal Analysis of the 741 1015 Substituting re = 2.63 kΩ and α 1 yields Gm1 = 1/5.26 mA/V. The expression for Gm1 can be written in the alternate form (12.83′) where gm1 is the transconductance of each of Q1 to Q4.
To complete our modeling of the 741 input stage, we must find its output resistance Ro1.
This is the resistance seen “looking back” into the collector terminal of Q6 in Fig. 12.19.
Thus Ro1 is the parallel equivalent of the output resistance of the current source supplying the signal current αie, and the output resistance of Q6. The first component is the resistance looking into the collector of Q4 in Fig. 12.18. Finding this resistance is considerably simpli-fied if we assume that the common bases of Q3 and Q4 are at a virtual ground. This of course happens only when the input signal vi is applied in a complementary fashion. Nevertheless, this assumption does not result in a large error.
Assuming that the base of Q4 is at virtual ground, the resistance we are after is Ro4, indi-cated in Fig. 12.20(a). This is the output resistance of a common-base transistor that has a resistance (re of Q2) in its emitter. To find Ro4 we may use the following expression (Eq. 7.51): (12.84) Substituting and , where VA = 50 V and I = 9.5 μA (thus ro = 5.26 MΩ), and neglecting rπ since it is (β + 1) times larger than RE, results in Ro4 = 10.5 MΩ.
Gm1 1 2 ---= gm1 12.15 For the circuit in Fig. 12.19, find in terms of ie: (a) the signal voltage at the base of Q6; (b) the signal current in the emitter of Q7; (c) the signal current in the base of Q7; (d) the signal voltage at the base of Q7; (e) the input resistance seen by the left-hand-side signal current source αie. (Note: For simplicity, assume that IC7 IC5 = IC6.) Ans. (a) 3.63 kΩ × ie; (b) 0.08ie; (c) 0.0004ie; (d) 3.84 kΩ × ie; (e) 3.84 kΩ EXERCISE Ro ro 1 gm Re||rπ ( ) + [ ] = Re re 2.63 kΩ ≡ = ro = V A /I Figure 12.20 Simplified circuits for finding the two components of the output resistance Ro1 of the first stage.
1016 Chapter 12 Operational-Amplifier Circuits The second component of the output resistance is that seen looking into the collector of Q6 in Fig. 12.19 with the generator set to 0. Although the base of Q6 is not at signal ground, we shall assume that the signal voltage at the base is small enough to make this approxima-tion valid. The circuit then takes the form shown in Fig. 12.20(b), and Ro6 can be determined using Eq. (12.84) with Re = R2. Thus .
Finally, we combine Ro4 and Ro6 in parallel to obtain the output resistance of the input stage, Ro1, as Ro1 = 6.7 MΩ.
Figure 12.21 shows the equivalent circuit that we have derived for the input stage.
Figure 12.21 Small-signal equivalent circuit for the input stage of the 741 op amp.
αie Ro6 18.2 MΩ We wish to find the input offset voltage resulting from a 2% mismatch between the resistances R1 and R2 in Fig. 12.13.
Solution Consider first the situation when both input terminals are grounded, and assume that R1 = R and R2 = R + ΔR, where ΔR/R = 0.02. From Fig. 12.22 we see that while Q5 still conducts a current equal to I, the cur-rent in Q6 will be smaller by ΔI. The value of ΔI can be found from Thus (12.85) The quantity on the left-hand side is in effect the change in VBE due to a change in IE of ΔI. We may there-fore write (12.86) Equations (12.85) and (12.86) can be combined to obtain (12.87) Substituting R = 1 kΩ and re = 2.63 kΩ shows that a 2% mismatch between R1 and R2 gives rise to an output current To reduce this output current to zero we have to apply an input voltage VOS given by V BE5 IR + V BE6 I ΔI – ( ) R ΔR + ( ) + = V BE5 V BE6 – = IΔR ΔI R ΔR + ( ) – V BE5 V BE6 ΔIre – ΔI I ------ΔR R ΔR re + + ----------------------------= ΔI 5.5 10 3 – I.
× = Example 12.3 12.5 Small-Signal Analysis of the 741 1017 (12.88) Substituting I = 9.5 μA and results in the offset voltage It should be pointed out that the offset voltage calculated is only one component of the input offset voltage of the 741. Other components arise because of mismatches in transistor characteristics. The 741 offset voltage is specified to be typically 2 mV.
Figure 12.22 Input stage with both inputs grounded and a mismatch ΔR between R1 and R2.
V OS ΔI Gm1 ---------5.5 10 3 – I × Gm1 --------------------------= = Gm1 1 5.26 mA/V ⁄ = V OS 0.3 mV.
It is required to find the CMRR of the 741 input stage. Assume that the circuit is balanced except for mis-matches in the current-mirror load that result in an error in the mirror’s current-transfer ratio; that is, the ratio becomes .
Solution In Section 8.5.4 we analyzed the common-mode operation of the current-mirror-loaded differential amplifier and derived an expression for its CMRR. The situation in the 741 input stage, however, differs substantially because of the feedback loop that regulates the bias current. Since this feedback loop is sen-sitive to the common-mode signal, as will be seen shortly, the loop operates to reduce the common-mode gain and, correspondingly, to increase the CMRR. Hence, its action is referred to as common-mode feedback. Figure 12.23 shows the 741 input stage with a common-mode signal applied to both input termi-nals. We have assumed that as a result of a signal current i flows as shown. Since the stage is bal-anced, both sides carry the same current i. εm 1 εm – ( ) vicm vicm, Example 12.4 1018 Chapter 12 Operational-Amplifier Circuits Example 12.4 continued Our objective now is to determine how i relates to . Toward that end, observe that for common-mode inputs, both sides of the differential amplifier, that is, and , act as followers, deliv-ering a signal almost equal to to the common-base node of and Now, this node Y is con-nected to the collectors of two current sources, and Denoting the total resistance between node Y and ground we write (12.89) In Fig. 12.23 we have “pulled out,” thus leaving behind ideal current sources and . Since the current in is constant, we show in Fig. 12.23 as having a zero incremental current. Transistor on the other hand, provides a current approximately equal to that fed into , which is This is the feedback current. Since senses the sum of the currents in the two sides of the differential amplifier, the feedback loop operates only on the common-mode signal and is insensitive to any difference signal.
Proceeding with the analysis, we now can write a node equation at Y, (12.90) Assuming , this equation simplifies to (12.91) Having determined i, we now proceed to complete our analysis by finding the output current . From the circuit in Fig. 12.23, we see that (12.92) Thus the common-mode transconductance of the input stage is given by R4 Ro vicm vicm /Ro Y vicm vicm Gmcm vicm mi In Out Current Mirror 2i io mi i (1 m) i i i i/bP i/bP 2i/bP 2i 2i Q9 Q2 Q3 Q4 Q1 Q8 Q10 i i i 0 Figure 12.23 Example 12.4: Analysis of the common-mode gain of the 741 input stage. Note that , has been “pulled out” and shown seperately, leaving behind ideal current sources Q9 and Q10.
Ro Ro9 || Ro10 = vicm Q 1 Q 3 – Q2 Q4 – vicm Q3 Q4.
Q9 Q10.
Ro, Ro Ro9 Ro10 || = Ro Q9 Q10 Q10 Q10 Q9, Q8 2i.
Q8 2i 2i βP ------vicm Ro ---------= + βP 1 i vicm 2Ro ---------io io εmi = Gmcm io vicm ---------εmi vicm ---------= ≡ 12.5 Small-Signal Analysis of the 741 1019 12.5.2 The Second Stage Figure 12.24 shows the 741 second stage prepared for small-signal analysis. In this section we shall analyze the second stage to determine the values of the parameters of the equivalent circuit shown in Fig. 12.25.
Input Resistance The input resistance Ri2 can be found by inspection to be (12.96) Substituting for i from Eq. (12.91) gives (12.93) Finally, the CMRR can be found as the ratio of the differential transconductance found in Eq.
(12.83′) and the common-mode transconductance , (12.94) where is the transconductance of . Now substituting for from Eq. (12.89), we obtain (12.95) Before leaving this example, we observe that if the feedback were not present, the 2i term in Eq. (12.90) would be absent and the current i would become , which is times higher than that when feedback is present. In other words, common-mode feedback reduces i, hence the common-mode transconductance and the common-mode gain, by a factor Gmcm εm 2Ro ---------= Gm1 Gmcm CMRR Gm1 Gmcm ------------2gm1Ro εm ⁄ = ≡ gm1 Q1 Ro CMRR 2gm1 Ro9 Ro10 || ( ) εm ⁄ = βP vicm 2Ro ⁄ ( ) βP βP.
12.16 Show that if the source of the imbalance in the current-mirror load is that while , the error is given by Evaluate for .
Ans.
12.17 Refer to Fig. 12.23 and assume that the bases of and are at approximately constant voltages (signal ground). Find , , and hence . Use for npn and 50 V for pnp tran-sistors. Use the bias current values in Table 12.1.
Ans.
; ; 12.18 Use the results of Exercises 12.16 and 12.17 to determine and CMRR of the 741 input stage.
What would the CMRR be if the common-mode feedback were not present? Assume .
Ans. mA/V; or 104.5 dB; without common-mode feedback, CMRR = 70.5 dB R1 R, R2 R ΔR + = = εm εm ΔR R re5 ΔR + + ------------------------------= εm ΔR R ⁄ 0.02 = εm 5.5 10 3 – × = Q9 Q10 Ro9 Ro10 Ro VA 125 V = Ro9 2.63 MΩ = Ro10 31.1 MΩ = Ro 2.43 MΩ = Gmcm βP 50 = Gmcm 1.13 10 6 – × = CMRR 1.68 105 × = EXERCISES Ri2 β16 1 + ( ) re16 R9 || β17 1 + ( ) re17 R8 + ( ) [ ] + { } = 1020 Chapter 12 Operational-Amplifier Circuits Substituting the appropriate parameter values yields Transconductance From the equivalent circuit of Fig. 12.25, we see that the transcon-ductance Gm2 is the ratio of the short-circuit output current to the input voltage. Short-circuiting the output terminal of the second stage (Fig. 12.24) to ground makes the signal current through the output resistance of Q13B zero, and the output short-circuit current becomes equal to the collector signal current of Q17 (ic17). This latter current can be easily related to vi2 as follows: (12.97) (12.98) (12.99) where we have neglected ro16 because ro16 R9. These equations can be combined to obtain (12.100) which, for the 741 parameter values, is found to be Gm2 = 6.5 mA/V.
Output Resistance To determine the output resistance Ro2 of the second stage in Fig.
12.24, we ground the input terminal and find the resistance looking back into the output terminal.
Figure 12.25 Small-signal equivalent-circuit model of the second stage.
Ri17 Figure 12.24 The 741 second stage prepared for small-signal analysis.
Ri2 4 MΩ.
ic17 αvb17 re17 R8 + --------------------= vb17 vi2 R9||Ri17 ( ) R9||Ri17 ( ) re16 + -------------------------------------= Ri17 β17 1 + ( ) re17 R8 + ( ) = Gm2 ic17 vi2 -------≡ 12.5 Small-Signal Analysis of the 741 1021 It follows that Ro2 is given by (12.101) where Ro13B is the resistance looking into the collector of Q13B while its base and emitter are connected to ground. It can be easily seen that (12.102) For the 741 component values we obtain Ro13B = 90.9 kΩ.
The second component in Eq. (12.101), Ro17, is the resistance seen looking into the collec-tor of Q17, as indicated in Fig. 12.26. Since the resistance between the base of Q17 and ground is relatively small, one can considerably simplify matters by assuming that the base is grounded. Doing this, we can use Eq. (12.84) to determine Ro17. For our case, the result is Combining Ro13B and Ro17 in parallel yields Ro2 = 81 kΩ.
Thévenin Equivalent Circuit The second-stage equivalent circuit can be converted to the Thévenin form, as shown in Fig. 12.27. Note that the stage open-circuit voltage gain is −Gm2Ro2. Figure 12.26 Definition of Ro17.
Ro2 Ro13B||Ro17 ( ) = Ro13B ro13B = Ro17 787 kΩ.
Figure 12.27 Thévenin form of the small-signal model of the second stage.
12.19 Use Eq. (12.96) to show that Ri2 4 MΩ.
12.20 Use Eqs. (12.97) to (12.100) to verify that Gm2 is 6.5 mA/V.
12.21 Verify that Ro2 81 kΩ.
12.22 Find the open-circuit voltage gain of the second stage of the 741.
Ans. −526.5 V/V EXERCISES 1022 Chapter 12 Operational-Amplifier Circuits 12.5.3 The Output Stage The 741 output stage is shown in Fig. 12.28 without the short-circuit-protection circuitry.
The stage is shown driven by the second-stage transistor Q17 and loaded with a 2-kΩ resis-tance. The circuit is of the AB class (Section 11.4), with the network composed of Q18, Q19, and R10 providing the bias of the output transistors Q14 and Q20. The use of this network rather than two diode-connected transistors in series enables biasing the output transistors at a low current (0.15 mA) in spite of the fact that the output devices are three times as large as the standard devices. This result is obtained by arranging that the current in Q19 is very small and thus its VBE is also small. We analyzed the dc bias in Section 12.4.7.
Another feature of the 741 output stage worth noting is that the stage is driven by an emit-ter follower Q23. As will be shown, this emitter follower provides added buffering, which makes the op-amp gain almost independent of the parameters of the output transistors.
Output Voltage Limits The maximum positive output voltage is limited by the satura-tion of current-source transistor Q13A. Thus, (12.103) which is about 1 V below VCC. The minimum output voltage (i.e., maximum negative ampli-tude) is limited by the saturation of Q17. Neglecting the voltage drop across R8, we obtain Figure 12.28 The 741 output stage without the short-circuit-protection circuitry. vOmax V CC V CEsat VBE14 – – = 12.5 Small-Signal Analysis of the 741 1023 (12.104) which is about 1.5 V above −VEE.
Small-Signal Model We shall now carry out a small-signal analysis of the output stage for the purpose of determining the values of the parameters of the equivalent-circuit model shown in Fig. 12.29. The model is shown fed by vo2, which is the open-circuit output voltage of the second stage. From Fig. 12.27, vo2 is given by (12.105) where Gm2 and Ro2 were previously determined as Gm2 = 6.5 mA/V and Ro2 = 81 kΩ. Resis-tance Rin3 is the input resistance of the output stage determined with the amplifier loaded with RL. Although the effect of loading an amplifier stage on its input resistance is negligible in the input and second stages, this is not the case in general in an output stage. Defining Rin3 in this manner enables correct evaluation of the voltage gain of the second stage, A2, as (12.106) To determine Rin3, assume that one of the two output transistors—say, Q20—is conducting a current of, say, 5 mA while Q14 is cutoff. It follows that the input resistance looking into the base of Q20 is approximately β20RL. Assuming β20 = 50, for RL = 2 kΩ, the input resis-tance of Q20 is 100 kΩ. This resistance appears in parallel with the series combination of the output resistance of Q13A (ro13A 280 kΩ) and the resistance of the Q18–Q19 network. The latter resistance is very small (about 160 Ω; see later: Exercise 12.23). Thus the total resistance in the emitter of Q23 is approximately (100 kΩ || 280 kΩ) or 74 kΩ and the input resistance Rin3 is given by which for β23 = 50 is Rin3 3.7 MΩ. Since Ro2 = 81 kΩ, we see that Rin3 Ro2, and the value of Rin3 will have little effect on the performance of the op amp. Still we can use the value obtained for Rin3 to determine the gain of the second stage using Eq. (12.106) as A2 = −515 V/V.
The value of A2 will be needed in Section 12.6 in connection with the frequency-response analysis. Continuing with the determination of the equivalent circuit-model-parameters, we note from Fig. 12.29 that Gv o3 is the open-circuit overall voltage gain of the output stage, (12.107) Figure 12.29 Model for the 741 output stage.
Rout Rin3 Gvo3vo2 vOmin V – EE V CEsat V EB23 V EB20 + + + = vo2 Gm2Ro2vi2 – = A2 vi3 vi2 ------≡ Gm2Ro2 – Rin3 Rin3 Ro2 + ----------------------= Rin3 β23 74 kΩ × Gvo3 vo vo2 -------RL ∞ = = 1024 Chapter 12 Operational-Amplifier Circuits With RL = ∞, the gain of the emitter-follower output transistor (Q14 or Q20) will be nearly unity. Also, with RL = ∞ the resistance in the emitter of Q23 will be very large. This means that the gain of Q23 will be nearly unity and the input resistance of Q23 will be very large.
We thus conclude that Gvo3 1.
Next, we shall find the value of the output resistance of the op amp, Rout. For this purpose refer to the circuit shown in Fig. 12.30. In accordance with the definition of Rout from Fig. 12.29, the input source feeding the output stage is grounded, but its resistance (which is the output resistance of the second stage, Ro2) is included. We have assumed that the output voltage vO is negative, and thus Q20 is conducting most of the current; transistor Q14 has there-fore been eliminated. The exact value of the output resistance will of course depend on which transistor (Q14 or Q20) is conducting and on the value of load current. Nevertheless, we wish to find an estimate of Rout.
As indicated in Fig. 12.30, the resistance seen looking into the emitter of Q23 is (12.108) Substituting Ro2 = 81 kΩ, β23 = 50, and re23 = 25/0.18 = 139 Ω yields Ro23 = 1.73 kΩ. This resistance appears in parallel with the series combination of ro13A and the resistance of the Q18–Q19 network. Since ro13A alone (0.28 MΩ) is much larger than Ro23, the effective resis-tance between the base of Q20 and ground is approximately equal to Ro23. Now we can find the output resistance Rout as (12.109) For β20 = 50, the first component of Rout is 34 Ω. The second component depends critically on the value of output current. For an output current of 5 mA, re20 is 5 Ω and Rout is 39 Ω. To this value we must add the resistance R7 (27 Ω) (see Fig. 12.13), which is included for short-circuit protection. The output resistance of the 741 is specified to be typically 75 Ω.
Figure 12.30 Circuit for finding the output resistance Rout.
Rout Ro23 Ro2 β23 1 + ----------------re23 + = Rout Ro23 β20 1 + ----------------re20 + = 12.5 Small-Signal Analysis of the 741 1025 12.23 Using a simple (rπ, gm) model for each of the two transistors Q18 and Q19 in Fig. E12.23, find the small-signal resistance between A and A′. (Note: From Table 12.1, IC18 = 165 μA and IC19 16 μA. Ans. 163 Ω 12.24 Figure E12.24 shows the circuit for determining the op-amp output resistance when vO is positive and Q14 is conducting most of the current. Using the resistance of the Q18–Q19 network calculated in Exercise 12.23 and neglecting the large output resistance of Q13A, find Rout when Q14 is sourcing an output current of 5 mA.
Ans. 14.4 Ω Figure E12.23 Rout Figure E12.24 EXERCISES 1026 Chapter 12 Operational-Amplifier Circuits Output Short-Circuit Protection If the op-amp output terminal is short-circuited to one of the power supplies, one of the two output transistors could conduct a large amount of current. Such a large current can result in sufficient heating to cause burnout of the IC (Chapter 11). To guard against this possibility, the 741 op amp is equipped with a special circuit for short-circuit protection. The function of this circuit is to limit the current in the output transistors in the event of a short circuit.
Refer to Fig. 12.13. Resistance R6 together with transistor Q15 limits the current that would flow out of Q14 in the event of a short circuit. Specifically, if the current in the emit-ter of Q14 exceeds about 20 mA, the voltage drop across R6 exceeds 540 mV, which turns Q15 on. As Q15 turns on, its collector robs some of the current supplied by Q13A, thus reduc-ing the base current of Q14. This mechanism thus limits the maximum current that the op amp can source (i.e., supply from the output terminal in the outward direction) to about 20 mA.
Limiting of the maximum current that the op amp can sink, and hence the current through Q20, is done by a mechanism similar to the one discussed above. The relevant circuit is composed of R7, Q21, Q24, and Q22. For the components shown, the current in the inward direction is limited also to about 20 mA. 12.6 Gain, Frequency Response, and Slew Rate of the 741 In this section we shall evaluate the overall small-signal voltage gain of the 741 op amp. We shall then consider the op amp’s frequency response and its slew-rate limitation.
12.6.1 Small-Signal Gain The overall small-signal gain can be found from the cascade of the equivalent circuits derived in the preceding sections for the three op-amp stages. This cascade is shown in Fig. 12.31, loaded with RL = 2 kΩ, which is the typical value used in measuring and specify-ing the 741 data. The overall gain can be expressed as (12.110) (12.111) Figure 12.31 Cascading the small-signal equivalent circuits of the individual stages for the evaluation of the overall voltage gain.
vo vi ----vi2 vi -----vo2 vi2 ------vo vo2 ------= Gm1 Ro1||Ri2 ( ) Gm2Ro2 – ( )Gvo3 RL RL Rout + --------------------– = Rin3 Rout Gvo3vo2 12.6 Gain, Frequency Response, and Slew Rate of the 741 1027 Using the values found earlier yields for the overall open-circuit voltage gain, (12.112) 12.6.2 Frequency Response The 741 is an internally compensated op amp. It employs the Miller compensation tech-nique, studied in Section 10.13.3, to introduce a dominant low-frequency pole. Specifically, a 30-pF capacitor (CC) is connected in the negative-feedback path of the second stage. An approximate estimate of the frequency of the dominant pole can be obtained as follows.
From Miller’s theorem (Section 9.4.4), we see that the effective capacitance due to CC between the base of Q16 and ground is (see Fig. 12.13) (12.113) where A2 is the second-stage gain. Use of the value calculated for A2 in Section 12.5.3, A2 = −515, results in Cin = 15,480 pF. Since this capacitance is quite large, we shall neglect all other capacitances between the base of Q16 and signal ground. The total resistance between this node and ground is (12.114) Thus the dominant pole has a frequency fP given by (12.115) It should be noted that this approach is equivalent to using the approximate formula in Eq. (10.116).
As discussed in Section 10.13.3, Miller compensation provides an additional advanta-geous effect, namely, pole splitting. As a result, the other poles of the circuit are moved to very high frequencies. This has been confirmed by computer-aided analysis [see Gray et al (2000)].
Assuming that all nondominant poles are at very high frequencies, the calculated values give rise to the Bode plot shown in Fig. 12.32, where f3dB = fP. The unity-gain bandwidth f t can be calculated from (12.116) Thus, (12.117) Although this Bode plot implies that the phase shift at f t is −90° and thus that the phase margin is 90°, in practice a phase margin of about 80° is obtained. The excess phase shift (about 10°) is due to the nondominant poles. This phase margin is sufficient to provide stable operation of closed-loop amplifiers with any value of feedback factor β. This convenience of A0 vo vi ----≡ 476.1 – 526.5 – ( ) 0.97 × × 243,147 V/V = = ≡107.7 dB Cin CC 1 A2 + ( ) = Rt Ro1 || Ri2 = 6.7 MΩ || 4 MΩ = 2.5 MΩ = f P 1 2πCinRt -------------------4.1 Hz = = ft A0f3dB = f t 243,147 4.1 × 1 MHz = 1028 Chapter 12 Operational-Amplifier Circuits use of the internally compensated 741 is achieved at the expense of a great reduction in open-loop gain and hence in the amount of negative feedback. In other words, if one requires a closed-loop amplifier with a gain of 1000, then the 741 is overcompensated for such an application, and one would be much better off designing one’s own compensation (assuming, of course, the availability of an op amp that is not already internally compensated).
12.6.3 A Simplified Model Figure 12.33 shows a simplified model of the 741 op amp in which the high-gain second stage, with its feedback capacitance CC, is modeled by an ideal integrator. In this model, the gain of the second stage is assumed to be sufficiently large that a virtual ground appears at its input. For this reason the output resistance of the input stage and the input resistance of the second stage have been omitted. Furthermore, the output stage is assumed to be an ideal unity-gain follower. Except for the presence of the output stage, this model is identical to that which we used for the two-stage CMOS amplifier in Section 12.1.4 (Fig. 12.3).
Analysis of the model in Fig. 12.33 gives (12.118) Figure 12.32 Bode plot for the 741 gain, neglecting nondominant poles.
Figure 12.33 A simple model for the 741 based on modeling the second stage as an integrator.
A s ( ) Vo s ( ) Vi s ( ) -------------≡ Gm1 sCC ---------= 12.6 Gain, Frequency Response, and Slew Rate of the 741 1029 Thus, (12.119) and the magnitude of gain becomes unity at ω = ωt, where (12.120) Substituting Gm1 = 1/5.26 mA/V and CC = 30 pF yields (12.121) which is equal to the value calculated before. It should be pointed out, however, that this model is valid only at frequencies f f3dB. At such frequencies the gain falls off with a slope of −20 dB/decade, just like that of an integrator.
12.6.4 Slew Rate The slew-rate limitation of op amps is discussed in Chapter 2. Here we shall illustrate the origin of the slewing phenomenon in the context of the 741 circuit. This development is sim-ilar to that we presented for the CMOS op-amp in Section 12.1.6.
Consider the unity-gain follower of Fig. 12.34 with a step of, say, 10 V applied at the input. Because of amplifier dynamics, its output will not change in zero time. Thus immedi-ately after the input is applied, almost the entire value of the step will appear as a differential signal between the two input terminals. This large input voltage causes the input stage to be overdriven, and its small-signal model no longer applies. Rather, half the stage cuts off and the other half conducts all the current. Specifically, reference to Fig. 12.13 shows that a large positive differential input voltage causes Q1 and Q3 to conduct all the available bias current (2I) while Q2 and Q4 will be cut off. The current mirror Q5, Q6, and Q7 will still func-tion, and Q6 will produce a collector current of 2I.
Using the observations above, and modeling the second stage as an ideal integrator, results in the model of Fig. 12.35. From this circuit we see that the output voltage will be a ramp with a slope of 2I/CC: (12.122) Figure 12.34 A unity-gain follower with a large step input. Since the output voltage cannot change instan-taneously, a large differential voltage appears between the op-amp input terminals.
A jω ( ) Gm1 jωCC -------------= ωt Gm1 CC ---------= ft ωt 2π ------ 1 MHz = vO t ( ) 2I CC ------t = 1030 Chapter 12 Operational-Amplifier Circuits Thus the slew rate SR is given by (12.123) For the 741, I = 9.5 μA and CC = 30 pF, resulting in SR = 0.63 V/μs.
It should be pointed out that this is a rather simplified model of the slewing process.
More detail can be found in Gray et al., (2000).
12.6.5 Relationship Between ft and SR A simple relationship exists between the unity-gain bandwidth f t and the slew rate SR. This relationship is obtained by combining Eqs. (12.120), (12.123), and (12.124) and then using Eq. (12.83′) to obtain (12.125) Now, since gm1 is the transconductance of each of Q1 through Q4, (12.126) Thus, (12.127) As a check, for the 741 we have Figure 12.35 Model for the 741 op amp when a large positive differential signal is applied.
SR 2I CC ------= 12.25 Use the value of the slew rate calculated above to find the full-power bandwidth fM of the 741 op amp. Assume that the maximum output is ±10 V.
Ans. 10 kHz EXERCISE SR 2I Gm1 ---------ωt = SR 4I gm1 --------ωt = gm1 I VT -----= SR 4V Tωt = SR 4 25 10 3 – 2π 10 6 × × × × 0.63 V/μs = = 12.7 Modern Techniques for the Design of BJT Op Amps 1031 which is the result obtained previously. Observe that Eq. (12.127) is of the same form as Eq. (12.42), which applies to the two-stage CMOS op amp. Here, 4VT replaces VOV. Since, typi-cally, VOV will be two to three times the value of 4VT , a two-stage CMOS op amp with an ft equal to that of the 741 exhibits a slew rate that is two to three times as large as that of the 741.
A general form for the relationship between SR and ωt for an op amp with a structure similar to that of the 741 (including the two-stage CMOS circuit) is (12.128) where a is the constant of proportionality relating the transconductance of the first stage Gm1, to the total bias current of the input differential stage. That is, for the 741 circuit Gm1 = a(2I), while for the CMOS circuit of Fig. 12.1, Gm1 = aI.3 For a given ωt, a higher value of SR is obtained by making a smaller; that is, the total bias current is kept con-stant and Gm1 is reduced. This is a viable technique for increasing slew rate. It is referred to as the Gm-reduction method (see Exercise 12.27).
12.7 Modern Techniques for the Design of BJT Op Amps Although the ingenious techniques employed in the design of the 741 op amp have stood the test of time, they are now more than 40 years old! Technological advances have resulted in changes in the user requirements of general-purpose bipolar op amps. The resulting more demanding specifications have in turn posed new challenges to analog IC designers who, as they have done repeatedly before, are responding with new and exciting circuits. In this section we present a sample of recently developed design techniques. For more on this rather advanced topic the reader is referred to the Analog Circuits section of the bibliography in Appendix G.
12.7.1 Special Performance Requirements Many of the special performance requirements stem from the need to operate modern op amps from power supplies of much lower voltages. Thus while the 741-type op amp operated from 3The difference is just a matter of notation; We used I to denote the total bias current of the input differential stage of the CMOS circuit, and we used 2I for the 741 case!
SR ωt a ⁄ = 12.26 Consider the integrator model of the op amp in Fig. 12.33. Find the value of the resistor that, when connected across CC, provides the correct value of the dc gain.
Ans. 1279 MΩ D12.27 If a resistance RE is included in each of the emitter leads of Q3 and Q4 show that SR = 4(VT + IRE/ 2)ωt.
Hence find the value of RE that would double the 741 slew rate while keeping ωt and I unchanged.
What are the new values of CC, the dc gain, and the 3-dB frequency?
Ans. 5.26 kΩ; 15 pF; 101.7 dB (a 6-dB decrease); 8.2 Hz EXERCISES 1032 Chapter 12 Operational-Amplifier Circuits power supplies, many modern BJT op amps are required to operate from a single power supply of only 2 V to 3 V. This is done for a number of reasons, including the following.
1. Modern small-feature-size IC fabrication technologies require low power-supply voltages. 2. Compatibility must be achieved with other parts of the system that use low-voltage supplies.
3. Power dissipation must be minimized, especially for battery-operated equipment.
As Fig. 12.36 indicates, there are two important changes: the use of a single ground-refer-enced power supply , and the low value of . Both of these requirements give rise to changes in performance specifications and pose new design challenges. In the following we discuss two of the resulting changes.
Rail-to-Rail Input Common-Mode Range Recall that the input common-mode range of an op amp is the range of common-mode input voltages for which the op amp operates properly and meets its performance specifications, such as voltage gain and CMRR. Op amps of the 741 type operate from supplies and exhibit an input common-mode range that extends to within a couple of volts of each supply. Such a gap between the input common-mode range and the power supply is obviously unacceptable if the op amp is to be operated from a single supply that is only 2 V to 3 V. Indeed we will now show that these single-sup-ply, low-voltage op amps need to have an input common-mode range that extends over the entire supply voltage, 0 to , referred to as rail-to-rail input common mode range.
Consider first the inverting op-amp configuration shown in Fig. 12.37(a). Since the posi-tive input terminal is connected to ground (which is the voltage of the negative-supply rail), Figure 12.36 Power supply requirements have changed considerably. Modern BJT op amps are required to operate from a single supply VCC of 2 to 3 V.
Figure 12.37 (a) In the inverting configuration, the + ive op-amp input is connected to ground; thus it is imperative that the input common-mode range includes ground. (b) In the unity-gain follower configuration, vICM = vI ; thus it is highly desirable for the input common-mode range to include ground and VCC.
Modern VCC 3 V 741 VCC 15 V VEE 15 V 15-V ± VCC VCC 15-V ± VCC VCC vO vI VCC R2 R1 vO vI (a) (b) 12.7 Modern Techniques for the Design of BJT Op Amps 1033 ground voltage has to be within the allowable input common-mode range. In fact, because for positive output voltages the voltage at the inverting input terminal can go slightly nega-tive, the input common-mode range should extend below the negative-supply rail (ground).
Next consider the unity-gain voltage follower obtained by applying 100% negative feed-back to an op amp, as shown in Fig. 12.37(b). Here the input common-mode voltage is equal to the input signal . To maximize the usefulness of this buffer amplifier, its input signal should be allowed to extend from 0 to , especially since is only 2 to 3 V. Thus the input common-mode range should include also the positive supply rail. As will be seen shortly, modern BJT op amps can operate over an input common-mode voltage range that extends a fraction of a volt beyond its two supply rails: that is, more than rail-to-rail operation!
Near Rail-to-Rail Output Signal Swing In the 741 op amp, we were satisfied with an output that can swing to within 2 V or so of each of the supply rails. With a supply of , this capacity resulted in a respectable output range. However, to limit the output swing to within 2 V of the supply rails in an op amp operating from a single 3-V supply would result in an unusable device! Thus, here too, we require near rail-to-rail operation. As we shall see in Section 12.7.5, this requirement forces us to adopt a whole new approach to output-stage design.
Device Parameters The technology we shall use in the examples, exercises, and prob-lems for this section has the following characteristics: VA = 30 V = 20 V For both, and . It is important to note that we will assume that for this technology, the transistor will remain in the active mode for as low as 0.1 V (in other words, that 0.6 V is needed to forward-bias the CBJ).
12.7.2 Bias Design As in the 741 circuit, the bias design of modern BJT amplifiers makes extensive use of cur-rent mirrors and current-steering circuits (Sections 7.4 and 7.5). Typically, however, the bias currents are small (in the micro amp range). Thus, the Widlar current source (Section 7.5.5) is especially popular here. As well, emitter-degeneration resistors (in the tens-of-kilohm range) are frequently used.
Figure 12.38 shows a self-biased current-reference source that utilizes a Widlar cir-cuit formed by , , and , and a current mirror with matched emitter-degeneration resistors and . The circuit establishes a current I in each of the four transistors, with the value of I determined as follows. Neglecting base currents and ’s for simplicity, we write Thus, vI vI VCC VCC 15 V ± 13-V ± npn Transistors: β 40 = pnp Transistors: β 10 = VA VBE 0.7 V VCEsat 0.1 V VCE Q1 Q2 R2 Q3 Q4 – R3 R4 ro VBE1 VT ln I IS1 ------⎝ ⎠ ⎛ ⎞ = VBE2 VT ln I IS2 ------⎝ ⎠ ⎛ ⎞ = VBE1 VBE2 V = T ln IS2 IS1 ------⎝ ⎠ ⎛ ⎞ – 1034 Chapter 12 Operational-Amplifier Circuits But, Thus, (12.129) Thus the value of I is determined by and the ratio of the emitter areas of and Also, observe that I is independent of a highly desirable outcome. Neglecting the tem-perature dependence of we see that I is directly PTAT (proportional to the absolute tem-perature T ). It follows that transistors biased by I or mirrored versions of it will exhibit ’s that are constant independent of temperature!
The circuit in Fig. 12.38 provides a bias line with a voltage equal to . This can be used to bias other transistors and thus generate currents proportional to I by appropriately scaling their emitter areas. Similarly, the circuit provides a bias line at a voltage below . This bias line can be used to bias other transistors and thus generate constant currents proportional to I by appropriately scaling emitter areas and emitter-degeneration resistances. These ideas are illustrated in Fig. 12.39.
R4 CC R3 Q3 Q4 VBIAS 2 Q2 Q1 VBIAS 1 R2 I I Figure 12.38 A self-biased current-reference source utilizing a Widler circuit to generate I = VT/R2ln(IS2/IS1) The bias voltages VBIAS1 and VBIAS2 are utilized in other parts of the op-amp circuit for biasing other transistors.
VBE1 VBE2 IR2 = – I VT R2 ------ ln IS2 IS1 ------⎝ ⎠ ⎛ ⎞ = R2 Q1 Q2.
VCC, R2, gm D12.28 Design the circuit in Fig. 12.38 to generate a current I = 10 μA. Utilize transistors and having their areas in a 1:2 ratio. Assume that and are matched and design for a 0.2-V drop across each of and Specify the values of and Ans. 1.73 ; 20 ; 20 Q1 Q2 Q3 Q4 R3 R4.
R2, R3, R4.
kΩ kΩ kΩ EXERCISE VBIAS1 VBE1 VBIAS2 IR3 VEB3 + ( ) VCC 12.7 Modern Techniques for the Design of BJT Op Amps 1035 12.7.3 Design of the Input Stage to Obtain Rail-to-Rail VICM The classical differential input stage with current-mirror load is shown in Fig. 12.40(a). This is essentially the core of the 741 input stage, except that here we are using a single positive power supply. As well, the CMOS counterpart of this circuit is utilized in nearly every VBIAS 2 VCC Q8 Q9 Q10 R8 I8 I9 I10 R9 R10 VBIAS 1 Q5 Q6 Q7 R5 I5 I6 I7 R6 R7 Figure 12.39 The bias lines VBIAS1 and VBIAS2 provided by the circuit in Fig. 12.38 are utilized to bias other transistors and generate constant current I5 to I10. Both the transistor area and the emitter degener-ation resistance value have to be appropriately scaled.
D12.29 Refer to the circuit in Fig. 12.39 and assume that the line is connected to the correspond-ing line in Fig. 12.38. It is required to generate currents , , and . Specify the required emitter areas of , , and as ratios of the emitter area of . Also specify the values required for , , and . Use the values of and found in Exercise 12.28. Ignore base currents.
Ans. 1, 2, 0.5; 20 , 10 , 40 VBIAS2 I8 10 μA = I9 20 μA = I10 5 μA = Q8 Q9 Q10 Q3 R8 R9 R10 R3 R4 kΩ kΩ kΩ EXERCISE vo Q1 Q2 Q5 Q3 Q4 I VBIAS VCC vo Q1 Q2 Q5 I VBIAS (a) (b) VCC RC RC Figure 12.40 For the input common-mode range to include ground voltage, the classical current-mirror-loaded input stage in (a) has to be replaced with the resistively-loaded con-figuration in (b) with the dc voltage drop across RC limited to 0.2–0.3 V.
1036 Chapter 12 Operational-Amplifier Circuits CMOS op-amp design (see Section 12.1). Unfortunately, this very popular circuit does not meet our requirement of rail-to-rail common-mode operation.
Consider first the low end of the input common-mode range. The value of is lim-ited by the need to keep in the active mode. Specifically, since the collector of is at a voltage V, we see that the voltage applied to the base of cannot go lower than 0.1 V without causing the collector–base junction of to become forward biased.
Thus V, and the input common-mode range does not include ground voltage as required.
The only way to extend to 0 V is to lower the voltage at the collector of . This in turn can be achieved only by abandoning the use of the current-mirror load and utilizing instead resistive loads, as shown in Fig. 12.40(b). Observe that in effect we are going back to the resistively loaded differential pair with which we began our study of differential amplifi-ers in Chapter 8!
The minimum allowed value of in the circuit of Fig. 12.40(b) is still of course lim-ited by the need to keep and in the active mode. This in turn is achieved by avoiding values that cause the base voltages of and to go below their collector voltages by more than 0.6 V, where is the voltage drop across each of and . Now if is selected to be 0.2 to 0.3 V, then will be V to , which is exactly what we need.
The major drawback of replacing the current-mirror load with resistive loads is that the differential gain realized is considerably reduced, where we have neglected for simplicity. Thus for , the gain realized is only 12 V/V. As we will see shortly, this low-gain problem can be solved by cascoding.
Next consider the upper end of the input common-mode range. Reference to the circuit in Fig. 12.40(b) shows that the maximum voltage that can be applied to the bases of and is limited by the need to keep the current-source transistor in the active mode. This in turn is achieved by ensuring that the voltage across , does not fall below 0.1 V or so. Thus the maximum value of will be a voltage or approximately 0.7 V lower, That is, the upper end of the input common-mode range is at least 0.8 V below , a severe limitation.
To recap, while the circuit in Fig. 12.40(b) has of a few tenths of a volt below the negative power-supply rail (at ground voltage), the upper end of is rather far from , VICMmin Q1 Q1 VBE3 0.7 Q1 Q1 VICMmin 0.1 = VICMmin Q1 VICM Q1 Q2 VICM Q1 Q2 VICMmin VRC 0.6 V – = VRC RC1 RC2 VRC VICMmin 0.4 – 0.3 V – vo vid ------gm1 2 , RC – = I 2 ⁄ VT --------- RC VRC VT --------– = – = ro VRC 0.3 V = Q1 Q2 Q5 VEC5 VICM VEB1 2 , VICMmax VCC 0.1 – 0.7 VCC 0.8 – = – = VCC VICMmin VICM VCC 0.3 VICM VCC 0.8 – ≤ ≤ – 12.7 Modern Techniques for the Design of BJT Op Amps 1037 where we have assumed . To extend the upper end of , we adopt a solution similar to that used in the CMOS case (Section 12.2.6, Fig. 12.11), namely, we utilize a par-allel complementary input stage. Toward that end, note that the npn version of the circuit of Fig. 12.40(b), shown in Fig. 12.41, has a common-input range of where we have assumed that . Thus, as expected, the high end meets our specifi-cations and in fact is above the positive supply rail by 0.3 V. The lower end, however, does not; but this should cause us no concern because the lower end will be looked after by the pnp pair. Finally, note that there is a range of in which both the pnp and the npn cir-cuits will be active and properly operating, Figure 12.42 shows an input stage that achieves more than rail-to-rail input common-mode range by utilizing a pnp differential pair ( , ) and an npn differential pair ( , ), connected in parallel. To keep the diagram simple, we are not showing the parallel connec-tion of the input terminals; the + input terminals are assumed to be connected together, and similarly for the – input terminals. In order to increase the gain obtained from the resistively loaded differential pairs, a folded cascode stage is added. Here and are the resistive loads of the pnp pair , and are its cascode transistors. Similarly, and are the resistive loads of the npn pair and are its cascode transistors.
Observe that the cascode transistors do “double duty.” For instance, operate as the cascode devices for and at the same time as current-source loads for . A similar statement can be made about . The output voltage of the first stage, , is taken between the collectors of the cascode devices.
For , the npn stage will be inactive and the gain is determined by the transconductance of the pair together with the output resistance seen between the collectors of the cascode transistors. At the other end of , that is, , the stage will be inactive, and the gain will be determined by the transconductance of the pair and the output resistance between the collectors of the cascode devices. In the overlap region both the pnp and npn stages will be active and their effective transconductances add up, thus resulting in a higher gain. The dependence of the differential gain on the input common-mode is usually undesirable VRC 0.3 V = VICM RC RC vo VCC VBIAS Q3 Q4 Q6 Figure 12.41 The complement of the circuit in Fig. 12.40(b). While the input common-mode range of the circuit in Figure 12.40(b) extends below ground, here it extends above VCC. Connecting the two circuits in parallel, as will be shown, results in a rail-to-rail VICM range.
0.8 VICM VCC 0.3 + ≤ ≤ VRC 0.3 V = VICM 0.8 VICM VCC 0.8 – ≤ ≤ Q1 Q2 Q3 Q4 R7 R8 Q1 Q2 – Q7 Q8 – R9 R10 Q3 Q4, – Q9 Q10 – Q7 Q8 – Q1 Q2 – Q9 Q10 – Q9 Q10 – vod VICM 0.8 V Gm Q1 Q2 – VICM VICM VCC 0.8 – Q1 Q2 – Gm Q3 Q4 – 0.8 VICM VCC 0.8, – ≤ ≤ Gm VICM 1038 Chapter 12 Operational-Amplifier Circuits and can be reduced considerably by arranging that one of the two differential pairs is turned off when the other one is active.4 4This is done in the NE5234 op amp, whose circuit is described and analyzed in great detail in Gray et al., (2009).
R9 VCC VB R10 Q10 Q9 VBIAS 3 VB Q8 Q7 vO2 vO1 vod R8 R7 Q1 Q2 Q5 VBIAS 1 npn pair pnp pair Cascode Q3 Q4 Q6 VBIAS2 Figure 12.42 Input stage with rail-to-rail input common-mode range and a folded-cascode stage to increase the gain. Note that all the bias voltages including VBIAS3 and VB are generated elsewhere on the chip.
It is required to find the input resistance and the voltage gain of the input stage shown in Fig. 12.42. Let so that the pair is off. Assume that supplies 10 μA, that each of to is biased at 10 μA, and that all four cascode transistors are operating in the active mode. The input resis-tance of the second stage of the op amp (not shown) is . The emitter-degeneration resistances are , and Recall that the device parameters are V, V.
Solution Since the stage is fully balanced, we can use the differential half-circuit shown in Fig. 12.43(a). The input resistance is twice the value of where VICM 0.8 V Q3 Q4 – Q5 Q7 Q10 RL 2 MΩ = R7 R8 20 kΩ = = R9 R10 30 kΩ.
= = βN 40, = βP 10, = VAn 30 = VAp 20 = Rid rπ1, Rid 2rπ1 2βP gm1 ⁄ = = gm1 IC1 VT -------5 10 6 – × 25 10 3 – × ----------------------0.2 mA/V = = = Example 12.5 12.7 Modern Techniques for the Design of BJT Op Amps 1039 Thus, To find the short-circuit transconductance, we short the output to ground as shown in Fig. 12.43(b) and find as At node X we have four parallel resistances to ground, Obviously and are very large and can be neglected. Then, the portion of that flows into the emitter proper of can be found from and the output short-circuit current is RL 2 Q1 Q1 Q7 R9 (b) (a) vid 2 vod Ro9 Ro7 2 Rid 2 Q7 R7 R7 Q9 vid re7 X ro7 ro1 ie7 io 2 gm1 vid 2 Figure 12.43 (a) Differential half circuit for the input stage shown in Fig. 12.42 with VICM 0.8 V. (b) Determining Gm1 io vid 2 ⁄ ( ) ⁄ = Rid 2 10 × 0.2 ---------------100 kΩ = = Gm1 Gm1 ic7 vid 2 ⁄ -------------= ro1 VAp IC1 -----------20 V 5 μA -------------4 MΩ = = = R7 20 kΩ = ro7 VAn IC7 --------30 V 10 μA ----------------3 MΩ = = = re7 1 gm7 --------VT IC7 -------25 mV 10 μA ----------------2.5 kΩ = = = ro1 ro7 gm1 vid 2 ⁄ ( ) Q7 ie7 gm1 vid 2 ------⎝ ⎠ ⎛ ⎞ R7 R7 re7 + -------------------⎝ ⎠ ⎛ ⎞ gm1 vid 2 ------⎝ ⎠ ⎛ ⎞ 20 20 2.5 + -------------------0.89gm1 vid 2 ------⎝ ⎠ ⎛ ⎞ = = io io ie7 0.89gm1 vid 2 ⁄ ( ) = 1040 Chapter 12 Operational-Amplifier Circuits Example 12.5 continued Thus, To find the voltage gain, we need to determine the total resistance between the output node and ground for the circuit in Fig. 12.43(a), The resistance is the output resistance of , which has an emitter-degeneration resistance Thus can be found using Eq. (7.50), where Thus The resistance is the output resistance of which has an emitter-degeneration resistance Thus, where Thus, Gm1 io vid 2 ⁄ -------------0.89gm1 0.89 0.2 0.18 mA/V = × = = ≡ R Ro9 Ro7 RL 2 ⁄ ( ) || || = Ro9 Q9 R9.
Ro9 Ro9 ro9 R9 rπ 9 || ( ) 1 gm9 + ro9 ( ) + = ro9 VAp IC9 -----------20 V 10 μA ----------------2 MΩ = = = gm9 IC9 VT -------10 μA 25 mV ----------------0.4 mA/V = = = rπ 9 βP gm9 --------10 0.4 mA/V ------------------------25 kΩ = = = Ro9 2 30 25 || ( ) 10 3 – × 1 0.4 2 103 × × + ( ) + = 12.9 MΩ = Ro7 Q7, R7 ro1 || ( ) R7.
Ro7 ro7 R7 rπ7 || ( ) 1 gm7 + ro7 ( ) + = ro7 VAn IC7 --------30 V 10 μA ---------------3 MΩ = = = gm7 IC7 VT -------10 μA 25 mV ----------------0.4 mA/V = = = rπ7 βN gm7 --------40 0.4 -------100 kΩ = = = Ro7 3 20 100 || ( ) 10 3 – × 1 0.4 3 103 × × + ( ) + = 23 MΩ = RL 2 ------2 MΩ 2 ---------------1 MΩ = = 12.7 Modern Techniques for the Design of BJT Op Amps 1041 12.7.4 Common-Mode Feedback to Control the dc Voltage at the Output of the Input Stage For the cascode circuit in Fig. 12.42 to operate properly and provide high output resistance and thus high voltage gain, the cascode transistors Q7 through Q10 must operate in the active mode at all times. However, relying solely on matching will not be sufficient to ensure that the currents supplied by and are exactly equal to the currents supplied by and Any small mismatch between the two sets of currents will be multiplied by the large output resistance between each of the collector nodes and ground, and thus there will be large changes in the voltages and These changes in turn can cause one set of the current sources (i.e., or ) to saturate. We therefore need a circuit that detects the change in the dc or common-mode component of and (12.130) and adjusts the bias voltage on the bases of and to restore current equality. This negative-feedback loop should be insensitive to the differential signal components of and otherwise it would reduce the differential gain. Thus the feedback loop should pro-vide common-mode feedback (CMF).
Figure 12.44 shows the cascode circuit with the CMF circuit shown as a black box. The CMF circuit accepts and as inputs and provides the bias voltage as output. In a particular implementation we will present shortly, the CMF circuit has the transfer characteristic (12.131) By keeping higher than by only 0.4 V, the CMF circuit ensures that and remain active (0.6 V is needed for saturation).
The nominal value of is determined by the quiescent current of Q7 through Q10, the quiescent value of and and the value of and The resulting nominal value of and the corresponding value of from Eq. (12.131) are designed to ensure that and operate in the active mode. Here, it is important to recall that is determined by the rest of the op-amp bias circuit.
To see how the CMF circuit regulates the dc voltage , assume that for some reason is higher than it should be and as a result the currents of and exceed the currents supplied by and by an increment When multiplied by the total resistance between each of the output nodes and ground, the increment will result in a large The total resistance R can now be found as Finally, we can find the voltage gain as R 12.9 23 1 0.89 MΩ = || || = Ad vod 2 ⁄ vid 2 ⁄ --------------Gm1R1 = = 0.18 0.89 103 × × 160 V/V = = Q9 Q10 Q7 Q8.
I Δ vO1 vO2.
Q7 Q8 – Q9 Q10 – VCM vO1 vO2, VCM 1 2 --- vO1 vO2 + ( ) = Q7 Q8, VB, vO1 vO2; vO1 vO2 VB VB VCM 0.4 + = VB VCM Q7 Q8 VB I1 I2, R7 R8.
VB VCM Q9 Q10 VBIAS3 VCM VB Q7 Q8 Q9 Q10 I.
Δ I Δ 1042 Chapter 12 Operational-Amplifier Circuits negative voltage increment in and The CMF circuit responds by lowering to the value that restores the equality of currents. The change in needed to restore equilibrium is usually small (see Example 12.6 below) and according to Eq. (12.131) the corresponding change in will be equally small. Thus we see negative feedback in action: It minimizes the initial change and thus keeps nearly constant at its nominal value, which is designed to operate Q7 through Q10 in the active region.
We conclude by considering briefly a possible implementation of the CMF circuit. Figure 12.45 shows the second stage of an op-amp circuit. The circuit is fed by the outputs of the input stage, and VCC R10 Q9 (determined by the op amp bias network) Q8 Q7 R8 R9 Q10 vO1 I3 I4 vO2 Common-Mode Feedback Circuit In Out I1 I2 R7 VB VBIAS3 Figure 12.44 The cascode output circuit of the input stage and the CMF circuit that responds to the com-mon-mode component by adjusting VB so that Q7–Q8 conduct equal currents to Q9–Q10, and Q7–Q10 operate in the active mode.
VCM 1 2 -- vO1 vO2 + ( ) = vO1 vO2.
VB VB VCM VCM vO2 vO1 VBIAS vo3 ID VB VE Q13 Q14 Q11 D Q12 Q15 Figure 12.45 An op amp second stage incorporating the common-mode feedback circuit for the input stage. Note that the circuit generates the voltage VB needed to bias the cascode circuit in the first stage.
Diode D is a Schottky-barrier diode which exhibits a forward voltage drop of about 0.4V.
vO1 vO2, 12.7 Modern Techniques for the Design of BJT Op Amps 1043 In addition to amplifying the differential component of the circuit generates a dc volt-age , To see how the circuit works, note that and are emitter followers that minimize the loading of the second stage on the input stage. The emitter followers deliver to the bases of the differential pair voltages that are almost equal to and but dc shifted by . Thus the voltage at the emitters of will be which reduces to The voltage is simply equal to plus the voltage drop of diode The latter is a Schottky barrier diode (SBD), which features a low forward drop of about 0.4 V. Thus, as required.
vO1 VCM vd 2 ⁄ + = vO2 VCM vd 2 ⁄ – = vd, VB VB VCM 0.4 + = Q11 Q12 Q13 Q14 – vO1 vO2 VEB11,12 Q13 Q14 – VE VCM VEB11,12 VBE13,14 – + = VE VCM VB VE D1.
VB VE VD VCM 0.4 + = + = Consider the operation of the circuit in Fig. 12.44. Assume that and thus the npn input pair (Fig. 12.42) is off. Hence Also assume that only dc voltages are present and thus Each of to is biased at 10 μA, , and Neglect base currents and neglect the loading effect of the CMF circuit on the output nodes of the cascode circuit. The CMF circuit provides . (a) Determine the nominal values of and . Does the value of ensure operation in the active mode for Q7 through Q10? (b) If the CMF circuit were not present, what would be the change in and (i.e., in ) as a result of a current mismatch between and ? Use the output resistance values found in Example 12.5.
(c) Now, if the CMF circuit is connected, what change will it cause in to eliminate the current mis-match ? What is the corresponding change in from its nominal value?
Solution (a) The nominal value of is found as follows: VICM 0.8 V I3 I4 0.
= = I1 I2 5 μA.
= = Q7 Q10 VCC 3 V, = VBIAS3 VCC 1 – = R7 R8 20 kΩ, = = R9 R10 30 kΩ.
= = VB VCM 0.4 + = VB VCM VCM vO1 vO2 VCM I 0.3 μA = Δ Q7 Q8 – Q9 Q10 – VB I Δ VCM VB VB VBE7 IE7 I1 + ( )R7 + = 0.7 10 5 + ( ) 10 3 – × 20 × + 1 V = Example 12.6 1044 Chapter 12 Operational-Amplifier Circuits Example 12.6 continued The nominal value of can now be found from For to be active, that is, For to be active That is, resulting in Thus, for all four cascode transistors to operate in the active mode, Thus the nominal value of 0.6 V ensures active mode operation.
(b) For where is the output resistance between the collectors of and and ground, In Example 12.5 we found that and ; thus, Thus, Now if is positive, which exceeds the 2.6 V maximum allowed value before saturate. If is negative, which is far below the V needed to keep in the active mode. Thus, in the absence of CMF, a current mismatch of would cause one set of the cascode transistors (depending on the polarity of ) to saturate.
VCM VCM VB 0.4 1 0.4 0.6 V = – = – = Q7 Q8 – VCM VB7 8 , 0.6 – > VCM 0.4 V > Q9 Q10 – VCM VBIAS3 0.6 + < VCM VCC 1 – 0.6 + < VCM 2.6 V < 0.4 V VCM 2.6 V < < IC9 IC7 IC10 IC8 I, Δ = – = – VCM IRo1 Δ = Δ Ro1 Q7 Q9 Ro1 Ro7 Ro9 || = Ro7 23 MΩ = Ro9 12.9 = Ro1 23 12.9 8.3 MΩ = || = VCM 0.3 8.3 2.5 V × = Δ VCM Δ VCM 0.6 2.5 3.1 V = + = Q9 Q10 – VCM Δ VCM 0.6 2.5 1.9 V – = – = +0.4 Q7 Q8 – 0.3 μA ± I Δ 12.7 Modern Techniques for the Design of BJT Op Amps 1045 12.7.5 Output-Stage Design for Near Rail-to-Rail Output Swing As mentioned earlier, modern low-voltage bipolar op amps cannot afford to use the classical emitter-follower-based class AB output stage; it would consume too much of the power sup-ply voltage. Instead, a complementary pair of common-emitter transistors are utilized, as shown in Fig. 12.46. The output transistors and are operated in a class AB fashion.
Typically, can be as high as 10 mA to 15 mA and is determined by and For where the quiescent current is normally a fraction of a milliamp. The output stage in Fig. 12.46 is driven by two separate but equal signals, and When and are high, supplies the load current in the direction opposite to that shown5 and the output voltage can swing to within 0.1 V or so of ground. In the mean-time, is inactive. Nevertheless, in order to minimize crossover distortion, is 5For this to happen, either RL is returned to the positive supply (rather than ground) or RL is capacitively coupled to the amplifier output.
(c) With the CFB circuit in place, the feedback will adjust by so that the currents in and will change by a increment equal to , thus restoring current equality. Since a change results in then Correspondingly Thus, to restore the current equality, the change required in and is only 6.75 mV.
VB VB Δ Q7 Q8 I Δ VB Δ IC7 IC8 VB Δ re7 R7 + -------------------= Δ = Δ I VB Δ re7 R7 + -------------------= Δ VB I re7 R7 + ( ) Δ = Δ 0.3 μA 25 mV 10 μA ----------------20 kΩ + ⎝ ⎠ ⎛ ⎞ = 0.3 22.5 6.75 mV = × = VCM VB 6.75 mV = Δ = Δ VB VCM v BP v BN iP VCC QP QN vO iL iN RL Figure 12.46 In order to provide vO that can swing to within 0.1 V of VCC and ground, a near rail-to-rail operation, the output stage utilizes common-emitter transistors. Note that the driving signals VBP and VBN are separate but identical.
QP QN iL vO RL.
iL 0, = iP iN IQ, = = IQ vBP vBN.
vBP vBN QN vO QP QP 1046 Chapter 12 Operational-Amplifier Circuits prevented from turning off and is forced (as will be shown shortly) to conduct a minimum current of about .
The opposite happens when and are low: supplies the load current in the direction indicated, and can go up as high as . In the meantime, is inac-tive but is prevented from turning off and forced to conduct a minimum current of about .
From the description above, we see that can swing to within 0.1 V of each of the sup-ply rails. This near rail-to-rail operation is the major advantage of this CE output stage. Its disadvantage is the relatively high output resistance. However, given that the op amp will almost always be used with a negative-feedback loop, the closed-loop output resistance can still be very low.
A Buffer/Driver Stage The output transistors can be called on to supply currents in the 10 mA to 15 mA range. When this happens, the base currents of and can be substan-tial (recall that and ). Such large currents cannot usually be supplied direct-ly by the amplifier stage preceding the output stage. Rather a buffer/driver stage is usually needed, as shown in Fig. 12.47. Here an emitter follower is used to drive However, because of the low a double buffer consisting of complementary emitter followers and is used to drive The driver stage is fed by two separate but identical signals and that come from the preceding amplifier stage (which is usually the second stage) in the op amp circuit.6 6An interesting approach for generating two identical outputs in the second stage is utilized in the NE5234 (see Gray et al., 2009).
IQ 2 ⁄ vBP vBN QP iL vO VCC 0.1 V – QN IQ 2 ⁄ vO QP QN βP 10 βN 40 vIP VCC Q1 Q2 v IN Q3 QP QN iP iN Identical signals from the preceding stage Buffer/driver stage Output transistors iL vo Figure 12.47 The output stage which is operated as class AB needs emitter follower buffers/drives to reduce the loading on the preceding stage and to provide the current gain necessary to drive QP and QN.
Q3 QN.
βP, Q1 Q2 QP.
vIP vIN 12.7 Modern Techniques for the Design of BJT Op Amps 1047 Establishing IQ and Maintaining a Minimum Current in the Inactive Transistor We next consider the circuit for establishing the quiescent current in and and for maintaining a minimum current of in the inactive output transistor.
Figure 12.48 shows a fuller version of the output stage. In addition to the output transistors and the buffer/driver stage, which we have already discussed, the circuit includes two circuit blocks whose operation we shall now explain.
The first is the circuit composed of the differential pair and associated transistors and , and resistors and . This circuit measures the currents in the output transis-tors, and , and arranges for the current I to divide between and according to the ratio , and provides a related output voltage Specifically, it can be shown [Prob-lem 12.73] that (12.132) (12.133) (12.134) where and are the saturation currents of and , respectively. Observe that for , and . Thus turns off and conducts all of I. The emitter volt-age becomes Thus, (12.135) This equation simply states that which could have been directly obtained from the circuit diagram in Fig. 12.48. The important point to note, however, is that since is a constant, is determined by the current in the inactive transistor, In the other extreme case of , , ; thus turns off and conducts all of I.
In this case we can use Eq. (12.134) to show that (12.136) 12.30 (a) For the circuit in Fig. 12.47, find the current gain from each of the and terminals to the output in terms of and .
(b) For mA, how much signal current is needed at the and inputs?
Ans. (a) , ; (b) 2.5 μA, 6.25 μA vIP vIN βP βN iL 10 ± = vIP vIN βNβP 2 βN 2 EXERCISE IQ QN QP IQ 2 ⁄ QP QN – Q6 Q7 – Q4 Q5 R4 R5 iP iN Q6 Q7 iN iP ⁄ vE.
iC6 I iN iP iN + ---------------= iC7 I iP iP iN + ---------------= vE VT ln iN iP iN iP + ---------------I ISN IS7 ----------------= ISN IS7 QN Q7 iP iN iC6 0 iC7 I Q6 Q7 vE vE VT ln iN ISN --------⎝ ⎠ ⎛ ⎞+ VT ln I IS7 --------⎝ ⎠ ⎛ ⎞ vE V = T ln iN ISN --------⎝ ⎠ ⎛ ⎞+ VEB7 vE vBEN VEB7, + = VEB7 vE iN QN.
iN iP iC6 I iC7 0 Q7 Q6 vE V = T ln iP ISN --------⎝ ⎠ ⎛ ⎞+VEB6 1048 Chapter 12 Operational-Amplifier Circuits Thus, here too, since is a constant, is determined by the current in the inactive tran-sistor, .
The second circuit block is a differential amplifier composed of with their emitter-degeneration resistors , . The voltage generated by the measuring circuit is fed to one input of the differential amplifier, and the other input is fed with a reference voltage gen-erated by passing a reference current through the series connection of diode-connected transistors and . This differential amplifier takes part in a negative- feedback loop that uses the value of to control the currents and through the nodes and . The objective of the feedback control is to set the current in the inactive output transistor to a mini-mum value. To see how the feedback operates, consider the case when , and thus is the inactive transistor. In this case, turns off, conducts all of I, and is given by Eq.
(12.135). Now, if for some reason falls below its minimum intended value, decreases, Q1 Q2 Q3 Q5 QP QN R9 R5 R8 iC6 iC4 iC7 Q4 R4 iP iN iL IREF vIN I vE vIP VREF Q8 Q10 Q11 Q9 Q7 Q6 OUT Feedback control of iN and iP Measuring the relative values of iN and iP Buffers / Drivers Output transistors Figure 12.48 A more complete version of the output stage showing the circuits that establish the quies-cent current in QP and QN. As well, this circuit forces a minimum current of (IQ/2) to follow in the inactive output transistor, thus preventing the transistor from turning off and minimizing crossover distortion.
VEB6 vE QP Q8 Q9 – R8 R9 vE VREF IREF Q10 Q11 vE iP iN vIP vIN iP iN QN Q6 Q7 vE iN vE 12.7 Modern Techniques for the Design of BJT Op Amps 1049 causing to decrease. This in turn will cause the node to rise and the voltage at the base of will eventually rise, thus increasing to its intended value.
Analytically, we can obtain a relationship between and as follows. Assume that the loop gain of the feedback loop that is anchored by the differential amplifier is high enough to force the two input terminals to the same voltage, that is, Substituting for from Eq. (12.134) results in (12.137) Observe that the quantity on the right-hand side is a constant. In the quiescent case, , Eq. (12.137) yields (12.138) Thus, the constant on the right-hand side of Eq. (12.137) is , and we can rewrite (12.137) as (12.139) Equation (12.139) clearly shows that for , , and that for , Thus the circuit not only establishes the quiescent current (Eq. 12.138) but also sets the minimum current in the inactive output transistor at iC9 vIN QN iN iN iP Q8 Q9 – vE VREF VT ln IREF IS10 ---------VT ln IREF IS11 ---------+ = = vE iN iP iN iP + ---------------IREF 2 I ---------⎝ ⎠ ⎛ ⎞ISN IS10 --------⎝ ⎠ ⎛ ⎞ IS7 IS11 --------⎝ ⎠ ⎛ ⎞ = iN iP IQ = = IQ 2 IREF 2 I ---------⎝ ⎠ ⎛ ⎞ISN IS10 --------⎝ ⎠ ⎛ ⎞ IS7 IS11 --------⎝ ⎠ ⎛ ⎞ = IQ 2 ⁄ iN iP iN iP + ---------------1 2 ---IQ = iN iP iP 1 2 ---IQ iP iN iN 1 2 ---IQ.
IQ 1 2 ---IQ.
D12.31 For the circuit in Fig. 12.48, determine the value that should have so that and have a quiescent current . Assume that the transistor areas are scaled so that and . Let I = 10 μA. Also, if in the direction out of the amplifier is 10 mA, find and Ans. IREF QN QP IQ 0.4 mA = ISN IS10 ⁄ 10 = IS7 IS11 ⁄ 2 = iL iP iN.
IREF 10 μA; = iP 10.2 mA, iN 0.2 mA EXERCISE 1050 Chapter 12 Operational-Amplifier Circuits Summary Most CMOS op amps are designed to operate as part of a VLSI circuit and thus are required to drive only small capacitive loads. Therefore, most do not have a low-out-put-resistance stage.
There are basically two approaches to the design of CMOS op amps: a two-stage configuration and a single-stage topology utilizing the folded-cascode circuit.
In the two-stage CMOS op amp, approximately equal gains are realized in the two stages.
The threshold mismatch ΔVt together with the low trans-conductance of the input stage result in a larger input offset voltage for CMOS op amps than for bipolar units.
Miller compensation is employed in the two-stage CMOS op amp, but a series resistor is required to place the transmission zero at either s = ∞ or on the negative real axis.
CMOS op amps have higher slew rates than their bipo-lar counterparts with comparable f t values.
Use of the cascode configuration increases the gain of a CMOS amplifier stage by about two orders of magni-tude, thus making possible a single-stage op amp.
The dominant pole of the folded-cascode op amp is de-termined by the total capacitance at the output node, CL.
Increasing CL improves the phase margin at the expense of reducing the bandwidth.
By using two complementary input differential pairs in parallel, the input common-mode range can be extended to equal the entire power-supply voltage, providing so-called rail-to-rail operation at the input.
The output voltage swing of the folded-cascode op amp can be extended by utilizing a wide-swing current mir-ror in place of the cascode mirror.
The internal circuit of the 741 op amp embodies many of the design techniques employed in bipolar analog in-tegrated circuits.
The 741 circuit consists of an input differential stage, a high-gain single-ended second stage, and a class AB output stage. Though 40 years old, this structure is typ-ical of most BJT op amps and is known as the two-stage topology (not counting the output stage). It is also the same structure used in the two-stage CMOS op amp of Section 12.1.
To obtain low input offset voltage and current, and high CMRR, the 741 input stage is designed to be per-fectly balanced. The CMRR is increased by common-mode feedback, which also stabilizes the dc operating point.
To obtain high input resistance and low input bias current, the input stage of the 741 is operated at a very low current level.
In the 741, output short-circuit protection is accom-plished by turning on a transistor that takes away most of the base current drive of the output transistor.
The use of Miller frequency compensation in the 741 circuit enables locating the dominant pole at a very low frequency, while utilizing a relatively small compensat-ing capacitance.
Two-stage op amps can be modeled as a transconduc-tance amplifier feeding an ideal integrator with CC as the integrating capacitor.
The slew rate of a two-stage op amp is determined by the first-stage bias current and the frequency-compensation capacitor.
While the 741 and its generation of op amps nominally operate from -V power supplies, modern BJT op amps typically utilize a single ground-referenced supply of only 2 V to 3 V.
Operation from a single low-voltage supply gives rise to a number of new important specifications including a common-mode input range that extends beyond the sup-ply rails (i.e., more than rail-to-rail operation) and a near rail-to-rail output voltage swing.
The rail-to-rail input common-mode range is achieved by using resistive loads (instead of current-mirror loads) for the input differential pair as well as utilizing two comple-mentary differential amplifiers in parallel.
To increase the gain of the input stage above that achieved with resistive loads, the folded-cascode config-uration is utilized.
To regulate the dc bias voltages at the outputs of the dif-ferential folded-cascode stage so as to maintain active-mode operation at all times, common-mode feedback is employed.
The output stage of a low-voltage op amp utilizes a complementary pair of common-emitter transistors.
This allows to swing to within 0.1 V or so from each of the supply rails. The disadvantage is a high open-loop output resistance. This, however, is sub-stantially reduced when negative feedback is applied around the op amp.
Modern output stages operate in the class AB mode and utilize interesting feedback techniques to set the quies-cent current as well as to ensure that the inactive output transistor does not turn off, a precaution that avoids in-creases in crossover distortion.
15 ± vO PROBLEMS Computer Simulation Problems Problems identified by this icon are intended to dem-onstrate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as allowable signal swing and amplifier nonlinear distortion.
Instructions to assist in setting up PSpice and Multism simu-lations for all the indicated problems can be found in the corresponding files on the CD. Note that if a particular parameter value is not specified in the problem statement, you are to make a reasonable assumption.
difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 12.1: The Two-Stage CMOS Op Amp 12.1 A particular design of the two-stage CMOS opera-tional amplifier of Fig. 12.1 utilizes ±1-V power supplies.
All transistors are operated at overdrive voltages of 0.15-V magnitude. The process technology provides devices with = 0.45 V. Find the input common-mode range and the range allowed for vO.
12.2 The CMOS op amp of Fig. 12.1 is fabricated in a pro-cess for which = 25 and = 20 . Find A1, A2, and Av if all devices are 0.5-μm long and are operated at equal overdrive voltages of 0.2-V magnitude. Also, determine the op-amp output resistance obtained when the second stage is biased at 0.4 mA. What do you expect the output resistance of a unity-gain voltage amplifier to be, using this op amp?
D 12.3 The CMOS op amp of Fig. 12.1 is fabricated in a process for which for all devices is 24 . If all transistors have L = 0.5 μm and are operated at equal over-drive voltages, find the magnitude of the overdrive voltage required to obtain a dc open-loop gain of 6400 .
12.4 This problem is identical to Problem 8.107.
Consider the circuit in Fig. 12.1 with the device geome-tries shown at the bottom of this page. Let IREF = 225 μA, for all devices = 0.75 V, μnCox = 180 μpCox = 60 for all devices = 9 V, VDD = VSS = 1.5 V.
Determine the width of Q6, W, that will ensure that the op amp will not have a systematic offset voltage. Then, for all devices, evaluate ID, , , gm, and ro. Provide your results in a table. Also find A1, A2, the dc open-loop voltage gain, the input common-mode range, and the out-put voltage range. Neglect the effect of V A on the bias currents.
D 12.5 Design the two-stage CMOS op amp in Fig. 12.1 to provide a CMRR of about 80 dB. If all the transistors are operated at equal overdrive voltages of 0.15 V and have equal channel lengths, find the minimum required channel length. For this technology, V/μm. D 12.6 A particular implementation of the CMOS amplifier of Figs. 12.1 and 12.2 provides Gm1 = 0.3 mA/V, Gm2 = 0.6 mA/V, ro2 = ro4 = 222 kΩ, ro6 = ro7 = 111 kΩ, and C2 = 1 pF.
(a) Find the frequency of the second pole, fP2.
(b) Find the value of the resistance R which when placed in series with CC causes the transmission zero to be located at s = ∞.
(c) With R in place, as in (b), find the value of CC that results in the highest possible value of ft while providing a phase margin of 80°. What value of ft is realized? What is the corresponding frequency of the dominant pole?
(d) To what value should CC be changed to double the value of ft? At the new value of ft , what is the phase shift intro-duced by the second pole? To reduce this excess phase shift to 10° and thus obtain an 80° phase margin, as before, what value should R be changed to?
D 12.7 A two-stage CMOS op amp similar to that in Fig.
12.1 is found to have a capacitance between the output node and ground of 0.5 pF. If it is desired to have a unity-gain bandwidth ft of 150 MHz with a phase margin of 75° what must gm6 be set to? Assume that a resistance R is con-nected in series with the frequency-compensation capaci-tor CC and adjusted to place the transmission zero at infinity. What value should R have? If the first stage is operated at = 0.15 V, what is the value of slew rate obtained? If the first-stage bias current I = 100 μA, what is the required value of CC?
D 12.8 A CMOS op amp with the topology shown in Fig.
12.1 is designed to provide mA/V and mA.
(a) Find the value of that results in MHz.
(b) What is the maximum value that can have while achieving a phase margin?
D 12.9 A CMOS op amp with the topology shown in Fig.
12.1 but with a resistance R included in series with CC is designed to provide Gm1 = 1 mA/V and Gm2 = 2 mA/V.
(a) Find the value of CC that results in ft = 100 MHz.
(b) For R = 500 Ω, what is the maximum allowed value of C2 for which a phase margin of at least 60° is obtained?
V tn V tp = VAn ′ V/μm V ′ Ap V/μm VA ′ V/μm V/V Vt μA/V2, μA/V2, V A VOV VGS VA ′ 20 = VOV Gm1 1 = Gm2 5 = CC ft 100 = C2 70° Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/ L (μm/μm) 30/ 0.5 30/ 0.5 10/ 0.5 10/ 0.5 60/ 0.5 W/ 0.5 60/ 0.5 60/ 0.5 CHAPTER 12 PR OBLE MS 1052 Chapter 12 Operational-Amplifier Circuits 12.10 A two-stage CMOS op amp resembling that in Fig.
12.1 is found to have a slew rate of 60 and a unity-gain bandwidth ft of 50 MHz.
(a) Estimate the value of the overdrive voltage at which the input-stage transistors are operating.
(b) If the first-stage bias current I = 100 μA, what value of CC must be used?
(c) For a process for which μpCox = 50 μA/V2, what ratio applies for Q1 and Q2?
D 12.11 Sketch the circuit of a two-stage CMOS amplifier having the structure of Fig. 12.1 but utilizing NMOS transis-tors in the input stage (i.e., Q1 and Q2).
D 12.12 (a) Show that the of a CMOS two-stage op amp for which all transistors have the same channel length and are operated at equal is given by (b) For , what is the minimum channel length required to obtain a of 80 dB? For the technology available, V/μm. Section 12.2: The Folded-Cascode Op Amp D 12.13 If the circuit of Fig. 12.8 utilizes ±1.65-V power supplies and the power dissipation is to be limited to 1 mW, find the values of IB and I. To avoid turning off the current mirror during slewing, select IB to be 20% larger than I.
D 12.14 For the folded-cascode op amp in Fig. 12.9 utiliz-ing power supplies of ±1 V, find the values of VBIAS1, VBIAS2, and VBIAS3 to maximize the allowable range of VICM and vO.
Assume that all transistors are operated at equal overdrive voltages of 0.15 V. Assume for all devices is 0.45 V.
Specify the maximum range of VICM and of vO.
D 12.15 For the folded-cascode op-amp circuit of Figs.
12.8 and 12.9 with bias currents I = 96 μA and IB = 120 μA, and with all transistors operated at overdrive voltages of 0.2 V, find the ratios for all devices. Assume that the technology available is characterized by = 400 and = 100 .
12.16 Consider a design of the cascode op amp of Fig. 12.9 for which I = 96 μA and IB = 120 μA. Assume that all transis-tors are operated at = 0.2 V and that for all devices, = 12 V. Find Gm, Ro, and Av . Also, if the op amp is con-nected in the feedback configuration shown in Fig. P12.16, find the voltage gain and output resistance of the closed-loop amplifier.
D 12.17 Consider the folded-cascode op amp of Fig.
12.8 when loaded with a 10-pF capacitance. What should the bias current I be to obtain a slew rate of at least 10 ? If the input-stage transistors are operated at over-drive voltages of 0.2 V, what is the unity-gain bandwidth realized? If the two nondominant poles have the same fre-quency of 25 MHz, what is the phase margin obtained? If it is required to have a phase margin of 75°, what must ft be reduced to? By what amount should CL be increased?
What is the new value of SR?
D 12.18 Design the folded-cascode circuit of Fig. 12.9 to provide voltage gain of 80 dB and a unity-gain frequency of 10 MHz when CL = 10 pF. Design for IB = I, and operate all devices at the same . Utilize transistors with 1-μm channel length for which is specified to be 20 V. Find the required overdrive voltages and bias currents. What slew rate is achieved? Also, for = 2.5 = 200 specify the required width of each of the 11 transistors used.
D 12.19 Sketch the circuit that is complementary to that in Fig. 12.9, that is, one that uses an input p-channel dif-ferential pair.
12.20 For the circuit in Fig. 12.11, assume that all transis-tors are operating at equal overdrive voltages of 0.2-V mag-nitude and have = 0.5 V and that VDD = VSS = 1.65 V.
Find (a) the range over which the NMOS input stage oper-ates, (b) the range over which the PMOS input stage oper-ates, (c) the range over which both operate (the overlap range), and (d) the input common-mode range.
12.21 A particular design of the wide-swing current mirror of Fig. 12.12(b) utilizes devices having = 25, = 200 μA/V2, and Vt = 0.5 V. For IREF = 100 μA, what value of VBIAS is needed? Also give the voltages that you expect to appear at all nodes and specify the minimum voltage allowable at the output terminal. If VA is specified to be 10 V, what is the output resistance of the mirror?
D 12.22 For the folded-cascode circuit of Fig. 12.8, let the total capacitance to ground at each of the source nodes of Q3 and Q4 be denoted CP. Assuming that the incremental resistance between the drain of Q3 and ground is small, Show that the pole that arises at the interface between the V/μs W L ⁄ PSRR– VOV PSRR– 2 VA VOV ---------2 = VOV 0.2 V = PSRR– VA ′ 20 = Vt W L ⁄ kn ′ μA/V 2 kp ′ μA/V2 VOV VA C 9C Vi Vo Rof Figure P12.16 V/μs VOV VA kn ′ kp ′ μA/V 2, Vt W L ⁄ k′ n Problems 1053 CHAPTER 12 PR OBLEM S first and second stages has a frequency .
Now, if this is the only nondominant pole, what is the largest value that CP can be (expressed as a fraction of CL) while a phase margin of 75° is achieved? Assume that all transistors are operated at the same bias current and over-drive voltage.
Section 12.3: The 741 Op-Amp Circuit 12.23 In the 741 op-amp circuit of Fig. 12.13, Q1, Q2, Q5, and Q6 are biased at collector currents of 9.5 μA; Q16 is biased at a collector current of 16.2 μA; and Q17 is biased at a collector current of 550 μA. All these devices are of the “standard npn” type, having IS = 10–14 A, β = 200, and VA = 125 V. For each of these transistors, find VBE, gm, re, rπ, and ro. Provide your results in table form. (Note that these parameter values are utilized in the text in the analysis of the 741 circuit.) D 12.24 For the (mirror) bias circuit shown in Fig.
E12.11 and the result verified in the associated exercise, find I1 for the case in which IS3 = 3 × 10–14 A, IS4 = 6 × 10–14 A, and IS1 = IS2 = 10–14 A and for which a bias current I3 = 154 μA is required.
12.25 Transistor Q13 in the circuit of Fig. 12.13 consists, in effect, of two transistors whose emitter–base junctions are connected in parallel and for which ISA = 0.25 × 10–14 A, ISB = 0.75 × 10–14 A, β = 50, and VA = 50 V. For operation at a total emitter current of 0.73 mA, find values for the param-eters VEB, gm, re, rπ, and ro for the A and B devices.
12.26 In the circuit of Fig. 12.13, Q1 and Q2 exhibit emitter–base breakdown at 7 V, while for Q3 and Q4 such a breakdown occurs at about 50 V. What differential input voltage would result in the breakdown of the input-stage transistors?
D 12.27 Figure P12.27 shows the CMOS version of the circuit in Fig. E12.11. Find the relationship between I3 and I1 in terms of k1, k2, k3, and k4 of the four transistors, assum-ing the threshold voltages of all devices to be equal in magnitude. Note that k denotes . In the event that k1 = k2 and k3 = k4 = 16k1, find the required value of I1 to yield a bias current in Q3 and Q4 of 1.6 mA.
Section 12.4: DC Analysis of the 741 D 12.28 For the 741 circuit, estimate the input reference current IREF in the event that ±5-V supplies are used. Find a more precise value assuming that for the two BJTs involved, IS = 10–14 A. What value of R5 would be necessary to rees-tablish the same bias current for ±5-V supplies as exists for ±15 V in the original design?
D 12.29 Design the Widlar current source of Fig. 12.14 to generate a current IC10 = 10 μA given that IREF = 0.2 mA. If for the transistors, IS = 10–14 A, find VBE11 and VBE10. Assume β to be high.
12.30 Consider the dc analysis of the 741 input stage shown in Fig. 12.15. For what value of βP do the currents in Q1 and Q2 differ from the ideal value of IC10/2 by 10%?
D 12.31 Consider the dc analysis of the 741 input stage shown in Fig. 12.15 for the situation in which IS9 = 2IS8. For IC10 = 19 μA and assuming βP to be high, what does I become?
Redesign the Widlar source to reestablish IC1 = IC2 = 9.5 μA.
12.32 For the mirror circuit shown in Fig. 12.16 with the bias and component values given in the text for the 741 cir-cuit, what does the current in Q6 become if R2 is shorted?
D 12.33 It is required to redesign the circuit of Fig. 12.16 by selecting a new value for R3 so that when the base cur-rents are not neglected, the collector currents of Q5, Q6, and Q7 all become equal, assuming that the input current IC3 = 9.4 μA. Find the new value of R3 and the three currents.
Recall that βN = 200.
12.34 Consider the input circuit of the 741 op amp of Fig.
12.13 when the emitter current of Q8 is about 19 μA. If β of Q1 is 150 and that of Q2 is 200, find the input bias current IB and the input offset current IOS of the op amp.
12.35 For a particular application, consideration is being given to selecting 741 ICs for input bias and offset currents limited to 50 nA and 4 nA, respectively. Assuming other fP gm3 2πCP ⁄ μCoxW/L Figure P12.27 CHAPTER 12 PR OBLE MS 1054 Chapter 12 Operational-Amplifier Circuits aspects of the selected units to be normal, what minimum βN and what βN variation are implied?
12.36 A manufacturing problem in a 741 op amp causes the current transfer ratio of the mirror circuit that loads the input stage to become 0.8 A/A. For input devices (Q1–Q4) appropriately matched and with high β, and normally biased at 9.5 μA, what input offset voltage results?
D 12.37 Consider the design of the second stage of the 741. What value of R9 would be needed to reduce IC16 to 9.5 μA?
D 12.38 Reconsider the 741 output stage as shown in Fig.
12.17, in which R10 is adjusted to make IC19 = IC18. What is the new value of R10? What values of IC14 and IC20 result?
D 12.39 An alternative approach to providing the voltage drop needed to bias the output transistors is the VBE– multiplier circuit shown in Fig. P12.39. Design the circuit to provide a terminal voltage of 1.118 V (the same as in the 741 circuit). Base your design on half the current flowing through R1, and assume that IS = 10–14 A and β = 200. What is the incremental resistance between the two terminals of the VBE– multiplier circuit?
12.40 For the circuit of Fig. 12.13, what is the total cur-rent required from the power supplies when the op amp is operated in the linear mode, but with no load? Hence, esti-mate the quiescent power dissipation in the circuit. (Hint: Use the data given in Table 12.1.) Section 12.5: Small-Signal Analysis of the 741 12.41 Consider the 741 input stage as modeled in Fig.
12.18, with two additional npn diode-connected transistors, Q1a and Q2a, connected between the present npn and pnp devices, one per side. Convince yourself that each of the additional devices will be biased at the same current as Q1 to Q4—that is, 9.5 μA. What does Rid become? What does Gm1 become? What is the value of Ro4 now? What is the output resistance of the first stage, Ro1? What is the new open-circuit voltage gain, Gm1Ro1? Compare these values with the original ones.
D 12.42 What relatively simple change can be made to the mirror load of stage 1 to increase its output resistance, say by a factor of 2?
12.43 Repeat Exercise 12.15 with R1 = R2 replaced by 2-kΩ resistors.
12.44 In Example 12.3 we investigated the effect of a mismatch between R1 and R2 on the input offset voltage of the op amp. Conversely, R1 and R2 can be deliberately mis-matched (using the circuit shown in Fig. P12.44, for example) to compensate for the op-amp input offset voltage.
(a) Show that an input offset voltage VOS can be compen-sated for (i.e., reduced to zero) by creating a relative mis-match ΔR/R between R1 and R2, where re is the emitter resistance of each of Q1 to Q6, and R is the nominal value of R1 and R2. (Hint: Use Eq. 12.87) (b) Find ΔR/R to trim a 5-mV offset to zero.
(c) What is the maximum offset voltage that can be trimmed this way (corresponding to R2 completely shorted)?
12.45 Through a processing imperfection, the β of Q4 in Fig. 12.13 is reduced to 20, while the β of Q3 remains at its regular value of 50. Find the input offset voltage that this mismatch introduces. (Hint: Follow the general procedure outlined in Example 12.3.) I 180 μA 180 μA Figure P12.39 ΔR R -------V OS 2V T ---------1 re R ⁄ + 1 V OS 2V T ⁄ – -------------------------------= Figure P12.44 Problems 1055 CHAPTER 12 PR OBLEM S 12.46 Consider the circuit of Fig. 12.13 modified to include resistors R in series with the emitters of each of Q8 and Q9. What does the resistance looking into the collector of Q9, Ro9, become? For what value of R does it equal Ro10? For this case, what does Ro looking to the left of node Y become?
12.47 What is the effect on the differential gain of the 741 op amp of short-circuiting one, or the other, or both, of R1 and R2 in Fig. 12.13? (Refer to Fig. 12.19.) For simplic-ity, assume β = ∞.
12.48 It is required to show that the loop gain of the com-mon-mode feedback loop shown in Fig. 12.23 is approxi-mately equal to . To determine the loop gain, connect both input terminals to ground. Break the loop at the input to the current mirror, connecting the collec-tors to signal ground. (This is because the original resistance between the collectors and ground is , which is small.) Apply a test current to and determine the returned current in the common collectors’ connection to ground, then find the loop gain as . Assume that of Q1 to Q4 is much lower than and that , .
12.49 An alternative approach to that presented in Exam-ple 12.4 for determining the CMRR of the 741 input stage is investigated in this problem. Rather than performing the analysis on the closed loop shown in Fig. 12.23, we observe that the negative feedback increases the resistance at node Y by the amount of negative feedback. Thus, we can break the loop at Y and connect a resistance between the common base connection of and ground. We can then determine the current i and .
Using the fact that the loop gain is approximately equal to (Problem 12.48) show that this approach yields an iden-tical result to that found in Example 12.4.
12.50 Consider a variation on the design of the 741 sec-ond stage in which R8 = 50 Ω. What Ri2 and Gm2 correspond?
12.51 In the analysis of the 741 second stage, note that Ro2 is affected most strongly by the low value of Ro13B. Consider the effect of placing appropriate resistors in the emitters of Q12, Q13A, and Q13B on this value. What resistor in the emitter of Q13B would be required to make Ro13B equal to Ro17 and thus Ro2 half as great? What resistors in each of the other emitters would be required?
12.52 For a 741 employing ±5-V supplies, and , find the output voltage limits that apply.
D 12.53 Consider an alternative to the present 741 output stage in which Q23 is not used, that is, in which its base and emitter are joined. Reevaluate the reflection of RL = 2 kΩ to the collector of Q17. What does A2 become?
12.54 Consider the positive current-limiting circuit involving Q13A, Q15, and R6. Find the current in R6 at which the collector current of Q15 equals the current available from Q13A (180 μA) minus the base current of Q14. (You need to perform a couple of iterations.) D 12.55 Consider the 741 sinking-current limit involv-ing R7, Q21, Q24, R11, and Q22. For what current through R7 is the current in Q22 equal to the maximum current avail-able from the input stage (i.e., the current in Q8)? What simple change would you make to reduce this current limit to 10 mA?
Section 12.6: Gain, Frequency Response, and Slew Rate of the 741 12.56 Using the data provided in Eq. (12.112) (alone) for the overall gain of the 741 with a 2-kΩ load, and realizing the significance of the factor 0.97 in relation to the load, cal-culate the open-circuit voltage gain, the output resistance, and the gain with a load of 200 Ω. 12.57 A 741 op amp has a phase margin of 75°. If the excess phase shift is due to a second single pole, what is the frequency of this pole?
12.58 A 741 op amp has a phase margin of 75°. If the op amp has nearly coincident second and third poles, what is their frequency?
D 12.59 For a modified 741 whose second pole is at 5 MHz, what dominant-pole frequency is required for 80° phase margin with a closed-loop gain of 100? Assuming CC continues to control the dominant pole, what value of CC would be required?
12.60 An internally compensated op amp having an ft of 10 MHz and dc gain of 106 utilizes Miller compensation around an inverting amplifier stage with a gain of –1000. If space exists for at most a 50-pF capacitor, what resistance level must be reached at the input of the Miller amplifier for compensation to be possible?
12.61 Consider the integrator op-amp model shown in Fig. 12.33. For Gm1 = 5 mA/V, CC = 100 pF, and a resis-tance of Ω shunting CC , sketch and label a Bode plot for the magnitude of the open-loop gain. If Gm1 is related to the first-stage bias current as Gm1 = I/2VT, find the slew rate of this op amp.
12.62 For an amplifier with a slew rate of 10 V/μs, what is the full-power bandwidth for outputs of ±10 V? What unity-gain bandwidth, ωt, would you expect if the topology was similar to that of the 741?
βP Q8 Q9 – Q1 Q2 – re8 It Q8 Ir Ir It ⁄ – rπ Ro βN βP 1 Rf 1 Aβ + ( )Ro = Q3 Q4 – Gmcm βP V BE 0.6 V = V CEsat 0.2 V = 2 107 × CHAPTER 12 PR OBLE MS 1056 Chapter 12 Operational-Amplifier Circuits D 12.63 Figure P12.63 shows a circuit suitable for op-amp applications. For all transistors β = 100, VBE = 0.7 V, and ro = ∞.
(a) For inputs grounded and output held at 0 V (by negative feedback) find the collector currents of all transistors.
Neglect base currents. (b) Calculate the input resistance.
(c) Calculate the gain of the amplifier with a load of 5 kΩ.
(d) With load as in (c) calculate the value of the capacitor C required for a 3-dB frequency of 100 Hz.
Section 12.7: Modern Techniques for the Design of BJT Op Amps Unless otherwise specified, for the problems in this section assume , , V, V, V, V.
D 12.64 Design the circuit in Fig. 12.38 to generate a current I = 6 μA. Utilize transistors and having areas in a ratio of 1:4. Assume that and are matched and design for a 0.2-V drop across each of and Specify the values of and Ignore base currents.
D 12.65 Consider the circuit of Fig. 12.38 for the case designed in Exercise 12.28, namely, I = 10 μA, , , . Aug-ment the circuit with npn transistors and with emit-ters connected to ground and bases connected to , to generate constant currents of 10 μA and 40 μA, respectively.
What should the emitter areas of and be relative to that of ? What value of a resistance will, when con-nected in the emitter of , reduce the current generated by to 10 μA? Assuming that the line has a low incre-mental resistance to ground, find the output resistance of current source and of current source with con-nected. Ignore base currents.
D 12.66 (a) Find the input common-mode range of the circuit in Fig. 12.40(a). Let V and 2.3 V.
(b) Give the complementary version of the circuit in Fig.
12.40(a), that is, the one in which the differential pair is npn.
For the same conditions as in (a), what is the input common-mode range?
12.67 For the circuit in Fig. 12.40(b), let V, V, I = 20 μA, and . Find the input common-mode range and the differential voltage gain . Neglect base currents.
12.68 For the circuit in Fig. 12.41, let V, V, and μA. Find that results in a differential gain of 10 V/V. What is the input common-mode range and the input differential resistance? Ignore base currents except when calculating .
12.69 It is required to find the input resistance and the voltage gain of the input stage shown in Fig. 12.42. Let V so that the pair is off. Assume that Figure P12.63 βN 40 = βP 10 = VAn 30 = VAp 20 = VBE 0.7 = VCEsat 0.1 = Q1 Q2 Q3 Q4 R3 R4.
R2, R3, R4.
IS2 IS1 ⁄ 2 = R2 1.73 kΩ = R3 R4 20 kΩ = = Q5 Q6 VBIAS1 Q5 Q6 Q1 R6 Q6 Q6 VBIAS1 Q5 Q6 R6 VCC 3 = VBIAS = VCC 3 = VBIAS 2.3 = RC 20 kΩ = vo vid ⁄ VCC 3 = VBIAS 0.7 = IC6 10 = RC Rid VICM 0.8 Q3 Q4 – Problems 1057 CHAPTER 12 PR OBLEM S supplies 6 μA, that each of to is biased at 6 μA, and that all four cascode transistors are operating in the active mode. The input resistance of the second stage of the op amp is 1.3 M . The emitter degeneration resistances are k , and k . [Hint: Refer to Fig. 12.43.] D 12.70 Consider the equivalent half-circuit shown in Fig. 12.43. Assume that in the original circuit, is biased at a current I, and are biased at 2I, the dc voltage drop across is 0.2 V, and the dc voltage drop across is 0.3 V. Find the open-circuit voltage gain (i.e., the voltage gain for ). Also find the output resistance in terms of I. Now with connected, find the voltage gain in terms of . For , find I that will result in the voltage gains of 160 V/V and 320 V/V.
12.71 (a) For the circuit in Fig. 12.44, show that the loop gain of the common-mode feedback loop is Recall that the CMF circuit realizes the transfer characteris-tic . Ignore the loading effect of the CMF circuit on the collectors of the cascode transistors. (b) For the values in Example 12.6, calculate the loop gain .
(c) In Example 12.6, we found that with the CMF absent, a current mismatch μA gives rise to V.
Now, with the CMF present, use the value of loop gain found in (b) to calculate the expected and compare to the value found by a different approach in Example 12.6. [Hint: Recall that negative feedback reduces change by a factor equal to .] 12.72 The output stage in Fig. 12.46 operates at a quiescent current of 0.4 mA. The maximum current that the stage can provide in either direction is 10 mA. Also, the output stage is equipped with a feedback circuit that maintains a minimum current of in the inactive output transistor.
(a) What is the allowable range of (b) For , what is the output resistance of the op amp?
(c) If the open-loop gain of the op amp is 100,000 V/V, find the closed-loop output resistance obtained when the op amp is connected in the unity-gain voltage follower configura-tion, with (d) If the op amp is sourcing a load current find and the open-loop output resistance.
(e) Repeat (d) for the case of the open-loop op amp sinking a load current of 10 mA.
12.73 It is required to derive the expressions in Eqs. (12.132) and (12.133). Toward that end, first find in terms of and hence Then find in terms of For the latter pur-pose note that measures and develops a current . This current is supplied to the series connection of and where In the expression you obtain for use the relationship to express in terms of and Now with and determined, find and 12.74 It is required to derive the expression for in Eq.
(12.134). Toward that end, note from the circuit in Fig.
12.48 that and note that conducts a current and conducts a current given by Eq.
(12.133).
D 12.75 For the output stage in Fig. 12.48, find the cur-rent that results in a quiescent current Assume that I = 10 μA, has eight times the area of , and has four times the area of .
What is the minimum current in and Q5 Q7 Q10 Ω R7 R8 22 = = Ω R9 R10 33 = = Ω Q1 Q7 Q9 R7 R9 RL ∞ = RL IRL ( ) RL 2 MΩ = Aβ Ro9 Ro7 || re7 R7 + ----------------------VB VCM 0.4 + = Aβ I 0.3 = Δ VCM 2.5 = Δ VCM Δ 1 Aβ + ( ) IQ iL IQ 2 ⁄ vO?
iL 0 = iL 0.
= iL 10 mA, = iP, iN, vB7 vBEN iN.
vB6 iP.
Q4 vEBP i4 vEBP vEB4 – ( ) R4 ⁄ = Q5 R5 R5 R4.
= vB6, ISP IS4 -------ISN IS5 -------= vB6 iP ISN.
vB6 vB7 iC6 iC7.
vE vE vEB7 vBEN + = QN iN Q7 iC7 IREF IQ 0.36 mA.
= QN Q10 Q7 Q11 QN QP?
CHAPTER 13 CMOS Digital Logic Circuits 1060 CHAPTER 14 Advanced MOS and Bipolar Logic Circuits 1142 CHAPTER 15 Memory Circuits 1202 PART III Digital Integrated Circuits here are two indisputable facts about digital systems. They have dramatically changed our lives; and the digital revolution is driven by microelectronics.
Evidence of the pervasiveness and influence of digital systems can be found by thinking of what we do in our daily lives. Digital circuits exist in almost every electrical appliance we use in our homes; in the vehicles and transportation systems we use to travel; in the telephones and, most obviously, the cell phones we use to communicate; in the medical equipment needed to care for our health; in the computers we use to do our work; and in the audio and video systems and the radio and TV sets we use to entertain ourselves. Indeed, it is very difficult to conceive of modern life without digital systems, none of which would have been possible without microelectronics.
Although the idea of a digital computing machine was conceived as early as the 1830s, early implementations were very cumbersome and expensive mechanical devices. The first serious digital computers using vacuum tubes appeared in the 1930s and 1940s. These early computers used thou-sands of tubes and were housed literally in many rooms. Their fundamental limitation was low T reliability: vacuum tubes had a finite life and needed large amounts of power. Had it not been for the invention of the transistor in 1947 ushering in the era of solid-state electron-ics, digital computers would have remained specialized machines used primarily in mili-tary and scientific applications.
By the mid 1950s, the first digital logic gates made of discrete bipolar transistors be-came commercially available. The invention of the integrated circuit in the late 1950s was also key, leading to the first digital IC in the early 1960s. Early digital ICs were made of bi-polar transistors, with the most successful logic-circuit family of this type being transistor-transistor logic (or TTL), which dominated digital circuit design, until the early 1980s.
Bipolar was replaced by NMOS, and NMOS by CMOS, again predominantly because of power dissipation and the need to pack more and more transistors on each IC chip.
Bearing out Moore’s law, which predicted in 1968 that IC chips would double the number of their transistors every two to three years (see Section 13.5), digital ICs have grown from a few transistors to 2.3 billion devices and to memory chips with 4 Gbit capacity.
Part III aims to provide a brief but nonetheless comprehensive and sufficiently de-tailed exposure to digital IC design. Our treatment is almost self-contained, requiring for the most part only a thorough understanding of the MOSFET material presented in Chap-ter 5. Thus Part III can be studied right after Chapter 5. The only exceptions to this are the last two sections in Chapter 14, which require knowledge of the BJT (Chapter 6). Also, knowledge of the MOSFET internal capacitances (Section 9.2.2) will be needed.
Chapter 13 is the cornerstone of Part III. It provides an introduction to digital circuits and then concentrates on the bread-and-butter topic of digital IC design: the CMOS in-verter and logic gates. Today, CMOS represents 98% of newly designed digital systems.
The material in Chapter 13 is the minimum needed to learn something meaningful about digital circuits; it is a must study!
Chapter 14 builds on the foundation established in Chapter 13 and introduces three important types of MOS logic circuits and a significant family of bipolar logic circuits. The chapter concludes with an interesting digital circuit technology that attempts to combine the best of bipolar and CMOS: BiCMOS. Digital circuits can be broadly divided into logic and memory circuits. The latter is the subject of Chapter 15.
1059 CHAPTER 13 CMOS Digital Logic Circuits Introduction 1061 13.1 Digital Logic Inverters 1062 13.2 The CMOS Inverter 1089 13.3 Dynamic Operation of the CMOS Inverter 1098 13.4 CMOS Logic-Gate Circuits 1110 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1122 Summary 1132 Problems 1134 1061 IN THIS CHAPTER YOU WILL LEARN 1. How the operation of the basic element in digital circuits, the logic inverter, is characterized by such parameters as noise margins, propaga-tion delay, and power dissipation, and how it is implemented by using one of three possible arrangements of voltage-controlled switches (transistors).
2. That the three most significant metrics in digital IC design are speed of operation, power dissipation, and silicon area, and that each design is in effect a trade-off among the three metrics.
3. How and why CMOS has become the dominant technology for digital IC design.
4. The structure, circuit operation, static and dynamic performance analysis, and the design of the CMOS inverter.
5. The synthesis and design optimization of CMOS logic circuits.
6. The implications of technology scaling (Moore’s law) over 40 years and continuing, and some of the current challenges in the design of deep-submicron ( < 0.25 μm) circuits.
Introduction This chapter does three things: It introduces the basic element of digital circuits, the logic inverter; it presents a relatively detailed study of the CMOS inverter and of CMOS logic-circuit design; and it provides a perspective on the astounding phenomenon of technology scal-ing (Moore’s law) and the opportunities and challenges of deep-submicron ( ) IC design.
Our study of the inverter in Section 13.1 provides the foundation for the study of digital electronics in the remainder of the chapter and in the next two chapters. Without getting into circuit implementation detail, Section 13.1 introduces all the parameters and metrics used in digital IC design. As well, it provides an overview of digital IC technologies and logic-circuit families. In this way, it provides the basis for appreciating how and why CMOS has emerged the dominant technology in digital IC design. The section concludes with a discus-sion of the various styles of digital system design: from small-scale and medium-scale inte-grated-circuit (SSI and MSI) packages assembled on printed-circuit boards to systems assembled using very-large-scale integrated (VLSI) circuits such as microprocessors, mem-ory, and custom and semicustom ICs.
L 0.25 μm < 1062 Chapter 13 CMOS Digital Logic Circuits Sections 13.2 and 13.3 provide a comprehensive and thorough study of the CMOS inverter. Section 13.4 builds on this material and presents the basic CMOS logic-gate cir-cuits as well as a general approach for the CMOS implementation of arbitrary logic func-tions. We also consider the design optimization of the resulting circuits.
The chapter concludes with a retrospective and a prospective look at Moore’s law and the technology scaling that has continued over the last 40 years and shows no signs of stopping.
This leads naturally to a discussion of the phenomena that take place in deep-submicron MOSFETs and how to modify the model we studied in Chapter 5 to take account of these phenomena. This section should serve as a bridge between this introductory course and more advanced study of digital IC design.
This chapter provides a self-contained study of CMOS logic circuits, the bread and butter of digital IC design. We will build on this foundation in our study of the more specialized topics in the next two chapters.
13.1 Digital Logic Inverters The logic inverter is the most basic element in digital circuit design; it plays a role parallel to that of the amplifier in analog circuits. In this section we provide an introduction to the logic inverter and to digital circuit design.
13.1.1 Function of the Inverter As its name implies, the logic inverter inverts the logic value of its input signal. Thus, for a logic-0 input, the output will be a logic 1, and vice versa. In terms of voltage levels, consider the inverter shown in block form in Fig. 13.1. Its implementation will ensure that when is low (close to 0 V), the output will be high (close to and vice versa. 13.1.2 The Voltage-Transfer Characteristic (VTC) To quantify the operation of the inverter, we utilize its voltage-transfer characteristic (VTC).
We have already introduced the concept of the VTC and utilized it to characterize the opera-tion of basic MOSFET amplifiers in Section 5.4.2. Figure 13.2 shows such a circuit, together with its VTC. Observe that the circuit in fact implements the inverter function: For a logic-0 input, is close to 0 V and specifically lower than the MOSFET threshold voltage Vtn, the transistor will be off, , and , which is a logic 1. For a logic-1 input, , the transistor will be conducting and operating in the triode region (at point D on the VTC), and the output voltage will be low (logic 0). Figure 13.1 A logic inverter operating from a dc supply VDD.
L 0.25 μm < ( ) vI vO VDD), vI iD 0 = vO VDD = vI VDD = vI VDD vO 13.1 Digital Logic Inverters 1063 Thus to use this amplifier as a logic inverter, we utilize its extreme regions of operation.
This is exactly the opposite to its use as a signal amplifier, where it would be biased at the middle of the transfer characteristic segment BC and the signal kept small enough to restrict operation to a short, almost linear, segment of the transfer curve. Digital applications, on the other hand, make use of the gross nonlinearity exhibited by the VTC.
With these observations in mind, we show in Fig. 13.3 a possible VTC of a logic inverter.
For simplicity, we are using three straight lines to approximate the VTC, which is usually a nonlinear curve such as that in Fig. 13.2. Observe that the output high level, denoted VOH, does not depend on the exact value of vI as long as vI does not exceed the value labeled VIL; when vI exceeds VIL, the output decreases and the inverter enters its amplifier region of Figure 13.2 The simple resistively loaded MOS amplifier can be used as a logic inverter when operated in cut-off and in triode . The output high level is VDD and the low level is VOD.
Figure 13.3 Voltage transfer characteristic of an inverter. The VTC is approximated by three straight-line segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).
RD vO Q vI (a) VDD iD D VOD vO Q in Saturation VDD Q Off B Q in triode Vtn VIC (b) VDD vI C 0 A vI Vtn < ( ) vI VIC > ( ) vO VOH VOL VOL 0 VIL VIH VOH vI NMH NML 1064 Chapter 13 CMOS Digital Logic Circuits operation, also called the transition region. It follows that VIL is an important parameter of the inverter VTC: It is the maximum value that vI can have while being interpreted by the inverter as representing a logic 0.
Similarly, we observe that the output low level, denoted VOL, does not depend on the exact value of vI as long as vI does not fall below VIH. Thus VIH is an important parameter of the inverter VTC: It is the minimum value that vI can have while being interpreted by the inverter as representing a logic 1.
13.1.3 Noise Margins The insensitivity of the inverter output to the exact value of vI within allowed regions is a great advantage that digital circuits have over analog circuits. To quantify this insensitivity property, consider the situation that occurs often in a digital system where an inverter (or a logic gate based on the inverter circuit) is driving another similar inverter, as shown in Fig. 13.4 Here we assume that a noise or interference signal is somehow coupled to the inter-connection between the output of inverter and the input of inverter with the result that the input of becomes (13.1) where the noise voltage can be either positive or negative. Now consider the case ; that is, inverter is driven by a logic-0 signal. Reference to Fig. 13.3 indi-cates that in this case will continue to function properly as long as its input does not exceed . Equation (13.1) then indicates that can be as high as VIL–VOL while con-tinues to function properly. Thus, we can say that inverter has a noise margin for low input, , of (13.2) Similarly, if , the driven inverter will continue to see a high input as long as does not fall below . Thus, in the high-input state, inverter can tolerate a nega-tive of magnitude as high as . We can thus state that has a high-input noise margin, , of (13.3) In summary, four parameters, VOH, VOL, VIH, and VIL, define the VTC of an inverter and determine its noise margins, which in turn measure the ability of the inverter to tolerate.
Figure 13.4 Noise voltage vN is coupled to the interconnection between the output of inverter G1 and the input of inverter G2.
vN G1 G2 G2 vI2 vO1 vN + = vN vO1 VOL = G2 G2 vI2 VIL vN G2 G2 NML NML VIL VOL – = vO1 VOH = G2 vI2 VIH G2 vN VOH VIH – G2 NMH NMH VOH VIH – = G1 G2 vO1 vI2 vN 13.1 Digital Logic Inverters 1065 variations in the input signal levels. In this regard, observe that changes in the input signal level within the noise margins are rejected by the inverter. Thus noise is not allowed to propagate further through the system, a definite advantage of digital over analog circuits.
Alternatively, we can think of the inverter as restoring the signal levels to standard values (VOL and VOH) even when it is presented with corrupted input signal levels (within the noise margins). As a summary, useful for future reference, we present a listing and definitions of the important parameters of the inverter VTC in Table 13.1. The formal definitions of the threshold voltages and are given in Fig. 13.5.
Observe that and are defined as the VTC points at which the slope is V/V. As exceeds the magnitude of the inverter gain increases and the VTC enters its transi-tion region. Similarly, as falls below the inverter enters the transition region and the magnitude of the gain increases. Finally, note that Fig. 13.5 shows the definition of another important point on the VTC; this is point M at which Point M is loosely consid-ered to be the midpoint of the VTC and thus the point at which the inverter switches from one state to the other. Point M plays an important role in the definition of the time delay of the inverter, as we shall see shortly.
Table 13.1 Important Parameters of the VTC of the Logic Inverter (Refer to Fig. 13.3) VOL: Output low level VOH: Output high level VIL: Maximum value of input interpreted by the inverter as a logic 0 VIH: Minimum value of input interpreted by the inverter as a logic 1 NML: Noise margin for low input = VIL – VOL NMH: Noise margin for high input = VOH – VIH Figure 13.5 Typical voltage transfer characteristic (VTC) of a logic inverter, illustrating the definition of the critical points.
VIL VIH VIL VIH 1 – vI VIL, vI VIH, vO vI.
= Slope 1 VM VM VIL 1066 Chapter 13 CMOS Digital Logic Circuits 13.1.4 The Ideal VTC The question naturally arises as to what constitutes an ideal VTC for an inverter. The answer follows directly from the preceding discussion: An ideal VTC is one that maximizes the out-put signal swing and the noise margins. For an inverter operated from a power supply maximum signal swing is obtained when and To obtain maximum noise margins, we first arrange for the transition region to be made as narrow as possible and ideally of zero width. Then, the two noise margins are equalized by arranging for the transition from high to low to occur at the midpoint of the power supply, that is, at The result is the VTC shown in Fig. 13.6, for which Observe that the sharp transition at indicates that if the inverter were to be used as an amplifier, its gain would be infinite. Again, we point out that while the analog designer’s interest would be focused on the transition region of the VTC, the digital designer would prefer the transition region to be as narrow as possible, as is the case in the ideal VTC of Fig.
13.6. Finally, we will see in Section 13.2 that inverters implemented using CMOS technol-ogy come very close to realizing the ideal VTC 13.1.5 Inverter Implementation Inverters are implemented using transistors (Chapters 5 and 6) operating as voltage-controlled switches. The simplest inverter implementation. is shown in Fig. 13.7(a). The switch is Figure 13.6 The VTC of an ideal inverter.
VDD, VOH VDD = VOL 0 = VDD 2.
⁄ VIL VIH VM VDD = 2 ⁄ = = VDD 2 ⁄ VOL 0 vO 2 VOH VDD VIL VIH VM VDD VDD vI 13.1 Digital Logic Inverters 1067 controlled by the inverter input voltage vI: When vI is low, the switch will be open and vO = VDD, since no current flows through R. When vI is high, the switch will be closed and, assuming an ideal switch, vO will be 0.
Transistor switches, however, as we know from Chapters 5 and 6, are not perfect.
Although their off resistances are very high and thus an open switch closely approximates an open circuit, the “on” switch has a finite closure or “on” resistance, Ron. The result is that when vI is high, the inverter has the equivalent circuit shown in Fig. 13.7(c), from which VOL can be found.1 We observe that the circuit in Fig. 13.2(a) is a direct implementation of the inverter in Fig.
13.7. In this case, is equal to of the MOSFET evaluated at its operating point in the triode region with .
Figure 13.7 (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b) equivalent circuit when vI is low; (c) equivalent circuit when vI is high. Note that the switch is assumed to close when vI is high.
1 If a BJT is used to implement the switch in Fig. 13.7(a), its equivalent circuit in the closed position includes in addition to the resistance , an offset voltage of about 50 mV to 100 mV (see Fig. 6.19c). We shall not pursue this subject any further here, since the relatively long delay time needed to turn off a saturated BJT has caused the use of BJT switches operated in saturation to all but disappear from the digital IC world.
vI VDD R vO (a) vI low VDD R vO (b) vI high VDD R Ron (c) vO Ron RCEsat = VOL VDD Ron R Ron + ------------------= Ron rDS VGS VDD = D13.1 Design the inverter in Fig. 13.2(a) to provide and to draw a supply current of in the low-output state. Let the transistor be specified to have , and . The power supply . Specify the required values of W/L and . How much power is drawn from when the switch is open? Closed? Hint: Recall that for small , VOL 0.1 V = 50 μA Vt 0.5 V, = μnCox 125 μA V2 ⁄ = λ 0 = VDD 2.5 V = RD VDD vDS EXERCISE 1068 Chapter 13 CMOS Digital Logic Circuits More elaborate implementations of the logic inverter exist, and we show two of these in Fig. 13.8(a) and 13.9. The circuit in Fig. 13.8(a) utilizes a pair of complementary switches, the “pull-up” (PU) switch connects the output node to VDD, and the “pull-down” (PD) switch connects the output node to ground. When vI is low, the PU switch will be closed and the PD switch open, resulting in the equivalent circuit of Fig. 13.8(b). Observe that in this case Ron of PU connects the output to VDD, thus establishing VOH = VDD. Also observe that no current flows and thus no power is dissipated in the circuit. Next, if vI is raised to the logic-1 level, the PU switch will open while the PD switch will close, resulting in the equivalent circuit shown in Fig. 13.8(c). Here Ron of the PD switch connects the output to ground, thus establishing VOL = 0. Here again no current flows, and no power is dissi-pated. The superiority of this inverter implementation over that using the single pull-down switch and a resistor (known as a pull-up resistor) should be obvious: With VOL = 0 and VOH = VDD, the signal swing is at its maximum possible, and the power dissipation is zero in both states. This circuit constitutes the basis of the CMOS inverter that we will study in Section 13.3. Finally, consider the inverter implementation of Fig. 13.9. Here a double-throw switch is used to steer the constant current IEE into one of two resistors connected to the positive supply VCC. The reader is urged to show that if a high vI results in the switch being connected to RC1, then a logic inversion function is realized at vO1. Note that the output voltage is inde-pendent of the switch resistance. This current-steering or current-mode logic arrangement is the basis of the fastest available digital logic circuits, called emitter-coupled logic (ECL), which we shall study in Section 14.4. In fact, ECL is the only BJT logic-circuit type that is currently employed in new designs and the only one studied in this book.
Figure 13.8 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter that we shall study in Section 13.2.
Ans. 2; 48 k ; 0; 125 rDS 1 μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞VGS Vt – ( ) Ω μW vI VDD PU PD R (a) PU vI high VDD Ron vO vO vO (c) PD Ron vI low VDD (b) 13.1 Digital Logic Inverters 1069 Figure 13.9 Another inverter implementation utilizing a double-throw switch to steer the constant current IEE to RC1 (when vI is high) or RC2 (when vI is low). This is the basis of the emitter-coupled logic (ECL) studied in Chapter 14.
vI VCC vO2 vO1 RC1 RC2 IEE VEE 13.2 For the current-steering circuit in Fig. 13.9, let and . What are the high and low logic levels obtained at the outputs?
Ans.
; VCC 5 V, = IEE 1 mA, = RC1 RC2 2 kΩ = = VOH 5 V = VOL 3 V = EXERCISE For the simple MOS inverter in Fig. 13.2(a): (a) Derive expressions for and . For simplicity, neglect channel-length modula-tion (i.e., assume ). Show that these inverter parameters can be expressed in terms of , and The latter parameter has the dimension of ; and to simplify the expressions, denote (b) Show that can be used as a design parameter for the inverter circuit. In particular, find the value of that results in .
(c) Find numerical values for all parameters and for the inverter noise margins for and set to the value found in (b).
(d) For and W/L = 1.5, find the required value of and use it to determine the aver-age power dissipated in the inverter, assuming that the inverter spends half of the time in each of its two states.
(e) Comment on the characteristics of this inverter circuit vis-à-vis the ideal characteristics as well as on its suitability for implementation in integrated-circuit form.
VOH, VOL, VIL, VIH, VM λ 0 = VDD, Vt knRD ( ).
V 1 – knRD 1 Vx ⁄ .
≡ Vx Vx VM VDD 2 ⁄ = VDD 1.8 V, = Vt 0.5 V, = Vx kn ′ 300 μA V2 ⁄ = RD Example 13.1 Resistively Loaded MOS Inverter 1070 Chapter 13 CMOS Digital Logic Circuits Example 13.1 continued Solution (a) Refer to Fig. 13.10. For the MOSFET is off, and Thus (13.4) As exceeds the MOSFET turns on and operates initially in the saturation region. Assuming , and substituting , the BC segment of the VTC is described by (13.5) To determine , we differentiate Eq. (13.5) and set , Figure 13.10 The resistively loaded MOS inverter and its VTC (Example 13.1).
RD vO vI Q (a) VDD iD VOL VM VOH VIH (b) A B Vt VM VDD vI vO C 0 M 1 1 NML VIL NMH D vI Vt, < iD 0, = vO VDD.
= VOH VDD = vI Vt, λ 0 = iD 1 2 ---kn vI Vt – ( )2RD = vO VDD RDiD VDD 1 2 ---knRD vI Vt – ( )2 – = – = knRD 1 Vx ⁄ = vO VDD 1 2Vx --------- vI Vt – ( )2 – = VIL dvO dvI ⁄ 1 – = dvO dvI ---------1 Vx ----- vI Vt – ( ) – = 1 1 Vx ----- VIL Vt – ( ) – = – 13.1 Digital Logic Inverters 1071 which results in (13.6) To determine the coordinates of the midpoint M, we substitute in Eq. (13.5), thus obtaining (13.7) which can be solved to obtain (13.8) The boundary of the saturation-region segment BC, point C, is determined by substituting in Eq. (13.5) and solving for to obtain (13.9) and (13.10) Beyond point C, the transistor operates in the triode region, thus and the output voltage is obtained as (13.11) which describes the segment CD of the VTC. To determine , we differentiate Eq. (13.11) and set : which results in (13.12) Substituting in Eq. (13.11) for with the value of from Eq. (13.12) results in an equation in the value of corresponding to , which can be solved to yield (13.13) which can be substituted in Eq. (13.12) to obtain (13.14) VIL Vt Vx + = vO vI VM = = VDD VM 1 2Vx --------- VM Vt – ( )2 = – VM Vt 2 VDD Vt – ( )Vx Vx 2 + Vx – + = vO vI Vt – = vO VOC 2VDDVx Vx 2 + Vx – = VIC Vt 2VDDVx Vx 2 + Vx – + = iD kn vI Vt – ( )vO 1 2 ---vO 2 – = vO VDD 1 Vx -----vI Vt – ( )vO 1 2 ---vO 2 – – = VIH dvO dvI ⁄ 1 – = dvO dvI ---------1 Vx -----⎝ ⎠ ⎛ ⎞ vI Vt – ( )dvO dvI ---------vO vO dvO dvI ---------– + – = 1 1 Vx -----VIH Vt – ( ) – 2vO + [ ] – = – VIH Vt 2vO Vx – = – vI VIH vO vI VIH = vO vI VIH = 0.816 VDDVx = VIH Vt 1.63 VDDVx Vx – + = 1072 Chapter 13 CMOS Digital Logic Circuits Example 13.1 continued To determine we substitute in Eq. (13.11): (13.15) Since we expect to be much smaller than , we can approximate Eq. (13.15) as which results in (13.16) It is interesting to note that the value of can alternatively be found by noting that at point D, the MOSFET switch has a closure resistance , (13.17) and can be obtained from the voltage divider formed by and , (13.18) Substituting for from Eq. (13.17) gives an expression for identical to that in Eq. (13.16).
(b) We observe that all the inverter parameters derived above are functions of , , and only.
Since and are determined by the process technology, the only design parameter available is . To place at half the supply voltage , we substitute in Eq. (13.7) to obtain the value must have as (13.19) (c) For and , we use Eq. (13.19) to obtain From Eq. (13.4): From Eq. (13.16): From Eq. (13.6): From Eq. (13.14): (d) To determine we use VOL vI VOH VDD = = VOL VDD 1 Vx -----VDD Vt – ( )VOL 1 2 ---VOL 2 – – = VOL 2 VDD Vt – ( ) VOL VDD 1 Vx ----- VDD Vt – ( )VOL – VOL VDD 1 VDD Vt – ( ) Vx ⁄ [ ] + --------------------------------------------------= VOL rDS rDS 1 kn VDD Vt – ( ) -------------------------------= VOL RD rDS VOL VDD rDS RD rDS + ---------------------VDD 1 RD rDS ⁄ + ----------------------------= = rDS VOL VDD Vt Vx VDD Vt Vx 1 knRD ⁄ ≡ VM VDD VM VDD 2 ⁄ = Vx Vx VM VDD 2 ⁄ = VDD 2 Vt – ⁄ ( )2 VDD -----------------------------------= VDD 1.8 V = Vt 0.5 = Vx VM 0.9 V = 1.8 2 0.5 – ⁄ ( )2 1.8 -----------------------------------0.089 V = = VOH 1.8 V = VOL 0.12 V = VIL 0.59 V = VIH 1.06 V = NML VIL VOL 0.47 V = – = NMH VOH VIH 0.74 V = – = RD, knRD 1 Vx -----1 0.089 -------------11.24 = = = 13.1 Digital Logic Inverters 1073 Thus, The inverter dissipates power only when the output is low, in which case the current drawn from the sup-ply is and the power drawn from the supply during the low-output interval is Since the inverter spends half of the time in this state, (e) We now can make a few comments on the characteristics of this inverter circuit in comparison to the ideal characteristics: 1.
The output signal swing, though not equal to the full power supply, is reasonably good: 2.
The noise margins, though of reasonable values, are far from the optimum value of This is particularly the case for 3.
Most seriously, the gate dissipates a relatively large amount of power. To appreciate this point, con-sider an IC chip with a million inverters (a small number by today’s standards): Its power dissipation will be 61 W. This is too large, especially given that this is “static power,” unrelated to the switching activity of the gates (more on this later).
We consider this inverter implementation to be entirely unsuitable for IC fabrication because each inverter requires a load resistance of 25 k a value that needs a large chip area (see Appendix A). To overcome this problem, we investigate in Example 13.2 the replacement of the passive resistance with an NMOS transistor.
RD 11.24 kn ′ W L ⁄ ( ) ----------------------11.24 300 10 6 – 1.5 × × ---------------------------------------25 kΩ = = = IDD VDD VOL – RD -------------------------1.8 0.12 – 25 kΩ ------------------------67 μA = = = PD VDDIDD 1.8 67 121 μW = × = = PDaverage 1 2 ---PD 60.5 μW = = VOH 1.8 V, = VOL 0.12 V.
= VDD 2 ⁄ .
NML.
Ω, RD D13.3 In an attempt to reduce the required value of to 10 the designer of the inverter in Ex-ample 13.1 decides to keep the parameter unchanged but increases W/L. What is the new value required for W/L? Do the noise margins change? What does the power dissipation become?
Ans. 3.75; no; 151 D13.4 In an attempt to reduce the required value of to 10 the designer of the inverter in Exam-ples 13.1 decides to change while keeping W/L unchanged. What new value of is needed?
What do the noise margins become? What does the power dissipation become?
Ans. 139 RD, kΩ, Vx μW RD kΩ, Vx Vx Vx 0.22 V; = NML 0.46 V, = NMH 0.49 V; = μW EXERCISES 1074 Chapter 13 CMOS Digital Logic Circuits 2 To overcome the problem associated with the need for a large resistance in the circuit of Fig.
13.10(a), studied in Example 13.1, can be replaced by a MOSFET. One such possibility is the circuit shown in Fig. 13.11(a), where the load is an NMOS transistor operated in the saturation region (by connecting its drain to its gate). Although not shown on the diagram, the body terminal of is con-nected to the lowest-voltage node, which is ground.
(a) Neglecting the body effect in and assuming , determine the inverter parameters , , , , and . Express the results in terms of (where ), and (b) For , and find numerical values for all param-eters and for the noise margins.
(c) If find the average power dissipated in the inverter, assuming that it spends half the time in each of its two states.
(d) Qualitatively describe how the body effect in affects the noise margins.
(e) Comment on the characteristics of this inverter implementation vis-à-vis the ideal characteristics.
How suitable is this circuit for implementation in IC form?
Figure 13.11 (a) Enhancement-load MOS inverter; (b) load curve; (c) construction to determine VTC; (d) the VTC.
RD RD Q2 Q2 Q2 λ1 λ2 0 = = VOH VOL VIL VIH VM VDD, Vt Vt1 Vt2 Vt = = kr kn1 kn2 ⁄ .
≡ VDD 1.8 V, = Vt 0.5 V = W L ⁄ ( )1 5, = W L ⁄ ( )2 1 5 ---, = kn ′ 300 μA V2, ⁄ = Q2 VDD Q2 Q1 i v vO vI (a) Vt2 0 v i (b) vI Vt2 vI VDD Vt2 VDD VDD – Vt2 A, B Load curve 0 vO i D C (c) VIL Vt1 NML NMH VDD Vt2 Slope kr 1 VIH VOH VOL 0 vI vO D C M A B (d) Example 13.2 The Saturated NMOS-Load Inverter 13.1 Digital Logic Inverters 1075 2To see this point more clearly, consider the usual situation of a capacitance between the output node of the inverter and ground. Assume that initially was high and was low. Now let go low. cuts off, and provides a current that charges up. As increases, the current provided by decreases until reaches , at which point the current supplied by reaches zero.
Thus the charging process terminates and stabilizes at .
CL vI vO vI Q1 Q2 CL vO Q2 vO VDD Vt2 – Q2 vO VDD Vt2 – Solution (a) The inverter VTC can be determined graphically by superimposing the load curve, which is the characteristic of the diode-connected transistor shown in Fig. 13.11(b), on the characteristics of . As we have done in the graphical analysis of MOSFET circuits in Section 5.4, we shift the load curve horizontally by and flip it around the vertical axis, as shown in Fig. 13.11(c). The resulting VTC is shown in Fig. 13.11(d).
For , will be off, which forces the current in to be zero. Transistor although it will be conducting a zero current, will have a voltage drop of This is a result of its characteristic shown in Fig. 13.11(b). Thus the output voltage will not reach but will be at that is,2 (13.20) As exceeds , turns on and initially operates in saturation, thus Since operates in saturation at all times, Equating and and substituting , and , gives (13.21) which is the equation for segment BC of the VTC in Fig. 13.11(d). It is interesting to observe that the rela-tionship between and is linear and that the slope of this straight line is Since the slope of the VTC changes from zero to at point B, it is reasonable to consider point B to be the determinant of ; thus, (13.22) To obtain we substitute in Eq. (13.21); thus, (13.23) We next determine the coordinates of point C at which enters the triode region by substituting in Eq. (13.21) . The result is (13.24) d i v – Q2, i v – Q1 VDD vI Vt1 < Q1 Q2 Q2, Vt2.
i v – vO VDD VDD Vt2, – VOH VDD Vt – = vI Vt1 Q1 iD1 1 2 ---kn1 vI Vt1 – ( )2 = Q2 iD2 1 2 ---kn2 VDD vO V – t2 – ( )2 = iD1 iD2 Vt1 Vt2 Vt = = kn1 kn2 ⁄ kr = vO VDD kr 1 – ( )Vt krvI – + = vO vI kr.
– kr – VIL VIL Vt1 Vt = = VM vI vO VM = = VM VDD kr 1 – ( )Vt + kr 1 + ----------------------------------------= Q1 vO vI Vt – = VIC VDD krVt + kr 1 + --------------------------= 1076 Chapter 13 CMOS Digital Logic Circuits Example 13.2 continued and (13.25) Comparing Eqs. (13.24) and (13.23), we make the comforting observation that , confirming our implicit assumption that M lies on the linear segment of the VTC.
For , operates in the triode region; thus, Meanwhile, still operates in saturation. Equating their currents results in (13.26) Although this equation can be used to determine the effort involved to do this symbolically is too great. We will instead find numerically; however, can be determined by substituting in Eq.
(13.26) and (13.27) Since we expect to be much smaller than and we can approximate Eq. (13.27) as follows: Thus, (13.28) We observe that all the inverter parameters are functions of three quantities only: and Since the first two are determined by the process technology, the only design parameter is which determines the steepness of the transition region.
(b) Given and we first determine as From Eq. (13.20): From Eq. (13.28): From Eq. (13.22): From Eq. (13.23): To determine we utilize Eq. (13.26) together with setting The result is VOC VDD Vt – kr 1 + ---------------------= VIC VM > vI VIC > Q1 iD1 kn1 vI Vt1 – ( )vO 1 2 ---vO 2 – = Q2 2kr 2 vI Vt – ( )vO 1 2 ---vO 2 – VDD Vt – vO – ( )2 = VIH, VIH VOL, vI VOH VDD Vt – = = vO VOL, = 2kr 2 VDD 2Vt – ( )VOL 1 2 ---VOL 2 – VDD Vt – VOL – ( )2 = VOL 2 VDD 2Vt – ( ) VDD Vt – ( ), 2kr 2 VDD 2Vt – ( )VOL VDD Vt – ( )2 VOL VDD Vt – ( )2 2kr 2 VDD 2Vt – ( ) --------------------------------------VDD, Vt, kr.
kr, VDD 1.8 V, = Vt 0.5 V, = W L ⁄ ( )1 5, = W L ⁄ ( )2 1 5 ---, = kr kr kn1 kn2 -------W L ⁄ ( )1 W L ⁄ ( )2 -------------------5 1 5 ⁄ ----------5 = = = = VOH 1.3 V = VOL 0.04 V = VIL 0.5 V = VM 0.63 V = VIH dvO dvI 1.
– = ⁄ VIH 0.75 V = 13.1 Digital Logic Inverters 1077 Thus, (c) The inverter dissipates power only when In this case, the current drawn from the supply is Thus, and, Since the inverter is in the low-output state for half the time, (d) Since the body of is connected to ground, its source-to-body voltage is Now, since the threshold voltage is given by (13.29) we see that will increase with This is of immense concern, since will be at its largest value for Thus, will be lower than the value calculated above. This reduces the output signal swing and (e) We now can make the following comments on the characteristics of this inverter implementation: 1.
The fact that is lower than by and that can be large because of the body effect im-poses a major disadvantage on this NMOS-load inverter.
2.
The noise margins are much lower than the ideal values of Also, is far from the power-supply midpoint.
3.
The sharpness of the transition of the VTC increases with the value of Increasing however, has the effect of increasing the silicon area (see Exercise 13.6).
4.
Like the resistively-loaded MOS inverter considered in Example 13.1, the NMOS-loaded inverter dis-sipates a large amount of power.
Since the circuit utilizes NMOS transistors exclusively, it is certainly suitable for implementation in IC form. As we will discuss shortly, all-NMOS technology was at one time (1970s) the technology of choice for the implementation of microprocessor chips. Its high power dissipation, however, has caused its demise in favor of CMOS technology.
NML VIL VOL 0.5 0.04 0.46 V = – = – = NMH VOH VIH 1.3 0.75 0.55 V = – = – = vO VOL.
= IDD iD2 1 2 ---kn2 VDD VOL – Vt – ( )2 = = IDD 1 2 ---300 1 5 ---× × 1.8 0.04 – 0.5 – ( )2 × = 47.6 μA = PD VDDIDD 1.8 47.6 85.7 μW = × = = PDaverage 1 2 ---85.7 42.9 = × μW = Q2 VSB V SB vO = Vt2 Vt0 γ VSB 2φf + 2φf – [ ] + = Vt2 vO.
Vt2 vO VOH VDD Vt2.
– = = VOH NMH.
VOH VDD Vt2 Vt2 VDD 2 ⁄ .
VM kr.
kr, 1078 Chapter 13 CMOS Digital Logic Circuits 13.1.6 Power Dissipation Digital systems are implemented using very large numbers of logic gates. For space and other economic considerations, it is desirable to implement the system with as few integrated-circuit (IC) chips as possible. It follows that one must pack as many logic gates as possible on an IC chip. At present, one million gates or more can be fabricated on a single IC chip in what is known as very-large-scale integration (VLSI). To keep the power dissipated in the chip to acceptable limits (imposed by thermal considerations), the power dissipation per gate must be kept to a minimum. Indeed, a very important performance measure of the logic inverter is the power it dissipates.
The inverter of Fig. 13.7 dissipates no power when vI is low and the switch is open. In the other state, however, the power dissipation is approximately and can be sub-stantial, as we have seen in Examples 13.1 and 13.2. This power dissipation occurs even if the inverter is not switching and is thus known as static power dissipation.
The inverter of Fig. 13.8 exhibits no static power dissipation, a definite advantage. Unfor-tunately, however, another component of power dissipation arises when a capacitance exists between the output node of the inverter and ground. This is always the case, for the devices that implement the switches have internal capacitances, the wires that connect the inverter out-put to other circuits have capacitance, and, of course, there is the input capacitance of whatever circuit the inverter is driving. Now, as the inverter is switched from one state to another, cur-rent must flow through the switch(es) to charge (and discharge) the load capacitance. These currents give rise to power dissipation in the switches, called dynamic power dissipation. An expression for the dynamic power dissipation of the inverter of Fig. 13.8 can be derived as follows. Consider first the situation when goes low. The pull-down switch 13.5 Repeat part (b) of Example 13.3 for the case and Specifically, find the values of and Ans. 1.3 V; 0.12 V; 0.5 V; 0.87 V; 0.7 V; 0.43 V; 0.38 V 13.6 Consider the inverter in Fig. 13.11(a) with and Show that if the minimum dimension (i.e. length or width) of each of the two transistors is denoted d, the inverter silicon area is W L ⁄ ( )1 3 = W L ⁄ ( )2 1 3 ---.
= VOH, VOL, VIL, VIH, VM, NMH, NML.
W L ⁄ ( )1 kr = W L ⁄ ( )2 1 kr ⁄ .
= 2krd2.
EXERCISES VDD 2 R ⁄ vI PD RPU VDD C (a) RPD C (b) Figure 13.12 Equivalent circuits for calculating the dynamic power dissipation of the inverter in Figure 13.8: (a) When vI is low; (b) When vI is high.
13.1 Digital Logic Inverters 1079 turns off and the pull-up switch turns on. In this state, the inverter can be represented by the equivalent circuit shown in Fig. 13.12(a). Capacitor C will charge through the on-resistance of the pull-up switch, and the voltage across C will increase from 0 to Denoting by the charging current supplied by we can write for the instantaneous power drawn from the expression The energy delivered by the power supply to charge the capacitor can be determined by inte-grating over the charging interval where Q is the charge delivered to the capacitor during the charging interval. Since the ini-tial charge on C was zero, Thus, (13.30) Since at the end of the charging process the energy stored on the capacitor is (13.31) we can find the energy dissipated in the pull-up switch as (13.32) This energy is dissipated in the on-resistance of switch and is converted to heat. Next consider the situation when goes high. The pull-up switch turns off and the pull-down switch turns on. The equivalent circuit in this case is that shown in Fig.
13.12(b). Capacitor C is discharged through the on-resistance of the pull-down switch, and its voltage changes from to 0. At the end of the discharge interval, there will be no energy left on the capacitor. Thus all of the energy initially stored on the capacitor, , will be dissipated in the pull-down switch, (13.33) This amount of energy is dissipated in the on-resistance of switch and is converted to heat.
Thus in each cycle of inverter switching, an amount of energy of is dissipated in the pull-up switch and is dissipated in the pull-down switch, for a total energy loss per cycle of (13.34) PU VDD.
iD t ( ) VDD, VDD pDD t ( ) VDDiD t ( ) = pDD t ( ) Tc, EDD VDDiD t ( ) t d 0 Tc ∫ = VDD iD t ( ) t d 0 Tc ∫ = VDDQ = Q CVDD = EDD CVDD 2 = Estored 1 2 ---CVDD 2 = Edissipated EDD Estored 1 2 ---CVDD 2 = – = PU vI PU PD VDD 1 2 ---CVDD 2 Edissipated 1 2 ---CVDD 2 = PD 1 2 ---CVDD 2 1 2 ---CVDD 2 Edissipated cycle CVDD 2 = ⁄ 1080 Chapter 13 CMOS Digital Logic Circuits If the inverter is switched at a frequency of f Hz, the dynamic power dissipation of the inverter will be (13.35) This is a general expression that does not depend on the inverter circuit details or the values of the on-resistance of the switches.
The expression in Eq. (13.35) indicates that to minimize the dynamic power dissipation, one must strive to reduce the value of C. However, in many cases C is largely determined by the transistors of the inverter itself and cannot be substantially reduced. Another important factor in determining the dynamic power dissipation is the power-supply voltage Reducing , reduces significantly. This has been a major motivating factor behind the reduction of with every technology generation (see Table 7.A.1). Thus, while the 0.5-μm CMOS process utilized a 5-V power supply, the power-supply voltage used with the 0.13-μm process is only 1.2 V.
Finally, since is proportional to the operating frequency f, one may be tempted to reduce by reducing f. This, however, is not a viable proposition in light of the desire to operate digital systems at increasingly higher speeds. This point will be discussed next.
13.1.7 Propagation Delay A very important measure of the performance of a digital system, such as a computer, is the maximum speed at which it is capable of operating. Although many factors come into play in determining the operating speed of a system, a core factor is the speed of operation of the basic logic inverter utilized in its implementation. This in turn is characterized by the time it takes the inverter to respond to a change at its input. To be more precise, consider an inverter fed with the ideal pulse shown in Fig. 13.13(a). The resulting output signal of the inverter is shown in Fig. 13.13(b). We make the following two observations.
1. The output signal is no longer an ideal pulse. Rather, it has rounded edges; that is, the pulse takes some time to fall to its low value and to rise to its high value. We speak of this as the pulse having finite fall and rise times. We will provide a precise definition of these shortly.
2. There is a time delay between each edge of the input pulse and the corresponding change in the output of the inverter. If we define the “switching point” of the output as the time at Pdyn fCVDD 2 = VDD.
VDD Pdyn VDD Pdyn Pdyn 13.7 Find the dynamic power dissipation of an inverter operated from a 1.8-V supply and having a load capacitance of 100 fF. Let the inverter be switched at 100 MHz.
Ans. 32.4 13.8 A particular inverter circuit initially designed in a 0.5-μm process is fabricated in a 0.13-μm process.
Assuming that the capacitance C will scale down in proportion to the minimum feature size (more on this later) and that the power supply will be reduced from 5 V to 1.2 V, by what factor do you expect the dynamic power dissipation to decrease? Assume that the switching frequency f remains unchanged.
Ans. 66.8 μW EXERCISES 13.1 Digital Logic Inverters 1081 which the output pulse passes through the half-point of its excursion, then we can define the propagation delays of the inverter as indicated in Fig. 13.13(b). Note that there are two propagation delays, which are not necessarily equal: the propagation delay for the output going from high to low, and the propagation delay for the output going from low to high, . The inverter propagation delay is defined as the average of the two, (13.36) Having defined the inverter propagation delay, we now consider the maximum switching frequency of the inverter. From Fig. 13.13(b) we can see that the minimum period for each cycle is (13.37) Thus the maximum switching frequency is (13.38) At this point the reader is no doubt wondering about the cause of the finite propagation time of the inverter. It is simply a result of the time needed to charge and discharge the various capacitances in the circuit. These include the MOSFET capacitances, the wiring capaci-tance, and the input capacitances of all the logic gates driven by the inverter. We will have a lot more to say about these capacitances and about the determination of in later sections.
For the time being, however, we make two important points: 1. A fundamental relationship in analyzing the dynamic operation of a circuit is (13.39) Figure 13.13 An inverter fed with the ideal pulse in (a) provides at its output the pulse in (b). Two delay times are defined as indicated.
VDD vI t 0 (a) VDD vO t 0 2 VDD tPHL tPLH (b) tPHL, tPLH tP tP 1 2 --- tPLH tPHL + ( ) ≡ Tmin tPHL tPLH 2tP = + = fmax 1 Tmin ---------1 2tP -------= = tP I t Q C V Δ = Δ = Δ 1082 Chapter 13 CMOS Digital Logic Circuits That is, a current I flowing through a capacitance C for an interval deposits a charge on the capacitor, which causes the capacitor voltage to increase by .
2. A thorough familiarity with the time response of single-time-constant (STC) circuits is of great help in the analysis of the dynamic operation of digital circuits. A review of this subject is presented in Appendix E. For our purposes here, we remind the reader of the key equation in determining the response to a step function: Consider a step-function input applied to an STC network of either the low-pass or high-pass type, and let the network have a time constant τ. The output at any time t is given by (13.40) where Y∞ is the final value, that is, the value toward which the response is heading, and Y0+ is the value of the response immediately after t = 0. This equation states that the output at any time t is equal to the difference between the final value Y∞ and a gap whose initial value is Y∞ – Y0+ and that is shrinking exponentially.
t Δ Q Δ V Δ y t ( ) Y∞ Y∞ Y0+ – ( )e t/τ – – = Consider the inverter of Fig. 13.7(a) with a capacitor C connected between the output node and ground. If at t = 0, goes low, and assuming that the switch opens instantaneously, find the time for to reach This is the low-to-high propagation time, Calculate the value of for the case R = 25 k and C = 10 fF.
Solution Before the switch opens, When the switch opens at t = 0, the circuit takes the form shown in Fig. 13.14(a). Since the voltage across the capacitor cannot change instantaneously, at the output will still be Then the capacitor charges through R, and rises exponentially toward The vI vO 1 2 --- VOH VOL + ( ).
tPLH.
tPLH Ω (a) C S VDD R vO Figure 13.14 Example 13.3: (a) The inverter circuit after the switch opens (i.e., for t ≥ 0+). (b) Waveforms of vI and vO. Observe that the switch is assumed to operate instantaneously. vO rises exponentially, starting at VOL and head-ing toward VOH.
vI 0 2 1 (b) VOH VDD VOL (VOH VOL ) vO t tPLH t 0 vO VOL.
= t 0+ = VOL.
vO VDD.
Example 13.3 13.1 Digital Logic Inverters 1083 We conclude this section by showing in Fig. 13.15 the formal definition of the propaga-tion delay of an inverter. As shown, an input pulse with finite (nonzero) rise and fall times is applied. The inverted pulse at the output exhibits finite rise and fall times (labeled tTLH and tTHL, where the subscript T denotes transition, LH denotes low to high, and HL denotes high to low). There is also a delay time between the input and output waveforms.
The usual way to specify the propagation delay is to take the average of the high-to-low propagation delay, tPHL, and the low-to-high propagation delay, tPLH. As indicated, these delays are measured between the 50% points of the input and output waveforms. Also note that the transition times are specified using the 10% and 90% points of the output excursion (VOH – VOL).
output waveform will be as shown in Fig. 13.14(b), and its equation can be obtained by substituting in Eq.
(13.39): and Thus, where To find we substitute Thus, which results in Note that this expression is independent of the values of and . For the numerical values given, = 173 ps vO ∞ ( ) VOH VDD = = vO 0+ ( ) VOL.
= vO t ( ) VOH VOH VOL – ( )e t τ ⁄ – – = τ CR.
= tPLH, vO tPLH ( ) 1 2 --- VOH VOL + ( ) = 1 2 --- VOH VOL + ( ) VOH VOH VOL – ( )e tPLH τ ⁄ – – = tPLH τ ln 2 = 0.69 τ = VOL VOH tPLH 0.69 RC = 0.69 25 103 × × 10 10 15 – × × = 13.9 A capacitor C whose initial voltage is 0 is charged to a voltage by a constant-current source I.
Find the time at which the capacitor voltage reaches What value of I is required to obtain a 10-ps propagation delay with C = 10 fF and ?
Ans.
; 0.9 mA 13.10 For the inverter of Fig. 13.8(a), let the on-resistance of be 20 and that of If the capacitance C = 10 fF, find and Ans. 138 ps; 69 ps; 104 ps VDD tPLH VDD 2 ⁄ ( ).
VDD 1.8 V = tPLH CVDD 2I ⁄ = PU kΩ PD 10 kΩ.
= tPLH, tPHL, tP.
EXERCISES 1084 Chapter 13 CMOS Digital Logic Circuits 13.1.8 Power–Delay and Energy–Delay Products One is usually interested in high-speed operation (low ) combined with low power dissi-pation. Unfortunately, these two requirements are often in conflict: Generally, if the designer of an inverter attempts to reduce power dissipation by, say, decreasing the supply voltage or the supply current, or both, the current-driving capability of the inverter decreases. This in turn results in longer times to charge and discharge the load and parasitic capacitances, and thus the propagation delay increases. It follows that a figure of merit for comparing logic-circuit technologies is the power–delay product (PDP) of the basic inverter of the given technology, defined as (13.41) Figure 13.15 Definitions of propagation delays and transition times of the logic inverter.
13.11 A capacitor C = 100 fF is discharged from a voltage to zero through a resistance .
Find the fall time of the capacitor voltage.
Ans.
VDD R 2 k = Ω tf tf 2.2CR 0.44 ns = EXERCISE tP VDD, PDP PDtP ≡ 13.1 Digital Logic Inverters 1085 where is the power dissipation of the inverter. Note that the PDP is an energy quantity and has the units of joules. The lower the PDP, the more effective the inverter and the logic circuits based on the inverter are.
For CMOS logic circuits, which is the digital IC technology of primary interest to us here, the static power dissipation of the inverter is zero,3 and thus is equal to and given by Eq. (13.35), Thus for the CMOS inverter, (13.42) If the inverter is operated at its maximum switching speed given by Eq. (13.38), then (13.43) From our earlier discussion of dynamic power dissipation we know that is the amount of energy dissipated during each charging or discharging event of the capacitor, that is, for each output transition of the inverter. Thus, the PDP has an interesting physical inter-pretation: It is the energy consumed by the inverter for each output transition.
Although the PDP is a valuable metric for comparing different technologies for imple-menting inverters, it is not useful as a design parameter for optimizing a given inverter cir-cuit. To appreciate this point, observe that the expression in Eq. (13.43) indicates that the PDP can be minimized by reducing as much as possible while, of course, maintaining proper circuit operation. This, however, would not necessarily result in optimal performance, for will increase as is reduced. The problem is that the PDP expression in Eq. (13.43) does not in fact have information about It follows that a better metric can be obtained by multiplying the energy per transition by the propagation delay. We can thus define the energy–delay product EDP as (13.44) We will utilize the EDP in later sections.
13.1.9 Silicon Area In addition to minimizing power dissipation and propagation delay, another objective in the design of digital VLSI circuits is the minimization of silicon area per logic gate. Smaller area requirement enables the fabrication of a larger number of gates per chip, which has eco-nomic and space advantages from a system-design standpoint. Area reduction occurs in three different ways: through advances in processing technology that enable the reduction of the minimum device size, through advances in circuit-design techniques, and through care-ful chip layout. In this book, our interest lies in circuit design, and we shall make frequent 3The exception to this statement is the power dissipation due to leakage currents and subthreshold con-duction in the MOSFETs, discussed in Section 13.5.3.
PD PD Pdyn PD fCVDD 2 = PDP fCVDD 2 tP = PDP 1 2 ---CVDD 2 = 1 2 ---CVDD 2 VDD tP VDD tP.
EDP Energy per transition tP × ≡ 1 2 ---CVDD 2 tP = 1086 Chapter 13 CMOS Digital Logic Circuits comments on the relationship between the circuit design and its silicon area. As a general rule, the simpler the circuit, the smaller the area required. As will be seen shortly, the circuit designer has to decide on device sizes. Choosing smaller devices has the obvious advantage of requiring smaller silicon area and at the same time reducing parasitic capacitances and thus increasing speed. Smaller devices, however, have lower current-driving capability, which tends to increase delay. Thus, as in all engineering design problems, there is a trade-off to be quantified and exercised in a manner that optimizes whatever aspect of the design is thought to be critical for the application at hand.
13.1.10 Digital IC Technologies and Logic-Circuit Families The chart in Figure 13.16 shows the major IC technologies and logic-circuit families that are currently in use. The concept of a logic-circuit family perhaps needs a few words of expla-nation. The basic element of a logic-circuit family is the inverter. A family would include a variety of logic-circuit types made with the same technology, having a similar circuit struc-ture, and exhibiting the same basic features. Each logic-circuit family offers a unique set of advantages and disadvantages. In the conventional style of designing systems, one selects an appropriate logic family (e.g., TTL, CMOS, or ECL) and attempts to implement as much of the system as possible using circuit modules (packages) that belong to this family. In this way, interconnection of the various packages is relatively straightforward. If, on the other hand, packages from more than one family are used, one has to design suitable interface cir-cuits. The selection of a logic family is based on such considerations as logic flexibility, speed of operation, availability of complex functions, noise immunity, operating-temperature range, power dissipation, and cost. We will discuss some of these considerations in this chapter and the next two. To begin with, we make some brief remarks on each of the four technologies listed in the chart of Fig. 13.16.
CMOS Although shown as one of four possible technologies, this is not an indication of digital IC market share: CMOS technology is, by a very large margin, the most dominant of all the IC technologies available for digital-circuit design. Although early microprocessors were made using NMOS logic (based on the inverter circuit we studied in Example 13.2), CMOS has completely replaced NMOS. There are a number of reasons for this develop-ment, the most important of which is the much lower power dissipation of CMOS circuits.
CMOS has also replaced bipolar as the technology of choice in digital-system design and has Figure 13.16 Digital IC technologies and logic-circuit families.
CMOS Complementary CMOS Pseudo-NMOS Digital IC technologies and logic-circuit families Pass-transistor logic TTL ECL Dynamic logic Bipolar BiCMOS GaAs 13.1 Digital Logic Inverters 1087 made possible levels of integration (or circuit-packing densities) and a range of applications, neither of which would have been possible with bipolar technology. Furthermore, CMOS continues to advance, whereas there appear to be few innovations at the present time in bipo-lar digital circuits. Some of the reasons for CMOS displacing bipolar technology in digital applications are as follows.
1. CMOS logic circuits dissipate much less power than bipolar logic circuits and thus one can pack more CMOS circuits on a chip than is possible with bipolar circuits.
2. The high input impedance of the MOS transistor allows the designer to use charge stor-age as a means for the temporary storage of information in both logic and memory cir-cuits. This technique cannot be used in bipolar circuits.
3. The feature size (i.e., minimum channel length) of the MOS transistor has decreased dra-matically over the years, with some recently reported designs utilizing channel lengths as short as 32 nm. This permits very tight circuit packing and, correspondingly, very high levels of integration. A microprocessor chip reported in 2009 had 2.3 billion transistors.
Of the various forms of CMOS, complementary CMOS circuits based on the inverter studied in Section 13.2 are the most widely used. They are available both as small-scale integrated (SSI) circuit packages (containing 1–10 logic gates) and medium-scale integrated (MSI) circuit packages (10–100 gates per chip) for assembling digital systems on printed-circuit boards. More significantly, complementary CMOS is used in very-large-scale-integrated (VLSI) logic (with millions of gates per chip) and memory-circuit design. In some applica-tions, complementary CMOS is supplemented by one (or both) of two other MOS logic circuit forms. These are pseudo-NMOS, so-named because of the similarity of its structure to NMOS logic, and pass-transistor logic, both of which will be studied in Chapter 14.
A fourth type of CMOS logic circuit utilizes dynamic techniques to obtain faster circuit operation, while keeping the power dissipation very low. Dynamic CMOS logic, studied in Chapter 14, represents an area of growing importance. Lastly, CMOS technology is used in the design of memory chips, as will be detailed in Chapter 15.
Bipolar Two logic-circuit families based on the bipolar junction transistor are in some use at present: TTL and ECL. Transistor–transistor logic (TTL or T2L) was for many years the most widely used logic-circuit family. Its decline was precipitated by the advent of the VLSI era. TTL manufacturers, however, fought back with the introduction of low-power and high-speed versions. In these newer versions, the higher speeds of operation are made possible by preventing the BJT from saturating and thus avoiding the slow turnoff process of a saturated bipolar transistor. These nonsaturating versions of TTL utilize the Schottky diode discussed in Section 4.7 and are called Schottky TTL or variations of this name.
Despite all these efforts, TTL is no longer a significant logic-circuit family and will not be studied in this book. However, the interested reader can find significant amounts of mate-rial on TTL on the CD accompanying this book and on the book’s website.
The other bipolar logic-circuit family in present use is emitter-coupled logic (ECL). It is based on the current-switch implementation of the inverter shown in Fig. 13.9. The basic element of ECL is the differential BJT pair studied in Chapter 8. Because ECL is basically a current-steering logic, and, correspondingly, also called current-mode logic (CML), in which saturation is avoided, very high speeds of operation are possible. Indeed, of all the commercially available logic-circuit families, ECL is the fastest. ECL is also used in VLSI circuit design when very high operating speeds are required and the designer is willing to accept higher power dissipation and increased silicon area. As such, ECL is considered an important specialty technology and will be discussed in Chapter 14.
1088 Chapter 13 CMOS Digital Logic Circuits BiCMOS BiCMOS combines the high operating speeds possible with BJTs (because of their inherently higher transconductance) with the low power dissipation and other excellent characteristics of CMOS. Like CMOS, BiCMOS allows for the implementation of both ana-log and digital circuits on the same chip. (See the discussion of analog BiCMOS circuits in Chapter 7.) At present, BiCMOS is used to great advantage in special applications, includ-ing memory chips, where its high performance as a high-speed capacitive-current driver jus-tifies the more complex process technology it requires. A brief discussion of BiCMOS is provided in Chapter 14.
Gallium Arsenide (GaAs) The high carrier mobility in GaAs results in very high speeds of operation. This has been demonstrated in a number of digital IC chips utilizing GaAs technology. It should be pointed out, however, that GaAs remains an “emerging technology,” one that appears to have great potential but has not yet achieved such potential commer-cially. As such, it will not be studied in this book. Nevertheless, considerable material on GaAs devices and circuits, including digital circuits, can be found on the CD accompanying this book and on the book’s website.
13.1.11 Styles for Digital-System Design The conventional approach to designing digital systems consists of assembling the system using standard IC packages of various levels of complexity (and hence integration). Many systems have been built this way using, for example, TTL SSI and MSI packages. The advent of VLSI, in addition to providing the system designer with more powerful off-the-shelf components such as microprocessors and memory chips, has made possible alternative design styles. One such alternative is to opt for implementing part or all of the system using one or more custom VLSI chips. However, custom IC design is usually economically justi-fied only when the production volume is large (greater than about 100,000 parts).
An intermediate approach, known as semicustom design, utilizes gate-array chips. These are integrated circuits containing 100,000 or more unconnected logic gates. Their intercon-nection can be achieved by a final metallization step (performed at the IC fabrication facility) according to a pattern specified by the user to implement the user’s particular functional need.
A more recently available type of gate array, known as a field-programmable gate array (FPGA), can, as its name indicates, be programmed directly by the user. FPGAs provide a very convenient means for the digital-system designer to implement complex logic functions in VLSI form without having to incur either the cost or the “turnaround time” inherent in custom and, to a lesser extent, in semicustom IC design. 13.1.12 Design Abstraction and Computer Aids The design of very complex digital systems, whether on a single IC chip or using off-the-shelf components, is made possible by the use of different levels of design abstraction, and the use of a variety of computer aids. To appreciate the concept of design abstraction, con-sider the process of designing a digital system using off-the-shelf packages of logic gates.
The designer consults data sheets (in data books or on websites) to determine the input and output characteristics of the gates, their fan-in and fan-out limitations, and so on. In connecting the gates, the designer needs to adhere to a set of rules specified by the manu-facturer in the data sheets. The designer does not need to consider, in a direct way, the cir-cuit inside the gate package. In effect, the circuit has been abstracted in the form of a functional block that can be used as a component. This greatly simplifies system design.
The digital-IC designer follows a similar process. Circuit blocks are designed, 13.2 The CMOS Inverter 1089 characterized, and stored in a library as standard cells. These cells can then be used by the IC designer to assemble a larger subsystem (e.g., an adder or a multiplier), which in turn is characterized and stored as a functional block to be used in the design of an even larger system (e.g., an entire processor).
At every level of design abstraction, the need arises for simulation and other computer programs that help make the design process as automated as possible. Whereas SPICE is employed in circuit simulation, other software tools are utilized at other levels and in other phases of the design process. Although digital-system design and design automation are out-side the scope of this book, it is important that the reader appreciate the role of design abstraction and computer aids in digital design. They are what make it humanly possible to design a billion-transistor digital IC. Unfortunately, analog IC design does not lend itself to the same level of abstraction and automation. Each analog IC to a large extent has to be “handcrafted.” As a result, the complexity and density of analog ICs remain much below what is possible in a digital IC.
Whatever approach or style is adopted in digital design, some familiarity with the various digital-circuit technologies and design techniques is essential. This chapter and the next two aim to provide such a background.
13.2 The CMOS Inverter In this section we study the inverter circuit of the most widely used digital IC technology: CMOS. The basic CMOS inverter is shown in Fig. 13.17. It utilizes two MOSFETs: one, QN, with an n channel and the other, QP, with a p channel. The body of each device is connected to its source, and thus no body effect arises. As will be seen shortly, the CMOS circuit real-izes the conceptual inverter implementation studied in the previous section (Fig. 13.8), where a pair of switches are operated in a complementary fashion by the input voltage vI.
13.2.1 Circuit Operation We first consider the two extreme cases: when vI is at logic-0 level, which is 0 V; and when vI is at logic-1 level, which is VDD volts. In both cases, for ease of exposition we shall con-sider the n-channel device QN to be the driving transistor and the p-channel device QP to be Figure 13.17 The CMOS inverter.
1090 Chapter 13 CMOS Digital Logic Circuits the load. However, since the circuit is symmetric, this assumption is obviously arbitrary, and the reverse would lead to identical results.
Figure 13.18 illustrates the case when vI = VDD, showing the iD−vDS characteristic curve for QN with vGSN = VDD. (Note that iD = i and vDSN = vO.) Superimposed on the QN characteristic curve is the load curve, which is the iD−vSD curve of QP for the case vSGP = 0 V. Since , the load curve will be a horizontal straight line at zero current level. The operat-ing point will be at the intersection of the two curves, where we note that the output voltage is zero and the current through the two devices is also zero. This means that the power dissi-pation in the circuit is zero. Note, however, that although QN is operating at zero current and zero drain-source voltage (i.e., at the origin of the iD−vDS plane), the operating point is on a steep segment of the iD−vDS characteristic curve. Thus QN provides a low-resistance path between the output terminal and ground, with the resistance obtained using Eq. (5.13b) as (13.45) Figure 13.18(c) shows the equivalent circuit of the inverter when the input is high. This cir-cuit confirms that and that the power dissipation in the inverter is zero.
The other extreme case, when vI = 0 V, is illustrated in Fig. 13.19. In this case QN is oper-ating at vGSN = 0; hence its iD−vDS characteristic is a horizontal straight line at zero current level. The load curve is the iD−vSD characteristic of the p-channel device with vSGP = VDD. As shown, at the operating point the output voltage is equal to VDD, and the current in the two devices is still zero. Thus the power dissipation in the circuit is zero in both extreme states.
Figure 13.19(c) shows the equivalent circuit of the inverter when the input is low. Here we see that QP provides a low-resistance path between the output terminal and the dc supply VDD, with the resistance given by (13.46) (a) (b) VDD rDSN vO0 (c) Figure 13.18 Operation of the CMOS inverter when vI is high: (a) circuit with vI = VDD (logic-1 level, or VOH); (b) graphical construction to determine the operating point; (c) equivalent circuit.
vSGP Vt < rDSN 1 kn ′ W L -----⎝ ⎠ ⎛ ⎞ n VDD Vtn – ( ) = vO VOL ≡ 0 V = rDSP 1 kp ′ W L -----⎝ ⎠ ⎛ ⎞ p VDD Vtp – ( ) = 13.2 The CMOS Inverter 1091 The equivalent circuit confirms that in this case and that the power dissipa-tion in the inverter is zero.
It should be noted, however, that in spite of the fact that the quiescent current is zero, the load-driving capability of the CMOS inverter is high. For instance, with the input high, as in the circuit of Fig. 13.18, transistor QN can sink a relatively large load current. This current can quickly discharge the load capacitance, as will be seen shortly. Because of its action in sinking load current and thus pulling the output voltage down toward ground, transistor QN is known as the pull-down device. Similarly, with the input low, as in the circuit of Fig. 13.19, transistor QP can source a relatively large load current. This current can quickly charge up a load capacitance, thus pulling the output voltage up toward VDD. Hence, QP is known as the pull-up device. The reader will recall that we used this terminology in con-nection with the conceptual inverter circuit of Fig. 13.8.
From the above, we conclude that the basic CMOS logic inverter behaves as an ideal inverter. In summary: 1. The output voltage levels are 0 and VDD, and thus the signal swing is the maximum pos-sible. This, coupled with the fact that the inverter can be designed to provide a symmet-rical voltage-transfer characteristic, results in wide noise margins.
2. The static power dissipation in the inverter is zero (neglecting the dissipation due to leak-age currents) in both of its states. This is because no dc path exists between the power supply and ground in either state.
3. A low-resistance path exists between the output terminal and ground (in the low-out-put state) or VDD (in the high-output state). These low-resistance paths ensure that the output voltage is 0 or VDD independent of the exact values of the W/L ratios or other device parameters. Furthermore, the low output resistance makes the inverter less sensi-tive to the effects of noise and other disturbances.
4. The active pull-up and pull-down devices provide the inverter with high output-driv-ing capability in both directions. As will be seen, this speeds up the operation considerably.
Figure 13.19 Operation of the CMOS inverter when vI is low: (a) circuit with vI = 0 V (logic-0 level, or VOL); (b) graphical construction to determine the operating point; (c) equivalent circuit.
(b) (a) VDD rDSP vO VDD (c) vO VOH ≡ = VDD 1092 Chapter 13 CMOS Digital Logic Circuits 5. The input resistance of the inverter is infinite (because IG = 0). Thus the inverter can drive an arbitrarily large number of similar inverters with no loss in signal level. Of course, each additional inverter increases the load capacitance on the driving inverter and slows down the operation. Shortly, we will consider the inverter switching times.
13.2.2 The Voltage-Transfer Characteristic The complete voltage-transfer characteristic (VTC) of the CMOS inverter can be obtained by repeating the graphical procedure, used above in the two extreme cases, for all inter-mediate values of vI. In the following, we shall calculate the critical points of the resulting voltage-transfer curve. For this we need the i−v relationships of QN and QP. For QN, (13.47) and (13.48) For QP, (13.49) and (13.50) The CMOS inverter is usually designed to have . Also, although this is not always the case, we shall assume that QN and QP are matched; that is, . It should be noted that since μp is 0.25 to 0.5 times the value of μn, to make of the two devices equal, the width of the p-channel device is made two to four times that of the n-channel device. More specifically, the two devices are designed to have equal lengths, with widths related by (13.51) This will result in , and the inverter will have a symmetric transfer characteristic and equal current-driving capability in both directions (pull-up and pull-down).
With QN and QP matched, the CMOS inverter has the voltage transfer characteristic shown in Fig. 13.20. As indicated, the transfer characteristic has five distinct segments cor-responding to different combinations of modes of operation of QN and QP. The vertical segment BC is obtained when both QN and QP are operating in the saturation region.
Because we are neglecting the finite output resistance in saturation, that is, assuming , the inverter gain in this region is infinite. From symmetry, this vertical segment occurs at and is bounded by , at which value QP enters the triode region and , at which value QN enters the triode region.
iDN kn ′ W L -----⎝ ⎠ ⎛ ⎞ n vI Vtn – ( )vO 1 2 ---vO 2 – = for vO vI Vtn – ≤ iDN 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ n vI Vtn – ( ) 2 for vO vI Vtn – ≥ = iDP kp ′ W L -----⎝ ⎠ ⎛ ⎞ p VDD vI Vtp – – ( ) VDD vO – ( ) 1 2 --- VDD vO – ( ) 2 – = for vO v ≥ I Vtp + iDP 1 2 ---kp ′ W L -----⎝ ⎠ ⎛ ⎞ p VDD vI Vtp – – ( ) 2 for vO vI Vtp + ≤ = V tn Vtp Vt = = kn ′ W L ⁄ ( )n = kp ′ W L ⁄ ( )p k′ W L ⁄ ( ) Wp Wn -------μn μp -----= kn ′ W L ⁄ ( )n = kp ′ W L ⁄ ( )p λN λP 0 = = vI VDD 2 ⁄ = vO B ( ) VDD 2 ⁄ Vt + = vO C ( ) VDD 2 Vt – ⁄ = 13.2 The CMOS Inverter 1093 The reader will recall from Section 13.1.3 that in addition to VOL and VOH, two other points on the transfer curve determine the noise margins of the inverter. These are the maxi-mum permitted logic-0 or “low” level at the input, VIL, and the minimum permitted logic-1 or “high” level at the input, VIH. These are formally defined as the two points on the transfer curve at which the incremental gain is unity (i.e., the slope is −1 V/V).
To determine VIH, we note that QN is in the triode region, and thus its current is given by Eq. (13.47), while QP is in saturation and its current is given by Eq. (13.50). Equating iDN and iDP, and assuming matched devices, gives (13.52) Differentiating both sides relative to vI results in in which we substitute vI = VIH and to obtain (13.53) Figure 13.20 The voltage-transfer characteristic of the CMOS inverter when QN and QP are matched.
M vI Vt – ( )vO 1 2 --- vO 2 1 2 --- VDD vI Vt – – ( ) 2 = – vI Vt – ( ) dvO dvI --------vO vO dvO dvI --------VDD vI Vt – – ( ) – = – + dvO dvI ⁄ 1 – = vO VIH VDD 2 ---------– = 1094 Chapter 13 CMOS Digital Logic Circuits Substituting vI = VIH and for vO from Eq. (13.53) in Eq. (13.52) gives (13.54) VIL can be determined in a manner similar to that used to find VIH. Alternatively, we can use the symmetry relationship together with VIH from Eq. (13.54) to obtain (13.55) The noise margins can now be determined as follows: (13.56) (13.57) As expected, the symmetry of the voltage-transfer characteristic results in equal noise mar-gins. Of course, if QN and QP are not matched, the voltage-transfer characteristic will no longer be symmetric, and the noise margins will not be equal.
13.2.3 The Situation When QN and QP Are Not Matched In the above we assumed that and are matched; that is, in addition to , the transconductance parameters and are made equal by selecting according to Eq. (13.51). The result is a symmetrical VTC that switches at the midpoint of the supply; that is, The symmetry, as we have seen, equalizes and maximizes the noise margins.
The price paid for obtaining a perfectly symmetric VTC is that the width of the p-channel device can be three to four times as large as that of the n-channel device. This can result in a relatively large silicon area which, besides being wasteful of silicon real estate, can also result in increased device capacitances and a corresponding increase in the propagation delay of the inverter. It is useful, therefore, to inquire into the effect of not matching and Toward that end we derive an expression for the switching voltage as follows.
Since at M, both and operate in saturation, their currents are given by Eqs.
(13.48) and (13.50). Substituting and equating the two currents results in (13.58) VIH 1 8 --- 5VDD 2Vt – ( ) = VIH VDD 2 ---------VDD 2 ---------VIL – = – VIL 1 8 --- 3VDD 2Vt + ( ) = NMH VOH VIH – = VDD 1 8 --- 5VDD 2Vt – ( ) – = 1 8 --- 3VDD 2Vt + ( ) = NML VIL VOL – = 1 8 --- 3VDD 2Vt + ( ) 0 – = 1 8 --- 3VDD 2Vt + ( ) = QN QP Vtn Vtp = kn kp Wp Wn ⁄ VM VDD 2.
⁄ = QN QP.
VM QN QP vI vO VM, = = VM r VDD Vtp – ( ) Vtn + r 1 + -----------------------------------------------= 13.2 The CMOS Inverter 1095 where (13.59) where we have assumed that and have the same channel length L, which is usually the case with L equal to the minimum available for the given process technology. Note that the matched case corresponds to r = 1. For , and r = 1, Eq. (13.58) yields , as expected. For a given process, that is, given values for , , and , one can plot versus the matching parameter r. Such a plot, for a 0.18-μm process, is shown in Fig. 13.21. We make the following two observations: 1. increases with r. Thus, making shifts toward . Conversely, making shifts toward 0.
2. is not a strong function of r. For the particular case shown, lowering r by a factor of 2 (from 1 to 0.5), reduces by only 0.13 V.
Observation 2 implies that if one is willing to tolerate a small reduction in substantial savings in silicon area can be obtained. This point is illustrated in Example 13.4. Figure 13.21 Variation of the inverter switching voltage, VM, with the parameter .
1.2 0.8 1.0 0.6 0.4 0.2 0.5 1.0 1.5 2.0 r VM (V) VDD 1.8 V Vtn Vtp 0.5 V r kp kn ⁄ = r kp kn ----μpWp μnWn -------------= = QN QP Vtp Vtn = VM VDD 2 ⁄ = VDD Vtn Vtp VM VM kp kn > VM VDD kp kn < VM VM VM NML, Consider a CMOS inverter fabricated in a 0.18-μm process for which and In addition, and have L = 0.18 μm and (a) Find that results in What is the silicon area utilized by the inverter in this case?
(b) For the matched case in (a), find the values of and the noise margins and For what value of results? This can be considered the worst-case value of Similarly, for find that is the worst-case value of . Now, use these worst-case val-ues to determine more conservative values for the noise margins.
(c) For the matched case in (a), find the output resistance of the inverter in each of its two states. VDD 1.8 V, = Vtn Vtp 0.5 V, = = μn 4μp, = μnCox 300 μA V2.
⁄ = QN QP W L ⁄ ( )n 1.5.
= Wp VM VDD 2 0.9 V = ⁄ .
= VOH, VOL, VIH, VIL, NML NMH.
vI VIH, = vO VOL.
vI VIL, = vO VOH Example 13.4 1096 Chapter 13 CMOS Digital Logic Circuits Example 13.4 continued (d) If , what is the inverter gain at If a straight line is drawn through the point with a slope equal to the gain, at what values of does it intercept the hori-zontal lines and ? Use these intercepts to estimate the width of the transition re-gion of the VTC.
(e) If , what value of results? What do you estimate the reduction of (relative to the matched case) to be? What is the percentage savings in silicon area (relative to the matched case)?
(f) Repeat (e) for the case This case, which is frequently used in industry, can be considered to be a compromise between the minimum-area case in (e) and the matched case. Solution (a) To obtain , we select according to Eq. (13.51), Since . Thus, For this design, the silicon area is (b) To obtain we use Eq. (13.54), To obtain we use Eq. (13.55), We can now compute the noise margins as As expected, and their value is very close to the optimum value of For we can obtain the corresponding value of by substituting in Eq. (13.53), Thus, the worst-case value of that is, is 0.1 V, and the noise margin reduces to From symmetry, we can obtain the value of corresponding to as λn λp 0.2 V 1 – = = vI VM.
= vI vO VM = = vI vO 0 = vO VDD = Wp Wn = VM NML Wp 2Wn.
= VM VDD 2 0.9 V = ⁄ = Wp Wp Wn -------μn μp -----4 = = Wn L ⁄ 1.5, = Wn 1.5 0.18 0.27 μm = × = Wp 4 0.27 1.08 μm = × = A WnL WpL L Wn Wp + ( ) = + = 0.18 0.27 1.08 + ( ) 0.243 μm2 = = VOH VDD 1.8 V = = VOL 0 V = VIH VIH 1 8 --- 5VDD 2Vt – ( ) 1 8 --- 5 1.8 2 0.5 × – × ( ) 1 V = = = VIL VIL 1 8 --- 3VDD 2Vt + ( ) 1 8 --- 3 1.8 2 0.5 × + × ( ) 0.8 V = = = NMH VOH VIH 1.8 1.0 0.8 V = – = – = NML VIL VOL 0.8 0 0.8 V = – = – = NMH NML, = VDD 2 0.9 V.
= ⁄ vI VIH 1 V, = = vO vO VIH VDD 2 ----------1 1.8 2 -------0.1 V = – = – = VOL, VOLmax, NML NML VIL VOLmax 0.8 0.1 0.7 V = – = – = vO vI VIL = vO VDD 0.1 1.7 V = – = 13.2 The CMOS Inverter 1097 Thus the worst-case value of , that is, , is 1.7 V, and the noise margin reduces to Note that the reduction in the noise margins is slight.
(c) The output resistance of the inverter in the low-output state is Since and are matched, the output resistance in the high-output state will be equal, that is, (d) If the inverter is biased to operate at , then each of and will be oper-ating at an overdrive voltage and will be conducting equal dc cur-rents of Thus, and will have equal transconductances: Transistors and will have equal output resistances , We can now compute the voltage gain at M as When the straight line at M of slope V/V is extrapolated, it intersects the line at and the line at Thus the width of the transition region can be considered to be (e) For , the parameter r can be found from Eq. (13.59), The corresponding value of can be determined from Eq. (13.58) as VOH VOHmin NMH NMH VOHmin VIH 1.7 1 0.7 V = – = – = rDSN 1 μnCox W ⁄ L ( )n VDD Vtn – ( ) ----------------------------------------------------------------= 1 300 10 6 – 1.5 1.8 0.5 – ( ) × × -----------------------------------------------------------------1.71 kΩ = = QN QP rDSP rDSN 1.71 kΩ = = vI vO VM 0.9 V = = = QN QP VOV VM Vt 0.9 0.5 0.4 V = – = – = ID ID 1 2 ---μnCox W L -----⎝ ⎠ ⎛ ⎞ N VOV 2 = 1 2 ---300 1.5 0.42 × × × = 36 μA = QN QP gmn gmp 2ID VOV ---------2 36 × 0.4 ---------------0.18 mA/V2 = = = = QN QP ro ron rop VA ID ---------1 λ ID -----------1 0.2 36 × -------------------139 kΩ = = = = = Av gmn gmp + ( ) ron rop || ( ) – = 0.18 0.18 + ( ) 139 139 || ( ) 25 V/V – = – = 25 – vO 0 = 0.9 0.9 ⁄ 25 + [ ] 0.936 V = vO VDD = 0.9 0.9 ⁄ – 25 ( ) 0.864 V.
= 0.936 0.864 – ( ) 0.072 V.
= Wp Wn = r μpWp μnWn -------------1 4 ---1 × 0.5 = = = VM VM 0.5 1.8 0.5 – ( ) 0.5 + 0.5 1 + -----------------------------------------------0.77 V = = 1098 Chapter 13 CMOS Digital Logic Circuits 13.3 Dynamic Operation of the CMOS Inverter As explained in Section 13.1.7, the speed of operation of a digital system (e.g., a computer) is determined by the propagation delay of the logic gates used to construct the system. Since the inverter is the basic logic gate of any digital IC technology, the propagation delay of the Example 13.4 continued Thus shifts by only Without recalculating we can estimate the reduction in to be approximately equal to the shift in that is, becomes The silicon area for this design can be computed as follows: This represents a 60% reduction from the matched case!
(f) For Thus, relative to the matched case, the shift in is only We estimate that will decrease from 0.8 V by the same amount; thus becomes 0.73 V. In this case, the silicon area required is which represents a 40% reduction relative to the matched case!
VM 0.13 V.
– VIL NML VM, NML 0.8 0.13 – 0.67 V.
= A L Wn Wp + ( ) 0.18 0.27 0.27 + ( ) = = 0.0972 μm2 = Wp 2Wn, = r 1 4 ---2 × 1 2 -------0.707 = = = VM 0.707 1.8 0.5 – ( ) 0.5 + 0.707 1 + -----------------------------------------------------0.83 V = = VM 0.07 V.
– NML NML A L Wn Wp + ( ) 0.18 0.27 0.54 + ( ) = = 0.146 μm2 = 13.12 Consider a CMOS inverter fabricated in a 0.13-μm process for which , and In addition, and have L = 0.13 μm and .
(a) Find that results in (b) For the matched case in (a), find the values of and (c) For the inverter in (a), find the output resistance in each of its two states.
(d) For a minimum-size inverter for which , find .
Ans. (a) 0.52 μm; (b) 1.2 V, 0 V, 0.65 V, 0.55 V, 0.55 V, 0.55 V, (c) 2.9 k , 2.9 k ; (d) 0.53 V D13.13 A CMOS inverter utilizes and .
Find and so that and so that for the inverter can sink a current of 0.2 mA with the output voltage not exceeding 0.2 V.
Ans. VDD 1.2 V, = Vtn Vtp 0.4 V = – = μn μp ⁄ 4, = μnCox 430 μA V2.
⁄ = QN QP W L ⁄ ( )n 1.0 = Wp VM 0.6 V.
= VOH, VOL, VIH, VIL, NMH, NML.
W L ⁄ ( )p W L ⁄ ( )n 1.0 = = VM Ω Ω VDD 5 V, = Vtn Vtp 1 V, = = μnCox = 2μpCox = 50 μA V2 ⁄ W L ⁄ ( )n W L ⁄ ( )p VM 2.5 V = vI VDD, = W L ⁄ ( )n 5; W L ⁄ ( )p 10 EXERCISES 13.3 Dynamic Operation of the CMOS Inverter 1099 inverter is a fundamental parameter in characterizing the technology. In the following, we analyze the switching operation of the CMOS inverter to determine its propagation delay.
We shall do this by utilizing a two-step process.
1. Replace all the capacitances in the circuit: that is, the various capacitances associated with and the capacitance of the wire that connects the output of the inverter to other circuits, and the input capacitance of the logic gates the inverter drives, by a single equivalent capacitance C connected between the output node of the inverter and ground.
2. Analyze the resulting capacitively loaded inverter to determine its and and hence We shall study these two separable steps in reverse order. Thus, in Section 13.3.1 we show how the propagation delay can be determined. Then, in Section 13.3.2, we show how to cal-culate the value of C.
13.3.1 Determining the Propagation Delay Figure 13.22(a) shows a CMOS inverter with a capacitance C connected between its out-put node and ground. To determine the propagation delays and we apply to the input an ideal pulse, that is, one with zero rise and fall times, as shown in Fig. 13.22(b).
Since the circuit is symmetric, the analyses to determine the two propagation delays will be similar. Therefore, we will derive in detail and extrapolate the result to determine Just prior to the leading edge of the input pulse (i.e., at t = 0), the output voltage is equal to and capacitor C is charged to this voltage. At t = 0, rises to causing to turn off and to turn on. From then on, the circuit is equivalent to that shown in Fig. 13.22(c), with the initial value of Thus, at t = 0+, will operate in the sat-uration region and will supply a relatively large current to begin the process of discharging C. Figure 13.22(d) shows the trajectory of the operating point of as C is discharged.
Here we are interested in the interval during which reduces from to .
Correspondingly, the operating point of moves from E to M. For a portion of this time, corresponding to the segment EF of the trajectory, operates in saturation. Then at F, , and enters the triode region.
A simple approach for determining consists of first calculating the average value of the current supplied by over the segment EM. Then, we use this average value of the discharge current to determine by means of the charge balance equation resulting in (13.60) The value of can be found as follows: (13.61) QN QP, tPLH tPHL, tP.
tPHL tPLH, tPHL tPLH.
VDD vI VDD, QP QN vO VDD.
= QN QN tPHL vO VDD VDD 2 ⁄ QN QN vO VDD Vt – = QN tPHL QN tPHL Iav tPHL C VDD VDD 2 ⁄ ( ) – [ ] = tPHL CVDD 2Iav --------------= Iav Iav 1 2 --- iDN E ( ) iDN M ( ) + [ ] = 1100 Chapter 13 CMOS Digital Logic Circuits where (13.62) and (13.63) Note that we have assumed Combining Eqs. (13.60) to (13.63) provides (13.64) Figure 13.22 Dynamic operation of a capacitively loaded CMOS inverter: (a) circuit; (b) input and out-put waveforms; (c) equivalent circuit during the capacitor discharge; (d) trajectory of the operating point as the input goes high and C discharges through QN.
(a) t PLH (c) (d) iDN E ( ) 1 2 ---kn ′ W L -----⎝ ⎠ ⎛ ⎞ n VDD Vtn – ( )2 = iDN M ( ) kn ′ W L -----⎝ ⎠ ⎛ ⎞ n VDD Vtn – ( ) VDD 2 ----------⎝ ⎠ ⎛ ⎞ 1 2 --- VDD 2 ----------⎝ ⎠ ⎛ ⎞ 2 – = λn 0.
= tPHL αnC kn ′ W L ⁄ ( )nVDD -----------------------------------= 13.3 Dynamic Operation of the CMOS Inverter 1101 where is a factor determined by the relative values of and (13.65) The value of falls in the range of 1 to 2.
An expression for the low-to-high inverter delay, tPLH, can be written by analogy to the tPHL expression in Eq. (13.64), (13.66) where (13.67) Finally, the propagation delay tP can be found as the average of tPHL and tPLH, Examination of the formulas in Eqs. (13.64) to (13.67) enables us to make a number of use-ful observations: 1. As expected, the two components of tP can be equalized by selecting the (W/L) ratios to equalize kn and kp, that is, by matching QN and QP.
2. Since tP is proportional to C, the designer should strive to reduce C. This is achieved by using the minimum possible channel length and by minimizing wiring and other parasitic capacitances. Careful layout of the chip can result in significant reduction in such capacitances.
3. Using a process technology with larger transconductance parameter k′ can result in shorter propagation delays. Keep in mind, however, that for such processes Cox is increased, and thus the value of C increases at the same time (more on this later).
4. Using larger W/L ratios can result in a reduction in tP. Care, however, should be exercised here also, since increasing the size of the devices increases the value of C, and thus the expected reduction in tP might not materialize. Reducing tP by increasing W/L, how-ever, is an effective strategy when C is dominated by components not directly related to the size of the driving device (such as wiring or fan-out devices).
5. A larger supply voltage VDD results in a lower tP. However, VDD is determined by the pro-cess technology and thus is often not under the control of the designer. Furthermore, modern process technologies in which device sizes are reduced require lower VDD (see Table 7.A.1). A motivating factor for lowering VDD is the need to keep the dynamic power dissipation at acceptable levels, especially in very-high-density chips. We will have more to say on this point shortly.
These observations clearly illustrate the conflicting requirements and the trade-offs avail-able in the design of a CMOS digital integrated circuit (and indeed in any engineering design problem).
An Alternative Approach The formulas derived above for and underestimate the delay values for inverters implemented in deep-submicron technologies. This arises be-cause of the velocity saturation effect, which we shall discuss briefly in Section 13.5. There α n Vt VDD; α n 2 7 4 ---3Vtn VDD ----------– Vtn VDD ----------⎝ ⎠ ⎛ ⎞ 2 + = α n tPLH α p k′ p W L -----⎝ ⎠ ⎛ ⎞ p VDD -----------------------------= αp 2 7 4 ---3 Vtp VDD -------------– Vtp VDD ---------2 + = tP 1 2 --- tPHL tPLH + ( ) = tPHL tPLH 1102 Chapter 13 CMOS Digital Logic Circuits we will see that velocity saturation results in lower MOSFET currents in the saturation region, and hence in increased delay times. To deal with this problem, we present a very simple alter-native approach to estimating the inverter propagation delay.
Figure 13.23 illustrates the alternative approach. During the discharge delay is replaced by an equivalent resistance Similarly, during the charging delay is replaced by an equivalent resistance It is easy to show that (13.68) and (13.69) Empirical values have been found for and (13.70) (13.71) Furthermore, it has been found that these values apply for a number of CMOS fabrication processes including 0.25 μm, 0.18 μm, and 0.13 μm (see Hodges et al., 2004).
Figure 13.23 Equivalent circuits for determining the propagation delays (a) tPHL and (b) tPLH of the inverter.
iDN vO vI vO t 0 0 VDD QN C VDD RN C VDD 2 0 tPHL t (a) vO vI VDD QP C VDD VDD 2 0 0 tPLH t t 0 0 VDD (b) vO VDD RP C tPHL, QN RN.
tPLH, QP RP.
tPHL 0.69RNC = tPLH 0.69RPC = RN RP, RN 12.5 W L ⁄ ( )n ------------------- kΩ = RP 30 W L ⁄ ( )p ------------------- kΩ = 13.3 Dynamic Operation of the CMOS Inverter 1103 For the 0.25-μm process characterized by , , find and for an inverter for which and , and for C = 10 fF. Use both the approach based on average currents and that based on equivalent resistances, and compare the results obtained. If to save on power dissipation the inverter is operated at , by what factor does change?
Solution (a) Using the average current approach, we determine from Eq. (13.65), and using Eq. (13.64), Since , and we can determine from Eq. (13.66) as The propagation delay can now be found as (b) Using the equivalent resistance approach, we first find from Eq. (13.70) as and then use Eq. (13.68) to determine Similarly we use Eq. (13.71) to determine and Eq. (13.69) to determine Thus, while the value obtained for is higher than that found using average currents, the value for is about the same. Finally, can be found as which a little higher than the value found using average currents.
VDD 2.5 V, = Vtn Vtp 0.5 V = – = kn ′ 3.5kp ′ 115 μA V2 ⁄ = = tPLH, tPHL, tP W L ⁄ ( )n 1.5 = W L ⁄ ( )p 3 = VDD 2.0 V = tP α n 2 7 4 ---3 0.5 × 2.5 ----------------– 0.5 2.5 -------⎝ ⎠ ⎛ ⎞ 2 + ------------------------------------------------1.7 = = tPHL 1.7 10 10 15 – × × 110 10 6 – 1.5 2.5 × × × -----------------------------------------------------41.2 ps = = Vtp Vtn = α p α n 1.7 = = tPLH tPLH 1.7 10 10 15 – × × 110 3.5 ⁄ ( ) 10 6 – 3 2.5 × × × -----------------------------------------------------------------72.1 ps = = tP 1 2 --- tPHL tPLH + ( ) = 1 2 --- 41.2 72.1 + ( ) 56.7 ps = = RN RN 12.5 1.5 ----------8.33 kΩ = = tPHL, tPHL 0.69 8.33 103 10 10 15 – × × × × 57.5 ps = = RP, RP 30 3 ------10 kΩ = = tPLH, tPLH 0.69 10 103 10 10 15 – × × 69 ps = × × = tPHL tPLH tP tP 1 2 --- 57.5 69 + ( ) 63.2 ps = = Example 13.5 1104 Chapter 13 CMOS Digital Logic Circuits Before leaving the subject of propagation delay, we should emphasize that hand analysis using the simple formulas above should not be expected to yield precise results. Rather, its value is in obtaining design insight. Precise results can always be obtained using SPICE and Multisim simulations (see examples in Appendix B and the extensive material on the CD and the website). However, it is never a good idea to use simulation if one does not know beforehand approximate values of the expected results.
13.3.2 Determining the Equivalent Load Capacitance C Having determined the propagation delay of the CMOS inverter in terms of the equivalent load capacitance C, it now remains to determine the value of C. For this purpose, a thorough understanding of the various capacitances in a MOS transistor is essential, and we urge the reader to review the material in Section 9.2.1. Example 13.5 continued To find the change in propagation delays obtained when the inverter is operated at we have to use the method of average currents. (The dependence on the power-supply voltage is absorbed in the empirical values of and RP.) Using Eq. (13.65), we write The value of can now be found by using Eq. (13.64): Similarly, the value of can be substituted in Eq. (13.66) to obtain and can be calculated as Thus, as expected, reducing has resulted in increased propagation delay.
VDD 2.0 V, = RN α n 2 7 4 ---3 0.5 × 2 ----------------– 0.5 2 -------⎝ ⎠ ⎛ ⎞ 2 + ------------------------------------------------2.1 = = tPHL tPHL 2.1 10 10 15 – × × 110 10 6 – 1.5 2 × × × ------------------------------------------------63.6 ps = = α p α n 2.1 = = tPLH 2.1 10 10 15 – × × 110 3.5 ⁄ ( ) 10 6 – 3 2 × × × ------------------------------------------------------------111.4 ps = = tP tP 1 2 --- 63.6 111.4 + ( ) 87.5 ps = = VDD 13.14 For a CMOS inverter fabricated in a 0.18-μm process with , and having and find and when the equivalent load capacitance C = 10 fF. Use the method of average currents. Ans. 24.7 ps; 49.4 ps; 37 ps D13.15 For a CMOS inverter fabricated in a 0.13-μm process, use the equivalent-resistances approach to determine and so that when the effective load capaci-tance C = 20 fF.
Ans. 3.5; 8.3 VDD 1.8 V, = Vtn Vtp 0.5 V = – = kn ′ 4kp ′ 300 μA V2 ⁄ = = W L ⁄ ( )n 1.5 = W L ⁄ ( )p 3, = tPHL, tPLH, tP W L ⁄ ( )n W L ⁄ ( )p tPLH tPHL 50 ps = = EXERCISES 13.3 Dynamic Operation of the CMOS Inverter 1105 Figure 13.24 shows the circuit for determining the propagation delay of the CMOS inverter formed by and Note that we are showing the inverter driving a similar inverter formed by transistors and This reflects a practical situation and will help us explain how to determine the contribution of a driven inverter to the equivalent capacitance C at the output of the inverter under study (that formed by and ).
Indicated in Fig. 13.24 are the various transistor capacitances that connect to the output node of the inverter. Also shown is the wiring capacitance , which represents the capacitance of the wire or interconnect that connects the output of the inverter to the input of the inverter. Interconnect capacitances have become increasingly dominant as the technology has scaled down. In fact, some digital IC designers hold the view that interconnect poses a greater limitation on the speed of operation than the transis-tors themselves. We will discuss this topic briefly in Section 13.5.
A glance at the circuit in Fig. 13.24 should be sufficient to indicate that a pencil-and-paper analysis is virtually impossible. That, of course, is the reason we opted for the simpli-fication of replacing all these capacitances with an equivalent capacitance C. Before we con-sider the determination of C, it is useful to observe that during tPLH or tPHL, the output of the first inverter changes from 0 to or from VDD to , respectively. It follows that the second inverter remains in the same state during each of our analysis intervals. This obser-vation will have an important bearing on our estimation of the equivalent input capacitance of the second inverter. Let’s now consider the contribution of each of the capacitances in Fig. 13.24 to the value of the equivalent load capacitance C: 1. The gate–drain overlap capacitance of Q1, Cgd1, can be replaced by an equivalent capac-itance between the output node and ground of 2Cgd1. The factor 2 arises because of the Miller effect (Section 9.4.4). Specifically, refer to Fig. 13.25 and note that as vI goes high and vO goes low by the same amount, the change in voltage across Cgd1 is twice that amount. Thus the output node sees in effect twice the value of Cgd1. The same applies for the gate–drain overlap capacitance of Q2, Cgd2, which can be replaced by a capaci-tance 2Cgd2 between the output node and ground.
Figure 13.24 Circuit for analyzing the propagation delay of the inverter formed by Q1 and Q2, which is driving a similar inverter formed by Q3 and Q4.
Q1 Q2.
Q3 Q4.
Q1 Q2 Q1 Q2 – Cw Q1 Q2 – Q3 Q4 – Q2 Q1 t 0 VDD vI vO Q4 Q3 VDD Cgd2 Cg3 Cg4 Cdb2 Cw Cdb1 Cgd1 VDD V DD 2 ⁄ V DD 2 ⁄ 1106 Chapter 13 CMOS Digital Logic Circuits 2. Each of the drain–body capacitances Cdb1 and Cdb2 has a terminal at a constant voltage.
Thus for the purpose of our analysis here, Cdb1 and Cdb2 can be replaced with equal capacitances between the output node and ground. Note, however, that the formulas given in Section 9.2.1 for calculating Cdb1 and Cdb2 are small-signal relationships, whereas the analysis here is obviously a large-signal one. A technique has been developed for finding equivalent large-signal values for Cdb1 and Cdb2 (see Hodges et al., (2004) and Rabaey et al., (2003)).
3. Since the second inverter does not switch states, we will assume that the input capaci-tances of Q3 and Q4 remain approximately constant and equal to the total gate capaci-tance That is, the input capacitance of the load inverter will be (13.72) 4. The last component of C is the wiring capacitance Cw, which simply adds to the value of C.
Thus, the total value of C is given by (13.73) Figure 13.25 The Miller multiplication of the feedback capacitance Cgd1.
WLCox Cgsov Cgdov + + ( ).
Cg3 Cg4 + WL ( )3Cox WL ( )4Cox Cgsov3 C gdov3 C gsov4 C gdov4 + + + + + = C = 2Cgd1 2Cgd2 Cdb1 Cdb2 Cg3 Cg4 Cw + + + + + + V V V V 2 Cgd1 Cgd1 2 Cgd1 Consider a CMOS inverter fabricated in a 0.25-μm process for which Cox = 6 μnCox = 115 μpCox = 30 Vtn = −Vtp = 0.5 V, and VDD = 2.5 V. The ratio of QN is 0.375 μm, and that for QP is 1.125 μm. The gate–source and gate–drain overlap capacitances are specified to be 0.3 of gate width. Further, the effective (large-signal) values of drain–body capacitances are = 1 fF and = 1 fF. The wiring capacitance Cw = 0.2 fF. Find tPHL, tPLH, and tP when the inverter is driv-ing an identical inverter.
Solution First, we determine the value of the equivalent capacitance C using Eqs. (13.72) and (13.73), where fF/μm2, μA/V2, μA/V2, W L ⁄ μm 0.25 ⁄ μm 0.25 ⁄ fF/μm Cdbn Cdbp C 2Cgd1 2Cgd2 Cdb1 Cdb2 Cg3 Cg4 Cw + + + + + + = Cgd1 0.3 Wn × 0.3 0.375 = 0.1125 × fF = = Cgd2 0.3 Wp × 0.3 1.125 = 0.3375 × fF = = Example 13.6 13.3 Dynamic Operation of the CMOS Inverter 1107 13.3.3 Inverter Sizing In this section we address the question of selecting appropriate (W/L) ratios for the two tran-sistors and in an inverter. Our reasoning can be summarized as follows.
1. To minimize area, the length of all channels is usually made equal to the minimum length permitted by the given technology.
Thus, Next we use Eqs. (13.64) and (13.65) to determine , Similarly, we use Eqs. (13.66) and (13.67) to determine , Finally, we determine as Cdb1 = 1 fF Cdb2 = 1 fF Cg3 = 0.375 0.25 × 6 × 2 0.3 0.375 0.7875 fF = × × + Cg4 = 1.125 0.25 × 6 × 2 0.3 1.125 2.3625 = × × fF + Cw = 0.2 fF C = 2 0.1125 × 2 0.3375 1 1 0.7875 2.3625 0.2 + + + + + × + 6.25 fF = tPHL α n 2 7 4 ---3 0.5 × 2.5 ----------------– 0.5 2.5 -------⎝ ⎠ ⎛ ⎞ 2 + ------------------------------------------------1.7 = = tPHL 1.7 6.25 10 15 – × × 115 10 6 – 0.375 0.25 ⁄ ( ) 2.5 × × × ------------------------------------------------------------------------------24.6 ps = = tPLH α p 1.7 = tPLH 1.7 6.25 10 15 – × × 30 10 6 – 1.125 0.25 ⁄ ( ) 2.5 × × × ---------------------------------------------------------------------------31.5 ps = = tP tP 1 2 --- 24.6 31.5 + ( ) 28 ps = = 13.16 Consider the inverter specified in Example 13.6 when loaded with an additional 0.1-pF capacitance.
What will the propagation delay become?
Ans. 437 ps 13.17 In an attempt to decrease the area of the inverter in Example 13.6, (W/L)p is made equal to (W/L)n.
What is the percentage reduction in area achieved? Find the new values of C, tPHL, tPLH, and tP. As-sume that does not change significantly.
Ans. 50%; 4.225 fF; 16.6 ps; 21.3 ps; 19 ps 13.18 For the inverter of Example 13.6, find the maximum frequency at which it can be operated.
Ans. 17.9 GHz Cdbp EXERCISES QN QP 1108 Chapter 13 CMOS Digital Logic Circuits 2. In a given inverter, if our interest is strictly to minimize area, is usually selected in the range 1 to 1.5. The selection of relative to has influence on the noise margins and Both are optimized by matching and This, however, is usually wasteful of area and equally important can increase the effective capacitance C, so that although is made equal to the value of both can be higher than in the case without matching (see Problem 13.40). Thus, selecting is a possibility, and is a frequently used compromise.
3. Having settled on an appropriate ratio of to we still have to select to reduce and thus allow higher speeds of operation. Any increase in and proportionally in will of course increase area, and hence the inverter contribution to the value of the equivalent capacitance C. To be more precise we express C as the sum of an intrinsic component contributed by and of the inverter, and an extrinsic component resulting from the wiring and the input capac-itance of the driven gates, (13.74) Increasing and of the inverter by a factor S relative to that of a min-imum size inverter for which results in (13.75) Now, if we use the equivalent-resistances approach to compute and define an equiv-alent inverter resistance as (13.76) then, (13.77) Further, if for the minimum-size inverter is increasing and by the factor S reduces by the same factor: (13.78) Combining Eqs. (13.77), (13.78), and (13.75), we obtain (13.79) We thus see that scaling the W/L ratios does not change the component of caused by the capacitances of and It does, however, reduce the component of that re-sults from capacitances external to the inverter itself. It follows that one can use W L ⁄ ( )n W L ⁄ ( )p W L ⁄ ( )n tPLH.
QP QN.
tPLH tPHL, W L ⁄ ( )p W L ⁄ ( )n = W L ⁄ ( )p 2 W L ⁄ ( )n = W L ⁄ ( )p W L ⁄ ( )n, W L ⁄ ( )n tP W L ⁄ ( )n W L ⁄ ( )p Cint QN QP Cext C Cint Cext + = W L ⁄ ( )n W L ⁄ ( )p Cint Cint0 = C SCint0 Cext + = tP Req Req 1 2 --- RN RP + ( ) = tP 0.69ReqC = Req Req0, W L ⁄ ( )n W L ⁄ ( )p Req Req Req0 S ⁄ = tP 0.69 Req0 S ----------⎝ ⎠ ⎛ ⎞SCint0 Cext + ( ) = tP 0.69 Req0Cint0 1 S --- Req0Cext + ⎝ ⎠ ⎛ ⎞ = tP QN QP.
tP 13.3 Dynamic Operation of the CMOS Inverter 1109 Eq. (13.79) to decide on a suitable scaling factor S that keeps below a specified max-imum value, keeping in mind of course the effect of increasing S on silicon area.
13.3.4 Dynamic Power Dissipation The negligible static power dissipation of CMOS has been a significant factor in its domi-nance as the technology of choice in implementing high-density VLSI circuits. However, as the number of gates per chip steadily increases, the dynamic power dissipation has become a serious issue. The dynamic power dissipated in the CMOS inverter is given by Eq. (13.35), which we repeat here as (13.80) where f is the frequency at which the gate is switched. It follows that minimizing C is an effective means for reducing dynamic-power dissipation. An even more effective strategy is the use of a lower power-supply voltage. As we have mentioned, CMOS process technologies now utilize VDD values of 1 V or less. These newer chips, however, pack much more circuitry on the chip (as many as 2.3 billion transistors) and operate at higher frequencies (micro-processor clock frequencies above 3 GHz are now available). The dynamic power dissipation of such high-density chips can be over 100 W.
In addition to the dynamic power dissipation that results from the periodic charging and discharging of the inverter load capacitance, there is another component of power dissipa-tion that results from the current that flows through and during every switching event. Figure 13.26 shows this inverter current as a function of the input voltage for a matched inverter. We note that the current peaks at . Since at this voltage both and operate in saturation, the peak current is given by (13.81) The width of the current pulse will depend on the rate of change of with time; the slower the rising edge of the input waveform, the wider the current pulse and the greater the energy drawn from the supply. In general, however, this power component is usually much smaller than tP 13.19 For the inverter analyzed in Example 13.6: (a) Find the intrinsic and extrinsic components of C.
(b) By what factor must and be increased to reduce the extrinsic part of by a factor of 2? (c) Estimate the resulting .
(d) By what factor is the inverter area increased?
Ans. (a) 2.9 fF, 3.35 fF; (b) 2; (c) 20.5 ps; (d) 2 W L ⁄ ( )n W L ⁄ ( )p tP tP EXERCISE Pdyn f CV 2 DD = QP QN vI VM VDD 2 ⁄ = QN QP Ipeak 1 2 ---μ nCox W L -----⎝ ⎠ ⎛ ⎞ n VDD 2 ----------Vtn – ⎝ ⎠ ⎛ ⎞ 2 = vI Pdyn.
1110 Chapter 13 CMOS Digital Logic Circuits 13.4 CMOS Logic-Gate Circuits In this section, we build on our knowledge of inverter design and consider the design of CMOS circuits that realize combinational-logic functions. In combinational circuits, the out-put at any time is a function only of the values of input signals at that time. Thus, these cir-cuits do not have memory and do not employ feedback. Combinational-logic circuits are used in large quantities in a multitude of applications; indeed, every digital system contains large numbers of combinational-logic circuits.
13.4.1 Basic Structure A CMOS logic circuit is in effect an extension, or a generalization, of the CMOS inverter: The inverter consists of an NMOS pull-down transistor, and a PMOS pull-up transistor, operated by the input voltage in a complementary fashion. The CMOS logic gate consists of two networks: the pull-down network (PDN) constructed of NMOS transistors, and the pull-up network (PUN) constructed of PMOS transistors (see Fig. 13.27). The two net-works are operated by the input variables, in a complementary fashion. Thus, for the three-input gate represented in Fig. 13.27, the PDN will conduct for all input combina-tions that require a low output (Y = 0) and will then pull the output node down to ground, Figure 13.26 The current in the CMOS inverter versus the input voltage.
13.20 Find the dynamic power dissipation of the inverter analyzed in Example 13.6 when operated at a 1-GHz frequency. If this inverter is switched at its maximum possible operating frequency, what is the value of the power–delay product?
Ans. 39 ; 19.5 fJ μW EXERCISE 13.4 CMOS Logic-Gate Circuits 1111 causing a zero voltage to appear at the output, vY = 0. Simultaneously, the PUN will be off, and no direct dc path will exist between VDD and ground. On the other hand, all input com-binations that call for a high output (Y = 1) will cause the PUN to conduct, and the PUN will then pull the output node up to VDD, establishing an output voltage vY = VDD. Simulta-neously, the PDN will be cut off, and again, no dc current path between VDD and ground will exist in the circuit.
Now, since the PDN comprises NMOS transistors, and since an NMOS transistor conducts when the signal at its gate is high, the PDN is activated (i.e., conducts) when the inputs are high. In a dual manner, the PUN comprises PMOS transistors, and a PMOS transistor conducts when the input signal at its gate is low; thus the PUN is activated when the inputs are low.
The PDN and the PUN each utilizes devices in parallel to form an OR function, and devices in series to form an AND function. Here, the OR and AND notation refer to current flow or conduction. Figure 13.28 shows examples of PDNs. For the circuit in Fig. 13.28(a), we observe that QA will conduct when A is high (vA = VDD) and will then pull the output node down to ground (vY = 0 V, Y = 0). Similarly, QB conducts and pulls Y down when B is high. Thus Y will be low when A is high or B is high, which can be expressed as or equivalently The PDN in Fig. 13.28(b) will conduct only when A and B are both high simultaneously.
Thus Y will be low when A is high and B is high, or equivalently Pull-up network (PUN) Pull-down network (PDN) Y VDD A B C A B C Figure 13.27 Representation of a three-input CMOS logic gate. The PUN comprises PMOS transistors, and the PDN comprises NMOS transistors.
Y = A + B Y A B + = Y AB = Y AB = 1112 Chapter 13 CMOS Digital Logic Circuits As a final example, the PDN in Fig. 13.28(c) will conduct and cause Y to be 0 when A is high or when B and C are both high, thus or equivalently Next consider the PUN examples shown in Fig. 13.29. The PUN in Fig. 13.29(a) will conduct and pull Y up to VDD(Y = 1) when A is low or B is low, thus The PUN in Fig. 13.29(b) will conduct and produce a high output (vY = VDD, Y = 1) only when A and B are both low, thus Figure 13.28 Examples of pull-down networks.
Figure 13.29 Examples of pull-up networks.
QA QB B Y A B A Y (a) QA QB B Y AB A Y (b) QA Y A BC A Y QB QC C B (c) Y A VDD QA B QB Y A B (a) Y A VDD QA B QB Y A B (b) B VDD QB C QC Y A QA Y A BC (c) Y A BC + = Y A BC + = Y A B + = Y AB = 13.4 CMOS Logic-Gate Circuits 1113 Finally, the PUN in Fig. 13.29(c) will conduct and cause Y to be high (logic 1) if A is low or if B and C are both low; thus, Having developed an understanding and an appreciation of the structure and operation of PDNs and PUNs, we now consider complete CMOS gates. Before doing so, however, we wish to introduce alternative circuit symbols, that are almost universally used for MOS transistors by digital-circuit designers. Figure 13.30 shows our usual symbols (left) and the corresponding “digital” symbols (right). Observe that the symbol for the PMOS transistor with a circle at the gate terminal is intended to indicate that the signal at the gate has to be low for the device to be activated (i.e., to conduct). Thus, in terms of logic-circuit terminology, the gate terminal of the PMOS transistor is an active low input. Besides indicating this property of PMOS devices, the digital symbols omit any indication of which of the device terminals is the source and which is the drain. This should cause no difficulty at this stage of our study; simply remember that for an NMOS transistor, the drain is the terminal that is at the higher voltage (current flows from drain to source), and for a PMOS transistor the source is the terminal that is at the higher voltage (current flows from source to drain). To be consistent with the litera-ture, we shall henceforth use these modified symbols for MOS transistors in logic applica-tions, except in locations where our usual symbols help in understanding circuit operation.
13.4.2 The Two-Input NOR Gate We first consider the CMOS gate that realizes the two-input NOR function (13.82) We see that Y is to be low (PDN conducting) when A is high or B is high. Thus the PDN con-sists of two parallel NMOS devices with A and B as inputs (i.e., the circuit in Fig. 13.28a).
For the PUN, we note from the second expression in Eq. (13.82) that Y is to be high when A and B are both low. Thus the PUN consists of two series PMOS devices with A and B as the inputs (i.e., the circuit in Fig. 13.29b). Putting the PDN and the PUN together gives the CMOS NOR gate shown in Fig. 13.31. Note that extension to a higher number of inputs is straightforward: For each additional input, an NMOS transistor is added in parallel with QNA and QNB, and a PMOS transistor is added in series with QPA and QPB.
Figure 13.30 Usual and alternative circuit symbols for MOSFETs.
NMOS (a) PMOS (b) Y A BC + = Y A B + AB = = 1114 Chapter 13 CMOS Digital Logic Circuits 13.4.3 The Two-Input NAND Gate The two-input NAND function is described by the Boolean expression (13.83) To synthesize the PDN, we consider the input combinations that require Y to be low: There is only one such combination, namely, A and B both high. Thus, the PDN simply comprises two NMOS transistors in series (such as the circuit in Fig. 13.28b). To synthesize the PUN, we consider the input combinations that result in Y being high. These are found from the second expression in Eq. (13.83) as A low or B low. Thus, the PUN consists of two parallel PMOS transistors with A and B applied to their gates (such as the circuit in Fig. 13.29a). Put-ting the PDN and PUN together results in the CMOS NAND gate implementation shown in Fig. 13.32. Note that extension to a higher number of inputs is straightforward: For each QNA QNB B Y A B A Y QPA QPB B A VDD Figure 13.31 A two-input CMOS NOR gate.
Y AB A B + = = A B Y QNA QPB QPA QNB B A VDD Y AB Figure 13.32 A two-input CMOS NAND gate.
13.4 CMOS Logic-Gate Circuits 1115 additional input, we add an NMOS transistor in series with QNA and QNB, and a PMOS tran-sistor in parallel with QPA and QPB.
13.4.4 A Complex Gate Consider next the more complex logic function (13.84) Since , we see that Y should be low for A high and simultaneously either B high or C and D both high, from which the PDN is directly obtained. To obtain the PUN, we need to express Y in terms of the complemented variables. We do this through repeated application of DeMorgan’s law, as follows: (13.85) Thus, Y is high for A low or B low and either C or D low. The corresponding complete CMOS circuit will be as shown in Fig. 13.33.
13.4.5 Obtaining the PUN from the PDN and Vice Versa From the CMOS gate circuits considered thus far (e.g., that in Fig. 13.33), we observe that the PDN and the PUN are dual networks: Where a series branch exists in one, a parallel branch exists in the other. Thus, we can obtain one from the other, a process that can be sim-pler than having to synthesize each separately from the Boolean expression of the function.
For instance, in the circuit of Fig. 13.33, we found it relatively easy to obtain the PDN, sim-ply because we already had in terms of the uncomplemented inputs. On the other hand, to obtain the PUN, we had to manipulate the given Boolean expression to express Y as a func-tion of the complemented variables, the form convenient for synthesizing PUNs. Alterna-tively, we could have used this duality property to obtain the PUN from the PDN. The reader is urged to refer to Fig. 13.33 to convince herself that this is indeed possible. It should, however, be mentioned that at times it is not easy to obtain one of the two net-works from the other using the duality property. For such cases, one has to resort to a more rigorous process, which is beyond the scope of this book (see Kang and Leblebici, 1999).
13.4.6 The Exclusive-OR Function An important function that often arises in logic design is the exclusive-OR (XOR) function, (13.86) We observe that since Y (rather than ) is given, it is easier to synthesize the PUN. We note, however, that unfortunately Y is not a function of the complemented variables only (as we Y A B CD + ( ) = Y = A B CD + ( ) Y A B CD + ( ) = A B CD + + = A B CD + = A B C D + ( ) + = Y Y AB AB + = Y 1116 Chapter 13 CMOS Digital Logic Circuits would like it to be). Thus, we will need additional inverters. The PUN obtained directly from Eq. (13.86) is shown in Fig. 13.34(a). Note that the Q1, Q2 branch realizes the first term ( ), whereas the Q3, Q4 branch realizes the second term ( ). Note also the need for two additional inverters to generate and .
As for synthesizing the PDN, we can obtain it as the dual network of the PUN in Fig. 13.34(a). Alternatively, we can develop an expression for and use it to synthesize the PDN. Leaving the first approach for the reader to do as an exercise, we shall utilize the direct synthesis approach. DeMorgan’s law can be applied to the expression in Eq. (13.86) to obtain as (13.87) The corresponding PDN will be as in Fig. 13.34(b), which shows the CMOS realization of the exclusive-OR function except for the two additional inverters. Note that the exclusive-OR requires 12 transistors for its realization, a rather complex network. Later, in Section 14.2, we shall show a simpler realization of the XOR employing a different form of CMOS logic.
Another interesting observation follows from the circuit in Fig. 13.34(b). The PDN and the PUN here are not dual networks. Indeed, duality of the PDN and the PUN is not a neces-sary condition. Thus, although a dual of PDN (or PUN) can always be used for PUN (or PDN), the two networks are not necessarily duals.
A B Y QNA QPB QPA QNB B QND D QNC C A VDD D QPD C QPC Y A(B CD) Figure 13.33 CMOS realization of a com-plex gate.
AB AB A B Y Y Y AB AB + = 13.4 CMOS Logic-Gate Circuits 1117 13.4.7 Summary of the Synthesis Method 1. The PDN can be most directly synthesized by expressing as a function of the uncom-plemented variables. If complemented variables appear in this expression, additional inverters will be required to generate them.
2. The PUN can be most directly synthesized by expressing Y as a function of the comple-mented variables and then applying the uncomplemented variables to the gates of the PMOS transistors. If uncomplemented variables appear in the expression, additional inverters will be needed.
3. The PDN can be obtained from the PUN (and vice versa) using the duality property.
13.4.8 Transistor Sizing Once a CMOS gate circuit has been generated, the only significant step remaining in the design is to decide on ratios for all devices. These ratios usually are selected to provide the gate with current-driving capability in both directions equal to that of the basic inverter. For the basic inverter design, denote = n and = p, where n is usually 1 to 1.5 and, for a matched design, p = n; although often p = 2n and for minimum area p = n. Thus, we wish to select individual ratios for all transistors in a logic gate so that the PDN should be able to provide a capacitor discharge current at least equal to that of an NMOS transistor with = n, and the PUN should be able to Figure 13.34 Realization of the exclusive-OR (XOR) function: (a) The PUN synthesized directly from the expression in Eq. (13.86). (b) The complete XOR realization utilizing the PUN in (a) and a PDN that is synthesized directly from the expression in Eq. (13.87). Note that two inverters (not shown) are needed to generate the complemented variables. Also note that in this XOR realization, the PDN and the PUN are not dual networks; however, a realization based on dual networks is possible (see Problem 13.47).
Y Q1 Q2 B VDD Q3 Q4 A B A (a) A B Y B VDD A B B A A (b) Y W L ⁄ (W L ⁄ )n (W L ⁄ )p μn μp ⁄ ( ) W L ⁄ W L ⁄ 1118 Chapter 13 CMOS Digital Logic Circuits provide a charging current at least equal to that of a PMOS transistor with = p.
This will guarantee a worst-case gate delay equal to that of the basic inverter.4 In the preceding description, the idea of “worst case” should be emphasized. It means that in deciding on device sizing, we should find the input combinations that result in the lowest output current and then choose sizes that will make this current equal to that of the basic inverter. Before we consider examples, we need to address the issue of determining the current-driving capability of a circuit consisting of a number of MOS devices. In other words, we need to find the equivalent ratio of a network of MOS transistors. Toward that end, we consider the parallel and series connection of MOSFETs and find the equivalent ratios.
The derivation of the equivalent ratio is based on the fact that the on resistance of a MOSFET is inversely proportional to (see Eqs. 13.70 and 13.71). Thus, if a number of MOSFETs having ratios of , , . . ., are connected in series, the equivalent series resistance obtained by adding the on-resistances will be resulting in the following expression for for transistors connected in series: (13.88) Similarly, we can show that the parallel connection of transistors with ratios of , , . . . , results in an equivalent of (13.89) As an example, two identical MOS transistors with individual ratios of 4 result in an equivalent of 2 when connected in series and of 8 when connected in parallel.5 As an example of proper sizing, consider the four-input NOR in Fig. 13.35. Here, the worst case (the lowest current) for the PDN is obtained when only one of the NMOS transis-tors is conducting. We therefore select the of each NMOS transistor to be equal to that of the NMOS transistor of the basic inverter, namely, n. For the PUN, however, the worst-case situation (and indeed the only case) occurs when all inputs are low and the four series PMOS transistors are conducting. Since the equivalent will be one-quarter of that of 4This statement assumes that the total effective capacitance C of the logic gate is the same as that of the inverter. In actual practice, the value of C will be larger for a gate, especially as the fan-in is increased.
5Another way of thinking about this is as follows: Connecting MOS transistors in series is equivalent to adding the lengths of their channels while the width does not change; connecting MOS transistors in parallel does not change the channel length but increases the width to the sum of the W’s.
W L ⁄ W L ⁄ W L ⁄ W L ⁄ W L ⁄ (W L ⁄ )1 (W L ⁄ )2 Rseries RN1 RN2 . . .
+ + = constant (W L ⁄ )1 --------------------constant (W L ⁄ ) 2 --------------------. . .
+ + = constant 1 (W L ⁄ )1 -------------------1 (W L ⁄ ) 2 -------------------. . .
+ + = constant (W L ⁄ )eq ---------------------= (W L ⁄ )eq (W L ⁄ )eq 1 1 (W L ⁄ )1 -------------------1 (W L ⁄ )2 -------------------. . .
+ + ----------------------------------------------------------= W L ⁄ (W L ⁄ )1 (W L ⁄ )2 W L ⁄ (W L ⁄ )eq (W L ⁄ )1 (W L ⁄ )2 . . .
+ + = W L ⁄ W L ⁄ W L ⁄ W L ⁄ 13.4 CMOS Logic-Gate Circuits 1119 each PMOS device, we should select the ratio of each PMOS transistor to be four times that of QP of the basic inverter, that is, 4p.
As another example, we show in Fig. 13.36 the proper sizing for a four-input NAND gate. Comparison of the NAND and NOR gates in Figs. 13.35 and 13.36 indicates that Figure 13.35 Proper transistor sizing for a four-input NOR gate. Note that n and p denote the ratios of QN and QP, respectively, of the basic inverter.
Figure 13.36 Proper transistor sizing for a four-input NAND gate. Note that n and p denote the ratios of QN and QP, respectively, of the basic inverter.
n Y A B C D 4p 4p 4p 4p A B C D B n C n D n A VDD W L ⁄ Y ABCD 4n 4n p p p p 4n 4n A A B C D B C D VDD W L ⁄ W L ⁄ 1120 Chapter 13 CMOS Digital Logic Circuits because p is usually two to three times n, the NOR gate will require much greater area than the NAND gate. For this reason, NAND gates are generally preferred for implementing combinational logic functions in CMOS.
Provide transistor ratios for the logic circuit shown in Fig. 13.37. Assume that for the basic inverter n = 1.5 and p = 5 and that the channel length is 0.25 μm.
Solution Refer to Fig. 13.37, and consider the PDN first. We note that the worst case occurs when QNB is on and either or is on. That is, in the worst case, we have two transistors in series. Therefore, we select each of and to have twice the width of the n-channel device in the basic inverter, thus For transistor select to be equal to that of the n-channel device in the basic inverter: Figure 13.37 Circuit for Example 13.7.
W L ⁄ QNA (0.375/0.25) QNB (0.75/0.25) A Y QPB (1.875/0.25) B QPD QPC (3.75/0.25) C QNC (0.75/0.25) QND (0.75/0.25) C QPA (3.75/0.25) A B D VDD (3.75/0.25) QNC QND QNB, QNC, QND QNB: W L ⁄ = 2n = 3 = 0.75 0.25 ⁄ QNC: W L ⁄ = 2n = 3 = 0.75 0.25 ⁄ QND: W L ⁄ = 2n = 3 = 0.75 0.25 ⁄ QNA, W L ⁄ QNA: W L ⁄ = n = 1.5 = 0.375 0.25 ⁄ Example 13.7 13.4 CMOS Logic-Gate Circuits 1121 .
13.4.9 Effects of Fan-In and Fan-Out on Propagation Delay Each additional input to a CMOS gate requires two additional transistors, one NMOS and one PMOS. This is in contrast to other forms of MOS logic, where each additional input requires only one additional transistor (see Section 14.1). The additional transistor in CMOS not only increases the chip area but also increases the total effective capacitance per gate and in turn increases the propagation delay. The size-scaling method described earlier compen-sates for some (but not all) of the increase in tP. Specifically, by increasing device size, we are able to preserve the current-driving capability. However, the capacitance C increases because of both the increased number of inputs and the increase in device size. Thus tP will still increase with fan-in, a fact that imposes a practical limit on the fan-in of, say, the NAND gate to about 4. If a higher number of inputs is required, then “clever” logic design should be adopted to realize the given Boolean function with gates of no more than four inputs. This would usually mean an increase in the number of cascaded stages and thus an increase in delay. However, such an increase in delay can be less than the increase due to the large fan-in (see Problem 13.56).
An increase in a gate’s fan-out adds directly to its load capacitance and, thus, increases its propagation delay.
Thus although CMOS has many advantages, it does suffer from increased circuit com-plexity when the fan-in and fan-out are increased, and from the corresponding effects of this complexity on both chip area and propagation delay. Later, in Sections 14.1 and 14.2, we shall study some simplified forms of CMOS logic that attempt to reduce this complexity, although at the expense of forgoing some of the advantages of basic CMOS.
Next, consider the PUN. Here, we see that in the worst case, we have three transistors in series: QPA, QPC, and QPD. Therefore, we select the ratio of each of these to be three times that of QP in the basic inverter, that is, 3p, thus Finally, the ratio for QPB should be selected so that the equivalent of the series connection of QPB and QPA should be equal to p. It follows that for QPB the ratio should be 1.5p, Figure 13.37 shows the circuit with the transistor sizes indicated.
W L ⁄ QPA: W L ⁄ = 3p = 15 = 3.75 0.25 ⁄ QPC: W L ⁄ = 3p = 15 = 3.75 0.25 ⁄ QPD: W L ⁄ = 3p = 15 = 3.75 0.25 ⁄ W L ⁄ W L ⁄ QPB: W L ⁄ = 1.5p = 7.5 = 1.875 0.25 ⁄ 13.21 For a process technology with L = 0.18 μm, n = 1.5, p = 3, give the sizes of all transistors in (a) a four-input NOR and (b) a four-input NAND. Also, give the relative areas of the two gates.
Ans.
(a) NMOS devices: = 0.27/0.18, PMOS devices: 2.16/0.18; (b) NMOS devices: = 1.08/0.18, PMOS devices: 0.54/0.18; NOR area = 1.5 W L ⁄ W L ⁄ area NAND ⁄ EXERCISES 1122 Chapter 13 CMOS Digital Logic Circuits 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design As mentioned in Chapter 4, and in a number of locations throughout the book, the minimum MOSFET channel length has been continually reduced over the past 40 years or so. In fact, a new CMOS fabrication technology has been introduced every 2 or 3 years, with the mini-mum allowable channel length reduced by about 30%, that is, to 0.7 the value in the preced-ing generation. Thus, with every new technology generation, the device area has been reduced by a factor of or approximately 2, allowing the fabrication of twice as many devices on a chip of the same area. This astounding phenomenon, predicted more than 40 years ago by Gordon Moore,6 has become known as Moore’s law. It is this ability to pack an exponentially increasing number of transistors on an IC chip that has resulted in the continuing reduction in the cost per logic function.
Figure 13.38 shows the exponential reduction in MOSFET channel length (by a factor of 2 every 5 years) over a 40 year period, with the dots indicating some of the prominent technol-ogy generations, or nodes. Thus, we see the 10-μm process of the early 1970s, the submicron processes of the early 1990s, and the deep-submicron processes of the last decade, including the current 45-nm process. A microprocessor chip fabricated in a 45-nm CMOS process and having 2.3 billion transistors was announced in 2009. Deep-submicron (DSM) processes present the circuit designer with a host of new opportunities and challenges.
It is our purpose in this section to briefly consider some of these.
6Gordon Moore is one of the pioneers of the semiconductor industry and a cofounder of Intel.
Figure 13.38 The MOSFET channel length has been reduced by a factor of 2 every about 5 years. This phenomenon, known as Moore’s law is continuing.
13.22 For the scaled NAND gate in Exercise 13.21, find the ratio of the maximum to minimum current available to (a) charge a load capacitance and (b) discharge a load capacitance.
Ans. (a) 4; (b) 1 1 0.7 0.7 × ( ) ⁄ L 1 μm < ( ) L 0.25 μm < ( ) 1.0 m 1970 1980 1990 2000 Year Lmin 10 nm 0.1 m 2010 10 m 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1123 13.5.1 Scaling Implications Table 13.2 provides a summary of the implications of scaling the device dimensions by a factor 1/S, where . As well, we assume that and are scaled by the same factor.
Although the scaling of has occurred for a number of technology nodes (e.g., from 5 V for the 0.5-μm process down to 1.2 V for the 0.13-μm process), has been reduced but not by the same factor. Thus the assumption in row 2 of Table 13.2 is not entirely correct. Nev-ertheless, our interest here is to gain a general appreciation for the effects of scaling.
Table 13.2 provides the relationships for the various transistor and inverter parameters in order to show how the resulting scale factors are obtained. We thus see that the device area scales by ; the oxide capacitance , and the transconductance parameters and scale by S; and the MOSFET gate capacitance scales by 1/S. It is important to note that the component of the inverter propagation delay due to the transistor capacitances (i.e., exclud-ing the wiring capacitance) scales by 1/S; this very useful result of scaling implies that the circuit can be operated at S times the frequency; that is, the speed of operation increases by a factor S. Equally important, the dynamic power dissipation scales by . This, of course, is a major motivating factor behind the scaling of . Another motivating factor is the need to keep the electric fields in the MOSFETs within acceptable bounds.
Although the dynamic power dissipation is scaled by , the power per unit area remains unchanged. Nevertheless, for a number of reasons, as the size and complexity of digital IC chips continue to increase, so does their power dissipation. Indeed power dissipa-tion has now become the number-one issue in IC design. The problem is further exacerbated by the static power dissipation, arising from both subthreshold conduction and diode leak-age currents, that plagues deep-submicron CMOS devices. We will discuss this issue shortly.
Table 13.2 Implications of Device and Voltage Scaling Parameter Relationship Scaling Factor 1 W, L, 1/S 2 , 1/S 3 Area/Device WL 1/S 2 4 S 5 , , S 6 1/S 7 (intrinsic) 1/S 8 Energy/Switching cycle (intrinsic) 1/S 3 9 1/S2 10 Power density /Device area 1 S 1 > VDD Vt VDD Vt 1 S2 ⁄ Cox kn ′ kp ′ 1 S2 ⁄ VDD 1 S2 ⁄ tox VDD Vt Cox εox tox ⁄ kn ′ kp ′ μnCox μ pCox Cgate WLCox tP αC k ′ ⁄ VDD CVDD 2 Pdyn fmaxCVDD 2 CVDD 2 2tP -------------= Pdyn 1124 Chapter 13 CMOS Digital Logic Circuits 13.5.2 Velocity Saturation The short channels of MOSFETs fabricated in deep-submicron processes give rise to physi-cal phenomena not present in long-channel devices, and thus to changes in the MOSFET characteristics. The most important of these short-channel effects is velocity satura-tion. Here we refer to the drift velocity of electrons in the channel of an NMOS transistor (holes in PMOS) under the influence of the longitudinal electric field established by . In our derivation of the MOSFET characteristics in Section 5.1, we assumed that the velocity vn of the electrons in an n-channel device is given by (13.90) where E is the electric field given by (13.91) The relationship in Eq. (13.90) applies as long as E is below a critical value which falls in the range 1 V/μm to 5 V/μm. For the drift velocity saturates at a value of approxi-mately Figure 13.39 shows a sketch of versus E. Although the change from a linear to a constant is gradual, we shall assume for simplicity that saturates abruptly at Figure 13.39 The velocity of electrons in the channel of an NMOS transistor reach a constant velocity vsat 107 cm/s when the electric field E reaches a critical value Ecr. A similar situation occurs for p-channel devices.
13.23 By what factor does the power–delay product PDP change if an inverter is fabricated in a 0.13 μm technology rather than a 0.25-μm technology? Assume .
Ans. PDP decreases by a factor of 8.
13.24 If and are kept constant, which entries in Table 13.2 change and to what value?
Ans. now scales by 1/S2; the energy/switching cycle now scales by 1/S only; now scales by S; and the power density now scales by S3 (a major problem).
S 2 VDD Vt tP Pdyn EXERCISES i v – vDS i v – vn μ nE = E vDS L --------= Ecr E Ecr, > vsat 107cm/s.
v v v E Ecr.
= Ecr vsat vn E n Slope 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1125 The electric field E in a short-channel MOSFET can easily exceed even though is low. If we denote the value of at which velocity saturation occurs by , then from Eq. (13.91), (13.92) which when substituted in Eq. (13.90) provides (13.93) or alternatively, (13.94) Thus, is a device parameter. The iD–vDS Characteristics The equations of the MOSFET can be modified to in-clude velocity saturation as follows. Consider a long-channel NMOS transistor operating in the triode region with set to a constant value The drain current will be (13.95) where we have for the time being neglected channel-length modulation. We know from our study in Section 5.1 that will saturate at (13.96) and the saturation current will be (13.97) This will also be the case in a short-channel device as long as the value of in Eq. (13.96) is lower than . That is, as long as the current will be given by Eqs. (13.95) and (13.97). If, on the other hand, Ecr VDD vDS VDSsat Ecr VDSsat L --------------= vsat μ n VDSsat L --------------⎝ ⎠ ⎛ ⎞ = vDSsat L μ n -------⎝ ⎠ ⎛ ⎞vsat = VDSsat 13.25 Find for an NMOS transistor fabricated in a 0.25-μm CMOS process with . Let L = 0.25 μm and assume .
Ans. 0.63 V VDSsat μn 400 cm2 V s ⋅ ⁄ = vsat 107cm/s = EXERCISE iD vDS – vGS VGS.
iD μ nCox W L -----⎝ ⎠ ⎛ ⎞vDS VGS Vt – ( ) 1 2 ---vDS – = iD vDS VOV VGS Vt – = = iD 1 2 ---μnCox W L -----⎝ ⎠ ⎛ ⎞VGS Vt – ( )2 = vDS VDSsat VOV VDSsat < iD VOV VDSsat > 1126 Chapter 13 CMOS Digital Logic Circuits then velocity saturation kicks in at and saturates at a value as shown in Fig. 13.40. The value of can be obtained by substituting in Eq. (13.95), (13.98) This expression can be simplified by utilizing Eq. (13.94) to obtain (13.99) Replacing in Eq. (13.98) with , and incorporating the channel-length modulation factor we obtain a general expression for the drain current of an NMOS transis-tor operating in velocity saturation, (13.100) which applies for and (13.101) Figure 13.41 shows a set of characteristic curves and clearly delineates the three regions of operation: triode, saturation, and velocity saturation.
Equation (13.100) indicates that in the velocity-saturation region, is linearly related to This is a major change from the quadratic relationship that characterizes operation in the saturation region. Figure 13.42 makes this point clearer by presenting a graph for ver-sus of a short-channel device operating at Observe that for the MOSFET operates in the saturation region and is related to by the familiar quadratic equation (Eq. 13.97). For the transistor enters the velocity-saturation region and varies linearly with (Eq. 13.100). Short-channel PMOS transistors undergo velocity saturation at the same value of (approximately ), but the effects on the device characteristics are less pronounced than in the NMOS case. This is due to the lower values of and the correspondingly higher values of and .
Figure 13.40 Velocity saturation causes the iD–vDS characteristic to saturate at VDSsat. This early saturation results in a current IDsat that is lower than the value for a long-channel device.
VOV iD vDS vGS Vt VOV VDSsat IDsat μ Cox VOV n 1 2 2 W L vDS VDSsat = iD IDsat, IDsat vDS VDSsat = IDsat μnCox W L -----⎝ ⎠ ⎛ ⎞VDSsat VGS Vt – 1 2 ---VDSsat – ⎝ ⎠ ⎛ ⎞ = IDsat WCoxvsat VGS Vt – 1 2 ---VDSsat – ⎝ ⎠ ⎛ ⎞ = VGS vGS 1 λ vDS + ( ), iD μ nCox W L -----⎝ ⎠ ⎛ ⎞VDSsat vGS Vt – 1 2 ---VDSsat – ⎝ ⎠ ⎛ ⎞1 λvDS + ( ) = vGS Vt VDSsat ≥ – vDS VDSsat ≥ iD vDS – iD vGS.
iD vGS vDS VDSsat.
0 vGS Vt VDSsat, ≤ – < iD vGS vGS Vt VDSsat, ≥ – iD vGS vsat 107cm s ⁄ μ p Ecr VDSsat 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1127 Figure 13.41 The iD–vDS characteristics of a short-channel MOSFET. Note the three different regions of operation: triode; saturation; and velocity saturation.
Figure 13.42 The iD–vGS characteristic of a short-channel NMOS transistor operating at vDS > VDSsat.
Observe the quadratic and the linear portions of the characteristic. Also note that in the absense of velocity saturation, the quadratic curve would continue as shown with the broken line.
Consider MOS transistors fabricated in a 0.25-μm CMOS process for which , and Let L = 0.25 μm and . Measurements indicate that for the NMOS transistor, and for the PMOS device, . Calculate the drain current obtained in each of the NMOS and PMOS transistors for . Compare with the values that would have been obtained in the absence of velocity saturation. Also give the range of for which is saturated, with and without velocity saturation.
Solution For the NMOS transistor, results in , which is greater than . Also, is greater than ; thus both conditions in Eq. (13.101) are satisfied, and VDD 2.5 V, = Vtn Vtp 0.5 V = – = μ nCox 115 μA V2 ⁄ , = μ pCox 30 μA V2 ⁄ , = λn 0.6 V 1 – , = λ p 0.1 V 1 – .
= W L ⁄ ( )n W L ⁄ ( )p 1.5 = = VDSsat 0.63 V, = VDSsat 1 V = VGS VDS VDD = = vDS iD VGS 2.5 V = VGS Vtn 2.5 0.5 2 V = – = – VDSsat VDS 2.5 V = VDSsat Example 13.8 iD VDSsat vDS vGS Vt VDSsat vGS Vt VDSsat vGS Vt VDSsat vGS Vt VDSsat Triode Velocity saturation Saturation 0 iD vGS Vt (Vt VDSsat) Linear Quadratic 0 1128 Chapter 13 CMOS Digital Logic Circuits Example 13.8 continued the NMOS transistor will be operating in the velocity-saturation region, and thus is given by Eq. (13.100): If velocity saturation were absent, the current would be Thus, velocity saturation reduces the current level by nearly 50%! The saturation current, however, is obtained over a larger range of ; specifically, for to 2.5 V. (Of course, the current does not remain constant over this range because of channel-length modulation.) In the absence of velocity sat-uration, the current saturates at and thus the saturation current is obtained over the range V to 2.5 V. For the PMOS transistor, we see that since and are both larger that the device will be operating in velocity saturation, and can be obtained by adapt-ing Eq. (13.100) as follows: Without velocity saturation, we have Thus velocity saturation reduces the current by 25% (which is less than in the case of the NMOS transis-tor), and the saturated current is obtained over the range to 2.5 V. In the absence of velocity saturation, the saturated would have been obtained for V to 2.5 V.
iD iD 115 10 × 6 – 1.5 0.63 2.5 0.5 – 1 2 ---0.63 × – ⎝ ⎠ ⎛ ⎞ 1 0.06 2.5 × + ( ) × × × × 210.6 μA = = iD 1 2 --- μ nCox ( ) W L -----⎝ ⎠ ⎛ ⎞ n vGS Vtn – ( )2 1 λvDS + ( ) = 1 2 ---115 10 6 – × × 1.5 2.5 0.5 – ( ) × × 2 1 0.06 2.5 × + ( ) × = 396.8 μA = vDS vDS 0.63 V = VOV VGS Vt 2 V, = – = vDS 2 = VGS Vt 2 V = – VDS 2.5 V = VDSsat 1 V = iD iD μ pCox ( ) W L -----⎝ ⎠ ⎛ ⎞ p VDSsat VGS Vtp – 1 2 --- VDSsat – ⎝ ⎠ ⎛ ⎞1 λp VDS + ( ) = 30 10 6 – × 1.5 1 2.5 0.5 – 1 2 ---1 × – ⎝ ⎠ ⎛ ⎞ × × × 1 0.1 2.5 × + ( ) = 84.4 μA = iD 1 2 --- μ pCox ( ) W L -----⎝ ⎠ ⎛ ⎞ p VGS Vtp – ( )2 1 λp VDS + ( ) = 1 2 ---30 10 6 – × × 1.5 2.5 0.5 – ( )2 × × 1 0.1 2.5 × + ( ) = 112.5 μA = VDS 1 V = iD VDS 2 = 13.26 Repeat the problem in Example 13.8 for transistors fabricated in a 0.13-μm CMOS process for which , , . Let L = 0.13 μm, , (NMOS) = 0.34 V, and (PMOS) = 0.6 V.
VDD 1.2 V, = Vtn Vtp 0.4 V, = – = μ nCox 430 μA V2 ⁄ = μ pCox 110 μA V2 ⁄ = λ n λ p 0.1 V 1 – = = W L ⁄ ( )n W L ⁄ ( )p 1.5 = = VDSsat VDSsat EXERCISE 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1129 Effect on the Inverter Characteristics The VTC of the CMOS inverter can be derived using the modified characteristics of the MOSFETs. The results, however, indicate relatively small changes from the VTC derived in Section 13.2 using the long-channel equa-tions (see Rabaey et al., 2003 and Hodges et al., 2004), and we shall not pursue this subject here. The dynamic characteristics of the inverter, however, are significantly impacted by velocity saturation. This is because the current available to charge and discharge the equiva-lent load capacitance C is substantially reduced.
A Remark on the MOSFET Model The model derived above for short-channel MOS-FETs is an approximate one, intended to enable the circuit designer to perform hand analysis to gain insight into circuit operation. Also, the model parameter values are usually obtained from measured data by means of a numerical curve-fitting process. As a result, the model applies only over a restricted range of terminal voltages.
Modeling short-channel MOSFETs is an advanced topic that is beyond the scope of this book. Suffice it to say that sophisticated models have been developed and are utilized by cir-cuit simulation programs such as SPICE (see Appendix B). Circuit simulation is an essential step in the design of integrated circuits. However, it is not a substitute for initial hand analy-sis and design.
13.5.3 Subthreshold Conduction In our study of the NMOS transistor in Section 5.1, we assumed that current conduction between drain and source occurs only when exceeds . That is, we assumed that for no current flows between drain and source. This, however, turns out not to be the case, especially for deep-submicron devices. Specifically, for a small current flows. To be able to see this subthreshold conduction, we have redrawn the graph of Fig. 13.42, utilizing a logarithmic scale for , as shown in Fig. 13.43. Observe that at low values of , the relationship between log and is linear, indicating that var-ies exponentially with , (13.102) where is a constant, is the thermal voltage at room temperature, and n is a constant whose value falls in the range 1 to 2, depending on the material and struc-ture of the device.7 Subthreshold conduction has been put to good use in the design of very-low-power cir-cuits such as those needed for electronic watches. Generally speaking, however, subthresh-old conduction is a problem in digital IC design. This is so for two reasons.
7This relationship is reminiscent of the relationship of a BJT (Chapter 6). This is no coinci-dence, for the subthreshold conduction in a MOSFET is due to the lateral bipolar transistor formed by the source and drain diffusions with the substrate acting as the base region (see Fig. 5.1).
Ans. NMOS: compared to 231.2 without velocity saturation; saturation is obtained over the range to 1.2 V, compared to to 1.2 V in the ab-sence of velocity saturation. PMOS: compared to , and to 1.2 V compared to 0.8 V to 1.2 V.
ID 154.4 μA, = μA vDS 0.34 V = vDS 0.8 V = ID 55.4 μA = 59.9 μA vDS 0.6 V = iD vDS – vGS Vt vGS Vt < vGS Vt < iD iD vGS – iD vGS iD vGS iD vGS iD ISe vGS nVT ⁄ = IS VT kT q ⁄ = 25 mV iC vBE – 1130 Chapter 13 CMOS Digital Logic Circuits 1. The nonzero current that flows for (see Fig. 13.43) causes the CMOS inverter to dissipate static power. To keep this off current as low as possible, of the MOS-FET is kept relatively high. This indeed is the reason why has not been scaled by the same factor as that used for the channel length. Although the off current is low (10 pA to 100 pA) and the power dissipation per inverter is small, the problem becomes serious in chips with a billion transistors!
2. The nonzero current of a normally off transistor can cause the discharge of capacitors in dynamic MOS circuits. As we shall see in the next two chapters, dynamic logic and memory circuits rely on charge storage on capacitors for their proper operation. Thus, subthreshold conduction can disrupt the operation of such circuits.
13.5.4 Wiring—The Interconnect The logic gates on a digital IC chip are connected together by metal wires8 (see Appendix A). As well, the power supply and ground are distributed throughout the chip by metal wires. Technology scaling into the deep-submicron range have caused these wires to behave Figure 13.43 The iD– vGS characteristic of a short channel MOSFET. To show the details of subthreshold conduction a logarithmic scale is needed for iD.
8These are strips of metal deposited on an insulating surface on top of the chip. In modern digital ICs, as many as eight layers of such wiring are utilized.
vGS Vt iD 10 2.3 nVT 0 (log scale) vGS 0 = Vt Vt 13.27 (a) Refer to Fig. 13.43 and to Eq. (13.102). Show that the inverse of the slope of the straight line representing subthreshold conduction is given by V per decade of current change.
(b) If measurements indicate n = 1.22 and at , find at (c) For a chip having 500 million transistors, find the current drawn from the 1.2-V supply as a result of subthreshold conduction. Hence estimate the resulting power dissipation.
Ans. (b) 0.1 nA; (c) 50 mA, 60 mW 2.3nVT iD 100 nA = vGS 0.21 V = iD vGS 0.
= VDD EXERCISE VDD 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1131 not simply as wires! Specifically, the narrow wires typical of deep-submicron technologies exhibit nonzero resistance. The result is an IR drop on the line resulting in somewhat different voltages being delivered to different parts of the chip, as shown in Fig. 13.44. This can have deleterious effects on the operation of the overall circuit.
Since chips fabricated in deep-submicron technologies can have hundreds of millions of gates, the wire connection between gates can be long. The resulting narrow and long inter-connect lines have not only nonzero resistance but also capacitance to ground, as shown in Fig. 13.45. The resistance and capacitance of an interconnect line can cause a propagation delay approaching that of the logic gate itself. As well, the capacitance between adjacent wires can cause the signals on one wire to be coupled to the other, which can cause errone-ous operation of logic circuits.
In short, the circuit designer of modern deep-submicron digital ICs has to concern herself not only with the logic-circuit design but also with the wiring or interconnect issues. Indeed, advanced textbooks on digital IC design devote entire chapters to this topic (see Rabaey et al., 2003, and Hodges et al., 2004). Our intent here is simply to point out that interconnect has become an important issue in digital IC design.
Figure 13.44 The power-supply line in a deep submicron IC has non-zero resistance. The IR drops along the VDD line cause the voltages delivered to various circuits to differ.
Figure 13.45 The interconnect (wire) between two circuit blocks, A and B, on an IC chip has finite resis-tance and a capacitance to ground.
VDD A B Out In A B Out In 1132 Chapter 13 CMOS Digital Logic Circuits Summary The digital logic inverter is the basic building block of digital circuits, just as the amplifier is the basic building block of analog circuits.
The static operation of the inverter is described by its voltage-transfer characteristic (VTC). The VTC deter-mines the inverter noise margins; refer to Fig. 13.5 and to Table 13.1 for the definitions of important VTC points and the noise margins. In particular, note that and and refer to the ideal VTC in Fig. 13.6. The inverter is implemented using transistors operating as voltage-controlled switches. There are three possible arrange-ments, shown in Figs. 13.7, 13.8, and 13.9. The arrangement in Fig. 13.8 results in a high-performance inverter and is the basis for the CMOS inverter studied in Section 13.2.
An important performance parameter of the inverter is the amount of power it dissipates. There are two components of power dissipation: static and dynamic. The first is the result of current flow in either the 0 or 1 state or both. The second occurs when the inverter is switched and has a ca-pacitor load C. Dynamic power dissipation The speed of operation of the inverter is characterized by its propagation delay, Refer to Fig. 13.15 for the def-initions of and and note that The maximum frequency at which an inverter can be switched A metric that combines speed of operation and power dis-sipation is the power–delay product, The lower the PDP, the more effective the logic-circuit family is. If dynamic power is dominant, such as in CMOS, , which is the energy drawn from the supply for a 0-to-1 and a 1-to-0 transition. (i.e., one switching cycle).
Besides speed of operation and power dissipation, the sil-icon area required for an inverter is the third significant metric in digital IC design.
Predominantly because of its low power dissipation and because of its scalability, CMOS is by far the most dom-inant technology for digital IC design. This situation is expected to continue for many years to come.
Table 13.3 provides a summary of the important charac-teristics of the CMOS inverter.
Digital ICs usually utilize the minimum channel length of the technology available. Thus for the CMOS inverter, and have If matching is desired, is selected equal to at the expense of increased area and capacitance. For minimum area, . Also, a frequently used compromise is . For minimum area, is selected equal to 1. How-ever, to reduce especially when a major part of C is ex-trinsic to the inverter, and correspondingly can be increased.
A CMOS logic gate consists of an NMOS pull-down net-work (PDN) and a PMOS pull-up network (PUN). The PDN conducts for every input combination that requires a low output. Since an NMOS transistor conducts when its input is high, the PDN is most directly synthesized from the expression for the low output as a function of the uncomplemented inputs. In a complementary fashion, the PUN conducts for every input combination that corre-sponds to a high output. Since a PMOS conducts when its input is low, the PUN is most directly synthesized from the expression for a high output (Y) as a function of the complemented inputs.
CMOS logic circuits are usually designed to provide equal current-driving capability in both directions. Fur-thermore, the worst-case values of the pull-up and pull-down currents are made equal to those of the basic invert-er. Transistor sizing is based on this principle and makes use of the equivalent W/L ratios of series and parallel de-vices (Eqs. 13.88 and 13.89).
Refer to Table 13.2 for the implications of scaling the di-mension of the MOSFET and and by a factor .
In devices with short channels velocity saturation occurs. Its effect is that saturates early, and its value is lower than would be the case in long-channel devices (see Figs. 13.40, 13.41 and 13.42, and Eq.
13.100).
NMH VOH VIH – = NML VIL VOL, – = Pdyn fCVDD 2 .
= tP.
tPLH tPHL, tP 1 2 --- tPLH tPHL + ( ).
= fmax 1 2tP ⁄ .
= PDP PDtP.
= PDP CVDD 2 = QN QP L Lmin.
= Wp Wn ⁄ μ n μ p ⁄ .
Wp Wn = Wp 2Wn = W L ⁄ ( )n tP W L ⁄ ( )n W L ⁄ ( )p Y ( ) VDD Vt 1 S ⁄ L 0.25 μm < ( ) iD 13.5 Implications of Technology Scaling: Issues in Deep-Submicron Design 1133 Table 13.3 Summary of Important Characteristics of the CMOS Logic Inverter Inverter Output Resistance When vO is low (current sinking): When vO is high (current sourcing): Inverter VTC and Noise Margins where For matched devices, that is, Propagation Delay (Fig. 13.22) Using average currents: where where Using equivalent resistances (Fig. 13.23): where where QP QN VDD vI vO rDSP rDSN SP SN VDD vO rDSN 1 kn ′ W L -----⎝ ⎠ ⎛ ⎞ n VDD Vtn – ( ) = rDSP 1 kp ′ W L -----⎝ ⎠ ⎛ ⎞ p VDD Vtp – ( ) = Slope 1 Slope 1 Slope 1 Vt VM VIL VOL 0 NMH VIH VDD VOH VDD vI vO 0 2 VDD NML VM r VDD Vtp – ( ) Vtn + 1 r + -----------------------------------------------= r kp ′ W L ⁄ ( )p kn ′ W L ⁄ ( )n --------------------------= μn W L -----⎝ ⎠ ⎛ ⎞ n μp W L -----⎝ ⎠ ⎛ ⎞ p : = VM VDD 2 ⁄ = VIL 1 8 -- 3VDD 2Vt + ( ) = VIH 1 8 --- 5VDD 2Vt – ( ) = NMH NML 1 8 -- 3VDD 2Vt + ( ) = = tPHL αnC kn ′ W L ⁄ ( )nVDD ------------------------------------αn 2 7 4 ---3Vtn VDD ----------– Vtn VDD ---------⎝ ⎠ ⎛ ⎞ 2 + = tPLH αpC kp ′ W L ⁄ ( )pVDD ------------------------------------αp 2 7 4 ---3 Vtp VDD -------------– Vtp VDD ----------⎝ ⎠ ⎛ ⎞ 2 + = tPHL 0.69RNC = RN 12.5 W L ⁄ ( )n ------------------- kΩ = tPLH 0.69RPC = RP 30 W L ⁄ ( )p ------------------- kΩ = PROBLEMS Problems identified by this icon are intended to demon-strate the value of using SPICE simulation to verify hand analysis and design, and to investigate important issues such as gate noise margins and propagation delays. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can be found in the corresponding files on the CD. Note that if a particular parameter value is not speci-fied in the problem statement, you are to make a reasonable assumption. difficult problem; more difficult; very challenging and/or time-consuming; D: design problem.
Section 13.1: Digital Logic Inverters 13.1 A particular logic inverter is specified to have VIL = 1.2 V, VIH = 1.5 V, VOL = 0.2 V, and VOH = 2.5 V. Find the high and low noise margins, NMH and NML.
13.2 The voltage-transfer characteristic of a particular logic inverter is modeled by three straight-line segments in the manner shown in Fig. 13.3. If VIL = 2.0 V, VIH = 2.5 V, VOL = 0.5 V, and VOH = 5 V, find: (a) The noise margins (b) The value of VM (c) The voltage gain in the transition region 13.3 For a particular inverter design using a power supply VDD, VOL = 0.1VDD, VOH = 0.8VDD, VIL = 0.4VDD, and VIH = 0.6VDD. What are the noise margins? What is the width of the transition region? For a minimum noise margin of 1 V, what value of VDD is required?
13.4 A logic circuit family that used to be very popular is transistor-transistor logic (TTL). The TTL logic gates and other building blocks are available commercially in small-scale integrated (SSI) and medium-scale-integrated (MSI) packages. Such packages can be assembled on printed-cir-cuit boards to implement a digital system. The device data sheets provide the following specifications of the basic TTL inverter (of the SN7400 type): Logic-1 input level required to ensure a logic-0 level at the output: MIN (minimum) 2 V Logic-0 input level required to ensure a logic-1 level at the output: MAX (maximum) 0.8 V Logic-1 output voltage: MIN 2.4 V, TYP (typical) 3.3 V Logic-0 output voltage: TYP 0.22 V, MAX 0.4 V Logic-0-level supply current: TYP 3 mA, MAX 5 mA Logic-1-level supply current: TYP 1 mA, MAX 2 mA Propagation delay time to logic-0 level (tPHL): TYP 7 ns, MAX 15 ns Propagation delay time to logic-1 level (tPLH): TYP 11 ns, MAX 22 ns (a) Find the worst-case values of the noise margins.
(b) Assuming that the inverter is in the 1-state 50% of the time and in the 0-state 50% of the time, find the average static power dissipation in a typical circuit. The power sup-ply is 5 V.
(c) Assuming that the inverter drives a capacitance CL = 45 pF and is switched at a 1-MHz rate, use the formula in Eq. (13.35) to estimate the dynamic power dissipation.
(d) Find the propagation delay tP.
13.5 Consider an inverter implemented as in Fig. 13.7(a). Let VDD = 5 V, R = 1.8 kΩ, Ron = 200 Ω, VIL = 1 V, and VIH = 2 V.
(a) Find VOL, VOH, NMH, and NML.
(b) The inverter is driving N identical inverters. Each of these load inverters, or fan-out inverters as they are usually called, is specified to require an input current of 0.2 mA when the input voltage (of the fan-out inverter) is high and zero current when the input voltage is low. Noting that the input currents of the fan-out inverters will have to be sup-plied through R of the driving inverter, find the resulting value of VOH and of NMH as a function of the number of fan-out inverters N. Hence find the maximum value N can have while the inverter is still providing an NMH value approxi-mately equal to its NML.
(c) Find the static power dissipation in the inverter in the two cases: (i) the output is low, and (ii) the output is high and driving the maximum fan-out found in (b).
13.6 For a logic-circuit family employing a 3-V supply, suggest an ideal set of values for VM, VIL, VIH, VOL, VOH, NML, NMH. Also, sketch the VTC. What value of voltage gain in the transition region does your ideal specification imply?
13.7 For a particular logic-circuit family, the basic technology used provides an inherent limit to the small-signal low-frequency voltage gain of 50 V/V. If, with a 3.3-V supply, the values of VOL and VOH are ideal, but = 0.4VDD, what are the best possible values of VIL and VIH that can be expected? What are the best possible noise margins you could expect? If the actual noise margins are only of these values, what VIL and VIH result? What is the large-signal voltage gain [defined as ]. (Hint: Use straight-line approxi-mations for the VTC.) 13.8 A logic-circuit family intended for use in a digital-signal-processing application in a newly developed hear-ing aid can operate down to single-cell supply voltages of 1.2 V. If for its inverter, the output signals swing between 0 and VDD, the “gain-of-one” points are separated by less than VDD, and the noise margins are within 30% of one another, what ranges of values of VIL, VIH, VOL, VOH, NML, and NMH can you expect for the lowest possible battery supply?
D 13.9 Design the inverter circuit in Fig. 13.2(a) to pro-vide and so that the current VM 7 10 ⁄ (VOH VOL) – (VIL VIH) – ⁄ 1 3 ---VOH 2 V, = VOL 0.1 V, = Problems 1135 CHAPTER 13 PR OBLEM S drawn from the supply in the low-output state is 20 μA. The transistor has , and . Specify the required values of , and W/L.
How much power is drawn from the supply when the output is high? When the output is low?
13.10 For the current-steering circuit in Fig. 13.9, , , find the values of and to obtain a voltage swing of 1.5 V at each output. What are the values realized for and ?
D 13.11 Refer to the analysis of the resistive-load MOS inverter in Example 13.1 and utilize the expressions derived there for the various inverter parameters. Design the circuit to satisfy the following requirements: , and the power dissipation in the low-output state = 125 μW. The transistor available has and Specify the required values of , , and W/L. What are the values obtained for , , , , and ?
D 13.12 Refer to the analysis of the resistive-load MOS inverter in Example 13.1 and utilize the expressions derived there for the various inverter parameters. For a technology for which , it is required to design the inverter to obtain . In terms of , what is the required value of the design parameter ? What values are obtained for , , , , , and , in terms of ? Give numerical values for the case .
Now, express the power dissipated in the inverter in its low-output state in terms of the transistor’s W/L ratio. Let . If the power dissipation is to be limited to approximately 100 μW, what W/L ratio is needed and what value of corresponds?
13.13 Consider the saturated-load inverter of Fig. 13.11(a), analyzed in Example 13.2. From Eq. (13.20), where is given by For , 0.8 V, use an iterative process to determine and By how much is reduced as a result of the body effect on ?
13.14 Determining of the saturated-load inverter of Fig. 13.11(a) requires a rather tedious process (see Example 13.2). An approximate estimate of can be obtained by reference to the VTC shown in Fig. 13.11(d). Specifically, when the straight-line segment BC is extrapolated, it meets the horizontal axis at which is usually close to the value of What is the approximate value obtained this way for the case analyzed in Example 13.2?
How much does it differ from the value calculated the long way in Example 13.2?
D 13.15 It is required to design the saturated-load inverter in Fig. 13.11(a) for the case , , , and . Design for . Utilize the expressions derived in Example 13.2, except for use the following approximate expres-sion (see Problem 13.11): Neglect the body effect in . Determine , , and for your design. Also determine and assuming that . What is the power dissipated in the inverter during its low-output state? 13.16 An IC inverter fabricated in a 0.25-μm CMOS pro-cess is found to have a load capacitance of 10 fF. If the inverter is operated from a 2.5-V power supply, find the energy needed to charge and discharge the load capacitance.
If the IC chip has 1 million of these inverters operating at an average switching frequency of 1 GHz, what is the power dissipated in the chip? What is the average current drawn from the power supply?
13.17 Consider a logic inverter of the type shown in Fig. 13.8.
Let VDD = 5 V, and let a 1-pF capacitance be connected between the output node and ground. If the inverter is switched at the rate of 100 MHz, determine the dynamic power dissipation. What is the average current drawn from the dc power supply?
13.18 In a particular logic family, operating with a 3.3-V supply, the basic inverter draws (from the supply) a current of 40 μA in one state and 0 μA in the other. When the inverter is switched at the rate of 100 MHz, the average sup-ply current becomes 150 μA. Estimate the equivalent capac-itance at the output node of the inverter.
13.19 A collection of logic gates for which the static-power dissipation is zero, and the dynamic-power dissipation is 10 mW is operating at 50 MHz with a 5-V supply. By what fraction could the power dissipation be reduced if operation at 3.3 V were possible? If the frequency of operation is reduced by the same factor as the supply voltage (i.e., ), what additional power can be saved?
13.20 A logic inverter is implemented using the arrange-ment of Fig. 13.8 with switches having Ron = 1 kΩ, VDD = 5 V, and (a) Find VOL, VOH, NML, and NMH.
(b) If vI rises instantaneously from 0 V to +5 V and assum-ing the switches operate instantaneously—that is, at t = 0, Vt 0.5 V = μ nCox 100 μA V2 ⁄ , = λ 0 = VDD RD, VCC 3 V = IEE 1 mA = RC1 RC2 VOH VOL VOH 2.5 V; = VOL 0.1 V = Vt 0.5 V, = μnCox 100 μA V2, ⁄ = λ 0.
= VDD RD VIL VM VIH NML NMH Vt 0.2VDD = VM VDD 2 ⁄ = VDD Vx VOH VOL VIL VIH NMH NML VDD VDD 2.5 V = kn′ 100 μA V2 ⁄ = RD VOH VDD Vt2 – = Vt2 Vt2 Vt0 γ VOH 2φf + 2φf – [ ] + = Vt0 0.5 V = VDD 1.8 V, = γ 0.3 V1 2 ⁄ , = 2φf = Vt2 VOH.
VOH Q2 VIH VIH VM VM kr ⁄ + ( ), VIH.
VDD 2.5 V = Vt 0.5 V = kn ′ 100 μA V2 ⁄ = λ 0 = VOL 0.05 V VIH VIH VM VM kr -------+ Q2 VM NML NMH W L ⁄ ( )1 W L ⁄ ( )2 W L ⁄ ( )2 1 W L ⁄ ( ) ⁄ 1 = 3.3 5 ⁄ VIL V = IH V = DD 2.
⁄ CHAPTER 13 PR OBLE MS 1136 Chapter 13 CMOS Digital Logic Circuits PU opens and PD closes—find an expression for vO(t), assuming that a capacitance C is connected between the out-put node and ground. Hence find the high-to-low propaga-tion delay (tPHL) for C = 1 pF. Also find tTHL (see Fig. 13.15).
(c) Repeat (b) for vI falling instantaneously from +5 V to 0 V. Again assume that PD opens and PU closes instanta-neously. Find an expression for vO(t), and hence find tPLH and tTLH.
13.21 In a particular logic family, the standard inverter, when loaded by a similar circuit, has a propagation delay specified to be 1.2 ns: (a) If the current available to charge a load capacitance is half as large as that available to discharge the capacitance, what do you expect tPLH and tPHL to be?
(b) If when an external capacitive load of 1 pF is added at the inverter output, its propagation delays increase by 70%, what do you estimate the normal combined capacitance of inverter output and input to be?
(c) If without the additional 1-pF load connected, the load inverter is removed and the propagation delays were observed to decrease by 40%, estimate the two compo-nents of the capacitance found in (b) that is, the compo-nent due to the inverter output and other associated parasitics, and the component due to the input of the load inverter.
13.22 Consider an inverter for which tPLH, tPHL, tTLH, and tTHL are 20 ns, 10 ns, 30 ns, and 15 ns, respectively. The ris-ing and falling edges of the inverter output can be approxi-mated by linear ramps. Also, for simplicity, we define tTLH to be 0% to 100% (rather than 10% to 90%) rise time, and similarly for tTHL. Two such inverters are connected in tan-dem and driven by an ideal input having zero rise and fall times. Calculate the time taken for the output voltage to complete its excursion for (a) a rising input and (b) a falling input. What is the propagation delay for the inverter?
13.23 A particular logic gate has tPLH and tPHL of 50 ns and 70 ns, respectively, and dissipates 1 mW with output low and 0.5 mW with output high. Calculate the corre-sponding delay–power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation).
D 13.24 We wish to investigate the design of the inverter shown in Fig. 13.7(a). In particular, we wish to determine the value for R. Selection of a suitable value for R is deter-mined by two considerations: propagation delay and power dissipation.
(a) Show that if vI changes instantaneously from high to low and assuming that the switch opens instantaneously, the out-put voltage obtained across a load capacitance C will be where Hence show that the time required for vO(t) to reach the 50% point, is tPLH = 0.69CR (b) Following a steady state, if vI goes high and assuming that the switch closes immediately and has the equivalent circuit in Fig. 13.7(c), show that the output falls exponentially according to where . Hence show that the time for vO(t) to reach the 50% point is tPHL = 0.69CRon (c) Use the results of (a) and (b) to obtain the inverter prop-agation delay, defined as the average of tPLH and tPHL as (d) Show that for an inverter that spends half the time in the 0-state and half the time in the 1-state, the average static power dissipation is (e) Now that the trade-offs in selecting R should be clear, show that, for VDD = 5 V and C = 10 pF, to obtain a propaga-tion delay no greater than 10 ns and a power dissipation no greater than 10 mW, R should be in a specific range. Find that range and select an appropriate value for R. Then deter-mine the resulting values of tP and P.
D 13.25 A logic-circuit family with zero static-power dissipation, normally operates at VDD = 5 V. To reduce its dynamic-power dissipation operation at 3.3 V is consid-ered. It is found, however, that the currents available to charge and discharge load capacitances also decrease. If current is (a) proportional to VDD or (b) proportional to , what reductions in maximum operating frequency do you expect in each case? What fractional change in delay– power product do you expect in each case?
Section 13.2: The CMOS Inverter 13.26 Consider a CMOS inverter fabricated in a 0.25-μm CMOS process for which , and . In addition, and have L = 0.25 μm and . (a) Find that results in . What is the sili-con area utilized by the inverter in this case?
vO t ( ) VOH VOH VOL – ( )e t τ1 ⁄ – – = τ1 CR.
= 1 2 -- VOH VOL + ( ), vO t ( ) VOL VOH VOL – ( )e t – τ2 ⁄ + = τ2 C R Ron || ( ) CRon for Ron R ( ) = tP 0.35CR for Ron · R P 1 2 ---V 2 DD R ------------= VDD 2 VDD 2.5 V = Vtn = Vtp 0.5 V, = – μ nCox 3.5μpCox = = 115 μA V2 ⁄ QN QP W L ⁄ ( )n 1.5 = Wp VM VDD 2 ⁄ = PROBLEMS Problems 1137 CHAPTER 13 PR OBLEM S (b) For the matched case in (a), find the values of , and (c) For the matched case in (a), find the output resistance of the inverter in each of its two states.
13.27 For the technology specified in Problem 13.26, investigate the variation of with the ratio . Spe-cifically, calculate for (a) (the matched case); (b) (the minimum-size case); and (c) (a compromise case). For cases (b) and (c), esti-mate the approximate reduction in and silicon area relative to the matched case (a).
13.28 For a technology in which show that the maximum current that the inverter can sink while its low-output level does not exceed 0.1 is 0.075 For , find that permits this maximum current to be 0.5 mA.
13.29 A CMOS inverter for which and Vt = 0.5 V is connected as shown in Fig. P13.29 to a sinusoidal signal source having a Thévenin equivalent volt-age of 0.1-V peak amplitude and resistance of 100 kΩ. What signal voltage appears at node A with vI = +1.5 V? With vI = −1.5 V?
D 13.30 There are situations in which and of the CMOS inverter are deliberately mismatched to realize a cer-tain desired value for . Show that the value required of the parameter r of Eq. (13.59) is given by For a 0.18-μm process characterized by , , and , find the ratio required to obtain .
13.31 Consider the CMOS inverter of Fig. 13.17 with and matched and with the input rising slowly from 0 to . At what value of does the current flowing through and reach its peak? Give an expression for the peak current, neglecting and For , , and , find the value of the peak current.
13.32 For a CMOS inverter fabricated in a 0.13-μm process with , , , and having and , find , , and when the equiva-lent load capacitance C = 10 fF. Use the method of average currents.
D 13.33 Consider a matched CMOS inverter fabricated in the 0.13-μm process specified in Problem 13.32. If C = 20 fF, use the method of average currents to determine the required (W/L) ratios so that . 13.34 For the CMOS inverter in Exercise 13.14 use the method of equivalent resistance to determine and 13.35 Use the method of equivalent resistance to deter-mine the propagation delay of a minimum-size inverter, that is, one for which , designed in a 0.18-μm technology. The equivalent load capacitance C = 10 fF. D 13.36 Use the method of equivalent resistance to design an inverter to be fabricated in a 0.18-μm technology. It is required that for C = 10 fF, and .
13.37 The method of average currents yields smaller val-ues for and than those obtained by the method of equivalent resistances. Most of this discrepancy is due to the fact that the formula we derived for does not take into account velocity saturation. As will be seen in Section 13.5.2, velocity saturation reduces the current significantly.
Using the results in Example 13.5, by what factor do you estimate the current reduction to be in the NMOS transistor?
Since does not change, what do you conclude about the effect of velocity saturation on the PMOS transistor in this technology?
13.38 Find the propagation delay for a minimum-size inverter for which and ( )n = VDD = 3.3 V, Vtn = –Vtp = 0.7 V, and the capacitance is roughly 2 fF/μm of device width plus 1 fF/device. What does tP become if the design is changed to a matched one? Use the method of average current.
13.39 A matched CMOS inverter fabricated in a process for which Cox = 3.7 fF/μm2, μnCox = 180 μA/V2, μpCox = 45 μA/V2, = − = 0.7 V, and VDD = 3.3 V, uses Wn = 0.75 μm and Ln = Lp = 0.5 μm. The overlap capacitance and the effective drain–body capacitance per micrometer of gate width are 0.4 fF and 1.0 fF, respectively. The wiring capacitance is VOH, VOL VIH, VIL, NML, NMH.
VM Wp Wn ⁄ VM Wp 3.5Wn = Wp Wn = Wp 2Wn = NML Vtn 0.2VDD, = VDD kn′ W L ⁄ ( )nVDD 2 .
VDD 2.5 V, = kn′ = 115 μA V2 ⁄ W L ⁄ ( )n kn = 10kp = 100 μA/V 2 QP A 100-mV signal 100 k QN vI Figure P13.29 QN QP VM r VM Vtn – VDD Vtp – VM – ---------------------------------------= Vtn Vtp 0.5 V = – = VDD 1.8 V = μn 4μp = Wp Wn ⁄ VM 0.6VDD = QN QP vI VDD vI QN QP λn λp.
kn′ 300 μA V2 ⁄ = W L ⁄ ( )n 1.5 = VDD 1.8 V, = Vtn 0.5 V = VDD 1.2 V = Vtn Vtp 0.4 V = – = kn′ 4kp ′ 430 μ = A V2 ⁄ = W L ⁄ ( )n 1.5 = W L ⁄ ( )p 3 = tPHL tPLH tP tP 20 ps ≤ tPHL, tPLH, tP.
W L ⁄ ( )n W L ⁄ ( )p 1 = = tPLH tPHL, = tP 40 ps ≤ tPHL tPLH Iav tPLH kn ′ = 3k′ p = 180 μA/V 2 W L ⁄ (W L)p ⁄ 0.75 μm 0.5 ⁄ μm, = V tn Vtp CHAPTER 13 PR OBLE MS 1138 Chapter 13 CMOS Digital Logic Circuits Cw = 2 fF. If the inverter is driving another identical inverter, find tPLH, tPHL, and tP. For how much additional capacitance load does the propagation delay increase by 50%?
D 13.40 In this problem we investigate the effect of the selection of the ratio on the propagation delay of an inverter driving an identical inverter, as in Fig. 13.24.
(a) Noting that except for each of the capacitances in Eqs. (13.72) and (13.73) is proportional to the width of the relevant transistor, show that C can be expressed as where is determined by the NMOS transistors.
(b) Using the equivalent resistances and , show that for , (c) Use the results of (a) and (b) to determine in the case , in terms of and .
(d) Use the results of (a) and (b) to determine in the matched case: that is, when is selected to yield .
(e) Compare the values in (c) and (d) for the two extreme cases: (i) (ii) What do you conclude about the selection of ?
13.41 An inverter whose equivalent load capacitance C is composed of 10 fF contributed by the inverter transistors, and 20 fF contributed by the wiring and other external cir-cuitry, has been found to have a propagation delay of 60 ps.
By what factor must and be increased so as to reduce to 30 ps?
13.42 A CMOS microprocessor chip containing the equiv-alent of 1 million gates operates from a 5-V supply. The power dissipation is found to be 9 W when the chip is oper-ating at 120 MHz, and 4.7 W when operating at 50 MHz.
What is the power lost in the chip by some clock-indepen-dent mechanism, such as leakage and other static currents?
If 70% of the gates are assumed to be active at any time, what is the average gate capacitance in such a design?
13.43 Repeat Problem 13.39 for an inverter for which Find tP and the dynamic power dissipation when the circuit is operated at a 250-MHz rate.
13.44 In this problem we estimate the inverter power dissi-pation resulting from the current pulse that flows in and when the input pulse has finite rise and fall times. Refer to Fig. 13.26 and let , and . Let the input rising and fall-ing edges be linear ramps with the 0-to- and -to-0 transitions taking 1 ns each. Find To determine the energy drawn from the supply per transition, assume that the current pulse can be approximated by a triangle with a base corresponding to the time for the rising or falling edge to go from to , and the height equal to Also, determine the power dissipation that results when the inverter is switched at 100 MHz.
Section 13.4: CMOS Logic-Gate Circuits D 13.45 Sketch a CMOS realization for the function .
D 13.46 A CMOS logic gate is required to provide an out-put . How many transistors does it need? Sketch a suitable PUN and PDN, obtaining each first independently, then one from the other using the dual-networks idea.
D 13.47 Give two different realizations of the exclusive OR function in which the PDN and the PUN are dual networks.
D 13.48 Sketch a CMOS logic circuit that realizes the function . This is called the equivalence or coincidence function.
D 13.49 Sketch a CMOS logic circuit that realizes the function .
D 13.50 It is required to design a CMOS logic circuit that realizes a three-input, even-parity checker. Specifically, the output Y is to be low when an even number (0 or 2) of the inputs A, B, and C are high.
(a) Give the Boolean function (b) Sketch a PDN directly from the expression for Note that it requires 12 transistors in addition to those in the invert-ers.
(c) From inspection of the PDN circuit, reduce the number of transistors to 10.
(d) Find the PUN as a dual of the PDN in (c), and hence the complete realization.
D 13.51 Give a CMOS logic circuit that realizes the function of three-input, odd-parity checker. Specifically, Wp Wn ⁄ Cw C Cn 1 Wp Wn -------+ ⎝ ⎠ ⎛ ⎞ Cw + = Cn RN RP W L ⁄ ( )n 1 = tPHL 8.625 103 × C = tPLH 20.7 103 × Wp Wn ⁄ -------------------------C = tP Wp Wn = Cn Cw tP Wp Wn ⁄ tPHL t = PLH tP Cw 0 = Cw Cn Wp Wn ⁄ W L ⁄ ( )n W L ⁄ ( )p tP (W L)n ⁄ = (W L)p ⁄ = 0.75 μm 0.5 ⁄ μm.
QN QP Vtn Vtp 0.5 V = – = VDD 1.8 V, = kn kp 450 μ = A V2 ⁄ = VDD VDD Ipeak.
Vt VDD Vt – Ipeak.
Y A B C D + ( ) + = Y ABC ABC ABC + + = Y AB AB + = Y AB AB + = Y ABC ABC + = Y.
Y.
Problems 1139 CHAPTER 13 PR OBLEM S the output is to be high when an odd number (1 or 3) of the inputs are high. Attempt a design with 10 transistors (not counting those in the inverters) in each of the PUN and the PDN.
D 13.52 Design a CMOS full-adder circuit with inputs A, B, and C, and two outputs S and C0 such that S is 1 if one or three inputs are 1, and C0 is 1 if two or more inputs are 1.
D 13.53 Consider the CMOS gate shown in Fig. 13.33.
Specify ratios for all transistors in terms of the ratios n and p of the basic inverter, such that the worst-case tPHL and tPLH of the gate are equal to those of the basic inverter.
D 13.54 Find appropriate sizes for the transistors used in the exclusive-OR circuit of Fig. 13.34(b). Assume that the basic inverter has and What is the total area, including that of the required inverters?
13.55 Consider a four-input CMOS NAND gate for which the transient response is dominated by a fixed-size capaci-tance between the output node and ground. Compare the val-ues of tPLH and tPHL, obtained when the devices are sized as in Fig. 13.36, to the values obtained when all n-channel devices have = n and all p-channel devices have = p.
13.56 Figure P13.56 shows two approaches to realizing the OR function of six input variables. The circuit in Fig.
P13.56(b), though it uses additional transistors, has in fact less total area and lower propagation delay because it uses NOR gates with lower fan-in. Assuming that the transistors in both circuits are properly sized to provide each gate with a current-driving capability equal to that of the basic matched inverter, find the number of transistors and the total area of each circuit. Assume the basic inverter to have a ( )n ratio of and a ( )p ratio of 13.57 Consider the two-input CMOS NOR gate of Fig. 13.31 whose transistors are properly sized so that the current-driving capability in each direction is equal to that of a matched inverter. For and VDD = 5 V, find the gate threshold in the cases for which (a) input terminal A is connected to ground and (b) the two input terminals are tied together. Neglect the body effect in QPB.
Section 13.5: Implications of Technology Scal-ing: Issues in Deep-Submicron Design 13.58 A chip with a certain area designed using the 10-μm process of the early 1970s contains 10,000 transistors. What does Moore’s law predict the number of transistors to be on a chip of equal area fabricated using the 45-nm process of 2009?
13.59 Consider the scaling from a 0.18-μm process to a 45-nm process.
(a) Assuming and are scaled by the same factor as the device dimensions , find the factor by which the maximum operating speed, power density, and PDP decrease (or increase)?
(b) Repeat (a) for the situation in which and are scaled by a factor of only 2.
13.60 For a 0.18-μm technology, for minimum-length NMOS devices is measured to be 0.6 V and that for minimum-length PMOS devices 1.0 V. What do you esti-mate the effective values of and to be? Also find the values of for both device polarities.
W L ⁄ (W L)n ⁄ 0.27 μm 0.18 ⁄ μm = (W L)p ⁄ = 0.54 μm 0.18 ⁄ μm.
W L ⁄ W L ⁄ W L ⁄ 0.27 μm 0.18 ⁄ μm W L ⁄ 0.54 μm 0.18 ⁄ μm.
A1 A6 Y A1 A2 A6 … … (a) A4 A6 A5 A1 A3 A2 Y A1 A2 A6 … (b) Figure P13.56 Vt = 1 V VDD Vt S 4 = ( ) tP, Pdyn, VDD Vt VDSsat μ n μp Ecr CHAPTER 13 PR OBLE MS 1140 Chapter 13 CMOS Digital Logic Circuits 13.61 Consider NMOS and PMOS transistors with mini-mum channel length fabricated in a 0.13-μm CMOS pro-cess. If the effective values of and are 325 and 200 , respectively, find the expected values of for both device polarities.
13.62 (a) Show that for short-channel NMOS transistor, the ratio of the current obtained at to the current obtained if velocity saturation were absent is given by (b) Find the ratio in (a) for a transistor fabricated in a 0.13-μm process with L = 0.13 μm, , , and .
13.63 (a) Consider a CMOS inverter fabricated in a deep-submicron technology utilizing transistors with the mini-mum allowed channel length and having an equivalent load capacitance C. Let rise instantaneously to and assume that turns off and turns on immediately.
Ignoring channel-length modulation, that is, , and assuming operates in the velocity-saturation region, show that (b) Using the equivalent resistance of show that (c) If the formulas in (a) and (b) are to yield the same result, find for the NMOS transistor for a 0.13-μm technol-ogy characterized by , , and . D 13.64 (a) For a CMOS inverter fabricated in a deep-sub-micron technology with = the minimum allowed channel length, it is required to select so that . This can be achieved by making of equal to of at Show that is given by (b) Find the required for a 0.13-μm technology for which , , , and .
D 13.65 The current in the subthreshold conduction Eq. (13.102) is proportional to . If the threshold voltage of an NMOS transistor is reduced by 0.1 V, by what factor will the static power dissipation increase? Repeat for a reduction in by 0.2 V. What do you conclude about the selection of a value of in process design?
μ n μ p cm2 V s ⋅ ⁄ cm2 V s ⋅ ⁄ VDSsat IDsat vGS VDD = IDsat ID ----------2VDSsat VDD Vt – 1 2 ---VDSsat – ⎝ ⎠ ⎛ ⎞ VDD Vt – ( )2 --------------------------------------------------------------------= Vt 0.4 V = VDSsat 0.34 V = VDD 1.2 V = vI VDD QP QN λ 0 = QN tPHL CVDD 2IDsat --------------= QN tPHL 0.69C 12.5 103 × W L ⁄ ( )n -------------------------= VDSsat VDD 1.2 V = Vt 0.4 V = μ nCox 325 μA V2 ⁄ = Ln Lp = Wp Wn ⁄ tPHL tPLH = IDsat QN IDsat QP vGS VDD.
= Wp Wn ⁄ Wp Wn -------μ n μ p ----- VDSsatn VDSsatp -------------------VDD Vtn – 1 2 ---VDSsatn – VDD Vtp – 1 2 --- VDSsatp – -------------------------------------------------------= Wp Wn ⁄ μn μp 4 = ⁄ VDD 1.2 V = Vtn Vtp 0.4 V, = – = VDSsatn 0.34 V = VDSsatp 0.6 V = IS e Vt nVT ⁄ – Vt Vt Problems 1141 CHAPTER 13 PR OBLEM S 13.66 An interconnect wire with a length L, a width W, and a thickness T has a resistance R given by where is the resistivity of the material of which the wire is made. The quantity is called the sheet resistance and has the dimension of ohms, although it is usually expressed as ohms/square or (refer to Fig. P13.66a).
(a) Find the resistance of an aluminum wire that is 10 mm long and 0.5 μm wide, if the sheet resistance is specified to be 27 .
(b) If the wire capacitance to ground is 0.1 fF/μm length, what is the total wire capacitance?
(c) If we can model the wire very approximately as an RC circuit as shown in Fig. P13.66(b), find the delay time intro-duced by the wire. (Hint: .) (P.S. Only a small fraction of the interconnect on an IC would be this long!) R ρL A ---ρL TW --------= = ρ ρ T ⁄ Ω ⁄ mΩ ⁄ tdelay 0.69RC = L (a) W W T Square R C (b) Figure P13.66 CHAPTER 14 Advanced MOS and Bipolar Logic Circuits Introduction 1143 14.1 Pseudo-NMOS Logic Circuits 1144 14.2 Pass-Transistor Logic Circuits 1152 14.3 Dynamic MOS Logic Circuits 1166 14.4 Emitter-Coupled Logic (ECL) 1175 14.5 BiCMOS Digital Circuits 1189 Summary 1195 Problems 1196 1143 IN THIS CHAPTER YOU WILL LEARN 1. That by replacing the pull-up network (PUN) of a CMOS logic gate by a single, permanently-on PMOS transistor, considerable savings in transis-tor count and silicon area can be achieved in gates with high fan-in. The resulting circuits are known as pseudo-NMOS.
2. That a useful and conceptually simple form of MOS logic circuits, known as pass-transistor logic (PTL), utilizes MOS transistors as series switches in the signal path from input to output.
3. That a very effective switch for both analog and digital applications, known as transmission gate, is formed by connecting an NMOS and a PMOS transistor in parallel.
4. That eliminating the pull-up network and placing two complementary switches, operated by a clock signal, in series with the pull-down net-work of a CMOS gate, results in an interesting and useful class of circuits known as dynamic logic.
5. How the BJT differential-pair configuration is used as a current switch to realize the fastest commercially available logic-circuit family: emitter-coupled logic (ECL).
6. How the MOSFET and the BJT are combined in BiCMOS circuits in ways that take advantage of the best attributes of each device.
Introduction Standard CMOS logic, which we studied in Chapter 13, excels in almost every performance category: It is easy to design, has the maximum possible voltage swing, is robust from a noise-immunity standpoint, dissipates no static power, and can be designed to provide equal high-to-low and low-to-high propagation delays. Its main disadvantage is the requirement of two transistors for each additional gate input, which for gates with high fan-in can make the chip area large and increase the total capacitance and, correspondingly, the propagation delay and the dynamic power dissipation. For this reason designers of digital integrated cir-cuits have been searching for forms of CMOS logic circuits that can be used to supplement standard CMOS. This chapter presents three such forms that reduce the required number of transistors but incur other costs. These forms are not intended to replace standard CMOS, but are rather to be used in special applications for special purposes.
1144 Chapter 14 Advanced MOS and Bipolar Logic Circuits Pseudo-NMOS logic, studied in Section 14.1, replaces the pull-up network (PUN) in a CMOS logic gate by a single permanently “on” PMOS transistor. The reduction in transistor count and silicon area comes at the expense of static power dissipation. As well, the output low level VOL becomes dependent on the transistors’ W/L ratios.
Pass-transistor logic (PTL), studied in Section 14.2, utilizes MOS transistors as switches in the series path from input to output. Though simple and attractive for special applications, PTL does not restore the signal level and thus requires the occasional use of standard CMOS inverters to avoid signal-level degradation, especially in long chains of switches.
The dynamic logic circuits studied in Section 14.3 dispense with the PUN and place two complementary switches in series with the PDN. The switches are operated by a clock, and the gate output is stored on the load capacitance. Here the reduction in transistor count is achieved at the expense of a more complex design that is less robust than static CMOS.
Although CMOS accounts for the vast majority of digital integrated circuits, there is a bipolar logic-circuit family that is still of some interest. This is emitter-coupled logic (ECL), which we study in Section 14.4. Finally, in Section 14.5 we show how the MOSFET and the BJT can be combined in ways that take advantage of the best properties of each, resulting in what are known as BiCMOS circuits.
14.1 Pseudo-NMOS Logic Circuits 14.1.1 The Pseudo-NMOS Inverter Figure 14.1 shows a modified form of the CMOS inverter. Here, only QN is driven by the input voltage while the gate of QP is grounded, and QP acts as an active load for QN. Even before we examine the operation of this circuit in detail, an advantage over standard CMOS is obvious: Each input needs to be connected to the gate of only one transistor or, alterna-tively, only one additional transistor (an NMOS) will be needed for each additional gate input. Thus the area and delay penalties arising from increased fan-in in a standard CMOS will be reduced. This is indeed the motivation for exploring this modified inverter circuit.
The inverter circuit of Fig. 14.1(a) resembles other forms of NMOS logic that consist of a driver transistor (QN) and a load transistor (in this case, QP); hence the name pseudo-NMOS.
Figure 14.1 (a) The pseudo-NMOS logic inverter. (b) The enhancement-load (or saturated-load) NMOS inverter. (c) The depletion-load NMOS inverter.
QP QN iDN vO vI iDP VDD (a) Q2 iD2 iD1 Q1 vO vI (b) VDD Q1 iD Q2 vO vI (c) VDD 14.1 Pseudo-NMOS Logic Circuits 1145 For comparison purposes, we shall briefly mention two older forms of NMOS logic. The earliest form, popular in the mid-1970s, utilized an enhancement MOSFET for the load element, in a topology whose basic inverter is shown in Fig. 14.1(b). We studied this inverter circuit in Example 13.2, where we found that it suffers from a relatively small logic swing, small noise margins, and high static power dissipation. For these reasons, this logic-circuit technology is virtually obsolete. It was replaced in the late 1970s and early 1980s with depletion-load NMOS circuits, in which a depletion NMOS transistor (see Section 5.9.6) with its gate connected to its source is used as the load element. The topology of the basic depletion-load inverter is shown in Fig. 14.1(c).
It was initially expected that the depletion NMOS with VGS = 0 would operate as a constant-current source and would thus provide an excellent load element.1 However, it was quickly real-ized that the body effect in the depletion transistor causes its i–v characteristic to deviate con-siderably from that of a constant-current source. Nevertheless, depletion-load NMOS circuits feature significant improvements over their enhancement-load counterparts, enough to justify the extra processing step required to fabricate the depletion devices (namely, ion-implanting the channel). Although depletion-load NMOS has been virtually replaced by CMOS, one can still see some depletion-load circuits in specialized applications. We will not study depletion-load NMOS logic here (the interested reader can refer to the CD or the website of this book).
The pseudo-NMOS inverter that we are about to study is similar to depletion-load NMOS, but with rather improved characteristics. It also has the advantage of being directly compatible with standard CMOS circuits.
14.1.2 Static Characteristics The static characteristics of the pseudo-NMOS inverter can be derived in a manner similar to that used for standard CMOS. Toward that end, we note that the drain currents of QN and QP are given by (14.1) (14.2) (14.3) (14.4) where we have assumed that = − = , and have used = and = to simplify matters.
To obtain the voltage-transfer characteristic of the inverter, we superimpose the load curve represented by Eqs. (14.3) and (14.4) on the iD–vDS characteristics of QN, which can be relabeled as iDN–vO and drawn for various values of vGS = vI. Such a graphical construction is shown in Fig. 14.2, where, to keep the diagram simple, we show the QN curves for only the two extreme values of vI, namely, 0 and VDD. Two observations follow: 1A constant-current load provides a capacitor-charging current that does not diminish as vO rises toward VDD, as is the case with a resistive load. Thus the value of tPLH obtained with a current-source load is significantly lower than that obtained with a resistive load (see Problem 14.1). Of course, a resistive load, such as in the circuit studied in Example 13.1, is simply out of the question because of the very large silicon area it would occupy (equivalent to that of thousands of transistors!).
iDN 1 2 ---kn vI Vt – ( ) 2 for vO vI ≥ − Vt (saturation) , = iDN kn vI Vt – ( )vO 1 2 ---vO 2 – [ ] for vO vI ≤ − Vt (triode) , = iDP 1 2 ---kp VDD Vt – ( ) 2 for vO Vt ≤ (saturation) , = iDP kp VDD Vt – ( ) VDD vO – ( ) − 1 2 --- VDD vO – ( ) 2 [ ] for vO Vt ≥ (triode) , = V tn V tp V t kn k′ n(W L ⁄ )n kp k′ p (W L ⁄ )p 1146 Chapter 14 Advanced MOS and Bipolar Logic Circuits 1. The load curve represents a much lower saturation current (Eq. 14.3) than is repre-sented by the corresponding curve for QN, namely, that for vI = VDD. This is a result of the fact that the pseudo-NMOS inverter is usually designed so that kn is greater than kp by a factor of 4 to 10. As we will show shortly, this inverter is of the so-called ratioed type,2 and the ratio determines all the breakpoints of the VTC, that is, VOL, VIL, VIH, and so on, and thus determines the noise margins. Selection of a relatively high value for r reduces VOL and widens the noise margins.
2. Although one tends to think of QP as acting as a constant-current source, it actually operates in saturation for only a small range of vO, namely, For the remain-der of the vO range, QP operates in the triode region.
Consider first the two extreme cases of vI: When vI = 0, QN is cut off and QP is operating in the triode region, though with zero current and zero drain–source voltage. Thus the operating point is that labeled A in Fig. 14.2, where vO = VOH = VDD, the static current is zero, and the static power dissipation is zero. When vI = VDD, the inverter will operate at the point labeled E in Fig. 14.2. Observe that unlike standard CMOS, here VOL is not zero, an obvious disad-vantage. Another disadvantage is that the gate conducts current (Istat) in the low-output state, and thus there will be static power dissipation 14.1.3 Derivation of the VTC Figure 14.3 shows the VTC of the pseudo-NMOS inverter. As indicated, it has four distinct regions, labeled I through IV, corresponding to the different combinations of possible modes of operation of QN and QP. The four regions, the corresponding transistor modes of opera-tion, and the conditions that define the regions are listed in Table 14.1. We shall utilize the information in this table together with the device equations given in Eqs. (14.1) through (14.4) to derive expressions for the various segments of the VTC and in particular for the important parameters that characterize the static operation of the inverter.
Figure 14.2 Graphical construction to determine the VTC of the inverter in Fig. 14.1(a).
2For the NMOS inverters such as that studied in Example 13.2, VOL depends on the ratio of the transcon-ductance parameters of the devices, that is, on the ratio . Such circuits are therefore known as ratioed logic circuits. Standard CMOS logic circuits do not have such a dependency and can therefore be called ratioless.
vI 0 VOL 0 Istat iDN, iDP vI VDD E A VDDVt VDD vO Vt Load curve r kn kp ⁄ ≡ (k′ (W L ⁄ ))driver (k′ (W L ⁄ ))load ( ⁄ vO Vt.
≤ PD I stat VDD × = ( ).
··· 14.1 Pseudo-NMOS Logic Circuits 1147 Figure 14.3 VTC for the pseudo-NMOS inverter. This curve is plotted for VDD = 5 V, Vtn = −Vtp = 1 V, and r = 9.
Table 14.1 Regions of Operation of the Pseudo-NMOS Inverter Region Segment of VTC QN QP Condition I AB Cutoff Triode II BC Saturation Triode III CD Triode Triode IV DE Triode Saturation 0 1 2 3 4 5 vI(V) vO(V) (vO vI) 2 3 4 5 A 1 Slope 1 Slope 1 VOL VOL Vt VOH VIL VM VIH Vt VOH VDD B C D E Region II Region IV Region III Region I Slope 1 vI Vt < vO vI Vt – ≥ Vt vO vI ≤ Vt – ≤ vO Vt ≤ 1148 Chapter 14 Advanced MOS and Bipolar Logic Circuits Region I (segment AB): (14.5) Region II (segment BC): Equating iDN from Eq. (14.1) and iDP from Eq. (14.4) together with substituting , and with some manipulations, we obtain (14.6) The value of VIL can be obtained by differentiating this equation and substituting and vI = VIL: (14.7) The threshold voltage VM is by definition the value of vI for which vO = vI, (14.8) Finally, the end of the region II segment (point C) can be found by substituting vO = vI − Vt in Eq. (14.6), the condition for QN leaving saturation and entering the triode region.
Region III (segment CD) This is a short segment that is not of great interest. Point D is characterized by vO = Vt.
Region IV (segment DE) Equating iDN from Eq. (14.2) to iDP from Eq. (14.3) and substituting kn = rkp results in (14.9) The value of VIH can be determined by differentiating this equation and setting and (14.10) The value of VOL can be found by substituting vI = VDD into Eq. (14.9), (14.11) The static current conducted by the inverter in the low-output state is found from Eq. (14.3) as (14.12) Finally, we can use Eqs. (14.7) and (14.11) to determine NML and Eqs. (14.5) and (14.10) to determine NMH : (14.13) (14.14) vO VOH VDD = = kn rkp = vO = Vt (VDD Vt) – 2 r vI Vt) 2 – ( – + vO ∂ vI ∂ ⁄ 1 – = VIL = Vt VDD Vt – r r 1 + ( ) -----------------------+ VM = Vt VDD Vt – r 1 + --------------------+ vO vI Vt – ( ) vI Vt – ( ) 2 1 r --- VDD Vt – ( ) 2 – – = ∂vO ∂vI ⁄ 1 – = vI = VIH, V IH Vt 2 3r --------- VDD Vt – ( ) + = VOL VDD Vt – ( ) 1 1 1 r ---– – = Istat 1 2 ---kp VDD Vt – ( ) 2 = NML Vt V DD Vt – ( ) 1 1 1 r ---– – 1 r r 1 + ( ) -----------------------– – = NMH V DD Vt – ( ) 1 2 3r ---------– ⎝ ⎠ ⎛ ⎞ = 14.1 Pseudo-NMOS Logic Circuits 1149 As a final observation, we note that since VDD and Vt are determined by the process technology, the only design parameter for controlling the values of VOL and the noise margins is the ratio r.
14.1.4 Dynamic Operation Analysis of the inverter transient response to determine tPLH with the inverter loaded by a capacitance C is identical to that of the complementary CMOS inverter. The capacitance will be charged by the current iDP; we can determine an estimate for tPLH by using the average value of iDP over the range vO = 0 to vO = VDD ⁄ 2. The result is: (14.15) where (14.16) The case for the capacitor discharge is somewhat different because the current iDP has to be subtracted from iDN to determine the discharge current. The result is (14.17) where (14.18) which, for a large value of r, reduces to (14.19) Although these are similar formulas to those for the standard CMOS inverter, the pseudo-NMOS inverter has a special problem: Since kp is r times smaller than kn, tPLH will be approx-imately r times larger than tPHL. Thus the circuit exhibits an asymmetrical delay perfor-mance. Recall, however, that for gates with large fan-in, pseudo-NMOS requires fewer transistors and thus C can be smaller than in the corresponding standard CMOS gate.
14.1.5 Design The design involves selecting the ratio r and the W/L for one of the transistors. The value of for the other device can then be obtained using r. The design parameters of interest are VOL, NML, NMH, Istat, PD, tPLH, and tPHL. Important design considerations are as follows: 1. The ratio r determines all the breakpoints of the VTC; the larger the value of r, the lower VOL is (Eq. 14.11) and the wider the noise margins are (Eqs. 14.13 and 14.14).
However, a larger r increases the asymmetry in the dynamic response and, for a given (W/L)p, makes the silicon area larger. Thus, selecting a value for r represents a com-promise between noise margins on the one hand and silicon area and tP on the other.
Usually, r is selected in the range 4 to 10.
tPLH α pC kpVDD --------------= α p 2 7 4 ---3 Vt VDD ---------⎝ ⎠ ⎛ ⎞ – Vt VDD ---------⎝ ⎠ ⎛ ⎞ 2 + = tPHL α nC knVDD --------------α n 2 1 3 4 ---+ 1 1 r ---– ⎝ ⎠ ⎛ ⎞ 3 1 r ---– ⎝ ⎠ ⎛ ⎞ Vt VDD ---------⎝ ⎠ ⎛ ⎞ – Vt VDD ---------⎝ ⎠ ⎛ ⎞ 2 + = α n α p W L ⁄ 1150 Chapter 14 Advanced MOS and Bipolar Logic Circuits 2. Once r has been determined, a value for (W/L)p or (W/L)n can be selected and the other determined. Here, one would select a small (W/L)n to keep the gate area small and thus obtain a small value for C. Similarly, a small (W/L)p keeps Istat and PD low.
On the other hand, one would want to select larger W/L ratios to obtain low and thus fast response. For usual (high-speed) applications, (W/L)p is selected so that Istat is in the range of 50 µA to 100 µA, which for VDD = 1.8 V results in PD in the range of 90 µW to 180 µW.
14.1.6 Gate Circuits Except for the load device, the pseudo-NMOS gate circuit is identical to the PDN of the com-plementary CMOS gate. Four-input, pseudo-NMOS NOR and NAND gates are shown in Fig. 14.4. Note that each requires five transistors compared to the eight used in standard CMOS. In pseudo-NMOS, NOR gates are preferred over NAND gates because the former do not utilize transistors in series and thus can be designed with minimum-size NMOS devices.
14.1.7 Concluding Remarks Pseudo-NMOS is particularly suited for applications in which the output remains high most of the time. In such applications, the static power dissipation can be reasonably low (since the gate dissipates static power only in the low-output state). Further, the output transitions that matter would presumably be high-to-low ones, where the propagation delay can be made as short as necessary. A particular application of this type can be found in the design of address decoders for memory chips (Section 15.4) and in read-only memories (Section 15.5).
Figure 14.4 NOR and NAND gates of the pseudo-NMOS type.
tP Y Y A B C D QP B C QND D QNB QNC QNA A VDD (a) Y Y ABCD QNB QNA QP QND QNC A B C D VDD (b) 14.1 Pseudo-NMOS Logic Circuits 1151 Consider a pseudo-NMOS inverter fabricated in a 0.25-µm CMOS technology for which μnCox = 115 μpCox = 30 = − = 0.5 V, and VDD = 2.5 V. Let the ratio of QN be (0.375 μm ⁄ 0.25 μm) and r = 9. Find: (a) VOH, VOL, VIL, VIH, VM, NMH, and NML (b) (W/L)p (c) Istat and PD (d) tPLH, tPHL, and tP, assuming a total capacitance at the inverter output of 7 fF Solution (a) VOH = VDD = 2.5 V VOL is determined from Eq. (14.11) as VIL is determined from Eq. (14.7) as VIH is determined from Eq. (14.10) as VM is determined from Eq. (14.8) as The noise margins can now be determined as Observe that the noise margins are not equal and that NML is rather low.
(b) The ratio of QP can be found from Thus, (W/L)p = 0.64 μA/V2, μA/V2, Vtn Vtp W L ⁄ V OL = 2.5 0.5 – ( ) 1 1 1 9 ---– – 0.11 V = V IL = 0.5 2.5 0.5 – 9 9 1 + ( ) ------------------------+ 0.71 V = VIH = 0.5 2 3 9 × ----------------+ 2.5 0.5 – ( ) × 1.27 V = VM = 0.5 2.5 0.5 – 9 1 + ---------------------+ 1.13 V = NMH VOH VIH – 2.5 1.27 – 1.23 V = = = NML VIL VOL – 0.71 0.11 – 0.60 V = = = W L ⁄ μnCox W L ⁄ ( )n μpCox W L ⁄ ( )p ----------------------------------9 = 115 0.375 0.25 -------------× 30 W L ⁄ ( )p -----------------------------9 = Example 14.1 1152 Chapter 14 Advanced MOS and Bipolar Logic Circuits 14.2 Pass-Transistor Logic Circuits A conceptually simple approach for implementing logic functions utilizes series and parallel combinations of switches that are controlled by input logic variables to connect the input Example 14.1 continued (c) The dc current in the low-output state can be determined from Eq. (14.12) as The static power dissipation can now be found from (d) The low-to-high propagation delay can be found by using Eqs. (14.15) and (14.16): The high-to-low propagation delay can be found by using Eqs. (14.17) and (14.18): Now, the propagation delay can be determined as Although the propagation delay is considerably greater than that of a standard CMOS inverter, this is not an entirely fair comparison: Recall that the advantage of pseudo-NMOS occurs in gates with large fan-in, not in a single inverter.
Istat 1 2 ---30 0.64 2.5 0.5 – ( ) × × 2 38.4 μA = = PD IstatVDD = 38.4 2.5 × = = 96 μW α p 1.68 = tPLH 1.68 7 10 15 – × × 30 10 6 – 0.64 2.5 × × × -----------------------------------------------------0.25 ns = = αn 1.54 = tPHL 1.54 7 10 15 – × × 115 10 6 – 0.375 0.25 -------------2.5 × × × -----------------------------------------------------------0.03 ns = = tP 1 2 --- 0.25 0.03 + ( ) 0.14 ns = = EXERCISES 14.1 While keeping r unchanged, redesign the inverter circuit of Example 14.1 to lower its static power dissipation to half the value found. Find the ratios for the new design. Also find tPLH, tPHL, and tP, assuming that C remains unchanged. Would the noise margins change?
Ans. ( )n = 1.5; ( )p = 0.32; 0.5 ns; 0.03 ns; 0.27 ns; no 14.2 Redesign the inverter of Example 14.1 using r = 4. Find VOL and the noise margins. If ( )n = find ( )p, and tP. Assume C = 7 fF.
Ans. VOL = 0.27 V; NML = 0.68 V; NMH = 0.85 V; ( )p = 1.44; Istat = 86.3 μA; PD = 0.22 mW; tPLH = 0.11 ns; tPHL = 0.03 ns; tP = 0.07 ns W L ⁄ W L ⁄ W L ⁄ W L ⁄ 0.375 μm 0.25 μm, ⁄ W L ⁄ Istat, PD, tPLH, tPHL, W L ⁄ 14.2 Pass-Transistor Logic Circuits 1153 and output nodes (see Fig. 14.5). Each of the switches can be implemented either by a sin-gle NMOS transistor (Fig. 14.6) or by a pair of complementary MOS transistors connected in what is known as the CMOS transmission-gate configuration (Fig. 14.6). The result is a simple form of logic circuit that is particularly suited for some special logic functions and is frequently used in conjunction with standard CMOS logic to implement such functions effi-ciently: that is, with a lower total number of transistors than is possible with CMOS alone.
Because this form of logic utilizes MOS transistors in the series path from input to out-put, to pass or block signal transmission, it is known as pass-transistor logic (PTL). As mentioned earlier, CMOS transmission gates are frequently employed to implement the switches, giving this logic-circuit form the alternative name, transmission-gate logic. The terms are used interchangeably independent of the actual implementation of the switches.
Though conceptually simple, pass-transistor logic circuits have to be designed with care.
In the following, we shall study the basic principles of PTL circuit design and present exam-ples of its application.
14.2.1 An Essential Design Requirement An essential requirement in the design of PTL circuits is ensuring that every circuit node has at all times a low-resistance path either to VDD or to ground. To appreciate this point, Figure 14.5 Conceptual pass-transistor logic gates. (a) Two switches, controlled by the input variables B and C, when connected in series in the path between the input node to which an input variable A is applied and the output node (with an implied load to ground) realize the function Y = ABC. (b) When the two switches are connected in parallel, the function realized is Y = A(B + C).
Y A B C (a) Y A B C (b) Y A C (a) C Y A C (b) Figure 14.6 Two possible implementations of a voltage-controlled switch connecting nodes A and Y: (a) single NMOS transistor and (b) CMOS transmission gate.
1154 Chapter 14 Advanced MOS and Bipolar Logic Circuits consider the situation depicted in Fig. 14.7(a): A switch S1 (usually part of a larger PTL net-work, not shown) is used to form the AND function of its controlling variable B and the variable A available at the output of a CMOS inverter. The output Y of the PTL circuit is shown connected to the input of another inverter. Now, if B is high, S1 closes and Y = A.
Node Y will then be connected either to VDD (if A is high) through Q2 or to ground (if A is low) through Q1. But what happens when B goes low and S1 opens? Node Y will now become a high-impedance node. If initially vY was zero, it will remain so. However, if ini-tially vY was high at VDD, this voltage will be maintained by the charge on the parasitic capacitance C, and Y will not be a logic 0 as required of the AND function.
The problem can be easily solved by establishing for node Y a low-resistance path that is activated when B goes low, as shown in Fig. 14.7(b). Here, another switch, S2, controlled by , is connected between Y and ground. When B goes low, S2 closes and establishes a low-resistance path between Y and ground. The voltage vY will then be 0 volts, the proper output of the AND function when B is zero.
14.2.2 Operation with NMOS Transistors as Switches Implementing the switches in a PTL circuit with single NMOS transistors results in a simple circuit with small area and small node capacitances. These advantages, however, are obtained at the expense of serious shortcomings in both the static characteristics and the dynamic performance of the resulting circuits. To illustrate, consider the circuit shown in Fig. 14.8, where an NMOS transistor Q is used to implement a switch connecting an input node with voltage vI and an output node. The total capacitance between the output node and ground is represented by capacitor C. The switch is shown in the closed state with the control signal applied to its gate being high at VDD. We wish to analyze the operation of the circuit as the input voltage vI goes high (to VDD) at time t = 0. We assume that initially the output voltage vO is zero and capacitor C is fully discharged.3 Figure 14.7 A basic design requirement of PTL circuits is that every node have, at all times, a low-resistance path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in (b) through switch S2.
3Although the MOS transistor is symmetric and its drain and source are interchangeable, it is always useful to know which terminal is functioning as the source and which as the drain. The terminal with the higher voltage in an NMOS transistor is the drain. The opposite is true for the PMOS transistor.
Q2 Q1 S1 VDD Q4 Q3 Y A C B (a) Q2 Q1 S1 S2 VDD Y A C B B (b) B 14.2 Pass-Transistor Logic Circuits 1155 When vI goes high, the transistor operates in the saturation mode and delivers a current iD to charge the capacitor, (14.20) where and Vt is determined by the body effect since the source is at a voltage vO relative to the body (which, though not shown, is connected to ground); thus (see Eq.
5. 107), (14.21) Thus, initially (at t = 0), Vt = Vt0 and the current iD is relatively large. However, as C charges up and vO rises, Vt increases (Eq. 14.21) and iD decreases. The latter effect is due to both the increase in vO and in Vt. It follows that the process of charging the capacitor will be relatively slow. More seriously, observe from Eq. (14.20) that iD reduces to zero when vO reaches (VDD − Vt). Thus the high output voltage (VOH) will not be equal to VDD; rather, it will be lower by Vt, and to make matters worse, the value of Vt can be as high as 1.5 to 2 times Vt0!
In addition to reducing the gate noise immunity, the low value of VOH (commonly referred to as a “poor 1”) has another detrimental effect: Consider what happens when the output node is connected to the input of a standard CMOS inverter (as was the case in Fig. 14.7). The low value of VOH can cause QP of the load inverter to conduct. Thus the inverter will have a finite static current and static power dissipation.
The propagation delay tPLH of the PTL gate of Fig. 14.8 can be determined as the time for vO to reach This can be calculated using techniques similar to those employed in the analysis of the CMOS inverter in Section 13.3, as will be illustrated shortly in an example.
Figure 14.9 shows the NMOS switch circuit when vI is brought down to 0 V. We assume that initially vO = VDD. Thus at t = 0+, the transistor conducts and operates in the saturation region, (14.22) where we note that since the source is now at 0 V (note that the drain and source have inter-changed roles), there will be no body effect, and Vt remains constant at Vt0. As C discharges, vO decreases and the transistor enters the triode region at vO = VDD − Vt. Nevertheless, the capacitor discharge continues until C is fully discharged and vO = 0. Thus, the NMOS tran-sistor provides VOL = 0, or a “good 0.” Again, the propagation delay tPHL can be determined using usual techniques, as illustrated by the following example.
Figure 14.8 Operation of the NMOS transistor as a switch in the implementation of PTL circuits. This analysis is for the case with the switch closed (vC is high) and the input going high (vI = VDD).
vI t 0 C Q VDD vO t tPLH 0 2 VDD Vt VDD vO vC VDD vI VDD iD iD 1 2 ---kn(VDD vO – Vt) – 2 = kn = k′ n (W L ⁄ ), Vt = Vt0 γ vO 2φf + 2φf – ( ) + VDD 2.
⁄ iD 1 2 ---kn VDD Vt – ( ) 2 = 1156 Chapter 14 Advanced MOS and Bipolar Logic Circuits Figure 14.9 Operation of the NMOS switch as the input goes low (vI = 0 V). Note that the drain of an NMOS transistor is always higher in voltage than the source; correspondingly, the drain and source terminals interchange roles in comparison to the circuit in Fig. 14.8.
vI t 0 C Q vO t tPHL 0 2 VDD VDD vO vC VDD vI 0 iD Example 14.2 Consider the NMOS transistor switch in the circuits of Figs. 14.8 and 14.9 to be fabricated in a technol-ogy for which μnCox = 50 μpCox = 20 γ = 0.5 V1/2, 2φf = 0.6 V, and VDD = 5 V, where φf is a physical parameter. Let the transistor be of the minimum size for this technology, namely, 4 μm/2 μm, and assume that the total capacitance between the output node and ground is C = 50 fF.
(a) For the case with vI high (Fig. 14.8), find VOH.
(b) If the output feeds a CMOS inverter whose μm, find the static current of the inverter and its power dissipation when its input is at the value found in (a). Also find the inverter output voltage.
(c) Find tPLH.
(d) For the case with vI going low (Fig. 14.9), find tPHL.
(e) Find tP.
Solution (a) Refer to Fig. 14.8. If VOH is the value of vO at which Q stops conducting, then, where Vt is the value of the threshold voltage at a source–body reverse bias equal to VOH. Using Eq. (14.21), we have Substituting Vt0 = 1, γ = 0.5, VDD = 5, and 2φf = 0.6, we obtain a quadratic equation in Vt whose solution yields Thus, μA/V2, μA/V2, Vt0 1 V, = (W L ⁄ )p = 2.5 (W L ⁄ )n = 10 μm 2 ⁄ VDD VOH – Vt – 0 = VOH VDD Vt – = Vt Vt0 γ VOH 2φf + 2φf – ( ) + = Vt0 = γ VDD Vt – 2φf + 2φf – ( ) + Vt 1.6 V = VOH 3.4 V = 14.2 Pass-Transistor Logic Circuits 1157 Note that this represents a significant loss in signal amplitude.
(b) The load inverter will have an input signal of 3.4 V. Thus, its QP will conduct a current of where we have assumed QP to be operating in saturation, as we still expect vO of the inverter to be close to 0. Thus, the static power dissipation of the inverter will be The output voltage of the inverter can be found by noting that QN will be operating in the triode region.
Equating its current to that of QP (i.e., 18 μA) enables us to determine the output voltage to be 0.08 V.
(c) To determine tPLH, refer to Fig 14.8. We need to find the current iD at t = 0 (where vO = 0, Vt = Vt0 = 1 V) and at t = tPLH (where vO = 2.5 V, Vt to be determined), as follows: We can now compute the average discharge current as and tPLH can be found as (d) Refer to the circuit in Fig. 14.9. Observe that, here, Vt remains constant at Vt0 = 1 V. At t = 0, Q will be operating in saturation, and the drain current will be At t = tPHL, Q will be operating in the triode region, and thus Thus, the average discharge current is given by and tPHL can be determined as (e) iDP 1 2 ---20 10 2 ------× × 5 3.4 – 1 – ( )2 18 μA = = PD VDDiDP 5 18 × 90 μW = = = iD 0 ( ) 1 2 ---50 4 2 ---× × 5 1 – ( ) × 2 800 μA = = Vt at vO 2.5 V = ( ) 1 0.5 2.5 0.6 + 0.6 – ( ) + 1.49 V = = iD tPLH ( ) 1 2 ---50 4 2 --- 5 2.5 – 1.49 – ( ) × × 2 50 μA = = iD av 800 50 + 2 ---------------------425 μA = = tPLH C VDD 2 ⁄ ( ) iD av --------------------------= 50 10 15 – 2.5 × × 425 10 6 – × --------------------------------------= 0.29 ns = iD 0 ( ) 1 2 ---50 4 2 --- 5 1 – ( ) × × 2 800 μA = = iD tPHL ( ) 50 4 2 ---5 1 – ( ) 2.5 1 2 ---– × 2.52 × × = 690 μA = iD av 1 2 −800 690 + ( ) 740 μA = = tPHL 50 10 15 – 2.5 × × 740 10 6 – × --------------------------------------0.17 ns = = tP 1 2 --- tPLH tPHL + ( ) 1 2 --- 0.29 0.17 + ( ) 0.23 ns = = = 1158 Chapter 14 Advanced MOS and Bipolar Logic Circuits 14.2.3 Restoring the Value of VOH to VDD Example 14.2 illustrates clearly the problem of signal-level loss and its deleterious effect on the operation of the succeeding CMOS inverter. Some rather ingenious techniques have been developed to restore the output level to VDD. We shall briefly discuss two such tech-niques. One is circuit-based and the other is based on process technology.
The circuit-based approach is illustrated in Fig. 14.10. Here, Q1 is a pass-transistor con-trolled by input B. The output node of the PTL network is connected to the input of a standard CMOS inverter formed by QN and QP. A PMOS transistor QR, whose gate is controlled by the output voltage of the inverter, vO2, has been added to the circuit. Observe that in the event that the output of the PTL gate, vO1, is low (at ground), vO2 will be high (at VDD), and QR will be off.
On the other hand, if vO1 is high but not quite equal to VDD, the output of the inverter will be low (as it should be) and QR will turn on, supplying a current to charge C up to VDD. This process will stop when vO1 = VDD, that is, when the output voltage has been restored to its proper level. The “level-restoring” function performed by QR is frequently employed in MOS digital-circuit design. It should be noted that although the description of operation is relatively straight for-ward, the addition of QR closes a “positive-feedback” loop around the CMOS inverter, and thus operation is more involved than it appears, especially during transients. Selection of a ratio for QR is also a somewhat involved process, although normally kr is selected to be much lower than kn (say a third or a fifth as large). Intuitively, this is appealing, for it implies that QR will not play a major role in circuit operation, apart from restoring the level of VOH to VDD, as explained above. Transistor QR is said to be a “weak PMOS transistor.” See Problem 14.17.
The other technique for correcting for the loss of the high-output signal level (VOH) is a tech-nology-based solution. Specifically, recall that the loss in the value of VOH is equal to It fol-lows that we can reduce the loss by using a lower value of for the NMOS switches, and we can eliminate the loss altogether by using devices for which = 0. These zero-threshold devices can be fabricated by using ion implantation to control the value of and are known as EXERCISE 14.3 Let the NMOS transistor switch in Fig. 14.8 be fabricated in a 0.18-μm CMOS process for which and Find Ans. 1.15 V Vt0 0.5 V, = γ 0.3 V1 2 ⁄ , = 2φf 0.85 V, = VDD 1.8 V.
= VOH.
W L ⁄ Vtn.
Vtn Vtn Vtn Q1 B A C QP VDD VDD QR QN vO2 vO1 Figure 14.10 The use of transistor QR, con-nected in a feedback loop around the CMOS inverter, to restore the VOH level, produced by Q1, to VDD.
14.2 Pass-Transistor Logic Circuits 1159 natural devices. The problem of low-threshold devices, however, is the increased subthreshold conduction (Section 13.5.3) and the corresponding increase in static power dissipation.
14.2.4 The Use of CMOS Transmission Gates as Switches Great improvements in static and dynamic performance are obtained when the switches are implemented with CMOS transmission gates. The transmission gate utilizes a pair of comple-mentary transistors connected in parallel. It acts as an excellent switch, providing bidirectional current flow, and it exhibits an “on” resistance that remains almost constant for wide ranges of input voltage. These characteristics make the transmission gate not only an excellent switch in digital applications but also an excellent analog switch in such applications as data converters and switched-capacitor filters (Chapter 16).
Before we analyze the transmission gate circuit, it is useful to reflect on its origin. Recall that an NMOS transistor transmits the 0-V level to the output perfectly and thus produces a “good 0.” It has difficulty, however, in passing the level, with the result that (a “poor 1”). It can be shown (see Problem 14.18) that a PMOS transistor does exactly the opposite; that is, it passes the level perfectly and thus produces a “good 1” but has trouble passing the 0-V level, thus producing a “poor 0.” It is natural there-fore to think that placing an NMOS and a PMOS transistor in parallel would produce good results in both the 0 and 1 cases.
Another way to describe the performance of the two transistor types is that the NMOS is good at pulling the output down to 0 V, while the PMOS is good at pulling the output up to . Interestingly, these are also the roles they play in the standard CMOS inverter.
Figure 14.11 shows the transmission gate together with its frequently used circuit sym-bol. The transmission gate is a bilateral switch that results in when is high ( ). In terms of logic variables, its function is described by Figure 14.12(a) shows the transmission-gate switch in the “on” position with the input, vI, rising to VDD at t = 0. Assuming, as before, that initially the output voltage is zero, we see that QN will be operating in saturation and providing a charging current of (14.23) VDD VOH VDD Vt – = VDD VDD vY vX = vC VDD Y X if C 1 = = iDN 1 2 ---kn VDD vO – Vtn – ( ) 2 = QP QN X Y Y X C C C C Figure 14.11 The CMOS transmission gate and its circuit symbol.
1160 Chapter 14 Advanced MOS and Bipolar Logic Circuits where, as in the case of the single NMOS switch, is determined by the body effect, (14.24) Transistor QN will conduct a diminishing current that reduces to zero at vO = VDD – Observe, however, that QP operates with VSG = VDD and is initially in saturation, (14.25) where, since the body of QP is connected to VDD, remains constant at the value Vt0, assumed to be the same value as for the n-channel device. The total capacitor-charging cur-rent is the sum of iDN and iDP. Now, QP will enter the triode region at vO = but will con-tinue to conduct until C is fully charged and vO = VOH = VDD. Thus, the p-channel device will provide the gate with a “good 1.” The value of tPLH can be calculated using usual techniques, where we expect that as a result of the additional current available from the PMOS device, for the same value of C, tPLH will be lower than in the case of the single NMOS switch. Note, however, that adding the PMOS transistor increases the value of C.
When vI goes low, as shown in Fig. 14.12(b), QN and QP interchange roles. Analysis of the circuit in Fig. 14.12(b) will indicate that QP will cease conduction when vO falls to where is given by [ ] (14.26) vI VDD vC VDD vC 0 QN QP vI t 0 VDD C vO t tPLH 0 2 VDD VDD vO iDN iDP (a) vI 0 vC VDD vC 0 QN QP vI t 0 VDD C vO t tPHL 0 2 VDD VDD vO iDN iDP (b) Figure 14.12 Operation of the transmission gate as a switch in PTL circuits with (a) vI high and (b) vI low.
V tn V tn Vt0 γ vO 2φf + 2φf – ( ) + = Vtn.
iDP 1 2 ---kp VDD Vtp – ( ) 2 = Vtp Vtp , Vtp , Vtp Vtp Vt0 γ + = V DD vO – 2φf + 2φf – 14.2 Pass-Transistor Logic Circuits 1161 Transistor QN, however, continues to conduct until C is fully discharged and vO = VOL = 0 V, a “good 0.” We conclude that transmission gates provide far superior performance, both static and dynamic, than is possible with single NMOS switches. The price paid is increased circuit complexity, area, and capacitance.
Equivalent Resistance of the Transmission Gate Although the transmission gate is capable of passing the full 1 and 0 levels to the load capacitance, it is not a perfect switch. In particular, the transmission gate has a finite “on” resistance. It is useful for us to obtain an estimate for this resistance. It can, for instance, be used together with the load capacitance as an alternative means to determining propagation delay. This approach is particularly useful in situations involving a network of inverters and transmission gates, as we shall shortly see. To obtain an estimate of the resistance of the transmission gate, we shall consider the sit-uation in Fig. 14.12(a), where the transmission gate is on and is passing a high input to the capacitor load. Transistor operates in saturation until the output voltage reaches , at which time turns off; thus, for (14.27) for (14.28) A gross estimate for the equivalent resistance of can be obtained by dividing the volt-age across it, , by , and neglecting the body effect, that is, assuming remains constant; thus, for (14.29) and for (14.30) 14.4 The transmission gate of Figs. 14.12(a) and 14.12(b) is fabricated in a CMOS process technology for which Vt0 = 1 V, γ = 0.5 V1/2, 2φf = 0.6 V, and VDD = 5 V. Let QN and QP be of the minimum size possible with this process technology, ( )n = ( )p = 4 μm/2 μm. The total capacitance at the output node is 70 fF. Utilize as many of the results of Example 14.2 as you need.
(a) What are the values of VOH and VOL?
(b) For the situation in Fig. 14.12(a), find iDN(0), iDP(0), iDN(tPLH), iDP(tPLH), and tPLH.
(c) For the situation depicted in Fig. 14.12(b), find iDN(0), iDP(0), iDN(tPHL), iDP(tPHL), and tPHL. At what value of vO will QP turn off?
(d) Find tP.
Ans. (a) 5 V, 0 V; (b) 800 μA, 320 μA, 50 μA, 275 μA, 0.24 ns; (c) 800 μA, 320 μA, 688 μA, 20 μA, 0.19 ns, 1.6 V; (d) 0.22 ns k′ n = 50 μA/V2, k′ p = 20 μA/V2, Vtn Vtp , = W L ⁄ W L ⁄ EXERCISE VDD ( ) QN vO VDD Vtn – ( ) QN iDN 1 2 ---kn VDD Vtn – vO – ( ) 2 = vO VDD Vtn – ≤ iDN 0 = vO VDD Vtn – ≥ QN VDD vO – ( ) iDN Vtn RNeq VDD vO – 1 2 ---kn VDD Vtn – vO – ( ) 2 ---------------------------------------------------= vO VDD Vtn – ≤ RNeq ∞ = vO VDD Vtn – ≥ 1162 Chapter 14 Advanced MOS and Bipolar Logic Circuits Transistor will operate in saturation until after which it enters the triode region; thus, for (14.31) for (14.32) A gross estimate for the resistance of can be obtained by dividing the voltage across it, by ; thus, for (14.33) for (14.34) Finally, the equivalent resistance of the transmission gate can be obtained as the paral-lel equivalent of and (14.35) Obviously, is a function of the output voltage As an example, we show in Fig. 14.13 a plot for for the transmission gate analyzed in Exercise 14.4. Observe that remains relatively constant over the full range of The average value of over the range to can be used to determine , as illustrated in Exercise 14.5.
The expression for derived above applies only to the case of capacitor charging. A similar analysis can be performed for the case of capacitor discharge illustrated in Fig. 14.12(b). The resulting value of is close to that obtained above (see Problem 14.21).
Similar to the empirical formulas for and of the CMOS inverter (Eqs. 13.70 and 13.71), there is a simple empirical formula for that applies for both capacitor charging and discharging and for all modern submicron technologies (see Hodges et al., 2004), namely, (14.36) QP vO Vtp , = iDP 1 2 ---kp VDD Vtp – ( )2 = vO Vtp ≤ iDP kp VDD Vtp – ( ) VDD vO – ( ) 1 2 --- VDD vO – ( ) 2 – = vO Vtp ≥ QP VDD vO – ( ), iDP RPeq VDD vO – 1 2 ---kp VDD Vtp – ( )2 ------------------------------------------= vO Vtp ≤ RPeq 1 kp VDD Vtp – 1 2 --- VDD vO – ( ) – --------------------------------------------------------------------------= vO Vtp ≥ RTG RNeq RPeq, RTG RNeq RPeq || = RTG vO.
RTG RTG vO.
RTG vO 0 = VDD 2 ⁄ tPLH 14.5 For the transmission gate analyzed in Exercise 14.4, whose equivalent resistance for capacitor charg-ing is plotted in Fig. 14.13, use the average resistance value over the range V to 2.5 V to determine Compare the result to that obtained using average currents in Exercise 14.4. Note that from the graph, at and at Recall that Ans. very close to the value of 0.24 ns obtained in Exercise 14.4 vO 0 = tPLH.
RTG 4.5 kΩ = vO 0 V, = RTG 6.5 kΩ = vO 2.5 V.
= tPLH 0.69RC.
= tPLH 0.27 ns, = EXERCISE RTG RTG RN RP RTG RTG 12.5 W L ⁄ ( )n ------------------- kΩ 14.2 Pass-Transistor Logic Circuits 1163 Having an estimate of the resistance of the transmission gate enables us to calculate the propagation delay of a signal path containing one or more transmission gates. Figure 14.14(a) shows one such circuit. It consists of a transmission gate connecting the output of an inverter to the input of another. We are interested in finding the propagation delay from the input of the first inverter to the input of the second as we apply a negative going step to the input of the first inverter. Fig. 14.14(b) shows the equivalent circuit where is the equivalent resistance of is the equivalent resistance of the transmission gate, is the output capacitance of the driver inverter, and are the capacitances introduced by the transmission gate at its input and output, respectively, and is the input capacitance of the load inverter.
Observe that the circuit takes the form of an RC ladder network. A simple formula has been developed for calculating the delay of an arbitrarily long RC ladder network such as that shown in Fig. 14.15 having three sections. Known as the Elmore delay formula, it gives for the ladder in Fig. 14.15 (14.37) Applying the Elmore formula to the two-stage ladder in Fig. 14.14(b) gives (14.38) Figure 14.13 Plot of the equivalent resistances of the two transistors of the transmission gate in Fig. 14.12(a) and the overall resistance RTG versus vO. The data apply to the situation specified in Exercise 14.5.
R 1 2 3 4 5 2 0 4 6 8 10 12 14 16 18 vO (V) RTG RPeq RNeq ( k ) 14.6 Use Eq. (14.36) to estimate the value of for a transmission gate fabricated in a 0.18-μm CMOS technology with Ans. 8.3 RTG W L ⁄ ( )n W L ⁄ ( )p 1.5.
= = kΩ EXERCISE RP1 QP1, RTG Cout1 CTG1 CTG2 Cin2 tP 0.69 C1R1 C2 R1 R2 + ( ) C3 R1 R2 R3 + + ( ) + + [ ] = tP 0.69 Cout1 CTG1 + ( )R1 Cin2 CTG2 + ( ) R1 R2 + ( ) + [ ] = 1164 Chapter 14 Advanced MOS and Bipolar Logic Circuits 14.2.5 Pass-Transistor Logic Circuit Examples We conclude this section by showing examples of PTL logic circuits. Figure 14.16 shows a PTL realization of a two-to-one multiplexer: Depending on the logic value of C, either A or B is connected to the output Y. The circuit realizes the Boolean function Figure 14.14 (a) A transmission gate connects the output of a CMOS inverter to the input of another. (b) Equivalent circuit for the purpose of analyzing the propagation delay of the circuit in (a).
QP2 QN2 VDD C C (a) QN1 QP1 QN3 QP3 vI vO RP1 RTG (b) Cout1 CTG1 CTG2 Cin2 VDD vO R1 C1 vI R2 C2 R3 C3 vO Figure 14.15 A three-section RC ladder network.
14.7 The circuit in Fig. 14.14 is fabricated in a 0.13-μm CMOS technology; of the first inverter has W/L = 2, and both transistors of the transmission gate have W/L = 1. The capacitances have been estimated to be fF, fF, and fF. Use the empirical formu-las to obtain the values of and Then, determine an estimate for Ans. ; ; QP Cout1 10 = CTG1 CTG2 5 = = Cin2 10 = RP1 RTG.
tP.
RP1 15 kΩ = RTG 12.5 kΩ = tP 0.64 ns = EXERCISE Y = CA CB + 14.2 Pass-Transistor Logic Circuits 1165 Our second example is an efficient realization of the exclusive-OR (XOR) function. The circuit, shown in Fig. 14.17, utilizes four transistors in the transmission gates and another four for the two inverters needed to generate the complements and for a total of eight transis-tors. Note that 12 transistors are needed in the realization with standard CMOS.
Our final PTL example is the circuit shown in Fig. 14.18. It uses NMOS switches with low or zero threshold. Observe that both the input variables and their complements are employed and that the circuit generates both the Boolean function and its complement. Thus this form of circuit is known as complementary pass-transistor logic (CPL). The circuit consists of two identical networks of pass transistors with the corresponding transistor gates controlled by the same signal (B and The inputs to the PTL, however, are complemented: A and B for the first network, and and for the second. The circuit shown realizes both the AND and NAND functions.
C Y CA CB A B C C Figure 14.16 Realization of a two-to-one multi-plexer using pass-transistor logic.
A A B B B Y AB AB Figure 14.17 Realization of the XOR function using pass-transistor logic.
A B, B).
A B 1166 Chapter 14 Advanced MOS and Bipolar Logic Circuits 14.2.6 A Final Remark Although the use of zero-threshold devices solves the problem of the loss of signal levels when NMOS switches are used, the resulting circuits can be much more sensitive to noise and other effects, such as leakage currents resulting from subthreshold conduction.
14.3 Dynamic MOS Logic Circuits The logic circuits that we have studied thus far are of the static type. In a static logic circuit, every node has, at all times, a low-resistance path to VDD or ground. By the same token, the voltage of each node is well defined at all times, and no node is left floating. Static circuits do not need clocks (i.e., periodic timing signals) for their operation, although clocks may be present for other purposes. In contrast, the dynamic logic circuits we are about to discuss rely on the storage of signal voltages on parasitic capacitances at certain circuit nodes. Since charge will leak away with time, the circuits need to be periodically refreshed; thus the presence of a clock with a certain specified minimum frequency is essential.
To place dynamic logic circuit techniques into perspective, let’s take stock of the various styles we have studied for logic circuits. Standard CMOS excels in nearly every perfor-mance category: It is easy to design, has the maximum possible logic swing, is robust from a noise-immunity standpoint, dissipates no static power, and can be designed to provide equal low-to-high and high-to-low propagation delays. Its main disadvantage is the requirement of two transistors for each additional gate input, which for high fan-in gates can make the chip A B 1 2 5 6 A B 3 4 Y A B AB Y AB B B Figure 14.18 An example of a pass-transistor logic gate utilizing both the input variables and their com-plements. This type of circuit is therefore known as complementary pass-transistor logic, or CPL. Note that both the output function and its complement are generated.
14.8 Consider the circuit in Fig. 14.8, and for each case, find Y and The input signals are changed as follows: (a) The signals at terminals 5 and 6 are interchanged ( applied to 5 and B applied to 6). All the rest are the same.
(b) The signals at terminals 5 or 6 are interchanged as in (a), and the signals at 2 and 4 are changed to and A, respectively. All the rest remain the same.
Ans. (a) (i.e., OR–NOR); (b) (i.e., XOR–XNOR) Y.
B A Y = A + B, Y = AB = A + B Y = AB + AB Y AB AB + = , EXERCISE 14.3 Dynamic MOS Logic Circuits 1167 area large and increase the total capacitance and, correspondingly, the propagation delay and the dynamic power dissipation. Pseudo-NMOS reduces the number of required transistors at the expense of static power dissipation. Pass-transistor logic can result in simple small-area circuits but is limited to special applications and requires the use of CMOS inverters to restore signal levels, especially when the switches are simple NMOS transistors. The dynamic logic techniques studied in this section maintain the low device count of pseudo-NMOS while reducing the static power dissipation to zero. As will be seen, this is achieved at the expense of more complex, and less robust, design.
14.3.1 The Basic Principle Figure 14.19(a) shows the basic dynamic logic gate. It consists of a pull-down network (PDN) that realizes the logic function in exactly the same way as the PDN of a standard CMOS gate or a pseudo-NMOS gate. Here, however, we have two switches in series that are periodically operated by the clock signal φ whose waveform is shown in Fig. 14.19(b). When φ is low, Qp is turned on, and the circuit is said to be in the setup or precharge phase. When φ is high, Qp is off and Qe turns on, and the circuit is in the evaluation phase. Finally, note that CL denotes the total capacitance between the output node and ground.
During precharge, Qp conducts and charges capacitance CL so that at the end of the precharge interval, the voltage at Y is equal to VDD. Also during precharge, the inputs A, B, and C are allowed to change and settle to their proper values. Observe that because Qe is off, no path to ground exists.
During the evaluation phase, Qp is off and Qe is turned on. Now, if the input combination is one that corresponds to a high output, the PDN does not conduct (just as in a standard Figure 14.19 (a) Basic structure of dynamic-MOS logic circuits. (b) Waveform of the clock needed to operate the dynamic logic circuit. (c) An example circuit.
A B C PDN Qp Qe VDD CL Y (a) VDD 0 Precharge Evaluate t (b) VDD Qp Qe Y A BC A B C (c) 1168 Chapter 14 Advanced MOS and Bipolar Logic Circuits CMOS gate) and the output remains high at VDD; thus VOH = VDD. Observe that no low-to-high propagation delay is required, thus tPLH = 0. On the other hand, if the combination of inputs is one that corresponds to a low output, the appropriate NMOS transistors in the PDN will conduct and establish a path between the output node and ground through the “on” tran-sistor Qe. Thus CL will be discharged through the PDN, and the voltage at the output node will reduce to VOL = 0 V. The high-to-low propagation delay tPHL can be calculated in exactly the same way as for a standard CMOS circuit, except that here we have an additional transis-tor, Qe, in the series path to ground. Although this will increase the delay slightly, the increase will be more than offset by the reduced capacitance at the output node as a result of the absence of the PUN.
As an example, we show in Fig. 14.19(c) the circuit that realizes the function Sizing of the PDN transistors often follows the same procedure employed in the design of static CMOS. For Qp, we select a ratio large enough to ensure that CL will be fully charged during the precharge interval, but small enough so that the capacitance CL will not be increased significantly. This is a ratioless form of MOS logic, where the output levels do not depend on the transistors’ ratios (unlike pseudo-NMOS, for instance).
Y A BC.
+ = W L ⁄ W L ⁄ Example 14.3 Consider the four-input, dynamic-logic NAND gate shown in Fig. 14.20(a). Assume that the gate is fabricated in a 0.18-μm CMOS technology for which and To keep small, NMOS devices with W/L = are used (including transistor ). The PMOS precharge transistor has W/L = 0.54 μm/0.18 μm.
The total capacitance is found to be 20 fF.
(a) Consider the precharge operation (Fig. 14.20b) with the gate of at 0 V, and assume that at t = 0, is fully discharged. Calculate the rise time of the output voltage, defined as the time for to rise from 10% to 90% of the final voltage (b) For A = B = C = D = 1, find the value of Solution (a) From Fig. 14.20(a) we see that at will be operating in the saturation region and will be At will be operating in the triode region; thus, VDD 1.8 V, = Vt 0.5 V, = μnCox 4μpCox 300 μA V2.
⁄ = = CL 0.27 μm 0.18 μm ⁄ Qe Qp CL Qp CL vY VDD.
tPHL.
vY 0.1VDD 0.18 V, = = Qp iD iD 0.1VDD ( ) 1 2 ---μpCox W L -----⎝ ⎠ ⎛ ⎞ p VDD Vtp – ( )2 = 1 2 ---75 0.54 0.18 ----------× × 1.8 0.5 – ( )2 = 190.1 μA = vY 0.9VDD 1.62 V, = = Qp iD 0.9VDD ( ) μpCox W L -----⎝ ⎠ ⎛ ⎞ p VDD Vtp – ( ) VDD 0.9VDD – ( ) 1 2 --- VDD 0.9VDD – ( )2 – = 75 0.54 0.18 ----------× 1.8 0.5 – ( ) 1.8 1.62 – ( ) 1 2 --- 1.8 1.62 – ( )2 – = 49 μA = 14.3 Dynamic MOS Logic Circuits 1169 Thus the average capacitor charging current is The rise time of can now be determined from Thus, (b) When A = B = C = D = 1, all the NMOS transistors will be conducting during the evaluation phase.
Replacing the five identical transistors with an equivalent device with , we obtain the equivalent circuit for the capacitor discharge, shown in Fig. 14.20(c). At , will be operating in saturation; thus, Figure 14.20 Circuits for Example 14.3.
CL Qp QA QB QC QD Qe f A Y B C D (a) f CL (c) Qeq vY iD VDD CL QP vY iD VDD (b) Iav 1 2 --- 190.1 49 + ( ) 119.6 μA = = tr vY tr C vY Δ Iav -------------= C 0.9VDD 0.1VDD – ( ) Iav ---------------------------------------------------= tr 20 10 15 – 0.8 1.8 × × × 119.6 10 6 – × ----------------------------------------------------0.19 ns = = Qeq W L ⁄ ( )eq 1 5 -- W L ⁄ ( ) = = 1 5 --1.5 0.3 = × vY VDD = Qeq iD VDD ( ) 1 2 --- μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ eq VDD Vt – ( )2 = 1 2 ---300 0.3 1.8 0.5 – ( )2 × × = 76.1 = μA 1170 Chapter 14 Advanced MOS and Bipolar Logic Circuits 14.3.2 Nonideal Effects We now briefly consider various sources of nonideal operation of dynamic logic circuits.
Noise Margins Since, during the evaluation phase, the NMOS transistors begin to con-duct for vI = , and thus the noise margins will be Thus the noise margins are far from equal, and NML is rather low. Although NMH is high, other nonideal effects reduce its value, as we shall shortly see. At this time, however, observe that the output node is a high-impedance node and thus will be susceptible to noise pickup and other disturbances.
Output Voltage Decay Due to Leakage Effects In the absence of a path to ground through the PDN, the output voltage will ideally remain high at VDD. This, however, is based Example 14.3 continued At will be operating in the triode region; thus, Thus the average capacitor-discharge current is and can be found from vY VDD 2, ⁄ = Qeq iD VDD 2 ⁄ ( ) μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ eq VDD Vt – ( )VDD 2 ----------1 2 --- VDD 2 ----------⎝ ⎠ ⎛ ⎞ 2 – = 300 0.3 1.8 0.5 – ( ) 1.8 2 -------⎝ ⎠ ⎛ ⎞ 1 2 --- 1.8 2 -------⎝ ⎠ ⎛ ⎞ 2 – × = 68.9 = μA Iav 76.1 68.9 + 2 ---------------------------72.5 μA = = tPHL tPHL C VDD V – DD 2 ⁄ ( ) Iav ------------------------------------------= 20 10 15 – 1.8 0.9 – ( ) × 72.5 10 6 – × ---------------------------------------------------0.25 ns = = 14.9 In an attempt to reduce of the NAND gate in Example 14.3, the designer doubles the value of W/L of each of the NMOS devices. If C increases to 30 fF, what is the new value if Ans. 0.19 ns tPHL tPHL?
EXERCISE V tn VIL VIH V tn NML VIL VOL – = Vtn 0 – Vtn = = NMH VOH VIH – = VDD Vtn – = 14.3 Dynamic MOS Logic Circuits 1171 on the assumption that the charge on CL will remain intact. In practice, there will be leakage current that will cause CL to slowly discharge and vY to decay. The principal source of leak-age is the reverse current of the reverse-biased junction between the drain diffusion of transistors connected to the output node and the substrate. Such currents can be in the range of A to A, and they increase rapidly with temperature (approximately doubling for every rise in temperature). Thus the circuit can malfunction if the clock is operat-ing at a very low frequency and the output node is not “refreshed” periodically. This exact same point will be encountered when we study dynamic memory cells in Chapter 15.
Charge Sharing There is another and often more serious way for CL to lose some of its charge and thus cause vY to fall significantly below VDD. To see how this can happen, refer to Fig. 14.21(a), which shows only Q1 and Q2, the two top transistors of the PDN, together with the precharge transistor Qp. Here, C1 is the capacitance between the common node of Q1 and Q2 and ground. At the beginning of the evaluation phase, after Qp has turned off and with CL charged to VDD (Fig. 14.21a), we assume that C1 is initially discharged and that the inputs are such that at the gate of Q1 we have a high signal, whereas at the gate of Q2 the signal is low.
We can easily see that Q1 will turn on and its drain current, iD1, will flow as indicated. Thus iD1 will discharge CL and charge C1. Although eventually iD1 will reduce to zero, CL will have lost some of its charge, which will have been transferred to C1. This phenomenon is known as charge sharing (see Problem 14.31).
We shall not pursue the problem of charge sharing any further here, except to point out a couple of the techniques usually employed to minimize its effect. One approach involves add-ing a p-channel device that continuously conducts a small current to replenish the charge lost by CL, as shown in Fig. 14.21(b). This arrangement should remind us of pseudo-NMOS. Indeed, adding this transistor will cause the gate to dissipate static power. On the positive side, however, the added transistor will lower the impedance level of the output node and make it less suscepti-ble to noise as well as solving the leakage and charge-sharing problems. Another approach to Figure 14.21 (a) Charge sharing. (b) Adding a permanently turned-on transistor QL solves the charge-sharing problem at the expense of static power dissipation.
10 12 – 10 15 – 10°C VDD VDD Y iD1 iD1 Q1 Qp Q2 0 0 CL C1 VDD 0 V (a) Qp QL VDD CL Y (b) 1172 Chapter 14 Advanced MOS and Bipolar Logic Circuits solving the charge-sharing problem is to precharge the internal nodes: that is, to precharge capacitor C1. The price paid in this case is increased circuit complexity and node capacitances.
Cascading Dynamic Logic Gates A serious problem arises if one attempts to cascade dynamic logic gates. Consider the situation depicted in Fig. 14.22, where two single-input dynamic gates are connected in cascade. During the precharge phase, CL1 and CL2 will be charged through Qp1 and Qp2, respectively. Thus, at the end of the precharge interval, vY1 = VDD and vY2 = VDD. Now consider what happens in the evaluation phase for the case of high input A. Obviously, the correct result will be Y1 low (vY1 = 0 V) and Y2 high (vY2 = VDD). What happens, however, is somewhat different. As the evaluation phase begins, Q1 turns on and CL1 begins to discharge. However, simultaneously, Q2 turns on and CL2 also begins to discharge. Only when vY1 drops below Vtn will Q2 turn off. Unfortunately, how-ever, by that time, CL2 will have lost a significant amount of its charge, and vY2 will be less than the expected value of VDD. (Here it is important to note that in dynamic logic, once charge has been lost, it cannot be recovered.) This problem is sufficiently serious to make simple cascading an impractical proposition. As usual, however, the ingenuity of circuit designers has come to the rescue, and a number of schemes have been proposed to make cas-cading possible in dynamic-logic circuits. We shall discuss one such scheme after considering Exercise 14.10.
Figure 14.22 Two single-input dynamic logic gates connected in cascade. With the input A high, during the evaluation phase CL2 will partially discharge and the output at Y2 will fall lower than VDD, which can cause logic malfunction.
Qp1 Q1 Qe1 A Qp2 Q2 Qe2 CL1 CL2 Y1 Y2 VDD VDD 14.10 To gain further insight into the cascading problem described above, let us determine the decrease in the output voltage vY2 for the circuit in Fig. 14.22. Specifically, consider the circuit as the evalu-ation phase begins: At t = 0, vY1 = vY2 = VDD and Transistors Qp1 and Qp2 are cut off and can be removed from the equivalent circuit. Furthermore, for the purpose of this approxi-mate analysis, we can replace the series combination of Q1 and Qe1 with a single device having an appropriate and similarly for the combination of Q2 and Qe2. The result is the approximate equivalent circuit in Fig. E14.10. We are interested in the operation of this circuit in the interval Δt vφ vA VDD.
= = W L, ⁄ EXERCISE 14.3 Dynamic MOS Logic Circuits 1173 14.3.3 Domino CMOS Logic Domino CMOS logic is a form of dynamic logic that results in cascadable gates. Figure 14.23 shows the structure of the Domino CMOS logic gate. We observe that it is simply the basic dynamic logic gate of Fig. 14.19(a) with a static CMOS inverter connected to its output.
Operation of the gate is straightforward. During precharge, X will be raised to VDD, and the gate output Y will be at 0 V. During evaluation, depending on the combination of input vari-ables, either X will remain high and thus the output Y will remain low (tPHL = 0) or X will be brought down to 0 V and the output Y will rise to VDD (tPLH finite). Thus, during evaluation, the output either remains low or makes only one low-to-high transition.
To see why Domino CMOS gates can be cascaded, consider the situation in Fig. 14.24(a), where we show two Domino gates connected in cascade. For simplicity, we show single-input gates. At the end of precharge, X1 will be at VDD, Y1 will be at 0 V, X2 will be at VDD, and Y2 will be at 0 V. As in the preceding case, assume that A is high at the beginning of evaluation.
Thus, as φ goes up, capacitor CL1 will begin discharging, pulling X1 down. Meanwhile, the low input at the gate of Q2 keeps Q2 off, and CL2 remains fully charged. When vX1 falls below the threshold voltage of inverter I1, Y1 will go up, turning Q2 on, which in turn begins to dis-charge CL2 and pulls X2 low. Eventually, Y2 rises to VDD.
during which vY1 falls from VDD to Vt, at which time Qeq2 turns off and CL2 stops discharging. Assume that the process technology has the parameter values specified in Example 14.2; that for all NMOS transistors in the circuit of Fig. 14.22, = μm and CL1 = CL2 = 40 fF.
(a) Find and .
(b) Find the values of iD1 at vY1 = VDD and at vY1 = Vt. Hence determine an average value for iD1.
(c) Use the average value of iD1 found in (b) to determine an estimate for the interval Δt.
(d) Find the average value of iD2 during Δt. To simplify matters, take the average to be the value of iD2 obtained when the gate voltage vY1 is midway through its excursion (i.e., vY1 = 3 V). (Hint: Qeq2 will remain in saturation.) (e) Use the value of Δt found in (c) together with the average value of iD2 determined in (d) to find an estimate of the reduction in vY2 during Δt. Hence determine the final value of vY2.
Ans. (a) 1, 1; (b) 400 μA and 175 μA, for an average value of 288 μA; (c) 0.56 ns; (d) 100 μA; (e) ΔvY2 = 1.4 V, thus vY2 decreases to 3.6 V Figure E 14.10 W L ⁄ 4 μm 2 ⁄ Qeq1 VDD CL1 CL2 vY2 vY1 iD1 Qeq2 iD2 (W L ⁄ )eq1 (W L ⁄ )eq2 1174 Chapter 14 Advanced MOS and Bipolar Logic Circuits From this description, we see that because the output of the Domino gate is low at the beginning of evaluation, no premature capacitor discharge will occur in the subsequent gate in the cascade. As indicated in Fig. 14.24(b), output Y1 will make a 0-to-1 transition tPLH Figure 14.24 (a) Two single-input Domino CMOS logic gates connected in cascade. (b) Waveforms dur-ing the evaluation phase.
Figure 14.23 The Domino CMOS logic gate. The circuit con-sists of a dynamic-MOS logic gate with a static-CMOS inverter connected to the output. During evaluation, Y either will remain low (at 0 V) or will make one 0-to-1 transition (to VDD).
A B C PDN Qp Qe VDD Y X I Qp1 Q1 Qe1 A Qp2 Q2 Qe2 CL1 CL2 Y1 Y2 VDD I1 I2 X2 X1 (a) VDD 0 Y1 Y2 t (b) 14.4 Emitter-Coupled Logic (ECL) 1175 seconds after the rising edge of the clock. Subsequently, output Y2 makes a 0-to-1 transition after another tPLH interval. The propagation of the rising edge through a cascade of gates resembles contiguously placed dominoes falling over, each toppling the next, which is the ori-gin of the name Domino CMOS logic. Domino CMOS logic finds application in the design of address decoders in memory chips, for example.
14.3.4 Concluding Remarks Dynamic logic presents many challenges to the circuit designer. Although it can provide considerable reduction in the chip-area requirement, as well as high-speed operation, and zero (or little) static-power dissipation, the circuits are prone to many nonideal effects, some of which have been discussed here. It should also be remembered that dynamic power dissi-pation is an important issue in dynamic logic. Another factor that should be considered is the “dead time” during precharge when the output of the circuit is not yet available.
14.4 Emitter-Coupled Logic (ECL) Emitter-coupled logic (ECL) is the fastest logic circuit family available for conventional logic-system design.4 High speed is achieved by operating all bipolar transistors out of saturation, thus avoiding storage-time delays, and by keeping the logic signal swings relatively small (about 0.8 V or less), thus reducing the time required to charge and discharge the various load and parasitic capacitances. Saturation in ECL is avoided by using the BJT differential pair as a current switch.5 The BJT differential pair was studied in Chapter 8, and we urge the reader to review the introduction given in Section 8.3 before proceeding with the study of ECL.
14.4.1 The Basic Principle Emitter-coupled logic is based on the use of the current-steering switch introduced in Section 13.1 (Fig 13.9). Such a switch can be most conveniently realized using the differential pair shown in Fig. 14.25. The pair is biased with a constant-current source I, and one side is con-nected to a reference voltage VR. As shown in Section 8.3, the current I can be steered to either Q1 or Q2 under the control of the input signal vI. Specifically, when vI is greater than VR by about 4VT (100 mV), nearly all the current I is conducted by Q1, and thus for α1 1, vO1 = VCC − IRC. Simultaneously, the current through Q2 will be nearly zero, and thus vO2 = VCC. Con-versely, when vI is lower than VR by about 4VT, most of the current I will flow through Q2 and the current through Q1 will be nearly zero. Thus vO1 = VCC and vO2 = VCC − IRC.
The preceding description suggests that as a logic element, the differential pair realizes an inversion function at vO1 and simultaneously provides the complementary output signal at vO2. The output logic levels are VOH = VCC and VOL = VCC − IRC, and thus the output logic swing is IRC. A number of additional remarks can be made concerning this circuit: 4Although higher speeds of operation can be obtained with gallium arsenide (GaAs) circuits, the latter are not available as off-the-shelf components for conventional digital system design. GaAs digital cir-cuits are not covered in this book; however, a substantial amount of material on this subject can be found on the CD accompanying the book and on the website.
5This is in sharp contrast to the technique utilized in a nonsaturating variant of transistor-transistor logic (TTL) known as Schottky TTL. There, a Schottky diode is placed across the CBJ junction to shunt away some of the base current and, owing to the low voltage drop of the Schottky diode, the CBJ is prevented from becoming forward biased.
1176 Chapter 14 Advanced MOS and Bipolar Logic Circuits 1. The differential nature of the circuit makes it less susceptible to picked-up noise. In particular, an interfering signal will tend to affect both sides of the differential pair similarly and thus will not result in current switching. This is the common-mode rejection property of the differential pair (see Section 8.3).
2. The current drawn from the power supply remains constant during switching. Thus, unlike CMOS (and TTL), no supply current spikes occur in ECL, eliminating an important source of noise in digital circuits. This is a definite advantage, especially since ECL is usually designed to operate with small signal swings and has corre-spondingly low noise margins.
3. The output signal levels are both referenced to VCC and thus can be made particularly stable by operating the circuit with VCC = 0: in other words, by utilizing a negative power supply and connecting the VCC line to ground. In this case, VOH = 0 and VOL = −IRC.
4. Some means must be provided to make the output signal levels compatible with those at the input so that one gate can drive another. As we shall see shortly, practi-cal ECL gate circuits incorporate a level-shifting arrangement that serves to center the output signal levels on the value of VR. 5. The availability of complementary outputs considerably simplifies logic design with ECL.
14.4.2 ECL Families Currently there are two popular forms of commercially available ECL—namely, ECL 10 K and ECL 100K. The ECL 100K series features gate delays on the order of 0.75 ns and 14.11 For the circuit in Fig. 14.25, let VCC = 0, I = 4 mA, RC = 220 Ω, VR = –1.32 V, and assume α 1.
Determine VOH and VOL. By how much should the output levels be shifted so that the values of VOH and VOL become centered on VR? What will the shifted values of VOH and VOL be?
Ans. 0; −0.88 V; −0.88 V; −0.88 V, −1.76 V EXERCISE vI vO1 vO2 VR RC RC Q1 Q2 iC2 iC1 VCC I Figure 14.25 The basic element of ECL is the dif-ferential pair. Here, VR is a reference voltage.
14.4 Emitter-Coupled Logic (ECL) 1177 dissipates about 40 mW/gate, for a delay–power product of 30 pJ. Although its power dissi-pation is relatively high, the 100K series provides the shortest available gate delay in small-and medium-scale integrated circuit packages.
The ECL 10 K series is slightly slower; it features a gate propagation delay of 2 ns and a power dissipation of 25 mW for a delay–power product of 50 pJ. Although the value of PDP is higher than that obtained in the 100K series, the 10K series is easier to use. This is because the rise and fall times of the pulse signals are deliberately made longer, thus reduc-ing signal coupling, or cross talk, between adjacent signal lines. ECL 10K has an “edge speed” of about 3.5 ns, compared with the approximately 1 ns of ECL 100K. To give con-creteness to our study of ECL, in the following we shall consider the popular ECL 10K in some detail. The same techniques, however, can be applied to other types of ECL.
In addition to its usage in SSI and MSI circuit packages, ECL is also employed in large-scale and VLSI applications. A variant of ECL known as current-mode logic (CML) is uti-lized in VLSI applications (see Treadway, 1989, and Wilson, 1990).
14.4.3 The Basic Gate Circuit The basic gate circuit of the ECL 10K family is shown in Fig. 14.26. The circuit consists of three parts. The network composed of Q1, D1, D2, R1, R2, and R3 generates a reference voltage VR whose value at room temperature is –1.32 V. As will be shown, the value of this reference voltage is made to change with temperature in a predetermined manner to keep the noise margins almost constant. Also, the reference voltage VR is made relatively insensitive to variations in the power-supply voltage VEE.
14.12 Figure E14.12 shows the circuit that generates the reference voltage VR. Assuming that the voltage drop across each of D1, D2, and the base–emitter junction of Q1 is 0.75 V, calculate the value of VR.
Neglect the base current of Q1.
Ans. −1.32 V D D Figure E14.12 EXERCISE 1178 Chapter 14 Advanced MOS and Bipolar Logic Circuits 1 1 Emitter–follower outputs D D Figure 14.26 Basic circuit of the ECL 10K logic-gate family.
14.4 Emitter-Coupled Logic (ECL) 1179 The second part, and the heart of the gate, is the differential amplifier formed by QR and either QA or QB. This differential amplifier is biased not by a constant-current source, as was done in the circuit of Fig. 14.25, but with a resistance RE connected to the negative supply –VEE. Nevertheless, we will shortly show that the current in RE remains approxi-mately constant over the normal range of operation of the gate. One side of the differential amplifier consists of the reference transistor QR, whose base is connected to the reference volt-age VR. The other side consists of a number of transistors (two in the case shown), connected in parallel, with separated bases, each connected to a gate input. If the voltages applied to A and B are at the logic-0 level, which, as we will soon find out, is about 0.4 V below VR, both QA and QB, will be off and the current IE in RE will flow through the reference transistor QR.
The resulting voltage drop across RC2 will cause the collector voltage of QR to be low.
On the other hand, when the voltage applied to A or B is at the logic-1 level, which, as we will show shortly, is about 0.4 V above VR, transistor QA or QB, or both, will be on and QR will be off. Thus the current IE will flow through QA or QB, or both, and an almost equal cur-rent will flow through RC1. The resulting voltage drop across RC1 will cause the collector voltage to drop. Meanwhile, since QR is off, its collector voltage rises. We thus see that the voltage at the collector of QR will be high if A or B, or both, is high, and thus at the collector of QR, the OR logic function, A + B, is realized. On the other hand, the common collector of QA and QB will be high only when A and B are simultaneously low. Thus at the common col-lector of QA and QB, the logic function is realized. We therefore conclude that the two-input gate of Fig. 14.26 realizes the OR function and its complement, the NOR function. The availability of complementary outputs is an important advantage of ECL; it simplifies logic design and avoids the use of additional inverters with associated time delay.
It should be noted that the resistance connecting each of the gate input terminals to the neg-ative supply enables the user to leave an unused input terminal open: An open input terminal will be pulled down to the negative supply voltage, and its associated transistor will be off.
The third part of the ECL gate circuit is composed of the two emitter followers, Q2 and Q3. The emitter followers do not have on-chip loads, since in many applications of high-speed logic circuits the gate output drives a transmission line terminated at the other end, as indicated in Fig. 14.27. (More on this later in Section 14.4.6.) The emitter followers have two purposes: First, they shift the level of the output signals by one VBE drop. Thus, using the results of Exercise 14.13, we see that the output levels become approximately −1.75 V and −0.75 V. These shifted levels are centered approxi-mately around the reference voltage (VR = −1.32 V), which means that one gate can drive another. This compatibility of logic levels at input and output is an essential requirement in the design of gate circuits.
The second function of the output emitter followers is to provide the gate with low out-put resistances and with the large output currents required for charging load capacitances.
AB = A B + 14.13 With input terminals A and B in Fig. 14.26 left open, find the current IE through RE. Also find the voltages at the collector of QR and at the common collector of the input transistors QA and QB.
Use VR = −1.32 V, VBE of QR 0.75 V, and assume that β of QR is very high.
Ans. 4 mA; –1 V; 0 V EXERCISE 1180 Chapter 14 Advanced MOS and Bipolar Logic Circuits Since these large transient currents can cause spikes on the power-supply line, the collectors of the emitter followers are connected to a power-supply terminal VCC1 separate from that of the differential amplifier and the reference-voltage circuit, VCC2. Here we note that the sup-ply current of the differential amplifier and the reference circuit remains almost constant.
The use of separate power-supply terminals prevents the coupling of power-supply spikes from the output circuit to the gate circuit and thus lessens the likelihood of false gate switching. Both VCC1 and VCC2 are of course connected to the same system ground, external to the chip.
14.4.4 Voltage-Transfer Characteristics Having provided a qualitative description of the operation of the ECL gate, we shall now derive its voltage-transfer characteristics. This will be done under the conditions that the outputs are terminated in the manner indicated in Fig. 14.27. Assuming that the B input is low and thus QB is off, the circuit simplifies to that shown in Fig. 14.28. We wish to analyze this circuit to determine vOR versus vI and vNOR versus vI (where vI ≡ vA).
Figure 14.27 The proper way to connect high-speed logic gates such as ECL. Properly terminating the transmission line connecting the two gates eliminates the “ringing” that would otherwise corrupt the logic signals. (See Section 14.4.6.) Figure 14.28 Simplified version of the ECL gate for the purpose of finding transfer characteristics.
R 14.4 Emitter-Coupled Logic (ECL) 1181 In the analysis to follow we shall make use of the exponential iC–vBE characteristic of the BJT. Since the BJTs used in ECL circuits have small areas (in order to have small capaci-tances and hence high fT), their scale currents IS are small. We will therefore assume that at an emitter current of 1 mA, an ECL transistor has a VBE drop of 0.75 V.
The OR Transfer Curve Figure 14.29 is a sketch of the OR transfer characteristic, vOR versus vI, with the parameters VOL, VOH, VIL, and VIH indicated. However, to simplify the cal-culation of VIL and VIH, we shall use an alternative to the unity-gain definition. Specifically, we shall assume that at point x, transistor QA is conducting 1% of IE while QR is conducting 99% of IE. The reverse will be assumed for point y. Thus at point x we have Using the exponential iE–vBE relationship, we obtain which gives Assuming QA and QR to be matched, we can write which can be used to find VIH as To obtain VOL, we note that QA is off and QR carries the entire current IE, given by Figure 14.29 The OR transfer characteristic vOR versus vI, for the circuit in Fig. 14.28.
IE QR IE QA ----------- = 99 V BE QR V BE QA – = VT 99 ln = 115 mV V IL = 1.32 – 0.115 = – 1.435 V – V IH − VR = VR − VIL V IH 1.205 V – = IE VR VBE QR – V EE + RE -----------------------------------------= 1182 Chapter 14 Advanced MOS and Bipolar Logic Circuits 4 mA (If we wish, we can iterate to determine a better estimate of and hence of IE.) Assum-ing that QR has a high β so that its α 1, its collector current will be approximately 4 mA.
If we neglect the base current of Q2, we obtain for the collector voltage of QR Thus a first approximation for the value of the output voltage VOL is −0.98 − 0.75 = −1.73 V We can use this value to find the emitter current of Q2 and then iterate to determine a better estimate of its base–emitter voltage. The result is and, correspondingly, At this value of output voltage, Q2 supplies a load current of about 4.6 mA.
To find the value of VOH we assume that QR is completely cut off (because ).
Thus the circuit for determining VOH simplifies to that in Fig. 14.30. Analysis of this circuit, assuming results in and 1.32 – − 0.75 + 5.2 0.779 ----------------------------------------------= VBE QR VC QR 4 0.245 × – 0.98 V – = V OL = VC QR −V BE Q2 V BE2 0.79 V V OL 1.77 V – vI V IH > β2 = 100, VBE2 0.83 V, IE2 = 22.4 mA, V OH 0.88 V – Figure 14.30 Circuit for determining VOH.
14.14 For the circuit in Fig. 14.28, determine the values of IE obtained when vI = VIL, VR, and VIH. Also, find the value of vOR corresponding to vI = VR. Assume that vBE = 0.75 V at a current of 1 mA.
Ans. 3.97 mA; 4.00 mA; 4.12 mA; −1.31 V EXERCISE 14.4 Emitter-Coupled Logic (ECL) 1183 Noise Margins The results of Exercise 14.14 indicate that the bias current IE remains approximately constant. Also, the output voltage corresponding to vI = VR is approximately equal to VR. Notice further that this is also approximately the midpoint of the logic swing; specifically, Thus the output logic levels are centered around the midpoint of the input transition band.
This is an ideal situation from the point of view of noise margins, and it is one of the reasons for selecting the rather arbitrary-looking numbers ( and VEE = 5.2 V) for refer-ence and supply voltages.
The noise margins can now be evaluated as follows: = −0.88 − (−1.205) = 0.325 V = −1.435 − (−1.77) = 0.335 V Note that these values are approximately equal. The NOR Transfer Curve The NOR transfer characteristic, which is vNOR versus vI for the circuit in Fig. 14.28, is sketched in Fig. 14.31. The values of VIL and VIH are identical to those found earlier for the OR characteristic. To emphasize this, we have labeled the thresh-old points x and y, the same letters used in Fig. 14.29.
For QA is off and the output voltage vNOR can be found by analyzing the circuit composed of RC1, Q3, and its 50-Ω termination. Except that RC1 is slightly smaller than RC2, this circuit is identical to that in Fig. 14.30. Thus the output voltage will be only slightly greater than the value VOH found earlier. In the sketch of Fig. 14.31 we have assumed that the output voltage is approximately equal to VOH.
For QA is on and is conducting the entire bias current. The circuit then simpli-fies to that in Fig. 14.32. This circuit can be easily analyzed to obtain vNOR versus vI for the Figure 14.31 The NOR transfer characteristic, vNOR versus vI, for the circuit in Fig. 14.28.
V OL V OH + 2 ------------------------1.325 V R – = V R = 1.32 V – NMH = V OH VIH – NML = V IL V OL – vI VIL, < vI V IH, > 1184 Chapter 14 Advanced MOS and Bipolar Logic Circuits range A number of observations are in order. First, note that results in an output voltage slightly higher than VOL. This is because RC1 is smaller than RC2. In fact, RC1 is chosen lower in value than RC2 so that with vI equal to the normal logic-1 value (i.e., VOH, which is approximately −0.88 V), the output will be equal to the VOL value found earlier for the OR output.
Second, note that as vI exceeds VIH, transistor QA operates in the active mode and the circuit of Fig. 14.32 can be analyzed to find the gain of this amplifier, which is the slope of the segment yz of the transfer characteristic. At point z, transistor QA saturates. Further increments in vI (beyond the point vI = VS) cause the collector voltage and hence vNOR to increase. The slope of the segment of the transfer characteristic beyond point z, however, is not unity, but is about 0.5, because as QA is driven deeper into saturation, a portion of the increment in vI appears as an increment in the base–collector forward-bias voltage.
The reader is urged to solve Exercise 14.15, which is concerned with the details of the NOR transfer characteristic.
Manufacturers’ Specifications ECL manufacturers supply gate transfer characteris-tics of the form shown in Figs. 14.29 and 14.31. A manufacturer usually provides such curves measured at a number of temperatures. In addition, at each relevant temperature, worst-case values for the parameters VIL, VIH, VOL, and VOH are given. These worst-case values are specified with the inevitable component tolerances taken into account. As an example, Motorola specifies that for MECL 10,000 at 25°C, the following worst-case Figure 14.32 Circuit for finding vNOR versus vI for the range vI > VIH.
vNOR vI vI V IH.
≥ vI = V IH 14.15 Consider the circuit in Fig. 14.32. (a) For vI = VIH = −1.205 V, find vNOR. (b) For vI = V OH = −0.88 V, find vNOR. (c) Find the slope of the transfer characteristic at the point vI = VOH = −0.88 V.
(d) Find the value of vI at which QA saturates (i.e., VS). Assume that VBE = 0.75 V at a current of 1 mA, VCEsat 0.3 V, and β = 100.
Ans. (a) −1.70 V; (b) −1.79 V; (c) −0.24 V/V; (d) −0.58 V EXERCISE 14.4 Emitter-Coupled Logic (ECL) 1185 values apply6 These values can be used to determine worst-case noise margins, which are about half the typical values previously calculated.
For additional information on MECL specifications the interested reader is referred to the Motorola (1988, 1989) publications listed in the bibliography in Appendix G.
14.4.5 Fan-Out When the input signal to an ECL gate is low (VOL), the input current is equal to the current that flows in the 50-kΩ pull-down resistor. Thus, When the input is high (VOH), the input current is greater because of the base current of the input transistor. Thus, assuming a transistor β of 100, we obtain Both these current values are quite small, which, coupled with the very small output resis-tance of the ECL gate, ensures that little degradation of logic-signal levels results from the input currents of fan-out gates. It follows that the fan-out of ECL gates is not limited by logic-level considerations but rather by the degradation of the circuit speed (rise and fall times). This latter effect is due to the capacitance that each fan-out gate presents to the driving gate (approximately 3 pF). Thus while the dc fan-out can be as high as 90 and thus does not represent a design prob-lem, the ac fan-out is limited by considerations of circuit speed to 10 or so.
14.4.6 Speed of Operation and Signal Transmission The speed of operation of a logic family is measured by the delay of its basic gate and by the rise and fall times of the output waveforms. Typical values of these parameters for ECL have already been given. Here we should note that because the output circuit is an emitter follower, the rise time of the output signal is shorter than its fall time, since on the rising edge of the output pulse, the emitter follower functions and provides the output current required to charge up the load and parasitic capacitances. On the other hand, as the signal at the base of the emitter follower falls, the emitter follower cuts off, and the load capacitance discharges through the combination of load and pull-down resistances.
To take full advantage of the very high speed of operation possible with ECL, special attention should be paid to the method of interconnecting the various logic gates in a system.
To appreciate this point, we shall briefly discuss the problem of signal transmission.
ECL deals with signals whose rise times may be 1 ns or even less, the time it takes for light to travel only 30 cm or so. For such signals, a wire and its environment become a rela-tively complex circuit element along which signals propagate with finite speed (perhaps half the speed of light—i.e., 15 cm/ns). Unless special care is taken, energy that reaches the end 6MECL is the trade name used by Motorola (now Freescale Semiconductors) for its ECL.
VILmax = 1.475 V – V IHmin = 1.105 V – V OLmax = 1.630 V – V OHmin = 0.980 V – NML = 0.155 V NMH = 0.125 V I IL = −1.77 5.2 + 50 --------------------------- 69 μA IIH −0.88 5.2 + 50 ---------------------------4 101 --------- 126 μA + = 1186 Chapter 14 Advanced MOS and Bipolar Logic Circuits of such a wire is not absorbed but rather returns as a reflection to the transmitting end, where (without special care) it may be re-reflected. The result of this process of reflection is what can be observed as ringing, a damped oscillatory excursion of the signal about its final value.
Unfortunately, ECL is particularly sensitive to ringing because the signal levels are so small. Thus it is important that transmission of signals be well controlled, and surplus energy absorbed, to prevent reflections. The accepted technique is to limit the nature of con-necting wires in some way. One way is to insist that they be very short, where “short” is taken to mean with respect to the signal rise time. The reason for this is that if the wire con-nection is so short that reflections return while the input is still rising, the result becomes only a somewhat slowed and “bumpy” rising edge.
If, however, the reflection returns after the rising edge, it produces not simply a modifi-cation of the initiating edge but an independent second event. This is clearly bad! Thus the time taken for a signal to go from one end of a line and back is restricted to less than the rise time of the driving signal by some factor—say, 5. Thus for a signal with a 1-ns rise time and for propagation at the speed of light (30 cm/ns), a double path of only 0.2-ns equivalent length, or 6 cm, would be allowed, representing in the limit a wire only 3 cm from end to end.
Such is the restriction on ECL 100K. However, ECL 10K has an intentionally slower rise time of about 3.5 ns. Using the same rules, wires can accordingly be as long as about 10 cm for ECL 10K.
If greater lengths are needed, then transmission lines must be used. These are simply wires in a controlled environment in which the distance to a ground reference plane or a second wire is highly controlled. Thus they might simply be twisted pairs of wires, one of which is grounded, or parallel ribbon wires, every second of which is grounded, or so-called microstrip lines on a printed-circuit board. The latter are simply copper strips of controlled geometry on one side of a thin printed-circuit board, the other side of which consists of a grounded plane.
Such transmission lines have a characteristic impedance, R0, that ranges from a few tens of ohms to hundreds of ohms. Signals propagate on such lines somewhat more slowly than the speed of light, perhaps half as fast. When a transmission line is terminated at its receiv-ing end in a resistance equal to its characteristic impedance, R0, all the energy sent on the line is absorbed at the receiving end, and no reflections occur (since the termination acts as a limitless length of transmission line). Thus, signal integrity is maintained. Such transmission lines are said to be properly terminated. A properly terminated line appears at its sending end as a resistor of value R0. The followers of ECL 10K with their open emitters and low out-put resistances (specified to be 7 Ω maximum) are ideally suited for driving transmission lines. ECL is also good as a line receiver. The simple gate with its high (50-kΩ) pull-down input resistor represents a very high resistance to the line. Thus a few such gates can be con-nected to a terminated line with little difficulty. Both these ideas are represented in Fig. 14.27.
14.4.7 Power Dissipation Because of the differential-amplifier nature of ECL, the gate current remains approximately constant and is simply steered from one side of the gate to the other depending on the input logic signals. Thus, the supply current and hence the gate power dissipation of unterminated ECL remain relatively constant independent of the logic state of the gate. It follows that no voltage spikes are introduced on the supply line. Such spikes can be a dangerous source of noise in a digital system. It follows that in ECL the need for supply-line bypassing7 is not as great as in, say, TTL. This is another advantage of ECL.
7Achieved by connecting capacitances to ground at frequent intervals along the power-supply line on a printed-circuit board.
14.4 Emitter-Coupled Logic (ECL) 1187 At this juncture we should reiterate a point we made earlier, namely, that although an ECL gate would operate with and the selection of and is recommended, because in the circuit, all signal levels are referenced to VCC, and ground is certainly an excellent reference.8 14.4.8 Thermal Effects In our analysis of the ECL gate of Fig. 14.26, we found that at room temperature the ref-erence voltage VR is −1.32 V. We have also shown that the midpoint of the output logic swing is approximately equal to this voltage, which is an ideal situation in that it results in equal high and low noise margins. In Example 14.4, we shall derive expressions for the tem-perature coefficients of the reference voltage and of the output low and high voltages. In this way, it will be shown that the midpoint of the output logic swing varies with temperature at the same rate as the reference voltage. As a result, although the magnitudes of the high and low noise margins change with temperature, their values remain equal. This is an added advantage of ECL and provides a demonstration of the high degree of design optimization of this gate circuit.
8 VEE = 0 V CC = +5.2 V, V EE = 5.2 V – V CC = 0 V 14.16 For the ECL gate in Fig. 14.26, calculate an approximate value for the power dissipated in the cir-cuit under the condition that all inputs are low and that the emitters of the output followers are left open. Assume that the reference circuit supplies four identical gates, and hence only a quarter of the power dissipated in the reference circuit should be attributed to a single gate.
Ans. 22.4 mW EXERCISE Example 14.4 We wish to determine the temperature coefficient of the reference voltage VR and of the midpoint between VOL and VOH.
Solution To determine the temperature coefficient of VR, consider the circuit in Fig. E14.12 and assume that the temperature changes by +1°C. Denoting the temperature coefficient of the diode and transistor voltage drops by δ, where δ −2 mV/°C, we obtain the equivalent circuit shown in Fig. 14.33. In the latter cir-cuit, the changes in device voltage drops are considered as signals, and hence the power supply is shown as a signal ground.
In the circuit of Fig. 14.33 we have two signal generators, and we wish to analyze the circuit to deter-mine ΔVR, the change in VR. We shall do so using the principle of superposition.8 Consider first the branch R1, D1, D2, 2δ, and R2, and neglect the signal base current of Q1. The voltage signal at the base of Q1 can be easily obtained from 8Although the circuit contains diodes and a transistor, which are nonlinear elements, we can use super-position because we are dealing with small changes in voltages and currents, and thus the diodes and the transistor are replaced by their linear small-signal models.
1188 Chapter 14 Advanced MOS and Bipolar Logic Circuits where rd1 and rd2 denote the incremental resistances of diodes D1 and D2, respectively. The dc bias current through D1 and D2 is approximately 0.64 mA, and thus Hence Since the gain of the emitter follower Q1 is approximately unity, it follows that the component of ΔVR due to the generator 2δ is approximately equal to vb1; that is, ΔVR1 = 0.3δ.
Consider next the component of ΔVR due to the generator δ. Reflection into the emitter circuit of the total resistance of the base circuit, , by dividing it by β + 1 results in the following component of ΔVR: Here RB denotes the total resistance in the base circuit, and re1 denotes the emitter resistance of This calculation yields Adding this value to that due to the generator 2δ gives Thus for δ = −2 mV/°C, the temperature coefficient of VR is +1.4 mV/°C.
We next consider the determination of the temperature coefficient of VOL. The circuit on which to per-form this analysis is shown in Fig. 14.34. Here we have three generators whose contributions can be con-sidered separately and the resulting components of ΔVOL summed. The result is Substituting the values given and those obtained throughout the analysis of this section, we find VR D D Figure 14.33 Equivalent circuit for determining the temperature coefficient of the reference voltage VR.
vb1 2δ R1 × R1 rd1 rd2 R2 + + + --------------------------------------------= rd1 = rd2 = 39.5 Ω.
vb1 0.3δ.
R1|| rd1 rd2 R2 + + ( ) [ ] with β 100 ( ) ΔVR2 δ R3 × RB β 1 + ( ) ⁄ [ ] re1 R3 + + ----------------------------------------------------------– = Q1 40 Ω ( ).
ΔVR2 δ.
– ΔVR 0.7δ – .
ΔVOL ΔVR RC2 – reR RE + ------------------- RT RT re2 + -------------------δ – RC2 – reR RE + ------------------- RT RT re2 + -------------------δ – RT RT re2 R + C2 β 1 + ( ) ⁄ + -------------------------------------------------------ΔVOL 0.43δ – Example 14.4 continued 14.4 Emitter-Coupled Logic (ECL) 1189 The circuit for determining the temperature coefficient of VOH is shown in Fig. 14.35, from which we obtain We now can obtain the variation of the midpoint of the logic swing as which is approximately equal to that of the reference voltage Figure 14.34 Equivalent circuit for determining the temperature coefficient of VOL.
ΔVOH = δ – RT RT re2 R + C2 β 1 + ( ) ⁄ + ------------------------------------------------------- = 0.93δ – ΔVOL ΔVOH + 2 --------------------------------- = 0.68δ – V R 0.7δ – ( ).
Figure 14.35 Equivalent circuit for determin-ing the temperature coefficient of VOH.
1190 Chapter 14 Advanced MOS and Bipolar Logic Circuits 14.4.9 The Wired-OR Capability The emitter–follower output stage of the ECL family allows an additional level of logic to be performed at very low cost by simply wiring the outputs of several gates in parallel. This is illustrated in Fig. 14.36, where the outputs of two gates are wired together. Note that the base–emitter diodes of the output followers realize an OR function: This wired-OR connec-tion can be used to provide gates with high fan-in as well as to increase the flexibility of ECL in logic design.
14.4.10 Final Remarks We have chosen to study ECL by focusing on a commercially available circuit family. As has been demonstrated, a great deal of design optimization has been applied to create a very-high-performance family of SSI and MSI logic circuits. As already mentioned, ECL and some of its variants are also used in VLSI circuit design. Applications include very-high-speed processors such as those used in supercomputers, as well as high-speed and high-frequency communication systems. When employed in VLSI design, current–source biasing is almost always utilized. Further, a variety of circuit configurations are employed (see Rabaey, 1996).
14.5 BiCMOS Digital Circuits In this section, we provide an introduction to a VLSI circuit technology that is becoming increasingly popular, BiCMOS. As its name implies, BiCMOS technology combines bipolar and CMOS circuits on one IC chip. The aim is to combine the low-power, high-input imped-ance and wide noise margins of CMOS with the high current-driving capability of bipolar transistors. Specifically, CMOS, although a nearly ideal logic-circuit technology in many respects, has a limited current-driving capability. This is not a serious problem when the CMOS gate has to drive a few other CMOS gates. It becomes a serious issue, however, when relatively large capacitive loads (e.g., greater than 0.5 pF or so) are present. In such cases, one has to either resort to the use of elaborate CMOS buffer circuits or face the usu-ally unacceptable consequence of long propagation delays. On the other hand, we know that by virtue of its much larger transconductance, the BJT is capable of large output currents.
We have seen a practical illustration of that in the emitter–follower output stage of ECL.
Figure 14.36 The wired-OR capability of ECL.
14.5 BiCMOS Digital Circuits 1191 Indeed, the high current-driving capability contributes to making ECL two to five times faster than CMOS (under equivalent conditions)—of course, at the expense of high power dissipation. In summary, then, BiCMOS seeks to combine the best of the CMOS and bipolar technologies to obtain a class of circuits that is particularly useful when output currents that are higher than possible with CMOS are needed. Furthermore, since BiCMOS technology is well suited for the implementation of high-performance analog circuits (see, e.g., Section 7.3.9), it makes possible the realization of both analog and digital functions on the same IC chip, making the “system on a chip” an attainable goal. The price paid is a more complex, and hence more expensive (than CMOS) processing technology.
14.5.1 The BiCMOS Inverter A variety of BiCMOS inverter circuits have been proposed and are in use. All of these are based on the use of npn transistors to increase the output current available from a CMOS inverter. This can be most simply achieved by cascading each of the QN and QP devices of the CMOS inverter with an npn transistor, as shown in Fig. 14.37(a). Observe that this cir-cuit can be thought of as utilizing the pair of complementary composite MOS-BJT devices shown in Fig. 14.37(b). These composite devices9 retain the high input impedance of the MOS transistor while in effect multiplying its rather low gm by the β of the BJT. It is also use-ful to observe that the output stage formed by Q1 and Q2 has what is known as the totem-pole configuration utilized by TTL.10 9It is interesting to note that these composite devices were proposed as early as 1969 (see Lin et al., 1969).
Figure 14.37 Development of the BiCMOS inverter circuit. (a) The basic concept is to use an additional bipolar transistor to increase the output current drive of each of QN and QP of the CMOS inverter. (b) The cir-cuit in (a) can be thought of as utilizing these composite devices. (c) To reduce the turn-off times of Q1 and Q2, “bleeder resistors” R1 and R2 are added. (d) Implementation of the circuit in (c) using NMOS transistors to realize the resistors. (e) An improved version of the circuit in (c) obtained by connecting the lower end of R1 to the output node.
10Refer to the CD accompanying this book or the book’s website for a description of the basic TTL logic-gate circuit and its totem-pole output stage.
(a) QP Q2 Q1 QN VDD vI vO (b) 1192 Chapter 14 Advanced MOS and Bipolar Logic Circuits The circuit of Fig. 14.37(a) operates as follows: When vI is low, both QN and Q2 are off while QP conducts and supplies Q1 with base current, thus turning it on. Transistor Q1 then provides a large output current to charge the load capacitance. The result is a very fast charg-ing of the load capacitance and correspondingly a short low-to-high propagation delay, tPLH.
Transistor Q1 turns off when vO reaches a value of about VDD − VBE1, and thus the output high level is lower than VDD, a disadvantage. When vI goes high, QP and Q1 turn off, and QN turns on, providing its drain current into the base of Q2. Transistor Q2 then turns on and provides a large output current that quickly discharges the load capacitance. Here again the result is a short high-to-low propagation delay, tPHL. On the negative side, Q2 turns off when vO reaches a value of about VBE2, and thus the output low level is greater than zero, a disadvantage.
Thus, while the circuit of Fig. 14.37(a) features large output currents and short propaga-tion delays, it has the disadvantage of reduced logic swing and, correspondingly, reduced noise margins. There is also another and perhaps more serious disadvantage, namely, the relatively long turn-off delays of Q1 and Q2 arising from the absence of circuit paths along which the base charge can be removed. This problem can be solved by adding a resistor between the base of each of Q1 and Q2 and ground, as shown in Fig. 14.37(c). Now when either Q1 or Q2 is turned off, its stored base charge is removed to ground through R1 or R2, respectively. Resistor R2 provides an additional benefit: With vI high, and after Q2 cuts off, vO continues to fall below VBE2, and the output node is pulled to ground through the series path of QN and R2. Thus R2 functions as a pull-down resistor. The QN–R2 path, however, is a high-impedance one with the result that pulling vO to ground is a rather slow process. Incor-porating the resistor R1, however, is disadvantageous from a static power-dissipation stand-point: When vI is low, a dc path exists between VDD and ground through the conducting QP and R1. Finally, it should be noted that R1 and R2 take some of the drain currents of QP and QN away from the bases of Q1 and Q2 and thus slightly reduce the gate output current avail-able to charge and discharge the load capacitance.
Figure 14.38 continued QP Q2 Q1 R1 R2 QN VDD vI vO (c) Q1 Q2 QR2 QP QR1 QN vI vO VDD (d) QP Q2 Q1 R1 R2 QN VDD vI vO (e) 14.5 BiCMOS Digital Circuits 1193 Figure 14.37(d) shows the way in which R1 and R2 are usually implemented. As indi-cated, NMOS devices QR1 and QR2 are used to realize R1 and R2. As an added innovation, these two transistors are made to conduct only when needed. Thus, QR1 will conduct only when vI rises, at which time its drain current constitutes a reverse base current for Q1, speed-ing up its turn-off. Similarly, QR2 will conduct only when vI falls and QP conducts, pulling the gate of QR2 high. The drain current of QR2 then constitutes a reverse base current for Q2, speeding up its turn-off.
As a final circuit for the BiCMOS inverter, we show the so-called R-circuit in Fig. 14.37(e).
This circuit differs from that in Fig. 14.37(c) in only one respect: Rather than returning R1 to ground, we have connected R1 to the output node of the inverter. This simple change has two benefits. First, the problem of static power dissipation is now solved. Second, R1 now func-tions as a pull-up resistor, pulling the output node voltage up to VDD (through the conducting QP) after Q1 has turned off. Thus, the R circuit in Fig. 14.37(e) does in fact have output levels very close to VDD and ground.
As a final remark on the BiCMOS inverter, we note that the circuit is designed so that transistors Q1 and Q2 are never simultaneously conducting and neither is allowed to saturate.
Unfortunately, sometimes the resistance of the collector region of the BJT in conjunction with large capacitive-charging currents causes saturation to occur. Specifically, at large out-put currents, the voltage developed across rC (which can be of the order of 100 Ω) can lower the voltage at the intrinsic collector terminal and cause the CBJ to become forward biased.
As the reader will recall, saturation is a harmful effect for two reasons: It limits the collector current to a value less than βIB, and it slows down the transistor turn-off.
14.5.2 Dynamic Operation A detailed analysis of the dynamic operation of the BiCMOS inverter circuit is a rather com-plex undertaking. Nevertheless, an estimate of its propagation delay can be obtained by con-sidering only the time required to charge and discharge a load capacitance C. Such an approximation is justified when C is relatively large and thus its effect on inverter dynamics is dominant: in other words, when we are able to neglect the time required to charge the parasitic capacitances present at internal circuit nodes. Fortunately, this is usually the case in practice, for if the load capacitance is not large, one would use the simpler CMOS inverter. In fact, it has been shown (Embabi, Bellaouar, and Elmasry, 1993) that the speed advantage of Bi-CMOS (over CMOS) becomes evident only when the gate is required to drive a large fan-out or a large load capacitance. For instance, at a load capacitance of 50 fF to 100 fF, BiCMOS and CMOS typically feature equal delays. However, at a load capacitance of 1 pF, tP of a BiC-MOS inverter is 0.3 ns, whereas that of an otherwise comparable CMOS inverter is about 1 ns.
Finally, in Fig. 14.38, we show simplified equivalent circuits that can be employed in obtaining rough estimates of tPLH and tPHL of the R-type BiCMOS inverter (see Problem 14.49).
14.5.3 BiCMOS Logic Gates In BiCMOS, the logic is performed by the CMOS part of the gate, with the bipolar portion simply functioning as an output stage. It follows that BiCMOS logic-gate circuits can be generated following the same approach used in CMOS. As an example, we show in Fig. 14.39 a BiCMOS two-input NAND gate.
As a final remark, we note that BiCMOS technology is applied in a variety of products including microprocessors, static RAMs, and gate arrays (see Alvarez, 1993).
1194 Chapter 14 Advanced MOS and Bipolar Logic Circuits Figure 14.39 Equivalent circuits for charging and discharging a load capacitance C. Note that C includes all the capacitances present at the output node.
Figure 14.40 A BiCMOS two-input NAND gate.
(a) QP Q1 R1 VDD i vO C (b) QN Q2 R2 VDD i vO C Y AB Q1 Q2 R2 R1 QNA QPA QPB QNB A B VDD A B D14.17 The threshold voltage of the BiCMOS inverter of Fig. 14.37(e) is the value of vI at which both QN and QP are conducting equal currents and operating in the saturation region. At this value of vI, Q2 will be on, causing the voltage at the source of QN to be approximately 0.7 V. It is required to design the circuit so that the threshold voltage is equal to . For VDD = 5 V, = 0.6 V, and assuming equal channel lengths for QN and QP and that μn 2.5 μp, find the required ratio of widths, Ans. 1 V DD 2 ⁄ Vt Wp Wn.
⁄ EXERCISE 14.5 BiCMOS Digital Circuits 1195 Summary Standard CMOS logic utilizes two transistors, an NMOS and a PMOS, for each input variable. Thus the circuit complexity, silicon area, and parasitic capaci-tance all increase with fan-in.
To reduce the device count, two other forms of static CMOS, namely, pseudo-NMOS and pass-transistor logic (PTL), are employed in special applications as supplements to standard CMOS.
Pseudo-NMOS utilizes the same PDN as in standard CMOS logic but replaces the PUN with a single PMOS transistor whose gate is grounded and thus is permanent-ly on. Unlike standard CMOS, pseudo-NMOS is a ratio-ed form of logic in which VOL is determined by the ratio r of kn to kp. Normally, r is selected in the range of 4 to 10 and its value determines the noise margins.
Pseudo-NMOS has the disadvantage of dissipating static power when the output of the logic gate is low.
Static power can be eliminated by turning the PMOS load on for only a brief interval, known as the precharge interval, to charge the capacitance at the output node to VDD. Then the inputs are applied, and depending on the input combination, the output node either remains high or is discharged through the PDN.
This is the essence of dynamic logic.
Pass-transistor logic utilizes either single NMOS transis-tors or CMOS transmission gates to implement a net-work of switches that are controlled by the input logic variables. Switches implemented by single NMOS transistors, though simple, result in the reduction of VOH from VDD to VDD − Vt.
The CMOS transmission gate, composed of the parallel connection of an NMOS and a PMOS transistor, is a very effective switch in both analog and digital applica-tions. It passes the entire input signal swing, 0 to VDD. As well, it has an almost constant “on” resistance over the full output range.
A particular form of dynamic logic circuits, known as Domino logic, allows the cascading of dynamic logic gates.
Emitter-coupled logic (ECL) is the fastest commercially available logic-circuit family. It achieves its high speed of operation by avoiding transistor saturation and by utilizing small logic-signal swings.
In ECL the input signals are used to steer a bias current between a reference transistor and an input transistor.
The basic gate configuration is that of a differential amplifier.
There are two popular commercially available ECL types: ECL 10K, having tP = 2 ns, PD = 25 mW, and PDP = 50 pJ; and ECL 100K, having tP = 0.75 ns, PD = 40 mW, and PDP = 30 pJ. ECL 10K is easier to use because the rise and fall times of its signals are deliberately made long (about 3.5 ns).
Because of the very high operating speeds of ECL, care should be taken in connecting the output of one gate to the input of another. Transmission-line techniques are usually employed.
The design of the ECL gate is optimized so that the noise margins are equal and remain equal as temperature changes.
The ECL gate provides two complementary outputs, realizing the OR and NOR functions.
The outputs of ECL gates can be wired together to real-ize the OR function of the individual output variables.
BiCMOS combines the low-power and wide noise mar-gins of CMOS with the high current-driving capability (and thus the short gate delays) of BJTs to obtain a tech-nology that is capable of implementing very dense, low-power, high-speed VLSI circuits that can also include analog functions.
PROBLEMS Problems involving design are marked with D throughout the text. As well, problems are marked with asterisks to describe their degree of difficulty. Difficult problems are marked with an asterisk (); more difficult problems with two asterisks (); and very challenging and/or time-con-suming problems with three asterisks ().
Section 14.1: Pseudo-NMOS Logic Circuits 14.1 The purpose of this problem is to compare the value of tPLH obtained with a resistive load (see Fig. P14.1a) to that obtained with a current–source load (see Fig. P14.1b). For a fair comparison, let the current source which is the initial current available to charge the capacitor in the case of a resistive load. Find tPLH for each case, and hence the percentage reduction obtained when a current–source load is used.
D 14.2 Design a pseudo-NMOS inverter that has equal capacitive charging and discharging currents at vO = for use in a system with VDD = 2.5 V, = 0.5 V, and (W/L)n = 1.5.
What are the values of ( )p, VIL, VIH, VM, VOH, VOL, NMH, and NML?
14.3 Find , , and for a pseudo-NMOS inverter fabricated in a 0.13-μm CMOS technology for which and Assume that the inverter has r = 4 and and that the equivalent load capacitance is 10 fF.
14.4 Use Eq. (14.13) to find the value of r for which NML is maximized. What is the corresponding value of NML for the case VDD = 2.5 V and Vt = 0.5 V ?
D 14.5 Design a pseudo-NMOS inverter that has VOL = 0.1 V .
Let and What is the value of ( )n? Calculate the values of NML and the static power dissipation.
14.6 For what value of r does NMH of a pseudo-NMOS inverter become zero? Prepare a table of NMH and NML versus r, for r = 1 to 16. Let VDD = 2.5 V and Vt= 0.5 V. 14.7 For a pseudo-NMOS inverter, what value of r results in NML = NMH? Let VDD = 2.5 V and = 0.5 V. What is the resulting margin?
D 14.8 It is required to design a minimum-area pseudo-NMOS inverter with equal high and low noise margins using a 2.5-V supply and devices for which = 0.5 V, , and the minimum-size device has ( ) = 1. Use r = 3.2 and show that NML NMH. Specify the values of ( )n and ( )p. What is the static power dissipated in this gate? What is the ratio of propagation delays for low-to-high and high-to-low transitions? For an equivalent load capacitance of 0.1 pF, find tPLH, tPHL, and tP.
At what frequency of operation would the static and dynamic power levels be equal? Is this speed of operation possible in view of the tP value you found?
D 14.9 Sketch a pseudo-NMOS realization of the function I VDD RD, ⁄ = QN vI C vO RD VDD 0 0 t VDD vI (a) QN vI C vO I VDD 0 0 t VDD vI (b) Figure P 14.1 VDD 4 ⁄ Vt kn ′ 115 μA V2, ⁄ = kp ′ 30μA V2, ⁄ = W L ⁄ tPLH tPHL tP VDD 1.2 V, = Vt 0.4 V, = μnCox 4μpCox = = 430 μA V2.
⁄ W L ⁄ ( )n 1 = VDD = 2.5 V, Vt = 0.5 V, k′ n 4k′p = 120 μA/V2, = (W L) p ⁄ 1.
= W L ⁄ Vt Vt k′ n = 4k′ p = 120 μA/V2 W L ⁄ W L ⁄ W L ⁄ Y A B C D + ( ) + .
= CHAPTER 14 P RO BL E MS Problems 1197 D 14.10 Sketch a pseudo-NMOS realization of the exclu-sive-OR function D 14.11 Consider a four-input pseudo-NMOS NOR gate in which the NMOS devices have ( )n = / It is required to find ( )p so that the worst-case value of VOL is 0.1 V. Let VDD = 1.8 V, and Assume that the minimum width possible is 0.2 μm.
14.12 This problem investigates the effect of velocity satu-ration (Section 13.5.2) on the operation of a pseudo-NMOS inverter fabricated in a 0.13-μm CMOS process for which , VDD = 1.2 V, Vt = 0.4 V, and Consider the case with and Note that will be operating in the velocity-saturation region. Find its current and use it to determine Section 10.2: Pass-Transistor Logic Circuits 14.13 Consider the NMOS transistor switch in the circuits of Figs. 14.8 and 14.9 to be fabricated in a 0.18-μm CMOS technology for which γ = 0.3 V1/2, and VDD = 1.8 V. Let the transistor have W/L = 1.5, and assume that the total capacitance between the output node and ground is C = 10 fF. (a) For the case find (b) If the output feeds a CMOS inverter having find the static current of the inverter and its power dissipation when the inverter input is at the value found in (a). Also, find the inverter output voltage.
(c) Find (d) For going low (Fig. 14.9), find (e) Find 14.14 A designer, beginning to experiment with the idea of pass-transistor logic, seizes upon what he sees as two good ideas: (a) that a string of minimum-size single MOS transistors can do complex logic functions, but (b) that there must always be a path between output and a supply terminal.
Correspondingly, he first considers two circuits (shown in Fig. P14.14). For each, express Y as a function of A and B. In each case, what can be said about general operation? About the logic levels at Y ? About node X ? Do either of these cir-cuits look familiar? If in each case the terminal connected to VDD is instead connected to the output of a CMOS inverter whose input is connected to a signal C, what does the func-tion Y become?
14.15 Consider the circuits in Fig. P14.14 with all PMOS transistors replaced with NMOS, and all NMOS by PMOS, and with ground and VDD connections interchanged. What do the output functions Y become?
14.16 An NMOS pass-transistor switch with used in a 3.3-V system for which Vt0 = 0.8 V, drives a 100-fF load capacitance at the input of a matched standard CMOS inverter using (W/L)n = For the switch gate terminal at VDD, eval-uate the switch VOH and VOL for inputs at VDD and 0 V, respec-tively. For this value of VOH, what inverter static current results? Estimate tPLH and tPHL for this arrangement as mea-sured from the input to the output of the switch itself.
D 14.17 The purpose of this problem is to design the level-restoring circuit of Fig. 14.10 and gain insight into its operation. Assume that = 0.5 V1/2 / and C = 20 fF. Let vB = VDD.
(a) Consider first the situation with vA = VDD. Find the value of the voltage vO1 that causes vO2 to drop a threshold voltage Y AB AB.
+ = W L ⁄ 0.27 μm 0.18 μm.
W L ⁄ Vt 0.5 V, = k′ n = 4k′p = 300 μA/V2.
μnCox 4μpCox = 430 μA V2, ⁄ = VDSsatp 0.6 V.
= vI VDD = vO VOL.
= QP IDsat VOL.
μnCox 4μpCox 300 μA V2, ⁄ = = Vt0 0.5 V, = 2φf 0.85 V, = vI VDD, = VOH.
W L ⁄ ( )p 2 W L ⁄ ( )n 0.54 μm 0.18 μm, ⁄ = = tPLH.
vI tPHL.
tP.
Figure P14.14 A A VDD B B X Y (a) A A VDD B B X Y (b) W L ⁄ = 1.2 μm 0.8 μm, ⁄ γ = 0.5 V1 2 ⁄ , 2φf = 0.6 V, μnCox = 3μpCox = 75 μA/V2, 1.2 μm 0.8 ⁄ μm.
k′n = 3k′ p = 75 μA/V2, VDD = 3.3 V, Vt0 = 0.8 V, γ 2φf = 0.6 V, (W L ⁄ )1 = (W L ⁄ )n = 1.2 μm 0.8 ⁄ μm, (W L ⁄ )p = 3.6 μm 0.8 μm, CHAPTER 14 PR OBLE MS 1198 Chapter 14 Advanced MOS and Bipolar Logic Circuits below VDD; that is, to 2.5 V so that QR turns on. At this value of vO1, find Vt of Q1. What is the capacitor-charging current available at this time (i.e., just prior to QR turning on)? What is it at vO1 = 0? What is the average current available for charging C? Estimate the time tPLH for vO1 to rise from 0 to the value at which QR turns on. Note that after QR turns on, vO1 rises to VDD.
(b) Now, to determine a suitable ratio for QR, con-sider the situation when vA is brought down to 0 V and Q1 conducts and begins to discharge C. The voltage vO1 will begin to drop. Meanwhile, vO2 is still low and QR is conduct-ing. The current that QR conducts subtracts from the current of Q1, reducing the current available to discharge C. Find the value of vO1 at which the inverter begins to switch. This is Then, find the current that Q1 con-ducts at this value of vO1. Choose for QR so that the maximum current it conducts is limited to one-half the value of the current in Q1. What is the you have chosen?
Estimate tPHL as the time for vO1 to drop from VDD to VIH.
14.18 Figure P14.18 shows a PMOS transistor operating as a switch in the on position.
(a) If initially and at t = 0, is raised to , what is the final value reached at the output?
(b) If initially, and at t = 0, is lowered to 0 V, what is the final value reached at the output?
(c) For the situation in (a), find for to rise from 0 to Let and 14.19 The transmission gate in Fig. 14.12(a) and 14.12(b) is fabricated in a CMOS process technology for which and Let and have The total capacitance at the output node is 15 fF.
(a) What are the values of and ?
(b) For the situation in Fig. 14.12(a), find , and (c) For the situation depicted in Fig. 14.12(b), find and At what value of will turn off?
(d) Find 14.20 For the transmission gate specified in Problem 14.19, find at and 0.9 V. Use the average of those values to determine for the situation in which C = 15 fF. 14.21 Refer to the situation in Fig. 14.12(b). Derive expressions for and following the approach used in Section 14.2.4 for the capacitor-charging case. Evaluate the value of for and for the process technology specified in Problem 14.19. Find the average value of and use it to determine for the case C = 15 fF.
14.22 A transmission gate for which (W/L)n = is fabricated in a 0.18-μm CMOS technol-ogy and used in a circuit for which C = 10 fF. Use Eq.
(14.36) to obtain an estimate of and hence of the prop-agation delay 14.23 Figure P14.23 shows a chain of transmission gates.
This situation often occurs in circuits such as adders and multiplexers. Consider the case when all the transmission gates are turned on and a step voltage is applied to the input. The propagation delay can be determined from the Elmore delay formula as follows: where is the resistance of each transmission gate, C is the capacitance between each node and ground, and n is the W L ⁄ VIH = 1 8 --- 5VDD 2Vt – ( ).
W L ⁄ W L ⁄ C vO vI Q Figure P14.18 vO 0 = vI VDD VOH vO VDD = vI VOL tPLH vO VDD 2 ⁄ .
kp 225 μA V2 ⁄ , = VDD 1.8 V, = Vtp 0.5 V.
= kn ′ 4kp ′ 300 μA V2, ⁄ = = Vt0 0.5 V, = γ 0.3 V1 2 ⁄ , = 2φf 0.85 V, = VDD 1.8 V.
= QN QP W L ⁄ ( )n W L ⁄ ( )p 1.5.
= = VOH VOL iDN 0 ( ) iDP 0 ( ), iDN tPLH ( ), iDP tPLH ( ), tPLH.
iDN 0 ( ), iDP 0 ( ), iDN tPHL ( ), iDP tPHL ( ), tPHL.
vO QP tP.
RTG vO 0 = tPLH RNeq, RPeq, RTG RTG vO VDD = vO VDD 2 ⁄ = RTG tPHL W L ⁄ ( )p 1.5 = RTG tP.
VDD tP tP 0.69 kCRTG k 0 = n ∑ = RTG C C C C vI VDD 0 t vO 1 2 3 n Figure P14.23 CHAPTER 14 P RO BL E MS Problems 1199 number of transmission gates in the chain. Note that the sum of the series in this formula is given by Now evaluate for the case of 16 transmission gates with and C = 10 fF.
D 14.24 (a) Use the idea embodied in the exclusive-OR realization in Fig. 14.17 to realize . That is, find a realization for using two transmission gates.
(b) Now combine the circuit obtained in (a) with the circuit in Fig. 14.17 to obtain a realization of the function Z = where C is a third input. Sketch the complete 12-transistor circuit realization of Z. Note that Z is a three-input exclusive-OR.
D 14.25 Using the idea presented in Fig. 14.18, sketch a CPL circuit whose outputs are and .
D 14.26 Extend the CPL idea in Fig. 14.18 to three vari-ables to form Z = ABC and Section 14.3: Dynamic MOS Logic Circuits D 14.27 Based on the basic dynamic logic circuit of Fig. 14.19, sketch complete circuits for NOT, NAND, and NOR gates, the latter two with two inputs, and a circuit for which 14.28 In this and the following problem, we investigate the dynamic operation of a two-input NAND gate realized in the dynamic logic form and fabricated in a CMOS pro-cess technology for which and VDD = 3 V. To keep CL small, minimum-size NMOS devices are used for which (this includes Qe). The PMOS precharge transistor Qp has The capacitance CL is found to be 30 fF. Consider the precharge operation with the gate of Qp at 0 V, and assume that at t = 0, CL is fully discharged. We wish to calculate the rise time of the output voltage, defined as the time for vY to rise from 10% to 90% of the final value of 3 V. Find the current at vY = 0.3 V and the current at vY = 2.7 V, then compute an approximate value for tr, where Iav is the aver-age value of the two currents.
14.29 For the gate specified in Problem 14.28, evaluate the high-to-low propagation delay, tPHL. To obtain an approximate value of tPHL, replace the three series NMOS transistors with an equivalent device and find the average discharge current.
14.30 The leakage current in a dynamic-logic gate causes the capacitor CL to discharge during the evaluation phase, even if the PDN is not conducting. For CL = 15 fF, and Ileakage = 10−12 A, find the longest allowable evaluate time if the decay in output voltage is to be limited to 0.2 V. If the precharge interval is much shorter than the maximum allow-able evaluate time, find the minimum clocking frequency required.
14.31 In this problem, we wish to calculate the reduction in the output voltage of a dynamic-logic gate as a result of charge redistribution. Refer to the circuit in Fig. 14.21(a), and assume that at t = 0−, vY = VDD, and vC1 = 0. At t = 0, φ goes high and QP turns off, and simultaneously the voltage at the gate of Q1 goes high (to VDD), turning Q1 on. Transistor Q1 will remain conducting until either the voltage at its source (vC1) reaches VDD − or until vY = vC1, whichever comes first. In both cases, the final value of vY can be found using charge conservation; that is, by equating the charge gained by C1 to the charge lost by CL.
(a) Convince yourself that the first situation obtains when (b) For each of the two situations, derive an expression for (c) Find an expression for the maximum ratio (C1/CL) for which (d) For = 1 V, VDD = 5 V, CL = 30 fF, and neglecting the body effect in Q1, find the drop in voltage at the output in the two cases: (a) C1 = 5 fF and (b) C1 = 10 fF.
14.32 Solve the problem in Exercise 14.10 symbolically (rather than numerically). Refer to Fig E14.10 and assume Qeq1 and Qeq2 to be identical with threshold voltages Vtn = 0.2VDD and transconductance parameters kn. Also, let CL1 = CL2. Derive an expression for the drop in the output voltage, ΔvY2.
14.33 For the four-input dynamic-logic NAND gate ana-lyzed in Example 14.3, estimate the maximum clocking fre-quency allowed.
Section 14.4: Emitter-Coupled Logic (ECL) D 14.34 For the ECL circuit in Fig. P14.34, the transis-tors exhibit VBE of 0.75 V at an emitter current I and have very high β.
(a) Find VOH and VOL.
(b) For the input at B that is sufficiently negative for QB to be cut off, what voltage at A causes a current of to flow in QR?
(c) Repeat (b) for a current in QR of 0.99I.
(d) Repeat (c) for a current in QR of 0.01I.
(e) Use the results of (c) and (d) to specify VIL and VIH.
(f) Find NMH and NML.
(g) Find the value of IR that makes the noise margins equal to the width of the transition region, VIH − VIL.
tP 0.69CRTG n n 1 + ( ) 2 --------------------= tP RTG 10 kΩ = Y = AB AB + Y YC YC, + Y = AB AB + Y = AB AB + Z ABC A B C.
+ + = = Y AB CD.
+ = k′ n = 3k′ p = 75 μA/V2, Vtn = Vtp – = 0.8 V, W L ⁄ = 1.2 μm 0.8 ⁄ μm 2.4 μm 0.8 ⁄ μm.
tr CL 2.7 0.3 – ( ) Iav ⁄ , = Vtn vY Δ Vtn.
≤ vY.
Δ vY Δ Vtn.
≤ Vtn I 2 ⁄ CHAPTER 14 PR OBLE MS 1200 Chapter 14 Advanced MOS and Bipolar Logic Circuits (h) Using the IR value obtained in (g), give numerical val-ues for VOH, VOL, VIH, VIL, and VR for this ECL gate.
14.35 Three logic inverters are connected in a ring.
Specifications for this family of gates indicate a typical propagation delay of 3 ns for high-to-low output transitions and 7 ns for low-to-high transitions. Assume that for some reason the input to one of the gates undergoes a low-to-high transition. By sketching the waveforms at the outputs of the three gates and keeping track of their relative positions, show that the circuit functions as an oscillator. What is the frequency of oscillation of this ring oscillator? In each cycle, how long is the output high? low?
14.36 Following the idea of a ring oscillator introduced in Problem 14.35, consider an implementation using a ring of five ECL 100K inverters. Assume that the inverters have linearly rising and falling edges (and thus the waveforms are trapezoidal in shape). Let the 0 to 100% rise and fall times be equal to 1 ns. Also, let the propagation delay (for both transi-tions) be equal to 1 ns. Provide a labeled sketch of the five output signals, taking care that relevant phase information is provided. What is the frequency of oscillation?
D 14.37 Using the logic and circuit flexibility of ECL indicated by Figs. 14.26 and 14.36, sketch an ECL logic cir-cuit that realizes the exclusive OR function, Give a logic diagram (as opposed to a circuit diagram).
14.38 For the circuit in Fig. 14.28 whose transfer charac-teristic is shown in Fig. 14.29, calculate the incremental volt-age gain from input to the OR output at points x, m, and y of the transfer characteristic. Assume β = 100. Use the results of Exercise 14.14, and let the output at x be −1.77 V and that at y be −0.88 V. (Hint: Recall that x and y are defined by a 1%, 99% current split.) 14.39 For the circuit in Fig. 14.28 whose transfer charac-teristic is shown in Fig. 14.29, find VIL and VIH if x and y are defined as the points at which (a) 90% of the current IE is switched. (b) 99.9% of the current IE is switched.
14.40 For the symmetrically loaded circuit of Fig. 14.28 and for typical output signal levels (VOH = −0.88 V and VOL = −1.77 V), calculate the power lost in both load resistors RT and both output followers. What then is the total power dissipation of a single ECL gate, including its symmetrical output terminations?
14.41 Considering the circuit of Fig. 14.30, what is the value of β of Q2, for which the high noise margin (NMH) is reduced by 50%?
14.42 Consider an ECL gate whose inverting output is terminated in a 50-Ω resistance connected to a −2-V supply.
Let the total load capacitance be denoted C. As the input of Y AB AB.
+ = D I R C A B Q2 I I I I R R 2 QA QB QR Q3 Q1 Figure P14.34 CHAPTER 14 P RO BL E MS Problems 1201 the gate rises, the output emitter follower cuts off and the load capacitance C discharges through the 50-Ω load (until the emitter follower conducts again). Find the value of C that will result in a discharge time of 1 ns. Assume that the two output levels are −0.88 V and −1.77 V.
14.43 For signals whose rise and fall times are 3.5 ns, what length of unterminated gate-to-gate wire interconnect can be used if a ratio of rise time to return time of 5 to 1 is required? Assume the environment of the wire to be such that the signal propagates at two-thirds the speed of light (which is 30 cm/ns).
14.44 For the circuit in Fig. P14.44, let the levels of the inputs A, B, C, and D be 0 and +5 V. For all inputs low at 0 V, what is the voltage at E? If A and C are raised to +5 V, what is the voltage at E? Assume and β = 50.
Express E as a logic function of A, B, C, and D. Section 14.5: BiCMOS Digital Circuits 14.45 Consider the conceptual BiCMOS circuit of Fig. 14.37(a), for the conditions that VDD = 5 V, VBE = 0.7 V, β = 100, and For find so that What is this totem-pole tran-sient current?
14.46 Consider the conceptual BiCMOS circuit of Fig. 14.37(a) for the conditions stated in Problem 14.45. What is the threshold voltage of the inverter if both QN and QP have What totem-pole current flows at vI equal to the threshold voltage?
D 14.47 Consider the choice of values for R1 and R2 in the circuit of Fig. 14.37(c). An important consideration in making this choice is that the loss of base drive current will be limited. This loss becomes particularly acute when the current through QN and QP becomes small. This in turn hap-pens near the end of the output signal swing when the asso-ciated MOS device is deeply in triode operation (say at Determine values for R1 and R2 so that the loss in base current is limited to 50%. What is the ratio Repeat for a 20% loss in base drive.
14.48 For the circuit of Fig. 14.37(a) with parameters as in Problem 14.45 and with estimate the propagation delays tPLH, tPHL and tP obtained for a load capaci-tance of 2 pF. Assume that the internal node capacitances do not contribute much to this result. Use average values for the charging and discharging currents.
14.49 Repeat Problem 14.48 for the circuit in Fig.
14.37(e), assuming that R1 = R2 = 5 kΩ.
D 14.50 Consider the dynamic response of the NAND gate of Fig. 14.39 with a large external capacitive load. If the worst-case response is to be identical to that of the inverter of Fig. 14.37(e), how must the ratios of QNA, QNB, QN, QPA, QPB, and QP be related?
D 14.51 Sketch the circuit of a BiCMOS two-input NOR gate. If, when loaded with a large capacitance, the gate is to have worst-case delays equal to the corresponding values of the inverter of Fig. 14.37(e), find of each transistor in terms of and VBE 0.7 V = C D 18 k 2.5 k 5 V Q5 Q3 Q6 Q1 Q2 Q4 A B E 18 k Figure P14.44 Vt = 1 V, kn ′ = 2.5k′p = 100 μA/V 2 , (W L ⁄ )n = 2 μm 1 μm.
⁄ vI vO VDD 2, ⁄ = = (W L ⁄ )p IEQ1 IEQ2.
= W L ⁄ = 2 μm 1 μm?
⁄ vDS Vt 3).
⁄ = R1 R2?
⁄ (W L ⁄ )p = (W L ⁄ )n, W L ⁄ W L ⁄ (W L ⁄ )n (W L ⁄ )p.
CHAPTER 15 Memory Circuits Introduction 1203 15.1 Latches and Flip-Flops 1204 15.2 Semiconductor Memories: Types and Architectures 1214 15.3 Random-Access Memory (RAM) Cells 1217 15.4 Sense Amplifiers and Address Decoders 1227 15.5 Read-Only Memory (ROM) 1240 Summary 1246 Problems 1246 1203 IN THIS CHAPTER YOU WILL LEARN: 1. How the basic bistable circuit, the latch, is realized by connecting two inverters in a positive-feedback loop.
2. How to augment the latch to obtain different types of flip-flops that are useful building blocks for digital systems.
3. How CMOS is particularly suited for the efficient implementation of a particular type of flip-flop, the D flip-flop.
4. How memory chips that contain as many as 4 gigabits are organized, as well as their various types and the terminology used to describe them.
5. The analysis and design of the six-transistor circuit that is almost univer-sally used to implement the storage cell in static random access memory (SRAM) and the one-transistor circuit that is equally universal in the im-plementation of the storage cell in dynamic random access memory (DRAM).
6. Interesting circuit techniques for accessing a particular storage cell in a memory chip and for amplifying the signal readout from the cell.
7. How various types of read-only memory (ROM) are designed, pro-grammed, erased, and reprogrammed.
Introduction The logic circuits studied in Chapters 13 and 14 are called combinational circuits. Their output depends only on the present value of the input. Thus these circuits do not have memory.
Memory is a very important part of digital systems. Its availability in digital computers allows for storing programs and data. Furthermore, it is important for temporary storage of the output produced by a combinational circuit for use at a later time in the operation of a digital system.
Logic circuits that incorporate memory are called sequential circuits; that is, their output depends not only on the present value of the input but also on the input’s previous values.
Such circuits require a timing generator (a clock) for their operation.
There are basically two approaches for providing memory to a digital circuit. The first relies on the application of positive feedback that, as will be seen shortly, can be arranged to provide a circuit with two stable states. Such a bistable circuit can then be used to store one bit of information: One stable state would correspond to a stored 0, and the other to a stored 1.
A bistable circuit can remain in either state indefinitely, and thus it belongs to the category 1204 Chapter 15 Memory Circuits of static sequential circuits. The other approach to realizing memory utilizes the storage of charge on a capacitor: When the capacitor is charged, it would be regarded as storing a 1; when it is discharged, it would be storing a 0. Since the inevitable leakage effects will cause the capacitor to discharge, such a form of memory requires the periodic recharging of the capacitor, a process known as refresh. Thus, like dynamic logic (Section 14.3), memory based on charge storage is known as dynamic memory and the corresponding sequential cir-cuits as dynamic sequential circuits. This chapter is concerned with the study of memory circuits. We begin in Section 15.1 with the basic bistable circuit, the latch, and its application in flip-flops, an important class of building blocks for digital systems. After an overview of memory-chip types, organiza-tion, and nomenclature in Section 15.2, we study the circuit of the static memory cell (SRAM) and that of the dynamic memory cell (DRAM) in Section 15.3. Besides the array of storage cells, memory chips require circuits for selecting and accessing a particular cell in the array (address decoders) and for amplifying the signal that is retrieved from a particular cell (sense amplifiers). A sampling of these peripheral circuits is presented in Section 15.4.
The chapter concludes with an important class of memories, the read-only memory (ROM) in Section 15.5.
15.1 Latches and Flip-Flops In this section, we shall study the basic memory element, the latch, and consider a sampling of its applications. Both static and dynamic circuits will be considered. 15.1.1 The Latch The basic memory element, the latch, is shown in Fig. 15.1(a). It consists of two cross-coupled logic inverters, G1 and G2. The inverters form a positive-feedback loop. To investigate the operation of the latch we break the feedback loop at the input of one of the inverters, say G1, and apply an input signal, vW, as shown in Fig. 15.1(b). Assuming that the input impedance of G1 is large, breaking the feedback loop will not change the loop voltage transfer charac-teristic, which can be determined from the circuit of Fig. 15.1(b) by plotting vZ versus vW.
This is the voltage transfer characteristic of two cascaded inverters and thus takes the shape shown in Fig. 15.1(c). Observe that the transfer characteristic consists of three segments, with the middle segment corresponding to the transition region of the inverters.
Also shown in Fig. 15.1(c) is a straight line with unity slope. This straight line represents the relationship vW = vZ that is realized by reconnecting Z to W to close the feedback loop and thus to return it to its original form. As indicated, the straight line intersects the loop transfer curve at three points, A, B, and C. Thus any of these three points can serve as the operating point for the latch. We shall now show that while points A and C are stable operating points in the sense that the circuit can remain at either indefinitely, point B is an unstable operating point; the latch cannot operate at B for any significant period of time.
The reason point B is unstable can be seen by considering the latch circuit in Fig. 15.1(a) to be operating at point B, and taking account of the electrical interference (or noise) that is inev-itably present in any circuit. Let the voltage vW increase by a small increment vw. The voltage at X will increase (in magnitude) by a larger increment, equal to the product of vw and the incre-mental gain of G1 at point B. The resulting signal vx is applied to G2 and gives rise to an even larger signal at node Z. The voltage vz is related to the original increment vw by the loop gain at point B, which is the slope of the curve of vZ versus vW at point B. This gain is usually much 15.1 Latches and Flip-Flops 1205 greater than unity. Since vz is coupled to the input of G1, it becomes the new value of vW and is further amplified by the loop gain. This regenerative process continues, shifting the operating point from B upward to point C, as illustrated in Fig. 15.2. Since at C the loop gain is zero (or almost zero), no regeneration can take place.
In the description above, we assumed arbitrarily an initial positive voltage increment at W. Had we instead assumed a negative voltage increment, we would have seen that the oper-ating point moves downward from B to A. Again, since at point A the slope of the transfer curve is zero (or almost zero), no regeneration can take place. In fact, for regeneration to occur, the loop gain must be greater than unity, which is the case at point B.
Figure 15.1 (a) Basic latch. (b) The latch with the feedback loop opened. (c) Determining the operating point(s) of the latch.
Figure 15.2 Point B is an unstable operating point for the latch: A small positive increment vw gets ampli-fied around the loop and causes the operating point to shift to the stable operating point C. Had vw been negative, the operating point would have shifted to the other stable point, A.
(a) G1 G2 G1 G2 vZ (b) (c) VOH B C A VOL vZ vw vz vW 1206 Chapter 15 Memory Circuits The discussion above leads us to conclude that the latch has two stable operating points, A and C. At point C, vW is high, vX is low, vY is low, and vZ is high. The reverse is true at point A. If we consider X and Z as the latch outputs, we see that in one of the stable states (say that corresponding to operating point A), vX is high (at VOH) and vZ is low (at VOL). In the other state (corresponding to operating point C), vX is low (at VOL) and vZ is high (at VOH). Thus the latch is a bistable circuit having two complementary outputs. The stable state in which the latch operates depends on the external excitation that forces it to the particular state. The latch then memorizes this external action by staying indefinitely in the acquired state. As a mem-ory element the latch is capable of storing one bit of information. For instance, we can arbi-trarily designate the state in which vX is high and vZ is low as corresponding to a stored logic 1. The other complementary state then is designated by a stored logic 0. Finally, we note that the latch circuit described is of the static variety.
It now remains to devise a mechanism by which the latch can be triggered to change state. The latch together with the triggering circuitry forms a flip-flop. This will be discussed next. Analog bistable circuits utilizing op amps will be presented in Chapter 17.
15.1.2 The SR Flip-Flop The simplest type of flip-flop is the set/reset (SR) flip-flop shown in Fig. 15.3(a). It is formed by cross-coupling two NOR gates, and thus it incorporates a latch. The second inputs of G1 and G2 together serve as the trigger inputs of the flip-flop. These two inputs are labeled S (for set) and R (for reset). The outputs are labeled Q and , emphasizing their complementarity. The flip-flop is considered to be set (i.e., storing a logic 1) when Q is high and is low. When the flip-flop is in the other state (Q low, high), it is considered to be reset (storing a logic 0).
In the rest or memory state (i.e., when we do not wish to change the state of the flip-flop), both the S and R inputs should be low. Consider the case when the flip-flop is storing a logic 0.
Since Q will be low, both inputs to the NOR gate G2 will be low. Its output will therefore be high. This high is applied to the input of G1, causing its output Q to be low, satisfying the original assumption. To set the flip-flop we raise S to the logic-1 level while leaving R at 0.
The 1 at the S terminal will force the output of G2, , to 0. Thus the two inputs to G1 will be 0 and its output Q will go to 1. Now even if S returns to 0, the Q = 1 signal fed to the input of G2 will keep = 0, and the flip-flop will remain in the newly acquired set state. Note that if we raise S to 1 again (with R remaining at 0), no change will occur. To reset the flip-flop we need to raise R to 1 while leaving S = 0. We can readily show that this forces the flip-flop into the reset state (Q = 0, = 1) and that the flip-flop remains in this state even after R has returned to 0. It should be observed that the trigger signal merely starts the regenerative action of the positive-feedback loop of the latch.
Q Q Q Q Q Q G1 G2 (a) (b) Figure 15.3 (a) The set/reset (SR) flip-flop and (b) its truth table.
15.1 Latches and Flip-Flops 1207 Finally, we inquire into what happens if both S and R are simultaneously raised to 1. The two NOR gates will cause both Q and to become 0 (note that in this case the complemen-tary labeling of these two variables is incorrect). However, if R and S return to the rest state (R = S = 0) simultaneously, the state of the flip-flop will be undefined. In other words, it will be impossible to predict the final state of the flip-flop. For this reason, this input combina-tion is usually disallowed (i.e., not used). Note, however, that this situation arises only in the idealized case, when both R and S return to 0 precisely simultaneously. In actual practice one of the two will return to 0 first, and the final state will be determined by the input that remains high longest.
The operation of the flip-flop is summarized by the truth table in Fig. 15.3(b), where Qn denotes the value of Q at time tn just before the application of the R and S signals, and Qn+1 denotes the value of Q at time tn+1 after the application of the input signals.
Rather than using two NOR gates, one can also implement an SR flip-flop by cross-coupling two NAND gates, in which case the set and reset functions are active when low (see Problem 15.2).
15.1.3 CMOS Implementation of SR Flip-Flops The SR flip-flop of Fig. 15.3 can be directly implemented in CMOS by simply replacing each of the NOR gates by its CMOS circuit realization. We encourage the reader to sketch the resulting circuit (see Problem 15.1). Although the CMOS circuit thus obtained works well, it is somewhat complex. As an alternative, we consider a simplified circuit that further-more implements additional logic. Specifically, Fig. 15.4 shows a clocked version of an SR flip-flop. Since the clock inputs form AND functions with the set and reset inputs, the flip-flop can be set or reset only when the clock φ is high. Observe that although the two cross-coupled inverters at the heart of the flip-flop are of the standard CMOS type, only NMOS transistors are used for the set–reset circuitry. Nevertheless, since there is no conducting path between VDD and ground (except during switching), the circuit does not dissipate any static power.
Except for the addition of clocking, the SR flip-flop of Fig. 15.4 operates in exactly the same way as its logic antecedent in Fig. 15.3: To illustrate, consider what happens when the flip-flop is in the reset state (Q = 0, = 1, vQ = 0, = VDD), and assume that we wish to set Figure 15.4 CMOS implementation of a clocked SR flip-flop. The clock signal is denoted by φ.
Q Q vQ Q Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q S R VDD 1208 Chapter 15 Memory Circuits it. To do so, we arrange for a high (VDD) signal to appear on the S input while R is held low at 0 V. Then, when the clock φ goes high, both Q5 and Q6 will conduct, pulling the voltage down. If goes below the threshold VM of the (Q3, Q4) inverter, the inverter will switch states (or at least begin to switch states), and its output vQ will rise. This increase in vQ is fed back to the input of the (Q1, Q2) inverter, causing its output to go down even further; the regeneration process, characteristic of the positive-feedback latch, is now in progress.
The preceding description of flip-flop switching is predicated on two assumptions: 1. Transistors Q5 and Q6 supply sufficient current to pull the node down to a voltage at least slightly below the threshold of the (Q3, Q4) inverter. This is essential for the regen-erative process to begin. Without this initial trigger, the flip-flop will fail to switch. In Example 15.1, we shall investigate the minimum ratios that Q5 and Q6 must have to meet this requirement.
2. The set signal remains high for an interval long enough to cause regeneration to take over the switching process. An estimate of the minimum width required for the set pulse can be obtained as the sum of the interval during which is reduced from VDD to and the interval for the voltage vQ to respond and rise to This point also will be illustrated in Example 15.1.
Finally, note that the symmetry of the circuit indicates that all the preceding remarks apply equally well to the reset process.
vQ vQ vQ Q W L ⁄ vQ V DD 2, ⁄ V DD 2.
⁄ The CMOS SR flip-flop in Fig. 15.4 is fabricated in a 0.18-μm process for which μnCox = 4 μpCox = 300 μA/V2, = 0.5 V, and VDD = 1.8 V. The inverters have = 0.27 μm/0.18 μm and = 4 The four NMOS transistors in the set–reset circuit have equal ratios. (a) Determine the minimum value required for this ratio to ensure that the flip-flop will switch.
(b) Also, determine the minimum width the set pulse must have for the case in which the W/L ratio of each of the four transistors in the set–reset circuit is selected at twice the minimum value found in (a). As-sume that the total capacitance between each of the Q and nodes and ground is 20 fF.
Solution (a) Figure 15.5(a) shows the relevant portion of the circuit for our present purposes. Observe that since the circuit is in the reset state and regeneration has not yet begun, we assume that vQ = 0 and thus Q2 will be conducting. The circuit is in effect a pseudo-NMOS gate, and our task is to select the ratios for Q5 and Q6 so that VOL of this inverter is lower than (the threshold of the Q3, Q4 inverter whose QN and QP are matched). The minimum required for Q5 and Q6 can be found by equating the current supplied by Q5 and Q6 to the current supplied by Q2 at = . To simplify matters, we assume that the series connection of Q5 and Q6 is equivalent to a single transistor whose is half the of each of Q5 and Q6 (Fig. 15.5b). Now, since at both this equivalent transistor and Q2 will be operating in the triode region, we can write V tn = V tp (W L) ⁄ n (W L) ⁄ p (W L) ⁄ n.
W L ⁄ Q W L ⁄ V DD 2 ⁄ W L ⁄ vQ V DD 2 ⁄ W L ⁄ W L ⁄ vQ = V DD 2 ⁄ IDeq ID2 = 300 1 2 ---× W L -----⎝ ⎠ ⎛ ⎞ 5 1.8 0.5 – ( ) 1.8 2 -------⎝ ⎠ ⎛ ⎞ 1 2 --- 1.8 2 -------⎝ ⎠ ⎛ ⎞ 2 – 75 1.08 0.18 ----------× 1.8 0.5 – ( ) 1.8 2 -------⎝ ⎠ ⎛ ⎞ 1 2 --- 1.8 2 -------⎝ ⎠ ⎛ ⎞ 2 – = Example 15.1 15.1 Latches and Flip-Flops 1209 which yields and thus (b) The value calculated for and is the absolute minimum needed for switching to occur. To guarantee that the flip-flop will switch, the value selected for and is usually somewhat larger than the minimum. Selecting a value twice the minimum, The minimum required width of the set pulse is composed of two components: the time for in the cir-cuit of Fig. 15.5(a) to fall from to , where is the threshold voltage of the inverter formed by and in Fig. 15.4, and the time for the output of the inverter to rise from 0 to At the end of the second time interval, the feedback signal will have traveled around the feed-back loop, and regeneration can continue without the presence of the set pulse. We will denote the first component and the second and will calculate their values as follows.
To determine refer to the circuit in Fig. 15.6 and note that the capacitor discharge current is the difference between the current of the equivalent transistor and the current of To determine the average discharge current , we calculate and at t = 0 and At t = 0, thus is off, W L -----⎝ ⎠ ⎛ ⎞ 5 0.54 μm 0.18 μm ---------------------= W L -----⎝ ⎠ ⎛ ⎞ 6 0.54 μm 0.18 μm ---------------------= W L ⁄ ( )5 W L ⁄ ( )6 W L ⁄ ( )5 W L ⁄ ( )6 W L ⁄ ( )5 W L ⁄ ( )6 1.08 μm 0.18 μm ⁄ = = vQ VDD VDD 2 ⁄ VDD 2 ⁄ Q3 Q4 Q3 Q4 – VDD 2 ⁄ .
tPHL tPLH, tPHL iC Qeq Q2, iC iDeq iD2 – = iC iDeq iD2 t tPHL.
= vQ VDD, = Q2 VDD vS VDD vQ 0 Q6 (a) Q2 Q5 vQ v VDD Figure 15.5 (a) The relevant portion of the flip-flop circuit of Fig. 15.4 for determining the minimum ratios of Q5 and Q6 needed to ensure that the flip-flop will switch. (b) The circuit in (a) with Q5 and Q6 replaced with their equivalent transistor Qeq, at the point of switching. W L ⁄ VDD VDD Q2 Qeq W/L = (b) (W/L)5,6 1 2 ID2 IDeq v Q = VDD 2 – 1210 Chapter 15 Memory Circuits and is in saturation, Thus, At thus both and will be in the triode region, and Thus, and the average value of over the interval t = 0 to is VDD VDD VDD 2 0 tPHL t VDD C Q2 Qeq iD2 iC iDeq v Q – Figure 15.6 Determining the time tPHL for vQ to fall from VDD to VDD/2.
iD2 0 ( ) 0 = Qeq iDeq 1 2 ---300 1 2 ---× × 1.08 0.18 ----------× 1.8 0.5 – ( ) × 2 = 760.5 μA = iC 0 ( ) 760.5 0 760.5 μA = – = t tPHL, = vQ VDD 2 ⁄ , = Q2 Qeq iD2 tPHL ( ) 75 1.08 0.18 ----------× 1.8 0.5 – ( ) 0.5 1.8 2 -------⎝ ⎠ ⎛ ⎞ 2 – × = 344.25 μA = iDeq tPHL ( ) 300 1 2 ---× 1.08 0.18 ----------1.8 0.5 – ( ) 1.8 2 -------⎝ ⎠ ⎛ ⎞ 0.5 1.8 2 -------⎝ ⎠ ⎛ ⎞ 2 – × = 688.5 μA = iC tPHL ( ) 688.5 344.25 344.25 μA = – = iC t tPHL = iC av iC 0 ( ) iC tPHL ( ) + 2 ---------------------------------------= 760.5 344.25 + 2 ------------------------------------552.4 μA = = Example 15.1 continued 15.1 Latches and Flip-Flops 1211 15.1.4 A Simpler CMOS Implementation of the Clocked SR Flip-Flop A simpler implementation of a clocked SR flip-flop is shown in Fig. 15.7. Here, pass-transistor logic is employed to implement the clocked set–reset functions. This circuit is very popular in the design of static random-access memory (SRAM) chips, where it is used as the basic memory cell (Section 15.4.1).
We now can calculate as Next we consider the time for the output of the inverter, , to rise from 0 to The value of can be calculated using the propagation delay formula derived in Chapter 13 (Eq.
13.66), which is also listed in Table 13.3, namely, where Substituting numerical values we obtain, and Finally, the minimum required width of the set pulse can be calculated as tPHL tPHL C VDD 2 ⁄ ( ) iC av --------------------------20 10 15 – 0.9 × × 552.4 10 6 – × --------------------------------------32.6 ps = = = tPHL Q3 Q4 – vQ VDD 2 ⁄ .
tPLH tPLH α pC kp ′ W L ⁄ ( )pVDD -----------------------------------= α p 2 7 4 ---3 Vtp VDD -------------– Vtp VDD ----------⎝ ⎠ ⎛ ⎞ 2 + = αp 2 1.75 3 0.5 × 1.8 ----------------– 0.5 1.8 -------⎝ ⎠ ⎛ ⎞ 2 + -------------------------------------------------------2.01 = = tPLH 2.01 20 10 15 – × × 75 10 6 – 1.08 0.18 ⁄ ( ) 1.8 × × × ------------------------------------------------------------------------49.7 ps = = Tmin tPHL tPLH + = 15.1 For the SR flip-flop specified in Example 15.1, find the minimum W/L for both and so that switching is achieved when inputs S and are at Ans. 14.3 Q5 Q6 φ VDD 2 ⁄ ( ).
EXERCISE 1212 Chapter 15 Memory Circuits 15.1.5 D Flip-Flop Circuits A variety of flip-flop types exist and can be synthesized using logic gates. CMOS circuit implementations can be obtained by simply replacing the gates with their CMOS circuit realizations. This approach, however, usually results in rather complex circuits. In many cases, simpler circuits can be found by taking a circuit-design viewpoint, rather than a logic-design one. To illustrate this point, we shall consider the CMOS implementation of a very important type of flip-flop, the data, or D, flip-flop.
The D flip-flop is shown in block diagram form in Fig. 15.8. It has two inputs, the data input D and the clock input φ. The complementary outputs are labeled Q and . When the clock is low, the flip-flop is in the memory, or rest, state; signal changes on the D input line have no effect on the state of the flip-flop. As the clock goes high, the flip-flop acquires the logic level that existed on the D line just before the rising edge of the clock. Such a flip-flop is said to be edge triggered. Some implementations of the D flip-flop include direct set and reset inputs that override the clocked operation just described. A simple implementation of the D flip-flop is shown in Fig. 15.9. The circuit consists of two inverters connected in a positive-feedback loop, just as in the static latch of Fig. 15.1(a), except that here the loop is closed for only part of the time. Specifically, the loop is closed when the clock is low The input D is connected to the flip-flop through a switch that closes when the clock is high. Operation is straightforward: When φ is high, the loop is opened, and the input D is connected to the input of inverter G1. The capacitance at the input node of G1 is charged to the value of D, and the capacitance at the input node of G2 is charged to the value of . Then, when the clock goes low, the input line is isolated from Figure 15.7 A simpler CMOS implementation of the clocked SR flip-flop. This circuit is popular as the basic cell in the design of static random-access memory (SRAM) chips.
Q Q Q1 Q2 Q3 Q4 Q5 Q6 R S VDD Q φ 0 φ , 1 = = ( ) · .
D D Q (clock) Q Figure 15.8 A block diagram representation of the D flip-flop.
15.1 Latches and Flip-Flops 1213 the flip-flop, the feedback loop is closed, and the latch acquires the state corresponding to the value of D just before φ went down, providing an output Q = D.
From the preceding, we observe that the circuit in Fig. 15.9 combines the positive-feedback technique of static bistable circuits and the charge-storage technique of dynamic circuits. It is important to note that the proper operation of this circuit, and of many circuits that use clocks, is predicated on the assumption that φ and will not be simultaneously high at any time. This condition is defined by referring to the two clock phases as being nonoverlapping.
An inherent drawback of the D flip-flop implementation of Fig. 15.9 is that during φ, the output of the flip-flop simply follows the signal on the D input line. This can cause problems in certain logic-design situations. The problem is solved very effectively by using the master– slave configuration shown in Fig. 15.10(a). Before discussing its circuit operation, we note that although the switches are shown implemented with single NMOS transistors, CMOS transmission gates are employed in many applications. We are simply using the single MOS transistor as a “shorthand notation” for a series switch.
The master–slave circuit consists of a pair of circuits of the type shown in Fig. 15.9, operated with alternate clock phases. Here, to emphasize that the two clock phases must be nonoverlapping, we denote them φ1 and φ2, and clearly show the nonoverlap interval in the waveforms of Fig. 15.10(b). Operation of the circuit is as follows: 1. When φ1 is high and φ2 is low, the input is connected to the master latch whose feedback loop is opened, while the slave latch is isolated. Thus, the output Q remains at the value stored previously in the slave latch whose loop is now closed. The node capacitances of the master latch are charged to the appropriate voltages corresponding to the present value of D.
2. When φ1 goes low, the master latch is isolated from the input data line. Then, when φ2 goes high, the feedback loop of the master latch is closed, locking in the value of D.
Further, its output is connected to the slave latch whose feedback loop is now open. The node capacitances in the slave are appropriately charged so that when φ1 goes high again, the slave latch locks in the new value of D and provides it at the output, Q = D. From this description, we note that at the positive transition of clock φ2 the output Q adopts the value of D that existed on the D line at the end of the preceding clock phase, φ1.
This output value remains constant for one clock period. Finally, note that during the non-overlap interval both latches have their feedback loops open, and we are relying on the node capacitances to maintain most of their charge. It follows that the nonoverlap interval should be kept reasonably short (perhaps one-tenth or less of the clock period, and of the order of 1 ns or so in current practice).
Figure 15.9 A simple implementation of the D flip-flop. The circuit in (a) utilizes the two-phase non-overlapping clock whose waveforms are shown in (b).
D Q Q G1 G2 (a) t t (b) φ 1214 Chapter 15 Memory Circuits 15.2 Semiconductor Memories: Types and Architectures A computer system, whether a large machine or a microcomputer, requires memory for storing data and program instructions. Furthermore, within a given computer system there usually are various types of memory utilizing a variety of technologies and having different access times.
Broadly speaking, computer memory can be divided into two types: main memory and mass-storage memory. The main memory is usually the most rapidly accessible memory and the one from which most, often all, instructions in programs are executed. The main memory is usually of the random-access type. A random-access memory (RAM) is one in which the time required for storing (writing) information and for retrieving (reading) information is inde-pendent of the physical location (within the memory) in which the information is stored.
Random-access memories should be contrasted with serial or sequential memories, such as disks and tapes, from which data are available only in the sequence in which the data were originally stored. Thus, in a serial memory the time to access particular information depends on the memory location in which the required information is stored, and the aver-age access time is longer than the access time of random-access memory. In a computer system, serial memory is used for mass storage. Items not frequently accessed, such as large Figure 15.10 (a) A master–slave D flip-flop. The switches can be, and usually are, implemented with CMOS transmission gates. (b) Waveforms of the two-phase nonoverlapping clock required. D 2 1 2 1 G1 G2 G3 G4 Q Q Master Slave (a) 1 t 2 t Nonoverlap interval (b) 15.2 Semiconductor Memories: Types and Architectures 1215 parts of the computer operating system, are usually stored in a moving-surface memory such as magnetic disk.
Another important classification of memory relates to whether it is a read/write or a read-only memory. Read/write (R/W) memory permits data to be stored and retrieved at comparable speeds. Computer systems require random-access read/write memory for data and program storage.
Read-only memories (ROM) permit reading at the same high speeds as R/W memories (or perhaps higher) but restrict the writing operation. ROMs can be used to store a micropro-cessor operating-system program. They are also employed in operations that require table lookup, such as finding the values of mathematical functions. A popular application of ROMs is their use in video game cartridges. It should be noted that read-only memory is usually of the random-access type. Nevertheless, in the digital circuit jargon, the acronym RAM usually refers to read/write, random-access memory, while ROM is used for read-only memory.
The regular structure of memory circuits has made them an ideal application for the design of circuits of the very-large-scale integrated (VLSI) type. Indeed, at any moment, memory chips represent the state of the art in packing density and hence integration level.
Beginning with the introduction of the 1-Kbit chip in 1970, memory-chip density has qua-drupled about every 3 years. At the present time (2009), chips containing 4 Gbit1 are avail-able. In this and the next two sections, we shall study some of the basic circuits employed in VLSI RAM chips. Read-only memory circuits are studied in Section 15.5.
15.2.1 Memory-Chip Organization The bits on a memory chip are addressable either individually or in groups of 4 to 16. As an example, a 64-Mbit chip in which all bits are individually addressable is said to be organized as 64M words × 1 bit (or simply 64M × 1). Such a chip needs a 26-bit address (226 = 67,108,864 = 64M). On the other hand, the 64-Mbit chip can be organized as 16M words × 4 bits (16M × 4), in which case a 24-bit address is required. For simplicity we shall assume in our subsequent discussion that all the bits on a memory chip are individually addressable.
The bulk of the memory chip consists of the cells in which the bits are stored. Each memory cell is an electronic circuit capable of storing one bit. We shall study memory-cell circuits in Section 15.3. For reasons that will become clear shortly, it is desirable to physi-cally organize the storage cells on a chip in a square or a nearly square matrix. Figure 15.11 illustrates such an organization. The cell matrix has 2M rows and 2N columns, for a total stor-age capacity of For example, a 1M-bit square matrix would have 1024 rows and 1024 columns (M = N = 10). Each cell in the array is connected to one of the 2M row lines, known rather loosely, but universally, as word lines, and to one of the 2N column lines, known as digit lines or, more commonly, bit lines. A particular cell is selected for reading or writing by activating its word line and its bit line.
Activating one of the 2M word lines is performed by the row decoder, a combinational logic circuit that selects (raises the voltage of) the particular word line whose M-bit address is applied to the decoder input. The address bits are denoted When the Kth word line is activated for, say, a read operation, all 2N cells in row K will provide their contents to their respective bit lines. Thus, if the cell in column L (Fig. 15.11) is storing a 1, the voltage of bit-line number L will be raised, usually by a small voltage, say 0.1 V to 0.2 V. The readout voltage 1The capacity of a memory chip to hold binary information as binary digits (or bits) is measured in kilobit (Kbit), megabit (Mbit), and gigabit (Gbit) units, where 1 Kbit = 1024 bits, 1 Mbit = 1024 × 1024 = 1,048,576 bits, and, 1 Gbit = 10243 bits. Thus a 64-Mbit chip contains 67,108,864 bits of memory.
2M+N.
A0, A1, …, AM−1.
1216 Chapter 15 Memory Circuits is small because the cell is small, a deliberate design decision, since the number of cells is very large. The small readout signal is applied to a sense amplifier connected to the bit line. As Fig.
15.11 indicates, there is a sense amplifier for every bit line. The sense amplifier provides a full-swing digital signal (from 0 to VDD) at its output. This signal, together with the output signals from all the other cells in the selected row, is then delivered to the column decoder. The col-umn decoder selects the signal of the particular column whose N-bit address is applied to the decoder input (the address bits are denoted ) and causes this signal to appear on the chip input/output (I/O) data line.
A write operation proceeds in a similar manner: The data bit to be stored (1 or 0) is applied to the I/O line. The cell in which the data bit is to be stored is selected through the combination of its row address and its column address. The sense amplifier of the selected column acts as a driver to write the applied signal into the selected cell. Circuits for sense amplifiers and address decoders will be studied in Section 15.4.
Before leaving the topic of memory organization (or memory-chip architecture), we wish to mention a relatively recent innovation in organization dictated by the exponential increase in chip density. To appreciate the need for a change, note that as the number of cells in the array Figure 15.11 A 2M+N-bit memory chip organized as an array of 2M rows × 2N columns.
Sense amplifiers / drivers Column decoder Row decoder I/O data Column address (N bits) AM AM1 AMN1 K 0 1 2M1 2N1 A0 A1 AM1 Row address (M bits) Word line Storage cell Storage cell array Bit line 0 1 L AM, AM+1, …, AM+N−1 15.3 Random-Access Memory (RAM) Cells 1217 increases, the physical lengths of the word lines and the bit lines increase. This has occurred even though for each new generation of memory chips, the transistor size has decreased (cur-rently, CMOS process technologies with 45-nm feature size are utilized). The net increase in word-line and bit-line lengths increases their total resistance and capacitance, and thus slows down their transient response. That is, as the lines lengthen, the exponential rise of the voltage of the word line becomes slower, and it takes longer for the cells to be activated. This problem has been solved by partitioning the memory chip into a number of blocks. Each of the blocks has an organization identical to that in Fig. 15.11. The row and column addresses are broadcast to all blocks, but the data selected come from only one of the blocks. Block selection is achieved by using an appropriate number of the address bits as a block address. Such an archi-tecture can be thought of as three-dimensional: rows, columns, and blocks.
15.2.2 Memory-Chip Timing The memory access time is the time between the initiation of a read operation and the appearance of the output data. The memory cycle time is the minimum time allowed between two consecutive memory operations. To be on the conservative side, a memory operation is usually taken to include both read and write (in the same location). MOS mem-ories have access and cycle times in the range of a few to a few hundred nanoseconds.
15.3 Random-Access Memory (RAM) Cells As mentioned in Section 15.2, the major part of the memory chip is taken up by the storage cells. It follows that to be able to pack a large number of bits on a chip, it is imperative that the cell size be reduced to the smallest possible. The power dissipation per cell should be minimized also. Thus, many of the flip-flop circuits studied in Section 15.1 are too complex to be suitable for implementing the storage cells in a RAM chip.
There are basically two types of MOS RAM: static and dynamic. Static RAMs (called SRAMs for short) utilize static latches as the storage cells. Dynamic RAMs (called DRAMs), on the other hand, store the binary data on capacitors, resulting in further reduction in cell area, but at the expense of more complex read and write circuitry. In particular, while static RAMs can hold their stored data indefinitely, provided the power supply remains on, dynamic RAMs 15.2 A 4-Mbit memory chip is partitioned into 32 blocks, with each block having 1024 rows and 128 columns. Give the number of bits required for the row address, column address, and block address.
Ans. 10; 7; 5 15.3 The word lines in a particular MOS memory chip are fabricated using polysilicon (see Appendix A).
The resistance of each word line is estimated to be 5 kΩ, and the total capacitance between the line and ground is 2 pF. Find the time for the voltage on the word line to reach assuming that the line is driven by a voltage VDD provided by a low-impedance inverter. (Note: The line is actually a distributed network that we are approximating by a lumped circuit consisting of a single resistor and a single capacitor.) Ans. 6.9 ns V DD 2 ⁄ , EXERCISES 1218 Chapter 15 Memory Circuits require periodic refreshing to regenerate the data stored on capacitors. This is because the stor-age capacitors will discharge, though slowly, as a result of the leakage currents inevitably present. By virtue of their smaller cell size, dynamic memory chips are usually four times as dense as their contemporary static chips. Thus while the state of the art in 2009 is a 4-Gbit DRAM chip, the highest-density SRAM chip has 1 Gbit capacity. Both static and dynamic RAMs are volatile; that is, they require the continuous presence of a power supply. By con-trast, most ROMs are of the nonvolatile type, as we shall see in Section 15.5. In the follow-ing subsections, we shall study basic SRAM and DRAM storage cells.
15.3.1 Static Memory (SRAM) Cell Figure 15.12 shows a typical static memory cell in CMOS technology. The circuit, which we encountered in Section 15.1, is a flip-flop comprising two cross-coupled inverters and two access transistors, Q5 and Q6. The access transistors are turned on when the word line is selected and its voltage raised to VDD, and they connect the flip-flop to the column (bit or B) line and ( or ) line. Note that although in principle only the B or the line suffices, most often both are utilized, as shown in Fig. 15.12. This both provides a differen-tial data path between the cell and the memory-chip output and increases the circuit reliabil-ity. The access transistors act as transmission gates allowing bidirectional current flow between the flip-flop and the B and lines. Finally, we note that this circuit is known as the six-transistor or 6T cell. The Read Operation Consider first a read operation, and assume that the cell is storing a 1.
In this case, Q will be high at VDD, and will be low at 0 V. Before the read operation begins, the B and lines are raised to a voltage in the range to This process, known as precharging, is performed using circuits we shall discuss in the next section in conjunction with the study of sense amplifiers. To simplify matters, we shall assume here that the pre-charge voltage of B and is When the word line is selected and the access transistors and are turned on, exam-ination of the circuit reveals that the only portion that will be conducting is that shown in Fig.
15.13. Noting that the initial value of is 0 V, we can see that current will flow from the Figure 15.12 A CMOS SRAM memory cell.
column bit B B B Q B VDD 2 ⁄ VDD.
B VDD.
Q5 Q6 vQ B Q4 Q3 VDD Word line (W) Q Q2 Q5 Q6 Q1 Q Bit line B Bit line B 15.3 Random-Access Memory (RAM) Cells 1219 line (actually, from the -line capacitance ) through and into capacitor , which is the small equivalent capacitance between the node and ground. This current charges and thus rises and conducts, sinking some of the current supplied by Equilibrium will be reached when is charged to a voltage at which equals and no current flows through Here it is extremely important to note that to avoid changing the state of the flip-flop, that is, for our read operation to be nondestructive, must not exceed the threshold voltage of the inverter In fact, SRAM designers usually impose a more stringent requirement on the value of , namely, that it should be lower than the threshold voltage of Thus, the design problem we shall now solve is as follows: Determine the ratio of so that Noting that will be operating in saturation and neglecting, for simplicity, the body effect, we can write (15.1) Transistor will be operating in the triode region, and its current can be written as (15.2) Equating and gives a quadratic equation in which can be solved to obtain (15.3) This is an attractive relationship, since it provides in normalized form and thus always applies, independent of the process technology utilized. Figure 15.14 shows a universal plot of versus For a given process technology, and are determined, and the plot in Fig. 15.14 can be used to determine the maximum value permitted for while keeping below a desired value. Alternatively, we Figure 15.13 Relevant parts of the SRAM cell circuit during a read operation when the cell is storing a logic 1. Note that initially and Also note that the B and lines are precharged to a voltage CB Q5 Q1 vQ vW VDD vQ VDD I5 I1 B line vB CQ vQ = VDD vQ = 0.
B V DD.
B CB Q5 CQ Q CQ vQ Q1 Q5.
CQ VQ I1 I5, CQ.
VQ Q3 Q4.
– VQ Q3, Vtn.
W L ⁄ ( )5 W L ⁄ ( )1 ⁄ VQ Vtn.
≤ Q5 I5 1 2 --- μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 5 VDD Vtn – VQ – ( )2 = Q1 I1 I1 μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 1 VDD Vtn – ( )VQ 1 2 ---V Q 2 – = I5 I1 VQ, VQ VDD Vtn – -----------------------1 1 1 W L ⁄ ( )5 W L ⁄ ( )1 -------------------+ ⁄ – = VQ VQ VDD Vtn – ( ) ⁄ [ ] W L ⁄ ( )5 W L ⁄ ( )1 ⁄ .
· VDD Vtn W L ⁄ ( )5 W L ⁄ ( )1 ⁄ VQ 1220 Chapter 15 Memory Circuits can derive a formula for this purpose. For instance, if is to be kept below the ratio of to must be kept below the value obtained from Eq. (15.3), that is, (15.4) This is an important design constraint that can be expressed in a slightly more general form by replacing with where the subscript a denotes access transistors and , and with which is the W/L ratio of in each of the two inverters; thus, (15.5) Figure 15.14 The normalized value of versus the ratio (W/L)5/(W/L)1 for the circuit in Fig. 15.13. This graph can be used to determine the maximum value permitted for (W/L)5/(W/L)1 so that is kept below a desired level.
0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 (W/L)5 (W/L)1 VQ VDD – Vtn ( ( – VQ VQ VQ Vtn, W L ⁄ ( )5 W L ⁄ ( )1 W L ⁄ ( )5 W L ⁄ ( )1 -------------------1 1 Vtn VDD Vtn – -----------------------– ⎝ ⎠ ⎛ ⎞ 2 ----------------------------------------1 – ≤ W L ⁄ ( )5 W L ⁄ ( )a, Q5 Q6 W L ⁄ ( )1 W L ⁄ ( )n, QN W L ⁄ ( )a W L ⁄ ( )n -------------------1 1 Vtn VDD Vtn – -----------------------– ⎝ ⎠ ⎛ ⎞ 2 ----------------------------------------1 – ≤ 15.4 Find the maximum allowable W/L for the access transistors of the SRAM cell in Fig. 15.12 so that in a read operation, the voltages at Q and do not change by more than Assume that the SRAM is fabricated in a 0.18-μm technology for which and that Ans.
Q Vt .
VDD 1.8 V, = Vtn Vtp 0.5 V = = W L ⁄ ( )n 1.5.
= W L ⁄ ( )a 2.5 ≤ EXERCISE 15.3 Random-Access Memory (RAM) Cells 1221 Having determined the constraint imposed by the read operation on the W/L ratios of the access transistors, we now return to the circuit in Fig. 15.13, and show in Fig. 15.15 the volt-age waveforms at various nodes during a read-1 operation. Observe that as we have already, discussed, rises from zero to a voltage Correspondingly, the change in will be very small, justifying the assumption implicit in the analysis above that remains con-stant at Most important, note that the voltage of the line, decreases by a small amount This is a result of the discharge of the capacitance of the line, by the current Assuming that reaches its equilibrium value in Eq. (15.1) relatively quickly, capacitor is in effect discharged by a constant current and the change in its voltage, obtained in a time interval can be found by writing a charge-balance equation, Thus, (15.6) Here we note that is usually relatively large (1–2 pF) because a large number of cells are connected to the line. The incremental change is therefore rather small (0.1–0.2 V), necessitating the use of a sense amplifier. If the sense amplifier requires a minimum decre-ment in to detect the presence of a “1”, then the read delay time can be found from Eq. (15.6) as (15.7) Figure 15.15 Voltage waveforms at various nodes in the SRAM cell during a read-1 operation.
v W VDD VDD VDD VDD t V Vtn 0 0 v Q – v B – v Q v B vQ VQ Vtn.
≤ vQ vQ VDD.
B vB, V.
Δ B CB, I5.
I5 CB I5 V, Δ t, Δ I5 t CB V Δ = Δ V I5 t Δ CB ---------= Δ CB B V Δ V Δ vB t CB V Δ I5 -----------------= Δ 1222 Chapter 15 Memory Circuits This equation indicates the need for a relatively large to reduce the delay time A large however, implies selecting near the upper bound given by Eq. (15.5), which in turn means an increase in the silicon area occupied by the access transistors and hence the cell area, an interesting design trade-off. We conclude our discussion of the read operation with two remarks: 1. Although we considered only the read-1 operation, the read-0 operation is identical; it involves and with the analysis resulting in an upper bound on equal to that we have found for This, of course, is entirely expected, since the circuit is symmetrical. The read-0 operation results in a decrement in the voltage of the B line, which is interpreted by the sense amplifier as a stored 0. 2. The component of the read delay is relatively large because and are rela-tively large (in the picofarad range). Also, is not the only component of the read delay; another significant component is due to the finite rise time of the voltage on the word line. Indeed, even the calculation of is optimistic, since the word line will have reached a voltage lower than only, when the process of discharging takes place. As will be seen shortly, the write operation is faster.
The Write Operation We next consider the write operation. Let the SRAM cell of Fig.
15.12 be storing a logic 1, thus and and assume that we wish to write a 0; that is, we wish to have the flip-flop switch states. To write a zero, the B line is lowered to 0 V, and the line is raised to and, of course, the cell is selected by raising the word line to The objective now is to pull node Q down and node up and have the voltage of at least one of these two nodes pass by the inverter threshold voltage. Thus, if decreases below the threshold voltage of inverter the regenerative action of the latch will start and the flip-flop will switch to the stored-0 state. Alternatively, or in addition, if we manage to raise above the threshold voltage of the inverter, the regenerative action will be engaged and the latch will eventually switch state. Either one of the two actions is suffi-cient to engage the regenerative mechanism of the latch.
Figure 15.16 shows the relevant parts of the SRAM circuit during the interval when is being pulled up (Fig. 15.16a) and is being pulled down (Fig. 15.16b). Since toggling (i.e., state change) has not yet taken place, we assume that the voltage feeding the gate of is still equal to and the voltage at the gate of is still equal to 0 V. These voltages will of course be changing as goes up and goes down, but this assumption is nevertheless rea-sonable for hand analysis.
I5 t.
Δ I5, W L ⁄ ( )a 15.5 For the SRAM cell considered in Exercise 15.4 whose and use Eq. (15.7) to determine the read delay in two cases: (a) and (b) Let In both cases, assume that and that the sense amplifier re-quires a of minimum magnitude of 0.2 V. [Hint: Use Eq. (15.1) to determine and recall that .] Ans. 1.7 ns; 2.8 ns W L ⁄ ( )n 1.5 = W L ⁄ ( )a 2.5, ≤ t Δ W L ⁄ ( )a 2.5 = W L ⁄ ( )a 1.5.
= μnCox 300 μA V ⁄ = 2.
CB 2 pF = V Δ I5, VQ Vtn = EXERCISE Q2 Q6 W L ⁄ ( )6 W L ⁄ ( )2 ⁄ W L ⁄ ( )5 W L ⁄ ( )1 ⁄ .
V Δ t Δ CB CB t Δ t Δ VDD CB VQ VDD = VQ 0 V, = B VDD VDD.
Q vQ Q1 Q2, – vQ Q3 Q4 – vQ vQ Q1 VDD Q4 vQ vQ 15.3 Random-Access Memory (RAM) Cells 1223 Consider first the circuit in Fig. 15.16(a). This is the same circuit we analyzed in detail in the study of the read operation above. Recall that to make the read process nondestructive, we imposed an upper bound on That upper bound ensured that will not rise above Thus, this circuit is not capable of raising to the point that it can start the regenerative action. We must therefore rely solely on the circuit of Fig. 15.16(b). That is, our write-0 operation will be accomplished by pulling node Q down in order to initiate the regenerative action of the latch. To ensure that the latch will in fact switch state, SRAM designers impose a more stringent requirement on the voltage namely, that it must fall below not just of the inverter but below of Let’s now look more closely at the circuit of Fig. 15.16(b). Initially, is at How-ever, as turns on, quickly discharges the small capacitance , and begins to fall.
This will enable to conduct, and equilibrium is reached when . To ensure tog-gling, we design the circuit so that this equilibrium occurs at a value of less than At such a value will be operating in saturation and will be operating in the triode region, thus (15.8) and (15.9) Substituting which is usually the case, and equating and results in a qua-dratic equation in whose solution is (15.10) This relationship is not as convenient as that in Eq. (15.3) because the right-hand side includes a process-dependent quantity, namely, Thus we do not have a universally Figure 15.16 Relevant parts of the 6T SRAM circuit of Fig. 15.12 during the process of writing a 0. It is assumed that the cell is originally storing a 1 and thus initially vQ = VDD and V.
VDD VDD VDD 0V 0V Q1 Q5 Q4 Q6 B B – I5 I1 I4 I6 v Q – C Q – C Q v W = VDD v W = VDD v Q (a) (b) vQ 0 = W L ⁄ ( )5.
vQ Vtn.
vQ vQ, VM Q1 Q2 – Vtn Q1.
vQ VDD.
Q6 I6 CQ vQ Q4 I4 I6 = vQ Vtn.
VQ, Q4 Q6 I4 1 2 --- μpCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 4 VDD Vtp – ( )2 = I6 μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 6 VDD Vtn – ( )VQ 1 2 ---VQ – 2 = Vtp Vtn, = I4 I6 VQ VQ VDD Vtn – -----------------------1 1 μp μn -----⎝ ⎠ ⎛ ⎞W L ⁄ ( )4 W L ⁄ ( )6 -------------------– – = μp μn ⁄ .
1224 Chapter 15 Memory Circuits applicable relationship. Nevertheless, for a number of CMOS process technologies, includ-ing the 0.25-μm, the 0.18-μm, and the 0.13-μm processes, Thus, upon substitut-ing in Eq. (15.10), we obtain the semiuniversal graph shown in Fig. 15.17.
We can use this graph to determine the maximum allowable value of the ratio that will ensure a value of for given process parameters and Alternatively, substituting and we can obtain the upper bound analytically as (15.11) Observe that this relationship provides an upper bound on in terms of and that the relationship in Eq. (15.5) provides an upper bound on in terms of Thus, the two relationships can be used together to design the SRAM cell.
Figure 15.17 The normalized value of VQ versus the ratio (W/L)4/(W/L)6 for the circuit in Fig. 15.16(b).
The graph applies for process technologies for which It can be used to determine the maximum (W/L)4/(W/L)6 for which VQ is guaranteed to fall below a desired value.
0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 (W/L)4 (W/L)6 VQ VDD – Vtn ( ( μn 4μp.
μn μp 4 ⁄ .
μp μn ⁄ 0.25 = W L ⁄ ( )4 W L ⁄ ( )6 ⁄ VQ Vtn ≤ VDD Vtn.
VQ Vtn, = W L ⁄ ( )4 W L ⁄ ( )p, = W L ⁄ ( )6 W L ⁄ ( )a, = W L ⁄ ( )p W L ⁄ ( )a -------------------μn μp -----⎝ ⎠ ⎛ ⎞1 1 Vtn VDD Vtn – -----------------------– ⎝ ⎠ ⎛ ⎞ 2 – ≤ W L ⁄ ( )p W L ⁄ ( )a W L ⁄ ( )a W L ⁄ ( )n.
15.6 For the SRAM cell considered in Exercise 15.4, where and use Eq. (15.11) to find the maximum allowable value of Recall that for this 0.18-μm process, For all transistors having L = 0.18 μm, find and that result in a minimum-area cell. Assume that the minimum allowable width is 0.18 μm.
Ans. thus for minimum area select W L ⁄ ( )n 1.5 = W L ⁄ ( )a 2.5 , ≤ W L ⁄ ( )p.
μp 4μn.
Wn, Wp, Wa W L ⁄ ( )p 2.5 ≤ W L ⁄ ( )a, W L ⁄ ( )p 6.25; ≤ Wn Wp = = Wa 0.18 μm.
= EXERCISE 15.3 Random-Access Memory (RAM) Cells 1225 We conclude our study of the write process by noting that it is fast because it does not require discharging the large capacitance of the bit lines. The voltages of the B and lines are driven to their required values of 0 or by powerful driver circuits and thus achieve their desired voltages very quickly. The write delay is determined roughly by the time for the regenerating signal to propagate around the feedback loop of the latch; thus it is about twice the propagation delay of the inverter. Of course, the write cycle time is still lengthened by the word-line delay. 15.3.2 Dynamic Memory Cell Although a variety of DRAM storage cells have been proposed over the years, a particular cell, shown in Fig. 15.18, has become the industry standard. The cell consists of a single n-channel MOSFET, known as the access transistor, and a storage capacitor CS. The cell is appropriately known as the one-transistor cell.2 The gate of the transistor is connected to the word line, and its source (drain) is connected to the bit line. Observe that only one bit line is used in DRAMs, whereas in SRAMs both the bit and bit lines are utilized. The DRAM cell stores its bit of information as charge on the cell capacitor When the cell is storing a 1, the capacitor is charged to when a 0 is stored, the capacitor is discharged to zero volts.
Some explanation is needed to appreciate how the capacitor can be charged to the full supply voltage Consider a write-1 operation. The word line is at and the bit line is at and the transistor is conducting, charging The transistor will cease conduction when the voltage on reaches This is the same problem we encountered with pass-transistor logic (PTL) in Section 14.2. The problem is overcome in DRAM design by boosting the word line to a voltage equal to In this case the capacitor voltage for a stored 1 will be equal to the full However, because of leakage effects, the capacitor charge will leak off, and hence the cell must be refreshed periodically. During refresh, the cell content is read and the data bit is rewritten, thus restoring the capacitor voltage to its proper value. Typically, the refresh operation must be performed every 5 ms to 10 ms.
Let us now consider the DRAM operation in more detail. As in the static RAM, the row decoder selects a particular row by raising the voltage of its word line. This causes all the 2The name was originally used to distinguish this cell from earlier ones utilizing three transistors. Figure 15.18 The one-transistor dynamic RAM (DRAM) cell.
B VDD CS.
VDD; VDD.
VDD VDD CS.
CS VDD Vt – ( ).
VDD Vt.
+ VDD.
Q Cell Word line Bit line CS 1226 Chapter 15 Memory Circuits access transistors in the selected row to become conductive, thereby connecting the storage capacitors of all the cells in the selected row to their respective bit lines. Thus the cell capac-itor CS is connected in parallel with the bit-line capacitance CB, as indicated in Fig. 15.19.
Here, it should be noted that CS is typically 20 fF to 30 fF, whereas CB is 10 times larger.
Now, if the operation is a read, the bit line is precharged to To find the change in the voltage on the bit line resulting from connecting a cell capacitor CS to it, let the initial volt-age on the cell capacitor be VCS (VCS = VDD when a 1 is stored, and VCS = 0 V when a 0 is stored). Using charge conservation, we can write from which we can obtain for ΔV (15.12) and since (15.13) Now, if the cell is storing a 1, VCS = VDD, and (15.14) whereas if the cell is storing a 0, VCS = 0, and (15.15) Since usually CB is much greater than CS, these readout voltages are very small. For exam-ple, for CB = 10 CS, VDD = 1.8 V, ΔV(0) will be about –90 mV, and ΔV(1) will be +90 mV.
This is a best-case scenario, for the 1 level in the cell might very well be below VDD.
Furthermore, in modern memory chips, VDD is 1.2 V or even lower. In any case, we see that a stored 1 in the cell results in a small positive increment in the bit-line voltage, whereas a stored zero results in a small negative increment. Observe also that the readout process is destructive, since the resulting voltage across CS will no longer be VDD or 0.
The change of voltage on the bit line is detected and amplified by the column sense amplifier causing the bit line to be driven to the full scale value (0 or VDD) of the detected signal. This amplified signal is then impressed on the storage capacitor, thus restoring its signal to the proper level (VDD or 0). In this way, all the cells in the selected row are refreshed. Simultaneously, the signal at the output of the sense amplifier of the selected col-umn is fed to the data-output line of the chip through the action of the column decoder.
The write operation proceeds similarly to the read operation, except that the data bit to be written, which is impressed on the data input line, is applied by the column decoder to the C CS CB Figure 15.19 When the voltage of the selected word line is raised, the transistor conducts, thus connecting the storage capacitor CS to the bit-line capacitance CB.
VDD 2.
⁄ CSV CS CB V DD 2 ---------+ CB CS + ( ) V DD 2 ---------ΔV + ⎝ ⎠ ⎛ ⎞ = ΔV CS CB CS + ------------------ V CS V DD 2 ---------– ⎝ ⎠ ⎛ ⎞ = C B CS , ΔV CS CB ------ V CS V DD 2 ---------– ⎝ ⎠ ⎛ ⎞ ΔV 1 ( ) CS CB ------ V DD 2 ---------⎝ ⎠ ⎛ ⎞ ΔV 0 ( ) CS CB ------– V DD 2 ---------⎝ ⎠ ⎛ ⎞ 15.4 Sense Amplifiers and Address Decoders 1227 selected bit line. Thus, if the data bit to be written is a 1, the B-line voltage is raised to VDD (i.e., CB is charged to VDD). When the access transistor of the particular cell is turned on, its capacitor CS will be charged to VDD; thus a 1 is written in the cell. Simultaneously, all the other cells in the selected row are simply refreshed.
Although the read and write operations result in automatic refreshing of all the cells in the selected row, provision must be made for the periodic refreshing of the entire memory, typically every 5 to 10 ms, as specified for the particular chip. The refresh operation is car-ried out in a burst mode, one row at a time. During refresh, the chip will not be available for read or write operations. This is not a serious matter, however, since the interval required to refresh the entire chip is typically less than 2% of the time between refresh cycles. In other words, the memory chip is available for normal operation more than 98% of the time.
15.4 Sense Amplifiers and Address Decoders Having studied the circuits commonly used to implement the storage cells in SRAMs and DRAMs, we now consider some of the other important circuit blocks in a memory chip. The design of these circuits, commonly referred to as the memory peripheral circuits, presents exciting challenges and opportunities to integrated-circuit designers: Improving the perfor-mance of peripheral circuits can result in denser and faster memory chips that dissipate less power.
15.4.1 The Sense Amplifier Next to the storage cells, the sense amplifier is the most critical component in a memory chip. Sense amplifiers are essential to the proper operation of DRAMs, and their use in SRAMs results in speed and area improvements.
A variety of sense-amplifier designs are in use, some of which closely resemble the active-load MOS differential amplifier studied in Chapter 8. Here, we first describe a differ-ential sense amplifier that employs positive feedback. Because the circuit is differential, it can be employed directly in SRAMs, where the SRAM cell utilizes both the B and B lines.
On the other hand, the one-transistor DRAM circuit we studied in Section 15.3.2 is a single-ended circuit, utilizing one bit line only. The DRAM circuit, however, can be made to resem-ble a differential signal source through the use of the “dummy-cell” technique, which we 15.7 In a particular dynamic memory chip, CS = 30 fF, CB = 0.3 pF, and VDD = 1.2 V. Find the output readout voltage for a stored 1 and a stored 0. Recall that in a read operation, the bit lines are pre-charged to Ans. 60 mV; –60 mV 15.8 A 64-Mbit DRAM chip fabricated in a 0.4-μm CMOS technology requires 2 μm2 per cell. If the storage array is square, estimate its dimensions. Further, if the peripheral circuitry (e.g., sense am-plifiers, decoders) adds about 30% to the chip area, estimate the dimensions of the resulting chip.
Ans. 11.6 mm × 11.6 mm; 13.2 mm × 13.2 mm V DD 2 ⁄ .
EXERCISES 1228 Chapter 15 Memory Circuits shall discuss shortly. Therefore, we shall assume that the memory cell whose output is to be amplified develops a difference output voltage between the B and B lines. This signal, which can range from 30 mV to 500 mV depending on the memory type and cell design, will be applied to the input terminals of the sense amplifier. The sense amplifier in turn responds by providing a full-swing (0 to VDD) signal at its output terminals. The particular amplifier circuit we shall discuss here has a rather unusual property: Its output and input terminals are the same!
A Sense Amplifier with Positive Feedback Figure 15.20 shows the sense amplifier together with some of the other column circuitry of a RAM chip. Note that the sense amplifier is nothing but the familiar latch formed by cross-coupling two CMOS inverters: One inverter Figure 15.20 A differential sense amplifier connected to the bit lines of a particular column. This arrangement can be used directly for SRAMs (which utilize both the B and B lines). DRAMs can be turned into differential circuits by using the “dummy-cell” arrangement shown later (Fig. 15.22).
Word line Q4 Q6 Q3 Q2 Q7 Q5 Q9 Q8 Q1 VDD/2 B line B line p s s y x VDD vB vB CB CB Cell Selected cell Differential sense amplifier Equalization and precharge circuitry 15.4 Sense Amplifiers and Address Decoders 1229 is implemented by transistors Q1 and Q2, and the other by transistors Q3 and Q4. Transistors Q5 and Q6 act as switches that connect the sense amplifier to ground and VDD only when data-sensing action is required. Otherwise, φs is low and the sense amplifier is turned off. This conserves power, an important consideration because usually there is one sense amplifier per column, resulting in thousands of sense amplifiers per chip. Note, again, that terminals x and y are both the input and the output terminals of the amplifier. As indicated, these I/O terminals are connected to the B and B lines. The amplifier is required to detect a small signal appearing between B and B, and to amplify it to provide a full-swing signal at B and B. For instance, if during a read operation, the cell has a stored 1, then a small positive voltage will develop be-tween B and B, with vB higher than The amplifier will then cause vB to rise to VDD and to fall to 0 V. This 1 output is then directed to the chip I/O pin by the column decoder (not shown) and at the same time is used to rewrite a 1 in the DRAM cell, thus performing the restore operation that is required because the DRAM readout process is destructive.
Figure 15.20 also shows the precharge and equalization circuit. Operation of this circuit is straightforward: When φp goes high (to VDD) prior to a read operation, all three transistors conduct. While Q8 and Q9 precharge the B and B lines to transistor Q7 helps speed up this process by equalizing the initial voltages on the two lines. This equalization is criti-cal to the proper operation of the sense amplifier. Any voltage difference present between B and B prior to commencement of the read operation can result in erroneous interpretation by the sense amplifier of its input signal. In Fig. 15.20, we show only one of the cells in this particular column, namely, the cell whose word line is activated. The cell can be either an SRAM or a DRAM cell. All other cells in this column will not be connected to the B and B lines (because their word lines will remain low).
Let us now consider the sequence of events during a read operation: 1. The precharge and equalization circuit is activated by raising the control signal φp. This will cause the B and B lines to be at equal voltages, equal to The clock φp then goes low, and the B and B lines are left to float for a brief interval.
2. The word line goes up, connecting the cell to the B and B lines. A voltage then devel-ops between B and B, with vB higher than vB if the accessed cell is storing a 1, or vB lower than vB if the cell is storing a 0. To keep the cell area small, and to facilitate operation at higher speeds, the readout signal, which the cell is required to provide between B and B, is kept small (typically, 30–500 mV).
3. Once an adequate difference voltage signal has been developed between B and B by the storage cell, the sense amplifier is turned on by connecting it to ground and VDD through Q5 and Q6, activated by raising the sense-control signal φs. Because ini-tially the input terminals of the inverters are at , the inverters will be operat-ing in their transition region where the gain is high (Section 13.2). It follows that initially the latch will be operating at its unstable equilibrium point. Thus, depending on the signal between the input terminals, the latch will quickly move to one of its two stable equilibrium points (refer to the description of the latch operation in Section 15.1). This is achieved by the regenerative action, inherent in positive feedback. Figure 15.21 clearly illustrates this point by showing the waveforms of the signal on the bit line for both a read-1 and a read-0 operation. Observe that once activated, the sense amplifier causes the small initial difference, ΔV(1) or ΔV(0), provided by the cell, to grow exponentially to either VDD (for a read-1 operation) or 0 (for a read-0 operation).
The waveforms of the signal on the B line will be complementary to those shown in Fig. 15.21 for the B line. In the following, we quantify the process of exponential growth of vB and vB.
vB.
vB V DD 2 ⁄ , V DD 2.
⁄ V DD 2 ⁄ 1230 Chapter 15 Memory Circuits A Closer Look at the Operation of the Sense Amplifier Developing a precise ex-pression for the output signal of the sense amplifier shown in Fig. 15.20 is a rather complex task requiring the use of large-signal (and thus nonlinear) models of the inverter voltage transfer characteristic, as well as taking the positive feedback into account. We will not do this here; rather, we shall consider the operation in a semiquantitative way.
Recall that at the time the sense amplifier is activated, each of its two inverters is operat-ing in the transition region near Thus, for small-signal operation, each inverter can be modeled using gmn and gmp, the transconductances of QN and QP, respectively, evaluated at an input bias of Specifically, a small-signal vi superimposed on at the input of one of the inverters gives rise to an inverter output current signal of (gmn + gmp) vi ≡ Gmvi.
This output current is delivered to one of the capacitors, CB or CB. The voltage thus devel-oped across the capacitor is then fed back to the other inverter and is multiplied by its Gm, which gives rise to an output current feeding the other capacitor, and so on, in a regenerative process. The positive feedback in this loop will mean that the signal around the loop, and thus vB and vB, will rise or decay exponentially (see Fig. 15.21) with a time constant of [or since we have been assuming CB = CB]. Thus, for example, in a read-1 operation we obtain (15.16) whereas in a read-0 operation, (15.17) Because these expressions have been derived assuming small-signal operation, they describe the exponential growth (decay) of vB reasonably accurately only for values close to Nevertheless, they can be used to obtain a reasonable estimate of the time required to develop a particular signal level on the bit line.
Figure 15.21 Waveforms of vB before and after the activation of the sense amplifier. In a read-1 operation, the sense amplifier causes the initial small increment ΔV(1) to grow exponentially to VDD. In a read-0 operation, the negative ΔV(0) grows to 0. Complementary signal waveforms develop on the B line.
V(1) VDD V(0) 0 V(1) V(0) Word line activated VDD /2 vB Sense amplifier activated Read 1 Read 0 t V DD 2 ⁄ .
V DD 2 ⁄ .
V DD 2 ⁄ (CB Gm ⁄ ) (CB Gm ⁄ ), vB V DD 2 ---------ΔV 1 ( )e Gm CB ⁄ t vB VDD ≤ , + = vB V DD 2 --------- Δ – V 0 ( )e Gm CB ⁄ ( )t = V DD 2.
⁄ 15.4 Sense Amplifiers and Address Decoders 1231 Obtaining Differential Operation in Dynamic RAMs The sense amplifier described earlier responds to difference signals appearing between the bit lines. Thus, it is capable of rejecting interference signals that are common to both lines, such as those caused by capacitive coupling from the word lines. For this common-mode rejection to be effective, great care has to be taken to match both sides of the amplifier, taking into account the circuits that feed each side.
This is an important consideration in any attempt to make the inherently single-ended output of the DRAM cell appear differential. We shall now discuss an ingenious scheme for accomplish-ing this task. Although the technique has been around for many years (see the first edition of this book, published in 1982), it is still in use today. The method is illustrated in Fig. 15.22.
Basically, each bit line is split into two identical halves. Each half-line is connected to half the cells in the column and to an additional cell, known as a dummy cell, having a storage capacitor CD = CS. When a word line on the left side is selected for reading, the dummy cell on the right side (controlled by ) is also selected, and vice versa; that is, when a word line on Consider the sense-amplifier circuit of Fig. 15.20 during the reading of a 1. Assume that the storage cell provides a voltage increment on the B line of ΔV(1) = 0.1 V. If the NMOS devices in the amplifiers have = 0.54 μm/ 0.18 μm and the PMOS devices have = 2.16 μm/0.18 μm, and assuming that VDD = 1.8 V, = 0.5 V, and μnCox = 4 μpCox = 300 μA/V2, find the time required for vB to reach 0.9 VDD. Assume CB = 1 pF.
Solution First, we determine the transconductances gmn and gmp Thus, the inverter Gm is and the time constant τ for the exponential growth of vB will be Now, the time, Δt, for vB to reach 0.9 VDD can be determined from resulting in Δt = 2.8 ns (W L ⁄ )n (W L ⁄ )p Vtn Vtp = gmn μnCox W L -----⎝ ⎠ ⎛ ⎞ n V GS Vt – ( ) = 300 0.54 0.18 ---------------× 0.9 0.5 – ( ) = 0.36 mA/V = gmp μpCox W L -----⎝ ⎠ ⎛ ⎞ p VGS Vt – ( ) = 75 2.16 0.18 ---------------× 0.9 0.5 – ( ) 0.36 mA V ⁄ = = Gm gmn gmp + 0.72 mA/V = = τ CB Gm -------≡ 1 10 12 – × 0.72 10 3 – × ---------------------------1.4 ns = = 0.9 1.8 × 0.9 0.1eΔt 1.4 ⁄ + = Example 15.2 φD 1232 Chapter 15 Memory Circuits the right side is selected, the dummy cell on the left (controlled by ) is also selected. In effect, then, the dummy cell serves as the other half of a differential DRAM cell. When the left-half bit line is in operation, the right-half bit line acts as its complement (or line) and vice versa.
Operation of the circuit in Fig. 15.22 is as follows: The two halves of the line are pre-charged to and their voltages are equalized. At the same time, the capacitors of the two dummy cells are precharged to Then a word line is selected, and the dummy cell on the other side is enabled (with or raised to VDD). Thus the half-line connected to the selected cell will develop a voltage increment (around of ΔV(1) or ΔV(0) depending on whether a 1 or a 0 is stored in the cell. Meanwhile, the other half of the line will have its voltage held equal to that of CD (i.e., The result is a differential signal of ΔV(1) or ΔV(0) that the sense amplifier detects and amplifies when it is enabled. As usual, by the end of the regenerative process, the amplifier will cause the voltage on one half of the line to become VDD and that on the other half to become 0.
Figure 15.22 An arrangement for obtaining differential operation from the single-ended DRAM cell. Note the dummy cells at the far right and far left.
CD CD D CS CS CS CS D Word lines Word lines Right dummy cell Left dummy cell Equalization and precharge Equalization and precharge Sense amplifier BK line 1 2 1 2 BK line φD B V DD 2 ⁄ V DD 2.
⁄ φD φD V DD 2 ⁄ ) V DD 2 ⁄ ).
15.9 It is required to reduce the time Δt of the sense-amplifier circuit in Example 15.2 by a factor of 2 by increasing gm of the transistors (while retaining the matched design of each inverter). What must the W/L ratios of the n- and p-channel devices become?
Ans. = 6; = 24 15.10 If in the sense amplifier of Example 15.2, the signal available from the cell is only half as large (i.e., only 50 mV), what will Δt become?
Ans. 3.7 ns, an increase of 32% (W L ⁄ )n (W L ⁄ )p EXERCISES 15.4 Sense Amplifiers and Address Decoders 1233 Alternative Precharging Arrangements If it is desired to precharge the B and lines to the arrangement in Fig. 15.23(a) can be utilized. Here precharging and equal-ization occur when is low. Then, just prior to the activation of the word line, goes high. Another precharging arrangement using diode-connected NMOS transistors is shown in Fig. 15.23(b). In this case, the B and lines are charged to and equalizes their voltages.
An Alternative Sense Amplifier Another popular implementation of the sense ampli-fier is the differential MOS amplifier with a current-mirror load, studied in detail in Section 8.5. Here, we present a brief overview of the operation of this versatile circuit as a sense amplifier.
The amplifier circuit is shown in Fig. 15.24 fed from the bit and lines (voltages and ). Transistors and are connected in the differential-pair configuration and are biased by a constant current I supplied by current source Transistors and form a current mirror, which acts as the load circuit for the amplifying transistors and The differential nature of the amplifier aids significantly in its effectiveness as a sense amplifier: It rejects noise or interference signals that are coupled equally to the B and lines, and amplifies only the small difference signals that appear between B and as a result of the read operation of a cell connected to the B and lines.
The amplifier is designed so that in normal small-signal operation, all transistors operate in the saturation region. Figure 15.24(b) shows the amplifier in its equilibrium state with Note that we have assumed that the B and lines are precharged to using the circuit in Fig. 15.23(b). It turns out that this voltage is particularly con-venient for the operation of this amplifier type as a sense amplifier. As indicated in Fig.
15.24(b), the bias current I divides equally between and thus each conducts a cur-rent The current of is fed to the input side of the current mirror, transistor thus the mirror provides an equal output current in the drain of At the output node, we see that we have two equal and opposite currents, leaving a zero current to flow into the load capacitor. Thus, in an ideal situation of perfect matching, will be equal to the voltage at the drain of Figure 15.23 Two alternative arrangements for precharging the bit line: (a) The B and lines are pre-charged to VDD; (b) the B and lines are charged to (VDD – Vt).
VDD – VDD Word Line Word Line B line B line (a) (b) Cell Cell Q7 Q7 Q8 Q9 fp – fp Q8 Q9 – B line B line – B B B VDD, φp φp B VDD Vt – ( ), Q7 bit vB vB Q1 Q2 Q5.
Q3 Q4 Q1 Q2.
B B B vB vB VDD Vt.
– = = B VDD Vt – ( ) Q1 Q2; I 2 ⁄ .
Q1 Q3; I 2 ⁄ Q4.
vO Q1.
1234 Chapter 15 Memory Circuits Next consider the situation when the B line shows an incremental voltage above the voltage of the line. As shown in Fig. 15.24(c), if is sufficiently large, will turn off and all the bias current I will flow through and on to Thus the mirror output current becomes I and flows through the amplifier output terminal to the equivalent output capaci-tance C. Thus C will charge to in time (15.18) The complementary situation when exceeds by is illustrated in Fig. 15.24(d).
Here and are turned off, and conducts all the current I. Thus capacitor C is discharged to ground by a constant current I.
Figure 15.24 The active-loaded MOS differential amplifier as a sense amplifier.
Q3 Q3 Q2 VR VR Q1 Q5 Q5 Q4 C Q3 I 2 Q4 C Q4 C Q2 Q1 Q2 Q5 C Q5 (a) (b) (c) (d) Q1 VR VB VR (VDD – Vt) (VDD – Vt) + V (VDD – Vt) + V (VDD – Vt) VDD VDD VDD vB vO vO vO vB – vB – vB – v O I I I I 0 I I I I 0 0 I I I 0 I 2 I 2 0 V Δ B V Δ Q2 Q1 Q3.
VDD t, Δ t CVDD I --------------= Δ vB vB V Δ Q1, Q3, Q4 Q2 15.4 Sense Amplifiers and Address Decoders 1235 An important question to answer before leaving this amplifier circuit is how large is that causes the current I to switch from one side of the differential pair to the other? The answer is given in Section 8.5 (see Fig. 8.32), namely, (15.19) where is the overdrive voltage at which and are operating in equilibrium, that is, (15.20) Finally, we note that this sense amplifier dissipates static power given by Observe that increasing I reduces the time in Eq. (15.18) at the expense of increased power dissipation.
15.4.2 The Row-Address Decoder As described in Section 15.2, the row-address decoder is required to select one of the 2M word lines in response to an M-bit address input. As an example, consider the case M = 3 and denote the three address bits A0, A1, and A2, and the eight word lines Conventionally, word line W0 will be high when A0 = 0, A1 = 0, and A2 = 0; thus we can express W0 as a Boolean function of A0, A1, and A2, Thus the selection of W0 can be accomplished by a three-input NOR gate whose three inputs are connected to A0, A1, and A2 and whose output is connected to word line 0. Word line W3 will be high when A0 = 1, A1 = 1, and A2 = 0; thus, Thus the selection of W3 can be realized by a three-input NOR gate whose three inputs are connected to and A2, and whose output is connected to word line 3. We can thus see that this address decoder can be realized by eight three-input NOR gates. Each NOR gate is fed with the appropriate combination of address bits and their complements, corresponding to the word line to which its output is connected.
A simple approach to realizing these NOR functions is provided by the matrix structure shown in Fig. 15.25. The circuit shown is a dynamic one (Section 14.3). Attached to each V Δ V 2VOV = Δ VOV Q1 Q2 I 2 ---1 2 --- μnCox ( ) W L -----⎝ ⎠ ⎛ ⎞ 1 2 , VOV 2 = P VDDI = t Δ D15.11 It is required to design the sense amplifier in Fig. 15.24 to detect an input signal and to provide a full output in 0.5 ns. If C = 50 fF and , find the required current I and the power dissipation.
Ans. 180 ; 324 V 100 mV = Δ VDD 1.8 V = μA μW EXERCISE W0,W1, …, W7.
W0 A0A1A2 A0 A1 A2 + + = = W3 A0A1A2 A0 A1 A2 + + = = A0 A1, , 1236 Chapter 15 Memory Circuits row line is a p-channel device that is activated, prior to the decoding process, using the pre-charge control signal φP. During precharge (φP low), all the word lines are pulled high to VDD. It is assumed that at this time the address input bits have not yet been applied and all the inputs are low; hence there is no need for the circuit to include the evaluation transistor uti-lized in dynamic logic gates. Then, the decoding operation begins when the address bits and their complements are applied. Observe that the NMOS transistors are placed so that the word lines not selected will be discharged. For any input combination, only one word line will not be discharged, and thus its voltage remains high at VDD. For instance, row 0 will be high only when A0 = 0, A1 = 0, and A2 = 0; this is the only combination that will result in all three transistors Figure 15.25 A NOR address decoder in array form. One out of eight lines (row lines) is selected using a 3-bit address.
Row 0 Row 1 Row 2 Row 3 Row 7 A0 A 0 A2 A1 VDD P A1 Row address A 2 . . . . .
P P P P 15.4 Sense Amplifiers and Address Decoders 1237 connected to row 0 being cut off. Similarly, row 3 has transistors connected to and A2, and thus it will be high when A0 = 1, A1 = 1, A2 = 0, and so on. After the decoder outputs have stabilized, the output lines are connected to the word lines of the array, usually via clock-con-trolled transmission gates. This decoder is known as a NOR decoder. Observe that because of the precharge operation, the decoder circuit does not dissipate static power. 15.4.3 The Column-Address Decoder From the description in Section 15.2, the function of the column-address decoder is to con-nect one of the 2N bit lines to the data I/O line of the chip. As such, it is a multiplexer and can be implemented using pass-transistor logic (Section 14.2) as shown in Fig. 15.26. Here, each bit line is connected to the data I/O line through an NMOS transistor. The gates of the pass transistors are controlled by 2N lines, one of which is selected by a NOR decoder similar to that used for decoding the row address. Finally, note that better performance can be obtained by utilizing transmission gates in place of NMOS transistors (Section 14.2). In such a case, however, the decoder needs to provide complementary output signals.
An alternative implementation of the column decoder that uses a smaller number of tran-sistors (but at the expense of slower speed of operation) is shown in Fig. 15.27. This circuit, known as a tree decoder, has a simple structure of pass transistors. Unfortunately, since a relatively large number of transistors can exist in the signal path, the resistance of the bit lines increases, and the speed decreases correspondingly.
Figure 15.26 A column decoder realized by a combination of a NOR decoder and a pass-transistor multiplexer.
A0 A1, , 15.12 How many transistors are needed for a NOR row decoder with an M-bit address?
Ans. M2M NMOS + 2M PMOS = 2M(M + 1) EXERCISE B0 0 1 2N1 B1 B2N1 N-bit column address Pass-transistor multiplexer AM AM1 AMN1 Bit lines NOR decoder I/O data 1238 Chapter 15 Memory Circuits 15.4.4 Pulse-Generation Circuits Memory chips require a large number of pulse signals, sometimes with intricate timing rela-tionships among them. It is not our purpose here to study this important subject; rather, we present two simple circuits that find widespread applicability in memory-chip timing as well as in other digital-system components, such as microprocessors.
The Ring Oscillator The ring oscillator is formed by connecting an odd number of invert-ers in a loop. Although usually at least five inverters are used, we illustrate the principle of operation using a ring of three inverters, as shown in Fig. 15.28(a). Figure 15.28(b) shows the waveforms obtained at the outputs of the three inverters. These waveforms are idealized in the sense that their edges have zero rise and fall times. Nevertheless, they will serve to explain the circuit operation.
Observe that a rising edge at node 1 propagates through gates 1, 2, and 3 to return inverted after a delay of 3tP. This falling edge then propagates, and returns with the original (rising) polarity after another 3tP interval. It follows that the circuit oscillates with a period Figure 15.27 A tree column decoder. Note that the colored path shows the transistors that are conducting when A0 = 1, A1 = 0, and A2 = 1, the address that results in connecting B5 to the data line.
B0 A0 B1 I/O data Bit lines A1 A1 A2 A2 B2 A0 B3 B4 A0 B5 B6 A0 B7 A1 A0 A0 A0 A0 A1 15.13 How many transistors are needed for a tree decoder when there are 2N bit lines?
Ans. 2(2N − 1) EXERCISE 15.4 Sense Amplifiers and Address Decoders 1239 of 6tP or correspondingly with frequency In general, a ring with N inverters (where N must be odd) will oscillate with a period of 2NtP and frequency As a final remark, we note that the ring oscillator provides a relatively simple means for measuring the inverter propagation delay.
A One-Shot or Monostable Multivibrator Circuit The one-shot or monostable mul-tivibrator circuit provides, when triggered, a single output pulse with a predetermined width.3 A variety of circuits exist for implementing the one-shot function, and some using op amps will be studied in Section 17.6. Here, in Fig. 15.29(a), we show a circuit commonly used in digital IC design. The circuit utilizes an exclusive-OR (XOR) gate together with a delay circuit. Recalling that the XOR gate provides a high output only when its two inputs are dissimilar, we see that prior to the arrival of the input positive step, the output will be Figure 15.28 (a) A ring oscillator formed by connecting three inverters in cascade. (Normally at least five inverters are used.) (b) The resulting waveform. Observe that the circuit oscillates with frequency 3The name “monostable” arises because this class of circuits has one stable state, which is the quiescent state. When a trigger is applied, the circuit moves to its quasi-stable state and stays in it for a predeter-mined length of time (the width of the output pulse). It then switches back automatically to the stable state.
1 2 3 1 v1 v2 v3 v1 G1 G2 G3 (a) v1 v2 v3 All delays tP Time (b) 1 6tP.
⁄ 1 6tP.
⁄ 1 2NtP ⁄ .
15.14 Find the frequency of oscillation of a ring of five inverters if the inverter propagation delay is spec-ified to be 1 ns.
Ans. 100 MHz EXERCISE 1240 Chapter 15 Memory Circuits low. When the input goes high, only the B input of the XOR will be high and thus its output will go high. The high input will reach input A of the XOR T seconds later, at which time both inputs of the XOR will be high and thus its output will go low. We thus see that the cir-cuit produces an output pulse with a duration T equal to the delay of the delay block for each transition of the input signal. The latter can be implemented by connecting an even number of inverters in cascade as shown in Fig. 15.29(b).
15.5 Read-only Memory (ROM) As mentioned in Section 15.2, read-only memory (ROM) is memory that contains fixed data patterns. It is used in a variety of digital-system applications. Currently, a very popular appli-cation is the use of ROM in microprocessor systems to store the instructions of the system’s basic operating program. ROM is particularly suited for such an application because it is nonvolatile; that is, it retains its contents when the power supply is switched off.
A ROM can be viewed as a combinational logic circuit for which the input is the collec-tion of address bits of the ROM and the output is the set of data bits retrieved from the addressed location. This viewpoint leads to the application of ROMs in code conversion— that is, in changing the code of the signal from one system (say, binary) to another. Code conversion is employed, for instance, in secure communication systems, where the process is known as scrambling. It consists of feeding the code of the data to be transmitted to a ROM that provides corresponding bits in a (supposedly) secret code. The reverse process, which also uses a ROM, is applied at the receiving end.
In this section we will study various types of read-only memory. These include fixed ROM, which we refer to simply as ROM, programmable ROM (PROM), and erasable pro-grammable ROM (EPROM).
15.5.1 A MOS ROM Figure 15.30 shows a simplified 32-bit (or 8-word × 4-bit) MOS ROM. As indicated, the mem-ory consists of an array of n-channel MOSFETs whose gates are connected to the word lines, whose sources are grounded, and whose drains are connected to the bit lines. Each bit line is con-nected to the power supply via a PMOS load transistor, in the manner of pseudo-NMOS logic Figure 15.29 (a) A one-shot or monostable circuit. Utilizing a delay circuit with a delay T and an XOR gate, this circuit provides an output pulse of width T. (b) The delay circuit can be implemented as the cascade of N inverters where N is even, in which case T = NtP.
T Delay Delay 1 2 N 0 t B A T (a) (b) T Y 0 t 15.5 Read-only Memory (ROM) 1241 To sense amplifiers W8 W1 W2 W3 W4 W5 W6 W7 Row decoder VDD B0 B3 B2 B1 Word address Figure 15.30 A simple MOS ROM organized as 8 words × 4 bits.
1242 Chapter 15 Memory Circuits (Section 14.1). An NMOS transistor exists in a particular cell if the cell is storing a 0; a cell stor-ing a 1 has no MOSFET. This ROM can be thought of as 8 words of 4 bits each. The row decoder selects one of the 8 words by raising the voltage of the corresponding word line. The cell transistors connected to this word line will then conduct, thus pulling the voltage of the bit lines (to which transistors in the selected row are connected) down from VDD to a voltage close to ground voltage (the logic-0 level). The bit lines that are connected to cells (of the selected word) without transistors (i.e., the cells that are storing a logic 1) will remain at the power-supply volt-age (logic 1) because of the action of the pull-up PMOS load devices. In this way, the bits of the addressed word can be read.
A disadvantage of the ROM circuit in Fig. 15.30 is that it dissipates static power. Spe-cifically, when a word is selected, the transistors in this particular row will conduct static current that is supplied by the PMOS load transistors. Static power dissipation can be eliminated by a simple change. Rather than grounding the gate terminals of the PMOS transistors, we can connect these transistors to a precharge line φ that is normally high.
Just before a read operation, φ is lowered and the bit lines are precharged to VDD through the PMOS transistors. The precharge signal φ then goes high, and the word line is selected. The bit lines that have transistors in the selected word are then discharged, thus indicating stored zeros, whereas those lines for which no transistor is present remain at VDD, indicating stored ones. 15.5.2 Mask-Programmable ROMs The data stored in the ROMs discussed thus far is determined at the time of fabrication, according to the user’s specifications. However, to avoid having to custom-design each ROM from scratch (which would be extremely costly), ROMs are manufactured using a 15.15 The purpose of this exercise is to estimate the various delay times involved in the operation of a ROM. Consider the ROM in Fig. 15.30 with the gates of the PMOS devices disconnected from ground and connected to a precharge control signal φ. Let all the NMOS devices have = 6 μm/2 μm and all the PMOS devices have = 24 μm/2 μm. Assume that μnCox = 50 μA/V2, μpCox = 20 μA/V2, Vtn = −Vtp = 1 V, and VDD = 5 V.
(a) During the precharge interval, φ is lowered to 0 V. Estimate the time required to charge a bit line from 0 V to 5 V. Use, as an average charging current, the current supplied by a PMOS transistor at a bit-line voltage halfway through the 0-V to 5-V excursion (i.e., 2.5 V). The bit-line capaci-tance is 2 pF. Note that all NMOS transistors are cut off at this time.
(b)After completion of the precharge interval and the return of φ to VDD, the row decoder raises the voltage of the selected word line. Because of the finite resistance and capacitance of the word line, the voltage rises exponentially toward VDD. If the resistance of each of the polysilicon word lines is 3 kΩ and the capacitance between the word line and ground is 3 pF, what is the (10% to 90%) rise time of the word-line voltage? What is the voltage reached at the end of one time constant?
(c) We account for the exponential rise of the word-line voltage by approximating the word-line volt-age by a step equal to the voltage reached in one time constant. Find the interval Δt required for an NMOS transistor to discharge the bit line and lower its voltage by 0.5 V. (It is assumed that the sense amplifier needs a 0.5-V change at its input to detect a low bit value.) Ans. (a) 6.1 ns; (b) 19.8 ns, 3.16 V; (c) 2.9 ns W L ⁄ W L ⁄ EXERCISE 15.5 Read-only Memory (ROM) 1243 process known as mask programming. As explained in Appendix A, integrated circuits are fabricated on a wafer of silicon using a sequence of processing steps that include photo-masking, etching, and diffusion. In this way, a pattern of junctions and interconnections is created on the surface of the wafer. One of the final steps in the fabrication process consists of coating the surface of the wafer with a layer of aluminum and then selectively (using a mask) etching away portions of the aluminum, leaving aluminum only where interconnec-tions are desired. This last step can be used to program (i.e., to store a desired pattern in) a ROM. For instance, if the ROM is made of MOS transistors as in Fig. 15.30, MOSFETs can be included at all bit locations, but only the gates of those transistors where 0s are to be stored are connected to the word lines; the gates of transistors where 1s are to be stored are not connected. This pattern is determined by the mask, which is produced according to the user’s specifications.
The economic advantages of the mask programming process should be obvious: All ROMs are fabricated similarly; customization occurs only during one of the final steps in fabrication.
15.5.3 Programmable ROMs (PROMs and EPROMs) PROMs are ROMs that can be programmed by the user, but only once. A typical arrange-ment employed in BJT PROMs involves using polysilicon fuses to connect the emitter of each BJT to the corresponding digit line. Depending on the desired content of a ROM cell, the fuse can be either left intact or blown out using a large current. The programming pro-cess is obviously irreversible.
An erasable programmable ROM, or EPROM, is a ROM that can be erased and repro-grammed as many times as the user wishes. It is therefore the most versatile type of read-only memory. It should be noted, however, that the process of erasure and reprogramming is time-consuming and is intended to be performed only infrequently.
State-of-the-art EPROMs use variants of the memory cell whose cross section is shown in Fig. 15.31(a). The cell is basically an enhancement-type n-channel MOSFET with two gates made of polysilicon material.4 One of the gates is not electrically connected to any Figure 15.31 (a) Cross section and (b) circuit symbol of the floating-gate transistor used as an EPROM cell.
4See Appendix A for a description of silicon-gate technology.
Si Oxide Si Drain n Source n Select gate Floating gate p-type silicon substrate (a) (b) Select gate D S 1244 Chapter 15 Memory Circuits other part of the circuit; rather, it is left floating and is appropriately called a floating gate.
The other gate, called a select gate, functions in the same manner as the gate of a regular enhancement MOSFET.
The MOS transistor of Fig. 15.31(a) is known as a floating-gate transistor and is given the circuit symbol shown in Fig. 15.31(b). In this symbol the broken line denotes the float-ing gate. The memory cell is known as the stacked-gate cell.
Let us now examine the operation of the floating-gate transistor. Before the cell is pro-grammed (we will shortly explain what this means), no charge exists on the floating gate and the device operates as a regular n-channel enhancement MOSFET. It thus exhibits the iD–vGS characteristic shown as curve (a) in Fig. 15.32. Note that in this case the threshold voltage (Vt) is rather low. This state of the transistor is known as the not-programmed state. It is one of two states in which the floating-gate transistor can exist. Let us arbi-trarily take the not-programmed state to represent a stored 1. That is, a floating-gate tran-sistor whose iD–vGS characteristic is that shown as curve (a) in Fig. 15.32 will be said to be storing a 1.
To program the floating-gate transistor, a large voltage (16–20 V) is applied between its drain and source. Simultaneously, a large voltage (about 25 V) is applied to its select gate.
Figure 15.33 shows the floating-gate MOSFET during programming. In the absence of any charge on the floating gate, the device behaves as a regular n-channel enhancement MOSFET: An n-type inversion layer (channel) is created at the wafer surface as a result of the large positive voltage applied to the select gate. Because of the large positive voltage at the drain, the channel has a tapered shape.
The drain-to-source voltage accelerates electrons through the channel. As these elec-trons reach the drain end of the channel, they acquire large kinetic energy and are referred to as hot electrons. The large positive voltage on the select gate (greater than the drain voltage) establishes an electric field in the insulating oxide. This electric field attracts the hot electrons and accelerates them (through the oxide) toward the floating gate. In this way the floating gate is charged, and the charge that accumulates on it becomes trapped. Figure 15.32 Illustrating the shift in the iD–vGS characteristic of a floating-gate transistor as a result of pro-gramming.
iD 0 (a) (b) Not programmed (1) Programmed (0) Sense voltage vGS 15.5 Read-only Memory (ROM) 1245 Fortunately, the process of charging the floating gate is self-limiting. The negative charge that accumulates on the floating gate reduces the strength of the electric field in the oxide to the point that it eventually becomes incapable of accelerating any more of the hot electrons. Let us now inquire about the effect of the floating gate’s negative charge on the opera-tion of the transistor. The negative charge trapped on the floating gate will cause electrons to be repelled from the surface of the substrate. This implies that to form a channel, the positive voltage that has to be applied to the select gate will have to be greater than that required when the floating gate is not charged. In other words, the threshold voltage Vt of the pro-grammed transistor will be higher than that of the not-programmed device. In fact, program-ming causes the iD–vGS characteristic to shift to the curve labeled (b) in Fig. 15.32. In this state, known as the programmed state, the cell is said to be storing a 0.
Once programmed, the floating-gate device retains its shifted i–v characteristic (curve b) even when the power supply is turned off. In fact, extrapolated experimental results indicate that the device can remain in the programmed state for as long as 100 years!
Reading the content of the stacked-gate cell is easy: A voltage VGS somewhere between the low and high threshold values (see Fig. 15.32) is applied to the selected gate. While a programmed device (one that is storing a 0) will not conduct, a not-programmed device (one that is storing a 1) will conduct heavily.
To return the floating-gate MOSFET to its not-programmed state, the charge stored on the floating gate has to be returned to the substrate. This erasure process can be accom-plished by illuminating the cell with ultraviolet light of the correct wavelength (2537 Å) for a specified duration. The ultraviolet light imparts sufficient photon energy to the trapped electrons to allow them to overcome the inherent energy barrier, and thus be transported through the oxide, back to the substrate. To allow this erasure process, the EPROM package contains a quartz window. Finally, it should be noted that the device is extremely durable, and can be erased and programmed many times.
A more versatile programmable ROM is the electrically erasable PROM (or EEPROM).
As the name implies, an EEPROM can be erased and reprogrammed electrically without the need for ultraviolet illumination. EEPROMs utilize a variant of the floating-gate MOSFET. An important class of EEPROMs using a floating gate variant and implementing block erasure are referred to as flash memories.
Figure 15.33 The floating-gate transistor during programming.
25 V Oxide 16 V Select gate n channel Source n Drain n Depletion layer p substrate 1246 Chapter 15 Memory Circuits Summary Flip-flops employ one or more latches. The basic static latch is a bistable circuit implemented using two inverters connected in a positive-feedback loop. The latch can remain in either stable state indefinitely.
As an alternative to the positive-feedback approach, memory can be provided through the use of charge stor-age. A number of CMOS flip-flops are realized this way, including some master–slave D flip-flops.
A random-access memory (RAM) is one in which the time required for storing (writing) information and for retrieving (reading) information is independent of the physical location (within the memory) in which the infor-mation is stored.
The major part of a memory chip consists of the cells in which the bits are stored and that are typically organized in a square matrix. A cell is selected for reading or writing by activating its row, via the row-address decoder, and its column, via the column-address decoder. The sense amplifier detects the content of the selected cell and pro-vides a full-swing version of it to the data-output terminal of the chip.
There are two kinds of MOS RAM: static and dynamic.
Static RAMs (SRAMs) employ flip-flops as the storage cells. In a dynamic RAM (DRAM), data is stored on a capacitor and thus must be periodically refreshed. DRAM chips provide the highest possible storage capacity for a given chip area.
Two circuits have emerged as the near-universal choice in implementing the storage cell: the six-transistor SRAM cell and the one-transistor DRAM cell. Although sense amplifiers are utilized in SRAMs to speed up operation, they are essential in DRAMs. A particular type of sense amplifier is a differential circuit that em-ploys positive feedback to obtain an output signal that grows exponentially toward either VDD or 0.
Read-only memory (ROM) contains fixed data patterns that are stored at the time of fabrication and cannot be changed by the user. On the other hand, the contents of an erasable programmable ROM (EPROM) can be changed by the user. The erasure and reprogramming is a time-consuming process and is performed only infrequently.
Some EPROMS utilize floating-gate MOSFETs as the storage cells. The cell is programmed by applying (to the selected gate) a high voltage, which in effect changes the threshold voltage of the MOSFET. Erasure is achieved by illuminating the chip by ultraviolet light. Even more ver-satile, EEPROMs can be erased and reprogrammed elec-trically.
PROBLEMS PROBLEMS Problems involving design are marked with D throughout the text. As well, problems are marked with asterisks to describe their degree of difficulty. Difficult problems are marked with an asterisk (); more difficult problems with two asterisks (); and very challenging and/or time-con-suming problems with three asterisks ().
Section 15.1: Latches and Flip-Flops D 15.1 Sketch the standard CMOS circuit implementation of the SR flip-flop shown in Fig. 15.3.
D 15.2 Sketch the logic-gate implementation of an SR flip-flop utilizing two cross-coupled NAND gates. Clearly label the output terminals and the input trigger terminals. Provide the truth table and describe the operation.
D 15.3 For the SR flip-flop of Fig. 15.4, show that if each of the two inverters utilizes matched transistors, that is, then the minimum W/L that each of must have so that switching occurs is Give the sizes of all eight transistors if the flip-flop is fabricated in a 0.13-μm process for which Use the minimum channel length for all transis-tors and the minimum size (W/L = 1) for and .
D 15.4 In this problem we investigate the effect of velocity saturation (Section 13.5) on the design of the SR flip-flop in Example 15.1. Specifically, answer part (a) of the question in Example 15.1, taking into account the fact that for this technology, for n-channel devices is 0.6 V and for p-channel devices is 1 V. Assume What is the minimum required value for and for Comment on this value rel-ative to that found in Example 15.1. (Hint: Refer to Eq.
13.100.) D 15.5 Repeat part (a) of the problem in Example 15.1 for the case of inverters that do not use matched and Rather, assume that each of the inverters uses Find the threshold voltage of each inverter. Then determine the value required for the W/L of each of to so that the flip-flop switches.
D 15.6 The CMOS SR flip-flop in Fig. 15.4 is fabricated in a 0.13-μm process for which μnCox= 4μpCox = 430 μΑ/V 2, , and The inverters have and (W/L)p = 0.8 μm/ 0.13 μm. The four NMOS transistors in the set–reset circuit have equal W/L ratios. (a) Determine the minimum value required for this ratio to ensure that the flip-flop will switch. (b) If a ratio twice the minimum is selected, determine the minimum required width of the set and reset pulses to ensure switching. Assume that the total capacitance between each of the Q and nodes and ground is 20 fF. D 15.7 Consider another possibility for the circuit in Fig.
15.7: Relabel the R input as and the S input as . Let and normally rest at Let the flip-flop be storing a 0; thus and To set the flip-flop, the terminal is lowered to 0 V and the clock is raised to The relevant part of the circuit is then transistors and For the flip-flop to switch, the voltage at must be lowered to What is the minimum required W/L for in terms of and D 15.8 The clocked SR flip-flop in Fig. 15.4 is not a fully complementary CMOS circuit. Sketch the fully comple-mentary version by augmenting the circuit with the PUN corresponding to the PDN comprising Q5, Q6, Q7, and Q8.
Note that the fully complementary circuit utilizes 12 tran-sistors. Although the circuit is more complex, it switches faster.
15.9 Consider the latch of Fig. 15.1 as implemented in CMOS technology. Let μnCox = 2μpCox = 20 Wp = 2Wn = 24 μm, Lp = Ln = 6 μm, and VDD = 5 V.
(a) Plot the transfer characteristic of each inverter—that is, vX versus vW, and vZ versus vY. Determine the output of each inverter at input voltages of 1, 1.5, 2, 2.25, 2.5, 2.75, 3, 3.5, 4, and 5 volts.
(b) Use the characteristics in (a) to determine the loop voltage-transfer curve of the latch—that is, vZ versus vW.
Find the coordinates of points A, B, and C as defined in Fig.
15.1(c).
(c) If the finite output resistance of the saturated MOSFET is taken into account, with , find the slope of the loop transfer characteristic at point B. What is the approximate width of the transition region?
15.10 Two CMOS inverters operating from a 5-V supply have VIH and VIL of 2.42 and 2.00 V and corresponding out-puts of 0.4 V and 4.6 V, respectively, and are connected as a latch. The MOSFETs have Approximating the corresponding transfer characteristic of each gate by straight lines between the break points, sketch the latch open-loop transfer characteristic. What are the coordinates of point B? What is the loop gain at B?
15.11 Figure P15.11 shows a commonly used circuit of a D flip-flop that is triggered by the negative-going edge of the clock .
(a) For high, what are the values of and Q in terms of D? Which transistors are conducting?
(b) If D is high and goes low, which transistors conduct and what signals appear at and at Q? Describe the circuit operation.
W L ⁄ ( )p μn μp ⁄ ( ) W L ⁄ ( )n, = Q5 Q8 – 2 W L ⁄ ( )n.
μn 4μp.
= Q1 Q3 VDSsat VDSsat λn λp 0.1 V 1 – .
= = W L ⁄ ( )5 W L ⁄ ( )6?
QN QP.
W L ⁄ ( )p W L ⁄ ( )n 0.27 μm 0.18 μm.
⁄ = = Q5 Q8 Vtn Vtp 0.4 V = = VDD 1.2 V.
= W L ⁄ ( )n 0.2 μm 0.13 μm ⁄ = Q S R S R VDD.
VQ 0 V = VQ VDD.
= S φ VDD.
Q5 Q2.
Q VDD 2 ⁄ .
Q5 W L ⁄ ( )2 μn μp ⁄ ( )?
μA/V2, Vt 1 V, = VA 100 V = Vt 1 V.
= φ φ Q φ Q CHAPTER 15 PR OBLE MS 1248 Chapter 15 Memory Circuits (c) Repeat (b) for D low with the clock going low. (d) Does the operation of this circuit rely on charge storage?
Section 15.2: Semiconductor Memories: Types and Architectures 15.12 A particular 1 M-bit square memory array has its periph-eral circuits reorganized to allow for the readout of a 16-bit word. How many address bits will the new design need?
15.13 For the memory chip described in Problem 15.12, how many word lines must be supplied by the row decoder? How many sense amplifiers/drivers would a straightforward implementation require? If the chip power dissipation is 500 mW with a 5-V supply for continuous operation with a 200-ns cycle time, and all the power loss is dynamic, estimate the total capacitance of all logic acti-vated in any one cycle. If we assume that 90% of this power loss occurs in array access, and that the major capacitance contributor will be the bit line itself, calculate the capacitance per bit line and per bit for this design.
(Recall from problem 15.12 that 16 bit lines are selected simultaneously.) If closer manufacturing control allows the memory array to operate at 3 V, how much larger a mem-ory array can be designed in the same technology at about the same power level?
15.14 An experimental 1.5-V, 1-Gbit dynamic RAM (called DRAM) by Hitachi uses a 0.16-μm process with a cell size of 0.38 × 0.76 μm2 in a 19 × 38 mm2 chip. What fraction of the chip is occupied by the I/O connections, peripheral cir-cuits, and interconnect?
Section 15.3: Random-Access Memory (RAM) Cells 15.15 Consider the read operation of the 6T SRAM cell of Fig. 15.12 when it is storing a 0, that is, and Assume that the bit lines are precharged to before the word-line voltage is raised to Sketch the rele-vant part of the circuit and describe the operation. Show that the analysis parallels that presented in the text for the read-1 operation.
D 15.16 Consider a 6T SRAM cell fabricated in a 0.18-μm CMOS process for which and If during a read-1 operation it is required that does not exceed 0.2 V, use the graph in Fig. 15.14 to determine the maximum allowable value of the ratio For select val-ues for and that minimize the combined areas of and Assume that the minimum width allowed is 0.18 μm.
15.17 Repeat Exercise 15.4 for an SRAM fabricated in a 0.25-μm CMOS process for which and 15.18 Repeat Exercise 15.4 for an SRAM fabricated in a 0.13-μm CMOS process for which and 15.19 Locate on the graph of Fig. 15.14 the points A, B, and C that correspond to the following three process technologies: (a) 0.25-μm: and (b) 0.18-μm: and (c) 0.13-μm: and In each case, impose the condition that in a read-1 operation 15.20 Refer to the circuit in Fig. 15.13 and find the max-imum ratio for this time taking into account the velocity-saturation effect (Section 13.5, Eq. 13.100). The SRAM is fabricated in a 0.18-μm CMOS process for which and for the n-channel devices Compare to the value obtained without accounting for velocity saturation. (Hint: Convince yourself that for this situation only will be operating in velocity saturation.) D 15.21 For the 6T SRAM of Fig. 15.12, fabricated in a 0.18-μm CMOS process for which and = 0.3 V1/2, find the maximum ratio for which during a read-1 operation (Fig. 15.13). Take into account the body effect in Compare to the value obtained without accounting for the body effect.
D 15.22 A 6T SRAM cell is fabricated in a 0.13-μm CMOS process for which and The inverters utilize (W/L)n = 1.
Each of the bit lines has a 2-pF capacitance to ground. The sense amplifier requires a minimum of 0.2-V input for reli-able and fast operation.
φ Q1 D f G1 G2 G3 Q4 Q2 VDD Q Q – Q3 Q5 Q6 Figure P15.11 VQ 0 V, = VQ VDD.
= VDD VDD.
Vtn Vtp 0.5 V = = VDD 1.8 V.
= VQ W L ⁄ ( )5 W L ⁄ ( )1 ⁄ .
L1 L5 0.18 μm, = = W1 W5 Q1 Q5.
VDD 2.5 V = Vt 0.5 V.
= VDD 1.2 V = Vt 0.4 V.
= VDD 2.5 V = Vt 0.5 V = VDD 1.8 V = Vt 0.5 V = VDD 1.2 V = Vt 0.4 V = VQ Vt.
= W L ⁄ ( )5 W L ⁄ ( )1 ⁄ VQ Vt, ≤ VDD 1.8 V, = Vt 0.5 V, = VDSsat 0.6 V.
= Q5 VDD 1.8 V, = Vt0 = 0.5 V, 2φf 0.8 V, = γ W L ⁄ ( )5 W L ⁄ ( )1 ⁄ VQ Vt0 ≤ Q5.
VDD 1.2 V, = Vt 0.4 V, = μnCox 430 μA V2 ⁄ .
= Problems 1249 CHAPTER 15 PR OBLEM S (a) Find the upper bound on for each of the access transistors so that and do not change by more than volts during the read operation.
(b) Find the delay time encountered in the read operation if the cell design utilizes minimum-size access transistors.
(c) Find the delay time if the design utilizes the maxi-mum allowable size for the access transistors.
15.23 Consider the operation of writing a 1 into a 6T SRAM cell that is originally storing a 0. Sketch the relevant part of the circuit and explain the operation. Without doing detailed analysis, show that the analysis would lead to results identical to those obtained in the text for the write-0 operation.
D 15.24 For a 6T SRAM cell fabricated in a 0.13-μm CMOS process, find the maximum permitted value of in terms of of the access transistors. Assume , , and .
D 15.25 For a 6T SRAM cell fabricated in a 0.25-μm CMOS process, find the maximum permitted value of in terms of of the access transistors. Assume and 15.26 Locate on the graph in Fig. 15.17 the points A, B, and C corresponding to the following three CMOS fabrica-tion processes: (a) 0.25-μm: (b) 0.18-μm: (c) 0.13-μm: For all three, In each case, is to be limited to a maximum value of D 15.27 Design a minimum-size 6T SRAM cell in a 0.13-μm process for which and All transistors are to have equal L = 0.13 μm.
Assume that the minimum width allowed is 0.13 μm. Verify that your minimum-size cell meets the constraints in Eqs.
(15.5) and (15.11).
15.28 For a particular DRAM design, the cell capaci-tance CS = 30 fF and VDD = 1.8 V. Each cell represents a capacitive load on the bit line of 1 fF. Assume a 28-fF capacitance for the sense amplifier and other circuitry attached to the bit line. What is the maximum number of cells that can be attached to a bit line while ensuring a minimum bit-line signal of 0.05 V? How many bits of row addressing can be used? If the sense-amplifier gain is increased by a factor of 5, how many word-line address bits can be accommodated?
15.29 For a DRAM available for regular use 98% of the time, having a row-to-column ratio of 2 to 1, a cycle time of 20 ns, and a refresh cycle of 8 ms, estimate the total memory capacity.
15.30 In a particular dynamic memory chip, CS = 25 fF, the bit-line capacitance per cell is 0.5 fF, and bit-line control circuitry involves 12 fF. For a 1-Mbit-square array, what bit-line signals result when a stored 1 is read? When a stored 0 is read? Assume that VDD = 1.8 V.
15.31 For a DRAM cell utilizing a capacitance of 20 fF, refresh is required within 10 ms. If a signal loss on the capacitor of 0.2 V can be tolerated, what is the largest acceptable leakage current present at the cell?
Section 15.4: Sense Amplifiers and Address Decoders D 15.32 Consider the operation of the differential sense amplifier of Fig. 15.20 following the rise of the sense con-trol signal φs. Assume that a balanced differential signal of 0.1 V is established between the bit lines, each of which has a 1 pF capacitance. For VDD = 3 V, what is the value of Gm of each of the inverters in the amplifier required to cause the outputs to reach 0.1VDD and 0.9VDD [from initial values of 0.5VDD + and 0.5VDD − volts, respec-tively] in 2 ns? If for the matched inverters, = 0.8 V and = 3 = 75 μA/V2, what are the device widths required? If the input signal is 0.2 V, what does the amplifier response time become?
15.33 A particular version of the regenerative sense ampli-fier of Fig. 15.20 in a 0.5-μm technology, uses transistors for which = 0.8 V, = 2.5 = 100 μA/V2, VDD = 3.3 V, with ( )n = and ( )p = / . For each inverter, find the value of Gm. For a bit-line capacitance of 0.8 pF, and a delay until an output of 0.9VDD is reached of 2 ns, find the initial difference-voltage required between the two bit lines. If the time can be relaxed by 1 ns, what input signal can be handled? With the increased delay time and with the input signal at the original level, by what percentage can the bit-line capacitance, and corre-spondingly the bit-line length, be increased? If the delay time required for the bit-line capacitances to charge by the constant current available from the storage cell, and thus develop the difference-voltage signal needed by the sense amplifier, was 5 ns, what does it increase to when longer lines are used?
D 15.34 (a) For the sense amplifier of Fig. 15.20, show that the time required for the bit lines to reach 0.9VDD and 0.1VDD is given by where W L ⁄ VQ VQ Vt Δt Δt W L ⁄ ( )p W L ⁄ ( )a VDD 1.2 V = Vtn Vtp 0.4 V = = μn 4μp = W L ⁄ ( )p W L ⁄ ( )a VDD 2.5 V, = Vtn Vtp 0.5 V, = = μn 4μp.
VDD 2.5 V, = Vtn Vtp 0.5 V = = VDD 1.8 V, = Vtn Vtp 0.5 V = = VDD 1.2 V, = Vtn Vtp 0.4 V = = μn 4μp.
VQ Vtn.
VDD 1.2 V = Vtn Vtp = = 0.4 V.
0.1 2 ⁄ ( ) 0.1 2 ⁄ ( ) Vt kn ′ kp ′ Vt kn ′ kp ′ W L ⁄ 6 μm 1.5 ⁄ μm W L ⁄ 15 μm 1.5 μm td = (CB Gm)ln (0.8VDD ΔV ⁄ ) ⁄ CHAPTER 15 PR OBLE MS 1250 Chapter 15 Memory Circuits ΔV is the initial difference-voltage between the two bit lines.
(Refer to Fig. 15.21.) (b) If the response time of the sense amplifier is to be reduced to one-half the value of an original design, by what factor must the width of all transistors be increased?
(c) If for a particular design, VDD = 1.8 V and ΔV = 0.2 V, find the factor by which the width of all transistors must be increased so that ΔV is reduced by a factor of 4 while keep-ing td unchanged?
D 15.35 It is required to design a sense amplifier of the type shown in Fig. 15.20 to operate with a DRAM using the dummy-cell technique illustrated in Fig. 15.22. The DRAM cell provides readout voltages of −100 mV when a 0 is stored and +40 mV when a 1 is stored. The sense amplifier is required to provide a differential output voltage of 2 V in at most 5 ns. Find the ratios of the transistors in the amplifier inverters, assuming that the processing technology is characterized by = 2.5 = 100 μA/V2, = 1 V, and VDD = 5 V. The capacitance of each half bit line is 1 pF.
What will be the amplifier response time when a 0 is read?
When a 1 is read?
D 15.36 It is required to design the sense amplifier of Fig.
15.24 to detect an input signal of 100 mV and provide a full output in 0.3 ns. If C = 60 fF and find the required current I and the power dissipation.
D 15.37 Consider the sense amplifier in Fig. 15.24 in the equilibrium condition shown in part (b) of the figure. Let and (a) If and are to operate at the edge of saturation, what is the dc voltage at the drain of (b) If the switching voltage is to be about 140 mV, at what overdrive voltage should and be oper-ated in equilibrium? What dc voltage should appear at the common-source terminals of and (c) If the delay component given by Eq. (15.18) is to be 0.5 ns, what current I is needed if C = 55 fF?
(d) Find the W/L required for each of to for (e) If is to operate at the same overdrive voltage as and find its required and the value of the refer-ence voltage 15.38 Consider a 512-row NOR decoder. To how many address bits does this correspond? How many output lines does it have? How many input lines does the NOR array require? How many NMOS and PMOS transistors does such a design need?
15.39 For the column decoder shown in Fig. 15.26, how many column-address bits are needed in a 256-Kbit square array? How many NMOS pass transistors are needed in the multiplexer? How many NMOS transistors are needed in the NOR decoder? How many PMOS transistors? What is the total number of NMOS and PMOS transistors needed?
15.40 Consider the use of the tree column decoder shown in Fig. 15.27 for application with a square 256-Kbit array. How many address bits are involved? How many levels of pass gates are used? How many pass transistors are there in total?
W L ⁄ kn ′ kp ′ Vt VDD 1.2 V, = VDD 1.8 V = Vt 0.5 V.
= Q1 Q2 Q1?
V Δ VOV Q1 Q2 Q1 Q2?
t Δ Q1 Q4 μnCox 4μpCox 300 μA V2 ⁄ .
= = Q5 Q1 Q2, W L ⁄ VR, Problems 1251 CHAPTER 15 PR OBLEM S 15.41 Consider a ring oscillator consisting of five inverters, each having ns and ns. Sketch one of the output waveforms, and specify its frequency and the per-centage of the cycle during which the output is high.
15.42 A ring-of-eleven oscillator is found to operate at 20 MHz. Find the propagation delay of the inverter.
D 15.43 Design the one-shot circuit of Fig. 15.29 to pro-vide an output pulse of 10-ns width. If the inverters avail-able have ns delay, how many inverters do you need for the delay circuit?
Section 15.5: Read-Only Memory (ROM) 15.44 Give the eight words stored in the ROM of Fig. 15.30.
D 15.45 Design the bit pattern to be stored in a (16 × 4) ROM that provides the 4-bit product of two 2-bit variables.
Give a circuit implementation of the ROM array using a form similar to that of Fig. 15.30.
15.46 Consider a dynamic version of the ROM in Fig. 15.30 in which the gates of the PMOS devices are connected to a precharge control signal φ. Let all the NMOS devices have = and all the PMOS devices have = Assume = 3 = 90 μA/V2, Vtn = −Vtp = 1 V, and VDD = 5 V.
(a) During the precharge interval, φ is lowered to 0 V. Esti-mate the time required to charge a bit line from 0 to 5 V.
Use as an average charging current the current supplied by a PMOS transistor at a bit-line voltage halfway through the 0 to 5 V excursion (i.e., 2.5 V). The bit-line capacitance is 1 pF. Note that all NMOS transistors are cut off at this time.
(b) After the precharge interval is completed and φ returns to VDD, the row decoder raises the voltage of the selected word line. Because of the finite resistance and capacitance of the word line, the voltage rises exponentially toward VDD. If the resistance of each of the polysilicon word lines is 5 kΩ and the capacitance between the word line and ground is 2 pF, what is the (10% to 90%) rise time of the word-line voltage? What is the voltage reached at the end of one time-constant?
(c) If we approximate the exponential rise of the word-line voltage by a step equal to the voltage reached in one time constant, find the interval Δt required for an NMOS transistor to discharge the bit line and lower its voltage by 1 V.
tPLH 6 = tPHL 4 = tP 2.5 = W L ⁄ 3 μm 1.2 ⁄ μm W L ⁄ 12 μm 1.2 ⁄ μm.
kn ′ kp ′ CHAPTER 16 Filters and Tuned Amplifiers 1254 CHAPTER 17 Signal Generators and Waveform-Shaping Circuits 1334 PART IV Filters and Oscillators 1253 n Part IV we study an important class of analog circuits: filters and oscillators. Both topics have in common an application or system orientation. They provide dramatic and powerful illustration of the application of both negative and positive feedback.
While the filters studied here are linear circuits, the design of oscillators makes use of both linear and nonlinear techniques.
Chapter 16 deals with the design of filters, which are important building blocks of communication and instrumentation systems. Filter design is one of the rare areas of en-gineering for which a complete design theory exists, starting from specification and cul-minating in an actual working circuit. The material presented should allow the reader to perform such a complete design process.
In the design of electronic systems, the need usually arises for signals of various waveforms—sinusoidal, pulse, square-wave, and so on. The generation of such signals is the subject of Chapter 17. It will be seen that some of the circuits utilized in waveform generation employ an op-amp version of the basic memory element studied in Chapter 15, the bistable multivibrator or latch.
The study of filters and oscillators relies on a thorough familiarity with basic feed-back concepts including the effect of feedback on the amplifier poles (Chapter 10), and with op-amp circuit applications (Chapter 2). As well, we assume knowledge of basic s-plane concepts including transfer functions, poles, zeros, and Bode plots.
I CHAPTER 16 Filters and Tuned Amplifiers Introduction 1255 16.1 Filter Transmission, Types, and Specification 1256 16.2 The Filter Transfer Function 1260 16.3 Butterworth and Chebyshev Filters 1263 16.4 First-Order and Second-Order Filter Functions 1270 16.5 The Second-Order LCR Resonator 1279 16.6 Second-Order Active Filters Based on Inductor Replacement 1285 16.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1293 16.8 Single-Amplifier Biquadratic Active Filters 1299 16.9 Sensitivity 1307 16.10 Switched-Capacitor Filters 1310 16.11 Tuned Amplifiers 1315 Summary 1327 Problems 1328 1255 IN THIS CHAPTER YOU WILL LEARN 1. How filters are characterized by their signal-transmission properties and how they are classified into different types based on the relative location of their passband(s) and stopband(s).
2. How filters are specified and how to obtain a filter transfer function that meets the given specifications, including the use of popular spe-cial functions such as the Butterworth and the Chebyshev.
3. The various first-order and second-order filter functions and their real-ization using op amps and RC circuits.
4. The basic second-order LCR resonator and how it can be used to real-ize the various second-order filter functions.
5. The best op amp–RC circuit for realizing an inductance and how it can be used as the basis for realizing the various second-order filter functions.
6. That connecting two op-amp integrators, one inverting and one nonin-verting, in a feedback loop realizes a second-order resonance circuit and can be used to obtain circuit realizations of the various second-order filter functions.
7. How second-order filter functions can be realized using a single op amp and an RC circuit, and the performance limitations of these mini-mal realizations.
8. How the powerful concept of circuit sensitivity can be applied to assess the performance of filter circuits in the face of finite component tolerances.
9. The basis for the most popular approach to the realization of filter functions in IC form; the switched-capacitor technique.
10. The design of tuned transistor amplifiers for radio-frequency (RF) applications.
Introduction In this chapter, we study the design of an important building block of communications and instrumentation systems, the electronic filter. Filter design is one of the very few areas of 1256 Chapter 16 Filters and Tuned Amplifiers engineering for which a complete design theory exists, starting from specification and ending with a circuit realization. A detailed study of filter design requires an entire book, and indeed such textbooks exist. In the limited space available here, we shall concentrate on a selection of topics that provide an introduction to the subject as well as a useful arsenal of filter cir-cuits and design methods.
The oldest technology for realizing filters makes use of inductors and capacitors, and the resulting circuits are called passive LC filters. Such filters work well at high frequen-cies; however, in low-frequency applications (dc to 100 kHz) the required inductors are large and physically bulky, and their characteristics are quite nonideal. Furthermore, such induc-tors are impossible to fabricate in monolithic form and are incompatible with any of the modern techniques for assembling electronic systems. Therefore, there has been consider-able interest in finding filter realizations that do not require inductors. Of the various possi-ble types of inductorless filters, we shall study active-RC filters and switched-capacitor filters.
Active-RC filters utilize op amps together with resistors and capacitors and are fabricated using discrete, hybrid thick-film, or hybrid thin-film technology. However, for large-volume production, such technologies do not yield the economies achieved by monolithic (IC) fabrica-tion. At the present time, the most viable approach for realizing fully integrated monolithic filters is the switched-capacitor technique.
The last topic studied in this chapter is the tuned amplifier commonly employed in the design of radio and TV receivers. Although tuned amplifiers are in effect bandpass filters, they are studied separately because their design is based on somewhat different techniques.
The material in this chapter requires a thorough familiarity with op-amp circuit applica-tions. Thus the study of Chapter 2 is a prerequisite.
16.1 Filter Transmission, Types, and Specification 16.1.1 Filter Transmission The filters we are about to study are linear circuits that can be represented by the general two-port network shown in Fig. 16.1. The filter transfer function T(s) is the ratio of the output voltage V o(s) to the input voltage Vi(s), (16.1) The filter transmission is found by evaluating T(s) for physical frequencies, s = jω, and can be expressed in terms of its magnitude and phase as (16.2) The magnitude of transmission is often expressed in decibels in terms of the gain function (16.3) or, alternatively, in terms of the attenuation function (16.4) A filter shapes the frequency spectrum of the input signal, , according to the magnitude of the transfer function , thus providing an output V o(jω) with a spectrum T(s) ≡Vo s ( ) Vi s ( ) -------------T jω ( ) = T jω ( ) ejφ ω ( ) G(ω) ≡20 log T jω ( ) , dB A(ω) ≡ 20 log T jω ( ) , dB – Vi jω ( ) T jω ( ) 16.1 Filter Transmission, Types, and Specification 1257 (16.5) Also, the phase characteristics of the signal are modified as it passes through the filter according to the filter phase function φ(ω).
16.1.2 Filter Types We are specifically interested here in filters that perform a frequency-selection function: pass-ing signals whose frequency spectrum lies within a specified range, and stopping signals whose frequency spectrum falls outside this range. Such a filter has ideally a frequency band (or bands) over which the magnitude of transmission is unity (the filter passband) and a fre-quency band (or bands) over which the transmission is zero (the filter stopband). Figure 16.2 depicts the ideal transmission characteristics of the four major filter types: low-pass (LP) in Fig. 16.2(a), high-pass (HP) in Fig. 16.2(b), bandpass (BP) in Fig. 16.2(c), and bandstop (BS) or band-reject in Fig. 16.2(d). These idealized characteristics, by virtue of their vertical edges, are known as brick-wall responses.
16.1.3 Filter Specification The filter-design process begins with the filter user specifying the transmission characteris-tics required of the filter. Such a specification cannot be of the form shown in Fig. 16.2 because physical circuits cannot realize these idealized characteristics. Figure 16.3 shows realistic specifications for the transmission characteristics of a low-pass filter. Observe that since a physical circuit cannot provide constant transmission at all passband frequencies, the specifications allow for deviation of the passband transmission from the ideal 0 dB, but place an upper bound, Amax (dB), on this deviation. Depending on the application, Amax typically ranges from 0.05 dB to 3 dB. Also, since a physical circuit cannot provide zero transmission at all stopband frequencies, the specifications in Fig. 16.3 allow for some transmission over the stopband. However, the specifications require the stopband signals to be attenuated by at least Amin (dB) relative to the passband signals. Depending on the filter application, Amin can range from 20 dB to 100 dB.
Since the transmission of a physical circuit cannot change abruptly at the edge of the passband, the specifications of Fig. 16.3 provide for a band of frequencies over which the attenuation increases from near 0 dB to Amin. This transition band extends from the pass-band edge ωp to the stopband edge ωs. The ratio ωs/ωp is usually used as a measure of the sharpness of the low-pass filter response and is called the selectivity factor. Finally, observe that for convenience the passband transmission is specified to be 0 dB. The final filter, however, can be given a passband gain, if desired, without changing its selectivity characteristics.
Vo jω ( ) = T jω ( ) Vi jω ( ) Figure 16.1 The filters studied in this chapter are linear circuits represented by the general two-port net-work shown. The filter transfer function Vi (s) Vo(s) Filter circuit T(s) T(s) ≡V o(s) Vi (s) ⁄ .
1258 Chapter 16 Filters and Tuned Amplifiers To summarize, the transmission of a low-pass filter is specified by four parameters: 1. The passband edge ωp 2. The maximum allowed variation in passband transmission Amax 3. The stopband edge ωs 4. The minimum required stopband attenuation Amin The more tightly one specifies a filter—that is, lower Amax, higher Amin, and/or a selectivity ratio closer to unity—the closer the response of the resulting filter will be to the ideal.
However, the resulting filter circuit must be of higher order and thus more complex and expensive.
In addition to specifying the magnitude of transmission, there are applications in which the phase response of the filter is also of interest. The filter-design problem, however, is con-siderably complicated when both magnitude and phase are specified.
Once the filter specifications have been decided upon, the next step in the design is to find a transfer function whose magnitude meets the specification. To meet specification, the magnitude-response curve must lie in the unshaded area in Fig. 16.3. The curve shown in the figure is for a filter that just meets specifications. Observe that for this particular filter, the magnitude response ripples throughout the passband, and the ripple peaks are all equal.
Since the peak ripple is equal to Amax it is usual to refer to Amax as the passband ripple and to (a) (b) (c) (d) Figure 16.2 Ideal transmission characteristics of the four major filter types: (a) low-pass (LP), (b) high-pass (HP), (c) bandpass (BP), and (d) bandstop (BS).
ωs ωp ⁄ 16.1 Filter Transmission, Types, and Specification 1259 ωp as the ripple bandwidth. The particular filter response shows ripples also in the stop-band, again with the ripple peaks all equal and of such a value that the minimum stopband attenuation achieved is equal to the specified value, Amin. Thus this particular response is said to be equiripple in both the passband and the stopband.
The process of obtaining a transfer function that meets given specifications is known as filter approximation. Filter approximation is usually performed using computer programs (Snelgrove, 1982; Ouslis and Sedra, 1995) or filter design tables (Zverev, 1967). In simpler cases, filter approximation can be performed using closed-form expressions, as will be seen in Section 16.3.
Finally, Fig. 16.4 shows transmission specifications for a bandpass filter and the response of a filter that meets these specifications. For this example we have chosen an approximation function that does not ripple in the passband; rather, the transmission decreases monotoni-cally on both sides of the center frequency, attaining the maximum allowable deviation at the two edges of the passband. Figure 16.3 Specification of the transmission characteristics of a low-pass filter. The magnitude response of a filter that just meets specifications is also shown.
Amin Passband Stopband 0 0 p s 2 Amax 1 Transi-tion band T , dB EXERCISES 16.1 Find approximate values of attenuation (in dB) corresponding to filter transmissions of 1, 0.99, 0.9, 0.8, 0.7, 0.5, 0.1, 0.
Ans. 0, 0.1, 1, 2, 3, 6, 20, ∞ (dB) 16.2 If the magnitude of passband transmission is to remain constant to within ±5%, and if the stopband transmission is to be no greater than 1% of the passband transmission, find Amax and Amin.
Ans. 0.9 dB; 40 dB 1260 Chapter 16 Filters and Tuned Amplifiers 16.2 The Filter Transfer Function The filter transfer function T(s) can be written as the ratio of two polynomials as (16.6) The degree of the denominator, N, is the filter order. For the filter circuit to be stable, the degree of the numerator must be less than or equal to that of the denominator; M ≤ N. The numerator and denominator coefficients, a0, a1, . . . , aM and b0, b1, . . . , bN−1, are real num-bers. The polynomials in the numerator and denominator can be factored, and T(s) can be expressed in the form (16.7) The numerator roots, z1, z2, . . . , zM, are the transfer function zeros, or transmission zeros; and the denominator roots, p1, p2, . . . , pN, are the transfer function poles, or the natural modes.1 Each transmission zero or pole can be either a real or a complex number. Complex zeros and poles, however, must occur in conjugate pairs. Thus, if −1 + j2 happens to be a zero, then −1 − j2 also must be a zero.
Since in the filter stopband the transmission is required to be zero or small, the filter transmission zeros are usually placed on the jω axis at stopband frequencies. This indeed is the case for the filter whose transmission function is sketched in Fig. 16.3. This particular fil-ter can be seen to have infinite attenuation (zero transmission) at two stopband frequencies: ωl1 and ωl2. The filter then must have transmission zeros at s = +jωl1 and s = +jωl2.
Figure 16.4 Transmission specifications for a bandpass filter. The magnitude response of a filter that just meets specifications is also shown. Note that this particular filter has a monotonically decreasing transmis-sion in the passband on both sides of the peak frequency.
1 Throughout this chapter, we use the names poles and natural modes interchangeably.
Lower stopband Upper stopband 0 s s2 v Amax Passband p2 1 Amin T , dB 2 1 p 1 T s ( ) = aMsM aM–1sM–1 . . . a0 + + + sN bN–1sN–1 . . . b0 + + + ---------------------------------------------------------------------T s ( ) = aM s z1 – ( ) s z2 – ( ) . . . s zM – ( ) s p1 – ( ) s p2 – ( ) . . . s pN – ( ) -------------------------------------------------------------------------16.2 The Filter Transfer Function 1261 However, since complex zeros occur in conjugate pairs, there must also be transmission zeros at s = −jωl1 and s = −jωl2. Thus the numerator polynomial of this filter will have the factors (s + jωl1)(s − jωl1)(s + jωl2)(s − jωl2), which can be written as .
For s = jω (physical frequencies) the numerator becomes , which indeed is zero at ω = ωl1 and ω = ωl2.
Continuing with the example in Fig. 16.3, we observe that the transmission decreases toward −∞ as ω approaches ∞. Thus the filter must have one or more transmission zeros at s = ∞. In general, the number of transmission zeros at s = ∞ is the difference between the degree of the numerator polynomial, M, and the degree of the denominator polynomial, N, of the transfer function in Eq. (16.6). This is because as s approaches ∞, T(s) approaches and thus is said to have N − M zeros at s = ∞.
For a filter circuit to be stable, all its poles must lie in the left half of the s plane, and thus p1, p2, . . . , pN must all have negative real parts. Figure 16.5 shows typical pole and zero locations for the low-pass filter whose transmission function is depicted in Fig. 16.3. We have assumed that this filter is of fifth order (N = 5). It has two pairs of complex-conjugate poles and one real-axis pole, for a total of five poles. All the poles lie in the vicinity of the passband, which is what gives the filter its high transmission at passband frequencies. The five transmission zeros are at s = ±jωl1, s = ±jωl2, and s = ∞. Thus, the transfer function for this filter is of the form (16.8) As another example, consider the bandpass filter whose magnitude response is shown in Fig. 16.4. This filter has transmission zeros at s = ± jωl1 and s = ± jωl2. It also has one or more zeros at s = 0 and one or more zeros at s = ∞ (because the transmission decreases toward 0 as ω approaches 0 and ∞). Assuming that only one zero exists at each of s = 0 and s = ∞, the fil-ter must be of sixth order, and its transfer function takes the form (16.9) A typical pole–zero plot for such a filter is shown in Fig. 16.6.
As a third and final example, consider the low-pass filter whose transmission function is depicted in Fig. 16.7(a). We observe that in this case there are no finite values of ω at which O O O O O O 0 poles zeros j 2 p 1 2 1 p s plane x x x x x x Figure 16.5 Pole–zero pattern for the low-pass filter whose transmission is sketched in Fig. 16.3. This is a fifth-order filter (N = 5).
s2 ωl1 2 + ( ) s2 ωl2 2 + ( ) −ω2 ωl1 2 + ( ) −ω2 ωl2 2 + ( ) aM sN M – ⁄ T s ( ) = a4 s2 ωl1 2 + ( ) s2 ωl2 2 + ( ) s5 b4s4 b3s3 b2s2 b1s b0 + + + + + --------------------------------------------------------------------------------T s ( ) a5s s2 ωl1 2 + ( ) s2 ωl2 2 + ( ) s6 b5s5 . . . b0 + + + --------------------------------------------------------= 1262 Chapter 16 Filters and Tuned Amplifiers the attenuation is infinite (zero transmission). Thus it is possible that all the transmission zeros of this filter are at s = ∞. If this is the case, the filter transfer function takes the form (16.10) Figure 16.6 Pole–zero pattern for the band-pass filter whose transmission function is shown in Fig. 16.4. This is a sixth-order filter (N = 6).
Figure 16.7 (a) Transmission characteristics of a fifth-order low-pass filter having all transmission zeros at infinity. (b) Pole–zero pattern for the filter in (a).
(a) (b) T s ( ) = a0 sN bN−1sN−1 . . . b0 + + + ------------------------------------------------------------16.3 Butterworth and Chebyshev Filters 1263 Such a filter is known as an all-pole filter. Typical pole–zero locations for a fifth-order all-pole low-pass filter are shown in Fig. 16.7(b).
Almost all the filters studied in this chapter have all their transmission zeros on the jω axis, in the filter stopband(s), including2ω = 0 and ω = ∞. Also, to obtain high selectivity, all the natural modes will be complex conjugate (except for the case of odd-order filters, where one natural mode must be on the real axis). Finally we note that the more selective the required filter response is, the higher its order must be, and the closer its natural modes are to the jω axis.
16.3 Butterworth and Chebyshev Filters In this section, we present two functions that are frequently used in approximating the transmis-sion characteristics of low-pass filters. Closed-form expressions are available for the parameters of these functions, and thus one can use them in filter design without the need for computers or filter-design tables. Their utility, however, is limited to relatively simple applications.
Although in this section we discuss the design of low-pass filters only, the approxima-tion functions presented can be applied to the design of other filter types through the use of frequency transformations (see Sedra and Brackett, 1978).
16.3.1 The Butterworth Filter Figure 16.8 shows a sketch of the magnitude response of a Butterworth3 filter. This filter exhibits a monotonically decreasing transmission with all the transmission zeros at ω = ∞, making it an all-pole filter. The magnitude function for an Nth-order Butterworth filter with a passband edge ωp is given by 2 Obviously, a low-pass filter should not have a transmission zero at ω = 0, and, similarly, a high-pass filter should not have a transmission zero at ω = ∞.
EXERCISES 16.3 A second-order filter has its poles at The transmission is zero at ω = 2 rad/s and is unity at dc (ω = 0). Find the transfer function.
Ans. 16.4 A fourth-order filter has zero transmission at ω = 0, ω = 2 rad/s, and ω = ∞. The natural modes are −0.1 ± j0.8 and −0.1 ± j1.2. Find T(s).
Ans. 16.5 Find the transfer function T(s) of a third-order all-pole low-pass filter whose poles are at a radial distance of 1 rad/s from the origin and whose complex poles are at 30° angles from the jω axis. The dc gain is unity. Show that . Find ω 3dB and the attenuation at ω = 3 rad/s.
Ans. T(s) = (s2 + s + 1); 1 rad/s; 28.6 dB s = −1 2 ⁄ ( ) j 3 2 ⁄ ( ).
± T s ( ) = 1 4 --- s2 4 + s2 s 1 + + ----------------------T s ( ) = a3s s2 4 + ( ) s2 0.2s 0.65 + + ( ) s2 0.2s 1.45 + + ( ) --------------------------------------------------------------------------------------T jω ( ) = 1 1 ω6 + ⁄ 1 s 1 + ( ) ⁄ 3 The Butterworth filter approximation is named after S. Butterworth, a British engineer who in 1930 was among the first to employ it.
1264 Chapter 16 Filters and Tuned Amplifiers (16.11) At ω = ωp, (16.12) Thus, the parameter determines the maximum variation in passband transmission, Amax, according to (16.13) Conversely, given Amax, the value of can be determined from (16.14) Observe that in the Butterworth response the maximum deviation in passband transmission (from the ideal value of unity) occurs at the passband edge only. It can be shown that the first 2N − 1 derivatives of relative to ω are zero at ω = 0 [see Van Valkenburg (1980)]. This property makes the Butterworth response very flat near ω = 0 and gives the response the name maximally flat response. The degree of passband flatness increases as the order N is increased, as can be seen from Fig. 16.9. This figure indicates also that, as should be expected, as the order N is increased the filter response approaches the ideal brick-wall type of response. At the edge of the stopband, ω = ωs, the attenuation of the Butterworth filter can be obtained by substituting ω = ωs in Eq. (16.11). The result is given by (16.15) Figure 16.8 The magnitude response of a Butterworth filter.
p 1 1 1 2 T 0 T jω ( ) = 1 1 2 ω ωp ------⎝ ⎠ ⎛ ⎞2N + ------------------------------------T jωp ( ) = 1 1 2 + ------------------Amax = 20 1 2 + log = 10 Amax 10 ⁄ −1 T A ωs ( ) 20 – 1 1 2 + ωs ωp ⁄ ( )2N ⁄ [ ] log = 10 1 2 + ωs ωp ⁄ ( )2N [ ] log = 16.3 Butterworth and Chebyshev Filters 1265 This equation can be used to determine the filter order required, which is the lowest integer value of N that yields A(ωs) ≥ Amin.
The natural modes of an Nth-order Butterworth filter can be determined from the graph-ical construction shown in Fig. 16.10(a). Observe that the natural modes lie on a circle of radius and are spaced by equal angles of with the first mode at an angle from the +jω axis. Since the natural modes all have equal radial distance from the origin, they all have the same frequency . Figure 16.10(b), (c), and (d) shows the natural modes of Butterworth filters of order N = 2, 3, and 4, respectively.
Once the N natural modes p1, p2, . . . , pN have been found, the transfer function can be written as (16.16) where K is a constant equal to the required dc gain of the filter.
To summarize, to find a Butterworth transfer function that meets transmission specifica-tions of the form in Fig. 16.3 we perform the following procedure: 1. Determine from Eq. (16.14). 2. Use Eq. (16.15) to determine the required filter order as the lowest integer value of N that results in A(ωs) ≥ Amin.
3. Use Fig. 16.10(a) to determine the N natural modes.
4. Use Eq. (16.16) to determine T(s). Figure 16.9 Magnitude response for Butterworth filters of various order with = 1. Note that as the order increases, the response approaches the ideal brick-wall type of transmission.
ωp(1 ⁄ )1 N ⁄ π N, ⁄ π 2N ⁄ ω0 = ωp (1 ⁄ )1 N ⁄ T s ( ) Kω0 N s p1 – ( ) s p2 – ( ) . . . s pN – ( ) -------------------------------------------------------------------= 1266 Chapter 16 Filters and Tuned Amplifiers Figure 16.10 Graphical construction for determining the poles of a Butterworth filter of order N. All the poles lie in the left half of the s plane on a circle of radius ω0 = ωp(1/)1/N, where is the passband deviation parameter ( ): (a) the general case; (b) N = 2; (c) N = 3; (d) N = 4.
Example 16.1 Find the Butterworth transfer function that meets the following low-pass filter specifications: fp = 10 kHz, Amax = 1 dB, fs = 15 kHz, Amin = 25 dB, dc gain = 1.
Solution Substituting Amax = 1 dB into Eq. (16.14) yields = 0.5088. Equation (16.15) is then used to determine the filter order by trying various values for N. We find that N = 8 yields A(ωs) = 22.3 dB and N = 9 gives 25.8 dB. We thus select N = 9. N 2N N p1 p2 0 j p3 1 1 N p s plane (a) 0 j p2 N 2 45 p1 45 s plane 1 1 2 p (b) 0 j p2 N 3 60 p1 60 p3 s plane 1 1 3 p (c) 0 j p4 s plane N 4 45 p1 45 22.5 45 22.5 p2 p3 1 1 4 p (d) = 10Amax 10 ⁄ 1 – 16.3 Butterworth and Chebyshev Filters 1267 16.3.2 The Chebyshev Filter Figure 16.12 shows representative transmission functions for Chebyshev4 filters of even and odd orders. The Chebyshev filter exhibits an equiripple response in the passband and a monotonically decreasing transmission in the stopband. While the odd-order filter has , the even-order filter exhibits its maximum magnitude deviation at ω = 0. In both Figure 16.11 Poles of the ninth-order Butterworth filter of Example 16.1.
Figure 16.11 shows the graphical construction for determining the poles. The poles all have the same frequency = 2π × 10 × 103 = 6.773 × 104 rad/s. The first pole p1 is given by Combining p1 with its complex conjugate p9 yields the factor in the denominator of the transfer function. The same can be done for the other complex poles, and the complete transfer function is obtained using Eq. (16.16), (16.17) ω0 = ωp (1 ⁄ )1 N ⁄ 1 0.5088 ⁄ ( )1 9 ⁄ p1 = ω0 − 80° cos j 80° sin + ( ) ω0 −0.1736 j0.9848 + ( ) = s2 s0.3472ω0 ω0 2 + + ( ) T s ( ) = ω0 9 s ω0 + ( ) s2 s1.8794ω0 ω0 2 + + ( ) s2 s1.5321ω0 ω0 2 + + ( ) --------------------------------------------------------------------------------------------------------------------------------- 1 s2 sω0 ω0 2 + + ( ) s2 s0.3472ω0 ω0 2 + + ( ) --------------------------------------------------------------------------------------------× 4 Named after the Russian mathematician P. L. Chebyshev, who in 1899 used these functions in studying the construction of steam engines.
T 0 ( ) =1 1268 Chapter 16 Filters and Tuned Amplifiers cases the total number of passband maxima and minima equals the order of the filter, N. All the transmission zeros of the Chebyshev filter are at ω = ∞, making it an all-pole filter.
The magnitude of the transfer function of an Nth-order Chebyshev filter with a passband edge (ripple bandwidth) ωp is given by (16.18) and (16.19) At the passband edge, ω = ωp, the magnitude function is given by Thus, the parameter determines the passband ripple according to (16.20) Conversely, given Amax, the value of is determined from (16.21) The attenuation achieved by the Chebyshev filter at the stopband edge (ω = ωs) is found using Eq. (16.19) as (16.22) Figure 16.12 Sketches of the transmission characteristics of representative (a) even-order and (b) odd-order Chebyshev filters.
1 2 1 1 0 N 4 p T (a) 1 0 N 5 T p 1 2 1 (b) T jω ( ) = 1 1 2cos2 Ncos 1 – ω ωp ⁄ ( ) [ ] + -----------------------------------------------------------------------for ω ωp ≤ T jω ( ) = 1 1 2cosh2 Ncosh 1 – ω ωp ⁄ ( ) [ ] + -----------------------------------------------------------------------------for ω ωp ≥ T jωp ( ) 1 1 2 + ------------------= Amax = 10 1 2 + ( ) log 10 Amax 10 ⁄ −1 = A ωs ( ) =10 1 2cosh2 Ncosh 1 – ωs ωp ⁄ ( ) ( ) + [ ] log 16.3 Butterworth and Chebyshev Filters 1269 With the aid of a calculator, this equation can be used to determine the order N required to obtain a specified Amin by finding the lowest integer value of N that yields A(ωs) ≥ Amin. As in the case of the Butterworth filter, increasing the order N of the Chebyshev filter causes its magnitude function to approach the ideal brick-wall low-pass response.
The poles of the Chebyshev filter are given by (16.23) Finally, the transfer function of the Chebyshev filter can be written as (16.24) where K is the dc gain that the filter is required to have.
To summarize, given low-pass transmission specifications of the type shown in Fig. 16.3, the transfer function of a Chebyshev filter that meets these specifications can be found as fol-lows: 1. Determine from Eq. (16.21).
2. Use Eq. (16.22) to determine the order required.
3. Determine the poles using Eq. (16.23).
4. Determine the transfer function using Eq. (16.24).
The Chebyshev filter provides a more efficient approximation than the Butterworth fil-ter. Thus, for the same order and the same Amax, the Chebyshev filter provides greater stop-band attenuation than the Butterworth filter. Alternatively, to meet identical specifications, one requires a lower order for the Chebyshev than for the Butterworth filter. This point will be illustrated by the following example.
pk ω – p 2k 1 – N ---------------π 2 ---⎝ ⎠ ⎛ ⎞ sin 1 N ----sinh 1 – 1 ---⎝ ⎠ ⎛ ⎞ sinh = jω + p 2k 1 – N ---------------π 2 ---⎝ ⎠ ⎛ ⎞ cos cosh 1 N ----sinh 1 – 1 ---⎝ ⎠ ⎛ ⎞ k = 1 2 . . . , N , , T s ( ) = Kωp N 2N−1 s p1 – ( ) s p2 – ( ) . . . s pN – ( ) ------------------------------------------------------------------------------------Example 16.2 Find the Chebyshev transfer function that meets the same low-pass filter specifications given in Example 16.1: namely, fp = 10 kHz, Amax = 1 dB, fs = 15 kHz, Amin = 25 dB, dc gain = 1.
Solution Substituting Amax = 1 dB into Eq. (16.21) yields = 0.5088. By trying various values for N in Eq. (16.22) we find that N = 4 yields A(ωs) = 21.6 dB and N = 5 provides 29.9 dB. We thus select N = 5. Recall that we required a ninth-order Butterworth filter to meet the same specifications in Example 16.1.
The poles are obtained by substituting in Eq. (16.23) as p1 p5 ωp −0.0895 j0.9901 ± ( ) = , p2 p4 ωp −0.2342 j0.6119 ± ( ) = , 1270 Chapter 16 Filters and Tuned Amplifiers 16.4 First-Order and Second-Order Filter Functions In this section, we shall study the simplest filter transfer functions, those of first and second order. These functions are useful in their own right in the design of simple filters. First- and second-order filters can also be cascaded to realize a high-order filter. Cascade design is in fact one of the most popular methods for the design of active filters (those utilizing op amps and RC circuits). Because the filter poles occur in complex-conjugate pairs, a high-order transfer function T(s) is factored into the product of second-order functions. If T(s) is odd, Example 16.2 continued The transfer function is obtained by substituting these values in Eq. (16.24) as (16.25) where ωp = 2π × 104 rad/s.
EXERCISES D16.6 Determine the order N of a Butterworth filter for which Amax = 1 dB, , and Amin = 30 dB. What is the actual value of minimum stopband attenuation realized? If Amin is to be exactly 30 dB, to what value can Amax be reduced?
Ans. N = 11; Amin = 32.87 dB; 0.54 dB 16.7 Find the natural modes and the transfer function of a Butterworth filter with ωp = 1 rad/s, Amax = 3 dB ( 1), and N = 3.
Ans. −0.5 and −1; T(s) = 16.8 Observe that Eq. (16.18) can be used to find the frequencies in the passband at which is at its peaks and at its valleys. (The peaks are reached when the cos2[ ] term is zero, and the valleys correspond to the cos2[ ] term equal to unity.) Find these frequencies for a fifth-order filter.
Ans. Peaks at ω = 0, 0.59ωp, and 0.95ωp; the valleys at ω = 0.31ωp and 0.81ωp D16.9 Find the attenuation provided at ω = 2ωp by a seventh-order Chebyshev filter with a 0.5-dB pass-band ripple. If the passband ripple is allowed to increase to 1 dB, by how much does the stopband attenuation increase?
Ans. 64.9 dB; 3.3 dB D16.10 It is required to design a low-pass filter having fp = 1 kHz, Amax = 1 dB, fs = 1.5 kHz, Amin = 50 dB. (a) Find the required order of a Chebyshev filter. What is the excess stopband attenua-tion obtained? (b) Repeat for a Butterworth filter.
Ans. (a) N = 8, 5 dB; (b) N = 16, 0.5 dB p5 ωp 0.2895 – ( ) = T s ( ) = ωp 5 8.1408 s 0.2895ωp + ( ) s2 s0.4684ωp 0.4293ωp 2 + + ( ) -----------------------------------------------------------------------------------------------------------------------------1 s2 s0.1789ωp 0.9883ωp 2 + + ----------------------------------------------------------------------× ωs ωp ⁄ =1.5 j 3 2 ⁄ ± 1 s 1 + ( ) s2 s 1 + + ( ) ⁄ T 16.4 First-Order and Second-Order Filter Functions 1271 there will also be a first-order function in the factorization. Each of the second-order func-tions [and the first-order function when T(s) is odd] is then realized using one of the op amp– RC circuits that will be studied in this chapter, and the resulting blocks are placed in cascade.
If the output of each block is taken at the output terminal of an op amp where the impedance level is low (ideally zero), cascading does not change the transfer functions of the individual blocks. Thus the overall transfer function of the cascade is simply the product of the transfer functions of the individual blocks, which is the original T(s).
16.4.1 First-Order Filters The general first-order transfer function is given by (16.26) This bilinear transfer function characterizes a first-order filter with a natural mode at s = −ω0, a transmission zero at , and a high-frequency gain that approaches a1. The numer-ator coefficients, a0 and a1, determine the type of filter (e.g., low pass, high pass, etc.). Some special cases together with passive (RC) and active (op amp–RC) realizations are shown in Fig. 16.13. Note that the active realizations provide considerably more versatility than their passive counterparts; in many cases the gain can be set to a desired value, and some transfer function parameters can be adjusted without affecting others. The output impedance of the active circuit is also very low, making cascading easily possible. The op amp, however, limits the high-frequency operation of the active circuits.
An important special case of the first-order filter function is the all-pass filter shown in Fig. 16.14. Here, the transmission zero and the natural mode are symmetrically located rela-tive to the jω axis. (They are said to display mirror-image symmetry with respect to the jω axis.) Observe that although the transmission of the all-pass filter is (ideally) constant at all frequencies, its phase shows frequency selectivity. All-pass filters are used as phase shifters and in systems that require phase shaping (e.g., in the design of circuits called delay equalizers, which cause the overall time delay of a transmission system to be constant with frequency).
16.4.2 Second-Order Filter Functions The general second-order (or biquadratic) filter transfer function is usually expressed in the standard form T s ( ) a1s a0 + s ω0 + -------------------= s a0 a1 ⁄ – = EXERCISES D16.11 Using R1 = 10 kΩ, design the op amp–RC circuit of Fig. 16.13(b) to realize a high-pass filter with a corner frequency of 104 rad/s and a high-frequency gain of 10.
Ans. R2 = 100 kΩ; C = 0.01 μF D16.12 Design the op amp–RC circuit of Fig. 16.14 to realize an all-pass filter with a 90 phase shift at 103 rad/s. Select suitable component values.
Ans. Possible choices: R = R1 = R2 = 10 kΩ; C = 0.1 μF 1272 Filter Type and T(s) s-Plane Singularities Bode Plot for |T| Passive Realization Op Amp–RC Realization (a) Low pass (LP) (b) High pass (HP) (c) General Figure 16.13 First-order filters.
T(s) = a0 s ω0 + ---------------0 0 j O at 0 (log) 20 log 0 20 dB decade T , dB a0 0 R C Vi Vo CR DC gain 1 1 0 R1 R2 C CR2 1 0 DC gain R2 R1 Vo Vi T(s) = a1s s ω0 + ---------------O0 j 0 0 (log) 0 20 dB decade T , dB a1 20 log R C Vi Vo CR High-frequency gain 1 1 0 R1 R2 C Vo Vi High-frequency gain R2 R1 CR1 1 0 T(s) = a1s a + 0 s ω0 + --------------------O 0 0 j a0 a1 a0 0 0 (log) 20 log 0 20 dB decade T , dB a0 a1 a1 20 log R2 C1 Vi Vo DC gain 1 0 R2 R1 R2 C2 R1 C1 C1 C2 (C1 C2) (R1 R2) HF gain C1R1 a1 a0 C1 C2 1 0 DC gain C1 C2 Vo Vi C2R2 HF gain a1 a0 R2 R1 R2 R1 C1R1 1273 T(s) Singularities |T| and φ Passive Realization Op Amp–RC Realization All pass (AP) Figure 16.14 First-order all-pass filter.
T(s) = −a1 s ω0 – s ω0 + ---------------a1 0 > O j 0 0 0 0 20 log a1 (log) T, dB 0 0 180 90 R1 Vi C R1 R Vo CR 1/0 Flat gain (a1) 0.5 Vi R C R1 Vo R1 CR 1/0 Flat gain (a1) 1 1274 Chapter 16 Filters and Tuned Amplifiers (16.27) where ω0 and Q determine the natural modes (poles) according to (16.28) We are usually interested in the case of complex-conjugate natural modes, obtained for Q > 0.5.
Figure 16.15 shows the location of the pair of complex-conjugate poles in the s plane. Observe that the radial distance of the natural modes (from the origin) is equal to ω0, which is known as the pole frequency. The parameter Q determines the distance of the poles from the jω axis: the higher the value of Q, the closer the poles are to the jω axis, and the more selective the filter response becomes. An infinite value for Q locates the poles on the jω axis and can yield sustained oscillations in the circuit realization. A negative value of Q implies that the poles are in the right half of the s plane, which certainly produces oscillations. The parameter Q is called the pole quality factor, or simply, pole Q.
The transmission zeros of the second-order filter are determined by the numerator co-efficients, a0, a1, and a2. It follows that the numerator coefficients determine the type of second-order filter function (i.e., LP, HP, etc.). Seven special cases of interest are illustrated in Fig. 16.16. For each case we give the transfer function, the s-plane locations of the trans-fer function singularities, and the magnitude response. Circuit realizations for the various second-order filter functions will be given in subsequent sections.
All seven special second-order filters have a pair of complex-conjugate natural modes characterized by a frequency ω0 and a quality factor Q.
In the low-pass (LP) case, shown in Fig. 16.16(a), the two transmission zeros are at s = ∞. The magnitude response can exhibit a peak with the details indicated. It can be shown that the peak occurs only for . The response obtained for is the Butterworth, or maximally flat, response.
The high-pass (HP) function shown in Fig. 16.16(b) has both transmission zeros at s = 0 (dc). The magnitude response shows a peak for , with the details of the response as indicated. Observe the duality between the LP and HP responses.
Next consider the bandpass (BP) filter function shown in Fig. 16.16(c). Here, one trans-mission zero is at s = 0 (dc), and the other is at s = ∞. The magnitude response peaks at ω = ω0. Thus the center frequency of the bandpass filter is equal to the pole frequency ω0. The selectivity of the second-order bandpass filter is usually measured by its 3-dB bandwidth. This Figure 16.15 Definition of the parameters ω0 and Q of a pair of complex-conjugate poles.
T s ( ) = a2s2 a1s a0 + + s2 ω0 Q ⁄ ( )s ω0 2 + + ----------------------------------------------p1 p2 , = ω0 2Q -------jω0 1 1 4Q2 ⁄ ( ) – ± – Q 1 2 ⁄ > Q = 1 2 ⁄ Q 1 2 ⁄ > 16.4 First-Order and Second-Order Filter Functions 1275 is the difference between the two frequencies ω1 and ω2 at which the magnitude response is 3 dB below its maximum value (at ω0). It can be shown that (16.29) Thus, (16.30) Observe that as Q increases, the bandwidth decreases and the bandpass filter becomes more selective.
If the transmission zeros are located on the jω axis, at the complex-conjugate locations , then the magnitude response exhibits zero transmission at ω = ωn. Thus a notch in the magnitude response occurs at ω = ωn, and ωn is known as the notch frequency. Three cases of the second-order notch filter are possible: the regular notch, obtained when ωn = ω0 (Fig. 16.16d); the low-pass notch, obtained when ωn > ω0 (Fig. 16.16e); and the high-pass notch, obtained when ωn < ω0 (Fig. 16.16f). The reader is urged to verify the response details given in these figures (a rather tedious task, though!). Observe that in all notch cases, the transmission at dc and at s = ∞ is finite. This is so because there are no transmission zeros at either s = 0 or s = ∞.
The last special case of interest is the all-pass (AP) filter whose characteristics are illus-trated in Fig. 16.16(g). Here the two transmission zeros are in the right half of the s plane, at the mirror-image locations of the poles. (This is the case for all-pass functions of any order.) The magnitude response of the all-pass function is constant over all frequencies; the flat gain, as it is called, is in our case equal to . The frequency selectivity of the all-pass function is in its phase response.
ω1 ω2 , ω0 1 1 4Q2 ⁄ ( ) + ± ω0 2Q -------= BW ω2 ω1 – ≡ ω0 Q ⁄ = jωn ± a2 EXERCISES 16.13 For a maximally flat second-order low-pass filter , show that at ω = ω0 the magni-tude response is 3 dB below the value at dc.
16.14 Give the transfer function of a second-order bandpass filter with a center frequency of 105 rad/s, a center-frequency gain of 10, and a 3-dB bandwidth of 103 rad/s.
Ans. 16.15 (a) For the second-order notch function with ωn = ω0, show that for the attenuation to be greater than A dB over a frequency band BWa, the value of Q is given by (Hint: First, show that any two frequencies, ω1 and ω2, at which is the same, are related by .) (b) Use the result of (a) to show that the 3-dB bandwidth is as indicated in Fig. 16.16(d).
16.16 Consider a low-pass notch with ω0 = 1 rad/s, Q = 10, ωn = 1.2 rad/s, and a dc gain of unity. Find the frequency and magnitude of the transmission peak. Also find the high-frequency transmission.
Ans. 0.986 rad/s; 3.17; 0.69 (Q 1 2 ⁄ ) = T s ( ) 104s s2 103s 1010 + + --------------------------------------= Q ω0 BW a 10A 10 ⁄ 1 – ----------------------------------------≤ T ω1ω2 =ω0 2 ω0 Q, ⁄ 1276 Filter Type and T(s) s-Plane Singularities |T| (a) Low pass (LP) DC gain (b) High pass (HP) High-frequency gain = a2 (c) Bandpass (BP) Center-frequency gain Figure 16.16 Second-order filtering functions.
T(s) = a0 s2 s ω0 Q ------ω0 2 + + ---------------------------------= a0 ω0 2 ------j 0 2Q 0 0 OO at 0 0 T max a0 / 2 0 a0Q 1 4Q2 2 0 1 max 1 2Q2 0 1 T(s) = a2s2 s2 s ω0 Q ------ω0 2 + + ---------------------------------j 0 0 0 2Q 0 0 T max a2 1 a2Q 1 4Q2 max 0 1 1 2Q2 T(s) = a1s s2 s ω0 Q ------ω0 2 + + --------------------------------- = a1Q ω0 ----------O at j 0 0 2Q 0 0 2Q 0 2 T 0 b Tmax 0.707 Tmax (a1Q/ ( 0 /Q) 1, 2 0) 1 1 4Q2 2 (a1Q/ 0) 2 0 1 a 2 2 0 1 a b 0 1277 Filter Type and T(s) s-Plane Singularities |T| (d) Notch DC gain = High-frequency gain = a2 (e) Low-pass notch (LPN) DC gain High-frequency gain = a2 (f) High-pass notch (HPN) DC gain High-frequency gain = a2 Figure 16.16 (continued) T(s) = a2 s2 ω0 2 + s2 s ω0 Q ------ω0 2 + + ---------------------------------1 2 2 1 0 2 T(s) = a2 s2 ωn 2 + s2 s ω0 Q ------ω0 2 + + ---------------------------------ωn ω0 ≥ = a2 ωn 2 ω0 2 ------a T(s) = a2 s2 ωn 2 + s2 s ω0 Q ------ω0 2 + + ---------------------------------ωn ω0 ≤ = a2 ωn 2 ω0 2 ------1278 (g) All pass (AP) Flat gain = a2 Figure 16.16 (continued) T(s) = a2 s2 s – ω0 Q ------ω0 2 + s2 s ω0 Q ------ω0 2 + + ---------------------------------j 0 2Q 0 0 0 2Q 0 O O 0 T a2 0 0 2 16.5 The Second-Order LCR Resonator 1279 16.5 The Second-Order LCR Resonator In this section we shall study the second-order LCR resonator shown in Fig. 16.17(a). The use of this resonator to derive circuit realizations for the various second-order filter functions will be demonstrated. It will be shown in the next section that replacing the inductor L by a simulated inductance obtained using an op amp–RC circuit results in an op amp–RC resonator.
The latter forms the basis of an important class of active-RC filters to be studied in Section 16.6.
16.5.1 The Resonator Natural Modes The natural modes of the parallel resonance circuit of Fig. 16.17(a) can be determined by applying an excitation that does not change the natural structure of the circuit. Two possible ways of exciting the circuit are shown in Fig. 16.17(b) and (c). In Fig. 16.17(b) the resonator is excited with a current source I connected in parallel. Since, as far as the natural response of a circuit is concerned, an independent ideal current source is equivalent to an open circuit, the excitation of Fig. 16.17(b) does not alter the natural structure of the resonator. Thus the circuit in Fig. 16.17(b) can be used to determine the natural modes of the resonator by simply finding the poles of any response function. We can for instance take the voltage Vo across the resonator as the response and thus obtain the response function , where Z is the impedance of the parallel resonance circuit. It is obviously more convenient, however, to work in terms of the admittance Y; thus, (16.31) Equating the denominator to the standard form leads to (16.32) and (16.33) Vo I ⁄ Z = V o I -----1 Y ---1 1 sL ⁄ ( ) sC 1 R ⁄ ( ) + + ----------------------------------------------------= = s C ⁄ s2 s 1 CR ⁄ ( ) 1 LC ⁄ ( ) + + -----------------------------------------------------------= [s2 s ω0 Q ⁄ ( ) ω0 2] + + ω0 2 = 1 LC ⁄ ω0 Q ⁄ = 1 CR ⁄ Figure 16.17 (a) The second-order parallel LCR resonator. (b, c) Two ways of exciting the resonator of (a) without changing its natural structure: resonator poles are those poles of and .
y z C L R x (a) Vo I L R C (b) Vi x R C L Vo (c) Vo I ⁄ Vo Vi ⁄ 1280 Chapter 16 Filters and Tuned Amplifiers Thus, (16.34) (16.35) These expressions should be familiar to the reader from studies of parallel resonance circuits in introductory courses on circuit theory.
An alternative way of exciting the parallel LCR resonator for the purpose of determin-ing its natural modes is shown in Fig. 16.17(c). Here, node x of inductor L has been discon-nected from ground and connected to an ideal voltage source Vi. Now, since as far as the natural response of a circuit is concerned, an ideal independent voltage source is equivalent to a short circuit, the excitation of Fig. 16.17(c) does not alter the natural structure of the res-onator. Thus we can use the circuit in Fig. 16.17(c) to determine the natural modes of the res-onator. These are the poles of any response function. For instance, we can select Vo as the response variable and find the transfer function . The reader can easily verify that this will lead to the natural modes determined earlier.
In a design problem, we will be given ω0 and Q and will be asked to determine L, C, and R. Equations (16.34) and (16.35) are two equations in the three unknowns. The one available degree of freedom can be utilized to set the impedance level of the circuit to a value that results in practical component values.
16.5.2 Realization of Transmission Zeros Having selected the component values of the LCR resonator to realize a given pair of complex-conjugate natural modes, we now consider the use of the resonator to realize a desired filter type (e.g., LP, HP, etc.). Specifically, we wish to find out where to inject the input voltage signal Vi so that the transfer function is the desired one. Toward that end, note that in the resonator circuit in Fig. 16.17(a), any of the nodes labeled x, y, or z can be disconnected from ground and connected to Vi without altering the circuit’s natural modes. When this is done, the circuit takes the form of a voltage divider, as shown in Fig. 16.18(a). Thus the transfer function realized is (16.36) We observe that the transmission zeros are the values of s at which Z2(s) is zero, provided Z1(s) is not simultaneously zero, and the values of s at which Z1(s) is infinite, provided Z2(s) is not simultaneously infinite. This statement makes physical sense: The output will be zero either when Z2(s) behaves as a short circuit or when Z1(s) behaves as an open circuit. If there is a value of s at which both Z1 and Z2 are zero, then will be finite and no transmission zero is obtained. Similarly, if there is a value of s at which both Z1 and Z2 are infinite, then will be finite and no transmission zero is realized.
16.5.3 Realization of the Low-Pass Function Using the scheme just outlined, we see that to realize a low-pass function, node x is dis-connected from ground and connected to Vi, as shown in Fig. 16.18(b). The transmission zeros of this circuit will be at the value of s for which the series impedance becomes infinite (sL becomes infinite at s = ∞) and the value of s at which the shunt impedance becomes zero ( becomes zero at s = ∞). Thus this circuit has two transmission zeros ω0 = 1 LC ⁄ Q = ω0CR Vo Vi ⁄ Vo Vi ⁄ T s ( ) Vo s ( ) Vi s ( ) -------------Z2 s ( ) Z1 s ( ) Z2 s ( ) + --------------------------------= = V o Vi ⁄ V o Vi ⁄ 1 sC 1 R ⁄ ( ) + [ ] ⁄ 16.5 The Second-Order LCR Resonator 1281 Figure 16.18 Realization of various second-order filter functions using the LCR resonator of Fig. 16.17(b): (a) general structure, (b) LP, (c) HP, (d) BP, (e) notch at ω0, (f) general notch, (g) LPN , (h) LPN as , (i) HPN .
Z2 Vo Z1 Vi General structure (a) LP Vo R C Vi L x (b) HP Vo L R C Vi y (c) BP Vo L R C Vi z (d) x Vo Vi L R C y Notch at 0 (e) Vo R Vi C2 y L1 C1 L2 x General notch (f) LPN (n 0) Vo R Vi L C1 C2 y x (g) Vo Vi C2 C1 LPN as s (h) L2 HPN (n 0) Vo R Vi y C L1 x (i) (ωn ω0) ≥ s ∞ → (ωn ω0) < 1282 Chapter 16 Filters and Tuned Amplifiers at s = ∞, as an LP is supposed to. The transfer function can be written either by inspection or by using the voltage divider rule. Following the latter approach, we obtain (16.37) 16.5.4 Realization of the High-Pass Function To realize the second-order high-pass function, node y is disconnected from ground and con-nected to Vi, as shown in Fig. 16.18(c). Here the series capacitor introduces a transmission zero at s = 0 (dc), and the shunt inductor introduces another transmission zero at s = 0 (dc). Thus, by inspection, the transfer function may be written as (16.38) where ω0 and Q are the natural mode parameters given by Eqs. (16.34) and (16.35) and a2 is the high-frequency transmission. The value of a2 can be determined from the circuit by observing that as s approaches ∞, the capacitor approaches a short circuit and Vo approaches Vi, resulting in a2 = 1.
16.5.5 Realization of the Bandpass Function The bandpass function is realized by disconnecting node z from ground and connecting it to Vi, as shown in Fig. 16.18(d). Here the series impedance is resistive and thus does not introduce any transmission zeros. These are obtained as follows: One zero at s = 0 is realized by the shunt inductor, and one zero at s = ∞ is realized by the shunt capacitor. At the center frequency ω0, the parallel LC-tuned circuit exhibits an infinite impedance, and thus no current flows in the circuit. It follows that at ω = ω0, Vo = Vi. In other words, the center-frequency gain of the bandpass filter is unity. Its transfer function can be obtained as follows: (16.39) 16.5.6 Realization of the Notch Functions To obtain a pair of transmission zeros on the jω axis, we use a parallel resonance circuit in the series arm, as shown in Fig. 16.18(e). Observe that this circuit is obtained by discon-necting both nodes x and y from ground and connecting them together to Vi. The impedance of the LC circuit becomes infinite at , thus causing zero transmission at this frequency. The shunt impedance is resistive and thus does not introduce transmission zeros.
It follows that the circuit in Fig. 16.18(e) will realize the notch transfer function (16.40) T s ( ) V o V i -----≡ Z2 Z1 Z2 + -----------------Y1 Y1 Y2 + -----------------1 sL ⁄ 1 sL ⁄ ( ) sC 1 R ⁄ ( ) + + ----------------------------------------------------= = = 1 LC ⁄ s2 s 1 CR ⁄ ( ) 1 LC ⁄ ( ) + + -----------------------------------------------------------= T s ( ) V o Vi -----≡ a2 s2 s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------= T s ( ) YR YR YL YC + + -------------------------------1 R ⁄ 1 R ⁄ ( ) 1 sL ⁄ ( ) sC + + ----------------------------------------------------= = s 1 CR ⁄ ( ) s2 s 1 CR ⁄ ( ) 1 LC ⁄ ( ) + + -----------------------------------------------------------= ω =ω0 = 1 LC ⁄ T s ( ) a2 s2 ω0 2 + s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------= 16.5 The Second-Order LCR Resonator 1283 The value of the high-frequency gain a2 can be found from the circuit to be unity.
To obtain a notch-filter realization in which the notch frequency ωn is arbitrarily placed relative to ω0, we adopt a variation on the scheme above. We still use a parallel LC circuit in the series branch, as shown in Fig. 16.18(f) where L1 and C1 are selected so that (16.41) Thus the L1C1 tank circuit will introduce a pair of transmission zeros at ±jωn, provided the L2C2 tank is not resonant at ωn. Apart from this restriction, the values of L2 and C2 must be selected to ensure that the natural modes have not been altered; thus, (16.42) (16.43) In other words, when Vi is replaced by a short circuit, the circuit should reduce to the original LCR resonator. Another way of thinking about the circuit of Fig. 16.18(f) is that it is obtained from the original LCR resonator by lifting part of L and part of C off ground and connecting them to Vi.
It should be noted that in the circuit of Fig. 16.18(f), L2 does not introduce a zero at s = 0 because at s = 0, the L1C1 circuit also has a zero. In fact, at s = 0 the circuit reduces to an inductive voltage divider with the dc transmission being . Similar comments can be made about C2 and the fact that it does not introduce a zero at s = ∞.
The LPN and HPN filter realizations are special cases of the general notch circuit of Fig. 16.18(f ). Specifically, for the LPN, and thus This condition can be satisfied with L2 eliminated (i.e., L2 = ∞ and L1 = L), resulting in the LPN circuit in Fig. 16.18(g). The transfer function can be written by inspection as (16.44) where and a2 is the high-frequency gain. From the circuit we see that as s → ∞, the circuit reduces to that in Fig. 16.18(h), for which Thus, (16.45) To obtain an HPN realization we start with the circuit of Fig. 16.18(f) and use the fact that to obtain L1C1 1 ωn 2 ⁄ = C1 C2 + = C L1 L2 || = L L2 L1 L2 + ( ) ⁄ ωn ω0 > L1C1 (L1 L2 || ) C1 C2 + ( ) < T s ( ) V o Vi -----≡ a2 s2 ωn 2 + s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------= ωn 2 1 LC1, ⁄ = ω0 2 1 L C1 C2 + ( ) ⁄ ω0 Q ⁄ , 1 CR, ⁄ = = V o V i -----C1 C1 C2 + ------------------= a2 C1 C1 C2 + ------------------= ωn ω0 < 1284 Chapter 16 Filters and Tuned Amplifiers which can be satisfied while selecting C2 = 0 (i.e., C1 = C). Thus we obtain the reduced circuit shown in Fig. 16.18(i). Observe that as s → ∞, Vo approaches Vi and thus the high-frequency gain is unity. Thus, the transfer function can be expressed as (16.46) 16.5.7 Realization of the All-Pass Function The all-pass transfer function (16.47) can be written as (16.48) The second term on the right-hand side is a bandpass function with a center-frequency gain of 2. We already have a bandpass circuit (Fig. 16.18d), but with a center-frequency gain of unity. We shall therefore attempt an all-pass realization with a flat gain of 0.5, that is, This function can be realized using a voltage divider with a transmission ratio of 0.5 together with the bandpass circuit of Fig. 16.18(d). To effect the subtraction, the output of the all-pass circuit is taken between the output terminal of the voltage divider and that of the bandpass filter, as shown in Fig. 16.19. Unfortunately this circuit has the disadvantage of lacking a common ground terminal between the input and the output. An op amp–RC realization of the all-pass function will be presented in the next section. L1C1 (L1 L2 || ) C1 C2 + ( ) > T s ( ) V o V i -----≡ s2 1 L1C ⁄ ( ) + s2 s 1 CR ⁄ ( ) [1 (L1 L2) || ⁄ C] + + -----------------------------------------------------------------------------= T s ( ) s2 s ω0 Q ⁄ ( ) ω0 2 + – s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------= T s ( ) 1 s2 ω0 Q ⁄ ( ) s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------– = T s ( ) 0.5 s ω0 Q ⁄ ( ) s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------– = EXERCISES 16.17 Use the circuit of Fig. 16.18(b) to realize a second-order low-pass function of the maximally flat type with a 3-dB frequency of 100 kHz. Ans. Selecting R = 1 kΩ, we obtain C = 1125 pF and L = 2.25 mH.
16.18 Use the circuit of Fig. 16.18(e) to design a notch filter to eliminate a bothersome power-supply hum at a 60-Hz frequency. The filter is to have a 3-dB bandwidth of 10 Hz (i.e., the attenuation is greater than 3 dB over a 10-Hz band around the 60-Hz center frequency; see Exercise 16.15 and Fig. 16.16d). Use R = 10 kΩ.
Ans. C = 1.6 μF and L = 4.42 H (Note the large inductor required. This is the reason passive filters are not practical in low-frequency applications.) 16.6 Second-Order Active Filters Based on Inductor Replacement 1285 16.6 Second-Order Active Filters Based on Inductor Replacement In this section, we study a family of op amp–RC circuits that realize the various second-order filter functions. The circuits are based on an op amp–RC resonator obtained by replacing the inductor L in the LCR resonator with an op amp–RC circuit that has an inductive input impedance.
16.6.1 The Antoniou Inductance-Simulation Circuit Over the years, many op amp–RC circuits have been proposed for simulating the operation of an inductor. Of these, one circuit invented by A. Antoniou5 (see Antoniou, 1969) has proved to be the “best.” By “best” we mean that the operation of the circuit is very tolerant of the nonideal properties of the op amps, in particular their finite gain and bandwidth.
Figure 16.20(a) shows the Antoniou inductance-simulation circuit. If the circuit is fed at its input (node 1) with a voltage source V1 and the input current is denoted I1, then for ideal op amps the input impedance can be shown to be (16.49) which is that of an inductance L given by (16.50) Figure 16.20(b) shows the analysis of the circuit assuming that the op amps are ideal and thus that a virtual short circuit appears between the two input terminals of each op amp, and assuming also that the input currents of the op amps are zero. The analysis begins at node 1, which is assumed to be fed by a voltage source V1, and proceeds step by step, with the order of the steps indicated by the circled numbers. The result of the analysis is the expression shown for the input current I1 from which Zin is found.
The design of this circuit is usually based on selecting R1 = R2 = R3 = R5 = R and C4 = C, which leads to L = CR2. Convenient values are then selected for C and R to yield the 5 Andreas Antoniou is a Canadian academic, currently (2009) a member of the faculty of the University of Victoria, British Columbia. Vi R L C Vo R1 R1 Figure 16.19 Realization of the second-order all-pass transfer function using a voltage divider and an LCR resonator.
Zin V1 I1 ⁄ ≡ = sC4R1R3R5 R2 ⁄ L C4R1R3R5 R2 ⁄ = 1286 Chapter 16 Filters and Tuned Amplifiers desired inductance value L. More details on this circuit and the effect of the nonidealities of the op amps on its performance can be found in Sedra and Brackett (1978). 16.6.2 The Op Amp–RC Resonator Figure 16.21(a) shows the LCR resonator we studied in detail in Section 16.5. Replacing the inductor L with a simulated inductance realized by the Antoniou circuit of Fig. 16.20(a) results in the op amp–RC resonator of Fig. 16.21(b). (Ignore for the moment the additional Figure 16.20 (a) The Antoniou inductance-simulation circuit. (b) Analysis of the circuit assuming ideal op amps. The order of the analysis steps is indicated by the circled numbers.
(a) (b) 16.6 Second-Order Active Filters Based on Inductor Replacement 1287 amplifier drawn with broken lines.) The circuit of Fig. 16.21(b) is a second-order resonator having a pole frequency (16.51) Figure 16.21 (a) An LCR resonator. (b) An op amp–RC resonator obtained by replacing the inductor L in the LCR resonator of (a) with a simulated inductance realized by the Antoniou circuit of Fig. 16.20(a). (c) Implementation of the buffer amplifier K.
L x C6 R6 z y Vr (a) Vr C4 x y Vo C6 A2 A1 R6 z R5 R3 R1 R2 K L C4R1R3R5/ R2 (b) r1 K r2 K 1 r2 r1 (c) ω0 1 LC6 ⁄ 1 C4C6R1R3R5 R2 ⁄ ⁄ = = 1288 Chapter 16 Filters and Tuned Amplifiers where we have used the expression for L given in Eq. (16.50). The pole Q factor can be obtained using the expressent in Eq. (16.35) with C = C6 and R = R6; thus, Q = ω0 C6 R6.
Replacing ω0 by the expression in Eq. (16.51) gives (16.52) Usually one selects C4 = C6 = C and R1 = R2 = R3 = R5 = R, which results in (16.53) (16.54) Thus, if we select a practically convenient value for C, we can use Eq. (16.53) to determine the value of R to realize a given ω0, and then use Eq. (16.54) to determine the value of R6 to realize a given Q.
16.6.3 Realization of the Various Filter Types The op amp–RC resonator of Fig. 16.21(b) can be used to generate circuit realizations for the various second-order filter functions by following the approach described in detail in Section 16.5 in connection with the LCR resonator. Thus to obtain a bandpass function, we disconnect node z from ground and connect it to the signal source Vi. A high-pass function is obtained by injecting Vi to node y. To realize a low-pass function using the LCR resonator, the inductor terminal x is disconnected from ground and connected to Vi.
The corresponding node in the active resonator is the node at which R5 is connected to ground,6 labeled as node x in Fig. 16.21(b). A regular notch function (ωn = ω0) is obtained by feeding Vi to nodes x and y. In all cases the output can be taken as the voltage across the resonance circuit, Vr. However, this is not a convenient node to use as the filter output terminal because connecting a load there would change the filter characteristics.
The problem can be solved easily by utilizing a buffer amplifier. This is the amplifier of gain K, drawn with broken lines in Fig. 16.21(b). Figure 16.21(c) shows how this ampli-fier can be simply implemented using an op amp connected in the noninverting configu-ration. Note that not only does the amplifier K buffer the output of the filter, but it also allows the designer to set the filter gain to any desired value by appropriately selecting the value of K. Figure 16.22 shows the various second-order filter circuits obtained from the resonator of Fig. 16.21(b). The transfer functions and design equations for these circuits are given in Table 16.1. Note that the transfer functions can be written by analogy to those of the LCR resonator. We have already commented on the LP, HP, BP, and regular-notch circuits given in Fig. 16.22(a) to (d). The LPN and HPN circuits in Fig. 16.22(e) and (f) are obtained by 6 This point might not be obvious! The reader, however, can show by direct analysis that when Vi is fed to this node, the function Vr/Vi is indeed low pass.
Q ω0C6R6 R6 C6 C4 ------R2 R1R3R5 ------------------= = ω0 =1 CR ⁄ Q = R6 R ⁄ 16.6 Second-Order Active Filters Based on Inductor Replacement 1289 direct analogy to their LCR counterparts in Fig. 16.18(g) and (i), respectively. The all-pass circuit in Fig. 16.22(g), however, deserves some explanation. 16.6.4 The All-Pass Circuit From Eq. (16.48) we see that an all-pass function with a flat gain of unity can be written as (16.55) Two circuits whose transfer functions are related in this fashion are said to be complemen-tary.7 Thus the all-pass circuit with unity flat gain is the complement of the bandpass circuit with a center-frequency gain of 2. A simple procedure exists for obtaining the complement of a given linear circuit: Disconnect all the circuit nodes that are connected to ground and connect them to Vi, and disconnect all the nodes that are connected to Vi and connect them to ground. That is, interchanging input and ground in a linear circuit generates a circuit whose transfer function is the complement of that of the original circuit.
Returning to the problem at hand, we first use the circuit of Fig. 16.22(c) to realize a BP with a gain of 2 by simply selecting K = 2 and implementing the buffer amplifier with the circuit of Fig. 16.21(c) with r1 = r2. We then interchange input and ground and thus obtain the all-pass circuit of Fig. 16.22(g).
Finally, in addition to being simple to design, the circuits in Fig. 16.22 exhibit excellent performance. They can be used on their own to realize second-order filter functions, or they can be cascaded to implement high-order filters.
7 More about complementary circuits will be presented later in conjunction with Fig. 16.31.
AP = 1 − (BP with a center-frequency gain of 2) EXERCISES D16.19 Use the circuit of Fig. 16.22(c) to design a second-order bandpass filter with a center frequency of 10 kHz, a 3-dB bandwidth of 500 Hz, and a center-frequency gain of 10. Use C = 1.2 nF.
Ans. R1 = R2 = R3 = R5 = 13.26 kΩ; R6 = 265 kΩ; C4 = C6 = 1.2 nF; K = 10, r1 = 10 kΩ, r2 = 90 kΩ D16.20 Realize the Chebyshev filter of Example 16.2, whose transfer function is given in Eq. (16.25), as the cascade connection of three circuits: two of the type shown in Fig. 16.22(a) and one first-order op amp–RC circuit of the type shown in Fig. 16.13(a). Note that you can make the dc gain of all sections equal to unity. Do so. Use as many 10-kΩ resistors as possible.
Ans. First-order section: R1 = R2 = 10 kΩ, C = 5.5 nF; second-order section with ω0 = 4.117 × 104 rad/s and Q = 1.4: R1 = R2 = R3 = R5 = 10 kΩ, R6 = 14 kΩ, C4 = C6 = 2.43 nF, r1 = ∞, r2 = 0; second-order section with ω0 = 6.246 × 104 rad/s and Q = 5.56: R1 = R2 = R3 = R5 = 10 kΩ, R6 = 55.6 kΩ, C4 = C6 = 1.6 nF, r1 = ∞, r2 = 0 1290 Chapter 16 Filters and Tuned Amplifiers Figure 16.22 Realizations for the various second-order filter functions using the op amp–RC resonator of Fig. 16.21(b): (a) LP, (b) HP, (c) BP. The circuits are based on the LCR circuit in Fig. 16.18. Design consid-erations are given in Table 16.1.
A1 R5 Vo C6 R1 R2 A2 R3 Vi C4 K x R6 LP (a) Vo R6 R1 R2 A2 R5 A1 C6 K Vi HP R3 C4 y (b) R5 Vo C6 R1 R2 A2 R3 A1 Vi C4 K R6 BP z (c) 16.6 Second-Order Active Filters Based on Inductor Replacement 1291 Figure 16.22 (continued) (d) Notch at ω0, (e) LPN, , (f ) HPN, . Vo C6 R1 R2 A2 R3 A1 Vi C4 K R6 Notch at 0 R5 y x (d) Vo C62 R1 R2 A2 R3 A1 Vi C4 K R6 R5 x y2 C61 y1 LPN, n 0 (e) Vo C6 R1 R2 A2 R3 A1 Vi C4 K R52 R51 x2 y HPN, n 0 R6 x1 (f) ωn ω0 ≥ ωn ω0 ≤ 1292 Chapter 16 Filters and Tuned Amplifiers Figure 16.22 (continued) (g) All pass. All-pass Vi C6 r2 Vo A2 A1 R6 R5 R3 R2 R1 r1 C4 (g) Table 16.1 Design Data for the Circuits of Fig. 16.22 Circuit Transfer Function and Other Parameters Design Equations Resonator Fig. 16.21(b) Low-pass (LP) Fig. 16.22(a) K = DC gain High-pass (HP) Fig. 16.22(b) K = High-frequency gain Bandpass (BP) Fig. 16.22(c) K = Center-frequency gain Regular notch (N) Fig. 16.22(d) K = Low- and high-frequency gain ω0 1 C4C6R1R3R5 R2 ⁄ ⁄ = Q R6 C6 C4 ------R2 R1R3R5 -------------------= C4 = C6 = C (practical value) R1 = R2 = R3 = R5 = 1 ω0C ⁄ R6 = Q ω0C ⁄ T s ( ) KR2 C4C6R1R3R5 ⁄ s2 s 1 C6R6 -------------R2 C4C6R1R3R5 ---------------------------------+ + -------------------------------------------------------------------= T s ( ) Ks2 s2 s 1 C6R6 -------------R2 C4C6R1R3R5 ---------------------------------+ + -------------------------------------------------------------------= T s ( ) Ks C6R6 ⁄ s2 s 1 C6R6 -------------R2 C4C6R1R3R5 ---------------------------------+ + -------------------------------------------------------------------= T s ( ) K s2 R2 C4C6R1R3R5 ⁄ ( ) + [ ] s2 s 1 C6R6 -------------R2 C4C6R1R3R5 ---------------------------------+ + --------------------------------------------------------------------= 16.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1293 16.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology In this section, we study another family of op amp–RC circuits that realize second-order fil-ter functions. The circuits are based on the use of two integrators connected in cascade in an overall feedback loop and are thus known as two-integrator-loop circuits.
16.7.1 Derivation of the Two-Integrator-Loop Biquad To derive the two-integrator-loop biquadratic circuit, or biquad as it is commonly known,8 consider the second-order high-pass transfer function (16.56) Low-pass notch (LPN) Fig. 16.22(e) K = DC gain C61 + C62 = C6 = C C62 = C − C61 High-pass notch (HPN) Fig. 16.22(f) K = High-frequency gain All-pass (AP) Fig. 16.22(g) r1 = r2 = r (arbitrary) Adjust r2 to make Qz = Q T s ( ) K C61 C61 C62 + -----------------------= s2 R2 C4C61R1R3R5 ⁄ ( ) + s2 s 1 C61 C62 + ( )R6 -----------------------------------R2 C4 C61 C62 + ( )R1R3R5 -------------------------------------------------------+ + ---------------------------------------------------------------------------------------------------------------× ωn 1 C4C61R1R3R5 R2 ⁄ ⁄ = ω0 1 C4 C61 C62 + ( )R1R3R5 R2 ⁄ ⁄ = Q R6 C61 C62 + C4 -----------------------R2 R1R3R5 -------------------= C61 = C ω0 ωn ⁄ ( )2 T s ( ) K s2 R2 C4C6R1R3R51 ⁄ ( ) + s2 s 1 C6R6 -------------R2 C4C6R1R3 --------------------------1 R51 --------1 R52 --------+ ⎝ ⎠ ⎛ ⎞ + + -----------------------------------------------------------------------------------------= ωn 1 C4C6R1R3R51 R2 ⁄ ⁄ = ω0 R2 C4C6R1R3 --------------------------1 R51 --------1 R52 --------+ ⎝ ⎠ ⎛ ⎞ = Q R6 C6 C4 ------ R2 R1R3 ------------1 R51 --------1 R52 --------+ ⎝ ⎠ ⎛ ⎞ = 1 R51 --------1 R52 --------+ = 1 R5 ------ = ω0C R51 = R5 ω0 ωn ⁄ ( )2 R52 = R5 1 ωn ω0 ⁄ ( )2 – [ ] ⁄ T s ( ) s2 s 1 C6R6 -------------r2 r1 ----– R2 C4C6R1R3R5 ---------------------------------+ s2 s 1 C6R6 -------------R2 C4C6R1R3R5 ---------------------------------+ + ------------------------------------------------------------------------= ωz ω0 = Qz Q r1 r2 ⁄ ( ) Flat gain 1 = = 8 The name biquad stems from the fact that this circuit in its most general form is capable of realizing a biquadratic transfer function, that is, one that is the ratio of two quadratic polynomials. Vhp Vi --------Ks2 s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------= 1294 Chapter 16 Filters and Tuned Amplifiers where K is the high-frequency gain. Cross-multiplying Eq. (16.56) and dividing both sides of the resulting equation by s2 (to get all the terms involving s in the form which is the transfer function of an integrator) gives (16.57) In this equation we observe that the signal Vhp can be obtained by passing Vhp through an integrator with a time constant equal to . Furthermore, passing the resulting signal through another identical integrator results in the third signal involving Vhp in Eq. (16.57)—namely, Vhp. Figure 16.23(a) shows a block diagram for such a two-integrator arrangement. Note that in anticipation of the use of the inverting op-amp Miller integrator circuit (Section 2.5.2) to implement each integrator, the integrator blocks in Fig.
16.23(a) have been assigned negative signs.
The problem still remains, however, of how to form Vhp, the input signal feeding the two cascaded integrators. Toward that end, we rearrange Eq. (16.57), expressing Vhp in terms of its single- and double-integrated versions and of Vi as (16.58) which suggests that Vhp can be obtained by using the weighted summer of Fig. 16.23(b).
Now it should be easy to see that a complete block diagram realization can be obtained by combining the integrator blocks of Fig. 16.23(a) with the summer block of Fig. 16.23(b), as shown in Fig. 16.23(c).
Figure 16.23 Derivation of a block diagram realization of the two-integrator-loop biquad.
1 s, ⁄ Vhp 1 Q ---- ω0 s ------Vhp ⎝ ⎠ ⎛ ⎞ ω0 2 s2 ------Vhp ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ + + KVi = ω0 s ⁄ ( ) 1 ω0 ⁄ ω0 2 s ⁄ 2 ( ) Vhp KVi 1 Q ----ω0 s ------Vhp – ω0 2 s2 ------Vhp – = (a) (b) (c) 16.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1295 In the realization of Fig. 16.23(c), Vhp, obtained at the output of the summer, realizes the high-pass transfer function of Eq. (16.56). The signal at the output of the first integrator is − Vhp, which is a bandpass function, (16.59) Therefore the signal at the output of the first integrator is labeled Vbp. Note that the center-frequency gain of the bandpass filter realized is equal to −KQ.
In a similar fashion, we can show that the transfer function realized at the output of the second integrator is the low-pass function, (16.60) Thus the output of the second integrator is labeled Vlp. Note that the dc gain of the low-pass filter realized is equal to K.
We conclude that the two-integrator-loop biquad shown in block diagram form in Fig. 16.23(c) realizes the three basic second-order filtering functions, LP, BP, and HP, simul-taneously. This versatility has made the circuit very popular and has given it the name uni-versal active filter.
16.7.2 Circuit Implementation To obtain an op-amp circuit implementation of the two-integrator-loop biquad of Fig. 16.23(c), we replace each integrator with a Miller integrator circuit having and we replace the summer block with an op-amp summing circuit that is capable of assigning both positive and negative weights to its inputs. The resulting circuit, known as the Kerwin– Huelsman–Newcomb or KHN biquad, after its inventors, is shown in Fig. 16.24(a). Given values for ω0, Q, and K, the design of the circuit is straightforward: We select suitably practical values for the components of the integrators C and R so that To determine the values of the resistors associated with the summer, we first use superposi-tion to express the output of the summer Vhp in terms of its inputs, Vi, Vbp and Vlp as Substituting and gives (16.61) Equating the last right-hand-side terms of Eqs. (16.61) and (16.58) gives (16.62) which implies that we can select arbitrary but practically convenient equal values for R1 and Rf. Then, equating the second-to-last terms on the right-hand side of Eqs. (16.61) and (16.58) and setting R1 = Rf yields the ratio required to realize a given Q as Thp Vhp Vi ⁄ ≡ ω0 s ⁄ ( ) ω0 s ⁄ – ( )Vhp Vi -----------------------------Kω0s s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------– Tbp s ( ) = = ω0 2 s2 ⁄ ( )Vhp Vi ----------------------------Kω0 2 s2 s ω0 Q ⁄ ( ) ω0 2 + + ----------------------------------------------Tlp s ( ) = = CR =1 ω0 ⁄ , CR =1 ω0 ⁄ .
Vhp Vi R3 R2 R3 + ------------------ 1 Rf R1 -----+ ⎝ ⎠ ⎛ ⎞ Vbp R2 R2 R3 + ------------------ 1 Rf R1 -----+ ⎝ ⎠ ⎛ ⎞ + Vlp Rf R1 -----– = Vbp ω0 s ⁄ ( )Vhp – = Vlp ω0 2 s2 ⁄ ( )Vhp = Vhp R3 R2 R3 + ------------------ 1 Rf R1 -----+ ⎝ ⎠ ⎛ ⎞Vi R2 R2 R3 + ------------------ 1 Rf R1 -----+ ⎝ ⎠ ⎛ ⎞ ω0 s ------Vhp – ⎝ ⎠ ⎛ ⎞ Rf R1 ----- ω0 2 s2 ------Vhp ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ – + = Rf R1 ⁄ 1 = R3 R2 ⁄ 1296 Chapter 16 Filters and Tuned Amplifiers (16.63) Thus an arbitrary but convenient value can be selected for either R2 or R3, and the value of the other resistance can be determined using Eq. (16.63). Finally, equating the coefficients of Vi in Eqs. (16.61) and (16.58) and substituting Rf = R1 and for from Eq. (16.63) results in (16.64) Thus the gain parameter K is fixed to this value.
The KHN biquad can be used to realize notch and all-pass functions by summing weighted versions of the three outputs, LP, BP, and HP. Such an op-amp summer is shown in Fig. 16.24(b); for this summer we can write (16.65) Substituting for Thp, Tbp, and Tlp from Eqs. (16.56), (16.59), and (16.60), respectively, gives the overall transfer function (16.66) Figure 16.24 (a) The KHN biquad circuit, obtained as a direct implementation of the block diagram of Fig. 16.23(c). The three basic filtering functions, HP, BP, and LP, are simultaneously realized. (b) To obtain notch and all-pass functions, the three outputs are summed with appropriate weights using this op-amp summer.
R1 Rf Vi R R3 C R Vlp C Vbp Vhp R2 (a) Vhp RL Vlp Vbp Vo RF RB RH (b) R3 R2 ⁄ = 2Q 1 – R3 R2 ⁄ K 2 (1 Q) ⁄ – = V o RF RH ------Vhp RF RB ------Vbp RF RL ------Vlp + + ⎝ ⎠ ⎛ ⎞ – = Vi RF RH ------Thp RF RB ------Tbp RF RL ------Tlp + + ⎝ ⎠ ⎛ ⎞ – = V o V i -----K (RF RH ⁄ )s2 s RF RB ⁄ ( )ω0 RF RL ⁄ ( )ω0 2 + – s2 s ω0 Q ⁄ ( ) ω0 2 + + ---------------------------------------------------------------------------------------------------– = 16.7 Second-Order Active Filters Based on the Two-Integrator-Loop Topology 1297 from which we can see that different transmission zeros can be obtained by the appropriate selection of the values of the summing resistors. For instance, a notch is obtained by select-ing RB = ∞ and (16.67) 16.7.3 An Alternative Two-Integrator-Loop Biquad Circuit An alternative two-integrator-loop biquad circuit in which all three op amps are used in a single-ended mode can be developed as follows: Rather than using the input summer to add signals with positive and negative coefficients, we can introduce an additional inverter, as shown in Fig. 16.25(a). Now all the coefficients of the summer have the same sign, and we can dispense with the summing amplifier altogether and perform the summation at the virtual-ground input of the first integrator. Observe that the summing weights of 1, 1/Q, and K are realized by using resistances of R, QR, and R/K, respectively. The resulting circuit is shown in Fig. 16.25(b), from which we observe that the high-pass function is no longer available! This is the price paid for obtaining a circuit that utilizes all op amps in a single-ended mode. The circuit of Fig. 16.25(b) is known as the Tow–Thomas biquad, after its originators.
Rather than using a fourth op amp to realize the finite transmission zeros required for the notch and all-pass functions, as was done with the KHN biquad, an economical feedfor-ward scheme can be employed with the Tow–Thomas circuit. Specifically, the virtual ground available at the input of each of the three op amps in the Tow–Thomas circuit permits the input signal to be fed to all three op amps, as shown in Fig. 16.26. If Vo is taken at the output of the damped integrator, straightforward analysis yields the filter transfer function Figure 16.25 (a) Derivation of an alternative two-integrator-loop biquad in which all op amps are used in a single-ended fashion. (b) The resulting circuit, known as the Tow–Thomas biquad.
RH RL ------ωn ω0 -------⎝ ⎠ ⎛ ⎞ 2 = Vlp Vlp 0 s 1 Q Vi K 1 Vhp Vbp 0 s 1 (a) Rd QR R C R Vlp Vbp Rg C r r R K Vi Vlp (b) 1298 Chapter 16 Filters and Tuned Amplifiers (16.68) which can be used to obtain the design data given in Table 16.2.
16.7.4 Final Remarks Two-integrator-loop biquads are extremely versatile and easy to design. However, their per-formance is adversely affected by the finite bandwidth of the op amps. Special techniques exist for compensating the circuit for such effects [see the SPICE simulation example on the CD and the website, and Sedra and Brackett (1978)].
Figure 16.26 The Tow–Thomas biquad with feedforward. The transfer function of Eq. (16.68) is realized by feeding the input signal through appropriate components to the inputs of the three op amps. This circuit can realize all special second-order functions. The design equations are given in Table 16.2.
Table 16.2 Design Data for the Circuit in Fig. 16.26 All cases C = arbitrary, r = arbitrary LP C1 = 0, R1 = ∞, R2 = R/dc gain, R3 = ∞ Positive BP C1 = 0, R1 = ∞, R2 = ∞, Negative BP C1 = 0, , R2 = ∞, R3 = ∞ HP C1 = C × high-frequency gain, R1 = ∞, R2 = ∞, R3 = ∞ Notch C1 = C × high-frequency gain, R1 = ∞, (all types) R3 = ∞ AP C1 = C × flat gain, R1 = ∞, , R = 1 ω0 ⁄ C, R3 = Qr center-frequency gain ⁄ R1 = QR center-frequency gain ⁄ R2 = R ω0 ωn ⁄ ( )2 high-frequency gain, ⁄ R2 = R gain ⁄ R3 = Qr gain ⁄ Vo Vi -----s2 C1 C ------⎝ ⎠ ⎛ ⎞ s 1 C ----1 R1 -----r RR3 ----------– ⎝ ⎠ ⎛ ⎞ 1 C2RR2 ----------------+ + s2 s 1 QCR ------------1 C2R2 ------------+ + ---------------------------------------------------------------------------------– = 16.8 Single-Amplifier Biquadratic Active Filters 1299 16.8 Single-Amplifier Biquadratic Active Filters The op amp–RC biquadratic circuits studied in the two preceding sections provide good per-formance, are versatile, and are easy to design and to adjust (tune) after final assembly.
Unfortunately, however, they are not economic in their use of op amps, requiring three or four amplifiers per second-order section. This can be a problem, especially in applications where power-supply current is to be conserved: for instance, in a battery-operated instru-ment. In this section we shall study a class of second-order filter circuits that requires only one op amp per biquad. These minimal realizations, however, suffer a greater dependence on the limited gain and bandwidth of the op amp and can also be more sensitive to the unavoid-able tolerances in the values of resistors and capacitors than the multiple-op-amp biquads of the preceding sections. The single-amplifier biquads (SABs) are therefore limited to the less stringent filter specifications—for example, pole Q factors less than about 10.
The synthesis of SAB circuits is based on the use of feedback to move the poles of an RC circuit from the negative real axis, where they naturally lie, to the complex-conjugate locations required to provide selective filter response. The synthesis of SABs follows a two-step process: 1. Synthesis of a feedback loop that realizes a pair of complex-conjugate poles charac-terized by a frequency ω0 and a Q factor Q. 2. Injecting the input signal in a way that realizes the desired transmission zeros.
16.8.1 Synthesis of the Feedback Loop Consider the circuit shown in Fig. 16.27(a), which consists of a two-port RC network n placed in the negative-feedback path of an op amp. We shall assume that, except for having a finite gain A, the op amp is ideal. We shall denote by t(s) the open-circuit voltage transfer EXERCISES D16.21 Design the KHN circuit to realize a high-pass function with f0 = 10 kHz and Q = 2. Choose C = 1 nF. What is the value of high-frequency gain obtained? What is the center-frequency gain of the bandpass function that is simultaneously available at the output of the first integrator?
Ans. R = 15.9 kΩ; R1 = Rf = R2 = 10 kΩ (arbitrary); R3 = 30 kΩ; 1.5; 3 D16.22 Use the KHN circuit together with an output summing amplifier to design a low-pass notch filter with f0 = 5 kHz, fn = 8 kHz, Q = 5, and a dc gain of 3. Select C = 1 nF and RL = 10 kΩ.
Ans. R = 31.83 kΩ; R1 = Rf = R2 = 10 kΩ (arbitrary); R3 = 90 kΩ; RH = 25.6 kΩ; RF = 16.7 kΩ; RB = ∞ D16.23 Use the Tow–Thomas biquad (Fig. 16.25b) to design a second-order bandpass filter with f0 = 10 kHz, Q = 20, and unity center-frequency gain. If R = 10 kΩ, give the values of C, Rd, and Rg.
Ans. 1.59 nF; 200 kΩ; 200 kΩ D16.24 Use the data of Table 16.2 to design the biquad circuit of Fig. 16.26 to realize an all-pass filter with ω0 = 104 rad/s, Q = 5, and flat gain = 1. Use C = 10 nF and r = 10 kΩ.
Ans. R = 10 kΩ; Q-determining resistor = 50 kΩ; C1 = 10 nF; R1 = ∞; R2 = 10 kΩ; R3 = 50 kΩ 1300 Chapter 16 Filters and Tuned Amplifiers function of the RC network n, where the definition of t(s) is illustrated in Fig. 16.27(b). The transfer function t(s) can in general be written as the ratio of two polynomials N(s) and D(s): The roots of N(s) are the transmission zeros of the RC network, and the roots of D(s) are its poles. Study of circuit theory shows that while the poles of an RC network are restricted to lie on the negative real axis, the zeros can in general lie anywhere in the s plane.
The loop gain L(s) of the feedback circuit in Fig. 16.27(a) can be determined using the method of Section 10.9. It is simply the product of the op-amp gain A and the transfer function t(s), (16.69) Substituting for L(s) into the characteristic equation (16.70) results in the poles sP of the closed-loop circuit obtained as solutions to the equation (16.71) In the ideal case, A = ∞ and the poles are obtained from (16.72) That is, the filter poles are identical to the zeros of the RC network.
Since our objective is to realize a pair of complex-conjugate poles, we should select an RC network that can have complex-conjugate transmission zeros. The simplest such networks are the bridged-T networks shown in Fig. 16.28 together with their transfer functions t(s) from b to a, with a open-circuited. As an example, consider the circuit generated by placing the bridged-T network of Fig. 16.28(a) in the negative-feedback path of an op amp, as shown in Fig. 16.29.
The pole polynomial of the active-filter circuit will be equal to the numerator polynomial of the bridged-T network; thus, Figure 16.27 (a) Feedback loop obtained by placing a two-port RC network n in the feedback path of an op amp. (b) Definition of the open-circuit transfer function t(s) of the RC network.
(a) A (b) t s ( ) N s ( ) D s ( ) -----------= L s ( ) At s ( ) AN s ( ) D s ( ) ---------------= = 1 L s ( ) + 0 = t(sP) = 1 A ---– N(sP) = 0 16.8 Single-Amplifier Biquadratic Active Filters 1301 which enables us to obtain ω0 and Q as (16.73) (16.74) Figure 16.28 Two RC networks (called bridged-T networks) that can have complex transmission zeros.
The transfer functions given are from b to a, with a open-circuited.
a b (a) a b (b) Figure 16.29 An active-filter feedback loop generated using the bridged-T network of Fig. 16.28(a).
s2 sω0 Q ------ω0 2 + + s2 s 1 C1 ------1 C2 ------+ ⎝ ⎠ ⎛ ⎞1 R3 -----1 C1C2R3R4 -------------------------+ + = ω0 1 C1C2R3R4 -----------------------------= Q C1C2R3R4 R3 -----------------------------1 C1 ------1 C2 ------+ ⎝ ⎠ ⎛ ⎞ 1 – = 1302 Chapter 16 Filters and Tuned Amplifiers If we are designing this circuit, ω0 and Q are given and Eqs. (16.73) and (16.74) can be used to determine C1, C2, R3, and R4. It follows that there are two degrees of freedom. Let us exhaust one of these by selecting C1 = C2 = C. Let us also denote R3 = R and By substituting in Eqs. (16.73) and (16.74), and with some manipulation, we obtain (16.75) (16.76) Thus if we are given the value of Q, Eq. (16.75) can be used to determine the ratio of the two resistances R3 and R4. Then the given values of ω0 and Q can be substituted in Eq. (16.76) to determine the time constant CR. There remains one degree of freedom—the value of C or R can be arbitrarily chosen. In an actual design, this value, which sets the impedance level of the circuit, should be chosen so that the resulting component values are practical.
16.8.2 Injecting the Input Signal Having synthesized a feedback loop that realizes a given pair of poles, we now consider con-necting the input signal source to the circuit. We wish to do this, of course, without altering the poles.
Since, for the purpose of finding the poles of a circuit, an ideal voltage source is equiva-lent to a short circuit, it follows that any circuit node that is connected to ground can instead be connected to the input voltage source without causing the poles to change. Thus the method of injecting the input voltage signal into the feedback loop is simply to disconnect a component (or several components) that is (are) connected to ground and connect it (them) to the input source. Depending on the component(s) through which the input signal is injected, different transmission zeros are obtained. This is, of course, the same method we used in Section 16.5 with the LCR resonator and in Section 16.6 with the biquads based on the LCR resonator.
As an example, consider the feedback loop of Fig. 16.29. Here we have two grounded nodes (one terminal of R4 and the positive input terminal of the op amp) that can serve for injecting the input signal. Figure 16.30(a) shows the circuit with the input signal injected through part of the resistance R4. Note that the two resistances and have a parallel equivalent of R4.
Analysis of the circuit to determine its voltage transfer function is illustrated in Fig. 16.30(b). Note that we have assumed the op amp to be ideal, and have R4 = R m.
⁄ m 4Q2 = CR 2Q ω0 -------= EXERCISES D16.25 Design the circuit of Fig. 16.29 to realize a pair of poles with ω0 = 104 rad/s and Q = 1.
Select C1 = C2 = 1 nF.
Ans. R3 = 200 kΩ; R4 = 50 kΩ 16.26 For the circuit designed in Exercise 16.25, find the location of the poles of the RC network in the feedback loop.
Ans. −0.382 × 104 and −2.618 × 104 rad/s R4 α ⁄ R4 1 α – ( ) ⁄ T s ( ) V o s ( ) Vi s ( ) ⁄ ≡ 16.8 Single-Amplifier Biquadratic Active Filters 1303 indicated the order of the analysis steps by the circled numbers. The final step, number 9, consists of writing a node equation at X and substituting for Vx by the value determined in step 5. The result is the transfer function We recognize this as a bandpass function whose center-frequency gain can be controlled by the value of α. As expected, the denominator polynomial is identical to the numerator polynomial of t(s) given in Fig. 16.28(a). Figure 16.30 (a) The feedback loop of Fig. 16.29 with the input signal injected through part of resistance R4. This circuit realizes the bandpass function. (b) Analysis of the circuit in (a) to determine its voltage trans-fer function T(s) with the order of the analysis steps indicated by the circled numbers.
(a) Vi (Vo /R3) sC1(Vo Vx) Node equation at X R4/(1) Vx Vx/ Vx Vo /R3 C2 R3 C1 ViVx R4/ (R4/) R4 7 3 0 A X 0 V 1 4 5 6 9 8 2 Vo Vo sC2R3 1 ( ( (b) Vo V i -----s α C1R4 ⁄ ( ) – s2 s 1 C1 ------1 C2 ------+ ⎝ ⎠ ⎛ ⎞1 R3 -----1 C1C2R3R4 -------------------------+ + -----------------------------------------------------------------------------= 1304 Chapter 16 Filters and Tuned Amplifiers 16.8.3 Generation of Equivalent Feedback Loops The complementary transformation of feedback loops is based on the property of linear net-works illustrated in Fig. 16.31 for the two-port (three-terminal) network n. In Fig. 16.31(a), ter-minal c is grounded and a signal Vb is applied to terminal b. The transfer function from b to a with c grounded is denoted t. Then, in Fig. 16.31(b), terminal b is grounded and the input sig-nal is applied to terminal c. The transfer function from c to a with b grounded can be shown to be the complement of t—that is, 1 – t. (Recall that we used this property in generating a circuit realization for the all-pass function in Section 16.6.) Application of the complementary transformation to a feedback loop to generate an equivalent feedback loop is a two-step process: 1. Nodes of the feedback network and any of the op-amp inputs that are connected to ground should be disconnected from ground and connected to the op-amp output.
Conversely, those nodes that were connected to the op-amp output should be now connected to ground. That is, we simply interchange the op-amp output terminal with ground.
2. The two input terminals of the op amp should be interchanged.
The feedback loop generated by this transformation has the same characteristic equation, and hence the same poles, as the original loop.
To illustrate, we show in Fig. 16.32(a) the feedback loop formed by connecting a two-port RC network in the negative-feedback path of an op amp. Application of the complementary transformation to this loop results in the feedback loop of Fig. 16.32(b). Note that in the latter loop the op amp is used in the unity-gain follower configuration. We shall now show that the two loops of Fig. 16.32 are equivalent.
If the op amp has an open-loop gain A, the follower in the circuit of Fig. 16.32(b) will have a gain of This, together with the fact that the transfer function of network n from c to a is 1 − t (see Fig. 16.31), enables us to write for the circuit in Fig. 16.32(b) the characteristic equation This equation can be manipulated to the form EXERCISE 16.27 Use the component values obtained in Exercise 16.25 to design the bandpass circuit of Fig. 16.30(a). Determine the values of and to obtain a center-frequency gain of unity.
Ans. 100 kΩ; 100 kΩ (R4 α ⁄ ) R4 (1 α) – ⁄ A A 1 + ( ) ⁄ .
1 A A 1 + ------------ 1 t – ( ) – 0 = 1 At + 0 = 16.8 Single-Amplifier Biquadratic Active Filters 1305 which is the characteristic equation of the loop in Fig. 16.32(a). As an example, consider the application of the complementary transformation to the feedback loop of Fig. 16.29: The feedback loop of Fig. 16.33(a) results. Injecting the input signal through C1 results in the cir-cuit in Fig. 16.33(b), which can be shown (by direct analysis) to realize a second-order high-pass function. This circuit is one of a family of SABs known as the Sallen-and-Key circuits, after their originators. The design of the circuit in Fig. 16.33(b) is based on Eqs. (16.73) through (16.76): namely, R3 = R, C1 = C2 = C, and the value of C is arbitrarily chosen to be practically convenient.
As another example, Fig. 16.34(a) shows the feedback loop generated by placing the two-port RC network of Fig. 16.28(b) in the negative-feedback path of an op amp. For an ideal op amp, this feedback loop realizes a pair of complex-conjugate natural modes having the same location as the zeros of t(s) of the RC network. Thus, using the expression for t(s) given in Fig. 16.28(b), we can write for the active-filter poles (16.77) Figure 16.31 Interchanging input and ground results in the complement of the transfer function.
Figure 16.32 Application of the complementary transformation to the feedback loop in (a) results in the equivalent loop (same poles) shown in (b).
c (a) (b) Network n t(s) A 1 t(s) Network n A R4 = R 4Q2, ⁄ CR = 2Q ω0 ⁄ , ω0 1 C3C4R1R2 ⁄ = 1306 Chapter 16 Filters and Tuned Amplifiers Figure 16.33 (a) Feedback loop obtained by applying the complementary transformation to the loop in Fig. 16.29. (b) Injecting the input signal through C1 realizes the high-pass function. This is one of the Sallen-and-Key family of circuits.
Figure 16.34 (a) Feedback loop obtained by placing the bridged-T network of Fig. 16.28(b) in the negative-feedback path of an op amp. (b) Equivalent feedback loop generated by applying the complementary transfor-mation to the loop in (a). (c) A low-pass filter obtained by injecting Vi through R1 into the loop in (b).
(a) (b) V C3 C4 R1 R2 (a) C4 C3 R1 R2 (b) C4 C3 R2 R1 Vi Vo (c) 16.9 Sensitivity 1307 (16.78) Normally the design of this circuit is based on selecting R1 = R2 = R, C4 = C, and C3 = C/m.
When substituted in Eqs. (16.77) and (16.78), these yield (16.79) (16.80) with the remaining degree of freedom (the value of C or R) left to the designer to choose.
Injecting the input signal to the C4 terminal that is connected to ground can be shown to result in a bandpass realization. If, however, we apply the complementary transformation to the feedback loop in Fig. 16.34(a), we obtain the equivalent loop in Fig. 16.34(b). The loop equivalence means that the circuit of Fig. 16.34(b) has the same poles and thus the same ω0 and Q and the same design equations (Eqs. 16.77 through 16.80). The new loop in Fig. 16.34(b) can be used to realize a low-pass function by injecting the input signal as shown in Fig. 16.34(c).
16.9 Sensitivity Because of the tolerances in component values and because of the finite op-amp gain, the response of the actual assembled filter will deviate from the ideal response. As a means for predicting such deviations, the filter designer employs the concept of sensitivity. Specifi-cally, for second-order filters one is usually interested in finding how sensitive their poles are relative to variations (both initial tolerances and future drifts) in RC component values and amplifier gain. These sensitivities can be quantified using the classical sensitivity function defined as (16.81) Thus, (16.82) Q C3C4R1R2 C4 ----------------------------- 1 R1 -----1 R2 -----+ ⎝ ⎠ ⎛ ⎞ 1 – = m 4Q2 = CR 2Q ω0 ⁄ = EXERCISES 16.28 Analyze the circuit in Fig. 16.34(c) to determine its transfer function and thus show that ω0 and Q are indeed those in Eqs. (16.77) and (16.78). Also show that the dc gain is unity.
D16.29 Design the circuit in Fig. 16.34(c) to realize a low-pass filter with f0 = 4 kHz and .
Use 10-kΩ resistors.
Ans. R1 = R2 = 10 kΩ; C3 = 2.81 nF; C4 = 5.63 nF V o s ( ) Vi s ( ) ⁄ Q 1 2 ⁄ = Sx y, Sx y Lim Δx→0 ≡ Δy y ⁄ Δx x ⁄ -------------Sx y ∂y ∂x ----- x y --= 1308 Chapter 16 Filters and Tuned Amplifiers Here, x denotes the value of a component (a resistor, a capacitor, or an amplifier gain) and y denotes a circuit parameter of interest (say, ω0 or Q). For small changes (16.83) Thus we can use the value of to determine the per-unit change in y due to a given per-unit change in x. For instance, if the sensitivity of Q relative to a particular resistance R1 is 5, then a 1% increase in R1 results in a 5% increase in the value of Q. Sx y Δy y ⁄ Δx x ⁄ -------------Sx y Example 16.3 For the feedback loop of Fig. 16.29, find the sensitivities of ω0 and Q relative to all the passive compo-nents and the op-amp gain. Evaluate these sensitivities for the design considered in the preceding section for which C1 = C2.
Solution To find the sensitivities with respect to the passive components, called passive sensitivities, we assume that the op-amp gain is infinite. In this case, ω0 and Q are given by Eqs. (16.73) and (16.74). Thus for ω0 we have which can be used together with the sensitivity definition of Eq. (16.82) to obtain For Q we have to which we apply the sensitivity definition to obtain For the design with C1 = C2 we see that Similarly, we can show that It is important to remember that the sensitivity expression should be derived before values corresponding to a particular design are substituted.
Next we consider the sensitivities relative to the amplifier gain. If we assume the op amp to have a finite gain A, the characteristic equation for the loop becomes (16.84) where t(s) is given in Fig. 16.28(a). To simplify matters we can substitute for the passive components by their design values. This causes no errors in evaluating sensitivities, since we are now finding the ω0 1 C1C2R3R4 -----------------------------= SC1 ω0 SC2 ω0 SR3 ω0 SR4 ω0 1 2 ---– = = = = Q C1C2R3R4 1 C1 ------1 C2 ------+ ⎝ ⎠ ⎛ ⎞1 R3 -----1 – = SC1 Q 1 2 ---C2 C1 ------C1 C2 ------– ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ C2 C1 ------C1 C2 ------+ ⎝ ⎠ ⎜ ⎟ ⎛ ⎞ 1 – = SC1 Q = 0.
SC2 Q 0, SR3 Q 1 2 ---, SR4 Q 1 2 ---– = = = 1 At s ( ) + 0 = 16.9 Sensitivity 1309 16.9.1 A Concluding Remark The9results of Example 16.3 indicate a serious disadvantage of single-amplifier biquads— the sensitivity of Q relative to the amplifier gain is quite high. Although a technique exists for reducing in SABs (see Sedra et al., 1980), this is done at the expense of increased passive sensitivities. Nevertheless, the resulting SABs are used extensively in many applica-tions. However, for filters with Q factors greater than about 10, one usually opts for one of the multiamplifier biquads studied in Sections 16.6 and 16.7. For these circuits is proportional to Q, rather than to Q2 as in the SAB case (Eq. 16.89). sensitivity with respect to the amplifier gain. Using the design values obtained earlier—namely, C1 = C2 = C, R3 = R, , and —we get (16.85) where ω0 and Q denote the nominal or design values of the pole frequency and Q factor. The actual values are obtained by substituting for t(s) in Eq. (16.84): Assuming the gain A to be real and dividing both sides by A + 1, we get (16.86) From this equation we see that the actual pole frequency, ω0a, and the pole Q, Qa, are (16.87) (16.88) Thus For and we obtain It is usual to drop the subscript a in this expression and write (16.89) Note that if Q is high its sensitivity relative to the amplifier gain can be quite high.9 R4 = R 4Q2 ⁄ CR = 2Q ω0 ⁄ t s ( ) s2 s ω0 Q ⁄ ( ) ω0 2 + + s2 s ω0 Q ⁄ ( ) 2Q2 1 + ( ) ω0 2 + + ----------------------------------------------------------------------= s2 sω0 Q ------ 2Q2 1 + ( ) ω0 2 A s2 sω0 Q ------ω0 2 + + ⎝ ⎠ ⎛ ⎞ + + + = 0 s2 sω0 Q ------ 1 2Q2 A 1 + ------------+ ⎝ ⎠ ⎛ ⎞ ω0 2 + + 0 = ω0a ω0 = Qa Q 1 2Q2 A 1 + ( ) ⁄ + -----------------------------------------= SA ω0a 0 = SA Qa A A 1 + -------------2Q2 A 1 + ( ) ⁄ 1 2Q2 A 1 + ( ) ⁄ + -----------------------------------------= A @ 2Q2 A @ 1 SA Qa 2Q2 A ----------SA Q 2Q2 A ----------Q 5 ≥ ( ), 9 Because the open-loop gain A of op amps usually has wide tolerance, it is important to keep and very small.
SA ω0 SA Q SA Q SA Q 1310 Chapter 16 Filters and Tuned Amplifiers 16.10 Switched-Capacitor Filters The active-RC filter circuits presented above have two properties that make their production in monolithic IC form difficult, if not practically impossible; these are the need for large-val-ued capacitors and the requirement of accurate RC time constants. The search therefore has continued for a method of filter design that would lend itself more naturally to IC implemen-tation. In this section we shall introduce one such method.
16.10.1 The Basic Principle The switched-capacitor filter technique is based on the realization that a capacitor switched between two circuit nodes at a sufficiently high rate is equivalent to a resistor connecting these two nodes. To be specific, consider the active-RC integrator of Fig. 16.35(a). This is the familiar Miller integrator, which we used in the two-integrator-loop biquad in Section 16.7. In Fig. 16.35(b) we have replaced the input resistor R1 by a grounded capacitor C1 together with two MOS transistors acting as switches. In some circuits, more elaborate switch configurations are used, but such details are beyond our present need.
The two MOS switches in Fig. 16.35(b) are driven by a nonoverlapping two-phase clock. Figure 16.35(c) shows the clock waveforms. We shall assume in this introductory exposition that the clock frequency is much higher than the frequency of the input signal vi. Thus during clock phase when C1 is connected across the input signal source vi, the variations in the input signal are negligibly small. It follows that during , capacitor C1 charges up to the voltage vi, vi Then, during clock phase , capacitor C1 is connected to the virtual-ground input of the op amp, as indicated in Fig. 16.35(d). Capacitor C1 is thus forced to discharge, and its previ-ous charge qC1 is transferred to C2, in the direction indicated in Fig. 16.35(d).
From the description above we see that during each clock period Tc an amount of charge qC1 = C1vi is extracted from the input source and supplied to the integrator capacitor C2.
Thus the average current flowing between the input node (IN) and the virtual-ground node (VG) is EXERCISE 16.30 In a particular filter utilizing the feedback loop of Fig. 16.29, with C1 = C2, use the results of Example 16.3 to find the expected percentage change in ω0 and Q under the conditions that (a) R3 is 2% high, (b) R4 is 2% high, (c) both R3 and R4 are 2% high, and (d) both capacitors are 2% low and both resistors are 2% high.
Ans. (a) −1%, +1%; (b) −1%, −1%; (c) −2%, 0%; (d) 0%, 0% fc fc 1 Tc ⁄ = ( ) φ1, φ1 qC1 C1 = φ2 iav C1vi Tc ----------= 16.10 Switched-capacitor Filters 1311 If Tc is sufficiently short, one can think of this process as almost continuous and define an equivalent resistance Req that is in effect present between nodes IN and VG: Thus, (16.90) Using Req we obtain an equivalent time constant for the integrator: (16.91) Thus the time constant that determines the frequency response of the filter is established by the clock period Tc and the capacitor ratio Both these parameters can be well con-trolled in an IC process. Specifically, note the dependence on capacitor ratios rather than on absolute values of capacitors. The accuracy of capacitor ratios in MOS technology can be controlled to within 0.1%.
Another point worth observing is that with a reasonable clocking frequency (such as 100 kHz) and not-too-large capacitor ratios (say, 10), one can obtain reasonably large time constants (such as 10−4 s) suitable for audio applications. Since capacitors typically occupy relatively large areas on the IC chip, one attempts to minimize their values. In this context, it is important to note that the ratio accuracies quoted earlier are obtainable with the smaller capacitor value as low as 0.1 pF.
Figure 16.35 Basic principle of the switched-capacitor filter technique. (a) Active-RC integrator.
(b) Switched-capacitor integrator. (c) Two-phase clock (nonoverlapping). (d) During C1 charges up to the current value of vi and then, during discharges into C2.
(a) (b) (c) (d) φ1, φ2, Req vi iav ⁄ ≡ Req = Tc C1 ⁄ Time constant C2Req = Tc C2 C1 ------= C2 C1.
⁄ 1312 Chapter 16 Filters and Tuned Amplifiers 16.10.2 Practical Circuits The switched-capacitor (SC) circuit in Fig. 16.35(b) realizes an inverting integrator (note the direction of charge flow through C2 in Fig. 16.35d). As we saw in Section 16.7, a two-inte-grator-loop active filter is composed of one inverting and one noninverting integrator.10 To realize a switched-capacitor biquad filter, we therefore need a pair of complementary switched-capacitor integrators. Figure 16.36(a) shows a noninverting, or positive, integrator circuit. The reader is urged to follow the operation of this circuit during the two clock phases and thus show that it operates in much the same way as the basic circuit of Fig. 16.35(b), except for a sign reversal.
In addition to realizing a noninverting integrator function, the circuit in Fig. 16.36(a) is insensitive to stray capacitances; however, we shall not explore this point any further. The interested reader is referred to Schaumann, Ghausi, and Laker (1990). By reversal of the clock phases on two of the switches, the circuit in Fig. 16.36(b) is obtained. This circuit realizes the inverting integrator function, like the circuit of Fig. 16.35(b), but is insensitive to stray capaci-tances (which the original circuit of Fig. 16.35b is not). The complementary integrators of Fig. 16.36 have become the standard building blocks in the design of switched-capacitor filters.
Let us now consider the realization of a complete biquad circuit. Figure 16.37(a) shows the active-RC, two-integrator-loop circuit studied earlier. By considering the cascade of 10 In the two-integrator loop of Fig. 16.25(b), the noninverting integrator is realized by the cascade of a Miller integrator and an inverting amplifier.
Figure 16.36 A pair of complementary stray-insensitive, switched-capacitor integrators. (a) Noninverting switched-capacitor integrator. (b) Inverting switched-capacitor integrator.
(a) (b) 1313 (b) Figure 16.37 (a) A two-integrator-loop, active-RC biquad (b) its switched-capacitor counterpart.
1314 Chapter 16 Filters and Tuned Amplifiers integrator 2 and the inverter as a positive integrator, and then simply replacing each resistor by its switched-capacitor equivalent, we obtain the circuit in Fig. 16.37(b). Ignore the damp-ing around the first integrator (i.e., the switched capacitor C5) for the time being and note that the feedback loop indeed consists of one inverting and one noninverting integrator. Then note the phasing of the switched capacitor used for damping. Reversing the phases here would convert the feedback to positive and move the poles to the right half of the s plane. On the other hand, the phasing of the feed-in switched capacitor (C6) is not that important; a reversal of phases would result only in an inversion in the sign of the function realized.
Having identified the correspondences between the active-RC biquad and the switched-capacitor biquad, we can now derive design equations. Analysis of the circuit in Fig. 16.37(a) yields (16.92) Replacing R2 and R4 with their switched-capacitor equivalent values, that is, gives ω0 of the switched-capacitor biquad as (16.93) It is usual to select the time constants of the two integrators to be equal; that is, (16.94) If, further, we select the two integrating capacitors C1 and C2 to be equal, (16.95) then (16.96) where from Eq. (16.93) (16.97) For the case of equal time constants, the Q factor of the circuit in Fig. 16.37(a) is given by . Thus the Q factor of the corresponding switched-capacitor circuit in Fig. 16.37(b) is given by (16.98) Thus C5 should be selected from (16.99) ω0 1 C1C2R3R4 -----------------------------= R3 = Tc C3 ⁄ and R4 = Tc C4 ⁄ ω0 1 T c -----C3 C2 ------C4 C1 ------= Tc C3 ------C2 Tc C4 ------C1 = C1 C2 C = = C3 C4 KC = = K ω0Tc = R5 R4 ⁄ Q Tc C5 ⁄ T c C4 ⁄ ---------------= C5 C4 Q ------KC Q --------ω0Tc C Q ----= = = 16.11 Tuned Amplifiers 1315 Finally, the center-frequency gain of the bandpass function is given by (16.100) 16.10.3 A Final Remark We have attempted to provide only an introduction to switched-capacitor filters. We have made many simplifying assumptions, the most important being the switched-capacitor– resistor equivalence (Eq. 16.90). This equivalence is correct only at fc = ∞ and is approxi-mately correct for fc f. Switched-capacitor filters are, in fact, sampled-data networks whose analysis and design can be carried out exactly using z-transform techniques. The interested reader is referred to the bibliography in Appendix G. 16.11 Tuned Amplifiers In this section, we study a special kind of frequency-selective network, the LC-tuned ampli-fier. Figure 16.38 shows the general shape of the frequency response of a tuned amplifier.
The techniques discussed apply to amplifiers with center frequencies in the range of a few hundred kilohertz to a few hundred megahertz. Tuned amplifiers find application in the radio-frequency (RF) and intermediate-frequency (IF) sections of communications receivers and in a variety of other systems. It should be noted that the tuned-amplifier response of Fig. 16.38 is similar to that of the bandpass filter discussed in earlier sections.
As indicated in Fig. 16.38, the response is characterized by the center frequency ω0, the 3-dB bandwidth B, and the skirt selectivity, which is usually measured as the ratio of the 30-dB bandwidth to the 3-dB bandwidth. In many applications, the 3-dB bandwidth is less than 5% of ω0. This narrow-band property makes possible certain approximations that can sim-plify the design process, as will be explained later.
The tuned amplifiers studied in this section are small-signal voltage amplifiers in which the transistors operate in the “class A” mode; that is, the transistors conduct at all times.
Tuned power amplifiers based on class C and other switching modes of operation are not studied in this book. (For a discussion on the classification of amplifiers, refer to Section 11.1.) 16.11.1 The Basic Principle The basic principle underlying the design of tuned amplifiers is the use of a parallel LCR cir-cuit as the load, or at the input, of a BJT or a FET amplifier. This is illustrated in Fig. 16.39 with a MOSFET amplifier having a tuned-circuit load. For simplicity, the bias details are not included. Since this circuit uses a single tuned circuit, it is known as a single-tuned Center-frequency gain C6 C5 ------Q C6 ω0TcC ----------------= = EXERCISE D16.31 Use C1 = C2 = 20 pF and design the circuit in Fig. 16.37(b) to realize a bandpass function with f0 = 10 kHz, Q = 20, and unity center-frequency gain. Use a clock frequency fc = 200 kHz.
Find the values of C3, C4, C5, and C6.
Ans. 6.283 pF; 6.283 pF; 0.314 pF; 0.314 pF 1316 Chapter 16 Filters and Tuned Amplifiers amplifier. The amplifier equivalent circuit is shown in Fig. 16.39(b). Here R denotes the par-allel equivalent of RL and the output resistance ro of the FET, and C is the parallel equivalent of CL and the FET output capacitance (usually very small). From the equivalent circuit we can write Thus the voltage gain can be expressed as (16.101) Figure 16.38 Frequency response of a tuned amplifier.
Figure 16.39 The basic principle of tuned amplifiers is illustrated using a MOSFET with a tuned-circuit load. Bias details are not shown.
(b) V o gmVi – Y L --------------gmVi – sC 1 R ⁄ 1 sL ⁄ + + -------------------------------------------= = V o V i -----gm C ------s s2 s 1 CR ⁄ ( ) 1 LC ⁄ + + ------------------------------------------------------– = 16.11 Tuned Amplifiers 1317 which is a second-order bandpass function. Thus the tuned amplifier has a center frequency of (16.102) a 3-dB bandwidth of (16.103) a Q factor of (16.104) and a center-frequency gain of (16.105) Note that the expression for the center-frequency gain could have been written by inspection; at resonance, the reactances of L and C cancel out and the impedance of the parallel LCR cir-cuit reduces to R.
16.11.2 Inductor Losses The power loss in the inductor is usually represented by a series resistance rs as shown in Fig. 16.40(a). However, rather than specifying the value of rs, the usual practice is to specify the inductor Q factor at the frequency of interest, (16.106) ω0 1 LC ⁄ = B 1 CR --------= Q ω0 B ⁄ ≡ ω0CR = V o jω0 ( ) V i jω0 ( ) -------------------gmR – = Example 16.4 It is required to design a tuned amplifier of the type shown in Fig. 16.39, having f0 = 1 MHz, 3-dB band-width = 10 kHz, and center-frequency gain = –10 V/V. The FET available has at the bias point gm = 5 mA/ V and ro = 10 kΩ. The output capacitance is negligibly small. Determine the values of RL, CL, and L.
Solution Center-frequency gain = –10 = –5R. Thus R = 2 kΩ. Since R = RL||ro, then RL = 2.5 kΩ.
Thus Since , we obtain B 2π × 104 1 CR --------= = C 1 2π 104 2 103 × × × ---------------------------------------------7958 pF = = ω0 2π × 106 1 LC ⁄ = = L 1 4π2 1012 7958 10 12 – × × × ---------------------------------------------------------------3.18 μH = = Q0 ω0L rs ----------≡ 1318 Chapter 16 Filters and Tuned Amplifiers Typically, Q0 is in the range of 50 to 200.
The analysis of a tuned amplifier is greatly simplified by representing the inductor loss by a parallel resistance Rp, as shown in Fig. 16.40(b). The relationship between Rp and Q0 can be found by writing, for the admittance of the circuit in Fig. 16.40(a), For , (16.107) Equating this to the admittance of the circuit in Fig. 16.40(b) gives (16.108) or, equivalently, (16.109) Finally, it should be noted that the coil Q factor poses an upper limit on the value of Q achieved by the tuned circuit.
(a) (b) Figure 16.40 Inductor equivalent circuits.
Y jω0 ( ) 1 rs jω0L + ----------------------= 1 jω0L ------------ 1 1 j 1 Q0 ⁄ ( ) – -----------------------------1 jω0L ------------ 1 j 1 Q0 ⁄ ( ) + 1 1 Q0 2 ⁄ ( ) + -----------------------------= = Q0 1 @ Y jω0 ( ) 1 jω0L ------------ 1 j 1 Q0 ------+ ⎝ ⎠ ⎛ ⎞ Q0 Rp ω0L ----------= Rp ω0LQ0 = EXERCISE 16.32 If the inductor in Example 16.4 has Q0 = 150, find Rp and then find the value to which RL should be changed to keep the overall Q, and hence the bandwidth, unchanged.
Ans. 3 kΩ; 15 kΩ 16.11 Tuned Amplifiers 1319 16.11.3 Use of Transformers In many cases it is found that the required value of inductance is not practical, in the sense that coils with the required inductance might not be available with the required high values of Q0. A simple solution is to use a transformer to effect an impedance change. Alternatively, a tapped coil, known as an autotransformer, can be used, as shown in Fig. 16.41. Provided the two parts of the inductor are tightly coupled, which can be achieved by winding on a fer-rite core, the transformation relationships shown hold. The result is that the tuned circuit seen between terminals 1 and 1 is equivalent to that in Fig. 16.39(b). For example, if a turns ratio n = 3 is used in the amplifier of Example 16.4, then a coil with inductance L = 9 3.18 = 28.6 μH and a capacitance C = = 884 pF will be required. Both these values are more practical than the original ones.
Figure 16.41 A tapped inductor is used as an impedance transformer to allow using a higher inductance, L, and a smaller capacitance, C.
Figure 16.42 (a) The output of a tuned amplifier is coupled to the input of another amplifier via a tapped coil. (b) An equivalent circuit. Note that the use of a tapped coil increases the effective input impedance of the second amplifier stage.
7958 9 ⁄ n 1 Ic Rin Cin R1 C1 L I (a) I R1 C1 L n2Rin Cin n2 (b) 1320 Chapter 16 Filters and Tuned Amplifiers In applications that involve coupling the output of a tuned amplifier to the input of another amplifier, the tapped coil can be used to raise the effective input resistance of the lat-ter amplifier stage. In this way, one can avoid reduction of the overall Q. This point is illus-trated in Fig. 16.42 and in the following exercises.
16.11.4 Amplifiers with Multiple Tuned Circuits The selectivity achieved with the single tuned circuit of Fig. 16.39 is not sufficient in many applications—for instance, in the IF amplifier of a radio or a TV receiver. Greater selectivity is obtained by using additional tuned stages. Figure 16.43 shows a BJT with tuned circuits at both the input and the output.11 In this circuit the bias details are shown, from which we note that biasing is quite similar to the classical arrangement employed in low-frequency, discrete-circuit design. However, to avoid the loading effect of the bias resistors RB1 and RB2 on the input tuned circuit, a radio frequency choke (RFC) is inserted in series with each resistor. Such chokes have high impedances at the frequencies of interest. The use of RFCs in biasing tuned RF amplifiers is common practice.
The analysis and design of the double-tuned amplifier of Fig. 16.43 is complicated by the Miller effect12 due to capacitance Cμ. Since the load is not simply resistive, as was the case in the amplifiers studied in Section 9.5.2, the Miller impedance at the input will be com-plex. This reflected impedance will cause detuning of the input circuit as well as “skewing” of the response of the input circuit. Needless to say, the coupling introduced by Cμ makes tun-ing (or aligning) the amplifier quite difficult. Worse still, the capacitor Cμ can cause oscilla-tions to occur [see Gray and Searle (1969) and Problem 16.75].
Methods exist for neutralizing the effect of Cμ, using additional circuits arranged to feed back a current equal and opposite to that through Cμ. An alternative, and preferred, approach is to use circuit configurations that do not suffer from the Miller effect. These are discussed later. Before leaving this section, however, we wish to point out that circuits of the type shown in Fig. 16.43 are usually designed utilizing the y-parameter model of the BJT EXERCISES D16.33 Consider the circuit in Fig. 16.42(a), first without tapping the coil. Let L = 5 μH and assume that R1 is fixed at 1 kΩ. We wish to design a tuned amplifier with f0 = 455 kHz and a 3-dB bandwidth of 10 kHz [this is the intermediate frequency (IF) amplifier of an AM radio]. If the BJT has Rin = 1 kΩ and Cin = 200 pF, find the actual bandwidth obtained and the required value of C1.
Ans. 13 kHz; 24.27 nF D16.34 Since the bandwidth realized in Exercise 16.33 is greater than desired, find an alternative design utilizing a tapped coil as in Fig. 16.42(a). Find the value of n that allows the specifications to be just met. Also find the new required value of C1 and the current gain at resonance. Assume that at the bias point the BJT has gm = 40 mA/V.
Ans. 1.36; 24.36 nF; 19.1 A/A Ic I ⁄ 11 Note that because the input circuit is a parallel resonant circuit, an input current source (rather than voltage source) signal is utilized.
12 Here we use “Miller effect” to refer to the effect of the feedback capacitance Cμ in reflecting back an input impedance that is a function of the amplifier load impedance.
16.11 Tuned Amplifiers 1321 (see Appendix C). This is done because here, in view of the fact that Cμ plays a significant role, the y-parameter model makes the analysis simpler (in comparison to that using the hybrid-π model). Also, the y parameters can easily be measured at the particular frequency of interest, ω0. For narrow-band amplifiers, the assumption is usually made that the y param-eters remain approximately constant over the passband.
16.11.5 The Cascode and the CC−CB Cascade From our study of amplifier frequency response in Chapter 9, we know that two amplifier configurations do not suffer from the Miller effect. These are the cascode configuration and the common-collector, common-base cascade. Figure 16.44 shows tuned amplifiers based on these two configurations. The CC−CB cascade is usually preferred in IC implementations because its differential structure makes it suitable for IC biasing techniques. (Note that the biasing details of the cascode circuit are not shown in Fig. 16.44a. Biasing can be done using arrangements similar to those discussed in earlier chapters.) 16.11.6 Synchronous Tuning In the design of a tuned amplifier with multiple tuned circuits, the question of the frequency to which each circuit should be tuned arises. The objective, of course, is for the overall response to exhibit high passband flatness and skirt selectivity. To investigate this question, we shall assume that the overall response is the product of the individual responses: in other words, that the stages do not interact. This can easily be achieved using circuits such as those in Fig. 16.44.
Consider first the case of N identical resonant circuits, known as the synchronously tuned case. Figure 16.45 shows the response of an individual stage and that of the cascade.
Observe the bandwidth “shrinkage” of the overall response. The 3-dB bandwidth B of the overall amplifier is related to that of the individual tuned circuits, by (see Problem 16.77) Figure 16.43 A BJT amplifier with tuned circuits at the input and the output.
ω0 Q, ⁄ 1322 Chapter 16 Filters and Tuned Amplifiers (16.110) The factor is known as the bandwidth-shrinkage factor. Given B and N, we can use Eq. (16.110) to determine the bandwidth required of the individual stages, . Figure 16.44 Two tuned-amplifier configurations that do not suffer from the Miller effect: (a) cascode and (b) common-collector, common-base cascade. (Note that bias details of the cascode circuit are not shown.) (a) (b) B ω0 Q ------ 21 N ⁄ 1 – = 21 N ⁄ 1 – ω0 Q ⁄ EXERCISE D16.35 Consider the design of an IF amplifier for an FM radio receiver. Using two synchronously tuned stages with f0 = 10.7 MHz, find the 3-dB bandwidth of each stage so that the overall bandwidth is 200 kHz. Using 3-μH inductors find C and R for each stage.
Ans. 310.8 kHz; 73.7 pF; 6.95 kΩ 16.11 Tuned Amplifiers 1323 16.11.7 Stagger-Tuning A much better overall response is obtained by stagger-tuning the individual stages, as illus-trated in Fig. 16.46. Stagger-tuned amplifiers are usually designed so that the overall response exhibits maximal flatness around the center frequency f0. Such a response can be obtained by transforming the response of a maximally flat (Butterworth) low-pass filter up the frequency axis to ω0. We show here how this can be done.
Figure 16.45 Frequency response of a synchronously tuned amplifier.
Figure 16.46 Stagger-tuning the individual resonant circuits can result in an overall response with a pass-band flatter than that obtained with synchronous tuning (Fig. 16.45).
T (dB) B 3 dB Response of individual stages Overall response 0 Q 0 0 1324 Chapter 16 Filters and Tuned Amplifiers The transfer function of a second-order bandpass filter can be expressed in terms of its poles as (16.111) For a narrow-band filter, Q 1, and for values of s in the neighborhood of +jω0 (see Fig. 16.47b), the second factor in the denominator is approximately (s + jω0 2s). Hence Eq. (16.111) can be approximated in the neighborhood of jω0 by (16.112) This is known as the narrow-band approximation.13 Note that the magnitude response, for s = jω, has a peak value of a1 at ω = ω0, as expected.
Now consider a first-order low-pass network with a single pole at (we use p to denote the complex frequency variable for the low-pass filter). Its transfer function is (16.113) where K is a constant. Comparing Eqs. (16.112) and (16.113) we note that they are identical for p = s − jω0 or, equivalently, s = p + jω0 (16.114) This result implies that the response of the second-order bandpass filter in the neighborhood of its center frequency s = jω0 is identical to the response of a first-order low-pass filter with a pole at in the neighborhood of p = 0. Thus the bandpass response can be obtained by shifting the pole of the low-pass prototype and adding the complex-conjugate pole, as illustrated in Fig. 16.47(b). This is called a lowpass-to-bandpass transformation for narrow-band filters.
The transformation p = s − jω0 can be applied to low-pass filters of order greater than one. For instance, we can transform a maximally flat, second-order low-pass filter to obtain a maximally flat bandpass filter. If the 3-dB bandwidth of the band-pass filter is to be B rad/s, then the low-pass filter should have a 3-dB frequency (and thus a pole frequency) of rad/s, as illustrated in Fig. 16.48. The resulting fourth-order bandpass filter will be a stagger-tuned one, with its two tuned circuits (refer to Fig. 16.48) having (16.115) 13 The bandpass response is geometrically symmetrical around the center frequency ω0. That is, each pair of frequencies ω1 and ω2 at which the magnitude response is equal are related by ω1ω2 = ω2 0 . For high Q, the symmetry becomes almost arithmetic for frequencies close to ω0. That is, two frequencies with the same magnitude response are almost equally spaced from ω0. The same is true for higher-order bandpass filters designed using the transformation presented in this section.
T s ( ) a1s s ω0 2Q -------jω0 1 1 4Q2 ----------– – + ⎝ ⎠ ⎛ ⎞s ω0 2Q -------jω0 1 1 4Q2 ----------– + + ⎝ ⎠ ⎛ ⎞ -------------------------------------------------------------------------------------------------------------------------= T s ( ) a1 2 ⁄ s ω0 2Q ⁄ jω0 – + -----------------------------------------a1 2 ⁄ s jω0 – ( ) ω0 2Q ⁄ + ----------------------------------------------= Q ω ⁄ 0 p = ω0 – 2Q ⁄ T p ( ) K p ω0 2Q ⁄ + ---------------------------= ω0 2Q ⁄ – ( ) (Q = 1 2 ⁄ ) B 2 ⁄ ( ) ω01 = ω0 B 2 2 ----------+ B1 = B 2 -------Q1 2ω0 B --------------16.11 Tuned Amplifiers 1325 (16.116) Note that for the overall response to have a normalized center-frequency gain of unity, the individual responses have to have equal center-frequency gains of , as shown in Fig. 16.48(d). Figure 16.47 Obtaining a second-order narrow-band bandpass filter by transforming a first-order low-pass filter. (a) Pole of the first-order filter in the p plane. (b) Applying the transformation s = p + jω0 and adding a complex-conjugate pole results in the poles of the second-order bandpass filter. (c) Magnitude response of the first-order low-pass filter. (d) Magnitude response of the second-order bandpass filter.
Im(p) Re(p) Low-pass filter p plane 0 0 2Q s p j0 (a) Bandpass filter s plane 0 j0 j j0 0 2Q 0 Q (b) s p j0 0 2Q 0.707 0 Im(p) 1 T (c) 0 Q 0.707 0 1 T 0 (d) ω02 = ω0 B 2 2 ----------– B2 = B 2 -------Q2 2ω0 B --------------= 2 1326 Chapter 16 Filters and Tuned Amplifiers Figure 16.48 Obtaining the poles and the frequency response of a fourth-order stagger-tuned, narrow-band bandpass amplifier by transforming a second-order low-pass, maximally flat response.
Im(p) Re(p) Low-pass filter 0 s p j0 B 2 45 p plane (a) 0 j B 2 45 45 B 2 j0 B 2 45 45 B 2 j B 2 2 j 2 2 B 0 2 2 B 0 j0 s plane Bandpass filter (b) s p j0 2 (c) B 0 Im(p) T 0.707 1.000 B 0.707 1.000 0 B 2 2 0 0 B Individual responses Overall response 2 2 1.414 (d) 16.11 Tuned Amplifiers 1327 EXERCISES D16.36 A stagger-tuned design for the IF amplifier specified in Exercise 16.35 is required. Find f01, B1, f02, and B2. Also give the value of C and R for each of the two stages. (Recall that 3-μH inductors are to be used.) Ans. 10.77 MHz; 141.4 kHz; 10.63 MHz; 141.4 kHz; 72.8 pF; 15.5 kΩ; 74.7 pF; 15.1 kΩ 16.37 Using the fact that the voltage gain at resonance is proportional to the value of R, find the ratio of the gain at 10.7 MHz of the stagger-tuned amplifier designed in Exercise 16.36 and the synchro-nously tuned amplifier designed in Exercise 16.35. (Hint: For the stagger-tuned amplifier, note that the gain at ω0 is equal to the product of the gains of the individual stages at their 3-dB fre-quencies.) Ans. 2.42 Summary A filter is a linear two-port network with a transfer func-tion For physical frequencies, the filter transmission is expressed as T(jω) = The magnitude of transmission can be expressed in deci-bels using either the gain function or the attenuation function .
The transmission characteristics of a filter are specified in terms of the edges of the passband(s) and the stop-band(s); the maximum allowed variation in passband transmission, Amax (dB); and the minimum attenuation required in the stopband, Amin (dB). In some applica-tions, the phase characteristics are also specified.
The filter transfer function can be expressed as the ratio of two polynomials in s; the degree of the denominator polynomial, N, is the filter order. The N roots of the denominator polynomial are the poles (natural modes).
To obtain a highly selective response, the poles are com-plex and occur in conjugate pairs (except for one real pole when N is odd). The zeros are placed on the jω axis in the stopband(s) including ω = 0 and ω = ∞.
The Butterworth filter approximation provides a low-pass response that is maximally flat at ω = 0. The transmission decreases monotonically as ω increases, reaching 0 (infinite attenuation) at ω = ∞, where all N transmission zeros lie. Eq. (16.11) gives where is given by Eq. (16.14) and the order N is determined using Eq. (16.15). The poles are found using the graphi-cal construction of Fig. 16.10, and the transfer function is given by Eq. (16.16).
The Chebyshev filter approximation provides a low-pass response that is equiripple in the passband with the trans-mission decreasing monotonically in the stopband. All the transmission zeros are at s = ∞. Eq. (16.18) gives in the passband and Eq. (16.19) gives in the stopband, where is given by Eq. (16.21). The order N can be determined using Eq. (16.22). The poles are given by Eq. (16.23) and the transfer function by Eq. (16.24).
Figures 16.13 and 16.14 provide a summary of first-order filter functions and their realizations. Figure 16.16 provides the characteristics of seven spe-cial second-order filtering functions.
The second-order LCR resonator of Fig. 16.17(a) real-izes a pair of complex-conjugate poles with ω0 = and Q = ω0CR. This resonator can be used to realize the various special second-order filtering func-tions, as shown in Fig. 16.18. By replacing the inductor of an LCR resonator with a sim-ulated inductance obtained using the Antoniou circuit of Fig. 16.20(a), the op amp–RC resonator of Fig. 16.21(b) is obtained. This resonator can be used to realize the various second-order filter functions as shown in Fig. 16.22. The design equations for these circuits are given in Table 16.1.
T s ( ) V o s ( ) Vi s ( ).
⁄ = T jω ( ) ejφ ω ( ).
G ω ( ) 20 log T ≡ A ω ( ) –20 log T ≡ T , T T 1 LC ⁄ 1328 Chapter 16 Filters and Trusted Amplifiers PROBLEMS Computer Simulation Problems Problems involving design are marked with D through-out the text. As well, problems are marked with asterisks to describe their degree of difficulty. Difficult problems are marked with an asterisk (); more difficult problems with two asterisks (); and very challenging and/or time-con-suming problems with three asterisks ().
Section 16.1: Filter Transmission, Types and Specification 16.1 The transfer function of a first-order low-pass filter (such as that realized by an RC circuit) can be expressed as where ω0 is the 3-dB frequency of the filter. Give in table form the values of , φ, G, and A at ω = 0, 0.5ω0, ω0, 2ω0, 5ω0, 10ω0, and 100ω0.
16.2 A filter has the transfer function [(s + 1) (s2 + s + 1)]. Show that and find an expres-sion for its phase response φ(ω). Calculate the values of and φ for ω = 0.1, 1, and 10 rad/s and then find the output corresponding to each of the following input signals: (a) 2 sin 0.1t (volts) (b) 2 sin t (volts) (c) 2 sin 10t (volts) 16.3 For the filter whose magnitude response is sketched (as the colored curve) in Fig. 16.3, find at ω = 0, ω = ωp, and ω = ωs. Amax = 0.5 dB, and Amin = 40 dB. D 16.4 A low-pass filter is required to pass all signals within its passband, extending from 0 to 4 kHz, with a trans-mission variation of at most 10% (i.e., the ratio of the maxi-mum to minimum transmission in the passband should not exceed 1.1). The transmission in the stopband, which extends from 5 kHz to ∞, should not exceed 0.1% of the maximum passband transmission. What are the values of Amax, Amin, and the selectivity factor for this filter?
16.5 A low-pass filter is specified to have Amax = 1 dB and Amin = 10 dB. It is found that these specifications can T s ( ) ω0 s ω0 + ( ) ⁄ , = T T s ( ) 1 ⁄ = T 1 ω6 + = T T Biquads based on the two-integrator-loop topology are the most versatile and popular second-order filter real-izations. There are two varieties: the KHN circuit of Fig. 16.24(a), which realizes the LP, BP, and HP func-tions simultaneously and can be combined with the out-put summing amplifier of Fig. 16.28(b) to realize the notch and all-pass functions; and the Tow–Thomas cir-cuit of Fig. 16.25(b), which realizes the BP and LP func-tions simultaneously. Feedforward can be applied to the Tow–Thomas circuit to obtain the circuit of Fig. 16.26, which can be designed to realize any of the second-order functions (see Table 16.2).
Single-amplifier biquads (SABs) are obtained by plac-ing a bridged-T network in the negative-feedback path of an op amp. If the op amp is ideal, the poles realized are at the same locations as the zeros of the RC net-work. The complementary transformation can be applied to the feedback loop to obtain another feed-back loop having identical poles. Different transmis-sion zeros are realized by feeding the input signal to circuit nodes that are connected to ground. SABs are economic in their use of op amps but are sensitive to the op-amp nonidealities and are thus limited to low-Q applications (Q ≤ 10).
The classical sensitivity function is a very useful tool in investigating how tolerant a filter circuit is to the unavoidable inaccuracies in component values and to the nonidealities of the op amps.
Switched-capacitor (SC) filters are based on the principle that a capacitor C, periodically switched between two cir-cuit nodes at a high rate, fc, is equivalent to a resistance R = 1/Cfc connecting the two circuit nodes. SC filters can be fabricated in monolithic form using CMOS IC technology.
Tuned amplifiers utilize LC-tuned circuits as loads, or at the input, of transistor amplifiers. They are used in the design of the RF tuner and the IF amplifier of communi-cation receivers. The cascode and the CC–CB cascade configurations are frequently used in the design of tuned amplifiers. Stagger-tuning the individual tuned circuits results in a flatter passband response (in comparison to that obtained with all the tuned circuits synchronously tuned).
Sx y ∂y y ⁄ ∂x x ⁄ ------------= Problems 1329 CHAPTER 16 PROB LEMS be just met with a single-time-constant RC circuit having a time constant of 1 s and a dc transmission of unity. What must ωp and ωs of this filter be? What is the selectivity factor? 16.6 Sketch transmission specifications for a high-pass fil-ter having a passband defined by f ≥ 2 kHz and a stopband defined by f ≤ 1 kHz. Amax = 0.5 dB, and Amin = 50 dB.
16.7 Sketch transmission specifications for a bandstop filter that is required to pass signals over the bands 0 ≤ f ≤ 10 kHz and 20 kHz ≤ f ≤ ∞ with Amax of 1 dB. The stopband extends from f = 12 kHz to f = 16 kHz, with a minimum required attenuation of 40 dB. Section 16.2: The Filter Transfer Function 16.8 Consider a fifth-order filter whose poles are all at a radial distance from the origin of 103 rad/s. One pair of complex conjugate poles is at 18° angles from the jω axis, and the other pair is at 54° angles. Give the transfer func-tion in each of the following cases: (a) The transmission zeros are all at s = ∞ and the dc gain is unity.
(b) The transmission zeros are all at s = 0 and the high-frequency gain is unity.
What type of filter results in each case?
16.9 A third-order low-pass filter has transmission zeros at ω = 2 rad/s and ω = ∞. Its natural modes are at s = −1 and s = −0.5 ± j0.8. The dc gain is unity. Find T(s).
16.10 Find the order N and the form of T(s) of a bandpass filter having transmission zeros as follows: one at ω = 0, one at ω = 103 rad/s, one at 3 103 rad/s, one at 6 103 rad/s, and one at ω = ∞. If this filter has a monotonically decreasing passband transmission with a peak at the center frequency of 2 103 rad/s, and equiripple response in the stopbands, sketch the shape of its .
16.11 Analyze the RLC network of Fig. P16.11 to deter-mine its transfer function Vo(s)/Vi(s) and hence its poles and zeros. (Hint: Begin the analysis at the output and work your way back to the input.) Figure P16.11 Section 16.3: Butterworth and Chebyshev Filters D 16.12 Determine the order N of the Butterworth filter for which Amax = 1 dB, Amin ≥ 20 dB, and the selectivity ratio What is the actual value of minimum stopband attenuation realized? If Amin is to be exactly 20 dB, to what value can Amax be reduced? 16.13 Calculate the value of attenuation obtained at a frequency 1.6 times the 3-dB frequency of a seventh-order Butterworth filter.
16.14 Find the natural modes of a Butterworth filter with a 1-dB bandwidth of 103 rad/s and N = 5.
D 16.15 Design a Butterworth filter that meets the follow-ing low-pass specifications: fp = 10 kHz, Amax = 2 dB, fs = 15 kHz, and Amin = 15 dB. Find N, the natural modes, and T(s). What is the attenuation provided at 20 kHz?
16.16 Sketch for a seventh-order low-pass Chebyshev filter with ωp = 1 rad/s and Amax = 1 dB. Use Eq. (16.18) to determine the values of ω at which = 1 and the values of ω at which . Indicate these values on your sketch. Use Eq. (16.19) to determine at ω = 2 rad/s, and indicate this point on your sketch. For large values of ω, at what rate (in dB/octave) does the transmission decrease?
16.17 Contrast the attenuation provided by a fifth-order Chebyshev filter at ωs = 2ωp to that provided by a Butter-worth filter of equal order. For both, Amax = 1 dB. Sketch for both filters on the same axes.
D 16.18 It is required to design a low-pass filter to meet the following specifications: fp = 3.4 kHz, Amax = 1 dB, fs = 4 kHz, Amin = 35 dB.
(a) Find the required order of Chebyshev filter. What is the excess (above 35 dB) stopband attenuation obtained?
(b) Find the poles and the transfer function.
Section 16.4: First-Order and Second-Order Filter Functions D 16.19 Use the information displayed in Fig. 16.13 to design a first-order op amp–RC low-pass filter having a 3-dB frequency of 10 kHz, a dc gain magnitude of 10, and an input resistance of 10 kΩ.
D 16.20 Use the information given in Fig. 16.13 to design a first-order op amp–RC high-pass filter with a 3-dB fre-quency of 100 Hz, a high-frequency input resistance of 100 kΩ, and a high-frequency gain magnitude of unity.
D 16.21 Use the information given in Fig. 16.13 to design a first-order op amp–RC spectrum-shaping network with a transmission zero frequency of 1 kHz, a pole frequency T 2 H 1 Vo(s) 1 F 1 1 F Vi(s) ωs ωp ⁄ = 1.3.
T T T = 1 1 e2 + ⁄ T T 1330 Chapter 16 Filters and Tuned Amplifiers CHAPTER 16 PR OBLEM S of 100 kHz, and a dc gain magnitude of unity. The low-frequency input resistance is to be 1 kΩ. What is the high-fre-quency gain that results? Sketch the magnitude of the trans-fer function versus frequency. D 16.22 By cascading a first-order op amp–RC low-pass circuit with a first-order op amp–RC high-pass circuit, one can design a wideband bandpass filter. Provide such a design for the case in which the midband gain is 12 dB and the 3-dB bandwidth extends from 100 Hz to 10 kHz. Select appropri-ate component values under the constraint that no resistors higher than 100 kΩ are to be used and that the input resis-tance is to be as high as possible.
D 16.23 Derive T(s) for the op amp–RC circuit in Fig.
16.14. We wish to use this circuit as a variable phase shifter by adjusting R. If the input signal frequency is 104 rad/s and if C = 10 nF, find the values of R required to obtain phase shifts of –30°, –60°, –90°, –120°, and –150°.
16.24 Show that by interchanging R and C in the op amp– RC circuit of Fig. 16.14, the resulting phase shift covers the range 0 to 180° (with 0° at high frequencies and 180° at low frequencies).
16.25 Use the information in Fig. 16.16(a) to obtain the transfer function of a second-order low-pass filter with ω0 = 103 rad/s, Q = 1, and dc gain = 1. At what frequency does peak? What is the peak transmission?
D 16.26 Use the information in Fig. 16.16(a) to obtain the transfer function of a second-order low-pass filter that just meets the specifications defined in Fig. 16.3 with ωp = 1 rad/s and Amax = 3 dB. Note that there are two possible solutions. For each, find ω0 and Q. Also, if ωs = 2 rad/s, find the value of Amin obtained in each case.
D 16.27 Use two first-order op amp–RC all-pass cir-cuits in cascade to design a circuit that provides a set of three-phase 60-Hz voltages, each separated by 120° and equal in magnitude, as shown in the phasor diagram of Fig.
P16.27. These voltages simulate those used in three-phase power transmission systems. Use 1-μF capacitors. 16.28 Use the information given in Fig. 16.16(b) to find the transfer function of a second-order high-pass filter with natu-ral modes at and a high-frequency gain of unity.
D 16.29 (a) Show that |T| of a second-order bandpass function is geometrically symmetrical around the center frequency ω0. That is, the members of each pair of frequencies ω1 and ω 2 for which |T( jω1)| = |T( jω2)| are related by ω1ω2 = ω2 0 . (b) Find the transfer function of the second-order bandpass filter that meets specifications of the form in Fig. 16.4 where ωp1 = 8100 rad/s, ωp2 = 10,000 rad/s, and Amax = 1 dB. If ωs1 = 3000 rad/s find Amin and ωs2.
D 16.30 Use the result of Exercise 16.15 to find the trans-fer function of a notch filter that is required to eliminate a bothersome interference of 60-Hz frequency. Since the fre-quency of the interference is not stable, the filter should be designed to provide attenuation ≥20 dB over a 6-Hz band centered around 60 Hz. The dc transmission of the filter is to be unity.
16.31 Consider a second-order all-pass circuit in which errors in the component values result in the frequency of the zeros being slightly lower than that of the poles.
Roughly sketch the expected |T|. Repeat for the case of the frequency of the zeros slightly higher than the frequency of the poles.
16.32 Consider a second-order all-pass filter in which errors in the component values result in the Q factor of the zeros being greater than the Q factor of the poles. Roughly sketch the expected |T|. Repeat for the case of the Q factor of the zeros lower than the Q factor of the poles.
Section 16.5: The Second-Order LCR Resonator D 16.33 Design the LCR resonator of Fig. 16.17(a) to obtain natural modes with ω0 = 104 rad/s and Q = 2. Use R = 10 kΩ.
16.34 For the LCR resonator of Fig. 16.17(a), find the change in ω0 that results from (a) increasing L by 1% (b) increasing C by 1% (c) increasing R by 1% 16.35 Derive an expression for of the high-pass circuit in Fig. 16.18(c).
D 16.36 Use the circuit of Fig. 16.18(b) to design a low-pass filter with ω0 = 105 rad/s and Q = . Utilize a 0.01-μF capacitor.
D 16.37 Modify the bandpass circuit of Fig. 16.18(d) to change its center-frequency gain from 1 to 0.5 without changing ω0 or Q.
Figure P16.27 T −0.5 j 3 2 ⁄ ± V o s ( ) Vi s ( ) ⁄ 1 2 ⁄ Problems 1331 CHAPTER 16 PROB LEMS 16.38 Consider the LCR resonator of Fig. 16.17(a) with node x disconnected from ground and connected to an input signal source Vx, node y disconnected from ground and connected to another input signal source Vy, and node z dis-connected from ground and connected to a third input sig-nal source Vz. Use superposition to find the voltage that develops across the resonator, Vo, in terms of Vx, Vy, and Vz.
16.39 Consider the notch circuit shown in Fig. 16.18(i).
For what ratio of L1 to L2 does the notch occur at 0.9ω0?
For this case, what is the magnitude of the transmission at frequencies ω0? At frequencies ω0?
Section 16.6: Second-Order Active Filters Based on Inductor Replacement D 16.40 Design the circuit of Fig. 16.20 (utilizing suit-able component values) to realize an inductance of (a) 10 H, (b) 1 H, and (c) 0.1 H.
16.41 Starting from first principles and assuming ideal op amps, derive the transfer function of the circuit in Fig.
16.22(a).
D 16.42 It is required to design a fifth-order Butterworth filter having a 3-dB bandwidth of 104 rad/s and a unity dc gain. Use a cascade of two circuits of the type shown in Fig. 16.22(a) and a first-order op amp–RC circuit of the type shown in Fig. 16.13(a). Select appropriate component values.
D 16.43 Design the circuit of Fig. 16.22(e) to realize an LPN function with f0 = 4 kHz, fn = 5 kHz, Q = 10, and a unity dc gain. Select C4 = 10 nF.
D 16.44 Design the all-pass circuit of Fig. 16.22(g) to provide a phase shift of 180 at f = 1 kHz and to have Q = 1.
Use 1-nF capacitors.
16.45 Consider the Antoniou circuit of Fig. 16.20(a) with R5 eliminated, a capacitor C6 connected between node 1 and ground, and a voltage source V2 connected to node 2.
Show that the input impedance seen by V2 is R2/ s2C4C6R1R3. How does this impedance behave for physical frequencies (s = jω)? (This impedance is known as a fre-quency-dependent negative resistance, or FDNR.) D 16.46 Using the transfer function of the LPN filter, given in Table 16.1, derive the design equations also given.
D 16.47 Using the transfer function of the HPN filter, given in Table 16.1, derive the design equations also given.
D 16.48 It is required to design a third-order low-pass filter whose |T| is equiripple in both the passband and the stopband (in the manner shown in Fig. 16.3, except that the response shown is for N = 5). The filter passband extends from ω = 0 to ω = 1 rad/s, and the passband transmission varies between 1 and 0.9. The stopband edge is at ω = 1.2 rad/s. The following transfer function was obtained using filter design tables: The actual filter realized is to have ωp = 104 rad/s.
(a) Obtain the transfer function of the actual filter by replacing s by .
(b) Realize this filter as the cascade connection of a first-order LP op amp–RC circuit of the type shown in Fig.
16.13(a) and a second-order LPN circuit of the type shown in Fig. 16.22(e). Each section is to have a dc gain of unity. Select appropriate component values. (Note: A filter with an equiripple response in both the passband and the stopband is known as an elliptic filter.) Section 16.7: Second-Order Active Filters Based on the Two-Integrator-Loop Topology D 16.49 Design the KHN circuit of Fig. 16.24(a) to real-ize a bandpass filter with a center frequency of 1 kHz and a 3-dB bandwidth of 50 Hz. Use 10-nF capacitors. Give the complete circuit and specify all component values. What value of center-frequency gain is obtained?
D 16.50 (a) Using the KHN biquad with the output sum-ming amplifier of Fig. 16.24(b), show that an all-pass func-tion is realized by selecting RL = RH = . Also show that the flat gain obtained is (b) Design the all-pass circuit to obtain ω0 = 104 rad/s, Q = 2, and flat gain = 10. Select appropriate component values.
D 16.51 Consider a notch filter with ωn = ω0 realized by using the KHN biquad with an output summing amplifier. If the summing resistors used have 1% tolerances, what is the worst-case percentage deviation between ωn and ω0?
D 16.52 Design the circuit of Fig. 16.26 to realize a low-pass notch filter with ω0 = 104 rad/s, Q = 10, dc gain = 1, and ωn = 1.2 × 104 rad/s. Use C = 10 nF and r = 20 kΩ..
D 16.53 In the all-pass realization using the circuit of Fig. 16.26, which component(s) does one need to trim to adjust (a) only ωz and (b) only Qz?
D 16.54 Repeat Problem 16.48 using the Tow–Thomas biquad of Fig. 16.26 to realize the second-order section in the cascade.
Section 16.8: Single-Amplifier Biquadratic Active Filters D 16.55 Design the circuit of Fig. 16.29 to realize a pair of poles with ω0 = 104 rad/s and Q = . Use C1 = C2 = 1 nF.
T s ( ) 0.4508 s2 1.6996 + ( ) s 0.7294 + ( ) s2 s0.2786 1.0504 + + ( ) ----------------------------------------------------------------------------------------= s 104 ⁄ RB Q ⁄ KRF RH ⁄ .
1 2 ⁄ 1332 Chapter 16 Filters and Tuned Amplifiers CHAPTER 16 PR OBLEM S 16.56 Consider the bridged-T network of Fig. 16.28(a) with R3 = R4 = R and C1 = C2 = C, and denote CR = τ. Find the zeros and poles of the bridged-T network. If the net-work is placed in the negative-feedback path of an ideal infinite-gain op amp, as in Fig. 16.29, find the poles of the closed-loop amplifier.
16.57 Consider the bridged-T network of Fig. 16.28(b) with R1 = R2 = R, C4 = C, and C3 = Let the network be placed in the negative-feedback path of an infinite-gain op amp and let C4 be disconnected from ground and con-nected to the input signal source Vi. Analyze the resulting circuit to determine its transfer function Vo(s)/Vi(s), where Vo(s) is the voltage at the op-amp output. Show that the circuit realized is a bandpass filter and find its ω0, Q, and the center-frequency gain.
D 16.58 Consider the bandpass circuit shown in Fig. 16.30a. Let C1 = C2 = C, R3 = R, R4 = , CR = and α = 1. Disconnect the positive input terminal of the op amp from ground and apply Vi through a voltage divider R1, R2 to the positive input terminal as well as through R4/α as before. Analyze the circuit to find its trans-fer function . Find the ratio so that the circuit realizes (a) an all-pass function and (b) a notch function.
Assume the op amp to be ideal.
D 16.59 Derive the transfer function of the circuit in Fig. 16.33(b) assuming the op amp to be ideal. Thus show that the circuit realizes a high-pass function. What is the high-frequency gain of the circuit? Design the circuit for a maxi-mally flat response with a 3-dB frequency of 103 rad/s. Use C1 = C2 = 10 nF. (Hint: For a maximally flat response, and ω3dB = ω0.) D 16.60 Design a fifth-order Butterworth low-pass filter with a 3-dB bandwidth of 5 kHz and a dc gain of unity using the cascade connection of two Sallen-and-Key cir-cuits (Fig. 16.34c) and a first-order section (Fig. 16.13a).
Use a 10-kΩ value for all resistors.
16.61 The process of obtaining the complement of a trans-fer function by interchanging input and ground, as illus-trated in Fig. 16.31, applies to any general network (not just RC networks as shown). Show that if the network n is a bandpass with a center-frequency gain of unity, then the complement obtained is a notch. Verify this by using the RLC circuits of Fig. 16.18(d) and (e).
Section 16.9: Sensitivity 16.62 Evaluate the sensitivities of ω0 and Q relative to R, L, and C of the bandpass circuit in Fig. 16.18(d).
16.63 Verify the following sensitivity identities: (a) If y = uv, then .
(b) If y = u/v, then .
(c) If y = ku, where k is a constant, then .
(d) If y = un, where n is a constant, then .
(e) If y = f1(u) and u = f2(x), then .
16.64 For the high-pass filter of Fig. 16.33(b), what are the sensitivities of ω0 and Q to amplifier gain A?
16.65 For the feedback loop of Fig. 16.34(a), use the expressions in Eqs. (16.77) and (16.78) to determine the sensitivities of ω0 and Q relative to all passive components for the design in which R1 = R2.
16.66 For the op amp−RC resonator of Fig. 16.21(b), use the expressions for ω0 and Q given in the top row of Table 16.1 to determine the sensitivities of ω0 and Q to all resistors and capacitors. Section 16.10: Switched-Capacitor Filters 16.67 For the switched-capacitor input circuit of Fig. 16.35(b), in which a clock frequency of 100 kHz is used, what input resistances correspond to capacitance C1 values of 1 pF and 10 pF?
16.68 For a dc voltage of 1 V applied to the input of the cir-cuit of Fig. 16.35(b), in which C1 is 1 pF, what charge is transferred for each cycle of the two-phase clock? For a 100-kHz clock, what is the average current drawn from the input source? For a feedback capacitance of 10 pF, what change would you expect in the output for each cycle of the clock? For an amplifier that saturates at ±10 V and the feedback capacitor initially discharged, how many clock cycles would it take to saturate the amplifier? What is the average slope of the staircase output voltage produced?
D 16.69 Repeat Exercise 16.31 for a clock frequency of 400 kHz.
D 16.70 Repeat Exercise 16.31 for Q = 40.
D 16.71 Design the circuit of Fig. 16.37(b) to realize, at the output of the second (noninverting) integrator, a maximally flat low-pass function with ω3dB = 104 rad/s and unity dc gain.
Use a clock frequency fc = 100 kHz and select C1 = C2 = 10 pF. Give the values of C3, C4, C5, and C6. (Hint: For a max-imally flat response, and ω3dB = ω0.) Section 16.11: Tuned Amplifiers 16.72 A voltage signal source with a resistance Rs = 10 kΩ is connected to the input of a common-emitter BJT amplifier.
Between base and emitter is connected a tuned circuit with C 16 ⁄ .
R 4Q2 ⁄ 2Q ω0 ⁄ , V o Vi ⁄ R2 R1 ⁄ Q 1 2 ⁄ = Sx y Sx u Sx v + = Sx y Sx u Sx v – = Sx y Sx u = Sx y nSx u = Sx y Su y.Sx u = Q = 1 2 ⁄ Problems 1333 CHAPTER 16 PROB LEMS L = 1 μH and C = 200 pF. The transistor is biased at 1 mA and has β = 200, Cπ = 10 pF, and Cμ = 1 pF. The transistor load is a resistance of 5 kΩ.. Find ω0, Q, the 3-dB bandwidth, and the center-frequency gain of this single-tuned amplifier.
16.73 A coil having an inductance of 10 μH is intended for applications around 1-MHz frequency. Its Q is specified to be 200. Find the equivalent parallel resistance Rp. What is the value of the capacitor required to produce reso-nance at 1 MHz? What additional parallel resistance is required to produce a 3-dB bandwidth of 10 kHz?
16.74 An inductance of 36 μH is resonated with a 1000-pF capacitor. If the inductor is tapped at one-third of its turns and a 1-kΩ resistor is connected across the one-third part, find f0 and Q of the resonator.
16.75 Consider a common-emitter transistor amplifier loaded with an inductance L. Ignoring ro and rx, show that for , the amplifier input admittance is given by (Note: The real part of the input admittance can be nega-tive. This can lead to oscillations.) 16.76 (a) Substituting s = jω in the transfer function T(s) of a second-order bandpass filter (see Fig. 16.16c), find . For ω in the vicinity of ω0 [i.e., ω = ω0 + δω = ω0 , where so that ], show that, for 1, (b) Use the result obtained in (a) to show that the 3-dB bandwidth B, of N synchronously tuned sections connected in cascade, is 16.77 (a) Using the fact that for 1 the second-order bandpass response in the neighborhood of ω0 is the same as the response of a first-order low-pass with 3-dB frequency of , show that the bandpass response at is given by (b) Use the relationship derived in (a) together with Eq.
(16.110) to show that a bandpass amplifier with a 3-dB bandwidth B, designed using N synchronously tuned stages, has an overall transfer function given by (c) Use the relationship derived in (b) to find the attenua-tion (in decibels) obtained at a bandwidth 2B for N = 1 to 5.
Also find the ratio of the 30-dB bandwidth to the 3-dB bandwidth for N = 1 to 5.
16.78 This problem investigates the selectivity of maxi-mally flat stagger-tuned amplifiers derived in the manner illustrated in Fig. 16.48.
(a) The low-pass maximally flat (Butterworth) filter hav-ing a 3-dB bandwidth and order N has the magnitude response where Ω = Im(p) is the frequency in the low-pass domain.
(This relationship can be obtained using the information provided in Section 16.3 on Butterworth filters.) Use this expression to obtain for the corresponding bandpass filter at ω = ω0 + δω, where , the relationship (b) Use the transfer function in (a) to find the attenuation (in decibels) obtained at a bandwidth of 2B for N = 1 to 5.
Also find the ratio of the 30-dB bandwidth to the 3-dB bandwidth for N = 1 to 5.
16.79 Consider a sixth-order, stagger-tuned bandpass amplifier with center frequency ω0 and 3-dB bandwidth B.
The poles are to be obtained by shifting those of the third-order maximally flat low-pass filter, given in Fig. 16.10(c).
For each of the three resonant circuits, find ω0, the 3-dB bandwidth, and Q. ωCμ 1 ωL ⁄ Yin 1 rπ -----ω2CμLgm – ⎝ ⎠ ⎛ ⎞ jω Cπ Cμ + ( ) + T jω ( ) 1 δω + ω ⁄ 0 ( ) δω ω ⁄ 0 1 ω2 ω0 2 (1 2δω ω ⁄ 0) + Q T jω ( ) T jω0 ( ) 1 4Q2(δω ω ⁄ 0)2 + -------------------------------------------------B ω0 Q ⁄ ( ) 21 N ⁄ 1 – = Q (ω 0 2Q ⁄ ) ω = ω0 δω, for δω + ω0, T jω ( ) T jω0 ( ) 1 4Q2(δω ω ⁄ 0)2 + -------------------------------------------------T jω ( ) overall T jω0 ( ) overall 1 4 21 N ⁄ 1 – ( ) δω B ⁄ ( )2 + [ ] N 2 ⁄ --------------------------------------------------------------------------= B 2 ⁄ T 1 1 Ω B 2 ⁄ ----------⎝ ⎠ ⎛ ⎞2N + = δω ω0 T 1 1 δω B 2 ⁄ ----------⎝ ⎠ ⎛ ⎞2N + = CHAPTER 17 Signal Generators and Waveform-Shaping Circuits Introduction 1335 17.1 Basic Principles of Sinusoidal Oscillators 1336 17.2 Op Amp–RC Oscillator Circuits 1342 17.3 LC and Crystal Oscillators 1349 17.4 Bistable Multivibrators 1355 17.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators 1363 17.6 Generation of a Standardized Pulse—The Monostable Multivibrator 1367 17.7 Integrated-Circuit Timers 1369 17.8 Nonlinear Waveform-Shaping Circuits 1374 17.9 Precision Rectifier Circuits 1378 Summary 1386 Problems 1387 1335 IN THIS CHAPTER YOU WILL LEARN 1. That an oscillator circuit that generates sine waves can be implemented by connecting a frequency-selective network in the positive-feedback path of an amplifier.
2. The conditions under which sustained oscillations are obtained and the frequency of the oscillations.
3. How to design nonlinear circuits to control the amplitude of the sine wave obtained in a linear oscillator.
4. A variety of circuits for implementing a linear sine-wave oscillator.
5. How op amps can be combined with resistors and capacitors to imple-ment precision multivibrator circuits.
6. How a bistable circuit can be connected in a feedback loop with an op-amp integrator to implement a generator of square and triangular waveforms.
7. The application of one of the most popular IC chips of all time, the 555 timer, in the design of generators of pulse and square waveforms.
8. How a triangular waveform can be shaped by a nonlinear circuit to pro-vide a sine waveform.
9. How op amps and diodes can be combined to implement a variety of high-precision rectifier circuits.
Introduction In the design of electronic systems, the need frequently arises for signals having prescribed standard waveforms, for example, sinusoidal, square, triangular, or pulse. Systems in which standard signals are required include computer and control systems where clock pulses are needed for, among other things, timing; communication systems where signals of a variety of waveforms are utilized as information carriers; and test and measurement systems where signals, again of a variety of waveforms, are employed for testing and characterizing elec-tronic devices and circuits. In this chapter we study signal-generator circuits.
1336 Chapter 17 Signal Generators and Waveform-Shaping Circuits There are two distinctly different approaches for the generation of sinusoids, perhaps the most commonly used of the standard waveforms. The first approach, studied in Sections 17.1 to 17.3, employs a positive-feedback loop consisting of an amplifier and an RC or LC frequency-selective network. The amplitude of the generated sine waves is limited, or set, using a nonlinear mechanism, implemented either with a separate circuit or using the nonlinear-ities of the amplifying device itself. In spite of this, these circuits, which generate sine waves utilizing resonance phenomena, are known as linear oscillators. The name clearly distinguishes them from the circuits that generate sinusoids by way of the second approach. In these circuits, a sine wave is obtained by appropriately shaping a triangular waveform. We study waveform-shaping circuits in Section 17.8, following the study of triangular-waveform generators.
Circuits that generate square, triangular, pulse (etc.) waveforms, called nonlinear oscillators or function generators, employ circuit building blocks known as multivibrators.
There are three types of multivibrator: the bistable (Section 17.4), the astable (Section 17.5), and the monostable (Section 17.6). The multivibrator circuits presented in this chapter employ op amps and are intended for precision analog applications. Bistable and monostable multivibrator circuits using digital logic gates were studied in Chapter 15.
A general and versatile scheme for the generation of square and triangular waveforms is obtained by connecting a bistable multivibrator and an op-amp integrator in a feedback loop (Section 17.5). Similar results can be obtained using a commercially available versatile IC chip, the 555 timer (Section 17.7). The chapter includes also a study of precision circuits that implement the rectifier functions introduced in Chapter 4. The circuits studied here (Section 17.9), however, are intended for applications that demand precision, such as in instrumenta-tion systems, including waveform generation.
17.1 Basic Principles of Sinusoidal Oscillators In this section, we study the basic principles of the design of linear sine-wave oscillators. In spite of the name linear oscillator, some form of nonlinearity has to be employed to provide control of the amplitude of the output sine wave. In fact, all oscillators are essentially non-linear circuits. This complicates the task of analysis and design of oscillators: No longer is one able to apply transform (s-plane) methods directly. Nevertheless, techniques have been developed by which the design of sinusoidal oscillators can be performed in two steps: The first step is a linear one, and frequency-domain methods of feedback circuit analysis can be readily employed. Subsequently, a nonlinear mechanism for amplitude control can be provided.
17.1.1 The Oscillator Feedback Loop The basic structure of a sinusoidal oscillator consists of an amplifier and a frequency-selective network connected in a positive-feedback loop, such as that shown in block diagram form in Fig. 17.1. Although no input signal will be present in an actual oscillator circuit, we include an input signal here to help explain the principle of operation. It is impor-tant to note that unlike the negative-feedback loop of Fig. 10.1, here the feedback signal xf is summed with a positive sign. Thus the gain-with-feedback is given by (17.1) where we note the negative sign in the denominator.
Af s ( ) A s ( ) 1 A s ( )β s ( ) – -------------------------------= 17.1 Basic Principles of Sinusoidal Oscillators 1337 According to the definition of loop gain in Chapter 10, the loop gain of the circuit in Fig. 17.1 is −A(s)β(s). However, for our purposes here it is more convenient to drop the minus sign and define the loop gain L(s) as L(s) ≡ A(s)β(s) (17.2) The characteristic equation thus becomes 1 − L(s) = 0 (17.3) Note that this new definition of loop gain1 corresponds directly to the actual gain seen around the feedback loop of Fig. 17.1.
17.1.2 The Oscillation Criterion If at a specific frequency f0 the loop gain Aβ is equal to unity, it follows from Eq. (17.1) that Af will be infinite. That is, at this frequency the circuit will have a finite output for zero input signal. Such a circuit is by definition an oscillator. Thus the condition for the feedback loop of Fig. 17.1 to provide sinusoidal oscillations of frequency ω0 is L( jω0) ≡ A( jω0)β( jω0) = 1 (17.4) That is, at ω0 the phase of the loop gain should be zero and the magnitude of the loop gain should be unity. This is known as the Barkhausen criterion. Note that for the circuit to oscillate at one frequency, the oscillation criterion should be satisfied only at one frequency (i.e., ω0); otherwise the resulting waveform will not be a simple sinusoid.
An intuitive feeling for the Barkhausen criterion can be gained by considering once more the feedback loop of Fig. 17.1. For this loop to produce and sustain an output xo with no input applied (xs = 0), the feedback signal xf xf = βxo should be sufficiently large that when multiplied by A it produces xo, that is, Axf = xo Figure 17.1 The basic structure of a sinusoidal oscillator. A positive-feedback loop is formed by an ampli-fier and a frequency-selective network. In an actual oscillator circuit, no input signal will be present; here an input signal xs is employed to help explain the principle of operation.
1 For both the negative-feedback loop in Fig. 10.1 and the positive-feedback loop in Fig. 17.1, the loop gain L = Aβ. However, the negative sign with which the feedback signal is summed in the negative-feedback loop results in the characteristic equation being 1 + L = 0. In the positive-feedback loop, the feedback signal is summed with a positive sign, thus resulting in the characteristic equation 1 − L = 0.
Amplifier A 1338 Chapter 17 Signal Generators and Waveform-Shaping Circuits that is, Aβxo = xo which results in Aβ = 1 It should be noted that the frequency of oscillation ω0 is determined solely by the phase characteristics of the feedback loop; the loop oscillates at the frequency for which the phase is zero. It follows that the stability of the frequency of oscillation will be determined by the manner in which the phase φ(ω) of the feedback loop varies with frequency. A “steep” func-tion φ(ω) will result in a more stable frequency. This can be seen if one imagines a change in phase Δφ due to a change in one of the circuit components. If dφ/dω is large, the resulting change in ω0 will be small, as illustrated in Fig. 17.2.
An alternative approach to the study of oscillator circuits consists of examining the circuit poles, which are the roots of the characteristic equation (Eq. 17.3). For the circuit to pro-duce sustained oscillations at a frequency ω0 the characteristic equation has to have roots at s = ±jω0. Thus 1 − A(s)β(s) should have a factor of the form s2 + ω 2 0.
Figure 17.2 Dependence of the oscillator-frequency stability on the slope of the phase response. A steep phase response (i.e., large dφ/dω) results in a small Δω0 for a given change in phase Δφ [resulting from a change (due, for example, to temperature) in a circuit component].
EXERCISES 17.1 Consider a sinusoidal oscillator formed of an amplifier with a gain of 2 and a second-order bandpass filter. Find the pole frequency and the center-frequency gain of the filter needed to produce sustained oscillations at 1 kHz.
Ans. 1 kHz; 0.5 17.1 Basic Principles of Sinusoidal Oscillators 1339 17.1.3 Nonlinear Amplitude Control The oscillation condition, the Barkhausen criterion, just discussed, guarantees sustained oscillations in a mathematical sense. It is well known, however, that the parameters of any physical system cannot be maintained constant for any length of time. In other words, suppose we work hard to make Aβ = 1 at ω = ω0, and then the temperature changes and Aβ becomes slightly less than unity. Obviously, oscillations will cease in this case. Conversely, if Aβ exceeds unity, oscillations will grow in amplitude. We therefore need a mechanism for forcing Aβ to remain equal to unity at the desired value of output amplitude. This task is accomplished by providing a nonlinear circuit for gain control.
Basically, the function of the gain-control mechanism is as follows: First, to ensure that oscillations will start, one designs the circuit such that Aβ is slightly greater than unity. This corresponds to designing the circuit so that the poles are in the right half of the s plane. Thus as the power supply is turned on, oscillations will grow in amplitude. When the amplitude reaches the desired level, the nonlinear network comes into action and causes the loop gain to be reduced to exactly unity. In other words, the poles will be “pulled back” to the jω axis.
This action will cause the circuit to sustain oscillations at this desired amplitude. If, for some reason, the loop gain is reduced below unity, the amplitude of the sine wave will diminish.
This will be detected by the nonlinear network, which will cause the loop gain to increase to exactly unity.
As will be seen, there are two basic approaches to the implementation of the nonlinear amplitude-stabilization mechanism. The first approach makes use of a limiter circuit (see Chapter 4). Oscillations are allowed to grow until the amplitude reaches the level to which the limiter is set. When the limiter comes into operation, the amplitude remains constant.
Obviously, the limiter should be “soft” to minimize nonlinear distortion. Such distortion, however, is reduced by the filtering action of the frequency-selective network in the feed-back loop. In fact, in one of the oscillator circuits studied in Section 17.2, the sine waves are hard limited, and the resulting square waves are applied to a bandpass filter present in the feedback loop. The “purity” of the output sine waves will be a function of the selectivity of this filter. That is, the higher the Q of the filter, the less the harmonic content of the sine-wave output.
The other mechanism for amplitude control utilizes an element whose resistance can be controlled by the amplitude of the output sinusoid. By placing this element in the feed-back circuit so that its resistance determines the loop gain, the circuit can be designed to ensure that the loop gain reaches unity at the desired output amplitude. Diodes, or JFETs operated in the triode region,2 are commonly employed to implement the controlled-resistance element. 17.1.4 A Popular Limiter Circuit for Amplitude Control We conclude this section by presenting a limiter circuit that is frequently employed for the amplitude control of op-amp oscillators, as well as in a variety of other applications. The cir-cuit is more precise and versatile than those presented in Chapter 4.
The limiter circuit is shown in Fig. 17.3(a), and its transfer characteristic is depicted in Fig. 17.3(b). To see how the transfer characteristic is obtained, consider first the case of a small (close to zero) input signal vI and a small output voltage vO, so that vA is positive and vB is negative. It can be easily seen that both diodes D1 and D2 will be off. Thus all of the 2 We have not studied JFETs in this book. However, the disk accompanying the book includes material on JFETs and JFET circuits. The same material can also be found on the book’s website.
1340 Chapter 17 Signal Generators and Waveform-Shaping Circuits input current flows through the feedback resistance Rf, and the output voltage is given by (17.5) This is the linear portion of the limiter transfer characteristic in Fig. 17.3(b). We now can use superposition to find the voltages at nodes A and B in terms of ±V and vO as (17.6) Figure 17.3 (a) A popular limiter circuit. (b) Transfer characteristic of the limiter circuit; L− and L+ are given by Eqs. (17.8) and (17.9), respectively. (c) When Rf is removed, the limiter turns into a comparator with the characteristic shown.
R2 D1 D2 R3 V vI R4 vO Rf R1 B A V R5 (a) Slope Slope vO R1 vI Rf L L 0 Slope R3 ( ) R1 Rf // R4 ( ) R1 Rf // (b) vO R1 vI R4 L L 0 Slope R3 R1 Slope (c) vI R1 ⁄ vO Rf R1 ⁄ ( )vI – = vA V R3 R2 R3 + -----------------vO R2 R2 R3 + -----------------+ = 17.1 Basic Principles of Sinusoidal Oscillators 1341 (17.7) As vI goes positive, vO goes negative (Eq. 17.5), and we see from Eq. (17.7) that vB will become more negative, thus keeping D2 off. Equation (17.6) shows, however, that vA becomes less positive. Then, if we continue to increase vI, a negative value of vO will be reached at which vA becomes −0.7 V or so and diode D1 conducts. If we use the constant-voltage-drop model for D1 and denote the voltage drop VD, the value of vO at which D1 conducts can be found from Eq. (17.6). This is the negative limiting level, which we denote L−, (17.8) The corresponding value of vI can be found by dividing L− by the limiter gain . If vI is increased beyond this value, more current is injected into D1, and vA remains at approxi-mately −VD. Thus the current through R2 remains constant, and the additional diode current flows through R3. Thus R3 appears in effect in parallel with Rf, and the incremental gain (ignoring the diode resistance) is −(Rf ||R3) ⁄R1. To make the slope of the transfer characteris-tic small in the limiting region, a low value should be selected for R3.
The transfer characteristic for negative vI can be found in a manner identical to that just employed. It can be easily seen that for negative vI, diode D2 plays an identical role to that played by diode D1 for positive vI. We can use Eq. (17.7) to find the positive limit-ing level L+ (17.9) and the slope of the transfer characteristic in the positive limiting region is −(Rf ||R4) ⁄R1. We thus see that the circuit of Fig. 17.3(a) functions as a soft limiter, with the limiting levels L+ and L−, and the limiting gains independently adjustable by the selection of appropriate resistor values.
Finally, we note that increasing Rf results in a higher gain in the linear region while keeping L+ and L− unchanged. In the limit, removing Rf altogether results in the transfer characteristic of Fig. 17.3(c), which is that of a comparator. That is, the circuit compares vI with the comparator reference value of 0 V: vI > 0 results in vO L−, and vI < 0 yields vO L+.
vB V – R4 R4 R5 + -----------------vO R5 R4 R5 + -----------------+ = L− V – R3 R2 -----V D 1 R3 R2 -----+ ⎝ ⎠ ⎛ ⎞ – = Rf R1 ⁄ – L+ V R4 R5 -----V D 1 R4 R5 -----+ ⎝ ⎠ ⎛ ⎞ + = EXERCISES 17.2 For the circuit of Fig. 17.3(a) with V = 15 V, R1 = 30 kΩ, Rf = 60 kΩ, R2 = R5 = 9 kΩ, and R3 = R4 = 3 kΩ, find the limiting levels and the value of vI at which the limiting levels are reached. Also determine the limiter gain and the slope of the transfer characteristic in the positive and negative limiting regions. Assume that VD = 0.7 V.
Ans. ±5.93 V; ±2.97 V; −2; −0.095 1342 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.2 Op Amp–RC Oscillator Circuits In this section we shall study some practical oscillator circuits utilizing op amps and RC net-works.
17.2.1 The Wien-Bridge Oscillator One of the simplest oscillator circuits is based on the Wien bridge. Figure 17.4 shows a Wien-bridge oscillator without the nonlinear gain-control network. The circuit consists of an op amp connected in the noninverting configuration, with a closed-loop gain of 1 + .
In the feedback path of this positive-gain amplifier an RC network is connected. The loop gain can be easily obtained by multiplying the transfer function Va(s) ⁄ Vo(s) of the feedback network by the amplifier gain, Thus, (17.10) Substituting results in (17.11) The loop gain will be a real number (i.e., the phase will be zero) at one frequency given by That is, (17.12) Figure 17.4 A Wien-bridge oscillator without amplitude stabilization.
R2 R1 ⁄ L s ( ) 1 R2 R1 -----+ Zp Zp Zs + ----------------= 1 R2 R1 ⁄ + 1 ZsYp + -------------------------= L s ( ) 1 R2 R1 ⁄ + 3 sCR 1 sCR ⁄ + + --------------------------------------------= s = jω L jω ( ) 1 R2 R1 ⁄ + 3 j ωCR 1 ωCR ⁄ – ( ) + ------------------------------------------------------= ω0CR 1 ω0CR --------------= ω0 = 1 C ⁄ R 17.2 Op Amp–RC Oscillator Circuits 1343 To obtain sustained oscillations at this frequency, one should set the magnitude of the loop gain to unity. This can be achieved by selecting (17.13) To ensure that oscillations will start, one chooses slightly greater than 2. The reader can easily verify that if , where is a small number, the roots of the charac-teristic equation will be in the right half of the s plane.
The amplitude of oscillation can be determined and stabilized by using a nonlinear con-trol network. Two different implementations of the amplitude-controlling function are shown in Figs. 17.5 and 17.6. The circuit in Fig. 17.5 employs a symmetrical feedback limiter of the type studied in Section 17.1.3. It is formed by diodes D1 and D2 together with resistors R3, R4, R5, and R6. The limiter operates in the following manner: At the positive peak of the out-put voltage vO, the voltage at node b will exceed the voltage v1 (which is about ), and diode D2 conducts. This will clamp the positive peak to a value determined by R5, R6, and the negative power supply. The value of the positive output peak can be calculated by setting and writing a node equation at node b while neglecting the current through D2. Similarly, the negative peak of the output sine wave will be clamped to the value that causes diode D1 to conduct. The value of the negative peak can be determined by setting and writing an equation at node a while neglecting the current through D1.
Finally, note that to obtain a symmetrical output waveform, R3 is chosen equal to R6, and R4 equal to R5.
Figure 17.5 A Wien-bridge oscillator with a limiter used for amplitude control.
R1 R2 Rs Rp Cs Cp 16 nF D2 D1 D2 D2 R2 R1 ⁄ = 2 R2 R1 ⁄ R2 R1 ⁄ = 2 δ + δ 1 L s ( ) – 0 = 1 3 ---vO vb = v1 VD2 + va = v1 V D1 – 1344 Chapter 17 Signal Generators and Waveform-Shaping Circuits The circuit of Fig. 17.6 employs an inexpensive implementation of the parameter-variation mechanism of amplitude control. Potentiometer P is adjusted until oscillations just start to grow. As the oscillations grow, the diodes start to conduct, causing the effective resis-tance between a and b to decrease. Equilibrium will be reached at the output amplitude that causes the loop gain to be exactly unity. The output amplitude can be varied by adjusting potentiometer P.
As indicated in Fig. 17.6, the output is taken at point b rather than at the op-amp output terminal because the signal at b has lower distortion than that at a. To appreciate this point, note that the voltage at b is proportional to the voltage at the op-amp input terminals and that the latter is a filtered (by the RC network) version of the voltage at node a. Node b, however, is a high-impedance node, and a buffer will be needed if a load is to be connected.
17.2.2 The Phase-Shift Oscillator The basic structure of the phase-shift oscillator is shown in Fig. 17.7. It consists of a negative-gain amplifier (−K) with a three-section (third-order) RC ladder network in the feedback. The circuit will oscillate at the frequency for which the phase shift of the RC network is 180°. Only at this frequency will the total phase shift around the loop be 0° or 360°. Here we should note that the reason for using a three-section RC network is that three is the minimum number of sections (i.e., lowest order) that is capable of producing a 180° phase shift at a finite frequency.
For oscillations to be sustained, the value of K should be equal to the inverse of the mag-nitude of the RC network transfer function at the frequency of oscillation. However, to ensure that oscillations start, the value of K has to be chosen slightly higher than the value that satisfies the unity-loop-gain condition. Oscillations will then grow in magnitude until limited by some nonlinear control mechanism.
Figure 17.8 shows a practical phase-shift oscillator with a feedback limiter, consisting of diodes D1 and D2 and resistors R1, R2, R3, and R4 for amplitude stabilization. To start EXERCISES 17.3 For the circuit in Fig. 17.5: (a) Disregarding the limiter circuit, find the location of the closed-loop poles. (b) Find the frequency of oscillation. (c) With the limiter in place, find the amplitude of the out-put sine wave (assume that the diode drop is 0.7 V).
Ans. (a) (105/16)(0.015 ± j); (b) 1 kHz; (c) 21.36 V (peak-to-peak) EXERCISES 17.4 For the circuit in Fig. 17.6 find the following: (a) The setting of potentiometer P at which oscillations just start. (b) The frequency of oscillation.
Ans. (a) 20 kΩ to ground; (b) 1 kHz 17.2 Op Amp–RC Oscillator Circuits 1345 oscillations, Rf has to be made slightly greater than the minimum required value. Although the circuit stabilizes more rapidly and provides sine waves with more stable amplitude, if Rf is made much larger than this minimum, the price paid is an increased output distortion.
Figure 17.6 A Wien-bridge oscillator with an alternative method for amplitude stabilization.
Figure 17.7 A phase-shift oscillator.
D1 D2 Rs Rp Cs Cp 16 nF P K EXERCISES 17.5 Consider the circuit of Fig. 17.8 without the limiter. Break the feedback loop at X and find the loop gain . To do this, it is easier to start at the output and work backward, finding the various currents and voltages, and eventually Vx in terms of Vo.
Ans. 17.6 Use the expression derived in Exercise 17.5 to find the frequency of oscillation f0 and the minimum required value of Rf for oscillations to start in the circuit of Fig. 17.8.
Ans. ω0 = 1/ CR; Rf ≥12 R; f0 = 574.3 Hz; Rf = 120 kΩ Aβ V o j ω ( ) V x j ω ( ) ⁄ ≡ ω2C2RRf 4 j 3ωCR 1 ωCR ⁄ – ( ) + ---------------------------------------------------------3 1346 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.2.3 The Quadrature Oscillator The quadrature oscillator is based on the two-integrator loop studied in Section 16.7. As an active filter, the loop is damped to locate the poles in the left half of the s plane. Here, no such damping will be used, since we wish to locate the poles on the axis to provide sus-tained oscillations. In fact, to ensure that oscillations start, the poles are initially located in the right half-plane and then “pulled back” by the nonlinear gain control.
Figure 17.9 shows a practical quadrature oscillator. Amplifier 1 is connected as an invert-ing Miller integrator with a limiter in the feedback for amplitude control. Amplifier 2 is con-nected as a noninverting integrator (thus replacing the cascade connection of the Miller integrator and the inverter in the two-integrator loop of Fig. 16.25b). To understand the opera-tion of this noninverting integrator, consider the equivalent circuit shown in Fig. 17.9(b). Here, we have replaced the integrator input voltage vO1 and the series resistance 2R by the Norton equivalent composed of a current source and a parallel resistance 2R. Now, since where v is the voltage at the input of op amp 2, the current through Rf will be in the direction from output to input. Thus Rf gives rise to a negative input resistance, −Rf , as indicated in the equivalent circuit of Fig. 17.9(b). Nominally, Rf is made equal to 2R, and thus −Rf cancels 2R, and at the input we are left with a current source feeding a capacitor C. The result is that and vO2 = 2v = .
That is, for the circuit functions as a perfect noninverting integrator. If, however, Rf is made smaller than 2R, a net negative resistance appears in parallel with C.
Figure 17.8 A practical phase-shift oscillator with a limiter for amplitude stabilization.
D1 D2 jω vO1 2R ⁄ vO2 = 2v, 2v v – ( ) Rf ⁄ = v Rf ⁄ vO1 2R ⁄ v = 1 C ----∫0 t vO1 2R -------- t d 1 CR ---------∫0 tvO1 t d Rf = 2R, 17.2 Op Amp–RC Oscillator Circuits 1347 Returning to the oscillator circuit in Fig. 17.9(a), we note that the resistance Rf in the positive-feedback path of op amp 2 is made variable, with a nominal value of 2R. Decreasing the value of Rf moves the poles to the right half-plane (Problem 17.19) and ensures that the oscillations start. Too much positive feedback, although it results in better amplitude stabil-ity, also results in higher output distortion (because the limiter has to operate “harder”). In this regard, note that the output vO2 will be “purer” than vO1 because of the filtering action provided by the second integrator on the peak-limited output of the first integrator. If we disregard the limiter and break the loop at X, the loop gain can be obtained as (17.14) Thus the loop will oscillate at frequency given by (17.15) Finally, it should be pointed out that the name quadrature oscillator is used because the circuit provides two sinusoids with 90° phase difference. This is the case because is the integral of There are many applications for which quadrature sinusoids are required.
17.2.4 The Active-Filter-Tuned Oscillator The last oscillator circuit that we shall discuss is quite simple both in principle and in design. Nevertheless, the approach is general and versatile and can result in high-quality (i.e., low-distortion) output sine waves. The basic principle is illustrated in Fig. 17.10. The Figure 17.9 (a) A quadrature-oscillator circuit. (b) Equivalent circuit at the input of op amp 2.
(a) D1 D2 v 2 vO1 2R v vO2 2 2R C Rf (b) L s ( ) V o2 V x --------≡ 1 s2C2R2 -----------------– = ω0, ω0 1 CR --------= vO2 vO1.
1348 Chapter 17 Signal Generators and Waveform-Shaping Circuits circuit consists of a high-Q bandpass filter connected in a positive-feedback loop with a hard limiter. To understand how this circuit works, assume that oscillations have already started. The output of the bandpass filter will be a sine wave whose frequency is equal to the center frequency of the filter, f0. The sine-wave signal v1 is fed to the limiter, which produces at its output a square wave whose levels are determined by the limiting levels and whose frequency is f0. The square wave in turn is fed to the bandpass filter, which filters out the harmonics and provides a sinusoidal output v1 at the fundamental frequency f0.
Obviously, the purity of the output sine wave will be a direct function of the selectivity (or Q factor) of the bandpass filter.
The simplicity of this approach to oscillator design should be apparent. We have indepen-dent control of frequency and amplitude as well as of distortion of the output sinusoid. Any filter circuit with positive gain can be used to implement the bandpass filter. The frequency stability of the oscillator will be directly determined by the frequency stability of the band-pass-filter circuit. Also, a variety of limiter circuits (see Chapter 4) with different degrees of sophistication can be used to implement the limiter block.
Figure 17.11 shows one possible implementation of the active-filter-tuned oscillator. This circuit uses a variation on the bandpass circuit based on the Antoniou inductance-simulation circuit (see Fig. 16.22c). Here resistor R2 and capacitor C4 are interchanged. This makes the output of the lower op amp directly proportional to (in fact, twice as large as) the voltage across the resonator, and we can therefore dispense with the buffer amplifier K. The limiter used is a very simple one consisting of a resistance R1 and two diodes.
Figure 17.10 Block diagram of the active-filter-tuned oscillator.
f0 V V v1 v2 EXERCISES 17.7 Using find the value of R such that the circuit of Fig. 17.11 produces 1-kHz sine waves. If the diode drop is 0.7 V, find the peak-to-peak amplitude of the output sine wave. (Hint: A square wave with peak-to-peak amplitude of V volts has a fundamental component with volts peak-to-peak amplitude.) Ans. 3.6 V C = 16 nF, 4V π ⁄ 10 kΩ; 17.3 LC and Crystal Oscillators 1349 17.2.5 A Final Remark The op amp–RC oscillator circuits studied are useful for operation in the range 10 Hz to 100 kHz (or perhaps 1 MHz at most). Whereas the lower frequency limit is dictated by the size of passive components required, the upper limit is governed by the frequency-response and slew-rate limitations of op amps. For higher frequencies, circuits that employ transistors together with LC-tuned circuits or crystals are frequently used.3 These are discussed in Section 17.3.
17.3 LC and Crystal Oscillators Oscillators utilizing transistors (FETs or BJTs), with LC-tuned circuits or crystals as feed-back elements, are used in the frequency range of 100 kHz to hundreds of megahertz. They exhibit higher Q than the RC types. However, LC oscillators are difficult to tune over wide ranges, and crystal oscillators operate at a single frequency.
17.3.1 LC-Tuned Oscillators Figure 17.12 shows two commonly used configurations of LC-tuned oscillators. They are known as the Colpitts oscillator and the Hartley oscillator. Both utilize a parallel LC cir-cuit connected between collector and base (or between drain and gate if a FET is used) with a fraction of the tuned-circuit voltage fed to the emitter (the source in a FET). This Figure 17.11 A practical implementation of the active-filter-tuned oscillator.
3 Of course, transistors can be used in place of the op amps in the circuits just studied. At higher frequencies, however, better results are obtained with LC-tuned circuits and crystals.
A2 A1 D1 D1 D2 D2 1350 Chapter 17 Signal Generators and Waveform-Shaping Circuits feedback is achieved by way of a capacitive divider in the Colpitts oscillator and by way of an inductive divider in the Hartley circuit. To focus attention on the oscillator’s structure, the bias details are not shown. In both circuits, the resistor R models the combination of the losses of the inductors, the load resistance of the oscillator, and the out-put resistance of the transistor. If the frequency of operation is sufficiently low that we can neglect the transistor capaci-tances, the frequency of oscillation will be determined by the resonance frequency of the parallel-tuned circuit (also known as a tank circuit because it behaves as a reservoir for energy storage). Thus for the Colpitts oscillator we have (17.16) and for the Hartley oscillator we have (17.17) The ratio or determines the feedback factor and thus must be adjusted in con-junction with the transistor gain to ensure that oscillations will start. To determine the oscil-lation condition for the Colpitts oscillator, we replace the transistor with its equivalent circuit, as shown in Fig. 17.13. To simplify the analysis, we have neglected the transistor capacitance ( for a FET). Capacitance (Cgs for a FET), although not shown, can be considered to be a part of C2. The input resistance (infinite for a FET) has also been neglected, assuming that at the frequency of oscillation @ . Finally, as men-tioned earlier, the resistance R includes ro of the transistor.
To find the loop gain, we break the loop at the transistor base, apply an input voltage , and find the returned voltage that appears across the input terminals of the transistor. We then equate the loop gain to unity. An alternative approach is to analyze the circuit and elim-inate all current and voltage variables, and thus obtain one equation that governs circuit operation. Oscillations will start if this equation is satisfied. Thus the resulting equation will give us the conditions for oscillation.
Figure 17.12 Two commonly used configurations of LC-tuned oscillators: (a) Colpitts and (b) Hartley.
(a) (b) ω0 1 L C1C2 C1 C2 + ------------------⎝ ⎠ ⎛ ⎞ = ω0 1 L1 L2 + ( )C ⁄ = L1 L2 ⁄ C1 C2 ⁄ Cμ Cgd Cπ rπ rπ 1 ωC2 ⁄ ( ) Vπ 17.3 LC and Crystal Oscillators 1351 A node equation at the transistor collector (node C) in the circuit of Fig. 17.13 yields Since (oscillations have started), it can be eliminated, and the equation can be rear-ranged in the form (17.18) Substituting gives (17.19) For oscillations to start, both the real and imaginary parts must be zero. Equating the imagi-nary part to zero gives the frequency of oscillation as (17.20) which is the resonance frequency of the tank circuit, as anticipated.4 Equating the real part to zero together with Eq. (17.20) gives (17.21) which has a simple physical interpretation: For sustained oscillations, the magnitude of the gain from base to collector (gmR) must be equal to the inverse of the voltage ratio provided by the capacitive divider, which from Fig. 17.12(a) can be seen to be Of course, for oscillations to start, the loop gain must be made greater than unity, a condition that can be stated in the equivalent form (17.22) Figure 17.13 Equivalent circuit of the Colpitts oscillator of Fig. 17.12(a). To simplify the analysis, Cμ and rπ are neglected. We can consider Cπ to be part of C2, and we can include ro in R.
4 If is taken into account, the frequency of oscillation can be shown to shift slightly from the value given by Eq. (17.20).
Vc R C L sC2 C1 LC2 gm V V V ( ) 1 s2 V sC2 V C2 sC2Vπ gmVπ 1 R ---s C1 + ⎝ ⎠ ⎛ ⎞1 s 2LC2 + ( )Vπ 0 = + + Vπ 0 ≠ s 3LC1C2 s 2 LC2 R ⁄ ( ) s C1 C2 + ( ) gm 1 R ---+ ⎝ ⎠ ⎛ ⎞ + + + 0 = s = jω gm 1 R ---ω 2LC2 R ----------------– + ⎝ ⎠ ⎛ ⎞ j ω C1 C2 + ( ) ω 3LC1C2 – [ ] + 0 = ω0 1 L C1C2 C1 C2 + ------------------⎝ ⎠ ⎛ ⎞ = rπ C2 C1 ⁄ gmR = veb vce ⁄ = C1 C2 ⁄ .
gmR C2 C ⁄ 1 > 1352 Chapter 17 Signal Generators and Waveform-Shaping Circuits As oscillations grow in amplitude, the transistor’s nonlinear characteristics reduce the effec-tive value of gm and, correspondingly, reduce the loop gain to unity, thus sustaining the oscil-lations.
Analysis similar to the foregoing can be carried out for the Hartley circuit (see later: Exercise 17.8). At high frequencies, more accurate transistor models must be used. Alterna-tively, the y parameters of the transistor can be measured at the intended frequency and the analysis can then be carried out using the y-parameter model (see Appendix C). This is usually simpler and more accurate, especially at frequencies above about 30% of the transistor fT.
As an example of a practical LC oscillator, we show in Fig. 17.14 the circuit of a Colpitts oscillator, complete with bias details. Here the radio-frequency choke (RFC) provides a high reactance at but a low dc resistance.
Finally, a few words are in order on the mechanism that determines the amplitude of oscillations in the LC-tuned oscillators discussed above. Unlike the op-amp oscillators that incorporate special amplitude-control circuitry, LC-tuned oscillators utilize the nonlinear iC– vBE characteristics of the BJT (the iD–vGS characteristics of the FET) for amplitude control.
Thus these LC-tuned oscillators are known as self-limiting oscillators. Specifically, as the oscillations grow in amplitude, the effective gain of the transistor is reduced below its small-signal value. Eventually, an amplitude is reached at which the effective gain is reduced to the point that the Barkhausen criterion is satisfied exactly. The amplitude then remains constant at this value.
Reliance on the nonlinear characteristics of the BJT (or the FET) implies that the collector (drain) current waveform will be nonlinearly distorted. Nevertheless, the output voltage signal will still be a sinusoid of high purity because of the filtering action of the LC-tuned circuit. Detailed analysis of amplitude control, which makes use of nonlinear-circuit techniques, is beyond the scope of this book.
Figure 17.14 Complete circuit for a Colpitts oscillator.
ω0, ω0 17.3 LC and Crystal Oscillators 1353 17.3.2 Crystal Oscillators A piezoelectric crystal, such as quartz, exhibits electromechanical-resonance characteristics that are very stable (with time and temperature) and highly selective (having very high Q factors). The circuit symbol of a crystal is shown in Fig. 17.15(a), and its equivalent circuit model is given in Fig. 17.15(b). The resonance properties are characterized by a large induc-tance L (as high as hundreds of henrys), a very small series capacitance Cs (as small as 0.0005 pF), a series resistance r representing a Q factor ω0L/r that can be as high as a few hundred thousand, and a parallel capacitance Cp (a few picofarads). Capacitor Cp repre-sents the electrostatic capacitance between the two parallel plates of the crystal. Note that Cp @ Cs.
EXERCISES 17.8 Show that for the Hartley oscillator of Fig. 17.12(b), the frequency of oscillation is given by Eq. (17.17) and that for oscillations to start gmR > .
D17.9 Using a BJT biased at IC = 1 mA, design a Colpitts oscillator to operate at ω0 = 106 rad/s. Use C1 = 0.01 μF and assume that the coil available has a Q of 100 (this can be represented by a resistance in parallel with C1 given by Q ⁄ω0C1). Also assume that there is a load resistance at the collector of 2 kΩ and that for the BJT, ro = 100 kΩ. Find C2 and L.
Ans. 0.66 μF; 100 μH (a somewhat smaller C2 would be used to allow oscillations to grow in amplitude) L1 L2 ⁄ ( ) Figure 17.15 A piezoelectric crystal. (a) Circuit symbol. (b) Equivalent circuit. (c) Crystal reactance versus frequency [note that, neglecting the small resistance r, Zcrystal = jX(ω)].
(a) (b) (c) 1354 Chapter 17 Signal Generators and Waveform-Shaping Circuits Since the Q factor is very high, we may neglect the resistance r and express the crystal impedance as which can be manipulated to the form (17.23) From Eq. (17.23) and from Fig. 17.15(b), we see that the crystal has two resonance frequen-cies: a series resonance at ωs (17.24) and a parallel resonance at ωp (17.25) Thus for s = jω we can write (17.26) From Eqs. (17.24) and (17.25) we note that ωp > ωs. However, since Cp @ Cs, the two reso-nance frequencies are very close. Expressing Z( jω) = jX(ω), the crystal reactance X(ω) will have the shape shown in Fig. 17.15(c). We observe that the crystal reactance is inductive over the very narrow frequency band between ωs and ωp. For a given crystal, this frequency band is well defined. Thus we may use the crystal to replace the inductor of the Colpitts oscillator (Fig. 17.12a). The resulting circuit will oscillate at the resonance frequency of the crystal inductance L with the series equivalent of Cs and . Since Cs is much smaller than the three other capacitances, it will be dominant and (17.27) In addition to the basic Colpitts oscillator, a variety of configurations exist for crystal oscilla-tors. Figure 17.16 shows a popular configuration (called the Pierce oscillator) utilizing a CMOS inverter (see Section 13.2) as an amplifier. Resistor Rf determines a dc operating point in the high-gain region of the VTC of the CMOS inverter. Resistor R1 together with capacitor C1 provides a low-pass filter that discourages the circuit from oscillating at a higher harmonic of the crystal frequency. Note that this circuit also is based on the Colpitts configuration.
The extremely stable resonance characteristics and the very high Q factors of quartz crystals result in oscillators with very accurate and stable frequencies. Crystals are available with resonance frequencies in the range of a few kilohertz to hundreds of megahertz. Tem-perature coefficients of ω0 of 1 or 2 parts per million (ppm) per degree Celsius are achievable. Unfortunately, however, crystal oscillators, being mechanical resonators, are fixed-frequency circuits.
Z s ( ) 1 sCp 1 sL 1 sCs ⁄ + ---------------------------+ = Z s ( ) 1 sCp --------s 2 1 LCs ⁄ ( ) + s 2 Cp Cs + ( ) LCsCp ⁄ [ ] + ----------------------------------------------------------= ωs 1 LCs ⁄ = ωp 1 L CsCp Cs Cp + ------------------⎝ ⎠ ⎛ ⎞ = Z j ω ( ) j 1 ωCp ---------- ω 2 ωs 2 – ω 2 ωp 2 – ------------------⎝ ⎠ ⎜ ⎟ ⎛ ⎞ – = (Cp C1C2 C1 C2 + ( ) ⁄ ) + ω0 1 LCs ⁄ ωs = 17.4 Bistable Multivibrators 1355 17.4 Bistable Multivibrators In this section we begin the study of waveform-generating circuits of the other type—nonlinear oscillators or function generators. These devices make use of a special class of circuits known as multivibrators. As mentioned earlier, there are three types of multivibrator: bistable, monostable, and astable. This section is concerned with the first, the bistable multi-vibrator.5 As its name indicates, the bistable multivibrator has two stable states. The circuit can remain in either stable state indefinitely and moves to the other stable state only when appro-priately triggered.
17.4.1 The Feedback Loop Bistability can be obtained by connecting a dc amplifier in a positive-feedback loop having a loop gain greater than unity. Such a feedback loop is shown in Fig. 17.17; it consists of an op amp and a resistive voltage divider in the positive-feedback path. To see how bistability is obtained, consider operation with the positive-input terminal of the op amp near ground potential. This is a reasonable starting point, since the circuit has no external excitation.
Figure 17.16 A Pierce crystal oscillator utilizing a CMOS inverter as an amplifier.
EXERCISES 17.10 A 2-MHz quartz crystal is specified to have L = 0.52 H, Cs = 0.012 pF, Cp = 4 pF, and r = 120 Ω..
Find fs, fp, and Q.
Ans. 2.015 MHz; 2.018 MHz; 55,000 5 Digital implementations of multivibrators were presented in Chapter 15. Here, we are interested in implementations utilizing op amps.
1356 Chapter 17 Signal Generators and Waveform-Shaping Circuits Assume that the electrical noise that is inevitably present in every electronic circuit causes a small positive increment in the voltage v+. This incremental signal will be amplified by the large open-loop gain A of the op amp, with the result that a much greater signal will appear in the op amp’s output voltage vO. The voltage divider (R1, R2) will feed a fraction of the output signal back to the positive-input terminal of the op amp. If Aβ is greater than unity, as is usually the case, the fed-back signal will be greater than the original increment in v+. This regenerative process continues until eventually the op amp sat-urates with its output voltage at the positive-saturation level, L+. When this happens, the volt-age at the positive-input terminal, v+, becomes , which is positive and thus keeps the op amp in positive saturation. This is one of the two stable states of the circuit.
In the description above we assumed that when v+ was near zero volts, a positive incre-ment occurred in v+. Had we assumed the equally probable situation of a negative increment, the op amp would have ended up saturated in the negative direction with vO = L− and v+ = . This is the other stable state.
We thus conclude that the circuit of Fig. 17.17 has two stable states, one with the op amp in positive saturation and the other with the op amp in negative saturation. The circuit can exist in either of these two states indefinitely. We also note that the circuit cannot exist in the state for which v+ = 0 and vO = 0 for any length of time. This is a state of unstable equilib-rium (also known as a metastable state); any disturbance, such as that caused by electrical noise, causes the bistable circuit to switch to one of its two stable states. This is in sharp con-trast to the case when the feedback is negative, causing a virtual short circuit to appear between the op amp’s input terminals and maintaining this virtual short circuit in the face of disturbances. A physical analogy for the operation of the bistable circuit is depicted in Fig. 17.18. 17.4.2 Transfer Characteristics of the Bistable Circuit The question naturally arises as to how we can make the bistable circuit of Fig. 17.17 change state. To help answer this crucial question, we derive the transfer characteristics of the Figure 17.17 A positive-feedback loop capable of bistable operation.
Figure 17.18 A physical analogy for the operation of the bistable circuit. The ball cannot remain at the top of the hill for any length of time (a state of unstable equilibrium or metastability); the inevitably present disturbance will cause the ball to fall to one side or the other, where it can remain indefinitely (the two stable states).
β R1 R1 R2 + ( ) ⁄ ≡ L+R1 R1 R2 + ( ) ⁄ L−R1 R1 R2 + ( ) ⁄ 17.4 Bistable Multivibrators 1357 bistable. Reference to Fig. 17.17 indicates that either of the two circuit nodes that are con-nected to ground can serve as an input terminal. We investigate both possibilities.
Figure 17.19(a) shows the bistable circuit with a voltage vI applied to the inverting input terminal of the op amp. To derive the transfer characteristic vO–vI, assume that vO is at one of its two possible levels, say L+, and thus v+ = βL+. Now as vI is increased from 0 V, we can see from the circuit that nothing happens until vI reaches a value equal to v+ (i.e., βL+). As vI begins to exceed this value, a net negative voltage develops between the input terminals of the op amp. This voltage is amplified by the open-loop gain of the op amp, and thus vO goes negative. The voltage divider in turn causes v+ to go negative, thus increasing the net nega-tive input to the op amp and keeping the regenerative process going. This process culminates in Figure 17.19 (a) The bistable circuit of Fig. 17.17 with the negative input terminal of the op amp discon-nected from ground and connected to an input signal vI. (b) The transfer characteristic of the circuit in (a) for increasing vI. (c) The transfer characteristic for decreasing vI. (d) The complete transfer characteristics.
v R1 R2 vI vO (a) vO vI VTH L 0 L (b) vO vI L 0 L VTL (c) L vO vI VTH 0 L VTL (d) 1358 Chapter 17 Signal Generators and Waveform-Shaping Circuits the op amp saturating in the negative direction: that is, with vO = L− and, correspondingly, v+ = βL−. It is easy to see that increasing vI further has no effect on the acquired state of the bistable circuit. Figure 17.19(b) shows the transfer characteristic for increasing vI. Observe that the characteristic is that of a comparator with a threshold voltage denoted VTH, where VTH = βL+.
Next consider what happens as vI is decreased. Since now v+ = βL−, we see that the cir-cuit remains in the negative-saturation state until vI goes negative to the point that it equals βL−. As vI goes below this value, a net positive voltage appears between the op amp’s input terminals. This voltage is amplified by the op-amp gain and thus gives rise to a positive voltage at the op amp’s output. The regenerative action of the positive-feedback loop then sets in and causes the circuit eventually to go to its positive-saturation state, in which vO = L+ and v+ = βL+. The transfer characteristic for decreasing vI is shown in Fig. 17.19(c). Here again we observe that the characteristic is that of a comparator, but with a threshold voltage VTL = βL−.
The complete transfer characteristics, vO−vI, of the circuit in Fig. 17.19(a) can be obtained by combining the characteristics in Fig. 17.19(b) and (c), as shown in Fig. 17.19(d). As indi-cated, the circuit changes state at different values of vI, depending on whether vI is increasing or decreasing. Thus the circuit is said to exhibit hysteresis; the width of the hysteresis is the difference between the high threshold VTH and the low threshold VTL. Also note that the bistable circuit is in effect a comparator with hysteresis. As will be shown shortly, adding hysteresis to a comparator’s characteristics can be very beneficial in certain applications.
Finally, observe that because the bistable circuit of Fig. 17.19 switches from the positive state (vO = L+) to the negative state (vO = L−) as vI is increased past the positive threshold VTH, the circuit is said to be inverting. A bistable circuit with a noninverting transfer characteristic will be presented shortly.
17.4.3 Triggering the Bistable Circuit Returning now to the question of how to make the bistable circuit change state, we observe from the transfer characteristics of Fig. 17.19(d) that if the circuit is in the L+ state it can be switched to the L− state by applying an input vI of value greater than VTH ≡ βL+. Such an input causes a net negative voltage to appear between the input terminals of the op amp, which initiates the regenerative cycle that culminates in the circuit switching to the L− stable state. Here it is important to note that the input vI merely initiates or triggers regeneration.
Thus we can remove vI with no effect on the regeneration process. In other words, vI can be simply a pulse of short duration. The input signal vI is thus referred to as a trigger signal, or simply a trigger.
The characteristics of Fig. 17.19(d) indicate also that the bistable circuit can be switched to the positive state (vO = L+) by applying a negative trigger signal vI of magnitude greater than that of the negative threshold VTL.
17.4.4 The Bistable Circuit as a Memory Element We observe from Fig. 17.19(d) that for input voltages in the range VTL < vI < VTH, the output can be either L+ or L−, depending on the state that the circuit is already in. Thus, for this input range, the output is determined by the previous value of the trigger signal (the trigger signal that caused the circuit to be in its current state). Thus the circuit exhibits memory.
Indeed, the bistable multivibrator is the basic memory element of digital systems, as we have seen in Chapter 15. Finally, note that in analog circuit applications, such as the ones of con-cern to us in this chapter, the bistable circuit is also known as a Schmitt trigger.
17.4 Bistable Multivibrators 1359 17.4.5 A Bistable Circuit with Noninverting Transfer Characteristics The basic bistable feedback loop of Fig. 17.17 can be used to derive a circuit with noninvert-ing transfer characteristics by applying the input signal vI (the trigger signal) to the terminal of R1 that is connected to ground. The resulting circuit is shown in Fig. 17.20(a). To obtain the transfer characteristics we first employ superposition to the linear circuit formed by R1 and R2, thus expressing v+ in terms of vI and vO as (17.28) From this equation we see that if the circuit is in the positive stable state with vO = L+, posi-tive values for vI will have no effect. To trigger the circuit into the L− state, vI must be made negative and of such a value as to make v+ decrease below zero. Thus the low threshold VTL can be found by substituting in Eq. (17.28) vO = L+, v+ = 0, and vI = VTL. The result is (17.29) Similarly, Eq. (17.28) indicates that when the circuit is in the negative-output state (vO = L−), negative values of vI will make v+ more negative with no effect on operation. To initiate the regeneration process that causes the circuit to switch to the positive state, v+ must be made to go slightly positive. The value of vI that causes this to happen is the high threshold voltage VTH, which can be found by substituting in Eq. (17.28) vO = L− and v+ = 0. The result is (17.30) The complete transfer characteristic of the circuit of Fig. 17.20(a) is displayed in Fig. 17.20(b).
Observe that a positive triggering signal vI (of value greater than VTH) causes the circuit to switch to the positive state (vO goes from L− to L+). Thus the transfer characteristic of this cir-cuit is noninverting.
v+ vI R2 R1 R2 + -----------------vO R1 R1 R2 + ------------------+ = VTL L+ R1 R2 ⁄ ( ) – = VTH L– R1 R2 ⁄ ( ) – = Figure 17.20 (a) A bistable circuit derived from the positive-feedback loop of Fig. 17.17 by applying vI through R1. (b) The transfer characteristic of the circuit in (a) is noninverting. (Compare it to the inverting characteristic in Fig. 17.19d.) v R1 R2 vI vO (a) L L vO vI 0 VTH VTL (b) 1360 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.4.6 Application of the Bistable Circuit as a Comparator The comparator is an analog-circuit building block that is used in a variety of applications ranging from detecting the level of an input signal relative to a preset threshold value, to the design of analog-to-digital (A/D) converters. Although one normally thinks of the comparator as having a single threshold value (see Fig. 17.21a), it is useful in many appli-cations to add hysteresis to the comparator characteristics. If this is done, the comparator exhibits two threshold values, VTL and VTH, symmetrically placed about the desired refer-ence level, as indicated in Fig. 17.21(b). Usually VTH and VTL are separated by a small amount, say 100 mV.
To demonstrate the need for hysteresis, we consider a common application of compara-tors. It is required to design a circuit that detects and counts the zero crossings of an arbi-trary waveform. Such a function can be implemented using a comparator whose threshold is set to 0 V. The comparator provides a step change at its output every time a zero crossing occurs. Each step change can be used to generate a pulse, and the pulses are fed to a counter circuit.
Figure 17.21 (a) Block diagram representation and transfer characteristic for a comparator having a refer-ence, or threshold, voltage VR. (b) Comparator characteristic with hysteresis.
(a) 17.4 Bistable Multivibrators 1361 Imagine now what happens if the signal being processed has—as it usually does have— interference superimposed on it, say of a frequency much higher than that of the signal. It follows that the signal might cross the zero axis a number of times around each of the zero-crossing points we are trying to detect, as shown in Fig. 17.22. The comparator would thus change state a number of times at each of the zero crossings, and our count would obviously be in error. However, if we have an idea of the expected peak-to-peak amplitude of the interference, the problem can be solved by introducing hysteresis of appropriate width in the comparator characteristics. Then, if the input signal is increasing in magni-tude, the comparator with hysteresis will remain in the low state until the input level exceeds the high threshold VTH. Subsequently the comparator will remain in the high state even if, owing to interference, the signal decreases below VTH. The comparator will switch to the low state only if the input signal is decreased below the low threshold VTL. The situ-ation is illustrated in Fig. 17.22, from which we see that including hysteresis in the com-parator characteristics provides an effective means for rejecting interference (thus providing another form of filtering).
17.4.7 Making the Output Levels More Precise The output levels of the bistable circuit can be made more precise than the saturation volt-ages of the op amp are by cascading the op amp with a limiter circuit (see Section 4.6 for a discussion of limiter circuits). Two such arrangements are shown in Fig. 17.23.
Figure 17.22 Illustrating the use of hysteresis in the comparator characteristics as a means of rejecting interference.
Signal corrupted with interference Multiple zero crossings VTL VR 0 VTH t 1362 Chapter 17 Signal Generators and Waveform-Shaping Circuits Figure 17.23 Limiter circuits are used to obtain more precise output levels for the bistable circuit. In both circuits the value of R should be chosen to yield the current required for the proper operation of the zener diodes. (a) For this circuit and , where VD is the forward diode drop. (b) For this circuit and R1 Z2 vI vO R2 Z1 R (a) R1 vI vO R2 R Z (b) D1 D1 D1 D3 D1 D2 D1 D4 L+ VZ1 VD + = L− VZ2 VD + ( ) – = L+ VZ VD1 VD2 + + = L– VZ VD3 VD4 + + ( ) – = .
EXERCISES D17.11 The op amp in the bistable circuit of Fig. 17.19(a) has output saturation voltages of ±13 V. Design the circuit to obtain threshold voltages of ±5 V. For R1 = 10 kΩ, find the value required for R2.
Ans. 16 kΩ D17.12 If the op amp in the circuit of Fig. 17.20(a) has ±10-V output saturation levels, design the circuit to obtain ±5-V thresholds. Give suitable component values.
Ans. Possible choice: R1 = 10 kΩ and R2 = 20 kΩ 17.13 Consider a bistable circuit with a noninverting transfer characteristic and let L+ = −L− = 10 V and VTH = −VTL = 5 V. If vI is a triangular wave with a 0-V average, a 10-V peak amplitude, and a 1-ms period, sketch the waveform of vO. Find the time interval between the zero crossings of vI and vO.
Ans. vO is a square wave with 0-V average, 10-V amplitude, and 1-ms period and is delayed by 125 μs relative to vI 17.14 Consider an op amp having saturation levels of ±12 V used without feedback, with the inverting input terminal connected to +3 V and the noninverting input terminal connected to vI. Character-ize its operation as a comparator. What are L+, L−, and VR, as defined in Fig. 17.21(a)?
Ans. +12 V; −12 V; +3 V 17.15 In the circuit of Fig. 17.20(a), let L+ = −L− = 10 V and R1 = 1 kΩ.. Find a value for R2 that gives a hysteresis of 100-mV width.
Ans. 200 kΩ 17.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators 1363 17.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators A square waveform can be generated by arranging for a bistable multivibrator to switch states periodically. This can be done by connecting the bistable multivibrator with an RC cir-cuit in a feedback loop, as shown in Fig. 17.24(a). Observe that the bistable multivibrator has an inverting transfer characteristic and can thus be realized using the circuit of Fig. 17.19(a). This results in the circuit of Fig. 17.24(b). We shall show shortly that this circuit has no stable states and thus is appropriately named an astable multivibrator.
At this point we wish to remind the reader of an important relationship, which we shall employ on many occasions in the following few sections: A capaciter C that is charging or discharging through a resistance R toward a final voltage V∞ has a voltage v (t), v (t) = V∞ – (V∞ – V0+ ) e−t/τ where V0+ is the voltage at t = 0+ and τ = CR is the time constant.
17.5.1 Operation of the Astable Multivibrator To see how the astable multivibrator operates, refer to Fig. 17.24(b) and let the output of the bistable multivibrator be at one of its two possible levels, say L+. Capacitor C will charge toward this level through resistor R. Thus the voltage across C, which is applied to the negative input terminal of the op amp and thus is denoted v−, will rise exponentially toward L+ with a time constant τ = CR. Meanwhile, the voltage at the positive input termi-nal of the op amp is v+ = βL+. This situation will continue until the capacitor voltage reaches the positive threshold VTH = βL+, at which point the bistable multivibrator will Figure 17.24 (a) Connecting a bistable multivibrator with inverting transfer characteristics in a feedback loop with an RC circuit results in a square-wave generator.
v2 v1 0 C R L t t L L v2 L v1 VTH VTL VTH VTL L L (a) 1364 Chapter 17 Signal Generators and Waveform-Shaping Circuits switch to the other stable, state, in which vO = L− and v+ = βL−. The capacitor will then start discharging, and its voltage, v−, will decrease exponentially toward L−. This new state will prevail until v− reaches the negative threshold VTL = βL−, at which time the bistable multivibrator switches to the positive-output state, the capacitor begins to charge, and the cycle repeats itself.
From the preceding description we see that the astable circuit oscillates and produces a square waveform at the output of the op amp. This waveform, and the waveforms at the two input terminals of the op amp, are displayed in Fig. 17.24(c). The period T of the square wave can be found as follows: During the charging interval T1 the voltage v− across the capacitor at any time t, with t = 0 at the beginning of T1, is given by (see Appendix E) Figure 17.24 (Continued) (b) The circuit obtained when the bistable multivibrator is implemented with the circuit of Fig. 17.19(a). (c) Waveforms at various nodes of the circuit in (b). This circuit is called an astable multivibrator.
(b) (c) v− L+ L+ βL− – ( )e t τ ⁄ – – = 17.5 Generation of Square and Triangular Waveforms Using Astable Multivibrators 1365 where τ = CR. Substituting v− = βL+ at t = T1 gives (17.31) Similarly, during the discharge interval T2 the voltage v− at any time t, with t = 0 at the begin-ning of T2, is given by Substituting v− = βL– at t = T2 gives (17.32) Equations (17.31) and (17.32) can be combined to obtain the period T = T1 + T2. Normally, L+ = −L−, resulting in symmetrical square waves of period T given by (17.33) Note that this square-wave generator can be made to have variable frequency by switching different capacitors C (usually in decades) and by continuously adjusting R (to obtain continuous frequency control within each decade of frequency). Also, the waveform across C can be made almost triangular by using a small value for the parameter β. How-ever, triangular waveforms of superior linearity can be easily generated using the scheme discussed next.
Before leaving this section, however, note that although the astable circuit has no stable states, it has two quasi-stable states and remains in each for a time interval determined by the time constant of the RC network and the thresholds of the bistable multivibrator.
T1 τ 1 β L−L+ ⁄ ( ) – 1 β – --------------------------------ln = v− L− L− βL+ – ( )e t τ ⁄ – – = T2 τ 1 β L+ L− ⁄ ( ) – 1 β – --------------------------------ln = T 2τ 1 β + 1 β – ------------ln = EXERCISES 17.16 For the circuit in Fig. 17.24(b), let the op-amp saturation voltages be ±10 V, R1 =100 kΩ, R2 = R = 1 MΩ, and C = 0.01 μF. Find the frequency of oscillation.
Ans. 274 Hz 17.17 Consider a modification of the circuit of Fig. 17.24(b) in which R1 is replaced by a pair of diodes connected in parallel in opposite directions. For L+ = −L− = 12 V, R2 = R = 10 kΩ, C = 0.1 μ F, and the diode voltage as a constant denoted VD, find an expression for frequency as a function of VD.
If VD = 0.70 V at 25°C with a TC of −2 mV/°C, find the frequency at 0°C, 25°C, 50°C, and 100°C.
Note that the output of this circuit can be sent to a remotely connected frequency meter to provide a digital readout of temperature.
Ans. f = 500/ln [(12 + VD) / (12 − VD)] Hz; 3995 Hz, 4281 Hz, 4611 Hz, 5451 Hz 1366 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.5.2 Generation of Triangular Waveforms The exponential waveforms generated in the astable circuit of Fig. 17.24 can be changed to triangular by replacing the low-pass RC circuit with an integrator. (The integrator is, after all, a low-pass circuit with a corner frequency at dc.) The integrator causes linear charging and discharging of the capacitor, thus providing a triangular waveform. The resulting circuit is shown in Fig. 17.25(a). Observe that because the integrator is inverting, it is necessary to invert the characteristics of the bistable circuit. Thus the bistable circuit required here is of the noninverting type and can be implemented using the circuit of Fig. 17.20.
We now proceed to show how the feedback loop of Fig. 17.25(a) oscillates and generates a triangular waveform v1 at the output of the integrator and a square waveform v2 at the out-put of the bistable circuit: Let the output of the bistable circuit be at L+. A current equal to will flow into the resistor R and through capacitor C, causing the output of the inte-grator to linearly decrease with a slope of as shown in Fig. 17.25(c). This will continue until the integrator output reaches the lower threshold VTL of the bistable circuit, at which point the bistable circuit will switch states, its output becoming negative and equal to L−. At this moment the current through R and C will reverse direction, and its value will become equal to It follows that the integrator output will start to increase linearly with a positive slope equal to This will continue until the integrator output voltage reaches the positive threshold of the bistable circuit, VTH. At this point the bistable circuit Figure 17.25 A general scheme for generating triangular and square waveforms.
L+ R ⁄ L+ – CR, ⁄ L− R.
⁄ L− CR.
⁄ (a) C v1 v1 v2 v2 L L VTH VTL v2 v1 (b) (c) 17.6 Generation of a Standardized Pulse—The Monostable Multivibrator 1367 switches, its output becomes positive (L+), the current into the integrator reverses direction, and the output of the integrator starts to decrease linearly, beginning a new cycle.
From the discussion above, it is relatively easy to derive an expression for the period T of the square and triangular waveforms. During the interval T1 we have, from Fig. 17.25(c), from which we obtain (17.34) Similarly, during T2 we have from which we obtain (17.35) Thus to obtain symmetrical square waves we design the bistable circuit to have L+ = −L−.
17.6 Generation of a Standardized Pulse—The Monostable Multivibrator In some applications the need arises for a pulse of known height and width generated in response to a trigger signal. Because the width of the pulse is predictable, its trailing edge can be used for timing purposes—that is, to initiate a particular task at a specified time. Such a standardized pulse can be generated by the third type of multivibrator, the monostable multivibrator.
The monostable multivibrator has one stable state in which it can remain indefinitely. It also has a quasi-stable state to which it can be triggered and in which it stays for a predeter-mined interval equal to the desired width of the output pulse. When this interval expires, the monostable multivibrator returns to its stable state and remains there, awaiting another trig-gering signal. The action of the monostable multivibrator has given rise to its alternative name, the one shot.
VTH VTL – T1 -----------------------L+ CR --------= T1 CRVTH VTL – L+ -----------------------= VTH VTL – T2 -----------------------L – − CR --------= T2 CRVTH VTL – L – − -----------------------= EXERCISES D17.18 Consider the circuit of Fig. 17.25(a) with the bistable circuit realized by the circuit in Fig. 17.20(a). If the op amps have saturation voltages of ±10 V, and if a capacitor C = 0.01 μF and a resistor R1 = 10 kΩ are used, find the values of R and R2 (note that R1 and R2 are associated with the bistable circuit of Fig. 17.20a) such that the frequency of oscillation is 1 kHz and the triangular waveform has a 10-V peak-to-peak amplitude.
Ans. 50 kΩ; 20 kΩ 1368 Chapter 17 Signal Generators and Waveform-Shaping Circuits Figure 17.26(a) shows an op-amp monostable circuit. We observe that this circuit is an augmented form of the astable circuit of Fig. 17.24(b). Specifically, a clamping diode D1 is added across the capacitor C1, and a trigger circuit composed of capacitor C2, resistor R4, and diode D2 is connected to the noninverting input terminal of the op amp. The circuit operates as follows: In the stable state, which prevails in the absence of the triggering signal, the out-put of the op amp is at L+ and diode D1 is conducting through R3 and thus clamping the volt-age vB to one diode drop above ground. We select R4 much larger than R1, so that diode D2 will be conducting a very small current and the voltage vC will be very closely determined by the voltage divider R1, R2. Thus vC = βL+, where The stable state is maintained because βL+ is greater than VD1.
Now consider the application of a negative-going step at the trigger input and refer to the signal waveforms shown in Fig. 17.26(b). The negative triggering edge is coupled to the cathode of diode D2 via capacitor C2, and thus D2 conducts heavily and pulls node C down. If the trigger signal is of sufficient height to cause vC to go below vB, the op amp will see a net negative input voltage and its output will switch to L−. This in turn will cause vC to go nega-tive to βL−, keeping the op amp in its newly acquired state. Note that D2 will then cut off, thus isolating the circuit from any further changes at the trigger input terminal.
The negative voltage at A causes D1 to cut off, and C1 begins to discharge exponentially toward L− with a time constant C1R3. The monostable multivibrator is now in its quasi-stable state, which will prevail until the declining vB goes below the voltage at node C, which is βL−. At this instant the op-amp output switches back to L+ and the voltage at node C goes back to βL+. Capacitor C1 then charges toward L+ until diode D1 turns on and the circuit returns to its stable state.
Figure 17.26 (a) An op-amp monostable circuit. (b) Signal waveforms in the circuit of (a).
(a) D1 D2 t D1 A C B ( L VD2) vE (b) β R1 R1 R2 + ( ) ⁄ .
= 17.7 Integrated-Circuit Timers 1369 From Fig. 17.26(b), we observe that a negative pulse is generated at the output during the quasi-stable state. The duration T of the output pulse is determined from the exponential waveform of vB, by substituting vB(T ) = βL−, which yields (17.36) For VD1 |L−|, this equation can be approximated by (17.37) Finally, note that the monostable circuit should not be triggered again until capacitor C1 has been recharged to VD1; otherwise the resulting output pulse will be shorter than normal. This recharging time is known as the recovery period. Circuit techniques exist for shortening the recovery period.
17.7 Integrated-Circuit Timers Commercially available integrated-circuit packages exist that contain the bulk of the cir-cuitry needed to implement monostable and astable multivibrators with precise characteris-tics. In this section we discuss the most popular of such ICs, the 555 timer. Introduced in 1972 by the Signetics Corporation as a bipolar integrated circuit, the 555 is also available in CMOS technology and from a number of manufacturers.6 17.7.1 The 555 Circuit Figure 17.27 shows a block diagram representation of the 555 timer circuit [for the actual circuit, refer to Grebene (1984)]. The circuit consists of two comparators, an SR flip-flop, and a transistor Q1 that operates as a switch. One power supply (VCC) is required for opera-tion, with the supply voltage typically 5 V. A resistive voltage divider, consisting of the three vB t ( ) L− L− VD1 – ( )e t C1R3 ⁄ – – = βL− L− L− VD1 – ( )e T C1R3 ⁄ – – = T C1R3 VD1 L− – βL− L− – ---------------------⎝ ⎠ ⎛ ⎞ ln = T C1R3 1 1 β – ------------⎝ ⎠ ⎛ ⎞ ln EXERCISES 17.19 For the monostable circuit of Fig. 17.26(a), find the value of R3 that will result in a 100-μs output pulse for C1 = 0.1 μ F, β = 0.1, VD = 0.7 V, and L+ = −L− = 12 V.
Ans. 6171 Ω 6 In a recent article in IEEE Spectrum (May 2009), the 555 was selected as one of the “25 Microchips That Shook the World.” 1370 Chapter 17 Signal Generators and Waveform-Shaping Circuits equal-valued resistors labeled R1, is connected across VCC and establishes the reference (threshold) voltages for the two comparators. These are for comparator 1 and for comparator 2.
We studied SR flip-flops in Chapter 15. For our purposes here we note that an SR flip-flop is a bistable circuit having complementary outputs, denoted Q and . In the set state, the output at Q is “high” (approximately equal to VCC) and that at is “low” (approximately equal to 0 V). In the other stable state, termed the reset state, the output at Q is low and that at is high. The flip-flop is set by applying a high level (VCC) to its set input terminal, labeled S. To reset the flip-flop, a high level is applied to the reset input terminal, labeled R.
Note that the reset and set input terminals of the flip-flop in the 555 circuit are connected to the outputs of comparator 1 and comparator 2, respectively.
The positive-input terminal of comparator 1 is brought out to an external terminal of the 555 package, labeled Threshold. Similarly, the negative-input terminal of comparator 2 is connected to an external terminal labeled Trigger, and the collector of transistor Q1 is con-nected to a terminal labeled Discharge. Finally, the Q output of the flip-flop is connected to the output terminal of the timer package, labeled Out.
17.7.2 Implementing a Monostable Multivibrator Using the 555 IC Figure 17.28(a) shows a monostable multivibrator implemented using the 555 IC together with an external resistor R and an external capacitor C. In the stable state the flip-flop will be in the reset state, and thus its output will be high, turning on transistor Q1. Transistor Q1 will be saturated, and thus vC will be close to 0 V, resulting in a low level at the output of comparator 1. The voltage at the trigger input terminal, labeled vtrigger, is kept high (greater than VTL), and thus the output of comparator 2 also will be low. Finally, note that since the flip-flop is in the reset state, Q will be low and thus vO will be close to 0 V.
Figure 17.27 A block diagram representation of the internal circuit of the 555 integrated-circuit timer.
R1 VTL R1 Q1 VCC VTH R1 R S Q Q 100 Flip-flop Comparator 1 Comparator 2 Out Ground Discharge Trigger Threshold VTH 2 3 --- V CC = VTL 1 3 ---V CC = Q Q Q Q 17.7 Integrated-Circuit Timers 1371 Figure 17.28 (a) The 555 timer connected to implement a monostable multivibrator. (b) Waveforms of the circuit in (a).
R1 R1 Q1 R R S Q Q 100 Flip-flop Comparator 1 Comparator 2 C R1 vO vtrigger VTL VTH VCC vC (a) VTL vO VTH VCC 0 0 0 vtrigger vC T T to VCC t t t (b) 1372 Chapter 17 Signal Generators and Waveform-Shaping Circuits To trigger the monostable multivibrator, a negative input pulse is applied to the trigger input terminal. As vtrigger goes below VTL, the output of comparator 2 goes to the high level, thus setting the flip-flop. Output Q of the flip-flop goes high, and thus vO goes high, and out-put goes low, turning off transistor Q1. Capacitor C now begins to charge up through resistor R, and its voltage vC rises exponentially toward VCC, as shown in Fig. 17.28(b). The monostable multivibrator is now in its quasi-stable state. This state prevails until vC reaches and begins to exceed the threshold of comparator 1, VTH, at which time the output of compar-ator 1 goes high, resetting the flip-flop. Output of the flip-flop now goes high and turns on transistor Q1. In turn, transistor Q1 rapidly discharges capacitor C, causing vC to go to 0 V.
Also, when the flip-flop is reset, its Q output goes low, and thus vO goes back to 0 V. The monostable multivibrator is now back in its stable state and is ready to receive a new trigger-ing pulse.
From the description above we see that the monostable multivibrator produces an output pulse vO as indicated in Fig. 17.28(b). The width of the pulse, T, is the time interval that the monostable multivibrator spends in the quasi-stable state; it can be determined by reference to the waveforms in Fig. 17.28(b) as follows: Denoting the instant at which the trigger pulse is applied as t = 0, the exponential waveform of vC can be expressed as (17.38) Substituting at t = T gives (17.39) Thus the pulse width is determined by the external components C and R, which can be selected to have values as precise as desired.
17.7.3 An Astable Multivibrator Using the 555 IC Figure 17.29(a) shows the circuit of an astable multivibrator employing a 555 IC, two exter-nal resistors, RA and RB, and an external capacitor C. To see how the circuit operates, refer to the waveforms depicted in Fig. 17.29(b). Assume that initially C is discharged and the flip-flop is set. Thus vO is high and Q1 is off. Capacitor C will charge up through the series com-bination of RA and RB, and the voltage across it, vC, will rise exponentially toward VCC. As vC crosses the level equal to VTL, the output of comparator 2 goes low. This, however, has no effect on the circuit operation, and the flip-flop remains set. Indeed, this state continues until vC reaches and begins to exceed the threshold of comparator 1, VTH. At this instant of time, the output of comparator 1 goes high and resets the flip-flop. Thus vO goes low, goes high, and transistor Q1 is turned on. The saturated transistor Q1 causes a voltage of approxi-mately zero volts to appear at the common node of RA and RB. Thus C begins to discharge through RB and the collector of Q1. The voltage vC decreases exponentially with a time con-stant CRB toward 0 V. When vC reaches the threshold of comparator 2, VTL, the output of comparator 2, goes high and sets the flip-flop. The output vO then goes high, and goes low, turning off Q1. Capacitor C begins to charge through the series equivalent of RA and RB, and its voltage rises exponentially toward VCC with a time constant C(RA + RB). This rise contin-ues until vC reaches VTH, at which time the output of comparator 1 goes high, resetting the flip-flop, and the cycle continues.
From the description above we see that the circuit of Fig. 17.29(a) oscillates and produces a square waveform at the output. The frequency of oscillation can be determined as follows.
Q Q vC VCC 1 e t CR ⁄ – – ( ) = vC = V TH 2 3 ---V CC = T CR 3 ln = 1.1CR Q Q 17.7 Integrated-Circuit Timers 1373 Figure 17.29 (a) The 555 timer connected to implement an astable multivibrator. (b) Waveforms of the circuit in (a).
RB R1 Q1 R S Q Q 100 Flip-flop Comparator 1 Comparator 2 C R1 vO VTL VTH VCC R1 RA vC (a) vO TL VCC vC VTH VCC VTL TH t t (b) 1374 Chapter 17 Signal Generators and Waveform-Shaping Circuits Reference to Fig. 17.29(b) indicates that the output will be high during the interval TH, in which vC rises from VTL to VTH. The exponential rise of vC can be described by (17.40) where t = 0 is the instant at which the interval TH begins. Substituting at t = TH and results in (17.41) We also note from Fig. 17.29(b) that vO will be low during the interval TL, in which vC falls from VTH to VTL. The exponential fall of vC can be described by (17.42) where we have taken t = 0 as the beginning of the interval TL. Substituting at t = TL and results in TL = CRB ln 2 0.69 CRB (17.43) Equations (17.41) and (17.43) can be combined to obtain the period T of the output square wave as T = TH + TL = 0.69 C(RA + 2RB) (17.44) Also, the duty cycle of the output square wave can be found from Eqs. (17.41) and (17.43): (17.45) Note that the duty cycle will always be greater than 0.5 (50%); it approaches 0.5 if RA is selected to be much smaller than RB (unfortunately, at the expense of supply current).
17.8 Nonlinear Waveform-Shaping Circuits Diodes or transistors can be combined with resistors to synthesize two-port networks having arbitrary nonlinear transfer characteristics. Such two-port networks can be employed in vC = V CC V CC V TL – ( )e t C RA+RB ( ) ⁄ – – vC = V TH 2 3 ---V CC = VTL 1 3 ---V CC = TH C(RA RB + ) 2 ln = 0.69 C RA RB + ( ) vC V THe t CRB ⁄ – = vC = VTL 1 3 ---V CC = V TH 2 3 ---V CC = Duty cycle T H T H T L + ------------------≡ RA RB + RA 2RB + ----------------------= EXERCISES 17.20 Using a 10-nF capacitor C, find the value of R that yields an output pulse of 100 μs in the monostable circuit of Fig. 17.28(a).
Ans. 9.1 kΩ D17.21 For the circuit in Fig. 17.29(a), with a 1-nF capacitor, find the values of RA and RB that result in an oscillation frequency of 100 kHz and a duty cycle of 75%.
Ans. 7.2 kΩ, 3.6 kΩ 17.8 Nonlinear Waveform-Shaping Circuits 1375 waveform shaping—that is, changing the waveform of an input signal in a prescribed man-ner to produce a waveform of a desired shape at the output. In this section we illustrate this application by a concrete example: the sine-wave shaper. This is a circuit whose purpose is to change the waveform of an input triangular-wave signal to a sine wave. Though simple, the sine-wave shaper is a practical building block used extensively in function generators.
This method of generating sine waves should be contrasted to that using linear oscillators (Sections 17.1–17.3). Although linear oscillators produce sine waves of high purity, they are not convenient at very low frequencies. Also, linear oscillators are in general more difficult to tune over wide frequency ranges. In the following we discuss two distinctly different tech-niques for designing sine-wave shapers.
17.8.1 The Breakpoint Method In the breakpoint method the desired nonlinear transfer characteristic (in our case the sine function shown in Fig. 17.30) is implemented as a piecewise linear curve. Diodes are utilized as switches that turn on at the various breakpoints of the transfer characteristic, thus switch-ing into the circuit additional resistors that cause the transfer characteristic to change slope.
Consider the circuit shown in Fig. 17.31(a). It consists of a chain of resistors connected across the entire symmetrical voltage supply +V, −V. The purpose of this voltage divider is to generate reference voltages that will serve to determine the breakpoints in the transfer char-acteristic. In our example these reference voltages are denoted +V2, +V1, −V1, −V2. Note that Figure 17.30 Using a nonlinear (sinusoidal) transfer characteristic to shape a triangular waveform into a sinusoid.
vO 0 t 0 T T 2 0 T 2 T vI 1376 Chapter 17 Signal Generators and Waveform-Shaping Circuits the entire circuit is symmetrical, driven by a symmetrical triangular wave and generating a symmetrical sine-wave output. The circuit approximates each quarter-cycle of the sine wave by three straight-line segments; the breakpoints between these segments are determined by the reference voltages V1 and V2.
The circuit works as follows: Let the input be the triangular wave shown in Fig. 17.31(b), and consider first the quarter-cycle defined by the two points labeled 0 and 1. When the input signal is less in magnitude than V1, none of the diodes conducts. Thus zero current flows through R4, and the output voltage at B will be equal to the input voltage. But as the input rises to V1 and above, D2 (assumed ideal) begins to conduct. Assuming that the conducting D2 behaves as a short circuit, we see that, for vI > V1, This implies that as the input continues to rise above V1, the output follows, but with a reduced slope. This gives rise to the second segment in the output waveform, as shown in Fig. 17.31(b). Note that in developing the equation above we have assumed that the resis-tances in the voltage divider are low enough in value to cause the voltages V1 and V2 to be constant independent of the current coming from the input.
Next consider what happens as the voltage at point B reaches the second breakpoint deter-mined by V2. At this point, D1 conducts, thus limiting the output vO to V2 (plus, of course, the voltage drop across D1 if it is not assumed to be ideal). This gives rise to the third segment, which is flat, in the output waveform. The overall result is to “bend” the waveform and shape it into an approximation of the first quarter-cycle of a sine wave. Then, beyond the Figure 17.31 (a) A three-segment sine-wave shaper. (b) The input triangular waveform and the output approximately sinusoidal waveform.
(a) D1 D1 D1 D2 D1 D3 D1 D4 (b) vO V1 vI V1 – ( ) R5 R4 R5 + -----------------+ = 17.8 Nonlinear Waveform-Shaping Circuits 1377 peak of the input triangular wave, as the input voltage decreases, the process unfolds, the output becoming progressively more like the input. Finally, when the input goes sufficiently negative, the process begins to repeat at −V1 and −V2 for the negative half-cycle.
Although the circuit is relatively simple, its performance is surprisingly good. A measure of goodness usually taken is to quantify the purity of the output sine wave by specifying the percentage total harmonic distortion (THD). This is the percentage ratio of the rms voltage of all harmonic components above the fundamental frequency (which is the frequency of the triangular wave) to the rms voltage of the fundamental (see also Chapter 11). Interestingly, one reason for the good performance of the diode shaper is the beneficial effects produced by the nonideal i–v characteristics of the diodes—that is, the exponential knee of the junction diode as it goes into forward conduction. The consequence is a relatively smooth transition from one line segment to the next.
Practical implementations of the breakpoint sine-wave shaper employ six to eight seg-ments (compared with the three used in the example above). Also, transistors are usually employed to provide more versatility in the design, with the goal being increased precision and lower THD (see Grebene, 1984, pages 592–595).
17.8.2 The Nonlinear-Amplification Method The other method we discuss for the conversion of a triangular wave into a sine wave is based on feeding the triangular wave to the input of an amplifier having a nonlinear transfer characteristic that approximates the sine function. One such amplifier circuit consists of a differential pair with a resistance connected between the two emitters, as shown in Fig. 17.32.
With appropriate choice of the values of the bias current I and the resistance R, the differ-ential amplifier can be made to have a transfer characteristic that closely approximates that shown in Fig. 17.30. Observe that for small vI the transfer characteristic of the circuit of Fig. 17.32 is almost linear, as a sine waveform is near its zero crossings. At large values of vI the nonlinear characteristics of the BJTs reduce the gain of the amplifier and cause the trans-fer characteristic to bend, approximating the sine wave as it approaches its peak. (More details on this circuit can be found in Grebene, 1984, pages 595–597.) Figure 17.32 A differential pair with an emitter-degeneration resistance used to implement a trian-gular-wave to sine-wave converter. Operation of the circuit can be graphically described by Fig. 17.30.
1378 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.9 Precision Rectifier Circuits Rectifier circuits were studied in Chapter 4, where the emphasis was on their application in power-supply design. In such applications, the voltages being rectified are usually much greater than the diode voltage drop, rendering the exact value of the diode drop unimportant to the proper operation of the rectifier. Other applications exist, however, where this is not the case. For instance, in instrumentation applications, the signal to be rectified can be of a very small amplitude, say 0.1 V, making it impossible to employ the conventional rectifier circuits. Also, in instrumentation applications, the need arises for rectifier circuits with very precise transfer characteristics.
In this section we study circuits that combine diodes and op amps to implement a variety of rectifier circuits with precise characteristics. Precision rectifiers, which can be considered a special class of wave-shaping circuits, find application in the design of instrumentation systems. An introduction to precision rectifiers was presented in Chapter 4. This material, however, is repeated here for the reader’s convenience.
17.9.1 Precision Half-Wave Rectifier—The “Superdiode” Figure 17.33(a) shows a precision half-wave-rectifier circuit consisting of a diode placed in the negative-feedback path of an op amp, with R being the rectifier load resistance. The circuit works as follows: If vI goes positive, the output voltage vA of the op amp will go positive and the diode will conduct, thus establishing a closed feedback path between the op amp’s output terminal and the negative input terminal. This negative-feedback path will EXERCISES D17.22 The circuit in Fig. E17.22 is required to provide a three-segment approximation to the nonlinear i–v characteristic, i = 0.1v2, where v is the voltage in volts and i is the current in milliamperes. Find the values of R1, R2, and R3 such that the approximation is perfect at v = 2 V, 4 V, and 8 V. Calculate the error in current value at v = 3 V, 5 V, 7 V, and 10 V. Assume ideal diodes.
Figure E17.22 Ans. 5 kΩ, 1.25 kΩ, 1.25 kΩ; −0.3 mA, +0.1 mA, −0.3 mA, 0 17.23 A detailed analysis of the circuit in Fig. 17.32 shows that its optimum performance occurs when the values of I and R are selected so that RI = 2.5VT, where VT is the thermal voltage. For this design, the peak amplitude of the input triangular wave should be 6.6VT, and the corresponding sine wave across R has a peak value of 2.42VT. For I = 0.25 mA and RC = 10 kΩ, find the peak amplitude of the sine-wave output vO. Assume α 1.
Ans. 4.84 V R3 i 7 V v 3 V R2 R1 17.9 Precision Rectifier Circuits 1379 cause a virtual short circuit to appear between the two input terminals of the op amp. Thus the voltage at the negative input terminal, which is also the output voltage vO, will equal (to within a few millivolts) that at the positive input terminal, which is the input voltage vI, Note that the offset voltage ( 0.5 V) exhibited in the simple half-wave-rectifier circuit is no longer present. For the op-amp circuit to start operation, vI has to exceed only a negligibly small voltage equal to the diode drop divided by the op amp’s open-loop gain. In other words, the straight-line transfer characteristic vO−vI almost passes through the origin. This makes this circuit suitable for applications involving very small signals.
Consider now the case when vI goes negative. The op amp’s output voltage vA will tend to follow and go negative. This will reverse-bias the diode, and no current will flow through resistance R, causing vO to remain equal to 0 V. Thus for vI < 0, vO = 0. Since in this case the diode is off, the op amp will be operating in an open-loop fashion and its output will be at the negative saturation level.
The transfer characteristic of this circuit will be that shown in Fig. 17.33(b), which is almost identical to the ideal characteristic of a half-wave rectifier. The nonideal diode characteristics have been almost completely masked by placing the diode in the negative-feedback path of an op amp. This is another dramatic application of negative feedback. The combination of diode and op amp, shown in the dashed box in Fig. 17.33(a), is appropriately referred to as a “superdiode.” As usual, though, not all is well. The circuit of Fig. 17.33 has some disadvantages: When vI goes negative and vO = 0, the entire magnitude of vI appears between the two input termi-nals of the op amp. If this magnitude is greater than a few volts, the op amp may be damaged unless it is equipped with what is called “overvoltage protection” (a feature that most mod-ern IC op amps have). Another disadvantage is that when vI is negative, the op amp will be saturated. Although not harmful to the op amp, saturation should usually be avoided, since getting the op amp out of the saturation region and back into its linear region of operation requires some time. This time delay will obviously slow down circuit operation and limit the frequency of operation of the superdiode half-wave-rectifier circuit.
17.9.2 An Alternative Circuit An alternative precision rectifier circuit that does not suffer from the disadvantages men-tioned above is shown in Fig. 17.34. The circuit operates in the following manner: For Figure 17.33 (a) The “superdiode” precision half-wave rectifier; (b) its almost ideal transfer characteristic.
Note that when vI > 0 and the diode conducts, the op amp supplies the load current, and the source is conve-niently buffered, an added advantage.
(a) (b) vO vI = vI 0 ≥ 1380 Chapter 17 Signal Generators and Waveform-Shaping Circuits positive vI, diode D2 conducts and closes the negative-feedback loop around the op amp. A virtual ground therefore will appear at the inverting input terminal, and the op amp’s output will be clamped at one diode drop below ground. This negative voltage will keep diode D1 off, and no current will flow in the feedback resistance R2. It follows that the rectifier output voltage will be zero.
As vI goes negative, the voltage at the inverting input terminal will tend to go negative, causing the voltage at the op amp’s output terminal to go positive. This will cause D2 to be reverse-biased and hence to be cut off. Diode D1, however, will conduct through R2, thus establishing a negative-feedback path around the op amp and forcing a virtual ground to appear at the inverting input terminal. The current through the feedback resistance R2 will be equal to the current through the input resistance R1. Thus for R1 = R2 the output voltage vO will be The transfer characteristic of the circuit is shown in Fig. 17.34(b). Note that unlike the situation for the circuit shown in Fig. 17.33, here the slope of the characteristic can be set to any desired value, including unity, by selecting appropriate values for R1 and R2.
As mentioned before, the major advantage of the improved half-wave-rectifier circuit is that the feedback loop around the op amp remains closed at all times. Hence the op amp remains in its linear operating region, avoiding the possibility of saturation and the associ-ated time delay required to “get out” of saturation. Diode D2 “catches” the op-amp output voltage as it goes negative and clamps it to one diode drop below ground; hence D2 is called a “catching diode.” 17.9.3 An Application: Measuring AC Voltages As one of the many possible applications of the precision rectifier circuits discussed in this section, consider the basic ac voltmeter circuit shown in Fig. 17.35. The circuit consists of a half-wave rectifier—formed by op amp A1, diodes D1 and D2, and resistors R1 and R2—and a first-order low-pass filter—formed by op amp A2, resistors R3 and R4, and capacitor C. For an input sinusoid having a peak amplitude Vp the output v1 of the rectifier will consist of a half sine wave having a peak amplitude of Vp . It can be shown using Fourier series analysis that the waveform of v1 has an average value of ( )( ) in addition to Figure 17.34 (a) An improved version of the precision half-wave rectifier: Diode D2 is included to keep the feedback loop closed around the op amp during the off times of the rectifier diode D1, thus preventing the op amp from saturating. (b) The transfer characteristic for R2 = R1.
(a) D1 D2 (b) vO v – I vI 0 ≤ = R2 R1 ⁄ V p π ⁄ R2 R1 ⁄ 17.9 Precision Rectifier Circuits 1381 Figure 17.35 A simple ac voltmeter consisting of a precision half-wave rectifier followed by a first-order low-pass filter.
D2 D1 EXERCISES 17.24 Consider the operational rectifier or superdiode circuit of Fig. 17.33(a), with R = 1 kΩ. For vI = 10 mV, 1 V, and −1 V, what are the voltages that result at the rectifier output and at the output of the op amp? Assume that the op amp is ideal and that its output saturates at ±12 V. The diode has a 0.7-V drop at 1-mA current, and the voltage drop changes by 0.1 V per decade of current change.
Ans. 10 mV, 0.51 V; 1 V, 1.7 V; 0 V, –12 V 17.25 If the diode in the circuit of Fig. 17.33(a) is reversed, what is the transfer characteristic vO as a function of vI?
Ans. vO = 0 for vI ≥ 0; vO = vI for vI ≤ 0 17.26 Consider the circuit in Fig. 17.34(a) with R1 = 1 kΩ and R2 = 10 kΩ. Find vO and the voltage at the amplifier output for vI = +1 V, −10 mV, and −1 V. Assume the op amp to be ideal with saturation voltages of ±12 V. The diodes have 0.7-V voltage drops at 1 mA, and the voltage drop changes by 0.1 V per decade of current change.
Ans. 0 V, −0.vm7 V; 0.1 V, 0.6 V; 10 V, 10.7 V 17.27 If the diodes in the circuit of Fig. 17.34(a) are reversed, what is the transfer characteristic vO as a function of vI?
Ans. vO = −( )vI for vI ≥ 0; vO = 0 for vI ≤ 0 17.28 Find the transfer characteristic for the circuit in Fig. E17.28.
Figure E17.28 Ans. vO = 0 for vI ≥ −5 V; vO = −vI − 5 for vI ≤ −5 V R2 R1 ⁄ D2 D1 1382 Chapter 17 Signal Generators and Waveform-Shaping Circuits harmonics of the frequency ω of the input signal. To reduce the amplitudes of all these harmonics to negligible levels, the corner frequency of the low-pass filter should be chosen to be much smaller than the lowest expected frequency ωmin of the input sine wave. This leads to ! ωmin Then the output voltage v2 will be mostly dc, with a value where is the dc gain of the low-pass filter. Note that this voltmeter essentially mea-sures the average value of the negative parts of the input signal but can be calibrated to provide rms readings for input sinusoids. 17.9.4 Precision Full-Wave Rectifier We now derive a circuit for a precision full-wave rectifier. From Chapter 4 we know that full-wave rectification is achieved by inverting the negative halves of the input-signal wave-form and applying the resulting signal to another diode rectifier. The outputs of the two rec-tifiers are then joined to a common load. Such an arrangement is depicted in Fig. 17.36, which also shows the waveforms at various nodes. Now replacing diode DA with a super-diode, and replacing diode DB and the inverting amplifier with the inverting precision half-wave rectifier of Fig. 17.34 but without the catching diode, we obtain the precision full-wave-rectifier circuit of Fig. 17.37(a).
To see how the circuit of Fig. 17.37(a) operates, consider first the case of positive input at A. The output of A2 will go positive, turning D2 on, which will conduct through RL and thus close the feedback loop around A2. A virtual short circuit will thus be established between the two input terminals of A2, and the voltage at the negative-input terminal, which is the output voltage of the circuit, will become equal to the input. Thus no current will flow through R1 and R2, and the voltage at the inverting input of A1 will be equal to the input and hence positive. Therefore the output terminal (F) of A1 will go negative until A1 saturates.
This causes D1 to be turned off.
Next consider what happens when A goes negative. The tendency for a negative voltage at the negative input of A1 causes F to rise, making D1 conduct to supply RL and allowing the feedback loop around A1 to be closed. Thus a virtual ground appears at the negative input of A1, and the two equal resistances R1 and R2 force the voltage at C, which is the output Figure 17.36 Principle of full-wave rectification.
1 CR4 ---------- V2 V p π -----R2 R1 -----R4 R3 -----– = R4 R3 ⁄ RL DA DB A C B 1 A B C or 17.9 Precision Rectifier Circuits 1383 voltage, to be equal to the negative of the input voltage at A and thus positive. The combina-tion of positive voltage at C and negative voltage at A causes the output of A2 to saturate in the negative direction, thus keeping D2 off.
Figure 17.37 (a) Precision full-wave rectifier based on the conceptual circuit of Fig. 17.36. (b) Transfer characteristic of the circuit in (a).
A2 A E C vI D2 R1 D1 RL R2 F vO A1 (a) vI 0 vO (b) EXERCISES 17.29 In the full-wave rectifier circuit of Fig. 17.37(a), let R1 = R2 = RL = 10 kΩ and assume the op amps to be ideal except for output saturation at ±12 V. When conducting a current of 1 mA, each diode exhibits a voltage drop of 0.7 V, and this voltage changes by 0.1 V per decade of current change.
Find vO, vE, and vF corresponding to vI = +0.1 V, +1 V, +10 V, –0.1 V, and −10 V.
Ans. + 0.1 V, + 0.6 V, −12 V; +1 V, +1.6 V, −12 V; +10 V, +10.7 V, −12 V; + 0.1 V, −12 V, + 0.63 V; +1 V, −12 V, + 1.63 V; +10 V, −12 V, +10.73 V D17.30 The block diagram shown in Fig. E17.30(a) gives another possible arrangement for implementing the absolute-value or full-wave-rectifier operation depicted symbolically in Fig. E17.30(b). The block diagram consists of two boxes: a half-wave rectifier, which can be implemented by the cir-cuit in Fig. 17.34(a) after reversing both diodes, and a weighted inverting summer. Convince yourself that this block diagram does in fact realize the absolute-value operation. Then draw a complete circuit diagram, giving reasonable values for all resistors.
Figure E17.30 (a) (b) 1384 Chapter 17 Signal Generators and Waveform-Shaping Circuits The overall result is perfect full-wave rectification, as represented by the transfer charac-teristic in Fig. 17.37(b). This precision is, of course, a result of placing the diodes in op-amp feedback loops, thus masking their nonidealities. This circuit is one of many possible preci-sion full-wave-rectifier or absolute-value circuits. Another related implementation of this function is examined in Exercise 17.30.
17.9.5 A Precision Bridge Rectifier for Instrumentation Applications The bridge rectifier circuit studied in Chapter 4 can be combined with an op amp to provide useful precision circuits. One such arrangement is shown in Fig. 17.38. This circuit causes a current equal to to flow through the moving-coil meter M. Thus the meter provides a reading that is proportional to the average of the absolute value of the input voltage vA. All the nonidealities of the meter and of the diodes are masked by placing the bridge circuit in the negative-feedback loop of the op amp. Observe that when vA is positive, current flows from the op-amp output through D1, M, D3, and R. When vA is negative, current flows into the op-amp output through R, D2, M, and D4. Thus the feedback loop remains closed for both polarities of vA. The resulting virtual short circuit at the input terminals of the op amp causes a replica of vA to appear across R. The circuit of Fig. 17.38 provides a relatively accurate high-input-impedance ac voltmeter using an inexpensive moving-coil meter. D1 D4 D2 D3 Figure 17.38 Use of the diode bridge in the design of an ac voltmeter.
vA R ⁄ EXERCISES D17.31 In the circuit of Fig. 17.38, find the value of R that would cause the meter to provide a full-scale reading when the input voltage is a sine wave of 5 V rms. Let meter M have a 1-mA, 50-Ω move-ment (i.e., its resistance is 50 Ω, and it provides full-scale deflection when the average current through it is 1 mA). What are the approximate maximum and minimum voltages at the op amp’s output? Assume that the diodes have constant 0.7-V drops when conducting.
Ans. 4.5 kΩ; +8.55 V; −8.55 V 17.9 Precision Rectifier Circuits 1385 17.9.6 Precision Peak Rectifiers Including the diode of the peak rectifier studied in Chapter 4 inside the negative-feedback loop of an op amp, as shown in Fig. 17.39, results in a precision peak rectifier. The diode– op-amp combination will be recognized as the superdiode of Fig. 17.33(a). Operation of the circuit in Fig. 17.39 is quite straightforward. For vI greater than the output voltage, the op amp will drive the diode on, thus closing the negative-feedback path and causing the op amp to act as a follower. The output voltage will therefore follow that of the input, with the op amp supplying the capacitor-charging current. This process continues until the input reaches its peak value. Beyond the positive peak, the op amp will see a negative voltage between its input terminals. Thus its output will go negative to the saturation level and the diode will turn off. Except for possible discharge through the load resistance, the capacitor will retain a voltage equal to the positive peak of the input. Inclusion of a load resistance is essential if the circuit is required to detect reductions in the magnitude of the positive peak.
17.9.7 A Buffered Precision Peak Detector When the peak detector is required to hold the value of the peak for a long time, the capacitor should be buffered, as shown in the circuit of Fig. 17.40. Here op amp A2, which should have high input impedance and low input bias current, is connected as a voltage follower. The remainder of the circuit is quite similar to the half-wave-rectifier circuit of Fig. 17.34. While diode D1 is the essential diode for the peak-rectification operation, diode D2 acts as a catch-ing diode to prevent negative saturation, and the associated delays, of op amp A1. During the holding state, follower A2 supplies D2 with a small current through R. The output of op amp A1 will then be clamped at one diode drop below the input voltage. Now if the input vI increases above the value stored on C, which is equal to the output voltage vO, op amp A1 sees Figure 17.39 A precision peak rectifier obtained by placing the diode in the feedback loop of an op amp.
Figure 17.40 A buffered precision peak rectifier.
D1 D2 1386 Chapter 17 Signal Generators and Waveform-Shaping Circuits a net positive input that drives its output toward the positive saturation level, turning off diode D2. Diode D1 is then turned on and capacitor C is charged to the new positive peak of the input, after which time the circuit returns to the holding state. Finally, note that this cir-cuit has a low-impedance output.
17.9.8 A Precision Clamping Circuit By replacing the diode in the clamping circuit studied in Chapter 4 with a “superdiode,” the precision clamp of Fig. 17.41 is obtained. Operation of this circuit should be self-explanatory.
Figure 17.41 A precision clamping circuit.
There are two distinctly different types of signal genera-tor: the linear oscillator, which utilizes some form of resonance, and the nonlinear oscillator or function gener-ator, which employs a switching mechanism imple-mented with a multivibrator circuit.
A linear oscillator can be realized by placing a frequency-selective network in the feedback path of an amplifier (an op amp or a transistor). The circuit will oscillate at the frequency at which the total phase shift around the loop is zero, provided that the magnitude of loop gain at this frequency is equal to, or greater than, unity.
If in an oscillator the magnitude of loop gain is greater than unity, the amplitude will increase until a nonlinear amplitude-control mechanism is activated.
The Wien-bridge oscillator, the phase-shift oscillator, the quadrature oscillator, and the active-filter-tuned oscillator are popular configurations for frequencies up to about 1 MHz. These circuits employ RC networks together with op amps or transistors. For higher frequencies, LC-tuned or crystal-tuned oscillators are utilized. A popular config-uration is the Colpitts circuit.
Crystal oscillators provide the highest possible frequency accuracy and stability.
There are three types of multivibrator: bistable, monostable, and astable. Op-amp circuit implementa-tions of multivibrators are useful in analog-circuit appli-cations that require high precision. The bistable multivibrator has two stable states and can remain in either state indefinitely. It changes state when triggered. A comparator with hysteresis is bistable.
A monostable multivibrator, also known as a one-shot, has one stable state, in which it can remain indefinitely.
When triggered, it goes into a quasi-stable state in which it remains for a predetermined interval, thus generating, at its output, a pulse of known width.
An astable multivibrator has no stable state. It oscillates between two quasi-stable states, remaining in each for a predetermined interval. It thus generates a periodic waveform at the output.
A feedback loop consisting of an integrator and a bistable multivibrator can be used to generate triangular and square waveforms.
The 555 timer, a commercially available IC, can be used with external resistors and a capacitor to implement high-quality monostable and astable multivibrators.
A sine waveform can be generated by feeding a triangular waveform to a sine-wave shaper. A sine-wave shaper can be implemented either by using diodes (or transistors) and resistors, or by using an amplifier having a nonlinear transfer characteristic that approximates the sine function.
Diodes can be combined with op amps to implement pre-cision rectifier circuits in which negative feed-back serves to mask the nonidealities of the diode characteristics.
Summary Problems involving design are marked with D throughout the text. As well, problems are marked with asterisks to describe their degree of difficulty. Difficult problems are marked with an asterisk (); more difficult problems with two asterisks (); and very challenging and/or time-consuming problems with three asterisks ().
Section 17.1: Basic Principles of Sinusoidal Oscillators 17.1 Consider a sinusoidal oscillator consisting of an amplifier having a frequency-independent gain A (where A is positive) and a second-order bandpass filter with a pole frequency ω0, a pole Q denoted Q, and a center-frequency gain K.
(a) Find the frequency of oscillation, and the condition that A and K must satisfy for sustained oscillation.
(b) Derive an expression for , evaluated at ω = ω0.
(c) Use the result of (b) to find an expression for the per-unit change in frequency of oscillation resulting from a phase-angle change of , in the amplifier transfer function.
17.2 For the oscillator described in Problem 17.1, show that, independent of the value of A and K, the poles of the circuit lie at a radial distance of ω0. Find the value of AK that results in poles appearing (a) on the jω axis, and (b) in the right-half of the s plane, at a horizontal distance from the jω axis of .
D 17.3 Sketch a circuit for a sinusoidal oscillator formed by an ideal op amp connected in the noninverting configu-ration and a bandpass filter implemented by an RLC reso-nator (such as that in Fig. 16.18d). What should the amplifier gain be to obtain sustained oscillation? What is the frequency of oscillation? Find the percentage change in ω0 resulting from a change of +1% in the value of (a) L, (b) C, and (c) R.
17.4 An oscillator is formed by loading a transconduc-tance amplifier having a positive gain with a parallel RLC circuit and connecting the output directly to the input (thus applying positive feedback with a factor β = 1). Let the transconductance amplifier have an input resistance of 10 kΩ and an output resistance of 10 kΩ.. The LC resonator has L = 10 μH, C = 1000 pF, and Q = 100. For what value of transconductance Gm will the circuit oscillate? At what frequency?
17.5 In a particular oscillator characterized by the structure of Fig. 17.1, the frequency-selective network exhibits a loss of 20 dB and a phase shift of 180° at ω0. What is the mini-mum gain and the phase shift that the amplifier must have for oscillation to begin?
D 17.6 Consider the circuit of Fig. 17.3(a) with Rf removed to realize the comparator function. Find suitable values for all resistors so that the comparator output levels are ±6 V and the slope of the limiting characteristic is 0.1. Use power-supply voltages of ±10 V and assume the voltage drop of a conduct-ing diode to be 0.7 V.
D 17.7 Consider the circuit of Fig. 17.3(a) with Rf removed to realize the comparator function. Sketch the transfer characteristic. Show that by connecting a dc source VB to the virtual ground of the op amp through a resistor RB, the transfer characteristic is shifted along the vI axis to the point . Utilizing available ±15-V dc sup-plies for ±V and for VB, find suitable component values so that the limiting levels are ±5 V and the comparator thresh-old is at vI = +5 V. Neglect the diode voltage drop (i.e., assume that VD = 0). The input resistance of the comparator is to be 100 kΩ, and the slope in the limiting regions is to be ≤0.05 V/V. Use standard 5% resistors (see Appendix H).
17.8 Denoting the zener voltages of Z1 and Z2 by VZ1 and VZ2 and assuming that in the forward direction the voltage drop is approximately 0.7 V, sketch and clearly label the transfer characteristics vO–vI of the circuits in Fig. P17.8.
Assume the op amps to be ideal.
Section 17.2: Op Amp–RC Oscillator Circuits 17.9 For the Wien-bridge oscillator circuit in Fig. 17.4, show that the transfer function of the feedback network is that of a bandpass filter. Find ω0 and Q of the poles, and find the center-frequency gain.
17.10 For the Wien-bridge oscillator of Fig. 17.4, let the closed-loop amplifier (formed by the op amp and the resistors R1 and R2) exhibit a phase shift of −0.1 rad in the neighborhood of . Find the frequency at which oscillations can occur in this case in terms of CR. (Hint: Use Eq. 17.11.) dφ dω ⁄ Δφ Hint: d dx ------ tan 1 – y ( ) 1 1 y2 + --------------dy dx ------= ω0 2Q ( ) ⁄ vI R1 RB ⁄ ( )V B – = [V a s ( ) V o ⁄ s ( )] ω = 1 CR ⁄ PROBLEMS CHAPTER 17 PR OBLE MS 1388 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.11 For the Wien-bridge oscillator of Fig. 17.4, use the expression for loop gain in Eq. (17.10) to find the poles of the closed-loop system. Give the expression for the pole Q, and use it to show that to locate the poles in the right half of the s plane, must be selected to be greater than 2.
D17.12 Reconsider Exercise 17.3 with R3 and R6 increased to reduce the output voltage. What values are required for a peak-to-peak output of 10 V? What results if R3 and R6 are open-circuited?
17.13 For the circuit in Fig. P17.13, find L(s), L( jω), the frequency for zero loop phase, and for oscillation.
Figure P17.13 17.14 Repeat Problem 17.13 for the circuit in Fig. P17.14.
17.15 Consider the circuit of Fig. 17.6 with the 50-kΩ potentiometer replaced by two fixed resistors: 10 kΩ between the op amp’s negative input and ground, and 18 kΩ.. Model-ing each diode as a 0.65-V battery in series with a 100-Ω resistance, find the peak-to-peak amplitude of the output sinusoid.
D17.16 Redesign the circuit of Fig. 17.6 for operation at 10 kHz using the same values of resistance. If at 10 kHz the op amp provides an excess phase shift (lag) of 5.7°, what will be the frequency of oscillation? (Assume that the phase shift introduced by the op amp remains constant for frequen-cies around 10 kHz.) To restore operation to 10 kHz, what change must be made in the shunt resistor of the Wien bridge? Also, to what value must be changed?
17.17 For the circuit of Fig. 17.8, connect an additional R = 10 kΩ resistor in series with the rightmost capacitor C.
For this modification (and ignoring the amplitude stabiliza-tion circuitry) find the loop gain Aβ by breaking the circuit at node X. Find Rf for oscillation to begin, and find f0.
D 17.18 For the circuit in Fig. P17.18, break the loop at node X and find the loop gain (working backward for simplic-ity to find Vx in terms of Vo). For R = 10 kΩ, find C and Rf to obtain sinusoidal oscillations at 10 kHz.
17.19 Consider the quadrature-oscillator circuit of Fig. 17.9 without the limiter. Let the resistance Rf be equal to Figure P17.8 (a) (b) R2 R1 ⁄ R2 R1 ⁄ C R1 R2 C R R Figure P17.14 R2 R1 ⁄ CHAPTER 17 PR OBLEM S Problems 1389 where Δ ! 1. Show that the poles of the char-acteristic equation are in the right-half s plane and given by 17.20 Assuming that the diode-clipped waveform in Exercise 17.7 is nearly an ideal square wave and that the resonator Q is 20, provide an estimate of the distortion in the output sine wave by calculating the magnitude (relative to the fundamental) of (a) the second harmonic (b) the third harmonic (c) the fifth harmonic (d) the rms of harmonics to the tenth Note that a square wave of amplitude V and frequency ω is represented by the series Section 17.3: LC and Crystal Oscillators 17.21 Figure P17.21 shows four oscillator circuits of the Colpitts type, complete with bias detail. For each circuit, derive an equation governing circuit operation and find the frequency of oscillation and the gain condition that ensures that oscillations start.
17.22 Consider the oscillator circuit in Fig. P17.22, and assume for simplicity that β = ∞.
(a) Find the frequency of oscillation and the minimum value of RC (in terms of the bias current I ) for oscillation to start.
(b) If RC is selected equal to (1/I ) kΩ, where I is in milli-amperes, convince yourself that oscillations will start. If oscillations grow to the point that Vo is large enough to turn the BJTs on and off, show that the voltage at the col-lector of Q2 will be a square wave of 1 V peak to peak.
Estimate the peak-to-peak amplitude of the output sine wave Vo.
17.23 Consider the Pierce crystal oscillator of Fig. 17.16 with the crystal as specified in Exercise 17.10. Let C1 be variable in the range 1 pF to 10 pF, and let C2 be fixed at 10 pF. Find the range over which the oscillation frequency can be tuned. (Hint: Use the result in the statement leading to the expression in Eq. 17.27.) Figure P17.18 2R 1 Δ + ( ) ⁄ , s 1 CR ⁄ ( ) Δ 4 ⁄ ( ) j ± [ ].
4V π ------- sin ωt 1 3 ---+ 3ω sin t 1 5 ---5ωt 1 7 ---+ 7ωt . . .
+ sin sin + ⎝ ⎠ ⎛ ⎞ C2 C1 L I RL Q1 (a) C2 L Q1 C1 RL (b) I Figure P17.21 CHAPTER 17 PR OBLE MS 1390 Chapter 17 Signal Generators and Waveform-Shaping Circuits Section 17.4: Bistable Multivibrators 17.24 Consider the bistable circuit of Fig. 17.19(a) with the op amp’s positive-input terminal connected to a positive-voltage source V through a resistor R3.
(a) Derive expressions for the threshold voltages VTL and VTH in terms of the op amp’s saturation levels L+ and L−, R1, R2, R3, and V.
(b) Let L+ = −L− = 13 V, V = 15 V, and R1 = 10 kΩ. Find the values of R2 and R3 that result in VTL = +4.9 V and VTH = +5.1 V.
17.25 Consider the bistable circuit of Fig. 17.20(a) with the op amp’s negative-input terminal disconnected from ground and connected to a reference voltage VR.
(a) Derive expressions for the threshold voltages VTL and VTH in terms of the op amp’s saturation levels L+ and L−, R1, R2, and VR.
(b) Let L+ = −L− = V and R1 = 10 kΩ. Find R2 and VR that result in threshold voltages of 0 and V/10.
17.26 For the circuit in Fig. P17.26, sketch and label the transfer characteristic vO−vI. The diodes are assumed to have a constant 0.7-V drop when conducting, and the op amp saturates at ±12 V. What is the maximum diode current?
17.27 Consider the circuit of Fig. P17.26 with R1 elimi-nated and R2 short-circuited. Sketch and label the transfer characteristic vO−vI. Assume that the diodes have a constant 0.7-V drop when conducting and that the op amp saturates at ±12 V.
Q1 C2 RL C1 L I (c) C2 Rf Q1 C1 0 I L (Assume ) Rf RL L (d) Figure P17.21 (Continued ) Figure P17.22 CHAPTER 17 PR OBLEM S Problems 1391 17.28 Consider a bistable circuit having a noninverting transfer characteristic with L+ = −L− = 12 V, VTL = −1 V, and VTH = +1 V.
(a) For a 0.5-V-amplitude sine-wave input having zero average, what is the output?
(b) Describe the output if a sinusoid of frequency f and amplitude of 1.1 V is applied at the input. By how much can the average of this sinusoidal input shift before the output becomes a constant value?
D 17.29 Design the circuit of Fig. 17.23(a) to realize a transfer characteristic with ±7.5-V output levels and ±7.5-V threshold values. Design so that when vI = 0 V a current of 0.1 mA flows in the feedback resistor and a current of 1 mA flows through the zener diodes. Assume that the out-put saturation levels of the op amp are ±12 V. Specify the voltages of the zener diodes and give the values of all resistors.
Section 17.5: Generation of Square and Triangular Waveforms Using Astable Multivibrators 17.30 Find the frequency of oscillation of the circuit in Fig. 17.24(b) for the case R1 = 10 kΩ, R2 = 16 kΩ, C = 10 nF, and R = 62 kΩ.
D 17.31 Augment the astable multivibrator circuit of Fig. 17.24(b) with an output limiter of the type shown in Fig. 17.23(b). Design the circuit to obtain an output square wave with 5-V amplitude and 1-kHz frequency using a 10-nF capacitor C. Use β = 0.462, and design for a current in the resistive divider approximately equal to the average cur-rent in the RC network over a half-cycle. Assuming ±13-V op-amp saturation voltages, arrange for the zener to operate at a current of 1 mA.
D 17.32 Using the scheme of Fig. 17.25, design a circuit that provides square waves of 10 V peak to peak and trian-gular waves of 10 V peak to peak. The frequency is to be 1 kHz. Implement the bistable circuit with the circuit of Fig. 17.23(b). Use a 0.01-μF capacitor and specify the values of all resistors and the required zener voltage. Design for a minimum zener current of 1 mA and for a maximum current in the resistive divider of 0.2 mA. Assume that the output saturation levels of the op amps are ±13 V.
D17.33 The circuit of Fig. P17.33 consists of an inverting bistable multivibrator with an output limiter and a nonin-verting integrator. Using equal values for all resistors except R7 and a 0.5-nF capacitor, design the circuit to obtain a square wave at the output of the bistable multivibrator of 15-V peak-to-peak amplitude and 10-kHz frequency. Sketch and label the waveform at the integrator output. Assuming ±13-V op-amp saturation levels, design for a minimum zener current of 1 mA. Specify the zener voltage required, and give the values of all resistors.
Figure P17.26 R4 R7 R5 R6 Z1 R3 C R1 R2 Z2 Figure P17.33 CHAPTER 17 PR OBLE MS 1392 Chapter 17 Signal Generators and Waveform-Shaping Circuits Section 17.6: Generation of a Standardized Pulse—The Monostable Multivibrator 17.34 Figure P17.34 shows a monostable multivibrator circuit. In the stable state, vO = L+, vA = 0, and vB = −Vref.
The circuit can be triggered by applying a positive input pulse of height greater than Vref. For normal operation, C1R1 CR. Show the resulting waveforms of vO and vA.
Also, show that the pulse generated at the output will have a width T given by Note that this circuit has the interesting property that the pulse width can be controlled by changing Vref.
17.35 For the monostable circuit considered in Exer-cise 17.19, calculate the recovery time.
D17.36 Using the circuit of Fig. 17.26, with a nearly ideal op amp for which the saturation levels are ±13 V, design a monostable multivibrator to provide a negative output pulse of 100-μs duration. Use capacitors of 0.1 nF and 1 nF. Wher-ever possible, choose resistors of 100 kΩ in your design.
Diodes have a drop of 0.7 V. What is the minimum input step size that will ensure triggering? How long does the cir-cuit take to recover to a state in which retriggering is possi-ble with a normal output?
Section 17.7: Integrated-Circuit Timers 17.37 Consider the 555 circuit of Fig. 17.27 when the Threshold and the Trigger input terminals are joined together and connected to an input voltage vI. Verify that the transfer characteristic vO–vI is that of an inverting bistable circuit with thresholds and and out-put levels of 0 and VCC.
17.38 (a) Using a 1-nF capacitor C in the circuit of Fig. 17.28(a), find the value of R that results in an output pulse of 10-μs duration.
(b) If the 555 timer used in (a) is powered with VCC = 15 V, and assuming that VTH can be varied externally (i.e., it need not remain equal to ), find its required value so that the pulse width is increased to 20 μs, with other conditions the same as in (a).
D 17.39 Using a 680-pF capacitor, design the astable circuit of Fig. 17.29(a) to obtain a square wave with a 50-kHz fre-quency and a 75% duty cycle. Specify the values of RA and RB.
17.40 The node in the 555 timer at which the voltage is VTH (i.e., the inverting input terminal of comparator 1) is usually connected to an external terminal. This allows the user to change VTH externally (i.e., VTH no longer remains at ). Note, however, that whatever the value of VTH becomes, VTL always remains .
(a) For the astable circuit of Fig. 17.29, rederive the expres-sions for TH and TL, expressing them in terms of VTH and VTL.
(b) For the case C = 1 nF, RA = 7.2 kΩ, RB = 3.6 kΩ, and VCC = 5 V, find the frequency of oscillation and the duty cycle of the resulting square wave when no external voltage is applied to the terminal VTH.
(c) For the design in (b), let a sine-wave signal of a much lower frequency than that found in (b) and of 1-V peak amplitude be capacitively coupled to the circuit node VTH.
This signal will cause VTH to change around its quiescent value of , and thus TH will change correspondingly—a modulation process. Find TH, and find the frequency of oscil-lation and the duty cycle at the two extreme values of VTH.
Section 17.8: Nonlinear Waveform-Shaping Circuits D17.41 The two-diode circuit shown in Fig. P17.41 can provide a crude approximation to a sine-wave output when driven by a triangular waveform. To obtain a good approxi-mation, we select the peak of the triangular waveform, V, so that the slope of the desired sine wave at the zero crossings is equal to that of the triangular wave. Also, the value of R is selected so that when vI is at its peak, the output voltage is equal to the desired peak of the sine wave. If the diodes exhibit a voltage drop of 0.7 V at 1-mA current, changing at the rate of 0.1 V per decade, find the values of V and R that will yield an approximation to a sine waveform of 0.7-V peak amplitude. Then find the angles θ (where θ = 90° when vI is at its peak) at which the output of the circuit, in volts, is 0.7, 0.65, 0.6, 0.55, 0.5, 0.4, 0.3, 0.2, 0.1, and 0. Use the angle values obtained to determine the values of the exact sine wave (i.e., 0.7 sin θ), and thus find the percentage error of this circuit as a sine shaper. Provide your results in tabular form.
T CR ln L+ L− – V ref -----------------⎝ ⎠ ⎛ ⎞ = Figure P17.34 VTL = 1 3 --- V CC V TH = 2 3 --- V CC 2 3 --- V CC 2 3 --- V CC 1 2 ---V TH 2 3 --- V CC CHAPTER 17 PR OBLEM S Problems 1393 D 17.42 Design a two-segment sine-wave shaper using a 10-kΩ-input resistor, two diodes, and two clamping volt-ages. The circuit, fed by a 10-V peak-to-peak triangular wave, should limit the amplitude of the output signal via a 0.7-V diode to a value corresponding to that of a sine wave whose zero-crossing slope matches that of the triangle. What are the clamping voltages you have chosen?
17.43 Show that the output voltage of the circuit in Fig. P17.43 is given by where IS is the saturation current of the diode and VT is the thermal voltage. Since the output voltage is proportional to the logarithm of the input voltage, the circuit is known as a logarithmic amplifier. Such amplifiers find application in situations where it is desired to compress the signal range.
17.44 Verify that the circuit in Fig. P17.44 implements the transfer characteristic vO = v1v2 for v1, v2 > 0. Such a circuit is known as an analog multiplier. Check the circuit’s perfor-mance for various combinations of input voltage of values, say, 0.5 V, 1 V, 2 V, and 3 V. Assume all diodes to be identi-cal, with 700-mV drop at 1-mA current. Note that a squarer can easily be produced using a single input (e.g., v1) con-nected via a 0.5-kΩ resistor (rather than the 1-kΩ resistor shown).
Figure P17.41 vO VT ln vI ISR --------⎝ ⎠ ⎛ ⎞ – = vI 0 > , Figure P17.43 Figure P17.44 D1 D2 D3 D4 A B C D CHAPTER 17 PR OBLE MS 1394 Chapter 17 Signal Generators and Waveform-Shaping Circuits 17.45 Detailed analysis of the circuit in Fig. 17.32 shows that optimum performance (as a sine shaper) occurs when the values of I and R are selected so that RI = 2.5VT, where VT is the thermal voltage, and the peak amplitude of the input triangular wave is 6.6VT. If the output is taken across R (i.e., between the two emitters), find vI corresponding to vO = 0.25VT, 0.5VT, VT, 1.5VT, 2VT, 2.4VT, and 2.42VT. Plot vO–vI and compare to the ideal curve given by Section 17.9: Precision Rectifier Circuits 17.46 Two superdiode circuits connected to a common-load resistor and having the same input signal have their diodes reversed, one with cathode to the load, the other with anode to the load. For a sine-wave input of 10 V peak to peak, what is the output waveform? Note that each half-cycle of the load current is provided by a separate amplifier, and that while one amplifier supplies the load current, the other amplifier idles. This idea, called class-B operation (see Chapter 11), is important in the implementation of power amplifiers.
D 17.47 The superdiode circuit of Fig. 17.33(a) can be made to have gain by connecting a resistor R2 in place of the short circuit between the cathode of the diode and the nega-tive-input terminal of the op amp, and a resistor R1 between the negative-input terminal and ground. Design the circuit for a gain of 2. For a 10-V peak-to-peak input sine wave, what is the average output voltage resulting?
D 17.48 Provide a design of the inverting precision recti-fier shown in Fig. 17.34(a) in which the gain is −2 for nega-tive inputs and zero otherwise, and the input resistance is 100 kΩ. What values of R1 and R2 do you choose?
D17.49 Provide a design for a voltmeter circuit similar to the one in Fig. 17.35, which is intended to function at frequencies of 10 Hz and above. It should be calibrated for sine-wave input signals to provide an output of +10 V for an input of 1 V rms. The input resistance should be as high as possible. To extend the bandwidth of operation, keep the gain in the ac part of the circuit reasonably small. As well, the design should result in reduction of the size of the capacitor C required. The largest value of resistor available is 1 MΩ.
17.50 Plot the transfer characteristic of the circuit in Fig. P17.50.
17.51 Plot the transfer characteristics vO1–vI and vO2–vI of the circuit in Fig. P17.51.
17.52 Sketch the transfer characteristics of the circuit in Fig. P17.52.
D 17.53 A circuit related to that in Fig. 17.38 is to be used to provide a current proportional to to a light-emitting diode (LED). The value of the current is to vO = 2.42VT vI 6.6 VT --------------90° × ⎝ ⎠ ⎛ ⎞ sin 2R vI R 15 V R vO R D1 D2 Figure P17.50 D1 D2 vO2 vO1 Figure P17.51 Figure P17.52 vA vA 0 ≥ ( ) CHAPTER 17 PR OBLEM S Problems 1395 be independent of the diode’s nonlinearities and variability.
Indicate how this may be done easily.
17.54 In the precision rectifier of Fig. 17.38, the resistor R is replaced by a capacitor C. What happens? For equivalent performance with a sine-wave input of 60-Hz frequency with R = 1 kΩ, what value of C should be used? What is the response of the modified circuit at 120 Hz? At 180 Hz? If the amplitude of vA is kept fixed, what new function does this circuit perform? Now consider the effect of a waveform change on both circuits (the one with R and the one with C).
For a triangular-wave input of 60-Hz frequency that pro-duces an average meter current of 1 mA in the circuit with R, what does the average meter current become when R is replaced with the C whose value was just calculated?
17.55 A positive-peak rectifier utilizing a fast op amp and a junction diode in a superdiode configuration, and a 10-μF capacitor initially uncharged, is driven by a series of 10-V pulses of 10-μs duration. If the maximum output current that the op amp can supply is 10 mA, what is the voltage on the capacitor following one pulse? Two pulses? Ten pulses?
How many pulses are required to reach 0.5 V? 1.0 V? 2.0 V?
D 17.56 Consider the buffered precision peak rectifier shown in Fig. 17.40 when connected to a triangular input of 1-V peak-to-peak amplitude and 1000-Hz frequency. It uti-lizes an op amp whose bias current (directed into A2) is 10 nA and diodes whose reverse leakage current is 1 nA. What is the smallest capacitor that can be used to guarantee an output ripple less than 1%?
Appendixes on DVD or your convenience, seven additional chapters on important reference topics are included on the in-text DVD. In PDF format, the Appendixes are fully searchable and can be bookmarked. Appendix A: VLSI Fabrication Technology This article is a concise explanation of the technology that goes into fabricating integrated circuits. The different processes used are described and compared, and the characteristics of the resulting devices. Design con-siderations that restrict IC designers are explored. Appendix B: SPICE Device Models and Design Simulation Examples Using PSpice® and Multisim™ This three-part appendix could stand as a book on its own.
Part 1 describes the models SPICE programs use to represent op amps, diodes, MOSFETs, and BJTs in integrated circuits. A thorough understanding of these models is critical for designers trying to extract meaningful information from an analysis. Part 2 describes and discusses all the PSpice® simulations included in the Lab-on-a-Disc, while Part 3 does the same for the Multisim™ simulations. The entire Lab-on-a-Disc is a rich resource to help analyze, experiment with, and design examples that relate to the topics studied in Micro-electronic Circuits. Appendix C: Two-Port Network Parameters Throughout the text, we use different possible ways to characterize linear two-port networks. This appendix summarizes the y, z, h, and g parameters and explains equivalent-circuit representation, a useful tool. Appendix D: Some Useful Network Theorems This article reviews Thévenin’s the-orem, Norton’s theorem, and the source-absorption theorem, all of which are useful in simplifying the analysis of electronic circuits. Appendix E: Single-Time-Constant Circuits STC circuits are composed of, or can be reduced to, one reactive component (inductance or capacitance) and one resistance. This is important to the design and analysis of linear and digital circuits. Analyzing an ampli-fier circuit can usually be reduced to the analysis of one or more STC circuits. F 1397 Appendix F: s-Domain Analysis: Poles, Zeroes, and Bode Plots Most of the work in analyzing the frequency response of an amplifier involves finding the amplifier voltage gain as a function of the complex frequency s. The tools to do this are summa-rized in this appendix.
Appendix G: Bibliography An excellent resource for students beginning research projects, this bibliography outlines key reference works on electronic circuits, circuit and system analysis, devices and IC fabrication, op amps, analog and digital circuits, filters and tuned amplifiers, and SPICE. Appendix H: Standard Resistance Values and Unit Prefixes H-1 Appendix I: Answers to Selected Problems I-1 Appendix A VLSI Fabrication Technology A-1 Appendix B NEW–SPICE appendix B-1 Appendix C Two-Port Network Theorems C-1 Appendix D Some Useful Network Theorems D-1 Appendix E Single-Time-Constant Circuits E-1 Appendix Appendix F Bibliography F-1 Appendix G Standard Resistance Values and Unit Prefixes G-1 Appendix H All NEW from ISM answers H-1 Appendix CD Domain Analysis: Poles, Zeros, and Bode Plots CD-1 A-1 Introduction Since the first edition of this text, we have witnessed a fantastic evolution in VLSI (very-large-scale integrated circuits) technology. In the late 1970s, non-self-aligned metal gate MOSFETs with gate lengths in the order of 10 µm were the norm. Current VLSI fabrication technology is already at the physical scaling limit with gate lengths in the 20-nm regime.
This represents a reduction in device size of almost 1000x, along with an even more impres-sive increase in the number of devices per VLSI chip. Future development in VLSI technol-ogy must rely on new device concepts and new materials, taking quantum effects into account. While this is a very exciting time for researchers to explore new technology, we can also be assured that the “traditional” CMOS and BiCMOS (bipolar CMOS) fabrication technology will continue to be the workhorse of the microelectronic industry for many more years to come.
The purpose of this appendix is to familiarize the reader with VLSI fabrication technol-ogy. Brief explanations of standard VLSI processing steps are given. The variety of devices available in CMOS and BiCMOS fabrication technologies are also presented. In particular, the availability of components in the IC (integrated circuit) environment that are distinct from discrete circuit design will be discussed. In order to enjoy the economics of integrated circuits, designers have to overcome some serious device limitations (such as poor device tolerances) while exploiting device advantages (such as good component matching). An understanding of device characteristics is therefore essential in designing high-performance custom VLSIs. This appendix will consider only silicon-based (Si) technologies. Although other com-pound materials in groups III through V, such as gallium arsenide (GaAs) and aluminum gallium nitride (AlGaN), are also used to implement VLSI chips, silicon is still the most popular material, with excellent cost–performance trade-off. Recent development in SiGe and strained-silicon technologies will further strengthen the position of Si-based fabrication processes in the microelectronic industry for many more years to come. Silicon is an abundant element and occurs naturally in the form of sand. It can be refined using well-established purification and crystal growth techniques. It also exhibits suitable physical properties for fabricating active devices with good electrical characteristics. In addition, silicon can be easily oxidized to form an excellent insulator, SiO2 (glass). This native oxide is useful for constructing capacitors and MOSFETs. It also serves as a diffusion barrier that can mask against unwanted impurities from diffusing into the high-purity silicon material. This masking property allows the electrical properties of the silicon to be altered in predefined areas. Therefore, active and passive elements can be built on the same piece of material (substrate). The components can then be interconnected using metal layers (similar to those used in printed-circuit boards) to form a monolithic IC.
APPENDIX A VLSI FABRICATION TECHNOLOGY A-2 Appendix A VLSI Fabrication Technology A.1 IC Fabrication Steps The basic IC fabrication steps will be described in the following sections. Some of these steps may be carried out many times, in different combinations and/or processing conditions during a complete fabrication run.
A.1.1 Silicon Wafers The starting material for modern integrated circuits is very-high-purity, single-crystal sili-con. The material is initially grown as a single crystal ingot. It takes the shape of a steel-gray solid cylinder 10 cm to 30 cm in diameter and can be one to two meters in length. This crys-tal is then sawed (like a loaf of bread) to produce circular wafers that are 400 µm to 600 µm thick (a micrometer, or micron, µm, is a millionth of a meter). The surface of the wafer is then polished to a mirror finish using chemical and mechanical polishing (CMP) techniques.
Semiconductor manufacturers usually purchase ready-made silicon wafers from a supplier and rarely start their fabrication process in ingot form.
The basic electrical and mechanical properties of the wafer depend on the orientation of the crystalline structure, the impurity concentrations, and the type of impurities present.
These variables are strictly controlled during crystal growth. A specific amount of impuri-ties can be added to the pure silicon in a process known as doping. This allows the alteration of the electrical properties of the silicon, in particular its resistivity. Depending on the types of impurity, either holes (in p-type silicon) or electrons (in n-type silicon) can be responsi-ble for electrical conduction. If a large number of impurity atoms is added, the silicon will be heavily doped (e.g., concentration > ~1018 atoms/cm−3). When designating the relative doping concentrations in semiconductor material, it is common to use the + and − symbols.
A heavily doped (low-resistivity) n-type silicon wafer is referred to as n+ material, while a lightly doped material (e.g., concentration < ~1016 atoms/cm−3) is referred to as n−. Simi-larly, p+ and p− designations refer to the heavily doped and lightly doped p-type regions, respectively. The ability to control the type of impurities and the doping concentration in the silicon permits the formation of diodes, transistors, and resistors in integrated circuits.
A.1.2 Oxidation In oxidation, silicon reacts with oxygen to form silicon dioxide (SiO2). To speed up this chemical reaction, it is necessary to carry out the oxidation at high temperatures (e.g., 1000– 1200°C) and inside ultraclean furnaces. To avoid the introduction of even small quantities of contaminants (which could significantly alter the electrical properties of the silicon), it is necessary to operate in a clean room. Particle filters are used to ensure that the airflow in the processing area is free from dust. All personnel must protect the clean-room environ-ment by wearing special lint-free clothing that covers a person from head to toe.
The oxygen used in the reaction can be introduced either as a high-purity gas (referred to as a “dry oxidation”) or as steam (forming a “wet oxidation”). In general, wet oxidation has a faster growth rate, but dry oxidation gives better electrical characteristics. The ther-mally grown oxide layer has excellent electrical insulation properties. The dielectric strength for SiO2 is approximately 107 V/cm. It has a dielectric constant of about 3.9, and it can be used to form excellent MOS capacitors. Silicon dioxide can also serve as an effective mask against many impurities, allowing the introduction of dopants into the silicon only in regions that are not covered with oxide. Silicon dioxide is a transparent film, and the silicon surface is highly reflective. If white light is shone on an oxidized wafer, constructive and destructive interference will cause A.1 IC Fabrication Steps A-3 certain colors to be reflected. The wavelengths of the reflected light depend on the thickness of the oxide layer. In fact, by categorizing the color of the wafer surface, one can deduce the thickness of the oxide layer. The same principle is used by more sophisticated optical infer-ometers to measure film thickness. On a processed wafer, there will be regions with differ-ent oxide thicknesses. The colors can be quite vivid and are immediately obvious when a finished wafer is viewed with the naked eye.
A.1.3 Photolithography Mass production with economy of scale is the primary reason for the tremendous impact VLSI has had on our society. The surface patterns of the various integrated-circuit compo-nents can be defined repeatedly using photolithography. The sequence of photolithographic steps is as illustrated in Fig. A.1.
The wafer surface is coated with a photosensitive layer called photoresist, using a spin-on technique. After this, a photographic plate with drawn patterns (e.g., a quartz plate with chromium layer for patterning) will be used to selectively expose the photoresist under a deep ultra-violet illumination (UV). The exposed areas will become softened (for positive photoresist). The exposed layer can then be removed using a chemical developer, causing the mask pattern to be duplicated on the wafer. Very fine surface geometries can be repro-duced accurately by this technique. Furthermore, the patterns can be projected directly onto the wafer, or by using a separate photomask produced by a 10x “step and repeat” reduction technique as shown in Fig. A.2. The patterned photoresist layer can be used as an effective masking layer to protect mate-rials below from wet chemical etching or reactive ion etching (RIE). Silicon dioxide, sili-con nitride, polysilicon, and metal layers can be selectively removed using the appropriate etching methods (see next section). After the etching step(s), the photoresist is stripped away, leaving behind a permanent pattern of the photomask on the wafer surface.
To make this process even more challenging, multiple masking layers (which can number more than 20 in advanced VLSI fabrication processes) must be aligned precisely on top of SiO2 layer to be patterned Silicon substrate Silicon substrate Silicon substrate Patterned wafers Photoresist removal Etching (wet or dry) Silicon substrate Silicon substrate Silicon substrate Silicon substrate Silicon substrate Silicon substrate Development Photoresist Photoresist Light Photomask Spin-on photoresist Align and expose Postive photo-resist Negative photo-resist or Figure A.1 Photolithography using positive or negative photoresist.
A-4 Appendix A VLSI Fabrication Technology previous layers. This must be done with even finer precision than the minimum geometry size of the masking patterns. This requirement imposes very critical mechanical and optical constraints on the photolithography equipment.
A.1.4 Etching To permanently imprint the photographic patterns onto the wafer, chemical (wet) etching or RIE dry etching procedures can be used. Chemical etching is usually referred to as wet etching. Different chemical solutions can be used to remove different layers. For example, hydrofluoric (HF) acid can be used to etch SiO2, potassium hydroxide (KOH) for silicon, phosphoric acid for aluminum, and so on. In wet etching, the chemical usually attacks the exposed regions that are not protected by the photoresist layer in all directions (isotropic etching). Depending on the thickness of the layer to be etched, a certain amount of undercut will occur. Therefore, the dimension of the actual pattern will differ slightly from the origi-nal pattern. If exact dimension is critical, RIE dry etching can be used. This method is essentially a directional bombardment of the exposed surface using a corrosive gas (or ions).
The cross section of the etched layer is usually highly directional (anisotropic etching) and has the same dimension as the photoresist pattern. A comparison between isotropic and anisotropic etching is given in Fig. A.3.
A.1.5 Diffusion Diffusion is a process by which atoms move from a high-concentration region to a low-concentration region. This is very much like a drop of ink dispersing through a glass of water except that it occurs much more slowly in solids. In VLSI fabrication, this is a method to introduce impurity atoms (dopants) into silicon to change its resistivity. The rate at which dopants diffuse in silicon is a strong function of temperature. Diffusion of impurities is usu-ally carried out at high temperatures (1000–1200°C) to obtain the desired doping profile.
When the wafer is cooled to room temperature, the impurities are essentially “frozen” in Actual photo-mask Step and repeat camera Mask aligner Patterned wafer x10 Reticle Figure A.2 Conceptual illustration of a step-and-repeat reduction technique to facilitate the mass produc-tion of integrated circuits.
A.1 IC Fabrication Steps A-5 position. The diffusion process is performed in furnaces similar to those used for oxidation.
The depth to which the impurities diffuse depends on both the temperature and the process-ing time.
The most common impurities used as dopants are boron, phosphorus, and arsenic. Boron is a p-type dopant, while phosphorus and arsenic are n-type dopants. These dopants can be effectively masked by thin silicon dioxide layers. By diffusing boron into an n-type sub-strate, a pn junction is formed (diode). If the doping concentration is heavy, the diffused layer can also be used as a conducting layer with very low resistivity.
A.1.6 Ion Implantation Ion implantation is another method used to introduce impurities into the semiconductor crystal. An ion implanter produces ions of the desired dopant, accelerates them by an elec-tric field, and allows them to strike the semiconductor surface. The ions become embedded in the crystal lattice. The depth of penetration is related to the energy of the ion beam, which can be controlled by the accelerating-field voltage. The quantity of ions implanted can be controlled by varying the beam current (flow of ions). Since both voltage and current can be accurately measured and controlled, ion implantation results in impurity profiles that are much more accurate and reproducible than can be obtained by diffusion. In addition, ion implantation can be performed at room temperature. Ion implantation normally is used when accurate control of the doping profile is essential for device operation.
A.1.7 Chemical Vapor Deposition Chemical vapor deposition (CVD) is a process by which gases or vapors are chemically reacted, leading to the formation of solids on a substrate. CVD can be used to deposit vari-ous materials on a silicon substrate including SiO2, Si3N4, polysilicon, and so on. For instance, if silane gas and oxygen are allowed to react above a silicon substrate, the end product, silicon dioxide, will be deposited as a solid film on the silicon wafer surface. The properties of the CVD oxide layer are not as good as those of a thermally grown oxide, but they are sufficient to allow the layer to act as an electrical insulator. The advantage of a CVD layer is that the oxide deposits at a faster rate and a lower temperature (below 500°C).
If silane gas alone is used, then a silicon layer will be deposited on the wafer. If the reac-tion temperature is high enough (above 1000°C), the layer deposited will be a crystalline layer (assuming that there is an exposed crystalline silicon substrate). Such a layer is called an epitaxial layer, and the deposition process is referred to as epitaxy instead of CVD. At lower temperatures, or if the substrate surface is not single-crystal silicon, the atoms will not be able to aligned along the same crystalline direction. Such a layer is called polycrystalline Photoresist Photoresist Silicon substrate (a) SiO2 SiO2 Undercut Photoresist Photoresist Silicon substrate (b) SiO2 SiO2 Figure A.3 (a) Cross-sectional view of an isotropic oxide etch with severe undercut beneath the photoresist layer. (b) Anisotropic etching, which usually produces a cross section with no undercut.
A-6 Appendix A VLSI Fabrication Technology silicon (poly Si), since it consists of many small crystals of silicon aligned in random fash-ion. Polysilicon layers are normally doped very heavily to form highly conductive regions that can be used for electrical interconnections.
A.1.8 Metallization The purpose of metallization is to interconnect the various components (transistors, capaci-tors, etc.) to form the desired integrated circuit. Metallization involves the deposition of a metal over the entire surface of the silicon. The required interconnection pattern is then selectively etched. The metal layer is normally deposited via a sputtering process. A pure metal disk (e.g., 99.99% aluminum target) is placed under an Ar (argon) ion gun inside a vacuum chamber. The wafers are also mounted inside the chamber above the target. The Ar ions will not react with the metal, since argon is a noble gas. However, the ions are made to physically bombard the target and literally knock metal atoms out of the target. These metal atoms will then coat all the surface inside the chamber, including the wafers. The thickness of the metal film can be controlled by the length of the sputtering time, which is normally in the range of 1 to 2 minutes. The metal interconnects can then be defined using photolithog-raphy and etching steps.
A.1.9 Packaging A finished silicon wafer may contain several hundreds of finished circuits or chips. A chip may contain from 10 to more than 108 transistors; each chip is rectangular and can be up to tens of millimeters on a side. The circuits are first tested electrically (while still in wafer form) using an automatic probing station. Bad circuits are marked for later identification.
The circuits are then separated from each other (by dicing), and the good circuits (dies) are mounted in packages (headers). Examples of such IC packages are given in Fig. A.4. Fine gold wires are normally used to interconnect the pins of the package to the metallization pat-tern on the die. Finally, the package is sealed using plastic or epoxy under vacuum or in an inert atmosphere.
A.2 VLSI Processes Integrated-circuit fabrication technology was originally dominated by bipolar technology.
By the late 1970s, metal oxide semiconductor (MOS) technology became more promising for VLSI implementation with higher packing density and lower power consumption. Since the early 1980s, complementary MOS (CMOS) technology has almost completely dominated the VLSI scene, leaving bipolar technology to fill specialized functions such as Figure A.4 Examples of an 8-pin plastic dual-in-line IC package and a 16-pin surface-mount package.
8 1 1 16 A.2 VLSI Processes A-7 high-speed analog and RF circuits. CMOS technologies continue to evolve, and in the late 1980s, the incorporation of bipolar devices led to the emergence of high-performance bipolar-CMOS (BiCMOS) fabrication processes that provided the best of both technologies.
However, BiCMOS processes are often very complicated and costly, since they require upwards of 15 to 20 masking levels per implementation—standard CMOS processes by comparison require only 10 to 12 masking levels. The performance of CMOS and BiCMOS processes continues to improve with finer lithography resolution. However, fundamental limitations on processing techniques and semiconductor properties have prompted the need to explore alternate materials. Newly emerged SiGe and strained-Si technologies are good compromises to improve performance while maintaining manufacturing compatibility (hence low cost) with existing silicon-based CMOS fabrication equipment.
In the subsection that follows, we will examine a typical CMOS process flow, the perfor-mance of the available components, and the inclusion of bipolar devices to form a BiCMOS process.
A.2.1 Twin-Well CMOS Process Depending on the choice of starting material (substrate), CMOS processes can be identified as n-well, p-well, or twin-well processes. The latter is the most complicated but most flexi-ble in the optimization of both the n and p-channel MOSFETs. In addition, many advanced CMOS processes may make use of trench isolation and silicon-on-insulator (SOI) technol-ogy to reduce parasitic capacitance (hence higher speed) and to improve packing density.
A modern twin-well CMOS process flow is shown in Fig. A.5. A minimum of 10 mask-ing layers is required. In practice, most CMOS processes will also require additional layers such as n- and p-guards for better latchup immunity, a second polysilicon layer for capaci-tors, and multilayer metals for high-density interconnections. The inclusion of these layers would increase the total number of 15 to 20 masking layers.
The starting material for the twin-well CMOS is a p-type substrate. The process begins with the formation of the p-well and the n-well (Fig. A.5a). The n-well is required wherever p-channel MOSFETs are to be placed, while the p-well is used to house the n-channel MOS-FETs. The well-formation procedures are similar. A thick photoresist layer is etched to expose the regions for n-well diffusion. The unexposed regions will be protected from the n-type phosphorus impurity. Phosphorus implantation is usually used for deep diffusions, since it has a large diffusion coefficient and can diffuse faster than arsenic into the substrate.
The second step is to define the active regions (region where transistors are to be placed) using a technique called shallow trench isolation (STI). To reduce the chance of unwanted latchup (a serious issue in CMOS technology), dry etching is used to produce trenches approximately 0.3 µm deep on the silicon surface. These trenches are then refilled using CVD oxide, followed by a planarization procedure. This results in a cross section with flat surface topology (Fig. A.5b). An alternate isolation technique is called local oxidation of silicon (LOCOS). This older technology uses silicon nitride (Si3N4) patterns to protect the penetration of oxygen during oxidation. This allows selective regions of the wafer surface to be oxidized. After a long wet-oxidation step, thick field oxide will appear in regions between transistors. This effectively produces an effect similar to that obtained in the STI process, but at the expense of large area overhead.
The next step is the formation of the polysilicon gate (Fig. A.5c). This is one of the most criti-cal steps in the CMOS process. The thin oxide layer in the active region is first removed using wet etching followed by the growth of a high-quality thin gate oxide. Current deep-submicron CMOS processes routinely make used of oxide thicknesses as thin as 20 Å to 50 Å (1 angstrom = A-8 Appendix A VLSI Fabrication Technology 10−8 cm). A polysilicon layer, usually arsenic doped (n-type), is then deposited and patterned.
The photolithography is most demanding in this step since the finest resolution is required to pro-duce the shortest possible MOS channel length.
The polysilicon gate is a self-aligned structure and is preferred over the older type of metal gate structure. This is normally accompanied by the formation of lightly doped drain (LDD) regions for MOSFETs of both types to suppress the generation of hot electrons that Photoresist (mask #2) p-well n-well p-substrate p-well n-well p-substrate p-well n-well p-substrate p-well n-well p-substrate p-well n-well p-substrate p-well n-well p-substrate p-well n-well p-substrate p-well n+ n+ n+ n+ p+ p+ n-well p-substrate (a) p-well and n-well formation (masks # 1 and #2) Phosphorus implant (b) Trench etch and STI refill (mask #3) STI STI (c) Gate oxidation and polysilicon patterning (mask #4) Arsenic implant Photoresist (mask #6) Polysilicon gate (d) n- and p-LDD (lightly doped drain) (mask #5 and 6) (h) Metallization (mask #10) n-MOSFET p-MOSFET (g) Contact holes (mask #9) CVD oxide Silicon nitride sidewall spacers (e) n+ diffusion (mask #7) Arsenic implant Photoresist STI STI STI SiO2 SiO2 (f) p+ diffusion (mask #8) Boron implant Photoresist p+ p+ n+ n+ STI STI p+ p+ n+ n+ Figure A.5 A modern twin-well CMOS process flow with shallow trench isolation (STI).
A.2 VLSI Processes A-9 might affect the reliability of the transistors. A noncritical mask, together with the polysili-con gates, is used to form the self-aligned LDD regions (Fig. A.5d). Prior to the n+ and p+ drain region implant, a sidewall spacer step is performed. A thick layer of silicon nitride is deposited uniformly on the wafer. Due to the conformal nature of the deposition, the thickness of the silicon nitride layer at all layer edges (i.e., at both ends of the polysilicon gate electrode) will be thicker than those deposited over a flat surface. After a timed RIE dry etch to remove all the silicon nitride layer, pockets of silicon nitride will remain at the edge of the polysilicon gate electrode (Fig. A.5e). Such pockets of silicon nitride are called sidewall spacers. They are used to block subsequent n+ or p+ source/drain implants, protecting the LDD regions.
A heavy arsenic implant can be used to form the n+ source and drain regions of the n-MOSFETs. The polysilicon gate also acts as a barrier for this implant to protect the chan-nel region. A layer of photoresist can be used to block the regions where p-MOSFETs are to be formed (Fig. A.5e). The thick field oxide stops the implant and prevents n+ regions from forming outside the active regions. A reversed photolithography step can be used to protect the n-MOSFETs during the p+ boron source and drain implant for the p-MOS-FETs (Fig. A.5f). Note that in both cases the separation between the source and drain diffusions—channel length—is defined by the polysilicon gate mask alone, hence the self-aligned property.
Before contact holes are opened, a thick layer of CVD oxide is deposited over the entire wafer. A photomask is used to define the contact window opening (Fig. A.5g), followed by a wet or dry oxide etch. A thin aluminum layer is then evaporated or sputtered onto the wafer. A final masking and etching step is used to pattern the interconnection (Fig. A.5h).
Not shown in the process flow is the final passivation step prior to packaging and wire bonding. A thick CVD oxide or pyrox glass is usually deposited on the wafer to serve as a protective layer.
A.2.2 Integrated Devices Besides the obvious n and p-channel MOSFETs, other devices can be obtained by appropri-ate masking patterns. These include pn junction diodes, MOS capacitors, and resistors.
A.2.3 MOSFETs The n-channel MOSFET is the preferred device in comparison to the p-MOSFET (Fig. A.6).
The electron surface mobility is two to three times higher than that for holes. Therefore, with the same device size (W and L), the n-MOSFET offers higher current drive (or lower on-resistance) and higher transconductance.
p-well n-well p-substrate n-MOSFET n+ n+ p+ p+ p-MOSFET W SiO2 STI L Figure A.6 Cross-sectional diagram of n- and p-MOSFETs.
A-10 Appendix A VLSI Fabrication Technology In an integrated-circuit design environment, MOSFETs are characterized by their thresh-old voltage and by their device sizes. Usually the n- and p-channel MOSFETs are designed to have threshold voltages of similar magnitude for a particular process. The transconduc-tance can be adjusted by changing the device surface dimensions (W and L). This feature is not available for bipolar transistor, making the design of integrated MOSFET circuits much more flexible.
A.2.4 Resistors Resistors in integrated form are not very precise. They can be made from various diffusion regions as shown in Fig. A.7. Different diffusion regions have different resistivity. The n well is usually used for medium-value resistors, while the n+ and p+ diffusions are useful for low-value resistors. The actual resistance value can be defined by changing the length and width of diffused regions. The tolerance of the resistor value is very poor (20–50%), but the matching of two similar resistor values is quite good (5%). Thus circuit designers should design circuits that exploit resistor matching and should avoid designs that require a specific resistor value.
All diffused resistors are self-isolated by the reverse-biased pn junctions. A serious draw-back for these resistors is the fact that they are accompanied by a substantial parasitic junction capacitance, making them not very useful for high-frequency applications. The reverse-biased pn junctions also exhibit a JFET effect, leading to a variation in the resistance value as the supply voltage is changed (a large voltage coefficient is undesirable). Since the mobilities of carriers vary with temperature, diffused resistors also exhibit a significant tem-perature coefficient.
A more useful resistor can be fabricated using the polysilicon layer that is placed on top of the thick field oxide. The thin polysilicon layer provides better surface area matching and hence more accurate resistor ratios. Furthermore, the polyresistor is physically separated from the substrate, resulting in a much lower parasitic capacitance and voltage coefficient.
A.2.5 Capacitors Two types of capacitor structure are available in CMOS processes: MOS and interpoly capacitors. The latter are also similar to metal–insulator–metal (MIM) capacitors. The cross sections of these structures are as shown in Fig. A.8. The MOS gate capacitance, depicted by the center structure, is basically the gate-to-source capacitance of a MOSFET. The capaci-tance value is dependent on the gate area. The oxide thickness is the same as the gate oxide Polyresistor SiO2 SiO2 SiO2 n+ diffusion resistor n+ n+ n+ polysilicon p-substrate n+ well Parasitic capacitance n+ p+ n+ well resistor p+ diffusion resistor Figure A.7 Cross sections of various resistor types available from a typical n-well CMOS process.
A.2 VLSI Processes A-11 thickness in the MOSFETs. This capacitor exhibits a large voltage dependence. To eliminate this problem, an addition n+ implant is required to form the bottom plate of the capacitors, as shown in the structure on the right. Both these MOS capacitors are physically in contact with the substrate, resulting in a large parasitic pn junction capacitance at the bottom plate.
The interpoly capacitor exhibits near-ideal characteristics but at the expense of the inclu-sion of a second polysilicon layer to the CMOS process. Since this capacitor is placed on top of the thick field oxide, parasitic effects are kept to a minimum.
A third and less often used capacitor is the junction capacitor. Any pn junction under reversed bias produces a depletion region that acts as a dielectric between the p and the n regions. The capacitance is determined by geometry and doping levels and has a large voltage coefficient. This type of capacitor is often used as a variactor (variable capacitor) for tuning circuits. However, this capacitor works only with reverse-bias voltages. For the interpoly and MOS capacitors, the capacitance values can be controlled to within 1%. Practical capacitance values range from 0.5 pF to a few tens of picofarads. The match-ing between capacitors of similar size can be within 0.1%. This property is extremely useful for designing precision analog CMOS circuits.
A.2.6 pn Junction Diodes Whenever n-type and p-type diffusion regions are placed next to each other, a pn junction diode results. A useful structure is the n-well diode shown in Fig. A.9. The diode fabricated in an n well can provide a high breakdown voltage. This diode is essential for the input clamping circuits for protection against electrostatic discharge. The diode is also very useful as an on-chip temperature sensor by monitoring the variation of its forward voltage drop.
Interpoly capacitor Poly 2 p-substrate Parasitic capacitance SiO2 SiO2 SiO2 n-well n+ n+ n+implant Poly 1 MOS capacitor MOS capacitor with implant Figure A.8 Interpoly and MOS capacitors in an n-well CMOS process.
p-substrate SiO2 pn junction diode n-well n+ p+ Figure A.9 A pn junction diode in an n-well CMOS process.
A-12 Appendix A VLSI Fabrication Technology A.2.7 BiCMOS Process An npn vertical bipolar transistor can be integrated into the n-well CMOS process with the addition of a p-base diffusion region (Fig. A.10). The characteristics of this device depend on the base width and the emitter area. The base width is determined by the difference in junction depth between the n+ and the p-base diffusions. The emitter area is determined by the junction area of the n+ diffusion at the emitter. The n-well serves as the collector for the npn transistor. Typically, the npn transistor has a β in the range of 50 to 100 and a cutoff fre-quency of greater than tens of gigahertz.
Normally, an n+ buried layer is used to reduce the series resistance of the collector, since the n well has a very high resistivity. However, this would further complicate the process by introducing p-type epitaxy and one more masking step. Other variations on the bipolar tran-sistor includes poly-emitter and self-aligned base contact to minimize parasitic effects.
A.2.8 Lateral pnp Transistor The fact that most BiCMOS processes do not have optimized pnp transistors makes circuit design somewhat difficult. However, in noncritical situations, a parasitic lateral pnp transis-tor can be used (Fig. A.11). In this case, the n well serves as the n-base region, with the p+ diffusions as the emitter and the collector. The base width is determined by the separation between the two p+ diffu-sions. Since the doping profile is not optimized for the base–collector junctions and because the base width is limited by the minimum photolithographic resolution, the performance of this device is not very good: typically, β of around 10, and the cutoff frequency is low.
A.2.9 p-Base and Pinched-Base Resistors With the additional p-base diffusion in the BiCMOS process, two additional resistor struc-tures are available. The p-base diffusion can be used to form a straightforward p-base Figure A.10 Cross-sectional diagram of a BiCMOS process.
n-MOSFET p-epitaxial layer n-well p-substrate n+ buried layer p-base n-well SiO2 SiO2 p-MOSFET p+ p+ p+ n+ n+ n+ n+ npn-bipolar transistor E B C Figure A.11 Lateral pnp transistor.
n-well p-substrate E B Lateral pnp transistor C p+ p+ n+ A.2 VLSI Processes A-13 resistor as shown in Fig. A.12. Since the base region is usually of a relatively low doping level and has a moderate junction depth, it is suitable for medium-value resistors (a few kilohms). If a large resistor value is required, the pinched-base resistor can be used. In this structure, the p-base region is encroached by the n+ diffusion, restricting the conduction path. Resistor values in the range of 10 kΩ to 100 kΩ can be obtained. As with the diffusion resistors discussed earlier, these resistors exhibit poor tolerance and temperature coefficients but relatively good matching.
A.2.10 SiGe BiCMOS Process With the burgeoning of wireless applications, the demand for high-performance, high-frequency RF integrated circuits is tremendous. Owing to the fundamental limitations of physical material properties, silicon-based technology was not able to compete with more expensive technologies relying on compounds from groups III through IV, such as GaAs.
By incorporating a controlled amount (typically no more than 15–20% mole fraction) of ger-manium (Ge) into crystal silicon (Si) in the BJT’s base region, the energy bandgap can be altered. The specific concentration profile of the Ge can be engineered in such a way that the energy bandgap can be gradually reduced from the pure Si region to a lower value in the SiGe region. This energy bandgap reduction produces a built-in electric field that can assist the movement of carriers, hence resulting in faster operating speed. Therefore, SiGe bipolar transistors can achieve significant higher cutoff frequency (e.g., in the 100–200 GHz range).
Another benefit is that the SiGe process is compatible with existing Si-based fabrication technology, ensuring a very favorable cost/performance ratio.
To take advantage of the SiGe material characteristics, the basic bipolar transistor struc-ture must also be modified to further reduce parasitic capacitance (for higher speed) and to improve the injection efficiency (for higher gain). A symmetric bipolar device structure is shown in Fig. A.13. The device made use of trench isolation to reduce the collector sidewall capacitance between the n-well/n+ buried layer and the p substrate. The emitter size and the p+ base contact size are defined by a self-aligned process to minimize the base–collector junction (Miller) capacitance. This type of device is called a heterojunction bipolar transis-tor (HBT) since the emitter–base junction is formed from two different types of material, polysilicon emitter and SiGe base. The injection efficiency is significantly better than a homojunction device (as in a conventional BJT). This advantage, coupled with the fact that base width is typically only around 50 nm, makes it easy to achieve current gain of more than 100. In addition, not shown in Fig. A.13, is the possible use of multiple layers of metal-lization to further reduce the device size and interconnect resistance. All these device features are necessary to complement the high-speed performance of SiGe material.
p-base resistor p-base n+buried layer p+ p+ p+ p+ n+ p-base n-well Pinched-base resistor SiO2 SiO2 SiO2 Figure A.12 p-base and pinched p-base resistors.
A-14 Appendix A VLSI Fabrication Technology A.3 VLSI Layout The designed circuit schematic must be transformed into a layout that consists of the geo-metric representation of the circuit components and interconnections. Today, computer-aided design tools allow many of the conversion steps, from schematic to layout, to be car-ried out semi- or fully automatically. However, any good mixed-signal IC designer must have practiced full custom layout at one point or another. An example of a CMOS inverter can be used to illustrate this procedure (Fig. A.14).
The circuit must first be “flattened” and redrawn to eliminate any interconnection cross-overs, similar to the requirement of a printed-circuit-board layout. Each process is made up of a specific set of masking layers. In this case, seven layers are used. Each layer is usually assigned a unique color and fill pattern for ease of identification on a computer screen or on a printed color plot. The layout begins with the placement of the transistors. For illustration purposes, the p and n MOSFETs are placed in an arrangement similar to that shown in the schematic. In practice, the designer is free to choose the most area-efficient layout. The MOSFETs are defined by the active areas overlapped by the “poly 1” layer. The MOS chan-nel length and width are defined by the width of the “poly 1” strip and that of the active region, respectively. The p-MOSFET is enclosed in an n well. For more complex circuits, multiple n wells can be used for different groups of p-MOSFETs. The n-MOSFET is enclosed by the n+ diffusion mask to form the source and drain, while the p-MOSFET is enclosed by the p+ diffusion mask. Contact holes are placed in regions where connection to the metal layer is required. Finally, the “metal 1” layer completes the interconnections.
The corresponding cross-sectional diagram of the CMOS inverter along the AA' plane is as shown in Fig. A.15. The poly-Si gates for both transistors are connected to form the input terminal, X. The drains of both transistors are tied together via “metal 1” to form the output terminal, Y. The sources of the n- and p-MOSFETs are connected to GND and VDD, respec-tively. Note that butting contacts consist of side-by-side n+/p+ diffusions that are used to tie the body potential of the n- and p-MOSFETs to the appropriate voltage levels.
When the layout is completed, the circuit must be verified using CAD tools such as the circuit extractor, the design rule checker (DRC), and the circuit simulator. Once these npn SiGe heterojunction bipolar transistor SiGe p-base C B E B C SiO2 SiO2 n+ polysilicon emitter n+ well p+ n+ n+ n+ buried layer RC1 RC3 RC2 p+ polysilicon p+ substrate Polysilicon refill Polysilicon Trench isolation Polysilicon Figure A.13 Cross-sectional diagram of a symmetric self-aligned SiGe heterojunction bipolar transistor, or HBT.
A.3 VLSI Layout A-15 verifications have been satisfied, the design can be “taped out” to a mask-making facility. A pattern generator (PG) machine can then draw the geometries on a glass or quartz photoplate using electronically driven shutters. Layers are drawn one by one onto different photoplates.
After these plates have been developed, clear and dark patterns resembling the geometries on the layout will result. A set of the photoplates for the CMOS inverter example is shown in Fig. A.16. Depending on whether the drawn geometries are meant to be opened as win-dows or kept as patterns, the plates can be clear or dark field. Note that each of these layers must be processed in sequence. The layers must be aligned within very fine tolerance to form the transistors and interconnections. Naturally, the greater the number of layers, the more difficult it is to maintain the alignment. This also requires better photolithography Figure A.14 A CMOS inverter schematic and its layout.
VDD VDD A Q2 Q2 GND A Q1 L2 L1 Q2 X n-well Active region (LOCOS) Poly 1 (Poly-Si gate) n+ diffusion p+ diffusion Contact hole Metal 1 X Y Y W1 Gate 1 W2 Gate 2 X p+ p+ p+ n+ n+ n-well p-substrate n+ Y Q1 Q2 SiO2 VDD Figure A.15 Cross section along the plane AA' of a CMOS inverter. Note that this particular layout is good for illustration purposes, but is not necessarily appropriate for latchup prevention.
A-16 Appendix A VLSI Fabrication Technology equipment and may result in lower yield. Hence, each additional mask will be reflected in an increase in the final cost of the IC chip.
Summary This appendix presents an overview of the various aspects of VLSI fabrication procedures.
This includes component characteristics, process flows, and layouts. This is by no means a (a) n-well (d) n+ diffusion (e) p+ diffusion (f) Contact hole Photographic plate (g) Metal 1 (b) Active region (c) Poly 1 Figure A.16 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate. Photo-plates (a), (d), (e), and (f) are dark-field masks, while (b), (c), and (g) are clear-field masks.
Bibliography A-17 complete account of state-of-the-art VLSI technologies. Interested readers should consult other references on this subject for more detailed descriptions.
Bibliography J. D. Plummer, M.D. Deal, and P.B. Griffin, Silicon VLSI Technology, Upper Saddle River, NJ, Prentice Hall, 2000.
R. S. Muller, T.I. Kamins, and M. Chan, Device Electronics for Integrated Circuits, 3rd ed., Hoboken, NJ, John Wiley & Sons, 2003.
S. Wolf, Microchip Manufacturing, Lattice Press (www.latticepress.com), 2004. B-1 Introduction This appendix is concerned with the very important topic of using PSpice and Multisim to simulate the operation of electronic circuits. The need for and the role of computer simula-tion in circuit design was described in the preface. The appendix has three sections: Section B.1 presents a brief description of the models that SPICE uses to describe the operation of op amps, diodes, MOSFETs, and BJTs. Section B.2 presents design and simulation examples using PSpice. Finally, design and simulation examples utilizing Multisim are presented in Section B.3. Besides the descriptions presented in this appendix, the reader will find the complete sim-ulation files for each example on the CD accompanying the book.
B.1 SPICE Device Models To the designer, the value of simulation results is a direct function of the quality of the mod-els used for the devices. The more faithfully the model represents the various characteristics of the device, the more accurately the simulation results will describe the operation of an actual fabricated circuit. In other words, to see the effect on circuit performance of various imperfections in device operation, these imperfections must be included in the device model used by the circuit simulator.
B.1.1 The Op-Amp Model In simulating circuits that use one or more op amps, it is useful to utilize a macromodel to represent each op amp. A macromodel is based on the observed terminal characteristics of the op amp rather than on the modeling of every transistor in the op-amp internal circuit.
Macromodels can be developed from data-sheet specifications without knowledge of the details of the internal circuitry of the op amp.
Linear Macromodel The schematic capture of a linear macromodel for an internally compensated op amp with finite gain and bandwidth is shown in Fig. B.1. In this equivalent-circuit model, the gain constant A0d of the voltage-controlled voltage source Ed corresponds APPENDIX B SPICE DEVICE MODELS AND DESIGN SIMULATION EXAMPLES USING PSPICE AND MULTISIM B-2 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim to the differential gain of the op amps at dc. Resistor Rb and capacitor Cb form a single-time-constant (STC) filter with a corner frequency (B.1) The low-pass response of this filter is used to model the frequency response of the internally compensated op amp. The values of Rb and Cb used in the macromodel are chosen such that fb corresponds to the 3-dB frequency of the op amp being modeled. This is done by arbitrarily selecting a value for either Rb or Cb (the selected value does not need to be a practical one) and then using Eq. (B.1) to compute the other value. In Fig. B.1, the voltage-controlled volt-age source Eb with a gain constant of unity is used as a buffer to isolate the low-pass filter from any load at the op-amp output. Thus any op-amp loading will not affect the frequency response of the filter and hence that of the op amp.
The linear macromodel in Fig. B.1 can be further expanded to account for other op-amp nonidealities. For example, the equivalent-circuit model in Fig. B.2 can be used to model an internally compensated op amp while accounting for the following op-amp nonidealities: Figure B.1 A linear macromodel used to model the finite gain and bandwidth of an internally compensated op amp.
Figure B.2 A comprehensive linear macromodel of an internally compensated op amp.
fb 1 2πRbCb -------------------= {Cb} {Rb} 2 1 1 1 Gain {A0d} Ed b d 0 0 2 2 b 3 3 Gain 1 Eb 0 0 {IB1} {IB2} {VOS} {2Ricm} {2Ricm} 1 1 0 2 2 {Rid} Ecm1 Ed Ecm2 {Cb} {Rb} 2 b 1 Gain {A0cm2} Gain {A0cm2} 0 0 0 0 2 1 Gain {A0d} {Ro} 0 b 3 3 Gain 1 0 Eb B.1 SPICE Device Models B-3 1. Input Offset Voltage (VOS). The dc voltage source VOS models the op-amp input off-set voltage.
2. Input Bias Current (IB) and Input Offset Current (IOS). The dc current sources IB1 and IB2 model the input bias current at each input terminal of the op amp, with where IB and IOS are, respectively, the input bias current and the input offset current specified by the op-amp manufacturer.
3. Common-Mode Input Resistance (Ricm). If the two input terminals of an op amp are tied together and the input resistance (to ground) is measured, the result is the common-mode input resistance Ricm. In the macromodel of Fig. B.2, we have split Ricm into two equal parts (2Ricm), each connected between one of the input terminals and ground.
4. Differential-Input Resistance (Rid). The resistance seen between the two input termi-nals of an op amp is the differential input resistance Rid.
5. Differential Gain at DC (A0d) and Common-Mode Rejection Ratio (CMRR). The output voltage of an op amp at dc can be expressed as (B.2) where A0d and A0cm are, respectively, the differential and common-mode gains of the op amp at dc. For an op amp with a finite CMRR, (B.3) where CMRR is expressed in V/V (not in dB). In the macromodel of Fig. B.2, the volt-age-controlled voltage sources Ecm1 and Ecm2 with gain constants of account for the finite CMRR while source Ed models A0d.
6. Unity-Gain Frequency ( ft). From Eq. (2.46), the 3-dB frequency fb and the unity-gain frequency (or gain-bandwidth product) f t of an internally compensated op amp with an STC frequency response are related by (B.4) As in Fig. B.1, the finite op-amp bandwidth is accounted for in the macromodel of Fig. B.2 by setting the corner frequency of the filter formed by resistor Rb and capac-itor Cb (Eq. B.1) to equal the 3-dB frequency of the op amp, fb.
7. Ouput Resistance (Ro). The resistance seen at the output terminal of an op amp is the output resistanceRo.
The linear macromodels in Figs. B.1 and B.2 assume that the op-amp circuit is operating in its linear range and do not account for its nonideal performance when large signals are present at the output. Therefore, nonlinear effects, such as output saturation and slew rate, are not modeled.
Nonlinear Macromodel The linear macromodel in Fig. B.2 can be expanded to account for the op-amp nonlinear performance. For example, the finite output voltage swing of the op amp can be modeled by placing limits on the output voltage of the voltage-controlled voltage IB1 IB IOS 2 -------and IB2 IB IOS 2 -------– = + = V3 = A0d V2 V1 – ( ) A0cm 2 ---------- V1 V2 + ( ) + A0cm A0d CMRR ⁄ = A0cm 2 ⁄ f b f t A0d -------= B-4 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim source Eb. In PSpice, this can be done using the ETABLE component in the analog-behavioral-modeling (ABM) library and setting the output voltage limits in the lookup table of this component. Further details on how to build nonlinear macromodels for the op amp can be found in the references on SPICE simulation. In general, robust macromodels that account for the nonlinear effects in an IC are provided by the op-amp manufacturers. Most simulators include such macromodels for some of the popular off-the-shelf ICs in their libraries. For example, PSpice and Multisim include models for the μA741, the LF411, and the LM324 op amps.
B.1.2 The Diode Model The large-signal SPICE model for the diode is shown in Fig. B.3. The static behavior is modeled by the exponential i−v relationship. Here, for generality, a constant n is included in the exponential. It is known as the emission cofficient, and its value ranges from 1 to 2. In our study of the diode in Chapter 3, we assumed n = 1. The dynamic behavior is represented by the nonlinear capacitor CD, which is the sum of the diffusion capacitance Cd and the junc-tion capacitance Cj. The series resistance RS represents the total resistance of the p and n regions on both sides of the junction. The value of this parasitic resistance is ideally zero, but it is typically in the range of a few ohms for small-signal diodes. For small-signal analy-sis, SPICE uses the diode incremental resistance rd and the incremental values of Cd and Cj. Table B.1 provides a partial listing of the diode-model parameters used by SPICE, all of which should be familiar to the reader. But having a good device model solves only half of the modeling problem; the other half is to determine appropriate values for the model parame-ters. This is by no means an easy task. The values of the model parameters are determined using a combination of characterization of the device-fabrication process and specific mea-surements performed on the actual manufactured devices. Semiconductor manufacturers expend enormous effort and money to extract the values of the model parameters for their devices. For discrete diodes, the values of the SPICE model parameters can be determined from the diode data sheets, supplemented if needed by key measurements. Circuit simulators (such as PSpice) include in their libraries the model parameters of some of the popular off-the-shelf components. For instance, in Example PS4.1, we will use the commercially available D1N418 pn-junction diode whose SPICE model parameters are available in PSpice. Figure B.3 The SPICE diode model.
CD iD vD RS iD IS evDnVT 1 CD Cd Cj IS evDnVT VT Cj0 1 m vD V0 T B.1 SPICE Device Models B-5 B.1.3 The Zener Diode Model The diode model in Fig. B.3 does not adequately describe the operation of the diode in the breakdown region. Hence, it does not provide a satisfactory model for zener diodes. How-ever, the equivalent-circuit model shown in Fig B.4 can be used to simulate a zener diode in SPICE. Here, diode D1 is an ideal diode that can be approximated in SPICE by using a very small value for n (say n = 0.01). Diode D2 is a regular diode that models the forward-bias region of the zener (for most applications, the parameters of D2 are of little consequence). B.1.4 MOSFET Models To simulate the operation of a MOSFET circuit, a simulator requires a mathematical model to represent the characteristics of the MOSFET. The model we derived in Chapter 5 to repre-sent the MOSFET is a simplified or first-order model. This model, called the square-law model because of the quadratic i–v relationship in saturation, works well for transistors with relatively long channels. However, for devices with short channels, especially deep-submicron transistors, many physical effects that we neglected come into play, with the result that the derived first-order model no longer accurately represents the actual operation of the MOSFET (see Section 14.5).
The simple square-law model is useful for understanding the basic operation of the MOSFET as a circuit element and is indeed used to obtain approximate pencil-and-paper circuit designs. However, more elaborate models, which account for short-channel effects, are required to be able to predict the performance of integrated circuits with a certain degree of precision prior to fabrication. Such models have indeed been developed and continue to Table B.1 Parameters of the SPICE Diode Model (Partial Listing) SPICE Parameter Book Symbol Description Units IS IS Saturation current A N n Emission coefficient RS RS Ohmic resistance Ω VJ V0 Built-in potential V CJ0 Cj0 Zero-bias depletion (junction) capacitance F M m Grading coefficient TT τT Transit time s BV VZK Breakdown voltage V IBV IZK Reverse current at VZK A D2 D1 rz VZ0 Figure B.4 Equivalent-circuit model used to simulate the zener diode in SPICE. Diode D1 is ideal and can be approxi-mated in SPICE by using a very small value for n (say n = 0.01).
B-6 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim be refined to more accurately represent the higher-order effects in short-channel transistors through a mix of physical relationships and empirical data. Examples include the Berkeley short-channel IGFET model (BSIM) and the EKV model, popular in Europe. Currently, semi-conductor manufacturers rely on such sophisticated models to accurately represent the fabri-cation process. These manufacturers select a MOSFET model and then extract the values for the corresponding model parameters using both their knowledge of the details of the fabri-cation process and extensive measurements on a variety of fabricated MOSFETs. A great deal of effort is expended on extracting the model parameter values. Such effort pays off in fabricated circuits exhibiting performance very close to that predicted by simulation, thus reducing the need for costly redesign.
Although it is beyond the scope of this book to delve into the subject of MOSFET model-ing and short-channel effects, it is important that the reader be aware of the limitations of the square-law model and of the availability of more accurate but, unfortunately, more complex MOSFET models. In fact, the power of computer simulation is more apparent when one has to use these complex device models in the analysis and design of integrated circuits.
SPICE-based simulators, like PSpice and Multisim, provide the user with a choice of MOSFET models. The corresponding SPICE model parameters (whose values are provided by the semiconductor manufacturer) include a parameter called LEVEL, which selects the MOSFET model to be used by the simulator. Although the value of this parameter is not always indicative of the accuracy, nor of the complexity of the corresponding MOSFET model, LEVEL = 1 corresponds to the simplest first-order model (called the Shichman-Hodges model), which is based on the square-law MOSFET equations presented in Chapter 5. For simplicity, we will use this model to illustrate the description of the MOS-FET model parameters in SPICE and to simulate the example circuits in PSpice and Multi-sim. However, the reader is again reminded of the need to use a more sophisticated model than the level-1 model to accurately predict the circuit performance, especially for deep, sub-micron transistors.
MOSFET Model Parameters Table B.2 provides a listing of some of the MOSFET model parameters used in the level-1 model of SPICE. The reader should already be familiar with these parameters, except for a few, which are described next.
MOSFET Diode Parameters For the two reverse-biased diodes formed between each of the source and drain diffusion regions and the body (see Fig B.4), the saturation-current den-sity is modeled in SPICE by the parameter JS. Furthermore, based on the parameters specified in Table B.2, SPICE will calculate the depletion-layer (junction) capacitances discussed in Section 8.2.1 as (B.5) (B.6) where AD and AS are the areas, while PD and PS are the perimeters of, respectively, the drain and source regions of the MOSFET. The first capacitance term in Eqs. (B.5) and (B.6) represents the depletion-layer (junction) capacitance over the bottom plate of the drain and source regions. The second capacitance term accounts for the depletion-layer capacitance along the sidewall (periphery) of these regions. Both terms are expressed using the formula Cdb CJ 1 VDB PB --------+ ⎝ ⎠ ⎛ ⎞ MJ ------------------------------- AD CJSW 1 VDB PB --------+ ⎝ ⎠ ⎛ ⎞ MJSW ------------------------------------- PD + = Csb CJ 1 VSB PB --------+ ⎝ ⎠ ⎛ ⎞ MJ ------------------------------- AS CJSW 1 VSB PB --------+ ⎝ ⎠ ⎛ ⎞ MJSW ------------------------------------- PS + = B.1 SPICE Device Models B-7 developed in Section 1.12.1 (Eq. 1.80). The values of AD, AS, PD, and PS must be specified by the user based on the dimensions of the device being used.
MOSFET Dimension and Gate-Capacitance Parameters In a fabricated MOSFET, the effective channel length is shorter than the nominal (or drawn) channel length L (as specified by the designer) because the source and drain diffusion regions extend slightly under the gate oxide during fabrication. Furthermore, the effective channel width of the MOSFET is shorter than the nominal or drawn channel width W because of the sideways diffusion into the channel from the body along the width. Based on the parameters specified in Table B.2, (B.7) (B.8) Table B.2 Parameters of the SPICE Level-1 MOSFET Model (Partial Listing) SPICE Parameter Book Symbol Description Units Basic Model Parameters LEVEL MOSFET model selector TOX tox Gate-oxide thickness m COX Cox Gate-oxide capacitance, per unit area F/m2 UO μ Carrier mobility cm2/V.s KP Process transconductance parameter A/V2 LAMBDA λ Channel-length modulation coefficient V−1 Threshold Voltage Parameters VTO Vt 0 Zero-bias threshold voltage V GAMMA γ Body-effect parameter NSUB NA, ND Substrate doping cm–3 PHI 2Φf Surface inversion potential V MOSFET Diode Parameters JS Body-junction saturation-current density A/m2 CJ Zero-bias body-junction capacitance, per unit area F/m2 over the drain/source region MJ Grading coefficient, for area component CJSW Zero-bias body-junction capacitance, per unit length along F/m the sidewall (periphery) of the drain/source region MJSW Grading coefficient, for sidewall component PB V0 Body-junction built-in potential V MOSFET Dimension Parameters LD Lov Lateral diffusion into the channel m from the source/drain diffusion regions WD Sideways diffusion into the channel m from the body along the width MOS Gate-Capacitance Parameters CGBO Gate-body overlap capacitance, per unit channel length F/m CGDO Cov/W Gate-drain overlap capacitance, per unit channel width F/m CGSO Cov/W Gate-source overlap capacitance, per unit channel width F/m k′ V1 2 ⁄ L eff W eff Leff L 2LD – = W eff W 2WD – = B-8 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim In a manner analogous to using Lov to denote LD, we will use the symbol Wov to denote WD.
Consequently, as indicated in Section 8.2.1, the gate-source capacitance Cgs and the gate-drain capacitance Cgd must be increased by an overlap component of, respectively, (B.9) and (B.10) Similarly, the gate-body capacitance Cgb must be increased by an overlap component of (B.11) The reader may have observed that there is a built-in redundancy in specifying the MOS-FET model parameters in SPICE. For example, the user may specify the value of KP for a MOSFET or, alternatively, specify TOX and UO and let SPICE compute KP as UO TOX.
Similarly, GAMMA can be directly specified, or the physical parameters that enable SPICE to determine it can be specified (e.g., NSUB). In any case, the user-specified values will always take precedence over (i.e., override) those values calculated by SPICE. As another example, note that the user has the option of either directly specifying the overlap capaci-tances CGBO, CGDO, and CGSO or letting SPICE compute them as CGDO = CGSO = LD COX and CGBO = WD COX.
Table B.3 provides typical values for the level-1 MOSFET model parameters of a modern 0.18-μm CMOS technology and for older 0.5-μm and 5-μm CMOS technologies. The corre-sponding values for the minimum channel length minimum channel width and the maximum supply voltage are as follows: When simulating a MOSFET circuit, the user needs to specify both the values of the model parameters and the dimensions of each MOSFET in the circuit being simulated. At least the channel length L and width W must be specified. The areas AD and AS and the perimeters PD and PS need to be specified for SPICE to model the body-junction capaci-tances (otherwise, zero capacitances would be assumed). The exact values of these geometry parameters depend on the actual layout of the device (Appendix A). However, to estimate these dimensions, we will assume that a metal contact is to be made to each of the source and drain regions of the MOSFET. For this purpose, typically, these diffusion regions must be extended past the end of the channel (i.e., in the L-direction in Fig. 5.1) by at least 2.75 . Thus, the minimum area and perimeter of a drain/source diffusion region with a contact are, respectively, (B.12) Technology 5-μm CMOS 5 μm 12.5 μm 10 V 0.5-μm CMOS 0.5 μm 1.25 μm 3.3 V 0.18-μm CMOS 0.18 μm 0.22 μm 1.8 V Cgs ov , W CGSO = Cgd ov , W CGDO = Cgb ov , L CGBO = Lmin, Wmin, VDD VSS + ( )max Lmin W min (VDD VSS ) + max Lmin AD = AS = 2.75Lmin W B.1 SPICE Device Models B-9 and (B.13) Unless otherwise specified, we will use Eqs. (B.12) and (B.13) to estimate the dimensions of the drain/source regions in our examples.
Finally, we note that SPICE computes the values for the parameters of the MOSFET small-signal model based on the dc operating point (bias point). These are then used by SPICE to perform the small-signal analysis (ac, or hand, analysis).
B.1.5 The BJT Model SPICE uses a general form of the BJT model that we discussed in Chapter 4 (Fig. 4.7). Known as the transport form of the Ebers-Moll model, it is shown in Fig. B.5. Here, the currents of the base–emitter diode (DBE) and the base–collector diode (DBC) are given, respectively, by (B.14) and (B.15) where nF and nR are the emission coefficients of the BEJ and BCJ, respectively. These coef-ficients are generalizations of the constant n of the pn-junction diode (Fig. B.3). (We have so Table B.3 Values of the Level-1 MOSFET Model Parameters for Two CMOS Technologies1 5-μm CMOS Process 0.5-μm CMOS Process 0.18-μm CMOS Process NMOS PMOS NMOS PMOS NMOS PMOS LEVEL 1 1 1 1 1 1 TOX 8.50e-08 8.50e-08 9.50e-09 9.50e-09 4.08e-09 4.08e-09 UO 750 250 460 115 291 102 LAMBDA 0.01 0.03 0.1 0.2 0.08 0.11 GAMMA 1.4 0.65 0.5 0.45 0.3 0.3 VTO 1 -1 0.7 -0.8 0.5 -0.45 PHI 0.7 0.65 0.8 0.75 0.84 0.8 LD 7.00e-07 6.00e-07 8.00e-08 9.00e-08 10e-9 10e.9 JS 1.00e-06 1.00e-06 1.00e-08 5.00e-09 8.38e-6 4.00e-07 CJ 4.00e-04 1.80e-04 5.70e-04 9.30e-04 1.60e-03 1.00e-03 MJ 0.5 0.5 0.5 0.5 0.5 0.45 CJSW 8.00e-10 6.00e-10 1.20e-10 1.70e-10 2.04e-10 2.04e-10 MJSW 0.5 0.5 0.4 0.35 0.2 0.29 PB 0.7 0.7 0.9 0.9 0.9 0.9 CGBO 2.00e-10 2.00e-10 3.80e-10 3.80e-10 3.80e-10 3.50e-10 CGDO 4.00e-10 4.00e-10 4.00e-10 3.50e-10 3.67e-10 3.43e-10 CGSO 4.00e-10 4.00e-10 4.00e-10 3.50e-10 3.67e-10 3.43e-10 1In PSpice, we have created MOSFET parts corresponding to the above models. Readers can find these parts in the SEDRA.olb library, which is available on the CD accompanying this book. The NMOS and PMOS parts for the 0.5-μm CMOS technology are labeled NMOS0P5_BODY and PMOS0P5_BODY, respectively. The NMOS and PMOS parts for the 5-μm CMOS technol-ogy are labelled NMOS5P0_BODY and PMOS5P0_BODY, respectively. Furthermore, parts NMOS5P0 and PMOS5P0 are cre-ated to correspond to, respectively, part NMOS0P5_BODY with its body connected to net 0 and part PMOS0P5_BODY with its body connected to net VDD. PD = PS = 2 2.75 × Lmin W + iBE IS βF ----- e vBE nFVT ⁄ 1 – ( ) = iBC IS βR ----- e vBC nRVT ⁄ 1 – ( ) = B-10 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim far assumed ). The parameters βF and βR are, respectively, the forward and reverse β of the BJT. The reverse β is the current gain obtained when the collector and emit-ter are interchanged and is much smaller than the forward β. In fact, βR 1. The controlled current-source iCE in the transport model is defined as (B.16) Observe that iCE represents the current component of iC and iE that arises as a result of the minority carrier diffusion across the base, or carrier transport across the base (hence the name transport model). The transport model can account for the Early effect in a forward-biased BJT by including the factor in the expression for the transport current iCE as follows: (B.17) Figure B.6 shows the model used in SPICE. Here, resistors rx, rE, and rC are added to rep-resent the ohmic resistance of, respectively, the base, emitter, and collector regions. The dynamic operation of the BJT is modeled by two nonlinear capacitors, CBC and CBE. Each of these capacitors generally includes a diffusion component (i.e., CDC and CDE) and a depletion or junction component (i.e., CJC and CJE) to account for the charge-storage effects within the BJT (as described in Section 8.2.2). Furthermore, the BJT model includes a depletion junc-tion capacitance CJS to account for the collector–substrate junction in integrated-circuit BJTs, where a reverse-biased pn- junction is formed between the collector and the substrate (which is common to all components of the IC).
For small-signal (ac) analysis, the SPICE BJT model is equivalent to the hybrid-π model of Fig. 8.8, but augmented with rE, rC, and (for IC BJTs) CJS. Furthermore, the model includes a large resistance rμ between the base and collector (in parallel with Cμ) to account for the dependence of iB on vCB. The resistance rμ is very large, typically greater than 10βro.
Although Fig. B.5 shows the SPICE model for the npn BJT, the corresponding model for the pnp BJT can be obtained by reversing the direction of the currents and the polarity of the diodes and terminal voltages.
iCE DBC B E C iB iE DBE iBC iBE iC Figure B.5 The transport form of the Ebers-Moll model for an npn BJT.
nF = nR = 1 iCE IS e vBE nFVT ⁄ e vBC nRVT ⁄ – ( ) = 1 vBC VA ⁄ – ( ) iCE IS e vBE nFVT ⁄ e vBC nRVT ⁄ – ( ) 1 vBC VA --------– ⎝ ⎠ ⎛ ⎞ = B.1 SPICE Device Models B-11 The SPICE Gummel-Poon Model of the BJT The BJT model described above lacks a representation of some second-order effects present in actual devices. One of the most important such effects is the variation of the current gains, βF and βR, with the current iC. The Ebers-Moll model assumes βF and βR to be constant, thereby neglecting their current depen-dence (as depicted in Fig. 4.19). To account for this, and other second-order effects, SPICE uses a more accurate, yet more complex, BJT model called the Gummel-Poon model (named after H. K. Gummel and H. C. Poon, two pioneers in this field). This model is based on the relationship between the electrical terminal characteristics of a BJT and its base charge. It is beyond the scope of this book to delve into the model details. However, it is important for the reader to be aware of the existence of such a model.
In SPICE, the Gummel-Poon model automatically simplifies to the Ebers-Moll model when certain model parameters are not specified. Consequently, the BJT model to be used by SPICE need not be explicitly specified by the user (unlike the MOSFET case in which the model is specified by the LEVEL parameter). For discrete BJTs, the values of the SPICE model parameters can be determined from the data specified on the BJT data sheets, supple-mented (if needed) by key measurements. For instance, in Example PS5.6.1, we will use the Q2N3904 npn BJT (from Fairchild Semiconductor) whose SPICE model is available in PSpice. In fact, the PSpice and Multisim library already includes the SPICE model parame-ters for many of the commercially available discrete BJTs. For IC BJTs, the values of the SPICE model parameters are determined by the IC manufacturer (using both measurements on the fabricated devices and knowledge of the details of the fabrication process) and are provided to the IC designers.
The SPICE BJT Model Parameters Table B.4 provides a listing of some of the BJT model parameters used in SPICE. The reader should be already familiar with these parame-ters. In the absence of a user-specified value for a particular parameter, SPICE uses a default value that typically results in the corresponding effect being ignored. For example, if no value is specified for the forward Early voltage (VAF), SPICE assumes that VAF = ∞ and does not account for the Early effect. Although ignoring VAF can be a serious issue in some circuits, the same is not true, for example, for the value of the reverse Early voltage (VAR). Figure B.6 The SPICE large-signal model for an npn BJT.
iCE CJS CBC CDC CJC CBE CDE CJE B E S (Substrate) iBC iBE rC C rx rE B-12 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The BJT Model Parameters BF and BR in SPICE Before leaving the SPICE model, a comment on β is in order. SPICE interprets the user-specified model parameters BF and BR as the ideal maximum values of the forward and reverse dc current gains, respectively, versus the operating current. These parameters are not equal to the constant-current-independent param-eters βF (βdc) and βR used in the Ebers-Moll model for the forward and reverse dc current gains of the BJT. SPICE uses a current-dependent model for βF and βR, and the user can specify other parameters (not shown in Table B.4) for this model. Only when such parameters are not specified, and the Early effect is neglected, will SPICE assume that βF and βR are constant and equal to BF and BR, respectively. Furthermore, SPICE computes values for both βdc and βac, the two parameters that we generally assume to be approximately equal. SPICE then uses βac to perform small-signal (ac) analysis.
Table B.4 Parameters of the SPICE BJT Model (Partial Listing) SPICE Parameter Book Symbol Description Units IS IS Saturation current A BF βF Ideal maximum forward current gain BR βR Ideal maximum reverse current gain NF nF Forward current emission coefficient NR nR Reverse current emission coefficient VAF VA Forward Early voltage V VAR Reverse Early voltage V RB rx Zero-bias base ohmic resistance Ω RC rC Collector ohmic resistance Ω RE rE Emitter ohmic resistance Ω TF τF Ideal forward transit time s TR τR Ideal reverse transit time s CJC Cμ0 Zero-bias base–collector depletion F (junction) capacitance MJC mBCJ Base–collector grading coefficient VJC V0c Base–collector built-in potential V CJE Cje0 Zero-bias base–emitter depletion F (junction) capacitance MJE mBEJ Base–emitter grading coefficient VJE V0e Base–emitter built-in potential V CJS Zero-bias collector–substrate depletion F (junction) capacitance MJS Collector–substrate grading coefficient VJS Collector–substrate built-in potential V B.2 PSpice Examples B-13 B.2 PSpice Examples Example PS.2.1 Performance of a Noninverting Amplifier Consider an op amp with a differential input resistance of 2 MΩ, an input offset voltage of 1 mV, a dc gain of 100 dB, and an output resistance of 75 Ω. Assume the op amp is internally compensated and has an STC frequency response with a gain–bandwidth product of 1 MHz.
(a) Create a subcircuit model for this op amp in PSpice.
(b) Using this subcircuit, simulate the closed-loop noninverting amplifier in Fig. 2.12 with resistors R1 = 1 kΩ and R2 = 100 kΩ to find: (i) Its 3-dB bandwidth f3dB. (ii) Its output offset voltage VOSout.
(iii) Its input resistance Rin.
(iv) Its output resistance Rout.
(c) Simulate the step response of the closed-loop amplifier, and measure its rise time tr. Verify that this time agrees with the 3-dB frequency measured above.
Solution To model the op amp in PSpice, we use the equivalent circuit in Fig. B.2, but with Rid = 2 MΩ, Ricm = ∞ (open circuit), IB1 = IB2 = 0 (open circuit), VOS = 1 mV, A0d = 105 V/V, A0cm = 0 (short circuit), and Ro = 75 Ω. Furthermore, we set Cb = 1 μF and Rb = 15.915 kΩ to achieve an ft = 1 MHz.
To measure the 3-dB frequency of the closed-loop amplifier, we apply a 1-V ac voltage at its input, perform an ac-analysis simulation in PSpice, and plot its output versus frequency. The output voltage, plotted in Fig. B.7, corresponds to the gain of the amplifier because we chose an input voltage of 1 V. Figure B.7 Frequency response of the closed-loop amplifier in Example PS.2.1.
0 V 20 V 40 V 60 V 80 V 1.0 10 100 1.0 K Frequency (Hz) 10 K 100 K 1.0 M 10 M 100 V V(OUT) (9.900 kHz, 71.347 V) B-14 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Example PS.2.1 continued Thus, from Fig. B.7, the closed-loop amplifier has a dc gain of G0 = 100.9 V/V, and the frequency at which its gain drops to is f3dB = 9.9 kHz, which agrees with Eq. (B.7).
The input resistance Rin corresponds to the reciprocal of the current drawn out of the 1-V ac voltage source used in the above ac-analysis simulation at 0.1 Hz. (Theoretically, Rin is the small-signal input resistance at dc. However, ac-analysis simulations must start at frequencies greater than zero, so we use 0.1 Hz to approximate the dc point.) Accordingly, Rin is found to be 2 GΩ.
To measure Rout, we short-circuit the amplifier input to ground, inject a 1-A ac current at its output, and perform an ac-analysis simulation. Rout corresponds to the amplifier output voltage at 0.1 Hz and is found to be 76 mΩ. Although an ac test voltage source could equally well have been used to measure the output resis-tance in this case, it is a good practice to attach a current source rather than a voltage source between the output and ground. This is because an ac current source appears as an open circuit when the simulator computes the dc bias point of the circuit while an ac voltage source appears as a short circuit, which can erroneously force the dc output voltage to zero. For similar reasons, an ac test voltage source should be attached in series with the biasing dc voltage source for measuring the input resistance of a voltage amplifier.
A careful look at Rin and Rout of the closed-loop amplifier reveals that their values have, respectively, increased and decreased by a factor of about 1000, relative to the corresponding resistances of the op amp. Such a large input resistance and small output resistance are indeed desirable characteristics for a voltage amplifier. This improvement in the small-signal resistances of the closed-loop amplifier is a direct consequence of applying negative feedback (through resistors R1 and R2) around the open-loop op amp.
We will study negative feedback in Chapter 9, where we will also learn how the improvement factor (1000 in this case) corresponds to the ratio of the open-loop op-amp gain (105) to the closed-loop ampli-fier gain (100). From Eqs. (2.55) and (2.53), the closed-loop amplifier has an STC low-pass response given by As described in Appendix E, the response of such an amplifier to an input step of height Vstep is given by (B.18) where Vfinal = G0Vstep is the final output-voltage value (i.e., the voltage value toward which the output is heading) and is the time constant of the amplifier. If we define t10% and t90% to be the time it takes for the output waveform to rise to, respectively, 10% and 90% of Vfinal, then from Eq. (B.18), t10% 0.1τ and t90% 2.3τ. Therefore, the rise time tr of the amplifier can be expressed as Therefore, if f3dB = 9.9 kHz, then tr = 35.4 μs. To simulate the step response of the closed-loop amplifier, we apply a step voltage at its input, using a piecewise-linear (PWL) source (with a very short rise time); then per-form a transient-analysis simulation, and measure the voltage at the output versus time. In our simulation, we applied a 1-V step input, plotted the output waveform in Fig. B.8, and measured tr to be 35.3 μs.
The linear macromodels in Figs. B.1 and B.2 assume that the op-amp circuit is operating in its linear range; they do not account for its nonideal performance when large signals are present at the output.
Therefore, nonlinear effects, such as output saturation and slew rate, are not modeled. This is why, in the step response of Fig. B.8, we could see an output voltage of 100 V when we applied a 1-V step input.
However, IC op amps are not capable of producing such large output voltages. Hence, a designer must be very careful when using these models.
G0 2 71.35 V/V = ⁄ V o s ( ) V i s ( ) -------------G0 1 s 2πf3dB ---------------+ -------------------------= vO t ( ) Vfinal 1 e t – τ ⁄ – ( ) = τ 1 2πf3dB ( ) ⁄ = tr t90% t10% – 2.2τ 2.2 2πf3dB ---------------= = = B.2 PSpice Examples B-15 It is important to point out that we also saw output voltages of 100 V or so in the ac analysis of Fig.
B.7, where for convenience we applied a 1-V ac input to measure the gain of the closed-loop amplifier. So, would we see such large output voltages if the op-amp macromodel accounted for nonlinear effects (particularly output saturation)? The answer is yes, because in an ac analysis PSpice uses a linear model for nonlinear devices with the linear-model parameters evaluated at a bias point. Thus, we must keep in mind that the voltage magnitudes encountered in an ac analysis may not be realistic. In this case, the voltage and current ratios (e.g., the output-to-input voltage ratio as a measure of voltage gain) are of importance to the designer.
Characteristics of the 741 OP Amp Consider the μA741 op amp whose macromodel is available in PSpice. Use PSpice to plot the open-loop gain and hence determine ft. Also, investigate the SR limitation and the output saturation of this op amp.
Solution Figure B.9 shows the schematic capture used to simulate the frequency response of the μA741 op amp.1 The μA741 part has seven terminals. Terminals 7 and 4 are, respectively, the positive and negative dc power-supply Figure B.8 Step response of the closed-loop amplifier in Example PS.2.1.
1The reader is reminded that the schematic capture diagram and the corresponding PSpice simulation files of all SPICE examples in this book can be found on the text’s CD. 0 20 40 60 Time (s) 80 100 120 0 V 20 V 40 V 60 V 80 V 100 V V(OUT) (37.0 s, 90.9 V) (1.7 s, 10.1 V) Example PS.2.2 B-16 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim terminals of the op amp. The 741-type op amps are typically operated from ±15-V power supplies; therefore we connected the dc voltage sources VCC = +15 V and VEE = −15 V to terminals 7 and 4, respectively.
Terminals 3 and 2 of the μA741 part correspond to the positive and negative input terminals, respectively, of the op amp. In general, as outlined in Section 2.1.3, the op-amp input signals are expressed as where vINP and vINN are the signals at, respectively, the positive- and negative-input terminals of the op amp with VCM being the common-mode input signal (which sets the dc bias voltage at the op-amp input terminals) and V d being the differential input signal to be amplified. The dc voltage source VCM in Fig. B.9 is used to set the common-mode input voltage. Typically, VCM is set to the average of the dc power-supply voltages VCC and VEE to maximize the available input signal swing. Hence, we set VCM = 0. The voltage source Vd in Fig. B.9 is used to generate the differential input signal Vd. This signal is applied differen-tially to the op-amp input terminals using the voltage-controlled voltage sources Ep and En, whose gain constants are set to 0.5.
Terminals 1 and 5 of part μA741 are the offset-nulling terminals of the op amp (as depicted in Fig. 2.36). However, a check of the PSpice netlist of this part (by selecting Edit → PSpice Model, in the Capture menus), reveals that these terminals are floating; therefore the offset-nulling characteristic of the op amp is not incorporated in this macromodel.
To measure ft of the op amp, we set the voltage of source Vd to be 1-V ac, perform an ac-analysis simu-lation in PSpice, and plot the output voltage versus frequency as shown in Fig. B.10. Accordingly, the fre-quency at which the op-amp voltage gain drops to 0 dB is ft = 0.9 MHz (which is close to the 1-MHz value reported in the data sheets for 741-type op amps).
To determine the slew rate of the μA741 op amp, we connect the op amp in a unity-gain configura-tion, as shown in Fig. B.11, apply a large pulse signal at the input with very short rise and fall times to Figure B.9 Simulating the frequency response of the μA741 op-amp in Example PS.2.2.
VEE 0 VCC d Vd 1Vac 0Vdc DC 15V DC 15V 0 d INP Ep En d CM VCM 0Vdc INN 0 0 0 Gain 0.5 Gain 0.5 INP 3 uA741 2 INN 7 4 VCC VEE V V 5 6 1 OS2 OS1 OUT vINP V CM + V d 2 -----= vINN V CM V d 2 -----– = Example PS.2.2 continued In these schematics (as shown in Fig. B.13), we use variable parameters to enter the values of the various circuit com-ponents. This allows one to investigate the effect of changing component values by simply changing the corresponding parameter values.
B.2 PSpice Examples B-17 cause slew-rate limiting at the output, perform a transient-analysis simulation in PSpice, and plot the out-put voltage as shown in Fg. B.12. The slope of the slew-rate limited output waveform corresponds to the slew-rate of the op amp and is found to be SR = 0.5 V/μs (which agrees with the value specified in the data sheets for 741-type opi amps).
Figure B.10 Frequency response of the μA741 op amp in Example PS.2.2.
Figure B.11 Circuit for determining the slew rate of the μA741 op amp in Example PS.5.2.2.
20 0 40 80 120 1.0 10 100 1.0 K Frequency (Hz) 10 K 100 K 1.0 M 10 M dB (V(OUT)) ft 888 kHz 0 V1 1 V2 1 TD 0 TR 1n TF 1n PW 20 PER 40 INP 3 uA741 2 7 4 VCC VEE V V 5 6 1 OS2 OS1 OUT VEE VCC 0 DC 15V DC 15V B-18 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim To determine the maximum output voltage of the μA741 op amp, we set the dc voltage of the differ-ential voltage source Vd in Fig. B.9 to a large value, say +1 V, and perform a bias-point simulation in PSpice. The corresponding dc output voltage is the positive-output saturation voltage of the op amp. We repeat the simulation with the dc differential input voltage set to −1 V to find the negative-output satura-tion voltage. Accordingly, we find that the μA741 op amp has a maximum output voltage Vomax = 14.8 V.
Design of a DC Power Supply In this example, we will design a dc power supply using the rectifier circuit whose capture schematic is shown in Fig. B.13. This circuit consists of a full-wave diode rectifier, a filter capacitor, and a zener volt-age regulator. The only perhaps puzzling component is the Risolation, the 100-MΩ resistor between the second-ary winding of the transformer and ground. This resistor is included to provide dc continuity and thus “keep SPICE happy”; it has little effect on circuit operation.
Let it be required that the power supply (in Fig. B.13) provide a nominal dc voltage of 5 V and be able to supply a load current Iload as large as 25 mA; that is, Rload can be as low as 200 Ω. The power supply is fed from a 120-V (rms) 60-Hz ac line. Note that in the PSpice schematic (Fig. B.13), we use a sinusoi-dal voltage source with a 169-V peak amplitude to represent the 120-V rms supply (as 120-V rms = 169-V peak). Assume the availability of a 5.1-V zener diode having rz = 10 Ω at IZ = 20 mA (and thus VZ0 = 4.9 V), and that the required minimum current through the zener diode is IZmin = 5 mA.
Figure B.12 Square-wave response of the μA741 op amp connected in the unity-gain configuration shown in Fig. B.11.
1.2 V 0.8 V 0.4 V 0 V 0.4 V 0.8 V 0 10 20 30 40 Time (s) 50 70 60 80 1.2 V Slope 0.5 Vs Slope 0.5 V/s V(OUT) Example PS.4.1 Example PS.2.2 continued B.2 PSpice Examples B-19 An approximate first-cut design can be obtained as follows: The 120-V (rms) supply is stepped down to provide 12-V (peak) sinusoids across each of the secondary windings using a 14:1 turns ratio for the center-tapped transformer. The choice of 12 V is a reasonable compromise between the need to allow for sufficient voltage (above the 5-V output) to operate the rectifier and the regulator, while keeping the PIV ratings of the diodes reasonably low. To determine a value for R, we can use the following expression: where an estimate for VCmin, the minimum voltage across the capacitor, can be obtained by subtracting a diode drop (say, 0.8 V) from 12 V and allowing for a ripple voltage across the capacitor of, say, Vr = 0.5 V. Thus, VSmin = 10.7 V. Furthermore, we note that ILmax = 25 mA and IZmin = 5 mA, and that VZ0 = 4.9 V and rz = 10 Ω. The result is that R = 191 Ω.
Next, we determine C using a restatement of Eq. (3.33) with Vp/R replaced by the current through the 191-Ω resistor. This current can be estimated by noting that the voltage across C varies from 10.7 V to 11.2 V, and thus has an average value of 10.95 V. Furthermore, the desired voltage across the zener is 5 V. The result is C = 520 μF. Now, with an approximate design in hand, we can proceed with the SPICE simulation. For the zener diode, we use the model of Fig. B.4, and assume (arbitrarily) that D1 has IS = 100 pA and n = 0.01 while D2 has IS = 100 pA and n = 1.7. For the rectifier diodes, we use the commercially available 1N4148 type2 (with IS = 2.682 nA, n = 1.836, RS = 0.5664 Ω, V0 = 0.5 V, Cj0 = 4 pF, m = 0.333, τT = 11.54 ns, VZK = 100 V, IZK = 100 μA).
In PSpice, we perform a transient analysis and plot the waveforms of both the voltage vC across the smoothing capacitor C and the voltage vO across the load resistor Rload. The simulation results for Rload = 200 Ω (Iload 25 mA) are presented in Fig. B.14. Observe that vC has an average of 10.85 V and a ripple of ± 0.21 V. Thus, Vr = 0.42 V, which is close to the 0.5-V value that we would expect from the chosen value of C. The output voltage vO is very close to the required 5 V, with vO varying between 4.957 V and 4.977 V for a ripple of only 20 mV. The variations of vO with Rload are illustrated in Fig. B.15 for Rload = 500 Ω, 250 Ω, 200 Ω, and 150 Ω. Accordingly, vO remains close to the nominal value of 5 V for Rload as Figure B.13 Schematic capture of the 5-V dc power supply in Example PS.4.1.
2The 1N4148 model is included in the evaluation (EVAL) library of PSpice, which is available on the CD ac-companying this book. PARAMETERS: C 520u R 191 Risolation 100E6 Rload 200 Rs 0.5 3 2 1 7 6 4 0 Vsin {Rload} Zener_diode {Risolation} Ls1 Ls2 Lp {R} {C} D1 D1N4148 5 D2 D1N4148 0 0 {Rs} VOFF 0 VAMPL 169 FREQ 60 R VCmin VZ0 – rzIZmin – IZmin ILmax + --------------------------------------------------= B-20 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.14 The voltage vC across the smoothing capacitor C and the voltage vO across the load resistor Rload = 200 Ω in the 5-V power supply of Example PS.4.1.
Figure B.15 The output-voltage waveform from the 5-V power supply (in Example PS.4.1) for various load resis-tances: Rload = 500 Ω, 250 Ω, 200 Ω, and 150 Ω. The voltage regulation is lost at a load resistance of 150 Ω.
Time (s) 0 50m 100m 150m 200m 0V 2V 4V 6V 8V 10V 12V Smoothing Capacitor Voltage VC Load Voltage VO V (7, 4) V (6, 4) Rload 150 Ω Time (ms) 160 165 170 175 180 185 190 195 200 4.50V 4.75V 5.00V 5.25V V (7, 4) Rload 500 Ω Rload 250 Ω Rload 200 Ω Example PS.4.1 continued B.2 PSpice Examples B-21 low as 200 Ω (Iload 25 mA). For Rload = 150 Ω (which implies Iload 33.3 mA, greater than the maximum designed value), we see a significant drop in vO (to about 4.8 V), as well as a large increase in the ripple voltage at the output (to about 190 mV). This is because the zener regulator is no longer operational; the zener has in fact cut off.
We conclude that the design meets the specifications, and we can stop here. Alternatively, we may consider using further runs of PSpice to help with the task of fine-tuning the design. For instance, we could consider what happens if we use a lower value of C, and so on. We can also investigate other prop-erties of the present design (e.g., the maximum current through each diode) and ascertain whether this maximum is within the rating specified for the diode. B.1 Use PSpice to investigate the operation of the voltage doubler whose schematic capture is shown in Fig. B.16(a). Specifically, plot the transient behavior of the voltages v2 and vout when the input is a sinu-soid of 10-V peak and 1-kHz frequency. Assume that the diodes are of the 1N4148 type (with IS = 2.682 nA, n = 1.836, RS = 0.5664 Ω, V0 = 0.5 V, Cj0 = 4 pF, m = 0.333, τT = 11.54 ns, VZK = 100 V, IZK = 100 μA).
Ans. The voltage waveforms are shown in Fig. B.16(b).
(a) {C2} {C1} D1 D1N4148 0 0 2 D2 D1N4148 OUT IN 0 VOFF 0 VAMPL 10V FREQ 1K PARAMETERS: C1 1u C2 1u Figure B.16 (a) Schematic capture of the voltage-doubler circuit in Exercise B.1. (b) Various voltage waveforms in the voltage-doubler circuit. The top graph displays the input sine-wave voltage signal, the middle graph displays the voltage across diode D1, and the bottom graph displays the voltage that appears at the output.
EXERCISE B-22 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.16 continued (b) Time (s) 0 1m 2m 3m 4m 5m 6m 7m 8m 9m 10m 20V 15V 10V 5V 0V V (IN) 10V 5V 0V 5V 10V 20V 10V 0V 10V 20V V (2) V (OUT) B.2 PSpice Examples B-23 The CS Amplifier In this example, we will use PSpice to analyze and verify the design of the CS amplifier whose capture schematic is shown in Fig. B.17.3 Observe that the MOSFET has its source and body connected in order to cancel the body effect. We will assume a 0.5-μm CMOS technology for the MOSFET and use the SPICE level-1 model parameters listed in Table B.3. We will also assume a signal-source resistance Rsig = 10 kΩ, a load resistance RL = 50 kΩ, and bypass and coupling capacitors of 10 μF. The targeted specifica-tions for this CS amplifier are a midband gain AM = 10 V/V and a maximum power consumption P = 1.5 mW. As should always be the case with computer simulation, we will begin with an approximate pencil-and-paper design. We will then use PSpice to fine-tune our design and to investigate the perfor-mance of the final design. In this way, maximum advantage and insight can be obtained from simulation.
With a 3.3-V power supply, the drain current of the MOSFET must be limited to to meet the power consumption specification. Choosing VOV = 0.3 V (a typical value in low-voltage designs) and (to achieve a large signal swing at the out-put), the MOSFET can now be sized as (B.19) where = 170.1 μA/V2 (from Table B.3). Here, Leff rather than L is used to more accurately compute ID. The effect of using Weff rather than W is much less important because typically W Wov.
Thus, choosing L = 0.6 μm results in Leff = L − 2Lov = 0.44 μm and W = 23.3 μm. Note that we chose L 3The reader is reminded that the schematic capture diagrams and the corresponding PSpice simulation files of all SPICE examples in this book can be found on the text’s CD. In these schematics (as shown in Fig. B.17), we used variable parameters to enter the values of the various circuit components, including the dimensions of the MOSFET. This will allow the reader to investigate the effect of changing component values by simply changing the corresponding parameter values.
Figure B.17 Schematic capture of the CS amplifier in Example PS.5.1.
Example PS.5.1 ID = P V DD ⁄ = 1.5 mW 3.3 V ⁄ 0.45 mA = VDS VDD 3 ⁄ = W Leff --------ID 1 2 --- kn ′VOV 2 1 λVDS + ( ) -----------------------------------------------0.45 10 3 – × 1 2 --- 170.1 10 6 – × ( ) 0.3 ( )2 1 0.1 1.1 ( ) + [ ] ---------------------------------------------------------------------------------------- 53 = = kn ′ μnCox = PARAMETERS: CCI 10u CCO 10u CS 10u RD 4.2K RG1 2E6 RG2 1.3E6 RL 50K RS 630 Rsig 10K W 22u L 0.6u VDD 3.3 IN OUT W {W} L {L} 0 {CCO} {RD} VDD {RL} {RG1} {Rsig} VDD {CS} 0 0 {RS} 0 {RG2} {CCI} 1Vac 0Vdc 0 VDD DC {VDD} 0 B-24 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim slightly larger than Lmin. This is a common practice in the design of analog ICs to minimize the effects of fabrication nonidealities on the actual value of L. As shown in the text, this is particularly important when the circuit performance depends on the matching between the dimensions of two or more MOSFETs (e.g., in the current-mirror circuits studied in Chapter 6). Next, RD is calculated based on the desired voltage gain: (B.20) where gm = 3.0 mA/V and ro = 22.2 kΩ. Hence, the output bias voltage is 1.39 V. An is needed to bias the MOSFET at a Finally, resistors RG1 = 2 MΩ and RG2 = 1.3 MΩ are chosen to set the gate bias voltage at . Using large values for these gate resistors ensures that both their power consumption and the loading effect on the input signal source are negligible. Note that we neglected the body effect in the expression for VG to simplify our hand calculations.
We will now use PSpice to verify our design and investigate the performance of the CS amplifier. We begin by performing a bias-point simulation to verify that the MOSFET is properly biased in the satura-tion region and that the dc voltages and currents are within the desired specifications. Based on this simu-lation, we have decreased the value of W to 22 μm to limit ID to about 0.45 mA. Next, to measure the midband gain AM and the 3-dB frequencies4 fL and fH, we apply a 1-V ac voltage at the input, perform an ac-analysis simulation, and plot the output-voltage magnitude (in dB) versus frequency as shown in Fig. B.18. This corresponds to the magnitude response of the CS amplifier because we chose a 1-V input signal.5 Accordingly, the midband gain is AM = 9.55 V/V and the 3-dB bandwidth is BW = fH − fL 122.1 MHz. Figure B.18 further shows that the gain begins to fall off at about 300 Hz but flattens out again at about 10 Hz. This flattening in the gain at low frequencies is due to a real transmission zero6 introduced in the transfer function of the amplifier by RS together with CS. This zero occurs at a frequency = 25.3 Hz, which is typically between the break frequencies fP2 and fP3 derived in Sec-tion 8.1.1. So, let us now verify this phenomenon by resimulating the CS amplifier with a CS = 0 (i.e., removing CS) in order to move fZ to infinity and remove its effect. The corresponding frequency response is plotted also in Fig. B.18. As expected, with CS = 0, we do not observe any flattening in the low-frequency response of the amplifier. However, because the CS amplifier now includes a source resistor RS, AM has dropped by a factor of 2.6. This factor is approximately equal to (1 + gmRS), as expected from our study of the CS amplifier with a source-degeneration resistance in Section 5.6.4.
Note that the bandwidth BW has increased by approximately the same factor as the drop in gain AM. As we will learn in Chapter 9 when we study negative feedback, the source-degeneration resistor RS pro-vides negative feedback, which allows us to trade off gain for wider bandwidth.
To conclude this example, we will demonstrate the improved bias stability achieved when a source resistor RS is used (see the discussion in Section 5.7.2). Specifically, we will change (in the MOSFET level-1 model for part NMOS0P5) the value of the zero-bias threshold voltage parameter VT0 by ±15% and perform a bias-point simulation in PSpice. Table B.5 shows the corresponding variations in ID and VO for the case in which . For the case without source degeneration, we use an in the 4No detailed knowledge of frequency-response calculations is required for this example; all that is needed is Section 5.8.6. Nevertheless, after the study of the frequency response of the CS amplifier in Sections 8.1 through 8.3, the reader will benefit by returning to this example and using PSpice to experiment further with the circuit.
5The reader should not be alarmed about the use of such a large signal amplitude. Recall that in a small-signal (ac) simulation, SPICE first finds the small-signal equivalent circuit at the bias point and then analyzes this linear circuit. Such ac analysis can, of course, be done with any ac signal amplitude. However, a 1-V ac input is conven-ient to use because the resulting ac output corresponds to the voltage gain of the circuit.
6Readers who have not yet studied poles and zeros can skip these few sentences.
Av gm RD RL ro || || ( ) 10 V/V RD 4.2 kΩ ⇒ = = V O = V DD IDRD = – RS VO VDD 3 ⁄ – ( ) ID ⁄ = 630 Ω = VDS VDD 3.
⁄ = VG IDRS VOV Vtn + + 1.29 V = fZ 1 (2π ⁄ RSCS) = RS 630 Ω = RS = 0 Example PS.5.1 continued B.2 PSpice Examples B-25 schematic of Fig. B.17. Furthermore, to obtain the same ID and VO in both cases (for the nominal threshold voltage Vt0 = 0.7 V), we use an RG2 = 0.88 MΩ to reduce VG to around . The correspond-ing variations in the bias point are shown in Table B.5. Accordingly, we see that the source-degeneration resistor makes the bias point of the CS amplifier less sensitive to changes in the threshold voltage. In fact, the reader can show for the values displayed in Table B.5 that the variation in bias current is reduced by approximately the same factor, (1 + gmRS). However, unless a large bypass capacitor CS is used, this reduced sensitivity comes at the expense of a reduction in the midband gain (as we observed in this example when we simulated the frequency response of the CS amplifier with a CS = 0).
Figure B.18 Frequency response of the CS amplifier in Example PS.5.1 with CS = 10 μF and CS = 0 (i.e., CS removed).
Table B.5 Variations in the Bias Point with the MOSFET Threshold Voltage Vtn0 RS = 630Ω RS = 0 ID (mA) VO (V) ID (mA) VO (V) 0.60 0.56 0.962 0.71 0.33 0.7 0.46 1.39 0.45 1.40 0.81 0.36 1.81 0.21 2.40 Frequency (Hz) 100m 1.0 10m 100 1.0K 10 100K 1.0M 10K 100M 1.0G 10M 20 15 10 5 0 dB (V(OUT)) CS 10 uF CS 0 AM 19.6 dB AM 11.3 dB fH 122.1 MHz fL 54.2 Hz fL 0.3 Hz fH 276.5 MHz V OV Vtn + 1 V = ΔI I ⁄ ( ) B-26 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Dependence of the BJT β on the Bias Current In this example, we use PSpice to simulate the dependence of βdc on the collector bias current for the Q2N3904 discrete BJT (from Fairchild Semiconductor) whose model parameters are listed in Table B.6 and are available in PSpice.7 As shown in the schematic capture8 of Fig. B.19, the VCE of the BJT is fixed using a constant voltage source (in this example, VCE = 2 V) and a dc current source IB is applied at the base. To illustrate the dependence of βdc on the collector current IC, we perform a dc-analysis simulation in which the sweep variable is the current source IB. The βdc of the BJT, which corresponds to the ratio of the collector current IC to the base current IB, can then be plotted versus IC using Probe (the graphical interface of PSpice), as shown in Fig. B.20. We see that to operate at the maximum value of βdc (i.e., βdc = 163), at VCE = 2 V, the BJT must be biased at an IC = 10 mA. Since increasing the bias current of a transis-tor increases the power dissipation, it is clear from Fig. B.20 that the choice of current IC is a trade-off between the current gain βdc and the power dissipation. Generally speaking, the optimum IC depends on the application and technology in hand. For example, for the Q2N3904 BJT operating at VCE = 2 V, decreasing IC by a factor of 20 (from 10 mA to 0.5 mA) results in a drop in βdc of about 25% (from 163 to 123). 7The Q2N3904 model is included in the evaluation (EVAL) library of PSpice which is available on the CD ac-companying this book.
8 The reader is reminded that the schematics diagrams and the corresponding PSpice simulation files of all SPICE examples in this book can be found on the text’s CD. In these schematics (as shown in Fig. B.19), we use variable parameters to enter the values of the various circuit components. This allows one to investigate the effect of changing component values by simply changing the corresponding parameter values.
Figure B.19 The PSpice test bench used to demonstrate the dependence of βdc on the collector bias current IC for the Q2N3904 discrete BJT (Example PS.6.1).
Table B.6 Spice Model Parameters of the Q2N3904 Discrete BJT IS=6.734F XTI=3 EG=1.11 VAF=74.03 BF=416.4 NE=1.259 ISE=6.734F IKF=66.78M XTB=1.5 BR=.7371 NC=2 ISC=0 IKR=0 RC=1 CJC=3.638P MJC=.3085 VJC=.75 FC=.5 CJE=4.493P MJE=.2593 VJE=.75 TR=239.5N TF=301.2P ITF=.4 VTF=4 XTF=2 RB=10 Example PS.6.1 {IB} IB 10u VCE 2V Q1 DC {VCE} 0 0 0 Q2N3904 PARAMETERS: B.2 PSpice Examples B-27 The CE Amplifier with Emitter Resistance In this example, we use PSpice to analyze and verify the design of the CE amplifier. A schematic capture of the CE amplifier is shown in Fig. B.21. We will use part Q2N3904 for the BJT and a ±5-V power sup-ply. We will also assume a signal source resistor Rsig = 10 kΩ, a load resistor RL = 10 kΩ, and bypass and coupling capacitors of 10 μF. To enable us to investigate the effect of including a resistance in the signal path of the emitter, a resistor Rce is connected in series with the emitter bypass capacitor CE. Note that the roles of RE and Rce are different. Resistor RE is the dc emitter-degeneration resistor because it appears in the dc path between the emitter and ground. It is therefore used to help stabilize the bias point for the amplifier. The equivalent resistance is the small-signal emitter-degeneration resistance because it appears in the ac (small-signal) path between the emitter and ground and helps stabilize the gain of the amplifier. In this example, we will investigate the effects of both RE and Re on the performance of the CE amplifier. However, as should always be the case with computer simulation, we will begin with an approximate pencil-and-paper design. In this way, maximum advantage and insight can be obtained from simulation.
Based on the plot of βdc versus IC in Fig. B.20, a collector bias current IC of 0.5 mA is selected for the BJT, resulting in βdc = 123. This choice of IC is a reasonable compromise between power dissipation and current gain. Furthermore, a collector bias voltage VC of 0 V (i.e., at the mid–supply rail) is selected to Figure B.20 Dependence of βdc on IC (at VCE = 2 V) in the Q2N3904 discrete BJT (Example PS.6.1).
IC (Q1) 0 A 5m A 10 mA 15 mA 20 mA 25 mA 30 mA IC (Q1)IB (Q1) 0 25 50 75 100 125 150 175 IC 0.5 mA, bdc 122.9 IC 10 mA, bdc 162.4 VCE 2V Example PS.6.2 Re = RE Rce || B-28 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim achieve a high signal swing at the amplifier output. For VCE = 2 V, the result is that VE = −2 V requires bias resistors with values and Assuming VBE = 0.7 V and using βdc = 123, we can determine Next, the formulas of Section 4.8.3 can be used to determine the input resistance and the midband volt-age gain of the CE amplifier: (B.21) (B.22) For simplicity, we will assume resulting in Thus, with no small-signal emitter degeneration (i.e., Rce = 0), and .
Using Eq. (B.22) and assuming is large enough to have a negligible effect on , it can be shown that Figure B.21 Schematic capture of the CE amplifier in Example PS.6.2.
IN VCC Q2N3904 OUT DC {VCC} 0 VEE DC {VEE} 0 0 {CCO} {RC} VCC VEE {RL} {Rce} {Rsig} {CE} 0 {RE} 0 {RB} {CCI} AC Source 1Vac 0Vdc 0 CE 10u CCI 10u CCO 10u RC 10K RB 340K RE 6K Rce 130 RL 10K Rsig 10K VCC 5 VEE 5 PARAMETERS: RC VCC VC – IC ----------------------10 kΩ = = RE VE VEE – IC ---------------------6 kΩ = = RB VB IB ------– 0 VBE V + E ( ) – IC βdc ⁄ -----------------------------------– 320 kΩ = = = Rin AM Rin RB βac 1 + ( ) || re R + e ( ) = AM Rin Rsig Rin + ----------------------– RC RL || re R + e ------------------× = βac βdc 123, = re βac βac 1 + ----------------⎝ ⎠ ⎛ ⎞VT IC ------⎝ ⎠ ⎛ ⎞ 49.6 Ω = = Rin 6.1 kΩ = AM = 38.2 V/V RB Rin Example PS.6.2 continued B.2 PSpice Examples B-29 the emitter-degeneration resistor Re decreases the voltage gain by a factor of Therefore, to limit the reduction in voltage gain to a factor of 2, we will select (B.23) Thus, . Substituting this value in Eqs. (B.21) and (B.22) shows that increases from to while drops from 38.2 V/V to 18.8 V/V.
We will now use PSpice to verify our design and investigate the performance of the CE amplifier. We begin by performing a bias-point simulation to verify that the BJT is properly biased in the active region and that the dc voltages and currents are within the desired specifications. Based on this simulation, we have increased the value of RB to in order to limit IC to about 0.5 mA while using a standard 1% resistor value (Appendix H). Next, to measure the midband gain AM and the 3-dB frequencies9 fL and fH, we apply a 1-V ac voltage at the input, perform an ac-analysis simulation, and plot the output-voltage magnitude (in dB) versus frequency as shown in Fig. B.22. This corresponds to the magnitude response of the CE amplifier because we chose a 1-V input signal.10 Accordingly, with no emitter degeneration, the midband gain is |AM| = 38.5 V/V = 31.7 dB and the 3-dB bandwidth is BW = fH − fL = 145.7 kHz. Using an results in a drop in the midband gain |AM| by a factor of 2 (i.e., 6 dB). Interestingly, how-ever, BW has now increased by approximately the same factor as the drop in |AM|. As we learned in Chap-ter 9 in our study of negative feedback, the emitter-degeneration resistor Rce provides negative feedback, which allows us to trade off gain for other desirable properties, such as a larger input resistance and a wider bandwidth.
To conclude this example, we will demonstrate the improved bias-point (or dc operating-point) stabil-ity achieved when an emitter resistor RE is used (see the discussion in Section 4.7.1). Specifically, we will increase/decrease the value of the parameter BF (i.e., the ideal maximum forward current gain) in the SPICE model for part Q2N3904 by a factor of 2 and perform a bias-point simulation. The corresponding change in BJT parameters (βdc and βac) and bias-point (including IC and CE) are presented in Table B.7 for the case of . Note that βac is not equal to βdc as we assumed, but is slightly larger. For the case without emitter degeneration, we will use in the schematic of Fig. B.21. Furthermore, to maintain the same IC and VC in both cases at the values obtained for nominal BF, we use RB = 1.12 MΩ to limit IC to approximately 0.5 mA. The corresponding variations in the BJT bias point are also shown in Table B.7.
Accordingly, we see that emitter degeneration makes the bias point of the CE amplifier much less sensi-tive to changes in β. However, unless a large bypass capacitor CE is used, this reduced bias sensitivity comes at the expense of a reduction in the midband gain (as we observed in this example when we simu-lated the frequency response of the CE amplifier with an ).
9No detailed knowledge of frequency-response calculations is required for this example; all that is needed is Sec-tion 4.8.6. Nevertheless, after the study of the frequency of the CE amplifier in Sections 8.1 through 8.3, the read-er will benefit by returning to this example to experiment further with the circuit using PSpice.
10The reader should not be alarmed about the use of such a large signal amplitude. Recall that in a small-signal (ac) simulation, SPICE first finds the small-signal equivalent circuit at the dc bias point and then analyzes this linear circuit. Such ac analysis can, of course, be done with any ac signal amplitude. However, an I–V ac input is convenient to use because the resulting ac output corresponds to the voltage gain of the circuit.
AM 1 Re re -----+ Rsig rπ --------+ 1 Rsig rπ --------+ ------------------------------Re re Rsig βac 1 + ----------------+ = Rce Re 130 Ω = Rin 6.1 kΩ 20.9 kΩ AM 340 kΩ Rce of 130 Ω RE 6 kΩ = RE = 0 Re = 130 Ω B-30 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The CMOS CS Amplifier In this example, we will use PSpice to compute the dc transfer characteristic of the CS amplifier whose capture schematic is shown in Fig. B.23. We will assume a 5-μm CMOS technology for the MOSFETs and use parts NMOS5P0 and PMOS5P0 whose SPICE level-1 parameters are listed in Table B.3. To specify the dimensions of the MOSFETs in PSpice, we will use the multiplicative factor m together with the channel length L and the channel width W. The MOSFET parameter m, whose default value is 1, is used in SPICE to specify the number of MOSFETs connected in parallel. As depicted in Fig. B.24, a wide transistor with channel length L and channel width m × W can be implemented using m narrower transistors in parallel, each having a channel length L and a channel width W. Thus, neglecting the channel-length modulation effect, the drain current of a MOSFET operating in the saturation region can be expressed as Figure B.22 Frequency response of the CE amplifier in Example PS.6.2 with and .
Rce = 0 Rce =130 Ω Frequency (Hz) 1.0 10 100 1.0 K 10 K 100 K 1.0 M 10 M 0 5 10 15 20 25 30 35 dB (V(OUT)) fL 131.1 Hz AM 31.7 dB Rce 0 fH 287.1 kHz Rce 130 AM 25.6 dB fH 145.8 kHz fL 62.9 Hz Table B.7 Variations in the Bias Point of the CE Amplifier with the SPICE Model-Parameter BF of BJT BF (in SPICE) RE = 6 k RE = 0 IC (mA) VC (V) IC (mA) VC (V) 208 106 94.9 0.452 0.484 109 96.9 0.377 1.227 416.4 (nominal value) 143 123 0.494 0.062 148 127 0.494 0.060 832 173 144 0.518 −0.183 181 151 0.588 −0.878 βac βdc βac βdc Example PS.7.1 Example PS.6.2 continued B.2 PSpice Examples B-31 (B.24) where Leff rather than L is used to more accurately estimate the drain current.
The CS amplifier in Fig. B.23 is designed for a bias current of 100 μA assuming a reference current Iref = 100 μA and VDD = 10 V. The current mirror transistors M2 and M3 are sized for VOV2 = VOV3 = 1 V, Figure B.23 Schematic capture of the CS amplifier in Example PS.7.1.
Figure B.24 Transistor equivalency.
0 PARAMETERS: Iref 100u M 2 M1 10 VDD VDD M {M} W 37.5u L 6u M {M} W 37.5u L 6u M {M1} W 12.5u L 6u VDD DC {VDD} 0 0 OUT IN 0 M3 M2 {Iref} 1.5Vdc VIN M1 VDD 10 iD D S G Aspect ratio mW L Aspect ratio of each MOSFET W L iD Q1 Q2 Qm D S iD m iD m iD m ID 1 2 ---μCoxm W Leff --------VOV 2 = B-32 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim while the input transistor M1 is sized for VOV1 = 0.5 V. Note that a smaller overdrive voltage is selected for M1 to achieve a larger voltage gain Gv for the CS amplifier, since (B.25) where VAn and VAp are the magnitudes of the Early voltages of, respectively, the NMOS and PMOS tran-sistors. Unit-size transistors are used with = 12.5 μm for the NMOS devices and = 37.5 μm for the PMOS devices. Thus, using Eq. (B.24) together with the 5-μm CMOS process parameters in Table B.4, we find m1 = 10 and m2 = m3 = 2 (rounded to the nearest integer).
Furthermore, Eq. (B.25) gives Gv = −100 V/V.
To compute the dc transfer characteristic of the CS amplifier, we perform a dc analysis in PSpice with VIN swept over the range 0 to VDD and plot the corresponding output voltage Figure B.25 (a) shows the resulting transfer characteristic. The slope of this characteristic (i.e., ) corresponds to the gain of the amplifier. The high-gain segment is clearly visible for VIN around 1.5 V. This corresponds to an overdrive voltage for M1 of 0.5 V, as desired. To examine the high-gain region more closely, we repeat the dc sweep for VIN between 1.3 V and 1.7 V. The resulting transfer characteristic is plotted in Fig. B.25 (b, middle curve). Using the Probe graphical interface of PSpice, we find that the lin-ear region of this dc transfer characteristic is bounded approximately by VIN = 1.465 V and VIN = 1.539 V.
The corresponding values of are 8.838 V and 0.573 V. These results are close to the expected val-ues. Specifically, transistors M1 and M2 will remain in the saturation region and, hence, the amplifier will operate in its linear region if VOV1 ≤ VOUT ≤ VDD − VOV2 or 0.5 V ≤ VOUT ≤ 9 V. From the results above, the volt-age gain Gv (i.e., the slope of the linear segment of the dc transfer characteristic) is approximately , which is reasonably close to the value obtained by hand ianalysis. Gv gm1RL ′ = gm1 ro1 ro2 || ( ) 2 V OV1 -----------V AnV Ap V An V Ap + -----------------------⎝ ⎠ ⎛ ⎞ – = – – = W L ⁄ μm 6 ⁄ W L ⁄ μm 6 ⁄ VOUT.
dVOUT dVIN ⁄ V OV1 = VIN V tn = – VOUT 112 V/V – V_VIN (a) 0V 2V 4V 6V 8V 10V V(OUT) 0V 2V 4V 6V 8V 10V Figure B.25 (a) Voltage transfer characteristic of the CS amplifier in Example PS.7.1. (b) Expanded view of the transfer characteristic in the high-gain region. Also shown are the transfer characteristics where process variations cause the width of transistor M1 to change by +15% and −15% from its nominal value of W1 = 12.5 μm. Example PS.7.1 continued B.2 PSpice Examples B-33 Note from the dc transfer characteristic in Fig. B.25(b) that for an input dc bias of VIN = 1.5 V, the output dc bias is VOUT = 4.88 V. This choice of VIN maximizes the available signal swing at the output by setting VOUT at the middle of the linear segment of the dc transfer characteristic. However, because of the high resistance at the output node (or, equivalently, because of the high voltage gain), this value of VOUT is highly sensitive to the effect of process and temperature variations on the characteristics of the transistors.
To illustrate this point, consider what happens when the width of M1 (i.e., W1, which is normally 12.5 μm) changes by ±15%. The corresponding dc transfer characteristics are shown in Fig. B.25(b). Accordingly, when VIN = 1.5 V, VOUT will drop to 0.84 V if W1 increases by 15% and will rise to 9.0 V if W1 decreases by 15%. In practical circuit implementations, this problem is circumvented by using negative feedback to accurately set the dc bias voltage at the output of the amplifier and, hence, to reduce the sensitivity of the circuit to process variations. We studied negative feedback in Chapter 9.
A Multistage Differential BJT Amplifier The schematic capture of the multistage op-amp circuit analyzed in Examples 7.1 and 7.7 is shown in Fig.
B.26.11 Observe the manner in which the differential signal input Vd and the common-mode input voltage VCM are applied. Such an input bias configuration for an op-amp circuit was presented and used in Exam-ple PS.2.2. In the following simulations, we will use parts Q2N3904 and Q2N3906 (from Fairchild 11This circuit cannot be simulated using the student evaluation version of PSpice. This is because, in this free version of PSpice, circuit simulation is restricted to circuits with no more than 10 transistors. V(OUT) V_VIN 1.30V 1.35V 1.40V 1.45V 1.50V 1.55V 1.60V 1.65V 1.70V 0V 2V 4V 6V 8V 10V (b) (1.5V, 0.836V) for W1 12.5u 15% (1.5V, 4.88V) for W1 12.5u (1.5V, 9.0V) for W1 12.5u 15% Figure 8.25 continued Example PS.8.1 B-34 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Semiconductor) for the npn and pnp BJTs, respectively. The model parameters of these discrete BJTs are listed in Table B.8 and are available in PSpice. In PSpice, the common-mode input voltage VCM of the op-amp circuit is set to 0 V (i.e., to the average of the dc power-supply voltages VCC and VEE) to maximize the available input signal swing. A bias-point simulation is performed to determine the dc operating point. Table B.9 summarizes the value of the dc collector currents as computed by PSpice and as calculated by the hand analysis in Example 7.6. Recall that our hand analysis assumed both and the Early voltage VA of the BJTs to be infinite. However, our SPICE simulations in Example PS.6.1 (where we investigated the dependence of on the collector cur-rent ) indicate that the Q2N3904 has at . Furthermore, its forward Early volt-age (SPICE parameter VAF) is 74 V, as given in Table B.8. Nevertheless, we observe from Table B.9 that the largest error in the calculation of the dc bias currents is on the order of 20%. Accordingly, we can conclude that a quick hand analysis using gross approximations can still yield reasonable results for a pre-liminary estimate and, of course, hand analysis yields much insight into the circuit operation. In addition to the dc bias currents listed in Table B.9, the bias-point simulation in PSpice shows that the output dc offset (i.e., VOUT when Vd ) is 3.62 V and that the input bias current is 2.88 μA. Table B.8 Spice Model Parameters of the Q2N3904 and Q2N3906 Discrete BJTs Q2N3904 Discrete BJT IS = 6.734f XTI = 3 EG = 1.11 VAF = 74.03 BF = 416.4 NE = 1.259 ISE = 6.734f IKF = 66.78m XTB = 1.5 BR = .7371 NC = 2 ISC = 0 IKR = 0 RC = 1 CJC = 3.638p MJC = .3085 VJC = .75 FC = .5 CJE = 4.493p MJE = .2593 VJE = .75 TR = 239.5n TF = 301.2p ITF = .4 VTF = 4 XTF = 2 RB = 10 Q2N3906 Discrete BJT IS = 1.41f XTI = 3 EG = 1.11 VAF = 18.7 BF = 180.7 NE = 1.5 ISE = 0 IKF = 80m XTB = 1.5 BR = 4.977 NC = 2 ISC = 0 IKR = 0 RC = 2.5 CJC = 9.728p MJC = .5776 VJC = .75 FC = .5 CJE = 8.063p MJE = .3677 VJE = .75 TR = 33.42n TF = 179.3p ITF = .4 VTF = 4 XTF = 6 RB = 10 Table B.9 DC Collector Currents of the Op-Amp Circuit in Fig. B.26 as Computed by Hand Analysis (Example 8.6) and by PSpice Collector Currents (mA) Transistor Hand Analysis (Example 8.6) PSpice Error (%) Q1 0.25 0.281 −11.0 Q2 0.25 0.281 −11.0 Q3 0.5 0.567 −11.8 Q4 1.0 1.27 −21.3 Q5 1.0 1.21 −17.4 Q6 2.0 2.50 −20.0 Q7 1.0 1.27 −21.3 Q8 5.0 6.17 −18.9 Q9 0.5 0.48 +4.2 β β IC β 125 IC 0.25 mA = = 0 IB1 Example PS.8.1 continued B.2 PSpice Examples B-35 To compute the large-signal differential transfer characteristic of the op-amp circuit, we perform a dc-analysis simulation in PSpice with the differential voltage input Vd swept over the range −VEE to +VCC, and we plot the corresponding output voltage VOUT. Figure B.27(a) shows the resulting dc transfer charac-teristic. The slope of this characteristic (i.e., ) corresponds to the differential gain of the amplifier. Note that, as expected, the high-gain region is in the vicinity of . However, the reso-lution of the input-voltage axis is too coarse to yield much information about the details of the high-gain region. Therefore, to examine this region more closely, the dc analysis is repeated with Vd swept over the range to at increments of 10 μV. The resulting differential dc transfer characteristic is plot-ted in Fig. B.27(b). We observe that the linear region of the large-signal differential characteristic is bounded approximately by and . Over this region, the output level changes from to about in a linear fashion. Thus, the output voltage swing for this amplifier is between and , a rather asymmetrical range. A rough estimate for the differential gain of this amplifier can be obtained from the boundaries of the linear region as . We also observe from Fig B.27(b) that μV when . Therefore, the amplifier has an input offset voltage VOS of +260 μV (by convention, the negative value of the x-axis intercept of the large-signal differential transfer character-istic). This corresponds to an output offset voltage of (260 μV) = 3.25 V, which is Figure B.26 Schematic capture of the op-amp circuit in Example 6.6.
Q2 INN INN INP d {VCM} {VCC} {VEE} GAIN 0.5 0 {RB} R1 20K R2 20K R3 3K R4 2.3K R5 15.7K R6 3K RB 28.6K VCC 15 VCM 0 VEE 15 PARAMETERS: 1Vac 0Vdc Vd 0 d {R3} VCC {R4} VCC {R6} OUT VEE VCC VCC {R2} VCC {R1} VCC Q5 Q4 Q7 Q8 {R5} VEE Q1 0 0 Q6D VEE Q6C VEE Q6B VEE Q6A VEE Q3 VEE VEE Q9 VEE 0 VCC 0 En INP d GAIN 0.5 0 Ep dVOUT dVd ⁄ Vd = 0 V 5 mV – +5 mV Vd = −1.5 mV Vd = +0.5 mV VOUT = −15 V VOUT = +10 V −15 V +10 V Ad = 10 15 – ( ) – [ ] V 0.5 1.5 – ( ) – [ ] ⁄ mV = 12.5 103 × V/V Vd −260 VOUT = 0 AdVOS 12.5 103 × ( ) B-36 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.27 (a) The large-signal differential transfer characteristic of the op-amp circuit in Fig. B.26. The com-mon-mode input voltage VCM is set to 0 V. (b) An expanded view of the transfer characteristic in the high-gain region.
10 15 5 5 0 10 15 20 V 10 V 0 V 10 V 20 V V_Vd (V) (a) V (OUT) 4.0 5.0 2.0 2.0 0 4.0 5.0 20 V 10 V 0 V 10 V 20 V V_Vd (mV) (b) V (OUT) Max. Output Voltage Swing Example PS.8.1 continued B.2 PSpice Examples B-37 close to the value found through the bias-point simulation. It should be emphasized that this offset volt-age is inherent in the design and is not the result of component or device mismatches. Thus, it is usually referred to as a systematic offset.
Next, to compute the frequency response of the op-amp circuit12 and to measure its differential gain Ad and its 3-dB frequency fH in PSpice, we set the differential input voltage Vd to be a 1-V ac signal (with 0-V dc level), perform an ac-analysis simulation, and plot the output voltage magnitude versus fre-quency. Figure B.28(a) shows the resulting frequency response. Accordingly, V/V or 82.8 dB, and kHz. Thus, this value of Ad is close to the value estimated using the large-signal differential transfer characteristic. An approximate value of fH can also be obtained using the expressions derived in Section 8.8. Specifi-cally, (B.26) where and The values of the small-signal parameters as computed by PSpice can be found in the output file of a bias-point (or an ac-analysis) simulation. Using these values results in pF, kΩ, and kHz. However, this approximate value of fH is much smaller than the value computed by PSpice. The reason for this disagreement is that the foregoing expression for fH was derived (in Section 8.8) using the equivalent differential half-circuit concept. However, the concept is accurate only when it is applied to a symmetrical circuit. The op-amp circuit in Fig. B.26 is not symmetrical because the sec-ond gain stage formed by the differential pair Q4–Q5 has a load resistor in the collector of only.
To verify that the expression for fH in Eq. (B.26) gives a close approximation for fH in the case of a sym-metric circuit, we insert a resistor (whose size is equal to ) in the collector of . Note that this will have only a minor effect on the dc operating point. The op-amp circuit with having a collector resistor is then simulated in PSpice. Figure B.28(b) shows the resulting frequency response of this symmetric op amp, where kHz. Accordingly, in the case of a perfectly symmetric op-amp cir-cuit, the value of fH in Eq. (B.26) closely approximates the value computed by PSpice. Comparing the fre-quency responses of the nonsymmetric (Fig. B.28a) and the symmetric (Fig. B.28b) op-amp circuits, we note that the 3-dB frequency of the op amp drops from 256.9 kHz to 155.7 kHz when resistor is inserted in the collector of to make the op-amp circuit symmetrical. This is because, with a resistor the collector of is no longer at signal ground and, hence, experiences the Miller effect. Con-sequently, the high-frequency response of the op-amp circuit is degraded.
Observe that in the preceding ac-analysis simulation, owing to the systematic offset inherent in the design, the op-amp circuit is operating at an output dc voltage of 3.62 V. However, in an actual circuit implementation (with ), negative feedback is employed (see Chapters 2 and 9) and the output dc voltage is stabilized at zero. Thus, the small-signal performance of the op-amp circuit can be more accurately simulated by biasing the circuit so as to force operation at this level of output volt-age. This can be easily done by applying a differential dc input of −VOS. Superimposed on this dc 12This part of the example requires study of Sections 8.8 and 8.10.2.
VOUT Ad = 13.96 103 × fH = 256.9 fH 1 2πReqCeq -----------------------Ceq = Cμ2 Cπ5 Cμ5 1 gm5 R3 ro5 rπ7 β 1 + ( )R4 + ( ) || || ( ) + [ ] + + Req = R2 ro2 rπ5 || || Ceq = 338 Req = 2.91 fH = 161.7 R3 Q5 R3 ′ R3 Q4 Q4 R3 ′ fH = 155.7 R3 ′ Q4 R3 ′, Q4 Cμ4 VCM = 0 B-38 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.28 Frequency response of (a) the op-amp circuit in Fig. B.26 and (b) the op-amp circuit in Fig. B.26 but with a resistor = R3 inserted in the collector of Q4 to make the op-amp circuit symmetrical.
100 Frequency (Hz) (a) 1.0 dB (V (OUT)) 10 100 1.0 K 10 K 100 K 1.0 M 10 M 100 M 1.0 G Ad 82.8 dB fH 256.9 kHz 80 60 40 20 0 100 Frequency (Hz) (b) 1.0 dB (V (OUT)) 10 100 1.0 K 10 K 100 K 1.0 M 10 M 100 M 1.0 G Ad 82.5 dB fH 155.7 kHz 80 60 40 20 0 R3 ′ Example PS.8.1 continued B.2 PSpice Examples B-39 input, we can apply an ac signal to perform an ac-analysis simulation for the purpose of, for example, computing the differential gain and the 3-dB frequency. Finally, to compute the input common-mode range of the op-amp circuit in Fig. B.26, we perform a dc-analysis simulation in PSpice with the input common-mode voltage swept over the range −VEE to VCC, while maintaining Vd constant at −VOS in order to cancel the output offset voltage (as discussed earlier) and, thus, prevent premature saturation of the BJTs. The corresponding output voltage VOUT is plotted in Fig. B.29(a). From this common-mode dc transfer characteristic we find that the amplifier behaves lin-early over the VCM range −14.1 V to +8.9 V, which is therefore the input common-mode range. In Example 7.6, we noted that the upper limit of this range is determined by and saturating, whereas the lower limit is determined by saturating. To verify this assertion, we requested PSpice to plot the values of the collector–base voltages of these BJTs versus the input common-mode voltage VCM.
The results are shown in Fig. B.29(b), from which we note that our assertion is indeed correct (recall that an npn BJT enters its saturation region when its base–collector junction becomes forward biased, i.e., ).
Q1 Q2 Q3 VBC 0 ≥ Figure B.29 (a) The large-signal common-mode transfer characteristic of the op-amp circuit in Fig. B.26. The dif-ferential input voltage Vd is set to –VOS = –260 μV to prevent premature saturation. (b) The effect of the common-mode input voltage VCM on the linearity of the input stage of the op-amp circuit in Fig. B.26. The base–collector voltage of Q1 and Q3 is shown as a function of VCM. The input stage of the op-amp circuit leaves the active region when the base–collector junction of either Q1 or Q3 becomes forward biased (i.e., when ).
VBC 0 ≥ 10 15 5 5 0 10 15 5 V 0 V 5 V 10 V 15 V V_VCM (V) (a) V (OUT) Input Common-Mode Range B-40 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Frequency Response of the CMOS CS and the Folded-Cascode Amplifiers In this example, we will use PSpice to compute the frequency response of both the CS and the folded-cas-code amplifiers whose schematic capture diagrams are shown shortly in Figs. B.30 and B.32, respec-tively. We will assume that the dc bias levels at the output of the amplifiers are stabilized using negative feedback. However, before performing a small-signal analysis (an ac-analysis simulation) in SPICE to measure the frequency response, we will perform a dc analysis (a bias-point simulation) to verify that all MOSFETs are operating in the saturation region and, hence, ensure that the amplifier is operating in its linear region. In the following, we will assume a 0.5-μm CMOS technology for the MOSFETs and use parts NMOSOP5 and PMOSOP5 whose SPICE level-1 model parameters are listed in Table B.3. To specify the dimensions of the MOSFETs in PSpice, we will use the multiplicative factor m, together with the channel length L and channel width W (as we did in Example PS.7.1). The CMOS CS Amplifier The CS amplifier circuit in Fig. B.30 is identical to the one shown in Fig. 6.4, except that a current source is connected to the source of the input transistor M1 to set its drain current ID1 independently of its drain volt-age VD1. Furthermore, in our PSpice simulations, we used an impractically large bypass capacitor CS of 1 F. This sets the source of M1 at approximately signal ground during the ac-analysis simulation. Accord-ingly, the CS amplifier circuits in Figs. 6.4 and B.30 are equivalent for the purpose of frequency-response Figure B.29 (Contd.).
10 15 5 5 0 10 15 10 V 0 V 10 V 20 V 30 V V_VCM (V) (b) V (Q3:B)–V (Q3:C) V (Q1:B)–V (Q1:C) VBC of Q3 VBC of Q1 Example PS.9.1 Example PS.8.1 continued B.2 PSpice Examples B-41 analysis. In Chapter 7, we found out, in the context of studying the differential pair, how the goals of this biasing approach for the CS amplifier are realized in practical IC implementations.
The CS amplifier in Fig. B.30 is designed assuming a reference current Iref = 100 μA and VDD = 3.3 V.
The current-mirror transistors, M2 and M3, are sized for VOV2 = VOV3 = 0.3 V, while the input transistor M1 is sized for VOV1 = 0.15 V. Unit-size transistors are used with = 1.25 0.6 μm for the NMOS devices and = 5 μm for the PMOS devices. Thus, using the square law ID – VOV of the MOSFET together with the 0.5-μm CMOS process parameters in Table B.4, we find m1 = 18 and m2 = m3 = 4.
Furthermore, Eq. (B.25) gives Gv = for the CS amplifier.
In the PSpice simulations of the CS amplifier in Fig. B.30, the dc bias voltage of the signal source is set such that the voltage at the source terminal of M1 is VS1 = 1.3 V. This requires the dc level of Vsig to be VOV1 + Vtn1 + VS1 = 2.45 V because V as a result of the body effect on M1. The reasoning behind this choice of VS1 is that, in a practical circuit implementation, the current source that feeds the source of M1 is realized using a cascode current mirror such as the one in Fig. 6.32. In this case, the minimum voltage required across the current source (i.e., the minimum VS1) is Vt + 2VOV = 1.3 V, assuming VOV = 0.3 V for the current-mirror transistors. A bias-point simulation is performed in PSpice to verify that all MOSFETs are biased in the satura-tion region. Next, to compute the frequency response of the amplifier, we set the ac voltage of the signal source to 1 V, perform an ac-analysis simulation, and plot the output voltage magnitude versus frequency.
Figure B.31(a) shows the resulting frequency response for Rsig = 100 Ω and Rsig = 1 MΩ. In both cases, a load capacitance of Cload = 0.5 pF is used. The corresponding values of the 3-dB frequency fH of the ampli-fier are given in Table B.10. Figure B.30 Schematic capture of the CS amplifier in Example PS.9.1 0 PARAMETERS: Cload 0.5p CS 1 Iref 100u M 4 M1 18 Rsig 100 VDD 3.3 VDD VDD M {M} W 5u L 0.6u M {M} W 5u L 0.6u M {M1} W 1.25u L 0.6u VDD DC {VDD} 0 0 OUT {Rsig} 0 0 M3 M2 {Iref} {Iref} {CS} 1Vac 2.45Vdc Vsig M1 IN 0 {Cload} W L ⁄ μm 0.6 ⁄ W L ⁄ μm 0.6 ⁄ 44.4 V/V – V tn1 1 B-42 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Observe that fH drops when Rsig is increased. This is anticipated from our study of the high-frequency response of the CS amplifier in Section 8.3. Specifically, as Rsig increases, the pole (B.27) formed at the amplifier input will have an increasingly significant effect on the overall frequency response of the amplifier. As a result, the effective time constant in Eq. (8.85) increases and fH decreases. When Rsig becomes very large, as it is when Rsig = 1 MΩ, a dominant pole is formed by Rsig and Cin. This results in (B.28) To estimate fp,in, we need to calculate the input capacitance Cin of the amplifier. Using Miller’s theorem, we have (B.29) Figure B.31 Frequency response of (a) the CS amplifier and (b) the folded-cascode amplifier in Example PS.9.1, with Rsig = 100 Ω and Rsig = 1 MΩ.
dB (V(OUT)) (a) (b) CS Amplifier CS Amplifier dB (V(OUT)) Frequency (Hz) 1.0 10 100 1.0 K 10 K 100 K 1.0 M 10 M 100 M 1.0 G 0 0 0 0 0 0 0 0 0 0 0 0 Gv 34.5 dB fH 7.49 MHz with Rsig 100 fH 293.2 kHz with Rsig 1 M fH 2.93 MHz with Rsig 100 fH 1.44 MHz with Rsig 1 M Gv 42.4 dB Cascode Amplifier Cascode Amplifier f p in , 1 2π ------1 RsigCin ----------------= τH fH fp in , Cin = Cgs1 Cgd1(1 gm1R′ L ) + + 2 3 ---m1W1L1Cox Cgs, ov1 + ( ) Cgd, ov1(1 gm1R′ L ) + + = Example PS.9.1 continued B.2 PSpice Examples B-43 where (B.30) Thus, Cin can be calculated using the values of Cgs1 and Cgd1, which are computed by PSpice and can be found in the output file of the bias-point simulation. Alternatively, Cin can be found using Eq. (B.29) with the values of the overlap capacitances Cgs, ov1 and Cgd, ov1 calculated using the process parameters in Table B.4 (as described in Eqs. B.9 and B.10); that is: (B.31) (B.32) This results in Cin = 0.53 pF when . Accordingly, using Eqs. (B.27) and (B.28), fH = 300.3 kHz when Rsig = 1 MΩ, which is close to the value computed by PSpice.
The Folded-Cascode Amplifier The folded-cascode amplifier circuit in Fig. B.32 is equivalent to the one in Fig. 6.16, except that a current source is placed in the source of the input transistor M1 (for the same dc-biasing purpose as in the case of the CS amplifier). Note that, in Fig. B.32, the PMOS current mirror M3−M4 and the NMOS current mirror M5−M6 are used to realize, respectively, current sources I1 and I2 in the circuit of Fig. 6.16. Furthermore, the current transfer ratio of mirror M3−M4 is set to 2 (i.e., ). This results in .
Hence, transistor M2 is biased at ID2 = ID3 − ID1 = Iref. The gate bias voltage of transistor M2 is generated using the diode-connected transistors M7 and M8. The size and drain current of these transistors are set equal to those of transistor M2. Therefore, ignoring the body effect, where VOVp is the overdrive voltage of the PMOS transistors in the amplifier circuit. These transistors have the same overdrive voltage because their is the same. Thus, such a biasing configuration results in as desired, while setting to improve the bias matching between M3 and M4.
The folded-cascode amplifier in Fig. B.32 is designed assuming a reference current Iref = 100 μA and VDD = 3.3 V (similar to the case of the CS amplifier). All transistors are sized for an overdrive voltage of 0.3 V, except for the input transistor M1, which is sized for VOV1 = 0.15 V. Thus, since , all the MOSFETs in the amplifier circuit are designed using m = 4, except for m1 = 18.
The midband voltage gain of the folded-cascode amplifier in Fig. B.32 can be expressed as (B.33) where (B.34) Table B.10 Dependence of the 3-dB Bandwidth fH on Rsig for the CS and the Folded-Cascode Amplifiers in Example PS.9.1 Rsig fH CS Amplifier Folded-Cascode Amplifier 100 Ω 7.49 MHz 2.93 MHz 1 MΩ 293.2 kHz 1.44 MHz RL ′ ro1 ro2 || = Cgs, ov1 m1W1CGSO = Cgd, ov1 m1W1CGDO = Gv gm1RL ′ = 53.2 V/V = m3 m4 2 = ⁄ ID3 2Iref VG2 = V DD VSG7 – V SG8 V DD 2( Vtp V OVp ) + – – ID m ⁄ VSG2 = Vtp V OVp + VSD3 = Vtp V OVp + ID = 1 2 --uCoxm W Leff ⁄ ( )V OV 2 Gv gm1Rout – = Rout Rout2 Rout5 || = B-44 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim 0 PARAMETERS: Cload 0.5p CS 1 Iref 100u M 4 M1 18 Rsig 100 VDD 3.3 VDD VDD VDD VDD M {M} W 5u L 0.6u M {2{M} } W 5u L 0.6u M {M1} W 1.25u L 0.6u M {M} W 1.25u L 0.6u M {M} W 1.25u L 0.6u M {M} W 5u L 0.6u M {M} W 5u L 0.6u M {M} W 5u L 0.6u VDD DC {VDD} 0 0 D {Rsig} 0 0 0 M4 M3 {Iref} {Iref} 0 {Iref} {Iref} {CS} 1Vac 2.45Vdc Vsig M1 M7 M2 M8 M6 M5 IN 0 0 {Cload} OUT Figure B.32 Schematic capture of the of folded cascode amplifier in Example PS.9.1.
Example PS.9.1 continued B.2 PSpice Examples B-45 is the output resistance of the amplifier. Here, Rout2 is the resistance seen looking into the drain of the cas-code transistor M2, while Rout5 is the resistance seen looking into the drain of the current-mirror transistor M5. Using Eq. (6.25), we have (B.35) where (B.36) is the effective resistance at the source of M2. Furthermore, (B.37) Thus, for the folded-cascoded amplifier in Fig. B.32, (B.38) and (B.39) Using the 0.5-μm CMOS parameters, this gives Rout = 100 kΩ and . Therefore, Rout and hence of the folded-cascode amplifier in Fig. B.32 are larger than those of the CS amplifier in Fig.
B.30 by a factor of 3.
Figure B.31(b) shows the frequency response of the folded-cascode amplifier as computed by PSpice for the cases of Rsig = 100 Ω and Rsig = 1 MΩ. The corresponding values of the 3-dB frequency fH of the amplifier are given in Table B.10. Observe that when Rsig is small, fH of the folded-cascode amplifier is lower than that of the CS amplifier by a factor of approximately 2.6, approximately equal to the factor by which the gain is increased. This is because when Rsig is small, the frequency response of both amplifiers is dominated by the pole formed at the output node, that is, (B.40) Since the output resistance of the folded-cascode amplifier is larger than that of the CS amplifier (by a factor of approximately 3, as found through the hand analysis above) while their output capacitances are approximately equal, the folded-cascode amplifier has a lower fH in this case.
On the other hand, when Rsig is large, fH of the folded-cascode amplifier is much higher than that of the CS amplifier. This is because, in this case, the effect of the pole at fp, in on the overall frequency response of the amplifier becomes significant. Since, due to the Miller effect, Cin of the CS amplifier is much larger than that of the folded-cascode amplifier, its fH is much lower in this case. To confirm this point, observe that Cin of the folded-cascode amplifier can be estimated by replacing in Eq. (B.29) with the total resis-tance Rd1 between the drain of M1 and ground. Here, (B.41) where Rin2 is the input resistance of the common-gate transistor M2 and can be obtained using an approxi-mation of the relationship in Eq. (6.34) as (B.42) Thus, (B.43) Rout2 gm2ro2 ( )Rs2 Rs2 ro1 ro3 || = Rout5 ro5 = Rout ro5 Gv gm1ro5 2 V An V OV1 -----------– = – Gv 133 V/V – = Gv f H f p out , = 1 2π ------1 RoutCout ------------------R′ L Rd1 ro1 ro3 Rin2 || || = Rin2 ro2 ro5 + gm2ro2 --------------------Rd1 ro1 ro3 ro2 ro5 + gm2ro2 -------------------- 2 gm2 --------⎝ ⎠ ⎛ ⎞ B-46 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Therefore, Rd1 is much smaller than in Eq. (B.30). Hence, Cin of the folded-cascode amplifier in Fig. B.32 is indeed much smaller than that of the CS amplifier in Fig. B.30. This confirms that the folded-cascode amplifier is much less impacted by the Miller effect and, therefore, can achieve a much higher fH when Rsig is large. The midband gain of the folded-cascode amplifier can be significantly increased by replacing the cur-rent mirror M5−M6 with a current mirror having a larger output resistance, such as the cascode current mirror in Fig. 6.32 whose output resistance is approximately . In this case, however, Rin2 and hence Rd1 increase, causing an increased Miller effect and a corresponding reduction in fH.
Finally, it is interesting to observe that the frequency response of the folded-cascode amplifier, shown in Fig. B.31(b), drops beyond fH at approximately –20 dB/decade when Rsig = 100 Ω and at approximately dB/decade when Rsig = 1 MΩ. This is because when Rsig is small, the frequency response is dominated by the pole at fp,out. However, when Rsig is increased, fp,in is moved closer to fp, out and both poles contribute to the gain falloff.
Determining the Loop Gain of a Feedback Amplifier This example illustrates the use of SPICE to compute the loop gain Aβ. For this purpose, we shall use the shunt–series feedbck amplifier shown in Fig. B.33 (see also Problem 9.101).
To compute the loop gain, we set the input signal VS to zero, and we choose to break the feedback loop between the collector of Q1 and the base of Q2. However, in breaking the feedback loop, we must ensure that the following two conditions that existed prior to breaking the feedback loop do not change: (1) the dc bias situation and (2) the ac signal termination.
Figure B.33 Circuit of the shunt–series feedback amplifier in Example PS.10.1.
R L ′ gmro 2 40 – Example PS.10.1 Q2 Cf CC2 RL RC2 8 k 1 k VCC 12 V RE2 3.4 k Q1 RC1 10 k VCC 12 V RE1 870 Rs 10 k CC1 RB1 100 k RB2 15 k CE1 Vs Rf 10 k Example PS.9.1 continued B.2 PSpice Examples B-47 To break the feedback loop without disturbing the dc bias conditions of the circuit, we insert a large inductor Lbreak, as shown in Fig. B.34(a). Using a value of, say, Lbreak = 1 GH will ensure that the loop is opened for ac signals while keeping dc bias conditions unchanged.
To break the feedback loop without disturbing the signal termination conditions, we must load the loop output at the collector of Q1 with a termination impedance Zt whose value is equal to the impedance seen looking into the loop input at the base of Q2. Furthermore, to avoid disturbing the dc bias conditions, Zt must be connected to the collector of Q1 via a large coupling capacitor. However, it is not always easy to determine the value of the termination impedance Zt. So, we will describe two simulation methods to compute the loop gain without explicitly determining ZT.
Method 1 Using the open-circuit and short-circuit transfer functions As described in Section 9.9, the loop gain can be expressed as where Toc is the open-circuit voltage transfer function and Tsc is the short-circuit voltage transfer function.
The circuit for determining Toc is shown in Fig. B.34(b). Here, an ac test signal voltage Vt is applied to the loop input at the base of Q2 via a large coupling capacitor (having a value of, say, 1 kF) to avoid dis-turbing the dc bias conditions. Then, where Voc is the ac open-circuit output voltage at the collector of Q1.
In the circuit for determining Tsc (Fig. B.34), an ac test signal current It is applied to the loop input at the base of Q2. Note that a coupling capacitor is not needed in this case because the ac current source appears as an open circuit at dc, and, hence, does not disturb the dc bias conditions.
The loop output at the collector of Q1 is ac short-circuited to ground via a large capacitor Cto. Then, where Isc is the ac short-circuit output current at the collector of Q1.
Method 2 Using a replica circuit As shown in Fig. B.35, a replica of the feedback amplifier circuit can be simply used as a termination impedance. Here, the feedback loops of both the amplifier circuit and the replica circuit are broken using a large inductor Lbreak to avoid disturbing the dc bias conditions. The loop output at the collector of Q1 in the amplifier circuit is then connected to the loop input at the base of Q2 in the replica circuit via a large coupling capacitor Cto (again, to avoid disturbing the dc bias conditions). Thus, for ac signals, the loop output at the collector of Q1 in the amplifier circuit sees an impedance equal to that seen before the feed-back loop is broken. Accordingly, we have ensured that the conditions that existed in the amplifier circuit prior to breaking the loop have not changed.
Next, to determine the loop gain Aβ, we apply an ac test signal voltage Vt via a large coupling capaci-tor Cti to the loop input at the base of Q2 in the amplifier circuit. Then, as described in Section 9.9, where Vr is the ac returned signal at the loop output at the collector of Q1 in the amplifier circuit.
Aβ 1 – 1 Toc -------1 Tsc ------+ ⎝ ⎠ ⎛ ⎞ = Toc = V oc V t -------Tsc = Isc It -----Aβ Vr Vt -----– = B-48 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.34 Circuits for simulating (a) the open-circuit voltage transfer function Toc and (b) the short-circuit current transfer function Tsc of the feedback amplifier in Fig. B.33 for the purpose of computing its loop gain.
(a) Q2 Cf CC2 RL RC2 VCC Rf RE2 Q1 RC1 VCC RE1 Rs CC1 RB1 RB2 CE1 Cti Voc Lbreak Vt (b) Q2 Cf CC2 RL RC2 Rf RE2 Q1 RC1 VCC RE1 Rs CC1 RB1 RB2 CE1 Isc Cto It Lbreak VCC Example PS.10.1 continued B.2 PSpice Examples B-49 To compute the loop gain Aβ of the feedback amplifier circuit in Fig. B.33 using PSpice, we choose to simulate the circuit in Fig. B.35. In the PSpice simulations, we used part Q2N3904 (whose SPICE model is given in Table B.6) for the BJTs, and we set Lbreak to be 1 GH and the coupling and bypass capac-itors to be 1 kF. The magnitude and phase of Aβ are plotted in Fig. B.36, from which we see that the feed-back amplifier has a gain margin of 53.7 dB and a phase margin of 88.7°. Figure B.35 Circuit for simulating the loop gain of the feedback amplifier circuit in Fig. B.33 using the replica-circuit method.
Q2 Cf CC2 RL RC2 VCC Rf RE2 Q1 RC1 VCC RE1 Rs CC1 RB1 RB2 CE1 Cti Vr Lbreak Q2 Cf CC2 RL RC2 VCC Rf RE2 Q1 RC1 VCC RE1 Rs CC1 RB1 RB2 CE1 Lbreak Cto Amplifier circuit Replica circuit Vt B-50 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Class B BJT Output Stage We investigate the operation of the class B output stage whose schematic capture is shown in Fig. B.37.
For the power transistors, we use the discrete BJTs MJE243 and MJE253 (from ON Semiconductor),13 which are rated for a maximum continuous collector current ICmax = 4 A and a maximum collector–emitter voltage of VCEmax = 100 V. To permit comparison with the hand analysis performed in Example 13.1, in the simulation, we use component and voltage values identical (or close) to those of the circuit designed in Example 13.1. Specifically, we use a load resistance of 8 Ω, an input sine-wave signal of 17.9-V peak and 1-kHz frequency, and 23-V power supplies. In PSpice, a transient-analysis simulation is performed over the interval 0 ms to 3 ms, and the waveforms of various node voltages and branch currents are plotted. In this example, Probe (the graphical interface of PSpice) is utilized to compute various power-dissipation values.
Some of the resulting waveforms are displayed in Fig. B.38. The upper and middle graphs show the load voltage and current, respectively. The peak voltage amplitude is 16.9 V, and the peak current ampli-tude is 2.1 A. If one looks carefully, one can observe that both exhibit crossover distortion. The bottom Figure B.36 (a) Magnitude and (b) phase of the loop gain Aβ of the feedback amplifier circuit in Fig. B.33.
13In PSpice, we have created BJT parts for these power transistors based on the values of the SPICE model pa-rameters available on the data sheets available from ON Semiconductor. Readers can find these parts (labeled QMJE243 and QMJE253) in the SEDRA.olb library, which is available on the CD accompanying this book.
60 40 20 0 20 dB (V (returned) /V (test)) 40 Frequency (Hz) 1.0 1.0 G 100 M 10 M 1.0 M 100 K 10 K 1.0 K 100 10 150d 120d 90d 60d 30d P (–V (returned) /V (test)) 0d 180d |AB|V 35.5 dB PM 88.7 GM 53.7 dB Example PS.11.1 Example PS.10.1 continued B.2 PSpice Examples B-51 graph displays the instantaneous and the average power dissipated in the load resistance as computed using Probe by multiplying the voltage and current values to obtain the instantaneous power, and taking a running average for the average load power PL. The transient behavior of the average load power, which eventually settles into a quasiconstant steady state of about 17.6 W, is an artifact of the PSpice algorithm used to compute the running average of a waveform.
The upper two graphs of Fig. B.39 show the voltage and current waveforms, respectively, of the pos-itive supply, +VCC. The bottom graph shows the instantaneous and average power supplied by +VCC.
Figure B.37 Capture schematic of the class B output stage in Example PS.11.1.
Figure B.38 Several waveforms associated with the class B output stage (shown in Fig. B.37) when excited by a 17.9-V, 1-kHz sinusoidal signal. The upper graph displays the voltage across the load resistance, the middle graph dis-plays the load current, and the lower graph displays the instantaneous and average power dissipated by the load.
VCC VCC {RL} QMJE253 OUT IN Vin 0 0 QMJE243 QN QP VCC 0 VOFF 0 VAMPL 17.9 FREQ 1K {VCC} VCC {VCC} RL 8 VCC 23 PARAMETERS: 20 V 0 V 20 V 0 0.5 1.0 1.5 Time (ms) 2.0 2.5 3.0 4.0 A 0 A 4.0 A 0 W 20 W 40 W AVG (I (RL) V (OUT)) V (OUT) I (RL) I (RL) V (OUT) B-52 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Similar waveforms can be plotted for the negative supply, −VCC. The average power provided by each supply is found to be about 15 W, for a total supply power PS of 30 W. Thus, the power-conversion effi-ciency can be computed to be Figure B.40 shows plots of the voltage, current, and power waveforms associated with transistor QP.
Similar waveforms can be obtained for QN. As expected, the voltage waveform is a sinusoid, and the cur-rent waveform consists of half-sinusoids. The waveform of the instantaneous power, however, is rather unusual. It indicates the presence of some distortion as a result of driving the transistors rather hard. This can be verified by reducing the amplitude of the input signal. Specifically, when the amplitude is reduced to about 17 V, the “dip” in the power waveform vanishes. The average power dissipated in each of QN and QP can be computed by Probe and are found to be approximately 6 W.
Table B.11 provides a comparison of the results found from the PSpice simulation and the corresponding values obtained using hand analysis in Example 13.1. Observe that the two sets of results are quite close.
To investigate the crossover distortion further, we present in Fig. B.41 a plot of the voltage transfer characteristic (VTC) of the class B output stage. This plot is obtained through a dc-analysis simulation with vIN swept over the range −10 V to +10 V in 1.0-mV increments. Using Probe, we determine that the slope of the VTC is nearly unity and that the dead band extends from −0.60 V to +0.58 V. The effect of the crossover distortion can be quantified by performing a Fourier analysis on the output voltage wave-form in PSpice. This analysis decomposes the waveform generated through a transient analysis into its Figure B.39 The voltage (upper graph), current (middle graph), and instantaneous and average power (bottom graph) supplied by the positive voltage supply (+VCC) in the circuit of Fig. B.37.
0 V 20 V 40 V 0 0.5 1.0 1.5 Time (ms) 2.0 2.5 3.0 0 A 2.0 A 4.0 A 0 W 25 W 50 W AVG (I (VCC) V (VCC)) V (VCC) I (VCC) I (VCC) V (VCC) η PL PS ⁄ 17.6 30 ----------100% × 58.6% = = = Example PS.11.1 continued B.2 PSpice Examples B-53 Fourier-series components. Further, PSpice computes the total harmonic distortion (THD) of the output waveform. The results obtained from the simulation output file are shown on the next page. These Fourier components are used to plot the line spectrum shown in Fig. B.42. We note that the out-put waveform is rather rich in odd harmonics and that the resulting THD is rather high (2.14%).
Figure B.40 Waveforms of the voltage across, the current through, and the power dissipated in the pnp transistor QP of the output stage shown in Fig. B.37.
Table B.11 Various Power Terms Associated with the Class B Output Stage Shown in Fig. B.37 as Computed by Hand and by PSpice Analysis Power/Efficiency Equation Hand Analysis (Example PS.11.1) PSpice Error %1 PS 31.2 W 30.0 W 4 PD 13.0 W 12.4 W 4.6 PL 18.2 W 17.6 W 3.3 η 58.3% 58.6% −0.5 1Relative percentage error between the values predicted by hand and by PSpice.
40 V 20 V 0 V 0 0.5 1.0 1.5 Time (ms) 2.0 2.5 3.0 4.0 A 2.0 A 0 A 0 W 10 W 20 W AVG (IC (QP) (V (QP:C) V (QP:E))) V (QP:C) V (QP:E) IC (QP) IC (QP) (V (QP:C) V (QP:E)) 2 π ---V ˆo RL ------VCC 2 π ---V ˆo RL ------VCC 1 2 ---V ˆ 2 o RL --------– 1 2 ---V ˆ 2 o RL --------PL PS ------100% × B-54 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.41 Transfer characteristic of the class B output stage of Fig. B.37.
10 5 V (OUT) V_Vin (V) 0 5 10 10 V 5 V 0 V 5 V 10 V FOURIER COMPONENTS OF TRANSIENT RESPONSE V(OUT) HARMONIC NO 1 2 3 4 5 6 7 8 9 10 FREQUENCY (HZ) 1.000E+03 2.000E+03 3.000E+03 4.000E+03 5.000E+03 6.000E+03 7.000E+03 8.000E+03 9.000E+03 1.000E+04 NORMALIZED COMPONENT 1.000E+00 5.428E-04 1.641E-02 2.433E-04 1.039E-02 3.484E-05 7.140E-03 3.435E-05 5.429E-03 1.937E-05 NORMALIZED PHASE (DEG) 0.000E+00 9.044E+01 -1.799E+02 9.036E+01 -1.799E+02 9.161E+01 -1.799E+02 9.129E+01 -1.799E+02 9.122E+01 TOTAL HARMONIC DISTORTION = 2.140017E+00 PERCENT -2.292E-03 9.044E+01 -1.799E+02 9.035E+01 -1.799E+02 9.159E+01 -1.800E+02 9.128E+01 -1.800E+02 9.120E+01 PHASE (DEG) FOURIER COMPONENT 1.674E+01 9.088E-03 2.747E-01 4.074E-03 1.739E-01 5.833E-04 1.195E-01 5.750E-04 9.090E-02 3.243E-04 DC COMPONENT = -1.525229E-02 Example PS.11.1 continued B.2 PSpice Examples B-55 Frequency Compensation of the Two-Stage CMOS Op Amp In this example, we will use PSpice to aid in designing the frequency compensation of the two-stage CMOS circuit whose capture schematic is shown in Fig. B.43. PSpice will then be employed to determine the frequency response and the slew rate of the op amp. We will assume a 0.5-μm n-well CMOS technol-ogy for the MOSFETs and will use the SPICE level-1 model parameters listed in Table B.4. Observe that to eliminate the body effect and improve the matching between M1 and M2, the source terminals of the input PMOS transistors M1 and M2 are connected to their n well.
The op-amp circuit in Fig. B.43 is designed using a reference current IREF = 90 μA, a supply voltage V DD = 3.3 V, and a load capacitor CL = 1 pF. Unit-size transistors with are used for both the NMOS and PMOS devices. The transistors are sized for an overdrive voltage The cor-responding multiplicative factors are given in Fig. B.43.
In PSpice, the common-mode input voltage VCM of the op-amp circuit is set to = 1.65 V. A bias-point simulation is performed to determine the dc operating point. Using the values found in the simula-tion output file for the small-signal parameters of the MOSFETs, we obtain14 Figure B.42 Fourier-series components of the output waveform of the class B output stage in Fig. B.37.
14Recall that Gm1 and Gm2 are the transconductances of, respectively, the first and second stages of the op amp.
Capacitors C1 and C2 represent the total capacitance to ground at the output nodes of, respectively, the first and second stages of the op amp.
1 2 3 4 5 6 7 8 9 10 90 80 70 60 50 40 30 20 0 10 Frequency [kHz] Normalized Magnitude [dB] Example PS.12.1 W L ⁄ = 1.25 μm 0.6 μm ⁄ V OV 0.3 V. = V DD 2 ⁄ B-56 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim INN d {VCM} GAIN 0.5 1Vac 0Vdc Vd 0 d 0 0 INP INN En INP d GAIN 0.5 0 Ep {VDD} M {M3} W 1.25u L 0.6u M {M4} W 1.25u L 0.6u M {M6} W 1.25u L 0.6u M {M8} W 1.25u L 0.6u M {M1} W 1.25u L 0.6u {Cc} {R} {Cload} OUT M {M2} W 1.25u L 0.6u VDD M3 M1 M8 M5 M2 M4 A 0 VDD 0 0 {Iref} Iref 0 M6 0 0 VDD M7 VDD M {M5} W 1.25u L 0.6u M {M7} W 1.25u L 0.6u Cc 0.6p Cload 1p Iref 90u M1 8 M2 8 M3 2 M4 2 M5 16 M6 4 M7 16 M8 16 R 1.53K VCM 1.65 VDD 3.3 PARAMETERS: Figure B.43 Schematic capture of the two-stage CMOS op amp in Example PS.12.1 Example PS.12.1 continued B.2 PSpice Examples B-57 using Eqs. (10.7), (10.14), (10.25), and (10.26), respectively. Then, using Eq. (10.28), the frequency of the second, nondominant, pole can be found as In order to place the transmission zero, given by Eq. (10.38), at infinite frequency, we select Now, using Eq. (10.38), the phase margin of the op amp can be expressed as (B.44) where ft is the unity-gain frequency, given in Eq. (10.31), (B.45) Using Eqs. (B.44) and (B.45), we determine that compensation capacitors of CC = 0.78 pF and CC = 2 pF are required to achieve phase margins of PM = 55° and PM = 75°, respectively.
Next, an ac-analysis simulation is performed in PSpice to compute the frequency response of the op amp and to verify the foregoing design values. It was found that with R = 1.53 kΩ, we needed CC = 0.6 pF and CC = 1.8 pF to set PM = 55° and PM = 75°, respectively. We note that these values are reasonably close to those predicted by hand analysis. The corresponding frequency responses for the compensated op amp are plotted in Figs. B.44 and B.45. For comparison, we also show the frequency response of the uncompensated op amp (CC = 0). Observe that the unity gain frequency ft drops from 70.2 MHz to 26.4 MHz as CC is increased to improve PM (as anticipated from Eq. B.45).
Rather than increasing the compensation capacitor CC, the value of the series resistor R can be increased to improve the phase margin PM: For a given CC, increasing R above places the trans-mission zero at a negative real-axis location (Eq. 10.38), where the phase it introduces adds to the phase margin. Thus, PM can be improved without affecting f t. To verify this point, we set CC to 0.6 pF and sim-ulate the op-amp circuit in PSpice for the cases of R = 1.53 kΩ and R = 3.2 kΩ. The corresponding fre-quency response is plotted in Fig. B.46. Observe how f t is approximately independent of R. However, by increasing R, PM is improved from 55° to 75°.
Increasing the PM is desirable because it reduces the overshoot in the step response of the op amp. To verify this point, we simulate in PSpice the step response of the op amp for PM = 55° and PM = 75°. To do that, we connect the op amp in a unity-gain configuration, apply a small (10-mV) pulse signal at the input with very short (1-ps) rise and fall times to emulate a step input, perform a transient-analysis simu-lation, and plot the output voltage as shown in Fig. B.47. Observe that the overshoot in the step response drops from 15% to 1.4% when the phase margin is increased from 55° to 75°.
We conclude this example by computing SR, the slew rate of the op amp. From Eq. (10.40), Gm1 0.333 mA/V = Gm2 0.650 mA/V = C1 26.5 fF = C2 1.04 pF = f P2 Gm2 2πC2 -------------97.2 MHz = R 1 Gm2 ---------1.53 kΩ = = PM 90° tan 1 – ft f P2 ------⎝ ⎠ ⎛ ⎞ – = ft Gm1 2πCC -------------= 1 Gm2 ⁄ SR = 2π f tV OV = Gm1 CC --------- V OV = 166.5 V/μs B-58 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim 25 25 50 0 75 180d 90d 45d 135d 0d Frequency (Hz) 1.0 10 100 1.0 K 10 K 100 K 1.0 M 10 M 100 M 1.0 G dB (V (OUT)) CC 0.6 pF CC 0 CC 0 CC 0.6 pF PM 55 P (V (OUT)) Figure B.44 Magnitude and phase response of the op-amp circuit in Fig. B.43: R = 1.53 kΩ, CC = 0 (no frequency compensation), and CC = 0.6 pF (PM = 55°).
Figure B.45 Magnitude and phase response of the op-amp circuit in Fig. B.43: R = 1.53 kΩ, CC = 0 (no frequency compensation), and CC = 1.8 pF (PM = 75°).
25 25 50 0 75 180d 90d 45d 135d 0d Frequency (Hz) 1.0 10 100 1.0 K 10 K 100 K 1.0 M 10 M 100 M 1.0 G dB (V (OUT)) CC 1.8 pF CC 0 CC 1.8 pF P (V (OUT)) PM 75 CC 0 Example PS.12.1 continued B.2 PSpice Examples B-59 when CC = 0.6 pF. Next, to determine SR using PSpice (see Example PS.2.2), we again connect the op amp in a unity-gain configuration and perform a transient-analysis simulation. However, we now apply Figure B.46 Magnitude and phase response of the op-amp circuit in Fig. B.43: CC = 0.6 pF, R = 1.53 kΩ (PM = 55°), and R = 3.2 kΩ (PM = 75°).
Figure B.47 Small-signal step response (for a 10-mV step input) of the op-amp circuit in Fig. B.43 connected in a unity-gain configuration: PM = 55° (CC = 0.6 pF, R = 1.53 kΩ) and PM = 75° (CC = 0.6 pF, R = 3.2 kΩ).
25 25 50 0 75 180d 90d 45d 135d 0d Frequency (Hz) 1.0 10 100 1.0 K 10 K 100 K 1.0 M 10 M 100 M 1.0 G dB (V (OUT)) R 1.53 kΩ R 3.2 kΩ R 3.2 kΩ R 1.53 kΩ P (V (OUT)) V (OUT) 1.660 V 150 200 250 300 350 1.644 V 1.648 V 1.652 V 1.656 V Time (ns) PM 55 PM 75 PM 75 PM 55 B-60 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim a large pulse signal (3.3 V) at the input to cause slew-rate limiting at the output. The corresponding output-voltage waveform is plotted in Fig. B.48. The slope of the slew-rate-limited output waveform corresponds to the slew rate of the op amp and is found to be SR = 160 V/μs and 60 V/μs for the nega-tive- and positive-going output, respectively. These results, with the unequal values of SR in the two directions, differ from those predicted by the simple model for the slew-rate limiting of the two-stage op-amp circuit (Section 10.1.6). The difference can perhaps be said to be a result of transistor M4 entering the triode region and its output current (which is sourced through CC) being correspondingly reduced. Of course, the availability of PSpice should enable the reader to explore this point further.
Operation of the CMOS Inverter In this example, we will use PSpice to simulate the CMOS inverter whose schematic capture is shown in Fig, B.49. We will assume a 0.5-μm CMOS technology for the MOSFETs and use parts NMOS0P5 and PMOS0P5 whose level-1 model parameters are listed in Table B.4. In addition to the channel length L and the channel width W, we have used the multiplicative factor m to specify the dimensions of the MOSFETs.
The MOSFET parameter m, whose default value is 1, is used in SPICE to specify the number of unit-size MOSFETs connected in parallel (see Fig. B.24). In our simulations, we will use unit-size transistors with L = 0.5 μm and W = 1.25 μm. We will simulate the inverter for two cases: (a) setting so that the NMOS and PMOS transistors have equal widths, and (b) setting so that the PMOS transistor is four times wider than the NMOS transistor (to compensate for the lower mobility in p-chan-nel devices as compared with n-channel ones). Here, mn and mp are the multiplicative factors of, respec-tively, the NMOS and PMOS transistors of the inverter.
Figure B.48 Large-signal step response (for a 3.3-V step-input) of the op-amp circuit in Fig. B.43 connected in a unity-gain configuration. The slope of the rising and falling edges of the output waveform correspond to the slew rate of the op amp.
Time (ns) Slope 160 V/us Slope 60 V/us 0 50 100 150 200 250 300 350 400 0 V 1.0 V 2.0 V 3.0 V 4.0 V 0.5 V V (IN) V (OUT) Example PS.13.1 mp mn ⁄ = 1 mp mn ⁄ = μn μp ⁄ = 4 Example PS.12.1 continued B.2 PSpice Examples B-61 To compute both the voltage transfer characteristic (VTC) of the inverter and its supply current at var-ious values of the input voltage Vin, we apply a dc voltage source at the input and perform a dc analysis with Vin swept over the range of 0 to VDD. The resulting VTC is plotted in Fig. B.50. Note that the slope of the VTC in the switching region (where both the NMOS and PMOS devices are in saturation) is not infi-nite as predicted from the simple theory presented in Chapter 14 (Section 14.2, Fig. 14.20). Rather, the nonzero value of λ causes the inverter gain to be finite. Using the derivative feature of Probe, we can find the two points on the VTC at which the inverter gain is unity (i.e., the VTC slope is −1 V/V) and, hence, determine VIL and VIH. Using the results given in Fig. B.50, the corresponding noise margins are NML = NMH = 1.34 V for the inverter with , while NML = 0.975 V and NMH = 1.74 V for the inverter with . Observe that these results correlate reasonably well with the values obtained using the approximate formula in Eq. (14.58). Furthermore, note that with , the NMOS and PMOS devices are closely matched and, hence, the two noise margins are equal.
The threshold voltage of the CMOS inverter is defined as the input voltage vIN that results in an identical output voltage vOUT, that is, (B.46) Thus, as shown in Fig. B.51, VM is the intersection of the VTC, with the straight line corresponding to vOUT = vIN (this line can be simply generated in Probe by plotting vIN versus vOUT, as shown in Fig. B.51). Note that for the inverter with . Furthermore, decreasing decreases .
Figure B.51 also shows the inverter supply current versus vIN. Observe that the location of the supply-current peak shifts with the threshold voltage.
Figure B.49 Schematic capture of the CMOS inverter in Example PS.13.1. V1 0 V2 {VDD} TD 2n TR 1p TF 1p PW 6n PER 12n OUT M {MN} W 1.25u L 0.5u NMOS0P5 Vsupply VDD DC {VDD} VDD 0 {CL} 0 0 IN 0 M {MP} W 1.25u L 0.5u PMOS0P5 PARAMETERS: CL 0.5p MN 1 MP 1 VDD 3.3 m p mn ⁄ = 4 m p mn ⁄ = 1 m p mn ⁄ = μn μp ⁄ = 4 VM VM = vIN vOUT vIN = VM VDD 2 ⁄ ( ) mp mn ⁄ = 4 mp mn ⁄ VM B-62 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.50 Input–output voltage transfer characteristic (VTC) of the CMOS inverter in Example PS.13.1 with and .
V (IN) 0 V 0.825 V 1.65 V 2.475 V 3.3 V 0 V 0.825 V 1.65 V 2.475 V 3.3 V V (OUT) VIH 1.96 V mpmn 4 mpmn 1 VIH 1.56 V VIL 1.34 V VIL 0.975 V m p mn ⁄ =1 mp mn ⁄ = 4 0 V 1.65 V 2.475 V 0.825 V 3.3 V V (OUT) V (IN) (a) VM 1.64 V mpmn 4 mpmn 1 VM 1.35 V Figure B.51 (a) Output voltage and (b) supply current versus input voltage for the CMOS inverter in Example PS.13.1 with and . mp mn ⁄ = 1 mp mn ⁄ = 4 Example PS.13.1 continued B.2 PSpice Examples B-63 To investigate the dynamic operation of the inverter with PSpice, we apply a pulse signal at the input (Fig. B.49), perform a transient analysis, and plot the input and output waveforms as shown in Fig. B.52. The rise and fall times of the pulse source are chosen to be very short. Note that increasing from 1 to 4 decreases tPLH (from 1.13 ns to 0.29 ns) because of the increased current available to charge CL, with only a minor increase in tPHL (from 0.33 ns to 0.34 ns). The two propagation delays, tPLH and tPHL, are not exactly equal when , because the NMOS and PMOS transistors are still not perfectly matched (e.g., ).
Figure B.52 Transient response of the CMOS inverter in Example PS.13.1 with and .
V (IN) (b) 0 V 0.825 V 1.650 V 2.475 V 3.3 V 0 A 200 uA 400 uA I (Vsupply) mpmn 4 mpmn 1 Figure B.51 (Contd.) V (IN) Time (s) 0 4 n 6 n 2 n 8 n 10 n 12 n 14 n V (OUT) 0 V 1.65 V 2.475 V 0.825 V 3.3 V 0 V 1.65 V 2.475 V 0.825 V 3.3 V mpmn 4 mpmn 1 tPHL 0.34 ns tPLH 0.29 ns tPLH 1.13 ns mp mn ⁄ = 1 mp mn ⁄ = 4 mp mn ⁄ mp mn ⁄ = 4 Vtn Vtp ≠ B-64 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Static and Dynamic Operation of an ECL Gate In this example, we use PSpice to investigate the static and dynamic operation of the ECL gate (stud-ied in Section 15.4) whose schematic capture is shown in Fig. B.53. Having no access to the actual values for the SPICE model parameters of the BJTs utilized in com-mercially available ECL, we have selected parameter values representative of the technology utilized that, from our experience, would lead to reasonable agreement between simulation results and the measured Figure B.53 Schematic capture of the two-input ECL gate for Example PS.14.1 Figure B.54 Circuit arrangement for computing the voltage transfer characteristics of the ECL gate in Fig. B.53.
Example PS.14.1 OR NOR A B VEE R 0 Reference-Voltage Circuit Logic Circuit {R1} Q1 QNOR QOR {Rc2} {Rc1} QR QA QB {Re} {Rb} {Ra} {R3} {R2} Q2 Q3 R1 907 R2 4.98K R3 6.1K Ra 50K Rb 50K Rc1 220 Rc2 245 Re 779 PARAMETERS: VOL 1.77 V VEE1 5.2 V VEE VEE2 2.0 V vA vOR A OR B RT2 50 vNOR NOR NOR OR RT1 50 B.2 PSpice Examples B-65 performance data supplied by the manufacturer. It should be noted that this problem would not be encountered by an IC designer using SPICE as an aid; presumably, the designer would have full access to the proprietary process parameters and the corresponding device model parameters. In any case, for the simulations we conducted, we have utilized the following BJT model parameter values15: IS = 0.26 fA, βF = 100; βR = 1, τF = 0.1 ns, Cje = 1 pF, Cjc = Cμ = 1.5 pF, and = 100 V.
We use the circuit arrangement of Fig. B.54 to compute the voltage transfer characteristics of the ECL gate, that is, vOR and vNOR versus vA, where vA is the input voltage at terminal A. For this investigation, the other input is deactivated by applying a voltage vB = VOL = −1.77 V. In PSpice, we perform a dc-analysis simula-tion with vA swept over the range −2 V to 0 V in 10-mV increments and plot vOR and vNOR versus vA. The simu-lation results are shown in Fig. B.55. We immediately recognize the VTCs as those we have seen and (partially) verified by manual analysis in Section 15.4. The two transfer curves are symmetrical about an input voltage of −1.32 V. PSpice also determined that the voltage VR at the base of the reference transistor QR has exactly this value (−1.32 V), which is also identical to the value we determined by hand analysis of the refer-ence-voltage circuit.
Utilizing Probe (the graphical interface of PSpice), one can determine the values of the important parameters of the VTC, as follows: OR output: VOL = −1.77 V, VOH = −0.88 V, VIL = −1.41 V, and VIH = −1.22 V; thus, NMH = 0.34 V and NML = 0.36 V NOR output: VOL = −1.78 V, VOH = −0.88 V, VIL = −1.41 V, and VIH = −1.22 V; thus, NMH = 0.34 V and NML = 0.37 V 15In PSpice, we have created a part called QECL based on these BJT model parameter values. Readers can find this part in the SEDRA.olb library, which is available on the CD accompanying this book.
Figure B.55 Voltage transfer characteristics of the OR and NOR outputs (see Fig. B.54) for the ECL gate shown in Fig. B.53. Also indicated is the reference voltage, VR = −1.32 V.
V A v(NOR) v(OR) v(R) vA 2.0 V 1.5 V 1.0 V 0.5 V 0.0 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V Reference voltage NOR output OR output B-66 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim These values are remarkably close to those found by pencil-and-paper analysis in Section 15.4.
We next use PSpice to investigate the temperature dependence of the transfer characteristics. The reader will recall that in Section 15.4, we discussed this point at some length and carried out a hand analy-sis in Example 15.7. Here, we use PSpice to find the voltage transfer characteristics at two temperatures, 0°C and 70°C (the VTCs shown in Fig. B.55 were computed at 27°C) for two different cases: the first case with VR generated as in Fig. B.53, and the second with the reference-voltage circuit eliminated and a con-stant, temperature-independent reference voltage of −1.32 V applied to the base of QR. The simulation results are displayed in Fig. B.56. Figure B.56(a) shows plots of the transfer characteristics for the case in which the reference circuit is utilized, and Fig. B.56(b) shows plots for the case in which a constant refer-ence voltage is employed. Figure B.56(a) indicates that as the temperature is varied and VR changes, the values of VOH and VOL also change but remain centered on VR. In other words, the low and high noise margins remain nearly equal. As mentioned in Section 15.4 and demonstrated in the analysis of Example 15.4, this is the basic idea behind making VR temperature dependent. When VR is not temperature dependent, the sym-metry of VOL and VOH around VR is no longer maintained, as demonstrated in Fig. B.56(b). Finally, we show some of the values obtained in Table B.12. Observe that for the temperature-compensated case, the average value of VOL and VOH remains very close to VR. The reader is encouraged to compare these results to those obtained in Example 15.4. Figure B.56 Comparing the voltage transfer characteristics of the OR and NOR outputs (see Fig. B.54) of the ECL gate shown in Fig. B.53, with the reference voltage VR generated using: (a) the temperature-compensated bias net-work of Fig. B.53; (b) a temperature-independent voltage source.
(a) 2.0 V 1.5 V 1.0 V 0.5 V 0.0 V 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V 70 C 0 C 70 C 0 C 70 C 0 C v(NOR) v(OR) v(R) vA Example PS.14.1 continued B.2 PSpice Examples B-67 The dynamic operation of the ECL gate is investigated using the arrangement of Fig. B.57. Here, two gates are connected by a 1.5-m coaxial cable having a characteristic impedance (Z0) of 50 Ω. The manufac-turer specifies that signals propagate along this cable (when it is properly terminated) at about half the speed of light, or 15 cm/ns. Thus we would expect the 1.5-m cable we are using to introduce a delay td of 10 ns.
Observe that in this circuit (Fig. B.57), resistor RT1 provides the proper cable termination. The cable is Table B.12 PSpice-Computed Parameter Values of the ECL Gate, With and Without Temperature Compensation, at Two Different Temperatures Temperature-Compensated Not Temperature-Compensated Temperature Parameter OR NOR OR NOR 0°C VOL −1.779 V −1.799 V −1.786 V −1.799 V VOH −0.9142 V −0.9092 V −0.9142 V −0.9092 V −1.3466 V −1.3541 V −1.3501 V −1.3541 V VR −1.345 V −1.345 V −1.32 V −1.32 V 1.6 mV 9.1 mV 30.1 mV 34.1 mV 70°C VOL −1.742 V −1.759 V −1.729 V −1.759 V VOH −0.8338 V −0.8285 V −0.8338 V −0.8285 V −1.288 V −1.294 V −1.2814 V −1.294 V VR −1.271 V −1.271 V −1.32 V −1.32 V 17 mV 23 mV 38 mV 26.2 mV Figure B.56 (Contd.).
(b) vA 2.0 V 2.0 V 1.4 V 1.2 V 1.0 V 0.8 V 1.6 V 1.8 V 1.5 V 1.0 V 0.5 V 0.0 V 70 C 0 C 0 C 70 C 0 C and 70 C v(NOR) v(OR) v(R) V avg = VOL V OH + 2 -------------------------Vavg VR – V avg = VOL V OH + 2 -------------------------Vavg VR – B-68 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim assumed to be lossless and is modeled in PSpice using the transmission line element (the T part in the Ana-log library) with Z0 = 50 Ω and td = 10 ns. A voltage step, rising from −1.77 V to −0.884 V in 1 ns, is applied to the input of the first gate, and a transient analysis over a 30-ns interval is requested. Figure B.58 shows plots of the waveforms of the input, the voltage at the output of the first gate, the voltage at the input of the second gate, and the output. Observe that despite the very high edge speeds involved, the waveforms are rea-sonably clean and free of excessive ringing and reflections. This is particularly remarkable because the sig-nal is being transported over a relatively long distance. A detailed examination of the waveforms reveals that the delay along the cable is indeed 10 ns, and the delay of the second gate is about 1.06 ns.
Figure B.57 Circuit arrangement for investigating the dynamic operation of ECL. Two ECL gates (Fig. B.53) are connected in cascade via a 1.5-m coaxial cable which has a characteristic impedance Z0 = 50 Ω and a propagation delay td = 10 ns. Resistor RT1 (50 Ω) provides proper termination for the coaxial cable.
Figure B.58 Transient response of a cascade of two ECL gates interconnected by a 1.5-m coaxial cable having a characteristic impedance of 50 Ω and a delay of 10 ns (see Fig. B.57).
IN IN2 OUT OUT1 1.5 m Transmission line RT1 50 RT2 50 Z0 50 td 10 ns RT3 50 RT4 50 vIN vOUT VEE1 5.2 V VEE1 5.2 V VEE2 2 V VEE2 2 V VEE2 2 V v(IN) v(OUT1) v(IN2) v(OUT) Time (ns) 0 5 10 15 20 25 30 0.8 V 1.0 V 1.2 V 1.4 V 1.6 V 1.8 V 2.0 V v(IN) v(OUT1) v(IN2) v(OUT) Example PS.14.1 continued B.2 PSpice Examples B-69 Finally, to verify the need for properly terminating the transmission line, the dynamic analysis is repeated, this time with the 50-Ω coaxial cable replaced with a 300-Ω twisted-pair cable while keeping the termination resistance unchanged. The results are the slow rising and falling and long-delayed waveforms shown in Fig. B.59. (Note the change of plotting scale.) Verification of the Design of a Fifth-Order Chebyshev Filter In this example we show how SPICE can be utilized to verify the design of a fifth-order Chebyshev filter.
Specifically, we simulate the operation of the circuit whose component values were obtained in Exercise 11.20. The complete circuit is shown in Fig. B.60(a). It consists of a cascade of two second-order simulated-LCR resonators using the Antoniou circuit and a first-order op amp–RC circuit. Using PSpice, we would like to compare the magnitude of the filter response with that computed directly from its transfer function. Here, we note that PSpice can also be used to perform the latter task by using the Laplace transfer-function block in the analog-behavioral-modeling (ABM) library.
Since the purpose of the simulation is simply to verify the design, we assume ideal components. For the op amps, we utilize a near-ideal model, namely, a voltage-controlled voltage source (VCVS) with a gain of 106 V/V, as shown in Fig. B.60(b).16 Figure B.59 Transient response of a cascade of two ECL gates interconnected by a 1.5-m cable having a character-istic impedance of 300 Ω. The termination resistance RT1 (see Fig. B.57) was kept unchanged at 50 Ω. Note the change in time scale of the plot.
16SPICE models for the op amp are described in Section B.1.1 0 50 100 150 200 250 300 350 400 0.5 V 1.0 V 1.5 V 2.0 V Time (ns) v(IN) v(OUT1) v(IN2) v(OUT) Example PS.16.1 B-70 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim In SPICE, we apply a 1-V ac signal at the filter input, perform an ac-analysis simulation over the range 1 Hz to 20 kHz, and plot the output voltage magnitude versus frequency, as shown in Fig. B.61.
Figure B.60 Circuits for Example PS.16.1 (a) Fifth-order Chebyshev filter circuit implemented as a cascade of two second-order simulated LCR resonator circuits and a single first-order op amp–RC circuit. (b) VCVS representation of an ideal op amp with gain A.
Vin R51 10 k R62 55.6 k R32 10 k C62 1.6 nF R13 10 k C42 1.6 nF R21 10 k R11 10 k R61 14 k R31 10 k C41 2.43 nF C61 2.43 nF R12 10 k R22 10 k R52 10 k A11 A32 A12 A21 A31 A22 A13 Vout C13 5.5 nF R23 10 k (a) Vid Vo Vo Vid A AVid (b) Example PS.16.1 continued B.2 PSpice Examples B-71 Both an expanded view of the passband and a view of the entire magnitude response are shown. These results are almost identical to those computed directly from the ideal transfer function, thereby verifying the correctness of the design. Effect of Finite Op-Amp Bandwidth on the Operation of the Two-Integrator-Loop Filter In this example, we investigate the effect of the finite bandwidth of practical op amps on the response of a two-integrator-loop bandpass filter utilizing the Tow-Thomas biquad circuit of Fig. 11.25(b). The circuit is designed to provide a bandpass response with f0 = 10 kHz, Q = 20, and a unity center-frequency gain.
The op amps are assumed to be of the 741 type. Specifically, we model the terminal behavior of the op amp with the single-time-constant linear network shown in Fig. B.62. Since the analysis performed here is a small-signal (ac) analysis that ignores nonlinearities, no nonlinearities are included in this op-amp Figure B.61 Magnitude response of the fifth-order lowpass filter circuit shown in Fig. B.60: (a) an expanded view of the passband region; (b) a view of both the passband and stopband regions. 0.5 1.0 0.0 dB 0 5 Frequency (kHz) 10 15 20 (a) 0 5 Frequency (kHz) 10 15 20 50 0 dB (b) Example PS.16.2 B-72 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim macromodel. (If the effects of op-amp nonlinearities are to be investigated, a transient analysis should be performed.) The following values are used for the parameters of the op-amp macromodel in Fig. B.62: Rid = 2 MΩ Ricm = 500 MΩ Ro = 75 Ω Gm = 0.19 mA/V Rb = 1.323 × 109 Ω Cb = 30 pF These values result in the specified input and output resistances of the 741-type op amp. Further, they provide a dc gain A0 = 2.52 × 105 V/V and a 3-dB frequency fb of 4 Hz, again equal to the values specified for the 741. Note that the selection of the individual values of Gm, Rb, and Cb is immaterial as long as GmRb = A0 and The Tow-Thomas circuit simulated is shown in Fig. B.63. The circuit is simulated in PSpice for two cases: (1) assuming 741-type op amps and using the linear macromodel in Fig. B.62; and (2) assuming ideal op amps with dc gain of and using the near-ideal model in Fig. B.60. In both cases, Figure B.62 One-pole equivalent-circuit macromodel of an op amp operated within its linear region.
Figure B.63 Circuit for Example PS.16.2 Second-order bandpass filter implemented with a Tow-Thomas biquad circuit having f0 = 10 kHz, Q = 20, and unity center-frequency gain. A0 GmR1 b 1/RbCb Gm Vid Vb Vid Rb Cb Ro Vo1 Vo Rid 2Ricm 2Ricm Rg 200 k A1 A2 A3 Vout C1 1.59 nF C2 1.59 nF Rd 200 k R2 10 k R3 10 k R4 10 k Vin R1 10 k CbRb = 1 2 ⁄ πfb.
A0 = 106 V/V Example PS.16.2 continued B.2 PSpice Examples B-73 we apply a 1-V ac signal at the filter input, perform an ac-analysis simulation over the range 8 kHz to 12 kHz, and plot the output-voltage magnitude versus frequency.
The simulation results are shown in Fig. B.64, from which we observe the significant deviation between the response of the filter using the 741 op amp and that using the near-ideal op-amp model. Specifically, the response with practical op amps shows a deviation in the center frequency of about −100 Hz, and a reduction in the 3-dB bandwidth from 500 Hz to about 110 Hz. Thus, in effect, the filter Q factor has increased from the ideal value of 20 to about 90. This phenomenon, known as Q-enhancement, is pre-dictable from an analysis of the two-integrator-loop biquad with the finite op-amp bandwidth taken into account [see Sedra and Brackett (1978)]. Such an analysis shows that Q-enhancement occurs as a result of the excess phase lag introduced by the finite op-amp bandwidth. The theory also shows that the Q-enhancement effect can be compensated for by introducing phase lead around the feedback loop.
This can be accomplished by connecting a small capacitor, Cc, across resistor R2. To investigate the potential of such a compensation technique, we repeat the PSpice simulation with various capacitance values. The results are displayed in Fig. B.65(a). We observe that as the compensation capacitance is increased from 0 pF, both the filter Q and the resonance peak of the filter response move closer to the desired values. It is evident, however, that a compensation capacitance of 80 pF causes the response to deviate further from the ideal. Thus, optimum compensation is obtained with a capacitance value between 60 pF and 80 pF. Further experimentation using PSpice enabled us to determine that such an optimum is obtained with a compensation capacitance of 64 pF. The corresponding response is shown, together with the ideal response, in Fig. B.65(b). We note that although the filter Q has been restored to its ideal value, there remains a deviation in the center frequency. We shall not pursue this matter any Figure B.64 Comparing the magnitude response of the Tow-Thomas biquad circuit (shown in Fig. B.63) constructed with 741-type op amps, with the ideal magnitude response. These results illustrate the effect of the finite dc gain and bandwidth of the 741 op amp on the frequency response of the Tow-Thomas biquad circuit. 20 10 0 10 20 dB 8.0 Frequency (kHz) 10 741 op amp Ideal op amp B-74 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim further here; our objective is not to present a detailed study of the design of two-integrator-loop biquads; rather, it is to illustrate the application of SPICE in investigating the nonideal performance of active-filter circuits, generally.
(a) 10 15 5 5 20 0 dB 10 Cc 60 pF Cc 20 pF Cc 0 pF Cc 80 pF Cc 40 pF Ideal 9.0 9.2 10.0 10.4 9.6 10.8 Frequency (kHz) (b) 8.0 8.5 10.0 11.0 10.5 9.5 9.0 11.5 Frequency (kHz) 20 0 8 16 4 12 4 dB Cc 64 pF Ideal Figure B.65 (a) Magnitude response of the Tow-Thomas biquad circuit with different values of compensation capacitance. For comparison, the ideal response is also shown. (b) Comparing the magnitude response of the Tow-Thomas biquad circuit using a 64-pF compensation capacitor and the ideal response. Example PS.16.2 continued B.2 PSpice Examples B-75 Wien-Bridge Oscillator For our first example on oscillators, we shall simulate the operation of the Wien-bridge oscillator whose schematic capture is shown in Fig. B.66. The component values are selected to yield oscillations at 1 kHz.
We would like to investigate the operation of the circuit for different settings of R1a and R1b, with . Since oscillation just starts when (see Exercise 12.4), that is, when R1a = 20 kΩ and R1b = 30 kΩ, we consider three possible settings: (a) R1a = 15 kΩ, R1b = 35 kΩ; (b) R1a = 18 kΩ, R1b = 32 kΩ; and (c) R1a = 25 kΩ, R1b = 25 kΩ. These settings correspond to loop gains of 1.33, 1.1, and 0.8, respectively. In PSpice, a 741-type op amp and 1N4148-type diodes are used to simulate the circuit in Fig. 12.42.17 A transient-analysis simulation is performed with the capacitor voltages initially set to zero. This demon-strates that the op-amp offset voltage is sufficient to cause the oscillations to start without the need for special start-up circuitry. Figure B.67 shows the simulation results. The graph in Fig. B.67(a) shows the 17The SPICE models for the 741 op amp and the 1N4148 diode are available in PSpice. The 741 op amp was characterized in Example PS.2.2. The 1N4148 diode was used in Example PS.4.1.
Figure B.66 Example PS.17.1: Schematic capture of a Wien-bridge oscillator.
Example PS.17.1 R1a R1b + = 50 kΩ R2 R1b + ( ) R1a ⁄ = 2 {VEE} VEE 0 {VCC} VCC 0 C3 16n C4 16n R1a 18K R1b {50K{R1a}} R2 10K R3 10K R4 10K VCC 15 VEE 15 PARAMETERS: {R2} {R3} 0 {C3} {R4} {C4} IC 0 IC 0 0 0 {R1b} D2 D1 OUT D1N4148 D1N4148 {R1a} VEE VCC A1 V V OS2 A OS1 uA741 OUT B-76 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.67 Start-up transient behavior of the Wien-bridge oscillator shown in Fig. B.66 for various values of loop gain.
15 V Time (ms) V (OUT) 10 V 0 V 10 V 15 V 0 5 10 15 20 (a) R1a 15 k , Loop Gain 1.33 8.0 V Time (ms) V (OUT) 0 V 4.0 V 4.0 V 8.0 V 0 5 10 15 20 (b) R1a 18 k , Loop Gain 1.1 Time (ms) V (OUT) 2.5 mV 0 5 10 15 20 0 V 2.5 mV 5.0 mV (c) R1a 25 k , Loop Gain 0.8 Example PS.17.1 continued B.2 PSpice Examples B-77 output waveform obtained for a loop gain of 1.33 V/V. Observe that although the oscillations grow and stabilize rapidly, the distortion is considerable. The output obtained for a loop gain of 1.1, shown in Fig.
B.67(b), is much less distorted. However, as expected, as the loop gain is reduced toward unity, it takes longer for the oscillations to build up and for the amplitude to stabilize. For this case, the frequency is 986.6 Hz, which is reasonably close to the design value of 1 kHz, and the amplitude is 7.37 V. Finally, for a loop gain of 0.8, the output shown in Fig. B.67(c) confirms our expectation that sustained oscillations cannot be obtained when the loop gain is less than unity.
PSpice can be used to investigate the spectral purity of the output sine wave. This is achieved using the Fourier analysis facility. It is found that in the steady state, the output for the case of a loop gain of 1.1 has a THD figure of 1.88%. When the oscillator output is taken at the op-amp output (voltage vA), a THD of 2.57% is obtained, which, as expected, is higher than that for the voltage vOUT, but not by very much. The output terminal of the op amp is of course a much more convenient place to take the output.
Active-Filter-Tuned Oscillator In this example, we use PSpice to verify our contention that a superior op amp–oscillator can be realized using the active-filter-tuned circuit of Fig. 12.11. We also investigate the effect of changing the value of the filter Q factor on the spectral purity of the output sine wave.
Consider the circuit whose schematic capture is shown in Fig. B.68. For this circuit, the center frequency is 1 kHz, and the filter Q is 5 when R1 = 50 kΩ and 20 when R1 = 200 kΩ. As in the case of the Wien-bridge circuit in Example PS.17.1, 741-type op amps and 1N4148-type diodes are utilized. In PSpice, a transient-analysis simulation is performed with the capacitor voltages initially set to zero. To be able to com-pute the Fourier components of the output, the analysis interval chosen must be long enough to allow the oscillator to reach a steady state. The time to reach a steady state is in turn determined by the value of the fil-ter Q; the higher the Q, the longer it takes the output to settle. For Q = 5, it was determined, through a com-bination of approximate calculations and experimentation using PSpice, that 50 ms is a reasonable estimate for the analysis interval. For plotting purposes, we use 200 points per period of oscillation.
The results of the transient analysis are plotted in Fig. B.69. The upper graph shows the sinusoi-dal waveform at the output of op amp A1 (voltage v1). The lower graph shows the waveform across the diode limiter (voltage v2). The frequency of oscillation is found to be very close to the design value of 1 kHz. The amplitude of the sine wave is determined using Probe (the graphical interface of PSpice) to be 1.15 V (or 2.3 V p-p). Note that this is lower than the 3.6 V estimated in Exercise 12.7.
The latter value, however, was based on an estimate of 0.7-V drop across each conducting diode in the limiter. The lower waveform in Fig. B.69 indicates that the diode drop is closer to 0.5 V for a 1 V peak-to-peak amplitude of the pseudo-square wave. We should therefore expect the peak-to-peak amplitude of the output sinusoid to be lower than 3.6 V by the same factor, and indeed it is approxi-mately the case.
In PSpice, the Fourier analysis of the output sine wave indicates that THD = 1.61%. Repeating the simulation with Q increased to 20 (by increasing R1 to 200 kΩ), we find that the value of THD is reduced to 1.01%. Thus, our expectations that the value of the filter Q can be used as an effective means for constrolling the THD of the output waveform are confirmed.
Example PS.17.2 B-78 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim uA741 VCC VEE VCC VEE {C1} {R6} 2 {R1} {R2} {R3} {R4} IC 0 IC 0 D1 D1N4148 D2 D1N4148 {R5} {C2} 0 0 0 0 1 OUT OS2 OS1 OS1 A2 uA741 A1 OS2 OUT {VEE} VEE 0 {VCC} VCC 0 C1 16n C2 16n R1 200K R2 10K R3 10K R4 10K R5 10K R6 10K VCC 15 VEE 15 PARAMETERS: V V V V Figure B.68 Example PS.17.2: Schematic capture of an active-filter-tuned oscillator for which the Q of the filter is adjustable by changing R1.
B.3 Multisim Examples B-79 The CS Amplifier In this example, we will use Multisim to characterize a CS amplifier whose schematic capture is shown in Fig. B.70. We will assume a 0.18-μm CMOS technology for the MOSFET and use typical SPICE level-1 model parameters for this technology, as provided in Table B.4. We will also assume a signal-source resistance Rsig = 10 k , a load resistance RL = 50 k , and bypass and coupling capacitors of 10 μF. The targeted specifications for this CS amplifier are a voltage gain |Av| = 10 V/V and a maximum power con-sumption P = 0.45 mW. As should always be the case with computer simulation, we will begin with an approximate hand-analysis design. We will then use Multisim to fine-tune our design and to investigate the performance of the final design. The amplifier specifications are summarized in Table B.13.
Hand Design With a 1.8-V power supply, the drain current of the MOSFET must be limited to ID = P/VDD = 0.45 mW/ 1.8 V = 0.25 mA to meet the power consumption specification. Choosing VOV = 0.15 V and VDS = VDD /3 = 0.6 V (to achieve a large signal swing at the output), the MOSFET can now be sized as Figure B.69 Output waveforms of the active-filter-tuned oscillator shown in Fig. B.68 for Q = 5 (R1 = 50 kΩ). 2.0 V 0 V 2.0 V 0 V 45 46 47 48 Time (ms) 49 50 500 mV SEL>> 500 mV V (1) V (2) Example MS.5.1 B.3 Multisim Examples Ω Ω B.3 Multisim Examples B-80 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim where . Here, Leff rather than L is used to more accurately compute ID.
The effect of using Weff instead of W is much less important, because typically W Wov. Thus, choos-ing L = 0.200 µm results in Leff = L – 2Lov = 0.180 μm, and W = 86 Leff = 15.48 μm.
Note that we chose L slightly larger than Lmin. This is a common practice in the design of analog ICs to minimize the effects of fabrication nonidealities on the actual value of L. As we have seen, this is particu-larly important when the circuit performance depends on the matching between the dimensions of two or more MOSFETs (e.g., in the current-mirror circuits studied in Chapter 6).
Next, RD is calculated based on the desired voltage gain: where Figure B.70 Capture schematic of the CS amplifier.
Table B.13 CS Amplifier Specifications Parameters Value Power 0.45 mW Rsig 10 kΩ RL 50 kΩ |Av| 10 V/V VDD 1.8 V 10 k 10 F Rsig vsig vsig 0 Vrms RG2 600 k 5% RS 0 CS 10 F 5% RG1 1.8 V 1.8 V VDD DEVICE PARAMETERS NAME W L KP LD VID LAMBDA GAMMA Q1:NMOS 15.48u 0.2u 291u 0.01u 0.45 0.08 0.3 VDD 1.2 M 5% RD 3.41k 5% RL 50 k VD VS Q1 10 F CCO 1 kHz 0 CCI VIN W Leff --------ID 1 2 ---kn ′V OV 2 1 λVDS + ( ) ------------------------------------------------250 10 6 – × 1 2 ---246.2 10 2 – 0.156 1 0.08 0.6 × + ( ) × × × × ------------------------------------------------------------------------------------------------------- 86 = = kn ′ μnCox 246.2μA V2 ⁄ = = Av gm RD||RL||ro ( ) 10V V ⁄ RD3.41kΩ ⇒ = = gm 2ID VOV ---------2 0.25 10 3 – × × 0.15 ------------------------------------3.33 mA/V = = = Example MS.5.1 continued B.3 Multisim Examples B-81 and Hence, the dc bias voltage is To stabilize the bias point of the CS amplifier, we include a resistor in the source lead. In other words, to bias the MOSFET at , we need an However, as a result of including such a resistor, the gain drops by a factor of (1 + gmRS). Therefore, we include a capacitor, CS, to eliminate the effect of RS on ac operation of the amplifier and gain.
Finally, choosing the current in the biasing branch to be 1 μA gives RG1 + RG2 = VDD /1μA = 1.8 Ω.
Also, we know that Hence, Using large values for these gate resistors ensures that both their power consumption and the loading effect on the input signal source are negligible.
Simulation Amplifier Biasing We will now use Multisim to verify our design and investigate the perform-ance of the CS amplifier. We begin by performing a bias-point simulation to verify that the MOSFET is properly biased in the saturation region and that the dc voltages and currents match the expected values (refer to this example’s simulation file: Ch5_CS_Amplifier_Ex_DC.ms10). The results are shown in Fig. B.71.
ro VA ID ------12.5 0.25 10 3 – × ---------------------------50 kΩ = = = VD VDD IDRD – 0.9457 V.
= = VDS VDD 3 ⁄ = Rs VS ID -----VD VDD 3 ⁄ – ( ) ID ----------------------------------0.3475 0.25 10 3 – × ---------------------------1.39 kΩ = = = = VGS VOV Vt + 0.15 0.45 0.6 V VG ⇒ = VS = 0.6 0.3475 0.6 0.9475 V = + = + + = = RG2 RG1 RG2 + ------------------------VG VDD ----------0.9475 1.8 ----------------RG1 0.8525 MΩ = , RG2 0.9475MΩ = ⇒ = = VDD 1.8 V RG1 852.5 k 5% RG2 947.5 k 5% RS 1.39 k 5% RD 3.41 k 5% Q1 VD VS 1.8 V V: 948 mV I: 250 uA V: 347 mV I: 250 uA V: 947 mV I: 0 A VDD Figure B.71 DC bias-point analysis of the CS amplifier.
B-82 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Amplifier Gain We can also verify if our design provides the desired gain. This can be done by per-forming transient response analysis, as set up in Ch5_CS_Amplifier_Ex_gain.ms10. As can be seen from Fig. B.72, |Gv| |Av| 11 V/V. Note the values of overall voltage gain Gv and Av are close since Rin = (RG1||RG2) Rsig. In the case where the capacitor CS is not included (CS = 0), the gain drops by a factor of 5.63 (approximately equal to 1 + gmRS) to 1.95. This is as expected from our study of the CS amplifier with a source-degeneration resistance.
Investigating Amplifier Bias Stability We can also demonstrate the improved bias stability achieved when a source resistor RS is used. Specifically, we change (in the MOSFET level-1 model) the value of the zero-bias threshold voltage parameter VT0 by ± 0.1 V and perform bias-point simulation in Multisim. Table B.14 shows the corresponding variations in ID and VD for the case in which RS = 1.39 k . For the case without source degeneration, we use an RS = 0 in the given schematic. Further-more, to obtain the same ID and VD in both cases (for the nominal threshold voltage Vt 0 = 0.45 V), we use RG1 = 1.2 M and RG2 = 0.6 M . Figure B.72 Av and Gv of the CS amplifier: transient analysis.
Table B.14 Variations in VT0 With RS = 1.39 k VT0 (V) ID (µA) ID % Change VD (V) VD % Change 0.45 250 0 0.948 0 0.35 309 23.60% 0.748 -21.10% 0.55 192 -37.86% 1.14 20.25% 15 m 10 m 5 m 0 Voltage (V) –5 m –10 m –15 m 0 500.0 1.0 m 1.5 m Time (s) 2.0 m 2.5 m V(vout), V(vin), Ω Ω Ω Ω Example MS.5.1 continued B.3 Multisim Examples B-83 Also, Table B.15 shows the worst case deviation of ID and VD values, when imposing 5% tolerance on the resistors that determine the gate voltage. Accordingly, we see that the source-degeneration resistor makes the bias point of the CS amplifier less sensitive to changes in the threshold voltage and the values of gate resistors. However, unless a large bypass capacitor CS is used, this reduced sensitivity comes at the expense of a reduction in gain.
Largest Allowable Input Signal Swing Next, we wish to analyze this amplifier circuit to deter-mine the largest allowable vsig for which the transistor remains in saturation: By enforcing this condition, with equality, at the point vGS is maximum and vDS is correspondingly mini-mum, we write: This can be verified from Ch5_CS_Amplifier_Ex_swing.ms10 simulation setup. If we increase the source signal’s amplitude beyond approximately 73 mV, we can observe the distortion in the output signal, indi-cating that the MOSFET has entered the triode region.
Amplifier Linearity Finally, we can investigate the linearity of the designed amplifier. To do so, we use the setup in Ch5_CS_Amplifier_Ex_linearity.ms10. In this case, we use a triangular wave-form and increase the amplitude of the signal until the output waveform begins to show nonlinear distortion (i.e., the rising and falling edges are no longer straight lines). Based on hand analysis, lin-earity holds as long as vin 2Vov. According to the simulation results, linearity holds until vin reaches the value of approximately 30 mV, which is one-tenth of the value of 2Vov.
Without RS 0.45 255.96 0 0.9292 0 0.35 492 96.80% 0.122 -87.13% 0.55 30.1 -90.26% 1.7 127.27% Table B.15 Variations Due to Resistor Tolerances RG1 (MΩ) RG2 (MΩ) With RS = 1.39 k s ID (µA) ID % Change VD (V) VD % Change Nominal 0.8525 0.9475 250 0 947.67 0 ID low VD high 0.895 0.9 223.86 -10.44% 1.037 9.39% ID high VD low 0.81 0.995 276.1 10.46% 0.858 -9.41% RG1 (MΩ) RG2 (MΩ) Without RS ID (µA) ID % Change VD (V) VD % Change Nominal 1.2 0.6 255.96 0 0.9292 0 ID low VD high 1.26 0.57 143.28 -44.02% 1.311 41.44% ID high VD low 1.14 0.63 398.62 55.74% 0.447 -52.47% Ω vDS vGS vt – ≥ vDS,min vGS,max vt0 – ≥ vDS Gv vsig – VGS v + sig vt0 – = vsig VDS VGS – Vt0 + 1 Gv + ( ) --------------------------------------0.9475 0.6 – 0.45 + 11 ----------------------------------------------72.5 mV = = = B-84 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Dependence of b on the Bias Current In this example, we use Multisim to investigate the dependence of βdc on the collector bias current of the Q2N3904 discrete BJT (from Fairchild Semiconductor) whose model parameters are listed in Table B.16 and are available in Multisim. As shown in the schematic capture of Fig. B.73, the VCE of the BJT is fixed using a constant voltage source (in this example, VCE = 2 V) and a dc current source IB is applied at the base.
To obtain the dependence of βdc on the collector current IC, we perform a dc-analysis simulation in which the sweep variable is the current source IB. The βdc of the BJT, which corresponds to the ratio of the collector current IC to the base current IB, can then be plotted versus IC (by exporting the data to a graphing software), as shown in Fig. B.74. We see that to operate at the maximum value of βdc (i.e., βdc = 163), at VCE = 2 V, the BJT must be biased at an IC = 10 mA. Since increasing the bias current of a transistor increases the power dissipation, it is clear from Fig. B.74 that the choice of current IC is a trade-off between the current gain βdc and the power dissipation. Generally speaking, the optimum IC depends on the application and technology in hand. For example, for the Q2N3904 BJT operating at VCE = 2 V, decreasing IC by a factor of 20 (from 10 mA to 0.5 mA) results in a drop in βdc of about 25% (from 163 to 123).
Table B.16 SPICE Model Parameters of the Q2N3904 Discrete BJT Is = 6.734f Bf = 416.4 Xtb = 1.5 Ikr = 0 Vjc = .75 Vje = .75 Vtf = 4 Xti = 3 Ne = 1.259 Br = .7371 Rc = 1 Fc = .5 Tr = 239.5n Xtf = 2 Eg = 1.11 Ise = 6.734f Nc = 2 Cjc = 3.638p Cje = 4.493p Tf = 301.2p Rb = 10 Vaf = 74.03 Ikf = 66.78m Isc = 0 Mjc = .3085 Mje = .2593 Itf = .4 Figure B.73 The test bench used to investigate the dependence of βdc on the bias current for the Q2N3904 discrete BJT.
Example MS.6.1 Q1 2N3904 IB VCE 2 V B.3 Multisim Examples B-85 The CE Amplifier with Emitter Resistance In this example, we use Multisim to compute the voltage gain and frequency response of the CE amplifier and investigate its bias-point stability. A schematic capture of the CE amplifier is shown in Fig. B.75. We will use part Q2N3904 for the BJT and a ±5-V power supply. We will assume a signal-source resistor Rsig = 10 k , a load resistor RL = 10 k and bypass and coupling capacitors of 10 μF. To enable us to investigate the effect of including a resistance in the signal path of the emitter, a resistor Rce is connected in series with the emitter bypass capacitor CE. Note that the roles of RE and Rce are different. Resistor RE is the dc emitter-degeneration resistor because it appears in the dc path between the emitter and ground. It is therefore used to help stabilize the bias point for the amplifier. The equivalent resistance Re = RE || Rce is the small-signal emitter-degeneration resistance because it appears in the ac (small-signal) path between the emitter and ground and helps stabilize the gain of the amplifier. In this example, we will investigate the effects of both RE and Re on the performance of the CE amplifier. However, as should always be the case with computer simulation, we will begin with an approximate hand analysis. In this way, maximum advantage and insight can be obtained from simulation.
Based on the plot of βdc versus IB in Fig. B.74, a collector bias current IC (i.e., βdcIB ) of 0.5 mA is selected for the BJT, resulting in βdc = 123. This choice of IC is a reasonable compromise between power dissipation and current gain. Furthermore, a collector bias voltage VC of 0 V (i.e., at the mid–supply rail) is selected to achieve a high signal swing at the amplifier output. For VCE = 2 V, the result is that VE = –2 V, requiring bias resistors with values Assuming VBE = 0.7 V and βdc = 123, we can determine Figure B.74 Dependence of βdc on IC (at VCE = 2 V) in the Q2N3904 discrete BJT.
180 160 140 b (IC/IB) 120 100 80 60 40 20 0 0 0.005 0.01 0.015 0.02 0.025 0.03 IC 0.035 Example MS.6.2 Ω Ω, RC VCC VC – IC ----------------------10 kΩ = = RE VE VEE – IC ---------------------320 kΩ = = RB VB IB ------– VBE VE + IC βdc ⁄ ----------------------– 320 kΩ = = = B-86 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Next, the input resistance Rin and the voltage gain |Av| of the CE amplifier: For simplicity, we will assume = 123, resulting in Thus, with no small-signal emitter degeneration (i.e., Rce = 0), Rin = 6.1 kΩ and |Av| = 38.2 V/V. Using the equation found for |Av| and assuming that RB is large enough to have a negligible effect on Rin, it can be shown that the emitter-degeneration resistance Re decreases the voltage gain |Av| by a factor of Therefore, to limit the reduction in voltage gain to a factor of 2, we will select Figure B.75 Schematic capture of the CE amplifier.
Rsig 10 k CCI 10 µF IC = 0 V RB 340 k Q1 2N3904 RE1 6 k RC 10 k CCO 10 µF IC = 0 V CB 10 µF IC = 0 V Rce 1 RL 10 k V1 1mVpk 1 kHz 0 Deg VEE –5 V VCC 5 V vout vsig VE VC VB Rin RB βac 1 + ( ) re Re + ( ) = Av Rin Rsig Rin + -----------------------RC|| RL re Re + -----------------× – = βac βdc re βac βac 1 + ----------------⎝ ⎠ ⎛ ⎞ VT Ic ------⎝ ⎠ ⎛ ⎞ 49.6Ω = = 1 Re re -----Rsig rπ ---------+ + 1 Rsig rπ ---------+ -------------------------------Re re Rsig βac 1 + ----------------+ = Example MS.6.2 continued B.3 Multisim Examples B-87 Thus, Rce Re = 130 . Substituting this value in the equations found for |Av| and Rin shows that Rin increases from 6.1 k to 20.9 k while |Av| drops from 38.2 V/V to 18.8 V/V.
We will now use Multisim to verify our design and investigate the performance of the CE amplifier.
We begin by performing a bias-point simulation to verify that the BJT is properly biased in the active region and that the dc voltages and currents meet the desired specifications. Based on this simulation forward, we have increased the value of RB to 340 k in order to limit IC to about 0.5 mA while using a standard 1% resistor value. Next, to measure the gain Av, we conduct a transient response analysis, as set up in Ch6_CE_Amplifier_Ex.ms10. Accordingly, with no emitter degeneration, the gain is |Av| = 38.5 V/ V. Using Rce = 130 results in a drop in the gain by a factor of 2 (as can be seen from Fig. B.76). Thus far in this example, we have assumed that the voltage gain of the BJT amplifier is constant and independent of the frequency of the input signal. However, as mentioned in Section 4.8.6, this is not true, since it implies that the amplifier has infinite bandwidth. To illustrate the finite bandwidth, we compute the frequency response of the amplifier. The plot of the output-voltage magnitude (in dB) versus fre-quency is shown in Fig. B.77. With no emitter degeneration, the midband gain is |AM| = 38.5 V/V = 31.7 dB and the 3-dB bandwidth is BW = fH – fL = 145.7 kHz. Using an Rce of 130Ω results in a drop in the midband gain |AM| by a factor of 2 (consistent with what we observed previously in our transient analysis).
Interestingly, however, BW has now increased by approximately the same factor as the drop in |AM|. As we learned in Chapter 9, the emitter-degeneration resistor Rce provides negative feedback, which allows us to trade off gain for other desirable properties such as a larger input resistance and a wider bandwidth.
To conclude this example, we will demonstrate the improved bias-point (or dc operating point) sta-bility achieved when an emitter resistor RE is used. Specifically, we will increase/decrease the value of the parameter BF (i.e., the ideal maximum forward current gain) in the SPICE model for part Q2N3904 by a factor of 2 and read the bias-point probes. The corresponding change in BJT parameter (βdc) and bias-point (IC and VCE) are presented in Table B.17 for the case of RE = 6 k . Figure B.76 Transient analysis of the CE amplifier with Rce = 0 and Rce = 130Ω.
Ω Ω Ω Ω Ω 60.0 m 50.0 m 40.0 m 30.0 m 20.0 m Output voltage (V) 10.0 m 0 –10.0 m –20.0 m –30.0 m –40.0 m –50.0 m 0 500.0000 1.0000 m 1.5000 m 2.0000 m Time (s) 2.5000 m Ω B-88 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim For the case without emitter degeneration, we will use RE = 0 in the schematic of Fig. B.75. Further-more, to maintain the same IC and VC in both cases at the values obtained for nominal BF, we use RB = 1.12 M to limit IC to approximately 0.5 mA. The corresponding variations in the BJT bias point are also shown in Table B.17. Accordingly, we see that emitter degeneration makes the bias point of the CE amplifier much less sensitive to changes in β. However, unless a large bypass capacitor CE is used, this reduced bias sensitivity comes at the expense of a reduction in gain (as we observed in this example when we simulated the transient response of the CE amplifier with an Rce = 130 ).
The CMOS CS Amplifier In this example, we will use Multisim to characterize the CMOS CS amplifier whose schematic capture is shown in Fig. B.78. We will assume a 0.18-μm CMOS technology for the MOSFET and use typical SPICE level-1 model parameters for this technology as given in Table B.4. We will begin with an approx-imate hand-analysis design. We will then use Multisim to investigate the performance of the final design.
The targeted specifications for this CMOS CS amplifier are a voltage gain |Gv| = 50 V/V and a bias current ID of 100 μA.
Figure B.77 Frequency response of the CE amplifier with Rce = 0 and Rce = 130 Table B.17 Variations in the Bias Point of the CE Amplifier with the SPICE Model Parameter BF of BJT BF (in SPICE) RE = 6 k RE = 0 dc IC (mA) VC (V) dc IC (mA) VC (V) 208 94.9 0.452 0.484 96.9 0.377 1.227 416.4 (nominal value) 123 0.494 0.062 127 0.494 0.060 832 144 0.518 -0.183 151 0.588 -0.878 35.0 20.0 Magnitude (dB) 5.0 –10.0 1.0000 10.0000 1.0000 k Frequency (Hz) 10.0000 k 100.0000 k 1.0000 M 100.0000 Ω.
Ω Ω Ω Example MS.7.1 Example MS.6.2 continued B.3 Multisim Examples B-89 The amplifier specifications are summarized in Table B.18.
Hand Design For the design of this amplifier we choose L = 0.20 μm, so that similar to Example MS.5.1, we have Leff = 0.18 μm. For this channel length, and in 0.18-μm CMOS technology, the magnitudes of the Early voltages of the NMOS and PMOS transistors are VAn = 12.5 V and |VAp| = 9 V, respectively. Therefore, the value of VOV1 can now be calculated as follows: MOSFET 1 can now be sized (by ignoring the channel-length modulation) as Table B.18 CMOS CS Amplifier Specifications Specification Value ID 100 µA |Gv| 50 V/V VDD 1.8 V Figure B.78 Schematic capture of the CMOS CS amplifier.
VDD VDD 1.8 V M = 9 Q3 I1 100 uA 0.707 mVrms 1000 Hz 0º vIN M = 6 M = 9 1.8 V vOUT Q1 Q2 vin 0.71 V + – NMOS 0.5 V 12.5 V 246.2uA/V^2 0.1 mA 0.2 um 0.523 um –0.5 V 9V –86.1 uA/V^2 0.1 mA 0.2 um 0.46 um PMOS Vtn |VAn| |VAp| kp' kn' I I L L W W Vtp Gv gmRL ′ – gm ro1||ro2 ( ) – 2 VOV1 -----------– VAn VAp VAn VAp --------------------⎝ ⎠ ⎛ ⎞ = = = VOV1 2 Gv ------ VAn VAp VAn VAp --------------------⎝ ⎠ ⎛ ⎞ – 2 50 – ( ) -------------- 12.5 9 × 12.5 9 + -------------------⎝ ⎠ ⎛ ⎞ 0.21V – = = W1 Leff --------ID 1 2 ---k′ nV OV1 2 --------------------100 10 6 – × 1 2 ---246.2 10 6 – 0.21 2 × × × ---------------------------------------------------------- 18.42 = = B-90 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim where, as mentioned, Leff = 0.180 μm, and similar to Example MS.5.1, kn′ = 246.2 μA/V2. This yields W1 = 18.42 Leff = 3.32 μm. To specify the dimensions of the MOSFETs in Multisim, we will use the mul-tiplicative factor m; its default value is 1, and it is used in SPICE to specify the number of MOSFETs con-nected in parallel. As depicted in Fig. B.79, a transistor with channel length L and channel width can be implemented using m narrower transistors in parallel, each having a channel length L and a chan-nel width W. In this example, a unit-size NMOS transistor is used with . Thus, we find Furthermore, MOSFETs 2 and 3 must be sized to have reasonably small VOV for the bias current ID of 100 µA. This allows large signal-swing at the output of the amplifier. Similar to our previous approach, by choosing |VOV2| = 0.3 V, and noting (mid–rail voltage): where Leff = 0.18 μm and This yields In this example, unit-size PMOS transistors are used with Thus, we find .
Simulation Amplifier Biasing Now our design can be verified using the simulation tool. The schematic is in Ch7_CMOS_CS_Amplifier_ Ex_VTC.ms10. Based on the simulation results, |Gv| = 54 V/V and ID = 101 µA. Therefore, the simulation results confirm that the designed CMOS CS amplifier meets the specifications.
DC Voltage Transfer Characteristic To compute the dc transfer characteristic of the CS ampli-fier, we perform a dc analysis in Multisim with VIN swept over the range 0 to VDD and plot the corre-sponding output voltage VOUT. Figure B.80(a) shows the resulting transfer characteristic. The slope of the VTC curve at VGS1 = 0.71 V corresponds to the desired gain of the amplifier. To examine the high-gain region more closely, we repeat the dc sweep for VIN between 0.6 V and 0.8 V. The resulting transfer characteristic is plotted in Fig. B.80b (middle curve). Using the cursor of the Grapher in Multisim, we find that the linear region of this dc trans-fer characteristic is bounded approximately by VIN = 0.698 V and VIN = 0.721 V. The corresponding values of VOUT are 1.513 V and 0.237 V. These results are close to the expected values. Specifically, transistors Q1 Figure B.79 Transistor equivalency.
m W × W1 L1 ⁄ 0.52μm 0.2μm ⁄ = m1 3.32 0.52 ⁄ 6.
= iD iD Aspect ratio of mW/L Aspect ratio of each transistor W/L Q1 Q2 Q3 DDS,2 · VDD 2 ⁄ ( ) 0.9V = W2 Leff --------ID 1 2 --- kp ′ V OV2 2 1 λ2 VDS,2 + ( ) ----------------------------------------------------------------100 10 6 – × 1 2 ---86.1 10 6 – × × 0.3 2 1 0.11 0.9 × + ( ) × × ------------------------------------------------------------------------------------------------- 23.5 = = kp ′ 86.1μA V2.
⁄ = W2 23.5 Leff × 4.23μm.
= = W2 L2 ⁄ W3 L3 ⁄ 0.46μm 0.2μm ⁄ .
= = m2 m3 4.23 0.46 ⁄ 9 = = Example MS.7.1 continued B.3 Multisim Examples B-91 Figure B.80 (a) Voltage transfer characteristic of the CMOS CS amplifier.
Figure B.80 (b) Expanded view of the transfer characteristics in the high-gain region for W = Wnominal ±15%.
2.00 1.25 V(out) 500.00 m –250.00 m 0 500.0 m VIN (V) 1.0 DC transfer characteristic 1.5 2.0 V(v[out]), Traces: 1.850 DC transfer characteristic 1.233 616.667 m VOUT (V) 0 600 m 625 m 650 m 675 m 700 m VIN (V) 725 m 750 m 775 m 800 m W = Wnom +15% W = Wnom –15% W = Wnom, Traces: B-92 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim and Q2 will remain in the saturation region and, hence, the amplifier will operate in its linear region if or From the results above, the voltage gain Gv (i.e., the slope of the linear segment of the dc transfer characteristic) is approximately –54 V/V, which exceeds but is reasonably close to the targeted gain.
Note, from the dc transfer characteristic in Fig. 80(b), that for an input dc bias of VIN = 0.710 V, the output dc bias is VOUT = 0.871 V. This choice of VIN maximizes the available signal swing at the output by setting VOUT at approximately the middle of the linear segment of the dc transfer characteristic.
Using Transient Analysis to Verify Gv This can be done by conducting transient response analy-sis, as set up in Ch7_CMOS_CS_Amplifier_ Ex_gain.ms10. As can be seen from Fig. B.81, |Gv| |Av| 54 V/V.
Sensitivity to Process Variations Because of the high resistance at the output node (or, equiva-lently, because of the high voltage gain), the value of VOUT is highly sensitive to the effect of process and temperature variations on the characteristics of the transistors. To illustrate this point, consider what hap-pens when the width of Q1 (i.e., W1) changes by ±15%. The corresponding dc transfer characteristics are shown in Fig. B.80(b). Accordingly, when VIN = 0.71 V, VOUT will drop to 0.180 V if W1 increases by 15%, and will rise to 1.556 V if W1 decreases by 15%. In practical circuit implementations, this problem is alleviated by using negative feedback to accurately set the dc bias voltage at the output of the amplifier and, hence, to reduce the sensitivity of the circuit to process variations. We studied the topic of negative feedback in Chapter 9.
Figure B.81 Gv of the CMOS CS amplifier (transient analysis).
VOV1 VOUT VDD VOV2 – ≤ ≤ 0.21V VOUT 1.5 V.
≤ ≤ 60 m Transient analysis 40 m 20 m Voltage (V) 0 –20 m –40 m –60 m 0 500.0 1.0 m 1.5 m Time (s) 2.0 m 2.5 m 3.0 m V(v[out])–0.873 V(vin) Traces: Example MS.7.1 continued B.3 Multisim Examples B-93 The Folded-Cascode Amplifier In this example, we will use Multisim to design the folded-cascode amplifier whose schematic capture is shown in Fig. B.82. We will assume a 0.18-μm CMOS technology for the MOSFET and use typical SPICE level-1 model parameters for this technology, excluding the intrinsic capacitance values. We will begin with an approximate hand-analysis design. We will then use Multisim to verify that the designed circuit meets the specifications. The targeted specifications for this folded-cascode amplifier are a dc gain |Gv| = 100 V/V and a bias current ID of 100 μA. Note that while this design does not provide a very high gain, its bandwidth is large (see Chapter 8). The amplifier specifications are summarized in Table B.19.
Hand Design For the design of this amplifier we choose L = 200 μm, so we have Leff = 180 μm. For this channel length, and in 0.18-μm CMOS technology, the magnitudes of the Early voltages of the NMOS and PMOS tran-sistors are VAn = 12.5 V and = 9 V, respectively.
The folded-cascode amplifier in Fig. B.82 is equivalent to the one in Fig. 6.16, except that a current source is placed in the source of the input transistor Q1 (for the same dc-biasing purpose as in the case of the CS amplifier). Note that in Fig. B.82, the PMOS current mirror Q3–Q4 and the NMOS current mirror Q5–Q6 are used to realize, respectively, current sources I1 and I2 in the circuit of Fig. 6.16. Furthermore, the current transfer ratio of mirror Q3–Q4 is set to 2 (i.e., ). This results in ID3 2Iref. Hence, transistor Q2 is biased at .
Figure B.82 Schematic capture of the folded-cascode amplifier.
Table B.19 Folded-Cascode Amplifier Specifications Parameters Value ID 100 µA |Gv| 100 V/V VDD 1.8 V Example MS.7.2 VDD VDD VDD 1.8 V 1.8 V 1.8 V M = 10 M = 5 M = 5 M = 5 M = 10 M = 10 M = 10 VDD 1.8 V vOUT Iref4 100uA CLoad 500 fF IC = 0 V Q4 Q1 Q6 Q5 Q2 Q8 Q7 M = 20 Q3 Iref 100 A Vsig IVac Ire f2 100uA Cs 10 F IC = 0 V Iref3 100uA 0.75 V Rsig 100 NMOS 0.5 V 12.5 V 246.2uA/V^2 0.1 mA 0.2 um 0.48 um –0.5 V 9V –86.1 A/V^2 0.1 mA 0.2 um 0.64 um PMOS Vtn |VAn| |VAp| kp' kn' IREF IREF L L W W Vtp VAp m3 m4 ⁄ 2 = ID2 ID3 ID1 – – Iref = B-94 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The overall dc voltage gain of the folded-cascode amplifier under design can be expressed by using Eq. (6.22) as where is the output resistance of the amplifier. Here, Rout2 is the resistance seen looking into the drain of the cas-code transistor Q2, while Rout5 is the resistance seen looking into the drain of the current mirror transistor Q5. Using Eq. (6.25), we have where is the effective resistance at the source of Q2. Furthermore, Thus, for the folded-cascode amplifier in Fig. B.82, and Therefore, based on the given information, the value of VOV1 can be determined: The gate bias voltage of transistor Q2 is generated using the diode-connected transistors Q7 and Q8.
The size and drain currents of these transistors are set equal to those of transistor Q2. Therefore, ignoring the body effect, where VOV,P is the overdrive voltage of the PMOS transistors in the amplifier circuit. Thus, such a biasing configuration results in as desired, while setting to improve the bias matching between Q3 and Q4. For this example, all transistors are sized for an overdrive voltage of 0.25 V. Also, to simplify the design procedure, we ignore the channel-length modulation effect. As a result, using unit-size NMOS transistors with and unit-size PMOS transistors with the corre-sponding multiplicative factor m for each transistor can be calculated by rounding to the nearest integer the value of m: Gv gm1Rout – = Rout Rout2 || Rout5 = Rout2 gm2ro2 ( )RS2 RS2 ro1 || ro3 ( ) = Rout5 ro5 = Rout ro5 Gv gm1ro5 – 2 VAn VOV1 -----------– = = Vov1 2VAn Gv ---------212.5 100 ----------0.25V = = = VG,2 VDD VSG,7 – VSG,8 – VDD 2 Vtp VOV,P + ( ) – = = VSG,2 Vtp VOV,P + 0.5 0.25 + 0.75V = = = VSD 3 , Vtp VOV,P + 0.75V = = Wn Ln ⁄ 0.48 μm 0.2 μm, ⁄ = Wp Lp ⁄ 0.64 μm 0.2 μm, ⁄ = m ID 1 2 ---k′ W Leff ----------⎝ ⎠ ⎛ ⎞VOV 2 -----------------------------------= Example MS.7.2 continued B.3 Multisim Examples B-95 Table B.20 summarizes the relevant design information and the calculated m values for each transistor.
Simulation Verifying Gv Now our design can be verified by reading probes or conducting transient response anal-ysis, as set up in Ch7_Folded_Cascode _ Ex.ms10. Based on the simulation results, |Gv| = 102 V/V (Fig B.83) and ID1 = ID2 = 100 μA. Therefore, the simulation results confirm that the designed folded-cascode amplifier meets the specifications.
Sensitivity to Channel Length Modulation In the hand design of this example, the channel-length modulation effect was ignored (except for the role of ro5 in determining the gain). However, the simulation took the finite ro of each transistor into account. Furthermore, one can investigate the effect of changes in the Early voltages by modifying the value of lambda for each transistor in the design.
Table B.20 Transistor Sizes Transistor ID (µA) VOV (V) W (µm) Leff (µm) K (µA/V2) m 1 100 0.25 0.48 0.18 246.2 5 2 100 0.25 0.64 0.18 86.1 10 3 200 0.25 0.64 0.18 86.1 20 4 100 0.25 0.64 0.18 86.1 10 5 100 0.25 0.48 0.18 246.2 5 6 100 0.25 0.48 0.18 246.2 5 7 100 0.25 0.64 0.18 86.1 10 8 100 0.25 0.64 0.18 86.1 10 Figure B.83 Gv of the folded-cascode amplifier (transient analysis).
104 m Transient analysis 69 m 35 m 0 Voltage (V) –35 m –69 m –104 m 0 500.0 1.0 m 1.5 m Time (s) 2.0 m 2.5 m 3.0 m V(in) V(out) Traces: B-96 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The Two-Stage CMOS Op Amp In this example, we will design the two-stage CMOS op amp whose schematic capture is shown in Fig.
B.84. Once designed, the circuit’s characteristics, such as the input common-mode range, the common-mode rejection ratio, the output-voltage range, and the input offset voltage will be evaluated. The first stage is differential pair Q1–Q2 (which is actively loaded with the current mirror formed by Q3 and Q4), with bias current supplied by the current mirror formed by Q8, and Q5, which utilizes the refer-ence bias current IREF. The second stage consists of Q6, which is a common-source amplifier actively loaded with the current source transistor Q7.
For the design of this CMOS op amp, we will assume a 0.18-µm CMOS technology for the MOSFETs and use typical SPICE level-1 model parameters for this technology, excluding the intrinsic capacitance values. We will begin with an approximate hand-analysis design. We will then use Multisim to verify that the implemented circuit meets the specifications. The targeted specifications for this op amp are a dc open-loop voltage gain |Av| = 2500 V/V, with each of transistors Q1, Q2, Q3, and Q4 conducting a drain current of 100 µA.
To achieve the targeted specifications, a biasing current IREF = 200 µA is used, and the transistors Q5, Q6, Q7, and Q8 will be sized so that they conduct the drain current of 200 µA. Also, the open-loop voltage gain for this design is the product of the voltage gains of the two stages. Accordingly, each stage is designed to contribute a voltage gain of –50 V/V, so as to achieve the specified open-loop voltage gain.
The amplifier specifications are summarized in Table B.21.
Figure B.84 Schematic capture of the two-stage CMOS op amp.
Example MS.8.1 Q1 Q2 Q3 Q4 Q6 IREF 200 uA Q8 Q5 Q7 VDD 1.0 V VSS –1.0 V VDD 1.0 V VDD 1.0 V VDD 1.0 V VSS –1.0 V VSS –1.0 V NMOS Vtn |VAn| kn' IREF L W 0.5 V 12.5V 246.2A/V^2 0.2mA 0.2 um 0.48 um PMOS Vtp |VAp| kp' IREF L W –0.5 V 9V –86.1 A/V^2 0.1mA 0.2 um 0.64 um vOUT B.3 Multisim Examples B-97 Hand Design For the design of this amplifier we choose L = 0.200 μm, so we have Leff = 0.180 μm.
For this channel length, and in 0.18-μm CMOS technology, the magnitudes of the Early voltages of the NMOS and PMOS transistors are VAn = 12.5 V and |VAp| = 9 V.
The two-stage CMOS op amp in Fig. B.84 is equivalent to the one in Fig. 7.41, except that the first stage is an NMOS differential amplifier and the second stage is a PMOS common source. Note that the differential voltage gain of the first stage can be expressed using Eq. (7.176) as: Hence, resulting in Also, the voltage gain of the second stage is provided by Eq. (7.177) as Therefore, resulting in For this example, all transistors are sized for an overdrive voltage of 0.21 V. Furthermore, to simplify the design procedure, we ignore the channel-length modulation effect. As a result, using unit-size NMOS transistors with and unit-size PMOS transistors with , the corresponding multiplicative factor m for each transistor can be calculated by round-ing to the nearest integer value which is calculated as m: Table B.22 summarizes the relevant information and the calculated m values for each transistor.
Table B.21 Two-Stage CMOS Op-Amp Specifications Parameter Value I(Q1, Q2, Q3, and Q4) 100 µA I(Q5, Q6, Q7, and Q8) 200 µA |A1| 50 V/V |A2| 50 V/V VDD 1 V VSS –1 V A1 gm1 ro2 || ro4 ( ) – = A1 2 VOV1 -----------– VAn VAp VAn VAp + --------------------------⎝ ⎠ ⎛ ⎞ = VOV1 2 A1 -----– VAn VAp VAn VAp + --------------------------⎝ ⎠ ⎛ ⎞ 2 50 – ( ) --------------– 12.5 9 × 12.5 9 + -------------------⎝ ⎠ ⎛ ⎞ 0.21V = = A2 gm6 ro6 || ro7 ( ) – = A2 2 VOV6 -----------– VAn VAp VAn VAp + --------------------------⎝ ⎠ ⎛ ⎞ = VOV6 2 A2 -----– VAn VAp VAn VAp + --------------------------⎝ ⎠ ⎛ ⎞ 2 50 – ( ) --------------– 12.5 9 × 12.5 9 + -------------------⎝ ⎠ ⎛ ⎞ 0.21V = = Wn Ln ⁄ 0.64 μm 0.2 μm, ⁄ = Wn Ln ⁄ = 0.48μm 0.2μm ⁄ m ID 1 2 ---k′ W Leff --------⎝ ⎠ ⎛ ⎞VOV 2 ---------------------------------= B-98 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Simulation Verifying Av Now our design can be verified by reading probes, as set up in Ch8_ Two_Stage_Op_ Amp_Ex.ms10. Based on the simulation results we read |A1| = 57 V/V, |A2| = 58.6 V/V, |Av| = 3340 V/V, I(Q1, Q2, Q3, and Q4) = 97 μA, IQ5 = 194 μA, I(Q6, Q7) = 202 μA, and IQ8 = 200 μA. These values are somewhat different from the targeted specifications. The deviations can be attributed to the fact that we rounded the values of m to the nearest integer and ignored the effect of channel-length modulation, that is, the term (1 + VDS), when calculat-ing the multiplicative factor. To get closer to our targeted specifications, we may use the obtained VDS values for each transistor, from the original design, to estimate new multiplicative factor values by taking the term (1 + VDS) into account. Table B.23 shows the revised multiplicative factor values.
The revised design is evaluated by reading probes, as set up in Ch8_Two_Stage_Op_Amp_revised_ Ex.ms10. The simulation results show |A1| = 54 V/V, |A2| = 58.2 V/V, |Av| = 3145 V/V, I(Q1, Q2, Q3, and Q4) = 103 µA, IQ5 = 206 µA, I(Q6, Q7) = 205 µA, and IQ8 = 200 µA, from which we see that the voltage gains are closer to the targeted specifications. One should note that the discrepancies between the hand-design and simulation results in this simula-tion example are more apparent because errors in each stage add up.
Next, we will explore some important characteristics of the designed two-stage CMOS op amp.
Input Common-Mode Range The upper limit of the input common-mode range is the value of input voltage at which Q1 and Q2 leave the saturation region. This occurs when the input voltage exceeds Table B.22 Transistor Sizes Transistor ID (µA) VOV (V) W (µm) Leff (µm) k′ (µA/V2) m 1 100 0.21 0.48 0.18 246.2 7 2 100 0.21 0.48 0.18 246.2 7 3 100 0.21 0.64 0.18 86.1 15 4 100 0.21 0.64 0.18 86.1 15 5 200 0.21 0.48 0.18 246.2 14 6 200 0.21 0.64 0.18 86.1 30 7 200 0.21 0.48 0.18 246.2 14 8 200 0.21 0.48 0.18 246.2 14 Table B.23 Revised Transistor Multiplicative Factors Transistor m 1 6 2 6 3 14 4 14 5 13 6 26 7 13 8 13 λ λ Example MS.8.1 continued B.3 Multisim Examples B-99 the drain voltage of Q1 by Vtn = 0.5 V. Since the drain of Q1 is at 1 – (0.21 + 0.5) = 0.29 V, then the upper limit of the input common-mode range is The lower limit of the input common-mode range is the value of input voltage at which Q5 leaves the saturation region. Since for Q5 to operate in saturation the voltage across it (i.e., VDS5) should at least be equal to the overdrive voltage at which it is operating (i.e., 0.21 V), the highest voltage permitted at the drain of Q5 should be –0.79 V. It follows that the lowest value of vICM should be To verify the results using the simulation tool, we swept the input common-mode voltage vICM from – 1 V to 1 V and plotted the resulting vGD of Q1 and Q5 (as set up in Ch8_Two_Stage_Op_Amp_ Ex_CM_Range.ms10). As can be seen from Fig. B.85, both transistors Q1 and Q5 stay in saturation for the input common-mode range of as indicated by cursors.
Common-Mode Rejection Ratio (CMRR) of the First Stage The value of the CMRR of the first stage (the active-loaded MOS differential amplifier) is determined from Eq. B.147. Note that the value of RSS in the provided equation corresponds to the output resistance of Q5 (i.e., ro5). Thus, Using the simulation tool, the value of CMRR is calculated by dividing the previously obtained A1 value (54 V/V) by the common-mode gain of the first stage as measured in Ch8_Two_Stage_Op_Amp_ Ex_CMRR.ms10. This yields Output Voltage Range The lowest allowable output voltage is the value at which Q7 leaves the sat-uration region, which is The highest allowable output voltage is the value at which Q6 leaves saturation, which is Thus, the output-volt-age range is –0.79 V to 0.79 V.
As set up in Ch8_Two_Stage_Op_Amp_Ex_Output_Range.ms10, to verify the calculated output volt-age range, we swept the input voltage from –2 mV to 2 mV (we used a small input voltage due to high Figure B.85 Input common–mode range of the two-stage CMOS op amp.
1.0 500.0 m 0 –500.0 m –1.0 VGD of Q and Q5 (V) –1.5 –2.0 –500 m 0 vv1 Voltage (V) 500 m –1 Q1 leaves saturation Q5 leaves saturation vICMmax 0.29 0.5 + 0.79V.
= = vICMmin 0.08 V.
– = 0.08 V vICM 0.79 V, ≤ ≤ – CMRR A1 Acm -----------≡ 50 1 2gm3ro5 ⁄ --------------------------100gm3ro5 100 2 100 10 6 – × × 0.21 ------------------------------------ 12.5 200 10 6 – × -------------------------5952.4 75.5 dB = = = = = CMRR A1 Acm -----------≡ 54 78 10 3 – × ----------------------6923 76.8 dB = = = VSS – VOV7 + 1 – 0.21 + 0.79 V.
= = VDD V – OV6 – 1 0.21 – 0.79 V.
= = B-100 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim gain). As can be seen from Fig. B.86, the output level changes from –0.795 V to 0.784 V, a rather sym-metrical range. Therefore, the simulation results confirm our hand-analysis calculations. Input Offset Voltage Although, theoretically, there should be no systematic offset, we do observe an output offset voltage Vo. As defined by Eq. 7.102, the input offset voltage, VOS, can be obtained as Figure B.86 Output-voltage range of the two-stage CMOS op amp.
Figure B.87 Input offset voltage of the two-stage CMOS op amp.
1.0 Output voltage swing 500.0 m –500.0 m –1.0 –1.5 –2 m –1 m 0 vvin Voltage (V) 1 m 0 Voltage (V) Output Swing VOS VO Av ------= 1.0 Input offset of the op amp 500.0 m –500.0 m Voltage (V) –1.0 –1.5 –750 –375 –375 0 vvin voltage (V) 0 Input Offset Example MS.8.1 continued B.3 Multisim Examples B-101 Equivalently, if we apply a voltage –VOS between the input terminals of the differential amplifier, the output voltage should be reduced to zero. This equivalency can be verified using the simulation tool (Ch8_Two_Stage_Op_Amp_Ex_Output_Range.ms10). When both the input terminals are grounded, the probe at the output reads the dc voltage 0.574 V. Also, when we apply the voltage , between the input terminals, the output voltage is reduced to zero (Fig.
B.87). Hence, the op amp has an input offset voltage of VOS = 195 µV, which approximately corresponds to an output offset voltage of VO = 0.574 V.
Frequency Response of the Discrete CS Amplifier In this example, we will investigate the frequency response of the CS amplifier of Example MS.5.1. By using Multisim to perform “ac analysis” on the designed CS amplifier, we are able to measure the mid-band gain AM and the 3-dB frequencies fL and fH, and to plot the output-voltage magnitude (in dB) versus frequency. Figure B.88 shows the schematic capture of the CS amplifier.
Hand Analysis Midband Gain The midband gain of this CS amplifier can be determined using Eq. (8.9) as follows: Figure B.88 Schematic capture of discrete CS amplifier.
VOS 0.574 3145 ⁄ ( ) 183μV = Example MS.9.1 NAME W L KP LD VT0 LAMBDA GAMMA DEVICE PARAMETERS Q1:NMOS 15.48u 0.2u 0.01u 0.45 0.08 0.3 246u RG1 852.5 k RD1 3.41 k RG2 947.5 k RL1 50 k Rsig1 10 k CCI1 10 µF CCO1 10 µF CS1 10 µF VDD 1.8 V VDD 1.8 V V1 0.707 mVrms 1 kHz 0˚ RS1 1.39 k vout Q1 AM Rin Rin Rsig + ---------------------- gm RD||RL ( ) [ ] = Rin RG1||RG2 ( ) 852.5 10 3 × || 947.5 10 3 × 448.75 10 3 × Ω = = = gm 3.33 mA/V = AM 448.75 103 × 448.75 10 3 10 10 3 × + × --------------------------------------------------------- 3.33 10 3 – × 3.41 10 3||50 10 3 × × ( ) [ ] 10 V/V = B-102 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Low-Frequency Poles and Zero We know from Section 8.1.1 that the low-frequency poles are as follows: And the location of the real transmission zero is determined as Upon observing the relative magnitude of each of the poles, we can conclude that fP3 will determine fL, the lower 3-dB frequency of the amplifier gain, fL fP3 11.45 Hz High-Frequency Rolloff The high-frequency rolloff of the amplifier gain is caused by the MOSFET internal capacitance. The typical values for 0.180 µm CMOS technology are given in Table B.4. We know from Eq. (8.54) in Section 8.3.1 that Note that Cgs0 and Cgd0 are per-unit-width values provided in the models.
Now we can determine the bandwidth, BW, of the CS amplifier: BW = fH – fL BW fH = 191 MHz Simulation Figure B.89 shows the magnitude plot of the frequency response of this CS amplifier.
Based on the simulation results, the midband gain is AM = 9.80 V/V. Also, fL = 60.8 Hz and fH = 192.2 MHz, resulting in 3-dB bandwidth of BW = fL – fH = 192.2 MHz. Figure B.89 further shows that fP1 1 2π CCI Rsig Rin + ( ) × -------------------------------------------------1 2π 10 10 6 – 10 103 × ( ) 448.75 103 × + [ ] × × -------------------------------------------------------------------------------------------------------= = fP1 0.0347 Hz = fP2 1 2π CCO RD RL + ( ) × -----------------------------------------------1 2π 10 10 6 – 3.41 10 3 × ( ) 50 10 3 × ( ) + × × -------------------------------------------------------------------------------------------------= = fP2 0.30 Hz = fP3 1 2π CS × -------------------gm 1 RS -----+ ⎝ ⎠ ⎛ ⎞ 1 2π 10 10 6 – × × -----------------------------------3.33 10 3 – × ( ) 1 1.39 10 3 × -------------------------+ = = fP3 64.4 Hz = fZ 1 2π CSRS × -------------------------1 2π 10 10 6 – × ( ) 1.39 103 × ( ) × ----------------------------------------------------------------------= = fZ 11.45 Hz = fH 1 2π CinR′ sig × ------------------------------= R′ sig 10 10 3 × ||448.75 10 3 × 9.78 10 3 × = = Cin W Cgs0 Cgd0 1 gm RL||RL ( ) + [ ] + { } = Cin 15.48 10 6 – × ( ) 0.3665 10 9 – × ( ) × 1 1 3.33 + 10 3 – 50 10 3 || 3.41 10 3 – × × ( ) × + [ ] × = Cin 0.716 fF = fH 1 2π 0.716 10 15 – 9.78 10 3 × × × × ----------------------------------------------------------------------------= fH 191 MHz Example MS.9.1 continued B.3 Multisim Examples B-103 (moving toward the left) the gain begins to fall off at about 300 Hz, but flattens out again at about 12.2 Hz. This flattening in the gain at low frequencies is due to a real transmission zero introduced in the transfer function of the amplifier by RS together with CS, with a frequency fZ – =1/2πRSCS = 11.45 Hz. Stu-dents are encouraged to investigate this relationship by using the simulation tool to modify the values of RS and CS and observing the corresponding change in the zero frequency. Note this value of zero is typi-cally between the break frequencies fP2 and fP3. The simulation is set up in Ch9 _CS_Amplifier_Ex.ms10. We can further verify this phenomenon by resimulating the CS amplifier with a CS = 0 (i.e., removing CS) in order to move fZ to infinity and remove its effect. The corresponding frequency response is plotted in Fig. B.90. As expected with CS = 0, we do not observe any flattening in the low-frequency response of the amplifier. However, because the CS amplifier now includes a source resistor RS, the value of AM has dropped by a factor of 5.4. This factor is approximately equal to (1 + gmRS), as expected from our Figure B.89 Frequency response of the CS amplifier.
Figure B.90 Frequency response of the CS amplifier with CS = 10 µF and CS = 0.
30 20 10 –10 –20 –30 –40 10 m 1 100 10 k Frequency (Hz) 1 M 100 M 10 G 0 Magnitude fP1 fP2 fH fz fP2 = fL 30.0 20.0 10.0 10.0 20.0 30.0 40.0 10.0 m 1.0 100.0 10.0 k Frequency (Hz) 1.0 M 100.0 M 10.0 G 0 Magnitude B-104 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim study of the CS amplifier with a source-degeneration resistance. Note that the bandwidth BW has increased by approximately the same factor as the drop in gain AM. As we learned in Chapter 9 in our study of negative feedback, the source-degeneration resistor RS provides negative feedback, which allows us to trade off gain for a wider bandwidth.
The Frequency Response of CMOS CS Amplifier and the Folded-Cascode Amplifier In this example, we will investigate the frequency response of the CMOS CS amplifier and the folded-cascode amplifier studied in Examples MS.7.1 and MS.7.2. The circuit diagram of the CMOS CS ampli-fier is given in Fig. B.91. By using Multisim to perform “ac analysis” on the designed CMOS CS amplifier, we are able to mea-sure the midband gain AM and the 3-dB frequency fH, and to plot the output-voltage magnitude (in dB) ver-sus frequency for two different cases of Rsig (100 and 1 M ), as shown in Fig. B.92.
Observe that fH decreases when Rsig is increased. This is anticipated from our study of the high-frequency response of the CS amplifier. Specifically, as Rsig increases, the pole formed at the amplifier input will have an increasingly significant effect on the overall frequency response of the amplifier. As a result, the effective time constant H increases and fH decreases. When Rsig becomes very large, as it is when Rsig = 1 MΩ, a dominant pole is formed by Rsig and Cin. This results in To estimate fp,in, we need to calculate the input capacitance Cin of the amplifier. Using Miller’s theo-rem, we have where The value of Cin can be calculated by using the overlap capacitances Cgs,ov1 and gate-to-channel Cgs and Cgd,ov1 as follows: For Cgs, we write This results in Cin = 45.78 fF when |Gv| = 50 V/V. Accordingly, which is close to the value computed by Multisim (i.e., fH = 3.66 MHz).
Example MS.9.2 Ω Ω fp,in 1 2π ------1 RsigCin ----------------= τ fH fp,in Cin Cgs1 Cgd1 1 gm1R′ L + ( ) + = R′L ro1 || ro2 = Cgs ov1 , m1W1CGSO 5 0.48 10 6 – × × ( ) 0.3665 10 9 – × ( ) × 0.880 fF = = = Cgd ov1 , m1W1CGDO 5 0.48 10 6 – × × ( ) 0.3665 10 9 – × ( ) × 0.880 fF = = = Cgs_channel 2 3 ---m1W1LCox 2 3 ---5 0.48 10 6 – × × ( ) 0.18 10 6 – × ( ) 3.9 8.85 10 12 – × × 4.08 10 9 – × -------------------------------------------⎝ ⎠ ⎛ ⎞ × = = Cgs_channel 2.48 fF = Cgs 2.48 fF 0.880 fF + 3.36 fF = = fH 1 2π ------1 1 106 43.3 10 15 – × × × -----------------------------------------------------3.48 MHz = Example MS.9.1 continued B.3 Multisim Examples B-105 Figure B.91 Schematic capture of the CMOS CS amplifier.
Figure B.92 Frequency response of the CMOS CS amplifier with Rsig = 100 Ω and Rsig = 1 MΩ.
Iref 100 uA Rsig 100 Vsig 1 Vac CS 1F VDD 1.8 V VDD 1.8 V Q4 M = 10 Q3 M = 10 Q1 M = 5 NMOS Vtn |VAn| kn' IREF L W 0.5 V 12.5V 246.2uA/V^2 0.1mA 0.2 um 0.48 um PMOS Vtp |VAp| kp' IREF L W –0.5 V 9V –86.1 uA/V^2 0.1mA 0.2 um 0.64 um Iref2 100 uA vout 40.0 10.0 –20.0 Magnitude (dB) –50.0 1.0 100.0 10.0 k Frequency (Hz) 1.0 M 100.0 M 10.0 G B-106 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The Folded-Cascode Amplifier Next, we will investigate the frequency response of the folded-cascode amplifier and compare its performance with that of the CS amplifier. Figure B.93 shows the cir-cuit diagram of the folded-cascode amplifier.
Figure B.94 shows the frequency response of the folded-cascode amplifier as simulated by Multisim for the cases of Rsig = 100Ω and 1 MΩ. The corresponding values of the 3-dB frequency fH of the amplifier are given in Table B.24.
Figure B.93 Schematic capture of the Folded-Cascode amplifier.
Figure B.94 Frequency response of the folded-cascode amplifier with Rsig = 100 Ω and Rsig = 1 MΩ.
Iref 100uA Rsig 1 M Vsig 1V ac CS 1F IC = 0 V Iref3 100uA Iref4 100uA VDD 1.8 V VDD 1.8 V VDD 1.8 V VDD 1.8 V M = 10 Q7 M = 10 Q4 M = 20 Q3 M = 5 Q1 M = 5 Q5 M = 5 Q6 M = 10 Q2 M = 10 Q8 NMOS Vtn |VAn| kn' IREF L W 0.5 V 12.5V 246.2uA/V^2 0.1mA 0.2 um 0.48 um PMOS Vtp |VAp| kp' IREF L W –0.5 V 9V –86.1 uA/V^2 0.1mA 0.2 um 0.64 um Iref2 100uA VOUT 50.0 30.0 10.0 –10.0 Magnitude (dB) –30.0 –50.0 1.0 100.0 10.0 k Frequency (Hz) 1.0 M 100.0 M 10.0 G Example MS.9.2 continued B.3 Multisim Examples B-107 First, note that for the designed folded-cascode amplifier, Rout = 125 k and |Gv| = 100 V/V. Thus, Rout and Gv are larger than those of the CS amplifier (by a factor of 2). Note that these calculations can be found in Examples MS.7.1 and MS.7.2.
Also, observe that when Rsig is small, fH of the folded-cascode amplifier is lower than that of the CS amplifier by a factor of about 1.8, approximately equal to the factor by which the gain is increased. This is because when Rsig is small, the frequency response of both amplifiers is dominated by the pole formed at the output node, that is, Now the output resistance of the folded-cascode amplifier is larger than that of the CS amplifier, while their output capacitances are approximately equal. Therefore, the folded-cascode amplifier has a lower fH in this case.
On the other hand, when Rsig is large, fH of the folded-cascode amplifier is much higher than that of the CS amplifier. This is because in this case, the effect of the pole at fp,in on the overall frequency response of the amplifier becomes dominant. Since, owing to the Miller effect, Cin of the CS amplifier is much larger than that of the folded-cascode amplifier, its fH is much lower.
To confirm this point, observe that Cin of the folded-cascode amplifier can be estimated by replacing in the equation used to compute Cin for the CS amplifier, with the total resistance Rd1, between the drain of Q1 and ground. Here, where Rin2 is the input resistance of the common-gate transistor Q2 and can be obtained using an approxi-mation of the relationship found for input resistance of the common-gate amplifier: Thus, Therefore, Rd1 is much smaller than (in the CS amplifier ro1 || ro3). Hence, Cin of the designed folded-cascode amplifier is indeed much smaller than that of the CS amplifier because the (1 + gmR') multiplier is smaller for the folded-cascode device. This confirms that the folded-cascode amplifier is much less impacted by the Miller effect and, therefore, can achieve a much higher fH when Rsig is large.
The midband gain of the folded-cascode amplifier can be significantly increased by replacing the cur-rent mirror Q5–Q6 with a current mirror having a larger output resistance, such as the cascode current mir-ror in Fig. 6.32, whose output resistance is approximately gmro 2. In this case, however, Rin2 and, hence, Rd1 increase, causing an increased Miller effect and a corresponding reduction in fH.
Finally, it is interesting to observe that the frequency response of the folded-cascode amplifier shown in Fig. B.94 drops beyond fH at approximately –20 dB/decade when Rsig = 100 and at approximately –40 dB/decade when Rsig = 1M . This is because when Rsig is small, the frequency response is dominated by the pole at fp,out. However, when Rsig is increased, fp,in is moved closer to fp,out, and both poles contribute to the gain falloff.
Table B.24 Dependence of fH for the Designed Amplifiers Rsig fH CS Amplifier Folded-Cascode Amplifier 100 510.7 MHz 296.2 MHz 1 M 3.39 MHz 24.0 MHz Ω Ω Ω fH fp out , 1 2π ------1 RoutCout -------------------= R′ L Rd1 r01 || r03 || Rin2 = Rin2 ro2 r + o5 gm2ro2 --------------------Rd1 ro1 || ro3 || ro2 r + o5 gm2ro2 --------------------2 gm2 --------= R′ L Ω Ω B-108 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim A Two-Stage CMOS Op Amp with Series–Shunt Feedback In this example, we will investigate the effect of applying a series–shunt feedback to the two-stage CMOS op amp whose schematic capture is shown in Fig. B.95. The first stage is a differential pair Q1–Q2 (which is actively loaded with the current mirror formed by Q3 and Q4) with bias current supplied by a current mirror formed by Q8 and Q5, which utilizes the refer-ence bias current IREF. The second stage consists of Q6, which is a common-drain amplifier actively loaded with a current source load (transistor Q7).
For the implementation of this CMOS op amp, we will use a 0.18-µm CMOS technology for the MOSFETs and typical SPICE level-1 model parameters for this technology, including the intrinsic capacitance values. The targeted specifications are an unloaded dc open-loop voltage gain |Av| = 50 V/V, and closed-loop voltage gain |Af| = 10 V/V, with each of transistors Q1, Q2, Q3, and Q4 biased at a drain current of 100 µA.
To achieve the targeted specifications, a biasing current IREF = 200 µA is used, and the transistors Q5, Q6, Q7, and Q8 will be sized to conduct drain currents of 200 µA. The dc open-loop voltage gain for this amplifier is the product of the voltage gains of the two stages. Since the gain of the second stage (source follower) is approximately 1 V/V, the first stage must be designed to provide the full voltage gain of 50 V/V to achieve the specified open-loop voltage gain.
The amplifier specifications are summarized in Table B.25.
Figure B.95 Schematic capture of the two-stage CMOS op amp.
Example MS.10.1 VDD VDD VDD VDD 1 V 1REF 200 μA Q3 Q1 Q2 Q5 Q8 Q4 1 V 1 V Q6 Q7 vOUT VSS –1 V –1 V –1 V VSS VSS 1 V vid 0.707μVrms 1 MHz 0º NMOS Vtn |VAn| kn' L W 0.5 V 12.5V 246.2uA/V^2 0.2 um 0.48 um PMOS Vtp |VAp| kp' L W –0.5 V 9V –86.1 µA/V^2 0.2 um 0.64 um B.3 Multisim Examples B-109 Hand Design Design of the Two-Stage Op Amp The first stage of this CMOS op amp is identical to the first stage of the op amp we designed in Example MS.8.1, to which the reader is referred. Also, tran-sistors Q6 and Q7 are sized to provide the bias current of 200 µA in the second stage.
As a result, using unit-size NMOS transistors with and unit-size PMOS transistors with the corresponding multiplicative factor m for each transistor can be calculated as found in Example MS.8.1 (with the difference here that Q6 and Q7 have the same dimen-sions). Table B.26 summarizes the relevant information and the calculated m values for the transistor.
Design of the Feedback Network First we need to determine the value of the feedback factor β for this series–shunt feedback amplifier. The β network can be implemented using a voltage divider, as shown in Fig. B.96. The resistor values are chosen large enough (in comparison to the output resistance of the designed two-stage op amp) to minimize the effect of loading. Therefore, effectively, where A is the open-loop gain of the amplifier (with loading). Now we can calculate the required feed-back factor, β, as follows: Table B.25 Two-Stage CMOS Op-Amp Specifications Parameters Value I(Q1, Q2, Q3, and Q4) 100 µA I(Q5, Q6, Q7, and Q8) 200 µA |A1| 50 V/V |A2| 1 V/V |Af| 10 V/V VDD 1 V VSS –1 V Table B.26 Transistor Sizes Transistor ID (µA) m 1 100 6 2 100 6 3 100 14 4 100 14 5 200 13 6 200 13 7 200 13 8 200 13 Wn Ln ⁄ 0.48 μm 0.20 ⁄ μm, = Wp Lp ⁄ 0.64 μm 0.20 ⁄ μm, = A Av Af Av 1 Avβ + ------------------50 1 50β + -------------------10V/V = = = β 0.08 = B-110 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The resistor values of this voltage divider are selected to provide voltage divisions of 0.08 (R1 = 92 k and R2 = 8k Simulation Now we will simulate our designed circuit to verify our hand design and study the effect of feedback on the dc-gain, bandwidth, and output resistance of the amplifier.
Verifying Av The schematic capture of the two-stage CMOS amplifier is in Fig. B.95. We can verify the dc voltage gain of this amplifier by performing frequency-response analysis as set up in Ch10_OpAmp_Ex_Av.ms10.
As can be seen from Fig. B.97, |Av| = 35.0 dB 56.2 V/V, which is close to the targeted specification.
Verifying A The schematic capture of the A-circuit is given in Fig. B98.
Figure B.96 β Network.
Figure B.97 Frequency response of the two–stage CMOS op-amp amplifier.
Ω Ω).
vOUT negative_input R1 92 k R2 8 k 40 AC analysis 30 20 Magnitude Phase (deg) 10 0 25 –25 –75 1M 10M 100M Frequency (Hz) 1G –100 –125 –50 0 1 M 10 M 100 M Frequency (Hz) 1 G Example MS.10.1 continued B.3 Multisim Examples B-111 We can verify the open-loop voltage gain of this circuit by performing a frequency-response analysis as set up in Ch10_OpAmp_Ex_A.ms10. As can be seen from Fig. B.99, |A| = 34.9 dB 55.6 V/V, which is close to the value of Av. This supports our assumption of Verifying Af The schematic capture of the closed-loop circuit is given in Fig. B.100. As can be seen from this schematic, the β-network establishes a series connection at the input and a shunt connection at the output of the original two-stage CMOS op amp.
Figure B.98 Schematic capture of the A circuit.
Figure B.99 Schematic capture of the A- circuit.
VDD 1 V 1 V 1 V 1 V Q3 Q8 VSS VSS VSS –1 V –1 V –1 V Q1 R1 8 k R3 R2 92 k R4 8 k 92 k Q5 Q7 0.707uVrms 1 MHz 0˚ vid Q2 Q6 vOUT Q4 IREF 200 uA VDD VDD VDD NMOS Vtn |VAn| kn' L W 0.5 V 12.5V 246.2µA/V^2 0.2 um 0.48 um PMOS Vtp |VAp| kp' L W –0.5 V 9V –86.1 uA/V^2 0.2 um 0.64 um A Av.
40 AC analysis 30 20 10 –10 1 M 25 0 –25 –50 –75 –100 Phase (deg) Magnitude –125 –155 10 M 100 M Frequency (Hz) Frequency (Hz) 1 G 1 M 10 M 100 M 1 G 0 B-112 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim We can verify the closed-loop voltage gain by performing a frequency-response analysis as set up in Ch10_OpAmp_Ex_Af.ms10. As can be seen from Fig. B.101, |Af| = 20.2 dB 10.2 V/V, which is close to the targeted specification for Af .
Figure B.100 Schematic capture of the closed-loop circuit.
Figure B.101 Frequency response of the closed-loop circuit.
VDD VDD VDD VDD Q3 Q4 Q1 Q2 Q6 vOUT vid R1 R2 8 k 92 k Q5 Q7 Q8 VSS VSS VSS –1 V –1 V –1 V 0.707uVms 1 MHz 0˚ 1 V 1 V 1 V 1 V IREF 200 uA NMOS Vtn |VAn| kn' L W 0.5 V 12.5V 246.2uA/V^2 0.2 um 0.48 um PMOS Vtp |VAp| kp' L W –0.5 V 9V –86.1 uA/V^2 0.2 um 0.64 um 25 AC analysis 10 Magnitude –5 –20 1 M 25 –25 Phase (deg) –50 –75 –100 –125 –150 1 M 0 10 M 100 M 1 G Frequency (Hz) 10 M 100 M 1 G Frequency (Hz) Example MS.10.1 continued B.3 Multisim Examples B-113 Investigating the Effect of Feedback In addition to the frequency-response analysis, which provided information on the dc voltage gain and the 3-dB bandwidth, we used Multisim to find the out-put resistances of the open-loop and closed-loop circuits (as set up in Ch10_OpAmp_Ex_A.ms10 and Ch10_OpAmp_Ex_Af.ms10). Table B.27 summarizes our findings for open-loop (A circuit) and closed-loop circuits.
It can be seen from Table B.27 that the series–shunt feedback connection causes the dc voltage gain and the output resistance of the circuit to decrease by a factor of 5.5, while the 3-dB bandwidth increases by approximately the same factor. This factor is equal to 1 + Aβ, the amount of the feedback. This is as expected and corresponds to what we learned in Chapter 9. Class B Bipolar Output Stage In this example, we will design a class B output stage to deliver an average power of 20 W to an 8-Ω load.
The schematic capture of a class B output stage implemented using BJTs is shown in Fig. B.102. We then will investigate various characteristics of the designed circuit such as crossover distortion and power-conversion efficiency. For this design, we are to select VCC about 5 V greater than the peak output voltage in order to avoid transistor saturation and signal distortion. Table B.27 Effect of Feedback on Gain, 3-dB Bandwidth, and Output Resistor Circuit Gain (V/V) 3-dB Bandwidth (MHz) Rout (Ω) Open loop 55.6 137 492.6 Closed loop 10.2 816 89.3 Figure B.102 Schematic capture of class B output stage.
Example MS.11.1 QN QP VCC 23 V VEE –23 V RL 8 V1 12.6 Vrms 1000 Hz 0˚ IN OUT B-114 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The circuit specifications are summarized in Table B.28.
Hand Design We know from Eq. (13.12) that Thus which leads to VCC = 23 V.
The peak current drawn from the supply will be Now we can use Eq. (13.13) to calculate the average power drawn from each of the supplies PS+ = PS– = 16.4 W PS = PS+ + PS– = 16.4 + 16.4 = 32.8 W Therefore, the power-conversion efficiency, η , is Now we can utilize Eq. (13.22) to calculate the maximum power dissipated in each of the transistors as Simulation Next, we use Multisim to verify the operation of the class B output stage designed above. For simulation purposes, we will use discrete-power transistors MJE243 and MJE253 (from ON Semiconductor), which are rated for a maximum continuous collector current ICmax = 4 A and a maximum collector–emitter volt-age VCEmax of 100 V. Table B.28 Class B Output Stage Specifications Specification Value PL 20 W RL 8Ω VCC + 5 V V ˆ PL 1 2 ---V ˆ 2 RL -------= V 2PLRL 2 20 8 × × = = V 17.9 V = IO V ˆ RL ------17.9 8 ----------= = Io 2.24A = PS+ PS– 1 π --- V ˆ RL ------VCC 1 π ---2.24 23 × × = = = η PL PS ------100% × 17.9 32.8 ----------100% × 61% = = = PDNmax PDPmax VCC 2 π2RL ------------23 ( )2 π2 8 × --------------= = = PDNmax PDPmax 6.7 W = = Example MS.11.1 continued B.3 Multisim Examples B-115 Load Power PL To measure the amount of power delivered to the load, we will utilize Transient Analysis in Multisim as set up in Ch11_Class_B_Ex.ms10. The transient analysis simulation is per-formed over the interval 0 ms to 2 ms, and the waveforms of the voltage at the output node and the output current are plotted in Fig. B.103. As can be seen in Fig. B.103, the peak voltage amplitude is approximately 16.9 V and the peak cur-rent amplitude is 2.1 A. Upon a closer look at the current and voltage waveforms, we can observe that both exhibit crossover distortion. The bottom graph in Fig. B.103 shows the instantaneous and the Figure B.103 Load voltage, current, and instantaneous and average load power.
20 10 Voltage V (OUT) Current (A) I(RL) I(RL)V (OUT) & AVG(I(RL)V(OUT)) –10 –20 0 0 0 1.0 m Time (s) Time (s) Time (s) 1.5 m 2.0 m 500.0 3 2 1 0 –1 –2 –3 0 40 25 10 –5 1.0 m 1.0 m 1.5 m 2.0 m 500.0 1.5 m 2.0 m 500.0 B-116 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim average power dissipated in the load resistance. These waveforms were obtained by multiplying the cur-rent and voltage waveforms, and by taking the running average for the average power, PL. The transient behavior of average power eventually settles into a quasiconstant steady-state value of 17.6 W. Supply Power, PS Similarly, we can plot instantaneous voltage and current at the VCC and VEE nodes to measure the value of PS. Figure B.104 shows the voltage, current, instantaneous, and average power for +VCC . We can plot these quantities for –VEE as well. However, owing to symmetry, we do not need to generate plots for the negative voltage supply. The average power provided by +VCC, PS+, is 15 W. There-fore, the total power provided by both voltage supplies is 30 W.
Figure B.104 Supply voltage, current, and instantaneous and average supply power.
26 25 24 23 22 21 20 3 2 I (VCC) A VCC (V) 1 60 50 40 Instantaneous and Avg Power (W) 30 20 10 0 –10 0 0 1.0 m 1.5 m Time (s) 2.0 m 2.5 m 3.0 m 500.0 0 1.0 m 1.5 m Time (s) 2.0 m 2.5 m 3.0 m 500.0 0 1.0 m 1.5 m Time (s) 2.0 m 2.5 m 3.0 m 500.0 Example MS.11.1 continued B.3 Multisim Examples B-117 Power-Conversion Efficiency, h Now we can calculate the power-conversion efficiency of the simulated circuit as follows. Transistor Power Dissipation, PD Figure B.103 shows voltage, current, instantaneous and average power plots for Qp only. A similar plot can be obtained for Qn to measure the power dissipated in the npn device. As expected, the voltage waveform is a sinusoid, and the current waveform consists of half-sinusoids. The waveform of instantaneous power is rather unusual. It indicates the presence of some distor-tion as a result of driving the transistors rather hard. This can be verified by reducing the amplitude of the input signal. Students are encouraged to investigate this point. The average power dissipated in Qp, as mea-sured from Fig. B.105, is approximately 6 W. Therefore, the total power dissipated in the transistors is 12 W.
Figure B.105 Voltage, current, and instantaneous and average power for Qp.
η PL PS ------100% × 17.6 30 ----------100% × 58.6% = = = 0 –13 –27 VCE (QP) A IC (QP) A Instantaneous and Avg Power of QP (W) –40 0 500.0 1.0 m Time (s) Time (s) 1.5 m 2.0 m 2.5 m 3.0 m 0 –10 –2.0 –3.0 0 500.0 1.0 m 1.5 m 2.0 m 2.5 m 3.0 m Time (s) 0 500.0 1.0 m 1.5 m 2.0 m 2.5 m 3.0 m 20 15 10 5 0 B-118 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The simulation results and hand-design calculations are summarized in Table B.29. Observe that the values are quite close, which verifies our design of the class B output stage. Crossover Distortion We can further investigate the crossover distortion of this circuit by utilizing the voltage transfer characteristics (VTC) curve of the class B output stage. The plot is obtained through a dc sweep analysis in Multisim where vIN is swept over the range –10 V to 10 V in 1.0-mV increments.
From the resulting VTC curve, shown in Fig. B.106, we can see that the dead band extends from –0.605 V to 0.56 V. The effect of crossover distortion can be quantified by performing a Fourier analysis on the output voltage in Multisim. Total Harmonic Distortion (THD) This analysis decomposes the waveform generated via transient analysis into its Fourier-series components. Furthermore, Multisim computes the THD of the output waveform, and the results are shown in Fig. B.107. Table B.29 Summary of Simulation and Hand-Design Results Measurement Hand Design Simulated Error % PL 17.9 W 17.6 W 1.7 PS 32.8 W 30 W 8.5 PD 13.4 W 12 W 10.4 n 61% 58.6% 3.9 Figure B.106 VTC of class B output stage.
15 10 5 0 –5 –10 –15 –10 –5 0 vv1 Voltage (V) Voltage (V) 5 10 Example MS.11.1 continued B.3 Multisim Examples B-119 From the Fourier analysis, we note that the waveform is rather rich in odd harmonics and that the resulting THD is 2.13%, which is rather high. A Two-Stage CMOS Op Amp with Frequency Compensation In this example, we will use Multisim to aid in designing the frequency compensation of the two-stage CMOS circuit whose schematic is shown in Fig. B.108. Multisim will then be employed to determine the frequency response and the slew rate of the op amp. We will assume a 0.5-μm CMOS technology for the MOSFETs and use typical SPICE level-1 model parameters for this technology. The op-amp circuit in Fig. B.108 is designed using a reference current IREF = 90 µA, a supply voltage VDD = 3.3 V, and a load capacitor CL = 1 pF. Unit-size transistors with are used for both the NMOS and PMOS devices. The transistors are sized for an overdrive voltage VOV = 0.3 V.
The corresponding multiplicative factors are shown in Fig. B.108.
In Multisim, the common-mode input voltage VCM of the op-amp circuit is set to and DC Operating Point Analysis is performed to determine the dc bias conditions. Using the values found from the simulation results for the small-signal parameters of the MOSFETs, we obtain Gm1 = 0.333 mA/V Gm2 = 0.650 mA/V C1 = 26.5 fF C2 = 1.04 pF Figure B.107 Fourier-series components of the output voltage and class B output stage THD.
30 Magnitude (dB) –30 –60 0 2 k 4 k 6 k Frequency (Hz) Fourier Analysis 8 k 10 k 0 Example MS.12.1 W L ⁄ 1.25μm 0.6μm ⁄ = VDD 2 ⁄ 1.65V, = B-120 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim using Eqs. (10.7), (10.14), (10.25), and (10.26) respectively. Recall that Gm1 and Gm2 are the transconduc-tances of, respectively, the first and second stages of the op amp. Capacitors C1 and C2 represent the total capacitance to ground at the output nodes of, respectively, the first and second stage of the op amp.
Then, using Eq. (10.28), the frequency of the second, nondominant, pole can be found as To place the transmission zero, given by Eq. (10.38), at infinite frequency, we select Now, using Eq. (10.37), the phase margin of the op amp can be expressed as where ft is the unity-gain frequency, given in Eq. (10.31): Using the above two equations we determine that compensation capacitors of CC = 0.78 pF and CC = 2 pF are required to achieve phase margins of PM = 55o and PM = 75o, respectively.
Next, an ac-analysis simulation is performed in Multisim to compute the frequency response of the op amp and to verify the foregoing design values (as set up in Ch12_Two_Stage_CMOS_OpAmp_ Ex_Freq-Resp.ms10). It Figure B.108 Schematic capture of the two-stage CMOS op amp.
VDD VDD VDD 3.3 V 3.3 V 3.3 V M=16 Q5 M = 8 Q2 M = 4 Q6 vOUT R Cc 600 fF 1.53 k M = 16 Q7 CLoad 1 pF M = 8 Q1 M = 2 Q3 M = 2 Q4 INN Iref1 90 uA INP INP 2 2 D Ep V1 0 V 10 mV 100 nsec 200 nsec 2 K K 0–5 v/v 0 v 0 v VCM 1.65 V 0-5 v/v 0 v 0 v INP M = 16 Q8 + NMOS Vtn LAMBDA kn' IREF L 0.7 V 0.1 246.2uA/V^2 0.09 mA IREF 0.09 mA 0.6 um W 1.25 um PMOS Vtp LAMBDA kp' L W –0.7 V 0.2 –86.1 uA/V^2 0.6 um 1.25 um fP2 Gm2 2πC2 -------------97.2 MHz = R 1 Gm2 ---------1.53 kΩ = = PM 90° 1 – ft fP2 ------⎝ ⎠ ⎛ ⎞ tan – = f1 Gm1 2πCC -------------= Example MS.12.1 continued B.3 Multisim Examples B-121 was found that, with R = 1.53 kΩ, we needed CC = 0.6 pF and CC = 1.8 pF to set PM = 55o and PM = 75o, respectively. We note that these values are reasonably close to those predicted by hand analysis. The corre-sponding frequency responses for the compensated op amps are plotted in Figs. B.109 and B.110. For compar-ison, we also show the frequency response of the uncompensated op amp (CC = 0). Observe that the unity-gain frequency ft drops from 70.8 MHz to 26.4 MHz as CC is increased to improve PM. Rather than increasing the compensation capacitor CC to improve the phase margin, the value of the series resistor R can be increased: for a given CC, increasing R above places the transmission zero at a negative real-axis location (Eq. 10.38), where the phase it introduces adds to the phase margin. Thus, PM can be improved without affecting ft. To verify this point, we set CC to 0.6 pF and simulate the op-amp circuit in Multisim for the cases of R = 1.53 kΩ and R = 3.2 kΩ. The corresponding frequency response is plotted in Fig. B.111. Observe how ft is approximately independent of R. However, by increasing R, we can improve PM from 55o to 75o.
Increasing the PM is desirable because it reduces the overshoot in the step response of the op amp. To verify this point, we simulate in Multisim the step response of the op amp for PM = 55o and PM = 75o. To do that, we connect the op amp in a unity-gain configuration, apply a small (10-mV) pulse signal at the input with very short (1-ps) rise and fall times to emulate a step input, perform a transient analysis simu-lation (as set up in Ch12_Two_Stage_CMOS_OpAmp_Ex_Small-Signal.ms10), and plot the output volt-age as shown in Fig. B.112. Observe that the overshoot in the step response drops from 15% to 1.4% when the phase margin is increased from 55o to 75o.
We conclude this example by computing SR, the slew rate of the op amp. From Eq. (10.40), we have Figure B.109 Magnitude and phase response of the op-amp circuit with R = 1.53 k, CC = 0 (no frequency compen-sation), and CC = 1.8 pF (PM = 75o).
75.0 50.0 25.0 Magnitude (dB) Phase (degrees) 25.0 50.0 1.0000 0 45.0 90.0 135.0 180.0 1.0000 100.0000 10.0000 k Phase (deg) 1.0000 M 100.0000 M 100.0000 10.0000 k Frequency (Hz) 1.0000 M 100.0000 M 0 ft 1 Gm2 ⁄ SR 2πftVOV Gm1 CC ---------VOV 166.5 V/μs = = = B-122 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim Figure B.110 Magnitude and phase response of the op-amp circuit with R = 1.53 kΩ, CC = 0 (no frequency compen-sation), and CC = 1.8 pF (PM = 75o).
Figure B.111 Magnitude and phase response of the op amp circuit with CC = 0.6 pF, R = 1.53 kΩ (PM = 55o), and R = 3.2 kΩ (PM = 75o).
60.0 40.0 Magnitude (dB) Phase (deg) 20.0 20.0 40.0 45.0 90.0 135.0 180.0 1.0000 100.0000 10.0000 k 1.0000 M Phase (deg) 100.0000 M 0 1.0000 100.0000 10.0000 k 1.0000 M Frequency (Hz) 100.0000 M 0 ft f 60.000 50.000 40.000 30.000 20.000 10.000 10.000 20.000 30.000 40.000 1.00 0 45.0 90.0 135.0 180.0 1.000 Magnitude (dB) Phase (deg) 100.0000 10.0000 k Phase (deg) 1.0000 M 1.00 k Frequency (Hz) 1.00 M 0 Example MS.12.1 continued B.3 Multisim Examples B-123 when CC = 0.6 pF. Next, to determine SR using Multisim, we again connect the op amp in a unity-gain con-figuration and perform a transient analysis simulation (as set up in Ch12_Two_Stage_CMOS_ OpAmp_Ex_Large-Signal.ms10). However, we now apply a large pulse signal (2.2 V) at the input to cause slew-rate limiting at the output. The corresponding output voltage waveform is plotted in Fig. B.113. The slope of the slew-rate-limited output waveform corresponds to the slew rate of the op amp and is found to be SR = 160 V/µs and 60 V/µs for the negative- and positive-going output, respectively. These results, with the Figure B.112 Small-signal step response (for a 10-mV step input) if the op-amp circuit is connected in a unity-gain configuration: PM = 55o (CC = 0.6 pF, R = 1.53 kΩ) and PM = 75o (CC = 0.6 pF, R = 3.2 kΩ).
Figure B.113 Large-signal step response (for a 2.2-V step input) if the op-amp circuit is connected in a unity-gain configuration. The slope of the rising and falling edges of the output waveform correspond to the slew rate of the op amp.
1.6570 1.6550 1.6530 1.6510 1.6490 500 n 550 n 600 n 650 n Time (s) 700 n 750 n 800 n 3.5 2.5 1.5 Voltage (V) 500.0 m 500.0 m 500 n 550 n 600 n 650 n Time (s) 700 n 750 n B-124 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim unequal values of SR in the two directions, differ from those predicted by the simple model for the slew-rate limiting of the two-stage op-amp circuit. The difference can perhaps be said to be a result of transistor Q4 entering the triode region and its output current (which is sourced through CC) being correspondingly reduced. Of course, the availability of Multisim should enable the reader to explore this point further.
The CMOS Inverter In this example, we will use Multisim to design a CMOS inverter whose schematic capture is shown in Fig.
B.114. We will assume a 0.18-μm CMOS technology for the MOSFETs and use typical SPICE level-1 model parameters for this technology, including the intrinsic capacitance values. This model does not take into account the short-channel effects for this technology. Also, the load capacitance is assumed to be dom-inated by the extrinsic component Cext (resulting from the wiring and the input capacitance of the driven gates), where the value used in this example is 15 fF. We will begin with an approximate hand-analysis design. We will then use Multisim to verify that the designed circuit meets the specifications. The targeted specification for this inverter is a high-to-low propagation delay (tPHL) of less than 45 ps. Once designed, the other characteristics of this inverter such as low-to-high propagation delay (tPLH), noise margins, and threshold voltage will be investigated. The inverter specifications are summarized in Table B.30.
Table B.30 CMOS Inverter Specifications Parameters Value tPHL 45 ps CL 15 fF VDD 1.8 V Figure B.114 Schematic capture of the CMOS inverter.
Example MS.13.1 vIN 0 V 1.8 V 0.5usec 1usec + Q1 Q2 1.8 V vOUT CL 15fF VDD Example MS.12.1 continued B.3 Multisim Examples B-125 Hand Design For the design of this inverter we choose L = 0.2 µm, so we have Leff = 0 .180 µm. As mentioned earlier, to minimize area, all channels are usually made equal to the minimum length permitted by the given technology. To meet the specified tPHL, we need to size carefully. Once sized, is chosen, which is a compromise between area, noise margins, and tPLH. The value of tPHL can be estimated using Eq. (14.64) as where αn is a factor determined by the relative values of Vt and VDD (Vtn /VDD = 0.5/1.8 = 0.278): Based on the above equations, the specified tPHL can be achieved by selecting the ratio and consequently . Table B.31 summarizes the relevant sizing informa-tion for each transistor. The third column of this table shows the transconductance parameter values for each transistor (which are typical values for 0.18-µm CMOS technology).
Note that for the selected width values, the intrinsic capacitances Cgd1 and Cgd2 are insignificant in comparison to the load capacitance. This confirms our initial assumption that in our hand calculations of delay, we could neglect Cgd1 an Cgd2 (which vary proportionally with width).
Simulation Verifying Propagation Delay To investigate the dynamic operation of the inverter and to verify that the design meets the specified tPHL, we apply an ideal pulse signal at the input and perform a transient analy-sis, as set up in Ch13_CMOS_Inverter_tPHL_Ex.ms10. Then, we plot the input and output waveforms as shown in Fig. B.115. Based on the simulated response, tPHL = 40.5 ps (as indicated in Fig. B.115). Similarly, we obtain tPLH = 60.3 ps, resulting in the inverter propagation delay (tP) of 50.4 ps. Therefore, the specified high-to-low propagation delay specification is met, and tP takes a reasonable value.
Voltage Transfer Characteristic (VTC) To compute both the VTC of the inverter and its supply current at various values of the input voltage Vin, we apply a dc voltage source at the input and perform a dc sweep with Vin swept over the range 0 to VDD, as set up in Ch13_CMOS_Inverter_VTC_Ex.ms10. The resulting VTC is plotted in Fig. B.116. Note that the slope of the VTC in the switching region (where the NMOS and PMOS devices are both in saturation) is not infinite as predicted from the simple theory pre-sented earlier. Rather, the nonzero value of λ causes the inverter gain to be finite. The two points on the VTC at which the inverter gain is unity (i.e., the VTC slope is –1 V/V) and that determine VIL and VIH are indicated in Fig. B.116. The corresponding noise margins are NML = 0.76 V and NMH = 0.81V. Note that the design provides high tolerance to noise, since noise margins are reasonably high (NML and NMH are 42% and 45% of the supply voltage). This implies that the inverter would provide the correct logic output for an input noise variation of up to approximately 40% of the VDD.
Table B.31 Transistor Sizes Transistor W (µm) Leff (µm) k’ (µA/V2) NMOS 0.27 0.18 246.2 PMOS 0.54 0.18 86.1 W Leff ⁄ ( )n W Leff ⁄ ( )p = 2 W Leff ⁄ ( )n tPHL αnC k′ n W Leff --------⎝ ⎠ ⎛ ⎞VDD ---------------------------------15 10 15 – × αn 246.2 10 6 – W Leff --------⎝ ⎠ ⎛ ⎞1.8 × ------------------------------------------------------= = αn 2 7 4 3 – Vtn VDD ⁄ ( ) Vtn VDD ⁄ ( ) 2 + ⁄ ---------------------------------------------------------------------------2.01 = = W Leff ⁄ ( )n 1.5 = W Leff ⁄ ( )n 3 = B-126 Appendix B SPICE Device Models and Design Simulation Examples Using PSpice and Multisim The threshold voltage VM of the CMOS inverter is defined as the input voltage vIN that results in an identical switching output voltage vOUT, that is, Thus, as shown in Fig. B.117, VM is at the intersection of the VTC with the straight line corresponding to vOUT = vIN. This line can be simply generated by plotting vIN on the vertical axis, in addition to vOUT.
Note that VM = 0.87 V, which is very close to the desired value of VDD/2 = 0.9V, as desired.
Figure B.115 Time domain response of the CMOS inverter to measure tPHL.
Figure B.116 Output voltage versus input voltage for the inverter (to measure low and high noise margins NML and NMH).
490.018 p –66.462 m 326.249 m 718.961 m 1.112 Voltage (V) 1.504 1.897 577.367 p 752.064 p 839.413 p 926.762 p 664.716 p Time (s) 500.0 m 0 –250 m 500 m 1 Voltage (V) 2 1.0 vvin Voltage (V) 1.5 VM vIN vOUT vIN = = Example MS.13.1 continued B.3 Multisim Examples B-127 Finally, the supply current is plotted versus input voltage in Fig. B.118. Observe that in the transition region, where the inverter is switching, the current is no longer zero. Specifically, the peak current occurs at the inverter threshold voltage. Figure B.117 Output voltage versus input voltage for the inverter (to the threshold voltage measure Vth).
Figure B.118 Supply current versus input voltage for the inverter.
500.0 m 0 –250.00 m –500.00 m 1.25 Voltage (V) 2.00 1.0 vvin Voltage (V) 1.5 30 µ 25 µ 20 µ Current (A) 15 µ 10 µ 5 µ 5 µ 500.0m 0 1.0 vvin Voltage (V) 1.5 0 C-1 APPENDIX C TWO-PORT NETWORK PARAMETERS Introduction At various points throughout the text, we make use of some of the different possible ways to characterize linear two-port networks. A summary of this topic is presented in this appendix.
C.1 Characterization of Linear Two-Port Networks A two-port network (Fig. C.1) has four port variables: V1, I1, V2, and I2. If the two-port net-work is linear, we can use two of the variables as excitation variables and the other two as response variables. For instance, the network can be excited by a voltage V1 at port 1 and a voltage V2 at port 2, and the two currents, I1 and I2, can be measured to represent the net-work response. In this case, V1 and V2 are independent variables and I1 and I2 are dependent variables, and the network operation can be described by the two equations (C.1) (C.2) Here, the four parameters y11, y12, y21, and y22 are admittances, and their values completely characterize the linear two-port network.
Depending on which two of the four port variables are used to represent the network excitation, a different set of equations (and a correspondingly different set of parameters) is obtained for characterizing the network. We shall present the four parameter sets commonly used in electronics.
I1 y11V1 y12V2 + = I2 y21V1 y22V2 + = V1 I1 I2 V2 Linear two-port network Figure C.1 The reference directions of the four port variables in a linear two-port network.
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C-2 Appendix C Two-Port Network Parameters C.1.1 y Parameters The short-circuit admittance (or y-parameter) characterization is based on exciting the net-work by V1 and V2, as shown in Fig. C.2(a). The describing equations are Eqs. (C.1) and (C.2). The four admittance parameters can be defined according to their roles in Eqs. (C.1) and (C.2).
Specifically, from Eq. (C.1) we see that y11 is defined as . (C.3) Thus y11 is the input admittance at port 1 with port 2 short-circuited. This definition is illustrated in Fig. C.2(b), which also provides a conceptual method for measuring the input short-circuit admittance y11.
The definition of y12 can be obtained from Eq. (C.1) as (C.4) Thus y12 represents transmission from port 2 to port 1. Since in amplifiers, port 1 represents the input port and port 2 the output port, y12 represents internal feedback in the network.
Figure C.2(c) illustrates the definition of and the method for measuring y12.
Figure C.2 Definition of and conceptual measurement circuits for the y parameters.
y11 = I1 V1 -----V2=0 y12 = I1 V2 -----V1=0 ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
C.1 Characterization of Linear Two-Port Networks C-3 The definition of y21 can be obtained from Eq. (C.2) as (C.5) Thus y21 represents transmission from port 1 to port 2. If port 1 is the input port and port 2 the output port of an amplifier, then y21 provides a measure of the forward gain or transmis-sion. Figure C.2(d) illustrates the definition of and the method for measuring y21.
The parameter y22 can be defined, based on Eq. (C.2), as (C.6) Thus y22 is the admittance looking into port 2 while port 1 is short-circuited. For amplifiers, y22 is the output short-circuit admittance. Figure C.2(e) illustrates the definition of and the method for measuring y22.
C.1.2 z Parameters The open-circuit impedance (or z-parameter) characterization of two-port networks is based on exciting the network by I1 and I2, as shown in Fig. C.3(a). The describing equations are (C.7) (C.8) Figure C.3 Definition of and conceptual measurement circuits for the z parameters.
y21 = I2 V1 -----V2=0 y22 = I2 V2 -----V1=0 V1 z11I1 z12I2 + = V2 z21I1 z22I2 + = ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
C-4 Appendix C Two-Port Network Parameters Owing to the duality between the z- and y-parameter characterizations, we shall not give a detailed discussion of z parameters. The definition and the method of measuring each of the four z parameters are given in Fig. C.3.
C.1.3 h Parameters The hybrid (or h-parameter) characterization of two-port networks is based on exciting the network by I1 and V2, as shown in Fig. C.4(a) (note the reason behind the name hybrid). The describing equations are (C.9) (C.10) from which the definition of the four h parameters can be obtained as Figure C.4 Definition of and conceptual measurement circuits for the h parameters.
V1 h11I1 h12V2 + = I2 h21I1 h22V2 + = h11 V1 I1 -----V2=0 = h21 I2 I1 ----V2=0 = h12 V1 V2 -----I1=0 = h22 I2 V2 -----I1=0 = (e) ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
C.1 Characterization of Linear Two-Port Networks C-5 Thus, h11 is the input impedance at port 1 with port 2 short-circuited. The parameter h12 represents the reverse or feedback voltage ratio of the network, measured with the input port open-circuited. The forward-transmission parameter h21 represents the current gain of the network with the output port short-circuited; for this reason, h21 is called the short-circuit current gain. Finally, h22 is the output admittance with the input port open-circuited.
The definitions and conceptual measuring setups of the h parameters are given in Fig. C.4.
C.1.4 g Parameters The inverse-hybrid (or g-parameter) characterization of two-port networks is based on excitation of the network by V1 and I2, as shown in Fig. C.5(a). The describing equations are (C.11) (C.12) The definitions and conceptual measuring setups are given in Fig. C.5.
C.1.5 Equivalent-Circuit Representation A two-port network can be represented by an equivalent circuit based on the set of parameters used for its characterization. Figure C.6 shows four possible equivalent circuits corresponding Figure C.5 Definition of and conceptual measurement circuits for the g parameters.
I1 g11V1 g12I2 + = V2 g21V1 g22I2 + = I I ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
C-6 Appendix C Two-Port Network Parameters to the four parameter types just discussed. Each of these equivalent circuits is a direct pictorial representation of the corresponding two equations describing the network in terms of the particular parameter set.
Finally, it should be mentioned that other parameter sets exist for characterizing two-port networks, but these are not discussed or used in this book. Figure C.6 Equivalent circuits for two-port networks in terms of (a) y, (b) z, (c) h, and (d) g parameters.
EXERCISE C.1 Figure EC.1 shows the small-signal, equivalent-circuit model of a transistor. Calculate the values of the h parameters.
Ans. h11 2.6 kΩ; h12 2.5 × 10−4; h21 100; h22 2 × 10−5 Ω Figure EC.1 ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
C.1 Characterization of Linear Two-Port Networks C-7 PROBLEMS C.1 (a) An amplifier characterized by the h-parameter equi-valent circuit of Fig. C.6(c) is fed with a source having a volt-age Vs and a resistance Rs, and is loaded in a resistance RL.
Show that its voltage gain is given by (b) Use the expression derived in (a) to find the voltage gain of the transistor in Exercise C.1 for Rs = 1 kΩ and RL = 10 kΩ.
C.2 The terminal properties of a two-port network are mea-sured with the following results: With the output short-circuited and an input current of 0.01 mA, the output current is 1.0 mA and the input voltage is 26 mV. With the input open-circuited and a voltage of 10 V applied to the output, the current in the output is 0.2 mA and the voltage measured at the input is 2.5 mV. Find values for the h parameters of this network.
C.3 Figure PC.3 shows the high-frequency equivalent cir-cuit of a BJT. (For simplicity, rx has been omitted.) Find the y parameters.
Figure PC.3 V2 Vs ------h21 – h11 Rs + ( ) h22 1 RL ⁄ + ( ) h12h21 – -------------------------------------------------------------------------------= ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
D-1 APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin’s theorem, Norton’s theorem, and the source-absorption theorem.
D.1 Thévenin’s Theorem Thévenin’s theorem is used to represent a part of a network by a voltage source Vt and a series impedance Zt, as shown in Fig. D.1. Figure D.1(a) shows a network divided into two parts, A and B. In Fig. D.1(b), part A of the network has been replaced by its Thévenin equivalent: a voltage source Vt and a series impedance Zt. Figure D.1(c) illustrates how Vt is to be deter-mined: Simply open-circuit the two terminals of network A and measure (or calculate) the volt-age that appears between these two terminals. To determine Zt, we reduce all external (i.e., independent) sources in network A to zero by short-circuiting voltage sources and open-circuit-ing current sources. The impedance Zt will be equal to the input impedance of network A after this reduction has been performed, as illustrated in Fig. D.1(d).
D.2 Norton’s Theorem Norton’s theorem is the dual of Thévenin’s theorem. It is used to represent a part of a network by a current source In and a parallel impedance Zn, as shown in Fig. D.2. Figure D.2(a) shows a network divided into two parts, A and B. In Fig. D.2(b), part A has been replaced by its Norton’s equivalent: a current source In and a parallel impedance Zn. The Norton’s current source In can be measured (or calculated) as shown in Fig. D.2(c). The terminals of the network being reduced (network A) are shorted, and the current In will be equal simply to the short-cir-cuit current. To determine the impedance Zn, we first reduce the external excitation in network A to zero: That is, we short-circuit independent voltage sources and open-circuit independent current sources. The impedance Zn will be equal to the input impedance of network A after this source-elimination process has taken place. Thus the Norton impedance Zn is equal to the Thévenin impedance Zt. Finally, note that , where Z = Zn = Zt. In = Vt Z ⁄ ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
D-2 Appendix D Some Useful Network Theorems Figure D.1 Thévenin’s theorem.
Figure D.2 Norton’s theorem.
n Example D.1 Figure D.3(a) shows a bipolar junction transistor circuit. The transistor is a three-terminal device with the terminals labeled E (emitter), B (base), and C (collector). As shown, the base is connected to the dc power supply V + via the voltage divider composed of R1 and R2. The collector is connected to the dc supply V + through R3 and to ground through R4. To simplify the analysis, we wish to apply Thévenin’s theorem to reduce the circuit.
Solution Thévenin’s theorem can be used at the base side to reduce the network composed of V +, R1, and R2 to a dc voltage source VBB, VBB V+ R2 R1 R2 + ------------------= ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
D.3 Source-Absorption Theorem D-3 D.3 Source-Absorption Theorem Consider the situation shown in Fig. D.4. In the course of analyzing a network, we find a con-trolled current source Ix appearing between two nodes whose voltage difference is the control-ling voltage Vx. That is, Ix = gmVx where gm is a conductance. We can replace this controlled source by an impedance , as shown in Fig. D.4, because the current drawn by this impedance will be equal to the current of the controlled source that we have replaced. and a resistance RB, || R2 where || denotes “in parallel with.” At the collector side, Thévenin’s theorem can be applied to reduce the network composed of V+, R3, and R4 to a dc voltage source VCC, and a resistance RC, || R4 The reduced circuit is shown in Fig. D.3(b).
Figure D.3 Thévenin’s theorem applied to simplify the circuit of (a) to that in (b). (See Example D.1.) RB R1 = VCC V+ R4 R3 R4 + ------------------= RC R3 = Figure D.4 The source-absorption theorem.
Zx = Vx Ix ⁄ = 1 gm ⁄ ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
D-4 Appendix D Some Useful Network Theorems Example D.2 Figure D.5(a) shows the small-signal, equivalent-circuit model of a transistor. We want to find the resis-tance Rin “looking into” the emitter terminal E—that is, the resistance between the emitter and ground— with the base B and collector C grounded.
Solution From Fig. D.5(a), we see that the voltage vπ will be equal to –ve. Thus, looking between E and ground, we see a resistance rπ in parallel with a current source drawing a current gmve away from terminal E. The latter source can be replaced by a resistance , resulting in the input resistance Rin given by || as illustrated in Fig. D.5(b).
Figure D.5 Circuit for Example D.2.
(a) (1 gm ⁄ ) Rin rπ = (1 gm ⁄ ) EXERCISES D.1 A source is measured and found to have a 10-V open-circuit voltage and to provide 1 mA into a short circuit. Calculate its Thévenin and Norton equivalent source parameters. Ans. Vt = 10 V; Zt = Zn = 10 kΩ; In = 1 mA D.2 In the circuit shown in Fig. ED.2, the diode has a voltage drop VD 0.7 V. Use Thévenin’s theo-rem to simplify the circuit and hence calculate the diode current ID.
Ans. 1 mA ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
D.3 Source-Absorption Theorem D-5 D.3 The two-terminal device M in the circuit of Fig. ED.3 has a current IM 1 mA independent of the volt-age VM across it. Use Norton’s theorem to simplify the circuit and hence calculate the voltage VM. Ans. 5 V Figure ED.2 Figure ED.3 PROBLEMS D.1 Consider the Thévenin equivalent circuit characterized by Vt and Zt. Find the open-circuit voltage Voc and the short-circuit current IsD (i.e., the current that flows when the terminals are shorted together). Express Zt in terms of Voc and IsD.
D.2 Repeat Problem D.1 for a Norton equivalent circuit characterized by In and Zn.
D.3 A voltage divider consists of a 9-kΩ resistor con-nected to +10 V and a resistor of 1 kΩ connected to ground. What is the Thévenin equivalent of this voltage divider? What output voltage results if it is loaded with 1 kΩ? Calculate this two ways: directly and using your Thévenin equivalent.
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D-6 Appendix D Some Useful Network Theorems APPENDIX D PROBLEMS D.4 Find the output voltage and output resistance of the circuit shown in Fig. PD.4 by considering a succession of Thévenin equivalent circuits.
D.5 Repeat Example D.2 with a resistance RB connected between B and ground in Fig. D.5 (i.e., rather than directly grounding the base B as indicated in Fig. D.5).
D.6 Figure PD.6(a) shows the circuit symbol of a device known as the p-channel junction field-effect transistor (JFET). As indicated, the JFET has three terminals. When the gate terminal G is connected to the source terminal S, the two-terminal device shown in Fig. PD.6(b) is obtained. Its i–v characteristic is given by where IDSS and VP are positive constants for the particular JFET. Now consider the circuit shown in Fig. PD.6(c) and let VP = 2 V and IDSS = 2 mA. For V + = 10 V show that the JFET is operating in the constant-current mode and find the voltage across it. What is the minimum value of V + for which this mode of operation is maintained? For V + = 2 V find the values of I and V.
i IDSS 2 v VP ------v VP ------⎝ ⎠ ⎛ ⎞2 – for v VP ≤ = i IDSS for v VP ≥ = Figure PD.6 Figure PD.4 Vo ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E-1 APPENDIX E SINGLE-TIME-CONSTANT CIRCUITS Introduction Single-time-constant (STC) circuits are those circuits that are composed of or can be reduced to one reactive component (inductance or capacitance) and one resistance. An STC circuit formed of an inductance L and a resistance R has a time constant . The time constant τ of an STC circuit composed of a capacitance C and a resistance R is given by τ = CR.
Although STC circuits are quite simple, they play an important role in the design and analysis of linear and digital circuits. For instance, the analysis of an amplifier circuit can usually be reduced to the analysis of one or more STC circuits. For this reason, we will review in this appen-dix the process of evaluating the response of STC circuits to sinusoidal and other input signals such as step and pulse waveforms. The latter signal waveforms are encountered in some amplifier applications but are more important in switching circuits, including digital circuits.
E.1 Evaluating the Time Constant The first step in the analysis of an STC circuit is to evaluate its time constant τ.
E.1.1 Rapid Evaluation of τ In many instances, it will be important to be able to evaluate rapidly the time constant τ of a given STC circuit. A simple method for accomplishing this goal consists first of reducing the excitation to zero; that is, if the excitation is by a voltage source, short it, and if by a current τ = L R ⁄ Example E.1 Reduce the circuit in Fig. E.1(a) to an STC circuit, and find its time constant.
Solution The reduction process is illustrated in Fig. E.1 and consists of repeated applications of Thévenin’s theo-rem. From the final circuit (Fig. E.1c), we obtain the time constant as || || τ = C R4 { [R3 R1 ( + R2)]} ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E-2 Appendix E Single-Time-Constant Circuits source, open it. Then, if the circuit has one reactive component and a number of resistances, “grab hold” of the two terminals of the reactive component (capacitance or inductance) and find the equivalent resistance Req seen by the component. The time constant is then either or CReq. As an example, in the circuit of Fig. E.1(a), we find that the capacitor C “sees” a resistance R4 in parallel with the series combination of R3 and R2 in parallel with R1. Thus || || and the time constant is CReq.
In some cases it may be found that the circuit has one resistance and a number of capacitances or inductances. In such a case, the procedure should be inverted; that is, “grab hold” of the resis-tance terminals and find the equivalent capacitance Ceq, or equivalent inductance Leq, seen by this resistance. The time constant is then found as CeqR or Leq/R. This is illustrated in Exam-ple E.2. Figure E.1 The reduction of the circuit in (a) to the STC circuit in (c) through the repeated application of Thévenin’s theorem.
L Req ⁄ Req = R4 [R3 R2 ( + R1)] Example E.2 Find the time constant of the circuit in Fig. E.2.
Figure E.2 Circuit for Example E.2.
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E.1 Evaluating the Time Constant E-3 Finally, in some cases an STC circuit has more than one resistance and more than one capacitance (or more than one inductance). Such cases require some initial work to simplify the circuit, as illustrated by Example E.3. Solution After reducing the excitation to zero by short-circuiting the voltage source, we see that the resistance R “sees” an equivalent capacitance C1 + C2. Thus, the time constant τ is given by τ = C1 C2 + ( )R Example E.3 Here we show that the response of the circuit in Fig. E.3(a) can be obtained using the method of analysis of STC circuits.
Solution The analysis steps are illustrated in Fig. E.3. In Fig. E.3(b) we show the circuit excited by two separate but equal voltage sources. The reader should convince himself or herself of the equivalence of the circuits in Fig. E.3(a) and E.3(b). The “trick” employed to obtain the arrangement in Fig. E.3(b) is a very useful one.
Figure E.3 The response of the circuit in (a) can be found by superposition, that is, by summing the responses of the circuits in (d) and (e).
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E-4 Appendix E Single-Time-Constant Circuits E.2 Classification of STC Circuits STC circuits can be classified into two categories, low-pass (LP) and high-pass (HP) types, with each category displaying distinctly different signal responses. The task of finding whether an STC circuit is of LP or HP type may be accomplished in a number of ways, the simplest of which uses the frequency domain response. Specifically, low-pass circuits pass dc (i.e., signals with zero frequency) and attenuate high frequencies, with the transmission being zero at ω = ∞. Thus, we can test for the circuit type either at ω = 0 or at ω = ∞. At ω = 0 capacitors should be replaced by open circuits and inductors should be replaced by short circuits (jωL = 0). Then if the output is zero, the circuit is of the high-pass type, while if the output is finite, the circuit is of the low-pass type. Alternatively, we may test at ω = ∞ by replacing capacitors with short circuits and inductors with open circuits (jωL = ∞). Then if the output is finite, the circuit is of the HP type, whereas if the output is zero, the circuit is of the LP type. In Table E.1, which provides a summary of these results, s.c.
stands for short circuit and o.c. for open circuit.
Figure E.4 shows examples of low-pass STC circuits, and Fig. E.5 shows examples of high-pass STC circuits. For each circuit we have indicated the input and output variables of interest.
Note that a given circuit can be of either category, depending on the input and output variables.
The reader is urged to verify, using the rules of Table E.1, that the circuits of Figs. E.4 and E.5 are correctly classified. Example E.3 continued Application of Thévenin’s theorem to the circuit to the left of the line and then to the circuit to the right of that line results in the circuit of Fig. E.3(c). Since this is a linear circuit, the response may be obtained using the principle of superposition. Specifically, the output voltage vO will be the sum of the two components vO1 and vO2. The first component, vO1, is the output due to the left-hand-side voltage source with the other voltage source reduced to zero. The circuit for calculating vO1 is shown in Fig. E.3(d). It is an STC circuit with a time constant given by || Similarly, the second component vO2 is the output obtained with the left-hand-side voltage source reduced to zero. It can be calculated from the circuit of Fig. E.3(e), which is an STC circuit with the same time constant τ.
Finally, it should be observed that the fact that the circuit is an STC one can also be ascertained by set-ting the independent source vI in Fig. E.3(a) to zero. Also, the time constant is then immediately obvious.
XX′ τ C1 C2 + ( ) R1 ( = R2) Table E.1 Rules for Finding the Type of STC Circuit Test at Replace Circuit is LP if Circuit is HP if ω = 0 C by o.c.
output is finite output is zero L by s.c.
ω = ∞ C by s.c.
output is zero output is finite L by o.c.
(1 jωC ⁄ = ∞) (1 jωC ⁄ = 0) ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E.2 Classification of STC Circuits E-5 Figure E.4 STC circuits of the low-pass type.
Figure E.5 STC circuits of the high-pass type.
(a) (b) (c) (d) (e) (f) (a) (b) (c) (d) (e) (f) EXERCISES E.1 Find the time constants for the circuits shown in Fig. EE.1.
Ans. (a) ; (b) Figure EE.1 R ----------------------------------------(a) (L1 || L2) (L1 || L2) (R1 || R2) ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E-6 Appendix E Single-Time-Constant Circuits E.3 Frequency Response of STC Circuits E.3.1 Low-Pass Circuits The transfer function T(s) of an STC low-pass circuit can always be written in the form (E.1) which, for physical frequencies, where s = jω, becomes (E.2) where K is the magnitude of the transfer function at ω = 0 (dc) and ω0 is defined by with τ being the time constant. Thus the magnitude response is given by (E.3) and the phase response is given by (E.4) Figure E.6 sketches the magnitude and phase responses for an STC low-pass circuit. The magnitude response shown in Fig. E.6(a) is simply a graph of the function in Eq. (E.3). The mag-nitude is normalized with respect to the dc gain K and is expressed in decibels; that is, the plot is for with a logarithmic scale used for the frequency axis. Furthermore, the fre-quency variable has been normalized with respect to ω0. As shown, the magnitude curve is closely defined by two straight-line asymptotes. The low-frequency asymptote is a horizontal straight line at 0 dB. To find the slope of the high-frequency asymptote, consider Eq. (E.3) and let 1, resulting in It follows that if ω doubles in value, the magnitude is halved. On a logarithmic frequency axis, doublings of ω represent equally spaced points, with each interval called an octave.
Halving the magnitude function corresponds to a 6-dB reduction in transmission (20 log 0.5 = –6 dB). Thus the slope of the high-frequency asymptote is –6 dB/octave. This can be equivalently expressed as –20 dB/decade, where “decade” indicates an increase in frequency by a factor of 10.
The two straight-line asymptotes of the magnitude–response curve meet at the “corner fre-quency” or “break frequency” ω0. The difference between the actual magnitude–response curve E.2 Classify the following circuits as STC high-pass or low-pass: Fig. E.4(a) with output iO in C to ground; Fig. E.4(b) with output iO in R to ground; Fig. E.4(d) with output iO in C to ground; Fig. E.4(e) with output iO in R to ground; Fig. E.5(b) with output iO in L to ground; and Fig. E.5(d) with output vO across C.
Ans. HP; LP; HP; HP; LP; LP T s ( ) K 1 s ω0 ⁄ ( ) + --------------------------= T jω ( ) K 1 j ω ω0 ⁄ ( ) + ------------------------------= ω0 1 τ ⁄ = T jω ( ) K 1 ω ω0 ⁄ ( )2 + -----------------------------------= φ ω ( ) tan 1 – ω ω0 ⁄ ( ) – = 20 log T jω ( ) K ⁄ , ω ω0 ⁄ T jω ( ) Kω0 ω ------©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E.3 Frequency Response of STC Circuits E-7 and the asymptotic response is largest at the corner frequency, where its value is 3 dB. To ver-ify that this value is correct, simply substitute ω = ω0 in Eq. (E.3) to obtain K/ Thus at ω = ω0, the gain drops by a factor of relative to the dc gain, which corresponds to a 3-dB reduction in gain. The corner frequency ω0 is appropriately referred to as the 3-dB frequency.
Similar to the magnitude response, the phase–response curve, shown in Fig. E.6(b), is closely defined by straight-line asymptotes. Note that at the corner frequency the phase is –45°, and that for ω ω0 the phase approaches –90°. Also note that the –45°/decade straight line approximates the phase function, with a maximum error of 5.7°, over the frequency range 0.1ω0 to 10ω0. Figure E.6 (a) Magnitude and (b) phase response of STC circuits of the low-pass type.
T jω0 ( ) = 2 2 Example E.4 Consider the circuit shown in Fig. E.7(a), where an ideal voltage amplifier of gain µ = –100 has a small (10-pF) capacitance connected in its feedback path. The amplifier is fed by a voltage source having a source resistance of 100 kΩ. Show that the frequency response Vo /Vs of this amplifier is equivalent to that of an STC circuit, and sketch the magnitude response.
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E-8 Appendix E Single-Time-Constant Circuits E.3.2 High-Pass Circuits The transfer function T(s) of an STC high-pass circuit can always be expressed in the form (E.5) which for physical frequencies s = jω becomes (E.6) where K denotes the gain as s or ω approaches infinity and ω 0 is the inverse of the time constant τ, The magnitude response (E.7) and the phase response (E.8) Example E.4 continued Solution Direct analysis of the circuit in Fig. E.7(a) results in the transfer function which can be seen to be that of a low-pass STC circuit with a dc gain µ = –100 (or, equivalently, 40 dB) and a time constant τ = RCf(–µ + 1) = 100 × 103 × 10 × 10–12 × 101 10–4 s, which corresponds to a frequency ω0 = 1/τ = 104 rad/s. The magnitude response is sketched in Fig. E.7(b).
Figure E.7 (a) An amplifier circuit and (b) a sketch of the magnitude of its transfer function.
(b) (a) Vo Vs -----µ 1 sRCf µ – 1 + ( ) + ---------------------------------------------= T s ( ) Ks s ω0 + ---------------= T jω ( ) K 1 jω0 ω ⁄ – -------------------------= ω0 = 1 τ ⁄ T jω ( ) K 1 ω0 ω ⁄ ( )2 + -----------------------------------= φ ω ( ) = tan 1 – ω0 ω ⁄ ( ) ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E.3 Frequency Response of STC Circuits E-9 are sketched in Fig. E.8. As in the low-pass case, the magnitude and phase curves are well defined by straight-line asymptotes. Because of the similarity (or, more appropriately, duality) with the low-pass case, no further explanation will be given. Figure E.8 (a) Magnitude and (b) phase response of STC circuits of the high-pass type.
(a) EXERCISES E.3 Find the dc transmission, the corner frequency f0, and the transmission at f = 2 MHz for the low-pass STC circuit shown in Fig. EE.3.
Figure EE.3 Ans. –6 dB; 318 kHz; –22 dB E.4 Find the transfer function T(s) of the circuit in Fig. E.2. What type of STC network is it?
Ans. HP T s ( ) = C1 C1 C2 + ------------------ s s 1/(C1 C2)R + [ ] + ----------------------------------------------; ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E-10 Appendix E Single-Time-Constant Circuits E.4 Step Response of STC Circuits In this section we consider the response of STC circuits to the step-function signal shown in Fig. E.9. Knowledge of the step response enables rapid evaluation of the response to other switching-signal waveforms, such as pulses and square waves.
E.4.1 Low-Pass Circuits In response to an input step signal of height S, a low-pass STC circuit (with a dc gain K = 1) produces the waveform shown in Fig. E.10. Note that while the input rises from 0 to S at t = 0, the output does not respond immediately to this transient and simply begins to rise exponen-tially toward the final dc value of the input, S. In the long term—that is, for t τ —the output approaches the dc value S, a manifestation of the fact that low-pass circuits faithfully pass dc.
The equation of the output waveform can be obtained from the expression (E.9) where Y∞ denotes the final value or the value toward which the output is heading and Y0+ denotes the value of the output immediately after t = 0. This equation states that the output at any time t is equal to the difference between the final value Y∞ and a gap that has an initial value of Y∞ – Y0+ and is “shrinking” exponentially. In our case, Y∞ = S and Y0+ = 0; thus, (E.10) E.5 For the situation discussed in Exercise E.4, if R = 10 kΩ, find the capacitor values that result in the circuit having a high-frequency transmission of 0.5 V/V and a corner frequency ω0 = 10 rad/s.
Ans. C1 = C2 = 5 µF E.6 Find the high-frequency gain, the 3-dB frequency f0, and the gain at f = 1 Hz of the capacitively coupled amplifier shown in Fig. EE.6. Assume the voltage amplifier to be ideal.
Figure EE.6 Ans. 40 dB; 15.9 Hz; 16 dB Figure E.9 A step-function signal of height S.
y t ( ) = Y∞ Y∞ Y0+ – ( )e t τ ⁄ – – y t ( ) S 1 e t τ ⁄ – – ( ) = ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E.4 Step Response of STC Circuits E-11 The reader’s attention is drawn to the slope of the tangent to y(t) at t = 0, which is indicated in Fig. E.10.
E.4.2 High-Pass Circuits The response of an STC high-pass circuit (with a high-frequency gain K = 1) to an input step of height S is shown in Fig. E.11. The high-pass circuit faithfully transmits the transient part of the input signal (the step change) but blocks the dc. Thus the output at t = 0 follows the input, and then it decays toward zero, Substituting for Y0+ and Y∞ in Eq. (E.9) results in the output y(t), (E.11) The reader’s attention is drawn to the slope of the tangent to y(t) at t = 0, indicated in Fig. E.11. Figure E.10 The output y(t) of a low-pass STC circuit excited by a step of height S.
Figure E.11 The output y(t) of a high-pass STC circuit excited by a step of height S.
Y0+ S = Y∞ 0 = y t ( ) Se t τ ⁄ – = Example E.5 This example is a continuation of the problem considered in Example E.3. For an input vI that is a 10-V step, find the condition under which the output vO is a perfect step.
Solution Following the analysis in Example E.3, which is illustrated in Fig. E.3, we have vO1 kr 10 1 e t τ ⁄ – – ( ) [ ] = ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E-12 Appendix E Single-Time-Constant Circuits Example E.5 continued where and where and || Thus It follows that the output can be made a perfect step of height 10kr volts if we arrange that that is, if the resistive voltage divider ratio is made equal to the capacitive voltage divider ratio.
This example illustrates an important technique, namely, that of the “compensated attenuator.” An applica-tion of this technique is found in the design of the oscilloscope probe. The oscilloscope probe problem is investigated in Problem E.3.
EXERCISES E.7 For the circuit of Fig. E.4(f), find vO if iI is a 3-mA step, R = 1 kΩ, and C = 100 pF.
Ans. E.8 In the circuit of Fig. E.5(f), find vO(t) if iI is a 2-mA step, R = 2 kΩ, and L = 10 µH.
Ans. E.9 The amplifier circuit of Fig. EE.6 is fed with a signal source that delivers a 20-mV step. If the source resistance is 100 kΩ, find the time constant τ and vO(t).
Ans. τ = 2 × 10−2 s; vO(t) = 1 × e–50t E.10 For the circuit in Fig. E.2 with C1 = C2 = 0.5 µF, R = 1 MΩ, find vO(t) if vI(t) is a 10-V step.
Ans. 5e−t E.11 Show that the area under the exponential of Fig. E.11 is equal to that of the rectangle of height S and width τ.
kr R2 R1 R2 + ------------------≡ vO2 = kc 10e t τ ⁄ – ( ) kc C1 C1 C2 + ------------------≡ τ C1 C2 + ( ) R1 ( = R2) vO vO1 vO2 + = = 10kr 10e t τ ⁄ – kc kr – ( ) + kc = kr 3 1 e 10 7t – – ( ) 4e 2 10 8t × – ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E.5 Pulse Response of STC Circuits E-13 E.5 Pulse Response of STC Circuits Figure E.12 shows a pulse signal whose height is P and whose width is T. We wish to find the response of STC circuits to input signals of this form. Note at the outset that a pulse can be con-sidered as the sum of two steps: a positive one of height P occurring at t = 0 and a negative one of height P occurring at t = T. Thus, the response of a linear circuit to the pulse signal can be obtained by summing the responses to the two step signals.
E.5.1 Low-Pass Circuits Figure E.13(a) shows the response of a low-pass STC circuit (having unity dc gain) to an input pulse of the form shown in Fig. E.12. In this case, we have assumed that the time constant τ is in the same range as the pulse width T. As shown, the LP circuit does not respond immediately to the step change at the leading edge of the pulse; rather, the output starts to rise exponentially toward a final value of P. This exponential rise, however, will be stopped at time t = T, that is, at the trailing edge of the pulse when the input undergoes a negative step change. Again, the output will respond by starting an exponential decay toward the final value of the input, which is zero. Finally, note that the area under the output waveform will be equal to the area under the input pulse waveform, since the LP circuit faithfully passes dc.
A low-pass effect usually occurs when a pulse signal from one part of an electronic system is connected to another. The low-pass circuit in this case is formed by the output resistance (Théve-nin’s equivalent resistance) of the system part from which the signal originates and the input capacitance of the system part to which the signal is fed. This unavoidable low-pass filter will cause distortion—of the type shown in Fig. E.13(a)—of the pulse signal. In a well-designed sys-tem such distortion is kept to a low value by arranging that the time constant τ be much smaller than the pulse width T. In this case, the result will be a slight rounding of the pulse edges, as shown in Fig. E.13(b). Note, however, that the edges are still exponential. The distortion of a pulse signal by a parasitic (i.e., unwanted) low-pass circuit is measured by its rise time and fall time. The rise time is conventionally defined as the time taken by the ampli-tude to increase from 10% to 90% of the final value. Similarly, the fall time is the time during which the pulse amplitude falls from 90% to 10% of the maximum value. These definitions are illustrated in Fig. E.13(b). By use of the exponential equations of the rising and falling edges of the output waveform, it can be easily shown that (E.12) which can be also expressed in terms of f0 = ω 02π = 12πτ as (E.13) tr tf 2.2τ = tr tf 0.35 f0 -------------= Figure E.12 A pulse signal with height P and width T.
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E-14 Appendix E Single-Time-Constant Circuits Finally, we note that the effect of the parasitic low-pass circuits that are always present in a sys-tem is to “slow down” the operation of the system: To keep the signal distortion within accept-able limits, one has to use a relatively long pulse width (for a given low-pass time constant).
The other extreme case—namely, when τ is much larger than T, is illustrated in Fig. E.13(c). As shown, the output waveform rises exponentially toward the level P. However, since τ T, the value reached at t = T will be much smaller than P. At t = T, the output waveform starts its exponential decay toward zero. Note that in this case the output waveform bears little resemblance to the input pulse. Also note that because τ T, the portion of the exponential curve from t = 0 to t = T is almost linear. Since the slope of this linear curve is proportional to the height of the input pulse, we see that the output waveform approximates the time integral of the input pulse. That is, a low-pass network with a large time constant approximates the operation of an integrator.
E.5.2 High-Pass Circuits Figure E.14(a) shows the output of an STC HP circuit (with unity high-frequency gain) excited by the input pulse of Fig. E.12, assuming that τ and T are comparable in value. As shown, the step transition at the leading edge of the input pulse is faithfully reproduced at the output of the HP circuit. However, since the HP circuit blocks dc, the output waveform immediately starts an exponential decay toward zero. This decay process is stopped at t = T, when the negative step transition of the input occurs and the HP circuit faithfully reproduces it. Thus, at t = T the output waveform exhibits an undershoot. Then it starts an exponential decay toward zero.
Finally, note that the area of the output waveform above the zero axis will be equal to that below the axis for a total average area of zero, consistent with the fact that HP circuits block dc.
In many applications, an STC high-pass circuit is used to couple a pulse from one part of a system to another part. In such an application, it is necessary to keep the distortion in the pulse shape as small as possible. This can be accomplished by selecting the time constant τ to be much longer than the pulse width T. If this is indeed the case, the loss in amplitude during the pulse period T will be very small, as shown in Fig. E.14(b). Nevertheless, the output waveform still swings negatively, and the area under the negative portion will be equal to that under the positive portion.
Consider the waveform in Fig. E.14(b). Since τ is much larger than T, it follows that the por-tion of the exponential curve from t = 0 to t = T will be almost linear and that its slope will be Figure E.13 Pulse responses of three STC low-pass circuits.
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E.5 Pulse Response of STC Circuits E-15 equal to the slope of the exponential curve at t = 0, which is Pτ. We can use this value of the slope to determine the loss in amplitude ∆P as (E.14) The distortion effect of the high-pass circuit on the input pulse is usually specified in terms of the per-unit or percentage loss in pulse height. This quantity is taken as an indication of the “sag” in the output pulse, (E.15) Thus (E.16) Finally, note that the magnitude of the undershoot at t = T is equal to ∆P.
The other extreme case—namely, τ T—is illustrated in Fig. E.14(c). In this case, the expo-nential decay is quite rapid, resulting in the output becoming almost zero shortly beyond the lead-ing edge of the pulse. At the trailing edge of the pulse, the output swings negatively by an amount almost equal to the pulse height P. Then the waveform decays rapidly to zero. As seen from Fig. E.14(c), the output waveform bears no resemblance to the input pulse. It consists of two spikes: a positive one at the leading edge and a negative one at the trailing edge. Note that the out-put waveform is approximately equal to the time derivative of the input pulse. That is, for τ T, an STC high-pass circuit approximates a differentiator. However, the resulting differentiator is not an ideal one; an ideal differentiator would produce two impulses. Nevertheless, high-pass STC circuits with short time constants are employed in some applications to produce sharp pulses or spikes at the transitions of an input waveform. Figure E.14 Pulse responses of three STC high-pass circuits.
∆P P τ --- T Percentage sag ∆P P -------100 × ≡ Percentage sag = T τ ---100 × ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
E-16 Appendix E Single-Time-Constant Circuits EXERCISES E.12 Find the rise and fall times of a 1-µs pulse after it has passed through a low-pass RC circuit with a corner frequency of 10 MHz.
Ans. 35 ns E.13 Consider the pulse response of a low-pass STC circuit, as shown in Fig. E.13(c). If τ = 100T, find the output voltage at t = T. Also, find the difference in the slope of the rising portion of the output waveform at t = 0 and t = T (expressed as a percentage of the slope at t = 0).
Ans. 0.01P; 1% E.14 The output of an amplifier stage is connected to the input of another stage via a capacitance C. If the first stage has an output resistance of 10 kΩ, and the second stage has an input resistance of 40 kΩ, find the minimum value of C such that a 10-µs pulse exhibits less than 1% sag.
Ans. 0.02 µF E.15 A high-pass STC circuit with a time constant of 100 µs is excited by a pulse of 1-V height and 100-µs width. Calculate the value of the undershoot in the output waveform.
Ans. 0.632 V PROBLEMS E.1 Consider the circuit of Fig. E.3(a) and the equivalent shown in (d) and (e). There, the output, vO = vO1 + vO2, is the sum of outputs of a low-pass and a high-pass circuit, each with the time constant τ = (C1 + C2)(R1|| R2). What is the condition that makes the contribution of the low-pass cir-cuit at zero frequency equal to the contribution of the high-pass circuit at infinite frequency? Show that this condition can be expressed as C1R1 = C2R2. If this condition applies, sketch versus frequency for the case R1 = R2.
E.2 Use the voltage divider rule to find the transfer func-tion Vo(s)/Vi(s) of the circuit in Fig. E.3(a). Show that the transfer function can be made independent of frequency if the condition C1R1 = C2R2 applies. Under this condition the circuit is called a compensated attenuator. Find the transmis-sion of the compensated attenuator in terms of R1 and R2.
DE.3 The circuit of Fig. E.3(a) is used as a compen-sated attenuator (see Problems E.1 and E.2) for an oscillo-scope probe. The objective is to reduce the signal voltage applied to the input amplifier of the oscilloscope, with the signal attenuation independent of frequency. The probe itself includes R1 and C1, while R2 and C2 model the oscil-loscope input circuit. For an oscilloscope having an input resistance of 1 MΩ and an input capacitance of 30 pF, design a compensated “10-to-1 probe”—that is, a probe that attenuates the input signal by a factor of 10. Find the input impedance of the probe when connected to the oscil-loscope, which is the impedance seen by vI in Fig. E.3(a).
Show that this impedance is 10 times higher than that of the oscilloscope itself. This is the great advantage of the 10:1 probe.
E.4 In the circuits of Figs. E.4 and E.5, let L = 10 mH, C = 0.01 µF, and R = 1 kΩ . At what frequency does a phase angle of 45° occur?
E.5 Consider a voltage amplifier with an open-circuit voltage gain Avo = −100 V/V , Ro = 0, Ri = 10 kΩ, and an input capacitance Ci (in parallel with Ri) of 10 pF. The amplifier has a feedback capacitance (a capacitance con-nected between output and input) Cf = 1 pF. The amplifier is fed with a voltage source Vs having a resistance Rs = 10 kΩ. Find the amplifier transfer function Vo(s)/Vs(s) and sketch its magnitude response versus frequency (dB vs. fre-quency) on a log axis.
E.6 For the circuit in Fig. PE.6, assume the voltage amplifier to be ideal. Derive the transfer function V o(s)/Vi(s). What type of STC response is this? For C = 0.01 µF and R = 100 kΩ, find the corner frequency.
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E.5 Pulse Response of STC Circuits E-17 Figure PE.6 E.7 For the circuits of Figs. E.4(b) and E.5(b), find vO(t) if vI is a 10-V step, R = 1 kΩ , and L = 1 mH.
E.8 Consider the exponential response of an STC low-pass circuit to a 10-V step input. In terms of the time constant τ, find the time taken for the output to reach 5 V , 9 V , 9.9 V , and 9.99 V .
E.9 The high-frequency response of an oscilloscope is specified to be like that of an STC LP circuit with a 100-MHz corner frequency. If this oscilloscope is used to display an ideal step waveform, what rise time (10% to 90%) would you expect to observe?
E.10 An oscilloscope whose step response is like that of a low-pass STC circuit has a rise time of ts seconds. If an input signal having a rise time of tw seconds is displayed, the waveform seen will have a rise time td seconds, which can be found using the empirical formula If ts = 35 ns, what is the 3-dB frequency of the oscilloscope? What is the observed rise time for a waveform rising in 100 ns, 35 ns, and 10 ns? What is the actual rise time of a waveform whose dis-played rise time is 49.5 ns?
E.11 A pulse of 10-ms width and 10-V amplitude is trans-mitted through a system characterized as having an STC high-pass response with a corner frequency of 10 Hz. What undershoot would you expect?
E.12 An RC differentiator having a time constant τ is used to implement a short-pulse detector. When a long pulse with T τ is fed to the circuit, the positive and negative peak outputs are of equal magnitude. At what pulse width does the negative output peak differ from the positive one by 10%?
E.13 A high-pass STC circuit with a time constant of 1 ms is excited by a pulse of 10-V height and 1-ms width. Calcu-late the value of the undershoot in the output waveform. If an undershoot of 1 V or less is required, what is the time constant necessary?
E.14 A capacitor C is used to couple the output of an amplifier stage to the input of the next stage. If the first stage has an output resistance of 2 kΩ and the second stage has an input resistance of 3 kΩ , find the value of C so that a 1-ms pulse exhibits less than 1% sag. What is the associated 3-dB frequency?
DE.15 An RC differentiator is used to convert a step voltage change V to a single pulse for a digital-logic application. The logic circuit that the differentiator drives distinguishes signals above V/2 as “high” and below V/2 as “low.” What must the time constant of the circuit be to convert a step input into a pulse that will be interpreted as “high” for 10 µs?
DE.16 Consider the circuit in Fig. E.7(a) with µ = –100, Cf = 100 pF, and the amplifier being ideal. Find the value of R so that the gain has a 3-dB frequency of 1 kHz.
td = ts 2 tw 2 .
+ Vo V ⁄ s APPENDIX E PROBLEMS ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
F-1 APPENDIX F s-DOMAIN ANALYSIS: POLES, ZEROS, AND BODE PLOTS In analyzing the frequency response of an amplifier, most of the work involves finding the amplifier voltage gain as a function of the complex frequency s. In this s-domain analysis, a capacitance C is replaced by an admittance sC, or equivalently an impedance , and an inductance L is replaced by an impedance sL. Then, using usual circuit-analysis techniques, one derives the voltage transfer function .
Once the transfer function T(s) is obtained, it can be evaluated for physical frequencies by replacing s by jω. The resulting transfer function T( jω) is in general a complex quantity whose magnitude gives the magnitude response (or transmission) and whose angle gives the phase response of the amplifier.
In many cases it will not be necessary to substitute s = jω and evaluate T( jω); rather, the form of T(s) will reveal many useful facts about the circuit performance. In general, for all 1 sC ⁄ T s ( ) V o s ( ) Vi s ( ) ⁄ ≡ EXERCISE F.1 Find the voltage transfer function for the STC network shown in Fig. EF.1.
Figure EF.1 Ans. T s ( ) V o s ( ) Vi s ( ) ⁄ ≡ Vi R2 R1 C Vo T s ( ) 1 CR1 ⁄ s + 1 C R1 R2 || ( ) ⁄ ------------------------------------------= ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
F-2 Appendix F s-Domain Analysis: Poles, Zeros, and Bode Plots the circuits dealt with in this book, T(s) can be expressed in the form (F.1) where the coefficients a and b are real numbers, and the order m of the numerator is smaller than or equal to the order n of the denominator; the latter is called the order of the network. Furthermore, for a stable circuit—that is, one that does not generate signals on its own—the denominator coefficients should be such that the roots of the denominator polynomial all have negative real parts. The problem of amplifier stability is studied in Chapter 10.
F.1 Poles and Zeros An alternate form for expressing T(s) is (F.2) where am is a multiplicative constant (the coefficient of sm in the numerator), Z1, Z2, . . . , Zm are the roots of the numerator polynomial, and P1, P2, . . ., Pn are the roots of the denominator polynomial. Z1, Z2, . . . , Zm are called the transfer-function zeros or transmission zeros, and P1, P2, . . . , Pn are the transfer-function poles or the natural modes of the network. A transfer function is completely specified in terms of its poles and zeros together with the value of the multiplicative constant.
The poles and zeros can be either real or complex numbers. However, since the a and b coefficients are real numbers, the complex poles (or zeros) must occur in conjugate pairs.
That is, if 5 + j3 is a zero, then 5 − j3 also must be a zero. A zero that is purely imaginary (±jωZ) causes the transfer function T( jω) to be exactly zero at ω = ωZ. This is because the numerator will have the factors (s + jωZ)(s − jωZ) = (s2 + ), which for physical frequen-cies becomes (−ω 2 + ), and thus the transfer fraction will be exactly zero at ω = ωZ. Thus the “trap” one places at the input of a television set is a circuit that has a transmission zero at the particular interfering frequency. Real zeros, on the other hand, do not produce transmis-sion nulls. Finally, note that for values of s much greater than all the poles and zeros, the transfer function in Eq. (F.1) becomes . Thus the transfer function has (n −m) zeros at s = ∞.
F.2 First-Order Functions Many of the transfer functions encountered in this book have real poles and zeros and can therefore be written as the product of first-order transfer functions of the general form (F.3) where −ω0 is the location of the real pole. The quantity ω0, called the pole frequency, is equal to the inverse of the time constant of this single-time-constant (STC) network (see Appendix E). The constants a0 and a1 determine the type of STC network. Specifically, we T s ( ) amsm am−1sm−1 … a0 + + + sn bn−1sn−1 … b0 + + + ----------------------------------------------------------------= T s ( ) am s Z1 – ( ) s Z2 – ( )… s Zm – ( ) s P1 – ( ) s P2 – ( )… s Pn – ( ) ----------------------------------------------------------------= ωZ 2 ωZ 2 T s ( ) am sn−m ⁄ T s ( ) a1s a0 + s ω0 + -------------------= ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
F.3 Bode Plots F-3 studied in Chapter 1 two types of STC networks, low pass and high pass. For the low-pass first-order network we have (F.4) In this case the dc gain is , and ω0 is the corner or 3-dB frequency. Note that this transfer function has one zero at s = ∞. On the other hand, the first-order high-pass transfer function has a zero at dc and can be written as (F.5) At this point the reader is strongly urged to review the material on STC networks and their frequency and pulse responses in Appendix E. Of specific interest are the plots of the magni-tude and phase responses of the two special kinds of STC networks. Such plots can be employed to generate the magnitude and phase plots of a high-order transfer function, as explained below.
F.3 Bode Plots A simple technique exists for obtaining an approximate plot of the magnitude and phase of a transfer function given its poles and zeros. The technique is particularly useful in the case of real poles and zeros. The method was developed by H. Bode, and the resulting diagrams are called Bode plots.
A transfer function of the form depicted in Eq. (F.2) consists of a product of factors of the form s + a, where such a factor appears on top if it corresponds to a zero and on the bot-tom if it corresponds to a pole. It follows that the magnitude response in decibels of the net-work can be obtained by summing together terms of the form 20 log10 , and the phase response can be obtained by summing terms of the form tan−1( ). In both cases the terms corresponding to poles are summed with negative signs. For convenience we can extract the constant a and write the typical magnitude term in the form 20 log .
On a plot of decibels versus log frequency this term gives rise to the curve and straight-line asymptotes shown in Fig. F.1. Here the low-frequency asymptote is a horizontal straight line Figure F.1 Bode plot for the typical magnitude term. The curve shown applies for the case of a zero. For a pole, the high-frequency asymptote should be drawn with a –6-dB/octave slope.
T s ( ) a0 s ω0 + ---------------= a0 ω0 ⁄ T s ( ) a1s s ω0 + ---------------= a2 ω2 + ω a ⁄ 1 ω a ⁄ ( )2 + 1 (/a)2 (dB) 0 dB Actual curve 6 dB/octave ( 20 dB/decade) 3 dB (log scale) 3dB a 1 20 log ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
F-4 Appendix F s-Domain Analysis: Poles, Zeros, and Bode Plots at 0-dB level and the high-frequency asymptote is a straight line with a slope of 6 dB/octave or, equivalently, 20 dB/decade. The two asymptotes meet at the frequency ω = , which is called the corner frequency. As indicated, the actual magnitude plot differs slightly from the value given by the asymptotes; the maximum difference is 3 dB and occurs at the corner frequency.
For a = 0—that is, a pole or a zero at s = 0—the plot is simply a straight line of 6 dB/ octave slope intersecting the 0-dB line at ω = 1.
In summary, to obtain the Bode plot for the magnitude of a transfer function, the asymp-totic plot for each pole and zero is first drawn. The slope of the high-frequency asymptote of the curve corresponding to a zero is +20 dB/decade, while that for a pole is −20 dB/decade.
The various plots are then added together, and the overall curve is shifted vertically by an amount determined by the multiplicative constant of the transfer function. a Example F.1 An amplifier has the voltage transfer function Find the poles and zeros and sketch the magnitude of the gain versus frequency. Find approximate values for the gain at ω = 10, 103, and 106 rad/s.
Solution The zeros are as follows: one at s = 0 and one at s = ∞. The poles are as follows: one at s = –102 rad/s and one at s = –105 rad/s.
Figure F.2 shows the asymptotic Bode plots of the different factors of the transfer function. Curve 1, which is a straight line intersecting the ω-axis at 1 rad/s and having a +20 dB/decade slope, corresponds to the s term (that is, the zero at s = 0) in the numerator. The pole at s = –102 results in curve 2, which consists of two asymptotes intersecting at ω = 102. Similarly, the pole at s = –105 is represented by curve 3, where the inter-section of the asymptotes is at ω = 105. Finally, curve 4 represents the multiplicative constant of value 10.
T s ( ) = 10s 1 s 102 ⁄ + ( ) 1 s 105 ⁄ + ( ) ----------------------------------------------------------Figure F.2 Bode plots for Example F.1.
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F.3 Bode Plots F-5 We next consider the Bode phase plot. Figure F.3 shows a plot of the typical phase term tan–1(ω/a), assuming that a is negative. Also shown is an asymptotic straight-line approxi-mation of the arctan function. The asymptotic plot consists of three straight lines. The first is horizontal at φ = 0 and extends up to The second line has a slope of –45°/decade and extends from to The third line has a zero slope and a level of φ = –90°. The complete phase response can be obtained by summing the asymptotic Bode plots of the phase of all poles and zeros. Adding the four curves results in the asymptotic Bode diagram of the amplifier gain (curve 5). Note that since the two poles are widely separated, the gain will be very close to 103 (60 dB) over the frequency range 102 to 105 rad/s. At the two corner frequencies (102 and 105 rad/s) the gain will be approximately 3 dB below the maximum of 60 dB. At the three specific frequencies, the values of the gain as obtained from the Bode plot and from exact evaluation of the transfer function are as follows: ω Approximate Gain Exact Gain 10 40 dB 39.96 dB 103 60 dB 59.96 dB 106 40 dB 39.96 dB Figure F.3 Bode plot of the typical phase term tan–1(ω/a) when a is negative.
ω = 0.1 a .
ω = 0.1 a ω = 10 a .
Example F.2 Find the Bode plot for the phase of the transfer function of the amplifier considered in Example F.1.
Solution The zero at s = 0 gives rise to a constant +90° phase function represented by curve 1 in Fig. F.4. The pole at s = –102 gives rise to the phase function φ1 = tan 1 – ω 102 --------– ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
F-6 Appendix F s-Domain Analysis: Poles, Zeros, and Bode Plots F.4 An Important Remark For constructing Bode plots, it is most convenient to express the transfer-function factors in the form The material of Figs. F.1 and F.2 and of the preceding two examples is then directly applicable.
(the leading minus sign is due to the fact that this singularity is a pole). The asymptotic plot for this function is given by curve 2 in Fig. F.4. Similarly, the pole at s = –105 gives rise to the phase function whose asymptotic plot is given by curve 3. The overall phase response (curve 4) is obtained by direct sum-mation of the three plots. We see that at 100 rad/s, the amplifier phase leads by 45° and at 105 rad/s the phase lags by 45°.
Figure F.4 Phase plots for Example F.2.
φ2 = tan 1 – ω 105 --------– (1 s a ⁄ ) + .
PROBLEMS F.1 Find the transfer function of the cir-cuit in Fig. PF.1. Is this an STC network? If so, of what type?
For C1 = C2 = 0.5 µF and R = 100 kΩ, find the location of the pole(s) and zero(s), and sketch Bode plots for the magni-tude response and the phase response.
Figure PF.1 T s ( ) = V o s ( ) Vi s ( ) ⁄ C2 R Vo C1 Vi Vo C1 Vi ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
F.4 An Important Remark F-7 APPENDIX F PROBLEMS DF.2 (a) Find the voltage transfer function , for the STC network shown in Fig. PF.2.
Figure PF.2 (b) In this circuit, capacitor C is used to couple the signal source Vs having a resistance Rs to a load RL. For Rs = 10 kΩ, design the circuit, specifying the values of RL and C to only one significant digit to meet the following requirements: (i) The load resistance should be as small as possible.
(ii) The output signal should be at least 70% of the input at high frequencies.
(iii) The output should be at least 10% of the input at 10 Hz. F.3 Two STC RC circuits, each with a pole at 100 rad/s and a maximum gain of unity, are connected in cascade with an intervening unity-gain buffer that ensures that they function separately. Characterize the possible combinations (of low-pass and high-pass circuits) by providing (i) the relevant trans-fer functions, (ii) the voltage gain at 10 rad/s, (iii) the voltage gain at 100 rad/s, and (iv) the voltage gain at 1000 rad/s.
F.4 Design the transfer function in Eq. (F.5) by specifying a1 and ω0 so that the gain is 10 V/V at high frequencies and 1 V/V at 10 Hz.
F.5 An amplifier has a low-pass STC frequency response.
The magnitude of the gain is 20 dB at dc and 0 dB at 100 kHz.
What is the corner frequency? At what frequency is the gain 19 dB? At what frequency is the phase −6°?
F.6 A transfer function has poles at (−5), (−7 + j10), and (−20), and a zero at (−1 − j20). Since this function represents an actual physical circuit, where must other poles and zeros be found?
F.7 An amplifier has a voltage transfer function Convert this to the form convenient for constructing Bode plots [that is, place the denominator factors in the form (1+s/a)]. Provide a Bode plot for the magnitude response, and use it to find approximate values for the amplifier gain at 1, 10, 102, 103, 104, and 105 rad/s.
What would the actual gain be at 10 rad/s? At 103 rad/s?
F.8 Find the Bode phase plot of the transfer function of the amplifier considered in Problem F.7. Estimate the phase angle at 1, 10, 102, 103, 104, and 105 rad/s. For comparison, calculate the actual phase at 1, 10, and 100 rad/s.
F.9 A transfer function has the following zeros and poles: one zero at s = 0 and one zero at s = ∞; one pole at s = −100 and one pole at s = −106. The magnitude of the transfer function at ω = 104 rad/s is 100. Find the transfer function T(s) and sketch a Bode plot for its magnitude.
F.10 Sketch Bode plots for the magnitude and phase of the transfer function From your sketches, determine approximate values for the magnitude and phase at ω = 106 rad/s. What are the exact values determined from the transfer function?
F.11 A particular amplifier has a voltage transfer function Find the poles and zeros. Sketch the magnitude of the gain in dB versus frequency on a logarithmic scale. Estimate the gain at 100, 103, 105, and 107 rad/s.
F.12 A direct-coupled differential amplifier has a differen-tial gain of 100 V/V with poles at 106 and 108 rad/s, and a common-mode gain of 10−3 V/V with a zero at 104 rad/s and a pole at 108 rad/s. Sketch the Bode magnitude plots for the differential gain, the common-mode gain, and the CMRR.
What is the CMRR at 107 rad/s? (Hint: Division of magni-tudes corresponds to subtraction of logarithms.) T s ( ) = V o s ( ) Vi s ( ) ⁄ Rs C Vs Vo RL T s ( ) = 106s s 10 + ( ) s 103 + ( ).
⁄ T s ( ) 104 1 s 105 ⁄ + ( ) 1 s 103 ⁄ + ( ) 1 s 104 ⁄ + ( ) ----------------------------------------------------------= T s ( ) = 10s2 1 s 10 ⁄ + ( ) 1 s 100 ⁄ + ( ) 1 s 106 ⁄ + ( ).
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G-1 APPENDIX G BIBLIOGRAPHY HISTORY OF ELECTRONICS L. Berlin, The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley, New York: Oxford University Press, 2005.
T.R. Reid, The Chip, New York: Random House, 2001.
J.N. Shurkin, Broken Genius: The Rise and Fall of Wil-liam Shockley, Creator of the Electronic Age, New York, Macmillan, 2008.
J. Williams, editor, Analog Circuit Design: Art, Sci-ence, and Personalities, Boston: Butterworth-Heinemann, 1991.
IEEE Solid-State Circuits Magazine, and its predeces-sor, IEEE Solid-State Circuits Newsletter, pub-lished quarterly by the IEEE Solid-State Circuits Society.
GENERAL TEXTBOOKS ON ELECTRONIC CIRCUITS E.F. Angelo Jr., Electronics: BJTs, FETs, and Micro-circuits, New York: McGraw-Hill, 1969.
S.B. Burns and P.R. Bond, Principles of Electronic Cir-cuits, St. Paul: West, 1987.
M.S. Ghausi, Electronic Devices and Circuits: Discrete and Integrated, New York: Holt, Rinehart and Winston, 1985.
P.E. Gray and C.L. Searle, Electronic Principles, New York: Wiley, 1969.
A.R. Hambley, Electronics, 2nd ed., Upper Saddle Riv-er, NJ: Prentice-Hall, 1999.
W.H. Hayt and G.W. Neudeck, Electronic Circuit Anal-ysis and Design, 2nd ed., Boston: Houghton Mifflin Co., 1984.
C.A. Holt, Electronic Circuits, New York: Wiley, 1978.
M.N. Horenstein, Microelectronic Circuits and Devices, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1995.
R.T. Howe and C.G. Sodini, Microelectronics—An Integrated Approach, Englewood Cliffs, NJ: Prentice-Hall, 1997.
R.C. Jaeger and T.N. Blalock, Microelectronic Circuit Design, 3rd ed., New York: McGraw-Hill, 2008.
N.R. Malik, Electronic Circuits: Analysis, Simula-tion, and Design, Englewood Cliffs, NJ: Prentice-Hall, 1995.
J. Millman and A. Grabel, Microelectronics, 2nd ed., New York: McGraw-Hill, 1987.
D.A. Neamen, Electronic Circuit Analysis and Design, 3rd ed., New York: McGraw-Hill, 2007.
M.H. Rashid, Microelectronic Circuits: Analysis and Design, Boston: PWS, 1999.
B. Ravazi, Fundamentals of Microelectronics, Hoboken, NJ: Wiley, 2008.
D.L. Schilling and C. Belove, Electronic Circuits, 2nd ed., New York: McGraw-Hill, 1979.
R.A. Spencer and M.S. Ghausi, Introduction to Elec-tronic Circuit Design, Upper Saddle River, NJ: Pearson Education Inc. (Prentice-Hall), 2003.
CIRCUIT AND SYSTEM ANALYSIS L.S. Bobrow, Elementary Linear Circuit Analysis, 2nd ed., New York: Holt, Rinehart and Winston, 1987.
A.M. Davis, Linear Circuit Analysis, Boston, PWS Publishing Company, 1998.
S.S. Haykin, Active Network Theory, Reading, MA: Addison-Wesley, 1970.
W.H. Hayt, G.E. Kemmerly, and S.M. Durbin, Engi-neering Circuit Analysis, 6th ed., New York: McGraw-Hill, 2003.
D. Irwin, Basic Engineering Circuit Analysis, 7th ed., New York: Wiley, 2001.
B.P. Lathi, Linear Systems and Signals, New York: Ox-ford University Press, 1992.
J.W. Nilsson and S. Riedel, Electronic Circuits, 7th ed., Upper Saddle River, NJ: Prentice-Hall, 2005. DEVICES AND IC FABRICATION R.S.C. Cobbold, Theory and Applications of Field Ef-fect Transistors, New York: Wiley, 1969.
I. Getreu, Modeling the Bipolar Transistor, Beaverton, OR: Tektronix, Inc., 1976.
R.S. Muller and T.I. Kamins, Device Electronics for In-tegrated Circuits, 3rd ed., New York: Wiley, 2003.
J.D. Plummer, M.D. Deal, and P.B. Griffin, Silicon VLSI Technology, Upper Saddle River, NJ: Prentice-Hall, 2000.
D.L. Pulfrey and N.G. Tarr, Introduction to Microelec-tronic Devices, Englewood Cliffs, NJ: Prentice-Hall, 1989.
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G-2 Appendix G Bibliography C.L. Searle, A.R. Boothroyd, E.J. Angelo, Jr., P.E.
Gray, and D.O. Pederson, Elementary Circuit Properties of Transistors, Vol. 3 of the SEEC Se-ries, New York: Wiley, 1964. B.G. Streetman and S. Banerjee, Solid-State Electronic Devices, 5th ed., Upper Saddle River, NJ: Prentice-Hall, 2000.
Y. Tsividis, Operation and Modeling of the MOS Tran-sistor, 2nd ed., New York: Oxford University Press, 1999. OPERATIONAL AMPLIFIERS G.B. Clayton, Experimenting with Operational Ampli-fiers, London: Macmillan, 1975.
G.B. Clayton, Operational Amplifiers, 2nd ed., Lon-don: Newnes-Butterworths, 1979.
S. Franco, Design with Operational Amplifiers and An-alog Integrated Circuits, 3rd ed., New York: McGraw-Hill, 2001.
J.G. Graeme, G.E. Tobey, and L.P. Huelsman, Opera-tional Amplifiers: Design and Applications, New York: McGraw-Hill, 1971.
W. Jung, IC Op Amp Cookbook, Indianapolis: Howard Sams, 1974. E.J. Kennedy, Operational Amplifier Circuits: Theory and Applications, New York: Holt, Rinehart and Winston, 1988. J.K. Roberge, Operational Amplifiers: Theory and Practice, New York: Wiley, 1975.
J.L. Smith, Modern Operational Circuit Design, New York: Wiley-Interscience, 1971.
J.V. Wait, L.P. Huelsman, and G.A. Korn, Introduction to Operational Amplifiers: Theory and Applica-tions, New York: McGraw-Hill, 1975. ANALOG CIRCUITS P.E. Allen and D.R. Holberg, CMOS Analog Circuit Design, 2nd ed., New York: Oxford University Press, 2002.
K. Bult, Transistor-Level Analog IC Design. Notes for a short course organized by Mead, Ecole Polytechnique Féderal de Lausanne, 2002.
M.J. Fonderic and J.H. Huising, Design of Low-Voltage Bipolar Operational Amplifiers, Boston: Kluwer Academic Publishers, 1993.
R.L. Geiger, P.E. Allen, and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, New York: McGraw-Hill, 1990. P.R. Gray, P.J. Hurst, S.H. Lewis, and R.G. Meyer, Analysis and Design of Analog Integrated Cir-cuits, 5th ed., Hoboken, NJ: Wiley, 2008.
A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley, 1984. R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley, 1986.
J.H. Huising, Operational Amplifiers, Boston: Kluwer Academic Publishers, 2001.
IEEE Journal of Solid-State Circuits, a monthly publi-cation of the IEEE.
D.A. Johns and K. Martin, Analog Integrated Circuit Design, New York: Wiley, 1997. K. Laker and W. Sansen, Design for Analog Integrated Circuits and Systems, New York: McGraw-Hill, 1999. H.S. Lee, “Analog Design,” Chapter 8 in BiCMOS Technology and Applications, A.R. Alvarez, edi-tor, Boston: Kluwer Academic Publishers, 1989.
National Semiconductor Corporation, Audio/Radio Handbook, Santa Clara, CA: National Semicon-ductor Corporation, 1980. B. Razavi, Design of Analog CMOS Integrated Cir-cuits, New York: McGraw-Hill, 2001. J.K. Roberge, Operational Amplifiers: Theory and Practice, New York: Wiley, 1975. S. Rosenstark, Feedback Amplifier Principles, New York: Macmillan, 1986.
W.M.C. Sansen, Analog Design Essentials, Dordrecht, The Netherlands: Springer, 2006.
A.S. Sedra and G.W. Roberts, “Current Conveyor Theo-ry and Practice,” Chapter 3 in Analogue IC Design: The Current-Mode Approach, C. Toumazou, F.J.
Lidgey, and D.G. Haigh, editors, London: Peter Peregrinus, 1990. R. Severns, editor, MOSPOWER Applications Hand-book, Santa Clara, CA: Siliconix, 1984. Texas Instruments, Inc., Power Transistor and TTL Integrated-Circuit Applications, New York: McGraw-Hill, 1977. S. Soclof, Applications of Analog Integrated Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1985. J.M. Steininger, “Understanding wideband MOS tran-sistors,” IEEE Circuits and Devices, Vol. 6, No. 3, pp. 26–31, May 1990.
DIGITAL CIRCUITS A.R. Alvarez, editor, BiCMOS Technology and Appli-cations, 2nd ed., Boston: Kluwer Academic Pub-lishers, 1993.
S.H.K Embabi, A. Bellaour, and M.I. Elmasry, Digital BiCMOS Integrated Circuit Design, Boston: Kluw-er, 1993. M.I. Elmasry, editor, Digital MOS Integrated Circuits, New York: IEEE Press, 1981. Also, Digital MOS Integrated Circuits II, 1992.
D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits, 3rd ed., New York: McGraw-Hill, 2004. IEEE Journal of Solid-State Circuits, a monthly publi-cation of the IEEE. S.M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, 3rd ed., New York: McGraw-Hill, 2003.
R. Littauer, Pulse Electronics, New York: McGraw-Hill, 1965.
K. Martin, Digital Integrated Circuit Design, New York: Oxford University Press, 2000.
J. Millman and H. Taub, Pulse, Digital, and Switching Waveforms, New York: McGraw-Hill, 1965.
Motorola, MECL Device Data, Phoenix, AZ: Motorola Semiconductor Products, Inc., 1989.
Motorola, MECL System Design Handbook, Phoe-nix, AZ: Motorola Semiconductor Products, Inc., 1988. ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
Bibliography G-3 J.M. Rabaey, Digital Integrated Circuits, Englewood Cliffs, NJ: Prentice-Hall, 1996. Note: A 2nd ed., with A. Chandrakasan and B. Nikolic, also appeared in 2003.
L. Strauss, Wave Generation and Shaping, 2nd ed., New York: McGraw-Hill, 1970.
H. Taub and D. Schilling, Digital Integrated Electron-ics, New York: McGraw-Hill, 1977. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Reading, MA: Addison-Wesley, 1985 and 1993.
FILTERS AND TUNED AMPLIFIERS P.E. Allen and E. Sanchez-Sinencio, Switched-Capaci-tor Circuits, New York: Van Nostrand Reinhold, 1984.
K.K. Clarke and D.T. Hess, Communication Circuits: Analysis and Design, Ch. 6, Reading, MA: Addi-son Wesley, 1971. G. Daryanani, Principles of Active Network Synthesis and Design, New York: Wiley, 1976.
R. Gregorian and G.C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York: Wiley-Interscience, 1986. C. Ouslis and A. Sedra, “Designing custom filters,” IEEE Circuits and Devices, May 1995, pp. 29–37. S.K. Mitra and C.F. Kurth, editors, Miniaturized and In-tegrated Filters, New York: Wiley-Interscience, 1989. R. Schaumann, M.S. Ghausi, and K.R. Laker, Design of Analog Filters, Englewood Cliffs, NJ: Prentice-Hall, 1990.
R. Schaumann, M. Soderstand, and K. Laker, editors, Modern Active Filter Design, New York: IEEE Press, 1981. R. Schaumann and M.E. Van Valkenburg, Design of Analog Filters, New York: Oxford University Press, 2001.
A.S. Sedra, “Switched-capacitor filter synthesis,” in MOS VLSI Circuits for Telecommunications, Y.
Tsividis and P. Antognetti, editors, Englewood Cliffs, NJ: Prentice-Hall, 1985.
A.S. Sedra and P.O. Brackett, Filter Theory and De-sign: Active and Passive, Portland, OR: Matrix, 1978. M.E. Van Valkenburg, Analog Filter Design, New York: Holt, Rinehart and Winston, 1981. A.I. Zverev, Handbook of Filter Synthesis, New York: Wiley, 1967.
SPICE M.E. Herniter, Schematic Capture with Cadence PSpice, 2nd ed., Upper Saddle River, NJ: Prentice-Hall, 2003. G. Massobrio and P. Antognetti, Semiconductor Device Modeling with SPICE, 2nd ed., New York: McGraw-Hill, 1993.
G.W. Roberts and A.S. Sedra, SPICE, New York: Ox-ford University Press, 1992 and 1997.
J.A. Svoboda, PSpice for Linear Circuits, New York: Wiley, 2002. P.W. Tuinenga, SPICE: A Guide to Circuit Simulation & Analysis Using PSpice, 2nd ed., Englewood Cliffs, NJ: Prentice-Hall, 1992. ©2010 Oxford University Press, Inc. Reprinting or distribution, electronically or otherwise, without the express written consent of Oxford University Press, Inc. is prohibited.
H-1 Discrete resistors are available only in standard values. Table H.1 provides the multipliers for the standard values of 5%-tolerance and 1%-tolerance resistors. Thus, in the kilohm Table H.1 Standard Resistance Values 1% Resistor Values (kΩ) 5% Resistor Values (kΩ) 100–174 178–309 316–549 562–976 10 100 178 316 562 11 102 182 324 576 12 105 187 332 590 13 107 191 340 604 15 110 196 348 619 16 113 200 357 634 18 115 205 365 649 20 118 210 374 665 22 121 215 383 681 24 124 221 392 698 27 127 226 402 715 30 130 232 412 732 33 133 237 422 750 36 137 243 432 768 39 140 249 442 787 43 143 255 453 806 47 147 261 464 825 51 150 267 475 845 56 154 274 487 866 62 158 280 499 887 68 162 287 511 909 75 165 294 523 931 82 169 301 536 953 91 174 309 549 976 APPENDIX H STANDARD RESISTANCE VALUES AND UNIT PREFIXES H-2 Appendix H Standard Resistance Values and Unit Prefixes range of 5% resistors, one finds resistances of 1.0, 1.1, 1.2, 1.3, 1.5, . . . . In the same range, one finds 1% resistors of kilohm values of 1.00, 1.02, 1.05, 1.07, 1.10, . . . .
Table H.2 provides the SI unit prefixes used in this book and in all modern works in English.
Table H.3 provides the meter conversion factors.
Table H.2 SI Unit Prefixes Name Symbol Factor femto f × 10−15 pico p × 10−12 nano n × 10−9 micro μ × 10−6 milli m × 10−3 kilo k × 103 mega M × 106 giga G × 109 tera T × 1012 peta P × 1015 Table H.3 Meter Conversion factors 1 μm = 10−4 cm = 10−6 m 1 m = 102 cm = 106 μm 0.1 μm = 100 nm 1 Å = 10−8 cm = 10−10 m I-1 CHAPTER 1 1.1 (a) 10 mA; (b) 10 kΩ; (c) 100 V; (d) 0.1 A 1.2 (a) 0.9 W, 1 W; (c) 0.09 W, 1/8 W; (f) 0.121 W, 1/8 W but preferably 1/4 W 1.4 17 1.7 2.94 V, 2.22 kΩ; 2.75 V to 3.14 V, 2.11 kΩ to 2.33 kΩ 1.9 10.2 V; shunt the 10-kΩ resistor a 157-kΩ resistor; add a series resistor of 200 Ω; shunt the 4.7-kΩ resistor with a 157 kΩ and the 10-kΩ resistor with 90 kΩ 1.11 250 Ω 1.13 Shunt RL with a 1.1-kΩ resistor; current divider 1.15 0.77 V and 6.15 kΩ; 0.1 mA 1.17 1.88 μA; 5.64 V 1.19 (a) 10−7 s, 107 Hz, 6.28 × 107 Hz; (f) 103 rad/s, 1.59 × 102 Hz, 6.28 × 10−3 s 1.21 (a) (1 − j1.59) kΩ; (c) (71.72 − j45.04) kΩ 1.22 (b) 0.1 V, 10 μA, 10 kΩ 1.24 10 kΩ 1.28 (a) 165 V; (b) 24 V 1.30 0.5 V; 1 V; 0 V; 1 V; 1000 Hz; 10−3 s 1.32 4 kHz; 4 Hz 1.34 0, 101, 1000, 11001, 111001 1.36 (c) 11; 4.9 mV; 2.4 mV 1.38 7.056 × 105 bits per second 1.40 11 V/V or 20.8 dB; 22 A/A or 26.8 dB; 242 W/W or 23.8 dB; 120 mW; 95.8 mW; 20.2% 1.42 9 mV; 57.5 mV; 0.573 V 1.43 (a) 8.26 V/V or 18.3 dB; (b) 2.5 V/V or 8 dB; (c) 0.083 V/V or −21.6 dB 1.46 0.83 V; −1.6 dB; 79.2 dB; 38.8 dB 1.51 (a) 300 V/V; (b) 90 kΩ, 3 × 104 A/A, 9 × 106 W/W; (c) 667 Ω; (d) 555.7 V/V; (e) 100 kΩ, 100 Ω, 363 V/V 1.57 Transconductance amplifier; 100 kΩ; 100 kΩ; 121 V/V 1.65 s/(s + 1/CR) 1.68 0.64 μF 1.71 0.51/CR 1.72 13.3 pF; 0.26 pF 1.75 20 dB; 37 dB; 40 dB; 37 dB; 20 dB; 0 dB; −20 dB; 9900 Hz 1.76 1/(sC1R1 + 1); 15.9 Hz; −Gms(R2//R3)/(s + 1/(C2(R2 + R3))); 53 Hz; 16 Hz CHAPTER 2 2.2 2002 V/V 2.5 20,000 V/V 2.8 (a) −10 V/V, 10 kΩ; (b) −10 V/V, 10 kΩ; (c) −10 V/V, 10 kΩ; (d) −10 V/V, 10 kΩ 2.11 (a) −1 V/V; (b) −10 V/V; (c) −0.1 V/V; (d) −100 V/V; (e) −10 V/V 2.12 (b) R1 = 10 kΩ, R2 = 20 kΩ (d) R1 = 10 kΩ, R2 = 1 MΩ 2.14 Rin = 50.1 kΩ 2.18 0 V, 5 V; −4.9 V to −5.1 V 2.20 (b) −66.4 V/V 2.21 ±5 mV 2.26 (b) 909 V/V 2.29 100 Ω; 100 Ω; 100 kΩ 2.31 (a) R, R, R, R; (b) I, 2I, 4I, 8I; (c) −IR, −2IR, −4IR, −8IR 2.34 (a) 1.11 kΩ; (b) 0 Ω, ∞ 2.36 vo = –(v1 + ½ v2); −1 V 2.43 12.8 kΩ 2.46 R = 100 kΩ; No 2.50 v0 = 4 sin(2π × 1000t) 2.53 (a) 0.099 V; 0.099 mA; 0.099 mA; (b) 10 V; 10 mA; 0 mA 2.54 vo ⁄ v1 = 1 ⁄ (1 + 1 ⁄Α); 0.999, −0.1%; 0.990, −1.0%; 0.909, −9.1% 2.56 8.33 V/V; Shunt R1 with Rsh = 36 kΩ; 9.09 V/V; 11.1 V/V 2.59 −10.714 to +10.714 V; 1.07 V 2.62 vo = v2 − v1; R; 2R; 2R; R 2.64 R1 = R3 2.66 68 dB 2.68 (a) 1, 0; (b) −5 V to +5 V; (c) 1, 0, −30 to +30 V 2.73 (a) −0.14 to +0.14 V; −14 to +14 V 2.76 R1 = 0.5 kΩ fixed; R2 = 50 kΩ 2.77 (a) 3 V/V, −3.0 V/V; (b) 6 V/V; (c) 56 V (peak-to-peak), 19.8 V (rms) 2.81 100 kHz; 1.59 μs 2.85 100 pulses 2.88 1.59 kHz; 10 V (peak-to-peak) 2.97 1.4 mV 2.99 57.5 mV; 42.5 to 57.5 mV; Add a 5-kΩ resistor in series with the positive input terminal; ±10 mV; add 5-kΩ resistor in series with the negative input load.
2.101 4.54 mV 2.104 (a) 0.1 V; (b) 0.2 V; (c) 10 kΩ, 10 mV; (d) 110 mV 2.108 46 dB; 501 Hz; 10 MHz 2.111 47.6 kHz; 19.9 V/V; 19.9 V/V APPENDIX I ANSWERS TO SELECTED PROBLEMS I-2 Appendix I Answers to Selected Problems 2.114 32 V/V 2.117 (a) ( – 1)1/2 f1; (b) 10 kHz; (c) 64.4 kHz, about six times greater 2.120 For each, f3dB = ft ⁄ 3 2.127 (a) 31.8 kHz; (b) 0.795 V; (c) 0 to 200 kHz; (d) 1 V peak CHAPTER 3 3.1 5.33 × 10–18; 3.05 × 10–14; 1.72 x 10–13; 2.87 × 10–11; 9.45 × 10–11 3.4 1.5 × 1017 P atoms/cm3 3.5 Hole concentration 2.25 × 104/cm3; 2.23 × 109/cm3 3.9 4.63 × 1017/cm3 3.10 0.432 A/cm2 3.11 Dn: 35, 28.5, 18.1, 9.3; Dp: 12.4, 10.4, 6.7, 3.9 3.13 0.633 V; 0.951 μm; 0.8642 μm; 0.8642 μm; 5.53 × 10–14 C 3.22 3.6 × 10–15 A; 0.6645 V 3.27 259 pS; 1 pF CHAPTER 4 4.1 (a) 0 A; 1.5 V; (b) 1.5 A; 0 V 4.2 (a) 5 V; 1 mA; (b) 5 V; 0 mA; (c) 5 V; 1 mA; (d) 5 V; 0 mA 4.8 50 kΩ 4.9 (a) 0 V; 0.3 mA; (b) 0.4 V; 0 mA 4.10 (a) 4.5 V; 0.225 mA; (b) 2 V; 0 A 4.15 29.67 V; 3.75 Ω; 0.75 A; 26.83 V; 30 V; 3 Ω; 20.5%; 136 mA; 1 A; 27 V 4.16 red lights; neither light; green lights 4.18 0.345 V; 1.45 × 1012IS 4.20 537 × 10−18 A; 0.746 mA; 27.32 mA; 0.335 mA; 9.17 μA; 57.56 mV 4.23 7.9 mA; −10.15 mV 4.26 194 Ω 4.29 50°C; 9 W; 5.56°C/W 4.33 0.6635 V; 0.3365 mA 4.35 R = 947 Ω 4.38 0.86 mA; 0 V; 0 A; 3.6 V 4.51 157 μA; −84.3° to −5.71° 4.58 −30 mV/mA; −120 mV/mA 4.60 8.96 V; 9.01 V; 9.46 V 4.63 8.83 V; 19.13 mA; 300 Ω; 9.14 V; ±0.01 V; +0.12 V; 578 Ω; 8.83 V; 90 mV/V; −27.3 mA/mA 4.68 16.27 V; 48.7%; 0.13; 5.06 V; 5.06 mA 4.69 16.27 V; 97.4%; 10.12 V; 10.12 mA 4.70 15.57 V; 94.8%; 9.44 V; 9.44 mA 4.72 55 V 4.75 (a) 166.7 μF; 15.4 V; 7.1%; 233 mA; 449 mA; (b) 1667 μF; 16.19 V; 2.25%; 735 mA; 1455 mA 4.76 (a) 83.3 μF; 15.5 V; 14.2%; 124.4 mA; 233 mA; (b) 833 μF; 16.19 V; 4.5%; 376 mA; 735 mA 4.79 (a) 23.6 V; (b) 444.4 μF; (c) 32.7 V; 49 V; (d) 0.73 A; (e) 1.36 A 4.91 14.14 V CHAPTER 5 5.2 1.875 fC 5.7 2.38 μm 5.12 Wp/Wn = 2.5 5.13 238 Ω; 238 mV; 50 5.14 (a) 7.3 mA; (b) 1.62 mA; 1.61 mA; 17.7 mA 5.17 3.5 V; 1.5 V; 500 Ω; 100 Ω 5.18 1.0 V; 0.5 V; 1.5 V; 1.0 V 5.22 0.3 V 5.23 100 Ω to 10 kΩ; (a) 200 Ω to 20 kΩ; (b) 50 Ω to 5 kΩ; (c) 100 Ω to 10 kΩ 5.31 500 kΩ; 50 kΩ; 2%; 2% 5.33 82.13 μA; 2.7%; use L = 6 μm 5.38 0.24 mA; 0.52 mA; 0.54 mA; 0.59 mA 5.39 −3 V; +3 V; −4 V; +4 V; −1 V; −50 V; −0.02 V−1; 1.39 mA/V2 5.42 (b) −0.3%/°C 5.46 R = 11.1 kΩ; R = 1.67 kΩ 5.49 25 μm; 1.875 kΩ 5.50 2 μm; 5.6 μm; 2.8 kΩ 5.52 0.395 mA; 7.6 V 5.57 (a) 0.9 V; −1.6 V; (b) 4.1 V; 2.5 V; 0.9 V 5.59 (a) 7.5 μA; 1.5 V; (b) 4.6 μA; 1.4 V; (c) 1.5 V; 7.5 μA 5.61 (a) 1 V; 1 V; −1.32 V; (b) 0.2 V; 1.8 V; −1.35 V 5.65 0.4 V; 8.33 5.71 (a) 125 µA; 0.8 V; (b) 1 mS; (c) −8.0 V/V; (d) 80 kΩ; −7.3 V/V 5.75 4 μm; 1.0 V 5.77 −18.2 V/V; 1.207 V; −23.6 V/V 5.78 NMOS: 424 µS, 160 kΩ, 0.47 V; PMOS: 245 µS, 240 kΩ, 0.82 V 5.100 3.39 V; 0.86 mA to 0.36 mA; 1.1 kΩ 5.101 1 mA; 7.6% 5.102 2 V; 2.40 V; 2.55 mA 5.106 (a) −1.5 V; +0.5 V; 2 V; (b) −1.37 V; +0.5 V; +1.87 V 5.108 15.9 kΩ; 0.314 mA; 1.82 V 5.110 −11.2 V/V CHAPTER 6 6.1 active; saturation; active; saturation; inversed active; active; cutoff; cutoff 6.8 53.3; 0.982 6.10 0.5; 0.667; 0.909; 0.952; 0.991, 0.995; 0.999; 0.9995 6.7 0.907 mA; 0.587 V 2 Answers to Selected Problems I-3 6.12 3 to 15 mA; 3.05 to 15.05 mA; 135 mW 6.17 −0.718 V; 4.06 V; 0.03 mA 6.22 −2 V; 0.82 mA; −0.57 V 6.24 0.91 mA; 9.09 mA; 0.803 V; 9.99 mA 6.28 (a) 1 mA; (b) −2 V; (c) 1 mA; 1 V; (d) 0.965 mA; 0.35 V 6.38 0.74 V; 0.54 V 6.40 3.35 μA 6.43 33.3 kΩ; 100 V; 3.3 kΩ 6.45 1.72 mA; 6 V; 34 V; 20 kΩ 6.47 150; 125; 1.474 mA 6.70 −360 V/V; 0.7 V, 2 mV 6.75 −100 V/V 6.78 3 mA; −120 V/V; −0.66 V; −0.6 V; 0.54 V; 0.6 V 6.51 (a) 1.3 V, 3.7 V; (b) 0.3 V, 4.7 V; (c) 0 V, +5 V 6.54 −0.7 V; +4.7 V; −0.5 V (−1 V; +5 V); +2.6 V (1.9 V, 2.6 V) 6.56 0.3 V; 15 μA; 0.8 mA; 0.785 mA; −1.075 V; 52.3; 0.98 6.61 (a) −0.7 V, 1.8 V; (b) 1.872 V, 1.955 mA; (c) −0.7 V, 0 V, 1.872 V; (d) 1.9 V, −0.209 V; (e) 1.224 V, 1.924 V, −0.246 V 6.64 1.08 kΩ; the transistor saturates.
6.94 1.25 V; 20 mA/V; 150 V/V 6.102 135; 41.8 Ω; 23 mA/V; 1.09 kΩ; −0.76 V/V 6.105 9.3 kΩ; 28.6 kΩ; 143 V/V 6.106 1 mA; 0.996 V/V; 0.63 V/V 6.152 (a) 1.73 mA, 68.5 mA/V, 14.5 Ω, 1.46 kΩ; (b) 148.2 kΩ, 0.93 V/V; (c) 18.21 kΩ, 0.64 V/V CHAPTER 7 7.15 0.905 V; 1.4 V2 7.19 (a) 0.5 mA; (b) 100 kΩ, 100 kΩ, 50 kΩ; (c) 2.5 kΩ, 20 mA/V; (d) 2.5 kΩ, 50 kΩ, −1000 V/V 7.46 10.5 kΩ; 0.25 V; 50 kΩ; 10 μA 7.49 100 μA; 0.2 V; 0.7 V; 5 μA 7.52 4: 25, 50, 200, 400 μA; 3: 16.7, 40, 133 μA; 1.05 V 7.54 (a) 10 μA to 10 mA; 0.633 to 0.806 V 7.57 0.2 mΑ; 10% 7.60 (a) 1.0 mΑ, −0.7 V, 3 V, 0.7 V, −5.7 V, −3.2 V; (b) 0.1 mA, −0.7 V, 3 V, 0.7 V, −0.7 V, −3.2 V 7.63 1.56 µA 7.64 8.93 MΩ; 0.95 V; 1.45 V; 100.4 µA 7.69 500 Ω 7.70 2 μA; 0.2% 7.76 (a) 5.7 kΩ; (b) 16.4 MΩ, 0.3 μA 7.78 7.46 MΩ 7.79 (a) 68.5 kΩ; (b) 112.5 MΩ 7.80 6.42 kΩ 7.84 12; 34 7.85 2.88 7.88 0.5 mA; 4 mA/V 7.93 16.7 GHz; 23.9 GHz; because the overlap capacitance is neglected.
7.94 15 V/V; 164.2 MHz; 2.5 GHz, 0.155 mA; quadrupled to 0.62 mA; 7.5 V/V; 656.8 MHz 7.97 5.3 MHz; 391 MHz CHAPTER 8 8.9 0.724 V; 3.57 mA/V; 0.317 V; 1.6 mA 8.11 −1.5 V; +0.5 V; equal in both cases; 0.05 V; −0.05 V; 0.536 V 8.32 −1.665 V; 0.52 V 8.34 −1.53 V to 0.92 V 8.38 (a) VCC − (I/2)RC; (b) −(I/2)RC, +(I/2)RC; (c) 4 V; (d) 0.4 mA, 10 kΩ 8.41 (a) 20IRC V/V; (b) VCC − 0.0275Av 8.43 IE1 = 2 mA, IE2 = 1 mA, IC1 = 2 mA, IC2 = 1 mA; 17.3 mV 8.45 4 mA/V; 75.5 kΩ 8.48 (a) 0.2 mA, 10 mV; (b) 0.7 mA, 0.3 mA; (c) −2.4 V, +2.4 V; (d) 48 V/V 8.59 50 V/V; 50.5 kΩ 8.60 50 V/V; 50.5 kΩ 8.63 25 V/V; 40.4 kΩ; 0.001 V/V; 6.56 MΩ 8.64 (a) 200 V/V; (b) 20.2 kΩ; (c) 0.0005 V/V; (d) 112 dB; (e) 9.76 mΩ 8.67 1.8 mA; 360 V/V; 1.8 sin ωt V 8.68 RE = 25 Ω; RC = 10 kΩ; Ro 50 kΩ; Ricm = 5 MΩ; ±12 V would do, ±15 V would be better.
8.69 2% 8.70 0.008 V/V 8.77 −125 μV 8.79 1.7 mVM 8.81 (a) 0.3; (b) 0 8.115 Rid 1 = 40.4 kΩ; Rid 2 = 10.1 kΩ; 20.2 V/V; 3823 V/V decrease 8.116 R5 = 7.34 kΩ; 4104 V/V; R4 = 1.11 kΩ 8.117 (a) 173.1 × 103 V/V (b) 5583 V/V 8.118 (a) 0.97 mA; (b) 2.23 kΩ, 129 Ω; (c) 2.86 × 104 V/V CHAPTER 9 9.1 1.43 V/V, 9.3 μF 9.4 −16 V/V; CC1 = 21.2 nF, CS = 9.6 μF; CC2 = 0.5 μF; 50 Hz 9.17 6.3 GHz 9.19 5.4 GHz 9.24 500 MHz, 600 MHz, 251.9 ps, 0.435 pF 9.25 0.69 pF; 40 mA/V; 4 kΩ; 50 MHz 9.33 (a) −15.9 V/V; (b) 40.1 kHz 9.45 (a) 2.07; (b) 7.02 9.46 (a) 104 rad/s; (b) 10.1 Κrad/s 9.47 5.67 × 106 rad/s I-4 Appendix I Answers to Selected Problems 9.54 40.6 V/V; 243.75 ns; 3100 ns; 300 ns; 43.7 kHz 9.58 (a) −1000 V/V, Ci = 1.001 nF, Co = 1.001 pF; (b) −10 V/V, Ci = 110 pF, Co = 11 pF; (c) −1 V/V, Ci = 20 pF, Co = 20 pF; (d) 1 V/V, Ci = 0 pF, Co = 0 pF; (e) 10 V/V, Ci = −90 pF, Co = 9 pF 9.62 6.37 GHz; 673.23 kHz; 21.39 MHz; 673.23 kHz 9.66 139 V/V; 21.22 GHz; 1.99 MHz; 83.22 MHz; 1.99 MHz 9.68 −80 V/V; 3.79 MHz; 303.2 MHz 9.72 159.1 fF 9.75 16 V/V; 398 MHz; 3.79 MHz; 3.79 MHz 9.88 0.964 V/V; 593.8 MHz 9.103 (a) 2.5 MΩ, −3943.6 V/V; (b) 107.8 kHz, (CL + Cμ2) dominates, Cμ2 or CT is the second most significant CHAPTER 10 10.1 9.99 × 10−3; 91.74; −8.26% 10.14 AMf = AM ⁄(1 + AMβ); WLf = WL ⁄(1 + AMβ) 10.16 1 MHz; 1 Hz 10.34 (a) h11 = R1R2/(R1 + R2) Ω, h12 = R2/(R1 + R2) V/V, h21 = −R2 /(R1 + R2) A/A, h22 = 1/(R1 + R2) Ω; (b) h11 = 10 Ω, h12 = 0.01 V/V, h21 = −0.01 A/V, h22 = 0.99 × 10−3 Ω 10.35 100 V/V; 1.001 MΩ 10.62 (a) shunt–series; (b) series– series; (c) shunt–shunt 10.80 104 rad/s; β = 0.002; 500 V/V 10.82 K < 0.008 10.84 9.9 V/V; 1.01 MHz; 10 MHz; 101 10.85 (a) 5.5 × 105 Hz, β = 2.025 × 10−3; (b) 330.6 V/V; (c) 166.3 V/V, 1⁄ 2; (d) 1.33 10.87 ω0 = 1/CR; Q = 1/(2.1 − K); 0.1; 0.686; K = 2.1 10.89 1 MHz; 90° 10.91 56.87°; 54.07°; 59.24°; 52.93° 10.93 159.2 μs; 39.3°; 20 dB 10.95 3 KHz 10.96 15 KHz; 200 10.97 1/10CR; 1/CR; 1/(100 x Cf x R); 9.1/CR 10.98 100 Hz; 1.59 nF 10.99 58.8 pF; 37.95 MHz CHAPTER 11 11.1 Upper limit (same in all cases): 4.7 V, 5.4 V; lower limits: −4.3 V, −3.6 V; −2.15 V, −1.45 V 11.4 152 Ω; 0.998 V/V; 0.996 V/V; 0.978 V/V; 2% 11.6 VCCI 11.8 5 V 11.10 4.5 V; 6.4%; 625 Ω 11.12 5.0 V peak; 3.18 V peak; 3.425 Ω; 4.83 Ω; 3.65 W; 0.647 W 11.19 12.5 11.21 20.7 mA; 788 mW; 7.9°C; 37.6 mA 11.22 1.34 kΩ; 1.04 kΩ 11.30 50 W; 2.5 A 11.32 140°C; 0.57 V 11.34 100 W; 0.4°C/W 11.45 13 Ω; 433 mV; 0.33 μA 11.47 R1 = 60 kΩ; R2 = 5 kΩ; 0.01 μA 11.49 IE1 = IE2 17 μA; IE3 = IE4 358 μA; IE5 IE6 = 341 μA; 10.5 V 11.50 14 V; 1.9 W; 11 V 11.51 R3 = R4 = 40 Ω; R1 = R2 = 2.2 kΩ 11.53 40 kΩ; 50 kΩ 11.55 L = μn(vGS − Vt) ⁄ Usat; 3 μm; 3 A; 1 A/V CHAPTER 12 12.24 36.3 μA 12.25 0.625 V; for A, 7.3 mA/V, 134.3 Ω, 6.85 kΩ, 274 kΩ; for B, 21.9 mA/V, 44.7 Ω, 2.28 kΩ, 91.3 kΩ 12.29 593 mV; 518 mV; 7.5 kΩ 12.31 4.75 μA; 1.94 kΩ 12.33 56.5 kΩ; 9.353 μA 12.36 5.6 mV 12.38 6.37 kΩ; 270 μA 12.40 1.68 mA; 50.4 mW 12.42 Raise R′1, R′2 to 4.63 kΩ 12.45 1.4 mV 12.50 3.1 MΩ; 9.38 mA/V 12.52 4.2 V to −3.6 V 12.54 105.6 dB; |Vo| < 4 V; 21.0 mA 12.56 108 dB; 61.9 Ω 12.58 7.6 MHz 12.60 318 kΩ 12.62 159.2 kHz; 15.9 MHz CHAPTER 13 13.6 1.5 V; 1.5 V; 1.5 V; 0 V; 3 V; 1.5 V; 1.5 V; ∞ 13.8 0.349 to 0.451 V; 0.749 to 0.852 V; 0 V; 1.2 V; 0.349 to 0.452 V; 0.348 to 0.451 V 13.19 4.36 mW; 1.48 mW 13.21 (a) tPLH = 1.6 ns, tPHL = 0.8 ns; (b) C = 1.43 pF; (c) Co = 0.86 pF, Ci = 0.57 pF 13.25 (a) 0.66, 0.435 (b) 0.436, 0.435 13.29 9.09 mV; 50 mV 13.46 24 13.53 pA = p : pB = pC = pD = 2p; and nA = nB = 2n : nC = nD = 2(2n) = 4n 13.55 tPHL is 4 times larger; tPLH is the same Answers to Selected Problems I-5 CHAPTER 14 14.1 (a) 0.693 RDC; (b) 0.5RDC, for a 21.5% reduction 14.2 1.52; 0.97 V; 1.69 V; 1.2 V; 2.5 V; 0.28 V; 0.81 V; 0.69 V 14.4 r 2.1; NMLmax 0.731 V 14.6 1.33 14.23 9.38 ns 14.30 3 ms; 333 Hz 14.33 2.27 GHz 14.35 33.3 MHz; high 13 ns; low 17 ns 14.38 0.33 V/V; 8.95 V/V; 0.37 V/V 14.39 (a) −1.375 V, −1.265 V; (b) −1.493 V, −1.147 V 14.41 21.2 14.43 7 cm 14.45 (W ⁄ L) = 5 μm ⁄ 1 μm; 6.5 μA 14.46 2.32 V; 3.88 mA 14.47 For R1: 50%; 36.5 kΩ; 20%; 91.1 kΩ; for R2: 50%; 6.70 kΩ; 20%; 16.7 kΩ; 50%; R1 ⁄ R2 = 5.45; 20%; R1 ⁄ R2 = 5.45 14.48 83.2 ps; 50.7 ps; 67.0 ps 14.50 (W/L)NA = (W/L)NB = 2(W/L)N; (W/L)PA = (W/L)PB = (W/L)P CHAPTER 15 15.10 2.236 V; 100 V/V 15.12 1024; 1024; 400 pF; 225 pF; 220 fF/bit; 2.8 times 15.13 60% 15.29 41 mV 15.31 0.4 pA 15.32 1.589 mA/V; 11.36 μm; 34.1 μm; 1.56 ns 15.33 680 μA/V; 0.482 V; 0.206 V; 50%; 7.5 ns 15.38 9; 512; 18; 4608 NMOS and 512 PMOS transistors 15.39 9; 1024; 4608; 512; 5641; 521 15.44 0100, 0000, 1000, 1001, 0101, 0001, 0110, and 0010 15.46 2.42 ns; 23 ns, 3.16 V; 1.90 ns CHAPTER 16 16.1 1 V/V, 0°, 0 dB, 0 dB; 0.894 V/V, −26.6°, −0.97 dB, 0.97 dB; 0.707 V/V, −45.0°, −3.01 dB, 3.01 dB; 0.447 V/V, −63.4°, −6.99 dB, 6.99 dB; 0.196 V/V, −78.7°, −14.1 dB, 14.1 dB; 0.100 V/V, −84.3°, −20.0 dB, 20.0 dB; 0.010 V/V, −89.4°, −40.0 dB, 40.0 dB 16.5 0.5088 rad/s; 3 rad/s; 5.9 16.9 T(s) = 0.2225 (s2 + 4) ⁄ [(s + 1)(s2 + s + 0.89)] 16.11 T(s) = 0.5 ⁄ s3 + 2s2 + 2s + 1; poles at s = −1, −1/2 ± j ⁄ 2, 3 zeros at s = 16.13 28.6 dB 16.19 R1 = 10 kΩ; R2 = 100 kΩ; C = 159 pF 16.21 40 dΒ 16.23 T(s) = –(S – ω0 ⁄ S + ω0); 2.68 kΩ, 5.77 kΩ, 10 kΩ, 17.3 kΩ, 37.3 kΩ 16.25 T(s) = 106 ⁄ (s2 + 103s + 106); 0.707 rad/s; 1.15 V/V; 1.21 dB 16.33 L = 500 mH; C = 20 nF 16.35 s2 ⁄ (s2 + s ⁄ RC + 1 ⁄ LC) 16.39 L1 ⁄ L2 = 0.2346; |T| = L2 ⁄ (L1 + L2); |T| = 1 16.43 R1 = R2 = R3 = R5 = 3.979 kΩ; R6 = 39.79 kΩ; C61 = 6.4 nF; C62 = 3.6 nF 16.44 C4 = C6 = 1 nF; R1 = R2 = R3 = R5 = R6 = 159.16 kΩ 16.49 C = 10 nF; R = 15.92 kΩ; R1 = Rf = 10 kΩ; R2 = 10 kΩ; R3 = 390 kΩ; 39 V/V 16.51 ±1% 16.55 R3 = 141.4 kΩ; R4 = 70.7 kΩ 16.57 4 ⁄ RC; 2; 8 V/V 16.59 High-pass; 1 V/V; R3 = 141.4 kΩ; R4 = 70.7 kΩ 16.64 0; 2Q2/A CHAPTER 17 17.1 (a) ω = ω0, AK = 1; (b) −2Q ⁄ ω0; (c) Δω0 ⁄ ω0 = −Δφ ⁄ 2Q 17.5 20 dB; ±180° 17.9 1 ⁄ RC;¾;¾ 17.10 1.15 ⁄ RC 17.15 20.3 V 17.17 1; 29R; 0.065/RC 17.23 2.01612 MHz to 2.0172 MHz 17.25 (a) VTL = VR (1 − R1 ⁄ R2) − L+R1 ⁄ R2, VTH = VR(1 + R2 ⁄R1) − L−R1 ⁄ R2 L−; (b) R2 = 200 kΩ, VR = 47.62 mV 17.28 (a) +12 V or −12 V 17.29 VZ = 6.8 V; R1 = R2 = 37.5 kΩ; R = 4.1 kΩ 17.33 VZ = 6.8 V; R1 = R2 = R3 = R4 = R5 = R6 = 200 kΩ; R7 = 5.1 kΩ; triangle with period of 100 μs and ±7.5 V peaks 17.35 96 μs 17.38 (a) 9.1 kΩ; (b) 13.3 V 17.39 RA = 21.2 kΩ; RB = 10.7 kΩ 17.41 V = 1.0996 V; R = 400 Ω; Table rows, for vO, θ, 0.7 sin θ, error % are: 0.70 V, 90°, 0.700 V, 0%; 0.65 V, 63.6°, 0.627 V, 3.7%; 0.60 V, 52.4°, 0.554 V, 8.2%; 0.55 V, 46.1°, 0.504 V, 9.1%; 0.50 V, 41.3°, 0.462 V, 8.3%; 0.40 V, 32.8°, 0.379 V, 5.6%; 0.30 V, 24.6°, 0.291 V, 3.1%; 0.20 V, 16.4°, 0.197 V, 1.5%; 0.10 V, 8.2°, 0.100 V, 0%; 0.00 V, 0°, 0.0 V, 0%.
17.42 2.5 V 17.55 10 mV, 20 mV, 100 mV; 50 pulses, 100 pulses, 200 pulses 3 JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 1 5.11 THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET) The junction field-effect transistor, or JFET, is perhaps the simplest transistor available. It has some important characteristics, notably a very high input resistance. Unfortunately, however (for the JFET), the MOSFET has an even higher input resistance. This, together with the many other advantages of MOS transistors, has made the JFET virtually obsolete.
Currently, its applications are limited to discrete-circuit design, where it is used both as an amplifier and as a switch. Its integrated-circuit applications are limited to the design of the differential input stage of some operational amplifiers, where advantage is taken of its high input resistance (compared to the BJT). In this section, we briefly consider JFET operation and characteristics. Another important reason for including the JFET in the study of elec-tronics is that it helps in understanding the operation of gallium arsenide devices, the subject of the next section.
Device Structure As with other FET types, the JFET is available in two polarities: n-channel and p-channel.
Fig. 5.69(a) shows a simplified structure of the n-channel JFET. It consists of a slab of n-type silicon with p-type regions diffused on its two sides. The n region is the chan-nel, and the p-type regions are electrically connected together and form the gate. The device operation is based on reverse-biasing the pn junction between gate and channel.
Indeed, it is the reverse bias on this junction that is used to control the channel width and hence the current flow from drain to source. The major role that this pn junction plays in the operation of this FET has given rise to its name: Junction Field-Effect Tran-sistor (JFET).
FIGURE 5.69 (a) Basic structure of n-channel JFET. This is a simplified structure utilized to explain device operation. (b) Circuit symbol for the n-channel JFET. (c) Circuit symbol for the p-channel JFET.
Channel n (a) (b) (c) 2 MICROELECTRONIC CIRCUITS SEDRA/SMITH It should be obvious that a p-channel device can be fabricated by simply reversing all the semiconductor types, thus using p-type silicon for the channel and n-type silicon for the gate regions.
Figures 5.69(b) and (c) show the circuit symbols for JFETs of both polarities. Observe that the device polarity (n-channel or p-channel) is indicated by the direction of the arrow-head on the gate line. This arrowhead points in the forward direction of the gate–channel pn junction. Although the JFET is a symmetrical device whose source and drain can be interchanged, it is useful in circuit design to designate one of these two terminals as source and the other as drain. The circuit symbol achieves this designation by placing the gate closer to the source than to the drain.
Physical Operation Consider an n-channel JFET and refer to Fig. 5.70(a). (Note that to simplify matters, we will not show the electrical connection between the gate terminals; it is assumed, how-ever, that the two terminals labeled G are joined together.) With vGS = 0, the application of a voltage vDS causes current to flow from the drain to the source. When a negative vGS is applied, the depletion region of the gate–channel junction widens and the channel be-comes correspondingly narrower; thus the channel resistance increases and the current iD (for a given vDS) decreases. Because vDS is small, the channel is almost of uniform width. The JFET is simply operating as a resistance whose value is controlled by vGS. If we keep increasing vGS in the negative direction, a value is reached at which the depletion region occupies the entire channel. At this value of vGS the channel is completely depleted of charge carriers (electrons); the channel has in effect disappeared. This value of vGS is therefore the threshold voltage of the device, Vt, which is obviously negative for an n-channel JFET. For JFETs the threshold voltage is called the pinch-off voltage and is denoted VP.
Consider next the situation depicted in Fig. 5.70(b). Here vGS is held constant at a value greater (that is, less negative) than VP, and vDS is increased. Since vDS appears as a voltage drop across the length of the channel, the voltage increases as we move along the channel from source to drain. It follows that the reverse-bias voltage between gate and channel varies at different points along the channel and is highest at the drain end. Thus the channel acquires a tapered shape and the iD−vDS characteristic becomes nonlinear. When the reverse bias at the drain end, vGD, falls below the pinch-off voltage VP, the channel is pinched off at the drain end and the drain current saturates. The remainder of the description of JFET oper-ation follows closely that given for the depletion MOSFET.
The description above clearly indicates that the JFET is a depletion-type device. Its char-acteristics should therefore be similar to those of the depletion-type MOSFET. This is true with a very important exception: While it is possible to operate the depletion-type MOSFET in the enhancement mode (by simply applying a positive vGS if the device is n channel) this is impossible in the JFET case. If we attempt to apply a positive vGS, the gate–channel pn junction becomes forward biased and the gate ceases to control the channel. Thus the maximum vGS is limited to 0 V, though it is possible to go as high as 0.3 V or so since a pn junction remains essentially cut off at such a small forward voltage.
Current–Voltage Characteristics The current–voltage characteristics of the JFET are identical to those of the depletion-mode MOSFET studied in Section 5.3 except that for the JFET the maximum vGS allowed is JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 3 normally 0 V. Furthermore, the JFET is specified in terms of the pinch-off voltage VP (equal to Vt of the MOSFET) and the drain-to-source current with the gate shorted to the source, IDSS, which corresponds to for the MOSFET. With these substitutions, the n-channel JFET characteristics can be described as follows: Cutoff: FIGURE 5.70 Physical operation of the n-channel JFET: (a) For small vDS the channel is uniform and the device functions as a resistance whose value is controlled by vGS. (b) Increasing vDS causes the channel to acquire a tapered shape and eventually pinch-off occurs. Note that, though not shown, the two gate regions are electrically connected.
(a) (b) 1 2 ---kn ′Vt 2 vGS VP, ≤ iD 0 = 4 MICROELECTRONIC CIRCUITS SEDRA/SMITH Triode region: (5.116) Saturation (pinch-off) region: (5.117) where λ is the inverse of the Early voltage; λ = 1/VA, and VA and λ are positive for n-channel devices.
Recalling that for an n-channel device, VP is negative, we see that operation in the pinch-off region is obtained when the drain voltage is greater than the gate voltage by at least |VP|.
Since the gate–channel junction is always reverse-biased, only a leakage current flows through the gate terminal. From Chapter 3, we know that such a current is of the order of 10−9 A. Although iG is very small, and is assumed zero in almost all applications, it should be noted that the gate current in a JFET is many orders of magnitude greater than the gate current in a MOSFET. Of course the latter is so tiny because of the insulated gate structure.
Another complication arises in the JFET because of the strong dependence of gate leakage current on temperature—approximately doubling for every 10°C rise in temperature, just as in the case of a reverse-biased diode (see Chapter 3).
The p-Channel JFET The current–voltage characteristics of the p-channel JFET are described by the same equa-tions as the n-channel JFET. Note, however, that for the p-channel JFET, VP is positive, , vDS is negative, λ and VA are negative, and the current iD flows out of the drain terminal. To operate the p-channel JFET in pinch-off, , which in words means that the drain voltage must be lower than the gate voltage by at least |VP|. Otherwise, with , the p-channel JFET operates in the triode region.
The JFET Small-Signal Model The JFET small-signal model is identical to that of the MOSFET [see Fig. 5.34(b)]. Here, gm is given by (5.118a) or alternatively by (5.118b) where VGS and ID are the dc bias quantities, and (5.119) At high frequencies, the equivalent circuit of Fig. 5.67(c) applies with Cgs and Cgd being both depletion capacitances. Typically, Cgs = 1 to 3 pF, Cgd = 0.1 to 0.5 pF, and fT = 20 to 100 MHz.
VP vGS 0 vDS vGS VP – ≤ , ≤ ≤ iD IDSS 2 1 vGS VP --------– vDS VP – --------- vDS VP -------- 2 – = VP vGS 0 vDS vGS VP – ≥ , ≤ ≤ iD IDSS 1 vGS VP --------– 2 1 λvDS + ( ) = 0 vGS VP ≤ ≤ vDS vGS VP – ≤ vDS vGS VP – ≥ gm 2IDSS V P ------------- 1 VGS V P ---------– = gm 2IDSS V P ------------- ID IDSS ---------= ro V A ID ---------= JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 5 EXERCISES In Exercises 5.43 to 5.46, let the n-channel JFET have VP = –4 V and IDSS = 10 mA, and unless otherwise specified assume that in pinch-off (saturation) the output resistance is infinite.
5.43 For vGS = −2 V, find the minimum vDS for the device to operate in pinch-off. Calculate iD for vGS = −2 V and vDS = 3 V.
Ans. 2 V; 2.5 mA 5.44 For vDS = 3 V, find the change in iD corresponding to a change in vGS from −2 to −1.6 V.
Ans. 1.1 mA 5.45 For small vDS, calculate the value of rDS at vGS = 0 V and at vGS = −3 V.
Ans. 200 Ω; 800 Ω 5.46 If VA = 100 V, find the JFET output resistance ro when operating in pinch-off at a current of 1 mA, 2.5 mA, and 10 mA.
Ans. 100 kΩ; 40 kΩ; 10 kΩ D5.47 The JFET in the circuit of Fig. E5.47 has VP = −3 V, IDSS = 9 mA, and λ = 0. Find the values of all resis-tors so that VG = 5 V, ID = 4 mA, and VD = 11 V. Design for 0.05 mA in the voltage divider.
Ans. RG1 = 200 kΩ; RG2 = 100 kΩ; RS = 1.5 kΩ; RD = 1 kΩ 5.48 For the JFET circuit designed in Exercise 5.47, let an input signal vi be capacitively coupled to the gate, a large bypass capacitor be connected between the source and ground, and the output signal vo be taken from the drain through a large coupling capacitor. The resulting common-source amplifier is shown in Fig. E5.48. Calculate gm and ro (assuming VA = 100 V). Also find Ri, , and Ro.
Ans. 4 mA/V; 25 kΩ; 66.7 kΩ; −3.8 V/V; 962 Ω FIGURE E5.47 Av vo vi ⁄ ( ) ≡ vo vi i RG2 RG1 RD VDD RS R o R FIGURE E5.48 6 MICROELECTRONIC CIRCUITS SEDRA/SMITH 5.12 GALLIUM ARSENIDE (GaAs) DEVICES—THE MESFET10 The devices discussed thus far, and indeed the devices used in most of the circuits studied in this book, are made of silicon. This reflects the situation that has existed in the micro-electronics industry for at least three decades. Furthermore, owing to the advances that are continually being made in silicon device and circuit technologies, the dominance of silicon as the most useful semiconductor material is expected to continue for many years to come.
Nevertheless, another semiconductor material has been making inroads into digital applica-tions that require extremely high speeds of operation and analog applications that require very high operating frequencies. We refer to gallium arsenide (GaAs), a compound semi-conductor formed of gallium, which is in the third column of the periodic table of elements, and arsenic, which is in the fifth column; thus GaAs is known as a III-V semiconductor.
The major advantage that GaAs offers over silicon is that electrons travel much faster in n-type GaAs than in silicon. This is a result of the fact that the electron drift mobility µn (which is the constant that relates the electron drift velocity to the electric field; velocity = µnE) is five to ten times higher in GaAs than in silicon. Thus for the same input voltages, GaAs devices have higher output currents, and thus higher gm, than the corresponding silicon devices. The larger output currents enable faster charging and discharging of load and parasitic capaci-tances and thus result in increased speeds of operation.
Gallium arsenide devices have been used for some years in the design of discrete-component amplifiers for microwave applications (in the 109 Hz or GHz frequency range).
More recently, GaAs has begun to be employed in the design of very-high-speed digital integrated circuits and in analog ICs, such as op amps, that operate in the hundreds of MHz frequency range. Although the technology is still relatively immature, suffering from yield and reliability problems and generally limited to low levels of integration, it offers great potential. Therefore, this book includes a brief study of GaAs devices and circuits. Specifi-cally, the basic GaAs devices are studied in this section; their basic amplifier circuit config-urations are discussed in Section 6.8; and GaAs digital circuits are studied in Section 14.8.
The Basic GaAs Devices Although there are a number of GaAs technologies currently in various stages of develop-ment, we shall study the most mature of these technologies. The active device available in this technology is an n-channel field effect transistor known as the metal semiconductor FET or MESFET. The technology also provides a type of diode known as the Schottky-barrier diode (SBD). (Recall that the SBD was briefly introduced in Section 3.9.) The structure of these two basic devices is illustrated by their cross sections, depicted in Fig. 5.71.
The GaAs circuit is formed on an undoped GaAs substrate. Since the conductivity of undoped GaAs is very low, the substrate is said to be semi-insulating. This turns out to be an advantage for GaAs technology as it simplifies the process of isolating the devices on the chip from one another, as well as resulting in smaller parasitic capacitances between the devices and the circuit ground.
As indicated in Fig. 5.71, a Schottky-barrier diode consists of a metal–semiconductor junction. The metal, referred to as the Schottky-barrier metal to distinguish it from the dif-ferent kind of metal used to make a contact (see Long and Butner (1990) for a detailed explanation of the difference), forms the anode of the diode. The n-type GaAs forms the 10 The material in this section is required only for the study of the GaAs circuits in Sections 6.8 and 14.8.
Otherwise, this section can be skipped without loss of continuity. JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 7 cathode. Note that heavily doped n-type GaAs (indicated by n+) is used between the n region and the cathode metal contact in order to keep the parasitic series resistance low.
The gate of the MESFET is formed by Schottky-barrier metal in direct contact with the n-type GaAs that forms the channel region. The channel length L is defined by the length of the gate electrode, and similarly for the width W (in the direction perpendicular to the page).
To reduce the parasitic resistances between the drain and source contacts and the channel, the two contacts are surrounded with heavily doped (n+) GaAs.
Since the main reason for using GaAs circuits is to achieve high speed/frequency of operation, the channel length is made as small as possible. Typically L = 0.2−2 µm. Also, usually all the transistors on the IC chip are made to have the same length, leaving only the width W of each device to be specified by the circuit designer.
Only n-channel MESFETs are available in GaAs technology. This is because holes have a relatively low drift mobility in GaAs, making p-channel MESFETs unattractive. The lack of complementary transistors is a definite disadvantage of GaAs technology. Correspondingly, it makes the task of the circuit designer even more challenging than usual.
Device Operation The MESFET operates in a very similar manner to the JFET, with the Schottky metal play-ing the role of the p-type gate of the JFET (refer to Fig. 5.69). Basically, a depletion region forms in the channel below the gate surface, and the thickness of the depletion region is con-trolled by the gate voltage vGS. This in turn effects control over the channel dimensions and thus on the current that flows from drain to source in response to an applied vDS. The latter voltage causes the channel to have a tapered shape, with pinch-off eventually occurring at the drain end of the channel.
The most common GaAs MESFETs available are of the depletion type with a threshold voltage Vt (or, equivalently, pinch-off voltage VP) in the range of −0.5 to −2.5 V. These devices can be operated with vGS values ranging from the negative Vt to positive values as high as a few tenths of a volt. However, as vGS reaches 0.7 V or so, the Schottky-barrier diode between gate and channel conducts heavily and the gate voltage no longer effectively FIGURE 5.71 Cross-section of a GaAs Schottky-barrier diode (SBD) and a MESFET. n n n n n Isolation regions Channel Anode Cathode Contact metal Gate (G) Drain (D) Source (S) SBD MESFET Schottky-barrier metal L Semi-insulating GaAs substrate 8 MICROELECTRONIC CIRCUITS SEDRA/SMITH controls the drain-to-source current. Gate conduction, which is not possible in MOSFETs, is another definite disadvantage of the MESFET.
Although less common, enhancement-mode MESFETs are available in certain technolo-gies. These normally-off devices are obtained by arranging that the depletion region existing at vGS = 0 extends through the entire channel depth, thus blocking the channel and causing iD = 0. To cause current to flow from drain to source the channel must be opened by apply-ing to the gate a positive voltage of sufficient magnitude to reduce the thickness of the depletion region below that of the channel region. Typically, the threshold voltage Vt is between 0.1 and 0.3 V.
The above description of MESFET operation suggests that the iD−vDS characteristics should saturate at vDS = vGS − Vt, as is the case in a silicon JFET. It has been observed, how-ever, that the iD−vDS characteristics of GaAs MESFETs saturate at lower values of vDS and, furthermore, that the saturation voltages vDSsat do not depend strongly on the value of vGS.
This “early saturation” phenomenon comes about because the velocity of the electrons in the channel does not remain proportional to the electric field (which in turn is determined by vDS and L; E = vDS/L) as is the case in silicon; rather, the electron velocity reaches a high peak value and then saturates (that is, becomes constant independent of vDS). The velocity-saturation effect is even more pronounced in short-channel devices (L ≤ 1 µm), occurring at values of vDS lower than (vGS − Vt).
Finally, a few words about the operation of the Schottky-barrier diode. Forward current is conducted by the majority carriers (electrons) flowing into the Schottky-barrier metal (the anode). Unlike the pn-junction diode, minority carriers play no role in the operation of the SBD. As a result, the SBD does not exhibit minority-carrier storage effects, which give rise to the diffusion capacitance of the pn-junction diode. Thus, the SBD has only one capacitive effect, that associated with the depletion-layer capacitance Cj.
Device Characteristics and Models A first-order model for the MESFET, suitable for hand calculations, is obtained by neglect-ing the velocity-saturation effect, and thus the resulting model is almost identical to that of the JFET though expressed somewhat differently in order to correspond to the literature: (5.120) The only differences between these equations and those for the JFETs are (1) the channel-length modulation factor, 1 + λvDS, is included also in the equation describing the triode region (also called the ohmic region) simply because λ of the MESFET is rather large and including this factor results in a better fit to measured characteristics; and (2) a transconduc-tance parameter β is used so as to correspond with the MESFET literature. Obviously, β is related to IDSS of the JFET and k′(W/L) of the MOSFET. (Note, however, that this β has absolutely nothing to do with β of the BJT!) A modification of this model to account for the early saturation effects is given in Hodges and Jackson (1988).
Figure 5.72(a) shows the circuit symbol for the depletion-type n-channel GaAs MESFET.
Since only one type of transistor (n channel) is available, all devices will be drawn the iD = 0 for vGS V t < iD β 2 vGS V t – ( )vDS v 2 DS – [ ] 1 λvDS + ( ) for vGS V t vDS v < , GS ≥ V t – = iD β vGS V t – ( ) 2 1 λvDS + ( ) for vGS V t vDS v ≥ , GS ≥ V t – = JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 9 same way, and there should be no confusion as to which terminal is the drain and which is the source.
The circuit symbol of the Schottky-barrier diode is depicted in Fig. 5.72(b). In spite of the fact that the physical operation of the SBD differs from that of the pn-junction diode, their i−v characteristics are identical. Thus the i−v characteristic of the SBD is given by the same exponential relationship studied in Chapter 3. For the GaAs SBD, the constant n is typically in the range of 1 to 1.2.
The small-signal model of the MESFET is identical to that of other FET types. The parameter values are given by (5.121) (5.122) The MESFET, however, has a rather high value for λ (0.1 to 0.3 V−1) which results in a small output resistance ro. This turns out to be a serious drawback of GaAs MESFET tech-nology, resulting in low voltage-gain obtainable from each stage. Furthermore, it has been found that ro decreases at high frequencies. Circuit design techniques for coping with the low ro will be presented in Section 6.8.
For easy reference, Table 5.2 gives typical values for device parameters in a GaAs MESFET technology. The devices in this technology have a channel length L = 1 µm. The values given are for a device with a width W = 1 µm. The parameter values for actual devices can be obtained by appropriately scaling by the width W. This process is illustrated in the fol-lowing example. Unless otherwise specified, the values of Table 5.2 are to be used for the exercises and the end-of-chapter problems.
TABLE 5.2 Typical Parameter Values for GaAs MESFETS and Schottky Diodes in L = 1 µm Technology, Normalized for W = 1 µm (b) (a) FIGURE 5.72 Circuit symbols for (a) an n-channel depletion-type GaAs MESFET, and (b) a Schottky-barrier diode (SBD). gm 2β VGS V t – ( )(1 λV DS) + = ro iD ∂ vDS ∂ -----------1 – ≡ 1/λβ VGS Vt – ( ) 2 = V t 1.0 V – = β 10 4 – A/V 2 = λ 0.1 V 1 – = IS 10 15 – A = n 1.1 = 10 MICROELECTRONIC CIRCUITS SEDRA/SMITH EXAMPLE 5.11 Figure 5.73 shows a simple GaAs MESFET amplifier, with the W values of the transistors indi-cated. Assume that the dc component of vI, that is VGS1, biases Q1 at the current provided by the current source Q2 so that both devices operate in saturation and that the dc output is at half of the supply voltage. Find: (a) the β values for Q1 and Q2; (b) VGS1; (c) gm1, ro1, and ro2; and (d) the small-signal voltage gain.
Solution (a) The values of β can be obtained by scaling the value given in Table 5.2 using the specified values of W, (b) Thus, FIGURE 5.73 Circuit for Example 5.11: a simple MESFET amplifier.
β1 100 10 4 – × 10 2 – A/V2 10 mA/V2 = = = β2 50 10 4 – × 5 10 × 3 – A/V2 5 mA/V2 = = = ID2 β2 (VGS2 V t) – 2(1 λVDS2) + = 5 0 1 + ( )2 1 0.1 5 × + ( ) = 7.5 mA = ID1 ID2 7.5 mA = = 7.5 β1 VGS1 Vt – ( )2 (1 λVDS1) + = 10 VGS1 1 + ( )2 1 0.1 5 × + ( ) = V GS1 0.3 V – = JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 11 (c) (d) As already mentioned, the main reason for using GaAs devices and circuits is their high frequency and high speed of operation. A remark is therefore in order on the internal capac-itances and fT of GaAs transistors. For a particular GaAs technology with L = 1 µm, Cgs (at VGS = 0 V) is 1.6 fF/µm-width, and Cgd (at VDS = 2 V) is 0.16 fF/µm-width. Thus for a MESFET with W = 100 µm, Cgs = 0.16 pF and Cgd = 0.016 pF. fT typically ranges from 5 to 15 GHz.
6.8 GaAs AMPLIFIERS3 Gallium arsenide (GaAs) technology makes possible the design of amplifiers having very wide bandwidths, in the hundreds of megahertz or even gigahertz range. In this section we shall study some of the circuit design techniques that have been developed over the last few years for the design of GaAs amplifiers. As will be seen, these techniques aim to circumvent the major problem of the MESFET, namely, its low output resistance in saturation. Before proceeding with this section the reader is advised to review the material on GaAs devices presented in Section 5.12.
Current Sources Current sources play a fundamental role in the design of integrated-circuit amplifiers, being employed both for biasing and as active loads. In GaAs technology, the simplest way to implement a current source is to connect the gate of a depletion-type MESFET to its source, gm1 2 10 0.3 – 1 + ( ) × 1 0.1 5 × + ( ) = 21 mA/V = ro1 1 0.1 10 0.3 – 1 + ( )2 × ------------------------------------------------2 kΩ = = ro2 1 0.1 5 0 1 + ( )2 × ------------------------------------2 kΩ = = Av gm1 ro1 // ro2 ( ) – = 21 2 // 2 ( ) × – = 21 V/V – = EXERCISE 5.49 For a MESFET with the gate shorted to the source and having W = 10 µm, find the minimum voltage between drain and source to operate in saturation. For VDS = 5 V, find the current ID. What is the output resistance of this current source?
Ans. 1 V; 1.5 mA; 10 kΩ 3 This section can be omitted with no loss in continuity.
12 MICROELECTRONIC CIRCUITS SEDRA/SMITH as shown in Fig. 6.39(a). Provided that vDS is maintained greater than |Vt|, the MESFET will operate in saturation and the current iD will be (6.126) Thus the current source will have the equivalent circuit shown in Fig. 6.39(b), where the output resistance is the MESFET ro, (6.127) In JFET terminology, and ; thus (6.128) Since for the MESFET, λ is relatively high (0.1 to 0.3 V−1) the output resistance of the cur-rent source of Fig. 6.39(a) is usually low, rendering this current-source realization inade-quate for most applications. Before considering means for increasing the effective output resistance of the current source, we show in Fig. 6.39(c) how the basic current source can be connected to source currents to a load whose voltage can be as high as VDD − |Vt|. Alterna-tively, the same device can be connected as shown in Fig. 6.39(d) to sink currents from a load whose voltage can be as low as −VSS + |Vt|. A Cascode Current Source The output resistance of the current source can be increased by utilizing the cascode config-uration as shown in Fig. 6.40. The output resistance Ro of the cascode current source can be FIGURE 6.39 (a) The basic MESFET current source; (b) equivalent circuit of the current source; (c) the cur-rent source connected to a positive power supply to source currents to loads at voltages ≤VDD − |Vt|; (d) the current source connected to a negative power supply to sink currents from loads at voltages ≥−VSS + |Vt|.
ro Vt 2 vD (a) (b) (c) (d) S iD V DD I VSS I iD = βV t 2 1 λvDS + ( ) ro = 1/λβV t 2 βV t 2 = IDSS λ = 1/ VA ro VA IDSS ⁄ = EXERCISE 6.23 Using the device data given in Table 5.2 (page 456), find the current provided by a 10-µm-wide MESFET connected in the current-source configuration. Let the source be connected to a −5-V supply and find the current when the drain voltage is −4V. What is the output resistance of the current source? What change in current occurs if the drain voltage is raised by +4V?
Ans. 1.1 mA; 10 kΩ; 0.4 mA JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 13 found by using Eq. (6.116), (6.129) Thus, adding the cascode transistor Q2 raises the output resistance of the current source by the factor gm2ro2, which is the intrinsic voltage gain of Q2. For GaAs MESFETs, gm2ro2 is typically 10 to 40. To allow a wide range of voltages at the output of the cascode current source, VBIAS should be the lowest value that results in Q1 operating in saturation. Increasing the Output Resistance by Bootstrapping Another technique frequently employed to increase the effective output resistance of a MESFET, including the current-source-connected MESFET, is known as bootstrapping.
The bootstrapping idea is illustrated in Fig. 6.41(a). Here the circuit inside the box senses the voltage at the bottom node of the current source, vA, and causes a voltage vB to appear at the top node of a value (6.130) where VS is the dc voltage required to operate the current-source transistor in saturation and α is a constant ≤1. The incremental output resistance of the bootstrapped current source can be found by causing the voltage vA to increase by an increment va. From Eq. (6.130) we find that the resulting increment in vB is vb = αva. The incremental current through the current source is therefore (va − vb) ⁄ro or (1 − α)va ⁄ro. Thus the output resistance Ro is (6.131) I Ro VBIAS Q1 Q2 VSS FIGURE 6.40 Adding the cascode transistor Q2 increases the output resistance of the current source by the factor gm2ro2; that is, Ro = gm2ro2ro1.
Ro gm2r o2ro1 EXERCISE D6.24 For the cascode current source of Fig. 6.40 let VSS = 5 V, W1 = 10 µm, and W2 = 20 µm, and assume that the devices have the typical parameter values given in Table 5.2. (a) Find the value of VBIAS that will result in Q1 operating at the edge of the saturation region (i.e., VDS1 = |Vt|) when the voltage at the output is −3 V. (b) What is the lowest allowable voltage at the current-source output? (c) What value of output current is obtained for VO = −3 V? (d) What is the output resistance of the current source? (e) What change in output current results when the output voltage is raised from −3 V to +1 V?
Ans. (a) −4.3 V; (b) −3.3 V; (c) 1.1 mA; (d) 310 kΩ; (e) 0.013 mA vB = VS αvA + VS V t ≥ ( ) Ro = va 1 α – ( )va ro ⁄ ------------------------------- = ro 1 α – ------------14 MICROELECTRONIC CIRCUITS SEDRA/SMITH Thus, bootstrapping increases the output resistance by the factor 1/(1 − α), which increases as α approaches unity. Perfect bootstrapping is achieved with α = 1, resulting in Ro = ∞.
From the above we observe that the bootstrapping circuit senses whatever change occurs in the voltage at one terminal of the current source and causes an almost equal change to occur at the other terminal, thus maintaining an almost constant voltage across the current source and minimizing the change in current through the current-source transistor. The FIGURE 6.41 Bootstrapping of a MESFET current source Q1: (a) basic arrangement; (b) an implementa-tion; (c) small-signal equivalent circuit model of the circuit in (b), for the purpose of determining the output resistance Ro.
Bootstrapping circuit B A Q2 (W/2) I Ro Q1 I Q1 (W) I/2 E D1 D2 A B Q3 (W) VDD C Bootstrapping circuit ro2 A B C ro3 Q3 1/gm3 ro1 Q2 1/gm2 Ro va/ia ia va I (a) (b) (c) JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 15 action of the bootstrapping circuit can be likened to that of a person who attempts to lift himself off the ground by pulling on the straps of his boots (!), the origin of the name of this circuit technique, which, incidentally, predates GaAs technology. Bootstrapping is a form of positive feedback; the signal vb that is fed back by the bootstrapping circuit is in phase with (has the same polarity as) the signal that is being sensed, va. Feedback will be studied formally in Chapter 8.
An implementation of the bootstrapped current source is shown in Fig. 6.41(b). Here transistor Q2 is a source follower used to buffer node A, whose voltage is being sensed. The width of Q2 is half that of Q1 and is operating at half the bias current. (Transistors Q1 and Q2 are said to operate at the same current density.) Thus VGS of Q2 will be equal to that of Q1—namely, zero—and hence VC = VA. The two Schottky diodes behave as a battery of approximately 1.4 V, resulting in the dc voltage at node E being 1.4 V higher than VC. Note that the signal voltage at node C appears intact at node E; only the dc level is shifted. The diodes are said to perform level shifting, a common application of Schottky diodes in GaAs MESFET technology.
Transistor Q3 is a source follower that is operating at the same current density as Q1, and thus its VGS must be zero, resulting in VB = VE. The end result is that the bootstrapping circuit causes a dc voltage of 1.4 V to appear across the current-source transistor Q1. Provided that |Vt| of Q1 is less than 1.4 V, Q1 will be operating in saturation as required.
To determine the output resistance of the bootstrapped current source, apply an incre-mental voltage va to node A, as shown in Fig. 6.41(c). Note that this small-signal equivalent circuit is obtained by implicitly using the T model (including ro) for each FET and assuming that the Schottky diodes act as a perfect level shifter (that is, as an ideal dc voltage of 1.4 V with zero internal resistance). Analysis of this circuit is straightforward and yields (6.132) which is smaller than, but close to, unity, as required. The output resistance Ro is then obtained as (6.133) For ro3 = ro1, assuming that gm3ro3 and gm2ro2 are 1, and using the relationships for gm and ro for Q2 and Q3, one can show that (6.134) which represents an increase of about an order of magnitude in output resistance. Unfortu-nately, however, the circuit is rather complex.
A Simple Cascode Configuration–The Composite Transistor The rather low output resistance of the MESFET places a severe limitation on the perfor-mance of MESFET current sources and various MESFET amplifiers. This problem can be alleviated by using the composite MESFET configuration shown in Fig. 6.42(a) in place of a α ≡ vb va -----gm3ro3 gm2r o2 gm2ro2 1 + ------------------------ro3 ro1 ------+ gm3ro3 ro3 ro1 ------ +1 + ------------------------------------------------------= Ro va ia -----≡ ro1 1 α – ------------= ro1 gm3ro3 (ro3 ro1 ⁄ ) 1 + + gm3ro3 gm2 r o2 1 + ( ) ⁄ 1 + ----------------------------------------------------------= Ro ro1 gm3ro3 2 ⁄ ( ) 16 MICROELECTRONIC CIRCUITS SEDRA/SMITH single MESFET. This circuit is unique to GaAs MESFETs and works only because of the early-saturation phenomenon observed in these devices. Recall from the discussion in Sec-tion 5.12 that early saturation refers to the fact that in a GaAs MESFET the drain current saturates at a voltage vDSsat that is lower than vGS − Vt.
In the composite MESFET of Fig. 6.42(a), Q2 is made much wider than Q1. It follows that since the two devices are conducting the same current, Q2 will have a gate-to-source voltage vGS2 whose magnitude is much closer to |Vt| than |vGS1| is (thus, |vGS2| |vGS1|).
For instance, if we use the devices whose typical parameters are given in Table 5.2 and ignore for the moment channel-length modulation (λ = 0), we find that for W1 = 10 µm and W2 = 90 µm, at a current of 1 mA, vGS1 = 0 and V. Now, since the drain-to-source voltage of Q1 is vDS1 = −vGS2 + vGS1, we see that vDS1 will be positive and close to but lower than vGS1 − Vt ( V in our example compared to 1 V). Thus in the absence of early saturation, Q1 would be operating in the triode region. With early saturation, how-ever, it has been found that saturation-mode operation is achieved for Q1 by making Q2 5 to 10 times wider.
The composite MESFET of Fig. 6.42(a) can be thought of as a cascode configuration, in which Q2 is the cascode transistor, but without a separate bias line to feed the gate of the cascode transistor (as in Fig. 6.40). By replacing each of Q1 and Q2 with their small-signal models one can show that the composite device can be represented with the equivalent circuit model of Fig. 6.42(b). Thus while gm of the composite device is equal to that of Q1, the output resistance is increased by the intrinsic gain of Q2, gm2ro2, which is typically in the range 10 to 40. This is a substantial increase and is the reason for the attractiveness of the composite MESFET.
The composite MESFET can be employed in any of the applications that can benefit from its increased output resistance. Some examples are shown in Fig. 6.43. The circuit in Fig. 6.43(a) is that of a current source with increased output resistance. Another view of the operation of this circuit can be obtained by considering Q2 as a source follower that causes the drain of Q1 to follow the voltage changes at the current-source terminal (node A), thereby bootstrapping Q1 and increasing the effective output resistance of the current source.
This alternative interpretation of circuit operation has resulted in its alternative name: the self-bootstrapped current source.
The application of the composite MESFET as a source follower is depicted in Fig. 6.43(b). Assuming the bias-current source I to be ideal, we can write for the gain of FIGURE 6.42 (a) The composite MESFET and (b) its small-signal model.
Composite MESFET D G S Q2 Q1 (a) S D G vgs ro1 vgs gm1 gm2ro2 (b) vGS2 = 2 3 ---– 2 3 --- JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 17 this follower (6.135) which is much closer to the ideal value of unity than is the gain of a single MESFET source follower.
A final example of the application of the composite MESFET is shown in Fig. 6.43(c).
The circuit is a gain stage utilizing a composite MESFET (Q1, Q2) as a driver and another composite MESFET (Q3, Q4) as a current-source load. The small-signal gain is given by (6.136) where Ro is the output resistance, (6.137) FIGURE 6.43 Applications of the composite MESFET: (a) as a current source; (b) as a source follower; and (c) as a gain stage.
Q1 VDD Q2 (b) vi (a) I I Q1 Q2 A VDD vo Q1 VDD Q2 vi vo Q3 Q4 (c) vo vi ----- = ro eff , ro eff , (1 gm1) ⁄ + -------------------------------------- = gm2ro2 ro1 gm2 ro2 ro1 (1 gm1) ⁄ + -------------------------------------------------EXERCISE 6.25 Using the device data given in Table 5.2, contrast the voltage gain of a source follower formed using a single MESFET having W = 10 µm with a composite MESFET follower with W1 = 10 µm and W2 = 90 µm. In both cases assume biasing at 1 mA and neglect λ while calculating gm (for simplicity).
Ans. Single: 0.952 V/V; composite: 0.999 V/V vo vi ----- = gm1Ro – Ro = ro eff , Q1 Q2 , ( )//ro eff , Q3 Q4 , ( ) = gm2ro2ro1// gm4ro4 ro3 18 MICROELECTRONIC CIRCUITS SEDRA/SMITH Differential Amplifiers The simplest possible implementation of a differential amplifier in GaAs MESFET technol-ogy is shown in Fig. 6.44. Here Q1 and Q2 form the differential pair, Q3 forms the bias current source, and Q4 forms the active (current-source) load. The performance of the circuit is impaired by the low output resistances of Q3 and Q4. The voltage gain is given by (6.138) The gain can be increased by using one of the improved current-source implementations discussed above. Also, a rather ingenious technique has been developed for enhancing the gain of the MESFET differential pair. The circuit is shown in Fig. 6.45(a). While the drain FIGURE 6.45 (a) A MESFET differential amplifier whose gain is enhanced by the application of positive feedback through the source follower Q3; (b) small-signal analysis of the circuit in (a).
Q4 Q3 VDD VSS vo vi Q1 Q2 FIGURE 6.44 A simple MESFET differential amplifier.
vo vi -----gm2 ro2 //ro 4 ( ) – = (a) (b) JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 19 of Q2 is loaded with a current-source load (as before), the output signal developed is fed back to the drain of Q1 via the source follower Q3. The small-signal analysis of the circuit is illustrated in Fig. 6.45(b) where the current sources I and I/2 have been assumed ideal and thus replaced with open circuits. To determine the voltage gain, we have grounded the gate terminal of Q2 and applied the differential input signal vi to the gate of Q1. The analysis pro-ceeds along the following steps: 1. From the output node we see that id2 = 0.
2. From the sources node, since id2 = 0, we find that id1 = 0.
3. From the node at the drain of Q1, since id1 = 0, we find that id3 = 0.
4. Writing for each transistor we obtain three equations in the three unknowns vd1, vs, and vo. The solution yields (6.139) If all three transistors have the same geometry and are operating at equal dc currents, their gm and ro values will be equal and the expression in Eq. (6.139) reduces to (6.140) Thus application of positive feedback through follower Q3 enables one to obtain a gain equal to the square of that naturally available from a single stage!
14.8 GALLIUM-ARSENIDE DIGITAL CIRCUITS We conclude our study of digital-circuit families with a discussion of logic circuits imple-mented using the emerging technology of gallium arsenide. An introduction to this technol-ogy and its two basic devices, the MESFET and the Schottky-barrier diode (SBD), was given in Section 5.12. We urge the reader to review Section 5.12 before proceeding with the study of this section.
The major advantage that GaAs technology offers is a higher speed of operation than currently achievable using silicon devices. Gate delays of 10 to 100 ps have been reported for GaAs circuits. The disadvantages are a relatively high power dissipation per gate (1 to 10 mW); relatively small voltage swings and, correspondingly, narrow noise margins; low packing density, mostly as a result of the high-power dissipation per gate; and low manufac-turing yield. The present state of affairs is that a few specialized manufacturers produce SSI, MSI, and some LSI digital circuits performing relatively specialized functions, with a cost per gate considerably higher than that of silicon digital ICs. Nevertheless, the very high id = gmvgs vds ro ⁄ + = 0 vo vi ----- = gm1ro1 gm1ro1 1 + gm2ro2 1 + ------------------------gm3ro3 gm3r o3 1 + ------------------------– vo vi ----- (gmro) 2 EXERCISE 6.26 Using the device data given in Table 5.2, find the gain of the differential amplifier circuit of Fig. 6.45(a) for I = 10 mA and W1 = W2 = W3 = 100 µm.
Ans. 784 V/V 20 MICROELECTRONIC CIRCUITS SEDRA/SMITH speeds of operation achievable in GaAs circuits make it a worthwhile technology whose applications will possibly grow.
Unlike the CMOS logic circuits that we have studied in Chapter 13, and the bipolar logic families that we have studied in earlier sections of this chapter, there are no standard GaAs logic-circuit families. The lack of standards extends not only to the topology of the basic gates but also to the power-supply voltages used. In the following we present examples of the most popular GaAs logic gate circuits.
Direct-Coupled FET Logic (DCFL) Direct-coupled FET logic (DCFL) is the simplest form of GaAs digital logic circuits. The basic gate is shown in Fig. 14.47. The gate utilizes enhancement MESFETs, Q1 and Q2, for the input switching transistors, and a depletion MESFET for the load transistor QL. The gate closely resembles the now obsolete depletion-load MOSFET circuit. The GaAs circuit of Fig. 14.47 implements a two-input NOR function.
To see how the MESFET circuit of Fig. 14.47 operates, ignore input B and consider the basic inverter formed by Q1 and QL. When the input voltage applied to node A, vI, is lower than the threshold voltage of the enhancement MESFET Q1, denoted VtE, transistor Q1 will be off. Recall that VtE is positive and for GaAs MESFETs is typically 0.1 to 0.3 V. Now if the gate output Y is open circuited, the output voltage will be very close to VDD. In practice, however, the gate will be driving another gate, as indicated in Fig. 14.47, where Q3 is the input transistor of the subsequent gate. In such a case, current will flow from VDD through QL and into the gate terminal of Q3. Recalling that the gate to source of a GaAs MESFET is a Schottky-barrier diode that exhibits a voltage drop of about 0.7 V when conducting, we see that the gate conduction of Q3 will clamp the output high voltage (VOH) to about 0.7 V. This is in sharp contrast to the MOSFET case, where no gate conduction takes place.
Figure 14.48 shows the DCFL inverter under study with the input of the subsequent gate represented by a Schottky diode Q3. With vI < VtE, i1 = 0 and iL flows through Q3 resulting in vO = VOH 0.7 V. Since VDD is usually low (1.2 to 1.5 V) and the threshold voltage of QL, VtD, is typically −0.7 to −1 V, QL will be operating in the triode region. (To simplify matters, we shall ignore in this discussion the early-saturation effect exhibited by GaAs MESFETs.) As vI is increased above VtE, Q1 turns on and conducts a current denoted i1. Initially, Q1 will be in the saturation region. Current i1 subtracts from iL, thus reducing the current in Q3. The voltage across Q3, vO, decreases slightly. However, for the present discussion we shall assume that vO will remain close to 0.7 V as long as Q3 is conducting. This will con-tinue until vI reaches the value that results in i1 = iL. At this point, Q3 ceases conduction FIGURE 14.47 A DCFL GaAs gate implementing a two-input NOR function.
The gate is shown driving the input transis-tor Q3 of another gate. JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 21 and can be ignored altogether. Further increase in vI results in i1 increasing, vO decreasing, and iL = i1. When (VDD – vO) exceeds , QL saturates; and when vO falls below vI by VtE, Q1 enters the triode region. Eventually, when vI = VOH = 0.7 V, vO = VOL, which is typi-cally 0.1 to 0.2 V.
From the description above we see that the output voltage swing of the DCFL gate is limited by gate conduction to a value less than 0.7 V (typically 0.5 V or so). Further details on the operation of the DCFL gate are illustrated by the following example.
EXAMPLE 14.3 Consider a DCFL gate fabricated in a GaAs technology for which L = 1 µm, VtD = −1 V, VtE = 0.2 V, β (for 1-µm width) = 10−4 A/V2, and λ = 0.1 V−1. Let the widths of the input MESFETs be 50 µm, and let the width of the load MESFET be 6 µm. VDD = 1.5 V. Using a constant-voltage-drop model for the gate-source Schottky diode with VD = 0.7 V, and neglecting the early-saturation effect of GaAs MESFETs (that is, using Eqs. 5.120 to describe MESFET operation), find VOH, VOL, VIH, NMH, NML, the static power dissipation, and the propagation delay for a total equivalent capacitance at the gate output of 30 fF.
Solution From the description above of the operation of the DCFL gate we found that VOH = 0.7 V. To obtain VOL, we consider the inverter in the circuit of Fig. 14.48 and let vI = VOH = 0.7 V. Since we expect vO = VOL to be small, we assume Q1 to be in the triode region and QL to be in saturation.
(Q3 is of course off.) Equating i1 and iL gives the equation To simplify matters, we neglect the terms 0.1VOL and substitute βL ⁄ β1 = WL ⁄ W1 = 6 ⁄ 50 to obtain a quadratic equation in VOL whose solution gives VOL 0.17 V.
Toward obtaining the value of VIL we shall first find the value of vI at which i1 = iL, the diode Q3 turns off, and vO begins to decrease. Since at this point vO = 0.7 V, we assume that Q1 is in sat-uration. Transistor QL has a vDS of 0.8 V, which is less than and is thus in the triode region.
Equating i1 and iL gives Substituting βL ⁄ β1 = WL ⁄ W1 = 6 ⁄ 50 and solving the resulting equation yields vI = 0.54 V.
Figure 14.49 shows a sketch of the transfer characteristic of the inverter. The slope dvO ⁄ dvI at FIGURE 14.48 The DCFL gate with the input of the subsequent gate represented by a Schottky diode Q3.
VtD β1 2 0.7 0.2 – ( )VOL VOL 2 – [ ] 1 0.1VOL + ( ) βL 0 1 – ( ) – [ ]2 1 0.1 1.5 VOL – ( ) + [ ] = VtD β1 vI 0.2 – ( )2 1 0.1 0.7 × + ( ) βL 2 1 ( ) 1.5 0.7 – ( ) 1.5 0.7 – ( )2 – [ ] 1 0.1 1.5 0.7 – ( ) + [ ] = 22 MICROELECTRONIC CIRCUITS SEDRA/SMITH point A can be found to be −14.2 V/V. We shall consider point A as the point at which the inverter begins to switch from the high-output state; thus VIL 0.54 V.
To obtain VIH, we find the co-ordinates of point B at which dvO ⁄ dvI = −1. This can be done using a procedure similar to that employed for the MOSFET inverters and assuming Q1 to be in the triode region and QL to be in saturation. Neglecting terms in 0.1vO, the result is VIH 0.63 V.
The noise margins can now be found as The static power dissipation is determined by finding the supply current IDD in the output-high and the output-low cases. When the output is high (at 0.7 V), QL is in the triode region and the supply current is Substituting βL = 10−4 × WL = 0.6 mA/V2 results in When the output is low (at 0.17 V), QL is in saturation and the supply current is Thus the average supply current is FIGURE 14.49 Transfer characteristic of the DCFL inverter of Fig. 14.48.
0.7 0.6 0.5 0.4 0.3 0.1 0 vI (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 vO (V) A B VIH 0.63 V NML 0.37 V VOH 0.7 V VOL 0.17 V NMH 0.07 V VIL 0.54 V Slope 1 0.2 NMH V OH V IH 0.7 0.63 0.07 V = – = – ≡ NML V IL V OL 0.54 0.17 0.37 V = – = – ≡ IDD βL 2 0 1 + ( ) 1.5 0.7 – ( ) 1.5 0.7 – ( )2 – [ ] 1 0.1 1.5 0.7 – ( ) + [ ] = IDD 0.61 mA = IDD βL 0 1 + ( )2 1 0.1 1.5 0.17 – ( ) + [ ] 0.68 mA = = IDD 1 2 --- 0.61 0.68 + ( ) 0.645 mA = = JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 23 and the static power dissipation is The propagation delay tPHL is the time for the output voltage of the inverter to decrease from VOH = 0.7 V to (VOH + VOL) = 0.435 V. During this time vI is at the high level of 0.7 V, and the capacitance C (assumed to be 30 fempto Farads [fF]) is discharged by (i1 − iL); refer to Fig. 14.50(a).
The average discharge current is found by calculating i1 and iL at the beginning and at the end of the discharge interval. The result is that i1 changes from 1.34 mA to 1.28 mA and iL changes from 0.61 mA to 0.66 mA. Thus the discharge current (i1 − iL) changes from 0.73 mA to 0.62 mA for an average value of 0.675 mA. Thus To determine tPLH we refer to the circuit in Fig. 14.50(b) and note that during tPLH, vO changes from VOL = 0.17 V to (VOH + VOL) = 0.435 V. The charging current is the average value of iL, which changes from 0.8 mA to 0.66 mA. Thus = 0.73 mA and The propagation delay of the DCFL gate can now be found as As a final remark, we note that the analysis above was done using simplified device models; our objective is to show how the circuit works rather than to find accurate perfor-mance measures. These can be obtained using SPICE simulation with more elaborate models [see Roberts and Sedra (1997)].
Logic Gates Using Depletion MESFETs The DCFL circuits studied above require both enhancement and depletion devices and thus are somewhat difficult to fabricate. Also, owing to the fact that the voltage swings and noise margins are rather small, very careful control of the value of VtE is required in fabrication.
As an alternative, we now present circuits that utilize depletion devices only.
FIGURE 14.50 Circuits for calculating the propagation delays of the DCFL inverter: (a) tPHL; (b) tPLH.
PD 0.645 1.5 × 1 mW = 1 2 ---tPHL C V ∆ I ------------30 10 15 – × 0.7 0.435 – ( ) 0.675 10 3 – × ---------------------------------------------------------11.8 ps = = = 1 2 ---iL average tPLH 30 10 15 – × 0.435 0.17 – ( ) × 0.73 10 3 – × ------------------------------------------------------------------10.9 ps = = tP 1 2 --- tPHL tPLH + ( ) 11.4 ps = = 24 MICROELECTRONIC CIRCUITS SEDRA/SMITH Figure 14.51 shows the basic inverter circuit of a family of GaAs logic circuits known at FET logic (FL). The heart of the FL inverter is formed by the switching transistor QS and its load QL—both depletion-type MESFETs. Since the threshold voltage of a depletion MESFET, VtD, is negative, a negative voltage <VtD is needed to turn QS off. On the other hand the output low voltage at the drain of QS will always be positive. It follows that the logic levels at the drain of QS are not compatible with the levels required at the gate input. The incom-patibility problem is solved by simply shifting the level of the voltage down by two diode drops, that is, by approximately 1.4 V. This level shifting is accomplished by the two Schottky diodes D1 and D2. The depletion transistor QPD provides a constant-current bias for D1 and D2. To ensure that QPD operates in the saturation region at all times, its source is con-nected to a negative supply −VSS, and the value of VSS is selected to be equal to or greater than the lowest level of vO(VOL) plus the magnitude of the threshold voltage, . Transis-tor QPD also supplies the current required to discharge a load capacitance when the output voltage of the gate goes low, hence the name “pull-down” transistor and the subscript PD.
To see how the inverter of Fig. 14.51 operates, refer to its transfer characteristic, shown in Fig. 14.52. The circuit is usually designed using MESFETs having equal channel lengths (typ-ically 1 µm) and having widths WS = WL = 2WPD. The transfer characteristic shown is for the case VtD = −0.9 V. For vI lower than VtD, QS will be off and QL will operate in saturation, sup-plying a constant current IL to D1 and D2. Transistor QPD will also operate in saturation with a constant current . The difference between the two currents will flow through the gate terminal of the input transistor of the next gate in the chain, QS2. Thus the input Schottky diode of QS2 clamps the output voltage vO to approximately 0.7 V, which is the output high level, VOH.
(Note that for this discussion we shall neglect the finite output resistance in saturation.) As vI is raised above VtD, QS turns on. Since its drain is at +2.1 V, QS will operate in the sat-uration region and will take away some of the current supplied by QL. Thus the current flowing into the gate of QS2 decreases by an equal amount. If we keep increasing vI, a value is reached for which the current in QS equals , thus leaving no current to flow through the gate of QS2.
This corresponds to the point labeled A on the transfer characteristic. A further slight increase in vI will cause the voltage to fall to the point B where QS enters the triode region. The segment AB of the transfer curve represents the high-gain region of operation, having a slope equal to −gms R where R denotes the total equivalent resistance at the drain node. Note that this segment is shown as vertical in Fig. 14.52 because we are neglecting the output resistance in saturation.
FIGURE 14.51 An inverter circuit utilizing depletion-mode devices only. Schottky diodes are employed to shift the output logic levels to values compatible with the input levels required to turn the depletion MESFET QS on and off. This circuit is known as FET logic (FL).
VDD 3 V QL vI QS D1 D2 QPD v O QS2 Subsequent gate VSS 2 V vO v ′ O VtD IPD = 1 2 ---IL 1 2 ---IL v ′ O JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 25 The segment BC of the transfer curve corresponds to QS operating in the triode region.
Here QL and QPD continue to operate in saturation and D1 and D2 remain conducting. Finally, for vI = VOH = 0.7 V, vO = VOL, which for the case VtD = −0.9 V can be found to be −1.3 V.
As indicated in Fig. 14.52, the FL inverter exhibits much higher noise margins than those for the DCFL circuit. The FL inverter, however, requires two power supplies.
The FL inverter can be used to construct a NOR gate by simply adding transistors with drain and source connected in parallel with those of QS.
FIGURE 14.52 Transfer characteristic of the FL inverter of Fig. 14.51.
1.27 V 0.7 V IH EXERCISE 14.30 Verify that the co-ordinates of points A, B, and C of the transfer characteristic are as indicated in Fig. 14.52. Let VtD = −0.9 V and λ = 0.
26 MICROELECTRONIC CIRCUITS SEDRA/SMITH Schottky Diode FET Logic (SDFL) If the diode level-shifting network of the FL inverter is connected at the input side of the gate, rather than at the output side, we obtain the circuit shown in Fig. 14.53(a). This inverter operates in much the same manner as the FL inverter. The modified circuit, how-ever, has a very interesting feature: The NOR function can be implemented by simply con-necting additional diodes, as shown in Fig. 14.53(b). This logic form is known as Schottky diode FET logic (SDFL). SDFL permits higher packing density than other forms of MESFET logic because only an additional diode, rather than an additional transistor, is required for each additional input, and diodes require much smaller areas than transistors.
Buffered FET Logic (BFL) Another variation on the basic FL inverter of Fig. 14.51 is possible. A source follower can be inserted between the drain of QS and the diode level-shifting network. The resulting gate, shown for the case of a two-input NOR, is depicted in Fig. 14.54. This form of GaAs logic circuit is known as buffered FET logic (BFL). The source-follower transistor QSF increases the output current-driving capability, thus decreasing the low-to-high propagation time. FL, BFL, and SDFL feature propagation delays of the order of 100 ps and power dissipation of the order of 10 mW/gate.
FIGURE 14.53 (a) An SDFL inverter. (b) An SDFL NOR gate.
VSS 2 V QPD QL D2 VDD 3 V D1A D1B A B Y A B vI VSS 2 V (a) (b) QPD QL vO D2 VDD 3 V QS D1 FIGURE 14.54 A BFL two-input NOR gate. The gate is formed by inserting a source-follower transistor QSF between the inverting stage and the level-shifting stage. JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 27 14.3 TRANSISTOR–TRANSISTOR LOGIC (TTL OR T2L) For more than two decades (late 1960s to late 1980s) TTL enjoyed immense popularity.
Indeed, the bulk of digital systems applications employing SSI and MSI packages were designed using TTL.
We shall begin this section with a study of the evolution of TTL from DTL. In this way we shall explain the function of each of the stages of the complete TTL gate circuit. Charac-teristics of standard TTL gates will be studied in Section 14.4. Standard TTL, however, has now been virtually replaced with more advanced forms of TTL that feature improved per-formance. These will be discussed in Section 14.5.
Evolution of TTL from DTL The basic DTL gate circuit in discrete form was discussed in the previous section (see Fig. 14.6). The integrated-circuit form of the DTL gate is shown in Fig. 14.7 with only one input indicated. As a prelude to introducing TTL, we have drawn the input diode as a diode-connected transistor (Q1), which corresponds to how diodes are made in IC form.
This circuit differs from the discrete DTL circuit of Fig. 14.6 in two important aspects.
First, one of the steering diodes is replaced by the base–emitter junction of a transistor (Q2) that is either cut off (when the input is low) or in the active mode (when the input is high). This is done to reduce the input current and thereby increase the fan-out capability of the gate. A detailed explanation of this point, however, is not relevant to our study of TTL. Second, the resistance RB is returned to ground rather than to a negative supply, as was done in the earlier discrete circuit. An obvious advantage of this is the elimination of the additional power supply.
The disadvantage, however, is that the reverse base current available to remove the excess charge stored in the base of Q3 is rather small. We shall elaborate on this point below. FIGURE 14.7 IC form of the DTL gate with the input diode shown as a diode-connected transistor (Q1).
Only one input terminal is shown.
28 MICROELECTRONIC CIRCUITS SEDRA/SMITH Reasons for the Slow Response of DTL The DTL gate has relatively good noise margins and reasonably good fan-out capability. Its response, however, is rather slow. There are two reasons for this: first, when the input goes low and Q2 and D turn off, the charge stored in the base of Q3 has to leak through RB to ground. The initial value of the reverse base current that accomplishes this “base discharg-ing” process is approximately 0.7 V/RB, which is about 0.14 mA. Because this current is quite small in comparison to the forward base current, the time required for the removal of base charge is rather long, which contributes to lengthening the gate delay.
The second reason for the relatively slow response of DTL derives from the nature of the output circuit of the gate, which is simply a common-emitter transistor. Figure 14.8 shows the output transistor of a DTL gate driving a capacitive load CL. The capacitance CL repre-sents the input capacitance of another gate and/or the wiring and parasitic capacitances that are inevitably present in any circuit. When Q3 is turned on, its collector voltage cannot instantaneously fall because of the existence of CL. Thus Q3 will not immediately saturate but rather will operate in the active region. The collector of Q3 will therefore act as a constant-current source and will sink a relatively large current (βIB). This large current will rapidly discharge CL. We thus see that the common-emitter output stage features a short turn-on time. However, turnoff is another matter. Consider next the operation of the common-emitter output stage when Q3 is turned off.
The output voltage will not rise immediately to the high level (VCC). Rather, CL will charge up to VCC through RC. This is a rather slow process, and it results in lengthening the DTL gate delay (and similarly the RTL gate delay).
Having identified the two reasons for the slow response of DTL, we shall see in the fol-lowing how these problems are remedied in TTL.
Input Circuit of the TTL Gate Figure 14.9 shows a conceptual TTL gate with only one input terminal indicated. The most important feature to note is that the input diode has been replaced by a transistor. One can EXERCISE 14.4 Consider the DTL gate circuit shown in Fig. 14.7 and assume that β(Q2) = β(Q3) = 50. (a) When vI = 0.2 V, find the input current. (b) When vI = +5 V, find the base current of Q3.
Ans. (a) 1.1 mA; (b) 1.6 mA FIGURE 14.8 The output circuit of a DTL gate driving a capacitive load CL. JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 29 think of this simply as if the short circuit between base and collector of Q1 in Fig. 14.7 has been removed.
To see how the conceptual TTL circuit of Fig. 14.9 works, let the input vI be high (say, vI = VCC). In this case current will flow from VCC through R, thus forward-biasing the base− collector junction of Q1. Meanwhile, the base−emitter junction of Q1 will be reverse-biased.
Therefore Q1 will be operating in the inverse active mode—that is, in the active mode but with the roles of emitter and collector interchanged. The voltages and currents will be as indicated in Fig. 14.10, where the current I can be calculated from In actual TTL circuits Q1 is designed to have a very low reverse β (βR 0.02). Thus the gate input current will be very small, and the base current of Q3 will be approximately equal to I.
This current will be sufficient to drive Q3 into saturation, and the output voltage will be low (0.1 to 0.2 V).
Next let the gate input voltage be brought down to the logic-0 level (say, vI 0.2 V).
The current I will then be diverted to the emitter of Q1. The base−emitter junction of Q1 will become forward-biased, and the base voltage of Q1 will therefore drop to 0.9 V. Since Q3 was in saturation, its base voltage will remain at +0.7 V pending the removal of the excess charge stored in the base region. Figure 14.11 indicates the various voltage and current val-ues immediately after the input is lowered. We see that Q1 will be operating in the normal FIGURE 14.10 Analysis of the conceptual TTL gate when the input is high.
FIGURE 14.9 Conceptual form of TTL gate. Only one input terminal is shown.
I V CC 1.4 – R -----------------------= 30 MICROELECTRONIC CIRCUITS SEDRA/SMITH active mode3 and its collector will carry a large current (βFI). This large current rapidly dis-charges the base of Q3 and drives it into cutoff. We thus see the action of Q1 in speeding up the turn-off process.
As Q3 turns off, the voltage at its base is reduced, and Q1 enters the saturation mode.
Eventually the collector current of Q1 will become negligibly small, which implies that its VCEsat will be approximately 0.1 V and the base of Q3 will be at about 0.3 V, which keeps Q3 in cutoff.
Output Circuit of the TTL Gate The above discussion illustrates how one of the two problems that slow down the operation of DTL is solved in TTL. The second problem, the long rise time of the output waveform, is solved by modifying the output stage, as we shall now explain.
First, recall that the common-emitter output stage provides fast discharging of load capacitance but rather slow charging. The opposite is obtained in the emitter-follower output stage shown in Fig. 14.12. Here, as vI goes high, the transistor turns on and provides a low output resistance (characteristic of emitter followers), which results in fast charging of CL.
On the other hand, when vI goes low, the transistor turns off and CL is then left to discharge slowly through RE. FIGURE 14.11 Voltage and current values in the conceptual TTL circuit immediately after the input volt-age is lowered.
3 Although the collector voltage of Q1 is lower than its base voltage by 0.2 V, the collector–base junction will in effect be cut off and Q1 will be operating in the active mode.
RE CL FIGURE 14.12 An emitter-follower output stage with capacitive load. JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 31 It follows that an optimum output stage would be a combination of the common-emitter and the emitter-follower configurations. Such an output stage, shown in Fig. 14.13, has to be driven by two complementary signals vI1 and vI2. When vI1 is high vI2 will be low, and in this case Q3 will be on and saturated, and Q4 will be off. The common-emitter transistor Q3 will then provide the fast discharging of load capacitance and in steady state provide a low resis-tance (RCEsat) to ground. Thus when the output is low, the gate can sink substantial amounts of current through the saturated transistor Q3.
When vI1 is low and vI2 is high, Q3 will be off and Q4 will be conducting. The emitter fol-lower Q4 will then provide fast charging of load capacitance. It also provides the gate with a low output resistance in the high state and hence with the ability to source a substantial amount of load current.
Because of the appearance of the circuit in Fig. 14.13, with Q4 stacked on top of Q3, the circuit has been given the name totem-pole output stage. Also, because of the action of Q4 in pulling up the output voltage to the high level, Q4 is referred to as the pull-up transistor.
Since the pulling up is achieved here by an active element (Q4), the circuit is said to have an active pull-up. This is in contrast to the passive pull-up of RTL and DTL gates. Of course, the common-emitter transistor Q3 provides the circuit with active pull-down. Finally, note that a special driver circuit is needed to generate the two complementary signals vI1 and vI2.
EXAMPLE 14.1 We wish to analyze the circuit shown together with its driving waveforms in Fig. 14.14 to deter-mine the waveform of the output signal vO. Assume that Q3 and Q4 have β = 50. Solution Consider first the situation before vI1 goes high—that is, at time t < 0. In this case Q3 is off and Q4 is on, and the circuit can be simplified to that shown in Fig. 14.15. In this simplified circuit we have replaced the voltage divider (R1, R2) by its Thévenin equivalent. In the steady state, CL will be charged to the output voltage vO, whose value can be obtained as follows: Substituting VBE 0.7 V and IB = IE ⁄ (β + 1) = IE ⁄ 51 gives IE = 2.59 mA. Thus the output voltage vO is given by FIGURE 14.13 The totem-pole output stage.
5 10 IB VBE IE 0.5 2.5 + × + + × = vO 2.5 IE 0.5 × + 3.79 V = = 32 MICROELECTRONIC CIRCUITS SEDRA/SMITH We next consider the circuit as vI1 goes high and vI2 goes low. Transistor Q3 turns on and transis-tor Q4 turns off, and the circuit simplifies to that shown in Fig. 14.16. Again we have used the Thévenin equivalent of the divider (R1, R2). We shall also assume that the switching times of the transistors are negligibly small. Thus at t = 0+ the base current of Q3 becomes Since at t = 0 the collector voltage of Q3 is 3.79 V, and since this value cannot change instanta-neously because of CL, we see that at t = 0+ transistor Q3 will be in the active mode. The collector current of Q3 will be βIB, which is 21.5 mA, and the circuit will have the equivalent shown in Fig. 14.17(a). A simpler version of this equivalent circuit, obtained using Thévenin’s theorem, is shown in Fig. 14.17(b).
The equivalent circuit of Fig. 14.17 applies as long as Q3 remains in the active mode. This condition persists while CL is being discharged and until vO reaches about +0.3 V, at which time Q3 enters saturation. This is illustrated by the waveform in Fig. 14.18. The time for the output FIGURE 14.14 Circuit and input waveforms for Example 14.1.
FIGURE 14.15 The circuit of Fig. 14.14 when Q3 is off. 0 V IB 5 0.7 – 10 ----------------0.43 mA = = JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 33 FIGURE 14.16 The circuit of Fig. 14.14 when Q4 is off.
FIGURE 14.17 (a) Equivalent circuit for the circuit in Fig. 14.16 when Q3 is in the active mode. (b) Sim-pler version of the circuit in (a) obtained using Thévenin’s theorem.
FIGURE 14.18 Details of the output voltage waveform for the circuit in Fig. 14.14.
34 MICROELECTRONIC CIRCUITS SEDRA/SMITH voltage to fall from +3.79 V to +0.3 V, which can be considered the fall time tf, can be obtained from which results in where Thus tf = 3.4 ns.
After Q3 enters saturation, the capacitor discharges further to the final steady-state value of VCEsat (0.2 V). The transistor model that applies during this interval is more complex; since the interval in question is quite short, we shall not pursue the matter further.
Consider next the situation as vI1 goes low and vI2 goes high at t = T. Transistor Q3 turns off as Q4 turns on. We shall assume that this occurs immediately, and thus at t = T+ the circuit sim-plifies to that in Fig. 14.15. We have already analyzed this circuit in the steady state and thus know that eventually vO will reach +3.79 V. Thus vO rises exponentially from +0.2 V toward +3.79 V with a time constant of CL{0.5 kΩ//[10 kΩ/(β + 1)]}, where we have neglected the emit-ter resistance re. Denoting this time constant τ1, we obtain τ1 = 2.8 ns. Defining the rise time tr as the time for vO to reach 90% of the final value, we obtain , which results in tr = 6.4 ns. Figure 14.18 illustrates the details of the output voltage waveform.
The Complete Circuit of the TTL Gate Figure 14.19 shows the complete TTL gate circuit. It consists of three stages: the input tran-sistor Q1, whose operation has already been explained, the driver stage Q2, whose function is to generate the two complementary voltage signals required to drive the totem-pole circuit, FIGURE 14.19 The complete TTL gate circuit with only one input terminal indicated.
8.25 – 8.25 – 3.79 – ( )e tf – τ ⁄ – 0.3 = tf 0.34τ τ CL 0.5 kΩ × 10 ns = = 3.79 3.79 0.2 – ( )e tr τ1 ⁄ – 0.9 3.79 × = – JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 35 which is the third (output) stage of the gate. The totem-pole circuit in the TTL gate has two additional components: the 130-Ω resistance in the collector circuit of Q4 and the diode D in the emitter circuit of Q4. The function of these two additional components will be explained shortly. Notice that the TTL gate is shown with only one input terminal indicated. Inclusion of additional input terminals will be considered in Section 14.4.
Because the driver stage Q2 provides two complementary (that is, out-of-phase) signals, it is known as a phase splitter.
We shall now provide a detailed analysis of the TTL gate circuit in its two extreme states: one with the input high and one with the input low.
Analysis When the Input Is High When the input is high (say, +5 V), the various voltages and currents of the TTL circuit will have the values indicated in Fig. 14.20. The analysis illustrated in Fig. 14.20 is quite straightforward, and the order of the steps followed is indicated by the circled numbers. As expected, the input transistor is operating in the inverse active mode, and the input current, called the input high current IIH, is small; that is, where we assume that .
The collector current of Q1 flows into the base of Q2, and its value is sufficient to satu-rate the phase-splitter transistor Q2. The latter supplies the base of Q3 with sufficient current to drive it into saturation and lower its output voltage to VCEsat (0.1 to 0.2 V). The voltage at the collector of Q2 is VBE3 + VCEsat(Q2), which is approximately +0.9 V. If diode D were not included, this voltage would be sufficient to turn Q4 on, which is contrary to the proper oper-ation of the totem-pole circuit. Including diode D ensures that both Q4 and D remain off.
IIH βRI 15 µA = βR 0.02 FIGURE 14.20 Analysis of the TTL gate with the input high. The circled numbers indicate the order of the analysis steps.
36 MICROELECTRONIC CIRCUITS SEDRA/SMITH The saturated transistor Q3 then establishes the low output voltage of the gate (VCEsat) and provides a low impedance to ground.
In the low-output state the gate can sink a load current iL, provided that the value of iL does not exceed β × 2.6 mA, which is the maximum collector current that Q3 can sustain while remaining in saturation. Obviously the greater the value of iL, the greater the output voltage will be. To maintain the logic-0 level below a certain specified limit, a correspond-ing limit has to be placed on the load current iL. As will be seen shortly, it is this limit that determines the maximum fan-out of the TTL gate.
Figure 14.21 shows a sketch of the output voltage vO versus the load current iL of the TTL gate when the output is low. This is simply the vCE−iC characteristic curve of Q3 mea-sured with a base current of 2.6 mA. Note that at iL = 0, vO is the offset voltage, which is about 100 mV.
Analysis When the Input Is Low Consider next the operation of the TTL gate when the input is at the logic-0 level (0.2 V).
The analysis is illustrated in Fig. 14.22, from which we see that the base−emitter junction of Q1 will be forward-biased and the base voltage will be approximately +0.9 V. Thus the current I can be found to be approximately 1 mA. Since 0.9 V is insufficient to forward-bias the series combination of the collector–base junction of Q1 and the base−emitter junction of Q2 (at least 1.2 V would be required), the latter will be off. Therefore the collector current of Q1 will be almost zero and Q1 will be saturated, with VCEsat 0.1 V. Thus the base of Q2 will be at approximately +0.3 V, which is indeed insufficient to turn Q2 on.
The gate input current in the low state, called input-low current IIL, is approximately equal to the current I ( 1 mA) and flows out of the emitter of Q1. If the TTL gate is driven FIGURE 14.21 The vO–iL characteristic of the TTL gate when the output is low.
EXERCISE 14.5 Assume that the saturation portion of the vO−iL characteristic shown in Fig. 14.21 can be approximated by a straight line (of slope = 8 Ω) that intersects the vO axis at 0.1 V. Find the maximum load current that the gate is allowed to sink if the logic-0 level is specified to be ≤0.3 V.
Ans. 25 mA JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 37 by another TTL gate, the output transistor Q3 of the driving gate should sink this current IIL.
Since the output current that a TTL gate can sink is limited to a certain maximum value, the maximum fan-out of the gate is directly determined by the value of IIL.
Let us continue with our analysis of the TTL gate. When the input is low, we see that both Q2 and Q3 will be off. Transistor Q4 will be on and will supply (source) the load current iL. Depending on the value of iL, Q4 will be either in the active mode or in the saturation mode.
With the gate output terminal open, the current iL will be very small (mostly leakage) and the two junctions (base−emitter junction of Q4 and diode D) will be barely conducting.
Assuming that each junction has a 0.65-V drop and neglecting the voltage drop across the 1.6-kΩ resistance, we find that the output voltage will be FIGURE 14.22 Analysis of the TTL gate when the input is low. The circled numbers indicate the order of the analysis steps.
6 5 4 2 1 vI 0.2 V (off) 0 mA 0.3 V 0.9 V 5 0.9 4 1 mA I IIL 1 mA 3 0 V 1.6 k VCC 5 V 7 4 k 1 k 130 Q2 Q3 iL vo Q4 (off) 0 mA Q1 D EXERCISES 14.6 Consider the TTL gate analyzed in Exercise 14.5. Find its maximum allowable fan-out using the value of IIL calculated above.
Ans. 25 14.7 Use Eq. (4.114) to find VCEsat of transistor Q1 when the input of the gate is low (0.2 V). Assume that βF = 50 and βR = 0.02.
Ans. 98 mV vO 5 0.65 – 0.65 – 3.7 V = 38 MICROELECTRONIC CIRCUITS SEDRA/SMITH As iL is increased, Q4 and D conduct more heavily, but for a range of iL, Q4 remains in the active mode, and vO is given by (14.4) If we keep increasing iL, a value will be reached at which Q4 saturates. Then the output volt-age becomes determined by the 130-Ω resistance according to the approximate relationship (14.5) Function of the 130-Ω Resistance At this point the reason for including the 130-Ω resistance should be evident: It is simply to limit the current that flows through Q4, especially in the event that the output terminal is accidentally short-circuited to ground. This resistance also limits the supply current in another circumstance, namely, when Q4 turns on while Q3 is still in saturation. To see how this occurs, consider the case where the gate input was high and then is suddenly brought down to the low level. Transistor Q2 will turn off relatively fast because of the availability of a large reverse current supplied to its base terminal by the collector of Q1. On the other hand, the base of Q3 will have to discharge through the 1-kΩ resistance, and thus Q3 will take some time to turn off. Meanwhile Q4 will turn on, and a large current pulse will flow through the series combination of Q4 and Q3. Part of this current will serve the useful pur-pose of charging up any load capacitance to the logic-1 level. The magnitude of the current pulse will be limited by the 130-Ω resistance to about 30 mA.
The occurrence of these current pulses of short duration (called current spikes) raises another important issue. The current spikes have to be supplied by the VCC source and, because of its finite source resistance, will result in voltage spikes (or “glitches”) super-imposed on VCC. These voltage spikes could be coupled to other gates and flip-flops in the digital system and thus might produce false switching in other parts of the system. This effect, which might loosely be called crosstalk, is a problem in TTL systems. To reduce the size of the voltage spikes, capacitors (called bypass capacitors) should be connected between the supply rail and ground at frequent locations. These capacitors lower the impedance of the supply-voltage source and hence reduce the magnitude of the voltage spikes. Alternatively, one can think of the bypass capacitors as supplying the impulsive cur-rent spikes. vO VCC iL β 1 + ------------1.6 kΩ VBE4 – × – VD – = vO VCC iL 130 V CEsat – × Q4 ( ) – −VD EXERCISES 14.8 Assuming that Q4 has β = 50 and that at the verge of saturation VCEsat = 0.3 V, find the value of iL at which Q4 saturates.
Ans. 4.16 mA 14.9 Assuming that at a current of 1 mA the voltage drops across the emitter−base junction of Q4 and the diode D are each 0.7 V, find vO when iL = 1 mA and 10 mA. (Note the result of the previous exercise.) Ans. 3.6 V; 2.7 V 14.10 Find the maximum current that can be sourced by a TTL gate while the output high level (VOH) remains greater than the minimum guaranteed value of 2.4 V.
Ans. 12.3 mA; or, more accurately, taking the base current of Q4 into account, 13.05 mA JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 39 14.4 CHARACTERISTICS OF STANDARD TTL Because of its historical popularity and continued importance, TTL will be studied further in this and the next sections. In this section we shall consider some of the important char-acteristics of standard TTL gates. Special improved forms of TTL will be dealt with in Section 14.5.
Transfer Characteristic Figure 14.23 shows the TTL gate together with a sketch of its voltage transfer characteristic drawn in a piecewise-linear fashion. The actual characteristic is, of course, a smooth curve.
We shall now explain the transfer characteristic and calculate the various break-points and slopes. It will be assumed that the output terminal of the gate is open.
Segment AB is obtained when transistor Q1 is saturated, Q2 and Q3 are off, and Q4 and D are on. The output voltage is approximately two diode drops below VCC. At point B the phase split-ter (Q2) begins to turn on because the voltage at its base reaches 0.6 V (0.5 V + VCEsat of Q1).
Over segment BC, transistor Q1 remains saturated, but more and more of its base current I gets diverted to its base−collector junction and into the base of Q2, which operates as a lin-ear amplifier. Transistor Q4 and diode D remain on, with Q4 acting as an emitter follower.
Meanwhile the voltage at the base of Q3, although increasing, remains insufficient to turn Q3 on (less than 0.6 V).
Let us now find the slope of segment BC of the transfer characteristic. Let the input vI increase by an increment ∆vI. This increment appears at the collector of Q1, since the satu-rated Q1 behaves (approximately) as a three-terminal short circuit as far as signals are FIGURE 14.23 The TTL gate and its voltage transfer characteristic.
(a) (b) 40 MICROELECTRONIC CIRCUITS SEDRA/SMITH concerned. Thus at the base of Q2 we have a signal ∆vI. Neglecting the loading of emitter follower Q4 on the collector of Q2, we can find the gain of the phase splitter from (14.6) The value of re2 will obviously depend on the current in Q2. This current will range from zero (as Q2 begins to turn on) to the value that results in a voltage of about 0.6 V at the emitter of Q2 (the base of Q3). This value is about 0.6 mA and corresponds to point C on the transfer charac-teristic. Assuming an average current in Q2 of 0.3 mA, we obtain re2 83 Ω. For α = 0.98, Eq. (14.6) results in a gain value of 1.45. Since the gain of the output follower Q4 is close to unity, the overall gain of the gate, which is the slope of the BC segment, is about −1.45.
As already implied, breakpoint C is determined by Q3 starting to conduct. The corre-sponding input voltage can be found from At this point the emitter current of Q2 is approximately 0.6 mA. The collector current of Q2 is also approximately 0.6 mA; neglecting the base current of Q4, the voltage at the collector of Q2 is Thus Q2 is still in the active mode. The corresponding output voltage is As vI is increased past the value of vI(C) = 1.2 V, Q3 begins to conduct and operates in the active mode. Meanwhile, Q1 remains saturated, and Q2 and Q4 remain in the active mode. The circuit behaves as an amplifier until Q2 and Q3 saturate and Q4 cuts off. This occurs at point D on the transfer characteristic, which corresponds to an input voltage vI(D) obtained from Note that we have in effect assumed that at point D transistor Q1 is still saturated, but with VCEsat 0. To see how this comes about, note that from point B on, more and more of the base current of Q1 is diverted to its base−collector junction. Thus while the drop across the base−collector junction increases, that across the base−emitter junction decreases. At point D these drops become almost equal. For vI > vI(D) the base−emitter junction of Q1 cuts off; thus Q1 leaves saturation and enters the inverse active mode.
Calculation of gain over the segment CD is a relatively complicated task. This is due to the fact that there are two paths from input to output: one through Q3 and one through Q4. A simple but gross approximation for the gain of this segment can be obtained from the coor-dinates of points C and D in Fig. 14.23(b), as follows: vc2 vb2 -------α2R1 – re2 R2 + ------------------= vI C ( ) VBE3 VBE2 V CEsat Q1 ( ) – + = 0.6 0.7 0.1 – + = 1.2 V = vC2 C ( ) 5 0.6 1.6 4 V ≅ × – = vO C ( ) 4 0.65 – 0.65 – 2.7 V = = vI D ( ) VBE3 VBE2 VBC1 VBE1 – + + = 0.7 0.7 0.7 0.7 – + + = 1.4 V = Gain vO C ( ) vO D ( ) – vI D ( ) vI C ( ) – ------------------------------------– = 2.7 0.1 – 1.4 1.2 – ---------------------– = 13 V/V – = JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 41 From the transfer curve of Fig. 14.23(b) we can determine the critical points and the noise margins as follows: VOH = 3.7 V; VIL is somewhere in the range of 0.5 V to 1.2 V, and thus a conservative estimate would be 0.5 V; VOL = 0.1 V; VIH = 1.4 V; NMH = VOH − VIH = 2.3 V; and NML = VIL − VOL = 0.4 V. It should be noted that these values are computed assuming that the gate is not loaded and without taking into account power-supply or tem-perature variations.
Manufacturers’ Specifications Manufacturers of TTL usually provide curves for the gate transfer characteristic, the input i−v characteristic, and the output i−v characteristic, measured at the limits of the specified oper-ating temperature range. In addition, guaranteed values are usually given for the parameters VOL, VOH, VIL, and VIH. For standard TTL (known as the 74 series) these values are VOL = 0.4 V, VOH = 2.4 V, VIL = 0.8 V, and VIH = 2 V. These limit values are guaranteed for a specified tolerance in power-supply voltage and for a maximum fan-out of 10. From our discussion in Section 14.3 we know that the maximum fan-out is determined by the maximum current that Q3 can sink while remaining in saturation and while maintaining a saturation voltage lower than a guaranteed maximum (VOL = 0.4 V). Calculations performed in Section 14.3 indicate the possibility of a maximum fan-out of 20 to 30. Thus the figure specified by the manufac-turer is appropriately conservative.
The parameters VOL, VOH, VIL, and VIH can be used to compute the noise margins as follows: EXERCISE 14.11 Taking into account the fact that the voltage across a forward-biased pn junction changes by about −2 mV/°C, find the coordinates of points A, B, C, and D of the gate transfer characteristic at −55°C and at +125°C. Assume that the characteristic in Fig. 14.23(b) applies at 25°C, and neglect the small tem-perature coefficient of VCEsat.
Ans. At −55°C: (0, 3.38), (0.66, 3.38), (1.52, 2.16), (1.72, 0.1); at +125°C: (0, 4.1), (0.3, 4.1), (0.8, 3.46), (1.0, 0.1) NMH VOH VIH – 0.4 V = = NML VIL VOL – 0.4 V = = EXERCISES 14.12 In Section 14.3 we found that when the gate input is high, the base current of Q3 is approximately 2.6 mA. Assume that this value applies at 25°C and that at this temperature VBE 0.7 V. Taking into account the −2-mV/°C temperature coefficient of VBE and neglecting all other changes, find the base current of Q3 at −55°C and at +125°C.
Ans. 2.2 mA; 3 mA 42 MICROELECTRONIC CIRCUITS SEDRA/SMITH Propagation Delay The propagation delay of TTL gates is defined conventionally as the time between the 1.5-V points of corresponding edges of the input and output waveforms. For standard TTL (also known as medium-speed TTL) tP is typically about 10 ns.
As far as power dissipation is concerned it can be shown (see Exercise 14.14) that when the gate output is high the gate dissipates 5 mW, and when the output is low the dissipation is 16.7 mW. Thus the average dissipation is 11 mW, resulting in a delay-power product of about 100 pJ.
Dynamic Power Dissipation In Section 14.3 the occurrence of supply current spikes was explained. These spikes give rise to additional power drain from the VCC supply. This dynamic power is also dissipated in the gate circuit. It can be evaluated by multiplying the average current due to the spikes by VCC, as illustrated by the solution of Exercise 14.15.
14.13 Figure E14.13 shows sketches of the iL−vO characteristics of a TTL gate when the output is low. Use these characteristics together with the results of Exercise 14.12 to calculate the value of β of transistor Q3 at −55°C, +25°C, and +125°C.
Ans. 16; 25; 28 FIGURE E14.13 EXERCISE 14.14 Calculate the value of the supply current (ICC), and hence the power dissipated in the TTL gate, when the output terminal is open and the input is (a) low at 0.2 V (see Fig. 14.22) and (b) high at +5 V (see Fig. 14.20).
Ans. (a) 1 mA, 5 mW; (b) 3.33 mA, 16.7 mW JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 43 The TTL NAND Gate Figure 14.24 shows the basic TTL gate. Its most important feature is the multiemitter tran-sistor Q1 used at the input. Figure 14.25 shows the structure of the multiemitter transistor.
It can be easily verified that the gate of Fig. 14.24 performs the NAND function. The output will be high if one (or both) of the inputs is (are) low. The output will be low in only EXERCISE 14.15 Consider a TTL gate that is switched on and off at the rate of 1 MHz. Assume that each time the gate is turned off (that is, the output goes high) a supply-current pulse of 30-mA amplitude and 2-ns width occurs. Also assume that no current spike occurs when the gate is turned on. Calculate the average sup-ply current due to the spikes, and the dynamic power dissipation.
Ans. 60 µA; 0.3 mW FIGURE 14.24 The TTL NAND gate.
FIGURE 14.25 Structure of the multiemitter transistor Q1.
44 MICROELECTRONIC CIRCUITS SEDRA/SMITH one case: when both inputs are high. Extension to more than two inputs is straightforward and is achieved by diffusing additional emitter regions.
Although theoretically an unused input terminal may be left open-circuited, this is gen-erally not a good practice. An open-circuit input terminal acts as an “antenna” that “picks up” interfering signals and thus could cause erroneous gate switching. An unused input ter-minal should therefore be connected to the positive power supply through a resistance (of, say, 1 kΩ). In this way the corresponding base–emitter junction of Q1 will be reverse-biased and thus will have no effect on the operation of the gate. The series resistance is included in order to limit the current in case of breakdown of the base–emitter junction due to transients on the power supply.
Other TTL Logic Circuits On a TTL MSI chip there are many cases in which logic functions are implemented using “stripped-down” versions of the basic TTL gate. As an example we show in Fig. 14.26 the TTL implementation of the AND-OR-INVERT function. As shown, the phase-splitter tran-sistors of two gates are connected in parallel, and a single output stage is used. The reader is urged to verify that the logic function realized is as indicated.
At this point it should be noted that the totem-pole output stage of TTL does not allow connecting the output terminals of two gates to realize the AND function of their outputs (known as the wired-AND connection). To see the reason for this, consider two gates whose outputs are connected together, and let one gate have a high output and the other have a low output. Current will flow from Q4 of the first gate through Q3 of the second gate. The current value will fortunately be limited by the 130-Ω resistance. Obviously, however, no useful logic function is realized by this connection.
The lack of wired-AND capability is a drawback of TTL. Nevertheless, the problem is solved in a number of ways, including doing the paralleling at the phase-splitter stage, as illustrated in Fig. 14.26. Another solution consists of deleting the emitter-follower transistor FIGURE 14.26 A TTL AND-OR-INVERT gate. JFETs, GaAs DEVICES AND CIRCUITS, AND TTL CIRCUITS 45 altogether. The result is an output stage consisting solely of the common-emitter transistor Q3 without even a collector resistance. Obviously, one can connect the outputs of such gates together to a common collector resistance and achieve a wired-AND capability. TTL gates of this type are known as open-collector TTL. The obvious disadvantage is the slow rise time of the output waveform.
Another useful variant of TTL is the tristate output arrangement explored in Exercise 14.16.
Tristate TTL enables the connection of a number of TTL gates to a common output line (or bus). At any particular time the signal on the bus will be determined by the one TTL gate EXERCISE 14.16 The circuit shown in Fig. E14.16 is called tristate TTL. Verify that when the terminal labeled Third state is high, the gate functions normally and that when this terminal is low, both transistors Q3 and Q4 cut off and the output of the gate is an open circuit. The latter state is the third state, or the high-output-impedance state.
FIGURE E14.16 46 MICROELECTRONIC CIRCUITS SEDRA/SMITH that is enabled (by raising its third-state input terminal). All other gates will be in the third state and thus will have no control of the bus.
14.5 TTL FAMILIES WITH IMPROVED PERFORMANCE The standard TTL circuits studied in the two previous sections were introduced in the mid-1960s. Since then, several improved versions have been developed. In this section we shall discuss some of these improved TTL subfamilies. As will be seen the improvements are in two directions: increasing speed and reducing power dissipation.
The speed of the standard TTL gate of Fig. 14.24 is limited by two mechanisms: first, transistors Q1, Q2, and Q3 saturate, and hence we have to contend with their finite storage time. Although Q2 is discharged reasonably quickly because of the active mode of operation of Q1, as already explained, this is not true for Q3, whose base charge has to leak out through the 1-kΩ resistance in its base circuit. Second, the resistances in the circuit, together with the various transistor and wiring capacitances, form relatively long time constants, which con-tribute to lengthening the gate delay.
It follows that there are two approaches to speeding up the operation of TTL. The first is to prevent transistor saturation and the second is to reduce the values of all resistances. Both approaches are utilized in the Schottky TTL circuit family.
Schottky TTL In Schottky TTL, transistors are prevented from saturation by connecting a low-voltage-drop diode between base and collector, as shown in Fig. 14.27. These diodes, formed as a metal-to-semiconductor junction, are called Schottky diodes and have a forward voltage drop of about 0.5 V. We have briefly discussed Schottky diodes in Section 3.9. Schottky diodes4 are easily fabricated and do not increase chip area. In fact, the Schottky TTL fabri-cation process has been designed to yield transistors with smaller areas and thus higher β and fT than those produced by the standard TTL process. Figure 14.27 also shows the sym-bol used to represent the combination of a transistor and a Schottky diode, referred to as a Schottky transistor. 4 Note that silicon Schottky diodes exhibit voltage drops of about 0.5 V, whereas GaAs Schottky diodes (Section 5.12) exhibit voltage drops of about 0.7 V.
(a) (b) FIGURE 14.27 (a) A transistor with a Schottky diode clamp. (b) Circuit symbol for the connection in (a), known as a Schottky transistor.
922 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS 9.7 DATA CONVERTERS—AN INTRODUCTION In this section we begin the study of another group of analog IC circuits of great importance; namely, data converters.
9.7.1 Digital Processing of Signals Most physical signals, such as those obtained at transducer outputs, exist in analog form.
Some of the processing required on these signals is most conveniently performed in an analog fashion. For instance, in instrumentation systems it is quite common to use a high-input-impedance, high-gain, high-CMRR differential amplifier right at the output of the transducer. This is usually followed by a filter whose purpose is to eliminate interference.
However, further signal processing is usually required, which can range from simply obtain-ing a measurement of signal strength to performing some algebraic manipulations on this and related signals to obtain the value of a particular system parameter of interest, as is usu-ally the case in systems intended to provide a complex control function. Another example of signal processing can be found in the common need for transmission of signals to a remote receiver.
Many such forms of signal processing can be performed by analog means. In earlier chapters we encountered circuits for implementing a number of such tasks. However, an attractive alternative exists: It is to convert, following some initial analog processing, the signal from analog to digital form and then use economical, accurate, and convenient digital ICs to perform digital signal processing. Such processing can in its simplest form provide us with a measure of the signal strength as an easy-to-read number (consider, e.g., the digital voltmeter). In more involved cases the digital signal processor can perform a variety of arithmetic and logic operations that implement a filtering algorithm. The resulting digital filter does many of the same tasks that an analog filter performs—namely, eliminate inter-ference and noise. Yet another example of digital signal processing is found in digital com-munications systems, where signals are transmitted as a sequence of binary pulses, with the obvious advantage that corruption of the amplitudes of these pulses by noise is, to a large extent, of no consequence.
Once digital signal processing has been performed, we might be content to display the result in digital form, such as a printed list of numbers. Alternatively, we might require an analog output. Such is the case in a telecommunications system, where the usual output may be audible speech. If such an analog output is desired, then obviously we need to convert the digital signal back to an analog form.
It is not our purpose here to study the techniques of digital signal processing. Rather, we shall examine the interface circuits between the analog and digital domains. Specifically, we shall study the basic techniques and circuits employed to convert an analog signal to digital form (analog-to-digital or simply A/D conversion) and those used to convert a digital signal to analog form (digital-to-analog or simply D/A conversion). Digital circuits are studied in Chapters 10 and 11.
9.7.2 Sampling of Analog Signals The principle underlying digital signal processing is that of sampling the analog signal.
Figure 9.36 illustrates in a conceptual form the process of obtaining samples of an analog signal. The switch shown closes periodically under the control of a periodic pulse signal (clock). The closure time of the switch, τ, is relatively short, and the samples obtained are 9.7 DATA CONVERTERS—AN INTRODUCTION 923 stored (held) on the capacitor. The circuit of Fig. 9.36 is known as a sample-and-hold (S/H) circuit. As indicated, the S/H circuit consists of an analog switch that can be implemented by a MOSFET transmission gate (Section 10.5), a storage capacitor, and (not shown) a buffer amplifier.
Between the sampling intervals—that is, during the hold intervals—the voltage level on the capacitor represents the signal samples we are after. Each of these voltage levels is then fed to the input of an A/D converter, which provides an N-bit binary number proportional to the value of signal sample.
The fact that we can do our processing on a limited number of samples of an analog signal while ignoring the analog-signal details between samples is based on the Shannon’s sampling theorem [see Lathi (1965)].
FIGURE 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit.
The switch closes for a small part (τ seconds) of every clock period (T). (b) Input signal waveform. (c) Sam-pling signal (control signal for the switch). (d) Output signal (to be fed to A/D converter).
C vO vI (a) vO vI t t t vS T (b) (c) (d) 924 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS 9.7.3 Signal Quantization Consider an analog signal whose values range from 0 to +10 V. Let us assume that we wish to convert this signal to digital form and that the required output is a 4-bit digital signal.4 We know that a 4-bit binary number can represent 16 different values, 0 to 15; it follows that the resolution of our conversion will be 10 V. Thus an analog signal of 0 V will be represented by 0000, V will be represented by 0001, 6 V will be represented by 1001, and 10 V will be represented by 1111.
All these sample numbers are multiples of the basic increment ( V). A question now arises regarding the conversion of numbers that fall between these successive incremental levels. For instance, consider the case of a 6.2-V analog level. This falls between 18/3 and 20/3. However, since it is closer to 18/3 we treat it as if it were 6 V and code it as 1001. This process is called quantization. Obviously errors are inherent in this process; such errors are called quantization errors. Using more bits to represent (encode or, simply, code) an analog signal reduces quantization errors but requires more complex circuitry. 9.7.4 The A/D and D/A Converters as Functional Blocks Figure 9.37 depicts the functional block representations of A/D and D/A converters. As indi-cated, the A/D converter (also called an ADC) accepts an analog sample vA and produces an N-bit digital word. Conversely, the D/A converter (also called a DAC) accepts an n-bit digital word and produces an analog sample. The output samples of the D/A converter are often fed to a sample-and-hold circuit. At the output of the S/H circuit a staircase waveform, such as that in Fig. 9.38, is obtained. The staircase waveform can then be smoothed by a 4 Bit stands for binary digit.
FIGURE 9.37 The A/D and D/A converters as circuit blocks.
FIGURE 9.38 The analog samples at the output of a D/A converter are usually fed to a sample-and-hold circuit to obtain the staircase waveform shown. This waveform can then be filtered to obtain the smooth waveform, shown in color. The time delay usually introduced by the filter is not shown.
V 15 ⁄ 2 3 ---= 2 3 ---2 3 ---vA t 9.8 D/A CONVERTER CIRCUITS 925 low-pass filter, giving rise to the smooth curve shown in color in Fig. 9.38. In this way an analog output signal is reconstructed. Finally, note that the quantization error of an A/D con-verter is equivalent to least significant bit (bN).
9.8 D/A CONVERTER CIRCUITS 9.8.1 Basic Circuit Using Binary-Weighted Resistors Figure 9.39 shows a simple circuit for an N-bit D/A converter. The circuit consists of a ref-erence voltage VREF, N binary-weighted resistors R, 2R, 4R, 8R, . . . , 2N−1R, N single-pole double-throw switches S1, S2, . . . , SN, and an op amp together with its feedback resistance Rf = R/2.
The switches are controlled by an N-bit digital input word D, (9.109) where b1, b2, and so on are bit coefficients that are either 1 or 0. Note that the bit bN is the least significant bit (LSB) and b1 is the most significant bit (MSB). In the circuit in Fig. 9.39, b1 controls switch S1, b2 controls S2, and so on. When bi is 0, switch Si is in posi-tion 1, and when bi is 1 switch Si is in position 2.
Since position 1 of all switches is ground and position 2 is virtual ground, the current through each resistor remains constant. Each switch simply controls where its corresponding current goes: to ground (when the corresponding bit is 0) or to virtual ground (when the cor-responding bit is 1). The currents flowing into the virtual ground add up, and the sum flows 1 2 ---± EXERCISE 9.31 An analog signal in the range 0 to +10 V is to be converted to an 8-bit digital signal. What is the resolu-tion of the conversion in volts? What is the digital representation of an input of 6 V? What is the represen-tation of an input of 6.2 V? What is the error made in the quantization of 6.2 V in absolute terms and as a percentage of the input? As a percentage of full scale? What is the largest possible quantization error as a percentage of full scale?
Ans. 0.0392 V; 10011001; 10011110; −0.0064 V; −0.1%; −0.064%; 0.196% FIGURE 9.39 An N-bit D/A converter using a binary-weighted resistive ladder network.
D b1 2 1 -----b2 2 2 ----- . . .
bN 2 N ------+ + + = VREF 926 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS through the feedback resistance Rf. The total current iO is therefore given by Thus, (9.110) and the output voltage vO is given by vO = −iORf = −VREFD (9.111) which is directly proportional to the digital word D, as desired.
It should be noted that the accuracy of the DAC depends critically on (1) the accuracy of VREF, (2) the precision of the binary-weighted resistors, and (3) the perfection of the switches.
Regarding the third point, we should emphasize that these switches handle analog signals; thus their perfection is of considerable interest. While the offset voltage and the finite on resistance are not of critical significance in a digital switch, these parameters are of immense importance in analog switches. The use of MOSFETs to implement analog switches will be discussed in Chapter 10. Also, we shall shortly see that in practical circuit implementations of the DAC, the binary-weighted currents are generated by current sources. In this case the analog switch can be realized using the differential-pair circuit, as will be shown shortly.
A disadvantage of the binary-weighted resistor network is that for a large number of bits (N > 4) the spread between the smallest and largest resistances becomes quite large. This implies difficulties in maintaining accuracy in resistor values. A more convenient scheme exists utilizing a resistive network called the R-2R ladder.
9.8.2 R-2R Ladders Figure 9.40 shows the basic arrangement of a DAC using an R-2R ladder. Because of the small spread in resistance values, this network is usually preferred to the binary-weighted scheme discussed earlier, especially for N > 4. Operation of the R-2R ladder is straightfor-ward. First, it can be shown, by starting from the right and working toward the left, that the FIGURE 9.40 The basic circuit configuration of a DAC utilizing an R-2R ladder network.
iO V REF R -----------b1 V REF 2R -----------b2 . . .
V REF 2 N 1 – R ----------------bN + + + = 2V REF R -------------- b1 2 1 -----b2 2 2 -----. . .
bN 2 N ------+ + + = iO 2V REF R --------------D = VREF 9.8 D/A CONVERTER CIRCUITS 927 resistance to the right of each ladder node, such as that labeled X, is equal to 2R. Thus the current flowing to the right, away from each node, is equal to the current flowing downward to ground, and twice that current flows into the node from the left side. It follows that I1 = 2I2 = 4I3 = . . . = 2N−1IN (9.112) Thus, as in the binary-weighted resistive network, the currents controlled by the switches are binary weighted. The output current iO will therefore be given by (9.113) 9.8.3 A Practical Circuit Implementation A practical circuit implementation of the DAC utilizing an R-2R ladder is shown in Fig. 9.41.
The circuit utilizes BJTs to generate binary-weighted constant currents I1, I2, . . . , IN, which are switched between ground and virtual ground of an output summing op amp (not shown).
We shall first show that the currents I1 to IN are indeed binary-weighted, with I1 correspond-ing to the MSB and IN corresponding to the LSB of the DAC.
Starting at the two rightmost transistors, QN and Qt, we see that if they are matched, their emitter currents will be equal and are denoted (IN/α). Transistor Qt is included to provide proper termination of the R-2R network. The voltage between the base line of the BJTs and node N will be FIGURE 9.41 A practical circuit implementation of a DAC utilizing an R-2R ladder network.
iO V REF R -----------D = VN VBEN I N α ----- 2R ( ) + = SN 2R 2R 2R 2R 2R 2R 2R R R R R 1 2 3 N N 1 RREF VEE 0 A 0 V VREF A1 Qt IREF iO S2 S3 S1 I1 I2 I3 IN1 QREF Q1 Q2 Q3 QN 1 QN 2IN IN I3 I2 I1 IREF IN IN · · · To virtual ground of output op amp B · · · · · · · · · IN1 928 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS where is the base–emitter voltage of QN. Since the current flowing through the resistor R connected to node N is (2IN/α), the voltage between node B and node (N − 1) will be Assuming, for the moment, that we see that a voltage of (4IN/α)R appears across the resistance 2R in the emitter of QN−1. Thus QN−1 will have an emitter current of (2IN/α) and a collector current of (2IN), twice the current in QN. The two transistors will have equal VBE drops if their junction areas are scaled in the same proportion as their currents, which is usually done in practice.
Proceeding in the manner above we can show that I1 = 2I2 = 4I3 = . . . = 2N−1IN (9.114) under the assumption that the EBJ areas of Q1 to QN are scaled in a binary-weighted fashion.
Next consider op amp A1, which, together with the reference transistor QREF, forms a negative-feedback loop. (Convince yourself that the feedback is indeed negative.) A virtual ground appears at the collector of QREF forcing it to conduct a collector current IREF = VREF/RREF independent of whatever imperfections QREF might have. Now, if QREF and Q1 are matched, their collector currents will be equal, I1 = IREF Thus, the binary-weighted currents are directly related to the reference current, independent of the exact values of V BE and α. Also observe that op amp A1 supplies the base currents of all the BJTs.
9.8.4 Current Switches Each of the single-pole double-throw switches in the DAC circuit of Fig. 9.41 can be imple-mented by a circuit such as that shown in Fig. 9.42 for switch Sm. Here Im denotes the current flowing in the collector of the mth-bit transistor. The circuit is a differential pair with the FIGURE 9.42 Circuit implementation of switch Sm in the DAC of Fig. 9.41. In a BiCMOS technology, Qms and Qmr can be implemented using MOSFETs, thus avoiding the inaccuracy caused by the base current of BJTs.
VBEN VN 1 – VN 2I N α -------- R + VBEN 4I N α --------R + = = V BE N 1 – VBEN, = iO VBIAS VBIAS 9.9 A/D CONVERTER CIRCUITS 929 base of the reference transistor Qmr connected to a suitable dc voltage VBIAS, and the digital signal representing the mth bit bm applied to the base of the other transistor Qms. If the volt-age representing bm is higher than VBIAS by a few hundred millivolts, Qms will turn on and Qmr will turn off. The bit current Im will flow through Qms and onto the output summing line.
On the other hand, when bm is low, Qms will be off and Im will flow through Qmr to ground.
The current switch of Fig. 9.42 is simple and features high-speed operation. It suffers, however, from the fact that part of the current Im flows through the base of Qms and thus does not appear on the output summing line. More elaborate circuits for current switches can be found in Grebene (1984). Also, in a BiCMOS technology the differential-pair transistors Qms and Qmr can be replaced with MOSFETs, thus eliminating the base current problem. 9.9 A/D CONVERTER CIRCUITS There exist a number of A/D conversion techniques varying in complexity and speed. We shall discuss four different approaches: two simple, but slow, schemes, one complex (in terms of the amount of circuitry required) but extremely fast method, and, finally, a method particularly suited for MOS implementation.
9.9.1 The Feedback-Type Converter Figure 9.43 shows a simple A/D converter that employs a comparator, an up/down counter, and a D/A converter. The comparator circuit provides an output that assumes one of two EXERCISES 9.32 What is the maximum resistor ratio required by a 12-bit D/A converter utilizing a binary-weighted resistor network?
Ans. 2048 9.33 If the input bias current of an op amp, used as the output summer in a 10-bit DAC, is to be no more than that equivalent to LSB, what is the maximum current required to flow in Rf for an op amp whose bias current is as great as 0.5 µA?
Ans. 2.046 mA 1 4 ---FIGURE 9.43 A simple feedback-type A/D converter.
930 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS distinct values: positive when the difference input signal is positive, and negative when the difference input signal is negative. We shall study comparator circuits in Chapter 13. An up/down counter is simply a counter that can count either up or down depending on the binary level applied at its up/down control terminal. Because the A/D converter of Fig. 9.43 employs a DAC in its feedback loop it is usually called a feedback-type A/D converter. It operates as follows: With a 0 count in the counter, the D/A converter output, vO, will be zero and the output of the comparator will be high, instructing the counter to count the clock pulses in the up direction. As the count increases, the output of the DAC rises. The process continues until the DAC output reaches the value of the analog input signal, at which point the comparator switches and stops the counter. The counter output will then be the digital equivalent of the input analog voltage.
Operation of the converter of Fig. 9.43 is slow if it starts from zero. This converter how-ever, tracks incremental changes in the input signal quite rapidly.
9.9.2 The Dual-Slope A/D Converter A very popular high-resolution (12- to 14-bit) (but slow) A/D conversion scheme is illus-trated in Fig. 9.44. To see how it operates, refer to Fig. 9.44 and assume that the analog input signal vA is negative. Prior to the start of the conversion cycle, switch S2 is closed, thus discharging capacitor C and setting v1 = 0. The conversion cycle begins with opening S2 and connecting the integrator input through switch S1 to the analog input signal. Since vA is negative, a current I = vA/R will flow through R in the direction away from the integrator.
Thus v1 rises linearly with a slope of I/C = vA/RC, as indicated in Fig. 9.44(b). Simulta-neously, the counter is enabled and it counts the pulses from a fixed-frequency clock. This phase of the conversion process continues for a fixed duration T1. It ends when the counter has accumulated a fixed count denoted nREF. Usually, for an N-bit converter, nREF = 2N.
Denoting the peak voltage at the output of the integrator as VPEAK, we can write with reference to Fig. 9.44(b) (9.115) At the end of this phase, the counter is reset to zero.
Phase II of the conversion begins at t = T1 by connecting the integrator input through switch S1 to the positive reference voltage VREF. The current into the integrator reverses direction and is equal to VREF/R. Thus v1 decreases linearly with a slope of (VREF/RC). Simul-taneously the counter is enabled and it counts the pulses from the fixed-frequency clock.
When v1 reaches zero volts, the comparator signals the control logic to stop the counter.
Denoting the duration of phase II by T2, we can write, by reference to Fig. 9.44(b), (9.116) Equations (9.115) and (9.116) can be combined to yield (9.117) Since the counter reading, nREF, at the end of T1 is proportional to T1 and the reading, n, at the end of T2 is proportional to T2, we have (9.118) V PEAK T 1 --------------vA RC --------= V PEAK T2 --------------V REF RC -----------= T2 T1 vA VREF ----------- = n nREF vA VREF ----------- = 9.9 A/D CONVERTER CIRCUITS 931 FIGURE 9.44 The dual-slope A/D conversion method. Note that vA is assumed to be negative.
VREF (a) VPEAK VREF RC 932 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS Thus the content of the counter,5 n, at the end of the conversion process is the digital equiv-alent of vA.
The dual-slope converter features high accuracy, since its performance is independent of the exact values of R and C. There exist many commercial implementations of the dual-slope method, some of which utilize CMOS technology.
9.9.3 The Parallel or Flash Converter The fastest A/D conversion scheme is the simultaneous, parallel, or flash conversion process illustrated in Fig. 9.45. Conceptually, flash conversion is very simple. It utilizes 2N − 1 comparators to compare the input signal level with each of the 2N − 1 possible quantization levels. The outputs of the comparators are processed by an encoding-logic block to provide the N bits of the output digital word. Note that a complete conversion can be obtained within one clock cycle.
Although flash conversion is very fast, the price paid is a rather complex circuit imple-mentation. Variations on the basic technique have been successfully employed in the design of IC converters.
9.9.4 The Charge-Redistribution Converter The last A/D conversion technique that we shall discuss is particularly suited for CMOS implementation. As shown in Fig. 9.46, the circuit utilizes a binary-weighted capacitor array, a voltage comparator, and analog switches; control logic (not shown in Fig. 9.46) is also required. The circuit shown is for a 5-bit converter; capacitor CT serves the purpose of terminating the capacitor array, making the total capacitance equal to the desired value of 2C.
Operation of the converter can be divided into three distinct phases, as illustrated in Fig. 9.46. In the sample phase (Fig. 9.46a) switch SB is closed, thus connecting the top plate of all capacitors to ground and setting vO to zero. Meanwhile, switch SA is connected to the analog input voltage vA. Thus the voltage vA appears across the total capacitance of 2C, resulting in a stored charge of 2CvA. Thus, during this phase, a sample of vA is taken and a proportional amount of charge is stored on the capacitor array.
FIGURE 9.45 Parallel, simultaneous, or flash A/D conversion.
5 Note that n is not a continuous function of vA, as might be inferred from Eq. (9.118). Rather, n takes on discrete values corresponding to one of the 2N quantized levels of vA.
Comparator 1 Comparator 2 Comparator 2N 1 Bit 1 Bit 2 Bit N Digital output Logic Analog input VR1 VR2 VR(2 N1) · · · · · · 9.9 A/D CONVERTER CIRCUITS 933 During the hold phase (Fig. 9.46b), switch SB is opened and switches S1 to S5, and ST are thrown to the ground side. Thus the top plate of the capacitor array is open-circuited while their bottom plates are connected to ground. Since no discharge path has been provided, the capacitor charges must remain constant, with the total equal to 2CvA. It follows that the volt-age at the top plate must become −vA. Finally, note that during the hold phase, SA is con-nected to VREF in preparation for the charge-redistribution phase.
FIGURE 9.46 Charge-redistribution A/D converter suitable for CMOS implementation: (a) sample phase, (b) hold phase, and (c) charge-redistribution phase.
SB C 2 4 8 CT ST S1 S2 S3 S4 S5 SA vA VREF Control logic Comparator C 16 C 16 C C C vO 0 (a) SB C 2 4 8 CT ST S1 S2 S3 S4 S5 SA vA VREF C 16 C 16 C C C vO vA (b) SB C 2 4 8 CT ST S1 S2 S3 S4 S5 SA vA VREF C 16 C 16 C C C vO 0 (c) 934 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS Next, we consider the operation during the charge-redistribution phase illustrated in Fig. 9.46(c). First, switch S1 is connected to VREF (through SA). The circuit then consists of VREF, a series capacitor C, and a total capacitance to ground of value C. This capacitive divider causes a voltage increment of to appear on the top plates. Now, if vA is greater than , the net voltage at the top plate will remain negative, which means that S1 will be left in its new position as we move on to switch S2. If, on the other hand, vA was smaller than , then the net voltage at the top plate would become positive. The comparator will detect this situation and signal the control logic to return S1 to its ground position and then to move on to S2.
Next, switch S2 is connected to VREF, which causes a voltage increment of to appear on the top plate. If the resulting voltage is still negative, S2 is left in its new position; otherwise, S2 is returned to its ground position. We then move on to switch S3, and so on until all the bit switches S1 to S5 have been tried.
It can be seen that during the charge-redistribution phase the voltage on the top plate will be reduced incrementally to zero. The connection of the bit switches at the conclusion of this phase gives the output digital word; a switch connected to ground indicates a 0 value for the corresponding bit, whereas connection to VREF indicates a 1. The particular switch configu-ration depicted in Fig. 9.46(c) is for D = 01101. Observe that at the end of the conversion process, all the charge is stored in the capacitors corresponding to 1 bits; the capacitors of the 0 bits have been discharged.
The accuracy of this A/D conversion method is independent of the value of stray capaci-tances from the bottom plate of the capacitors to ground. This is because the bottom plates are connected either to ground or to VREF; thus the charge on the stray capacitances will not flow into the capacitor array. Also, because both the initial and the final voltages on the top plate are zero, the circuit is also insensitive to the stray capacitances between the top plates and ground.6 The insensitivity to stray capacitances makes the charge-redistribution technique a reasonably accurate method capable of implementing A/D converters with as many as 10 bits.
9.10 SPICE SIMULATION EXAMPLE We conclude this chapter with an example to illustrate the use of SPICE in the simulation of the two-stage CMOS op amp.
6 More precisely, the final voltage can deviate from zero by as much as the analog equivalent of the LSB. Thus, the insensitivity to top-plate capacitance is not complete.
VREF 2 ⁄ VREF 2 ⁄ VREF 2 ⁄ VREF 4 ⁄ EXERCISES 9.34 Consider the 5-bit charge-redistribution converter in Fig. 9.46 with VREF = 4 V. What is the voltage increment appearing on the top plate when S5 is switched? What is the full-scale voltage of this con-verter? If vA = 2.5 V, which switches will be connected to VREF at the end of conversion?
Ans. V; V; S1 and S3 9.35 Express the maximum quantization error of an N-bit A/D converter in terms of its least-significant bit (LSB) and in terms of its full-scale analog input VFS.
Ans. ± LSB; 1 8 ---31 8 ------1 2 ---VFS 2(2N 1) – ⁄ |
12555 | https://www.nrpa.org/contentassets/87a651f66deb46c89eebb36c5dec0a43/measures-evaluate-park-use-quality.pdf | Recommended Measures to Evaluate Park Use and Quality Table of Contents Introduction 1 General Park Use 2 Activity and Recreation 6 User Satisfaction 8 Community and Social Capital 10 Built Environment 11 Perceived Safety 12 Economic Impact 13 Conclusion 14 Acknowledgements 14 About the National Recreation and Park Association 15 APPENDIX: SOPARC Supplement – Case Study 16 Determining park use is helpful to inform management decisions and future investments. Photo credit: freepik.com Local parks provide a wide range of benefits to communities. Cover photo credit: freepik.com Introduction Local parks provide a wide range of benefits to communities, including opportunities for physical activity, social interaction, positive youth development, connection to nature, and mental and emotional rejuvenation. While residents in communities across the country widely use and highly value their local parks, it is important that park and recreation professionals continually monitor their inventory of park areas to ensure they meet the needs of the public. A primary method for analyzing the health and vitality of parks is through evaluations. These evaluations allow an organization to: • Better understand the park-use patterns, preferences and priorities of a community • Inform and improve park operations, maintenance and design • Identify opportunities for the park to support new or diversified programming based on community input •Justify public investment in a park and gather success stories to gain support and partnerships This resource presents an overview of measures commonly used in park evaluations. Any measures selected should be based on the purpose of the evaluation and via input from community members and key stakeholders. This resource is not exhaustive — there are many other metrics that can be used in any evaluation. 1 Recommended Measures to Evaluate Park Use and Quality Some common measures of physical activity include type of park activity and where in the park activity occurs. Photo credit: freepik.com 2. On a usual ABC Park visit, who are you with? (Check all that apply.) Nobody Young kids (under 5 yrs.) Older kids (5 to 10 yrs.) Tweens (11 to 14 yrs.) Teens (15 to 19 yrs.) Spouse/Partner Other family members Friends Pets 1. During 2018, how often did you visit ABC Park? Daily A few times per year Once per week/A few times per month Monthly Less than monthly Not at all Surveys General use can be measured by conducting a series of intercept (within the park) surveys and community surveys, which typically are administered door to door, online, via U.S. mail or by phone. While response rates for community surveys can be very low, these surveys often reveal views of non-park users and reasons why they do not use a park. Common survey questions include: ●• Frequency of use (see #1 in sample below) ●• Who is visiting (see #2 in sample below) • Duration of use (e.g., ≤15 minutes; 16-30 minutes; 31-60 minutes; >1 hour) • Timing of use (specific days or times of the week) 2 Recommended Measures to Evaluate Park Use and Quality General Park Use Why Measure Measuring the use of parks helps park and recreation agency planners and managers optimize their limited resources and provide the best experience for visitors. Measuring park use highlights barriers and helps identify and manage overcrowding. It also demonstrates the value of investment by showing the public and elected officials key metrics regarding community park use.
What to Measure Measurement includes determining the number of individuals using park areas at specific locations and points in time. Specific measures may include information on how many people are using which park facilities, their length of stay, and how individuals move throughout the space.
How to Measure Park use can be determined through a variety of methods — some more complex than others. Some require investment in technology and others rely exclusively on in-person efforts.
For more information on conducting community surveys and identifying ways to reach your community, see NRPA’s Community Needs Assessment Toolkit.
Observations This method of determining park use involves the actual counting of users and is the most objective approach to measuring use. A best practice is for an observer to be physically present in a park and count users two to four times per day for a minimum of four days, including weekdays and weekend days. Observations also work best when repeated at different times of the year to account for seasonal variation in park use. In addition, comparing observation counts year over year (or quarter over quarter, etc.) can reveal changes in park use. There are limitations to the observational approach of measuring park use, including availability of staff and volunteers to observe and count users and the possibility that inclement weather could skew results.
Observational approaches can be adapted for many settings and should include the following: • A written protocol with agreed-upon steps guiding observers on the following: • Where to stand during the observation (e.g., to the left of the playground entrance sign) • What area(s) should be observed (e.g., from the sidewalk to the right, including the set of six swings) • Timing of observations (e.g., scan each area for a short period and count everyone present; repeat every 15 minutes for one hour) • What should be counted (number of users; number of users by age group, number of visitors running) Note: Counting individuals in subjective categories — like age groups, race/ethnicity and categories that involve estimation — can be tricky; the observation team should discuss and practice a consistent approach.
3 Recommended Measures to Evaluate Park Use and Quality Park staff members or volunteers can conduct intercept surveys of park users in real time. In this type of data collection, surveyors position themselves within a park, approach park visitors and ask them to complete a survey (e.g., a hard-copy survey on a clipboard or digital survey on an electronic device, such as a tablet or smartphone). If a sufficient number of staff members are available, it is a best practice to have staff ask the survey questions out loud to the respondent and record answers. When staffing is limited, utilizing multiple clipboards, tablets or smartphones, or posting quick response (QR) codes in high-traffic areas around the park are viable alternatives.
Staff members can conduct community surveys in a variety of ways. The first step is to identify your potential respondents based on the questions you are trying to answer. Two sources for participants are email addresses and physical addresses from existing administrative data, such as program registrations or park facility reservations, which enable you to email an electronic survey or post a hard-copy version in the U.S. mail. If your agency has a strong social media following, you can post an electronic survey link to your social media sites or ask any partners to repost the survey on their websites. Unfortunately, both of these approaches are biased toward community members who already have a connection to your park, agency and/or partners. This bias toward already-engaged members of the community limits perspectives and may negate or constrain the views of some community groups.
If possible, the best way to conduct a community survey is to purchase a random sample of addresses, phone numbers and/ or emails from a market research firm that administers your survey to a sample of your community that mirrors its broader demographic characteristics. This approach is the “gold standard,” but it is expensive and often requires collaboration with consultants/statisticians. 4 Recommended Measures to Evaluate Park Use and Quality The System for Observing Play and Active Recreation in Communities (SOPARC) is one of the best tools for recording user counts and activities in park settings. This tool is discussed in the next section, titled “Activity and Recreation,” and additional information on SOPARC is included in the Appendix.
• Adequate time for practicing, observing and then comparing answers with other observers; this ensures all observers are using the same criteria for recording use and will improve repeatability across observers and time • A schedule of dates and times for observation and staff/volunteers to cover all times; ideally, observations should be completed in pairs for safety and reliability • A prepared document for recording observations. This may include: • Pen and paper with table for times and spaces to be observed • A smartphone or tablet application, software or spreadsheet for collecting counts • A dataset for compiling observational data if paper log sheets are used Parks act as social hubs, offering spaces for people to enjoy activities that build bonds. Photo credit: freepik.com 5 Recommended Measures to Evaluate Park Use and Quality Trail and Parking Counters Pneumatic or traffic counters record and tally passing objects. They detect moving objects through tubes or pads placed on a road or trail surface or via magnetic loops. These devices can count vehicles, hikers, horseback riders, bicyclists and boaters. In addition to pneumatic tubes, common commercial counters include those with magnets embedded in trails and roadways (for vehicles and bikes) and passive mounted infrared counters that detect those breaking the infrared beam while passing. This method is limited because it does not account for length of stay, group size or individuals passing counters multiple times in one visit. Counters also are not ideal for open areas where there is more than one confined entrance. Finally, to gauge visitation using car counters more accurately, you must determine a multiplier corresponding to the average number of people in a car. This multiplier can be ascertained by observing how many people, on average, exit a vehicle. These observations to calculate the multiplier should be conducted on specific days to account for variation in park visitation across days of the week and seasons of the year. For more information about multipliers, see below.
Cameras Video, infrared, trail or still cameras also can be used to measure park usage. Cameras work best when placed in sites where a visitor passes a specific location, such as an entrance or trailhead. Cameras installed farther off the ground may be able to capture a broader field of vision, such as a playground. It is important to have signage letting visitors know about the presence of cameras. Depending on the camera used, the processing of images, video and data may be resource intensive.
Cellphone (Mobile) Data There are multiple for-profit companies that purchase and aggregate cellphone location data. While this data is anonymous, it can be quite detailed. For park-usage purposes, the data may include the number of times per day, week or month a cellphone has been in a park space or where in larger parks the cellphone moved. The cost to purchase such data from these companies varies depending on the number of dates, parks or specific details requested. In general, cellphone data can reveal patterns in park visitation over time (daily to annual), but is limited to those visitors who bring their cellphones into the parks and if they have location services turned on for at least one mobile app.
Voluntary Registration Common in larger, nature-based parks, this method requires individuals or groups to sign a registration form during their visit. Registration sites usually are unstaffed and located near trailheads, visitor centers or parking lots. Registration numbers can be linked to actual park and trail use through other methods, such as observations and trail/parking counters. By cross-referencing these data sources, park- and trail-specific multipliers can then be calculated to achieve more accurate park- use data. For example, if a staff member observes 20 individuals using a trail between 10 a.m. and noon and then counts 10 people registered at the trailhead, a “2x multiplier” can be calculated. The multiplier is more likely to be accurate with multiple comparisons across days of the week, times of day and throughout the different seasons.
Activity and Recreation Why Measure A prime directive for park and recreation professionals is to provide space for recreation and play. Measuring exactly what people are doing in your parks and how often they visit will be valuable information to help inform management decisions and future investments (such as sport courts and fields, outdoor exercise equipment and playgrounds). It also provides stakeholders with information about how parks support the general physical health of communities.
What to Measure Some common measures of physical activity include type of park activity, intensity (e.g., sitting vs. running), duration and/or frequency of physical activity, and where in the park activity occurs. How to Measure Self-reported surveys and systematic observations are the two most common ways of measuring recreation and activity. But before conducting surveys or observing visitors, be sure to ask onsite staff (maintenance, law enforcement, visitor services, etc.) for their perceptions about what activities visitors pursue most frequently when they visit a specific park. These personnel are valuable observers of park activity; make sure you involve them.
Surveys Surveys provide a self-reported record of park activity. Staff can administer surveys either in person through intercept surveys or through community surveys, as described previously. Using more than one of these survey methods may help maximize community reach. Be sure to consider the language, cultural and technology barriers that may exist in the community, and then accommodate them appropriately. Common survey questions include: • Type of activities • Duration • Frequency 6 Recommended Measures to Evaluate Park Use and Quality 3. Why do you usually visit ABC Park? (Check up to THREE reasons.) To supervise a child To attend a class (yoga, dance, etc.) To socialize To walk To play a sport (basketball, baseball, etc.) To exercise or train To have a picnic To go to a market, festival, party, etc. To be outdoors To relax or read To walk through on the way to somewhere else 7 Recommended Measures to Evaluate Park Use and Quality FREQUENCY OF PARK USE Please answer the following questions having your usual park in mind.
1 2 3 4 On a usual park visit with your child, how long do you stay in the park? (Note to surveyor: record answers in hours and/or minutes) During the past 30 days, on how many days did you visit this park?
On a usual park visit with your child, do you go...
(Note to survevor: only choose one below) When deciding which park to go to, who usually makes the decision? (Note to surveyor: only choose one below) Answer: Answer: Answer: Answer: 1. With your child alone 2. With your child and other children 3. With your child and other family members 4. With your child and your pet 1. You 2. Other parent/caregiver 3. Child 4. Other 8 Recommended Measures to Evaluate Park Use and Quality Systematic Observation The SOPARC method, described in the previous section, divides a park into play spaces or target areas. Each target area is observed every 15 minutes. Recorded observations of visitors include age group, gender, activity intensity (sedentary, walking - moderate or vigorous), and perceived race/ethnicity (if desired for diversity, equity and inclusion data). Well-trained observers following a strict protocol are critical for the reliability of systematic observation data.
The SOPARC method produces a large amount of numeric data that can be challenging to analyze. Some analysis methods are available using the RAND Corporation SOPARC App or other data-organization tools, such as template Excel spreadsheets available for download. In addition, you may benefit from partnering with a statistician to analyze the data more effectively.
The SOPARC Supplement included in the Appendix of this report provides a case study on the design and implementation of a SOPARC analysis.
More Information About SOPARC NRPA SOPARC Report SOPARC: Reliability and Feasibility Measures User Satisfaction Why Measure Understanding satisfaction with park areas is an effective way to gauge how positively people view your parks and how well those parks are being managed. When users are satisfied with their park experience, they likely will visit the park again in the future and recommend it to others. User satisfaction also is an important indicator of the success of management practices. Positive satisfaction data can be a powerful advocacy tool to share with local decision-makers (such as elected and appointed officials); at the other end of the spectrum, lower levels of satisfaction are essential in determining where efforts for improvement should be focused.
What to Measure User satisfaction measures the positive experiences of visitors related to their park visit.
How to Measure Surveys Satisfaction typically is measured via surveys. It can be quantified holistically via a single question (e.g., “How satisfied were you with your visit today?”) or via a series of questions focused on various parts of a visitor’s experience at a park (e.g., parking, bathrooms, park amenities, etc.). Using one question about overall satisfaction often reduces the length of the survey and allows for easy comparisons of responses over time. If desired, evaluators can ask about users’ satisfaction regarding different aspects of a park. Some of these elements relate to the built environment, or areas designed and managed for human use. (See the Built Environment section for more information.) Be sure to include a “Not applicable” response option in case the user did not engage with an aspect of the park.
4. How satisfied were you following your ABC Park visit regarding each of the following? Extremely Somewhat Not at All Didn’t Use/ Not Applicable Facilities and play equipment for kids Presence of supervision/staff Presence of other kids Availability of open spaces Fountains, restrooms and other services Programs General cleanliness Overall visit 9 Recommended Measures to Evaluate Park Use and Quality Net Promoter Score The Net Promoter Score (NPS) is a common survey question used to gauge the satisfaction, enthusiasm and loyalty a person has toward a specific service. Using a 0 to 10 scale, respondents are asked, “How likely is it that you would recommend [X] to a friend or colleague?” In our case, [X] can be replaced with a specific park or the entire park system. Responses are classified as either “promoters” (score of 9 or 10), “passives” (score of 7 or 8) or “detractors” (score of 0 to 6). The NPS is calculated by subtracting the percentage of detractors from the percentage of promoters. The resulting NPS will give you a sense of your customers’ (or users’) perceptions of your park/park system. The NPS can be collected progressively to evaluate changes in user perceptions over time. For more information about the Net Promoter Score, visit the resource netpromoter.com.
Feedback Kiosks Ideal for high-traffic and staffed parks, these kiosks or terminals can provide instant feedback from visitors at busy sites and provide instantaneous input on user satisfaction. Often displaying a range of smiley faces/emojis from happy to sad, feedback kiosks allow users to provide quick input by selecting the face that best matches their experience at your park. The kiosks should be secured and sheltered from weather when your park closes.
Parks have a unique ability to develop and grow social capital in communities. Photo credit: freepik.com 10 Recommended Measures to Evaluate Park Use and Quality Community and Social Capital Why Measure Social capital is the shared knowledge, norms and trust that develop within a neighborhood. Given their place as pillars of public spaces and their ability to foster community experiences, parks have a unique ability to develop and grow social capital in communities. Parks act as social hubs, offering spaces for people to enjoy activities that build bonds (e.g., socializing, birthday parties, farmers markets, community meetings, sporting events). How a community views a park and its surrounding community can influence how the space is used or not used. Park cleanliness, programming and shared community values can all influence a park’s use and associated benefits.
What to Measure Community and social capital are measured by assessing who is visiting the park together, trust, shared values, diversity and opportunities to learn in the park.
How to Measure Surveys Social capital commonly is assessed through survey questions. Some sample questions include: 5. How much do you agree with the following statements regarding the neighborhood around ABC Park?
Strongly Agree Somewhat Agree Somewhat Disagree Strongly Disagree People get along with each other.
People share the same values.
You can count on adults to ensure children are safe and do not get into trouble.
6. Does ABC Park give adults and/or youth a chance to learn or experience something new? Adults Only Youth Only Both Neither Not Sure 7. Have you or your children met, played and/or interacted with anyone new at ABC Park? Adults Only Youth Only Both Neither Not Sure Not Sure Qualitative Interviews and Focus Groups Social capital also can be evaluated through interviews and focus groups. Interviews can be conducted onsite with park users, in scheduled discussions held in person or via phone/virtually, or via written conversation through texts or emails. Interviews can result in recommendations of other potential participants.
Focus groups are scheduled gatherings of up to 10 participants who have agreed to share their thoughts and feedback on specific topics. These meetings are moderated by a skilled facilitator who asks key questions to gather information from all participants. Providing a small incentive for participation (compensation for their time or providing a meal) and making efforts to reduce barriers (providing childcare) can encourage participation.
For both individual interviews and focus groups, facilitators and stakeholders should collaborate to create a guide that details the key questions. Asking probing questions in response to what participants share and asking others how they feel about what has been said can result in richer insights into the topic. Careful notes or an audio recording (with permission) that is later transcribed will greatly assist in the analysis process. These qualitative approaches often provide rich context on key topics and can be combined with quantitative data to craft an informative and memorable story with the evaluation results. Some sample qualitative questions to measure social capital are: ●• Tell me about who visited the park with you during your most recent visit. Why did you decide to go to the park together?
●• How do community members interact with each other while in the park?
●• Provide examples of shared values between park users.
●• How have community members contributed to your feelings of safety at the park?
●• Describe what your child has learned or newly experienced at the park recently.
●• Tell me about a time you or your child met somebody new at the park.
11 Recommended Measures to Evaluate Park Use and Quality Built Environment Why Measure Most local park areas are designed and managed for human use. The built environment — spaces designed by people for human use — can play a significant role in how people interact with a park and the surrounding community. The built environment may include sidewalk connectivity, lighting, public restrooms, cleanliness, maintenance, and other aspects or infrastructure. Understanding the perceptions of these human-centric design features is helpful to assessing overall park quality.
What to Measure To evaluate the built environment, questions should address the accessibility, safety and quality of the park. Elements to measure may include sidewalk connectivity and accessibility, marked crosswalks, public transportation proximity and speed limit. Some other non-functional elements in the built environment that may impact park use or experience include litter and broken or boarded windows.
How to Measure Surveys Community and park visitor perceptions of the built environment are most easily collected through surveys. Sample question 4 on page 9 illustrates one way that satisfaction questions about the built environment may be incorporated into your satisfaction survey.
Sample question 8 illustrates an alternative way to ask visitors about a park’s built environment.
8. Is there anything that makes it difficult to visit ABC Park? (Check all that apply.) Sidewalk conditions Safety concerns related to crime/violence Traffic Lack of parking Nothing Other 12 Recommended Measures to Evaluate Park Use and Quality Perceived Safety Why Measure A person’s perception of park safety is directly related to when, how often and what people do when they visit park areas. It is important to evaluate perceived safety to ensure residents feel safe accessing their parks; lack of safety is a common barrier to park use, and evaluation results can help identify specific perceptions of safety that can be addressed. Though objective crime (i.e., actual reports of crime to the police) is associated with park use, perceptions of crime continually show a higher association with park-use behavior than actual crime statistics.
What to Measure Perceptions of safety can be useful for understanding attitudes toward parks and changes in park use. Importantly, perceived safety includes perceptions of safety while in a park, barriers to using a park and its amenities, and a sense of safety accessing a park from the surrounding neighborhood.
How to Measure Surveys Surveys can measure perceived safety by asking community members and park users directly about their perceptions of safety.
9. How much do you agree with the following statements regarding the neighborhood around ABC Park?
Strongly Agree Somewhat Agree Somewhat Disagree Strongly Disagree Walkers and bikers can be easily seen by people in their homes.
I see and speak to other people when I am walking.
The crime rate makes it unsafe to go on walks during the day.
The crime rate makes it unsafe to go on walks at night.
Not Sure 13 Recommended Measures to Evaluate Park Use and Quality Interviews/Focus Groups Similar questions can be used for interviews and focus groups to gather more in-depth information. Often, combining survey results with more in-depth, open-ended questions in a one-to-one discussion or in a group can pinpoint exactly what action may be necessary. Examples include: ●• Please describe your feelings of safety walking from home to the park.
●• Tell me about a time you felt unsafe while accessing or being in the park.
●• Tell me about a time you felt safe, and supported by the community, while accessing or being in the park.
Economic Impact Why Measure While property values are influenced by a range of factors, research has shown that close proximity to park and recreation areas contributes to increases in property values, especially in areas where green space is limited. For local and state governments, higher property values equate to higher revenue generation via property taxes and/or real estate transfer tax revenues. Quantifying and communicating this economic impact to government officials could be powerful and persuasive in encouraging further investment in parks as economic drivers. While rising property values is generally perceived as a positive development, gentrification (the displacement of lower-income individuals from their communities because of wealthier people moving in) is a concern. Monitoring tax value assessment fluctuations also can clarify longer-term community impacts.
What to Measure Property values based on tax assessment value.
How to Measure Mapping/Databases Tax assessments are publicly available information usually accessible via a local government’s tax assessor (or related office). Many counties and municipalities provide access to this public data online via a mapping platform or database. Data in these systems may be exportable directly from the mapping platform/ database or can be requested from the local government. Once the tax assessment information is acquired, property values (residential and commercial) in proximity to park areas can be analyzed using Geographic Information Systems (GIS) software. Changes in property values for park-adjacent properties can provide an indicator of how parks have an impact on the economy. This type of analysis requires beginner to intermediate knowledge and a basic understanding of GIS data management tools. This is a sample residential property tax assessment of ABC Park. Photo credit: William Beam 14 Recommended Measures to Evaluate Park Use and Quality Evaluation can help you monitor and manage some of your community’s most precious resources — your local park areas. Understanding park use and quality will help to inform and improve your operations and potentially justify further investment in these essential public spaces. This resource is a helpful starting point for identifying what kinds of questions you might want to include in your own park evaluation. As you continue on this journey, NRPA encourages you to engage with your local community from the beginning and partner with local colleges and universities to help hone your plan for evaluation. Additional resources are available on NRPA’s Evaluation homepage: nrpa.org/Evaluation.
Acknowledgements Thank you to the following individuals for their contributions to this report: North Carolina State University Kat Deutsch J. Aaron Hipp Will Beam National Recreation and Park Association Austin Barrett Dianne Palladino Kevin Roth Kevin Brady Lauren Redmore Danielle Doll Lindsay Collins Vitisia Paynich Meagan Yee Ivy McCormick Conclusion User satisfaction measures the positive experiences of visitors related to their park visit. Photo credit: freepik.com 15 Recommended Measures to Evaluate Park Use and Quality About the National Recreation and Park Association The National Recreation and Park Association (NRPA) is the leading not-for-profit organization dedicated to building strong, vibrant and resilient communities through the power of parks and recreation. With more than 60,000 members, NRPA advances this vision by investing in and championing the work of park and recreation professionals and advocates — the catalysts for positive change in service of equity, climate-readiness, and overall health and well-being.
NRPA brings strength to our message by partnering with like-minded organizations, including those in the federal government, nonprofits and commercial enterprises. Funded through dues, grants, registrations and charitable contributions, NRPA produces research, education and policy initiatives for our members that ultimately enrich the communities they serve.
NRPA places immense importance on evidence-based decision making to raise the status of Parks and Recreation. We use robust research and evaluation methods to help park and recreation programs measure progress toward stated goals, strive for continuous improvement and to advocate for parks and recreation as an essential community service. We also work with subject matter experts, consultants, and the academic community to develop tools, training and other resources that help park and recreation professionals to perform cost-effective, efficient and sustainable evaluation in the field. Learn more at nrpa.org/evaluation.
Measuring park use determines the value of investment by showing the public and elected officials key metrics regarding community park use. Photo credit: freepik.com APPENDIX: SOPARC Supplement — Case Study Researchers from North Carolina State University (NCSU) conducted an evaluation of the 2019 NRPA Parks Build Community project at ABC Park Park in Baltimore. As part of their evaluation, NCSU researchers used the System for Observing Play and Active Recreation in Communities (SOPARC) method to measure park use and activity engagement. Below is an overview of their use of SOPARC: Steps Taken 16 Recommended Measures to Evaluate Park Use and Quality 1. Divided the park space into visible target areas (see example below) 2. Established observation times over the study period; These represented each day of the week and all time periods of interest; Controlled for seasonal events, such as school holidays and hot/cold weather by keeping observation dates relatively consistent 3. Trained observers and practiced observations to ensure consistency and reduce observation subjectivity; ABC Park observation training involved observers confirming answers with each other to establish agreement 4. Completed one SOPARC form for each scan — one for each target area each time it was scanned; For the ABC Park evaluation, the team scanned four times per hour over eight target areas, resulting in 32 completed forms per hour 5. After the dataset was complete, researchers conducted appropriate descriptive analyses, such as frequencies and percentages (e.g., 40 percent of baseball field users were vigorously active) and averages (e.g., 40 percent of baseball field users were vigorously active) and averages (e.g., in the spring, an average of 6.7 players were active on the basketball court) This is a sample park layout. Photo credit: Baltimore County Department of Recreation and Parks 17 Recommended Measures to Evaluate Park Use and Quality Scanning Process The systematic observation, or momentary scan, is a left-to-right visual scan of the target areas. Observers use a countdown and then scan. For example, an observer will stand at the corner of a basketball court, countdown “three, two, one,” then scan the court area left to right, noting the activity intensity of each person playing at the end of the countdown. Activity intensity is what the person(s) are doing at that moment. That is, if someone was playing basketball and sprinting down the court, but they were standing still under the basket for a rebound at that exact moment of the countdown and scan, that person would be recorded as sedentary. Therefore, momentary scans should be captured two to four times per hour to provide a broader understanding of total use of space.
Schedule Researchers included four scans per hour of each space and incorporated a scan for each hour of the day, 9 a.m. to dusk, seven days of the week. For example, this schedule may have involved scanning at 9 a.m. and 10 a.m. on a Tuesday, then 4 p.m. and 5 p.m. on a Thursday. The schedule was repeated on the weekend because of different use patterns for school/ work days versus on the weekend. Together, the collected data included systematic observations from each daylight hour across a week and weekend during at least one season of the year.
Supplies Needed • Pens/Pencils • Clipboards • Watch/Phone for time • Printed SOPARC forms (see below) • Computer, spreadsheet, database for SOPARC analysis Example SOPARC Form |
12556 | https://arc.aiaa.org/doi/10.2514/5.9781624107252.0613.0640 | Propeller Aircraft Performance | AIAA Education Series
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12557 | https://www.spanishdict.com/translate/mientras | Mientras | Spanish to English Translation - SpanishDictionary.com
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mientras(myehn - trahs)
A conjunction is a word that connects words, phrases, clauses, or sentences (e.g., The cat and the dog slept.).
conjunction
1.(at the same time)
a.while
Lavó los platos mientras yo dormía la siesta.He did the dishes while I took a nap.
2.(during the time that)
a.as long as(followed by verb in subjunctive)
Mientras trabaje aquí, nunca podré tomarme unas vacaciones en condiciones.As long as I work here, I'll never manage to take a proper vacation.
3.(if)
a.as long as(followed by verb in subjunctive)
Mientras termines los deberes a tiempo, me da igual que escuches música o no.As long as you finish your homework on time, I don't mind if you listen to music.
4.(in contrast with; used with "que")
a.whereas
Mientras que a mi hermana le encanta leer, a su esposo le encanta trabajar en el jardín.Whereas my sister loves to read, her husband loves to garden.
b.while
Yo soy vegetariana, mientras que a mi marido le encanta la carne.I'm vegetarian, while my husband loves meat.
An adverb is a word that describes a verb, an adjective, or other adverbs (e.g., to run quickly, very tired).
adverb
5.(at the same time)
a.meanwhile
Tu hermana va a recoger su cuarto. Mientras, tú puedes quitar el polvo del salón.Your sister is going to clean up her room. Meanwhile, you can dust the living room.
b.in the meantime
Saca al perro; mientras, puedo trapear el piso de la cocina.Take the dog out. I can mop the kitchen floor in the meantime.
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while (203K)
as (54K)
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Algunos efectos secundarios pueden ocurrir mientras toma Olmecip (Omesartan Medoxomil).Some side effects may occur while taking Olmecip (Omesartan Medoxomil).
Mantener su privacidad mientras usa DirecTV Now es extremadamente importante.Maintaining your privacy while using DirecTV Now is extremely important.
Algunas mascotas pueden experimentar efectos secundarios mientras toman Dolocarp (Carprofen).Some pets may experience side effects while taking Dolocarp (Carprofen).
Conoce dos lugares importantes mientras visita la ciudad de Barcelona.Meet two important places while visiting the city of Barcelona.
Puede ver estas anotaciones mientras lee el libro en línea.You can view these annotations while reading the book online.
El único deporte que puedes jugar mientras tomas una siesta.The only sport you can play while taking a nap.
Su pierna está literalmente muriendo mientras nos sentamos aquí recordando.His leg is literally dying while we sit here reminiscing.
Ahora él tiene que mirar mientras Marcus recoge sus ganancias.Now he has to watch while Marcus collects his winnings.
A su regreso, relájese mientras toma un Puerto de Honor.On your return, relax while taking a Port of Honor.
Hable con su médico sobre beber mientras toma un antidepresivo.Talk to your doctor about drinking while taking an antidepressant.
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Phrases
mientras tantomeanwhile
mientras quewhereas
hablo mientras comoI speak and eat at the same time
un rato mientras espero a la peluquerafor a while while I wait for the hairdresser
te estoy siguiendo mientras bailamos el tangoI'm following you as we dance tango
mientras estábamos allíwhile we were there
la discusión comenzó mientras el profesor daba una clase sobre deportesthe argument started while the teacher was teaching a class on sports
mientras yowhile I
mientras por competir con tu cabellonow while to match your hair
mientras conduces, debes poner las dos manos en el volanteyou have to put both hands on the steering wheel while you're driving
te sugiero que pongas música mientras lavas los platosI suggest you listen to music while you wash the dishes
mientras se cocinan las patatas, batir los huevoswhile the potatoes are cooking, whisk the eggs
mientras hablas por teléfono celular, no es buena ideawhen you're on the phone, it's not a good idea to
no habrá verdadera paz mientras que haya injusticia socialThere will be no real peace as long as there is social injustice
por mientrasmeanwhile
yo leo mientras comoI read while I eat
yo conducía el auto mientrasI was driving the car while
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12558 | https://www.reddit.com/r/askmath/comments/owucsc/intervals_in_which_the_function_y1x_is_decreasing/ | Intervals in which the function y=-1/x is decreasing or decreasing. : r/askmath
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AstrophysicsStudent
Intervals in which the function y=-1/x is decreasing or decreasing.
Functions
I was asked to find the intervals in which the function y=-1/x is decreasing or increasing. Graph
I can see that it's increasing from (- ∞, 0), but the book states that it is decreasing from (0, ∞ )
That doesn't seem to right to me because the graph starts of very, very negative, and it gets closer to zero. If a negative number gets closer to 0, that's an increase, so shouldn't the graph also be increasing from (0, ∞)? Did the book get it wrong?
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12559 | https://artofproblemsolving.com/wiki/index.php/Double_angle_identities?srsltid=AfmBOorXnWxL6g0usSQ7gxEizdgLzBFyGzzh4jbQHXIiFcZBbZoSTrXy | Art of Problem Solving
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Double angle identities
The trigonometric double-angle identities are easily derived from the angle addition formulas by just letting . Doing so yields:
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12560 | https://www.geogebra.org/m/NQXTcNTt | Area of Annulus – GeoGebra
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Showing area of annulus between two circles. Like a math contest problem one might see.
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12561 | https://www.slideshare.net/slideshow/velocity-triangle-for-moving-blade-of-an-impulse-turbine/86340504 | Velocity Triangle for Moving Blade of an impulse Turbine | PPTX | Physics | Science
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Velocity Triangle for Moving Blade of an impulse Turbine
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Impulse turbines use steam jets to transfer momentum to rotating blades, while reaction turbines use the pressure of steam flowing over stationary and moving blades to rotate the shaft. Both use velocity triangles to analyze steam flow at the inlet and outlet of curved blades. The power produced depends on the change in steam whirl velocity as it flows through the blades. Reaction turbines experience axial thrust from the change in steam flow velocity from inlet to outlet.
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Velocity Triangle for Moving Blade of an impulse Turbine
Velocity triangle forMoving Blade of an impulse turbine 1. Consider a steam jet entering a curved blade after leaving the nozzle at C. 2. Now let the jet glides over the inside surface and leaves the blade at D, as shown in fig. 3. Now let us draw the velocity triangles at inlet and outlet tips of the moving blade, as shown in fig. 4. The inlet triangle of velocities represented by AEC and outlet triangle by AFD. 5. The relations between inlet and outlet velocity triangle is Vr= Vr1. Fig.: Velocity triangle of an impulse turbine
Velocity triangle forMoving Blade of an impulse turbine Let Vb = Liner velocity of the moving blade(AB) V= Absolute velocity of steam entering the moving blade(AC), Vr= Relative velocity of jet to the moving blade(BC). It is the vectorial difference between Vb and V. Vf= Velocity of flow at entrance of the moving blade. It is the vertical component of V. Vw=Velocity of whirl at entrance of the moving blade. It is horizontal component of V. θ= Angle which the relative velocity of jet to the moving blade(Vr) makes with the direction of motion of the blade. α= Angle with the direction of motion of the blade at which the jet enterns the blade. V1, Vr1, Vf1, Vw1, β, ϕ = Corresponding values at exit of the moving blade. Fig.: Velocity triangle of an impulse turbine
Power produced byan Impulse Turbine Consider an impulse turbine working under the action of a steam jet. Let, m = Mass of steam flowing through the turbine in Kg./s Now, Change in the velocity of whirl in m/s = Vw+ Vw1 [Vw – (– Vw1 ), when Vw1 is negative] We know that according to the Newton’s second law of motion, force in the direction of motion of the blades Fx = Mass of steam flowing per second × Change in the velocity of whirl = m(Vw+ Vw1) and work done in the direction of motion of the blades = Force × distance = m(Vw+ Vw1)× Vb N-m/s So, Power produced by the turbine P= m(Vw+ Vw1)× Vb watts. [ 1 N-m/s = 1 watt]
Power produced byan Impulse Turbine Similarly, we can find out the axial thrust on the wheel is due to the difference of velocities of flow at inlet and outlet. So, axial thrust on the wheel FY = Mass of steam flowing per second × Change in the velocity of flow = m(Vf - Vf1) The value of Vw1 is taken as negative because of the opposite direction of Vw with respect to the blade motion. If Vw1 is in the same direction with respect to the blade motion, then Vw1 is taken as positive. The ratio of Vr1 to Vr is known as blade velocity coefficient or friction factor, denoted by K So, K =
Reaction Turbine 1. Ina reaction turbine, the steam enters the wheel under pressure and flows over the blades. 2. The steam, while gliding, propels the blades and make them to move. 3. As a matter of fact, the turbine runner is rotated by the reactive force of steam jets. 4. It has the following main components: i. Casing ii. Guide mechanism iii. Runner iv. Draft tube
1. Casing 1. Itis an air-tight metallic case. 2. In it the steam from the boiler, under a high pressure and temperature, is distributed around the fixed blades(guide mechanism). 3. It is designed in such a way that the steam enters the fixed blades with a uniform velocity.
2. Guide mechanism Itis a mechanism, made up with the help of guide blades, in the form of a wheel and generally fixed to the casing. It is designed properly in order to: 1. Allow the steam to enter the runner without shock. 2. Allow the required quantity of steam to enter the turbine.
3.Runner 1. It isconsists of runner blades fixed to a shaft or rings. 2. The blades, fixed to the runner, are properly designed in order to allow the steam to enter and leave the runner without shock. 3. The surface of the turbine runner is made very smooth to minimise the frictional losses. 4. It is, generally, cast in one piece but sometimes made up of separate steel plates welded together.
4.Draft tube The steam,after passing through the runner, flows into the condenser through a tube called draft tube.
Velocity triangle formoving blades of a reaction turbine 1. Consider steam, in the form of a jet, entering the curved blade at C. 2. Let the jet glides over the inside surface and leaves the blade at D as shown in fig. 3. Now let us draw the velocity triangles at inlet and outlet tips of the moving blade as shown in fig. Fig.: Velocity triangle for a reaction turbine
Velocity triangle formoving blades of a reaction turbine Let Vb = Liner velocity of the moving blade(BA) V= Absolute velocity of steam entering the moving blade(BC), Vr = Relative velocity of jet to the moving blade(AC). It is the vectorial difference between Vb and V. Vf = Velocity of flow at entrance of the moving blade EC. It is the vertical component of V. Vw =Velocity of whirl at entrance of the moving blade BE. It is horizontal component of V. Θ = Angle which the relative velocity of jet to the moving blade(Vr) makes with the direction of motion of the blade. α= Angle with the direction of motion of the blade at which the jet enters the blade. V1, Vr1, Vf1, Vw1, β, ϕ = Corresponding values at exit of the moving blade. Fig.: Velocity triangle for a reaction turbine
Power produced bya Reaction Turbine Consider a reaction turbine working under the action of a steam jet. Let, m= Mass of steam flowing through the turbine in Kg./s, Change in the velocity of whirl in m/s = Vw+ Vw1 [Vw – (– Vw1 ), when Vw1 is negative] We know that according to the Newton’s second law of motion, force in the direction of motion of the blades Fx = Mass of steam flowing per second × Change in the velocity of whirl = m(Vw+ Vw1) and work done in the direction of motion of the blades = Force × distance = m(Vw+ Vw1)× Vb N-m/s So, Power produced by the turbine P= m(Vw+ Vw1)× Vb watts. [ 1 N-m/s = 1 watt]
Power produced bya Reaction Turbine Similarly, we can find out the axial thrust on the wheel is due to the difference of velocities of flow at inlet and outlet. So, axial thrust on the wheel FY = Mass of steam flowing per second × Change in the velocity of flow = m(Vf - Vf1) The value of Vw1 is taken as negative because of the opposite direction of Vw with respect to the blade motion. If Vw1 is in the same direction with respect to the blade motion, then Vw1 is taken as positive. The ratio of Vr1 to Vr is known as blade velocity coefficient or friction factor, denoted by K So, K =
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12562 | https://arxiv.org/pdf/2009.05495 | arXiv:2009.05495v3 [math.CO] 31 Mar 2021
Every graph contains a linearly sized induced subgraph with all degrees odd
Asaf Ferber ∗ Michael Krivelevich †
April 2, 2021
Abstract
We prove that every graph G on n vertices with no isolated vertices contains an induced subgraph of size at least n/ 10000 with all degrees odd. This solves an old and well-known conjecture in graph theory.
1 Introduction
We start with recalling a classical theorem of Gallai (see , Problem 5.17 for a proof):
Theorem 1 (Gallai’s Theorem) . Let G be any graph. 1. There exists a partition V (G) = V1 ∪ V2 such that both graphs G[V1] and G[V2] have all their degrees even. 2. There exists a partition V (G) = Vo ∪ Ve such that the graph G[Ve] has all its degrees even, and the graph G[Vo] has all its degrees odd.
It follows immediately from 1 . that every graph G has an induced subgraph of size at least |V (G)|/2with all its degrees even. This is easily seen to be tight by taking G to be a path. It is natural to ask whether we can derive analogous results for induced subgraphs with all degrees odd. Some caution is required here — an isolated vertex can never be a part of a subgraph with all degrees odd. Thus we restrict our attention to graphs of positive minimum degree. Let us introduce a relevant notation: given a graph G = ( V, E ), we define
fo(G) = max {| V0| : G[V0] has all degrees odd. },
and set
fo(n) = min {fo(G) | G is a graph on n vertices with δ(G) ≥ 1}.
The following is a very well known conjecture, aptly described by Caro already more than a quarter century ago as “part of the graph theory folklore”:
∗
Department of Mathematics, University of California, Irvine. Email:asaff@uci.edu. Research supported in part by NSF grants DMS-1954395 and DMS-1953799.
†
School of Mathematical Sciences, Tel Aviv University, Tel Aviv 6997801, Israel. Email: krivelev@tauex.tau.ac.il. Research supported in part by USA–Israel BSF grant 2018267 and by ISF grant 1261/17.
1Conjecture 2. There exists a constant c > 0 such that for every n ∈ N we have fo(n) ≥ cn .
Caro himself proved that fo(n) = Ω( √n), resolving a question of Alon who asked whether fo(n)is polynomial in n. The current best bound, due to Scott , is fo(n) = Ω( n/ log n). There have been numerous variants and partial results about the conjecture, we will not cover them here. Our main result establishes Conjecture 2 with c = 0 .0001.
Theorem 3. Every graph G on n vertices with δ(G) ≥ 1 satisfies: fo(G) ≥ cn for c = 1
10000
.
With some effort/more accurate calculations the constant can be improved but probably to a value which is still quite far from the optimal one; we decided not to invest a substantial effort in its opti-mization and just chose some constants that work. A relevant parameter was studied by Scott : given a graph G with no isolated vertices, let t(G) be the minimal k for which there exists a vertex cover of G with k sets, each spanning an induced graph with all degrees odd. Letting
t(n) = min {t(G) | G is a graph on n vertices with δ(G) ≥ 1},
Scott proved (Theorem 4 in ) that Ω(log n) = t(n) = O(log 2 n).
As indicated by Scott already, showing that fo(n) is linear in n proves the following:
Corollary 4. t(n) = Θ(log n).
For completeness, we outline its proof here.
Proof. Let G be a graph on n vertices with δ(G) ≥ 1. By a repeated use of Theorem 3, we can find disjoint sets V1, . . . , V t such that: 1. Vi ⊆ V (G) \
(⋃i−1
j=1
Vj
)
, and 2. all the degrees in G[Vi] are odd, and 3. letting ni be the number of non-isolated vertices in G
[
V (G) \
(⋃i−1
j=1
Vj
)]
, we have that |Vi| ≥
ni/10000. We continue the above process as long as ni > 0. Clearly, the process terminates after t = O(log n)steps. Moreover, letting U = V (G) \ (⋃ ti=1 Vi
), we have that U is an independent set in G. Finally, as shown in the proof of Theorem 4 in , every independent set in such G can be covered by O(log n)odd graphs. This proves that t(n) = O(log n). To show a lower bound, we can use the following example due to Scott : assume n is of the form
n = s + (s
2
). Let the vertex set of G be composed of two disjoint sets: A of size s associated with [ s], and
B of size (s
2
) associated with ([s]2
). The graph G is bipartite with the edges defined as follows: a pair (i, j ) ∈ B is connected to both i, j ∈ A. Observe that if U ⊂ V (G) spans a subgraph of G with all degrees odd and containing ( i, j ) ∈ B, then U contains exactly one of i, j ∈ A. Hence if U = ( U1, . . . , U t) forms a cover of V (G) with subsets spanning odd subgraphs, then U separates the set A, and the minimum size of such a separating family is easily shown to be asymptotic to log 2 s = Ω(log 2 n).
22 Auxiliary results
The following lemma appears as Theorem 2.1 in . For the convenience of the reader we provide its simple proof.
Lemma 2.1. For every graph G we have that fo(G) ≥ ∆( G)
2
.
Proof. Let v ∈ V (G) be a vertex with dG(v) = ∆( G), and let U ⊆ NG(v) be an odd subset of size
|U | ≥ ∆( G) − 1. Apply Gallai’s Theorem to G[U ] to obtain a partition U = Ve ∪ Vo, and observe that Vo
must be of an even size (so in particular, |Ve| is odd). If |Vo| ≥ ∆( G)/2, then we are done. Otherwise, define V ∗ = {v} ∪ Ve, and observe that G[V ∗] has all its degrees odd and is of size at least ∆( G)/2 as required.
The next lemma appears as Theorem 1 in , and again, for the sake of completeness, we give its proof here.
Lemma 2.2. For every graph G with δ(G) ≥ 1 we have that fo(G) ≥ α(G)
2
.
Proof. Let I ⊆ V (G) be a largest independent set in G. Since δ(G) ≥ 1, every u ∈ I has at least one neighbor in V (G) \ I.Let D ⊆ V (G) \ I be a smallest subset dominating all vertices in I. Observe that by the minimality of D for every w ∈ D there exists some uw ∈ I such that NG(uw) ∩ D = {w}; let ID := {uw | w ∈ D}.Let D′ ⊆ D be a subset of D chosen uniformly at random, and let I0 ⊆ I \ ID be a subset consisting of all elements u ∈ I \ ID that have an odd degree into D′.Let
I1 = {uw ∈ ID | w ∈ D′ and w′ has even degree in D′ ∪ I0},
and observe that G[I0 ∪ I1 ∪ D′] is an induced subgraph of G with all its degrees odd. Finally, since Pr[ u ∈ I0] = 1
2
, by linearity of expectation we have that
E[|I0 ∪ I1 ∪ D′|] = E[|I0|] + E[|I1|] + E[|D′|] ≥ |I| − | D|
2 + |D|
2 = α(G)
2 .
Hence there exists a set D′ for which
|I0| + |I1| + |D′| ≥ α(G)
2 ,
as desired.
Next we argue that if G contains a semi-induced matching with “nice” expansion properties, then it also has a large induced subgraph with all degrees odd.
Lemma 2.3. Let G be a graph and let M be a matching in G with parts U and W , where every vertex
w ∈ W has only one neighbor in G between the vertices covered by M . Assume that |NG(U ) \ (W ∪
NG(W )) | ≥ k. Then fo(G) ≥ k
4
.
Proof. Let X = NG(U ) \ (W ∪ NG(W )) and recall that |X| ≥ k. Let U0 be a random subset of U chosen according to the uniform distribution, and let
X0 = {x ∈ X : dG(x, U 0) is odd }.
3Since E[|X0|] = |X|/2, it follows that there exists an outcome U0 ⊆ U for which |X0| ≥ | X|/2 ≥ k/ 2. Fix such U0.Next, apply Gallai’s theorem to G[X0] to find a subset X1 ⊆ X0 with |X1| ≥ | X0|/2 ≥ k/ 4 and all degrees in G[X1] even. Finally, for every u ∈ U0 with dG(u, X 1) even, add an edge of M containing u.Clearly, the obtained graph G1 has size at least |X1| ≥ | X|/4 ≥ k/ 4, and all its degrees are odd. This completes the proof.
The following simple lemma will be used several times below.
Lemma 2.4. Let G be a bipartite graph with parts A, B such that d(b) > 0 for every b ∈ B. Assume that |A| ≤ α|B| for some 0 < α ≤ 1. Then there is an edge ab ∈ E(G) with d(a) ≥ d(b)
α
.Proof. We have:
∑
ab ∈E(G)
( 1
d(b) − 1
d(a)
)
= ∑
b∈B
d(b) · 1
d(b) − ∑
a∈A,d (a)>0
d(a) · 1
d(a) ≥ | B| − | A| ≥ (1 − α)|B| .
Hence there is b ∈ B with ∑
a∈NG(b)
( 1
d(b) − 1
d(a)
)
≥ 1 − α .
It follows that there is a neighbor a of b for which 1
d(b)
− 1
d(a)
≥ (1 − α) 1
d(b)
, implying d(a) ≥ d(b)
α
as desired.
For a graph G = ( V, E ) and β > 0, define
L = L(G; β) = {v ∈ V : ∃u ∈ V, uv ∈ E(G), |N (u) \ N (v)| ≥ β|N (u) ∪ N (v)|} .
We say that for v ∈ L, an edge uv as above witnesses v ∈ L.Set
β = 1
20 ,δ = 1
14 ,ǫ = 1
10 .
The next lemma is a key part in the proof of our main theorem. We did not really pursue the goal of optimizing the constants in its statement.
Lemma 2.5. Let G = ( V, E ) be a graph on |V | = n vertices with δ(G) > 0 and |L(G; β)| ≤ δn . Then
fo(G) ≥ n/ 61 .Proof. Define
V1 = {v ∈ V \ L : d(v, L ) ≥ ǫd (v)} ,V2 = V \ (V1 ∪ L).
4Suppose first that |V1| ≥ 12 |L|. Observe that d(v, L ) ≥ ǫd (v) > 0 by the assumption δ(G) > 0. By Lemma 2.4 there exists uv ∈ E(G) with v ∈ V1 and u ∈ L such that d(u, V 1) ≥ 12 d(v, L ) ≥ 12 ǫd (v). Therefore we have that
|N (u) \ N (v)| ≥ d(u) − d(v) ≥ 12 ǫ − 1
12 ǫ + 1 (d(u) + d(v)) > β |N (u) ∪ N (v)|,
so in particular v should also be in L with uv witnessing it — a contradiction. We conclude that
|V1| < 12 |L| ≤ 12 δn ,
and therefore |V2| ≥ (1 − δ − 12 δ)n = n
14
.Let v 6 ∈ L. Take an edge uv ∈ E(G). Then max {1, d (u) − d(v)} ≤ | N (u) \ N (v)| ≤ β|N (u) ∪ N (v)| ≤ β(d(u) + d(v)) ,
yielding:
d(u) ≤ 1 + β
1 − β d(v) ,
and
β
( 1 + β
1 − β + 1
)
d(v) ≥ 1 .
This shows that every vertex v ∈ V \ L has degree d(v) ≥ ⌈ 1−β
2β
⌉ = 10. Let now uv ∈ E(G) with u, v 6 ∈ L. Then
|N (u) \ N (v)|, |N (v) \ N (u)| ≤ β|N (u) ∪ N (v)| ,
and hence
|N (u) ∩ N (v)| ≥ (1 − 2β)|N (u) ∪ N (v)|. (1) Since
|N (u) ∩ N (v)| ≤ min {d(u), d (v)} and |N (u) ∪ N (v)| ≥ max {d(u), d (v)},
it follows that (1 − 2β)d(u) ≤ d(v) ≤ d(u)
1 − 2β < (1 + 3 β)d(u). (2) Now, for all v / ∈ L define R(v) = ( {v} ∪ N (v)) \ L. Notice that as d(v) ≥ 10 we have |R(v)| ≥
(1 − ǫ)d(v) + 1 ≥ 10 for v ∈ V2. Suppose that R(u) ∩ R(v) 6 = ∅ for some u 6 = v where v ∈ V2 (note that it might be that u ∈ V1). Then for w ∈ R(v) ∩ R(u), by (1) we have
|N (u) ∩ N (w)| ≥ (1 − 2β)|N (u) ∪ N (w)| and |N (v) ∩ N (w)| ≥ (1 − 2β)|N (v) ∪ N (w)|,
which implies, by the identity |A△B| = |A ∪ B| − | A ∩ B|, that
|N (u)△N (w)| ≤ 2β
1 − 2β |N (u) ∩ N (w)| < 3β|N (u) ∩ N (w)|
and
|N (v)△N (w)| ≤ 2β
1 − 2β |N (v) ∩ N (w)| < 3β|N (v) ∩ N (w)| .
5Therefore, we have
|N (u) ∩ N (v)| ≥ | N (u) ∩ N (v) ∩ N (w)| (3)
≥ | N (u) ∪ N (v)| − | N (u)△N (w)| − | N (v)△N (w)|
|N (u) ∪ N (v)| − 6β max {d(u), d (v)}≥ (1 − 6β)|N (u) ∪ N (v)|.
Since v ∈ V2 we conclude that
|R(u) ∩ R(v)| ≥ | N (u) ∩ N (v)| − ǫd (v) (4)
(1 − 6β − ǫ) |N (u) ∪ N (v)|≥ (1 − 6β − ǫ) |N (u) ∪ R(v)|
= (1 − 8β) |N (u) ∪ R(v)| .
Next, let R1, . . . , R k be a maximal by inclusion collection of non-intersecting sets R(vi), v i ∈ V2. Due to maximality, every v ∈ V2 has its set R(v) intersecting with at least one of the Ri’s; moreover, the above argument shows that it can intersect only one such set. Define now
Ui = {v / ∈ L : R(v) ∩ Ri 6 = ∅} .
Trivially we have Ri ⊆ Ui. Also, V2 ⊆ ⋃ki=1 Ui due to the maximality of the family R1, . . . , R k.We wish to show that all Ui are disjoint and that there are no edges in between different Ui’s. (This will add to the above stated fact that the family of Ui’s forms a cover of V2.) To prove the latter claim, suppose that there exists an edge w1w2 ∈ E(G) for some w1 ∈ Ui, w 2 ∈ Uj ,1 ≤ i 6 = j ≤ k. We will obtain a contradiction by showing that Ri ∩ Rj 6 = ∅. Since both w1, w 2 /∈ L, by (1) and (2) we conclude that
|N (w1) ∩ N (w2)| ≥ (1 − 2β)|N (w1) ∪ N (w2)| and |N (w1)| ∈ (1 ± 3β)|N (w2)| .
Moreover, by (3) we have
|N (w1) ∩ N (vi)| > (1 − 6β)|N (w1) ∪ N (vi)|, and |N (w2) ∩ N (vj )| ≥ (1 − 6β)|N (w2) ∪ N (vj )|.
Since vi, v j ∈ V2, the above inequalities imply that
|N (w1) ∩ Ri| > (1 − 6β − ǫ)|N (w1) ∪ Ri|, and |N (w2) ∩ Rj | > (1 − 6β − ǫ)|N (w2) ∪ Rj |.
It follows that
|N (w1) ∩ Ri| > (1 − 6β − ǫ)|N (w1)|
and
|N (w2) ∩ Rj | > (1 − 6β − ǫ)|N (w2)| ,
and recalling that
|N (w1) ∩ N (w2)| ≥ (1 − 2β)|N (w1) ∪ N (w2)| ,
we conclude that Ri ∩ Rj 6 = ∅ — a contradiction. In a similar way we can show that Ui ∩ Uj = ∅.Next, suppose that |Ui| ≥ (1 + 19 β)|Ri|. Then by looking at the auxiliary bipartite graph between
Ri and Ui (v ∈ Ri, u ∈ Ui are connected by an edge if uv ∈ E(G)) and by applying Lemma 2.4 to this 6graph we derive that there are v ∈ Ri, u ∈ Ui with d(v) ≥ (1 + 19 β)d(u, R i ). Since uv ∈ E(G) and both
u, v 6 ∈ L, it follows that
d(v) < (1 + 3 β)d(u) .
Moreover, since u ∈ Ui we have:
d(u, R i) ≥ (1 − 8β)d(u) .
All in all, since d(v) ≥ (1 + 19 β)d(u, R i ) we conclude that (1 + 3 β)d(u) > d (v) ≥ (1 + 19 β)d(v, R i ) > (1 + 19 β)(1 − 8β)d(u) > (1 + 3 β)d(u) ,
a contradiction. Therefore, we can assume that |Ui| ≤ (1 + 19 β)|Ri| for all 1 ≤ i ≤ k. Looking at the induced subgraph G[Ui], we note that it has vertex vi of degree |Ri| − 1 ≥ 9|Ri|
10
≥ 9
10(1+19 β)
|Ui|. By applying Lemma 2.1 to G[Ui] we find an induced odd subgraph Oi of G[Ui] of size at least 9
20(1+19 β)
|Ui| = 9|Ui|
39
.Finally, since all Ui’s are disjoint, there are no edges between any two such Ui’s and since V2 ⊆ ⋃ Ui,we conclude that O = ⋃ki=1 Oi is an induced odd subgraph of size at least 9|V2|
39
n/ 61. This completes the proof.
3 Proof of Theorem 3
The main plan is as follows. We will grow edge by edge a matching M with sides U, W so that every
w ∈ W has exactly one neighbor between the vertices covered by M (which is of course its mate u in the matching). Moreover, the set U has “many” neighbors outside of M not connected to W . If the set of such neighbors is substantially large, then we will be able to apply Lemma 2.3 to get a large induced subgraph with all degrees odd. Otherwise we will show that either there exists a large subset of vertices
V ′ such that δ(G[V ′]) ≥ 1 with small L(G[V ′]; 1 /20) (and then we are done by Lemma 2.5), or that we can extend the matching while enlarging substantially the set of neighbors outside M not connected to
W . The details are given below. We start with M0 = ∅, and given Mi, i ≥ 0, we define
Xi = N (Ui) \ (Wi ∪ N (Wi)) ,Vi = V \ N (Ui ∪ Wi) .
In particular, we initially have X0 = ∅ and V0 = V . We will run our process until the first time we have |Vi| < n/ 2 (in particular, we may assume throughout the process that |Vi| ≥ n/ 2). Now, fix β = 1 /20 and δ = 1 /14 (same parameters as set before Lemma 2.5). Our goal is to show that
fo(G) ≥ n
T
, where T = 10000. We will maintain |Xi| ≥ |V \Vi|
40
. If at some point we reach |Xi| ≥ 4n
T
then we are done by Lemma 2.3. Hence we assume |Xi| ≤ 4n
T
= n
2500
. Moreover, if G[Vi] has at least 2 n/T
isolated vertices, then since this set induces an independent set in G, by Lemma 2.2 we are done as well. Therefore, letting V ′
i
⊆ Vi be the set of all non-isolated vertices in G[Vi], since |Vi| ≥ n/ 2 we obtain that |V ′
i
| ≥ (1 − 4/T )|Vi| ≥ | Vi|/2. We can further assume |L(G[V ′
i
]; β)| ≥ δ|V ′
i
| ≥ δn/ 4, as otherwise by Lemma 2.5 we obtain an odd subgraph of size at least |V ′
i
|/61 ≥ n/ 244. Our goal now is to show that under these assumptions we can add an edge to Mi while maintaining |Xi+1 | ≥ |V \Vi+1 |
40
.Consider first the case where every v ∈ L := L(G[V ′
i
]; β) satisfies d(v, X i) ≥ d(v, V i)/40. By Lemma 2.4 applied to the bipartite graph between Xi and L, using the fact that
|Xi| ≤ 4n
T = n
2500 ≤ |L|
44 ,
7we derive that there is an edge xv with x ∈ Xi and v ∈ L and d(x, L ) ≥ 44 d(v, X i ) ≥ 1.1d(v, V i ) > 0. Then we can define Mi+1 by adding xv to Mi and setting Ui+1 := Ui ∪ { x} and Wi+1 := Wi ∪ { v}. By doing so we obtain that
|Xi+1 | = |N (Ui+1 ) \ (Wi+1 ∪ N (Wi+1 )|≥ | N (Ui) \ (Wi ∪ N (Wi)) | + |N (x, V i)| − | N (v, X i)| − | N (v, V i)|
= |Xi| + d(x, V i) − d(v, X i) − d(v, V i)
≥ | Xi| + d(x, V i)
(
1 − 1
44 − 10
11
)
|Xi| + 3d(x, V i)
44 .
Moreover, since we clearly have that
|Vi+1 | ≥ | Vi| − d(x, V i) − d(v, V i) ≥ | Vi| − 21 d(x, V i)
11 ,
it follows that at least 3/44
21 /11
1
40
proportion of the vertices deleted from Vi go to Xi+1 .In the complementary case there exists a vertex v ∈ L with d(v, X i) ≤ d(v, V i)/40. Let uv be an edge in G[V ′
i
] witnessing v ∈ L (that is, |N (u, V i) \ N (v, V i)| ≥ β|N (u, V i) ∪ N (v, V i)|). Then we can define Mi+1 by adding uv to Mi, and set Ui+1 := Ui ∪ { u} and Wi+1 := Wi ∪ { v}. In this case we have:
|Xi+1 | = |N (Ui+1 ) \ (Wi+1 ∪ N (Wi+1 )) |≥ | N (Ui) \ (Wi ∪ N (Wi)) | + |N (u, V i) \ N (v, V i)| − | N (v, X i)|
= |Xi| + |N (u, V i) \ N (v, V i)| − | N (v, X i)|≥ | Xi| + β|N (u, V i) ∪ N (v, V i)| − | N (v, X i)|≥ | Xi| + ( β − 1
40 )|N (u, V i) ∪ N (v, V i)|.
Moreover, since we have |Vi+1 | ≥ | Vi| − | N (u, V i) ∪ N (v, V i)|, at least β − 1
40
= 1
40
proportion of the vertices deleted from Vi go to Xi+1 .All in all, in each step, either we find an odd subgraph of size at least n
T
(in case that we have “many” isolated vertices, or that |Xi| ≥ 4n
T
, or that L(G[V ′
i
]; β) is “large”), or we can keep Xi of size at least
|V\Vi|
40
. In particular, if the latter case holds until |Vi| < n/ 2, we obtain that |Xi| ≥ n
80
and we are done by Lemma 2.3. This completes the proof.
Acknowledgement. We would like to thank Alex Scott for his remarks, and for pointing out a serious flaw in the previous version.
References
Y. Caro, On induced subgraphs with odd degrees, Discrete Mathematics 132 (1994), 23–28. L. Lov´ asz, Combinatorial Problems and Exercises, 2nd edition, AMS Chelsea Publishing, 1993. A. D. Scott, Large induced subgraphs with all degrees odd, Combinatorics, Probability and Com-puting 1 (1992), 335–349. A. D. Scott, On induced subgraphs will all degrees odd, Graphs and Combinatorics 17 (2001), 539–553. 8 |
12563 | https://blog.csdn.net/victor_woo/article/details/10065585 | 求平面两圆公切线 切点坐标_两圆的公切线的切点坐标怎么求-CSDN博客
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求平面两圆公切线 切点坐标
最新推荐文章于 2021-02-11 17:53:25 发布
victor_woo于 2013-08-19 11:41:38 发布
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要正确绘制 两圆 之间的 公切线,需要计算切线方程: 两圆 心距离:d = radius_large - radius = 2.0 切线长度:L = sqrt(d² + r²)(r为半径差) 正确的切线方向向量应为: dx=(radius_largenp.cos(theta)-radiusnp.cos(theta))dy=(radius_largenp.sin(theta)-radiusnp.sin(theta)) ...
【算法分析】QQ“一键退朝”之详细计算方法_canvas metaball 算法-CSDN...
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2.求 切点 坐标 复习一下初中数学: 两个外离的圆,一定有两条外 公切线。若 两圆 半径相同,则两外 公切线 平行;否则相交于一点,且该点与 两圆 心在同一直线。 我们再作一张有 公切线 的图: 切点 为P1、P2、P3、P4P1、P2、P3、P4,我们现在目的就要 求 出这四个点,然后就能够在程序中画出切线。
2017届高考数学大一轮总复习第八章 平面 解析几何计时双基练48直线与圆圆与圆的位置关系文北师大版.doc
09-12
第9题，两个圆恰有三条 公切线 意味着 两圆 外切，建立方程组 求 解a、b的关系，进而 求 解表达式的最小值。 这些题目覆盖了 平面 解析几何中的基本概念、公式和方法，包括点到直线的距离公式、圆的标准方程、圆的切线性质、...
2021届高考数学一轮复习第八章 平面 解析几何第四节直线与圆圆与圆的位置关系课时规范练文含解析北师大版202102201179
08-07
- 圆的切线方程可以通过已知圆的方程和 切点 坐标 求 得，例如第4题中利用点斜式方程。 4. 距离公式： - 圆心到直线的距离公式：d = |ax0 + by0 + c| / √(a^2 + b^2)，其中(a, b)是圆心 坐标，c是直线一般式Ax + ...
两个圆 公切线 求 法_ 两圆 的 公切线 教案
weixin_39725885的博客
02-11 1394
两圆 的 公切线 教案第一课时 两圆 的 公切线(一)教学目标：(1)理解 两圆 相切长等有关概念，掌握 两圆 外 公切线 长的 求 法；(2)培养学生的归纳、总结能力；(3)通过 两圆 外 公切线 长的 求 法向学生渗透“转化”思想．教学重点：理解 两圆 相切长等有关概念，两圆 外 公切线 的 求 法．教学难点：两圆 外 公切线 和 两圆 外 公切线 长学生理解的不透，容易混淆．教学活动设计(一)实际问题(引入)很多机器上的传动带与主动轮、从动轮之间的位置关系...
两个圆 公切线 求 法_ 求 两圆 的 公切线 计算
weixin_39695374的博客
12-18 5240
关于 两圆 的 公切线 计算我们首先需要搞清楚的是两个圆之间有哪些位置关系，两个圆的位置包括内含、内切、外切、外离几种方式，可以看出位置关系可以根据“两圆 心之间的距离”与“两圆 半径和”以及“两圆 半径差”之间的关系判断。 假设大圆半径为R，小圆半径为 r， 把“两圆 心之间的距离”表示为d，“两圆 半径和”表示为s，“两圆 半径差”表示为x，那么：d = |R + r|;x =|R - r|;可以得出各位置...
求 两个圆的 公切线
weixin_30662109的博客
11-24 813
[Manipulate[ Block{deta1, deta2, p1, p2, q, a1, b1, a2, b2, outerLine1, outerLine2, innerLine1, innerLine2}, {{a1, b1}, {a2, b2}} = p; deta1 = (a1 - a2)^2 + (b1 - b2)^2 - (r1 + r2)^2; ...
UVa 10674 (求 两圆 公切线) Tangents
weixin_30613433的博客
10-15 184
题意: 给出两个圆的圆心 坐标 和半径，求 这两个圆的 公切线 切点 的 坐标 及对应线段长度。若 两圆 重合，有无数条 公切线 则输出-1. 输出是按照一定顺序输出的。 分析： 首先情况比较多，要一一判断，不要漏掉。 如果高中的那点老底还在的话，代码还是很好理解的。 1 //#define LOCAL 2 #include 3 #include &...
E. Fruit Slicer--计算几何+两圆 公切线
zjyang12345的博客
09-22 971
很明显，直线是 两圆 公切线 的时候，经过的圆最多，而n只有100，公切线 最多4条，只需要(n^2）暴力枚举 两圆 公切线，然后再(n)得到 公切线 经过圆的数目，最后取max即可。复杂度O(n^3)级别 #include #include #include&l...
UVA 10674 || Tangents（求 两圆 的共切线
野生
04-14 1396
大白模板题，但是大白模板放这题会有精度误差，死Wa，看了个题解，也是从大白模板改的，全部都用了浮点误差，偷偷敲走。 两圆 的共切线，根据 两圆 的圆心距从小到大排列，一共有六种情况。 1） 两圆 完全重合，有无数条 公切线，返回-1； 2）两圆 内含，没有公共点，无 公切线，返回0； 3）两圆 内切，有一条外 公切线； 4）两圆 相交，有两条外 公切线； 5）两圆 外切，有两条外 公切线，一条内 公切线；
【UVa10674】Tangents（两圆 公切线 的 切点--验板子题）
Cassie_zkq的博客
08-16 675
题目地址： 题目： 给出两个圆的圆心 坐标 和半径，求 公切线 数目（-1表示无穷）、两圆 公切线 的 切点 和这条 公切线 上 切点 的距离。 ac代码： 注意精度！！比较大小尽量用三态函数 #include <bit...
两圆 圆心距离计算及位置关系判断（C++实现）
LeopoldZhang2000的博客
02-14 6477
定义一个表示圆的类Circle，包含x,y,r三个私有变量，分别为圆心x 坐标，圆心y 坐标 和圆半径。声明Circle类的两个友元函数distance和relation，分别计算 两圆 圆心位置和判断 两圆 位置关系。
二维几何模板-与圆有关的计算 _long double 版
Jingqi@Mr.B的ACM博客
04-12 590
#include #include #include #include #include const long double eps=1e-10; const long double PI=acos(-1); using namespace std; struct Point{ long double x; long double y; Point(long doub
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victor_woo:Behavior of polymorphic methods inside constructors “if you call a dynamically bound method inside a constructor ,the overridden definition for that method is also used.However , the effect of this call be rather unexpected because the overridden method will be called before the object if fully constructed .This can conceal some difficult-to-find bugs." "On the other hand, you hsould be pretty horrified at the outcome of this program. You've done a perfectly logical thing,and yet the behavior is mysteriously wrong,with no complaints from the compiler. C++produces more rational behavior in this situation. Bugs like this could easily be buried and take a long time to discover." "As a result.......The only safe methods to call inside a constructor are those that are final in the base class(This also applies to private methods,which are automatically final.)
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12564 | https://www.ncbi.nlm.nih.gov/books/NBK190102/table/epb42-spherocytosis.T.genes_associated_w/ | Table 3a. [Genes Associated With Hereditary Spherocytosis]. - GeneReviews® - NCBI Bookshelf
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Adam MP, Feldman J, Mirzaa GM, et al., editors. GeneReviews® [Internet]. Seattle (WA): University of Washington, Seattle; 1993-2025.
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Table 3a.
Genes Associated With Hereditary Spherocytosis
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| Gene | Protein | MOI | Severity 1 | Comment | OMIM |
--- --- --- |
| ANK1 | Ankyrin-1 | AD | Mild to moderate | | 182900 |
| AR | Moderately severe to severe | Often transfusion dependent |
| EPB42 | Protein 4.2 2 | AR | Mild to moderate 3 | 1 person reported w/moderately severe HS | 612690 |
| SLC4A1 | Band 3 anion transport protein | AD | Mild to moderate | | 612653 |
| AR | Severe 2 | Rare; persons present w/life-threatening hydrops fetalis & remain transfusion dependent even after splenectomy. | |
| SPTA1 | Spectrin alpha chain, erythrocytic 1 | AR | Severe | Very frequently transfusion dependent | 270970 |
| SPTB | Spectrin beta chain, erythrocytic | AD | Mild to moderate | | 616649 |
| AR | Severe | 1 person reported: infant w/fatal HS | |
AD = autosomal dominant; AR = autosomal recessive; HS = hereditary spherocytosis; MOI = mode of inheritance
Defined in Table 1.
Significant decrease or absence of erythrocyte membrane protein 4.2 in erythrocytes of persons with HS may also be secondary to biallelicSLC4A1 pathogenic variants by either decreasing band 3 in the red blood cell membrane [Toye et al 2008] or affecting the band 3 binding site for protein 4.2 [Kanzaki et al 1997].
EPB42-related HS is typically milder than the other forms of HS inherited in an AR manner (i.e., autosomal recessiveANK1-related HS and SPTA1-related HS) [Kalfa 2021].
From: EPB42-Related Hereditary Spherocytosis
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Kalfa TA, Begtrup AH. EPB42-Related Hereditary Spherocytosis. 2014 Mar 13 [Updated 2022 Apr 7]. In: Adam MP, Feldman J, Mirzaa GM, et al., editors. GeneReviews® [Internet]. Seattle (WA): University of Washington, Seattle; 1993-2025. Table 3a. [Genes Associated With Hereditary Spherocytosis]. Available from:
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12565 | https://jmedicalcasereports.biomedcentral.com/articles/10.1186/s13256-023-03986-y | Journal of Medical Case Reports
Adult Hirschsprung’s disease presenting as chronic constipation: a case report
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Case report
Open access
Published:
Adult Hirschsprung’s disease presenting as chronic constipation: a case report
Theresia Monica Rahardjo ORCID: orcid.org/0000-0001-9280-023X1,
Yeppy Arief Nurzaman2,
Janice Natalia ORCID: orcid.org/0000-0002-8033-45901,
Indra Hapdijaya ORCID: orcid.org/0000-0002-7469-09511,
Livia Devina ORCID: orcid.org/0000-0002-1017-13511,
Hendrik Andrianto ORCID: orcid.org/0000-0002-6829-27891 &
…
Jeffrey Christian Mahardhika ORCID: orcid.org/0000-0002-1172-49312
Journal of Medical Case Reports volume 17, Article number: 308 (2023) Cite this article
11k Accesses
6 Citations
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Abstract
Background
Hirschsprung’s disease is a congenital disorder identified by the absence of ganglion cells at the Meissner’s plexus of the submucosa and Auerbach’s plexus of the muscularis. This disease can be found in approximately 1 in 5000 live births. It is a congenital disorder that is rarely diagnosed in adults, where 95% of cases are diagnosed in infants aged under 1 year old. Here we present a rare case of adult Hirschsprung’s disease to enrich the body of knowledge in diagnosing adult patients with chronic refractory constipation symptoms.
Case report
An 18-year-old Indonesian woman came to the general surgery department of Unggul Karsa Medika Teaching Hospital with a defecating problem (constipation) since childhood. There was no history of her passage of meconium. A contrast enema study showed that the sigmoid colon was dilated and the rectum was narrowed, with rectosigmoid index < 1. With these findings, it was suspected that the patient may have ultra-short segment Hirschsprung’s disease. The patient was then referred to the digestive surgery department of referral hospital for surgical treatment.
Conclusion
In adult patients presenting with history of constipation since childhood, it is necessary to consider the possibility of Hirschsprung’s disease that was not diagnosed in early childhood. Hirschsprung’s disease in adults is usually a short or ultra-short aganglionic segment because it shows relatively mild symptoms. Surgical removal of the aganglionic segment of the gut is the definitive treatment for Hirschsprung’s disease.
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Background
Hirschsprung’s disease is a congenital disorder identified by the absence of ganglion cells at the Meissner’s plexus of the submucosa and Auerbach’s plexus of the muscularis. It is usually characterized by nonspecific symptoms such as chronic constipation [1/
. Accessed 3 Dec 2022.")]. Hirschsprung’s disease can be found in approximately 1 in 5000 live births . Since it is a rare disease, literature study is often conducted without gender-specific analysis and only including a small number of patients . The diagnosis is made before the age of 1 month in 65% of the total cases and before the age of 1 year in 95% of the total cases [1: StatPearls Publishing; 2022 Jan.
. Accessed 3 Dec 2022.")]. Rectal touch findings might show a tight anal sphincter and explosive discharge of gas and stool. Despite the fact that most patients are identified in their infancy and the early stages of their lives, there are some rare cases that may not be detected until the age of adolescence or adult . This report presents a rare case of chronic constipation of an adult who was later diagnosed as Hirschsprung’s disease.
Case presentation
An 18-year-old Indonesian woman came to the general surgery department of Unggul Karsa Medika Teaching Hospital with a main complaint of a defecating problem (constipation) since childhood. She said that her defecation frequency is once or twice a month. She has not taken any medical interventions in any hospital or clinic except over-the-counter drugs such as cathartic drugs. She was unaware of her past history of passage of meconium. There was no history of growth or development problems. Physical examinations conducted on the patient showed her abdomen was slightly bloated, and rectal touch showed a collapsed ampullae.
Plain abdominal radiograph revealed that the air distribution in the colon and small intestine was increased with coiled spring appearance (Fig. 1A). There was neither stepladder appearance nor subdiaphragmatic free air. A contrast enema study was performed and showed that the sigmoid colon was dilated and the rectum was narrowed with rectosigmoid index less than 1 and irregular rectosigmoid mucosa. The study also showed neither rat tail appearance nor filling defects (Fig. 1B–F). With these findings, it was suspected that the patient may have ultra-short segment hypo-ganglionic type of Hirschsprung’s disease. As we do not have a digestive surgery consultant to perform the surgery, we performed rectal washout using laxative agents. The patient felt better after she could defecate, and we then referred her to the nearest referral hospital for surgical intervention. However, owing to economic problems, the patient could not afford surgery and thus only used laxative agents once a week. The patient said laxative can relieve constipation and help to improve her quality of life, even though surgery is the main treatment for her condition.
Discussion
Constipation is a common disorder that usually refers to persistent, infrequent defecation, difficult stool passage with pain and stiffness [51
.")]. Chronic constipation in adults is the sixth most common gastrointestinal symptom, with global prevalence of 15%. Chronic constipation affects women more than men, with a median female-to-male ratio of 1.5:1. The prevalence is also higher in non-Caucasians group compared with Caucasians. It can be either primary or secondary [6:1232-1249.e3.
.")].
The pathophysiology and differential diagnosis of chronic constipation are multifactorial and include iatrogenic, organic stenosis, endocrine or metabolic disorders, neurological disorders, enteric neuropathies, myogenic disorders, colon disease (such as irritable bowel syndrome or diverticulitis), and anorectal disorders 51
."), [7:886–93.
.")]. Careful history-taking and physical examination should be performed, including duration of symptoms, frequency and consistency of stool, size of the stool, sensation of incomplete stool evacuation, straining, and digital rectal examination [5. 2018;97(20): e10631.
."), 8:185–91.
.")]. After the initial history and physical examination, a series of tests should be performed to exclude underlying diseases. Barium enema, endoscopy, anorectal manometry, and balloon expulsion test can be considered to diagnose chronic constipation [5. 2018;97(20): e10631.
.")].
Hirschsprung's disease is characterized as the total nonexistence of ganglion cells within the colonic wall and an absent recto-anal inhibitory reflex. This is the most frequent finding within the gastrointestinal neuromuscular disorder, a group of disorders that also includes hypoganglionosis, ganglioneuromatosis, intestinal neuronal dysplasia, myopathies, and abnormalities of the interstitial cells of Cajal. It is known in 2% of patients, a chief complaint of chronic constipation is caused by the disease. This symptom of chronic constipation will show up as a result of short aganglionic segment in the descending part of the colon less than 10 cm in length .
Hirschsprung's disease is one of the main causes of intestinal obstruction in infancy. Diagnosis and treatment are conducted at an early age, in the first 5 years of life in more than 90% of cases. Consequently, the diagnosis of Hirschsprung’s disease in adulthood is rare [97
.")]. The classic clinical symptoms including abdominal distension (in more than 90% cases), vomiting (more than 85% cases), which may be bilious, and failure to pass meconium during the first 24 h of life (more than 60% cases) [10:164.
.")].
Adult Hirschsprung’s disease is commonly misdiagnosed as refractory constipation. The absence of intramural ganglion cells in the affected segment of the colon is the underlying mechanism of refractory constipation in Hirschsprung’s disease in both infants and adults. Mild Hirschsprung’s disease in early life might go undetected due to the proximal colon compensating for the nonmobile colon segment, then presenting as chronic refractory constipation in adulthood. When this happens, most patients usually use cathartic agents to alleviate this symptom. However, at some point, this condition can deteriorate into distal colon obstruction, then the patient will experience rapidly worsening constipation or even acute intestinal obstruction .
Once Hirschsprung’s disease is clinically suspected, imaging studies, anal manometry, and full-thickness rectal biopsies are usually performed to confirm the diagnosis . Plain abdominal radiograph is usually the first investigation. It might demonstrate grossly distended large bowel, with possible absence of stool in the distal colon or rectum. However, the water-soluble contrast enema, which has been used for more than 50 years to diagnose Hirschsprung’s disease, is a radiologic examination of choice. It shows a transition zone between a narrow distal aganglionic bowel segment and distended proximal ganglionated bowel, which is considered to be the most accurate radiologic feature of Hirschsprung’s disease .
A case similar to that reported herein was reported in Bali, Indonesia: a 13-year-old girl who had chronic refractory constipation and abdominal distension since birth. The patient only defecated once a month. Histopathological examination was performed, and the result confirmed that the distal rectum part was aganglionic. Therefore, the patient was diagnosed with ultra-short segment Hirschsprung's disease . Another case of adult Hirschprung’s disease was reported by Soussan et al. The patient was a 20-year-old male with history of chronic constipation who presented with inability to evacuate stool and gas along with abdominal pain. Abdominal CT scan showed dilated colon and intestine. Surgical treatment was done, and histological findings showed aganglionic part of sigmoid, thus confirming the diagnosis of Hirschprung’s disease [144
.")].
Based on the length of the aganglionic segment of the colon, Hirschsprung's disease is classified into four categories. The first one is short aganglionic segment (75–80% of cases) in which the aganglionic segment is present in the distal sigmoid colon and rectum. The second one is long aganglionic segment (10% of cases) in which the aganglionic colon segment is present from distal sigmoid colon and rectum until splenic flexure. The third one is the rarest form of Hirschsprung's disease and has the most severe clinical course, which is total colonic aganglionosis or involving the entire colon (5% of cases). The last one is called the ultra-short aganlionic segment, which involves only the distal rectum and the anal canal above the pectinate line. Hirschsprung’s disease in adults usually presents as short aganglionic segment or ultra-short aganglionic segment, thus showing relatively mild symptoms, especially in the early stages of life .
Intravenous fluid resuscitation, decompression method with nasogastric tube insertion and rectal washouts, along with antibiotic treatment when indicated, for example when perforation of abdominal organs is suspected, are the initial treatments for adult Hirschsprung’s disesase. Meanwhile, surgical removal of the aganglionic segment remains the definitive treatment for this disease [152
.")].
The surgical approach for Hirschsprung’s disease is determined by the length of the achalasic zone, the length and reversibility of colonic dilation, the nutritional status of the patient, and the experience of the operator. Trans-anal myectomy is primarily used to remove the spasm from the aganglionic zone when it is very short. Sigmoid rectal resection with colo-anal anastomosis and Swenson’s procedure is used to remove the aganglional part of the rectum and the irreversibly distended part of the upstream colon .
The Duhamel technique is based on the principle of a short circuit of the aganglionic zone, lowering the healthy colon behind the diseased rectum left in place. This technique is performed when rectal dissection is very difficult to achieve and has morbid consequences to the patient. Another technique is the Soave’s procedure, which is resecting the distended colon and the upper part of the pathological rectum, but then the resection stops before approaching the lower rectum. The ganglionic colon is then pulled through the rectum, from which the mucosa has been removed. This surgical technique has a degree of difficulty that is related to the length of the remaining ganglionic colon of the patient [160
.")].
We report herein a rare case of adult Hirschsprung’s disease with history of chronic refractory constipation since childhood. While our case report did not present how the definitive treatment was done or its result owing to the lack of digestive surgeon in our hospital, this case report suggests the necessity to workup towards Hirschsprung’s disease when encountering patients with chronic refractory constipation. Hirschsprung’s disease in adults is usually caused by short aganglionic segment of distal colon or ultra-short aganglionic segment because those types will show relatively mild symptoms, thus leading to late diagnosis of the disease . Careful history-taking, physical examination, and the usage of simple radiology modalities such as abdominal plain radiograph and contrast enema study can be very useful in diagnosing adult Hirschsprung’s disease. Radiological studies showed signs of distal colon obstruction as there was increased air distribution in the colon and coiled spring appearance, then the contrast enema study showed dilation of sigmoid colon and narrow rectum with rectosigmoid index less than 1 and irregular rectosigmoid mucosa. These findings thus directed our clinical judgement to the diagnosis of Hirschsprung’s disease.
Initial treatment to decompress the abdomen was necessary to alleviate the symptoms, using nasogastric tube and rectal washout using laxative agents. However, the definitive treatment of surgery using one of the techniques stated above has to be done.
Conclusion
In adult patients presenting with history of constipation since childhood, it is necessary to consider the possibility of Hirschsprung’s disease which was failed to be diagnosed in early childhood. Hirschsprung’s disease in adults is usually a short or ultra-short aganglionic segment because it shows relatively mild symptoms. Surgical removal of the aganglionic segment of the colon is definitive treatment for Hirschsprung’s disease.
Availability of data and materials
The data and materials from this study are available from the corresponding author.
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Acknowledgements
We thank Unggul Karsa Medika Hospital for supporting this study by providing the patient data.
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Authors and Affiliations
Faculty of Medicine, Maranatha Christian University, Suria Sumantri 65, Bandung, West Java, 40164, Indonesia
Theresia Monica Rahardjo, Janice Natalia, Indra Hapdijaya, Livia Devina & Hendrik Andrianto
2. Unggul Karsa Medika Teaching Hospital, Taman Kopo Indah III Block H-1, Bandung, West Java, 40218, Indonesia
Yeppy Arief Nurzaman & Jeffrey Christian Mahardhika
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Theresia Monica Rahardjo
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Contributions
TMR: provided discussion section and reviewing the manuscript, provided files related to ethics and consent. YAN: treated the patients, provided the case and discussion section. JN: provided data for the case report, provided the background and discussion section. IA: provided data for the case report, provided the background and discussion section. LD: provided data for the case report, provided the background and discussion section. HA: provided data for the case report, provided the background and discussion section. JCM: reviewing the manuscript, providing the discussion section. All authors read and approved the final manuscript.
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Correspondence to Theresia Monica Rahardjo.
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Rahardjo, T.M., Nurzaman, Y.A., Natalia, J. et al. Adult Hirschsprung’s disease presenting as chronic constipation: a case report. J Med Case Reports 17, 308 (2023).
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Keywords
Hirschsprung’s disease
Constipation
Congenital
Adult
Case report
Journal of Medical Case Reports
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12567 | https://www.princeton.edu/~aaa/Public/Teaching/ORF523/S16/ORF523_S16_Lec2_gh.pdf | ORF 523 Lecture 2 Spring 2016, Princeton University Instructor: A.A. Ahmadi Scribe: G. Hall Tuesday, February 9, 2016 When in doubt on the accuracy of these notes, please cross check with the instructor’s notes, on aaa. princeton. edu/ orf523 . Any typos should be emailed to gh4@princeton.edu.
Today, we review basic math concepts that you will need throughout the course.
• Inner products and norms • Positive semidefinite matrices • Basic differential calculus 1 Inner products and norms 1.1 Inner products 1.1.1 Definition Definition 1 (Inner product). A function ⟨., .⟩: Rn × Rn →R is an inner product if 1. ⟨x, x⟩≥0, ⟨x, x⟩= 0 ⇔x = 0 (positivity) 2. ⟨x, y⟩= ⟨y, x⟩(symmetry) 3. ⟨x + y, z⟩= ⟨x, z⟩+ ⟨y, z⟩(additivity) 4. ⟨rx, y⟩= r⟨x, y⟩for all r ∈R (homogeneity) Homogeneity in the second argument follows: ⟨x, ry⟩= ⟨ry, x⟩= r⟨y, x⟩= r⟨x, y⟩ using properties (2) and (4) and again (2) respectively, and ⟨x, y + z⟩= ⟨y + z, x⟩= ⟨y, x⟩+ ⟨z, x⟩= ⟨x, y⟩+ ⟨x, z⟩ using properties (2), (3) and again (2).
1 1.1.2 Examples • The standard inner product is ⟨x, y⟩= xTy = X xiyi, x, y ∈Rn.
• The standard inner product between matrices is ⟨X, Y ⟩= Tr(XTY ) = X i X j XijYij where X, Y ∈Rm×n.
Notation: Here, Rm×n is the space of real m × n matrices. Tr(Z) is the trace of a real square matrix Z, i.e., Tr(Z) = P i Zii.
Note: The matrix inner product is the same as our original inner product between two vectors of length mn obtained by stacking the columns of the two matrices.
• A less classical example in R2 is the following: ⟨x, y⟩= 5x1y1 + 8x2y2 −6x1y2 −6x2y1 Properties (2), (3) and (4) are obvious, positivity is less obvious. It can be seen by writing ⟨x, x⟩= 5x2 1 + 8x2 2 −12x1x2 = (x1 −2x2)2 + (2x1 −2x2)2 ≥0 ⟨x, x⟩= 0 ⇔x1 −2x2 = 0 and 2x1 −2x2 = 0 ⇔x1 = 0 and x2 = 0.
1.1.3 Properties of inner products Definition 2 (Orthogonality). We say that x and y are orthogonal if ⟨x, y⟩= 0.
Theorem 1 (Cauchy Schwarz). For x, y ∈Rn |⟨x, y⟩| ≤||x|| ||y||, where ||x|| := p ⟨x, x⟩is the length of x (it is also a norm as we will show later on).
2 Proof: First, assume that ||x|| = ||y|| = 1.
||x −y||2 ≥0 ⇒⟨x −y, x −y⟩= ⟨x, x⟩+ ⟨y, y⟩−2⟨x, y⟩≥0 ⇒⟨x, y⟩≤1.
Now, consider any x, y ∈Rn. If one of the vectors is zero, the inequality is trivially verified.
If they are both nonzero, then: x ||x||, y ||y|| ≤1 ⇒⟨x, y⟩≤||x|| · ||y||.
(1) Since (1) holds ∀x, y, replace y with −y: ⟨x, −y⟩≤||x|| · || −y|| ⟨x, −y⟩≥−||x|| · ||y|| using properties (1) and (2) respectively. □ 1.2 Norms 1.2.1 Definition Definition 3 (Norm). A function f : Rn →R is a norm if 1. f(x) ≥0, f(x) = 0 ⇔x = 0 (positivity) 2. f(αx) = |α|f(x), ∀α ∈R (homogeneity) 3. f(x + y) ≤f(x) + f(y) (triangle inequality) Examples: • The 2-norm: ||x|| = pP i x2 i • The 1-norm: ||x||1 = P i |xi| • The inf-norm: ||x||∞= maxi |xi| • The p-norm: ||x||p = (P i |xi|p)1/p, p ≥1 Lemma 1. Take any inner product ⟨., .⟩and define f(x) = p ⟨x, x⟩. Then f is a norm.
3 Proof: Positivity follows from the definition.
For homogeneity, f(αx) = p ⟨αx, αx⟩= |α| p ⟨x, x⟩ We prove triangular inequality by contradiction. If it is not satisfied, then ∃x, y s.t.
p ⟨x + y, x + y⟩> p ⟨x, x⟩+ p ⟨y, y⟩ ⇒⟨x + y, x + y⟩> ⟨x, x⟩+ 2 p ⟨x, x⟩⟨y, y⟩+ ⟨y, y⟩ ⇒2⟨x, y⟩> 2 p ⟨x, x⟩⟨y, y⟩ which contradicts Cauchy-Schwarz.
Note: Not every norm comes from an inner product.
1.2.2 Matrix norms Matrix norms are functions f : Rm×n →R that satisfy the same properties as vector norms.
Let A ∈Rm×n. Here are a few examples of matrix norms: • The Frobenius norm: ||A||F = p Tr(ATA) = qP i,j A2 i,j • The sum-absolute-value norm: ||A||sav = P i,j |Xi,j| • The max-absolute-value norm: ||A||mav = maxi,j |Ai,j| Definition 4 (Operator norm). An operator (or induced) matrix norm is a norm ||.||a,b : Rm×n →R defined as ||A||a,b = max x ||Ax||a s.t. ||x||b ≤1, where ||.||a is a vector norm on Rm and ||.||b is a vector norm on Rn.
Notation: When the same vector norm is used in both spaces, we write ||A||c = max ||Ax||c s.t. ||x||c ≤1.
Examples: 4 • ||A||2 = p λmax(ATA), where λmax denotes the largest eigenvalue.
• ||A||1 = maxj P i |Aij|, i.e., the maximum column sum.
• ||A||∞= maxi P j |Aij|, i.e., the maximum row sum.
Notice that not all matrix norms are induced norms. An example is the Frobenius norm given above as ||I||∗= 1 for any induced norm, but ||I||F = √n.
Lemma 2. Every induced norm is submultiplicative, i.e., ||AB|| ≤||A|| ||B||.
Proof: We first show that ||Ax|| ≤||A|| ||x||. Suppose that this is not the case, then ||Ax|| > ||A|| |x|| ⇒ 1 ||x||||Ax|| > ||A|| ⇒ A x ||x|| > ||A|| but x ||x|| is a vector of unit norm. This contradicts the definition of ||A||.
Now we proceed to prove the claim.
||AB|| = max ||x||≤1 ||ABx|| ≤max ||x||≤1 ||A|| ||Bx|| = ||A|| max ||x||≤1 ||Bx|| = ||A|| ||B||.
□ Remark: This is only true for induced norms that use the same vector norm in both spaces. In the case where the vector norms are different, submultiplicativity can fail to hold. Consider e.g., the induced norm || · ||∞,2, and the matrices A = " √ 2/2 √ 2/2 − √ 2/2 √ 2/2 # and B = " 1 0 1 0 # .
In this case, ||AB||∞,2 > ||A||∞,2 · ||B||∞,2.
Indeed, the image of the unit circle by A (notice that A is a rotation matrix of angle π/4) stays within the unit square, and so ||A||∞,2 ≤1. Using similar reasoning, ||B||∞,2 ≤1.
5 This implies that ||A||∞,2||B||∞,2 ≤1. However, ||AB||∞,2 ≥ √ 2, as ||ABx||∞= √ 2 for x = (1, 0)T.
Example of a norm that is not submultiplicative: ||A||mav = max i,j |Ai,j| This can be seen as any submultiplicative norm satisfies ||A2|| ≤||A||2.
In this case, A = 1 1 1 1 !
and A2 = 2 2 2 2 !
So ||A2||mav = 2 > 1 = ||A||2 mav.
Remark: Not all submultiplicative norms are induced norms. An example is the Frobenius norm.
1.2.3 Dual norms Definition 5 (Dual norm). Let ||.|| be any norm. Its dual norm is defined as ||x||∗= max xTy s.t. ||y|| ≤1.
You can think of this as the operator norm of xT.
The dual norm is indeed a norm. The first two properties are straightforward to prove. The triangle inequality can be shown in the following way: ||x + z||∗= max ||y||≤1(xTy + zTy) ≤max ||y||≤1 xTy + max ||y||≤1 zTy = ||x||∗+ ||z||∗ □ Examples: 1. ||x||1∗= ||x||∞ 6 2. ||x||2∗= ||x||2 3. ||x||∞∗= ||x||1.
Proofs: • The proof of (1) is left as an exercise.
• Proof of (2): We have ||x||2∗= max y xTy s.t. ||y||2 ≤1.
Cauchy-Schwarz implies that xTy ≤||x|| ||y|| ≤||x|| and y = x ||x|| achieves this bound.
• Proof of (3): We have ||x||∞∗= max y xTy s.t. ||y||∞≤1 So yopt = sign(x) and the optimal value is ||x||1.
2 Positive semidefinite matrices We denote by Sn×n the set of all symmetric (real) n × n matrices.
2.1 Definition Definition 6. A matrix A ∈Sn×n is • positive semidefinite (psd) (notation: A ⪰0) if xTAx ≥0, ∀x ∈Rn.
• positive definite (pd) (notation: A ≻0) if xTAx > 0, ∀x ∈Rn, x ̸= 0.
7 • negative semidefinite if −A is psd. (Notation: A ⪯0) • negative definite if −A is pd. (Notation: A ≺0.) Notation: A ⪰0 means A is psd; A ≥0 means that Aij ≥0, for all i, j.
Remark: Whenever we consider a quadratic form xTAx, we can assume without loss of generality that the matrix A is symmetric. The reason behind this is that any matrix A can be written as A = A + AT 2 + A −AT 2 where B := A+AT 2 is the symmetric part of A and C := A−AT 2 is the anti-symmetric part of A. Notice that xTCx = 0 for any x ∈Rn.
Example: The matrix M = 5 1 1 −2 !
is indefinite. To see this, consider x = (1, 0)T and x = (0, 1)T.
2.2 Eigenvalues of positive semidefinite matrices Theorem 2. The eigenvalues of a symmetric real-valued matrix A are real.
Proof: Let x ∈Cn be a nonzero eigenvector of A and let λ ∈C be the corresponding eigenvalue; i.e., Ax = λx.
By multiplying either side of the equality by the conjugate transpose x∗of eigenvector x, we obtain x∗Ax = λx∗x, (2) We now take the conjugate of both sides, remembering that A ∈Sn×n : x∗ATx = ¯ λx∗x ⇒x∗Ax = ¯ λx∗x (3) Combining (2) and (3), we get λx∗x = ¯ λx∗x ⇒x∗x(λ −¯ λ) = 0 ⇒λ = ¯ λ, since x ̸= 0.
8 Theorem 3.
A ⪰0 ⇔all eigenvalues of A are ≥0 A ≻0 ⇔all eigenvalues of A are > 0 Proof: We will just prove the first point here. The second one can be proved analogously.
(⇒) Suppose some eigenvalue λ is negative and let x denote its corresponding eigenvector.
Then Ax = λx ⇒xTAx = λxTx < 0 ⇒A 0.
(⇐) For any symmetric matrix, we can pick a set of eigenvectors v1, . . . , vn that form an orthogonal basis of Rn. Pick any x ∈Rn.
xTAx = (α1v1 + . . . + αnvn)TA(α1v1 + . . . + αnvn) = X i α2 i vT i Avi = X i α2 i λivT i vi ≥0 where we have used the fact that vT i vj = 0, for i ̸= j.
2.3 Sylvester’s characterization Theorem 4.
A ⪰0 ⇔All 2n −1 principal minors are nonnegative.
A ≻0 ⇔All n leading principal minors are positive.
Minors are determinants of subblocks of A. Principal minors are minors where the block comes from the same row and column index set. Leading principal minors are minors with index set 1, . . . , k for k = 1, . . . , n. Examples are given below.
9 Figure 1: A demonstration of the Sylverster criteria in the 2 × 2 and 3 × 3 case.
Proof: We only prove (⇒). Principal submatrices of psd matrices should be psd (why?).
The determinant of psd matrices is nonnegative (why?).
3 Basic differential calculus You should be comfortable with the notions of continuous functions, closed sets, boundary and interior of sets. If you need a refresher, please refer to [1, Appendix A].
3.1 Partial derivatives, Jacobians, and Hessians Definition 7. Let f : Rn →R.
• The partial derivative of f with respect to xi is defined as ∂f ∂xi = lim t→0 f(x + tei) −f(x) t .
• The gradient of f is the vector of its first partial derivatives: ∇f = ∂f ∂x1 .
.
.
∂f ∂xn .
10 • Let f : Rn →Rm, in the form f = f1(x) .
.
.
fm(x) . Then the Jacobian of f is the m × n matrix of first derivatives: Jf = ∂f1 ∂x1 . . .
∂f1 ∂xn .
.
.
.
.
.
∂fm ∂x1 . . .
∂fm ∂xn .
• Let f : Rn →R. Then the Hessian of f, denoted by ∇2f(x), is the n × n symmetric matrix of second derivatives: (∇2f)ij = ∂f ∂xi∂xj .
3.2 Level Sets Definition 8 (Level sets). The α-level set of a function f : Rn →R is the set Sα = {x ∈Rn | f(x) = α}.
Definition 9 (Sublevel sets). The α-sublevel set of a function f : Rn →R is the set ¯ Sα = {x ∈Rn | f(x) ≤α}.
Lemma 3. At any point x, the gradient is orthogonal to the level set.
Figure 2: Illustration of Lemma 3 11 3.3 Common functions We will encounter the following functions from Rn to R frequently.
It is also useful to remember their gradients and Hessians.
• Linear functions: f(x) = cTx, c ∈Rn, c ̸= 0.
• Affine functions: f(x) = cTx + b, c ∈Rn, b ∈R ∇f(x) = c, ∇2f(x) = 0.
• Quadratic functions f(x) = xTQx + cTx + b ∇f(x) = 2Qx + c ∇2f(x) = 2Q.
3.4 Differentiation rules • Product rule. Let f, g : Rn →Rm, h(x) = f T(x)g(x) then Jh(x) = f T(x)Jg(x) + gT(x)Jf(x) and ∇h(x) = JT h (x) • Chain rule. Let f : R →Rm, g : Rn →R, h(t) = g(f(t)) then h′(t) = ∇f T(f(t)) f ′ 1(t) .
.
.
f ′ n(t) .
Important special case: Fix x, y ∈Rn. Consider g : Rn →R and let h(t) = g(x + ty).
Then, h′(t) = yT∇g(x + ty).
12 3.5 Taylor expansion • Let f ∈Cm (m times continuously differentiable). The Taylor expansion of a univariate function around a point a is given by f(b) = f(a) + h 1!f ′(a) + h2 2! f ′′(a) + . . . + hm m! f (m)(a) + o(hm) where h := b −a. We recall the “little o” notation: we say that f = o(g(x)) if lim x→0 |f(x)| |g(x)| = 0.
In other words, f goes to zero faster than g.
• In multiple dimensions, the first and second order Taylor expansions of a function f : Rn →R will often be useful to us: First order: f(x) = f(x0) + ∇f T(x0)(x −x0) + o(||x −x0||).
Second order: f(x) = f(x0) + ∇f T(x0)(x −x0) + 1 2(x −x0)T∇2f(x0)(x −x0) + o(||x −x0||2).
Notes For more background material see [1, Appendix A].
References S. Boyd and L. Vandenberghe.
Convex Optimization.
Cambridge University Press, boyd/cvxbook/, 2004.
E.K.P Chong and S.H. Zak. An Introduction to Optimization, Fourth Edition. Wiley, 2013.
13 |
12568 | https://www.youtube.com/watch?v=CBgRO7k1_Lw | Piecewise and odd/even functions
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Transcript:
he girls so this video is about peace M functions um sometimes they're also called peace wise functions and here's an example so let's say I've got FX equals two different things so it equals x if x is uh bigger than one and equals 1 if x is less than one okay so let's draw that so we've got our X and basically we split the axes into two regions the region bigger than one the region less than one so when it's less than one the curve is always one so that gives us a horizontal line through here at one when it's bigger than one the curve is X so that would be this curve which I'll try and draw dotted but it's only counted when X is bigger than one so that means it's just this section here that's thick and so that is the full P Mill function for this particular FX and then from here we might be asked to evaluate so you know we might be asked to evaluate F of 7 so then we go all right where does seven land well seven is bigger than one so seven lands there so so we replace x with 7 so it's just 7 and then we might be asked to evaluate I know F of 0 Z and here it's less than one and the function is identically one for anything less than one so F of 0 must be one okay let's do another example um let's say that FX oops something in red now oh well um equals x + 2 for X great than to0 should have go if there but whatever and X2 if x is less than zero and let's draw so we break our curve when X is zero so that's the y axis so it's bigger than zero it equals the line x equals sorry x + 2 so looks like that and when it's zero and below it looks like X2 so it looks like that half a parel that should hit the origin sorry now there's one other thing that we need to notice here and that is that they do not meet so in the one we had before I'll go back you can see that they met at their boundary this one does not meet so what we need to do is we need to consider which value what do we take when X is zero well when X is zero the curve says to evaluate x + 2 so that's the line so that means we don't evaluate the parabola which means there is an open circle there and obviously it doesn't need to be that big but we draw an open circle there and we could even emphasize a little bit and draw a closed Circle here to indicate that at that point of discontinuity basically where I lift my pen from the page at that point of discontinuity we go with the closed Circle not the open circle okay again we might be asked to evaluate so we could evate F of zero just to reinforce that point so at zero it must be on the top curve so it must be 0 + 2 so it must be two um f of -3 well -3 is less than zero so it must be -3 squar so that must be N9 and then we could be asked to evaluate F of a squar now this one's a little bit tricky a squ cuz it's a squared number must be positive so it must lie in the top one so we replace x with a 2 in the top one so it must be a 2 + 2 and that's basically P me function is I want to talk very quickly about OD and even functions as well so firstly we'll talk about even functions the definition of an even function is that if I take F ATX it's the same as sorry that's wrong it is the same as FX now what that means visually is if I draw some kind of curve over here on the right and then I try to evaluate it on the negative side which is what this is saying and it should be exactly the same value as it is on the positive side which means it should be exactly symmetrical something like that around the y- AIS and you can use those two definitions um interchangeably as long as you have a good drawing obviously so for example let's say we've got FX is x 4 - x^2 + 7 and we want to prove that it's even well we evaluate F of - x like that and then obviously when we raise anything to the power four becomes positive so that's x 4 same with squaring becomes positive and that is FX so that is even now in reality what we'll end up doing is we will use this to sketch the curve we'll have the curve we'll sketch the positive side and then we'll use symmetry to sketch the negative it's a day later I got really distracted by Porsche so sorry if this sounds odd um and what a lead in um now we're talking about odd functions so odd functions are similar to even functions except that F of - x = - F ofx so even functions it was plus F ofx odd functions it's minus and just to point something out this is the same as if I make it - F of - x = f ofx and I'll give you an example so the most common example that you'll see is y is X cubed and I should have used FX shouldn't lie but anyway so in this case f of - x = - x all cubed which = - x Cub which = - F ofx if you look at a graph so let's just look at X Cub first so this is X cubed now think about the Symmetry for a minute and you can hopefully see that it is a rotation around the x-axis sorry not around the xaxis around the origin so if you take this curve here and it's going to be bad because I've not done a good drawing and you rotate just that section 180° you get this so for that reason we say that this is a the Symmetry here is around the origin because if I take the full curve even if I take the full curve and you imagine it as like a I don't know you know a stick of piece of paper that You' cut out or something and you spin the whole thing 180° it will overlap where it was before um just for your edification another example is just like y = x right so if I take F of - x I get min - x which is - F of sorry minus F ofx and I'll just squeeze it in here if you think about what that looks like it's just a straight line through the origin apparently and if you spin it 180° it gets back to where it started okay that's a functions that'll do for today and I'll see you in class tomorrow to talk more about it bye-bye |
12569 | https://www.shmoop.com/study-guides/surface-area-volume/surface-area-cones.html | Surface Area and Volume Surface Area of Cones
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We've covered pyramids (literally, since we found the surface area), and now it's time to cover cones (literally, since we'll find the surface area).
A right cone is a cone where the axis is also the altitude. That means the height from the point on top to the base on the bottom hits the circle dead center at a 90° angle. All other cones are wrong. They're just plain wrong.
If we take a look at this cone's net, we'll be able to say something about its lateral and surface areas other than, "It's right here." Duh.
The lateral area of the cone is really a sector of a circle with radius l. (It used to be the slant height, now it's the radius?) The arc length of the sector is the same as the circumference of the base circle.
Proportions have served us well in the past, and they'll continue to do that if we use them right. The lateral area is the area of the sector. If we compare that to the area of what would be the whole circle, we can compare the arc length to what would have been the circumference.
The area of the sector is what we're trying to find. The area of the circle with radius l is π l 2. The measure of the arc is the circumference of the smaller circle, 2π r, and the circumference of the bigger circle is 2π l.
You could go through rearranging and solving yourself, or just trust us that it'll look like this in the end:
Area of sector = π rl
That means the lateral area of a cone is equal to π rl. Unexpectedly simple. To get the total surface area of a cone, we add in the area of the base:
SA = π rl + π r 2
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Sample Problem
The "Bigger Is Better" Ice Cream Company makes its own conical waffle cones. Their Super Duper Ice Cream Scooper is a scoop of ice cream that's 6 inches in diameter in a waffle cone. Mmmm. The cone itself has an altitude of 10 inches. How much waffle do they need to make the cone (in square inches)? And where's the closest store?
The diameter of the scoop is the diameter of the circular base of the cone. We're interested in the radius, not the diameter. (Hopefully he'll have better luck on match.com.) That means our radius r is 3 inches.
What about l, the slant height? The radius and the altitude form two legs of a right triangle with the slant height as the hypotenuse. Pythagorize it up.
a 2 + b 2 = c 2
3 2 + 10 2 = c 2
109 = c 2
c ≈ 10.44 inches
Now that we've found our slant height, we can find the waffle area using the lateral area formula for a cone.
L = π rl
L = π(3 inches)(10.44 inches)
L ≈ 98.4 square inches
Bigger really is better.
Like a pyramid, the surface area of an entire cone (base included), is just the lateral area plus the area of the base.
SA = L + B
We know the lateral area of a cone is π rl. The base of the cone is a circle with area π r 2. Plug those in, and we've got a surface area formula.
SA = π rl + π r 2
Sweet. Get your spoons poised and your fudge hot and ready. It's ice cream time.
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W hy's T his F unny?
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12570 | https://proofwiki.org/wiki/Preimage_Theorem | Preimage Theorem
From ProofWiki
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Contents
1 Theorem
2 Proof
3 Also known as
4 Sources
Theorem
Let yy be a regular value of a smooth submersion f:X→Yf:X→Y.
Then the preimage f−1(y)f−1(y) is a smooth submanifold of XX, with dimf−1(y)=dimX−dimYdimf−1(y)=dimX−dimY.
Proof
Let k,lk,l be natural numbers with k≥lk≥l.
By the Local Submersion Theorem, there exists coordinates in some open neighborhoods of x,yx,y such that f(x1,x2,…,xk)=(x1,…,xl)f(x1,x2,…,xk)=(x1,…,xl) and yy corresponds to (0,…,0)(0,…,0).
Let VV be that neighborhood of xx.
Then f−1(y)∩Vf−1(y)∩V is the set of points where x1=0,…,xl=0x1=0,…,xl=0.
The functions xl+1,…,xkxl+1,…,xk therefore form a coordinate system on the set f−1(y)∩Vf−1(y)∩V, which is a relatively open subset of f−1(y)f−1(y).
Together these functions then form a diffeomorphism to a Euclidean space.
We also have, by the regular value properties of yy, a surjection of tangent spaces from xx to yy.
This ensures smoothness of the solution set f−1(y)f−1(y).
◼■
Also known as
This theorem is also known as the submersion level set theorem, regular value theorem and regular level set theorem.
Sources
2013: John M. Lee: Introduction to Smooth Manifolds (2nd ed.): 55: Submanifolds §§ Embedded Submanifolds
Retrieved from "
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12571 | https://www.nature.com/articles/s41574-023-00949-7 | Skip to main content
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Consensus Statement
Published:
Consensus guideline for the diagnosis and management of pituitary adenomas in childhood and adolescence: Part 2, specific diseases
Márta Korbonits
ORCID: orcid.org/0000-0002-4101-94321,
Joanne C. Blair2,
Anna Boguslawska
ORCID: orcid.org/0000-0002-1348-39243,
John Ayuk4,
Justin H. Davies5,
Maralyn R. Druce1,
Jane Evanson6,
Daniel Flanagan7,
Nigel Glynn1,
Claire E. Higham8,
Thomas S. Jacques9,10,
Saurabh Sinha11,
Ian Simmons12,
Nicky Thorp8,
Francesca M. Swords13,
Helen L. Storr
ORCID: orcid.org/0000-0002-9963-19311 &
…
Helen A. Spoudeas10,14
Nature Reviews Endocrinology
volume 20, pages 290–309 (2024)Cite this article
25k Accesses
22 Citations
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This article has been updated
Abstract
Pituitary adenomas are rare in children and young people under the age of 19 (hereafter referred to as CYP) but they pose some different diagnostic and management challenges in this age group than in adults. These rare neoplasms can disrupt maturational, visual, intellectual and developmental processes and, in CYP, they tend to have more occult presentation, aggressive behaviour and are more likely to have a genetic basis than in adults. Through standardized AGREE II methodology, literature review and Delphi consensus, a multidisciplinary expert group developed 74 pragmatic management recommendations aimed at optimizing care for CYP in the first-ever comprehensive consensus guideline to cover the care of CYP with pituitary adenoma. Part 2 of this consensus guideline details 57 recommendations for paediatric patients with prolactinomas, Cushing disease, growth hormone excess causing gigantism and acromegaly, clinically non-functioning adenomas, and the rare TSHomas. Compared with adult patients with pituitary adenomas, we highlight that, in the CYP group, there is a greater proportion of functioning tumours, including macroprolactinomas, greater likelihood of underlying genetic disease, more corticotrophinomas in boys aged under 10 years than in girls and difficulty of peri-pubertal diagnosis of growth hormone excess. Collaboration with pituitary specialists caring for adult patients, as part of commissioned and centralized multidisciplinary teams, is key for optimizing management, transition and lifelong care and facilitates the collection of health-related quality of survival outcomes of novel medical, surgical and radiotherapeutic treatments, which are currently largely missing.
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Introduction
In children and young people under 19 years of age (hereafter referred to as CYP), pituitary adenomas (sometimes referred to as pituitary neuroendocrine tumours or PitNETs) are very much rarer than in adults, especially before puberty. In CYP, pituitary adenomas can also differ in their characteristics, be more aggressive or more treatment resistant than adenomas in adults and can present as a sign of genetic disease. Thus, their optimal diagnosis and management need multidisciplinary collaboration from both paediatric and adult pituitary specialists. Their rarity precludes a high-quality evidence base for their management. Therefore, the recommendations in this two-part consensus guideline were developed with Appraisal of Guidelines Research and Evaluation Instrument II (AGREE II)1 methodology between 2014 and 2022 to generate a best practice reference document of 74 recommendations for the management of suspected pituitary adenomas in CYP to improve the quality of clinical care and thus health outcomes.
Part 1 of this consensus guideline includes 17 general recommendations on neuroimaging, visual assessment, histopathology, genetics, pituitary surgery and radiotherapy relevant to all types of pituitary adenoma in CYP2."). Here, in Part 2, we detail the 57 recommendations with a total of 69 statements (as some of the recommendations included two or more interrelated statements) pertaining to each adenoma type in CYP: prolactinomas, Cushing disease, growth hormone (GH) excess causing gigantism and acromegaly, clinically non-functioning pituitary adenomas (NFPAs), and thyroid stimulating hormone (TSH)-secreting adenomas (TSHomas) and we also mention the rare functioning gonadotroph adenomas (Supplementary Table 1).
Methodology
For methodology, refer to Part 1 of this publication2."), which includes the summary of the guideline development process and the literature review flowchart. The detailed evidence tables for Part 2 can be found in Supplementary Table 2.
Recommendations
Prolactinomas
Epidemiology and aetiology
Prolactinomas are the most common adenoma type in CYP, occurring in approximately 0.1 million children every year3. However, prolactinomas are exceptionally rare before puberty, when corticotrophinomas are more common. In a series of 136 CYP presenting with pituitary adenomas before 20 years of age, 53% had prolactinomas, but 93% of these presented after 12 years of age. Pituitary adenomas were 3 times4,5,6 to 4.5 times7 more common in female patients than in male patients. Although patients can present with prolactinomas within the first decade of life4,5,8, an adolescent presentation is more typical4,6,7,8,9,10. Median duration of symptom history before diagnosis is 12 months3,11. Of note, macroprolactinomas or giant prolactinomas, which can exert secondary mass effects that compromise growth, puberty and vision, also occur more frequently in CYP than in adults6,12. In a study of CYP with macroprolactinomas, 46% had overweight or obesity at diagnosis and, of these, 23% cited weight gain as one of the reasons for seeking medical advice10. A small percentage of paediatric prolactinomas are related to familial isolated pituitary adenoma or syndromic disease (multiple endocrine neoplasia type 1 syndrome (MEN1), MEN1-like or phaeochromocytoma–paraganglioma-related pituitary disease), even without a known family history13. Therefore, genetic testing should be considered (see Part 1: R11 in ref. 2.")).
Diagnosis: clinical features
Part 2: R1. Offer serum prolactin measurement in CYP presenting with one or more of the following signs and symptoms: delayed puberty; galactorrhoea; visual field loss; growth or pubertal arrest; or girls with menstrual disturbance (strong recommendation, moderate-quality evidence).
High serum levels of prolactin inhibit gonadotrophin secretion via inhibition of the hypothalamic hormone kisspeptin14. Paediatric patients with hyperprolactinaemia might therefore present with delayed (>2 standard deviations (SD) later than mean population age for sex) or arrested puberty, growth failure or short stature, primary amenorrhoea, galactorrhoea, menstrual disturbance or secondary amenorrhoea (in post-menarcheal girls)3,6. Boys might present with gynaecomastia as a result of hypogonadism. Mass effects, occurring more commonly in boys than girls, include headache and visual field loss15. Obesity, gynaecomastia, constitutional delay in growth and puberty in boys, and menstrual disturbance in girls are common physiological variations that are very rarely caused by prolactinoma. However, the cost of measuring prolactin is offset by the benefits of an early diagnosis and timely treatment.
Diagnosis: biochemical evaluation
Part 2: R2. In CYP with signs or symptoms of hyperprolactinaemia, offer prolactin measurement in a single blood sample collected at any time of day (strong recommendation, high-quality evidence).
Part 2: R3. Consider investigating modestly elevated serum prolactin levels by serial measurements over time to exclude the effect of stress and prolactin pulsatility (moderate recommendation, low-quality evidence, Delphi 87%).
A single prolactin measurement taken at any time of the day is sufficient to assess hyperprolactinaemia16,17. As prolactin secretion also rises in response to stress, in patients with elevated baseline prolactin (up to five times of the upper limit of normal18), sampling can be repeated on a different day with two or three samples at 20–60 min intervals, using an indwelling cannula, to differentiate stress-related hyperprolactinaemia from organic disease16,18.
Part 2: R4. The diagnosis of hyperprolactinaemia in CYP requires age-specific and sex-specific prolactin reference ranges and the exclusion of confounding conditions such as hypothyroidism, renal and/or hepatic impairment, and use of medications that cause hyperprolactinaemia (strong recommendation, moderate-quality evidence).
Serum prolactin concentrations vary with age and sex. They are highest in the first 2 years of life and fall to a nadir in mid-childhood, to rise again in adolescence when they are higher in girls than in boys. Paediatric cohort studies of prolactinomas report diagnostic serum prolactin concentrations usually above 4,000 mU/l (188 µg/l)4,8,10, although lower levels can be seen in patients with microprolactinomas3. To rule out mixed prolactin and GH hypersecretion, age-dependent and sex-dependent insulin-like growth factor 1 (IGF1) evaluation should always accompany prolactin assessment in CYP with prolactinomas.
Unexplained, persistently mildly or moderately elevated prolactin in blood samples taken after rest could be due to the stalk effect (disconnection hyperprolactinaemia, pituitary stalk compression from mass lesions disrupting the dopaminergic inhibition of lactotroph cells). In adult patients with stalk effect, prolactin levels are reported above the normal range but not higher than 2,000 mU/l; 94 µg/l (ref. 19) or six times above the upper limit of normal18. Even if no corresponding symptoms of hyperprolactinaemia, hypopituitarism or a pituitary mass are observed, pituitary imaging should be considered. If hyperprolactinaemia is due to a pituitary mass, baseline and dynamic pituitary assessment can identify a potential lack or excess of other anterior pituitary hormones.
Severe primary hypothyroidism can be accompanied by hyperprolactinaemia, probably due to compensatory thyrotropin-releasing hormone hypersecretion and pituitary hyperplasia; care should be taken to distinguish such pituitary enlargement from a true prolactinoma20,21. Severe and prolonged primary hypothyroidism in children can disrupt kidney and liver function as well as delay growth and puberty. In a large cohort of 2,848 adults, hyperprolactinaemia was reported in 43% of women and 40% of men presenting with frank primary hypothyroidism, in 36% of women and 32% of men with subclinical hypothyroidism, and only in around 2% of euthyroid individuals21. Hyperprolactinaemia is reported in 30–65% of adult patients with chronic kidney disease due to increased prolactin secretion and reduced renal clearance22. Severe liver disease is also associated with hyperprolactinaemia in adults18. Intracranial hypotension can cause hyperprolactinaemia18. Although we could find no parallel data describing the prevalence of hyperprolactinaemia in these clinical scenarios in CYP, the Guideline Development Group (GDG)2.") recommends the exclusion of confounding diseases. Up to 80% of patients with tetrahydrobiopterin deficiencies (a group of rare neurometabolic disorders characterized by insufficient synthesis of monoamine neurotransmitters, including dopamine) can have hyperprolactinaemia (10–30 fold elevation of prolactin), usually from the teenage years; development of a microprolactinoma has been also described in case reports23) deficiencies. Orphanet J. Rare Dis. 15, 126 (2020)."),24."). While less likely in the CYP population, pregnancy should not be overlooked as a cause of hyperprolactinaemia18.").
Medications are one of the most common causes of hyperprolactinaemia in adults through direct prolactin stimulatory pathways or by antagonizing inhibitory dopaminergic tone25. Medication-induced hyperprolactinaemia is also well described in CYP (Supplementary Table 3). The role of synthetic oral oestrogens (for example, contraceptive pills) in causing mild elevation of prolactin is controversial.
Part 2: R5. Assess baseline macroprolactin levels where serum prolactin is found to be mildly or incidentally elevated (strong recommendation, low-quality evidence, GDG consensus).
In addition to monomeric prolactin (23 kDa), dimeric (48–56 kDa) and polymeric (>100 kDa) forms (usually associated with an antibody) can circulate (‘macroprolactin’, which has low biological activity), with or without excess monomeric prolactin. No routine assays distinguish between monomeric prolactin and macroprolactin; therefore, prompt and appropriate secondary analysis should be undertaken to detect the possible presence of macroprolactin in the initial investigation of asymptomatic CYP with hyperprolactinaemia26,27. In large retrospective cohorts of adults with hyperprolactinaemia, macroprolactinaemia was present in 10–40% of individuals with hyperprolactinaemia17,26,27, 20% of whom had galactorrhoea, 45% oligo-amenorrhoea and 20% pituitary adenomas. Few patients with macroprolactinaemia are reported in the paediatric literature. In a cohort of five patients aged 11–18 years with an incidental finding of hyperprolactinaemia due to macroprolactinaemia, none developed clinical features of prolactin excess during an observation period ranging from 3 months to 8 years28. In another report, one of six CYP with macroprolactinaemia was asymptomatic; the other five had either headache, menstrual disturbance, short stature, increased hair growth or early puberty. Four of those with symptoms underwent pituitary MRI and a microadenoma was identified in two (one with headache and one with oligomenorrhoea)29. Given these data and the current widespread clinical practice6, the GDG strengthened R5.
Part 2: R6. Perform serial dilutions of serum for prolactin measurement in CYP with large pituitary lesions and normal or mildly elevated prolactin levels (strong recommendation, moderate-quality evidence).
Serum prolactin levels directly correlate with prolactinoma size and are important markers of treatment response. Based on adult data, approximately 5% of patients with macroprolactinomas and a paradoxically modest serum concentration of hyperprolactinaemia have grossly elevated prolactin concentrations following serum dilution30. When prolactin is measured in two-site immunoradiometric assays, very high concentrations of prolactin could saturate the signalling antibody, making it less available for binding to the coupling antibody, resulting in artificially low measurements16. This phenomenon has been described as the ‘high-dose hook effect’30 and is well recognized. Some prolactin assay manufacturers have put specific mitigating factors in place, such as large linear ranges or automatic dilution steps, in many modern assays. However, the potential remains for this effect to be a source of anomalous results31. Thus, contact with the clinical biochemist to request manual dilution is advised when a discrepancy exists between a large pituitary adenoma on imaging and only modestly elevated prolactin concentrations on initial biochemistry. Of note, inconsistent symptoms and laboratory results can occasionally arise due to biotin exposure or heterophilic anti-animal antibodies18.
Treatment
Part 2: R7. In CYP with prolactinoma, offer a dopamine agonist as first-line therapy to reduce serum prolactin concentrations and induce tumour shrinkage; cabergoline is the dopamine agonist of choice given its superior effectiveness and lower adverse effect profile (strong recommendation, moderate-quality evidence).
Part 2: R8. In CYP with prolactinoma, offer cabergoline as first-line therapy, even in the presence of visual disturbance and pituitary apoplexy, while carefully monitoring for any deterioration in vision, pituitary function or general status (strong recommendation, low-quality evidence, Delphi 100%).
Dopamine agonists reduce pituitary-origin hyperprolactinaemia of any cause18. In adults with prolactinoma, dopamine agonists induce normalization of the prolactin level (median: 68% of patients; range: 40–100%), tumour shrinkage (62%; 20–100%), resolution of visual field defects (67%; 33–100%), normalization of menses (78%; 40–100%), fertility (53%; 10–100%) and sexual function (67%; 6–100%), and resolution of galactorrhoea (86%; 33–100%)11,32,33. In both adults and CYP with prolactinoma, cabergoline is the dopamine agonist of choice3,11,12. Cabergoline has a longer half-life and greater affinity for the dopamine receptor than other dopamine agonists. In a randomized controlled trial of adult women with prolactinoma, cabergoline was superior to bromocriptine in normalizing prolactin (83% versus 59%), resuming ovulatory cycles or achieving pregnancy. Adverse events were more commonly reported with bromocriptine than with cabergoline (72% versus 52%)34.
In studies of CYP with prolactinomas, dopamine agonists lower prolactin concentrations in 60–70% of patients3,4,8,10,11,35, reduce tumour size by 80–88%3,11, improve visual deficits36, resolve pubertal delay and eliminate headache11. In an observational study of 28 paediatric patients, CYP with prolactinomas smaller than 13.5 mm in diameter (13 patients) achieved normalization of prolactin levels without surgery, using conventional cabergoline doses (up to 2 mg/week)12. Moreover, another series of 22 CYP with prolactinomas reported that all tumours of >20 mm diameter required surgery6. Although successful dopamine agonist discontinuation has been achieved in CYP, younger patients and those with high serum prolactin concentrations at diagnosis (a marker of adenoma size) are less likely to achieve complete remission and euprolactinaemia3,11,37.
Medication-induced shrinkage of prolactinomas that have invaded sphenoid bone can cause rhinorrhoea after a few months of drug administration (mean 3.3 months, range 3 days–17 months) due to a cerebrospinal fluid leak38, but this adverse effect can also occur during long-term treatment. Detection of β2-transferrin or β-trace protein (specific to cerebrospinal fluid) in nasal secretions confirms a cerebrospinal fluid leak39. Cerebrospinal fluid leak can require urgent intervention (for example, lumbar drain or surgical repair), with or without a temporary cessation in dopamine agonist therapy40."). Apoplexy has been described during cabergoline therapy both in adults and CYP6.").
Part 2: R9. For CYP resistant to standard doses of cabergoline, offer graduated dose increments of up to 3.5 mg per week or up to 7 mg per week in exceptional cases (strong recommendation, moderate-quality evidence, Delphi 100%).
Evidence indicates that adult patients with prolactinoma who are unresponsive to standard dopamine agonist doses (up to 1.5–2 mg of cabergoline per week) might respond to higher doses (3.5–7 mg per week), whilst even higher doses (up to 12 mg per week41,42 but below the 21 mg per week dose used for Parkinson disease) have been tried. High-dose cabergoline is reportedly well tolerated and doses of up to 7 mg per week have been used to successfully treat CYP with prolactinoma10,11. However, others report little benefit of cabergoline doses above 3.5 mg per week in adults41. Patients with cabergoline resistance or intolerance will require adjuvant therapy with surgery or radiotherapy42.
Part 2: R10.1. Following multidisciplinary discussion, for CYP with prolactinomas offer surgery when the patient is unable to tolerate or is resistant to high-dose cabergoline (strong recommendation, low-quality evidence, Delphi 95%).
Part 2: R10.2. Following multidisciplinary discussion, for CYP with prolactinomas offer surgery when the patient develops deteriorating vision on cabergoline (strong recommendation, low-quality evidence, Delphi 90%).
Part 2: R10.3. Following multidisciplinary discussion, for CYP with prolactinomas offer radiotherapy if surgery is not an option (strong recommendation, low-quality evidence, Delphi 100%).
Small nocturnal dose increments of cabergoline can effectively diminish the adverse effects of gastrointestinal intolerance and postural hypotension, thereby avoiding trials of less effective dopamine agonists (bromocriptine or quinagolide). Dose-independent psychological intolerance (mood changes, depression, aggression, hypersexuality and impulse control disorder) is similar between agents and described in adults as well as CYP37,43, but the frequency of these adverse events might be higher in CYP than in adults11,44. Dopamine agonist resistance is usually defined in adults and CYP as failure to achieve normoprolactinaemia (biochemical resistance) and less than 50% reduction in tumour area in the coronal plane and/or less than 30% reduction of the longest diameter of the tumour (tumour size resistance, assessed by Response Evaluation Criteria In Solid Tumours (RECIST) criteria) after 3–6 months of maximally tolerated dopamine agonist doses (at least 2 mg per week)18,41,45,46. In a paediatric macroprolactinoma cohort of patients who were unresponsive to 3 months of 15 mg per day bromocriptine, 600 µg per day quinagolide or 3.5 mg per week cabergoline, 26% were biochemically resistant and 24% were tumour-shrinkage resistant10. This resistance directly correlated with tumour size and prolactin levels (which in turn were closely correlated) but was independent of MEN1 mutation status10.
In CYP with prolactinoma, neurosurgical intervention should be considered if vision deteriorates or does not improve on medical therapy or if dopamine agonist resistance, escape or intolerance occurs. Careful multidisciplinary discussion is needed if the patient expresses a preference for surgery rather than long-term medication or is non-adherent to the latter.
Transsphenoidal surgery induced remission in 30–50% of adults with prolactinomas and any residual post-operative hyperprolactinaemia was subsequently more responsive to dopamine agonists than pre-operatively47. Tumour size negatively predicted surgical remission rates, with smaller adenomas being more often cured by surgery alone than larger ones47,48. Paediatric series report lower surgical remission rates than in adults, most likely due to the higher incidence of proportionately larger prolactinomas in CYP, as well as a possible higher frequency of new and permanent pituitary hormone deficiencies after surgery43,49,50,51,52. In adults with microprolactinomas or intrasellar macroprolactinomas, surgery is a viable option with an excellent cure rate (83% in microprolactinomas and 60% in macroprolactinomas), especially in high-volume surgical centres, and is certainly an alternative to long-term cabergoline therapy18,53.
Radiotherapy should be reserved for exceptional patients with a growing prolactinoma and where other treatment modalities are not available or have been exhausted; the main indication for radiotherapy is control of tumour growth, whereas normalization of prolactin levels is a secondary objective2."). After radiotherapy, initially 6-monthly and later 12-monthly follow-up should monitor for the development of hypopituitarism or recurrence. The detailed assessment and treatment of hypopituitarism in CYP is beyond the scope of these guidelines.
Part 2: R11. In CYP with prolactinoma, offer an echocardiogram at the start of treatment with a dopamine agonist; offer yearly surveillance echocardiography for patients receiving >2 mg per week cabergoline and every 5 years if on ≤2 mg per week (moderate recommendation, moderate-quality evidence).
High-dose and long-term use of dopamine agonists in Parkinson disease pose a recognized risk of cardiac valve regurgitation; however, the doses used in treating prolactinomas are notably lower. A meta-analysis that identified an increased prevalence of echocardiographic tricuspid regurgitation in adults was heavily influenced by a single study, with no reports of increased clinical valvular disease54. A subsequent population-based, matched control cohort study in adults failed to identify an excess in hard clinical cardiac endpoints55. Nevertheless, the long-term cardiac safety of ergot-based dopamine agonists in CYP requires a balanced judgement against the increasing background rate of cardiac valvulopathy that occurs with age and the often more aggressive nature of prolactinomas in the paediatric age group, who require longer treatment durations and higher cumulative doses than adults. The relative contributions of peak versus cumulative doses of dopamine agonists in the aetiology of valvulopathy are unknown. In adults with Parkinson disease and moderate-to-severe valvulopathy, the mean cumulative cabergoline dose was 4,015 mg, with one SD below the mean being 720 mg (ref. 56), yet a critical cumulative dose threshold could not be established56. Similar respective cumulative doses in CYP with prolactinoma would require 39 years (4,015 mg) or 7 years (720 mg) of 2 mg per week cabergoline treatment. To date, valvulopathy in CYP treated with dopamine agonists for hyperprolactinaemia has not been reported. A 2019 position statement for adults with prolactinomas treated with dopamine agonists recommends pre-treatment baseline and annual echocardiography with cardiac auscultation for those on >2 mg per week of cabergoline, reduced to 5-yearly echocardiographic surveillance if the cabergoline dose is ≤2 mg per week57. Until data specific to CYP emerge, following these recommendations (endorsed by three relevant UK professional societies56) seems prudent.
Part 2: R12. Temozolomide treatment might need consideration for CYP with aggressive pituitary tumours resistant to medical, surgical and radiation therapy (weak recommendation, low-quality evidence, Delphi 88%).
Temozolomide treatment for aggressive pituitary tumours and pituitary carcinomas is well described in the adult pituitary literature58. These entities are extremely rare in CYP: four patients with pituitary carcinomas are reported to have had disease commencing in childhood59,60,61,62. The 2017 European Society of Endocrinology guideline recommends first-line temozolomide monotherapy for aggressive pituitary tumours and pituitary carcinomas unresponsive to standard therapies, with evaluation of responders and non-responders after three cycles of 150 mg/m2 per day for 5 days in every 28 days, with dose increases to 200 mg/m2 per day in patients with good tolerance63. A minimum of 6 months of treatment is recommended for responding patients. Five paediatric patients receiving temozolomide treatment for pituitary tumours were identified in the literature, with two more paediatric-onset patients receiving temozolomide as adults (Table 1).
Follow-up and surveillance
Part 2: R13. If the serum level of prolactin has been normalized for at least 2 years on medical therapy and there is no visible residual prolactinoma on MRI, consider gradual cabergoline dose reduction to maintain normoprolactinaemia and eventual treatment discontinuation, with continued serum prolactin monitoring for at least 2 more years (moderate recommendation, low-quality evidence, Delphi 100%).
The relapse rates of prolactinomas in CYP treated with dopamine agonists are not reported. The Endocrine Society guideline for the treatment of hyperprolactinaemia in adults recommends a trial of therapy discontinuation in those patients with no tumour remnant on MRI and normoprolactinaemia after 2 or more years of medical treatment18. Studies report variable (26–89%) hyperprolactinaemia recurrence rates under these conditions, largely within the first 2 years of treatment withdrawal18,64. Discontinuation might also be attempted with normoprolactinaemia and a small tumour remnant51.
Two meta-analyses have examined factors associated with relapse following treatment withdrawal in patients with prolactinoma treated with dopamine agonists. The first (19 studies, 743 patients) concluded that both the use of cabergoline and treatment for more than 2 years were associated with a decreased relapse rate65. The second (11 studies, 637 patients) found that tapering doses prior to withdrawal reduced the risk of relapse but that treatment beyond 2 years had no further beneficial effect66.
CYP with prolactinomas should be monitored clinically (including assessment of growth, puberty, galactorrhoea, menstrual history, gynaecomastia or loss of libido in puberty) and biochemically by measurement of serum prolactin. For macroprolactinomas, MRI should be repeated 3–6 months after starting cabergoline treatment; for microprolactinomas, re-imaging depends on clinical and biochemical follow-up; imaging is suggested before considering cabergoline withdrawal18. Longer-term imaging frequency depends on symptoms, biochemical control and the closeness of the pituitary mass to the optic chiasm18. One observational study (including 11 CYP) reported low bone mineral density (BMD) at diagnosis with modest degrees of recovery after 2 years of dopamine agonist therapy. Assessment of BMD 2 years after diagnosis might be important in patients with prolactinoma67; however, the inevitable negative impact of delayed growth and puberty on peak bone mineral accrual will confound definitions of ‘osteopenia’ in CYP. Thus, repeated longitudinal assessments require interpretation not only alongside cure rates but also with clinical pubertal staging, additional sex and adrenal hormone replacement, and at growth completion (epiphyseal fusion) and full pubertal maturation (age 25 years).
The optimal frequency of MRI imaging following cessation of treatment is unknown. Prolactin levels, assessed at 3–6-monthly intervals initially, can be used as markers of tumour relapse, although biochemical relapse is not always accompanied by radiological MRI change.
Cushing disease
Epidemiology and aetiology
Cushing disease is caused by an adrenocorticotropin (ACTH)-secreting pituitary adenoma and is the most common form of ACTH-dependent Cushing syndrome, yet it is rare in CYP. The incidence is approximately 10% of that in adults, of ~0.5 new patients per million individuals per year68. Cushing disease accounts for 75–80% of CYP with Cushing syndrome, compared with 49–71% of adults69,70. In fact, corticotroph adenomas are the most common pituitary adenoma diagnosed in early childhood (55% of pituitary adenomas in those aged 0–11 years; 30% in those aged 12–17 years)7, with mean age at presentation of 12.3 ± 3.5 years (mean ± SD; range 5.7–17.8)71. An overall male predominance exists in CYP, with 63% of patients with paediatric Cushing disease being boys compared with 79% of patients being female in adult series. This discrepancy is driven by prepubertal male predominance (71%)72. Boys with Cushing disease tend to have more aggressive disease with elevated BMI, shorter height and higher plasma ACTH levels than girls73. At all ages, microadenomas are the most common cause of Cushing disease, accounting for 98% of cases in CYP, with the adenoma diameter frequently being ≤2 mm (refs. 7,68,72,74). Macroadenomas, often showing invasion of the cavernous sinus, are rare in CYP (2–5% CYP versus 10% of adults with Cushing disease)75. Genetic associations are described in Part 1 (ref. 2.")).
Diagnosis: clinical features
Part 2: R14. Offer screening for Cushing syndrome in CYP with obesity but only if weight gain is inexplicable and combined with either a decrement in height SD score (SDS) or height velocity (strong recommendation, moderate-quality evidence).
The clinical features of Cushing disease in CYP are well documented69,73,74,76,77,78 and demonstrate interesting differences compared with adult patients72. CYP might show growth failure (subnormal growth velocity), with respective short stature and weight gain (height SDS below and BMI SDS above the mean for age and sex)69,72,74,78,79. Yet, not all CYP with Cushing syndrome have obesity and few patients with obesity prove to have Cushing syndrome80. Consensus statements advise that only CYP with unexplained weight gain and either growth rate deceleration or decrement in height centile over time require investigation, as this combination of features has a high sensitivity and specificity for Cushing syndrome in CYP81,82. The presence of growth failure sensitively discriminates simple obesity from Cushing syndrome in prepubertal CYP83 but is an unreliable indicator in post-pubertal CYP, who require assessment according to adult guidelines82.
Diagnosis: biochemical investigations
Part 2: R15. In CYP with suspected Cushing syndrome, offer investigations using established algorithms, first to determine the diagnosis of Cushing syndrome (the presence of hypercortisolaemia), followed by investigations to ascertain its aetiology (strong recommendation, moderate-quality evidence).
The biochemical investigation of children with suspected Cushing syndrome has been extensively reviewed69,76,81,84,85. The algorithms for testing consist initially of confirmation or exclusion of the diagnosis of hypercortisolaemia and then investigations to determine its aetiology81.
Part 2: R16. Suspected Cushing syndrome in CYP is effectively excluded by either two normal 24-h urinary free cortisol (UFC) measurements and a normal low-dose dexamethasone suppression test (LDDST; 0.5 mg 6-hourly for 48 h or, if patient weight is <40 kg, 30 µg/kg per day for 48 h); or a midnight sleeping serum cortisol concentration of <50 nmol/l (strong recommendation, high-quality evidence).
Part 2: R17. Two late-night salivary cortisol tests could be a useful alternative for the midnight serum cortisol test as a means of excluding Cushing syndrome, but age-specific and assay-specific normal ranges are not currently available and need to be carefully characterized (moderate recommendation, moderate-quality evidence).
Diagnosis of hypercortisolism usually includes three tests: dexamethasone suppression testing, 24-h UFC, and late-night salivary or sleeping midnight serum cortisol level (Table 2). None of these tests has 100% diagnostic accuracy and each test has some limitations86. It is important to eliminate the effect of exogenous glucocorticoids before biochemical testing.
Dexamethasone suppression testing can be either standard 48-h LDDST or overnight dexamethasone test (25 μg/kg at 11:00 h or midnight, maximum dose 1 mg). The 1 mg overnight dexamethasone suppression test is now routine in adults82 but considerably less data are available in children, where this test has lower sensitivity86,87. Both the 48-h and the overnight dexamethasone tests can be influenced by diarrhoea or coeliac disease, or by medications that increase cortisol-binding globulin levels or influence CYP3A4 activity. Measurements of serum dexamethasone can be used to ensure appropriate blood levels, but data for children are lacking and dexamethasone assays are not widely available. Repeated 24 h UFC measurements in the normal range (corrected for body surface area, micrograms per metre squared per 24 h) can support the lack of hypercortisolism. Physiological increases in UFC excretion can occur in girls in the peri-menarcheal phase. Limitations of the UFC test include difficulties in accurately and repeatedly collecting urinary samples in young children and lower sensitivity in milder cases of hypercortisolism and in severe kidney dysfunction. A sleeping midnight serum cortisol measurement has high sensitivity (94–100%) and specificity (100%) for Cushing disease. The test needs an overnight stay in the hospital and the patient needs to be asleep at the initiation of sampling. By contrast, a late-night salivary cortisol test is easy and cost-efficient, with high sensitivity (93–100%) and specificity (95–100%), but lacks age-specific and assay-specific normal ranges.
Clinical suspicion of Cushing syndrome but normal biochemical test results could rarely be due to periodic Cushing syndrome. In these patients, multiple, periodic, sequential late-night salivary cortisol tests can be helpful in detecting episodes of cortisol excess longitudinally82.
Part 2: R18.1. In CYP with confirmed Cushing syndrome, Cushing disease can be confirmed by its ACTH dependency, which is supported by a normal or elevated 09:00 h plasma ACTH (strong recommendation, moderate-quality evidence).
Part 2: R18.2. In CYP with confirmed Cushing syndrome, the diagnosis of pituitary-origin ACTH excess is supported by >20% increase in cortisol from baseline during a corticotrophin-releasing hormone (CRH) test (moderate recommendation, low-quality evidence, Delphi 92%).
Following confirmation of hypercortisolism, the priority is to determine its cause. Cushing disease is most easily confirmed by determination of basal (morning, 08:00–09:00 h) plasma ACTH. In all patients with Cushing disease, ACTH is detectable (>5 ng/l (>1.1 pmol/l); Table 2). In the presence of confirmed hypercortisolism, using a cut-off value of 29 ng/l (6.4 pmol/l), ACTH has a 70% sensitivity and 100% specificity for diagnosing Cushing disease85. Based on adult data and guidelines, in ACTH-independent Cushing syndrome, ACTH is always low and usually undetectable.
High-dose dexamethasone suppression tests (HDDST; 80–120 μg/kg, maximum 8 mg) are no longer necessary in the routine investigation of Cushing disease given that, in CYP (as in adults), >30% cortisol suppression during LDDST (but still above 50 nmol/l) correlates with HDDST results and strongly supports the diagnosis of Cushing disease. Furthermore, CYP with ectopic ACTH-secreting tumours might show cortisol suppression on HDDST, while the HDDST itself can induce transient hypertension and hyperglycaemia in CYP76,86,88,89,90. Therefore, many centres have abandoned HDDST. A CRH test using human sequence CRH (1 µg/kg intravenously) is recommended to support the suspected diagnosis of Cushing disease; in 92% of paediatric patients with Cushing disease (36 of 39 patients), serum cortisol level increased by >20% (range 2–454%) in response to CRH72. Ectopic ACTH syndrome is so rare in children that the need for a CRH test is questionable, although a cortisol increase of >20% to CRH has a 97.5% sensitivity and 100% specificity for Cushing disease and can contribute to the diagnosis85. As the availability of CRH is not universal, desmopressin (10 µg intravenous) has been used in CYP for bilateral simultaneous inferior petrosal sinus sampling (BSIPSS), with similar cut-off ratios to the CRH test91,92. A recommended protocol for the diagnosis of Cushing disease in CYP is shown in Table 2. All tests need to be interpreted in the light of the pre-test probability of the disease being present.
Diagnosis: neuroimaging and BSIPSS
In CYP with suspected Cushing disease, pre-operative MRI to localize the pituitary adenoma is strongly recommended, although only 50–63% of corticotroph adenomas were identified on post-contrast images in several large paediatric series72,85,93. This poor visualization rate in children could be explained by the limited spatial resolution of MRI, making small lesions within a small pituitary gland inconspicuous. Therefore, pituitary MRI imaging alone cannot reliably predict the adenoma position or confirm the diagnosis of Cushing disease in CYP.
Part 2: R19.1. Offer BSIPSS to CYP with confirmed ACTH-dependent Cushing syndrome and no identified adenoma on pituitary MRI to confirm a central source of ACTH excess (strong recommendation, low-quality evidence, Delphi 83%).
Part 2: R19.2. Offer BSIPSS only in a specialist centre with expertise in such testing and by an experienced interventional radiologist who regularly undertakes this procedure in adults (strong recommendation, moderate-quality evidence).
Part 2: R19.3. Consider confirming hypercortisolaemia immediately prior to BSIPSS to ensure the patient is in an active disease phase (moderate recommendation, moderate-quality evidence).
Part 2: R19.4. During BSIPSS, a pituitary source of ACTH excess is confirmed by a ≥2:1 ratio of central-to-peripheral ACTH before CRH or desmopressin and ≥3:1 ratio after CRH or desmopressin stimulation (strong recommendation, low-quality evidence, Delphi 100%).
Part 2: R19.5. BSIPSS could provide some information on tumour lateralization if the inter-petrosal sinus ACTH gradient after CRH or desmopressin stimulation is ≥1.4 between the two sides (moderate recommendation, moderate-quality evidence, Delphi 67% and GDG consensus).
BSIPSS was initially piloted in adults at the National Institute of Health (NIH)94 to enable distinction between Cushing disease and ectopic ACTH syndrome. In adult practice, BSIPSS has become routine unless the MRI unequivocally shows a pituitary adenoma that is unlikely to be an incidentaloma. A pituitary source of ACTH excess confirmed during BSIPSS has a high sensitivity for Cushing disease in experienced centres72,84,93,94,95. Hypercortisolaemia can be confirmed on the morning of the BSIPSS procedure to ensure the few patients with cyclical Cushing disease80 are in an active phase. BSIPSS using desmopressin as the stimulant has been reported in five paediatric series, with similar accuracy to CRH stimulation91,92. The reliability of the results of BSIPSS and the incidence of adverse events are related to the experience of the radiology team84. To enable the accurate interpretation of the results, medical therapy for Cushing disease (steroidogenesis inhibitors) must be stopped before undertaking BSIPSS; the length of time of treatment discontinuation depends on the half-life of the agent used.
BSIPSS might also help to lateralize pituitary ACTH secretion, where no lesion is visible on MRI81. If, on BSIPSS, the ACTH gradient between the two sides is greater than or equal to 1.4 after CRH (or desmopressin) stimulation, this finding might indicate lateralization of the tumour84,93,94,96,97,98 with possibly greater accuracy in CYP than in adults with Cushing disease75,96. The first paediatric data were reported in a large NIH series, where the predictive value for lateralization was 75–80%69. Similar values have been reported in other smaller series, with surgical concordance of adenoma site in 87–91% of patients75,96. Another NIH study of BSIPSS in 94 paediatric patients reported only 58% concurrence of ACTH lateralization with site of adenoma at surgery, which increased to 70% (51 out of 73) after the exclusion of 18 centrally located and 4 bilateral lesions98. Data from 2021 and 2022 confirm similar95 or higher (87.5%) percentages93. Based on these data, the GDG strengthened R19.5. Theoretically, false lateralization could occur due to altered pituitary blood flow94 but, in adult patients with Cushing disease, despite asymmetric internal petrosal sinuses in 11 of 38 patients (39%), both symmetric (100%) and asymmetric (93%) petrosal sinuses gave good lateralization99. Prolactin measurements during BSIPSS have been reported to be a useful marker of accurate catheterization, but two studies in adult Cushing disease suggested that prolactin-corrected ACTH concentrations did not substantially increase the accuracy of lateralization100,101 and this protocol has not been studied in CYP. Thus, no robust data exist to demonstrate, unequivocally, that lateralization of the tumour on BSIPSS improves surgical outcomes or preservation of residual pituitary function. However, observational studies of CYP suggest that improvements in rates of surgical cure might be related to the introduction of BSIPSS75,96.
Treatment: pituitary surgery
Part 2: R20.1. Offer selective adenomectomy as first-line treatment of choice for CYP with Cushing disease (strong recommendation, moderate-quality evidence).
Part 2: R20.2. Consider repeat surgery for CYP with persistent or recurrent disease (moderate recommendation, low-quality evidence, Delphi 100%).
Optimal treatment for CYP with Cushing disease is surgical resection by selective removal of the adenoma, performed by a surgeon experienced in paediatric transsphenoidal surgery102. Selective removal of the adenoma is now considered first-line therapy, maximizing the potential for normal pituitary tissue to remain in situ7,74,102. Low rates of post-operative hypopituitarism have been reported in several large studies in CYP103,104. However, selective microadenomectomy can be technically very difficult in children and surgeon experience is a predictor of success102,105.
Early post-operative remission in children was associated with identification of the adenoma at surgery, whilst long-term remission correlated with a younger age, a smaller adenoma, the absence of cavernous sinus or dural invasion, and a morning serum cortisol level of <1 µg/dl (<28 nmol/l) after surgery74. Repeat surgery for paediatric Cushing disease resulted in early biochemical remission in 93% of 27 patients74. However, recurrence of Cushing disease in adults has been reported up to 15 years after apparent surgical cure, even in individuals who had very low or undetectable post-operative cortisol levels106,107. Therefore, lifelong follow-up for children treated for Cushing disease is essential.
Treatment: pituitary radiotherapy
Part 2: R21. Offer radiotherapy to CYP with recurrent Cushing disease not amenable to curative surgery (strong recommendation, moderate-quality evidence, Delphi 93%).
A proportion of paediatric patients who undergo transsphenoidal surgery for Cushing disease do not achieve post-operative cure or remission87,108,109. The options for second-line therapy are repeat transsphenoidal surgery, radiotherapy, long-term medical therapy to control hypercortisolaemia and bilateral adrenalectomy. Focal external beam radiotherapy is more rapidly effective in children with Cushing disease than in adults108,109,110 and is often initiated 2–4 weeks after unsuccessful transsphenoidal surgery, when it is clear from circulating cortisol levels that a complete cure has not been achieved102.
Stereotactic radiotherapy, fractionated proton beam and gamma knife approaches have been proposed and utilized in adult Cushing disease. By contrast, over the past decade, fractionated proton beam radiotherapy with ongoing safety data monitoring has become the standard for focal cranial radiation in CYP with brain tumours generally111; however, experience is limited, particularly in children112,113. For fractionated treatment, a total radiation dose of 45 Gy in 25 fractions over 35 days seems effective108,114."). A gamma knife stereotactic radiosurgery study in CYP with Cushing disease used a maximum dose of 50 Gy (range, 33–80) and a margin dose of 25 Gy (range, 12.90–27.1)115."). The rapid effectiveness of these treatments is shown in Table 3; however, long-term data on adverse late effects are needed.
Treatment: medical therapies
Part 2: R22.1. Offer oral medical therapies, such as metyrapone or ketoconazole, to reduce the cortisol burden in CYP with Cushing disease awaiting definitive surgery or the effect of pituitary radiotherapy (strong recommendation, low-quality evidence, Delphi 100%).
Part 2: R22.2. Due to their adverse effects, metyrapone and ketoconazole have a limited role in the long-term treatment of Cushing disease in CYP (strong recommendation, low-quality evidence, Delphi 60% and GDG consensus).
Adrenal steroidogenesis inhibitors, such as metyrapone and ketoconazole, are well tolerated and can be highly effective at reducing cortisol levels, either alone or in combination102. In CYP, these drugs should be prescribed by experienced clinical teams with careful titration (metyrapone: 15 mg/kg every 4 h for 6 doses, alternatively 300 mg/m2 every 4 h, usual dose 250–750 mg every 4 h; ketoconazole for patients over 12 years: initially 400–600 mg per day in 2–3 divided doses, increased to 800–1,200 mg per day until cortisol levels normalize and then reaching a maintenance dose of 400–800 mg per day in 2–3 divided doses). However, hypercortisolaemia control can be lost due to the hypersecretion of ACTH and treatment might not be effective in the long term. Common adverse effects of metyrapone include hirsutism, dizziness, arthralgia, fatigue, hypokalaemia and nausea82. Prolonged usage can lead to hyperandrogenism and advanced bone age in children. Ketoconazole is associated with hepatotoxicity and liver function should be monitored on therapy. Gastrointestinal disturbance and adrenal insufficiency are recognized adverse effects of both therapies.
The GDG refined R22.2 after three rounds of an international Delphi consensus, in which only four individuals had the expertise to respond (voting details are provided in Part 1 (ref. 2."))). Definitive treatments, which allow rapid normalization of subsequent growth and puberty, such as surgery and/or radiotherapy, are currently recommended for the management of paediatric Cushing disease, whilst medical therapies are currently limited87.") and not well studied. Nevertheless, given the rarity of this condition in CYP, the effect of these medical agents on growth, and the importance of normalizing childhood growth and puberty, the GDG felt that, in contrast to adults, where long-term medical therapy might have a place after other treatments have failed82."), their use in CYP should be confined to normalizing cortisol levels in preparation for surgery or while awaiting a biochemical response to radiotherapy.
The effects and safety of osilodrostat, an inhibitor of 11β-hydroxylase (CYP11B1), are currently being evaluated in a small phase II trial in CYP (NCT03708900)116, while the effects of cabergoline117, mifepristone and pasireotide in children are very limited or unknown. Temozolomide treatment has been used in an adult patient with childhood-onset Cushing disease (Table 1).
Part 2: R23. Offer intravenous etomidate treatment in CYP with Cushing disease in an intensive care setting only for the emergency control of severe cortisol excess (strong recommendation, moderate-quality evidence, Delphi 100%).
Intravenous administration of etomidate has successfully controlled hypercortisolaemia in children with severe Cushing disease, who were either too unwell for transsphenoidal surgery or presented with acute unmanageable symptoms, for example, respiratory failure or severe psychosis118. To enable the accurate assessment of surgical response, oral therapies, if feasible, should be stopped before surgery, depending on the half-life of the treatment; for example, for metyrapone, 48 h discontinuation should be sufficient.
Treatment: bilateral adrenalectomy
Part 2: R24. Reserve bilateral adrenalectomy only for CYP with severe refractory Cushing disease or for life-threatening emergencies (strong recommendation, low-quality evidence, Delphi 80% and GDG consensus).
Bilateral adrenalectomy remains a therapeutic option for Cushing disease in life-threatening situations or where transsphenoidal surgery is not possible or not available119. However, corticotroph tumour progression after bilateral adrenalectomy (Nelson syndrome, a potentially life-threatening secondary consequence of bilateral adrenalectomy, in which the pituitary adenoma continues to grow and secrete ACTH) seems to be more frequent in children than in adults and often requires pituitary surgery or radiotherapy120,121.
Follow-up and surveillance
Part 2: R25. Consider dynamic testing for GH deficiency soon after definitive therapy in all CYP in remission from Cushing disease who have not completed linear growth, and closely monitor pubertal progression to identify hypogonadotrophic hypogonadism (moderate recommendation, moderate-quality evidence).
Part 2: R26. Offer prompt initiation of GH replacement to CYP in remission from Cushing disease who are proven GH deficient or fail to show catch-up growth (strong recommendation, moderate-quality evidence, GDG consensus).
Part 2: R27. Consider BMD assessment prior to adult transition in patients at high risk for bone fragility (weak recommendation, low-quality evidence, Delphi 86%).
Growth failure and resultant short stature are almost always present at diagnosis in paediatric patients with Cushing disease69. Virilization from adrenal androgens can lead to pubarche and gonadotrophin-independent pubertal development, accelerating skeletal maturity and further compromising adult height potential122. After normalization of cortisol, CYP with growth retardation should be evaluated for GH deficiency with appropriate dynamic testing and receive early GH replacement therapy given the limited window of opportunity to normalize lean-to-adipose mass ratio, promote catch-up growth and attain their normal adult height84,123,124,125,126,127. Given these data and the current clinical practice86, a randomized controlled trial of early GH treatment in CYP in remission from Cushing disease is unlikely, and the GDG therefore strengthened R26. GH deficiency is well recognized following transsphenoidal surgery124 and pituitary irradiation106,108,109. The challenge is to reverse these adverse effects and maximize growth potential to achieve normal adult height and body composition. One approach is to routinely assess for the possibility of GH deficiency soon (up to 3 months)86 after surgery or radiotherapy and substitute GH at conventional replacement doses (0.025 mg/kg per day), if deficient. Gonadotrophin-releasing hormone analogue therapy can be added to delay puberty and epiphyseal closure. Results demonstrate that this regimen usually enables adequate catch-up growth and adult height within the range of target height for the majority of patients106,128. Combined treatment with GH and aromatase inhibitors to reduce bone maturation induced by oestradiol could also be a therapeutic alternative in pubertal patients129. Normal body composition and BMD are more difficult to achieve128,130. Many CYP with Cushing disease have disturbed timing or progression through puberty and require sex steroid replacement to enhance growth velocity and reverse the suppressant effect of cortisol excess on gonadotrophins122.
Pituitary function following remission
Part 2: R28. To assess possible recurrence, offer to all CYP in remission from Cushing disease 6-monthly clinical examination, 24 h UFC, electrolytes and morning serum cortisol for at least 2 years and lifelong annual clinical assessment (strong recommendation, low-quality evidence, Delphi 100%).
Pituitary hormone deficiencies are common after surgical or radiotherapeutic cure of Cushing disease106,109,131. GH deficiency is the most frequent pituitary deficit (see previous section), although recovery in adult life has been reported106,132. During long-term follow-up of patients in remission, gonadotrophin secretion is generally preserved, with normal or true gonadotrophin-dependent early puberty occurring, the latter being well recognized after cranial radiotherapy. After radiotherapy, additional anterior pituitary deficiencies (TSH and permanent ACTH deficits) can rarely develop, typically occurring in combination106,132, with the risk of anterior pituitary hormone deficiencies potentially increasing over time84.
Psychiatric and neurocognitive effects
Part 2: R29. In addition to lifelong follow-up for endocrinopathies, consider long-term monitoring for psychiatric and neurocognitive co-morbidities following remission of Cushing disease in CYP (moderate recommendation, moderate-quality evidence).
Studies of adult patients with Cushing syndrome have reported brain atrophy, cognitive impairment and psychological disease, most commonly depression, associated with excess endogenous circulating glucocorticoids133. A study in 11 patients134 also found considerable cerebral atrophy in children with Cushing disease at diagnosis but without IQ differences between patients and control individuals. Interestingly, an almost complete reversal occurred of the cerebral atrophy 1 year after cure with transsphenoidal surgery but with a paradoxical decline in cognitive function. Another study shows notable improvements in severe psychiatric and behavioural symptoms after cure; however, long-term cognitive and memory problems were identified in ~25% of patients106 and this observation is consistent with similar cognitive and memory deterioration in adults135. Furthermore, the grey matter volume loss of active Cushing disease reverses 3 months after remission, except in the frontal and temporal lobes, strongly associated with cognition and memory136. Children with Cushing disease experience impaired health-related quality of life, which is not fully resolved at 1 year post-treatment137.
Relapse of Cushing disease
Part 2: R30. In suspected recurrence of Cushing disease in CYP, offer the same stepwise investigations as at first presentation (strong recommendation, low-quality evidence, GDG consensus).
Reported recurrence rates after remission of Cushing disease in CYP vary considerably, from 6% to 40%74,79,106,138, and usually occur within 5 years following definitive treatment. However, relapse can occur later106, and the percentage of patients who relapse increases with time107, suggesting that lifelong follow-up is required. This observation is consistent with data from long-term follow-up in adult patients with Cushing disease107; therefore, the GDG strengthened R30.
GH excess: gigantism and acromegaly
Epidemiology and aetiology
A GH-secreting pituitary adenoma arising from somatotroph cells (somatotrophinoma) is the most common cause of acromegaly in CYP and is usually detectable on a contrast-enhanced pituitary MRI. Rarely, CYP with somatotroph hyperplasia due to McCune–Albright syndrome139, Carney complex140, X-linked acrogigantism141 or GH-releasing hormone-secreting tumours (usually associated with MEN1 syndrome in CYP142,143) have been described. GH excess is rare in CYP. Annual incidence rates of GH excess are estimated to be 3–8 cases per million person-years among children aged 0–17 years old, while annual prevalence rates are estimated to be 29–37 patients per million children aged 0–17 years144. Among surgically treated paediatric pituitary adenomas, 8.8%145 to 21%146 are associated with GH excess, with an age-related increase (6.4% at 0–11 years, 9.1% at 12–16 years and 11.8% at 18–19 years). While there are more male patients with gigantism overall145,147,148, more girls (62%) than boys are diagnosed with gigantism in the CYP age group149.
If GH excess occurs before epiphyseal fusion, the patient develops tall stature or gigantism. The definition of pituitary gigantism is arbitrary150,151 (Box 1). Gigantism can be exacerbated by delayed puberty due to gonadotrophin inhibition by co-secretion of prolactin from the adenoma, hyperprolactinaemia from stalk compression or mass effects causing gonadotrophin deficiency. Gigantism has an identifiable genetic basis in almost 50% of patients currently, so genetic assessment and testing are particularly important in CYP (see Part 1, Genetics section2.")).
Box 1 Definitions of pituitary gigantism in CYP
The following definitions for pituitary gigantism have been used in various studies. GH–IGF1 excess associated with:
Accelerated growth velocity >+ 2 SDS or
Abnormally tall stature defined as + 2 or + 3 SDS above the country-specific, age-appropriate and sex-appropriate mean height or + 2 SDS above the mid-parental height
CYP, children and young people under 19 years of age; GH, growth hormone; IGF1, insulin-like growth factor 1; SDS, standard deviation score.
Diagnosis: clinical features
Part 2: R31. Offer testing for GH excess to CYP with excess height (more than 2 SDS) or consistently elevated height velocity and acromegalic features, with or without delayed or arrested puberty or family history of pituitary adenoma (strong recommendation, moderate-quality evidence, Delphi 100%).
The most prominent clinical feature of GH excess in CYP before epiphyseal closure is increased growth velocity. Serial heights and photographs are useful for timing the onset of disease152.
Ethnicity-adjusted height of >2 SDS above age-adjusted and sex-adjusted normal values or 2 SDS above mid-parental target height, persistently elevated growth velocity (>2 SDS), acral enlargement, headache, visual field defects, pubertal delay, delayed bone age and joint pain are common signs of GH excess in CYP. Other features, typical of adult-onset GH excess, can also develop, including coarsened facial features, prognathism, dental malocclusion, teeth separation, frontal bossing, sweating, kyphosis, insulin resistance and occasionally secondary diabetes mellitus, hypertension, sleep disturbance, sleep apnoea, carpal tunnel syndrome, galactorrhoea, pituitary apoplexy, left ventricular hypertrophy and diastolic dysfunction105,145,149,153,154,155,156,157,158,159,160, while joint hypermobility has occasionally been observed161.
X-linked acrogigantism is characterized by tall stature onset before 5 years (usually before 2 years) in all patients141,147,148,162,163 and disproportionally enlarged hands, feet, teeth separation, acanthosis nigricans, increased BMI and increased appetite141,162. In McCune–Albright syndrome139, early-onset (3 years onwards) GH excess, café-au-lait pigmentation, fibrous dysplasia and precocious puberty (or other hormone excess conditions) are prominent clinical features, while in Carney complex140 typical skin pigmentation, myxomas, testicular and adrenal disease are characteristic, in addition to other pleiotropic manifestations.
Diagnosis: biochemical investigations
Part 2: R32. A diagnosis of GH excess is supported by an elevated serum IGF1 level in relation to the age-adjusted, sex-adjusted and Tanner stage-matched normal range (strong recommendation, moderate-quality evidence).
Elevated Tanner stage-matched and age-adjusted circulating serum IGF1 concentration is a reliable marker for GH excess, but marginal or mild elevation in adolescence, during the peak growth spurt, needs cautious interpretation. IGF1 values might be falsely normal or low in CYP with a GH-secreting adenoma and concurrent severe hypothyroidism, malnutrition or severe infection164,165,166, or might be falsely elevated in CYP without GH-secreting adenoma in poorly controlled diabetes mellitus, hepatic and/or renal failure. Oral oestrogens can also confound detection accuracy by reducing IGF1 generation by the liver167, whilst local Tanner stage-matched, sex-matched and age-matched normal ranges for the IGF1 assay must be established to avoid notable inter-assay variability168.
Part 2: R33. Consider the diagnosis of GH excess in CYP whose serum GH levels fail to suppress below 1 µg/l in response to an oral glucose load (cut-off based on adult population); however, complete suppression of GH can be difficult to achieve in normal adolescence (moderate recommendation, moderate-quality evidence, Delphi 100%).
Algorithms for assessing GH excess in CYP are based on those established in adult patients150,169. In healthy adults, serum levels of GH should be suppressed after an oral glucose load: cut-off GH nadirs are 1 µg/l or, using sensitive GH assays, 0.4 µg/l (refs. 170,171). GH nadir after glucose load in CYP undergoing puberty is sex and pubertal stage specific: the highest levels were observed in mid-puberty (Tanner stage 2–3) in girls more than in boys (mean ± 2 SD GH nadir after 2.35 g/kg, maximum 100 g glucose load: in girls 0.22 µg/l ± 0.03–1.57, in boys 0.21 µg/l ± 0.09–0.48)172. However, an earlier study reported a lack of GH suppression (defined as <1 µg/l following 1.75 g/kg, maximum 75 g glucose load) in approximately 30% of children with tall stature (+3.1 ± 0.8 height SDS)173, rendering the diagnosis of GH excess by these criteria challenging in this patient group. An elevated serum IGF1 concentration, with apparently normal serum GH values, might reflect early disease174. We suggest that biochemical results should be interpreted within a clinical assessment of phenotype that includes height velocity, pubertal stage and bone age.
From adult data, serum IGF1 levels correlate linearly with GH levels only up to 4 µg/l and plateau at about 10 µg/l (refs. 175,176). Baseline GH levels are predictive of surgical outcome (higher GH levels predict a lower likelihood of remission after surgery)177 and are key to monitoring the hormone-producing activity of the adenoma176. Thus, both GH and IGF1 should be monitored at baseline and during follow-up in CYP with GH excess.
Part 2: R34. In CYP with GH excess, offer dynamic pituitary assessment of possible hypofunction and hyperfunction of other anterior pituitary hormones (strong recommendation, high-quality evidence).
Hypofunction of other pituitary hormones caused by tumour mass compression or prolactin co-secretion has been noted in 25–35% of patients with somatotrophinomas105,149. Hypogonadism and consequent bone age delay are particularly relevant to GH excess as they increase the time window for longitudinal growth. Co-secretion of other anterior pituitary hormones is common in both adults and CYP with GH excess. A review of 137 published cases of CYP with acromegaly found that 65% had hyperprolactinaemia at presentation, while half showed both GH and prolactin immunostaining in the adenoma tissue105. Furthermore, 34–36% of CYP with gigantism had prolactin co-secretion in two large cohorts147,149. TSH can also be co-secreted by somatotrophinomas but less frequently than prolactin. Patients require assessment and treatment of complications of GH excess such as glucose intolerance and hypertension.
Part 2: R35.1. Pituitary adenomas can be associated with syndromic diseases; offer clinical evaluation for associated syndromic causes of somatotrophinomas to CYP with GH excess (strong recommendation, low-quality evidence, Delphi 93%).
Part 2: R35.2. Offer biochemical screening for pituitary hormone excess to all CYP with Carney complex, McCune–Albright syndrome, and patients with MEN1 or MEN1-like disease (strong recommendation, high-quality evidence, Delphi 100%).
Several syndromes, including McCune–Albright syndrome, Carney complex, MEN1 or, rarely, MEN1-like diseases (MEN4, MEN5) and phaeochromocytoma–paraganglioma-related pituitary disease2.") can be associated with childhood-onset pituitary adenomas, including GH excess. The biochemical diagnosis of GH excess in the context of such syndromes is identical to sporadic cases of acromegaly139."),141."),147."),149."),151."),178."),179."). In CYP with Carney complex, biochemical alterations of the GH axis without overt clinical acromegaly can often be observed. GH-releasing hormone-secreting pancreatic tumours should also be considered as a cause of GH excess in CYP with MEN1 syndrome142."),143."). GH hypersecretion, usually transient, occurs in 10% of infants and children with neurofibromatosis type 1 and optic pathway hypothalamic gliomas180."); some of these patients have been treated temporarily with somatostatin analogues or pegvisomant180."),181."),182."). GH excess is probably a result of hypothalamic dysregulation of the GH axis. Data on the aetiology of temporary GH excess in CYP with optic glioma, therapeutic interventions, the effects of GH excess on glioma growth itself and the observed evolution from GH excess to GH deficiency remain unexplained and poorly understood. The GDG suggested the establishment of a collaborative neuroendocrine oncology research study to gather evidence for these questions.
Treatment: pituitary surgery
Part 2: R36. Offer surgery to reduce GH burden as the treatment of choice in the majority of CYP with GH-secreting adenomas, even where surgical cure is unlikely (strong recommendation, moderate-quality evidence, Delphi 93%).
Part 2: R37.1. Consider pre-operative medical therapy with somatostatin analogues and/or GH receptor antagonists to rapidly control signs and symptoms and support perioperative airway management (weak recommendation, low-quality evidence, Delphi 75%, GDG consensus).
Part 2: R37.2. Consider pre-operative medical therapy with somatostatin analogues and/or GH receptor antagonists to reduce height velocity, particularly if pituitary surgery is delayed (weak recommendation, low-quality evidence, Delphi 100%).
The goals of any therapy for GH excess include normalization of growth velocity, prevention of excessive height and suppression of IGF1 into the normal range; adenoma shrinkage and visual preservation with potential restoration of other hormone function; and prevention of long-term morbidity. Surgery performed by an experienced neurosurgeon offers the prospect of complete remission and is therefore recommended as the first-line treatment for CYP with gigantism or acromegaly159,183,184,185, as for adults150,186,187,188. Even if remission is thought to be unlikely following surgery, tumour debulking can reduce the circulating GH burden and facilitate more successful medical therapy and/or radiotherapy. In an experienced pituitary neurosurgical unit between 2003 and 2016, the surgical success rate in 17 CYP with GH excess was ~50%189. Re-operation could be considered in patients with notable residual tumour and inadequate response to somatostatin analogue therapy or if considerable tumour re-growth occurs.
A role for somatostatin analogues in safely reducing pre-operative GH levels in adults with macroadenomas, with favourable effects on short-term cure, has been suggested by a systematic review, although long-term outcomes require further study190. Patients with severe cardiac and/or respiratory complications from GH excess might benefit from pre-operative reduction of GH levels. Pre-operatively, patients should be assessed for enlargement of the upper airway soft-tissue structures, including the tongue and epiglottis as well as jaw deformity, to prevent perioperative airway difficulties191,192.
In the absence of prospective trials, factors predicting outcome of surgery in CYP with gigantism or acromegaly are limited, although retrospective studies and case reports suggest that a rapid reduction in growth velocity might be a favourable predictor105,149,153.
In patients with genetic causes of acromegaly, the whole gland could be affected (typically in McCune–Albright syndrome, Carney complex and X-linked acrogigantism). Selective adenomectomy193, radical surgery162 or hypophysectomy139,194 have all been described as surgical approaches in these conditions.
Treatment: medical therapies
Part 2: R38. Offer monotherapy or combination medical therapy in CYP with GH excess and post-operative residual disease (strong recommendation, moderate-quality evidence, Delphi 100%).
Part 2: R39. Assess efficacy of medical treatment in CYP with GH excess by both auxological measurements and serum levels of GH and IGF1 (strong recommendation, moderate-quality evidence, Delphi 100%).
Studies of medical therapy in patients with post-operative residual GH excess have been conducted primarily in adults, although case series and case reports also confirm their utility in CYP105,139,147,149,153,154,155,160,162,195. Adjunctive post-operative long-acting somatostatin analogues reduce serum concentrations of GH to ‘safe’ levels and normalize serum levels of IGF1 in approximately 35% of adult patients with GH-secreting adenoma196 with less predictable tumour shrinkage in up to 40%. Retrospective studies have also confirmed the tumour-shrinking effect of somatostatin analogues in adolescents with gigantism139,147,149,153,162. While no formal dosing recommendation exists for children, the dose of long-acting somatostatin analogues can be titrated to normalize IGF1 levels. In adults, the starting monthly dose of lanreotide autogel is 60 mg and of octreotide-LAR 10 mg whereas, for very young children, the dose needs to be individualized. In CYP with acromegaly, numerous reports of the failure of somatostatin analogues to normalize IGF1, satisfactorily reduce GH levels or initiate tumour shrinkage suggest that treatment resistance is more common in CYP than in adults147,149,156,160,162. CYP with AIP or GPR101 mutations have more aggressive disease and are less responsive to first-generation somatostatin analogue therapy147,149,162, whereas the response to medical treatment in patients with Carney complex and McCune–Albright syndrome is more promising139. The second-generation somatostatin analogue pasireotide has also been used in adult patients with childhood-onset GH excess, with mixed results197,198.
Regardless of the presence or absence of prolactin co-secretion, dopamine agonists (primarily cabergoline) can be used alone in CYP with mild GH excess, co-administered with somatostatin analogues where GH hypersecretion is not adequately controlled, or substituted for the latter where poorly tolerated199,200,201,202. However, the GH-lowering effect of dopamine agonists is only modest105,155,156,160 and doses required in acromegaly are often high (see R11 on cabergoline use).
Several studies and case reports have been published of the GH receptor antagonist pegvisomant normalizing serum IGF1 levels in CYP with acromegaly or gigantism when used in adequate doses105,139,147,149,154,160,162,203,204,205. This medication can suppress growth velocity, a clinical priority in CYP with gigantism, suggesting that earlier introduction could be beneficial. The dose of pegvisomant should be started at 10 mg daily and titrated until serum IGF1 levels normalize. Patients treated with pegvisomant require only IGF1 measurements during follow-up. As pegvisomant has no direct pituitary action, careful radiological tumour monitoring is required. Tumour expansion described during pegvisomant treatment105,152 might represent the natural history of the tumour rather than being secondary to reduced negative feedback from reductions in IGF1. Combination therapy with pegvisomant and somatostatin analogues has also been successfully tried in CYP with GH excess149,203,204,205. Temozolomide therapy has been reported in a CYP patient with a GH-secreting tumour and another with a GH–prolactin co-secreting tumour (Table 1).
Treatment: pituitary radiotherapy
Part 2: R40.1. Offer pituitary radiotherapy to CYP with GH-secreting adenoma and uncontrolled tumour growth and incomplete surgical and medical response, except for patients with skull base fibrous dysplasia (strong recommendation, low-quality evidence, Delphi 75%).
Part 2: R40.2. After radiotherapy in CYP with GH-secreting adenoma, offer intermittent dose reduction or withdrawal of medical therapy to assess radiation efficacy on GH hypersecretion (strong recommendation, low-quality evidence, Delphi 100%).
Radiotherapy might be useful for CYP with gigantism or acromegaly who have post-operative residual tumour bulk and in whom surgery and medical therapy have failed to control GH–IGF1 levels (see Part 1, Radiotherapy section2.")). Conventional conformal, stereotactic and proton beam radiotherapy have all been used successfully to control tumour growth and lower serum GH levels in CYP105."),115."),149."),152."), although adult data indicate that it might take up to 10 years for radiotherapy to be fully effective in suppressing GH206."). Therefore, medical therapy is probably required, at least as a temporary measure, in CYP who receive pituitary radiotherapy. Intermittent interruption of medical therapy for 1–3 months (to allow clearance of the drug) might be required to allow biochemical assessment of the efficacy of radiotherapy. After radiotherapy, at first 6-monthly and later 12-monthly follow-ups should monitor the patient for the development of hypopituitarism or recurrence.
GH excess in the context of McCune–Albright syndrome is typically accompanied by fibrous dysplasia of the craniofacial bones. In one study of patients with this syndrome, 6 of 112 patients, 3 of whom had prior pituitary irradiation, developed a skull base sarcoma139. While a causal link to pituitary radiation is not proven, the risk of sarcomatous transformation is higher in McCune–Albright syndrome than in isolated fibrous dysplasia207. Almost half of the patients with McCune–Albright syndrome are CYP (46%) at the time of diagnosis of GH excess. Given the uncertain transforming effect of GH–IGF1 on dysplastic bone208,209,210, alternative medical and surgical treatments, rather than radiotherapy, might be considered in this condition to control GH excess and preserve vision.
Follow-up and surveillance
Part 2: R41. There is no evidence to suggest that CYP with GH excess require routine screening for colonic polyps during childhood (strong recommendation, low-quality evidence, Delphi 92%).
Part 2: R42. Consider avoiding corrective surgery for jaw, spine and joint abnormalities in CYP with gigantism or acromegaly until GH and IGF1 are at safe levels (weak recommendation, low-quality evidence, GDG consensus).
While good evidence indicates an increased risk of colonic polyps in adults with acromegaly, such data are lacking in CYP, and the Delphi panel returned a 92% consensus against routine colonoscopy in CYP with GH excess.
Bone overgrowth induced by GH excess does not reverse with successful treatment of acromegaly and, while jaw and dental deformity can be troublesome, corrective surgery should be deferred until GH–IGF1 levels are adequately controlled and jaw changes have stabilized211.
Late recurrence of GH excess, up to 10 years after apparent remission, has been described212. Thus, long-term annual serum IGF1 monitoring is necessary with repeat biochemical (oral glucose tolerance tests) and radiological (MRI) assessment if recurrence is suspected. Due to the high rates of persistent post-operative disease in CYP with GH excess, many will receive long-term medical therapy or radiotherapy. Monitoring of their efficacy and adverse effects, together with management of secondary pituitary deficits and medical complications, requires experienced specialist support within a dedicated pituitary multidisciplinary team. Close interaction between paediatric and adult endocrine services is required to coordinate long-term medical care and the transition to adult services.
TSHoma
Epidemiology
TSH-secreting adenomas are extremely rare in children and the literature is limited to case reports. In adults with TSHoma, the incidence has been estimated to be 0.26 cases per million per year; co-secretion of other pituitary hormones occurs in 25–42% of cases213. Co-secretion of GH was also noted in an adolescent with gigantism and secondary hyperthyroidism214.
Diagnosis
Part 2: R43. Consider assessment for TSHoma in CYP with hyperthyroxinaemia and an unsuppressed TSH, particularly in the presence of clinical thyrotoxicosis and neurological or visual deterioration (moderate recommendation, moderate-quality evidence).
Part 2: R44. Consider assessment for thyroid hormone resistance and euthyroid hyperthyroxinaemia in the differential diagnosis of TSHoma in CYP (moderate recommendation, low-quality evidence, Delphi 100%).
Patients with TSHomas present with elevated thyroid hormone levels and unsuppressed TSH, differentiating them from primary hyperthyroidism. Usually, children have symptoms of hyperthyroidism but some are reported to be asymptomatic215. Most TSHomas reported in children have presented as macroadenomas; thus, mass effects can cause optic nerve compression and deficiency of other pituitary hormones215,216,217. Following the diagnosis of a TSHoma, investigation for pituitary hypofunction and hyperfunction with baseline and dynamic pituitary testing is recommended. Prompt treatment of any cortisol, GH or sex steroid deficiency is recommended to optimize surgical, growth and well-being outcomes.
An unsuppressed TSH in the setting of hyperthyroxinaemia can occur due to assay interference and due to genetic causes of euthyroid hyperthyroxinaemia such as familial dysalbuminaemic hyperthyroxinaemia and resistance to thyroid hormone. Of note, a case of TSH-secreting microadenoma and resistance to thyroid hormone in a child has been reported218.
Treatment
Part 2: R45. Consider pre-operative somatostatin analogue treatment to normalize thyroid function in CYP with confirmed TSHoma (moderate recommendation, low-quality evidence, Delphi 73% and GDG consensus).
Part 2: R46. Offer transsphenoidal surgery as the treatment of choice in CYP with TSHomas (moderate recommendation, low-quality evidence, Delphi 93%).
In adults with TSHoma, somatostatin analogues improve the symptoms of thyrotoxicosis, decrease serum-free T4 and TSH concentrations, and can cause pre-operative tumour shrinkage219. In one paediatric patient, somatostatin analogues reduced thyroid hormone levels and tumour size, thereby postponing definitive surgery215,220. Out of 44 patients aged 11–73 years on pre-operative somatostatin analogue treatment, 84% had normalization of thyroid function levels and 61% showed tumour shrinkage221.
Surgery offers a potentially definitive cure. Even partial tumour debulking can be worthwhile in reducing TSH and free T4 levels, decompressing the optic apparatus or improving the effectiveness of subsequent medical therapy216,217,221,222.
Follow-up and surveillance
Part 2: R47. Disease monitoring with regular thyroid function tests and regular MRI surveillance, similar to the protocol described for NFPA, is suggested in CYP with confirmed TSHomas (weak recommendation, low-quality evidence, GDG consensus).
There is no evidence base to inform a surveillance schedule in CYP with TSHoma and the natural history of disease progression is unknown. We therefore suggest a pragmatic approach to biochemical and MRI surveillance to detect secondary hyperthyroidism and to identify those with rapid tumour progression or recurrence early, even if asymptomatic. We suggest monthly thyroid function tests for 6 months after initial treatment but, given the uncertainty regarding tumour progression, biochemical and MRI surveillance should be individualized.
Part 2: R48. Consider pituitary radiotherapy in CYP with post-operative tumour remnant and resistance to medical therapy or relapsing TSHomas if re-operation is not an option (moderate recommendation, low-quality evidence, Delphi 92% and GDG consensus).
If surgery is unsuccessful or contraindicated and the paediatric patient with TSHoma fails to achieve normal thyroid function or shows tumour growth despite somatostatin analogue therapy, radiotherapy could be considered222,223 (see Part 1, Radiotherapy section2.")). After radiotherapy, at first 6-monthly and later 12-monthly follow-ups should monitor for the development of hypopituitarism or recurrence.
Incidentalomas and NFPAs
Epidemiology and aetiology
Clinically non-secreting pituitary adenomas account for 4–6% of all paediatric pituitary adenomas224,225 and for 10% of cases in a surgical series220, in stark difference to adult pituitary patients where NFPAs account for 15–30% of clinically relevant pituitary adenomas and 50–60% of cases in a surgical series226. Depending on case selection criteria, NFPAs represent 13–56% of incidentally discovered pituitary lesions (incidentalomas) in large retrospective radiological series of CYP227,228,229. NFPAs also represent 25% of MEN1-associated pituitary lesions in CYP, and small lesions detected by screening can be seen in patients with AIP variants151,230,231. NFPAs in CYP usually present in the second decade of life, with increasing incidence thereafter9,228,230,232. There is no consistent male or female predisposition9,230,232,233,234,235,236, although a 2019 surgical series in CYP reported a slight female predominance220.
Presentation
CYP with NFPAs, by definition, do not have features of a hypersecretory syndrome. Symptomatic NFPAs are macroadenomas, whereas microadenomas are usually discovered as a coincidental finding on an MRI scan. The clinical features of macroadenomas at presentation result from mass effects on surrounding structures. These include headache, visual field defects, pituitary apoplexy (probably more common than in adult NFPA235,236) with or without mild prolactin elevation, or hypopituitarism manifesting as secondary amenorrhoea, delayed puberty, hypothyroidism, hypocortisolaemia, growth failure and/or hyperprolactinaemia9,220,228,230,232,233,234. Headache, visual impairment and hypogonadism were the most common presenting features in a surgical series in CYP236. Immunohistochemistry for pituitary hormones in 14 NFPAs, from CYP aged 12–19 years, revealed 6 silent plurihormonal tumours, 3 silent lactotrophs, 1 each of a silent gonadotroph and a corticotroph, and 3 hormone-negative tumours (transcription factor staining not reported)236. These proportions are different from those in adult patients, where silent gonadotrophinomas represent the majority of NFPAs. Non-functioning pituitary microadenomas do not usually cause hypopituitarism or visual abnormalities227.
Diagnosis and investigation
Part 2: R49. Identification of a pituitary incidentaloma or NFPA requires exclusion of clinical or laboratory evidence of pituitary hormone hypersecretion (except mild hyperprolactinaemia from pituitary stalk disruption); exclusion of elevation of serum level of α-fetoprotein (AFP) and β-human chorionic gonadotrophin (βHCG) and the absence of other suprasellar and intracranial lesions (strong recommendation, low-quality evidence, Delphi 100%).
Part 2: R50. Offer baseline and dynamic evaluation of pituitary function to assess hypopituitarism and exclude hormone excess in all CYP with suspected NFPA (strong recommendation, low-quality evidence, Delphi 100%).
If a pituitary mass is suspected on MRI, baseline and dynamic pituitary investigations should be undertaken as indicated clinically to confirm the absence of pituitary hormone excess from a functioning adenoma or the presence of hormone deficiency. The MRI appearance of a small Rathke cleft cyst or pars intermedia cyst can present a differential diagnosis for a clinically non-functioning microadenoma. Stalk compression from macroadenomas, or rarely microadenomas237, can cause mild hyperprolactinaemia, usually below 2,000 mU/l (94 µg/l)19.
Intracranial germ-cell tumours, more common in the adolescent age group than NFPAs, can present with similar MRI appearances238,239. AFP and βHCG (markers of germ-cell tumours) should be measured in the serum and, if clinically or radiologically indicated, also in the cerebrospinal fluid240.
Hypopituitarism is common in children with symptomatic non-functioning pituitary macroadenoma9,220,228,230,232,233. Basal and dynamic pituitary assessment is recommended following diagnosis of an NFPA together with prompt replacement therapy of any cortisol, thyroid hormone, sex steroid and GH deficiency to optimize surgical, growth and well-being outcomes. Arginine vasopressin deficiency (also known as central diabetes insipidus) is an extremely infrequent finding at diagnosis of an NFPA unless the tumour has undergone apoplexy9,220,228,230,232,233, and its presence strongly suggests an alternative diagnosis such as a craniopharyngioma, histiocytosis or germ-cell tumour111,240.
Visual deterioration is a well-described presentation of NFPA in CYP9,228,232,233 and an urgent indication for surgery to decompress the optic apparatus if sight is threatened. Thus, early assessment of visual acuity and visual fields is mandated111.
Part 2: R51. There is no evidence to suggest a benefit of routine diagnostic biopsy in CYP of incidental pituitary masses whose radiological features are typical of a pituitary adenoma with no other intracranial abnormalities (strong recommendation, low-quality evidence, GDG consensus).
A pituitary biopsy is not required in clinically non-functioning lesions with MRI appearance strongly suggestive of a pituitary adenoma and no other intracranial abnormality, which remain asymptomatic, without visual or pituitary function compromise, unchanged in size over time, and negative for serum βHCG and AFP. In these patients, the risk of a biopsy harming pituitary function is greater than the likelihood of achieving a ‘tissue’ diagnosis or a diagnosis requiring alternative management240. MRI surveillance should be instituted if the optic apparatus is not compressed.
Treatment
Part 2: R52. Offer treatment to CYP with NFPA only if the patient is symptomatic (hypopituitarism), the visual pathway is threatened or there is interval tumour growth on MRI (strong recommendation, low-quality evidence, Delphi 94%).
Part 2: R53. Offer transsphenoidal surgery as the treatment of choice in CYP with NFPA needing surgical intervention (strong recommendation, high-quality evidence, Delphi 100%).
The majority of non-functioning microadenomas in CYP are asymptomatic and detected incidentally or as part of a screening programme, with little data on their frequency, natural history or complication rates. By contrast, macroadenomas enlarge in over 40% of adult patients at 5 years241, while there are no equivalent data in CYP. Surgical removal of a growing macroadenoma is an effective intervention to prevent further damage to surrounding tissues and cranial nerves9,228,229,230,232,233,234.
Part 2: R54. There is insufficient evidence to recommend medical therapy, including cabergoline, in CYP with NFPA (moderate recommendation, low-quality evidence, Delphi 80%).
No data are available to suggest that medical therapy (for example, dopamine agonists or somatostatin analogues) can induce tumour shrinkage in CYP with NFPA, and these medications are not recommended in adult guidelines. Some inconsistent reports of effectiveness in adults with NFPAs receiving somatostatin analogues242 or dopamine agonists243,244,245 suggest that dopamine agonists might reduce tumour growth in some recurrent cases244,245.
Part 2: R55. Consider second surgery or radiotherapy for CYP with recurrent or symptomatic NFPAs (moderate recommendation, low-quality evidence, Delphi 94% and GDG consensus).
Both surgery and radiotherapy have been used to treat recurrent NFPA9,146,246,247,248 and the optimal treatment modality for CYP is not clear. The specialist age-appropriate pituitary multidisciplinary team should make an individual treatment recommendation, accounting for tumour location and any hypothalamic or cavernous sinus invasion, ease of surgery, and the age of the child. Local tumour control after radiotherapy for NFPA in CYP ranges from 80% to 97%249. After radiotherapy, at first 6-monthly and later 12-monthly follow-ups should monitor for the potential development of hypopituitarism or recurrence. Temozolomide treatment was reported for one childhood-onset hormone-negative tumour (Table 1). Based on results from adults250 and the above data, the GDG strengthened R55.
Follow-up and surveillance
Part 2: R56. Following NFPA surgery in CYP, offer post-operative MRI surveillance at a minimum of 3 and 6 months, and 1, 2, 3 and 5 years after surgery (strong recommendation, low-quality evidence, Delphi 89%).
Part 2: R57. In CYP with incidental NFPAs, offer MRI surveillance for microincidentalomas: at 12 months and, if stable, at 1–2 year intervals for 3 years with gradual reduction thereafter; for macroincidentalomas: at 6 months and, if stable, annually for 3 years with gradual reduction thereafter (strong recommendation, low-quality evidence, Delphi 100%).
Although evidence in CYP following pituitary surgery for NFPAs is lacking, data in adults show a recurrence rate of non-irradiated operated pituitary adenomas of up to 38% of those with a visible residuum on post-operative MRI over a follow-up period of 5 years. A post-operative MRI at 3 months will assess the extent of residual tumour, with a further scan at 6 months to assess for recurrence and, if stable, a gradual reduction in the annual scanning frequency as above, with screening continuing lifelong251,252.
The natural history of NFPA in CYP is unknown and could vary. In adults, macroadenomas tend to have higher growth rates than microadenomas (12.5 macroadenomas grow over 100 patient-years versus 3.3 microadenomas)253. Microadenomas seem to follow a benign course in children227, and follow-up can be gradually reduced and stopped227,228,229. For macroadenomas, we recommend lifelong clinical surveillance (as in adults), with an individualized radiological (MRI) surveillance strategy to identify those with rapid tumour progression or post-operative recurrence early, even if asymptomatic.
Visual surveillance in patients with either operated or incidental macroadenomas should be adjusted to their individual needs. Retrospective pituitary imaging studies in CYP highlight the need to recognize that physiological pubertal pituitary hypertrophy can occur and draw attention to the lack of progression of microadenomas227,228,229. As more comprehensive data on incidentalomas or non-gonadotroph silent tumours in CYP are lacking, we suggest following adult guidelines for follow-up as above251,252. While the radiological surveillance of stable non-functioning microadenomas can cease after 1–3 years, macroadenomas need to be followed in the long term251,252. We suggest a decreasing scanning interval for adenomas proven stable over the years. Concerns regarding repeated gadolinium administration over prolonged imaging follow-up are discussed in the Radiology section of Part 1 (ref. 2.")).
Gonadotrophinomas in CYP
Functioning gonadotroph adenomas are exceedingly rare in CYP. They can result in isosexual precocious puberty or ovarian hyperstimulation syndrome254,255. Germ-cell tumours secreting βHCG can represent a differential diagnostic dilemma as symptoms can overlap with those of functioning gonadotrophinomas. Silent gonadotrophinomas are discussed above.
Conclusions
Children and young people are at a disadvantage compared with adults in accessing age-appropriate, highly specialized pituitary care for pituitary adenomas. The incidence, type, symptomatology, aggressiveness and aetiology of their disease not only differ from that of adults but their impact, treatment choice and timely remediation can carry far greater consequences on the developing body and brain as well as on secondary health, intellectual, visual and psychosocial adult outcomes. These can limit the quality of adult relationships and represent challenges for parenting and employment over a long lifespan. The purpose of these recommendations — the first comprehensive consensus guideline of its kind — is to equalize and optimize health care for CYP with pituitary adenomas, raise awareness of diagnostic and treatment delays with potentially life-limiting complications, and improve access to modern pituitary-specific specialist centres, novel therapies, research and monitoring of long-term health and well-being outcomes. The latter must encompass the transition to adult services; closer integration of paediatric and adult pituitary services and data sets can only benefit CYP.
Key developments have occurred over the past few years regarding the diagnosis and treatment of pituitary adenomas — genetic testing, intraoperative MRI and the introduction of pegvisomant are just a few examples. Due to the rarity of pituitary adenomas in CYP, data have necessarily been gathered from retrospective studies, case series, anecdotal case reports and experience from the adult population for most of the management recommendations we present here and in Part 1 (ref. 2.")) (Supplementary Table 1). Facilitating referral and service pathways so that CYP can access centralized speciality pituitary multidisciplinary advisory panels across the age range and establishing national and international data registries of morbidity outcomes are in the best interest of CYP and vital to informing future best practice recommendations and to improving the long-term quality of life of these children and young people.
Change history
19 February 2024
In the version of the article initially published, an earlier, incorrect version of the Supplementary Information was posted. This has now been amended, and the correct Supplementary Information file now accompanies the online article.
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Acknowledgements
The development of this consensus guideline was sponsored by unrestricted grants from professional societies (The Society of British Neurosurgical Surgeons, Children’s Cancer and Leukaemia Group (CCLG) and British Society for Paediatric Endocrinology and Diabetes), patient support groups (Association of Multiple Endocrine Neoplastic Disorders (AMEND), Success Charity and The Pituitary Foundation) and from Sandoz Pharmaceuticals. All, except Sandoz, were stakeholders. Sandoz supported administrative and travel expenses after the initial seed funding ended and had no role in instigating the endeavour, the development of guideline methodology or the final recommendations. The CCLG provided administrative support throughout the development of these consensus statements and the Royal College of Paediatrics and Child Health (RCPCH) provided advice and appraisal to ensure the process met rigorous AGREE II guideline standards. The CCLG, British Society for Paediatric Endocrinology and Diabetes, AMEND, Success Charity, Society of British Neurosurgical Surgeons or The Pituitary Foundation did not influence the decisions of the Guideline Development Group (GDG) nor the recommendations other than through their roles as stakeholders, as described in the main text. We would like to thank all of the stakeholders who contributed comments to this consensus guideline at various stages of development, including members of the Society for Endocrinology, Society of British Neurological Surgeons, British Paediatric Neurosurgical Group, Royal College of Physicians, British Society for Paediatric Endocrinology and Diabetes, British Society of Paediatric Radiology, RCPCH, British Neuropathology Society, and the Association for Clinical Biochemistry and Laboratory Medicine as well as patient organizations AMEND, Success Charity and the Pituitary Foundation. The GDG would like to thank the Project Board members and Delphi panellists (Supplementary Table 2) and our external peer reviewers for their input into this consensus guideline. The GDG would also like to thank Rosa Nieto Hernandez (Clinical Guidelines Manager) and Helen McElroy (Quality Improvement Committee Clinical Lead for Evidence Base Medicine and Appraisals), both at the Research and Quality Improvement Directorate of the RCPCH, for their advice and appraisal of this consensus guideline at different stages. We also wish to thank Stephen Shalet (University of Manchester UK), William Drake (Queen Mary University of London, London UK), Mark Gurnell (University of Cambridge, Cambridge, UK), Luis Syro (Queen Mary University of London, London, UK), Di Zou (London, UK), Lucas Castro (Queen Mary University of London, London, UK), Sarah Farndon (Great Ormond Street Hospital for Children, London, UK), Mary Dang (Queen Mary University of London, London UK), Amy Ronaldson (Queen Mary University of London, London, UK), Rezvan Salehidoost (Queen Mary University of London, London, UK), Gabriela Mihai (Queen Mary University of London, London, UK) and Benjamin Loughrey (Queen’s University Belfast, Belfast, UK) for their help in updating the literature search, grading the papers from the literature search, reviewing the manuscript and providing administrative support.
Author information
Authors and Affiliations
Centre for Endocrinology, William Harvey Research Institute, Barts and the London School of Medicine and Dentistry, Queen Mary University of London, London, UK
Márta Korbonits, Maralyn R. Druce, Nigel Glynn & Helen L. Storr
2. Alder Hey Children’s Hospital, Liverpool, UK
Joanne C. Blair
3. Department of Endocrinology, Jagiellonian University Medical College, Krakow, Poland
Anna Boguslawska
4. University Hospitals Birmingham NHS Foundation Trust, Birmingham, UK
John Ayuk
5. University Hospital Southampton NHS Foundation Trust, Southampton, UK
Justin H. Davies
6. Neuroradiology, Barts Health NHS Trust, London, UK
Jane Evanson
7. Plymouth Hospitals NHS Trust, Plymouth, UK
Daniel Flanagan
8. The Christie NHS Foundation Trust, Manchester, UK
Claire E. Higham & Nicky Thorp
9. Great Ormond Street Institute of Child Health, University College London, London, UK
Thomas S. Jacques
10. Great Ormond Street Hospital for Children NHS Foundation Trust, London, UK
Thomas S. Jacques & Helen A. Spoudeas
Sheffield Children’s and Sheffield Teaching Hospitals NHS Foundation Trust, Sheffield, UK
Saurabh Sinha
12. The Leeds Teaching Hospitals NHS Trust, Leeds, UK
Ian Simmons
13. Norwich and Norfolk NHS Foundation Trust, Norwich, UK
Francesca M. Swords
14. University College London Hospitals NHS Foundation Trust, London, UK
Helen A. Spoudeas
Contributions
All authors researched data for the article. M.K., J.C.B., J. A., J.H.D., J.E., D.F., C.E.H., T.S.J., S.S., I.S., M.R.D., N.G., N.T., F.M.S., H.L.S. and H.A.S. contributed substantially to discussion of the content. M.K., J.C.B., A.B., J.H.D., J.E., T.S.J., S.S., I.S., N.T., H.L.S. and H.A.S. wrote the article. All authors reviewed and/or edited the manuscript before submission.
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Correspondence to
Márta Korbonits.
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Competing interests
M.K. received grant funding or served on the Advisory Board for Pfizer, Crinetics, Novo Nordisk, Recordati, and ONO Pharmaceuticals and honoraria from Ipsen, Corcept, Sandoz and Novo Nordisk. J.C.B. has received honoraria, funding and travel bursaries from Novo Nordisk and honoraria from Sandoz and Ipsen. J.H.D. has received travel bursaries from Sandoz, Pfizer, and Novo Nordisk and grant funding from Pfizer. T.S.J. is director and shareholder in Repath Ltd. and Neuropath Ltd. and received an honorarium from Bayer. H.L.S. received grant funding from Ipsen and Sandoz and consultancy fees from Novo Nordisk, Pfizer and Springer. H.A.S. has received honoraria from Ferring and Pfizer and grants from Novo Nordisk and Sandoz. The other authors declare no competing interests.
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Nature Reviews Endocrinology thanks Bing Xing and the other, anonymous, reviewers for their contribution to the peer review of this work.
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Disclaimer Health-care providers need to use clinical judgment, knowledge and expertise when deciding whether it is appropriate to apply these guidelines. The recommendations cited here are a guide and might not be appropriate for use in all situations. The decision to adopt any of the recommendations cited here is the responsibility of the treating clinician and must be made in the light of individual patient circumstances, the wishes of the patient and their family, clinical expertise, and resources.
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Korbonits, M., Blair, J.C., Boguslawska, A. et al. Consensus guideline for the diagnosis and management of pituitary adenomas in childhood and adolescence: Part 2, specific diseases.
Nat Rev Endocrinol 20, 290–309 (2024).
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This article is cited by
Pituitary incidentaloma: a Pituitary Society international consensus guideline statement
Maria Fleseriu
Mark Gurnell
Theodore H. Schwartz
Nature Reviews Endocrinology (2025)
### Consensus guideline for the diagnosis and management of pituitary adenomas in childhood and adolescence: Part 1, general recommendations
Márta Korbonits
Joanne C. Blair
Helen A. Spoudeas
Nature Reviews Endocrinology (2024) |
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Related Topics:
: chemical equilibrium
: Le Chatelier’s principle
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Top Questions
What is the common ion effect in chemistry?
The common ion effect is the phenomenon in which the addition of an ion already present in a solution reduces the solubility of a weak electrolyte or suppresses the ionization of a weak acid or base.
How does the common ion effect relate to Le Chatelier’s principle?
The common ion effect is a direct application of Le Chatelier’s principle, in which adding more of a reactant causes a system to shift to counteract the change, reducing dissociation or ionization.
What are some applications of the common ion effect?
Applications of the common ion effect include selective precipitation in qualitative analysis, maintaining stable pH in buffer systems, controlling solubility and reaction rates in industrial chemistry, and purifying salts.
common ion effect, in chemistry, phenomenon in which the addition of an ion that is already present in a solution reduces the solubility of a weak electrolyte or suppresses the ionization of a weak acid or base. It is a direct application of Le Chatelier’s principle, an underlying concept of chemical equilibrium, and serves a key role in buffer systems, pH control, and salt precipitation.
According to Le Chatelier’s principle, when a system at equilibrium is disturbed by adding more of a reactant, the system will shift to counteract the change. Thus, when added to a solution, a salt or an electrolyte that shares an ion in common with a dissolved weak acid, weak base, or slightly soluble salt induces a shift toward the reactants, resulting in reduced dissociation. This can result in decreased solubility of a slightly soluble salt or, in the case of a weak acid or weak base, decreased ionization.
Examples
Solubility reduction involving the sparingly soluble salt AgCl (silver chloride). AgCl dissolves in water as AgCl(s) ⇌ Ag+(aq) + Cl−(aq). If NaCl (sodium chloride) is added to a solution of AgCl, Cl− ions are released. The additional Cl− ions from NaCl cause the equilibrium to shift left, reducing the solubility of AgCl and causing more of it to precipitate.
Suppression of weak acid ionization involving CH3COOH (acetic acid). In the presence of CH3COONa (sodium acetate), acetic acid dissociates to release CH3COO− ions. The added CH3COO− ions shift the equilibrium left, reducing the ionization of acetic acid and making the solution less acidic.
Suppression of weak base ionization involving NH3 (ammonia). When NH4Cl (ammonium chloride) is added to a solution of ammonia, NH4Cl releases NH4+ ions, shifting the equilibrium left and reducing NH3 ionization, thereby lowering the pH of the solution.
Applications
The common ion effect has various applications. For example, in precipitation reactions, it is used to selectively precipitate ions in qualitative analysis. It can also be used to maintain a stable pH in biological and chemical buffer systems. In industrial chemistry, the common ion effect can be used to control solubility and reaction rates in pharmaceutical and chemical production. It is also used in the purification of salts, where it can control ion concentrations to reduce unwanted impurities.
Kara Rogers |
12573 | https://www.cuemath.com/numbers/multiples-of-4/ | LearnPracticeDownload
Multiples of 4
Did you know that 4 is the only number that is equal to the number of letters in its name? In this mini-lesson, we will discuss about the multiples of 4 and learn interesting facts about these multiples.
First five multiples of 4: 4, 8, 12, 16, 20
Prime factorization of 4: 4 = 2 × 2 = 22
| | |
--- |
| 1. | What Are the Multiples of 4? |
| 2. | Important Notes |
| 3. | First 20 Multiples of 4 |
| 4. | FAQs on Multiples of 4 |
| 5. | Challenging Questions |
What Are the Multiples of 4?
To get the multiples of a number, we need to multiply natural numbers with integers. A multiple is a product of a number with another number. If X is a multiple of a and b, it means a × b = X. Here a and b are natural numbers and X is the resultant multiple. Below are few examples to justify the above definition mathematically. For example, 4 × 9 = 36. 36 is a multiple of 9 and 4.
Now consider
4 × 1 = 4
4 × 2 = 8
4 × 3 = 12
4 × 4 = 16
Look at the number line below and observe the pattern showing multiples of 4.
In the number line above, do you observe that the multiples of 4 have a pattern of addition hidden? Yes, you just learned another method to find multiples, i.e., addition of a number to itself. According to this, the first five multiples you just learned are 4, 8, 12, 16, and 20.
Important Notes:
Here is a list of the most important and useful identities.
The first multiple of every number is the number itself, 4 × 1 = 4
The multiples of a number are an infinite chain.4 × 1 = 44 × 2 = 84 × 3 = 124 × 4 = 16 and so on
Every multiple of a number is greater than or equal to the number itself.4 × 1 = 4 (4=4)4 × 2 = 8, (8>4) 4 × 3 = 12,(12>4)4 × 4 =16,(16>4) and so on
Multiples of an even number are always even.
A multiple is termed to be a common multiple if it is common to two or more numbers.Example:9 × 2 = 182 × 9 = 18
18 is a common multiple of 9 and 2.
List of First 20 Multiples of 4
In the above section, you have learned about the first 5 multiples of 4. In this section, you will be finding the next 15 multiples of 4
Please use a number line.
Hurray! In the end, you have a total of 20 multiples of 4. If you separate the alternate numbers after 8, that is 16, 24, 32, etc. each one of them is a multiple of 8.
To understand the concept of finding multiples, let us take a few more examples.
Multiples of 5 - The first five multiples of 5 are 5, 10, 15, 20, 25
Multiples of 6 - The first five multiples of 6 are 6, 12, 18, 24, 30
Multiples of 7 - The first five multiples of 7 are 7, 14, 21, 28, 35
Multiples of 8 - The first five multiples of 8 are 8, 16, 24, 32, 40
Multiples of 9 - The first five multiples of 9 are 9, 18, 27, 36, 45
Challenging Questions:
Can you find the multiples of 4, multiples of 9, and multiples of 15? Can you find their factors as well?
Multiples of 4 Solved Examples
Example 1: October 4 is celebrated as World Animal Welfare Day. Can you find the multiples of 4 and multiples of 9 in the month of October?
Solution:
We have a total of 31 days in the month of October. Every 4th day is a multiple of 4 in the calendar.Multiples of 4 in the calendar are:
4 × 1 = 4
4 × 2 = 8
4 × 3 = 12
4 × 4 = 16
4 × 5 = 20
4 × 6 = 24
4 × 7 = 28
Multiples of 9 in the calendar are:
9 × 1 = 9
9 × 2 = 18
9 × 3 = 27
Hence, multiples of 4 in the calendar are 4, 8, 12, 16, 20, 24, and 28 and multiples of 9 in the calendar are 9, 18, and 27.
2. Example 2: With the help of the calendar, find out the common multiples of 4 and 3 in the month of October. Also, find the multiples of 15.
Solution:
We have a total of 31 days in the month of October. According to the calendar, every 3rd day is a multiple of 3 and every 4th day is a multiple of 4. On counting altogether, we have 12 and 24 as common multiples of 3 and 4 in the month of October.
The multiples of 15 in the calendar are:
15 × 1 = 15
15 × 2 = 30
Hence, common multiples of 4 and 3 are 12 and 24. Multiples of 15 are 15 and 30.
Show Answer >
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FAQs on Multiples of 4
What are the common multiples of 3 and 4?
Common multiples of 3 and 4 are infinite. They are 12, 24, 36, and so on.
What are the 5 multiples of 4?
There are infinite multiples of 4. The first 5 multiples of 4 are:
4 × 1 = 4
4 × 2 = 8
4 × 3 = 12
4 × 4 = 16
4 × 5 = 20
Are the multiples of 4 always even?
Yes. We know that 4 is an even number and multiples of an even number are always even.
What is the least common multiple of 4 and 6?
The least common multiples of two numbers 4 and 6 can be calculated using the formula: product of the numbers/GCF of the numbers where GCF(4, 6) is the greatest common factor of 4 and 6.
GCF(4, 6) = 2LCM(4, 6) = (4 × 6)/GCF(4, 6) = 24/2 = 12
Is 2 a multiple of 4?
No, 2 is not a multiple of 4.
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12575 | https://zenodo.org/record/1838251/files/article.pdf?download=1 | l^2 School Science bar and close to the back edge a small hole is made through which a half. knitting needle is thrust at right angles to the bar. The bar is placed on the tumbler as shown in the figure, care being taken to have the pin-point come as close as possible to but not touch the liquid surface. Then the sight-edge is adjusted so that it appears to be in line with the pin-point and the needle-point in the water. The measurement may be transferred directly to the note-book by marking off on two lines, drawn at right angles, the posi-tion of the sight-edge on one and that of the pin-point on the other, also marking the position of the needle-point. Then with any convenient radius and the pin-point as a center describe acircle; construct a perpendicular through the pin-point; draw the path of the incident ray from the needle-point to the pin-point, and that of the refracted ray from the pin-point to the sight-edge; finally construct, measure and compute the ratio of the sines. By varying the length of the needle two or more pairs of angles may be measured in the same figure and the constant ratio of the sines thus clearly shown. The results are surprisingly accurate, coming within one or two per cent with the average pupil; while the simplicity of the apparatus and the directness of the operation both recommend it for individual laboratory work. AN EXPERIMENT TO DETERMINE THE APPARENT COEFFICIENT OF EXPANSION OF A LIQUID. BY F. A. OSBORN. Professor of Physics, Olivet College, Midi. The following method of determining the coefficient of expan-sion of a liquid has been in use for three years in my laboratory and has given such excellent results that other teachers may be glad to have their attention called to, it. An air-thermometer bulb, with a rather large capillary stem, is the chief piece of apparatus. Weigh the empty bulb, and then fill it with boiled distilled water so that the water in the stem is School Sctence 153 3 or 4 cms. from the bulb, when it is at the temperature of the room. The bulb can be best filled by supporting it in a vertical posi-tion in a water bath with the open end of the stem connected to asmall funnel by means of a rubber stopper. Pour the distilled water into the funnel and heat. Air will bubble out through the water; after a few minutes stop heating; the water will run into the bulb as the air contracts. Repeat these operations until the bulb is filled. Take the bulb out of bath and leave it to cool, re-moving the funnel when the bulb has reached the temperature of the room. The desired position of the water in the stem can be obtained by heating the bulb with the hand, thus causing some of the liquid in the stem to flow out. The bulb, being filled to the desired point (which should be marked by a scratch on the stem), is now carefully weighed. The mass of the water in the bulb may be found from the two weighings. From a table get the density of water at the given temperature, and then compute the capacity of the bulb and stem up to the fixed point. The capacity at o C. may be found by the equation: ^ ==^’ (i 0.0000261). The bulb is now to be emptied, dried, and the stem filled with pure mercury for a distance of 10 or 20 cms. Determine care-fully ,the length of this mercury filament and the weight of the bulb and mercury. From these data obtain the area of the cross-section of the stem. The work so far is preliminary, and is done by students in the fall term, as two exercises in the use of the balance. The bulb is now to be filled with the liquid whose coefficient of expansion is to be found. Turpentine, sweet oil, glycerine are good liquids. When filled, immerse the bulb in finely crushed clean ice. When the liquid has reached the temperature of the ice, as shown by the liquid in the stem remaining stationary, mark position by sticking to’ the tube a piece of paper; Remove the bulb, place it in a beaker of cold water and raise the temperature about 20 degrees, if this temperature does not cause the liquid in the stem to overflow. Stir the water constantly and mark the IS4 School Science position of the liquid when it begins to fall after having reached its maximum point. Read the thermometer at this time. With a millimeter scale determine carefully the distance between the two marks. From the data thus obtained, knowing the volume of the bulb and the cross section of the stem, the coefficient of apparent ex-pansion may be computed. For if v be the volume of the liquid at o C., and i/ its apparent volume at the temperature t, then a, the coefficient of apparent expansion, is given by the equation: or ^ = v (i +at), v’ - vDATA FROM A STUDENTS NOTEBOOK. Weight of bulb, full............................................66.790 g. Weight of bulb, empty. ........................................30.960 g. Weight of water......................................."....... .35.830 g. Weight of i c.c. of water at 12.2 degrees C. ...................... 0.999 g. Capacity of bulb and stem to fixed point (35.830 | 0.999) ==35.865 c.c. Capacity of bulb and stem at o degrees C., 35.865 (i 0.000026x12.2)== 35.844 c.c. Length of mercury filament.................................... 14.8 cms. Weight of mercury and bulb. ................................. .35.576 g. Weight of mercury............................................. 4.616 g. Are’a of cross section of stem, 0.0229 sq. cm. Density of mercury, 13.599. Elevation of surface of liquid in stem. Temperature, v v . a. ’Liquid. 11.30 cm. 15.0 degrees 0.2587 0.000481 Glycerine 12.30 cm. 16.4 degrees 0.2816 0.000479 Glycerine 10.40 cm. 13.8 degrees 0.2381 0.000481 Glycerine A Dumas Tablet. A bronze tablet in honor of J. B. A. Dumas has been placed in the house in Rue St. Dominique, Paris, where the bril-liant chemist lived for many years. |
12576 | https://www.therecoveringtraditionalist.com/math-story-problems/ | Well this is video number 6 in our 7 part series about how to teach math without a textbook. All the other videos are linked down below this video and in video number 2, I talked about three instructional practices that you should be doing in elementary math; number sense routines, story problems, and practice.
I’m Christina Tondevold, the Recovering Traditionalist and I hope you stick around because in this video we are going to dig into how to teach math through story problems in our quest to build our math minds so we can build the math minds of our students.
Watch the video or read the transcript below:
Here are links to products/activities mentioned in this vlog. (Some may be affiliate links which just means that if you do purchase using my link, the company you purchased from sends me some money. Find more info HERE about that.)
Video series prior videos
1: Why you shouldn’t teach math through a textbook
2: How to Teach Elementary Math Without a Textbook
3: Creating School Change When Others Don’t Want To
4: Components of Number Sense in PreK-2
5: Components of Number Sense in 3rd-5th
6: Teaching Math through Story Problems
7: Math Practice: Building Math Fluency through Games (releases 10-17)
Download the Guide to Teaching Elementary Math Without a Textbook
Teacher’s Guide to CGI from the University of Wisconsin Oshkosh
Cognitively Guided Instruction: A Knowledge Base for Reform in Primary Mathematics Instruction by Carpenter, Fennema, and Franke.
Children’s Mathematics: Cognitively Guided Instruction by Carpenter, Fennema, Franke, Levi, Empson
5 Practices for Orchestrating Productive Discussion by Smith & Stein
Robert Kaplinsky’s How Old is The Shepherd? Video
Dan Meyer’s TED talk – Math Class Needs a Makeover
Join Course Waitlist
Let me start off with a little bit about what teaching with story problems is not.
It is not teaching kids steps and tricks to solve problems, like CUBES and Key Words. Those things need to go away.
It is not saving the story problem for the end of the lesson after the kids have done 20 bare problems, just so kids get that real world connection.
I’m a believer in using context, or story problems, to teach the mathematics. We don’t add in the story problem at the end to help kids see a connection to it, we start with story problems to begin with.
Cognitively Guided Instruction – What teaching math with story problems should look like
You’ve probably heard me talk about it before, but I’m going to bring it back around. Cognitively Guided Instruction. It is what the teaching of mathematics with story problems should look like. Now, Cognitively Guided Instruction is often referred to as C-G-I, we love our acronyms in education, and this is just another one of them. But if you hear me refer to CGI, that’s Cognitively Guided Instruction.
The basic premise of CGI, this is a summary version of it, but the idea is that you give kids a problem in context without any instruction and you just let them solve it using their own intuitive understanding of the mathematics and you watch to see how they approach it. And then, what they discovered is this progression that kids go through with their solution strategies for addition, subtraction, multiplication, and division, and that progression is something you need to watch for as kids are solving the problems and then you help guide them to more advanced solution strategies as you see that they are ready for it. But one of the things that is underlying Cognitively Guided Instruction is this idea of the problem types.
I’m not going to go too deep into it. I’ll show a picture here of the CGI problem types for addition and subtraction.
There’s also one for multiplication and division and you can find them very easily by Googling “CGI Problem Types Chart.”
I’ll also link below to some of my favorite. These problem types have kind of gotten used in the wrong way, I guess I should say, is that often times we look at these problem types and we teach kids how to solve each of the different problem types. The idea of the problem types is to understand them for ourselves as teachers because the type of problem that we give students will partly determine the solution strategy they use. There are kids who will solve problems in one problem type and then you give them the exact same numbers in a different problem type and they can’t solve it.
So, if you want to learn even more about Cognitively Guided Instruction, I’ll link to one of their research articles and I’ll link to the book that details it out for you guys underneath this video. But I just want to give you one quick example of why the story problem type makes a difference. So let’s use this example:
“Sierra has some money. She earns $17. Now she has $36. How much money did she begin with?”
To adults that seems like we could pull out the numbers and subtract, which is why our textbooks will often put that kind of a story problem in a subtraction lesson because yes, you can take 36 and subtract 17 and get your answer, but that problem is not a subtraction problem to kids.
To children, it’s basically, she has some, so like you could put a X, you could put a circle there, whatever you want to put, she has some. She got 17 more, so you add 17 and now you’re at 36. To them that is not a subtraction problem. They need to figure out what to add, what added to 17 gets them to 36.
They’re not seeing it as subtraction and yes, later down the road, yeah, we want them to see all of those relationships and be able to use subtraction to solve it, but if we jump straight to, just solve this with subtraction. This is where kids start to become what my friend Graham Fletcher calls Number Pluckers. They just start plucking out the numbers and trying to operate on them, thinking that it doesn’t need to make sense. I just need to perform some kind of operation.
So the premise of CGI is to really understand kids’ solution strategies, give them problems based upon the problem types and where you think that they would be able to solve things and then you watch to see how they’re solving it. How are they intuitively thinking about that problem?
Now the other cool part about knowing the problem types is that once you know those problem types, you could really put in any numbers that you want.
You could take Sierra’s problem there that I just had and you could replace it with some with decimals. You could even put fraction in there. You could even make it single digit, right? It just depends upon what your students are working on. You could totally use that same story problem, just replace the numbers to be something that’s appropriate for your students at the time.
Now another key component to teaching with story problems in mathematics is really what I like to refer to as the missing piece.
5 Practices – The missing piece of teaching math with story problems
When I first learned about this stuff I went back into my classroom and I would give kids a story problem, I’d let them solve it and it didn’t work out too well to begin with, but I would let them solve it and then I would do what I would consider the show and tell.
Once they solved a problem, I would have kids come up and show and tell about the strategy that they used to solve the problem. Then they would go sit down. Another kid would come up and show and tell about their strategy, another kid would show and tell, and then I would just end the lesson.
But one of the key pieces to using story problems in your classroom is the discussion that needs to happen about the different solution strategies. Once you have kids share, the powerful piece is connecting those strategies. If kids are feeling, if you see kids kind of toning out when kids are sharing their strategies, it’s because they aren’t seeing the connectedness between it.
So one of the jobs for us as teachers when we’re teaching through story problems is yes, letting kids share, but then weaving the thread of connectedness. Helping kids see how this strategy is similar to this strategy. How are they alike, how are they different, what do you see? And build relationships around solution strategies. Don’t just do the show and tell.
One of the best ways I ever learned to do this was from the book, 5 Practices. Now I just call it the five practices but it’s the 5 Practices for Orchestrating Productive Mathematical Discussions and I’ll link to that below this video as well. It walks you through how to make that time be the most productive that it can be and it’s such a powerful piece. And most of us are doing it incorrectly, I know I was. So that book really helped me out. But it’s all about monitoring for certain solutions, picking the ones that you want to come up so that you can weave that connectedness for the students.
Where to get tasks to help you teach math with story problems
Okay, the last piece here when you are trying to teach math with story problems is where do you get the tasks? So, you can definitely create your own using the CGI problem types. If you Google that, you will see the charts and it will give you a framework basically to write your own.
That’s one of the most powerful ways to do it because you can write them using your kids, your students names. You can write them using number sets that are appropriate for them. What kind of numbers should you have in there? And context that matter to your students.
Every year there’s a new fad coming around. Video games, whatever it is that your students are interested in, write story problems using those contexts. So, create your own. The other thing is, it doesn’t have to be story problems like the typical story problem frameworks, there are lots of cool ways that you can encompass this problem solving atmosphere in your classroom.
One of my other favorites is through the use of Three-Act Math Tasks. Now Graham Fletcher is one of the leading experts in that for elementary school. Upper grades, Dan Meyer was one of the first people to get started in that from junior high and high school, but I’ll link to Graham’s site where he lists all of his Three-Act Math Tasks that you can use with elementary students.
The last thing I’m going to link to underneath this video is how to modify your textbook. One of my favorite videos that got me started in this was Dan Meyer’s TED Talk about how the math classroom needs a makeover and he talks about how he modifies a high school textbook, but that gave me so many ideas about how to modify textbooks in the elementary and middle school as well.
All of those will be linked below this video and I also want to remind you that there is a guide that I have available for teaching math without a textbook that I would love for you to go check out that you can get your hands on and it talks you through all of this whole video series. And don’t forget the rest of the videos are linked below this video.
I hope that this video has built your mind around how to teach mathematics through story problems because they are one of the best ways to build your students’ math minds. Have a great day.
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Welcome! I’m a Recovering Traditionalist elementary teacher and now, I help teachers and children learn to love math. Explore how I can help provide you PD at your fingertips! BuildMathMinds.com |
12577 | https://fisica.unipv.it/PLS/filespdf/quanto-di-luce-PVnov2013.pdf | Il quanto di luce e la fisica quantistica Giuseppina Rinaudo – Dipartimento di Fisica – Università di Torino Corso di aggiornamento in fisica – AIF Sezione di Pavia - Novembre 2013 • motivazioni della scelta • ripensare all’energia in fisica classica: aspetti “corpuscolari” e “ondulatori” • dal “quanto di azione” di Planck al “quanto di luce” di Einstein • il metodo della “somma sui molti cammini” Riferimenti R.Feynman, “QED, la strana teoria della luce” ADELPHI 1985 E.F.Taylor, Computers in Physics 12 (1998) 190 E.Fabri, “Come introdurre la fisica moderna nella scuola secondaria superiore” LFNS 29, Suppl.n.1, p.63-80 (1996) L.Borello et al.,“Il metodo della somma sui molti cammini di Feynman per l’introduzione della Meccanica Quantistica” LFNS 35, Suppl.n.2, p.119-124 (2002) M.Romita, “Il paradigma onto-semiotico nella didattica per la Meccanica Quantistica: una proposta di formazione per i docenti di scuola superiore” LFNS 46, Suppl.n.1, p.147-153 (2013) Sito web Motivazioni della scelta La proposta nasce nel 2000 (avvio corsi SIS e progetto SECIF-Guidoni) Scopo: introdurre la fisica dei quanti con un percorso che • richieda prerequisiti ragionevoli di conoscenze matematiche (NO all’uso di numeri complessi e di equazioni differenziali) • richieda prerequisiti ragionevoli di conoscenze fisiche (concetti di energia, spazio, tempo, massa, velocità, quantità di moto, frequenza) • eviti di porre in contrapposizione fisica “classica” e fisica “quantistica”, anzi rinforzi i concetti fondamentali della fisica classica • permetta una “visualizzazione” ragionevole dei concetti fondamentali della meccanica quantistica (dibattito Schrödinger-Heisenberg) • eviti il “dualismo onda-particella” • fornisca una chiave di interpretazione degli esperimenti tutto è ricondotto sostanzialmente alla sola relazione di Planck E = h f Che cosa c’è da capire nella relazione di Planck E = h f : E = energia, h = quanto di azione, f = frequenza • lega l’energia E alla frequenza f, • con un coefficiente di proporzionalità, h, che è una “costante naturale” In fisica classica, energia e frequenza sono concetti che appartengono a fenomeni diversi, perché • l’energia è una proprietà che, nella fisica classica, associamo abitualmente a un corpo materiale, ben localizzato nello spazio-tempo, al quale però è difficile associare una “frequenza” • la frequenza è caratteristica di un fenomeno periodico, al quale però è difficile associare una “energia” ben localizzata nello spazio-tempo È quindi essenziale ripensare al ruolo che il concetto di energia ha nella fisica classica Energia: la cenerentola della fisica classica • in fisica classica l’energia ha spesso, rispetto ad altri concetti, un ruolo marginale nella descrizione e comprensione dei fenomeni • in meccanica quantistica l’energia è invece la grandezza cruciale: l’equazione di Schrödinger è una relazione fra “l’operatore energia” e i suoi “autovalori” • l’energia va quindi ricondotta, fin dalla fisica classica, al suo ruolo centrale di “variabile di stato” e, come tale, descrittore fondamentale e unificante dei fenomeni anche il ruolo della quantità di moto è mal utilizzato in fisica classica: • viene usato principalmente per risolvere in modo abbreviato problemi in cui interviene la legge di conservazione della quantità di moto • e non come descrittore di una proprietà caratteristica dell’oggetto in moto, come avviene invece in MQ • anche la quantità di moto va ricondotta, fin dalla fisica classica, al suo ruolo di descrittore di una caratteristica del corpo in moto e non solo della sua interazione con altri corpi Energia e quantità di moto in meccanica • nella meccanica classica l’approccio al moto è calato in un’ottica newtoniana che finisce con il condizionarlo • l’energia viene introdotta attraverso la via forza →lavoro →energia • in questo modo, il concetto di energia è ancillare a quello di lavoro, a sua volta ancillare a quello di forza • rimane in secondo piano la proprietà dell’energia di essere una “variabile di stato”, cioè qualcosa che il corpo (o il sistema) porta con sé e lo caratterizza, • l’essere una variabile di stato è ciò che determina essenzialmente il ruolo importante che l’energia ha in meccanica quantistica • anche la quantità di moto dovrebbe essere vista come la vera proprietà dinamica che descrive il corpo in moto • è molto più importante della velocità, che descrive invece la caratteristica cinematica del moto del corpo e che, in meccanica quantistica, perde significato • mentre la quantità di moto mantiene, anche in MQ, il suo ruolo importante (è l’operatore che descrive la variazione spaziale della funzione d’onda!) L’energia in elettromagnetismo • in elettromagnetismo il ruolo riservato all’energia nell’approccio tradizionale è ancora più confuso che in meccanica • manca soprattutto il concetto di energia “immagazzinata” in un campo elettrico o in un campo magnetico • esperimenti cruciali: - per caricare un condensatore occorre un’energia Eel = ½ ε Ε 2 V che poi rimane immagazzinata come energia elettrostatica nel volume V del condensatore - nel campo magnetico di un solenoide c’è un’energia Emg=½ μ H2 V, immagazzinata nel volume V del solenoide • sono concetti essenziali per capire che un’onda elettromagnetica trasporta energia in quantità proporzionale al quadrato dei campi E e H • peraltro l’idea di “campo” e di energia associata al “campo” è ormai famigliare anche a un ragazzino di scuola media! Riassumendo, che cosa si dovrebbe aver chiaro dalla fisica classica nei riguardi dell’energia: • che l’energia è una proprietà caratteristica del corpo in sé (o del sistema di corpi) • che può essere trasferita da un corpo all’altro in modi diversi attraverso interazioni diverse • che può essere trasportata anche mediante onde, in particolare onde elettromagnetiche, senza che vi sia trasporto di massa • che l’energia portata da un’onda non è localizzata è distribuita in un volume di dimensioni finite, a differenza di quella portata da un corpo materiale che, idealmente, può avere dimensioni piccole a piacere • che l’energia può essere trasferita da un’onda a un corpo dotato di massa attraverso interazioni opportune Tutto ciò vale per fenomeni macroscopici: è ancora valido a dimensioni microscopiche?
L’inizio della storia: la relazione di Planck, E = h f • formulata da Planck nel 1901 per interpretare una anomalia dello “spettro di corpo nero” non spiegata dal modello classico • introdotta in modo confuso e spesso errato nei testi di fisica per seguire lo sviluppo storico violetto blu verde giallo arancio rosso infrarosso ↓ ↓ ↓ 380 550 750 →λ (nm) spettro sole1-ore15 0 500 1000 1500 2000 2500 3000 3500 4000 300 400 500 600 700 800 900 1000 lunghezza d'onda (nm) O, N atm Hα Sole He1 Sole O atm He4 Sole He3 Sole He2 Sole Hβ Sole Hγ Sole spettro della luce solare spettro di corpo nero del sole un po’ di chiarezza fra i termini: •“spettro”: separazione della luce (radiazione elettromagnetica) nelle diverse lunghezze d’onda (colori). Si ottiene con un prisma o con un reticolo di diffrazione •“spettro della luce solare”: intensità luminosa (energia/tempo) in un intervallo di lunghezza d’onda. Si misura con un fotodiodo che cattura l’energia solo in quel dato intervallo di lunghezza d’onda •“spettro di corpo nero”: è una curva teorica che si calcola ipotizzando un equilibrio fra la radiazione elettromagnetica emessa o assorbita da un corpo a temperatura T. L’andamento dello spettro solare è ben approssimato da uno spettro di corpo nero con una temperatura di circa 6500 K sulla superficie del Sole con sovrapposte le righe di assorbimento dell’atmosfera solare Lo spettro di corpo nero 0 50 100 150 200 250 0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 lunghezza d'onda (nm) intensità (unità arbitrarie) UV visibile infrarosso 6000 K 1000 K 3000 K 1 2 ) ( / 3 3 − = − T k hf B e c f h f I • legge di Wien (1985): la frequenza a cui si verifica il picco di intensità è proporzionale alla temperatura assoluta T del corpo che ha emesso la radiazione, fmax= 5AT (A=3⋅10-3 m⋅K, costante di Wien). Dal valore di A si ottiene B ≈6,6⋅10-34 J⋅s ≈h!
• l’andamento “a campana” dello spettro di corpo nero era già stato modellizzato nella seconda metà dell’Ottocento con ragionamenti classici di elettromagnetismo e di meccanica statistica termine di Boltzmann, con “energia” E proporzionale alla frequenza f T k Bf B e Cf f I / 3 ) ( − = T k E B e / − • idea base: la radiazione e.m. viene emessa di preferenza alla frequenza f a cui oscillano gli elettroni presenti nel corpo, che è legata alla temperatura assoluta T • “l’anomalia infrarossa”: l’intensità a piccole frequenze del modello di Wien era troppo bassa Planck aggiunge sostanzialmente l’ipotesi che l’energia E della radiazione emessa da un singolo oscillatore sia un multiplo intero di una energia fondamentale Eo=hf, E=nEo=nhf • e ottiene l’espressione corretta dello spettro: - e il valore della costante C del modello di Wien, C=2hc-3, che determina il valore assoluto della potenza emessa per unità di angolo solido: primo esempio di calcolo statistico quantizzato!
- con il termine “-1” aggiunto al denominatore della formula di Wien, che cura “l’anomalia infrarossa” Il significato della relazione di Planck • Planck ipotizza sostanzialmente che materia e radiazione scambino energia in quantità elementari che sono pari al prodotto del “quanto di azione” h moltiplicato per la frequenza f E = h f E=energia h=quanto di “azione” f=frequenza • la relazione di Planck è rivoluzionaria perché esprime un legame fra l’energia E ceduta da un corpuscolo “puntiforme” (l’elettrone) e la frequenza la frequenza f di un campo e.m.: E = proprietà tipica dei “corpuscoli materiali” f = proprietà caratteristica di “un’onda” • domanda chiave: l’energia del campo e.m. è “di per sé” quantizzata in multipli di hf, oppure si comporta come se fosse quantizzata solo quando viene scambiata con oggetti materiali come gli elettroni? 1 2 1 2 ) ( / 3 3 / 3 3 − = − = − − T k hf T k E B B e c f h e c f h f I E = h f Da Planck a Einstein l’interpretazione di Einstein (1905) - l’energia di un campo elettromagnetico è “quantizzata” - il valore del “quanto elementare” di energia di frequenza f è Ef = hf - h è la “costante di Planck” h=6,6⋅10-34 J⋅s - la quantizzazione dell’energia non avviene al momento dell’interazione con la materia, ma è il campo e.m. stesso che si comporta come una particella (il “fotone”) che ha contemporaneamente aspetti corpuscolari (E) e ondulatori (f) L’interpretazione dell’effetto fotoelettrico L’effetto fotoelettrico (Lénard, 1902) - sul fotocatodo incide luce di frequenza f - gli elettroni che escono sono attirati verso l’anodo dalla differenza di potenziale V - la corrente va a zero per un valore del potenziale di arresto che dipende linearmente da f eV=a+hf h=6,6⋅10-34 J⋅s h=costante di Planck fotocatodo anodo L’effetto Compton (1922) • un fotone di energia E=hf ha una quantità di moto p = hf / c = E / c • Il fotone si comporta come una particella di massa nulla dotata di energia e quantità di moto L’esperimento: • Un fascio di raggi X di λ=0,0709 nm viene diffuso dagli elettroni di atomi di carbonio • I fotoni che escono a un angolo θ hanno λ maggiori, compatibili con l’ipotesi che il fotone cede all’elettrone energia e quantità di moto compatibili con le leggi di conservazione Bohr e l’interpretazione delle righe spettrali dell’atomo di idrogeno • anche l’elettrone ha proprietà ondulatorie • la sua lunghezza d’onda vale λ = h / p • ipotesi confermata (1927) dagli esperimenti di Davidsson, Germer e, indipendentemente, da G.P.Thomson Perché è difficile vedere effetti ondulatori in interazioni di elettroni • Energia di un elettrone accelerato con una differenza di potenziale di 100 V: E = 1,6 ⋅10-17 J = 100 eV • Quantità di moto: p = √2mE ≈5,4 ⋅10-24 kg m/s • Lunghezza d’onda: λ = h / p ≈1,2 nm λ è estremamente piccola anche per elettroni di bassa energia!
Negli esperimenti storici come quello di J.J.Thomson λ è così piccola che gli effetti ondulatori sono trascurabili: l’elettrone si comporta come una particella “classica”!
Bohr e l’interpretazione delle righe spettrali 1859 leggi di Kirchoff sugli “spettri a righe” degli atomi 1885 serie di Balmer: f∝1/n2-1/m2 (f = frequenza della riga) 1913 ipotesi di Bohr sugli stati stazionari dell’elettrone nell’atomo di idrogeno e sulle transizioni fra stati: anche l’elettrone ha una “frequenza propria” calcolata dalla relazione di Planck in base all’energia cinetica Ea+Eγ = Eb assorbimento Ea= Eγ+ Eb emissione la quantizzazione delle frequenze coincide con la conservazione dell’energia stati stazionari Ea γ γ Eb Ea Eb Modello di Bohr: • l’elettrone percorre un’orbita circolare di raggio r calcolato secondo la meccanica classica • l’energia cinetica e quella potenziale dipendono dalla distanza media r dal nucleo come pure il periodo T e la pulsazione ω=2π /T • non tutte le orbite sono stabili, ma solo quelle per cui la frequenza di rotazione è pari alla frequenza “propria” dell’elettrone calcolata dalla relazione di Planck in base all’energia cinetica • di qui segue che il momento angolare orbitale è multiplo intero di h/2π e che i valori permessi dell’energia totale Etot=Ekin+Epot sono discreti (quantizzati) e sono espressi dalla relazione En=-RH/n2 • per la proporzionalità tra frequenza ed energia della radiazione (Eγ =h fγ), l’emissione o l’assorbimento della radiazione avviene a una frequenza “sintonizzata” non con la frequenza di rotazione dell’elettrone ma con la differenza di energia fra stati stazionari De Broglie e la lunghezza d’onda dell’elettrone (1924) • l’elettrone ha proprietà ondulatorie • la sua lunghezza d’onda vale λ = h / p • ipotesi confermata (1927) dagli esperimenti di Davidsson, Germer e, indipendentemente, da G.P.Thomson Perché è difficile vedere effetti ondulatori in interazioni di elettroni • Energia di un elettrone accelerato con una differenza di potenziale di 100 V: E = 1,6 ⋅10-17 J = 100 eV • Quantità di moto: p = √2mE ≈5,4 ⋅10-24 kg m/s • Lunghezza d’onda: λ = h / p ≈1,2 nm λ è estremamente piccola anche per elettroni di bassa energia!
Negli esperimenti storici come quello di J.J.Thomson λ è così piccola che gli effetti ondulatori sono trascurabili: l’elettrone si comporta come una particella “classica”!
Il cambio di paradigma Lo sviluppo storico della fisica classica ci ha abituati a pensare che • un corpo dotato di una massa m, come l’elettrone, è una particella descrivibile come un “punto materiale” che segue le leggi della meccanica newtoniana: la descrizione del moto dei corpi dotati di massa come “punti materiali” risale infatti al XVII secolo e ha avuto innumerevoli verifiche sperimentali, mentre, per gli aspetti “ondulatori”, bisogna arrivare al modello di Bohr (1913) e, per le prime evidenze sperimentali dirette, agli esperimenti di D.G.T (1927) • la radiazione elettromagnetica è un’onda costituita da campi elettrici e magnetici che si propagano con un’ampiezza che varia secondo l’equazione dell’onda e che si sovrappongono nello spazio-tempo: la prima descrizione della luce come “onda” risale infatti al XVII secolo (Huygens), la prima verifica sperimentale è del 1801 (Young), mentre bisogna arrivare al 1902 per la prima evidenza sperimentale di aspetti “corpuscolari” e all’interpretazione di Einstein del 1905 Come dice Feynman fin dall'inizio del suo libro "QED, la strana teoria della luce", il linguaggio e le leggi della fisica classica sono inadeguate a descrivere il moto nelle condizioni estreme come quelle che si verificano nel mondo microscopico per cui non solo è obbligatorio ricorrere alle leggi della meccanica quantistica ma dobbiamo anche staccarci, nel linguaggio, dal modo di esprimersi proprio della meccanica classica, che è quello a noi più congegnale, dato che, in fondo, anche noi siamo degli oggetti “classici” Perché è difficile descrivere un oggetto che si comporta in “modo quanto-meccanico” le associazioni mentali, evocate dall'uso di certe parole come "onda" o "corpuscolo", sono fuorvianti nell’esperimento di Davidson e Germer il rivelatore non rivela la frazione dell’onda “elettronica” che riesce a intercettare perché cade nel suo angolo solido, ma rivela sempre l’intero elettrone o non lo rivela per nulla • quando si dice che un elettrone ha “comportamenti ondulatori” non significa che l’elettrone si comporta come “un’onda classica”: un elettrone che viene rivelato da un dispositivo è rivelato “per intero”, con tutta la sua energia, mentre per un’onda classica viene rivelata generalmente solo la frazione di onda che il dispositivo intercetta perché cade nell’angolo solido di copertura • quando si dice che un fotone ha “comportamenti corpuscolari” non significa che si comporta come una particella “classica” perché ha una frequenza f e un’energia pari a hf, la sua posizione spaziale è definita solo all’interno di una “figura di diffrazione”, ecc.
Dalla “fisica dei quanti” alla “meccanica quantistica” • è lecito tentare di “visualizzare” in qualche modo il comportamento di un corpo nelle condizioni in cui è richiesta la descrizione quantistica? • il modello di Feynman va appunto in questa direzione: fu sviluppato (1985) per far capire agli “amici non fisici”, in modo semplificato ma ragionevolmente rigoroso, le peculiarità di un oggetto che si comporta in un "modo quanto-meccanico" • oggi molte riserve sul linguaggio sono superate perché lo sviluppo del Microscopio a Forza Atomica (AFM) e altri strumenti simili ha permesso di ottenere immagini di oggetti a livello atomico • il modello ondulatorio di de Broglie: “l’onda di probabilità” • l’equazione di Schrödinger (1926): la “funzione d’onda” e “l’ampiezza di probabilità” • la meccanica delle matrici di Heisenberg (1925) e le relazioni di indeterminazione (1927) • la scuola di Copenhagen e il dibattito sui fondamenti della meccanica quantistica 10 atomi in 3 nm → circa 1 atomo ogni 3 Å Immagini all’AFM: grafite e nanotubi di carbonio Richard Errett Smalley (premio nobel per la chimica - 1996) "This STM image shows the direct observation of standing-wave patterns in the local density of states of the Cu(111) surface. These spatial oscillations are quantum-mechanical interference patterns caused by scattering of the two-dimensional electron gas off the Fe atoms and point defects." Un “miraggio” quantistico Visita all’INRIM 19/1/07 Un “superatomo” formato da circa 2000 atomi di rubidio raffreddati a temperature inferiori a 1 mK E.Cornell e C.Wieman premio Nobel per la fisica 2001 La condensazione di Bose-Einstein • ipotesi di partenza: la relazione di Planck E = hf • l’oggetto quantistico è caratterizzato dall'energia E e dalla frequenza f , legata a E attraverso il quanto di azione h, • ha quindi ha un suo orologio interno che gira con la frequenza f • e una fase ϕ che varia periodicamente nel tempo con un periodo pari a 1/f • per andare da A a B, l’oggetto quantistico non percorre un dato cammino ma una sovrapposizione di cammini possibili, • il risultato dell’osservazione in B dell’oggetto quantistico dipende dalla sovrapposizione dei vettori di fase in B (principio di sovrapposizione) L’oggetto quantistico di Feynman: ipotesi e “regole” Dato che le associazioni mentali, evocate dall'uso di certe parole come "onda" o "corpuscolo", sono fuorvianti, chiamiamo per brevità oggetto quantistico l'oggetto che si comporta in un "modo quanto-meccanico" Il linguaggio dei “molti cammini”: frequenza, lunghezza d’onda, vettore di fase (fasore) IX VI III XI λ mentre il clock interno fa un giro completo • la fase varia di 2π • l’oggetto quantistico percorre un cammino λ • che dipende dalla quantità di moto p dell'oggetto e si calcola dalla relazione di de Broglie: λ = h / p I diversi cammini • per andare da A a B l’oggetto quantistico può percorrere cammini diversi, anzi percorre tutti i possibili cammini • lungo ogni cammino il suo vettore di fase avanza per una fase proporzionale alla lunghezza del cammino • è la sovrapposizione dei vettori di fase che determina la probabilità di rivelare l’oggetto in B (principio di sovrapposizione) • 3 cammini fra A e B che stanno in una finestra di larghezza Dtrasv • 3 vettori di fase e la loro risultante r Un esempio: una fenditura che blocca tutti i percorsi al di fuori di una data finestra 3 2 1 A B ϕ1 ϕ2 ϕ3 1 2 r 3 Dtrasv Attenzione: la risposta del rivelatore posto in B è sempre “sì” o “no”, ma la probabilità che sia “sì” è proporzionale a r2 (principio di sovrapposizione) Un esempio di calcolo della somma sui molti cammini con un foglio “excel” 9 10 11 8 6 5 4 3 2 1 7 B A Dtrasv DA DB • 11 cammini fra A e B • con valori equispaziati dell’intersezione al centro della fenditura • la probabilità di rivelare l’oggetto quantistico in B è proporzionale a r2 per il principio di sovrapposizione Parametri: • DA • DB • Dtrasv • massa m • energia E Somme dei vettori di fase 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 -8.0 -6.0 -4.0 -2.0 0.0 Su Sv r Il significato della sovrapposizione r • r2 (e quindi la probabilità) diminuisce man mano che B si allontana dal centro della fenditura • ma rimane >0 anche quando B entra nel cono d’ombra • per un elettrone “classico” sarebbe stata =0 nel cono d’ombra e costante (=1) fuori yB=0 r2=145 yB=0,5 mm r2=111 cammini (n=21) -2 -1 0 1 2 0 500 1000 1500 2000 2500 d (mm) y (mm) cammini (n=21) -2 -1 0 1 2 0 500 1000 1500 2000 2500 d (mm) y (mm) cammini (n=21) -2 -1 0 1 2 0 500 1000 1500 2000 2500 d (mm) y (mm) yB=1,5 mm r2=18 yB=1 mm r2=37 Somma dei vettori di fase -14 -12 -10 -8 -6 -4 -2 0 2 4 -2 0 2 4 Su Sv Somma dei vettori di fase -14 -12 -10 -8 -6 -4 -2 0 2 4 -4 -2 0 2 4 Su Sv Somma dei vettori di fase -14 -12 -10 -8 -6 -4 -2 0 2 4 -5 0 5 10 Su Sv cammini (n=21) -2 -1 0 1 2 0 500 1000 1500 2000 2500 d (mm) y (mm) Somma dei vettori di fase -14 -12 -10 -8 -6 -4 -2 0 2 4 -4 -2 0 2 4 Su Sv r r r r cono d’ombra cono d’ombra B B B B … e per concludere un’immagine“quantistica” Pissarro Haymakers rest Il metodo della “somma sui molti cammini” di Feynman: il sito web Panoramica Motivazioni L'oggetto quantistico Ipotesi e regole Impostazione del calcolo • Tutorial →xls • La probabilità quantistica →xls • I cammini e gli ostacoli →xls • Oscillazioni →xls • Ombre →xls • Diffrazione →xls • Rifrazione →xls Guida agli esperimenti Letture Sperimentazioni in classe Download Il sito web |
12578 | https://www.bbc.co.uk/bitesize/articles/zs83dnb | Module 7 (M7) – Algebra - Proportion and Variation - BBC Bitesize
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Module 7 (M7) – Algebra - Proportion and Variation
Part ofMathsM7: Algebra
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Direct proportion
Examples
Test yourself
Before reading this guide, it may be helpful to read the guide from Module 3 (M3) on equations.
Direct proportion
There is a direct proportion between two values when one is a multiple of the other. For example, 1 cm=10 mm. To convert cm to mm, the multiplier is always 10.
Direct proportion is used to calculate the cost of petrol or exchange rates of foreign money.
The symbol for direct proportion is ∝.
The statement ‘T is directly proportional to r’ can be written using the proportionality symbol:
T∝r
This means that T=k r.
k is a constant called the constant of proportionality.
There will be information in the question that will enable you to calculate the value of k and set up an equation.
There are four steps to do this:
write the proportional relationship
convert to an equation using a constant of proportionality
use given information to find the constant of proportionality
substitute the constant of proportionality into the equation
Example
The value e is directly proportional to p. When e=20, p=10. Find an equation relating e and p.
e∝p
e=k p
20=10 k so k=20÷10=2
e=2 p
This equation can now be used to calculate other values of e and p.
For example, if p=6 then e=2×6=12.
In general…
Write down how the variables are connected, using the proportion sign ∝
Rewrite using k and an equal sign (=)
Substitute the values given for the two variables into this equation
Solve to find a value for k
Rewrite the equation using this value for k
Use the equation as a formula to find any unknown values
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Examples
Question
Q is proportional to p. When p=5, Q=20.
Write and equation relating Q and p and use it to find the value of Q when p=1.2.
Show answer Hide answer
Solution
Write down how the variables are connected, using the proportion sign ∝
Q is proportional to p
Q∝p
Rewrite using k and an equal sign (=)
Q=k p
Substitute the values given for the two variables into this equation
When p=5, Q=20, so 20=5 p
Solve to find a value for k
k=4
Rewrite the equation, using this value for k
Equation is Q=4 p
Use this formula to find any unknown values
When p=1.2, Q=4(1.2)
=4.8
Answer
Q=4.8
Question
The value V (in £) of a precious gem varies as the square of its weight w (in grams).
If a gem weighing 0.8 grams is worth £2000,
Find V in terms of w;
How much will a gem weighing 0.5 grams be worth? Give your answer to the nearest £.
Show answer Hide answer
Solution
Write down how the variables are connected, using the proportion sign ∝
V varies as the square of w
This is a different way to say 'V is proportional to the square of w'.
Therefore, V∝w 2
Make sure you square w and not V!
Rewrite using k and an equal sign (=)
V=k w 2
Substitute the values given for the two variables into this equation
When w=0.8, V=2000, so 2000=(0.8)2 k
Solve to find a value for k
2000 0.8 2=k
k=3125
Rewrite the equation using this value for k
V=3125 w 2
Use this formula to find any unknown values
Find V when w=0.5
V=3125(0.5)2
V=£781 (nearest £)
Answer
£781
Question
z is proportional to the square root of y. When y=1.96, z=84.
Find a formula connecting z and y.
Find the value of y when z=222.
Show answer Hide answer
Solution
z is proportional to the square root of y
z∝y
A common error here is to write y 2 instead of y.
z=k y
y=1.96 z=84⟶84=k 1.96
84=1.4 k
k=60
z=60 y
z=222 y=?⟶222=60 y
222 60=y
3.7=y
y=3.7 2=13.69
Answer
y=13.69
Questions on this topic are often set in real-world situations, usually with scientific terms.
You do not need to understand the science behind the question – just pick out the variables, and find the connecting equation as in the examples above.
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Module 7 (M7) – Algebra - Standard form
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12579 | https://en.wikipedia.org/wiki/Number | Jump to content
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Used to count, measure, and label
For other uses, see Number (disambiguation).
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A number is a mathematical object used to count, measure, and label. The most basic examples are the natural numbers 1, 2, 3, 4, and so forth. Individual numbers can be represented in language with number words or by dedicated symbols called numerals; for example, "five" is a number word and "5" is the corresponding numeral. As only a relatively small number of symbols can be memorized, basic numerals are commonly arranged in a numeral system, which is an organized way to represent any number. The most common numeral system is the Hindu–Arabic numeral system, which allows for the representation of any non-negative integer using a combination of ten fundamental numeric symbols, called digits.[a] In addition to their use in counting and measuring, numerals are often used for labels (as with telephone numbers), for ordering (as with serial numbers), and for codes (as with ISBNs). In common usage, a numeral is not clearly distinguished from the number that it represents.
In mathematics, the notion of number has been extended over the centuries to include zero (0), negative numbers, rational numbers such as one half , real numbers such as the square root of 2 and π, and complex numbers which extend the real numbers with a square root of −1 (and its combinations with real numbers by adding or subtracting its multiples). Calculations with numbers are done with arithmetical operations, the most familiar being addition, subtraction, multiplication, division, and exponentiation. Their study or usage is called arithmetic, a term which may also refer to number theory, the study of the properties of numbers.
Besides their practical uses, numbers have cultural significance throughout the world. For example, in Western society, the number 13 is often regarded as unlucky, and "a million" may signify "a lot" rather than an exact quantity. Though it is now regarded as pseudoscience, belief in a mystical significance of numbers, known as numerology, permeated ancient and medieval thought. Numerology heavily influenced the development of Greek mathematics, stimulating the investigation of many problems in number theory which are still of interest today.
During the 19th century, mathematicians began to develop many different systems now called algebraic structures, which share certain properties of numbers, and may be seen as extending the concept. Among the first were residue systems, p-adic numbers, and hypercomplex numbers, which, in modern mathematics, are considered important special examples of more general algebraic structures, such as rings and fields. The use of the term "number" for qualifying the elements of these systems is a matter of convention, without fundamental significance.
History
First use of numbers
Main article: History of ancient numeral systems
Bones and other artifacts have been discovered with marks cut into them that many believe are tally marks. Some historians suggest that the Lebombo bone (dated about 43,000 years ago) and the Ishango bone (dated about 22,000 to 30,000 years ago) are the oldest arithmetic artifacts but this interpretation is disputed. These tally marks may have been used for counting elapsed time, such as numbers of days, lunar cycles or keeping records of quantities, such as of animals. A perceptual system for quantity thought to underlie numeracy, is shared with other species, a phylogenetic distribution suggesting it would have existed before the emergence of language.
A tallying system has no concept of place value (as in modern decimal notation), which limits its representation of large numbers. Nonetheless, tallying systems are considered the first kind of abstract numeral system.
The earliest unambiguous numbers in the archaeological record are the Mesopotamian base 60 system (c. 3400 BC); place value emerged in it in the 3rd millennium BCE. The earliest known base 10 system dates to 3100 BC in Egypt.
Numerals
Main article: Numeral system
Numbers should be distinguished from numerals, the symbols used to represent numbers. The Egyptians invented the first ciphered numeral system, and the Greeks followed by mapping their counting numbers onto Ionian and Doric alphabets. Roman numerals, a system that used combinations of letters from the Roman alphabet, remained dominant in Europe until the spread of the Hindu–Arabic numeral system around the late 14th century, and the Hindu–Arabic numeral system remains the most common system for representing numbers in the world today. The key to the effectiveness of the system was the symbol for zero, which was developed by ancient Indian mathematicians around 500 AD.
Zero
The first known recorded use of zero dates to AD 628, and appeared in the Brāhmasphuṭasiddhānta, the main work of the Indian mathematician Brahmagupta. He treated 0 as a number and discussed operations involving it, including division by zero. By this time (the 7th century), the concept had clearly reached Cambodia in the form of Khmer numerals, and documentation shows the idea later spreading to China and the Islamic world.
Brahmagupta's Brāhmasphuṭasiddhānta is the first book that mentions zero as a number, hence Brahmagupta is usually considered the first to formulate the concept of zero. He gave rules of using zero with negative and positive numbers, such as "zero plus a positive number is a positive number, and a negative number plus zero is the negative number". The Brāhmasphuṭasiddhānta is the earliest known text to treat zero as a number in its own right, rather than as simply a placeholder digit in representing another number as was done by the Babylonians or as a symbol for a lack of quantity as was done by Ptolemy and the Romans.
The use of 0 as a number should be distinguished from its use as a placeholder numeral in place-value systems. Many ancient texts used 0. Babylonian and Egyptian texts used it. Egyptians used the word nfr to denote zero balance in double entry accounting. Indian texts used a Sanskrit word Shunye or shunya to refer to the concept of void. In mathematics texts this word often refers to the number zero. In a similar vein, Pāṇini (5th century BC) used the null (zero) operator in the Ashtadhyayi, an early example of an algebraic grammar for the Sanskrit language (also see Pingala).
There are other uses of zero before Brahmagupta, though the documentation is not as complete as it is in the Brāhmasphuṭasiddhānta.
Records show that the Ancient Greeks seemed unsure about the status of 0 as a number: they asked themselves "How can 'nothing' be something?" leading to interesting philosophical and, by the Medieval period, religious arguments about the nature and existence of 0 and the vacuum. The paradoxes of Zeno of Elea depend in part on the uncertain interpretation of 0. (The ancient Greeks even questioned whether 1 was a number.)
The late Olmec people of south-central Mexico began to use a symbol for zero, a shell glyph, in the New World, possibly by the 4th century BC but certainly by 40 BC, which became an integral part of Maya numerals and the Maya calendar. Maya arithmetic used base 4 and base 5 written as base 20. George I. Sánchez in 1961 reported a base 4, base 5 "finger" abacus.[better source needed]
By 130 AD, Ptolemy, influenced by Hipparchus and the Babylonians, was using a symbol for 0 (a small circle with a long overbar) within a sexagesimal numeral system otherwise using alphabetic Greek numerals. Because it was used alone, not as just a placeholder, this Hellenistic zero was the first documented use of a true zero in the Old World. In later Byzantine manuscripts of his Syntaxis Mathematica (Almagest), the Hellenistic zero had morphed into the Greek letter Omicron (otherwise meaning 70).
Another true zero was used in tables alongside Roman numerals by 525 (first known use by Dionysius Exiguus), but as a word, nulla meaning nothing, not as a symbol. When division produced 0 as a remainder, nihil, also meaning nothing, was used. These medieval zeros were used by all future medieval computists (calculators of Easter). An isolated use of their initial, N, was used in a table of Roman numerals by Bede or a colleague about 725, a true zero symbol.
Negative numbers
Further information: History of negative numbers
The abstract concept of negative numbers was recognized as early as 100–50 BC in China. The Nine Chapters on the Mathematical Art contains methods for finding the areas of figures; red rods were used to denote positive coefficients, black for negative. The first reference in a Western work was in the 3rd century AD in Greece. Diophantus referred to the equation equivalent to 4x + 20 = 0 (the solution is negative) in Arithmetica, saying that the equation gave an absurd result.
During the 600s, negative numbers were in use in India to represent debts. Diophantus' previous reference was discussed more explicitly by Indian mathematician Brahmagupta, in Brāhmasphuṭasiddhānta in 628, who used negative numbers to produce the general form quadratic formula that remains in use today. However, in the 12th century in India, Bhaskara gives negative roots for quadratic equations but says the negative value "is in this case not to be taken, for it is inadequate; people do not approve of negative roots".
European mathematicians, for the most part, resisted the concept of negative numbers until the 17th century, although Fibonacci allowed negative solutions in financial problems where they could be interpreted as debts (chapter 13 of Liber Abaci, 1202) and later as losses (in Flos). René Descartes called them false roots as they cropped up in algebraic polynomials yet he found a way to swap true roots and false roots as well. At the same time, the Chinese were indicating negative numbers by drawing a diagonal stroke through the right-most non-zero digit of the corresponding positive number's numeral. The first use of negative numbers in a European work was by Nicolas Chuquet during the 15th century. He used them as exponents, but referred to them as "absurd numbers".
As recently as the 18th century, it was common practice to ignore any negative results returned by equations on the assumption that they were meaningless.
Rational numbers
It is likely that the concept of fractional numbers dates to prehistoric times. The Ancient Egyptians used their Egyptian fraction notation for rational numbers in mathematical texts such as the Rhind Mathematical Papyrus and the Kahun Papyrus. Classical Greek and Indian mathematicians made studies of the theory of rational numbers, as part of the general study of number theory. The best known of these is Euclid's Elements, dating to roughly 300 BC. Of the Indian texts, the most relevant is the Sthananga Sutra, which also covers number theory as part of a general study of mathematics.
The concept of decimal fractions is closely linked with decimal place-value notation; the two seem to have developed in tandem. For example, it is common for the Jain math sutra to include calculations of decimal-fraction approximations to pi or the square root of 2.[citation needed] Similarly, Babylonian math texts used sexagesimal (base 60) fractions with great frequency.
Irrational numbers
Further information: History of irrational numbers
The Babylonians, as early as 1800 BCE, demonstrated numerical approximations of irrational quantities such as √2 on clay tablets, with an accuracy analogous to six decimal places, as in the tablet YBC 7289. These values were primarily used for practical calculations in geometry and land measurement. There were practical approximations of irrational numbers in the Indian Shulba Sutras composed between 800 and 500 BC. The first existence proofs of irrational numbers is usually attributed to Pythagoras, more specifically to the Pythagorean Hippasus, who produced a (most likely geometrical) proof of the irrationality of the square root of 2. The story goes that Hippasus discovered irrational numbers when trying to represent the square root of 2 as a fraction. However, Pythagoras believed in the absoluteness of numbers. He could not disprove the existence of irrational numbers, or accept them, so according to legend, he sentenced Hippasus to death by drowning, to impede the spread of this unsettling news.
The 16th century brought final European acceptance of negative integral and fractional numbers. By the 17th century, mathematicians generally used decimal fractions with modern notation. It was not, however, until the 19th century that mathematicians separated irrationals into algebraic and transcendental parts, and once more undertook the scientific study of irrationals. It had remained almost dormant since Euclid. In 1872, the publication of the theories of Karl Weierstrass (by his pupil E. Kossak), Eduard Heine, Georg Cantor, and Richard Dedekind was brought about. In 1869, Charles Méray had taken the same point of departure as Heine, but the theory is generally referred to the year 1872. Weierstrass's method was completely set forth by Salvatore Pincherle (1880), and Dedekind's has received additional prominence through the author's later work (1888) and endorsement by Paul Tannery (1894). Weierstrass, Cantor, and Heine base their theories on infinite series, while Dedekind founds his on the idea of a cut (Schnitt) in the system of real numbers, separating all rational numbers into two groups having certain characteristic properties. The subject has received later contributions at the hands of Weierstrass, Kronecker, and Méray.
The search for roots of quintic and higher degree equations was an important development, the Abel–Ruffini theorem (Ruffini 1799, Abel 1824) showed that they could not be solved by radicals (formulas involving only arithmetical operations and roots). Hence it was necessary to consider the wider set of algebraic numbers (all solutions to polynomial equations). Galois (1832) linked polynomial equations to group theory giving rise to the field of Galois theory.
Simple continued fractions, closely related to irrational numbers (and due to Cataldi, 1613), received attention at the hands of Euler, and at the opening of the 19th century were brought into prominence through the writings of Joseph Louis Lagrange. Other noteworthy contributions have been made by Druckenmüller (1837), Kunze (1857), Lemke (1870), and Günther (1872). Ramus first connected the subject with determinants, resulting, with the subsequent contributions of Heine, Möbius, and Günther, in the theory of Kettenbruchdeterminanten.
Transcendental numbers and reals
Further information: History of π
The existence of transcendental numbers was first established by Liouville (1844, 1851). Hermite proved in 1873 that e is transcendental and Lindemann proved in 1882 that π is transcendental. Finally, Cantor showed that the set of all real numbers is uncountably infinite but the set of all algebraic numbers is countably infinite, so there is an uncountably infinite number of transcendental numbers.
Infinity and infinitesimals
Further information: History of infinity
The earliest known conception of mathematical infinity appears in the Yajur Veda, an ancient Indian script, which at one point states, "If you remove a part from infinity or add a part to infinity, still what remains is infinity." Infinity was a popular topic of philosophical study among the Jain mathematicians c. 400 BC. They distinguished between five types of infinity: infinite in one and two directions, infinite in area, infinite everywhere, and infinite perpetually. The symbol is often used to represent an infinite quantity.
Aristotle defined the traditional Western notion of mathematical infinity. He distinguished between actual infinity and potential infinity—the general consensus being that only the latter had true value. Galileo Galilei's Two New Sciences discussed the idea of one-to-one correspondences between infinite sets. But the next major advance in the theory was made by Georg Cantor; in 1895 he published a book about his new set theory, introducing, among other things, transfinite numbers and formulating the continuum hypothesis.
In the 1960s, Abraham Robinson showed how infinitely large and infinitesimal numbers can be rigorously defined and used to develop the field of nonstandard analysis. The system of hyperreal numbers represents a rigorous method of treating the ideas about infinite and infinitesimal numbers that had been used casually by mathematicians, scientists, and engineers ever since the invention of infinitesimal calculus by Newton and Leibniz.
A modern geometrical version of infinity is given by projective geometry, which introduces "ideal points at infinity", one for each spatial direction. Each family of parallel lines in a given direction is postulated to converge to the corresponding ideal point. This is closely related to the idea of vanishing points in perspective drawing.
Complex numbers
Further information: History of complex numbers
The earliest fleeting reference to square roots of negative numbers occurred in the work of the mathematician and inventor Heron of Alexandria in the 1st century AD, when he considered the volume of an impossible frustum of a pyramid. They became more prominent when in the 16th century closed formulas for the roots of third and fourth degree polynomials were discovered by Italian mathematicians such as Niccolò Fontana Tartaglia and Gerolamo Cardano. It was soon realized that these formulas, even if one was only interested in real solutions, sometimes required the manipulation of square roots of negative numbers.
This was doubly unsettling since they did not even consider negative numbers to be on firm ground at the time. When René Descartes coined the term "imaginary" for these quantities in 1637, he intended it as derogatory. (See imaginary number for a discussion of the "reality" of complex numbers.) A further source of confusion was that the equation
seemed capriciously inconsistent with the algebraic identity
which is valid for positive real numbers a and b, and was also used in complex number calculations with one of a, b positive and the other negative. The incorrect use of this identity, and the related identity
in the case when both a and b are negative even bedeviled Euler. This difficulty eventually led him to the convention of using the special symbol i in place of to guard against this mistake.
The 18th century saw the work of Abraham de Moivre and Leonhard Euler. De Moivre's formula (1730) states:
while Euler's formula of complex analysis (1748) gave us:
The existence of complex numbers was not completely accepted until Caspar Wessel described the geometrical interpretation in 1799. Carl Friedrich Gauss rediscovered and popularized it several years later, and as a result the theory of complex numbers received a notable expansion. The idea of the graphic representation of complex numbers had appeared, however, as early as 1685, in Wallis's De algebra tractatus.
In the same year, Gauss provided the first generally accepted proof of the fundamental theorem of algebra, showing that every polynomial over the complex numbers has a full set of solutions in that realm. Gauss studied complex numbers of the form a + bi, where a and b are integers (now called Gaussian integers) or rational numbers. His student, Gotthold Eisenstein, studied the type a + bω, where ω is a complex root of x3 − 1 = 0 (now called Eisenstein integers). Other such classes (called cyclotomic fields) of complex numbers derive from the roots of unity xk − 1 = 0 for higher values of k. This generalization is largely due to Ernst Kummer, who also invented ideal numbers, which were expressed as geometrical entities by Felix Klein in 1893.
In 1850 Victor Alexandre Puiseux took the key step of distinguishing between poles and branch points, and introduced the concept of essential singular points.[clarification needed] This eventually led to the concept of the extended complex plane.
Prime numbers
Prime numbers have been studied throughout recorded history.[citation needed] They are positive integers that are divisible only by 1 and themselves. Euclid devoted one book of the Elements to the theory of primes; in it he proved the infinitude of the primes and the fundamental theorem of arithmetic, and presented the Euclidean algorithm for finding the greatest common divisor of two numbers.
In 240 BC, Eratosthenes used the Sieve of Eratosthenes to quickly isolate prime numbers. But most further development of the theory of primes in Europe dates to the Renaissance and later eras.[citation needed]
In 1796, Adrien-Marie Legendre conjectured the prime number theorem, describing the asymptotic distribution of primes. Other results concerning the distribution of the primes include Euler's proof that the sum of the reciprocals of the primes diverges, and the Goldbach conjecture, which claims that any sufficiently large even number is the sum of two primes. Yet another conjecture related to the distribution of prime numbers is the Riemann hypothesis, formulated by Bernhard Riemann in 1859. The prime number theorem was finally proved by Jacques Hadamard and Charles de la Vallée-Poussin in 1896. Goldbach and Riemann's conjectures remain unproven and unrefuted.
Main classification
"Number system" redirects here. For systems which express numbers, see Numeral system.
See also: List of types of numbers
Numbers can be classified into sets, called number sets or number systems, such as the natural numbers and the real numbers. The main number systems are as follows:
Main number systems
| Symbol | Name | Examples/Explanation |
| | Natural numbers | 0, 1, 2, 3, 4, 5, ... or 1, 2, 3, 4, 5, ... or are sometimes used. |
| | Integers | ..., −5, −4, −3, −2, −1, 0, 1, 2, 3, 4, 5, ... |
| | Rational numbers | a/b where a and b are integers and b is not 0 |
| | Real numbers | The limit of a convergent sequence of rational numbers |
| | Complex numbers | a + bi where a and b are real numbers and i is a formal square root of −1 |
Each of these number systems is a subset of the next one. So, for example, a rational number is also a real number, and every real number is also a complex number. This can be expressed symbolically as
: .
A more complete list of number sets appears in the following diagram.
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
--- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- | | Number systems | Complex | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --- --- --- --- --- --- --- --- --- --- --- --- --- --- | Real | | | | | | | | | | | | | | | | | | | | | | | --- --- --- --- --- --- --- --- --- --- | | | | | | | | | | | | | | | | | | | | | | --- --- --- --- --- --- --- --- --- --- | | Rational | | | | | | | | | | | | | --- --- --- --- --- | | | | | | | | | | | | --- --- --- --- --- | | Integer | | | | | | | | | --- --- --- | | | | | | | | --- --- --- | | Natural | | | | Zero: 0 | | One: 1 | | Prime numbers | | Composite numbers | | | | Negative integers | | | | | | | | | | | --- --- --- | | Fraction | | | | Finite decimal | | Dyadic (finite binary) | | Repeating decimal | | | | | | | | | | | | | --- --- | Irrational | | | | Algebraic irrational | | Irrational period | | Transcendental | | | | | | Imaginary | | | |
Natural numbers
Main article: Natural number
The most familiar numbers are the natural numbers (sometimes called whole numbers or counting numbers): 1, 2, 3, and so on. Traditionally, the sequence of natural numbers started with 1 (0 was not even considered a number for the Ancient Greeks.) However, in the 19th century, set theorists and other mathematicians started including 0 (cardinality of the empty set, i.e. 0 elements, where 0 is thus the smallest cardinal number) in the set of natural numbers. Today, different mathematicians use the term to describe both sets, including 0 or not. The mathematical symbol for the set of all natural numbers is N, also written , and sometimes or when it is necessary to indicate whether the set should start with 0 or 1, respectively.
In the base 10 numeral system, in almost universal use today for mathematical operations, the symbols for natural numbers are written using ten digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9. The radix or base is the number of unique numerical digits, including zero, that a numeral system uses to represent numbers (for the decimal system, the radix is 10). In this base 10 system, the rightmost digit of a natural number has a place value of 1, and every other digit has a place value ten times that of the place value of the digit to its right.
In set theory, which is capable of acting as an axiomatic foundation for modern mathematics, natural numbers can be represented by classes of equivalent sets. For instance, the number 3 can be represented as the class of all sets that have exactly three elements. Alternatively, in Peano Arithmetic, the number 3 is represented as sss0, where s is the "successor" function (i.e., 3 is the third successor of 0). Many different representations are possible; all that is needed to formally represent 3 is to inscribe a certain symbol or pattern of symbols three times.
Integers
Main article: Integer
The negative of a positive integer is defined as a number that produces 0 when it is added to the corresponding positive integer. Negative numbers are usually written with a negative sign (a minus sign). As an example, the negative of 7 is written −7, and 7 + (−7) = 0. When the set of negative numbers is combined with the set of natural numbers (including 0), the result is defined as the set of integers, Z also written . Here the letter Z comes from German Zahl 'number'. The set of integers forms a ring with the operations addition and multiplication.
The natural numbers form a subset of the integers. As there is no common standard for the inclusion or not of zero in the natural numbers, the natural numbers without zero are commonly referred to as positive integers, and the natural numbers with zero are referred to as non-negative integers.
Rational numbers
Main article: Rational number
A rational number is a number that can be expressed as a fraction with an integer numerator and a positive integer denominator. Negative denominators are allowed, but are commonly avoided, as every rational number is equal to a fraction with positive denominator. Fractions are written as two integers, the numerator and the denominator, with a dividing bar between them. The fraction m/n represents m parts of a whole divided into n equal parts. Two different fractions may correspond to the same rational number; for example 1/2 and 2/4 are equal, that is:
In general,
: if and only if
If the absolute value of m is greater than n (supposed to be positive), then the absolute value of the fraction is greater than 1. Fractions can be greater than, less than, or equal to 1 and can also be positive, negative, or 0. The set of all rational numbers includes the integers since every integer can be written as a fraction with denominator 1. For example −7 can be written −7/1. The symbol for the rational numbers is Q (for quotient), also written .
Real numbers
Main article: Real number
The symbol for the real numbers is R, also written as They include all the measuring numbers. Every real number corresponds to a point on the number line. The following paragraph will focus primarily on positive real numbers. The treatment of negative real numbers is according to the general rules of arithmetic and their denotation is simply prefixing the corresponding positive numeral by a minus sign, e.g. −123.456.
Most real numbers can only be approximated by decimal numerals, in which a decimal point is placed to the right of the digit with place value 1. Each digit to the right of the decimal point has a place value one-tenth of the place value of the digit to its left. For example, 123.456 represents 123456/1000, or, in words, one hundred, two tens, three ones, four tenths, five hundredths, and six thousandths. A real number can be expressed by a finite number of decimal digits only if it is rational and its fractional part has a denominator whose prime factors are 2 or 5 or both, because these are the prime factors of 10, the base of the decimal system. Thus, for example, one half is 0.5, one fifth is 0.2, one-tenth is 0.1, and one fiftieth is 0.02. Representing other real numbers as decimals would require an infinite sequence of digits to the right of the decimal point. If this infinite sequence of digits follows a pattern, it can be written with an ellipsis or another notation that indicates the repeating pattern. Such a decimal is called a repeating decimal. Thus 1/3 can be written as 0.333..., with an ellipsis to indicate that the pattern continues. Forever repeating 3s are also written as 0.3.
It turns out that these repeating decimals (including the repetition of zeroes) denote exactly the rational numbers, i.e., all rational numbers are also real numbers, but it is not the case that every real number is rational. A real number that is not rational is called irrational. A famous irrational real number is the π, the ratio of the circumference of any circle to its diameter. When pi is written as
as it sometimes is, the ellipsis does not mean that the decimals repeat (they do not), but rather that there is no end to them. It has been proved that π is irrational. Another well-known number, proven to be an irrational real number, is
the square root of 2, that is, the unique positive real number whose square is 2. Both these numbers have been approximated (by computer) to trillions ( 1 trillion = 1012 = 1,000,000,000,000 ) of digits.
Not only these prominent examples but almost all real numbers are irrational and therefore have no repeating patterns and hence no corresponding decimal numeral. They can only be approximated by decimal numerals, denoting rounded or truncated real numbers. Any rounded or truncated number is necessarily a rational number, of which there are only countably many. All measurements are, by their nature, approximations, and always have a margin of error. Thus 123.456 is considered an approximation of any real number greater or equal to 1234555/10000 and strictly less than 1234565/10000 (rounding to 3 decimals), or of any real number greater or equal to 123456/1000 and strictly less than 123457/1000 (truncation after the 3. decimal). Digits that suggest a greater accuracy than the measurement itself does, should be removed. The remaining digits are then called significant digits. For example, measurements with a ruler can seldom be made without a margin of error of at least 0.001 m. If the sides of a rectangle are measured as 1.23 m and 4.56 m, then multiplication gives an area for the rectangle between 5.614591 m2 and 5.603011 m2. Since not even the second digit after the decimal place is preserved, the following digits are not significant. Therefore, the result is usually rounded to 5.61.
Just as the same fraction can be written in more than one way, the same real number may have more than one decimal representation. For example, 0.999..., 1.0, 1.00, 1.000, ..., all represent the natural number 1. A given real number has only the following decimal representations: an approximation to some finite number of decimal places, an approximation in which a pattern is established that continues for an unlimited number of decimal places or an exact value with only finitely many decimal places. In this last case, the last non-zero digit may be replaced by the digit one smaller followed by an unlimited number of 9s, or the last non-zero digit may be followed by an unlimited number of zeros. Thus the exact real number 3.74 can also be written 3.7399999999... and 3.74000000000.... Similarly, a decimal numeral with an unlimited number of 0s can be rewritten by dropping the 0s to the right of the rightmost nonzero digit, and a decimal numeral with an unlimited number of 9s can be rewritten by increasing by one the rightmost digit less than 9, and changing all the 9s to the right of that digit to 0s. Finally, an unlimited sequence of 0s to the right of a decimal place can be dropped. For example, 6.849999999999... = 6.85 and 6.850000000000... = 6.85. Finally, if all of the digits in a numeral are 0, the number is 0, and if all of the digits in a numeral are an unending string of 9s, you can drop the nines to the right of the decimal place, and add one to the string of 9s to the left of the decimal place. For example, 99.999... = 100.
The real numbers also have an important but highly technical property called the least upper bound property.
It can be shown that any ordered field, which is also complete, is isomorphic to the real numbers. The real numbers are not, however, an algebraically closed field, because they do not include a solution (often called a square root of minus one) to the algebraic equation .
Complex numbers
Main article: Complex number
Moving to a greater level of abstraction, the real numbers can be extended to the complex numbers. This set of numbers arose historically from trying to find closed formulas for the roots of cubic and quadratic polynomials. This led to expressions involving the square roots of negative numbers, and eventually to the definition of a new number: a square root of −1, denoted by i, a symbol assigned by Leonhard Euler, and called the imaginary unit. The complex numbers consist of all numbers of the form
where a and b are real numbers. Because of this, complex numbers correspond to points on the complex plane, a vector space of two real dimensions. In the expression a + bi, the real number a is called the real part and b is called the imaginary part. If the real part of a complex number is 0, then the number is called an imaginary number or is referred to as purely imaginary; if the imaginary part is 0, then the number is a real number. Thus the real numbers are a subset of the complex numbers. If the real and imaginary parts of a complex number are both integers, then the number is called a Gaussian integer. The symbol for the complex numbers is C or .
The fundamental theorem of algebra asserts that the complex numbers form an algebraically closed field, meaning that every polynomial with complex coefficients has a root in the complex numbers. Like the reals, the complex numbers form a field, which is complete, but unlike the real numbers, it is not ordered. That is, there is no consistent meaning assignable to saying that i is greater than 1, nor is there any meaning in saying that i is less than 1. In technical terms, the complex numbers lack a total order that is compatible with field operations.
Subclasses of the integers
Even and odd numbers
Main article: Even and odd numbers
An even number is an integer that is "evenly divisible" by two, that is divisible by two without remainder; an odd number is an integer that is not even. (The old-fashioned term "evenly divisible" is now almost always shortened to "divisible".) Any odd number n may be constructed by the formula n = 2k + 1, for a suitable integer k. Starting with k = 0, the first non-negative odd numbers are {1, 3, 5, 7, ...}. Any even number m has the form m = 2k where k is again an integer. Similarly, the first non-negative even numbers are {0, 2, 4, 6, ...}.
Prime numbers
Main article: Prime number
A prime number, often shortened to just prime, is an integer greater than 1 that is not the product of two smaller positive integers. The first few prime numbers are 2, 3, 5, 7, and 11. There is no such simple formula as for odd and even numbers to generate the prime numbers. The primes have been widely studied for more than 2000 years and have led to many questions, only some of which have been answered. The study of these questions belongs to number theory. Goldbach's conjecture is an example of a still unanswered question: "Is every even number the sum of two primes?"
One answered question, as to whether every integer greater than one is a product of primes in only one way, except for a rearrangement of the primes, was confirmed; this proven claim is called the fundamental theorem of arithmetic. A proof appears in Euclid's Elements.
Other classes of integers
Many subsets of the natural numbers have been the subject of specific studies and have been named, often after the first mathematician that has studied them. Example of such sets of integers are Fibonacci numbers and perfect numbers. For more examples, see Integer sequence.
Subclasses of the complex numbers
Algebraic, irrational and transcendental numbers
Algebraic numbers are those that are a solution to a polynomial equation with integer coefficients. Real numbers that are not rational numbers are called irrational numbers. Complex numbers which are not algebraic are called transcendental numbers. The algebraic numbers that are solutions of a monic polynomial equation with integer coefficients are called algebraic integers.
Periods and exponential periods
Main article: Period (algebraic geometry)
A period is a complex number that can be expressed as an integral of an algebraic function over an algebraic domain. The periods are a class of numbers which includes, alongside the algebraic numbers, many well known mathematical constants such as the number π. The set of periods form a countable ring and bridge the gap between algebraic and transcendental numbers.
The periods can be extended by permitting the integrand to be the product of an algebraic function and the exponential of an algebraic function. This gives another countable ring: the exponential periods. The number e as well as Euler's constant are exponential periods.
Constructible numbers
Motivated by the classical problems of constructions with straightedge and compass, the constructible numbers are those complex numbers whose real and imaginary parts can be constructed using straightedge and compass, starting from a given segment of unit length, in a finite number of steps.
Computable numbers
Main article: Computable number
A computable number, also known as recursive number, is a real number such that there exists an algorithm which, given a positive number n as input, produces the first n digits of the computable number's decimal representation. Equivalent definitions can be given using μ-recursive functions, Turing machines or λ-calculus. The computable numbers are stable for all usual arithmetic operations, including the computation of the roots of a polynomial, and thus form a real closed field that contains the real algebraic numbers.
The computable numbers may be viewed as the real numbers that may be exactly represented in a computer: a computable number is exactly represented by its first digits and a program for computing further digits. However, the computable numbers are rarely used in practice. One reason is that there is no algorithm for testing the equality of two computable numbers. More precisely, there cannot exist any algorithm which takes any computable number as an input, and decides in every case if this number is equal to zero or not.
The set of computable numbers has the same cardinality as the natural numbers. Therefore, almost all real numbers are non-computable. However, it is very difficult to produce explicitly a real number that is not computable.
Extensions of the concept
p-adic numbers
Main article: p-adic number
The p-adic numbers may have infinitely long expansions to the left of the decimal point, in the same way that real numbers may have infinitely long expansions to the right. The number system that results depends on what base is used for the digits: any base is possible, but a prime number base provides the best mathematical properties. The set of the p-adic numbers contains the rational numbers, but is not contained in the complex numbers.
The elements of an algebraic function field over a finite field and algebraic numbers have many similar properties (see Function field analogy). Therefore, they are often regarded as numbers by number theorists. The p-adic numbers play an important role in this analogy.
Hypercomplex numbers
Main article: hypercomplex number
Some number systems that are not included in the complex numbers may be constructed from the real numbers in a way that generalize the construction of the complex numbers. They are sometimes called hypercomplex numbers. They include the quaternions , introduced by Sir William Rowan Hamilton, in which multiplication is not commutative, the octonions , in which multiplication is not associative in addition to not being commutative, and the sedenions , in which multiplication is not alternative, neither associative nor commutative. The hypercomplex numbers include one real unit together with imaginary units, for which n is a non-negative integer. For example, quaternions can generally represented using the form
where the coefficients a, b, c, d are real numbers, and i, j, k are 3 different imaginary units.
Each hypercomplex number system is a subset of the next hypercomplex number system of double dimensions obtained via the Cayley–Dickson construction. For example, the 4-dimensional quaternions are a subset of the 8-dimensional quaternions , which are in turn a subset of the 16-dimensional sedenions , in turn a subset of the 32-dimensional trigintaduonions , and ad infinitum with dimensions, with n being any non-negative integer. Including the complex and real numbers and their subsets, this can be expressed symbolically as:
Alternatively, starting from the real numbers , which have zero complex units, this can be expressed as
with containing dimensions.
Transfinite numbers
Main article: transfinite number
For dealing with infinite sets, the natural numbers have been generalized to the ordinal numbers and to the cardinal numbers. The former gives the ordering of the set, while the latter gives its size. For finite sets, both ordinal and cardinal numbers are identified with the natural numbers. In the infinite case, many ordinal numbers correspond to the same cardinal number.
Nonstandard numbers
Hyperreal numbers are used in non-standard analysis. The hyperreals, or nonstandard reals (usually denoted as R), denote an ordered field that is a proper extension of the ordered field of real numbers R and satisfies the transfer principle. This principle allows true first-order statements about R to be reinterpreted as true first-order statements about R.
Superreal and surreal numbers extend the real numbers by adding infinitesimally small numbers and infinitely large numbers, but still form fields.
See also
Mathematics portal
Concrete number
List of numbers
List of types of numbers
List of books on history of number systems
Mathematical constant – Fixed number that has received a name
Complex numbers
Numerical cognition
Orders of magnitude
Physical constant – Universal and unchanging physical quantity
Physical quantity – Measurable property of a material or system
Pi – Number, approximately 3.14
Positional notation – Method for representing or encoding numbers
Prime number – Number divisible only by 1 or itself
Scalar (mathematics) – Elements of a field, e.g. real numbers, in the context of linear algebra
Subitizing and counting
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^ a b Bulliet, Richard; Crossley, Pamela; Headrick, Daniel; Hirsch, Steven; Johnson, Lyman (2010). The Earth and Its Peoples: A Global History, Volume 1. Cengage Learning. p. 192. ISBN 978-1-4390-8474-8. Archived from the original on 28 January 2017. Retrieved 16 May 2017. Indian mathematicians invented the concept of zero and developed the "Arabic" numerals and system of place-value notation used in most parts of the world today
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^ Staszkow, Ronald; Robert Bradshaw (2004). The Mathematical Palette (3rd ed.). Brooks Cole. p. 41. ISBN 0-534-40365-4.
^ Smith, David Eugene (1958). History of Modern Mathematics. Dover Publications. p. 259. ISBN 0-486-20429-4. {{cite book}}: ISBN / Date incompatibility (help)
^ "Classical Greek culture (article)". Khan Academy. Archived from the original on 4 May 2022. Retrieved 4 May 2022.
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Krulwich, Robert (22 July 2011). "What's the World's Favorite Number?". NPR. Archived from the original on 18 May 2021. Retrieved 17 September 2011.; "Cuddling With 9, Smooching With 8, Winking At 7". NPR. 21 August 2011. Archived from the original on 6 November 2018. Retrieved 17 September 2011.
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12580 | https://wpcdn.web.wsu.edu/wp-labs/uploads/sites/147/2018/10/MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.pdf | Laplace's Equation with Boundary Conditions in One Dimension To date we have used Gauss's Law and the Method of Images to find the potential and electric field for rather symmetric geometries. For more complex geometries, V(x,y,z) can often be found by solving Laplace's equa-tion: ∇2 V(x,y,z) = 0. Although the number of solutions to Laplace's equation is infinite, knowing either the potential or the field along the boundaries of the region of interest ("The Boundary Conditions") normally guarantees a unique solution (the uniqueness theorem). Solving differential equations can be relatively difficult. In this module, we will restrict ourselves to simple 1-D systems for which solutions are readily derived. After learning what we can from these, we will move on to more complicated systems where we "up the ante".
In this context, a one-dimensional problem does not mean that our fields exist in a one-dimensional vector space. Our electric fields are vectors in 3-space, as they always are. Rather, the direction and magnitude of the electric fields only depend on one variable. In Cartesian space, this could be x. In this case, the direction and magnitude of the electric field would not depend on y or z. Similarly, the value of the potential would depend on x and not y or z. Laplace’s Equation in One Dimension—Infinite Parallel Plates In the infinite parallel plate geometry, the fields and potentials depend on only one Cartesian variable, say x. The boundaries of the region of interest are planes parallel to the y-z plane, which we will assume intersect the x-axis at points x = x1 and x = x2. We will assume that V(x1, y, z) = V1 (a specific value of potential) for all values of y and z. Similarly V(x2,y,z) = V2. Between x1 and x2, the potential will be some function V(x). This is the geometry of a parallel plate capacitor with plates that extend to infinity in the y and z directions. You will remember from your work with Coulomb’s Law and Gauss’s Law that V(x) in this system is proportional to x and the E field is constant in magnitude and direction (± x ! — in the direction of decreasing potential).
In 1-D Cartesian coordinates, Laplace’s equation takes the form d2 V[x] d x2 = 0 (a) Although you probably know the solution, use M’s DSolve[V’’[x] == 0, V[x], x] command to solve this equation. By NOT inserting the BCs, we will see that we can generate a general solution. The double prime after the V in the first argument indicates the second derivative. (The double prime is not the quotation mark, “, it is two hits on the apostrophe key, ’ ’.) We seek V[x], the second argument of the command, and the derivatives are taken with respect to x, the third argument. To refer to the solution later, set the variable sol to the result of the DSolve[] command. ( Input code below ) ClearAll["Global"] ( Leave the ClearAll command ) M returns a list of solutions (in the case ONLY ONE!). The entire list is enclosed in brackets, and each solution is enclosed in its own, additional brackets. The solution {V[x] → C + x C} is part of this larger list, so we get nested brackets. (b) Execute sol; this should get you this single bracket element of sol: ( Input code below ) 2 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb Technically, M treats the solution sol as a "rule" that can be applied in various ways. We want to convert this rule to a function. We can use way the "ReplaceAll" command, usually written "/." (without the quotes) to replace V[x] with the rule given by sol. (c) Type in and execute V[x]/.sol ( Input code below ) This is still not a function that we can plot.
(d) To get a function, we need to set a real function (in x_) equal to V[x]. This adds an extra step. (use % for the above result to achieve this definition, that is, V[x_] = %.) ( Input code below ) (e) Just as a check enter and execute the “new” V[x] ( Input code below ) As expected, this solution is a linear function of x. We started with V’’[x], the second derivative. M had to integrate twice to find the solution. C and C are the two constants of integration. (f) To meet our boundary conditions, we require V[x1] = V1 and V[x2] = V2. Use these two require-ments and M's Solve[] command to determine the values C and C. If the uniqueness theorem applies to this problem (It Does!), only one choice of C and C will work. Like DSolve[], Solve[] returns a nested list of solutions. We must specify which solution we want, even if there is only one. SO: Use Solve and extract the two constants C and C that satisfy our BCs. Then use the ReplaceAll option (or your two hands) to input these values into your V[x] function. ( Input code below ) Handling M’s constants of integration is tricky. Here is another way to do it. Introducing C1 and C2 as temporary constants gets around M’s touchiness regarding the symbol “C” The ReplaceAll trick works only once per M session unless you change the constant names. We can’t change the names of C and C. If you get an error message, quit M and re-execute only one version of of the ReplaceAll command.
Study, but do not execute code below.
sol3=Solve[{V[x1] ⩵V1,V[x2]⩵V2}, {C,C}] C1= C/.sol3 C2 = C/.sol3 V[x_] = C1 + C2 x MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb 3 Handling M s constants of integration is tricky. Here is another way to do it. Introducing C1 and C2 as temporary constants gets around M’s touchiness regarding the symbol “C” The ReplaceAll trick works only once per M session unless you change the constant names. We can’t change the names of C and C. If you get an error message, quit M and re-execute only one version of of the ReplaceAll command.
Study, but do not execute code below.
sol3=Solve[{V[x1] ⩵V1,V[x2]⩵V2}, {C,C}] C1= C/.sol3 C2 = C/.sol3 V[x_] = C1 + C2 x (g) To verify that this choice of C and C satisfies the boundary conditions, evaluate V[x1] and V[x2] explicitly. [You are trying to show that V[x1] = V1 and V[x2] = V2. The Simplify[] command may be useful here. For instance: Simplify[V[x1]]. (This also works: V[x1]//Simplify ) // = PostFix) ( Input code below ) We see that the BC's are satisfied. If you get something like C+x1 C, you need to make sure V[x_] is defined properly in terms of x1, x2, V1 and V2.
(h) Now use DSolve with BCs inserted (notice how it saves a lot of trouble) to find the potential between the plates where again (code will look something like this: sol2=DSolve[{V’’[x]⩵0,V[x1] ⩵V1, V[x2] ⩵V2}, V[x],x] Just a reminder: the plates are located at x = x1 and x = x2. V(x1, y, z) = V1 and V(x2,y,z) = V2. ( Input code below ) ClearAll[""] ( Leave the ClearAll statement.
We are starting over. ) Same as V[x] above. Here we have let M do all the work.
(i) Griffith's ( in Section 3.1.2) claims that all solutions V[x] of the 1-D Laplace's equation are feature-less, and the potential at x is the average of the potentials at x+a and x-a; it has no minimum or maximum except at the boundaries. [You can think of a being small but it’s not necessary].
We therefore expect: V[xo] = V[xo-a] + V[xo+a] 2 Use M to see if Wolfram agrees. (Use the test: == ; might want to use Simplify.) ( Input code below ) So the statement that the potential at x is the average of the potentials at x+a and x–a is true.
This general result is important, because it shows that the solutions of Laplace’s equation have “no local minima or maxima”. All the minima and maxima potential values lie on the boundaries. This is also the basis of the “relaxation method” for numerically solving Laplace’s equation in Cartesian coordinates.
4 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb So the statement that the potential at x is the average of the potentials at x+a and x–a is true.
This general result is important, because it shows that the solutions of Laplace’s equation have “no local minima or maxima”. All the minima and maxima potential values lie on the boundaries. This is also the basis of the “relaxation method” for numerically solving Laplace’s equation in Cartesian coordinates.
(j) For laughs, show that this is true for some consistent (numerical) choices of x1, x2, xo (located between x1 and x2), V1, and V2, and some arbitrary a. I chose: x1 = 1; x2 = 2; V1 = 10; V2 = 100; xo = 1.5; a = 0.02; ( Input code below ) (k) Now Plot the Solution for x1 < x < x2. ( Input code below ) (l) Although somewhat mundane, interpret your results. (Is the result consistent with your previous work in this geometry? — think parallel plate capacitor.) (m) Find the E Field. In 3D, EE = –Grad[V]; This yields a 3D Vector.
The electric field amplitude should be MINUS the slope of the potential plot times (–1), which is about –(90 V)/(1 m) or –90 V/m. ( Input code below ) Clear [xo, x1, x2, V1, V2, a] ( Leave the Clear statement ) EE[x] is CONSTANT VECTOR and points from the more positive plate towards the less positive plate (in the –x , direction). The E Field is UNIFORM between the plates. Everything looks consistent with our previous Coulomb’s Law/Gauss’s Law approach.
A general expression for just the x-component of the E field (the x-component being the only non-zero component) is given below. MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb 5 EE[x] is CONSTANT VECTOR and points from the more positive plate towards the less positive plate (in the –x , direction). The E Field is UNIFORM between the plates. Everything looks consistent with our previous Coulomb’s Law/Gauss’s Law approach.
A general expression for just the x-component of the E field (the x-component being the only non-zero component) is given below. ( Execute code below ) V[x] EE[x_] = -D[V[x], x] ( note that this is the - of the slope of V[x] ) So lets rewrite: EE[x] = V2-V1 x2-x1 x ,. For V2 > V1 and x2>x1, EE[x] points in the + x direction as it should.
Not much more to say here. BUT: by going through this simple 1D potential problem using Laplace's Equation we get an understanding of the importance of BCs, the nature of the resulting potential, and the simple connection of the E-field to this V.
Laplace’s Equation in One Dimension—Concentric Cylinders In systems with cylindrical symmetry, the potential is a function of the radial coordinate, s, and independent of ϕ and z. We will seek the potential between two circular cylinders which serve as boundaries, where the boundaries are equipotentials. The boundary conditions then take the form V(s1) = V1 and V(s2) = V2. Ignoring the terms in ϕ and z, Laplace’s equation in cylindrical coordinates is given by: 1 s ∂ ∂s s ∂V ∂s = ∂2V ∂s2 + 1 s ∂V ∂s = 0 By convention, we multiply each term by s before attempting a solution. Factors of s are often easier to work with than factors of (1/s), that is, sV’’[s] + V’[s] ⩵ 0 (n) Use M to find V[s] using : DSolve[{sV''[s] + V'[s] ⩵ 0, V[s1] ⩵V1,V[s2]⩵V2 }, V[s], s]. WE'RE putting in the BCs into DSolve from the start. This gives us the particular solution. Is your solution consistent with what you found from Gauss’s Law earlier in the semester? Comment.
6 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb ( Input code below ) ClearAll"Global"( Leave the ClearAll statement ) <Enter comment in this text cell> (o) Verify that these expressions satisfy the boundary conditions (i.e., does V[s1] = V1, etc.??) Comment.
( Input code below ) <Enter comment in this text cell> (p) Plot V[s] for the co-axial cylinders. For plotting, I assumed: s1 = 1; s2 = 2; V1 = 10; V2 = 100; ( Input code below ) Note that for the given constants s1, s2, V1, V2, the slope of the potential function V[s] is monotonically decreasing; as expected; no min or max in V[s] occurs except at the endpoints (the boundaries). (q) Clear the constants (s1, s2, V1, V2) and find the ONE DIMENSIONAL E field from V[s].
Use M’s Grad function in Cylindrical Coordinates.
Here is some help: M writes it as: Grad[f[r,θ,z],{r,θ,z},”Cylindrical”], where f is a general, undefined, scalar function in cylindrical coordinates. Evaluate the following: ( Execute code below ) Clear[s1, s2, V1, V2] Grad[f[s, ϕ, z], {s, ϕ, z}, "Cylindrical"] M assumes that EACH component of the gradient can have a dependence on all three coordinates. The result is a 3D Vector which is easily translated into: ∂ ∂s f[s, ϕ, z], ∂ ∂ϕ f[s,ϕ,z] s , ∂ ∂z f[s, ϕ, z] Note M’s notation: [f(1,0,0)[s, ϕ, z] = ∂ ∂s f[s, ϕ, z], etc.] MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb 7 M assumes that EACH component of the gradient can have a dependence on all three coordinates. The result is a 3D Vector which is easily translated into: ∂ ∂s f[s, ϕ, z], ∂ ∂ϕ f[s,ϕ,z] s , ∂ ∂z f[s, ϕ, z] Note M’s notation: [f(1,0,0)[s, ϕ, z] = ∂ ∂s f[s, ϕ, z], etc.] For our task, I suggest that you simply enter: Ecylindrical[s_] = –Grad[V[s],{s,ϕ,z},"Cylindrical"] and execute. Don't overlook the – sign. The lack of ϕ and z dependence in V does its magic (i.e., the ϕ and z components come out zero.) ( Input code below ) Repeat: Since V[s] is a function of s only, only the s component of the Gradient is non zero ∂ ∂ϕ V[s] and ∂ ∂z V[s] both = 0.
Given the symmetry of the problem we are not surprised to see that Ecylindrical is: A function of s only AND The only non-zero component is the s ! component.
(r) Plot the 2D EE field using Vector Field. (Since the field does not depend on z, consider z = 0). REMEMBER: M requires that we transform EEcylindrical into EEcartesian for plotting. ( Execute the code below to express the field in terms of the Cartesian coordinates x and y ) EECartesian[s_] = TransformedField[ "Cylindrical" →"Cartesian", Ecylindrical[s], {s, ϕ, ζ} →{x, y, z}] ( does not like a common z!!! so we write ζ instead of z in {s,ϕ,ζ} ) EECartesian2D[x_, y_] = {EECartesian[s], EECartesian[s]} ( selects out the x,y components ) Now put in some values for the constants and plot ( Input code below ) Remember this is a 2D PLOT. It represents a cut through the cylinders normal to the z axis at (any) particular z, say z = 0. The E vectors are all radial and only are defined between the electrodes. By default, M positions the middle of each arrow at the location of the vector. Therefore the heads and tails will appear to cross the boundaries at points. The middle of each arrow lies between the boundaries.
For our assumed constants, E points from the outer more positive electrode (cylinder), inward. E increases in intensity (the vectors get longer) as one moves from s2 into s1 This is consistent with the 8 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb Remember this is a 2D PLOT. It represents a cut through the cylinders normal to the z axis at (any) particular z, say z = 0. The E vectors are all radial and only are defined between the electrodes. By default, M positions the middle of each arrow at the location of the vector. Therefore the heads and tails will appear to cross the boundaries at points. The middle of each arrow lies between the boundaries.
For our assumed constants, E points from the outer more positive electrode (cylinder), inward. E increases in intensity (the vectors get longer) as one moves from s2 into s1. This is consistent with the SLOPE of V[s] (largest at s = s1). (Again, don’t forget the – sign in E = – Grad[V] (so the E vectors point towards smaller, decreasing s). Here is a copy/paste of the V[s] plot above.
V1 s1 ¬ V2 s2 ¬ 0.0 0.5 1.0 1.5 2.0 s 20 40 60 80 100 V[s] The Potential vs. Distance between Co-axial Conducting Cylinders Just to nail our understanding, we will generate the contours of V[s] (between the electrodes), the stream-line plot of the E field, and their superposition. Note: to plot the contour map, we have to convert V[s] into it’s Cartesian form (in this case, it is simply substituting s = x2 + y2 into V[s] (from above, V[s] = V1 Log[s]-V2 Log[s]+V2 Log[s1]-V1 Log[s2] Log[s1]-Log[s2] ) I use M’s TransformedField function to do the work; this time it is transforming a scalar function, V[s].
( Execute code below ) Clear[s1, s2, V1, V2] ( Leave the Clear statement ) VV[x_, y_] = TransformedField["Cylindrical" →"Cartesian", V[s], {s, θ, ζ} →{x, y, z}] s1 = 1; s2 = 2; V1 = 10; V2 = 100; contoury = ContourPlot If x2 + y2 ≤s1 || x2 + y2 ≥s2, Null, VV[x, y], {x, -3, 3}, {y, -3, 3}; Show[contoury, innerelectrode, outerelectrode] As expected the contours of V[s] are circles (s = constants); in 3D they would be concentric cylinders. If you want to see the magnitudes of V corresponding to each contour, click your mouse inside the plot and point to the contour lines.
Now we plot the streamlines: MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb 9 As expected the contours of V[s] are circles (s = constants); in 3D they would be concentric cylinders. If you want to see the magnitudes of V corresponding to each contour, click your mouse inside the plot and point to the contour lines.
Now we plot the streamlines: ( Execute code below ) streamy = StreamPlotIf x2 + y2 ≤s1 || x2 + y2 ≥s2, {0, 0}, EECartesian2D[x, y], {x, -3, 3}, {y, -3, 3}, StreamPoints →100; Show[streamy, innerelectrode, outerelectrode] And finely superimpose the streamlines onto the contourplot.
( Execute code below ) Show[ contoury, innerelectrode, outerelectrode, streamy] One more time — because of the symmetry, this is a ONE D Laplace’s Equation problem. (Remember, this is a SLICE through the CYLINDERS, e.g., at z = 0).
Laplace’s Equation in One Dimension—Spherical Symmetry In systems with spherical symmetry, the potential is a function of the radial coordinate, r, and independent of θ and ϕ. We will seek the potential between two concentric spheres which serve as boundaries, where the boundaries are equipotentials. The boundary conditions then take the form V(r1) = V1 and V(r2) = V2. Laplace’s equation for spherical coordinates, ignoring the terms in θ and ϕ, is: 1 r2 ∂ ∂r r2 ∂V ∂r = 2 r ∂V ∂r + ∂2V ∂r2 = 0 It is conventional to multiply each term (including the terms in θ and ϕ, which are not shown) by r2. This removes the r’s in the denominator of each term (including those not shown). 10 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb It is conventional to multiply each term (including the terms in θ and ϕ, which are not shown) by r2. This removes the r’s in the denominator of each term (including those not shown). (s) Use the M DSolve function with the BCs: V[r1] = V1 and V[r2] = V2 to find V[r] between the spheri-cal electrodes. Is your solution consistent with what your found earlier in the semester, using Gauss’s Law? Comment.
( Input code below ) ClearAll["Global"] ( Leave the ClearAll statement ) (t) Check to make sure V[r] does indeed satisfy the boundary conditions, V[r1] = V1 and V[r2] = V2. ( Input code below ) (u) Plot your results for the potential as a function of r for the the concentric spheres. For plotting, I assumed: r1 = 1; r2 = 2; V1 = 10; V2 = 100; ( Input code below ) Note that for the given constants r1, r2, V1, V2, the slope of the potential function V[r] is monotonically decreasing; as expected, no min or max in V[r] occurs except at the endpoints (the boundaries). (v) Clear the constants (r1, r2, V1, V2) and find the ONE DIMENSIONAL E field from V[r].
Use M’s Grad function in Spherical Coordinates.
Here is some help: M writes it as: Grad[f[r,θ,z],{r,θ,z},”Spherical”], where f is the scalar function being operated on.
Evaluate the following: ( Execute code below ) Clear[r1, r2, V1, V2] Grad[f[r, θ, ϕ], {r, θ, ϕ}, "Spherical"] Here f[r, θ, ϕ] is a general, undefined, scalar function in spherical coordinates; M assumes that EACH component of the gradient can have a dependence on all three coordinates. The result is a 3D Vector which is easily translated into: ∂f[ θ ϕ] Csc[θ] ∂f[r θ ϕ] MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb 11 Here f[r, θ, ϕ] is a general, undefined, scalar function in spherical coordinates; M assumes that EACH component of the gradient can have a dependence on all three coordinates. The result is a 3D Vector which is easily translated into: ∂ ∂s f[r, θ, ϕ], ∂ ∂θ f[r,θ,ϕ] r , Csc[θ] ∂ ∂ϕ f[r,θ,ϕ] r , which should look familiar. Note M’s notation: f(0,0,1)[r, θ, ϕ] = ∂ ∂ϕ f[r, θ, ϕ] ] SO: suggest that you simply enter: Espherical[r_] = –Grad[V[r],{s,θ,ϕ},”Spherical”] and execute. Don’t overlook the – sign. The lack of ϕ and z dependence in V does its magic (i.e., the ϕ and z components come out zero.) ( Input code below ) Broken Record: This operation yields a 3D vector. Since V[r] is a function of r only, only the r compo-nent of the Gradient is non zero ∂ ∂θ V[r] and ∂ ∂ϕ V[r] both = 0.
Given the symmetry of the problem we are not surprised to see that Espherical is: A function of r only AND The only non-zero component is the r ! component.
(w) Plot the 2D EE field using Vector Field (there is no z dependence; consider letting z = 0). REMEM-BER: M requires that we transform EEspherical into EEcartesian for plotting.
( Execute code below ) EECartesian[x_, y_, z_] = TransformedField["Spherical" →"Cartesian", Espherical[r], {r, θ, ϕ} →{x, y, z}] EECartesian2D[x_, y_] = {EECartesian[x, y, 0], EECartesian[x, y, 0]} ( selects out the x,y components ) (x) Now put in some values for the constants and make a VectorPlot of the E-Field.
( Input code below ) Remember this is a 2D VectorPlot. It represents a cut through (or cross section of) the spheres. It’s easiest to think of a plane passing through the polar (z) axis which of course passes through the origin.
The E vectors are all radial and only are defined between the electrodes. For our assumed constants, E points from the outer more positive sphere, inward. E increases in intensity (the vectors get longer) as one moves from r2 into r1. This is consistent with the SLOPE of V[r] (largest at r= r1). (Again, don’t forget the –sign in E = – Grad[V] (so the E vectors point towards smaller, decreasing r.) 12 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb Remember this is a 2D VectorPlot. It represents a cut through (or cross section of) the spheres. It’s easiest to think of a plane passing through the polar (z) axis which of course passes through the origin.
The E vectors are all radial and only are defined between the electrodes. For our assumed constants, E points from the outer more positive sphere, inward. E increases in intensity (the vectors get longer) as one moves from r2 into r1. This is consistent with the SLOPE of V[r] (largest at r= r1). (Again, don’t forget the –sign in E = – Grad[V] (so the E vectors point towards smaller, decreasing r.) V1 r1 ¬ V2 r2 ¬ 0.0 0.5 1.0 1.5 2.0 r 20 40 60 80 100 V[r] The Potential vs. Distance between Concentric Conducting Spheres Just to nail our understanding, we will generate the contours of V[r] (between the electrodes), the stream-line plot of the E field, and their superposition. Note: to plot the contour map, we have to convert V[r] into it’s Cartesian form.
I use M’s TransformedField function to do the work; again, it is transforming a scalar function, V[r].
( Execute code below ) Clear[r1, r2, V1, V2] ( Leave Clear statement ) VV[x_, y_] = TransformedField["Spherical" →"Cartesian", V[r], {r, θ, ϕ} →{x, y, z}] /. z →0 r1 = 1; r2 = 2; V1 = 10; V2 = 100; contoury = ContourPlot If x2 + y2 ≤r1 || x2 + y2 ≥r2, Null, VV[x, y], {x, -3, 3}, {y, -3, 3}; Show[contoury, innerelectrode, outerelectrode] As expected the contours of V[r] are circles (r= constants); in 3D they would be concentric spheres.
Now we plot the streamlines: ( Execute code below ) streamy = StreamPlotIf x2 + y2 ≤r1 || x2 + y2 ≥r2, {0, 0}, EECartesian2D[x, y], {x, -3, 3}, {y, -3, 3}, StreamPoints →100; Show[streamy, innerelectrode, outerelectrode] MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb 13 And finely superimpose the streamlines onto the contour plot.
( Execute code below ) Show[ contoury, innerelectrode, outerelectrode, streamy] One more time — because of the symmetry, this is a ONE D Laplace’s Equation problem (r dependent only). Remember, the plots above are slices through the SPHERES.
Clearly, and not surprising, the basic behavior of the 2D plots for the cylinders and the spheres look somewhat similar — BUT, importantly, they are represented by different functions.
14 MODULE-STUDENT-VERSION-OneD_LaplacesEquation-READY-FOR-WEB-PAGE-UPLOAD.nb |
12581 | https://www.geeksforgeeks.org/dsa/minimum-number-deletions-make-sorted-sequence/ | Published Time: 2017-05-18 09:43:56
Minimum number of deletions to make a sorted sequence - GeeksforGeeks
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Next Article: Minimum number of deletions so that no two consecutive are same
Minimum number of deletions to make a sorted sequence
Last Updated : 07 Nov, 2023
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Given an array of n integers. The task is to remove or delete the minimum number of elements from the array so that when the remaining elements are placed in the same sequence order to form an increasing sorted sequence.
Examples :
Input : {5, 6, 1, 7, 4}
Output : 2
Removing 1 and 4
leaves the remaining sequence order as
5 6 7 which is a sorted sequence.
Input : {30, 40, 2, 5, 1, 7, 45, 50, 8}
Output : 4
A simple solution is to remove all subsequences one by one and check if remaining set of elements is in sorted order or not. The time complexity of this solution is exponential.
An efficient approach uses the concept of finding the length of the longest increasing subsequence of a given sequence.
Algorithm:
-->arr be the given array.
-->n number of elements in arr.
-->len be the length of longest
increasing subsequence in arr.
-->// minimum number of deletions
min = n - len
Try it on GfG Practice C++
```cpp
// C++ implementation to find
// minimum number of deletions
// to make a sorted sequence
include
using namespace std;
/ lis() returns the length
of the longest increasing
subsequence in arr[] of size n /
int lis( int arr[], int n )
{
int result = 0;
int lis[n];
/ Initialize LIS values
for all indexes /
for (int i = 0; i < n; i++ )
lis[i] = 1;
/ Compute optimized LIS
values in bottom up manner /
for (int i = 1; i < n; i++ )
for (int j = 0; j < i; j++ )
if ( arr[i] > arr[j] &&
lis[i] < lis[j] + 1)
lis[i] = lis[j] + 1;
/ Pick resultimum
of all LIS values /
for (int i = 0; i < n; i++ )
if (result < lis[i])
result = lis[i];
return result;
}
// function to calculate minimum
// number of deletions
int minimumNumberOfDeletions(int arr[],
int n)
{
// Find longest increasing
// subsequence
int len = lis(arr, n);
// After removing elements
// other than the lis, we
// get sorted sequence.
return (n - len);
}
// Driver Code
int main()
{
int arr[] = {30, 40, 2, 5, 1,
7, 45, 50, 8};
int n = sizeof(arr) / sizeof(arr);
cout << "Minimum number of deletions = "
<< minimumNumberOfDeletions(arr, n);
return 0;
}
```
// C++ implementation to find
// minimum number of deletions // to make a sorted sequence#include using namespace std;/ lis() returns the length of the longest increasing subsequence in arr[] of size n /int lis( int arr[], int n ){ int result = 0; int lis[n]; / Initialize LIS values for all indexes / for (int i = 0; i < n; i++ ) lis[i] = 1; / Compute optimized LIS values in bottom up manner / for (int i = 1; i < n; i++ ) for (int j = 0; j < i; j++ ) if ( arr[i] > arr[j] && lis[i] < lis[j] + 1) lis[i] = lis[j] + 1; / Pick resultimum of all LIS values / for (int i = 0; i < n; i++ ) if (result < lis[i]) result = lis[i]; return result;}// function to calculate minimum// number of deletions int minimumNumberOfDeletions(int arr[], int n){ // Find longest increasing // subsequence int len = lis(arr, n); // After removing elements // other than the lis, we // get sorted sequence. return (n - len);}// Driver Code int main(){ int arr[] = {30, 40, 2, 5, 1, 7, 45, 50, 8}; int n = sizeof(arr) / sizeof(arr); cout << "Minimum number of deletions = " << minimumNumberOfDeletions(arr, n); return 0;}
Java
```java
// Java implementation to find
// minimum number of deletions
// to make a sorted sequence
class GFG
{
/ lis() returns the length
of the longest increasing
subsequence in arr[] of size n /
static int lis( int arr[], int n )
{
int result = 0;
int[] lis = new int[n];
/ Initialize LIS values
for all indexes /
for (int i = 0; i < n; i++ )
lis[i] = 1;
/ Compute optimized LIS
values in bottom up manner /
for (int i = 1; i < n; i++ )
for (int j = 0; j < i; j++ )
if ( arr[i] > arr[j] &&
lis[i] < lis[j] + 1)
lis[i] = lis[j] + 1;
/ Pick resultimum of
all LIS values /
for (int i = 0; i < n; i++ )
if (result < lis[i])
result = lis[i];
return result;
}
// function to calculate minimum
// number of deletions
static int minimumNumberOfDeletions(int arr[],
int n)
{
// Find longest
// increasing subsequence
int len = lis(arr, n);
// After removing elements
// other than the lis, we get
// sorted sequence.
return (n - len);
}
// Driver Code
public static void main (String[] args)
{
int arr[] = {30, 40, 2, 5, 1,
7, 45, 50, 8};
int n = arr.length;
System.out.println("Minimum number of" +
" deletions = " +
minimumNumberOfDeletions(arr, n));
}
}
/ This code is contributed by Harsh Agarwal /
Python3python3
Python3 implementation to find
minimum number of deletions to
make a sorted sequence
lis() returns the length
of the longest increasing
subsequence in arr[] of size n
def lis(arr, n):
result = 0
lis = [0 for i in range(n)]
# Initialize LIS values
# for all indexes
for i in range(n):
lis[i] = 1
# Compute optimized LIS values
# in bottom up manner
for i in range(1, n):
for j in range(i):
if ( arr[i] > arr[j] and
lis[i] < lis[j] + 1):
lis[i] = lis[j] + 1
# Pick resultimum
# of all LIS values
for i in range(n):
if (result < lis[i]):
result = lis[i]
return result
Function to calculate minimum
number of deletions
def minimumNumberOfDeletions(arr, n):
# Find longest increasing
# subsequence
len = lis(arr, n)
# After removing elements
# other than the lis, we
# get sorted sequence.
return (n - len)
Driver Code
arr = [30, 40, 2, 5, 1,
7, 45, 50, 8]
n = len(arr)
print("Minimum number of deletions = ",
minimumNumberOfDeletions(arr, n))
This code is contributed by Anant Agarwal.
C#csharp
// C# implementation to find
// minimum number of deletions
// to make a sorted sequence
using System;
class GfG
{
/ lis() returns the length of
the longest increasing subsequence
in arr[] of size n /
static int lis( int []arr, int n )
{
int result = 0;
int[] lis = new int[n];
/ Initialize LIS values for
all indexes /
for (int i = 0; i < n; i++ )
lis[i] = 1;
/ Compute optimized LIS values
in bottom up manner /
for (int i = 1; i < n; i++ )
for (int j = 0; j < i; j++ )
if ( arr[i] > arr[j] &&
lis[i] < lis[j] + 1)
lis[i] = lis[j] + 1;
/ Pick resultimum of all LIS
values /
for (int i = 0; i < n; i++ )
if (result < lis[i])
result = lis[i];
return result;
}
// function to calculate minimum
// number of deletions
static int minimumNumberOfDeletions(
int []arr, int n)
{
// Find longest increasing
// subsequence
int len = lis(arr, n);
// After removing elements other
// than the lis, we get sorted
// sequence.
return (n - len);
}
// Driver Code
public static void Main (String[] args)
{
int []arr = {30, 40, 2, 5, 1,
7, 45, 50, 8};
int n = arr.Length;
Console.Write("Minimum number of" +
" deletions = " +
minimumNumberOfDeletions(arr, n));
}
}
// This code is contributed by parashar.
JavaScriptjavascript
// javascript implementation to find
// minimum number of deletions
// to make a sorted sequence
/ lis() returns the length
of the longest increasing
subsequence in arr[] of size n /
function lis(arr,n)
{
let result = 0;
let lis= new Array(n);
/ Initialize LIS values
for all indexes /
for (let i = 0; i < n; i++ )
lis[i] = 1;
/ Compute optimized LIS
values in bottom up manner /
for (let i = 1; i < n; i++ )
for (let j = 0; j < i; j++ )
if ( arr[i] > arr[j] &&
lis[i] < lis[j] + 1)
lis[i] = lis[j] + 1;
/ Pick resultimum
of all LIS values /
for (let i = 0; i < n; i++ )
if (result < lis[i])
result = lis[i];
return result;
}
// function to calculate minimum
// number of deletions
function minimumNumberOfDeletions(arr,n)
{
// Find longest increasing
// subsequence
let len = lis(arr,n);
// After removing elements
// other than the lis, we
// get sorted sequence.
return (n - len);
}
let arr = [30, 40, 2, 5, 1,7, 45, 50, 8];
let n = arr.length;
document.write("Minimum number of deletions = "
+ minimumNumberOfDeletions(arr,n));
// This code is contributed by vaibhavrabadiya117.
PHPphp
php
// PHP implementation to find
// minimum number of deletions
// to make a sorted sequence
/ lis() returns the length of
the longest increasing subsequence
in arr[] of size n /
function lis( $arr, $n )
{
$result = 0;
$lis[$n] = 0;
/ Initialize LIS values
for all indexes /
for ($i = 0; $i < $n; $i++ )
$lis[$i] = 1;
/ Compute optimized LIS
values in bottom up manner /
for ($i = 1; $i < $n; $i++ )
for ($j = 0; $j < $i; $j++ )
if ( $arr[$i] $arr[$j] &&
$lis[$i] < $lis[$j] + 1)
$lis[$i] = $lis[$j] + 1;
/ Pick resultimum of
all LIS values /
for ($i = 0; $i < $n; $i++ )
if ($result < $lis[$i])
$result = $lis[$i];
return $result;
}
// function to calculate minimum
// number of deletions
function minimumNumberOfDeletions($arr, $n)
{
// Find longest increasing
// subsequence
$len = lis($arr, $n);
// After removing elements
// other than the lis, we
// get sorted sequence.
return ($n - $len);
}
// Driver Code
$arr = array(30, 40, 2, 5, 1,
7, 45, 50, 8);
$n = sizeof($arr) / sizeof($arr);
echo "Minimum number of deletions = " ,
minimumNumberOfDeletions($arr, $n);
// This code is contributed by nitin mittal.
?>
```
OutputMinimum number of deletions = 4
Time Complexity : O(n 2)
Auxiliary Space:O(n)
Time Complexity can be decreased to O(nlogn) by finding the Longest Increasing Subsequence Size(N Log N)
This article is contributed by Ayush Jauhari.
Approach#2: Using longest increasing subsequence
One approach to solve this problem is to find the length of the longest increasing subsequence (LIS) of the given array and subtract it from the length of the array. The difference gives us the minimum number of deletions required to make the array sorted.
Algorithm
Calculate the length of the longest increasing subsequence (LIS) of the array.
Subtract the length of the LIS from the length of the array.
Return the difference obtained in step 2 as the output.
C++
```cpp
include
include
include // Required for max_element
using namespace std;
// Function to find the minimum number of deletions
int minDeletions(vector arr) {
int n = arr.size();
vector lis(n, 1); // Initialize LIS array with 1
// Calculate LIS values
for (int i = 1; i < n; ++i) {
for (int j = 0; j < i; ++j) {
if (arr[i] > arr[j]) {
lis[i] = max(lis[i], lis[j] + 1); // Update LIS value
}
}
}
// Find the maximum length of LIS
int maxLength = max_element(lis.begin(), lis.end());
// Return the minimum number of deletions
return n - maxLength;
}
//Driver code
int main() {
vector arr = {5, 6, 1, 7, 4};
// Call the minDeletions function and print the result
cout << minDeletions(arr) << endl;
return 0;
}
```
include
include #include // Required for max_element using namespace std;// Function to find the minimum number of deletions int minDeletions(vector arr) { int n = arr.size(); vector lis(n, 1); // Initialize LIS array with 1 // Calculate LIS values for (int i = 1; i < n; ++i) { for (int j = 0; j < i; ++j) { if (arr[i] > arr[j]) { lis[i] = max(lis[i], lis[j] + 1); // Update LIS value } } } // Find the maximum length of LIS int maxLength = max_element(lis.begin(), lis.end()); // Return the minimum number of deletions return n - maxLength;}//Driver code int main() { vector arr = {5, 6, 1, 7, 4}; // Call the minDeletions function and print the result cout << minDeletions(arr) << endl; return 0;}
Java
```java
import java.util.Arrays;
public class Main {
public static int minDeletions(int[] arr) {
int n = arr.length;
int[] lis = new int[n];
Arrays.fill(lis, 1); // Initialize the LIS array with all 1's
for (int i = 1; i < n; i++) {
for (int j = 0; j < i; j++) {
if (arr[i] > arr[j]) {
lis[i] = Math.max(lis[i], lis[j] + 1);
}
}
}
return n - Arrays.stream(lis).max().getAsInt(); // Return the number of elements to delete
}
public static void main(String[] args) {
int[] arr = {5, 6, 1, 7, 4};
System.out.println(minDeletions(arr)); // Output: 2
}
}
Python3python3
def min_deletions(arr):
n = len(arr)
lis = n
for i in range(1, n):
for j in range(i):
if arr[i] > arr[j]:
lis[i] = max(lis[i], lis[j] + 1)
return n - max(lis)
arr = [5, 6, 1, 7, 4]
print(min_deletions(arr))
C#csharp
using System;
using System.Collections.Generic;
using System.Linq;
namespace MinDeletionsExample
{
class Program
{
static int MinDeletions(List arr)
{
int n = arr.Count;
List lis = Enumerable.Repeat(1, n).ToList(); // Initialize LIS array with 1
// Calculate LIS values
for (int i = 1; i < n; ++i)
{
for (int j = 0; j < i; ++j)
{
if (arr[i] > arr[j])
{
lis[i] = Math.Max(lis[i], lis[j] + 1); // Update LIS value
}
}
}
// Find the maximum length of LIS
int maxLength = lis.Max();
// Return the minimum number of deletions
return n - maxLength;
}
// Driver Code
static void Main(string[] args)
{
List<int> arr = new List<int> { 5, 6, 1, 7, 4 };
// Call the MinDeletions function and print the result
Console.WriteLine(MinDeletions(arr));
// Keep console window open until a key is pressed
Console.ReadKey();
}
}
}
JavaScriptjavascript
function minDeletions(arr) {
let n = arr.length;
let lis = new Array(n).fill(1);
for (let i = 1; i < n; i++) {
for (let j = 0; j < i; j++) {
if (arr[i] > arr[j]) {
lis[i] = Math.max(lis[i], lis[j] + 1);
}
}
}
return n - Math.max(...lis);
}
let arr = [5, 6, 1, 7, 4];
console.log(minDeletions(arr));
```
Output2
Time complexity: O(n^2), where n is length of array
Space complexity: O(n), where n is length of array
Approach#3: Using binary search
This approach uses binary search to find the correct position to insert a given element into the subsequence.
Algorithm
Initialize a list 'sub' with the first element of the input list.
For each subsequent element in the input list, if it is greater than the last element in 'sub', append it to 'sub'.
Otherwise, use binary search to find the correct position to insert the element into 'sub'.
The minimum number of deletions required is equal to the length of the input list minus the length of 'sub'.
C++
```cpp
include
include
using namespace std;
// Function to find the minimum number of deletions to make a strictly increasing subsequence
int minDeletions(vector& arr) {
int n = arr.size();
vector sub; // Stores the longest increasing subsequence
sub.push_back(arr); // Initialize the subsequence with the first element of the array
for (int i = 1; i < n; i++) {
if (arr[i] > sub.back()) {
// If the current element is greater than the last element of the subsequence,
// it can be added to the subsequence to make it longer.
sub.push_back(arr[i]);
} else {
int index = -1; // Initialize index to -1
int val = arr[i]; // Current element value
int l = 0, r = sub.size() - 1; // Initialize left and right pointers for binary search
// Binary search to find the index where the current element can be placed in the subsequence
while (l <= r) {
int mid = (l + r) / 2; // Calculate the middle index
if (sub[mid] >= val) {
index = mid; // Update the index if the middle element is greater or equal to the current element
r = mid - 1; // Move the right pointer to mid - 1
} else {
l = mid + 1; // Move the left pointer to mid + 1
}
}
if (index != -1) {
sub[index] = val; // Replace the element at the found index with the current element
}
}
}
// The minimum number of deletions is equal to the difference between the input array size and the size of the longest increasing subsequence
return n - sub.size();
}
int main() {
vector arr = {30, 40, 2, 5, 1, 7, 45, 50, 8};
int output = minDeletions(arr);
cout << output << endl;
return 0;
}
```
include
include using namespace std;// Function to find the minimum number of deletions to make a strictly increasing subsequence int minDeletions(vector& arr) { int n = arr.size(); vector sub; // Stores the longest increasing subsequence sub.push_back(arr); // Initialize the subsequence with the first element of the array for (int i = 1; i < n; i++) { if (arr[i] > sub.back()) { // If the current element is greater than the last element of the subsequence, // it can be added to the subsequence to make it longer. sub.push_back(arr[i]); } else { int index = -1; // Initialize index to -1 int val = arr[i]; // Current element value int l = 0, r = sub.size() - 1; // Initialize left and right pointers for binary search // Binary search to find the index where the current element can be placed in the subsequence while (l <= r) { int mid = (l + r) / 2; // Calculate the middle index if (sub[mid] >= val) { index = mid; // Update the index if the middle element is greater or equal to the current element r = mid - 1; // Move the right pointer to mid - 1 } else { l = mid + 1; // Move the left pointer to mid + 1 } } if (index != -1) { sub[index] = val; // Replace the element at the found index with the current element } } } // The minimum number of deletions is equal to the difference between the input array size and the size of the longest increasing subsequence return n - sub.size();}int main() { vector arr = {30, 40, 2, 5, 1, 7, 45, 50, 8}; int output = minDeletions(arr); cout << output << endl; return 0;}
Java
```java
import java.util.ArrayList;
public class Main {
// Function to find the minimum number of deletions to make a strictly increasing subsequence
static int minDeletions(ArrayList<Integer> arr) {
int n = arr.size();
ArrayList<Integer> sub = new ArrayList<>(); // Stores the longest increasing subsequence
sub.add(arr.get(0)); // Initialize the subsequence with the first element of the array
for (int i = 1; i < n; i++) {
if (arr.get(i) > sub.get(sub.size() - 1)) {
// If the current element is greater than the last element of the subsequence,
// it can be added to the subsequence to make it longer.
sub.add(arr.get(i));
} else {
int index = -1; // Initialize index to -1
int val = arr.get(i); // Current element value
int l = 0, r = sub.size() - 1; // Initialize left and right pointers for binary search
// Binary search to find the index where the current element can be placed in the subsequence
while (l <= r) {
int mid = (l + r) / 2; // Calculate the middle index
if (sub.get(mid) >= val) {
index = mid; // Update the index if the middle element is greater or equal to the current element
r = mid - 1; // Move the right pointer to mid - 1
} else {
l = mid + 1; // Move the left pointer to mid + 1
}
}
if (index != -1) {
sub.set(index, val); // Replace the element at the found index with the current element
}
}
}
// The minimum number of deletions is equal to the difference between the input array size and the size of the longest increasing subsequence
return n - sub.size();
}
public static void main(String[] args) {
ArrayList<Integer> arr = new ArrayList<>();
arr.add(30);
arr.add(40);
arr.add(2);
arr.add(5);
arr.add(1);
arr.add(7);
arr.add(45);
arr.add(50);
arr.add(8);
int output = minDeletions(arr);
System.out.println(output);
}
}
Python3python3
def min_deletions(arr):
def ceil_index(sub, val):
l, r = 0, len(sub)-1
while l <= r:
mid = (l + r) // 2
if sub[mid] >= val:
r = mid - 1
else:
l = mid + 1
return l
sub = [arr]
for i in range(1, len(arr)):
if arr[i] > sub[-1]:
sub.append(arr[i])
else:
sub[ceil_index(sub, arr[i])] = arr[i]
return len(arr) - len(sub)
arr = [30, 40, 2, 5, 1, 7, 45, 50, 8]
output = min_deletions(arr)
print(output)
C#csharp
using System;
using System.Collections.Generic;
class Program
{
// Function to find the minimum number of deletions to make a strictly increasing subsequence
static int MinDeletions(List arr)
{
int n = arr.Count;
List sub = new List(); // Stores the longest increasing subsequence
sub.Add(arr); // Initialize the subsequence with the first element of the array
for (int i = 1; i < n; i++)
{
if (arr[i] > sub[sub.Count - 1])
{
// If the current element is greater than the last element of the subsequence,
// it can be added to the subsequence to make it longer.
sub.Add(arr[i]);
}
else
{
int index = -1; // Initialize index to -1
int val = arr[i]; // Current element value
int l = 0, r = sub.Count - 1; // Initialize left and right
// pointers for binary search
// Binary search to find the index where the current element
// can be placed in the subsequence
while (l <= r)
{
int mid = (l + r) / 2; // Calculate the middle index
if (sub[mid] >= val)
{
index = mid; // Update the index if the middle element is
// greater or equal to the current element
r = mid - 1; // Move the right pointer to mid - 1
}
else
{
l = mid + 1; // Move the left pointer to mid + 1
}
}
if (index != -1)
{
sub[index] = val; // Replace the element at the found index
// with the current element
}
}
}
// The minimum number of deletions is equal to the difference
// between the input list size and the size of the
// longest increasing subsequence
return n - sub.Count;
}
// Driver code
static void Main()
{
List arr = new List { 30, 40, 2, 5, 1, 7, 45, 50, 8 };
int output = MinDeletions(arr);
Console.WriteLine(output);
Console.ReadLine();
}
}
JavaScriptjavascript
// Function to find the minimum number of deletions to make a strictly increasing subsequence
function minDeletions(arr) {
let n = arr.length;
let sub = []; // Stores the longest increasing subsequence
sub.push(arr); // Initialize the subsequence with the first element of the array
for (let i = 1; i < n; i++) {
if (arr[i] > sub[sub.length - 1]) {
// If the current element is greater than the last element of the subsequence,
// it can be added to the subsequence to make it longer.
sub.push(arr[i]);
} else {
let index = -1; // Initialize index to -1
let val = arr[i]; // Current element value
let l = 0, r = sub.length - 1; // Initialize left and right pointers for binary search
// Binary search to find the index where the current element can be placed
// in the subsequence
while (l <= r) {
let mid = Math.floor((l + r) / 2); // Calculate the middle index
if (sub[mid] >= val) {
index = mid; // Update the index if the middle element is greater
//or equal to the current element
r = mid - 1; // Move the right pointer to mid - 1
} else {
l = mid + 1; // Move the left pointer to mid + 1
}
}
if (index !== -1) {
sub[index] = val; // Replace the element at the found index with the current element
}
}
}
// The minimum number of deletions is equal to the difference
//between the input array size and the size of the longest increasing subsequence
return n - sub.length;
}
let arr = [30, 40, 2, 5, 1, 7, 45, 50, 8];
let output = minDeletions(arr);
console.log(output);
```
Output4
Time Complexity: O(n log n)
Auxiliary Space: O(n)
Comment
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Minimum number of deletions so that no two consecutive are same
A
Ayush
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Article Tags :
Dynamic Programming
DSA
LIS
Practice Tags :
Dynamic Programming
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Optics
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Optics Formulas
Light Right-Hand Rule
Light is a transverse electromagnetic wave. The electric E and magnetic M fields are perpendicular to each other and to the propagation vector k, as shown below.
Power density is given by Poyntings vector, P, the vector product of E and H. You can easily remember the directions if you curl E into H with the fingers of the right hand: your thumb points in the direction of propagation.
Figure 1. Illustration of the right-hand rule of electromagnetic waves.
Intensity Nomogram
The nomogram below relates E, H, and the light intensity I in vacuum. You may also use it for other area units, for example, [V/mm], [A/mm] and [W/mm2]. If you change the electrical units, remember to change the units of I by the product of the units of E and H: for example [V/m], [mA/m], [mW/m2] or [kV/m], [kA/m], [MW/m2].
Figure 2. Illustration of intensity nomogram.
Light Intensity
The light intensity, I is measured in Watts/m2, E in Volts/m, and H in Amperes/m. The equations relating I to E and H are quite analogous to OHMS LAW. For peak values these equations are:
Figure 3. Light intensity formulas.
The quantity η0 is the wave impedance of vacuum, and η is the wave impedance of a medium with refractive index n.
Wave Quantity Relationship
Figure 4. Wave quantity relationship formulas.
k: wave vector [radians/m]
ν: frequency [Hertz]
ω: angular frequency [radians/sec]
λ: wavelength [m]
λ0: wavelength in vacuum [m]
n: refractive index
Light Energy Conversions
Figure 5. Light energy conversion formulas.
Wavelength Conversions
1 nm = 10 Angstroms (Å) = 10-9m = 10-7cm = 10-3µm
Plane-Polarized Light
For plane-polarized light the E and H fields remain in perpendicular planes parallel to the propagation vector k, as shown below.
Figure 6. Illustration of plane polarized light.
Both E and H oscillate in time and space as: sin (ωt-kx)
Wavelength Nomogram
The wavelength nomogram relates wavenumber, photon energy and wavelength.
Figure 7. Illustration of wavelength nomogram.
Snells Law
Snells Law describes how a light ray behaves when it passes from a medium with index of refraction n1, to a medium with a different index of refraction, n2. In general, the light will enter the interface between the two media at an angle. This angle is called the angle of incidence. It is the angle measured between the normal to the surface (interface) and the incoming light beam (see figure). In the case that n1 is smaller than n2, the light is bent towards the normal. If n1 is greater than n2, the light is bent away from the normal (see figure below). Snells Law is expressed as n1sinθ1 = n2sinθ2.
Figure 8. Illustration of Snells Law.
Beam Displacement
A flat piece of glass can be used to displace a light ray laterally without changing its direction. The displacement varies with the angle of incidence; it is zero at normal incidence and equals the thickness h of the flat at grazing incidence.
Grazing incidence is light incident at almost or close to 90° to the normal of the surface.
Figure 9. Illustration of beam displacement.
The relationship between the tilt angle of the flat and the two different refractive indices is shown in the graph below.
Figure 10. Displacement/Thickness vs Tilt Angle.
Beam Deviation
Both displacement and deviation occur if the media on the two sides of the tilted flat are different for example, a tilted window in a fish tank. The displacement is the same, but the angular deviation δ is given by the formula below. Note:δ is independent of the index of the flat; it is the same as if a single boundary existed between media 1 and 3. (see Figure 9)
Example: The refractive index of air at STP (Standard Temperature and Pressure) is about 1.0003. The deviation of a light ray passing through a glass Brewsters angle window on a HeNe laser is then:
δ= (n3 - n1) tan θ
At Brewsters angle, tan θ= n2
δ= (0.0003) x 1.5 = 0.45 mrad
At 10,000 ft. altitude, air pressure is 2/3 that at sea level; the deviation is 0.30 mrad. This change may misalign the laser if its two windows are symmetrical rather than parallel.
Angular Deviation of a Prism
Figure 11. Illustration of angular devition in a prism.
Angular deviation of a prism depends on the prism angle α, the refractive index, n, and the angle of incidence θi. Minimum deviation occurs when the ray within the prism is normal to the bisector of the prism angle. For small prism angles (optical wedges), the deviation is constant over a fairly wide range of angles around normal incidence. For such wedges the deviation is:
δ (n - 1)α
Figure 12. Angular devition vs. incident angle for a prism.
Prism Total Internal Reflection (TIR)
TIR depends on a clean glass-air interface. Reflective surfaces must be free of foreign materials. TIR may also be defeated by decreasing the incidence angle beyond a critical value. For a right angle prism of index n, rays should enter the prism face at an angle θ:
θ < arcsin (((n2-1)1/2-1)/2)
In the visible range, θ = 5.8° for BK 7 (n = 1.517) and 2.6° for fused silica (n = 1.46). Finally, prisms increase the optical path. Although effects are minimal in laser applications, focus shift and chromatic effects in divergent beams should be considered.
Fresnel Equations:
i - incident medium
t - transmitted medium
use Snells law to find θt
Normal Incidence:
r = (ni-nt)/(ni + nt)
t = 2ni/(ni + nt)
Brewster's Angle:
θβ = arctan (nt/ni)
Only s-polarized light reflected.
Total Internal Reflection (TIR):
θTIR > arcsin (nt/ni)
nt < ni is required for TIR
Field Reflection and Transmission Coefficients:
The field reflection and transmission coefficients are given by:
r = Er/Ei t = Et/Ei
Non-Normal Incidence:
rs = (nicosθi -ntcosθt)/(nicosθi + ntcosθt)
rp = (ntcos θi -nicosθt)/ntcosθi + nicosθt)
ts = 2nicosθi/(nicosθi + ntcosθt)
tp = 2nicosθi/(ntcosθi + nicosθt)
Power Reflection:
The power reflection and transmission coefficients are denoted by capital letters:
R = r2 T = t2(ntcosθt)/(nicosθi)
The refractive indices account for the different light velocities in the two media; the cosine ratio corrects for the different cross sectional areas of the beams on the two sides of the boundary.
The intensities (watts/area) must also be corrected by this geometric obliquity factor:
It = T x Ii(cosθi/cosθt)
Conservation of Energy:
R + T = 1
This relation holds for p and s components individually and for total power.
Polarization
To simplify reflection and transmission calculations, the incident electric field is broken into two plane-polarized components. The wheel in the pictures below denotes plane of incidence. The normal to the surface and all propagation vectors (ki, kr, kt) lie in this plane.
Figure 13. E parallel to the plane of incidence; p-polarized.
Figure 14. E normal to the plane of incidence; s-polarized.
Power Reflection Coefficients
Power reflection coefficients Rs and Rp are plotted linearly and logarithmically for light traveling from air (ni = 1) into BK 7 glass (nt = 1.51673). Brewsters angle = 56.60°.
The corresponding reflection coefficients are shown below for light traveling from BK 7 glass into air Brewsters angle = 33.40°. Critical angle (TIR angle) = 41.25°.
Thin Lens Equations
If a lens can be characterized by a single plane then the lens is thin. Various relations hold among the quantities shown in the figure 15.
Figure 15. Diagram of a thin lens.
Gaussian:
1/s1 + 1/s2 = 1/F
Newtonian:
x1x2 = -F2
Transverse Magnification:
MT = Y2/Y1 = -S2/S1
MT < 0, image inverted
Longitudinal Magnification:
ML = ΔX2/ΔX1 = -MT2
ML <0, no front to back inversion
Sign Conventions for Images and Lenses
| | | |
---
| Quantity | +
| s1 | real | virtual |
| s2 | real | virtual |
| F | convex lens | concave lens |
Lens Types for Minimum Aberration
| | |
--- |
| | s2/s1 | | Best lens |
| <0.2 | plano-convex/concave |
| >5 | plano-convex/concave |
| >0.2 or <5 | bi-convex/concave |
Thick Lenses
A thick lens cannot be characterized by a single focal length measured from a single plane. A single focal length F may be retained if it is measured from two planes, H1, H2, at distances P1, P2 from the vertices of the lens, V1, V2. The two back focal lengths, BFL1 and BFL2, are measured from the vertices. The thin lens equations may be used, provided all quantities are measured from the principal planes.
Figure 16. Diagram of a thick lens.
Lens Nomogram:
Figure 17. Illustration of a lens nomogram.
The Lensmakers Equation
Convex surfaces facing left have positive radii. Below, R1>0, R2<0. Principal plane offsets, P, are positive to the right. As illustrated, P1>0, P2<0. The thin lens focal length is given when Tc = 0.
Figure 18. The lens maker's equation.
Numerical Aperture
Figure 19. Numeric aperture diagram.
φMAX is the full angle of the cone of light rays that can pass through the system.
Figure 20. Numeric aperture equation.
For small φ:
Figure 21. Numeric aperture equation for small φ.
Both f-number and NA refer to the system and not the exit lens.
Constants and Prefixes
| | |
--- |
| Speed of light in vacuum | c = 2.998 x 108 m/s |
| Plancks const. | h = 6.625 x 10-34 Js |
| Boltzmanns const. | k = 1.308 x 10-23 J/K |
| Stefan-Boltzmann | σ = 5.67 x 10-8 W/m2K4 |
| 1 electron volt | eV = 1.602 x 10-19 J |
| exa (E) | 1018 |
| peta (P) | 1015 |
| tera (T) | 1012 |
| giga (G) | 109 |
| mega (M) | 106 |
| kilo (k) | 103 |
| milli (m) | 10-3 |
| micro (µ) | 10-6 |
| nano (n) | 10-9 |
| pico (p) | 10-12 |
| femto (f) | 10-15 |
| atto (a) | 10-18 |
Wavelengths of Common Lasers
| Source | (nm) |
--- |
| ArF | 193 |
| KrF | 248 |
| Nd:YAG(4) | 266 |
| XeCl | 308 |
| HeCd | 325, 441.6 |
| N2 | 337.1, 427 |
| XeF | 351 |
| Nd:YAG(3) | 354.7 |
| Ar | 488, 514.5, 351.1, 363.8 |
| Cu | 510.6, 578.2 |
| Nd:YAG(2) | 532 |
| HeNe | 632.8, 543.5, 594.1, 611.9, 1153, 1523 |
| Kr | 647.1, 676.4 |
| Ruby | 694.3 |
| Nd:Glass | 1060 |
| Nd:YAG | 1064, 1319 |
| Ho:YAG | 2100 |
| Er:YAG | 2940 |
Gaussian Intensity Distribution
The Gaussian intensity distribution:
I(r) = I(0) exp(-2r2/ω02)
is shown below
Figure 22. Gaussian intensity distribution.
The right hand ordinate gives the fraction of the total power encircled at radius r:
Figure 23. Right hand ordinate of a Gaussian beam equation.
The total beam power, P() [watts], and the on-axis intensity I(0) [watts/area] are related by:
Figure 24. Total beam power, and the on-axis intensity of a Gaussian beam equation.
Diffraction
Figure 25 below compares the far-field intensity distributions of a uniformly illuminated slit, a circular hole, and Gaussian distributions with 1/e2 diameters of D and 0.66D (99% of a 0.66D Gaussian will pass through an aperture of diameter D). The point of observation is Y off axis at a distance X>>Y from the source.
Figure 25. Far-field intensity distributions.
Focusing a Collimated Gaussian Beam
Figure 26. Focusing a collimated gaussian beam diagram.
In the figure 26 above the 1/e2 radius, ω(x), and the wavefront curvature, R(x), change with x through a beam waist at x = 0. The governing equations are:
Figure 27. Focusing a collimated gaussian beam equations.
2ω0 is the waist diameter at the 1/e2 intensity points. The wavefronts are planar at the waist [R(0) = ].
At the waist, the distance from the lens will be approximately the focal length: s2 F.
D = collimated beam diameter or diameter illuminated on lens.
Depth of Focus (DOF)
DOF = (8λ/π)(f/#)2
Only if DOF < F, then
New Waist Diameter
Beam Spread
Optical Density
D = - log (T)
or
T= 10-D
SAG
where R = radius of curvature and Y = radius of the aperture of the surface. SAG is an abbreviation for "sagitta," the Latin word for arrow. Used to specify the distance on the normal from the surface of a concave lens to the center of the curvature. It refers to the height of a curve measured from the chord.
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John KeayThe Spice Route: A HistoryISBN 13:9780719568053
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The Spice Route is one of history's greatest anomalies: shrouded in mystery, it existed long before anyone knew of its extent or configuration. Spices came from lands unseen, possibly uninhabitable, and almost by definition unattainable; that was what made them so desirable. Yet more livelihoods depended on this pungent traffic, more nations participated in it, more wars were fought for it, and more discoveries resulted from it than from...
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John Keay's recent books include Sowing the Wind: The Mismanagement of the Middle East 1900-1960 and Last Post: The End of Empire in the Far East. He lives in Scotland and is married to the author Julia Keay. Together they edited the Collins Encyclopaedia of Scotland and are now revising the London Encyclopaedia. They have four children. John's earlier books include standard histories of India and the...
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'A typically droll and beautifully wrought book' -- Literary Review 'A springy, fresh feel!The Spice Route is what happens when you match a writer at the top of his form with a fashionable subject!The result is tremendous.' -- Literary Review-Nick Smith 'Its digressiveness is also a boon, allowing Keay to touch on everything' -- FT MAgazine 20050814 'Fascinating new history' -- Daily Telegraph 20050814 'Absorbing' -- Scotsman 20050814 'Keay...
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John Keay
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12584 | http://www.wordnet-online.com/cultivate.shtml | cultivate - definition, thesaurus and related words from WordNet-Online
WordNet-Online Free dictionary and thesaurus of English. Definitions, synonyms, antonyms and more... Hint:double-click any word to get it searched! Enter your search terms Submit search form Web www.wordnet-online.com cultivate --------- ### Check what's hot: new and trending productsProduct search for cultivate (opens new tab) Verbcultivate has 4 senses 1. cultivate - foster the growth of Derived forms:nouncultivation 2, nouncultivator 1 Sample sentence: They cultivate rye in the field 2. cultivate,crop, work - prepare for crops; "Work the soil"; "cultivate the land" --2 is one way tofix, prepare, set up, ready, gear up, set Derived forms:nouncultivation 2, nouncultivator 2 Sample sentence: Somebody ----s something 3. educate, school, train, cultivate, civilize, civilise - train to be discriminative in taste or judgment; "Cultivate your musical taste"; "Train your tastebuds"; "She is well schooled in poetry" --3 is one way topolish, refine, fine-tune, down Derived form:nouncultivation 3 Sample sentences: Somebody ----s something Somebody ----s somebody 4. domesticate, cultivate, naturalize, naturalise, tame - adapt (a wild plant or unclaimed land) to the environment; "domesticate oats"; "tame the soil" --4 is one way toadapt, accommodate Sample sentence: Somebody ----s something
cultishcultismcultismscultistcultistscultivablecultivarcultivatablecultivatecultivate antonymscultivatedcultivatedcultivated cabbagecultivated carrotcultivated celerycultivated crab applecultivated land Sponsored (shop thru our affiliate link to help maintain this site): Check latest bestsellers | New Arrivals in Electronics | Product search for cultivate WordNet-Online Home | Free dictionary software | Copyright notice | Contact us | WordNet dictionary | Automotive thesaurus | News Warner |
12585 | https://www.sciencedirect.com/science/article/abs/pii/0010448585902490 | Offset curves in the plane - ScienceDirect
Typesetting math: 100%
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Cited by (69)
Computer-Aided Design
Volume 17, Issue 2, March 1985, Pages 77-82
Offset curves in the plane
Author links open overlay panel Josef Hoschek
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Abstract
For applications such as the generation of ornamental patterns for the numerical control of sewing machines in the textile industry or in the shoe industry or the numerical control of milling machines in the car body industry, offset curves must be generated from curves D i given by a designer. During the generation process further problems arise, for example finding the intersection points of neighbouring branches of the offset curves or deleting undesirable portions of the offset curves with cusps or with self-intersection points. In this paper methods are developed for attacking this problems.
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References (7)
P. Bézier
Numerical control
(1972)
I.D. Faux et al.
Computational geometry for design and manufacture
(1981)
H. Wieleitner
Spezielle ebene kurven
(1908)
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Computing offsets of NURBS curves and surfaces
1999, CAD Computer Aided Design Show abstract This paper presents algorithms for computing offsets of NURBS curves and surfaces. The basic approach consists of four steps: (1) recognition of special curves and surfaces; (2) sampling the offset curve or surface based on bounds on second derivatives; (3) interpolating these points; and (4) removing all unwanted knots using the offset tolerance. The method provides a good handle on error control and results in the fewest number of control points compared to all published work. It also allows one to control the degree and the parametrization of the offset approximation.
### Axial deformations: an intuitive deformation technique
1994, Computer Aided Design Show abstract The paper is part of a research effort that focuses on the provision of more efficient and effective design methods for broadcast modelling systems. It presents an interactive deformation technique called AxDf (Axial Deformations). Based on the paradigm of the modelling tool, the axial-deformations technique allows deformations, such as bending, scaling, twisting and stretching, that can be controlled with a 3D axis to be easily specified. Moreover, AxDf can easily be combined with other existing deformation techniques.
### Offset curves and surfaces: a brief survey
1992, Computer Aided Design Show abstract The designing of offset curves and surfaces is an essential task in many industrial applications such as the generation of tool-path geometry in numerical-control machining and robot-path planning. The paper discusses problems that are encountered in the designing of offsets, gives a brief survey of existing techniques, and suggests some directions for future research.
### Analytic properties of plane offset curves
1990, Computer Aided Geometric Design Show abstract We survey the principal geometric and topological features of plane offset curves. With appropriate sign conventions, the irregular points of the offset at distance d from a regular generator curve arise where the generator has curvature κ=−1 d. Usually, this induces a cusp on the offset, but if κ is also a local extremum, we observe instead a tangent-continuous extraordinary point of infinite curvature. Such irregular points are intimately related to the evolute, or locus of centers of curvature, of the generator. Certain special regular points are then identified: those of horizontal or vertical tangent, and those where the curvature or its derivative vanish. A one-to-one correspondence (with due allowance for irregularities) is established between such characteristic points on the generator and its offsets at each distance d. In the absence of irregular points, simple relations between certain global properties of the generator and offset curves, such as their arc length, the area they bound, and their mean square curvature or “smoothness” may be derived. The self-intersections of offset curves, and the trimming of certain extraneous loops they delineate, are also addressed.
### Spatial Tessellations: Concepts and Applications of Voronoi Diagrams
2025, Spatial Tessellations Concepts and Applications of Voronoi Diagrams
### An Algorithm for Generating NC Tool Paths for Arbitrarily Shaped Pockets with Islands
1992, ACM Transactions on Graphics Tog
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Copyright © 1985 Published by Elsevier Ltd.
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12586 | https://www.physicsclassroom.com/Lesson-Plans/Conceptual-Physics/Free-Fall-and-Projectiles/Teacher-Notes | Physics Classroom - Home
Red Text and the Conceptual Physics Course Pack
In creating our Lesson Plans and Learning Outcomes for this course we have labeled some items with red text. These resources are part of a separate purchasable product, our Conceptual Physics Course Pack. The download contains source documents, answer keys, and teacher guides for 110 Think Sheets and 55 student labs.
As long as you are a teacher or homeschool parent, you may purchase this course pack ($75 US). Since this course is compatible with our Task Tracker Subscription, we are offering also a $25 (US) discount when bundling this purchase with a subscription.
Purchase Course Pack Individually ($75) OR Bundle with Task Tracker Subscription ($50)
Teacher Notes for Free Fall and Projectiles
Lesson Plans || Learning Outcomes and Activities || Teacher Notes || Labs
Unit Overview
The Mathematical Approach
Our Lesson Plans
As is our practice, we have presented a collection of daily lesson plans as a illustration of how the tools of our course can be put together to form an effective unit of student. We have also organized these tools around a set of learning outcomes. While we have taught this unit with real Conceptual Physics students, we unfortunately do not have the Think Sheets and Lab material in a readily presentable form. They will be eventually gathered together and included in our Conceptual Physics Course Package. Because the mathematical approach that we have taken is so different than anything that we have on our website, we have provided considerably more detail about our Think Sheets. The hope is that there is enough detail to allow teachers to implement the approach with their classes. This course is being prepared in July of 2024. As soon as we complete it, we will be devoted ourselves to two lengthy projects; one of those projects is the creation of the Conceptual Physics Course Package. We will have everything neatly packaged together at that time.
Labs
We have proposed four labs for this unit. Since we do not have any Teacher's Guides available, we will supply some notes here:
Lab 1: The first lab requires the use of Video Analysis software. There are several commercial packages available for a small cost. Tracker is a free version that has gained popularity among the Physics teaching community. Students will need to capture video of balls of varying mass rising and falling. The videos can be analyzed to obtain a velocity-time graph. The slope can be acquired to obtain an acceleration. Values of acceleration and mass can be collected from all lab groups. We have found it useful to collect data throughout the day for several classes and to display the data to students the following day.
Lab 2: Lab 2 involves the vertical launch of an object. We have used a Stomp Rocket similar to those found in toy stores. Anything that launches an object upward can be used. If you can't find a launcher then throw a tennis ball vertically upward. Students acquire the time for the object to rise to its peak and return to its launch height. A single trial is needed. They can determine the launch speed (initial speed) and the peak height from this time value. We allow students to use a Desmos graph.
Lab 3: Lab 3 requires a projectile launcher. If you plan on doing Lab 4 as well, then you will need to have a projectile launcher that has some relatively high precision. That is, it consistently launches the projectile at the same speed. We prefer those made available by Pasco Scientific. They can be very pricey, but they are precise and will work well for Lab 4. Students will use the same launcher on Lab 4 that they used on Lab 3. Whatever launchers are used, it is imperative to emphasize the wearing of goggles and attention to lab safety.
In Lab 3, students launch the projectile vertically. They should be able to stand on a chair or table with a couple of meter sticks or measuring tape stretched out and determine the peak height. Run several trials and determine an average height value. From the peak height above the launch position, students can use the provided Desmos graph to determine the launch speed. The graph is made for high-speed launches. Students can zoom in on the graph to view the trajectory for a low-speed launch. They will need to use a trial-and-error method to determine the launch speed; they can manipulate the launch speed and see what peak height it gives. The continue the trial-and-error process until they have found the launch speed that leads to the measured height. Values for launch speed can be entered into the field on Desmos.
Lab 4: Using the same launcher from Lab 3, students conduct Lab 4 to predict where a target must be placed in order to launch the projectile horizontally into the target. We have provided a Data sheet for Lab 4 on our Lab page. Our practice is to have one projectile for all students. Each lab group gets one shot at the target. Lab groups can set up their launcher, make their measurements, perform their "calculations" (actually, measurements with Desmos graphs), and place their target on the floor where they think the projectile will land. The target can be a sheet of paper with a set of concentric circles (smaller circle for best score) with a sheet of carbon paper placed on top of it. Or for more dramatic results, use a cylinder that stands upright on the floor. If using a cylinder, it is important that students measure dy as the distance from the launcher vertically down to the top of the cylinder. You know your students better than we do; but we would recommend targets that are large enough to allow for success and to compensate for variability in launch speed. 1-meter diameter cylinders are a bit extreme; but cylinders the size of old-fashioned film canisters is not going to lead to much success. We cut long packaging tubes with ~8-inch diameters into sections and have provided each lab group a cylinder as the target. If you have a single projectile launcher, you can provide cylinders of varying height to different lab groups.
Project - Trajectory
We have included an open-ended project in our 12-day unit plan. Those teachers who opt out of the use of the project could shorten the unit by as much as two to three days. The Student Project can be found in the Vectors and Projectiles unit of our Physics Interactives section. Students ask and answer a question of their own choosing using a spreadsheet-like, numerical modeling program titled Trajectory. The project has some structure to it, stepping students through the brainstorming of a question, the generation of a purpose of study, the design of the study, and the execution of the study. Once the study is conducted, students create a short report in which they describe what they did, present the data that they collected, and make a claim that is supported by their evidence and reasoning.
The numerical modeling program is relatively easy to use. It outputs data in the form of a data table with several columns and in the form of any one of nine possible graphs. Screen captures of the data or the graphs can be taken for insertion into their reports. Our program does the calculations, but students are responsible for the design of the study and the interpretation of the data tables and graphs. In this sense, the project fits well with the flavor of the unit in which data and graphs are used to answer questions.
We have provided the student activity as both a PDF and a Microsoft Word document. There is a scoring rubric available for those who wish to use it. The downloads can be accessed here.
The Calculator Pad
As a teacher of Conceptual Physics, it is unlikely that you are looking for more physics problems to inflict on your students. However we recognize that classrooms exist on a spectrum and there may be some situations in which teachers have opted to use our Conceptual Physics course plan but have students that lie on the spectrum in the region between Conceptual Physics and On-Level Physics.
If that is the case, you may be interested in the use of kinematic equations to solve projectile motion problems. You will find plenty of these types of problems in the Calculator Pad section of our website. One-dimensional free-fall problems can be found in our Kinematics chapter. And projectile motion problems can be found in our Vectors and Projectiles chapter.
Other Resources
There are a few resources that we did not list in our Lesson Plans and Learning Outcomes and Activities that you may find to be very helpful or more in-style with your approach. These include:
Teacher Presentation Pack
Also Available ... |
12587 | https://www.ebsco.com/research-starters/history/law-multiple-proportions | Research Starters Home
EBSCO Knowledge Advantage TM
Law of multiple proportions
The Law of Multiple Proportions, proposed by English chemist John Dalton in the early 1800s, describes how two elements can combine to form multiple compounds. When a fixed mass of one element is compared to varying masses of another element across different compounds, the resulting ratios will be simple whole numbers. This principle notably supports Dalton's atomic theory, which posits that all matter is composed of indivisible atoms that combine in specific ratios to form compounds.
For instance, examining the compounds water (H₂O) and hydrogen peroxide (H₂O₂) illustrates this law. In both cases, the mass of hydrogen is constant at 2 grams, while the mass of oxygen varies—16 grams in water and 32 grams in hydrogen peroxide. The Law of Multiple Proportions thus provides a foundational understanding of chemical combinations and reactions, reinforcing the concept that chemical compounds have consistent composition based on the properties of their constituent elements. Dalton's work laid essential groundwork for modern chemistry and the understanding of atomic structure.
Published in: 2023
By: Zukauskas, Rebecca Sparling
Go to EBSCOhost and sign in to access more content about this topic.
Law of multiple proportions
English chemist John Dalton proposed the Law of Multiple Proportions in the early 1800s. The law is applied when two elements combine to form more than one compound. In such instances, the ratios of the masses of one element in the different compounds, when combined with the fixed mass of the other element, will be simple whole numbers. The Law of Multiple Proportions provided important support for Dalton's atomic theory of matter.
Life of John Dalton
John Dalton was born into a Quaker family on September 6, 1766, in Eaglesfield, England. His father was a weaver, and the family had little money. Dalton showed an interest in academics at an early age. He attended a Quaker school for several years and began teaching there when he was only twelve years old. After spending a year working on a farm, he returned to teaching and eventually became the principal of a boarding school.
He later took a position tutoring students in math and philosophy at New College in Manchester, England. Dalton also became a member of the local philosophical society, which allowed him to use its laboratory. During this time, he investigated color blindness, a condition that affected both Dalton and his brother. He also studied meteorology and published his findings in the book Meteorological Observations and Essays in 1793.
Dalton later turned his attention to studying gases. It was during his work with gases that he began to consider the structure of the different forms of matter, which include gases, solids, and liquids. He concluded that all elements of matter were made up of tiny particles called atoms. This idea was not exactly new, as Greek philosopher Democritus of Abdera had proposed a similar theory centuries earlier. However, Dalton expanded on this theory. He believed that different elements would have different atomic weights, which would help scientists identify them. He also found that atoms could not be destroyed or created. He detailed his findings in the 1808 book A New System of Chemical Philosophy. It was in this book that Dalton also discussed the Law of Multiple Proportions. This was one of several postulates that confirmed Dalton's atomic theory. The most important points in Dalton's theory are as follows:
All matter is made of atoms that cannot be created or destroyed.
All the atoms in a given element have identical properties and are different from the atoms found in other elements.
When two or more different kinds of atoms combine, a compound is formed.
Chemical reactions rearrange atoms.
Dalton updated A New System of Chemical Philosophy in 1810 with a chart that showed the atomic weightsof certain elements, but scientists later found that some of his calculations were incorrect. The scientific community did not widely accept Dalton's theory at first, and scientists debated the validity of his atomic theory for many years. Nevertheless, Dalton's work provided the foundation for modern atomic theory, which is crucial to scientists' understanding of chemistry.
In his later life, Dalton continued to teach at various universities across the country. He also continued his studies of the weather, taking more than two hundred thousand meteorological measurements during his life. Dalton served as the president of the Manchester Literary and Philosophical Society from 1817 until his death in 1844. He never married, and he lived a quiet life in which he focused on his scientific studies and his Quaker faith. Because modesty was an important aspect of the Quaker religion, Dalton tried to avoid public acknowledgement for his work. Still, he received some awards during his life, including an honorary doctorate from Oxford University. A statue of Dalton was also erected in London in 1834 to honor his remarkable work.
In 1837, Dalton's health declined after he suffered a stroke, and he had trouble speaking. A subsequent stroke led to his death on July 26, 1844. A civic funeral was held, and forty thousand people watched the funeral procession, showing their respect for a man who made a lasting contribution to the scientific world.
Overview of the Law of Multiple Proportions
Dalton's Law of Multiple Proportions concerns elements that combine to form more than one compound. When the mass of one of the elements in the compounds is fixed, the ratios of the masses of the other element in the compounds will be simple whole numbers.
This law can be demonstrated when examining the compounds H2O (water) and H2O2 (hydrogen peroxide). In both compounds, the mass of hydrogen is fixed at 2 grams. In water, 2 grams of hydrogen combine with 16 grams of oxygen. In hydrogen peroxide, 2 grams of hydrogen combine with 32 grams of water.
To prove the Law of Multiple Proportions using these two compounds, the weight of the oxygen in the hydrogen can be divided by the weight of the oxygen in the water.
Bibliography
"Atoms and Atomic Structure." GCSE Bitesize. BBC. 2014. Web. 15 Dec. 2014.
Balchin, Jon. "John Dalton." Science: 100 Scientists Who Changed the World. New York: Enchanted Lion Books, 2003, 96–97.
Childs, Peter E. "Dalton, John." Chemistry: Foundations and Applications. Ed. J. J. Lagowski. Vol. 2. New York: Macmillan Reference USA, 2004, 1–3.
"John Dalton." Bio. A&E Television Networks. 2014. Web. 15 Dec. 2014.
"Law of Multiple Proportions." UC Davis Chemwiki. University of California, Davis. Web. 15 Dec. 2014.
"Stoichiometry." Chemistry Department at Davidson College. Davidson College. Web. 15 Dec. 2014.
Related Topics
Elements of the Periodic Table: Research Starters TopicDalton Formulates the Atomic Theory of MatterQuakersColor blindness and geneticsMeteorologyDemocritus: FragmentsRelative atomic mass |
12588 | https://pwg.gsfc.nasa.gov/stargaze/Kep3laws.htm | Kepler's Three Laws of Planetary Motion
International Solar Terrestrial Physics (ISTP) Historical Pages
Disclaimer: The following material is being kept online for archival purposes.
Although accurate at the time of publication, it is no longer being updated. The page may contain broken links or outdated information, and parts may not function in current web browsers.
Site Map#10. Kepler & Laws#10a. Scale of Solar Sys.#11a. First Law#12. 2nd law#12a. More on 2nd lawGlossaryTimeline
Kepler's Three Laws of Planetary Motion =========================================
An Overview for Science teachers
By David P. Stern
Below is a lecture given on March 23, 2005, to science teachers of Anne Arundel County, Maryland. It contains an overview of Kepler's laws with examples, applications, problems and related history, a resource for classroom materials
It is keyed and linked to appropriate sections of "From Stargazers to Starships." The teachers were also given disks with the web material, allowing it to be accessed off-line.
Much of this overview is drawn from "From Stargazers to Starships", a detailed course on astronomy, Newtonian mechanics, physics of the Sun and spaceflight. Its home page is and it also includes translations (Spanish, Italian and French), a glossary, a timeline, problems, lesson plans, over 500 answers to questions from users and more. It uses algebra and trigonometry (on which a short course is included), stresses conceptual understanding, history, applications and ties to culture and society, and its sections cover a wide range of levels, from middle school to freshman college. A quick guide to sections of "Stargazers" related to Kepler's laws can be found in the section "Kepler's Laws". In what follows, those sections will sometimes be referred to by their numbers. You can also reach the complete list of links either from "Site Map" at the top of this page or from "Back to the Home Page" at the end. Note that addresses here are abbreviated, because you are already logged onto "Stargazers." Thus the home page is Sintro.htm not "Stargazers" contains more material than can ever be covered in a regular class. Still, teachers need a wider knowledge, allowing them to pick and choose material according to circumstances, and to mention odd tidbits without detailed discussion, just to create interest. And some very lucky teachers may sometimes find in class a kid or two who really want to find out more. Such students can be directed here to satisfy their interest. This overview focuses on three items: ---what are Kepler's laws, what do they mean, and why are they important. The laws were formulated between 1609 to 16l9, and are (as usually stated):
Planets move around the Sun in ellipses, with the Sun at one focus
The line connecting the Sun to a planet sweeps equal areas in equal times.
Thesquare of the orbital period of a planet is proportional to the cube (3rd power) of the mean distance from the Sun
(also stated as--...of the "semi-major axis" of the orbital ellipse, half the sum of smallest and greatest distances from the Sun)
The Significance of Kepler's Laws ----------------------------------- Kepler's laws describe the motion of planets around the Sun. Kepler knew 6 planets: Earth, Venus, Mercury, Mars, Jupiter and Saturn. The orbit of the Earth around the Sun. This is a perspective view, the shape of the actual orbit is very close to a circle.
All these (also the Moon) move in nearly the same flat plane (section #2 in "Stargazers"). The solar system is flat like a pancake! The Earth is on the pancake, too, so we see the entire systemedge-on--the entire pancake occupies one line (or maybe a narrow strip) cutting across the sky, known as the ecliptic. Every planet, the Moon and Sun too, move along or near the ecliptic. If you see a bunch of bright stars strung out in a line across the sky--with the line perhaps also including the Moon, (whose orbit is also close to that "pancake"), or the place on the horizon where the Sun had just set--you are probably seeing planets.
Ancient astronomers believed the Earth was the center of the Universe--the stars were on a sphere rotating around it (we now know it's actually the earth that is turning) and the planets were moving on their own "crystal spheres" with variable speed. They usually moved in the same direction, but sometimes their motion reversed for a month or two, and no one knew why.
A Polish clergyman named Nicholas Copernicus figured out by 1543 that those motions made sense if planets moved around the Sun, if the Earth was one of them, and if the more distant ones moved more slowly. The Earth then sometimes overtakes the slower planets more distant from the Sun, making their positions among stars move backwards (for a while). The orbits of Venus and Mercury are inside that of Earth, so they are never seen far from the Sun (e.g. at midnight).
I hope you that describing those features--the "pancake" of the ecliptic, the reversed ("retrograde") motion, Venus always close to the Sun--will help students get a feeling for the appearance of planets in the sky, as bright stars moving along the same track as Sun and Moon. The 12 constellations along that line are known as the zodiac, a name which should be familiar to those who follow astrology. Venus, the brightest planet, seems to bounce back and forth across the position of the Sun, and so does Mercury--but since it is much closer to the Sun, you may only see it whe it is most distant from the Sun, and then only shortly after sunset or before sunrise.
Students will probably have heard or read that the pope and church fought the idea of Copernicus, because in one of the psalms (which are really prayer-poems) the bible says that God "set up the Earth that it will not move" [that was one translation: a more correct one may be "will not collapse"]. Galileo, an Italian contemporary of Kepler who supported the ideas of Copernicus, was tried by the church for disobedience and was sentenced to house arrest for the rest of his life.
It was an age when people often followed ancient authors (like the Greek Aristoteles) rather than check out with their own eyes what Nature was really doing. When people started checking, observing, experimenting and calculating, that brought the era of the scientific revolution and of technology. Our modern technology is the ultimate result, and Kepler's laws (together with Galileo's work, and that of William Gilbert on magnetism) are important, because they started that revolution .
Johannes
Kepler
Kepler worked with Tycho Brahe, a Danish nobleman who pushed pre-telescope astronomy to its greatest precision, measuring positions of planets as accurately as the eye could make out (Brahe died in 1602 in Prague, now the Czech capital; telescopes started with Galileo around 1609). If you want to read about it, I recommend "Tycho and Kepler" by Kitty Ferguson, reviewed at or at least, read the review. Let me quote from it:
Religious intolerance was widespread--indeed, events were moving towards the 30 years' war (1618-48), Europe's most destructive religious battle, mirrored by the civil war in Britain. Kepler was forced out of Graz, among all other employees of Protestant colleges in town, after the ruling archduke decreed they must leave the city by nightfall, that same day. It was also an era when Kepler's mother was arrested for witchcraft, when most of his numerous children died in childhood, and when Tycho's marriage was regarded as a second-rate "slegfred" union because his chosen wife was not from the nobility.
Try to get that across to students, too. 1620 was when the "Pilgrims" landed in Plymouth Rock, fleeing from the outbreak of the religious war which later devastated Europe. Quite possibly it was the memory of such wars that led the US, much later, to decree the separation of church and state. Explain how the development of science and society are often closely related.
Kepler's First Law
(1) Planets move around the Sun in ellipses, with the Sun at one focus
First explain what an ellipse is: one of the "conic sections," shapes obtaining by slicing a cone with a flat surface. A flashlight creates a cone of light: aim it at a flat wall and you get a conic section. Hit the wall perpendicular. The wall cuts the cone perpendicular to its axis and you get a circle of light. Slant the cone relative to the wall: an ellipse. The more you slant, the more far away the ellipse closes. The curves generated as "conic sections" when flat planes are cut across a cone. Finally, if the axis of the cone is parallel to the wall, the curve never closes: you get a parabola. Kepler's laws (as we now know them) allow all conic sections, and parabolas are very close to the orbits of nonperiodic comets, which start very far away. (Tilt still more and you get hyperbolas--not only don't the trajectories close, but the directions of coming and going make a definite angle). Ellipses have other properties--they have two special points, "foci", and if you take any two points on the ellipse, the sum of distances (r 1+r 2) from the two foci is always the same (for that ellipse). The end of section #11 also has a nice story "Whispers in the US Capitol", on how an ellipsoid--the surface created by twirling an ellipse around its axis--can focus sound waves. -------------------------------------- There is much, much more... but let me just bring up two points. They are good points to raise in class, because they bring together Kepler's work of about 1610 with the latest scientific discoveries of the 21st century. First of all, a very famous ellipse is shown below. Its story is told in section #S7-a You probably all know our sun is part of a huge disk-shaped collection of stars--about 100 billion at last count--called the galaxy. It's a flat disk, a pancake like the solar system--and here too, we look at that pancake sideways, so it too cuts out view in a narrow strip. In that strip we see a belt of faint stars running all around the globe of the sky, the "Milky Way." What holds our galaxy (and more distant ones) together? For a long time it was believed there was a humongous black hole in the middle, but that middle was obscured by dust clouds and hence not easy to observe. Recently, high resolution telescopes sensitive to infra red light were built, which can see though the dust, and they have shown a large concentration of fast moving stars near the center of the galaxy, in orbits which obey Kepler's laws. The web site shows the ellipse of a star orbiting the center once in 15.2 years, and calculations deduce a mass of about 3.7 million suns, give or take 1.5 millions. [For astronomers only: the central mass helps keep the galaxy together, but there is a lot of more mass involved, so the rotation of the more extended parts of galaxies does not obey Kepler's 3rd law. In fact, their main parts seem to rotate like solid disks, which is hard to explain unless we assume galaxies contain, in addition to shining stars, a lot of "dark matter" which affects gravity but is invisible. See note and end of #20] Second, we said the Earth orbits the Sun (and by the way, the same laws also hold for artificial satellites that orbit Earth). But imagine you could gradually make Earth heavier and heavier, and the Sun at the same time lighter and lighter. What then? At the point where Earth and Sun are equally heavy--which orbits which? About 50 years after Kepler Isaac Newton explained Kepler's laws (and in doing so, firmly established the "scientific revolution", from there on). Here is what he did:
---First he devised the basic laws of motion--known ever since then as "Newton's 3 laws of motion", and you probably teach them, too.
---Second, he gave us the law of universal gravitation--showed that the same force which caused apples and stones to fall down, also held the Moon in its orbit--and therefore, probably, created all orbits in the solar system.
(For more on that (even that apple), see section #20
)
--and third, he, proved that if the above two held, Kepler's laws could be derived mathematically...
... but with one small change: planets orbited not around the Sun, but around a common center of gravity. While the Earth makes a big circuit each year, the Sun also makes, a very small one, around the Sun-Earth center of gravity.
(actually, the Sun is also moved by Jupiter, Saturn etc.. and the resultant pattern is complicated.)
Why is this important? Because it helps us discover if other stars have planets! We cannot see those planets--too dim--but if the star wiggles back and forth in a complicated way, it may be because a planet makes it move so.
Does it work? Yes and no (end of #11a). Many planets have been discovered this way, but most of them are too close to the star (wiggles on a time scale of weeks) and are very big. To discover Earth-like planets is harder--the wiggle is smaller and we need observe for many years to extract a periodicity of the order of one year. But stay tuned, astronomers are working on it.
Kepler's 2nd law
(2) The line connecting the Sun to a planet sweeps
equal areas in equal times.
(That line is sometimes called "the radius vector"). Illustrating Kepler's 2nd law: segments AB and CD take equal times to cover. An ellipse is symmetric elongated oval, with two foci symmetrically locates towards the "sharper" ends--one focus contains the Sun, the other is empty. (Draw such an ellipse.) If we bring the foci closer and closer, the ellipse appears more and more like a circle,and when they overlap, we do have a circle. [ The Earth's orbit, and most planetary orbits, are very close to circles. If one you were shown the Earth's orbit without the Sun at the focus, you would probably not be able to distinguish it from a circle. With the Sun included, though, you might notice it was slightly off-center.] The point of Kepler's 2nd law is that, although the orbit is symmetric, the motion is not. A planet speeds up as it approaches the Sun, gets its greatest velocity when passing closest, then slows down again. (The star S2 speeds up to 2% of velocity of light when approaching the black hole at the center of our galaxy!) What happen is best understood in terms of energy. As the planet moves away from the Sun (or the satellite from Earth), it loses energy by overcoming the pull of gravity, and it slows down, like a stone thrown upwards. And like the stone, it regains its energy (completely--no air resistance in space) as it comes back. There is an easy exercise here, which is also in section #12A Suppose you have a planet whose smallest/greatest distance from the center are (r 1, r 2)--they are called perihelion and aphelion [ap-helion]) if the center is the Sun, or (perigee, apogee) if the center is the Earth. (Distances are always measured from the center of the bodies, or from centers of gravity) Say it is a planet orbiting the Sun. Then -- the velocity V 1 at perihelion is the fastest one for the orbit. It is therefore the distance covered in one second at perihelion. -- the velocity V 2 at aphelion is the slowest one for the orbit. It is therefore the distance covered in one second at aphelion. The area swept by the "radius vector"r during one second after perihelion is a right-angled triangle of base V 1, so its area is 0.5 r 1 V 1 The area swept by the "radius vector"r during one second after aphelion is a right-angled triangle of base V 2, so its area is 0.5 r 2 V 2 By the law of areas, both areas are the same, so r 1 V 1 = r 2 V 2 Divide both sides by r 1 V 2 and get V 1:V 2 = r 2:r 1 If the aphelion r 2 is 3 times the distance of perihelion, the velocity V 2 there is 3 times slower. (Note: this ratio only works at these two points of the orbit. At other point the velocity and the radius are not perpendicular.) ---------------- When are we closest to the Sun? About January 4th, by about 1.5%, not enough to make the Sun look different. Here is a quick way to demonstrate this asymmetry (although you may not have time to cover it in class). Draw an ellipse, with the long axis and a line perpendicular to it through the Sun) It so happens (pure accident) that spring equinox and fallequinox, when day and night are equal, typically March 21, September 22 or 23, fall very close to that perpendicular line. Look at the schematic view of the Earth's orbit in section #3. The long axis (as defined above) is the line connecting December-June in that drawing, and the perpendicular line is the one connecting March-September. If the orbit were exactly a circle (in which case what we call "long axis would be completely arbitrary, a diameter no different from any other), then by Kepler's 2nd law, the Earth would move at a constant speed and spend equal times in the summer half and the winter half of the year. Actually, it spends about 2 days fewer in the winter half! (Take a calendar and count days from one equinox to the other). That may mean The winter half is shorter, or The Earth moves faster in the winter half Actually, both conditions hold, if Earth is closest to the Sun around January 4. The "half" of the ellipse (determined by the perpendicular line defined above) which is closer to the Sun is smaller (demonstrate with a drawing of an ellipse that is notably oval), and by Kepler's 2nd law, the Earth moves faster when closer to the Sun. ------------------------- The fact the northern hemisphere is closest to the Sun in mid-winter and most distance in mid-summer, moderates the seasons, making them milder. In the southern hemisphere, they would be harsher, although the big oceans there moderate this effect. But the axis of the Earth moves around a cone, in about 26000 years. In 13,000 years we will be closest to the Sun in midsummer, and climate will get harsher. As described in section 7, this may be one effect tied to the origins of ice ages, but the details are beyond the scope of this review. Kepler's 3rd Law ------------------
(3) The square of the orbital period of a planet is proportional
to the cube of the mean distance from the Sun
(also stated as--...of the "semi-major axis" of the orbital ellipse, half the sum of smallest and greatest distances from the Sun)
This is a mathematical law, and your students need calculators with square roots, also 3/2 powers and 2/3 powers (and maybe cube roots or 1/3 powers, same thing)..
If two planets (or two Earth satellites--works the same) have orbital periods T1 and T2 days or years, and mean distances from the Sun (or semi-major axes) A1 and A2 then the formula expressing the 3rd law is
(T 1 / T 2)2 = (A 1 / A 2)3
Students will ask right away--we can count days to get orbital period T (although it may be tricky, we need subtract the Earth's motion around the Sun)--but how do we know distance A?
In truth, we don't, but notice only ratios of distances are needed, and units don't affect ratios. For instance, suppose "Planet 2" is the Earth, and all times are in years. Then T 2 =1 (year) and we can measure all distances in Astronomical Units (AU), the mean Sun-Earth distance, so that A 2 =1 (AU). The law then becomes, for any other planet,(T 1)2 = (A 1)3 This can be checked, and in section 10 you find the results on a table:
| Kepler's 3rd Law T in years, a in astronomical units; then T 2 = a 3 Discrepancies are from limited accuracy | | Planet | Period T | Dist. a fr. Sun | T 2 | a 3 | | Mercury | 0.241 | 0.387 | 0.05808 | 0.05796 | | Venus | 0.616 | 0.723 | 0.37946 | 0.37793 | | Earth | 1 | 1 | 1 | 1 | | Mars | 1.88 | 1.524 | 3.5344 | 3.5396 | | Jupiter | 11.9 | 5.203 | 141.61 | 140.85 | | Saturn | 29.5 | 9.539 | 870.25 | 867.98 | | Uranus | 84.0 | 19.191 | 7056 | 7068 | | Neptune | 165.0 | 30.071 | 27225 | 27192 | | Pluto | 248.0 | 39.457 | 61504 | 61429 | You can see that, even with our limited accuracy, the law holds pretty well. It also shows the greater the distance, the slower the motion, which leads to the overtaking of outer planets by the Earth, making them (for a while) seem to move backwards relative to the fixed stars in the sky. You can prove all this mathematically for circular orbits using Newton's laws (see section #21), but again, I'll skip that. In kilometers the astronomical unit is about 150,000,000 km, 400 times the Moon's distance. All sorts of attempts were made to derive it, starting with the ancient Greek Aristarchus (sect. #9a) and they are discussed in sect #10a. It was first done with any accuracy in 1672, and the excitement over the recent "transit of Venus" in front of the Sun was motivated by a proposal made around then by Halley (of comet fame) to use such rare transits to measure the AU. The most recent ones occurred in 2004 and 2012, then more than a century passes before the next one. A crude version of the calculation, not a short one, is in sections #12c to #12e of "Stargazers". (Some other "methods" can be found on the web, involving the transit of Venus but not its duration, and they are not genuine.) All sorts of problems can be solved with Kepler's 3rd law. Here are a few: 1. How long does it take to reach Mars, in the most efficient orbit? This is called the "Hohmann Transfer Orbit" (Wolfgang Hohmann, 1925). The spaceship must first get free of Earth (it still orbits the Sun together with Earth, at 30 km/s, at a distance of 1 AU), then it adds speed so that its aphelion (in its orbit around the Sun) just grazes the orbit of Mars, A = 1.524 AU (ignoring ellipticity). The Hohmann Transfer Orbit For the Hohmann orbit, the smallest distance is 1.00 AU (Earth), the largest one 1.524 AU (Mars), so the semi-major axis is A = 0.5(1.00 + 1.524) = 1.262 AUA 3 = 2.00992 = T 2 The period is the square root T = 1.412years To reach Mars takes just half an orbit or T/2 = 0.7088 years It equals about 8.5 months; more details are in section #21b. 2. How long would it take for a spacecraft from Earth to reach the Sun? The Sun is the hardest object in the solar system to reach! It's far easier to escape to interstellar space (and those people who propose hurling nuclear waste into the Sun should learn more astronomy.) To reach the Sun directly from Earth, we need shoot the spacecraft free of Earth. It still orbits the Sun with Earth, at 30 km/sec (low Earth orbit only takes 8 km/s), so we need give it an opposing thrust, adding (-30 km/s) to its velocity. It then falls straight into the Sun. That orbit is also an ellipse, though a very skinny one. Its total length is 1 (AU), so the semimajor axis is A = 0.5 AU. By the 3rd law, A 3 = 0.125 = T 2, and taking the square root , T=0.35355 years. We need divide this by 2 (it's a one-way trip!) and multiply by 365.25 to get days. Multiplying: T/2 = (0.5) 0.35355 (365.25) = 64.6 days Note: if you miss the Sun, and the spacecraft does not evaporate in the solar heat, it comes right back to Earth's orbit! 3. How far (from the center of Earth) do synchronous satellites orbit? These are (mostly) communication satellites and have a 24 hour period, which helps match longitude with the same station, keeping it in view at any time. The Moon is at 60 RE (earth radii) away and has a period of T = 27.3217 days (see section 20 on gravitation). The synchronous orbit is circular, so A is also its radius R. We get (R/ 60)3 = R 3 / 216,000 = (1 / 27.3217 days)2 = 1/ (27.3217 days)2 = 1 / 746.5753 so R 3 = 216,00/746.5753 = 289.32 This number is between 6 3 = 216 and 7 3 = 343, so when the calculator gives R = 6.614 RE. you know you've got it about right. 4. How far does Halley's comet go? Its period is about 75 years, and 75 2 = 5625. Take the cube root: A = 17.784 AU. That, however is the SEMImajor axis. The length of the entire orbital ellipse is 2A = 35.57 AU. Perihelion is inside the Earth's orbit, less than 1 AU from the Sun, so aphelion is about 35 AU from the Sun--as the table shows, somewhere between Neptune's orbit and Pluto's ===================================================== If you are a teacher trying to cover Kepler's laws, I hope this quick overview has given you a wide range of tools and insights which may prove useful in the classroom. Now pass it along! You will find a lot more in the web sites described here. First among sections on Kepler's laws: #10 Kepler and his Laws
TimelineGlossaryBack to the Master List
Author and Curator: Dr. David P. Stern
Mail to Dr.Stern: stargaze["at" symbol]phy6.org .
Last updated: 4 April 2014
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Curators: Robert Candey, Alex Young, Tamara Kovalick
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12589 | https://pubs.sciepub.com/wjce/8/3/1/index.html | Choose Your Own (Green) Adventure: A Solventless Aldol Condensation Experiment for the Organic Chemistry Laboratory
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Choose Your Own (Green) Adventure: A Solventless Aldol Condensation Experiment for the Organic Chemistry Laboratory
Theresse M. Robinson, Melinda C. Box, Maria T. Gallardo-Williams
World Journal of Chemical Education. 2020, 8(3), 104-106. DOI: 10.12691/wjce-8-3-1
Received April 16, 2020; Revised May 18, 2020; Accepted May 25, 2020
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Abstract
Aldol condensation reactions are routinely used in organic chemistry teaching labs. In this experiment, we developed a greener method for the aldol condensation experiment of the Organic Chemistry II lab at North Carolina State University. To do this, we used the 12 Principles of Green Chemistry, and altered our current procedure to fit as many of them as possible. The main approach used throughout this process was developing aldol condensation reactions that were completely solventless. We currently have a procedure that allows for all possible combinations of two aldehydes: 4-tolualdehyde and 4-anisaldehyde, and two ketones: acetophenone and 4-methylacetophenone. We have developed a method that not only reduces solvent consumption, but also qualifies under 5 other green chemistry principles: prevention of waste, less hazardous chemical synthesis, reduction of derivatives, accident prevention, and atom economy. This new experimental design allows students to choose the compounds they would prefer to use from a list of available reagents therefore allowing a certain degree of lab personalization.
Keywords:green chemistrysophomore organic labaldol condensationsolventless reactions
1. Introduction
Green Chemistry is a rapidly growing discipline aimed at designing chemical reactions and products that reduce the production of hazardous substances. 1 The twelve principles of green chemistry lay the foundation for this goal and must be utilized at all opportunities to maximize the greenness of the desired reaction. The current method of thinking about Green Chemistry was developed in 1987 from the United Nations Commission on Environment and Development. This commission defined sustainable development as “...meeting the needs of the present without compromising the ability of future generations to meet their own needs.” 2 This commission paved the way to the development of the 12 principles of green chemistry, laid out below. 1
2. Principles of Green Chemistry:
Prevent Waste
Atom Economy
Less Hazardous Synthesis
Design Benign Chemicals
Benign Solvents & Auxiliaries
Design for Energy Efficiency
Use of Renewable Feedstocks
Reduce Derivatives
Catalysis
Design for Degradation
Real-time Analysis for Pollution Prevention
Inherently Benign Chemistry for Accident Prevention.
In recent years, the greening of organic chemistry teaching labs has been well underway, with numerous publications and presentations at conferences involving new lab experiments that incorporated the principles of green chemistry. 3 From alkene isomerization to reduction of a ketone to oxidation of alcohols, many experimental methods have been developed to alter the organic chemistry labs. 2 Even acylation reactions, such as lidocaine synthesis, have been modified to implement green chemistry. 4 Green Chemistry doesn’t just have application in organic chemistry though, it can apply to nanotechnology and even into industry. 5, 6 Introducing the principles of green chemistry into teaching or industrial labs is said to have many benefits beyond just environmental. One study noted that integrating green chemistry into teaching labs at an introductory collegiate level lead to an increase in students’ passion for both chemistry and the green movement. 6
Aldol condensation reactions have been studied extensively, as they are one of the most significant general methods for the formation of carbon-carbon bonds in organic chemistry. 7 This reaction is a common experiment done in a sophomore level organic chemistry lab. While many researchers have aimed to integrate green chemistry into the aldol reaction, they have typically come with a major drawback, such as high hazards or high waste production. 8 Palleros (2004) published a comprehensive paper in the Journal of Chemical Education that provided several examples of this reaction. 9 From this, we aimed to produce a practical resource to use within an undergraduate teaching lab.
We have been interested in the incorporation of green experiments in our organic chemistry lab curriculum. 10 In this experiment, modifications have been made to the traditional aldol condensation used in labs on campus, in order to make it greener. These changes result in a faster reaction time (when compared to the traditional procedure), an elimination of the need for a solvent, a reduction in the amount of waste produced, and a simpler reaction procedure. 9, 11 The modifications fulfill six of the twelve principles of Green Chemistry: prevention of waste, reduction of derivatives, safer solvents and auxiliaries, safer chemistry for accident prevention, less hazardous chemical synthesis, and maximization of atom economy.
3. Experimental
3.1. Reagents Used
The following chemicals were utilized in this experiment: 4-tolualdehyde, 4-anisaldehyde, 4-methylacetophenone, acetophenone, and sodium hydroxide pellets, as well as a 10% aqueous HCl solution. Reagents were purchased from Sigma-Aldrich and Fisher Scientific and used without further purification.
3.2. Procedure
This procedure is written for all possible combinations of the 2 aldehydes and 2 ketones previously mentioned in the Reagents Used section. Using a volumetric pipet, 0.50 mL of the selected aldehyde and 0.40 mL of the selected ketone were added to a mortar. Approximately 0.10 g of solid NaOH was added to the reaction and then using a pestle, was crushed up within the solution. The reaction was ground until the formation of a solid was observed. After the solid began to form, the mixture was allowed to sit for 10 minutes, to ensure completion. Once the 10 minutes had passed, 2 mL of 10% aqueous HCl were added to neutralize any residual NaOH. This mixture was then allowed to sit for an additional 10 minutes, before vacuum filtration was performed. The sample was washed with a small amount of cold 90% ethanol.
3.3. Hazards
The use of proper personal protective equipment, such as eye protection, by researchers was required at all times in the laboratory. Ethanol was handled with caution due to flammability. Both aldehydes (4-anisaldehyde and 4-tolualdehyde) are air sensitive, so the containers were covered with parafilm to avoid contamination. In addition to this, the reagents used are eye, skin, and respiratory irritants and were dispensed within a fume hood. Used solvents and filtrate were disposed of in the organic unwanted liquid material container, while solid product was disposed of in the organic unwanted solid material container.
4. Results and Discussion
This experiment was designed to offer a green alternative to traditional aldol condensation reactions within a second semester organic chemistry lab. Introducing a procedure that incorporates several principles of green chemistry, such as reduced auxiliaries, atom economy, and waste reduction, could be beneficial to students. The traditional procedure requires students to combine acetone and acetophenone with a 1:1 95% ethanol: 3M sodium hydroxide solution in an Erlenmeyer flask. The students then stir intermittently for 15 minutes, isolate the product, and recrystallize. This procedure leads to low yields and impure products (as determined through melting point analysis). 11 The proposed procedure will require students to mix one of two aldehydes (4-tolualdehyde or 4-anisaldehyde) with one of two ketones (acetophenone or 4-methylacetophenone) in the presence of a pellet of sodium hydroxide in a mortar. The students then grind the solution until a solid is observed. Next, they use a small amount of 10% HCl to neutralize the product, followed by filtering and washing with cold 90% ethanol. No recrystallization was necessary with these products as they have moderate to high purity based on IR spectroscopy and melting point analysis, with the exception of the combination of anisaldehyde and acetophenone, which did not react.
Table 1 shows the three combinations of aldehydes and ketones that were tested in this experiment. These combinations (options 1-3) are then compared to the traditional aldol reaction done with benzaldehyde and acetone in Table 2.
Table 2 below shows a comparative analysis of the greenness of the two procedures. The comparison was limited to the 6 principles of green chemistry that the proposed procedure enhanced from the prior method.
Table 1. Combinations of aldehydes and ketones tested for green aldol condensation reaction
Tables index View option Full SizeNext Table
Table 2. Comparative analysis of a current and the proposed procedures for an aldol condensation reaction
Tables index View option Full SizePrevious Table
As seen in Table 2, the proposed method offers many green benefits when compared to the current one, such as the elimination of solvent, reduction of waste and derivatives, curtailment of hazardous risks, improvement of atom economy, and enhancement of accident prevention. An additional benefit of the proposed procedure is that with the multiple choices and reduction of reaction time, students are able to synthesize more than one product, thus giving them more practice with the various techniques used. Students also have more time to analyze the IR spectra and melting point data to determine the relative purity of the product.
5. Conclusion
The aldol condensation is a very useful reaction in organic chemistry for its ability to form carbon-carbon bonds; it is also a relatively simple procedure in use in many teaching labs. Some current methods tend to result in low yields and purity. In this experiment, we redesigned this method to enhance the green chemistry aspect of the reaction and increased the number of possible reagents in order to give students a degree of choice when completing the experiment. The modifications of the experiment to meet the principles of green chemistry resulted in a new procedure that not only produced high yields and purity, but also eliminated the use of solvents, reduced derivative formation, reduced chemical risks, increased atom economy, and decreased the chance of accidents.
Acknowledgments
We thank the Department of Chemistry at North Carolina State University for financial support of this project.
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In articleView Article
Palleros, D.R.; Solvent-Free Synthesis of Chalcones. J. Chem. Ed., 2004, 81 (9), 1345.
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Crouse, B.J., Vernon, E.L., Hubbard, B.A., Kim, S., Box, M.C., Gallardo-Williams, M.T.; Microwave Extraction of Eugenol from Cloves: A Greener Undergraduate Experiment for the Organic Chemistry Lab. World J. Chem. Ed., 2019, 7 (1), 21-25.
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Published with license by Science and Education Publishing, Copyright © 2020 Theresse M. Robinson, Melinda C. Box and Maria T. Gallardo-Williams
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Theresse M. Robinson, Melinda C. Box, Maria T. Gallardo-Williams. Choose Your Own (Green) Adventure: A Solventless Aldol Condensation Experiment for the Organic Chemistry Laboratory. World Journal of Chemical Education. Vol. 8, No. 3, 2020, pp 104-106.
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Robinson, Theresse M., Melinda C. Box, and Maria T. Gallardo-Williams. "Choose Your Own (Green) Adventure: A Solventless Aldol Condensation Experiment for the Organic Chemistry Laboratory." World Journal of Chemical Education 8.3 (2020): 104-106.
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Robinson, T. M. , Box, M. C. , & Gallardo-Williams, M. T. (2020). Choose Your Own (Green) Adventure: A Solventless Aldol Condensation Experiment for the Organic Chemistry Laboratory. World Journal of Chemical Education, 8(3), 104-106.
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Robinson, Theresse M., Melinda C. Box, and Maria T. Gallardo-Williams. "Choose Your Own (Green) Adventure: A Solventless Aldol Condensation Experiment for the Organic Chemistry Laboratory." World Journal of Chemical Education 8, no. 3 (2020): 104-106.
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1. Introduction
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Table 1. Combinations of aldehydes and ketones tested for green aldol condensation reaction
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Table 2. Comparative analysis of a current and the proposed procedures for an aldol condensation reaction
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Anastas, P. T.; Warner, J. C. Green Chemistry: Theory and Practice, Oxford University Press: New York, 1998, p.30.
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Haack, J.A., Hutchison, J.E., Kirchoff, M.M., Levy, I.V., Going Green: Lecture Assignments and Lab Experiments for the College Curriculum. J. Chem. Educ., 2005, 82(7), 974-976.
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Lancaster, M.; Green Chemistry: An Introductory Text, RSC Publishing, Cambridge, 2010.
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Josephson, P., Nykvist, V., Qasim, W., Blomkvist, B., Diner, P., Student-Driven Development of Greener Chemistry in Undergraduate Teaching: Synthesis of Lidocaine Revisited. J. Chem. Educ., 2019, 96, 1389-1394.
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Sharma, R.K., Gulati, S., Mehta, S., Preparation of Gold Nanoparticles Using Tea: A Green Chemistry Experiment. J. Chem. Educ., 2012, 89, 1316-1318.
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Bodner, G.M.,The Quadruple Bottom Line: The Advantages of Incorporating Green Chemistry into the Undergraduate Chemistry Major. Phys. Sci. Rev., 2017, 2(9), 10.1515.
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Clayden, J.; Greeves, N.; Warren, S. In Organic Chemistry; Oxford University Press: New York, 2012; 614-640.
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Mestres, R., A Green Look at the Aldol Reaction. Green. Chem., 2004, 6 (12), 283.
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Palleros, D.R.; Solvent-Free Synthesis of Chalcones. J. Chem. Ed., 2004, 81 (9), 1345.
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Crouse, B.J., Vernon, E.L., Hubbard, B.A., Kim, S., Box, M.C., Gallardo-Williams, M.T.; Microwave Extraction of Eugenol from Cloves: A Greener Undergraduate Experiment for the Organic Chemistry Lab. World J. Chem. Ed., 2019, 7 (1), 21-25.
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百分比变化_Percentage Change
什么是百分比变化？
百分比变化是一种简单的计算方法，广泛应用于金融和商业领域，例如评估某段时间内股票或其他投资的相对表现。以下是计算方法。
主要要点
百分比变化在金融中有多种用途，尤其用于跟踪和比较股票、债券及市场指数的表现。
企业也利用百分比变化比较当前表现与过去某一时刻的差异。
计算百分比变化的方法在变化代表增加或减少时略有不同。
百分比变化的工作原理
任何通过时间测量的数量都可以计算百分比变化。在金融领域，百分比变化公式常用于跟踪大型市场指数（如标准普尔500或道琼斯工业平均指数）和个别证券的价格，以及比较不同国家货币的波动价值。
百分比变化在商业中同样被广泛使用，例如企业在资产负债表中展示其年度收入增长情况。如果百分比变化显著，企业通常会尝试解释原因。例如，星巴克在2020年第三季度报告中称，与2019年同期相比，净收入下降了38%，原因是“受COVID-19的负面影响。” 随后的季度报告显示，星巴克的收入逐渐恢复，净收入的百分比变化也为正值，因为因COVID-19引起的商业中断逐渐减小。
注意: 百分比变化与其它金融公式一样，可以通过电子表格进行计算，例如微软Excel或谷歌表格。
百分比变化的公式和计算
要计算百分比增加，首先确定您比较的两个数字之间的差值（增加）：
增加=新数字−原始数字\begin{aligned}\text{增加}=\text{新数字}-\text{原始数字}\end{aligned}增加=新数字−原始数字
接下来，将增加值除以原始数字，并将结果乘以100：
百分比增加=(增加 原始数字)×100.\begin{aligned}\text{百分比增加}=\left(\frac{\text{增加}}{\text{原始数字}}\right)\times100.\end{aligned}百分比增加=(原始数字 增加)×100.
这将变化表示为百分比——即百分比变化。
同样地，要计算百分比减少，首先确定两个数字之间的差值（减少）。
减少=原始数字−新数字\begin{aligned}\text{减少}=\text{原始数字}-\text{新数字}\end{aligned}减少=原始数字−新数字
接下来，将减少值除以原始数字，并将结果乘以100。
百分比减少=(减少 原始数字)×100\begin{aligned}\text{百分比�减少}=\left(\frac{\text{减少}}{\text{原始数字}}\right)\times 100\end{aligned}百分比减少=(原始数字 减少)×100
最终结果以百分比形式表示变化——即百分比变化。
提示: 如果只想记住一个公式，可以使用正增加的公式。结果将是正数或负数（如果使用两个公式，结果始终为正），这可以告诉您百分比变化是增加（正数）还是减少（负数）。
百分比变化的用途
投资者、公司和整个行业可以通过分析价格或其它指标如何在不同时间段内变化而受益。以下是投资者如何利用百分比变化计算获得优势的一些方式：
衡量单个投资回报：各种资产（如股票、债券或共同基金）的投资回报率（ROI）通常以百分比变化的形式表示。这帮助投资者评估其资产在特定时间段内的表现，并与其他可能的投资进行比较。
评估投资组合：除计算投资组合内各个资产的百分比变化外，投资者也可以计算整个投资组合的变化。这对于确定当前资产配置是否能带来所需回报，或是否需要考虑重新平衡十分有用。
分析价格变动：股票、商品或其他金融工具价格的百分比变化有助于识别趋势、波动性和潜在交易机会。
与基准对比：投资者可以将其投资的百分比变化与相关股票指数或其它基准的百分比变化进行比较，以查看其持仓是否超越或落后于市场。如果明显落后于基准，值得探讨原因。
风险管理：使用止损单保护自己免受投资价值大幅下跌影响的投资者，可以根据百分比变化设定目标。
百分比变化计算示例
以计算百分比变化为例，假设Grace在去年1月1日以每股35美元购买了一只股票。一年后，该股票价值每股45.50美元。Grace的股票价值增加了多少百分比？
要回答这个问题，首先计算新旧数字之间的价格变化：45.50−45.50 - 45.50−35 = $10.50。然后将增加值除以原始价格：
10.5 35=0.3\begin{aligned}\frac{10.5}{35}=0.3\end{aligned}35 10.5=0.3
0.3×100=30\begin{aligned}0.3\times100=30\end{aligned}0.3×100=30
如何计算百分比变化？
如果您在跟踪价格增加，请使用公式：(新价格 - 旧价格) ÷ 旧价格，然后将该数字乘以100。相反，如果价格下降，请使用公式：(旧价格 - 新价格) ÷ 旧价格，并将该数字乘以100。
什么是资产负债表，与百分比变化有什么关系？
资产负债表是公司用于报告资产、负债和股东权益的财务报表。资产负债表提供了公司在特定时间段（如一个季度或一个财政年度）的财务快照。
许多公司选择通过检查从一个时期到下一个时期特定账户余额的百分比变化来分析其资产负债表。例如，一家公司可以通过观察过去几年的现金余额的百分比变化来检查其即时流动性趋势。
百分比变化在金融中的应用
百分比变化常被投资者用于跟踪证券价值随时间的增加或减少，并将其与相关指数的表现进行比较。它还用于比较不同国家货币的价值变化，以及衡量如房地产等实物资产的升值。
总结
百分比变化是一种简单的计算方法，在金融和商业中有多种用途。如果投资者希望迅速了解某项投资的表现，将其百分比变化与相同时间段内类似投资的百分比变化进行比较即可得到答案。
参考文献
Starbucks Stories & News. "Starbucks Reports Q3 Fiscal 2020 Results."
Starbucks Investor Relations. "Starbucks Reports Record Q4 and Full Year 2021 Results."
Reed.edu. "Percentage Change and Percentage Point Change: A Primer."
Harvard Business School Online. "How to Prepare a Balance Sheet: 5 Steps for Beginners."
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什么是百分比变化？
主要要点
百分比变化的工作原理
百分比变化的公式和计算
百分比变化的用途
百分比变化计算示例
如何计算百分比变化？
什么是资产负债表，与百分比变化有什么关系？
百分比变化在金融中的应用
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/8
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What is (5 + 6i) + (4 - 3i)?
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EASY
Simplify the expression:
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HARD
Simplify the expression:
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Let and .What is ?
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Write the complex number √-7
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12593 | https://mathworld.wolfram.com/ParallelLines.html | Parallel Lines -- from Wolfram MathWorld
TOPICS
AlgebraApplied MathematicsCalculus and AnalysisDiscrete MathematicsFoundations of MathematicsGeometryHistory and TerminologyNumber TheoryProbability and StatisticsRecreational MathematicsTopologyAlphabetical IndexNew in MathWorld
Geometry
Line Geometry
Concurrence
Parallel Lines
Two lines in two-dimensional Euclidean space are said to be parallel if they do not intersect.
In three-dimensional Euclidean space, parallel lines not only fail to intersect, but also maintain a constant separation between points closest to each other on the two lines. Therefore, parallel lines in three-space lie in a single plane (Kern and Blank 1948, p.9). Lines in three-space which are not parallel but do not intersect are called skew lines.
Two trilinear lines
(1)
(2)
are parallel if
(3)
(Kimberling 1998, p.29).
See also
Café Wall Illusion, Coplanar, Intersecting Lines, Parallel, Parallel Curves, Parallel Line and Plane, Parallel Planes, Parallel Postulate, Perpendicular, Ponzo's Illusion, Proclus' Axiom, Skew Lines, Zöllner's Illusion
Explore with Wolfram|Alpha
More things to try:
concur
ackermann[2,3]
Clebsch-Gordan calculator
References
Kern, W.F. and Bland, J.R. Solid Mensuration with Proofs, 2nd ed. New York: Wiley, p.9, 1948.Kimberling, C. "Triangle Centers and Central Triangles." Congr. Numer.129, 1-295, 1998.
Referenced on Wolfram|Alpha
Parallel Lines
Cite this as:
Weisstein, Eric W. "Parallel Lines." From MathWorld--A Wolfram Resource.
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Concurrence
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Created, developed and nurtured by Eric Weisstein at Wolfram Research |
12594 | https://www.quora.com/What-is-the-formula-for-finding-the-altitude-of-a-triangle-with-two-angles-one-side-length-and-another-side-length | What is the formula for finding the altitude of a triangle with two angles, one side length, and another side length? - Quora
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5
What is the formula for finding the altitude of a triangle with two angles, one side length, and another side length?
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Bheema Mudda
Former Rtd Director at Government of India (2002–2007) · Author has 4.8K answers and 2.8M answer views
·1y
suppose ∠ A,∠C &side b are given ; ∠ B = 180-∠A-∠C so ∠ B is known
h =Altitude =b sinC
applying Sine Rule : a/SinA =b/SinB= c/SinC
a SinB=b sinA==> b= aSinB sinA in RHS all variables known so b is calculated
repeat for other variations
Continue Reading
suppose ∠ A,∠C &side b are given ; ∠ B = 180-∠A-∠C so ∠ B is known
h =Altitude =b sinC
applying Sine Rule : a/SinA =b/SinB= c/SinC
a SinB=b sinA==> b= aSinB sinA in RHS all variables known so b is calculated
repeat for other variations
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More answers below
How can we find the other two sides and altitude of a triangle if we are given one side length?
If one side of a triangle is twice as long as another, what is the length of its height or altitude?
What is the length of the altitude of an equilateral triangle with a side of 6 cm?
Two sides of a triangle are of length 5 cm and 14 cm. what is the length of third side?
Is there a triangle with sides 1 2 and 3?
Peter Shea
B. Sc in Mathematics&Computer Science, Monash University (Graduated 1972) · Author has 5.2K answers and 1.2M answer views
·1y
QPG, if you know 2 angles, you can calculate the remaining angle because the total of all angles is 180 degrees.
Then you can use the Sine Rule to calculate a missing side if you need it. Then you are guaranteed to know the base.
Using cosines, you can calculate any desired altitude.
This gives
Upvote ·
Pradeep Hebbar
Many years of Structural Engineering & Math enthusiasm · Author has 9.3K answers and 6.2M answer views
·Mar 19
Related
If the length of the sides of a triangle are in the ratio of 4:5:6 and the inradius of the triangle is 3 cm, what is the altitude of the triangle corresponding to the largest base?
Let the given triangle be A B C A B C having side lengths in the ratio A B:B C:A C=4:5:6 A B:B C:A C=4:5:6
Let A B=4 k A B=4 k, B C=5 k B C=5 k and A C=6 k A C=6 k
Let h 1 h 1, h 2 h 2 and h 3 h 3 respectively be the lengths of altitudes drawn on A B A B, B C B C and A C A C
Let T T be the area and r r be the inradius of triangle
T=1 4√[(4 k+5 k+6 k)(4 k+5 k−6 k)(4 k+6 k−5 k)(5 k+6 k−4 k)T=1 4[(4 k+5 k+6 k)(4 k+5 k−6 k)(4 k+6 k−5 k)(5 k+6 k−4 k)
T=15 k 2√7 4 T=15 k 2 7 4
Now,
A B×h 1 2=T⟹1 h 1=4 k 2 T A B×h 1 2=T⟹1 h 1=4 k 2 T
Similarly,
1 h 2=5 k 2 T 1 h 2=5 k 2 T
1 h 3=6 k 2 T 1 h 3=6 k 2 T
We have,
1 r=1 h 1+1 h 2+1 h 3 1 r=1 h 1+1 h 2+1 h 3
\dfrac{1}{r}=\dfrac{4k}{2T}+\dfrac{5k}{2T}+\dfrac{6k}{\dfrac{1}{r}=\dfrac{4k}{2T}+\dfrac{5k}{2T}+\dfrac{6k}{
Continue Reading
Let the given triangle be A B C A B C having side lengths in the ratio A B:B C:A C=4:5:6 A B:B C:A C=4:5:6
Let A B=4 k A B=4 k, B C=5 k B C=5 k and A C=6 k A C=6 k
Let h 1 h 1, h 2 h 2 and h 3 h 3 respectively be the lengths of altitudes drawn on A B A B, B C B C and A C A C
Let T T be the area and r r be the inradius of triangle
T=1 4√[(4 k+5 k+6 k)(4 k+5 k−6 k)(4 k+6 k−5 k)(5 k+6 k−4 k)T=1 4[(4 k+5 k+6 k)(4 k+5 k−6 k)(4 k+6 k−5 k)(5 k+6 k−4 k)
T=15 k 2√7 4 T=15 k 2 7 4
Now,
A B×h 1 2=T⟹1 h 1=4 k 2 T A B×h 1 2=T⟹1 h 1=4 k 2 T
Similarly,
1 h 2=5 k 2 T 1 h 2=5 k 2 T
1 h 3=6 k 2 T 1 h 3=6 k 2 T
We have,
1 r=1 h 1+1 h 2+1 h 3 1 r=1 h 1+1 h 2+1 h 3
1 r=4 k 2 T+5 k 2 T+6 k 2 T 1 r=4 k 2 T+5 k 2 T+6 k 2 T
1 r=15 k 2 T 1 r=15 k 2 T
1 3=15 k 2(15 k 2√7 4)⟹k=6√7 1 3=15 k 2(15 k 2 7 4)⟹k=6 7
Now, h 3 h 3 is the length of altitude drawn on largest side length,
1 h 3=4 5√7(6√7)1 h 3=4 5 7(6 7)
h 3=15 2 h 3=15 2
Ans: 7.5 7.5 cm
Upvote ·
99 11
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Mr AB
If you need an answer, you will get an answer · Author has 4K answers and 2.5M answer views
·1y
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How do you find the altitude of a triangle given the side lengths and base angles?
A figure is given below for demonstration purpose:
We will use Trigonometry to find the length of the altitude with base angles and side lengths gi...
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A figure is given below for demonstration purpose:
We will use Trigonometry to find the length of the altitude with base angles and side lengths gi...
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Here are a couple of the worst mistakes I’ve seen people make:
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If you aren’t using an ad blocker yet, you definitely should be.
A good ad blocking app will eliminate virtually all of the ads you’d see on the internet before they load.
No more YouTube ads, no more banner ads, no more pop-up ads, etc.
Most people I know use Total Adblock (link here) - it’s about £2/month, but there are plenty of solid options.
Ads also typically take a while to load, so using an ad blocker reduces loading times (typically by 50% or more). They also block ad tracking pixels to protect your privacy, which is nice.
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I've used Freecash in the past - it’s solid. (They also gave me a £3 bonus instantly when I installed my first game, which was cool).
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Related questions
More answers below
Two sides of a triangle is 23 cm. What is the length of the third side?
How can we determine the values of all three angles of a triangle without knowing any side lengths, given that one side length and two angles are known?
What is the length of an altitude of an equilateral triangle each of whose sides in 8 cm long?
What is the formula for calculating side length from altitude?
What happens to the other two sides and angles of a triangle if one side has a length of zero? What are their lengths and angles?
Wes Luo
Former Health Professional (Retired) · Author has 2K answers and 1M answer views
·2y
Related
How can you find the height of a triangle if you know two angles and one side?
Heights of a triangle may differ depending on which side of the triangle is considered as base.
Take ΔABC, with sides a,b,c opposite to ∠s A,B,C.
∠A, ∠ B and c are known. Configuration ASA.
We want to find h₁ on c. ∠C is 180-∠B -∠A.
Proceed to find a. Using sine ratio, a=c(sinA)/(sinC). ∴ h₁=asinB
To find h₂ on b, h₂ = c sin A
To find h₃ on a, h₃ = c sin B.
If instead ∠A, ∠C and c are known, the configuration is AAS, the third ∠B = 180°-∠C-∠A. Then solve all the heights as before.
Alternately you can find the area first using configuration SAS, but that requires find the two missing sides first usin
Continue Reading
Heights of a triangle may differ depending on which side of the triangle is considered as base.
Take ΔABC, with sides a,b,c opposite to ∠s A,B,C.
∠A, ∠ B and c are known. Configuration ASA.
We want to find h₁ on c. ∠C is 180-∠B -∠A.
Proceed to find a. Using sine ratio, a=c(sinA)/(sinC). ∴ h₁=asinB
To find h₂ on b, h₂ = c sin A
To find h₃ on a, h₃ = c sin B.
If instead ∠A, ∠C and c are known, the configuration is AAS, the third ∠B = 180°-∠C-∠A. Then solve all the heights as before.
Alternately you can find the area first using configuration SAS, but that requires find the two missing sides first using sine ratios. From area A, height h₁ can be found from 2A/c.
Also note that all heights of the triangle merge at a point at the orthocentre of the circle. An orthocentre could be located outside of the circle if the triangle is obtuse.
Upvote ·
9 1
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Gary Ward
MaEd in Education&Mathematics, Austin Peay State University (Graduated 1997) · Author has 4.9K answers and 7.6M answer views
·May 4
Related
What is the formula for finding the missing side lengths in a right triangle with one known side length and two known angles, one of which is 90 degrees?
What is the formula for finding the missing side lengths in a right triangle with one known side length and two known angles, one of which is 90 degrees?
Taking A to be your other known angle,
if side length a is known: b = a/tan A and c = a/sin A
if side length b is known a = b · tan A and c = b/cos A
if hypotenuse c is known a = c · sin A and b = c · cos A
It’s SOH-CAH-TOA
(Sin A)/1 = a/c, (Cos A)/1 = b/c, and (Tan A)/1 = a/b
Just a little insight. You can work these like proportions. If A = 30°, the sin A = 0.5/1 = 5/10, 5/10=a/c.
Plug in the known side and solve for the unknown side.
Continue Reading
What is the formula for finding the missing side lengths in a right triangle with one known side length and two known angles, one of which is 90 degrees?
Taking A to be your other known angle,
if side length a is known: b = a/tan A and c = a/sin A
if side length b is known a = b · tan A and c = b/cos A
if hypotenuse c is known a = c · sin A and b = c · cos A
It’s SOH-CAH-TOA
(Sin A)/1 = a/c, (Cos A)/1 = b/c, and (Tan A)/1 = a/b
Just a little insight. You can work these like proportions. If A = 30°, the sin A = 0.5/1 = 5/10, 5/10=a/c.
Plug in the known side and solve for the unknown side.
Upvote ·
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Subramanya R
Former Retired Govt Employee, Interested in All Fields · Author has 2K answers and 1.5M answer views
·10mo
Related
What is the formula for finding the radius and height of an equilateral triangle using its area and one side length?
What is the formula for finding the radius and height of an equilateral triangle using its area and one side length?
Let given side length be ‘a’ of an equilateral triangle, then its perimeter is 3a Let given side length be ‘a’ of an equilateral triangle, then its perimeter is 3a
That is ;P=3 a That is ;P=3 a
Also, the relation between its in-radius and perimeter is P=6√3 r Also, the relation between its in-radius and perimeter is P=6 3 r
where radius is denoted by r where radius is denoted by r
∴6√3 r=3 a−−−(1)∴6 3 r=3 a−−−(1)
\boxed{r=\dfrac{a}{2\sqrt{3\boxed{r=\dfrac{a}{2\sqrt{3
Continue Reading
What is the formula for finding the radius and height of an equilateral triangle using its area and one side length?
Let given side length be ‘a’ of an equilateral triangle, then its perimeter is 3a Let given side length be ‘a’ of an equilateral triangle, then its perimeter is 3a
That is ;P=3 a That is ;P=3 a
Also, the relation between its in-radius and perimeter is P=6√3 r Also, the relation between its in-radius and perimeter is P=6 3 r
where radius is denoted by r where radius is denoted by r
∴6√3 r=3 a−−−(1)∴6 3 r=3 a−−−(1)
r=a 2√3 r=a 2 3
Relation between in-radius and circum - radius is R=2r, whence circum-radius Relation between in-radius and circum - radius is R=2r, whence circum-radius
is denoted by R is denoted by R
Accordingly, circum-radius is :R=a√3 Accordingly, circum-radius is :R=a 3
Relation between inradius and circumference radius of eq. Triangle is :Relation between inradius and circumference radius of eq. Triangle is :
h=3 r; here h denotes height.h=3 r; here h denotes height.
Then,h=3 r Then,h=3 r
Accordingly,h=3 a 2√3 Accordingly,h=3 a 2 3
h=√3 a 2 h=3 a 2
Let given area of the equilateral triangle be A.Then relation between its Let given area of the equilateral triangle be A.Then relation between its
inradius and area is A=3√3 r 2; r denotes inradius.inradius and area is A=3 3 r 2; r denotes inradius.
r=√A 3√3 r=A 3 3
Circumradius is:R=2√A 3√3 Circumradius is:R=2 A 3 3
[math]\tex...
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Jesus Sanchez
Software Developer at TrianCal (2015–present) · Author has 342 answers and 1.1M answer views
·1y
Related
What is the method for finding the remaining sides of a triangle if one side, altitude, and area are given?
a = side a
b = side b
c = side c
h = height from side a
t = triangle area
a = 2t/h
c = √(b²h²+4t²±4ht√(b²-h²))/h (normaly 2 solutions)
Example with TrianCal:
Continue Reading
a = side a
b = side b
c = side c
h = height from side a
t = triangle area
a = 2t/h
c = √(b²h²+4t²±4ht√(b²-h²))/h (normaly 2 solutions)
Example with TrianCal:
Upvote ·
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Girija Warrier
Author of the book ‘Madeira Math 500’ (2018–present) · Author has 5.9K answers and 13.9M answer views
·4y
Related
Is there a formula for me to calculate the remaining side of a triangle when two sides and an angle are not included?
Yes! I derived a formula… In a triangle ABC , if 2 sides AB & AC are known. & non-included <C is known
We can find out the measure of BC first. Then with the help of T-ratio, find the remaining angles.
In the following triangle ABC, let AB = 3 , AC = 4 &< C = 30 deg Construct altitude AD from A to BC
BC = BD + DC
FORMULA:
❇️BC = √{AB^2 - AC^2Sin^2(C)} + √{AC^2 - AC^2Sin^2(C)} ❇️
How did I generate the formula ❓❓➡️
Let DC= x => AD = √(16-x^2)
Sin30deg = AD/AC = √(16-x^2) / 4 = 1/2
=> 16-x^2 = 4 => x^2 = 12 => x =√12
=>DC = √12……………. (1)
ie DC = √{AC^2 - AC^2sin^(2)<C}
So, AD = √(16–12) =2
Now, BD^2 = A
Continue Reading
Yes! I derived a formula… In a triangle ABC , if 2 sides AB & AC are known. & non-included <C is known
We can find out the measure of BC first. Then with the help of T-ratio, find the remaining angles.
In the following triangle ABC, let AB = 3 , AC = 4 &< C = 30 deg Construct altitude AD from A to BC
BC = BD + DC
FORMULA:
❇️BC = √{AB^2 - AC^2Sin^2(C)} + √{AC^2 - AC^2Sin^2(C)} ❇️
How did I generate the formula ❓❓➡️
Let DC= x => AD = √(16-x^2)
Sin30deg = AD/AC = √(16-x^2) / 4 = 1/2
=> 16-x^2 = 4 => x^2 = 12 => x =√12
=>DC = √12……………. (1)
ie DC = √{AC^2 - AC^2sin^(2)<C}
So, AD = √(16–12) =2
Now, BD^2 = AB^2 - AD^2 = 9 - 4 = 5
ie BD = √{AB^2 - AC^2sin^(2)<C}
=>BD = √5 …………….. (2)
& BC = BD + DC ( by adding (1) & (2) )
This way I generated the above formula by adding BD & DC
Now, find <B. Since SinB = AD/AB = 2/3
=><B = sin^(-1)2/3
Then, by angle sum property of a triangle calculate the third <A
Upvote ·
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Dhrubajyoti Bhattacharjee
BSMS(Dual) Mathematics from National Institute of Technology, Agartala (Graduated 2023) · Author has 624 answers and 1.6M answer views
·Updated 2y
Related
If the length of the sides of a triangle are in the ratio of 4:5:6 and the inradius of the triangle is 3 cm, what is the altitude of the triangle corresponding to the largest base?
Let us name the triangle as A B C A B C.
Consider the figure shown in the above picture.
I've taken the side lengths as 4 x 4 x cm, 5 x 5 x cm, and 6 x 6 x cm respectively; where x x is a proportionality constant.
In Δ A B C,Δ A B C,
A B=4 x c m,B C=6 x c m A B=4 x c m,B C=6 x c m, and A C=5 x c m.A C=5 x c m.
Clearly, B C B C is the largest side (base) and A D A D is the corresponding altitude.
Suppose, A D=h c m A D=h c m.
Now, we will use the following formula:
Δ=r×s Δ=r×s where Δ Δ is the area of the triangle, r r is the inradius (=3=3 cm, given) and s s is the semi-perimeter.
Next, substituting the values of Δ,Δ,r,r, and s s in the aforesaid formu
Continue Reading
Let us name the triangle as A B C A B C.
Consider the figure shown in the above picture.
I've taken the side lengths as 4 x 4 x cm, 5 x 5 x cm, and 6 x 6 x cm respectively; where x x is a proportionality constant.
In Δ A B C,Δ A B C,
A B=4 x c m,B C=6 x c m A B=4 x c m,B C=6 x c m, and A C=5 x c m.A C=5 x c m.
Clearly, B C B C is the largest side (base) and A D A D is the corresponding altitude.
Suppose, A D=h c m A D=h c m.
Now, we will use the following formula:
Δ=r×s Δ=r×s where Δ Δ is the area of the triangle, r r is the inradius (=3=3 cm, given) and s s is the semi-perimeter.
Next, substituting the values of Δ,Δ,r,r, and s s in the aforesaid formula, we get:
1 2×(6 x)×h=3×(4 x+5 x+6 x)2⇒1 2×(6 x)×h=3×15 x 2⇒2 h=15∴h=7.5.1 2×(6 x)×h=3×(4 x+5 x+6 x)2⇒1 2×(6 x)×h=3×15 x 2⇒2 h=15∴h=7.5.
Thus, we get the required length of the altitude (A D)(A D) corresponding to the largest base (B C)(B C) as 7.5 c m.■7.5 c m.◼
Thank You!
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Rick Marcus
Former R&D Engineer at Stanford University (1983–1989) · Author has 823 answers and 121.4K answer views
·1y
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What is the formula for calculating an unknown length in a right-angled triangle when two lengths and one angle are known?
The angle ‘c’ is 90 degrees.
Since this is a right triangle, you don’t need to know either of the two acute angles to determine the unknown length.
If ‘A’ and ‘B’ are known, you can use the Pythagorean Theorem to find the length of the hypotenuse ‘C’.
C^2=A^2+B^2
You can use the Pythagorean Theorem to determine the length of ‘B’ if ‘A’ and ‘C’ are known.
A^2+B^2=C^2
B^2=C^2-A^2
If the length ‘C’ is known and the angle ‘a’ is known, you can use the trig function Cosine to determine the length of B.
cos(a)=B/C
B=Ccos(a)
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The angle ‘c’ is 90 degrees.
Since this is a right triangle, you don’t need to know either of the two acute angles to determine the unknown length.
If ‘A’ and ‘B’ are known, you can use the Pythagorean Theorem to find the length of the hypotenuse ‘C’.
C^2=A^2+B^2
You can use the Pythagorean Theorem to determine the length of ‘B’ if ‘A’ and ‘C’ are known.
A^2+B^2=C^2
B^2=C^2-A^2
If the length ‘C’ is known and the angle ‘a’ is known, you can use the trig function Cosine to determine the length of B.
cos(a)=B/C
B=Ccos(a)
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Roy Østensen
Translator with fondness of numbers (mathematics) · Author has 1.1K answers and 1.2M answer views
·7y
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A triangle has side lengths 10, 17 and 21 cm. What is the length of the shortest altitude?
Answer: The shortest altitude is 8 cm
Explanation
What we can know before we start to calculate, is that the shortest altitude must be from the corner between the two shortest sides and down on the longest side. We, therefore, want to know the length of CE=h in the following figure.
We have two right angled triangles here, ACE and BCE. Pythagoras, therefore gives us:
h 2=10 2−x 2=17 2−(21−x)2 h 2=10 2−x 2=17 2−(21−x)2
We, therefore, have
100−x 2=289−(21 2–42 x+x 2)100−x 2=289−(21 2–42 x+x 2)
−x 2=189−441+42 x−x 2−x 2=189−441+42 x−x 2
42 x=441−189=252 42 x=441−189=252
x=6
As 6, 8, and 10 is a variation of the well known right triangle, we can deduct that h=8 h=8 without actually using
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Answer: The shortest altitude is 8 cm
Explanation
What we can know before we start to calculate, is that the shortest altitude must be from the corner between the two shortest sides and down on the longest side. We, therefore, want to know the length of CE=h in the following figure.
We have two right angled triangles here, ACE and BCE. Pythagoras, therefore gives us:
h 2=10 2−x 2=17 2−(21−x)2 h 2=10 2−x 2=17 2−(21−x)2
We, therefore, have
100−x 2=289−(21 2–42 x+x 2)100−x 2=289−(21 2–42 x+x 2)
−x 2=189−441+42 x−x 2−x 2=189−441+42 x−x 2
42 x=441−189=252 42 x=441−189=252
x=6
As 6, 8, and 10 is a variation of the well known right triangle, we can deduct that h=8 h=8 without actually using Pythagoras to compute it.
If we contruct the triangle in Geogebra, we get a confirmation that this is actually so.
Addition
I’d like to add to the above. We notice that the right triangle has the sides 8, 15 and 17. We, therefore, have two of many triplets making up a right triangle. The most well known is (3, 4, 5), but (5, 12, 13) is another that is almost as well known.
We might wonder if there is a limited number of such triplets, or if the number is infinite. The answer is that it is infinite, and it is actually easy to find such triplets by the formula below. (There may be other triplets not covered by this forumula, by the way.)
Take 2 natural numbers a and b, where a>b and one of them is even, the other is odd, and where they have no factor in common. (They could, of course, but then we can simplify the triplet.)
Sides in a right triangle on the form
s 1=2 a b,s 2=a 2−b 2,s 3=a 2+b 2 s 1=2 a b,s 2=a 2−b 2,s 3=a 2+b 2 (s 3 s 3 is the hypotenuse, by the way, since it is the longest).
We then note that
s 2 1+s 2 2=4 a 2 b 2+(a 2−b 2)2 s 1 2+s 2 2=4 a 2 b 2+(a 2−b 2)2
=4(a b)2+(a 4–2(a b)2+b 4)=4(a b)2+(a 4–2(a b)2+b 4)
=a 4+2(a b)2+b 4=a 4+2(a b)2+b 4
=(a 2+b 2)2=(a 2+b 2)2
=s 2 3=s 3 2
Which means the sides fulfill Pythagoras.
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Doctor Sachidanand Das
Ph.D.(Physics 1981), Polymath, World Teacher,38 yrs in Govt · Author has 11.3K answers and 16M answer views
·Updated 7y
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What is the formula for calculating altitude of a triangle?
The altitude or height of a triangle is the perpendicular drawn from any vertex of the triangle to the opposite side or its extension. The side to which the perpendicular is drawn is then called the base of the triangle. The three altitudes of a triangle always meet in one point called the orthocentre. In an acute-angle triangle, all three altitudes lie within the triangle.
Consider a triangle with
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The altitude or height of a triangle is the perpendicular drawn from any vertex of the triangle to the opposite side or its extension. The side to which the perpendicular is drawn is then called the base of the triangle. The three altitudes of a triangle always meet in one point called the orthocentre. In an acute-angle triangle, all three altitudes lie within the triangle.
Consider a triangle with vertices A,B and C. Let us drop an altitude from A onto the opposite side a. If we denote this altitude by h(a), it can be expressed by the following formula
h(a) = 2 {[s(s-a)(s-b)(s-c)]^1/2}/a
where a, b and c are the lengths of three sides of the triangle and 2s = a + b+ c is the perimeter of...
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12595 | https://www.ohioelectronicstextbook.org/ide-dc-9-basic_dc_circuit_analysis.html | Chapter 9: Basic DC Circuit Analysis
Version 1.00
Table of Contents
1. What is Network Analysis?
2. Branch Current Method
3. Mesh Current Methods
3.1. Conventional Method
3.2. Inspection Method
4. Node Voltage Method
5. Introduction to Network Theorems
5.1. Millman’s Theorem
5.2. Superposition Theorem
5.2.1. Additional Example Problems
5.3. Thevenin’s Theorem
5.3.1. Additional Example Problems
5.4. Norton’s Theorem
5.4.1. Additional Example Problems
5.5. Thevenin-Norton Equivalencies
5.6. Millman’s Theorem Revisited
5.7. Maximum Power Transfer Theorem
5.7.1. Additional Example Problems
6. Δ-Y and Y-Δ Conversions
6.1. Additional Example Problems
7. Bibliography
1. What is Network Analysis?
Generally speaking, network analysis is any structured technique used to mathematically analyze a circuit (a "network" of interconnected components). Quite often the technician or engineer will encounter circuits containing multiple sources of power or component configurations which defy simplification by series/parallel analysis techniques. In those cases, he or she will be forced to use other means. This chapter presents a few techniques useful in analyzing such complex circuits.
To illustrate how even a simple circuit can defy analysis by breakdown into series and parallel portions, take start with this series-parallel circuit:
To analyze the above circuit, one would first find the equivalent of R2 and R3 in parallel, then add R1 in series to arrive at a total resistance. Then, taking the voltage of battery B1 with that total circuit resistance, the total current could be calculated through the use of Ohm’s law (I=E/R), then that current figure used to calculate voltage drops in the circuit. All in all, a fairly simple procedure.
However, the addition of just one more battery could change all of that:
Resistors R2 and R3 are no longer in parallel with each other, because B2 has been inserted into R3's branch of the circuit. Upon closer inspection, it appears there are no two resistors in this circuit directly in series or parallel with each other. This is the crux of our problem: in series-parallel analysis, we started off by identifying sets of resistors that were directly in series or parallel with each other, reducing them to single equivalent resistances. If there are no resistors in a simple series or parallel configuration with each other, then what can we do?
It should be clear that this seemingly simple circuit, with only three resistors, is impossible to reduce as a combination of simple series and simple parallel sections: it is something different altogether. However, this is not the only type of circuit defying series/parallel analysis:
Here we have a bridge circuit, and for the sake of example we will suppose that it is not balanced (ratio R1/R4 not equal to ratio R2/R5). If it were balanced, there would be zero current through R3, and it could be approached as a series/parallel combination circuit (R1--R4 // R2--R5). However, any current through R3 makes a series/parallel analysis impossible. R1 is not in series with R4 because there’s another path for electrons to flow through R3. Neither is R2 in series with R5 for the same reason. Likewise, R1 is not in parallel with R2 because R3 is separating their bottom leads. Neither is R4 in parallel with R5. Aaarrggghhhh!
Although it might not be apparent at this point, the heart of the problem is the existence of multiple unknown quantities. At least in a series/parallel combination circuit, there was a way to find total resistance and total voltage, leaving total current as a single unknown value to calculate (and then that current was used to satisfy previously unknown variables in the reduction process until the entire circuit could be analyzed). With these problems, more than one parameter (variable) is unknown at the most basic level of circuit simplification.
With the two-battery circuit, there is no way to arrive at a value for "total resistance," because there are two sources of power to provide voltage and current (we would need two "total" resistances in order to proceed with any Ohm’s law calculations). With the unbalanced bridge circuit, there is such a thing as total resistance across the one battery (paving the way for a calculation of total current), but that total current immediately splits up into unknown proportions at each end of the bridge, so no further Ohm’s law calculations for voltage (E=IR) can be carried out.
So what can we do when we’re faced with multiple unknowns in a circuit? The answer is initially found in a mathematical process known as simultaneous equations or systems of equations, whereby multiple unknown variables are solved by relating them to each other in multiple equations. In a scenario with only one unknown (such as every Ohm’s law equation we’ve dealt with thus far), there only needs to be a single equation to solve for the single unknown:
However, when we’re solving for multiple unknown values, we need to have the same number of equations as we have unknowns in order to reach a solution. There are several methods of solving simultaneous equations, all rather intimidating and all too complex for explanation in this chapter. However, many scientific and programmable calculators are able to solve for simultaneous unknowns, so it is recommended to use such a calculator when first learning how to analyze these circuits.
This is not as scary as it may seem at first. Trust me!
Later on we’ll see that some clever people have found tricks to avoid having to use simultaneous equations on these types of circuits. We call these tricks network theorems, and we will explore a few later in this chapter.
Some circuit configurations ("networks") cannot be solved by reduction according to series/parallel circuit rules, due to multiple unknown values.
Mathematical techniques to solve for multiple unknowns (called "simultaneous equations" or "systems") can be applied to basic Laws of circuits to solve networks.
2. Branch Current Method
The first and most straightforward network analysis technique is called the Branch Current Method. In this method, we assume directions of currents in a network, then write equations describing their relationships to each other through Kirchhoff’s and Ohm’s laws. Once we have one equation for every unknown current, we can solve the simultaneous equations and determine all currents, and therefore all voltage drops in the network.
Let’s use this circuit to illustrate the method:
The first step is to choose a node (junction of wires) in the circuit to use as a point of reference for our unknown currents. I’ll choose the node joining the right of R1, the top of R2, and the left of R3.
At this node, guess which directions the three wires' currents take, labeling the three currents as I1, I2, and I3, respectively. Bear in mind that these directions of current are speculative at this point. Fortunately, if it turns out that any of our guesses were wrong, we will know when we mathematically solve for the currents (any "wrong" current directions will show up as negative numbers in our solution).
Kirchhoff’s Current Law (KCL) tells us that the algebraic sum of currents entering and exiting a node must equal zero, so we can relate these three currents (I1, I2, and I3) to each other in a single equation. For the sake of convention, I’ll denote any current entering the node as positive in sign, and any current exiting the node as negative in sign:
The next step is to label all voltage drop polarities across resistors according to the assumed directions of the currents. Remember that the "upstream" end of a resistor will always be negative, and the "downstream" end of a resistor positive with respect to each other, since electrons are negatively charged:
The battery polarities, of course, remain as they were according to their symbology (short end negative, long end positive). It is OK if the polarity of a resistor’s voltage drop doesn’t match with the polarity of the nearest battery, so long as the resistor voltage polarity is correctly based on the assumed direction of current through it. In some cases we may discover that current will be forced backwards through a battery, causing this very effect. The important thing to remember here is to base all your resistor polarities and subsequent calculations on the directions of current(s) initially assumed. As stated earlier, if your assumption happens to be incorrect, it will be apparent once the equations have been solved (by means of a negative solution). The magnitude of the solution, however, will still be correct.
Kirchhoff’s Voltage Law (KVL) tells us that the algebraic sum of all voltages in a loop must equal zero, so we can create more equations with current terms (I1, I2, and I3) for our simultaneous equations. To obtain a KVL equation, we must tally voltage drops in a loop of the circuit, as though we were measuring with a real voltmeter. I’ll choose to trace the left loop of this circuit first, starting from the upper-left corner and moving counter-clockwise (the choice of starting points and directions is arbitrary). The result will look like this:
Having completed our trace of the left loop, we add these voltage indications together for a sum of zero:
Of course, we don’t yet know what the voltage is across R1 or R2, so we can’t insert those values into the equation as numerical figures at this point. However, we do know that all three voltages must algebraically add to zero, so the equation is true. We can go a step further and express the unknown voltages as the product of the corresponding unknown currents (I1 and I2) and their respective resistors, following Ohm’s law (E=IR), as well as eliminate the 0 term:
Since we know what the values of all the resistors are in ohms, we can just substitute those figures into the equation to simplify things a bit:
You might be wondering why we went through all the trouble of manipulating this equation from its initial form (-28 + ER2 + ER1). After all, the last two terms are still unknown, so what advantage is there to expressing them in terms of unknown voltages or as unknown currents (multiplied by resistances)? The purpose in doing this is to get the KVL equation expressed using the same unknown variables as the KCL equation, for this is a necessary requirement for any simultaneous equation solution method. To solve for three unknown currents (I1, I2, and I3), we must have three equations relating these three currents (not voltages!) together.
Applying the same steps to the right loop of the circuit (starting at the chosen node and moving counter-clockwise), we get another KVL equation:
Knowing now that the voltage across each resistor can be and should be expressed as the product of the corresponding current and the (known) resistance of each resistor, we can rewrite the equation as such:
Now we have a mathematical system of three equations (one KCL equation and two KVL equations) and three unknowns:
For some methods of solution (especially any method involving a calculator), it is helpful to express each unknown term in each equation, with any constant value to the right of the equal sign, and with any "unity" terms expressed with an explicit coefficient of 1. Re-writing the equations again, we have:
Using whatever solution techniques are available to us, we should arrive at a solution for the three unknown current values:
So, I1 is 5 amps, I2 is 4 amps, and I3 is a negative 1 amp. But what does "negative" current mean? In this case, it means that our assumed direction for I3 was opposite of its real direction. Going back to our original circuit, we can redraw the current arrow for I3 (and redraw the polarity of R3's voltage drop to match):
Notice how current is being pushed backwards through battery 2 (electrons flowing "up") due to the higher voltage of battery 1 (whose current is pointed "down" as it normally would)! Despite the fact that battery B2's polarity is trying to push electrons down in that branch of the circuit, electrons are being forced backwards through it due to the superior voltage of battery B1. Does this mean that the stronger battery will always "win" and the weaker battery always get current forced through it backwards? No! It actually depends on both the batteries' relative voltages and the resistor values in the circuit. The only sure way to determine what’s going on is to take the time to mathematically analyze the network.
Now that we know the magnitude of all currents in this circuit, we can calculate voltage drops across all resistors with Ohm’s law (E=IR):
Let us now analyze this network using SPICE to verify our voltage figures.[spi] We could analyze current as well with SPICE, but since that requires the insertion of extra components into the circuit, and because we know that if the voltages are all the same and all the resistances are the same, the currents must all be the same, I’ll opt for the less complex analysis. Here’s a redrawing of our circuit, complete with node numbers for SPICE to reference:
network analysis example v1 1 0 v2 3 0 dc 7 r1 1 2 4 r2 2 0 2 r3 2 3 1 .dc v1 28 28 1 .print dc v(1,2) v(2,0) v(2,3) .end
v1 v(1,2) v(2) v(2,3) 2.800E+01 2.000E+01 8.000E+00 1.000E+00
Sure enough, the voltage figures all turn out to be the same: 20 volts across R1 (nodes 1 and 2), 8 volts across R2 (nodes 2 and 0), and 1 volt across R3 (nodes 2 and 3). Take note of the signs of all these voltage figures: they’re all positive values! SPICE bases its polarities on the order in which nodes are listed, the first node being positive and the second node negative. For example, a figure of positive (+) 20 volts between nodes 1 and 2 means that node 1 is positive with respect to node 2. If the figure had come out negative in the SPICE analysis, we would have known that our actual polarity was "backwards" (node 1 negative with respect to node 2). Checking the node orders in the SPICE listing, we can see that the polarities all match what we determined through the Branch Current method of analysis.
REVIEW
Steps to follow for the "Branch Current" method of analysis:
(1) Choose a node and assume directions of currents.
(2) Write a KCL equation relating currents at the node.
(3) Label resistor voltage drop polarities based on assumed currents.
(4) Write KVL equations for each loop of the circuit, substituting the product IR for E in each resistor term of the equations.
(5) Solve for unknown branch currents (simultaneous equations).
(6) If any solution is negative, then the assumed direction of current for that solution is wrong!
(7) Solve for voltage drops across all resistors (E=IR).
3. Mesh Current Methods
The Mesh Current Method, also known as the Loop Current Method, is quite similar to the Branch Current method in that it uses simultaneous equations, Kirchhoff’s Voltage Law, and Ohm’s law to determine unknown currents in a network. It differs from the Branch Current method in that it does not use Kirchhoff’s Current Law, and it is usually able to solve a circuit with less unknown variables and less simultaneous equations, which is especially nice if you’re forced to solve without a calculator.
3.1. Conventional Method
Let’s see how this method works on the same example problem:
The first step in the Mesh Current method is to identify "loops" within the circuit encompassing all components. In our example circuit, the loop formed by B1, R1, and R2 will be the first while the loop formed by B2, R2, and R3 will be the second. The strangest part of the Mesh Current method is envisioning circulating currents in each of the loops. In fact, this method gets its name from the idea of these currents meshing together between loops like sets of spinning gears:
The choice of each current’s direction is entirely arbitrary, just as in the Branch Current method, but the resulting equations are easier to solve if the currents are going the same direction through intersecting components (note how currents I1 and I2 are both going "up" through resistor R2, where they "mesh," or intersect). If the assumed direction of a mesh current is wrong, the answer for that current will have a negative value.
The next step is to label all voltage drop polarities across resistors according to the assumed directions of the mesh currents. Remember that the "upstream" end of a resistor will always be negative, and the "downstream" end of a resistor positive with respect to each other, since electrons are negatively charged. The battery polarities, of course, are dictated by their symbol orientations in the diagram, and may or may not "agree" with the resistor polarities (assumed current directions):
Using Kirchhoff’s Voltage Law, we can now step around each of these loops, generating equations representative of the component voltage drops and polarities. As with the Branch Current method, we will denote a resistor’s voltage drop as the product of the resistance (in ohms) and its respective mesh current (that quantity being unknown at this point). Where two currents mesh together, we will write that term in the equation with resistor current being the sum of the two meshing currents.
Tracing the left loop of the circuit, starting from the upper-left corner and moving counter-clockwise (the choice of starting points and directions is ultimately irrelevant), counting polarity as if we had a voltmeter in hand, red lead on the point ahead and black lead on the point behind, we get this equation:
Notice that the middle term of the equation uses the sum of mesh currents I1 and I2 as the current through resistor R2. This is because mesh currents I1 and I2 are going the same direction through R2, and thus complement each other. Distributing the coefficient of 2 to the I1 and I2 terms, and then combining I1 terms in the equation, we can simplify as such:
At this time we have one equation with two unknowns. To be able to solve for two unknown mesh currents, we must have two equations. If we trace the other loop of the circuit, we can obtain another KVL equation and have enough data to solve for the two currents. Creature of habit that I am, I’ll start at the upper-left hand corner of the right loop and trace counter-clockwise:
Simplifying the equation as before, we end up with:
Now, with two equations, we can use one of several methods to mathematically solve for the unknown currents I1 and I2:
Knowing that these solutions are values for mesh currents, not branch currents, we must go back to our diagram to see how they fit together to give currents through all components:
The solution of -1 amp for I2 means that our initially assumed direction of current was incorrect. In actuality, I2 is flowing in a counter-clockwise direction at a value of (positive) 1 amp:
This change of current direction from what was first assumed will alter the polarity of the voltage drops across R2 and R3 due to current I2. From here, we can say that the current through R1 is 5 amps, with the voltage drop across R1 being the product of current and resistance (E=IR), 20 volts (positive on the left and negative on the right). Also, we can safely say that the current through R3 is 1 amp, with a voltage drop of 1 volt (E=IR), positive on the left and negative on the right. But what is happening at R2?
Mesh current I1 is going "up" through R2, while mesh current I2 is going "down" through R2. To determine the actual current through R2, we must see how mesh currents I1 and I2 interact (in this case they’re in opposition), and algebraically add them to arrive at a final value. Since I1 is going "up" at 5 amps, and I2 is going "down" at 1 amp, the real current through R2 must be a value of 4 amps, going "up:"
A current of 4 amps through R2's resistance of 2 Ω gives us a voltage drop of 8 volts (E=IR), positive on the top and negative on the bottom.
The primary advantage of Mesh Current analysis is that it generally allows for the solution of a large network with fewer unknown values and fewer simultaneous equations. Our example problem took three equations to solve the Branch Current method and only two equations using the Mesh Current method. This advantage is much greater as networks increase in complexity:
To solve this network using Branch Currents, we’d have to establish five variables to account for each and every unique current in the circuit (I1 through I5). This would require five equations for solution, in the form of two KCL equations and three KVL equations (two equations for KCL at the nodes, and three equations for KVL in each loop):
I suppose if you have nothing better to do with your time than to solve for five unknown variables with five equations, you might not mind using the Branch Current method of analysis for this circuit. For those of us who have better things to do with our time, the Mesh Current method is a whole lot easier, requiring only three unknowns and three equations to solve:
Less equations to work with is a decided advantage, especially when performing simultaneous equation solution by hand (without a calculator).
Another type of circuit that lends itself well to Mesh Current is the unbalanced Wheatstone Bridge. Take this circuit, for example:
Since the ratios of R1/R4 and R2/R5 are unequal, we know that there will be voltage across resistor R3, and some amount of current through it. As discussed at the beginning of this chapter, this type of circuit is irreducible by normal series-parallel analysis, and may only be analyzed by some other method.
We could apply the Branch Current method to this circuit, but it would require six currents (I1 through I6), leading to a very large set of simultaneous equations to solve. Using the Mesh Current method, though, we may solve for all currents and voltages with much fewer variables.
The first step in the Mesh Current method is to draw just enough mesh currents to account for all components in the circuit. Looking at our bridge circuit, it should be obvious where to place two of these currents:
The directions of these mesh currents, of course, is arbitrary. However, two mesh currents is not enough in this circuit, because neither I1 nor I2 goes through the battery. So, we must add a third mesh current, I3:
Here, I have chosen I3 to loop from the bottom side of the battery, through R4, through R1, and back to the top side of the battery. This is not the only path I could have chosen for I3, but it seems the simplest.
Now, we must label the resistor voltage drop polarities, following each of the assumed currents' directions:
Notice something very important here: at resistor R4, the polarities for the respective mesh currents do not agree. This is because those mesh currents (I2 and I3) are going through R4 in different directions. This does not preclude the use of the Mesh Current method of analysis, but it does complicate it a bit. Though later, we will show how to avoid the R4 current clash. (See Example below)
Generating a KVL equation for the top loop of the bridge, starting from the top node and tracing in a clockwise direction:
In this equation, we represent the common directions of currents by their sums through common resistors. For example, resistor R3, with a value of 100 Ω, has its voltage drop represented in the above KVL equation by the expression 100(I1 + I2), since both currents I1 and I2 go through R3 from right to left. The same may be said for resistor R1, with its voltage drop expression shown as 150(I1 I3), since both I1 and I3 go from bottom to top through that resistor, and thus work together to generate its voltage drop.
Generating a KVL equation for the bottom loop of the bridge will not be so easy, since we have two currents going against each other through resistor R4. Here is how I do it (starting at the right-hand node, and tracing counter-clockwise):
Note how the second term in the equation’s original form has resistor R4's value of 300 Ω multiplied by the difference between I2 and I3 (I2 - I3). This is how we represent the combined effect of two mesh currents going in opposite directions through the same component. Choosing the appropriate mathematical signs is very important here: 300(I2 - I3) does not mean the same thing as 300(I3 - I2). I chose to write 300(I2 - I3) because I was thinking first of I2's effect (creating a positive voltage drop, measuring with an imaginary voltmeter across R4, red lead on the bottom and black lead on the top), and secondarily of I3's effect (creating a negative voltage drop, red lead on the bottom and black lead on the top). If I had thought in terms of I3's effect first and I2's effect secondarily, holding my imaginary voltmeter leads in the same positions (red on bottom and black on top), the expression would have been -300(I3 - I2). Note that this expression is mathematically equivalent to the first one: +300(I2 - I3).
Well, that takes care of two equations, but I still need a third equation to complete my simultaneous equation set of three variables, three equations. This third equation must also include the battery’s voltage, which up to this point does not appear in either two of the previous KVL equations. To generate this equation, I will trace a loop again with my imaginary voltmeter starting from the battery’s bottom (negative) terminal, stepping clockwise (again, the direction in which I step is arbitrary, and does not need to be the same as the direction of the mesh current in that loop):
Solving for I1, I2, and I3 using whatever simultaneous equation method we prefer:
Example:
Use Octave to find the solution for I1, I2, and I3 from the above simplified form of equations. [octav]
Solution:
In Octave, an open source Matlab® clone, enter the coefficients into the A matrix between square brackets with column elements comma separated, and rows semicolon separated.[octav] Enter the voltages into the column vector: b. The unknown currents: I1, I2, and I3 are calculated by the command: x=A\b. These are contained within the x column vector.
octave:1>A = [300,100,150;100,650,-300;-150,300,-450] A = 300 100 150 100 650 -300 -150 300 -450 octave:2> b = [0;0;-24] b = 0 0 -24 octave:3> x = A\b x = -0.093793 0.077241 0.136092
The negative value arrived at for I1 tells us that the assumed direction for that mesh current was incorrect. Thus, the actual current values through each resistor is as such:
Calculating voltage drops across each resistor:
A SPICE simulation confirms the accuracy of our voltage calculations:[spi]
unbalanced wheatstone bridge v1 1 0 r1 1 2 150 r2 1 3 50 r3 2 3 100 r4 2 0 300 r5 3 0 250 .dc v1 24 24 1 .print dc v(1,2) v(1,3) v(3,2) v(2,0) v(3,0) .end
v1 v(1,2) v(1,3) v(3,2) v(2) v(3) 2.400E+01 6.345E+00 4.690E+00 1.655E+00 1.766E+01 1.931E+01
Example:
(a) Find a new path for current I3 that does not produce a conflicting polarity on any resistor compared to I1 or I2. R4 was the offending component. (b) Find values for I1, I2, and I3. (c) Find the five resistor currents and compare to the previous values.
Solution: [dvn]
(a) Route I3 through R5, R3 and R1 as shown:
Note that the conflicting polarity on R4 has been removed. Moreover, none of the other resistors have conflicting polarities.
(b) Octave, an open source (free) matlab clone, yields a mesh current vector at "x":[octav]
octave:1> A = [300,100,250;100,650,350;-250,-350,-500] A = 300 100 250 100 650 350 -250 -350 -500 octave:2> b = [0;0;-24] b = 0 0 -24 octave:3> x = A\b x = -0.093793 -0.058851 0.136092
Not all currents I1, I2, and I3 are the same (I2) as the previous bridge because of different loop paths However, the resistor currents compare to the previous values:
IR1 = I1 + I3 = -93.793 ma + 136.092 ma = 42.299 ma IR2 = I1 = -93.793 ma IR3 = I1 + I2 + I3 = -93.793 ma -58.851 ma + 136.092 ma = -16.552 ma IR4 = I2 = -58.851 ma IR5 = I2 + I3 = -58.851 ma + 136.092 ma = 77.241 ma
Since the resistor currents are the same as the previous values, the resistor voltages will be identical and need not be calculated again.
REVIEW
Steps to follow for the "Mesh Current" method of analysis:
(1) Draw mesh currents in loops of circuit, enough to account for all components.
(2) Label resistor voltage drop polarities based on assumed directions of mesh currents.
(3) Write KVL equations for each loop of the circuit, substituting the product IR for E in each resistor term of the equation. Where two mesh currents intersect through a component, express the current as the algebraic sum of those two mesh currents (i.e. I1 + I2) if the currents go in the same direction through that component. If not, express the current as the difference (i.e. I1 - I2).
(4) Solve for unknown mesh currents (simultaneous equations).
(5) If any solution is negative, then the assumed current direction is wrong!
(6) Algebraically add mesh currents to find current in components sharing multiple mesh currents.
(7) Solve for voltage drops across all resistors (E=IR).
3.2. Inspection Method
We take a second look at the "mesh current method" with all the currents running counterclockwise (ccw). The motivation is to simplify the writing of mesh equations by ignoring the resistor voltage drop polarity. Though, we must pay attention to the polarity of voltage sources with respect to assumed current direction. The sign of the resistor voltage drops will follow a fixed pattern.
If we write a set of conventional mesh current equations for the circuit below, where we do pay attention to the signs of the voltage drop across the resistors, we may rearrange the coefficients into a fixed pattern:
Once rearranged, we may write equations by inspection. The signs of the coefficients follow a fixed pattern in the pair above, or the set of three in the rules below.
Mesh current rules:
This method assumes electron flow (not conventional current flow) voltage sources. Replace any current source in parallel with a resistor with an equivalent voltage source in series with an equivalent resistance.
Ignoring current direction or voltage polarity on resistors, draw counterclockwise current loops traversing all components. Avoid nested loops.
Write voltage-law equations in terms of unknown currents currents: I1, I2, and I3. Equation 1 coefficient 1, equation 2, coefficient 2, and equation 3 coefficient 3 are the positive sums of resistors around the respective loops.
All other coefficients are negative, representative of the resistance common to a pair of loops. Equation 1 coefficient 2 is the resistor common to loops 1 and 2, coefficient 3 the resistor common to loops 1 an 3. Repeat for other equations and coefficients.
The right hand side of the equations is equal to any electron current flow voltage source. A voltage rise with respect to the counterclockwise assumed current is positive, and 0 for no voltage source.
Solve equations for mesh currents:I1, I2, and I3 . Solve for currents through individual resistors with KCL. Solve for voltages with Ohms Law and KVL.
While the above rules are specific for a three mesh circuit, the rules may be extended to smaller or larger meshes. The figure below illustrates the application of the rules. The three currents are all drawn in the same direction, counterclockwise. One KVL equation is written for each of the three loops. Note that there is no polarity drawn on the resistors. We do not need it to determine the signs of the coefficients. Though we do need to pay attention to the polarity of the voltage source with respect to current direction. The I3counterclockwise current traverses the 24V source from (+) to (-). This is a voltage rise for electron current flow. Therefore, the third equation right hand side is +24V.
In Octave, enter the coefficients into the A matrix with column elements comma separated, and rows semicolon separated. Enter the voltages into the column vector b. Solve for the unknown currents: I1, I2, and I3 with the command: x=A\b. These currents are contained within the x column vector. The positive values indicate that the three mesh currents all flow in the assumed counterclockwise direction.
octave:2> A=[300,-100,-150;-100,650,-300;-150,-300,450] A = 300 -100 -150 -100 650 -300 -150 -300 450 octave:3> b=[0;0;24] b = 0 0 24 octave:4> x=A\b x = 0.093793 0.077241 0.136092
The mesh currents match the previous solution by a different mesh current method.. The calculation of resistor voltages and currents will be identical to the previous solution. No need to repeat here.
Note that electrical engineering texts are based on conventional current flow. The loop-current, mesh-current method in those text will run the assumed mesh currents clockwise.[aef] The conventional current flows out the (+) terminal of the battery through the circuit, returning to the (-) terminal. A conventional current voltage rise corresponds to tracing the assumed current from (-) to (+) through any voltage sources.
One more example of a previous circuit follows. The resistance around loop 1 is 6 Ω, around loop 2: 3 Ω. The resistance common to both loops is 2 Ω. Note the coefficients of I1 and I2 in the pair of equations. Tracing the assumed counterclockwise loop 1 current through B1 from (+) to (-) corresponds to an electron current flow voltage rise. Thus, the sign of the 28 V is positive. The loop 2 counter clockwise assumed current traces (-) to (+) through B2, a voltage drop. Thus, the sign of B2 is negative, -7 in the 2nd mesh equation. Once again, there are no polarity markings on the resistors. Nor do they figure into the equations.
The currents I1 = 5 A, and I2 = 1 A are both positive. They both flow in the direction of the counterclockwise loops. This compares with previous results.
Summary:
The modified mesh-current method avoids having to determine the signs of the equation coefficients by drawing all mesh currents counterclockwise for electron current flow.
However, we do need to determine the sign of any voltage sources in the loop. The voltage source is positive if the assumed ccw current flows with the battery (source). The sign is negative if the assumed ccw current flows against the battery.
See rules above for details.
4. Node Voltage Method
The node voltage method of analysis solves for unknown voltages at circuit nodes in terms of a system of KCL equations. This analysis looks strange because it involves replacing voltage sources with equivalent current sources. Also, resistor values in ohms are replaced by equivalent conductances in siemens, G = 1/R. The siemens (S) is the unit of conductance, having replaced the mho unit. In any event S = Ω-1. And S = mho (obsolete).
We start with a circuit having conventional voltage sources. A common node E0 is chosen as a reference point. The node voltages E1 and E2 are calculated with respect to this point.
A voltage source in series with a resistance must be replaced by an equivalent current source in parallel with the resistance. We will write KCL equations for each node. The right hand side of the equation is the value of the current source feeding the node.
Replacing voltage sources and associated series resistors with equivalent current sources and parallel resistors yields the modified circuit. Substitute resistor conductances in siemens for resistance in ohms.
I1 = E1/R1 = 10/2 = 5 A I2 = E2/R5 = 4/1 = 4 A G1 = 1/R1 = 1/2 Ω = 0.5 S G2 = 1/R2 = 1/4 Ω = 0.25 S G3 = 1/R3 = 1/2.5 Ω = 0.4 S G4 = 1/R4 = 1/5 Ω = 0.2 S G5 = 1/R5 = 1/1 Ω = 1.0 S
The Parallel conductances (resistors) may be combined by addition of the conductances. Though, we will not redraw the circuit. The circuit is ready for application of the node voltage method.
GA = G1 + G2 = 0.5 S + 0.25 S = 0.75 S GB = G4 + G5 = 0.2 S + 1 S = 1.2 S
Deriving a general node voltage method, we write a pair of KCL equations in terms of unknown node voltages V1 and V2 this one time. We do this to illustrate a pattern for writing equations by inspection.
GAE1 + G3(E1 - E2) = I1 (1) GBE2 - G3(E1 - E2) = I2 (2) (GA + G3 )E1 -G3E2 = I1 (1) -G3E1 + (GB + G3)E2 = I2 (2)
The coefficients of the last pair of equations above have been rearranged to show a pattern. The sum of conductances connected to the first node is the positive coefficient of the first voltage in equation (1). The sum of conductances connected to the second node is the positive coefficient of the second voltage in equation (2). The other coefficients are negative, representing conductances between nodes. For both equations, the right hand side is equal to the respective current source connected to the node. This pattern allows us to quickly write the equations by inspection. This leads to a set of rules for the node voltage method of analysis.
Node voltage rules:
Convert voltage sources in series with a resistor to an equivalent current source with the resistor in parallel.
Change resistor values to conductances.
Select a reference node(E0)
Assign unknown voltages (E1)(E2) … (EN)to remaining nodes.
Write a KCL equation for each node 1,2, … N. The positive coefficient of the first voltage in the first equation is the sum of conductances connected to the node. The coefficient for the second voltage in the second equation is the sum of conductances connected to that node. Repeat for coefficient of third voltage, third equation, and other equations. These coefficients fall on a diagonal.
All other coefficients for all equations are negative, representing conductances between nodes. The first equation, second coefficient is the conductance from node 1 to node 2, the third coefficient is the conductance from node 1 to node 3. Fill in negative coefficients for other equations.
The right hand side of the equations is the current source connected to the respective nodes.
Solve system of equations for unknown node voltages.
Example: Set up the equations and solve for the node voltages using the numerical values in the above figure.
Solution:
(0.5+0.25+0.4)E1 -(0.4)E2 = 5 -(0.4)E1 +(0.4+0.2+1.0)E2 = -4 (1.15)E1 -(0.4)E2 = 5 -(0.4)E1 +(1.6)E2 = -4 E1 = 3.8095 E2 = -1.5476
The solution of two equations can be performed with a calculator, or with octave (not shown).[octav] The solution is verified with SPICE based on the original schematic diagram with voltage sources. [spi] Though, the circuit with the current sources could have been simulated.
V1 11 0 DC 10 V2 22 0 DC -4 r1 11 1 2 r2 1 0 4 r3 1 2 2.5 r4 2 0 5 r5 2 22 1 .DC V1 10 10 1 V2 -4 -4 1 .print DC V(1) V(2) .end v(1) v(2) 3.809524e+00 -1.547619e+00
One more example. This one has three nodes. We do not list the conductances on the schematic diagram. However, G1 = 1/R1, etc.
There are three nodes to write equations for by inspection. Note that the coefficients are positive for equation (1) E1, equation (2) E2, and equation (3) E3. These are the sums of all conductances connected to the nodes. All other coefficients are negative, representing a conductance between nodes. The right hand side of the equations is the associated current source, 0.136092 A for the only current source at node 1. The other equations are zero on the right hand side for lack of current sources. We are too lazy to calculate the conductances for the resistors on the diagram. Thus, the subscripted G’s are the coefficients.
(G1 + G2)E1 -G1E2 -G2E3 = 0.136092 -G1E1 +(G1 + G3 + G4)E2 -G3E3 = 0 -G2E1 -G3E2 +(G2 + G3 + G5)E3 = 0
We are so lazy that we enter reciprocal resistances and sums of reciprocal resistances into the octave "A" matrix, letting octave compute the matrix of conductances after "A=".[octav] The initial entry line was so long that it was split into three rows. This is different than previous examples. The entered "A" matrix is delineated by starting and ending square brackets. Column elements are space separated. Rows are "new line" separated. Commas and semicolons are not need as separators. Though, the current vector at "b" is semicolon separated to yield a column vector of currents.
octave:12> A = [1/150+1/50 -1/150 -1/50 > -1/150 1/150+1/100+1/300 -1/100 > -1/50 -1/100 1/50+1/100+1/250] A = 0.0266667 -0.0066667 -0.0200000 -0.0066667 0.0200000 -0.0100000 -0.0200000 -0.0100000 0.0340000 octave:13> b = [0.136092;0;0] b = 0.13609 0.00000 0.00000 octave:14> x=A\b x = 24.000 17.655 19.310
Note that the "A" matrix diagonal coefficients are positive, That all other coefficients are negative.
The solution as a voltage vector is at "x". E1 = 24.000 V, E2 = 17.655 V, E3 = 19.310 V. These three voltages compare to the previous mesh current and SPICE solutions to the unbalanced bridge problem. This is no coincidence, for the 0.13609 A current source was purposely chosen to yield the 24 V used as a voltage source in that problem.
Summary
Given a network of conductances and current sources, the node voltage method of circuit analysis solves for unknown node voltages from KCL equations.
See rules above for details in writing the equations by inspection.
The unit of conductance G is the siemens S. Conductance is the reciprocal of resistance: G = 1/R
5. Introduction to Network Theorems
Anyone who’s studied geometry should be familiar with the concept of a theorem: a relatively simple rule used to solve a problem, derived from a more intensive analysis using fundamental rules of mathematics. At least hypothetically, any problem in math can be solved just by using the simple rules of arithmetic (in fact, this is how modern digital computers carry out the most complex mathematical calculations: by repeating many cycles of additions and subtractions!), but human beings aren’t as consistent or as fast as a digital computer. We need "shortcut" methods in order to avoid procedural errors.
In electric network analysis, the fundamental rules are Ohm’s law and Kirchhoff’s Laws. While these humble laws may be applied to analyze just about any circuit configuration (even if we have to resort to complex algebra to handle multiple unknowns), there are some "shortcut" methods of analysis to make the math easier for the average human.
As with any theorem of geometry or algebra, these network theorems are derived from fundamental rules. In this chapter, I’m not going to delve into the formal proofs of any of these theorems. If you doubt their validity, you can always empirically test them by setting up example circuits and calculating values using the "old" (simultaneous equation) methods versus the "new" theorems, to see if the answers coincide. They always should!
5.1. Millman’s Theorem
In Millman’s Theorem, the circuit is redrawn as a parallel network of branches, each branch containing a resistor or series battery/resistor combination. Millman’s Theorem is applicable only to those circuits which can be redrawn accordingly. Here again is our example circuit used for the last two analysis methods:
And here is that same circuit, redrawn for the sake of applying Millman’s Theorem:
By considering the supply voltage within each branch and the resistance within each branch, Millman’s Theorem will tell us the voltage across all branches. Please note that I’ve labeled the battery in the rightmost branch as "B3" to clearly denote it as being in the third branch, even though there is no "B2" in the circuit!
Millman’s Theorem is nothing more than a long equation, applied to any circuit drawn as a set of parallel-connected branches, each branch with its own voltage source and series resistance:
Substituting actual voltage and resistance figures from our example circuit for the variable terms of this equation, we get the following expression:
The final answer of 8 volts is the voltage seen across all parallel branches, like this:
The polarity of all voltages in Millman’s Theorem are referenced to the same point. In the example circuit above, I used the bottom wire of the parallel circuit as my reference point, and so the voltages within each branch (28 for the R1 branch, 0 for the R2 branch, and 7 for the R3 branch) were inserted into the equation as positive numbers. Likewise, when the answer came out to 8 volts (positive), this meant that the top wire of the circuit was positive with respect to the bottom wire (the original point of reference). If both batteries had been connected backwards (negative ends up and positive ends down), the voltage for branch 1 would have been entered into the equation as a -28 volts, the voltage for branch 3 as -7 volts, and the resulting answer of -8 volts would have told us that the top wire was negative with respect to the bottom wire (our initial point of reference).
To solve for resistor voltage drops, the Millman voltage (across the parallel network) must be compared against the voltage source within each branch, using the principle of voltages adding in series to determine the magnitude and polarity of voltage across each resistor:
To solve for branch currents, each resistor voltage drop can be divided by its respective resistance (I=E/R):
The direction of current through each resistor is determined by the polarity across each resistor, not by the polarity across each battery, as current can be forced backwards through a battery, as is the case with B3 in the example circuit. This is important to keep in mind, since Millman’s Theorem doesn’t provide as direct an indication of "wrong" current direction as does the Branch Current or Mesh Current methods. You must pay close attention to the polarities of resistor voltage drops as given by Kirchhoff’s Voltage Law, determining direction of currents from that.
Millman’s Theorem is very convenient for determining the voltage across a set of parallel branches, where there are enough voltage sources present to preclude solution via regular series-parallel reduction method. It also is easy in the sense that it doesn’t require the use of simultaneous equations. However, it is limited in that it only applied to circuits which can be redrawn to fit this form. It cannot be used, for example, to solve an unbalanced bridge circuit. And, even in cases where Millman’s Theorem can be applied, the solution of individual resistor voltage drops can be a bit daunting to some, the Millman’s Theorem equation only providing a single figure for branch voltage.
As you will see, each network analysis method has its own advantages and disadvantages. Each method is a tool, and there is no tool that is perfect for all jobs. The skilled technician, however, carries these methods in his or her mind like a mechanic carries a set of tools in his or her tool box. The more tools you have equipped yourself with, the better prepared you will be for any eventuality.
REVIEW
Millman’s Theorem treats circuits as a parallel set of series-component branches.
All voltages entered and solved for in Millman’s Theorem are polarity-referenced at the same point in the circuit (typically the bottom wire of the parallel network).
5.2. Superposition Theorem
Superposition theorem is one of those strokes of genius that takes a complex subject and simplifies it in a way that makes perfect sense. A theorem like Millman’s certainly works well, but it is not quite obvious why it works so well. Superposition, on the other hand, is obvious.
The strategy used in the Superposition Theorem is to eliminate all but one source of power within a network at a time, using series/parallel analysis to determine voltage drops (and/or currents) within the modified network for each power source separately. Then, once voltage drops and/or currents have been determined for each power source working separately, the values are all "superimposed" on top of each other (added algebraically) to find the actual voltage drops/currents with all sources active. Let’s look at our example circuit again and apply Superposition Theorem to it:
Since we have two sources of power in this circuit, we will have to calculate two sets of values for voltage drops and/or currents, one for the circuit with only the 28 volt battery in effect. . .
. . and one for the circuit with only the 7 volt battery in effect:
When redrawing the circuit for series/parallel analysis with one source, all other voltage sources are replaced by wires (shorts), and all current sources with open circuits (breaks). Since we only have voltage sources (batteries) in our example circuit, we will replace every inactive source during analysis with a wire.
Analyzing the circuit with only the 28 volt battery, we obtain the following values for voltage and current:
Analyzing the circuit with only the 7 volt battery, we obtain another set of values for voltage and current:
When superimposing these values of voltage and current, we have to be very careful to consider polarity (voltage drop) and direction (electron flow), as the values have to be added algebraically.
Applying these superimposed voltage figures to the circuit, the end result looks something like this:
Currents add up algebraically as well, and can either be superimposed as done with the resistor voltage drops, or simply calculated from the final voltage drops and respective resistances (I=E/R). Either way, the answers will be the same. Here I will show the superposition method applied to current:
Once again applying these superimposed figures to our circuit:
Quite simple and elegant, don’t you think? It must be noted, though, that the Superposition Theorem works only for circuits that are reducible to series/parallel combinations for each of the power sources at a time (thus, this theorem is useless for analyzing an unbalanced bridge circuit), and it only works where the underlying equations are linear (no mathematical powers or roots). The requisite of linearity means that Superposition Theorem is only applicable for determining voltage and current, not power!!! Power dissipations, being nonlinear functions, do not algebraically add to an accurate total when only one source is considered at a time. The need for linearity also means this Theorem cannot be applied in circuits where the resistance of a component changes with voltage or current. Hence, networks containing components like lamps (incandescent or gas-discharge) or varistors could not be analyzed.
Another prerequisite for Superposition Theorem is that all components must be "bilateral," meaning that they behave the same with electrons flowing either direction through them. Resistors have no polarity-specific behavior, and so the circuits we’ve been studying so far all meet this criterion.
The Superposition Theorem finds use in the study of alternating current (AC) circuits, and semiconductor (amplifier) circuits, where sometimes AC is often mixed (superimposed) with DC. Because AC voltage and current equations (Ohm’s law) are linear just like DC, we can use Superposition to analyze the circuit with just the DC power source, then just the AC power source, combining the results to tell what will happen with both AC and DC sources in effect. For now, though, Superposition will suffice as a break from having to do simultaneous equations to analyze a circuit.
5.2.1. Additional Example Problems
Example: Superposition
REVIEW
The Superposition Theorem states that a circuit can be analyzed with only one source of power at a time, the corresponding component voltages and currents algebraically added to find out what they’ll do with all power sources in effect.
To negate all but one power source for analysis, replace any source of voltage (batteries) with a wire; replace any current source with an open (break).
5.3. Thevenin’s Theorem
Thevenin’s Theorem states that it is possible to simplify any linear circuit, no matter how complex, to an equivalent circuit with just a single voltage source and series resistance connected to a load. The qualification of "linear" is identical to that found in the Superposition Theorem, where all the underlying equations must be linear (no exponents or roots). If we’re dealing with passive components (such as resistors, and later, inductors and capacitors), this is true. However, there are some components (especially certain gas-discharge and semiconductor components) which are nonlinear: that is, their opposition to current changes with voltage and/or current. As such, we would call circuits containing these types of components, nonlinear circuits.
Thevenin’s Theorem is especially useful in analyzing power systems and other circuits where one particular resistor in the circuit (called the "load" resistor) is subject to change, and recalculation of the circuit is necessary with each trial value of load resistance, to determine voltage across it and current through it. Let’s take another look at our example circuit:
Let’s suppose that we decide to designate R2 as the "load" resistor in this circuit. We already have four methods of analysis at our disposal (Branch Current, Mesh Current, Millman’s Theorem, and Superposition Theorem) to use in determining voltage across R2 and current through R2, but each of these methods are time-consuming. Imagine repeating any of these methods over and over again to find what would happen if the load resistance changed (changing load resistance is very common in power systems, as multiple loads get switched on and off as needed. the total resistance of their parallel connections changing depending on how many are connected at a time). This could potentially involve a lot of work!
Thevenin’s Theorem makes this easy by temporarily removing the load resistance from the original circuit and reducing what’s left to an equivalent circuit composed of a single voltage source and series resistance. The load resistance can then be reconnected to this "Thevenin equivalent circuit" and calculations carried out as if the whole network were nothing but a simple series circuit:
. . after Thevenin conversion . . .
The "Thevenin Equivalent Circuit" is the electrical equivalent of B1, R1, R3, and B2 as seen from the two points where our load resistor (R2) connects.
The Thevenin equivalent circuit, if correctly derived, will behave exactly the same as the original circuit formed by B1, R1, R3, and B2. In other words, the load resistor (R2) voltage and current should be exactly the same for the same value of load resistance in the two circuits. The load resistor R2 cannot "tell the difference" between the original network of B1, R1, R3, and B2, and the Thevenin equivalent circuit of EThevenin, and RThevenin, provided that the values for EThevenin and RThevenin have been calculated correctly.
The advantage in performing the "Thevenin conversion" to the simpler circuit, of course, is that it makes load voltage and load current so much easier to solve than in the original network. Calculating the equivalent Thevenin source voltage and series resistance is actually quite easy. First, the chosen load resistor is removed from the original circuit, replaced with a break (open circuit):
Next, the voltage between the two points where the load resistor used to be attached is determined. Use whatever analysis methods are at your disposal to do this. In this case, the original circuit with the load resistor removed is nothing more than a simple series circuit with opposing batteries, and so we can determine the voltage across the open load terminals by applying the rules of series circuits, Ohm’s law, and Kirchhoff’s Voltage Law:
The voltage between the two load connection points can be figured from the one of the battery’s voltage and one of the resistor’s voltage drops, and comes out to 11.2 volts. This is our "Thevenin voltage" (EThevenin) in the equivalent circuit:
To find the Thevenin series resistance for our equivalent circuit, we need to take the original circuit (with the load resistor still removed), remove the power sources (in the same style as we did with the Superposition Theorem: voltage sources replaced with wires and current sources replaced with breaks), and figure the resistance from one load terminal to the other:
With the removal of the two batteries, the total resistance measured at this location is equal to R1 and R3 in parallel: 0.8 Ω. This is our "Thevenin resistance" (RThevenin) for the equivalent circuit:
With the load resistor (2 Ω) attached between the connection points, we can determine voltage across it and current through it as though the whole network were nothing more than a simple series circuit:
Notice that the voltage and current figures for R2 (8 volts, 4 amps) are identical to those found using other methods of analysis. Also notice that the voltage and current figures for the Thevenin series resistance and the Thevenin source (total) do not apply to any component in the original, complex circuit. Thevenin’s Theorem is only useful for determining what happens to a single resistor in a network: the load.
The advantage, of course, is that you can quickly determine what would happen to that single resistor if it were of a value other than 2 Ω without having to go through a lot of analysis again. Just plug in that other value for the load resistor into the Thevenin equivalent circuit and a little bit of series circuit calculation will give you the result.
5.3.1. Additional Example Problems
Example: Thevenin’s Theorem 1
Example: Thevenin’s Theorem 2
REVIEW
Thevenin’s Theorem is a way to reduce a network to an equivalent circuit composed of a single voltage source, series resistance, and series load.
Steps to follow for Thevenin’s Theorem:
(1) Find the Thevenin source voltage by removing the load resistor from the original circuit and calculating voltage across the open connection points where the load resistor used to be.
(2) Find the Thevenin resistance by removing all power sources in the original circuit (voltage sources shorted and current sources open) and calculating total resistance between the open connection points.
(3) Draw the Thevenin equivalent circuit, with the Thevenin voltage source in series with the Thevenin resistance. The load resistor reattaches between the two open points of the equivalent circuit.
(4) Analyze voltage and current for the load resistor following the rules for series circuits.
5.4. Norton’s Theorem
Norton’s Theorem states that it is possible to simplify any linear circuit, no matter how complex, to an equivalent circuit with just a single current source and parallel resistance connected to a load. Just as with Thevenin’s Theorem, the qualification of "linear" is identical to that found in the Superposition Theorem: all underlying equations must be linear (no exponents or roots).
Contrasting our original example circuit against the Norton equivalent: it looks something like this:
. . after Norton conversion . . .
Remember that a current source is a component whose job is to provide a constant amount of current, outputting as much or as little voltage necessary to maintain that constant current.
As with Thevenin’s Theorem, everything in the original circuit except the load resistance has been reduced to an equivalent circuit that is simpler to analyze. Also similar to Thevenin’s Theorem are the steps used in Norton’s Theorem to calculate the Norton source current (INorton) and Norton resistance (RNorton).
As before, the first step is to identify the load resistance and remove it from the original circuit:
Then, to find the Norton current (for the current source in the Norton equivalent circuit), place a direct wire (short) connection between the load points and determine the resultant current. Note that this step is exactly opposite the respective step in Thevenin’s Theorem, where we replaced the load resistor with a break (open circuit):
With zero voltage dropped between the load resistor connection points, the current through R1 is strictly a function of B1's voltage and R1's resistance: 7 amps (I=E/R). Likewise, the current through R3 is now strictly a function of B2's voltage and R3's resistance: 7 amps (I=E/R). The total current through the short between the load connection points is the sum of these two currents: 7 amps + 7 amps = 14 amps. This figure of 14 amps becomes the Norton source current (INorton) in our equivalent circuit:
Remember, the arrow notation for a current source points in the direction opposite that of electron flow. Again, apologies for the confusion. For better or for worse, this is standard electronic symbol notation. Blame Mr. Franklin again!
To calculate the Norton resistance (RNorton), we do the exact same thing as we did for calculating Thevenin resistance (RThevenin): take the original circuit (with the load resistor still removed), remove the power sources (in the same style as we did with the Superposition Theorem: voltage sources replaced with wires and current sources replaced with breaks), and figure total resistance from one load connection point to the other:
Now our Norton equivalent circuit looks like this:
If we reconnect our original load resistance of 2 Ω, we can analyze the Norton circuit as a simple parallel arrangement:
As with the Thevenin equivalent circuit, the only useful information from this analysis is the voltage and current values for R2; the rest of the information is irrelevant to the original circuit. However, the same advantages seen with Thevenin’s Theorem apply to Norton’s as well: if we wish to analyze load resistor voltage and current over several different values of load resistance, we can use the Norton equivalent circuit again and again, applying nothing more complex than simple parallel circuit analysis to determine what’s happening with each trial load.
5.4.1. Additional Example Problems
Example: Norton’s Theorem
REVIEW
Norton’s Theorem is a way to reduce a network to an equivalent circuit composed of a single current source, parallel resistance, and parallel load.
Steps to follow for Norton’s Theorem:
(1) Find the Norton source current by removing the load resistor from the original circuit and calculating current through a short (wire) jumping across the open connection points where the load resistor used to be.
(2) Find the Norton resistance by removing all power sources in the original circuit (voltage sources shorted and current sources open) and calculating total resistance between the open connection points.
(3) Draw the Norton equivalent circuit, with the Norton current source in parallel with the Norton resistance. The load resistor reattaches between the two open points of the equivalent circuit.
(4) Analyze voltage and current for the load resistor following the rules for parallel circuits.
5.5. Thevenin-Norton Equivalencies
Since Thevenin’s and Norton’s Theorems are two equally valid methods of reducing a complex network down to something simpler to analyze, there must be some way to convert a Thevenin equivalent circuit to a Norton equivalent circuit, and vice versa (just what you were dying to know, right?). Well, the procedure is very simple.
You may have noticed that the procedure for calculating Thevenin resistance is identical to the procedure for calculating Norton resistance: remove all power sources and determine resistance between the open load connection points. As such, Thevenin and Norton resistances for the same original network must be equal. Using the example circuits from the last two sections, we can see that the two resistances are indeed equal:
Considering the fact that both Thevenin and Norton equivalent circuits are intended to behave the same as the original network in supplying voltage and current to the load resistor (as seen from the perspective of the load connection points), these two equivalent circuits, having been derived from the same original network should behave identically.
This means that both Thevenin and Norton equivalent circuits should produce the same voltage across the load terminals with no load resistor attached. With the Thevenin equivalent, the open-circuited voltage would be equal to the Thevenin source voltage (no circuit current present to drop voltage across the series resistor), which is 11.2 volts in this case. With the Norton equivalent circuit, all 14 amps from the Norton current source would have to flow through the 0.8 Ω Norton resistance, producing the exact same voltage, 11.2 volts (E=IR). Thus, we can say that the Thevenin voltage is equal to the Norton current times the Norton resistance:
So, if we wanted to convert a Norton equivalent circuit to a Thevenin equivalent circuit, we could use the same resistance and calculate the Thevenin voltage with Ohm’s law.
Conversely, both Thevenin and Norton equivalent circuits should generate the same amount of current through a short circuit across the load terminals. With the Norton equivalent, the short-circuit current would be exactly equal to the Norton source current, which is 14 amps in this case. With the Thevenin equivalent, all 11.2 volts would be applied across the 0.8 Ω Thevenin resistance, producing the exact same current through the short, 14 amps (I=E/R). Thus, we can say that the Norton current is equal to the Thevenin voltage divided by the Thevenin resistance:
This equivalence between Thevenin and Norton circuits can be a useful tool in itself, as we shall see in the next section.
REVIEW
Thevenin and Norton resistances are equal.
Thevenin voltage is equal to Norton current times Norton resistance.
Norton current is equal to Thevenin voltage divided by Thevenin resistance.
5.6. Millman’s Theorem Revisited
You may have wondered where we got that strange equation for the determination of "Millman Voltage" across parallel branches of a circuit where each branch contains a series resistance and voltage source:
Parts of this equation seem familiar to equations we’ve seen before. For instance, the denominator of the large fraction looks conspicuously like the denominator of our parallel resistance equation. And, of course, the E/R terms in the numerator of the large fraction should give figures for current, Ohm’s law being what it is (I=E/R).
Now that we’ve covered Thevenin and Norton source equivalencies, we have the tools necessary to understand Millman’s equation. What Millman’s equation is actually doing is treating each branch (with its series voltage source and resistance) as a Thevenin equivalent circuit and then converting each one into equivalent Norton circuits.
Thus, in the circuit above, battery B1 and resistor R1 are seen as a Thevenin source to be converted into a Norton source of 7 amps (28 volts / 4 Ω) in parallel with a 4 Ω resistor. The rightmost branch will be converted into a 7 amp current source (7 volts / 1 Ω) and 1 Ω resistor in parallel. The center branch, containing no voltage source at all, will be converted into a Norton source of 0 amps in parallel with a 2 Ω resistor:
Since current sources directly add their respective currents in parallel, the total circuit current will be 7 + 0 + 7, or 14 amps. This addition of Norton source currents is what’s being represented in the numerator of the Millman equation:
All the Norton resistances are in parallel with each other as well in the equivalent circuit, so they diminish to create a total resistance. This diminishing of source resistances is what’s being represented in the denominator of the Millman’s equation:
In this case, the resistance total will be equal to 571.43 milliohms (571.43 mΩ). We can redraw our equivalent circuit now as one with a single Norton current source and Norton resistance:
Ohm’s law can tell us the voltage across these two components now (E=IR):
Let’s summarize what we know about the circuit thus far. We know that the total current in this circuit is given by the sum of all the branch voltages divided by their respective resistances. We also know that the total resistance is found by taking the reciprocal of all the branch resistance reciprocals. Furthermore, we should be well aware of the fact that total voltage across all the branches can be found by multiplying total current by total resistance (E=IR). All we need to do is put together the two equations we had earlier for total circuit current and total resistance, multiplying them to find total voltage:
The Millman’s equation is nothing more than a Thevenin-to-Norton conversion matched together with the parallel resistance formula to find total voltage across all the branches of the circuit. So, hopefully some of the mystery is gone now!
5.7. Maximum Power Transfer Theorem
The Maximum Power Transfer Theorem is not so much a means of analysis as it is an aid to system design. Simply stated, the maximum amount of power will be dissipated by a load resistance when that load resistance is equal to the Thevenin/Norton resistance of the network supplying the power. If the load resistance is lower or higher than the Thevenin/Norton resistance of the source network, its dissipated power will be less than maximum.
This is essentially what is aimed for in radio transmitter design , where the antenna or transmission line "impedance" is matched to final power amplifier "impedance" for maximum radio frequency power output. Impedance, the overall opposition to AC and DC current, is very similar to resistance, and must be equal between source and load for the greatest amount of power to be transferred to the load. A load impedance that is too high will result in low power output. A load impedance that is too low will not only result in low power output, but possibly overheating of the amplifier due to the power dissipated in its internal (Thevenin or Norton) impedance.
Taking our Thevenin equivalent example circuit, the Maximum Power Transfer Theorem tells us that the load resistance resulting in greatest power dissipation is equal in value to the Thevenin resistance (in this case, 0.8 Ω):
With this value of load resistance, the dissipated power will be 39.2 watts:
If we were to try a lower value for the load resistance (0.5 Ω instead of 0.8 Ω, for example), our power dissipated by the load resistance would decrease:
Power dissipation increased for both the Thevenin resistance and the total circuit, but it decreased for the load resistor. Likewise, if we increase the load resistance (1.1 Ω instead of 0.8 Ω, for example), power dissipation will also be less than it was at 0.8 Ω exactly:
If you were designing a circuit for maximum power dissipation at the load resistance, this theorem would be very useful. Having reduced a network down to a Thevenin voltage and resistance (or Norton current and resistance), you simply set the load resistance equal to that Thevenin or Norton equivalent (or vice versa) to ensure maximum power dissipation at the load. Practical applications of this might include radio transmitter final amplifier stage design (seeking to maximize power delivered to the antenna or transmission line), a grid tied inverter loading a solar array, or electric vehicle design (seeking to maximize power delivered to drive motor).
The Maximum Power Transfer Theorem is not: Maximum power transfer does not coincide with maximum efficiency. Application of The Maximum Power Transfer theorem to AC power distribution will not result in maximum or even high efficiency. The goal of high efficiency is more important for AC power distribution, which dictates a relatively low generator impedance compared to load impedance.
Similar to AC power distribution, high fidelity audio amplifiers are designed for a relatively low output impedance and a relatively high speaker load impedance. As a ratio, "output impdance" : "load impedance" is known as damping factor, typically in the range of 100 to 1000. [rar] [dfd]
Maximum power transfer does not coincide with the goal of lowest noise. For example, the low-level radio frequency amplifier between the antenna and a radio receiver is often designed for lowest possible noise. This often requires a mismatch of the amplifier input impedance to the antenna as compared with that dictated by the maximum power transfer theorem.
5.7.1. Additional Example Problems
Example: Calculate Maximum Possible Power Transfer
REVIEW
The Maximum Power Transfer Theorem states that the maximum amount of power will be dissipated by a load resistance if it is equal to the Thevenin or Norton resistance of the network supplying power.
The Maximum Power Transfer Theorem does not satisfy the goal of maximum efficiency.
6. Δ-Y and Y-Δ Conversions
In many circuit applications, we encounter components connected together in one of two ways to form a three-terminal network: the "Delta," or Δ (also known as the "Pi," or π) configuration, and the "Y" (also known as the "T") configuration.
It is possible to calculate the proper values of resistors necessary to form one kind of network (Δ or Y) that behaves identically to the other kind, as analyzed from the terminal connections alone. That is, if we had two separate resistor networks, one Δ and one Y, each with its resistors hidden from view, with nothing but the three terminals (A, B, and C) exposed for testing, the resistors could be sized for the two networks so that there would be no way to electrically determine one network apart from the other. In other words, equivalent Δ and Y networks behave identically.
There are several equations used to convert one network to the other:
Δ and Y networks are seen frequently in 3-phase AC power systems (a topic covered in volume II of this book series), but even then they’re usually balanced networks (all resistors equal in value) and conversion from one to the other need not involve such complex calculations. When would the average technician ever need to use these equations?
A prime application for Δ-Y conversion is in the solution of unbalanced bridge circuits, such as the one below:
Solution of this circuit with Branch Current or Mesh Current analysis is fairly involved, and neither the Millman nor Superposition Theorems are of any help, since there’s only one source of power. We could use Thevenin’s or Norton’s Theorem, treating R3 as our load, but what fun would that be?
If we were to treat resistors R1, R2, and R3 as being connected in a Δ configuration (Rab, Rac, and Rbc, respectively) and generate an equivalent Y network to replace them, we could turn this bridge circuit into a (simpler) series/parallel combination circuit:
After the Δ-Y conversion . . .
If we perform our calculations correctly, the voltages between points A, B, and C will be the same in the converted circuit as in the original circuit, and we can transfer those values back to the original bridge configuration.
Resistors R4 and R5, of course, remain the same at 18 Ω and 12 Ω, respectively. Analyzing the circuit now as a series/parallel combination, we arrive at the following figures:
We must use the voltage drops figures from the table above to determine the voltages between points A, B, and C, seeing how the add up (or subtract, as is the case with voltage between points B and C):
Now that we know these voltages, we can transfer them to the same points A, B, and C in the original bridge circuit:
Voltage drops across R4 and R5, of course, are exactly the same as they were in the converted circuit.
At this point, we could take these voltages and determine resistor currents through the repeated use of Ohm’s law (I=E/R):
A quick simulation with SPICE will serve to verify our work:[spi]
unbalanced bridge circuit v1 1 0 r1 1 2 12 r2 1 3 18 r3 2 3 6 r4 2 0 18 r5 3 0 12 .dc v1 10 10 1 .print dc v(1,2) v(1,3) v(2,3) v(2,0) v(3,0) .end
v1 v(1,2) v(1,3) v(2,3) v(2) v(3) 1.000E+01 4.706E+00 5.294E+00 5.882E-01 5.294E+00 4.706E+00
The voltage figures, as read from left to right, represent voltage drops across the five respective resistors, R1 through R5. I could have shown currents as well, but since that would have required insertion of "dummy" voltage sources in the SPICE netlist, and since we’re primarily interested in validating the Δ-Y conversion equations and not Ohm’s law, this will suffice.
6.1. Additional Example Problems
Example: Delta (Δ) to Wye (Y) Conversion
Example: Wye (Y) to Delta (Δ) Conversion
REVIEW
"Delta" (Δ) networks are also known as "Pi" (π) networks.
"Y" networks are also known as "T" networks.
Δ and Y networks can be converted to their equivalent counterparts with the proper resistance equations. By "equivalent," I mean that the two networks will be electrically identical as measured from the three terminals (A, B, and C).
A bridge circuit can be simplified to a series/parallel circuit by converting half of it from a Δ to a Y network. After voltage drops between the original three connection points (A, B, and C) have been solved for, those voltages can be transferred back to the original bridge circuit, across those same equivalent points.
7. Bibliography
[aef] A.E. Fitzergerald, David E. Higginbotham, Arvin Grabel, Basic Electrical Engineering, (McGraw-Hill, 1975).
[spi] Tony Kuphaldt,Using the Spice Circuit Simulation Program, in"Lessons in Electricity, Reference", Volume 5, Chapter 7, at
[dvn] Davy Van Nieuwenborgh, private communications, Theoretical Computer Science laboratory, Department of Computer Science, Vrije Universiteit Brussel (4/7/2004).
[octav] Octave, Matrix calculator open source program for Linux or MS Windows, at
[rar]Ray A. Rayburn , private communications, Senior Consultant K2 Audio, LLC; Fellow of the Audio Engineering Society, (6/29/2009).
[dfd]Damping Factor De-Mystified , at
Last updated 2023-09-06 11:03:45 -0400 |
12596 | https://www.vocabulary.com/dictionary/debilitate | SKIP TO CONTENT
IPA guide
Other forms: debilitating; debilitated; debilitates
To debilitate something is to make it weaker. A bad flu may debilitate your powers of concentration, like the New Year's resolutions that temporarily debilitate bakeries' business.
The verb debilitate traces back to the Latin word debilis, meaning lame, disabled, crippled. Its often used to describe what disability or illness does to a person's health, but it can describe anything that has been weakened, like the sense of community that is slowly debilitated by people working longer hours and the lack of sidewalks that in many towns make it harder to walk around and meet the neighbors.
Definitions of debilitate
verb
make weak
synonyms: drain, enfeeble
see moresee less
types:
emaciate, macerate, waste
cause to grow thin or weak
type of:
nerf, weaken
lessen the strength of
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Flag Day is June 14. At the end of a hot summer day, you can droop like Old Glory on a day without wind, and that feeling of fatigue is another meaning of the word "flag." On this Flag Day, here are eleven synonyms for that droopy, beginning-to-fade definition of "flag."
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12597 | https://www.quora.com/Is-there-a-function-that-satisfies-the-equation-f-a-b-f-a-f-b-If-not-why-is-it-not-possible-for-such-a-function-to-exist | Is there a function that satisfies the equation f(a^b) = f(a) f(b)? If not, why is it not possible for such a function to exist? - Quora
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Is there a function that satisfies the equation f(a^b) = f(a) f(b)? If not, why is it not possible for such a function to exist?
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David Anick
Ph.D. in Mathematics, Massachusetts Institute of Technology (Graduated 1980) · Author has 92 answers and 115.3K answer views
·1y
Question: Is there a function that satisfies the equation f(a^b) = f(a) f(b)? If not, why is it not possible for such a function to exist?
The expression a^b is not always defined (or is not always a well-defined real number) if a < 0, so I will assume the permitted domain for a and b here is the positive real numbers.
There is such a function, if we allow f(x) = 0 for all x or f(x) = 1 for all x. Then the equation simply says 0 = (0)(0) or 1 = (1)(1). Are these the only solutions?
What happens when a = 1? The equation would say f(1^b) = f(1)f(b) and since f(1^b)=f(1) we can divide both sides by
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Question: Is there a function that satisfies the equation f(a^b) = f(a) f(b)? If not, why is it not possible for such a function to exist?
The expression a^b is not always defined (or is not always a well-defined real number) if a < 0, so I will assume the permitted domain for a and b here is the positive real numbers.
There is such a function, if we allow f(x) = 0 for all x or f(x) = 1 for all x. Then the equation simply says 0 = (0)(0) or 1 = (1)(1). Are these the only solutions?
What happens when a = 1? The equation would say f(1^b) = f(1)f(b) and since f(1^b)=f(1) we can divide both sides by f(1) (unless f(1) = 0) to get f(b) = 1 for all b. We already have the case where f(b) = 1 for all b (we say f is “identically” equal to 1, written f ≡≡ 1), so this forces f(1) = 0. Knowing this, put b = 1 and obtain f(a) = f(a^1) = f(a)f(1) = 0 which makes f ≡≡ 0. So yes, f ≡≡ 1 and f ≡≡ 0 are the only solutions.
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Gabriele Scopel
Bachelors Degree in Mathematics, Tor Vergata University of Rome (Graduated 2025) · Author has 628 answers and 185.5K answer views
·1y
If f(a b)=f(a)f(b)f(a b)=f(a)f(b) for all a,b∈R a,b∈R, then also f(b a)=f(b)f(a)=f(a)f(b)f(b a)=f(b)f(a)=f(a)f(b)
This means that f(a b)=f(b a)f(a b)=f(b a) for all a,b∈R a,b∈R
In particular, for b=1 b=1 and a∈R a∈R we get f(a 1)=f(1 a)⟹f(a)=f(1)f(a 1)=f(1 a)⟹f(a)=f(1) for all a∈R a∈R
This means that the only functions satisfying this property are constant
Moreover, if f(x)≡c f(x)≡c, then f(a b)=f(a)f(b)f(a b)=f(a)f(b) translates to c=c 2 c=c 2.
Thus there are only two functions with satisfy f(a b)=f(a)f(b)f(a b)=f(a)f(b): the constant functions f(x)≡0 f(x)≡0 and f(x)≡1 f(x)≡1
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Petr Ugarov
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Justin Rising
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What functions f f don't satisfy f(b)=f(a)+∫b a f′(t)d t f(b)=f(a)+∫a b f′(t)d t?
Any function f f such that f′f′ isn’t Riemann integrable on [a,b][a,b]. A good example of such a function is Volterra’s function. Otherwise, by the Fundamental Theorem of Calculus, as long as f′f′ is Riemann integrable on [a,b][a,b], the resulting integral must be f(b)−f(a)f(b)−f(a). That is, ∫b a f′(t)d t=f(b)−f(a)∫a b f′(t)d t=f(b)−f(a). Then, f(b)=f(a)+(f(b)−f(a))=f(b)f(b)=f(a)+(f(b)−f(a))=f(b). So any function such that f′f′ is Riemann integrable on [a,b][a,b] must satisfy the equality.
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Abdelhadi Nakhal
Lives in Morocco · Author has 1.3K answers and 435.7K answer views
·5y
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If a = b, then f(a) = f(b), does f(x) have to be one-to-one function or can f(x) be a non one-to-one function?
let: f:E→F f:E→F be a function.
By the definition:
A map must correspond (map) uniquely each element of E to an element of F (its image by f)
uniquely signifies that if a and b are identical then they have the same image in F.
This property have nothing with another property you mentioned in your question:
the injection:
a function is one to one or injective if every element of F is the image of at most one element of E.
We say at most because it is possible that some elements of F may have no antecedents by f.
that is injection signifies that there exist no different element a,b of E having the same im
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let: f:E→F f:E→F be a function.
By the definition:
A map must correspond (map) uniquely each element of E to an element of F (its image by f)
uniquely signifies that if a and b are identical then they have the same image in F.
This property have nothing with another property you mentioned in your question:
the injection:
a function is one to one or injective if every element of F is the image of at most one element of E.
We say at most because it is possible that some elements of F may have no antecedents by f.
that is injection signifies that there exist no different element a,b of E having the same image by f
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More answers below
If x^6=64 and (2/× - ×/2) = b, what is the function f that satisfies f(b+1) =0?
Is there a function that satisfies the equation $f(2x) =xf(x) $?
What is f(2) if f(x) satisfies f (1-f(x)) =x for f:R->R?
Can you give me equation along with values of x and y such that it satisfies f(x) f(y) = f(x+y)?
What function graph satisfies f(x) = -|f(x) | = f(-x)?
Francesco Amato
Studied at University of Bari (Graduated 1999) · Upvoted by
David Kaplan
, Ph.D. Mathematics, University of South Florida · Author has 4.5K answers and 1M answer views
·Mar 31
Related
Is it possible to find integers x and y that satisfy the equation x^y = y^x? If so, what are they? If not, why is it not possible?
All positive integers are solution of the transcendental equation
x y=y x x y=y x
provided that x=y x=y, except x=4 x=4 and y=2 y=2 or viceversa.
All other non integer solutions (see the graph below) are related by the function we are going to express as it follows:
y x(1 x)y=1 y x(1 x)y=1
y(1 x)y x=1 y(1 x)y x=1
y e log⎛⎝1 x⎞⎠y x=1 y e log(1 x)y x=1
y e y x log⎛⎝1 x⎞⎠=1 y e y x log(1 x)=1
−y x log x⋅e y x log⎛⎝1 x⎞⎠=−log x x−y x logx⋅e y x log(1 x)=−logx x
−y x log x⋅e−y x log x=−log x x−y x logx⋅e−y x logx=−logx x
W^{-1}\left[-\dfrac{y}{x}\l W^{-1}\left[-\dfrac{y}{x}\l
Continue Reading
All positive integers are solution of the transcendental equation
x y=y x x y=y x
provided that x=y x=y, except x=4 x=4 and y=2 y=2 or viceversa.
All other non integer solutions (see the graph below) are related by the function we are going to express as it follows:
y x(1 x)y=1 y x(1 x)y=1
y(1 x)y x=1 y(1 x)y x=1
y e log⎛⎝1 x⎞⎠y x=1 y e log(1 x)y x=1
y e y x log⎛⎝1 x⎞⎠=1 y e y x log(1 x)=1
−y x log x⋅e y x log⎛⎝1 x⎞⎠=−log x x−y x logx⋅e y x log(1 x)=−logx x
−y x log x⋅e−y x log x=−log x x−y x logx⋅e−y x logx=−logx x
W−1[−y x log x]=−log x x W−1[−y x logx]=−logx x
−y x log x=W[−log x x]−y x logx=W[−logx x]
y(x)=−x W[−log x x]log x y(x)=−x W[−logx x]logx
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Krishanu Dev
MCA from MNNIT, Allahabad (Graduated 2020)
·5y
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Which functions can satisfy f''(x) =f(x).f'(x) and f'(x) =f''(x).f(x)? (individual functions for each equation)
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Richard P
MMath in Mathematics, Churchill College, Cambridge (Graduated 2011) · Author has 807 answers and 317K answer views
·1y
Related
Can an expression for f(x) be found such that f(f(x)) = x? If so, what is the solution?
There are multiple candidates for f(x) such that f(f(x)) = x. A few are listed below:
f(x) = …
x
k - x (where k is a constant)
1/x (except at x=0 or its image at infinity)
-1/x (except at x=0 or its image at infinity)
∛(1-x³)
…
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9 2
Terry Moore
Calculus fan since 1958. · Author has 16.6K answers and 29.3M answer views
·6y
Related
How can I find all functions which satisfy f (x+f(x)) =x+f(f(x))?
How can I find all functions which satisfy f (x+f(x)) =x+f(f(x))?
Functional equations are difficult. It is often useful to start with some special cases and use an inductive method. Also, make use to the recurrence formula given.
The best I can do is refer you to Functional equation - Wikipedia. However, they don’t have any examples like yours.
Your equation is certainly satisfied by the identity function.
Also you could try starting from f(1)=c f(1)=c so that f(1+c)=1+f(c)f(1+c)=1+f(c). But I’m not sure where to go from here.
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Luboš Motl
Lives in Czechia · Author has 7.8K answers and 17.5M answer views
·10mo
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Does a function exist that satisfies the functional equation $f(x+y) =f(x) +f(y) $ for all real numbers $x$ and $y$?
A simple proportional function f(x)=a x f(x)=a x obeys the condition for any value of a a. However, with the axiom of choice, there are also infinitely many pathological, totally discontinuous solutions. With the axiom of choice, you may write real numbers as an infinite-dimensional linear space with (really, infinitely many!) rational coordinates.
So while f(0)=0 f(0)=0 is always needed, trivially from x=y=0 x=y=0 substituted to the general additivity rule, you may choose any values of f(1)f(1), f(√2)f(2), f(√3)f(3), f(e)f(e), f(π)f(π), and the values of the function at infinitely many other points that cannot be obtained fro
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A simple proportional function f(x)=a x f(x)=a x obeys the condition for any value of a a. However, with the axiom of choice, there are also infinitely many pathological, totally discontinuous solutions. With the axiom of choice, you may write real numbers as an infinite-dimensional linear space with (really, infinitely many!) rational coordinates.
So while f(0)=0 f(0)=0 is always needed, trivially from x=y=0 x=y=0 substituted to the general additivity rule, you may choose any values of f(1)f(1), f(√2)f(2), f(√3)f(3), f(e)f(e), f(π)f(π), and the values of the function at infinitely many other points that cannot be obtained from each other through rational coefficients, and complete the function to a function of all real numbers.
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9 1
Jacob Bartell
B.S in Fisheries&Aquatic Sciences, Grand Valley State University (Graduated 2023)
·5y
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If a = b, then f(a) = f(b), does f(x) have to be one-to-one function or can f(x) be a non one-to-one function?
I apologize, but I’m not sure I understand your question 100%, but I will give you my best answer. I’m the case of a one-to-one function, you can have f(x) functions. For example f(x)=x^2 is not a one-to-one (oto from here on out) function because you could have the following ordered pairs be true: (-2,4) and (2,4). There for you have two x (inputs) set to a single y (output). An example of a O.T.O. Function would be f(x)= x^3 where f(2)=8 and f(-2)=-8, in this case there is only one input for every output, and the graph of which would pass the horizontal line test. (A horizontal line will o
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I apologize, but I’m not sure I understand your question 100%, but I will give you my best answer. I’m the case of a one-to-one function, you can have f(x) functions. For example f(x)=x^2 is not a one-to-one (oto from here on out) function because you could have the following ordered pairs be true: (-2,4) and (2,4). There for you have two x (inputs) set to a single y (output). An example of a O.T.O. Function would be f(x)= x^3 where f(2)=8 and f(-2)=-8, in this case there is only one input for every output, and the graph of which would pass the horizontal line test. (A horizontal line will only touch one point no matter where it is set). Another OTO function is f(x)= x+1, no matter the input your output will be unique.
Hope this helps!
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9 1
Imad Zghaib
BA in Mathematics&Engineering, Free University of Brussels (ULB) (Graduated 1989) · Author has 2.6K answers and 1.6M answer views
·6y
Related
Is there a function f(x), such that f(a^b) = b^a (where a,b are real numbers)?
Yes
This function f(a^b) = b^a
Ex.
f(2^3)= 3^2
The function is f(x)=x 1/x f(x)=x 1/x
If x=a^b => f(x) = b^a
[(a^b)^{1/b}]{b^a}/a}
This function will be of two(2) variables.
f(x, y) = x^y
f(y, x) = y^x
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Vadim Yakovlevich
B.S. in Computer Science, Boston University · Author has 7.5K answers and 5M answer views
·5y
Related
If a = b, then f(a) = f(b), does f(x) have to be one-to-one function or can f(x) be a non one-to-one function?
If a=b, then f(a)=f(b) without regard to the function’s bijectivity. It follows from the definition of equality: a and b are fungible, it would make no sense if a function could distinguish between them.
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Luboš Motl
MSc in Mathematics and Physics&Theoretical Physics, Charles University in Prague (Graduated 1997) · Author has 7.8K answers and 17.5M answer views
·10mo
Related
What is the nature of a function that satisfies the equation $f(f(x)) =g(x) $? Can you provide some examples of such functions?
For literally any function f(x)f(x), you may simply calculate f(f(x))f(f(x)) for a given x x - by substituting the value of f(x)f(x) as an argument to the same function. If you use a new symbol for this f(f(x))f(f(x)), namely
g(x):=f(f(x))g(x):=f(f(x)),
you will clearly get a solution (f(x),g(x))(f(x),g(x)) of your functional condition, and there are obviously no other solutions because I have found all possible functions g(x)g(x) that work for all candidate functions f(x)f(x).
So for example, f(x)=sin x f(x)=sinx and g(x)=sin(sin x).g(x)=sin(sinx).
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What is a function that satisfies the functional equation f(x) =f(x)?
A linear function f satisfies f(0) = -1 and f(1) =-4. If f(x) = m(x-2) +b, what is b?
What is the function f:R→R f:R→R that satisfies f(f(x))=x f(f(x))=x?
Does $f(x+y) +y$ not exceed $f (f(f(x))) $ (functions, functional equations, functional inequalities, math)?
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If x^6=64 and (2/× - ×/2) = b, what is the function f that satisfies f(b+1) =0?
Is there a function that satisfies the equation $f(2x) =xf(x) $?
What is f(2) if f(x) satisfies f (1-f(x)) =x for f:R->R?
Can you give me equation along with values of x and y such that it satisfies f(x) f(y) = f(x+y)?
What function graph satisfies f(x) = -|f(x) | = f(-x)?
A function f satisfies f (7) = 3 and f (3) = 6. A function g satisfies g (3) = 7 and g (5) = 8. What is the value of f (g (3))?
What functions f f don't satisfy f(b)=f(a)+∫b a f′(t)d t f(b)=f(a)+∫a b f′(t)d t?
Let f be a function from R to R defined by f(x) =x-5. What are the values of a a and b given that (a,4) and (1,b) furthermore belong to f?
Does there exist injective functions f:N→N f:N→N satisfying f(f(n))=n+99 f(f(n))=n+99?
How does a function f f that satisfies f(2 x+y)=f(x+1)+f(y)+4 x y f(2 x+y)=f(x+1)+f(y)+4 x y for all x,y x,y exist (real analysis, functions, math)?
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What is a function that satisfies the functional equation f(x) =f(x)?
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What is the function f:R→R f:R→R that satisfies f(f(x))=x f(f(x))=x?
Does $f(x+y) +y$ not exceed $f (f(f(x))) $ (functions, functional equations, functional inequalities, math)?
What is a function which satisfies f(x+1) =f(x) and f(1) =1?
If x^6=64 and (2/× - ×/2) = b, what is the function f that satisfies f(b+1) =0?
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12598 | https://www.ocr.org.uk/Images/704406-examiners-report-the-business-environment.pdf | 05834–05837, 05878 CAMBRIDGE TECHNICALS LEVEL 3 (2016) ocr.org.uk/cambridgetechnicals Oxford Cambridge and RSA Version 1 CAMBRIDGE TECHNICALS BUSINESS Examiners’ report Unit 1 Summer 2023 series Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 2 © OCR 2023 Contents Introduction .......................................................................................................................................... 3 Unit 1 series overview ........................................................................................................................... 4 Section A overview ............................................................................................................................... 5 Question 2 ........................................................................................................................................ 5 Question 5 ........................................................................................................................................ 6 Question 7 ........................................................................................................................................ 7 Section B overview ............................................................................................................................... 8 Question 21 ...................................................................................................................................... 9 Question 22 .................................................................................................................................... 10 Question 23 .................................................................................................................................... 11 Question 24 .................................................................................................................................... 12 Question 25 .................................................................................................................................... 13 Section C overview ............................................................................................................................. 14 Question 26 .................................................................................................................................... 14 Question 27 .................................................................................................................................... 15 Question 28 .................................................................................................................................... 16 Question 29 (a) ............................................................................................................................... 17 Question 29 (b) ............................................................................................................................... 18 Question 30 (a) ............................................................................................................................... 19 Question 30 (b) ............................................................................................................................... 20 Question 31 .................................................................................................................................... 21 Question 32 .................................................................................................................................... 22 Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 3 © OCR 2023 Introduction Our examiners’ reports are produced to offer constructive feedback on candidates’ performance in the examinations. They provide useful guidance for future candidates. The reports will include a general commentary on candidates’ performance, identify technical aspects examined in the questions and highlight good performance and where performance could be improved. The reports will also explain aspects which caused difficulty and why the difficulties arose, whether through a lack of knowledge, poor examination technique, or any other identifiable and explainable reason. Where overall performance on a question/question part was considered good, with no particular areas to highlight, these questions have not been included in the report. A full copy of the question paper and the mark scheme can be downloaded from OCR. Would you prefer a Word version? Did you know that you can save this PDF as a Word file using Acrobat Professional? Simply click on File > Export to and select Microsoft Word (If you have opened this PDF in your browser you will need to save it first. Simply right click anywhere on the page and select Save as . . . to save the PDF. Then open the PDF in Acrobat Professional.) If you do not have access to Acrobat Professional there are a number of free applications available that will also convert PDF to Word (search for PDF to Word converter). Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 4 © OCR 2023 Unit 1 series overview This series has seen some successful responses relating to environmentally friendly business operations (as illustrated by responses to Question 28). Examiners have also seen some improvement in candidates’ understanding of financial documents and concepts (as illustrated by responses to Questions 29 (a) and (b). However, Learning Outcome (LO) 7 appears to be an area of the specification for which candidates are not fully prepared, in particular LO7.2 (sources of finance), as highlighted by responses to Question 23. In addition, LO3 relating to organisational structure (as highlighted by responses to Question 22), appears difficult for candidates to assimilate and is worthy of extra attention. As ever, those candidates who showed a sound understanding across the breadth of the Specification, coupled with an ability to analyse and evaluate, did well on this paper. Candidates who did well on this paper generally: Candidates who did less well on this paper generally: • researched a wide variety of businesses, targeted to the research brief (for Section B) • demonstrated numerical skill (in Questions 5 and 13) and the ability to interpret data in a table (Question 8) and in an income statement (Question 29 (a)) • answered questions contextually (in Sections B and C) • made judgements supported by justified reasoning (Section C extended response questions). • left answer spaces blank (including multiple-choice questions and Question 26) • showed little evidence of studying the topics indicated in the pre-release research brief (particularly evident was a lack of knowledge of a mortgage as a form of finance (Question 23)) • ended extended response questions abruptly, without making an overall judgement • demonstrated little, or no knowledge of organisational structure (Specification reference LO3), in particular for the hierarchy in Question 2 hierarchy and matrix structure in Question 22. Areas which caused most problems on this paper were organisational structure (Questions 2 and 22), legal issues (Question 25) and mortgages as a source of finance (Question 23). However, Question 24 on meeting the needs of employees, Question 27 on the advantages and disadvantages of trading as a partnership and Question 29 (a) on interpretation of an income statement were well answered. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 5 © OCR 2023 Section A overview Section A gives time for candidates to settle into the exam. This section of the paper was generally well answered by most candidates. A few candidates missed out on marks because they ticked two responses instead of just one. Candidates should be instructed not to take this approach. Where a candidate indicates a response and subsequently changes their mind, they should clearly cross out their original tick. In addition, some candidates lost marks by leaving a multiple-choice question entirely blank. This is not good examination technique and candidates should be encouraged to indicate a response to all 20 questions. The vast majority of multiple-choice questions were well answered. Those that were more problematic are discussed below. Question 2 This question tested knowledge and understanding of hierarchical organisational structure, often portrayed on an organisation chart. Candidate responses were fairly evenly split. This appears to indicate confusion between the different job roles. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 6 © OCR 2023 Question 5 This question tested knowledge and understanding of variable costs rather than fixed costs. Candidates should be aware that variable costs are ‘unit’ based, in this case ‘per tablet’; whereas fixed costs are ‘time’ based, in this case a year. A few candidates selected the correct response, i.e. B £67 (£25+ £38+£4). Assessment for learning Centres are advised to get candidates to practise cost, revenue and profit calculations at frequent intervals throughout the programme of study. They could do this as a starter to a lesson, while waiting for all students to arrive. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 7 © OCR 2023 Question 7 This question tested the impact of the external environment on a business. In this case, the cause of the rising costs was economic, i.e. inflation. Very few candidates gave the correct response. This suggests that the impact on the external environment is an aspect of the specification that needs further reinforcement. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 8 © OCR 2023 Section B overview The questions in Section B should be answered with direct reference to candidates’ personal research, as directed by the pre-released research brief available in advance of the examination. How each question in this section links to the research brief is tabulated below. For each question in this section, candidates are advised to select the most appropriate business from the ones that they have researched, rather than answer all questions about the same business. Evidence suggests that choosing a specific business on which to answer each question leads to better focused responses and higher marks. Section B was still not as well answered as might be expected, given the clear guidance on areas to focus on in the pre-issued research brief for this examination. Some less successful responses showed no evidence at all of research for Section B, the one area of the paper where candidates can prepare in advance. Centres are advised to devote adequate time to the preparation of candidates for Section B of this paper, the research brief for each series is specific to that series and is issued well in advance of the examination. How the research brief linked to the questions in Section B Question 21: Identify two growth aims of a business that you have researched. The non-financial aims of businesses. Question 22: Explain one advantage and one disadvantage to a business that you have researched of using a matrix structure. Matrix structures and their impact on business operations. Question 23: Explain two advantages to a business that you have researched of using a mortgage as a source of finance. The benefits of using long term sources of finance. Question 24: Analyse one advantage and one disadvantage to a business that you have researched of meeting the needs of its employees. Responding to the ever-increasing demands of stakeholders. Question 25: Describe how a business that you have researched has altered its business practices to comply with the General Data Protection Regulation (GDPR), now included in the Data Protection Act. Complying with the requirements of the General Data Protection Regulation (GDPR). Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 9 © OCR 2023 The wording of Questions 22 and 25 linked extremely closely with the wording of the pre-issued research brief, however some candidates still showed very limited knowledge or understanding. Centres are advised to emphasise to candidates the importance of focussing their business research and revision on the topics indicated in the corresponding series’ research brief. Evidence suggests that those candidates who chose to answer all five questions in Section B on the same business did less well than those who selected a business according to the question. Candidates should be encouraged to select the business they use depending on the question, i.e. to choose a specific business for which their understanding is suitable for answering the question. This was especially important for Question 22 where the business needed to use a matrix structure and for Question 23 where the business needed to have a mortgage. Question 21 This question was generally well answered with most candidates gaining at least 1 of the 2 marks. Where no marks were achieved the error was almost always to give financial or reputational aims. The specification splits business aims into five types, please see the specification and the published mark scheme for further details. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 10 © OCR 2023 Question 22 There were not many successful responses to this question. Candidates often had attempted to give an advantage or disadvantage, but it was clear that they had no robust understanding of what a matrix structure was. Organisational structure is an area of the specification that candidates find difficult to assimilate. Matrix structure was even more difficult to grasp than many of the other structures. Assessment for learning Centres are advised to make sure candidates have a robust understanding of different organisational structures. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 11 © OCR 2023 Question 23 Despite the benefits of long-term finance being indicated on the research brief as an area for detailed study, it appeared that many candidates did not know what the benefits of a mortgage are. Those that did were given at least 2 marks, and those who used context were given full marks. In addition, a frequent error was to give an advantage and a disadvantage rather than two advantages. Candidates need to be encouraged to read the question carefully and, having written their response, re-read the question to check it is the one they have answered. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 12 © OCR 2023 Question 24 The advantage was generally well answered, often contextually. This showed candidates had a good grasp of why businesses should meet the needs of its employees. The disadvantage was less well answered, with some candidates suggesting that there were no disadvantages. The most commonly seen correct response to this part of the question was the financial cost involved. Some candidates misinterpreted the second part of the question and answered about not meeting the needs of employees, and this could not be given any marks, which shows the importance of reading the question carefully. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 13 © OCR 2023 Question 25 This question dichotomised candidates. Some showed very clear knowledge of the extra requirements of the GDPR, while others had no knowledge at all. The most common error was to give non-GDPR requirements of the Data Protection Act (DPA). Please see the published mark scheme for more details. The focus on the GDPR requirements was clearly indicated in the research brief issued in advance of the examination. Centres need to make sure that candidates are familiar with how to use this research brief. If not, the candidate is at a significant disadvantage when answering Section B of this qualification. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 14 © OCR 2023 Section C overview As always, Section C contained three high tariff, extended response questions. These questions were Level of Response marked. Candidates needed to demonstrate the skills of analysis (Level 3) and evaluation (Level 4) to gain the highest marks. Analytical skill (Level 3) Analysis requires candidates to develop their responses to include impacts on the business. It should be noted that phrases such as ‘this will change the firm’s reputation’ (Question 28), ’this will affect their ability to pay bills (Question 31 (b)) or ‘this will impact on revenue’ (Question 31), cannot be given the marks because the direction of the impact is unclear. Candidates need to make explicit the direction of the impact, i.e. a better reputation, less likely to be able to repay and increased revenue. Analytical skill (Level 4) Evaluation requires a reasoned decision that answers the question, i.e. the best benefit from the business’ perspective of being environmentally friendly (Question 28), the worst negative impact on the business of the Weaknesses in the SWOT analysis (Question 30 (b)) and a recommendation as to which change to the service provision of the hotel in the light of a fall in unemployment (Question 31). Candidates should be encouraged to reach decisions and give detailed justification to support th eir argument using contextual information. While an accurate judgement that applies to most businesses would achieve a Level 4 mark, a response which argues using the particular circumstances of the business scenario, in this case a basic hotel, would be given more marks. All of the questions in this section link to the business scenario which should be read carefully before answering any of the questions in this Section of the exam paper. Question 26 Taylor and Mia operate as a partnership, therefore they have unlimited liability. Some candidates selected the wrong answer which indicates that knowledge of the liability status of various types of business is not robust. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 15 © OCR 2023 Question 27 In contrast to Question 26, candidates appeared to have a firm understanding of the advantages and disadvantages of operating as a partnership rather than as a sole trader. The most common correct advantages related to increased capital, sharing ideas and sharing workload. Candidates whose response suggested that liability was shared could not be given the marks because partners are jointly and severally liable. The most common disadvantages related to decision-making, arguments and profits having to be shared. Most candidates were given at least 2 marks for this question, and those that answered in context were given full marks. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 16 © OCR 2023 Question 28 As with all 12 mark questions on this paper, this question is Level of Response marked. The type of response examiners were looking for is shown in the exemplar response in the published mark scheme. This question centres around the benefits to a business of being environmentally friendly. There were plenty of benefits to choose from. Candidates did well on this question, with most candidates being able to accurately identify and articulate the benefits of operating a hotel in an environmentally friendly manner. By far the most common response was ‘enhanced reputation’ (Level 1), attracting more customers (Level 2) leading to greater revenue (Level 3). Such a chain of argument scored 7 of the available 12 marks solely for discussion of this one impact. Other commonly cited impacts, i.e. Level 1, were ‘savings on electricity’ and ‘having a unique selling point’. Many candidates were able to develop their responses through a chain of argument to the impact on the business, gaining extra Level 3 marks. Once Level 3 had been achieved, a selection of one impact with appropriate justification as to why it was the best was placed in Level 4. Those candidates who gave a contextual justification achieved a minimum of 11 marks. About a quarter of candidates attempted to make such a decision, i.e. which would be the best benefit for Wattis Hotel. Those who did, and also gave a valid reason for their choice, were given a Level 4 mark. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 17 © OCR 2023 Question 29 (a) Most candidates showed a good grasp of the income statement and correctly identified that a significant increase in operating expenses was the problem and many were given full marks. Of those that did not achieve full marks, there was one particular type of error. This related to insufficient consideration of the column headings. The column headings contained two important pieces of information, namely the years and the units, i.e. £’000s. Ignoring of either of these pieces of information could lead to giving an incorrect response. Assessment for learning Candidates should be encouraged to carefully check the dates at the top of columns for numerical data. When accounting data is presented, the convention is often to put the most recent year to the left. In addition, they should carefully check the units. Saying that the operating expenses increased by £42 is a significant way from the truth, they increased by £42,000. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 18 © OCR 2023 Question 29 (b) Candidates did well with ‘costs’ and ‘net profit’ with the vast majority giving correct responses. The impact on the ‘break-even point’ was less well answered. Many candidates expressed that the impact on the break-even was likely to be damaging, but in firming up their response said that this would lead to a ‘lower’ break-even point. Misconception There appears to be a common misconception among candidates that a lower break-even point is a bad thing. A lower break-even point is always advantageous to a business. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 19 © OCR 2023 Question 30 (a) Many good, clearly expressed responses were received for this question, with differences explicitly stated. The most common response was about the source of the issue, i.e. external for Threat, internal for Weakness. Less successful responses made vague points about one or both of the terms, but did not actually point out a difference. Such responses were given 1 of the available 2 marks. Some responses revealed assumptions about the meaning of the terms which were simply incorrect. Please see the misconception box below. Misconception Answers to this year’s question about the differences between Weaknesses and Threats on a SWOT analysis revealed several misconceptions, these include: • Threats are serious, weaknesses less severe • Threats might happen, weaknesses have happened • Threats can be ignored, weaknesses must be fixed None of these are correct. Please see the published mark scheme for suggested corrected responses. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 20 © OCR 2023 Question 30 (b) As with all 12 mark questions on this paper, this question was Level of Response marked. The type of response the examiner was looking for is shown in the exemplar response in the published mark scheme. This question required candidates to evaluate negative impacts on Wattis Hotel of the Weaknesses on its SWOT analysis. Most candidates were able to suggest negative impacts of the human resource, marketing and cash flow issues identified. Those who could suggest the further impact of these on the hotel gained Level 3 marks. To encourage all candidates to make a justified judgement for Level 4, the question demanded this explicitly. Most candidates, therefore, wrote a final paragraph which selected their chosen negative impact. Those that gave a valid reason for their choice were given a mark in Level 4. Those candidates who gave a contextual justification achieved a minimum of 11 marks. It is good practice to re-read the question before attempting to write the conclusion. This hopefully avoids writing an incorrect type of judgement. For this question, an incorrect type of conclusion would be suggesting solutions to each of the three weaknesses or arguing why all impacts of Weaknesses are negative rather than positive. Neither of these types of conclusions answers the question set. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 21 © OCR 2023 Question 31 As with all 12 mark questions on this paper, this question was Level of Response marked. The type of response examiners was looking for is shown in the exemplar response in the published mark scheme. This question centres around improvement to service provision in the light of a fall in unemployment levels. Some more successful responses gave practical suggestions such as adding a kitchen or breakfast room, redecorating the bedrooms or adding a gym. All of these were appropriate for a period where disposable income is increasing and were placed in Level 1. Unfortunately, several candidates suggested that in a period of lower unemployment that prices should be lowered, this is incorrect and may indicate a misreading of the question. To move through the Levels of Response, candidates needed to explain the reason for their suggestion (Level 2) and analyse the benefit to the business of their suggestion (Level 3). One such common chain of argument was ‘offer breakfast (Level 1) because the travellers have more money to spend (Leve l 2), increasing revenue for the hotel (Level 3)’. Many successful responses ended abruptly after the final weakness had been analysed. To improve their responses, candidates should be encouraged to add an evaluative conclusion to achieve Level 4. Some candidates performed less well than expected on this question. Some candidates discussed human resource issues relating to increasing the wages of staff or offering them motivational packages. These responses did not answer the question set, which related to increasing service provision in times when unemployment falls. Marks could not be given for general suggestions about how to improve the running of the hotel. Level 3 Cambridge Technical in Business - Unit 1 - Summer 2023 Examiners’ report 22 © OCR 2023 Question 32 This question tested the role of business functions, in this case customer service. Responses relating to specific job roles, e.g. checking people in to a hotel could not be given the marks as this is the role of the receptionist. Likewise, activities such as ‘cleaning the rooms’ could not be given the marks as this is the role of the operations functional area. The most common correct responses related to answering customers queries or dealing with complaints. Please see the published mark scheme for other acceptable responses. Supporting you Teach Cambridge Make sure you visit our secure website Teach Cambridge to find the full range of resources and support for the subjects you teach. This includes secure materials such as set assignments and exemplars, online and on-demand training.
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12599 | https://www.youtube.com/watch?v=KoVQlqv4e_8 | Chapter 7: Membrane Structure and Function | Campbell Biology (Podcast Summary)
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Posted: 13 Mar 2025
Chapter 7 of Campbell Biology explores the structure and function of cellular membranes, emphasizing their role in selective permeability, transport, and communication. The fluid mosaic model describes membranes as a bilayer of phospholipids with embedded proteins, which regulate the passage of substances and enable cell signaling. The chapter also covers passive and active transport, osmosis, and bulk transport mechanisms (exocytosis and endocytosis).
The membrane's amphipathic nature—with hydrophilic heads and hydrophobic tails—allows it to form a selectively permeable barrier. Proteins and carbohydrates contribute to cell recognition, signaling, and structural support, while cholesterol stabilizes membrane fluidity. The chapter further explains diffusion, osmosis, facilitated diffusion, and energy-requiring transport mechanisms, highlighting their importance in cellular function and homeostasis.
🔹 Key Concepts
🔹 Fluid Mosaic Model: Membrane Structure and Function
Phospholipid bilayer forms a flexible membrane with hydrophilic heads facing outward and hydrophobic tails inward.
Integral proteins span the membrane, involved in transport and signaling.
Peripheral proteins attach to the membrane’s surface, aiding in communication and support.
Membrane carbohydrates (glycolipids and glycoproteins) assist in cell recognition and signaling.
Cholesterol in animal cell membranes helps maintain fluidity at different temperatures.
🔹 Membrane Permeability and Transport
✅ Selective Permeability
Small nonpolar molecules (O₂, CO₂) easily cross the membrane.
Ions and polar molecules require transport proteins.
✅ Passive Transport: Diffusion Without Energy
Simple diffusion: Molecules move from high to low concentration without energy input.
Osmosis: Water moves across membranes from low solute concentration to high solute concentration.
Facilitated diffusion: Transport proteins help polar molecules and ions cross (e.g., aquaporins for water).
✅ Tonicity and Water Balance
Isotonic Solution: No net water movement; cell remains stable.
Hypotonic Solution: Water enters the cell; animal cells may lyse, plant cells become turgid.
Hypertonic Solution: Water leaves the cell; cells shrink (plasmolysis in plants).
🔹 Active Transport: Energy-Dependent Movement
Requires ATP to move molecules against their concentration gradient.
Sodium-Potassium Pump (Na⁺/K⁺ Pump): Moves 3 Na⁺ out and 2 K⁺ in, maintaining membrane potential.
Proton Pumps: Actively transport H⁺ ions, generating voltage for cellular processes.
🔹 Bulk Transport: Exocytosis and Endocytosis
✅ Exocytosis: Vesicles fuse with the plasma membrane, secreting materials (e.g., neurotransmitters).
✅ Endocytosis: Cell engulfs materials into vesicles:
Phagocytosis ("cell eating"): Engulfs large particles.
Pinocytosis ("cell drinking"): Engulfs fluids and solutes.
Receptor-Mediated Endocytosis: Highly specific uptake of molecules via receptor proteins.
📖 Glossary of Terms
🔹 Amphipathic Molecule – A molecule with both hydrophilic and hydrophobic regions.
🔹 Fluid Mosaic Model – Describes the dynamic, flexible nature of the membrane with embedded proteins.
🔹 Selective Permeability – The ability of the membrane to regulate what enters and exits the cell.
🔹 Osmosis – Diffusion of water across a selectively permeable membrane.
🔹 Isotonic, Hypotonic, Hypertonic – Terms describing solute concentration effects on cells.
🔹 Facilitated Diffusion – Passive transport with the help of transport proteins.
🔹 Active Transport – Movement of molecules against a gradient using ATP.
🔹 Sodium-Potassium Pump – An active transporter that moves Na⁺ out and K⁺ into the cell.
🔹 Exocytosis – Process where vesicles release materials outside the cell.
🔹 Endocytosis – Process where the cell engulfs molecules into vesicles (includes phagocytosis, pinocytosis, and receptor-mediated endocytosis).
Campbell Biology Chapter 7 summary, Membrane Structure and Function, Fluid Mosaic Model, Passive and Active Transport, Osmosis and Diffusion, Endocytosis and Exocytosis, Sodium-Potassium Pump, Cellular Transport, AP Biology Study Guide, College Biology Notes 📘 Read full blog summaries for every chapter:
Transcript:
Welcome back to the deep dive. You know, this time we are uh diving into a world that's so tiny you need a microscope to even see it. Oh wow. We're talking about the cell membrane. That's right. You requested a deep dive into chapter 7 of your biology textbook. Excellent choice. And that's what we're going to do. Unpack all that awesome science that's packed in those pages. Absolutely. Cell membranes, you know, they might be small, but they're uh oh, they are absolutely critical for life. They're like the gatekeepers, you know. I like that. For the cell. Yeah. They control what goes in, what goes out, and they're involved in so many of the cells uh most essential processes. And to help us navigate this microscopic marvel, we have our expert in all things cellular. Happy to be here. I am so excited to learn about this. I have to admit when I first read through the chapter, I was a little overwhelmed, I can imagine, by all the details, all the terminology. We've got the fluid mosaic model and phosphoipids, proteins, transport mechanisms. It's uh it's a lot to take in. It definitely can be. But uh don't worry, we'll break it all down step by step. And uh by the end, I promise you'll have a much deeper appreciation for just how amazing cell membranes truly are. That's what I like to hear. Okay, so the chapter kicks off with the fluid mosaic model. I remember reading that and thinking, okay, well that sounds kind of cool, but what does it actually mean? Yeah, it's a uh really elegant way of describing the structure of the cell membrane. Just imagine uh like a sea of lipids, kind of like a constantly moving ocean. Okay. And scattered throughout this sea are all sorts of proteins. Imagine those are like ships sailing around. So, it's not just a rigid wall then. No, not at all. It's uh more dynamic and constantly changing environment. Exactly. And this fluidity is uh it's crucial for so many reasons. Number one, it allows the membrane to kind of uh adjust to changing conditions. Think about temperature. Oh, okay. When it's cold, the membrane needs to stay fluid enough to function properly, but when it's warm, it can't uh become too loose. That makes sense. It's like um how olive oil will become thicker in the fridge, but it flows really easily at room temperature. That's a great analogy. The types of lipids in the membrane can actually change to adjust to different temperatures. It's like a a built-in thermostat. Wow, that's pretty cool. Yeah. So, we have this sea of lipids and then these proteins that are floating around. What are the proteins up to? Ah, yes. The proteins. Well, they are the real workh horses of the cell membrane. They do Oh, they do all sorts of jobs like uh transporting molecules, acting as enzymes, receiving signals from other cells, and they even help cells stick together. Wait, so they're not just like floating around aimlessly. Do they have specific roles? Absolutely. And the types of proteins that are present in a membrane, those determine the specific functions of that cell. It's like um having a team of specialists, each with their own unique skill set. So if we think back to that city analogy, the proteins are like all the different businesses and services that make a city function, right? We've got the transportation workers, the chefs, the construction crews, communication experts, each one contributing to the overall operation of the city. Exactly. And just like in a city, there's a lot of uh communication and interaction going on between these different proteins. They work together to maintain the cell's internal environment and they respond to changes in the external world. Okay, that's starting to paint a clearer picture for me. But um let's back up a bit and talk about those lipids that make up the foundation of the membrane. The chapter mentions something about a phosphoipid billayer. What's that all about? Right. So the uh the most common type of lipid in the membrane is a phosphoipid. And these molecules have a unique structure. You see they have a head that loves water what we call hydrophilic. Okay. And then a tail that hates water which we call hydrophobic. Okay. So water loving heads, waterfearing tails. Where do they fit into this whole membrane picture? Well, remember how the cell exists in a watery environment both inside and outside. Yeah. So to accommodate this, the phospholipids arrange themselves in a really clever way. They form a double layer or a blayer with their water loving heads facing outwards towards the water, right? And their waterfearing tails tucked inwards away from the water. So it's like a um like a double- layered sandwich, right? Where the bread represents those water loving parts and then the filling represents the waterfearing parts. That's a that's a delicious way to visualize it. And the whole sandwich is sitting in a cool of water. That's right. And this uh this unique arrangement creates a barrier that is selectively permeable, meaning that uh some things can pass through easily while others can't. And this selectivity is vital for the cell to function properly. It's amazing how such a seemingly simple arrangement of molecules can create such a sophisticated system. I'm already starting to see why you said cell membranes are so remarkable. And we've only just uh scratched the surface, but before we move on, are there any burning questions that you have about the fluid mosaic model or the phosphoipid billayer? I think you've done a great job explaining those concepts so far. I'm particularly intrigued by this idea of selective permeability, though. Yes. How does the membrane decide what gets in and what stays out? That's a great question and it leads us perfectly into the next part of our deep dive. The fascinating world of membrane transport. So, you're curious about how the cell membrane decides what gets in and what stays out. Well, that's a question that has fascinated scientists oh for decades. It's like the membrane is playing the role of a bouncer at a very exclusive club. Oh, I like that. Right. Some molecules get the VIP treatment and sail right in. Yeah. While others are left standing outside in the cold. I like that analogy. And just like a good bouncer, the cell membrane has a set of rules that determines who gets in and who doesn't. Okay. And these rules, they're based on the size, the charge, and even the polarity of the molecule that's trying to cross. So, it's not just like a uh a random free-for-all. Not at all. There's a method to the madness. Absolutely. The membrane is incredibly selective, and this selectivity is crucial. Uh it's really crucial for maintaining the cell's internal environment and ensuring that it can function properly. Now the way things move across the membrane can be broadly categorized into two main types. Passive transport and active transport. Okay, those terms uh ring a bell from the chapter. Good. Passive transport sounds like the uh easy route. No effort required. Exactly. Passive transport is all about moving down the concentration gradient. Imagine you have a crowded room and you have a spacious one. People are naturally going to move to where there's more elbow room. Right. It's like going with the flow. Yes. from where there's more of something to where there's less. No need to push or shove, just ride the wave. Perfect description. And this movement uh it doesn't require any energy from the cell. It's uh it's a spontaneous process. It's driven by the natural tendency of molecules to kind of spread out. A classic example is oxygen entering cells for respiration. Oxygen is more concentrated outside of the cell. So, it naturally diffuses across the membrane to where it's needed inside. Okay, that makes sense. Yeah, but not everything can just uh you know walt across the membrane, right? What about those molecules that need a little extra help? Uh that's where facilitated diffusion comes in. It's still passive transport, meaning that no energy is required from the cell, but it involves uh it involves special proteins that are embedded in the membrane that act like little helpers facilitating the movement of certain molecules. So these proteins are like the um the friendly ushers at the club guiding certain guests to their designated areas. Exactly. And uh there are different types of these helper proteins. Some are like channels creating a direct pathway through the membrane for specific molecules to pass. Others are like carriers. They bind to a molecule and change shape to shuttle it across. It's amazing how these tiny proteins are so specialized. Each one designed for a specific task. It is ensuring the right molecules get to where they need to go. It's uh it's a remarkable example of how evolution has fine-tuned the cell membrane to be an incredibly efficient and selective barrier. Yeah. But sometimes cells need to move things against the natural flow, you know, from low concentration to high concentration and that requires a little more effort. Okay. So that's where active transport comes in, right? You got it. It's uh it's like swimming upstream. You need to put in some serious energy to make it happen. Exactly. Active transport requires energy, usually in the form of ATP, which is like the cell's energy currency, right? And uh this energy is used to power special protein pumps that move molecules against their concentration gradient. The chapter gave the example of the sodium potassium pump. Yes. Which sounds like a real workhorse. Can you tell me more about that? Oh, the sodium potassium pump is a classic example of active transport. It's constantly working to pump sodium ions out of the cell and potassium ions in even though there's already a higher concentration of sodium outside and potassium inside. So it's uh constantly battling against the natural flow like trying to keep a beach ball submerged in a pool. Exactly. And uh this constant pumping is essential for maintaining the right balance of ions inside and outside the cell which is crucial for so many cellular processes including nerve impulse transmission and muscle contraction. Wow. It's mind-blowing to think that something as simple as moving ions across a membrane is so crucial for so many complex functions. Yeah. It really highlights the importance of active transport. Absolutely. It's uh it's a fundamental process that allows cells to create and maintain an internal environment that is different from their surroundings which is uh you know essential for life as we know it. Now, we've talked about how small molecules move across the membrane, but what about larger molecules, right, like proteins or even whole bacteria? How do they get in and out? That's a good question. I remember the chapter mentioned something about bulk transport, right? Bulk transport is how cells move really large molecules in and out. Uh they use these things called vesicles. They're like tiny membrane bound packages. So, instead of using doors or channels, the cell is using these little delivery trucks to move the big cargo in and out. Yes, it is. And there are two main types of bulk transport. Okay? Exocytosis where vesicles fuse with the membrane to release their contents outside the cell. Right? And endoccytosis where the membrane pinches inward to engulf substances and bring them inside. Okay. So echoytosis is like sending out a delivery truck. And endoccytosis is like receiving a package. Can you give me some uh real world examples of these processes in action? Of course. Think about hormone secretion. Cells in your pancreas package insulin into vesicles and release them into your bloodstream via exocytosis helping to regulate your blood sugar levels. Or think about how nerve cells communicate. They release neurotransmitters which are chemical messengers via exocytosis allowing signals to travel throughout your nervous system. So exocytosis is like the cell's way of communicating with the outside world. Exactly. What about endoccytosis? What kind of packages are cells bringing in? Endoccytosis is uh it's all about bringing in essential supplies or even engulfing whole cells. For example, white blood cells use a type of endoccytosis called faggoytosis to engulf and destroy bacteria. Oh wow. Protecting your body from infection. So our immune system relies on these uh tiny packages to fight off invaders. It's amazing to think about all the drama unfolding at the cellular level. It is. And there are other types of endoccytosis as well like pinoytosis where cells take in droplets of fluid and receptor mediated endoccytosis which is a highly specific process where certain molecules bind to receptors on the cell surface and this triggers the formation of a vesicle. Receptor mediated endoccytosis sounds very precise. Is that how cells take in specific nutrients or signals from their surroundings? Exactly. It's a way for cells to be very selective about what they bring in. Kind of like having a personal shopper for the cell. And uh this process is crucial for many important functions including the uptake of cholesterol from your blood. Wow. So all these different types of transport are happening constantly. Yeah. Ensuring that cells get what they need and maintain a stable internal environment. They are. It's a real balancing act. It is. And it all comes back to the remarkable properties of the cell membrane. its fluidity, its selective permeability, and its ability to interact with a wide range of molecules and signals. Okay, so we've covered a lot of ground about membrane transport. We have. We've explored passive and active transport, facilitated diffusion, and even bulk transport with exocytosis and endoccytosis. We have. Is there anything else we need to know about how things move across this incredible barrier? Well, we've covered the major players in membrane transport, but there's one more fascinating process we need to talk about, and that's osmosis. Osmosis. I remember that word from the chapter, but I'll admit it always makes me think of high school science labs and uh those shriveled potatoes. I understand. Osmosis can seem a bit intimidating at first, but it's actually a very simple concept uh once you get the hang of it. Okay, so uh remind me what exactly is osmosis? It's just water moving around randomly. Not exactly random. Osmosis is the movement of water across a selectively permeable membrane like our cell membrane friend, right? From a region of high water concentration to a region of low water concentration. It's a type of diffusion but specifically for water. So water wants to go where there's less water. That seems a little counterintuitive. It does seem a bit strange, right? But it makes more sense if you think about it in terms of solute concentration. Water moves to dilute the area with more stuff dissolved in it. Okay? Things like salts, sugars, proteins. So, water flows from an area of low salute concentration to an area of high salute concentration trying to even things out. Okay. So, it's not that water is attracted to where there's less water. It's more like it's trying to uh dilute the areas where there's more stuff dissolved. Exactly. And this difference in salute concentration across a membrane this creates what we call tenicity. Okay. And there are three main types of tenicity. Okay. Isotonic, hypertonic and hypotonic. Those terms sound familiar but uh refreshing my memory. What do they actually mean? Sure. So isotonic means that the solute concentration is balanced inside and outside the cell. Okay? So there's no net movement of water. Think of it like equilibrium. Everyone's happy. No need to move. Okay? Isotonic. Everything's balanced. What about hypertonic? That sounds a little more intense. Hypertonic means that the solute concentration is higher outside the cell than inside. Okay. So water rushes out of the cell trying to dilute that outside environment and the cell shrivels up like those uh like those poor shriveled potatoes in the science lab. Exactly. So basically the water is leaving the cell to go hang out with all the solutes outside. And what about hypotonic? Hypotonic is the opposite. The solute concentration is lower outside the cell. Oh. So water rushes into the cell trying to dilute the inside environment and the cell swells up. And if too much water rushes in, the cell could even burst. Right. Like an overfilled water balloon. Exactly. But cells have uh they have these clever ways to regulate their water content and prevent that from happening. Plant cells, for example, they have rigid cell walls that prevent them from bursting in those hypotonic environments. Right? In fact, they actually thrive in hypotonic conditions because the water pressure, which we call tur pressure, helps them stay firm and upright. That's why wilted lettuce perks up in water. It's absorbing water and regaining that tur pressure. Fascinating. It is. And even single-sellled organisms like parramium, which don't have cell walls, have developed mechanisms to deal with osmotic pressure. They have these things called contractile vacules which act like tiny pumps constantly expelling excess water. It's incredible how much effort goes into maintaining water balance at the cellular level. It really underscores the importance of osmosis and the delicate balance that cells need to maintain. We've talked about how water moves, but remember membranes are involved in transporting all sorts of molecules. Right. That's right. We've explored how small molecules move in and out, how large molecules get transported, and how water plays a crucial role in maintaining balance. What else is there to uncover about these amazing membranes? Well, remember how we talked about those membrane proteins having all those specialized jobs? Some of those proteins are involved in more than just transport. Okay. They play crucial roles in cell signaling and communication. Oh, right. Like those receptor proteins we mentioned earlier. Exactly. They're like the cell's ears listening for signals from the outside world. Exactly. These receptors are incredibly specific. They bind only to certain molecules like hormones or neurotransmitters. And when a molecule binds to its receptor, it triggers this cascade of events inside the cell leading to a specific response. So it's like a lock and key system, only the right key can unlock that specific response. A perfect analogy. And this communication system, it's essential for everything from coordinating our bodily functions to responding to environmental changes. Think about how your body regulates blood sugar levels. Okay? When your blood sugar rises, cells in your pancreas release insulin, which binds to receptors on other cells, signaling them to take up glucose from the blood. So without these receptor proteins, our cells would be deaf to the world around them. Exactly. And this communication system is just one example of the many complex and dynamic processes that occur at the cell membrane. But before we wrap up our deep dive, I want to highlight one more aspect. the amazing diversity of membrane structures. Oh yeah, I remember reading about all sorts of specialized structures like junctions, infoldings, lipid rafts. It was a bit of a whirlwind. It's a lot to take in, but it's fascinating how those basic principles of the fluid mosaic model can be adapted to create such a wide array of specialized structures. Can you give me some examples of how these structures play unique roles in different cells? Absolutely. Take membrane junctions for instance. These are specialized structures that connect adjacent cells, allowing them to communicate and function as a coordinated unit. So, it's not just about individual cells doing their own thing. It's about them working together as part of a larger community. Exactly. And there are different types of junctions, each with its own unique function. Tight junctions create a seal between cells, preventing leakage, like the lining of your intestines. Desmosomes act like rivets, anchoring cells together and providing strength like in your skin. And gap junctions are like tiny tunnels connecting the cytoplasm of adjacent cells allowing for direct communication. It's amazing how these tiny junctions play such a big role in coordinating cellular behavior. It really is. And then there are membrane infoldings which increase the surface area of the membrane like adding shelves to a closet, right? And this is especially important for cells involved in absorption like those lining the small intestine where microvilli those finger-like projections maximize the surface area for nutrient uptake. So more surface area means more space for transport proteins which means more efficient absorption. Exactly. And even the lipid composition of the membrane can be specialized. Lipid rafts are regions of the membrane that are enriched with certain lipids and proteins and these create these specialized zones for specific functions like cell signaling. It's like creating different neighborhoods within the city, each with its own unique character and purpose. A great analogy. And all of this diversity just highlights the incredible adaptability of the cell membrane. It's not just a static barrier. It's a dynamic and versatile platform that plays a central role in oh virtually every aspect of cellular life. Wow. This deep dive has been truly eye opening. I had no idea just how intricate and fascinating cell membranes are. It's a testament to the beauty and complexity of life at the molecular level. And it really underscores the importance of continuing to explore and understand these fundamental structures. Absolutely. Because the more we learn about cell membranes, the better equipped we'll be to address a wide range of challenges from developing new treatments for diseases to engineering novel materials. It's an exciting time to be studying biology, and the cell membrane is at the forefront of many groundbreaking discoveries. I can't wait to learn more. Well, there you have it. A journey through the remarkable world of the cell membrane. Huge thanks to our expert for being such a fantastic guide. I feel like I've gone from feeling totally overwhelmed to actually appreciating the complexity and elegance of these tiny structures. It's been my pleasure. And remember, there's always more to explore. The world of the cell is full of wonders just waiting to be discovered. Thanks for joining us on this deep dive into the fascinating world of cell membranes. We'll see you next time on the deep dive. |
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